From 51b248c9453562a663975c0cc11baa8b2c43ef30 Mon Sep 17 00:00:00 2001 From: Sandeep Dasgupta Date: Thu, 31 Jan 2019 14:18:37 -0600 Subject: [PATCH 01/15] Fixed the assembly names of some instructions which produces ambiguous disassembly. There are two variants like this: `VCVTPD2DQ xmm1, xmm2/m128` and `VCVTPD2DQ xmm1, ymm2/m256` In order to distinguish them the correct assembly mneumonic (prescribed by xed and objdump) are VCVTPD2DQX and VCVTPD2DQY resp. --- .../{vpinsrq_xmm_m64_imm8.k => pinsrq_xmm_m64_imm8.k} | 10 +++++----- .../{vcvtpd2dq_xmm_m256.k => vcvtpd2dqy_xmm_m256.k} | 8 ++++---- .../{vcvtpd2ps_xmm_m128.k => vcvtpd2psx_xmm_m128.k} | 10 +++++----- .../{vcvtpd2ps_xmm_m256.k => vcvtpd2psy_xmm_m256.k} | 6 +++--- .../{vcvttpd2dq_xmm_m128.k => vcvttpd2dqx_xmm_m128.k} | 10 +++++----- .../{vcvttpd2dq_xmm_m256.k => vcvttpd2dqy_xmm_m256.k} | 6 +++--- .../{vcvtdq2pd_ymm_ymm.k => vcvtdq2pd_ymm_xmm.k} | 4 ++-- semantics/x86-syntax.k | 8 +++++--- 8 files changed, 32 insertions(+), 30 deletions(-) rename semantics/memoryInstructions/{vpinsrq_xmm_m64_imm8.k => pinsrq_xmm_m64_imm8.k} (70%) rename semantics/memoryInstructions/{vcvtpd2dq_xmm_m256.k => vcvtpd2dqy_xmm_m256.k} (69%) rename semantics/memoryInstructions/{vcvtpd2ps_xmm_m128.k => vcvtpd2psx_xmm_m128.k} (62%) rename semantics/memoryInstructions/{vcvtpd2ps_xmm_m256.k => vcvtpd2psy_xmm_m256.k} (74%) rename semantics/memoryInstructions/{vcvttpd2dq_xmm_m128.k => vcvttpd2dqx_xmm_m128.k} (62%) rename semantics/memoryInstructions/{vcvttpd2dq_xmm_m256.k => vcvttpd2dqy_xmm_m256.k} (75%) rename semantics/registerInstructions/{vcvtdq2pd_ymm_ymm.k => vcvtdq2pd_ymm_xmm.k} (88%) diff --git a/semantics/memoryInstructions/vpinsrq_xmm_m64_imm8.k b/semantics/memoryInstructions/pinsrq_xmm_m64_imm8.k similarity index 70% rename from semantics/memoryInstructions/vpinsrq_xmm_m64_imm8.k rename to semantics/memoryInstructions/pinsrq_xmm_m64_imm8.k index fa6241dd1..edfe63203 100644 --- a/semantics/memoryInstructions/vpinsrq_xmm_m64_imm8.k +++ b/semantics/memoryInstructions/pinsrq_xmm_m64_imm8.k @@ -1,20 +1,20 @@ // Autogenerated using stratification. requires "x86-configuration.k" -module VPINSRQ-XMM-M64-IMM8 +module PINSRQ-XMM-M64-IMM8 imports X86-CONFIGURATION - context execinstr(vpinsrq:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(pinsrq:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpinsrq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (pinsrq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 64) ~> - execinstr (vpinsrq Imm8, memOffset( MemOff), R3:Xmm, .Operands) + execinstr (pinsrq Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (vpinsrq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (pinsrq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... diff --git a/semantics/memoryInstructions/vcvtpd2dq_xmm_m256.k b/semantics/memoryInstructions/vcvtpd2dqy_xmm_m256.k similarity index 69% rename from semantics/memoryInstructions/vcvtpd2dq_xmm_m256.k rename to semantics/memoryInstructions/vcvtpd2dqy_xmm_m256.k index fd4d76fab..0ce3461ab 100644 --- a/semantics/memoryInstructions/vcvtpd2dq_xmm_m256.k +++ b/semantics/memoryInstructions/vcvtpd2dqy_xmm_m256.k @@ -4,17 +4,17 @@ requires "x86-configuration.k" module VCVTPD2DQ-XMM-M256 imports X86-CONFIGURATION - context execinstr(vcvtpd2dq:Opcode HOLE:Mem, R2:Xmm, .Operands) [result(MemOffset)] + context execinstr(vcvtpd2dqy:Opcode HOLE:Mem, R2:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vcvtpd2dq:Opcode memOffset( MemOff:MInt):MemOffset, R2:Xmm, .Operands) => + execinstr (vcvtpd2dqy:Opcode memOffset( MemOff:MInt):MemOffset, R2:Xmm, .Operands) => loadFromMemory( MemOff, 256) ~> - execinstr (vcvtpd2dq memOffset( MemOff), R2:Xmm, .Operands) + execinstr (vcvtpd2dqy memOffset( MemOff), R2:Xmm, .Operands) ... RSMap:Map rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vcvtpd2dq:Opcode memOffset( MemOff:MInt):MemOffset, R2:Xmm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vcvtpd2dqy:Opcode memOffset( MemOff:MInt):MemOffset, R2:Xmm, .Operands) => . ... diff --git a/semantics/memoryInstructions/vcvtpd2ps_xmm_m128.k b/semantics/memoryInstructions/vcvtpd2psx_xmm_m128.k similarity index 62% rename from semantics/memoryInstructions/vcvtpd2ps_xmm_m128.k rename to semantics/memoryInstructions/vcvtpd2psx_xmm_m128.k index a9acbbfe6..ec7077ca7 100644 --- a/semantics/memoryInstructions/vcvtpd2ps_xmm_m128.k +++ b/semantics/memoryInstructions/vcvtpd2psx_xmm_m128.k @@ -1,20 +1,20 @@ // Autogenerated using stratification. requires "x86-configuration.k" -module VCVTPD2PS-XMM-M128 +module VCVTPD2PSX-XMM-M128 imports X86-CONFIGURATION - context execinstr(vcvtpd2ps:Opcode HOLE:Mem, R2:Xmm, .Operands) [result(MemOffset)] + context execinstr(vcvtpd2psx:Opcode HOLE:Mem, R2:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vcvtpd2ps:Opcode memOffset( MemOff:MInt):MemOffset, R2:Xmm, .Operands) => + execinstr (vcvtpd2psx:Opcode memOffset( MemOff:MInt):MemOffset, R2:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> - execinstr (vcvtpd2ps memOffset( MemOff), R2:Xmm, .Operands) + execinstr (vcvtpd2psx memOffset( MemOff), R2:Xmm, .Operands) ... RSMap:Map rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vcvtpd2ps:Opcode memOffset( MemOff:MInt):MemOffset, R2:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vcvtpd2psx:Opcode memOffset( MemOff:MInt):MemOffset, R2:Xmm, .Operands) => . ... diff --git a/semantics/memoryInstructions/vcvtpd2ps_xmm_m256.k b/semantics/memoryInstructions/vcvtpd2psy_xmm_m256.k similarity index 74% rename from semantics/memoryInstructions/vcvtpd2ps_xmm_m256.k rename to semantics/memoryInstructions/vcvtpd2psy_xmm_m256.k index 38fa524ef..e2af0b829 100644 --- a/semantics/memoryInstructions/vcvtpd2ps_xmm_m256.k +++ b/semantics/memoryInstructions/vcvtpd2psy_xmm_m256.k @@ -1,13 +1,13 @@ // Autogenerated using stratification. requires "x86-configuration.k" -module VCVTPD2PS-XMM-M256 +module VCVTPD2PSY-XMM-M256 imports X86-CONFIGURATION - context execinstr(vcvtpd2ps:Opcode HOLE:Mem, R2:Xmm, .Operands) [result(MemOffset)] + context execinstr(vcvtpd2psy:Opcode HOLE:Mem, R2:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vcvtpd2ps:Opcode memOffset( MemOff:MInt):MemOffset, R2:Xmm, .Operands) => + execinstr (vcvtpd2psy:Opcode memOffset( MemOff:MInt):MemOffset, R2:Xmm, .Operands) => . ... diff --git a/semantics/memoryInstructions/vcvttpd2dq_xmm_m128.k b/semantics/memoryInstructions/vcvttpd2dqx_xmm_m128.k similarity index 62% rename from semantics/memoryInstructions/vcvttpd2dq_xmm_m128.k rename to semantics/memoryInstructions/vcvttpd2dqx_xmm_m128.k index 8ed96b62f..9f2627314 100644 --- a/semantics/memoryInstructions/vcvttpd2dq_xmm_m128.k +++ b/semantics/memoryInstructions/vcvttpd2dqx_xmm_m128.k @@ -1,20 +1,20 @@ // Autogenerated using stratification. requires "x86-configuration.k" -module VCVTTPD2DQ-XMM-M128 +module VCVTTPD2DQX-XMM-M128 imports X86-CONFIGURATION - context execinstr(vcvttpd2dq:Opcode HOLE:Mem, R2:Xmm, .Operands) [result(MemOffset)] + context execinstr(vcvttpd2dqx:Opcode HOLE:Mem, R2:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vcvttpd2dq:Opcode memOffset( MemOff:MInt):MemOffset, R2:Xmm, .Operands) => + execinstr (vcvttpd2dqx:Opcode memOffset( MemOff:MInt):MemOffset, R2:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> - execinstr (vcvttpd2dq memOffset( MemOff), R2:Xmm, .Operands) + execinstr (vcvttpd2dqx memOffset( MemOff), R2:Xmm, .Operands) ... RSMap:Map rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vcvttpd2dq:Opcode memOffset( MemOff:MInt):MemOffset, R2:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vcvttpd2dqx:Opcode memOffset( MemOff:MInt):MemOffset, R2:Xmm, .Operands) => . ... diff --git a/semantics/memoryInstructions/vcvttpd2dq_xmm_m256.k b/semantics/memoryInstructions/vcvttpd2dqy_xmm_m256.k similarity index 75% rename from semantics/memoryInstructions/vcvttpd2dq_xmm_m256.k rename to semantics/memoryInstructions/vcvttpd2dqy_xmm_m256.k index 8e49459bc..e72bc31e4 100644 --- a/semantics/memoryInstructions/vcvttpd2dq_xmm_m256.k +++ b/semantics/memoryInstructions/vcvttpd2dqy_xmm_m256.k @@ -1,13 +1,13 @@ // Autogenerated using stratification. requires "x86-configuration.k" -module VCVTTPD2DQ-XMM-M256 +module VCVTTPD2DQY-XMM-M256 imports X86-CONFIGURATION - context execinstr(vcvttpd2dq:Opcode HOLE:Mem, R2:Xmm, .Operands) [result(MemOffset)] + context execinstr(vcvttpd2dqy:Opcode HOLE:Mem, R2:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vcvttpd2dq:Opcode memOffset( MemOff:MInt):MemOffset, R2:Xmm, .Operands) => + execinstr (vcvttpd2dqy:Opcode memOffset( MemOff:MInt):MemOffset, R2:Xmm, .Operands) => . ... diff --git a/semantics/registerInstructions/vcvtdq2pd_ymm_ymm.k b/semantics/registerInstructions/vcvtdq2pd_ymm_xmm.k similarity index 88% rename from semantics/registerInstructions/vcvtdq2pd_ymm_ymm.k rename to semantics/registerInstructions/vcvtdq2pd_ymm_xmm.k index de22e58da..d9c30cc39 100644 --- a/semantics/registerInstructions/vcvtdq2pd_ymm_ymm.k +++ b/semantics/registerInstructions/vcvtdq2pd_ymm_xmm.k @@ -1,11 +1,11 @@ // Autogenerated using stratification. requires "x86-configuration.k" -module VCVTDQ2PD-YMM-YMM +module VCVTDQ2PD-YMM-XMM imports X86-CONFIGURATION rule - execinstr (vcvtdq2pd R1:Ymm, R2:Ymm, .Operands) => . + execinstr (vcvtdq2pd R1:Xmm, R2:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, diff --git a/semantics/x86-syntax.k b/semantics/x86-syntax.k index 15c1f2b96..875f7f5f8 100644 --- a/semantics/x86-syntax.k +++ b/semantics/x86-syntax.k @@ -913,9 +913,10 @@ module X86-SYNTAX | "vcomiss" | "vcvtdq2pd" | "vcvtdq2ps" - | "vcvtpd2dq" + | "vcvtpd2dqy" | "vcvtpd2dqx" - | "vcvtpd2ps" + | "vcvtpd2psx" + | "vcvtpd2psy" | "vcvtph2ps" | "vcvtps2dq" | "vcvtps2pd" @@ -929,7 +930,8 @@ module X86-SYNTAX | "vcvtsi2ss" | "vcvtss2sd" | "vcvtss2si" - | "vcvttpd2dq" + | "vcvttpd2dqx" + | "vcvttpd2dqy" | "vcvttps2dq" | "vcvttsd2si" | "vcvttss2si" From 7532c1d8214a922dcf17bdf0fd6ca312a1e5ca49 Mon Sep 17 00:00:00 2001 From: andrew_miranti Date: Sat, 2 Feb 2019 23:38:35 -0600 Subject: [PATCH 02/15] Fix some missing opcodes --- semantics/x86-syntax.k | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/semantics/x86-syntax.k b/semantics/x86-syntax.k index 875f7f5f8..f0dc3f547 100644 --- a/semantics/x86-syntax.k +++ b/semantics/x86-syntax.k @@ -698,6 +698,7 @@ module X86-SYNTAX | "phsubw" | "pinsrb" | "pinsrd" + | "pinsrq" | "pinsrw" | "pmaddubsw" | "pmaddwd" @@ -913,8 +914,10 @@ module X86-SYNTAX | "vcomiss" | "vcvtdq2pd" | "vcvtdq2ps" - | "vcvtpd2dqy" + | "vcvtpd2dq" | "vcvtpd2dqx" + | "vcvtpd2dqy" + | "vcvtpd2ps" | "vcvtpd2psx" | "vcvtpd2psy" | "vcvtph2ps" @@ -930,6 +933,7 @@ module X86-SYNTAX | "vcvtsi2ss" | "vcvtss2sd" | "vcvtss2si" + | "vcvttpd2dq" | "vcvttpd2dqx" | "vcvttpd2dqy" | "vcvttps2dq" From 956e1dfd9e547f921d99bf00c2375d2ac2a61f5f Mon Sep 17 00:00:00 2001 From: andrew_miranti Date: Mon, 4 Feb 2019 12:15:11 -0600 Subject: [PATCH 03/15] Make opcodes tokens --- semantics/x86-syntax.k | 2370 ++++++++++++++++++++-------------------- 1 file changed, 1185 insertions(+), 1185 deletions(-) diff --git a/semantics/x86-syntax.k b/semantics/x86-syntax.k index f0dc3f547..8540377f9 100644 --- a/semantics/x86-syntax.k +++ b/semantics/x86-syntax.k @@ -83,7 +83,7 @@ module X86-SYNTAX | "stdout" [token] syntax AssemblerDirective ::= ".section" ".rodata" - | ".data" + | ".data" [token] | ".text" | ".bss" | ".file" String @@ -205,1196 +205,1196 @@ module X86-SYNTAX // | Sreg ":" Offset "(" R32 "," R32 ")" // | Sreg ":" Offset "(" R64 "," R64 ")" - syntax Rip ::= "%rip" + syntax Rip ::= "%rip" [token] syntax Scale ::= Int - syntax Rh ::= "%ah" - | "%bh" - | "%ch" - | "%dh" - syntax R8 ::= "%al" - | "%bl" - | "%cl" - | "%dl" - | "%sil" - | "%dil" - | "%spl" - | "%bpl" - | "%r8b" - | "%r9b" - | "%r10b" - | "%r11b" - | "%r12b" - | "%r13b" - | "%r14b" - | "%r15b" - syntax R16 ::= "%ax" - | "%bx" - | "%cx" - | "%dx" - | "%si" - | "%di" - | "%sp" - | "%bp" - | "%r8w" - | "%r9w" - | "%r10w" - | "%r11w" - | "%r12w" - | "%r13w" - | "%r14w" - | "%r15w" - syntax R32 ::= "%eax" - | "%ebx" - | "%ecx" - | "%edx" - | "%esi" - | "%edi" - | "%esp" - | "%ebp" - | "%r8d" - | "%r9d" - | "%r10d" - | "%r11d" - | "%r12d" - | "%r13d" - | "%r14d" - | "%r15d" - syntax R64 ::= "%rax" - | "%rbx" - | "%rcx" - | "%rdx" - | "%rsi" - | "%rdi" - | "%rsp" - | "%rbp" - | "%r8" - | "%r9" - | "%r10" - | "%r11" - | "%r12" - | "%r13" - | "%r14" - | "%r15" + syntax Rh ::= "%ah" [token] + | "%bh" [token] + | "%ch" [token] + | "%dh" [token] + syntax R8 ::= "%al" [token] + | "%bl" [token] + | "%cl" [token] + | "%dl" [token] + | "%sil" [token] + | "%dil" [token] + | "%spl" [token] + | "%bpl" [token] + | "%r8b" [token] + | "%r9b" [token] + | "%r10b" [token] + | "%r11b" [token] + | "%r12b" [token] + | "%r13b" [token] + | "%r14b" [token] + | "%r15b" [token] + syntax R16 ::= "%ax" [token] + | "%bx" [token] + | "%cx" [token] + | "%dx" [token] + | "%si" [token] + | "%di" [token] + | "%sp" [token] + | "%bp" [token] + | "%r8w" [token] + | "%r9w" [token] + | "%r10w" [token] + | "%r11w" [token] + | "%r12w" [token] + | "%r13w" [token] + | "%r14w" [token] + | "%r15w" [token] + syntax R32 ::= "%eax" [token] + | "%ebx" [token] + | "%ecx" [token] + | "%edx" [token] + | "%esi" [token] + | "%edi" [token] + | "%esp" [token] + | "%ebp" [token] + | "%r8d" [token] + | "%r9d" [token] + | "%r10d" [token] + | "%r11d" [token] + | "%r12d" [token] + | "%r13d" [token] + | "%r14d" [token] + | "%r15d" [token] + syntax R64 ::= "%rax" [token] + | "%rbx" [token] + | "%rcx" [token] + | "%rdx" [token] + | "%rsi" [token] + | "%rdi" [token] + | "%rsp" [token] + | "%rbp" [token] + | "%r8" [token] + | "%r9" [token] + | "%r10" [token] + | "%r11" [token] + | "%r12" [token] + | "%r13" [token] + | "%r14" [token] + | "%r15" [token] - syntax Sreg ::= "%es" - | "%cs" - | "%ss" - | "%ds" - | "%fs" - | "%gs" + syntax Sreg ::= "%es" [token] + | "%cs" [token] + | "%ss" [token] + | "%ds" [token] + | "%fs" [token] + | "%gs" [token] - syntax St ::= "%st" - | "%st(0)" - | "%st(1)" - | "%st(2)" - | "%st(3)" - | "%st(4)" - | "%st(5)" - | "%st(6)" - | "%st(7)" + syntax St ::= "%st" [token] + | "%st(0)" [token] + | "%st(1)" [token] + | "%st(2)" [token] + | "%st(3)" [token] + | "%st(4)" [token] + | "%st(5)" [token] + | "%st(6)" [token] + | "%st(7)" [token] - syntax Xmm ::= "%xmm0" - | "%xmm1" - | "%xmm2" - | "%xmm3" - | "%xmm4" - | "%xmm5" - | "%xmm6" - | "%xmm7" - | "%xmm8" - | "%xmm9" - | "%xmm10" - | "%xmm11" - | "%xmm12" - | "%xmm13" - | "%xmm14" - | "%xmm15" + syntax Xmm ::= "%xmm0" [token] + | "%xmm1" [token] + | "%xmm2" [token] + | "%xmm3" [token] + | "%xmm4" [token] + | "%xmm5" [token] + | "%xmm6" [token] + | "%xmm7" [token] + | "%xmm8" [token] + | "%xmm9" [token] + | "%xmm10" [token] + | "%xmm11" [token] + | "%xmm12" [token] + | "%xmm13" [token] + | "%xmm14" [token] + | "%xmm15" [token] - syntax Mm ::= "%mmx0" - | "%mmx1" - | "%mmx2" - | "%mmx3" - | "%mmx4" - | "%mmx5" - | "%mmx6" - | "%mmx7" + syntax Mm ::= "%mmx0" [token] + | "%mmx1" [token] + | "%mmx2" [token] + | "%mmx3" [token] + | "%mmx4" [token] + | "%mmx5" [token] + | "%mmx6" [token] + | "%mmx7" [token] - syntax Ymm ::= "%ymm0" - | "%ymm1" - | "%ymm2" - | "%ymm3" - | "%ymm4" - | "%ymm5" - | "%ymm6" - | "%ymm7" - | "%ymm8" - | "%ymm9" - | "%ymm10" - | "%ymm11" - | "%ymm12" - | "%ymm13" - | "%ymm14" - | "%ymm15" + syntax Ymm ::= "%ymm0" [token] + | "%ymm1" [token] + | "%ymm2" [token] + | "%ymm3" [token] + | "%ymm4" [token] + | "%ymm5" [token] + | "%ymm6" [token] + | "%ymm7" [token] + | "%ymm8" [token] + | "%ymm9" [token] + | "%ymm10" [token] + | "%ymm11" [token] + | "%ymm12" [token] + | "%ymm13" [token] + | "%ymm14" [token] + | "%ymm15" [token] - syntax Opcode ::= "adcb" - | "adcl" - | "adcq" - | "adcw" - | "addb" - | "addl" - | "addpd" - | "addps" - | "addq" - | "addsd" - | "addss" - | "addsubpd" - | "addsubps" - | "addw" - | "andb" - | "andl" - | "andnl" - | "andnpd" - | "andnps" - | "andnq" - | "andpd" - | "andps" - | "andq" - | "andw" - | "bextrl" - | "bextrq" - | "blendpd" - | "blendps" - | "blendvpd" - | "blendvps" - | "blsil" - | "blsiq" - | "blsmskl" - | "blsmskq" - | "blsrl" - | "blsrq" - | "bswap" - | "btcl" - | "btcq" - | "btcw" - | "btl" - | "btq" - | "btrl" - | "btrq" - | "btrw" - | "btsl" - | "btsq" - | "btsw" - | "btw" - | "bzhil" - | "bzhiq" - | "cbtw" - | "clc" - | "cltd" - | "cltq" - | "cmc" - | "cmovael" - | "cmovaeq" - | "cmovaew" - | "cmoval" - | "cmovaq" - | "cmovaw" - | "cmovbel" - | "cmovbeq" - | "cmovbew" - | "cmovbe" - | "cmovbl" - | "cmovbq" - | "cmovbw" - | "cmovcl" - | "cmovcq" - | "cmovcw" - | "cmovc" - | "cmovel" - | "cmoveq" - | "cmovew" - | "cmovgel" - | "cmovgeq" - | "cmovgew" - | "cmovge" - | "cmovgl" - | "cmovgq" - | "cmovgw" - | "cmovlel" - | "cmovleq" - | "cmovlew" - | "cmovll" - | "cmovlq" - | "cmovlw" - | "cmovnael" - | "cmovnaeq" - | "cmovnaew" - | "cmovnal" - | "cmovnaq" - | "cmovnaw" - | "cmovnbel" - | "cmovnbeq" - | "cmovnbew" - | "cmovnbl" - | "cmovnbq" - | "cmovnbw" - | "cmovncl" - | "cmovncq" - | "cmovncw" - | "cmovnel" - | "cmovne" - | "cmovneq" - | "cmovnew" - | "cmovngel" - | "cmovngeq" - | "cmovngew" - | "cmovngl" - | "cmovngq" - | "cmovngw" - | "cmovnlel" - | "cmovnleq" - | "cmovnlew" - | "cmovnll" - | "cmovnlq" - | "cmovnlw" - | "cmovnol" - | "cmovnoq" - | "cmovnow" - | "cmovnpl" - | "cmovnpq" - | "cmovnpw" - | "cmovnsl" - | "cmovnsq" - | "cmovnsw" - | "cmovnzl" - | "cmovnzq" - | "cmovnzw" - | "cmovol" - | "cmovoq" - | "cmovow" - | "cmovpel" - | "cmovpeq" - | "cmovpew" - | "cmovpl" - | "cmovpol" - | "cmovpoq" - | "cmovpow" - | "cmovpq" - | "cmovpw" - | "cmovsl" - | "cmovsq" - | "cmovsw" - | "cmovzl" - | "cmovzq" - | "cmovzw" - | "cmpb" - | "cmpl" - | "cmppd" - | "cmpps" - | "cmpq" - | "cmpsd" - | "cmpss" - | "cmpw" - | "cmpxchg16b" - | "cmpxchg8b" - | "cmpxchgb" - | "cmpxchgl" - | "cmpxchgq" - | "cmpxchgw" - | "comisd" - | "comiss" - | "cqto" - | "cvtdq2pd" - | "cvtdq2ps" - | "cvtpd2dq" - | "cvtpd2ps" - | "cvtpi2pd" - | "cvtpi2ps" - | "cvtps2dq" - | "cvtps2pd" - | "cvtsd2si" - | "cvtsd2ss" - | "cvtsi2sdl" - | "cvtsi2sdq" - | "cvtsi2ssl" - | "cvtsi2ssq" - | "cvtss2sd" - | "cvtss2si" - | "cvttpd2dq" - | "cvttps2dq" - | "cvttsd2si" - | "cvttss2si" - | "cwtd" - | "cwtl" - | "decb" - | "decl" - | "decq" - | "decw" - | "divb" - | "divl" - | "divpd" - | "divps" - | "divq" - | "divsd" - | "divss" - | "divw" - | "dppd" - | "dpps" - | "extractps" - | "haddpd" - | "haddps" - | "hsubpd" - | "hsubps" - | "idivb" - | "idivl" - | "idivq" - | "idivw" - | "imulb" - | "imull" - | "imulq" - | "imulw" - | "incb" - | "incl" - | "incq" - | "incw" - | "insertps" - | "lddqu" - | "leal" - | "leaq" - | "leaw" - | "lzcntl" - | "lzcntq" - | "lzcntw" - | "maxpd" - | "maxps" - | "maxsd" - | "maxss" - | "minpd" - | "minps" - | "minsd" - | "minss" - | "movapd" - | "movaps" - | "movb" - | "movbel" - | "movbeq" - | "movbew" - | "movbe" - | "movd" - | "movddup" - | "movdqa" - | "movdqu" - | "movhlps" - | "movhpd" - | "movhps" - | "movl" - | "movlhps" - | "movlpd" - | "movlps" - | "movmskpd" - | "movmskps" - | "movntdq" - | "movntdqa" - | "movnti" - | "movntpd" - | "movntps" - | "movq" - | "movsbl" - | "movsbq" - | "movsbw" - | "movsd" - | "movshdup" - | "movsldup" - | "movslq" - | "movss" - | "movswl" - | "movswq" - | "movupd" - | "movups" - | "movw" - | "movzbl" - | "movzbq" - | "movzbw" - | "movzwl" - | "movzwq" - | "mpsadbw" - | "mulb" - | "mull" - | "mulpd" - | "mulps" - | "mulq" - | "mulsd" - | "mulss" - | "mulw" - | "mulxl" - | "mulxq" - | "mulx" - | "negb" - | "negl" - | "negq" - | "negw" - | "nop" - | "nopl" - | "nopw" - | "notb" - | "notl" - | "notq" - | "notw" - | "orb" - | "orl" - | "orpd" - | "orps" - | "orq" - | "orw" - | "pabsb" - | "pabsd" - | "pabsw" - | "packssdw" - | "packsswb" - | "packusdw" - | "packuswb" - | "paddb" - | "paddd" - | "paddq" - | "paddsb" - | "paddsw" - | "paddusb" - | "paddusw" - | "paddw" - | "palignr" - | "pand" - | "pandn" - | "pavgb" - | "pavgw" - | "pblendvb" - | "pblendw" - | "pclmulqdq" - | "pcmpeqb" - | "pcmpeqd" - | "pcmpeqq" - | "pcmpeqw" - | "pcmpestri" - | "pcmpestrm" - | "pcmpgtb" - | "pcmpgtd" - | "pcmpgtq" - | "pcmpgtw" - | "pcmpistri" - | "pcmpistrm" - | "pdepl" - | "pdepq" - | "pextl" - | "pextq" - | "pextrb" - | "pextrd" - | "pextrq" - | "pextrw" - | "phaddd" - | "phaddsw" - | "phaddw" - | "phminposuw" - | "phsubd" - | "phsubsw" - | "phsubw" - | "pinsrb" - | "pinsrd" - | "pinsrq" - | "pinsrw" - | "pmaddubsw" - | "pmaddwd" - | "pmaxsb" - | "pmaxsd" - | "pmaxsw" - | "pmaxub" - | "pmaxud" - | "pmaxuw" - | "pminsb" - | "pminsd" - | "pminsw" - | "pminub" - | "pminud" - | "pminuw" - | "pmovmskb" - | "pmovsxbd" - | "pmovsxbq" - | "pmovsxbw" - | "pmovsxdq" - | "pmovsxwd" - | "pmovsxwq" - | "pmovzxbd" - | "pmovzxbq" - | "pmovzxbw" - | "pmovzxdq" - | "pmovzxwd" - | "pmovzxwq" - | "pmuldq" - | "pmulhrsw" - | "pmulhuw" - | "pmulhw" - | "pmulld" - | "pmullw" - | "pmuludq" - | "popcntl" - | "popcntq" - | "popcntw" - | "popq" - | "popw" - | "por" - | "psadbw" - | "pshufb" - | "pshufd" - | "pshufhw" - | "pshuflw" - | "psignb" - | "psignd" - | "psignw" - | "pslld" - | "pslldq" - | "psllq" - | "psllw" - | "psrad" - | "psraw" - | "psrld" - | "psrldq" - | "psrlq" - | "psrlw" - | "psubb" - | "psubd" - | "psubq" - | "psubsb" - | "psubsw" - | "psubusb" - | "psubusw" - | "psubw" - | "ptest" - | "punpckhbw" - | "punpckhdq" - | "punpckhqdq" - | "punpckhwd" - | "punpcklbw" - | "punpckldq" - | "punpcklqdq" - | "punpcklwd" - | "pushq" - | "pushw" - | "pxor" - | "rclb" - | "rcll" - | "rclq" - | "rclw" - | "rcpps" - | "rcpss" - | "rcrb" - | "rcrl" - | "rcrq" - | "rcrw" - | "rolb" - | "roll" - | "rolq" - | "rolw" - | "rorb" - | "rorl" - | "rorq" - | "rorw" - | "rorxl" - | "rorxq" - | "rorx" - | "roundpd" - | "roundps" - | "roundsd" - | "roundss" - | "rsqrtps" - | "rsqrtss" - | "salb" - | "sall" - | "salq" - | "salw" - | "sarb" - | "sarl" - | "sarq" - | "sarw" - | "sarxl" - | "sarxq" - | "sbbb" - | "sbbl" - | "sbbq" - | "sbbw" - | "seta" - | "setae" - | "setb" - | "setbe" - | "setc" - | "sete" - | "setg" - | "setge" - | "setl" - | "setle" - | "setna" - | "setnae" - | "setnb" - | "setnbe" - | "setnc" - | "setne" - | "setng" - | "setnge" - | "setnl" - | "setnle" - | "setno" - | "setnp" - | "setns" - | "setnz" - | "seto" - | "setp" - | "setpe" - | "setpo" - | "sets" - | "setz" - | "shlb" - | "shll" - | "shlq" - | "shlw" - | "shlxl" - | "shlxq" - | "shrb" - | "shrl" - | "shrq" - | "shrw" - | "shrxl" - | "shrxq" - | "shufpd" - | "shufps" - | "sqrtpd" - | "sqrtps" - | "sqrtsd" - | "sqrtss" - | "stc" - | "subb" - | "subl" - | "subpd" - | "subps" - | "subq" - | "subsd" - | "subss" - | "subw" - | "testb" - | "testl" - | "testq" - | "testw" - | "tzcntl" - | "tzcntq" - | "tzcntw" - | "ucomisd" - | "ucomiss" - | "unpckhpd" - | "unpckhps" - | "unpcklpd" - | "unpcklps" - | "vaddpd" - | "vaddps" - | "vaddsd" - | "vaddss" - | "vaddsubpd" - | "vaddsubps" - | "vandnpd" - | "vandnps" - | "vandpd" - | "vandps" - | "vblendpd" - | "vblendps" - | "vblendvpd" - | "vblendvps" - | "vbroadcastf128" - | "vbroadcastsd" - | "vbroadcastss" - | "vcmppd" - | "vcmpps" - | "vcmpsd" - | "vcmpss" - | "vcomisd" - | "vcomiss" - | "vcvtdq2pd" - | "vcvtdq2ps" - | "vcvtpd2dq" - | "vcvtpd2dqx" - | "vcvtpd2dqy" - | "vcvtpd2ps" - | "vcvtpd2psx" - | "vcvtpd2psy" - | "vcvtph2ps" - | "vcvtps2dq" - | "vcvtps2pd" - | "vcvtps2ph" - | "vcvtsd2si" - | "vcvtsd2ss" - | "vcvtsi2sdl" - | "vcvtsi2sdq" - | "vcvtsi2ssl" - | "vcvtsi2ssq" - | "vcvtsi2ss" - | "vcvtss2sd" - | "vcvtss2si" - | "vcvttpd2dq" - | "vcvttpd2dqx" - | "vcvttpd2dqy" - | "vcvttps2dq" - | "vcvttsd2si" - | "vcvttss2si" - | "vdivpd" - | "vdivps" - | "vdivsd" - | "vdivss" - | "vdppd" - | "vdpps" - | "vextractf128" - | "vextracti128" - | "vextractps" - | "vfmadd132pd" - | "vfmadd132ps" - | "vfmadd132sd" - | "vfmadd132ss" - | "vfmadd213pd" - | "vfmadd213ps" - | "vfmadd213sd" - | "vfmadd213ss" - | "vfmadd231pd" - | "vfmadd231ps" - | "vfmadd231sd" - | "vfmadd231ss" - | "vfmaddsub132pd" - | "vfmaddsub132ps" - | "vfmaddsub213pd" - | "vfmaddsub213ps" - | "vfmaddsub231pd" - | "vfmaddsub231ps" - | "vfmsub132pd" - | "vfmsub132ps" - | "vfmsub132sd" - | "vfmsub132ss" - | "vfmsub213pd" - | "vfmsub213ps" - | "vfmsub213sd" - | "vfmsub213ss" - | "vfmsub231pd" - | "vfmsub231ps" - | "vfmsub231sd" - | "vfmsub231ss" - | "vfmsubadd132pd" - | "vfmsubadd132ps" - | "vfmsubadd213pd" - | "vfmsubadd213ps" - | "vfmsubadd231pd" - | "vfmsubadd231ps" - | "vfnmadd132pd" - | "vfnmadd132ps" - | "vfnmadd132sd" - | "vfnmadd132ss" - | "vfnmadd213pd" - | "vfnmadd213ps" - | "vfnmadd213sd" - | "vfnmadd213ss" - | "vfnmadd231pd" - | "vfnmadd231ps" - | "vfnmadd231sd" - | "vfnmadd231ss" - | "vfnmsub132pd" - | "vfnmsub132ps" - | "vfnmsub132sd" - | "vfnmsub132ss" - | "vfnmsub213pd" - | "vfnmsub213ps" - | "vfnmsub213sd" - | "vfnmsub213ss" - | "vfnmsub231pd" - | "vfnmsub231ps" - | "vfnmsub231sd" - | "vfnmsub231ss" - | "vhaddpd" - | "vhaddps" - | "vhsubpd" - | "vhsubps" - | "vinsertf128" - | "vinserti128" - | "vinsertps" - | "vlddqu" - | "vmaskmovpd" - | "vmaskmovps" - | "vmaxpd" - | "vmaxps" - | "vmaxsd" - | "vmaxss" - | "vminpd" - | "vminps" - | "vminsd" - | "vminss" - | "vmovapd" - | "vmovaps" - | "vmovd" - | "vmovddup" - | "vmovdqa" - | "vmovdqu" - | "vmovhlps" - | "vmovhpd" - | "vmovhps" - | "vmovlhps" - | "vmovlpd" - | "vmovlps" - | "vmovmskpd" - | "vmovmskps" - | "vmovntdqa" - | "vmovntdq" - | "vmovntpd" - | "vmovntps" - | "vmovq" - | "vmovsd" - | "vmovshdup" - | "vmovsldup" - | "vmovss" - | "vmovupd" - | "vmovups" - | "vmpsadbw" - | "vmulpd" - | "vmulps" - | "vmulsd" - | "vmulss" - | "vorpd" - | "vorps" - | "vpabsb" - | "vpabsd" - | "vpabsw" - | "vpackssdw" - | "vpacksswb" - | "vpackusdw" - | "vpackuswb" - | "vpaddb" - | "vpaddd" - | "vpaddq" - | "vpaddsb" - | "vpaddsw" - | "vpaddusb" - | "vpaddusw" - | "vpaddw" - | "vpalignr" - | "vpand" - | "vpandn" - | "vpavgb" - | "vpavgw" - | "vpblendd" - | "vpblendvb" - | "vpblendw" - | "vpbroadcastb" - | "vpbroadcastd" - | "vbroadcasti128" - | "vpbroadcastq" - | "vpbroadcastw" - | "vpclmulqdq" - | "vpcmpeqb" - | "vpcmpeqd" - | "vpcmpeqq" - | "vpcmpeqw" - | "vpcmpestri" - | "vpcmpestrm" - | "vpcmpgtb" - | "vpcmpgtd" - | "vpcmpgtq" - | "vpcmpgtw" - | "vpcmpistri" - | "vpcmpistrm" - | "vperm2f128" - | "vperm2i128" - | "vpermd" - | "vpermilpd" - | "vpermilps" - | "vpermpd" - | "vpermps" - | "vpermq" - | "vpextrb" - | "vpextrd" - | "vpextrq" - | "vpextrw" - | "vphaddd" - | "vphaddsw" - | "vphaddw" - | "vphminposuw" - | "vphsubd" - | "vphsubsw" - | "vphsubw" - | "vpinsrb" - | "vpinsrd" - | "vpinsrq" - | "vpinsrw" - | "vpmaddubsw" - | "vpmaddwd" - | "vpmaskmovd" - | "vpmaskmovq" - | "vpmaxsb" - | "vpmaxsd" - | "vpmaxsw" - | "vpmaxub" - | "vpmaxud" - | "vpmaxuw" - | "vpminsb" - | "vpminsd" - | "vpminsw" - | "vpminub" - | "vpminud" - | "vpminuw" - | "vpmovmskb" - | "vpmovsxbd" - | "vpmovsxbq" - | "vpmovsxbw" - | "vpmovsxdq" - | "vpmovsxwd" - | "vpmovsxwq" - | "vpmovzxbd" - | "vpmovzxbq" - | "vpmovzxbw" - | "vpmovzxdq" - | "vpmovzxwd" - | "vpmovzxwq" - | "vpmuldq" - | "vpmulhrsw" - | "vpmulhuw" - | "vpmulhw" - | "vpmulld" - | "vpmullw" - | "vpmuludq" - | "vpor" - | "vpsadbw" - | "vpshufb" - | "vpshufd" - | "vpshufhw" - | "vpshuflw" - | "vpsignb" - | "vpsignd" - | "vpsignw" - | "vpslld" - | "vpslldq" - | "vpsllq" - | "vpsllvd" - | "vpsllvq" - | "vpsllw" - | "vpsrad" - | "vpsravd" - | "vpsraw" - | "vpsrld" - | "vpsrldq" - | "vpsrlq" - | "vpsrlvd" - | "vpsrlvq" - | "vpsrlw" - | "vpsubb" - | "vpsubd" - | "vpsubq" - | "vpsubsb" - | "vpsubsw" - | "vpsubusb" - | "vpsubusw" - | "vpsubw" - | "vptest" - | "vpunpckhbw" - | "vpunpckhdq" - | "vpunpckhqdq" - | "vpunpckhwd" - | "vpunpcklbw" - | "vpunpckldq" - | "vpunpcklqdq" - | "vpunpcklwd" - | "vpvmpgtq" - | "vpxor" - | "vrcpps" - | "vrcpss" - | "vroundpd" - | "vroundps" - | "vroundsd" - | "vroundss" - | "vrsqrtps" - | "vrsqrtss" - | "vshufpd" - | "vshufps" - | "vsqrtpd" - | "vsqrtps" - | "vsqrtsd" - | "vsqrtss" - | "vsubpd" - | "vsubps" - | "vsubsd" - | "vsubss" - | "vtestpd" - | "vtestps" - | "vucomisd" - | "vucomiss" - | "vunpckhpd" - | "vunpckhps" - | "vunpcklpd" - | "vunpcklps" - | "vxorpd" - | "vxorps" - | "vzeroall" - | "vzeroupper" - | "xaddb" - | "xaddl" - | "xaddq" - | "xaddw" - | "xchgb" - | "xchgl" - | "xchgq" - | "xchgw" - | "xorb" - | "xorl" - | "xorpd" - | "xorps" - | "xorq" - | "xorw" - | "call" - | "ret" - | "leave" - | "jmp" - | "je" - | "jne" - | "jns" - | "js" - | "jnc" - | "jb" - | "jae" - | "jnb" - | "jle" - | "jg" - | "jge" - | "jl" - | "jbe" - | "ja" - | "jp" - | "jc" - | "jecxz" - | "jna" - | "jnae" - | "jnbe" - | "jng" - | "jnge" - | "jnl" - | "jnle" - | "jno" - | "jnp" - | "jnz" - | "jo" - | "jpe" - | "jpo" - | "jrcxz" - | "jz" - | "movabsq" - | "vcvtsi2sd" - | "sarx" - | "shlx" - | "shrx" - | "cmovs" - | "cmovns" - | "cmovge" - | "cmove" - | "cmovle" - | "cmovbe" - | "ud2" - | "bsfl" - | "bsfq" - | "bsfw" - | "bsrw" - | "bsrl" - | "bsrq" - | "shldq" - | "shldl" - | "shldw" - | "shrdq" - | "shrdl" - | "shrdw" - | "pcmpestri" - | "pcmpestrm" - | "pcmpistri" - | "pcmpistrm" - | "loop" - | "loope" - | "loopne" - | "loopz" - | "loopnz" - | "scasb" - | "repz scasb" - | "repe scasb" - | "repnz scasb" - | "repne scasb" - | "scasw" - | "repz scasw" - | "repe scasw" - | "repnz scasw" - | "repne scasw" - | "scasl" - | "repz scasl" - | "repe scasl" - | "repnz scasl" - | "repne scasl" - | "scasq" - | "repz scasq" - | "repe scasq" - | "repnz scasq" - | "repne scasq" - | "std" - | "cld" - | "stosb" - | "rep stosb" - | "stosw" - | "rep stosw" - | "rep stosl" - | "stosl" - | "stosq" - | "rep stosq" - | "cmpsb" - | "repz cmpsb" - | "repe cmpsb" - | "repnz cmpsb" - | "repne cmpsb" - | "cmpsw" - | "repz cmpsw" - | "repe cmpsw" - | "repnz cmpsw" - | "repne cmpsw" - | "cmpsl" - | "repz cmpsl" - | "repe cmpsl" - | "repnz cmpsl" - | "repne cmpsl" - | "cmpsq" - | "repz cmpsq" - | "repe cmpsq" - | "repnz cmpsq" - | "repne cmpsq" - | "lodsb" - | "rep lodsb" - | "lodsw" - | "rep lodsw" - | "lodsl" - | "rep lodsl" - | "lodsq" - | "rep lodsq" - | "movsb" - | "rep movsb" - | "movsw" - | "rep movsw" - | "movsl" - | "rep movsl" - | "movsq" - | "rep movsq" - | "maskmovdqu" - | "vmaskmovdqu" - | "push" - | "pop" - | "mov" - | "sub" - | "dec" - | "cmp" - | "lea" - | "add" - | "inc" - | "nop" - | "retq" - | "callq" - | "jmpq" - | "leaveq" - | "pseudofloattestopcode1" + syntax Opcode ::= "adcb" [token] + | "adcl" [token] + | "adcq" [token] + | "adcw" [token] + | "addb" [token] + | "addl" [token] + | "addpd" [token] + | "addps" [token] + | "addq" [token] + | "addsd" [token] + | "addss" [token] + | "addsubpd" [token] + | "addsubps" [token] + | "addw" [token] + | "andb" [token] + | "andl" [token] + | "andnl" [token] + | "andnpd" [token] + | "andnps" [token] + | "andnq" [token] + | "andpd" [token] + | "andps" [token] + | "andq" [token] + | "andw" [token] + | "bextrl" [token] + | "bextrq" [token] + | "blendpd" [token] + | "blendps" [token] + | "blendvpd" [token] + | "blendvps" [token] + | "blsil" [token] + | "blsiq" [token] + | "blsmskl" [token] + | "blsmskq" [token] + | "blsrl" [token] + | "blsrq" [token] + | "bswap" [token] + | "btcl" [token] + | "btcq" [token] + | "btcw" [token] + | "btl" [token] + | "btq" [token] + | "btrl" [token] + | "btrq" [token] + | "btrw" [token] + | "btsl" [token] + | "btsq" [token] + | "btsw" [token] + | "btw" [token] + | "bzhil" [token] + | "bzhiq" [token] + | "cbtw" [token] + | "clc" [token] + | "cltd" [token] + | "cltq" [token] + | "cmc" [token] + | "cmovael" [token] + | "cmovaeq" [token] + | "cmovaew" [token] + | "cmoval" [token] + | "cmovaq" [token] + | "cmovaw" [token] + | "cmovbel" [token] + | "cmovbeq" [token] + | "cmovbew" [token] + | "cmovbe" [token] + | "cmovbl" [token] + | "cmovbq" [token] + | "cmovbw" [token] + | "cmovcl" [token] + | "cmovcq" [token] + | "cmovcw" [token] + | "cmovc" [token] + | "cmovel" [token] + | "cmoveq" [token] + | "cmovew" [token] + | "cmovgel" [token] + | "cmovgeq" [token] + | "cmovgew" [token] + | "cmovge" [token] + | "cmovgl" [token] + | "cmovgq" [token] + | "cmovgw" [token] + | "cmovlel" [token] + | "cmovleq" [token] + | "cmovlew" [token] + | "cmovll" [token] + | "cmovlq" [token] + | "cmovlw" [token] + | "cmovnael" [token] + | "cmovnaeq" [token] + | "cmovnaew" [token] + | "cmovnal" [token] + | "cmovnaq" [token] + | "cmovnaw" [token] + | "cmovnbel" [token] + | "cmovnbeq" [token] + | "cmovnbew" [token] + | "cmovnbl" [token] + | "cmovnbq" [token] + | "cmovnbw" [token] + | "cmovncl" [token] + | "cmovncq" [token] + | "cmovncw" [token] + | "cmovnel" [token] + | "cmovne" [token] + | "cmovneq" [token] + | "cmovnew" [token] + | "cmovngel" [token] + | "cmovngeq" [token] + | "cmovngew" [token] + | "cmovngl" [token] + | "cmovngq" [token] + | "cmovngw" [token] + | "cmovnlel" [token] + | "cmovnleq" [token] + | "cmovnlew" [token] + | "cmovnll" [token] + | "cmovnlq" [token] + | "cmovnlw" [token] + | "cmovnol" [token] + | "cmovnoq" [token] + | "cmovnow" [token] + | "cmovnpl" [token] + | "cmovnpq" [token] + | "cmovnpw" [token] + | "cmovnsl" [token] + | "cmovnsq" [token] + | "cmovnsw" [token] + | "cmovnzl" [token] + | "cmovnzq" [token] + | "cmovnzw" [token] + | "cmovol" [token] + | "cmovoq" [token] + | "cmovow" [token] + | "cmovpel" [token] + | "cmovpeq" [token] + | "cmovpew" [token] + | "cmovpl" [token] + | "cmovpol" [token] + | "cmovpoq" [token] + | "cmovpow" [token] + | "cmovpq" [token] + | "cmovpw" [token] + | "cmovsl" [token] + | "cmovsq" [token] + | "cmovsw" [token] + | "cmovzl" [token] + | "cmovzq" [token] + | "cmovzw" [token] + | "cmpb" [token] + | "cmpl" [token] + | "cmppd" [token] + | "cmpps" [token] + | "cmpq" [token] + | "cmpsd" [token] + | "cmpss" [token] + | "cmpw" [token] + | "cmpxchg16b" [token] + | "cmpxchg8b" [token] + | "cmpxchgb" [token] + | "cmpxchgl" [token] + | "cmpxchgq" [token] + | "cmpxchgw" [token] + | "comisd" [token] + | "comiss" [token] + | "cqto" [token] + | "cvtdq2pd" [token] + | "cvtdq2ps" [token] + | "cvtpd2dq" [token] + | "cvtpd2ps" [token] + | "cvtpi2pd" [token] + | "cvtpi2ps" [token] + | "cvtps2dq" [token] + | "cvtps2pd" [token] + | "cvtsd2si" [token] + | "cvtsd2ss" [token] + | "cvtsi2sdl" [token] + | "cvtsi2sdq" [token] + | "cvtsi2ssl" [token] + | "cvtsi2ssq" [token] + | "cvtss2sd" [token] + | "cvtss2si" [token] + | "cvttpd2dq" [token] + | "cvttps2dq" [token] + | "cvttsd2si" [token] + | "cvttss2si" [token] + | "cwtd" [token] + | "cwtl" [token] + | "decb" [token] + | "decl" [token] + | "decq" [token] + | "decw" [token] + | "divb" [token] + | "divl" [token] + | "divpd" [token] + | "divps" [token] + | "divq" [token] + | "divsd" [token] + | "divss" [token] + | "divw" [token] + | "dppd" [token] + | "dpps" [token] + | "extractps" [token] + | "haddpd" [token] + | "haddps" [token] + | "hsubpd" [token] + | "hsubps" [token] + | "idivb" [token] + | "idivl" [token] + | "idivq" [token] + | "idivw" [token] + | "imulb" [token] + | "imull" [token] + | "imulq" [token] + | "imulw" [token] + | "incb" [token] + | "incl" [token] + | "incq" [token] + | "incw" [token] + | "insertps" [token] + | "lddqu" [token] + | "leal" [token] + | "leaq" [token] + | "leaw" [token] + | "lzcntl" [token] + | "lzcntq" [token] + | "lzcntw" [token] + | "maxpd" [token] + | "maxps" [token] + | "maxsd" [token] + | "maxss" [token] + | "minpd" [token] + | "minps" [token] + | "minsd" [token] + | "minss" [token] + | "movapd" [token] + | "movaps" [token] + | "movb" [token] + | "movbel" [token] + | "movbeq" [token] + | "movbew" [token] + | "movbe" [token] + | "movd" [token] + | "movddup" [token] + | "movdqa" [token] + | "movdqu" [token] + | "movhlps" [token] + | "movhpd" [token] + | "movhps" [token] + | "movl" [token] + | "movlhps" [token] + | "movlpd" [token] + | "movlps" [token] + | "movmskpd" [token] + | "movmskps" [token] + | "movntdq" [token] + | "movntdqa" [token] + | "movnti" [token] + | "movntpd" [token] + | "movntps" [token] + | "movq" [token] + | "movsbl" [token] + | "movsbq" [token] + | "movsbw" [token] + | "movsd" [token] + | "movshdup" [token] + | "movsldup" [token] + | "movslq" [token] + | "movss" [token] + | "movswl" [token] + | "movswq" [token] + | "movupd" [token] + | "movups" [token] + | "movw" [token] + | "movzbl" [token] + | "movzbq" [token] + | "movzbw" [token] + | "movzwl" [token] + | "movzwq" [token] + | "mpsadbw" [token] + | "mulb" [token] + | "mull" [token] + | "mulpd" [token] + | "mulps" [token] + | "mulq" [token] + | "mulsd" [token] + | "mulss" [token] + | "mulw" [token] + | "mulxl" [token] + | "mulxq" [token] + | "mulx" [token] + | "negb" [token] + | "negl" [token] + | "negq" [token] + | "negw" [token] + | "nop" [token] + | "nopl" [token] + | "nopw" [token] + | "notb" [token] + | "notl" [token] + | "notq" [token] + | "notw" [token] + | "orb" [token] + | "orl" [token] + | "orpd" [token] + | "orps" [token] + | "orq" [token] + | "orw" [token] + | "pabsb" [token] + | "pabsd" [token] + | "pabsw" [token] + | "packssdw" [token] + | "packsswb" [token] + | "packusdw" [token] + | "packuswb" [token] + | "paddb" [token] + | "paddd" [token] + | "paddq" [token] + | "paddsb" [token] + | "paddsw" [token] + | "paddusb" [token] + | "paddusw" [token] + | "paddw" [token] + | "palignr" [token] + | "pand" [token] + | "pandn" [token] + | "pavgb" [token] + | "pavgw" [token] + | "pblendvb" [token] + | "pblendw" [token] + | "pclmulqdq" [token] + | "pcmpeqb" [token] + | "pcmpeqd" [token] + | "pcmpeqq" [token] + | "pcmpeqw" [token] + | "pcmpestri" [token] + | "pcmpestrm" [token] + | "pcmpgtb" [token] + | "pcmpgtd" [token] + | "pcmpgtq" [token] + | "pcmpgtw" [token] + | "pcmpistri" [token] + | "pcmpistrm" [token] + | "pdepl" [token] + | "pdepq" [token] + | "pextl" [token] + | "pextq" [token] + | "pextrb" [token] + | "pextrd" [token] + | "pextrq" [token] + | "pextrw" [token] + | "phaddd" [token] + | "phaddsw" [token] + | "phaddw" [token] + | "phminposuw" [token] + | "phsubd" [token] + | "phsubsw" [token] + | "phsubw" [token] + | "pinsrb" [token] + | "pinsrd" [token] + | "pinsrq" [token] + | "pinsrw" [token] + | "pmaddubsw" [token] + | "pmaddwd" [token] + | "pmaxsb" [token] + | "pmaxsd" [token] + | "pmaxsw" [token] + | "pmaxub" [token] + | "pmaxud" [token] + | "pmaxuw" [token] + | "pminsb" [token] + | "pminsd" [token] + | "pminsw" [token] + | "pminub" [token] + | "pminud" [token] + | "pminuw" [token] + | "pmovmskb" [token] + | "pmovsxbd" [token] + | "pmovsxbq" [token] + | "pmovsxbw" [token] + | "pmovsxdq" [token] + | "pmovsxwd" [token] + | "pmovsxwq" [token] + | "pmovzxbd" [token] + | "pmovzxbq" [token] + | "pmovzxbw" [token] + | "pmovzxdq" [token] + | "pmovzxwd" [token] + | "pmovzxwq" [token] + | "pmuldq" [token] + | "pmulhrsw" [token] + | "pmulhuw" [token] + | "pmulhw" [token] + | "pmulld" [token] + | "pmullw" [token] + | "pmuludq" [token] + | "popcntl" [token] + | "popcntq" [token] + | "popcntw" [token] + | "popq" [token] + | "popw" [token] + | "por" [token] + | "psadbw" [token] + | "pshufb" [token] + | "pshufd" [token] + | "pshufhw" [token] + | "pshuflw" [token] + | "psignb" [token] + | "psignd" [token] + | "psignw" [token] + | "pslld" [token] + | "pslldq" [token] + | "psllq" [token] + | "psllw" [token] + | "psrad" [token] + | "psraw" [token] + | "psrld" [token] + | "psrldq" [token] + | "psrlq" [token] + | "psrlw" [token] + | "psubb" [token] + | "psubd" [token] + | "psubq" [token] + | "psubsb" [token] + | "psubsw" [token] + | "psubusb" [token] + | "psubusw" [token] + | "psubw" [token] + | "ptest" [token] + | "punpckhbw" [token] + | "punpckhdq" [token] + | "punpckhqdq" [token] + | "punpckhwd" [token] + | "punpcklbw" [token] + | "punpckldq" [token] + | "punpcklqdq" [token] + | "punpcklwd" [token] + | "pushq" [token] + | "pushw" [token] + | "pxor" [token] + | "rclb" [token] + | "rcll" [token] + | "rclq" [token] + | "rclw" [token] + | "rcpps" [token] + | "rcpss" [token] + | "rcrb" [token] + | "rcrl" [token] + | "rcrq" [token] + | "rcrw" [token] + | "rolb" [token] + | "roll" [token] + | "rolq" [token] + | "rolw" [token] + | "rorb" [token] + | "rorl" [token] + | "rorq" [token] + | "rorw" [token] + | "rorxl" [token] + | "rorxq" [token] + | "rorx" [token] + | "roundpd" [token] + | "roundps" [token] + | "roundsd" [token] + | "roundss" [token] + | "rsqrtps" [token] + | "rsqrtss" [token] + | "salb" [token] + | "sall" [token] + | "salq" [token] + | "salw" [token] + | "sarb" [token] + | "sarl" [token] + | "sarq" [token] + | "sarw" [token] + | "sarxl" [token] + | "sarxq" [token] + | "sbbb" [token] + | "sbbl" [token] + | "sbbq" [token] + | "sbbw" [token] + | "seta" [token] + | "setae" [token] + | "setb" [token] + | "setbe" [token] + | "setc" [token] + | "sete" [token] + | "setg" [token] + | "setge" [token] + | "setl" [token] + | "setle" [token] + | "setna" [token] + | "setnae" [token] + | "setnb" [token] + | "setnbe" [token] + | "setnc" [token] + | "setne" [token] + | "setng" [token] + | "setnge" [token] + | "setnl" [token] + | "setnle" [token] + | "setno" [token] + | "setnp" [token] + | "setns" [token] + | "setnz" [token] + | "seto" [token] + | "setp" [token] + | "setpe" [token] + | "setpo" [token] + | "sets" [token] + | "setz" [token] + | "shlb" [token] + | "shll" [token] + | "shlq" [token] + | "shlw" [token] + | "shlxl" [token] + | "shlxq" [token] + | "shrb" [token] + | "shrl" [token] + | "shrq" [token] + | "shrw" [token] + | "shrxl" [token] + | "shrxq" [token] + | "shufpd" [token] + | "shufps" [token] + | "sqrtpd" [token] + | "sqrtps" [token] + | "sqrtsd" [token] + | "sqrtss" [token] + | "stc" [token] + | "subb" [token] + | "subl" [token] + | "subpd" [token] + | "subps" [token] + | "subq" [token] + | "subsd" [token] + | "subss" [token] + | "subw" [token] + | "testb" [token] + | "testl" [token] + | "testq" [token] + | "testw" [token] + | "tzcntl" [token] + | "tzcntq" [token] + | "tzcntw" [token] + | "ucomisd" [token] + | "ucomiss" [token] + | "unpckhpd" [token] + | "unpckhps" [token] + | "unpcklpd" [token] + | "unpcklps" [token] + | "vaddpd" [token] + | "vaddps" [token] + | "vaddsd" [token] + | "vaddss" [token] + | "vaddsubpd" [token] + | "vaddsubps" [token] + | "vandnpd" [token] + | "vandnps" [token] + | "vandpd" [token] + | "vandps" [token] + | "vblendpd" [token] + | "vblendps" [token] + | "vblendvpd" [token] + | "vblendvps" [token] + | "vbroadcastf128" [token] + | "vbroadcastsd" [token] + | "vbroadcastss" [token] + | "vcmppd" [token] + | "vcmpps" [token] + | "vcmpsd" [token] + | "vcmpss" [token] + | "vcomisd" [token] + | "vcomiss" [token] + | "vcvtdq2pd" [token] + | "vcvtdq2ps" [token] + | "vcvtpd2dq" [token] + | "vcvtpd2dqx" [token] + | "vcvtpd2dqy" [token] + | "vcvtpd2ps" [token] + | "vcvtpd2psx" [token] + | "vcvtpd2psy" [token] + | "vcvtph2ps" [token] + | "vcvtps2dq" [token] + | "vcvtps2pd" [token] + | "vcvtps2ph" [token] + | "vcvtsd2si" [token] + | "vcvtsd2ss" [token] + | "vcvtsi2sdl" [token] + | "vcvtsi2sdq" [token] + | "vcvtsi2ssl" [token] + | "vcvtsi2ssq" [token] + | "vcvtsi2ss" [token] + | "vcvtss2sd" [token] + | "vcvtss2si" [token] + | "vcvttpd2dq" [token] + | "vcvttpd2dqx" [token] + | "vcvttpd2dqy" [token] + | "vcvttps2dq" [token] + | "vcvttsd2si" [token] + | "vcvttss2si" [token] + | "vdivpd" [token] + | "vdivps" [token] + | "vdivsd" [token] + | "vdivss" [token] + | "vdppd" [token] + | "vdpps" [token] + | "vextractf128" [token] + | "vextracti128" [token] + | "vextractps" [token] + | "vfmadd132pd" [token] + | "vfmadd132ps" [token] + | "vfmadd132sd" [token] + | "vfmadd132ss" [token] + | "vfmadd213pd" [token] + | "vfmadd213ps" [token] + | "vfmadd213sd" [token] + | "vfmadd213ss" [token] + | "vfmadd231pd" [token] + | "vfmadd231ps" [token] + | "vfmadd231sd" [token] + | "vfmadd231ss" [token] + | "vfmaddsub132pd" [token] + | "vfmaddsub132ps" [token] + | "vfmaddsub213pd" [token] + | "vfmaddsub213ps" [token] + | "vfmaddsub231pd" [token] + | "vfmaddsub231ps" [token] + | "vfmsub132pd" [token] + | "vfmsub132ps" [token] + | "vfmsub132sd" [token] + | "vfmsub132ss" [token] + | "vfmsub213pd" [token] + | "vfmsub213ps" [token] + | "vfmsub213sd" [token] + | "vfmsub213ss" [token] + | "vfmsub231pd" [token] + | "vfmsub231ps" [token] + | "vfmsub231sd" [token] + | "vfmsub231ss" [token] + | "vfmsubadd132pd" [token] + | "vfmsubadd132ps" [token] + | "vfmsubadd213pd" [token] + | "vfmsubadd213ps" [token] + | "vfmsubadd231pd" [token] + | "vfmsubadd231ps" [token] + | "vfnmadd132pd" [token] + | "vfnmadd132ps" [token] + | "vfnmadd132sd" [token] + | "vfnmadd132ss" [token] + | "vfnmadd213pd" [token] + | "vfnmadd213ps" [token] + | "vfnmadd213sd" [token] + | "vfnmadd213ss" [token] + | "vfnmadd231pd" [token] + | "vfnmadd231ps" [token] + | "vfnmadd231sd" [token] + | "vfnmadd231ss" [token] + | "vfnmsub132pd" [token] + | "vfnmsub132ps" [token] + | "vfnmsub132sd" [token] + | "vfnmsub132ss" [token] + | "vfnmsub213pd" [token] + | "vfnmsub213ps" [token] + | "vfnmsub213sd" [token] + | "vfnmsub213ss" [token] + | "vfnmsub231pd" [token] + | "vfnmsub231ps" [token] + | "vfnmsub231sd" [token] + | "vfnmsub231ss" [token] + | "vhaddpd" [token] + | "vhaddps" [token] + | "vhsubpd" [token] + | "vhsubps" [token] + | "vinsertf128" [token] + | "vinserti128" [token] + | "vinsertps" [token] + | "vlddqu" [token] + | "vmaskmovpd" [token] + | "vmaskmovps" [token] + | "vmaxpd" [token] + | "vmaxps" [token] + | "vmaxsd" [token] + | "vmaxss" [token] + | "vminpd" [token] + | "vminps" [token] + | "vminsd" [token] + | "vminss" [token] + | "vmovapd" [token] + | "vmovaps" [token] + | "vmovd" [token] + | "vmovddup" [token] + | "vmovdqa" [token] + | "vmovdqu" [token] + | "vmovhlps" [token] + | "vmovhpd" [token] + | "vmovhps" [token] + | "vmovlhps" [token] + | "vmovlpd" [token] + | "vmovlps" [token] + | "vmovmskpd" [token] + | "vmovmskps" [token] + | "vmovntdqa" [token] + | "vmovntdq" [token] + | "vmovntpd" [token] + | "vmovntps" [token] + | "vmovq" [token] + | "vmovsd" [token] + | "vmovshdup" [token] + | "vmovsldup" [token] + | "vmovss" [token] + | "vmovupd" [token] + | "vmovups" [token] + | "vmpsadbw" [token] + | "vmulpd" [token] + | "vmulps" [token] + | "vmulsd" [token] + | "vmulss" [token] + | "vorpd" [token] + | "vorps" [token] + | "vpabsb" [token] + | "vpabsd" [token] + | "vpabsw" [token] + | "vpackssdw" [token] + | "vpacksswb" [token] + | "vpackusdw" [token] + | "vpackuswb" [token] + | "vpaddb" [token] + | "vpaddd" [token] + | "vpaddq" [token] + | "vpaddsb" [token] + | "vpaddsw" [token] + | "vpaddusb" [token] + | "vpaddusw" [token] + | "vpaddw" [token] + | "vpalignr" [token] + | "vpand" [token] + | "vpandn" [token] + | "vpavgb" [token] + | "vpavgw" [token] + | "vpblendd" [token] + | "vpblendvb" [token] + | "vpblendw" [token] + | "vpbroadcastb" [token] + | "vpbroadcastd" [token] + | "vbroadcasti128" [token] + | "vpbroadcastq" [token] + | "vpbroadcastw" [token] + | "vpclmulqdq" [token] + | "vpcmpeqb" [token] + | "vpcmpeqd" [token] + | "vpcmpeqq" [token] + | "vpcmpeqw" [token] + | "vpcmpestri" [token] + | "vpcmpestrm" [token] + | "vpcmpgtb" [token] + | "vpcmpgtd" [token] + | "vpcmpgtq" [token] + | "vpcmpgtw" [token] + | "vpcmpistri" [token] + | "vpcmpistrm" [token] + | "vperm2f128" [token] + | "vperm2i128" [token] + | "vpermd" [token] + | "vpermilpd" [token] + | "vpermilps" [token] + | "vpermpd" [token] + | "vpermps" [token] + | "vpermq" [token] + | "vpextrb" [token] + | "vpextrd" [token] + | "vpextrq" [token] + | "vpextrw" [token] + | "vphaddd" [token] + | "vphaddsw" [token] + | "vphaddw" [token] + | "vphminposuw" [token] + | "vphsubd" [token] + | "vphsubsw" [token] + | "vphsubw" [token] + | "vpinsrb" [token] + | "vpinsrd" [token] + | "vpinsrq" [token] + | "vpinsrw" [token] + | "vpmaddubsw" [token] + | "vpmaddwd" [token] + | "vpmaskmovd" [token] + | "vpmaskmovq" [token] + | "vpmaxsb" [token] + | "vpmaxsd" [token] + | "vpmaxsw" [token] + | "vpmaxub" [token] + | "vpmaxud" [token] + | "vpmaxuw" [token] + | "vpminsb" [token] + | "vpminsd" [token] + | "vpminsw" [token] + | "vpminub" [token] + | "vpminud" [token] + | "vpminuw" [token] + | "vpmovmskb" [token] + | "vpmovsxbd" [token] + | "vpmovsxbq" [token] + | "vpmovsxbw" [token] + | "vpmovsxdq" [token] + | "vpmovsxwd" [token] + | "vpmovsxwq" [token] + | "vpmovzxbd" [token] + | "vpmovzxbq" [token] + | "vpmovzxbw" [token] + | "vpmovzxdq" [token] + | "vpmovzxwd" [token] + | "vpmovzxwq" [token] + | "vpmuldq" [token] + | "vpmulhrsw" [token] + | "vpmulhuw" [token] + | "vpmulhw" [token] + | "vpmulld" [token] + | "vpmullw" [token] + | "vpmuludq" [token] + | "vpor" [token] + | "vpsadbw" [token] + | "vpshufb" [token] + | "vpshufd" [token] + | "vpshufhw" [token] + | "vpshuflw" [token] + | "vpsignb" [token] + | "vpsignd" [token] + | "vpsignw" [token] + | "vpslld" [token] + | "vpslldq" [token] + | "vpsllq" [token] + | "vpsllvd" [token] + | "vpsllvq" [token] + | "vpsllw" [token] + | "vpsrad" [token] + | "vpsravd" [token] + | "vpsraw" [token] + | "vpsrld" [token] + | "vpsrldq" [token] + | "vpsrlq" [token] + | "vpsrlvd" [token] + | "vpsrlvq" [token] + | "vpsrlw" [token] + | "vpsubb" [token] + | "vpsubd" [token] + | "vpsubq" [token] + | "vpsubsb" [token] + | "vpsubsw" [token] + | "vpsubusb" [token] + | "vpsubusw" [token] + | "vpsubw" [token] + | "vptest" [token] + | "vpunpckhbw" [token] + | "vpunpckhdq" [token] + | "vpunpckhqdq" [token] + | "vpunpckhwd" [token] + | "vpunpcklbw" [token] + | "vpunpckldq" [token] + | "vpunpcklqdq" [token] + | "vpunpcklwd" [token] + | "vpvmpgtq" [token] + | "vpxor" [token] + | "vrcpps" [token] + | "vrcpss" [token] + | "vroundpd" [token] + | "vroundps" [token] + | "vroundsd" [token] + | "vroundss" [token] + | "vrsqrtps" [token] + | "vrsqrtss" [token] + | "vshufpd" [token] + | "vshufps" [token] + | "vsqrtpd" [token] + | "vsqrtps" [token] + | "vsqrtsd" [token] + | "vsqrtss" [token] + | "vsubpd" [token] + | "vsubps" [token] + | "vsubsd" [token] + | "vsubss" [token] + | "vtestpd" [token] + | "vtestps" [token] + | "vucomisd" [token] + | "vucomiss" [token] + | "vunpckhpd" [token] + | "vunpckhps" [token] + | "vunpcklpd" [token] + | "vunpcklps" [token] + | "vxorpd" [token] + | "vxorps" [token] + | "vzeroall" [token] + | "vzeroupper" [token] + | "xaddb" [token] + | "xaddl" [token] + | "xaddq" [token] + | "xaddw" [token] + | "xchgb" [token] + | "xchgl" [token] + | "xchgq" [token] + | "xchgw" [token] + | "xorb" [token] + | "xorl" [token] + | "xorpd" [token] + | "xorps" [token] + | "xorq" [token] + | "xorw" [token] + | "call" [token] + | "ret" [token] + | "leave" [token] + | "jmp" [token] + | "je" [token] + | "jne" [token] + | "jns" [token] + | "js" [token] + | "jnc" [token] + | "jb" [token] + | "jae" [token] + | "jnb" [token] + | "jle" [token] + | "jg" [token] + | "jge" [token] + | "jl" [token] + | "jbe" [token] + | "ja" [token] + | "jp" [token] + | "jc" [token] + | "jecxz" [token] + | "jna" [token] + | "jnae" [token] + | "jnbe" [token] + | "jng" [token] + | "jnge" [token] + | "jnl" [token] + | "jnle" [token] + | "jno" [token] + | "jnp" [token] + | "jnz" [token] + | "jo" [token] + | "jpe" [token] + | "jpo" [token] + | "jrcxz" [token] + | "jz" [token] + | "movabsq" [token] + | "vcvtsi2sd" [token] + | "sarx" [token] + | "shlx" [token] + | "shrx" [token] + | "cmovs" [token] + | "cmovns" [token] + | "cmovge" [token] + | "cmove" [token] + | "cmovle" [token] + | "cmovbe" [token] + | "ud2" [token] + | "bsfl" [token] + | "bsfq" [token] + | "bsfw" [token] + | "bsrw" [token] + | "bsrl" [token] + | "bsrq" [token] + | "shldq" [token] + | "shldl" [token] + | "shldw" [token] + | "shrdq" [token] + | "shrdl" [token] + | "shrdw" [token] + | "pcmpestri" [token] + | "pcmpestrm" [token] + | "pcmpistri" [token] + | "pcmpistrm" [token] + | "loop" [token] + | "loope" [token] + | "loopne" [token] + | "loopz" [token] + | "loopnz" [token] + | "scasb" [token] + | "repz scasb" [token] + | "repe scasb" [token] + | "repnz scasb" [token] + | "repne scasb" [token] + | "scasw" [token] + | "repz scasw" [token] + | "repe scasw" [token] + | "repnz scasw" [token] + | "repne scasw" [token] + | "scasl" [token] + | "repz scasl" [token] + | "repe scasl" [token] + | "repnz scasl" [token] + | "repne scasl" [token] + | "scasq" [token] + | "repz scasq" [token] + | "repe scasq" [token] + | "repnz scasq" [token] + | "repne scasq" [token] + | "std" [token] + | "cld" [token] + | "stosb" [token] + | "rep stosb" [token] + | "stosw" [token] + | "rep stosw" [token] + | "rep stosl" [token] + | "stosl" [token] + | "stosq" [token] + | "rep stosq" [token] + | "cmpsb" [token] + | "repz cmpsb" [token] + | "repe cmpsb" [token] + | "repnz cmpsb" [token] + | "repne cmpsb" [token] + | "cmpsw" [token] + | "repz cmpsw" [token] + | "repe cmpsw" [token] + | "repnz cmpsw" [token] + | "repne cmpsw" [token] + | "cmpsl" [token] + | "repz cmpsl" [token] + | "repe cmpsl" [token] + | "repnz cmpsl" [token] + | "repne cmpsl" [token] + | "cmpsq" [token] + | "repz cmpsq" [token] + | "repe cmpsq" [token] + | "repnz cmpsq" [token] + | "repne cmpsq" [token] + | "lodsb" [token] + | "rep lodsb" [token] + | "lodsw" [token] + | "rep lodsw" [token] + | "lodsl" [token] + | "rep lodsl" [token] + | "lodsq" [token] + | "rep lodsq" [token] + | "movsb" [token] + | "rep movsb" [token] + | "movsw" [token] + | "rep movsw" [token] + | "movsl" [token] + | "rep movsl" [token] + | "movsq" [token] + | "rep movsq" [token] + | "maskmovdqu" [token] + | "vmaskmovdqu" [token] + | "push" [token] + | "pop" [token] + | "mov" [token] + | "sub" [token] + | "dec" [token] + | "cmp" [token] + | "lea" [token] + | "add" [token] + | "inc" [token] + | "nop" [token] + | "retq" [token] + | "callq" [token] + | "jmpq" [token] + | "leaveq" [token] + | "pseudofloattestopcode1" [token] endmodule From c43b75fc2b17bdd6826921a1a6585dc405fa594d Mon Sep 17 00:00:00 2001 From: andrew_miranti Date: Tue, 5 Feb 2019 20:21:53 -0600 Subject: [PATCH 04/15] Changes to make decoder compile --- semantics/common/library/common-c-library-configuration.k | 2 +- semantics/common/library/common-c-library-stdlib.k | 4 +--- semantics/x86-syntax.k | 7 +++++-- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/semantics/common/library/common-c-library-configuration.k b/semantics/common/library/common-c-library-configuration.k index 10fc117d5..cd0bdd626 100644 --- a/semantics/common/library/common-c-library-configuration.k +++ b/semantics/common/library/common-c-library-configuration.k @@ -19,7 +19,7 @@ module COMMON-C-LIBRARY-CONFIGURATION .Set - + .K .K 0 diff --git a/semantics/common/library/common-c-library-stdlib.k b/semantics/common/library/common-c-library-stdlib.k index 361e2eff0..f94e5f509 100644 --- a/semantics/common/library/common-c-library-stdlib.k +++ b/semantics/common/library/common-c-library-stdlib.k @@ -20,9 +20,7 @@ module COMMON-C-LIBRARY-STDLIB rule stdlib_exit(I::Int) => exitExecution(I) - rule stdlib_abort ~> _ - => - writeFD(#stdout, "Aborted\n") ~> flush(#stdout) ~> asCInt(134) + rule stdlib_abort ~> _ => writeFD(#stdout, "Aborted\n") ~> flush(#stdout) ~> asCInt(134) rule stdlib_atexit(FP::VoidFunctionPointer) => success ... (.K => callExitHandler(FP)) ... diff --git a/semantics/x86-syntax.k b/semantics/x86-syntax.k index 7140e9465..e82602b6c 100644 --- a/semantics/x86-syntax.k +++ b/semantics/x86-syntax.k @@ -144,12 +144,16 @@ module X86-SYNTAX | Xmm | Ymm | Mm + | Sreg + | Rip + | St // syntax Memoffs ::= Offset // | Sreg ":" Offset syntax Offset ::= Int syntax Imm ::= "$" Int | HexConstant + /*@ * `Mem` can be evaluated to a KResult `MemOffset` * Hence making MemOffset a subsort of Mem. @@ -181,7 +185,7 @@ module X86-SYNTAX | X86Id "(" R64 "," R64 ")" | X86Id "+" Int "(" R64 "," R64 "," Scale ")" | X86Id "+" Int "(" R64 "," R64 ")" - + // | Int ? How should we do this for absolute addressing? // | Sreg ":" "(" R32 ")" // | Sreg ":" "(" R64 ")" // | Sreg ":" "(" Rip ")" @@ -337,7 +341,6 @@ module X86-SYNTAX | "%ymm14" [token] | "%ymm15" [token] -<<<<<<< HEAD syntax Opcode ::= "adcb" [token] | "adcl" [token] | "adcq" [token] From 9b8787e17709613fe28351c5b6f00a434ebec1e0 Mon Sep 17 00:00:00 2001 From: andrew_miranti Date: Mon, 11 Feb 2019 19:01:56 -0600 Subject: [PATCH 05/15] Minor syntax updates because I was getting strange kompile errors --- semantics/x86-syntax.k | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/semantics/x86-syntax.k b/semantics/x86-syntax.k index e82602b6c..06feaa148 100644 --- a/semantics/x86-syntax.k +++ b/semantics/x86-syntax.k @@ -136,16 +136,17 @@ module X86-SYNTAX //syntax Simpleoperand ::= Register | Imm | MemOffset //syntax Operand ::= Simpleoperand + syntax R64OrRIP ::= R64 | Rip + syntax Register ::= Rh | R8 | R16 | R32 - | R64 + | R64OrRIP | Xmm | Ymm | Mm | Sreg - | Rip | St // syntax Memoffs ::= Offset // | Sreg ":" Offset @@ -159,14 +160,14 @@ module X86-SYNTAX * Hence making MemOffset a subsort of Mem. */ syntax Mem ::= MemOffset - syntax Mem ::= "(" Rip ")" + syntax Mem ::= /*"(" Rip ")" | X86Id "(" Rip ")" | X86Id "+" Int "(" Rip ")" //------------------------------------ - | "(" R64 ")" - | Offset "(" R64 ")" - | X86Id "(" R64 ")" - | X86Id "+" Int "(" R64 ")" + |*/ "(" R64OrRIP ")" + | Offset "(" R64OrRIP ")" + | X86Id "(" R64OrRIP ")" + | X86Id "+" Int "(" R64OrRIP ")" //------------------------------------ | "(" "," R64 "," Scale ")" | "(" "," R64 ")" From b64e647dbc2730e18c397f85c8f800975c31c2d4 Mon Sep 17 00:00:00 2001 From: andrew_miranti Date: Tue, 12 Feb 2019 00:31:20 -0600 Subject: [PATCH 06/15] The memory model migration begins. Removing lots of call sites into the old model to replace them with new, removed assembler labels (since they will not exist in the decoded instruction stream) --- semantics/common/common-memory.k | 458 ------------------ semantics/common/common.k | 2 - semantics/elf-loader.k | 27 ++ semantics/elf-syntax.k | 16 + semantics/extras/alternative_opcodes.k | 6 - semantics/hex-token.k | 18 + .../immediateInstructions/addq_r64_label.k | 34 -- .../immediateInstructions/cmpq_r64_label.k | 33 -- .../immediateInstructions/movl_r32_label.k | 22 - .../immediateInstructions/movq_r64_label.k | 23 - semantics/memoryInstructions/cmpq_m64_label.k | 42 -- semantics/memoryInstructions/movq_m64_label.k | 30 -- semantics/systemInstructions/callq_label.k | 15 - semantics/systemInstructions/ja_label.k | 23 - semantics/systemInstructions/ja_rel32.k | 20 +- semantics/systemInstructions/jae_label.k | 21 - semantics/systemInstructions/jb_label.k | 21 - semantics/systemInstructions/jbe_label.k | 23 - semantics/systemInstructions/jc_label.k | 21 - semantics/systemInstructions/je_label.k | 21 - semantics/systemInstructions/jecxz_label.k | 21 - semantics/systemInstructions/jg_label.k | 23 - semantics/systemInstructions/jge_label.k | 19 - semantics/systemInstructions/jl_label.k | 19 - semantics/systemInstructions/jle_label.k | 23 - semantics/systemInstructions/jmp_label.k | 14 - semantics/systemInstructions/jna_label.k | 21 - semantics/systemInstructions/jnae_label.k | 21 - semantics/systemInstructions/jnb_label.k | 21 - semantics/systemInstructions/jnbe_label.k | 22 - semantics/systemInstructions/jnc_label.k | 21 - semantics/systemInstructions/jne_label.k | 21 - semantics/systemInstructions/jng_label.k | 21 - semantics/systemInstructions/jnge_label.k | 21 - semantics/systemInstructions/jnl_label.k | 21 - semantics/systemInstructions/jnle_label.k | 21 - semantics/systemInstructions/jno_label.k | 21 - semantics/systemInstructions/jnp_label.k | 21 - semantics/systemInstructions/jns_label.k | 21 - semantics/systemInstructions/jnz_label.k | 21 - semantics/systemInstructions/jo_label.k | 21 - semantics/systemInstructions/jp_label.k | 21 - semantics/systemInstructions/jpe_label.k | 21 - semantics/systemInstructions/jpo_label.k | 21 - semantics/systemInstructions/jrcxz_label.k | 21 - semantics/systemInstructions/js_label.k | 21 - semantics/systemInstructions/jz_label.k | 21 - semantics/systemInstructions/loop_label.k | 33 -- semantics/systemInstructions/loope_label.k | 35 -- semantics/systemInstructions/loopne_label.k | 35 -- semantics/systemInstructions/loopnz_label.k | 35 -- semantics/systemInstructions/loopz_label.k | 35 -- semantics/x86-abstract-semantics.k | 177 +------ semantics/x86-abstract-syntax.k | 20 +- semantics/x86-commom-memory-clib-interface.k | 2 - semantics/x86-configuration.k | 32 +- semantics/x86-env-init.k | 11 +- semantics/x86-fetch-execute.k | 8 +- semantics/x86-mint-wrapper.k | 2 +- semantics/x86-semantics.k | 3 - semantics/x86-syntax.k | 106 +--- 61 files changed, 110 insertions(+), 1861 deletions(-) delete mode 100644 semantics/common/common-memory.k create mode 100644 semantics/elf-loader.k create mode 100644 semantics/elf-syntax.k create mode 100644 semantics/hex-token.k delete mode 100644 semantics/immediateInstructions/addq_r64_label.k delete mode 100644 semantics/immediateInstructions/cmpq_r64_label.k delete mode 100644 semantics/immediateInstructions/movl_r32_label.k delete mode 100644 semantics/immediateInstructions/movq_r64_label.k delete mode 100644 semantics/memoryInstructions/cmpq_m64_label.k delete mode 100644 semantics/memoryInstructions/movq_m64_label.k delete mode 100644 semantics/systemInstructions/callq_label.k delete mode 100644 semantics/systemInstructions/ja_label.k delete mode 100644 semantics/systemInstructions/jae_label.k delete mode 100644 semantics/systemInstructions/jb_label.k delete mode 100644 semantics/systemInstructions/jbe_label.k delete mode 100644 semantics/systemInstructions/jc_label.k delete mode 100644 semantics/systemInstructions/je_label.k delete mode 100644 semantics/systemInstructions/jecxz_label.k delete mode 100644 semantics/systemInstructions/jg_label.k delete mode 100644 semantics/systemInstructions/jge_label.k delete mode 100644 semantics/systemInstructions/jl_label.k delete mode 100644 semantics/systemInstructions/jle_label.k delete mode 100644 semantics/systemInstructions/jmp_label.k delete mode 100644 semantics/systemInstructions/jna_label.k delete mode 100644 semantics/systemInstructions/jnae_label.k delete mode 100644 semantics/systemInstructions/jnb_label.k delete mode 100644 semantics/systemInstructions/jnbe_label.k delete mode 100644 semantics/systemInstructions/jnc_label.k delete mode 100644 semantics/systemInstructions/jne_label.k delete mode 100644 semantics/systemInstructions/jng_label.k delete mode 100644 semantics/systemInstructions/jnge_label.k delete mode 100644 semantics/systemInstructions/jnl_label.k delete mode 100644 semantics/systemInstructions/jnle_label.k delete mode 100644 semantics/systemInstructions/jno_label.k delete mode 100644 semantics/systemInstructions/jnp_label.k delete mode 100644 semantics/systemInstructions/jns_label.k delete mode 100644 semantics/systemInstructions/jnz_label.k delete mode 100644 semantics/systemInstructions/jo_label.k delete mode 100644 semantics/systemInstructions/jp_label.k delete mode 100644 semantics/systemInstructions/jpe_label.k delete mode 100644 semantics/systemInstructions/jpo_label.k delete mode 100644 semantics/systemInstructions/jrcxz_label.k delete mode 100644 semantics/systemInstructions/js_label.k delete mode 100644 semantics/systemInstructions/jz_label.k delete mode 100644 semantics/systemInstructions/loop_label.k delete mode 100644 semantics/systemInstructions/loope_label.k delete mode 100644 semantics/systemInstructions/loopne_label.k delete mode 100644 semantics/systemInstructions/loopnz_label.k delete mode 100644 semantics/systemInstructions/loopz_label.k diff --git a/semantics/common/common-memory.k b/semantics/common/common-memory.k deleted file mode 100644 index 7641df98b..000000000 --- a/semantics/common/common-memory.k +++ /dev/null @@ -1,458 +0,0 @@ -module COMMON-MEMORY-OPAQUE-SORTS - // This sort should be provided by the client and represents the scalar values - // that can be stored in memory cells. - syntax AbstractValue [smt-prelude] -endmodule - - -module COMMON-MEMORY-SORTS - syntax MemLoc [smt-prelude] - syntax MemData - syntax MemValue - syntax MemoryMap [smt-prelude] - syntax MemorySet [smt-prelude] - syntax Memory -endmodule - - -module COMMON-MEMORY-OPAQUE-SYNTAX - imports COMMON-MEMORY-OPAQUE-SORTS - - // This function should be implemented by the client. It returns the default - // AbstractValue to be used for uninitialized memory cells. - syntax AbstractValue ::= getDefaultAbstractValue() [function] -endmodule - - -// A map to be used for memory contents: MemLoc -> AbstractValue. -// This map uses array theory and is implemented as a complete mapping, using -// the default AbstractValue as the initial binding for any key. -module COMMON-MEMORY-MAP-SYNTAX - imports COMMON-MEMORY-OPAQUE-SORTS - imports COMMON-MEMORY-SORTS - - // Empty MemoryMap - syntax MemoryMap ::= ".MemoryMap" [function] - - // Retrieve the AbstractValue associated with the given MemLoc. - syntax AbstractValue ::= selectMemoryMap(MemoryMap, MemLoc) - [function, smtlib(select)] - - // Update a MemoryMap with a new AbstractValue binding for MemLoc. - syntax MemoryMap ::= storeMemoryMap(MemoryMap, MemLoc, AbstractValue) - [function, smtlib(store)] -endmodule - - -// A set to be used to keep track of freed memory locations. This set -// is implemented as a complete array from MemLoc to Bool. -module COMMON-MEMORY-SET-SYNTAX - imports COMMON-MEMORY-OPAQUE-SORTS - imports COMMON-MEMORY-SORTS - - // Empty MemorySet - syntax MemorySet ::= ".MemorySet" [function, smtlib(smt_set_emp)] - - // Check for membership - syntax Bool ::= inMemorySet(MemLoc, MemorySet) - [function, smtlib(smt_set_mem)] - - // Add a MemLoc to the set. - syntax MemorySet ::= addMemorySet(MemorySet, MemLoc) - [function, smtlib(smt_set_add)] -endmodule - - -module COMMON-MEMORY-SYNTAX - imports COMMON-MEMORY-SORTS - imports COMMON-MEMORY-OPAQUE-SORTS - - imports INT - - // A symbolically addressed memory location. - syntax MemLoc ::= symloc(/* location ID */ Int, - /* alignment in bits */ Int, - /* location size in elements */ Int, - /* element size in bits */ Int, - /* offset in elements */ Int) - [smtlib(symloc), smt-prelude] - - // The memory model supports concrete addresses for memory locations. - // They are guaranteed to not be aliased with any of the symbolically - // addressed memory locations, but the client is responsible for not - // overlapping two or more memory locations with concrete addresses. - syntax MemLoc ::= loc(/* actual address */ Int, - /* location size in elements */ Int, - /* element size in bits */ Int, - /* offset in elements */ Int) - [smtlib(loc), smt-prelude] - - syntax Bool ::= isMemLocAlignedAt(/* alignment requirement in bits */ Int, - MemLoc) - [function] - - syntax Bool ::= isMemLocNull(MemLoc) [function] - - syntax MemData ::= ".MemData" [smtlib(emptyMemData)] - | AbstractValue MemData [smtlib(memData)] - - syntax Int ::= lengthMemData(MemData) [function] - syntax MemData ::= appendMemData(MemData, MemData) [function] - syntax MemData ::= revMemData(MemData) [function] - syntax MemData ::= takeMemData(Int, MemData) [function] - syntax MemData ::= dropMemData(Int, MemData) [function] - syntax MemData ::= makeMemData(/* number of elements */ Int, - /* initial element value */ AbstractValue) - [function] - - syntax MemValue ::= mList(/* size in elements */ Int, - /* element size in bits */ Int, - /* list of elements */ MemData) - - syntax Int ::= bitSizeOfMemValue(MemValue) [function] - - syntax Memory ::= mem(MemoryMap) - - syntax KItem ::= mSize(MemLoc) - - syntax KItem ::= mAlloc(/* allocation size in elements */ Int, - /* element size in bits */ Int, - /* alignment in bits */ Int) - - syntax KItem ::= mRead(MemLoc, - /* offset in bits */ Int, - /* size to read in elements */ Int, - /* element size in bits */ Int) - - syntax KItem ::= mWrite(MemLoc, /* offset in bits */ Int, MemValue) - - syntax KItem ::= mClear(MemLoc) - - // Int is a KResult, since mSize evaluates to an Int - syntax KResult ::= Int - - // MemLoc is a KResult, since mAlloc evaluates to a MemLoc - syntax KResult ::= MemLoc - - // MemValue is a KResult, since mRead evaluates to a MemValue - syntax KResult ::= MemValue -endmodule - - -module COMMON-MEMORY-CONFIGURATION - imports COMMON-MEMORY-MAP-SYNTAX - imports COMMON-MEMORY-SET-SYNTAX - imports COMMON-MEMORY-SYNTAX - - configuration - - 1 // TODO: should be randomly initialized - mem(.MemoryMap) - .MemorySet - -endmodule - - -module COMMON-MEMORY - imports COMMON-MEMORY-SYNTAX - imports COMMON-MEMORY-OPAQUE-SYNTAX - imports COMMON-MEMORY-MAP-SYNTAX - imports COMMON-MEMORY-SET-SYNTAX - imports COMMON-ERROR-SYNTAX - imports COMMON-UTILS-SYNTAX - imports COMMON-CONFIGURATION - - imports MAP - imports SET - - rule isMemLocAlignedAt(A:Int, loc(Addr:Int, _:Int, _:Int, _:Int)) - => - Addr %Int A ==Int 0 - rule isMemLocAlignedAt(A:Int, symloc(_:Int, LocA:Int, _:Int, _:Int, _:Int)) - => - A <=Int LocA - - rule isMemLocNull(loc(Addr:Int, _:Int, _:Int, _:Int)) => Addr ==Int 0 - rule isMemLocNull(symloc(_:Int, _:Int, _:Int, _:Int, _:Int)) => false - - rule lengthMemData(D:MemData) => lengthMemDataAux(D, 0) - - syntax Int ::= lengthMemDataAux(MemData, Int) [function] - rule lengthMemDataAux(.MemData, Len:Int) => Len - rule lengthMemDataAux(_:AbstractValue D:MemData, Len:Int) - => - lengthMemDataAux(D, Len +Int 1) - - rule appendMemData(D1:MemData, D2:MemData) - => - revAppendMemData(revMemData(D1), D2) - - rule revMemData(D:MemData) => revAppendMemData(D, .MemData) - - syntax MemData ::= revAppendMemData(MemData, MemData) [function] - rule revAppendMemData(.MemData, D:MemData) => D - rule revAppendMemData(V:AbstractValue D1:MemData, D2:MemData) - => - revAppendMemData(D1, V D2) - - rule takeMemData(N:Int, D:MemData) => takeMemDataAux(N, D, .MemData) - - syntax MemData ::= takeMemDataAux(Int, MemData, MemData) [function] - rule takeMemDataAux(N:Int, _:MemData, D:MemData) => revMemData(D) - requires N ==Int 0 - rule takeMemDataAux(N:Int, V:AbstractValue D:MemData, Acc:MemData) - => - takeMemDataAux(N -Int 1, D, V Acc) - requires N >Int 0 - - rule dropMemData(N:Int, D:MemData) => D - requires N ==Int 0 - rule dropMemData(N:Int, V:AbstractValue D:MemData) => dropMemData(N -Int 1, D) - requires N >Int 0 - - rule makeMemData(N:Int, V:AbstractValue) => makeMemDataAux(N, V, .MemData) - - syntax MemData ::= makeMemDataAux(Int, AbstractValue, MemData) [function] - rule makeMemDataAux(N:Int, _:AbstractValue, D:MemData) => D - requires N ==Int 0 - rule makeMemDataAux(N:Int, V:AbstractValue, Acc:MemData) - => - makeMemDataAux(N -Int 1, V, V Acc) - requires N >Int 0 - - rule bitSizeOfMemValue(mList(N:Int, Sz:Int, _:MemData)) => N *Int Sz - - syntax Bool ::= inBoundsAccess(/* size in elements */ Int, - /* element size in bits */ Int, - /* offset in bits */ Int, - /* access size in bits */ Int) - [function] - rule inBoundsAccess(N:Int, Sz:Int, Offs:Int, AccessSz:Int) - => - Offs >=Int 0 andBool AccessSz >=Int 0 andBool - Offs +Int AccessSz <=Int N *Int Sz andBool - Offs %Int Sz ==Int 0 - - // This function assumes that the memory access is inbounds - syntax MemValue ::= - readMemValue(/* pointer in memory location */ MemLoc, - /* offset in bits */ Int, - /* number of elements to read */ Int, - /* element size in bits */ Int, - /* memory to read from */ Memory) - [function] - rule readMemValue(loc(Addr:Int, N:Int, Sz:Int, I:Int), - Offs:Int, NumElems:Int, ElemSz:Int, mem(M:MemoryMap)) - => - mList(NumElems, Sz, readMemValueAux(loc(Addr, N, Sz, I), - Offs /Int Sz +Int NumElems -Int 1, - NumElems, - M, .MemData)) - requires ElemSz ==Int Sz - // TODO: More cases needed when sizes do not agree - rule readMemValue(symloc(LocID:Int, A:Int, N:Int, Sz:Int, I:Int), - Offs:Int, NumElems:Int, ElemSz:Int, mem(M:MemoryMap)) - => - mList(NumElems, Sz, readMemValueAux(symloc(LocID, A, N, Sz, I), - Offs /Int Sz +Int NumElems -Int 1, - NumElems, - M, .MemData)) - requires ElemSz ==Int Sz - // TODO: More cases needed when sizes do not agree - - syntax MemData ::= readMemValueAux(MemLoc, Int, Int, MemoryMap, MemData) - [function] - rule readMemValueAux(_:MemLoc, OffsI:Int, ElemsToRead:Int, _:MemoryMap, - D:MemData) - => - D - requires ElemsToRead ==Int 0 - rule readMemValueAux(loc(Addr:Int, N:Int, Sz:Int, I:Int), - OffsI:Int, ElemsToRead:Int, M:MemoryMap, D:MemData) - => - readMemValueAux(loc(Addr, N, Sz, I), OffsI -Int 1, ElemsToRead -Int 1, M, - selectMemoryMap(M, loc(Addr, N, Sz, I +Int OffsI)) D) - requires ElemsToRead >Int 0 - rule readMemValueAux(symloc(LocID:Int, A:Int, N:Int, Sz:Int, I:Int), - OffsI:Int, ElemsToRead:Int, M:MemoryMap, D:MemData) - => - readMemValueAux( - symloc(LocID, A, N, Sz, I), OffsI -Int 1, ElemsToRead -Int 1, M, - selectMemoryMap(M, symloc(LocID, A, N, Sz, I +Int OffsI)) D) - requires ElemsToRead >Int 0 - - // This function assumes that the memory access is inbounds - syntax Memory ::= writeMemValue(/* memory to write into */ Memory, - /* pointer in memory location */ MemLoc, - /* offset in bits */ Int, - /* value to write */ MemValue) - [function] - rule writeMemValue(mem(M:MemoryMap), loc(Addr:Int, N:Int, Sz:Int, I:Int), - Offs:Int, mList(NumElems:Int, ElemSz:Int, D:MemData)) - => - mem(writeMemValueAux(loc(Addr, N, Sz, I), - Offs /Int Sz, - NumElems, - D, M)) - requires ElemSz ==Int Sz - // TODO: More cases needed when sizes do not agree - rule writeMemValue(mem(M:MemoryMap), - symloc(LocID:Int, A:Int , N:Int, Sz:Int, I:Int), - Offs:Int, mList(NumElems:Int, ElemSz:Int, D:MemData)) - => - mem(writeMemValueAux(symloc(LocID, A, N, Sz, I), - Offs /Int Sz, - NumElems, - D, M)) - requires ElemSz ==Int Sz - // TODO: More cases needed when sizes do not agree - - syntax MemoryMap ::= writeMemValueAux(MemLoc, Int, Int, MemData, MemoryMap) - [function] - rule writeMemValueAux(_:MemLoc, OffsI:Int, ElemsToWrite:Int, .MemData, - M:MemoryMap) - => - M - requires ElemsToWrite ==Int 0 - rule writeMemValueAux(loc(Addr:Int, N:Int, Sz:Int, I:Int), - OffsI:Int, ElemsToWrite:Int, V:AbstractValue D:MemData, - M:MemoryMap) - => - writeMemValueAux(loc(Addr, N, Sz, I), OffsI +Int 1, ElemsToWrite -Int 1, - D, storeMemoryMap(M, loc(Addr, N, Sz, I +Int OffsI), V)) - requires ElemsToWrite >Int 0 - rule writeMemValueAux(symloc(LocID:Int, A:Int, N:Int, Sz:Int, I:Int), - OffsI:Int, ElemsToWrite:Int, V:AbstractValue D:MemData, - M:MemoryMap) - => - writeMemValueAux( - symloc(LocID, A, N, Sz, I), OffsI +Int 1, ElemsToWrite -Int 1, D, - storeMemoryMap(M, symloc(LocID, A, N, Sz, I +Int OffsI), V)) - requires ElemsToWrite >Int 0 - - rule mSize(loc(_:Int, N:Int, Sz:Int, _:Int)) => N *Int Sz - rule mSize(symloc(_:Int, _:Int, N:Int, Sz:Int, _:Int)) => N *Int Sz - - rule mAlloc(N:Int, Sz:Int, A:Int) => symloc(LocID, A, N, Sz, 0) ... - LocID:Int => LocID +Int 1 - - rule - mRead(loc(Addr:Int, N:Int, Sz:Int, I:Int), - Offs:Int, NumElems:Int, ElemSz:Int) - => - readMemValue(loc(Addr, N, Sz, I), Offs, NumElems, ElemSz, M) - ... - M:Memory - F:MemorySet - requires notBool inMemorySet(loc(Addr, N, Sz, 0), F) - andBool inBoundsAccess(N, Sz, I *Int Sz +Int Offs, - NumElems *Int ElemSz) - rule - mRead(symloc(LocID:Int, A:Int, N:Int, Sz:Int, I:Int), - Offs:Int, NumElems:Int, ElemSz:Int) - => - readMemValue(symloc(LocID, A, N, Sz, I), Offs, NumElems, ElemSz, M) - ... - M:Memory - F:MemorySet - requires notBool inMemorySet(symloc(LocID, A, N, Sz, 0), F) - andBool inBoundsAccess(N, Sz, I *Int Sz +Int Offs, - NumElems *Int ElemSz) - rule - mRead(loc(Addr:Int, N:Int, Sz:Int, I:Int), - Offs:Int, NumElems:Int, ElemSz:Int) - => - error(outOfBoundsMemoryAccess) - ... - F:MemorySet - requires notBool inBoundsAccess(N, Sz, I *Int Sz +Int Offs, - NumElems *Int ElemSz) - orBool inMemorySet(loc(Addr, N, Sz, 0), F) - rule - mRead(symloc(LocID:Int, A:Int, N:Int, Sz:Int, I:Int), - Offs:Int, NumElems:Int, ElemSz:Int) - => - error(outOfBoundsMemoryAccess) - ... - F:MemorySet - requires notBool inBoundsAccess(N, Sz, I *Int Sz +Int Offs, - NumElems *Int ElemSz) - orBool inMemorySet(symloc(LocID, A, N, Sz, 0), F) - - rule - mWrite(loc(Addr:Int, N:Int, Sz:Int, I:Int), Offs:Int, MV:MemValue) - => - . - ... - - M:Memory => writeMemValue(M, loc(Addr, N, Sz, I), Offs, MV) - - F:MemorySet - requires notBool inMemorySet(loc(Addr, N, Sz, 0), F) - andBool inBoundsAccess(N, Sz, I *Int Sz +Int Offs, - bitSizeOfMemValue(MV)) - rule - mWrite(symloc(LocID:Int, A:Int, N:Int, Sz:Int, I:Int), - Offs:Int, MV:MemValue) - => - . - ... - - M:Memory => writeMemValue(M, symloc(LocID, A, N, Sz, I), Offs, MV) - - F:MemorySet - requires notBool inMemorySet(symloc(LocID, A, N, Sz, 0), F) - andBool inBoundsAccess(N, Sz, I *Int Sz +Int Offs, - bitSizeOfMemValue(MV)) - rule - mWrite(loc(Addr:Int, N:Int, Sz:Int, I:Int), Offs:Int, MV:MemValue) - => - error(outOfBoundsMemoryAccess) - ... - F:MemorySet - requires notBool inBoundsAccess(N, Sz, I *Int Sz +Int Offs, - bitSizeOfMemValue(MV)) - orBool inMemorySet(loc(Addr, N, Sz, 0), F) - rule - mWrite(symloc(LocID:Int, A:Int, N:Int, Sz:Int, I:Int), - Offs:Int, MV:MemValue) - => - error(outOfBoundsMemoryAccess) - ... - F:MemorySet - requires notBool inBoundsAccess(N, Sz, I *Int Sz +Int Offs, - bitSizeOfMemValue(MV)) - orBool inMemorySet(symloc(LocID, A, N, Sz, 0), F) - - rule mClear(loc(Addr:Int, N:Int, Sz:Int, I:Int)) => . ... - F:MemorySet => addMemorySet(F, loc(Addr, N, Sz, 0)) - requires I ==Int 0 - rule mClear(symloc(LocID:Int, A:Int, N:Int, Sz:Int, I:Int)) => . ... - - F:MemorySet => addMemorySet(F, symloc(LocID, A, N, Sz, 0)) - - requires I ==Int 0 - - // Concrete implementation for MemoryMap - syntax MemoryMap ::= Map - - rule .MemoryMap => .Map [concrete] - - rule selectMemoryMap(M:Map, L:MemLoc) => {M[L]}:>AbstractValue - requires L in_keys(M) - [concrete] - rule selectMemoryMap(M:Map, L:MemLoc) => getDefaultAbstractValue() - requires notBool (L in_keys(M)) - [concrete] - - rule storeMemoryMap(M:Map, L:MemLoc, V:AbstractValue) => M[L <- V] [concrete] - - // Concrete implementation for MemorySet - syntax MemorySet ::= Set - - rule .MemorySet => .Set [concrete] - - rule inMemorySet(L:MemLoc, S:Set) => L in S [concrete] - - rule addMemorySet(S:Set, L:MemLoc) => SetItem(L) S [concrete] -endmodule diff --git a/semantics/common/common.k b/semantics/common/common.k index 9c875a33b..bcc36a413 100644 --- a/semantics/common/common.k +++ b/semantics/common/common.k @@ -1,6 +1,5 @@ requires "verification-lemmas.k" requires "common-configuration.k" -requires "common-memory.k" requires "common-utils.k" requires "common-error.k" requires "library/common-c-library.k" @@ -8,7 +7,6 @@ requires "library/common-c-library.k" module COMMON imports COMMON-CONFIGURATION imports VERIFICATION-LEMMAS - imports COMMON-MEMORY imports COMMON-UTILS imports COMMON-C-LIBRARY diff --git a/semantics/elf-loader.k b/semantics/elf-loader.k new file mode 100644 index 000000000..093853328 --- /dev/null +++ b/semantics/elf-loader.k @@ -0,0 +1,27 @@ +require "hex-token.k" +require "elf-syntax.k" +require "x86-configuration.k" + +module ELF-LOADER + imports MINT + imports ELF-SYNTAX + imports HEX-TOKEN + imports X86-CONFIGURATION + + rule Cs:Commands ; => Cs [structural] + rule C:Command ; Cs:Commands => C ~> Cs [structural] + rule .Commands => . [structural] + + rule Load(Base:HexConstant, Mem:HexConstant, Len:HexConstant) => . ... + ... (.List => ListItem(StringSegment(HexConstant2Int(Base), HexConstant2Int(Base) + HexConstant2Int(Len), HexConstant2StringNoPrefix(Mem)))) + + // TODO: This rule might be unwise. Right now the *parser* implicitly defines the entry point... should be the semantics job. + rule Entry(E:HexConstant) => . ... + RSMap => RSMap["RIP" <- mi(64, HexConstant2Int(E))] + + // TODO: Log these? Emit warnings? Halt? + rule NamedSymbol(_, NotPresentInFile) => . ... + + rule NamedSymbol(N:String, Addr:HexConstant) => . ... + SymMap => SymMap[N <- mi(64, HexConstant2Int(Addr))] +endmodule diff --git a/semantics/elf-syntax.k b/semantics/elf-syntax.k new file mode 100644 index 000000000..9ffb52f26 --- /dev/null +++ b/semantics/elf-syntax.k @@ -0,0 +1,16 @@ +require "hex-token.k" + +module ELF-SYNTAX + imports STRING-SYNTAX + imports HEX-TOKEN-SYNTAX + + syntax Command ::= "Load" "(" HexConstant "," HexConstant "," HexConstant ")" /* BaseAddress, MemoryContents, SegmentLength */ + // Note: SegmentLength may be "too large," remaining bytes are implicitly zero. + | "Entry" "(" HexConstant ")" + | "NamedSymbol" "(" String "," "NotPresentInFile" ")" + | "NamedSymbol" "(" String "," HexConstant ")" + + syntax Commands ::= List{Command, ";"} + + syntax Elf ::= Commands ";" +endmodule diff --git a/semantics/extras/alternative_opcodes.k b/semantics/extras/alternative_opcodes.k index e73c943c9..70769ecd1 100644 --- a/semantics/extras/alternative_opcodes.k +++ b/semantics/extras/alternative_opcodes.k @@ -89,13 +89,7 @@ module ALTERNATIVE-OPCODES rule execinstr(leaveq:Opcode .Operands) => execinstr(leave .Operands) - ... - rule - execinstr (callq:Opcode LabelId:X86Id, .Operands) => execinstr (call LabelId, .Operands) ... rule execinstr (callq:Opcode B:Builtin, .Operands) => execinstr (call B, .Operands) ... - rule - execinstr (jmpq:Opcode LabelId:X86Id, .Operands) => execinstr (jmp LabelId, .Operands) - ... diff --git a/semantics/hex-token.k b/semantics/hex-token.k new file mode 100644 index 000000000..af1972daa --- /dev/null +++ b/semantics/hex-token.k @@ -0,0 +1,18 @@ +module HEX-TOKEN-SYNTAX + syntax HexConstant ::= r"0x[0-9a-fA-F]+" [token] +endmodule + +module HEX-TOKEN + imports HEX-TOKEN-SYNTAX + imports STRING + imports INT + + syntax String ::= HexConstant2String(HexConstant) [function, hook(STRING.token2string)] + + // Remove 0x hex prefix. + syntax String ::= HexConstant2StringNoPrefix(HexConstant) [function] + rule HexConstant2StringNoPrefix(H) => substrString(HexConstant2String(H), 2, lengthString(HexConstant2String(H))) + + syntax Int ::= HexConstant2Int(HexConstant) [function] + rule HexConstant2Int(H) => String2Base(HexConstant2StringNoPrefix(H), 16) +endmodule diff --git a/semantics/immediateInstructions/addq_r64_label.k b/semantics/immediateInstructions/addq_r64_label.k deleted file mode 100644 index 45d5d4b77..000000000 --- a/semantics/immediateInstructions/addq_r64_label.k +++ /dev/null @@ -1,34 +0,0 @@ -// Autogenerated using stratification. -requires "x86-configuration.k" - -module ADDQ-R64-LABEL - imports X86-CONFIGURATION - - rule - execinstr (addq $ L:X86Id, R2:R64, .Operands) => execinstr (addq $ L:X86Id + 0, R2:R64, .Operands) - ... - - rule - execinstr (addq $ L:X86Id + I:Int , R2:R64, .Operands) => . - ... - -RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), addMInt( LoadAddr, mi(64, I))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) - -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), addMInt( LoadAddr, mi(64, I))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1) - -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), addMInt( LoadAddr, mi(64, I))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), addMInt( LoadAddr, mi(64, I))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), addMInt( LoadAddr, mi(64, I))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), addMInt( LoadAddr, mi(64, I))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), addMInt( LoadAddr, mi(64, I))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), addMInt( LoadAddr, mi(64, I))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), addMInt( LoadAddr, mi(64, I))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), addMInt( LoadAddr, mi(64, I))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) - -"AF" |-> xorMInt( xorMInt( extractMInt( extractMInt(addMInt( LoadAddr, mi(64, I)), 32, 64), 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), addMInt( LoadAddr, mi(64, I))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) - -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), addMInt( LoadAddr, mi(64, I))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) - -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), addMInt( LoadAddr, mi(64, I))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) - -"OF" |-> (#ifMInt ((eqMInt( extractMInt( addMInt( LoadAddr, mi(64, I)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( addMInt( LoadAddr, mi(64, I)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), addMInt( LoadAddr, mi(64, I))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) -) - - - ... L |-> LoadAddr:PointerVal ... - -endmodule diff --git a/semantics/immediateInstructions/cmpq_r64_label.k b/semantics/immediateInstructions/cmpq_r64_label.k deleted file mode 100644 index b48946b0e..000000000 --- a/semantics/immediateInstructions/cmpq_r64_label.k +++ /dev/null @@ -1,33 +0,0 @@ -// Autogenerated using stratification. -requires "x86-configuration.k" - -module CMPQ-R64-LABEL - imports X86-CONFIGURATION - - rule - execinstr (cmpq $ L:X86Id, R2:R64, .Operands) => execinstr (cmpq $ L:X86Id + 0, R2:R64, .Operands) - ... - - rule - execinstr (cmpq $ L:X86Id + I:Int, R2:R64, .Operands) => . - ... - -RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( addMInt( LoadAddr, mi(64, I)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) - -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( addMInt( LoadAddr, mi(64, I)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( addMInt( LoadAddr, mi(64, I)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( addMInt( LoadAddr, mi(64, I)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( addMInt( LoadAddr, mi(64, I)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( addMInt( LoadAddr, mi(64, I)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( addMInt( LoadAddr, mi(64, I)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( addMInt( LoadAddr, mi(64, I)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( addMInt( LoadAddr, mi(64, I)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) - -"AF" |-> xorMInt( xorMInt( extractMInt( extractMInt(addMInt( LoadAddr, mi(64, I)), 32, 64), 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( addMInt( LoadAddr, mi(64, I)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) - -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( addMInt( LoadAddr, mi(64, I)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) - -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( addMInt( LoadAddr, mi(64, I)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) - -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( addMInt( LoadAddr, mi(64, I)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( addMInt( LoadAddr, mi(64, I)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( addMInt( LoadAddr, mi(64, I)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) -) - - - ... L |-> LoadAddr:PointerVal ... - -endmodule - diff --git a/semantics/immediateInstructions/movl_r32_label.k b/semantics/immediateInstructions/movl_r32_label.k deleted file mode 100644 index f7f450524..000000000 --- a/semantics/immediateInstructions/movl_r32_label.k +++ /dev/null @@ -1,22 +0,0 @@ -// Autogenerated using stratification. -requires "x86-configuration.k" - -module MOVL-R32-LABEL - imports X86-CONFIGURATION - - rule - execinstr (movl $ L:X86Id, R2:R32, .Operands) => execinstr (movl $ L:X86Id + 0, R2:R32, .Operands) - ... - - rule - execinstr (movl $ L:X86Id + I:Int, R2:R32, .Operands) => . - ... - -RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), addMInt(extractMInt(LoadAddr, 32, 64), mi(32, I))) -) - - - ... L |-> LoadAddr:PointerVal ... - -endmodule diff --git a/semantics/immediateInstructions/movq_r64_label.k b/semantics/immediateInstructions/movq_r64_label.k deleted file mode 100644 index 8c654c1b4..000000000 --- a/semantics/immediateInstructions/movq_r64_label.k +++ /dev/null @@ -1,23 +0,0 @@ -// Autogenerated using stratification. -requires "x86-configuration.k" - -module MOVQ-R64-LABEL - imports X86-CONFIGURATION - - rule - execinstr (movq $ L:X86Id, R2:R64, .Operands) => execinstr (movq $ L:X86Id + 0, R2:R64, .Operands) - ... - - rule - execinstr (movq $ L:X86Id + I:Int, R2:R64, .Operands) => . - ... - -RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> addMInt( LoadAddr, mi(64, I)) -) - - - ... L |-> LoadAddr:PointerVal ... - -endmodule - diff --git a/semantics/memoryInstructions/cmpq_m64_label.k b/semantics/memoryInstructions/cmpq_m64_label.k deleted file mode 100644 index c2d02cb52..000000000 --- a/semantics/memoryInstructions/cmpq_m64_label.k +++ /dev/null @@ -1,42 +0,0 @@ -// Autogenerated using stratification. -requires "x86-configuration.k" - -module CMPQ-M64-LABEL - imports X86-CONFIGURATION - - rule - execinstr (cmpq $ L:X86Id, M:Mem, .Operands) => - execinstr (cmpq $ L:X86Id + 0, M:Mem, .Operands) - ... - - context execinstr(cmpq:Opcode $ L:X86Id + I:Int, HOLE:Mem, .Operands) [result(MemOffset)] - - rule - execinstr (cmpq:Opcode $ L:X86Id + I:Int, memOffset( MemOff:MInt):MemOffset, .Operands) => - loadFromMemory( MemOff, 64) ~> - execinstr (cmpq $ L + I, memOffset( MemOff), .Operands) - ... - RSMap:Map - - rule - memLoadValue(Mem64:MInt):MemLoadValue ~> - execinstr (cmpq:Opcode $ L:X86Id + I:Int, memOffset( MemOff:MInt):MemOffset, .Operands) => - . - ... - - RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( addMInt( LoadAddr, mi(64, I)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) - -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( addMInt( LoadAddr, mi(64, I)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( addMInt( LoadAddr, mi(64, I)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( addMInt( LoadAddr, mi(64, I)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( addMInt( LoadAddr, mi(64, I)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( addMInt( LoadAddr, mi(64, I)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( addMInt( LoadAddr, mi(64, I)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( addMInt( LoadAddr, mi(64, I)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( addMInt( LoadAddr, mi(64, I)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) - -"AF" |-> xorMInt( xorMInt( extractMInt( extractMInt(addMInt( LoadAddr, mi(64, I)), 32, 64), 27, 28), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( addMInt( LoadAddr, mi(64, I)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) - -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( addMInt( LoadAddr, mi(64, I)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) - -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( addMInt( LoadAddr, mi(64, I)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2) - -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( addMInt( LoadAddr, mi(64, I)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( addMInt( LoadAddr, mi(64, I)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( addMInt( LoadAddr, mi(64, I)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) - ) - - ... L |-> LoadAddr:PointerVal ... -endmodule diff --git a/semantics/memoryInstructions/movq_m64_label.k b/semantics/memoryInstructions/movq_m64_label.k deleted file mode 100644 index b8ac2c543..000000000 --- a/semantics/memoryInstructions/movq_m64_label.k +++ /dev/null @@ -1,30 +0,0 @@ -// Autogenerated using stratification. -requires "x86-configuration.k" - -module MOVQ-M64-LABEL - imports X86-CONFIGURATION - - rule - execinstr (movq:Opcode $ L:X86Id, M:Mem, .Operands) => execinstr (movq:Opcode $ L:X86Id + 0, M, .Operands) - ... - - context execinstr(movq:Opcode $ L:X86Id + I:Int, HOLE:Mem, .Operands) [result(MemOffset)] - - rule - execinstr (movq:Opcode $ L:X86Id + I:Int, memOffset( MemOff:MInt):MemOffset, .Operands) => - - storeToMemory( - ptr( - getMemLoc(PV), - mi(64, svalueMInt( - addMInt( - extractMInt( getMIntVal(PV), 32, 64), mi(32, I) - )))), - MemOff, - 64 - ) - - ... - RSMap:Map - ... L |-> PV:PointerVal ... -endmodule diff --git a/semantics/systemInstructions/callq_label.k b/semantics/systemInstructions/callq_label.k deleted file mode 100644 index 3d9f0a6c8..000000000 --- a/semantics/systemInstructions/callq_label.k +++ /dev/null @@ -1,15 +0,0 @@ -requires "x86-configuration.k" - - -module CALLQ-LABEL - imports X86-CONFIGURATION - - rule - execinstr (call LabelId:X86Id, .Operands) => - storeToMemory({RSMap["RIP"]}:>MInt, subMInt(getRegisterValue(%rsp, RSMap), mi(64, 8)), 64) - ~> decRSPInBytes(8) - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... -endmodule diff --git a/semantics/systemInstructions/ja_label.k b/semantics/systemInstructions/ja_label.k deleted file mode 100644 index c6cec1bb1..000000000 --- a/semantics/systemInstructions/ja_label.k +++ /dev/null @@ -1,23 +0,0 @@ -requires "x86-configuration.k" - - -module JA-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (ja LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) - andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) - - rule - execinstr (ja LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) - orBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) -endmodule diff --git a/semantics/systemInstructions/ja_rel32.k b/semantics/systemInstructions/ja_rel32.k index 5623ff99d..7edfdbd8f 100644 --- a/semantics/systemInstructions/ja_rel32.k +++ b/semantics/systemInstructions/ja_rel32.k @@ -1,24 +1,10 @@ requires "x86-configuration.k" - module JA-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (ja Imm32:Imm, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> - addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, - 32, 64)))) - - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) - andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) - - rule - execinstr (ja LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) - orBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + rule execinstr (ja Imm32:Imm, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jae_label.k b/semantics/systemInstructions/jae_label.k deleted file mode 100644 index 4c4b9bbd5..000000000 --- a/semantics/systemInstructions/jae_label.k +++ /dev/null @@ -1,21 +0,0 @@ -requires "x86-configuration.k" - - -module JAE-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jae LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) - - rule - execinstr (jae LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) -endmodule diff --git a/semantics/systemInstructions/jb_label.k b/semantics/systemInstructions/jb_label.k deleted file mode 100644 index 8925ed263..000000000 --- a/semantics/systemInstructions/jb_label.k +++ /dev/null @@ -1,21 +0,0 @@ -requires "x86-configuration.k" - - -module JB-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jb LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) - - rule - execinstr (jb LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) -endmodule diff --git a/semantics/systemInstructions/jbe_label.k b/semantics/systemInstructions/jbe_label.k deleted file mode 100644 index a9899dc3e..000000000 --- a/semantics/systemInstructions/jbe_label.k +++ /dev/null @@ -1,23 +0,0 @@ -requires "x86-configuration.k" - - -module JBE-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jbe LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) - orBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) - - rule - execinstr (jbe LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) - andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) -endmodule diff --git a/semantics/systemInstructions/jc_label.k b/semantics/systemInstructions/jc_label.k deleted file mode 100644 index 1f1c02d3d..000000000 --- a/semantics/systemInstructions/jc_label.k +++ /dev/null @@ -1,21 +0,0 @@ -requires "x86-configuration.k" - - -module JC-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jc LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) - - rule - execinstr (jc LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) -endmodule diff --git a/semantics/systemInstructions/je_label.k b/semantics/systemInstructions/je_label.k deleted file mode 100644 index f02240895..000000000 --- a/semantics/systemInstructions/je_label.k +++ /dev/null @@ -1,21 +0,0 @@ -requires "x86-configuration.k" - - -module JE-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (je LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) - - rule - execinstr (je LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) -endmodule diff --git a/semantics/systemInstructions/jecxz_label.k b/semantics/systemInstructions/jecxz_label.k deleted file mode 100644 index 1c27aa8f8..000000000 --- a/semantics/systemInstructions/jecxz_label.k +++ /dev/null @@ -1,21 +0,0 @@ -requires "x86-configuration.k" - - -module JECXZ-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jecxz LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires eqMInt(getRegisterValue(%ecx, RSMap), mi(32, 0)) - - rule - execinstr (jecxz LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires notBool eqMInt(getRegisterValue(%ecx, RSMap), mi(32, 0)) -endmodule diff --git a/semantics/systemInstructions/jg_label.k b/semantics/systemInstructions/jg_label.k deleted file mode 100644 index f5ff9a91a..000000000 --- a/semantics/systemInstructions/jg_label.k +++ /dev/null @@ -1,23 +0,0 @@ -requires "x86-configuration.k" -module JG-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jg LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) - andBool - eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) - - rule - execinstr (jg LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) - orBool - notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) -endmodule diff --git a/semantics/systemInstructions/jge_label.k b/semantics/systemInstructions/jge_label.k deleted file mode 100644 index 5cb333cc0..000000000 --- a/semantics/systemInstructions/jge_label.k +++ /dev/null @@ -1,19 +0,0 @@ -requires "x86-configuration.k" -module JGE-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jge LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) - - rule - execinstr (jge LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) -endmodule diff --git a/semantics/systemInstructions/jl_label.k b/semantics/systemInstructions/jl_label.k deleted file mode 100644 index 929b56fec..000000000 --- a/semantics/systemInstructions/jl_label.k +++ /dev/null @@ -1,19 +0,0 @@ -requires "x86-configuration.k" -module JL-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jl LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) - - rule - execinstr (jl LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) -endmodule diff --git a/semantics/systemInstructions/jle_label.k b/semantics/systemInstructions/jle_label.k deleted file mode 100644 index b186bb90a..000000000 --- a/semantics/systemInstructions/jle_label.k +++ /dev/null @@ -1,23 +0,0 @@ -requires "x86-configuration.k" -module JLE-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jle LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) - orBool - (notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) - - rule - execinstr (jle LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) - andBool - eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) -endmodule diff --git a/semantics/systemInstructions/jmp_label.k b/semantics/systemInstructions/jmp_label.k deleted file mode 100644 index 30245b395..000000000 --- a/semantics/systemInstructions/jmp_label.k +++ /dev/null @@ -1,14 +0,0 @@ -requires "x86-configuration.k" - - -module JMPQ-LABEL - imports X86-CONFIGURATION - - rule - execinstr (jmp LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - -endmodule diff --git a/semantics/systemInstructions/jna_label.k b/semantics/systemInstructions/jna_label.k deleted file mode 100644 index 3eddc8f65..000000000 --- a/semantics/systemInstructions/jna_label.k +++ /dev/null @@ -1,21 +0,0 @@ -requires "x86-configuration.k" - - -module JNA-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jna LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) orBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) - - rule - execinstr (jna LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) andBool notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) -endmodule diff --git a/semantics/systemInstructions/jnae_label.k b/semantics/systemInstructions/jnae_label.k deleted file mode 100644 index d7d881593..000000000 --- a/semantics/systemInstructions/jnae_label.k +++ /dev/null @@ -1,21 +0,0 @@ -requires "x86-configuration.k" - - -module JNAE-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jnae LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) - - rule - execinstr (jnae LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) -endmodule diff --git a/semantics/systemInstructions/jnb_label.k b/semantics/systemInstructions/jnb_label.k deleted file mode 100644 index 28576fb3c..000000000 --- a/semantics/systemInstructions/jnb_label.k +++ /dev/null @@ -1,21 +0,0 @@ -requires "x86-configuration.k" - - -module JNB-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jnb LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) - - rule - execinstr (jnb LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) -endmodule diff --git a/semantics/systemInstructions/jnbe_label.k b/semantics/systemInstructions/jnbe_label.k deleted file mode 100644 index d432d8626..000000000 --- a/semantics/systemInstructions/jnbe_label.k +++ /dev/null @@ -1,22 +0,0 @@ -requires "x86-configuration.k" - - -module JNBE-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jnbe LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) - - rule - execinstr (jnbe LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) - orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) -endmodule diff --git a/semantics/systemInstructions/jnc_label.k b/semantics/systemInstructions/jnc_label.k deleted file mode 100644 index dc21dcff9..000000000 --- a/semantics/systemInstructions/jnc_label.k +++ /dev/null @@ -1,21 +0,0 @@ -requires "x86-configuration.k" - - -module JNC-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jnc LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) - - rule - execinstr (jnc LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) -endmodule diff --git a/semantics/systemInstructions/jne_label.k b/semantics/systemInstructions/jne_label.k deleted file mode 100644 index d244a1171..000000000 --- a/semantics/systemInstructions/jne_label.k +++ /dev/null @@ -1,21 +0,0 @@ -requires "x86-configuration.k" - - -module JNE-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jne LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) - - rule - execinstr (jne LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) -endmodule diff --git a/semantics/systemInstructions/jng_label.k b/semantics/systemInstructions/jng_label.k deleted file mode 100644 index f4c108d16..000000000 --- a/semantics/systemInstructions/jng_label.k +++ /dev/null @@ -1,21 +0,0 @@ -requires "x86-configuration.k" - - -module JNG-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jng LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) orBool notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) - - rule - execinstr (jng LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) andBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) -endmodule diff --git a/semantics/systemInstructions/jnge_label.k b/semantics/systemInstructions/jnge_label.k deleted file mode 100644 index dc117749e..000000000 --- a/semantics/systemInstructions/jnge_label.k +++ /dev/null @@ -1,21 +0,0 @@ -requires "x86-configuration.k" - - -module JNGE-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jnge LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) - - rule - execinstr (jnge LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) -endmodule diff --git a/semantics/systemInstructions/jnl_label.k b/semantics/systemInstructions/jnl_label.k deleted file mode 100644 index a7de0993d..000000000 --- a/semantics/systemInstructions/jnl_label.k +++ /dev/null @@ -1,21 +0,0 @@ -requires "x86-configuration.k" - - -module JNL-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jnl LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) - - rule - execinstr (jnl LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) -endmodule diff --git a/semantics/systemInstructions/jnle_label.k b/semantics/systemInstructions/jnle_label.k deleted file mode 100644 index 3efc2cfc8..000000000 --- a/semantics/systemInstructions/jnle_label.k +++ /dev/null @@ -1,21 +0,0 @@ -requires "x86-configuration.k" - - -module JNLE-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jnle LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) - - rule - execinstr (jnle LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires notBool eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) orBool notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) -endmodule diff --git a/semantics/systemInstructions/jno_label.k b/semantics/systemInstructions/jno_label.k deleted file mode 100644 index ba1651a5e..000000000 --- a/semantics/systemInstructions/jno_label.k +++ /dev/null @@ -1,21 +0,0 @@ -requires "x86-configuration.k" - - -module JNO-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jno LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires eqMInt({RSMap["OF"]}:>MInt, mi(1, 0)) - - rule - execinstr (jno LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires notBool eqMInt({RSMap["OF"]}:>MInt, mi(1, 0)) -endmodule diff --git a/semantics/systemInstructions/jnp_label.k b/semantics/systemInstructions/jnp_label.k deleted file mode 100644 index 48535e052..000000000 --- a/semantics/systemInstructions/jnp_label.k +++ /dev/null @@ -1,21 +0,0 @@ -requires "x86-configuration.k" - - -module JNP-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jnp LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) - - rule - execinstr (jnp LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires notBool eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) -endmodule diff --git a/semantics/systemInstructions/jns_label.k b/semantics/systemInstructions/jns_label.k deleted file mode 100644 index dd99ec644..000000000 --- a/semantics/systemInstructions/jns_label.k +++ /dev/null @@ -1,21 +0,0 @@ -requires "x86-configuration.k" - - -module JNS-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jns LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) - - rule - execinstr (jns LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires eqMInt({RSMap["SF"]}:>MInt, mi(1, 1)) -endmodule diff --git a/semantics/systemInstructions/jnz_label.k b/semantics/systemInstructions/jnz_label.k deleted file mode 100644 index 14b7714f5..000000000 --- a/semantics/systemInstructions/jnz_label.k +++ /dev/null @@ -1,21 +0,0 @@ -requires "x86-configuration.k" - - -module JNZ-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jnz LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) - - rule - execinstr (jnz LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) -endmodule diff --git a/semantics/systemInstructions/jo_label.k b/semantics/systemInstructions/jo_label.k deleted file mode 100644 index ee4cce474..000000000 --- a/semantics/systemInstructions/jo_label.k +++ /dev/null @@ -1,21 +0,0 @@ -requires "x86-configuration.k" - - -module JO-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jo LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires eqMInt({RSMap["OF"]}:>MInt, mi(1, 1)) - - rule - execinstr (jo LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires notBool eqMInt({RSMap["OF"]}:>MInt, mi(1, 1)) -endmodule diff --git a/semantics/systemInstructions/jp_label.k b/semantics/systemInstructions/jp_label.k deleted file mode 100644 index d77fed5c3..000000000 --- a/semantics/systemInstructions/jp_label.k +++ /dev/null @@ -1,21 +0,0 @@ -requires "x86-configuration.k" - - -module JP-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jp LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 1)) - - rule - execinstr (jp LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) -endmodule diff --git a/semantics/systemInstructions/jpe_label.k b/semantics/systemInstructions/jpe_label.k deleted file mode 100644 index d4b4f3296..000000000 --- a/semantics/systemInstructions/jpe_label.k +++ /dev/null @@ -1,21 +0,0 @@ -requires "x86-configuration.k" - - -module JPE-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jpe LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 1)) - - rule - execinstr (jpe LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) -endmodule diff --git a/semantics/systemInstructions/jpo_label.k b/semantics/systemInstructions/jpo_label.k deleted file mode 100644 index 9ecb2dffd..000000000 --- a/semantics/systemInstructions/jpo_label.k +++ /dev/null @@ -1,21 +0,0 @@ -requires "x86-configuration.k" - - -module JPO-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jpo LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) - - rule - execinstr (jpo LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires notBool eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) -endmodule diff --git a/semantics/systemInstructions/jrcxz_label.k b/semantics/systemInstructions/jrcxz_label.k deleted file mode 100644 index 4fc679959..000000000 --- a/semantics/systemInstructions/jrcxz_label.k +++ /dev/null @@ -1,21 +0,0 @@ -requires "x86-configuration.k" - - -module JRCXZ-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jrcxz LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires eqMInt(getRegisterValue(%rcx, RSMap), mi(64, 0)) - - rule - execinstr (jrcxz LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires notBool eqMInt(getRegisterValue(%rcx, RSMap), mi(64, 0)) -endmodule diff --git a/semantics/systemInstructions/js_label.k b/semantics/systemInstructions/js_label.k deleted file mode 100644 index a064ef25e..000000000 --- a/semantics/systemInstructions/js_label.k +++ /dev/null @@ -1,21 +0,0 @@ -requires "x86-configuration.k" - - -module JS-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (js LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires eqMInt({RSMap["SF"]}:>MInt, mi(1, 1)) - - rule - execinstr (js LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) -endmodule diff --git a/semantics/systemInstructions/jz_label.k b/semantics/systemInstructions/jz_label.k deleted file mode 100644 index fadfebbb3..000000000 --- a/semantics/systemInstructions/jz_label.k +++ /dev/null @@ -1,21 +0,0 @@ -requires "x86-configuration.k" - - -module JZ-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jz LabelId:X86Id, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> Target)) - - ... LabelId |-> Target ... - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) - - rule - execinstr (jz LabelId:X86Id, .Operands) => . - ... - RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) -endmodule diff --git a/semantics/systemInstructions/loop_label.k b/semantics/systemInstructions/loop_label.k deleted file mode 100644 index 3beb71109..000000000 --- a/semantics/systemInstructions/loop_label.k +++ /dev/null @@ -1,33 +0,0 @@ -requires "x86-configuration.k" - - -module LOOP-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (loop LabelId:X86Id, .Operands) => execinstr (loop LabelId, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) - ... - RSMap - - rule - execinstr (loop LabelId:X86Id, Count:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, - ("RIP" |-> Target) - ("RCX" |-> Count) - ) - - ... LabelId |-> Target ... - requires notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) - - rule - execinstr (loop LabelId:X86Id, Count:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, - ("RCX" |-> Count) - ) - - requires eqMInt(Count, mi(bitwidthMInt(Count), 0)) - -endmodule diff --git a/semantics/systemInstructions/loope_label.k b/semantics/systemInstructions/loope_label.k deleted file mode 100644 index 2bbae35c9..000000000 --- a/semantics/systemInstructions/loope_label.k +++ /dev/null @@ -1,35 +0,0 @@ -requires "x86-configuration.k" - - -module LOOPE-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (loope LabelId:X86Id, .Operands) => execinstr (loope LabelId, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) - ... - RSMap - - rule - execinstr (loope LabelId:X86Id, Count:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, - ("RIP" |-> Target) - ("RCX" |-> Count) - ) - - ... LabelId |-> Target ... - requires notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) - andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) - - rule - execinstr (loope LabelId:X86Id, Count:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, - ("RCX" |-> Count) - ) - - requires eqMInt(Count, mi(bitwidthMInt(Count), 0)) - orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) - -endmodule diff --git a/semantics/systemInstructions/loopne_label.k b/semantics/systemInstructions/loopne_label.k deleted file mode 100644 index c940f161b..000000000 --- a/semantics/systemInstructions/loopne_label.k +++ /dev/null @@ -1,35 +0,0 @@ -requires "x86-configuration.k" - - -module LOOPNE-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (loopne LabelId:X86Id, .Operands) => execinstr (loope LabelId, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) - ... - RSMap - - rule - execinstr (loopne LabelId:X86Id, Count:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, - ("RIP" |-> Target) - ("RCX" |-> Count) - ) - - ... LabelId |-> Target ... - requires notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) - andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) - - rule - execinstr (loopne LabelId:X86Id, Count:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, - ("RCX" |-> Count) - ) - - requires eqMInt(Count, mi(bitwidthMInt(Count), 0)) - orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) - -endmodule diff --git a/semantics/systemInstructions/loopnz_label.k b/semantics/systemInstructions/loopnz_label.k deleted file mode 100644 index 2500886bc..000000000 --- a/semantics/systemInstructions/loopnz_label.k +++ /dev/null @@ -1,35 +0,0 @@ -requires "x86-configuration.k" - - -module LOOPNE-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (loopnz LabelId:X86Id, .Operands) => execinstr (loopnz LabelId, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) - ... - RSMap - - rule - execinstr (loopnz LabelId:X86Id, Count:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, - ("RIP" |-> Target) - ("RCX" |-> Count) - ) - - ... LabelId |-> Target ... - requires notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) - andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) - - rule - execinstr (loopnz LabelId:X86Id, Count:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, - ("RCX" |-> Count) - ) - - requires eqMInt(Count, mi(bitwidthMInt(Count), 0)) - orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) - -endmodule diff --git a/semantics/systemInstructions/loopz_label.k b/semantics/systemInstructions/loopz_label.k deleted file mode 100644 index 97b9d91a0..000000000 --- a/semantics/systemInstructions/loopz_label.k +++ /dev/null @@ -1,35 +0,0 @@ -requires "x86-configuration.k" - - -module LOOPE-LABEL - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (loopz LabelId:X86Id, .Operands) => execinstr (loopz LabelId, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) - ... - RSMap - - rule - execinstr (loopz LabelId:X86Id, Count:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, - ("RIP" |-> Target) - ("RCX" |-> Count) - ) - - ... LabelId |-> Target ... - requires notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) - andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) - - rule - execinstr (loopz LabelId:X86Id, Count:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, - ("RCX" |-> Count) - ) - - requires eqMInt(Count, mi(bitwidthMInt(Count), 0)) - orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) - -endmodule diff --git a/semantics/x86-abstract-semantics.k b/semantics/x86-abstract-semantics.k index 268c90983..1e9a1dd82 100644 --- a/semantics/x86-abstract-semantics.k +++ b/semantics/x86-abstract-semantics.k @@ -1,96 +1,14 @@ require "x86-configuration.k" +require "hex-token.k" module X86-ABSTRACT-SEMANTICS imports X86-CONFIGURATION + imports HEX-TOKEN /*@ Function related to null checks */ - rule isPointerValNull(null) => true - rule isPointerValNull(ptr(Loc:MemLoc, Offs:MInt)) - => - isMemLocNull(Loc) andBool eqMInt(Offs, mi(bitwidthMInt(Offs), 0)) - - /*@ - Redefining functions over PointerVal - */ - rule getMemLoc(ptr(L:MemLoc, MI:MInt)) => L - rule getMIntVal(ptr(L:MemLoc, MI:MInt)) => MI - - syntax MInt ::= "convertPV" "(" MInt ")" [function] - rule convertPV(PV:PointerVal) => getMIntVal(PV) - rule convertPV(MI:MInt) => MI [owise] - - //rule mi(W:Int, svalueMInt(PV:PointerVal)) => ptr(getMemLoc(PV), mi(W, svalueMInt(getMIntVal(PV)))) - - //negMInt - rule negMInt(PV:PointerVal) => - ptr (getMemLoc(PV), negMInt(getMIntVal(PV))) - - //lshrMInt - rule lshrMInt(PV:PointerVal, I:Int) => - ptr (getMemLoc(PV), lshrMInt(getMIntVal(PV), I)) - - //shlMInt - rule shlMInt(PV:PointerVal, I:Int) => - ptr (getMemLoc(PV), shlMInt(getMIntVal(PV), I)) - - // Arithmetic:add - rule addMInt(PV:PointerVal, MI:MInt) => - ptr( getMemLoc(PV), addMInt(convertPV(PV), convertPV(MI))) - rule addMInt(MI:MInt, PV:PointerVal) => - ptr( getMemLoc(PV), addMInt(convertPV(MI), convertPV(PV))) - - // Arithmetic:and - rule andMInt(PV:PointerVal, MI:MInt) => - ptr( getMemLoc(PV), andMInt(convertPV(PV), convertPV(MI))) - rule andMInt(MI:MInt, PV:PointerVal) => - ptr( getMemLoc(PV), andMInt(convertPV(MI), convertPV(PV))) - - // Mul - rule mulMInt(PV:PointerVal, MI:MInt) => - ptr( getMemLoc(PV), mulMInt(convertPV(PV), convertPV(MI))) - rule mulMInt(MI:MInt, PV:PointerVal) => - ptr( getMemLoc(PV), mulMInt(convertPV(MI), convertPV(PV))) - - // Xor - rule xorMInt(PV:PointerVal, MI:MInt) => - ptr( getMemLoc(PV), xorMInt(convertPV(PV), convertPV(MI))) - rule xorMInt(MI:MInt, PV:PointerVal) => - ptr( getMemLoc(PV), xorMInt(convertPV(MI), convertPV(PV))) - - // Sub - rule subMInt(PV:PointerVal, MI:MInt) => - ptr( getMemLoc(PV), subMInt(convertPV(PV), convertPV(MI))) - - // Bitwidth - //rule bitwidthMInt(ptr(L:MemLoc, MI:MInt)) => bitwidthMInt(MI) - rule bitwidthMInt(PV:PointerVal) => bitwidthMInt(getMIntVal(PV)) - - // Extract - //rule extractMInt(ptr(L:MemLoc, MI:MInt), S:Int, E:Int) => ptr(L, extractMInt(MI, S, E)) - rule extractMInt(PV:PointerVal, S:Int, E:Int) => - ptr(getMemLoc(PV), extractMInt(getMIntVal(PV), S, E)) - - // Concatenate - rule concatenateMInt(PV:PointerVal, MI:MInt) => - ptr( getMemLoc(PV), concatenateMInt(convertPV(PV), convertPV(MI))) - rule concatenateMInt(MI:MInt, PV:PointerVal) => - ptr( getMemLoc(PV), concatenateMInt(convertPV(MI), convertPV(PV))) - - - // eqMInt - rule eqMInt(ptr(L:MemLoc, MI1:MInt), MI2:MInt) => eqMInt(MI1, MI2) - rule eqMInt(MI1:MInt, ptr(L:MemLoc, MI2:MInt)) => eqMInt(MI1, MI2) - rule eqMInt(ptr(L:MemLoc, MI1:MInt), ptr(L:MemLoc, MI2:MInt)) => - eqMInt(MI1, MI2) - - // Sign Extension - //rule mi(W:Int, svalueMInt(PV:PointerVal)) => - // ptr(getMemLoc(PV), mi(W, svalueMInt(getMIntVal(PV)))) - - // Avoid bloating - //rule ptr(L:MemLoc, ptr(L:MemLoc, M:MInt)) => ptr(L, M) + rule isPointerValNull(Addr:MInt) => uvalueMInt(Addr) ==Int 0 /*@ X86-64 mnemonic allows the following ways of computing memory offsets. @@ -111,71 +29,25 @@ module X86-ABSTRACT-SEMANTICS instrcution. */ - // rip - rule L:X86Id (%rip) => L:X86Id + 0 (%rip) ... - rule L:X86Id + I:Int (%rip) => - memOffset( ptr(getMemLoc(LoadAddr), addMInt( getMIntVal(LoadAddr), mi(bitwidthMInt(LoadAddr), I)))) - ... - RSMap - ... L |-> LoadAddr:PointerVal ... - // (%r64) rule (R1:R64):Mem => 0 (R1:R64) ... - rule I:Int (R1:R64):Mem => - memOffset( addMInt(mi(64, I), addMInt(getRegisterValue(R1, RSMap), mulMInt(mi(64, 0), mi(64, 1))))) - ... - RSMap - - rule L:X86Id (R1:R64):Mem => L:X86Id + 0 (R1:R64):Mem ... - rule L:X86Id + I:Int (R1:R64):Mem => - memOffset( addMInt(addMInt(LoadAddr, mi(bitwidthMInt(LoadAddr), I)), addMInt(getRegisterValue(R1, RSMap), mulMInt(mi(64, 0), mi(64, 1))))) - ... - RSMap - ... L |-> LoadAddr:PointerVal ... + rule I:Int (R1:R64):Mem => memOffset( addMInt(mi(64, I), getRegisterValue(R1, RSMap))) ... + RSMap // (, %r64) rule (, R2:R64):Mem => 0 (, R2, 1) ... rule I:Int (, R2:R64):Mem => I (, R2, 1) ... rule ( , R2:R64, S:Int):Mem => 0 (, R2, S) ... rule I:Int (, R2:R64):Mem => I (, R2, 1) ... - rule I:Int (, R2:R64, S:Int):Mem => - memOffset( addMInt(mi(64, I), addMInt(mi(64, 0), mulMInt(getRegisterValue(R2, RSMap), mi(64, S))))) - ... - RSMap - - rule L:X86Id (, R2:R64):Mem => L + 0 (, R2, 1) ... - rule L:X86Id ( , R2:R64, S:Int):Mem => L + 0 (, R2, S) ... - rule L:X86Id + I:Int (, R2:R64, S:Int):Mem => - memOffset( addMInt( - addMInt(LoadAddr, mi(bitwidthMInt(LoadAddr), I)), - addMInt(mi(64, 0), mulMInt(getRegisterValue(R2, RSMap), mi(64, S))))) - ... - RSMap - ... L |-> LoadAddr:PointerVal ... + rule I:Int (, R2:R64, S:Int):Mem => memOffset( addMInt(mi(64, I), mulMInt(getRegisterValue(R2, RSMap), mi(64, S)))) ... + RSMap // (%r64, %r64) rule (R1:R64, R2:R64):Mem => 0 (R1, R2, 1) ... rule (R1:R64, R2:R64, S:Int):Mem => 0 (R1, R2, S) ... rule I:Int (R1:R64, R2:R64):Mem => I (R1, R2, 1) ... - rule I:Int (R1:R64, R2:R64, S:Int):Mem => - memOffset( addMInt(mi(64, I), addMInt(getRegisterValue(R1, RSMap), mulMInt(getRegisterValue(R2, RSMap), mi(64, S))))) - ... - RSMap - - rule L:X86Id (R1:R64, R2:R64):Mem => L + 0 (R1, R2, 1) ... - rule L:X86Id (R1:R64, R2:R64, S:Int):Mem => L + 0 (R1, R2, S) ... - rule L:X86Id + I:Int (R1:R64, R2:R64):Mem => L + I (R1, R2, 1) ... - rule L:X86Id + I:Int (R1:R64, R2:R64, S:Int):Mem => - memOffset( addMInt( - addMInt(LoadAddr, mi(bitwidthMInt(LoadAddr), I)), - addMInt(getRegisterValue(R1, RSMap), mulMInt(getRegisterValue(R2, RSMap), mi(64, S))))) - ... - RSMap - ... L |-> LoadAddr:PointerVal ... - /*@ - Size of instructions. - rule getISize((OpC:Opcode OpR:Operands):Instruction) => 1 - */ + rule I:Int (R1:R64, R2:R64, S:Int):Mem => memOffset( addMInt(mi(64, I), addMInt(getRegisterValue(R1, RSMap), mulMInt(getRegisterValue(R2, RSMap), mi(64, S))))) ... + RSMap /*@ Reg to Regtstate keys @@ -434,13 +306,10 @@ module X86-ABSTRACT-SEMANTICS // Imm could be an Int rule handleImmediateWithSignExtend(($ I:Int):Imm, M:Int, N:Int) => signExtend(mi(M,I), N) - // Or a HexConstant: For hexconstants ike 0x800, we have to provide the substr 800 - // as an argument to String2Base - syntax String ::= HexConstant2String ( HexConstant ) [function, hook(STRING.token2string)] - //rule handleImmediateWithSignExtend($0x H:HexConstant, M:Int, N:Int) => - // signExtend(mi(M, String2Base(HexConstant2String(H), 16)), N) - rule handleImmediateWithSignExtend((H:HexConstant):Imm, M:Int, N:Int) => - signExtend(mi(M, String2Base(substrString(HexConstant2String(H), 3, lengthString(HexConstant2String(H))), 16)), N) + // Or a HexConstant: For hexconstants like 0x800, we have to provide the substr 800 + // as an argument to String2Base + rule handleImmediateWithSignExtend(($ H:HexConstant):Imm, M:Int, N:Int) => + signExtend(mi(M, HexConstant2Int(H)), N) /*@ Check if two registers are the same @@ -966,25 +835,5 @@ module X86-ABSTRACT-SEMANTICS #fi ) requires Count =/=Int (NumElems -Int 1) - - endmodule - - - - - - - - - - - - - - - - - - diff --git a/semantics/x86-abstract-syntax.k b/semantics/x86-abstract-syntax.k index 476a6c9e7..befb36710 100644 --- a/semantics/x86-abstract-syntax.k +++ b/semantics/x86-abstract-syntax.k @@ -1,8 +1,8 @@ +require "elf-syntax.k" require "x86-syntax.k" require "x86-memory.k" module X86-ABSTRACT-SORTS syntax PointerVal - syntax NullVal endmodule module X86-ABSTRACT-SYNTAX @@ -13,25 +13,15 @@ module X86-ABSTRACT-SYNTAX imports COMMON-MEMORY-SORTS imports X86-ABSTRACT-SORTS - - syntax PointerVal ::= ptr(MemLoc, /* offset in bits */ MInt) - syntax MInt ::= PointerVal - syntax NullVal ::= "null" - syntax PointerVal ::= NullVal + syntax PointerVal ::= MInt syntax Bool ::= isPointerValNull(PointerVal) [function] - syntax MemLoc ::= getMemLoc(PointerVal) [function] - syntax MInt ::= getMIntVal(PointerVal) [function] + + syntax ROMSegment ::= StringSegment(Int, Int, String) /*@ Sorts of config cell entities */ syntax CodeInMemory ::= code(/*PointerVal -> storeInstr(Instruction)*/ Map) - //syntax CodeInMemory ::= code(/*iloc(MInt) -> storeInstr(Instruction)*/ Map) - //syntax Int ::= iloc(MInt) - syntax StackBaseInfo ::= stackBaseInfo(/*MemLoc, Intial Offset*/ K, K) - syntax ROBaseInfo ::= roBaseInfo(/*MemLoc, Intial Offset, Next location*/ K, K, K) - syntax DataBaseInfo ::= dataBaseInfo(/*MemLoc, Intial Offset, Next location*/ K, K, K) - syntax BssBaseInfo ::= bssBaseInfo(/*MemLoc, Intial Offset, Next location*/ K, K, K) syntax Abstractinstruction ::= storedInstr(Instruction) syntax Abstractinstruction ::= execinstr(Instruction) @@ -55,8 +45,6 @@ module X86-ABSTRACT-SYNTAX Subregs to Regs */ syntax Register ::= convSubRegsToRegs(Register) [function] - //syntax R64 ::= convSubRegsToRegs(Register) [function] - //syntax Ymm ::= convSubRegsToRegs(Register) [function] /*@ Reg to Regtstate keys diff --git a/semantics/x86-commom-memory-clib-interface.k b/semantics/x86-commom-memory-clib-interface.k index fb4e820e1..315943690 100644 --- a/semantics/x86-commom-memory-clib-interface.k +++ b/semantics/x86-commom-memory-clib-interface.k @@ -1,4 +1,3 @@ -requires "common-memory.k" requires "common-utils.k" requires "common-error.k" requires "library/common-c-library.k" @@ -8,7 +7,6 @@ module COMMON-CONFIGURATION endmodule module COMMON-MEMORY-CLIB-INTERFACE - imports COMMON-MEMORY imports COMMON-UTILS imports COMMON-C-LIBRARY endmodule diff --git a/semantics/x86-configuration.k b/semantics/x86-configuration.k index 7658365f1..2f345a11a 100644 --- a/semantics/x86-configuration.k +++ b/semantics/x86-configuration.k @@ -1,4 +1,5 @@ require "x86-syntax.k" +require "elf-syntax.k" require "x86-abstract-syntax.k" require "common-memory.k" require "x86-memory.k" @@ -9,44 +10,32 @@ module X86-CONFIGURATION imports X86-SYNTAX imports X86-ABSTRACT-SYNTAX imports COMMON-MEMORY-CONFIGURATION - imports X86-MEMORY-SYNTAX imports X86-INIT-SYNTAX imports MINT-WRAPPER-SYNTAX imports X86-LOADER-SYNTAX imports COMMON-C-LIBRARY-CONFIGURATION + imports ELF-SYNTAX + imports ELF-LOADER - // configuration configuration -//initEnvironment(ListItem("a.out") ListItem("HelloWorld!") .List) ~> //initRegisters($REGV:RegValPairList) ~> //initEnvironment($ARGV:List) ~> initEnvironment(.List) ~> - $PGM:Instructions ~> - loadEntryPoint ~> + $PGM:Elf ~> inforegisters ~> fetch - .Map - .Map - .Map - .Map - .K - mi(64, 0) - .K - "text" + + .Map + + mi(64, -1) - code( .Map ) - - - stackBaseInfo(.K, .K) - roBaseInfo(.K /* Alocation id*/, .K /*Base Pointer*/, .K /*Next Location*/ ) - dataBaseInfo(.K , .K , .K ) - bssBaseInfo(.K , .K , .K ) - + .Map + .List @@ -106,7 +95,6 @@ module X86-CONFIGURATION regstatequeue: For testing purposes */ - // .List .List 0 diff --git a/semantics/x86-env-init.k b/semantics/x86-env-init.k index 8e6858467..ea82b22fa 100644 --- a/semantics/x86-env-init.k +++ b/semantics/x86-env-init.k @@ -36,7 +36,7 @@ module X86-INIT 2. Setting up argc and argv in environment memory. */ rule initEnvironment(L:List) => - //allocateStackMemory(64, 16 *Int 8) ~> allocateROMemory(64, 16 *Int 8) ~> initReturnFromEntryFunction ~> initArgc(mySize(L)) ~> initArgv(L) + //allocateStackMemory(64, 16 *Int 8) ~> allocateROMemory(64, 16 *Int 8) ~> initReturnFromEntryFunction ~> initArgc(size(L)) ~> initArgv(L) allocateStackMemory(1024, 16 *Int 8) ~> allocateROMemory(256, 16 *Int 8) ~> allocateDataMemory(256, 16 *Int 8) ~> @@ -91,13 +91,8 @@ module X86-INIT Store a fake return adress mi(64, -1) which signals program executaion halt. */ syntax KItem ::= "initReturnFromEntryFunction" - rule initReturnFromEntryFunction => storeToMemory(mi(64, -1), ptr(L, BaseOffset), 64) - ... - stackBaseInfo( L:MemLoc, BaseOffset:MInt) - - syntax Int ::= mySize(List) [function] - rule mySize(.List) => 0 - rule mySize(ListItem(_) L:List) => mySize(L) +Int 1 + rule initReturnFromEntryFunction => storeToMemory(mi(64, -1), BaseOffset, 64) ... + stackBaseInfo(BaseOffset:MInt) /*@ Initialize argc diff --git a/semantics/x86-fetch-execute.k b/semantics/x86-fetch-execute.k index b3f6583c0..85489dfba 100644 --- a/semantics/x86-fetch-execute.k +++ b/semantics/x86-fetch-execute.k @@ -8,10 +8,8 @@ module X86-FETCH-EXECUTE */ rule fetch => execinstr(OpC OpR) ~> inforegisters ~> fetch ... - //code(iloc(PC) |-> storedInstr(OpC OpR) _:Map) code(PV:PointerVal |-> storedInstr(OpC OpR) _:Map) - //... "RIP" |-> ( PC => addMInt(PC, mi(64, 1))) ... - ... "RIP" |-> ( PV => addMInt(PV, ptr(getMemLoc(PV), mi(64, 1)))) ... + ... "RIP" |-> ( PV => addMInt(PV, mi(64, 1))) ... /*@ After execution of last instrcution, no more fecthes. @@ -22,7 +20,6 @@ module X86-FETCH-EXECUTE fetch => . ... code (CMap) RSMap - //requires notBool iloc( {RSMap["RIP"]}:>MInt ) in_keys ( CMap ) requires notBool {RSMap["RIP"]}:>PointerVal in_keys ( CMap ) /*@ @@ -30,12 +27,10 @@ module X86-FETCH-EXECUTE */ rule inforegisters => . ... - // ... .List => ListItem(RSMap) ListItem(FMap) ... .List => ListItem(RSMap) RSMap FMap:Map code (CMap) - //requires iloc( {RSMap["RIP"]}:>MInt ) in_keys ( CMap ) requires {RSMap["RIP"]}:>PointerVal in_keys ( CMap ) rule @@ -44,7 +39,6 @@ module X86-FETCH-EXECUTE code (CMap) RSMap FMap:Map - //requires notBool iloc( {RSMap["RIP"]}:>MInt ) in_keys ( CMap ) requires notBool {RSMap["RIP"]}:>PointerVal in_keys ( CMap ) /*@ diff --git a/semantics/x86-mint-wrapper.k b/semantics/x86-mint-wrapper.k index 534d72556..5e3eea805 100644 --- a/semantics/x86-mint-wrapper.k +++ b/semantics/x86-mint-wrapper.k @@ -441,7 +441,7 @@ module MINT-WRAPPER /*@ Covert Ints to MInts. */ - rule convertIntsToMInts(I Is, W) => mi(I, W) convertIntsToMInts(Is, W) + rule convertIntsToMInts(I Is, W) => mi(W, I) convertIntsToMInts(Is, W) rule convertIntsToMInts(.Ints, _) => .MInts /*@ diff --git a/semantics/x86-semantics.k b/semantics/x86-semantics.k index cc4edbbe9..63444af99 100644 --- a/semantics/x86-semantics.k +++ b/semantics/x86-semantics.k @@ -3,11 +3,9 @@ require "x86-env-init.k" require "x86-fetch-execute.k" require "x86-abstract-semantics.k" require "x86-flag-checks.k" -//require "x86-verification-lemmas.k" require "x86-instructions-semantics.k" require "x86-memory.k" require "x86-mint-wrapper.k" -//require "common.k" require "x86-commom-memory-clib-interface.k" require "x86-builtin.k" require "x86-c-library.k" @@ -18,7 +16,6 @@ module X86-SEMANTICS imports X86-FETCH-EXECUTE imports X86-ABSTRACT-SEMANTICS imports X86-FLAG-CHECKS - //imports X86-VERIFICATION-LEMMAS imports X86-INSTRUCTIONS-SEMANTICS imports X86-MEMORY imports MINT-WRAPPER diff --git a/semantics/x86-syntax.k b/semantics/x86-syntax.k index 06feaa148..80961ba21 100644 --- a/semantics/x86-syntax.k +++ b/semantics/x86-syntax.k @@ -1,7 +1,8 @@ +require "hex-token.k" + module X86-SORT syntax Instructions syntax Instruction - syntax Label syntax HexConstant syntax Operands syntax MemOffset @@ -32,16 +33,13 @@ module X86-SYNTAX imports FLOAT imports STRING imports MINT - imports ID - imports MINT + imports HEX-TOKEN-SYNTAX /*@ The following captures the At&t syntax of x86 assembly. */ syntax Instructions ::= List{Instruction, ""} [klabel(instructionlist)] - syntax Instruction ::= Opcode Operands - | AssemblerDirective - | Label + syntax Instruction ::= Opcode Operands syntax Builtin ::= "putchar" [token] | "getchar" [token] @@ -74,45 +72,13 @@ module X86-SYNTAX | "free" [token] | "sqrt" [token] - syntax X86Id ::= Id - /*@ - Special symbols. - */ - syntax X86Id ::= "main" [token] - | "_start" [token] - | "stdout" [token] - - syntax AssemblerDirective ::= ".section" ".rodata" - | ".data" [token] - | ".text" - | ".bss" - | ".file" String - | ".globl" X86Id - | ".string" String - | ".ascii" String - | ".long" Int - | ".quad" Int - | ".quad" X86Id - | ".quad" X86Id "+" Int - | ".comm" X86Id "," Int "," Int - | ".zero" Int - | ".byte" Int - | ".value" Int - - syntax Label ::= X86Id ":" - - syntax HexConstant ::= r"$0x[0-9a-fA-F]+" [token] - syntax Operands ::= List{Operand, ","} [klabel(operandlist)] - syntax Operand ::= Imm - | Mem - | Register - | MemOffset - | X86Id - | Builtin - | "$" X86Id - | "$" X86Id "+" Int + syntax Operand ::= Imm + | Mem + | Register + | MemOffset + | Builtin /*@ * Adding Int and Float as operands helps in * testing float-conversion directly. @@ -126,16 +92,9 @@ module X86-SYNTAX * which requires MInt to be a subSort of Operand. */ | MInt -// | Mm -// | St -// | Memoffs -// | Sreg syntax MemOffset ::= memOffset ( MInt ) -//syntax Simpleoperand ::= Register | Imm | MemOffset -//syntax Operand ::= Simpleoperand - syntax R64OrRIP ::= R64 | Rip syntax Register ::= Rh @@ -148,11 +107,9 @@ module X86-SYNTAX | Mm | Sreg | St -// syntax Memoffs ::= Offset -// | Sreg ":" Offset + syntax Offset ::= Int - syntax Imm ::= "$" Int - | HexConstant + syntax Imm ::= "$" Int | "$" HexConstant /*@ @@ -160,55 +117,20 @@ module X86-SYNTAX * Hence making MemOffset a subsort of Mem. */ syntax Mem ::= MemOffset - syntax Mem ::= /*"(" Rip ")" - | X86Id "(" Rip ")" - | X86Id "+" Int "(" Rip ")" - //------------------------------------ - |*/ "(" R64OrRIP ")" + syntax Mem ::= "(" R64OrRIP ")" | Offset "(" R64OrRIP ")" - | X86Id "(" R64OrRIP ")" - | X86Id "+" Int "(" R64OrRIP ")" //------------------------------------ | "(" "," R64 "," Scale ")" | "(" "," R64 ")" | Offset "(" "," R64 "," Scale ")" | Offset "(" "," R64 ")" - | X86Id "(" "," R64 "," Scale ")" - | X86Id "(" "," R64 ")" - | X86Id "+" Int "(" "," R64 "," Scale ")" - | X86Id "+" Int "(" "," R64 ")" //------------------------------------ | "(" R64 "," R64 "," Scale ")" | "(" R64 "," R64 ")" | Offset "(" R64 "," R64 "," Scale ")" | Offset "(" R64 "," R64 ")" - | X86Id "(" R64 "," R64 "," Scale ")" - | X86Id "(" R64 "," R64 ")" - | X86Id "+" Int "(" R64 "," R64 "," Scale ")" - | X86Id "+" Int "(" R64 "," R64 ")" - // | Int ? How should we do this for absolute addressing? -// | Sreg ":" "(" R32 ")" -// | Sreg ":" "(" R64 ")" -// | Sreg ":" "(" Rip ")" -// | Sreg ":" Offset "(" R32 ")" -// | Sreg ":" Offset "(" R64 ")" -// | Sreg ":" Offset "(" Rip ")" -// | Sreg ":" "(" "," R32 "," Scale ")" -// | Sreg ":" "(" "," R64 "," Scale ")" -// | Sreg ":" "(" "," R32 ")" -// | Sreg ":" "(" "," R64 ")" -// | Sreg ":" Offset "(" "," R32 "," Scale ")" -// | Sreg ":" Offset "(" "," R64 "," Scale ")" -// | Sreg ":" Offset "(" "," R32 ")" -// | Sreg ":" Offset "(" "," R64 ")" -// | Sreg ":" "(" R32 "," R32 "," Scale ")" -// | Sreg ":" "(" R64 "," R64 "," Scale ")" -// | Sreg ":" "(" R32 "," R32 ")" -// | Sreg ":" "(" R64 "," R64 ")" -// | Sreg ":" Offset "(" R32 "," R32 "," Scale ")" -// | Sreg ":" Offset "(" R64 "," R64 "," Scale ")" -// | Sreg ":" Offset "(" R32 "," R32 ")" -// | Sreg ":" Offset "(" R64 "," R64 ")" + //------------------------------------ + | Offset /* For absolute addressing... not sure I like this solution */ syntax Rip ::= "%rip" [token] syntax Scale ::= Int From 54631d485dcb3bf945f9ed3163472da7e575831a Mon Sep 17 00:00:00 2001 From: andrew_miranti Date: Sat, 16 Feb 2019 17:59:24 -0600 Subject: [PATCH 07/15] Hello World Works! --- scripts/process_spec.pl | 9 +- semantics/a.out | Bin 0 -> 912672 bytes semantics/builtins.k | 32 + semantics/elf-loader.k | 8 +- semantics/elf-syntax.k | 6 +- semantics/elf_reader | Bin 0 -> 917520 bytes semantics/elf_reader.c | 212 + semantics/files-to-update.txt | 78 + semantics/helloworld.c | 4 + semantics/out.txt | 163279 ++++++++++++++++++ semantics/parser_script.sh | 4 + semantics/systemInstructions/callq_rel32.k | 20 +- semantics/test.c | 6 + semantics/x86-abstract-semantics.k | 3 +- semantics/x86-abstract-syntax.k | 17 - semantics/x86-builtin.k | 101 +- semantics/x86-c-library.k | 41 +- semantics/x86-configuration.k | 24 +- semantics/x86-env-init.k | 29 +- semantics/x86-fetch-execute.k | 82 +- semantics/x86-loader.k | 653 - semantics/x86-memory.k | 320 +- semantics/x86-mint-wrapper.k | 18 +- semantics/x86-semantics.k | 5 +- semantics/x86-syntax.k | 6 +- 25 files changed, 163864 insertions(+), 1093 deletions(-) create mode 100755 semantics/a.out create mode 100644 semantics/builtins.k create mode 100755 semantics/elf_reader create mode 100644 semantics/elf_reader.c create mode 100644 semantics/files-to-update.txt create mode 100644 semantics/helloworld.c create mode 100644 semantics/out.txt create mode 100755 semantics/parser_script.sh create mode 100644 semantics/test.c delete mode 100644 semantics/x86-loader.k diff --git a/scripts/process_spec.pl b/scripts/process_spec.pl index f8672e2ce..4a9e7c87c 100755 --- a/scripts/process_spec.pl +++ b/scripts/process_spec.pl @@ -30,7 +30,7 @@ BEGIN "$home/Github/strata-data/data-regs/instructions/"; my $script = "~/x86-semantics/scripts/process_spec.pl"; my $UTInstructionsPath = "underTestInstructions/"; - +my $DECODER_DIR = "/home/andrewmiranti/Documents/University/Grad/decoder"; # TEMPORARY my $help = ""; my $stratum = ""; my $readmod = ""; @@ -313,11 +313,16 @@ BEGIN execute("mkdir -p $UTInstructionsPath"); createSingleFileDefn(); execute("git status x86-instructions-semantics.k"); +# execute( +#"time kompile x86-semantics.k --syntax-module X86-SYNTAX --main-module X86-SEMANTICS --debug -v --backend $backend -I ~/Github/llvm-verified-backend/ -I ~/Github/llvm-verified-backend/common/x86-config/", +# 1 +# ); execute( -"time kompile x86-semantics.k --syntax-module X86-SYNTAX --main-module X86-SEMANTICS --debug -v --backend $backend -I ~/Github/llvm-verified-backend/ -I ~/Github/llvm-verified-backend/common/x86-config/", +"time kompile x86-semantics.k --syntax-module ELF-SYNTAX --main-module X86-SEMANTICS --debug -v --backend $backend -I . -I ./common/ -I $DECODER_DIR", 1 ); + exit(0); } diff --git a/semantics/a.out b/semantics/a.out new file mode 100755 index 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"fgets" [token] + | "gets" [token] + | "fseek" [token] + | "rewind" [token] + | "malloc" [token] + | "free" [token] + | "sqrt" [token] +endmodule diff --git a/semantics/elf-loader.k b/semantics/elf-loader.k index 093853328..a18548c1e 100644 --- a/semantics/elf-loader.k +++ b/semantics/elf-loader.k @@ -1,19 +1,21 @@ require "hex-token.k" require "elf-syntax.k" require "x86-configuration.k" +require "x86-syntax.k" module ELF-LOADER imports MINT imports ELF-SYNTAX imports HEX-TOKEN imports X86-CONFIGURATION + imports X86-SYNTAX rule Cs:Commands ; => Cs [structural] rule C:Command ; Cs:Commands => C ~> Cs [structural] rule .Commands => . [structural] rule Load(Base:HexConstant, Mem:HexConstant, Len:HexConstant) => . ... - ... (.List => ListItem(StringSegment(HexConstant2Int(Base), HexConstant2Int(Base) + HexConstant2Int(Len), HexConstant2StringNoPrefix(Mem)))) + ... (.List => ListItem(StringSegment(HexConstant2Int(Base), HexConstant2Int(Base) +Int HexConstant2Int(Len), HexConstant2StringNoPrefix(Mem)))) // TODO: This rule might be unwise. Right now the *parser* implicitly defines the entry point... should be the semantics job. rule Entry(E:HexConstant) => . ... @@ -22,6 +24,6 @@ module ELF-LOADER // TODO: Log these? Emit warnings? Halt? rule NamedSymbol(_, NotPresentInFile) => . ... - rule NamedSymbol(N:String, Addr:HexConstant) => . ... - SymMap => SymMap[N <- mi(64, HexConstant2Int(Addr))] + rule NamedSymbol(B:Builtin, Addr:HexConstant) => . ... + SymMap => SymMap[mi(64, HexConstant2Int(Addr)) <- B] endmodule diff --git a/semantics/elf-syntax.k b/semantics/elf-syntax.k index 9ffb52f26..354c05d22 100644 --- a/semantics/elf-syntax.k +++ b/semantics/elf-syntax.k @@ -1,14 +1,16 @@ +require "builtins.k" require "hex-token.k" module ELF-SYNTAX imports STRING-SYNTAX imports HEX-TOKEN-SYNTAX + imports BUILTINS syntax Command ::= "Load" "(" HexConstant "," HexConstant "," HexConstant ")" /* BaseAddress, MemoryContents, SegmentLength */ // Note: SegmentLength may be "too large," remaining bytes are implicitly zero. | "Entry" "(" HexConstant ")" - | "NamedSymbol" "(" String "," "NotPresentInFile" ")" - | "NamedSymbol" "(" String "," HexConstant ")" + | "NamedSymbol" "(" Builtin "," "NotPresentInFile" ")" + | "NamedSymbol" "(" Builtin "," HexConstant ")" syntax Commands ::= List{Command, ";"} diff --git a/semantics/elf_reader b/semantics/elf_reader new file mode 100755 index 0000000000000000000000000000000000000000..01885a67e195b79b3bee957121bbcbf5f6328132 GIT binary patch literal 917520 zcmbTf33wD$)<4{xq@mfYpe#{Af`&~Ih=Q_3)6kJ>=x7w8ILLs4Ac%_6%_3W{yM?lB zjS9**F1VwP+l(ThWMN6dq69=i5eOhsMYBZEB%sjW@0_YzT?x$m-{+fWOrN^;E4VtS8prki2Q+tVMUfRMK+cy)SG&eGXNQv7Z|D>_iXv zUuyaw{vFw%yfDMZ<#`Rt^R6`7%MHq_gGPCFgYuF&MtR=`<>^z6@?H(fKb>NfcWqcc z+bB7w zoXYp|f}?Ikfvg$CYFr z^Qk*^lc)B_@m|G^`jr&Xk}Gy2+&AxpU)dyZ zp^sOo6v)%hH8hAdoMqaR<%rk2Ay1Z2n+%(j&Itac+TF;@5;*#r!I<)`HbUN}@ zIqpNv5pXJ6dM|3;!XItY3L1+P-lt=jp6MWQU03=)JC+XB|>@`}mWMZ4w#_*M}Zi+DIK7%381TW9boB=s@FsJEgD} zEWOdYol3Rz=JF1~{nCoo4q(WUWAj=@wg+0sil%In{~_0&2DjYEFY~(ll`6l|$+a4+ z3Vw0O+v@Pt7*Dd|s$10^5mtpVJp73VkddCb8cqNiS-JL86lE72A|yQhn;IytxA;dx z*(f}{gD0|pq5GFmw7A&R`U83(6F?H}RWbpB6^{kdn{p(sl+Ejug~6p@Mvl?z-du11 zm8nWuplN9=Ra&t*vN1SFcAi~8X}LgpvM0o%mOw8!uE=)C<)zvDQ=Zo{+o9cvxybKE`;~WXp5n-tug$}c9ICrWRt`kma#pD!;s&IC%&C4+#hRLiB>&9bvh-gYj~+M?D>P(wVA zUT5$x$hvfGcZVZ*Wj+wKhslFekNcQ;C! zaKlws0$fd<6B&Ta?9iH}q~IZE7f`CGfKc$P>D0?*we?^OXDHL;YjUb&HMmPwbF1X& zKp1kHtgJ1fRIZhuK~pEyyIN6mrCj^Hjne@GcSX@}7{Fwubagv4<@Uwyc1Wv9e>oh* zjJ{GMPOcxhUAeZgHK7J?2G=TiK#msd!~C5k5UWmB^YLF$L(wk85fF{u=Fr~kZYrXp z6%+u)g(k%rOi>D73zHGz#&v9{1xHJmz#19l<7G9aQ&)b@smm;p)d-aqp&-HHliFm5 z5*dN=&>H&dm^DC)UE*-44ru&l|0GfqY#qc_UBdWXp{ga~zG|WJhQlBmT{0F#R3<1Z zKY+$-HOWvNRF?>HU*DUpiW%3V zy;2;emuvP3VdHxtmxtGEd6f1$N%{VP^u1(;i3`}C2>r5Q< zViCUWfiu{`Iep0F^JRAG1Pqvg_7Lu`_f6sYqOlbKdyglYN?(?Qs%}D{=d+N6j1H3y z+!Dftls8x$XA;M4br>tDLoGAwDOwFJKBfB4P;YdoiKaxRwUxQ(5W#979OqgTm4G-0rdtUzimLWv5bl>wg92qiF2VYLAJUJa>X) zok)2xN;QO*j&xHsy^WD$5SGqLM5I(yBCRNixtJ8l`Yf``h-@gQ%4wo^CG;8pv7XTQ zR;%$eG>$n7(S8@T-$j{CdSX9Dy}}E+sjJOR*8+hYGms)gcxfPc=@P1uRm)4Hgyp0> z%SlT9N?FPM6pbs)#wDsuo+W?u2O;T`QU#76f2=h8Q3bGsZNeUYtnX?vrCeKMcW-Q> z(JGJnDYfovbF4{-91CLH1P*S%2Eyl)T!>H(pra?_al~g+6p=^Vu{QNA_Smyn7*Mvd z5(!1(E<_??C?Cq@R{|5yOza(4*A%ykq>nw!m4>-?nW~e-a5br3X%EHh6za>3Lv_sp zNz_qtP3qi{z@c1QVvt81u}E^ioVq|Gkg1EcB|mdq@Cf$UqVuFy=3)+y?ql{75sIO? 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a/semantics/elf_reader.c b/semantics/elf_reader.c new file mode 100644 index 000000000..8ed7439ba --- /dev/null +++ b/semantics/elf_reader.c @@ -0,0 +1,212 @@ +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void * read_stdin() { + const size_t INITIAL_SIZE = 1024; + void * result = mmap(NULL, INITIAL_SIZE, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, 0, 0); + size_t so_far = 0; + size_t size = INITIAL_SIZE; + while (!feof(stdin)) { + so_far += fread((char*)result + so_far, 1, size-so_far, stdin); + if (ferror(stdin)) { + fprintf(stderr, "Error occurred while reading"); + exit(EXIT_FAILURE); + } else if (!feof(stdin) && so_far == size) { + const size_t new_size = 2 * size; + result = mremap(result, size, new_size, MREMAP_MAYMOVE); + size = new_size; + } + } + return result; +} + +void * read_file(const char * name) { + int fd = open(name, O_RDONLY); + if (fd < 0) { + fprintf(stderr, "Failed to open file %s with error: %s\n", name, strerror(errno)); + exit(EXIT_FAILURE); + } + struct stat file_stats; + if (fstat(fd, &file_stats) < 0) { + fprintf(stderr, "Failed to stat file %s with error: %s\n", name, strerror(errno)); + exit(EXIT_FAILURE); + } + + void * result = mmap(NULL, file_stats.st_size, PROT_READ, MAP_PRIVATE, fd, 0); + if (result == (void*)-1) { + fprintf(stderr, "Failed to mmap file %s with error: %s\n", name, strerror(errno)); + exit(EXIT_FAILURE); + } + + close(fd); + return result; +} + +const Elf64_Ehdr * read_elf_header(const char * name, const void * data) { + const Elf64_Ehdr * elf_header = (const Elf64_Ehdr*)data; + if (elf_header->e_ident[EI_MAG0] != ELFMAG0 || + elf_header->e_ident[EI_MAG1] != ELFMAG1 || + elf_header->e_ident[EI_MAG2] != ELFMAG2 || + elf_header->e_ident[EI_MAG3] != ELFMAG3) { + fprintf(stderr, "File %s does not appear to be an ELF file\n", name); + exit(EXIT_FAILURE); + } + + if (elf_header->e_ident[EI_DATA] != ELFDATA2LSB) { + fprintf(stderr, "This program currently only supports LSB ELF files"); // I believe all x86_64 ELF files are LSB but might be wrong about that. + exit(EXIT_FAILURE); + } + + if (elf_header->e_ident[EI_CLASS] != ELFCLASS64) { + fprintf(stderr, "This program only supports 64-bit ELF files\n"); + exit(EXIT_FAILURE); + } + + if (elf_header->e_type != ET_EXEC) { + fprintf(stderr, "Warning - Unsupported use-case: file %s is not an executable\n", name); + } + + if (!(elf_header->e_type & EM_X86_64)) { + if (elf_header->e_type != EM_NONE) { + fprintf(stderr, "Warning: This executable's machine type is not known.\n"); + } else { + fprintf(stderr, "This executable is not x86_64, exiting.\n"); + exit(EXIT_FAILURE); + } + } + + return elf_header; +} + +size_t read_num_program_headers(const Elf64_Ehdr * header, const void * input) { + if (!header->e_phoff) { + return 0; + } + if (header->e_phnum < PN_XNUM) { + return header->e_phnum; + } else { + return ((const Elf64_Shdr*)((const char *)input + header->e_shoff))->sh_info; + } +} + +void read_program_header(const Elf64_Ehdr * file_header, const void * input) { + const size_t num_headers = read_num_program_headers(file_header, input); + + for (size_t i = 0; i < num_headers; ++i) { + const Elf64_Phdr * program_header = + (const Elf64_Phdr*)((const char*)input + file_header->e_phoff + i * file_header->e_phentsize); + switch (program_header->p_type) { + case PT_INTERP: + case PT_DYNAMIC: + fprintf(stderr, "Found dynamic linking information, this file only supports statically linked executables\n"); + exit(EXIT_FAILURE); + break; + case PT_LOAD: + printf("Load(0x%lx, 0x", (size_t)program_header->p_vaddr); + const char * base = (const char*)input + program_header->p_offset; + for (size_t i = 0; i < program_header->p_memsz; ++i) { + printf("%02x", i < program_header->p_filesz ? (unsigned int)(base[i]) & 0xFF : 0); + } + printf(", 0x%lx);\n", program_header->p_memsz); + break; + default: + break; + } + } +} + +size_t read_num_sections(const Elf64_Ehdr * header, const void * input) { + if (!header->e_shoff) { + return 0; + } + + if (header->e_shnum) { + return header->e_shnum; + } else { + return ((const Elf64_Shdr *)(((const char *)input) + header->e_shoff))->sh_size; + } +} + +const size_t NAME_NOT_FOUND = (size_t)(-1); + +const char * MAIN_SYMBOL_NAME = "main"; +// Based on code from https://wiki.osdev.org/ELF_Tutorial#Accessing_Section_Headers - since the man page doesn't document sh_link at all. +size_t find_main_in_symbol_table(const Elf64_Ehdr * elf_header, const Elf64_Shdr* section_header, const void * input, const char * query) { + const Elf64_Shdr * string_table = (const Elf64_Shdr*)(((const char *)input) + elf_header->e_shoff + section_header->sh_link * elf_header->e_shentsize); + const size_t num_symbols = section_header->sh_size / section_header->sh_entsize; + for (size_t i = 0; i < num_symbols; ++i) { + const Elf64_Sym * symbol = (const Elf64_Sym *)(((const char *)input) + section_header->sh_offset + i * section_header->sh_entsize); + const char * name = ((const char *)input) + string_table->sh_offset + symbol->st_name; + if (!strcmp(name, query)) { + return symbol->st_value; + } + } + return NAME_NOT_FOUND; +} + +// We can't use the main program entry point yet, as the glibc initialization code will not work until we have implementations of several syscalls +// (Including uname, settimeofday, among others) & an implementation of cpuid. +size_t find_symbol(const Elf64_Ehdr * elf_header, const void * input, const char * query) { + const size_t num_sections = read_num_sections(elf_header, input); + for (size_t i = 0; i < num_sections; ++i) { + const Elf64_Shdr * section_header = + (const Elf64_Shdr*)((const char*)input + elf_header->e_shoff + i * elf_header->e_shentsize); + switch (section_header->sh_type) { + case SHT_SYMTAB: + case SHT_DYNSYM: + { + const size_t result = find_main_in_symbol_table(elf_header, section_header, input, query); + if (result != NAME_NOT_FOUND) { + return result; + } + } + default: + break; + } + } + return NAME_NOT_FOUND; +} + +int main(const int argc, const char ** argv) { + const void * input = NULL; + const char * name = NULL; + + if (argc < 2) { + fprintf(stderr, "Usage: ./elf_reader (elf_file/-) name1 name2 name3... \n"); // Main is always added to this list. + exit(EXIT_FAILURE); + } + + if(!strcmp(argv[1], "-")) { + name = "stdin"; + input = read_stdin(); + } else { + name = argv[1]; + input = read_file(name); + } + + const Elf64_Ehdr * elf_header = read_elf_header(name, input); + printf("Entry(0x%lx);\n", find_symbol(elf_header, input, MAIN_SYMBOL_NAME)); + + for (int i = 2; i < argc; ++i) { + const char * symbol_name = argv[i]; + const size_t value = find_symbol(elf_header, input, symbol_name); + if (value == NAME_NOT_FOUND) { + printf("NamedSymbol(%s, NotPresentInFile);\n", symbol_name); + } else { + printf("NamedSymbol(%s, 0x%lx);\n", symbol_name, value); + } + } + + read_program_header(elf_header, input); + + return 0; +} diff --git a/semantics/files-to-update.txt b/semantics/files-to-update.txt new file mode 100644 index 000000000..8ba8b4f9f --- /dev/null +++ b/semantics/files-to-update.txt @@ -0,0 +1,78 @@ +./systemInstructions/callq_m64.k +./systemInstructions/callq_r64.k +./systemInstructions/callq_rel32.k +./systemInstructions/jae_rel32.k +./systemInstructions/jae_rel8.k +./systemInstructions/ja_rel32.k +./systemInstructions/ja_rel8.k +./systemInstructions/jbe_rel32.k +./systemInstructions/jbe_rel8.k +./systemInstructions/jb_rel32.k +./systemInstructions/jb_rel8.k +./systemInstructions/jc_rel32.k +./systemInstructions/jc_rel8.k +./systemInstructions/jecxz_rel32.k +./systemInstructions/jecxz_rel8.k +./systemInstructions/je_rel32.k +./systemInstructions/je_rel8.k +./systemInstructions/jge_rel32.k +./systemInstructions/jge_rel8.k +./systemInstructions/jg_rel32.k +./systemInstructions/jg_rel8.k +./systemInstructions/jle_rel32.k +./systemInstructions/jle_rel8.k +./systemInstructions/jl_rel32.k +./systemInstructions/jl_rel8.k +./systemInstructions/jmp_m64.k +./systemInstructions/jmp_r64.k +./systemInstructions/jmp_rel32.k +./systemInstructions/jmp_rel8.k +./systemInstructions/jnae_rel32.k +./systemInstructions/jnae_rel8.k +./systemInstructions/jna_rel32.k +./systemInstructions/jna_rel8.k +./systemInstructions/jnbe_rel32.k +./systemInstructions/jnbe_rel8.k +./systemInstructions/jnb_rel32.k +./systemInstructions/jnb_rel8.k +./systemInstructions/jnc_rel32.k +./systemInstructions/jnc_rel8.k +./systemInstructions/jne_rel32.k +./systemInstructions/jne_rel8.k +./systemInstructions/jnge_rel32.k +./systemInstructions/jnge_rel8.k +./systemInstructions/jng_rel32.k +./systemInstructions/jng_rel8.k +./systemInstructions/jnle_rel32.k +./systemInstructions/jnle_rel8.k +./systemInstructions/jnl_rel32.k +./systemInstructions/jnl_rel8.k +./systemInstructions/jno_rel32.k +./systemInstructions/jno_rel8.k +./systemInstructions/jnp_rel32.k +./systemInstructions/jnp_rel8.k +./systemInstructions/jns_rel32.k +./systemInstructions/jns_rel8.k +./systemInstructions/jnz_rel32.k +./systemInstructions/jnz_rel8.k +./systemInstructions/jo_rel32.k +./systemInstructions/jo_rel8.k +./systemInstructions/jpe_rel32.k +./systemInstructions/jpe_rel8.k +./systemInstructions/jpo_rel32.k +./systemInstructions/jpo_rel8.k +./systemInstructions/jp_rel32.k +./systemInstructions/jp_rel8.k +./systemInstructions/jrcxz_rel32.k +./systemInstructions/jrcxz_rel8.k +./systemInstructions/js_rel32.k +./systemInstructions/js_rel8.k +./systemInstructions/jz_rel32.k +./systemInstructions/jz_rel8.k +./systemInstructions/loope_rel8.k +./systemInstructions/loopne_rel8.k +./systemInstructions/loopnz_rel8.k +./systemInstructions/loop_rel8.k +./systemInstructions/loopz_rel8.k +./systemInstructions/retq.k +./systemInstructions/ud2.k diff --git a/semantics/helloworld.c b/semantics/helloworld.c new file mode 100644 index 000000000..0abea747e --- /dev/null +++ b/semantics/helloworld.c @@ -0,0 +1,4 @@ +#include +int main() { + printf("Hello World\n"); +} diff --git a/semantics/out.txt b/semantics/out.txt new file mode 100644 index 000000000..8f5ffa60f --- /dev/null +++ b/semantics/out.txt @@ -0,0 +1,163279 @@ + +a.out: file format elf64-x86-64 + + +Disassembly of section .init: + +00000000004002c8 <_init>: + 4002c8: 48 83 ec 08 sub $0x8,%rsp + 4002cc: 48 8b 05 1d 9d 2c 00 mov 0x2c9d1d(%rip),%rax # 6c9ff0 <__stack_prot+0x10> + 4002d3: 48 85 c0 test %rax,%rax + 4002d6: 74 05 je 4002dd <_init+0x15> + 4002d8: e8 23 fd bf ff callq 0 <_nl_current_LC_CTYPE> + 4002dd: 48 83 c4 08 add $0x8,%rsp + 4002e1: c3 retq + +Disassembly of section .plt: + +00000000004002f0 <.plt>: + 4002f0: ff 25 22 9d 2c 00 jmpq *0x2c9d22(%rip) # 6ca018 <_GLOBAL_OFFSET_TABLE_+0x18> + 4002f6: 68 00 00 00 00 pushq $0x0 + 4002fb: e9 00 00 00 00 jmpq 400300 <__rela_iplt_end+0x38> + 400300: ff 25 1a 9d 2c 00 jmpq *0x2c9d1a(%rip) # 6ca020 <_GLOBAL_OFFSET_TABLE_+0x20> + 400306: 68 00 00 00 00 pushq $0x0 + 40030b: e9 00 00 00 00 jmpq 400310 <__rela_iplt_end+0x48> + 400310: ff 25 12 9d 2c 00 jmpq *0x2c9d12(%rip) # 6ca028 <_GLOBAL_OFFSET_TABLE_+0x28> + 400316: 68 00 00 00 00 pushq $0x0 + 40031b: e9 00 00 00 00 jmpq 400320 <__rela_iplt_end+0x58> + 400320: ff 25 0a 9d 2c 00 jmpq *0x2c9d0a(%rip) # 6ca030 <_GLOBAL_OFFSET_TABLE_+0x30> + 400326: 68 00 00 00 00 pushq $0x0 + 40032b: e9 00 00 00 00 jmpq 400330 <__rela_iplt_end+0x68> + 400330: ff 25 02 9d 2c 00 jmpq *0x2c9d02(%rip) # 6ca038 <_GLOBAL_OFFSET_TABLE_+0x38> + 400336: 68 00 00 00 00 pushq $0x0 + 40033b: e9 00 00 00 00 jmpq 400340 <__rela_iplt_end+0x78> + 400340: ff 25 fa 9c 2c 00 jmpq *0x2c9cfa(%rip) # 6ca040 <_GLOBAL_OFFSET_TABLE_+0x40> + 400346: 68 00 00 00 00 pushq $0x0 + 40034b: e9 00 00 00 00 jmpq 400350 <__rela_iplt_end+0x88> + 400350: ff 25 f2 9c 2c 00 jmpq *0x2c9cf2(%rip) # 6ca048 <_GLOBAL_OFFSET_TABLE_+0x48> + 400356: 68 00 00 00 00 pushq $0x0 + 40035b: e9 00 00 00 00 jmpq 400360 <__rela_iplt_end+0x98> + 400360: ff 25 ea 9c 2c 00 jmpq *0x2c9cea(%rip) # 6ca050 <_GLOBAL_OFFSET_TABLE_+0x50> + 400366: 68 00 00 00 00 pushq $0x0 + 40036b: e9 00 00 00 00 jmpq 400370 <__rela_iplt_end+0xa8> + 400370: ff 25 e2 9c 2c 00 jmpq *0x2c9ce2(%rip) # 6ca058 <_GLOBAL_OFFSET_TABLE_+0x58> + 400376: 68 00 00 00 00 pushq $0x0 + 40037b: e9 00 00 00 00 jmpq 400380 <__rela_iplt_end+0xb8> + 400380: ff 25 da 9c 2c 00 jmpq *0x2c9cda(%rip) # 6ca060 <_GLOBAL_OFFSET_TABLE_+0x60> + 400386: 68 00 00 00 00 pushq $0x0 + 40038b: e9 00 00 00 00 jmpq 400390 + +Disassembly of section .text: + +0000000000400390 : + 400390: ff cf dec %edi + 400392: 0f 8e 3a 01 00 00 jle 4004d2 + 400398: 40 84 f6 test %sil,%sil + 40039b: 0f 84 31 01 00 00 je 4004d2 + 4003a1: 55 push %rbp + 4003a2: 53 push %rbx + 4003a3: be 40 00 00 00 mov $0x40,%esi + 4003a8: 89 d5 mov %edx,%ebp + 4003aa: 48 81 ec 08 06 00 00 sub $0x608,%rsp + 4003b1: 48 89 e7 mov %rsp,%rdi + 4003b4: e8 b7 23 04 00 callq 442770 <__backtrace> + 4003b9: 83 f8 02 cmp $0x2,%eax + 4003bc: 41 89 c0 mov %eax,%r8d + 4003bf: 0f 8e 04 01 00 00 jle 4004c9 + 4003c5: 48 63 dd movslq %ebp,%rbx + 4003c8: ba 1d 00 00 00 mov $0x1d,%edx + 4003cd: be c8 1b 4a 00 mov $0x4a1bc8,%esi + 4003d2: 48 89 df mov %rbx,%rdi + 4003d5: b8 01 00 00 00 mov $0x1,%eax + 4003da: 0f 05 syscall + 4003dc: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 4003e2: 76 0c jbe 4003f0 + 4003e4: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx + 4003eb: f7 d8 neg %eax + 4003ed: 64 89 02 mov %eax,%fs:(%rdx) + 4003f0: 41 8d 70 ff lea -0x1(%r8),%esi + 4003f4: 48 8d 7c 24 08 lea 0x8(%rsp),%rdi + 4003f9: 89 ea mov %ebp,%edx + 4003fb: e8 d0 23 04 00 callq 4427d0 <__backtrace_symbols_fd> + 400400: ba 1d 00 00 00 mov $0x1d,%edx + 400405: be e6 1b 4a 00 mov $0x4a1be6,%esi + 40040a: 48 89 df mov %rbx,%rdi + 40040d: b8 01 00 00 00 mov $0x1,%eax + 400412: 0f 05 syscall + 400414: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 40041a: 76 0c jbe 400428 + 40041c: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx + 400423: f7 d8 neg %eax + 400425: 64 89 02 mov %eax,%fs:(%rdx) + 400428: 31 f6 xor %esi,%esi + 40042a: bf 04 1c 4a 00 mov $0x4a1c04,%edi + 40042f: b8 02 00 00 00 mov $0x2,%eax + 400434: 0f 05 syscall + 400436: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 40043c: 76 10 jbe 40044e + 40043e: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx + 400445: f7 d8 neg %eax + 400447: 64 89 02 mov %eax,%fs:(%rdx) + 40044a: 48 83 c8 ff or $0xffffffffffffffff,%rax + 40044e: 4c 63 c0 movslq %eax,%r8 + 400451: 31 ed xor %ebp,%ebp + 400453: 41 ba 01 00 00 00 mov $0x1,%r10d + 400459: ba 00 04 00 00 mov $0x400,%edx + 40045e: 48 8d b4 24 00 02 00 lea 0x200(%rsp),%rsi + 400465: 00 + 400466: 4c 89 c7 mov %r8,%rdi + 400469: 89 e8 mov %ebp,%eax + 40046b: 0f 05 syscall + 40046d: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 400473: 49 89 c1 mov %rax,%r9 + 400476: 76 1a jbe 400492 + 400478: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 40047f: 41 f7 d9 neg %r9d + 400482: 64 44 89 08 mov %r9d,%fs:(%rax) + 400486: 4c 89 c7 mov %r8,%rdi + 400489: b8 03 00 00 00 mov $0x3,%eax + 40048e: 0f 05 syscall + 400490: eb 37 jmp 4004c9 + 400492: 48 85 c0 test %rax,%rax + 400495: 7e ef jle 400486 + 400497: 4c 89 ca mov %r9,%rdx + 40049a: 48 8d b4 24 00 02 00 lea 0x200(%rsp),%rsi + 4004a1: 00 + 4004a2: 48 89 df mov %rbx,%rdi + 4004a5: 44 89 d0 mov %r10d,%eax + 4004a8: 0f 05 syscall + 4004aa: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 4004b0: 76 10 jbe 4004c2 + 4004b2: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx + 4004b9: f7 d8 neg %eax + 4004bb: 64 89 02 mov %eax,%fs:(%rdx) + 4004be: 48 83 c8 ff or $0xffffffffffffffff,%rax + 4004c2: 49 39 c1 cmp %rax,%r9 + 4004c5: 74 92 je 400459 + 4004c7: eb bd jmp 400486 + 4004c9: 48 81 c4 08 06 00 00 add $0x608,%rsp + 4004d0: 5b pop %rbx + 4004d1: 5d pop %rbp + 4004d2: c3 retq + +00000000004004d3 : + 4004d3: 50 push %rax + 4004d4: b9 28 2e 4a 00 mov $0x4a2e28,%ecx + 4004d9: ba 75 02 00 00 mov $0x275,%edx + 4004de: be a8 1f 4a 00 mov $0x4a1fa8,%esi + 4004e3: bf 80 23 4a 00 mov $0x4a2380,%edi + 4004e8: e8 33 69 01 00 callq 416e20 <__malloc_assert> + +00000000004004ed <__gconv_release_step.part.1>: + 4004ed: 50 push %rax + 4004ee: b9 80 51 4a 00 mov $0x4a5180,%ecx + 4004f3: ba ea 00 00 00 mov $0xea,%edx + 4004f8: be 18 51 4a 00 mov $0x4a5118,%esi + 4004fd: bf 23 51 4a 00 mov $0x4a5123,%edi + 400502: e8 39 12 00 00 callq 401740 <__assert_fail> + +0000000000400507 : + 400507: 48 8b 07 mov (%rdi),%rax + 40050a: be ff ff ff 7f mov $0x7fffffff,%esi + 40050f: 0f b6 00 movzbl (%rax),%eax + 400512: 83 e8 30 sub $0x30,%eax + 400515: 48 8b 17 mov (%rdi),%rdx + 400518: 48 8d 4a 01 lea 0x1(%rdx),%rcx + 40051c: 48 89 0f mov %rcx,(%rdi) + 40051f: 0f b6 4a 01 movzbl 0x1(%rdx),%ecx + 400523: 83 e9 30 sub $0x30,%ecx + 400526: 83 f9 09 cmp $0x9,%ecx + 400529: 77 25 ja 400550 + 40052b: 85 c0 test %eax,%eax + 40052d: 78 e6 js 400515 + 40052f: 3d cc cc cc 0c cmp $0xccccccc,%eax + 400534: 7f 15 jg 40054b + 400536: 6b d0 0a imul $0xa,%eax,%edx + 400539: 89 f0 mov %esi,%eax + 40053b: 29 c8 sub %ecx,%eax + 40053d: 01 d1 add %edx,%ecx + 40053f: 39 c2 cmp %eax,%edx + 400541: b8 ff ff ff ff mov $0xffffffff,%eax + 400546: 0f 4e c1 cmovle %ecx,%eax + 400549: eb ca jmp 400515 + 40054b: 83 c8 ff or $0xffffffff,%eax + 40054e: eb c5 jmp 400515 + 400550: c3 retq + +0000000000400551 : + 400551: 48 8b 0f mov (%rdi),%rcx + 400554: 41 b8 ff ff ff 7f mov $0x7fffffff,%r8d + 40055a: 8b 01 mov (%rcx),%eax + 40055c: 48 83 c1 04 add $0x4,%rcx + 400560: 83 e8 30 sub $0x30,%eax + 400563: 8b 11 mov (%rcx),%edx + 400565: 8d 72 d0 lea -0x30(%rdx),%esi + 400568: 83 fe 09 cmp $0x9,%esi + 40056b: 77 2a ja 400597 + 40056d: 85 c0 test %eax,%eax + 40056f: 78 20 js 400591 + 400571: 3d cc cc cc 0c cmp $0xccccccc,%eax + 400576: 7f 16 jg 40058e + 400578: 6b d0 0a imul $0xa,%eax,%edx + 40057b: 44 89 c0 mov %r8d,%eax + 40057e: 29 f0 sub %esi,%eax + 400580: 01 d6 add %edx,%esi + 400582: 39 c2 cmp %eax,%edx + 400584: b8 ff ff ff ff mov $0xffffffff,%eax + 400589: 0f 4e c6 cmovle %esi,%eax + 40058c: eb 03 jmp 400591 + 40058e: 83 c8 ff or $0xffffffff,%eax + 400591: 48 83 c1 04 add $0x4,%rcx + 400595: eb cc jmp 400563 + 400597: 48 89 0f mov %rcx,(%rdi) + 40059a: c3 retq + +000000000040059b : + 40059b: 50 push %rax + 40059c: bf 02 00 00 00 mov $0x2,%edi + 4005a1: be 98 5b 4b 00 mov $0x4b5b98,%esi + 4005a6: 31 c0 xor %eax,%eax + 4005a8: e8 a3 35 07 00 callq 473b50 <_dl_dprintf> + 4005ad: bf 7f 00 00 00 mov $0x7f,%edi + 4005b2: e8 19 e2 03 00 callq 43e7d0 <_exit> + 4005b7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 4005be: 00 00 + +00000000004005c0 : + 4005c0: 48 8b 05 31 c4 2c 00 mov 0x2cc431(%rip),%rax # 6cc9f8 + 4005c7: 48 85 c0 test %rax,%rax + 4005ca: 74 11 je 4005dd + 4005cc: bf 7c c4 4b 00 mov $0x4bc47c,%edi + 4005d1: b9 0e 00 00 00 mov $0xe,%ecx + 4005d6: 48 89 c6 mov %rax,%rsi + 4005d9: f3 a6 repz cmpsb %es:(%rdi),%ds:(%rsi) + 4005db: 75 01 jne 4005de + 4005dd: c3 retq + 4005de: 48 89 c7 mov %rax,%rdi + 4005e1: e9 ca d7 01 00 jmpq 41ddb0 <__cfree> + 4005e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4005ed: 00 00 00 + +00000000004005f0 : + 4005f0: 8b 05 8a c0 2c 00 mov 0x2cc08a(%rip),%eax # 6cc680 <_dl_x86_cpu_features> + 4005f6: 41 54 push %r12 + 4005f8: 55 push %rbp + 4005f9: 53 push %rbx + 4005fa: 83 f8 01 cmp $0x1,%eax + 4005fd: 74 0e je 40060d + 4005ff: 83 f8 02 cmp $0x2,%eax + 400602: 0f 84 07 01 00 00 je 40070f + 400608: 5b pop %rbx + 400609: 5d pop %rbp + 40060a: 41 5c pop %r12 + 40060c: c3 retq + 40060d: 8b 35 71 c0 2c 00 mov 0x2cc071(%rip),%esi # 6cc684 <_dl_x86_cpu_features+0x4> + 400613: bf bc 00 00 00 mov $0xbc,%edi + 400618: e8 03 da 03 00 callq 43e020 + 40061d: 8b 35 61 c0 2c 00 mov 0x2cc061(%rip),%esi # 6cc684 <_dl_x86_cpu_features+0x4> + 400623: bf c2 00 00 00 mov $0xc2,%edi + 400628: 49 89 c4 mov %rax,%r12 + 40062b: e8 f0 d9 03 00 callq 43e020 + 400630: 48 85 c0 test %rax,%rax + 400633: 48 89 c5 mov %rax,%rbp + 400636: bf 03 00 00 00 mov $0x3,%edi + 40063b: 0f 8e 2c 02 00 00 jle 40086d + 400641: 44 8b 05 3c c0 2c 00 mov 0x2cc03c(%rip),%r8d # 6cc684 <_dl_x86_cpu_features+0x4> + 400648: 41 83 f8 03 cmp $0x3,%r8d + 40064c: 7e 39 jle 400687 + 40064e: 44 8b 0d 63 c0 2c 00 mov 0x2cc063(%rip),%r9d # 6cc6b8 <_dl_x86_cpu_features+0x38> + 400655: 44 8b 15 60 c0 2c 00 mov 0x2cc060(%rip),%r10d # 6cc6bc <_dl_x86_cpu_features+0x3c> + 40065c: 31 c9 xor %ecx,%ecx + 40065e: be 04 00 00 00 mov $0x4,%esi + 400663: eb 16 jmp 40067b + 400665: 0f 1f 00 nopl (%rax) + 400668: 89 c2 mov %eax,%edx + 40066a: 44 89 d9 mov %r11d,%ecx + 40066d: c1 ea 05 shr $0x5,%edx + 400670: 83 e2 07 and $0x7,%edx + 400673: 39 d7 cmp %edx,%edi + 400675: 0f 84 44 01 00 00 je 4007bf + 40067b: 44 8d 59 01 lea 0x1(%rcx),%r11d + 40067f: 89 f0 mov %esi,%eax + 400681: 0f a2 cpuid + 400683: a8 1f test $0x1f,%al + 400685: 75 e1 jne 400668 + 400687: 0f b6 15 00 c0 2c 00 movzbl 0x2cc000(%rip),%edx # 6cc68e <_dl_x86_cpu_features+0xe> + 40068e: 48 85 ed test %rbp,%rbp + 400691: 7e 11 jle 4006a4 + 400693: 85 d2 test %edx,%edx + 400695: 74 0d je 4006a4 + 400697: 48 89 e8 mov %rbp,%rax + 40069a: 89 d1 mov %edx,%ecx + 40069c: 48 99 cqto + 40069e: 48 f7 f9 idiv %rcx + 4006a1: 48 89 c5 mov %rax,%rbp + 4006a4: 4d 85 e4 test %r12,%r12 + 4006a7: 7e 2c jle 4006d5 + 4006a9: 4c 89 e0 mov %r12,%rax + 4006ac: 4c 89 25 05 aa 2c 00 mov %r12,0x2caa05(%rip) # 6cb0b8 <__x86_raw_data_cache_size> + 4006b3: 41 80 e4 00 and $0x0,%r12b + 4006b7: 48 d1 f8 sar %rax + 4006ba: 4c 89 25 07 aa 2c 00 mov %r12,0x2caa07(%rip) # 6cb0c8 <__x86_data_cache_size> + 4006c1: 48 89 05 f8 a9 2c 00 mov %rax,0x2ca9f8(%rip) # 6cb0c0 <__x86_raw_data_cache_size_half> + 4006c8: 4c 89 e0 mov %r12,%rax + 4006cb: 48 d1 f8 sar %rax + 4006ce: 48 89 05 fb a9 2c 00 mov %rax,0x2ca9fb(%rip) # 6cb0d0 <__x86_data_cache_size_half> + 4006d5: 48 85 ed test %rbp,%rbp + 4006d8: 0f 8e 2a ff ff ff jle 400608 + 4006de: 48 89 e8 mov %rbp,%rax + 4006e1: 48 89 2d b0 a9 2c 00 mov %rbp,0x2ca9b0(%rip) # 6cb098 <__x86_raw_shared_cache_size> + 4006e8: 40 80 e5 00 and $0x0,%bpl + 4006ec: 48 d1 f8 sar %rax + 4006ef: 48 89 2d b2 a9 2c 00 mov %rbp,0x2ca9b2(%rip) # 6cb0a8 <__x86_shared_cache_size> + 4006f6: 48 89 05 a3 a9 2c 00 mov %rax,0x2ca9a3(%rip) # 6cb0a0 <__x86_raw_shared_cache_size_half> + 4006fd: 48 89 e8 mov %rbp,%rax + 400700: 48 d1 f8 sar %rax + 400703: 5b pop %rbx + 400704: 48 89 05 a5 a9 2c 00 mov %rax,0x2ca9a5(%rip) # 6cb0b0 <__x86_shared_cache_size_half> + 40070b: 5d pop %rbp + 40070c: 41 5c pop %r12 + 40070e: c3 retq + 40070f: bf bc 00 00 00 mov $0xbc,%edi + 400714: e8 27 da 03 00 callq 43e140 + 400719: bf bf 00 00 00 mov $0xbf,%edi + 40071e: 49 89 c4 mov %rax,%r12 + 400721: e8 1a da 03 00 callq 43e140 + 400726: bf c2 00 00 00 mov $0xc2,%edi + 40072b: 48 89 c5 mov %rax,%rbp + 40072e: e8 0d da 03 00 callq 43e140 + 400733: 48 89 c7 mov %rax,%rdi + 400736: b8 00 00 00 80 mov $0x80000000,%eax + 40073b: 0f a2 cpuid + 40073d: 48 85 ff test %rdi,%rdi + 400740: 89 c6 mov %eax,%esi + 400742: 7e 25 jle 400769 + 400744: 3d 07 00 00 80 cmp $0x80000007,%eax + 400749: 77 45 ja 400790 + 40074b: b8 01 00 00 00 mov $0x1,%eax + 400750: 0f a2 cpuid + 400752: 81 e2 00 00 00 10 and $0x10000000,%edx + 400758: 89 c6 mov %eax,%esi + 40075a: 74 0a je 400766 + 40075c: c1 eb 10 shr $0x10,%ebx + 40075f: 0f b6 cb movzbl %bl,%ecx + 400762: 85 c9 test %ecx,%ecx + 400764: 75 42 jne 4007a8 + 400766: 48 01 fd add %rdi,%rbp + 400769: 81 fe 00 00 00 80 cmp $0x80000000,%esi + 40076f: 0f 86 2f ff ff ff jbe 4006a4 + 400775: b8 01 00 00 80 mov $0x80000001,%eax + 40077a: 0f a2 cpuid + 40077c: 80 e5 01 and $0x1,%ch + 40077f: 74 34 je 4007b5 + 400781: c7 05 2d ca 2c 00 ff movl $0xffffffff,0x2cca2d(%rip) # 6cd1b8 <__x86_prefetchw> + 400788: ff ff ff + 40078b: e9 14 ff ff ff jmpq 4006a4 + 400790: b8 08 00 00 80 mov $0x80000008,%eax + 400795: 0f a2 cpuid + 400797: c1 e9 0c shr $0xc,%ecx + 40079a: 89 c6 mov %eax,%esi + 40079c: b8 01 00 00 00 mov $0x1,%eax + 4007a1: 83 e1 0f and $0xf,%ecx + 4007a4: d3 e0 shl %cl,%eax + 4007a6: 89 c1 mov %eax,%ecx + 4007a8: 48 89 f8 mov %rdi,%rax + 4007ab: 48 99 cqto + 4007ad: 48 f7 f9 idiv %rcx + 4007b0: 48 89 c7 mov %rax,%rdi + 4007b3: eb b1 jmp 400766 + 4007b5: 85 d2 test %edx,%edx + 4007b7: 0f 89 e7 fe ff ff jns 4006a4 + 4007bd: eb c2 jmp 400781 + 4007bf: c1 e8 0e shr $0xe,%eax + 4007c2: ba 01 00 00 00 mov $0x1,%edx + 4007c7: 25 ff 03 00 00 and $0x3ff,%eax + 4007cc: 89 c6 mov %eax,%esi + 4007ce: 0f 84 ba fe ff ff je 40068e + 4007d4: 41 83 f8 0a cmp $0xa,%r8d + 4007d8: 7e 43 jle 40081d + 4007da: 31 d2 xor %edx,%edx + 4007dc: 41 bb 0b 00 00 00 mov $0xb,%r11d + 4007e2: 44 8d 42 01 lea 0x1(%rdx),%r8d + 4007e6: 44 89 d8 mov %r11d,%eax + 4007e9: 89 d1 mov %edx,%ecx + 4007eb: 0f a2 cpuid + 4007ed: 0f b6 db movzbl %bl,%ebx + 4007f0: 81 e1 f0 0f 00 00 and $0xff0,%ecx + 4007f6: 85 db test %ebx,%ebx + 4007f8: 74 23 je 40081d + 4007fa: 85 c9 test %ecx,%ecx + 4007fc: 74 1f je 40081d + 4007fe: 81 f9 00 02 00 00 cmp $0x200,%ecx + 400804: 44 89 c2 mov %r8d,%edx + 400807: 75 d9 jne 4007e2 + 400809: 0f bd c6 bsr %esi,%eax + 40080c: 8d 48 01 lea 0x1(%rax),%ecx + 40080f: 83 c8 ff or $0xffffffff,%eax + 400812: 83 eb 01 sub $0x1,%ebx + 400815: d3 e0 shl %cl,%eax + 400817: f7 d0 not %eax + 400819: 21 d8 and %ebx,%eax + 40081b: 89 c6 mov %eax,%esi + 40081d: 41 83 f9 06 cmp $0x6,%r9d + 400821: 8d 56 01 lea 0x1(%rsi),%edx + 400824: 0f 94 c1 sete %cl + 400827: 83 ff 02 cmp $0x2,%edi + 40082a: 0f 94 c0 sete %al + 40082d: 84 c1 test %al,%cl + 40082f: 0f 84 59 fe ff ff je 40068e + 400835: 83 fa 02 cmp $0x2,%edx + 400838: 0f 86 50 fe ff ff jbe 40068e + 40083e: 41 8d 4a c9 lea -0x37(%r10),%ecx + 400842: 83 f9 26 cmp $0x26,%ecx + 400845: 0f 87 43 fe ff ff ja 40068e + 40084b: b8 01 00 00 00 mov $0x1,%eax + 400850: 48 d3 e0 shl %cl,%rax + 400853: 48 b9 01 00 48 00 49 movabs $0x4900480001,%rcx + 40085a: 00 00 00 + 40085d: 48 85 c8 test %rcx,%rax + 400860: b8 02 00 00 00 mov $0x2,%eax + 400865: 0f 45 d0 cmovne %eax,%edx + 400868: e9 21 fe ff ff jmpq 40068e + 40086d: 8b 35 11 be 2c 00 mov 0x2cbe11(%rip),%esi # 6cc684 <_dl_x86_cpu_features+0x4> + 400873: bf bf 00 00 00 mov $0xbf,%edi + 400878: e8 a3 d7 03 00 callq 43e020 + 40087d: bf 02 00 00 00 mov $0x2,%edi + 400882: 48 89 c5 mov %rax,%rbp + 400885: e9 b7 fd ff ff jmpq 400641 + 40088a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + +0000000000400890 <_start>: + 400890: 31 ed xor %ebp,%ebp + 400892: 49 89 d1 mov %rdx,%r9 + 400895: 5e pop %rsi + 400896: 48 89 e2 mov %rsp,%rdx + 400899: 48 83 e4 f0 and $0xfffffffffffffff0,%rsp + 40089d: 50 push %rax + 40089e: 54 push %rsp + 40089f: 49 c7 c0 c0 15 40 00 mov $0x4015c0,%r8 + 4008a6: 48 c7 c1 30 15 40 00 mov $0x401530,%rcx + 4008ad: 48 c7 c7 ae 09 40 00 mov $0x4009ae,%rdi + 4008b4: e8 27 04 00 00 callq 400ce0 <__libc_start_main> + 4008b9: f4 hlt + 4008ba: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + +00000000004008c0 : + 4008c0: b8 57 bb 6c 00 mov $0x6cbb57,%eax + 4008c5: 55 push %rbp + 4008c6: 48 2d 50 bb 6c 00 sub $0x6cbb50,%rax + 4008cc: 48 83 f8 0e cmp $0xe,%rax + 4008d0: 48 89 e5 mov %rsp,%rbp + 4008d3: 76 1b jbe 4008f0 + 4008d5: b8 00 00 00 00 mov $0x0,%eax + 4008da: 48 85 c0 test %rax,%rax + 4008dd: 74 11 je 4008f0 + 4008df: 5d pop %rbp + 4008e0: bf 50 bb 6c 00 mov $0x6cbb50,%edi + 4008e5: ff e0 jmpq *%rax + 4008e7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 4008ee: 00 00 + 4008f0: 5d pop %rbp + 4008f1: c3 retq + 4008f2: 0f 1f 40 00 nopl 0x0(%rax) + 4008f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4008fd: 00 00 00 + +0000000000400900 : + 400900: be 50 bb 6c 00 mov $0x6cbb50,%esi + 400905: 55 push %rbp + 400906: 48 81 ee 50 bb 6c 00 sub $0x6cbb50,%rsi + 40090d: 48 c1 fe 03 sar $0x3,%rsi + 400911: 48 89 e5 mov %rsp,%rbp + 400914: 48 89 f0 mov %rsi,%rax + 400917: 48 c1 e8 3f shr $0x3f,%rax + 40091b: 48 01 c6 add %rax,%rsi + 40091e: 48 d1 fe sar %rsi + 400921: 74 15 je 400938 + 400923: b8 00 00 00 00 mov $0x0,%eax + 400928: 48 85 c0 test %rax,%rax + 40092b: 74 0b je 400938 + 40092d: 5d pop %rbp + 40092e: bf 50 bb 6c 00 mov $0x6cbb50,%edi + 400933: ff e0 jmpq *%rax + 400935: 0f 1f 00 nopl (%rax) + 400938: 5d pop %rbp + 400939: c3 retq + 40093a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + +0000000000400940 <__do_global_dtors_aux>: + 400940: 80 3d 19 b2 2c 00 00 cmpb $0x0,0x2cb219(%rip) # 6cbb60 + 400947: 75 22 jne 40096b <__do_global_dtors_aux+0x2b> + 400949: 55 push %rbp + 40094a: 48 89 e5 mov %rsp,%rbp + 40094d: e8 6e ff ff ff callq 4008c0 + 400952: b8 30 e1 49 00 mov $0x49e130,%eax + 400957: 48 85 c0 test %rax,%rax + 40095a: 74 07 je 400963 <__do_global_dtors_aux+0x23> + 40095c: bf a0 e1 4b 00 mov $0x4be1a0,%edi + 400961: ff d0 callq *%rax + 400963: 5d pop %rbp + 400964: c6 05 f5 b1 2c 00 01 movb $0x1,0x2cb1f5(%rip) # 6cbb60 + 40096b: f3 c3 repz retq + 40096d: 0f 1f 00 nopl (%rax) + +0000000000400970 : + 400970: 55 push %rbp + 400971: b8 00 df 49 00 mov $0x49df00,%eax + 400976: 48 85 c0 test %rax,%rax + 400979: 48 89 e5 mov %rsp,%rbp + 40097c: 74 0f je 40098d + 40097e: be 80 bb 6c 00 mov $0x6cbb80,%esi + 400983: bf a0 e1 4b 00 mov $0x4be1a0,%edi + 400988: e8 73 d5 09 00 callq 49df00 <__register_frame_info> + 40098d: bf f8 9e 6c 00 mov $0x6c9ef8,%edi + 400992: 48 83 3f 00 cmpq $0x0,(%rdi) + 400996: 75 08 jne 4009a0 + 400998: 5d pop %rbp + 400999: e9 62 ff ff ff jmpq 400900 + 40099e: 66 90 xchg %ax,%ax + 4009a0: b8 00 00 00 00 mov $0x0,%eax + 4009a5: 48 85 c0 test %rax,%rax + 4009a8: 74 ee je 400998 + 4009aa: ff d0 callq *%rax + 4009ac: eb ea jmp 400998 + +00000000004009ae

    : + 4009ae: 55 push %rbp + 4009af: 48 89 e5 mov %rsp,%rbp + 4009b2: c7 45 fc 05 00 00 00 movl $0x5,-0x4(%rbp) + 4009b9: 83 45 fc 01 addl $0x1,-0x4(%rbp) + 4009bd: 83 6d fc 01 subl $0x1,-0x4(%rbp) + 4009c1: b8 00 00 00 00 mov $0x0,%eax + 4009c6: 5d pop %rbp + 4009c7: c3 retq + 4009c8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 4009cf: 00 + +00000000004009d0 : + 4009d0: 41 56 push %r14 + 4009d2: 41 55 push %r13 + 4009d4: b8 00 00 00 00 mov $0x0,%eax + 4009d9: 41 54 push %r12 + 4009db: 55 push %rbp + 4009dc: 49 89 cc mov %rcx,%r12 + 4009df: 53 push %rbx + 4009e0: 4d 89 c5 mov %r8,%r13 + 4009e3: 4d 89 ce mov %r9,%r14 + 4009e6: 48 81 ec 90 00 00 00 sub $0x90,%rsp + 4009ed: 48 85 c0 test %rax,%rax + 4009f0: 48 89 7c 24 18 mov %rdi,0x18(%rsp) + 4009f5: 89 74 24 0c mov %esi,0xc(%rsp) + 4009f9: 48 89 54 24 10 mov %rdx,0x10(%rsp) + 4009fe: 0f 84 2d 01 00 00 je 400b31 + 400a04: 8b 0d f6 f5 bf ff mov -0x400a0a(%rip),%ecx # 0 <_nl_current_LC_CTYPE> + 400a0a: 31 c0 xor %eax,%eax + 400a0c: 85 c9 test %ecx,%ecx + 400a0e: 48 89 d1 mov %rdx,%rcx + 400a11: 0f 94 c0 sete %al + 400a14: 89 05 e6 ac 2c 00 mov %eax,0x2cace6(%rip) # 6cb700 <__libc_multiple_libcs> + 400a1a: 48 63 44 24 0c movslq 0xc(%rsp),%rax + 400a1f: 48 8d 7c c1 08 lea 0x8(%rcx,%rax,8),%rdi + 400a24: 48 8b 84 24 c0 00 00 mov 0xc0(%rsp),%rax + 400a2b: 00 + 400a2c: 48 89 3d 0d bc 2c 00 mov %rdi,0x2cbc0d(%rip) # 6cc640 <__environ> + 400a33: 48 89 05 56 95 2c 00 mov %rax,0x2c9556(%rip) # 6c9f90 <__libc_stack_end> + 400a3a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 400a40: 48 83 c7 08 add $0x8,%rdi + 400a44: 48 83 7f f8 00 cmpq $0x0,-0x8(%rdi) + 400a49: 75 f5 jne 400a40 + 400a4b: e8 50 21 04 00 callq 442ba0 <_dl_aux_init> + 400a50: 48 83 3d f0 c7 2c 00 cmpq $0x0,0x2cc7f0(%rip) # 6cd248 <_dl_phdr> + 400a57: 00 + 400a58: 75 4f jne 400aa9 + 400a5a: b8 00 00 40 00 mov $0x400000,%eax + 400a5f: 48 85 c0 test %rax,%rax + 400a62: 74 45 je 400aa9 + 400a64: 66 83 3d ca f5 ff ff cmpw $0x38,-0xa36(%rip) # 400036 <__ehdr_start+0x36> + 400a6b: 38 + 400a6c: 74 19 je 400a87 + 400a6e: b9 70 0f 4a 00 mov $0x4a0f70,%ecx + 400a73: ba af 00 00 00 mov $0xaf,%edx + 400a78: be c4 0e 4a 00 mov $0x4a0ec4,%esi + 400a7d: bf f0 0e 4a 00 mov $0x4a0ef0,%edi + 400a82: e8 b9 0c 00 00 callq 401740 <__assert_fail> + 400a87: 48 8b 05 92 f5 ff ff mov -0xa6e(%rip),%rax # 400020 <__ehdr_start+0x20> + 400a8e: 48 05 00 00 40 00 add $0x400000,%rax + 400a94: 48 89 05 ad c7 2c 00 mov %rax,0x2cc7ad(%rip) # 6cd248 <_dl_phdr> + 400a9b: 0f b7 05 96 f5 ff ff movzwl -0xa6a(%rip),%eax # 400038 <__ehdr_start+0x38> + 400aa2: 48 89 05 d7 c7 2c 00 mov %rax,0x2cc7d7(%rip) # 6cd280 <_dl_phnum> + 400aa9: 8b 05 51 ac 2c 00 mov 0x2cac51(%rip),%eax # 6cb700 <__libc_multiple_libcs> + 400aaf: 85 c0 test %eax,%eax + 400ab1: 74 4c je 400aff + 400ab3: b8 d8 01 40 00 mov $0x4001d8,%eax + 400ab8: 48 3d c8 02 40 00 cmp $0x4002c8,%rax + 400abe: 73 7b jae 400b3b + 400ac0: 83 3d 19 f7 ff ff 25 cmpl $0x25,-0x8e7(%rip) # 4001e0 <__rela_iplt_start+0x8> + 400ac7: 48 8b 2d 0a f7 ff ff mov -0x8f6(%rip),%rbp # 4001d8 <__rela_iplt_start> + 400ace: bb d8 01 40 00 mov $0x4001d8,%ebx + 400ad3: 75 20 jne 400af5 + 400ad5: 0f 1f 00 nopl (%rax) + 400ad8: ff 53 10 callq *0x10(%rbx) + 400adb: 48 83 c3 18 add $0x18,%rbx + 400adf: 48 89 45 00 mov %rax,0x0(%rbp) + 400ae3: 48 81 fb c8 02 40 00 cmp $0x4002c8,%rbx + 400aea: 73 4f jae 400b3b + 400aec: 83 7b 08 25 cmpl $0x25,0x8(%rbx) + 400af0: 48 8b 2b mov (%rbx),%rbp + 400af3: 74 e3 je 400ad8 + 400af5: bf 48 0f 4a 00 mov $0x4a0f48,%edi + 400afa: e8 91 0d 01 00 callq 411890 <__libc_fatal> + 400aff: e8 9c 34 04 00 callq 443fa0 <_dl_discover_osversion> + 400b04: 85 c0 test %eax,%eax + 400b06: 0f 88 4c 01 00 00 js 400c58 + 400b0c: 8b 15 8e c7 2c 00 mov 0x2cc78e(%rip),%edx # 6cd2a0 <_dl_osversion> + 400b12: 85 d2 test %edx,%edx + 400b14: 0f 85 03 01 00 00 jne 400c1d + 400b1a: 89 05 80 c7 2c 00 mov %eax,0x2cc780(%rip) # 6cd2a0 <_dl_osversion> + 400b20: 3d 1f 06 02 00 cmp $0x2061f,%eax + 400b25: 7f 8c jg 400ab3 + 400b27: bf d8 0e 4a 00 mov $0x4a0ed8,%edi + 400b2c: e8 5f 0d 01 00 callq 411890 <__libc_fatal> + 400b31: 31 c0 xor %eax,%eax + 400b33: 48 89 d1 mov %rdx,%rcx + 400b36: e9 d9 fe ff ff jmpq 400a14 + 400b3b: e8 e0 09 00 00 callq 401520 <__pthread_initialize_minimal> + 400b40: 48 8b 15 39 94 2c 00 mov 0x2c9439(%rip),%rdx # 6c9f80 <_dl_random> + 400b47: 48 8b 02 mov (%rdx),%rax + 400b4a: 30 c0 xor %al,%al + 400b4c: 64 48 89 04 25 28 00 mov %rax,%fs:0x28 + 400b53: 00 00 + 400b55: 48 8b 42 08 mov 0x8(%rdx),%rax + 400b59: 64 48 89 04 25 30 00 mov %rax,%fs:0x30 + 400b60: 00 00 + 400b62: 4d 85 f6 test %r14,%r14 + 400b65: 74 0c je 400b73 + 400b67: 31 d2 xor %edx,%edx + 400b69: 31 f6 xor %esi,%esi + 400b6b: 4c 89 f7 mov %r14,%rdi + 400b6e: e8 7d e0 00 00 callq 40ebf0 <__cxa_atexit> + 400b73: 48 8b 15 c6 ba 2c 00 mov 0x2cbac6(%rip),%rdx # 6cc640 <__environ> + 400b7a: 48 8b 74 24 10 mov 0x10(%rsp),%rsi + 400b7f: 8b 7c 24 0c mov 0xc(%rsp),%edi + 400b83: e8 28 35 04 00 callq 4440b0 <__libc_init_first> + 400b88: 4d 85 ed test %r13,%r13 + 400b8b: 74 0c je 400b99 + 400b8d: 31 d2 xor %edx,%edx + 400b8f: 31 f6 xor %esi,%esi + 400b91: 4c 89 ef mov %r13,%rdi + 400b94: e8 57 e0 00 00 callq 40ebf0 <__cxa_atexit> + 400b99: 83 3d f8 93 2c 00 00 cmpl $0x0,0x2c93f8(%rip) # 6c9f98 <__libc_enable_secure> + 400ba0: 0f 85 bc 00 00 00 jne 400c62 + 400ba6: 4d 85 e4 test %r12,%r12 + 400ba9: 74 13 je 400bbe + 400bab: 48 8b 15 8e ba 2c 00 mov 0x2cba8e(%rip),%rdx # 6cc640 <__environ> + 400bb2: 48 8b 74 24 10 mov 0x10(%rsp),%rsi + 400bb7: 8b 7c 24 0c mov 0xc(%rsp),%edi + 400bbb: 41 ff d4 callq *%r12 + 400bbe: 31 ff xor %edi,%edi + 400bc0: 31 f6 xor %esi,%esi + 400bc2: e8 69 1f 04 00 callq 442b30 <_dl_debug_initialize> + 400bc7: 48 8d 7c 24 20 lea 0x20(%rsp),%rdi + 400bcc: e8 9f cf 00 00 callq 40db70 <_setjmp> + 400bd1: 85 c0 test %eax,%eax + 400bd3: 75 55 jne 400c2a + 400bd5: 64 48 8b 04 25 00 03 mov %fs:0x300,%rax + 400bdc: 00 00 + 400bde: 48 89 44 24 68 mov %rax,0x68(%rsp) + 400be3: 64 48 8b 04 25 f8 02 mov %fs:0x2f8,%rax + 400bea: 00 00 + 400bec: 48 89 44 24 70 mov %rax,0x70(%rsp) + 400bf1: 48 8d 44 24 20 lea 0x20(%rsp),%rax + 400bf6: 64 48 89 04 25 00 03 mov %rax,%fs:0x300 + 400bfd: 00 00 + 400bff: 48 8b 15 3a ba 2c 00 mov 0x2cba3a(%rip),%rdx # 6cc640 <__environ> + 400c06: 48 8b 74 24 10 mov 0x10(%rsp),%rsi + 400c0b: 8b 7c 24 0c mov 0xc(%rsp),%edi + 400c0f: 48 8b 44 24 18 mov 0x18(%rsp),%rax + 400c14: ff d0 callq *%rax + 400c16: 89 c7 mov %eax,%edi + 400c18: e8 d3 dd 00 00 callq 40e9f0 + 400c1d: 39 c2 cmp %eax,%edx + 400c1f: 0f 86 fb fe ff ff jbe 400b20 + 400c25: e9 f0 fe ff ff jmpq 400b1a + 400c2a: e8 d1 f3 bf ff callq 0 <_nl_current_LC_CTYPE> + 400c2f: f0 ff 0d ca f3 bf ff lock decl -0x400c36(%rip) # 0 <_nl_current_LC_CTYPE> + 400c36: 0f 94 c0 sete %al + 400c39: 84 c0 test %al,%al + 400c3b: 74 04 je 400c41 + 400c3d: 31 c0 xor %eax,%eax + 400c3f: eb d5 jmp 400c16 + 400c41: ba 3c 00 00 00 mov $0x3c,%edx + 400c46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 400c4d: 00 00 00 + 400c50: 31 ff xor %edi,%edi + 400c52: 89 d0 mov %edx,%eax + 400c54: 0f 05 syscall + 400c56: eb f8 jmp 400c50 + 400c58: bf 20 0f 4a 00 mov $0x4a0f20,%edi + 400c5d: e8 2e 0c 01 00 callq 411890 <__libc_fatal> + 400c62: e8 59 04 00 00 callq 4010c0 <__libc_check_standard_fds> + 400c67: e9 3a ff ff ff jmpq 400ba6 + 400c6c: 0f 1f 40 00 nopl 0x0(%rax) + +0000000000400c70 : + 400c70: 49 89 d1 mov %rdx,%r9 + 400c73: 53 push %rbx + 400c74: 49 89 c8 mov %rcx,%r8 + 400c77: b8 01 00 00 00 mov $0x1,%eax + 400c7c: 0f a2 cpuid + 400c7e: 89 15 10 ba 2c 00 mov %edx,0x2cba10(%rip) # 6cc694 <_dl_x86_cpu_features+0x14> + 400c84: 89 c2 mov %eax,%edx + 400c86: 89 1d 00 ba 2c 00 mov %ebx,0x2cba00(%rip) # 6cc68c <_dl_x86_cpu_features+0xc> + 400c8c: c1 ea 08 shr $0x8,%edx + 400c8f: 89 0d fb b9 2c 00 mov %ecx,0x2cb9fb(%rip) # 6cc690 <_dl_x86_cpu_features+0x10> + 400c95: 89 05 ed b9 2c 00 mov %eax,0x2cb9ed(%rip) # 6cc688 <_dl_x86_cpu_features+0x8> + 400c9b: 83 e2 0f and $0xf,%edx + 400c9e: 89 17 mov %edx,(%rdi) + 400ca0: 89 c2 mov %eax,%edx + 400ca2: c1 ea 04 shr $0x4,%edx + 400ca5: 83 e2 0f and $0xf,%edx + 400ca8: 89 16 mov %edx,(%rsi) + 400caa: 89 c2 mov %eax,%edx + 400cac: c1 ea 0c shr $0xc,%edx + 400caf: 81 e2 f0 00 00 00 and $0xf0,%edx + 400cb5: 41 89 11 mov %edx,(%r9) + 400cb8: 83 3f 0f cmpl $0xf,(%rdi) + 400cbb: 75 12 jne 400ccf + 400cbd: 89 c2 mov %eax,%edx + 400cbf: c1 ea 14 shr $0x14,%edx + 400cc2: 0f b6 d2 movzbl %dl,%edx + 400cc5: 83 c2 0f add $0xf,%edx + 400cc8: 89 17 mov %edx,(%rdi) + 400cca: 41 8b 11 mov (%r9),%edx + 400ccd: 01 16 add %edx,(%rsi) + 400ccf: 83 e0 0f and $0xf,%eax + 400cd2: 41 89 00 mov %eax,(%r8) + 400cd5: 5b pop %rbx + 400cd6: c3 retq + 400cd7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 400cde: 00 00 + +0000000000400ce0 <__libc_start_main>: + 400ce0: 41 55 push %r13 + 400ce2: 41 54 push %r12 + 400ce4: 31 c0 xor %eax,%eax + 400ce6: 55 push %rbp + 400ce7: 53 push %rbx + 400ce8: 48 89 d5 mov %rdx,%rbp + 400ceb: 49 89 cc mov %rcx,%r12 + 400cee: 41 89 f3 mov %esi,%r11d + 400cf1: 49 89 fa mov %rdi,%r10 + 400cf4: 48 83 ec 28 sub $0x28,%rsp + 400cf8: 0f a2 cpuid + 400cfa: 81 fb 47 65 6e 75 cmp $0x756e6547,%ebx + 400d00: 89 05 7e b9 2c 00 mov %eax,0x2cb97e(%rip) # 6cc684 <_dl_x86_cpu_features+0x4> + 400d06: c7 44 24 10 00 00 00 movl $0x0,0x10(%rsp) + 400d0d: 00 + 400d0e: 40 0f 94 c6 sete %sil + 400d12: 81 f9 6e 74 65 6c cmp $0x6c65746e,%ecx + 400d18: c7 44 24 14 00 00 00 movl $0x0,0x14(%rsp) + 400d1f: 00 + 400d20: 0f 94 c0 sete %al + 400d23: c7 44 24 18 00 00 00 movl $0x0,0x18(%rsp) + 400d2a: 00 + 400d2b: 40 84 c6 test %al,%sil + 400d2e: 74 0c je 400d3c <__libc_start_main+0x5c> + 400d30: 81 fa 69 6e 65 49 cmp $0x49656e69,%edx + 400d36: 0f 84 6d 01 00 00 je 400ea9 <__libc_start_main+0x1c9> + 400d3c: 81 fb 41 75 74 68 cmp $0x68747541,%ebx + 400d42: 40 0f 94 c6 sete %sil + 400d46: 81 f9 63 41 4d 44 cmp $0x444d4163,%ecx + 400d4c: 0f 94 c0 sete %al + 400d4f: 40 84 c6 test %al,%sil + 400d52: 74 0c je 400d60 <__libc_start_main+0x80> + 400d54: 81 fa 65 6e 74 69 cmp $0x69746e65,%edx + 400d5a: 0f 84 94 01 00 00 je 400ef4 <__libc_start_main+0x214> + 400d60: 44 8b 2d 29 b9 2c 00 mov 0x2cb929(%rip),%r13d # 6cc690 <_dl_x86_cpu_features+0x10> + 400d67: 8b 7c 24 14 mov 0x14(%rsp),%edi + 400d6b: be 03 00 00 00 mov $0x3,%esi + 400d70: 8b 05 1e b9 2c 00 mov 0x2cb91e(%rip),%eax # 6cc694 <_dl_x86_cpu_features+0x14> + 400d76: f6 c4 01 test $0x1,%ah + 400d79: 74 0a je 400d85 <__libc_start_main+0xa5> + 400d7b: 81 0d 3b b9 2c 00 00 orl $0x4000,0x2cb93b(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> + 400d82: 40 00 00 + 400d85: f6 c4 80 test $0x80,%ah + 400d88: 74 0a je 400d94 <__libc_start_main+0xb4> + 400d8a: 81 0d 2c b9 2c 00 00 orl $0x8000,0x2cb92c(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> + 400d91: 80 00 00 + 400d94: 83 3d e9 b8 2c 00 06 cmpl $0x6,0x2cb8e9(%rip) # 6cc684 <_dl_x86_cpu_features+0x4> + 400d9b: 7e 21 jle 400dbe <__libc_start_main+0xde> + 400d9d: b8 07 00 00 00 mov $0x7,%eax + 400da2: 31 c9 xor %ecx,%ecx + 400da4: 0f a2 cpuid + 400da6: 89 05 ec b8 2c 00 mov %eax,0x2cb8ec(%rip) # 6cc698 <_dl_x86_cpu_features+0x18> + 400dac: 89 1d ea b8 2c 00 mov %ebx,0x2cb8ea(%rip) # 6cc69c <_dl_x86_cpu_features+0x1c> + 400db2: 89 0d e8 b8 2c 00 mov %ecx,0x2cb8e8(%rip) # 6cc6a0 <_dl_x86_cpu_features+0x20> + 400db8: 89 15 e6 b8 2c 00 mov %edx,0x2cb8e6(%rip) # 6cc6a4 <_dl_x86_cpu_features+0x24> + 400dbe: 41 f7 c5 00 00 00 08 test $0x8000000,%r13d + 400dc5: 74 0f je 400dd6 <__libc_start_main+0xf6> + 400dc7: 31 c9 xor %ecx,%ecx + 400dc9: 0f 01 d0 xgetbv + 400dcc: 89 c2 mov %eax,%edx + 400dce: 83 e2 06 and $0x6,%edx + 400dd1: 83 fa 06 cmp $0x6,%edx + 400dd4: 74 6f je 400e45 <__libc_start_main+0x165> + 400dd6: 83 fe 01 cmp $0x1,%esi + 400dd9: 74 2f je 400e0a <__libc_start_main+0x12a> + 400ddb: 8b 44 24 10 mov 0x10(%rsp),%eax + 400ddf: 48 83 ec 08 sub $0x8,%rsp + 400de3: 89 3d d3 b8 2c 00 mov %edi,0x2cb8d3(%rip) # 6cc6bc <_dl_x86_cpu_features+0x3c> + 400de9: ff 74 24 58 pushq 0x58(%rsp) + 400ded: 89 35 8d b8 2c 00 mov %esi,0x2cb88d(%rip) # 6cc680 <_dl_x86_cpu_features> + 400df3: 4c 89 e1 mov %r12,%rcx + 400df6: 48 89 ea mov %rbp,%rdx + 400df9: 44 89 de mov %r11d,%esi + 400dfc: 4c 89 d7 mov %r10,%rdi + 400dff: 89 05 b3 b8 2c 00 mov %eax,0x2cb8b3(%rip) # 6cc6b8 <_dl_x86_cpu_features+0x38> + 400e05: e8 c6 fb ff ff callq 4009d0 + 400e0a: 83 7c 24 10 06 cmpl $0x6,0x10(%rsp) + 400e0f: 75 ca jne 400ddb <__libc_start_main+0xfb> + 400e11: 83 ff 3f cmp $0x3f,%edi + 400e14: 0f 84 7a 01 00 00 je 400f94 <__libc_start_main+0x2b4> + 400e1a: 83 ff 3c cmp $0x3c,%edi + 400e1d: 0f 84 0b 02 00 00 je 40102e <__libc_start_main+0x34e> + 400e23: 8d 47 bb lea -0x45(%rdi),%eax + 400e26: 83 f8 01 cmp $0x1,%eax + 400e29: 0f 86 3d 01 00 00 jbe 400f6c <__libc_start_main+0x28c> + 400e2f: 83 ff 3d cmp $0x3d,%edi + 400e32: 0f 85 4e 01 00 00 jne 400f86 <__libc_start_main+0x2a6> + 400e38: 83 7c 24 18 04 cmpl $0x4,0x18(%rsp) + 400e3d: 0f 86 34 01 00 00 jbe 400f77 <__libc_start_main+0x297> + 400e43: eb 96 jmp 400ddb <__libc_start_main+0xfb> + 400e45: 41 f7 c5 00 00 00 10 test $0x10000000,%r13d + 400e4c: 74 07 je 400e55 <__libc_start_main+0x175> + 400e4e: 83 0d 6b b8 2c 00 40 orl $0x40,0x2cb86b(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> + 400e55: 8b 15 41 b8 2c 00 mov 0x2cb841(%rip),%edx # 6cc69c <_dl_x86_cpu_features+0x1c> + 400e5b: f6 c2 20 test $0x20,%dl + 400e5e: 74 0a je 400e6a <__libc_start_main+0x18a> + 400e60: 81 0d 56 b8 2c 00 00 orl $0xc00,0x2cb856(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> + 400e67: 0c 00 00 + 400e6a: 25 e0 00 00 00 and $0xe0,%eax + 400e6f: 3d e0 00 00 00 cmp $0xe0,%eax + 400e74: 0f 84 8c 01 00 00 je 401006 <__libc_start_main+0x326> + 400e7a: 41 81 e5 00 10 00 00 and $0x1000,%r13d + 400e81: 74 0a je 400e8d <__libc_start_main+0x1ad> + 400e83: 81 0d 33 b8 2c 00 80 orl $0x80,0x2cb833(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> + 400e8a: 00 00 00 + 400e8d: f6 05 1e b8 2c 00 01 testb $0x1,0x2cb81e(%rip) # 6cc6b2 <_dl_x86_cpu_features+0x32> + 400e94: 0f 84 3c ff ff ff je 400dd6 <__libc_start_main+0xf6> + 400e9a: 81 0d 1c b8 2c 00 00 orl $0x100,0x2cb81c(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> + 400ea1: 01 00 00 + 400ea4: e9 2d ff ff ff jmpq 400dd6 <__libc_start_main+0xf6> + 400ea9: 48 8d 4c 24 18 lea 0x18(%rsp),%rcx + 400eae: 48 8d 54 24 1c lea 0x1c(%rsp),%rdx + 400eb3: 48 8d 74 24 14 lea 0x14(%rsp),%rsi + 400eb8: 48 8d 7c 24 10 lea 0x10(%rsp),%rdi + 400ebd: 4c 89 4c 24 08 mov %r9,0x8(%rsp) + 400ec2: 4c 89 04 24 mov %r8,(%rsp) + 400ec6: e8 a5 fd ff ff callq 400c70 + 400ecb: 83 7c 24 10 06 cmpl $0x6,0x10(%rsp) + 400ed0: 44 8b 2d b9 b7 2c 00 mov 0x2cb7b9(%rip),%r13d # 6cc690 <_dl_x86_cpu_features+0x10> + 400ed7: 4c 8b 04 24 mov (%rsp),%r8 + 400edb: 4c 8b 4c 24 08 mov 0x8(%rsp),%r9 + 400ee0: 0f 84 ba 00 00 00 je 400fa0 <__libc_start_main+0x2c0> + 400ee6: be 01 00 00 00 mov $0x1,%esi + 400eeb: 8b 7c 24 14 mov 0x14(%rsp),%edi + 400eef: e9 7c fe ff ff jmpq 400d70 <__libc_start_main+0x90> + 400ef4: 48 8d 4c 24 18 lea 0x18(%rsp),%rcx + 400ef9: 48 8d 54 24 1c lea 0x1c(%rsp),%rdx + 400efe: 48 8d 74 24 14 lea 0x14(%rsp),%rsi + 400f03: 48 8d 7c 24 10 lea 0x10(%rsp),%rdi + 400f08: 4c 89 4c 24 08 mov %r9,0x8(%rsp) + 400f0d: 4c 89 04 24 mov %r8,(%rsp) + 400f11: e8 5a fd ff ff callq 400c70 + 400f16: b8 00 00 00 80 mov $0x80000000,%eax + 400f1b: 4c 8b 04 24 mov (%rsp),%r8 + 400f1f: 4c 8b 4c 24 08 mov 0x8(%rsp),%r9 + 400f24: 0f a2 cpuid + 400f26: 3d 00 00 00 80 cmp $0x80000000,%eax + 400f2b: 76 1f jbe 400f4c <__libc_start_main+0x26c> + 400f2d: b8 01 00 00 80 mov $0x80000001,%eax + 400f32: 0f a2 cpuid + 400f34: 89 05 6e b7 2c 00 mov %eax,0x2cb76e(%rip) # 6cc6a8 <_dl_x86_cpu_features+0x28> + 400f3a: 89 1d 6c b7 2c 00 mov %ebx,0x2cb76c(%rip) # 6cc6ac <_dl_x86_cpu_features+0x2c> + 400f40: 89 0d 6a b7 2c 00 mov %ecx,0x2cb76a(%rip) # 6cc6b0 <_dl_x86_cpu_features+0x30> + 400f46: 89 15 68 b7 2c 00 mov %edx,0x2cb768(%rip) # 6cc6b4 <_dl_x86_cpu_features+0x34> + 400f4c: 83 7c 24 10 15 cmpl $0x15,0x10(%rsp) + 400f51: 8b 7c 24 14 mov 0x14(%rsp),%edi + 400f55: 0f 84 93 00 00 00 je 400fee <__libc_start_main+0x30e> + 400f5b: be 02 00 00 00 mov $0x2,%esi + 400f60: 44 8b 2d 29 b7 2c 00 mov 0x2cb729(%rip),%r13d # 6cc690 <_dl_x86_cpu_features+0x10> + 400f67: e9 04 fe ff ff jmpq 400d70 <__libc_start_main+0x90> + 400f6c: 83 7c 24 18 01 cmpl $0x1,0x18(%rsp) + 400f71: 0f 87 64 fe ff ff ja 400ddb <__libc_start_main+0xfb> + 400f77: 81 25 1b b7 2c 00 ef andl $0xfffff7ef,0x2cb71b(%rip) # 6cc69c <_dl_x86_cpu_features+0x1c> + 400f7e: f7 ff ff + 400f81: e9 55 fe ff ff jmpq 400ddb <__libc_start_main+0xfb> + 400f86: 83 ff 47 cmp $0x47,%edi + 400f89: 74 e1 je 400f6c <__libc_start_main+0x28c> + 400f8b: 83 ff 56 cmp $0x56,%edi + 400f8e: 0f 85 47 fe ff ff jne 400ddb <__libc_start_main+0xfb> + 400f94: 83 7c 24 18 02 cmpl $0x2,0x18(%rsp) + 400f99: 76 dc jbe 400f77 <__libc_start_main+0x297> + 400f9b: e9 3b fe ff ff jmpq 400ddb <__libc_start_main+0xfb> + 400fa0: 8b 44 24 1c mov 0x1c(%rsp),%eax + 400fa4: 03 44 24 14 add 0x14(%rsp),%eax + 400fa8: 83 f8 2f cmp $0x2f,%eax + 400fab: 89 44 24 14 mov %eax,0x14(%rsp) + 400faf: 0f 87 97 00 00 00 ja 40104c <__libc_start_main+0x36c> + 400fb5: 83 f8 2e cmp $0x2e,%eax + 400fb8: 0f 83 df 00 00 00 jae 40109d <__libc_start_main+0x3bd> + 400fbe: 83 f8 1f cmp $0x1f,%eax + 400fc1: 0f 87 b6 00 00 00 ja 40107d <__libc_start_main+0x39d> + 400fc7: 83 f8 1e cmp $0x1e,%eax + 400fca: 0f 83 cd 00 00 00 jae 40109d <__libc_start_main+0x3bd> + 400fd0: 83 f8 1a cmp $0x1a,%eax + 400fd3: 0f 84 c4 00 00 00 je 40109d <__libc_start_main+0x3bd> + 400fd9: 83 f8 1c cmp $0x1c,%eax + 400fdc: 0f 85 ae 00 00 00 jne 401090 <__libc_start_main+0x3b0> + 400fe2: 83 0d d7 b6 2c 00 04 orl $0x4,0x2cb6d7(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> + 400fe9: e9 f8 fe ff ff jmpq 400ee6 <__libc_start_main+0x206> + 400fee: 8d 47 a0 lea -0x60(%rdi),%eax + 400ff1: 83 f8 1f cmp $0x1f,%eax + 400ff4: 0f 87 61 ff ff ff ja 400f5b <__libc_start_main+0x27b> + 400ffa: 83 0d bf b6 2c 00 10 orl $0x10,0x2cb6bf(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> + 401001: e9 55 ff ff ff jmpq 400f5b <__libc_start_main+0x27b> + 401006: f7 c2 00 00 01 00 test $0x10000,%edx + 40100c: 0f 84 68 fe ff ff je 400e7a <__libc_start_main+0x19a> + 401012: 81 e2 00 00 02 00 and $0x20000,%edx + 401018: 8b 05 a2 b6 2c 00 mov 0x2cb6a2(%rip),%eax # 6cc6c0 <_dl_x86_cpu_features+0x40> + 40101e: 75 1e jne 40103e <__libc_start_main+0x35e> + 401020: 80 cc 10 or $0x10,%ah + 401023: 89 05 97 b6 2c 00 mov %eax,0x2cb697(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> + 401029: e9 4c fe ff ff jmpq 400e7a <__libc_start_main+0x19a> + 40102e: 83 7c 24 18 03 cmpl $0x3,0x18(%rsp) + 401033: 0f 86 3e ff ff ff jbe 400f77 <__libc_start_main+0x297> + 401039: e9 9d fd ff ff jmpq 400ddb <__libc_start_main+0xfb> + 40103e: 80 cc 30 or $0x30,%ah + 401041: 89 05 79 b6 2c 00 mov %eax,0x2cb679(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> + 401047: e9 2e fe ff ff jmpq 400e7a <__libc_start_main+0x19a> + 40104c: 83 f8 4d cmp $0x4d,%eax + 40104f: 74 62 je 4010b3 <__libc_start_main+0x3d3> + 401051: 76 56 jbe 4010a9 <__libc_start_main+0x3c9> + 401053: 83 f8 5a cmp $0x5a,%eax + 401056: 74 5b je 4010b3 <__libc_start_main+0x3d3> + 401058: 83 f8 5d cmp $0x5d,%eax + 40105b: 74 56 je 4010b3 <__libc_start_main+0x3d3> + 40105d: 83 f8 57 cmp $0x57,%eax + 401060: 75 2e jne 401090 <__libc_start_main+0x3b0> + 401062: 8b 05 58 b6 2c 00 mov 0x2cb658(%rip),%eax # 6cc6c0 <_dl_x86_cpu_features+0x40> + 401068: 0d 00 00 02 00 or $0x20000,%eax + 40106d: 0d 30 02 00 00 or $0x230,%eax + 401072: 89 05 48 b6 2c 00 mov %eax,0x2cb648(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> + 401078: e9 69 fe ff ff jmpq 400ee6 <__libc_start_main+0x206> + 40107d: 83 f8 26 cmp $0x26,%eax + 401080: 0f 84 5c ff ff ff je 400fe2 <__libc_start_main+0x302> + 401086: 83 f8 2c cmp $0x2c,%eax + 401089: 74 12 je 40109d <__libc_start_main+0x3bd> + 40108b: 83 f8 25 cmp $0x25,%eax + 40108e: 74 0d je 40109d <__libc_start_main+0x3bd> + 401090: 41 f7 c5 00 00 00 10 test $0x10000000,%r13d + 401097: 0f 84 49 fe ff ff je 400ee6 <__libc_start_main+0x206> + 40109d: 83 0d 1c b6 2c 00 33 orl $0x33,0x2cb61c(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> + 4010a4: e9 3d fe ff ff jmpq 400ee6 <__libc_start_main+0x206> + 4010a9: 83 f8 37 cmp $0x37,%eax + 4010ac: 74 05 je 4010b3 <__libc_start_main+0x3d3> + 4010ae: 83 f8 4a cmp $0x4a,%eax + 4010b1: 75 dd jne 401090 <__libc_start_main+0x3b0> + 4010b3: 8b 05 07 b6 2c 00 mov 0x2cb607(%rip),%eax # 6cc6c0 <_dl_x86_cpu_features+0x40> + 4010b9: eb b2 jmp 40106d <__libc_start_main+0x38d> + 4010bb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + +00000000004010c0 <__libc_check_standard_fds>: + 4010c0: 48 81 ec 98 00 00 00 sub $0x98,%rsp + 4010c7: 31 ff xor %edi,%edi + 4010c9: 31 c0 xor %eax,%eax + 4010cb: be 01 00 00 00 mov $0x1,%esi + 4010d0: e8 fb e1 03 00 callq 43f2d0 <__libc_fcntl> + 4010d5: 83 f8 ff cmp $0xffffffff,%eax + 4010d8: 74 3c je 401116 <__libc_check_standard_fds+0x56> + 4010da: 31 c0 xor %eax,%eax + 4010dc: be 01 00 00 00 mov $0x1,%esi + 4010e1: bf 01 00 00 00 mov $0x1,%edi + 4010e6: e8 e5 e1 03 00 callq 43f2d0 <__libc_fcntl> + 4010eb: 83 f8 ff cmp $0xffffffff,%eax + 4010ee: 0f 84 8f 00 00 00 je 401183 <__libc_check_standard_fds+0xc3> + 4010f4: 31 c0 xor %eax,%eax + 4010f6: be 01 00 00 00 mov $0x1,%esi + 4010fb: bf 02 00 00 00 mov $0x2,%edi + 401100: e8 cb e1 03 00 callq 43f2d0 <__libc_fcntl> + 401105: 83 f8 ff cmp $0xffffffff,%eax + 401108: 0f 84 e5 00 00 00 je 4011f3 <__libc_check_standard_fds+0x133> + 40110e: 48 81 c4 98 00 00 00 add $0x98,%rsp + 401115: c3 retq + 401116: 49 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%r8 + 40111d: 64 41 83 38 09 cmpl $0x9,%fs:(%r8) + 401122: 75 b6 jne 4010da <__libc_check_standard_fds+0x1a> + 401124: 31 d2 xor %edx,%edx + 401126: be 01 00 02 00 mov $0x20001,%esi + 40112b: bf 83 0f 4a 00 mov $0x4a0f83,%edi + 401130: b8 02 00 00 00 mov $0x2,%eax + 401135: 0f 05 syscall + 401137: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 40113d: 0f 87 20 01 00 00 ja 401263 <__libc_check_standard_fds+0x1a3> + 401143: 85 c0 test %eax,%eax + 401145: 75 39 jne 401180 <__libc_check_standard_fds+0xc0> + 401147: 31 f6 xor %esi,%esi + 401149: 48 89 e2 mov %rsp,%rdx + 40114c: bf 01 00 00 00 mov $0x1,%edi + 401151: e8 7a df 03 00 callq 43f0d0 <__fxstat> + 401156: 85 c0 test %eax,%eax + 401158: 75 26 jne 401180 <__libc_check_standard_fds+0xc0> + 40115a: 8b 44 24 18 mov 0x18(%rsp),%eax + 40115e: 25 00 f0 00 00 and $0xf000,%eax + 401163: 3d 00 20 00 00 cmp $0x2000,%eax + 401168: 75 16 jne 401180 <__libc_check_standard_fds+0xc0> + 40116a: 48 81 7c 24 28 07 01 cmpq $0x107,0x28(%rsp) + 401171: 00 00 + 401173: 0f 84 61 ff ff ff je 4010da <__libc_check_standard_fds+0x1a> + 401179: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 401180: f4 hlt + 401181: eb fd jmp 401180 <__libc_check_standard_fds+0xc0> + 401183: 49 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%r8 + 40118a: 64 41 83 38 09 cmpl $0x9,%fs:(%r8) + 40118f: 0f 85 5f ff ff ff jne 4010f4 <__libc_check_standard_fds+0x34> + 401195: 31 d2 xor %edx,%edx + 401197: be 00 00 02 00 mov $0x20000,%esi + 40119c: bf 8d 0f 4a 00 mov $0x4a0f8d,%edi + 4011a1: b8 02 00 00 00 mov $0x2,%eax + 4011a6: 0f 05 syscall + 4011a8: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 4011ae: 0f 87 c2 00 00 00 ja 401276 <__libc_check_standard_fds+0x1b6> + 4011b4: 83 f8 01 cmp $0x1,%eax + 4011b7: 75 37 jne 4011f0 <__libc_check_standard_fds+0x130> + 4011b9: 48 89 e2 mov %rsp,%rdx + 4011bc: be 01 00 00 00 mov $0x1,%esi + 4011c1: bf 01 00 00 00 mov $0x1,%edi + 4011c6: e8 05 df 03 00 callq 43f0d0 <__fxstat> + 4011cb: 85 c0 test %eax,%eax + 4011cd: 75 21 jne 4011f0 <__libc_check_standard_fds+0x130> + 4011cf: 8b 44 24 18 mov 0x18(%rsp),%eax + 4011d3: 25 00 f0 00 00 and $0xf000,%eax + 4011d8: 3d 00 20 00 00 cmp $0x2000,%eax + 4011dd: 75 11 jne 4011f0 <__libc_check_standard_fds+0x130> + 4011df: 48 81 7c 24 28 03 01 cmpq $0x103,0x28(%rsp) + 4011e6: 00 00 + 4011e8: 0f 84 06 ff ff ff je 4010f4 <__libc_check_standard_fds+0x34> + 4011ee: 66 90 xchg %ax,%ax + 4011f0: f4 hlt + 4011f1: eb fd jmp 4011f0 <__libc_check_standard_fds+0x130> + 4011f3: 49 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%r8 + 4011fa: 64 41 83 38 09 cmpl $0x9,%fs:(%r8) + 4011ff: 0f 85 09 ff ff ff jne 40110e <__libc_check_standard_fds+0x4e> + 401205: 31 d2 xor %edx,%edx + 401207: be 00 00 02 00 mov $0x20000,%esi + 40120c: bf 8d 0f 4a 00 mov $0x4a0f8d,%edi + 401211: b8 02 00 00 00 mov $0x2,%eax + 401216: 0f 05 syscall + 401218: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 40121e: 77 4e ja 40126e <__libc_check_standard_fds+0x1ae> + 401220: 83 f8 02 cmp $0x2,%eax + 401223: 75 3b jne 401260 <__libc_check_standard_fds+0x1a0> + 401225: 48 89 e2 mov %rsp,%rdx + 401228: be 02 00 00 00 mov $0x2,%esi + 40122d: bf 01 00 00 00 mov $0x1,%edi + 401232: e8 99 de 03 00 callq 43f0d0 <__fxstat> + 401237: 85 c0 test %eax,%eax + 401239: 75 25 jne 401260 <__libc_check_standard_fds+0x1a0> + 40123b: 8b 44 24 18 mov 0x18(%rsp),%eax + 40123f: 25 00 f0 00 00 and $0xf000,%eax + 401244: 3d 00 20 00 00 cmp $0x2000,%eax + 401249: 75 15 jne 401260 <__libc_check_standard_fds+0x1a0> + 40124b: 48 81 7c 24 28 03 01 cmpq $0x103,0x28(%rsp) + 401252: 00 00 + 401254: 0f 84 b4 fe ff ff je 40110e <__libc_check_standard_fds+0x4e> + 40125a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 401260: f4 hlt + 401261: eb fd jmp 401260 <__libc_check_standard_fds+0x1a0> + 401263: f7 d8 neg %eax + 401265: 64 41 89 00 mov %eax,%fs:(%r8) + 401269: e9 12 ff ff ff jmpq 401180 <__libc_check_standard_fds+0xc0> + 40126e: f7 d8 neg %eax + 401270: 64 41 89 00 mov %eax,%fs:(%r8) + 401274: eb ea jmp 401260 <__libc_check_standard_fds+0x1a0> + 401276: f7 d8 neg %eax + 401278: 64 41 89 00 mov %eax,%fs:(%r8) + 40127c: e9 6f ff ff ff jmpq 4011f0 <__libc_check_standard_fds+0x130> + 401281: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 401288: 00 00 00 + 40128b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + +0000000000401290 <__libc_setup_tls>: + 401290: 41 57 push %r15 + 401292: 41 56 push %r14 + 401294: 41 55 push %r13 + 401296: 41 54 push %r12 + 401298: 55 push %rbp + 401299: 53 push %rbx + 40129a: 48 89 f3 mov %rsi,%rbx + 40129d: 48 83 ec 18 sub $0x18,%rsp + 4012a1: 48 8b 15 a0 bf 2c 00 mov 0x2cbfa0(%rip),%rdx # 6cd248 <_dl_phdr> + 4012a8: 48 85 d2 test %rdx,%rdx + 4012ab: 74 53 je 401300 <__libc_setup_tls+0x70> + 4012ad: 48 8b 05 cc bf 2c 00 mov 0x2cbfcc(%rip),%rax # 6cd280 <_dl_phnum> + 4012b4: 48 8d 0c c5 00 00 00 lea 0x0(,%rax,8),%rcx + 4012bb: 00 + 4012bc: 48 c1 e0 06 shl $0x6,%rax + 4012c0: 48 29 c8 sub %rcx,%rax + 4012c3: 48 01 d0 add %rdx,%rax + 4012c6: 48 39 c2 cmp %rax,%rdx + 4012c9: 72 0e jb 4012d9 <__libc_setup_tls+0x49> + 4012cb: eb 33 jmp 401300 <__libc_setup_tls+0x70> + 4012cd: 0f 1f 00 nopl (%rax) + 4012d0: 48 83 c2 38 add $0x38,%rdx + 4012d4: 48 39 c2 cmp %rax,%rdx + 4012d7: 73 27 jae 401300 <__libc_setup_tls+0x70> + 4012d9: 83 3a 07 cmpl $0x7,(%rdx) + 4012dc: 75 f2 jne 4012d0 <__libc_setup_tls+0x40> + 4012de: 4c 8b 72 30 mov 0x30(%rdx),%r14 + 4012e2: 48 8b 6a 28 mov 0x28(%rdx),%rbp + 4012e6: 4c 8b 62 20 mov 0x20(%rdx),%r12 + 4012ea: 4c 8b 6a 10 mov 0x10(%rdx),%r13 + 4012ee: 4c 39 f3 cmp %r14,%rbx + 4012f1: 49 0f 42 de cmovb %r14,%rbx + 4012f5: eb 14 jmp 40130b <__libc_setup_tls+0x7b> + 4012f7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 4012fe: 00 00 + 401300: 45 31 f6 xor %r14d,%r14d + 401303: 45 31 ed xor %r13d,%r13d + 401306: 45 31 e4 xor %r12d,%r12d + 401309: 31 ed xor %ebp,%ebp + 40130b: 48 89 e8 mov %rbp,%rax + 40130e: 48 03 05 7b 8d 2c 00 add 0x2c8d7b(%rip),%rax # 6ca090 <_dl_tls_static_size> + 401315: 31 d2 xor %edx,%edx + 401317: 48 01 df add %rbx,%rdi + 40131a: 48 8d 44 18 ff lea -0x1(%rax,%rbx,1),%rax + 40131f: 48 f7 f3 div %rbx + 401322: 48 0f af c3 imul %rbx,%rax + 401326: 48 01 c7 add %rax,%rdi + 401329: 49 89 c7 mov %rax,%r15 + 40132c: e8 bf e7 03 00 callq 43faf0 <__sbrk> + 401331: 48 8d 74 18 ff lea -0x1(%rax,%rbx,1),%rsi + 401336: 48 89 d8 mov %rbx,%rax + 401339: 48 c7 05 3c ba 2c 00 movq $0x3e,0x2cba3c(%rip) # 6ccd80 <_dl_static_dtv> + 401340: 3e 00 00 00 + 401344: 48 f7 d8 neg %rax + 401347: 4c 8b 0d 72 9e 2c 00 mov 0x2c9e72(%rip),%r9 # 6cb1c0 <_dl_ns> + 40134e: 48 89 f1 mov %rsi,%rcx + 401351: 48 21 c1 and %rax,%rcx + 401354: 4d 85 f6 test %r14,%r14 + 401357: 74 77 je 4013d0 <__libc_setup_tls+0x140> + 401359: 4a 8d 44 35 ff lea -0x1(%rbp,%r14,1),%rax + 40135e: 31 d2 xor %edx,%edx + 401360: 4c 89 ff mov %r15,%rdi + 401363: 49 f7 f6 div %r14 + 401366: 49 0f af c6 imul %r14,%rax + 40136a: 48 29 c7 sub %rax,%rdi + 40136d: 48 01 cf add %rcx,%rdi + 401370: 4c 89 ee mov %r13,%rsi + 401373: 49 89 81 40 04 00 00 mov %rax,0x440(%r9) + 40137a: 4c 89 e2 mov %r12,%rdx + 40137d: 48 89 0c 24 mov %rcx,(%rsp) + 401381: 48 89 3d 18 ba 2c 00 mov %rdi,0x2cba18(%rip) # 6ccda0 <_dl_static_dtv+0x20> + 401388: 4c 89 4c 24 08 mov %r9,0x8(%rsp) + 40138d: c6 05 14 ba 2c 00 01 movb $0x1,0x2cba14(%rip) # 6ccda8 <_dl_static_dtv+0x28> + 401394: e8 87 ac 02 00 callq 42c020 + 401399: 48 8b 0c 24 mov (%rsp),%rcx + 40139d: bf 02 10 00 00 mov $0x1002,%edi + 4013a2: b8 9e 00 00 00 mov $0x9e,%eax + 4013a7: 4a 8d 34 39 lea (%rcx,%r15,1),%rsi + 4013ab: 48 c7 46 08 90 cd 6c movq $0x6ccd90,0x8(%rsi) + 4013b2: 00 + 4013b3: 48 89 36 mov %rsi,(%rsi) + 4013b6: 48 89 76 10 mov %rsi,0x10(%rsi) + 4013ba: 0f 05 syscall + 4013bc: 85 c0 test %eax,%eax + 4013be: 74 20 je 4013e0 <__libc_setup_tls+0x150> + 4013c0: bf 98 0f 4a 00 mov $0x4a0f98,%edi + 4013c5: e8 c6 04 01 00 callq 411890 <__libc_fatal> + 4013ca: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4013d0: 4c 89 ff mov %r15,%rdi + 4013d3: 48 89 e8 mov %rbp,%rax + 4013d6: 48 29 ef sub %rbp,%rdi + 4013d9: 48 01 cf add %rcx,%rdi + 4013dc: eb 92 jmp 401370 <__libc_setup_tls+0xe0> + 4013de: 66 90 xchg %ax,%ax + 4013e0: 4c 8b 4c 24 08 mov 0x8(%rsp),%r9 + 4013e5: 4d 85 f6 test %r14,%r14 + 4013e8: 48 c7 05 cd a7 2c 00 movq $0x40,0x2ca7cd(%rip) # 6cbbc0 + 4013ef: 40 00 00 00 + 4013f3: 48 c7 05 72 b9 2c 00 movq $0x1,0x2cb972(%rip) # 6ccd70 <_dl_tls_max_dtv_idx> + 4013fa: 01 00 00 00 + 4013fe: 48 c7 05 77 bd 2c 00 movq $0x6cbbc0,0x2cbd77(%rip) # 6cd180 <_dl_tls_dtv_slotinfo_list> + 401405: c0 bb 6c 00 + 401409: 4d 89 b1 30 04 00 00 mov %r14,0x430(%r9) + 401410: 49 89 a9 28 04 00 00 mov %rbp,0x428(%r9) + 401417: 4d 89 a9 18 04 00 00 mov %r13,0x418(%r9) + 40141e: 4d 89 a1 20 04 00 00 mov %r12,0x420(%r9) + 401425: 49 c7 81 48 04 00 00 movq $0x1,0x448(%r9) + 40142c: 01 00 00 00 + 401430: 4c 89 0d b1 a7 2c 00 mov %r9,0x2ca7b1(%rip) # 6cbbe8 + 401437: 75 67 jne 4014a0 <__libc_setup_tls+0x210> + 401439: 48 89 e8 mov %rbp,%rax + 40143c: ba 01 00 00 00 mov $0x1,%edx + 401441: 48 0f af c2 imul %rdx,%rax + 401445: 48 8b 15 44 8c 2c 00 mov 0x2c8c44(%rip),%rdx # 6ca090 <_dl_tls_static_size> + 40144c: 48 c7 05 41 bd 2c 00 movq $0x1,0x2cbd41(%rip) # 6cd198 <_dl_tls_static_nelem> + 401453: 01 00 00 00 + 401457: 48 8d 54 10 3f lea 0x3f(%rax,%rdx,1),%rdx + 40145c: 48 89 05 fd b8 2c 00 mov %rax,0x2cb8fd(%rip) # 6ccd60 <_dl_tls_static_used> + 401463: b8 40 00 00 00 mov $0x40,%eax + 401468: 48 83 e2 c0 and $0xffffffffffffffc0,%rdx + 40146c: 48 81 c2 00 09 00 00 add $0x900,%rdx + 401473: 48 83 fb 40 cmp $0x40,%rbx + 401477: 48 0f 42 d8 cmovb %rax,%rbx + 40147b: 48 89 15 0e 8c 2c 00 mov %rdx,0x2c8c0e(%rip) # 6ca090 <_dl_tls_static_size> + 401482: 48 89 1d df b8 2c 00 mov %rbx,0x2cb8df(%rip) # 6ccd68 <_dl_tls_static_align> + 401489: 48 83 c4 18 add $0x18,%rsp + 40148d: 5b pop %rbx + 40148e: 5d pop %rbp + 40148f: 41 5c pop %r12 + 401491: 41 5d pop %r13 + 401493: 41 5e pop %r14 + 401495: 41 5f pop %r15 + 401497: c3 retq + 401498: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 40149f: 00 + 4014a0: 4a 8d 44 35 ff lea -0x1(%rbp,%r14,1),%rax + 4014a5: 31 d2 xor %edx,%edx + 4014a7: 49 f7 f6 div %r14 + 4014aa: 4c 89 f2 mov %r14,%rdx + 4014ad: eb 92 jmp 401441 <__libc_setup_tls+0x1b1> + 4014af: 90 nop + +00000000004014b0 <_dl_tls_setup>: + 4014b0: 48 8b 05 d9 8b 2c 00 mov 0x2c8bd9(%rip),%rax # 6ca090 <_dl_tls_static_size> + 4014b7: 48 c7 05 fe a6 2c 00 movq $0x40,0x2ca6fe(%rip) # 6cbbc0 + 4014be: 40 00 00 00 + 4014c2: 48 c7 05 a3 b8 2c 00 movq $0x1,0x2cb8a3(%rip) # 6ccd70 <_dl_tls_max_dtv_idx> + 4014c9: 01 00 00 00 + 4014cd: 48 c7 05 a8 bc 2c 00 movq $0x6cbbc0,0x2cbca8(%rip) # 6cd180 <_dl_tls_dtv_slotinfo_list> + 4014d4: c0 bb 6c 00 + 4014d8: 48 c7 05 7d b8 2c 00 movq $0x900,0x2cb87d(%rip) # 6ccd60 <_dl_tls_static_used> + 4014df: 00 09 00 00 + 4014e3: 48 c7 05 7a b8 2c 00 movq $0x40,0x2cb87a(%rip) # 6ccd68 <_dl_tls_static_align> + 4014ea: 40 00 00 00 + 4014ee: 48 05 3f 09 00 00 add $0x93f,%rax + 4014f4: 48 c7 05 99 bc 2c 00 movq $0x1,0x2cbc99(%rip) # 6cd198 <_dl_tls_static_nelem> + 4014fb: 01 00 00 00 + 4014ff: 48 83 e0 c0 and $0xffffffffffffffc0,%rax + 401503: 48 05 00 09 00 00 add $0x900,%rax + 401509: 48 89 05 80 8b 2c 00 mov %rax,0x2c8b80(%rip) # 6ca090 <_dl_tls_static_size> + 401510: 31 c0 xor %eax,%eax + 401512: c3 retq + 401513: 0f 1f 00 nopl (%rax) + 401516: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 40151d: 00 00 00 + +0000000000401520 <__pthread_initialize_minimal>: + 401520: be 40 00 00 00 mov $0x40,%esi + 401525: bf 00 09 00 00 mov $0x900,%edi + 40152a: e9 61 fd ff ff jmpq 401290 <__libc_setup_tls> + 40152f: 90 nop + +0000000000401530 <__libc_csu_init>: + 401530: 41 56 push %r14 + 401532: 41 be d8 9e 6c 00 mov $0x6c9ed8,%r14d + 401538: 41 55 push %r13 + 40153a: 49 81 ee d8 9e 6c 00 sub $0x6c9ed8,%r14 + 401541: 41 54 push %r12 + 401543: 55 push %rbp + 401544: 49 c1 fe 03 sar $0x3,%r14 + 401548: 53 push %rbx + 401549: 31 db xor %ebx,%ebx + 40154b: 4d 85 f6 test %r14,%r14 + 40154e: 89 fd mov %edi,%ebp + 401550: 49 89 f4 mov %rsi,%r12 + 401553: 49 89 d5 mov %rdx,%r13 + 401556: 74 20 je 401578 <__libc_csu_init+0x48> + 401558: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 40155f: 00 + 401560: 4c 89 ea mov %r13,%rdx + 401563: 4c 89 e6 mov %r12,%rsi + 401566: 89 ef mov %ebp,%edi + 401568: ff 14 dd d8 9e 6c 00 callq *0x6c9ed8(,%rbx,8) + 40156f: 48 83 c3 01 add $0x1,%rbx + 401573: 4c 39 f3 cmp %r14,%rbx + 401576: 75 e8 jne 401560 <__libc_csu_init+0x30> + 401578: 41 be e8 9e 6c 00 mov $0x6c9ee8,%r14d + 40157e: 31 db xor %ebx,%ebx + 401580: 49 81 ee d8 9e 6c 00 sub $0x6c9ed8,%r14 + 401587: 49 c1 fe 03 sar $0x3,%r14 + 40158b: e8 38 ed ff ff callq 4002c8 <__rela_iplt_end> + 401590: 4d 85 f6 test %r14,%r14 + 401593: 74 1b je 4015b0 <__libc_csu_init+0x80> + 401595: 0f 1f 00 nopl (%rax) + 401598: 4c 89 ea mov %r13,%rdx + 40159b: 4c 89 e6 mov %r12,%rsi + 40159e: 89 ef mov %ebp,%edi + 4015a0: ff 14 dd d8 9e 6c 00 callq *0x6c9ed8(,%rbx,8) + 4015a7: 48 83 c3 01 add $0x1,%rbx + 4015ab: 4c 39 f3 cmp %r14,%rbx + 4015ae: 75 e8 jne 401598 <__libc_csu_init+0x68> + 4015b0: 5b pop %rbx + 4015b1: 5d pop %rbp + 4015b2: 41 5c pop %r12 + 4015b4: 41 5d pop %r13 + 4015b6: 41 5e pop %r14 + 4015b8: c3 retq + 4015b9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + +00000000004015c0 <__libc_csu_fini>: + 4015c0: 53 push %rbx + 4015c1: bb f8 9e 6c 00 mov $0x6c9ef8,%ebx + 4015c6: 48 81 eb e8 9e 6c 00 sub $0x6c9ee8,%rbx + 4015cd: 48 c1 fb 03 sar $0x3,%rbx + 4015d1: 48 85 db test %rbx,%rbx + 4015d4: 74 17 je 4015ed <__libc_csu_fini+0x2d> + 4015d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4015dd: 00 00 00 + 4015e0: ff 14 dd e0 9e 6c 00 callq *0x6c9ee0(,%rbx,8) + 4015e7: 48 83 eb 01 sub $0x1,%rbx + 4015eb: 75 f3 jne 4015e0 <__libc_csu_fini+0x20> + 4015ed: 5b pop %rbx + 4015ee: e9 ad f8 09 00 jmpq 4a0ea0 <_fini> + 4015f3: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4015fa: 00 00 00 + 4015fd: 0f 1f 00 nopl (%rax) + +0000000000401600 <__assert_fail_base>: + 401600: 41 56 push %r14 + 401602: 41 55 push %r13 + 401604: b8 00 00 00 00 mov $0x0,%eax + 401609: 41 54 push %r12 + 40160b: 55 push %rbp + 40160c: 49 89 f6 mov %rsi,%r14 + 40160f: 53 push %rbx + 401610: 48 89 fd mov %rdi,%rbp + 401613: 49 89 d4 mov %rdx,%r12 + 401616: 41 89 cd mov %ecx,%r13d + 401619: 4c 89 c3 mov %r8,%rbx + 40161c: 48 83 ec 10 sub $0x10,%rsp + 401620: 48 85 c0 test %rax,%rax + 401623: 74 09 je 40162e <__assert_fail_base+0x2e> + 401625: 31 f6 xor %esi,%esi + 401627: bf 01 00 00 00 mov $0x1,%edi + 40162c: ff d0 callq *%rax + 40162e: 48 8b 3d ab 9a 2c 00 mov 0x2c9aab(%rip),%rdi # 6cb0e0 <__progname> + 401635: be 25 67 4b 00 mov $0x4b6725,%esi + 40163a: b8 6f 52 4b 00 mov $0x4b526f,%eax + 40163f: 48 85 db test %rbx,%rbx + 401642: 48 89 f2 mov %rsi,%rdx + 401645: 48 89 c1 mov %rax,%rcx + 401648: 48 0f 44 ce cmove %rsi,%rcx + 40164c: 48 0f 45 d3 cmovne %rbx,%rdx + 401650: 45 89 e9 mov %r13d,%r9d + 401653: 80 3f 00 cmpb $0x0,(%rdi) + 401656: 4d 89 e0 mov %r12,%r8 + 401659: 48 0f 44 c6 cmove %rsi,%rax + 40165d: 48 8d 74 24 04 lea 0x4(%rsp),%rsi + 401662: 56 push %rsi + 401663: 41 56 push %r14 + 401665: 48 89 ee mov %rbp,%rsi + 401668: 51 push %rcx + 401669: 52 push %rdx + 40166a: 48 89 fa mov %rdi,%rdx + 40166d: 48 89 c1 mov %rax,%rcx + 401670: 31 c0 xor %eax,%eax + 401672: 48 8d 7c 24 28 lea 0x28(%rsp),%rdi + 401677: e8 84 dc 00 00 callq 40f300 <___asprintf> + 40167c: 48 83 c4 20 add $0x20,%rsp + 401680: 85 c0 test %eax,%eax + 401682: 0f 88 93 00 00 00 js 40171b <__assert_fail_base+0x11b> + 401688: 48 8b 54 24 08 mov 0x8(%rsp),%rdx + 40168d: be 99 c4 4b 00 mov $0x4bc499,%esi + 401692: 31 ff xor %edi,%edi + 401694: 31 c0 xor %eax,%eax + 401696: e8 f5 dc 00 00 callq 40f390 <__fxprintf> + 40169b: 48 8b 3d 96 90 2c 00 mov 0x2c9096(%rip),%rdi # 6ca738 <_IO_stderr> + 4016a2: e8 99 e0 00 00 callq 40f740 <_IO_fflush> + 4016a7: 48 8b 05 d2 9a 2c 00 mov 0x2c9ad2(%rip),%rax # 6cb180 <_dl_pagesize> + 4016ae: 8b 74 24 04 mov 0x4(%rsp),%esi + 4016b2: 45 31 c9 xor %r9d,%r9d + 4016b5: 31 ff xor %edi,%edi + 4016b7: 41 b8 ff ff ff ff mov $0xffffffff,%r8d + 4016bd: b9 22 00 00 00 mov $0x22,%ecx + 4016c2: ba 03 00 00 00 mov $0x3,%edx + 4016c7: 01 c6 add %eax,%esi + 4016c9: f7 d8 neg %eax + 4016cb: 21 c6 and %eax,%esi + 4016cd: 89 74 24 04 mov %esi,0x4(%rsp) + 4016d1: 48 63 f6 movslq %esi,%rsi + 4016d4: e8 17 e5 03 00 callq 43fbf0 <__mmap> + 4016d9: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 4016dd: 48 89 c3 mov %rax,%rbx + 4016e0: 74 2a je 40170c <__assert_fail_base+0x10c> + 4016e2: 8b 44 24 04 mov 0x4(%rsp),%eax + 4016e6: 48 8b 74 24 08 mov 0x8(%rsp),%rsi + 4016eb: 48 8d 7b 04 lea 0x4(%rbx),%rdi + 4016ef: 89 03 mov %eax,(%rbx) + 4016f1: e8 fa eb ff ff callq 4002f0 <__rela_iplt_end+0x28> + 4016f6: 48 89 df mov %rbx,%rdi + 4016f9: 48 87 3d 20 aa 2c 00 xchg %rdi,0x2caa20(%rip) # 6cc120 <__abort_msg> + 401700: 48 85 ff test %rdi,%rdi + 401703: 74 07 je 40170c <__assert_fail_base+0x10c> + 401705: 8b 37 mov (%rdi),%esi + 401707: e8 a4 e5 03 00 callq 43fcb0 <__munmap> + 40170c: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi + 401711: e8 9a c6 01 00 callq 41ddb0 <__cfree> + 401716: e8 e5 c4 00 00 callq 40dc00 + 40171b: ba 12 00 00 00 mov $0x12,%edx + 401720: be 00 10 4a 00 mov $0x4a1000,%esi + 401725: bf 02 00 00 00 mov $0x2,%edi + 40172a: e8 b1 da 03 00 callq 43f1e0 <__libc_write> + 40172f: eb e5 jmp 401716 <__assert_fail_base+0x116> + 401731: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 401736: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 40173d: 00 00 00 + +0000000000401740 <__assert_fail>: + 401740: 41 55 push %r13 + 401742: 41 54 push %r12 + 401744: 49 89 cd mov %rcx,%r13 + 401747: 55 push %rbp + 401748: 53 push %rbx + 401749: 48 89 f5 mov %rsi,%rbp + 40174c: 48 89 fb mov %rdi,%rbx + 40174f: 41 89 d4 mov %edx,%r12d + 401752: be d0 0f 4a 00 mov $0x4a0fd0,%esi + 401757: ba 05 00 00 00 mov $0x5,%edx + 40175c: bf 5c 26 4b 00 mov $0x4b265c,%edi + 401761: 48 83 ec 08 sub $0x8,%rsp + 401765: e8 16 00 00 00 callq 401780 <__dcgettext> + 40176a: 4d 89 e8 mov %r13,%r8 + 40176d: 44 89 e1 mov %r12d,%ecx + 401770: 48 89 ea mov %rbp,%rdx + 401773: 48 89 de mov %rbx,%rsi + 401776: 48 89 c7 mov %rax,%rdi + 401779: e8 82 fe ff ff callq 401600 <__assert_fail_base> + 40177e: 66 90 xchg %ax,%ax + +0000000000401780 <__dcgettext>: + 401780: 41 89 d1 mov %edx,%r9d + 401783: 45 31 c0 xor %r8d,%r8d + 401786: 31 c9 xor %ecx,%ecx + 401788: 31 d2 xor %edx,%edx + 40178a: e9 e1 13 00 00 jmpq 402b70 <__dcigettext> + 40178f: 90 nop + +0000000000401790 : + 401790: 55 push %rbp + 401791: 53 push %rbx + 401792: 48 89 fd mov %rdi,%rbp + 401795: 48 89 f3 mov %rsi,%rbx + 401798: 48 83 ec 08 sub $0x8,%rsp + 40179c: 48 83 7e 20 00 cmpq $0x0,0x20(%rsi) + 4017a1: 74 5d je 401800 + 4017a3: 48 8d 76 38 lea 0x38(%rsi),%rsi + 4017a7: 48 83 7d 20 00 cmpq $0x0,0x20(%rbp) + 4017ac: 74 42 je 4017f0 + 4017ae: 48 8d 7d 38 lea 0x38(%rbp),%rdi + 4017b2: e8 a9 eb ff ff callq 400360 <__rela_iplt_end+0x98> + 4017b7: 85 c0 test %eax,%eax + 4017b9: 75 27 jne 4017e2 + 4017bb: 48 8b 33 mov (%rbx),%rsi + 4017be: 48 8b 7d 00 mov 0x0(%rbp),%rdi + 4017c2: e8 99 eb ff ff callq 400360 <__rela_iplt_end+0x98> + 4017c7: 85 c0 test %eax,%eax + 4017c9: 75 17 jne 4017e2 + 4017cb: 48 8b 73 10 mov 0x10(%rbx),%rsi + 4017cf: 48 8b 7d 10 mov 0x10(%rbp),%rdi + 4017d3: e8 88 eb ff ff callq 400360 <__rela_iplt_end+0x98> + 4017d8: 85 c0 test %eax,%eax + 4017da: 75 06 jne 4017e2 + 4017dc: 8b 45 08 mov 0x8(%rbp),%eax + 4017df: 2b 43 08 sub 0x8(%rbx),%eax + 4017e2: 48 83 c4 08 add $0x8,%rsp + 4017e6: 5b pop %rbx + 4017e7: 5d pop %rbp + 4017e8: c3 retq + 4017e9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4017f0: 48 8b 7d 38 mov 0x38(%rbp),%rdi + 4017f4: eb bc jmp 4017b2 + 4017f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4017fd: 00 00 00 + 401800: 48 8b 76 38 mov 0x38(%rsi),%rsi + 401804: eb a1 jmp 4017a7 + 401806: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 40180d: 00 00 00 + +0000000000401810 : + 401810: 41 57 push %r15 + 401812: 41 56 push %r14 + 401814: 41 55 push %r13 + 401816: 41 54 push %r12 + 401818: 49 89 f4 mov %rsi,%r12 + 40181b: 55 push %rbp + 40181c: 53 push %rbx + 40181d: 48 89 fb mov %rdi,%rbx + 401820: 48 83 ec 08 sub $0x8,%rsp + 401824: 8b 03 mov (%rbx),%eax + 401826: 83 f8 01 cmp $0x1,%eax + 401829: 0f 84 f9 00 00 00 je 401928 + 40182f: 0f 8e d3 00 00 00 jle 401908 + 401835: 83 f8 02 cmp $0x2,%eax + 401838: 74 56 je 401890 + 40183a: 83 f8 03 cmp $0x3,%eax + 40183d: 0f 85 ad 00 00 00 jne 4018f0 + 401843: 4c 8b 6b 08 mov 0x8(%rbx),%r13 + 401847: 41 8b 6d 00 mov 0x0(%r13),%ebp + 40184b: 83 fd 01 cmp $0x1,%ebp + 40184e: 0f 84 2c 02 00 00 je 401a80 + 401854: 0f 8e 16 01 00 00 jle 401970 + 40185a: 83 fd 02 cmp $0x2,%ebp + 40185d: 0f 84 45 02 00 00 je 401aa8 + 401863: 83 fd 03 cmp $0x3,%ebp + 401866: 0f 85 74 01 00 00 jne 4019e0 + 40186c: 49 8b 7d 08 mov 0x8(%r13),%rdi + 401870: 4c 89 e6 mov %r12,%rsi + 401873: e8 98 ff ff ff callq 401810 + 401878: 48 83 f8 01 cmp $0x1,%rax + 40187c: 19 c0 sbb %eax,%eax + 40187e: f7 d0 not %eax + 401880: 83 c0 02 add $0x2,%eax + 401883: 48 98 cltq + 401885: 4d 8b 6c c5 08 mov 0x8(%r13,%rax,8),%r13 + 40188a: eb bb jmp 401847 + 40188c: 0f 1f 40 00 nopl 0x0(%rax) + 401890: 48 8b 6b 08 mov 0x8(%rbx),%rbp + 401894: 8b 45 00 mov 0x0(%rbp),%eax + 401897: 83 f8 01 cmp $0x1,%eax + 40189a: 0f 84 b8 02 00 00 je 401b58 + 4018a0: 0f 8e ea 00 00 00 jle 401990 + 4018a6: 83 f8 02 cmp $0x2,%eax + 4018a9: 0f 84 41 02 00 00 je 401af0 + 4018af: 83 f8 03 cmp $0x3,%eax + 4018b2: 75 24 jne 4018d8 + 4018b4: 48 8b 7d 08 mov 0x8(%rbp),%rdi + 4018b8: 4c 89 e6 mov %r12,%rsi + 4018bb: e8 50 ff ff ff callq 401810 + 4018c0: 48 83 f8 01 cmp $0x1,%rax + 4018c4: 19 c0 sbb %eax,%eax + 4018c6: f7 d0 not %eax + 4018c8: 83 c0 02 add $0x2,%eax + 4018cb: 48 98 cltq + 4018cd: 48 8b 6c c5 08 mov 0x8(%rbp,%rax,8),%rbp + 4018d2: eb c0 jmp 401894 + 4018d4: 0f 1f 40 00 nopl 0x0(%rax) + 4018d8: 8b 43 04 mov 0x4(%rbx),%eax + 4018db: 83 f8 0f cmp $0xf,%eax + 4018de: 0f 84 a8 02 00 00 je 401b8c + 4018e4: 45 31 ed xor %r13d,%r13d + 4018e7: 83 f8 0e cmp $0xe,%eax + 4018ea: 0f 85 08 01 00 00 jne 4019f8 + 4018f0: 31 c9 xor %ecx,%ecx + 4018f2: 48 83 c4 08 add $0x8,%rsp + 4018f6: 48 89 c8 mov %rcx,%rax + 4018f9: 5b pop %rbx + 4018fa: 5d pop %rbp + 4018fb: 41 5c pop %r12 + 4018fd: 41 5d pop %r13 + 4018ff: 41 5e pop %r14 + 401901: 41 5f pop %r15 + 401903: c3 retq + 401904: 0f 1f 40 00 nopl 0x0(%rax) + 401908: 85 c0 test %eax,%eax + 40190a: 75 e4 jne 4018f0 + 40190c: 8b 43 04 mov 0x4(%rbx),%eax + 40190f: 4c 89 e1 mov %r12,%rcx + 401912: 85 c0 test %eax,%eax + 401914: 74 dc je 4018f2 + 401916: 83 f8 01 cmp $0x1,%eax + 401919: 75 d5 jne 4018f0 + 40191b: 48 8b 4b 08 mov 0x8(%rbx),%rcx + 40191f: eb d1 jmp 4018f2 + 401921: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 401928: 48 8b 5b 08 mov 0x8(%rbx),%rbx + 40192c: 8b 03 mov (%rbx),%eax + 40192e: 83 f8 01 cmp $0x1,%eax + 401931: 0f 84 01 02 00 00 je 401b38 + 401937: 7e 7f jle 4019b8 + 401939: 83 f8 02 cmp $0x2,%eax + 40193c: 0f 84 ee 00 00 00 je 401a30 + 401942: 83 f8 03 cmp $0x3,%eax + 401945: 0f 85 d5 00 00 00 jne 401a20 + 40194b: 48 8b 7b 08 mov 0x8(%rbx),%rdi + 40194f: 4c 89 e6 mov %r12,%rsi + 401952: e8 b9 fe ff ff callq 401810 + 401957: 48 83 f8 01 cmp $0x1,%rax + 40195b: 19 c0 sbb %eax,%eax + 40195d: f7 d0 not %eax + 40195f: 83 c0 02 add $0x2,%eax + 401962: 48 98 cltq + 401964: 48 8b 5c c3 08 mov 0x8(%rbx,%rax,8),%rbx + 401969: eb c1 jmp 40192c + 40196b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 401970: 85 ed test %ebp,%ebp + 401972: 75 6c jne 4019e0 + 401974: 41 8b 45 04 mov 0x4(%r13),%eax + 401978: 85 c0 test %eax,%eax + 40197a: 0f 84 30 02 00 00 je 401bb0 + 401980: 83 f8 01 cmp $0x1,%eax + 401983: 75 5b jne 4019e0 + 401985: 49 8b 4d 08 mov 0x8(%r13),%rcx + 401989: e9 06 01 00 00 jmpq 401a94 + 40198e: 66 90 xchg %ax,%ax + 401990: 85 c0 test %eax,%eax + 401992: 0f 85 40 ff ff ff jne 4018d8 + 401998: 8b 45 04 mov 0x4(%rbp),%eax + 40199b: 85 c0 test %eax,%eax + 40199d: 0f 84 05 02 00 00 je 401ba8 + 4019a3: 83 f8 01 cmp $0x1,%eax + 4019a6: 0f 85 2c ff ff ff jne 4018d8 + 4019ac: 4c 8b 6d 08 mov 0x8(%rbp),%r13 + 4019b0: e9 b9 01 00 00 jmpq 401b6e + 4019b5: 0f 1f 00 nopl (%rax) + 4019b8: 85 c0 test %eax,%eax + 4019ba: 75 64 jne 401a20 + 4019bc: 8b 43 04 mov 0x4(%rbx),%eax + 4019bf: 85 c0 test %eax,%eax + 4019c1: 0f 84 d1 01 00 00 je 401b98 + 4019c7: 83 f8 01 cmp $0x1,%eax + 4019ca: 75 54 jne 401a20 + 4019cc: 31 c9 xor %ecx,%ecx + 4019ce: 48 83 7b 08 00 cmpq $0x0,0x8(%rbx) + 4019d3: 0f 94 c1 sete %cl + 4019d6: e9 17 ff ff ff jmpq 4018f2 + 4019db: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4019e0: bd 02 00 00 00 mov $0x2,%ebp + 4019e5: 48 63 ed movslq %ebp,%rbp + 4019e8: 48 8b 5c eb 08 mov 0x8(%rbx,%rbp,8),%rbx + 4019ed: e9 32 fe ff ff jmpq 401824 + 4019f2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4019f8: 48 8b 7b 10 mov 0x10(%rbx),%rdi + 4019fc: 4c 89 e6 mov %r12,%rsi + 4019ff: e8 0c fe ff ff callq 401810 + 401a04: 8b 4b 04 mov 0x4(%rbx),%ecx + 401a07: 48 89 c5 mov %rax,%rbp + 401a0a: 83 e9 03 sub $0x3,%ecx + 401a0d: 83 f9 0a cmp $0xa,%ecx + 401a10: 0f 87 da fe ff ff ja 4018f0 + 401a16: ff 24 cd 18 10 4a 00 jmpq *0x4a1018(,%rcx,8) + 401a1d: 0f 1f 00 nopl (%rax) + 401a20: b9 01 00 00 00 mov $0x1,%ecx + 401a25: e9 c8 fe ff ff jmpq 4018f2 + 401a2a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 401a30: 48 8b 7b 08 mov 0x8(%rbx),%rdi + 401a34: 4c 89 e6 mov %r12,%rsi + 401a37: e8 d4 fd ff ff callq 401810 + 401a3c: 8b 4b 04 mov 0x4(%rbx),%ecx + 401a3f: 48 89 c5 mov %rax,%rbp + 401a42: 83 f9 0f cmp $0xf,%ecx + 401a45: 0f 84 85 01 00 00 je 401bd0 + 401a4b: 83 f9 0e cmp $0xe,%ecx + 401a4e: 0f 85 1c 04 00 00 jne 401e70 + 401a54: 48 85 c0 test %rax,%rax + 401a57: b9 01 00 00 00 mov $0x1,%ecx + 401a5c: 0f 84 90 fe ff ff je 4018f2 + 401a62: 48 8b 7b 10 mov 0x10(%rbx),%rdi + 401a66: 4c 89 e6 mov %r12,%rsi + 401a69: e8 a2 fd ff ff callq 401810 + 401a6e: 31 c9 xor %ecx,%ecx + 401a70: 48 85 c0 test %rax,%rax + 401a73: 0f 94 c1 sete %cl + 401a76: e9 77 fe ff ff jmpq 4018f2 + 401a7b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 401a80: 49 8b 7d 08 mov 0x8(%r13),%rdi + 401a84: 4c 89 e6 mov %r12,%rsi + 401a87: e8 84 fd ff ff callq 401810 + 401a8c: 31 c9 xor %ecx,%ecx + 401a8e: 48 85 c0 test %rax,%rax + 401a91: 0f 94 c1 sete %cl + 401a94: 48 83 f9 01 cmp $0x1,%rcx + 401a98: 19 ed sbb %ebp,%ebp + 401a9a: f7 d5 not %ebp + 401a9c: 83 c5 02 add $0x2,%ebp + 401a9f: e9 41 ff ff ff jmpq 4019e5 + 401aa4: 0f 1f 40 00 nopl 0x0(%rax) + 401aa8: 49 8b 7d 08 mov 0x8(%r13),%rdi + 401aac: 4c 89 e6 mov %r12,%rsi + 401aaf: e8 5c fd ff ff callq 401810 + 401ab4: 49 89 c6 mov %rax,%r14 + 401ab7: 41 8b 45 04 mov 0x4(%r13),%eax + 401abb: 83 f8 0f cmp $0xf,%eax + 401abe: 0f 84 1c 01 00 00 je 401be0 + 401ac4: 83 f8 0e cmp $0xe,%eax + 401ac7: 0f 85 eb 01 00 00 jne 401cb8 + 401acd: 4d 85 f6 test %r14,%r14 + 401ad0: 0f 84 0f ff ff ff je 4019e5 + 401ad6: 49 8b 7d 10 mov 0x10(%r13),%rdi + 401ada: 4c 89 e6 mov %r12,%rsi + 401add: e8 2e fd ff ff callq 401810 + 401ae2: 31 c9 xor %ecx,%ecx + 401ae4: 48 85 c0 test %rax,%rax + 401ae7: 0f 95 c1 setne %cl + 401aea: eb a8 jmp 401a94 + 401aec: 0f 1f 40 00 nopl 0x0(%rax) + 401af0: 48 8b 7d 08 mov 0x8(%rbp),%rdi + 401af4: 4c 89 e6 mov %r12,%rsi + 401af7: e8 14 fd ff ff callq 401810 + 401afc: 8b 4d 04 mov 0x4(%rbp),%ecx + 401aff: 49 89 c6 mov %rax,%r14 + 401b02: 83 f9 0f cmp $0xf,%ecx + 401b05: 0f 84 b5 00 00 00 je 401bc0 + 401b0b: 83 f9 0e cmp $0xe,%ecx + 401b0e: 0f 85 7c 02 00 00 jne 401d90 + 401b14: 45 31 ed xor %r13d,%r13d + 401b17: 48 85 c0 test %rax,%rax + 401b1a: 74 52 je 401b6e + 401b1c: 48 8b 7d 10 mov 0x10(%rbp),%rdi + 401b20: 4c 89 e6 mov %r12,%rsi + 401b23: 45 31 ed xor %r13d,%r13d + 401b26: e8 e5 fc ff ff callq 401810 + 401b2b: 48 85 c0 test %rax,%rax + 401b2e: 41 0f 95 c5 setne %r13b + 401b32: eb 3a jmp 401b6e + 401b34: 0f 1f 40 00 nopl 0x0(%rax) + 401b38: 48 8b 7b 08 mov 0x8(%rbx),%rdi + 401b3c: 4c 89 e6 mov %r12,%rsi + 401b3f: e8 cc fc ff ff callq 401810 + 401b44: 31 c9 xor %ecx,%ecx + 401b46: 48 85 c0 test %rax,%rax + 401b49: 0f 95 c1 setne %cl + 401b4c: e9 a1 fd ff ff jmpq 4018f2 + 401b51: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 401b58: 48 8b 7d 08 mov 0x8(%rbp),%rdi + 401b5c: 4c 89 e6 mov %r12,%rsi + 401b5f: 45 31 ed xor %r13d,%r13d + 401b62: e8 a9 fc ff ff callq 401810 + 401b67: 48 85 c0 test %rax,%rax + 401b6a: 41 0f 94 c5 sete %r13b + 401b6e: 8b 4b 04 mov 0x4(%rbx),%ecx + 401b71: 83 f9 0f cmp $0xf,%ecx + 401b74: 0f 84 26 01 00 00 je 401ca0 + 401b7a: 83 f9 0e cmp $0xe,%ecx + 401b7d: 0f 85 75 fe ff ff jne 4019f8 + 401b83: 4d 85 ed test %r13,%r13 + 401b86: 0f 84 64 fd ff ff je 4018f0 + 401b8c: 48 8b 7b 10 mov 0x10(%rbx),%rdi + 401b90: eb aa jmp 401b3c + 401b92: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 401b98: 31 c9 xor %ecx,%ecx + 401b9a: 4d 85 e4 test %r12,%r12 + 401b9d: 0f 94 c1 sete %cl + 401ba0: e9 4d fd ff ff jmpq 4018f2 + 401ba5: 0f 1f 00 nopl (%rax) + 401ba8: 4d 89 e5 mov %r12,%r13 + 401bab: eb c1 jmp 401b6e + 401bad: 0f 1f 00 nopl (%rax) + 401bb0: 4c 89 e1 mov %r12,%rcx + 401bb3: e9 dc fe ff ff jmpq 401a94 + 401bb8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 401bbf: 00 + 401bc0: 48 85 c0 test %rax,%rax + 401bc3: 41 bd 01 00 00 00 mov $0x1,%r13d + 401bc9: 75 a3 jne 401b6e + 401bcb: e9 4c ff ff ff jmpq 401b1c + 401bd0: 31 c9 xor %ecx,%ecx + 401bd2: 48 85 c0 test %rax,%rax + 401bd5: 0f 85 17 fd ff ff jne 4018f2 + 401bdb: e9 82 fe ff ff jmpq 401a62 + 401be0: 4d 85 f6 test %r14,%r14 + 401be3: bd 01 00 00 00 mov $0x1,%ebp + 401be8: 0f 85 f7 fd ff ff jne 4019e5 + 401bee: e9 e3 fe ff ff jmpq 401ad6 + 401bf3: 31 c9 xor %ecx,%ecx + 401bf5: 4c 39 e8 cmp %r13,%rax + 401bf8: 0f 95 c1 setne %cl + 401bfb: e9 f2 fc ff ff jmpq 4018f2 + 401c00: 31 c9 xor %ecx,%ecx + 401c02: 4c 39 e8 cmp %r13,%rax + 401c05: 0f 94 c1 sete %cl + 401c08: e9 e5 fc ff ff jmpq 4018f2 + 401c0d: 31 c9 xor %ecx,%ecx + 401c0f: 4c 39 e8 cmp %r13,%rax + 401c12: 0f 96 c1 setbe %cl + 401c15: e9 d8 fc ff ff jmpq 4018f2 + 401c1a: 31 c9 xor %ecx,%ecx + 401c1c: 4c 39 e8 cmp %r13,%rax + 401c1f: 0f 93 c1 setae %cl + 401c22: e9 cb fc ff ff jmpq 4018f2 + 401c27: 31 c9 xor %ecx,%ecx + 401c29: 4c 39 e8 cmp %r13,%rax + 401c2c: 0f 92 c1 setb %cl + 401c2f: e9 be fc ff ff jmpq 4018f2 + 401c34: 31 c9 xor %ecx,%ecx + 401c36: 4c 39 e8 cmp %r13,%rax + 401c39: 0f 97 c1 seta %cl + 401c3c: e9 b1 fc ff ff jmpq 4018f2 + 401c41: 4c 89 e9 mov %r13,%rcx + 401c44: 48 29 c1 sub %rax,%rcx + 401c47: e9 a6 fc ff ff jmpq 4018f2 + 401c4c: 4a 8d 0c 28 lea (%rax,%r13,1),%rcx + 401c50: e9 9d fc ff ff jmpq 4018f2 + 401c55: 48 85 c0 test %rax,%rax + 401c58: 75 0a jne 401c64 + 401c5a: bf 08 00 00 00 mov $0x8,%edi + 401c5f: e8 1c bf 00 00 callq 40db80 + 401c64: 4c 89 e8 mov %r13,%rax + 401c67: 31 d2 xor %edx,%edx + 401c69: 48 f7 f5 div %rbp + 401c6c: 48 89 d1 mov %rdx,%rcx + 401c6f: e9 7e fc ff ff jmpq 4018f2 + 401c74: 48 85 c0 test %rax,%rax + 401c77: 75 0a jne 401c83 + 401c79: bf 08 00 00 00 mov $0x8,%edi + 401c7e: e8 fd be 00 00 callq 40db80 + 401c83: 4c 89 e8 mov %r13,%rax + 401c86: 31 d2 xor %edx,%edx + 401c88: 48 f7 f5 div %rbp + 401c8b: 48 89 c1 mov %rax,%rcx + 401c8e: e9 5f fc ff ff jmpq 4018f2 + 401c93: 48 89 c1 mov %rax,%rcx + 401c96: 49 0f af cd imul %r13,%rcx + 401c9a: e9 53 fc ff ff jmpq 4018f2 + 401c9f: 90 nop + 401ca0: 4d 85 ed test %r13,%r13 + 401ca3: b9 01 00 00 00 mov $0x1,%ecx + 401ca8: 0f 85 44 fc ff ff jne 4018f2 + 401cae: e9 d9 fe ff ff jmpq 401b8c + 401cb3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 401cb8: 49 8b 7d 10 mov 0x10(%r13),%rdi + 401cbc: 4c 89 e6 mov %r12,%rsi + 401cbf: e8 4c fb ff ff callq 401810 + 401cc4: 48 89 c5 mov %rax,%rbp + 401cc7: 41 8b 45 04 mov 0x4(%r13),%eax + 401ccb: 83 e8 03 sub $0x3,%eax + 401cce: 83 f8 0a cmp $0xa,%eax + 401cd1: 0f 87 09 fd ff ff ja 4019e0 + 401cd7: ff 24 c5 70 10 4a 00 jmpq *0x4a1070(,%rax,8) + 401cde: 31 c9 xor %ecx,%ecx + 401ce0: 49 39 ee cmp %rbp,%r14 + 401ce3: 0f 94 c1 sete %cl + 401ce6: e9 a9 fd ff ff jmpq 401a94 + 401ceb: 31 c9 xor %ecx,%ecx + 401ced: 49 39 ee cmp %rbp,%r14 + 401cf0: 0f 93 c1 setae %cl + 401cf3: e9 9c fd ff ff jmpq 401a94 + 401cf8: 31 c9 xor %ecx,%ecx + 401cfa: 49 39 ee cmp %rbp,%r14 + 401cfd: 0f 96 c1 setbe %cl + 401d00: e9 8f fd ff ff jmpq 401a94 + 401d05: 31 c9 xor %ecx,%ecx + 401d07: 49 39 ee cmp %rbp,%r14 + 401d0a: 0f 97 c1 seta %cl + 401d0d: e9 82 fd ff ff jmpq 401a94 + 401d12: 31 c9 xor %ecx,%ecx + 401d14: 49 39 ee cmp %rbp,%r14 + 401d17: 0f 92 c1 setb %cl + 401d1a: e9 75 fd ff ff jmpq 401a94 + 401d1f: 4c 89 f1 mov %r14,%rcx + 401d22: 48 29 e9 sub %rbp,%rcx + 401d25: e9 6a fd ff ff jmpq 401a94 + 401d2a: 49 8d 0c 2e lea (%r14,%rbp,1),%rcx + 401d2e: e9 61 fd ff ff jmpq 401a94 + 401d33: 48 85 ed test %rbp,%rbp + 401d36: 75 0a jne 401d42 + 401d38: bf 08 00 00 00 mov $0x8,%edi + 401d3d: e8 3e be 00 00 callq 40db80 + 401d42: 4c 89 f0 mov %r14,%rax + 401d45: 31 d2 xor %edx,%edx + 401d47: 48 f7 f5 div %rbp + 401d4a: 48 89 d1 mov %rdx,%rcx + 401d4d: e9 42 fd ff ff jmpq 401a94 + 401d52: 48 85 ed test %rbp,%rbp + 401d55: 75 0a jne 401d61 + 401d57: bf 08 00 00 00 mov $0x8,%edi + 401d5c: e8 1f be 00 00 callq 40db80 + 401d61: 4c 89 f0 mov %r14,%rax + 401d64: 31 d2 xor %edx,%edx + 401d66: 48 f7 f5 div %rbp + 401d69: 48 89 c1 mov %rax,%rcx + 401d6c: e9 23 fd ff ff jmpq 401a94 + 401d71: 4c 89 f1 mov %r14,%rcx + 401d74: 48 0f af cd imul %rbp,%rcx + 401d78: e9 17 fd ff ff jmpq 401a94 + 401d7d: 31 c9 xor %ecx,%ecx + 401d7f: 49 39 ee cmp %rbp,%r14 + 401d82: 0f 95 c1 setne %cl + 401d85: e9 0a fd ff ff jmpq 401a94 + 401d8a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 401d90: 48 8b 7d 10 mov 0x10(%rbp),%rdi + 401d94: 4c 89 e6 mov %r12,%rsi + 401d97: e8 74 fa ff ff callq 401810 + 401d9c: 8b 4d 04 mov 0x4(%rbp),%ecx + 401d9f: 49 89 c7 mov %rax,%r15 + 401da2: 83 e9 03 sub $0x3,%ecx + 401da5: 83 f9 0a cmp $0xa,%ecx + 401da8: 0f 87 2a fb ff ff ja 4018d8 + 401dae: ff 24 cd c8 10 4a 00 jmpq *0x4a10c8(,%rcx,8) + 401db5: 45 31 ed xor %r13d,%r13d + 401db8: 49 39 c6 cmp %rax,%r14 + 401dbb: 41 0f 94 c5 sete %r13b + 401dbf: e9 aa fd ff ff jmpq 401b6e + 401dc4: 45 31 ed xor %r13d,%r13d + 401dc7: 49 39 c6 cmp %rax,%r14 + 401dca: 41 0f 93 c5 setae %r13b + 401dce: e9 9b fd ff ff jmpq 401b6e + 401dd3: 45 31 ed xor %r13d,%r13d + 401dd6: 49 39 c6 cmp %rax,%r14 + 401dd9: 41 0f 96 c5 setbe %r13b + 401ddd: e9 8c fd ff ff jmpq 401b6e + 401de2: 45 31 ed xor %r13d,%r13d + 401de5: 49 39 c6 cmp %rax,%r14 + 401de8: 41 0f 97 c5 seta %r13b + 401dec: e9 7d fd ff ff jmpq 401b6e + 401df1: 45 31 ed xor %r13d,%r13d + 401df4: 49 39 c6 cmp %rax,%r14 + 401df7: 41 0f 92 c5 setb %r13b + 401dfb: e9 6e fd ff ff jmpq 401b6e + 401e00: 49 29 c6 sub %rax,%r14 + 401e03: 4d 89 f5 mov %r14,%r13 + 401e06: e9 63 fd ff ff jmpq 401b6e + 401e0b: 4d 8d 2c 06 lea (%r14,%rax,1),%r13 + 401e0f: e9 5a fd ff ff jmpq 401b6e + 401e14: 48 85 c0 test %rax,%rax + 401e17: 75 0a jne 401e23 + 401e19: bf 08 00 00 00 mov $0x8,%edi + 401e1e: e8 5d bd 00 00 callq 40db80 + 401e23: 4c 89 f0 mov %r14,%rax + 401e26: 31 d2 xor %edx,%edx + 401e28: 49 f7 f7 div %r15 + 401e2b: 49 89 d5 mov %rdx,%r13 + 401e2e: e9 3b fd ff ff jmpq 401b6e + 401e33: 48 85 c0 test %rax,%rax + 401e36: 75 0a jne 401e42 + 401e38: bf 08 00 00 00 mov $0x8,%edi + 401e3d: e8 3e bd 00 00 callq 40db80 + 401e42: 4c 89 f0 mov %r14,%rax + 401e45: 31 d2 xor %edx,%edx + 401e47: 49 f7 f7 div %r15 + 401e4a: 49 89 c5 mov %rax,%r13 + 401e4d: e9 1c fd ff ff jmpq 401b6e + 401e52: 4c 0f af f0 imul %rax,%r14 + 401e56: 4d 89 f5 mov %r14,%r13 + 401e59: e9 10 fd ff ff jmpq 401b6e + 401e5e: 45 31 ed xor %r13d,%r13d + 401e61: 49 39 c6 cmp %rax,%r14 + 401e64: 41 0f 95 c5 setne %r13b + 401e68: e9 01 fd ff ff jmpq 401b6e + 401e6d: 0f 1f 00 nopl (%rax) + 401e70: 48 8b 7b 10 mov 0x10(%rbx),%rdi + 401e74: 4c 89 e6 mov %r12,%rsi + 401e77: e8 94 f9 ff ff callq 401810 + 401e7c: 8b 4b 04 mov 0x4(%rbx),%ecx + 401e7f: 49 89 c4 mov %rax,%r12 + 401e82: 83 e9 03 sub $0x3,%ecx + 401e85: 83 f9 0a cmp $0xa,%ecx + 401e88: 0f 87 92 fb ff ff ja 401a20 + 401e8e: ff 24 cd 20 11 4a 00 jmpq *0x4a1120(,%rcx,8) + 401e95: 31 c9 xor %ecx,%ecx + 401e97: 48 39 c5 cmp %rax,%rbp + 401e9a: 0f 94 c1 sete %cl + 401e9d: e9 50 fa ff ff jmpq 4018f2 + 401ea2: 31 c9 xor %ecx,%ecx + 401ea4: 48 39 c5 cmp %rax,%rbp + 401ea7: 0f 92 c1 setb %cl + 401eaa: e9 43 fa ff ff jmpq 4018f2 + 401eaf: 31 c9 xor %ecx,%ecx + 401eb1: 48 39 c5 cmp %rax,%rbp + 401eb4: 0f 97 c1 seta %cl + 401eb7: e9 36 fa ff ff jmpq 4018f2 + 401ebc: 31 c9 xor %ecx,%ecx + 401ebe: 48 39 c5 cmp %rax,%rbp + 401ec1: 0f 96 c1 setbe %cl + 401ec4: e9 29 fa ff ff jmpq 4018f2 + 401ec9: 31 c9 xor %ecx,%ecx + 401ecb: 48 39 c5 cmp %rax,%rbp + 401ece: 0f 93 c1 setae %cl + 401ed1: e9 1c fa ff ff jmpq 4018f2 + 401ed6: 31 c9 xor %ecx,%ecx + 401ed8: 48 39 c5 cmp %rax,%rbp + 401edb: 0f 95 c1 setne %cl + 401ede: e9 0f fa ff ff jmpq 4018f2 + 401ee3: 31 c9 xor %ecx,%ecx + 401ee5: 48 01 c5 add %rax,%rbp + 401ee8: 0f 94 c1 sete %cl + 401eeb: e9 02 fa ff ff jmpq 4018f2 + 401ef0: 48 85 c0 test %rax,%rax + 401ef3: 75 0a jne 401eff + 401ef5: bf 08 00 00 00 mov $0x8,%edi + 401efa: e8 81 bc 00 00 callq 40db80 + 401eff: 31 d2 xor %edx,%edx + 401f01: 48 89 e8 mov %rbp,%rax + 401f04: 31 c9 xor %ecx,%ecx + 401f06: 49 f7 f4 div %r12 + 401f09: 48 85 d2 test %rdx,%rdx + 401f0c: 0f 94 c1 sete %cl + 401f0f: e9 de f9 ff ff jmpq 4018f2 + 401f14: 48 85 c0 test %rax,%rax + 401f17: 75 0a jne 401f23 + 401f19: bf 08 00 00 00 mov $0x8,%edi + 401f1e: e8 5d bc 00 00 callq 40db80 + 401f23: 31 d2 xor %edx,%edx + 401f25: 48 89 e8 mov %rbp,%rax + 401f28: 31 c9 xor %ecx,%ecx + 401f2a: 49 f7 f4 div %r12 + 401f2d: 48 85 c0 test %rax,%rax + 401f30: 0f 94 c1 sete %cl + 401f33: e9 ba f9 ff ff jmpq 4018f2 + 401f38: 48 0f af e8 imul %rax,%rbp + 401f3c: 31 c9 xor %ecx,%ecx + 401f3e: 48 85 ed test %rbp,%rbp + 401f41: 0f 94 c1 sete %cl + 401f44: e9 a9 f9 ff ff jmpq 4018f2 + 401f49: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + +0000000000401f50 <_nl_find_msg>: + 401f50: 55 push %rbp + 401f51: 48 89 f8 mov %rdi,%rax + 401f54: 48 89 e5 mov %rsp,%rbp + 401f57: 41 57 push %r15 + 401f59: 41 56 push %r14 + 401f5b: 41 55 push %r13 + 401f5d: 41 54 push %r12 + 401f5f: 53 push %rbx + 401f60: 48 81 ec 88 00 00 00 sub $0x88,%rsp + 401f67: 4c 89 85 60 ff ff ff mov %r8,-0xa0(%rbp) + 401f6e: 44 8b 47 08 mov 0x8(%rdi),%r8d + 401f72: 48 89 bd 70 ff ff ff mov %rdi,-0x90(%rbp) + 401f79: 48 89 b5 58 ff ff ff mov %rsi,-0xa8(%rbp) + 401f80: 48 89 55 a0 mov %rdx,-0x60(%rbp) + 401f84: 89 8d 68 ff ff ff mov %ecx,-0x98(%rbp) + 401f8a: 45 85 c0 test %r8d,%r8d + 401f8d: 0f 8e dd 03 00 00 jle 402370 <_nl_find_msg+0x420> + 401f93: 48 8b 58 10 mov 0x10(%rax),%rbx + 401f97: 48 85 db test %rbx,%rbx + 401f9a: 0f 84 0c 01 00 00 je 4020ac <_nl_find_msg+0x15c> + 401fa0: 48 83 7b 60 00 cmpq $0x0,0x60(%rbx) + 401fa5: 8b 43 28 mov 0x28(%rbx),%eax + 401fa8: 89 45 a8 mov %eax,-0x58(%rbp) + 401fab: 0f 84 9f 02 00 00 je 402250 <_nl_find_msg+0x300> + 401fb1: 4c 8b 75 a0 mov -0x60(%rbp),%r14 + 401fb5: 4c 89 f7 mov %r14,%rdi + 401fb8: e8 93 16 02 00 callq 423650 + 401fbd: 4c 89 f7 mov %r14,%rdi + 401fc0: 49 89 c7 mov %rax,%r15 + 401fc3: 89 85 78 ff ff ff mov %eax,-0x88(%rbp) + 401fc9: e8 62 bb 00 00 callq 40db30 <__hash_string> + 401fce: 8b 7b 58 mov 0x58(%rbx),%edi + 401fd1: 31 d2 xor %edx,%edx + 401fd3: 89 c6 mov %eax,%esi + 401fd5: 44 8b 73 68 mov 0x68(%rbx),%r14d + 401fd9: f7 f7 div %edi + 401fdb: 44 8d 47 fe lea -0x2(%rdi),%r8d + 401fdf: 89 f0 mov %esi,%eax + 401fe1: 41 89 d5 mov %edx,%r13d + 401fe4: 31 d2 xor %edx,%edx + 401fe6: 41 f7 f0 div %r8d + 401fe9: 48 8b 43 60 mov 0x60(%rbx),%rax + 401fed: 48 89 45 98 mov %rax,-0x68(%rbp) + 401ff1: 44 89 f8 mov %r15d,%eax + 401ff4: 41 89 ff mov %edi,%r15d + 401ff7: 48 89 45 80 mov %rax,-0x80(%rbp) + 401ffb: 44 8d 62 01 lea 0x1(%rdx),%r12d + 401fff: 44 89 e0 mov %r12d,%eax + 402002: 45 29 e7 sub %r12d,%r15d + 402005: 29 f8 sub %edi,%eax + 402007: 89 45 90 mov %eax,-0x70(%rbp) + 40200a: 44 89 f8 mov %r15d,%eax + 40200d: 45 89 e7 mov %r12d,%r15d + 402010: 49 89 dc mov %rbx,%r12 + 402013: 44 89 eb mov %r13d,%ebx + 402016: 41 89 c5 mov %eax,%r13d + 402019: eb 7d jmp 402098 <_nl_find_msg+0x148> + 40201b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 402020: 48 8b 4d 98 mov -0x68(%rbp),%rcx + 402024: 44 8b 14 81 mov (%rcx,%rax,4),%r10d + 402028: 41 0f ca bswap %r10d + 40202b: 45 85 d2 test %r10d,%r10d + 40202e: 74 7c je 4020ac <_nl_find_msg+0x15c> + 402030: 41 83 ea 01 sub $0x1,%r10d + 402034: 44 39 55 a8 cmp %r10d,-0x58(%rbp) + 402038: 0f 86 82 00 00 00 jbe 4020c0 <_nl_find_msg+0x170> + 40203e: 41 8b 7c 24 18 mov 0x18(%r12),%edi + 402043: 49 8b 44 24 30 mov 0x30(%r12),%rax + 402048: 85 ff test %edi,%edi + 40204a: 0f 84 e0 01 00 00 je 402230 <_nl_find_msg+0x2e0> + 402050: 4a 8d 3c d0 lea (%rax,%r10,8),%rdi + 402054: 8b 07 mov (%rdi),%eax + 402056: 0f c8 bswap %eax + 402058: 39 85 78 ff ff ff cmp %eax,-0x88(%rbp) + 40205e: 77 27 ja 402087 <_nl_find_msg+0x137> + 402060: 8b 47 04 mov 0x4(%rdi),%eax + 402063: 49 8b 34 24 mov (%r12),%rsi + 402067: 0f c8 bswap %eax + 402069: 89 c0 mov %eax,%eax + 40206b: 48 8b 7d a0 mov -0x60(%rbp),%rdi + 40206f: 48 01 c6 add %rax,%rsi + 402072: 4c 89 55 88 mov %r10,-0x78(%rbp) + 402076: e8 e5 e2 ff ff callq 400360 <__rela_iplt_end+0x98> + 40207b: 85 c0 test %eax,%eax + 40207d: 4c 8b 55 88 mov -0x78(%rbp),%r10 + 402081: 0f 84 8a 0a 00 00 je 402b11 <_nl_find_msg+0xbc1> + 402087: 8b 45 90 mov -0x70(%rbp),%eax + 40208a: 42 8d 34 3b lea (%rbx,%r15,1),%esi + 40208e: 01 d8 add %ebx,%eax + 402090: 44 39 eb cmp %r13d,%ebx + 402093: 0f 42 c6 cmovb %esi,%eax + 402096: 89 c3 mov %eax,%ebx + 402098: 45 85 f6 test %r14d,%r14d + 40209b: 89 d8 mov %ebx,%eax + 40209d: 75 81 jne 402020 <_nl_find_msg+0xd0> + 40209f: 48 8b 55 98 mov -0x68(%rbp),%rdx + 4020a3: 44 8b 14 82 mov (%rdx,%rax,4),%r10d + 4020a7: 45 85 d2 test %r10d,%r10d + 4020aa: 75 84 jne 402030 <_nl_find_msg+0xe0> + 4020ac: 31 c0 xor %eax,%eax + 4020ae: 48 8d 65 d8 lea -0x28(%rbp),%rsp + 4020b2: 5b pop %rbx + 4020b3: 41 5c pop %r12 + 4020b5: 41 5d pop %r13 + 4020b7: 41 5e pop %r14 + 4020b9: 41 5f pop %r15 + 4020bb: 5d pop %rbp + 4020bc: c3 retq + 4020bd: 0f 1f 00 nopl (%rax) + 4020c0: 44 89 d0 mov %r10d,%eax + 4020c3: 2b 45 a8 sub -0x58(%rbp),%eax + 4020c6: 48 8b 55 80 mov -0x80(%rbp),%rdx + 4020ca: 44 89 55 88 mov %r10d,-0x78(%rbp) + 4020ce: 48 c1 e0 04 shl $0x4,%rax + 4020d2: 49 03 44 24 48 add 0x48(%r12),%rax + 4020d7: 48 3b 10 cmp (%rax),%rdx + 4020da: 73 ab jae 402087 <_nl_find_msg+0x137> + 4020dc: 48 8b 70 08 mov 0x8(%rax),%rsi + 4020e0: 48 8b 7d a0 mov -0x60(%rbp),%rdi + 4020e4: e8 77 e2 ff ff callq 400360 <__rela_iplt_end+0x98> + 4020e9: 85 c0 test %eax,%eax + 4020eb: 75 9a jne 402087 <_nl_find_msg+0x137> + 4020ed: 44 8b 55 88 mov -0x78(%rbp),%r10d + 4020f1: 4c 89 e3 mov %r12,%rbx + 4020f4: 8b 45 a8 mov -0x58(%rbp),%eax + 4020f7: 4d 89 d6 mov %r10,%r14 + 4020fa: 49 39 c6 cmp %rax,%r14 + 4020fd: 0f 83 f5 01 00 00 jae 4022f8 <_nl_find_msg+0x3a8> + 402103: 8b 4b 18 mov 0x18(%rbx),%ecx + 402106: 4c 8b 3b mov (%rbx),%r15 + 402109: 48 8b 43 38 mov 0x38(%rbx),%rax + 40210d: 85 c9 test %ecx,%ecx + 40210f: 0f 84 3b 02 00 00 je 402350 <_nl_find_msg+0x400> + 402115: 4a 8d 14 f0 lea (%rax,%r14,8),%rdx + 402119: 8b 42 04 mov 0x4(%rdx),%eax + 40211c: 0f c8 bswap %eax + 40211e: 89 c0 mov %eax,%eax + 402120: 4c 01 f8 add %r15,%rax + 402123: 48 89 45 a0 mov %rax,-0x60(%rbp) + 402127: 8b 02 mov (%rdx),%eax + 402129: 8b 95 68 ff ff ff mov -0x98(%rbp),%edx + 40212f: 0f c8 bswap %eax + 402131: 83 c0 01 add $0x1,%eax + 402134: 85 d2 test %edx,%edx + 402136: 48 89 45 98 mov %rax,-0x68(%rbp) + 40213a: 0f 84 e6 01 00 00 je 402326 <_nl_find_msg+0x3d6> + 402140: 48 8b 85 58 ff ff ff mov -0xa8(%rbp),%rax + 402147: 48 85 c0 test %rax,%rax + 40214a: 0f 84 f7 02 00 00 je 402447 <_nl_find_msg+0x4f7> + 402150: 48 8b 40 10 mov 0x10(%rax),%rax + 402154: 48 85 c0 test %rax,%rax + 402157: 48 89 45 90 mov %rax,-0x70(%rbp) + 40215b: 0f 84 e6 02 00 00 je 402447 <_nl_find_msg+0x4f7> + 402161: b8 00 00 00 00 mov $0x0,%eax + 402166: 48 85 c0 test %rax,%rax + 402169: 74 09 je 402174 <_nl_find_msg+0x224> + 40216b: 48 8d bb 80 00 00 00 lea 0x80(%rbx),%rdi + 402172: ff d0 callq *%rax + 402174: 4c 8b 6b 78 mov 0x78(%rbx),%r13 + 402178: 4d 85 ed test %r13,%r13 + 40217b: 0f 84 17 02 00 00 je 402398 <_nl_find_msg+0x448> + 402181: 48 8b 53 70 mov 0x70(%rbx),%rdx + 402185: 4b 8d 44 6d 00 lea 0x0(%r13,%r13,2),%rax + 40218a: 48 89 5d 88 mov %rbx,-0x78(%rbp) + 40218e: 4c 8b 65 90 mov -0x70(%rbp),%r12 + 402192: 4c 89 eb mov %r13,%rbx + 402195: 4c 8d 7c c2 e8 lea -0x18(%rdx,%rax,8),%r15 + 40219a: eb 11 jmp 4021ad <_nl_find_msg+0x25d> + 40219c: 0f 1f 40 00 nopl 0x0(%rax) + 4021a0: 49 83 ef 18 sub $0x18,%r15 + 4021a4: 48 85 db test %rbx,%rbx + 4021a7: 0f 84 e7 01 00 00 je 402394 <_nl_find_msg+0x444> + 4021ad: 49 8b 3f mov (%r15),%rdi + 4021b0: 4c 89 e6 mov %r12,%rsi + 4021b3: 48 83 eb 01 sub $0x1,%rbx + 4021b7: e8 a4 e1 ff ff callq 400360 <__rela_iplt_end+0x98> + 4021bc: 85 c0 test %eax,%eax + 4021be: 75 e0 jne 4021a0 <_nl_find_msg+0x250> + 4021c0: b8 00 00 00 00 mov $0x0,%eax + 4021c5: 48 8b 5d 88 mov -0x78(%rbp),%rbx + 4021c9: 4d 89 fc mov %r15,%r12 + 4021cc: 48 85 c0 test %rax,%rax + 4021cf: 48 89 45 88 mov %rax,-0x78(%rbp) + 4021d3: 74 15 je 4021ea <_nl_find_msg+0x29a> + 4021d5: 48 8d bb 80 00 00 00 lea 0x80(%rbx),%rdi + 4021dc: e8 1f de bf ff callq 0 <_nl_current_LC_CTYPE> + 4021e1: 4d 85 e4 test %r12,%r12 + 4021e4: 0f 84 c3 01 00 00 je 4023ad <_nl_find_msg+0x45d> + 4021ea: 49 83 7c 24 08 ff cmpq $0xffffffffffffffff,0x8(%r12) + 4021f0: 0f 84 30 01 00 00 je 402326 <_nl_find_msg+0x3d6> + 4021f6: 49 8b 44 24 10 mov 0x10(%r12),%rax + 4021fb: 48 85 c0 test %rax,%rax + 4021fe: 0f 84 ed 02 00 00 je 4024f1 <_nl_find_msg+0x5a1> + 402204: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 402208: 0f 84 d7 02 00 00 je 4024e5 <_nl_find_msg+0x595> + 40220e: 4a 8b 04 f0 mov (%rax,%r14,8),%rax + 402212: 48 85 c0 test %rax,%rax + 402215: 0f 84 5f 03 00 00 je 40257a <_nl_find_msg+0x62a> + 40221b: 48 8d 78 08 lea 0x8(%rax),%rdi + 40221f: 48 8b 00 mov (%rax),%rax + 402222: 48 89 7d a0 mov %rdi,-0x60(%rbp) + 402226: 48 89 45 98 mov %rax,-0x68(%rbp) + 40222a: e9 f7 00 00 00 jmpq 402326 <_nl_find_msg+0x3d6> + 40222f: 90 nop + 402230: 4a 8d 04 d0 lea (%rax,%r10,8),%rax + 402234: 8b 95 78 ff ff ff mov -0x88(%rbp),%edx + 40223a: 3b 10 cmp (%rax),%edx + 40223c: 0f 87 45 fe ff ff ja 402087 <_nl_find_msg+0x137> + 402242: 49 8b 34 24 mov (%r12),%rsi + 402246: 8b 40 04 mov 0x4(%rax),%eax + 402249: e9 1d fe ff ff jmpq 40206b <_nl_find_msg+0x11b> + 40224e: 66 90 xchg %ax,%ax + 402250: 8b 45 a8 mov -0x58(%rbp),%eax + 402253: 45 31 ff xor %r15d,%r15d + 402256: 49 89 c5 mov %rax,%r13 + 402259: 48 89 45 90 mov %rax,-0x70(%rbp) + 40225d: 48 89 d8 mov %rbx,%rax + 402260: 4c 89 eb mov %r13,%rbx + 402263: 49 89 c5 mov %rax,%r13 + 402266: eb 31 jmp 402299 <_nl_find_msg+0x349> + 402268: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 40226f: 00 + 402270: 4e 8d 34 3b lea (%rbx,%r15,1),%r14 + 402274: 48 8b 7d a0 mov -0x60(%rbp),%rdi + 402278: 49 d1 ee shr %r14 + 40227b: 43 8b 74 f4 04 mov 0x4(%r12,%r14,8),%esi + 402280: 48 03 75 98 add -0x68(%rbp),%rsi + 402284: e8 d7 e0 ff ff callq 400360 <__rela_iplt_end+0x98> + 402289: 85 c0 test %eax,%eax + 40228b: 78 5b js 4022e8 <_nl_find_msg+0x398> + 40228d: 85 c0 test %eax,%eax + 40228f: 0f 84 f3 00 00 00 je 402388 <_nl_find_msg+0x438> + 402295: 4d 8d 7e 01 lea 0x1(%r14),%r15 + 402299: 49 39 df cmp %rbx,%r15 + 40229c: 0f 83 0a fe ff ff jae 4020ac <_nl_find_msg+0x15c> + 4022a2: 41 8b 75 18 mov 0x18(%r13),%esi + 4022a6: 49 8b 45 00 mov 0x0(%r13),%rax + 4022aa: 4d 8b 65 30 mov 0x30(%r13),%r12 + 4022ae: 85 f6 test %esi,%esi + 4022b0: 48 89 45 98 mov %rax,-0x68(%rbp) + 4022b4: 74 ba je 402270 <_nl_find_msg+0x320> + 4022b6: 4d 8d 34 1f lea (%r15,%rbx,1),%r14 + 4022ba: 48 8b 7d a0 mov -0x60(%rbp),%rdi + 4022be: 49 d1 ee shr %r14 + 4022c1: 43 8b 74 f4 04 mov 0x4(%r12,%r14,8),%esi + 4022c6: 0f ce bswap %esi + 4022c8: 89 f6 mov %esi,%esi + 4022ca: 48 03 75 98 add -0x68(%rbp),%rsi + 4022ce: e8 8d e0 ff ff callq 400360 <__rela_iplt_end+0x98> + 4022d3: 85 c0 test %eax,%eax + 4022d5: 79 b6 jns 40228d <_nl_find_msg+0x33d> + 4022d7: 4d 39 f7 cmp %r14,%r15 + 4022da: 4c 89 f3 mov %r14,%rbx + 4022dd: 72 d7 jb 4022b6 <_nl_find_msg+0x366> + 4022df: e9 c8 fd ff ff jmpq 4020ac <_nl_find_msg+0x15c> + 4022e4: 0f 1f 40 00 nopl 0x0(%rax) + 4022e8: 4d 39 f7 cmp %r14,%r15 + 4022eb: 4c 89 f3 mov %r14,%rbx + 4022ee: 72 80 jb 402270 <_nl_find_msg+0x320> + 4022f0: e9 b7 fd ff ff jmpq 4020ac <_nl_find_msg+0x15c> + 4022f5: 0f 1f 00 nopl (%rax) + 4022f8: 4c 89 f1 mov %r14,%rcx + 4022fb: 48 29 c1 sub %rax,%rcx + 4022fe: 48 89 c8 mov %rcx,%rax + 402301: 48 c1 e0 04 shl $0x4,%rax + 402305: 48 03 43 50 add 0x50(%rbx),%rax + 402309: 48 8b 48 08 mov 0x8(%rax),%rcx + 40230d: 48 8b 00 mov (%rax),%rax + 402310: 48 89 4d a0 mov %rcx,-0x60(%rbp) + 402314: 48 89 45 98 mov %rax,-0x68(%rbp) + 402318: 8b 95 68 ff ff ff mov -0x98(%rbp),%edx + 40231e: 85 d2 test %edx,%edx + 402320: 0f 85 1a fe ff ff jne 402140 <_nl_find_msg+0x1f0> + 402326: 48 8b 85 60 ff ff ff mov -0xa0(%rbp),%rax + 40232d: 48 8b 7d 98 mov -0x68(%rbp),%rdi + 402331: 48 89 38 mov %rdi,(%rax) + 402334: 48 8b 45 a0 mov -0x60(%rbp),%rax + 402338: 48 8d 65 d8 lea -0x28(%rbp),%rsp + 40233c: 5b pop %rbx + 40233d: 41 5c pop %r12 + 40233f: 41 5d pop %r13 + 402341: 41 5e pop %r14 + 402343: 41 5f pop %r15 + 402345: 5d pop %rbp + 402346: c3 retq + 402347: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 40234e: 00 00 + 402350: 4a 8d 04 f0 lea (%rax,%r14,8),%rax + 402354: 8b 50 04 mov 0x4(%rax),%edx + 402357: 8b 00 mov (%rax),%eax + 402359: 83 c0 01 add $0x1,%eax + 40235c: 49 8d 3c 17 lea (%r15,%rdx,1),%rdi + 402360: 48 89 45 98 mov %rax,-0x68(%rbp) + 402364: 48 89 7d a0 mov %rdi,-0x60(%rbp) + 402368: eb ae jmp 402318 <_nl_find_msg+0x3c8> + 40236a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 402370: e8 cb 13 00 00 callq 403740 <_nl_load_domain> + 402375: 48 8b 85 70 ff ff ff mov -0x90(%rbp),%rax + 40237c: e9 12 fc ff ff jmpq 401f93 <_nl_find_msg+0x43> + 402381: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 402388: 4c 89 eb mov %r13,%rbx + 40238b: 48 8b 45 90 mov -0x70(%rbp),%rax + 40238f: e9 66 fd ff ff jmpq 4020fa <_nl_find_msg+0x1aa> + 402394: 48 8b 5d 88 mov -0x78(%rbp),%rbx + 402398: b8 00 00 00 00 mov $0x0,%eax + 40239d: 45 31 e4 xor %r12d,%r12d + 4023a0: 48 85 c0 test %rax,%rax + 4023a3: 48 89 45 88 mov %rax,-0x78(%rbp) + 4023a7: 0f 85 28 fe ff ff jne 4021d5 <_nl_find_msg+0x285> + 4023ad: b8 00 00 00 00 mov $0x0,%eax + 4023b2: 48 85 c0 test %rax,%rax + 4023b5: 74 09 je 4023c0 <_nl_find_msg+0x470> + 4023b7: 48 8d bb 80 00 00 00 lea 0x80(%rbx),%rdi + 4023be: ff d0 callq *%rax + 4023c0: 48 8b 43 78 mov 0x78(%rbx),%rax + 4023c4: 48 85 c0 test %rax,%rax + 4023c7: 48 89 45 80 mov %rax,-0x80(%rbp) + 4023cb: 0f 84 cd 06 00 00 je 402a9e <_nl_find_msg+0xb4e> + 4023d1: 48 89 c1 mov %rax,%rcx + 4023d4: 48 8b 43 70 mov 0x70(%rbx),%rax + 4023d8: 48 89 9d 68 ff ff ff mov %rbx,-0x98(%rbp) + 4023df: 4c 8b 7d 90 mov -0x70(%rbp),%r15 + 4023e3: 48 89 cb mov %rcx,%rbx + 4023e6: 48 89 c7 mov %rax,%rdi + 4023e9: 48 89 85 78 ff ff ff mov %rax,-0x88(%rbp) + 4023f0: 48 8d 04 49 lea (%rcx,%rcx,2),%rax + 4023f4: 48 8d 54 c7 e8 lea -0x18(%rdi,%rax,8),%rdx + 4023f9: 49 89 d5 mov %rdx,%r13 + 4023fc: eb 0f jmp 40240d <_nl_find_msg+0x4bd> + 4023fe: 66 90 xchg %ax,%ax + 402400: 49 83 ed 18 sub $0x18,%r13 + 402404: 48 85 db test %rbx,%rbx + 402407: 0f 84 f3 02 00 00 je 402700 <_nl_find_msg+0x7b0> + 40240d: 49 8b 7d 00 mov 0x0(%r13),%rdi + 402411: 4c 89 fe mov %r15,%rsi + 402414: 48 83 eb 01 sub $0x1,%rbx + 402418: 4d 89 ec mov %r13,%r12 + 40241b: e8 40 df ff ff callq 400360 <__rela_iplt_end+0x98> + 402420: 85 c0 test %eax,%eax + 402422: 75 dc jne 402400 <_nl_find_msg+0x4b0> + 402424: 48 8b 9d 68 ff ff ff mov -0x98(%rbp),%rbx + 40242b: 48 83 7d 88 00 cmpq $0x0,-0x78(%rbp) + 402430: 0f 84 b4 fd ff ff je 4021ea <_nl_find_msg+0x29a> + 402436: 48 8d bb 80 00 00 00 lea 0x80(%rbx),%rdi + 40243d: e8 be db bf ff callq 0 <_nl_current_LC_CTYPE> + 402442: e9 a3 fd ff ff jmpq 4021ea <_nl_find_msg+0x29a> + 402447: 8b 05 d3 9b 2c 00 mov 0x2c9bd3(%rip),%eax # 6cc020 + 40244d: 4c 8b 2d c4 9b 2c 00 mov 0x2c9bc4(%rip),%r13 # 6cc018 + 402454: 85 c0 test %eax,%eax + 402456: 0f 84 73 02 00 00 je 4026cf <_nl_find_msg+0x77f> + 40245c: 4d 85 ed test %r13,%r13 + 40245f: 4c 89 6d 90 mov %r13,-0x70(%rbp) + 402463: 0f 85 f8 fc ff ff jne 402161 <_nl_find_msg+0x211> + 402469: 48 c7 c0 b0 ff ff ff mov $0xffffffffffffffb0,%rax + 402470: 64 48 8b 00 mov %fs:(%rax),%rax + 402474: 48 8b 00 mov (%rax),%rax + 402477: 48 8b 80 b0 00 00 00 mov 0xb0(%rax),%rax + 40247e: 48 89 45 90 mov %rax,-0x70(%rbp) + 402482: e9 da fc ff ff jmpq 402161 <_nl_find_msg+0x211> + 402487: 48 8b 03 mov (%rbx),%rax + 40248a: 48 89 df mov %rbx,%rdi + 40248d: 48 89 05 ac 9b 2c 00 mov %rax,0x2c9bac(%rip) # 6cc040 + 402494: e8 17 b9 01 00 callq 41ddb0 <__cfree> + 402499: 48 c7 05 8c 9b 2c 00 movq $0x0,0x2c9b8c(%rip) # 6cc030 + 4024a0: 00 00 00 00 + 4024a4: 48 c7 05 79 9b 2c 00 movq $0x0,0x2c9b79(%rip) # 6cc028 + 4024ab: 00 00 00 00 + 4024af: 83 3d 06 ad 2c 00 00 cmpl $0x0,0x2cad06(%rip) # 6cd1bc <__libc_multiple_threads> + 4024b6: 74 0b je 4024c3 <_nl_find_msg+0x573> + 4024b8: f0 ff 0d 79 9b 2c 00 lock decl 0x2c9b79(%rip) # 6cc038 + 4024bf: 75 0a jne 4024cb <_nl_find_msg+0x57b> + 4024c1: eb 22 jmp 4024e5 <_nl_find_msg+0x595> + 4024c3: ff 0d 6f 9b 2c 00 decl 0x2c9b6f(%rip) # 6cc038 + 4024c9: 74 1a je 4024e5 <_nl_find_msg+0x595> + 4024cb: 48 8d 3d 66 9b 2c 00 lea 0x2c9b66(%rip),%rdi # 6cc038 + 4024d2: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 4024d9: e8 22 01 04 00 callq 442600 <__lll_unlock_wake_private> + 4024de: 48 81 c4 80 00 00 00 add $0x80,%rsp + 4024e5: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax + 4024ec: e9 bd fb ff ff jmpq 4020ae <_nl_find_msg+0x15e> + 4024f1: be 01 00 00 00 mov $0x1,%esi + 4024f6: 83 3d bf ac 2c 00 00 cmpl $0x0,0x2cacbf(%rip) # 6cd1bc <__libc_multiple_threads> + 4024fd: 74 0c je 40250b <_nl_find_msg+0x5bb> + 4024ff: f0 0f b1 35 31 9b 2c lock cmpxchg %esi,0x2c9b31(%rip) # 6cc038 + 402506: 00 + 402507: 75 0b jne 402514 <_nl_find_msg+0x5c4> + 402509: eb 23 jmp 40252e <_nl_find_msg+0x5de> + 40250b: 0f b1 35 26 9b 2c 00 cmpxchg %esi,0x2c9b26(%rip) # 6cc038 + 402512: 74 1a je 40252e <_nl_find_msg+0x5de> + 402514: 48 8d 3d 1d 9b 2c 00 lea 0x2c9b1d(%rip),%rdi # 6cc038 + 40251b: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 402522: e8 a9 00 04 00 callq 4425d0 <__lll_lock_wait_private> + 402527: 48 81 c4 80 00 00 00 add $0x80,%rsp + 40252e: 49 83 7c 24 10 00 cmpq $0x0,0x10(%r12) + 402534: 0f 84 88 05 00 00 je 402ac2 <_nl_find_msg+0xb72> + 40253a: 83 3d 7b ac 2c 00 00 cmpl $0x0,0x2cac7b(%rip) # 6cd1bc <__libc_multiple_threads> + 402541: 74 0b je 40254e <_nl_find_msg+0x5fe> + 402543: f0 ff 0d ee 9a 2c 00 lock decl 0x2c9aee(%rip) # 6cc038 + 40254a: 75 0a jne 402556 <_nl_find_msg+0x606> + 40254c: eb 22 jmp 402570 <_nl_find_msg+0x620> + 40254e: ff 0d e4 9a 2c 00 decl 0x2c9ae4(%rip) # 6cc038 + 402554: 74 1a je 402570 <_nl_find_msg+0x620> + 402556: 48 8d 3d db 9a 2c 00 lea 0x2c9adb(%rip),%rdi # 6cc038 + 40255d: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 402564: e8 97 00 04 00 callq 442600 <__lll_unlock_wake_private> + 402569: 48 81 c4 80 00 00 00 add $0x80,%rsp + 402570: 49 8b 44 24 10 mov 0x10(%r12),%rax + 402575: e9 8a fc ff ff jmpq 402204 <_nl_find_msg+0x2b4> + 40257a: be 01 00 00 00 mov $0x1,%esi + 40257f: 83 3d 36 ac 2c 00 00 cmpl $0x0,0x2cac36(%rip) # 6cd1bc <__libc_multiple_threads> + 402586: 74 0c je 402594 <_nl_find_msg+0x644> + 402588: f0 0f b1 35 a8 9a 2c lock cmpxchg %esi,0x2c9aa8(%rip) # 6cc038 + 40258f: 00 + 402590: 75 0b jne 40259d <_nl_find_msg+0x64d> + 402592: eb 23 jmp 4025b7 <_nl_find_msg+0x667> + 402594: 0f b1 35 9d 9a 2c 00 cmpxchg %esi,0x2c9a9d(%rip) # 6cc038 + 40259b: 74 1a je 4025b7 <_nl_find_msg+0x667> + 40259d: 48 8d 3d 94 9a 2c 00 lea 0x2c9a94(%rip),%rdi # 6cc038 + 4025a4: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 4025ab: e8 20 00 04 00 callq 4425d0 <__lll_lock_wait_private> + 4025b0: 48 81 c4 80 00 00 00 add $0x80,%rsp + 4025b7: 48 8b 45 a0 mov -0x60(%rbp),%rax + 4025bb: 45 31 ed xor %r13d,%r13d + 4025be: 4c 89 75 a8 mov %r14,-0x58(%rbp) + 4025c2: 48 8b 0d 5f 9a 2c 00 mov 0x2c9a5f(%rip),%rcx # 6cc028 + 4025c9: 4c 8b 7d 98 mov -0x68(%rbp),%r15 + 4025cd: 45 89 ee mov %r13d,%r14d + 4025d0: 48 89 45 b8 mov %rax,-0x48(%rbp) + 4025d4: 48 8b 05 55 9a 2c 00 mov 0x2c9a55(%rip),%rax # 6cc030 + 4025db: 48 83 c0 08 add $0x8,%rax + 4025df: 48 89 45 c0 mov %rax,-0x40(%rbp) + 4025e3: eb 61 jmp 402646 <_nl_find_msg+0x6f6> + 4025e5: 0f 1f 00 nopl (%rax) + 4025e8: 45 85 f6 test %r14d,%r14d + 4025eb: 0f 84 9f 00 00 00 je 402690 <_nl_find_msg+0x740> + 4025f1: 41 83 c6 01 add $0x1,%r14d + 4025f5: 48 8b 1d 44 9a 2c 00 mov 0x2c9a44(%rip),%rbx # 6cc040 + 4025fc: 41 69 ce f0 0f 00 00 imul $0xff0,%r14d,%ecx + 402603: 48 89 df mov %rbx,%rdi + 402606: 4c 63 e9 movslq %ecx,%r13 + 402609: 4c 89 ee mov %r13,%rsi + 40260c: 4c 89 2d 15 9a 2c 00 mov %r13,0x2c9a15(%rip) # 6cc028 + 402613: e8 58 b9 01 00 callq 41df70 <__libc_realloc> + 402618: 48 85 c0 test %rax,%rax + 40261b: 0f 84 66 fe ff ff je 402487 <_nl_find_msg+0x537> + 402621: 49 8d 4d f8 lea -0x8(%r13),%rcx + 402625: 48 89 05 14 9a 2c 00 mov %rax,0x2c9a14(%rip) # 6cc040 + 40262c: 48 8d 50 08 lea 0x8(%rax),%rdx + 402630: 48 83 c0 10 add $0x10,%rax + 402634: 48 89 0d ed 99 2c 00 mov %rcx,0x2c99ed(%rip) # 6cc028 + 40263b: 48 89 45 c0 mov %rax,-0x40(%rbp) + 40263f: 48 89 15 ea 99 2c 00 mov %rdx,0x2c99ea(%rip) # 6cc030 + 402646: 48 83 f9 07 cmp $0x7,%rcx + 40264a: 76 9c jbe 4025e8 <_nl_find_msg+0x698> + 40264c: 4c 89 fa mov %r15,%rdx + 40264f: 48 03 55 b8 add -0x48(%rbp),%rdx + 402653: 49 8b 7c 24 08 mov 0x8(%r12),%rdi + 402658: 4c 8d 44 08 f8 lea -0x8(%rax,%rcx,1),%r8 + 40265d: 4c 8d 4d c8 lea -0x38(%rbp),%r9 + 402661: 48 8d 4d c0 lea -0x40(%rbp),%rcx + 402665: 48 8d 75 b8 lea -0x48(%rbp),%rsi + 402669: e8 02 20 04 00 callq 444670 <__gconv> + 40266e: a9 fb ff ff ff test $0xfffffffb,%eax + 402673: 0f 84 46 03 00 00 je 4029bf <_nl_find_msg+0xa6f> + 402679: 83 f8 05 cmp $0x5,%eax + 40267c: 0f 85 02 03 00 00 jne 402984 <_nl_find_msg+0xa34> + 402682: 48 8b 45 a0 mov -0x60(%rbp),%rax + 402686: 48 89 45 b8 mov %rax,-0x48(%rbp) + 40268a: e9 59 ff ff ff jmpq 4025e8 <_nl_find_msg+0x698> + 40268f: 90 nop + 402690: bf f0 0f 00 00 mov $0xff0,%edi + 402695: 48 c7 05 88 99 2c 00 movq $0xff0,0x2c9988(%rip) # 6cc028 + 40269c: f0 0f 00 00 + 4026a0: e8 6b b3 01 00 callq 41da10 <__libc_malloc> + 4026a5: 48 85 c0 test %rax,%rax + 4026a8: 0f 84 eb fd ff ff je 402499 <_nl_find_msg+0x549> + 4026ae: 48 8b 15 8b 99 2c 00 mov 0x2c998b(%rip),%rdx # 6cc040 + 4026b5: b9 e8 0f 00 00 mov $0xfe8,%ecx + 4026ba: 48 89 05 7f 99 2c 00 mov %rax,0x2c997f(%rip) # 6cc040 + 4026c1: 41 be 01 00 00 00 mov $0x1,%r14d + 4026c7: 48 89 10 mov %rdx,(%rax) + 4026ca: e9 5d ff ff ff jmpq 40262c <_nl_find_msg+0x6dc> + 4026cf: bf 78 11 4a 00 mov $0x4a1178,%edi + 4026d4: e8 07 c1 00 00 callq 40e7e0 + 4026d9: 48 85 c0 test %rax,%rax + 4026dc: 49 89 c4 mov %rax,%r12 + 4026df: 74 09 je 4026ea <_nl_find_msg+0x79a> + 4026e1: 80 38 00 cmpb $0x0,(%rax) + 4026e4: 0f 85 64 03 00 00 jne 402a4e <_nl_find_msg+0xafe> + 4026ea: 4c 8b 2d 27 99 2c 00 mov 0x2c9927(%rip),%r13 # 6cc018 + 4026f1: c7 05 25 99 2c 00 01 movl $0x1,0x2c9925(%rip) # 6cc020 + 4026f8: 00 00 00 + 4026fb: e9 5c fd ff ff jmpq 40245c <_nl_find_msg+0x50c> + 402700: 48 8b 9d 68 ff ff ff mov -0x98(%rbp),%rbx + 402707: 48 8b 85 78 ff ff ff mov -0x88(%rbp),%rax + 40270e: 48 85 c0 test %rax,%rax + 402711: 0f 84 6d 03 00 00 je 402a84 <_nl_find_msg+0xb34> + 402717: 48 8b 7d 80 mov -0x80(%rbp),%rdi + 40271b: 48 8d 74 7f 03 lea 0x3(%rdi,%rdi,2),%rsi + 402720: 48 89 c7 mov %rax,%rdi + 402723: 48 c1 e6 03 shl $0x3,%rsi + 402727: e8 44 b8 01 00 callq 41df70 <__libc_realloc> + 40272c: 49 89 c4 mov %rax,%r12 + 40272f: 4d 85 e4 test %r12,%r12 + 402732: 0f 84 0d 02 00 00 je 402945 <_nl_find_msg+0x9f5> + 402738: 48 8b 7d 90 mov -0x70(%rbp),%rdi + 40273c: 4c 89 63 70 mov %r12,0x70(%rbx) + 402740: e8 bb 0e 02 00 callq 423600 <__strdup> + 402745: 48 85 c0 test %rax,%rax + 402748: 49 89 c5 mov %rax,%r13 + 40274b: 0f 84 f4 01 00 00 je 402945 <_nl_find_msg+0x9f5> + 402751: 48 8b 45 80 mov -0x80(%rbp),%rax + 402755: 48 8b bd 70 ff ff ff mov -0x90(%rbp),%rdi + 40275c: 4c 8d 45 c8 lea -0x38(%rbp),%r8 + 402760: 48 8b b5 58 ff ff ff mov -0xa8(%rbp),%rsi + 402767: 31 c9 xor %ecx,%ecx + 402769: ba 25 67 4b 00 mov $0x4b6725,%edx + 40276e: 48 8d 04 40 lea (%rax,%rax,2),%rax + 402772: 4d 8d 24 c4 lea (%r12,%rax,8),%r12 + 402776: 4d 89 2c 24 mov %r13,(%r12) + 40277a: 49 c7 44 24 08 ff ff movq $0xffffffffffffffff,0x8(%r12) + 402781: ff ff + 402783: e8 c8 f7 ff ff callq 401f50 <_nl_find_msg> + 402788: 48 89 c7 mov %rax,%rdi + 40278b: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax + 402792: 48 39 c7 cmp %rax,%rdi + 402795: 0f 84 13 f9 ff ff je 4020ae <_nl_find_msg+0x15e> + 40279b: 48 85 ff test %rdi,%rdi + 40279e: 0f 84 cd 01 00 00 je 402971 <_nl_find_msg+0xa21> + 4027a4: be 87 11 4a 00 mov $0x4a1187,%esi + 4027a9: e8 72 db ff ff callq 400320 <__rela_iplt_end+0x58> + 4027ae: 48 85 c0 test %rax,%rax + 4027b1: 0f 84 ba 01 00 00 je 402971 <_nl_find_msg+0xa21> + 4027b7: 0f b6 50 08 movzbl 0x8(%rax),%edx + 4027bb: 48 8d 70 08 lea 0x8(%rax),%rsi + 4027bf: f6 c2 df test $0xdf,%dl + 4027c2: 0f 84 8b 03 00 00 je 402b53 <_nl_find_msg+0xc03> + 4027c8: 83 ea 09 sub $0x9,%edx + 4027cb: 80 fa 01 cmp $0x1,%dl + 4027ce: ba 00 00 00 00 mov $0x0,%edx + 4027d3: 77 13 ja 4027e8 <_nl_find_msg+0x898> + 4027d5: eb 1f jmp 4027f6 <_nl_find_msg+0x8a6> + 4027d7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 4027de: 00 00 + 4027e0: 83 e9 09 sub $0x9,%ecx + 4027e3: 80 f9 01 cmp $0x1,%cl + 4027e6: 76 0e jbe 4027f6 <_nl_find_msg+0x8a6> + 4027e8: 48 83 c2 01 add $0x1,%rdx + 4027ec: 0f b6 4c 10 08 movzbl 0x8(%rax,%rdx,1),%ecx + 4027f1: f6 c1 df test $0xdf,%cl + 4027f4: 75 ea jne 4027e0 <_nl_find_msg+0x890> + 4027f6: 48 8d 42 1f lea 0x1f(%rdx),%rax + 4027fa: 48 83 e0 f0 and $0xfffffffffffffff0,%rax + 4027fe: 48 29 c4 sub %rax,%rsp + 402801: 4c 8d 44 24 0f lea 0xf(%rsp),%r8 + 402806: 49 83 e0 f0 and $0xfffffffffffffff0,%r8 + 40280a: 4c 89 c7 mov %r8,%rdi + 40280d: 4c 89 45 80 mov %r8,-0x80(%rbp) + 402811: 4c 89 45 90 mov %r8,-0x70(%rbp) + 402815: e8 a6 3d 02 00 callq 4265c0 <__mempcpy> + 40281a: 31 ff xor %edi,%edi + 40281c: c6 00 00 movb $0x0,(%rax) + 40281f: 48 8b 4d 80 mov -0x80(%rbp),%rcx + 402823: 4c 89 e8 mov %r13,%rax + 402826: 4c 8b 45 90 mov -0x70(%rbp),%r8 + 40282a: eb 14 jmp 402840 <_nl_find_msg+0x8f0> + 40282c: 0f 1f 40 00 nopl 0x0(%rax) + 402830: 48 83 c0 01 add $0x1,%rax + 402834: 80 fa 2f cmp $0x2f,%dl + 402837: 0f 94 c2 sete %dl + 40283a: 0f b6 d2 movzbl %dl,%edx + 40283d: 48 01 d7 add %rdx,%rdi + 402840: 0f b6 10 movzbl (%rax),%edx + 402843: 84 d2 test %dl,%dl + 402845: 75 e9 jne 402830 <_nl_find_msg+0x8e0> + 402847: 4c 29 e8 sub %r13,%rax + 40284a: 49 0f be 55 00 movsbq 0x0(%r13),%rdx + 40284f: 48 83 c0 29 add $0x29,%rax + 402853: 48 83 e0 f0 and $0xfffffffffffffff0,%rax + 402857: 48 29 c4 sub %rax,%rsp + 40285a: 48 8d 44 24 0f lea 0xf(%rsp),%rax + 40285f: 48 83 e0 f0 and $0xfffffffffffffff0,%rax + 402863: 84 d2 test %dl,%dl + 402865: 49 89 c1 mov %rax,%r9 + 402868: 74 21 je 40288b <_nl_find_msg+0x93b> + 40286a: 4c 8b 1d 87 fe 0a 00 mov 0xafe87(%rip),%r11 # 4b26f8 <_nl_C_locobj+0x78> + 402871: 4c 89 ee mov %r13,%rsi + 402874: 41 8b 14 93 mov (%r11,%rdx,4),%edx + 402878: 48 83 c0 01 add $0x1,%rax + 40287c: 48 83 c6 01 add $0x1,%rsi + 402880: 88 50 ff mov %dl,-0x1(%rax) + 402883: 48 0f be 16 movsbq (%rsi),%rdx + 402887: 84 d2 test %dl,%dl + 402889: 75 e9 jne 402874 <_nl_find_msg+0x924> + 40288b: 48 83 ff 01 cmp $0x1,%rdi + 40288f: 0f 86 19 02 00 00 jbe 402aae <_nl_find_msg+0xb5e> + 402895: c6 00 00 movb $0x0,(%rax) + 402898: 31 ff xor %edi,%edi + 40289a: 4c 89 c0 mov %r8,%rax + 40289d: eb 11 jmp 4028b0 <_nl_find_msg+0x960> + 40289f: 90 nop + 4028a0: 48 83 c0 01 add $0x1,%rax + 4028a4: 80 fa 2f cmp $0x2f,%dl + 4028a7: 0f 94 c2 sete %dl + 4028aa: 0f b6 d2 movzbl %dl,%edx + 4028ad: 48 01 d7 add %rdx,%rdi + 4028b0: 0f b6 10 movzbl (%rax),%edx + 4028b3: 84 d2 test %dl,%dl + 4028b5: 75 e9 jne 4028a0 <_nl_find_msg+0x950> + 4028b7: 4c 29 c0 sub %r8,%rax + 4028ba: 48 83 c0 21 add $0x21,%rax + 4028be: 48 83 e0 f0 and $0xfffffffffffffff0,%rax + 4028c2: 48 29 c4 sub %rax,%rsp + 4028c5: 49 0f be 00 movsbq (%r8),%rax + 4028c9: 48 8d 74 24 0f lea 0xf(%rsp),%rsi + 4028ce: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi + 4028d2: 84 c0 test %al,%al + 4028d4: 0f 84 80 02 00 00 je 402b5a <_nl_find_msg+0xc0a> + 4028da: 4c 8b 05 17 fe 0a 00 mov 0xafe17(%rip),%r8 # 4b26f8 <_nl_C_locobj+0x78> + 4028e1: 48 89 f2 mov %rsi,%rdx + 4028e4: 41 8b 04 80 mov (%r8,%rax,4),%eax + 4028e8: 48 83 c2 01 add $0x1,%rdx + 4028ec: 48 83 c1 01 add $0x1,%rcx + 4028f0: 88 42 ff mov %al,-0x1(%rdx) + 4028f3: 48 0f be 01 movsbq (%rcx),%rax + 4028f7: 84 c0 test %al,%al + 4028f9: 75 e9 jne 4028e4 <_nl_find_msg+0x994> + 4028fb: 48 83 ff 01 cmp $0x1,%rdi + 4028ff: 0f 86 eb 01 00 00 jbe 402af0 <_nl_find_msg+0xba0> + 402905: c6 02 00 movb $0x0,(%rdx) + 402908: 49 8d 54 24 08 lea 0x8(%r12),%rdx + 40290d: b9 01 00 00 00 mov $0x1,%ecx + 402912: 4c 89 cf mov %r9,%rdi + 402915: e8 46 18 04 00 callq 444160 <__gconv_open> + 40291a: 85 c0 test %eax,%eax + 40291c: 74 53 je 402971 <_nl_find_msg+0xa21> + 40291e: 83 f8 ff cmp $0xffffffff,%eax + 402921: 74 45 je 402968 <_nl_find_msg+0xa18> + 402923: 48 83 7d 88 00 cmpq $0x0,-0x78(%rbp) + 402928: 74 0c je 402936 <_nl_find_msg+0x9e6> + 40292a: 48 8d bb 80 00 00 00 lea 0x80(%rbx),%rdi + 402931: e8 ca d6 bf ff callq 0 <_nl_current_LC_CTYPE> + 402936: 4c 89 ef mov %r13,%rdi + 402939: e8 72 b4 01 00 callq 41ddb0 <__cfree> + 40293e: 31 c0 xor %eax,%eax + 402940: e9 69 f7 ff ff jmpq 4020ae <_nl_find_msg+0x15e> + 402945: 48 83 7d 88 00 cmpq $0x0,-0x78(%rbp) + 40294a: 0f 84 95 fb ff ff je 4024e5 <_nl_find_msg+0x595> + 402950: 48 8d bb 80 00 00 00 lea 0x80(%rbx),%rdi + 402957: e8 a4 d6 bf ff callq 0 <_nl_current_LC_CTYPE> + 40295c: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax + 402963: e9 46 f7 ff ff jmpq 4020ae <_nl_find_msg+0x15e> + 402968: 49 c7 44 24 08 ff ff movq $0xffffffffffffffff,0x8(%r12) + 40296f: ff ff + 402971: 49 c7 44 24 10 00 00 movq $0x0,0x10(%r12) + 402978: 00 00 + 40297a: 48 83 43 78 01 addq $0x1,0x78(%rbx) + 40297f: e9 a7 fa ff ff jmpq 40242b <_nl_find_msg+0x4db> + 402984: 83 3d 31 a8 2c 00 00 cmpl $0x0,0x2ca831(%rip) # 6cd1bc <__libc_multiple_threads> + 40298b: 74 0b je 402998 <_nl_find_msg+0xa48> + 40298d: f0 ff 0d a4 96 2c 00 lock decl 0x2c96a4(%rip) # 6cc038 + 402994: 75 0a jne 4029a0 <_nl_find_msg+0xa50> + 402996: eb 22 jmp 4029ba <_nl_find_msg+0xa6a> + 402998: ff 0d 9a 96 2c 00 decl 0x2c969a(%rip) # 6cc038 + 40299e: 74 1a je 4029ba <_nl_find_msg+0xa6a> + 4029a0: 48 8d 3d 91 96 2c 00 lea 0x2c9691(%rip),%rdi # 6cc038 + 4029a7: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 4029ae: e8 4d fc 03 00 callq 442600 <__lll_unlock_wake_private> + 4029b3: 48 81 c4 80 00 00 00 add $0x80,%rsp + 4029ba: e9 ed f6 ff ff jmpq 4020ac <_nl_find_msg+0x15c> + 4029bf: 48 8b 05 6a 96 2c 00 mov 0x2c966a(%rip),%rax # 6cc030 + 4029c6: 48 8b 55 c0 mov -0x40(%rbp),%rdx + 4029ca: 4c 8b 75 a8 mov -0x58(%rbp),%r14 + 4029ce: 48 29 c2 sub %rax,%rdx + 4029d1: 48 83 ea 08 sub $0x8,%rdx + 4029d5: 48 89 10 mov %rdx,(%rax) + 4029d8: 49 8b 54 24 10 mov 0x10(%r12),%rdx + 4029dd: 4a 89 04 f2 mov %rax,(%rdx,%r14,8) + 4029e1: 48 8b 4d c0 mov -0x40(%rbp),%rcx + 4029e5: 48 29 c8 sub %rcx,%rax + 4029e8: 48 03 05 39 96 2c 00 add 0x2c9639(%rip),%rax # 6cc028 + 4029ef: 48 89 c2 mov %rax,%rdx + 4029f2: 48 83 e0 f8 and $0xfffffffffffffff8,%rax + 4029f6: 83 e2 07 and $0x7,%edx + 4029f9: 48 89 05 28 96 2c 00 mov %rax,0x2c9628(%rip) # 6cc028 + 402a00: 48 01 ca add %rcx,%rdx + 402a03: 48 89 15 26 96 2c 00 mov %rdx,0x2c9626(%rip) # 6cc030 + 402a0a: 83 3d ab a7 2c 00 00 cmpl $0x0,0x2ca7ab(%rip) # 6cd1bc <__libc_multiple_threads> + 402a11: 74 0b je 402a1e <_nl_find_msg+0xace> + 402a13: f0 ff 0d 1e 96 2c 00 lock decl 0x2c961e(%rip) # 6cc038 + 402a1a: 75 0a jne 402a26 <_nl_find_msg+0xad6> + 402a1c: eb 22 jmp 402a40 <_nl_find_msg+0xaf0> + 402a1e: ff 0d 14 96 2c 00 decl 0x2c9614(%rip) # 6cc038 + 402a24: 74 1a je 402a40 <_nl_find_msg+0xaf0> + 402a26: 48 8d 3d 0b 96 2c 00 lea 0x2c960b(%rip),%rdi # 6cc038 + 402a2d: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 402a34: e8 c7 fb 03 00 callq 442600 <__lll_unlock_wake_private> + 402a39: 48 81 c4 80 00 00 00 add $0x80,%rsp + 402a40: 49 8b 44 24 10 mov 0x10(%r12),%rax + 402a45: 4a 8b 04 f0 mov (%rax,%r14,8),%rax + 402a49: e9 cd f7 ff ff jmpq 40221b <_nl_find_msg+0x2cb> + 402a4e: 48 89 c7 mov %rax,%rdi + 402a51: e8 fa 0b 02 00 callq 423650 + 402a56: 4c 8d 78 01 lea 0x1(%rax),%r15 + 402a5a: 4c 89 ff mov %r15,%rdi + 402a5d: e8 ae af 01 00 callq 41da10 <__libc_malloc> + 402a62: 48 85 c0 test %rax,%rax + 402a65: 49 89 c5 mov %rax,%r13 + 402a68: 74 0e je 402a78 <_nl_find_msg+0xb28> + 402a6a: 4c 89 fa mov %r15,%rdx + 402a6d: 4c 89 e6 mov %r12,%rsi + 402a70: 48 89 c7 mov %rax,%rdi + 402a73: e8 a8 95 02 00 callq 42c020 + 402a78: 4c 89 2d 99 95 2c 00 mov %r13,0x2c9599(%rip) # 6cc018 + 402a7f: e9 6d fc ff ff jmpq 4026f1 <_nl_find_msg+0x7a1> + 402a84: 48 8b 45 80 mov -0x80(%rbp),%rax + 402a88: 48 8d 7c 40 03 lea 0x3(%rax,%rax,2),%rdi + 402a8d: 48 c1 e7 03 shl $0x3,%rdi + 402a91: e8 7a af 01 00 callq 41da10 <__libc_malloc> + 402a96: 49 89 c4 mov %rax,%r12 + 402a99: e9 91 fc ff ff jmpq 40272f <_nl_find_msg+0x7df> + 402a9e: 48 8b 43 70 mov 0x70(%rbx),%rax + 402aa2: 48 89 85 78 ff ff ff mov %rax,-0x88(%rbp) + 402aa9: e9 60 fc ff ff jmpq 40270e <_nl_find_msg+0x7be> + 402aae: 48 85 ff test %rdi,%rdi + 402ab1: 48 8d 50 01 lea 0x1(%rax),%rdx + 402ab5: c6 00 2f movb $0x2f,(%rax) + 402ab8: 74 5f je 402b19 <_nl_find_msg+0xbc9> + 402aba: 48 89 d0 mov %rdx,%rax + 402abd: e9 d3 fd ff ff jmpq 402895 <_nl_find_msg+0x945> + 402ac2: 8b 7d a8 mov -0x58(%rbp),%edi + 402ac5: 03 7b 40 add 0x40(%rbx),%edi + 402ac8: be 08 00 00 00 mov $0x8,%esi + 402acd: e8 ee ba 01 00 callq 41e5c0 <__calloc> + 402ad2: 48 85 c0 test %rax,%rax + 402ad5: 49 89 44 24 10 mov %rax,0x10(%r12) + 402ada: 0f 85 d7 fa ff ff jne 4025b7 <_nl_find_msg+0x667> + 402ae0: 49 c7 44 24 10 ff ff movq $0xffffffffffffffff,0x10(%r12) + 402ae7: ff ff + 402ae9: e9 4c fa ff ff jmpq 40253a <_nl_find_msg+0x5ea> + 402aee: 66 90 xchg %ax,%ax + 402af0: 48 85 ff test %rdi,%rdi + 402af3: 48 8d 42 01 lea 0x1(%rdx),%rax + 402af7: c6 02 2f movb $0x2f,(%rdx) + 402afa: 75 0d jne 402b09 <_nl_find_msg+0xbb9> + 402afc: c6 42 01 2f movb $0x2f,0x1(%rdx) + 402b00: 48 83 c2 02 add $0x2,%rdx + 402b04: e9 fc fd ff ff jmpq 402905 <_nl_find_msg+0x9b5> + 402b09: 48 89 c2 mov %rax,%rdx + 402b0c: e9 f4 fd ff ff jmpq 402905 <_nl_find_msg+0x9b5> + 402b11: 4c 89 e3 mov %r12,%rbx + 402b14: e9 db f5 ff ff jmpq 4020f4 <_nl_find_msg+0x1a4> + 402b19: 48 8d 78 02 lea 0x2(%rax),%rdi + 402b1d: c6 40 01 2f movb $0x2f,0x1(%rax) + 402b21: ba 08 00 00 00 mov $0x8,%edx + 402b26: be b1 3f 4a 00 mov $0x4a3fb1,%esi + 402b2b: 4c 89 8d 78 ff ff ff mov %r9,-0x88(%rbp) + 402b32: 4c 89 45 80 mov %r8,-0x80(%rbp) + 402b36: 48 89 4d 90 mov %rcx,-0x70(%rbp) + 402b3a: e8 81 3a 02 00 callq 4265c0 <__mempcpy> + 402b3f: 48 8b 4d 90 mov -0x70(%rbp),%rcx + 402b43: 4c 8b 45 80 mov -0x80(%rbp),%r8 + 402b47: 4c 8b 8d 78 ff ff ff mov -0x88(%rbp),%r9 + 402b4e: e9 42 fd ff ff jmpq 402895 <_nl_find_msg+0x945> + 402b53: 31 d2 xor %edx,%edx + 402b55: e9 9c fc ff ff jmpq 4027f6 <_nl_find_msg+0x8a6> + 402b5a: 48 89 f2 mov %rsi,%rdx + 402b5d: e9 99 fd ff ff jmpq 4028fb <_nl_find_msg+0x9ab> + 402b62: 0f 1f 40 00 nopl 0x0(%rax) + 402b66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 402b6d: 00 00 00 + +0000000000402b70 <__dcigettext>: + 402b70: 55 push %rbp + 402b71: 48 89 e5 mov %rsp,%rbp + 402b74: 41 57 push %r15 + 402b76: 41 56 push %r14 + 402b78: 41 55 push %r13 + 402b7a: 41 54 push %r12 + 402b7c: 53 push %rbx + 402b7d: 48 81 ec b8 00 00 00 sub $0xb8,%rsp + 402b84: 48 85 f6 test %rsi,%rsi + 402b87: 48 89 bd 60 ff ff ff mov %rdi,-0xa0(%rbp) + 402b8e: 48 89 b5 70 ff ff ff mov %rsi,-0x90(%rbp) + 402b95: 48 89 95 48 ff ff ff mov %rdx,-0xb8(%rbp) + 402b9c: 89 8d 58 ff ff ff mov %ecx,-0xa8(%rbp) + 402ba2: 4c 89 85 50 ff ff ff mov %r8,-0xb0(%rbp) + 402ba9: 44 89 8d 5c ff ff ff mov %r9d,-0xa4(%rbp) + 402bb0: 0f 84 9a 08 00 00 je 403450 <__dcigettext+0x8e0> + 402bb6: 41 83 f9 0c cmp $0xc,%r9d + 402bba: 0f 87 46 03 00 00 ja 402f06 <__dcigettext+0x396> + 402bc0: 41 83 f9 06 cmp $0x6,%r9d + 402bc4: 0f 84 3c 03 00 00 je 402f06 <__dcigettext+0x396> + 402bca: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 402bd1: bb 00 00 00 00 mov $0x0,%ebx + 402bd6: 48 85 db test %rbx,%rbx + 402bd9: 64 8b 00 mov %fs:(%rax),%eax + 402bdc: 89 85 3c ff ff ff mov %eax,-0xc4(%rbp) + 402be2: 0f 84 65 04 00 00 je 40304d <__dcigettext+0x4dd> + 402be8: bf 20 c7 6c 00 mov $0x6cc720,%edi + 402bed: ff d3 callq *%rbx + 402bef: bf e0 bf 6c 00 mov $0x6cbfe0,%edi + 402bf4: ff d3 callq *%rbx + 402bf6: 48 83 bd 60 ff ff ff cmpq $0x0,-0xa0(%rbp) + 402bfd: 00 + 402bfe: 0f 84 91 05 00 00 je 403195 <__dcigettext+0x625> + 402c04: 48 8b 85 70 ff ff ff mov -0x90(%rbp),%rax + 402c0b: 48 c7 45 b0 00 00 00 movq $0x0,-0x50(%rbp) + 402c12: 00 + 402c13: 48 89 45 c8 mov %rax,-0x38(%rbp) + 402c17: 48 8b 85 60 ff ff ff mov -0xa0(%rbp),%rax + 402c1e: 48 89 45 90 mov %rax,-0x70(%rbp) + 402c22: 8b 85 5c ff ff ff mov -0xa4(%rbp),%eax + 402c28: 89 c7 mov %eax,%edi + 402c2a: 89 45 98 mov %eax,-0x68(%rbp) + 402c2d: e8 fe c6 04 00 callq 44f330 <__current_locale_name> + 402c32: 48 89 c7 mov %rax,%rdi + 402c35: 48 89 c3 mov %rax,%rbx + 402c38: e8 13 0a 02 00 callq 423650 + 402c3d: 48 8d 50 01 lea 0x1(%rax),%rdx + 402c41: 48 83 c0 1f add $0x1f,%rax + 402c45: 48 89 de mov %rbx,%rsi + 402c48: 48 83 e0 f0 and $0xfffffffffffffff0,%rax + 402c4c: 48 29 c4 sub %rax,%rsp + 402c4f: 48 8d 7c 24 0f lea 0xf(%rsp),%rdi + 402c54: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi + 402c58: e8 c3 93 02 00 callq 42c020 + 402c5d: 48 89 85 30 ff ff ff mov %rax,-0xd0(%rbp) + 402c64: 48 89 45 a0 mov %rax,-0x60(%rbp) + 402c68: bf 60 c0 6c 00 mov $0x6cc060,%edi + 402c6d: e8 8e d3 bf ff callq 0 <_nl_current_LC_CTYPE> + 402c72: 48 8d 7d 90 lea -0x70(%rbp),%rdi + 402c76: ba 90 17 40 00 mov $0x401790,%edx + 402c7b: be 48 c0 6c 00 mov $0x6cc048,%esi + 402c80: e8 7b d9 03 00 callq 440600 <__tfind> + 402c85: 48 89 85 40 ff ff ff mov %rax,-0xc0(%rbp) + 402c8c: b8 00 00 00 00 mov $0x0,%eax + 402c91: 48 85 c0 test %rax,%rax + 402c94: 74 07 je 402c9d <__dcigettext+0x12d> + 402c96: bf 60 c0 6c 00 mov $0x6cc060,%edi + 402c9b: ff d0 callq *%rax + 402c9d: 48 8b 85 40 ff ff ff mov -0xc0(%rbp),%rax + 402ca4: 48 85 c0 test %rax,%rax + 402ca7: 74 12 je 402cbb <__dcigettext+0x14b> + 402ca9: 48 8b 00 mov (%rax),%rax + 402cac: 8b 0d f6 a4 2c 00 mov 0x2ca4f6(%rip),%ecx # 6cd1a8 <_nl_msg_cat_cntr> + 402cb2: 39 48 18 cmp %ecx,0x18(%rax) + 402cb5: 0f 84 02 04 00 00 je 4030bd <__dcigettext+0x54d> + 402cbb: 48 8b 1d de a4 2c 00 mov 0x2ca4de(%rip),%rbx # 6cd1a0 <_nl_domain_bindings> + 402cc2: 48 85 db test %rbx,%rbx + 402cc5: 0f 84 6a 02 00 00 je 402f35 <__dcigettext+0x3c5> + 402ccb: 4c 8b a5 60 ff ff ff mov -0xa0(%rbp),%r12 + 402cd2: eb 16 jmp 402cea <__dcigettext+0x17a> + 402cd4: 0f 1f 40 00 nopl 0x0(%rax) + 402cd8: 0f 88 55 02 00 00 js 402f33 <__dcigettext+0x3c3> + 402cde: 48 8b 1b mov (%rbx),%rbx + 402ce1: 48 85 db test %rbx,%rbx + 402ce4: 0f 84 4b 02 00 00 je 402f35 <__dcigettext+0x3c5> + 402cea: 48 8d 73 18 lea 0x18(%rbx),%rsi + 402cee: 4c 89 e7 mov %r12,%rdi + 402cf1: e8 6a d6 ff ff callq 400360 <__rela_iplt_end+0x98> + 402cf6: 85 c0 test %eax,%eax + 402cf8: 75 de jne 402cd8 <__dcigettext+0x168> + 402cfa: 48 8b 43 08 mov 0x8(%rbx),%rax + 402cfe: 80 38 2f cmpb $0x2f,(%rax) + 402d01: 48 89 85 78 ff ff ff mov %rax,-0x88(%rbp) + 402d08: 0f 84 8d 00 00 00 je 402d9b <__dcigettext+0x22b> + 402d0e: 48 89 c7 mov %rax,%rdi + 402d11: 41 bd 02 10 00 00 mov $0x1002,%r13d + 402d17: e8 34 09 02 00 callq 423650 + 402d1c: 4c 8d 78 01 lea 0x1(%rax),%r15 + 402d20: eb 22 jmp 402d44 <__dcigettext+0x1d4> + 402d22: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 402d28: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 402d2f: 64 83 38 22 cmpl $0x22,%fs:(%rax) + 402d33: 0f 85 a2 01 00 00 jne 402edb <__dcigettext+0x36b> + 402d39: 4c 89 e8 mov %r13,%rax + 402d3c: 48 d1 e8 shr %rax + 402d3f: 4d 8d 6c 05 20 lea 0x20(%r13,%rax,1),%r13 + 402d44: 4b 8d 44 3d 1e lea 0x1e(%r13,%r15,1),%rax + 402d49: 4c 89 ee mov %r13,%rsi + 402d4c: 48 83 e0 f0 and $0xfffffffffffffff0,%rax + 402d50: 48 29 c4 sub %rax,%rsp + 402d53: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 402d5a: 4c 8d 64 24 0f lea 0xf(%rsp),%r12 + 402d5f: 49 83 e4 f0 and $0xfffffffffffffff0,%r12 + 402d63: 64 c7 00 00 00 00 00 movl $0x0,%fs:(%rax) + 402d6a: 4c 89 e7 mov %r12,%rdi + 402d6d: e8 5e c6 03 00 callq 43f3d0 <__getcwd> + 402d72: 48 85 c0 test %rax,%rax + 402d75: 74 b1 je 402d28 <__dcigettext+0x1b8> + 402d77: 31 f6 xor %esi,%esi + 402d79: 4c 89 e7 mov %r12,%rdi + 402d7c: e8 4f 9c 02 00 callq 42c9d0 <__rawmemchr> + 402d81: 48 8b b5 78 ff ff ff mov -0x88(%rbp),%rsi + 402d88: 48 8d 78 01 lea 0x1(%rax),%rdi + 402d8c: c6 00 2f movb $0x2f,(%rax) + 402d8f: e8 5c d5 ff ff callq 4002f0 <__rela_iplt_end+0x28> + 402d94: 4c 89 a5 78 ff ff ff mov %r12,-0x88(%rbp) + 402d9b: 8b bd 5c ff ff ff mov -0xa4(%rbp),%edi + 402da1: 48 63 c7 movslq %edi,%rax + 402da4: 44 0f b6 a0 b8 5f 4a movzbl 0x4a5fb8(%rax),%r12d + 402dab: 00 + 402dac: e8 7f c5 04 00 callq 44f330 <__current_locale_name> + 402db1: 49 89 c5 mov %rax,%r13 + 402db4: 49 81 c4 e0 5f 4a 00 add $0x4a5fe0,%r12 + 402dbb: 80 38 43 cmpb $0x43,(%rax) + 402dbe: 0f 85 81 01 00 00 jne 402f45 <__dcigettext+0x3d5> + 402dc4: 80 78 01 00 cmpb $0x0,0x1(%rax) + 402dc8: 0f 85 77 01 00 00 jne 402f45 <__dcigettext+0x3d5> + 402dce: 4c 8b bd 60 ff ff ff mov -0xa0(%rbp),%r15 + 402dd5: 4c 89 ff mov %r15,%rdi + 402dd8: e8 73 08 02 00 callq 423650 + 402ddd: 4c 89 e7 mov %r12,%rdi + 402de0: 49 89 c6 mov %rax,%r14 + 402de3: 48 89 85 20 ff ff ff mov %rax,-0xe0(%rbp) + 402dea: e8 61 08 02 00 callq 423650 + 402def: 49 8d 44 06 23 lea 0x23(%r14,%rax,1),%rax + 402df4: 4c 89 e6 mov %r12,%rsi + 402df7: 48 83 e0 f0 and $0xfffffffffffffff0,%rax + 402dfb: 48 29 c4 sub %rax,%rsp + 402dfe: 48 8d 44 24 0f lea 0xf(%rsp),%rax + 402e03: 48 83 e0 f0 and $0xfffffffffffffff0,%rax + 402e07: 48 89 c7 mov %rax,%rdi + 402e0a: 48 89 85 68 ff ff ff mov %rax,-0x98(%rbp) + 402e11: e8 fa d4 ff ff callq 400310 <__rela_iplt_end+0x48> + 402e16: b9 2f 00 00 00 mov $0x2f,%ecx + 402e1b: 48 8d 78 01 lea 0x1(%rax),%rdi + 402e1f: 4c 89 f2 mov %r14,%rdx + 402e22: 66 89 08 mov %cx,(%rax) + 402e25: 4c 89 fe mov %r15,%rsi + 402e28: e8 93 37 02 00 callq 4265c0 <__mempcpy> + 402e2d: 4c 89 ef mov %r13,%rdi + 402e30: c7 00 2e 6d 6f 00 movl $0x6f6d2e,(%rax) + 402e36: e8 15 08 02 00 callq 423650 + 402e3b: 48 83 c0 1f add $0x1f,%rax + 402e3f: 48 83 e0 f0 and $0xfffffffffffffff0,%rax + 402e43: 48 29 c4 sub %rax,%rsp + 402e46: 4c 8d 64 24 0f lea 0xf(%rsp),%r12 + 402e4b: 49 83 e4 f0 and $0xfffffffffffffff0,%r12 + 402e4f: 90 nop + 402e50: 41 0f b6 45 00 movzbl 0x0(%r13),%eax + 402e55: 3c 3a cmp $0x3a,%al + 402e57: 0f 84 73 01 00 00 je 402fd0 <__dcigettext+0x460> + 402e5d: 84 c0 test %al,%al + 402e5f: 0f 85 0b 01 00 00 jne 402f70 <__dcigettext+0x400> + 402e65: 41 c6 04 24 43 movb $0x43,(%r12) + 402e6a: 41 c6 44 24 01 00 movb $0x0,0x1(%r12) + 402e70: 41 80 7c 24 01 00 cmpb $0x0,0x1(%r12) + 402e76: 74 63 je 402edb <__dcigettext+0x36b> + 402e78: bf 99 11 4a 00 mov $0x4a1199,%edi + 402e7d: b9 06 00 00 00 mov $0x6,%ecx + 402e82: 4c 89 e6 mov %r12,%rsi + 402e85: f3 a6 repz cmpsb %es:(%rdi),%ds:(%rsi) + 402e87: 74 52 je 402edb <__dcigettext+0x36b> + 402e89: 48 8b 95 68 ff ff ff mov -0x98(%rbp),%rdx + 402e90: 48 8b bd 78 ff ff ff mov -0x88(%rbp),%rdi + 402e97: 48 89 d9 mov %rbx,%rcx + 402e9a: 4c 89 e6 mov %r12,%rsi + 402e9d: e8 2e 06 00 00 callq 4034d0 <_nl_find_domain> + 402ea2: 48 85 c0 test %rax,%rax + 402ea5: 49 89 c7 mov %rax,%r15 + 402ea8: 74 a6 je 402e50 <__dcigettext+0x2e0> + 402eaa: 48 8b 95 70 ff ff ff mov -0x90(%rbp),%rdx + 402eb1: 4c 8d 45 88 lea -0x78(%rbp),%r8 + 402eb5: b9 01 00 00 00 mov $0x1,%ecx + 402eba: 48 89 de mov %rbx,%rsi + 402ebd: 48 89 c7 mov %rax,%rdi + 402ec0: e8 8b f0 ff ff callq 401f50 <_nl_find_msg> + 402ec5: 48 85 c0 test %rax,%rax + 402ec8: 0f 84 12 01 00 00 je 402fe0 <__dcigettext+0x470> + 402ece: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 402ed2: 48 89 c1 mov %rax,%rcx + 402ed5: 0f 85 2f 02 00 00 jne 40310a <__dcigettext+0x59a> + 402edb: b8 00 00 00 00 mov $0x0,%eax + 402ee0: 48 85 c0 test %rax,%rax + 402ee3: 74 11 je 402ef6 <__dcigettext+0x386> + 402ee5: bf e0 bf 6c 00 mov $0x6cbfe0,%edi + 402eea: ff d0 callq *%rax + 402eec: bf 20 c7 6c 00 mov $0x6cc720,%edi + 402ef1: e8 0a d1 bf ff callq 0 <_nl_current_LC_CTYPE> + 402ef6: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 402efd: 8b 8d 3c ff ff ff mov -0xc4(%rbp),%ecx + 402f03: 64 89 08 mov %ecx,%fs:(%rax) + 402f06: 48 83 bd 50 ff ff ff cmpq $0x1,-0xb0(%rbp) + 402f0d: 01 + 402f0e: 74 54 je 402f64 <__dcigettext+0x3f4> + 402f10: 8b bd 58 ff ff ff mov -0xa8(%rbp),%edi + 402f16: 4c 8b ad 48 ff ff ff mov -0xb8(%rbp),%r13 + 402f1d: 85 ff test %edi,%edi + 402f1f: 74 43 je 402f64 <__dcigettext+0x3f4> + 402f21: 48 8d 65 d8 lea -0x28(%rbp),%rsp + 402f25: 4c 89 e8 mov %r13,%rax + 402f28: 5b pop %rbx + 402f29: 41 5c pop %r12 + 402f2b: 41 5d pop %r13 + 402f2d: 41 5e pop %r14 + 402f2f: 41 5f pop %r15 + 402f31: 5d pop %rbp + 402f32: c3 retq + 402f33: 31 db xor %ebx,%ebx + 402f35: 48 c7 85 78 ff ff ff movq $0x4a11a0,-0x88(%rbp) + 402f3c: a0 11 4a 00 + 402f40: e9 56 fe ff ff jmpq 402d9b <__dcigettext+0x22b> + 402f45: bf 90 11 4a 00 mov $0x4a1190,%edi + 402f4a: e8 91 b8 00 00 callq 40e7e0 + 402f4f: 48 85 c0 test %rax,%rax + 402f52: 0f 84 76 fe ff ff je 402dce <__dcigettext+0x25e> + 402f58: 80 38 00 cmpb $0x0,(%rax) + 402f5b: 4c 0f 45 e8 cmovne %rax,%r13 + 402f5f: e9 6a fe ff ff jmpq 402dce <__dcigettext+0x25e> + 402f64: 4c 8b ad 70 ff ff ff mov -0x90(%rbp),%r13 + 402f6b: eb b4 jmp 402f21 <__dcigettext+0x3b1> + 402f6d: 0f 1f 00 nopl (%rax) + 402f70: 4c 89 e2 mov %r12,%rdx + 402f73: eb 07 jmp 402f7c <__dcigettext+0x40c> + 402f75: 0f 1f 00 nopl (%rax) + 402f78: 3c 3a cmp $0x3a,%al + 402f7a: 74 14 je 402f90 <__dcigettext+0x420> + 402f7c: 48 83 c2 01 add $0x1,%rdx + 402f80: 49 83 c5 01 add $0x1,%r13 + 402f84: 88 42 ff mov %al,-0x1(%rdx) + 402f87: 41 0f b6 45 00 movzbl 0x0(%r13),%eax + 402f8c: 84 c0 test %al,%al + 402f8e: 75 e8 jne 402f78 <__dcigettext+0x408> + 402f90: c6 02 00 movb $0x0,(%rdx) + 402f93: 8b 15 ff 6f 2c 00 mov 0x2c6fff(%rip),%edx # 6c9f98 <__libc_enable_secure> + 402f99: 85 d2 test %edx,%edx + 402f9b: 74 1b je 402fb8 <__dcigettext+0x448> + 402f9d: be 2f 00 00 00 mov $0x2f,%esi + 402fa2: 4c 89 e7 mov %r12,%rdi + 402fa5: e8 d6 d3 ff ff callq 400380 <__rela_iplt_end+0xb8> + 402faa: 48 85 c0 test %rax,%rax + 402fad: 0f 85 9d fe ff ff jne 402e50 <__dcigettext+0x2e0> + 402fb3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 402fb8: 41 0f b6 04 24 movzbl (%r12),%eax + 402fbd: 3c 43 cmp $0x43,%al + 402fbf: 0f 85 b3 fe ff ff jne 402e78 <__dcigettext+0x308> + 402fc5: e9 a6 fe ff ff jmpq 402e70 <__dcigettext+0x300> + 402fca: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 402fd0: 49 83 c5 01 add $0x1,%r13 + 402fd4: e9 77 fe ff ff jmpq 402e50 <__dcigettext+0x2e0> + 402fd9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 402fe0: 49 8b 7f 20 mov 0x20(%r15),%rdi + 402fe4: 48 85 ff test %rdi,%rdi + 402fe7: 0f 84 63 fe ff ff je 402e50 <__dcigettext+0x2e0> + 402fed: 45 31 f6 xor %r14d,%r14d + 402ff0: 4c 89 ad 28 ff ff ff mov %r13,-0xd8(%rbp) + 402ff7: 45 89 f5 mov %r14d,%r13d + 402ffa: 4d 89 e6 mov %r12,%r14 + 402ffd: 4c 8b a5 70 ff ff ff mov -0x90(%rbp),%r12 + 403004: eb 28 jmp 40302e <__dcigettext+0x4be> + 403006: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 40300d: 00 00 00 + 403010: 48 85 c0 test %rax,%rax + 403013: 0f 85 e6 00 00 00 jne 4030ff <__dcigettext+0x58f> + 403019: 41 83 c5 01 add $0x1,%r13d + 40301d: 49 63 c5 movslq %r13d,%rax + 403020: 49 8b 7c c7 20 mov 0x20(%r15,%rax,8),%rdi + 403025: 48 85 ff test %rdi,%rdi + 403028: 0f 84 58 01 00 00 je 403186 <__dcigettext+0x616> + 40302e: 4c 8d 45 88 lea -0x78(%rbp),%r8 + 403032: b9 01 00 00 00 mov $0x1,%ecx + 403037: 4c 89 e2 mov %r12,%rdx + 40303a: 48 89 de mov %rbx,%rsi + 40303d: e8 0e ef ff ff callq 401f50 <_nl_find_msg> + 403042: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 403046: 75 c8 jne 403010 <__dcigettext+0x4a0> + 403048: e9 8e fe ff ff jmpq 402edb <__dcigettext+0x36b> + 40304d: 48 83 bd 60 ff ff ff cmpq $0x0,-0xa0(%rbp) + 403054: 00 + 403055: 0f 84 3a 01 00 00 je 403195 <__dcigettext+0x625> + 40305b: 48 8b 85 60 ff ff ff mov -0xa0(%rbp),%rax + 403062: 48 89 75 c8 mov %rsi,-0x38(%rbp) + 403066: 48 c7 45 b0 00 00 00 movq $0x0,-0x50(%rbp) + 40306d: 00 + 40306e: 48 89 45 90 mov %rax,-0x70(%rbp) + 403072: 8b 85 5c ff ff ff mov -0xa4(%rbp),%eax + 403078: 89 c7 mov %eax,%edi + 40307a: 89 45 98 mov %eax,-0x68(%rbp) + 40307d: e8 ae c2 04 00 callq 44f330 <__current_locale_name> + 403082: 48 89 c7 mov %rax,%rdi + 403085: 48 89 c3 mov %rax,%rbx + 403088: e8 c3 05 02 00 callq 423650 + 40308d: 48 8d 50 01 lea 0x1(%rax),%rdx + 403091: 48 83 c0 1f add $0x1f,%rax + 403095: 48 89 de mov %rbx,%rsi + 403098: 48 83 e0 f0 and $0xfffffffffffffff0,%rax + 40309c: 48 29 c4 sub %rax,%rsp + 40309f: 48 8d 7c 24 0f lea 0xf(%rsp),%rdi + 4030a4: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi + 4030a8: e8 73 8f 02 00 callq 42c020 + 4030ad: 48 89 85 30 ff ff ff mov %rax,-0xd0(%rbp) + 4030b4: 48 89 45 a0 mov %rax,-0x60(%rbp) + 4030b8: e9 b5 fb ff ff jmpq 402c72 <__dcigettext+0x102> + 4030bd: 8b b5 58 ff ff ff mov -0xa8(%rbp),%esi + 4030c3: 85 f6 test %esi,%esi + 4030c5: 0f 85 1d 03 00 00 jne 4033e8 <__dcigettext+0x878> + 4030cb: 4c 8b 68 28 mov 0x28(%rax),%r13 + 4030cf: b8 00 00 00 00 mov $0x0,%eax + 4030d4: 48 85 c0 test %rax,%rax + 4030d7: 74 11 je 4030ea <__dcigettext+0x57a> + 4030d9: bf e0 bf 6c 00 mov $0x6cbfe0,%edi + 4030de: ff d0 callq *%rax + 4030e0: bf 20 c7 6c 00 mov $0x6cc720,%edi + 4030e5: e8 16 cf bf ff callq 0 <_nl_current_LC_CTYPE> + 4030ea: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 4030f1: 8b 8d 3c ff ff ff mov -0xc4(%rbp),%ecx + 4030f7: 64 89 08 mov %ecx,%fs:(%rax) + 4030fa: e9 22 fe ff ff jmpq 402f21 <__dcigettext+0x3b1> + 4030ff: 4d 63 d5 movslq %r13d,%r10 + 403102: 48 89 c1 mov %rax,%rcx + 403105: 4f 8b 7c d7 20 mov 0x20(%r15,%r10,8),%r15 + 40310a: 48 83 bd 40 ff ff ff cmpq $0x0,-0xc0(%rbp) + 403111: 00 + 403112: 0f 84 f6 00 00 00 je 40320e <__dcigettext+0x69e> + 403118: 48 8b 9d 40 ff ff ff mov -0xc0(%rbp),%rbx + 40311f: 8b 15 83 a0 2c 00 mov 0x2ca083(%rip),%edx # 6cd1a8 <_nl_msg_cat_cntr> + 403125: 48 8b 03 mov (%rbx),%rax + 403128: 89 50 18 mov %edx,0x18(%rax) + 40312b: 4c 89 78 20 mov %r15,0x20(%rax) + 40312f: 48 8b 03 mov (%rbx),%rax + 403132: 48 8b 55 88 mov -0x78(%rbp),%rdx + 403136: 48 89 48 28 mov %rcx,0x28(%rax) + 40313a: 48 8b 03 mov (%rbx),%rax + 40313d: 48 89 50 30 mov %rdx,0x30(%rax) + 403141: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 403148: 8b 9d 3c ff ff ff mov -0xc4(%rbp),%ebx + 40314e: 64 89 18 mov %ebx,%fs:(%rax) + 403151: 8b 85 58 ff ff ff mov -0xa8(%rbp),%eax + 403157: 85 c0 test %eax,%eax + 403159: 0f 85 f9 02 00 00 jne 403458 <__dcigettext+0x8e8> + 40315f: b8 00 00 00 00 mov $0x0,%eax + 403164: 49 89 cd mov %rcx,%r13 + 403167: 48 85 c0 test %rax,%rax + 40316a: 0f 84 b1 fd ff ff je 402f21 <__dcigettext+0x3b1> + 403170: bf e0 bf 6c 00 mov $0x6cbfe0,%edi + 403175: ff d0 callq *%rax + 403177: bf 20 c7 6c 00 mov $0x6cc720,%edi + 40317c: e8 7f ce bf ff callq 0 <_nl_current_LC_CTYPE> + 403181: e9 9b fd ff ff jmpq 402f21 <__dcigettext+0x3b1> + 403186: 4c 8b ad 28 ff ff ff mov -0xd8(%rbp),%r13 + 40318d: 4d 89 f4 mov %r14,%r12 + 403190: e9 bb fc ff ff jmpq 402e50 <__dcigettext+0x2e0> + 403195: 48 8b 05 fc 6e 2c 00 mov 0x2c6efc(%rip),%rax # 6ca098 <_nl_current_default_domain> + 40319c: 48 8b 8d 70 ff ff ff mov -0x90(%rbp),%rcx + 4031a3: 48 c7 45 b0 00 00 00 movq $0x0,-0x50(%rbp) + 4031aa: 00 + 4031ab: 48 89 85 60 ff ff ff mov %rax,-0xa0(%rbp) + 4031b2: 48 89 45 90 mov %rax,-0x70(%rbp) + 4031b6: 8b 85 5c ff ff ff mov -0xa4(%rbp),%eax + 4031bc: 48 89 4d c8 mov %rcx,-0x38(%rbp) + 4031c0: 89 c7 mov %eax,%edi + 4031c2: 89 45 98 mov %eax,-0x68(%rbp) + 4031c5: e8 66 c1 04 00 callq 44f330 <__current_locale_name> + 4031ca: 48 89 c7 mov %rax,%rdi + 4031cd: 49 89 c4 mov %rax,%r12 + 4031d0: e8 7b 04 02 00 callq 423650 + 4031d5: 48 8d 50 01 lea 0x1(%rax),%rdx + 4031d9: 48 83 c0 1f add $0x1f,%rax + 4031dd: 4c 89 e6 mov %r12,%rsi + 4031e0: 48 83 e0 f0 and $0xfffffffffffffff0,%rax + 4031e4: 48 29 c4 sub %rax,%rsp + 4031e7: 48 8d 7c 24 0f lea 0xf(%rsp),%rdi + 4031ec: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi + 4031f0: e8 2b 8e 02 00 callq 42c020 + 4031f5: 48 85 db test %rbx,%rbx + 4031f8: 48 89 85 30 ff ff ff mov %rax,-0xd0(%rbp) + 4031ff: 48 89 45 a0 mov %rax,-0x60(%rbp) + 403203: 0f 85 5f fa ff ff jne 402c68 <__dcigettext+0xf8> + 403209: e9 64 fa ff ff jmpq 402c72 <__dcigettext+0x102> + 40320e: 48 8b bd 70 ff ff ff mov -0x90(%rbp),%rdi + 403215: 48 89 8d 78 ff ff ff mov %rcx,-0x88(%rbp) + 40321c: e8 2f 04 02 00 callq 423650 + 403221: 4c 8b a5 30 ff ff ff mov -0xd0(%rbp),%r12 + 403228: 48 8b 8d 78 ff ff ff mov -0x88(%rbp),%rcx + 40322f: 48 8d 58 01 lea 0x1(%rax),%rbx + 403233: 41 8b 14 24 mov (%r12),%edx + 403237: 49 83 c4 04 add $0x4,%r12 + 40323b: 8d 82 ff fe fe fe lea -0x1010101(%rdx),%eax + 403241: f7 d2 not %edx + 403243: 21 d0 and %edx,%eax + 403245: 25 80 80 80 80 and $0x80808080,%eax + 40324a: 74 e7 je 403233 <__dcigettext+0x6c3> + 40324c: 89 c2 mov %eax,%edx + 40324e: 48 89 8d 78 ff ff ff mov %rcx,-0x88(%rbp) + 403255: 4c 8b b5 20 ff ff ff mov -0xe0(%rbp),%r14 + 40325c: c1 ea 10 shr $0x10,%edx + 40325f: a9 80 80 00 00 test $0x8080,%eax + 403264: 0f 44 c2 cmove %edx,%eax + 403267: 49 8d 54 24 02 lea 0x2(%r12),%rdx + 40326c: 89 c1 mov %eax,%ecx + 40326e: 4c 0f 44 e2 cmove %rdx,%r12 + 403272: 00 c1 add %al,%cl + 403274: 49 83 dc 03 sbb $0x3,%r12 + 403278: 4c 2b a5 30 ff ff ff sub -0xd0(%rbp),%r12 + 40327f: 4b 8d 7c 34 3a lea 0x3a(%r12,%r14,1),%rdi + 403284: 48 01 df add %rbx,%rdi + 403287: e8 84 a7 01 00 callq 41da10 <__libc_malloc> + 40328c: 48 85 c0 test %rax,%rax + 40328f: 48 8b 8d 78 ff ff ff mov -0x88(%rbp),%rcx + 403296: 0f 84 a5 fe ff ff je 403141 <__dcigettext+0x5d1> + 40329c: 48 8b b5 70 ff ff ff mov -0x90(%rbp),%rsi + 4032a3: 48 8d 78 38 lea 0x38(%rax),%rdi + 4032a7: 48 89 da mov %rbx,%rdx + 4032aa: 48 89 8d 68 ff ff ff mov %rcx,-0x98(%rbp) + 4032b1: 48 89 85 78 ff ff ff mov %rax,-0x88(%rbp) + 4032b8: e8 03 33 02 00 callq 4265c0 <__mempcpy> + 4032bd: 48 8b b5 60 ff ff ff mov -0xa0(%rbp),%rsi + 4032c4: 48 89 c3 mov %rax,%rbx + 4032c7: 4c 89 f0 mov %r14,%rax + 4032ca: 48 83 c0 01 add $0x1,%rax + 4032ce: 48 89 df mov %rbx,%rdi + 4032d1: 49 89 c5 mov %rax,%r13 + 4032d4: 48 89 c2 mov %rax,%rdx + 4032d7: e8 44 8d 02 00 callq 42c020 + 4032dc: 4e 8d 0c 2b lea (%rbx,%r13,1),%r9 + 4032e0: 48 8b b5 30 ff ff ff mov -0xd0(%rbp),%rsi + 4032e7: 49 8d 54 24 01 lea 0x1(%r12),%rdx + 4032ec: 4c 89 cf mov %r9,%rdi + 4032ef: e8 2c 8d 02 00 callq 42c020 + 4032f4: 4c 8b 85 78 ff ff ff mov -0x88(%rbp),%r8 + 4032fb: 49 89 c1 mov %rax,%r9 + 4032fe: 8b 85 5c ff ff ff mov -0xa4(%rbp),%eax + 403304: 48 8b 8d 68 ff ff ff mov -0x98(%rbp),%rcx + 40330b: 41 89 40 08 mov %eax,0x8(%r8) + 40330f: 8b 05 93 9e 2c 00 mov 0x2c9e93(%rip),%eax # 6cd1a8 <_nl_msg_cat_cntr> + 403315: 49 89 18 mov %rbx,(%r8) + 403318: 4d 89 48 10 mov %r9,0x10(%r8) + 40331c: 4d 89 78 20 mov %r15,0x20(%r8) + 403320: 49 89 48 28 mov %rcx,0x28(%r8) + 403324: 41 89 40 18 mov %eax,0x18(%r8) + 403328: 48 8b 45 88 mov -0x78(%rbp),%rax + 40332c: 49 89 40 30 mov %rax,0x30(%r8) + 403330: b8 00 00 00 00 mov $0x0,%eax + 403335: 48 85 c0 test %rax,%rax + 403338: 74 23 je 40335d <__dcigettext+0x7ed> + 40333a: 4c 89 85 70 ff ff ff mov %r8,-0x90(%rbp) + 403341: 48 89 8d 78 ff ff ff mov %rcx,-0x88(%rbp) + 403348: bf 60 c0 6c 00 mov $0x6cc060,%edi + 40334d: ff d0 callq *%rax + 40334f: 4c 8b 85 70 ff ff ff mov -0x90(%rbp),%r8 + 403356: 48 8b 8d 78 ff ff ff mov -0x88(%rbp),%rcx + 40335d: 4c 89 c7 mov %r8,%rdi + 403360: ba 90 17 40 00 mov $0x401790,%edx + 403365: be 48 c0 6c 00 mov $0x6cc048,%esi + 40336a: 48 89 8d 70 ff ff ff mov %rcx,-0x90(%rbp) + 403371: 4c 89 85 78 ff ff ff mov %r8,-0x88(%rbp) + 403378: e8 23 cf 03 00 callq 4402a0 <__tsearch> + 40337d: 48 89 c3 mov %rax,%rbx + 403380: b8 00 00 00 00 mov $0x0,%eax + 403385: 4c 8b 85 78 ff ff ff mov -0x88(%rbp),%r8 + 40338c: 48 85 c0 test %rax,%rax + 40338f: 48 8b 8d 70 ff ff ff mov -0x90(%rbp),%rcx + 403396: 74 23 je 4033bb <__dcigettext+0x84b> + 403398: 4c 89 85 70 ff ff ff mov %r8,-0x90(%rbp) + 40339f: 48 89 8d 78 ff ff ff mov %rcx,-0x88(%rbp) + 4033a6: bf 60 c0 6c 00 mov $0x6cc060,%edi + 4033ab: ff d0 callq *%rax + 4033ad: 4c 8b 85 70 ff ff ff mov -0x90(%rbp),%r8 + 4033b4: 48 8b 8d 78 ff ff ff mov -0x88(%rbp),%rcx + 4033bb: 48 85 db test %rbx,%rbx + 4033be: 74 09 je 4033c9 <__dcigettext+0x859> + 4033c0: 4c 3b 03 cmp (%rbx),%r8 + 4033c3: 0f 84 78 fd ff ff je 403141 <__dcigettext+0x5d1> + 4033c9: 4c 89 c7 mov %r8,%rdi + 4033cc: 48 89 8d 78 ff ff ff mov %rcx,-0x88(%rbp) + 4033d3: e8 d8 a9 01 00 callq 41ddb0 <__cfree> + 4033d8: 48 8b 8d 78 ff ff ff mov -0x88(%rbp),%rcx + 4033df: e9 5d fd ff ff jmpq 403141 <__dcigettext+0x5d1> + 4033e4: 0f 1f 40 00 nopl 0x0(%rax) + 4033e8: 48 8b 58 30 mov 0x30(%rax),%rbx + 4033ec: 4c 8b 68 28 mov 0x28(%rax),%r13 + 4033f0: 48 8b 40 20 mov 0x20(%rax),%rax + 4033f4: 48 8b b5 50 ff ff ff mov -0xb0(%rbp),%rsi + 4033fb: 4c 8b 60 10 mov 0x10(%rax),%r12 + 4033ff: 49 8b bc 24 b8 00 00 mov 0xb8(%r12),%rdi + 403406: 00 + 403407: e8 04 e4 ff ff callq 401810 + 40340c: 49 3b 84 24 c0 00 00 cmp 0xc0(%r12),%rax + 403413: 00 + 403414: 0f 83 b5 fc ff ff jae 4030cf <__dcigettext+0x55f> + 40341a: 4c 89 ef mov %r13,%rdi + 40341d: 49 89 c4 mov %rax,%r12 + 403420: 4c 01 eb add %r13,%rbx + 403423: eb 1b jmp 403440 <__dcigettext+0x8d0> + 403425: 0f 1f 00 nopl (%rax) + 403428: 31 f6 xor %esi,%esi + 40342a: 49 83 ec 01 sub $0x1,%r12 + 40342e: e8 9d 95 02 00 callq 42c9d0 <__rawmemchr> + 403433: 48 8d 78 01 lea 0x1(%rax),%rdi + 403437: 48 39 df cmp %rbx,%rdi + 40343a: 0f 83 8f fc ff ff jae 4030cf <__dcigettext+0x55f> + 403440: 4d 85 e4 test %r12,%r12 + 403443: 75 e3 jne 403428 <__dcigettext+0x8b8> + 403445: 49 89 fd mov %rdi,%r13 + 403448: e9 82 fc ff ff jmpq 4030cf <__dcigettext+0x55f> + 40344d: 0f 1f 00 nopl (%rax) + 403450: 45 31 ed xor %r13d,%r13d + 403453: e9 c9 fa ff ff jmpq 402f21 <__dcigettext+0x3b1> + 403458: 4d 8b 67 10 mov 0x10(%r15),%r12 + 40345c: 48 8b b5 50 ff ff ff mov -0xb0(%rbp),%rsi + 403463: 48 89 8d 78 ff ff ff mov %rcx,-0x88(%rbp) + 40346a: 48 8b 5d 88 mov -0x78(%rbp),%rbx + 40346e: 49 8b bc 24 b8 00 00 mov 0xb8(%r12),%rdi + 403475: 00 + 403476: e8 95 e3 ff ff callq 401810 + 40347b: 49 3b 84 24 c0 00 00 cmp 0xc0(%r12),%rax + 403482: 00 + 403483: 48 8b 8d 78 ff ff ff mov -0x88(%rbp),%rcx + 40348a: 0f 83 cf fc ff ff jae 40315f <__dcigettext+0x5ef> + 403490: 48 89 cf mov %rcx,%rdi + 403493: 49 89 c4 mov %rax,%r12 + 403496: 48 01 cb add %rcx,%rbx + 403499: 49 89 cd mov %rcx,%r13 + 40349c: 4d 85 e4 test %r12,%r12 + 40349f: 74 1c je 4034bd <__dcigettext+0x94d> + 4034a1: 31 f6 xor %esi,%esi + 4034a3: 49 83 ec 01 sub $0x1,%r12 + 4034a7: e8 24 95 02 00 callq 42c9d0 <__rawmemchr> + 4034ac: 48 8d 78 01 lea 0x1(%rax),%rdi + 4034b0: 48 39 df cmp %rbx,%rdi + 4034b3: 72 e7 jb 40349c <__dcigettext+0x92c> + 4034b5: 4c 89 e9 mov %r13,%rcx + 4034b8: e9 a2 fc ff ff jmpq 40315f <__dcigettext+0x5ef> + 4034bd: 48 89 f9 mov %rdi,%rcx + 4034c0: e9 9a fc ff ff jmpq 40315f <__dcigettext+0x5ef> + 4034c5: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4034cc: 00 00 00 + 4034cf: 90 nop + +00000000004034d0 <_nl_find_domain>: + 4034d0: 41 57 push %r15 + 4034d2: 41 56 push %r14 + 4034d4: b8 00 00 00 00 mov $0x0,%eax + 4034d9: 41 55 push %r13 + 4034db: 41 54 push %r12 + 4034dd: 49 89 f5 mov %rsi,%r13 + 4034e0: 55 push %rbp + 4034e1: 53 push %rbx + 4034e2: 48 89 fd mov %rdi,%rbp + 4034e5: 49 89 d6 mov %rdx,%r14 + 4034e8: 49 89 cc mov %rcx,%r12 + 4034eb: 48 83 ec 48 sub $0x48,%rsp + 4034ef: 48 85 c0 test %rax,%rax + 4034f2: 74 07 je 4034fb <_nl_find_domain+0x2b> + 4034f4: bf a0 c0 6c 00 mov $0x6cc0a0,%edi + 4034f9: ff d0 callq *%rax + 4034fb: 48 89 ef mov %rbp,%rdi + 4034fe: 41 bf 00 00 00 00 mov $0x0,%r15d + 403504: e8 47 01 02 00 callq 423650 + 403509: 48 83 ec 08 sub $0x8,%rsp + 40350d: 48 8d 50 01 lea 0x1(%rax),%rdx + 403511: 45 31 c9 xor %r9d,%r9d + 403514: 6a 00 pushq $0x0 + 403516: 41 56 push %r14 + 403518: 31 c9 xor %ecx,%ecx + 40351a: 6a 00 pushq $0x0 + 40351c: 6a 00 pushq $0x0 + 40351e: 4d 89 e8 mov %r13,%r8 + 403521: 6a 00 pushq $0x0 + 403523: 48 89 ee mov %rbp,%rsi + 403526: bf d8 c0 6c 00 mov $0x6cc0d8,%edi + 40352b: e8 b0 1d 00 00 callq 4052e0 <_nl_make_l10nflist> + 403530: 48 83 c4 30 add $0x30,%rsp + 403534: 4d 85 ff test %r15,%r15 + 403537: 48 89 c3 mov %rax,%rbx + 40353a: 74 08 je 403544 <_nl_find_domain+0x74> + 40353c: bf a0 c0 6c 00 mov $0x6cc0a0,%edi + 403541: 41 ff d7 callq *%r15 + 403544: 48 85 db test %rbx,%rbx + 403547: 0f 84 93 00 00 00 je 4035e0 <_nl_find_domain+0x110> + 40354d: 8b 73 08 mov 0x8(%rbx),%esi + 403550: 85 f6 test %esi,%esi + 403552: 7e 74 jle 4035c8 <_nl_find_domain+0xf8> + 403554: 48 83 7b 10 00 cmpq $0x0,0x10(%rbx) + 403559: 48 89 d8 mov %rbx,%rax + 40355c: 74 12 je 403570 <_nl_find_domain+0xa0> + 40355e: 48 83 c4 48 add $0x48,%rsp + 403562: 5b pop %rbx + 403563: 5d pop %rbp + 403564: 41 5c pop %r12 + 403566: 41 5d pop %r13 + 403568: 41 5e pop %r14 + 40356a: 41 5f pop %r15 + 40356c: c3 retq + 40356d: 0f 1f 00 nopl (%rax) + 403570: 48 8b 7b 20 mov 0x20(%rbx),%rdi + 403574: 48 85 ff test %rdi,%rdi + 403577: 74 e5 je 40355e <_nl_find_domain+0x8e> + 403579: 31 ed xor %ebp,%ebp + 40357b: eb 1a jmp 403597 <_nl_find_domain+0xc7> + 40357d: 0f 1f 00 nopl (%rax) + 403580: 48 83 7f 10 00 cmpq $0x0,0x10(%rdi) + 403585: 75 29 jne 4035b0 <_nl_find_domain+0xe0> + 403587: 83 c5 01 add $0x1,%ebp + 40358a: 48 63 c5 movslq %ebp,%rax + 40358d: 48 8b 7c c3 20 mov 0x20(%rbx,%rax,8),%rdi + 403592: 48 85 ff test %rdi,%rdi + 403595: 74 19 je 4035b0 <_nl_find_domain+0xe0> + 403597: 8b 4f 08 mov 0x8(%rdi),%ecx + 40359a: 85 c9 test %ecx,%ecx + 40359c: 7f e2 jg 403580 <_nl_find_domain+0xb0> + 40359e: 4c 89 e6 mov %r12,%rsi + 4035a1: e8 9a 01 00 00 callq 403740 <_nl_load_domain> + 4035a6: 48 63 c5 movslq %ebp,%rax + 4035a9: 48 8b 7c c3 20 mov 0x20(%rbx,%rax,8),%rdi + 4035ae: eb d0 jmp 403580 <_nl_find_domain+0xb0> + 4035b0: 48 83 c4 48 add $0x48,%rsp + 4035b4: 48 89 d8 mov %rbx,%rax + 4035b7: 5b pop %rbx + 4035b8: 5d pop %rbp + 4035b9: 41 5c pop %r12 + 4035bb: 41 5d pop %r13 + 4035bd: 41 5e pop %r14 + 4035bf: 41 5f pop %r15 + 4035c1: c3 retq + 4035c2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4035c8: 4c 89 e6 mov %r12,%rsi + 4035cb: 48 89 df mov %rbx,%rdi + 4035ce: e8 6d 01 00 00 callq 403740 <_nl_load_domain> + 4035d3: e9 7c ff ff ff jmpq 403554 <_nl_find_domain+0x84> + 4035d8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 4035df: 00 + 4035e0: 4c 89 ef mov %r13,%rdi + 4035e3: e8 38 1b 00 00 callq 405120 <_nl_expand_alias> + 4035e8: 48 85 c0 test %rax,%rax + 4035eb: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4035f0: 74 14 je 403606 <_nl_find_domain+0x136> + 4035f2: 48 89 c7 mov %rax,%rdi + 4035f5: e8 06 00 02 00 callq 423600 <__strdup> + 4035fa: 48 85 c0 test %rax,%rax + 4035fd: 49 89 c5 mov %rax,%r13 + 403600: 0f 84 2b 01 00 00 je 403731 <_nl_find_domain+0x261> + 403606: 4c 8d 4c 24 38 lea 0x38(%rsp),%r9 + 40360b: 4c 8d 44 24 30 lea 0x30(%rsp),%r8 + 403610: 48 8d 4c 24 28 lea 0x28(%rsp),%rcx + 403615: 48 8d 54 24 20 lea 0x20(%rsp),%rdx + 40361a: 48 8d 74 24 18 lea 0x18(%rsp),%rsi + 40361f: 4c 89 ef mov %r13,%rdi + 403622: e8 89 23 00 00 callq 4059b0 <_nl_explode_name> + 403627: 83 f8 ff cmp $0xffffffff,%eax + 40362a: 89 c3 mov %eax,%ebx + 40362c: 0f 84 ff 00 00 00 je 403731 <_nl_find_domain+0x261> + 403632: b8 00 00 00 00 mov $0x0,%eax + 403637: 48 85 c0 test %rax,%rax + 40363a: 74 07 je 403643 <_nl_find_domain+0x173> + 40363c: bf a0 c0 6c 00 mov $0x6cc0a0,%edi + 403641: ff d0 callq *%rax + 403643: 48 89 ef mov %rbp,%rdi + 403646: e8 05 00 02 00 callq 423650 + 40364b: 48 83 ec 08 sub $0x8,%rsp + 40364f: 48 8d 50 01 lea 0x1(%rax),%rdx + 403653: 48 89 ee mov %rbp,%rsi + 403656: 6a 01 pushq $0x1 + 403658: 41 56 push %r14 + 40365a: 89 d9 mov %ebx,%ecx + 40365c: ff 74 24 38 pushq 0x38(%rsp) + 403660: ff 74 24 58 pushq 0x58(%rsp) + 403664: bf d8 c0 6c 00 mov $0x6cc0d8,%edi + 403669: ff 74 24 58 pushq 0x58(%rsp) + 40366d: 4c 8b 4c 24 58 mov 0x58(%rsp),%r9 + 403672: 4c 8b 44 24 48 mov 0x48(%rsp),%r8 + 403677: e8 64 1c 00 00 callq 4052e0 <_nl_make_l10nflist> + 40367c: 48 83 c4 30 add $0x30,%rsp + 403680: 4d 85 ff test %r15,%r15 + 403683: 48 89 c5 mov %rax,%rbp + 403686: 74 0a je 403692 <_nl_find_domain+0x1c2> + 403688: bf a0 c0 6c 00 mov $0x6cc0a0,%edi + 40368d: e8 6e c9 bf ff callq 0 <_nl_current_LC_CTYPE> + 403692: 48 85 ed test %rbp,%rbp + 403695: 74 22 je 4036b9 <_nl_find_domain+0x1e9> + 403697: 8b 55 08 mov 0x8(%rbp),%edx + 40369a: 85 d2 test %edx,%edx + 40369c: 0f 8e 7f 00 00 00 jle 403721 <_nl_find_domain+0x251> + 4036a2: 48 83 7d 10 00 cmpq $0x0,0x10(%rbp) + 4036a7: 74 35 je 4036de <_nl_find_domain+0x20e> + 4036a9: 48 83 7c 24 08 00 cmpq $0x0,0x8(%rsp) + 4036af: 74 08 je 4036b9 <_nl_find_domain+0x1e9> + 4036b1: 4c 89 ef mov %r13,%rdi + 4036b4: e8 f7 a6 01 00 callq 41ddb0 <__cfree> + 4036b9: 83 e3 01 and $0x1,%ebx + 4036bc: 48 89 e8 mov %rbp,%rax + 4036bf: 0f 84 99 fe ff ff je 40355e <_nl_find_domain+0x8e> + 4036c5: 48 8b 7c 24 38 mov 0x38(%rsp),%rdi + 4036ca: 48 89 6c 24 08 mov %rbp,0x8(%rsp) + 4036cf: e8 dc a6 01 00 callq 41ddb0 <__cfree> + 4036d4: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4036d9: e9 80 fe ff ff jmpq 40355e <_nl_find_domain+0x8e> + 4036de: 48 8b 7d 20 mov 0x20(%rbp),%rdi + 4036e2: 48 85 ff test %rdi,%rdi + 4036e5: 74 c2 je 4036a9 <_nl_find_domain+0x1d9> + 4036e7: 45 31 f6 xor %r14d,%r14d + 4036ea: eb 1c jmp 403708 <_nl_find_domain+0x238> + 4036ec: 0f 1f 40 00 nopl 0x0(%rax) + 4036f0: 48 83 7f 10 00 cmpq $0x0,0x10(%rdi) + 4036f5: 75 b2 jne 4036a9 <_nl_find_domain+0x1d9> + 4036f7: 41 83 c6 01 add $0x1,%r14d + 4036fb: 49 63 c6 movslq %r14d,%rax + 4036fe: 48 8b 7c c5 20 mov 0x20(%rbp,%rax,8),%rdi + 403703: 48 85 ff test %rdi,%rdi + 403706: 74 a1 je 4036a9 <_nl_find_domain+0x1d9> + 403708: 8b 47 08 mov 0x8(%rdi),%eax + 40370b: 85 c0 test %eax,%eax + 40370d: 7f e1 jg 4036f0 <_nl_find_domain+0x220> + 40370f: 4c 89 e6 mov %r12,%rsi + 403712: e8 29 00 00 00 callq 403740 <_nl_load_domain> + 403717: 49 63 c6 movslq %r14d,%rax + 40371a: 48 8b 7c c5 20 mov 0x20(%rbp,%rax,8),%rdi + 40371f: eb cf jmp 4036f0 <_nl_find_domain+0x220> + 403721: 4c 89 e6 mov %r12,%rsi + 403724: 48 89 ef mov %rbp,%rdi + 403727: e8 14 00 00 00 callq 403740 <_nl_load_domain> + 40372c: e9 71 ff ff ff jmpq 4036a2 <_nl_find_domain+0x1d2> + 403731: 31 c0 xor %eax,%eax + 403733: e9 26 fe ff ff jmpq 40355e <_nl_find_domain+0x8e> + 403738: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 40373f: 00 + +0000000000403740 <_nl_load_domain>: + 403740: 55 push %rbp + 403741: 49 89 f0 mov %rsi,%r8 + 403744: 64 48 8b 14 25 10 00 mov %fs:0x10,%rdx + 40374b: 00 00 + 40374d: 48 89 e5 mov %rsp,%rbp + 403750: 41 57 push %r15 + 403752: 41 56 push %r14 + 403754: 41 55 push %r13 + 403756: 41 54 push %r12 + 403758: 53 push %rbx + 403759: 48 89 fb mov %rdi,%rbx + 40375c: 48 81 ec 38 01 00 00 sub $0x138,%rsp + 403763: 48 3b 15 7e 89 2c 00 cmp 0x2c897e(%rip),%rdx # 6cc0e8 + 40376a: 74 46 je 4037b2 <_nl_load_domain+0x72> + 40376c: be 01 00 00 00 mov $0x1,%esi + 403771: 31 c0 xor %eax,%eax + 403773: 83 3d 42 9a 2c 00 00 cmpl $0x0,0x2c9a42(%rip) # 6cd1bc <__libc_multiple_threads> + 40377a: 74 0c je 403788 <_nl_load_domain+0x48> + 40377c: f0 0f b1 35 5c 89 2c lock cmpxchg %esi,0x2c895c(%rip) # 6cc0e0 + 403783: 00 + 403784: 75 0b jne 403791 <_nl_load_domain+0x51> + 403786: eb 23 jmp 4037ab <_nl_load_domain+0x6b> + 403788: 0f b1 35 51 89 2c 00 cmpxchg %esi,0x2c8951(%rip) # 6cc0e0 + 40378f: 74 1a je 4037ab <_nl_load_domain+0x6b> + 403791: 48 8d 3d 48 89 2c 00 lea 0x2c8948(%rip),%rdi # 6cc0e0 + 403798: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 40379f: e8 2c ee 03 00 callq 4425d0 <__lll_lock_wait_private> + 4037a4: 48 81 c4 80 00 00 00 add $0x80,%rsp + 4037ab: 48 89 15 36 89 2c 00 mov %rdx,0x2c8936(%rip) # 6cc0e8 + 4037b2: 8b 05 2c 89 2c 00 mov 0x2c892c(%rip),%eax # 6cc0e4 + 4037b8: 44 8b 63 08 mov 0x8(%rbx),%r12d + 4037bc: 83 c0 01 add $0x1,%eax + 4037bf: 45 85 e4 test %r12d,%r12d + 4037c2: 89 05 1c 89 2c 00 mov %eax,0x2c891c(%rip) # 6cc0e4 + 4037c8: 75 4b jne 403815 <_nl_load_domain+0xd5> + 4037ca: 48 8b 3b mov (%rbx),%rdi + 4037cd: 4d 89 c6 mov %r8,%r14 + 4037d0: c7 43 08 ff ff ff ff movl $0xffffffff,0x8(%rbx) + 4037d7: 48 c7 43 10 00 00 00 movq $0x0,0x10(%rbx) + 4037de: 00 + 4037df: 48 85 ff test %rdi,%rdi + 4037e2: 74 2a je 40380e <_nl_load_domain+0xce> + 4037e4: b9 02 00 00 00 mov $0x2,%ecx + 4037e9: 31 f6 xor %esi,%esi + 4037eb: 89 c8 mov %ecx,%eax + 4037ed: 0f 05 syscall + 4037ef: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 4037f5: 49 89 c4 mov %rax,%r12 + 4037f8: 76 7e jbe 403878 <_nl_load_domain+0x138> + 4037fa: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 403801: 41 f7 dc neg %r12d + 403804: 64 44 89 20 mov %r12d,%fs:(%rax) + 403808: 8b 05 d6 88 2c 00 mov 0x2c88d6(%rip),%eax # 6cc0e4 + 40380e: c7 43 08 01 00 00 00 movl $0x1,0x8(%rbx) + 403815: 83 e8 01 sub $0x1,%eax + 403818: 85 c0 test %eax,%eax + 40381a: 89 05 c4 88 2c 00 mov %eax,0x2c88c4(%rip) # 6cc0e4 + 403820: 75 41 jne 403863 <_nl_load_domain+0x123> + 403822: 48 c7 05 bb 88 2c 00 movq $0x0,0x2c88bb(%rip) # 6cc0e8 + 403829: 00 00 00 00 + 40382d: 83 3d 88 99 2c 00 00 cmpl $0x0,0x2c9988(%rip) # 6cd1bc <__libc_multiple_threads> + 403834: 74 0b je 403841 <_nl_load_domain+0x101> + 403836: f0 ff 0d a3 88 2c 00 lock decl 0x2c88a3(%rip) # 6cc0e0 + 40383d: 75 0a jne 403849 <_nl_load_domain+0x109> + 40383f: eb 22 jmp 403863 <_nl_load_domain+0x123> + 403841: ff 0d 99 88 2c 00 decl 0x2c8899(%rip) # 6cc0e0 + 403847: 74 1a je 403863 <_nl_load_domain+0x123> + 403849: 48 8d 3d 90 88 2c 00 lea 0x2c8890(%rip),%rdi # 6cc0e0 + 403850: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 403857: e8 a4 ed 03 00 callq 442600 <__lll_unlock_wake_private> + 40385c: 48 81 c4 80 00 00 00 add $0x80,%rsp + 403863: 48 8d 65 d8 lea -0x28(%rbp),%rsp + 403867: 5b pop %rbx + 403868: 41 5c pop %r12 + 40386a: 41 5d pop %r13 + 40386c: 41 5e pop %r14 + 40386e: 41 5f pop %r15 + 403870: 5d pop %rbp + 403871: c3 retq + 403872: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 403878: 83 f8 ff cmp $0xffffffff,%eax + 40387b: 74 24 je 4038a1 <_nl_load_domain+0x161> + 40387d: 48 8d 95 40 ff ff ff lea -0xc0(%rbp),%rdx + 403884: 89 c6 mov %eax,%esi + 403886: bf 01 00 00 00 mov $0x1,%edi + 40388b: e8 40 b8 03 00 callq 43f0d0 <__fxstat> + 403890: 85 c0 test %eax,%eax + 403892: 74 1c je 4038b0 <_nl_load_domain+0x170> + 403894: 4d 63 e4 movslq %r12d,%r12 + 403897: 4c 89 e7 mov %r12,%rdi + 40389a: b8 03 00 00 00 mov $0x3,%eax + 40389f: 0f 05 syscall + 4038a1: 8b 05 3d 88 2c 00 mov 0x2c883d(%rip),%eax # 6cc0e4 + 4038a7: e9 62 ff ff ff jmpq 40380e <_nl_load_domain+0xce> + 4038ac: 0f 1f 40 00 nopl 0x0(%rax) + 4038b0: 4c 8b ad 70 ff ff ff mov -0x90(%rbp),%r13 + 4038b7: 49 83 fd 2f cmp $0x2f,%r13 + 4038bb: 76 d7 jbe 403894 <_nl_load_domain+0x154> + 4038bd: 45 31 c9 xor %r9d,%r9d + 4038c0: 31 ff xor %edi,%edi + 4038c2: 45 89 e0 mov %r12d,%r8d + 4038c5: b9 02 00 00 00 mov $0x2,%ecx + 4038ca: ba 01 00 00 00 mov $0x1,%edx + 4038cf: 4c 89 ee mov %r13,%rsi + 4038d2: e8 19 c3 03 00 callq 43fbf0 <__mmap> + 4038d7: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 4038db: 49 89 c7 mov %rax,%r15 + 4038de: 0f 84 b1 01 00 00 je 403a95 <_nl_load_domain+0x355> + 4038e4: 49 63 fc movslq %r12d,%rdi + 4038e7: b8 03 00 00 00 mov $0x3,%eax + 4038ec: 0f 05 syscall + 4038ee: 41 8b 07 mov (%r15),%eax + 4038f1: 3d de 12 04 95 cmp $0x950412de,%eax + 4038f6: 0f 95 c2 setne %dl + 4038f9: 3d 95 04 12 de cmp $0xde120495,%eax + 4038fe: 88 95 20 ff ff ff mov %dl,-0xe0(%rbp) + 403904: 74 1a je 403920 <_nl_load_domain+0x1e0> + 403906: 84 d2 test %dl,%dl + 403908: 74 16 je 403920 <_nl_load_domain+0x1e0> + 40390a: 4c 89 ee mov %r13,%rsi + 40390d: 4c 89 ff mov %r15,%rdi + 403910: e8 9b c3 03 00 callq 43fcb0 <__munmap> + 403915: eb 8a jmp 4038a1 <_nl_load_domain+0x161> + 403917: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 40391e: 00 00 + 403920: c7 85 1c ff ff ff 01 movl $0x1,-0xe4(%rbp) + 403927: 00 00 00 + 40392a: bf c8 00 00 00 mov $0xc8,%edi + 40392f: e8 dc a0 01 00 callq 41da10 <__libc_malloc> + 403934: 48 85 c0 test %rax,%rax + 403937: 48 89 85 28 ff ff ff mov %rax,-0xd8(%rbp) + 40393e: 0f 84 5d ff ff ff je 4038a1 <_nl_load_domain+0x161> + 403944: 0f b6 95 20 ff ff ff movzbl -0xe0(%rbp),%edx + 40394b: 8b 8d 1c ff ff ff mov -0xe4(%rbp),%ecx + 403951: 48 89 43 10 mov %rax,0x10(%rbx) + 403955: 4c 89 38 mov %r15,(%rax) + 403958: 4c 89 68 10 mov %r13,0x10(%rax) + 40395c: 48 c7 40 20 00 00 00 movq $0x0,0x20(%rax) + 403963: 00 + 403964: 89 48 08 mov %ecx,0x8(%rax) + 403967: 84 d2 test %dl,%dl + 403969: 89 50 18 mov %edx,0x18(%rax) + 40396c: 41 8b 47 04 mov 0x4(%r15),%eax + 403970: 0f 84 bd 01 00 00 je 403b33 <_nl_load_domain+0x3f3> + 403976: 0f c8 bswap %eax + 403978: 3d ff ff 01 00 cmp $0x1ffff,%eax + 40397d: 0f 87 4b 02 00 00 ja 403bce <_nl_load_domain+0x48e> + 403983: 41 8b 4f 08 mov 0x8(%r15),%ecx + 403987: 48 8b b5 28 ff ff ff mov -0xd8(%rbp),%rsi + 40398e: 45 8b 57 14 mov 0x14(%r15),%r10d + 403992: 0f c9 bswap %ecx + 403994: 89 4e 28 mov %ecx,0x28(%rsi) + 403997: 41 8b 4f 0c mov 0xc(%r15),%ecx + 40399b: 41 0f ca bswap %r10d + 40399e: 0f c9 bswap %ecx + 4039a0: 89 c9 mov %ecx,%ecx + 4039a2: 4c 01 f9 add %r15,%rcx + 4039a5: 48 89 4e 30 mov %rcx,0x30(%rsi) + 4039a9: 41 8b 4f 10 mov 0x10(%r15),%ecx + 4039ad: 44 89 56 58 mov %r10d,0x58(%rsi) + 4039b1: 0f c9 bswap %ecx + 4039b3: 89 c9 mov %ecx,%ecx + 4039b5: 4c 01 f9 add %r15,%rcx + 4039b8: 41 83 fa 02 cmp $0x2,%r10d + 4039bc: 48 89 4e 38 mov %rcx,0x38(%rsi) + 4039c0: 0f 86 b3 01 00 00 jbe 403b79 <_nl_load_domain+0x439> + 4039c6: 41 8b 4f 18 mov 0x18(%r15),%ecx + 4039ca: 0f c9 bswap %ecx + 4039cc: 89 c9 mov %ecx,%ecx + 4039ce: 4c 01 f9 add %r15,%rcx + 4039d1: 66 85 c0 test %ax,%ax + 4039d4: 89 56 68 mov %edx,0x68(%rsi) + 4039d7: 48 89 4e 60 mov %rcx,0x60(%rsi) + 4039db: 74 2a je 403a07 <_nl_load_domain+0x2c7> + 4039dd: 48 85 c9 test %rcx,%rcx + 4039e0: 0f 84 e8 01 00 00 je 403bce <_nl_load_domain+0x48e> + 4039e6: 80 bd 20 ff ff ff 00 cmpb $0x0,-0xe0(%rbp) + 4039ed: 41 8b 47 24 mov 0x24(%r15),%eax + 4039f1: 0f 84 02 02 00 00 je 403bf9 <_nl_load_domain+0x4b9> + 4039f7: 0f c8 bswap %eax + 4039f9: 85 c0 test %eax,%eax + 4039fb: 89 85 e0 fe ff ff mov %eax,-0x120(%rbp) + 403a01: 0f 85 9b 03 00 00 jne 403da2 <_nl_load_domain+0x662> + 403a07: 48 8b 85 28 ff ff ff mov -0xd8(%rbp),%rax + 403a0e: c7 40 40 00 00 00 00 movl $0x0,0x40(%rax) + 403a15: 48 c7 40 48 00 00 00 movq $0x0,0x48(%rax) + 403a1c: 00 + 403a1d: 48 89 c1 mov %rax,%rcx + 403a20: 48 c7 40 50 00 00 00 movq $0x0,0x50(%rax) + 403a27: 00 + 403a28: b8 00 00 00 00 mov $0x0,%eax + 403a2d: 48 c7 41 70 00 00 00 movq $0x0,0x70(%rcx) + 403a34: 00 + 403a35: 48 c7 41 78 00 00 00 movq $0x0,0x78(%rcx) + 403a3c: 00 + 403a3d: 48 85 c0 test %rax,%rax + 403a40: 74 0e je 403a50 <_nl_load_domain+0x310> + 403a42: 48 8d b9 80 00 00 00 lea 0x80(%rcx),%rdi + 403a49: 31 f6 xor %esi,%esi + 403a4b: e8 b0 c5 bf ff callq 0 <_nl_current_LC_CTYPE> + 403a50: 4c 8d 85 30 ff ff ff lea -0xd0(%rbp),%r8 + 403a57: 31 c9 xor %ecx,%ecx + 403a59: ba 25 67 4b 00 mov $0x4b6725,%edx + 403a5e: 4c 89 f6 mov %r14,%rsi + 403a61: 48 89 df mov %rbx,%rdi + 403a64: e8 e7 e4 ff ff callq 401f50 <_nl_find_msg> + 403a69: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 403a6d: 0f 84 5f 01 00 00 je 403bd2 <_nl_load_domain+0x492> + 403a73: 48 8b 8d 28 ff ff ff mov -0xd8(%rbp),%rcx + 403a7a: 48 89 c7 mov %rax,%rdi + 403a7d: 48 8d 91 c0 00 00 00 lea 0xc0(%rcx),%rdx + 403a84: 48 8d b1 b8 00 00 00 lea 0xb8(%rcx),%rsi + 403a8b: e8 c0 9f 00 00 callq 40da50 <__gettext_extract_plural> + 403a90: e9 0c fe ff ff jmpq 4038a1 <_nl_load_domain+0x161> + 403a95: 4c 89 ef mov %r13,%rdi + 403a98: e8 73 9f 01 00 callq 41da10 <__libc_malloc> + 403a9d: 48 85 c0 test %rax,%rax + 403aa0: 49 89 c7 mov %rax,%r15 + 403aa3: 0f 84 eb fd ff ff je 403894 <_nl_load_domain+0x154> + 403aa9: 4d 63 e4 movslq %r12d,%r12 + 403aac: 49 89 c1 mov %rax,%r9 + 403aaf: 4d 89 e8 mov %r13,%r8 + 403ab2: 45 31 d2 xor %r10d,%r10d + 403ab5: 4c 89 c2 mov %r8,%rdx + 403ab8: 4c 89 ce mov %r9,%rsi + 403abb: 4c 89 e7 mov %r12,%rdi + 403abe: 44 89 d0 mov %r10d,%eax + 403ac1: 0f 05 syscall + 403ac3: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 403ac9: 76 57 jbe 403b22 <_nl_load_domain+0x3e2> + 403acb: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx + 403ad2: f7 d8 neg %eax + 403ad4: 83 f8 04 cmp $0x4,%eax + 403ad7: 64 89 02 mov %eax,%fs:(%rdx) + 403ada: 0f 85 b7 fd ff ff jne 403897 <_nl_load_domain+0x157> + 403ae0: 4d 85 c0 test %r8,%r8 + 403ae3: 75 d0 jne 403ab5 <_nl_load_domain+0x375> + 403ae5: 4c 89 e7 mov %r12,%rdi + 403ae8: b8 03 00 00 00 mov $0x3,%eax + 403aed: 0f 05 syscall + 403aef: 41 8b 17 mov (%r15),%edx + 403af2: 81 fa de 12 04 95 cmp $0x950412de,%edx + 403af8: 0f 95 c0 setne %al + 403afb: 81 fa 95 04 12 de cmp $0xde120495,%edx + 403b01: 88 85 20 ff ff ff mov %al,-0xe0(%rbp) + 403b07: 0f 84 e5 0a 00 00 je 4045f2 <_nl_load_domain+0xeb2> + 403b0d: 84 c0 test %al,%al + 403b0f: 0f 84 dd 0a 00 00 je 4045f2 <_nl_load_domain+0xeb2> + 403b15: 4c 89 ff mov %r15,%rdi + 403b18: e8 93 a2 01 00 callq 41ddb0 <__cfree> + 403b1d: e9 7f fd ff ff jmpq 4038a1 <_nl_load_domain+0x161> + 403b22: 48 85 c0 test %rax,%rax + 403b25: 0f 8e 6c fd ff ff jle 403897 <_nl_load_domain+0x157> + 403b2b: 49 01 c1 add %rax,%r9 + 403b2e: 49 29 c0 sub %rax,%r8 + 403b31: eb ad jmp 403ae0 <_nl_load_domain+0x3a0> + 403b33: 3d ff ff 01 00 cmp $0x1ffff,%eax + 403b38: 0f 87 90 00 00 00 ja 403bce <_nl_load_domain+0x48e> + 403b3e: 41 8b 4f 08 mov 0x8(%r15),%ecx + 403b42: 48 8b b5 28 ff ff ff mov -0xd8(%rbp),%rsi + 403b49: 45 8b 57 14 mov 0x14(%r15),%r10d + 403b4d: 89 4e 28 mov %ecx,0x28(%rsi) + 403b50: 41 8b 4f 0c mov 0xc(%r15),%ecx + 403b54: 4c 01 f9 add %r15,%rcx + 403b57: 48 89 4e 30 mov %rcx,0x30(%rsi) + 403b5b: 41 8b 4f 10 mov 0x10(%r15),%ecx + 403b5f: 44 89 56 58 mov %r10d,0x58(%rsi) + 403b63: 4c 01 f9 add %r15,%rcx + 403b66: 41 83 fa 02 cmp $0x2,%r10d + 403b6a: 48 89 4e 38 mov %rcx,0x38(%rsi) + 403b6e: 76 09 jbe 403b79 <_nl_load_domain+0x439> + 403b70: 41 8b 4f 18 mov 0x18(%r15),%ecx + 403b74: e9 55 fe ff ff jmpq 4039ce <_nl_load_domain+0x28e> + 403b79: 66 85 c0 test %ax,%ax + 403b7c: 48 c7 46 60 00 00 00 movq $0x0,0x60(%rsi) + 403b83: 00 + 403b84: 89 56 68 mov %edx,0x68(%rsi) + 403b87: 0f 84 7a fe ff ff je 403a07 <_nl_load_domain+0x2c7> + 403b8d: 48 8b 7e 20 mov 0x20(%rsi),%rdi + 403b91: e8 1a a2 01 00 callq 41ddb0 <__cfree> + 403b96: 8b 85 1c ff ff ff mov -0xe4(%rbp),%eax + 403b9c: 85 c0 test %eax,%eax + 403b9e: 74 24 je 403bc4 <_nl_load_domain+0x484> + 403ba0: 4c 89 ee mov %r13,%rsi + 403ba3: 4c 89 ff mov %r15,%rdi + 403ba6: e8 05 c1 03 00 callq 43fcb0 <__munmap> + 403bab: 48 8b bd 28 ff ff ff mov -0xd8(%rbp),%rdi + 403bb2: e8 f9 a1 01 00 callq 41ddb0 <__cfree> + 403bb7: 48 c7 43 10 00 00 00 movq $0x0,0x10(%rbx) + 403bbe: 00 + 403bbf: e9 dd fc ff ff jmpq 4038a1 <_nl_load_domain+0x161> + 403bc4: 4c 89 ff mov %r15,%rdi + 403bc7: e8 e4 a1 01 00 callq 41ddb0 <__cfree> + 403bcc: eb dd jmp 403bab <_nl_load_domain+0x46b> + 403bce: 31 ff xor %edi,%edi + 403bd0: eb bf jmp 403b91 <_nl_load_domain+0x451> + 403bd2: b8 00 00 00 00 mov $0x0,%eax + 403bd7: 48 85 c0 test %rax,%rax + 403bda: 0f 84 e6 05 00 00 je 4041c6 <_nl_load_domain+0xa86> + 403be0: 4c 8b b5 28 ff ff ff mov -0xd8(%rbp),%r14 + 403be7: 49 8d be 80 00 00 00 lea 0x80(%r14),%rdi + 403bee: e8 0d c4 bf ff callq 0 <_nl_current_LC_CTYPE> + 403bf3: 49 8b 7e 20 mov 0x20(%r14),%rdi + 403bf7: eb 98 jmp 403b91 <_nl_load_domain+0x451> + 403bf9: 85 c0 test %eax,%eax + 403bfb: 89 85 e0 fe ff ff mov %eax,-0x120(%rbp) + 403c01: 0f 84 00 fe ff ff je 403a07 <_nl_load_domain+0x2c7> + 403c07: 41 8b 47 1c mov 0x1c(%r15),%eax + 403c0b: 41 8b 77 20 mov 0x20(%r15),%esi + 403c0f: 89 c1 mov %eax,%ecx + 403c11: 89 85 e8 fe ff ff mov %eax,-0x118(%rbp) + 403c17: 48 8d 04 c5 1e 00 00 lea 0x1e(,%rax,8),%rax + 403c1e: 00 + 403c1f: 4c 01 fe add %r15,%rsi + 403c22: 48 c1 e8 04 shr $0x4,%rax + 403c26: 48 c1 e0 04 shl $0x4,%rax + 403c2a: 48 29 c4 sub %rax,%rsp + 403c2d: 48 8d 44 24 0f lea 0xf(%rsp),%rax + 403c32: 48 83 e0 f0 and $0xfffffffffffffff0,%rax + 403c36: 85 c9 test %ecx,%ecx + 403c38: 48 89 85 00 ff ff ff mov %rax,-0x100(%rbp) + 403c3f: 0f 84 b3 05 00 00 je 4041f8 <_nl_load_domain+0xab8> + 403c45: 44 89 95 f8 fe ff ff mov %r10d,-0x108(%rbp) + 403c4c: 48 89 9d 08 ff ff ff mov %rbx,-0xf8(%rbp) + 403c53: 48 83 c6 04 add $0x4,%rsi + 403c57: 45 31 c0 xor %r8d,%r8d + 403c5a: 31 ff xor %edi,%edi + 403c5c: 41 bb cd 11 4a 00 mov $0x4a11cd,%r11d + 403c62: 49 bc 01 10 82 20 01 movabs $0x120821001,%r12 + 403c69: 00 00 00 + 403c6c: 44 8b 95 e8 fe ff ff mov -0x118(%rbp),%r10d + 403c73: 44 0f b6 8d 20 ff ff movzbl -0xe0(%rbp),%r9d + 403c7a: ff + 403c7b: 4c 89 ad 10 ff ff ff mov %r13,-0xf0(%rbp) + 403c82: 48 8b 9d 00 ff ff ff mov -0x100(%rbp),%rbx + 403c89: eb 57 jmp 403ce2 <_nl_load_domain+0x5a2> + 403c8b: 8b 16 mov (%rsi),%edx + 403c8d: 8b 46 fc mov -0x4(%rsi),%eax + 403c90: 0f ca bswap %edx + 403c92: 0f c8 bswap %eax + 403c94: 89 d2 mov %edx,%edx + 403c96: 4c 01 fa add %r15,%rdx + 403c99: 85 c0 test %eax,%eax + 403c9b: 0f 84 e3 00 00 00 je 403d84 <_nl_load_domain+0x644> + 403ca1: 83 e8 01 sub $0x1,%eax + 403ca4: 80 3c 02 00 cmpb $0x0,(%rdx,%rax,1) + 403ca8: 0f 85 d6 00 00 00 jne 403d84 <_nl_load_domain+0x644> + 403cae: 0f b6 02 movzbl (%rdx),%eax + 403cb1: 3c 50 cmp $0x50,%al + 403cb3: 74 3c je 403cf1 <_nl_load_domain+0x5b1> + 403cb5: 3c 49 cmp $0x49,%al + 403cb7: 0f 85 7f 08 00 00 jne 40453c <_nl_load_domain+0xdfc> + 403cbd: 80 7a 01 00 cmpb $0x0,0x1(%rdx) + 403cc1: b8 00 00 00 00 mov $0x0,%eax + 403cc6: 49 0f 44 c3 cmove %r11,%rax + 403cca: 83 c7 01 add $0x1,%edi + 403ccd: 4a 89 04 03 mov %rax,(%rbx,%r8,1) + 403cd1: 48 83 c6 08 add $0x8,%rsi + 403cd5: 49 83 c0 08 add $0x8,%r8 + 403cd9: 41 39 fa cmp %edi,%r10d + 403cdc: 0f 86 f4 04 00 00 jbe 4041d6 <_nl_load_domain+0xa96> + 403ce2: 45 84 c9 test %r9b,%r9b + 403ce5: 75 a4 jne 403c8b <_nl_load_domain+0x54b> + 403ce7: 8b 16 mov (%rsi),%edx + 403ce9: 8b 46 fc mov -0x4(%rsi),%eax + 403cec: 4c 01 fa add %r15,%rdx + 403cef: eb a8 jmp 403c99 <_nl_load_domain+0x559> + 403cf1: 31 c0 xor %eax,%eax + 403cf3: 80 7a 01 52 cmpb $0x52,0x1(%rdx) + 403cf7: 75 d1 jne 403cca <_nl_load_domain+0x58a> + 403cf9: 80 7a 02 49 cmpb $0x49,0x2(%rdx) + 403cfd: 75 cb jne 403cca <_nl_load_domain+0x58a> + 403cff: 0f b6 4a 03 movzbl 0x3(%rdx),%ecx + 403d03: 44 8d 69 a8 lea -0x58(%rcx),%r13d + 403d07: 41 80 fd 20 cmp $0x20,%r13b + 403d0b: 77 bd ja 403cca <_nl_load_domain+0x58a> + 403d0d: 4d 0f a3 ec bt %r13,%r12 + 403d11: 73 b7 jae 403cca <_nl_load_domain+0x58a> + 403d13: 44 0f b6 6a 04 movzbl 0x4(%rdx),%r13d + 403d18: 41 80 fd 38 cmp $0x38,%r13b + 403d1c: 0f 84 b1 05 00 00 je 4042d3 <_nl_load_domain+0xb93> + 403d22: 41 80 fd 31 cmp $0x31,%r13b + 403d26: 0f 84 53 05 00 00 je 40427f <_nl_load_domain+0xb3f> + 403d2c: 31 c0 xor %eax,%eax + 403d2e: 41 80 fd 33 cmp $0x33,%r13b + 403d32: 0f 85 11 09 00 00 jne 404649 <_nl_load_domain+0xf09> + 403d38: 80 7a 05 32 cmpb $0x32,0x5(%rdx) + 403d3c: 75 8c jne 403cca <_nl_load_domain+0x58a> + 403d3e: 80 7a 06 00 cmpb $0x0,0x6(%rdx) + 403d42: 75 86 jne 403cca <_nl_load_domain+0x58a> + 403d44: 80 f9 64 cmp $0x64,%cl + 403d47: 0f 84 f2 08 00 00 je 40463f <_nl_load_domain+0xeff> + 403d4d: 80 f9 69 cmp $0x69,%cl + 403d50: 0f 84 df 08 00 00 je 404635 <_nl_load_domain+0xef5> + 403d56: 80 f9 6f cmp $0x6f,%cl + 403d59: 0f 84 cc 08 00 00 je 40462b <_nl_load_domain+0xeeb> + 403d5f: 80 f9 75 cmp $0x75,%cl + 403d62: 0f 84 b9 08 00 00 je 404621 <_nl_load_domain+0xee1> + 403d68: 80 f9 78 cmp $0x78,%cl + 403d6b: 0f 84 a6 08 00 00 je 404617 <_nl_load_domain+0xed7> + 403d71: 80 f9 58 cmp $0x58,%cl + 403d74: 0f 85 bd 07 00 00 jne 404537 <_nl_load_domain+0xdf7> + 403d7a: b8 a5 5a 4b 00 mov $0x4b5aa5,%eax + 403d7f: e9 46 ff ff ff jmpq 403cca <_nl_load_domain+0x58a> + 403d84: 48 8b 85 28 ff ff ff mov -0xd8(%rbp),%rax + 403d8b: 4c 8b ad 10 ff ff ff mov -0xf0(%rbp),%r13 + 403d92: 48 8b 9d 08 ff ff ff mov -0xf8(%rbp),%rbx + 403d99: 48 8b 78 20 mov 0x20(%rax),%rdi + 403d9d: e9 ef fd ff ff jmpq 403b91 <_nl_load_domain+0x451> + 403da2: 41 8b 47 1c mov 0x1c(%r15),%eax + 403da6: 41 8b 77 20 mov 0x20(%r15),%esi + 403daa: 0f c8 bswap %eax + 403dac: 0f ce bswap %esi + 403dae: 89 c1 mov %eax,%ecx + 403db0: 89 85 e8 fe ff ff mov %eax,-0x118(%rbp) + 403db6: 89 c0 mov %eax,%eax + 403db8: 48 8d 04 c5 1e 00 00 lea 0x1e(,%rax,8),%rax + 403dbf: 00 + 403dc0: 89 f6 mov %esi,%esi + 403dc2: 4c 01 fe add %r15,%rsi + 403dc5: 48 c1 e8 04 shr $0x4,%rax + 403dc9: 48 c1 e0 04 shl $0x4,%rax + 403dcd: 48 29 c4 sub %rax,%rsp + 403dd0: 48 8d 44 24 0f lea 0xf(%rsp),%rax + 403dd5: 48 83 e0 f0 and $0xfffffffffffffff0,%rax + 403dd9: 85 c9 test %ecx,%ecx + 403ddb: 48 89 85 00 ff ff ff mov %rax,-0x100(%rbp) + 403de2: 0f 85 5d fe ff ff jne 403c45 <_nl_load_domain+0x505> + 403de8: 41 8b 47 28 mov 0x28(%r15),%eax + 403dec: 0f c8 bswap %eax + 403dee: 89 c0 mov %eax,%eax + 403df0: 4c 01 f8 add %r15,%rax + 403df3: 48 89 85 f0 fe ff ff mov %rax,-0x110(%rbp) + 403dfa: 41 8b 47 2c mov 0x2c(%r15),%eax + 403dfe: 0f c8 bswap %eax + 403e00: 89 c0 mov %eax,%eax + 403e02: 4c 01 f8 add %r15,%rax + 403e05: 45 89 d2 mov %r10d,%r10d + 403e08: 4c 89 b5 b0 fe ff ff mov %r14,-0x150(%rbp) + 403e0f: 48 89 85 d8 fe ff ff mov %rax,-0x128(%rbp) + 403e16: 4c 8b a5 00 ff ff ff mov -0x100(%rbp),%r12 + 403e1d: 4a 8d 04 95 00 00 00 lea 0x0(,%r10,4),%rax + 403e24: 00 + 403e25: 44 8b b5 e8 fe ff ff mov -0x118(%rbp),%r14d + 403e2c: 48 c7 85 08 ff ff ff movq $0x0,-0xf8(%rbp) + 403e33: 00 00 00 00 + 403e37: 48 89 85 b8 fe ff ff mov %rax,-0x148(%rbp) + 403e3e: 48 89 85 c0 fe ff ff mov %rax,-0x140(%rbp) + 403e45: c7 85 10 ff ff ff 00 movl $0x0,-0xf0(%rbp) + 403e4c: 00 00 00 + 403e4f: 4c 89 ad d0 fe ff ff mov %r13,-0x130(%rbp) + 403e56: 4c 89 bd f8 fe ff ff mov %r15,-0x108(%rbp) + 403e5d: 48 89 9d c8 fe ff ff mov %rbx,-0x138(%rbp) + 403e64: 45 31 ed xor %r13d,%r13d + 403e67: 80 bd 20 ff ff ff 00 cmpb $0x0,-0xe0(%rbp) + 403e6e: 0f 84 ce 02 00 00 je 404142 <_nl_load_domain+0xa02> + 403e74: 4d 85 ed test %r13,%r13 + 403e77: 0f 84 5f 07 00 00 je 4045dc <_nl_load_domain+0xe9c> + 403e7d: 48 8b 85 d8 fe ff ff mov -0x128(%rbp),%rax + 403e84: 48 8b 8d 08 ff ff ff mov -0xf8(%rbp),%rcx + 403e8b: 8b 04 88 mov (%rax,%rcx,4),%eax + 403e8e: 0f c8 bswap %eax + 403e90: 89 c2 mov %eax,%edx + 403e92: 48 03 95 f8 fe ff ff add -0x108(%rbp),%rdx + 403e99: 83 7a 08 ff cmpl $0xffffffff,0x8(%rdx) + 403e9d: 0f 84 07 03 00 00 je 4041aa <_nl_load_domain+0xa6a> + 403ea3: 4c 8d 7a 04 lea 0x4(%rdx),%r15 + 403ea7: 31 db xor %ebx,%ebx + 403ea9: eb 25 jmp 403ed0 <_nl_load_domain+0x790> + 403eab: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 403eb0: 44 39 f0 cmp %r14d,%eax + 403eb3: 0f 83 f8 02 00 00 jae 4041b1 <_nl_load_domain+0xa71> + 403eb9: 89 c0 mov %eax,%eax + 403ebb: 49 8b 3c c4 mov (%r12,%rax,8),%rdi + 403ebf: 48 85 ff test %rdi,%rdi + 403ec2: 74 53 je 403f17 <_nl_load_domain+0x7d7> + 403ec4: e8 87 f7 01 00 callq 423650 + 403ec9: 49 83 c7 08 add $0x8,%r15 + 403ecd: 48 01 c3 add %rax,%rbx + 403ed0: 41 8b 07 mov (%r15),%eax + 403ed3: 0f c8 bswap %eax + 403ed5: 89 c0 mov %eax,%eax + 403ed7: 48 01 c3 add %rax,%rbx + 403eda: 41 8b 47 04 mov 0x4(%r15),%eax + 403ede: 0f c8 bswap %eax + 403ee0: 83 f8 ff cmp $0xffffffff,%eax + 403ee3: 75 cb jne 403eb0 <_nl_load_domain+0x770> + 403ee5: 4a 89 9c ed 30 ff ff mov %rbx,-0xd0(%rbp,%r13,8) + 403eec: ff + 403eed: 49 83 c5 01 add $0x1,%r13 + 403ef1: 49 83 fd 02 cmp $0x2,%r13 + 403ef5: 0f 85 6c ff ff ff jne 403e67 <_nl_load_domain+0x727> + 403efb: 48 8b 85 38 ff ff ff mov -0xc8(%rbp),%rax + 403f02: 48 03 85 30 ff ff ff add -0xd0(%rbp),%rax + 403f09: 83 85 10 ff ff ff 01 addl $0x1,-0xf0(%rbp) + 403f10: 48 01 85 c0 fe ff ff add %rax,-0x140(%rbp) + 403f17: 48 83 85 08 ff ff ff addq $0x1,-0xf8(%rbp) + 403f1e: 01 + 403f1f: 48 8b 85 08 ff ff ff mov -0xf8(%rbp),%rax + 403f26: 39 85 e0 fe ff ff cmp %eax,-0x120(%rbp) + 403f2c: 0f 87 32 ff ff ff ja 403e64 <_nl_load_domain+0x724> + 403f32: 83 bd 10 ff ff ff 00 cmpl $0x0,-0xf0(%rbp) + 403f39: 4c 8b ad d0 fe ff ff mov -0x130(%rbp),%r13 + 403f40: 4c 8b bd f8 fe ff ff mov -0x108(%rbp),%r15 + 403f47: 48 8b 9d c8 fe ff ff mov -0x138(%rbp),%rbx + 403f4e: 4c 8b b5 b0 fe ff ff mov -0x150(%rbp),%r14 + 403f55: 0f 84 ac fa ff ff je 403a07 <_nl_load_domain+0x2c7> + 403f5b: 8b 85 10 ff ff ff mov -0xf0(%rbp),%eax + 403f61: 8d 3c 00 lea (%rax,%rax,1),%edi + 403f64: 48 c1 e7 04 shl $0x4,%rdi + 403f68: 48 03 bd c0 fe ff ff add -0x140(%rbp),%rdi + 403f6f: e8 9c 9a 01 00 callq 41da10 <__libc_malloc> + 403f74: 48 85 c0 test %rax,%rax + 403f77: 48 89 85 20 ff ff ff mov %rax,-0xe0(%rbp) + 403f7e: 0f 84 42 02 00 00 je 4041c6 <_nl_load_domain+0xa86> + 403f84: 8b 85 10 ff ff ff mov -0xf0(%rbp),%eax + 403f8a: 48 8b 8d 20 ff ff ff mov -0xe0(%rbp),%rcx + 403f91: 48 8b 95 28 ff ff ff mov -0xd8(%rbp),%rdx + 403f98: 4c 8b 8d b8 fe ff ff mov -0x148(%rbp),%r9 + 403f9f: 4c 8b 95 f0 fe ff ff mov -0x110(%rbp),%r10 + 403fa6: c7 85 f8 fe ff ff 00 movl $0x0,-0x108(%rbp) + 403fad: 00 00 00 + 403fb0: 4c 89 ad c8 fe ff ff mov %r13,-0x138(%rbp) + 403fb7: 48 89 9d c0 fe ff ff mov %rbx,-0x140(%rbp) + 403fbe: 48 c1 e0 04 shl $0x4,%rax + 403fc2: 48 89 4a 20 mov %rcx,0x20(%rdx) + 403fc6: 4c 89 b5 b8 fe ff ff mov %r14,-0x148(%rbp) + 403fcd: 48 01 c1 add %rax,%rcx + 403fd0: 48 01 c8 add %rcx,%rax + 403fd3: 48 89 8d d0 fe ff ff mov %rcx,-0x130(%rbp) + 403fda: 48 89 85 e8 fe ff ff mov %rax,-0x118(%rbp) + 403fe1: 49 01 c1 add %rax,%r9 + 403fe4: 48 8b 85 d8 fe ff ff mov -0x128(%rbp),%rax + 403feb: 48 89 85 08 ff ff ff mov %rax,-0xf8(%rbp) + 403ff2: 8b 85 e0 fe ff ff mov -0x120(%rbp),%eax + 403ff8: 49 8d 04 82 lea (%r10,%rax,4),%rax + 403ffc: 48 89 85 d8 fe ff ff mov %rax,-0x128(%rbp) + 404003: 4c 3b 95 d8 fe ff ff cmp -0x128(%rbp),%r10 + 40400a: 0f 84 b7 03 00 00 je 4043c7 <_nl_load_domain+0xc87> + 404010: 48 8b 85 28 ff ff ff mov -0xd8(%rbp),%rax + 404017: 48 8b 8d 00 ff ff ff mov -0x100(%rbp),%rcx + 40401e: 31 d2 xor %edx,%edx + 404020: 48 8b b5 08 ff ff ff mov -0xf8(%rbp),%rsi + 404027: 44 8b 58 18 mov 0x18(%rax),%r11d + 40402b: 45 85 db test %r11d,%r11d + 40402e: 0f 84 5a 03 00 00 je 40438e <_nl_load_domain+0xc4e> + 404034: 85 d2 test %edx,%edx + 404036: 0f 84 db 04 00 00 je 404517 <_nl_load_domain+0xdd7> + 40403c: 8b 06 mov (%rsi),%eax + 40403e: 0f c8 bswap %eax + 404040: 89 c0 mov %eax,%eax + 404042: 4c 01 f8 add %r15,%rax + 404045: 83 78 08 ff cmpl $0xffffffff,0x8(%rax) + 404049: 0f 85 19 03 00 00 jne 404368 <_nl_load_domain+0xc28> + 40404f: 83 c2 01 add $0x1,%edx + 404052: 83 fa 02 cmp $0x2,%edx + 404055: 75 d4 jne 40402b <_nl_load_domain+0x8eb> + 404057: 8b 85 f8 fe ff ff mov -0x108(%rbp),%eax + 40405d: 48 8b 8d 20 ff ff ff mov -0xe0(%rbp),%rcx + 404064: 45 31 c0 xor %r8d,%r8d + 404067: 48 c1 e0 04 shl $0x4,%rax + 40406b: 48 01 c1 add %rax,%rcx + 40406e: 48 03 85 d0 fe ff ff add -0x130(%rbp),%rax + 404075: 48 89 8d e0 fe ff ff mov %rcx,-0x120(%rbp) + 40407c: 48 89 85 f0 fe ff ff mov %rax,-0x110(%rbp) + 404083: 45 85 db test %r11d,%r11d + 404086: 0f 84 a1 02 00 00 je 40432d <_nl_load_domain+0xbed> + 40408c: 45 85 c0 test %r8d,%r8d + 40408f: 0f 84 19 05 00 00 je 4045ae <_nl_load_domain+0xe6e> + 404095: 48 8b 85 08 ff ff ff mov -0xf8(%rbp),%rax + 40409c: 4c 8b b5 f0 fe ff ff mov -0x110(%rbp),%r14 + 4040a3: 8b 18 mov (%rax),%ebx + 4040a5: 0f cb bswap %ebx + 4040a7: 89 db mov %ebx,%ebx + 4040a9: 4c 01 fb add %r15,%rbx + 4040ac: 44 8b 23 mov (%rbx),%r12d + 4040af: 41 0f cc bswap %r12d + 4040b2: 45 89 e4 mov %r12d,%r12d + 4040b5: 4d 01 fc add %r15,%r12 + 4040b8: 83 7b 08 ff cmpl $0xffffffff,0x8(%rbx) + 4040bc: 0f 84 0e 05 00 00 je 4045d0 <_nl_load_domain+0xe90> + 4040c2: 4d 89 4e 08 mov %r9,0x8(%r14) + 4040c6: 4c 89 b5 b0 fe ff ff mov %r14,-0x150(%rbp) + 4040cd: 48 83 c3 04 add $0x4,%rbx + 4040d1: 44 89 85 18 ff ff ff mov %r8d,-0xe8(%rbp) + 4040d8: 4c 89 95 a8 fe ff ff mov %r10,-0x158(%rbp) + 4040df: 45 89 de mov %r11d,%r14d + 4040e2: eb 51 jmp 404135 <_nl_load_domain+0x9f5> + 4040e4: 8b 4b 04 mov 0x4(%rbx),%ecx + 4040e7: 41 0f cd bswap %r13d + 4040ea: 0f c9 bswap %ecx + 4040ec: 45 85 ed test %r13d,%r13d + 4040ef: 0f 85 1a 01 00 00 jne 40420f <_nl_load_domain+0xacf> + 4040f5: 83 f9 ff cmp $0xffffffff,%ecx + 4040f8: 0f 84 3c 01 00 00 je 40423a <_nl_load_domain+0xafa> + 4040fe: 48 8b 85 00 ff ff ff mov -0x100(%rbp),%rax + 404105: 89 c9 mov %ecx,%ecx + 404107: 48 83 c3 08 add $0x8,%rbx + 40410b: 48 8b 34 c8 mov (%rax,%rcx,8),%rsi + 40410f: 31 c0 xor %eax,%eax + 404111: 48 83 c9 ff or $0xffffffffffffffff,%rcx + 404115: 48 89 f7 mov %rsi,%rdi + 404118: f2 ae repnz scas %es:(%rdi),%al + 40411a: 4c 89 cf mov %r9,%rdi + 40411d: 48 89 c8 mov %rcx,%rax + 404120: 48 f7 d0 not %rax + 404123: 4c 8d 68 ff lea -0x1(%rax),%r13 + 404127: 4c 89 ea mov %r13,%rdx + 40412a: e8 f1 7e 02 00 callq 42c020 + 40412f: 49 89 c1 mov %rax,%r9 + 404132: 4d 01 e9 add %r13,%r9 + 404135: 45 85 f6 test %r14d,%r14d + 404138: 44 8b 2b mov (%rbx),%r13d + 40413b: 75 a7 jne 4040e4 <_nl_load_domain+0x9a4> + 40413d: 8b 4b 04 mov 0x4(%rbx),%ecx + 404140: eb aa jmp 4040ec <_nl_load_domain+0x9ac> + 404142: 4d 85 ed test %r13,%r13 + 404145: 0f 84 b6 04 00 00 je 404601 <_nl_load_domain+0xec1> + 40414b: 48 8b 85 d8 fe ff ff mov -0x128(%rbp),%rax + 404152: 48 8b 8d 08 ff ff ff mov -0xf8(%rbp),%rcx + 404159: 8b 14 88 mov (%rax,%rcx,4),%edx + 40415c: 48 03 95 f8 fe ff ff add -0x108(%rbp),%rdx + 404163: 83 7a 08 ff cmpl $0xffffffff,0x8(%rdx) + 404167: 74 41 je 4041aa <_nl_load_domain+0xa6a> + 404169: 4c 8d 7a 04 lea 0x4(%rdx),%r15 + 40416d: 31 db xor %ebx,%ebx + 40416f: eb 25 jmp 404196 <_nl_load_domain+0xa56> + 404171: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 404178: 41 39 c6 cmp %eax,%r14d + 40417b: 76 34 jbe 4041b1 <_nl_load_domain+0xa71> + 40417d: 49 8b 3c c4 mov (%r12,%rax,8),%rdi + 404181: 48 85 ff test %rdi,%rdi + 404184: 0f 84 8d fd ff ff je 403f17 <_nl_load_domain+0x7d7> + 40418a: e8 c1 f4 01 00 callq 423650 + 40418f: 49 83 c7 08 add $0x8,%r15 + 404193: 48 01 c3 add %rax,%rbx + 404196: 41 8b 07 mov (%r15),%eax + 404199: 48 01 c3 add %rax,%rbx + 40419c: 41 8b 47 04 mov 0x4(%r15),%eax + 4041a0: 83 f8 ff cmp $0xffffffff,%eax + 4041a3: 75 d3 jne 404178 <_nl_load_domain+0xa38> + 4041a5: e9 3b fd ff ff jmpq 403ee5 <_nl_load_domain+0x7a5> + 4041aa: 31 db xor %ebx,%ebx + 4041ac: e9 34 fd ff ff jmpq 403ee5 <_nl_load_domain+0x7a5> + 4041b1: 4c 8b ad d0 fe ff ff mov -0x130(%rbp),%r13 + 4041b8: 4c 8b bd f8 fe ff ff mov -0x108(%rbp),%r15 + 4041bf: 48 8b 9d c8 fe ff ff mov -0x138(%rbp),%rbx + 4041c6: 48 8b 85 28 ff ff ff mov -0xd8(%rbp),%rax + 4041cd: 48 8b 78 20 mov 0x20(%rax),%rdi + 4041d1: e9 bb f9 ff ff jmpq 403b91 <_nl_load_domain+0x451> + 4041d6: 80 bd 20 ff ff ff 00 cmpb $0x0,-0xe0(%rbp) + 4041dd: 44 8b 95 f8 fe ff ff mov -0x108(%rbp),%r10d + 4041e4: 4c 8b ad 10 ff ff ff mov -0xf0(%rbp),%r13 + 4041eb: 48 8b 9d 08 ff ff ff mov -0xf8(%rbp),%rbx + 4041f2: 0f 85 f0 fb ff ff jne 403de8 <_nl_load_domain+0x6a8> + 4041f8: 41 8b 47 28 mov 0x28(%r15),%eax + 4041fc: 4c 01 f8 add %r15,%rax + 4041ff: 48 89 85 f0 fe ff ff mov %rax,-0x110(%rbp) + 404206: 41 8b 47 2c mov 0x2c(%r15),%eax + 40420a: e9 f3 fb ff ff jmpq 403e02 <_nl_load_domain+0x6c2> + 40420f: 45 89 ed mov %r13d,%r13d + 404212: 4c 89 e6 mov %r12,%rsi + 404215: 4c 89 cf mov %r9,%rdi + 404218: 4c 89 ea mov %r13,%rdx + 40421b: 89 8d a4 fe ff ff mov %ecx,-0x15c(%rbp) + 404221: 4d 01 ec add %r13,%r12 + 404224: e8 f7 7d 02 00 callq 42c020 + 404229: 49 89 c1 mov %rax,%r9 + 40422c: 8b 8d a4 fe ff ff mov -0x15c(%rbp),%ecx + 404232: 4d 01 e9 add %r13,%r9 + 404235: e9 bb fe ff ff jmpq 4040f5 <_nl_load_domain+0x9b5> + 40423a: 4c 8b b5 b0 fe ff ff mov -0x150(%rbp),%r14 + 404241: 4c 89 c8 mov %r9,%rax + 404244: 44 8b 85 18 ff ff ff mov -0xe8(%rbp),%r8d + 40424b: 4c 8b 95 a8 fe ff ff mov -0x158(%rbp),%r10 + 404252: 49 2b 46 08 sub 0x8(%r14),%rax + 404256: 49 89 06 mov %rax,(%r14) + 404259: 41 83 c0 01 add $0x1,%r8d + 40425d: 41 83 f8 02 cmp $0x2,%r8d + 404261: 0f 85 b6 00 00 00 jne 40431d <_nl_load_domain+0xbdd> + 404267: 83 85 f8 fe ff ff 01 addl $0x1,-0x108(%rbp) + 40426e: 49 83 c2 04 add $0x4,%r10 + 404272: 48 83 85 08 ff ff ff addq $0x4,-0xf8(%rbp) + 404279: 04 + 40427a: e9 84 fd ff ff jmpq 404003 <_nl_load_domain+0x8c3> + 40427f: 80 7a 05 36 cmpb $0x36,0x5(%rdx) + 404283: 0f 85 41 fa ff ff jne 403cca <_nl_load_domain+0x58a> + 404289: 80 7a 06 00 cmpb $0x0,0x6(%rdx) + 40428d: 0f 85 e2 02 00 00 jne 404575 <_nl_load_domain+0xe35> + 404293: 80 f9 64 cmp $0x64,%cl + 404296: 0f 84 cf 02 00 00 je 40456b <_nl_load_domain+0xe2b> + 40429c: 80 f9 69 cmp $0x69,%cl + 40429f: 0f 84 bc 02 00 00 je 404561 <_nl_load_domain+0xe21> + 4042a5: 80 f9 6f cmp $0x6f,%cl + 4042a8: 0f 84 a9 02 00 00 je 404557 <_nl_load_domain+0xe17> + 4042ae: 80 f9 75 cmp $0x75,%cl + 4042b1: 0f 84 96 02 00 00 je 40454d <_nl_load_domain+0xe0d> + 4042b7: 80 f9 78 cmp $0x78,%cl + 4042ba: 0f 84 83 02 00 00 je 404543 <_nl_load_domain+0xe03> + 4042c0: 80 f9 58 cmp $0x58,%cl + 4042c3: 0f 85 6e 02 00 00 jne 404537 <_nl_load_domain+0xdf7> + 4042c9: b8 a5 5a 4b 00 mov $0x4b5aa5,%eax + 4042ce: e9 f7 f9 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 4042d3: 80 7a 05 00 cmpb $0x0,0x5(%rdx) + 4042d7: 0f 85 ed f9 ff ff jne 403cca <_nl_load_domain+0x58a> + 4042dd: 80 f9 64 cmp $0x64,%cl + 4042e0: 0f 84 b4 02 00 00 je 40459a <_nl_load_domain+0xe5a> + 4042e6: 80 f9 69 cmp $0x69,%cl + 4042e9: 0f 84 a1 02 00 00 je 404590 <_nl_load_domain+0xe50> + 4042ef: 80 f9 6f cmp $0x6f,%cl + 4042f2: 0f 84 8e 02 00 00 je 404586 <_nl_load_domain+0xe46> + 4042f8: 80 f9 75 cmp $0x75,%cl + 4042fb: 0f 84 7b 02 00 00 je 40457c <_nl_load_domain+0xe3c> + 404301: 80 f9 78 cmp $0x78,%cl + 404304: 0f 84 9a 02 00 00 je 4045a4 <_nl_load_domain+0xe64> + 40430a: 80 f9 58 cmp $0x58,%cl + 40430d: 0f 85 24 02 00 00 jne 404537 <_nl_load_domain+0xdf7> + 404313: b8 a5 5a 4b 00 mov $0x4b5aa5,%eax + 404318: e9 ad f9 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 40431d: 48 8b 85 28 ff ff ff mov -0xd8(%rbp),%rax + 404324: 44 8b 58 18 mov 0x18(%rax),%r11d + 404328: e9 56 fd ff ff jmpq 404083 <_nl_load_domain+0x943> + 40432d: 45 85 c0 test %r8d,%r8d + 404330: 0f 84 e9 01 00 00 je 40451f <_nl_load_domain+0xddf> + 404336: 48 8b 85 08 ff ff ff mov -0xf8(%rbp),%rax + 40433d: 4c 8b b5 f0 fe ff ff mov -0x110(%rbp),%r14 + 404344: 8b 18 mov (%rax),%ebx + 404346: 4c 01 fb add %r15,%rbx + 404349: 44 8b 23 mov (%rbx),%r12d + 40434c: 4d 01 fc add %r15,%r12 + 40434f: 83 7b 08 ff cmpl $0xffffffff,0x8(%rbx) + 404353: 0f 85 69 fd ff ff jne 4040c2 <_nl_load_domain+0x982> + 404359: 8b 43 04 mov 0x4(%rbx),%eax + 40435c: 49 89 06 mov %rax,(%r14) + 40435f: 4d 89 66 08 mov %r12,0x8(%r14) + 404363: e9 f1 fe ff ff jmpq 404259 <_nl_load_domain+0xb19> + 404368: 48 83 c0 04 add $0x4,%rax + 40436c: eb 11 jmp 40437f <_nl_load_domain+0xc3f> + 40436e: 89 ff mov %edi,%edi + 404370: 48 83 3c f9 00 cmpq $0x0,(%rcx,%rdi,8) + 404375: 0f 84 f3 fe ff ff je 40426e <_nl_load_domain+0xb2e> + 40437b: 48 83 c0 08 add $0x8,%rax + 40437f: 8b 78 04 mov 0x4(%rax),%edi + 404382: 0f cf bswap %edi + 404384: 83 ff ff cmp $0xffffffff,%edi + 404387: 75 e5 jne 40436e <_nl_load_domain+0xc2e> + 404389: e9 c1 fc ff ff jmpq 40404f <_nl_load_domain+0x90f> + 40438e: 85 d2 test %edx,%edx + 404390: 0f 84 79 01 00 00 je 40450f <_nl_load_domain+0xdcf> + 404396: 8b 06 mov (%rsi),%eax + 404398: 4c 01 f8 add %r15,%rax + 40439b: 83 78 08 ff cmpl $0xffffffff,0x8(%rax) + 40439f: 0f 84 aa fc ff ff je 40404f <_nl_load_domain+0x90f> + 4043a5: 48 83 c0 04 add $0x4,%rax + 4043a9: eb 0f jmp 4043ba <_nl_load_domain+0xc7a> + 4043ab: 48 83 3c f9 00 cmpq $0x0,(%rcx,%rdi,8) + 4043b0: 0f 84 b8 fe ff ff je 40426e <_nl_load_domain+0xb2e> + 4043b6: 48 83 c0 08 add $0x8,%rax + 4043ba: 8b 78 04 mov 0x4(%rax),%edi + 4043bd: 83 ff ff cmp $0xffffffff,%edi + 4043c0: 75 e9 jne 4043ab <_nl_load_domain+0xc6b> + 4043c2: e9 88 fc ff ff jmpq 40404f <_nl_load_domain+0x90f> + 4043c7: 8b 8d f8 fe ff ff mov -0x108(%rbp),%ecx + 4043cd: 39 8d 10 ff ff ff cmp %ecx,-0xf0(%rbp) + 4043d3: 4c 8b ad c8 fe ff ff mov -0x138(%rbp),%r13 + 4043da: 48 8b 9d c0 fe ff ff mov -0x140(%rbp),%rbx + 4043e1: 4c 8b b5 b8 fe ff ff mov -0x148(%rbp),%r14 + 4043e8: 0f 85 49 01 00 00 jne 404537 <_nl_load_domain+0xdf7> + 4043ee: 48 8b b5 28 ff ff ff mov -0xd8(%rbp),%rsi + 4043f5: 31 c0 xor %eax,%eax + 4043f7: 8b 4e 58 mov 0x58(%rsi),%ecx + 4043fa: eb 1d jmp 404419 <_nl_load_domain+0xcd9> + 4043fc: 83 7e 68 00 cmpl $0x0,0x68(%rsi) + 404400: 48 8b 56 60 mov 0x60(%rsi),%rdx + 404404: 8b 14 82 mov (%rdx,%rax,4),%edx + 404407: 74 02 je 40440b <_nl_load_domain+0xccb> + 404409: 0f ca bswap %edx + 40440b: 48 8b bd e8 fe ff ff mov -0x118(%rbp),%rdi + 404412: 89 14 87 mov %edx,(%rdi,%rax,4) + 404415: 48 83 c0 01 add $0x1,%rax + 404419: 39 c1 cmp %eax,%ecx + 40441b: 77 df ja 4043fc <_nl_load_domain+0xcbc> + 40441d: 49 89 d8 mov %rbx,%r8 + 404420: 48 8b 9d 28 ff ff ff mov -0xd8(%rbp),%rbx + 404427: 45 31 c9 xor %r9d,%r9d + 40442a: 4d 89 cc mov %r9,%r12 + 40442d: 4d 89 f1 mov %r14,%r9 + 404430: 4d 89 ee mov %r13,%r14 + 404433: 48 8b 8d 20 ff ff ff mov -0xe0(%rbp),%rcx + 40443a: 4c 89 e0 mov %r12,%rax + 40443d: 4c 89 8d 00 ff ff ff mov %r9,-0x100(%rbp) + 404444: 48 c1 e0 04 shl $0x4,%rax + 404448: 4c 89 85 08 ff ff ff mov %r8,-0xf8(%rbp) + 40444f: 45 89 e5 mov %r12d,%r13d + 404452: 48 8b 7c 01 08 mov 0x8(%rcx,%rax,1),%rdi + 404457: e8 d4 96 00 00 callq 40db30 <__hash_string> + 40445c: 8b 7b 58 mov 0x58(%rbx),%edi + 40445f: 31 d2 xor %edx,%edx + 404461: 89 c1 mov %eax,%ecx + 404463: 4c 8b 85 08 ff ff ff mov -0xf8(%rbp),%r8 + 40446a: 4c 8b 8d 00 ff ff ff mov -0x100(%rbp),%r9 + 404471: f7 f7 div %edi + 404473: 44 8d 57 fe lea -0x2(%rdi),%r10d + 404477: 89 c8 mov %ecx,%eax + 404479: 89 d6 mov %edx,%esi + 40447b: 31 d2 xor %edx,%edx + 40447d: 41 f7 f2 div %r10d + 404480: 41 89 fa mov %edi,%r10d + 404483: 8d 42 01 lea 0x1(%rdx),%eax + 404486: 89 c1 mov %eax,%ecx + 404488: 41 29 c2 sub %eax,%r10d + 40448b: 29 f9 sub %edi,%ecx + 40448d: eb 0e jmp 40449d <_nl_load_domain+0xd5d> + 40448f: 8d 14 0e lea (%rsi,%rcx,1),%edx + 404492: 8d 3c 06 lea (%rsi,%rax,1),%edi + 404495: 44 39 d6 cmp %r10d,%esi + 404498: 0f 42 d7 cmovb %edi,%edx + 40449b: 89 d6 mov %edx,%esi + 40449d: 48 8b bd e8 fe ff ff mov -0x118(%rbp),%rdi + 4044a4: 89 f2 mov %esi,%edx + 4044a6: 48 8d 14 97 lea (%rdi,%rdx,4),%rdx + 4044aa: 44 8b 1a mov (%rdx),%r11d + 4044ad: 45 85 db test %r11d,%r11d + 4044b0: 75 dd jne 40448f <_nl_load_domain+0xd4f> + 4044b2: 8b 43 28 mov 0x28(%rbx),%eax + 4044b5: 49 83 c4 01 add $0x1,%r12 + 4044b9: 44 39 a5 10 ff ff ff cmp %r12d,-0xf0(%rbp) + 4044c0: 41 8d 44 05 01 lea 0x1(%r13,%rax,1),%eax + 4044c5: 89 02 mov %eax,(%rdx) + 4044c7: 0f 87 66 ff ff ff ja 404433 <_nl_load_domain+0xcf3> + 4044cd: 48 8b 85 28 ff ff ff mov -0xd8(%rbp),%rax + 4044d4: 8b 8d 10 ff ff ff mov -0xf0(%rbp),%ecx + 4044da: 4d 89 f5 mov %r14,%r13 + 4044dd: 4c 89 c3 mov %r8,%rbx + 4044e0: 4d 89 ce mov %r9,%r14 + 4044e3: 89 48 40 mov %ecx,0x40(%rax) + 4044e6: 48 8b 8d 20 ff ff ff mov -0xe0(%rbp),%rcx + 4044ed: 48 89 78 60 mov %rdi,0x60(%rax) + 4044f1: c7 40 68 00 00 00 00 movl $0x0,0x68(%rax) + 4044f8: 48 89 48 48 mov %rcx,0x48(%rax) + 4044fc: 48 8b 8d d0 fe ff ff mov -0x130(%rbp),%rcx + 404503: 48 89 48 50 mov %rcx,0x50(%rax) + 404507: 48 89 c1 mov %rax,%rcx + 40450a: e9 19 f5 ff ff jmpq 403a28 <_nl_load_domain+0x2e8> + 40450f: 41 8b 02 mov (%r10),%eax + 404512: e9 81 fe ff ff jmpq 404398 <_nl_load_domain+0xc58> + 404517: 41 8b 02 mov (%r10),%eax + 40451a: e9 1f fb ff ff jmpq 40403e <_nl_load_domain+0x8fe> + 40451f: 41 8b 1a mov (%r10),%ebx + 404522: 4c 8b b5 e0 fe ff ff mov -0x120(%rbp),%r14 + 404529: 4c 01 fb add %r15,%rbx + 40452c: 44 8b 23 mov (%rbx),%r12d + 40452f: 4d 01 fc add %r15,%r12 + 404532: e9 18 fe ff ff jmpq 40434f <_nl_load_domain+0xc0f> + 404537: e8 c4 96 00 00 callq 40dc00 + 40453c: 31 c0 xor %eax,%eax + 40453e: e9 87 f7 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404543: b8 5a 4a 4a 00 mov $0x4a4a5a,%eax + 404548: e9 7d f7 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 40454d: b8 22 66 4b 00 mov $0x4b6622,%eax + 404552: e9 73 f7 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404557: b8 34 4a 4a 00 mov $0x4a4a34,%eax + 40455c: e9 69 f7 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404561: b8 b7 52 4a 00 mov $0x4a52b7,%eax + 404566: e9 5f f7 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 40456b: b8 43 d4 4b 00 mov $0x4bd443,%eax + 404570: e9 55 f7 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404575: 31 c0 xor %eax,%eax + 404577: e9 4e f7 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 40457c: b8 22 66 4b 00 mov $0x4b6622,%eax + 404581: e9 44 f7 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404586: b8 34 4a 4a 00 mov $0x4a4a34,%eax + 40458b: e9 3a f7 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404590: b8 b7 52 4a 00 mov $0x4a52b7,%eax + 404595: e9 30 f7 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 40459a: b8 43 d4 4b 00 mov $0x4bd443,%eax + 40459f: e9 26 f7 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 4045a4: b8 5a 4a 4a 00 mov $0x4a4a5a,%eax + 4045a9: e9 1c f7 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 4045ae: 41 8b 1a mov (%r10),%ebx + 4045b1: 4c 8b b5 e0 fe ff ff mov -0x120(%rbp),%r14 + 4045b8: 0f cb bswap %ebx + 4045ba: 89 db mov %ebx,%ebx + 4045bc: 4c 01 fb add %r15,%rbx + 4045bf: 44 8b 23 mov (%rbx),%r12d + 4045c2: 41 0f cc bswap %r12d + 4045c5: 45 89 e4 mov %r12d,%r12d + 4045c8: 4d 01 fc add %r15,%r12 + 4045cb: e9 e8 fa ff ff jmpq 4040b8 <_nl_load_domain+0x978> + 4045d0: 8b 43 04 mov 0x4(%rbx),%eax + 4045d3: 0f c8 bswap %eax + 4045d5: 89 c0 mov %eax,%eax + 4045d7: e9 80 fd ff ff jmpq 40435c <_nl_load_domain+0xc1c> + 4045dc: 48 8b 85 f0 fe ff ff mov -0x110(%rbp),%rax + 4045e3: 48 8b 8d 08 ff ff ff mov -0xf8(%rbp),%rcx + 4045ea: 8b 04 88 mov (%rax,%rcx,4),%eax + 4045ed: e9 9c f8 ff ff jmpq 403e8e <_nl_load_domain+0x74e> + 4045f2: c7 85 1c ff ff ff 00 movl $0x0,-0xe4(%rbp) + 4045f9: 00 00 00 + 4045fc: e9 29 f3 ff ff jmpq 40392a <_nl_load_domain+0x1ea> + 404601: 48 8b 85 f0 fe ff ff mov -0x110(%rbp),%rax + 404608: 48 8b 8d 08 ff ff ff mov -0xf8(%rbp),%rcx + 40460f: 8b 14 88 mov (%rax,%rcx,4),%edx + 404612: e9 45 fb ff ff jmpq 40415c <_nl_load_domain+0xa1c> + 404617: b8 5a 4a 4a 00 mov $0x4a4a5a,%eax + 40461c: e9 a9 f6 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404621: b8 22 66 4b 00 mov $0x4b6622,%eax + 404626: e9 9f f6 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 40462b: b8 34 4a 4a 00 mov $0x4a4a34,%eax + 404630: e9 95 f6 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404635: b8 b7 52 4a 00 mov $0x4a52b7,%eax + 40463a: e9 8b f6 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 40463f: b8 43 d4 4b 00 mov $0x4bd443,%eax + 404644: e9 81 f6 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404649: 41 80 fd 36 cmp $0x36,%r13b + 40464d: 75 54 jne 4046a3 <_nl_load_domain+0xf63> + 40464f: 80 7a 05 34 cmpb $0x34,0x5(%rdx) + 404653: 0f 85 71 f6 ff ff jne 403cca <_nl_load_domain+0x58a> + 404659: 80 7a 06 00 cmpb $0x0,0x6(%rdx) + 40465d: 0f 85 67 f6 ff ff jne 403cca <_nl_load_domain+0x58a> + 404663: 80 f9 64 cmp $0x64,%cl + 404666: 0f 84 13 06 00 00 je 404c7f <_nl_load_domain+0x153f> + 40466c: 80 f9 69 cmp $0x69,%cl + 40466f: 0f 84 00 06 00 00 je 404c75 <_nl_load_domain+0x1535> + 404675: 80 f9 6f cmp $0x6f,%cl + 404678: 0f 84 ed 05 00 00 je 404c6b <_nl_load_domain+0x152b> + 40467e: 80 f9 75 cmp $0x75,%cl + 404681: 0f 84 da 05 00 00 je 404c61 <_nl_load_domain+0x1521> + 404687: 80 f9 78 cmp $0x78,%cl + 40468a: 0f 84 85 00 00 00 je 404715 <_nl_load_domain+0xfd5> + 404690: 80 f9 58 cmp $0x58,%cl + 404693: 0f 85 9e fe ff ff jne 404537 <_nl_load_domain+0xdf7> + 404699: b8 ca 11 4a 00 mov $0x4a11ca,%eax + 40469e: e9 27 f6 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 4046a3: 41 80 fd 4c cmp $0x4c,%r13b + 4046a7: 0f 84 a3 01 00 00 je 404850 <_nl_load_domain+0x1110> + 4046ad: 41 80 fd 46 cmp $0x46,%r13b + 4046b1: 0f 84 f8 00 00 00 je 4047af <_nl_load_domain+0x106f> + 4046b7: 41 80 fd 4d cmp $0x4d,%r13b + 4046bb: 0f 84 90 00 00 00 je 404751 <_nl_load_domain+0x1011> + 4046c1: 41 80 fd 50 cmp $0x50,%r13b + 4046c5: 0f 85 ff f5 ff ff jne 403cca <_nl_load_domain+0x58a> + 4046cb: 80 7a 05 54 cmpb $0x54,0x5(%rdx) + 4046cf: 0f 85 f5 f5 ff ff jne 403cca <_nl_load_domain+0x58a> + 4046d5: 80 7a 06 52 cmpb $0x52,0x6(%rdx) + 4046d9: 0f 85 eb f5 ff ff jne 403cca <_nl_load_domain+0x58a> + 4046df: 80 7a 07 00 cmpb $0x0,0x7(%rdx) + 4046e3: 0f 85 e1 f5 ff ff jne 403cca <_nl_load_domain+0x58a> + 4046e9: 80 f9 64 cmp $0x64,%cl + 4046ec: 74 59 je 404747 <_nl_load_domain+0x1007> + 4046ee: 80 f9 69 cmp $0x69,%cl + 4046f1: 74 4a je 40473d <_nl_load_domain+0xffd> + 4046f3: 80 f9 6f cmp $0x6f,%cl + 4046f6: 74 3b je 404733 <_nl_load_domain+0xff3> + 4046f8: 80 f9 75 cmp $0x75,%cl + 4046fb: 74 2c je 404729 <_nl_load_domain+0xfe9> + 4046fd: 80 f9 78 cmp $0x78,%cl + 404700: 74 1d je 40471f <_nl_load_domain+0xfdf> + 404702: 80 f9 58 cmp $0x58,%cl + 404705: 0f 85 2c fe ff ff jne 404537 <_nl_load_domain+0xdf7> + 40470b: b8 ca 11 4a 00 mov $0x4a11ca,%eax + 404710: e9 b5 f5 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404715: b8 c1 11 4a 00 mov $0x4a11c1,%eax + 40471a: e9 ab f5 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 40471f: b8 c1 11 4a 00 mov $0x4a11c1,%eax + 404724: e9 a1 f5 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404729: b8 c7 11 4a 00 mov $0x4a11c7,%eax + 40472e: e9 97 f5 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404733: b8 d2 11 4a 00 mov $0x4a11d2,%eax + 404738: e9 8d f5 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 40473d: b8 cf 11 4a 00 mov $0x4a11cf,%eax + 404742: e9 83 f5 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404747: b8 c4 11 4a 00 mov $0x4a11c4,%eax + 40474c: e9 79 f5 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404751: 80 7a 05 41 cmpb $0x41,0x5(%rdx) + 404755: 0f 85 6f f5 ff ff jne 403cca <_nl_load_domain+0x58a> + 40475b: 80 7a 06 58 cmpb $0x58,0x6(%rdx) + 40475f: 0f 85 65 f5 ff ff jne 403cca <_nl_load_domain+0x58a> + 404765: 80 7a 07 00 cmpb $0x0,0x7(%rdx) + 404769: 0f 85 5b f5 ff ff jne 403cca <_nl_load_domain+0x58a> + 40476f: 80 f9 64 cmp $0x64,%cl + 404772: 0f 84 df 04 00 00 je 404c57 <_nl_load_domain+0x1517> + 404778: 80 f9 69 cmp $0x69,%cl + 40477b: 0f 84 cc 04 00 00 je 404c4d <_nl_load_domain+0x150d> + 404781: 80 f9 6f cmp $0x6f,%cl + 404784: 0f 84 b9 04 00 00 je 404c43 <_nl_load_domain+0x1503> + 40478a: 80 f9 75 cmp $0x75,%cl + 40478d: 0f 84 a6 04 00 00 je 404c39 <_nl_load_domain+0x14f9> + 404793: 80 f9 78 cmp $0x78,%cl + 404796: 0f 84 4b 01 00 00 je 4048e7 <_nl_load_domain+0x11a7> + 40479c: 80 f9 58 cmp $0x58,%cl + 40479f: 0f 85 92 fd ff ff jne 404537 <_nl_load_domain+0xdf7> + 4047a5: b8 ca 11 4a 00 mov $0x4a11ca,%eax + 4047aa: e9 1b f5 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 4047af: 80 7a 05 41 cmpb $0x41,0x5(%rdx) + 4047b3: 0f 85 11 f5 ff ff jne 403cca <_nl_load_domain+0x58a> + 4047b9: 80 7a 06 53 cmpb $0x53,0x6(%rdx) + 4047bd: 0f 85 07 f5 ff ff jne 403cca <_nl_load_domain+0x58a> + 4047c3: 80 7a 07 54 cmpb $0x54,0x7(%rdx) + 4047c7: 0f 85 fd f4 ff ff jne 403cca <_nl_load_domain+0x58a> + 4047cd: 44 0f b6 6a 08 movzbl 0x8(%rdx),%r13d + 4047d2: 41 80 fd 38 cmp $0x38,%r13b + 4047d6: 0f 84 83 03 00 00 je 404b5f <_nl_load_domain+0x141f> + 4047dc: 41 80 fd 31 cmp $0x31,%r13b + 4047e0: 0f 84 35 03 00 00 je 404b1b <_nl_load_domain+0x13db> + 4047e6: 41 80 fd 33 cmp $0x33,%r13b + 4047ea: 0f 84 d7 02 00 00 je 404ac7 <_nl_load_domain+0x1387> + 4047f0: 41 80 fd 36 cmp $0x36,%r13b + 4047f4: 0f 85 d0 f4 ff ff jne 403cca <_nl_load_domain+0x58a> + 4047fa: 31 c0 xor %eax,%eax + 4047fc: 80 7a 09 34 cmpb $0x34,0x9(%rdx) + 404800: 0f 85 c4 f4 ff ff jne 403cca <_nl_load_domain+0x58a> + 404806: 80 7a 0a 00 cmpb $0x0,0xa(%rdx) + 40480a: 0f 85 ba f4 ff ff jne 403cca <_nl_load_domain+0x58a> + 404810: 80 f9 64 cmp $0x64,%cl + 404813: 0f 84 a4 02 00 00 je 404abd <_nl_load_domain+0x137d> + 404819: 80 f9 69 cmp $0x69,%cl + 40481c: 0f 84 91 02 00 00 je 404ab3 <_nl_load_domain+0x1373> + 404822: 80 f9 6f cmp $0x6f,%cl + 404825: 0f 84 7e 02 00 00 je 404aa9 <_nl_load_domain+0x1369> + 40482b: 80 f9 75 cmp $0x75,%cl + 40482e: 0f 84 6b 02 00 00 je 404a9f <_nl_load_domain+0x135f> + 404834: 80 f9 78 cmp $0x78,%cl + 404837: 0f 84 58 02 00 00 je 404a95 <_nl_load_domain+0x1355> + 40483d: 80 f9 58 cmp $0x58,%cl + 404840: 0f 85 f1 fc ff ff jne 404537 <_nl_load_domain+0xdf7> + 404846: b8 ca 11 4a 00 mov $0x4a11ca,%eax + 40484b: e9 7a f4 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404850: 80 7a 05 45 cmpb $0x45,0x5(%rdx) + 404854: 0f 85 70 f4 ff ff jne 403cca <_nl_load_domain+0x58a> + 40485a: 80 7a 06 41 cmpb $0x41,0x6(%rdx) + 40485e: 0f 85 66 f4 ff ff jne 403cca <_nl_load_domain+0x58a> + 404864: 80 7a 07 53 cmpb $0x53,0x7(%rdx) + 404868: 0f 85 5c f4 ff ff jne 403cca <_nl_load_domain+0x58a> + 40486e: 80 7a 08 54 cmpb $0x54,0x8(%rdx) + 404872: 0f 85 52 f4 ff ff jne 403cca <_nl_load_domain+0x58a> + 404878: 44 0f b6 6a 09 movzbl 0x9(%rdx),%r13d + 40487d: 41 80 fd 38 cmp $0x38,%r13b + 404881: 0f 84 34 01 00 00 je 4049bb <_nl_load_domain+0x127b> + 404887: 41 80 fd 31 cmp $0x31,%r13b + 40488b: 0f 84 e6 00 00 00 je 404977 <_nl_load_domain+0x1237> + 404891: 41 80 fd 33 cmp $0x33,%r13b + 404895: 0f 84 88 00 00 00 je 404923 <_nl_load_domain+0x11e3> + 40489b: 41 80 fd 36 cmp $0x36,%r13b + 40489f: 0f 85 25 f4 ff ff jne 403cca <_nl_load_domain+0x58a> + 4048a5: 31 c0 xor %eax,%eax + 4048a7: 80 7a 0a 34 cmpb $0x34,0xa(%rdx) + 4048ab: 0f 85 19 f4 ff ff jne 403cca <_nl_load_domain+0x58a> + 4048b1: 80 7a 0b 00 cmpb $0x0,0xb(%rdx) + 4048b5: 0f 85 0f f4 ff ff jne 403cca <_nl_load_domain+0x58a> + 4048bb: 80 f9 64 cmp $0x64,%cl + 4048be: 74 59 je 404919 <_nl_load_domain+0x11d9> + 4048c0: 80 f9 69 cmp $0x69,%cl + 4048c3: 74 4a je 40490f <_nl_load_domain+0x11cf> + 4048c5: 80 f9 6f cmp $0x6f,%cl + 4048c8: 74 3b je 404905 <_nl_load_domain+0x11c5> + 4048ca: 80 f9 75 cmp $0x75,%cl + 4048cd: 74 2c je 4048fb <_nl_load_domain+0x11bb> + 4048cf: 80 f9 78 cmp $0x78,%cl + 4048d2: 74 1d je 4048f1 <_nl_load_domain+0x11b1> + 4048d4: 80 f9 58 cmp $0x58,%cl + 4048d7: 0f 85 5a fc ff ff jne 404537 <_nl_load_domain+0xdf7> + 4048dd: b8 ca 11 4a 00 mov $0x4a11ca,%eax + 4048e2: e9 e3 f3 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 4048e7: b8 c1 11 4a 00 mov $0x4a11c1,%eax + 4048ec: e9 d9 f3 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 4048f1: b8 c1 11 4a 00 mov $0x4a11c1,%eax + 4048f6: e9 cf f3 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 4048fb: b8 c7 11 4a 00 mov $0x4a11c7,%eax + 404900: e9 c5 f3 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404905: b8 d2 11 4a 00 mov $0x4a11d2,%eax + 40490a: e9 bb f3 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 40490f: b8 cf 11 4a 00 mov $0x4a11cf,%eax + 404914: e9 b1 f3 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404919: b8 c4 11 4a 00 mov $0x4a11c4,%eax + 40491e: e9 a7 f3 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404923: 80 7a 0a 32 cmpb $0x32,0xa(%rdx) + 404927: 0f 85 9d f3 ff ff jne 403cca <_nl_load_domain+0x58a> + 40492d: 80 7a 0b 00 cmpb $0x0,0xb(%rdx) + 404931: 0f 85 57 01 00 00 jne 404a8e <_nl_load_domain+0x134e> + 404937: 80 f9 64 cmp $0x64,%cl + 40493a: 0f 84 44 01 00 00 je 404a84 <_nl_load_domain+0x1344> + 404940: 80 f9 69 cmp $0x69,%cl + 404943: 0f 84 31 01 00 00 je 404a7a <_nl_load_domain+0x133a> + 404949: 80 f9 6f cmp $0x6f,%cl + 40494c: 0f 84 1e 01 00 00 je 404a70 <_nl_load_domain+0x1330> + 404952: 80 f9 75 cmp $0x75,%cl + 404955: 0f 84 0b 01 00 00 je 404a66 <_nl_load_domain+0x1326> + 40495b: 80 f9 78 cmp $0x78,%cl + 40495e: 0f 84 f8 00 00 00 je 404a5c <_nl_load_domain+0x131c> + 404964: 80 f9 58 cmp $0x58,%cl + 404967: 0f 85 ca fb ff ff jne 404537 <_nl_load_domain+0xdf7> + 40496d: b8 a5 5a 4b 00 mov $0x4b5aa5,%eax + 404972: e9 53 f3 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404977: 80 7a 0a 36 cmpb $0x36,0xa(%rdx) + 40497b: 0f 85 49 f3 ff ff jne 403cca <_nl_load_domain+0x58a> + 404981: 80 7a 0b 00 cmpb $0x0,0xb(%rdx) + 404985: 0f 85 ca 00 00 00 jne 404a55 <_nl_load_domain+0x1315> + 40498b: 80 f9 64 cmp $0x64,%cl + 40498e: 0f 84 b7 00 00 00 je 404a4b <_nl_load_domain+0x130b> + 404994: 80 f9 69 cmp $0x69,%cl + 404997: 74 6c je 404a05 <_nl_load_domain+0x12c5> + 404999: 80 f9 6f cmp $0x6f,%cl + 40499c: 74 5d je 4049fb <_nl_load_domain+0x12bb> + 40499e: 80 f9 75 cmp $0x75,%cl + 4049a1: 74 6c je 404a0f <_nl_load_domain+0x12cf> + 4049a3: 80 f9 78 cmp $0x78,%cl + 4049a6: 74 49 je 4049f1 <_nl_load_domain+0x12b1> + 4049a8: 80 f9 58 cmp $0x58,%cl + 4049ab: 0f 85 86 fb ff ff jne 404537 <_nl_load_domain+0xdf7> + 4049b1: b8 a5 5a 4b 00 mov $0x4b5aa5,%eax + 4049b6: e9 0f f3 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 4049bb: 80 7a 0a 00 cmpb $0x0,0xa(%rdx) + 4049bf: 0f 85 05 f3 ff ff jne 403cca <_nl_load_domain+0x58a> + 4049c5: 80 f9 64 cmp $0x64,%cl + 4049c8: 74 77 je 404a41 <_nl_load_domain+0x1301> + 4049ca: 80 f9 69 cmp $0x69,%cl + 4049cd: 74 68 je 404a37 <_nl_load_domain+0x12f7> + 4049cf: 80 f9 6f cmp $0x6f,%cl + 4049d2: 74 59 je 404a2d <_nl_load_domain+0x12ed> + 4049d4: 80 f9 75 cmp $0x75,%cl + 4049d7: 74 4a je 404a23 <_nl_load_domain+0x12e3> + 4049d9: 80 f9 78 cmp $0x78,%cl + 4049dc: 74 3b je 404a19 <_nl_load_domain+0x12d9> + 4049de: 80 f9 58 cmp $0x58,%cl + 4049e1: 0f 85 50 fb ff ff jne 404537 <_nl_load_domain+0xdf7> + 4049e7: b8 a5 5a 4b 00 mov $0x4b5aa5,%eax + 4049ec: e9 d9 f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 4049f1: b8 5a 4a 4a 00 mov $0x4a4a5a,%eax + 4049f6: e9 cf f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 4049fb: b8 34 4a 4a 00 mov $0x4a4a34,%eax + 404a00: e9 c5 f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404a05: b8 b7 52 4a 00 mov $0x4a52b7,%eax + 404a0a: e9 bb f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404a0f: b8 22 66 4b 00 mov $0x4b6622,%eax + 404a14: e9 b1 f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404a19: b8 5a 4a 4a 00 mov $0x4a4a5a,%eax + 404a1e: e9 a7 f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404a23: b8 22 66 4b 00 mov $0x4b6622,%eax + 404a28: e9 9d f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404a2d: b8 34 4a 4a 00 mov $0x4a4a34,%eax + 404a32: e9 93 f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404a37: b8 b7 52 4a 00 mov $0x4a52b7,%eax + 404a3c: e9 89 f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404a41: b8 43 d4 4b 00 mov $0x4bd443,%eax + 404a46: e9 7f f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404a4b: b8 43 d4 4b 00 mov $0x4bd443,%eax + 404a50: e9 75 f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404a55: 31 c0 xor %eax,%eax + 404a57: e9 6e f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404a5c: b8 5a 4a 4a 00 mov $0x4a4a5a,%eax + 404a61: e9 64 f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404a66: b8 22 66 4b 00 mov $0x4b6622,%eax + 404a6b: e9 5a f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404a70: b8 34 4a 4a 00 mov $0x4a4a34,%eax + 404a75: e9 50 f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404a7a: b8 b7 52 4a 00 mov $0x4a52b7,%eax + 404a7f: e9 46 f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404a84: b8 43 d4 4b 00 mov $0x4bd443,%eax + 404a89: e9 3c f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404a8e: 31 c0 xor %eax,%eax + 404a90: e9 35 f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404a95: b8 c1 11 4a 00 mov $0x4a11c1,%eax + 404a9a: e9 2b f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404a9f: b8 c7 11 4a 00 mov $0x4a11c7,%eax + 404aa4: e9 21 f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404aa9: b8 d2 11 4a 00 mov $0x4a11d2,%eax + 404aae: e9 17 f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404ab3: b8 cf 11 4a 00 mov $0x4a11cf,%eax + 404ab8: e9 0d f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404abd: b8 c4 11 4a 00 mov $0x4a11c4,%eax + 404ac2: e9 03 f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404ac7: 80 7a 09 32 cmpb $0x32,0x9(%rdx) + 404acb: 0f 85 f9 f1 ff ff jne 403cca <_nl_load_domain+0x58a> + 404ad1: 80 7a 0a 00 cmpb $0x0,0xa(%rdx) + 404ad5: 0f 85 57 01 00 00 jne 404c32 <_nl_load_domain+0x14f2> + 404adb: 80 f9 64 cmp $0x64,%cl + 404ade: 0f 84 44 01 00 00 je 404c28 <_nl_load_domain+0x14e8> + 404ae4: 80 f9 69 cmp $0x69,%cl + 404ae7: 0f 84 31 01 00 00 je 404c1e <_nl_load_domain+0x14de> + 404aed: 80 f9 6f cmp $0x6f,%cl + 404af0: 0f 84 1e 01 00 00 je 404c14 <_nl_load_domain+0x14d4> + 404af6: 80 f9 75 cmp $0x75,%cl + 404af9: 0f 84 0b 01 00 00 je 404c0a <_nl_load_domain+0x14ca> + 404aff: 80 f9 78 cmp $0x78,%cl + 404b02: 0f 84 f8 00 00 00 je 404c00 <_nl_load_domain+0x14c0> + 404b08: 80 f9 58 cmp $0x58,%cl + 404b0b: 0f 85 26 fa ff ff jne 404537 <_nl_load_domain+0xdf7> + 404b11: b8 ca 11 4a 00 mov $0x4a11ca,%eax + 404b16: e9 af f1 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404b1b: 80 7a 09 36 cmpb $0x36,0x9(%rdx) + 404b1f: 0f 85 a5 f1 ff ff jne 403cca <_nl_load_domain+0x58a> + 404b25: 80 7a 0a 00 cmpb $0x0,0xa(%rdx) + 404b29: 0f 85 ca 00 00 00 jne 404bf9 <_nl_load_domain+0x14b9> + 404b2f: 80 f9 64 cmp $0x64,%cl + 404b32: 0f 84 b7 00 00 00 je 404bef <_nl_load_domain+0x14af> + 404b38: 80 f9 69 cmp $0x69,%cl + 404b3b: 74 6c je 404ba9 <_nl_load_domain+0x1469> + 404b3d: 80 f9 6f cmp $0x6f,%cl + 404b40: 74 5d je 404b9f <_nl_load_domain+0x145f> + 404b42: 80 f9 75 cmp $0x75,%cl + 404b45: 74 6c je 404bb3 <_nl_load_domain+0x1473> + 404b47: 80 f9 78 cmp $0x78,%cl + 404b4a: 74 49 je 404b95 <_nl_load_domain+0x1455> + 404b4c: 80 f9 58 cmp $0x58,%cl + 404b4f: 0f 85 e2 f9 ff ff jne 404537 <_nl_load_domain+0xdf7> + 404b55: b8 ca 11 4a 00 mov $0x4a11ca,%eax + 404b5a: e9 6b f1 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404b5f: 80 7a 09 00 cmpb $0x0,0x9(%rdx) + 404b63: 0f 85 61 f1 ff ff jne 403cca <_nl_load_domain+0x58a> + 404b69: 80 f9 64 cmp $0x64,%cl + 404b6c: 74 77 je 404be5 <_nl_load_domain+0x14a5> + 404b6e: 80 f9 69 cmp $0x69,%cl + 404b71: 74 68 je 404bdb <_nl_load_domain+0x149b> + 404b73: 80 f9 6f cmp $0x6f,%cl + 404b76: 74 59 je 404bd1 <_nl_load_domain+0x1491> + 404b78: 80 f9 75 cmp $0x75,%cl + 404b7b: 74 4a je 404bc7 <_nl_load_domain+0x1487> + 404b7d: 80 f9 78 cmp $0x78,%cl + 404b80: 74 3b je 404bbd <_nl_load_domain+0x147d> + 404b82: 80 f9 58 cmp $0x58,%cl + 404b85: 0f 85 ac f9 ff ff jne 404537 <_nl_load_domain+0xdf7> + 404b8b: b8 a5 5a 4b 00 mov $0x4b5aa5,%eax + 404b90: e9 35 f1 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404b95: b8 c1 11 4a 00 mov $0x4a11c1,%eax + 404b9a: e9 2b f1 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404b9f: b8 d2 11 4a 00 mov $0x4a11d2,%eax + 404ba4: e9 21 f1 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404ba9: b8 cf 11 4a 00 mov $0x4a11cf,%eax + 404bae: e9 17 f1 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404bb3: b8 c7 11 4a 00 mov $0x4a11c7,%eax + 404bb8: e9 0d f1 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404bbd: b8 5a 4a 4a 00 mov $0x4a4a5a,%eax + 404bc2: e9 03 f1 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404bc7: b8 22 66 4b 00 mov $0x4b6622,%eax + 404bcc: e9 f9 f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404bd1: b8 34 4a 4a 00 mov $0x4a4a34,%eax + 404bd6: e9 ef f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404bdb: b8 b7 52 4a 00 mov $0x4a52b7,%eax + 404be0: e9 e5 f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404be5: b8 43 d4 4b 00 mov $0x4bd443,%eax + 404bea: e9 db f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404bef: b8 c4 11 4a 00 mov $0x4a11c4,%eax + 404bf4: e9 d1 f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404bf9: 31 c0 xor %eax,%eax + 404bfb: e9 ca f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404c00: b8 c1 11 4a 00 mov $0x4a11c1,%eax + 404c05: e9 c0 f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404c0a: b8 c7 11 4a 00 mov $0x4a11c7,%eax + 404c0f: e9 b6 f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404c14: b8 d2 11 4a 00 mov $0x4a11d2,%eax + 404c19: e9 ac f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404c1e: b8 cf 11 4a 00 mov $0x4a11cf,%eax + 404c23: e9 a2 f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404c28: b8 c4 11 4a 00 mov $0x4a11c4,%eax + 404c2d: e9 98 f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404c32: 31 c0 xor %eax,%eax + 404c34: e9 91 f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404c39: b8 c7 11 4a 00 mov $0x4a11c7,%eax + 404c3e: e9 87 f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404c43: b8 d2 11 4a 00 mov $0x4a11d2,%eax + 404c48: e9 7d f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404c4d: b8 cf 11 4a 00 mov $0x4a11cf,%eax + 404c52: e9 73 f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404c57: b8 c4 11 4a 00 mov $0x4a11c4,%eax + 404c5c: e9 69 f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404c61: b8 c7 11 4a 00 mov $0x4a11c7,%eax + 404c66: e9 5f f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404c6b: b8 d2 11 4a 00 mov $0x4a11d2,%eax + 404c70: e9 55 f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404c75: b8 cf 11 4a 00 mov $0x4a11cf,%eax + 404c7a: e9 4b f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404c7f: b8 c4 11 4a 00 mov $0x4a11c4,%eax + 404c84: e9 41 f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> + 404c89: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + +0000000000404c90 : + 404c90: 48 8b 36 mov (%rsi),%rsi + 404c93: 48 8b 3f mov (%rdi),%rdi + 404c96: ba 80 26 4b 00 mov $0x4b2680,%edx + 404c9b: e9 a0 b6 ff ff jmpq 400340 <__rela_iplt_end+0x78> + +0000000000404ca0 : + 404ca0: 55 push %rbp + 404ca1: 48 63 d6 movslq %esi,%rdx + 404ca4: 48 89 fe mov %rdi,%rsi + 404ca7: 48 8d 42 2c lea 0x2c(%rdx),%rax + 404cab: 48 89 e5 mov %rsp,%rbp + 404cae: 41 57 push %r15 + 404cb0: 41 56 push %r14 + 404cb2: 41 55 push %r13 + 404cb4: 41 54 push %r12 + 404cb6: 48 83 e0 f0 and $0xfffffffffffffff0,%rax + 404cba: 53 push %rbx + 404cbb: 48 81 ec d8 01 00 00 sub $0x1d8,%rsp + 404cc2: 48 29 c4 sub %rax,%rsp + 404cc5: 48 8d 5c 24 0f lea 0xf(%rsp),%rbx + 404cca: 48 83 e3 f0 and $0xfffffffffffffff0,%rbx + 404cce: 48 89 df mov %rbx,%rdi + 404cd1: e8 ea 18 02 00 callq 4265c0 <__mempcpy> + 404cd6: ba 0e 00 00 00 mov $0xe,%edx + 404cdb: be f0 11 4a 00 mov $0x4a11f0,%esi + 404ce0: 48 89 c7 mov %rax,%rdi + 404ce3: e8 d8 18 02 00 callq 4265c0 <__mempcpy> + 404ce8: be d5 11 4a 00 mov $0x4a11d5,%esi + 404ced: 48 89 df mov %rbx,%rdi + 404cf0: e8 bb ac 00 00 callq 40f9b0 <_IO_new_fopen> + 404cf5: 48 85 c0 test %rax,%rax + 404cf8: 0f 84 0d 04 00 00 je 40510b + 404cfe: 49 89 c7 mov %rax,%r15 + 404d01: 8b 00 mov (%rax),%eax + 404d03: 89 c2 mov %eax,%edx + 404d05: 80 ce 80 or $0x80,%dh + 404d08: a8 10 test $0x10,%al + 404d0a: 41 89 17 mov %edx,(%r15) + 404d0d: 0f 85 f0 03 00 00 jne 405103 + 404d13: 48 c7 85 18 fe ff ff movq $0x0,-0x1e8(%rbp) + 404d1a: 00 00 00 00 + 404d1e: 66 90 xchg %ax,%ax + 404d20: 48 8d bd 40 fe ff ff lea -0x1c0(%rbp),%rdi + 404d27: 4c 89 fa mov %r15,%rdx + 404d2a: be 90 01 00 00 mov $0x190,%esi + 404d2f: e8 7c cb 00 00 callq 4118b0 <__fgets_unlocked> + 404d34: 48 85 c0 test %rax,%rax + 404d37: 0f 84 ff 01 00 00 je 404f3c + 404d3d: 48 8d bd 40 fe ff ff lea -0x1c0(%rbp),%rdi + 404d44: be 0a 00 00 00 mov $0xa,%esi + 404d49: e8 32 b6 ff ff callq 400380 <__rela_iplt_end+0xb8> + 404d4e: 49 89 c6 mov %rax,%r14 + 404d51: 48 c7 c0 f0 ff ff ff mov $0xfffffffffffffff0,%rax + 404d58: 0f b6 8d 40 fe ff ff movzbl -0x1c0(%rbp),%ecx + 404d5f: 64 48 8b 00 mov %fs:(%rax),%rax + 404d63: 48 89 ca mov %rcx,%rdx + 404d66: f6 44 48 01 20 testb $0x20,0x1(%rax,%rcx,2) + 404d6b: 48 8d 8d 40 fe ff ff lea -0x1c0(%rbp),%rcx + 404d72: 74 15 je 404d89 + 404d74: 0f 1f 40 00 nopl 0x0(%rax) + 404d78: 48 83 c1 01 add $0x1,%rcx + 404d7c: 0f b6 31 movzbl (%rcx),%esi + 404d7f: f6 44 70 01 20 testb $0x20,0x1(%rax,%rsi,2) + 404d84: 48 89 f2 mov %rsi,%rdx + 404d87: 75 ef jne 404d78 + 404d89: 84 d2 test %dl,%dl + 404d8b: 0f 84 9c 01 00 00 je 404f2d + 404d91: 80 fa 23 cmp $0x23,%dl + 404d94: 0f 84 93 01 00 00 je 404f2d + 404d9a: 0f b6 51 01 movzbl 0x1(%rcx),%edx + 404d9e: 48 8d 59 01 lea 0x1(%rcx),%rbx + 404da2: 84 d2 test %dl,%dl + 404da4: 75 19 jne 404dbf + 404da6: e9 15 02 00 00 jmpq 404fc0 + 404dab: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 404db0: 48 83 c3 01 add $0x1,%rbx + 404db4: 0f b6 13 movzbl (%rbx),%edx + 404db7: 84 d2 test %dl,%dl + 404db9: 0f 84 01 02 00 00 je 404fc0 + 404dbf: f6 44 50 01 20 testb $0x20,0x1(%rax,%rdx,2) + 404dc4: 74 ea je 404db0 + 404dc6: 48 89 da mov %rbx,%rdx + 404dc9: 48 83 c3 01 add $0x1,%rbx + 404dcd: 0f b6 72 01 movzbl 0x1(%rdx),%esi + 404dd1: c6 02 00 movb $0x0,(%rdx) + 404dd4: f6 44 70 01 20 testb $0x20,0x1(%rax,%rsi,2) + 404dd9: 48 89 f2 mov %rsi,%rdx + 404ddc: 74 13 je 404df1 + 404dde: 66 90 xchg %ax,%ax + 404de0: 48 83 c3 01 add $0x1,%rbx + 404de4: 0f b6 33 movzbl (%rbx),%esi + 404de7: f6 44 70 01 20 testb $0x20,0x1(%rax,%rsi,2) + 404dec: 48 89 f2 mov %rsi,%rdx + 404def: 75 ef jne 404de0 + 404df1: 84 d2 test %dl,%dl + 404df3: 0f 84 34 01 00 00 je 404f2d + 404df9: 0f b6 53 01 movzbl 0x1(%rbx),%edx + 404dfd: 48 8d 73 01 lea 0x1(%rbx),%rsi + 404e01: 84 d2 test %dl,%dl + 404e03: 75 16 jne 404e1b + 404e05: eb 2e jmp 404e35 + 404e07: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 404e0e: 00 00 + 404e10: 48 83 c6 01 add $0x1,%rsi + 404e14: 0f b6 16 movzbl (%rsi),%edx + 404e17: 84 d2 test %dl,%dl + 404e19: 74 1a je 404e35 + 404e1b: 0f b6 fa movzbl %dl,%edi + 404e1e: f6 44 78 01 20 testb $0x20,0x1(%rax,%rdi,2) + 404e23: 74 eb je 404e10 + 404e25: 80 fa 0a cmp $0xa,%dl + 404e28: 0f 85 7d 02 00 00 jne 4050ab + 404e2e: c6 06 00 movb $0x0,(%rsi) + 404e31: c6 46 01 0a movb $0xa,0x1(%rsi) + 404e35: 4c 8b 25 c4 72 2c 00 mov 0x2c72c4(%rip),%r12 # 6cc100 + 404e3c: 48 8b 35 b5 72 2c 00 mov 0x2c72b5(%rip),%rsi # 6cc0f8 + 404e43: 49 39 f4 cmp %rsi,%r12 + 404e46: 0f 83 67 02 00 00 jae 4050b3 + 404e4c: 48 89 cf mov %rcx,%rdi + 404e4f: 48 89 8d 28 fe ff ff mov %rcx,-0x1d8(%rbp) + 404e56: e8 f5 e7 01 00 callq 423650 + 404e5b: 48 8d 50 01 lea 0x1(%rax),%rdx + 404e5f: 48 89 df mov %rbx,%rdi + 404e62: 48 89 95 38 fe ff ff mov %rdx,-0x1c8(%rbp) + 404e69: e8 e2 e7 01 00 callq 423650 + 404e6e: 48 8b 95 38 fe ff ff mov -0x1c8(%rbp),%rdx + 404e75: 4c 8b 1d 94 72 2c 00 mov 0x2c7294(%rip),%r11 # 6cc110 + 404e7c: 4c 8d 50 01 lea 0x1(%rax),%r10 + 404e80: 48 8b 8d 28 fe ff ff mov -0x1d8(%rbp),%rcx + 404e87: 4a 8d 04 1a lea (%rdx,%r11,1),%rax + 404e8b: 48 89 85 38 fe ff ff mov %rax,-0x1c8(%rbp) + 404e92: 4c 01 d0 add %r10,%rax + 404e95: 48 89 c7 mov %rax,%rdi + 404e98: 48 89 85 30 fe ff ff mov %rax,-0x1d0(%rbp) + 404e9f: 48 8b 05 62 72 2c 00 mov 0x2c7262(%rip),%rax # 6cc108 + 404ea6: 48 39 c7 cmp %rax,%rdi + 404ea9: 0f 87 21 01 00 00 ja 404fd0 + 404eaf: 4c 8b 0d 2a 85 2c 00 mov 0x2c852a(%rip),%r9 # 6cd3e0 + 404eb6: 48 8b 3d 1b 85 2c 00 mov 0x2c851b(%rip),%rdi # 6cd3d8 + 404ebd: 4d 89 e5 mov %r12,%r13 + 404ec0: 48 89 ce mov %rcx,%rsi + 404ec3: 4c 89 95 20 fe ff ff mov %r10,-0x1e0(%rbp) + 404eca: 49 c1 e5 04 shl $0x4,%r13 + 404ece: 4c 89 8d 28 fe ff ff mov %r9,-0x1d8(%rbp) + 404ed5: 49 83 c4 01 add $0x1,%r12 + 404ed9: 49 01 fd add %rdi,%r13 + 404edc: 4b 8d 3c 19 lea (%r9,%r11,1),%rdi + 404ee0: e8 3b 71 02 00 callq 42c020 + 404ee5: 48 8b bd 38 fe ff ff mov -0x1c8(%rbp),%rdi + 404eec: 4c 8b 8d 28 fe ff ff mov -0x1d8(%rbp),%r9 + 404ef3: 48 89 de mov %rbx,%rsi + 404ef6: 4c 8b 95 20 fe ff ff mov -0x1e0(%rbp),%r10 + 404efd: 49 89 45 00 mov %rax,0x0(%r13) + 404f01: 4c 01 cf add %r9,%rdi + 404f04: 4c 89 d2 mov %r10,%rdx + 404f07: e8 14 71 02 00 callq 42c020 + 404f0c: 48 83 85 18 fe ff ff addq $0x1,-0x1e8(%rbp) + 404f13: 01 + 404f14: 49 89 45 08 mov %rax,0x8(%r13) + 404f18: 48 8b 85 30 fe ff ff mov -0x1d0(%rbp),%rax + 404f1f: 4c 89 25 da 71 2c 00 mov %r12,0x2c71da(%rip) # 6cc100 + 404f26: 48 89 05 e3 71 2c 00 mov %rax,0x2c71e3(%rip) # 6cc110 + 404f2d: 4d 85 f6 test %r14,%r14 + 404f30: 74 6c je 404f9e + 404f32: 41 f6 07 10 testb $0x10,(%r15) + 404f36: 0f 84 e4 fd ff ff je 404d20 + 404f3c: 4c 89 ff mov %r15,%rdi + 404f3f: e8 9c a5 00 00 callq 40f4e0 <_IO_new_fclose> + 404f44: 31 c0 xor %eax,%eax + 404f46: 48 83 bd 18 fe ff ff cmpq $0x0,-0x1e8(%rbp) + 404f4d: 00 + 404f4e: 74 24 je 404f74 + 404f50: 48 8b 35 a9 71 2c 00 mov 0x2c71a9(%rip),%rsi # 6cc100 + 404f57: 48 8b 3d 7a 84 2c 00 mov 0x2c847a(%rip),%rdi # 6cd3d8 + 404f5e: b9 90 4c 40 00 mov $0x404c90,%ecx + 404f63: ba 10 00 00 00 mov $0x10,%edx + 404f68: e8 63 98 00 00 callq 40e7d0 + 404f6d: 48 8b 85 18 fe ff ff mov -0x1e8(%rbp),%rax + 404f74: 48 8d 65 d8 lea -0x28(%rbp),%rsp + 404f78: 5b pop %rbx + 404f79: 41 5c pop %r12 + 404f7b: 41 5d pop %r13 + 404f7d: 41 5e pop %r14 + 404f7f: 41 5f pop %r15 + 404f81: 5d pop %rbp + 404f82: c3 retq + 404f83: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 404f88: 48 8d bd 40 fe ff ff lea -0x1c0(%rbp),%rdi + 404f8f: be 0a 00 00 00 mov $0xa,%esi + 404f94: e8 e7 b3 ff ff callq 400380 <__rela_iplt_end+0xb8> + 404f99: 48 85 c0 test %rax,%rax + 404f9c: 75 94 jne 404f32 + 404f9e: 48 8d bd 40 fe ff ff lea -0x1c0(%rbp),%rdi + 404fa5: 4c 89 fa mov %r15,%rdx + 404fa8: be 90 01 00 00 mov $0x190,%esi + 404fad: e8 fe c8 00 00 callq 4118b0 <__fgets_unlocked> + 404fb2: 48 85 c0 test %rax,%rax + 404fb5: 75 d1 jne 404f88 + 404fb7: e9 76 ff ff ff jmpq 404f32 + 404fbc: 0f 1f 40 00 nopl 0x0(%rax) + 404fc0: 66 f7 00 00 20 testw $0x2000,(%rax) + 404fc5: 0f 85 15 fe ff ff jne 404de0 + 404fcb: e9 5d ff ff ff jmpq 404f2d + 404fd0: 4a 8d 34 12 lea (%rdx,%r10,1),%rsi + 404fd4: bf 00 04 00 00 mov $0x400,%edi + 404fd9: 4c 8b 2d 00 84 2c 00 mov 0x2c8400(%rip),%r13 # 6cd3e0 + 404fe0: 4c 89 9d 00 fe ff ff mov %r11,-0x200(%rbp) + 404fe7: 48 89 8d 08 fe ff ff mov %rcx,-0x1f8(%rbp) + 404fee: 48 81 fe 00 04 00 00 cmp $0x400,%rsi + 404ff5: 4c 89 95 10 fe ff ff mov %r10,-0x1f0(%rbp) + 404ffc: 48 89 95 20 fe ff ff mov %rdx,-0x1e0(%rbp) + 405003: 48 0f 42 f7 cmovb %rdi,%rsi + 405007: 4c 89 ef mov %r13,%rdi + 40500a: 4c 8d 04 06 lea (%rsi,%rax,1),%r8 + 40500e: 4c 89 c6 mov %r8,%rsi + 405011: 4c 89 85 28 fe ff ff mov %r8,-0x1d8(%rbp) + 405018: e8 53 8f 01 00 callq 41df70 <__libc_realloc> + 40501d: 48 85 c0 test %rax,%rax + 405020: 0f 84 16 ff ff ff je 404f3c + 405026: 49 39 c5 cmp %rax,%r13 + 405029: 48 8b 3d a8 83 2c 00 mov 0x2c83a8(%rip),%rdi # 6cd3d8 + 405030: 4c 8b 85 28 fe ff ff mov -0x1d8(%rbp),%r8 + 405037: 48 8b 95 20 fe ff ff mov -0x1e0(%rbp),%rdx + 40503e: 4c 8b 95 10 fe ff ff mov -0x1f0(%rbp),%r10 + 405045: 48 8b 8d 08 fe ff ff mov -0x1f8(%rbp),%rcx + 40504c: 4c 8b 9d 00 fe ff ff mov -0x200(%rbp),%r11 + 405053: 74 40 je 405095 + 405055: 4d 85 e4 test %r12,%r12 + 405058: 74 3b je 405095 + 40505a: 48 89 c6 mov %rax,%rsi + 40505d: 4d 89 e1 mov %r12,%r9 + 405060: 4c 29 ee sub %r13,%rsi + 405063: 49 c1 e1 04 shl $0x4,%r9 + 405067: 48 89 b5 28 fe ff ff mov %rsi,-0x1d8(%rbp) + 40506e: 49 01 f9 add %rdi,%r9 + 405071: 48 89 fe mov %rdi,%rsi + 405074: f3 0f 7e 8d 28 fe ff movq -0x1d8(%rbp),%xmm1 + 40507b: ff + 40507c: 66 0f 6c c9 punpcklqdq %xmm1,%xmm1 + 405080: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 405084: 48 83 c6 10 add $0x10,%rsi + 405088: 66 0f d4 c1 paddq %xmm1,%xmm0 + 40508c: 0f 11 46 f0 movups %xmm0,-0x10(%rsi) + 405090: 4c 39 ce cmp %r9,%rsi + 405093: 75 eb jne 405080 + 405095: 48 89 05 44 83 2c 00 mov %rax,0x2c8344(%rip) # 6cd3e0 + 40509c: 4c 89 05 65 70 2c 00 mov %r8,0x2c7065(%rip) # 6cc108 + 4050a3: 49 89 c1 mov %rax,%r9 + 4050a6: e9 12 fe ff ff jmpq 404ebd + 4050ab: c6 06 00 movb $0x0,(%rsi) + 4050ae: e9 82 fd ff ff jmpq 404e35 + 4050b3: 48 85 f6 test %rsi,%rsi + 4050b6: 74 3e je 4050f6 + 4050b8: 4c 8d 2c 36 lea (%rsi,%rsi,1),%r13 + 4050bc: 48 c1 e6 05 shl $0x5,%rsi + 4050c0: 48 8b 3d 11 83 2c 00 mov 0x2c8311(%rip),%rdi # 6cd3d8 + 4050c7: 48 89 8d 38 fe ff ff mov %rcx,-0x1c8(%rbp) + 4050ce: e8 9d 8e 01 00 callq 41df70 <__libc_realloc> + 4050d3: 48 85 c0 test %rax,%rax + 4050d6: 0f 84 60 fe ff ff je 404f3c + 4050dc: 48 89 05 f5 82 2c 00 mov %rax,0x2c82f5(%rip) # 6cd3d8 + 4050e3: 4c 89 2d 0e 70 2c 00 mov %r13,0x2c700e(%rip) # 6cc0f8 + 4050ea: 48 8b 8d 38 fe ff ff mov -0x1c8(%rbp),%rcx + 4050f1: e9 56 fd ff ff jmpq 404e4c + 4050f6: be 40 06 00 00 mov $0x640,%esi + 4050fb: 41 bd 64 00 00 00 mov $0x64,%r13d + 405101: eb bd jmp 4050c0 + 405103: 4c 89 ff mov %r15,%rdi + 405106: e8 d5 a3 00 00 callq 40f4e0 <_IO_new_fclose> + 40510b: 48 8d 65 d8 lea -0x28(%rbp),%rsp + 40510f: 31 c0 xor %eax,%eax + 405111: 5b pop %rbx + 405112: 41 5c pop %r12 + 405114: 41 5d pop %r13 + 405116: 41 5e pop %r14 + 405118: 41 5f pop %r15 + 40511a: 5d pop %rbp + 40511b: c3 retq + 40511c: 0f 1f 40 00 nopl 0x0(%rax) + +0000000000405120 <_nl_expand_alias>: + 405120: 41 57 push %r15 + 405122: 41 56 push %r14 + 405124: be 01 00 00 00 mov $0x1,%esi + 405129: 41 55 push %r13 + 40512b: 41 54 push %r12 + 40512d: 31 c0 xor %eax,%eax + 40512f: 55 push %rbp + 405130: 53 push %rbx + 405131: 48 89 fb mov %rdi,%rbx + 405134: 48 83 ec 08 sub $0x8,%rsp + 405138: 83 3d 7d 80 2c 00 00 cmpl $0x0,0x2c807d(%rip) # 6cd1bc <__libc_multiple_threads> + 40513f: 74 0c je 40514d <_nl_expand_alias+0x2d> + 405141: f0 0f b1 35 cf 6f 2c lock cmpxchg %esi,0x2c6fcf(%rip) # 6cc118 + 405148: 00 + 405149: 75 0b jne 405156 <_nl_expand_alias+0x36> + 40514b: eb 23 jmp 405170 <_nl_expand_alias+0x50> + 40514d: 0f b1 35 c4 6f 2c 00 cmpxchg %esi,0x2c6fc4(%rip) # 6cc118 + 405154: 74 1a je 405170 <_nl_expand_alias+0x50> + 405156: 48 8d 3d bb 6f 2c 00 lea 0x2c6fbb(%rip),%rdi # 6cc118 + 40515d: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 405164: e8 67 d4 03 00 callq 4425d0 <__lll_lock_wait_private> + 405169: 48 81 c4 80 00 00 00 add $0x80,%rsp + 405170: 48 83 3d 78 6f 2c 00 cmpq $0x0,0x2c6f78(%rip) # 6cc0f0 + 405177: 00 + 405178: 0f 84 51 01 00 00 je 4052cf <_nl_expand_alias+0x1af> + 40517e: 4c 8b 3d 7b 6f 2c 00 mov 0x2c6f7b(%rip),%r15 # 6cc100 + 405185: 4d 85 ff test %r15,%r15 + 405188: 74 54 je 4051de <_nl_expand_alias+0xbe> + 40518a: 4c 8b 35 47 82 2c 00 mov 0x2c8247(%rip),%r14 # 6cd3d8 + 405191: 45 31 ed xor %r13d,%r13d + 405194: eb 19 jmp 4051af <_nl_expand_alias+0x8f> + 405196: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 40519d: 00 00 00 + 4051a0: 0f 84 22 01 00 00 je 4052c8 <_nl_expand_alias+0x1a8> + 4051a6: 4c 8d 6d 01 lea 0x1(%rbp),%r13 + 4051aa: 4d 39 ef cmp %r13,%r15 + 4051ad: 76 2f jbe 4051de <_nl_expand_alias+0xbe> + 4051af: 4b 8d 6c 3d 00 lea 0x0(%r13,%r15,1),%rbp + 4051b4: ba 80 26 4b 00 mov $0x4b2680,%edx + 4051b9: 48 89 df mov %rbx,%rdi + 4051bc: 48 d1 ed shr %rbp + 4051bf: 49 89 ec mov %rbp,%r12 + 4051c2: 49 c1 e4 04 shl $0x4,%r12 + 4051c6: 4d 01 f4 add %r14,%r12 + 4051c9: 49 8b 34 24 mov (%r12),%rsi + 4051cd: e8 6e b1 ff ff callq 400340 <__rela_iplt_end+0x78> + 4051d2: 85 c0 test %eax,%eax + 4051d4: 79 ca jns 4051a0 <_nl_expand_alias+0x80> + 4051d6: 49 89 ef mov %rbp,%r15 + 4051d9: 4d 39 ef cmp %r13,%r15 + 4051dc: 77 d1 ja 4051af <_nl_expand_alias+0x8f> + 4051de: 48 8b 0d 0b 6f 2c 00 mov 0x2c6f0b(%rip),%rcx # 6cc0f0 + 4051e5: 0f b6 01 movzbl (%rcx),%eax + 4051e8: 84 c0 test %al,%al + 4051ea: 74 69 je 405255 <_nl_expand_alias+0x135> + 4051ec: 48 89 cf mov %rcx,%rdi + 4051ef: 31 f6 xor %esi,%esi + 4051f1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4051f8: 3c 3a cmp $0x3a,%al + 4051fa: 48 8d 51 01 lea 0x1(%rcx),%rdx + 4051fe: 75 17 jne 405217 <_nl_expand_alias+0xf7> + 405200: 48 89 d7 mov %rdx,%rdi + 405203: 48 8d 52 01 lea 0x1(%rdx),%rdx + 405207: 0f b6 42 ff movzbl -0x1(%rdx),%eax + 40520b: 3c 3a cmp $0x3a,%al + 40520d: 74 f1 je 405200 <_nl_expand_alias+0xe0> + 40520f: 48 89 f9 mov %rdi,%rcx + 405212: be 01 00 00 00 mov $0x1,%esi + 405217: 84 c0 test %al,%al + 405219: 0f 84 9d 00 00 00 je 4052bc <_nl_expand_alias+0x19c> + 40521f: 48 8d 77 01 lea 0x1(%rdi),%rsi + 405223: eb 0a jmp 40522f <_nl_expand_alias+0x10f> + 405225: 0f 1f 00 nopl (%rax) + 405228: 3c 3a cmp $0x3a,%al + 40522a: 74 11 je 40523d <_nl_expand_alias+0x11d> + 40522c: 48 89 d6 mov %rdx,%rsi + 40522f: 0f b6 06 movzbl (%rsi),%eax + 405232: 48 89 f1 mov %rsi,%rcx + 405235: 48 8d 56 01 lea 0x1(%rsi),%rdx + 405239: 84 c0 test %al,%al + 40523b: 75 eb jne 405228 <_nl_expand_alias+0x108> + 40523d: 48 39 fe cmp %rdi,%rsi + 405240: 77 5d ja 40529f <_nl_expand_alias+0x17f> + 405242: 84 c0 test %al,%al + 405244: 48 89 f7 mov %rsi,%rdi + 405247: be 01 00 00 00 mov $0x1,%esi + 40524c: 75 aa jne 4051f8 <_nl_expand_alias+0xd8> + 40524e: 48 89 0d 9b 6e 2c 00 mov %rcx,0x2c6e9b(%rip) # 6cc0f0 + 405255: 31 d2 xor %edx,%edx + 405257: 83 3d 5e 7f 2c 00 00 cmpl $0x0,0x2c7f5e(%rip) # 6cd1bc <__libc_multiple_threads> + 40525e: 74 0b je 40526b <_nl_expand_alias+0x14b> + 405260: f0 ff 0d b1 6e 2c 00 lock decl 0x2c6eb1(%rip) # 6cc118 + 405267: 75 0a jne 405273 <_nl_expand_alias+0x153> + 405269: eb 22 jmp 40528d <_nl_expand_alias+0x16d> + 40526b: ff 0d a7 6e 2c 00 decl 0x2c6ea7(%rip) # 6cc118 + 405271: 74 1a je 40528d <_nl_expand_alias+0x16d> + 405273: 48 8d 3d 9e 6e 2c 00 lea 0x2c6e9e(%rip),%rdi # 6cc118 + 40527a: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 405281: e8 7a d3 03 00 callq 442600 <__lll_unlock_wake_private> + 405286: 48 81 c4 80 00 00 00 add $0x80,%rsp + 40528d: 48 83 c4 08 add $0x8,%rsp + 405291: 48 89 d0 mov %rdx,%rax + 405294: 5b pop %rbx + 405295: 5d pop %rbp + 405296: 41 5c pop %r12 + 405298: 41 5d pop %r13 + 40529a: 41 5e pop %r14 + 40529c: 41 5f pop %r15 + 40529e: c3 retq + 40529f: 48 89 35 4a 6e 2c 00 mov %rsi,0x2c6e4a(%rip) # 6cc0f0 + 4052a6: 48 29 fe sub %rdi,%rsi + 4052a9: e8 f2 f9 ff ff callq 404ca0 + 4052ae: 48 85 c0 test %rax,%rax + 4052b1: 0f 84 27 ff ff ff je 4051de <_nl_expand_alias+0xbe> + 4052b7: e9 c2 fe ff ff jmpq 40517e <_nl_expand_alias+0x5e> + 4052bc: 40 84 f6 test %sil,%sil + 4052bf: 74 94 je 405255 <_nl_expand_alias+0x135> + 4052c1: eb 8b jmp 40524e <_nl_expand_alias+0x12e> + 4052c3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4052c8: 49 8b 54 24 08 mov 0x8(%r12),%rdx + 4052cd: eb 88 jmp 405257 <_nl_expand_alias+0x137> + 4052cf: 48 c7 05 16 6e 2c 00 movq $0x4a11d9,0x2c6e16(%rip) # 6cc0f0 + 4052d6: d9 11 4a 00 + 4052da: e9 9f fe ff ff jmpq 40517e <_nl_expand_alias+0x5e> + 4052df: 90 nop + +00000000004052e0 <_nl_make_l10nflist>: + 4052e0: 41 57 push %r15 + 4052e2: 41 56 push %r14 + 4052e4: 4d 89 ce mov %r9,%r14 + 4052e7: 41 55 push %r13 + 4052e9: 41 54 push %r12 + 4052eb: 41 89 cc mov %ecx,%r12d + 4052ee: 55 push %rbp + 4052ef: 53 push %rbx + 4052f0: 48 89 d3 mov %rdx,%rbx + 4052f3: 48 83 c3 02 add $0x2,%rbx + 4052f7: 48 83 ec 48 sub $0x48,%rsp + 4052fb: 48 89 7c 24 08 mov %rdi,0x8(%rsp) + 405300: 4c 89 c7 mov %r8,%rdi + 405303: 48 89 74 24 28 mov %rsi,0x28(%rsp) + 405308: 48 89 54 24 18 mov %rdx,0x18(%rsp) + 40530d: 89 4c 24 34 mov %ecx,0x34(%rsp) + 405311: 4c 89 04 24 mov %r8,(%rsp) + 405315: 4c 89 4c 24 10 mov %r9,0x10(%rsp) + 40531a: e8 31 e3 01 00 callq 423650 + 40531f: 41 83 e4 04 and $0x4,%r12d + 405323: 4c 8b bc 24 98 00 00 mov 0x98(%rsp),%r15 + 40532a: 00 + 40532b: 49 89 c5 mov %rax,%r13 + 40532e: 0f 84 5c 04 00 00 je 405790 <_nl_make_l10nflist+0x4b0> + 405334: 4c 89 f7 mov %r14,%rdi + 405337: e8 14 e3 01 00 callq 423650 + 40533c: 48 8d 68 01 lea 0x1(%rax),%rbp + 405340: 8b 44 24 34 mov 0x34(%rsp),%eax + 405344: 49 01 dd add %rbx,%r13 + 405347: 45 31 f6 xor %r14d,%r14d + 40534a: 83 e0 02 and $0x2,%eax + 40534d: 89 44 24 20 mov %eax,0x20(%rsp) + 405351: 74 11 je 405364 <_nl_make_l10nflist+0x84> + 405353: 48 8b bc 24 80 00 00 mov 0x80(%rsp),%rdi + 40535a: 00 + 40535b: e8 f0 e2 01 00 callq 423650 + 405360: 4c 8d 70 01 lea 0x1(%rax),%r14 + 405364: 8b 44 24 34 mov 0x34(%rsp),%eax + 405368: 4c 01 ed add %r13,%rbp + 40536b: 31 db xor %ebx,%ebx + 40536d: 83 e0 01 and $0x1,%eax + 405370: 89 44 24 38 mov %eax,0x38(%rsp) + 405374: 74 11 je 405387 <_nl_make_l10nflist+0xa7> + 405376: 48 8b bc 24 88 00 00 mov 0x88(%rsp),%rdi + 40537d: 00 + 40537e: e8 cd e2 01 00 callq 423650 + 405383: 48 8d 58 01 lea 0x1(%rax),%rbx + 405387: 8b 44 24 34 mov 0x34(%rsp),%eax + 40538b: 4c 01 f5 add %r14,%rbp + 40538e: 45 31 ed xor %r13d,%r13d + 405391: 83 e0 08 and $0x8,%eax + 405394: 89 44 24 3c mov %eax,0x3c(%rsp) + 405398: 74 11 je 4053ab <_nl_make_l10nflist+0xcb> + 40539a: 48 8b bc 24 90 00 00 mov 0x90(%rsp),%rdi + 4053a1: 00 + 4053a2: e8 a9 e2 01 00 callq 423650 + 4053a7: 4c 8d 68 01 lea 0x1(%rax),%r13 + 4053ab: 4c 89 ff mov %r15,%rdi + 4053ae: e8 9d e2 01 00 callq 423650 + 4053b3: 48 8d 3c 2b lea (%rbx,%rbp,1),%rdi + 4053b7: 49 89 c6 mov %rax,%r14 + 4053ba: 4c 01 ef add %r13,%rdi + 4053bd: 48 01 c7 add %rax,%rdi + 4053c0: e8 4b 86 01 00 callq 41da10 <__libc_malloc> + 4053c5: 48 85 c0 test %rax,%rax + 4053c8: 49 89 c5 mov %rax,%r13 + 4053cb: 0f 84 a3 04 00 00 je 405874 <_nl_make_l10nflist+0x594> + 4053d1: 48 8b 5c 24 18 mov 0x18(%rsp),%rbx + 4053d6: 48 8b 74 24 28 mov 0x28(%rsp),%rsi + 4053db: 48 89 c7 mov %rax,%rdi + 4053de: 48 89 da mov %rbx,%rdx + 4053e1: e8 3a 6c 02 00 callq 42c020 + 4053e6: 48 85 db test %rbx,%rbx + 4053e9: 74 25 je 405410 <_nl_make_l10nflist+0x130> + 4053eb: 4c 89 ed mov %r13,%rbp + 4053ee: 66 90 xchg %ax,%ax + 4053f0: 48 89 ef mov %rbp,%rdi + 4053f3: e8 58 e2 01 00 callq 423650 + 4053f8: 48 29 c3 sub %rax,%rbx + 4053fb: 48 83 eb 01 sub $0x1,%rbx + 4053ff: 74 0f je 405410 <_nl_make_l10nflist+0x130> + 405401: 48 01 e8 add %rbp,%rax + 405404: 48 8d 68 01 lea 0x1(%rax),%rbp + 405408: c6 00 3a movb $0x3a,(%rax) + 40540b: eb e3 jmp 4053f0 <_nl_make_l10nflist+0x110> + 40540d: 0f 1f 00 nopl (%rax) + 405410: 48 8b 44 24 18 mov 0x18(%rsp),%rax + 405415: 48 8b 34 24 mov (%rsp),%rsi + 405419: 49 8d 7c 05 00 lea 0x0(%r13,%rax,1),%rdi + 40541e: 41 c6 44 05 ff 2f movb $0x2f,-0x1(%r13,%rax,1) + 405424: e8 e7 ae ff ff callq 400310 <__rela_iplt_end+0x48> + 405429: 45 85 e4 test %r12d,%r12d + 40542c: 0f 85 ce 03 00 00 jne 405800 <_nl_make_l10nflist+0x520> + 405432: 8b 74 24 20 mov 0x20(%rsp),%esi + 405436: 85 f6 test %esi,%esi + 405438: 0f 85 a0 03 00 00 jne 4057de <_nl_make_l10nflist+0x4fe> + 40543e: 8b 4c 24 38 mov 0x38(%rsp),%ecx + 405442: 85 c9 test %ecx,%ecx + 405444: 0f 85 7b 03 00 00 jne 4057c5 <_nl_make_l10nflist+0x4e5> + 40544a: 8b 54 24 3c mov 0x3c(%rsp),%edx + 40544e: 85 d2 test %edx,%edx + 405450: 0f 85 56 03 00 00 jne 4057ac <_nl_make_l10nflist+0x4cc> + 405456: 48 8d 78 01 lea 0x1(%rax),%rdi + 40545a: 49 8d 56 01 lea 0x1(%r14),%rdx + 40545e: c6 00 2f movb $0x2f,(%rax) + 405461: 4c 89 fe mov %r15,%rsi + 405464: e8 b7 6b 02 00 callq 42c020 + 405469: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40546e: 48 8b 00 mov (%rax),%rax + 405471: 48 85 c0 test %rax,%rax + 405474: 48 89 44 24 20 mov %rax,0x20(%rsp) + 405479: 0f 84 fc 03 00 00 je 40587b <_nl_make_l10nflist+0x59b> + 40547f: 49 89 c4 mov %rax,%r12 + 405482: 31 ed xor %ebp,%ebp + 405484: 0f 1f 40 00 nopl 0x0(%rax) + 405488: 49 8b 3c 24 mov (%r12),%rdi + 40548c: 48 85 ff test %rdi,%rdi + 40548f: 74 15 je 4054a6 <_nl_make_l10nflist+0x1c6> + 405491: 4c 89 ee mov %r13,%rsi + 405494: e8 c7 ae ff ff callq 400360 <__rela_iplt_end+0x98> + 405499: 85 c0 test %eax,%eax + 40549b: 0f 84 78 03 00 00 je 405819 <_nl_make_l10nflist+0x539> + 4054a1: 78 0d js 4054b0 <_nl_make_l10nflist+0x1d0> + 4054a3: 4c 89 e5 mov %r12,%rbp + 4054a6: 4d 8b 64 24 18 mov 0x18(%r12),%r12 + 4054ab: 4d 85 e4 test %r12,%r12 + 4054ae: 75 d8 jne 405488 <_nl_make_l10nflist+0x1a8> + 4054b0: 8b 84 24 a0 00 00 00 mov 0xa0(%rsp),%eax + 4054b7: 85 c0 test %eax,%eax + 4054b9: 0f 84 57 03 00 00 je 405816 <_nl_make_l10nflist+0x536> + 4054bf: 48 8b 44 24 18 mov 0x18(%rsp),%rax + 4054c4: 45 31 e4 xor %r12d,%r12d + 4054c7: 4c 8b 74 24 28 mov 0x28(%rsp),%r14 + 4054cc: 48 85 c0 test %rax,%rax + 4054cf: 48 89 c3 mov %rax,%rbx + 4054d2: 0f 84 7c 03 00 00 je 405854 <_nl_make_l10nflist+0x574> + 4054d8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 4054df: 00 + 4054e0: 4c 89 f7 mov %r14,%rdi + 4054e3: 49 83 c4 01 add $0x1,%r12 + 4054e7: e8 64 e1 01 00 callq 423650 + 4054ec: 48 29 c3 sub %rax,%rbx + 4054ef: 4d 8d 74 06 01 lea 0x1(%r14,%rax,1),%r14 + 4054f4: 48 83 eb 01 sub $0x1,%rbx + 4054f8: 75 e6 jne 4054e0 <_nl_make_l10nflist+0x200> + 4054fa: 8b 44 24 34 mov 0x34(%rsp),%eax + 4054fe: 89 c2 mov %eax,%edx + 405500: 25 55 55 00 00 and $0x5555,%eax + 405505: 81 e2 aa aa ff ff and $0xffffaaaa,%edx + 40550b: d1 fa sar %edx + 40550d: 01 c2 add %eax,%edx + 40550f: 89 d0 mov %edx,%eax + 405511: 81 e2 33 33 00 00 and $0x3333,%edx + 405517: 25 cc cc ff ff and $0xffffcccc,%eax + 40551c: c1 f8 02 sar $0x2,%eax + 40551f: 01 d0 add %edx,%eax + 405521: 89 c2 mov %eax,%edx + 405523: c1 fa 04 sar $0x4,%edx + 405526: 01 d0 add %edx,%eax + 405528: 25 0f 0f 00 00 and $0xf0f,%eax + 40552d: 89 c1 mov %eax,%ecx + 40552f: c1 f9 08 sar $0x8,%ecx + 405532: 01 c1 add %eax,%ecx + 405534: b8 01 00 00 00 mov $0x1,%eax + 405539: d3 e0 shl %cl,%eax + 40553b: 48 63 f8 movslq %eax,%rdi + 40553e: 48 c1 e7 04 shl $0x4,%rdi + 405542: 4c 0f af e7 imul %rdi,%r12 + 405546: 49 8d 7c 24 28 lea 0x28(%r12),%rdi + 40554b: e8 c0 84 01 00 callq 41da10 <__libc_malloc> + 405550: 48 85 c0 test %rax,%rax + 405553: 49 89 c4 mov %rax,%r12 + 405556: 0f 84 26 03 00 00 je 405882 <_nl_make_l10nflist+0x5a2> + 40555c: 48 8b 5c 24 18 mov 0x18(%rsp),%rbx + 405561: 4c 8b 74 24 28 mov 0x28(%rsp),%r14 + 405566: 4c 89 28 mov %r13,(%rax) + 405569: 45 31 ed xor %r13d,%r13d + 40556c: 0f 1f 40 00 nopl 0x0(%rax) + 405570: 4c 89 f7 mov %r14,%rdi + 405573: 49 83 c5 01 add $0x1,%r13 + 405577: e8 d4 e0 01 00 callq 423650 + 40557c: 48 29 c3 sub %rax,%rbx + 40557f: 4d 8d 74 06 01 lea 0x1(%r14,%rax,1),%r14 + 405584: 48 83 eb 01 sub $0x1,%rbx + 405588: 75 e6 jne 405570 <_nl_make_l10nflist+0x290> + 40558a: 49 83 fd 01 cmp $0x1,%r13 + 40558e: b8 01 00 00 00 mov $0x1,%eax + 405593: 0f 84 fe 01 00 00 je 405797 <_nl_make_l10nflist+0x4b7> + 405599: 48 85 ed test %rbp,%rbp + 40559c: 41 89 44 24 08 mov %eax,0x8(%r12) + 4055a1: 49 c7 44 24 10 00 00 movq $0x0,0x10(%r12) + 4055a8: 00 00 + 4055aa: 0f 84 83 02 00 00 je 405833 <_nl_make_l10nflist+0x553> + 4055b0: 48 8b 45 18 mov 0x18(%rbp),%rax + 4055b4: 49 89 44 24 18 mov %rax,0x18(%r12) + 4055b9: 4c 89 65 18 mov %r12,0x18(%rbp) + 4055bd: 48 8b 44 24 18 mov 0x18(%rsp),%rax + 4055c2: 48 85 c0 test %rax,%rax + 4055c5: 0f 84 7f 02 00 00 je 40584a <_nl_make_l10nflist+0x56a> + 4055cb: 4c 8b 6c 24 28 mov 0x28(%rsp),%r13 + 4055d0: 48 89 c3 mov %rax,%rbx + 4055d3: 31 ed xor %ebp,%ebp + 4055d5: 0f 1f 00 nopl (%rax) + 4055d8: 4c 89 ef mov %r13,%rdi + 4055db: 48 83 c5 01 add $0x1,%rbp + 4055df: e8 6c e0 01 00 callq 423650 + 4055e4: 48 29 c3 sub %rax,%rbx + 4055e7: 4d 8d 6c 05 01 lea 0x1(%r13,%rax,1),%r13 + 4055ec: 48 83 eb 01 sub $0x1,%rbx + 4055f0: 75 e6 jne 4055d8 <_nl_make_l10nflist+0x2f8> + 4055f2: 44 8b 6c 24 34 mov 0x34(%rsp),%r13d + 4055f7: 31 c0 xor %eax,%eax + 4055f9: 48 83 fd 01 cmp $0x1,%rbp + 4055fd: 0f 94 c0 sete %al + 405600: 41 29 c5 sub %eax,%r13d + 405603: 45 85 ed test %r13d,%r13d + 405606: 0f 88 c4 00 00 00 js 4056d0 <_nl_make_l10nflist+0x3f0> + 40560c: 8b 44 24 34 mov 0x34(%rsp),%eax + 405610: 48 8b 4c 24 18 mov 0x18(%rsp),%rcx + 405615: 31 ed xor %ebp,%ebp + 405617: f7 d0 not %eax + 405619: 89 44 24 20 mov %eax,0x20(%rsp) + 40561d: 48 8b 44 24 28 mov 0x28(%rsp),%rax + 405622: 4c 8d 34 08 lea (%rax,%rcx,1),%r14 + 405626: eb 16 jmp 40563e <_nl_make_l10nflist+0x35e> + 405628: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 40562f: 00 + 405630: 41 83 ed 01 sub $0x1,%r13d + 405634: 41 83 fd ff cmp $0xffffffff,%r13d + 405638: 0f 84 9a 00 00 00 je 4056d8 <_nl_make_l10nflist+0x3f8> + 40563e: 44 85 6c 24 20 test %r13d,0x20(%rsp) + 405643: 75 eb jne 405630 <_nl_make_l10nflist+0x350> + 405645: 48 83 7c 24 18 00 cmpq $0x0,0x18(%rsp) + 40564b: 74 e3 je 405630 <_nl_make_l10nflist+0x350> + 40564d: 48 8b 5c 24 28 mov 0x28(%rsp),%rbx + 405652: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 405658: 48 89 df mov %rbx,%rdi + 40565b: 48 83 c5 01 add $0x1,%rbp + 40565f: e8 ec df 01 00 callq 423650 + 405664: 48 83 ec 08 sub $0x8,%rsp + 405668: 48 8d 50 01 lea 0x1(%rax),%rdx + 40566c: 44 89 e9 mov %r13d,%ecx + 40566f: 6a 01 pushq $0x1 + 405671: 41 57 push %r15 + 405673: 48 89 de mov %rbx,%rsi + 405676: ff b4 24 a8 00 00 00 pushq 0xa8(%rsp) + 40567d: ff b4 24 a8 00 00 00 pushq 0xa8(%rsp) + 405684: ff b4 24 a8 00 00 00 pushq 0xa8(%rsp) + 40568b: 4c 8b 4c 24 40 mov 0x40(%rsp),%r9 + 405690: 4c 8b 44 24 30 mov 0x30(%rsp),%r8 + 405695: 48 8b 7c 24 38 mov 0x38(%rsp),%rdi + 40569a: e8 41 fc ff ff callq 4052e0 <_nl_make_l10nflist> + 40569f: 48 83 c4 30 add $0x30,%rsp + 4056a3: 49 39 de cmp %rbx,%r14 + 4056a6: 49 89 44 ec 18 mov %rax,0x18(%r12,%rbp,8) + 4056ab: 76 83 jbe 405630 <_nl_make_l10nflist+0x350> + 4056ad: 31 f6 xor %esi,%esi + 4056af: 48 89 df mov %rbx,%rdi + 4056b2: e8 19 73 02 00 callq 42c9d0 <__rawmemchr> + 4056b7: 48 8d 58 01 lea 0x1(%rax),%rbx + 4056bb: 4c 39 f3 cmp %r14,%rbx + 4056be: 0f 83 6c ff ff ff jae 405630 <_nl_make_l10nflist+0x350> + 4056c4: 48 85 db test %rbx,%rbx + 4056c7: 75 8f jne 405658 <_nl_make_l10nflist+0x378> + 4056c9: e9 62 ff ff ff jmpq 405630 <_nl_make_l10nflist+0x350> + 4056ce: 66 90 xchg %ax,%ax + 4056d0: 31 ed xor %ebp,%ebp + 4056d2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4056d8: bf fe 11 4a 00 mov $0x4a11fe,%edi + 4056dd: b9 0b 00 00 00 mov $0xb,%ecx + 4056e2: 4c 89 fe mov %r15,%rsi + 4056e5: f3 a6 repz cmpsb %es:(%rdi),%ds:(%rsi) + 4056e7: 0f 85 87 00 00 00 jne 405774 <_nl_make_l10nflist+0x494> + 4056ed: 8b 5c 24 34 mov 0x34(%rsp),%ebx + 4056f1: 85 db test %ebx,%ebx + 4056f3: 78 7f js 405774 <_nl_make_l10nflist+0x494> + 4056f5: 41 89 dd mov %ebx,%r13d + 4056f8: 41 f7 d5 not %r13d + 4056fb: 45 89 ee mov %r13d,%r14d + 4056fe: 49 89 ed mov %rbp,%r13 + 405701: 4c 89 fd mov %r15,%rbp + 405704: eb 12 jmp 405718 <_nl_make_l10nflist+0x438> + 405706: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 40570d: 00 00 00 + 405710: 83 eb 01 sub $0x1,%ebx + 405713: 83 fb ff cmp $0xffffffff,%ebx + 405716: 74 59 je 405771 <_nl_make_l10nflist+0x491> + 405718: 44 85 f3 test %r14d,%ebx + 40571b: 75 f3 jne 405710 <_nl_make_l10nflist+0x430> + 40571d: 48 83 ec 08 sub $0x8,%rsp + 405721: 89 d9 mov %ebx,%ecx + 405723: 4d 8d 7d 01 lea 0x1(%r13),%r15 + 405727: 6a 01 pushq $0x1 + 405729: 55 push %rbp + 40572a: ba 1b 00 00 00 mov $0x1b,%edx + 40572f: ff b4 24 a8 00 00 00 pushq 0xa8(%rsp) + 405736: ff b4 24 a8 00 00 00 pushq 0xa8(%rsp) + 40573d: be 0a 12 4a 00 mov $0x4a120a,%esi + 405742: ff b4 24 a8 00 00 00 pushq 0xa8(%rsp) + 405749: 4c 8b 4c 24 40 mov 0x40(%rsp),%r9 + 40574e: 83 eb 01 sub $0x1,%ebx + 405751: 4c 8b 44 24 30 mov 0x30(%rsp),%r8 + 405756: 48 8b 7c 24 38 mov 0x38(%rsp),%rdi + 40575b: e8 80 fb ff ff callq 4052e0 <_nl_make_l10nflist> + 405760: 48 83 c4 30 add $0x30,%rsp + 405764: 83 fb ff cmp $0xffffffff,%ebx + 405767: 4b 89 44 ec 20 mov %rax,0x20(%r12,%r13,8) + 40576c: 4d 89 fd mov %r15,%r13 + 40576f: 75 a7 jne 405718 <_nl_make_l10nflist+0x438> + 405771: 4c 89 ed mov %r13,%rbp + 405774: 49 c7 44 ec 20 00 00 movq $0x0,0x20(%r12,%rbp,8) + 40577b: 00 00 + 40577d: 4c 89 e0 mov %r12,%rax + 405780: 48 83 c4 48 add $0x48,%rsp + 405784: 5b pop %rbx + 405785: 5d pop %rbp + 405786: 41 5c pop %r12 + 405788: 41 5d pop %r13 + 40578a: 41 5e pop %r14 + 40578c: 41 5f pop %r15 + 40578e: c3 retq + 40578f: 90 nop + 405790: 31 ed xor %ebp,%ebp + 405792: e9 a9 fb ff ff jmpq 405340 <_nl_make_l10nflist+0x60> + 405797: 8b 44 24 34 mov 0x34(%rsp),%eax + 40579b: 83 e0 03 and $0x3,%eax + 40579e: 83 f8 03 cmp $0x3,%eax + 4057a1: 0f 94 c0 sete %al + 4057a4: 0f b6 c0 movzbl %al,%eax + 4057a7: e9 ed fd ff ff jmpq 405599 <_nl_make_l10nflist+0x2b9> + 4057ac: 48 8b b4 24 90 00 00 mov 0x90(%rsp),%rsi + 4057b3: 00 + 4057b4: 48 8d 78 01 lea 0x1(%rax),%rdi + 4057b8: c6 00 40 movb $0x40,(%rax) + 4057bb: e8 50 ab ff ff callq 400310 <__rela_iplt_end+0x48> + 4057c0: e9 91 fc ff ff jmpq 405456 <_nl_make_l10nflist+0x176> + 4057c5: 48 8b b4 24 88 00 00 mov 0x88(%rsp),%rsi + 4057cc: 00 + 4057cd: 48 8d 78 01 lea 0x1(%rax),%rdi + 4057d1: c6 00 2e movb $0x2e,(%rax) + 4057d4: e8 37 ab ff ff callq 400310 <__rela_iplt_end+0x48> + 4057d9: e9 6c fc ff ff jmpq 40544a <_nl_make_l10nflist+0x16a> + 4057de: 48 8b b4 24 80 00 00 mov 0x80(%rsp),%rsi + 4057e5: 00 + 4057e6: 48 8d 78 01 lea 0x1(%rax),%rdi + 4057ea: c6 00 2e movb $0x2e,(%rax) + 4057ed: e8 1e ab ff ff callq 400310 <__rela_iplt_end+0x48> + 4057f2: e9 47 fc ff ff jmpq 40543e <_nl_make_l10nflist+0x15e> + 4057f7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 4057fe: 00 00 + 405800: 48 8b 74 24 10 mov 0x10(%rsp),%rsi + 405805: 48 8d 78 01 lea 0x1(%rax),%rdi + 405809: c6 00 5f movb $0x5f,(%rax) + 40580c: e8 ff aa ff ff callq 400310 <__rela_iplt_end+0x48> + 405811: e9 1c fc ff ff jmpq 405432 <_nl_make_l10nflist+0x152> + 405816: 45 31 e4 xor %r12d,%r12d + 405819: 4c 89 ef mov %r13,%rdi + 40581c: e8 8f 85 01 00 callq 41ddb0 <__cfree> + 405821: 48 83 c4 48 add $0x48,%rsp + 405825: 4c 89 e0 mov %r12,%rax + 405828: 5b pop %rbx + 405829: 5d pop %rbp + 40582a: 41 5c pop %r12 + 40582c: 41 5d pop %r13 + 40582e: 41 5e pop %r14 + 405830: 41 5f pop %r15 + 405832: c3 retq + 405833: 48 8b 44 24 20 mov 0x20(%rsp),%rax + 405838: 49 89 44 24 18 mov %rax,0x18(%r12) + 40583d: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 405842: 4c 89 20 mov %r12,(%rax) + 405845: e9 73 fd ff ff jmpq 4055bd <_nl_make_l10nflist+0x2dd> + 40584a: 44 8b 6c 24 34 mov 0x34(%rsp),%r13d + 40584f: e9 af fd ff ff jmpq 405603 <_nl_make_l10nflist+0x323> + 405854: bf 28 00 00 00 mov $0x28,%edi + 405859: e8 b2 81 01 00 callq 41da10 <__libc_malloc> + 40585e: 48 85 c0 test %rax,%rax + 405861: 49 89 c4 mov %rax,%r12 + 405864: 74 1c je 405882 <_nl_make_l10nflist+0x5a2> + 405866: 4d 89 2c 24 mov %r13,(%r12) + 40586a: b8 01 00 00 00 mov $0x1,%eax + 40586f: e9 25 fd ff ff jmpq 405599 <_nl_make_l10nflist+0x2b9> + 405874: 31 c0 xor %eax,%eax + 405876: e9 05 ff ff ff jmpq 405780 <_nl_make_l10nflist+0x4a0> + 40587b: 31 ed xor %ebp,%ebp + 40587d: e9 2e fc ff ff jmpq 4054b0 <_nl_make_l10nflist+0x1d0> + 405882: 4c 89 ef mov %r13,%rdi + 405885: e8 26 85 01 00 callq 41ddb0 <__cfree> + 40588a: 31 c0 xor %eax,%eax + 40588c: e9 ef fe ff ff jmpq 405780 <_nl_make_l10nflist+0x4a0> + 405891: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 405896: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 40589d: 00 00 00 + +00000000004058a0 <_nl_normalize_codeset>: + 4058a0: 41 55 push %r13 + 4058a2: 41 54 push %r12 + 4058a4: 49 89 f5 mov %rsi,%r13 + 4058a7: 55 push %rbp + 4058a8: 53 push %rbx + 4058a9: 48 89 fb mov %rdi,%rbx + 4058ac: 48 83 ec 08 sub $0x8,%rsp + 4058b0: 48 85 f6 test %rsi,%rsi + 4058b3: 0f 84 e4 00 00 00 je 40599d <_nl_normalize_codeset+0xfd> + 4058b9: 48 8b 2d 28 ce 0a 00 mov 0xace28(%rip),%rbp # 4b26e8 <_nl_C_locobj+0x68> + 4058c0: 4c 8d 24 37 lea (%rdi,%rsi,1),%r12 + 4058c4: 48 89 fa mov %rdi,%rdx + 4058c7: 41 b8 01 00 00 00 mov $0x1,%r8d + 4058cd: 31 ff xor %edi,%edi + 4058cf: 31 f6 xor %esi,%esi + 4058d1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4058d8: 0f b6 0a movzbl (%rdx),%ecx + 4058db: f6 44 4d 00 08 testb $0x8,0x0(%rbp,%rcx,2) + 4058e0: 48 89 c8 mov %rcx,%rax + 4058e3: 74 0e je 4058f3 <_nl_normalize_codeset+0x53> + 4058e5: 83 e8 30 sub $0x30,%eax + 4058e8: 48 83 c7 01 add $0x1,%rdi + 4058ec: 83 f8 0a cmp $0xa,%eax + 4058ef: 44 0f 43 c6 cmovae %esi,%r8d + 4058f3: 48 83 c2 01 add $0x1,%rdx + 4058f7: 4c 39 e2 cmp %r12,%rdx + 4058fa: 75 dc jne 4058d8 <_nl_normalize_codeset+0x38> + 4058fc: 45 85 c0 test %r8d,%r8d + 4058ff: 75 6f jne 405970 <_nl_normalize_codeset+0xd0> + 405901: 48 83 c7 01 add $0x1,%rdi + 405905: e8 06 81 01 00 callq 41da10 <__libc_malloc> + 40590a: 48 85 c0 test %rax,%rax + 40590d: 74 51 je 405960 <_nl_normalize_codeset+0xc0> + 40590f: 49 89 c0 mov %rax,%r8 + 405912: 48 8b 35 d7 cd 0a 00 mov 0xacdd7(%rip),%rsi # 4b26f0 <_nl_C_locobj+0x70> + 405919: 48 89 df mov %rbx,%rdi + 40591c: eb 16 jmp 405934 <_nl_normalize_codeset+0x94> + 40591e: 66 90 xchg %ax,%ax + 405920: 8b 14 8e mov (%rsi,%rcx,4),%edx + 405923: 49 83 c0 01 add $0x1,%r8 + 405927: 41 88 50 ff mov %dl,-0x1(%r8) + 40592b: 48 83 c7 01 add $0x1,%rdi + 40592f: 49 39 fc cmp %rdi,%r12 + 405932: 74 28 je 40595c <_nl_normalize_codeset+0xbc> + 405934: 0f b6 0f movzbl (%rdi),%ecx + 405937: f6 44 4d 01 04 testb $0x4,0x1(%rbp,%rcx,2) + 40593c: 48 89 ca mov %rcx,%rdx + 40593f: 75 df jne 405920 <_nl_normalize_codeset+0x80> + 405941: 0f b6 c9 movzbl %cl,%ecx + 405944: 83 e9 30 sub $0x30,%ecx + 405947: 83 f9 09 cmp $0x9,%ecx + 40594a: 77 df ja 40592b <_nl_normalize_codeset+0x8b> + 40594c: 48 83 c7 01 add $0x1,%rdi + 405950: 41 88 10 mov %dl,(%r8) + 405953: 49 83 c0 01 add $0x1,%r8 + 405957: 49 39 fc cmp %rdi,%r12 + 40595a: 75 d8 jne 405934 <_nl_normalize_codeset+0x94> + 40595c: 41 c6 00 00 movb $0x0,(%r8) + 405960: 48 83 c4 08 add $0x8,%rsp + 405964: 5b pop %rbx + 405965: 5d pop %rbp + 405966: 41 5c pop %r12 + 405968: 41 5d pop %r13 + 40596a: c3 retq + 40596b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 405970: 48 83 c7 04 add $0x4,%rdi + 405974: e8 97 80 01 00 callq 41da10 <__libc_malloc> + 405979: 48 85 c0 test %rax,%rax + 40597c: 74 e2 je 405960 <_nl_normalize_codeset+0xc0> + 40597e: 4d 85 ed test %r13,%r13 + 405981: c7 00 69 73 6f 00 movl $0x6f7369,(%rax) + 405987: 4c 8d 40 03 lea 0x3(%rax),%r8 + 40598b: 74 cf je 40595c <_nl_normalize_codeset+0xbc> + 40598d: 48 8b 2d 54 cd 0a 00 mov 0xacd54(%rip),%rbp # 4b26e8 <_nl_C_locobj+0x68> + 405994: 4e 8d 24 2b lea (%rbx,%r13,1),%r12 + 405998: e9 75 ff ff ff jmpq 405912 <_nl_normalize_codeset+0x72> + 40599d: bf 04 00 00 00 mov $0x4,%edi + 4059a2: e8 69 80 01 00 callq 41da10 <__libc_malloc> + 4059a7: 48 85 c0 test %rax,%rax + 4059aa: 75 d2 jne 40597e <_nl_normalize_codeset+0xde> + 4059ac: eb b2 jmp 405960 <_nl_normalize_codeset+0xc0> + 4059ae: 66 90 xchg %ax,%ax + +00000000004059b0 <_nl_explode_name>: + 4059b0: 41 56 push %r14 + 4059b2: 41 55 push %r13 + 4059b4: 41 54 push %r12 + 4059b6: 55 push %rbp + 4059b7: 53 push %rbx + 4059b8: 48 83 ec 20 sub $0x20,%rsp + 4059bc: 48 c7 02 00 00 00 00 movq $0x0,(%rdx) + 4059c3: 48 c7 01 00 00 00 00 movq $0x0,(%rcx) + 4059ca: 49 c7 00 00 00 00 00 movq $0x0,(%r8) + 4059d1: 49 c7 01 00 00 00 00 movq $0x0,(%r9) + 4059d8: 48 89 3e mov %rdi,(%rsi) + 4059db: 0f b6 07 movzbl (%rdi),%eax + 4059de: a8 bf test $0xbf,%al + 4059e0: 0f 84 aa 01 00 00 je 405b90 <_nl_explode_name+0x1e0> + 4059e6: 3c 5f cmp $0x5f,%al + 4059e8: 0f 84 a2 01 00 00 je 405b90 <_nl_explode_name+0x1e0> + 4059ee: 3c 2e cmp $0x2e,%al + 4059f0: 0f 84 9a 01 00 00 je 405b90 <_nl_explode_name+0x1e0> + 4059f6: 48 89 fb mov %rdi,%rbx + 4059f9: eb 1f jmp 405a1a <_nl_explode_name+0x6a> + 4059fb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 405a00: 40 80 fe 5f cmp $0x5f,%sil + 405a04: 74 20 je 405a26 <_nl_explode_name+0x76> + 405a06: 40 80 fe 40 cmp $0x40,%sil + 405a0a: 0f 84 10 01 00 00 je 405b20 <_nl_explode_name+0x170> + 405a10: 40 80 fe 2e cmp $0x2e,%sil + 405a14: 0f 84 06 01 00 00 je 405b20 <_nl_explode_name+0x170> + 405a1a: 48 83 c3 01 add $0x1,%rbx + 405a1e: 0f b6 33 movzbl (%rbx),%esi + 405a21: 40 84 f6 test %sil,%sil + 405a24: 75 da jne 405a00 <_nl_explode_name+0x50> + 405a26: 48 39 df cmp %rbx,%rdi + 405a29: 0f 84 61 01 00 00 je 405b90 <_nl_explode_name+0x1e0> + 405a2f: 40 80 fe 5f cmp $0x5f,%sil + 405a33: 0f 85 ec 00 00 00 jne 405b25 <_nl_explode_name+0x175> + 405a39: 48 8d 43 01 lea 0x1(%rbx),%rax + 405a3d: c6 03 00 movb $0x0,(%rbx) + 405a40: 48 89 01 mov %rax,(%rcx) + 405a43: 0f b6 73 01 movzbl 0x1(%rbx),%esi + 405a47: 40 f6 c6 bf test $0xbf,%sil + 405a4b: 75 10 jne 405a5d <_nl_explode_name+0xad> + 405a4d: eb 14 jmp 405a63 <_nl_explode_name+0xb3> + 405a4f: 90 nop + 405a50: 48 83 c0 01 add $0x1,%rax + 405a54: 0f b6 30 movzbl (%rax),%esi + 405a57: 40 f6 c6 bf test $0xbf,%sil + 405a5b: 74 06 je 405a63 <_nl_explode_name+0xb3> + 405a5d: 40 80 fe 2e cmp $0x2e,%sil + 405a61: 75 ed jne 405a50 <_nl_explode_name+0xa0> + 405a63: 40 80 fe 2e cmp $0x2e,%sil + 405a67: 48 89 c3 mov %rax,%rbx + 405a6a: 41 bd 06 00 00 00 mov $0x6,%r13d + 405a70: bd 04 00 00 00 mov $0x4,%ebp + 405a75: 0f 85 bc 00 00 00 jne 405b37 <_nl_explode_name+0x187> + 405a7b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 405a80: 48 8d 7b 01 lea 0x1(%rbx),%rdi + 405a84: c6 03 00 movb $0x0,(%rbx) + 405a87: 49 89 38 mov %rdi,(%r8) + 405a8a: 0f b6 73 01 movzbl 0x1(%rbx),%esi + 405a8e: 40 f6 c6 bf test $0xbf,%sil + 405a92: 0f 84 5a 01 00 00 je 405bf2 <_nl_explode_name+0x242> + 405a98: 49 89 fc mov %rdi,%r12 + 405a9b: eb 06 jmp 405aa3 <_nl_explode_name+0xf3> + 405a9d: 0f 1f 00 nopl (%rax) + 405aa0: 49 89 dc mov %rbx,%r12 + 405aa3: 41 f6 44 24 01 bf testb $0xbf,0x1(%r12) + 405aa9: 49 8d 5c 24 01 lea 0x1(%r12),%rbx + 405aae: 75 f0 jne 405aa0 <_nl_explode_name+0xf0> + 405ab0: 48 39 df cmp %rbx,%rdi + 405ab3: 4c 89 0c 24 mov %r9,(%rsp) + 405ab7: 0f 84 40 01 00 00 je 405bfd <_nl_explode_name+0x24d> + 405abd: 48 89 de mov %rbx,%rsi + 405ac0: 4c 89 44 24 18 mov %r8,0x18(%rsp) + 405ac5: 48 89 4c 24 10 mov %rcx,0x10(%rsp) + 405aca: 48 29 fe sub %rdi,%rsi + 405acd: 48 89 54 24 08 mov %rdx,0x8(%rsp) + 405ad2: e8 c9 fd ff ff callq 4058a0 <_nl_normalize_codeset> + 405ad7: 4c 8b 0c 24 mov (%rsp),%r9 + 405adb: 48 85 c0 test %rax,%rax + 405ade: 49 89 c6 mov %rax,%r14 + 405ae1: 49 89 01 mov %rax,(%r9) + 405ae4: 0f 84 1b 01 00 00 je 405c05 <_nl_explode_name+0x255> + 405aea: 4c 8b 44 24 18 mov 0x18(%rsp),%r8 + 405aef: 48 89 c6 mov %rax,%rsi + 405af2: 49 8b 38 mov (%r8),%rdi + 405af5: 4c 89 04 24 mov %r8,(%rsp) + 405af9: e8 62 a8 ff ff callq 400360 <__rela_iplt_end+0x98> + 405afe: 85 c0 test %eax,%eax + 405b00: 4c 8b 04 24 mov (%rsp),%r8 + 405b04: 48 8b 54 24 08 mov 0x8(%rsp),%rdx + 405b09: 48 8b 4c 24 10 mov 0x10(%rsp),%rcx + 405b0e: 0f 84 ac 00 00 00 je 405bc0 <_nl_explode_name+0x210> + 405b14: 83 cd 03 or $0x3,%ebp + 405b17: 41 0f b6 74 24 01 movzbl 0x1(%r12),%esi + 405b1d: eb 18 jmp 405b37 <_nl_explode_name+0x187> + 405b1f: 90 nop + 405b20: 48 39 df cmp %rbx,%rdi + 405b23: 74 6b je 405b90 <_nl_explode_name+0x1e0> + 405b25: 31 ed xor %ebp,%ebp + 405b27: 40 80 fe 2e cmp $0x2e,%sil + 405b2b: 41 bd 02 00 00 00 mov $0x2,%r13d + 405b31: 0f 84 49 ff ff ff je 405a80 <_nl_explode_name+0xd0> + 405b37: 40 80 fe 40 cmp $0x40,%sil + 405b3b: 74 3b je 405b78 <_nl_explode_name+0x1c8> + 405b3d: 48 8b 01 mov (%rcx),%rax + 405b40: 48 85 c0 test %rax,%rax + 405b43: 74 0b je 405b50 <_nl_explode_name+0x1a0> + 405b45: 89 ea mov %ebp,%edx + 405b47: 83 e2 fb and $0xfffffffb,%edx + 405b4a: 80 38 00 cmpb $0x0,(%rax) + 405b4d: 0f 44 ea cmove %edx,%ebp + 405b50: 49 8b 10 mov (%r8),%rdx + 405b53: 89 e8 mov %ebp,%eax + 405b55: 48 85 d2 test %rdx,%rdx + 405b58: 74 0b je 405b65 <_nl_explode_name+0x1b5> + 405b5a: 89 e9 mov %ebp,%ecx + 405b5c: 83 e1 fd and $0xfffffffd,%ecx + 405b5f: 80 3a 00 cmpb $0x0,(%rdx) + 405b62: 0f 44 c1 cmove %ecx,%eax + 405b65: 48 83 c4 20 add $0x20,%rsp + 405b69: 5b pop %rbx + 405b6a: 5d pop %rbp + 405b6b: 41 5c pop %r12 + 405b6d: 41 5d pop %r13 + 405b6f: 41 5e pop %r14 + 405b71: c3 retq + 405b72: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 405b78: 48 8d 43 01 lea 0x1(%rbx),%rax + 405b7c: c6 03 00 movb $0x0,(%rbx) + 405b7f: 48 89 02 mov %rax,(%rdx) + 405b82: 89 e8 mov %ebp,%eax + 405b84: 83 c8 08 or $0x8,%eax + 405b87: 80 7b 01 00 cmpb $0x0,0x1(%rbx) + 405b8b: 0f 45 e8 cmovne %eax,%ebp + 405b8e: eb ad jmp 405b3d <_nl_explode_name+0x18d> + 405b90: 31 f6 xor %esi,%esi + 405b92: 4c 89 44 24 10 mov %r8,0x10(%rsp) + 405b97: 48 89 4c 24 08 mov %rcx,0x8(%rsp) + 405b9c: 48 89 14 24 mov %rdx,(%rsp) + 405ba0: 31 ed xor %ebp,%ebp + 405ba2: e8 29 6e 02 00 callq 42c9d0 <__rawmemchr> + 405ba7: 48 8b 14 24 mov (%rsp),%rdx + 405bab: 48 89 c3 mov %rax,%rbx + 405bae: 0f b6 30 movzbl (%rax),%esi + 405bb1: 48 8b 4c 24 08 mov 0x8(%rsp),%rcx + 405bb6: 4c 8b 44 24 10 mov 0x10(%rsp),%r8 + 405bbb: e9 77 ff ff ff jmpq 405b37 <_nl_explode_name+0x187> + 405bc0: 4c 89 f7 mov %r14,%rdi + 405bc3: 4c 89 44 24 10 mov %r8,0x10(%rsp) + 405bc8: 48 89 4c 24 08 mov %rcx,0x8(%rsp) + 405bcd: 48 89 14 24 mov %rdx,(%rsp) + 405bd1: 44 89 ed mov %r13d,%ebp + 405bd4: e8 d7 81 01 00 callq 41ddb0 <__cfree> + 405bd9: 41 0f b6 74 24 01 movzbl 0x1(%r12),%esi + 405bdf: 48 8b 14 24 mov (%rsp),%rdx + 405be3: 48 8b 4c 24 08 mov 0x8(%rsp),%rcx + 405be8: 4c 8b 44 24 10 mov 0x10(%rsp),%r8 + 405bed: e9 45 ff ff ff jmpq 405b37 <_nl_explode_name+0x187> + 405bf2: 44 89 ed mov %r13d,%ebp + 405bf5: 48 89 fb mov %rdi,%rbx + 405bf8: e9 3a ff ff ff jmpq 405b37 <_nl_explode_name+0x187> + 405bfd: 44 89 ed mov %r13d,%ebp + 405c00: e9 32 ff ff ff jmpq 405b37 <_nl_explode_name+0x187> + 405c05: b8 ff ff ff ff mov $0xffffffff,%eax + 405c0a: e9 56 ff ff ff jmpq 405b65 <_nl_explode_name+0x1b5> + 405c0f: 90 nop + +0000000000405c10 <__gettext_free_exp>: + 405c10: 48 85 ff test %rdi,%rdi + 405c13: 0f 84 af 06 00 00 je 4062c8 <__gettext_free_exp+0x6b8> + 405c19: 41 57 push %r15 + 405c1b: 41 56 push %r14 + 405c1d: 41 55 push %r13 + 405c1f: 41 54 push %r12 + 405c21: 55 push %rbp + 405c22: 53 push %rbx + 405c23: 48 89 fb mov %rdi,%rbx + 405c26: 48 83 ec 08 sub $0x8,%rsp + 405c2a: 8b 07 mov (%rdi),%eax + 405c2c: 83 f8 02 cmp $0x2,%eax + 405c2f: 74 56 je 405c87 <__gettext_free_exp+0x77> + 405c31: 83 f8 03 cmp $0x3,%eax + 405c34: 74 22 je 405c58 <__gettext_free_exp+0x48> + 405c36: 83 f8 01 cmp $0x1,%eax + 405c39: 74 7b je 405cb6 <__gettext_free_exp+0xa6> + 405c3b: 48 83 c4 08 add $0x8,%rsp + 405c3f: 48 89 df mov %rbx,%rdi + 405c42: 5b pop %rbx + 405c43: 5d pop %rbp + 405c44: 41 5c pop %r12 + 405c46: 41 5d pop %r13 + 405c48: 41 5e pop %r14 + 405c4a: 41 5f pop %r15 + 405c4c: e9 5f 81 01 00 jmpq 41ddb0 <__cfree> + 405c51: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 405c58: 48 8b 6f 18 mov 0x18(%rdi),%rbp + 405c5c: 48 85 ed test %rbp,%rbp + 405c5f: 74 26 je 405c87 <__gettext_free_exp+0x77> + 405c61: 8b 45 00 mov 0x0(%rbp),%eax + 405c64: 83 f8 02 cmp $0x2,%eax + 405c67: 0f 84 6c 03 00 00 je 405fd9 <__gettext_free_exp+0x3c9> + 405c6d: 83 f8 03 cmp $0x3,%eax + 405c70: 0f 84 5a 03 00 00 je 405fd0 <__gettext_free_exp+0x3c0> + 405c76: 83 f8 01 cmp $0x1,%eax + 405c79: 0f 84 63 03 00 00 je 405fe2 <__gettext_free_exp+0x3d2> + 405c7f: 48 89 ef mov %rbp,%rdi + 405c82: e8 29 81 01 00 callq 41ddb0 <__cfree> + 405c87: 48 8b 6b 10 mov 0x10(%rbx),%rbp + 405c8b: 48 85 ed test %rbp,%rbp + 405c8e: 74 26 je 405cb6 <__gettext_free_exp+0xa6> + 405c90: 8b 45 00 mov 0x0(%rbp),%eax + 405c93: 83 f8 02 cmp $0x2,%eax + 405c96: 0f 84 5d 01 00 00 je 405df9 <__gettext_free_exp+0x1e9> + 405c9c: 83 f8 03 cmp $0x3,%eax + 405c9f: 0f 84 4b 01 00 00 je 405df0 <__gettext_free_exp+0x1e0> + 405ca5: 83 f8 01 cmp $0x1,%eax + 405ca8: 0f 84 7b 01 00 00 je 405e29 <__gettext_free_exp+0x219> + 405cae: 48 89 ef mov %rbp,%rdi + 405cb1: e8 fa 80 01 00 callq 41ddb0 <__cfree> + 405cb6: 48 8b 6b 08 mov 0x8(%rbx),%rbp + 405cba: 48 85 ed test %rbp,%rbp + 405cbd: 0f 84 78 ff ff ff je 405c3b <__gettext_free_exp+0x2b> + 405cc3: 8b 45 00 mov 0x0(%rbp),%eax + 405cc6: 83 f8 02 cmp $0x2,%eax + 405cc9: 74 4b je 405d16 <__gettext_free_exp+0x106> + 405ccb: 83 f8 03 cmp $0x3,%eax + 405cce: 0f 84 cc 03 00 00 je 4060a0 <__gettext_free_exp+0x490> + 405cd4: 83 f8 01 cmp $0x1,%eax + 405cd7: 74 6d je 405d46 <__gettext_free_exp+0x136> + 405cd9: 48 89 ef mov %rbp,%rdi + 405cdc: e8 cf 80 01 00 callq 41ddb0 <__cfree> + 405ce1: e9 55 ff ff ff jmpq 405c3b <__gettext_free_exp+0x2b> + 405ce6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 405ced: 00 00 00 + 405cf0: 49 8b 7c 24 18 mov 0x18(%r12),%rdi + 405cf5: e8 16 ff ff ff callq 405c10 <__gettext_free_exp> + 405cfa: 49 8b 7c 24 10 mov 0x10(%r12),%rdi + 405cff: e8 0c ff ff ff callq 405c10 <__gettext_free_exp> + 405d04: 49 8b 7c 24 08 mov 0x8(%r12),%rdi + 405d09: e8 02 ff ff ff callq 405c10 <__gettext_free_exp> + 405d0e: 4c 89 e7 mov %r12,%rdi + 405d11: e8 9a 80 01 00 callq 41ddb0 <__cfree> + 405d16: 4c 8b 65 10 mov 0x10(%rbp),%r12 + 405d1a: 4d 85 e4 test %r12,%r12 + 405d1d: 74 27 je 405d46 <__gettext_free_exp+0x136> + 405d1f: 41 8b 04 24 mov (%r12),%eax + 405d23: 83 f8 02 cmp $0x2,%eax + 405d26: 0f 84 36 02 00 00 je 405f62 <__gettext_free_exp+0x352> + 405d2c: 83 f8 03 cmp $0x3,%eax + 405d2f: 0f 84 23 02 00 00 je 405f58 <__gettext_free_exp+0x348> + 405d35: 83 f8 01 cmp $0x1,%eax + 405d38: 0f 84 55 02 00 00 je 405f93 <__gettext_free_exp+0x383> + 405d3e: 4c 89 e7 mov %r12,%rdi + 405d41: e8 6a 80 01 00 callq 41ddb0 <__cfree> + 405d46: 4c 8b 65 08 mov 0x8(%rbp),%r12 + 405d4a: 4d 85 e4 test %r12,%r12 + 405d4d: 74 8a je 405cd9 <__gettext_free_exp+0xc9> + 405d4f: 41 8b 04 24 mov (%r12),%eax + 405d53: 83 f8 02 cmp $0x2,%eax + 405d56: 74 22 je 405d7a <__gettext_free_exp+0x16a> + 405d58: 83 f8 03 cmp $0x3,%eax + 405d5b: 74 13 je 405d70 <__gettext_free_exp+0x160> + 405d5d: 83 f8 01 cmp $0x1,%eax + 405d60: 74 49 je 405dab <__gettext_free_exp+0x19b> + 405d62: 4c 89 e7 mov %r12,%rdi + 405d65: e8 46 80 01 00 callq 41ddb0 <__cfree> + 405d6a: e9 6a ff ff ff jmpq 405cd9 <__gettext_free_exp+0xc9> + 405d6f: 90 nop + 405d70: 49 8b 7c 24 18 mov 0x18(%r12),%rdi + 405d75: e8 96 fe ff ff callq 405c10 <__gettext_free_exp> + 405d7a: 4d 8b 6c 24 10 mov 0x10(%r12),%r13 + 405d7f: 4d 85 ed test %r13,%r13 + 405d82: 74 27 je 405dab <__gettext_free_exp+0x19b> + 405d84: 41 8b 45 00 mov 0x0(%r13),%eax + 405d88: 83 f8 02 cmp $0x2,%eax + 405d8b: 0f 84 b8 03 00 00 je 406149 <__gettext_free_exp+0x539> + 405d91: 83 f8 03 cmp $0x3,%eax + 405d94: 0f 84 a6 03 00 00 je 406140 <__gettext_free_exp+0x530> + 405d9a: 83 f8 01 cmp $0x1,%eax + 405d9d: 0f 84 af 03 00 00 je 406152 <__gettext_free_exp+0x542> + 405da3: 4c 89 ef mov %r13,%rdi + 405da6: e8 05 80 01 00 callq 41ddb0 <__cfree> + 405dab: 4d 8b 6c 24 08 mov 0x8(%r12),%r13 + 405db0: 4d 85 ed test %r13,%r13 + 405db3: 74 ad je 405d62 <__gettext_free_exp+0x152> + 405db5: 41 8b 45 00 mov 0x0(%r13),%eax + 405db9: 83 f8 02 cmp $0x2,%eax + 405dbc: 0f 84 b7 00 00 00 je 405e79 <__gettext_free_exp+0x269> + 405dc2: 83 f8 03 cmp $0x3,%eax + 405dc5: 0f 84 a5 00 00 00 je 405e70 <__gettext_free_exp+0x260> + 405dcb: 83 f8 01 cmp $0x1,%eax + 405dce: 0f 84 d4 00 00 00 je 405ea8 <__gettext_free_exp+0x298> + 405dd4: 4c 89 ef mov %r13,%rdi + 405dd7: e8 d4 7f 01 00 callq 41ddb0 <__cfree> + 405ddc: 4c 89 e7 mov %r12,%rdi + 405ddf: e8 cc 7f 01 00 callq 41ddb0 <__cfree> + 405de4: e9 f0 fe ff ff jmpq 405cd9 <__gettext_free_exp+0xc9> + 405de9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 405df0: 48 8b 7d 18 mov 0x18(%rbp),%rdi + 405df4: e8 17 fe ff ff callq 405c10 <__gettext_free_exp> + 405df9: 4c 8b 65 10 mov 0x10(%rbp),%r12 + 405dfd: 4d 85 e4 test %r12,%r12 + 405e00: 74 27 je 405e29 <__gettext_free_exp+0x219> + 405e02: 41 8b 04 24 mov (%r12),%eax + 405e06: 83 f8 02 cmp $0x2,%eax + 405e09: 0f 84 5b 04 00 00 je 40626a <__gettext_free_exp+0x65a> + 405e0f: 83 f8 03 cmp $0x3,%eax + 405e12: 0f 84 48 04 00 00 je 406260 <__gettext_free_exp+0x650> + 405e18: 83 f8 01 cmp $0x1,%eax + 405e1b: 0f 84 53 04 00 00 je 406274 <__gettext_free_exp+0x664> + 405e21: 4c 89 e7 mov %r12,%rdi + 405e24: e8 87 7f 01 00 callq 41ddb0 <__cfree> + 405e29: 4c 8b 65 08 mov 0x8(%rbp),%r12 + 405e2d: 4d 85 e4 test %r12,%r12 + 405e30: 0f 84 78 fe ff ff je 405cae <__gettext_free_exp+0x9e> + 405e36: 41 8b 04 24 mov (%r12),%eax + 405e3a: 83 f8 02 cmp $0x2,%eax + 405e3d: 0f 84 a7 00 00 00 je 405eea <__gettext_free_exp+0x2da> + 405e43: 83 f8 03 cmp $0x3,%eax + 405e46: 0f 84 94 00 00 00 je 405ee0 <__gettext_free_exp+0x2d0> + 405e4c: 83 f8 01 cmp $0x1,%eax + 405e4f: 0f 84 c6 00 00 00 je 405f1b <__gettext_free_exp+0x30b> + 405e55: 4c 89 e7 mov %r12,%rdi + 405e58: e8 53 7f 01 00 callq 41ddb0 <__cfree> + 405e5d: 48 89 ef mov %rbp,%rdi + 405e60: e8 4b 7f 01 00 callq 41ddb0 <__cfree> + 405e65: e9 4c fe ff ff jmpq 405cb6 <__gettext_free_exp+0xa6> + 405e6a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 405e70: 49 8b 7d 18 mov 0x18(%r13),%rdi + 405e74: e8 97 fd ff ff callq 405c10 <__gettext_free_exp> + 405e79: 4d 8b 75 10 mov 0x10(%r13),%r14 + 405e7d: 4d 85 f6 test %r14,%r14 + 405e80: 74 26 je 405ea8 <__gettext_free_exp+0x298> + 405e82: 41 8b 06 mov (%r14),%eax + 405e85: 83 f8 02 cmp $0x2,%eax + 405e88: 0f 84 bb 01 00 00 je 406049 <__gettext_free_exp+0x439> + 405e8e: 83 f8 03 cmp $0x3,%eax + 405e91: 0f 84 a9 01 00 00 je 406040 <__gettext_free_exp+0x430> + 405e97: 83 f8 01 cmp $0x1,%eax + 405e9a: 0f 84 b2 01 00 00 je 406052 <__gettext_free_exp+0x442> + 405ea0: 4c 89 f7 mov %r14,%rdi + 405ea3: e8 08 7f 01 00 callq 41ddb0 <__cfree> + 405ea8: 4d 8b 75 08 mov 0x8(%r13),%r14 + 405eac: 4d 85 f6 test %r14,%r14 + 405eaf: 0f 84 1f ff ff ff je 405dd4 <__gettext_free_exp+0x1c4> + 405eb5: 41 8b 06 mov (%r14),%eax + 405eb8: 83 f8 02 cmp $0x2,%eax + 405ebb: 0f 84 20 02 00 00 je 4060e1 <__gettext_free_exp+0x4d1> + 405ec1: 83 f8 03 cmp $0x3,%eax + 405ec4: 0f 84 0e 02 00 00 je 4060d8 <__gettext_free_exp+0x4c8> + 405eca: 83 f8 01 cmp $0x1,%eax + 405ecd: 0f 84 17 02 00 00 je 4060ea <__gettext_free_exp+0x4da> + 405ed3: 4c 89 f7 mov %r14,%rdi + 405ed6: e8 d5 7e 01 00 callq 41ddb0 <__cfree> + 405edb: e9 f4 fe ff ff jmpq 405dd4 <__gettext_free_exp+0x1c4> + 405ee0: 49 8b 7c 24 18 mov 0x18(%r12),%rdi + 405ee5: e8 26 fd ff ff callq 405c10 <__gettext_free_exp> + 405eea: 4d 8b 6c 24 10 mov 0x10(%r12),%r13 + 405eef: 4d 85 ed test %r13,%r13 + 405ef2: 74 27 je 405f1b <__gettext_free_exp+0x30b> + 405ef4: 41 8b 45 00 mov 0x0(%r13),%eax + 405ef8: 83 f8 02 cmp $0x2,%eax + 405efb: 0f 84 88 01 00 00 je 406089 <__gettext_free_exp+0x479> + 405f01: 83 f8 03 cmp $0x3,%eax + 405f04: 0f 84 76 01 00 00 je 406080 <__gettext_free_exp+0x470> + 405f0a: 83 f8 01 cmp $0x1,%eax + 405f0d: 0f 84 7f 01 00 00 je 406092 <__gettext_free_exp+0x482> + 405f13: 4c 89 ef mov %r13,%rdi + 405f16: e8 95 7e 01 00 callq 41ddb0 <__cfree> + 405f1b: 4d 8b 6c 24 08 mov 0x8(%r12),%r13 + 405f20: 4d 85 ed test %r13,%r13 + 405f23: 0f 84 2c ff ff ff je 405e55 <__gettext_free_exp+0x245> + 405f29: 41 8b 45 00 mov 0x0(%r13),%eax + 405f2d: 83 f8 02 cmp $0x2,%eax + 405f30: 0f 84 73 02 00 00 je 4061a9 <__gettext_free_exp+0x599> + 405f36: 83 f8 03 cmp $0x3,%eax + 405f39: 0f 84 61 02 00 00 je 4061a0 <__gettext_free_exp+0x590> + 405f3f: 83 f8 01 cmp $0x1,%eax + 405f42: 0f 84 6a 02 00 00 je 4061b2 <__gettext_free_exp+0x5a2> + 405f48: 4c 89 ef mov %r13,%rdi + 405f4b: e8 60 7e 01 00 callq 41ddb0 <__cfree> + 405f50: e9 00 ff ff ff jmpq 405e55 <__gettext_free_exp+0x245> + 405f55: 0f 1f 00 nopl (%rax) + 405f58: 49 8b 7c 24 18 mov 0x18(%r12),%rdi + 405f5d: e8 ae fc ff ff callq 405c10 <__gettext_free_exp> + 405f62: 4d 8b 6c 24 10 mov 0x10(%r12),%r13 + 405f67: 4d 85 ed test %r13,%r13 + 405f6a: 74 27 je 405f93 <__gettext_free_exp+0x383> + 405f6c: 41 8b 45 00 mov 0x0(%r13),%eax + 405f70: 83 f8 02 cmp $0x2,%eax + 405f73: 0f 84 f0 00 00 00 je 406069 <__gettext_free_exp+0x459> + 405f79: 83 f8 03 cmp $0x3,%eax + 405f7c: 0f 84 de 00 00 00 je 406060 <__gettext_free_exp+0x450> + 405f82: 83 f8 01 cmp $0x1,%eax + 405f85: 0f 84 e7 00 00 00 je 406072 <__gettext_free_exp+0x462> + 405f8b: 4c 89 ef mov %r13,%rdi + 405f8e: e8 1d 7e 01 00 callq 41ddb0 <__cfree> + 405f93: 4d 8b 6c 24 08 mov 0x8(%r12),%r13 + 405f98: 4d 85 ed test %r13,%r13 + 405f9b: 0f 84 9d fd ff ff je 405d3e <__gettext_free_exp+0x12e> + 405fa1: 41 8b 45 00 mov 0x0(%r13),%eax + 405fa5: 83 f8 02 cmp $0x2,%eax + 405fa8: 0f 84 5b 02 00 00 je 406209 <__gettext_free_exp+0x5f9> + 405fae: 83 f8 03 cmp $0x3,%eax + 405fb1: 0f 84 49 02 00 00 je 406200 <__gettext_free_exp+0x5f0> + 405fb7: 83 f8 01 cmp $0x1,%eax + 405fba: 0f 84 52 02 00 00 je 406212 <__gettext_free_exp+0x602> + 405fc0: 4c 89 ef mov %r13,%rdi + 405fc3: e8 e8 7d 01 00 callq 41ddb0 <__cfree> + 405fc8: e9 71 fd ff ff jmpq 405d3e <__gettext_free_exp+0x12e> + 405fcd: 0f 1f 00 nopl (%rax) + 405fd0: 48 8b 7d 18 mov 0x18(%rbp),%rdi + 405fd4: e8 37 fc ff ff callq 405c10 <__gettext_free_exp> + 405fd9: 48 8b 7d 10 mov 0x10(%rbp),%rdi + 405fdd: e8 2e fc ff ff callq 405c10 <__gettext_free_exp> + 405fe2: 4c 8b 65 08 mov 0x8(%rbp),%r12 + 405fe6: 4d 85 e4 test %r12,%r12 + 405fe9: 0f 84 90 fc ff ff je 405c7f <__gettext_free_exp+0x6f> + 405fef: 41 8b 04 24 mov (%r12),%eax + 405ff3: 83 f8 02 cmp $0x2,%eax + 405ff6: 74 22 je 40601a <__gettext_free_exp+0x40a> + 405ff8: 83 f8 03 cmp $0x3,%eax + 405ffb: 74 13 je 406010 <__gettext_free_exp+0x400> + 405ffd: 83 f8 01 cmp $0x1,%eax + 406000: 74 22 je 406024 <__gettext_free_exp+0x414> + 406002: 4c 89 e7 mov %r12,%rdi + 406005: e8 a6 7d 01 00 callq 41ddb0 <__cfree> + 40600a: e9 70 fc ff ff jmpq 405c7f <__gettext_free_exp+0x6f> + 40600f: 90 nop + 406010: 49 8b 7c 24 18 mov 0x18(%r12),%rdi + 406015: e8 f6 fb ff ff callq 405c10 <__gettext_free_exp> + 40601a: 49 8b 7c 24 10 mov 0x10(%r12),%rdi + 40601f: e8 ec fb ff ff callq 405c10 <__gettext_free_exp> + 406024: 49 8b 7c 24 08 mov 0x8(%r12),%rdi + 406029: e8 e2 fb ff ff callq 405c10 <__gettext_free_exp> + 40602e: 4c 89 e7 mov %r12,%rdi + 406031: e8 7a 7d 01 00 callq 41ddb0 <__cfree> + 406036: e9 44 fc ff ff jmpq 405c7f <__gettext_free_exp+0x6f> + 40603b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 406040: 49 8b 7e 18 mov 0x18(%r14),%rdi + 406044: e8 c7 fb ff ff callq 405c10 <__gettext_free_exp> + 406049: 49 8b 7e 10 mov 0x10(%r14),%rdi + 40604d: e8 be fb ff ff callq 405c10 <__gettext_free_exp> + 406052: 49 8b 7e 08 mov 0x8(%r14),%rdi + 406056: e8 b5 fb ff ff callq 405c10 <__gettext_free_exp> + 40605b: e9 40 fe ff ff jmpq 405ea0 <__gettext_free_exp+0x290> + 406060: 49 8b 7d 18 mov 0x18(%r13),%rdi + 406064: e8 a7 fb ff ff callq 405c10 <__gettext_free_exp> + 406069: 49 8b 7d 10 mov 0x10(%r13),%rdi + 40606d: e8 9e fb ff ff callq 405c10 <__gettext_free_exp> + 406072: 49 8b 7d 08 mov 0x8(%r13),%rdi + 406076: e8 95 fb ff ff callq 405c10 <__gettext_free_exp> + 40607b: e9 0b ff ff ff jmpq 405f8b <__gettext_free_exp+0x37b> + 406080: 49 8b 7d 18 mov 0x18(%r13),%rdi + 406084: e8 87 fb ff ff callq 405c10 <__gettext_free_exp> + 406089: 49 8b 7d 10 mov 0x10(%r13),%rdi + 40608d: e8 7e fb ff ff callq 405c10 <__gettext_free_exp> + 406092: 49 8b 7d 08 mov 0x8(%r13),%rdi + 406096: e8 75 fb ff ff callq 405c10 <__gettext_free_exp> + 40609b: e9 73 fe ff ff jmpq 405f13 <__gettext_free_exp+0x303> + 4060a0: 4c 8b 65 18 mov 0x18(%rbp),%r12 + 4060a4: 4d 85 e4 test %r12,%r12 + 4060a7: 0f 84 69 fc ff ff je 405d16 <__gettext_free_exp+0x106> + 4060ad: 41 8b 04 24 mov (%r12),%eax + 4060b1: 83 f8 02 cmp $0x2,%eax + 4060b4: 0f 84 40 fc ff ff je 405cfa <__gettext_free_exp+0xea> + 4060ba: 83 f8 03 cmp $0x3,%eax + 4060bd: 0f 84 2d fc ff ff je 405cf0 <__gettext_free_exp+0xe0> + 4060c3: 83 f8 01 cmp $0x1,%eax + 4060c6: 0f 85 42 fc ff ff jne 405d0e <__gettext_free_exp+0xfe> + 4060cc: e9 33 fc ff ff jmpq 405d04 <__gettext_free_exp+0xf4> + 4060d1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4060d8: 49 8b 7e 18 mov 0x18(%r14),%rdi + 4060dc: e8 2f fb ff ff callq 405c10 <__gettext_free_exp> + 4060e1: 49 8b 7e 10 mov 0x10(%r14),%rdi + 4060e5: e8 26 fb ff ff callq 405c10 <__gettext_free_exp> + 4060ea: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 4060ee: 4d 85 ff test %r15,%r15 + 4060f1: 0f 84 dc fd ff ff je 405ed3 <__gettext_free_exp+0x2c3> + 4060f7: 41 8b 07 mov (%r15),%eax + 4060fa: 83 f8 02 cmp $0x2,%eax + 4060fd: 74 2a je 406129 <__gettext_free_exp+0x519> + 4060ff: 83 f8 03 cmp $0x3,%eax + 406102: 74 1c je 406120 <__gettext_free_exp+0x510> + 406104: 83 f8 01 cmp $0x1,%eax + 406107: 74 29 je 406132 <__gettext_free_exp+0x522> + 406109: 4c 89 ff mov %r15,%rdi + 40610c: e8 9f 7c 01 00 callq 41ddb0 <__cfree> + 406111: e9 bd fd ff ff jmpq 405ed3 <__gettext_free_exp+0x2c3> + 406116: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 40611d: 00 00 00 + 406120: 49 8b 7f 18 mov 0x18(%r15),%rdi + 406124: e8 e7 fa ff ff callq 405c10 <__gettext_free_exp> + 406129: 49 8b 7f 10 mov 0x10(%r15),%rdi + 40612d: e8 de fa ff ff callq 405c10 <__gettext_free_exp> + 406132: 49 8b 7f 08 mov 0x8(%r15),%rdi + 406136: e8 d5 fa ff ff callq 405c10 <__gettext_free_exp> + 40613b: eb cc jmp 406109 <__gettext_free_exp+0x4f9> + 40613d: 0f 1f 00 nopl (%rax) + 406140: 49 8b 7d 18 mov 0x18(%r13),%rdi + 406144: e8 c7 fa ff ff callq 405c10 <__gettext_free_exp> + 406149: 49 8b 7d 10 mov 0x10(%r13),%rdi + 40614d: e8 be fa ff ff callq 405c10 <__gettext_free_exp> + 406152: 4d 8b 75 08 mov 0x8(%r13),%r14 + 406156: 4d 85 f6 test %r14,%r14 + 406159: 0f 84 44 fc ff ff je 405da3 <__gettext_free_exp+0x193> + 40615f: 41 8b 06 mov (%r14),%eax + 406162: 83 f8 02 cmp $0x2,%eax + 406165: 74 22 je 406189 <__gettext_free_exp+0x579> + 406167: 83 f8 03 cmp $0x3,%eax + 40616a: 74 14 je 406180 <__gettext_free_exp+0x570> + 40616c: 83 f8 01 cmp $0x1,%eax + 40616f: 74 21 je 406192 <__gettext_free_exp+0x582> + 406171: 4c 89 f7 mov %r14,%rdi + 406174: e8 37 7c 01 00 callq 41ddb0 <__cfree> + 406179: e9 25 fc ff ff jmpq 405da3 <__gettext_free_exp+0x193> + 40617e: 66 90 xchg %ax,%ax + 406180: 49 8b 7e 18 mov 0x18(%r14),%rdi + 406184: e8 87 fa ff ff callq 405c10 <__gettext_free_exp> + 406189: 49 8b 7e 10 mov 0x10(%r14),%rdi + 40618d: e8 7e fa ff ff callq 405c10 <__gettext_free_exp> + 406192: 49 8b 7e 08 mov 0x8(%r14),%rdi + 406196: e8 75 fa ff ff callq 405c10 <__gettext_free_exp> + 40619b: eb d4 jmp 406171 <__gettext_free_exp+0x561> + 40619d: 0f 1f 00 nopl (%rax) + 4061a0: 49 8b 7d 18 mov 0x18(%r13),%rdi + 4061a4: e8 67 fa ff ff callq 405c10 <__gettext_free_exp> + 4061a9: 49 8b 7d 10 mov 0x10(%r13),%rdi + 4061ad: e8 5e fa ff ff callq 405c10 <__gettext_free_exp> + 4061b2: 4d 8b 75 08 mov 0x8(%r13),%r14 + 4061b6: 4d 85 f6 test %r14,%r14 + 4061b9: 0f 84 89 fd ff ff je 405f48 <__gettext_free_exp+0x338> + 4061bf: 41 8b 06 mov (%r14),%eax + 4061c2: 83 f8 02 cmp $0x2,%eax + 4061c5: 74 22 je 4061e9 <__gettext_free_exp+0x5d9> + 4061c7: 83 f8 03 cmp $0x3,%eax + 4061ca: 74 14 je 4061e0 <__gettext_free_exp+0x5d0> + 4061cc: 83 f8 01 cmp $0x1,%eax + 4061cf: 74 21 je 4061f2 <__gettext_free_exp+0x5e2> + 4061d1: 4c 89 f7 mov %r14,%rdi + 4061d4: e8 d7 7b 01 00 callq 41ddb0 <__cfree> + 4061d9: e9 6a fd ff ff jmpq 405f48 <__gettext_free_exp+0x338> + 4061de: 66 90 xchg %ax,%ax + 4061e0: 49 8b 7e 18 mov 0x18(%r14),%rdi + 4061e4: e8 27 fa ff ff callq 405c10 <__gettext_free_exp> + 4061e9: 49 8b 7e 10 mov 0x10(%r14),%rdi + 4061ed: e8 1e fa ff ff callq 405c10 <__gettext_free_exp> + 4061f2: 49 8b 7e 08 mov 0x8(%r14),%rdi + 4061f6: e8 15 fa ff ff callq 405c10 <__gettext_free_exp> + 4061fb: eb d4 jmp 4061d1 <__gettext_free_exp+0x5c1> + 4061fd: 0f 1f 00 nopl (%rax) + 406200: 49 8b 7d 18 mov 0x18(%r13),%rdi + 406204: e8 07 fa ff ff callq 405c10 <__gettext_free_exp> + 406209: 49 8b 7d 10 mov 0x10(%r13),%rdi + 40620d: e8 fe f9 ff ff callq 405c10 <__gettext_free_exp> + 406212: 4d 8b 75 08 mov 0x8(%r13),%r14 + 406216: 4d 85 f6 test %r14,%r14 + 406219: 0f 84 a1 fd ff ff je 405fc0 <__gettext_free_exp+0x3b0> + 40621f: 41 8b 06 mov (%r14),%eax + 406222: 83 f8 02 cmp $0x2,%eax + 406225: 74 22 je 406249 <__gettext_free_exp+0x639> + 406227: 83 f8 03 cmp $0x3,%eax + 40622a: 74 14 je 406240 <__gettext_free_exp+0x630> + 40622c: 83 f8 01 cmp $0x1,%eax + 40622f: 74 21 je 406252 <__gettext_free_exp+0x642> + 406231: 4c 89 f7 mov %r14,%rdi + 406234: e8 77 7b 01 00 callq 41ddb0 <__cfree> + 406239: e9 82 fd ff ff jmpq 405fc0 <__gettext_free_exp+0x3b0> + 40623e: 66 90 xchg %ax,%ax + 406240: 49 8b 7e 18 mov 0x18(%r14),%rdi + 406244: e8 c7 f9 ff ff callq 405c10 <__gettext_free_exp> + 406249: 49 8b 7e 10 mov 0x10(%r14),%rdi + 40624d: e8 be f9 ff ff callq 405c10 <__gettext_free_exp> + 406252: 49 8b 7e 08 mov 0x8(%r14),%rdi + 406256: e8 b5 f9 ff ff callq 405c10 <__gettext_free_exp> + 40625b: eb d4 jmp 406231 <__gettext_free_exp+0x621> + 40625d: 0f 1f 00 nopl (%rax) + 406260: 49 8b 7c 24 18 mov 0x18(%r12),%rdi + 406265: e8 a6 f9 ff ff callq 405c10 <__gettext_free_exp> + 40626a: 49 8b 7c 24 10 mov 0x10(%r12),%rdi + 40626f: e8 9c f9 ff ff callq 405c10 <__gettext_free_exp> + 406274: 4d 8b 6c 24 08 mov 0x8(%r12),%r13 + 406279: 4d 85 ed test %r13,%r13 + 40627c: 0f 84 9f fb ff ff je 405e21 <__gettext_free_exp+0x211> + 406282: 41 8b 45 00 mov 0x0(%r13),%eax + 406286: 83 f8 02 cmp $0x2,%eax + 406289: 74 26 je 4062b1 <__gettext_free_exp+0x6a1> + 40628b: 83 f8 03 cmp $0x3,%eax + 40628e: 74 18 je 4062a8 <__gettext_free_exp+0x698> + 406290: 83 f8 01 cmp $0x1,%eax + 406293: 74 25 je 4062ba <__gettext_free_exp+0x6aa> + 406295: 4c 89 ef mov %r13,%rdi + 406298: e8 13 7b 01 00 callq 41ddb0 <__cfree> + 40629d: e9 7f fb ff ff jmpq 405e21 <__gettext_free_exp+0x211> + 4062a2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4062a8: 49 8b 7d 18 mov 0x18(%r13),%rdi + 4062ac: e8 5f f9 ff ff callq 405c10 <__gettext_free_exp> + 4062b1: 49 8b 7d 10 mov 0x10(%r13),%rdi + 4062b5: e8 56 f9 ff ff callq 405c10 <__gettext_free_exp> + 4062ba: 49 8b 7d 08 mov 0x8(%r13),%rdi + 4062be: e8 4d f9 ff ff callq 405c10 <__gettext_free_exp> + 4062c3: eb d0 jmp 406295 <__gettext_free_exp+0x685> + 4062c5: 0f 1f 00 nopl (%rax) + 4062c8: f3 c3 repz retq + 4062ca: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + +00000000004062d0 : + 4062d0: 41 57 push %r15 + 4062d2: 41 56 push %r14 + 4062d4: 49 89 f6 mov %rsi,%r14 + 4062d7: 41 55 push %r13 + 4062d9: 41 54 push %r12 + 4062db: 55 push %rbp + 4062dc: 53 push %rbx + 4062dd: 48 83 ec 18 sub $0x18,%rsp + 4062e1: 48 8b 5e 08 mov 0x8(%rsi),%rbx + 4062e5: 48 85 db test %rbx,%rbx + 4062e8: 74 3e je 406328 + 4062ea: 48 8b 2e mov (%rsi),%rbp + 4062ed: 48 85 ed test %rbp,%rbp + 4062f0: 74 36 je 406328 + 4062f2: 41 89 fc mov %edi,%r12d + 4062f5: bf 20 00 00 00 mov $0x20,%edi + 4062fa: e8 11 77 01 00 callq 41da10 <__libc_malloc> + 4062ff: 48 85 c0 test %rax,%rax + 406302: 74 24 je 406328 + 406304: c7 00 02 00 00 00 movl $0x2,(%rax) + 40630a: 44 89 60 04 mov %r12d,0x4(%rax) + 40630e: 48 89 58 10 mov %rbx,0x10(%rax) + 406312: 48 89 68 08 mov %rbp,0x8(%rax) + 406316: 48 83 c4 18 add $0x18,%rsp + 40631a: 5b pop %rbx + 40631b: 5d pop %rbp + 40631c: 41 5c pop %r12 + 40631e: 41 5d pop %r13 + 406320: 41 5e pop %r14 + 406322: 41 5f pop %r15 + 406324: c3 retq + 406325: 0f 1f 00 nopl (%rax) + 406328: 31 ed xor %ebp,%ebp + 40632a: eb 28 jmp 406354 + 40632c: 0f 1f 40 00 nopl 0x0(%rax) + 406330: 83 f8 03 cmp $0x3,%eax + 406333: 0f 84 27 03 00 00 je 406660 + 406339: 83 f8 01 cmp $0x1,%eax + 40633c: 74 57 je 406395 + 40633e: 48 89 df mov %rbx,%rdi + 406341: e8 6a 7a 01 00 callq 41ddb0 <__cfree> + 406346: 48 83 ed 08 sub $0x8,%rbp + 40634a: 48 83 fd f0 cmp $0xfffffffffffffff0,%rbp + 40634e: 0f 84 ec 0c 00 00 je 407040 + 406354: 49 8b 5c 2e 08 mov 0x8(%r14,%rbp,1),%rbx + 406359: 48 85 db test %rbx,%rbx + 40635c: 74 e8 je 406346 + 40635e: 8b 03 mov (%rbx),%eax + 406360: 83 f8 02 cmp $0x2,%eax + 406363: 75 cb jne 406330 + 406365: 4c 8b 63 10 mov 0x10(%rbx),%r12 + 406369: 4d 85 e4 test %r12,%r12 + 40636c: 74 27 je 406395 + 40636e: 41 8b 04 24 mov (%r12),%eax + 406372: 83 f8 02 cmp $0x2,%eax + 406375: 0f 84 76 02 00 00 je 4065f1 + 40637b: 83 f8 03 cmp $0x3,%eax + 40637e: 0f 84 7c 0c 00 00 je 407000 + 406384: 83 f8 01 cmp $0x1,%eax + 406387: 0f 84 95 02 00 00 je 406622 + 40638d: 4c 89 e7 mov %r12,%rdi + 406390: e8 1b 7a 01 00 callq 41ddb0 <__cfree> + 406395: 4c 8b 63 08 mov 0x8(%rbx),%r12 + 406399: 4d 85 e4 test %r12,%r12 + 40639c: 74 a0 je 40633e + 40639e: 41 8b 04 24 mov (%r12),%eax + 4063a2: 83 f8 02 cmp $0x2,%eax + 4063a5: 74 4a je 4063f1 + 4063a7: 83 f8 03 cmp $0x3,%eax + 4063aa: 74 14 je 4063c0 + 4063ac: 83 f8 01 cmp $0x1,%eax + 4063af: 74 71 je 406422 + 4063b1: 4c 89 e7 mov %r12,%rdi + 4063b4: e8 f7 79 01 00 callq 41ddb0 <__cfree> + 4063b9: eb 83 jmp 40633e + 4063bb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4063c0: 4d 8b 6c 24 18 mov 0x18(%r12),%r13 + 4063c5: 4d 85 ed test %r13,%r13 + 4063c8: 74 27 je 4063f1 + 4063ca: 41 8b 45 00 mov 0x0(%r13),%eax + 4063ce: 83 f8 02 cmp $0x2,%eax + 4063d1: 0f 84 68 0a 00 00 je 406e3f + 4063d7: 83 f8 03 cmp $0x3,%eax + 4063da: 0f 84 30 0a 00 00 je 406e10 + 4063e0: 83 f8 01 cmp $0x1,%eax + 4063e3: 0f 84 85 0a 00 00 je 406e6e + 4063e9: 4c 89 ef mov %r13,%rdi + 4063ec: e8 bf 79 01 00 callq 41ddb0 <__cfree> + 4063f1: 4d 8b 6c 24 10 mov 0x10(%r12),%r13 + 4063f6: 4d 85 ed test %r13,%r13 + 4063f9: 74 27 je 406422 + 4063fb: 41 8b 45 00 mov 0x0(%r13),%eax + 4063ff: 83 f8 02 cmp $0x2,%eax + 406402: 0f 84 07 04 00 00 je 40680f + 406408: 83 f8 03 cmp $0x3,%eax + 40640b: 0f 84 cf 03 00 00 je 4067e0 + 406411: 83 f8 01 cmp $0x1,%eax + 406414: 0f 84 24 04 00 00 je 40683e + 40641a: 4c 89 ef mov %r13,%rdi + 40641d: e8 8e 79 01 00 callq 41ddb0 <__cfree> + 406422: 4d 8b 6c 24 08 mov 0x8(%r12),%r13 + 406427: 4d 85 ed test %r13,%r13 + 40642a: 74 85 je 4063b1 + 40642c: 41 8b 45 00 mov 0x0(%r13),%eax + 406430: 83 f8 02 cmp $0x2,%eax + 406433: 0f 84 c8 00 00 00 je 406501 + 406439: 83 f8 03 cmp $0x3,%eax + 40643c: 0f 84 0e 0b 00 00 je 406f50 + 406442: 83 f8 01 cmp $0x1,%eax + 406445: 0f 84 e5 00 00 00 je 406530 + 40644b: 4c 89 ef mov %r13,%rdi + 40644e: e8 5d 79 01 00 callq 41ddb0 <__cfree> + 406453: e9 59 ff ff ff jmpq 4063b1 + 406458: 48 8b 78 18 mov 0x18(%rax),%rdi + 40645c: 48 89 04 24 mov %rax,(%rsp) + 406460: e8 ab f7 ff ff callq 405c10 <__gettext_free_exp> + 406465: 48 8b 04 24 mov (%rsp),%rax + 406469: 48 8b 78 10 mov 0x10(%rax),%rdi + 40646d: 48 89 04 24 mov %rax,(%rsp) + 406471: e8 9a f7 ff ff callq 405c10 <__gettext_free_exp> + 406476: 48 8b 04 24 mov (%rsp),%rax + 40647a: 48 8b 78 08 mov 0x8(%rax),%rdi + 40647e: 48 89 04 24 mov %rax,(%rsp) + 406482: e8 89 f7 ff ff callq 405c10 <__gettext_free_exp> + 406487: 48 8b 04 24 mov (%rsp),%rax + 40648b: 48 89 c7 mov %rax,%rdi + 40648e: e8 1d 79 01 00 callq 41ddb0 <__cfree> + 406493: 49 8b 47 10 mov 0x10(%r15),%rax + 406497: 48 85 c0 test %rax,%rax + 40649a: 48 89 04 24 mov %rax,(%rsp) + 40649e: 74 26 je 4064c6 + 4064a0: 8b 00 mov (%rax),%eax + 4064a2: 83 f8 02 cmp $0x2,%eax + 4064a5: 0f 84 9d 20 00 00 je 408548 + 4064ab: 83 f8 03 cmp $0x3,%eax + 4064ae: 0f 84 87 20 00 00 je 40853b + 4064b4: 83 f8 01 cmp $0x1,%eax + 4064b7: 0f 84 bd 20 00 00 je 40857a + 4064bd: 48 8b 3c 24 mov (%rsp),%rdi + 4064c1: e8 ea 78 01 00 callq 41ddb0 <__cfree> + 4064c6: 49 8b 47 08 mov 0x8(%r15),%rax + 4064ca: 48 85 c0 test %rax,%rax + 4064cd: 48 89 04 24 mov %rax,(%rsp) + 4064d1: 74 26 je 4064f9 + 4064d3: 8b 00 mov (%rax),%eax + 4064d5: 83 f8 02 cmp $0x2,%eax + 4064d8: 0f 84 9f 14 00 00 je 40797d + 4064de: 83 f8 03 cmp $0x3,%eax + 4064e1: 0f 84 89 14 00 00 je 407970 + 4064e7: 83 f8 01 cmp $0x1,%eax + 4064ea: 0f 84 bf 14 00 00 je 4079af + 4064f0: 48 8b 3c 24 mov (%rsp),%rdi + 4064f4: e8 b7 78 01 00 callq 41ddb0 <__cfree> + 4064f9: 4c 89 ff mov %r15,%rdi + 4064fc: e8 af 78 01 00 callq 41ddb0 <__cfree> + 406501: 4d 8b 7d 10 mov 0x10(%r13),%r15 + 406505: 4d 85 ff test %r15,%r15 + 406508: 74 26 je 406530 + 40650a: 41 8b 07 mov (%r15),%eax + 40650d: 83 f8 02 cmp $0x2,%eax + 406510: 0f 84 f8 10 00 00 je 40760e + 406516: 83 f8 03 cmp $0x3,%eax + 406519: 0f 84 c1 10 00 00 je 4075e0 + 40651f: 83 f8 01 cmp $0x1,%eax + 406522: 0f 84 12 05 00 00 je 406a3a + 406528: 4c 89 ff mov %r15,%rdi + 40652b: e8 80 78 01 00 callq 41ddb0 <__cfree> + 406530: 4d 8b 7d 08 mov 0x8(%r13),%r15 + 406534: 4d 85 ff test %r15,%r15 + 406537: 0f 84 0e ff ff ff je 40644b + 40653d: 41 8b 07 mov (%r15),%eax + 406540: 83 f8 02 cmp $0x2,%eax + 406543: 0f 84 8a 01 00 00 je 4066d3 + 406549: 83 f8 03 cmp $0x3,%eax + 40654c: 0f 84 4e 01 00 00 je 4066a0 + 406552: 83 f8 01 cmp $0x1,%eax + 406555: 0f 84 ab 01 00 00 je 406706 + 40655b: 4c 89 ff mov %r15,%rdi + 40655e: e8 4d 78 01 00 callq 41ddb0 <__cfree> + 406563: e9 e3 fe ff ff jmpq 40644b + 406568: 49 8b 7f 18 mov 0x18(%r15),%rdi + 40656c: e8 9f f6 ff ff callq 405c10 <__gettext_free_exp> + 406571: 49 8b 7f 10 mov 0x10(%r15),%rdi + 406575: e8 96 f6 ff ff callq 405c10 <__gettext_free_exp> + 40657a: 49 8b 7f 08 mov 0x8(%r15),%rdi + 40657e: e8 8d f6 ff ff callq 405c10 <__gettext_free_exp> + 406583: 4c 89 ff mov %r15,%rdi + 406586: e8 25 78 01 00 callq 41ddb0 <__cfree> + 40658b: 4d 8b 7d 10 mov 0x10(%r13),%r15 + 40658f: 4d 85 ff test %r15,%r15 + 406592: 74 26 je 4065ba + 406594: 41 8b 07 mov (%r15),%eax + 406597: 83 f8 02 cmp $0x2,%eax + 40659a: 0f 84 67 20 00 00 je 408607 + 4065a0: 83 f8 03 cmp $0x3,%eax + 4065a3: 0f 84 55 20 00 00 je 4085fe + 4065a9: 83 f8 01 cmp $0x1,%eax + 4065ac: 0f 84 5e 20 00 00 je 408610 + 4065b2: 4c 89 ff mov %r15,%rdi + 4065b5: e8 f6 77 01 00 callq 41ddb0 <__cfree> + 4065ba: 4d 8b 7d 08 mov 0x8(%r13),%r15 + 4065be: 4d 85 ff test %r15,%r15 + 4065c1: 74 26 je 4065e9 + 4065c3: 41 8b 07 mov (%r15),%eax + 4065c6: 83 f8 02 cmp $0x2,%eax + 4065c9: 0f 84 aa 15 00 00 je 407b79 + 4065cf: 83 f8 03 cmp $0x3,%eax + 4065d2: 0f 84 98 15 00 00 je 407b70 + 4065d8: 83 f8 01 cmp $0x1,%eax + 4065db: 0f 84 c6 15 00 00 je 407ba7 + 4065e1: 4c 89 ff mov %r15,%rdi + 4065e4: e8 c7 77 01 00 callq 41ddb0 <__cfree> + 4065e9: 4c 89 ef mov %r13,%rdi + 4065ec: e8 bf 77 01 00 callq 41ddb0 <__cfree> + 4065f1: 4d 8b 6c 24 10 mov 0x10(%r12),%r13 + 4065f6: 4d 85 ed test %r13,%r13 + 4065f9: 74 27 je 406622 + 4065fb: 41 8b 45 00 mov 0x0(%r13),%eax + 4065ff: 83 f8 02 cmp $0x2,%eax + 406602: 0f 84 27 13 00 00 je 40792f + 406608: 83 f8 03 cmp $0x3,%eax + 40660b: 0f 84 ef 12 00 00 je 407900 + 406611: 83 f8 01 cmp $0x1,%eax + 406614: 0f 84 78 06 00 00 je 406c92 + 40661a: 4c 89 ef mov %r13,%rdi + 40661d: e8 8e 77 01 00 callq 41ddb0 <__cfree> + 406622: 4d 8b 6c 24 08 mov 0x8(%r12),%r13 + 406627: 4d 85 ed test %r13,%r13 + 40662a: 0f 84 5d fd ff ff je 40638d + 406630: 41 8b 45 00 mov 0x0(%r13),%eax + 406634: 83 f8 02 cmp $0x2,%eax + 406637: 0f 84 32 01 00 00 je 40676f + 40663d: 83 f8 03 cmp $0x3,%eax + 406640: 0f 84 fa 00 00 00 je 406740 + 406646: 83 f8 01 cmp $0x1,%eax + 406649: 0f 84 4f 01 00 00 je 40679e + 40664f: 4c 89 ef mov %r13,%rdi + 406652: e8 59 77 01 00 callq 41ddb0 <__cfree> + 406657: e9 31 fd ff ff jmpq 40638d + 40665c: 0f 1f 40 00 nopl 0x0(%rax) + 406660: 4c 8b 63 18 mov 0x18(%rbx),%r12 + 406664: 4d 85 e4 test %r12,%r12 + 406667: 0f 84 f8 fc ff ff je 406365 + 40666d: 41 8b 04 24 mov (%r12),%eax + 406671: 83 f8 02 cmp $0x2,%eax + 406674: 0f 84 47 09 00 00 je 406fc1 + 40667a: 83 f8 03 cmp $0x3,%eax + 40667d: 0f 84 0d 09 00 00 je 406f90 + 406683: 83 f8 01 cmp $0x1,%eax + 406686: 0f 84 73 02 00 00 je 4068ff + 40668c: 4c 89 e7 mov %r12,%rdi + 40668f: e8 1c 77 01 00 callq 41ddb0 <__cfree> + 406694: e9 cc fc ff ff jmpq 406365 + 406699: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4066a0: 49 8b 47 18 mov 0x18(%r15),%rax + 4066a4: 48 85 c0 test %rax,%rax + 4066a7: 48 89 04 24 mov %rax,(%rsp) + 4066ab: 74 26 je 4066d3 + 4066ad: 8b 00 mov (%rax),%eax + 4066af: 83 f8 02 cmp $0x2,%eax + 4066b2: 0f 84 45 13 00 00 je 4079fd + 4066b8: 83 f8 03 cmp $0x3,%eax + 4066bb: 0f 84 2f 13 00 00 je 4079f0 + 4066c1: 83 f8 01 cmp $0x1,%eax + 4066c4: 0f 84 65 13 00 00 je 407a2f + 4066ca: 48 8b 3c 24 mov (%rsp),%rdi + 4066ce: e8 dd 76 01 00 callq 41ddb0 <__cfree> + 4066d3: 49 8b 47 10 mov 0x10(%r15),%rax + 4066d7: 48 85 c0 test %rax,%rax + 4066da: 48 89 04 24 mov %rax,(%rsp) + 4066de: 74 26 je 406706 + 4066e0: 8b 00 mov (%rax),%eax + 4066e2: 83 f8 02 cmp $0x2,%eax + 4066e5: 0f 84 87 0a 00 00 je 407172 + 4066eb: 83 f8 03 cmp $0x3,%eax + 4066ee: 0f 84 4c 0a 00 00 je 407140 + 4066f4: 83 f8 01 cmp $0x1,%eax + 4066f7: 0f 84 a7 0a 00 00 je 4071a4 + 4066fd: 48 8b 3c 24 mov (%rsp),%rdi + 406701: e8 aa 76 01 00 callq 41ddb0 <__cfree> + 406706: 49 8b 47 08 mov 0x8(%r15),%rax + 40670a: 48 85 c0 test %rax,%rax + 40670d: 0f 84 48 fe ff ff je 40655b + 406713: 8b 10 mov (%rax),%edx + 406715: 83 fa 02 cmp $0x2,%edx + 406718: 0f 84 f8 0c 00 00 je 407416 + 40671e: 83 fa 03 cmp $0x3,%edx + 406721: 0f 84 b9 0c 00 00 je 4073e0 + 406727: 83 fa 01 cmp $0x1,%edx + 40672a: 0f 84 71 02 00 00 je 4069a1 + 406730: 48 89 c7 mov %rax,%rdi + 406733: e8 78 76 01 00 callq 41ddb0 <__cfree> + 406738: e9 1e fe ff ff jmpq 40655b + 40673d: 0f 1f 00 nopl (%rax) + 406740: 4d 8b 7d 18 mov 0x18(%r13),%r15 + 406744: 4d 85 ff test %r15,%r15 + 406747: 74 26 je 40676f + 406749: 41 8b 07 mov (%r15),%eax + 40674c: 83 f8 02 cmp $0x2,%eax + 40674f: 0f 84 54 16 00 00 je 407da9 + 406755: 83 f8 03 cmp $0x3,%eax + 406758: 0f 84 42 16 00 00 je 407da0 + 40675e: 83 f8 01 cmp $0x1,%eax + 406761: 0f 84 70 16 00 00 je 407dd7 + 406767: 4c 89 ff mov %r15,%rdi + 40676a: e8 41 76 01 00 callq 41ddb0 <__cfree> + 40676f: 4d 8b 7d 10 mov 0x10(%r13),%r15 + 406773: 4d 85 ff test %r15,%r15 + 406776: 74 26 je 40679e + 406778: 41 8b 07 mov (%r15),%eax + 40677b: 83 f8 02 cmp $0x2,%eax + 40677e: 0f 84 fa 0e 00 00 je 40767e + 406784: 83 f8 03 cmp $0x3,%eax + 406787: 0f 84 c3 0e 00 00 je 407650 + 40678d: 83 f8 01 cmp $0x1,%eax + 406790: 0f 84 1b 0f 00 00 je 4076b1 + 406796: 4c 89 ff mov %r15,%rdi + 406799: e8 12 76 01 00 callq 41ddb0 <__cfree> + 40679e: 4d 8b 7d 08 mov 0x8(%r13),%r15 + 4067a2: 4d 85 ff test %r15,%r15 + 4067a5: 0f 84 a4 fe ff ff je 40664f + 4067ab: 41 8b 07 mov (%r15),%eax + 4067ae: 83 f8 02 cmp $0x2,%eax + 4067b1: 0f 84 07 11 00 00 je 4078be + 4067b7: 83 f8 03 cmp $0x3,%eax + 4067ba: 0f 84 d0 10 00 00 je 407890 + 4067c0: 83 f8 01 cmp $0x1,%eax + 4067c3: 0f 84 11 04 00 00 je 406bda + 4067c9: 4c 89 ff mov %r15,%rdi + 4067cc: e8 df 75 01 00 callq 41ddb0 <__cfree> + 4067d1: e9 79 fe ff ff jmpq 40664f + 4067d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4067dd: 00 00 00 + 4067e0: 4d 8b 7d 18 mov 0x18(%r13),%r15 + 4067e4: 4d 85 ff test %r15,%r15 + 4067e7: 74 26 je 40680f + 4067e9: 41 8b 07 mov (%r15),%eax + 4067ec: 83 f8 02 cmp $0x2,%eax + 4067ef: 0f 84 f4 13 00 00 je 407be9 + 4067f5: 83 f8 03 cmp $0x3,%eax + 4067f8: 0f 84 e2 13 00 00 je 407be0 + 4067fe: 83 f8 01 cmp $0x1,%eax + 406801: 0f 84 10 14 00 00 je 407c17 + 406807: 4c 89 ff mov %r15,%rdi + 40680a: e8 a1 75 01 00 callq 41ddb0 <__cfree> + 40680f: 4d 8b 7d 10 mov 0x10(%r13),%r15 + 406813: 4d 85 ff test %r15,%r15 + 406816: 74 26 je 40683e + 406818: 41 8b 07 mov (%r15),%eax + 40681b: 83 f8 02 cmp $0x2,%eax + 40681e: 0f 84 62 0c 00 00 je 407486 + 406824: 83 f8 03 cmp $0x3,%eax + 406827: 0f 84 2b 0c 00 00 je 407458 + 40682d: 83 f8 01 cmp $0x1,%eax + 406830: 0f 84 83 0c 00 00 je 4074b9 + 406836: 4c 89 ff mov %r15,%rdi + 406839: e8 72 75 01 00 callq 41ddb0 <__cfree> + 40683e: 4d 8b 7d 08 mov 0x8(%r13),%r15 + 406842: 4d 85 ff test %r15,%r15 + 406845: 0f 84 cf fb ff ff je 40641a + 40684b: 41 8b 07 mov (%r15),%eax + 40684e: 83 f8 02 cmp $0x2,%eax + 406851: 0f 84 47 0d 00 00 je 40759e + 406857: 83 f8 03 cmp $0x3,%eax + 40685a: 0f 84 10 0d 00 00 je 407570 + 406860: 83 f8 01 cmp $0x1,%eax + 406863: 0f 84 bb 02 00 00 je 406b24 + 406869: 4c 89 ff mov %r15,%rdi + 40686c: e8 3f 75 01 00 callq 41ddb0 <__cfree> + 406871: e9 a4 fb ff ff jmpq 40641a + 406876: 49 8b 7f 18 mov 0x18(%r15),%rdi + 40687a: e8 91 f3 ff ff callq 405c10 <__gettext_free_exp> + 40687f: 49 8b 7f 10 mov 0x10(%r15),%rdi + 406883: e8 88 f3 ff ff callq 405c10 <__gettext_free_exp> + 406888: 49 8b 7f 08 mov 0x8(%r15),%rdi + 40688c: e8 7f f3 ff ff callq 405c10 <__gettext_free_exp> + 406891: 4c 89 ff mov %r15,%rdi + 406894: e8 17 75 01 00 callq 41ddb0 <__cfree> + 406899: 4d 8b 7d 10 mov 0x10(%r13),%r15 + 40689d: 4d 85 ff test %r15,%r15 + 4068a0: 74 26 je 4068c8 + 4068a2: 41 8b 07 mov (%r15),%eax + 4068a5: 83 f8 02 cmp $0x2,%eax + 4068a8: 0f 84 10 1d 00 00 je 4085be + 4068ae: 83 f8 03 cmp $0x3,%eax + 4068b1: 0f 84 fe 1c 00 00 je 4085b5 + 4068b7: 83 f8 01 cmp $0x1,%eax + 4068ba: 0f 84 07 1d 00 00 je 4085c7 + 4068c0: 4c 89 ff mov %r15,%rdi + 4068c3: e8 e8 74 01 00 callq 41ddb0 <__cfree> + 4068c8: 4d 8b 7d 08 mov 0x8(%r13),%r15 + 4068cc: 4d 85 ff test %r15,%r15 + 4068cf: 74 26 je 4068f7 + 4068d1: 41 8b 07 mov (%r15),%eax + 4068d4: 83 f8 02 cmp $0x2,%eax + 4068d7: 0f 84 7c 13 00 00 je 407c59 + 4068dd: 83 f8 03 cmp $0x3,%eax + 4068e0: 0f 84 6a 13 00 00 je 407c50 + 4068e6: 83 f8 01 cmp $0x1,%eax + 4068e9: 0f 84 98 13 00 00 je 407c87 + 4068ef: 4c 89 ff mov %r15,%rdi + 4068f2: e8 b9 74 01 00 callq 41ddb0 <__cfree> + 4068f7: 4c 89 ef mov %r13,%rdi + 4068fa: e8 b1 74 01 00 callq 41ddb0 <__cfree> + 4068ff: 4d 8b 6c 24 08 mov 0x8(%r12),%r13 + 406904: 4d 85 ed test %r13,%r13 + 406907: 0f 84 7f fd ff ff je 40668c + 40690d: 41 8b 45 00 mov 0x0(%r13),%eax + 406911: 83 f8 02 cmp $0x2,%eax + 406914: 0f 84 e5 03 00 00 je 406cff + 40691a: 83 f8 03 cmp $0x3,%eax + 40691d: 0f 84 ad 03 00 00 je 406cd0 + 406923: 83 f8 01 cmp $0x1,%eax + 406926: 0f 84 02 04 00 00 je 406d2e + 40692c: 4c 89 ef mov %r13,%rdi + 40692f: e8 7c 74 01 00 callq 41ddb0 <__cfree> + 406934: e9 53 fd ff ff jmpq 40668c + 406939: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 406940: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 406944: 48 89 44 24 08 mov %rax,0x8(%rsp) + 406949: 48 89 14 24 mov %rdx,(%rsp) + 40694d: e8 be f2 ff ff callq 405c10 <__gettext_free_exp> + 406952: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 406957: 48 8b 14 24 mov (%rsp),%rdx + 40695b: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 40695f: 48 89 44 24 08 mov %rax,0x8(%rsp) + 406964: 48 89 14 24 mov %rdx,(%rsp) + 406968: e8 a3 f2 ff ff callq 405c10 <__gettext_free_exp> + 40696d: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 406972: 48 8b 14 24 mov (%rsp),%rdx + 406976: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 40697a: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40697f: 48 89 14 24 mov %rdx,(%rsp) + 406983: e8 88 f2 ff ff callq 405c10 <__gettext_free_exp> + 406988: 48 8b 14 24 mov (%rsp),%rdx + 40698c: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 406991: 48 89 d7 mov %rdx,%rdi + 406994: 48 89 04 24 mov %rax,(%rsp) + 406998: e8 13 74 01 00 callq 41ddb0 <__cfree> + 40699d: 48 8b 04 24 mov (%rsp),%rax + 4069a1: 48 8b 78 08 mov 0x8(%rax),%rdi + 4069a5: 48 89 04 24 mov %rax,(%rsp) + 4069a9: e8 62 f2 ff ff callq 405c10 <__gettext_free_exp> + 4069ae: 48 8b 04 24 mov (%rsp),%rax + 4069b2: e9 79 fd ff ff jmpq 406730 + 4069b7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 4069be: 00 00 + 4069c0: 48 8b 04 24 mov (%rsp),%rax + 4069c4: 48 8b 78 18 mov 0x18(%rax),%rdi + 4069c8: e8 43 f2 ff ff callq 405c10 <__gettext_free_exp> + 4069cd: 48 8b 04 24 mov (%rsp),%rax + 4069d1: 48 8b 40 10 mov 0x10(%rax),%rax + 4069d5: 48 85 c0 test %rax,%rax + 4069d8: 74 25 je 4069ff + 4069da: 8b 10 mov (%rax),%edx + 4069dc: 83 fa 02 cmp $0x2,%edx + 4069df: 0f 84 fc 1c 00 00 je 4086e1 + 4069e5: 83 fa 03 cmp $0x3,%edx + 4069e8: 0f 84 e0 1c 00 00 je 4086ce + 4069ee: 83 fa 01 cmp $0x1,%edx + 4069f1: 0f 84 fd 1c 00 00 je 4086f4 + 4069f7: 48 89 c7 mov %rax,%rdi + 4069fa: e8 b1 73 01 00 callq 41ddb0 <__cfree> + 4069ff: 48 8b 04 24 mov (%rsp),%rax + 406a03: 48 8b 40 08 mov 0x8(%rax),%rax + 406a07: 48 85 c0 test %rax,%rax + 406a0a: 74 25 je 406a31 + 406a0c: 8b 10 mov (%rax),%edx + 406a0e: 83 fa 02 cmp $0x2,%edx + 406a11: 0f 84 8c 14 00 00 je 407ea3 + 406a17: 83 fa 03 cmp $0x3,%edx + 406a1a: 0f 84 70 14 00 00 je 407e90 + 406a20: 83 fa 01 cmp $0x1,%edx + 406a23: 0f 84 8d 14 00 00 je 407eb6 + 406a29: 48 89 c7 mov %rax,%rdi + 406a2c: e8 7f 73 01 00 callq 41ddb0 <__cfree> + 406a31: 48 8b 3c 24 mov (%rsp),%rdi + 406a35: e8 76 73 01 00 callq 41ddb0 <__cfree> + 406a3a: 49 8b 47 08 mov 0x8(%r15),%rax + 406a3e: 48 85 c0 test %rax,%rax + 406a41: 48 89 04 24 mov %rax,(%rsp) + 406a45: 0f 84 dd fa ff ff je 406528 + 406a4b: 8b 00 mov (%rax),%eax + 406a4d: 83 f8 02 cmp $0x2,%eax + 406a50: 0f 84 dc 08 00 00 je 407332 + 406a56: 83 f8 03 cmp $0x3,%eax + 406a59: 0f 84 a1 08 00 00 je 407300 + 406a5f: 83 f8 01 cmp $0x1,%eax + 406a62: 0f 84 fc 08 00 00 je 407364 + 406a68: 48 8b 3c 24 mov (%rsp),%rdi + 406a6c: e8 3f 73 01 00 callq 41ddb0 <__cfree> + 406a71: e9 b2 fa ff ff jmpq 406528 + 406a76: 48 8b 78 18 mov 0x18(%rax),%rdi + 406a7a: 48 89 44 24 08 mov %rax,0x8(%rsp) + 406a7f: e8 8c f1 ff ff callq 405c10 <__gettext_free_exp> + 406a84: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 406a89: 48 8b 78 10 mov 0x10(%rax),%rdi + 406a8d: 48 89 44 24 08 mov %rax,0x8(%rsp) + 406a92: e8 79 f1 ff ff callq 405c10 <__gettext_free_exp> + 406a97: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 406a9c: 48 8b 78 08 mov 0x8(%rax),%rdi + 406aa0: 48 89 44 24 08 mov %rax,0x8(%rsp) + 406aa5: e8 66 f1 ff ff callq 405c10 <__gettext_free_exp> + 406aaa: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 406aaf: 48 89 c7 mov %rax,%rdi + 406ab2: e8 f9 72 01 00 callq 41ddb0 <__cfree> + 406ab7: 48 8b 04 24 mov (%rsp),%rax + 406abb: 48 8b 40 10 mov 0x10(%rax),%rax + 406abf: 48 85 c0 test %rax,%rax + 406ac2: 74 25 je 406ae9 + 406ac4: 8b 10 mov (%rax),%edx + 406ac6: 83 fa 02 cmp $0x2,%edx + 406ac9: 0f 84 d4 1b 00 00 je 4086a3 + 406acf: 83 fa 03 cmp $0x3,%edx + 406ad2: 0f 84 b8 1b 00 00 je 408690 + 406ad8: 83 fa 01 cmp $0x1,%edx + 406adb: 0f 84 d5 1b 00 00 je 4086b6 + 406ae1: 48 89 c7 mov %rax,%rdi + 406ae4: e8 c7 72 01 00 callq 41ddb0 <__cfree> + 406ae9: 48 8b 04 24 mov (%rsp),%rax + 406aed: 48 8b 40 08 mov 0x8(%rax),%rax + 406af1: 48 85 c0 test %rax,%rax + 406af4: 74 25 je 406b1b + 406af6: 8b 10 mov (%rax),%edx + 406af8: 83 fa 02 cmp $0x2,%edx + 406afb: 0f 84 22 14 00 00 je 407f23 + 406b01: 83 fa 03 cmp $0x3,%edx + 406b04: 0f 84 06 14 00 00 je 407f10 + 406b0a: 83 fa 01 cmp $0x1,%edx + 406b0d: 0f 84 23 14 00 00 je 407f36 + 406b13: 48 89 c7 mov %rax,%rdi + 406b16: e8 95 72 01 00 callq 41ddb0 <__cfree> + 406b1b: 48 8b 3c 24 mov (%rsp),%rdi + 406b1f: e8 8c 72 01 00 callq 41ddb0 <__cfree> + 406b24: 49 8b 47 08 mov 0x8(%r15),%rax + 406b28: 48 85 c0 test %rax,%rax + 406b2b: 48 89 04 24 mov %rax,(%rsp) + 406b2f: 0f 84 34 fd ff ff je 406869 + 406b35: 8b 00 mov (%rax),%eax + 406b37: 83 f8 02 cmp $0x2,%eax + 406b3a: 0f 84 12 07 00 00 je 407252 + 406b40: 83 f8 03 cmp $0x3,%eax + 406b43: 0f 84 d7 06 00 00 je 407220 + 406b49: 83 f8 01 cmp $0x1,%eax + 406b4c: 0f 84 32 07 00 00 je 407284 + 406b52: 48 8b 3c 24 mov (%rsp),%rdi + 406b56: e8 55 72 01 00 callq 41ddb0 <__cfree> + 406b5b: e9 09 fd ff ff jmpq 406869 + 406b60: 48 8b 04 24 mov (%rsp),%rax + 406b64: 48 8b 78 18 mov 0x18(%rax),%rdi + 406b68: e8 a3 f0 ff ff callq 405c10 <__gettext_free_exp> + 406b6d: 48 8b 04 24 mov (%rsp),%rax + 406b71: 48 8b 40 10 mov 0x10(%rax),%rax + 406b75: 48 85 c0 test %rax,%rax + 406b78: 74 25 je 406b9f + 406b7a: 8b 10 mov (%rax),%edx + 406b7c: 83 fa 02 cmp $0x2,%edx + 406b7f: 0f 84 16 1c 00 00 je 40879b + 406b85: 83 fa 03 cmp $0x3,%edx + 406b88: 0f 84 fa 1b 00 00 je 408788 + 406b8e: 83 fa 01 cmp $0x1,%edx + 406b91: 0f 84 17 1c 00 00 je 4087ae + 406b97: 48 89 c7 mov %rax,%rdi + 406b9a: e8 11 72 01 00 callq 41ddb0 <__cfree> + 406b9f: 48 8b 04 24 mov (%rsp),%rax + 406ba3: 48 8b 40 08 mov 0x8(%rax),%rax + 406ba7: 48 85 c0 test %rax,%rax + 406baa: 74 25 je 406bd1 + 406bac: 8b 10 mov (%rax),%edx + 406bae: 83 fa 02 cmp $0x2,%edx + 406bb1: 0f 84 6c 12 00 00 je 407e23 + 406bb7: 83 fa 03 cmp $0x3,%edx + 406bba: 0f 84 50 12 00 00 je 407e10 + 406bc0: 83 fa 01 cmp $0x1,%edx + 406bc3: 0f 84 6d 12 00 00 je 407e36 + 406bc9: 48 89 c7 mov %rax,%rdi + 406bcc: e8 df 71 01 00 callq 41ddb0 <__cfree> + 406bd1: 48 8b 3c 24 mov (%rsp),%rdi + 406bd5: e8 d6 71 01 00 callq 41ddb0 <__cfree> + 406bda: 49 8b 47 08 mov 0x8(%r15),%rax + 406bde: 48 85 c0 test %rax,%rax + 406be1: 48 89 04 24 mov %rax,(%rsp) + 406be5: 0f 84 de fb ff ff je 4067c9 + 406beb: 8b 00 mov (%rax),%eax + 406bed: 83 f8 02 cmp $0x2,%eax + 406bf0: 0f 84 94 04 00 00 je 40708a + 406bf6: 83 f8 03 cmp $0x3,%eax + 406bf9: 0f 84 59 04 00 00 je 407058 + 406bff: 83 f8 01 cmp $0x1,%eax + 406c02: 0f 84 b4 04 00 00 je 4070bc + 406c08: 48 8b 3c 24 mov (%rsp),%rdi + 406c0c: e8 9f 71 01 00 callq 41ddb0 <__cfree> + 406c11: e9 b3 fb ff ff jmpq 4067c9 + 406c16: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 406c1d: 00 00 00 + 406c20: 49 8b 7f 18 mov 0x18(%r15),%rdi + 406c24: e8 e7 ef ff ff callq 405c10 <__gettext_free_exp> + 406c29: 49 8b 47 10 mov 0x10(%r15),%rax + 406c2d: 48 85 c0 test %rax,%rax + 406c30: 74 25 je 406c57 + 406c32: 8b 10 mov (%rax),%edx + 406c34: 83 fa 02 cmp $0x2,%edx + 406c37: 0f 84 d8 1b 00 00 je 408815 + 406c3d: 83 fa 03 cmp $0x3,%edx + 406c40: 0f 84 be 1b 00 00 je 408804 + 406c46: 83 fa 01 cmp $0x1,%edx + 406c49: 0f 84 d7 1b 00 00 je 408826 + 406c4f: 48 89 c7 mov %rax,%rdi + 406c52: e8 59 71 01 00 callq 41ddb0 <__cfree> + 406c57: 49 8b 47 08 mov 0x8(%r15),%rax + 406c5b: 48 85 c0 test %rax,%rax + 406c5e: 48 89 04 24 mov %rax,(%rsp) + 406c62: 74 26 je 406c8a + 406c64: 8b 00 mov (%rax),%eax + 406c66: 83 f8 02 cmp $0x2,%eax + 406c69: 0f 84 2e 14 00 00 je 40809d + 406c6f: 83 f8 03 cmp $0x3,%eax + 406c72: 0f 84 18 14 00 00 je 408090 + 406c78: 83 f8 01 cmp $0x1,%eax + 406c7b: 0f 84 4e 14 00 00 je 4080cf + 406c81: 48 8b 3c 24 mov (%rsp),%rdi + 406c85: e8 26 71 01 00 callq 41ddb0 <__cfree> + 406c8a: 4c 89 ff mov %r15,%rdi + 406c8d: e8 1e 71 01 00 callq 41ddb0 <__cfree> + 406c92: 4d 8b 7d 08 mov 0x8(%r13),%r15 + 406c96: 4d 85 ff test %r15,%r15 + 406c99: 0f 84 7b f9 ff ff je 40661a + 406c9f: 41 8b 07 mov (%r15),%eax + 406ca2: 83 f8 02 cmp $0x2,%eax + 406ca5: 0f 84 f3 0a 00 00 je 40779e + 406cab: 83 f8 03 cmp $0x3,%eax + 406cae: 0f 84 bc 0a 00 00 je 407770 + 406cb4: 83 f8 01 cmp $0x1,%eax + 406cb7: 0f 84 14 0b 00 00 je 4077d1 + 406cbd: 4c 89 ff mov %r15,%rdi + 406cc0: e8 eb 70 01 00 callq 41ddb0 <__cfree> + 406cc5: e9 50 f9 ff ff jmpq 40661a + 406cca: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 406cd0: 4d 8b 7d 18 mov 0x18(%r13),%r15 + 406cd4: 4d 85 ff test %r15,%r15 + 406cd7: 74 26 je 406cff + 406cd9: 41 8b 07 mov (%r15),%eax + 406cdc: 83 f8 02 cmp $0x2,%eax + 406cdf: 0f 84 5b 22 00 00 je 408f40 + 406ce5: 83 f8 03 cmp $0x3,%eax + 406ce8: 0f 84 49 22 00 00 je 408f37 + 406cee: 83 f8 01 cmp $0x1,%eax + 406cf1: 0f 84 52 22 00 00 je 408f49 + 406cf7: 4c 89 ff mov %r15,%rdi + 406cfa: e8 b1 70 01 00 callq 41ddb0 <__cfree> + 406cff: 4d 8b 7d 10 mov 0x10(%r13),%r15 + 406d03: 4d 85 ff test %r15,%r15 + 406d06: 74 26 je 406d2e + 406d08: 41 8b 07 mov (%r15),%eax + 406d0b: 83 f8 02 cmp $0x2,%eax + 406d0e: 0f 84 b5 0f 00 00 je 407cc9 + 406d14: 83 f8 03 cmp $0x3,%eax + 406d17: 0f 84 a3 0f 00 00 je 407cc0 + 406d1d: 83 f8 01 cmp $0x1,%eax + 406d20: 0f 84 d1 0f 00 00 je 407cf7 + 406d26: 4c 89 ff mov %r15,%rdi + 406d29: e8 82 70 01 00 callq 41ddb0 <__cfree> + 406d2e: 4d 8b 7d 08 mov 0x8(%r13),%r15 + 406d32: 4d 85 ff test %r15,%r15 + 406d35: 0f 84 f1 fb ff ff je 40692c + 406d3b: 41 8b 07 mov (%r15),%eax + 406d3e: 83 f8 02 cmp $0x2,%eax + 406d41: 74 56 je 406d99 + 406d43: 83 f8 03 cmp $0x3,%eax + 406d46: 0f 84 14 21 00 00 je 408e60 + 406d4c: 83 f8 01 cmp $0x1,%eax + 406d4f: 74 76 je 406dc7 + 406d51: 4c 89 ff mov %r15,%rdi + 406d54: e8 57 70 01 00 callq 41ddb0 <__cfree> + 406d59: e9 ce fb ff ff jmpq 40692c + 406d5e: 48 8b 78 18 mov 0x18(%rax),%rdi + 406d62: 48 89 04 24 mov %rax,(%rsp) + 406d66: e8 a5 ee ff ff callq 405c10 <__gettext_free_exp> + 406d6b: 48 8b 04 24 mov (%rsp),%rax + 406d6f: 48 8b 78 10 mov 0x10(%rax),%rdi + 406d73: 48 89 04 24 mov %rax,(%rsp) + 406d77: e8 94 ee ff ff callq 405c10 <__gettext_free_exp> + 406d7c: 48 8b 04 24 mov (%rsp),%rax + 406d80: 48 8b 78 08 mov 0x8(%rax),%rdi + 406d84: 48 89 04 24 mov %rax,(%rsp) + 406d88: e8 83 ee ff ff callq 405c10 <__gettext_free_exp> + 406d8d: 48 8b 04 24 mov (%rsp),%rax + 406d91: 48 89 c7 mov %rax,%rdi + 406d94: e8 17 70 01 00 callq 41ddb0 <__cfree> + 406d99: 49 8b 47 10 mov 0x10(%r15),%rax + 406d9d: 48 85 c0 test %rax,%rax + 406da0: 74 25 je 406dc7 + 406da2: 8b 10 mov (%rax),%edx + 406da4: 83 fa 02 cmp $0x2,%edx + 406da7: 0f 84 1b 16 00 00 je 4083c8 + 406dad: 83 fa 03 cmp $0x3,%edx + 406db0: 0f 84 01 16 00 00 je 4083b7 + 406db6: 83 fa 01 cmp $0x1,%edx + 406db9: 0f 84 1a 16 00 00 je 4083d9 + 406dbf: 48 89 c7 mov %rax,%rdi + 406dc2: e8 e9 6f 01 00 callq 41ddb0 <__cfree> + 406dc7: 49 8b 47 08 mov 0x8(%r15),%rax + 406dcb: 48 85 c0 test %rax,%rax + 406dce: 48 89 04 24 mov %rax,(%rsp) + 406dd2: 0f 84 79 ff ff ff je 406d51 + 406dd8: 8b 00 mov (%rax),%eax + 406dda: 83 f8 02 cmp $0x2,%eax + 406ddd: 0f 84 9a 0c 00 00 je 407a7d + 406de3: 83 f8 03 cmp $0x3,%eax + 406de6: 0f 84 84 0c 00 00 je 407a70 + 406dec: 83 f8 01 cmp $0x1,%eax + 406def: 0f 84 ba 0c 00 00 je 407aaf + 406df5: 48 8b 3c 24 mov (%rsp),%rdi + 406df9: e8 b2 6f 01 00 callq 41ddb0 <__cfree> + 406dfe: 4c 89 ff mov %r15,%rdi + 406e01: e8 aa 6f 01 00 callq 41ddb0 <__cfree> + 406e06: e9 21 fb ff ff jmpq 40692c + 406e0b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 406e10: 4d 8b 7d 18 mov 0x18(%r13),%r15 + 406e14: 4d 85 ff test %r15,%r15 + 406e17: 74 26 je 406e3f + 406e19: 41 8b 07 mov (%r15),%eax + 406e1c: 83 f8 02 cmp $0x2,%eax + 406e1f: 0f 84 73 20 00 00 je 408e98 + 406e25: 83 f8 03 cmp $0x3,%eax + 406e28: 0f 84 61 20 00 00 je 408e8f + 406e2e: 83 f8 01 cmp $0x1,%eax + 406e31: 0f 84 6a 20 00 00 je 408ea1 + 406e37: 4c 89 ff mov %r15,%rdi + 406e3a: e8 71 6f 01 00 callq 41ddb0 <__cfree> + 406e3f: 4d 8b 7d 10 mov 0x10(%r13),%r15 + 406e43: 4d 85 ff test %r15,%r15 + 406e46: 74 26 je 406e6e + 406e48: 41 8b 07 mov (%r15),%eax + 406e4b: 83 f8 02 cmp $0x2,%eax + 406e4e: 0f 84 e5 0e 00 00 je 407d39 + 406e54: 83 f8 03 cmp $0x3,%eax + 406e57: 0f 84 d3 0e 00 00 je 407d30 + 406e5d: 83 f8 01 cmp $0x1,%eax + 406e60: 0f 84 01 0f 00 00 je 407d67 + 406e66: 4c 89 ff mov %r15,%rdi + 406e69: e8 42 6f 01 00 callq 41ddb0 <__cfree> + 406e6e: 4d 8b 7d 08 mov 0x8(%r13),%r15 + 406e72: 4d 85 ff test %r15,%r15 + 406e75: 0f 84 6e f5 ff ff je 4063e9 + 406e7b: 41 8b 07 mov (%r15),%eax + 406e7e: 83 f8 02 cmp $0x2,%eax + 406e81: 74 56 je 406ed9 + 406e83: 83 f8 03 cmp $0x3,%eax + 406e86: 0f 84 7c 20 00 00 je 408f08 + 406e8c: 83 f8 01 cmp $0x1,%eax + 406e8f: 74 76 je 406f07 + 406e91: 4c 89 ff mov %r15,%rdi + 406e94: e8 17 6f 01 00 callq 41ddb0 <__cfree> + 406e99: e9 4b f5 ff ff jmpq 4063e9 + 406e9e: 48 8b 78 18 mov 0x18(%rax),%rdi + 406ea2: 48 89 04 24 mov %rax,(%rsp) + 406ea6: e8 65 ed ff ff callq 405c10 <__gettext_free_exp> + 406eab: 48 8b 04 24 mov (%rsp),%rax + 406eaf: 48 8b 78 10 mov 0x10(%rax),%rdi + 406eb3: 48 89 04 24 mov %rax,(%rsp) + 406eb7: e8 54 ed ff ff callq 405c10 <__gettext_free_exp> + 406ebc: 48 8b 04 24 mov (%rsp),%rax + 406ec0: 48 8b 78 08 mov 0x8(%rax),%rdi + 406ec4: 48 89 04 24 mov %rax,(%rsp) + 406ec8: e8 43 ed ff ff callq 405c10 <__gettext_free_exp> + 406ecd: 48 8b 04 24 mov (%rsp),%rax + 406ed1: 48 89 c7 mov %rax,%rdi + 406ed4: e8 d7 6e 01 00 callq 41ddb0 <__cfree> + 406ed9: 49 8b 47 10 mov 0x10(%r15),%rax + 406edd: 48 85 c0 test %rax,%rax + 406ee0: 74 25 je 406f07 + 406ee2: 8b 10 mov (%rax),%edx + 406ee4: 83 fa 02 cmp $0x2,%edx + 406ee7: 0f 84 9d 15 00 00 je 40848a + 406eed: 83 fa 03 cmp $0x3,%edx + 406ef0: 0f 84 83 15 00 00 je 408479 + 406ef6: 83 fa 01 cmp $0x1,%edx + 406ef9: 0f 84 9c 15 00 00 je 40849b + 406eff: 48 89 c7 mov %rax,%rdi + 406f02: e8 a9 6e 01 00 callq 41ddb0 <__cfree> + 406f07: 49 8b 47 08 mov 0x8(%r15),%rax + 406f0b: 48 85 c0 test %rax,%rax + 406f0e: 48 89 04 24 mov %rax,(%rsp) + 406f12: 0f 84 79 ff ff ff je 406e91 + 406f18: 8b 00 mov (%rax),%eax + 406f1a: 83 f8 02 cmp $0x2,%eax + 406f1d: 0f 84 da 0b 00 00 je 407afd + 406f23: 83 f8 03 cmp $0x3,%eax + 406f26: 0f 84 c4 0b 00 00 je 407af0 + 406f2c: 83 f8 01 cmp $0x1,%eax + 406f2f: 0f 84 fa 0b 00 00 je 407b2f + 406f35: 48 8b 3c 24 mov (%rsp),%rdi + 406f39: e8 72 6e 01 00 callq 41ddb0 <__cfree> + 406f3e: 4c 89 ff mov %r15,%rdi + 406f41: e8 6a 6e 01 00 callq 41ddb0 <__cfree> + 406f46: e9 9e f4 ff ff jmpq 4063e9 + 406f4b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 406f50: 4d 8b 7d 18 mov 0x18(%r13),%r15 + 406f54: 4d 85 ff test %r15,%r15 + 406f57: 0f 84 a4 f5 ff ff je 406501 + 406f5d: 41 8b 07 mov (%r15),%eax + 406f60: 83 f8 02 cmp $0x2,%eax + 406f63: 0f 84 2a f5 ff ff je 406493 + 406f69: 83 f8 03 cmp $0x3,%eax + 406f6c: 0f 84 3e 20 00 00 je 408fb0 + 406f72: 83 f8 01 cmp $0x1,%eax + 406f75: 0f 84 4b f5 ff ff je 4064c6 + 406f7b: 4c 89 ff mov %r15,%rdi + 406f7e: e8 2d 6e 01 00 callq 41ddb0 <__cfree> + 406f83: e9 79 f5 ff ff jmpq 406501 + 406f88: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 406f8f: 00 + 406f90: 4d 8b 6c 24 18 mov 0x18(%r12),%r13 + 406f95: 4d 85 ed test %r13,%r13 + 406f98: 74 27 je 406fc1 + 406f9a: 41 8b 45 00 mov 0x0(%r13),%eax + 406f9e: 83 f8 02 cmp $0x2,%eax + 406fa1: 0f 84 f2 12 00 00 je 408299 + 406fa7: 83 f8 03 cmp $0x3,%eax + 406faa: 0f 84 e0 12 00 00 je 408290 + 406fb0: 83 f8 01 cmp $0x1,%eax + 406fb3: 0f 84 0f 13 00 00 je 4082c8 + 406fb9: 4c 89 ef mov %r13,%rdi + 406fbc: e8 ef 6d 01 00 callq 41ddb0 <__cfree> + 406fc1: 4d 8b 6c 24 10 mov 0x10(%r12),%r13 + 406fc6: 4d 85 ed test %r13,%r13 + 406fc9: 0f 84 30 f9 ff ff je 4068ff + 406fcf: 41 8b 45 00 mov 0x0(%r13),%eax + 406fd3: 83 f8 02 cmp $0x2,%eax + 406fd6: 0f 84 bd f8 ff ff je 406899 + 406fdc: 83 f8 03 cmp $0x3,%eax + 406fdf: 0f 84 ab 20 00 00 je 409090 + 406fe5: 83 f8 01 cmp $0x1,%eax + 406fe8: 0f 84 da f8 ff ff je 4068c8 + 406fee: 4c 89 ef mov %r13,%rdi + 406ff1: e8 ba 6d 01 00 callq 41ddb0 <__cfree> + 406ff6: e9 04 f9 ff ff jmpq 4068ff + 406ffb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 407000: 4d 8b 6c 24 18 mov 0x18(%r12),%r13 + 407005: 4d 85 ed test %r13,%r13 + 407008: 0f 84 e3 f5 ff ff je 4065f1 + 40700e: 41 8b 45 00 mov 0x0(%r13),%eax + 407012: 83 f8 02 cmp $0x2,%eax + 407015: 0f 84 70 f5 ff ff je 40658b + 40701b: 83 f8 03 cmp $0x3,%eax + 40701e: 0f 84 34 20 00 00 je 409058 + 407024: 83 f8 01 cmp $0x1,%eax + 407027: 0f 84 8d f5 ff ff je 4065ba + 40702d: 4c 89 ef mov %r13,%rdi + 407030: e8 7b 6d 01 00 callq 41ddb0 <__cfree> + 407035: e9 b7 f5 ff ff jmpq 4065f1 + 40703a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 407040: 48 83 c4 18 add $0x18,%rsp + 407044: 31 c0 xor %eax,%eax + 407046: 5b pop %rbx + 407047: 5d pop %rbp + 407048: 41 5c pop %r12 + 40704a: 41 5d pop %r13 + 40704c: 41 5e pop %r14 + 40704e: 41 5f pop %r15 + 407050: c3 retq + 407051: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 407058: 48 8b 04 24 mov (%rsp),%rax + 40705c: 48 8b 40 18 mov 0x18(%rax),%rax + 407060: 48 85 c0 test %rax,%rax + 407063: 74 25 je 40708a + 407065: 8b 10 mov (%rax),%edx + 407067: 83 fa 02 cmp $0x2,%edx + 40706a: 0f 84 63 20 00 00 je 4090d3 + 407070: 83 fa 03 cmp $0x3,%edx + 407073: 0f 84 47 20 00 00 je 4090c0 + 407079: 83 fa 01 cmp $0x1,%edx + 40707c: 0f 84 64 20 00 00 je 4090e6 + 407082: 48 89 c7 mov %rax,%rdi + 407085: e8 26 6d 01 00 callq 41ddb0 <__cfree> + 40708a: 48 8b 04 24 mov (%rsp),%rax + 40708e: 48 8b 40 10 mov 0x10(%rax),%rax + 407092: 48 85 c0 test %rax,%rax + 407095: 74 25 je 4070bc + 407097: 8b 10 mov (%rax),%edx + 407099: 83 fa 02 cmp $0x2,%edx + 40709c: 0f 84 01 0f 00 00 je 407fa3 + 4070a2: 83 fa 03 cmp $0x3,%edx + 4070a5: 0f 84 e5 0e 00 00 je 407f90 + 4070ab: 83 fa 01 cmp $0x1,%edx + 4070ae: 0f 84 02 0f 00 00 je 407fb6 + 4070b4: 48 89 c7 mov %rax,%rdi + 4070b7: e8 f4 6c 01 00 callq 41ddb0 <__cfree> + 4070bc: 48 8b 04 24 mov (%rsp),%rax + 4070c0: 48 8b 40 08 mov 0x8(%rax),%rax + 4070c4: 48 85 c0 test %rax,%rax + 4070c7: 0f 84 3b fb ff ff je 406c08 + 4070cd: 8b 10 mov (%rax),%edx + 4070cf: 83 fa 02 cmp $0x2,%edx + 4070d2: 74 2f je 407103 + 4070d4: 83 fa 03 cmp $0x3,%edx + 4070d7: 74 17 je 4070f0 + 4070d9: 83 fa 01 cmp $0x1,%edx + 4070dc: 74 38 je 407116 + 4070de: 48 89 c7 mov %rax,%rdi + 4070e1: e8 ca 6c 01 00 callq 41ddb0 <__cfree> + 4070e6: e9 1d fb ff ff jmpq 406c08 + 4070eb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4070f0: 48 8b 78 18 mov 0x18(%rax),%rdi + 4070f4: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4070f9: e8 12 eb ff ff callq 405c10 <__gettext_free_exp> + 4070fe: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 407103: 48 8b 78 10 mov 0x10(%rax),%rdi + 407107: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40710c: e8 ff ea ff ff callq 405c10 <__gettext_free_exp> + 407111: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 407116: 48 8b 78 08 mov 0x8(%rax),%rdi + 40711a: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40711f: e8 ec ea ff ff callq 405c10 <__gettext_free_exp> + 407124: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 407129: 48 89 c7 mov %rax,%rdi + 40712c: e8 7f 6c 01 00 callq 41ddb0 <__cfree> + 407131: e9 d2 fa ff ff jmpq 406c08 + 407136: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 40713d: 00 00 00 + 407140: 48 8b 04 24 mov (%rsp),%rax + 407144: 48 8b 40 18 mov 0x18(%rax),%rax + 407148: 48 85 c0 test %rax,%rax + 40714b: 74 25 je 407172 + 40714d: 8b 10 mov (%rax),%edx + 40714f: 83 fa 02 cmp $0x2,%edx + 407152: 0f 84 cb 21 00 00 je 409323 + 407158: 83 fa 03 cmp $0x3,%edx + 40715b: 0f 84 af 21 00 00 je 409310 + 407161: 83 fa 01 cmp $0x1,%edx + 407164: 0f 84 cc 21 00 00 je 409336 + 40716a: 48 89 c7 mov %rax,%rdi + 40716d: e8 3e 6c 01 00 callq 41ddb0 <__cfree> + 407172: 48 8b 04 24 mov (%rsp),%rax + 407176: 48 8b 40 10 mov 0x10(%rax),%rax + 40717a: 48 85 c0 test %rax,%rax + 40717d: 74 25 je 4071a4 + 40717f: 8b 10 mov (%rax),%edx + 407181: 83 fa 02 cmp $0x2,%edx + 407184: 0f 84 59 0d 00 00 je 407ee3 + 40718a: 83 fa 03 cmp $0x3,%edx + 40718d: 0f 84 3d 0d 00 00 je 407ed0 + 407193: 83 fa 01 cmp $0x1,%edx + 407196: 0f 84 5a 0d 00 00 je 407ef6 + 40719c: 48 89 c7 mov %rax,%rdi + 40719f: e8 0c 6c 01 00 callq 41ddb0 <__cfree> + 4071a4: 48 8b 04 24 mov (%rsp),%rax + 4071a8: 48 8b 40 08 mov 0x8(%rax),%rax + 4071ac: 48 85 c0 test %rax,%rax + 4071af: 0f 84 48 f5 ff ff je 4066fd + 4071b5: 8b 10 mov (%rax),%edx + 4071b7: 83 fa 02 cmp $0x2,%edx + 4071ba: 74 2f je 4071eb + 4071bc: 83 fa 03 cmp $0x3,%edx + 4071bf: 74 17 je 4071d8 + 4071c1: 83 fa 01 cmp $0x1,%edx + 4071c4: 74 38 je 4071fe + 4071c6: 48 89 c7 mov %rax,%rdi + 4071c9: e8 e2 6b 01 00 callq 41ddb0 <__cfree> + 4071ce: e9 2a f5 ff ff jmpq 4066fd + 4071d3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4071d8: 48 8b 78 18 mov 0x18(%rax),%rdi + 4071dc: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4071e1: e8 2a ea ff ff callq 405c10 <__gettext_free_exp> + 4071e6: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4071eb: 48 8b 78 10 mov 0x10(%rax),%rdi + 4071ef: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4071f4: e8 17 ea ff ff callq 405c10 <__gettext_free_exp> + 4071f9: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4071fe: 48 8b 78 08 mov 0x8(%rax),%rdi + 407202: 48 89 44 24 08 mov %rax,0x8(%rsp) + 407207: e8 04 ea ff ff callq 405c10 <__gettext_free_exp> + 40720c: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 407211: 48 89 c7 mov %rax,%rdi + 407214: e8 97 6b 01 00 callq 41ddb0 <__cfree> + 407219: e9 df f4 ff ff jmpq 4066fd + 40721e: 66 90 xchg %ax,%ax + 407220: 48 8b 04 24 mov (%rsp),%rax + 407224: 48 8b 40 18 mov 0x18(%rax),%rax + 407228: 48 85 c0 test %rax,%rax + 40722b: 74 25 je 407252 + 40722d: 8b 10 mov (%rax),%edx + 40722f: 83 fa 02 cmp $0x2,%edx + 407232: 0f 84 ad 20 00 00 je 4092e5 + 407238: 83 fa 03 cmp $0x3,%edx + 40723b: 0f 84 91 20 00 00 je 4092d2 + 407241: 83 fa 01 cmp $0x1,%edx + 407244: 0f 84 ae 20 00 00 je 4092f8 + 40724a: 48 89 c7 mov %rax,%rdi + 40724d: e8 5e 6b 01 00 callq 41ddb0 <__cfree> + 407252: 48 8b 04 24 mov (%rsp),%rax + 407256: 48 8b 40 10 mov 0x10(%rax),%rax + 40725a: 48 85 c0 test %rax,%rax + 40725d: 74 25 je 407284 + 40725f: 8b 10 mov (%rax),%edx + 407261: 83 fa 02 cmp $0x2,%edx + 407264: 0f 84 f9 0c 00 00 je 407f63 + 40726a: 83 fa 03 cmp $0x3,%edx + 40726d: 0f 84 dd 0c 00 00 je 407f50 + 407273: 83 fa 01 cmp $0x1,%edx + 407276: 0f 84 fa 0c 00 00 je 407f76 + 40727c: 48 89 c7 mov %rax,%rdi + 40727f: e8 2c 6b 01 00 callq 41ddb0 <__cfree> + 407284: 48 8b 04 24 mov (%rsp),%rax + 407288: 48 8b 40 08 mov 0x8(%rax),%rax + 40728c: 48 85 c0 test %rax,%rax + 40728f: 0f 84 bd f8 ff ff je 406b52 + 407295: 8b 10 mov (%rax),%edx + 407297: 83 fa 02 cmp $0x2,%edx + 40729a: 74 2f je 4072cb + 40729c: 83 fa 03 cmp $0x3,%edx + 40729f: 74 17 je 4072b8 + 4072a1: 83 fa 01 cmp $0x1,%edx + 4072a4: 74 38 je 4072de + 4072a6: 48 89 c7 mov %rax,%rdi + 4072a9: e8 02 6b 01 00 callq 41ddb0 <__cfree> + 4072ae: e9 9f f8 ff ff jmpq 406b52 + 4072b3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4072b8: 48 8b 78 18 mov 0x18(%rax),%rdi + 4072bc: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4072c1: e8 4a e9 ff ff callq 405c10 <__gettext_free_exp> + 4072c6: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4072cb: 48 8b 78 10 mov 0x10(%rax),%rdi + 4072cf: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4072d4: e8 37 e9 ff ff callq 405c10 <__gettext_free_exp> + 4072d9: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4072de: 48 8b 78 08 mov 0x8(%rax),%rdi + 4072e2: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4072e7: e8 24 e9 ff ff callq 405c10 <__gettext_free_exp> + 4072ec: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4072f1: 48 89 c7 mov %rax,%rdi + 4072f4: e8 b7 6a 01 00 callq 41ddb0 <__cfree> + 4072f9: e9 54 f8 ff ff jmpq 406b52 + 4072fe: 66 90 xchg %ax,%ax + 407300: 48 8b 04 24 mov (%rsp),%rax + 407304: 48 8b 40 18 mov 0x18(%rax),%rax + 407308: 48 85 c0 test %rax,%rax + 40730b: 74 25 je 407332 + 40730d: 8b 10 mov (%rax),%edx + 40730f: 83 fa 02 cmp $0x2,%edx + 407312: 0f 84 c9 22 00 00 je 4095e1 + 407318: 83 fa 03 cmp $0x3,%edx + 40731b: 0f 84 ad 22 00 00 je 4095ce + 407321: 83 fa 01 cmp $0x1,%edx + 407324: 0f 84 ca 22 00 00 je 4095f4 + 40732a: 48 89 c7 mov %rax,%rdi + 40732d: e8 7e 6a 01 00 callq 41ddb0 <__cfree> + 407332: 48 8b 04 24 mov (%rsp),%rax + 407336: 48 8b 40 10 mov 0x10(%rax),%rax + 40733a: 48 85 c0 test %rax,%rax + 40733d: 74 25 je 407364 + 40733f: 8b 10 mov (%rax),%edx + 407341: 83 fa 02 cmp $0x2,%edx + 407344: 0f 84 99 0c 00 00 je 407fe3 + 40734a: 83 fa 03 cmp $0x3,%edx + 40734d: 0f 84 7d 0c 00 00 je 407fd0 + 407353: 83 fa 01 cmp $0x1,%edx + 407356: 0f 84 9a 0c 00 00 je 407ff6 + 40735c: 48 89 c7 mov %rax,%rdi + 40735f: e8 4c 6a 01 00 callq 41ddb0 <__cfree> + 407364: 48 8b 04 24 mov (%rsp),%rax + 407368: 48 8b 40 08 mov 0x8(%rax),%rax + 40736c: 48 85 c0 test %rax,%rax + 40736f: 0f 84 f3 f6 ff ff je 406a68 + 407375: 8b 10 mov (%rax),%edx + 407377: 83 fa 02 cmp $0x2,%edx + 40737a: 74 2f je 4073ab + 40737c: 83 fa 03 cmp $0x3,%edx + 40737f: 74 17 je 407398 + 407381: 83 fa 01 cmp $0x1,%edx + 407384: 74 38 je 4073be + 407386: 48 89 c7 mov %rax,%rdi + 407389: e8 22 6a 01 00 callq 41ddb0 <__cfree> + 40738e: e9 d5 f6 ff ff jmpq 406a68 + 407393: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 407398: 48 8b 78 18 mov 0x18(%rax),%rdi + 40739c: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4073a1: e8 6a e8 ff ff callq 405c10 <__gettext_free_exp> + 4073a6: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4073ab: 48 8b 78 10 mov 0x10(%rax),%rdi + 4073af: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4073b4: e8 57 e8 ff ff callq 405c10 <__gettext_free_exp> + 4073b9: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4073be: 48 8b 78 08 mov 0x8(%rax),%rdi + 4073c2: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4073c7: e8 44 e8 ff ff callq 405c10 <__gettext_free_exp> + 4073cc: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4073d1: 48 89 c7 mov %rax,%rdi + 4073d4: e8 d7 69 01 00 callq 41ddb0 <__cfree> + 4073d9: e9 8a f6 ff ff jmpq 406a68 + 4073de: 66 90 xchg %ax,%ax + 4073e0: 48 8b 50 18 mov 0x18(%rax),%rdx + 4073e4: 48 85 d2 test %rdx,%rdx + 4073e7: 74 2d je 407416 + 4073e9: 8b 0a mov (%rdx),%ecx + 4073eb: 83 f9 02 cmp $0x2,%ecx + 4073ee: 0f 84 27 0f 00 00 je 40831b + 4073f4: 83 f9 03 cmp $0x3,%ecx + 4073f7: 0f 84 03 0f 00 00 je 408300 + 4073fd: 83 f9 01 cmp $0x1,%ecx + 407400: 0f 84 30 0f 00 00 je 408336 + 407406: 48 89 d7 mov %rdx,%rdi + 407409: 48 89 04 24 mov %rax,(%rsp) + 40740d: e8 9e 69 01 00 callq 41ddb0 <__cfree> + 407412: 48 8b 04 24 mov (%rsp),%rax + 407416: 48 8b 50 10 mov 0x10(%rax),%rdx + 40741a: 48 85 d2 test %rdx,%rdx + 40741d: 0f 84 7e f5 ff ff je 4069a1 + 407423: 8b 0a mov (%rdx),%ecx + 407425: 83 f9 02 cmp $0x2,%ecx + 407428: 0f 84 2d f5 ff ff je 40695b + 40742e: 83 f9 03 cmp $0x3,%ecx + 407431: 0f 84 09 f5 ff ff je 406940 + 407437: 83 f9 01 cmp $0x1,%ecx + 40743a: 0f 84 36 f5 ff ff je 406976 + 407440: 48 89 d7 mov %rdx,%rdi + 407443: 48 89 04 24 mov %rax,(%rsp) + 407447: e8 64 69 01 00 callq 41ddb0 <__cfree> + 40744c: 48 8b 04 24 mov (%rsp),%rax + 407450: e9 4c f5 ff ff jmpq 4069a1 + 407455: 0f 1f 00 nopl (%rax) + 407458: 49 8b 47 18 mov 0x18(%r15),%rax + 40745c: 48 85 c0 test %rax,%rax + 40745f: 74 25 je 407486 + 407461: 8b 10 mov (%rax),%edx + 407463: 83 fa 02 cmp $0x2,%edx + 407466: 0f 84 58 23 00 00 je 4097c4 + 40746c: 83 fa 03 cmp $0x3,%edx + 40746f: 0f 84 3e 23 00 00 je 4097b3 + 407475: 83 fa 01 cmp $0x1,%edx + 407478: 0f 84 57 23 00 00 je 4097d5 + 40747e: 48 89 c7 mov %rax,%rdi + 407481: e8 2a 69 01 00 callq 41ddb0 <__cfree> + 407486: 49 8b 47 10 mov 0x10(%r15),%rax + 40748a: 48 85 c0 test %rax,%rax + 40748d: 48 89 04 24 mov %rax,(%rsp) + 407491: 74 26 je 4074b9 + 407493: 8b 00 mov (%rax),%eax + 407495: 83 f8 02 cmp $0x2,%eax + 407498: 0f 84 7f 0c 00 00 je 40811d + 40749e: 83 f8 03 cmp $0x3,%eax + 4074a1: 0f 84 69 0c 00 00 je 408110 + 4074a7: 83 f8 01 cmp $0x1,%eax + 4074aa: 0f 84 9f 0c 00 00 je 40814f + 4074b0: 48 8b 3c 24 mov (%rsp),%rdi + 4074b4: e8 f7 68 01 00 callq 41ddb0 <__cfree> + 4074b9: 49 8b 47 08 mov 0x8(%r15),%rax + 4074bd: 48 85 c0 test %rax,%rax + 4074c0: 48 89 04 24 mov %rax,(%rsp) + 4074c4: 0f 84 6c f3 ff ff je 406836 + 4074ca: 8b 00 mov (%rax),%eax + 4074cc: 83 f8 02 cmp $0x2,%eax + 4074cf: 74 2c je 4074fd + 4074d1: 83 f8 03 cmp $0x3,%eax + 4074d4: 74 1a je 4074f0 + 4074d6: 83 f8 01 cmp $0x1,%eax + 4074d9: 74 54 je 40752f + 4074db: 48 8b 3c 24 mov (%rsp),%rdi + 4074df: e8 cc 68 01 00 callq 41ddb0 <__cfree> + 4074e4: e9 4d f3 ff ff jmpq 406836 + 4074e9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4074f0: 48 8b 04 24 mov (%rsp),%rax + 4074f4: 48 8b 78 18 mov 0x18(%rax),%rdi + 4074f8: e8 13 e7 ff ff callq 405c10 <__gettext_free_exp> + 4074fd: 48 8b 04 24 mov (%rsp),%rax + 407501: 48 8b 40 10 mov 0x10(%rax),%rax + 407505: 48 85 c0 test %rax,%rax + 407508: 74 25 je 40752f + 40750a: 8b 10 mov (%rax),%edx + 40750c: 83 fa 02 cmp $0x2,%edx + 40750f: 0f 84 48 12 00 00 je 40875d + 407515: 83 fa 03 cmp $0x3,%edx + 407518: 0f 84 2c 12 00 00 je 40874a + 40751e: 83 fa 01 cmp $0x1,%edx + 407521: 0f 84 49 12 00 00 je 408770 + 407527: 48 89 c7 mov %rax,%rdi + 40752a: e8 81 68 01 00 callq 41ddb0 <__cfree> + 40752f: 48 8b 04 24 mov (%rsp),%rax + 407533: 48 8b 40 08 mov 0x8(%rax),%rax + 407537: 48 85 c0 test %rax,%rax + 40753a: 74 9f je 4074db + 40753c: 8b 10 mov (%rax),%edx + 40753e: 83 fa 02 cmp $0x2,%edx + 407541: 0f 84 1c 09 00 00 je 407e63 + 407547: 83 fa 03 cmp $0x3,%edx + 40754a: 0f 84 00 09 00 00 je 407e50 + 407550: 83 fa 01 cmp $0x1,%edx + 407553: 0f 84 1d 09 00 00 je 407e76 + 407559: 48 89 c7 mov %rax,%rdi + 40755c: e8 4f 68 01 00 callq 41ddb0 <__cfree> + 407561: 48 8b 3c 24 mov (%rsp),%rdi + 407565: e8 46 68 01 00 callq 41ddb0 <__cfree> + 40756a: e9 c7 f2 ff ff jmpq 406836 + 40756f: 90 nop + 407570: 49 8b 47 18 mov 0x18(%r15),%rax + 407574: 48 85 c0 test %rax,%rax + 407577: 74 25 je 40759e + 407579: 8b 10 mov (%rax),%edx + 40757b: 83 fa 02 cmp $0x2,%edx + 40757e: 0f 84 e3 0d 00 00 je 408367 + 407584: 83 fa 03 cmp $0x3,%edx + 407587: 0f 84 c9 0d 00 00 je 408356 + 40758d: 83 fa 01 cmp $0x1,%edx + 407590: 0f 84 e2 0d 00 00 je 408378 + 407596: 48 89 c7 mov %rax,%rdi + 407599: e8 12 68 01 00 callq 41ddb0 <__cfree> + 40759e: 49 8b 47 10 mov 0x10(%r15),%rax + 4075a2: 48 85 c0 test %rax,%rax + 4075a5: 48 89 04 24 mov %rax,(%rsp) + 4075a9: 0f 84 75 f5 ff ff je 406b24 + 4075af: 8b 00 mov (%rax),%eax + 4075b1: 83 f8 02 cmp $0x2,%eax + 4075b4: 0f 84 fd f4 ff ff je 406ab7 + 4075ba: 83 f8 03 cmp $0x3,%eax + 4075bd: 0f 84 dd 20 00 00 je 4096a0 + 4075c3: 83 f8 01 cmp $0x1,%eax + 4075c6: 0f 84 1d f5 ff ff je 406ae9 + 4075cc: 48 8b 3c 24 mov (%rsp),%rdi + 4075d0: e8 db 67 01 00 callq 41ddb0 <__cfree> + 4075d5: e9 4a f5 ff ff jmpq 406b24 + 4075da: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4075e0: 49 8b 47 18 mov 0x18(%r15),%rax + 4075e4: 48 85 c0 test %rax,%rax + 4075e7: 74 25 je 40760e + 4075e9: 8b 10 mov (%rax),%edx + 4075eb: 83 fa 02 cmp $0x2,%edx + 4075ee: 0f 84 f7 0e 00 00 je 4084eb + 4075f4: 83 fa 03 cmp $0x3,%edx + 4075f7: 0f 84 dd 0e 00 00 je 4084da + 4075fd: 83 fa 01 cmp $0x1,%edx + 407600: 0f 84 f6 0e 00 00 je 4084fc + 407606: 48 89 c7 mov %rax,%rdi + 407609: e8 a2 67 01 00 callq 41ddb0 <__cfree> + 40760e: 49 8b 47 10 mov 0x10(%r15),%rax + 407612: 48 85 c0 test %rax,%rax + 407615: 48 89 04 24 mov %rax,(%rsp) + 407619: 0f 84 1b f4 ff ff je 406a3a + 40761f: 8b 00 mov (%rax),%eax + 407621: 83 f8 02 cmp $0x2,%eax + 407624: 0f 84 a3 f3 ff ff je 4069cd + 40762a: 83 f8 03 cmp $0x3,%eax + 40762d: 0f 84 8d f3 ff ff je 4069c0 + 407633: 83 f8 01 cmp $0x1,%eax + 407636: 0f 84 c3 f3 ff ff je 4069ff + 40763c: 48 8b 3c 24 mov (%rsp),%rdi + 407640: e8 6b 67 01 00 callq 41ddb0 <__cfree> + 407645: e9 f0 f3 ff ff jmpq 406a3a + 40764a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 407650: 49 8b 47 18 mov 0x18(%r15),%rax + 407654: 48 85 c0 test %rax,%rax + 407657: 74 25 je 40767e + 407659: 8b 10 mov (%rax),%edx + 40765b: 83 fa 02 cmp $0x2,%edx + 40765e: 0f 84 08 22 00 00 je 40986c + 407664: 83 fa 03 cmp $0x3,%edx + 407667: 0f 84 ee 21 00 00 je 40985b + 40766d: 83 fa 01 cmp $0x1,%edx + 407670: 0f 84 07 22 00 00 je 40987d + 407676: 48 89 c7 mov %rax,%rdi + 407679: e8 32 67 01 00 callq 41ddb0 <__cfree> + 40767e: 49 8b 47 10 mov 0x10(%r15),%rax + 407682: 48 85 c0 test %rax,%rax + 407685: 48 89 04 24 mov %rax,(%rsp) + 407689: 74 26 je 4076b1 + 40768b: 8b 00 mov (%rax),%eax + 40768d: 83 f8 02 cmp $0x2,%eax + 407690: 0f 84 87 0b 00 00 je 40821d + 407696: 83 f8 03 cmp $0x3,%eax + 407699: 0f 84 71 0b 00 00 je 408210 + 40769f: 83 f8 01 cmp $0x1,%eax + 4076a2: 0f 84 a7 0b 00 00 je 40824f + 4076a8: 48 8b 3c 24 mov (%rsp),%rdi + 4076ac: e8 ff 66 01 00 callq 41ddb0 <__cfree> + 4076b1: 49 8b 47 08 mov 0x8(%r15),%rax + 4076b5: 48 85 c0 test %rax,%rax + 4076b8: 48 89 04 24 mov %rax,(%rsp) + 4076bc: 0f 84 d4 f0 ff ff je 406796 + 4076c2: 8b 00 mov (%rax),%eax + 4076c4: 83 f8 02 cmp $0x2,%eax + 4076c7: 74 2c je 4076f5 + 4076c9: 83 f8 03 cmp $0x3,%eax + 4076cc: 74 1a je 4076e8 + 4076ce: 83 f8 01 cmp $0x1,%eax + 4076d1: 74 54 je 407727 + 4076d3: 48 8b 3c 24 mov (%rsp),%rdi + 4076d7: e8 d4 66 01 00 callq 41ddb0 <__cfree> + 4076dc: e9 b5 f0 ff ff jmpq 406796 + 4076e1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4076e8: 48 8b 04 24 mov (%rsp),%rax + 4076ec: 48 8b 78 18 mov 0x18(%rax),%rdi + 4076f0: e8 1b e5 ff ff callq 405c10 <__gettext_free_exp> + 4076f5: 48 8b 04 24 mov (%rsp),%rax + 4076f9: 48 8b 40 10 mov 0x10(%rax),%rax + 4076fd: 48 85 c0 test %rax,%rax + 407700: 74 25 je 407727 + 407702: 8b 10 mov (%rax),%edx + 407704: 83 fa 02 cmp $0x2,%edx + 407707: 0f 84 cc 10 00 00 je 4087d9 + 40770d: 83 fa 03 cmp $0x3,%edx + 407710: 0f 84 b0 10 00 00 je 4087c6 + 407716: 83 fa 01 cmp $0x1,%edx + 407719: 0f 84 cd 10 00 00 je 4087ec + 40771f: 48 89 c7 mov %rax,%rdi + 407722: e8 89 66 01 00 callq 41ddb0 <__cfree> + 407727: 48 8b 04 24 mov (%rsp),%rax + 40772b: 48 8b 40 08 mov 0x8(%rax),%rax + 40772f: 48 85 c0 test %rax,%rax + 407732: 74 9f je 4076d3 + 407734: 8b 10 mov (%rax),%edx + 407736: 83 fa 02 cmp $0x2,%edx + 407739: 0f 84 24 09 00 00 je 408063 + 40773f: 83 fa 03 cmp $0x3,%edx + 407742: 0f 84 08 09 00 00 je 408050 + 407748: 83 fa 01 cmp $0x1,%edx + 40774b: 0f 84 25 09 00 00 je 408076 + 407751: 48 89 c7 mov %rax,%rdi + 407754: e8 57 66 01 00 callq 41ddb0 <__cfree> + 407759: 48 8b 3c 24 mov (%rsp),%rdi + 40775d: e8 4e 66 01 00 callq 41ddb0 <__cfree> + 407762: e9 2f f0 ff ff jmpq 406796 + 407767: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 40776e: 00 00 + 407770: 49 8b 47 18 mov 0x18(%r15),%rax + 407774: 48 85 c0 test %rax,%rax + 407777: 74 25 je 40779e + 407779: 8b 10 mov (%rax),%edx + 40777b: 83 fa 02 cmp $0x2,%edx + 40777e: 0f 84 a8 22 00 00 je 409a2c + 407784: 83 fa 03 cmp $0x3,%edx + 407787: 0f 84 8e 22 00 00 je 409a1b + 40778d: 83 fa 01 cmp $0x1,%edx + 407790: 0f 84 a7 22 00 00 je 409a3d + 407796: 48 89 c7 mov %rax,%rdi + 407799: e8 12 66 01 00 callq 41ddb0 <__cfree> + 40779e: 49 8b 47 10 mov 0x10(%r15),%rax + 4077a2: 48 85 c0 test %rax,%rax + 4077a5: 48 89 04 24 mov %rax,(%rsp) + 4077a9: 74 26 je 4077d1 + 4077ab: 8b 00 mov (%rax),%eax + 4077ad: 83 f8 02 cmp $0x2,%eax + 4077b0: 0f 84 e7 09 00 00 je 40819d + 4077b6: 83 f8 03 cmp $0x3,%eax + 4077b9: 0f 84 d1 09 00 00 je 408190 + 4077bf: 83 f8 01 cmp $0x1,%eax + 4077c2: 0f 84 07 0a 00 00 je 4081cf + 4077c8: 48 8b 3c 24 mov (%rsp),%rdi + 4077cc: e8 df 65 01 00 callq 41ddb0 <__cfree> + 4077d1: 49 8b 47 08 mov 0x8(%r15),%rax + 4077d5: 48 85 c0 test %rax,%rax + 4077d8: 48 89 04 24 mov %rax,(%rsp) + 4077dc: 0f 84 db f4 ff ff je 406cbd + 4077e2: 8b 00 mov (%rax),%eax + 4077e4: 83 f8 02 cmp $0x2,%eax + 4077e7: 74 2c je 407815 + 4077e9: 83 f8 03 cmp $0x3,%eax + 4077ec: 74 1a je 407808 + 4077ee: 83 f8 01 cmp $0x1,%eax + 4077f1: 74 54 je 407847 + 4077f3: 48 8b 3c 24 mov (%rsp),%rdi + 4077f7: e8 b4 65 01 00 callq 41ddb0 <__cfree> + 4077fc: e9 bc f4 ff ff jmpq 406cbd + 407801: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 407808: 48 8b 04 24 mov (%rsp),%rax + 40780c: 48 8b 78 18 mov 0x18(%rax),%rdi + 407810: e8 fb e3 ff ff callq 405c10 <__gettext_free_exp> + 407815: 48 8b 04 24 mov (%rsp),%rax + 407819: 48 8b 40 10 mov 0x10(%rax),%rax + 40781d: 48 85 c0 test %rax,%rax + 407820: 74 25 je 407847 + 407822: 8b 10 mov (%rax),%edx + 407824: 83 fa 02 cmp $0x2,%edx + 407827: 0f 84 f2 0e 00 00 je 40871f + 40782d: 83 fa 03 cmp $0x3,%edx + 407830: 0f 84 d6 0e 00 00 je 40870c + 407836: 83 fa 01 cmp $0x1,%edx + 407839: 0f 84 f3 0e 00 00 je 408732 + 40783f: 48 89 c7 mov %rax,%rdi + 407842: e8 69 65 01 00 callq 41ddb0 <__cfree> + 407847: 48 8b 04 24 mov (%rsp),%rax + 40784b: 48 8b 40 08 mov 0x8(%rax),%rax + 40784f: 48 85 c0 test %rax,%rax + 407852: 74 9f je 4077f3 + 407854: 8b 10 mov (%rax),%edx + 407856: 83 fa 02 cmp $0x2,%edx + 407859: 0f 84 c4 07 00 00 je 408023 + 40785f: 83 fa 03 cmp $0x3,%edx + 407862: 0f 84 a8 07 00 00 je 408010 + 407868: 83 fa 01 cmp $0x1,%edx + 40786b: 0f 84 c5 07 00 00 je 408036 + 407871: 48 89 c7 mov %rax,%rdi + 407874: e8 37 65 01 00 callq 41ddb0 <__cfree> + 407879: 48 8b 3c 24 mov (%rsp),%rdi + 40787d: e8 2e 65 01 00 callq 41ddb0 <__cfree> + 407882: e9 36 f4 ff ff jmpq 406cbd + 407887: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 40788e: 00 00 + 407890: 49 8b 47 18 mov 0x18(%r15),%rax + 407894: 48 85 c0 test %rax,%rax + 407897: 74 25 je 4078be + 407899: 8b 10 mov (%rax),%edx + 40789b: 83 fa 02 cmp $0x2,%edx + 40789e: 0f 84 85 0b 00 00 je 408429 + 4078a4: 83 fa 03 cmp $0x3,%edx + 4078a7: 0f 84 6b 0b 00 00 je 408418 + 4078ad: 83 fa 01 cmp $0x1,%edx + 4078b0: 0f 84 84 0b 00 00 je 40843a + 4078b6: 48 89 c7 mov %rax,%rdi + 4078b9: e8 f2 64 01 00 callq 41ddb0 <__cfree> + 4078be: 49 8b 47 10 mov 0x10(%r15),%rax + 4078c2: 48 85 c0 test %rax,%rax + 4078c5: 48 89 04 24 mov %rax,(%rsp) + 4078c9: 0f 84 0b f3 ff ff je 406bda + 4078cf: 8b 00 mov (%rax),%eax + 4078d1: 83 f8 02 cmp $0x2,%eax + 4078d4: 0f 84 93 f2 ff ff je 406b6d + 4078da: 83 f8 03 cmp $0x3,%eax + 4078dd: 0f 84 7d f2 ff ff je 406b60 + 4078e3: 83 f8 01 cmp $0x1,%eax + 4078e6: 0f 84 b3 f2 ff ff je 406b9f + 4078ec: 48 8b 3c 24 mov (%rsp),%rdi + 4078f0: e8 bb 64 01 00 callq 41ddb0 <__cfree> + 4078f5: e9 e0 f2 ff ff jmpq 406bda + 4078fa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 407900: 4d 8b 7d 18 mov 0x18(%r13),%r15 + 407904: 4d 85 ff test %r15,%r15 + 407907: 74 26 je 40792f + 407909: 41 8b 07 mov (%r15),%eax + 40790c: 83 f8 02 cmp $0x2,%eax + 40790f: 0f 84 3b 0d 00 00 je 408650 + 407915: 83 f8 03 cmp $0x3,%eax + 407918: 0f 84 29 0d 00 00 je 408647 + 40791e: 83 f8 01 cmp $0x1,%eax + 407921: 0f 84 32 0d 00 00 je 408659 + 407927: 4c 89 ff mov %r15,%rdi + 40792a: e8 81 64 01 00 callq 41ddb0 <__cfree> + 40792f: 4d 8b 7d 10 mov 0x10(%r13),%r15 + 407933: 4d 85 ff test %r15,%r15 + 407936: 0f 84 56 f3 ff ff je 406c92 + 40793c: 41 8b 07 mov (%r15),%eax + 40793f: 83 f8 02 cmp $0x2,%eax + 407942: 0f 84 e1 f2 ff ff je 406c29 + 407948: 83 f8 03 cmp $0x3,%eax + 40794b: 0f 84 cf f2 ff ff je 406c20 + 407951: 83 f8 01 cmp $0x1,%eax + 407954: 0f 84 fd f2 ff ff je 406c57 + 40795a: 4c 89 ff mov %r15,%rdi + 40795d: e8 4e 64 01 00 callq 41ddb0 <__cfree> + 407962: e9 2b f3 ff ff jmpq 406c92 + 407967: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 40796e: 00 00 + 407970: 48 8b 04 24 mov (%rsp),%rax + 407974: 48 8b 78 18 mov 0x18(%rax),%rdi + 407978: e8 93 e2 ff ff callq 405c10 <__gettext_free_exp> + 40797d: 48 8b 04 24 mov (%rsp),%rax + 407981: 48 8b 40 10 mov 0x10(%rax),%rax + 407985: 48 85 c0 test %rax,%rax + 407988: 74 25 je 4079af + 40798a: 8b 10 mov (%rax),%edx + 40798c: 83 fa 02 cmp $0x2,%edx + 40798f: 0f 84 0c 1b 00 00 je 4094a1 + 407995: 83 fa 03 cmp $0x3,%edx + 407998: 0f 84 f0 1a 00 00 je 40948e + 40799e: 83 fa 01 cmp $0x1,%edx + 4079a1: 0f 84 0d 1b 00 00 je 4094b4 + 4079a7: 48 89 c7 mov %rax,%rdi + 4079aa: e8 01 64 01 00 callq 41ddb0 <__cfree> + 4079af: 48 8b 04 24 mov (%rsp),%rax + 4079b3: 48 8b 40 08 mov 0x8(%rax),%rax + 4079b7: 48 85 c0 test %rax,%rax + 4079ba: 0f 84 30 eb ff ff je 4064f0 + 4079c0: 8b 10 mov (%rax),%edx + 4079c2: 83 fa 02 cmp $0x2,%edx + 4079c5: 0f 84 69 10 00 00 je 408a34 + 4079cb: 83 fa 03 cmp $0x3,%edx + 4079ce: 0f 84 4d 10 00 00 je 408a21 + 4079d4: 83 fa 01 cmp $0x1,%edx + 4079d7: 0f 84 6a 10 00 00 je 408a47 + 4079dd: 48 89 c7 mov %rax,%rdi + 4079e0: e8 cb 63 01 00 callq 41ddb0 <__cfree> + 4079e5: e9 06 eb ff ff jmpq 4064f0 + 4079ea: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4079f0: 48 8b 04 24 mov (%rsp),%rax + 4079f4: 48 8b 78 18 mov 0x18(%rax),%rdi + 4079f8: e8 13 e2 ff ff callq 405c10 <__gettext_free_exp> + 4079fd: 48 8b 04 24 mov (%rsp),%rax + 407a01: 48 8b 40 10 mov 0x10(%rax),%rax + 407a05: 48 85 c0 test %rax,%rax + 407a08: 74 25 je 407a2f + 407a0a: 8b 10 mov (%rax),%edx + 407a0c: 83 fa 02 cmp $0x2,%edx + 407a0f: 0f 84 0a 1c 00 00 je 40961f + 407a15: 83 fa 03 cmp $0x3,%edx + 407a18: 0f 84 ee 1b 00 00 je 40960c + 407a1e: 83 fa 01 cmp $0x1,%edx + 407a21: 0f 84 0b 1c 00 00 je 409632 + 407a27: 48 89 c7 mov %rax,%rdi + 407a2a: e8 81 63 01 00 callq 41ddb0 <__cfree> + 407a2f: 48 8b 04 24 mov (%rsp),%rax + 407a33: 48 8b 40 08 mov 0x8(%rax),%rax + 407a37: 48 85 c0 test %rax,%rax + 407a3a: 0f 84 8a ec ff ff je 4066ca + 407a40: 8b 10 mov (%rax),%edx + 407a42: 83 fa 02 cmp $0x2,%edx + 407a45: 0f 84 a3 10 00 00 je 408aee + 407a4b: 83 fa 03 cmp $0x3,%edx + 407a4e: 0f 84 87 10 00 00 je 408adb + 407a54: 83 fa 01 cmp $0x1,%edx + 407a57: 0f 84 a4 10 00 00 je 408b01 + 407a5d: 48 89 c7 mov %rax,%rdi + 407a60: e8 4b 63 01 00 callq 41ddb0 <__cfree> + 407a65: e9 60 ec ff ff jmpq 4066ca + 407a6a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 407a70: 48 8b 04 24 mov (%rsp),%rax + 407a74: 48 8b 78 18 mov 0x18(%rax),%rdi + 407a78: e8 93 e1 ff ff callq 405c10 <__gettext_free_exp> + 407a7d: 48 8b 04 24 mov (%rsp),%rax + 407a81: 48 8b 40 10 mov 0x10(%rax),%rax + 407a85: 48 85 c0 test %rax,%rax + 407a88: 74 25 je 407aaf + 407a8a: 8b 10 mov (%rax),%edx + 407a8c: 83 fa 02 cmp $0x2,%edx + 407a8f: 0f 84 66 17 00 00 je 4091fb + 407a95: 83 fa 03 cmp $0x3,%edx + 407a98: 0f 84 4a 17 00 00 je 4091e8 + 407a9e: 83 fa 01 cmp $0x1,%edx + 407aa1: 0f 84 67 17 00 00 je 40920e + 407aa7: 48 89 c7 mov %rax,%rdi + 407aaa: e8 01 63 01 00 callq 41ddb0 <__cfree> + 407aaf: 48 8b 04 24 mov (%rsp),%rax + 407ab3: 48 8b 40 08 mov 0x8(%rax),%rax + 407ab7: 48 85 c0 test %rax,%rax + 407aba: 0f 84 35 f3 ff ff je 406df5 + 407ac0: 8b 10 mov (%rax),%edx + 407ac2: 83 fa 02 cmp $0x2,%edx + 407ac5: 0f 84 e5 0f 00 00 je 408ab0 + 407acb: 83 fa 03 cmp $0x3,%edx + 407ace: 0f 84 c9 0f 00 00 je 408a9d + 407ad4: 83 fa 01 cmp $0x1,%edx + 407ad7: 0f 84 e6 0f 00 00 je 408ac3 + 407add: 48 89 c7 mov %rax,%rdi + 407ae0: e8 cb 62 01 00 callq 41ddb0 <__cfree> + 407ae5: e9 0b f3 ff ff jmpq 406df5 + 407aea: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 407af0: 48 8b 04 24 mov (%rsp),%rax + 407af4: 48 8b 78 18 mov 0x18(%rax),%rdi + 407af8: e8 13 e1 ff ff callq 405c10 <__gettext_free_exp> + 407afd: 48 8b 04 24 mov (%rsp),%rax + 407b01: 48 8b 40 10 mov 0x10(%rax),%rax + 407b05: 48 85 c0 test %rax,%rax + 407b08: 74 25 je 407b2f + 407b0a: 8b 10 mov (%rax),%edx + 407b0c: 83 fa 02 cmp $0x2,%edx + 407b0f: 0f 84 a8 16 00 00 je 4091bd + 407b15: 83 fa 03 cmp $0x3,%edx + 407b18: 0f 84 8c 16 00 00 je 4091aa + 407b1e: 83 fa 01 cmp $0x1,%edx + 407b21: 0f 84 a9 16 00 00 je 4091d0 + 407b27: 48 89 c7 mov %rax,%rdi + 407b2a: e8 81 62 01 00 callq 41ddb0 <__cfree> + 407b2f: 48 8b 04 24 mov (%rsp),%rax + 407b33: 48 8b 40 08 mov 0x8(%rax),%rax + 407b37: 48 85 c0 test %rax,%rax + 407b3a: 0f 84 f5 f3 ff ff je 406f35 + 407b40: 8b 10 mov (%rax),%edx + 407b42: 83 fa 02 cmp $0x2,%edx + 407b45: 0f 84 27 0f 00 00 je 408a72 + 407b4b: 83 fa 03 cmp $0x3,%edx + 407b4e: 0f 84 0b 0f 00 00 je 408a5f + 407b54: 83 fa 01 cmp $0x1,%edx + 407b57: 0f 84 28 0f 00 00 je 408a85 + 407b5d: 48 89 c7 mov %rax,%rdi + 407b60: e8 4b 62 01 00 callq 41ddb0 <__cfree> + 407b65: e9 cb f3 ff ff jmpq 406f35 + 407b6a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 407b70: 49 8b 7f 18 mov 0x18(%r15),%rdi + 407b74: e8 97 e0 ff ff callq 405c10 <__gettext_free_exp> + 407b79: 49 8b 47 10 mov 0x10(%r15),%rax + 407b7d: 48 85 c0 test %rax,%rax + 407b80: 74 25 je 407ba7 + 407b82: 8b 10 mov (%rax),%edx + 407b84: 83 fa 02 cmp $0x2,%edx + 407b87: 0f 84 bf 1d 00 00 je 40994c + 407b8d: 83 fa 03 cmp $0x3,%edx + 407b90: 0f 84 a5 1d 00 00 je 40993b + 407b96: 83 fa 01 cmp $0x1,%edx + 407b99: 0f 84 be 1d 00 00 je 40995d + 407b9f: 48 89 c7 mov %rax,%rdi + 407ba2: e8 09 62 01 00 callq 41ddb0 <__cfree> + 407ba7: 49 8b 47 08 mov 0x8(%r15),%rax + 407bab: 48 85 c0 test %rax,%rax + 407bae: 0f 84 2d ea ff ff je 4065e1 + 407bb4: 8b 10 mov (%rax),%edx + 407bb6: 83 fa 02 cmp $0x2,%edx + 407bb9: 0f 84 50 11 00 00 je 408d0f + 407bbf: 83 fa 03 cmp $0x3,%edx + 407bc2: 0f 84 36 11 00 00 je 408cfe + 407bc8: 83 fa 01 cmp $0x1,%edx + 407bcb: 0f 84 4f 11 00 00 je 408d20 + 407bd1: 48 89 c7 mov %rax,%rdi + 407bd4: e8 d7 61 01 00 callq 41ddb0 <__cfree> + 407bd9: e9 03 ea ff ff jmpq 4065e1 + 407bde: 66 90 xchg %ax,%ax + 407be0: 49 8b 7f 18 mov 0x18(%r15),%rdi + 407be4: e8 27 e0 ff ff callq 405c10 <__gettext_free_exp> + 407be9: 49 8b 47 10 mov 0x10(%r15),%rax + 407bed: 48 85 c0 test %rax,%rax + 407bf0: 74 25 je 407c17 + 407bf2: 8b 10 mov (%rax),%edx + 407bf4: 83 fa 02 cmp $0x2,%edx + 407bf7: 0f 84 e7 1a 00 00 je 4096e4 + 407bfd: 83 fa 03 cmp $0x3,%edx + 407c00: 0f 84 cd 1a 00 00 je 4096d3 + 407c06: 83 fa 01 cmp $0x1,%edx + 407c09: 0f 84 e6 1a 00 00 je 4096f5 + 407c0f: 48 89 c7 mov %rax,%rdi + 407c12: e8 99 61 01 00 callq 41ddb0 <__cfree> + 407c17: 49 8b 47 08 mov 0x8(%r15),%rax + 407c1b: 48 85 c0 test %rax,%rax + 407c1e: 0f 84 e3 eb ff ff je 406807 + 407c24: 8b 10 mov (%rax),%edx + 407c26: 83 fa 02 cmp $0x2,%edx + 407c29: 0f 84 5c 0f 00 00 je 408b8b + 407c2f: 83 fa 03 cmp $0x3,%edx + 407c32: 0f 84 42 0f 00 00 je 408b7a + 407c38: 83 fa 01 cmp $0x1,%edx + 407c3b: 0f 84 5b 0f 00 00 je 408b9c + 407c41: 48 89 c7 mov %rax,%rdi + 407c44: e8 67 61 01 00 callq 41ddb0 <__cfree> + 407c49: e9 b9 eb ff ff jmpq 406807 + 407c4e: 66 90 xchg %ax,%ax + 407c50: 49 8b 7f 18 mov 0x18(%r15),%rdi + 407c54: e8 b7 df ff ff callq 405c10 <__gettext_free_exp> + 407c59: 49 8b 47 10 mov 0x10(%r15),%rax + 407c5d: 48 85 c0 test %rax,%rax + 407c60: 74 25 je 407c87 + 407c62: 8b 10 mov (%rax),%edx + 407c64: 83 fa 02 cmp $0x2,%edx + 407c67: 0f 84 4f 1d 00 00 je 4099bc + 407c6d: 83 fa 03 cmp $0x3,%edx + 407c70: 0f 84 35 1d 00 00 je 4099ab + 407c76: 83 fa 01 cmp $0x1,%edx + 407c79: 0f 84 4e 1d 00 00 je 4099cd + 407c7f: 48 89 c7 mov %rax,%rdi + 407c82: e8 29 61 01 00 callq 41ddb0 <__cfree> + 407c87: 49 8b 47 08 mov 0x8(%r15),%rax + 407c8b: 48 85 c0 test %rax,%rax + 407c8e: 0f 84 5b ec ff ff je 4068ef + 407c94: 8b 10 mov (%rax),%edx + 407c96: 83 fa 02 cmp $0x2,%edx + 407c99: 0f 84 4d 0f 00 00 je 408bec + 407c9f: 83 fa 03 cmp $0x3,%edx + 407ca2: 0f 84 33 0f 00 00 je 408bdb + 407ca8: 83 fa 01 cmp $0x1,%edx + 407cab: 0f 84 4c 0f 00 00 je 408bfd + 407cb1: 48 89 c7 mov %rax,%rdi + 407cb4: e8 f7 60 01 00 callq 41ddb0 <__cfree> + 407cb9: e9 31 ec ff ff jmpq 4068ef + 407cbe: 66 90 xchg %ax,%ax + 407cc0: 49 8b 7f 18 mov 0x18(%r15),%rdi + 407cc4: e8 47 df ff ff callq 405c10 <__gettext_free_exp> + 407cc9: 49 8b 47 10 mov 0x10(%r15),%rax + 407ccd: 48 85 c0 test %rax,%rax + 407cd0: 74 25 je 407cf7 + 407cd2: 8b 10 mov (%rax),%edx + 407cd4: 83 fa 02 cmp $0x2,%edx + 407cd7: 0f 84 17 1d 00 00 je 4099f4 + 407cdd: 83 fa 03 cmp $0x3,%edx + 407ce0: 0f 84 fd 1c 00 00 je 4099e3 + 407ce6: 83 fa 01 cmp $0x1,%edx + 407ce9: 0f 84 16 1d 00 00 je 409a05 + 407cef: 48 89 c7 mov %rax,%rdi + 407cf2: e8 b9 60 01 00 callq 41ddb0 <__cfree> + 407cf7: 49 8b 47 08 mov 0x8(%r15),%rax + 407cfb: 48 85 c0 test %rax,%rax + 407cfe: 0f 84 22 f0 ff ff je 406d26 + 407d04: 8b 10 mov (%rax),%edx + 407d06: 83 fa 02 cmp $0x2,%edx + 407d09: 0f 84 1b 0e 00 00 je 408b2a + 407d0f: 83 fa 03 cmp $0x3,%edx + 407d12: 0f 84 01 0e 00 00 je 408b19 + 407d18: 83 fa 01 cmp $0x1,%edx + 407d1b: 0f 84 1a 0e 00 00 je 408b3b + 407d21: 48 89 c7 mov %rax,%rdi + 407d24: e8 87 60 01 00 callq 41ddb0 <__cfree> + 407d29: e9 f8 ef ff ff jmpq 406d26 + 407d2e: 66 90 xchg %ax,%ax + 407d30: 49 8b 7f 18 mov 0x18(%r15),%rdi + 407d34: e8 d7 de ff ff callq 405c10 <__gettext_free_exp> + 407d39: 49 8b 47 10 mov 0x10(%r15),%rax + 407d3d: 48 85 c0 test %rax,%rax + 407d40: 74 25 je 407d67 + 407d42: 8b 10 mov (%rax),%edx + 407d44: 83 fa 02 cmp $0x2,%edx + 407d47: 0f 84 3f 1a 00 00 je 40978c + 407d4d: 83 fa 03 cmp $0x3,%edx + 407d50: 0f 84 25 1a 00 00 je 40977b + 407d56: 83 fa 01 cmp $0x1,%edx + 407d59: 0f 84 3e 1a 00 00 je 40979d + 407d5f: 48 89 c7 mov %rax,%rdi + 407d62: e8 49 60 01 00 callq 41ddb0 <__cfree> + 407d67: 49 8b 47 08 mov 0x8(%r15),%rax + 407d6b: 48 85 c0 test %rax,%rax + 407d6e: 0f 84 f2 f0 ff ff je 406e66 + 407d74: 8b 10 mov (%rax),%edx + 407d76: 83 fa 02 cmp $0x2,%edx + 407d79: 0f 84 ce 0e 00 00 je 408c4d + 407d7f: 83 fa 03 cmp $0x3,%edx + 407d82: 0f 84 b4 0e 00 00 je 408c3c + 407d88: 83 fa 01 cmp $0x1,%edx + 407d8b: 0f 84 cd 0e 00 00 je 408c5e + 407d91: 48 89 c7 mov %rax,%rdi + 407d94: e8 17 60 01 00 callq 41ddb0 <__cfree> + 407d99: e9 c8 f0 ff ff jmpq 406e66 + 407d9e: 66 90 xchg %ax,%ax + 407da0: 49 8b 7f 18 mov 0x18(%r15),%rdi + 407da4: e8 67 de ff ff callq 405c10 <__gettext_free_exp> + 407da9: 49 8b 47 10 mov 0x10(%r15),%rax + 407dad: 48 85 c0 test %rax,%rax + 407db0: 74 25 je 407dd7 + 407db2: 8b 10 mov (%rax),%edx + 407db4: 83 fa 02 cmp $0x2,%edx + 407db7: 0f 84 97 19 00 00 je 409754 + 407dbd: 83 fa 03 cmp $0x3,%edx + 407dc0: 0f 84 7d 19 00 00 je 409743 + 407dc6: 83 fa 01 cmp $0x1,%edx + 407dc9: 0f 84 96 19 00 00 je 409765 + 407dcf: 48 89 c7 mov %rax,%rdi + 407dd2: e8 d9 5f 01 00 callq 41ddb0 <__cfree> + 407dd7: 49 8b 47 08 mov 0x8(%r15),%rax + 407ddb: 48 85 c0 test %rax,%rax + 407dde: 0f 84 83 e9 ff ff je 406767 + 407de4: 8b 10 mov (%rax),%edx + 407de6: 83 fa 02 cmp $0x2,%edx + 407de9: 0f 84 bf 0e 00 00 je 408cae + 407def: 83 fa 03 cmp $0x3,%edx + 407df2: 0f 84 a5 0e 00 00 je 408c9d + 407df8: 83 fa 01 cmp $0x1,%edx + 407dfb: 0f 84 be 0e 00 00 je 408cbf + 407e01: 48 89 c7 mov %rax,%rdi + 407e04: e8 a7 5f 01 00 callq 41ddb0 <__cfree> + 407e09: e9 59 e9 ff ff jmpq 406767 + 407e0e: 66 90 xchg %ax,%ax + 407e10: 48 8b 78 18 mov 0x18(%rax),%rdi + 407e14: 48 89 44 24 08 mov %rax,0x8(%rsp) + 407e19: e8 f2 dd ff ff callq 405c10 <__gettext_free_exp> + 407e1e: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 407e23: 48 8b 78 10 mov 0x10(%rax),%rdi + 407e27: 48 89 44 24 08 mov %rax,0x8(%rsp) + 407e2c: e8 df dd ff ff callq 405c10 <__gettext_free_exp> + 407e31: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 407e36: 48 8b 78 08 mov 0x8(%rax),%rdi + 407e3a: 48 89 44 24 08 mov %rax,0x8(%rsp) + 407e3f: e8 cc dd ff ff callq 405c10 <__gettext_free_exp> + 407e44: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 407e49: e9 7b ed ff ff jmpq 406bc9 + 407e4e: 66 90 xchg %ax,%ax + 407e50: 48 8b 78 18 mov 0x18(%rax),%rdi + 407e54: 48 89 44 24 08 mov %rax,0x8(%rsp) + 407e59: e8 b2 dd ff ff callq 405c10 <__gettext_free_exp> + 407e5e: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 407e63: 48 8b 78 10 mov 0x10(%rax),%rdi + 407e67: 48 89 44 24 08 mov %rax,0x8(%rsp) + 407e6c: e8 9f dd ff ff callq 405c10 <__gettext_free_exp> + 407e71: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 407e76: 48 8b 78 08 mov 0x8(%rax),%rdi + 407e7a: 48 89 44 24 08 mov %rax,0x8(%rsp) + 407e7f: e8 8c dd ff ff callq 405c10 <__gettext_free_exp> + 407e84: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 407e89: e9 cb f6 ff ff jmpq 407559 + 407e8e: 66 90 xchg %ax,%ax + 407e90: 48 8b 78 18 mov 0x18(%rax),%rdi + 407e94: 48 89 44 24 08 mov %rax,0x8(%rsp) + 407e99: e8 72 dd ff ff callq 405c10 <__gettext_free_exp> + 407e9e: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 407ea3: 48 8b 78 10 mov 0x10(%rax),%rdi + 407ea7: 48 89 44 24 08 mov %rax,0x8(%rsp) + 407eac: e8 5f dd ff ff callq 405c10 <__gettext_free_exp> + 407eb1: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 407eb6: 48 8b 78 08 mov 0x8(%rax),%rdi + 407eba: 48 89 44 24 08 mov %rax,0x8(%rsp) + 407ebf: e8 4c dd ff ff callq 405c10 <__gettext_free_exp> + 407ec4: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 407ec9: e9 5b eb ff ff jmpq 406a29 + 407ece: 66 90 xchg %ax,%ax + 407ed0: 48 8b 78 18 mov 0x18(%rax),%rdi + 407ed4: 48 89 44 24 08 mov %rax,0x8(%rsp) + 407ed9: e8 32 dd ff ff callq 405c10 <__gettext_free_exp> + 407ede: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 407ee3: 48 8b 78 10 mov 0x10(%rax),%rdi + 407ee7: 48 89 44 24 08 mov %rax,0x8(%rsp) + 407eec: e8 1f dd ff ff callq 405c10 <__gettext_free_exp> + 407ef1: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 407ef6: 48 8b 78 08 mov 0x8(%rax),%rdi + 407efa: 48 89 44 24 08 mov %rax,0x8(%rsp) + 407eff: e8 0c dd ff ff callq 405c10 <__gettext_free_exp> + 407f04: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 407f09: e9 8e f2 ff ff jmpq 40719c + 407f0e: 66 90 xchg %ax,%ax + 407f10: 48 8b 78 18 mov 0x18(%rax),%rdi + 407f14: 48 89 44 24 08 mov %rax,0x8(%rsp) + 407f19: e8 f2 dc ff ff callq 405c10 <__gettext_free_exp> + 407f1e: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 407f23: 48 8b 78 10 mov 0x10(%rax),%rdi + 407f27: 48 89 44 24 08 mov %rax,0x8(%rsp) + 407f2c: e8 df dc ff ff callq 405c10 <__gettext_free_exp> + 407f31: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 407f36: 48 8b 78 08 mov 0x8(%rax),%rdi + 407f3a: 48 89 44 24 08 mov %rax,0x8(%rsp) + 407f3f: e8 cc dc ff ff callq 405c10 <__gettext_free_exp> + 407f44: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 407f49: e9 c5 eb ff ff jmpq 406b13 + 407f4e: 66 90 xchg %ax,%ax + 407f50: 48 8b 78 18 mov 0x18(%rax),%rdi + 407f54: 48 89 44 24 08 mov %rax,0x8(%rsp) + 407f59: e8 b2 dc ff ff callq 405c10 <__gettext_free_exp> + 407f5e: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 407f63: 48 8b 78 10 mov 0x10(%rax),%rdi + 407f67: 48 89 44 24 08 mov %rax,0x8(%rsp) + 407f6c: e8 9f dc ff ff callq 405c10 <__gettext_free_exp> + 407f71: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 407f76: 48 8b 78 08 mov 0x8(%rax),%rdi + 407f7a: 48 89 44 24 08 mov %rax,0x8(%rsp) + 407f7f: e8 8c dc ff ff callq 405c10 <__gettext_free_exp> + 407f84: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 407f89: e9 ee f2 ff ff jmpq 40727c + 407f8e: 66 90 xchg %ax,%ax + 407f90: 48 8b 78 18 mov 0x18(%rax),%rdi + 407f94: 48 89 44 24 08 mov %rax,0x8(%rsp) + 407f99: e8 72 dc ff ff callq 405c10 <__gettext_free_exp> + 407f9e: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 407fa3: 48 8b 78 10 mov 0x10(%rax),%rdi + 407fa7: 48 89 44 24 08 mov %rax,0x8(%rsp) + 407fac: e8 5f dc ff ff callq 405c10 <__gettext_free_exp> + 407fb1: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 407fb6: 48 8b 78 08 mov 0x8(%rax),%rdi + 407fba: 48 89 44 24 08 mov %rax,0x8(%rsp) + 407fbf: e8 4c dc ff ff callq 405c10 <__gettext_free_exp> + 407fc4: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 407fc9: e9 e6 f0 ff ff jmpq 4070b4 + 407fce: 66 90 xchg %ax,%ax + 407fd0: 48 8b 78 18 mov 0x18(%rax),%rdi + 407fd4: 48 89 44 24 08 mov %rax,0x8(%rsp) + 407fd9: e8 32 dc ff ff callq 405c10 <__gettext_free_exp> + 407fde: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 407fe3: 48 8b 78 10 mov 0x10(%rax),%rdi + 407fe7: 48 89 44 24 08 mov %rax,0x8(%rsp) + 407fec: e8 1f dc ff ff callq 405c10 <__gettext_free_exp> + 407ff1: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 407ff6: 48 8b 78 08 mov 0x8(%rax),%rdi + 407ffa: 48 89 44 24 08 mov %rax,0x8(%rsp) + 407fff: e8 0c dc ff ff callq 405c10 <__gettext_free_exp> + 408004: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408009: e9 4e f3 ff ff jmpq 40735c + 40800e: 66 90 xchg %ax,%ax + 408010: 48 8b 78 18 mov 0x18(%rax),%rdi + 408014: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408019: e8 f2 db ff ff callq 405c10 <__gettext_free_exp> + 40801e: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408023: 48 8b 78 10 mov 0x10(%rax),%rdi + 408027: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40802c: e8 df db ff ff callq 405c10 <__gettext_free_exp> + 408031: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408036: 48 8b 78 08 mov 0x8(%rax),%rdi + 40803a: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40803f: e8 cc db ff ff callq 405c10 <__gettext_free_exp> + 408044: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408049: e9 23 f8 ff ff jmpq 407871 + 40804e: 66 90 xchg %ax,%ax + 408050: 48 8b 78 18 mov 0x18(%rax),%rdi + 408054: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408059: e8 b2 db ff ff callq 405c10 <__gettext_free_exp> + 40805e: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408063: 48 8b 78 10 mov 0x10(%rax),%rdi + 408067: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40806c: e8 9f db ff ff callq 405c10 <__gettext_free_exp> + 408071: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408076: 48 8b 78 08 mov 0x8(%rax),%rdi + 40807a: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40807f: e8 8c db ff ff callq 405c10 <__gettext_free_exp> + 408084: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408089: e9 c3 f6 ff ff jmpq 407751 + 40808e: 66 90 xchg %ax,%ax + 408090: 48 8b 04 24 mov (%rsp),%rax + 408094: 48 8b 78 18 mov 0x18(%rax),%rdi + 408098: e8 73 db ff ff callq 405c10 <__gettext_free_exp> + 40809d: 48 8b 04 24 mov (%rsp),%rax + 4080a1: 48 8b 40 10 mov 0x10(%rax),%rax + 4080a5: 48 85 c0 test %rax,%rax + 4080a8: 74 25 je 4080cf + 4080aa: 8b 10 mov (%rax),%edx + 4080ac: 83 fa 02 cmp $0x2,%edx + 4080af: 0f 84 3f 08 00 00 je 4088f4 + 4080b5: 83 fa 03 cmp $0x3,%edx + 4080b8: 0f 84 23 08 00 00 je 4088e1 + 4080be: 83 fa 01 cmp $0x1,%edx + 4080c1: 0f 84 40 08 00 00 je 408907 + 4080c7: 48 89 c7 mov %rax,%rdi + 4080ca: e8 e1 5c 01 00 callq 41ddb0 <__cfree> + 4080cf: 48 8b 04 24 mov (%rsp),%rax + 4080d3: 48 8b 40 08 mov 0x8(%rax),%rax + 4080d7: 48 85 c0 test %rax,%rax + 4080da: 0f 84 a1 eb ff ff je 406c81 + 4080e0: 8b 10 mov (%rax),%edx + 4080e2: 83 fa 02 cmp $0x2,%edx + 4080e5: 0f 84 41 0d 00 00 je 408e2c + 4080eb: 83 fa 03 cmp $0x3,%edx + 4080ee: 0f 84 25 0d 00 00 je 408e19 + 4080f4: 83 fa 01 cmp $0x1,%edx + 4080f7: 0f 84 42 0d 00 00 je 408e3f + 4080fd: 48 89 c7 mov %rax,%rdi + 408100: e8 ab 5c 01 00 callq 41ddb0 <__cfree> + 408105: e9 77 eb ff ff jmpq 406c81 + 40810a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 408110: 48 8b 04 24 mov (%rsp),%rax + 408114: 48 8b 78 18 mov 0x18(%rax),%rdi + 408118: e8 f3 da ff ff callq 405c10 <__gettext_free_exp> + 40811d: 48 8b 04 24 mov (%rsp),%rax + 408121: 48 8b 40 10 mov 0x10(%rax),%rax + 408125: 48 85 c0 test %rax,%rax + 408128: 74 25 je 40814f + 40812a: 8b 10 mov (%rax),%edx + 40812c: 83 fa 02 cmp $0x2,%edx + 40812f: 0f 84 43 07 00 00 je 408878 + 408135: 83 fa 03 cmp $0x3,%edx + 408138: 0f 84 27 07 00 00 je 408865 + 40813e: 83 fa 01 cmp $0x1,%edx + 408141: 0f 84 44 07 00 00 je 40888b + 408147: 48 89 c7 mov %rax,%rdi + 40814a: e8 61 5c 01 00 callq 41ddb0 <__cfree> + 40814f: 48 8b 04 24 mov (%rsp),%rax + 408153: 48 8b 40 08 mov 0x8(%rax),%rax + 408157: 48 85 c0 test %rax,%rax + 40815a: 0f 84 50 f3 ff ff je 4074b0 + 408160: 8b 10 mov (%rax),%edx + 408162: 83 fa 02 cmp $0x2,%edx + 408165: 0f 84 45 0c 00 00 je 408db0 + 40816b: 83 fa 03 cmp $0x3,%edx + 40816e: 0f 84 29 0c 00 00 je 408d9d + 408174: 83 fa 01 cmp $0x1,%edx + 408177: 0f 84 46 0c 00 00 je 408dc3 + 40817d: 48 89 c7 mov %rax,%rdi + 408180: e8 2b 5c 01 00 callq 41ddb0 <__cfree> + 408185: e9 26 f3 ff ff jmpq 4074b0 + 40818a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 408190: 48 8b 04 24 mov (%rsp),%rax + 408194: 48 8b 78 18 mov 0x18(%rax),%rdi + 408198: e8 73 da ff ff callq 405c10 <__gettext_free_exp> + 40819d: 48 8b 04 24 mov (%rsp),%rax + 4081a1: 48 8b 40 10 mov 0x10(%rax),%rax + 4081a5: 48 85 c0 test %rax,%rax + 4081a8: 74 25 je 4081cf + 4081aa: 8b 10 mov (%rax),%edx + 4081ac: 83 fa 02 cmp $0x2,%edx + 4081af: 0f 84 7d 07 00 00 je 408932 + 4081b5: 83 fa 03 cmp $0x3,%edx + 4081b8: 0f 84 61 07 00 00 je 40891f + 4081be: 83 fa 01 cmp $0x1,%edx + 4081c1: 0f 84 7e 07 00 00 je 408945 + 4081c7: 48 89 c7 mov %rax,%rdi + 4081ca: e8 e1 5b 01 00 callq 41ddb0 <__cfree> + 4081cf: 48 8b 04 24 mov (%rsp),%rax + 4081d3: 48 8b 40 08 mov 0x8(%rax),%rax + 4081d7: 48 85 c0 test %rax,%rax + 4081da: 0f 84 e8 f5 ff ff je 4077c8 + 4081e0: 8b 10 mov (%rax),%edx + 4081e2: 83 fa 02 cmp $0x2,%edx + 4081e5: 0f 84 87 0b 00 00 je 408d72 + 4081eb: 83 fa 03 cmp $0x3,%edx + 4081ee: 0f 84 6b 0b 00 00 je 408d5f + 4081f4: 83 fa 01 cmp $0x1,%edx + 4081f7: 0f 84 88 0b 00 00 je 408d85 + 4081fd: 48 89 c7 mov %rax,%rdi + 408200: e8 ab 5b 01 00 callq 41ddb0 <__cfree> + 408205: e9 be f5 ff ff jmpq 4077c8 + 40820a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 408210: 48 8b 04 24 mov (%rsp),%rax + 408214: 48 8b 78 18 mov 0x18(%rax),%rdi + 408218: e8 f3 d9 ff ff callq 405c10 <__gettext_free_exp> + 40821d: 48 8b 04 24 mov (%rsp),%rax + 408221: 48 8b 40 10 mov 0x10(%rax),%rax + 408225: 48 85 c0 test %rax,%rax + 408228: 74 25 je 40824f + 40822a: 8b 10 mov (%rax),%edx + 40822c: 83 fa 02 cmp $0x2,%edx + 40822f: 0f 84 81 06 00 00 je 4088b6 + 408235: 83 fa 03 cmp $0x3,%edx + 408238: 0f 84 65 06 00 00 je 4088a3 + 40823e: 83 fa 01 cmp $0x1,%edx + 408241: 0f 84 82 06 00 00 je 4088c9 + 408247: 48 89 c7 mov %rax,%rdi + 40824a: e8 61 5b 01 00 callq 41ddb0 <__cfree> + 40824f: 48 8b 04 24 mov (%rsp),%rax + 408253: 48 8b 40 08 mov 0x8(%rax),%rax + 408257: 48 85 c0 test %rax,%rax + 40825a: 0f 84 48 f4 ff ff je 4076a8 + 408260: 8b 10 mov (%rax),%edx + 408262: 83 fa 02 cmp $0x2,%edx + 408265: 0f 84 83 0b 00 00 je 408dee + 40826b: 83 fa 03 cmp $0x3,%edx + 40826e: 0f 84 67 0b 00 00 je 408ddb + 408274: 83 fa 01 cmp $0x1,%edx + 408277: 0f 84 84 0b 00 00 je 408e01 + 40827d: 48 89 c7 mov %rax,%rdi + 408280: e8 2b 5b 01 00 callq 41ddb0 <__cfree> + 408285: e9 1e f4 ff ff jmpq 4076a8 + 40828a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 408290: 49 8b 7d 18 mov 0x18(%r13),%rdi + 408294: e8 77 d9 ff ff callq 405c10 <__gettext_free_exp> + 408299: 4d 8b 7d 10 mov 0x10(%r13),%r15 + 40829d: 4d 85 ff test %r15,%r15 + 4082a0: 74 26 je 4082c8 + 4082a2: 41 8b 07 mov (%r15),%eax + 4082a5: 83 f8 02 cmp $0x2,%eax + 4082a8: 0f 84 1e 07 00 00 je 4089cc + 4082ae: 83 f8 03 cmp $0x3,%eax + 4082b1: 0f 84 0c 07 00 00 je 4089c3 + 4082b7: 83 f8 01 cmp $0x1,%eax + 4082ba: 0f 84 15 07 00 00 je 4089d5 + 4082c0: 4c 89 ff mov %r15,%rdi + 4082c3: e8 e8 5a 01 00 callq 41ddb0 <__cfree> + 4082c8: 4d 8b 7d 08 mov 0x8(%r13),%r15 + 4082cc: 4d 85 ff test %r15,%r15 + 4082cf: 0f 84 e4 ec ff ff je 406fb9 + 4082d5: 41 8b 07 mov (%r15),%eax + 4082d8: 83 f8 02 cmp $0x2,%eax + 4082db: 0f 84 07 0d 00 00 je 408fe8 + 4082e1: 83 f8 03 cmp $0x3,%eax + 4082e4: 0f 84 f5 0c 00 00 je 408fdf + 4082ea: 83 f8 01 cmp $0x1,%eax + 4082ed: 0f 84 fe 0c 00 00 je 408ff1 + 4082f3: 4c 89 ff mov %r15,%rdi + 4082f6: e8 b5 5a 01 00 callq 41ddb0 <__cfree> + 4082fb: e9 b9 ec ff ff jmpq 406fb9 + 408300: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 408304: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408309: 48 89 14 24 mov %rdx,(%rsp) + 40830d: e8 fe d8 ff ff callq 405c10 <__gettext_free_exp> + 408312: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408317: 48 8b 14 24 mov (%rsp),%rdx + 40831b: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 40831f: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408324: 48 89 14 24 mov %rdx,(%rsp) + 408328: e8 e3 d8 ff ff callq 405c10 <__gettext_free_exp> + 40832d: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408332: 48 8b 14 24 mov (%rsp),%rdx + 408336: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 40833a: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40833f: 48 89 14 24 mov %rdx,(%rsp) + 408343: e8 c8 d8 ff ff callq 405c10 <__gettext_free_exp> + 408348: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40834d: 48 8b 14 24 mov (%rsp),%rdx + 408351: e9 b0 f0 ff ff jmpq 407406 + 408356: 48 8b 78 18 mov 0x18(%rax),%rdi + 40835a: 48 89 04 24 mov %rax,(%rsp) + 40835e: e8 ad d8 ff ff callq 405c10 <__gettext_free_exp> + 408363: 48 8b 04 24 mov (%rsp),%rax + 408367: 48 8b 78 10 mov 0x10(%rax),%rdi + 40836b: 48 89 04 24 mov %rax,(%rsp) + 40836f: e8 9c d8 ff ff callq 405c10 <__gettext_free_exp> + 408374: 48 8b 04 24 mov (%rsp),%rax + 408378: 48 8b 50 08 mov 0x8(%rax),%rdx + 40837c: 48 85 d2 test %rdx,%rdx + 40837f: 0f 84 11 f2 ff ff je 407596 + 408385: 8b 0a mov (%rdx),%ecx + 408387: 83 f9 02 cmp $0x2,%ecx + 40838a: 0f 84 c3 10 00 00 je 409453 + 408390: 83 f9 03 cmp $0x3,%ecx + 408393: 0f 84 9f 10 00 00 je 409438 + 408399: 83 f9 01 cmp $0x1,%ecx + 40839c: 0f 84 cc 10 00 00 je 40946e + 4083a2: 48 89 d7 mov %rdx,%rdi + 4083a5: 48 89 04 24 mov %rax,(%rsp) + 4083a9: e8 02 5a 01 00 callq 41ddb0 <__cfree> + 4083ae: 48 8b 04 24 mov (%rsp),%rax + 4083b2: e9 df f1 ff ff jmpq 407596 + 4083b7: 48 8b 78 18 mov 0x18(%rax),%rdi + 4083bb: 48 89 04 24 mov %rax,(%rsp) + 4083bf: e8 4c d8 ff ff callq 405c10 <__gettext_free_exp> + 4083c4: 48 8b 04 24 mov (%rsp),%rax + 4083c8: 48 8b 78 10 mov 0x10(%rax),%rdi + 4083cc: 48 89 04 24 mov %rax,(%rsp) + 4083d0: e8 3b d8 ff ff callq 405c10 <__gettext_free_exp> + 4083d5: 48 8b 04 24 mov (%rsp),%rax + 4083d9: 48 8b 50 08 mov 0x8(%rax),%rdx + 4083dd: 48 85 d2 test %rdx,%rdx + 4083e0: 0f 84 d9 e9 ff ff je 406dbf + 4083e6: 8b 0a mov (%rdx),%ecx + 4083e8: 83 f9 02 cmp $0x2,%ecx + 4083eb: 0f 84 4c 11 00 00 je 40953d + 4083f1: 83 f9 03 cmp $0x3,%ecx + 4083f4: 0f 84 28 11 00 00 je 409522 + 4083fa: 83 f9 01 cmp $0x1,%ecx + 4083fd: 0f 84 55 11 00 00 je 409558 + 408403: 48 89 d7 mov %rdx,%rdi + 408406: 48 89 04 24 mov %rax,(%rsp) + 40840a: e8 a1 59 01 00 callq 41ddb0 <__cfree> + 40840f: 48 8b 04 24 mov (%rsp),%rax + 408413: e9 a7 e9 ff ff jmpq 406dbf + 408418: 48 8b 78 18 mov 0x18(%rax),%rdi + 40841c: 48 89 04 24 mov %rax,(%rsp) + 408420: e8 eb d7 ff ff callq 405c10 <__gettext_free_exp> + 408425: 48 8b 04 24 mov (%rsp),%rax + 408429: 48 8b 78 10 mov 0x10(%rax),%rdi + 40842d: 48 89 04 24 mov %rax,(%rsp) + 408431: e8 da d7 ff ff callq 405c10 <__gettext_free_exp> + 408436: 48 8b 04 24 mov (%rsp),%rax + 40843a: 48 8b 50 08 mov 0x8(%rax),%rdx + 40843e: 48 85 d2 test %rdx,%rdx + 408441: 0f 84 6f f4 ff ff je 4078b6 + 408447: 8b 0a mov (%rdx),%ecx + 408449: 83 f9 02 cmp $0x2,%ecx + 40844c: 0f 84 95 10 00 00 je 4094e7 + 408452: 83 f9 03 cmp $0x3,%ecx + 408455: 0f 84 71 10 00 00 je 4094cc + 40845b: 83 f9 01 cmp $0x1,%ecx + 40845e: 0f 84 9e 10 00 00 je 409502 + 408464: 48 89 d7 mov %rdx,%rdi + 408467: 48 89 04 24 mov %rax,(%rsp) + 40846b: e8 40 59 01 00 callq 41ddb0 <__cfree> + 408470: 48 8b 04 24 mov (%rsp),%rax + 408474: e9 3d f4 ff ff jmpq 4078b6 + 408479: 48 8b 78 18 mov 0x18(%rax),%rdi + 40847d: 48 89 04 24 mov %rax,(%rsp) + 408481: e8 8a d7 ff ff callq 405c10 <__gettext_free_exp> + 408486: 48 8b 04 24 mov (%rsp),%rax + 40848a: 48 8b 78 10 mov 0x10(%rax),%rdi + 40848e: 48 89 04 24 mov %rax,(%rsp) + 408492: e8 79 d7 ff ff callq 405c10 <__gettext_free_exp> + 408497: 48 8b 04 24 mov (%rsp),%rax + 40849b: 48 8b 50 08 mov 0x8(%rax),%rdx + 40849f: 48 85 d2 test %rdx,%rdx + 4084a2: 0f 84 57 ea ff ff je 406eff + 4084a8: 8b 0a mov (%rdx),%ecx + 4084aa: 83 f9 02 cmp $0x2,%ecx + 4084ad: 0f 84 bc 0c 00 00 je 40916f + 4084b3: 83 f9 03 cmp $0x3,%ecx + 4084b6: 0f 84 98 0c 00 00 je 409154 + 4084bc: 83 f9 01 cmp $0x1,%ecx + 4084bf: 0f 84 c5 0c 00 00 je 40918a + 4084c5: 48 89 d7 mov %rdx,%rdi + 4084c8: 48 89 04 24 mov %rax,(%rsp) + 4084cc: e8 df 58 01 00 callq 41ddb0 <__cfree> + 4084d1: 48 8b 04 24 mov (%rsp),%rax + 4084d5: e9 25 ea ff ff jmpq 406eff + 4084da: 48 8b 78 18 mov 0x18(%rax),%rdi + 4084de: 48 89 04 24 mov %rax,(%rsp) + 4084e2: e8 29 d7 ff ff callq 405c10 <__gettext_free_exp> + 4084e7: 48 8b 04 24 mov (%rsp),%rax + 4084eb: 48 8b 78 10 mov 0x10(%rax),%rdi + 4084ef: 48 89 04 24 mov %rax,(%rsp) + 4084f3: e8 18 d7 ff ff callq 405c10 <__gettext_free_exp> + 4084f8: 48 8b 04 24 mov (%rsp),%rax + 4084fc: 48 8b 50 08 mov 0x8(%rax),%rdx + 408500: 48 85 d2 test %rdx,%rdx + 408503: 0f 84 fd f0 ff ff je 407606 + 408509: 8b 0a mov (%rdx),%ecx + 40850b: 83 f9 02 cmp $0x2,%ecx + 40850e: 0f 84 e9 0e 00 00 je 4093fd + 408514: 83 f9 03 cmp $0x3,%ecx + 408517: 0f 84 c5 0e 00 00 je 4093e2 + 40851d: 83 f9 01 cmp $0x1,%ecx + 408520: 0f 84 f2 0e 00 00 je 409418 + 408526: 48 89 d7 mov %rdx,%rdi + 408529: 48 89 04 24 mov %rax,(%rsp) + 40852d: e8 7e 58 01 00 callq 41ddb0 <__cfree> + 408532: 48 8b 04 24 mov (%rsp),%rax + 408536: e9 cb f0 ff ff jmpq 407606 + 40853b: 48 8b 04 24 mov (%rsp),%rax + 40853f: 48 8b 78 18 mov 0x18(%rax),%rdi + 408543: e8 c8 d6 ff ff callq 405c10 <__gettext_free_exp> + 408548: 48 8b 04 24 mov (%rsp),%rax + 40854c: 48 8b 40 10 mov 0x10(%rax),%rax + 408550: 48 85 c0 test %rax,%rax + 408553: 74 25 je 40857a + 408555: 8b 10 mov (%rax),%edx + 408557: 83 fa 02 cmp $0x2,%edx + 40855a: 0f 84 96 04 00 00 je 4089f6 + 408560: 83 fa 03 cmp $0x3,%edx + 408563: 0f 84 7a 04 00 00 je 4089e3 + 408569: 83 fa 01 cmp $0x1,%edx + 40856c: 0f 84 97 04 00 00 je 408a09 + 408572: 48 89 c7 mov %rax,%rdi + 408575: e8 36 58 01 00 callq 41ddb0 <__cfree> + 40857a: 48 8b 04 24 mov (%rsp),%rax + 40857e: 48 8b 40 08 mov 0x8(%rax),%rax + 408582: 48 85 c0 test %rax,%rax + 408585: 0f 84 32 df ff ff je 4064bd + 40858b: 8b 10 mov (%rax),%edx + 40858d: 83 fa 02 cmp $0x2,%edx + 408590: 0f 84 21 0e 00 00 je 4093b7 + 408596: 83 fa 03 cmp $0x3,%edx + 408599: 0f 84 05 0e 00 00 je 4093a4 + 40859f: 83 fa 01 cmp $0x1,%edx + 4085a2: 0f 84 22 0e 00 00 je 4093ca + 4085a8: 48 89 c7 mov %rax,%rdi + 4085ab: e8 00 58 01 00 callq 41ddb0 <__cfree> + 4085b0: e9 08 df ff ff jmpq 4064bd + 4085b5: 49 8b 7f 18 mov 0x18(%r15),%rdi + 4085b9: e8 52 d6 ff ff callq 405c10 <__gettext_free_exp> + 4085be: 49 8b 7f 10 mov 0x10(%r15),%rdi + 4085c2: e8 49 d6 ff ff callq 405c10 <__gettext_free_exp> + 4085c7: 49 8b 47 08 mov 0x8(%r15),%rax + 4085cb: 48 85 c0 test %rax,%rax + 4085ce: 0f 84 ec e2 ff ff je 4068c0 + 4085d4: 8b 10 mov (%rax),%edx + 4085d6: 83 fa 02 cmp $0x2,%edx + 4085d9: 0f 84 35 13 00 00 je 409914 + 4085df: 83 fa 03 cmp $0x3,%edx + 4085e2: 0f 84 1b 13 00 00 je 409903 + 4085e8: 83 fa 01 cmp $0x1,%edx + 4085eb: 0f 84 34 13 00 00 je 409925 + 4085f1: 48 89 c7 mov %rax,%rdi + 4085f4: e8 b7 57 01 00 callq 41ddb0 <__cfree> + 4085f9: e9 c2 e2 ff ff jmpq 4068c0 + 4085fe: 49 8b 7f 18 mov 0x18(%r15),%rdi + 408602: e8 09 d6 ff ff callq 405c10 <__gettext_free_exp> + 408607: 49 8b 7f 10 mov 0x10(%r15),%rdi + 40860b: e8 00 d6 ff ff callq 405c10 <__gettext_free_exp> + 408610: 49 8b 47 08 mov 0x8(%r15),%rax + 408614: 48 85 c0 test %rax,%rax + 408617: 0f 84 95 df ff ff je 4065b2 + 40861d: 8b 10 mov (%rax),%edx + 40861f: 83 fa 02 cmp $0x2,%edx + 408622: 0f 84 5c 13 00 00 je 409984 + 408628: 83 fa 03 cmp $0x3,%edx + 40862b: 0f 84 42 13 00 00 je 409973 + 408631: 83 fa 01 cmp $0x1,%edx + 408634: 0f 84 5b 13 00 00 je 409995 + 40863a: 48 89 c7 mov %rax,%rdi + 40863d: e8 6e 57 01 00 callq 41ddb0 <__cfree> + 408642: e9 6b df ff ff jmpq 4065b2 + 408647: 49 8b 7f 18 mov 0x18(%r15),%rdi + 40864b: e8 c0 d5 ff ff callq 405c10 <__gettext_free_exp> + 408650: 49 8b 7f 10 mov 0x10(%r15),%rdi + 408654: e8 b7 d5 ff ff callq 405c10 <__gettext_free_exp> + 408659: 49 8b 47 08 mov 0x8(%r15),%rax + 40865d: 48 85 c0 test %rax,%rax + 408660: 0f 84 c1 f2 ff ff je 407927 + 408666: 8b 10 mov (%rax),%edx + 408668: 83 fa 02 cmp $0x2,%edx + 40866b: 0f 84 ab 10 00 00 je 40971c + 408671: 83 fa 03 cmp $0x3,%edx + 408674: 0f 84 91 10 00 00 je 40970b + 40867a: 83 fa 01 cmp $0x1,%edx + 40867d: 0f 84 aa 10 00 00 je 40972d + 408683: 48 89 c7 mov %rax,%rdi + 408686: e8 25 57 01 00 callq 41ddb0 <__cfree> + 40868b: e9 97 f2 ff ff jmpq 407927 + 408690: 48 8b 78 18 mov 0x18(%rax),%rdi + 408694: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408699: e8 72 d5 ff ff callq 405c10 <__gettext_free_exp> + 40869e: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4086a3: 48 8b 78 10 mov 0x10(%rax),%rdi + 4086a7: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4086ac: e8 5f d5 ff ff callq 405c10 <__gettext_free_exp> + 4086b1: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4086b6: 48 8b 78 08 mov 0x8(%rax),%rdi + 4086ba: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4086bf: e8 4c d5 ff ff callq 405c10 <__gettext_free_exp> + 4086c4: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4086c9: e9 13 e4 ff ff jmpq 406ae1 + 4086ce: 48 8b 78 18 mov 0x18(%rax),%rdi + 4086d2: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4086d7: e8 34 d5 ff ff callq 405c10 <__gettext_free_exp> + 4086dc: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4086e1: 48 8b 78 10 mov 0x10(%rax),%rdi + 4086e5: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4086ea: e8 21 d5 ff ff callq 405c10 <__gettext_free_exp> + 4086ef: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4086f4: 48 8b 78 08 mov 0x8(%rax),%rdi + 4086f8: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4086fd: e8 0e d5 ff ff callq 405c10 <__gettext_free_exp> + 408702: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408707: e9 eb e2 ff ff jmpq 4069f7 + 40870c: 48 8b 78 18 mov 0x18(%rax),%rdi + 408710: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408715: e8 f6 d4 ff ff callq 405c10 <__gettext_free_exp> + 40871a: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40871f: 48 8b 78 10 mov 0x10(%rax),%rdi + 408723: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408728: e8 e3 d4 ff ff callq 405c10 <__gettext_free_exp> + 40872d: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408732: 48 8b 78 08 mov 0x8(%rax),%rdi + 408736: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40873b: e8 d0 d4 ff ff callq 405c10 <__gettext_free_exp> + 408740: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408745: e9 f5 f0 ff ff jmpq 40783f + 40874a: 48 8b 78 18 mov 0x18(%rax),%rdi + 40874e: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408753: e8 b8 d4 ff ff callq 405c10 <__gettext_free_exp> + 408758: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40875d: 48 8b 78 10 mov 0x10(%rax),%rdi + 408761: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408766: e8 a5 d4 ff ff callq 405c10 <__gettext_free_exp> + 40876b: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408770: 48 8b 78 08 mov 0x8(%rax),%rdi + 408774: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408779: e8 92 d4 ff ff callq 405c10 <__gettext_free_exp> + 40877e: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408783: e9 9f ed ff ff jmpq 407527 + 408788: 48 8b 78 18 mov 0x18(%rax),%rdi + 40878c: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408791: e8 7a d4 ff ff callq 405c10 <__gettext_free_exp> + 408796: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40879b: 48 8b 78 10 mov 0x10(%rax),%rdi + 40879f: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4087a4: e8 67 d4 ff ff callq 405c10 <__gettext_free_exp> + 4087a9: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4087ae: 48 8b 78 08 mov 0x8(%rax),%rdi + 4087b2: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4087b7: e8 54 d4 ff ff callq 405c10 <__gettext_free_exp> + 4087bc: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4087c1: e9 d1 e3 ff ff jmpq 406b97 + 4087c6: 48 8b 78 18 mov 0x18(%rax),%rdi + 4087ca: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4087cf: e8 3c d4 ff ff callq 405c10 <__gettext_free_exp> + 4087d4: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4087d9: 48 8b 78 10 mov 0x10(%rax),%rdi + 4087dd: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4087e2: e8 29 d4 ff ff callq 405c10 <__gettext_free_exp> + 4087e7: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4087ec: 48 8b 78 08 mov 0x8(%rax),%rdi + 4087f0: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4087f5: e8 16 d4 ff ff callq 405c10 <__gettext_free_exp> + 4087fa: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4087ff: e9 1b ef ff ff jmpq 40771f + 408804: 48 8b 78 18 mov 0x18(%rax),%rdi + 408808: 48 89 04 24 mov %rax,(%rsp) + 40880c: e8 ff d3 ff ff callq 405c10 <__gettext_free_exp> + 408811: 48 8b 04 24 mov (%rsp),%rax + 408815: 48 8b 78 10 mov 0x10(%rax),%rdi + 408819: 48 89 04 24 mov %rax,(%rsp) + 40881d: e8 ee d3 ff ff callq 405c10 <__gettext_free_exp> + 408822: 48 8b 04 24 mov (%rsp),%rax + 408826: 48 8b 50 08 mov 0x8(%rax),%rdx + 40882a: 48 85 d2 test %rdx,%rdx + 40882d: 0f 84 1c e4 ff ff je 406c4f + 408833: 8b 0a mov (%rdx),%ecx + 408835: 83 f9 02 cmp $0x2,%ecx + 408838: 0f 84 3a 01 00 00 je 408978 + 40883e: 83 f9 03 cmp $0x3,%ecx + 408841: 0f 84 16 01 00 00 je 40895d + 408847: 83 f9 01 cmp $0x1,%ecx + 40884a: 0f 84 43 01 00 00 je 408993 + 408850: 48 89 d7 mov %rdx,%rdi + 408853: 48 89 04 24 mov %rax,(%rsp) + 408857: e8 54 55 01 00 callq 41ddb0 <__cfree> + 40885c: 48 8b 04 24 mov (%rsp),%rax + 408860: e9 ea e3 ff ff jmpq 406c4f + 408865: 48 8b 78 18 mov 0x18(%rax),%rdi + 408869: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40886e: e8 9d d3 ff ff callq 405c10 <__gettext_free_exp> + 408873: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408878: 48 8b 78 10 mov 0x10(%rax),%rdi + 40887c: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408881: e8 8a d3 ff ff callq 405c10 <__gettext_free_exp> + 408886: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40888b: 48 8b 78 08 mov 0x8(%rax),%rdi + 40888f: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408894: e8 77 d3 ff ff callq 405c10 <__gettext_free_exp> + 408899: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40889e: e9 a4 f8 ff ff jmpq 408147 + 4088a3: 48 8b 78 18 mov 0x18(%rax),%rdi + 4088a7: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4088ac: e8 5f d3 ff ff callq 405c10 <__gettext_free_exp> + 4088b1: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4088b6: 48 8b 78 10 mov 0x10(%rax),%rdi + 4088ba: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4088bf: e8 4c d3 ff ff callq 405c10 <__gettext_free_exp> + 4088c4: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4088c9: 48 8b 78 08 mov 0x8(%rax),%rdi + 4088cd: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4088d2: e8 39 d3 ff ff callq 405c10 <__gettext_free_exp> + 4088d7: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4088dc: e9 66 f9 ff ff jmpq 408247 + 4088e1: 48 8b 78 18 mov 0x18(%rax),%rdi + 4088e5: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4088ea: e8 21 d3 ff ff callq 405c10 <__gettext_free_exp> + 4088ef: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4088f4: 48 8b 78 10 mov 0x10(%rax),%rdi + 4088f8: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4088fd: e8 0e d3 ff ff callq 405c10 <__gettext_free_exp> + 408902: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408907: 48 8b 78 08 mov 0x8(%rax),%rdi + 40890b: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408910: e8 fb d2 ff ff callq 405c10 <__gettext_free_exp> + 408915: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40891a: e9 a8 f7 ff ff jmpq 4080c7 + 40891f: 48 8b 78 18 mov 0x18(%rax),%rdi + 408923: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408928: e8 e3 d2 ff ff callq 405c10 <__gettext_free_exp> + 40892d: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408932: 48 8b 78 10 mov 0x10(%rax),%rdi + 408936: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40893b: e8 d0 d2 ff ff callq 405c10 <__gettext_free_exp> + 408940: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408945: 48 8b 78 08 mov 0x8(%rax),%rdi + 408949: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40894e: e8 bd d2 ff ff callq 405c10 <__gettext_free_exp> + 408953: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408958: e9 6a f8 ff ff jmpq 4081c7 + 40895d: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 408961: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408966: 48 89 14 24 mov %rdx,(%rsp) + 40896a: e8 a1 d2 ff ff callq 405c10 <__gettext_free_exp> + 40896f: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408974: 48 8b 14 24 mov (%rsp),%rdx + 408978: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 40897c: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408981: 48 89 14 24 mov %rdx,(%rsp) + 408985: e8 86 d2 ff ff callq 405c10 <__gettext_free_exp> + 40898a: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40898f: 48 8b 14 24 mov (%rsp),%rdx + 408993: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 408997: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40899c: 48 89 14 24 mov %rdx,(%rsp) + 4089a0: e8 6b d2 ff ff callq 405c10 <__gettext_free_exp> + 4089a5: 48 8b 14 24 mov (%rsp),%rdx + 4089a9: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4089ae: 48 89 d7 mov %rdx,%rdi + 4089b1: 48 89 04 24 mov %rax,(%rsp) + 4089b5: e8 f6 53 01 00 callq 41ddb0 <__cfree> + 4089ba: 48 8b 04 24 mov (%rsp),%rax + 4089be: e9 8c e2 ff ff jmpq 406c4f + 4089c3: 49 8b 7f 18 mov 0x18(%r15),%rdi + 4089c7: e8 44 d2 ff ff callq 405c10 <__gettext_free_exp> + 4089cc: 49 8b 7f 10 mov 0x10(%r15),%rdi + 4089d0: e8 3b d2 ff ff callq 405c10 <__gettext_free_exp> + 4089d5: 49 8b 7f 08 mov 0x8(%r15),%rdi + 4089d9: e8 32 d2 ff ff callq 405c10 <__gettext_free_exp> + 4089de: e9 dd f8 ff ff jmpq 4082c0 + 4089e3: 48 8b 78 18 mov 0x18(%rax),%rdi + 4089e7: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4089ec: e8 1f d2 ff ff callq 405c10 <__gettext_free_exp> + 4089f1: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4089f6: 48 8b 78 10 mov 0x10(%rax),%rdi + 4089fa: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4089ff: e8 0c d2 ff ff callq 405c10 <__gettext_free_exp> + 408a04: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408a09: 48 8b 78 08 mov 0x8(%rax),%rdi + 408a0d: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408a12: e8 f9 d1 ff ff callq 405c10 <__gettext_free_exp> + 408a17: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408a1c: e9 51 fb ff ff jmpq 408572 + 408a21: 48 8b 78 18 mov 0x18(%rax),%rdi + 408a25: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408a2a: e8 e1 d1 ff ff callq 405c10 <__gettext_free_exp> + 408a2f: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408a34: 48 8b 78 10 mov 0x10(%rax),%rdi + 408a38: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408a3d: e8 ce d1 ff ff callq 405c10 <__gettext_free_exp> + 408a42: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408a47: 48 8b 78 08 mov 0x8(%rax),%rdi + 408a4b: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408a50: e8 bb d1 ff ff callq 405c10 <__gettext_free_exp> + 408a55: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408a5a: e9 7e ef ff ff jmpq 4079dd + 408a5f: 48 8b 78 18 mov 0x18(%rax),%rdi + 408a63: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408a68: e8 a3 d1 ff ff callq 405c10 <__gettext_free_exp> + 408a6d: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408a72: 48 8b 78 10 mov 0x10(%rax),%rdi + 408a76: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408a7b: e8 90 d1 ff ff callq 405c10 <__gettext_free_exp> + 408a80: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408a85: 48 8b 78 08 mov 0x8(%rax),%rdi + 408a89: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408a8e: e8 7d d1 ff ff callq 405c10 <__gettext_free_exp> + 408a93: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408a98: e9 c0 f0 ff ff jmpq 407b5d + 408a9d: 48 8b 78 18 mov 0x18(%rax),%rdi + 408aa1: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408aa6: e8 65 d1 ff ff callq 405c10 <__gettext_free_exp> + 408aab: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408ab0: 48 8b 78 10 mov 0x10(%rax),%rdi + 408ab4: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408ab9: e8 52 d1 ff ff callq 405c10 <__gettext_free_exp> + 408abe: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408ac3: 48 8b 78 08 mov 0x8(%rax),%rdi + 408ac7: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408acc: e8 3f d1 ff ff callq 405c10 <__gettext_free_exp> + 408ad1: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408ad6: e9 02 f0 ff ff jmpq 407add + 408adb: 48 8b 78 18 mov 0x18(%rax),%rdi + 408adf: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408ae4: e8 27 d1 ff ff callq 405c10 <__gettext_free_exp> + 408ae9: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408aee: 48 8b 78 10 mov 0x10(%rax),%rdi + 408af2: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408af7: e8 14 d1 ff ff callq 405c10 <__gettext_free_exp> + 408afc: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408b01: 48 8b 78 08 mov 0x8(%rax),%rdi + 408b05: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408b0a: e8 01 d1 ff ff callq 405c10 <__gettext_free_exp> + 408b0f: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408b14: e9 44 ef ff ff jmpq 407a5d + 408b19: 48 8b 78 18 mov 0x18(%rax),%rdi + 408b1d: 48 89 04 24 mov %rax,(%rsp) + 408b21: e8 ea d0 ff ff callq 405c10 <__gettext_free_exp> + 408b26: 48 8b 04 24 mov (%rsp),%rax + 408b2a: 48 8b 78 10 mov 0x10(%rax),%rdi + 408b2e: 48 89 04 24 mov %rax,(%rsp) + 408b32: e8 d9 d0 ff ff callq 405c10 <__gettext_free_exp> + 408b37: 48 8b 04 24 mov (%rsp),%rax + 408b3b: 48 8b 50 08 mov 0x8(%rax),%rdx + 408b3f: 48 85 d2 test %rdx,%rdx + 408b42: 0f 84 d9 f1 ff ff je 407d21 + 408b48: 8b 0a mov (%rdx),%ecx + 408b4a: 83 f9 02 cmp $0x2,%ecx + 408b4d: 0f 84 40 0a 00 00 je 409593 + 408b53: 83 f9 03 cmp $0x3,%ecx + 408b56: 0f 84 1c 0a 00 00 je 409578 + 408b5c: 83 f9 01 cmp $0x1,%ecx + 408b5f: 0f 84 49 0a 00 00 je 4095ae + 408b65: 48 89 d7 mov %rdx,%rdi + 408b68: 48 89 04 24 mov %rax,(%rsp) + 408b6c: e8 3f 52 01 00 callq 41ddb0 <__cfree> + 408b71: 48 8b 04 24 mov (%rsp),%rax + 408b75: e9 a7 f1 ff ff jmpq 407d21 + 408b7a: 48 8b 78 18 mov 0x18(%rax),%rdi + 408b7e: 48 89 04 24 mov %rax,(%rsp) + 408b82: e8 89 d0 ff ff callq 405c10 <__gettext_free_exp> + 408b87: 48 8b 04 24 mov (%rsp),%rax + 408b8b: 48 8b 78 10 mov 0x10(%rax),%rdi + 408b8f: 48 89 04 24 mov %rax,(%rsp) + 408b93: e8 78 d0 ff ff callq 405c10 <__gettext_free_exp> + 408b98: 48 8b 04 24 mov (%rsp),%rax + 408b9c: 48 8b 50 08 mov 0x8(%rax),%rdx + 408ba0: 48 85 d2 test %rdx,%rdx + 408ba3: 0f 84 98 f0 ff ff je 407c41 + 408ba9: 8b 0a mov (%rdx),%ecx + 408bab: 83 f9 02 cmp $0x2,%ecx + 408bae: 0f 84 b1 0a 00 00 je 409665 + 408bb4: 83 f9 03 cmp $0x3,%ecx + 408bb7: 0f 84 8d 0a 00 00 je 40964a + 408bbd: 83 f9 01 cmp $0x1,%ecx + 408bc0: 0f 84 ba 0a 00 00 je 409680 + 408bc6: 48 89 d7 mov %rdx,%rdi + 408bc9: 48 89 04 24 mov %rax,(%rsp) + 408bcd: e8 de 51 01 00 callq 41ddb0 <__cfree> + 408bd2: 48 8b 04 24 mov (%rsp),%rax + 408bd6: e9 66 f0 ff ff jmpq 407c41 + 408bdb: 48 8b 78 18 mov 0x18(%rax),%rdi + 408bdf: 48 89 04 24 mov %rax,(%rsp) + 408be3: e8 28 d0 ff ff callq 405c10 <__gettext_free_exp> + 408be8: 48 8b 04 24 mov (%rsp),%rax + 408bec: 48 8b 78 10 mov 0x10(%rax),%rdi + 408bf0: 48 89 04 24 mov %rax,(%rsp) + 408bf4: e8 17 d0 ff ff callq 405c10 <__gettext_free_exp> + 408bf9: 48 8b 04 24 mov (%rsp),%rax + 408bfd: 48 8b 50 08 mov 0x8(%rax),%rdx + 408c01: 48 85 d2 test %rdx,%rdx + 408c04: 0f 84 a7 f0 ff ff je 407cb1 + 408c0a: 8b 0a mov (%rdx),%ecx + 408c0c: 83 f9 02 cmp $0x2,%ecx + 408c0f: 0f 84 04 05 00 00 je 409119 + 408c15: 83 f9 03 cmp $0x3,%ecx + 408c18: 0f 84 e0 04 00 00 je 4090fe + 408c1e: 83 f9 01 cmp $0x1,%ecx + 408c21: 0f 84 0d 05 00 00 je 409134 + 408c27: 48 89 d7 mov %rdx,%rdi + 408c2a: 48 89 04 24 mov %rax,(%rsp) + 408c2e: e8 7d 51 01 00 callq 41ddb0 <__cfree> + 408c33: 48 8b 04 24 mov (%rsp),%rax + 408c37: e9 75 f0 ff ff jmpq 407cb1 + 408c3c: 48 8b 78 18 mov 0x18(%rax),%rdi + 408c40: 48 89 04 24 mov %rax,(%rsp) + 408c44: e8 c7 cf ff ff callq 405c10 <__gettext_free_exp> + 408c49: 48 8b 04 24 mov (%rsp),%rax + 408c4d: 48 8b 78 10 mov 0x10(%rax),%rdi + 408c51: 48 89 04 24 mov %rax,(%rsp) + 408c55: e8 b6 cf ff ff callq 405c10 <__gettext_free_exp> + 408c5a: 48 8b 04 24 mov (%rsp),%rax + 408c5e: 48 8b 50 08 mov 0x8(%rax),%rdx + 408c62: 48 85 d2 test %rdx,%rdx + 408c65: 0f 84 26 f1 ff ff je 407d91 + 408c6b: 8b 0a mov (%rdx),%ecx + 408c6d: 83 f9 02 cmp $0x2,%ecx + 408c70: 0f 84 cb 05 00 00 je 409241 + 408c76: 83 f9 03 cmp $0x3,%ecx + 408c79: 0f 84 a7 05 00 00 je 409226 + 408c7f: 83 f9 01 cmp $0x1,%ecx + 408c82: 0f 84 d4 05 00 00 je 40925c + 408c88: 48 89 d7 mov %rdx,%rdi + 408c8b: 48 89 04 24 mov %rax,(%rsp) + 408c8f: e8 1c 51 01 00 callq 41ddb0 <__cfree> + 408c94: 48 8b 04 24 mov (%rsp),%rax + 408c98: e9 f4 f0 ff ff jmpq 407d91 + 408c9d: 48 8b 78 18 mov 0x18(%rax),%rdi + 408ca1: 48 89 04 24 mov %rax,(%rsp) + 408ca5: e8 66 cf ff ff callq 405c10 <__gettext_free_exp> + 408caa: 48 8b 04 24 mov (%rsp),%rax + 408cae: 48 8b 78 10 mov 0x10(%rax),%rdi + 408cb2: 48 89 04 24 mov %rax,(%rsp) + 408cb6: e8 55 cf ff ff callq 405c10 <__gettext_free_exp> + 408cbb: 48 8b 04 24 mov (%rsp),%rax + 408cbf: 48 8b 50 08 mov 0x8(%rax),%rdx + 408cc3: 48 85 d2 test %rdx,%rdx + 408cc6: 0f 84 35 f1 ff ff je 407e01 + 408ccc: 8b 0a mov (%rdx),%ecx + 408cce: 83 f9 02 cmp $0x2,%ecx + 408cd1: 0f 84 92 06 00 00 je 409369 + 408cd7: 83 f9 03 cmp $0x3,%ecx + 408cda: 0f 84 6e 06 00 00 je 40934e + 408ce0: 83 f9 01 cmp $0x1,%ecx + 408ce3: 0f 84 9b 06 00 00 je 409384 + 408ce9: 48 89 d7 mov %rdx,%rdi + 408cec: 48 89 04 24 mov %rax,(%rsp) + 408cf0: e8 bb 50 01 00 callq 41ddb0 <__cfree> + 408cf5: 48 8b 04 24 mov (%rsp),%rax + 408cf9: e9 03 f1 ff ff jmpq 407e01 + 408cfe: 48 8b 78 18 mov 0x18(%rax),%rdi + 408d02: 48 89 04 24 mov %rax,(%rsp) + 408d06: e8 05 cf ff ff callq 405c10 <__gettext_free_exp> + 408d0b: 48 8b 04 24 mov (%rsp),%rax + 408d0f: 48 8b 78 10 mov 0x10(%rax),%rdi + 408d13: 48 89 04 24 mov %rax,(%rsp) + 408d17: e8 f4 ce ff ff callq 405c10 <__gettext_free_exp> + 408d1c: 48 8b 04 24 mov (%rsp),%rax + 408d20: 48 8b 50 08 mov 0x8(%rax),%rdx + 408d24: 48 85 d2 test %rdx,%rdx + 408d27: 0f 84 a4 ee ff ff je 407bd1 + 408d2d: 8b 0a mov (%rdx),%ecx + 408d2f: 83 f9 02 cmp $0x2,%ecx + 408d32: 0f 84 5f 05 00 00 je 409297 + 408d38: 83 f9 03 cmp $0x3,%ecx + 408d3b: 0f 84 3b 05 00 00 je 40927c + 408d41: 83 f9 01 cmp $0x1,%ecx + 408d44: 0f 84 68 05 00 00 je 4092b2 + 408d4a: 48 89 d7 mov %rdx,%rdi + 408d4d: 48 89 04 24 mov %rax,(%rsp) + 408d51: e8 5a 50 01 00 callq 41ddb0 <__cfree> + 408d56: 48 8b 04 24 mov (%rsp),%rax + 408d5a: e9 72 ee ff ff jmpq 407bd1 + 408d5f: 48 8b 78 18 mov 0x18(%rax),%rdi + 408d63: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408d68: e8 a3 ce ff ff callq 405c10 <__gettext_free_exp> + 408d6d: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408d72: 48 8b 78 10 mov 0x10(%rax),%rdi + 408d76: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408d7b: e8 90 ce ff ff callq 405c10 <__gettext_free_exp> + 408d80: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408d85: 48 8b 78 08 mov 0x8(%rax),%rdi + 408d89: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408d8e: e8 7d ce ff ff callq 405c10 <__gettext_free_exp> + 408d93: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408d98: e9 60 f4 ff ff jmpq 4081fd + 408d9d: 48 8b 78 18 mov 0x18(%rax),%rdi + 408da1: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408da6: e8 65 ce ff ff callq 405c10 <__gettext_free_exp> + 408dab: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408db0: 48 8b 78 10 mov 0x10(%rax),%rdi + 408db4: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408db9: e8 52 ce ff ff callq 405c10 <__gettext_free_exp> + 408dbe: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408dc3: 48 8b 78 08 mov 0x8(%rax),%rdi + 408dc7: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408dcc: e8 3f ce ff ff callq 405c10 <__gettext_free_exp> + 408dd1: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408dd6: e9 a2 f3 ff ff jmpq 40817d + 408ddb: 48 8b 78 18 mov 0x18(%rax),%rdi + 408ddf: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408de4: e8 27 ce ff ff callq 405c10 <__gettext_free_exp> + 408de9: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408dee: 48 8b 78 10 mov 0x10(%rax),%rdi + 408df2: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408df7: e8 14 ce ff ff callq 405c10 <__gettext_free_exp> + 408dfc: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408e01: 48 8b 78 08 mov 0x8(%rax),%rdi + 408e05: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408e0a: e8 01 ce ff ff callq 405c10 <__gettext_free_exp> + 408e0f: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408e14: e9 64 f4 ff ff jmpq 40827d + 408e19: 48 8b 78 18 mov 0x18(%rax),%rdi + 408e1d: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408e22: e8 e9 cd ff ff callq 405c10 <__gettext_free_exp> + 408e27: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408e2c: 48 8b 78 10 mov 0x10(%rax),%rdi + 408e30: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408e35: e8 d6 cd ff ff callq 405c10 <__gettext_free_exp> + 408e3a: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408e3f: 48 8b 78 08 mov 0x8(%rax),%rdi + 408e43: 48 89 44 24 08 mov %rax,0x8(%rsp) + 408e48: e8 c3 cd ff ff callq 405c10 <__gettext_free_exp> + 408e4d: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 408e52: e9 a6 f2 ff ff jmpq 4080fd + 408e57: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 408e5e: 00 00 + 408e60: 49 8b 47 18 mov 0x18(%r15),%rax + 408e64: 48 85 c0 test %rax,%rax + 408e67: 0f 84 2c df ff ff je 406d99 + 408e6d: 8b 10 mov (%rax),%edx + 408e6f: 83 fa 02 cmp $0x2,%edx + 408e72: 0f 84 f7 de ff ff je 406d6f + 408e78: 83 fa 03 cmp $0x3,%edx + 408e7b: 0f 84 dd de ff ff je 406d5e + 408e81: 83 fa 01 cmp $0x1,%edx + 408e84: 0f 85 07 df ff ff jne 406d91 + 408e8a: e9 f1 de ff ff jmpq 406d80 + 408e8f: 49 8b 7f 18 mov 0x18(%r15),%rdi + 408e93: e8 78 cd ff ff callq 405c10 <__gettext_free_exp> + 408e98: 49 8b 7f 10 mov 0x10(%r15),%rdi + 408e9c: e8 6f cd ff ff callq 405c10 <__gettext_free_exp> + 408ea1: 49 8b 47 08 mov 0x8(%r15),%rax + 408ea5: 48 85 c0 test %rax,%rax + 408ea8: 0f 84 89 df ff ff je 406e37 + 408eae: 8b 10 mov (%rax),%edx + 408eb0: 83 fa 02 cmp $0x2,%edx + 408eb3: 74 28 je 408edd + 408eb5: 83 fa 03 cmp $0x3,%edx + 408eb8: 74 12 je 408ecc + 408eba: 83 fa 01 cmp $0x1,%edx + 408ebd: 74 2f je 408eee + 408ebf: 48 89 c7 mov %rax,%rdi + 408ec2: e8 e9 4e 01 00 callq 41ddb0 <__cfree> + 408ec7: e9 6b df ff ff jmpq 406e37 + 408ecc: 48 8b 78 18 mov 0x18(%rax),%rdi + 408ed0: 48 89 04 24 mov %rax,(%rsp) + 408ed4: e8 37 cd ff ff callq 405c10 <__gettext_free_exp> + 408ed9: 48 8b 04 24 mov (%rsp),%rax + 408edd: 48 8b 78 10 mov 0x10(%rax),%rdi + 408ee1: 48 89 04 24 mov %rax,(%rsp) + 408ee5: e8 26 cd ff ff callq 405c10 <__gettext_free_exp> + 408eea: 48 8b 04 24 mov (%rsp),%rax + 408eee: 48 8b 78 08 mov 0x8(%rax),%rdi + 408ef2: 48 89 04 24 mov %rax,(%rsp) + 408ef6: e8 15 cd ff ff callq 405c10 <__gettext_free_exp> + 408efb: 48 8b 04 24 mov (%rsp),%rax + 408eff: eb be jmp 408ebf + 408f01: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 408f08: 49 8b 47 18 mov 0x18(%r15),%rax + 408f0c: 48 85 c0 test %rax,%rax + 408f0f: 0f 84 c4 df ff ff je 406ed9 + 408f15: 8b 10 mov (%rax),%edx + 408f17: 83 fa 02 cmp $0x2,%edx + 408f1a: 0f 84 8f df ff ff je 406eaf + 408f20: 83 fa 03 cmp $0x3,%edx + 408f23: 0f 84 75 df ff ff je 406e9e + 408f29: 83 fa 01 cmp $0x1,%edx + 408f2c: 0f 85 9f df ff ff jne 406ed1 + 408f32: e9 89 df ff ff jmpq 406ec0 + 408f37: 49 8b 7f 18 mov 0x18(%r15),%rdi + 408f3b: e8 d0 cc ff ff callq 405c10 <__gettext_free_exp> + 408f40: 49 8b 7f 10 mov 0x10(%r15),%rdi + 408f44: e8 c7 cc ff ff callq 405c10 <__gettext_free_exp> + 408f49: 49 8b 47 08 mov 0x8(%r15),%rax + 408f4d: 48 85 c0 test %rax,%rax + 408f50: 0f 84 a1 dd ff ff je 406cf7 + 408f56: 8b 10 mov (%rax),%edx + 408f58: 83 fa 02 cmp $0x2,%edx + 408f5b: 74 28 je 408f85 + 408f5d: 83 fa 03 cmp $0x3,%edx + 408f60: 74 12 je 408f74 + 408f62: 83 fa 01 cmp $0x1,%edx + 408f65: 74 2f je 408f96 + 408f67: 48 89 c7 mov %rax,%rdi + 408f6a: e8 41 4e 01 00 callq 41ddb0 <__cfree> + 408f6f: e9 83 dd ff ff jmpq 406cf7 + 408f74: 48 8b 78 18 mov 0x18(%rax),%rdi + 408f78: 48 89 04 24 mov %rax,(%rsp) + 408f7c: e8 8f cc ff ff callq 405c10 <__gettext_free_exp> + 408f81: 48 8b 04 24 mov (%rsp),%rax + 408f85: 48 8b 78 10 mov 0x10(%rax),%rdi + 408f89: 48 89 04 24 mov %rax,(%rsp) + 408f8d: e8 7e cc ff ff callq 405c10 <__gettext_free_exp> + 408f92: 48 8b 04 24 mov (%rsp),%rax + 408f96: 48 8b 78 08 mov 0x8(%rax),%rdi + 408f9a: 48 89 04 24 mov %rax,(%rsp) + 408f9e: e8 6d cc ff ff callq 405c10 <__gettext_free_exp> + 408fa3: 48 8b 04 24 mov (%rsp),%rax + 408fa7: eb be jmp 408f67 + 408fa9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 408fb0: 49 8b 47 18 mov 0x18(%r15),%rax + 408fb4: 48 85 c0 test %rax,%rax + 408fb7: 0f 84 d6 d4 ff ff je 406493 + 408fbd: 8b 10 mov (%rax),%edx + 408fbf: 83 fa 02 cmp $0x2,%edx + 408fc2: 0f 84 a1 d4 ff ff je 406469 + 408fc8: 83 fa 03 cmp $0x3,%edx + 408fcb: 0f 84 87 d4 ff ff je 406458 + 408fd1: 83 fa 01 cmp $0x1,%edx + 408fd4: 0f 85 b1 d4 ff ff jne 40648b + 408fda: e9 9b d4 ff ff jmpq 40647a + 408fdf: 49 8b 7f 18 mov 0x18(%r15),%rdi + 408fe3: e8 28 cc ff ff callq 405c10 <__gettext_free_exp> + 408fe8: 49 8b 7f 10 mov 0x10(%r15),%rdi + 408fec: e8 1f cc ff ff callq 405c10 <__gettext_free_exp> + 408ff1: 49 8b 47 08 mov 0x8(%r15),%rax + 408ff5: 48 85 c0 test %rax,%rax + 408ff8: 0f 84 f5 f2 ff ff je 4082f3 + 408ffe: 8b 10 mov (%rax),%edx + 409000: 83 fa 02 cmp $0x2,%edx + 409003: 74 28 je 40902d + 409005: 83 fa 03 cmp $0x3,%edx + 409008: 74 12 je 40901c + 40900a: 83 fa 01 cmp $0x1,%edx + 40900d: 74 2f je 40903e + 40900f: 48 89 c7 mov %rax,%rdi + 409012: e8 99 4d 01 00 callq 41ddb0 <__cfree> + 409017: e9 d7 f2 ff ff jmpq 4082f3 + 40901c: 48 8b 78 18 mov 0x18(%rax),%rdi + 409020: 48 89 04 24 mov %rax,(%rsp) + 409024: e8 e7 cb ff ff callq 405c10 <__gettext_free_exp> + 409029: 48 8b 04 24 mov (%rsp),%rax + 40902d: 48 8b 78 10 mov 0x10(%rax),%rdi + 409031: 48 89 04 24 mov %rax,(%rsp) + 409035: e8 d6 cb ff ff callq 405c10 <__gettext_free_exp> + 40903a: 48 8b 04 24 mov (%rsp),%rax + 40903e: 48 8b 78 08 mov 0x8(%rax),%rdi + 409042: 48 89 04 24 mov %rax,(%rsp) + 409046: e8 c5 cb ff ff callq 405c10 <__gettext_free_exp> + 40904b: 48 8b 04 24 mov (%rsp),%rax + 40904f: eb be jmp 40900f + 409051: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 409058: 4d 8b 7d 18 mov 0x18(%r13),%r15 + 40905c: 4d 85 ff test %r15,%r15 + 40905f: 0f 84 26 d5 ff ff je 40658b + 409065: 41 8b 07 mov (%r15),%eax + 409068: 83 f8 02 cmp $0x2,%eax + 40906b: 0f 84 00 d5 ff ff je 406571 + 409071: 83 f8 03 cmp $0x3,%eax + 409074: 0f 84 ee d4 ff ff je 406568 + 40907a: 83 f8 01 cmp $0x1,%eax + 40907d: 0f 85 00 d5 ff ff jne 406583 + 409083: e9 f2 d4 ff ff jmpq 40657a + 409088: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 40908f: 00 + 409090: 4d 8b 7d 18 mov 0x18(%r13),%r15 + 409094: 4d 85 ff test %r15,%r15 + 409097: 0f 84 fc d7 ff ff je 406899 + 40909d: 41 8b 07 mov (%r15),%eax + 4090a0: 83 f8 02 cmp $0x2,%eax + 4090a3: 0f 84 d6 d7 ff ff je 40687f + 4090a9: 83 f8 03 cmp $0x3,%eax + 4090ac: 0f 84 c4 d7 ff ff je 406876 + 4090b2: 83 f8 01 cmp $0x1,%eax + 4090b5: 0f 85 d6 d7 ff ff jne 406891 + 4090bb: e9 c8 d7 ff ff jmpq 406888 + 4090c0: 48 8b 78 18 mov 0x18(%rax),%rdi + 4090c4: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4090c9: e8 42 cb ff ff callq 405c10 <__gettext_free_exp> + 4090ce: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4090d3: 48 8b 78 10 mov 0x10(%rax),%rdi + 4090d7: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4090dc: e8 2f cb ff ff callq 405c10 <__gettext_free_exp> + 4090e1: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4090e6: 48 8b 78 08 mov 0x8(%rax),%rdi + 4090ea: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4090ef: e8 1c cb ff ff callq 405c10 <__gettext_free_exp> + 4090f4: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4090f9: e9 84 df ff ff jmpq 407082 + 4090fe: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 409102: 48 89 44 24 08 mov %rax,0x8(%rsp) + 409107: 48 89 14 24 mov %rdx,(%rsp) + 40910b: e8 00 cb ff ff callq 405c10 <__gettext_free_exp> + 409110: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 409115: 48 8b 14 24 mov (%rsp),%rdx + 409119: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 40911d: 48 89 44 24 08 mov %rax,0x8(%rsp) + 409122: 48 89 14 24 mov %rdx,(%rsp) + 409126: e8 e5 ca ff ff callq 405c10 <__gettext_free_exp> + 40912b: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 409130: 48 8b 14 24 mov (%rsp),%rdx + 409134: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 409138: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40913d: 48 89 14 24 mov %rdx,(%rsp) + 409141: e8 ca ca ff ff callq 405c10 <__gettext_free_exp> + 409146: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40914b: 48 8b 14 24 mov (%rsp),%rdx + 40914f: e9 d3 fa ff ff jmpq 408c27 + 409154: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 409158: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40915d: 48 89 14 24 mov %rdx,(%rsp) + 409161: e8 aa ca ff ff callq 405c10 <__gettext_free_exp> + 409166: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40916b: 48 8b 14 24 mov (%rsp),%rdx + 40916f: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 409173: 48 89 44 24 08 mov %rax,0x8(%rsp) + 409178: 48 89 14 24 mov %rdx,(%rsp) + 40917c: e8 8f ca ff ff callq 405c10 <__gettext_free_exp> + 409181: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 409186: 48 8b 14 24 mov (%rsp),%rdx + 40918a: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 40918e: 48 89 44 24 08 mov %rax,0x8(%rsp) + 409193: 48 89 14 24 mov %rdx,(%rsp) + 409197: e8 74 ca ff ff callq 405c10 <__gettext_free_exp> + 40919c: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4091a1: 48 8b 14 24 mov (%rsp),%rdx + 4091a5: e9 1b f3 ff ff jmpq 4084c5 + 4091aa: 48 8b 78 18 mov 0x18(%rax),%rdi + 4091ae: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4091b3: e8 58 ca ff ff callq 405c10 <__gettext_free_exp> + 4091b8: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4091bd: 48 8b 78 10 mov 0x10(%rax),%rdi + 4091c1: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4091c6: e8 45 ca ff ff callq 405c10 <__gettext_free_exp> + 4091cb: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4091d0: 48 8b 78 08 mov 0x8(%rax),%rdi + 4091d4: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4091d9: e8 32 ca ff ff callq 405c10 <__gettext_free_exp> + 4091de: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4091e3: e9 3f e9 ff ff jmpq 407b27 + 4091e8: 48 8b 78 18 mov 0x18(%rax),%rdi + 4091ec: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4091f1: e8 1a ca ff ff callq 405c10 <__gettext_free_exp> + 4091f6: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4091fb: 48 8b 78 10 mov 0x10(%rax),%rdi + 4091ff: 48 89 44 24 08 mov %rax,0x8(%rsp) + 409204: e8 07 ca ff ff callq 405c10 <__gettext_free_exp> + 409209: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40920e: 48 8b 78 08 mov 0x8(%rax),%rdi + 409212: 48 89 44 24 08 mov %rax,0x8(%rsp) + 409217: e8 f4 c9 ff ff callq 405c10 <__gettext_free_exp> + 40921c: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 409221: e9 81 e8 ff ff jmpq 407aa7 + 409226: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 40922a: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40922f: 48 89 14 24 mov %rdx,(%rsp) + 409233: e8 d8 c9 ff ff callq 405c10 <__gettext_free_exp> + 409238: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40923d: 48 8b 14 24 mov (%rsp),%rdx + 409241: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 409245: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40924a: 48 89 14 24 mov %rdx,(%rsp) + 40924e: e8 bd c9 ff ff callq 405c10 <__gettext_free_exp> + 409253: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 409258: 48 8b 14 24 mov (%rsp),%rdx + 40925c: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 409260: 48 89 44 24 08 mov %rax,0x8(%rsp) + 409265: 48 89 14 24 mov %rdx,(%rsp) + 409269: e8 a2 c9 ff ff callq 405c10 <__gettext_free_exp> + 40926e: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 409273: 48 8b 14 24 mov (%rsp),%rdx + 409277: e9 0c fa ff ff jmpq 408c88 + 40927c: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 409280: 48 89 44 24 08 mov %rax,0x8(%rsp) + 409285: 48 89 14 24 mov %rdx,(%rsp) + 409289: e8 82 c9 ff ff callq 405c10 <__gettext_free_exp> + 40928e: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 409293: 48 8b 14 24 mov (%rsp),%rdx + 409297: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 40929b: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4092a0: 48 89 14 24 mov %rdx,(%rsp) + 4092a4: e8 67 c9 ff ff callq 405c10 <__gettext_free_exp> + 4092a9: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4092ae: 48 8b 14 24 mov (%rsp),%rdx + 4092b2: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 4092b6: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4092bb: 48 89 14 24 mov %rdx,(%rsp) + 4092bf: e8 4c c9 ff ff callq 405c10 <__gettext_free_exp> + 4092c4: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4092c9: 48 8b 14 24 mov (%rsp),%rdx + 4092cd: e9 78 fa ff ff jmpq 408d4a + 4092d2: 48 8b 78 18 mov 0x18(%rax),%rdi + 4092d6: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4092db: e8 30 c9 ff ff callq 405c10 <__gettext_free_exp> + 4092e0: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4092e5: 48 8b 78 10 mov 0x10(%rax),%rdi + 4092e9: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4092ee: e8 1d c9 ff ff callq 405c10 <__gettext_free_exp> + 4092f3: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4092f8: 48 8b 78 08 mov 0x8(%rax),%rdi + 4092fc: 48 89 44 24 08 mov %rax,0x8(%rsp) + 409301: e8 0a c9 ff ff callq 405c10 <__gettext_free_exp> + 409306: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40930b: e9 3a df ff ff jmpq 40724a + 409310: 48 8b 78 18 mov 0x18(%rax),%rdi + 409314: 48 89 44 24 08 mov %rax,0x8(%rsp) + 409319: e8 f2 c8 ff ff callq 405c10 <__gettext_free_exp> + 40931e: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 409323: 48 8b 78 10 mov 0x10(%rax),%rdi + 409327: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40932c: e8 df c8 ff ff callq 405c10 <__gettext_free_exp> + 409331: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 409336: 48 8b 78 08 mov 0x8(%rax),%rdi + 40933a: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40933f: e8 cc c8 ff ff callq 405c10 <__gettext_free_exp> + 409344: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 409349: e9 1c de ff ff jmpq 40716a + 40934e: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 409352: 48 89 44 24 08 mov %rax,0x8(%rsp) + 409357: 48 89 14 24 mov %rdx,(%rsp) + 40935b: e8 b0 c8 ff ff callq 405c10 <__gettext_free_exp> + 409360: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 409365: 48 8b 14 24 mov (%rsp),%rdx + 409369: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 40936d: 48 89 44 24 08 mov %rax,0x8(%rsp) + 409372: 48 89 14 24 mov %rdx,(%rsp) + 409376: e8 95 c8 ff ff callq 405c10 <__gettext_free_exp> + 40937b: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 409380: 48 8b 14 24 mov (%rsp),%rdx + 409384: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 409388: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40938d: 48 89 14 24 mov %rdx,(%rsp) + 409391: e8 7a c8 ff ff callq 405c10 <__gettext_free_exp> + 409396: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40939b: 48 8b 14 24 mov (%rsp),%rdx + 40939f: e9 45 f9 ff ff jmpq 408ce9 + 4093a4: 48 8b 78 18 mov 0x18(%rax),%rdi + 4093a8: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4093ad: e8 5e c8 ff ff callq 405c10 <__gettext_free_exp> + 4093b2: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4093b7: 48 8b 78 10 mov 0x10(%rax),%rdi + 4093bb: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4093c0: e8 4b c8 ff ff callq 405c10 <__gettext_free_exp> + 4093c5: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4093ca: 48 8b 78 08 mov 0x8(%rax),%rdi + 4093ce: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4093d3: e8 38 c8 ff ff callq 405c10 <__gettext_free_exp> + 4093d8: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4093dd: e9 c6 f1 ff ff jmpq 4085a8 + 4093e2: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 4093e6: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4093eb: 48 89 14 24 mov %rdx,(%rsp) + 4093ef: e8 1c c8 ff ff callq 405c10 <__gettext_free_exp> + 4093f4: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4093f9: 48 8b 14 24 mov (%rsp),%rdx + 4093fd: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 409401: 48 89 44 24 08 mov %rax,0x8(%rsp) + 409406: 48 89 14 24 mov %rdx,(%rsp) + 40940a: e8 01 c8 ff ff callq 405c10 <__gettext_free_exp> + 40940f: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 409414: 48 8b 14 24 mov (%rsp),%rdx + 409418: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 40941c: 48 89 44 24 08 mov %rax,0x8(%rsp) + 409421: 48 89 14 24 mov %rdx,(%rsp) + 409425: e8 e6 c7 ff ff callq 405c10 <__gettext_free_exp> + 40942a: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40942f: 48 8b 14 24 mov (%rsp),%rdx + 409433: e9 ee f0 ff ff jmpq 408526 + 409438: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 40943c: 48 89 44 24 08 mov %rax,0x8(%rsp) + 409441: 48 89 14 24 mov %rdx,(%rsp) + 409445: e8 c6 c7 ff ff callq 405c10 <__gettext_free_exp> + 40944a: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40944f: 48 8b 14 24 mov (%rsp),%rdx + 409453: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 409457: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40945c: 48 89 14 24 mov %rdx,(%rsp) + 409460: e8 ab c7 ff ff callq 405c10 <__gettext_free_exp> + 409465: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40946a: 48 8b 14 24 mov (%rsp),%rdx + 40946e: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 409472: 48 89 44 24 08 mov %rax,0x8(%rsp) + 409477: 48 89 14 24 mov %rdx,(%rsp) + 40947b: e8 90 c7 ff ff callq 405c10 <__gettext_free_exp> + 409480: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 409485: 48 8b 14 24 mov (%rsp),%rdx + 409489: e9 14 ef ff ff jmpq 4083a2 + 40948e: 48 8b 78 18 mov 0x18(%rax),%rdi + 409492: 48 89 44 24 08 mov %rax,0x8(%rsp) + 409497: e8 74 c7 ff ff callq 405c10 <__gettext_free_exp> + 40949c: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4094a1: 48 8b 78 10 mov 0x10(%rax),%rdi + 4094a5: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4094aa: e8 61 c7 ff ff callq 405c10 <__gettext_free_exp> + 4094af: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4094b4: 48 8b 78 08 mov 0x8(%rax),%rdi + 4094b8: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4094bd: e8 4e c7 ff ff callq 405c10 <__gettext_free_exp> + 4094c2: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4094c7: e9 db e4 ff ff jmpq 4079a7 + 4094cc: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 4094d0: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4094d5: 48 89 14 24 mov %rdx,(%rsp) + 4094d9: e8 32 c7 ff ff callq 405c10 <__gettext_free_exp> + 4094de: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4094e3: 48 8b 14 24 mov (%rsp),%rdx + 4094e7: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 4094eb: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4094f0: 48 89 14 24 mov %rdx,(%rsp) + 4094f4: e8 17 c7 ff ff callq 405c10 <__gettext_free_exp> + 4094f9: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4094fe: 48 8b 14 24 mov (%rsp),%rdx + 409502: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 409506: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40950b: 48 89 14 24 mov %rdx,(%rsp) + 40950f: e8 fc c6 ff ff callq 405c10 <__gettext_free_exp> + 409514: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 409519: 48 8b 14 24 mov (%rsp),%rdx + 40951d: e9 42 ef ff ff jmpq 408464 + 409522: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 409526: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40952b: 48 89 14 24 mov %rdx,(%rsp) + 40952f: e8 dc c6 ff ff callq 405c10 <__gettext_free_exp> + 409534: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 409539: 48 8b 14 24 mov (%rsp),%rdx + 40953d: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 409541: 48 89 44 24 08 mov %rax,0x8(%rsp) + 409546: 48 89 14 24 mov %rdx,(%rsp) + 40954a: e8 c1 c6 ff ff callq 405c10 <__gettext_free_exp> + 40954f: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 409554: 48 8b 14 24 mov (%rsp),%rdx + 409558: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 40955c: 48 89 44 24 08 mov %rax,0x8(%rsp) + 409561: 48 89 14 24 mov %rdx,(%rsp) + 409565: e8 a6 c6 ff ff callq 405c10 <__gettext_free_exp> + 40956a: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40956f: 48 8b 14 24 mov (%rsp),%rdx + 409573: e9 8b ee ff ff jmpq 408403 + 409578: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 40957c: 48 89 44 24 08 mov %rax,0x8(%rsp) + 409581: 48 89 14 24 mov %rdx,(%rsp) + 409585: e8 86 c6 ff ff callq 405c10 <__gettext_free_exp> + 40958a: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40958f: 48 8b 14 24 mov (%rsp),%rdx + 409593: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 409597: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40959c: 48 89 14 24 mov %rdx,(%rsp) + 4095a0: e8 6b c6 ff ff callq 405c10 <__gettext_free_exp> + 4095a5: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4095aa: 48 8b 14 24 mov (%rsp),%rdx + 4095ae: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 4095b2: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4095b7: 48 89 14 24 mov %rdx,(%rsp) + 4095bb: e8 50 c6 ff ff callq 405c10 <__gettext_free_exp> + 4095c0: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4095c5: 48 8b 14 24 mov (%rsp),%rdx + 4095c9: e9 97 f5 ff ff jmpq 408b65 + 4095ce: 48 8b 78 18 mov 0x18(%rax),%rdi + 4095d2: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4095d7: e8 34 c6 ff ff callq 405c10 <__gettext_free_exp> + 4095dc: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4095e1: 48 8b 78 10 mov 0x10(%rax),%rdi + 4095e5: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4095ea: e8 21 c6 ff ff callq 405c10 <__gettext_free_exp> + 4095ef: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4095f4: 48 8b 78 08 mov 0x8(%rax),%rdi + 4095f8: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4095fd: e8 0e c6 ff ff callq 405c10 <__gettext_free_exp> + 409602: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 409607: e9 1e dd ff ff jmpq 40732a + 40960c: 48 8b 78 18 mov 0x18(%rax),%rdi + 409610: 48 89 44 24 08 mov %rax,0x8(%rsp) + 409615: e8 f6 c5 ff ff callq 405c10 <__gettext_free_exp> + 40961a: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40961f: 48 8b 78 10 mov 0x10(%rax),%rdi + 409623: 48 89 44 24 08 mov %rax,0x8(%rsp) + 409628: e8 e3 c5 ff ff callq 405c10 <__gettext_free_exp> + 40962d: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 409632: 48 8b 78 08 mov 0x8(%rax),%rdi + 409636: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40963b: e8 d0 c5 ff ff callq 405c10 <__gettext_free_exp> + 409640: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 409645: e9 dd e3 ff ff jmpq 407a27 + 40964a: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 40964e: 48 89 44 24 08 mov %rax,0x8(%rsp) + 409653: 48 89 14 24 mov %rdx,(%rsp) + 409657: e8 b4 c5 ff ff callq 405c10 <__gettext_free_exp> + 40965c: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 409661: 48 8b 14 24 mov (%rsp),%rdx + 409665: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 409669: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40966e: 48 89 14 24 mov %rdx,(%rsp) + 409672: e8 99 c5 ff ff callq 405c10 <__gettext_free_exp> + 409677: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40967c: 48 8b 14 24 mov (%rsp),%rdx + 409680: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 409684: 48 89 44 24 08 mov %rax,0x8(%rsp) + 409689: 48 89 14 24 mov %rdx,(%rsp) + 40968d: e8 7e c5 ff ff callq 405c10 <__gettext_free_exp> + 409692: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 409697: 48 8b 14 24 mov (%rsp),%rdx + 40969b: e9 26 f5 ff ff jmpq 408bc6 + 4096a0: 48 8b 04 24 mov (%rsp),%rax + 4096a4: 48 8b 40 18 mov 0x18(%rax),%rax + 4096a8: 48 85 c0 test %rax,%rax + 4096ab: 0f 84 06 d4 ff ff je 406ab7 + 4096b1: 8b 10 mov (%rax),%edx + 4096b3: 83 fa 02 cmp $0x2,%edx + 4096b6: 0f 84 cd d3 ff ff je 406a89 + 4096bc: 83 fa 03 cmp $0x3,%edx + 4096bf: 0f 84 b1 d3 ff ff je 406a76 + 4096c5: 83 fa 01 cmp $0x1,%edx + 4096c8: 0f 85 e1 d3 ff ff jne 406aaf + 4096ce: e9 c9 d3 ff ff jmpq 406a9c + 4096d3: 48 8b 78 18 mov 0x18(%rax),%rdi + 4096d7: 48 89 04 24 mov %rax,(%rsp) + 4096db: e8 30 c5 ff ff callq 405c10 <__gettext_free_exp> + 4096e0: 48 8b 04 24 mov (%rsp),%rax + 4096e4: 48 8b 78 10 mov 0x10(%rax),%rdi + 4096e8: 48 89 04 24 mov %rax,(%rsp) + 4096ec: e8 1f c5 ff ff callq 405c10 <__gettext_free_exp> + 4096f1: 48 8b 04 24 mov (%rsp),%rax + 4096f5: 48 8b 78 08 mov 0x8(%rax),%rdi + 4096f9: 48 89 04 24 mov %rax,(%rsp) + 4096fd: e8 0e c5 ff ff callq 405c10 <__gettext_free_exp> + 409702: 48 8b 04 24 mov (%rsp),%rax + 409706: e9 04 e5 ff ff jmpq 407c0f + 40970b: 48 8b 78 18 mov 0x18(%rax),%rdi + 40970f: 48 89 04 24 mov %rax,(%rsp) + 409713: e8 f8 c4 ff ff callq 405c10 <__gettext_free_exp> + 409718: 48 8b 04 24 mov (%rsp),%rax + 40971c: 48 8b 78 10 mov 0x10(%rax),%rdi + 409720: 48 89 04 24 mov %rax,(%rsp) + 409724: e8 e7 c4 ff ff callq 405c10 <__gettext_free_exp> + 409729: 48 8b 04 24 mov (%rsp),%rax + 40972d: 48 8b 78 08 mov 0x8(%rax),%rdi + 409731: 48 89 04 24 mov %rax,(%rsp) + 409735: e8 d6 c4 ff ff callq 405c10 <__gettext_free_exp> + 40973a: 48 8b 04 24 mov (%rsp),%rax + 40973e: e9 40 ef ff ff jmpq 408683 + 409743: 48 8b 78 18 mov 0x18(%rax),%rdi + 409747: 48 89 04 24 mov %rax,(%rsp) + 40974b: e8 c0 c4 ff ff callq 405c10 <__gettext_free_exp> + 409750: 48 8b 04 24 mov (%rsp),%rax + 409754: 48 8b 78 10 mov 0x10(%rax),%rdi + 409758: 48 89 04 24 mov %rax,(%rsp) + 40975c: e8 af c4 ff ff callq 405c10 <__gettext_free_exp> + 409761: 48 8b 04 24 mov (%rsp),%rax + 409765: 48 8b 78 08 mov 0x8(%rax),%rdi + 409769: 48 89 04 24 mov %rax,(%rsp) + 40976d: e8 9e c4 ff ff callq 405c10 <__gettext_free_exp> + 409772: 48 8b 04 24 mov (%rsp),%rax + 409776: e9 54 e6 ff ff jmpq 407dcf + 40977b: 48 8b 78 18 mov 0x18(%rax),%rdi + 40977f: 48 89 04 24 mov %rax,(%rsp) + 409783: e8 88 c4 ff ff callq 405c10 <__gettext_free_exp> + 409788: 48 8b 04 24 mov (%rsp),%rax + 40978c: 48 8b 78 10 mov 0x10(%rax),%rdi + 409790: 48 89 04 24 mov %rax,(%rsp) + 409794: e8 77 c4 ff ff callq 405c10 <__gettext_free_exp> + 409799: 48 8b 04 24 mov (%rsp),%rax + 40979d: 48 8b 78 08 mov 0x8(%rax),%rdi + 4097a1: 48 89 04 24 mov %rax,(%rsp) + 4097a5: e8 66 c4 ff ff callq 405c10 <__gettext_free_exp> + 4097aa: 48 8b 04 24 mov (%rsp),%rax + 4097ae: e9 ac e5 ff ff jmpq 407d5f + 4097b3: 48 8b 78 18 mov 0x18(%rax),%rdi + 4097b7: 48 89 04 24 mov %rax,(%rsp) + 4097bb: e8 50 c4 ff ff callq 405c10 <__gettext_free_exp> + 4097c0: 48 8b 04 24 mov (%rsp),%rax + 4097c4: 48 8b 78 10 mov 0x10(%rax),%rdi + 4097c8: 48 89 04 24 mov %rax,(%rsp) + 4097cc: e8 3f c4 ff ff callq 405c10 <__gettext_free_exp> + 4097d1: 48 8b 04 24 mov (%rsp),%rax + 4097d5: 48 8b 50 08 mov 0x8(%rax),%rdx + 4097d9: 48 85 d2 test %rdx,%rdx + 4097dc: 0f 84 9c dc ff ff je 40747e + 4097e2: 8b 0a mov (%rdx),%ecx + 4097e4: 83 f9 02 cmp $0x2,%ecx + 4097e7: 74 3a je 409823 + 4097e9: 83 f9 03 cmp $0x3,%ecx + 4097ec: 74 1a je 409808 + 4097ee: 83 f9 01 cmp $0x1,%ecx + 4097f1: 74 4b je 40983e + 4097f3: 48 89 d7 mov %rdx,%rdi + 4097f6: 48 89 04 24 mov %rax,(%rsp) + 4097fa: e8 b1 45 01 00 callq 41ddb0 <__cfree> + 4097ff: 48 8b 04 24 mov (%rsp),%rax + 409803: e9 76 dc ff ff jmpq 40747e + 409808: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 40980c: 48 89 44 24 08 mov %rax,0x8(%rsp) + 409811: 48 89 14 24 mov %rdx,(%rsp) + 409815: e8 f6 c3 ff ff callq 405c10 <__gettext_free_exp> + 40981a: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40981f: 48 8b 14 24 mov (%rsp),%rdx + 409823: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 409827: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40982c: 48 89 14 24 mov %rdx,(%rsp) + 409830: e8 db c3 ff ff callq 405c10 <__gettext_free_exp> + 409835: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40983a: 48 8b 14 24 mov (%rsp),%rdx + 40983e: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 409842: 48 89 44 24 08 mov %rax,0x8(%rsp) + 409847: 48 89 14 24 mov %rdx,(%rsp) + 40984b: e8 c0 c3 ff ff callq 405c10 <__gettext_free_exp> + 409850: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 409855: 48 8b 14 24 mov (%rsp),%rdx + 409859: eb 98 jmp 4097f3 + 40985b: 48 8b 78 18 mov 0x18(%rax),%rdi + 40985f: 48 89 04 24 mov %rax,(%rsp) + 409863: e8 a8 c3 ff ff callq 405c10 <__gettext_free_exp> + 409868: 48 8b 04 24 mov (%rsp),%rax + 40986c: 48 8b 78 10 mov 0x10(%rax),%rdi + 409870: 48 89 04 24 mov %rax,(%rsp) + 409874: e8 97 c3 ff ff callq 405c10 <__gettext_free_exp> + 409879: 48 8b 04 24 mov (%rsp),%rax + 40987d: 48 8b 50 08 mov 0x8(%rax),%rdx + 409881: 48 85 d2 test %rdx,%rdx + 409884: 0f 84 ec dd ff ff je 407676 + 40988a: 8b 0a mov (%rdx),%ecx + 40988c: 83 f9 02 cmp $0x2,%ecx + 40988f: 74 3a je 4098cb + 409891: 83 f9 03 cmp $0x3,%ecx + 409894: 74 1a je 4098b0 + 409896: 83 f9 01 cmp $0x1,%ecx + 409899: 74 4b je 4098e6 + 40989b: 48 89 d7 mov %rdx,%rdi + 40989e: 48 89 04 24 mov %rax,(%rsp) + 4098a2: e8 09 45 01 00 callq 41ddb0 <__cfree> + 4098a7: 48 8b 04 24 mov (%rsp),%rax + 4098ab: e9 c6 dd ff ff jmpq 407676 + 4098b0: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 4098b4: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4098b9: 48 89 14 24 mov %rdx,(%rsp) + 4098bd: e8 4e c3 ff ff callq 405c10 <__gettext_free_exp> + 4098c2: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4098c7: 48 8b 14 24 mov (%rsp),%rdx + 4098cb: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 4098cf: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4098d4: 48 89 14 24 mov %rdx,(%rsp) + 4098d8: e8 33 c3 ff ff callq 405c10 <__gettext_free_exp> + 4098dd: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4098e2: 48 8b 14 24 mov (%rsp),%rdx + 4098e6: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 4098ea: 48 89 44 24 08 mov %rax,0x8(%rsp) + 4098ef: 48 89 14 24 mov %rdx,(%rsp) + 4098f3: e8 18 c3 ff ff callq 405c10 <__gettext_free_exp> + 4098f8: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4098fd: 48 8b 14 24 mov (%rsp),%rdx + 409901: eb 98 jmp 40989b + 409903: 48 8b 78 18 mov 0x18(%rax),%rdi + 409907: 48 89 04 24 mov %rax,(%rsp) + 40990b: e8 00 c3 ff ff callq 405c10 <__gettext_free_exp> + 409910: 48 8b 04 24 mov (%rsp),%rax + 409914: 48 8b 78 10 mov 0x10(%rax),%rdi + 409918: 48 89 04 24 mov %rax,(%rsp) + 40991c: e8 ef c2 ff ff callq 405c10 <__gettext_free_exp> + 409921: 48 8b 04 24 mov (%rsp),%rax + 409925: 48 8b 78 08 mov 0x8(%rax),%rdi + 409929: 48 89 04 24 mov %rax,(%rsp) + 40992d: e8 de c2 ff ff callq 405c10 <__gettext_free_exp> + 409932: 48 8b 04 24 mov (%rsp),%rax + 409936: e9 b6 ec ff ff jmpq 4085f1 + 40993b: 48 8b 78 18 mov 0x18(%rax),%rdi + 40993f: 48 89 04 24 mov %rax,(%rsp) + 409943: e8 c8 c2 ff ff callq 405c10 <__gettext_free_exp> + 409948: 48 8b 04 24 mov (%rsp),%rax + 40994c: 48 8b 78 10 mov 0x10(%rax),%rdi + 409950: 48 89 04 24 mov %rax,(%rsp) + 409954: e8 b7 c2 ff ff callq 405c10 <__gettext_free_exp> + 409959: 48 8b 04 24 mov (%rsp),%rax + 40995d: 48 8b 78 08 mov 0x8(%rax),%rdi + 409961: 48 89 04 24 mov %rax,(%rsp) + 409965: e8 a6 c2 ff ff callq 405c10 <__gettext_free_exp> + 40996a: 48 8b 04 24 mov (%rsp),%rax + 40996e: e9 2c e2 ff ff jmpq 407b9f + 409973: 48 8b 78 18 mov 0x18(%rax),%rdi + 409977: 48 89 04 24 mov %rax,(%rsp) + 40997b: e8 90 c2 ff ff callq 405c10 <__gettext_free_exp> + 409980: 48 8b 04 24 mov (%rsp),%rax + 409984: 48 8b 78 10 mov 0x10(%rax),%rdi + 409988: 48 89 04 24 mov %rax,(%rsp) + 40998c: e8 7f c2 ff ff callq 405c10 <__gettext_free_exp> + 409991: 48 8b 04 24 mov (%rsp),%rax + 409995: 48 8b 78 08 mov 0x8(%rax),%rdi + 409999: 48 89 04 24 mov %rax,(%rsp) + 40999d: e8 6e c2 ff ff callq 405c10 <__gettext_free_exp> + 4099a2: 48 8b 04 24 mov (%rsp),%rax + 4099a6: e9 8f ec ff ff jmpq 40863a + 4099ab: 48 8b 78 18 mov 0x18(%rax),%rdi + 4099af: 48 89 04 24 mov %rax,(%rsp) + 4099b3: e8 58 c2 ff ff callq 405c10 <__gettext_free_exp> + 4099b8: 48 8b 04 24 mov (%rsp),%rax + 4099bc: 48 8b 78 10 mov 0x10(%rax),%rdi + 4099c0: 48 89 04 24 mov %rax,(%rsp) + 4099c4: e8 47 c2 ff ff callq 405c10 <__gettext_free_exp> + 4099c9: 48 8b 04 24 mov (%rsp),%rax + 4099cd: 48 8b 78 08 mov 0x8(%rax),%rdi + 4099d1: 48 89 04 24 mov %rax,(%rsp) + 4099d5: e8 36 c2 ff ff callq 405c10 <__gettext_free_exp> + 4099da: 48 8b 04 24 mov (%rsp),%rax + 4099de: e9 9c e2 ff ff jmpq 407c7f + 4099e3: 48 8b 78 18 mov 0x18(%rax),%rdi + 4099e7: 48 89 04 24 mov %rax,(%rsp) + 4099eb: e8 20 c2 ff ff callq 405c10 <__gettext_free_exp> + 4099f0: 48 8b 04 24 mov (%rsp),%rax + 4099f4: 48 8b 78 10 mov 0x10(%rax),%rdi + 4099f8: 48 89 04 24 mov %rax,(%rsp) + 4099fc: e8 0f c2 ff ff callq 405c10 <__gettext_free_exp> + 409a01: 48 8b 04 24 mov (%rsp),%rax + 409a05: 48 8b 78 08 mov 0x8(%rax),%rdi + 409a09: 48 89 04 24 mov %rax,(%rsp) + 409a0d: e8 fe c1 ff ff callq 405c10 <__gettext_free_exp> + 409a12: 48 8b 04 24 mov (%rsp),%rax + 409a16: e9 d4 e2 ff ff jmpq 407cef + 409a1b: 48 8b 78 18 mov 0x18(%rax),%rdi + 409a1f: 48 89 04 24 mov %rax,(%rsp) + 409a23: e8 e8 c1 ff ff callq 405c10 <__gettext_free_exp> + 409a28: 48 8b 04 24 mov (%rsp),%rax + 409a2c: 48 8b 78 10 mov 0x10(%rax),%rdi + 409a30: 48 89 04 24 mov %rax,(%rsp) + 409a34: e8 d7 c1 ff ff callq 405c10 <__gettext_free_exp> + 409a39: 48 8b 04 24 mov (%rsp),%rax + 409a3d: 48 8b 78 08 mov 0x8(%rax),%rdi + 409a41: 48 89 04 24 mov %rax,(%rsp) + 409a45: e8 c6 c1 ff ff callq 405c10 <__gettext_free_exp> + 409a4a: 48 8b 04 24 mov (%rsp),%rax + 409a4e: e9 43 dd ff ff jmpq 407796 + 409a53: 0f 1f 00 nopl (%rax) + 409a56: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 409a5d: 00 00 00 + +0000000000409a60 : + 409a60: 41 57 push %r15 + 409a62: 41 56 push %r14 + 409a64: 41 55 push %r13 + 409a66: 41 54 push %r12 + 409a68: 4c 63 e7 movslq %edi,%r12 + 409a6b: 55 push %rbp + 409a6c: 53 push %rbx + 409a6d: 41 8d 5c 24 ff lea -0x1(%r12),%ebx + 409a72: 48 83 ec 18 sub $0x18,%rsp + 409a76: 85 db test %ebx,%ebx + 409a78: 0f 88 85 37 00 00 js 40d203 + 409a7e: 4c 63 eb movslq %ebx,%r13 + 409a81: 49 89 d7 mov %rdx,%r15 + 409a84: 89 dd mov %ebx,%ebp + 409a86: 4a 83 3c ea 00 cmpq $0x0,(%rdx,%r13,8) + 409a8b: 4a 8d 04 ed 00 00 00 lea 0x0(,%r13,8),%rax + 409a92: 00 + 409a93: 48 8d 4c 02 f8 lea -0x8(%rdx,%rax,1),%rcx + 409a98: 89 d8 mov %ebx,%eax + 409a9a: 75 0f jne 409aab + 409a9c: eb 72 jmp 409b10 + 409a9e: 66 90 xchg %ax,%ax + 409aa0: 48 83 e9 08 sub $0x8,%rcx + 409aa4: 48 83 79 08 00 cmpq $0x0,0x8(%rcx) + 409aa9: 74 65 je 409b10 + 409aab: 83 e8 01 sub $0x1,%eax + 409aae: 83 f8 ff cmp $0xffffffff,%eax + 409ab1: 75 ed jne 409aa0 + 409ab3: bf 20 00 00 00 mov $0x20,%edi + 409ab8: 89 34 24 mov %esi,(%rsp) + 409abb: e8 50 3f 01 00 callq 41da10 <__libc_malloc> + 409ac0: 48 85 c0 test %rax,%rax + 409ac3: 49 89 c6 mov %rax,%r14 + 409ac6: 8b 34 24 mov (%rsp),%esi + 409ac9: 74 45 je 409b10 + 409acb: 41 89 76 04 mov %esi,0x4(%r14) + 409acf: 4a 8d 34 e5 00 00 00 lea 0x0(,%r12,8),%rsi + 409ad6: 00 + 409ad7: 89 db mov %ebx,%ebx + 409ad9: 48 8d 14 dd 08 00 00 lea 0x8(,%rbx,8),%rdx + 409ae0: 00 + 409ae1: 45 89 26 mov %r12d,(%r14) + 409ae4: 48 8d 7e 08 lea 0x8(%rsi),%rdi + 409ae8: 48 29 d6 sub %rdx,%rsi + 409aeb: 48 29 d7 sub %rdx,%rdi + 409aee: 4c 01 fe add %r15,%rsi + 409af1: 4c 01 f7 add %r14,%rdi + 409af4: e8 27 25 02 00 callq 42c020 + 409af9: 48 83 c4 18 add $0x18,%rsp + 409afd: 4c 89 f0 mov %r14,%rax + 409b00: 5b pop %rbx + 409b01: 5d pop %rbp + 409b02: 41 5c pop %r12 + 409b04: 41 5d pop %r13 + 409b06: 41 5e pop %r14 + 409b08: 41 5f pop %r15 + 409b0a: c3 retq + 409b0b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 409b10: 4f 8d 24 ef lea (%r15,%r13,8),%r12 + 409b14: eb 30 jmp 409b46 + 409b16: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 409b1d: 00 00 00 + 409b20: 83 f8 03 cmp $0x3,%eax + 409b23: 0f 84 f7 02 00 00 je 409e20 + 409b29: 83 f8 01 cmp $0x1,%eax + 409b2c: 74 58 je 409b86 + 409b2e: 48 89 df mov %rbx,%rdi + 409b31: e8 7a 42 01 00 callq 41ddb0 <__cfree> + 409b36: 83 ed 01 sub $0x1,%ebp + 409b39: 49 83 ec 08 sub $0x8,%r12 + 409b3d: 83 fd ff cmp $0xffffffff,%ebp + 409b40: 0f 84 8a 0a 00 00 je 40a5d0 + 409b46: 49 8b 1c 24 mov (%r12),%rbx + 409b4a: 48 85 db test %rbx,%rbx + 409b4d: 74 e7 je 409b36 + 409b4f: 8b 03 mov (%rbx),%eax + 409b51: 83 f8 02 cmp $0x2,%eax + 409b54: 75 ca jne 409b20 + 409b56: 4c 8b 6b 10 mov 0x10(%rbx),%r13 + 409b5a: 4d 85 ed test %r13,%r13 + 409b5d: 74 27 je 409b86 + 409b5f: 41 8b 45 00 mov 0x0(%r13),%eax + 409b63: 83 f8 02 cmp $0x2,%eax + 409b66: 0f 84 35 09 00 00 je 40a4a1 + 409b6c: 83 f8 03 cmp $0x3,%eax + 409b6f: 0f 84 1b 0a 00 00 je 40a590 + 409b75: 83 f8 01 cmp $0x1,%eax + 409b78: 0f 84 63 02 00 00 je 409de1 + 409b7e: 4c 89 ef mov %r13,%rdi + 409b81: e8 2a 42 01 00 callq 41ddb0 <__cfree> + 409b86: 4c 8b 6b 08 mov 0x8(%rbx),%r13 + 409b8a: 4d 85 ed test %r13,%r13 + 409b8d: 74 9f je 409b2e + 409b8f: 41 8b 45 00 mov 0x0(%r13),%eax + 409b93: 83 f8 02 cmp $0x2,%eax + 409b96: 74 47 je 409bdf + 409b98: 83 f8 03 cmp $0x3,%eax + 409b9b: 74 13 je 409bb0 + 409b9d: 83 f8 01 cmp $0x1,%eax + 409ba0: 74 6c je 409c0e + 409ba2: 4c 89 ef mov %r13,%rdi + 409ba5: e8 06 42 01 00 callq 41ddb0 <__cfree> + 409baa: eb 82 jmp 409b2e + 409bac: 0f 1f 40 00 nopl 0x0(%rax) + 409bb0: 4d 8b 75 18 mov 0x18(%r13),%r14 + 409bb4: 4d 85 f6 test %r14,%r14 + 409bb7: 74 26 je 409bdf + 409bb9: 41 8b 06 mov (%r14),%eax + 409bbc: 83 f8 02 cmp $0x2,%eax + 409bbf: 0f 84 ca 0d 00 00 je 40a98f + 409bc5: 83 f8 03 cmp $0x3,%eax + 409bc8: 0f 84 92 0d 00 00 je 40a960 + 409bce: 83 f8 01 cmp $0x1,%eax + 409bd1: 0f 84 e7 0d 00 00 je 40a9be + 409bd7: 4c 89 f7 mov %r14,%rdi + 409bda: e8 d1 41 01 00 callq 41ddb0 <__cfree> + 409bdf: 4d 8b 75 10 mov 0x10(%r13),%r14 + 409be3: 4d 85 f6 test %r14,%r14 + 409be6: 74 26 je 409c0e + 409be8: 41 8b 06 mov (%r14),%eax + 409beb: 83 f8 02 cmp $0x2,%eax + 409bee: 0f 84 8b 04 00 00 je 40a07f + 409bf4: 83 f8 03 cmp $0x3,%eax + 409bf7: 0f 84 53 04 00 00 je 40a050 + 409bfd: 83 f8 01 cmp $0x1,%eax + 409c00: 0f 84 a8 04 00 00 je 40a0ae + 409c06: 4c 89 f7 mov %r14,%rdi + 409c09: e8 a2 41 01 00 callq 41ddb0 <__cfree> + 409c0e: 4d 8b 75 08 mov 0x8(%r13),%r14 + 409c12: 4d 85 f6 test %r14,%r14 + 409c15: 74 8b je 409ba2 + 409c17: 41 8b 06 mov (%r14),%eax + 409c1a: 83 f8 02 cmp $0x2,%eax + 409c1d: 0f 84 2f 06 00 00 je 40a252 + 409c23: 83 f8 03 cmp $0x3,%eax + 409c26: 0f 84 b4 08 00 00 je 40a4e0 + 409c2c: 83 f8 01 cmp $0x1,%eax + 409c2f: 0f 84 c8 00 00 00 je 409cfd + 409c35: 4c 89 f7 mov %r14,%rdi + 409c38: e8 73 41 01 00 callq 41ddb0 <__cfree> + 409c3d: e9 60 ff ff ff jmpq 409ba2 + 409c42: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 409c48: 48 8b 04 24 mov (%rsp),%rax + 409c4c: 48 8b 78 18 mov 0x18(%rax),%rdi + 409c50: e8 bb bf ff ff callq 405c10 <__gettext_free_exp> + 409c55: 48 8b 04 24 mov (%rsp),%rax + 409c59: 48 8b 40 10 mov 0x10(%rax),%rax + 409c5d: 48 85 c0 test %rax,%rax + 409c60: 74 25 je 409c87 + 409c62: 8b 10 mov (%rax),%edx + 409c64: 83 fa 02 cmp $0x2,%edx + 409c67: 0f 84 93 22 00 00 je 40bf00 + 409c6d: 83 fa 03 cmp $0x3,%edx + 409c70: 0f 84 77 22 00 00 je 40beed + 409c76: 83 fa 01 cmp $0x1,%edx + 409c79: 0f 84 94 22 00 00 je 40bf13 + 409c7f: 48 89 c7 mov %rax,%rdi + 409c82: e8 29 41 01 00 callq 41ddb0 <__cfree> + 409c87: 48 8b 04 24 mov (%rsp),%rax + 409c8b: 48 8b 40 08 mov 0x8(%rax),%rax + 409c8f: 48 85 c0 test %rax,%rax + 409c92: 74 25 je 409cb9 + 409c94: 8b 10 mov (%rax),%edx + 409c96: 83 fa 02 cmp $0x2,%edx + 409c99: 0f 84 6c 19 00 00 je 40b60b + 409c9f: 83 fa 03 cmp $0x3,%edx + 409ca2: 0f 84 50 19 00 00 je 40b5f8 + 409ca8: 83 fa 01 cmp $0x1,%edx + 409cab: 0f 84 6d 19 00 00 je 40b61e + 409cb1: 48 89 c7 mov %rax,%rdi + 409cb4: e8 f7 40 01 00 callq 41ddb0 <__cfree> + 409cb9: 48 8b 3c 24 mov (%rsp),%rdi + 409cbd: e8 ee 40 01 00 callq 41ddb0 <__cfree> + 409cc2: 49 8b 47 08 mov 0x8(%r15),%rax + 409cc6: 48 85 c0 test %rax,%rax + 409cc9: 48 89 04 24 mov %rax,(%rsp) + 409ccd: 74 26 je 409cf5 + 409ccf: 8b 00 mov (%rax),%eax + 409cd1: 83 f8 02 cmp $0x2,%eax + 409cd4: 0f 84 98 10 00 00 je 40ad72 + 409cda: 83 f8 03 cmp $0x3,%eax + 409cdd: 0f 84 5d 10 00 00 je 40ad40 + 409ce3: 83 f8 01 cmp $0x1,%eax + 409ce6: 0f 84 b8 10 00 00 je 40ada4 + 409cec: 48 8b 3c 24 mov (%rsp),%rdi + 409cf0: e8 bb 40 01 00 callq 41ddb0 <__cfree> + 409cf5: 4c 89 ff mov %r15,%rdi + 409cf8: e8 b3 40 01 00 callq 41ddb0 <__cfree> + 409cfd: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 409d01: 4d 85 ff test %r15,%r15 + 409d04: 0f 84 2b ff ff ff je 409c35 + 409d0a: 41 8b 07 mov (%r15),%eax + 409d0d: 83 f8 02 cmp $0x2,%eax + 409d10: 0f 84 45 02 00 00 je 409f5b + 409d16: 83 f8 03 cmp $0x3,%eax + 409d19: 0f 84 09 02 00 00 je 409f28 + 409d1f: 83 f8 01 cmp $0x1,%eax + 409d22: 0f 84 66 02 00 00 je 409f8e + 409d28: 4c 89 ff mov %r15,%rdi + 409d2b: e8 80 40 01 00 callq 41ddb0 <__cfree> + 409d30: e9 00 ff ff ff jmpq 409c35 + 409d35: 0f 1f 00 nopl (%rax) + 409d38: 49 8b 7f 18 mov 0x18(%r15),%rdi + 409d3c: e8 cf be ff ff callq 405c10 <__gettext_free_exp> + 409d41: 49 8b 47 10 mov 0x10(%r15),%rax + 409d45: 48 85 c0 test %rax,%rax + 409d48: 74 25 je 409d6f + 409d4a: 8b 10 mov (%rax),%edx + 409d4c: 83 fa 02 cmp $0x2,%edx + 409d4f: 0f 84 63 22 00 00 je 40bfb8 + 409d55: 83 fa 03 cmp $0x3,%edx + 409d58: 0f 84 49 22 00 00 je 40bfa7 + 409d5e: 83 fa 01 cmp $0x1,%edx + 409d61: 0f 84 62 22 00 00 je 40bfc9 + 409d67: 48 89 c7 mov %rax,%rdi + 409d6a: e8 41 40 01 00 callq 41ddb0 <__cfree> + 409d6f: 49 8b 47 08 mov 0x8(%r15),%rax + 409d73: 48 85 c0 test %rax,%rax + 409d76: 48 89 04 24 mov %rax,(%rsp) + 409d7a: 74 26 je 409da2 + 409d7c: 8b 00 mov (%rax),%eax + 409d7e: 83 f8 02 cmp $0x2,%eax + 409d81: 0f 84 64 1b 00 00 je 40b8eb + 409d87: 83 f8 03 cmp $0x3,%eax + 409d8a: 0f 84 4e 1b 00 00 je 40b8de + 409d90: 83 f8 01 cmp $0x1,%eax + 409d93: 0f 84 84 1b 00 00 je 40b91d + 409d99: 48 8b 3c 24 mov (%rsp),%rdi + 409d9d: e8 0e 40 01 00 callq 41ddb0 <__cfree> + 409da2: 4c 89 ff mov %r15,%rdi + 409da5: e8 06 40 01 00 callq 41ddb0 <__cfree> + 409daa: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 409dae: 4d 85 ff test %r15,%r15 + 409db1: 74 26 je 409dd9 + 409db3: 41 8b 07 mov (%r15),%eax + 409db6: 83 f8 02 cmp $0x2,%eax + 409db9: 0f 84 cf 12 00 00 je 40b08e + 409dbf: 83 f8 03 cmp $0x3,%eax + 409dc2: 0f 84 98 12 00 00 je 40b060 + 409dc8: 83 f8 01 cmp $0x1,%eax + 409dcb: 0f 84 f0 12 00 00 je 40b0c1 + 409dd1: 4c 89 ff mov %r15,%rdi + 409dd4: e8 d7 3f 01 00 callq 41ddb0 <__cfree> + 409dd9: 4c 89 f7 mov %r14,%rdi + 409ddc: e8 cf 3f 01 00 callq 41ddb0 <__cfree> + 409de1: 4d 8b 75 08 mov 0x8(%r13),%r14 + 409de5: 4d 85 f6 test %r14,%r14 + 409de8: 0f 84 90 fd ff ff je 409b7e + 409dee: 41 8b 06 mov (%r14),%eax + 409df1: 83 f8 02 cmp $0x2,%eax + 409df4: 0f 84 c5 04 00 00 je 40a2bf + 409dfa: 83 f8 03 cmp $0x3,%eax + 409dfd: 0f 84 8d 04 00 00 je 40a290 + 409e03: 83 f8 01 cmp $0x1,%eax + 409e06: 0f 84 e2 04 00 00 je 40a2ee + 409e0c: 4c 89 f7 mov %r14,%rdi + 409e0f: e8 9c 3f 01 00 callq 41ddb0 <__cfree> + 409e14: e9 65 fd ff ff jmpq 409b7e + 409e19: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 409e20: 4c 8b 6b 18 mov 0x18(%rbx),%r13 + 409e24: 4d 85 ed test %r13,%r13 + 409e27: 0f 84 29 fd ff ff je 409b56 + 409e2d: 41 8b 45 00 mov 0x0(%r13),%eax + 409e31: 83 f8 02 cmp $0x2,%eax + 409e34: 0f 84 15 07 00 00 je 40a54f + 409e3a: 83 f8 03 cmp $0x3,%eax + 409e3d: 0f 84 dd 06 00 00 je 40a520 + 409e43: 83 f8 01 cmp $0x1,%eax + 409e46: 0f 84 96 00 00 00 je 409ee2 + 409e4c: 4c 89 ef mov %r13,%rdi + 409e4f: e8 5c 3f 01 00 callq 41ddb0 <__cfree> + 409e54: e9 fd fc ff ff jmpq 409b56 + 409e59: 49 8b 7f 18 mov 0x18(%r15),%rdi + 409e5d: e8 ae bd ff ff callq 405c10 <__gettext_free_exp> + 409e62: 49 8b 7f 10 mov 0x10(%r15),%rdi + 409e66: e8 a5 bd ff ff callq 405c10 <__gettext_free_exp> + 409e6b: 49 8b 7f 08 mov 0x8(%r15),%rdi + 409e6f: e8 9c bd ff ff callq 405c10 <__gettext_free_exp> + 409e74: 4c 89 ff mov %r15,%rdi + 409e77: e8 34 3f 01 00 callq 41ddb0 <__cfree> + 409e7c: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 409e80: 4d 85 ff test %r15,%r15 + 409e83: 74 26 je 409eab + 409e85: 41 8b 07 mov (%r15),%eax + 409e88: 83 f8 02 cmp $0x2,%eax + 409e8b: 0f 84 19 1f 00 00 je 40bdaa + 409e91: 83 f8 03 cmp $0x3,%eax + 409e94: 0f 84 07 1f 00 00 je 40bda1 + 409e9a: 83 f8 01 cmp $0x1,%eax + 409e9d: 0f 84 10 1f 00 00 je 40bdb3 + 409ea3: 4c 89 ff mov %r15,%rdi + 409ea6: e8 05 3f 01 00 callq 41ddb0 <__cfree> + 409eab: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 409eaf: 4d 85 ff test %r15,%r15 + 409eb2: 74 26 je 409eda + 409eb4: 41 8b 07 mov (%r15),%eax + 409eb7: 83 f8 02 cmp $0x2,%eax + 409eba: 0f 84 16 15 00 00 je 40b3d6 + 409ec0: 83 f8 03 cmp $0x3,%eax + 409ec3: 0f 84 04 15 00 00 je 40b3cd + 409ec9: 83 f8 01 cmp $0x1,%eax + 409ecc: 0f 84 32 15 00 00 je 40b404 + 409ed2: 4c 89 ff mov %r15,%rdi + 409ed5: e8 d6 3e 01 00 callq 41ddb0 <__cfree> + 409eda: 4c 89 f7 mov %r14,%rdi + 409edd: e8 ce 3e 01 00 callq 41ddb0 <__cfree> + 409ee2: 4d 8b 75 08 mov 0x8(%r13),%r14 + 409ee6: 4d 85 f6 test %r14,%r14 + 409ee9: 0f 84 5d ff ff ff je 409e4c + 409eef: 41 8b 06 mov (%r14),%eax + 409ef2: 83 f8 02 cmp $0x2,%eax + 409ef5: 0f 84 54 09 00 00 je 40a84f + 409efb: 83 f8 03 cmp $0x3,%eax + 409efe: 0f 84 1c 09 00 00 je 40a820 + 409f04: 83 f8 01 cmp $0x1,%eax + 409f07: 0f 84 71 09 00 00 je 40a87e + 409f0d: 4c 89 f7 mov %r14,%rdi + 409f10: e8 9b 3e 01 00 callq 41ddb0 <__cfree> + 409f15: 4c 89 ef mov %r13,%rdi + 409f18: e8 93 3e 01 00 callq 41ddb0 <__cfree> + 409f1d: e9 34 fc ff ff jmpq 409b56 + 409f22: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 409f28: 49 8b 47 18 mov 0x18(%r15),%rax + 409f2c: 48 85 c0 test %rax,%rax + 409f2f: 48 89 04 24 mov %rax,(%rsp) + 409f33: 74 26 je 409f5b + 409f35: 8b 00 mov (%rax),%eax + 409f37: 83 f8 02 cmp $0x2,%eax + 409f3a: 0f 84 44 12 00 00 je 40b184 + 409f40: 83 f8 03 cmp $0x3,%eax + 409f43: 0f 84 2e 12 00 00 je 40b177 + 409f49: 83 f8 01 cmp $0x1,%eax + 409f4c: 0f 84 64 12 00 00 je 40b1b6 + 409f52: 48 8b 3c 24 mov (%rsp),%rdi + 409f56: e8 55 3e 01 00 callq 41ddb0 <__cfree> + 409f5b: 49 8b 47 10 mov 0x10(%r15),%rax + 409f5f: 48 85 c0 test %rax,%rax + 409f62: 48 89 04 24 mov %rax,(%rsp) + 409f66: 74 26 je 409f8e + 409f68: 8b 00 mov (%rax),%eax + 409f6a: 83 f8 02 cmp $0x2,%eax + 409f6d: 0f 84 3f 0c 00 00 je 40abb2 + 409f73: 83 f8 03 cmp $0x3,%eax + 409f76: 0f 84 04 0c 00 00 je 40ab80 + 409f7c: 83 f8 01 cmp $0x1,%eax + 409f7f: 0f 84 5f 0c 00 00 je 40abe4 + 409f85: 48 8b 3c 24 mov (%rsp),%rdi + 409f89: e8 22 3e 01 00 callq 41ddb0 <__cfree> + 409f8e: 49 8b 47 08 mov 0x8(%r15),%rax + 409f92: 48 85 c0 test %rax,%rax + 409f95: 0f 84 8d fd ff ff je 409d28 + 409f9b: 8b 10 mov (%rax),%edx + 409f9d: 83 fa 02 cmp $0x2,%edx + 409fa0: 0f 84 78 06 00 00 je 40a61e + 409fa6: 83 fa 03 cmp $0x3,%edx + 409fa9: 0f 84 39 06 00 00 je 40a5e8 + 409faf: 83 fa 01 cmp $0x1,%edx + 409fb2: 74 75 je 40a029 + 409fb4: 48 89 c7 mov %rax,%rdi + 409fb7: e8 f4 3d 01 00 callq 41ddb0 <__cfree> + 409fbc: e9 67 fd ff ff jmpq 409d28 + 409fc1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 409fc8: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 409fcc: 48 89 44 24 08 mov %rax,0x8(%rsp) + 409fd1: 48 89 14 24 mov %rdx,(%rsp) + 409fd5: e8 36 bc ff ff callq 405c10 <__gettext_free_exp> + 409fda: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 409fdf: 48 8b 14 24 mov (%rsp),%rdx + 409fe3: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 409fe7: 48 89 44 24 08 mov %rax,0x8(%rsp) + 409fec: 48 89 14 24 mov %rdx,(%rsp) + 409ff0: e8 1b bc ff ff callq 405c10 <__gettext_free_exp> + 409ff5: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 409ffa: 48 8b 14 24 mov (%rsp),%rdx + 409ffe: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 40a002: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40a007: 48 89 14 24 mov %rdx,(%rsp) + 40a00b: e8 00 bc ff ff callq 405c10 <__gettext_free_exp> + 40a010: 48 8b 14 24 mov (%rsp),%rdx + 40a014: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40a019: 48 89 d7 mov %rdx,%rdi + 40a01c: 48 89 04 24 mov %rax,(%rsp) + 40a020: e8 8b 3d 01 00 callq 41ddb0 <__cfree> + 40a025: 48 8b 04 24 mov (%rsp),%rax + 40a029: 48 8b 78 08 mov 0x8(%rax),%rdi + 40a02d: 48 89 04 24 mov %rax,(%rsp) + 40a031: e8 da bb ff ff callq 405c10 <__gettext_free_exp> + 40a036: 48 8b 04 24 mov (%rsp),%rax + 40a03a: 48 89 c7 mov %rax,%rdi + 40a03d: e8 6e 3d 01 00 callq 41ddb0 <__cfree> + 40a042: e9 e1 fc ff ff jmpq 409d28 + 40a047: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 40a04e: 00 00 + 40a050: 4d 8b 7e 18 mov 0x18(%r14),%r15 + 40a054: 4d 85 ff test %r15,%r15 + 40a057: 74 26 je 40a07f + 40a059: 41 8b 07 mov (%r15),%eax + 40a05c: 83 f8 02 cmp $0x2,%eax + 40a05f: 0f 84 29 15 00 00 je 40b58e + 40a065: 83 f8 03 cmp $0x3,%eax + 40a068: 0f 84 17 15 00 00 je 40b585 + 40a06e: 83 f8 01 cmp $0x1,%eax + 40a071: 0f 84 45 15 00 00 je 40b5bc + 40a077: 4c 89 ff mov %r15,%rdi + 40a07a: e8 31 3d 01 00 callq 41ddb0 <__cfree> + 40a07f: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 40a083: 4d 85 ff test %r15,%r15 + 40a086: 74 26 je 40a0ae + 40a088: 41 8b 07 mov (%r15),%eax + 40a08b: 83 f8 02 cmp $0x2,%eax + 40a08e: 0f 84 ba 0d 00 00 je 40ae4e + 40a094: 83 f8 03 cmp $0x3,%eax + 40a097: 0f 84 83 0d 00 00 je 40ae20 + 40a09d: 83 f8 01 cmp $0x1,%eax + 40a0a0: 0f 84 db 0d 00 00 je 40ae81 + 40a0a6: 4c 89 ff mov %r15,%rdi + 40a0a9: e8 02 3d 01 00 callq 41ddb0 <__cfree> + 40a0ae: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 40a0b2: 4d 85 ff test %r15,%r15 + 40a0b5: 0f 84 4b fb ff ff je 409c06 + 40a0bb: 41 8b 07 mov (%r15),%eax + 40a0be: 83 f8 02 cmp $0x2,%eax + 40a0c1: 0f 84 a7 06 00 00 je 40a76e + 40a0c7: 83 f8 03 cmp $0x3,%eax + 40a0ca: 0f 84 70 06 00 00 je 40a740 + 40a0d0: 83 f8 01 cmp $0x1,%eax + 40a0d3: 0f 84 91 00 00 00 je 40a16a + 40a0d9: 4c 89 ff mov %r15,%rdi + 40a0dc: e8 cf 3c 01 00 callq 41ddb0 <__cfree> + 40a0e1: e9 20 fb ff ff jmpq 409c06 + 40a0e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 40a0ed: 00 00 00 + 40a0f0: 48 8b 04 24 mov (%rsp),%rax + 40a0f4: 48 8b 78 18 mov 0x18(%rax),%rdi + 40a0f8: e8 13 bb ff ff callq 405c10 <__gettext_free_exp> + 40a0fd: 48 8b 04 24 mov (%rsp),%rax + 40a101: 48 8b 40 10 mov 0x10(%rax),%rax + 40a105: 48 85 c0 test %rax,%rax + 40a108: 74 25 je 40a12f + 40a10a: 8b 10 mov (%rax),%edx + 40a10c: 83 fa 02 cmp $0x2,%edx + 40a10f: 0f 84 6f 1d 00 00 je 40be84 + 40a115: 83 fa 03 cmp $0x3,%edx + 40a118: 0f 84 53 1d 00 00 je 40be71 + 40a11e: 83 fa 01 cmp $0x1,%edx + 40a121: 0f 84 70 1d 00 00 je 40be97 + 40a127: 48 89 c7 mov %rax,%rdi + 40a12a: e8 81 3c 01 00 callq 41ddb0 <__cfree> + 40a12f: 48 8b 04 24 mov (%rsp),%rax + 40a133: 48 8b 40 08 mov 0x8(%rax),%rax + 40a137: 48 85 c0 test %rax,%rax + 40a13a: 74 25 je 40a161 + 40a13c: 8b 10 mov (%rax),%edx + 40a13e: 83 fa 02 cmp $0x2,%edx + 40a141: 0f 84 76 16 00 00 je 40b7bd + 40a147: 83 fa 03 cmp $0x3,%edx + 40a14a: 0f 84 5a 16 00 00 je 40b7aa + 40a150: 83 fa 01 cmp $0x1,%edx + 40a153: 0f 84 77 16 00 00 je 40b7d0 + 40a159: 48 89 c7 mov %rax,%rdi + 40a15c: e8 4f 3c 01 00 callq 41ddb0 <__cfree> + 40a161: 48 8b 3c 24 mov (%rsp),%rdi + 40a165: e8 46 3c 01 00 callq 41ddb0 <__cfree> + 40a16a: 49 8b 47 08 mov 0x8(%r15),%rax + 40a16e: 48 85 c0 test %rax,%rax + 40a171: 48 89 04 24 mov %rax,(%rsp) + 40a175: 0f 84 5e ff ff ff je 40a0d9 + 40a17b: 8b 00 mov (%rax),%eax + 40a17d: 83 f8 02 cmp $0x2,%eax + 40a180: 0f 84 4c 09 00 00 je 40aad2 + 40a186: 83 f8 03 cmp $0x3,%eax + 40a189: 0f 84 11 09 00 00 je 40aaa0 + 40a18f: 83 f8 01 cmp $0x1,%eax + 40a192: 0f 84 6c 09 00 00 je 40ab04 + 40a198: 48 8b 3c 24 mov (%rsp),%rdi + 40a19c: e8 0f 3c 01 00 callq 41ddb0 <__cfree> + 40a1a1: 4c 89 ff mov %r15,%rdi + 40a1a4: e8 07 3c 01 00 callq 41ddb0 <__cfree> + 40a1a9: e9 58 fa ff ff jmpq 409c06 + 40a1ae: 48 8b 78 18 mov 0x18(%rax),%rdi + 40a1b2: 48 89 04 24 mov %rax,(%rsp) + 40a1b6: e8 55 ba ff ff callq 405c10 <__gettext_free_exp> + 40a1bb: 48 8b 04 24 mov (%rsp),%rax + 40a1bf: 48 8b 78 10 mov 0x10(%rax),%rdi + 40a1c3: 48 89 04 24 mov %rax,(%rsp) + 40a1c7: e8 44 ba ff ff callq 405c10 <__gettext_free_exp> + 40a1cc: 48 8b 04 24 mov (%rsp),%rax + 40a1d0: 48 8b 78 08 mov 0x8(%rax),%rdi + 40a1d4: 48 89 04 24 mov %rax,(%rsp) + 40a1d8: e8 33 ba ff ff callq 405c10 <__gettext_free_exp> + 40a1dd: 48 8b 04 24 mov (%rsp),%rax + 40a1e1: 48 89 c7 mov %rax,%rdi + 40a1e4: e8 c7 3b 01 00 callq 41ddb0 <__cfree> + 40a1e9: 49 8b 47 10 mov 0x10(%r15),%rax + 40a1ed: 48 85 c0 test %rax,%rax + 40a1f0: 74 25 je 40a217 + 40a1f2: 8b 10 mov (%rax),%edx + 40a1f4: 83 fa 02 cmp $0x2,%edx + 40a1f7: 0f 84 26 19 00 00 je 40bb23 + 40a1fd: 83 fa 03 cmp $0x3,%edx + 40a200: 0f 84 0c 19 00 00 je 40bb12 + 40a206: 83 fa 01 cmp $0x1,%edx + 40a209: 0f 84 25 19 00 00 je 40bb34 + 40a20f: 48 89 c7 mov %rax,%rdi + 40a212: e8 99 3b 01 00 callq 41ddb0 <__cfree> + 40a217: 49 8b 47 08 mov 0x8(%r15),%rax + 40a21b: 48 85 c0 test %rax,%rax + 40a21e: 48 89 04 24 mov %rax,(%rsp) + 40a222: 74 26 je 40a24a + 40a224: 8b 00 mov (%rax),%eax + 40a226: 83 f8 02 cmp $0x2,%eax + 40a229: 0f 84 cf 0f 00 00 je 40b1fe + 40a22f: 83 f8 03 cmp $0x3,%eax + 40a232: 0f 84 b9 0f 00 00 je 40b1f1 + 40a238: 83 f8 01 cmp $0x1,%eax + 40a23b: 0f 84 ef 0f 00 00 je 40b230 + 40a241: 48 8b 3c 24 mov (%rsp),%rdi + 40a245: e8 66 3b 01 00 callq 41ddb0 <__cfree> + 40a24a: 4c 89 ff mov %r15,%rdi + 40a24d: e8 5e 3b 01 00 callq 41ddb0 <__cfree> + 40a252: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 40a256: 4d 85 ff test %r15,%r15 + 40a259: 0f 84 9e fa ff ff je 409cfd + 40a25f: 41 8b 07 mov (%r15),%eax + 40a262: 83 f8 02 cmp $0x2,%eax + 40a265: 0f 84 23 04 00 00 je 40a68e + 40a26b: 83 f8 03 cmp $0x3,%eax + 40a26e: 0f 84 ec 03 00 00 je 40a660 + 40a274: 83 f8 01 cmp $0x1,%eax + 40a277: 0f 84 45 fa ff ff je 409cc2 + 40a27d: 4c 89 ff mov %r15,%rdi + 40a280: e8 2b 3b 01 00 callq 41ddb0 <__cfree> + 40a285: e9 73 fa ff ff jmpq 409cfd + 40a28a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 40a290: 4d 8b 7e 18 mov 0x18(%r14),%r15 + 40a294: 4d 85 ff test %r15,%r15 + 40a297: 74 26 je 40a2bf + 40a299: 41 8b 07 mov (%r15),%eax + 40a29c: 83 f8 02 cmp $0x2,%eax + 40a29f: 0f 84 0d 12 00 00 je 40b4b2 + 40a2a5: 83 f8 03 cmp $0x3,%eax + 40a2a8: 0f 84 fb 11 00 00 je 40b4a9 + 40a2ae: 83 f8 01 cmp $0x1,%eax + 40a2b1: 0f 84 29 12 00 00 je 40b4e0 + 40a2b7: 4c 89 ff mov %r15,%rdi + 40a2ba: e8 f1 3a 01 00 callq 41ddb0 <__cfree> + 40a2bf: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 40a2c3: 4d 85 ff test %r15,%r15 + 40a2c6: 74 26 je 40a2ee + 40a2c8: 41 8b 07 mov (%r15),%eax + 40a2cb: 83 f8 02 cmp $0x2,%eax + 40a2ce: 0f 84 9a 0c 00 00 je 40af6e + 40a2d4: 83 f8 03 cmp $0x3,%eax + 40a2d7: 0f 84 63 0c 00 00 je 40af40 + 40a2dd: 83 f8 01 cmp $0x1,%eax + 40a2e0: 0f 84 bb 0c 00 00 je 40afa1 + 40a2e6: 4c 89 ff mov %r15,%rdi + 40a2e9: e8 c2 3a 01 00 callq 41ddb0 <__cfree> + 40a2ee: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 40a2f2: 4d 85 ff test %r15,%r15 + 40a2f5: 0f 84 11 fb ff ff je 409e0c + 40a2fb: 41 8b 07 mov (%r15),%eax + 40a2fe: 83 f8 02 cmp $0x2,%eax + 40a301: 0f 84 f7 03 00 00 je 40a6fe + 40a307: 83 f8 03 cmp $0x3,%eax + 40a30a: 0f 84 c0 03 00 00 je 40a6d0 + 40a310: 83 f8 01 cmp $0x1,%eax + 40a313: 0f 84 bb 00 00 00 je 40a3d4 + 40a319: 4c 89 ff mov %r15,%rdi + 40a31c: e8 8f 3a 01 00 callq 41ddb0 <__cfree> + 40a321: e9 e6 fa ff ff jmpq 409e0c + 40a326: 48 8b 78 18 mov 0x18(%rax),%rdi + 40a32a: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40a32f: e8 dc b8 ff ff callq 405c10 <__gettext_free_exp> + 40a334: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40a339: 48 8b 78 10 mov 0x10(%rax),%rdi + 40a33d: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40a342: e8 c9 b8 ff ff callq 405c10 <__gettext_free_exp> + 40a347: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40a34c: 48 8b 78 08 mov 0x8(%rax),%rdi + 40a350: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40a355: e8 b6 b8 ff ff callq 405c10 <__gettext_free_exp> + 40a35a: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40a35f: 48 89 c7 mov %rax,%rdi + 40a362: e8 49 3a 01 00 callq 41ddb0 <__cfree> + 40a367: 48 8b 04 24 mov (%rsp),%rax + 40a36b: 48 8b 40 10 mov 0x10(%rax),%rax + 40a36f: 48 85 c0 test %rax,%rax + 40a372: 74 25 je 40a399 + 40a374: 8b 10 mov (%rax),%edx + 40a376: 83 fa 02 cmp $0x2,%edx + 40a379: 0f 84 c7 1a 00 00 je 40be46 + 40a37f: 83 fa 03 cmp $0x3,%edx + 40a382: 0f 84 ab 1a 00 00 je 40be33 + 40a388: 83 fa 01 cmp $0x1,%edx + 40a38b: 0f 84 c8 1a 00 00 je 40be59 + 40a391: 48 89 c7 mov %rax,%rdi + 40a394: e8 17 3a 01 00 callq 41ddb0 <__cfree> + 40a399: 48 8b 04 24 mov (%rsp),%rax + 40a39d: 48 8b 40 08 mov 0x8(%rax),%rax + 40a3a1: 48 85 c0 test %rax,%rax + 40a3a4: 74 25 je 40a3cb + 40a3a6: 8b 10 mov (%rax),%edx + 40a3a8: 83 fa 02 cmp $0x2,%edx + 40a3ab: 0f 84 4a 14 00 00 je 40b7fb + 40a3b1: 83 fa 03 cmp $0x3,%edx + 40a3b4: 0f 84 2e 14 00 00 je 40b7e8 + 40a3ba: 83 fa 01 cmp $0x1,%edx + 40a3bd: 0f 84 4b 14 00 00 je 40b80e + 40a3c3: 48 89 c7 mov %rax,%rdi + 40a3c6: e8 e5 39 01 00 callq 41ddb0 <__cfree> + 40a3cb: 48 8b 3c 24 mov (%rsp),%rdi + 40a3cf: e8 dc 39 01 00 callq 41ddb0 <__cfree> + 40a3d4: 49 8b 47 08 mov 0x8(%r15),%rax + 40a3d8: 48 85 c0 test %rax,%rax + 40a3db: 48 89 04 24 mov %rax,(%rsp) + 40a3df: 0f 84 34 ff ff ff je 40a319 + 40a3e5: 8b 00 mov (%rax),%eax + 40a3e7: 83 f8 02 cmp $0x2,%eax + 40a3ea: 0f 84 a2 08 00 00 je 40ac92 + 40a3f0: 83 f8 03 cmp $0x3,%eax + 40a3f3: 0f 84 67 08 00 00 je 40ac60 + 40a3f9: 83 f8 01 cmp $0x1,%eax + 40a3fc: 0f 84 c2 08 00 00 je 40acc4 + 40a402: 48 8b 3c 24 mov (%rsp),%rdi + 40a406: e8 a5 39 01 00 callq 41ddb0 <__cfree> + 40a40b: 4c 89 ff mov %r15,%rdi + 40a40e: e8 9d 39 01 00 callq 41ddb0 <__cfree> + 40a413: e9 f4 f9 ff ff jmpq 409e0c + 40a418: 49 8b 7f 18 mov 0x18(%r15),%rdi + 40a41c: e8 ef b7 ff ff callq 405c10 <__gettext_free_exp> + 40a421: 49 8b 7f 10 mov 0x10(%r15),%rdi + 40a425: e8 e6 b7 ff ff callq 405c10 <__gettext_free_exp> + 40a42a: 49 8b 7f 08 mov 0x8(%r15),%rdi + 40a42e: e8 dd b7 ff ff callq 405c10 <__gettext_free_exp> + 40a433: 4c 89 ff mov %r15,%rdi + 40a436: e8 75 39 01 00 callq 41ddb0 <__cfree> + 40a43b: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 40a43f: 4d 85 ff test %r15,%r15 + 40a442: 74 26 je 40a46a + 40a444: 41 8b 07 mov (%r15),%eax + 40a447: 83 f8 02 cmp $0x2,%eax + 40a44a: 0f 84 11 19 00 00 je 40bd61 + 40a450: 83 f8 03 cmp $0x3,%eax + 40a453: 0f 84 ff 18 00 00 je 40bd58 + 40a459: 83 f8 01 cmp $0x1,%eax + 40a45c: 0f 84 08 19 00 00 je 40bd6a + 40a462: 4c 89 ff mov %r15,%rdi + 40a465: e8 46 39 01 00 callq 41ddb0 <__cfree> + 40a46a: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 40a46e: 4d 85 ff test %r15,%r15 + 40a471: 74 26 je 40a499 + 40a473: 41 8b 07 mov (%r15),%eax + 40a476: 83 f8 02 cmp $0x2,%eax + 40a479: 0f 84 c5 0f 00 00 je 40b444 + 40a47f: 83 f8 03 cmp $0x3,%eax + 40a482: 0f 84 b3 0f 00 00 je 40b43b + 40a488: 83 f8 01 cmp $0x1,%eax + 40a48b: 0f 84 e1 0f 00 00 je 40b472 + 40a491: 4c 89 ff mov %r15,%rdi + 40a494: e8 17 39 01 00 callq 41ddb0 <__cfree> + 40a499: 4c 89 f7 mov %r14,%rdi + 40a49c: e8 0f 39 01 00 callq 41ddb0 <__cfree> + 40a4a1: 4d 8b 75 10 mov 0x10(%r13),%r14 + 40a4a5: 4d 85 f6 test %r14,%r14 + 40a4a8: 0f 84 33 f9 ff ff je 409de1 + 40a4ae: 41 8b 06 mov (%r14),%eax + 40a4b1: 83 f8 02 cmp $0x2,%eax + 40a4b4: 0f 84 25 03 00 00 je 40a7df + 40a4ba: 83 f8 03 cmp $0x3,%eax + 40a4bd: 0f 84 ed 02 00 00 je 40a7b0 + 40a4c3: 83 f8 01 cmp $0x1,%eax + 40a4c6: 0f 84 de f8 ff ff je 409daa + 40a4cc: 4c 89 f7 mov %r14,%rdi + 40a4cf: e8 dc 38 01 00 callq 41ddb0 <__cfree> + 40a4d4: e9 08 f9 ff ff jmpq 409de1 + 40a4d9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 40a4e0: 4d 8b 7e 18 mov 0x18(%r14),%r15 + 40a4e4: 4d 85 ff test %r15,%r15 + 40a4e7: 0f 84 65 fd ff ff je 40a252 + 40a4ed: 41 8b 07 mov (%r15),%eax + 40a4f0: 83 f8 02 cmp $0x2,%eax + 40a4f3: 0f 84 f0 fc ff ff je 40a1e9 + 40a4f9: 83 f8 03 cmp $0x3,%eax + 40a4fc: 0f 84 7e 21 00 00 je 40c680 + 40a502: 83 f8 01 cmp $0x1,%eax + 40a505: 0f 84 0c fd ff ff je 40a217 + 40a50b: 4c 89 ff mov %r15,%rdi + 40a50e: e8 9d 38 01 00 callq 41ddb0 <__cfree> + 40a513: e9 3a fd ff ff jmpq 40a252 + 40a518: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 40a51f: 00 + 40a520: 4d 8b 75 18 mov 0x18(%r13),%r14 + 40a524: 4d 85 f6 test %r14,%r14 + 40a527: 74 26 je 40a54f + 40a529: 41 8b 06 mov (%r14),%eax + 40a52c: 83 f8 02 cmp $0x2,%eax + 40a52f: 0f 84 20 15 00 00 je 40ba55 + 40a535: 83 f8 03 cmp $0x3,%eax + 40a538: 0f 84 0e 15 00 00 je 40ba4c + 40a53e: 83 f8 01 cmp $0x1,%eax + 40a541: 0f 84 3d 15 00 00 je 40ba84 + 40a547: 4c 89 f7 mov %r14,%rdi + 40a54a: e8 61 38 01 00 callq 41ddb0 <__cfree> + 40a54f: 4d 8b 75 10 mov 0x10(%r13),%r14 + 40a553: 4d 85 f6 test %r14,%r14 + 40a556: 0f 84 86 f9 ff ff je 409ee2 + 40a55c: 41 8b 06 mov (%r14),%eax + 40a55f: 83 f8 02 cmp $0x2,%eax + 40a562: 0f 84 14 f9 ff ff je 409e7c + 40a568: 83 f8 03 cmp $0x3,%eax + 40a56b: 0f 84 8f 22 00 00 je 40c800 + 40a571: 83 f8 01 cmp $0x1,%eax + 40a574: 0f 84 31 f9 ff ff je 409eab + 40a57a: 4c 89 f7 mov %r14,%rdi + 40a57d: e8 2e 38 01 00 callq 41ddb0 <__cfree> + 40a582: e9 5b f9 ff ff jmpq 409ee2 + 40a587: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 40a58e: 00 00 + 40a590: 4d 8b 75 18 mov 0x18(%r13),%r14 + 40a594: 4d 85 f6 test %r14,%r14 + 40a597: 0f 84 04 ff ff ff je 40a4a1 + 40a59d: 41 8b 06 mov (%r14),%eax + 40a5a0: 83 f8 02 cmp $0x2,%eax + 40a5a3: 0f 84 92 fe ff ff je 40a43b + 40a5a9: 83 f8 03 cmp $0x3,%eax + 40a5ac: 0f 84 16 22 00 00 je 40c7c8 + 40a5b2: 83 f8 01 cmp $0x1,%eax + 40a5b5: 0f 84 af fe ff ff je 40a46a + 40a5bb: 4c 89 f7 mov %r14,%rdi + 40a5be: e8 ed 37 01 00 callq 41ddb0 <__cfree> + 40a5c3: e9 d9 fe ff ff jmpq 40a4a1 + 40a5c8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 40a5cf: 00 + 40a5d0: 31 c0 xor %eax,%eax + 40a5d2: 48 83 c4 18 add $0x18,%rsp + 40a5d6: 5b pop %rbx + 40a5d7: 5d pop %rbp + 40a5d8: 41 5c pop %r12 + 40a5da: 41 5d pop %r13 + 40a5dc: 41 5e pop %r14 + 40a5de: 41 5f pop %r15 + 40a5e0: c3 retq + 40a5e1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 40a5e8: 48 8b 50 18 mov 0x18(%rax),%rdx + 40a5ec: 48 85 d2 test %rdx,%rdx + 40a5ef: 74 2d je 40a61e + 40a5f1: 8b 0a mov (%rdx),%ecx + 40a5f3: 83 f9 02 cmp $0x2,%ecx + 40a5f6: 0f 84 db 14 00 00 je 40bad7 + 40a5fc: 83 f9 03 cmp $0x3,%ecx + 40a5ff: 0f 84 b7 14 00 00 je 40babc + 40a605: 83 f9 01 cmp $0x1,%ecx + 40a608: 0f 84 e4 14 00 00 je 40baf2 + 40a60e: 48 89 d7 mov %rdx,%rdi + 40a611: 48 89 04 24 mov %rax,(%rsp) + 40a615: e8 96 37 01 00 callq 41ddb0 <__cfree> + 40a61a: 48 8b 04 24 mov (%rsp),%rax + 40a61e: 48 8b 50 10 mov 0x10(%rax),%rdx + 40a622: 48 85 d2 test %rdx,%rdx + 40a625: 0f 84 fe f9 ff ff je 40a029 + 40a62b: 8b 0a mov (%rdx),%ecx + 40a62d: 83 f9 02 cmp $0x2,%ecx + 40a630: 0f 84 ad f9 ff ff je 409fe3 + 40a636: 83 f9 03 cmp $0x3,%ecx + 40a639: 0f 84 89 f9 ff ff je 409fc8 + 40a63f: 83 f9 01 cmp $0x1,%ecx + 40a642: 0f 84 b6 f9 ff ff je 409ffe + 40a648: 48 89 d7 mov %rdx,%rdi + 40a64b: 48 89 04 24 mov %rax,(%rsp) + 40a64f: e8 5c 37 01 00 callq 41ddb0 <__cfree> + 40a654: 48 8b 04 24 mov (%rsp),%rax + 40a658: e9 cc f9 ff ff jmpq 40a029 + 40a65d: 0f 1f 00 nopl (%rax) + 40a660: 49 8b 47 18 mov 0x18(%r15),%rax + 40a664: 48 85 c0 test %rax,%rax + 40a667: 74 25 je 40a68e + 40a669: 8b 10 mov (%rax),%edx + 40a66b: 83 fa 02 cmp $0x2,%edx + 40a66e: 0f 84 10 15 00 00 je 40bb84 + 40a674: 83 fa 03 cmp $0x3,%edx + 40a677: 0f 84 f6 14 00 00 je 40bb73 + 40a67d: 83 fa 01 cmp $0x1,%edx + 40a680: 0f 84 0f 15 00 00 je 40bb95 + 40a686: 48 89 c7 mov %rax,%rdi + 40a689: e8 22 37 01 00 callq 41ddb0 <__cfree> + 40a68e: 49 8b 47 10 mov 0x10(%r15),%rax + 40a692: 48 85 c0 test %rax,%rax + 40a695: 48 89 04 24 mov %rax,(%rsp) + 40a699: 0f 84 23 f6 ff ff je 409cc2 + 40a69f: 8b 00 mov (%rax),%eax + 40a6a1: 83 f8 02 cmp $0x2,%eax + 40a6a4: 0f 84 ab f5 ff ff je 409c55 + 40a6aa: 83 f8 03 cmp $0x3,%eax + 40a6ad: 0f 84 95 f5 ff ff je 409c48 + 40a6b3: 83 f8 01 cmp $0x1,%eax + 40a6b6: 0f 84 cb f5 ff ff je 409c87 + 40a6bc: 48 8b 3c 24 mov (%rsp),%rdi + 40a6c0: e8 eb 36 01 00 callq 41ddb0 <__cfree> + 40a6c5: e9 f8 f5 ff ff jmpq 409cc2 + 40a6ca: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 40a6d0: 49 8b 47 18 mov 0x18(%r15),%rax + 40a6d4: 48 85 c0 test %rax,%rax + 40a6d7: 74 25 je 40a6fe + 40a6d9: 8b 10 mov (%rax),%edx + 40a6db: 83 fa 02 cmp $0x2,%edx + 40a6de: 0f 84 24 16 00 00 je 40bd08 + 40a6e4: 83 fa 03 cmp $0x3,%edx + 40a6e7: 0f 84 0a 16 00 00 je 40bcf7 + 40a6ed: 83 fa 01 cmp $0x1,%edx + 40a6f0: 0f 84 23 16 00 00 je 40bd19 + 40a6f6: 48 89 c7 mov %rax,%rdi + 40a6f9: e8 b2 36 01 00 callq 41ddb0 <__cfree> + 40a6fe: 49 8b 47 10 mov 0x10(%r15),%rax + 40a702: 48 85 c0 test %rax,%rax + 40a705: 48 89 04 24 mov %rax,(%rsp) + 40a709: 0f 84 c5 fc ff ff je 40a3d4 + 40a70f: 8b 00 mov (%rax),%eax + 40a711: 83 f8 02 cmp $0x2,%eax + 40a714: 0f 84 4d fc ff ff je 40a367 + 40a71a: 83 f8 03 cmp $0x3,%eax + 40a71d: 0f 84 ed 28 00 00 je 40d010 + 40a723: 83 f8 01 cmp $0x1,%eax + 40a726: 0f 84 6d fc ff ff je 40a399 + 40a72c: 48 8b 3c 24 mov (%rsp),%rdi + 40a730: e8 7b 36 01 00 callq 41ddb0 <__cfree> + 40a735: e9 9a fc ff ff jmpq 40a3d4 + 40a73a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 40a740: 49 8b 47 18 mov 0x18(%r15),%rax + 40a744: 48 85 c0 test %rax,%rax + 40a747: 74 25 je 40a76e + 40a749: 8b 10 mov (%rax),%edx + 40a74b: 83 fa 02 cmp $0x2,%edx + 40a74e: 0f 84 53 15 00 00 je 40bca7 + 40a754: 83 fa 03 cmp $0x3,%edx + 40a757: 0f 84 39 15 00 00 je 40bc96 + 40a75d: 83 fa 01 cmp $0x1,%edx + 40a760: 0f 84 52 15 00 00 je 40bcb8 + 40a766: 48 89 c7 mov %rax,%rdi + 40a769: e8 42 36 01 00 callq 41ddb0 <__cfree> + 40a76e: 49 8b 47 10 mov 0x10(%r15),%rax + 40a772: 48 85 c0 test %rax,%rax + 40a775: 48 89 04 24 mov %rax,(%rsp) + 40a779: 0f 84 eb f9 ff ff je 40a16a + 40a77f: 8b 00 mov (%rax),%eax + 40a781: 83 f8 02 cmp $0x2,%eax + 40a784: 0f 84 73 f9 ff ff je 40a0fd + 40a78a: 83 f8 03 cmp $0x3,%eax + 40a78d: 0f 84 5d f9 ff ff je 40a0f0 + 40a793: 83 f8 01 cmp $0x1,%eax + 40a796: 0f 84 93 f9 ff ff je 40a12f + 40a79c: 48 8b 3c 24 mov (%rsp),%rdi + 40a7a0: e8 0b 36 01 00 callq 41ddb0 <__cfree> + 40a7a5: e9 c0 f9 ff ff jmpq 40a16a + 40a7aa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 40a7b0: 4d 8b 7e 18 mov 0x18(%r14),%r15 + 40a7b4: 4d 85 ff test %r15,%r15 + 40a7b7: 74 26 je 40a7df + 40a7b9: 41 8b 07 mov (%r15),%eax + 40a7bc: 83 f8 02 cmp $0x2,%eax + 40a7bf: 0f 84 2e 16 00 00 je 40bdf3 + 40a7c5: 83 f8 03 cmp $0x3,%eax + 40a7c8: 0f 84 1c 16 00 00 je 40bdea + 40a7ce: 83 f8 01 cmp $0x1,%eax + 40a7d1: 0f 84 25 16 00 00 je 40bdfc + 40a7d7: 4c 89 ff mov %r15,%rdi + 40a7da: e8 d1 35 01 00 callq 41ddb0 <__cfree> + 40a7df: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 40a7e3: 4d 85 ff test %r15,%r15 + 40a7e6: 0f 84 be f5 ff ff je 409daa + 40a7ec: 41 8b 07 mov (%r15),%eax + 40a7ef: 83 f8 02 cmp $0x2,%eax + 40a7f2: 0f 84 49 f5 ff ff je 409d41 + 40a7f8: 83 f8 03 cmp $0x3,%eax + 40a7fb: 0f 84 37 f5 ff ff je 409d38 + 40a801: 83 f8 01 cmp $0x1,%eax + 40a804: 0f 84 65 f5 ff ff je 409d6f + 40a80a: 4c 89 ff mov %r15,%rdi + 40a80d: e8 9e 35 01 00 callq 41ddb0 <__cfree> + 40a812: e9 93 f5 ff ff jmpq 409daa + 40a817: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 40a81e: 00 00 + 40a820: 4d 8b 7e 18 mov 0x18(%r14),%r15 + 40a824: 4d 85 ff test %r15,%r15 + 40a827: 74 26 je 40a84f + 40a829: 41 8b 07 mov (%r15),%eax + 40a82c: 83 f8 02 cmp $0x2,%eax + 40a82f: 0f 84 ab 1d 00 00 je 40c5e0 + 40a835: 83 f8 03 cmp $0x3,%eax + 40a838: 0f 84 99 1d 00 00 je 40c5d7 + 40a83e: 83 f8 01 cmp $0x1,%eax + 40a841: 0f 84 a2 1d 00 00 je 40c5e9 + 40a847: 4c 89 ff mov %r15,%rdi + 40a84a: e8 61 35 01 00 callq 41ddb0 <__cfree> + 40a84f: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 40a853: 4d 85 ff test %r15,%r15 + 40a856: 74 26 je 40a87e + 40a858: 41 8b 07 mov (%r15),%eax + 40a85b: 83 f8 02 cmp $0x2,%eax + 40a85e: 0f 84 bc 0c 00 00 je 40b520 + 40a864: 83 f8 03 cmp $0x3,%eax + 40a867: 0f 84 aa 0c 00 00 je 40b517 + 40a86d: 83 f8 01 cmp $0x1,%eax + 40a870: 0f 84 d8 0c 00 00 je 40b54e + 40a876: 4c 89 ff mov %r15,%rdi + 40a879: e8 32 35 01 00 callq 41ddb0 <__cfree> + 40a87e: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 40a882: 4d 85 ff test %r15,%r15 + 40a885: 0f 84 82 f6 ff ff je 409f0d + 40a88b: 41 8b 07 mov (%r15),%eax + 40a88e: 83 f8 02 cmp $0x2,%eax + 40a891: 74 56 je 40a8e9 + 40a893: 83 f8 03 cmp $0x3,%eax + 40a896: 0f 84 b4 1d 00 00 je 40c650 + 40a89c: 83 f8 01 cmp $0x1,%eax + 40a89f: 74 76 je 40a917 + 40a8a1: 4c 89 ff mov %r15,%rdi + 40a8a4: e8 07 35 01 00 callq 41ddb0 <__cfree> + 40a8a9: e9 5f f6 ff ff jmpq 409f0d + 40a8ae: 48 8b 78 18 mov 0x18(%rax),%rdi + 40a8b2: 48 89 04 24 mov %rax,(%rsp) + 40a8b6: e8 55 b3 ff ff callq 405c10 <__gettext_free_exp> + 40a8bb: 48 8b 04 24 mov (%rsp),%rax + 40a8bf: 48 8b 78 10 mov 0x10(%rax),%rdi + 40a8c3: 48 89 04 24 mov %rax,(%rsp) + 40a8c7: e8 44 b3 ff ff callq 405c10 <__gettext_free_exp> + 40a8cc: 48 8b 04 24 mov (%rsp),%rax + 40a8d0: 48 8b 78 08 mov 0x8(%rax),%rdi + 40a8d4: 48 89 04 24 mov %rax,(%rsp) + 40a8d8: e8 33 b3 ff ff callq 405c10 <__gettext_free_exp> + 40a8dd: 48 8b 04 24 mov (%rsp),%rax + 40a8e1: 48 89 c7 mov %rax,%rdi + 40a8e4: e8 c7 34 01 00 callq 41ddb0 <__cfree> + 40a8e9: 49 8b 47 10 mov 0x10(%r15),%rax + 40a8ed: 48 85 c0 test %rax,%rax + 40a8f0: 74 25 je 40a917 + 40a8f2: 8b 10 mov (%rax),%edx + 40a8f4: 83 fa 02 cmp $0x2,%edx + 40a8f7: 0f 84 e8 12 00 00 je 40bbe5 + 40a8fd: 83 fa 03 cmp $0x3,%edx + 40a900: 0f 84 ce 12 00 00 je 40bbd4 + 40a906: 83 fa 01 cmp $0x1,%edx + 40a909: 0f 84 e7 12 00 00 je 40bbf6 + 40a90f: 48 89 c7 mov %rax,%rdi + 40a912: e8 99 34 01 00 callq 41ddb0 <__cfree> + 40a917: 49 8b 47 08 mov 0x8(%r15),%rax + 40a91b: 48 85 c0 test %rax,%rax + 40a91e: 48 89 04 24 mov %rax,(%rsp) + 40a922: 0f 84 79 ff ff ff je 40a8a1 + 40a928: 8b 00 mov (%rax),%eax + 40a92a: 83 f8 02 cmp $0x2,%eax + 40a92d: 0f 84 bf 09 00 00 je 40b2f2 + 40a933: 83 f8 03 cmp $0x3,%eax + 40a936: 0f 84 a9 09 00 00 je 40b2e5 + 40a93c: 83 f8 01 cmp $0x1,%eax + 40a93f: 0f 84 df 09 00 00 je 40b324 + 40a945: 48 8b 3c 24 mov (%rsp),%rdi + 40a949: e8 62 34 01 00 callq 41ddb0 <__cfree> + 40a94e: 4c 89 ff mov %r15,%rdi + 40a951: e8 5a 34 01 00 callq 41ddb0 <__cfree> + 40a956: e9 b2 f5 ff ff jmpq 409f0d + 40a95b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 40a960: 4d 8b 7e 18 mov 0x18(%r14),%r15 + 40a964: 4d 85 ff test %r15,%r15 + 40a967: 74 26 je 40a98f + 40a969: 41 8b 07 mov (%r15),%eax + 40a96c: 83 f8 02 cmp $0x2,%eax + 40a96f: 0f 84 73 1d 00 00 je 40c6e8 + 40a975: 83 f8 03 cmp $0x3,%eax + 40a978: 0f 84 61 1d 00 00 je 40c6df + 40a97e: 83 f8 01 cmp $0x1,%eax + 40a981: 0f 84 6a 1d 00 00 je 40c6f1 + 40a987: 4c 89 ff mov %r15,%rdi + 40a98a: e8 21 34 01 00 callq 41ddb0 <__cfree> + 40a98f: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 40a993: 4d 85 ff test %r15,%r15 + 40a996: 74 26 je 40a9be + 40a998: 41 8b 07 mov (%r15),%eax + 40a99b: 83 f8 02 cmp $0x2,%eax + 40a99e: 0f 84 c4 09 00 00 je 40b368 + 40a9a4: 83 f8 03 cmp $0x3,%eax + 40a9a7: 0f 84 b2 09 00 00 je 40b35f + 40a9ad: 83 f8 01 cmp $0x1,%eax + 40a9b0: 0f 84 e0 09 00 00 je 40b396 + 40a9b6: 4c 89 ff mov %r15,%rdi + 40a9b9: e8 f2 33 01 00 callq 41ddb0 <__cfree> + 40a9be: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 40a9c2: 4d 85 ff test %r15,%r15 + 40a9c5: 0f 84 0c f2 ff ff je 409bd7 + 40a9cb: 41 8b 07 mov (%r15),%eax + 40a9ce: 83 f8 02 cmp $0x2,%eax + 40a9d1: 74 56 je 40aa29 + 40a9d3: 83 f8 03 cmp $0x3,%eax + 40a9d6: 0f 84 d4 1c 00 00 je 40c6b0 + 40a9dc: 83 f8 01 cmp $0x1,%eax + 40a9df: 74 76 je 40aa57 + 40a9e1: 4c 89 ff mov %r15,%rdi + 40a9e4: e8 c7 33 01 00 callq 41ddb0 <__cfree> + 40a9e9: e9 e9 f1 ff ff jmpq 409bd7 + 40a9ee: 48 8b 78 18 mov 0x18(%rax),%rdi + 40a9f2: 48 89 04 24 mov %rax,(%rsp) + 40a9f6: e8 15 b2 ff ff callq 405c10 <__gettext_free_exp> + 40a9fb: 48 8b 04 24 mov (%rsp),%rax + 40a9ff: 48 8b 78 10 mov 0x10(%rax),%rdi + 40aa03: 48 89 04 24 mov %rax,(%rsp) + 40aa07: e8 04 b2 ff ff callq 405c10 <__gettext_free_exp> + 40aa0c: 48 8b 04 24 mov (%rsp),%rax + 40aa10: 48 8b 78 08 mov 0x8(%rax),%rdi + 40aa14: 48 89 04 24 mov %rax,(%rsp) + 40aa18: e8 f3 b1 ff ff callq 405c10 <__gettext_free_exp> + 40aa1d: 48 8b 04 24 mov (%rsp),%rax + 40aa21: 48 89 c7 mov %rax,%rdi + 40aa24: e8 87 33 01 00 callq 41ddb0 <__cfree> + 40aa29: 49 8b 47 10 mov 0x10(%r15),%rax + 40aa2d: 48 85 c0 test %rax,%rax + 40aa30: 74 25 je 40aa57 + 40aa32: 8b 10 mov (%rax),%edx + 40aa34: 83 fa 02 cmp $0x2,%edx + 40aa37: 0f 84 09 12 00 00 je 40bc46 + 40aa3d: 83 fa 03 cmp $0x3,%edx + 40aa40: 0f 84 ef 11 00 00 je 40bc35 + 40aa46: 83 fa 01 cmp $0x1,%edx + 40aa49: 0f 84 08 12 00 00 je 40bc57 + 40aa4f: 48 89 c7 mov %rax,%rdi + 40aa52: e8 59 33 01 00 callq 41ddb0 <__cfree> + 40aa57: 49 8b 47 08 mov 0x8(%r15),%rax + 40aa5b: 48 85 c0 test %rax,%rax + 40aa5e: 48 89 04 24 mov %rax,(%rsp) + 40aa62: 0f 84 79 ff ff ff je 40a9e1 + 40aa68: 8b 00 mov (%rax),%eax + 40aa6a: 83 f8 02 cmp $0x2,%eax + 40aa6d: 0f 84 05 08 00 00 je 40b278 + 40aa73: 83 f8 03 cmp $0x3,%eax + 40aa76: 0f 84 ef 07 00 00 je 40b26b + 40aa7c: 83 f8 01 cmp $0x1,%eax + 40aa7f: 0f 84 25 08 00 00 je 40b2aa + 40aa85: 48 8b 3c 24 mov (%rsp),%rdi + 40aa89: e8 22 33 01 00 callq 41ddb0 <__cfree> + 40aa8e: 4c 89 ff mov %r15,%rdi + 40aa91: e8 1a 33 01 00 callq 41ddb0 <__cfree> + 40aa96: e9 3c f1 ff ff jmpq 409bd7 + 40aa9b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 40aaa0: 48 8b 04 24 mov (%rsp),%rax + 40aaa4: 48 8b 40 18 mov 0x18(%rax),%rax + 40aaa8: 48 85 c0 test %rax,%rax + 40aaab: 74 25 je 40aad2 + 40aaad: 8b 10 mov (%rax),%edx + 40aaaf: 83 fa 02 cmp $0x2,%edx + 40aab2: 0f 84 81 22 00 00 je 40cd39 + 40aab8: 83 fa 03 cmp $0x3,%edx + 40aabb: 0f 84 65 22 00 00 je 40cd26 + 40aac1: 83 fa 01 cmp $0x1,%edx + 40aac4: 0f 84 82 22 00 00 je 40cd4c + 40aaca: 48 89 c7 mov %rax,%rdi + 40aacd: e8 de 32 01 00 callq 41ddb0 <__cfree> + 40aad2: 48 8b 04 24 mov (%rsp),%rax + 40aad6: 48 8b 40 10 mov 0x10(%rax),%rax + 40aada: 48 85 c0 test %rax,%rax + 40aadd: 74 25 je 40ab04 + 40aadf: 8b 10 mov (%rax),%edx + 40aae1: 83 fa 02 cmp $0x2,%edx + 40aae4: 0f 84 4f 0d 00 00 je 40b839 + 40aaea: 83 fa 03 cmp $0x3,%edx + 40aaed: 0f 84 33 0d 00 00 je 40b826 + 40aaf3: 83 fa 01 cmp $0x1,%edx + 40aaf6: 0f 84 50 0d 00 00 je 40b84c + 40aafc: 48 89 c7 mov %rax,%rdi + 40aaff: e8 ac 32 01 00 callq 41ddb0 <__cfree> + 40ab04: 48 8b 04 24 mov (%rsp),%rax + 40ab08: 48 8b 40 08 mov 0x8(%rax),%rax + 40ab0c: 48 85 c0 test %rax,%rax + 40ab0f: 0f 84 83 f6 ff ff je 40a198 + 40ab15: 8b 10 mov (%rax),%edx + 40ab17: 83 fa 02 cmp $0x2,%edx + 40ab1a: 74 2f je 40ab4b + 40ab1c: 83 fa 03 cmp $0x3,%edx + 40ab1f: 74 17 je 40ab38 + 40ab21: 83 fa 01 cmp $0x1,%edx + 40ab24: 74 38 je 40ab5e + 40ab26: 48 89 c7 mov %rax,%rdi + 40ab29: e8 82 32 01 00 callq 41ddb0 <__cfree> + 40ab2e: e9 65 f6 ff ff jmpq 40a198 + 40ab33: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 40ab38: 48 8b 78 18 mov 0x18(%rax),%rdi + 40ab3c: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40ab41: e8 ca b0 ff ff callq 405c10 <__gettext_free_exp> + 40ab46: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40ab4b: 48 8b 78 10 mov 0x10(%rax),%rdi + 40ab4f: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40ab54: e8 b7 b0 ff ff callq 405c10 <__gettext_free_exp> + 40ab59: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40ab5e: 48 8b 78 08 mov 0x8(%rax),%rdi + 40ab62: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40ab67: e8 a4 b0 ff ff callq 405c10 <__gettext_free_exp> + 40ab6c: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40ab71: 48 89 c7 mov %rax,%rdi + 40ab74: e8 37 32 01 00 callq 41ddb0 <__cfree> + 40ab79: e9 1a f6 ff ff jmpq 40a198 + 40ab7e: 66 90 xchg %ax,%ax + 40ab80: 48 8b 04 24 mov (%rsp),%rax + 40ab84: 48 8b 40 18 mov 0x18(%rax),%rax + 40ab88: 48 85 c0 test %rax,%rax + 40ab8b: 74 25 je 40abb2 + 40ab8d: 8b 10 mov (%rax),%edx + 40ab8f: 83 fa 02 cmp $0x2,%edx + 40ab92: 0f 84 39 1f 00 00 je 40cad1 + 40ab98: 83 fa 03 cmp $0x3,%edx + 40ab9b: 0f 84 1d 1f 00 00 je 40cabe + 40aba1: 83 fa 01 cmp $0x1,%edx + 40aba4: 0f 84 3a 1f 00 00 je 40cae4 + 40abaa: 48 89 c7 mov %rax,%rdi + 40abad: e8 fe 31 01 00 callq 41ddb0 <__cfree> + 40abb2: 48 8b 04 24 mov (%rsp),%rax + 40abb6: 48 8b 40 10 mov 0x10(%rax),%rax + 40abba: 48 85 c0 test %rax,%rax + 40abbd: 74 25 je 40abe4 + 40abbf: 8b 10 mov (%rax),%edx + 40abc1: 83 fa 02 cmp $0x2,%edx + 40abc4: 0f 84 b5 0b 00 00 je 40b77f + 40abca: 83 fa 03 cmp $0x3,%edx + 40abcd: 0f 84 99 0b 00 00 je 40b76c + 40abd3: 83 fa 01 cmp $0x1,%edx + 40abd6: 0f 84 b6 0b 00 00 je 40b792 + 40abdc: 48 89 c7 mov %rax,%rdi + 40abdf: e8 cc 31 01 00 callq 41ddb0 <__cfree> + 40abe4: 48 8b 04 24 mov (%rsp),%rax + 40abe8: 48 8b 40 08 mov 0x8(%rax),%rax + 40abec: 48 85 c0 test %rax,%rax + 40abef: 0f 84 90 f3 ff ff je 409f85 + 40abf5: 8b 10 mov (%rax),%edx + 40abf7: 83 fa 02 cmp $0x2,%edx + 40abfa: 74 2f je 40ac2b + 40abfc: 83 fa 03 cmp $0x3,%edx + 40abff: 74 17 je 40ac18 + 40ac01: 83 fa 01 cmp $0x1,%edx + 40ac04: 74 38 je 40ac3e + 40ac06: 48 89 c7 mov %rax,%rdi + 40ac09: e8 a2 31 01 00 callq 41ddb0 <__cfree> + 40ac0e: e9 72 f3 ff ff jmpq 409f85 + 40ac13: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 40ac18: 48 8b 78 18 mov 0x18(%rax),%rdi + 40ac1c: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40ac21: e8 ea af ff ff callq 405c10 <__gettext_free_exp> + 40ac26: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40ac2b: 48 8b 78 10 mov 0x10(%rax),%rdi + 40ac2f: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40ac34: e8 d7 af ff ff callq 405c10 <__gettext_free_exp> + 40ac39: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40ac3e: 48 8b 78 08 mov 0x8(%rax),%rdi + 40ac42: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40ac47: e8 c4 af ff ff callq 405c10 <__gettext_free_exp> + 40ac4c: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40ac51: 48 89 c7 mov %rax,%rdi + 40ac54: e8 57 31 01 00 callq 41ddb0 <__cfree> + 40ac59: e9 27 f3 ff ff jmpq 409f85 + 40ac5e: 66 90 xchg %ax,%ax + 40ac60: 48 8b 04 24 mov (%rsp),%rax + 40ac64: 48 8b 40 18 mov 0x18(%rax),%rax + 40ac68: 48 85 c0 test %rax,%rax + 40ac6b: 74 25 je 40ac92 + 40ac6d: 8b 10 mov (%rax),%edx + 40ac6f: 83 fa 02 cmp $0x2,%edx + 40ac72: 0f 84 1b 1e 00 00 je 40ca93 + 40ac78: 83 fa 03 cmp $0x3,%edx + 40ac7b: 0f 84 ff 1d 00 00 je 40ca80 + 40ac81: 83 fa 01 cmp $0x1,%edx + 40ac84: 0f 84 1c 1e 00 00 je 40caa6 + 40ac8a: 48 89 c7 mov %rax,%rdi + 40ac8d: e8 1e 31 01 00 callq 41ddb0 <__cfree> + 40ac92: 48 8b 04 24 mov (%rsp),%rax + 40ac96: 48 8b 40 10 mov 0x10(%rax),%rax + 40ac9a: 48 85 c0 test %rax,%rax + 40ac9d: 74 25 je 40acc4 + 40ac9f: 8b 10 mov (%rax),%edx + 40aca1: 83 fa 02 cmp $0x2,%edx + 40aca4: 0f 84 97 0a 00 00 je 40b741 + 40acaa: 83 fa 03 cmp $0x3,%edx + 40acad: 0f 84 7b 0a 00 00 je 40b72e + 40acb3: 83 fa 01 cmp $0x1,%edx + 40acb6: 0f 84 98 0a 00 00 je 40b754 + 40acbc: 48 89 c7 mov %rax,%rdi + 40acbf: e8 ec 30 01 00 callq 41ddb0 <__cfree> + 40acc4: 48 8b 04 24 mov (%rsp),%rax + 40acc8: 48 8b 40 08 mov 0x8(%rax),%rax + 40accc: 48 85 c0 test %rax,%rax + 40accf: 0f 84 2d f7 ff ff je 40a402 + 40acd5: 8b 10 mov (%rax),%edx + 40acd7: 83 fa 02 cmp $0x2,%edx + 40acda: 74 2f je 40ad0b + 40acdc: 83 fa 03 cmp $0x3,%edx + 40acdf: 74 17 je 40acf8 + 40ace1: 83 fa 01 cmp $0x1,%edx + 40ace4: 74 38 je 40ad1e + 40ace6: 48 89 c7 mov %rax,%rdi + 40ace9: e8 c2 30 01 00 callq 41ddb0 <__cfree> + 40acee: e9 0f f7 ff ff jmpq 40a402 + 40acf3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 40acf8: 48 8b 78 18 mov 0x18(%rax),%rdi + 40acfc: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40ad01: e8 0a af ff ff callq 405c10 <__gettext_free_exp> + 40ad06: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40ad0b: 48 8b 78 10 mov 0x10(%rax),%rdi + 40ad0f: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40ad14: e8 f7 ae ff ff callq 405c10 <__gettext_free_exp> + 40ad19: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40ad1e: 48 8b 78 08 mov 0x8(%rax),%rdi + 40ad22: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40ad27: e8 e4 ae ff ff callq 405c10 <__gettext_free_exp> + 40ad2c: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40ad31: 48 89 c7 mov %rax,%rdi + 40ad34: e8 77 30 01 00 callq 41ddb0 <__cfree> + 40ad39: e9 c4 f6 ff ff jmpq 40a402 + 40ad3e: 66 90 xchg %ax,%ax + 40ad40: 48 8b 04 24 mov (%rsp),%rax + 40ad44: 48 8b 40 18 mov 0x18(%rax),%rax + 40ad48: 48 85 c0 test %rax,%rax + 40ad4b: 74 25 je 40ad72 + 40ad4d: 8b 10 mov (%rax),%edx + 40ad4f: 83 fa 02 cmp $0x2,%edx + 40ad52: 0f 84 2b 1c 00 00 je 40c983 + 40ad58: 83 fa 03 cmp $0x3,%edx + 40ad5b: 0f 84 0f 1c 00 00 je 40c970 + 40ad61: 83 fa 01 cmp $0x1,%edx + 40ad64: 0f 84 2c 1c 00 00 je 40c996 + 40ad6a: 48 89 c7 mov %rax,%rdi + 40ad6d: e8 3e 30 01 00 callq 41ddb0 <__cfree> + 40ad72: 48 8b 04 24 mov (%rsp),%rax + 40ad76: 48 8b 40 10 mov 0x10(%rax),%rax + 40ad7a: 48 85 c0 test %rax,%rax + 40ad7d: 74 25 je 40ada4 + 40ad7f: 8b 10 mov (%rax),%edx + 40ad81: 83 fa 02 cmp $0x2,%edx + 40ad84: 0f 84 79 09 00 00 je 40b703 + 40ad8a: 83 fa 03 cmp $0x3,%edx + 40ad8d: 0f 84 5d 09 00 00 je 40b6f0 + 40ad93: 83 fa 01 cmp $0x1,%edx + 40ad96: 0f 84 7a 09 00 00 je 40b716 + 40ad9c: 48 89 c7 mov %rax,%rdi + 40ad9f: e8 0c 30 01 00 callq 41ddb0 <__cfree> + 40ada4: 48 8b 04 24 mov (%rsp),%rax + 40ada8: 48 8b 40 08 mov 0x8(%rax),%rax + 40adac: 48 85 c0 test %rax,%rax + 40adaf: 0f 84 37 ef ff ff je 409cec + 40adb5: 8b 10 mov (%rax),%edx + 40adb7: 83 fa 02 cmp $0x2,%edx + 40adba: 74 2f je 40adeb + 40adbc: 83 fa 03 cmp $0x3,%edx + 40adbf: 74 17 je 40add8 + 40adc1: 83 fa 01 cmp $0x1,%edx + 40adc4: 74 38 je 40adfe + 40adc6: 48 89 c7 mov %rax,%rdi + 40adc9: e8 e2 2f 01 00 callq 41ddb0 <__cfree> + 40adce: e9 19 ef ff ff jmpq 409cec + 40add3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 40add8: 48 8b 78 18 mov 0x18(%rax),%rdi + 40addc: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40ade1: e8 2a ae ff ff callq 405c10 <__gettext_free_exp> + 40ade6: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40adeb: 48 8b 78 10 mov 0x10(%rax),%rdi + 40adef: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40adf4: e8 17 ae ff ff callq 405c10 <__gettext_free_exp> + 40adf9: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40adfe: 48 8b 78 08 mov 0x8(%rax),%rdi + 40ae02: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40ae07: e8 04 ae ff ff callq 405c10 <__gettext_free_exp> + 40ae0c: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40ae11: 48 89 c7 mov %rax,%rdi + 40ae14: e8 97 2f 01 00 callq 41ddb0 <__cfree> + 40ae19: e9 ce ee ff ff jmpq 409cec + 40ae1e: 66 90 xchg %ax,%ax + 40ae20: 49 8b 47 18 mov 0x18(%r15),%rax + 40ae24: 48 85 c0 test %rax,%rax + 40ae27: 74 25 je 40ae4e + 40ae29: 8b 10 mov (%rax),%edx + 40ae2b: 83 fa 02 cmp $0x2,%edx + 40ae2e: 0f 84 20 22 00 00 je 40d054 + 40ae34: 83 fa 03 cmp $0x3,%edx + 40ae37: 0f 84 06 22 00 00 je 40d043 + 40ae3d: 83 fa 01 cmp $0x1,%edx + 40ae40: 0f 84 1f 22 00 00 je 40d065 + 40ae46: 48 89 c7 mov %rax,%rdi + 40ae49: e8 62 2f 01 00 callq 41ddb0 <__cfree> + 40ae4e: 49 8b 47 10 mov 0x10(%r15),%rax + 40ae52: 48 85 c0 test %rax,%rax + 40ae55: 48 89 04 24 mov %rax,(%rsp) + 40ae59: 74 26 je 40ae81 + 40ae5b: 8b 00 mov (%rax),%eax + 40ae5d: 83 f8 02 cmp $0x2,%eax + 40ae60: 0f 84 ff 0a 00 00 je 40b965 + 40ae66: 83 f8 03 cmp $0x3,%eax + 40ae69: 0f 84 e9 0a 00 00 je 40b958 + 40ae6f: 83 f8 01 cmp $0x1,%eax + 40ae72: 0f 84 1f 0b 00 00 je 40b997 + 40ae78: 48 8b 3c 24 mov (%rsp),%rdi + 40ae7c: e8 2f 2f 01 00 callq 41ddb0 <__cfree> + 40ae81: 49 8b 47 08 mov 0x8(%r15),%rax + 40ae85: 48 85 c0 test %rax,%rax + 40ae88: 48 89 04 24 mov %rax,(%rsp) + 40ae8c: 0f 84 14 f2 ff ff je 40a0a6 + 40ae92: 8b 00 mov (%rax),%eax + 40ae94: 83 f8 02 cmp $0x2,%eax + 40ae97: 74 2c je 40aec5 + 40ae99: 83 f8 03 cmp $0x3,%eax + 40ae9c: 74 1a je 40aeb8 + 40ae9e: 83 f8 01 cmp $0x1,%eax + 40aea1: 74 54 je 40aef7 + 40aea3: 48 8b 3c 24 mov (%rsp),%rdi + 40aea7: e8 04 2f 01 00 callq 41ddb0 <__cfree> + 40aeac: e9 f5 f1 ff ff jmpq 40a0a6 + 40aeb1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 40aeb8: 48 8b 04 24 mov (%rsp),%rax + 40aebc: 48 8b 78 18 mov 0x18(%rax),%rdi + 40aec0: e8 4b ad ff ff callq 405c10 <__gettext_free_exp> + 40aec5: 48 8b 04 24 mov (%rsp),%rax + 40aec9: 48 8b 40 10 mov 0x10(%rax),%rax + 40aecd: 48 85 c0 test %rax,%rax + 40aed0: 74 25 je 40aef7 + 40aed2: 8b 10 mov (%rax),%edx + 40aed4: 83 fa 02 cmp $0x2,%edx + 40aed7: 0f 84 e5 0f 00 00 je 40bec2 + 40aedd: 83 fa 03 cmp $0x3,%edx + 40aee0: 0f 84 c9 0f 00 00 je 40beaf + 40aee6: 83 fa 01 cmp $0x1,%edx + 40aee9: 0f 84 e6 0f 00 00 je 40bed5 + 40aeef: 48 89 c7 mov %rax,%rdi + 40aef2: e8 b9 2e 01 00 callq 41ddb0 <__cfree> + 40aef7: 48 8b 04 24 mov (%rsp),%rax + 40aefb: 48 8b 40 08 mov 0x8(%rax),%rax + 40aeff: 48 85 c0 test %rax,%rax + 40af02: 74 9f je 40aea3 + 40af04: 8b 10 mov (%rax),%edx + 40af06: 83 fa 02 cmp $0x2,%edx + 40af09: 0f 84 3a 07 00 00 je 40b649 + 40af0f: 83 fa 03 cmp $0x3,%edx + 40af12: 0f 84 1e 07 00 00 je 40b636 + 40af18: 83 fa 01 cmp $0x1,%edx + 40af1b: 0f 84 3b 07 00 00 je 40b65c + 40af21: 48 89 c7 mov %rax,%rdi + 40af24: e8 87 2e 01 00 callq 41ddb0 <__cfree> + 40af29: 48 8b 3c 24 mov (%rsp),%rdi + 40af2d: e8 7e 2e 01 00 callq 41ddb0 <__cfree> + 40af32: e9 6f f1 ff ff jmpq 40a0a6 + 40af37: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 40af3e: 00 00 + 40af40: 49 8b 47 18 mov 0x18(%r15),%rax + 40af44: 48 85 c0 test %rax,%rax + 40af47: 74 25 je 40af6e + 40af49: 8b 10 mov (%rax),%edx + 40af4b: 83 fa 02 cmp $0x2,%edx + 40af4e: 0f 84 a8 21 00 00 je 40d0fc + 40af54: 83 fa 03 cmp $0x3,%edx + 40af57: 0f 84 8e 21 00 00 je 40d0eb + 40af5d: 83 fa 01 cmp $0x1,%edx + 40af60: 0f 84 a7 21 00 00 je 40d10d + 40af66: 48 89 c7 mov %rax,%rdi + 40af69: e8 42 2e 01 00 callq 41ddb0 <__cfree> + 40af6e: 49 8b 47 10 mov 0x10(%r15),%rax + 40af72: 48 85 c0 test %rax,%rax + 40af75: 48 89 04 24 mov %rax,(%rsp) + 40af79: 74 26 je 40afa1 + 40af7b: 8b 00 mov (%rax),%eax + 40af7d: 83 f8 02 cmp $0x2,%eax + 40af80: 0f 84 eb 08 00 00 je 40b871 + 40af86: 83 f8 03 cmp $0x3,%eax + 40af89: 0f 84 d5 08 00 00 je 40b864 + 40af8f: 83 f8 01 cmp $0x1,%eax + 40af92: 0f 84 0b 09 00 00 je 40b8a3 + 40af98: 48 8b 3c 24 mov (%rsp),%rdi + 40af9c: e8 0f 2e 01 00 callq 41ddb0 <__cfree> + 40afa1: 49 8b 47 08 mov 0x8(%r15),%rax + 40afa5: 48 85 c0 test %rax,%rax + 40afa8: 48 89 04 24 mov %rax,(%rsp) + 40afac: 0f 84 34 f3 ff ff je 40a2e6 + 40afb2: 8b 00 mov (%rax),%eax + 40afb4: 83 f8 02 cmp $0x2,%eax + 40afb7: 74 2c je 40afe5 + 40afb9: 83 f8 03 cmp $0x3,%eax + 40afbc: 74 1a je 40afd8 + 40afbe: 83 f8 01 cmp $0x1,%eax + 40afc1: 74 54 je 40b017 + 40afc3: 48 8b 3c 24 mov (%rsp),%rdi + 40afc7: e8 e4 2d 01 00 callq 41ddb0 <__cfree> + 40afcc: e9 15 f3 ff ff jmpq 40a2e6 + 40afd1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 40afd8: 48 8b 04 24 mov (%rsp),%rax + 40afdc: 48 8b 78 18 mov 0x18(%rax),%rdi + 40afe0: e8 2b ac ff ff callq 405c10 <__gettext_free_exp> + 40afe5: 48 8b 04 24 mov (%rsp),%rax + 40afe9: 48 8b 40 10 mov 0x10(%rax),%rax + 40afed: 48 85 c0 test %rax,%rax + 40aff0: 74 25 je 40b017 + 40aff2: 8b 10 mov (%rax),%edx + 40aff4: 83 fa 02 cmp $0x2,%edx + 40aff7: 0f 84 7f 0f 00 00 je 40bf7c + 40affd: 83 fa 03 cmp $0x3,%edx + 40b000: 0f 84 63 0f 00 00 je 40bf69 + 40b006: 83 fa 01 cmp $0x1,%edx + 40b009: 0f 84 80 0f 00 00 je 40bf8f + 40b00f: 48 89 c7 mov %rax,%rdi + 40b012: e8 99 2d 01 00 callq 41ddb0 <__cfree> + 40b017: 48 8b 04 24 mov (%rsp),%rax + 40b01b: 48 8b 40 08 mov 0x8(%rax),%rax + 40b01f: 48 85 c0 test %rax,%rax + 40b022: 74 9f je 40afc3 + 40b024: 8b 10 mov (%rax),%edx + 40b026: 83 fa 02 cmp $0x2,%edx + 40b029: 0f 84 96 06 00 00 je 40b6c5 + 40b02f: 83 fa 03 cmp $0x3,%edx + 40b032: 0f 84 7a 06 00 00 je 40b6b2 + 40b038: 83 fa 01 cmp $0x1,%edx + 40b03b: 0f 84 97 06 00 00 je 40b6d8 + 40b041: 48 89 c7 mov %rax,%rdi + 40b044: e8 67 2d 01 00 callq 41ddb0 <__cfree> + 40b049: 48 8b 3c 24 mov (%rsp),%rdi + 40b04d: e8 5e 2d 01 00 callq 41ddb0 <__cfree> + 40b052: e9 8f f2 ff ff jmpq 40a2e6 + 40b057: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 40b05e: 00 00 + 40b060: 49 8b 47 18 mov 0x18(%r15),%rax + 40b064: 48 85 c0 test %rax,%rax + 40b067: 74 25 je 40b08e + 40b069: 8b 10 mov (%rax),%edx + 40b06b: 83 fa 02 cmp $0x2,%edx + 40b06e: 0f 84 c5 1e 00 00 je 40cf39 + 40b074: 83 fa 03 cmp $0x3,%edx + 40b077: 0f 84 ab 1e 00 00 je 40cf28 + 40b07d: 83 fa 01 cmp $0x1,%edx + 40b080: 0f 84 c4 1e 00 00 je 40cf4a + 40b086: 48 89 c7 mov %rax,%rdi + 40b089: e8 22 2d 01 00 callq 41ddb0 <__cfree> + 40b08e: 49 8b 47 10 mov 0x10(%r15),%rax + 40b092: 48 85 c0 test %rax,%rax + 40b095: 48 89 04 24 mov %rax,(%rsp) + 40b099: 74 26 je 40b0c1 + 40b09b: 8b 00 mov (%rax),%eax + 40b09d: 83 f8 02 cmp $0x2,%eax + 40b0a0: 0f 84 39 09 00 00 je 40b9df + 40b0a6: 83 f8 03 cmp $0x3,%eax + 40b0a9: 0f 84 23 09 00 00 je 40b9d2 + 40b0af: 83 f8 01 cmp $0x1,%eax + 40b0b2: 0f 84 59 09 00 00 je 40ba11 + 40b0b8: 48 8b 3c 24 mov (%rsp),%rdi + 40b0bc: e8 ef 2c 01 00 callq 41ddb0 <__cfree> + 40b0c1: 49 8b 47 08 mov 0x8(%r15),%rax + 40b0c5: 48 85 c0 test %rax,%rax + 40b0c8: 48 89 04 24 mov %rax,(%rsp) + 40b0cc: 0f 84 ff ec ff ff je 409dd1 + 40b0d2: 8b 00 mov (%rax),%eax + 40b0d4: 83 f8 02 cmp $0x2,%eax + 40b0d7: 74 2c je 40b105 + 40b0d9: 83 f8 03 cmp $0x3,%eax + 40b0dc: 74 1a je 40b0f8 + 40b0de: 83 f8 01 cmp $0x1,%eax + 40b0e1: 74 54 je 40b137 + 40b0e3: 48 8b 3c 24 mov (%rsp),%rdi + 40b0e7: e8 c4 2c 01 00 callq 41ddb0 <__cfree> + 40b0ec: e9 e0 ec ff ff jmpq 409dd1 + 40b0f1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 40b0f8: 48 8b 04 24 mov (%rsp),%rax + 40b0fc: 48 8b 78 18 mov 0x18(%rax),%rdi + 40b100: e8 0b ab ff ff callq 405c10 <__gettext_free_exp> + 40b105: 48 8b 04 24 mov (%rsp),%rax + 40b109: 48 8b 40 10 mov 0x10(%rax),%rax + 40b10d: 48 85 c0 test %rax,%rax + 40b110: 74 25 je 40b137 + 40b112: 8b 10 mov (%rax),%edx + 40b114: 83 fa 02 cmp $0x2,%edx + 40b117: 0f 84 21 0e 00 00 je 40bf3e + 40b11d: 83 fa 03 cmp $0x3,%edx + 40b120: 0f 84 05 0e 00 00 je 40bf2b + 40b126: 83 fa 01 cmp $0x1,%edx + 40b129: 0f 84 22 0e 00 00 je 40bf51 + 40b12f: 48 89 c7 mov %rax,%rdi + 40b132: e8 79 2c 01 00 callq 41ddb0 <__cfree> + 40b137: 48 8b 04 24 mov (%rsp),%rax + 40b13b: 48 8b 40 08 mov 0x8(%rax),%rax + 40b13f: 48 85 c0 test %rax,%rax + 40b142: 74 9f je 40b0e3 + 40b144: 8b 10 mov (%rax),%edx + 40b146: 83 fa 02 cmp $0x2,%edx + 40b149: 0f 84 38 05 00 00 je 40b687 + 40b14f: 83 fa 03 cmp $0x3,%edx + 40b152: 0f 84 1c 05 00 00 je 40b674 + 40b158: 83 fa 01 cmp $0x1,%edx + 40b15b: 0f 84 39 05 00 00 je 40b69a + 40b161: 48 89 c7 mov %rax,%rdi + 40b164: e8 47 2c 01 00 callq 41ddb0 <__cfree> + 40b169: 48 8b 3c 24 mov (%rsp),%rdi + 40b16d: e8 3e 2c 01 00 callq 41ddb0 <__cfree> + 40b172: e9 5a ec ff ff jmpq 409dd1 + 40b177: 48 8b 04 24 mov (%rsp),%rax + 40b17b: 48 8b 78 18 mov 0x18(%rax),%rdi + 40b17f: e8 8c aa ff ff callq 405c10 <__gettext_free_exp> + 40b184: 48 8b 04 24 mov (%rsp),%rax + 40b188: 48 8b 40 10 mov 0x10(%rax),%rax + 40b18c: 48 85 c0 test %rax,%rax + 40b18f: 74 25 je 40b1b6 + 40b191: 8b 10 mov (%rax),%edx + 40b193: 83 fa 02 cmp $0x2,%edx + 40b196: 0f 84 b9 18 00 00 je 40ca55 + 40b19c: 83 fa 03 cmp $0x3,%edx + 40b19f: 0f 84 9d 18 00 00 je 40ca42 + 40b1a5: 83 fa 01 cmp $0x1,%edx + 40b1a8: 0f 84 ba 18 00 00 je 40ca68 + 40b1ae: 48 89 c7 mov %rax,%rdi + 40b1b1: e8 fa 2b 01 00 callq 41ddb0 <__cfree> + 40b1b6: 48 8b 04 24 mov (%rsp),%rax + 40b1ba: 48 8b 40 08 mov 0x8(%rax),%rax + 40b1be: 48 85 c0 test %rax,%rax + 40b1c1: 0f 84 8b ed ff ff je 409f52 + 40b1c7: 8b 10 mov (%rax),%edx + 40b1c9: 83 fa 02 cmp $0x2,%edx + 40b1cc: 0f 84 c7 0f 00 00 je 40c199 + 40b1d2: 83 fa 03 cmp $0x3,%edx + 40b1d5: 0f 84 ab 0f 00 00 je 40c186 + 40b1db: 83 fa 01 cmp $0x1,%edx + 40b1de: 0f 84 c8 0f 00 00 je 40c1ac + 40b1e4: 48 89 c7 mov %rax,%rdi + 40b1e7: e8 c4 2b 01 00 callq 41ddb0 <__cfree> + 40b1ec: e9 61 ed ff ff jmpq 409f52 + 40b1f1: 48 8b 04 24 mov (%rsp),%rax + 40b1f5: 48 8b 78 18 mov 0x18(%rax),%rdi + 40b1f9: e8 12 aa ff ff callq 405c10 <__gettext_free_exp> + 40b1fe: 48 8b 04 24 mov (%rsp),%rax + 40b202: 48 8b 40 10 mov 0x10(%rax),%rax + 40b206: 48 85 c0 test %rax,%rax + 40b209: 74 25 je 40b230 + 40b20b: 8b 10 mov (%rax),%edx + 40b20d: 83 fa 02 cmp $0x2,%edx + 40b210: 0f 84 2f 17 00 00 je 40c945 + 40b216: 83 fa 03 cmp $0x3,%edx + 40b219: 0f 84 13 17 00 00 je 40c932 + 40b21f: 83 fa 01 cmp $0x1,%edx + 40b222: 0f 84 30 17 00 00 je 40c958 + 40b228: 48 89 c7 mov %rax,%rdi + 40b22b: e8 80 2b 01 00 callq 41ddb0 <__cfree> + 40b230: 48 8b 04 24 mov (%rsp),%rax + 40b234: 48 8b 40 08 mov 0x8(%rax),%rax + 40b238: 48 85 c0 test %rax,%rax + 40b23b: 0f 84 00 f0 ff ff je 40a241 + 40b241: 8b 10 mov (%rax),%edx + 40b243: 83 fa 02 cmp $0x2,%edx + 40b246: 0f 84 c9 0f 00 00 je 40c215 + 40b24c: 83 fa 03 cmp $0x3,%edx + 40b24f: 0f 84 ad 0f 00 00 je 40c202 + 40b255: 83 fa 01 cmp $0x1,%edx + 40b258: 0f 84 ca 0f 00 00 je 40c228 + 40b25e: 48 89 c7 mov %rax,%rdi + 40b261: e8 4a 2b 01 00 callq 41ddb0 <__cfree> + 40b266: e9 d6 ef ff ff jmpq 40a241 + 40b26b: 48 8b 04 24 mov (%rsp),%rax + 40b26f: 48 8b 78 18 mov 0x18(%rax),%rdi + 40b273: e8 98 a9 ff ff callq 405c10 <__gettext_free_exp> + 40b278: 48 8b 04 24 mov (%rsp),%rax + 40b27c: 48 8b 40 10 mov 0x10(%rax),%rax + 40b280: 48 85 c0 test %rax,%rax + 40b283: 74 25 je 40b2aa + 40b285: 8b 10 mov (%rax),%edx + 40b287: 83 fa 02 cmp $0x2,%edx + 40b28a: 0f 84 d5 18 00 00 je 40cb65 + 40b290: 83 fa 03 cmp $0x3,%edx + 40b293: 0f 84 b9 18 00 00 je 40cb52 + 40b299: 83 fa 01 cmp $0x1,%edx + 40b29c: 0f 84 d6 18 00 00 je 40cb78 + 40b2a2: 48 89 c7 mov %rax,%rdi + 40b2a5: e8 06 2b 01 00 callq 41ddb0 <__cfree> + 40b2aa: 48 8b 04 24 mov (%rsp),%rax + 40b2ae: 48 8b 40 08 mov 0x8(%rax),%rax + 40b2b2: 48 85 c0 test %rax,%rax + 40b2b5: 0f 84 ca f7 ff ff je 40aa85 + 40b2bb: 8b 10 mov (%rax),%edx + 40b2bd: 83 fa 02 cmp $0x2,%edx + 40b2c0: 0f 84 8d 0f 00 00 je 40c253 + 40b2c6: 83 fa 03 cmp $0x3,%edx + 40b2c9: 0f 84 71 0f 00 00 je 40c240 + 40b2cf: 83 fa 01 cmp $0x1,%edx + 40b2d2: 0f 84 8e 0f 00 00 je 40c266 + 40b2d8: 48 89 c7 mov %rax,%rdi + 40b2db: e8 d0 2a 01 00 callq 41ddb0 <__cfree> + 40b2e0: e9 a0 f7 ff ff jmpq 40aa85 + 40b2e5: 48 8b 04 24 mov (%rsp),%rax + 40b2e9: 48 8b 78 18 mov 0x18(%rax),%rdi + 40b2ed: e8 1e a9 ff ff callq 405c10 <__gettext_free_exp> + 40b2f2: 48 8b 04 24 mov (%rsp),%rax + 40b2f6: 48 8b 40 10 mov 0x10(%rax),%rax + 40b2fa: 48 85 c0 test %rax,%rax + 40b2fd: 74 25 je 40b324 + 40b2ff: 8b 10 mov (%rax),%edx + 40b301: 83 fa 02 cmp $0x2,%edx + 40b304: 0f 84 99 18 00 00 je 40cba3 + 40b30a: 83 fa 03 cmp $0x3,%edx + 40b30d: 0f 84 7d 18 00 00 je 40cb90 + 40b313: 83 fa 01 cmp $0x1,%edx + 40b316: 0f 84 9a 18 00 00 je 40cbb6 + 40b31c: 48 89 c7 mov %rax,%rdi + 40b31f: e8 8c 2a 01 00 callq 41ddb0 <__cfree> + 40b324: 48 8b 04 24 mov (%rsp),%rax + 40b328: 48 8b 40 08 mov 0x8(%rax),%rax + 40b32c: 48 85 c0 test %rax,%rax + 40b32f: 0f 84 10 f6 ff ff je 40a945 + 40b335: 8b 10 mov (%rax),%edx + 40b337: 83 fa 02 cmp $0x2,%edx + 40b33a: 0f 84 97 0e 00 00 je 40c1d7 + 40b340: 83 fa 03 cmp $0x3,%edx + 40b343: 0f 84 7b 0e 00 00 je 40c1c4 + 40b349: 83 fa 01 cmp $0x1,%edx + 40b34c: 0f 84 98 0e 00 00 je 40c1ea + 40b352: 48 89 c7 mov %rax,%rdi + 40b355: e8 56 2a 01 00 callq 41ddb0 <__cfree> + 40b35a: e9 e6 f5 ff ff jmpq 40a945 + 40b35f: 49 8b 7f 18 mov 0x18(%r15),%rdi + 40b363: e8 a8 a8 ff ff callq 405c10 <__gettext_free_exp> + 40b368: 49 8b 47 10 mov 0x10(%r15),%rax + 40b36c: 48 85 c0 test %rax,%rax + 40b36f: 74 25 je 40b396 + 40b371: 8b 10 mov (%rax),%edx + 40b373: 83 fa 02 cmp $0x2,%edx + 40b376: 0f 84 85 1b 00 00 je 40cf01 + 40b37c: 83 fa 03 cmp $0x3,%edx + 40b37f: 0f 84 6b 1b 00 00 je 40cef0 + 40b385: 83 fa 01 cmp $0x1,%edx + 40b388: 0f 84 84 1b 00 00 je 40cf12 + 40b38e: 48 89 c7 mov %rax,%rdi + 40b391: e8 1a 2a 01 00 callq 41ddb0 <__cfree> + 40b396: 49 8b 47 08 mov 0x8(%r15),%rax + 40b39a: 48 85 c0 test %rax,%rax + 40b39d: 0f 84 13 f6 ff ff je 40a9b6 + 40b3a3: 8b 10 mov (%rax),%edx + 40b3a5: 83 fa 02 cmp $0x2,%edx + 40b3a8: 0f 84 04 10 00 00 je 40c3b2 + 40b3ae: 83 fa 03 cmp $0x3,%edx + 40b3b1: 0f 84 ea 0f 00 00 je 40c3a1 + 40b3b7: 83 fa 01 cmp $0x1,%edx + 40b3ba: 0f 84 03 10 00 00 je 40c3c3 + 40b3c0: 48 89 c7 mov %rax,%rdi + 40b3c3: e8 e8 29 01 00 callq 41ddb0 <__cfree> + 40b3c8: e9 e9 f5 ff ff jmpq 40a9b6 + 40b3cd: 49 8b 7f 18 mov 0x18(%r15),%rdi + 40b3d1: e8 3a a8 ff ff callq 405c10 <__gettext_free_exp> + 40b3d6: 49 8b 47 10 mov 0x10(%r15),%rax + 40b3da: 48 85 c0 test %rax,%rax + 40b3dd: 74 25 je 40b404 + 40b3df: 8b 10 mov (%rax),%edx + 40b3e1: 83 fa 02 cmp $0x2,%edx + 40b3e4: 0f 84 a7 1a 00 00 je 40ce91 + 40b3ea: 83 fa 03 cmp $0x3,%edx + 40b3ed: 0f 84 8d 1a 00 00 je 40ce80 + 40b3f3: 83 fa 01 cmp $0x1,%edx + 40b3f6: 0f 84 a6 1a 00 00 je 40cea2 + 40b3fc: 48 89 c7 mov %rax,%rdi + 40b3ff: e8 ac 29 01 00 callq 41ddb0 <__cfree> + 40b404: 49 8b 47 08 mov 0x8(%r15),%rax + 40b408: 48 85 c0 test %rax,%rax + 40b40b: 0f 84 c1 ea ff ff je 409ed2 + 40b411: 8b 10 mov (%rax),%edx + 40b413: 83 fa 02 cmp $0x2,%edx + 40b416: 0f 84 35 0f 00 00 je 40c351 + 40b41c: 83 fa 03 cmp $0x3,%edx + 40b41f: 0f 84 1b 0f 00 00 je 40c340 + 40b425: 83 fa 01 cmp $0x1,%edx + 40b428: 0f 84 34 0f 00 00 je 40c362 + 40b42e: 48 89 c7 mov %rax,%rdi + 40b431: e8 7a 29 01 00 callq 41ddb0 <__cfree> + 40b436: e9 97 ea ff ff jmpq 409ed2 + 40b43b: 49 8b 7f 18 mov 0x18(%r15),%rdi + 40b43f: e8 cc a7 ff ff callq 405c10 <__gettext_free_exp> + 40b444: 49 8b 47 10 mov 0x10(%r15),%rax + 40b448: 48 85 c0 test %rax,%rax + 40b44b: 74 25 je 40b472 + 40b44d: 8b 10 mov (%rax),%edx + 40b44f: 83 fa 02 cmp $0x2,%edx + 40b452: 0f 84 14 1d 00 00 je 40d16c + 40b458: 83 fa 03 cmp $0x3,%edx + 40b45b: 0f 84 fa 1c 00 00 je 40d15b + 40b461: 83 fa 01 cmp $0x1,%edx + 40b464: 0f 84 13 1d 00 00 je 40d17d + 40b46a: 48 89 c7 mov %rax,%rdi + 40b46d: e8 3e 29 01 00 callq 41ddb0 <__cfree> + 40b472: 49 8b 47 08 mov 0x8(%r15),%rax + 40b476: 48 85 c0 test %rax,%rax + 40b479: 0f 84 12 f0 ff ff je 40a491 + 40b47f: 8b 10 mov (%rax),%edx + 40b481: 83 fa 02 cmp $0x2,%edx + 40b484: 0f 84 05 0e 00 00 je 40c28f + 40b48a: 83 fa 03 cmp $0x3,%edx + 40b48d: 0f 84 eb 0d 00 00 je 40c27e + 40b493: 83 fa 01 cmp $0x1,%edx + 40b496: 0f 84 04 0e 00 00 je 40c2a0 + 40b49c: 48 89 c7 mov %rax,%rdi + 40b49f: e8 0c 29 01 00 callq 41ddb0 <__cfree> + 40b4a4: e9 e8 ef ff ff jmpq 40a491 + 40b4a9: 49 8b 7f 18 mov 0x18(%r15),%rdi + 40b4ad: e8 5e a7 ff ff callq 405c10 <__gettext_free_exp> + 40b4b2: 49 8b 47 10 mov 0x10(%r15),%rax + 40b4b6: 48 85 c0 test %rax,%rax + 40b4b9: 74 25 je 40b4e0 + 40b4bb: 8b 10 mov (%rax),%edx + 40b4bd: 83 fa 02 cmp $0x2,%edx + 40b4c0: 0f 84 6e 1c 00 00 je 40d134 + 40b4c6: 83 fa 03 cmp $0x3,%edx + 40b4c9: 0f 84 54 1c 00 00 je 40d123 + 40b4cf: 83 fa 01 cmp $0x1,%edx + 40b4d2: 0f 84 6d 1c 00 00 je 40d145 + 40b4d8: 48 89 c7 mov %rax,%rdi + 40b4db: e8 d0 28 01 00 callq 41ddb0 <__cfree> + 40b4e0: 49 8b 47 08 mov 0x8(%r15),%rax + 40b4e4: 48 85 c0 test %rax,%rax + 40b4e7: 0f 84 ca ed ff ff je 40a2b7 + 40b4ed: 8b 10 mov (%rax),%edx + 40b4ef: 83 fa 02 cmp $0x2,%edx + 40b4f2: 0f 84 1b 0f 00 00 je 40c413 + 40b4f8: 83 fa 03 cmp $0x3,%edx + 40b4fb: 0f 84 01 0f 00 00 je 40c402 + 40b501: 83 fa 01 cmp $0x1,%edx + 40b504: 0f 84 1a 0f 00 00 je 40c424 + 40b50a: 48 89 c7 mov %rax,%rdi + 40b50d: e8 9e 28 01 00 callq 41ddb0 <__cfree> + 40b512: e9 a0 ed ff ff jmpq 40a2b7 + 40b517: 49 8b 7f 18 mov 0x18(%r15),%rdi + 40b51b: e8 f0 a6 ff ff callq 405c10 <__gettext_free_exp> + 40b520: 49 8b 47 10 mov 0x10(%r15),%rax + 40b524: 48 85 c0 test %rax,%rax + 40b527: 74 25 je 40b54e + 40b529: 8b 10 mov (%rax),%edx + 40b52b: 83 fa 02 cmp $0x2,%edx + 40b52e: 0f 84 25 19 00 00 je 40ce59 + 40b534: 83 fa 03 cmp $0x3,%edx + 40b537: 0f 84 0b 19 00 00 je 40ce48 + 40b53d: 83 fa 01 cmp $0x1,%edx + 40b540: 0f 84 24 19 00 00 je 40ce6a + 40b546: 48 89 c7 mov %rax,%rdi + 40b549: e8 62 28 01 00 callq 41ddb0 <__cfree> + 40b54e: 49 8b 47 08 mov 0x8(%r15),%rax + 40b552: 48 85 c0 test %rax,%rax + 40b555: 0f 84 1b f3 ff ff je 40a876 + 40b55b: 8b 10 mov (%rax),%edx + 40b55d: 83 fa 02 cmp $0x2,%edx + 40b560: 0f 84 8a 0d 00 00 je 40c2f0 + 40b566: 83 fa 03 cmp $0x3,%edx + 40b569: 0f 84 70 0d 00 00 je 40c2df + 40b56f: 83 fa 01 cmp $0x1,%edx + 40b572: 0f 84 89 0d 00 00 je 40c301 + 40b578: 48 89 c7 mov %rax,%rdi + 40b57b: e8 30 28 01 00 callq 41ddb0 <__cfree> + 40b580: e9 f1 f2 ff ff jmpq 40a876 + 40b585: 49 8b 7f 18 mov 0x18(%r15),%rdi + 40b589: e8 82 a6 ff ff callq 405c10 <__gettext_free_exp> + 40b58e: 49 8b 47 10 mov 0x10(%r15),%rax + 40b592: 48 85 c0 test %rax,%rax + 40b595: 74 25 je 40b5bc + 40b597: 8b 10 mov (%rax),%edx + 40b599: 83 fa 02 cmp $0x2,%edx + 40b59c: 0f 84 27 19 00 00 je 40cec9 + 40b5a2: 83 fa 03 cmp $0x3,%edx + 40b5a5: 0f 84 0d 19 00 00 je 40ceb8 + 40b5ab: 83 fa 01 cmp $0x1,%edx + 40b5ae: 0f 84 26 19 00 00 je 40ceda + 40b5b4: 48 89 c7 mov %rax,%rdi + 40b5b7: e8 f4 27 01 00 callq 41ddb0 <__cfree> + 40b5bc: 49 8b 47 08 mov 0x8(%r15),%rax + 40b5c0: 48 85 c0 test %rax,%rax + 40b5c3: 48 89 04 24 mov %rax,(%rsp) + 40b5c7: 0f 84 aa ea ff ff je 40a077 + 40b5cd: 8b 00 mov (%rax),%eax + 40b5cf: 83 f8 02 cmp $0x2,%eax + 40b5d2: 0f 84 cd 19 00 00 je 40cfa5 + 40b5d8: 83 f8 03 cmp $0x3,%eax + 40b5db: 0f 84 b7 19 00 00 je 40cf98 + 40b5e1: 83 f8 01 cmp $0x1,%eax + 40b5e4: 0f 84 ba 0e 00 00 je 40c4a4 + 40b5ea: 48 8b 3c 24 mov (%rsp),%rdi + 40b5ee: e8 bd 27 01 00 callq 41ddb0 <__cfree> + 40b5f3: e9 7f ea ff ff jmpq 40a077 + 40b5f8: 48 8b 78 18 mov 0x18(%rax),%rdi + 40b5fc: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40b601: e8 0a a6 ff ff callq 405c10 <__gettext_free_exp> + 40b606: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40b60b: 48 8b 78 10 mov 0x10(%rax),%rdi + 40b60f: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40b614: e8 f7 a5 ff ff callq 405c10 <__gettext_free_exp> + 40b619: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40b61e: 48 8b 78 08 mov 0x8(%rax),%rdi + 40b622: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40b627: e8 e4 a5 ff ff callq 405c10 <__gettext_free_exp> + 40b62c: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40b631: e9 7b e6 ff ff jmpq 409cb1 + 40b636: 48 8b 78 18 mov 0x18(%rax),%rdi + 40b63a: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40b63f: e8 cc a5 ff ff callq 405c10 <__gettext_free_exp> + 40b644: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40b649: 48 8b 78 10 mov 0x10(%rax),%rdi + 40b64d: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40b652: e8 b9 a5 ff ff callq 405c10 <__gettext_free_exp> + 40b657: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40b65c: 48 8b 78 08 mov 0x8(%rax),%rdi + 40b660: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40b665: e8 a6 a5 ff ff callq 405c10 <__gettext_free_exp> + 40b66a: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40b66f: e9 ad f8 ff ff jmpq 40af21 + 40b674: 48 8b 78 18 mov 0x18(%rax),%rdi + 40b678: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40b67d: e8 8e a5 ff ff callq 405c10 <__gettext_free_exp> + 40b682: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40b687: 48 8b 78 10 mov 0x10(%rax),%rdi + 40b68b: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40b690: e8 7b a5 ff ff callq 405c10 <__gettext_free_exp> + 40b695: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40b69a: 48 8b 78 08 mov 0x8(%rax),%rdi + 40b69e: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40b6a3: e8 68 a5 ff ff callq 405c10 <__gettext_free_exp> + 40b6a8: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40b6ad: e9 af fa ff ff jmpq 40b161 + 40b6b2: 48 8b 78 18 mov 0x18(%rax),%rdi + 40b6b6: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40b6bb: e8 50 a5 ff ff callq 405c10 <__gettext_free_exp> + 40b6c0: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40b6c5: 48 8b 78 10 mov 0x10(%rax),%rdi + 40b6c9: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40b6ce: e8 3d a5 ff ff callq 405c10 <__gettext_free_exp> + 40b6d3: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40b6d8: 48 8b 78 08 mov 0x8(%rax),%rdi + 40b6dc: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40b6e1: e8 2a a5 ff ff callq 405c10 <__gettext_free_exp> + 40b6e6: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40b6eb: e9 51 f9 ff ff jmpq 40b041 + 40b6f0: 48 8b 78 18 mov 0x18(%rax),%rdi + 40b6f4: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40b6f9: e8 12 a5 ff ff callq 405c10 <__gettext_free_exp> + 40b6fe: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40b703: 48 8b 78 10 mov 0x10(%rax),%rdi + 40b707: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40b70c: e8 ff a4 ff ff callq 405c10 <__gettext_free_exp> + 40b711: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40b716: 48 8b 78 08 mov 0x8(%rax),%rdi + 40b71a: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40b71f: e8 ec a4 ff ff callq 405c10 <__gettext_free_exp> + 40b724: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40b729: e9 6e f6 ff ff jmpq 40ad9c + 40b72e: 48 8b 78 18 mov 0x18(%rax),%rdi + 40b732: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40b737: e8 d4 a4 ff ff callq 405c10 <__gettext_free_exp> + 40b73c: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40b741: 48 8b 78 10 mov 0x10(%rax),%rdi + 40b745: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40b74a: e8 c1 a4 ff ff callq 405c10 <__gettext_free_exp> + 40b74f: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40b754: 48 8b 78 08 mov 0x8(%rax),%rdi + 40b758: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40b75d: e8 ae a4 ff ff callq 405c10 <__gettext_free_exp> + 40b762: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40b767: e9 50 f5 ff ff jmpq 40acbc + 40b76c: 48 8b 78 18 mov 0x18(%rax),%rdi + 40b770: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40b775: e8 96 a4 ff ff callq 405c10 <__gettext_free_exp> + 40b77a: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40b77f: 48 8b 78 10 mov 0x10(%rax),%rdi + 40b783: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40b788: e8 83 a4 ff ff callq 405c10 <__gettext_free_exp> + 40b78d: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40b792: 48 8b 78 08 mov 0x8(%rax),%rdi + 40b796: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40b79b: e8 70 a4 ff ff callq 405c10 <__gettext_free_exp> + 40b7a0: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40b7a5: e9 32 f4 ff ff jmpq 40abdc + 40b7aa: 48 8b 78 18 mov 0x18(%rax),%rdi + 40b7ae: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40b7b3: e8 58 a4 ff ff callq 405c10 <__gettext_free_exp> + 40b7b8: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40b7bd: 48 8b 78 10 mov 0x10(%rax),%rdi + 40b7c1: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40b7c6: e8 45 a4 ff ff callq 405c10 <__gettext_free_exp> + 40b7cb: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40b7d0: 48 8b 78 08 mov 0x8(%rax),%rdi + 40b7d4: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40b7d9: e8 32 a4 ff ff callq 405c10 <__gettext_free_exp> + 40b7de: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40b7e3: e9 71 e9 ff ff jmpq 40a159 + 40b7e8: 48 8b 78 18 mov 0x18(%rax),%rdi + 40b7ec: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40b7f1: e8 1a a4 ff ff callq 405c10 <__gettext_free_exp> + 40b7f6: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40b7fb: 48 8b 78 10 mov 0x10(%rax),%rdi + 40b7ff: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40b804: e8 07 a4 ff ff callq 405c10 <__gettext_free_exp> + 40b809: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40b80e: 48 8b 78 08 mov 0x8(%rax),%rdi + 40b812: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40b817: e8 f4 a3 ff ff callq 405c10 <__gettext_free_exp> + 40b81c: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40b821: e9 9d eb ff ff jmpq 40a3c3 + 40b826: 48 8b 78 18 mov 0x18(%rax),%rdi + 40b82a: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40b82f: e8 dc a3 ff ff callq 405c10 <__gettext_free_exp> + 40b834: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40b839: 48 8b 78 10 mov 0x10(%rax),%rdi + 40b83d: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40b842: e8 c9 a3 ff ff callq 405c10 <__gettext_free_exp> + 40b847: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40b84c: 48 8b 78 08 mov 0x8(%rax),%rdi + 40b850: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40b855: e8 b6 a3 ff ff callq 405c10 <__gettext_free_exp> + 40b85a: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40b85f: e9 98 f2 ff ff jmpq 40aafc + 40b864: 48 8b 04 24 mov (%rsp),%rax + 40b868: 48 8b 78 18 mov 0x18(%rax),%rdi + 40b86c: e8 9f a3 ff ff callq 405c10 <__gettext_free_exp> + 40b871: 48 8b 04 24 mov (%rsp),%rax + 40b875: 48 8b 40 10 mov 0x10(%rax),%rax + 40b879: 48 85 c0 test %rax,%rax + 40b87c: 74 25 je 40b8a3 + 40b87e: 8b 10 mov (%rax),%edx + 40b880: 83 fa 02 cmp $0x2,%edx + 40b883: 0f 84 d0 07 00 00 je 40c059 + 40b889: 83 fa 03 cmp $0x3,%edx + 40b88c: 0f 84 b4 07 00 00 je 40c046 + 40b892: 83 fa 01 cmp $0x1,%edx + 40b895: 0f 84 d1 07 00 00 je 40c06c + 40b89b: 48 89 c7 mov %rax,%rdi + 40b89e: e8 0d 25 01 00 callq 41ddb0 <__cfree> + 40b8a3: 48 8b 04 24 mov (%rsp),%rax + 40b8a7: 48 8b 40 08 mov 0x8(%rax),%rax + 40b8ab: 48 85 c0 test %rax,%rax + 40b8ae: 0f 84 e4 f6 ff ff je 40af98 + 40b8b4: 8b 10 mov (%rax),%edx + 40b8b6: 83 fa 02 cmp $0x2,%edx + 40b8b9: 0f 84 ed 0c 00 00 je 40c5ac + 40b8bf: 83 fa 03 cmp $0x3,%edx + 40b8c2: 0f 84 d1 0c 00 00 je 40c599 + 40b8c8: 83 fa 01 cmp $0x1,%edx + 40b8cb: 0f 84 ee 0c 00 00 je 40c5bf + 40b8d1: 48 89 c7 mov %rax,%rdi + 40b8d4: e8 d7 24 01 00 callq 41ddb0 <__cfree> + 40b8d9: e9 ba f6 ff ff jmpq 40af98 + 40b8de: 48 8b 04 24 mov (%rsp),%rax + 40b8e2: 48 8b 78 18 mov 0x18(%rax),%rdi + 40b8e6: e8 25 a3 ff ff callq 405c10 <__gettext_free_exp> + 40b8eb: 48 8b 04 24 mov (%rsp),%rax + 40b8ef: 48 8b 40 10 mov 0x10(%rax),%rax + 40b8f3: 48 85 c0 test %rax,%rax + 40b8f6: 74 25 je 40b91d + 40b8f8: 8b 10 mov (%rax),%edx + 40b8fa: 83 fa 02 cmp $0x2,%edx + 40b8fd: 0f 84 fa 07 00 00 je 40c0fd + 40b903: 83 fa 03 cmp $0x3,%edx + 40b906: 0f 84 de 07 00 00 je 40c0ea + 40b90c: 83 fa 01 cmp $0x1,%edx + 40b90f: 0f 84 fb 07 00 00 je 40c110 + 40b915: 48 89 c7 mov %rax,%rdi + 40b918: e8 93 24 01 00 callq 41ddb0 <__cfree> + 40b91d: 48 8b 04 24 mov (%rsp),%rax + 40b921: 48 8b 40 08 mov 0x8(%rax),%rax + 40b925: 48 85 c0 test %rax,%rax + 40b928: 0f 84 6b e4 ff ff je 409d99 + 40b92e: 8b 10 mov (%rax),%edx + 40b930: 83 fa 02 cmp $0x2,%edx + 40b933: 0f 84 b9 0b 00 00 je 40c4f2 + 40b939: 83 fa 03 cmp $0x3,%edx + 40b93c: 0f 84 9d 0b 00 00 je 40c4df + 40b942: 83 fa 01 cmp $0x1,%edx + 40b945: 0f 84 ba 0b 00 00 je 40c505 + 40b94b: 48 89 c7 mov %rax,%rdi + 40b94e: e8 5d 24 01 00 callq 41ddb0 <__cfree> + 40b953: e9 41 e4 ff ff jmpq 409d99 + 40b958: 48 8b 04 24 mov (%rsp),%rax + 40b95c: 48 8b 78 18 mov 0x18(%rax),%rdi + 40b960: e8 ab a2 ff ff callq 405c10 <__gettext_free_exp> + 40b965: 48 8b 04 24 mov (%rsp),%rax + 40b969: 48 8b 40 10 mov 0x10(%rax),%rax + 40b96d: 48 85 c0 test %rax,%rax + 40b970: 74 25 je 40b997 + 40b972: 8b 10 mov (%rax),%edx + 40b974: 83 fa 02 cmp $0x2,%edx + 40b977: 0f 84 9e 06 00 00 je 40c01b + 40b97d: 83 fa 03 cmp $0x3,%edx + 40b980: 0f 84 82 06 00 00 je 40c008 + 40b986: 83 fa 01 cmp $0x1,%edx + 40b989: 0f 84 9f 06 00 00 je 40c02e + 40b98f: 48 89 c7 mov %rax,%rdi + 40b992: e8 19 24 01 00 callq 41ddb0 <__cfree> + 40b997: 48 8b 04 24 mov (%rsp),%rax + 40b99b: 48 8b 40 08 mov 0x8(%rax),%rax + 40b99f: 48 85 c0 test %rax,%rax + 40b9a2: 0f 84 d0 f4 ff ff je 40ae78 + 40b9a8: 8b 10 mov (%rax),%edx + 40b9aa: 83 fa 02 cmp $0x2,%edx + 40b9ad: 0f 84 7d 0b 00 00 je 40c530 + 40b9b3: 83 fa 03 cmp $0x3,%edx + 40b9b6: 0f 84 61 0b 00 00 je 40c51d + 40b9bc: 83 fa 01 cmp $0x1,%edx + 40b9bf: 0f 84 7e 0b 00 00 je 40c543 + 40b9c5: 48 89 c7 mov %rax,%rdi + 40b9c8: e8 e3 23 01 00 callq 41ddb0 <__cfree> + 40b9cd: e9 a6 f4 ff ff jmpq 40ae78 + 40b9d2: 48 8b 04 24 mov (%rsp),%rax + 40b9d6: 48 8b 78 18 mov 0x18(%rax),%rdi + 40b9da: e8 31 a2 ff ff callq 405c10 <__gettext_free_exp> + 40b9df: 48 8b 04 24 mov (%rsp),%rax + 40b9e3: 48 8b 40 10 mov 0x10(%rax),%rax + 40b9e7: 48 85 c0 test %rax,%rax + 40b9ea: 74 25 je 40ba11 + 40b9ec: 8b 10 mov (%rax),%edx + 40b9ee: 83 fa 02 cmp $0x2,%edx + 40b9f1: 0f 84 44 07 00 00 je 40c13b + 40b9f7: 83 fa 03 cmp $0x3,%edx + 40b9fa: 0f 84 28 07 00 00 je 40c128 + 40ba00: 83 fa 01 cmp $0x1,%edx + 40ba03: 0f 84 45 07 00 00 je 40c14e + 40ba09: 48 89 c7 mov %rax,%rdi + 40ba0c: e8 9f 23 01 00 callq 41ddb0 <__cfree> + 40ba11: 48 8b 04 24 mov (%rsp),%rax + 40ba15: 48 8b 40 08 mov 0x8(%rax),%rax + 40ba19: 48 85 c0 test %rax,%rax + 40ba1c: 0f 84 96 f6 ff ff je 40b0b8 + 40ba22: 8b 10 mov (%rax),%edx + 40ba24: 83 fa 02 cmp $0x2,%edx + 40ba27: 0f 84 41 0b 00 00 je 40c56e + 40ba2d: 83 fa 03 cmp $0x3,%edx + 40ba30: 0f 84 25 0b 00 00 je 40c55b + 40ba36: 83 fa 01 cmp $0x1,%edx + 40ba39: 0f 84 42 0b 00 00 je 40c581 + 40ba3f: 48 89 c7 mov %rax,%rdi + 40ba42: e8 69 23 01 00 callq 41ddb0 <__cfree> + 40ba47: e9 6c f6 ff ff jmpq 40b0b8 + 40ba4c: 49 8b 7e 18 mov 0x18(%r14),%rdi + 40ba50: e8 bb a1 ff ff callq 405c10 <__gettext_free_exp> + 40ba55: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 40ba59: 4d 85 ff test %r15,%r15 + 40ba5c: 74 26 je 40ba84 + 40ba5e: 41 8b 07 mov (%r15),%eax + 40ba61: 83 f8 02 cmp $0x2,%eax + 40ba64: 0f 84 05 07 00 00 je 40c16f + 40ba6a: 83 f8 03 cmp $0x3,%eax + 40ba6d: 0f 84 f3 06 00 00 je 40c166 + 40ba73: 83 f8 01 cmp $0x1,%eax + 40ba76: 0f 84 fc 06 00 00 je 40c178 + 40ba7c: 4c 89 ff mov %r15,%rdi + 40ba7f: e8 2c 23 01 00 callq 41ddb0 <__cfree> + 40ba84: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 40ba88: 4d 85 ff test %r15,%r15 + 40ba8b: 0f 84 b6 ea ff ff je 40a547 + 40ba91: 41 8b 07 mov (%r15),%eax + 40ba94: 83 f8 02 cmp $0x2,%eax + 40ba97: 0f 84 bd 0c 00 00 je 40c75a + 40ba9d: 83 f8 03 cmp $0x3,%eax + 40baa0: 0f 84 ab 0c 00 00 je 40c751 + 40baa6: 83 f8 01 cmp $0x1,%eax + 40baa9: 0f 84 b4 0c 00 00 je 40c763 + 40baaf: 4c 89 ff mov %r15,%rdi + 40bab2: e8 f9 22 01 00 callq 41ddb0 <__cfree> + 40bab7: e9 8b ea ff ff jmpq 40a547 + 40babc: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 40bac0: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40bac5: 48 89 14 24 mov %rdx,(%rsp) + 40bac9: e8 42 a1 ff ff callq 405c10 <__gettext_free_exp> + 40bace: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40bad3: 48 8b 14 24 mov (%rsp),%rdx + 40bad7: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 40badb: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40bae0: 48 89 14 24 mov %rdx,(%rsp) + 40bae4: e8 27 a1 ff ff callq 405c10 <__gettext_free_exp> + 40bae9: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40baee: 48 8b 14 24 mov (%rsp),%rdx + 40baf2: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 40baf6: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40bafb: 48 89 14 24 mov %rdx,(%rsp) + 40baff: e8 0c a1 ff ff callq 405c10 <__gettext_free_exp> + 40bb04: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40bb09: 48 8b 14 24 mov (%rsp),%rdx + 40bb0d: e9 fc ea ff ff jmpq 40a60e + 40bb12: 48 8b 78 18 mov 0x18(%rax),%rdi + 40bb16: 48 89 04 24 mov %rax,(%rsp) + 40bb1a: e8 f1 a0 ff ff callq 405c10 <__gettext_free_exp> + 40bb1f: 48 8b 04 24 mov (%rsp),%rax + 40bb23: 48 8b 78 10 mov 0x10(%rax),%rdi + 40bb27: 48 89 04 24 mov %rax,(%rsp) + 40bb2b: e8 e0 a0 ff ff callq 405c10 <__gettext_free_exp> + 40bb30: 48 8b 04 24 mov (%rsp),%rax + 40bb34: 48 8b 50 08 mov 0x8(%rax),%rdx + 40bb38: 48 85 d2 test %rdx,%rdx + 40bb3b: 0f 84 ce e6 ff ff je 40a20f + 40bb41: 8b 0a mov (%rdx),%ecx + 40bb43: 83 f9 02 cmp $0x2,%ecx + 40bb46: 0f 84 33 12 00 00 je 40cd7f + 40bb4c: 83 f9 03 cmp $0x3,%ecx + 40bb4f: 0f 84 0f 12 00 00 je 40cd64 + 40bb55: 83 f9 01 cmp $0x1,%ecx + 40bb58: 0f 84 3c 12 00 00 je 40cd9a + 40bb5e: 48 89 d7 mov %rdx,%rdi + 40bb61: 48 89 04 24 mov %rax,(%rsp) + 40bb65: e8 46 22 01 00 callq 41ddb0 <__cfree> + 40bb6a: 48 8b 04 24 mov (%rsp),%rax + 40bb6e: e9 9c e6 ff ff jmpq 40a20f + 40bb73: 48 8b 78 18 mov 0x18(%rax),%rdi + 40bb77: 48 89 04 24 mov %rax,(%rsp) + 40bb7b: e8 90 a0 ff ff callq 405c10 <__gettext_free_exp> + 40bb80: 48 8b 04 24 mov (%rsp),%rax + 40bb84: 48 8b 78 10 mov 0x10(%rax),%rdi + 40bb88: 48 89 04 24 mov %rax,(%rsp) + 40bb8c: e8 7f a0 ff ff callq 405c10 <__gettext_free_exp> + 40bb91: 48 8b 04 24 mov (%rsp),%rax + 40bb95: 48 8b 50 08 mov 0x8(%rax),%rdx + 40bb99: 48 85 d2 test %rdx,%rdx + 40bb9c: 0f 84 e4 ea ff ff je 40a686 + 40bba2: 8b 0a mov (%rdx),%ecx + 40bba4: 83 f9 02 cmp $0x2,%ecx + 40bba7: 0f 84 e8 10 00 00 je 40cc95 + 40bbad: 83 f9 03 cmp $0x3,%ecx + 40bbb0: 0f 84 c4 10 00 00 je 40cc7a + 40bbb6: 83 f9 01 cmp $0x1,%ecx + 40bbb9: 0f 84 f1 10 00 00 je 40ccb0 + 40bbbf: 48 89 d7 mov %rdx,%rdi + 40bbc2: 48 89 04 24 mov %rax,(%rsp) + 40bbc6: e8 e5 21 01 00 callq 41ddb0 <__cfree> + 40bbcb: 48 8b 04 24 mov (%rsp),%rax + 40bbcf: e9 b2 ea ff ff jmpq 40a686 + 40bbd4: 48 8b 78 18 mov 0x18(%rax),%rdi + 40bbd8: 48 89 04 24 mov %rax,(%rsp) + 40bbdc: e8 2f a0 ff ff callq 405c10 <__gettext_free_exp> + 40bbe1: 48 8b 04 24 mov (%rsp),%rax + 40bbe5: 48 8b 78 10 mov 0x10(%rax),%rdi + 40bbe9: 48 89 04 24 mov %rax,(%rsp) + 40bbed: e8 1e a0 ff ff callq 405c10 <__gettext_free_exp> + 40bbf2: 48 8b 04 24 mov (%rsp),%rax + 40bbf6: 48 8b 50 08 mov 0x8(%rax),%rdx + 40bbfa: 48 85 d2 test %rdx,%rdx + 40bbfd: 0f 84 0c ed ff ff je 40a90f + 40bc03: 8b 0a mov (%rdx),%ecx + 40bc05: 83 f9 02 cmp $0x2,%ecx + 40bc08: 0f 84 93 0c 00 00 je 40c8a1 + 40bc0e: 83 f9 03 cmp $0x3,%ecx + 40bc11: 0f 84 6f 0c 00 00 je 40c886 + 40bc17: 83 f9 01 cmp $0x1,%ecx + 40bc1a: 0f 84 9c 0c 00 00 je 40c8bc + 40bc20: 48 89 d7 mov %rdx,%rdi + 40bc23: 48 89 04 24 mov %rax,(%rsp) + 40bc27: e8 84 21 01 00 callq 41ddb0 <__cfree> + 40bc2c: 48 8b 04 24 mov (%rsp),%rax + 40bc30: e9 da ec ff ff jmpq 40a90f + 40bc35: 48 8b 78 18 mov 0x18(%rax),%rdi + 40bc39: 48 89 04 24 mov %rax,(%rsp) + 40bc3d: e8 ce 9f ff ff callq 405c10 <__gettext_free_exp> + 40bc42: 48 8b 04 24 mov (%rsp),%rax + 40bc46: 48 8b 78 10 mov 0x10(%rax),%rdi + 40bc4a: 48 89 04 24 mov %rax,(%rsp) + 40bc4e: e8 bd 9f ff ff callq 405c10 <__gettext_free_exp> + 40bc53: 48 8b 04 24 mov (%rsp),%rax + 40bc57: 48 8b 50 08 mov 0x8(%rax),%rdx + 40bc5b: 48 85 d2 test %rdx,%rdx + 40bc5e: 0f 84 eb ed ff ff je 40aa4f + 40bc64: 8b 0a mov (%rdx),%ecx + 40bc66: 83 f9 02 cmp $0x2,%ecx + 40bc69: 0f 84 7c 10 00 00 je 40cceb + 40bc6f: 83 f9 03 cmp $0x3,%ecx + 40bc72: 0f 84 58 10 00 00 je 40ccd0 + 40bc78: 83 f9 01 cmp $0x1,%ecx + 40bc7b: 0f 84 85 10 00 00 je 40cd06 + 40bc81: 48 89 d7 mov %rdx,%rdi + 40bc84: 48 89 04 24 mov %rax,(%rsp) + 40bc88: e8 23 21 01 00 callq 41ddb0 <__cfree> + 40bc8d: 48 8b 04 24 mov (%rsp),%rax + 40bc91: e9 b9 ed ff ff jmpq 40aa4f + 40bc96: 48 8b 78 18 mov 0x18(%rax),%rdi + 40bc9a: 48 89 04 24 mov %rax,(%rsp) + 40bc9e: e8 6d 9f ff ff callq 405c10 <__gettext_free_exp> + 40bca3: 48 8b 04 24 mov (%rsp),%rax + 40bca7: 48 8b 78 10 mov 0x10(%rax),%rdi + 40bcab: 48 89 04 24 mov %rax,(%rsp) + 40bcaf: e8 5c 9f ff ff callq 405c10 <__gettext_free_exp> + 40bcb4: 48 8b 04 24 mov (%rsp),%rax + 40bcb8: 48 8b 50 08 mov 0x8(%rax),%rdx + 40bcbc: 48 85 d2 test %rdx,%rdx + 40bcbf: 0f 84 a1 ea ff ff je 40a766 + 40bcc5: 8b 0a mov (%rdx),%ecx + 40bcc7: 83 f9 02 cmp $0x2,%ecx + 40bcca: 0f 84 f9 0c 00 00 je 40c9c9 + 40bcd0: 83 f9 03 cmp $0x3,%ecx + 40bcd3: 0f 84 d5 0c 00 00 je 40c9ae + 40bcd9: 83 f9 01 cmp $0x1,%ecx + 40bcdc: 0f 84 02 0d 00 00 je 40c9e4 + 40bce2: 48 89 d7 mov %rdx,%rdi + 40bce5: 48 89 04 24 mov %rax,(%rsp) + 40bce9: e8 c2 20 01 00 callq 41ddb0 <__cfree> + 40bcee: 48 8b 04 24 mov (%rsp),%rax + 40bcf2: e9 6f ea ff ff jmpq 40a766 + 40bcf7: 48 8b 78 18 mov 0x18(%rax),%rdi + 40bcfb: 48 89 04 24 mov %rax,(%rsp) + 40bcff: e8 0c 9f ff ff callq 405c10 <__gettext_free_exp> + 40bd04: 48 8b 04 24 mov (%rsp),%rax + 40bd08: 48 8b 78 10 mov 0x10(%rax),%rdi + 40bd0c: 48 89 04 24 mov %rax,(%rsp) + 40bd10: e8 fb 9e ff ff callq 405c10 <__gettext_free_exp> + 40bd15: 48 8b 04 24 mov (%rsp),%rax + 40bd19: 48 8b 50 08 mov 0x8(%rax),%rdx + 40bd1d: 48 85 d2 test %rdx,%rdx + 40bd20: 0f 84 d0 e9 ff ff je 40a6f6 + 40bd26: 8b 0a mov (%rdx),%ecx + 40bd28: 83 f9 02 cmp $0x2,%ecx + 40bd2b: 0f 84 0e 0f 00 00 je 40cc3f + 40bd31: 83 f9 03 cmp $0x3,%ecx + 40bd34: 0f 84 ea 0e 00 00 je 40cc24 + 40bd3a: 83 f9 01 cmp $0x1,%ecx + 40bd3d: 0f 84 17 0f 00 00 je 40cc5a + 40bd43: 48 89 d7 mov %rdx,%rdi + 40bd46: 48 89 04 24 mov %rax,(%rsp) + 40bd4a: e8 61 20 01 00 callq 41ddb0 <__cfree> + 40bd4f: 48 8b 04 24 mov (%rsp),%rax + 40bd53: e9 9e e9 ff ff jmpq 40a6f6 + 40bd58: 49 8b 7f 18 mov 0x18(%r15),%rdi + 40bd5c: e8 af 9e ff ff callq 405c10 <__gettext_free_exp> + 40bd61: 49 8b 7f 10 mov 0x10(%r15),%rdi + 40bd65: e8 a6 9e ff ff callq 405c10 <__gettext_free_exp> + 40bd6a: 49 8b 47 08 mov 0x8(%r15),%rax + 40bd6e: 48 85 c0 test %rax,%rax + 40bd71: 0f 84 eb e6 ff ff je 40a462 + 40bd77: 8b 10 mov (%rax),%edx + 40bd79: 83 fa 02 cmp $0x2,%edx + 40bd7c: 0f 84 ef 11 00 00 je 40cf71 + 40bd82: 83 fa 03 cmp $0x3,%edx + 40bd85: 0f 84 d5 11 00 00 je 40cf60 + 40bd8b: 83 fa 01 cmp $0x1,%edx + 40bd8e: 0f 84 ee 11 00 00 je 40cf82 + 40bd94: 48 89 c7 mov %rax,%rdi + 40bd97: e8 14 20 01 00 callq 41ddb0 <__cfree> + 40bd9c: e9 c1 e6 ff ff jmpq 40a462 + 40bda1: 49 8b 7f 18 mov 0x18(%r15),%rdi + 40bda5: e8 66 9e ff ff callq 405c10 <__gettext_free_exp> + 40bdaa: 49 8b 7f 10 mov 0x10(%r15),%rdi + 40bdae: e8 5d 9e ff ff callq 405c10 <__gettext_free_exp> + 40bdb3: 49 8b 47 08 mov 0x8(%r15),%rax + 40bdb7: 48 85 c0 test %rax,%rax + 40bdba: 0f 84 e3 e0 ff ff je 409ea3 + 40bdc0: 8b 10 mov (%rax),%edx + 40bdc2: 83 fa 02 cmp $0x2,%edx + 40bdc5: 0f 84 56 10 00 00 je 40ce21 + 40bdcb: 83 fa 03 cmp $0x3,%edx + 40bdce: 0f 84 3c 10 00 00 je 40ce10 + 40bdd4: 83 fa 01 cmp $0x1,%edx + 40bdd7: 0f 84 55 10 00 00 je 40ce32 + 40bddd: 48 89 c7 mov %rax,%rdi + 40bde0: e8 cb 1f 01 00 callq 41ddb0 <__cfree> + 40bde5: e9 b9 e0 ff ff jmpq 409ea3 + 40bdea: 49 8b 7f 18 mov 0x18(%r15),%rdi + 40bdee: e8 1d 9e ff ff callq 405c10 <__gettext_free_exp> + 40bdf3: 49 8b 7f 10 mov 0x10(%r15),%rdi + 40bdf7: e8 14 9e ff ff callq 405c10 <__gettext_free_exp> + 40bdfc: 49 8b 47 08 mov 0x8(%r15),%rax + 40be00: 48 85 c0 test %rax,%rax + 40be03: 0f 84 ce e9 ff ff je 40a7d7 + 40be09: 8b 10 mov (%rax),%edx + 40be0b: 83 fa 02 cmp $0x2,%edx + 40be0e: 0f 84 d5 11 00 00 je 40cfe9 + 40be14: 83 fa 03 cmp $0x3,%edx + 40be17: 0f 84 bb 11 00 00 je 40cfd8 + 40be1d: 83 fa 01 cmp $0x1,%edx + 40be20: 0f 84 d4 11 00 00 je 40cffa + 40be26: 48 89 c7 mov %rax,%rdi + 40be29: e8 82 1f 01 00 callq 41ddb0 <__cfree> + 40be2e: e9 a4 e9 ff ff jmpq 40a7d7 + 40be33: 48 8b 78 18 mov 0x18(%rax),%rdi + 40be37: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40be3c: e8 cf 9d ff ff callq 405c10 <__gettext_free_exp> + 40be41: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40be46: 48 8b 78 10 mov 0x10(%rax),%rdi + 40be4a: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40be4f: e8 bc 9d ff ff callq 405c10 <__gettext_free_exp> + 40be54: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40be59: 48 8b 78 08 mov 0x8(%rax),%rdi + 40be5d: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40be62: e8 a9 9d ff ff callq 405c10 <__gettext_free_exp> + 40be67: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40be6c: e9 20 e5 ff ff jmpq 40a391 + 40be71: 48 8b 78 18 mov 0x18(%rax),%rdi + 40be75: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40be7a: e8 91 9d ff ff callq 405c10 <__gettext_free_exp> + 40be7f: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40be84: 48 8b 78 10 mov 0x10(%rax),%rdi + 40be88: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40be8d: e8 7e 9d ff ff callq 405c10 <__gettext_free_exp> + 40be92: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40be97: 48 8b 78 08 mov 0x8(%rax),%rdi + 40be9b: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40bea0: e8 6b 9d ff ff callq 405c10 <__gettext_free_exp> + 40bea5: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40beaa: e9 78 e2 ff ff jmpq 40a127 + 40beaf: 48 8b 78 18 mov 0x18(%rax),%rdi + 40beb3: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40beb8: e8 53 9d ff ff callq 405c10 <__gettext_free_exp> + 40bebd: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40bec2: 48 8b 78 10 mov 0x10(%rax),%rdi + 40bec6: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40becb: e8 40 9d ff ff callq 405c10 <__gettext_free_exp> + 40bed0: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40bed5: 48 8b 78 08 mov 0x8(%rax),%rdi + 40bed9: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40bede: e8 2d 9d ff ff callq 405c10 <__gettext_free_exp> + 40bee3: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40bee8: e9 02 f0 ff ff jmpq 40aeef + 40beed: 48 8b 78 18 mov 0x18(%rax),%rdi + 40bef1: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40bef6: e8 15 9d ff ff callq 405c10 <__gettext_free_exp> + 40befb: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40bf00: 48 8b 78 10 mov 0x10(%rax),%rdi + 40bf04: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40bf09: e8 02 9d ff ff callq 405c10 <__gettext_free_exp> + 40bf0e: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40bf13: 48 8b 78 08 mov 0x8(%rax),%rdi + 40bf17: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40bf1c: e8 ef 9c ff ff callq 405c10 <__gettext_free_exp> + 40bf21: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40bf26: e9 54 dd ff ff jmpq 409c7f + 40bf2b: 48 8b 78 18 mov 0x18(%rax),%rdi + 40bf2f: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40bf34: e8 d7 9c ff ff callq 405c10 <__gettext_free_exp> + 40bf39: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40bf3e: 48 8b 78 10 mov 0x10(%rax),%rdi + 40bf42: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40bf47: e8 c4 9c ff ff callq 405c10 <__gettext_free_exp> + 40bf4c: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40bf51: 48 8b 78 08 mov 0x8(%rax),%rdi + 40bf55: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40bf5a: e8 b1 9c ff ff callq 405c10 <__gettext_free_exp> + 40bf5f: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40bf64: e9 c6 f1 ff ff jmpq 40b12f + 40bf69: 48 8b 78 18 mov 0x18(%rax),%rdi + 40bf6d: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40bf72: e8 99 9c ff ff callq 405c10 <__gettext_free_exp> + 40bf77: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40bf7c: 48 8b 78 10 mov 0x10(%rax),%rdi + 40bf80: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40bf85: e8 86 9c ff ff callq 405c10 <__gettext_free_exp> + 40bf8a: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40bf8f: 48 8b 78 08 mov 0x8(%rax),%rdi + 40bf93: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40bf98: e8 73 9c ff ff callq 405c10 <__gettext_free_exp> + 40bf9d: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40bfa2: e9 68 f0 ff ff jmpq 40b00f + 40bfa7: 48 8b 78 18 mov 0x18(%rax),%rdi + 40bfab: 48 89 04 24 mov %rax,(%rsp) + 40bfaf: e8 5c 9c ff ff callq 405c10 <__gettext_free_exp> + 40bfb4: 48 8b 04 24 mov (%rsp),%rax + 40bfb8: 48 8b 78 10 mov 0x10(%rax),%rdi + 40bfbc: 48 89 04 24 mov %rax,(%rsp) + 40bfc0: e8 4b 9c ff ff callq 405c10 <__gettext_free_exp> + 40bfc5: 48 8b 04 24 mov (%rsp),%rax + 40bfc9: 48 8b 50 08 mov 0x8(%rax),%rdx + 40bfcd: 48 85 d2 test %rdx,%rdx + 40bfd0: 0f 84 91 dd ff ff je 409d67 + 40bfd6: 8b 0a mov (%rdx),%ecx + 40bfd8: 83 f9 02 cmp $0x2,%ecx + 40bfdb: 0f 84 be 00 00 00 je 40c09f + 40bfe1: 83 f9 03 cmp $0x3,%ecx + 40bfe4: 0f 84 9a 00 00 00 je 40c084 + 40bfea: 83 f9 01 cmp $0x1,%ecx + 40bfed: 0f 84 c7 00 00 00 je 40c0ba + 40bff3: 48 89 d7 mov %rdx,%rdi + 40bff6: 48 89 04 24 mov %rax,(%rsp) + 40bffa: e8 b1 1d 01 00 callq 41ddb0 <__cfree> + 40bfff: 48 8b 04 24 mov (%rsp),%rax + 40c003: e9 5f dd ff ff jmpq 409d67 + 40c008: 48 8b 78 18 mov 0x18(%rax),%rdi + 40c00c: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c011: e8 fa 9b ff ff callq 405c10 <__gettext_free_exp> + 40c016: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c01b: 48 8b 78 10 mov 0x10(%rax),%rdi + 40c01f: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c024: e8 e7 9b ff ff callq 405c10 <__gettext_free_exp> + 40c029: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c02e: 48 8b 78 08 mov 0x8(%rax),%rdi + 40c032: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c037: e8 d4 9b ff ff callq 405c10 <__gettext_free_exp> + 40c03c: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c041: e9 49 f9 ff ff jmpq 40b98f + 40c046: 48 8b 78 18 mov 0x18(%rax),%rdi + 40c04a: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c04f: e8 bc 9b ff ff callq 405c10 <__gettext_free_exp> + 40c054: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c059: 48 8b 78 10 mov 0x10(%rax),%rdi + 40c05d: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c062: e8 a9 9b ff ff callq 405c10 <__gettext_free_exp> + 40c067: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c06c: 48 8b 78 08 mov 0x8(%rax),%rdi + 40c070: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c075: e8 96 9b ff ff callq 405c10 <__gettext_free_exp> + 40c07a: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c07f: e9 17 f8 ff ff jmpq 40b89b + 40c084: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 40c088: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c08d: 48 89 14 24 mov %rdx,(%rsp) + 40c091: e8 7a 9b ff ff callq 405c10 <__gettext_free_exp> + 40c096: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c09b: 48 8b 14 24 mov (%rsp),%rdx + 40c09f: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 40c0a3: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c0a8: 48 89 14 24 mov %rdx,(%rsp) + 40c0ac: e8 5f 9b ff ff callq 405c10 <__gettext_free_exp> + 40c0b1: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c0b6: 48 8b 14 24 mov (%rsp),%rdx + 40c0ba: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 40c0be: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c0c3: 48 89 14 24 mov %rdx,(%rsp) + 40c0c7: e8 44 9b ff ff callq 405c10 <__gettext_free_exp> + 40c0cc: 48 8b 14 24 mov (%rsp),%rdx + 40c0d0: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c0d5: 48 89 d7 mov %rdx,%rdi + 40c0d8: 48 89 04 24 mov %rax,(%rsp) + 40c0dc: e8 cf 1c 01 00 callq 41ddb0 <__cfree> + 40c0e1: 48 8b 04 24 mov (%rsp),%rax + 40c0e5: e9 7d dc ff ff jmpq 409d67 + 40c0ea: 48 8b 78 18 mov 0x18(%rax),%rdi + 40c0ee: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c0f3: e8 18 9b ff ff callq 405c10 <__gettext_free_exp> + 40c0f8: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c0fd: 48 8b 78 10 mov 0x10(%rax),%rdi + 40c101: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c106: e8 05 9b ff ff callq 405c10 <__gettext_free_exp> + 40c10b: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c110: 48 8b 78 08 mov 0x8(%rax),%rdi + 40c114: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c119: e8 f2 9a ff ff callq 405c10 <__gettext_free_exp> + 40c11e: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c123: e9 ed f7 ff ff jmpq 40b915 + 40c128: 48 8b 78 18 mov 0x18(%rax),%rdi + 40c12c: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c131: e8 da 9a ff ff callq 405c10 <__gettext_free_exp> + 40c136: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c13b: 48 8b 78 10 mov 0x10(%rax),%rdi + 40c13f: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c144: e8 c7 9a ff ff callq 405c10 <__gettext_free_exp> + 40c149: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c14e: 48 8b 78 08 mov 0x8(%rax),%rdi + 40c152: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c157: e8 b4 9a ff ff callq 405c10 <__gettext_free_exp> + 40c15c: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c161: e9 a3 f8 ff ff jmpq 40ba09 + 40c166: 49 8b 7f 18 mov 0x18(%r15),%rdi + 40c16a: e8 a1 9a ff ff callq 405c10 <__gettext_free_exp> + 40c16f: 49 8b 7f 10 mov 0x10(%r15),%rdi + 40c173: e8 98 9a ff ff callq 405c10 <__gettext_free_exp> + 40c178: 49 8b 7f 08 mov 0x8(%r15),%rdi + 40c17c: e8 8f 9a ff ff callq 405c10 <__gettext_free_exp> + 40c181: e9 f6 f8 ff ff jmpq 40ba7c + 40c186: 48 8b 78 18 mov 0x18(%rax),%rdi + 40c18a: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c18f: e8 7c 9a ff ff callq 405c10 <__gettext_free_exp> + 40c194: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c199: 48 8b 78 10 mov 0x10(%rax),%rdi + 40c19d: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c1a2: e8 69 9a ff ff callq 405c10 <__gettext_free_exp> + 40c1a7: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c1ac: 48 8b 78 08 mov 0x8(%rax),%rdi + 40c1b0: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c1b5: e8 56 9a ff ff callq 405c10 <__gettext_free_exp> + 40c1ba: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c1bf: e9 20 f0 ff ff jmpq 40b1e4 + 40c1c4: 48 8b 78 18 mov 0x18(%rax),%rdi + 40c1c8: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c1cd: e8 3e 9a ff ff callq 405c10 <__gettext_free_exp> + 40c1d2: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c1d7: 48 8b 78 10 mov 0x10(%rax),%rdi + 40c1db: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c1e0: e8 2b 9a ff ff callq 405c10 <__gettext_free_exp> + 40c1e5: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c1ea: 48 8b 78 08 mov 0x8(%rax),%rdi + 40c1ee: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c1f3: e8 18 9a ff ff callq 405c10 <__gettext_free_exp> + 40c1f8: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c1fd: e9 50 f1 ff ff jmpq 40b352 + 40c202: 48 8b 78 18 mov 0x18(%rax),%rdi + 40c206: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c20b: e8 00 9a ff ff callq 405c10 <__gettext_free_exp> + 40c210: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c215: 48 8b 78 10 mov 0x10(%rax),%rdi + 40c219: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c21e: e8 ed 99 ff ff callq 405c10 <__gettext_free_exp> + 40c223: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c228: 48 8b 78 08 mov 0x8(%rax),%rdi + 40c22c: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c231: e8 da 99 ff ff callq 405c10 <__gettext_free_exp> + 40c236: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c23b: e9 1e f0 ff ff jmpq 40b25e + 40c240: 48 8b 78 18 mov 0x18(%rax),%rdi + 40c244: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c249: e8 c2 99 ff ff callq 405c10 <__gettext_free_exp> + 40c24e: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c253: 48 8b 78 10 mov 0x10(%rax),%rdi + 40c257: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c25c: e8 af 99 ff ff callq 405c10 <__gettext_free_exp> + 40c261: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c266: 48 8b 78 08 mov 0x8(%rax),%rdi + 40c26a: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c26f: e8 9c 99 ff ff callq 405c10 <__gettext_free_exp> + 40c274: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c279: e9 5a f0 ff ff jmpq 40b2d8 + 40c27e: 48 8b 78 18 mov 0x18(%rax),%rdi + 40c282: 48 89 04 24 mov %rax,(%rsp) + 40c286: e8 85 99 ff ff callq 405c10 <__gettext_free_exp> + 40c28b: 48 8b 04 24 mov (%rsp),%rax + 40c28f: 48 8b 78 10 mov 0x10(%rax),%rdi + 40c293: 48 89 04 24 mov %rax,(%rsp) + 40c297: e8 74 99 ff ff callq 405c10 <__gettext_free_exp> + 40c29c: 48 8b 04 24 mov (%rsp),%rax + 40c2a0: 48 8b 50 08 mov 0x8(%rax),%rdx + 40c2a4: 48 85 d2 test %rdx,%rdx + 40c2a7: 0f 84 ef f1 ff ff je 40b49c + 40c2ad: 8b 0a mov (%rdx),%ecx + 40c2af: 83 f9 02 cmp $0x2,%ecx + 40c2b2: 0f 84 1d 0b 00 00 je 40cdd5 + 40c2b8: 83 f9 03 cmp $0x3,%ecx + 40c2bb: 0f 84 f9 0a 00 00 je 40cdba + 40c2c1: 83 f9 01 cmp $0x1,%ecx + 40c2c4: 0f 84 26 0b 00 00 je 40cdf0 + 40c2ca: 48 89 d7 mov %rdx,%rdi + 40c2cd: 48 89 04 24 mov %rax,(%rsp) + 40c2d1: e8 da 1a 01 00 callq 41ddb0 <__cfree> + 40c2d6: 48 8b 04 24 mov (%rsp),%rax + 40c2da: e9 bd f1 ff ff jmpq 40b49c + 40c2df: 48 8b 78 18 mov 0x18(%rax),%rdi + 40c2e3: 48 89 04 24 mov %rax,(%rsp) + 40c2e7: e8 24 99 ff ff callq 405c10 <__gettext_free_exp> + 40c2ec: 48 8b 04 24 mov (%rsp),%rax + 40c2f0: 48 8b 78 10 mov 0x10(%rax),%rdi + 40c2f4: 48 89 04 24 mov %rax,(%rsp) + 40c2f8: e8 13 99 ff ff callq 405c10 <__gettext_free_exp> + 40c2fd: 48 8b 04 24 mov (%rsp),%rax + 40c301: 48 8b 50 08 mov 0x8(%rax),%rdx + 40c305: 48 85 d2 test %rdx,%rdx + 40c308: 0f 84 6a f2 ff ff je 40b578 + 40c30e: 8b 0a mov (%rdx),%ecx + 40c310: 83 f9 02 cmp $0x2,%ecx + 40c313: 0f 84 de 05 00 00 je 40c8f7 + 40c319: 83 f9 03 cmp $0x3,%ecx + 40c31c: 0f 84 ba 05 00 00 je 40c8dc + 40c322: 83 f9 01 cmp $0x1,%ecx + 40c325: 0f 84 e7 05 00 00 je 40c912 + 40c32b: 48 89 d7 mov %rdx,%rdi + 40c32e: 48 89 04 24 mov %rax,(%rsp) + 40c332: e8 79 1a 01 00 callq 41ddb0 <__cfree> + 40c337: 48 8b 04 24 mov (%rsp),%rax + 40c33b: e9 38 f2 ff ff jmpq 40b578 + 40c340: 48 8b 78 18 mov 0x18(%rax),%rdi + 40c344: 48 89 04 24 mov %rax,(%rsp) + 40c348: e8 c3 98 ff ff callq 405c10 <__gettext_free_exp> + 40c34d: 48 8b 04 24 mov (%rsp),%rax + 40c351: 48 8b 78 10 mov 0x10(%rax),%rdi + 40c355: 48 89 04 24 mov %rax,(%rsp) + 40c359: e8 b2 98 ff ff callq 405c10 <__gettext_free_exp> + 40c35e: 48 8b 04 24 mov (%rsp),%rax + 40c362: 48 8b 50 08 mov 0x8(%rax),%rdx + 40c366: 48 85 d2 test %rdx,%rdx + 40c369: 0f 84 bf f0 ff ff je 40b42e + 40c36f: 8b 0a mov (%rdx),%ecx + 40c371: 83 f9 02 cmp $0x2,%ecx + 40c374: 0f 84 d1 04 00 00 je 40c84b + 40c37a: 83 f9 03 cmp $0x3,%ecx + 40c37d: 0f 84 ad 04 00 00 je 40c830 + 40c383: 83 f9 01 cmp $0x1,%ecx + 40c386: 0f 84 da 04 00 00 je 40c866 + 40c38c: 48 89 d7 mov %rdx,%rdi + 40c38f: 48 89 04 24 mov %rax,(%rsp) + 40c393: e8 18 1a 01 00 callq 41ddb0 <__cfree> + 40c398: 48 8b 04 24 mov (%rsp),%rax + 40c39c: e9 8d f0 ff ff jmpq 40b42e + 40c3a1: 48 8b 78 18 mov 0x18(%rax),%rdi + 40c3a5: 48 89 04 24 mov %rax,(%rsp) + 40c3a9: e8 62 98 ff ff callq 405c10 <__gettext_free_exp> + 40c3ae: 48 8b 04 24 mov (%rsp),%rax + 40c3b2: 48 8b 78 10 mov 0x10(%rax),%rdi + 40c3b6: 48 89 04 24 mov %rax,(%rsp) + 40c3ba: e8 51 98 ff ff callq 405c10 <__gettext_free_exp> + 40c3bf: 48 8b 04 24 mov (%rsp),%rax + 40c3c3: 48 8b 50 08 mov 0x8(%rax),%rdx + 40c3c7: 48 85 d2 test %rdx,%rdx + 40c3ca: 0f 84 f0 ef ff ff je 40b3c0 + 40c3d0: 8b 0a mov (%rdx),%ecx + 40c3d2: 83 f9 02 cmp $0x2,%ecx + 40c3d5: 0f 84 3c 07 00 00 je 40cb17 + 40c3db: 83 f9 03 cmp $0x3,%ecx + 40c3de: 0f 84 18 07 00 00 je 40cafc + 40c3e4: 83 f9 01 cmp $0x1,%ecx + 40c3e7: 0f 84 45 07 00 00 je 40cb32 + 40c3ed: 48 89 d7 mov %rdx,%rdi + 40c3f0: 48 89 04 24 mov %rax,(%rsp) + 40c3f4: e8 b7 19 01 00 callq 41ddb0 <__cfree> + 40c3f9: 48 8b 04 24 mov (%rsp),%rax + 40c3fd: e9 be ef ff ff jmpq 40b3c0 + 40c402: 48 8b 78 18 mov 0x18(%rax),%rdi + 40c406: 48 89 04 24 mov %rax,(%rsp) + 40c40a: e8 01 98 ff ff callq 405c10 <__gettext_free_exp> + 40c40f: 48 8b 04 24 mov (%rsp),%rax + 40c413: 48 8b 78 10 mov 0x10(%rax),%rdi + 40c417: 48 89 04 24 mov %rax,(%rsp) + 40c41b: e8 f0 97 ff ff callq 405c10 <__gettext_free_exp> + 40c420: 48 8b 04 24 mov (%rsp),%rax + 40c424: 48 8b 50 08 mov 0x8(%rax),%rdx + 40c428: 48 85 d2 test %rdx,%rdx + 40c42b: 0f 84 d9 f0 ff ff je 40b50a + 40c431: 8b 0a mov (%rdx),%ecx + 40c433: 83 f9 02 cmp $0x2,%ecx + 40c436: 0f 84 ad 07 00 00 je 40cbe9 + 40c43c: 83 f9 03 cmp $0x3,%ecx + 40c43f: 0f 84 89 07 00 00 je 40cbce + 40c445: 83 f9 01 cmp $0x1,%ecx + 40c448: 0f 84 b6 07 00 00 je 40cc04 + 40c44e: 48 89 d7 mov %rdx,%rdi + 40c451: 48 89 04 24 mov %rax,(%rsp) + 40c455: e8 56 19 01 00 callq 41ddb0 <__cfree> + 40c45a: 48 8b 04 24 mov (%rsp),%rax + 40c45e: e9 a7 f0 ff ff jmpq 40b50a + 40c463: 48 8b 78 18 mov 0x18(%rax),%rdi + 40c467: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c46c: e8 9f 97 ff ff callq 405c10 <__gettext_free_exp> + 40c471: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c476: 48 8b 78 10 mov 0x10(%rax),%rdi + 40c47a: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c47f: e8 8c 97 ff ff callq 405c10 <__gettext_free_exp> + 40c484: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c489: 48 8b 78 08 mov 0x8(%rax),%rdi + 40c48d: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c492: e8 79 97 ff ff callq 405c10 <__gettext_free_exp> + 40c497: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c49c: 48 89 c7 mov %rax,%rdi + 40c49f: e8 0c 19 01 00 callq 41ddb0 <__cfree> + 40c4a4: 48 8b 04 24 mov (%rsp),%rax + 40c4a8: 48 8b 40 08 mov 0x8(%rax),%rax + 40c4ac: 48 85 c0 test %rax,%rax + 40c4af: 0f 84 35 f1 ff ff je 40b5ea + 40c4b5: 8b 10 mov (%rax),%edx + 40c4b7: 83 fa 02 cmp $0x2,%edx + 40c4ba: 0f 84 57 05 00 00 je 40ca17 + 40c4c0: 83 fa 03 cmp $0x3,%edx + 40c4c3: 0f 84 3b 05 00 00 je 40ca04 + 40c4c9: 83 fa 01 cmp $0x1,%edx + 40c4cc: 0f 84 58 05 00 00 je 40ca2a + 40c4d2: 48 89 c7 mov %rax,%rdi + 40c4d5: e8 d6 18 01 00 callq 41ddb0 <__cfree> + 40c4da: e9 0b f1 ff ff jmpq 40b5ea + 40c4df: 48 8b 78 18 mov 0x18(%rax),%rdi + 40c4e3: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c4e8: e8 23 97 ff ff callq 405c10 <__gettext_free_exp> + 40c4ed: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c4f2: 48 8b 78 10 mov 0x10(%rax),%rdi + 40c4f6: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c4fb: e8 10 97 ff ff callq 405c10 <__gettext_free_exp> + 40c500: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c505: 48 8b 78 08 mov 0x8(%rax),%rdi + 40c509: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c50e: e8 fd 96 ff ff callq 405c10 <__gettext_free_exp> + 40c513: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c518: e9 2e f4 ff ff jmpq 40b94b + 40c51d: 48 8b 78 18 mov 0x18(%rax),%rdi + 40c521: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c526: e8 e5 96 ff ff callq 405c10 <__gettext_free_exp> + 40c52b: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c530: 48 8b 78 10 mov 0x10(%rax),%rdi + 40c534: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c539: e8 d2 96 ff ff callq 405c10 <__gettext_free_exp> + 40c53e: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c543: 48 8b 78 08 mov 0x8(%rax),%rdi + 40c547: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c54c: e8 bf 96 ff ff callq 405c10 <__gettext_free_exp> + 40c551: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c556: e9 6a f4 ff ff jmpq 40b9c5 + 40c55b: 48 8b 78 18 mov 0x18(%rax),%rdi + 40c55f: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c564: e8 a7 96 ff ff callq 405c10 <__gettext_free_exp> + 40c569: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c56e: 48 8b 78 10 mov 0x10(%rax),%rdi + 40c572: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c577: e8 94 96 ff ff callq 405c10 <__gettext_free_exp> + 40c57c: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c581: 48 8b 78 08 mov 0x8(%rax),%rdi + 40c585: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c58a: e8 81 96 ff ff callq 405c10 <__gettext_free_exp> + 40c58f: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c594: e9 a6 f4 ff ff jmpq 40ba3f + 40c599: 48 8b 78 18 mov 0x18(%rax),%rdi + 40c59d: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c5a2: e8 69 96 ff ff callq 405c10 <__gettext_free_exp> + 40c5a7: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c5ac: 48 8b 78 10 mov 0x10(%rax),%rdi + 40c5b0: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c5b5: e8 56 96 ff ff callq 405c10 <__gettext_free_exp> + 40c5ba: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c5bf: 48 8b 78 08 mov 0x8(%rax),%rdi + 40c5c3: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c5c8: e8 43 96 ff ff callq 405c10 <__gettext_free_exp> + 40c5cd: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c5d2: e9 fa f2 ff ff jmpq 40b8d1 + 40c5d7: 49 8b 7f 18 mov 0x18(%r15),%rdi + 40c5db: e8 30 96 ff ff callq 405c10 <__gettext_free_exp> + 40c5e0: 49 8b 7f 10 mov 0x10(%r15),%rdi + 40c5e4: e8 27 96 ff ff callq 405c10 <__gettext_free_exp> + 40c5e9: 49 8b 47 08 mov 0x8(%r15),%rax + 40c5ed: 48 85 c0 test %rax,%rax + 40c5f0: 0f 84 51 e2 ff ff je 40a847 + 40c5f6: 8b 10 mov (%rax),%edx + 40c5f8: 83 fa 02 cmp $0x2,%edx + 40c5fb: 74 28 je 40c625 + 40c5fd: 83 fa 03 cmp $0x3,%edx + 40c600: 74 12 je 40c614 + 40c602: 83 fa 01 cmp $0x1,%edx + 40c605: 74 2f je 40c636 + 40c607: 48 89 c7 mov %rax,%rdi + 40c60a: e8 a1 17 01 00 callq 41ddb0 <__cfree> + 40c60f: e9 33 e2 ff ff jmpq 40a847 + 40c614: 48 8b 78 18 mov 0x18(%rax),%rdi + 40c618: 48 89 04 24 mov %rax,(%rsp) + 40c61c: e8 ef 95 ff ff callq 405c10 <__gettext_free_exp> + 40c621: 48 8b 04 24 mov (%rsp),%rax + 40c625: 48 8b 78 10 mov 0x10(%rax),%rdi + 40c629: 48 89 04 24 mov %rax,(%rsp) + 40c62d: e8 de 95 ff ff callq 405c10 <__gettext_free_exp> + 40c632: 48 8b 04 24 mov (%rsp),%rax + 40c636: 48 8b 78 08 mov 0x8(%rax),%rdi + 40c63a: 48 89 04 24 mov %rax,(%rsp) + 40c63e: e8 cd 95 ff ff callq 405c10 <__gettext_free_exp> + 40c643: 48 8b 04 24 mov (%rsp),%rax + 40c647: eb be jmp 40c607 + 40c649: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 40c650: 49 8b 47 18 mov 0x18(%r15),%rax + 40c654: 48 85 c0 test %rax,%rax + 40c657: 0f 84 8c e2 ff ff je 40a8e9 + 40c65d: 8b 10 mov (%rax),%edx + 40c65f: 83 fa 02 cmp $0x2,%edx + 40c662: 0f 84 57 e2 ff ff je 40a8bf + 40c668: 83 fa 03 cmp $0x3,%edx + 40c66b: 0f 84 3d e2 ff ff je 40a8ae + 40c671: 83 fa 01 cmp $0x1,%edx + 40c674: 0f 85 67 e2 ff ff jne 40a8e1 + 40c67a: e9 51 e2 ff ff jmpq 40a8d0 + 40c67f: 90 nop + 40c680: 49 8b 47 18 mov 0x18(%r15),%rax + 40c684: 48 85 c0 test %rax,%rax + 40c687: 0f 84 5c db ff ff je 40a1e9 + 40c68d: 8b 10 mov (%rax),%edx + 40c68f: 83 fa 02 cmp $0x2,%edx + 40c692: 0f 84 27 db ff ff je 40a1bf + 40c698: 83 fa 03 cmp $0x3,%edx + 40c69b: 0f 84 0d db ff ff je 40a1ae + 40c6a1: 83 fa 01 cmp $0x1,%edx + 40c6a4: 0f 85 37 db ff ff jne 40a1e1 + 40c6aa: e9 21 db ff ff jmpq 40a1d0 + 40c6af: 90 nop + 40c6b0: 49 8b 47 18 mov 0x18(%r15),%rax + 40c6b4: 48 85 c0 test %rax,%rax + 40c6b7: 0f 84 6c e3 ff ff je 40aa29 + 40c6bd: 8b 10 mov (%rax),%edx + 40c6bf: 83 fa 02 cmp $0x2,%edx + 40c6c2: 0f 84 37 e3 ff ff je 40a9ff + 40c6c8: 83 fa 03 cmp $0x3,%edx + 40c6cb: 0f 84 1d e3 ff ff je 40a9ee + 40c6d1: 83 fa 01 cmp $0x1,%edx + 40c6d4: 0f 85 47 e3 ff ff jne 40aa21 + 40c6da: e9 31 e3 ff ff jmpq 40aa10 + 40c6df: 49 8b 7f 18 mov 0x18(%r15),%rdi + 40c6e3: e8 28 95 ff ff callq 405c10 <__gettext_free_exp> + 40c6e8: 49 8b 7f 10 mov 0x10(%r15),%rdi + 40c6ec: e8 1f 95 ff ff callq 405c10 <__gettext_free_exp> + 40c6f1: 49 8b 47 08 mov 0x8(%r15),%rax + 40c6f5: 48 85 c0 test %rax,%rax + 40c6f8: 0f 84 89 e2 ff ff je 40a987 + 40c6fe: 8b 10 mov (%rax),%edx + 40c700: 83 fa 02 cmp $0x2,%edx + 40c703: 74 28 je 40c72d + 40c705: 83 fa 03 cmp $0x3,%edx + 40c708: 74 12 je 40c71c + 40c70a: 83 fa 01 cmp $0x1,%edx + 40c70d: 74 2f je 40c73e + 40c70f: 48 89 c7 mov %rax,%rdi + 40c712: e8 99 16 01 00 callq 41ddb0 <__cfree> + 40c717: e9 6b e2 ff ff jmpq 40a987 + 40c71c: 48 8b 78 18 mov 0x18(%rax),%rdi + 40c720: 48 89 04 24 mov %rax,(%rsp) + 40c724: e8 e7 94 ff ff callq 405c10 <__gettext_free_exp> + 40c729: 48 8b 04 24 mov (%rsp),%rax + 40c72d: 48 8b 78 10 mov 0x10(%rax),%rdi + 40c731: 48 89 04 24 mov %rax,(%rsp) + 40c735: e8 d6 94 ff ff callq 405c10 <__gettext_free_exp> + 40c73a: 48 8b 04 24 mov (%rsp),%rax + 40c73e: 48 8b 78 08 mov 0x8(%rax),%rdi + 40c742: 48 89 04 24 mov %rax,(%rsp) + 40c746: e8 c5 94 ff ff callq 405c10 <__gettext_free_exp> + 40c74b: 48 8b 04 24 mov (%rsp),%rax + 40c74f: eb be jmp 40c70f + 40c751: 49 8b 7f 18 mov 0x18(%r15),%rdi + 40c755: e8 b6 94 ff ff callq 405c10 <__gettext_free_exp> + 40c75a: 49 8b 7f 10 mov 0x10(%r15),%rdi + 40c75e: e8 ad 94 ff ff callq 405c10 <__gettext_free_exp> + 40c763: 49 8b 47 08 mov 0x8(%r15),%rax + 40c767: 48 85 c0 test %rax,%rax + 40c76a: 0f 84 3f f3 ff ff je 40baaf + 40c770: 8b 10 mov (%rax),%edx + 40c772: 83 fa 02 cmp $0x2,%edx + 40c775: 74 28 je 40c79f + 40c777: 83 fa 03 cmp $0x3,%edx + 40c77a: 74 12 je 40c78e + 40c77c: 83 fa 01 cmp $0x1,%edx + 40c77f: 74 2f je 40c7b0 + 40c781: 48 89 c7 mov %rax,%rdi + 40c784: e8 27 16 01 00 callq 41ddb0 <__cfree> + 40c789: e9 21 f3 ff ff jmpq 40baaf + 40c78e: 48 8b 78 18 mov 0x18(%rax),%rdi + 40c792: 48 89 04 24 mov %rax,(%rsp) + 40c796: e8 75 94 ff ff callq 405c10 <__gettext_free_exp> + 40c79b: 48 8b 04 24 mov (%rsp),%rax + 40c79f: 48 8b 78 10 mov 0x10(%rax),%rdi + 40c7a3: 48 89 04 24 mov %rax,(%rsp) + 40c7a7: e8 64 94 ff ff callq 405c10 <__gettext_free_exp> + 40c7ac: 48 8b 04 24 mov (%rsp),%rax + 40c7b0: 48 8b 78 08 mov 0x8(%rax),%rdi + 40c7b4: 48 89 04 24 mov %rax,(%rsp) + 40c7b8: e8 53 94 ff ff callq 405c10 <__gettext_free_exp> + 40c7bd: 48 8b 04 24 mov (%rsp),%rax + 40c7c1: eb be jmp 40c781 + 40c7c3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 40c7c8: 4d 8b 7e 18 mov 0x18(%r14),%r15 + 40c7cc: 4d 85 ff test %r15,%r15 + 40c7cf: 0f 84 66 dc ff ff je 40a43b + 40c7d5: 41 8b 07 mov (%r15),%eax + 40c7d8: 83 f8 02 cmp $0x2,%eax + 40c7db: 0f 84 40 dc ff ff je 40a421 + 40c7e1: 83 f8 03 cmp $0x3,%eax + 40c7e4: 0f 84 2e dc ff ff je 40a418 + 40c7ea: 83 f8 01 cmp $0x1,%eax + 40c7ed: 0f 85 40 dc ff ff jne 40a433 + 40c7f3: e9 32 dc ff ff jmpq 40a42a + 40c7f8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 40c7ff: 00 + 40c800: 4d 8b 7e 18 mov 0x18(%r14),%r15 + 40c804: 4d 85 ff test %r15,%r15 + 40c807: 0f 84 6f d6 ff ff je 409e7c + 40c80d: 41 8b 07 mov (%r15),%eax + 40c810: 83 f8 02 cmp $0x2,%eax + 40c813: 0f 84 49 d6 ff ff je 409e62 + 40c819: 83 f8 03 cmp $0x3,%eax + 40c81c: 0f 84 37 d6 ff ff je 409e59 + 40c822: 83 f8 01 cmp $0x1,%eax + 40c825: 0f 85 49 d6 ff ff jne 409e74 + 40c82b: e9 3b d6 ff ff jmpq 409e6b + 40c830: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 40c834: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c839: 48 89 14 24 mov %rdx,(%rsp) + 40c83d: e8 ce 93 ff ff callq 405c10 <__gettext_free_exp> + 40c842: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c847: 48 8b 14 24 mov (%rsp),%rdx + 40c84b: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 40c84f: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c854: 48 89 14 24 mov %rdx,(%rsp) + 40c858: e8 b3 93 ff ff callq 405c10 <__gettext_free_exp> + 40c85d: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c862: 48 8b 14 24 mov (%rsp),%rdx + 40c866: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 40c86a: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c86f: 48 89 14 24 mov %rdx,(%rsp) + 40c873: e8 98 93 ff ff callq 405c10 <__gettext_free_exp> + 40c878: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c87d: 48 8b 14 24 mov (%rsp),%rdx + 40c881: e9 06 fb ff ff jmpq 40c38c + 40c886: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 40c88a: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c88f: 48 89 14 24 mov %rdx,(%rsp) + 40c893: e8 78 93 ff ff callq 405c10 <__gettext_free_exp> + 40c898: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c89d: 48 8b 14 24 mov (%rsp),%rdx + 40c8a1: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 40c8a5: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c8aa: 48 89 14 24 mov %rdx,(%rsp) + 40c8ae: e8 5d 93 ff ff callq 405c10 <__gettext_free_exp> + 40c8b3: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c8b8: 48 8b 14 24 mov (%rsp),%rdx + 40c8bc: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 40c8c0: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c8c5: 48 89 14 24 mov %rdx,(%rsp) + 40c8c9: e8 42 93 ff ff callq 405c10 <__gettext_free_exp> + 40c8ce: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c8d3: 48 8b 14 24 mov (%rsp),%rdx + 40c8d7: e9 44 f3 ff ff jmpq 40bc20 + 40c8dc: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 40c8e0: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c8e5: 48 89 14 24 mov %rdx,(%rsp) + 40c8e9: e8 22 93 ff ff callq 405c10 <__gettext_free_exp> + 40c8ee: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c8f3: 48 8b 14 24 mov (%rsp),%rdx + 40c8f7: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 40c8fb: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c900: 48 89 14 24 mov %rdx,(%rsp) + 40c904: e8 07 93 ff ff callq 405c10 <__gettext_free_exp> + 40c909: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c90e: 48 8b 14 24 mov (%rsp),%rdx + 40c912: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 40c916: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c91b: 48 89 14 24 mov %rdx,(%rsp) + 40c91f: e8 ec 92 ff ff callq 405c10 <__gettext_free_exp> + 40c924: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c929: 48 8b 14 24 mov (%rsp),%rdx + 40c92d: e9 f9 f9 ff ff jmpq 40c32b + 40c932: 48 8b 78 18 mov 0x18(%rax),%rdi + 40c936: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c93b: e8 d0 92 ff ff callq 405c10 <__gettext_free_exp> + 40c940: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c945: 48 8b 78 10 mov 0x10(%rax),%rdi + 40c949: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c94e: e8 bd 92 ff ff callq 405c10 <__gettext_free_exp> + 40c953: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c958: 48 8b 78 08 mov 0x8(%rax),%rdi + 40c95c: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c961: e8 aa 92 ff ff callq 405c10 <__gettext_free_exp> + 40c966: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c96b: e9 b8 e8 ff ff jmpq 40b228 + 40c970: 48 8b 78 18 mov 0x18(%rax),%rdi + 40c974: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c979: e8 92 92 ff ff callq 405c10 <__gettext_free_exp> + 40c97e: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c983: 48 8b 78 10 mov 0x10(%rax),%rdi + 40c987: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c98c: e8 7f 92 ff ff callq 405c10 <__gettext_free_exp> + 40c991: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c996: 48 8b 78 08 mov 0x8(%rax),%rdi + 40c99a: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c99f: e8 6c 92 ff ff callq 405c10 <__gettext_free_exp> + 40c9a4: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c9a9: e9 bc e3 ff ff jmpq 40ad6a + 40c9ae: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 40c9b2: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c9b7: 48 89 14 24 mov %rdx,(%rsp) + 40c9bb: e8 50 92 ff ff callq 405c10 <__gettext_free_exp> + 40c9c0: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c9c5: 48 8b 14 24 mov (%rsp),%rdx + 40c9c9: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 40c9cd: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c9d2: 48 89 14 24 mov %rdx,(%rsp) + 40c9d6: e8 35 92 ff ff callq 405c10 <__gettext_free_exp> + 40c9db: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c9e0: 48 8b 14 24 mov (%rsp),%rdx + 40c9e4: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 40c9e8: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40c9ed: 48 89 14 24 mov %rdx,(%rsp) + 40c9f1: e8 1a 92 ff ff callq 405c10 <__gettext_free_exp> + 40c9f6: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40c9fb: 48 8b 14 24 mov (%rsp),%rdx + 40c9ff: e9 de f2 ff ff jmpq 40bce2 + 40ca04: 48 8b 78 18 mov 0x18(%rax),%rdi + 40ca08: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40ca0d: e8 fe 91 ff ff callq 405c10 <__gettext_free_exp> + 40ca12: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40ca17: 48 8b 78 10 mov 0x10(%rax),%rdi + 40ca1b: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40ca20: e8 eb 91 ff ff callq 405c10 <__gettext_free_exp> + 40ca25: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40ca2a: 48 8b 78 08 mov 0x8(%rax),%rdi + 40ca2e: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40ca33: e8 d8 91 ff ff callq 405c10 <__gettext_free_exp> + 40ca38: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40ca3d: e9 90 fa ff ff jmpq 40c4d2 + 40ca42: 48 8b 78 18 mov 0x18(%rax),%rdi + 40ca46: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40ca4b: e8 c0 91 ff ff callq 405c10 <__gettext_free_exp> + 40ca50: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40ca55: 48 8b 78 10 mov 0x10(%rax),%rdi + 40ca59: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40ca5e: e8 ad 91 ff ff callq 405c10 <__gettext_free_exp> + 40ca63: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40ca68: 48 8b 78 08 mov 0x8(%rax),%rdi + 40ca6c: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40ca71: e8 9a 91 ff ff callq 405c10 <__gettext_free_exp> + 40ca76: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40ca7b: e9 2e e7 ff ff jmpq 40b1ae + 40ca80: 48 8b 78 18 mov 0x18(%rax),%rdi + 40ca84: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40ca89: e8 82 91 ff ff callq 405c10 <__gettext_free_exp> + 40ca8e: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40ca93: 48 8b 78 10 mov 0x10(%rax),%rdi + 40ca97: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40ca9c: e8 6f 91 ff ff callq 405c10 <__gettext_free_exp> + 40caa1: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40caa6: 48 8b 78 08 mov 0x8(%rax),%rdi + 40caaa: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40caaf: e8 5c 91 ff ff callq 405c10 <__gettext_free_exp> + 40cab4: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40cab9: e9 cc e1 ff ff jmpq 40ac8a + 40cabe: 48 8b 78 18 mov 0x18(%rax),%rdi + 40cac2: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40cac7: e8 44 91 ff ff callq 405c10 <__gettext_free_exp> + 40cacc: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40cad1: 48 8b 78 10 mov 0x10(%rax),%rdi + 40cad5: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40cada: e8 31 91 ff ff callq 405c10 <__gettext_free_exp> + 40cadf: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40cae4: 48 8b 78 08 mov 0x8(%rax),%rdi + 40cae8: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40caed: e8 1e 91 ff ff callq 405c10 <__gettext_free_exp> + 40caf2: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40caf7: e9 ae e0 ff ff jmpq 40abaa + 40cafc: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 40cb00: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40cb05: 48 89 14 24 mov %rdx,(%rsp) + 40cb09: e8 02 91 ff ff callq 405c10 <__gettext_free_exp> + 40cb0e: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40cb13: 48 8b 14 24 mov (%rsp),%rdx + 40cb17: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 40cb1b: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40cb20: 48 89 14 24 mov %rdx,(%rsp) + 40cb24: e8 e7 90 ff ff callq 405c10 <__gettext_free_exp> + 40cb29: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40cb2e: 48 8b 14 24 mov (%rsp),%rdx + 40cb32: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 40cb36: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40cb3b: 48 89 14 24 mov %rdx,(%rsp) + 40cb3f: e8 cc 90 ff ff callq 405c10 <__gettext_free_exp> + 40cb44: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40cb49: 48 8b 14 24 mov (%rsp),%rdx + 40cb4d: e9 9b f8 ff ff jmpq 40c3ed + 40cb52: 48 8b 78 18 mov 0x18(%rax),%rdi + 40cb56: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40cb5b: e8 b0 90 ff ff callq 405c10 <__gettext_free_exp> + 40cb60: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40cb65: 48 8b 78 10 mov 0x10(%rax),%rdi + 40cb69: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40cb6e: e8 9d 90 ff ff callq 405c10 <__gettext_free_exp> + 40cb73: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40cb78: 48 8b 78 08 mov 0x8(%rax),%rdi + 40cb7c: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40cb81: e8 8a 90 ff ff callq 405c10 <__gettext_free_exp> + 40cb86: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40cb8b: e9 12 e7 ff ff jmpq 40b2a2 + 40cb90: 48 8b 78 18 mov 0x18(%rax),%rdi + 40cb94: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40cb99: e8 72 90 ff ff callq 405c10 <__gettext_free_exp> + 40cb9e: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40cba3: 48 8b 78 10 mov 0x10(%rax),%rdi + 40cba7: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40cbac: e8 5f 90 ff ff callq 405c10 <__gettext_free_exp> + 40cbb1: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40cbb6: 48 8b 78 08 mov 0x8(%rax),%rdi + 40cbba: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40cbbf: e8 4c 90 ff ff callq 405c10 <__gettext_free_exp> + 40cbc4: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40cbc9: e9 4e e7 ff ff jmpq 40b31c + 40cbce: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 40cbd2: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40cbd7: 48 89 14 24 mov %rdx,(%rsp) + 40cbdb: e8 30 90 ff ff callq 405c10 <__gettext_free_exp> + 40cbe0: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40cbe5: 48 8b 14 24 mov (%rsp),%rdx + 40cbe9: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 40cbed: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40cbf2: 48 89 14 24 mov %rdx,(%rsp) + 40cbf6: e8 15 90 ff ff callq 405c10 <__gettext_free_exp> + 40cbfb: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40cc00: 48 8b 14 24 mov (%rsp),%rdx + 40cc04: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 40cc08: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40cc0d: 48 89 14 24 mov %rdx,(%rsp) + 40cc11: e8 fa 8f ff ff callq 405c10 <__gettext_free_exp> + 40cc16: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40cc1b: 48 8b 14 24 mov (%rsp),%rdx + 40cc1f: e9 2a f8 ff ff jmpq 40c44e + 40cc24: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 40cc28: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40cc2d: 48 89 14 24 mov %rdx,(%rsp) + 40cc31: e8 da 8f ff ff callq 405c10 <__gettext_free_exp> + 40cc36: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40cc3b: 48 8b 14 24 mov (%rsp),%rdx + 40cc3f: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 40cc43: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40cc48: 48 89 14 24 mov %rdx,(%rsp) + 40cc4c: e8 bf 8f ff ff callq 405c10 <__gettext_free_exp> + 40cc51: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40cc56: 48 8b 14 24 mov (%rsp),%rdx + 40cc5a: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 40cc5e: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40cc63: 48 89 14 24 mov %rdx,(%rsp) + 40cc67: e8 a4 8f ff ff callq 405c10 <__gettext_free_exp> + 40cc6c: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40cc71: 48 8b 14 24 mov (%rsp),%rdx + 40cc75: e9 c9 f0 ff ff jmpq 40bd43 + 40cc7a: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 40cc7e: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40cc83: 48 89 14 24 mov %rdx,(%rsp) + 40cc87: e8 84 8f ff ff callq 405c10 <__gettext_free_exp> + 40cc8c: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40cc91: 48 8b 14 24 mov (%rsp),%rdx + 40cc95: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 40cc99: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40cc9e: 48 89 14 24 mov %rdx,(%rsp) + 40cca2: e8 69 8f ff ff callq 405c10 <__gettext_free_exp> + 40cca7: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40ccac: 48 8b 14 24 mov (%rsp),%rdx + 40ccb0: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 40ccb4: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40ccb9: 48 89 14 24 mov %rdx,(%rsp) + 40ccbd: e8 4e 8f ff ff callq 405c10 <__gettext_free_exp> + 40ccc2: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40ccc7: 48 8b 14 24 mov (%rsp),%rdx + 40cccb: e9 ef ee ff ff jmpq 40bbbf + 40ccd0: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 40ccd4: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40ccd9: 48 89 14 24 mov %rdx,(%rsp) + 40ccdd: e8 2e 8f ff ff callq 405c10 <__gettext_free_exp> + 40cce2: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40cce7: 48 8b 14 24 mov (%rsp),%rdx + 40cceb: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 40ccef: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40ccf4: 48 89 14 24 mov %rdx,(%rsp) + 40ccf8: e8 13 8f ff ff callq 405c10 <__gettext_free_exp> + 40ccfd: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40cd02: 48 8b 14 24 mov (%rsp),%rdx + 40cd06: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 40cd0a: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40cd0f: 48 89 14 24 mov %rdx,(%rsp) + 40cd13: e8 f8 8e ff ff callq 405c10 <__gettext_free_exp> + 40cd18: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40cd1d: 48 8b 14 24 mov (%rsp),%rdx + 40cd21: e9 5b ef ff ff jmpq 40bc81 + 40cd26: 48 8b 78 18 mov 0x18(%rax),%rdi + 40cd2a: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40cd2f: e8 dc 8e ff ff callq 405c10 <__gettext_free_exp> + 40cd34: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40cd39: 48 8b 78 10 mov 0x10(%rax),%rdi + 40cd3d: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40cd42: e8 c9 8e ff ff callq 405c10 <__gettext_free_exp> + 40cd47: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40cd4c: 48 8b 78 08 mov 0x8(%rax),%rdi + 40cd50: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40cd55: e8 b6 8e ff ff callq 405c10 <__gettext_free_exp> + 40cd5a: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40cd5f: e9 66 dd ff ff jmpq 40aaca + 40cd64: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 40cd68: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40cd6d: 48 89 14 24 mov %rdx,(%rsp) + 40cd71: e8 9a 8e ff ff callq 405c10 <__gettext_free_exp> + 40cd76: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40cd7b: 48 8b 14 24 mov (%rsp),%rdx + 40cd7f: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 40cd83: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40cd88: 48 89 14 24 mov %rdx,(%rsp) + 40cd8c: e8 7f 8e ff ff callq 405c10 <__gettext_free_exp> + 40cd91: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40cd96: 48 8b 14 24 mov (%rsp),%rdx + 40cd9a: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 40cd9e: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40cda3: 48 89 14 24 mov %rdx,(%rsp) + 40cda7: e8 64 8e ff ff callq 405c10 <__gettext_free_exp> + 40cdac: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40cdb1: 48 8b 14 24 mov (%rsp),%rdx + 40cdb5: e9 a4 ed ff ff jmpq 40bb5e + 40cdba: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 40cdbe: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40cdc3: 48 89 14 24 mov %rdx,(%rsp) + 40cdc7: e8 44 8e ff ff callq 405c10 <__gettext_free_exp> + 40cdcc: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40cdd1: 48 8b 14 24 mov (%rsp),%rdx + 40cdd5: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 40cdd9: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40cdde: 48 89 14 24 mov %rdx,(%rsp) + 40cde2: e8 29 8e ff ff callq 405c10 <__gettext_free_exp> + 40cde7: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40cdec: 48 8b 14 24 mov (%rsp),%rdx + 40cdf0: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 40cdf4: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40cdf9: 48 89 14 24 mov %rdx,(%rsp) + 40cdfd: e8 0e 8e ff ff callq 405c10 <__gettext_free_exp> + 40ce02: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40ce07: 48 8b 14 24 mov (%rsp),%rdx + 40ce0b: e9 ba f4 ff ff jmpq 40c2ca + 40ce10: 48 8b 78 18 mov 0x18(%rax),%rdi + 40ce14: 48 89 04 24 mov %rax,(%rsp) + 40ce18: e8 f3 8d ff ff callq 405c10 <__gettext_free_exp> + 40ce1d: 48 8b 04 24 mov (%rsp),%rax + 40ce21: 48 8b 78 10 mov 0x10(%rax),%rdi + 40ce25: 48 89 04 24 mov %rax,(%rsp) + 40ce29: e8 e2 8d ff ff callq 405c10 <__gettext_free_exp> + 40ce2e: 48 8b 04 24 mov (%rsp),%rax + 40ce32: 48 8b 78 08 mov 0x8(%rax),%rdi + 40ce36: 48 89 04 24 mov %rax,(%rsp) + 40ce3a: e8 d1 8d ff ff callq 405c10 <__gettext_free_exp> + 40ce3f: 48 8b 04 24 mov (%rsp),%rax + 40ce43: e9 95 ef ff ff jmpq 40bddd + 40ce48: 48 8b 78 18 mov 0x18(%rax),%rdi + 40ce4c: 48 89 04 24 mov %rax,(%rsp) + 40ce50: e8 bb 8d ff ff callq 405c10 <__gettext_free_exp> + 40ce55: 48 8b 04 24 mov (%rsp),%rax + 40ce59: 48 8b 78 10 mov 0x10(%rax),%rdi + 40ce5d: 48 89 04 24 mov %rax,(%rsp) + 40ce61: e8 aa 8d ff ff callq 405c10 <__gettext_free_exp> + 40ce66: 48 8b 04 24 mov (%rsp),%rax + 40ce6a: 48 8b 78 08 mov 0x8(%rax),%rdi + 40ce6e: 48 89 04 24 mov %rax,(%rsp) + 40ce72: e8 99 8d ff ff callq 405c10 <__gettext_free_exp> + 40ce77: 48 8b 04 24 mov (%rsp),%rax + 40ce7b: e9 c6 e6 ff ff jmpq 40b546 + 40ce80: 48 8b 78 18 mov 0x18(%rax),%rdi + 40ce84: 48 89 04 24 mov %rax,(%rsp) + 40ce88: e8 83 8d ff ff callq 405c10 <__gettext_free_exp> + 40ce8d: 48 8b 04 24 mov (%rsp),%rax + 40ce91: 48 8b 78 10 mov 0x10(%rax),%rdi + 40ce95: 48 89 04 24 mov %rax,(%rsp) + 40ce99: e8 72 8d ff ff callq 405c10 <__gettext_free_exp> + 40ce9e: 48 8b 04 24 mov (%rsp),%rax + 40cea2: 48 8b 78 08 mov 0x8(%rax),%rdi + 40cea6: 48 89 04 24 mov %rax,(%rsp) + 40ceaa: e8 61 8d ff ff callq 405c10 <__gettext_free_exp> + 40ceaf: 48 8b 04 24 mov (%rsp),%rax + 40ceb3: e9 44 e5 ff ff jmpq 40b3fc + 40ceb8: 48 8b 78 18 mov 0x18(%rax),%rdi + 40cebc: 48 89 04 24 mov %rax,(%rsp) + 40cec0: e8 4b 8d ff ff callq 405c10 <__gettext_free_exp> + 40cec5: 48 8b 04 24 mov (%rsp),%rax + 40cec9: 48 8b 78 10 mov 0x10(%rax),%rdi + 40cecd: 48 89 04 24 mov %rax,(%rsp) + 40ced1: e8 3a 8d ff ff callq 405c10 <__gettext_free_exp> + 40ced6: 48 8b 04 24 mov (%rsp),%rax + 40ceda: 48 8b 78 08 mov 0x8(%rax),%rdi + 40cede: 48 89 04 24 mov %rax,(%rsp) + 40cee2: e8 29 8d ff ff callq 405c10 <__gettext_free_exp> + 40cee7: 48 8b 04 24 mov (%rsp),%rax + 40ceeb: e9 c4 e6 ff ff jmpq 40b5b4 + 40cef0: 48 8b 78 18 mov 0x18(%rax),%rdi + 40cef4: 48 89 04 24 mov %rax,(%rsp) + 40cef8: e8 13 8d ff ff callq 405c10 <__gettext_free_exp> + 40cefd: 48 8b 04 24 mov (%rsp),%rax + 40cf01: 48 8b 78 10 mov 0x10(%rax),%rdi + 40cf05: 48 89 04 24 mov %rax,(%rsp) + 40cf09: e8 02 8d ff ff callq 405c10 <__gettext_free_exp> + 40cf0e: 48 8b 04 24 mov (%rsp),%rax + 40cf12: 48 8b 78 08 mov 0x8(%rax),%rdi + 40cf16: 48 89 04 24 mov %rax,(%rsp) + 40cf1a: e8 f1 8c ff ff callq 405c10 <__gettext_free_exp> + 40cf1f: 48 8b 04 24 mov (%rsp),%rax + 40cf23: e9 66 e4 ff ff jmpq 40b38e + 40cf28: 48 8b 78 18 mov 0x18(%rax),%rdi + 40cf2c: 48 89 04 24 mov %rax,(%rsp) + 40cf30: e8 db 8c ff ff callq 405c10 <__gettext_free_exp> + 40cf35: 48 8b 04 24 mov (%rsp),%rax + 40cf39: 48 8b 78 10 mov 0x10(%rax),%rdi + 40cf3d: 48 89 04 24 mov %rax,(%rsp) + 40cf41: e8 ca 8c ff ff callq 405c10 <__gettext_free_exp> + 40cf46: 48 8b 04 24 mov (%rsp),%rax + 40cf4a: 48 8b 78 08 mov 0x8(%rax),%rdi + 40cf4e: 48 89 04 24 mov %rax,(%rsp) + 40cf52: e8 b9 8c ff ff callq 405c10 <__gettext_free_exp> + 40cf57: 48 8b 04 24 mov (%rsp),%rax + 40cf5b: e9 26 e1 ff ff jmpq 40b086 + 40cf60: 48 8b 78 18 mov 0x18(%rax),%rdi + 40cf64: 48 89 04 24 mov %rax,(%rsp) + 40cf68: e8 a3 8c ff ff callq 405c10 <__gettext_free_exp> + 40cf6d: 48 8b 04 24 mov (%rsp),%rax + 40cf71: 48 8b 78 10 mov 0x10(%rax),%rdi + 40cf75: 48 89 04 24 mov %rax,(%rsp) + 40cf79: e8 92 8c ff ff callq 405c10 <__gettext_free_exp> + 40cf7e: 48 8b 04 24 mov (%rsp),%rax + 40cf82: 48 8b 78 08 mov 0x8(%rax),%rdi + 40cf86: 48 89 04 24 mov %rax,(%rsp) + 40cf8a: e8 81 8c ff ff callq 405c10 <__gettext_free_exp> + 40cf8f: 48 8b 04 24 mov (%rsp),%rax + 40cf93: e9 fc ed ff ff jmpq 40bd94 + 40cf98: 48 8b 04 24 mov (%rsp),%rax + 40cf9c: 48 8b 78 18 mov 0x18(%rax),%rdi + 40cfa0: e8 6b 8c ff ff callq 405c10 <__gettext_free_exp> + 40cfa5: 48 8b 04 24 mov (%rsp),%rax + 40cfa9: 48 8b 40 10 mov 0x10(%rax),%rax + 40cfad: 48 85 c0 test %rax,%rax + 40cfb0: 0f 84 ee f4 ff ff je 40c4a4 + 40cfb6: 8b 10 mov (%rax),%edx + 40cfb8: 83 fa 02 cmp $0x2,%edx + 40cfbb: 0f 84 b5 f4 ff ff je 40c476 + 40cfc1: 83 fa 03 cmp $0x3,%edx + 40cfc4: 0f 84 99 f4 ff ff je 40c463 + 40cfca: 83 fa 01 cmp $0x1,%edx + 40cfcd: 0f 85 c9 f4 ff ff jne 40c49c + 40cfd3: e9 b1 f4 ff ff jmpq 40c489 + 40cfd8: 48 8b 78 18 mov 0x18(%rax),%rdi + 40cfdc: 48 89 04 24 mov %rax,(%rsp) + 40cfe0: e8 2b 8c ff ff callq 405c10 <__gettext_free_exp> + 40cfe5: 48 8b 04 24 mov (%rsp),%rax + 40cfe9: 48 8b 78 10 mov 0x10(%rax),%rdi + 40cfed: 48 89 04 24 mov %rax,(%rsp) + 40cff1: e8 1a 8c ff ff callq 405c10 <__gettext_free_exp> + 40cff6: 48 8b 04 24 mov (%rsp),%rax + 40cffa: 48 8b 78 08 mov 0x8(%rax),%rdi + 40cffe: 48 89 04 24 mov %rax,(%rsp) + 40d002: e8 09 8c ff ff callq 405c10 <__gettext_free_exp> + 40d007: 48 8b 04 24 mov (%rsp),%rax + 40d00b: e9 16 ee ff ff jmpq 40be26 + 40d010: 48 8b 04 24 mov (%rsp),%rax + 40d014: 48 8b 40 18 mov 0x18(%rax),%rax + 40d018: 48 85 c0 test %rax,%rax + 40d01b: 0f 84 46 d3 ff ff je 40a367 + 40d021: 8b 10 mov (%rax),%edx + 40d023: 83 fa 02 cmp $0x2,%edx + 40d026: 0f 84 0d d3 ff ff je 40a339 + 40d02c: 83 fa 03 cmp $0x3,%edx + 40d02f: 0f 84 f1 d2 ff ff je 40a326 + 40d035: 83 fa 01 cmp $0x1,%edx + 40d038: 0f 85 21 d3 ff ff jne 40a35f + 40d03e: e9 09 d3 ff ff jmpq 40a34c + 40d043: 48 8b 78 18 mov 0x18(%rax),%rdi + 40d047: 48 89 04 24 mov %rax,(%rsp) + 40d04b: e8 c0 8b ff ff callq 405c10 <__gettext_free_exp> + 40d050: 48 8b 04 24 mov (%rsp),%rax + 40d054: 48 8b 78 10 mov 0x10(%rax),%rdi + 40d058: 48 89 04 24 mov %rax,(%rsp) + 40d05c: e8 af 8b ff ff callq 405c10 <__gettext_free_exp> + 40d061: 48 8b 04 24 mov (%rsp),%rax + 40d065: 48 8b 50 08 mov 0x8(%rax),%rdx + 40d069: 48 85 d2 test %rdx,%rdx + 40d06c: 0f 84 d4 dd ff ff je 40ae46 + 40d072: 8b 0a mov (%rdx),%ecx + 40d074: 83 f9 02 cmp $0x2,%ecx + 40d077: 74 3a je 40d0b3 + 40d079: 83 f9 03 cmp $0x3,%ecx + 40d07c: 74 1a je 40d098 + 40d07e: 83 f9 01 cmp $0x1,%ecx + 40d081: 74 4b je 40d0ce + 40d083: 48 89 d7 mov %rdx,%rdi + 40d086: 48 89 04 24 mov %rax,(%rsp) + 40d08a: e8 21 0d 01 00 callq 41ddb0 <__cfree> + 40d08f: 48 8b 04 24 mov (%rsp),%rax + 40d093: e9 ae dd ff ff jmpq 40ae46 + 40d098: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 40d09c: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40d0a1: 48 89 14 24 mov %rdx,(%rsp) + 40d0a5: e8 66 8b ff ff callq 405c10 <__gettext_free_exp> + 40d0aa: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40d0af: 48 8b 14 24 mov (%rsp),%rdx + 40d0b3: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 40d0b7: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40d0bc: 48 89 14 24 mov %rdx,(%rsp) + 40d0c0: e8 4b 8b ff ff callq 405c10 <__gettext_free_exp> + 40d0c5: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40d0ca: 48 8b 14 24 mov (%rsp),%rdx + 40d0ce: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 40d0d2: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40d0d7: 48 89 14 24 mov %rdx,(%rsp) + 40d0db: e8 30 8b ff ff callq 405c10 <__gettext_free_exp> + 40d0e0: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40d0e5: 48 8b 14 24 mov (%rsp),%rdx + 40d0e9: eb 98 jmp 40d083 + 40d0eb: 48 8b 78 18 mov 0x18(%rax),%rdi + 40d0ef: 48 89 04 24 mov %rax,(%rsp) + 40d0f3: e8 18 8b ff ff callq 405c10 <__gettext_free_exp> + 40d0f8: 48 8b 04 24 mov (%rsp),%rax + 40d0fc: 48 8b 78 10 mov 0x10(%rax),%rdi + 40d100: 48 89 04 24 mov %rax,(%rsp) + 40d104: e8 07 8b ff ff callq 405c10 <__gettext_free_exp> + 40d109: 48 8b 04 24 mov (%rsp),%rax + 40d10d: 48 8b 78 08 mov 0x8(%rax),%rdi + 40d111: 48 89 04 24 mov %rax,(%rsp) + 40d115: e8 f6 8a ff ff callq 405c10 <__gettext_free_exp> + 40d11a: 48 8b 04 24 mov (%rsp),%rax + 40d11e: e9 43 de ff ff jmpq 40af66 + 40d123: 48 8b 78 18 mov 0x18(%rax),%rdi + 40d127: 48 89 04 24 mov %rax,(%rsp) + 40d12b: e8 e0 8a ff ff callq 405c10 <__gettext_free_exp> + 40d130: 48 8b 04 24 mov (%rsp),%rax + 40d134: 48 8b 78 10 mov 0x10(%rax),%rdi + 40d138: 48 89 04 24 mov %rax,(%rsp) + 40d13c: e8 cf 8a ff ff callq 405c10 <__gettext_free_exp> + 40d141: 48 8b 04 24 mov (%rsp),%rax + 40d145: 48 8b 78 08 mov 0x8(%rax),%rdi + 40d149: 48 89 04 24 mov %rax,(%rsp) + 40d14d: e8 be 8a ff ff callq 405c10 <__gettext_free_exp> + 40d152: 48 8b 04 24 mov (%rsp),%rax + 40d156: e9 7d e3 ff ff jmpq 40b4d8 + 40d15b: 48 8b 78 18 mov 0x18(%rax),%rdi + 40d15f: 48 89 04 24 mov %rax,(%rsp) + 40d163: e8 a8 8a ff ff callq 405c10 <__gettext_free_exp> + 40d168: 48 8b 04 24 mov (%rsp),%rax + 40d16c: 48 8b 78 10 mov 0x10(%rax),%rdi + 40d170: 48 89 04 24 mov %rax,(%rsp) + 40d174: e8 97 8a ff ff callq 405c10 <__gettext_free_exp> + 40d179: 48 8b 04 24 mov (%rsp),%rax + 40d17d: 48 8b 50 08 mov 0x8(%rax),%rdx + 40d181: 48 85 d2 test %rdx,%rdx + 40d184: 0f 84 e0 e2 ff ff je 40b46a + 40d18a: 8b 0a mov (%rdx),%ecx + 40d18c: 83 f9 02 cmp $0x2,%ecx + 40d18f: 74 3a je 40d1cb + 40d191: 83 f9 03 cmp $0x3,%ecx + 40d194: 74 1a je 40d1b0 + 40d196: 83 f9 01 cmp $0x1,%ecx + 40d199: 74 4b je 40d1e6 + 40d19b: 48 89 d7 mov %rdx,%rdi + 40d19e: 48 89 04 24 mov %rax,(%rsp) + 40d1a2: e8 09 0c 01 00 callq 41ddb0 <__cfree> + 40d1a7: 48 8b 04 24 mov (%rsp),%rax + 40d1ab: e9 ba e2 ff ff jmpq 40b46a + 40d1b0: 48 8b 7a 18 mov 0x18(%rdx),%rdi + 40d1b4: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40d1b9: 48 89 14 24 mov %rdx,(%rsp) + 40d1bd: e8 4e 8a ff ff callq 405c10 <__gettext_free_exp> + 40d1c2: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40d1c7: 48 8b 14 24 mov (%rsp),%rdx + 40d1cb: 48 8b 7a 10 mov 0x10(%rdx),%rdi + 40d1cf: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40d1d4: 48 89 14 24 mov %rdx,(%rsp) + 40d1d8: e8 33 8a ff ff callq 405c10 <__gettext_free_exp> + 40d1dd: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40d1e2: 48 8b 14 24 mov (%rsp),%rdx + 40d1e6: 48 8b 7a 08 mov 0x8(%rdx),%rdi + 40d1ea: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40d1ef: 48 89 14 24 mov %rdx,(%rsp) + 40d1f3: e8 18 8a ff ff callq 405c10 <__gettext_free_exp> + 40d1f8: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40d1fd: 48 8b 14 24 mov (%rsp),%rdx + 40d201: eb 98 jmp 40d19b + 40d203: bf 20 00 00 00 mov $0x20,%edi + 40d208: 89 34 24 mov %esi,(%rsp) + 40d20b: e8 00 08 01 00 callq 41da10 <__libc_malloc> + 40d210: 48 85 c0 test %rax,%rax + 40d213: 8b 34 24 mov (%rsp),%esi + 40d216: 0f 84 b4 d3 ff ff je 40a5d0 + 40d21c: 44 89 20 mov %r12d,(%rax) + 40d21f: 89 70 04 mov %esi,0x4(%rax) + 40d222: e9 ab d3 ff ff jmpq 40a5d2 + 40d227: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 40d22e: 00 00 + +000000000040d230 <__gettextparse>: + 40d230: 41 57 push %r15 + 40d232: 41 56 push %r14 + 40d234: 45 31 c0 xor %r8d,%r8d + 40d237: 41 55 push %r13 + 40d239: 41 54 push %r12 + 40d23b: 45 89 c5 mov %r8d,%r13d + 40d23e: 55 push %rbp + 40d23f: 53 push %rbx + 40d240: bd c8 00 00 00 mov $0xc8,%ebp + 40d245: 41 bc fe ff ff ff mov $0xfffffffe,%r12d + 40d24b: 48 81 ec 28 08 00 00 sub $0x828,%rsp + 40d252: 48 8d 9c 24 e0 01 00 lea 0x1e0(%rsp),%rbx + 40d259: 00 + 40d25a: 4c 8d 74 24 50 lea 0x50(%rsp),%r14 + 40d25f: 48 89 7c 24 18 mov %rdi,0x18(%rsp) + 40d264: c7 44 24 0c 00 00 00 movl $0x0,0xc(%rsp) + 40d26b: 00 + 40d26c: 48 89 1c 24 mov %rbx,(%rsp) + 40d270: 4c 89 f1 mov %r14,%rcx + 40d273: 48 8d 44 2d 00 lea 0x0(%rbp,%rbp,1),%rax + 40d278: 66 45 89 2e mov %r13w,(%r14) + 40d27c: 48 8d 54 01 fe lea -0x2(%rcx,%rax,1),%rdx + 40d281: 49 39 d6 cmp %rdx,%r14 + 40d284: 0f 82 c4 00 00 00 jb 40d34e <__gettextparse+0x11e> + 40d28a: 49 29 ce sub %rcx,%r14 + 40d28d: 49 d1 fe sar %r14 + 40d290: 48 81 fd 0f 27 00 00 cmp $0x270f,%rbp + 40d297: 49 8d 5e 01 lea 0x1(%r14),%rbx + 40d29b: 0f 87 0e 07 00 00 ja 40d9af <__gettextparse+0x77f> + 40d2a1: 48 3d 10 27 00 00 cmp $0x2710,%rax + 40d2a7: bd 10 27 00 00 mov $0x2710,%ebp + 40d2ac: 48 89 4c 24 10 mov %rcx,0x10(%rsp) + 40d2b1: 48 0f 46 e8 cmovbe %rax,%rbp + 40d2b5: 48 8d 44 ad 00 lea 0x0(%rbp,%rbp,4),%rax + 40d2ba: 48 8d 7c 00 07 lea 0x7(%rax,%rax,1),%rdi + 40d2bf: e8 4c 07 01 00 callq 41da10 <__libc_malloc> + 40d2c4: 48 85 c0 test %rax,%rax + 40d2c7: 49 89 c7 mov %rax,%r15 + 40d2ca: 48 8b 4c 24 10 mov 0x10(%rsp),%rcx + 40d2cf: 0f 84 da 06 00 00 je 40d9af <__gettextparse+0x77f> + 40d2d5: 4c 8d 34 1b lea (%rbx,%rbx,1),%r14 + 40d2d9: 48 89 ce mov %rcx,%rsi + 40d2dc: 48 89 c7 mov %rax,%rdi + 40d2df: 48 c1 e3 03 shl $0x3,%rbx + 40d2e3: 4c 89 f2 mov %r14,%rdx + 40d2e6: e8 35 ed 01 00 callq 42c020 + 40d2eb: 4d 8d 14 6f lea (%r15,%rbp,2),%r10 + 40d2ef: 48 8b 34 24 mov (%rsp),%rsi + 40d2f3: 48 8d 44 2d 00 lea 0x0(%rbp,%rbp,1),%rax + 40d2f8: 48 89 da mov %rbx,%rdx + 40d2fb: 4c 89 d7 mov %r10,%rdi + 40d2fe: 48 89 44 24 20 mov %rax,0x20(%rsp) + 40d303: e8 18 ed 01 00 callq 42c020 + 40d308: 48 8b 4c 24 10 mov 0x10(%rsp),%rcx + 40d30d: 49 89 c2 mov %rax,%r10 + 40d310: 48 8d 44 24 50 lea 0x50(%rsp),%rax + 40d315: 48 39 c1 cmp %rax,%rcx + 40d318: 74 10 je 40d32a <__gettextparse+0xfa> + 40d31a: 48 89 cf mov %rcx,%rdi + 40d31d: 4c 89 14 24 mov %r10,(%rsp) + 40d321: e8 8a 0a 01 00 callq 41ddb0 <__cfree> + 40d326: 4c 8b 14 24 mov (%rsp),%r10 + 40d32a: 48 8d 44 2d 00 lea 0x0(%rbp,%rbp,1),%rax + 40d32f: 4f 8d 74 37 fe lea -0x2(%r15,%r14,1),%r14 + 40d334: 49 8d 5c 1a f8 lea -0x8(%r10,%rbx,1),%rbx + 40d339: 49 8d 44 07 fe lea -0x2(%r15,%rax,1),%rax + 40d33e: 49 39 c6 cmp %rax,%r14 + 40d341: 0f 83 7f 06 00 00 jae 40d9c6 <__gettextparse+0x796> + 40d347: 4c 89 14 24 mov %r10,(%rsp) + 40d34b: 4c 89 f9 mov %r15,%rcx + 40d34e: 41 83 fd 09 cmp $0x9,%r13d + 40d352: 0f 84 64 06 00 00 je 40d9bc <__gettextparse+0x78c> + 40d358: 4d 63 c5 movslq %r13d,%r8 + 40d35b: 41 0f be 80 20 17 4a movsbl 0x4a1720(%r8),%eax + 40d362: 00 + 40d363: 83 f8 f6 cmp $0xfffffff6,%eax + 40d366: 74 3f je 40d3a7 <__gettextparse+0x177> + 40d368: 41 83 fc fe cmp $0xfffffffe,%r12d + 40d36c: 0f 84 2e 02 00 00 je 40d5a0 <__gettextparse+0x370> + 40d372: 45 85 e4 test %r12d,%r12d + 40d375: 0f 8e bc 01 00 00 jle 40d537 <__gettextparse+0x307> + 40d37b: 41 81 fc 06 01 00 00 cmp $0x106,%r12d + 40d382: be 02 00 00 00 mov $0x2,%esi + 40d387: 0f 8e 93 01 00 00 jle 40d520 <__gettextparse+0x2f0> + 40d38d: 8d 14 06 lea (%rsi,%rax,1),%edx + 40d390: 83 fa 36 cmp $0x36,%edx + 40d393: 77 12 ja 40d3a7 <__gettextparse+0x177> + 40d395: 48 63 d2 movslq %edx,%rdx + 40d398: 0f be ba a0 16 4a 00 movsbl 0x4a16a0(%rdx),%edi + 40d39f: 39 fe cmp %edi,%esi + 40d3a1: 0f 84 b9 01 00 00 je 40d560 <__gettextparse+0x330> + 40d3a7: 41 0f b6 b0 40 17 4a movzbl 0x4a1740(%r8),%esi + 40d3ae: 00 + 40d3af: 85 f6 test %esi,%esi + 40d3b1: 48 89 f2 mov %rsi,%rdx + 40d3b4: 74 32 je 40d3e8 <__gettextparse+0x1b8> + 40d3b6: 48 63 f6 movslq %esi,%rsi + 40d3b9: bf 01 00 00 00 mov $0x1,%edi + 40d3be: 0f b6 86 60 17 4a 00 movzbl 0x4a1760(%rsi),%eax + 40d3c5: 29 c7 sub %eax,%edi + 40d3c7: 49 89 c7 mov %rax,%r15 + 40d3ca: 80 fa 0d cmp $0xd,%dl + 40d3cd: 48 63 c7 movslq %edi,%rax + 40d3d0: 48 8b 04 c3 mov (%rbx,%rax,8),%rax + 40d3d4: 0f 87 94 03 00 00 ja 40d76e <__gettextparse+0x53e> + 40d3da: ff 24 d5 40 12 4a 00 jmpq *0x4a1240(,%rdx,8) + 40d3e1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 40d3e8: 83 7c 24 0c 03 cmpl $0x3,0xc(%rsp) + 40d3ed: 75 21 jne 40d410 <__gettextparse+0x1e0> + 40d3ef: e9 54 01 00 00 jmpq 40d548 <__gettextparse+0x318> + 40d3f4: 0f 1f 40 00 nopl 0x0(%rax) + 40d3f8: 4c 39 f1 cmp %r14,%rcx + 40d3fb: 74 53 je 40d450 <__gettextparse+0x220> + 40d3fd: 49 83 ee 02 sub $0x2,%r14 + 40d401: 49 0f bf 06 movswq (%r14),%rax + 40d405: 48 83 eb 08 sub $0x8,%rbx + 40d409: 0f be 80 20 17 4a 00 movsbl 0x4a1720(%rax),%eax + 40d410: 83 f8 f6 cmp $0xfffffff6,%eax + 40d413: 74 e3 je 40d3f8 <__gettextparse+0x1c8> + 40d415: 83 c0 01 add $0x1,%eax + 40d418: 83 f8 36 cmp $0x36,%eax + 40d41b: 77 db ja 40d3f8 <__gettextparse+0x1c8> + 40d41d: 48 98 cltq + 40d41f: 80 b8 a0 16 4a 00 01 cmpb $0x1,0x4a16a0(%rax) + 40d426: 75 d0 jne 40d3f8 <__gettextparse+0x1c8> + 40d428: 44 0f b6 a8 e0 16 4a movzbl 0x4a16e0(%rax),%r13d + 40d42f: 00 + 40d430: 45 85 ed test %r13d,%r13d + 40d433: 74 c3 je 40d3f8 <__gettextparse+0x1c8> + 40d435: 48 8b 44 24 28 mov 0x28(%rsp),%rax + 40d43a: 48 83 c3 08 add $0x8,%rbx + 40d43e: c7 44 24 0c 03 00 00 movl $0x3,0xc(%rsp) + 40d445: 00 + 40d446: 48 89 03 mov %rax,(%rbx) + 40d449: e9 b0 00 00 00 jmpq 40d4fe <__gettextparse+0x2ce> + 40d44e: 66 90 xchg %ax,%ax + 40d450: bb 01 00 00 00 mov $0x1,%ebx + 40d455: 48 8d 44 24 50 lea 0x50(%rsp),%rax + 40d45a: 49 39 c6 cmp %rax,%r14 + 40d45d: 74 08 je 40d467 <__gettextparse+0x237> + 40d45f: 4c 89 f7 mov %r14,%rdi + 40d462: e8 49 09 01 00 callq 41ddb0 <__cfree> + 40d467: 48 81 c4 28 08 00 00 add $0x828,%rsp + 40d46e: 89 d8 mov %ebx,%eax + 40d470: 5b pop %rbx + 40d471: 5d pop %rbp + 40d472: 41 5c pop %r12 + 40d474: 41 5d pop %r13 + 40d476: 41 5e pop %r14 + 40d478: 41 5f pop %r15 + 40d47a: c3 retq + 40d47b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 40d480: 48 8b 03 mov (%rbx),%rax + 40d483: 48 8b 53 f0 mov -0x10(%rbx),%rdx + 40d487: 48 8d 74 24 30 lea 0x30(%rsp),%rsi + 40d48c: 8b 7b f8 mov -0x8(%rbx),%edi + 40d48f: 48 89 4c 24 10 mov %rcx,0x10(%rsp) + 40d494: 48 89 54 24 30 mov %rdx,0x30(%rsp) + 40d499: 48 89 44 24 38 mov %rax,0x38(%rsp) + 40d49e: e8 2d 8e ff ff callq 4062d0 + 40d4a3: 4a 8d 3c fd 00 00 00 lea 0x0(,%r15,8),%rdi + 40d4aa: 00 + 40d4ab: 4b 8d 14 3f lea (%r15,%r15,1),%rdx + 40d4af: 48 8b 4c 24 10 mov 0x10(%rsp),%rcx + 40d4b4: be ff ff ff ff mov $0xffffffff,%esi + 40d4b9: 41 b8 02 00 00 00 mov $0x2,%r8d + 40d4bf: 48 f7 df neg %rdi + 40d4c2: 48 f7 da neg %rdx + 40d4c5: 48 01 df add %rbx,%rdi + 40d4c8: 49 01 d6 add %rdx,%r14 + 40d4cb: 48 89 47 08 mov %rax,0x8(%rdi) + 40d4cf: 41 0f bf 06 movswl (%r14),%eax + 40d4d3: 48 8d 5f 08 lea 0x8(%rdi),%rbx + 40d4d7: 89 c2 mov %eax,%edx + 40d4d9: 01 f0 add %esi,%eax + 40d4db: 83 f8 36 cmp $0x36,%eax + 40d4de: 77 13 ja 40d4f3 <__gettextparse+0x2c3> + 40d4e0: 48 98 cltq + 40d4e2: 66 0f be b0 a0 16 4a movsbw 0x4a16a0(%rax),%si + 40d4e9: 00 + 40d4ea: 66 39 f2 cmp %si,%dx + 40d4ed: 0f 84 5b 02 00 00 je 40d74e <__gettextparse+0x51e> + 40d4f3: 4d 63 c0 movslq %r8d,%r8 + 40d4f6: 45 0f be a8 3b 17 4a movsbl 0x4a173b(%r8),%r13d + 40d4fd: 00 + 40d4fe: 49 83 c6 02 add $0x2,%r14 + 40d502: e9 6c fd ff ff jmpq 40d273 <__gettextparse+0x43> + 40d507: 49 8d 79 02 lea 0x2(%r9),%rdi + 40d50b: 48 8b 74 24 18 mov 0x18(%rsp),%rsi + 40d510: 45 85 e4 test %r12d,%r12d + 40d513: 48 89 3e mov %rdi,(%rsi) + 40d516: 7e 1f jle 40d537 <__gettextparse+0x307> + 40d518: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 40d51f: 00 + 40d520: 49 63 d4 movslq %r12d,%rdx + 40d523: 0f b6 b2 80 17 4a 00 movzbl 0x4a1780(%rdx),%esi + 40d52a: e9 5e fe ff ff jmpq 40d38d <__gettextparse+0x15d> + 40d52f: 48 8b 74 24 18 mov 0x18(%rsp),%rsi + 40d534: 4c 89 0e mov %r9,(%rsi) + 40d537: 31 f6 xor %esi,%esi + 40d539: 45 31 e4 xor %r12d,%r12d + 40d53c: e9 4c fe ff ff jmpq 40d38d <__gettextparse+0x15d> + 40d541: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 40d548: 41 83 fc 00 cmp $0x0,%r12d + 40d54c: 0f 8e 09 02 00 00 jle 40d75b <__gettextparse+0x52b> + 40d552: 41 bc fe ff ff ff mov $0xfffffffe,%r12d + 40d558: e9 b3 fe ff ff jmpq 40d410 <__gettextparse+0x1e0> + 40d55d: 0f 1f 00 nopl (%rax) + 40d560: 44 0f b6 aa e0 16 4a movzbl 0x4a16e0(%rdx),%r13d + 40d567: 00 + 40d568: 45 85 ed test %r13d,%r13d + 40d56b: 0f 84 c8 01 00 00 je 40d739 <__gettextparse+0x509> + 40d571: 8b 44 24 0c mov 0xc(%rsp),%eax + 40d575: 41 bc fe ff ff ff mov $0xfffffffe,%r12d + 40d57b: 83 f8 01 cmp $0x1,%eax + 40d57e: 83 d0 ff adc $0xffffffff,%eax + 40d581: 48 83 c3 08 add $0x8,%rbx + 40d585: 89 44 24 0c mov %eax,0xc(%rsp) + 40d589: 48 8b 44 24 28 mov 0x28(%rsp),%rax + 40d58e: 48 89 03 mov %rax,(%rbx) + 40d591: e9 68 ff ff ff jmpq 40d4fe <__gettextparse+0x2ce> + 40d596: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 40d59d: 00 00 00 + 40d5a0: 48 8b 74 24 18 mov 0x18(%rsp),%rsi + 40d5a5: 4c 8b 0e mov (%rsi),%r9 + 40d5a8: 41 0f b6 11 movzbl (%r9),%edx + 40d5ac: 84 d2 test %dl,%dl + 40d5ae: 74 84 je 40d534 <__gettextparse+0x304> + 40d5b0: 80 fa 09 cmp $0x9,%dl + 40d5b3: 74 0b je 40d5c0 <__gettextparse+0x390> + 40d5b5: 80 fa 20 cmp $0x20,%dl + 40d5b8: 75 20 jne 40d5da <__gettextparse+0x3aa> + 40d5ba: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 40d5c0: 49 83 c1 01 add $0x1,%r9 + 40d5c4: 41 0f b6 11 movzbl (%r9),%edx + 40d5c8: 84 d2 test %dl,%dl + 40d5ca: 0f 84 5f ff ff ff je 40d52f <__gettextparse+0x2ff> + 40d5d0: 80 fa 20 cmp $0x20,%dl + 40d5d3: 74 eb je 40d5c0 <__gettextparse+0x390> + 40d5d5: 80 fa 09 cmp $0x9,%dl + 40d5d8: 74 e6 je 40d5c0 <__gettextparse+0x390> + 40d5da: 80 fa 7c cmp $0x7c,%dl + 40d5dd: 49 8d 79 01 lea 0x1(%r9),%rdi + 40d5e1: 44 0f be e2 movsbl %dl,%r12d + 40d5e5: 0f 87 c0 01 00 00 ja 40d7ab <__gettextparse+0x57b> + 40d5eb: 0f b6 d2 movzbl %dl,%edx + 40d5ee: ff 24 d5 b0 12 4a 00 jmpq *0x4a12b0(,%rdx,8) + 40d5f5: 48 8b 13 mov (%rbx),%rdx + 40d5f8: 48 85 d2 test %rdx,%rdx + 40d5fb: 0f 84 60 01 00 00 je 40d761 <__gettextparse+0x531> + 40d601: 48 8b 74 24 18 mov 0x18(%rsp),%rsi + 40d606: 4a 8d 3c fd 00 00 00 lea 0x0(,%r15,8),%rdi + 40d60d: 00 + 40d60e: 41 b8 01 00 00 00 mov $0x1,%r8d + 40d614: 48 f7 df neg %rdi + 40d617: 48 89 56 08 mov %rdx,0x8(%rsi) + 40d61b: 4b 8d 14 3f lea (%r15,%r15,1),%rdx + 40d61f: be f6 ff ff ff mov $0xfffffff6,%esi + 40d624: 48 f7 da neg %rdx + 40d627: e9 99 fe ff ff jmpq 40d4c5 <__gettextparse+0x295> + 40d62c: 48 8b 53 f0 mov -0x10(%rbx),%rdx + 40d630: 48 8b 73 e0 mov -0x20(%rbx),%rsi + 40d634: bf 03 00 00 00 mov $0x3,%edi + 40d639: 48 8b 03 mov (%rbx),%rax + 40d63c: 48 89 4c 24 10 mov %rcx,0x10(%rsp) + 40d641: 48 89 54 24 38 mov %rdx,0x38(%rsp) + 40d646: 48 8d 54 24 30 lea 0x30(%rsp),%rdx + 40d64b: 48 89 74 24 30 mov %rsi,0x30(%rsp) + 40d650: be 10 00 00 00 mov $0x10,%esi + 40d655: 48 89 44 24 40 mov %rax,0x40(%rsp) + 40d65a: e8 01 c4 ff ff callq 409a60 + 40d65f: e9 3f fe ff ff jmpq 40d4a3 <__gettextparse+0x273> + 40d664: 48 8b 03 mov (%rbx),%rax + 40d667: 48 8b 53 f0 mov -0x10(%rbx),%rdx + 40d66b: 48 8d 74 24 30 lea 0x30(%rsp),%rsi + 40d670: 48 89 4c 24 10 mov %rcx,0x10(%rsp) + 40d675: bf 0f 00 00 00 mov $0xf,%edi + 40d67a: 48 89 54 24 30 mov %rdx,0x30(%rsp) + 40d67f: 48 89 44 24 38 mov %rax,0x38(%rsp) + 40d684: e9 15 fe ff ff jmpq 40d49e <__gettextparse+0x26e> + 40d689: 48 8b 03 mov (%rbx),%rax + 40d68c: 48 8b 53 f0 mov -0x10(%rbx),%rdx + 40d690: 48 8d 74 24 30 lea 0x30(%rsp),%rsi + 40d695: 48 89 4c 24 10 mov %rcx,0x10(%rsp) + 40d69a: bf 0e 00 00 00 mov $0xe,%edi + 40d69f: 48 89 54 24 30 mov %rdx,0x30(%rsp) + 40d6a4: 48 89 44 24 38 mov %rax,0x38(%rsp) + 40d6a9: e9 f0 fd ff ff jmpq 40d49e <__gettextparse+0x26e> + 40d6ae: 48 8b 43 f8 mov -0x8(%rbx),%rax + 40d6b2: 4a 8d 3c fd 00 00 00 lea 0x0(,%r15,8),%rdi + 40d6b9: 00 + 40d6ba: 4b 8d 14 3f lea (%r15,%r15,1),%rdx + 40d6be: be ff ff ff ff mov $0xffffffff,%esi + 40d6c3: 41 b8 02 00 00 00 mov $0x2,%r8d + 40d6c9: 48 f7 df neg %rdi + 40d6cc: 48 f7 da neg %rdx + 40d6cf: e9 f1 fd ff ff jmpq 40d4c5 <__gettextparse+0x295> + 40d6d4: 48 8b 03 mov (%rbx),%rax + 40d6d7: 48 8d 54 24 30 lea 0x30(%rsp),%rdx + 40d6dc: be 02 00 00 00 mov $0x2,%esi + 40d6e1: bf 01 00 00 00 mov $0x1,%edi + 40d6e6: 48 89 4c 24 10 mov %rcx,0x10(%rsp) + 40d6eb: 48 89 44 24 30 mov %rax,0x30(%rsp) + 40d6f0: e8 6b c3 ff ff callq 409a60 + 40d6f5: e9 a9 fd ff ff jmpq 40d4a3 <__gettextparse+0x273> + 40d6fa: 31 d2 xor %edx,%edx + 40d6fc: 31 ff xor %edi,%edi + 40d6fe: be 01 00 00 00 mov $0x1,%esi + 40d703: 48 89 4c 24 10 mov %rcx,0x10(%rsp) + 40d708: e8 53 c3 ff ff callq 409a60 + 40d70d: 48 85 c0 test %rax,%rax + 40d710: 48 8b 4c 24 10 mov 0x10(%rsp),%rcx + 40d715: 0f 84 b8 02 00 00 je 40d9d3 <__gettextparse+0x7a3> + 40d71b: 48 8b 13 mov (%rbx),%rdx + 40d71e: 48 89 50 08 mov %rdx,0x8(%rax) + 40d722: eb 8e jmp 40d6b2 <__gettextparse+0x482> + 40d724: 31 d2 xor %edx,%edx + 40d726: 31 f6 xor %esi,%esi + 40d728: 31 ff xor %edi,%edi + 40d72a: 48 89 4c 24 10 mov %rcx,0x10(%rsp) + 40d72f: e8 2c c3 ff ff callq 409a60 + 40d734: e9 6a fd ff ff jmpq 40d4a3 <__gettextparse+0x273> + 40d739: 48 8b 43 08 mov 0x8(%rbx),%rax + 40d73d: 31 f6 xor %esi,%esi + 40d73f: 41 b8 f0 ff ff ff mov $0xfffffff0,%r8d + 40d745: 31 d2 xor %edx,%edx + 40d747: 31 ff xor %edi,%edi + 40d749: e9 77 fd ff ff jmpq 40d4c5 <__gettextparse+0x295> + 40d74e: 44 0f b6 a8 e0 16 4a movzbl 0x4a16e0(%rax),%r13d + 40d755: 00 + 40d756: e9 a3 fd ff ff jmpq 40d4fe <__gettextparse+0x2ce> + 40d75b: 0f 85 af fc ff ff jne 40d410 <__gettextparse+0x1e0> + 40d761: 49 89 ce mov %rcx,%r14 + 40d764: bb 01 00 00 00 mov $0x1,%ebx + 40d769: e9 e7 fc ff ff jmpq 40d455 <__gettextparse+0x225> + 40d76e: 44 0f b6 86 70 17 4a movzbl 0x4a1770(%rsi),%r8d + 40d775: 00 + 40d776: 4a 8d 3c fd 00 00 00 lea 0x0(,%r15,8),%rdi + 40d77d: 00 + 40d77e: 4d 01 ff add %r15,%r15 + 40d781: 4c 89 fa mov %r15,%rdx + 40d784: 48 f7 df neg %rdi + 40d787: 48 f7 da neg %rdx + 40d78a: 41 83 e8 10 sub $0x10,%r8d + 40d78e: 49 63 f0 movslq %r8d,%rsi + 40d791: 0f be b6 17 17 4a 00 movsbl 0x4a1717(%rsi),%esi + 40d798: e9 28 fd ff ff jmpq 40d4c5 <__gettextparse+0x295> + 40d79d: 41 0f be 51 01 movsbl 0x1(%r9),%edx + 40d7a2: 41 39 d4 cmp %edx,%r12d + 40d7a5: 0f 84 5c fd ff ff je 40d507 <__gettextparse+0x2d7> + 40d7ab: be 01 00 00 00 mov $0x1,%esi + 40d7b0: 41 bc 00 01 00 00 mov $0x100,%r12d + 40d7b6: 48 8b 54 24 18 mov 0x18(%rsp),%rdx + 40d7bb: 48 89 3a mov %rdi,(%rdx) + 40d7be: e9 ca fb ff ff jmpq 40d38d <__gettextparse+0x15d> + 40d7c3: 48 ba 00 00 00 00 ff movabs $0xffffffff00000000,%rdx + 40d7ca: ff ff ff + 40d7cd: 48 23 54 24 28 and 0x28(%rsp),%rdx + 40d7d2: be 09 00 00 00 mov $0x9,%esi + 40d7d7: 41 bc 05 01 00 00 mov $0x105,%r12d + 40d7dd: 48 83 ca 05 or $0x5,%rdx + 40d7e1: 48 89 54 24 28 mov %rdx,0x28(%rsp) + 40d7e6: eb ce jmp 40d7b6 <__gettextparse+0x586> + 40d7e8: 41 80 79 01 3d cmpb $0x3d,0x1(%r9) + 40d7ed: 0f 85 18 fd ff ff jne 40d50b <__gettextparse+0x2db> + 40d7f3: 48 ba 00 00 00 00 ff movabs $0xffffffff00000000,%rdx + 40d7fa: ff ff ff + 40d7fd: 48 23 54 24 28 and 0x28(%rsp),%rdx + 40d802: 49 8d 79 02 lea 0x2(%r9),%rdi + 40d806: be 06 00 00 00 mov $0x6,%esi + 40d80b: 41 bc 02 01 00 00 mov $0x102,%r12d + 40d811: 48 83 ca 0d or $0xd,%rdx + 40d815: 48 89 54 24 28 mov %rdx,0x28(%rsp) + 40d81a: eb 9a jmp 40d7b6 <__gettextparse+0x586> + 40d81c: 41 80 79 01 3d cmpb $0x3d,0x1(%r9) + 40d821: 0f 84 d0 01 00 00 je 40d9f7 <__gettextparse+0x7c7> + 40d827: 48 ba 00 00 00 00 ff movabs $0xffffffff00000000,%rdx + 40d82e: ff ff ff + 40d831: 48 23 54 24 28 and 0x28(%rsp),%rdx + 40d836: be 07 00 00 00 mov $0x7,%esi + 40d83b: 41 bc 03 01 00 00 mov $0x103,%r12d + 40d841: 48 83 ca 09 or $0x9,%rdx + 40d845: 48 89 54 24 28 mov %rdx,0x28(%rsp) + 40d84a: e9 67 ff ff ff jmpq 40d7b6 <__gettextparse+0x586> + 40d84f: 41 80 79 01 3d cmpb $0x3d,0x1(%r9) + 40d854: be 01 00 00 00 mov $0x1,%esi + 40d859: 41 bc 00 01 00 00 mov $0x100,%r12d + 40d85f: 0f 85 51 ff ff ff jne 40d7b6 <__gettextparse+0x586> + 40d865: 48 ba 00 00 00 00 ff movabs $0xffffffff00000000,%rdx + 40d86c: ff ff ff + 40d86f: 48 23 54 24 28 and 0x28(%rsp),%rdx + 40d874: 49 8d 79 02 lea 0x2(%r9),%rdi + 40d878: be 06 00 00 00 mov $0x6,%esi + 40d87d: 41 bc 02 01 00 00 mov $0x102,%r12d + 40d883: 48 83 ca 0c or $0xc,%rdx + 40d887: 48 89 54 24 28 mov %rdx,0x28(%rsp) + 40d88c: e9 25 ff ff ff jmpq 40d7b6 <__gettextparse+0x586> + 40d891: 41 80 79 01 3d cmpb $0x3d,0x1(%r9) + 40d896: 0f 84 87 01 00 00 je 40da23 <__gettextparse+0x7f3> + 40d89c: 48 ba 00 00 00 00 ff movabs $0xffffffff00000000,%rdx + 40d8a3: ff ff ff + 40d8a6: 48 23 54 24 28 and 0x28(%rsp),%rdx + 40d8ab: be 07 00 00 00 mov $0x7,%esi + 40d8b0: 41 bc 03 01 00 00 mov $0x103,%r12d + 40d8b6: 48 83 ca 08 or $0x8,%rdx + 40d8ba: 48 89 54 24 28 mov %rdx,0x28(%rsp) + 40d8bf: e9 f2 fe ff ff jmpq 40d7b6 <__gettextparse+0x586> + 40d8c4: 41 0f be 51 01 movsbl 0x1(%r9),%edx + 40d8c9: 41 8d 74 24 d0 lea -0x30(%r12),%esi + 40d8ce: 48 63 f6 movslq %esi,%rsi + 40d8d1: 44 8d 4a d0 lea -0x30(%rdx),%r9d + 40d8d5: 41 80 f9 09 cmp $0x9,%r9b + 40d8d9: 77 1f ja 40d8fa <__gettextparse+0x6ca> + 40d8db: 83 ea 30 sub $0x30,%edx + 40d8de: 48 8d 34 b6 lea (%rsi,%rsi,4),%rsi + 40d8e2: 48 83 c7 01 add $0x1,%rdi + 40d8e6: 48 63 d2 movslq %edx,%rdx + 40d8e9: 48 8d 34 72 lea (%rdx,%rsi,2),%rsi + 40d8ed: 0f be 17 movsbl (%rdi),%edx + 40d8f0: 44 8d 4a d0 lea -0x30(%rdx),%r9d + 40d8f4: 41 80 f9 09 cmp $0x9,%r9b + 40d8f8: 76 e1 jbe 40d8db <__gettextparse+0x6ab> + 40d8fa: 48 89 74 24 28 mov %rsi,0x28(%rsp) + 40d8ff: 41 bc 06 01 00 00 mov $0x106,%r12d + 40d905: be 0b 00 00 00 mov $0xb,%esi + 40d90a: e9 a7 fe ff ff jmpq 40d7b6 <__gettextparse+0x586> + 40d90f: 48 ba 00 00 00 00 ff movabs $0xffffffff00000000,%rdx + 40d916: ff ff ff + 40d919: 48 23 54 24 28 and 0x28(%rsp),%rdx + 40d91e: be 09 00 00 00 mov $0x9,%esi + 40d923: 41 bc 05 01 00 00 mov $0x105,%r12d + 40d929: 48 83 ca 04 or $0x4,%rdx + 40d92d: 48 89 54 24 28 mov %rdx,0x28(%rsp) + 40d932: e9 7f fe ff ff jmpq 40d7b6 <__gettextparse+0x586> + 40d937: 48 ba 00 00 00 00 ff movabs $0xffffffff00000000,%rdx + 40d93e: ff ff ff + 40d941: 48 23 54 24 28 and 0x28(%rsp),%rdx + 40d946: be 08 00 00 00 mov $0x8,%esi + 40d94b: 41 bc 04 01 00 00 mov $0x104,%r12d + 40d951: 48 83 ca 06 or $0x6,%rdx + 40d955: 48 89 54 24 28 mov %rdx,0x28(%rsp) + 40d95a: e9 57 fe ff ff jmpq 40d7b6 <__gettextparse+0x586> + 40d95f: 48 ba 00 00 00 00 ff movabs $0xffffffff00000000,%rdx + 40d966: ff ff ff + 40d969: 48 23 54 24 28 and 0x28(%rsp),%rdx + 40d96e: be 09 00 00 00 mov $0x9,%esi + 40d973: 41 bc 05 01 00 00 mov $0x105,%r12d + 40d979: 48 83 ca 03 or $0x3,%rdx + 40d97d: 48 89 54 24 28 mov %rdx,0x28(%rsp) + 40d982: e9 2f fe ff ff jmpq 40d7b6 <__gettextparse+0x586> + 40d987: 48 ba 00 00 00 00 ff movabs $0xffffffff00000000,%rdx + 40d98e: ff ff ff + 40d991: 48 23 54 24 28 and 0x28(%rsp),%rdx + 40d996: be 08 00 00 00 mov $0x8,%esi + 40d99b: 41 bc 04 01 00 00 mov $0x104,%r12d + 40d9a1: 48 83 ca 07 or $0x7,%rdx + 40d9a5: 48 89 54 24 28 mov %rdx,0x28(%rsp) + 40d9aa: e9 07 fe ff ff jmpq 40d7b6 <__gettextparse+0x586> + 40d9af: 49 89 ce mov %rcx,%r14 + 40d9b2: bb 02 00 00 00 mov $0x2,%ebx + 40d9b7: e9 99 fa ff ff jmpq 40d455 <__gettextparse+0x225> + 40d9bc: 49 89 ce mov %rcx,%r14 + 40d9bf: 31 db xor %ebx,%ebx + 40d9c1: e9 8f fa ff ff jmpq 40d455 <__gettextparse+0x225> + 40d9c6: 4d 89 fe mov %r15,%r14 + 40d9c9: bb 01 00 00 00 mov $0x1,%ebx + 40d9ce: e9 82 fa ff ff jmpq 40d455 <__gettextparse+0x225> + 40d9d3: 4a 8d 3c fd 00 00 00 lea 0x0(,%r15,8),%rdi + 40d9da: 00 + 40d9db: 4d 01 ff add %r15,%r15 + 40d9de: be ff ff ff ff mov $0xffffffff,%esi + 40d9e3: 4c 89 fa mov %r15,%rdx + 40d9e6: 41 b8 02 00 00 00 mov $0x2,%r8d + 40d9ec: 48 f7 df neg %rdi + 40d9ef: 48 f7 da neg %rdx + 40d9f2: e9 ce fa ff ff jmpq 40d4c5 <__gettextparse+0x295> + 40d9f7: 48 ba 00 00 00 00 ff movabs $0xffffffff00000000,%rdx + 40d9fe: ff ff ff + 40da01: 48 23 54 24 28 and 0x28(%rsp),%rdx + 40da06: 49 8d 79 02 lea 0x2(%r9),%rdi + 40da0a: be 07 00 00 00 mov $0x7,%esi + 40da0f: 41 bc 03 01 00 00 mov $0x103,%r12d + 40da15: 48 83 ca 0b or $0xb,%rdx + 40da19: 48 89 54 24 28 mov %rdx,0x28(%rsp) + 40da1e: e9 93 fd ff ff jmpq 40d7b6 <__gettextparse+0x586> + 40da23: 48 ba 00 00 00 00 ff movabs $0xffffffff00000000,%rdx + 40da2a: ff ff ff + 40da2d: 48 23 54 24 28 and 0x28(%rsp),%rdx + 40da32: 49 8d 79 02 lea 0x2(%r9),%rdi + 40da36: be 07 00 00 00 mov $0x7,%esi + 40da3b: 41 bc 03 01 00 00 mov $0x103,%r12d + 40da41: 48 83 ca 0a or $0xa,%rdx + 40da45: 48 89 54 24 28 mov %rdx,0x28(%rsp) + 40da4a: e9 67 fd ff ff jmpq 40d7b6 <__gettextparse+0x586> + 40da4f: 90 nop + +000000000040da50 <__gettext_extract_plural>: + 40da50: 41 55 push %r13 + 40da52: 41 54 push %r12 + 40da54: 55 push %rbp + 40da55: 53 push %rbx + 40da56: 48 89 f5 mov %rsi,%rbp + 40da59: 48 89 d3 mov %rdx,%rbx + 40da5c: 48 83 ec 28 sub $0x28,%rsp + 40da60: 48 85 ff test %rdi,%rdi + 40da63: 0f 84 9f 00 00 00 je 40db08 <__gettext_extract_plural+0xb8> + 40da69: 49 89 fd mov %rdi,%r13 + 40da6c: be 87 18 4a 00 mov $0x4a1887,%esi + 40da71: e8 aa 28 ff ff callq 400320 <__rela_iplt_end+0x58> + 40da76: be 8f 18 4a 00 mov $0x4a188f,%esi + 40da7b: 49 89 c4 mov %rax,%r12 + 40da7e: 4c 89 ef mov %r13,%rdi + 40da81: e8 9a 28 ff ff callq 400320 <__rela_iplt_end+0x58> + 40da86: 4d 85 e4 test %r12,%r12 + 40da89: 74 7d je 40db08 <__gettext_extract_plural+0xb8> + 40da8b: 48 85 c0 test %rax,%rax + 40da8e: 74 78 je 40db08 <__gettext_extract_plural+0xb8> + 40da90: 4c 8d 68 09 lea 0x9(%rax),%r13 + 40da94: 0f b6 40 09 movzbl 0x9(%rax),%eax + 40da98: 84 c0 test %al,%al + 40da9a: 74 6c je 40db08 <__gettext_extract_plural+0xb8> + 40da9c: 48 c7 c2 f0 ff ff ff mov $0xfffffffffffffff0,%rdx + 40daa3: 64 48 8b 0a mov %fs:(%rdx),%rcx + 40daa7: eb 14 jmp 40dabd <__gettext_extract_plural+0x6d> + 40daa9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 40dab0: 49 83 c5 01 add $0x1,%r13 + 40dab4: 41 0f b6 45 00 movzbl 0x0(%r13),%eax + 40dab9: 84 c0 test %al,%al + 40dabb: 74 4b je 40db08 <__gettext_extract_plural+0xb8> + 40dabd: 0f b6 d0 movzbl %al,%edx + 40dac0: f6 44 51 01 20 testb $0x20,0x1(%rcx,%rdx,2) + 40dac5: 75 e9 jne 40dab0 <__gettext_extract_plural+0x60> + 40dac7: 83 e8 30 sub $0x30,%eax + 40daca: 3c 09 cmp $0x9,%al + 40dacc: 77 3a ja 40db08 <__gettext_extract_plural+0xb8> + 40dace: 48 8d 74 24 08 lea 0x8(%rsp),%rsi + 40dad3: ba 0a 00 00 00 mov $0xa,%edx + 40dad8: 4c 89 ef mov %r13,%rdi + 40dadb: e8 70 11 00 00 callq 40ec50 <__strtoul> + 40dae0: 4c 39 6c 24 08 cmp %r13,0x8(%rsp) + 40dae5: 74 21 je 40db08 <__gettext_extract_plural+0xb8> + 40dae7: 48 8d 7c 24 10 lea 0x10(%rsp),%rdi + 40daec: 49 83 c4 07 add $0x7,%r12 + 40daf0: 48 89 03 mov %rax,(%rbx) + 40daf3: 4c 89 64 24 10 mov %r12,0x10(%rsp) + 40daf8: e8 33 f7 ff ff callq 40d230 <__gettextparse> + 40dafd: 85 c0 test %eax,%eax + 40daff: 74 21 je 40db22 <__gettext_extract_plural+0xd2> + 40db01: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 40db08: 48 c7 45 00 a0 18 4a movq $0x4a18a0,0x0(%rbp) + 40db0f: 00 + 40db10: 48 c7 03 02 00 00 00 movq $0x2,(%rbx) + 40db17: 48 83 c4 28 add $0x28,%rsp + 40db1b: 5b pop %rbx + 40db1c: 5d pop %rbp + 40db1d: 41 5c pop %r12 + 40db1f: 41 5d pop %r13 + 40db21: c3 retq + 40db22: 48 8b 44 24 18 mov 0x18(%rsp),%rax + 40db27: 48 89 45 00 mov %rax,0x0(%rbp) + 40db2b: eb ea jmp 40db17 <__gettext_extract_plural+0xc7> + 40db2d: 0f 1f 00 nopl (%rax) + +000000000040db30 <__hash_string>: + 40db30: 31 c0 xor %eax,%eax + 40db32: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 40db38: 0f b6 17 movzbl (%rdi),%edx + 40db3b: 84 d2 test %dl,%dl + 40db3d: 74 27 je 40db66 <__hash_string+0x36> + 40db3f: 48 c1 e0 04 shl $0x4,%rax + 40db43: 48 83 c7 01 add $0x1,%rdi + 40db47: 48 01 d0 add %rdx,%rax + 40db4a: 48 89 c2 mov %rax,%rdx + 40db4d: 81 e2 00 00 00 f0 and $0xf0000000,%edx + 40db53: 74 e3 je 40db38 <__hash_string+0x8> + 40db55: 48 31 d0 xor %rdx,%rax + 40db58: 48 c1 ea 18 shr $0x18,%rdx + 40db5c: 48 31 d0 xor %rdx,%rax + 40db5f: 0f b6 17 movzbl (%rdi),%edx + 40db62: 84 d2 test %dl,%dl + 40db64: 75 d9 jne 40db3f <__hash_string+0xf> + 40db66: f3 c3 repz retq + 40db68: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 40db6f: 00 + +000000000040db70 <_setjmp>: + 40db70: 31 f6 xor %esi,%esi + 40db72: e9 b9 18 04 00 jmpq 44f430 <__sigsetjmp> + 40db77: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 40db7e: 00 00 + +000000000040db80 : + 40db80: 64 8b 0c 25 d4 02 00 mov %fs:0x2d4,%ecx + 40db87: 00 + 40db88: 64 8b 04 25 d0 02 00 mov %fs:0x2d0,%eax + 40db8f: 00 + 40db90: 48 63 f0 movslq %eax,%rsi + 40db93: 85 f6 test %esi,%esi + 40db95: 75 31 jne 40dbc8 + 40db97: b8 ba 00 00 00 mov $0xba,%eax + 40db9c: 0f 05 syscall + 40db9e: 89 c1 mov %eax,%ecx + 40dba0: 64 89 04 25 d0 02 00 mov %eax,%fs:0x2d0 + 40dba7: 00 + 40dba8: 48 63 f0 movslq %eax,%rsi + 40dbab: 48 63 d7 movslq %edi,%rdx + 40dbae: b8 ea 00 00 00 mov $0xea,%eax + 40dbb3: 48 63 f9 movslq %ecx,%rdi + 40dbb6: 0f 05 syscall + 40dbb8: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 40dbbe: 77 20 ja 40dbe0 + 40dbc0: f3 c3 repz retq + 40dbc2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 40dbc8: 85 c9 test %ecx,%ecx + 40dbca: 7f df jg 40dbab + 40dbcc: 89 ca mov %ecx,%edx + 40dbce: f7 da neg %edx + 40dbd0: 81 e1 ff ff ff 7f and $0x7fffffff,%ecx + 40dbd6: 0f 44 d6 cmove %esi,%edx + 40dbd9: 89 d1 mov %edx,%ecx + 40dbdb: eb ce jmp 40dbab + 40dbdd: 0f 1f 00 nopl (%rax) + 40dbe0: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx + 40dbe7: f7 d8 neg %eax + 40dbe9: 64 89 02 mov %eax,%fs:(%rdx) + 40dbec: b8 ff ff ff ff mov $0xffffffff,%eax + 40dbf1: c3 retq + 40dbf2: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 40dbf9: 00 00 00 + 40dbfc: 0f 1f 40 00 nopl 0x0(%rax) + +000000000040dc00 : + 40dc00: 48 81 ec 28 01 00 00 sub $0x128,%rsp + 40dc07: 64 48 8b 14 25 10 00 mov %fs:0x10,%rdx + 40dc0e: 00 00 + 40dc10: 48 3b 15 21 e5 2b 00 cmp 0x2be521(%rip),%rdx # 6cc138 + 40dc17: 74 46 je 40dc5f + 40dc19: be 01 00 00 00 mov $0x1,%esi + 40dc1e: 31 c0 xor %eax,%eax + 40dc20: 83 3d 95 f5 2b 00 00 cmpl $0x0,0x2bf595(%rip) # 6cd1bc <__libc_multiple_threads> + 40dc27: 74 0c je 40dc35 + 40dc29: f0 0f b1 35 ff e4 2b lock cmpxchg %esi,0x2be4ff(%rip) # 6cc130 + 40dc30: 00 + 40dc31: 75 0b jne 40dc3e + 40dc33: eb 23 jmp 40dc58 + 40dc35: 0f b1 35 f4 e4 2b 00 cmpxchg %esi,0x2be4f4(%rip) # 6cc130 + 40dc3c: 74 1a je 40dc58 + 40dc3e: 48 8d 3d eb e4 2b 00 lea 0x2be4eb(%rip),%rdi # 6cc130 + 40dc45: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 40dc4c: e8 7f 49 03 00 callq 4425d0 <__lll_lock_wait_private> + 40dc51: 48 81 c4 80 00 00 00 add $0x80,%rsp + 40dc58: 48 89 15 d9 e4 2b 00 mov %rdx,0x2be4d9(%rip) # 6cc138 + 40dc5f: 8b 05 db e4 2b 00 mov 0x2be4db(%rip),%eax # 6cc140 + 40dc65: 83 05 c8 e4 2b 00 01 addl $0x1,0x2be4c8(%rip) # 6cc134 + 40dc6c: 85 c0 test %eax,%eax + 40dc6e: 74 43 je 40dcb3 + 40dc70: 83 f8 01 cmp $0x1,%eax + 40dc73: 74 77 je 40dcec + 40dc75: 83 f8 02 cmp $0x2,%eax + 40dc78: 0f 84 8e 00 00 00 je 40dd0c + 40dc7e: 83 f8 03 cmp $0x3,%eax + 40dc81: 0f 84 42 01 00 00 je 40ddc9 + 40dc87: 83 f8 04 cmp $0x4,%eax + 40dc8a: 0f 84 05 02 00 00 je 40de95 + 40dc90: 83 f8 05 cmp $0x5,%eax + 40dc93: 0f 84 1a 02 00 00 je 40deb3 + 40dc99: 83 f8 06 cmp $0x6,%eax + 40dc9c: 0f 84 34 02 00 00 je 40ded6 + 40dca2: 83 f8 07 cmp $0x7,%eax + 40dca5: 0f 84 2c 02 00 00 je 40ded7 + 40dcab: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 40dcb0: f4 hlt + 40dcb1: eb fd jmp 40dcb0 + 40dcb3: 31 c0 xor %eax,%eax + 40dcb5: b9 10 00 00 00 mov $0x10,%ecx + 40dcba: 48 89 e7 mov %rsp,%rdi + 40dcbd: f3 48 ab rep stos %rax,%es:(%rdi) + 40dcc0: 31 d2 xor %edx,%edx + 40dcc2: 48 89 e6 mov %rsp,%rsi + 40dcc5: bf 01 00 00 00 mov $0x1,%edi + 40dcca: c7 05 6c e4 2b 00 01 movl $0x1,0x2be46c(%rip) # 6cc140 + 40dcd1: 00 00 00 + 40dcd4: 48 c7 04 24 20 00 00 movq $0x20,(%rsp) + 40dcdb: 00 + 40dcdc: e8 5f 1a 04 00 callq 44f740 <__sigprocmask> + 40dce1: 8b 05 59 e4 2b 00 mov 0x2be459(%rip),%eax # 6cc140 + 40dce7: 83 f8 01 cmp $0x1,%eax + 40dcea: 75 89 jne 40dc75 + 40dcec: 31 ff xor %edi,%edi + 40dcee: c7 05 48 e4 2b 00 02 movl $0x2,0x2be448(%rip) # 6cc140 + 40dcf5: 00 00 00 + 40dcf8: e8 03 7d 00 00 callq 415a00 <_IO_flush_all_lockp> + 40dcfd: 8b 05 3d e4 2b 00 mov 0x2be43d(%rip),%eax # 6cc140 + 40dd03: 83 f8 02 cmp $0x2,%eax + 40dd06: 0f 85 72 ff ff ff jne 40dc7e + 40dd0c: 83 2d 21 e4 2b 00 01 subl $0x1,0x2be421(%rip) # 6cc134 + 40dd13: c7 05 23 e4 2b 00 00 movl $0x0,0x2be423(%rip) # 6cc140 + 40dd1a: 00 00 00 + 40dd1d: 75 41 jne 40dd60 + 40dd1f: 48 c7 05 0e e4 2b 00 movq $0x0,0x2be40e(%rip) # 6cc138 + 40dd26: 00 00 00 00 + 40dd2a: 83 3d 8b f4 2b 00 00 cmpl $0x0,0x2bf48b(%rip) # 6cd1bc <__libc_multiple_threads> + 40dd31: 74 0b je 40dd3e + 40dd33: f0 ff 0d f6 e3 2b 00 lock decl 0x2be3f6(%rip) # 6cc130 + 40dd3a: 75 0a jne 40dd46 + 40dd3c: eb 22 jmp 40dd60 + 40dd3e: ff 0d ec e3 2b 00 decl 0x2be3ec(%rip) # 6cc130 + 40dd44: 74 1a je 40dd60 + 40dd46: 48 8d 3d e3 e3 2b 00 lea 0x2be3e3(%rip),%rdi # 6cc130 + 40dd4d: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 40dd54: e8 a7 48 03 00 callq 442600 <__lll_unlock_wake_private> + 40dd59: 48 81 c4 80 00 00 00 add $0x80,%rsp + 40dd60: bf 06 00 00 00 mov $0x6,%edi + 40dd65: e8 16 fe ff ff callq 40db80 + 40dd6a: 64 48 8b 14 25 10 00 mov %fs:0x10,%rdx + 40dd71: 00 00 + 40dd73: 48 3b 15 be e3 2b 00 cmp 0x2be3be(%rip),%rdx # 6cc138 + 40dd7a: 74 46 je 40ddc2 + 40dd7c: be 01 00 00 00 mov $0x1,%esi + 40dd81: 31 c0 xor %eax,%eax + 40dd83: 83 3d 32 f4 2b 00 00 cmpl $0x0,0x2bf432(%rip) # 6cd1bc <__libc_multiple_threads> + 40dd8a: 74 0c je 40dd98 + 40dd8c: f0 0f b1 35 9c e3 2b lock cmpxchg %esi,0x2be39c(%rip) # 6cc130 + 40dd93: 00 + 40dd94: 75 0b jne 40dda1 + 40dd96: eb 23 jmp 40ddbb + 40dd98: 0f b1 35 91 e3 2b 00 cmpxchg %esi,0x2be391(%rip) # 6cc130 + 40dd9f: 74 1a je 40ddbb + 40dda1: 48 8d 3d 88 e3 2b 00 lea 0x2be388(%rip),%rdi # 6cc130 + 40dda8: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 40ddaf: e8 1c 48 03 00 callq 4425d0 <__lll_lock_wait_private> + 40ddb4: 48 81 c4 80 00 00 00 add $0x80,%rsp + 40ddbb: 48 89 15 76 e3 2b 00 mov %rdx,0x2be376(%rip) # 6cc138 + 40ddc2: 83 05 6b e3 2b 00 01 addl $0x1,0x2be36b(%rip) # 6cc134 + 40ddc9: 48 8d b4 24 80 00 00 lea 0x80(%rsp),%rsi + 40ddd0: 00 + 40ddd1: 31 c0 xor %eax,%eax + 40ddd3: b9 13 00 00 00 mov $0x13,%ecx + 40ddd8: 31 d2 xor %edx,%edx + 40ddda: c7 05 5c e3 2b 00 04 movl $0x4,0x2be35c(%rip) # 6cc140 + 40dde1: 00 00 00 + 40dde4: 48 89 f7 mov %rsi,%rdi + 40dde7: f3 48 ab rep stos %rax,%es:(%rdi) + 40ddea: 48 c7 84 24 88 00 00 movq $0xffffffffffffffff,0x88(%rsp) + 40ddf1: 00 ff ff ff ff + 40ddf6: bf 06 00 00 00 mov $0x6,%edi + 40ddfb: 48 c7 46 10 ff ff ff movq $0xffffffffffffffff,0x10(%rsi) + 40de02: ff + 40de03: 48 c7 46 18 ff ff ff movq $0xffffffffffffffff,0x18(%rsi) + 40de0a: ff + 40de0b: 48 c7 46 20 ff ff ff movq $0xffffffffffffffff,0x20(%rsi) + 40de12: ff + 40de13: 48 c7 46 28 ff ff ff movq $0xffffffffffffffff,0x28(%rsi) + 40de1a: ff + 40de1b: 48 c7 46 30 ff ff ff movq $0xffffffffffffffff,0x30(%rsi) + 40de22: ff + 40de23: 48 c7 46 38 ff ff ff movq $0xffffffffffffffff,0x38(%rsi) + 40de2a: ff + 40de2b: 48 c7 46 40 ff ff ff movq $0xffffffffffffffff,0x40(%rsi) + 40de32: ff + 40de33: 48 c7 46 48 ff ff ff movq $0xffffffffffffffff,0x48(%rsi) + 40de3a: ff + 40de3b: 48 c7 46 50 ff ff ff movq $0xffffffffffffffff,0x50(%rsi) + 40de42: ff + 40de43: 48 c7 46 58 ff ff ff movq $0xffffffffffffffff,0x58(%rsi) + 40de4a: ff + 40de4b: 48 c7 46 60 ff ff ff movq $0xffffffffffffffff,0x60(%rsi) + 40de52: ff + 40de53: 48 c7 46 68 ff ff ff movq $0xffffffffffffffff,0x68(%rsi) + 40de5a: ff + 40de5b: 48 c7 46 70 ff ff ff movq $0xffffffffffffffff,0x70(%rsi) + 40de62: ff + 40de63: 48 c7 46 78 ff ff ff movq $0xffffffffffffffff,0x78(%rsi) + 40de6a: ff + 40de6b: 48 c7 86 80 00 00 00 movq $0xffffffffffffffff,0x80(%rsi) + 40de72: ff ff ff ff + 40de76: c7 84 24 08 01 00 00 movl $0x0,0x108(%rsp) + 40de7d: 00 00 00 00 + 40de81: e8 8a 18 04 00 callq 44f710 <__sigaction> + 40de86: 8b 05 b4 e2 2b 00 mov 0x2be2b4(%rip),%eax # 6cc140 + 40de8c: 83 f8 04 cmp $0x4,%eax + 40de8f: 0f 85 fb fd ff ff jne 40dc90 + 40de95: c7 05 a1 e2 2b 00 05 movl $0x5,0x2be2a1(%rip) # 6cc140 + 40de9c: 00 00 00 + 40de9f: e8 4c 35 00 00 callq 4113f0 <__fcloseall> + 40dea4: 8b 05 96 e2 2b 00 mov 0x2be296(%rip),%eax # 6cc140 + 40deaa: 83 f8 05 cmp $0x5,%eax + 40dead: 0f 85 e6 fd ff ff jne 40dc99 + 40deb3: bf 06 00 00 00 mov $0x6,%edi + 40deb8: c7 05 7e e2 2b 00 06 movl $0x6,0x2be27e(%rip) # 6cc140 + 40debf: 00 00 00 + 40dec2: e8 b9 fc ff ff callq 40db80 + 40dec7: 8b 05 73 e2 2b 00 mov 0x2be273(%rip),%eax # 6cc140 + 40decd: 83 f8 06 cmp $0x6,%eax + 40ded0: 0f 85 cc fd ff ff jne 40dca2 + 40ded6: f4 hlt + 40ded7: bf 7f 00 00 00 mov $0x7f,%edi + 40dedc: c7 05 5a e2 2b 00 08 movl $0x8,0x2be25a(%rip) # 6cc140 + 40dee3: 00 00 00 + 40dee6: e8 e5 08 03 00 callq 43e7d0 <_exit> + 40deeb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + +000000000040def0 : + 40def0: 41 57 push %r15 + 40def2: 41 56 push %r14 + 40def4: 48 89 f8 mov %rdi,%rax + 40def7: 41 55 push %r13 + 40def9: 41 54 push %r12 + 40defb: 49 89 d4 mov %rdx,%r12 + 40defe: 55 push %rbp + 40deff: 53 push %rbx + 40df00: 49 d1 ec shr %r12 + 40df03: 4d 89 e7 mov %r12,%r15 + 40df06: 48 89 d5 mov %rdx,%rbp + 40df09: 48 83 ec 58 sub $0x58,%rsp + 40df0d: 4c 29 e5 sub %r12,%rbp + 40df10: 4c 0f af 3f imul (%rdi),%r15 + 40df14: 48 89 7c 24 18 mov %rdi,0x18(%rsp) + 40df19: 48 89 74 24 28 mov %rsi,0x28(%rsp) + 40df1e: 48 89 54 24 48 mov %rdx,0x48(%rsp) + 40df23: 49 01 f7 add %rsi,%r15 + 40df26: 49 83 fc 01 cmp $0x1,%r12 + 40df2a: 76 0b jbe 40df37 + 40df2c: 4c 89 e2 mov %r12,%rdx + 40df2f: 48 89 c7 mov %rax,%rdi + 40df32: e8 b9 ff ff ff callq 40def0 + 40df37: 48 83 fd 01 cmp $0x1,%rbp + 40df3b: 76 10 jbe 40df4d + 40df3d: 48 8b 7c 24 18 mov 0x18(%rsp),%rdi + 40df42: 48 89 ea mov %rbp,%rdx + 40df45: 4c 89 fe mov %r15,%rsi + 40df48: e8 a3 ff ff ff callq 40def0 + 40df4d: 48 8b 44 24 18 mov 0x18(%rsp),%rax + 40df52: 48 8b 38 mov (%rax),%rdi + 40df55: 48 8b 58 20 mov 0x20(%rax),%rbx + 40df59: 4c 8b 70 10 mov 0x10(%rax),%r14 + 40df5d: 48 89 7c 24 10 mov %rdi,0x10(%rsp) + 40df62: 48 8b 78 18 mov 0x18(%rax),%rdi + 40df66: 48 8b 40 08 mov 0x8(%rax),%rax + 40df6a: 48 89 7c 24 08 mov %rdi,0x8(%rsp) + 40df6f: 48 83 f8 01 cmp $0x1,%rax + 40df73: 0f 84 df 02 00 00 je 40e258 + 40df79: 0f 82 61 02 00 00 jb 40e1e0 + 40df7f: 48 83 f8 02 cmp $0x2,%rax + 40df83: 74 73 je 40dff8 + 40df85: 48 83 f8 03 cmp $0x3,%rax + 40df89: 0f 85 29 03 00 00 jne 40e2b8 + 40df8f: 48 85 ed test %rbp,%rbp + 40df92: 0f 84 91 03 00 00 je 40e329 + 40df98: 4d 85 e4 test %r12,%r12 + 40df9b: 4c 8b 6c 24 28 mov 0x28(%rsp),%r13 + 40dfa0: 75 32 jne 40dfd4 + 40dfa2: e9 82 03 00 00 jmpq 40e329 + 40dfa7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 40dfae: 00 00 + 40dfb0: 49 8b 07 mov (%r15),%rax + 40dfb3: 48 83 ed 01 sub $0x1,%rbp + 40dfb7: 49 83 c7 08 add $0x8,%r15 + 40dfbb: 48 89 03 mov %rax,(%rbx) + 40dfbe: 48 83 c3 08 add $0x8,%rbx + 40dfc2: 4d 85 e4 test %r12,%r12 + 40dfc5: 0f 84 85 01 00 00 je 40e150 + 40dfcb: 48 85 ed test %rbp,%rbp + 40dfce: 0f 84 7c 01 00 00 je 40e150 + 40dfd4: 48 8b 54 24 08 mov 0x8(%rsp),%rdx + 40dfd9: 49 8b 37 mov (%r15),%rsi + 40dfdc: 49 8b 7d 00 mov 0x0(%r13),%rdi + 40dfe0: 41 ff d6 callq *%r14 + 40dfe3: 85 c0 test %eax,%eax + 40dfe5: 7f c9 jg 40dfb0 + 40dfe7: 49 8b 45 00 mov 0x0(%r13),%rax + 40dfeb: 49 83 ec 01 sub $0x1,%r12 + 40dfef: 49 83 c5 08 add $0x8,%r13 + 40dff3: eb c6 jmp 40dfbb + 40dff5: 0f 1f 00 nopl (%rax) + 40dff8: 48 8b 74 24 10 mov 0x10(%rsp),%rsi + 40dffd: b8 08 00 00 00 mov $0x8,%eax + 40e002: 4c 8b 6c 24 28 mov 0x28(%rsp),%r13 + 40e007: 4c 89 74 24 30 mov %r14,0x30(%rsp) + 40e00c: 48 29 f0 sub %rsi,%rax + 40e00f: 4c 89 6c 24 20 mov %r13,0x20(%rsp) + 40e014: 49 89 f6 mov %rsi,%r14 + 40e017: 48 89 44 24 38 mov %rax,0x38(%rsp) + 40e01c: b8 10 00 00 00 mov $0x10,%eax + 40e021: 49 89 ed mov %rbp,%r13 + 40e024: 48 29 f0 sub %rsi,%rax + 40e027: 4d 85 e4 test %r12,%r12 + 40e02a: 4c 89 fd mov %r15,%rbp + 40e02d: 48 89 44 24 40 mov %rax,0x40(%rsp) + 40e032: 0f 84 09 01 00 00 je 40e141 + 40e038: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 40e03f: 00 + 40e040: 4d 85 ed test %r13,%r13 + 40e043: 0f 84 f8 00 00 00 je 40e141 + 40e049: 48 8b 54 24 08 mov 0x8(%rsp),%rdx + 40e04e: 48 89 ee mov %rbp,%rsi + 40e051: 48 8b 7c 24 20 mov 0x20(%rsp),%rdi + 40e056: 48 8b 44 24 30 mov 0x30(%rsp),%rax + 40e05b: 4e 8d 3c 33 lea (%rbx,%r14,1),%r15 + 40e05f: ff d0 callq *%rax + 40e061: 85 c0 test %eax,%eax + 40e063: 0f 8e 47 01 00 00 jle 40e1b0 + 40e069: 48 89 e8 mov %rbp,%rax + 40e06c: 49 83 ed 01 sub $0x1,%r13 + 40e070: 4c 01 f5 add %r14,%rbp + 40e073: 4c 39 fb cmp %r15,%rbx + 40e076: 0f 83 b9 00 00 00 jae 40e135 + 40e07c: 48 8b 7c 24 38 mov 0x38(%rsp),%rdi + 40e081: 48 8b 74 24 40 mov 0x40(%rsp),%rsi + 40e086: 49 8d 57 07 lea 0x7(%r15),%rdx + 40e08a: 4c 01 ff add %r15,%rdi + 40e08d: 49 8d 0c 37 lea (%r15,%rsi,1),%rcx + 40e091: 48 29 fa sub %rdi,%rdx + 40e094: 48 c1 ea 03 shr $0x3,%rdx + 40e098: 48 83 c2 01 add $0x1,%rdx + 40e09c: 48 39 c8 cmp %rcx,%rax + 40e09f: 48 8d 48 10 lea 0x10(%rax),%rcx + 40e0a3: 40 0f 93 c6 setae %sil + 40e0a7: 48 39 cb cmp %rcx,%rbx + 40e0aa: 0f 93 c1 setae %cl + 40e0ad: 40 08 ce or %cl,%sil + 40e0b0: 0f 84 da 00 00 00 je 40e190 + 40e0b6: 48 83 fa 18 cmp $0x18,%rdx + 40e0ba: 0f 86 d0 00 00 00 jbe 40e190 + 40e0c0: 48 89 c1 mov %rax,%rcx + 40e0c3: 48 c1 e1 3c shl $0x3c,%rcx + 40e0c7: 48 c1 e9 3f shr $0x3f,%rcx + 40e0cb: 48 39 d1 cmp %rdx,%rcx + 40e0ce: 48 0f 47 ca cmova %rdx,%rcx + 40e0d2: 48 85 c9 test %rcx,%rcx + 40e0d5: 0f 84 f5 00 00 00 je 40e1d0 + 40e0db: 48 8b 30 mov (%rax),%rsi + 40e0de: 4c 8d 48 08 lea 0x8(%rax),%r9 + 40e0e2: 48 89 33 mov %rsi,(%rbx) + 40e0e5: 48 29 ca sub %rcx,%rdx + 40e0e8: 48 c1 e1 03 shl $0x3,%rcx + 40e0ec: 45 31 db xor %r11d,%r11d + 40e0ef: 48 8d 72 fe lea -0x2(%rdx),%rsi + 40e0f3: 48 01 c8 add %rcx,%rax + 40e0f6: 48 01 cb add %rcx,%rbx + 40e0f9: 31 c9 xor %ecx,%ecx + 40e0fb: 48 d1 ee shr %rsi + 40e0fe: 48 83 c6 01 add $0x1,%rsi + 40e102: 4c 8d 14 36 lea (%rsi,%rsi,1),%r10 + 40e106: 66 0f 6f 04 08 movdqa (%rax,%rcx,1),%xmm0 + 40e10b: 49 83 c3 01 add $0x1,%r11 + 40e10f: 0f 11 04 0b movups %xmm0,(%rbx,%rcx,1) + 40e113: 48 83 c1 10 add $0x10,%rcx + 40e117: 49 39 f3 cmp %rsi,%r11 + 40e11a: 72 ea jb 40e106 + 40e11c: 4a 8d 04 d5 00 00 00 lea 0x0(,%r10,8),%rax + 40e123: 00 + 40e124: 48 01 c7 add %rax,%rdi + 40e127: 49 01 c1 add %rax,%r9 + 40e12a: 49 39 d2 cmp %rdx,%r10 + 40e12d: 74 06 je 40e135 + 40e12f: 49 8b 01 mov (%r9),%rax + 40e132: 48 89 07 mov %rax,(%rdi) + 40e135: 4d 85 e4 test %r12,%r12 + 40e138: 4c 89 fb mov %r15,%rbx + 40e13b: 0f 85 ff fe ff ff jne 40e040 + 40e141: 4c 89 ed mov %r13,%rbp + 40e144: 4c 8b 6c 24 20 mov 0x20(%rsp),%r13 + 40e149: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 40e150: 4d 85 e4 test %r12,%r12 + 40e153: 0f 85 df 00 00 00 jne 40e238 + 40e159: 48 8b 54 24 48 mov 0x48(%rsp),%rdx + 40e15e: 48 8b 44 24 18 mov 0x18(%rsp),%rax + 40e163: 48 8b 7c 24 28 mov 0x28(%rsp),%rdi + 40e168: 48 29 ea sub %rbp,%rdx + 40e16b: 48 8b 70 20 mov 0x20(%rax),%rsi + 40e16f: 48 0f af 54 24 10 imul 0x10(%rsp),%rdx + 40e175: 48 83 c4 58 add $0x58,%rsp + 40e179: 5b pop %rbx + 40e17a: 5d pop %rbp + 40e17b: 41 5c pop %r12 + 40e17d: 41 5d pop %r13 + 40e17f: 41 5e pop %r14 + 40e181: 41 5f pop %r15 + 40e183: e9 98 de 01 00 jmpq 42c020 + 40e188: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 40e18f: 00 + 40e190: 48 83 c0 08 add $0x8,%rax + 40e194: 48 8b 50 f8 mov -0x8(%rax),%rdx + 40e198: 48 83 c3 08 add $0x8,%rbx + 40e19c: 49 39 df cmp %rbx,%r15 + 40e19f: 48 89 53 f8 mov %rdx,-0x8(%rbx) + 40e1a3: 77 eb ja 40e190 + 40e1a5: eb 8e jmp 40e135 + 40e1a7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 40e1ae: 00 00 + 40e1b0: 48 8b 7c 24 20 mov 0x20(%rsp),%rdi + 40e1b5: 49 83 ec 01 sub $0x1,%r12 + 40e1b9: 48 89 f8 mov %rdi,%rax + 40e1bc: 4c 01 f7 add %r14,%rdi + 40e1bf: 48 89 7c 24 20 mov %rdi,0x20(%rsp) + 40e1c4: e9 aa fe ff ff jmpq 40e073 + 40e1c9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 40e1d0: 49 89 c1 mov %rax,%r9 + 40e1d3: 48 89 df mov %rbx,%rdi + 40e1d6: e9 0a ff ff ff jmpq 40e0e5 + 40e1db: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 40e1e0: 4d 85 e4 test %r12,%r12 + 40e1e3: 4c 8b 6c 24 28 mov 0x28(%rsp),%r13 + 40e1e8: 75 20 jne 40e20a + 40e1ea: e9 61 ff ff ff jmpq 40e150 + 40e1ef: 90 nop + 40e1f0: 41 8b 07 mov (%r15),%eax + 40e1f3: 48 83 ed 01 sub $0x1,%rbp + 40e1f7: 49 83 c7 04 add $0x4,%r15 + 40e1fb: 89 03 mov %eax,(%rbx) + 40e1fd: 48 83 c3 04 add $0x4,%rbx + 40e201: 4d 85 e4 test %r12,%r12 + 40e204: 0f 84 46 ff ff ff je 40e150 + 40e20a: 48 85 ed test %rbp,%rbp + 40e20d: 0f 84 3d ff ff ff je 40e150 + 40e213: 48 8b 54 24 08 mov 0x8(%rsp),%rdx + 40e218: 4c 89 fe mov %r15,%rsi + 40e21b: 4c 89 ef mov %r13,%rdi + 40e21e: 41 ff d6 callq *%r14 + 40e221: 85 c0 test %eax,%eax + 40e223: 7f cb jg 40e1f0 + 40e225: 41 8b 45 00 mov 0x0(%r13),%eax + 40e229: 49 83 ec 01 sub $0x1,%r12 + 40e22d: 49 83 c5 04 add $0x4,%r13 + 40e231: eb c8 jmp 40e1fb + 40e233: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 40e238: 4c 89 e2 mov %r12,%rdx + 40e23b: 4c 89 ee mov %r13,%rsi + 40e23e: 48 89 df mov %rbx,%rdi + 40e241: 48 0f af 54 24 10 imul 0x10(%rsp),%rdx + 40e247: e8 d4 dd 01 00 callq 42c020 + 40e24c: e9 08 ff ff ff jmpq 40e159 + 40e251: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 40e258: 48 85 ed test %rbp,%rbp + 40e25b: 0f 84 c8 00 00 00 je 40e329 + 40e261: 4d 85 e4 test %r12,%r12 + 40e264: 4c 8b 6c 24 28 mov 0x28(%rsp),%r13 + 40e269: 75 29 jne 40e294 + 40e26b: e9 b9 00 00 00 jmpq 40e329 + 40e270: 49 8b 07 mov (%r15),%rax + 40e273: 48 83 ed 01 sub $0x1,%rbp + 40e277: 49 83 c7 08 add $0x8,%r15 + 40e27b: 48 89 03 mov %rax,(%rbx) + 40e27e: 48 83 c3 08 add $0x8,%rbx + 40e282: 4d 85 e4 test %r12,%r12 + 40e285: 0f 84 c5 fe ff ff je 40e150 + 40e28b: 48 85 ed test %rbp,%rbp + 40e28e: 0f 84 bc fe ff ff je 40e150 + 40e294: 48 8b 54 24 08 mov 0x8(%rsp),%rdx + 40e299: 4c 89 fe mov %r15,%rsi + 40e29c: 4c 89 ef mov %r13,%rdi + 40e29f: 41 ff d6 callq *%r14 + 40e2a2: 85 c0 test %eax,%eax + 40e2a4: 7f ca jg 40e270 + 40e2a6: 49 8b 45 00 mov 0x0(%r13),%rax + 40e2aa: 49 83 ec 01 sub $0x1,%r12 + 40e2ae: 49 83 c5 08 add $0x8,%r13 + 40e2b2: eb c7 jmp 40e27b + 40e2b4: 0f 1f 40 00 nopl 0x0(%rax) + 40e2b8: 4c 8b 6c 24 28 mov 0x28(%rsp),%r13 + 40e2bd: 4d 85 e4 test %r12,%r12 + 40e2c0: 0f 84 8a fe ff ff je 40e150 + 40e2c6: 48 85 ed test %rbp,%rbp + 40e2c9: 0f 84 81 fe ff ff je 40e150 + 40e2cf: 48 8b 54 24 08 mov 0x8(%rsp),%rdx + 40e2d4: 4c 89 fe mov %r15,%rsi + 40e2d7: 4c 89 ef mov %r13,%rdi + 40e2da: 41 ff d6 callq *%r14 + 40e2dd: 85 c0 test %eax,%eax + 40e2df: 48 8b 54 24 10 mov 0x10(%rsp),%rdx + 40e2e4: 7e 2a jle 40e310 + 40e2e6: 4c 89 fe mov %r15,%rsi + 40e2e9: 48 89 df mov %rbx,%rdi + 40e2ec: 48 83 ed 01 sub $0x1,%rbp + 40e2f0: e8 cb 82 01 00 callq 4265c0 <__mempcpy> + 40e2f5: 4c 03 7c 24 10 add 0x10(%rsp),%r15 + 40e2fa: 4d 85 e4 test %r12,%r12 + 40e2fd: 48 89 c3 mov %rax,%rbx + 40e300: 75 c4 jne 40e2c6 + 40e302: e9 49 fe ff ff jmpq 40e150 + 40e307: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 40e30e: 00 00 + 40e310: 4c 89 ee mov %r13,%rsi + 40e313: 48 89 df mov %rbx,%rdi + 40e316: 49 83 ec 01 sub $0x1,%r12 + 40e31a: e8 a1 82 01 00 callq 4265c0 <__mempcpy> + 40e31f: 4c 03 6c 24 10 add 0x10(%rsp),%r13 + 40e324: 48 89 c3 mov %rax,%rbx + 40e327: eb 94 jmp 40e2bd + 40e329: 4c 8b 6c 24 28 mov 0x28(%rsp),%r13 + 40e32e: e9 1d fe ff ff jmpq 40e150 + 40e333: 0f 1f 00 nopl (%rax) + 40e336: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 40e33d: 00 00 00 + +000000000040e340 <__qsort_r>: + 40e340: 55 push %rbp + 40e341: 48 89 e5 mov %rsp,%rbp + 40e344: 41 57 push %r15 + 40e346: 41 56 push %r14 + 40e348: 41 55 push %r13 + 40e34a: 41 54 push %r12 + 40e34c: 49 89 fe mov %rdi,%r14 + 40e34f: 53 push %rbx + 40e350: 49 89 cf mov %rcx,%r15 + 40e353: 48 89 d3 mov %rdx,%rbx + 40e356: 49 89 f5 mov %rsi,%r13 + 40e359: 48 83 ec 68 sub $0x68,%rsp + 40e35d: 48 83 fa 20 cmp $0x20,%rdx + 40e361: 48 89 75 88 mov %rsi,-0x78(%rbp) + 40e365: 0f 87 f5 02 00 00 ja 40e660 <__qsort_r+0x320> + 40e36b: 4c 0f af ea imul %rdx,%r13 + 40e36f: 49 81 fd ff 03 00 00 cmp $0x3ff,%r13 + 40e376: 0f 86 f8 02 00 00 jbe 40e674 <__qsort_r+0x334> + 40e37c: 8b 15 ce dd 2b 00 mov 0x2bddce(%rip),%edx # 6cc150 + 40e382: 85 d2 test %edx,%edx + 40e384: 0f 84 96 03 00 00 je 40e720 <__qsort_r+0x3e0> + 40e38a: 48 63 f2 movslq %edx,%rsi + 40e38d: 4c 89 e8 mov %r13,%rax + 40e390: 31 d2 xor %edx,%edx + 40e392: 48 f7 f6 div %rsi + 40e395: 48 3b 05 ac dd 2b 00 cmp 0x2bddac(%rip),%rax # 6cc148 + 40e39c: 0f 87 fe 02 00 00 ja 40e6a0 <__qsort_r+0x360> + 40e3a2: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 40e3a9: 4c 89 ef mov %r13,%rdi + 40e3ac: 4c 89 45 98 mov %r8,-0x68(%rbp) + 40e3b0: 64 44 8b 20 mov %fs:(%rax),%r12d + 40e3b4: e8 57 f6 00 00 callq 41da10 <__libc_malloc> + 40e3b9: 48 c7 c1 d0 ff ff ff mov $0xffffffffffffffd0,%rcx + 40e3c0: 48 85 c0 test %rax,%rax + 40e3c3: 48 89 85 78 ff ff ff mov %rax,-0x88(%rbp) + 40e3ca: 4c 8b 45 98 mov -0x68(%rbp),%r8 + 40e3ce: 64 44 89 21 mov %r12d,%fs:(%rcx) + 40e3d2: 0f 84 c8 02 00 00 je 40e6a0 <__qsort_r+0x360> + 40e3d8: 48 89 45 c0 mov %rax,-0x40(%rbp) + 40e3dc: 48 89 c6 mov %rax,%rsi + 40e3df: 48 83 fb 20 cmp $0x20,%rbx + 40e3e3: 48 89 5d a0 mov %rbx,-0x60(%rbp) + 40e3e7: 48 c7 45 a8 04 00 00 movq $0x4,-0x58(%rbp) + 40e3ee: 00 + 40e3ef: 4c 89 7d b0 mov %r15,-0x50(%rbp) + 40e3f3: 4c 89 45 b8 mov %r8,-0x48(%rbp) + 40e3f7: 0f 86 cb 02 00 00 jbe 40e6c8 <__qsort_r+0x388> + 40e3fd: 48 8b 45 88 mov -0x78(%rbp),%rax + 40e401: 4c 8d 0c c5 00 00 00 lea 0x0(,%rax,8),%r9 + 40e408: 00 + 40e409: 4e 8d 24 0e lea (%rsi,%r9,1),%r12 + 40e40d: 4b 8d 04 0c lea (%r12,%r9,1),%rax + 40e411: 49 39 c4 cmp %rax,%r12 + 40e414: 48 89 45 80 mov %rax,-0x80(%rbp) + 40e418: 0f 83 94 03 00 00 jae 40e7b2 <__qsort_r+0x472> + 40e41e: 49 8d 4c 24 08 lea 0x8(%r12),%rcx + 40e423: 4c 8d 58 07 lea 0x7(%rax),%r11 + 40e427: 4c 89 e2 mov %r12,%rdx + 40e42a: 48 c1 e2 3c shl $0x3c,%rdx + 40e42e: 49 29 cb sub %rcx,%r11 + 40e431: 48 c1 ea 3f shr $0x3f,%rdx + 40e435: 49 c1 eb 03 shr $0x3,%r11 + 40e439: 49 8d 7b 01 lea 0x1(%r11),%rdi + 40e43d: 48 39 fa cmp %rdi,%rdx + 40e440: 48 0f 47 d7 cmova %rdi,%rdx + 40e444: 48 83 ff 0a cmp $0xa,%rdi + 40e448: 0f 87 29 03 00 00 ja 40e777 <__qsort_r+0x437> + 40e44e: 48 89 fa mov %rdi,%rdx + 40e451: 48 83 fa 01 cmp $0x1,%rdx + 40e455: 4d 89 34 24 mov %r14,(%r12) + 40e459: 49 8d 04 1e lea (%r14,%rbx,1),%rax + 40e45d: 0f 84 a9 00 00 00 je 40e50c <__qsort_r+0x1cc> + 40e463: 49 89 44 24 08 mov %rax,0x8(%r12) + 40e468: 48 01 d8 add %rbx,%rax + 40e46b: 48 83 fa 02 cmp $0x2,%rdx + 40e46f: 49 8d 4c 24 10 lea 0x10(%r12),%rcx + 40e474: 0f 84 92 00 00 00 je 40e50c <__qsort_r+0x1cc> + 40e47a: 49 89 44 24 10 mov %rax,0x10(%r12) + 40e47f: 48 01 d8 add %rbx,%rax + 40e482: 48 83 fa 03 cmp $0x3,%rdx + 40e486: 49 8d 4c 24 18 lea 0x18(%r12),%rcx + 40e48b: 74 7f je 40e50c <__qsort_r+0x1cc> + 40e48d: 49 89 44 24 18 mov %rax,0x18(%r12) + 40e492: 48 01 d8 add %rbx,%rax + 40e495: 48 83 fa 04 cmp $0x4,%rdx + 40e499: 49 8d 4c 24 20 lea 0x20(%r12),%rcx + 40e49e: 74 6c je 40e50c <__qsort_r+0x1cc> + 40e4a0: 49 89 44 24 20 mov %rax,0x20(%r12) + 40e4a5: 48 01 d8 add %rbx,%rax + 40e4a8: 48 83 fa 05 cmp $0x5,%rdx + 40e4ac: 49 8d 4c 24 28 lea 0x28(%r12),%rcx + 40e4b1: 74 59 je 40e50c <__qsort_r+0x1cc> + 40e4b3: 49 89 44 24 28 mov %rax,0x28(%r12) + 40e4b8: 48 01 d8 add %rbx,%rax + 40e4bb: 48 83 fa 06 cmp $0x6,%rdx + 40e4bf: 49 8d 4c 24 30 lea 0x30(%r12),%rcx + 40e4c4: 74 46 je 40e50c <__qsort_r+0x1cc> + 40e4c6: 49 89 44 24 30 mov %rax,0x30(%r12) + 40e4cb: 48 01 d8 add %rbx,%rax + 40e4ce: 48 83 fa 07 cmp $0x7,%rdx + 40e4d2: 49 8d 4c 24 38 lea 0x38(%r12),%rcx + 40e4d7: 74 33 je 40e50c <__qsort_r+0x1cc> + 40e4d9: 49 89 44 24 38 mov %rax,0x38(%r12) + 40e4de: 48 01 d8 add %rbx,%rax + 40e4e1: 48 83 fa 08 cmp $0x8,%rdx + 40e4e5: 49 8d 4c 24 40 lea 0x40(%r12),%rcx + 40e4ea: 74 20 je 40e50c <__qsort_r+0x1cc> + 40e4ec: 49 89 44 24 40 mov %rax,0x40(%r12) + 40e4f1: 48 01 d8 add %rbx,%rax + 40e4f4: 48 83 fa 0a cmp $0xa,%rdx + 40e4f8: 49 8d 4c 24 48 lea 0x48(%r12),%rcx + 40e4fd: 75 0d jne 40e50c <__qsort_r+0x1cc> + 40e4ff: 49 8d 4c 24 50 lea 0x50(%r12),%rcx + 40e504: 49 89 44 24 48 mov %rax,0x48(%r12) + 40e509: 48 01 d8 add %rbx,%rax + 40e50c: 48 39 d7 cmp %rdx,%rdi + 40e50f: 74 72 je 40e583 <__qsort_r+0x243> + 40e511: 48 29 d7 sub %rdx,%rdi + 40e514: 4c 8d 47 fe lea -0x2(%rdi),%r8 + 40e518: 49 d1 e8 shr %r8 + 40e51b: 49 83 c0 01 add $0x1,%r8 + 40e51f: 49 39 d3 cmp %rdx,%r11 + 40e522: 4f 8d 14 00 lea (%r8,%r8,1),%r10 + 40e526: 74 58 je 40e580 <__qsort_r+0x240> + 40e528: 4c 8d 1c 03 lea (%rbx,%rax,1),%r11 + 40e52c: 48 89 45 98 mov %rax,-0x68(%rbp) + 40e530: 48 03 55 88 add -0x78(%rbp),%rdx + 40e534: f3 0f 7e 45 98 movq -0x68(%rbp),%xmm0 + 40e539: 4c 89 5d 98 mov %r11,-0x68(%rbp) + 40e53d: 4c 8d 1c 1b lea (%rbx,%rbx,1),%r11 + 40e541: 0f 16 45 98 movhps -0x68(%rbp),%xmm0 + 40e545: 4c 89 5d 98 mov %r11,-0x68(%rbp) + 40e549: 48 8d 34 d6 lea (%rsi,%rdx,8),%rsi + 40e54d: 31 d2 xor %edx,%edx + 40e54f: f3 0f 7e 4d 98 movq -0x68(%rbp),%xmm1 + 40e554: 66 0f 6c c9 punpcklqdq %xmm1,%xmm1 + 40e558: 48 83 c2 01 add $0x1,%rdx + 40e55c: 48 83 c6 10 add $0x10,%rsi + 40e560: 0f 29 46 f0 movaps %xmm0,-0x10(%rsi) + 40e564: 66 0f d4 c1 paddq %xmm1,%xmm0 + 40e568: 4c 39 c2 cmp %r8,%rdx + 40e56b: 72 eb jb 40e558 <__qsort_r+0x218> + 40e56d: 48 89 da mov %rbx,%rdx + 40e570: 4a 8d 0c d1 lea (%rcx,%r10,8),%rcx + 40e574: 49 0f af d2 imul %r10,%rdx + 40e578: 48 01 d0 add %rdx,%rax + 40e57b: 4c 39 d7 cmp %r10,%rdi + 40e57e: 74 03 je 40e583 <__qsort_r+0x243> + 40e580: 48 89 01 mov %rax,(%rcx) + 40e583: 4c 89 ce mov %r9,%rsi + 40e586: 48 03 75 c0 add -0x40(%rbp),%rsi + 40e58a: 48 8b 45 88 mov -0x78(%rbp),%rax + 40e58e: 48 c7 45 a0 08 00 00 movq $0x8,-0x60(%rbp) + 40e595: 00 + 40e596: 48 c7 45 a8 03 00 00 movq $0x3,-0x58(%rbp) + 40e59d: 00 + 40e59e: 48 83 f8 01 cmp $0x1,%rax + 40e5a2: 0f 86 e3 01 00 00 jbe 40e78b <__qsort_r+0x44b> + 40e5a8: 48 8d 7d a0 lea -0x60(%rbp),%rdi + 40e5ac: 48 89 c2 mov %rax,%rdx + 40e5af: e8 3c f9 ff ff callq 40def0 + 40e5b4: 48 c7 45 90 00 00 00 movq $0x0,-0x70(%rbp) + 40e5bb: 00 + 40e5bc: 48 8b 45 90 mov -0x70(%rbp),%rax + 40e5c0: 4c 89 75 98 mov %r14,-0x68(%rbp) + 40e5c4: 0f 1f 40 00 nopl 0x0(%rax) + 40e5c8: 4d 8b 3c c4 mov (%r12,%rax,8),%r15 + 40e5cc: 4c 8b 6d 98 mov -0x68(%rbp),%r13 + 40e5d0: 4d 39 ef cmp %r13,%r15 + 40e5d3: 74 5d je 40e632 <__qsort_r+0x2f2> + 40e5d5: 48 8b 7d 80 mov -0x80(%rbp),%rdi + 40e5d9: 4c 89 ee mov %r13,%rsi + 40e5dc: 48 89 da mov %rbx,%rdx + 40e5df: e8 3c da 01 00 callq 42c020 + 40e5e4: 4c 89 ef mov %r13,%rdi + 40e5e7: 48 8b 75 90 mov -0x70(%rbp),%rsi + 40e5eb: eb 06 jmp 40e5f3 <__qsort_r+0x2b3> + 40e5ed: 0f 1f 00 nopl (%rax) + 40e5f0: 49 89 c7 mov %rax,%r15 + 40e5f3: 4c 89 f8 mov %r15,%rax + 40e5f6: 31 d2 xor %edx,%edx + 40e5f8: 49 89 3c f4 mov %rdi,(%r12,%rsi,8) + 40e5fc: 4c 29 f0 sub %r14,%rax + 40e5ff: 4c 89 fe mov %r15,%rsi + 40e602: 48 f7 f3 div %rbx + 40e605: 48 89 da mov %rbx,%rdx + 40e608: 49 89 c5 mov %rax,%r13 + 40e60b: e8 10 da 01 00 callq 42c020 + 40e610: 4b 8d 14 ec lea (%r12,%r13,8),%rdx + 40e614: 4c 89 ee mov %r13,%rsi + 40e617: 4c 89 ff mov %r15,%rdi + 40e61a: 48 8b 02 mov (%rdx),%rax + 40e61d: 48 3b 45 98 cmp -0x68(%rbp),%rax + 40e621: 75 cd jne 40e5f0 <__qsort_r+0x2b0> + 40e623: 48 8b 75 80 mov -0x80(%rbp),%rsi + 40e627: 4c 89 3a mov %r15,(%rdx) + 40e62a: 48 89 da mov %rbx,%rdx + 40e62d: e8 ee d9 01 00 callq 42c020 + 40e632: 48 83 45 90 01 addq $0x1,-0x70(%rbp) + 40e637: 48 01 5d 98 add %rbx,-0x68(%rbp) + 40e63b: 48 8b 45 90 mov -0x70(%rbp),%rax + 40e63f: 48 39 45 88 cmp %rax,-0x78(%rbp) + 40e643: 75 83 jne 40e5c8 <__qsort_r+0x288> + 40e645: 48 8b bd 78 ff ff ff mov -0x88(%rbp),%rdi + 40e64c: e8 5f f7 00 00 callq 41ddb0 <__cfree> + 40e651: 48 8d 65 d8 lea -0x28(%rbp),%rsp + 40e655: 5b pop %rbx + 40e656: 41 5c pop %r12 + 40e658: 41 5d pop %r13 + 40e65a: 41 5e pop %r14 + 40e65c: 41 5f pop %r15 + 40e65e: 5d pop %rbp + 40e65f: c3 retq + 40e660: 49 c1 e5 04 shl $0x4,%r13 + 40e664: 49 01 d5 add %rdx,%r13 + 40e667: 49 81 fd ff 03 00 00 cmp $0x3ff,%r13 + 40e66e: 0f 87 08 fd ff ff ja 40e37c <__qsort_r+0x3c> + 40e674: 49 83 c5 1e add $0x1e,%r13 + 40e678: 48 c7 85 78 ff ff ff movq $0x0,-0x88(%rbp) + 40e67f: 00 00 00 00 + 40e683: 49 83 e5 f0 and $0xfffffffffffffff0,%r13 + 40e687: 4c 29 ec sub %r13,%rsp + 40e68a: 48 8d 74 24 0f lea 0xf(%rsp),%rsi + 40e68f: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi + 40e693: 48 89 75 c0 mov %rsi,-0x40(%rbp) + 40e697: e9 43 fd ff ff jmpq 40e3df <__qsort_r+0x9f> + 40e69c: 0f 1f 40 00 nopl 0x0(%rax) + 40e6a0: 48 8b 75 88 mov -0x78(%rbp),%rsi + 40e6a4: 4c 89 f9 mov %r15,%rcx + 40e6a7: 48 89 da mov %rbx,%rdx + 40e6aa: 4c 89 f7 mov %r14,%rdi + 40e6ad: e8 ce 10 04 00 callq 44f780 <_quicksort> + 40e6b2: 48 8d 65 d8 lea -0x28(%rbp),%rsp + 40e6b6: 5b pop %rbx + 40e6b7: 41 5c pop %r12 + 40e6b9: 41 5d pop %r13 + 40e6bb: 41 5e pop %r14 + 40e6bd: 41 5f pop %r15 + 40e6bf: 5d pop %rbp + 40e6c0: c3 retq + 40e6c1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 40e6c8: 48 89 d8 mov %rbx,%rax + 40e6cb: 4c 09 f0 or %r14,%rax + 40e6ce: a8 03 test $0x3,%al + 40e6d0: 75 20 jne 40e6f2 <__qsort_r+0x3b2> + 40e6d2: 48 83 fb 04 cmp $0x4,%rbx + 40e6d6: 0f 84 de 00 00 00 je 40e7ba <__qsort_r+0x47a> + 40e6dc: 48 83 fb 08 cmp $0x8,%rbx + 40e6e0: 0f 84 b5 00 00 00 je 40e79b <__qsort_r+0x45b> + 40e6e6: a8 07 test $0x7,%al + 40e6e8: 75 08 jne 40e6f2 <__qsort_r+0x3b2> + 40e6ea: 48 c7 45 a8 02 00 00 movq $0x2,-0x58(%rbp) + 40e6f1: 00 + 40e6f2: 48 8b 45 88 mov -0x78(%rbp),%rax + 40e6f6: 48 83 f8 01 cmp $0x1,%rax + 40e6fa: 0f 86 45 ff ff ff jbe 40e645 <__qsort_r+0x305> + 40e700: 48 8d 7d a0 lea -0x60(%rbp),%rdi + 40e704: 48 89 c2 mov %rax,%rdx + 40e707: 4c 89 f6 mov %r14,%rsi + 40e70a: e8 e1 f7 ff ff callq 40def0 + 40e70f: 48 8b bd 78 ff ff ff mov -0x88(%rbp),%rdi + 40e716: e8 95 f6 00 00 callq 41ddb0 <__cfree> + 40e71b: e9 31 ff ff ff jmpq 40e651 <__qsort_r+0x311> + 40e720: bf 55 00 00 00 mov $0x55,%edi + 40e725: 4c 89 45 98 mov %r8,-0x68(%rbp) + 40e729: e8 e2 01 03 00 callq 43e910 <__sysconf> + 40e72e: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 40e732: 48 ba ff ff ff ff ff movabs $0x1fffffffffffffff,%rdx + 40e739: ff ff 1f + 40e73c: 4c 8b 45 98 mov -0x68(%rbp),%r8 + 40e740: 74 0f je 40e751 <__qsort_r+0x411> + 40e742: 48 8d 50 03 lea 0x3(%rax),%rdx + 40e746: 48 85 c0 test %rax,%rax + 40e749: 48 0f 49 d0 cmovns %rax,%rdx + 40e74d: 48 c1 fa 02 sar $0x2,%rdx + 40e751: 4c 89 45 98 mov %r8,-0x68(%rbp) + 40e755: 48 89 15 ec d9 2b 00 mov %rdx,0x2bd9ec(%rip) # 6cc148 + 40e75c: bf 1e 00 00 00 mov $0x1e,%edi + 40e761: e8 aa 01 03 00 callq 43e910 <__sysconf> + 40e766: 4c 8b 45 98 mov -0x68(%rbp),%r8 + 40e76a: 89 c2 mov %eax,%edx + 40e76c: 89 05 de d9 2b 00 mov %eax,0x2bd9de(%rip) # 6cc150 + 40e772: e9 13 fc ff ff jmpq 40e38a <__qsort_r+0x4a> + 40e777: 48 85 d2 test %rdx,%rdx + 40e77a: 0f 85 d1 fc ff ff jne 40e451 <__qsort_r+0x111> + 40e780: 4c 89 e1 mov %r12,%rcx + 40e783: 4c 89 f0 mov %r14,%rax + 40e786: e9 86 fd ff ff jmpq 40e511 <__qsort_r+0x1d1> + 40e78b: 48 83 7d 88 00 cmpq $0x0,-0x78(%rbp) + 40e790: 0f 85 1e fe ff ff jne 40e5b4 <__qsort_r+0x274> + 40e796: e9 aa fe ff ff jmpq 40e645 <__qsort_r+0x305> + 40e79b: 41 f6 c6 07 test $0x7,%r14b + 40e79f: 0f 85 41 ff ff ff jne 40e6e6 <__qsort_r+0x3a6> + 40e7a5: 48 c7 45 a8 01 00 00 movq $0x1,-0x58(%rbp) + 40e7ac: 00 + 40e7ad: e9 40 ff ff ff jmpq 40e6f2 <__qsort_r+0x3b2> + 40e7b2: 4c 89 e6 mov %r12,%rsi + 40e7b5: e9 d0 fd ff ff jmpq 40e58a <__qsort_r+0x24a> + 40e7ba: 48 c7 45 a8 00 00 00 movq $0x0,-0x58(%rbp) + 40e7c1: 00 + 40e7c2: e9 2b ff ff ff jmpq 40e6f2 <__qsort_r+0x3b2> + 40e7c7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 40e7ce: 00 00 + +000000000040e7d0 : + 40e7d0: 45 31 c0 xor %r8d,%r8d + 40e7d3: e9 68 fb ff ff jmpq 40e340 <__qsort_r> + 40e7d8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 40e7df: 00 + +000000000040e7e0 : + 40e7e0: 41 57 push %r15 + 40e7e2: 41 56 push %r14 + 40e7e4: 41 55 push %r13 + 40e7e6: 41 54 push %r12 + 40e7e8: 55 push %rbp + 40e7e9: 53 push %rbx + 40e7ea: 48 89 fb mov %rdi,%rbx + 40e7ed: 48 83 ec 08 sub $0x8,%rsp + 40e7f1: e8 5a 4e 01 00 callq 423650 + 40e7f6: 48 8b 2d 43 de 2b 00 mov 0x2bde43(%rip),%rbp # 6cc640 <__environ> + 40e7fd: 48 85 ed test %rbp,%rbp + 40e800: 0f 84 b2 00 00 00 je 40e8b8 + 40e806: 49 89 c5 mov %rax,%r13 + 40e809: 0f b6 03 movzbl (%rbx),%eax + 40e80c: 84 c0 test %al,%al + 40e80e: 0f 84 a4 00 00 00 je 40e8b8 + 40e814: 80 7b 01 00 cmpb $0x0,0x1(%rbx) + 40e818: 75 46 jne 40e860 + 40e81a: 48 8b 5d 00 mov 0x0(%rbp),%rbx + 40e81e: 80 cc 3d or $0x3d,%ah + 40e821: 48 85 db test %rbx,%rbx + 40e824: 75 17 jne 40e83d + 40e826: eb 1e jmp 40e846 + 40e828: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 40e82f: 00 + 40e830: 48 83 c5 08 add $0x8,%rbp + 40e834: 48 8b 5d 00 mov 0x0(%rbp),%rbx + 40e838: 48 85 db test %rbx,%rbx + 40e83b: 74 09 je 40e846 + 40e83d: 66 3b 03 cmp (%rbx),%ax + 40e840: 75 ee jne 40e830 + 40e842: 48 83 c3 02 add $0x2,%rbx + 40e846: 48 83 c4 08 add $0x8,%rsp + 40e84a: 48 89 d8 mov %rbx,%rax + 40e84d: 5b pop %rbx + 40e84e: 5d pop %rbp + 40e84f: 41 5c pop %r12 + 40e851: 41 5d pop %r13 + 40e853: 41 5e pop %r14 + 40e855: 41 5f pop %r15 + 40e857: c3 retq + 40e858: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 40e85f: 00 + 40e860: 44 0f b7 23 movzwl (%rbx),%r12d + 40e864: 4c 8d 7b 02 lea 0x2(%rbx),%r15 + 40e868: 48 8b 5d 00 mov 0x0(%rbp),%rbx + 40e86c: 4d 8d 75 fe lea -0x2(%r13),%r14 + 40e870: 48 85 db test %rbx,%rbx + 40e873: 75 18 jne 40e88d + 40e875: eb cf jmp 40e846 + 40e877: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 40e87e: 00 00 + 40e880: 48 83 c5 08 add $0x8,%rbp + 40e884: 48 8b 5d 00 mov 0x0(%rbp),%rbx + 40e888: 48 85 db test %rbx,%rbx + 40e88b: 74 b9 je 40e846 + 40e88d: 66 44 3b 23 cmp (%rbx),%r12w + 40e891: 75 ed jne 40e880 + 40e893: 48 8d 7b 02 lea 0x2(%rbx),%rdi + 40e897: 4c 89 f2 mov %r14,%rdx + 40e89a: 4c 89 fe mov %r15,%rsi + 40e89d: e8 4e 4f 01 00 callq 4237f0 + 40e8a2: 85 c0 test %eax,%eax + 40e8a4: 75 da jne 40e880 + 40e8a6: 42 80 3c 2b 3d cmpb $0x3d,(%rbx,%r13,1) + 40e8ab: 75 d3 jne 40e880 + 40e8ad: 4a 8d 5c 2b 01 lea 0x1(%rbx,%r13,1),%rbx + 40e8b2: eb 92 jmp 40e846 + 40e8b4: 0f 1f 40 00 nopl 0x0(%rax) + 40e8b8: 31 db xor %ebx,%ebx + 40e8ba: eb 8a jmp 40e846 + 40e8bc: 0f 1f 40 00 nopl 0x0(%rax) + +000000000040e8c0 <__run_exit_handlers>: + 40e8c0: 41 55 push %r13 + 40e8c2: 41 54 push %r12 + 40e8c4: b8 00 00 00 00 mov $0x0,%eax + 40e8c9: 55 push %rbp + 40e8ca: 53 push %rbx + 40e8cb: 48 89 f5 mov %rsi,%rbp + 40e8ce: 89 fb mov %edi,%ebx + 40e8d0: 41 89 d4 mov %edx,%r12d + 40e8d3: 48 83 ec 08 sub $0x8,%rsp + 40e8d7: 48 85 c0 test %rax,%rax + 40e8da: 74 05 je 40e8e1 <__run_exit_handlers+0x21> + 40e8dc: e8 1f 17 bf ff callq 0 <_nl_current_LC_CTYPE> + 40e8e1: 4c 8b 6d 00 mov 0x0(%rbp),%r13 + 40e8e5: 4d 85 ed test %r13,%r13 + 40e8e8: 74 56 je 40e940 <__run_exit_handlers+0x80> + 40e8ea: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 40e8f0: 49 8b 45 08 mov 0x8(%r13),%rax + 40e8f4: 48 89 c2 mov %rax,%rdx + 40e8f7: 48 c1 e2 05 shl $0x5,%rdx + 40e8fb: 48 85 c0 test %rax,%rax + 40e8fe: 49 8d 4c 15 f0 lea -0x10(%r13,%rdx,1),%rcx + 40e903: 74 2a je 40e92f <__run_exit_handlers+0x6f> + 40e905: 48 83 e8 01 sub $0x1,%rax + 40e909: 49 89 45 08 mov %rax,0x8(%r13) + 40e90d: 48 8b 11 mov (%rcx),%rdx + 40e910: 48 83 fa 03 cmp $0x3,%rdx + 40e914: 0f 84 a6 00 00 00 je 40e9c0 <__run_exit_handlers+0x100> + 40e91a: 48 83 fa 04 cmp $0x4,%rdx + 40e91e: 74 78 je 40e998 <__run_exit_handlers+0xd8> + 40e920: 48 83 fa 02 cmp $0x2,%rdx + 40e924: 74 4a je 40e970 <__run_exit_handlers+0xb0> + 40e926: 48 83 e9 20 sub $0x20,%rcx + 40e92a: 48 85 c0 test %rax,%rax + 40e92d: 75 d6 jne 40e905 <__run_exit_handlers+0x45> + 40e92f: 49 8b 45 00 mov 0x0(%r13),%rax + 40e933: 48 85 c0 test %rax,%rax + 40e936: 48 89 45 00 mov %rax,0x0(%rbp) + 40e93a: 0f 85 9d 00 00 00 jne 40e9dd <__run_exit_handlers+0x11d> + 40e940: 45 84 e4 test %r12b,%r12b + 40e943: 74 20 je 40e965 <__run_exit_handlers+0xa5> + 40e945: b8 58 e1 4b 00 mov $0x4be158,%eax + 40e94a: 48 3d 60 e1 4b 00 cmp $0x4be160,%rax + 40e950: 73 13 jae 40e965 <__run_exit_handlers+0xa5> + 40e952: 48 89 c5 mov %rax,%rbp + 40e955: ff 55 00 callq *0x0(%rbp) + 40e958: 48 83 c5 08 add $0x8,%rbp + 40e95c: 48 81 fd 60 e1 4b 00 cmp $0x4be160,%rbp + 40e963: 72 f0 jb 40e955 <__run_exit_handlers+0x95> + 40e965: 89 df mov %ebx,%edi + 40e967: e8 64 fe 02 00 callq 43e7d0 <_exit> + 40e96c: 0f 1f 40 00 nopl 0x0(%rax) + 40e970: 48 c1 e0 05 shl $0x5,%rax + 40e974: 89 df mov %ebx,%edi + 40e976: 4c 01 e8 add %r13,%rax + 40e979: 48 8b 50 18 mov 0x18(%rax),%rdx + 40e97d: 48 8b 70 20 mov 0x20(%rax),%rsi + 40e981: 48 c1 ca 11 ror $0x11,%rdx + 40e985: 64 48 33 14 25 30 00 xor %fs:0x30,%rdx + 40e98c: 00 00 + 40e98e: ff d2 callq *%rdx + 40e990: e9 5b ff ff ff jmpq 40e8f0 <__run_exit_handlers+0x30> + 40e995: 0f 1f 00 nopl (%rax) + 40e998: 48 c1 e0 05 shl $0x5,%rax + 40e99c: 89 de mov %ebx,%esi + 40e99e: 4c 01 e8 add %r13,%rax + 40e9a1: 48 8b 50 18 mov 0x18(%rax),%rdx + 40e9a5: 48 8b 78 20 mov 0x20(%rax),%rdi + 40e9a9: 48 c1 ca 11 ror $0x11,%rdx + 40e9ad: 64 48 33 14 25 30 00 xor %fs:0x30,%rdx + 40e9b4: 00 00 + 40e9b6: ff d2 callq *%rdx + 40e9b8: e9 33 ff ff ff jmpq 40e8f0 <__run_exit_handlers+0x30> + 40e9bd: 0f 1f 00 nopl (%rax) + 40e9c0: 48 c1 e0 05 shl $0x5,%rax + 40e9c4: 49 8b 44 05 18 mov 0x18(%r13,%rax,1),%rax + 40e9c9: 48 c1 c8 11 ror $0x11,%rax + 40e9cd: 64 48 33 04 25 30 00 xor %fs:0x30,%rax + 40e9d4: 00 00 + 40e9d6: ff d0 callq *%rax + 40e9d8: e9 13 ff ff ff jmpq 40e8f0 <__run_exit_handlers+0x30> + 40e9dd: 4c 89 ef mov %r13,%rdi + 40e9e0: e8 cb f3 00 00 callq 41ddb0 <__cfree> + 40e9e5: e9 f7 fe ff ff jmpq 40e8e1 <__run_exit_handlers+0x21> + 40e9ea: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + +000000000040e9f0 : + 40e9f0: 48 83 ec 08 sub $0x8,%rsp + 40e9f4: ba 01 00 00 00 mov $0x1,%edx + 40e9f9: be a0 a0 6c 00 mov $0x6ca0a0,%esi + 40e9fe: e8 bd fe ff ff callq 40e8c0 <__run_exit_handlers> + 40ea03: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 40ea0a: 00 00 00 + 40ea0d: 0f 1f 00 nopl (%rax) + +000000000040ea10 <__new_exitfn>: + 40ea10: 55 push %rbp + 40ea11: 53 push %rbx + 40ea12: be 01 00 00 00 mov $0x1,%esi + 40ea17: 48 89 fb mov %rdi,%rbx + 40ea1a: 31 c0 xor %eax,%eax + 40ea1c: 48 83 ec 08 sub $0x8,%rsp + 40ea20: 83 3d 95 e7 2b 00 00 cmpl $0x0,0x2be795(%rip) # 6cd1bc <__libc_multiple_threads> + 40ea27: 74 0c je 40ea35 <__new_exitfn+0x25> + 40ea29: f0 0f b1 35 3f db 2b lock cmpxchg %esi,0x2bdb3f(%rip) # 6cc570 + 40ea30: 00 + 40ea31: 75 0b jne 40ea3e <__new_exitfn+0x2e> + 40ea33: eb 23 jmp 40ea58 <__new_exitfn+0x48> + 40ea35: 0f b1 35 34 db 2b 00 cmpxchg %esi,0x2bdb34(%rip) # 6cc570 + 40ea3c: 74 1a je 40ea58 <__new_exitfn+0x48> + 40ea3e: 48 8d 3d 2b db 2b 00 lea 0x2bdb2b(%rip),%rdi # 6cc570 + 40ea45: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 40ea4c: e8 7f 3b 03 00 callq 4425d0 <__lll_lock_wait_private> + 40ea51: 48 81 c4 80 00 00 00 add $0x80,%rsp + 40ea58: 48 8b 2b mov (%rbx),%rbp + 40ea5b: 31 ff xor %edi,%edi + 40ea5d: 48 85 ed test %rbp,%rbp + 40ea60: 48 89 e8 mov %rbp,%rax + 40ea63: 0f 84 10 01 00 00 je 40eb79 <__new_exitfn+0x169> + 40ea69: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 40ea70: 48 8b 48 08 mov 0x8(%rax),%rcx + 40ea74: 48 85 c9 test %rcx,%rcx + 40ea77: 74 3e je 40eab7 <__new_exitfn+0xa7> + 40ea79: 48 8d 51 ff lea -0x1(%rcx),%rdx + 40ea7d: 48 89 d6 mov %rdx,%rsi + 40ea80: 48 c1 e6 05 shl $0x5,%rsi + 40ea84: 48 83 7c 30 10 00 cmpq $0x0,0x10(%rax,%rsi,1) + 40ea8a: 75 47 jne 40ead3 <__new_exitfn+0xc3> + 40ea8c: 48 c1 e1 05 shl $0x5,%rcx + 40ea90: 48 8d 4c 08 d0 lea -0x30(%rax,%rcx,1),%rcx + 40ea95: eb 1b jmp 40eab2 <__new_exitfn+0xa2> + 40ea97: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 40ea9e: 00 00 + 40eaa0: 48 83 e9 20 sub $0x20,%rcx + 40eaa4: 48 8d 72 ff lea -0x1(%rdx),%rsi + 40eaa8: 48 83 79 20 00 cmpq $0x0,0x20(%rcx) + 40eaad: 75 31 jne 40eae0 <__new_exitfn+0xd0> + 40eaaf: 48 89 f2 mov %rsi,%rdx + 40eab2: 48 85 d2 test %rdx,%rdx + 40eab5: 75 e9 jne 40eaa0 <__new_exitfn+0x90> + 40eab7: 48 8b 10 mov (%rax),%rdx + 40eaba: 48 c7 40 08 00 00 00 movq $0x0,0x8(%rax) + 40eac1: 00 + 40eac2: 48 89 c7 mov %rax,%rdi + 40eac5: 48 85 d2 test %rdx,%rdx + 40eac8: 0f 84 9d 00 00 00 je 40eb6b <__new_exitfn+0x15b> + 40eace: 48 89 d0 mov %rdx,%rax + 40ead1: eb 9d jmp 40ea70 <__new_exitfn+0x60> + 40ead3: 48 89 ca mov %rcx,%rdx + 40ead6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 40eadd: 00 00 00 + 40eae0: 48 83 fa 20 cmp $0x20,%rdx + 40eae4: 74 63 je 40eb49 <__new_exitfn+0x139> + 40eae6: 48 89 d1 mov %rdx,%rcx + 40eae9: 48 83 c2 01 add $0x1,%rdx + 40eaed: 48 c1 e1 05 shl $0x5,%rcx + 40eaf1: 48 89 50 08 mov %rdx,0x8(%rax) + 40eaf5: 48 8d 74 08 10 lea 0x10(%rax,%rcx,1),%rsi + 40eafa: 48 c7 06 01 00 00 00 movq $0x1,(%rsi) + 40eb01: 48 83 05 a7 e6 2b 00 addq $0x1,0x2be6a7(%rip) # 6cd1b0 <__new_exitfn_called> + 40eb08: 01 + 40eb09: 83 3d ac e6 2b 00 00 cmpl $0x0,0x2be6ac(%rip) # 6cd1bc <__libc_multiple_threads> + 40eb10: 74 0b je 40eb1d <__new_exitfn+0x10d> + 40eb12: f0 ff 0d 57 da 2b 00 lock decl 0x2bda57(%rip) # 6cc570 + 40eb19: 75 0a jne 40eb25 <__new_exitfn+0x115> + 40eb1b: eb 22 jmp 40eb3f <__new_exitfn+0x12f> + 40eb1d: ff 0d 4d da 2b 00 decl 0x2bda4d(%rip) # 6cc570 + 40eb23: 74 1a je 40eb3f <__new_exitfn+0x12f> + 40eb25: 48 8d 3d 44 da 2b 00 lea 0x2bda44(%rip),%rdi # 6cc570 + 40eb2c: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 40eb33: e8 c8 3a 03 00 callq 442600 <__lll_unlock_wake_private> + 40eb38: 48 81 c4 80 00 00 00 add $0x80,%rsp + 40eb3f: 48 83 c4 08 add $0x8,%rsp + 40eb43: 48 89 f0 mov %rsi,%rax + 40eb46: 5b pop %rbx + 40eb47: 5d pop %rbp + 40eb48: c3 retq + 40eb49: 48 85 ff test %rdi,%rdi + 40eb4c: 48 89 f8 mov %rdi,%rax + 40eb4f: 75 1a jne 40eb6b <__new_exitfn+0x15b> + 40eb51: be 10 04 00 00 mov $0x410,%esi + 40eb56: bf 01 00 00 00 mov $0x1,%edi + 40eb5b: e8 60 fa 00 00 callq 41e5c0 <__calloc> + 40eb60: 48 85 c0 test %rax,%rax + 40eb63: 74 2d je 40eb92 <__new_exitfn+0x182> + 40eb65: 48 89 28 mov %rbp,(%rax) + 40eb68: 48 89 03 mov %rax,(%rbx) + 40eb6b: 48 8d 70 10 lea 0x10(%rax),%rsi + 40eb6f: 48 c7 40 08 01 00 00 movq $0x1,0x8(%rax) + 40eb76: 00 + 40eb77: eb 81 jmp 40eafa <__new_exitfn+0xea> + 40eb79: b9 18 19 4a 00 mov $0x4a1918,%ecx + 40eb7e: ba 64 00 00 00 mov $0x64,%edx + 40eb83: be 00 19 4a 00 mov $0x4a1900,%esi + 40eb88: bf 0d 19 4a 00 mov $0x4a190d,%edi + 40eb8d: e8 ae 2b ff ff callq 401740 <__assert_fail> + 40eb92: 31 f6 xor %esi,%esi + 40eb94: e9 70 ff ff ff jmpq 40eb09 <__new_exitfn+0xf9> + 40eb99: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + +000000000040eba0 <__internal_atexit>: + 40eba0: 41 54 push %r12 + 40eba2: 55 push %rbp + 40eba3: 49 89 f4 mov %rsi,%r12 + 40eba6: 53 push %rbx + 40eba7: 48 89 fb mov %rdi,%rbx + 40ebaa: 48 89 cf mov %rcx,%rdi + 40ebad: 48 89 d5 mov %rdx,%rbp + 40ebb0: e8 5b fe ff ff callq 40ea10 <__new_exitfn> + 40ebb5: 48 85 c0 test %rax,%rax + 40ebb8: 74 2a je 40ebe4 <__internal_atexit+0x44> + 40ebba: 48 89 df mov %rbx,%rdi + 40ebbd: 4c 89 60 10 mov %r12,0x10(%rax) + 40ebc1: 48 89 68 18 mov %rbp,0x18(%rax) + 40ebc5: 64 48 33 3c 25 30 00 xor %fs:0x30,%rdi + 40ebcc: 00 00 + 40ebce: 48 c1 c7 11 rol $0x11,%rdi + 40ebd2: 48 89 78 08 mov %rdi,0x8(%rax) + 40ebd6: 48 c7 00 04 00 00 00 movq $0x4,(%rax) + 40ebdd: 31 c0 xor %eax,%eax + 40ebdf: 5b pop %rbx + 40ebe0: 5d pop %rbp + 40ebe1: 41 5c pop %r12 + 40ebe3: c3 retq + 40ebe4: b8 ff ff ff ff mov $0xffffffff,%eax + 40ebe9: eb f4 jmp 40ebdf <__internal_atexit+0x3f> + 40ebeb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + +000000000040ebf0 <__cxa_atexit>: + 40ebf0: 41 54 push %r12 + 40ebf2: 55 push %rbp + 40ebf3: 49 89 f4 mov %rsi,%r12 + 40ebf6: 53 push %rbx + 40ebf7: 48 89 fb mov %rdi,%rbx + 40ebfa: bf a0 a0 6c 00 mov $0x6ca0a0,%edi + 40ebff: 48 89 d5 mov %rdx,%rbp + 40ec02: e8 09 fe ff ff callq 40ea10 <__new_exitfn> + 40ec07: 48 85 c0 test %rax,%rax + 40ec0a: 74 2a je 40ec36 <__cxa_atexit+0x46> + 40ec0c: 48 89 df mov %rbx,%rdi + 40ec0f: 4c 89 60 10 mov %r12,0x10(%rax) + 40ec13: 48 89 68 18 mov %rbp,0x18(%rax) + 40ec17: 64 48 33 3c 25 30 00 xor %fs:0x30,%rdi + 40ec1e: 00 00 + 40ec20: 48 c1 c7 11 rol $0x11,%rdi + 40ec24: 48 89 78 08 mov %rdi,0x8(%rax) + 40ec28: 48 c7 00 04 00 00 00 movq $0x4,(%rax) + 40ec2f: 31 c0 xor %eax,%eax + 40ec31: 5b pop %rbx + 40ec32: 5d pop %rbp + 40ec33: 41 5c pop %r12 + 40ec35: c3 retq + 40ec36: b8 ff ff ff ff mov $0xffffffff,%eax + 40ec3b: eb f4 jmp 40ec31 <__cxa_atexit+0x41> + 40ec3d: 0f 1f 00 nopl (%rax) + +000000000040ec40 <__strtoul_internal>: + 40ec40: 48 c7 c0 b8 ff ff ff mov $0xffffffffffffffb8,%rax + 40ec47: 64 4c 8b 00 mov %fs:(%rax),%r8 + 40ec4b: e9 20 00 00 00 jmpq 40ec70 <____strtoul_l_internal> + +000000000040ec50 <__strtoul>: + 40ec50: 48 c7 c0 b8 ff ff ff mov $0xffffffffffffffb8,%rax + 40ec57: 31 c9 xor %ecx,%ecx + 40ec59: 64 4c 8b 00 mov %fs:(%rax),%r8 + 40ec5d: e9 0e 00 00 00 jmpq 40ec70 <____strtoul_l_internal> + 40ec62: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 40ec69: 00 00 00 + 40ec6c: 0f 1f 40 00 nopl 0x0(%rax) + +000000000040ec70 <____strtoul_l_internal>: + 40ec70: 41 57 push %r15 + 40ec72: 41 56 push %r14 + 40ec74: 49 89 f7 mov %rsi,%r15 + 40ec77: 41 55 push %r13 + 40ec79: 41 54 push %r12 + 40ec7b: 49 89 fe mov %rdi,%r14 + 40ec7e: 55 push %rbp + 40ec7f: 53 push %rbx + 40ec80: 48 83 ec 28 sub $0x28,%rsp + 40ec84: 85 c9 test %ecx,%ecx + 40ec86: 74 16 je 40ec9e <____strtoul_l_internal+0x2e> + 40ec88: 49 8b 70 08 mov 0x8(%r8),%rsi + 40ec8c: 48 8b 4e 50 mov 0x50(%rsi),%rcx + 40ec90: 0f b6 01 movzbl (%rcx),%eax + 40ec93: 83 e8 01 sub $0x1,%eax + 40ec96: 3c 7d cmp $0x7d,%al + 40ec98: 0f 86 f2 00 00 00 jbe 40ed90 <____strtoul_l_internal+0x120> + 40ec9e: 31 c9 xor %ecx,%ecx + 40eca0: 31 ed xor %ebp,%ebp + 40eca2: 83 fa 01 cmp $0x1,%edx + 40eca5: 0f 84 c5 00 00 00 je 40ed70 <____strtoul_l_internal+0x100> + 40ecab: 83 fa 24 cmp $0x24,%edx + 40ecae: 0f 87 bc 00 00 00 ja 40ed70 <____strtoul_l_internal+0x100> + 40ecb4: 49 0f be 06 movsbq (%r14),%rax + 40ecb8: 49 8b 70 68 mov 0x68(%r8),%rsi + 40ecbc: 4d 89 f4 mov %r14,%r12 + 40ecbf: f6 44 46 01 20 testb $0x20,0x1(%rsi,%rax,2) + 40ecc4: 48 89 c3 mov %rax,%rbx + 40ecc7: 74 1a je 40ece3 <____strtoul_l_internal+0x73> + 40ecc9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 40ecd0: 49 83 c4 01 add $0x1,%r12 + 40ecd4: 49 0f be 04 24 movsbq (%r12),%rax + 40ecd9: f6 44 46 01 20 testb $0x20,0x1(%rsi,%rax,2) + 40ecde: 48 89 c3 mov %rax,%rbx + 40ece1: 75 ed jne 40ecd0 <____strtoul_l_internal+0x60> + 40ece3: 84 db test %bl,%bl + 40ece5: 0f 84 bd 00 00 00 je 40eda8 <____strtoul_l_internal+0x138> + 40eceb: 80 fb 2d cmp $0x2d,%bl + 40ecee: 0f 84 10 03 00 00 je 40f004 <____strtoul_l_internal+0x394> + 40ecf4: 80 fb 2b cmp $0x2b,%bl + 40ecf7: c7 44 24 14 00 00 00 movl $0x0,0x14(%rsp) + 40ecfe: 00 + 40ecff: 0f 84 5a 03 00 00 je 40f05f <____strtoul_l_internal+0x3ef> + 40ed05: 80 fb 30 cmp $0x30,%bl + 40ed08: 0f 84 dd 00 00 00 je 40edeb <____strtoul_l_internal+0x17b> + 40ed0e: 85 d2 test %edx,%edx + 40ed10: 0f 85 e1 00 00 00 jne 40edf7 <____strtoul_l_internal+0x187> + 40ed16: 48 85 c9 test %rcx,%rcx + 40ed19: 48 89 0c 24 mov %rcx,(%rsp) + 40ed1d: 0f 84 73 03 00 00 je 40f096 <____strtoul_l_internal+0x426> + 40ed23: 48 89 ef mov %rbp,%rdi + 40ed26: e8 25 49 01 00 callq 423650 + 40ed2b: 48 85 c0 test %rax,%rax + 40ed2e: 49 89 c5 mov %rax,%r13 + 40ed31: 74 78 je 40edab <____strtoul_l_internal+0x13b> + 40ed33: 0f b6 7d 00 movzbl 0x0(%rbp),%edi + 40ed37: 48 8b 0c 24 mov (%rsp),%rcx + 40ed3b: 40 38 df cmp %bl,%dil + 40ed3e: 0f 85 0e 02 00 00 jne 40ef52 <____strtoul_l_internal+0x2e2> + 40ed44: 31 d2 xor %edx,%edx + 40ed46: eb 18 jmp 40ed60 <____strtoul_l_internal+0xf0> + 40ed48: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 40ed4f: 00 + 40ed50: 41 0f b6 34 14 movzbl (%r12,%rdx,1),%esi + 40ed55: 40 38 74 15 00 cmp %sil,0x0(%rbp,%rdx,1) + 40ed5a: 0f 85 f2 01 00 00 jne 40ef52 <____strtoul_l_internal+0x2e2> + 40ed60: 48 83 c2 01 add $0x1,%rdx + 40ed64: 48 39 d0 cmp %rdx,%rax + 40ed67: 75 e7 jne 40ed50 <____strtoul_l_internal+0xe0> + 40ed69: eb 40 jmp 40edab <____strtoul_l_internal+0x13b> + 40ed6b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 40ed70: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 40ed77: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) + 40ed7e: 31 c0 xor %eax,%eax + 40ed80: 48 83 c4 28 add $0x28,%rsp + 40ed84: 5b pop %rbx + 40ed85: 5d pop %rbp + 40ed86: 41 5c pop %r12 + 40ed88: 41 5d pop %r13 + 40ed8a: 41 5e pop %r14 + 40ed8c: 41 5f pop %r15 + 40ed8e: c3 retq + 40ed8f: 90 nop + 40ed90: 48 8b 6e 48 mov 0x48(%rsi),%rbp + 40ed94: 80 7d 00 00 cmpb $0x0,0x0(%rbp) + 40ed98: 0f 85 04 ff ff ff jne 40eca2 <____strtoul_l_internal+0x32> + 40ed9e: e9 fb fe ff ff jmpq 40ec9e <____strtoul_l_internal+0x2e> + 40eda3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 40eda8: 4d 89 f4 mov %r14,%r12 + 40edab: 4d 85 ff test %r15,%r15 + 40edae: 0f 84 ba 02 00 00 je 40f06e <____strtoul_l_internal+0x3fe> + 40edb4: 4c 89 e0 mov %r12,%rax + 40edb7: 4c 29 f0 sub %r14,%rax + 40edba: 48 83 f8 01 cmp $0x1,%rax + 40edbe: 7e 17 jle 40edd7 <____strtoul_l_internal+0x167> + 40edc0: 49 0f be 54 24 ff movsbq -0x1(%r12),%rdx + 40edc6: 48 8b 05 2b 39 0a 00 mov 0xa392b(%rip),%rax # 4b26f8 <_nl_C_locobj+0x78> + 40edcd: 83 3c 90 58 cmpl $0x58,(%rax,%rdx,4) + 40edd1: 0f 84 6e 02 00 00 je 40f045 <____strtoul_l_internal+0x3d5> + 40edd7: 4d 89 37 mov %r14,(%r15) + 40edda: 48 83 c4 28 add $0x28,%rsp + 40edde: 31 c0 xor %eax,%eax + 40ede0: 5b pop %rbx + 40ede1: 5d pop %rbp + 40ede2: 41 5c pop %r12 + 40ede4: 41 5d pop %r13 + 40ede6: 41 5e pop %r14 + 40ede8: 41 5f pop %r15 + 40edea: c3 retq + 40edeb: f7 c2 ef ff ff ff test $0xffffffef,%edx + 40edf1: 0f 84 24 02 00 00 je 40f01b <____strtoul_l_internal+0x3ab> + 40edf7: 83 fa 0a cmp $0xa,%edx + 40edfa: 0f 84 16 ff ff ff je 40ed16 <____strtoul_l_internal+0xa6> + 40ee00: 8d 4a fe lea -0x2(%rdx),%ecx + 40ee03: 45 31 ed xor %r13d,%r13d + 40ee06: 31 c0 xor %eax,%eax + 40ee08: 48 63 c9 movslq %ecx,%rcx + 40ee0b: 4c 39 e0 cmp %r12,%rax + 40ee0e: 48 8b 3c cd c0 27 4b mov 0x4b27c0(,%rcx,8),%rdi + 40ee15: 00 + 40ee16: 48 89 3c 24 mov %rdi,(%rsp) + 40ee1a: 0f b6 b9 80 27 4b 00 movzbl 0x4b2780(%rcx),%edi + 40ee21: 40 88 7c 24 13 mov %dil,0x13(%rsp) + 40ee26: 74 83 je 40edab <____strtoul_l_internal+0x13b> + 40ee28: 84 db test %bl,%bl + 40ee2a: 0f 84 7b ff ff ff je 40edab <____strtoul_l_internal+0x13b> + 40ee30: 4d 8d 45 ff lea -0x1(%r13),%r8 + 40ee34: 4c 8b 15 ad 38 0a 00 mov 0xa38ad(%rip),%r10 # 4b26e8 <_nl_C_locobj+0x68> + 40ee3b: 4c 8b 1d b6 38 0a 00 mov 0xa38b6(%rip),%r11 # 4b26f8 <_nl_C_locobj+0x78> + 40ee42: 48 63 ca movslq %edx,%rcx + 40ee45: 4c 89 e7 mov %r12,%rdi + 40ee48: 4c 89 64 24 18 mov %r12,0x18(%rsp) + 40ee4d: 4c 89 44 24 08 mov %r8,0x8(%rsp) + 40ee52: 4c 8b 04 24 mov (%rsp),%r8 + 40ee56: 45 31 c9 xor %r9d,%r9d + 40ee59: 31 f6 xor %esi,%esi + 40ee5b: 49 89 cc mov %rcx,%r12 + 40ee5e: 66 90 xchg %ax,%ax + 40ee60: 8d 4b d0 lea -0x30(%rbx),%ecx + 40ee63: 80 f9 09 cmp $0x9,%cl + 40ee66: 0f 86 aa 00 00 00 jbe 40ef16 <____strtoul_l_internal+0x2a6> + 40ee6c: 4d 85 ed test %r13,%r13 + 40ee6f: 0f 84 8f 00 00 00 je 40ef04 <____strtoul_l_internal+0x294> + 40ee75: 38 5d 00 cmp %bl,0x0(%rbp) + 40ee78: 0f 85 86 00 00 00 jne 40ef04 <____strtoul_l_internal+0x294> + 40ee7e: 31 c9 xor %ecx,%ecx + 40ee80: 88 1c 24 mov %bl,(%rsp) + 40ee83: eb 0d jmp 40ee92 <____strtoul_l_internal+0x222> + 40ee85: 0f 1f 00 nopl (%rax) + 40ee88: 0f b6 1c 0f movzbl (%rdi,%rcx,1),%ebx + 40ee8c: 38 5c 0d 00 cmp %bl,0x0(%rbp,%rcx,1) + 40ee90: 75 6e jne 40ef00 <____strtoul_l_internal+0x290> + 40ee92: 48 83 c1 01 add $0x1,%rcx + 40ee96: 49 39 cd cmp %rcx,%r13 + 40ee99: 75 ed jne 40ee88 <____strtoul_l_internal+0x218> + 40ee9b: 48 8b 5c 24 08 mov 0x8(%rsp),%rbx + 40eea0: 48 8d 0c 1f lea (%rdi,%rbx,1),%rcx + 40eea4: 0f 1f 40 00 nopl 0x0(%rax) + 40eea8: 48 8d 79 01 lea 0x1(%rcx),%rdi + 40eeac: 0f b6 59 01 movzbl 0x1(%rcx),%ebx + 40eeb0: 48 39 f8 cmp %rdi,%rax + 40eeb3: 74 04 je 40eeb9 <____strtoul_l_internal+0x249> + 40eeb5: 84 db test %bl,%bl + 40eeb7: 75 a7 jne 40ee60 <____strtoul_l_internal+0x1f0> + 40eeb9: 4c 8b 64 24 18 mov 0x18(%rsp),%r12 + 40eebe: 49 39 fc cmp %rdi,%r12 + 40eec1: 0f 84 e4 fe ff ff je 40edab <____strtoul_l_internal+0x13b> + 40eec7: 4d 85 ff test %r15,%r15 + 40eeca: 74 03 je 40eecf <____strtoul_l_internal+0x25f> + 40eecc: 49 89 3f mov %rdi,(%r15) + 40eecf: 45 85 c9 test %r9d,%r9d + 40eed2: 0f 84 17 01 00 00 je 40efef <____strtoul_l_internal+0x37f> + 40eed8: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 40eedf: 64 c7 00 22 00 00 00 movl $0x22,%fs:(%rax) + 40eee6: 48 83 c4 28 add $0x28,%rsp + 40eeea: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax + 40eef1: 5b pop %rbx + 40eef2: 5d pop %rbp + 40eef3: 41 5c pop %r12 + 40eef5: 41 5d pop %r13 + 40eef7: 41 5e pop %r14 + 40eef9: 41 5f pop %r15 + 40eefb: c3 retq + 40eefc: 0f 1f 40 00 nopl 0x0(%rax) + 40ef00: 0f b6 1c 24 movzbl (%rsp),%ebx + 40ef04: 0f b6 db movzbl %bl,%ebx + 40ef07: 41 f6 44 5a 01 04 testb $0x4,0x1(%r10,%rbx,2) + 40ef0d: 74 aa je 40eeb9 <____strtoul_l_internal+0x249> + 40ef0f: 41 8b 0c 9b mov (%r11,%rbx,4),%ecx + 40ef13: 83 e9 37 sub $0x37,%ecx + 40ef16: 0f b6 d9 movzbl %cl,%ebx + 40ef19: 39 d3 cmp %edx,%ebx + 40ef1b: 7d 9c jge 40eeb9 <____strtoul_l_internal+0x249> + 40ef1d: 49 39 f0 cmp %rsi,%r8 + 40ef20: 72 0e jb 40ef30 <____strtoul_l_internal+0x2c0> + 40ef22: 3a 4c 24 13 cmp 0x13(%rsp),%cl + 40ef26: 76 18 jbe 40ef40 <____strtoul_l_internal+0x2d0> + 40ef28: 49 39 f0 cmp %rsi,%r8 + 40ef2b: 75 13 jne 40ef40 <____strtoul_l_internal+0x2d0> + 40ef2d: 0f 1f 00 nopl (%rax) + 40ef30: 48 89 f9 mov %rdi,%rcx + 40ef33: 41 b9 01 00 00 00 mov $0x1,%r9d + 40ef39: e9 6a ff ff ff jmpq 40eea8 <____strtoul_l_internal+0x238> + 40ef3e: 66 90 xchg %ax,%ax + 40ef40: 49 0f af f4 imul %r12,%rsi + 40ef44: 0f b6 c9 movzbl %cl,%ecx + 40ef47: 48 01 ce add %rcx,%rsi + 40ef4a: 48 89 f9 mov %rdi,%rcx + 40ef4d: e9 56 ff ff ff jmpq 40eea8 <____strtoul_l_internal+0x238> + 40ef52: 84 db test %bl,%bl + 40ef54: 0f 84 34 01 00 00 je 40f08e <____strtoul_l_internal+0x41e> + 40ef5a: 4c 8b 05 87 37 0a 00 mov 0xa3787(%rip),%r8 # 4b26e8 <_nl_C_locobj+0x68> + 40ef61: 4c 8b 0d 90 37 0a 00 mov 0xa3790(%rip),%r9 # 4b26f8 <_nl_C_locobj+0x78> + 40ef68: 4c 89 e6 mov %r12,%rsi + 40ef6b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 40ef70: 8d 53 d0 lea -0x30(%rbx),%edx + 40ef73: 80 fa 09 cmp $0x9,%dl + 40ef76: 76 25 jbe 40ef9d <____strtoul_l_internal+0x32d> + 40ef78: 40 3a 3e cmp (%rsi),%dil + 40ef7b: 75 53 jne 40efd0 <____strtoul_l_internal+0x360> + 40ef7d: 31 d2 xor %edx,%edx + 40ef7f: eb 13 jmp 40ef94 <____strtoul_l_internal+0x324> + 40ef81: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 40ef88: 44 0f b6 1c 16 movzbl (%rsi,%rdx,1),%r11d + 40ef8d: 44 38 5c 15 00 cmp %r11b,0x0(%rbp,%rdx,1) + 40ef92: 75 3c jne 40efd0 <____strtoul_l_internal+0x360> + 40ef94: 48 83 c2 01 add $0x1,%rdx + 40ef98: 48 39 d0 cmp %rdx,%rax + 40ef9b: 75 eb jne 40ef88 <____strtoul_l_internal+0x318> + 40ef9d: 48 83 c6 01 add $0x1,%rsi + 40efa1: 0f b6 1e movzbl (%rsi),%ebx + 40efa4: 84 db test %bl,%bl + 40efa6: 75 c8 jne 40ef70 <____strtoul_l_internal+0x300> + 40efa8: 48 89 ea mov %rbp,%rdx + 40efab: 4c 89 e7 mov %r12,%rdi + 40efae: e8 0d 01 00 00 callq 40f0c0 <__correctly_grouped_prefixmb> + 40efb3: 41 0f b6 1c 24 movzbl (%r12),%ebx + 40efb8: b9 08 00 00 00 mov $0x8,%ecx + 40efbd: ba 0a 00 00 00 mov $0xa,%edx + 40efc2: e9 41 fe ff ff jmpq 40ee08 <____strtoul_l_internal+0x198> + 40efc7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 40efce: 00 00 + 40efd0: 0f b6 db movzbl %bl,%ebx + 40efd3: 41 f6 44 58 01 04 testb $0x4,0x1(%r8,%rbx,2) + 40efd9: 74 cd je 40efa8 <____strtoul_l_internal+0x338> + 40efdb: 41 83 3c 99 40 cmpl $0x40,(%r9,%rbx,4) + 40efe0: 7f c6 jg 40efa8 <____strtoul_l_internal+0x338> + 40efe2: 48 83 c6 01 add $0x1,%rsi + 40efe6: 0f b6 1e movzbl (%rsi),%ebx + 40efe9: 84 db test %bl,%bl + 40efeb: 75 83 jne 40ef70 <____strtoul_l_internal+0x300> + 40efed: eb b9 jmp 40efa8 <____strtoul_l_internal+0x338> + 40efef: 8b 54 24 14 mov 0x14(%rsp),%edx + 40eff3: 48 89 f0 mov %rsi,%rax + 40eff6: 48 f7 d8 neg %rax + 40eff9: 85 d2 test %edx,%edx + 40effb: 48 0f 44 c6 cmove %rsi,%rax + 40efff: e9 7c fd ff ff jmpq 40ed80 <____strtoul_l_internal+0x110> + 40f004: 41 0f b6 5c 24 01 movzbl 0x1(%r12),%ebx + 40f00a: c7 44 24 14 01 00 00 movl $0x1,0x14(%rsp) + 40f011: 00 + 40f012: 49 83 c4 01 add $0x1,%r12 + 40f016: e9 ea fc ff ff jmpq 40ed05 <____strtoul_l_internal+0x95> + 40f01b: 49 0f be 74 24 01 movsbq 0x1(%r12),%rsi + 40f021: 48 8b 05 d0 36 0a 00 mov 0xa36d0(%rip),%rax # 4b26f8 <_nl_C_locobj+0x78> + 40f028: 83 3c b0 58 cmpl $0x58,(%rax,%rsi,4) + 40f02c: 74 47 je 40f075 <____strtoul_l_internal+0x405> + 40f02e: 85 d2 test %edx,%edx + 40f030: 0f 85 c1 fd ff ff jne 40edf7 <____strtoul_l_internal+0x187> + 40f036: b9 06 00 00 00 mov $0x6,%ecx + 40f03b: ba 08 00 00 00 mov $0x8,%edx + 40f040: e9 be fd ff ff jmpq 40ee03 <____strtoul_l_internal+0x193> + 40f045: 41 80 7c 24 fe 30 cmpb $0x30,-0x2(%r12) + 40f04b: 0f 85 86 fd ff ff jne 40edd7 <____strtoul_l_internal+0x167> + 40f051: 49 83 ec 01 sub $0x1,%r12 + 40f055: 31 c0 xor %eax,%eax + 40f057: 4d 89 27 mov %r12,(%r15) + 40f05a: e9 21 fd ff ff jmpq 40ed80 <____strtoul_l_internal+0x110> + 40f05f: 41 0f b6 5c 24 01 movzbl 0x1(%r12),%ebx + 40f065: 49 83 c4 01 add $0x1,%r12 + 40f069: e9 97 fc ff ff jmpq 40ed05 <____strtoul_l_internal+0x95> + 40f06e: 31 c0 xor %eax,%eax + 40f070: e9 0b fd ff ff jmpq 40ed80 <____strtoul_l_internal+0x110> + 40f075: 41 0f b6 5c 24 02 movzbl 0x2(%r12),%ebx + 40f07b: b9 0e 00 00 00 mov $0xe,%ecx + 40f080: 49 83 c4 02 add $0x2,%r12 + 40f084: ba 10 00 00 00 mov $0x10,%edx + 40f089: e9 75 fd ff ff jmpq 40ee03 <____strtoul_l_internal+0x193> + 40f08e: 4c 89 e6 mov %r12,%rsi + 40f091: e9 12 ff ff ff jmpq 40efa8 <____strtoul_l_internal+0x338> + 40f096: b9 08 00 00 00 mov $0x8,%ecx + 40f09b: ba 0a 00 00 00 mov $0xa,%edx + 40f0a0: e9 5e fd ff ff jmpq 40ee03 <____strtoul_l_internal+0x193> + 40f0a5: 90 nop + 40f0a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 40f0ad: 00 00 00 + +000000000040f0b0 <__strtoul_l>: + 40f0b0: 49 89 c8 mov %rcx,%r8 + 40f0b3: 31 c9 xor %ecx,%ecx + 40f0b5: e9 b6 fb ff ff jmpq 40ec70 <____strtoul_l_internal> + 40f0ba: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + +000000000040f0c0 <__correctly_grouped_prefixmb>: + 40f0c0: 41 57 push %r15 + 40f0c2: 41 56 push %r14 + 40f0c4: 41 55 push %r13 + 40f0c6: 41 54 push %r12 + 40f0c8: 55 push %rbp + 40f0c9: 53 push %rbx + 40f0ca: 48 83 ec 18 sub $0x18,%rsp + 40f0ce: 48 85 c9 test %rcx,%rcx + 40f0d1: 48 89 4c 24 08 mov %rcx,0x8(%rsp) + 40f0d6: 0f 84 fd 00 00 00 je 40f1d9 <__correctly_grouped_prefixmb+0x119> + 40f0dc: 48 89 fd mov %rdi,%rbp + 40f0df: 48 89 d7 mov %rdx,%rdi + 40f0e2: 48 89 34 24 mov %rsi,(%rsp) + 40f0e6: 48 89 d3 mov %rdx,%rbx + 40f0e9: e8 62 45 01 00 callq 423650 + 40f0ee: 48 8b 34 24 mov (%rsp),%rsi + 40f0f2: 48 39 ee cmp %rbp,%rsi + 40f0f5: 0f 86 ad 00 00 00 jbe 40f1a8 <__correctly_grouped_prefixmb+0xe8> + 40f0fb: 4c 8d 78 ff lea -0x1(%rax),%r15 + 40f0ff: 48 8d 55 ff lea -0x1(%rbp),%rdx + 40f103: 4c 8d 4e ff lea -0x1(%rsi),%r9 + 40f107: 4c 39 cd cmp %r9,%rbp + 40f10a: 0f 87 c9 00 00 00 ja 40f1d9 <__correctly_grouped_prefixmb+0x119> + 40f110: 44 0f b6 13 movzbl (%rbx),%r10d + 40f114: 4e 8d 1c 3e lea (%rsi,%r15,1),%r11 + 40f118: eb 17 jmp 40f131 <__correctly_grouped_prefixmb+0x71> + 40f11a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 40f120: 49 83 e9 01 sub $0x1,%r9 + 40f124: 49 83 eb 01 sub $0x1,%r11 + 40f128: 49 39 d1 cmp %rdx,%r9 + 40f12b: 0f 84 a8 00 00 00 je 40f1d9 <__correctly_grouped_prefixmb+0x119> + 40f131: 45 38 53 ff cmp %r10b,-0x1(%r11) + 40f135: 75 e9 jne 40f120 <__correctly_grouped_prefixmb+0x60> + 40f137: 0f b6 43 01 movzbl 0x1(%rbx),%eax + 40f13b: 84 c0 test %al,%al + 40f13d: 74 2b je 40f16a <__correctly_grouped_prefixmb+0xaa> + 40f13f: 41 38 43 fe cmp %al,-0x2(%r11) + 40f143: 75 db jne 40f120 <__correctly_grouped_prefixmb+0x60> + 40f145: 48 8d 43 02 lea 0x2(%rbx),%rax + 40f149: 4c 89 d9 mov %r11,%rcx + 40f14c: eb 14 jmp 40f162 <__correctly_grouped_prefixmb+0xa2> + 40f14e: 66 90 xchg %ax,%ax + 40f150: 44 0f b6 41 fd movzbl -0x3(%rcx),%r8d + 40f155: 48 83 c0 01 add $0x1,%rax + 40f159: 48 83 e9 01 sub $0x1,%rcx + 40f15d: 44 38 c7 cmp %r8b,%dil + 40f160: 75 be jne 40f120 <__correctly_grouped_prefixmb+0x60> + 40f162: 0f b6 38 movzbl (%rax),%edi + 40f165: 40 84 ff test %dil,%dil + 40f168: 75 e6 jne 40f150 <__correctly_grouped_prefixmb+0x90> + 40f16a: 4c 39 cd cmp %r9,%rbp + 40f16d: 77 6a ja 40f1d9 <__correctly_grouped_prefixmb+0x119> + 40f16f: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 40f174: 48 89 f1 mov %rsi,%rcx + 40f177: 4c 29 c9 sub %r9,%rcx + 40f17a: 48 0f be 00 movsbq (%rax),%rax + 40f17e: 49 89 c5 mov %rax,%r13 + 40f181: 83 c0 01 add $0x1,%eax + 40f184: 48 98 cltq + 40f186: 48 39 c1 cmp %rax,%rcx + 40f189: 74 60 je 40f1eb <__correctly_grouped_prefixmb+0x12b> + 40f18b: 4c 89 0c 24 mov %r9,(%rsp) + 40f18f: 7e 09 jle 40f19a <__correctly_grouped_prefixmb+0xda> + 40f191: 4b 8d 44 29 01 lea 0x1(%r9,%r13,1),%rax + 40f196: 48 89 04 24 mov %rax,(%rsp) + 40f19a: 48 3b 2c 24 cmp (%rsp),%rbp + 40f19e: 48 8b 34 24 mov (%rsp),%rsi + 40f1a2: 0f 82 5b ff ff ff jb 40f103 <__correctly_grouped_prefixmb+0x43> + 40f1a8: 48 39 f5 cmp %rsi,%rbp + 40f1ab: 48 89 f0 mov %rsi,%rax + 40f1ae: 48 0f 43 c5 cmovae %rbp,%rax + 40f1b2: 48 83 c4 18 add $0x18,%rsp + 40f1b6: 5b pop %rbx + 40f1b7: 5d pop %rbp + 40f1b8: 41 5c pop %r12 + 40f1ba: 41 5d pop %r13 + 40f1bc: 41 5e pop %r14 + 40f1be: 41 5f pop %r15 + 40f1c0: c3 retq + 40f1c1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 40f1c8: 49 83 e9 01 sub $0x1,%r9 + 40f1cc: 49 83 eb 01 sub $0x1,%r11 + 40f1d0: 4c 39 ca cmp %r9,%rdx + 40f1d3: 0f 85 d7 00 00 00 jne 40f2b0 <__correctly_grouped_prefixmb+0x1f0> + 40f1d9: 48 83 c4 18 add $0x18,%rsp + 40f1dd: 48 89 f0 mov %rsi,%rax + 40f1e0: 5b pop %rbx + 40f1e1: 5d pop %rbp + 40f1e2: 41 5c pop %r12 + 40f1e4: 41 5d pop %r13 + 40f1e6: 41 5e pop %r14 + 40f1e8: 41 5f pop %r15 + 40f1ea: c3 retq + 40f1eb: 4d 8d 61 ff lea -0x1(%r9),%r12 + 40f1ef: 4c 8b 74 24 08 mov 0x8(%rsp),%r14 + 40f1f4: 4c 89 24 24 mov %r12,(%rsp) + 40f1f8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 40f1ff: 00 + 40f200: 41 0f b6 46 01 movzbl 0x1(%r14),%eax + 40f205: 84 c0 test %al,%al + 40f207: 74 08 je 40f211 <__correctly_grouped_prefixmb+0x151> + 40f209: 49 83 c6 01 add $0x1,%r14 + 40f20d: 4c 0f be e8 movsbq %al,%r13 + 40f211: 41 80 fd 7f cmp $0x7f,%r13b + 40f215: 0f 84 85 00 00 00 je 40f2a0 <__correctly_grouped_prefixmb+0x1e0> + 40f21b: 45 84 ed test %r13b,%r13b + 40f21e: 0f 88 7c 00 00 00 js 40f2a0 <__correctly_grouped_prefixmb+0x1e0> + 40f224: 4c 39 e5 cmp %r12,%rbp + 40f227: 77 b0 ja 40f1d9 <__correctly_grouped_prefixmb+0x119> + 40f229: 4f 8d 1c 39 lea (%r9,%r15,1),%r11 + 40f22d: 4d 89 e1 mov %r12,%r9 + 40f230: 45 84 d2 test %r10b,%r10b + 40f233: 74 2c je 40f261 <__correctly_grouped_prefixmb+0x1a1> + 40f235: 45 3a 53 ff cmp -0x1(%r11),%r10b + 40f239: 48 8d 43 01 lea 0x1(%rbx),%rax + 40f23d: 4c 89 df mov %r11,%rdi + 40f240: 74 18 je 40f25a <__correctly_grouped_prefixmb+0x19a> + 40f242: eb 3c jmp 40f280 <__correctly_grouped_prefixmb+0x1c0> + 40f244: 0f 1f 40 00 nopl 0x0(%rax) + 40f248: 44 0f b6 47 fe movzbl -0x2(%rdi),%r8d + 40f24d: 48 83 c0 01 add $0x1,%rax + 40f251: 48 83 ef 01 sub $0x1,%rdi + 40f255: 44 38 c1 cmp %r8b,%cl + 40f258: 75 26 jne 40f280 <__correctly_grouped_prefixmb+0x1c0> + 40f25a: 0f b6 08 movzbl (%rax),%ecx + 40f25d: 84 c9 test %cl,%cl + 40f25f: 75 e7 jne 40f248 <__correctly_grouped_prefixmb+0x188> + 40f261: 4d 29 cc sub %r9,%r12 + 40f264: 4c 39 cd cmp %r9,%rbp + 40f267: 77 27 ja 40f290 <__correctly_grouped_prefixmb+0x1d0> + 40f269: 49 0f be c5 movsbq %r13b,%rax + 40f26d: 49 39 c4 cmp %rax,%r12 + 40f270: 0f 85 24 ff ff ff jne 40f19a <__correctly_grouped_prefixmb+0xda> + 40f276: 4d 8d 61 ff lea -0x1(%r9),%r12 + 40f27a: eb 84 jmp 40f200 <__correctly_grouped_prefixmb+0x140> + 40f27c: 0f 1f 40 00 nopl 0x0(%rax) + 40f280: 49 83 e9 01 sub $0x1,%r9 + 40f284: 49 83 eb 01 sub $0x1,%r11 + 40f288: 4c 39 ca cmp %r9,%rdx + 40f28b: 75 a3 jne 40f230 <__correctly_grouped_prefixmb+0x170> + 40f28d: 49 29 d4 sub %rdx,%r12 + 40f290: 4d 39 e5 cmp %r12,%r13 + 40f293: 0f 8c 01 ff ff ff jl 40f19a <__correctly_grouped_prefixmb+0xda> + 40f299: e9 3b ff ff ff jmpq 40f1d9 <__correctly_grouped_prefixmb+0x119> + 40f29e: 66 90 xchg %ax,%ax + 40f2a0: 4c 39 e5 cmp %r12,%rbp + 40f2a3: 0f 87 30 ff ff ff ja 40f1d9 <__correctly_grouped_prefixmb+0x119> + 40f2a9: 4f 8d 1c 39 lea (%r9,%r15,1),%r11 + 40f2ad: 4d 89 e1 mov %r12,%r9 + 40f2b0: 45 84 d2 test %r10b,%r10b + 40f2b3: 74 38 je 40f2ed <__correctly_grouped_prefixmb+0x22d> + 40f2b5: 45 38 53 ff cmp %r10b,-0x1(%r11) + 40f2b9: 48 8d 43 01 lea 0x1(%rbx),%rax + 40f2bd: 4c 89 df mov %r11,%rdi + 40f2c0: 74 24 je 40f2e6 <__correctly_grouped_prefixmb+0x226> + 40f2c2: e9 01 ff ff ff jmpq 40f1c8 <__correctly_grouped_prefixmb+0x108> + 40f2c7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 40f2ce: 00 00 + 40f2d0: 44 0f b6 47 fe movzbl -0x2(%rdi),%r8d + 40f2d5: 48 83 c0 01 add $0x1,%rax + 40f2d9: 48 83 ef 01 sub $0x1,%rdi + 40f2dd: 44 38 c1 cmp %r8b,%cl + 40f2e0: 0f 85 e2 fe ff ff jne 40f1c8 <__correctly_grouped_prefixmb+0x108> + 40f2e6: 0f b6 08 movzbl (%rax),%ecx + 40f2e9: 84 c9 test %cl,%cl + 40f2eb: 75 e3 jne 40f2d0 <__correctly_grouped_prefixmb+0x210> + 40f2ed: 4c 39 cd cmp %r9,%rbp + 40f2f0: 76 84 jbe 40f276 <__correctly_grouped_prefixmb+0x1b6> + 40f2f2: e9 e2 fe ff ff jmpq 40f1d9 <__correctly_grouped_prefixmb+0x119> + 40f2f7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 40f2fe: 00 00 + +000000000040f300 <___asprintf>: + 40f300: 48 81 ec d8 00 00 00 sub $0xd8,%rsp + 40f307: 84 c0 test %al,%al + 40f309: 48 89 54 24 30 mov %rdx,0x30(%rsp) + 40f30e: 48 89 4c 24 38 mov %rcx,0x38(%rsp) + 40f313: 4c 89 44 24 40 mov %r8,0x40(%rsp) + 40f318: 4c 89 4c 24 48 mov %r9,0x48(%rsp) + 40f31d: 74 37 je 40f356 <___asprintf+0x56> + 40f31f: 0f 29 44 24 50 movaps %xmm0,0x50(%rsp) + 40f324: 0f 29 4c 24 60 movaps %xmm1,0x60(%rsp) + 40f329: 0f 29 54 24 70 movaps %xmm2,0x70(%rsp) + 40f32e: 0f 29 9c 24 80 00 00 movaps %xmm3,0x80(%rsp) + 40f335: 00 + 40f336: 0f 29 a4 24 90 00 00 movaps %xmm4,0x90(%rsp) + 40f33d: 00 + 40f33e: 0f 29 ac 24 a0 00 00 movaps %xmm5,0xa0(%rsp) + 40f345: 00 + 40f346: 0f 29 b4 24 b0 00 00 movaps %xmm6,0xb0(%rsp) + 40f34d: 00 + 40f34e: 0f 29 bc 24 c0 00 00 movaps %xmm7,0xc0(%rsp) + 40f355: 00 + 40f356: 48 8d 84 24 e0 00 00 lea 0xe0(%rsp),%rax + 40f35d: 00 + 40f35e: 48 8d 54 24 08 lea 0x8(%rsp),%rdx + 40f363: 48 89 44 24 10 mov %rax,0x10(%rsp) + 40f368: 48 8d 44 24 20 lea 0x20(%rsp),%rax + 40f36d: c7 44 24 08 10 00 00 movl $0x10,0x8(%rsp) + 40f374: 00 + 40f375: c7 44 24 0c 30 00 00 movl $0x30,0xc(%rsp) + 40f37c: 00 + 40f37d: 48 89 44 24 18 mov %rax,0x18(%rsp) + 40f382: e8 19 1f 00 00 callq 4112a0 <_IO_vasprintf> + 40f387: 48 81 c4 d8 00 00 00 add $0xd8,%rsp + 40f38e: c3 retq + 40f38f: 90 nop + +000000000040f390 <__fxprintf>: + 40f390: 55 push %rbp + 40f391: 48 89 e5 mov %rsp,%rbp + 40f394: 41 55 push %r13 + 40f396: 41 54 push %r12 + 40f398: 53 push %rbx + 40f399: 49 89 fc mov %rdi,%r12 + 40f39c: 49 89 f5 mov %rsi,%r13 + 40f39f: 48 81 ec d8 00 00 00 sub $0xd8,%rsp + 40f3a6: 84 c0 test %al,%al + 40f3a8: 48 89 95 40 ff ff ff mov %rdx,-0xc0(%rbp) + 40f3af: 48 89 8d 48 ff ff ff mov %rcx,-0xb8(%rbp) + 40f3b6: 4c 89 85 50 ff ff ff mov %r8,-0xb0(%rbp) + 40f3bd: 4c 89 8d 58 ff ff ff mov %r9,-0xa8(%rbp) + 40f3c4: 74 26 je 40f3ec <__fxprintf+0x5c> + 40f3c6: 0f 29 85 60 ff ff ff movaps %xmm0,-0xa0(%rbp) + 40f3cd: 0f 29 8d 70 ff ff ff movaps %xmm1,-0x90(%rbp) + 40f3d4: 0f 29 55 80 movaps %xmm2,-0x80(%rbp) + 40f3d8: 0f 29 5d 90 movaps %xmm3,-0x70(%rbp) + 40f3dc: 0f 29 65 a0 movaps %xmm4,-0x60(%rbp) + 40f3e0: 0f 29 6d b0 movaps %xmm5,-0x50(%rbp) + 40f3e4: 0f 29 75 c0 movaps %xmm6,-0x40(%rbp) + 40f3e8: 0f 29 7d d0 movaps %xmm7,-0x30(%rbp) + 40f3ec: 4d 85 e4 test %r12,%r12 + 40f3ef: 48 8d 45 10 lea 0x10(%rbp),%rax + 40f3f3: 4c 0f 44 25 3d b3 2b cmove 0x2bb33d(%rip),%r12 # 6ca738 <_IO_stderr> + 40f3fa: 00 + 40f3fb: 48 89 85 20 ff ff ff mov %rax,-0xe0(%rbp) + 40f402: 48 8d 85 30 ff ff ff lea -0xd0(%rbp),%rax + 40f409: c7 85 18 ff ff ff 10 movl $0x10,-0xe8(%rbp) + 40f410: 00 00 00 + 40f413: c7 85 1c ff ff ff 30 movl $0x30,-0xe4(%rbp) + 40f41a: 00 00 00 + 40f41d: 48 89 85 28 ff ff ff mov %rax,-0xd8(%rbp) + 40f424: 41 8b 84 24 c0 00 00 mov 0xc0(%r12),%eax + 40f42b: 00 + 40f42c: 85 c0 test %eax,%eax + 40f42e: 7e 70 jle 40f4a0 <__fxprintf+0x110> + 40f430: 4c 89 ef mov %r13,%rdi + 40f433: 48 89 e3 mov %rsp,%rbx + 40f436: e8 15 42 01 00 callq 423650 + 40f43b: 48 83 c0 01 add $0x1,%rax + 40f43f: 48 8d 14 85 12 00 00 lea 0x12(,%rax,4),%rdx + 40f446: 00 + 40f447: 48 83 e2 f0 and $0xfffffffffffffff0,%rdx + 40f44b: 48 29 d4 sub %rdx,%rsp + 40f44e: 48 85 c0 test %rax,%rax + 40f451: 48 89 e6 mov %rsp,%rsi + 40f454: 74 28 je 40f47e <__fxprintf+0xee> + 40f456: 41 0f be 4d 00 movsbl 0x0(%r13),%ecx + 40f45b: 84 c9 test %cl,%cl + 40f45d: 78 5e js 40f4bd <__fxprintf+0x12d> + 40f45f: 31 d2 xor %edx,%edx + 40f461: eb 0f jmp 40f472 <__fxprintf+0xe2> + 40f463: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 40f468: 41 0f be 4c 15 00 movsbl 0x0(%r13,%rdx,1),%ecx + 40f46e: 84 c9 test %cl,%cl + 40f470: 78 4b js 40f4bd <__fxprintf+0x12d> + 40f472: 89 0c 96 mov %ecx,(%rsi,%rdx,4) + 40f475: 48 83 c2 01 add $0x1,%rdx + 40f479: 48 39 d0 cmp %rdx,%rax + 40f47c: 75 ea jne 40f468 <__fxprintf+0xd8> + 40f47e: 48 8d 95 18 ff ff ff lea -0xe8(%rbp),%rdx + 40f485: 4c 89 e7 mov %r12,%rdi + 40f488: e8 03 fd 04 00 callq 45f190 <_IO_vfwprintf> + 40f48d: 48 89 dc mov %rbx,%rsp + 40f490: 48 8d 65 e8 lea -0x18(%rbp),%rsp + 40f494: 5b pop %rbx + 40f495: 41 5c pop %r12 + 40f497: 41 5d pop %r13 + 40f499: 5d pop %rbp + 40f49a: c3 retq + 40f49b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 40f4a0: 48 8d 95 18 ff ff ff lea -0xe8(%rbp),%rdx + 40f4a7: 4c 89 ee mov %r13,%rsi + 40f4aa: 4c 89 e7 mov %r12,%rdi + 40f4ad: e8 1e 54 04 00 callq 4548d0 <_IO_vfprintf> + 40f4b2: 48 8d 65 e8 lea -0x18(%rbp),%rsp + 40f4b6: 5b pop %rbx + 40f4b7: 41 5c pop %r12 + 40f4b9: 41 5d pop %r13 + 40f4bb: 5d pop %rbp + 40f4bc: c3 retq + 40f4bd: b9 48 19 4a 00 mov $0x4a1948,%ecx + 40f4c2: ba 2c 00 00 00 mov $0x2c,%edx + 40f4c7: be 25 19 4a 00 mov $0x4a1925,%esi + 40f4cc: bf 30 19 4a 00 mov $0x4a1930,%edi + 40f4d1: e8 6a 22 ff ff callq 401740 <__assert_fail> + 40f4d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 40f4dd: 00 00 00 + +000000000040f4e0 <_IO_new_fclose>: + 40f4e0: 41 54 push %r12 + 40f4e2: 55 push %rbp + 40f4e3: 53 push %rbx + 40f4e4: 8b 07 mov (%rdi),%eax + 40f4e6: 48 89 fb mov %rdi,%rbx + 40f4e9: f6 c4 20 test $0x20,%ah + 40f4ec: 0f 85 fe 00 00 00 jne 40f5f0 <_IO_new_fclose+0x110> + 40f4f2: 89 c2 mov %eax,%edx + 40f4f4: 81 e2 00 80 00 00 and $0x8000,%edx + 40f4fa: 0f 84 fc 00 00 00 je 40f5fc <_IO_new_fclose+0x11c> + 40f500: c1 e0 1a shl $0x1a,%eax + 40f503: c1 f8 1f sar $0x1f,%eax + 40f506: 85 d2 test %edx,%edx + 40f508: 89 c5 mov %eax,%ebp + 40f50a: 0f 84 71 01 00 00 je 40f681 <_IO_new_fclose+0x1a1> + 40f510: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 40f517: 31 f6 xor %esi,%esi + 40f519: 48 89 df mov %rbx,%rdi + 40f51c: ff 50 10 callq *0x10(%rax) + 40f51f: 8b 83 c0 00 00 00 mov 0xc0(%rbx),%eax + 40f525: 85 c0 test %eax,%eax + 40f527: 0f 8e a3 01 00 00 jle 40f6d0 <_IO_new_fclose+0x1f0> + 40f52d: 4c 8b a3 98 00 00 00 mov 0x98(%rbx),%r12 + 40f534: be 01 00 00 00 mov $0x1,%esi + 40f539: 31 c0 xor %eax,%eax + 40f53b: 83 3d 7a dc 2b 00 00 cmpl $0x0,0x2bdc7a(%rip) # 6cd1bc <__libc_multiple_threads> + 40f542: 74 0c je 40f550 <_IO_new_fclose+0x70> + 40f544: f0 0f b1 35 84 dd 2b lock cmpxchg %esi,0x2bdd84(%rip) # 6cd2d0 <__gconv_lock> + 40f54b: 00 + 40f54c: 75 0b jne 40f559 <_IO_new_fclose+0x79> + 40f54e: eb 23 jmp 40f573 <_IO_new_fclose+0x93> + 40f550: 0f b1 35 79 dd 2b 00 cmpxchg %esi,0x2bdd79(%rip) # 6cd2d0 <__gconv_lock> + 40f557: 74 1a je 40f573 <_IO_new_fclose+0x93> + 40f559: 48 8d 3d 70 dd 2b 00 lea 0x2bdd70(%rip),%rdi # 6cd2d0 <__gconv_lock> + 40f560: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 40f567: e8 64 30 03 00 callq 4425d0 <__lll_lock_wait_private> + 40f56c: 48 81 c4 80 00 00 00 add $0x80,%rsp + 40f573: 49 8b 7c 24 48 mov 0x48(%r12),%rdi + 40f578: e8 43 5f 03 00 callq 4454c0 <__gconv_release_step> + 40f57d: 49 8b bc 24 88 00 00 mov 0x88(%r12),%rdi + 40f584: 00 + 40f585: e8 36 5f 03 00 callq 4454c0 <__gconv_release_step> + 40f58a: 83 3d 2b dc 2b 00 00 cmpl $0x0,0x2bdc2b(%rip) # 6cd1bc <__libc_multiple_threads> + 40f591: 74 0b je 40f59e <_IO_new_fclose+0xbe> + 40f593: f0 ff 0d 36 dd 2b 00 lock decl 0x2bdd36(%rip) # 6cd2d0 <__gconv_lock> + 40f59a: 75 0a jne 40f5a6 <_IO_new_fclose+0xc6> + 40f59c: eb 22 jmp 40f5c0 <_IO_new_fclose+0xe0> + 40f59e: ff 0d 2c dd 2b 00 decl 0x2bdd2c(%rip) # 6cd2d0 <__gconv_lock> + 40f5a4: 74 1a je 40f5c0 <_IO_new_fclose+0xe0> + 40f5a6: 48 8d 3d 23 dd 2b 00 lea 0x2bdd23(%rip),%rdi # 6cd2d0 <__gconv_lock> + 40f5ad: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 40f5b4: e8 47 30 03 00 callq 442600 <__lll_unlock_wake_private> + 40f5b9: 48 81 c4 80 00 00 00 add $0x80,%rsp + 40f5c0: 48 3b 1d 81 b1 2b 00 cmp 0x2bb181(%rip),%rbx # 6ca748 <_IO_stdin> + 40f5c7: 74 1a je 40f5e3 <_IO_new_fclose+0x103> + 40f5c9: 48 3b 1d 70 b1 2b 00 cmp 0x2bb170(%rip),%rbx # 6ca740 <_IO_stdout> + 40f5d0: 74 11 je 40f5e3 <_IO_new_fclose+0x103> + 40f5d2: 48 3b 1d 5f b1 2b 00 cmp 0x2bb15f(%rip),%rbx # 6ca738 <_IO_stderr> + 40f5d9: 74 08 je 40f5e3 <_IO_new_fclose+0x103> + 40f5db: 48 89 df mov %rbx,%rdi + 40f5de: e8 cd e7 00 00 callq 41ddb0 <__cfree> + 40f5e3: 89 e8 mov %ebp,%eax + 40f5e5: 5b pop %rbx + 40f5e6: 5d pop %rbp + 40f5e7: 41 5c pop %r12 + 40f5e9: c3 retq + 40f5ea: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 40f5f0: e8 5b 4e 00 00 callq 414450 <_IO_un_link> + 40f5f5: 8b 03 mov (%rbx),%eax + 40f5f7: f6 c4 80 test $0x80,%ah + 40f5fa: 75 5a jne 40f656 <_IO_new_fclose+0x176> + 40f5fc: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx + 40f603: 64 4c 8b 04 25 10 00 mov %fs:0x10,%r8 + 40f60a: 00 00 + 40f60c: 4c 3b 42 08 cmp 0x8(%rdx),%r8 + 40f610: 74 40 je 40f652 <_IO_new_fclose+0x172> + 40f612: be 01 00 00 00 mov $0x1,%esi + 40f617: 31 c0 xor %eax,%eax + 40f619: 83 3d 9c db 2b 00 00 cmpl $0x0,0x2bdb9c(%rip) # 6cd1bc <__libc_multiple_threads> + 40f620: 74 08 je 40f62a <_IO_new_fclose+0x14a> + 40f622: f0 0f b1 32 lock cmpxchg %esi,(%rdx) + 40f626: 75 07 jne 40f62f <_IO_new_fclose+0x14f> + 40f628: eb 1b jmp 40f645 <_IO_new_fclose+0x165> + 40f62a: 0f b1 32 cmpxchg %esi,(%rdx) + 40f62d: 74 16 je 40f645 <_IO_new_fclose+0x165> + 40f62f: 48 8d 3a lea (%rdx),%rdi + 40f632: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 40f639: e8 92 2f 03 00 callq 4425d0 <__lll_lock_wait_private> + 40f63e: 48 81 c4 80 00 00 00 add $0x80,%rsp + 40f645: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx + 40f64c: 8b 03 mov (%rbx),%eax + 40f64e: 4c 89 42 08 mov %r8,0x8(%rdx) + 40f652: 83 42 04 01 addl $0x1,0x4(%rdx) + 40f656: 89 c2 mov %eax,%edx + 40f658: 81 e2 00 80 00 00 and $0x8000,%edx + 40f65e: f6 c4 20 test $0x20,%ah + 40f661: 0f 84 99 fe ff ff je 40f500 <_IO_new_fclose+0x20> + 40f667: 48 89 df mov %rbx,%rdi + 40f66a: e8 71 3c 00 00 callq 4132e0 <_IO_new_file_close_it> + 40f66f: 8b 13 mov (%rbx),%edx + 40f671: 89 c5 mov %eax,%ebp + 40f673: 81 e2 00 80 00 00 and $0x8000,%edx + 40f679: 85 d2 test %edx,%edx + 40f67b: 0f 85 8f fe ff ff jne 40f510 <_IO_new_fclose+0x30> + 40f681: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx + 40f688: 83 6a 04 01 subl $0x1,0x4(%rdx) + 40f68c: 0f 85 7e fe ff ff jne 40f510 <_IO_new_fclose+0x30> + 40f692: 48 c7 42 08 00 00 00 movq $0x0,0x8(%rdx) + 40f699: 00 + 40f69a: 83 3d 1b db 2b 00 00 cmpl $0x0,0x2bdb1b(%rip) # 6cd1bc <__libc_multiple_threads> + 40f6a1: 74 07 je 40f6aa <_IO_new_fclose+0x1ca> + 40f6a3: f0 ff 0a lock decl (%rdx) + 40f6a6: 75 06 jne 40f6ae <_IO_new_fclose+0x1ce> + 40f6a8: eb 1a jmp 40f6c4 <_IO_new_fclose+0x1e4> + 40f6aa: ff 0a decl (%rdx) + 40f6ac: 74 16 je 40f6c4 <_IO_new_fclose+0x1e4> + 40f6ae: 48 8d 3a lea (%rdx),%rdi + 40f6b1: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 40f6b8: e8 43 2f 03 00 callq 442600 <__lll_unlock_wake_private> + 40f6bd: 48 81 c4 80 00 00 00 add $0x80,%rsp + 40f6c4: e9 47 fe ff ff jmpq 40f510 <_IO_new_fclose+0x30> + 40f6c9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 40f6d0: 48 83 7b 48 00 cmpq $0x0,0x48(%rbx) + 40f6d5: 0f 84 e5 fe ff ff je 40f5c0 <_IO_new_fclose+0xe0> + 40f6db: 48 89 df mov %rbx,%rdi + 40f6de: e8 4d 53 00 00 callq 414a30 <_IO_free_backup_area> + 40f6e3: e9 d8 fe ff ff jmpq 40f5c0 <_IO_new_fclose+0xe0> + 40f6e8: 48 89 c6 mov %rax,%rsi + 40f6eb: f7 03 00 80 00 00 testl $0x8000,(%rbx) + 40f6f1: 75 3f jne 40f732 <_IO_new_fclose+0x252> + 40f6f3: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx + 40f6fa: 83 6a 04 01 subl $0x1,0x4(%rdx) + 40f6fe: 75 32 jne 40f732 <_IO_new_fclose+0x252> + 40f700: 48 c7 42 08 00 00 00 movq $0x0,0x8(%rdx) + 40f707: 00 + 40f708: 83 3d ad da 2b 00 00 cmpl $0x0,0x2bdaad(%rip) # 6cd1bc <__libc_multiple_threads> + 40f70f: 74 07 je 40f718 <_IO_new_fclose+0x238> + 40f711: f0 ff 0a lock decl (%rdx) + 40f714: 75 06 jne 40f71c <_IO_new_fclose+0x23c> + 40f716: eb 1a jmp 40f732 <_IO_new_fclose+0x252> + 40f718: ff 0a decl (%rdx) + 40f71a: 74 16 je 40f732 <_IO_new_fclose+0x252> + 40f71c: 48 8d 3a lea (%rdx),%rdi + 40f71f: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 40f726: e8 d5 2e 03 00 callq 442600 <__lll_unlock_wake_private> + 40f72b: 48 81 c4 80 00 00 00 add $0x80,%rsp + 40f732: 48 89 f7 mov %rsi,%rdi + 40f735: e8 36 ce 08 00 callq 49c570 <_Unwind_Resume> + 40f73a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + +000000000040f740 <_IO_fflush>: + 40f740: 48 85 ff test %rdi,%rdi + 40f743: 0f 84 d7 00 00 00 je 40f820 <_IO_fflush+0xe0> + 40f749: 53 push %rbx + 40f74a: 8b 07 mov (%rdi),%eax + 40f74c: 48 89 fa mov %rdi,%rdx + 40f74f: 25 00 80 00 00 and $0x8000,%eax + 40f754: 75 59 jne 40f7af <_IO_fflush+0x6f> + 40f756: 4c 8b 87 88 00 00 00 mov 0x88(%rdi),%r8 + 40f75d: 64 4c 8b 0c 25 10 00 mov %fs:0x10,%r9 + 40f764: 00 00 + 40f766: 4d 3b 48 08 cmp 0x8(%r8),%r9 + 40f76a: 74 3e je 40f7aa <_IO_fflush+0x6a> + 40f76c: be 01 00 00 00 mov $0x1,%esi + 40f771: 83 3d 44 da 2b 00 00 cmpl $0x0,0x2bda44(%rip) # 6cd1bc <__libc_multiple_threads> + 40f778: 74 09 je 40f783 <_IO_fflush+0x43> + 40f77a: f0 41 0f b1 30 lock cmpxchg %esi,(%r8) + 40f77f: 75 08 jne 40f789 <_IO_fflush+0x49> + 40f781: eb 1c jmp 40f79f <_IO_fflush+0x5f> + 40f783: 41 0f b1 30 cmpxchg %esi,(%r8) + 40f787: 74 16 je 40f79f <_IO_fflush+0x5f> + 40f789: 49 8d 38 lea (%r8),%rdi + 40f78c: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 40f793: e8 38 2e 03 00 callq 4425d0 <__lll_lock_wait_private> + 40f798: 48 81 c4 80 00 00 00 add $0x80,%rsp + 40f79f: 4c 8b 82 88 00 00 00 mov 0x88(%rdx),%r8 + 40f7a6: 4d 89 48 08 mov %r9,0x8(%r8) + 40f7aa: 41 83 40 04 01 addl $0x1,0x4(%r8) + 40f7af: 48 8b 82 d8 00 00 00 mov 0xd8(%rdx),%rax + 40f7b6: 48 89 d3 mov %rdx,%rbx + 40f7b9: 48 89 d7 mov %rdx,%rdi + 40f7bc: ff 50 60 callq *0x60(%rax) + 40f7bf: 31 d2 xor %edx,%edx + 40f7c1: 85 c0 test %eax,%eax + 40f7c3: 0f 95 c2 setne %dl + 40f7c6: f7 da neg %edx + 40f7c8: f7 03 00 80 00 00 testl $0x8000,(%rbx) + 40f7ce: 74 08 je 40f7d8 <_IO_fflush+0x98> + 40f7d0: 89 d0 mov %edx,%eax + 40f7d2: 5b pop %rbx + 40f7d3: c3 retq + 40f7d4: 0f 1f 40 00 nopl 0x0(%rax) + 40f7d8: 48 8b b3 88 00 00 00 mov 0x88(%rbx),%rsi + 40f7df: 83 6e 04 01 subl $0x1,0x4(%rsi) + 40f7e3: 75 eb jne 40f7d0 <_IO_fflush+0x90> + 40f7e5: 48 c7 46 08 00 00 00 movq $0x0,0x8(%rsi) + 40f7ec: 00 + 40f7ed: 83 3d c8 d9 2b 00 00 cmpl $0x0,0x2bd9c8(%rip) # 6cd1bc <__libc_multiple_threads> + 40f7f4: 74 07 je 40f7fd <_IO_fflush+0xbd> + 40f7f6: f0 ff 0e lock decl (%rsi) + 40f7f9: 75 06 jne 40f801 <_IO_fflush+0xc1> + 40f7fb: eb 1a jmp 40f817 <_IO_fflush+0xd7> + 40f7fd: ff 0e decl (%rsi) + 40f7ff: 74 16 je 40f817 <_IO_fflush+0xd7> + 40f801: 48 8d 3e lea (%rsi),%rdi + 40f804: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 40f80b: e8 f0 2d 03 00 callq 442600 <__lll_unlock_wake_private> + 40f810: 48 81 c4 80 00 00 00 add $0x80,%rsp + 40f817: 89 d0 mov %edx,%eax + 40f819: 5b pop %rbx + 40f81a: c3 retq + 40f81b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 40f820: e9 ab 64 00 00 jmpq 415cd0 <_IO_flush_all> + 40f825: 48 89 c6 mov %rax,%rsi + 40f828: f7 03 00 80 00 00 testl $0x8000,(%rbx) + 40f82e: 75 3f jne 40f86f <_IO_fflush+0x12f> + 40f830: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx + 40f837: 83 6a 04 01 subl $0x1,0x4(%rdx) + 40f83b: 75 32 jne 40f86f <_IO_fflush+0x12f> + 40f83d: 48 c7 42 08 00 00 00 movq $0x0,0x8(%rdx) + 40f844: 00 + 40f845: 83 3d 70 d9 2b 00 00 cmpl $0x0,0x2bd970(%rip) # 6cd1bc <__libc_multiple_threads> + 40f84c: 74 07 je 40f855 <_IO_fflush+0x115> + 40f84e: f0 ff 0a lock decl (%rdx) + 40f851: 75 06 jne 40f859 <_IO_fflush+0x119> + 40f853: eb 1a jmp 40f86f <_IO_fflush+0x12f> + 40f855: ff 0a decl (%rdx) + 40f857: 74 16 je 40f86f <_IO_fflush+0x12f> + 40f859: 48 8d 3a lea (%rdx),%rdi + 40f85c: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 40f863: e8 98 2d 03 00 callq 442600 <__lll_unlock_wake_private> + 40f868: 48 81 c4 80 00 00 00 add $0x80,%rsp + 40f86f: 48 89 f7 mov %rsi,%rdi + 40f872: e8 f9 cc 08 00 callq 49c570 <_Unwind_Resume> + 40f877: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 40f87e: 00 00 + +000000000040f880 <__fopen_maybe_mmap>: + 40f880: f6 47 74 01 testb $0x1,0x74(%rdi) + 40f884: 48 89 f8 mov %rdi,%rax + 40f887: 74 30 je 40f8b9 <__fopen_maybe_mmap+0x39> + 40f889: f6 07 08 testb $0x8,(%rdi) + 40f88c: 74 2b je 40f8b9 <__fopen_maybe_mmap+0x39> + 40f88e: 8b 97 c0 00 00 00 mov 0xc0(%rdi),%edx + 40f894: b9 a0 19 4a 00 mov $0x4a19a0,%ecx + 40f899: 85 d2 test %edx,%edx + 40f89b: ba a0 1c 4a 00 mov $0x4a1ca0,%edx + 40f8a0: 48 0f 4f d1 cmovg %rcx,%rdx + 40f8a4: 48 89 97 d8 00 00 00 mov %rdx,0xd8(%rdi) + 40f8ab: 48 8b 97 a0 00 00 00 mov 0xa0(%rdi),%rdx + 40f8b2: 48 89 8a 30 01 00 00 mov %rcx,0x130(%rdx) + 40f8b9: f3 c3 repz retq + 40f8bb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + +000000000040f8c0 <__fopen_internal>: + 40f8c0: 41 55 push %r13 + 40f8c2: 41 54 push %r12 + 40f8c4: 41 89 d5 mov %edx,%r13d + 40f8c7: 55 push %rbp + 40f8c8: 53 push %rbx + 40f8c9: 48 89 fd mov %rdi,%rbp + 40f8cc: bf 28 02 00 00 mov $0x228,%edi + 40f8d1: 49 89 f4 mov %rsi,%r12 + 40f8d4: 48 83 ec 08 sub $0x8,%rsp + 40f8d8: e8 33 e1 00 00 callq 41da10 <__libc_malloc> + 40f8dd: 48 85 c0 test %rax,%rax + 40f8e0: 0f 84 b2 00 00 00 je 40f998 <__fopen_internal+0xd8> + 40f8e6: 48 8d 90 e0 00 00 00 lea 0xe0(%rax),%rdx + 40f8ed: 48 8d 88 f0 00 00 00 lea 0xf0(%rax),%rcx + 40f8f4: 48 89 c3 mov %rax,%rbx + 40f8f7: 31 f6 xor %esi,%esi + 40f8f9: 48 89 c7 mov %rax,%rdi + 40f8fc: 41 b8 20 1b 4a 00 mov $0x4a1b20,%r8d + 40f902: 48 89 90 88 00 00 00 mov %rdx,0x88(%rax) + 40f909: 31 d2 xor %edx,%edx + 40f90b: e8 b0 5b 00 00 callq 4154c0 <_IO_no_init> + 40f910: 48 89 df mov %rbx,%rdi + 40f913: 48 c7 83 d8 00 00 00 movq $0x4a1e20,0xd8(%rbx) + 40f91a: 20 1e 4a 00 + 40f91e: e8 0d 37 00 00 callq 413030 <_IO_new_file_init> + 40f923: 44 89 e9 mov %r13d,%ecx + 40f926: 4c 89 e2 mov %r12,%rdx + 40f929: 48 89 ee mov %rbp,%rsi + 40f92c: 48 89 df mov %rbx,%rdi + 40f92f: e8 2c 3b 00 00 callq 413460 <_IO_new_file_fopen> + 40f934: 48 85 c0 test %rax,%rax + 40f937: 74 63 je 40f99c <__fopen_internal+0xdc> + 40f939: f6 43 74 01 testb $0x1,0x74(%rbx) + 40f93d: 74 05 je 40f944 <__fopen_internal+0x84> + 40f93f: f6 03 08 testb $0x8,(%rbx) + 40f942: 75 14 jne 40f958 <__fopen_internal+0x98> + 40f944: 48 83 c4 08 add $0x8,%rsp + 40f948: 48 89 d8 mov %rbx,%rax + 40f94b: 5b pop %rbx + 40f94c: 5d pop %rbp + 40f94d: 41 5c pop %r12 + 40f94f: 41 5d pop %r13 + 40f951: c3 retq + 40f952: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 40f958: 8b 83 c0 00 00 00 mov 0xc0(%rbx),%eax + 40f95e: ba a0 19 4a 00 mov $0x4a19a0,%edx + 40f963: 85 c0 test %eax,%eax + 40f965: b8 a0 1c 4a 00 mov $0x4a1ca0,%eax + 40f96a: 48 0f 4f c2 cmovg %rdx,%rax + 40f96e: 48 89 83 d8 00 00 00 mov %rax,0xd8(%rbx) + 40f975: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 40f97c: 48 89 90 30 01 00 00 mov %rdx,0x130(%rax) + 40f983: 48 83 c4 08 add $0x8,%rsp + 40f987: 48 89 d8 mov %rbx,%rax + 40f98a: 5b pop %rbx + 40f98b: 5d pop %rbp + 40f98c: 41 5c pop %r12 + 40f98e: 41 5d pop %r13 + 40f990: c3 retq + 40f991: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 40f998: 31 db xor %ebx,%ebx + 40f99a: eb a8 jmp 40f944 <__fopen_internal+0x84> + 40f99c: 48 89 df mov %rbx,%rdi + 40f99f: e8 ac 4a 00 00 callq 414450 <_IO_un_link> + 40f9a4: 48 89 df mov %rbx,%rdi + 40f9a7: 31 db xor %ebx,%ebx + 40f9a9: e8 02 e4 00 00 callq 41ddb0 <__cfree> + 40f9ae: eb 94 jmp 40f944 <__fopen_internal+0x84> + +000000000040f9b0 <_IO_new_fopen>: + 40f9b0: 41 54 push %r12 + 40f9b2: 55 push %rbp + 40f9b3: 48 89 fd mov %rdi,%rbp + 40f9b6: 53 push %rbx + 40f9b7: bf 28 02 00 00 mov $0x228,%edi + 40f9bc: 49 89 f4 mov %rsi,%r12 + 40f9bf: e8 4c e0 00 00 callq 41da10 <__libc_malloc> + 40f9c4: 48 85 c0 test %rax,%rax + 40f9c7: 0f 84 a3 00 00 00 je 40fa70 <_IO_new_fopen+0xc0> + 40f9cd: 48 8d 90 e0 00 00 00 lea 0xe0(%rax),%rdx + 40f9d4: 48 8d 88 f0 00 00 00 lea 0xf0(%rax),%rcx + 40f9db: 48 89 c3 mov %rax,%rbx + 40f9de: 31 f6 xor %esi,%esi + 40f9e0: 48 89 c7 mov %rax,%rdi + 40f9e3: 41 b8 20 1b 4a 00 mov $0x4a1b20,%r8d + 40f9e9: 48 89 90 88 00 00 00 mov %rdx,0x88(%rax) + 40f9f0: 31 d2 xor %edx,%edx + 40f9f2: e8 c9 5a 00 00 callq 4154c0 <_IO_no_init> + 40f9f7: 48 89 df mov %rbx,%rdi + 40f9fa: 48 c7 83 d8 00 00 00 movq $0x4a1e20,0xd8(%rbx) + 40fa01: 20 1e 4a 00 + 40fa05: e8 26 36 00 00 callq 413030 <_IO_new_file_init> + 40fa0a: b9 01 00 00 00 mov $0x1,%ecx + 40fa0f: 4c 89 e2 mov %r12,%rdx + 40fa12: 48 89 ee mov %rbp,%rsi + 40fa15: 48 89 df mov %rbx,%rdi + 40fa18: e8 43 3a 00 00 callq 413460 <_IO_new_file_fopen> + 40fa1d: 48 85 c0 test %rax,%rax + 40fa20: 74 52 je 40fa74 <_IO_new_fopen+0xc4> + 40fa22: f6 43 74 01 testb $0x1,0x74(%rbx) + 40fa26: 74 05 je 40fa2d <_IO_new_fopen+0x7d> + 40fa28: f6 03 08 testb $0x8,(%rbx) + 40fa2b: 75 0b jne 40fa38 <_IO_new_fopen+0x88> + 40fa2d: 48 89 d8 mov %rbx,%rax + 40fa30: 5b pop %rbx + 40fa31: 5d pop %rbp + 40fa32: 41 5c pop %r12 + 40fa34: c3 retq + 40fa35: 0f 1f 00 nopl (%rax) + 40fa38: 8b 83 c0 00 00 00 mov 0xc0(%rbx),%eax + 40fa3e: ba a0 19 4a 00 mov $0x4a19a0,%edx + 40fa43: 85 c0 test %eax,%eax + 40fa45: b8 a0 1c 4a 00 mov $0x4a1ca0,%eax + 40fa4a: 48 0f 4f c2 cmovg %rdx,%rax + 40fa4e: 48 89 83 d8 00 00 00 mov %rax,0xd8(%rbx) + 40fa55: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 40fa5c: 48 89 90 30 01 00 00 mov %rdx,0x130(%rax) + 40fa63: 48 89 d8 mov %rbx,%rax + 40fa66: 5b pop %rbx + 40fa67: 5d pop %rbp + 40fa68: 41 5c pop %r12 + 40fa6a: c3 retq + 40fa6b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 40fa70: 31 db xor %ebx,%ebx + 40fa72: eb b9 jmp 40fa2d <_IO_new_fopen+0x7d> + 40fa74: 48 89 df mov %rbx,%rdi + 40fa77: e8 d4 49 00 00 callq 414450 <_IO_un_link> + 40fa7c: 48 89 df mov %rbx,%rdi + 40fa7f: 31 db xor %ebx,%ebx + 40fa81: e8 2a e3 00 00 callq 41ddb0 <__cfree> + 40fa86: eb a5 jmp 40fa2d <_IO_new_fopen+0x7d> + 40fa88: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 40fa8f: 00 + +000000000040fa90 : + 40fa90: 41 54 push %r12 + 40fa92: 55 push %rbp + 40fa93: 41 89 f4 mov %esi,%r12d + 40fa96: 53 push %rbx + 40fa97: 48 89 fb mov %rdi,%rbx + 40fa9a: 48 83 ec 10 sub $0x10,%rsp + 40fa9e: 48 8b af 98 00 00 00 mov 0x98(%rdi),%rbp + 40faa5: 48 89 ef mov %rbp,%rdi + 40faa8: ff 55 20 callq *0x20(%rbp) + 40faab: 85 c0 test %eax,%eax + 40faad: 0f 9f c2 setg %dl + 40fab0: 41 38 d4 cmp %dl,%r12b + 40fab3: 73 3b jae 40faf0 + 40fab5: 48 8b 53 08 mov 0x8(%rbx),%rdx + 40fab9: 48 2b 53 18 sub 0x18(%rbx),%rdx + 40fabd: 48 63 c8 movslq %eax,%rcx + 40fac0: 48 8b b3 a0 00 00 00 mov 0xa0(%rbx),%rsi + 40fac7: 48 89 d0 mov %rdx,%rax + 40faca: 48 99 cqto + 40facc: 48 f7 f9 idiv %rcx + 40facf: 48 c1 e0 02 shl $0x2,%rax + 40fad3: 48 01 46 08 add %rax,0x8(%rsi) + 40fad7: 48 8b 46 08 mov 0x8(%rsi),%rax + 40fadb: 48 89 06 mov %rax,(%rsi) + 40fade: 31 c0 xor %eax,%eax + 40fae0: 48 83 c4 10 add $0x10,%rsp + 40fae4: 5b pop %rbx + 40fae5: 5d pop %rbp + 40fae6: 41 5c pop %r12 + 40fae8: c3 retq + 40fae9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 40faf0: 48 8b 43 18 mov 0x18(%rbx),%rax + 40faf4: 48 89 44 24 08 mov %rax,0x8(%rsp) + 40faf9: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 40fb00: 48 8b 50 58 mov 0x58(%rax),%rdx + 40fb04: 48 89 50 60 mov %rdx,0x60(%rax) + 40fb08: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 40fb0f: 48 8b 4b 08 mov 0x8(%rbx),%rcx + 40fb13: 48 8b 53 18 mov 0x18(%rbx),%rdx + 40fb17: 48 8d 78 08 lea 0x8(%rax),%rdi + 40fb1b: 48 8d 70 58 lea 0x58(%rax),%rsi + 40fb1f: 57 push %rdi + 40fb20: ff 70 38 pushq 0x38(%rax) + 40fb23: 48 89 ef mov %rbp,%rdi + 40fb26: 4c 8b 48 10 mov 0x10(%rax),%r9 + 40fb2a: 4c 8d 44 24 18 lea 0x18(%rsp),%r8 + 40fb2f: ff 55 18 callq *0x18(%rbp) + 40fb32: 83 f8 02 cmp $0x2,%eax + 40fb35: 5a pop %rdx + 40fb36: 59 pop %rcx + 40fb37: 74 17 je 40fb50 + 40fb39: 83 f8 01 cmp $0x1,%eax + 40fb3c: 74 bb je 40faf9 + 40fb3e: 48 8b b3 a0 00 00 00 mov 0xa0(%rbx),%rsi + 40fb45: eb 90 jmp 40fad7 + 40fb47: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 40fb4e: 00 00 + 40fb50: 83 0b 20 orl $0x20,(%rbx) + 40fb53: b8 ff ff ff ff mov $0xffffffff,%eax + 40fb58: eb 86 jmp 40fae0 + 40fb5a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + +000000000040fb60 <_IO_wfile_underflow>: + 40fb60: 8b 07 mov (%rdi),%eax + 40fb62: a8 04 test $0x4,%al + 40fb64: 0f 85 96 04 00 00 jne 410000 <_IO_wfile_underflow+0x4a0> + 40fb6a: 48 8b 87 a0 00 00 00 mov 0xa0(%rdi),%rax + 40fb71: 48 8b 10 mov (%rax),%rdx + 40fb74: 48 3b 50 08 cmp 0x8(%rax),%rdx + 40fb78: 0f 82 62 03 00 00 jb 40fee0 <_IO_wfile_underflow+0x380> + 40fb7e: 41 57 push %r15 + 40fb80: 41 56 push %r14 + 40fb82: 41 55 push %r13 + 40fb84: 41 54 push %r12 + 40fb86: 55 push %rbp + 40fb87: 53 push %rbx + 40fb88: 48 89 fb mov %rdi,%rbx + 40fb8b: 48 83 ec 28 sub $0x28,%rsp + 40fb8f: 48 8b 57 08 mov 0x8(%rdi),%rdx + 40fb93: 48 3b 57 10 cmp 0x10(%rdi),%rdx + 40fb97: 4c 8b a7 98 00 00 00 mov 0x98(%rdi),%r12 + 40fb9e: 0f 82 7c 03 00 00 jb 40ff20 <_IO_wfile_underflow+0x3c0> + 40fba4: 48 8b 47 38 mov 0x38(%rdi),%rax + 40fba8: 48 89 47 10 mov %rax,0x10(%rdi) + 40fbac: 48 89 47 08 mov %rax,0x8(%rdi) + 40fbb0: 48 89 47 18 mov %rax,0x18(%rdi) + 40fbb4: 48 85 c0 test %rax,%rax + 40fbb7: 0f 84 8b 04 00 00 je 410048 <_IO_wfile_underflow+0x4e8> + 40fbbd: 48 89 43 30 mov %rax,0x30(%rbx) + 40fbc1: 48 89 43 28 mov %rax,0x28(%rbx) + 40fbc5: 48 89 43 20 mov %rax,0x20(%rbx) + 40fbc9: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 40fbd0: 48 83 78 30 00 cmpq $0x0,0x30(%rax) + 40fbd5: 0f 84 45 04 00 00 je 410020 <_IO_wfile_underflow+0x4c0> + 40fbdb: f7 03 02 02 00 00 testl $0x202,(%rbx) + 40fbe1: 0f 84 a9 00 00 00 je 40fc90 <_IO_wfile_underflow+0x130> + 40fbe7: 48 8b 2d 52 ab 2b 00 mov 0x2bab52(%rip),%rbp # 6ca740 <_IO_stdout> + 40fbee: 8b 55 00 mov 0x0(%rbp),%edx + 40fbf1: 89 d0 mov %edx,%eax + 40fbf3: 25 00 80 00 00 and $0x8000,%eax + 40fbf8: 0f 85 92 03 00 00 jne 40ff90 <_IO_wfile_underflow+0x430> + 40fbfe: 4c 8b 85 88 00 00 00 mov 0x88(%rbp),%r8 + 40fc05: 64 4c 8b 0c 25 10 00 mov %fs:0x10,%r9 + 40fc0c: 00 00 + 40fc0e: 4d 3b 48 08 cmp 0x8(%r8),%r9 + 40fc12: 0f 84 c4 04 00 00 je 4100dc <_IO_wfile_underflow+0x57c> + 40fc18: be 01 00 00 00 mov $0x1,%esi + 40fc1d: 83 3d 98 d5 2b 00 00 cmpl $0x0,0x2bd598(%rip) # 6cd1bc <__libc_multiple_threads> + 40fc24: 74 09 je 40fc2f <_IO_wfile_underflow+0xcf> + 40fc26: f0 41 0f b1 30 lock cmpxchg %esi,(%r8) + 40fc2b: 75 08 jne 40fc35 <_IO_wfile_underflow+0xd5> + 40fc2d: eb 1c jmp 40fc4b <_IO_wfile_underflow+0xeb> + 40fc2f: 41 0f b1 30 cmpxchg %esi,(%r8) + 40fc33: 74 16 je 40fc4b <_IO_wfile_underflow+0xeb> + 40fc35: 49 8d 38 lea (%r8),%rdi + 40fc38: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 40fc3f: e8 8c 29 03 00 callq 4425d0 <__lll_lock_wait_private> + 40fc44: 48 81 c4 80 00 00 00 add $0x80,%rsp + 40fc4b: 48 8b 3d ee aa 2b 00 mov 0x2baaee(%rip),%rdi # 6ca740 <_IO_stdout> + 40fc52: 4c 8b 85 88 00 00 00 mov 0x88(%rbp),%r8 + 40fc59: 8b 17 mov (%rdi),%edx + 40fc5b: 4d 89 48 08 mov %r9,0x8(%r8) + 40fc5f: 81 e2 88 02 00 00 and $0x288,%edx + 40fc65: 41 83 40 04 01 addl $0x1,0x4(%r8) + 40fc6a: 81 fa 80 02 00 00 cmp $0x280,%edx + 40fc70: 0f 84 2f 03 00 00 je 40ffa5 <_IO_wfile_underflow+0x445> + 40fc76: f7 45 00 00 80 00 00 testl $0x8000,0x0(%rbp) + 40fc7d: 75 11 jne 40fc90 <_IO_wfile_underflow+0x130> + 40fc7f: 48 8b 95 88 00 00 00 mov 0x88(%rbp),%rdx + 40fc86: 83 6a 04 01 subl $0x1,0x4(%rdx) + 40fc8a: 0f 84 15 04 00 00 je 4100a5 <_IO_wfile_underflow+0x545> + 40fc90: 48 89 df mov %rbx,%rdi + 40fc93: 4c 8d 6c 24 10 lea 0x10(%rsp),%r13 + 40fc98: 31 ed xor %ebp,%ebp + 40fc9a: e8 21 4d 00 00 callq 4149c0 <_IO_switch_to_get_mode> + 40fc9f: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 40fca6: 4c 8b 73 10 mov 0x10(%rbx),%r14 + 40fcaa: 48 8b 50 30 mov 0x30(%rax),%rdx + 40fcae: 48 89 10 mov %rdx,(%rax) + 40fcb1: 48 89 50 10 mov %rdx,0x10(%rax) + 40fcb5: 48 89 50 08 mov %rdx,0x8(%rax) + 40fcb9: 48 89 50 28 mov %rdx,0x28(%rax) + 40fcbd: 48 89 50 20 mov %rdx,0x20(%rax) + 40fcc1: 48 89 50 18 mov %rdx,0x18(%rax) + 40fcc5: 0f 1f 00 nopl (%rax) + 40fcc8: 48 8b 53 40 mov 0x40(%rbx),%rdx + 40fccc: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 40fcd3: 4c 89 f6 mov %r14,%rsi + 40fcd6: 48 89 df mov %rbx,%rdi + 40fcd9: 4c 29 f2 sub %r14,%rdx + 40fcdc: ff 50 70 callq *0x70(%rax) + 40fcdf: 48 83 f8 00 cmp $0x0,%rax + 40fce3: 0f 8e f7 00 00 00 jle 40fde0 <_IO_wfile_underflow+0x280> + 40fce9: 48 8b 8b 90 00 00 00 mov 0x90(%rbx),%rcx + 40fcf0: 48 01 43 10 add %rax,0x10(%rbx) + 40fcf4: 48 83 f9 ff cmp $0xffffffffffffffff,%rcx + 40fcf8: 74 0a je 40fd04 <_IO_wfile_underflow+0x1a4> + 40fcfa: 48 01 c1 add %rax,%rcx + 40fcfd: 48 89 8b 90 00 00 00 mov %rcx,0x90(%rbx) + 40fd04: 48 8b 93 a0 00 00 00 mov 0xa0(%rbx),%rdx + 40fd0b: 48 85 ed test %rbp,%rbp + 40fd0e: 48 8b 4a 58 mov 0x58(%rdx),%rcx + 40fd12: 48 89 4a 60 mov %rcx,0x60(%rdx) + 40fd16: 48 8b 7b 08 mov 0x8(%rbx),%rdi + 40fd1a: 48 8b 4b 10 mov 0x10(%rbx),%rcx + 40fd1e: 48 89 7b 18 mov %rdi,0x18(%rbx) + 40fd22: 0f 85 38 01 00 00 jne 40fe60 <_IO_wfile_underflow+0x300> + 40fd28: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 40fd2f: 48 8d 50 08 lea 0x8(%rax),%rdx + 40fd33: 48 8d 70 58 lea 0x58(%rax),%rsi + 40fd37: 52 push %rdx + 40fd38: ff 70 38 pushq 0x38(%rax) + 40fd3b: 48 89 fa mov %rdi,%rdx + 40fd3e: 4c 8b 48 08 mov 0x8(%rax),%r9 + 40fd42: 4c 89 e7 mov %r12,%rdi + 40fd45: 4c 8d 44 24 18 lea 0x18(%rsp),%r8 + 40fd4a: 41 ff 54 24 18 callq *0x18(%r12) + 40fd4f: 5a pop %rdx + 40fd50: 59 pop %rcx + 40fd51: 48 8b 4c 24 08 mov 0x8(%rsp),%rcx + 40fd56: 31 ed xor %ebp,%ebp + 40fd58: 48 89 ce mov %rcx,%rsi + 40fd5b: 48 8b 93 a0 00 00 00 mov 0xa0(%rbx),%rdx + 40fd62: 48 89 73 08 mov %rsi,0x8(%rbx) + 40fd66: 48 8b 7a 30 mov 0x30(%rdx),%rdi + 40fd6a: 48 39 7a 08 cmp %rdi,0x8(%rdx) + 40fd6e: 0f 85 74 02 00 00 jne 40ffe8 <_IO_wfile_underflow+0x488> + 40fd74: 83 f8 02 cmp $0x2,%eax + 40fd77: 0f 84 74 01 00 00 je 40fef1 <_IO_wfile_underflow+0x391> + 40fd7d: 83 f8 01 cmp $0x1,%eax + 40fd80: 0f 85 5e 03 00 00 jne 4100e4 <_IO_wfile_underflow+0x584> + 40fd86: 48 85 ed test %rbp,%rbp + 40fd89: 75 3d jne 40fdc8 <_IO_wfile_underflow+0x268> + 40fd8b: 4c 8b 73 18 mov 0x18(%rbx),%r14 + 40fd8f: 4c 39 f6 cmp %r14,%rsi + 40fd92: 0f 87 80 00 00 00 ja 40fe18 <_IO_wfile_underflow+0x2b8> + 40fd98: 48 8b 6b 10 mov 0x10(%rbx),%rbp + 40fd9c: 48 29 f5 sub %rsi,%rbp + 40fd9f: 48 83 fd 0f cmp $0xf,%rbp + 40fda3: 0f 87 48 01 00 00 ja 40fef1 <_IO_wfile_underflow+0x391> + 40fda9: 48 89 ea mov %rbp,%rdx + 40fdac: 4c 89 ef mov %r13,%rdi + 40fdaf: e8 6c c2 01 00 callq 42c020 + 40fdb4: 4c 89 73 10 mov %r14,0x10(%rbx) + 40fdb8: 4c 89 73 08 mov %r14,0x8(%rbx) + 40fdbc: e9 07 ff ff ff jmpq 40fcc8 <_IO_wfile_underflow+0x168> + 40fdc1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 40fdc8: 48 89 c8 mov %rcx,%rax + 40fdcb: 4c 29 e8 sub %r13,%rax + 40fdce: 75 78 jne 40fe48 <_IO_wfile_underflow+0x2e8> + 40fdd0: 48 83 fd 10 cmp $0x10,%rbp + 40fdd4: 0f 84 17 01 00 00 je 40fef1 <_IO_wfile_underflow+0x391> + 40fdda: 4c 8b 73 18 mov 0x18(%rbx),%r14 + 40fdde: eb d4 jmp 40fdb4 <_IO_wfile_underflow+0x254> + 40fde0: 0f 85 da 01 00 00 jne 40ffc0 <_IO_wfile_underflow+0x460> + 40fde6: 48 85 ed test %rbp,%rbp + 40fde9: 0f 85 d1 01 00 00 jne 40ffc0 <_IO_wfile_underflow+0x460> + 40fdef: 8b 03 mov (%rbx),%eax + 40fdf1: 48 c7 83 90 00 00 00 movq $0xffffffffffffffff,0x90(%rbx) + 40fdf8: ff ff ff ff + 40fdfc: 83 c8 10 or $0x10,%eax + 40fdff: 89 03 mov %eax,(%rbx) + 40fe01: b8 ff ff ff ff mov $0xffffffff,%eax + 40fe06: 48 83 c4 28 add $0x28,%rsp + 40fe0a: 5b pop %rbx + 40fe0b: 5d pop %rbp + 40fe0c: 41 5c pop %r12 + 40fe0e: 41 5d pop %r13 + 40fe10: 41 5e pop %r14 + 40fe12: 41 5f pop %r15 + 40fe14: c3 retq + 40fe15: 0f 1f 00 nopl (%rax) + 40fe18: 4c 8b 7b 10 mov 0x10(%rbx),%r15 + 40fe1c: 4c 89 f7 mov %r14,%rdi + 40fe1f: 49 29 f7 sub %rsi,%r15 + 40fe22: 4c 89 fa mov %r15,%rdx + 40fe25: e8 d6 04 ff ff callq 400300 <__rela_iplt_end+0x38> + 40fe2a: 4c 8b 73 10 mov 0x10(%rbx),%r14 + 40fe2e: 48 8b 43 18 mov 0x18(%rbx),%rax + 40fe32: 4d 29 fe sub %r15,%r14 + 40fe35: 48 89 43 08 mov %rax,0x8(%rbx) + 40fe39: 4c 89 73 10 mov %r14,0x10(%rbx) + 40fe3d: e9 86 fe ff ff jmpq 40fcc8 <_IO_wfile_underflow+0x168> + 40fe42: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 40fe48: 48 29 c5 sub %rax,%rbp + 40fe4b: 48 89 ce mov %rcx,%rsi + 40fe4e: 4c 89 ef mov %r13,%rdi + 40fe51: 48 89 ea mov %rbp,%rdx + 40fe54: e8 a7 04 ff ff callq 400300 <__rela_iplt_end+0x38> + 40fe59: e9 72 ff ff ff jmpq 40fdd0 <_IO_wfile_underflow+0x270> + 40fe5e: 66 90 xchg %ax,%ax + 40fe60: 41 b8 10 00 00 00 mov $0x10,%r8d + 40fe66: 4d 8d 74 2d 00 lea 0x0(%r13,%rbp,1),%r14 + 40fe6b: 48 89 fe mov %rdi,%rsi + 40fe6e: 49 29 e8 sub %rbp,%r8 + 40fe71: 49 39 c0 cmp %rax,%r8 + 40fe74: 4c 89 f7 mov %r14,%rdi + 40fe77: 49 0f 46 c0 cmovbe %r8,%rax + 40fe7b: 48 89 c2 mov %rax,%rdx + 40fe7e: 49 89 c7 mov %rax,%r15 + 40fe81: e8 3a 67 01 00 callq 4265c0 <__mempcpy> + 40fe86: 48 8b 93 a0 00 00 00 mov 0xa0(%rbx),%rdx + 40fe8d: 4c 01 fd add %r15,%rbp + 40fe90: 4c 89 e7 mov %r12,%rdi + 40fe93: 48 8d 4a 08 lea 0x8(%rdx),%rcx + 40fe97: 48 8d 72 58 lea 0x58(%rdx),%rsi + 40fe9b: 51 push %rcx + 40fe9c: ff 72 38 pushq 0x38(%rdx) + 40fe9f: 48 89 c1 mov %rax,%rcx + 40fea2: 4c 8b 4a 08 mov 0x8(%rdx),%r9 + 40fea6: 4c 89 ea mov %r13,%rdx + 40fea9: 4c 8d 44 24 18 lea 0x18(%rsp),%r8 + 40feae: 41 ff 54 24 18 callq *0x18(%r12) + 40feb3: 48 85 ed test %rbp,%rbp + 40feb6: 5e pop %rsi + 40feb7: 5f pop %rdi + 40feb8: 0f 84 93 fe ff ff je 40fd51 <_IO_wfile_underflow+0x1f1> + 40febe: 48 8b 4c 24 08 mov 0x8(%rsp),%rcx + 40fec3: be 00 00 00 00 mov $0x0,%esi + 40fec8: 48 89 ca mov %rcx,%rdx + 40fecb: 4c 29 f2 sub %r14,%rdx + 40fece: 48 0f 48 d6 cmovs %rsi,%rdx + 40fed2: 48 89 d6 mov %rdx,%rsi + 40fed5: 48 03 73 08 add 0x8(%rbx),%rsi + 40fed9: e9 7d fe ff ff jmpq 40fd5b <_IO_wfile_underflow+0x1fb> + 40fede: 66 90 xchg %ax,%ax + 40fee0: 8b 02 mov (%rdx),%eax + 40fee2: c3 retq + 40fee3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 40fee8: 83 f8 02 cmp $0x2,%eax + 40feeb: 0f 85 88 01 00 00 jne 410079 <_IO_wfile_underflow+0x519> + 40fef1: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 40fef8: 64 c7 00 54 00 00 00 movl $0x54,%fs:(%rax) + 40feff: 83 0b 20 orl $0x20,(%rbx) + 40ff02: 48 83 c4 28 add $0x28,%rsp + 40ff06: 5b pop %rbx + 40ff07: b8 ff ff ff ff mov $0xffffffff,%eax + 40ff0c: 5d pop %rbp + 40ff0d: 41 5c pop %r12 + 40ff0f: 41 5d pop %r13 + 40ff11: 41 5e pop %r14 + 40ff13: 41 5f pop %r15 + 40ff15: c3 retq + 40ff16: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 40ff1d: 00 00 00 + 40ff20: 48 89 54 24 10 mov %rdx,0x10(%rsp) + 40ff25: 48 8b 50 58 mov 0x58(%rax),%rdx + 40ff29: 48 89 50 60 mov %rdx,0x60(%rax) + 40ff2d: 48 8b 87 a0 00 00 00 mov 0xa0(%rdi),%rax + 40ff34: 48 8b 4f 10 mov 0x10(%rdi),%rcx + 40ff38: 48 8b 57 08 mov 0x8(%rdi),%rdx + 40ff3c: 4c 8b 48 30 mov 0x30(%rax),%r9 + 40ff40: 48 8d 78 08 lea 0x8(%rax),%rdi + 40ff44: 48 8d 70 58 lea 0x58(%rax),%rsi + 40ff48: 4c 89 08 mov %r9,(%rax) + 40ff4b: 4c 89 48 10 mov %r9,0x10(%rax) + 40ff4f: 57 push %rdi + 40ff50: ff 70 38 pushq 0x38(%rax) + 40ff53: 4c 89 e7 mov %r12,%rdi + 40ff56: 4c 8d 44 24 20 lea 0x20(%rsp),%r8 + 40ff5b: 41 ff 54 24 18 callq *0x18(%r12) + 40ff60: 48 8b 53 08 mov 0x8(%rbx),%rdx + 40ff64: 48 8b 74 24 20 mov 0x20(%rsp),%rsi + 40ff69: 48 89 53 18 mov %rdx,0x18(%rbx) + 40ff6d: 48 8b 93 a0 00 00 00 mov 0xa0(%rbx),%rdx + 40ff74: 48 89 73 08 mov %rsi,0x8(%rbx) + 40ff78: 41 58 pop %r8 + 40ff7a: 48 8b 0a mov (%rdx),%rcx + 40ff7d: 48 3b 4a 08 cmp 0x8(%rdx),%rcx + 40ff81: 41 59 pop %r9 + 40ff83: 0f 83 5f ff ff ff jae 40fee8 <_IO_wfile_underflow+0x388> + 40ff89: 8b 01 mov (%rcx),%eax + 40ff8b: e9 76 fe ff ff jmpq 40fe06 <_IO_wfile_underflow+0x2a6> + 40ff90: 81 e2 88 02 00 00 and $0x288,%edx + 40ff96: 81 fa 80 02 00 00 cmp $0x280,%edx + 40ff9c: 0f 85 ee fc ff ff jne 40fc90 <_IO_wfile_underflow+0x130> + 40ffa2: 48 89 ef mov %rbp,%rdi + 40ffa5: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax + 40ffac: be ff ff ff ff mov $0xffffffff,%esi + 40ffb1: ff 50 18 callq *0x18(%rax) + 40ffb4: e9 bd fc ff ff jmpq 40fc76 <_IO_wfile_underflow+0x116> + 40ffb9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 40ffc0: 83 0b 20 orl $0x20,(%rbx) + 40ffc3: 48 85 ed test %rbp,%rbp + 40ffc6: 0f 84 84 01 00 00 je 410150 <_IO_wfile_underflow+0x5f0> + 40ffcc: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 40ffd3: 64 c7 00 54 00 00 00 movl $0x54,%fs:(%rax) + 40ffda: b8 ff ff ff ff mov $0xffffffff,%eax + 40ffdf: e9 22 fe ff ff jmpq 40fe06 <_IO_wfile_underflow+0x2a6> + 40ffe4: 0f 1f 40 00 nopl 0x0(%rax) + 40ffe8: 48 8b 02 mov (%rdx),%rax + 40ffeb: 8b 00 mov (%rax),%eax + 40ffed: 48 83 c4 28 add $0x28,%rsp + 40fff1: 5b pop %rbx + 40fff2: 5d pop %rbp + 40fff3: 41 5c pop %r12 + 40fff5: 41 5d pop %r13 + 40fff7: 41 5e pop %r14 + 40fff9: 41 5f pop %r15 + 40fffb: c3 retq + 40fffc: 0f 1f 40 00 nopl 0x0(%rax) + 410000: 83 c8 20 or $0x20,%eax + 410003: 89 07 mov %eax,(%rdi) + 410005: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 41000c: 64 c7 00 09 00 00 00 movl $0x9,%fs:(%rax) + 410013: b8 ff ff ff ff mov $0xffffffff,%eax + 410018: c3 retq + 410019: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 410020: 48 8b 78 40 mov 0x40(%rax),%rdi + 410024: 48 85 ff test %rdi,%rdi + 410027: 74 0b je 410034 <_IO_wfile_underflow+0x4d4> + 410029: e8 82 dd 00 00 callq 41ddb0 <__cfree> + 41002e: 81 23 ff fe ff ff andl $0xfffffeff,(%rbx) + 410034: 48 89 df mov %rbx,%rdi + 410037: e8 64 46 05 00 callq 4646a0 <_IO_wdoallocbuf> + 41003c: e9 9a fb ff ff jmpq 40fbdb <_IO_wfile_underflow+0x7b> + 410041: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 410048: 48 8b 7b 48 mov 0x48(%rbx),%rdi + 41004c: 48 85 ff test %rdi,%rdi + 41004f: 74 0b je 41005c <_IO_wfile_underflow+0x4fc> + 410051: e8 5a dd 00 00 callq 41ddb0 <__cfree> + 410056: 81 23 ff fe ff ff andl $0xfffffeff,(%rbx) + 41005c: 48 89 df mov %rbx,%rdi + 41005f: e8 9c 4d 00 00 callq 414e00 <_IO_doallocbuf> + 410064: 48 8b 43 38 mov 0x38(%rbx),%rax + 410068: 48 89 43 10 mov %rax,0x10(%rbx) + 41006c: 48 89 43 08 mov %rax,0x8(%rbx) + 410070: 48 89 43 18 mov %rax,0x18(%rbx) + 410074: e9 44 fb ff ff jmpq 40fbbd <_IO_wfile_underflow+0x5d> + 410079: 48 8b 53 10 mov 0x10(%rbx),%rdx + 41007d: 48 8b 7b 38 mov 0x38(%rbx),%rdi + 410081: 48 29 f2 sub %rsi,%rdx + 410084: e8 77 02 ff ff callq 400300 <__rela_iplt_end+0x38> + 410089: 48 8b 43 38 mov 0x38(%rbx),%rax + 41008d: 48 89 c2 mov %rax,%rdx + 410090: 48 2b 53 08 sub 0x8(%rbx),%rdx + 410094: 48 89 43 18 mov %rax,0x18(%rbx) + 410098: 48 01 53 10 add %rdx,0x10(%rbx) + 41009c: 48 89 43 08 mov %rax,0x8(%rbx) + 4100a0: e9 0f fb ff ff jmpq 40fbb4 <_IO_wfile_underflow+0x54> + 4100a5: 48 c7 42 08 00 00 00 movq $0x0,0x8(%rdx) + 4100ac: 00 + 4100ad: 83 3d 08 d1 2b 00 00 cmpl $0x0,0x2bd108(%rip) # 6cd1bc <__libc_multiple_threads> + 4100b4: 74 07 je 4100bd <_IO_wfile_underflow+0x55d> + 4100b6: f0 ff 0a lock decl (%rdx) + 4100b9: 75 06 jne 4100c1 <_IO_wfile_underflow+0x561> + 4100bb: eb 1a jmp 4100d7 <_IO_wfile_underflow+0x577> + 4100bd: ff 0a decl (%rdx) + 4100bf: 74 16 je 4100d7 <_IO_wfile_underflow+0x577> + 4100c1: 48 8d 3a lea (%rdx),%rdi + 4100c4: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 4100cb: e8 30 25 03 00 callq 442600 <__lll_unlock_wake_private> + 4100d0: 48 81 c4 80 00 00 00 add $0x80,%rsp + 4100d7: e9 b4 fb ff ff jmpq 40fc90 <_IO_wfile_underflow+0x130> + 4100dc: 48 89 ef mov %rbp,%rdi + 4100df: e9 7b fb ff ff jmpq 40fc5f <_IO_wfile_underflow+0xff> + 4100e4: b9 80 19 4a 00 mov $0x4a1980,%ecx + 4100e9: ba 35 01 00 00 mov $0x135,%edx + 4100ee: be 53 19 4a 00 mov $0x4a1953,%esi + 4100f3: bf 5e 19 4a 00 mov $0x4a195e,%edi + 4100f8: e8 43 16 ff ff callq 401740 <__assert_fail> + 4100fd: f7 45 00 00 80 00 00 testl $0x8000,0x0(%rbp) + 410104: 48 89 c6 mov %rax,%rsi + 410107: 75 3f jne 410148 <_IO_wfile_underflow+0x5e8> + 410109: 48 8b 95 88 00 00 00 mov 0x88(%rbp),%rdx + 410110: 83 6a 04 01 subl $0x1,0x4(%rdx) + 410114: 75 32 jne 410148 <_IO_wfile_underflow+0x5e8> + 410116: 48 c7 42 08 00 00 00 movq $0x0,0x8(%rdx) + 41011d: 00 + 41011e: 83 3d 97 d0 2b 00 00 cmpl $0x0,0x2bd097(%rip) # 6cd1bc <__libc_multiple_threads> + 410125: 74 07 je 41012e <_IO_wfile_underflow+0x5ce> + 410127: f0 ff 0a lock decl (%rdx) + 41012a: 75 06 jne 410132 <_IO_wfile_underflow+0x5d2> + 41012c: eb 1a jmp 410148 <_IO_wfile_underflow+0x5e8> + 41012e: ff 0a decl (%rdx) + 410130: 74 16 je 410148 <_IO_wfile_underflow+0x5e8> + 410132: 48 8d 3a lea (%rdx),%rdi + 410135: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41013c: e8 bf 24 03 00 callq 442600 <__lll_unlock_wake_private> + 410141: 48 81 c4 80 00 00 00 add $0x80,%rsp + 410148: 48 89 f7 mov %rsi,%rdi + 41014b: e8 20 c4 08 00 callq 49c570 <_Unwind_Resume> + 410150: 83 c8 ff or $0xffffffff,%eax + 410153: e9 ae fc ff ff jmpq 40fe06 <_IO_wfile_underflow+0x2a6> + 410158: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 41015f: 00 + +0000000000410160 <_IO_wfile_seekoff>: + 410160: 41 57 push %r15 + 410162: 41 56 push %r14 + 410164: 49 89 ff mov %rdi,%r15 + 410167: 41 55 push %r13 + 410169: 41 54 push %r12 + 41016b: 55 push %rbp + 41016c: 53 push %rbx + 41016d: 48 81 ec b8 00 00 00 sub $0xb8,%rsp + 410174: 85 c9 test %ecx,%ecx + 410176: 0f 84 a4 02 00 00 je 410420 <_IO_wfile_seekoff+0x2c0> + 41017c: 48 8b 87 a0 00 00 00 mov 0xa0(%rdi),%rax + 410183: 48 89 f3 mov %rsi,%rbx + 410186: 89 d5 mov %edx,%ebp + 410188: 48 8b 70 08 mov 0x8(%rax),%rsi + 41018c: 48 39 70 10 cmp %rsi,0x10(%rax) + 410190: 74 3e je 4101d0 <_IO_wfile_seekoff+0x70> + 410192: 48 8b 48 20 mov 0x20(%rax),%rcx + 410196: 48 8b 50 18 mov 0x18(%rax),%rdx + 41019a: 45 31 e4 xor %r12d,%r12d + 41019d: 48 39 d1 cmp %rdx,%rcx + 4101a0: 76 46 jbe 4101e8 <_IO_wfile_seekoff+0x88> + 4101a2: 4c 89 ff mov %r15,%rdi + 4101a5: e8 f6 45 05 00 callq 4647a0 <_IO_switch_to_wget_mode> + 4101aa: 85 c0 test %eax,%eax + 4101ac: ba ff ff ff ff mov $0xffffffff,%edx + 4101b1: 0f 84 41 03 00 00 je 4104f8 <_IO_wfile_seekoff+0x398> + 4101b7: 48 81 c4 b8 00 00 00 add $0xb8,%rsp + 4101be: 48 89 d0 mov %rdx,%rax + 4101c1: 5b pop %rbx + 4101c2: 5d pop %rbp + 4101c3: 41 5c pop %r12 + 4101c5: 41 5d pop %r13 + 4101c7: 41 5e pop %r14 + 4101c9: 41 5f pop %r15 + 4101cb: c3 retq + 4101cc: 0f 1f 40 00 nopl 0x0(%rax) + 4101d0: 48 8b 50 18 mov 0x18(%rax),%rdx + 4101d4: 48 8b 48 20 mov 0x20(%rax),%rcx + 4101d8: 48 39 ca cmp %rcx,%rdx + 4101db: 75 bd jne 41019a <_IO_wfile_seekoff+0x3a> + 4101dd: 41 bc 01 00 00 00 mov $0x1,%r12d + 4101e3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4101e8: 41 f7 07 00 08 00 00 testl $0x800,(%r15) + 4101ef: 75 b1 jne 4101a2 <_IO_wfile_seekoff+0x42> + 4101f1: 48 83 78 30 00 cmpq $0x0,0x30(%rax) + 4101f6: 0f 84 b4 03 00 00 je 4105b0 <_IO_wfile_seekoff+0x450> + 4101fc: 83 fd 01 cmp $0x1,%ebp + 4101ff: 0f 84 bb 01 00 00 je 4103c0 <_IO_wfile_seekoff+0x260> + 410205: 83 fd 02 cmp $0x2,%ebp + 410208: 0f 85 c2 00 00 00 jne 4102d0 <_IO_wfile_seekoff+0x170> + 41020e: 49 8b 87 d8 00 00 00 mov 0xd8(%r15),%rax + 410215: 48 8d 74 24 20 lea 0x20(%rsp),%rsi + 41021a: 4c 89 ff mov %r15,%rdi + 41021d: ff 90 90 00 00 00 callq *0x90(%rax) + 410223: 85 c0 test %eax,%eax + 410225: 0f 84 85 00 00 00 je 4102b0 <_IO_wfile_seekoff+0x150> + 41022b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 410230: 4c 89 ff mov %r15,%rdi + 410233: e8 68 61 00 00 callq 4163a0 <_IO_unsave_markers> + 410238: 49 8b 87 d8 00 00 00 mov 0xd8(%r15),%rax + 41023f: 89 ea mov %ebp,%edx + 410241: 48 89 de mov %rbx,%rsi + 410244: 4c 89 ff mov %r15,%rdi + 410247: ff 90 80 00 00 00 callq *0x80(%rax) + 41024d: 48 c7 c2 ff ff ff ff mov $0xffffffffffffffff,%rdx + 410254: 48 39 d0 cmp %rdx,%rax + 410257: 0f 84 5a ff ff ff je 4101b7 <_IO_wfile_seekoff+0x57> + 41025d: 49 8b 57 38 mov 0x38(%r15),%rdx + 410261: 41 83 27 ef andl $0xffffffef,(%r15) + 410265: 49 89 87 90 00 00 00 mov %rax,0x90(%r15) + 41026c: 49 89 57 18 mov %rdx,0x18(%r15) + 410270: 49 89 57 08 mov %rdx,0x8(%r15) + 410274: 49 89 57 10 mov %rdx,0x10(%r15) + 410278: 49 89 57 28 mov %rdx,0x28(%r15) + 41027c: 49 89 57 20 mov %rdx,0x20(%r15) + 410280: 49 89 57 30 mov %rdx,0x30(%r15) + 410284: 49 8b 97 a0 00 00 00 mov 0xa0(%r15),%rdx + 41028b: 48 8b 4a 30 mov 0x30(%rdx),%rcx + 41028f: 48 89 4a 10 mov %rcx,0x10(%rdx) + 410293: 48 89 0a mov %rcx,(%rdx) + 410296: 48 89 4a 08 mov %rcx,0x8(%rdx) + 41029a: 48 89 4a 20 mov %rcx,0x20(%rdx) + 41029e: 48 89 4a 18 mov %rcx,0x18(%rdx) + 4102a2: 48 89 4a 28 mov %rcx,0x28(%rdx) + 4102a6: 48 89 c2 mov %rax,%rdx + 4102a9: e9 09 ff ff ff jmpq 4101b7 <_IO_wfile_seekoff+0x57> + 4102ae: 66 90 xchg %ax,%ax + 4102b0: 8b 44 24 38 mov 0x38(%rsp),%eax + 4102b4: 25 00 f0 00 00 and $0xf000,%eax + 4102b9: 3d 00 80 00 00 cmp $0x8000,%eax + 4102be: 0f 85 6c ff ff ff jne 410230 <_IO_wfile_seekoff+0xd0> + 4102c4: 48 03 5c 24 50 add 0x50(%rsp),%rbx + 4102c9: 31 ed xor %ebp,%ebp + 4102cb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4102d0: 49 8b 87 90 00 00 00 mov 0x90(%r15),%rax + 4102d7: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 4102db: 0f 84 27 02 00 00 je 410508 <_IO_wfile_seekoff+0x3a8> + 4102e1: 49 83 7f 18 00 cmpq $0x0,0x18(%r15) + 4102e6: 41 8b 17 mov (%r15),%edx + 4102e9: 74 25 je 410310 <_IO_wfile_seekoff+0x1b0> + 4102eb: f6 c6 01 test $0x1,%dh + 4102ee: 75 20 jne 410310 <_IO_wfile_seekoff+0x1b0> + 4102f0: 49 8b 4f 38 mov 0x38(%r15),%rcx + 4102f4: 48 89 ce mov %rcx,%rsi + 4102f7: 49 2b 77 10 sub 0x10(%r15),%rsi + 4102fb: 48 01 c6 add %rax,%rsi + 4102fe: 48 39 de cmp %rbx,%rsi + 410301: 7f 0d jg 410310 <_IO_wfile_seekoff+0x1b0> + 410303: 48 39 c3 cmp %rax,%rbx + 410306: 0f 8c ac 03 00 00 jl 4106b8 <_IO_wfile_seekoff+0x558> + 41030c: 0f 1f 40 00 nopl 0x0(%rax) + 410310: 83 e2 04 and $0x4,%edx + 410313: 0f 85 17 ff ff ff jne 410230 <_IO_wfile_seekoff+0xd0> + 410319: 49 8b 57 38 mov 0x38(%r15),%rdx + 41031d: 49 8b 47 40 mov 0x40(%r15),%rax + 410321: 49 89 dd mov %rbx,%r13 + 410324: 48 89 d6 mov %rdx,%rsi + 410327: 48 29 c6 sub %rax,%rsi + 41032a: 48 29 d0 sub %rdx,%rax + 41032d: ba 00 00 00 00 mov $0x0,%edx + 410332: 48 21 de and %rbx,%rsi + 410335: 49 29 f5 sub %rsi,%r13 + 410338: 49 39 c5 cmp %rax,%r13 + 41033b: 49 8b 87 d8 00 00 00 mov 0xd8(%r15),%rax + 410342: 0f 8f d8 01 00 00 jg 410520 <_IO_wfile_seekoff+0x3c0> + 410348: 4c 89 ff mov %r15,%rdi + 41034b: ff 90 80 00 00 00 callq *0x80(%rax) + 410351: 48 85 c0 test %rax,%rax + 410354: 49 89 c6 mov %rax,%r14 + 410357: 0f 88 8b 01 00 00 js 4104e8 <_IO_wfile_seekoff+0x388> + 41035d: 4d 85 ed test %r13,%r13 + 410360: 0f 84 ce 01 00 00 je 410534 <_IO_wfile_seekoff+0x3d4> + 410366: 49 8b 87 d8 00 00 00 mov 0xd8(%r15),%rax + 41036d: 45 85 e4 test %r12d,%r12d + 410370: 49 8b 77 38 mov 0x38(%r15),%rsi + 410374: 4c 89 ea mov %r13,%rdx + 410377: 48 8b 40 70 mov 0x70(%rax),%rax + 41037b: 75 07 jne 410384 <_IO_wfile_seekoff+0x224> + 41037d: 49 8b 57 40 mov 0x40(%r15),%rdx + 410381: 48 29 f2 sub %rsi,%rdx + 410384: 4c 89 ff mov %r15,%rdi + 410387: ff d0 callq *%rax + 410389: 49 39 c5 cmp %rax,%r13 + 41038c: 49 89 c4 mov %rax,%r12 + 41038f: 48 89 c2 mov %rax,%rdx + 410392: 0f 8e a4 01 00 00 jle 41053c <_IO_wfile_seekoff+0x3dc> + 410398: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 41039c: 4c 89 eb mov %r13,%rbx + 41039f: bd 01 00 00 00 mov $0x1,%ebp + 4103a4: 0f 84 86 fe ff ff je 410230 <_IO_wfile_seekoff+0xd0> + 4103aa: 48 29 c3 sub %rax,%rbx + 4103ad: bd 01 00 00 00 mov $0x1,%ebp + 4103b2: e9 79 fe ff ff jmpq 410230 <_IO_wfile_seekoff+0xd0> + 4103b7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 4103be: 00 00 + 4103c0: 4d 8b af 98 00 00 00 mov 0x98(%r15),%r13 + 4103c7: 4c 89 ef mov %r13,%rdi + 4103ca: 41 ff 55 20 callq *0x20(%r13) + 4103ce: 85 c0 test %eax,%eax + 4103d0: 0f 8e 6a 03 00 00 jle 410740 <_IO_wfile_seekoff+0x5e0> + 4103d6: 49 8b 8f a0 00 00 00 mov 0xa0(%r15),%rcx + 4103dd: 48 98 cltq + 4103df: 48 8b 51 08 mov 0x8(%rcx),%rdx + 4103e3: 48 2b 11 sub (%rcx),%rdx + 4103e6: 48 c1 fa 02 sar $0x2,%rdx + 4103ea: 48 0f af c2 imul %rdx,%rax + 4103ee: 48 29 c3 sub %rax,%rbx + 4103f1: 49 8b 47 10 mov 0x10(%r15),%rax + 4103f5: 49 2b 47 08 sub 0x8(%r15),%rax + 4103f9: 48 29 c3 sub %rax,%rbx + 4103fc: 49 8b 87 90 00 00 00 mov 0x90(%r15),%rax + 410403: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 410407: 0f 84 23 fe ff ff je 410230 <_IO_wfile_seekoff+0xd0> + 41040d: 48 01 c3 add %rax,%rbx + 410410: 31 ed xor %ebp,%ebp + 410412: e9 ca fe ff ff jmpq 4102e1 <_IO_wfile_seekoff+0x181> + 410417: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 41041e: 00 00 + 410420: 48 8b 87 a0 00 00 00 mov 0xa0(%rdi),%rax + 410427: 48 83 78 30 00 cmpq $0x0,0x30(%rax) + 41042c: 0f 84 06 03 00 00 je 410738 <_IO_wfile_seekoff+0x5d8> + 410432: 8b 17 mov (%rdi),%edx + 410434: 4c 8b 60 20 mov 0x20(%rax),%r12 + 410438: 48 8b 68 18 mov 0x18(%rax),%rbp + 41043c: 41 89 d5 mov %edx,%r13d + 41043f: 41 81 e5 00 10 00 00 and $0x1000,%r13d + 410446: 49 39 ec cmp %rbp,%r12 + 410449: 76 09 jbe 410454 <_IO_wfile_seekoff+0x2f4> + 41044b: 45 85 ed test %r13d,%r13d + 41044e: 0f 85 1c 02 00 00 jne 410670 <_IO_wfile_seekoff+0x510> + 410454: 80 e6 01 and $0x1,%dh + 410457: 0f 84 b3 01 00 00 je 410610 <_IO_wfile_seekoff+0x4b0> + 41045d: 48 8b 78 08 mov 0x8(%rax),%rdi + 410461: 48 39 38 cmp %rdi,(%rax) + 410464: 72 6e jb 4104d4 <_IO_wfile_seekoff+0x374> + 410466: 4c 8b 70 40 mov 0x40(%rax),%r14 + 41046a: 48 8b 40 50 mov 0x50(%rax),%rax + 41046e: 4c 89 74 24 08 mov %r14,0x8(%rsp) + 410473: 48 89 04 24 mov %rax,(%rsp) + 410477: 49 8b 9f 98 00 00 00 mov 0x98(%r15),%rbx + 41047e: 48 89 df mov %rbx,%rdi + 410481: ff 53 20 callq *0x20(%rbx) + 410484: 49 39 ec cmp %rbp,%r12 + 410487: 0f 87 a3 01 00 00 ja 410630 <_IO_wfile_seekoff+0x4d0> + 41048d: 85 c0 test %eax,%eax + 41048f: 0f 8e 3b 03 00 00 jle 4107d0 <_IO_wfile_seekoff+0x670> + 410495: 48 8b 14 24 mov (%rsp),%rdx + 410499: 48 98 cltq + 41049b: 4c 29 f2 sub %r14,%rdx + 41049e: 48 c1 fa 02 sar $0x2,%rdx + 4104a2: 48 0f af d0 imul %rax,%rdx + 4104a6: 49 8b 47 10 mov 0x10(%r15),%rax + 4104aa: 49 2b 47 08 sub 0x8(%r15),%rax + 4104ae: 48 f7 da neg %rdx + 4104b1: 48 89 d3 mov %rdx,%rbx + 4104b4: 48 29 c3 sub %rax,%rbx + 4104b7: 49 8b 87 90 00 00 00 mov 0x90(%r15),%rax + 4104be: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 4104c2: 0f 84 e0 02 00 00 je 4107a8 <_IO_wfile_seekoff+0x648> + 4104c8: 48 01 c3 add %rax,%rbx + 4104cb: 48 89 da mov %rbx,%rdx + 4104ce: 0f 89 e3 fc ff ff jns 4101b7 <_IO_wfile_seekoff+0x57> + 4104d4: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 4104db: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) + 4104e2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4104e8: 48 c7 c2 ff ff ff ff mov $0xffffffffffffffff,%rdx + 4104ef: e9 c3 fc ff ff jmpq 4101b7 <_IO_wfile_seekoff+0x57> + 4104f4: 0f 1f 40 00 nopl 0x0(%rax) + 4104f8: 49 8b 87 a0 00 00 00 mov 0xa0(%r15),%rax + 4104ff: e9 ed fc ff ff jmpq 4101f1 <_IO_wfile_seekoff+0x91> + 410504: 0f 1f 40 00 nopl 0x0(%rax) + 410508: 41 8b 17 mov (%r15),%edx + 41050b: 83 e2 04 and $0x4,%edx + 41050e: 0f 85 1c fd ff ff jne 410230 <_IO_wfile_seekoff+0xd0> + 410514: e9 00 fe ff ff jmpq 410319 <_IO_wfile_seekoff+0x1b9> + 410519: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 410520: 48 89 de mov %rbx,%rsi + 410523: 4c 89 ff mov %r15,%rdi + 410526: ff 90 80 00 00 00 callq *0x80(%rax) + 41052c: 48 85 c0 test %rax,%rax + 41052f: 49 89 c6 mov %rax,%r14 + 410532: 78 b4 js 4104e8 <_IO_wfile_seekoff+0x388> + 410534: 31 d2 xor %edx,%edx + 410536: 45 31 ed xor %r13d,%r13d + 410539: 45 31 e4 xor %r12d,%r12d + 41053c: 49 8b 47 38 mov 0x38(%r15),%rax + 410540: be 01 00 00 00 mov $0x1,%esi + 410545: 4c 89 ff mov %r15,%rdi + 410548: 49 89 47 18 mov %rax,0x18(%r15) + 41054c: 49 89 47 28 mov %rax,0x28(%r15) + 410550: 48 01 c2 add %rax,%rdx + 410553: 49 89 47 20 mov %rax,0x20(%r15) + 410557: 49 89 47 30 mov %rax,0x30(%r15) + 41055b: 49 01 c5 add %rax,%r13 + 41055e: 49 8b 87 a0 00 00 00 mov 0xa0(%r15),%rax + 410565: 49 89 57 10 mov %rdx,0x10(%r15) + 410569: 4d 89 6f 08 mov %r13,0x8(%r15) + 41056d: 48 8b 50 30 mov 0x30(%rax),%rdx + 410571: 48 89 50 10 mov %rdx,0x10(%rax) + 410575: 48 89 10 mov %rdx,(%rax) + 410578: 48 89 50 08 mov %rdx,0x8(%rax) + 41057c: 48 89 50 20 mov %rdx,0x20(%rax) + 410580: 48 89 50 18 mov %rdx,0x18(%rax) + 410584: 48 89 50 28 mov %rdx,0x28(%rax) + 410588: e8 03 f5 ff ff callq 40fa90 + 41058d: 85 c0 test %eax,%eax + 41058f: 0f 85 9b fc ff ff jne 410230 <_IO_wfile_seekoff+0xd0> + 410595: 4d 01 e6 add %r12,%r14 + 410598: 41 83 27 ef andl $0xffffffef,(%r15) + 41059c: 48 89 da mov %rbx,%rdx + 41059f: 4d 89 b7 90 00 00 00 mov %r14,0x90(%r15) + 4105a6: e9 0c fc ff ff jmpq 4101b7 <_IO_wfile_seekoff+0x57> + 4105ab: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4105b0: 48 8b 78 10 mov 0x10(%rax),%rdi + 4105b4: 48 85 ff test %rdi,%rdi + 4105b7: 74 0c je 4105c5 <_IO_wfile_seekoff+0x465> + 4105b9: e8 f2 d7 00 00 callq 41ddb0 <__cfree> + 4105be: 41 81 27 ff fe ff ff andl $0xfffffeff,(%r15) + 4105c5: 4c 89 ff mov %r15,%rdi + 4105c8: e8 33 48 00 00 callq 414e00 <_IO_doallocbuf> + 4105cd: 49 8b 47 38 mov 0x38(%r15),%rax + 4105d1: 49 89 47 28 mov %rax,0x28(%r15) + 4105d5: 49 89 47 20 mov %rax,0x20(%r15) + 4105d9: 49 89 47 30 mov %rax,0x30(%r15) + 4105dd: 49 89 47 18 mov %rax,0x18(%r15) + 4105e1: 49 89 47 08 mov %rax,0x8(%r15) + 4105e5: 49 89 47 10 mov %rax,0x10(%r15) + 4105e9: 49 8b 87 a0 00 00 00 mov 0xa0(%r15),%rax + 4105f0: 48 8b 50 30 mov 0x30(%rax),%rdx + 4105f4: 48 89 50 20 mov %rdx,0x20(%rax) + 4105f8: 48 89 50 18 mov %rdx,0x18(%rax) + 4105fc: 48 89 50 28 mov %rdx,0x28(%rax) + 410600: 48 89 50 10 mov %rdx,0x10(%rax) + 410604: 48 89 10 mov %rdx,(%rax) + 410607: 48 89 50 08 mov %rdx,0x8(%rax) + 41060b: e9 ec fb ff ff jmpq 4101fc <_IO_wfile_seekoff+0x9c> + 410610: 48 8b 78 10 mov 0x10(%rax),%rdi + 410614: 4c 8b 30 mov (%rax),%r14 + 410617: 48 8b 40 08 mov 0x8(%rax),%rax + 41061b: 48 89 7c 24 08 mov %rdi,0x8(%rsp) + 410620: 48 89 04 24 mov %rax,(%rsp) + 410624: e9 4e fe ff ff jmpq 410477 <_IO_wfile_seekoff+0x317> + 410629: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 410630: 85 c0 test %eax,%eax + 410632: 0f 8e e0 01 00 00 jle 410818 <_IO_wfile_seekoff+0x6b8> + 410638: 49 8b 97 a0 00 00 00 mov 0xa0(%r15),%rdx + 41063f: 48 98 cltq + 410641: 48 8b 5a 20 mov 0x20(%rdx),%rbx + 410645: 48 2b 5a 18 sub 0x18(%rdx),%rbx + 410649: 48 c1 fb 02 sar $0x2,%rbx + 41064d: 48 0f af d8 imul %rax,%rbx + 410651: 48 89 dd mov %rbx,%rbp + 410654: 45 85 ed test %r13d,%r13d + 410657: 49 8b 57 28 mov 0x28(%r15),%rdx + 41065b: 74 4b je 4106a8 <_IO_wfile_seekoff+0x548> + 41065d: 49 2b 57 20 sub 0x20(%r15),%rdx + 410661: 48 8d 1c 2a lea (%rdx,%rbp,1),%rbx + 410665: e9 4d fe ff ff jmpq 4104b7 <_IO_wfile_seekoff+0x357> + 41066a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 410670: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax + 410677: 31 f6 xor %esi,%esi + 410679: ba 02 00 00 00 mov $0x2,%edx + 41067e: ff 90 80 00 00 00 callq *0x80(%rax) + 410684: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 410688: 0f 84 5a fe ff ff je 4104e8 <_IO_wfile_seekoff+0x388> + 41068e: 49 89 87 90 00 00 00 mov %rax,0x90(%r15) + 410695: 41 8b 17 mov (%r15),%edx + 410698: 49 8b 87 a0 00 00 00 mov 0xa0(%r15),%rax + 41069f: e9 b0 fd ff ff jmpq 410454 <_IO_wfile_seekoff+0x2f4> + 4106a4: 0f 1f 40 00 nopl 0x0(%rax) + 4106a8: 49 2b 57 10 sub 0x10(%r15),%rdx + 4106ac: 48 8d 1c 2a lea (%rdx,%rbp,1),%rbx + 4106b0: e9 02 fe ff ff jmpq 4104b7 <_IO_wfile_seekoff+0x357> + 4106b5: 0f 1f 00 nopl (%rax) + 4106b8: 48 89 d8 mov %rbx,%rax + 4106bb: 49 89 4f 18 mov %rcx,0x18(%r15) + 4106bf: 49 89 4f 28 mov %rcx,0x28(%r15) + 4106c3: 48 29 f0 sub %rsi,%rax + 4106c6: 49 89 4f 20 mov %rcx,0x20(%r15) + 4106ca: 49 89 4f 30 mov %rcx,0x30(%r15) + 4106ce: 48 01 c8 add %rcx,%rax + 4106d1: 31 f6 xor %esi,%esi + 4106d3: 4c 89 ff mov %r15,%rdi + 4106d6: 49 89 47 08 mov %rax,0x8(%r15) + 4106da: 49 8b 87 a0 00 00 00 mov 0xa0(%r15),%rax + 4106e1: 48 8b 50 30 mov 0x30(%rax),%rdx + 4106e5: 48 89 50 10 mov %rdx,0x10(%rax) + 4106e9: 48 89 10 mov %rdx,(%rax) + 4106ec: 48 89 50 08 mov %rdx,0x8(%rax) + 4106f0: 48 89 50 20 mov %rdx,0x20(%rax) + 4106f4: 48 89 50 18 mov %rdx,0x18(%rax) + 4106f8: 48 89 50 28 mov %rdx,0x28(%rax) + 4106fc: e8 8f f3 ff ff callq 40fa90 + 410701: 85 c0 test %eax,%eax + 410703: 0f 85 27 fb ff ff jne 410230 <_IO_wfile_seekoff+0xd0> + 410709: 49 8b b7 90 00 00 00 mov 0x90(%r15),%rsi + 410710: 41 83 27 ef andl $0xffffffef,(%r15) + 410714: 48 85 f6 test %rsi,%rsi + 410717: 78 12 js 41072b <_IO_wfile_seekoff+0x5cb> + 410719: 49 8b 87 d8 00 00 00 mov 0xd8(%r15),%rax + 410720: 31 d2 xor %edx,%edx + 410722: 4c 89 ff mov %r15,%rdi + 410725: ff 90 80 00 00 00 callq *0x80(%rax) + 41072b: 48 89 da mov %rbx,%rdx + 41072e: e9 84 fa ff ff jmpq 4101b7 <_IO_wfile_seekoff+0x57> + 410733: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 410738: 31 db xor %ebx,%ebx + 41073a: e9 78 fd ff ff jmpq 4104b7 <_IO_wfile_seekoff+0x357> + 41073f: 90 nop + 410740: 49 8b 87 a0 00 00 00 mov 0xa0(%r15),%rax + 410747: 4c 89 ef mov %r13,%rdi + 41074a: 48 8b 50 60 mov 0x60(%rax),%rdx + 41074e: 4c 8b 00 mov (%rax),%r8 + 410751: 4c 2b 40 10 sub 0x10(%rax),%r8 + 410755: 48 89 50 58 mov %rdx,0x58(%rax) + 410759: 49 8b 87 a0 00 00 00 mov 0xa0(%r15),%rax + 410760: 49 8b 4f 10 mov 0x10(%r15),%rcx + 410764: 49 8b 57 18 mov 0x18(%r15),%rdx + 410768: 49 c1 f8 02 sar $0x2,%r8 + 41076c: 48 8d 70 58 lea 0x58(%rax),%rsi + 410770: 41 ff 55 30 callq *0x30(%r13) + 410774: 49 8b 4f 18 mov 0x18(%r15),%rcx + 410778: 48 63 d0 movslq %eax,%rdx + 41077b: 48 8d 04 11 lea (%rcx,%rdx,1),%rax + 41077f: 49 89 47 08 mov %rax,0x8(%r15) + 410783: 49 8b 87 a0 00 00 00 mov 0xa0(%r15),%rax + 41078a: 48 8b 30 mov (%rax),%rsi + 41078d: 48 89 70 08 mov %rsi,0x8(%rax) + 410791: 49 8b 47 10 mov 0x10(%r15),%rax + 410795: 48 29 c8 sub %rcx,%rax + 410798: 48 29 d0 sub %rdx,%rax + 41079b: 48 29 c3 sub %rax,%rbx + 41079e: e9 59 fc ff ff jmpq 4103fc <_IO_wfile_seekoff+0x29c> + 4107a3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4107a8: 49 8b 87 d8 00 00 00 mov 0xd8(%r15),%rax + 4107af: 31 f6 xor %esi,%esi + 4107b1: ba 01 00 00 00 mov $0x1,%edx + 4107b6: 4c 89 ff mov %r15,%rdi + 4107b9: ff 90 80 00 00 00 callq *0x80(%rax) + 4107bf: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 4107c3: 0f 84 1f fd ff ff je 4104e8 <_IO_wfile_seekoff+0x388> + 4107c9: e9 fa fc ff ff jmpq 4104c8 <_IO_wfile_seekoff+0x368> + 4107ce: 66 90 xchg %ax,%ax + 4107d0: 49 8b 87 a0 00 00 00 mov 0xa0(%r15),%rax + 4107d7: 4d 89 f0 mov %r14,%r8 + 4107da: 4c 2b 44 24 08 sub 0x8(%rsp),%r8 + 4107df: 49 8b 4f 10 mov 0x10(%r15),%rcx + 4107e3: 49 8b 57 18 mov 0x18(%r15),%rdx + 4107e7: 48 89 df mov %rbx,%rdi + 4107ea: 48 8d 74 24 20 lea 0x20(%rsp),%rsi + 4107ef: 48 8b 40 60 mov 0x60(%rax),%rax + 4107f3: 49 c1 f8 02 sar $0x2,%r8 + 4107f7: 48 89 44 24 20 mov %rax,0x20(%rsp) + 4107fc: ff 53 30 callq *0x30(%rbx) + 4107ff: 49 8b 4f 10 mov 0x10(%r15),%rcx + 410803: 49 2b 4f 18 sub 0x18(%r15),%rcx + 410807: 48 63 d0 movslq %eax,%rdx + 41080a: 48 89 d3 mov %rdx,%rbx + 41080d: 48 29 cb sub %rcx,%rbx + 410810: e9 a2 fc ff ff jmpq 4104b7 <_IO_wfile_seekoff+0x357> + 410815: 0f 1f 00 nopl (%rax) + 410818: 4d 8b b7 a0 00 00 00 mov 0xa0(%r15),%r14 + 41081f: 49 8b 4e 20 mov 0x20(%r14),%rcx + 410823: 4d 8b 66 18 mov 0x18(%r14),%r12 + 410827: 48 89 cd mov %rcx,%rbp + 41082a: 48 89 4c 24 08 mov %rcx,0x8(%rsp) + 41082f: 4c 29 e5 sub %r12,%rbp + 410832: 48 89 ef mov %rbp,%rdi + 410835: e8 d6 d1 00 00 callq 41da10 <__libc_malloc> + 41083a: 4c 89 64 24 20 mov %r12,0x20(%rsp) + 41083f: 48 89 44 24 18 mov %rax,0x18(%rsp) + 410844: 49 89 c2 mov %rax,%r10 + 410847: 49 8b 46 60 mov 0x60(%r14),%rax + 41084b: 4c 01 d5 add %r10,%rbp + 41084e: 4d 89 d1 mov %r10,%r9 + 410851: 4c 89 e2 mov %r12,%rdx + 410854: 48 89 df mov %rbx,%rdi + 410857: 48 89 44 24 10 mov %rax,0x10(%rsp) + 41085c: 48 8d 44 24 18 lea 0x18(%rsp),%rax + 410861: 50 push %rax + 410862: 55 push %rbp + 410863: 48 8b 4c 24 18 mov 0x18(%rsp),%rcx + 410868: 4c 89 54 24 10 mov %r10,0x10(%rsp) + 41086d: 4c 8d 44 24 30 lea 0x30(%rsp),%r8 + 410872: 48 8d 74 24 20 lea 0x20(%rsp),%rsi + 410877: ff 53 08 callq *0x8(%rbx) + 41087a: 5a pop %rdx + 41087b: 85 c0 test %eax,%eax + 41087d: 59 pop %rcx + 41087e: 4c 8b 14 24 mov (%rsp),%r10 + 410882: 75 15 jne 410899 <_IO_wfile_seekoff+0x739> + 410884: 48 8b 6c 24 18 mov 0x18(%rsp),%rbp + 410889: 4c 89 d7 mov %r10,%rdi + 41088c: 4c 29 d5 sub %r10,%rbp + 41088f: e8 1c d5 00 00 callq 41ddb0 <__cfree> + 410894: e9 bb fd ff ff jmpq 410654 <_IO_wfile_seekoff+0x4f4> + 410899: 4c 89 d7 mov %r10,%rdi + 41089c: e8 0f d5 00 00 callq 41ddb0 <__cfree> + 4108a1: ba ff ff ff ff mov $0xffffffff,%edx + 4108a6: e9 0c f9 ff ff jmpq 4101b7 <_IO_wfile_seekoff+0x57> + 4108ab: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + +00000000004108b0 <_IO_wfile_underflow_mmap>: + 4108b0: 8b 07 mov (%rdi),%eax + 4108b2: a8 04 test $0x4,%al + 4108b4: 0f 85 f6 00 00 00 jne 4109b0 <_IO_wfile_underflow_mmap+0x100> + 4108ba: 48 8b 87 a0 00 00 00 mov 0xa0(%rdi),%rax + 4108c1: 48 8b 10 mov (%rax),%rdx + 4108c4: 48 3b 50 08 cmp 0x8(%rax),%rdx + 4108c8: 0f 82 a2 00 00 00 jb 410970 <_IO_wfile_underflow_mmap+0xc0> + 4108ce: 55 push %rbp + 4108cf: 53 push %rbx + 4108d0: 48 89 fb mov %rdi,%rbx + 4108d3: 48 83 ec 18 sub $0x18,%rsp + 4108d7: 48 8b 57 08 mov 0x8(%rdi),%rdx + 4108db: 48 3b 57 10 cmp 0x10(%rdi),%rdx + 4108df: 48 8b af 98 00 00 00 mov 0x98(%rdi),%rbp + 4108e6: 0f 83 8c 00 00 00 jae 410978 <_IO_wfile_underflow_mmap+0xc8> + 4108ec: 48 83 78 30 00 cmpq $0x0,0x30(%rax) + 4108f1: 48 89 54 24 08 mov %rdx,0x8(%rsp) + 4108f6: 0f 84 d4 00 00 00 je 4109d0 <_IO_wfile_underflow_mmap+0x120> + 4108fc: 48 8b 50 58 mov 0x58(%rax),%rdx + 410900: 48 89 50 60 mov %rdx,0x60(%rax) + 410904: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 41090b: 48 8b 4b 10 mov 0x10(%rbx),%rcx + 41090f: 48 8b 53 08 mov 0x8(%rbx),%rdx + 410913: 4c 8b 48 30 mov 0x30(%rax),%r9 + 410917: 48 8d 78 08 lea 0x8(%rax),%rdi + 41091b: 48 8d 70 58 lea 0x58(%rax),%rsi + 41091f: 4c 89 08 mov %r9,(%rax) + 410922: 4c 89 48 10 mov %r9,0x10(%rax) + 410926: 57 push %rdi + 410927: ff 70 38 pushq 0x38(%rax) + 41092a: 48 89 ef mov %rbp,%rdi + 41092d: 4c 8d 44 24 18 lea 0x18(%rsp),%r8 + 410932: ff 55 18 callq *0x18(%rbp) + 410935: 48 8b 44 24 18 mov 0x18(%rsp),%rax + 41093a: 48 89 43 08 mov %rax,0x8(%rbx) + 41093e: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 410945: 59 pop %rcx + 410946: 5e pop %rsi + 410947: 48 8b 10 mov (%rax),%rdx + 41094a: 48 3b 50 08 cmp 0x8(%rax),%rdx + 41094e: 72 50 jb 4109a0 <_IO_wfile_underflow_mmap+0xf0> + 410950: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 410957: 64 c7 00 54 00 00 00 movl $0x54,%fs:(%rax) + 41095e: 83 0b 20 orl $0x20,(%rbx) + 410961: b8 ff ff ff ff mov $0xffffffff,%eax + 410966: 48 83 c4 18 add $0x18,%rsp + 41096a: 5b pop %rbx + 41096b: 5d pop %rbp + 41096c: c3 retq + 41096d: 0f 1f 00 nopl (%rax) + 410970: 8b 02 mov (%rdx),%eax + 410972: c3 retq + 410973: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 410978: e8 b3 24 00 00 callq 412e30 <_IO_file_underflow_mmap> + 41097d: 89 c2 mov %eax,%edx + 41097f: b8 ff ff ff ff mov $0xffffffff,%eax + 410984: 39 c2 cmp %eax,%edx + 410986: 74 de je 410966 <_IO_wfile_underflow_mmap+0xb6> + 410988: 48 8b 53 08 mov 0x8(%rbx),%rdx + 41098c: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 410993: e9 54 ff ff ff jmpq 4108ec <_IO_wfile_underflow_mmap+0x3c> + 410998: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 41099f: 00 + 4109a0: 8b 02 mov (%rdx),%eax + 4109a2: 48 83 c4 18 add $0x18,%rsp + 4109a6: 5b pop %rbx + 4109a7: 5d pop %rbp + 4109a8: c3 retq + 4109a9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4109b0: 83 c8 20 or $0x20,%eax + 4109b3: 89 07 mov %eax,(%rdi) + 4109b5: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 4109bc: 64 c7 00 09 00 00 00 movl $0x9,%fs:(%rax) + 4109c3: b8 ff ff ff ff mov $0xffffffff,%eax + 4109c8: c3 retq + 4109c9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4109d0: 48 8b 78 40 mov 0x40(%rax),%rdi + 4109d4: 48 85 ff test %rdi,%rdi + 4109d7: 74 0b je 4109e4 <_IO_wfile_underflow_mmap+0x134> + 4109d9: e8 d2 d3 00 00 callq 41ddb0 <__cfree> + 4109de: 81 23 ff fe ff ff andl $0xfffffeff,(%rbx) + 4109e4: 48 89 df mov %rbx,%rdi + 4109e7: e8 b4 3c 05 00 callq 4646a0 <_IO_wdoallocbuf> + 4109ec: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 4109f3: e9 04 ff ff ff jmpq 4108fc <_IO_wfile_underflow_mmap+0x4c> + 4109f8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 4109ff: 00 + +0000000000410a00 <_IO_wfile_underflow_maybe_mmap>: + 410a00: 53 push %rbx + 410a01: 48 89 fb mov %rdi,%rbx + 410a04: e8 b7 22 00 00 callq 412cc0 <_IO_file_underflow_maybe_mmap> + 410a09: 83 f8 ff cmp $0xffffffff,%eax + 410a0c: 75 02 jne 410a10 <_IO_wfile_underflow_maybe_mmap+0x10> + 410a0e: 5b pop %rbx + 410a0f: c3 retq + 410a10: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 410a17: 48 89 df mov %rbx,%rdi + 410a1a: 5b pop %rbx + 410a1b: 48 8b 80 30 01 00 00 mov 0x130(%rax),%rax + 410a22: 48 8b 40 20 mov 0x20(%rax),%rax + 410a26: ff e0 jmpq *%rax + 410a28: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 410a2f: 00 + +0000000000410a30 <_IO_wdo_write>: + 410a30: 41 57 push %r15 + 410a32: 41 56 push %r14 + 410a34: 41 55 push %r13 + 410a36: 41 54 push %r12 + 410a38: 55 push %rbp + 410a39: 53 push %rbx + 410a3a: 48 89 fb mov %rdi,%rbx + 410a3d: 48 83 ec 38 sub $0x38,%rsp + 410a41: 48 85 d2 test %rdx,%rdx + 410a44: 0f 84 46 01 00 00 je 410b90 <_IO_wdo_write+0x160> + 410a4a: 4c 8b 4f 28 mov 0x28(%rdi),%r9 + 410a4e: 4c 39 4f 30 cmp %r9,0x30(%rdi) + 410a52: 49 89 f7 mov %rsi,%r15 + 410a55: 48 8b 87 98 00 00 00 mov 0x98(%rdi),%rax + 410a5c: 49 89 d4 mov %rdx,%r12 + 410a5f: 48 8b 77 20 mov 0x20(%rdi),%rsi + 410a63: 48 89 44 24 08 mov %rax,0x8(%rsp) + 410a68: 0f 84 5e 01 00 00 je 410bcc <_IO_wdo_write+0x19c> + 410a6e: 48 89 f5 mov %rsi,%rbp + 410a71: e9 a7 00 00 00 jmpq 410b1d <_IO_wdo_write+0xed> + 410a76: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 410a7d: 00 00 00 + 410a80: 4c 8d 6c 24 20 lea 0x20(%rsp),%r13 + 410a85: 48 8d 44 24 30 lea 0x30(%rsp),%rax + 410a8a: 4d 89 e9 mov %r13,%r9 + 410a8d: 4c 89 ed mov %r13,%rbp + 410a90: 48 8b bb a0 00 00 00 mov 0xa0(%rbx),%rdi + 410a97: 4c 89 4c 24 18 mov %r9,0x18(%rsp) + 410a9c: 4b 8d 0c a7 lea (%r15,%r12,4),%rcx + 410aa0: 4c 89 fa mov %r15,%rdx + 410aa3: 48 8d 77 58 lea 0x58(%rdi),%rsi + 410aa7: 48 8d 7c 24 18 lea 0x18(%rsp),%rdi + 410aac: 57 push %rdi + 410aad: 50 push %rax + 410aae: 48 8b 44 24 18 mov 0x18(%rsp),%rax + 410ab3: 4c 8d 44 24 20 lea 0x20(%rsp),%r8 + 410ab8: 48 89 c7 mov %rax,%rdi + 410abb: ff 50 08 callq *0x8(%rax) + 410abe: 41 89 c6 mov %eax,%r14d + 410ac1: 48 89 ee mov %rbp,%rsi + 410ac4: 48 89 df mov %rbx,%rdi + 410ac7: 58 pop %rax + 410ac8: 5a pop %rdx + 410ac9: 48 8b 54 24 18 mov 0x18(%rsp),%rdx + 410ace: 4c 29 ea sub %r13,%rdx + 410ad1: e8 fa 26 00 00 callq 4131d0 <_IO_new_do_write> + 410ad6: 83 f8 ff cmp $0xffffffff,%eax + 410ad9: 0f 84 99 00 00 00 je 410b78 <_IO_wdo_write+0x148> + 410adf: 48 8b 54 24 10 mov 0x10(%rsp),%rdx + 410ae4: 48 89 d0 mov %rdx,%rax + 410ae7: 4c 29 f8 sub %r15,%rax + 410aea: 48 89 c6 mov %rax,%rsi + 410aed: 48 c1 fe 02 sar $0x2,%rsi + 410af1: 49 29 f4 sub %rsi,%r12 + 410af4: 45 85 f6 test %r14d,%r14d + 410af7: 74 10 je 410b09 <_IO_wdo_write+0xd9> + 410af9: 41 83 fe 01 cmp $0x1,%r14d + 410afd: 75 41 jne 410b40 <_IO_wdo_write+0x110> + 410aff: 48 83 c0 03 add $0x3,%rax + 410b03: 48 83 f8 06 cmp $0x6,%rax + 410b07: 76 37 jbe 410b40 <_IO_wdo_write+0x110> + 410b09: 4d 85 e4 test %r12,%r12 + 410b0c: 0f 84 7e 00 00 00 je 410b90 <_IO_wdo_write+0x160> + 410b12: 4c 8b 4b 28 mov 0x28(%rbx),%r9 + 410b16: 48 8b 6b 20 mov 0x20(%rbx),%rbp + 410b1a: 49 89 d7 mov %rdx,%r15 + 410b1d: 4c 89 c8 mov %r9,%rax + 410b20: 49 89 ed mov %rbp,%r13 + 410b23: 48 29 e8 sub %rbp,%rax + 410b26: 48 83 f8 0f cmp $0xf,%rax + 410b2a: 0f 86 50 ff ff ff jbe 410a80 <_IO_wdo_write+0x50> + 410b30: 48 8b 43 40 mov 0x40(%rbx),%rax + 410b34: e9 57 ff ff ff jmpq 410a90 <_IO_wdo_write+0x60> + 410b39: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 410b40: 48 8b 93 a0 00 00 00 mov 0xa0(%rbx),%rdx + 410b47: 31 c0 xor %eax,%eax + 410b49: 4d 85 e4 test %r12,%r12 + 410b4c: 0f 95 c0 setne %al + 410b4f: f7 d8 neg %eax + 410b51: f7 03 02 02 00 00 testl $0x202,(%rbx) + 410b57: 48 8b 4a 30 mov 0x30(%rdx),%rcx + 410b5b: 48 89 4a 10 mov %rcx,0x10(%rdx) + 410b5f: 48 89 0a mov %rcx,(%rdx) + 410b62: 48 89 4a 08 mov %rcx,0x8(%rdx) + 410b66: 48 89 4a 20 mov %rcx,0x20(%rdx) + 410b6a: 48 89 4a 18 mov %rcx,0x18(%rdx) + 410b6e: 75 04 jne 410b74 <_IO_wdo_write+0x144> + 410b70: 48 8b 4a 38 mov 0x38(%rdx),%rcx + 410b74: 48 89 4a 28 mov %rcx,0x28(%rdx) + 410b78: 48 83 c4 38 add $0x38,%rsp + 410b7c: 5b pop %rbx + 410b7d: 5d pop %rbp + 410b7e: 41 5c pop %r12 + 410b80: 41 5d pop %r13 + 410b82: 41 5e pop %r14 + 410b84: 41 5f pop %r15 + 410b86: c3 retq + 410b87: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 410b8e: 00 00 + 410b90: 48 8b 93 a0 00 00 00 mov 0xa0(%rbx),%rdx + 410b97: 8b 03 mov (%rbx),%eax + 410b99: 48 8b 4a 30 mov 0x30(%rdx),%rcx + 410b9d: 25 02 02 00 00 and $0x202,%eax + 410ba2: 48 89 4a 10 mov %rcx,0x10(%rdx) + 410ba6: 48 89 0a mov %rcx,(%rdx) + 410ba9: 48 89 4a 08 mov %rcx,0x8(%rdx) + 410bad: 48 89 4a 20 mov %rcx,0x20(%rdx) + 410bb1: 48 89 4a 18 mov %rcx,0x18(%rdx) + 410bb5: 74 b9 je 410b70 <_IO_wdo_write+0x140> + 410bb7: 48 89 4a 28 mov %rcx,0x28(%rdx) + 410bbb: 48 83 c4 38 add $0x38,%rsp + 410bbf: 31 c0 xor %eax,%eax + 410bc1: 5b pop %rbx + 410bc2: 5d pop %rbp + 410bc3: 41 5c pop %r12 + 410bc5: 41 5d pop %r13 + 410bc7: 41 5e pop %r14 + 410bc9: 41 5f pop %r15 + 410bcb: c3 retq + 410bcc: 49 39 f1 cmp %rsi,%r9 + 410bcf: 0f 84 99 fe ff ff je 410a6e <_IO_wdo_write+0x3e> + 410bd5: 4c 89 ca mov %r9,%rdx + 410bd8: 48 29 f2 sub %rsi,%rdx + 410bdb: e8 f0 25 00 00 callq 4131d0 <_IO_new_do_write> + 410be0: 83 f8 ff cmp $0xffffffff,%eax + 410be3: 74 93 je 410b78 <_IO_wdo_write+0x148> + 410be5: 4c 8b 4b 28 mov 0x28(%rbx),%r9 + 410be9: 48 8b 73 20 mov 0x20(%rbx),%rsi + 410bed: e9 7c fe ff ff jmpq 410a6e <_IO_wdo_write+0x3e> + 410bf2: 0f 1f 40 00 nopl 0x0(%rax) + 410bf6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 410bfd: 00 00 00 + +0000000000410c00 <_IO_wfile_overflow>: + 410c00: 8b 17 mov (%rdi),%edx + 410c02: f6 c2 08 test $0x8,%dl + 410c05: 74 19 je 410c20 <_IO_wfile_overflow+0x20> + 410c07: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 410c0e: 83 ca 20 or $0x20,%edx + 410c11: 89 17 mov %edx,(%rdi) + 410c13: 64 c7 00 09 00 00 00 movl $0x9,%fs:(%rax) + 410c1a: b8 ff ff ff ff mov $0xffffffff,%eax + 410c1f: c3 retq + 410c20: 55 push %rbp + 410c21: 53 push %rbx + 410c22: 89 f5 mov %esi,%ebp + 410c24: 48 89 fb mov %rdi,%rbx + 410c27: 48 83 ec 08 sub $0x8,%rsp + 410c2b: f6 c6 08 test $0x8,%dh + 410c2e: 75 6f jne 410c9f <_IO_wfile_overflow+0x9f> + 410c30: 48 8b 8f a0 00 00 00 mov 0xa0(%rdi),%rcx + 410c37: 48 83 79 18 00 cmpq $0x0,0x18(%rcx) + 410c3c: 0f 84 be 01 00 00 je 410e00 <_IO_wfile_overflow+0x200> + 410c42: 48 8b 01 mov (%rcx),%rax + 410c45: 48 8b 71 38 mov 0x38(%rcx),%rsi + 410c49: 48 39 f0 cmp %rsi,%rax + 410c4c: 0f 84 8e 01 00 00 je 410de0 <_IO_wfile_overflow+0x1e0> + 410c52: 48 89 71 28 mov %rsi,0x28(%rcx) + 410c56: 48 8b 71 08 mov 0x8(%rcx),%rsi + 410c5a: 48 89 41 20 mov %rax,0x20(%rcx) + 410c5e: 48 89 41 18 mov %rax,0x18(%rcx) + 410c62: 48 89 31 mov %rsi,(%rcx) + 410c65: 48 89 71 10 mov %rsi,0x10(%rcx) + 410c69: 48 8b 73 08 mov 0x8(%rbx),%rsi + 410c6d: 48 89 73 28 mov %rsi,0x28(%rbx) + 410c71: 48 89 73 20 mov %rsi,0x20(%rbx) + 410c75: 48 8b 73 40 mov 0x40(%rbx),%rsi + 410c79: 48 89 73 30 mov %rsi,0x30(%rbx) + 410c7d: 48 8b 73 10 mov 0x10(%rbx),%rsi + 410c81: 48 89 73 08 mov %rsi,0x8(%rbx) + 410c85: 48 89 73 18 mov %rsi,0x18(%rbx) + 410c89: 89 d6 mov %edx,%esi + 410c8b: 81 ce 00 08 00 00 or $0x800,%esi + 410c91: 81 e2 02 02 00 00 and $0x202,%edx + 410c97: 89 33 mov %esi,(%rbx) + 410c99: 74 04 je 410c9f <_IO_wfile_overflow+0x9f> + 410c9b: 48 89 41 28 mov %rax,0x28(%rcx) + 410c9f: 83 fd ff cmp $0xffffffff,%ebp + 410ca2: 74 7c je 410d20 <_IO_wfile_overflow+0x120> + 410ca4: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 410cab: 48 8b 48 20 mov 0x20(%rax),%rcx + 410caf: 48 3b 48 38 cmp 0x38(%rax),%rcx + 410cb3: 0f 84 9f 00 00 00 je 410d58 <_IO_wfile_overflow+0x158> + 410cb9: 48 8d 51 04 lea 0x4(%rcx),%rdx + 410cbd: 48 89 50 20 mov %rdx,0x20(%rax) + 410cc1: 89 29 mov %ebp,(%rcx) + 410cc3: 8b 0b mov (%rbx),%ecx + 410cc5: f6 c1 02 test $0x2,%cl + 410cc8: 74 3e je 410d08 <_IO_wfile_overflow+0x108> + 410cca: 8b 8b c0 00 00 00 mov 0xc0(%rbx),%ecx + 410cd0: 85 c9 test %ecx,%ecx + 410cd2: 0f 8e c8 00 00 00 jle 410da0 <_IO_wfile_overflow+0x1a0> + 410cd8: 48 8b 70 18 mov 0x18(%rax),%rsi + 410cdc: 48 89 df mov %rbx,%rdi + 410cdf: 48 29 f2 sub %rsi,%rdx + 410ce2: 48 c1 fa 02 sar $0x2,%rdx + 410ce6: e8 45 fd ff ff callq 410a30 <_IO_wdo_write> + 410ceb: 83 f8 ff cmp $0xffffffff,%eax + 410cee: 0f 94 c0 sete %al + 410cf1: 84 c0 test %al,%al + 410cf3: 74 1d je 410d12 <_IO_wfile_overflow+0x112> + 410cf5: 48 83 c4 08 add $0x8,%rsp + 410cf9: b8 ff ff ff ff mov $0xffffffff,%eax + 410cfe: 5b pop %rbx + 410cff: 5d pop %rbp + 410d00: c3 retq + 410d01: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 410d08: 80 e5 02 and $0x2,%ch + 410d0b: 74 05 je 410d12 <_IO_wfile_overflow+0x112> + 410d0d: 83 fd 0a cmp $0xa,%ebp + 410d10: 74 b8 je 410cca <_IO_wfile_overflow+0xca> + 410d12: 48 83 c4 08 add $0x8,%rsp + 410d16: 89 e8 mov %ebp,%eax + 410d18: 5b pop %rbx + 410d19: 5d pop %rbp + 410d1a: c3 retq + 410d1b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 410d20: 8b bb c0 00 00 00 mov 0xc0(%rbx),%edi + 410d26: 85 ff test %edi,%edi + 410d28: 0f 8e 92 00 00 00 jle 410dc0 <_IO_wfile_overflow+0x1c0> + 410d2e: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 410d35: 48 89 df mov %rbx,%rdi + 410d38: 48 8b 70 18 mov 0x18(%rax),%rsi + 410d3c: 48 8b 50 20 mov 0x20(%rax),%rdx + 410d40: 48 83 c4 08 add $0x8,%rsp + 410d44: 5b pop %rbx + 410d45: 5d pop %rbp + 410d46: 48 29 f2 sub %rsi,%rdx + 410d49: 48 c1 fa 02 sar $0x2,%rdx + 410d4d: e9 de fc ff ff jmpq 410a30 <_IO_wdo_write> + 410d52: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 410d58: 8b b3 c0 00 00 00 mov 0xc0(%rbx),%esi + 410d5e: 85 f6 test %esi,%esi + 410d60: 0f 8e c7 00 00 00 jle 410e2d <_IO_wfile_overflow+0x22d> + 410d66: 48 8b 70 18 mov 0x18(%rax),%rsi + 410d6a: 48 89 df mov %rbx,%rdi + 410d6d: 48 29 f1 sub %rsi,%rcx + 410d70: 48 89 ca mov %rcx,%rdx + 410d73: 48 c1 fa 02 sar $0x2,%rdx + 410d77: e8 b4 fc ff ff callq 410a30 <_IO_wdo_write> + 410d7c: 83 f8 ff cmp $0xffffffff,%eax + 410d7f: 0f 94 c0 sete %al + 410d82: 84 c0 test %al,%al + 410d84: 0f 85 6b ff ff ff jne 410cf5 <_IO_wfile_overflow+0xf5> + 410d8a: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 410d91: 48 8b 48 20 mov 0x20(%rax),%rcx + 410d95: e9 1f ff ff ff jmpq 410cb9 <_IO_wfile_overflow+0xb9> + 410d9a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 410da0: 48 8b 73 20 mov 0x20(%rbx),%rsi + 410da4: 48 8b 53 28 mov 0x28(%rbx),%rdx + 410da8: 48 89 df mov %rbx,%rdi + 410dab: 48 29 f2 sub %rsi,%rdx + 410dae: e8 1d 24 00 00 callq 4131d0 <_IO_new_do_write> + 410db3: 83 f8 ff cmp $0xffffffff,%eax + 410db6: 0f 94 c0 sete %al + 410db9: e9 33 ff ff ff jmpq 410cf1 <_IO_wfile_overflow+0xf1> + 410dbe: 66 90 xchg %ax,%ax + 410dc0: 48 8b 73 20 mov 0x20(%rbx),%rsi + 410dc4: 48 8b 53 28 mov 0x28(%rbx),%rdx + 410dc8: 48 83 c4 08 add $0x8,%rsp + 410dcc: 48 89 df mov %rbx,%rdi + 410dcf: 5b pop %rbx + 410dd0: 5d pop %rbp + 410dd1: 48 29 f2 sub %rsi,%rdx + 410dd4: e9 f7 23 00 00 jmpq 4131d0 <_IO_new_do_write> + 410dd9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 410de0: 48 8b 47 38 mov 0x38(%rdi),%rax + 410de4: 48 89 47 08 mov %rax,0x8(%rdi) + 410de8: 48 89 47 10 mov %rax,0x10(%rdi) + 410dec: 48 8b 41 30 mov 0x30(%rcx),%rax + 410df0: 48 89 01 mov %rax,(%rcx) + 410df3: 48 89 41 08 mov %rax,0x8(%rcx) + 410df7: e9 56 fe ff ff jmpq 410c52 <_IO_wfile_overflow+0x52> + 410dfc: 0f 1f 40 00 nopl 0x0(%rax) + 410e00: e8 9b 38 05 00 callq 4646a0 <_IO_wdoallocbuf> + 410e05: 48 8b 8b a0 00 00 00 mov 0xa0(%rbx),%rcx + 410e0c: 48 83 7b 20 00 cmpq $0x0,0x20(%rbx) + 410e11: 48 8b 41 30 mov 0x30(%rcx),%rax + 410e15: 48 89 41 10 mov %rax,0x10(%rcx) + 410e19: 48 89 01 mov %rax,(%rcx) + 410e1c: 48 89 41 08 mov %rax,0x8(%rcx) + 410e20: 74 29 je 410e4b <_IO_wfile_overflow+0x24b> + 410e22: 48 8b 71 38 mov 0x38(%rcx),%rsi + 410e26: 8b 13 mov (%rbx),%edx + 410e28: e9 25 fe ff ff jmpq 410c52 <_IO_wfile_overflow+0x52> + 410e2d: 48 8b 73 20 mov 0x20(%rbx),%rsi + 410e31: 48 8b 53 28 mov 0x28(%rbx),%rdx + 410e35: 48 89 df mov %rbx,%rdi + 410e38: 48 29 f2 sub %rsi,%rdx + 410e3b: e8 90 23 00 00 callq 4131d0 <_IO_new_do_write> + 410e40: 83 f8 ff cmp $0xffffffff,%eax + 410e43: 0f 94 c0 sete %al + 410e46: e9 37 ff ff ff jmpq 410d82 <_IO_wfile_overflow+0x182> + 410e4b: 48 89 df mov %rbx,%rdi + 410e4e: e8 ad 3f 00 00 callq 414e00 <_IO_doallocbuf> + 410e53: 48 8b 43 38 mov 0x38(%rbx),%rax + 410e57: 48 8b 8b a0 00 00 00 mov 0xa0(%rbx),%rcx + 410e5e: 48 89 43 08 mov %rax,0x8(%rbx) + 410e62: 48 89 43 10 mov %rax,0x10(%rbx) + 410e66: 48 8b 01 mov (%rcx),%rax + 410e69: eb b7 jmp 410e22 <_IO_wfile_overflow+0x222> + 410e6b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + +0000000000410e70 <_IO_wfile_sync>: + 410e70: 41 54 push %r12 + 410e72: 55 push %rbp + 410e73: 53 push %rbx + 410e74: 48 8b 87 a0 00 00 00 mov 0xa0(%rdi),%rax + 410e7b: 48 89 fb mov %rdi,%rbx + 410e7e: 48 8b 50 20 mov 0x20(%rax),%rdx + 410e82: 48 8b 70 18 mov 0x18(%rax),%rsi + 410e86: 48 39 f2 cmp %rsi,%rdx + 410e89: 76 3c jbe 410ec7 <_IO_wfile_sync+0x57> + 410e8b: 8b 87 c0 00 00 00 mov 0xc0(%rdi),%eax + 410e91: 85 c0 test %eax,%eax + 410e93: 0f 8e a7 00 00 00 jle 410f40 <_IO_wfile_sync+0xd0> + 410e99: 48 29 f2 sub %rsi,%rdx + 410e9c: 48 c1 fa 02 sar $0x2,%rdx + 410ea0: e8 8b fb ff ff callq 410a30 <_IO_wdo_write> + 410ea5: 85 c0 test %eax,%eax + 410ea7: 0f 95 c0 setne %al + 410eaa: 84 c0 test %al,%al + 410eac: 74 12 je 410ec0 <_IO_wfile_sync+0x50> + 410eae: 5b pop %rbx + 410eaf: b8 ff ff ff ff mov $0xffffffff,%eax + 410eb4: 5d pop %rbp + 410eb5: 41 5c pop %r12 + 410eb7: c3 retq + 410eb8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 410ebf: 00 + 410ec0: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 410ec7: 48 8b 28 mov (%rax),%rbp + 410eca: 48 2b 68 08 sub 0x8(%rax),%rbp + 410ece: 48 c1 fd 02 sar $0x2,%rbp + 410ed2: 48 85 ed test %rbp,%rbp + 410ed5: 75 19 jne 410ef0 <_IO_wfile_sync+0x80> + 410ed7: 48 c7 83 90 00 00 00 movq $0xffffffffffffffff,0x90(%rbx) + 410ede: ff ff ff ff + 410ee2: 31 c0 xor %eax,%eax + 410ee4: 5b pop %rbx + 410ee5: 5d pop %rbp + 410ee6: 41 5c pop %r12 + 410ee8: c3 retq + 410ee9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 410ef0: 4c 8b a3 98 00 00 00 mov 0x98(%rbx),%r12 + 410ef7: 4c 89 e7 mov %r12,%rdi + 410efa: 41 ff 54 24 20 callq *0x20(%r12) + 410eff: 85 c0 test %eax,%eax + 410f01: 7e 7d jle 410f80 <_IO_wfile_sync+0x110> + 410f03: 48 63 f0 movslq %eax,%rsi + 410f06: 48 0f af f5 imul %rbp,%rsi + 410f0a: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 410f11: ba 01 00 00 00 mov $0x1,%edx + 410f16: 48 89 df mov %rbx,%rdi + 410f19: ff 90 80 00 00 00 callq *0x80(%rax) + 410f1f: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 410f23: 74 3b je 410f60 <_IO_wfile_sync+0xf0> + 410f25: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 410f2c: 48 8b 10 mov (%rax),%rdx + 410f2f: 48 89 50 08 mov %rdx,0x8(%rax) + 410f33: 48 8b 43 08 mov 0x8(%rbx),%rax + 410f37: 48 89 43 10 mov %rax,0x10(%rbx) + 410f3b: eb 9a jmp 410ed7 <_IO_wfile_sync+0x67> + 410f3d: 0f 1f 00 nopl (%rax) + 410f40: 48 8b 77 20 mov 0x20(%rdi),%rsi + 410f44: 48 8b 57 28 mov 0x28(%rdi),%rdx + 410f48: 48 29 f2 sub %rsi,%rdx + 410f4b: e8 80 22 00 00 callq 4131d0 <_IO_new_do_write> + 410f50: 85 c0 test %eax,%eax + 410f52: 0f 95 c0 setne %al + 410f55: e9 50 ff ff ff jmpq 410eaa <_IO_wfile_sync+0x3a> + 410f5a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 410f60: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 410f67: 64 83 38 1d cmpl $0x1d,%fs:(%rax) + 410f6b: 0f 85 3d ff ff ff jne 410eae <_IO_wfile_sync+0x3e> + 410f71: e9 61 ff ff ff jmpq 410ed7 <_IO_wfile_sync+0x67> + 410f76: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 410f7d: 00 00 00 + 410f80: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 410f87: 49 89 e8 mov %rbp,%r8 + 410f8a: 4c 89 e7 mov %r12,%rdi + 410f8d: 48 8b 50 60 mov 0x60(%rax),%rdx + 410f91: 48 89 50 58 mov %rdx,0x58(%rax) + 410f95: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 410f9c: 48 8b 4b 10 mov 0x10(%rbx),%rcx + 410fa0: 48 8b 53 18 mov 0x18(%rbx),%rdx + 410fa4: 48 8d 70 58 lea 0x58(%rax),%rsi + 410fa8: 41 ff 54 24 30 callq *0x30(%r12) + 410fad: 48 8b 53 18 mov 0x18(%rbx),%rdx + 410fb1: 48 98 cltq + 410fb3: 48 8d 0c 02 lea (%rdx,%rax,1),%rcx + 410fb7: 48 2b 53 10 sub 0x10(%rbx),%rdx + 410fbb: 48 89 4b 08 mov %rcx,0x8(%rbx) + 410fbf: 48 8d 34 02 lea (%rdx,%rax,1),%rsi + 410fc3: e9 42 ff ff ff jmpq 410f0a <_IO_wfile_sync+0x9a> + 410fc8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 410fcf: 00 + +0000000000410fd0 <_IO_wfile_xsputn>: + 410fd0: 48 85 d2 test %rdx,%rdx + 410fd3: 0f 84 df 01 00 00 je 4111b8 <_IO_wfile_xsputn+0x1e8> + 410fd9: 41 57 push %r15 + 410fdb: 41 56 push %r14 + 410fdd: 41 55 push %r13 + 410fdf: 41 54 push %r12 + 410fe1: 49 89 fd mov %rdi,%r13 + 410fe4: 55 push %rbp + 410fe5: 53 push %rbx + 410fe6: 48 89 f5 mov %rsi,%rbp + 410fe9: 49 89 d4 mov %rdx,%r12 + 410fec: 48 83 ec 28 sub $0x28,%rsp + 410ff0: 41 8b 45 00 mov 0x0(%r13),%eax + 410ff4: 4c 8b b7 a0 00 00 00 mov 0xa0(%rdi),%r14 + 410ffb: 25 00 0a 00 00 and $0xa00,%eax + 411000: 49 8b 5e 28 mov 0x28(%r14),%rbx + 411004: 49 8b 7e 20 mov 0x20(%r14),%rdi + 411008: 3d 00 0a 00 00 cmp $0xa00,%eax + 41100d: 0f 84 cd 01 00 00 je 4111e0 <_IO_wfile_xsputn+0x210> + 411013: 48 29 fb sub %rdi,%rbx + 411016: 45 31 ff xor %r15d,%r15d + 411019: 48 c1 fb 02 sar $0x2,%rbx + 41101d: 48 85 db test %rbx,%rbx + 411020: 0f 84 9a 01 00 00 je 4111c0 <_IO_wfile_xsputn+0x1f0> + 411026: 49 39 dc cmp %rbx,%r12 + 411029: 49 0f 46 dc cmovbe %r12,%rbx + 41102d: 48 83 fb 14 cmp $0x14,%rbx + 411031: 0f 87 f9 01 00 00 ja 411230 <_IO_wfile_xsputn+0x260> + 411037: 48 8d 55 10 lea 0x10(%rbp),%rdx + 41103b: 8d 43 ff lea -0x1(%rbx),%eax + 41103e: 48 39 d7 cmp %rdx,%rdi + 411041: 48 8d 57 10 lea 0x10(%rdi),%rdx + 411045: 89 c1 mov %eax,%ecx + 411047: 40 0f 93 c6 setae %sil + 41104b: 48 39 d5 cmp %rdx,%rbp + 41104e: 0f 93 c2 setae %dl + 411051: 40 08 d6 or %dl,%sil + 411054: 0f 84 06 02 00 00 je 411260 <_IO_wfile_xsputn+0x290> + 41105a: 83 fb 0c cmp $0xc,%ebx + 41105d: 0f 86 fd 01 00 00 jbe 411260 <_IO_wfile_xsputn+0x290> + 411063: 49 89 e8 mov %rbp,%r8 + 411066: 41 83 e0 0f and $0xf,%r8d + 41106a: 49 c1 e8 02 shr $0x2,%r8 + 41106e: 49 f7 d8 neg %r8 + 411071: 41 83 e0 03 and $0x3,%r8d + 411075: 41 39 d8 cmp %ebx,%r8d + 411078: 44 0f 47 c3 cmova %ebx,%r8d + 41107c: 45 85 c0 test %r8d,%r8d + 41107f: 0f 84 cb 01 00 00 je 411250 <_IO_wfile_xsputn+0x280> + 411085: 8b 55 00 mov 0x0(%rbp),%edx + 411088: 41 83 f8 01 cmp $0x1,%r8d + 41108c: 48 8d 77 04 lea 0x4(%rdi),%rsi + 411090: 4c 8d 55 04 lea 0x4(%rbp),%r10 + 411094: 8d 4b fe lea -0x2(%rbx),%ecx + 411097: 89 17 mov %edx,(%rdi) + 411099: 74 28 je 4110c3 <_IO_wfile_xsputn+0xf3> + 41109b: 8b 55 04 mov 0x4(%rbp),%edx + 41109e: 41 83 f8 03 cmp $0x3,%r8d + 4110a2: 48 8d 77 08 lea 0x8(%rdi),%rsi + 4110a6: 4c 8d 55 08 lea 0x8(%rbp),%r10 + 4110aa: 8d 4b fd lea -0x3(%rbx),%ecx + 4110ad: 89 57 04 mov %edx,0x4(%rdi) + 4110b0: 75 11 jne 4110c3 <_IO_wfile_xsputn+0xf3> + 4110b2: 8b 55 08 mov 0x8(%rbp),%edx + 4110b5: 48 8d 77 0c lea 0xc(%rdi),%rsi + 4110b9: 4c 8d 55 0c lea 0xc(%rbp),%r10 + 4110bd: 8d 4b fc lea -0x4(%rbx),%ecx + 4110c0: 89 57 08 mov %edx,0x8(%rdi) + 4110c3: 89 da mov %ebx,%edx + 4110c5: 89 44 24 1c mov %eax,0x1c(%rsp) + 4110c9: 44 29 c2 sub %r8d,%edx + 4110cc: 45 89 c0 mov %r8d,%r8d + 4110cf: 89 54 24 14 mov %edx,0x14(%rsp) + 4110d3: 83 ea 04 sub $0x4,%edx + 4110d6: 49 c1 e0 02 shl $0x2,%r8 + 4110da: c1 ea 02 shr $0x2,%edx + 4110dd: 4e 8d 5c 05 00 lea 0x0(%rbp,%r8,1),%r11 + 4110e2: 83 c2 01 add $0x1,%edx + 4110e5: 44 8d 0c 95 00 00 00 lea 0x0(,%rdx,4),%r9d + 4110ec: 00 + 4110ed: 44 89 4c 24 18 mov %r9d,0x18(%rsp) + 4110f2: 4e 8d 0c 07 lea (%rdi,%r8,1),%r9 + 4110f6: 45 31 c0 xor %r8d,%r8d + 4110f9: 4c 89 4c 24 08 mov %r9,0x8(%rsp) + 4110fe: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 411103: 45 31 c9 xor %r9d,%r9d + 411106: 66 43 0f 6f 04 03 movdqa (%r11,%r8,1),%xmm0 + 41110c: 41 83 c1 01 add $0x1,%r9d + 411110: 42 0f 11 04 00 movups %xmm0,(%rax,%r8,1) + 411115: 49 83 c0 10 add $0x10,%r8 + 411119: 41 39 d1 cmp %edx,%r9d + 41111c: 72 e8 jb 411106 <_IO_wfile_xsputn+0x136> + 41111e: 44 8b 5c 24 18 mov 0x18(%rsp),%r11d + 411123: 8b 44 24 1c mov 0x1c(%rsp),%eax + 411127: 44 89 da mov %r11d,%edx + 41112a: 44 29 d9 sub %r11d,%ecx + 41112d: 48 c1 e2 02 shl $0x2,%rdx + 411131: 48 01 d6 add %rdx,%rsi + 411134: 49 01 d2 add %rdx,%r10 + 411137: 44 39 5c 24 14 cmp %r11d,0x14(%rsp) + 41113c: 74 1c je 41115a <_IO_wfile_xsputn+0x18a> + 41113e: 41 8b 12 mov (%r10),%edx + 411141: 85 c9 test %ecx,%ecx + 411143: 89 16 mov %edx,(%rsi) + 411145: 74 13 je 41115a <_IO_wfile_xsputn+0x18a> + 411147: 41 8b 52 04 mov 0x4(%r10),%edx + 41114b: 83 f9 01 cmp $0x1,%ecx + 41114e: 89 56 04 mov %edx,0x4(%rsi) + 411151: 74 07 je 41115a <_IO_wfile_xsputn+0x18a> + 411153: 41 8b 52 08 mov 0x8(%r10),%edx + 411157: 89 56 08 mov %edx,0x8(%rsi) + 41115a: 48 8d 04 85 04 00 00 lea 0x4(,%rax,4),%rax + 411161: 00 + 411162: 48 01 c7 add %rax,%rdi + 411165: 48 01 c5 add %rax,%rbp + 411168: 49 89 7e 20 mov %rdi,0x20(%r14) + 41116c: 4c 89 e0 mov %r12,%rax + 41116f: 48 29 d8 sub %rbx,%rax + 411172: 48 89 c3 mov %rax,%rbx + 411175: 75 4c jne 4111c3 <_IO_wfile_xsputn+0x1f3> + 411177: 45 85 ff test %r15d,%r15d + 41117a: 74 23 je 41119f <_IO_wfile_xsputn+0x1cf> + 41117c: 49 8b 85 a0 00 00 00 mov 0xa0(%r13),%rax + 411183: 48 8b 50 20 mov 0x20(%rax),%rdx + 411187: 48 8b 70 18 mov 0x18(%rax),%rsi + 41118b: 48 39 f2 cmp %rsi,%rdx + 41118e: 74 0f je 41119f <_IO_wfile_xsputn+0x1cf> + 411190: 48 29 f2 sub %rsi,%rdx + 411193: 4c 89 ef mov %r13,%rdi + 411196: 48 c1 fa 02 sar $0x2,%rdx + 41119a: e8 91 f8 ff ff callq 410a30 <_IO_wdo_write> + 41119f: 48 83 c4 28 add $0x28,%rsp + 4111a3: 4c 89 e0 mov %r12,%rax + 4111a6: 48 29 d8 sub %rbx,%rax + 4111a9: 5b pop %rbx + 4111aa: 5d pop %rbp + 4111ab: 41 5c pop %r12 + 4111ad: 41 5d pop %r13 + 4111af: 41 5e pop %r14 + 4111b1: 41 5f pop %r15 + 4111b3: c3 retq + 4111b4: 0f 1f 40 00 nopl 0x0(%rax) + 4111b8: 31 c0 xor %eax,%eax + 4111ba: c3 retq + 4111bb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4111c0: 4c 89 e3 mov %r12,%rbx + 4111c3: 48 89 da mov %rbx,%rdx + 4111c6: 48 89 ee mov %rbp,%rsi + 4111c9: 4c 89 ef mov %r13,%rdi + 4111cc: e8 df 2d 05 00 callq 463fb0 <_IO_wdefault_xsputn> + 4111d1: 48 29 c3 sub %rax,%rbx + 4111d4: eb a1 jmp 411177 <_IO_wfile_xsputn+0x1a7> + 4111d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4111dd: 00 00 00 + 4111e0: 49 8b 5e 38 mov 0x38(%r14),%rbx + 4111e4: 45 31 ff xor %r15d,%r15d + 4111e7: 48 29 fb sub %rdi,%rbx + 4111ea: 48 c1 fb 02 sar $0x2,%rbx + 4111ee: 48 39 da cmp %rbx,%rdx + 4111f1: 0f 87 26 fe ff ff ja 41101d <_IO_wfile_xsputn+0x4d> + 4111f7: 48 8d 14 96 lea (%rsi,%rdx,4),%rdx + 4111fb: 48 39 d6 cmp %rdx,%rsi + 4111fe: 0f 83 19 fe ff ff jae 41101d <_IO_wfile_xsputn+0x4d> + 411204: 83 7a fc 0a cmpl $0xa,-0x4(%rdx) + 411208: 48 8d 42 fc lea -0x4(%rdx),%rax + 41120c: 75 0b jne 411219 <_IO_wfile_xsputn+0x249> + 41120e: eb 78 jmp 411288 <_IO_wfile_xsputn+0x2b8> + 411210: 48 83 e8 04 sub $0x4,%rax + 411214: 83 38 0a cmpl $0xa,(%rax) + 411217: 74 6f je 411288 <_IO_wfile_xsputn+0x2b8> + 411219: 48 39 c5 cmp %rax,%rbp + 41121c: 72 f2 jb 411210 <_IO_wfile_xsputn+0x240> + 41121e: 45 31 ff xor %r15d,%r15d + 411221: e9 f7 fd ff ff jmpq 41101d <_IO_wfile_xsputn+0x4d> + 411226: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41122d: 00 00 00 + 411230: 48 89 ee mov %rbp,%rsi + 411233: 48 89 da mov %rbx,%rdx + 411236: 48 8d 6c 9d 00 lea 0x0(%rbp,%rbx,4),%rbp + 41123b: e8 00 d1 02 00 callq 43e340 <__wmempcpy> + 411240: 49 89 46 20 mov %rax,0x20(%r14) + 411244: e9 23 ff ff ff jmpq 41116c <_IO_wfile_xsputn+0x19c> + 411249: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 411250: 49 89 ea mov %rbp,%r10 + 411253: 48 89 fe mov %rdi,%rsi + 411256: e9 68 fe ff ff jmpq 4110c3 <_IO_wfile_xsputn+0xf3> + 41125b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 411260: 89 c6 mov %eax,%esi + 411262: 31 d2 xor %edx,%edx + 411264: 48 83 c6 01 add $0x1,%rsi + 411268: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 41126f: 00 + 411270: 8b 4c 95 00 mov 0x0(%rbp,%rdx,4),%ecx + 411274: 89 0c 97 mov %ecx,(%rdi,%rdx,4) + 411277: 48 83 c2 01 add $0x1,%rdx + 41127b: 48 39 f2 cmp %rsi,%rdx + 41127e: 75 f0 jne 411270 <_IO_wfile_xsputn+0x2a0> + 411280: e9 d5 fe ff ff jmpq 41115a <_IO_wfile_xsputn+0x18a> + 411285: 0f 1f 00 nopl (%rax) + 411288: 48 29 e8 sub %rbp,%rax + 41128b: 41 bf 01 00 00 00 mov $0x1,%r15d + 411291: 48 c1 f8 02 sar $0x2,%rax + 411295: 48 8d 58 01 lea 0x1(%rax),%rbx + 411299: e9 7f fd ff ff jmpq 41101d <_IO_wfile_xsputn+0x4d> + 41129e: 66 90 xchg %ax,%ax + +00000000004112a0 <_IO_vasprintf>: + 4112a0: 41 55 push %r13 + 4112a2: 41 54 push %r12 + 4112a4: 49 89 fc mov %rdi,%r12 + 4112a7: 55 push %rbp + 4112a8: 53 push %rbx + 4112a9: bf 64 00 00 00 mov $0x64,%edi + 4112ae: 48 89 f5 mov %rsi,%rbp + 4112b1: 49 89 d5 mov %rdx,%r13 + 4112b4: 48 81 ec f8 00 00 00 sub $0xf8,%rsp + 4112bb: e8 50 c7 00 00 callq 41da10 <__libc_malloc> + 4112c0: 48 85 c0 test %rax,%rax + 4112c3: 0f 84 17 01 00 00 je 4113e0 <_IO_vasprintf+0x140> + 4112c9: 48 89 c3 mov %rax,%rbx + 4112cc: 45 31 c0 xor %r8d,%r8d + 4112cf: 31 c9 xor %ecx,%ecx + 4112d1: ba ff ff ff ff mov $0xffffffff,%edx + 4112d6: be 00 80 00 00 mov $0x8000,%esi + 4112db: 48 89 e7 mov %rsp,%rdi + 4112de: 48 c7 84 24 88 00 00 movq $0x0,0x88(%rsp) + 4112e5: 00 00 00 00 00 + 4112ea: e8 d1 41 00 00 callq 4154c0 <_IO_no_init> + 4112ef: 48 89 d9 mov %rbx,%rcx + 4112f2: 48 89 de mov %rbx,%rsi + 4112f5: ba 64 00 00 00 mov $0x64,%edx + 4112fa: 48 89 e7 mov %rsp,%rdi + 4112fd: 48 c7 84 24 d8 00 00 movq $0x4a1f00,0xd8(%rsp) + 411304: 00 00 1f 4a 00 + 411309: e8 32 59 00 00 callq 416c40 <_IO_str_init_static_internal> + 41130e: 4c 89 ea mov %r13,%rdx + 411311: 48 89 ee mov %rbp,%rsi + 411314: 48 89 e7 mov %rsp,%rdi + 411317: 83 24 24 fe andl $0xfffffffe,(%rsp) + 41131b: 48 c7 84 24 e0 00 00 movq $0x41da10,0xe0(%rsp) + 411322: 00 10 da 41 00 + 411327: 48 c7 84 24 e8 00 00 movq $0x41ddb0,0xe8(%rsp) + 41132e: 00 b0 dd 41 00 + 411333: e8 98 35 04 00 callq 4548d0 <_IO_vfprintf> + 411338: 85 c0 test %eax,%eax + 41133a: 89 c3 mov %eax,%ebx + 41133c: 0f 88 8e 00 00 00 js 4113d0 <_IO_vasprintf+0x130> + 411342: 48 8b 44 24 20 mov 0x20(%rsp),%rax + 411347: 48 8b 6c 24 28 mov 0x28(%rsp),%rbp + 41134c: 48 8b 54 24 30 mov 0x30(%rsp),%rdx + 411351: 48 29 c5 sub %rax,%rbp + 411354: 48 29 c2 sub %rax,%rdx + 411357: 4c 8d 6d 01 lea 0x1(%rbp),%r13 + 41135b: 48 d1 ea shr %rdx + 41135e: 49 39 d5 cmp %rdx,%r13 + 411361: 72 2d jb 411390 <_IO_vasprintf+0xf0> + 411363: 48 8b 7c 24 38 mov 0x38(%rsp),%rdi + 411368: 4c 89 ee mov %r13,%rsi + 41136b: e8 00 cc 00 00 callq 41df70 <__libc_realloc> + 411370: 48 85 c0 test %rax,%rax + 411373: 49 89 04 24 mov %rax,(%r12) + 411377: 74 4c je 4113c5 <_IO_vasprintf+0x125> + 411379: c6 04 28 00 movb $0x0,(%rax,%rbp,1) + 41137d: 89 d8 mov %ebx,%eax + 41137f: 48 81 c4 f8 00 00 00 add $0xf8,%rsp + 411386: 5b pop %rbx + 411387: 5d pop %rbp + 411388: 41 5c pop %r12 + 41138a: 41 5d pop %r13 + 41138c: c3 retq + 41138d: 0f 1f 00 nopl (%rax) + 411390: 4c 89 ef mov %r13,%rdi + 411393: e8 78 c6 00 00 callq 41da10 <__libc_malloc> + 411398: 48 85 c0 test %rax,%rax + 41139b: 49 89 04 24 mov %rax,(%r12) + 41139f: 74 c2 je 411363 <_IO_vasprintf+0xc3> + 4113a1: 4c 8b 6c 24 38 mov 0x38(%rsp),%r13 + 4113a6: 48 89 ea mov %rbp,%rdx + 4113a9: 48 89 c7 mov %rax,%rdi + 4113ac: 4c 89 ee mov %r13,%rsi + 4113af: e8 6c ac 01 00 callq 42c020 + 4113b4: 4c 89 ef mov %r13,%rdi + 4113b7: e8 f4 c9 00 00 callq 41ddb0 <__cfree> + 4113bc: 49 8b 04 24 mov (%r12),%rax + 4113c0: 48 85 c0 test %rax,%rax + 4113c3: 75 b4 jne 411379 <_IO_vasprintf+0xd9> + 4113c5: 48 8b 44 24 38 mov 0x38(%rsp),%rax + 4113ca: 49 89 04 24 mov %rax,(%r12) + 4113ce: eb a9 jmp 411379 <_IO_vasprintf+0xd9> + 4113d0: 48 8b 7c 24 38 mov 0x38(%rsp),%rdi + 4113d5: e8 d6 c9 00 00 callq 41ddb0 <__cfree> + 4113da: 89 d8 mov %ebx,%eax + 4113dc: eb a1 jmp 41137f <_IO_vasprintf+0xdf> + 4113de: 66 90 xchg %ax,%ax + 4113e0: b8 ff ff ff ff mov $0xffffffff,%eax + 4113e5: eb 98 jmp 41137f <_IO_vasprintf+0xdf> + 4113e7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 4113ee: 00 00 + +00000000004113f0 <__fcloseall>: + 4113f0: e9 fb 2d 00 00 jmpq 4141f0 <_IO_cleanup> + 4113f5: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4113fc: 00 00 00 + 4113ff: 90 nop + +0000000000411400 <__libc_message.constprop.0>: + 411400: 55 push %rbp + 411401: bf 14 1c 4a 00 mov $0x4a1c14,%edi + 411406: 48 89 e5 mov %rsp,%rbp + 411409: 41 57 push %r15 + 41140b: 41 56 push %r14 + 41140d: 48 8d 45 10 lea 0x10(%rbp),%rax + 411411: 41 55 push %r13 + 411413: 41 54 push %r12 + 411415: 53 push %rbx + 411416: 48 83 ec 58 sub $0x58,%rsp + 41141a: 48 89 45 90 mov %rax,-0x70(%rbp) + 41141e: 48 8d 45 a0 lea -0x60(%rbp),%rax + 411422: 48 89 55 b0 mov %rdx,-0x50(%rbp) + 411426: 48 89 4d b8 mov %rcx,-0x48(%rbp) + 41142a: 4c 89 45 c0 mov %r8,-0x40(%rbp) + 41142e: 4c 89 4d c8 mov %r9,-0x38(%rbp) + 411432: c7 45 88 10 00 00 00 movl $0x10,-0x78(%rbp) + 411439: 48 89 45 98 mov %rax,-0x68(%rbp) + 41143d: e8 5e 05 04 00 callq 4519a0 <__libc_secure_getenv> + 411442: 48 85 c0 test %rax,%rax + 411445: 74 09 je 411450 <__libc_message.constprop.0+0x50> + 411447: 80 38 00 cmpb $0x0,(%rax) + 41144a: 0f 85 26 01 00 00 jne 411576 <__libc_message.constprop.0+0x176> + 411450: be 02 09 00 00 mov $0x902,%esi + 411455: bf 27 1c 4a 00 mov $0x4a1c27,%edi + 41145a: b8 02 00 00 00 mov $0x2,%eax + 41145f: 0f 05 syscall + 411461: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 411467: 0f 87 2b 01 00 00 ja 411598 <__libc_message.constprop.0+0x198> + 41146d: 83 f8 ff cmp $0xffffffff,%eax + 411470: 41 89 c5 mov %eax,%r13d + 411473: 0f 84 fd 00 00 00 je 411576 <__libc_message.constprop.0+0x176> + 411479: 4c 63 e0 movslq %eax,%r12 + 41147c: 8b 45 88 mov -0x78(%rbp),%eax + 41147f: 83 f8 2f cmp $0x2f,%eax + 411482: 0f 87 ff 00 00 00 ja 411587 <__libc_message.constprop.0+0x187> + 411488: 89 c2 mov %eax,%edx + 41148a: 48 03 55 98 add -0x68(%rbp),%rdx + 41148e: 83 c0 08 add $0x8,%eax + 411491: 89 45 88 mov %eax,-0x78(%rbp) + 411494: 4c 8b 32 mov (%rdx),%r14 + 411497: 4c 89 f7 mov %r14,%rdi + 41149a: e8 b1 21 01 00 callq 423650 + 41149f: 48 83 ec 30 sub $0x30,%rsp + 4114a3: 49 89 c0 mov %rax,%r8 + 4114a6: 41 b9 14 00 00 00 mov $0x14,%r9d + 4114ac: 48 8d 44 24 0f lea 0xf(%rsp),%rax + 4114b1: 48 83 ec 20 sub $0x20,%rsp + 4114b5: 48 8d 5c 24 0f lea 0xf(%rsp),%rbx + 4114ba: 48 83 e0 f0 and $0xfffffffffffffff0,%rax + 4114be: 48 83 e3 f0 and $0xfffffffffffffff0,%rbx + 4114c2: 4c 89 30 mov %r14,(%rax) + 4114c5: 4c 89 40 08 mov %r8,0x8(%rax) + 4114c9: 48 c7 40 10 00 00 00 movq $0x0,0x10(%rax) + 4114d0: 00 + 4114d1: 4c 89 33 mov %r14,(%rbx) + 4114d4: 4c 89 43 08 mov %r8,0x8(%rbx) + 4114d8: ba 01 00 00 00 mov $0x1,%edx + 4114dd: 48 89 de mov %rbx,%rsi + 4114e0: 4c 89 e7 mov %r12,%rdi + 4114e3: 44 89 c8 mov %r9d,%eax + 4114e6: 0f 05 syscall + 4114e8: 48 83 f8 fc cmp $0xfffffffffffffffc,%rax + 4114ec: 74 ea je 4114d8 <__libc_message.constprop.0+0xd8> + 4114ee: 4c 8b 3d 8b 9c 2b 00 mov 0x2b9c8b(%rip),%r15 # 6cb180 <_dl_pagesize> + 4114f5: 49 39 c0 cmp %rax,%r8 + 4114f8: b9 22 00 00 00 mov $0x22,%ecx + 4114fd: 41 0f 94 c4 sete %r12b + 411501: ba 03 00 00 00 mov $0x3,%edx + 411506: 45 31 c9 xor %r9d,%r9d + 411509: 31 ff xor %edi,%edi + 41150b: 4b 8d 04 38 lea (%r8,%r15,1),%rax + 41150f: 49 f7 df neg %r15 + 411512: 41 83 c8 ff or $0xffffffff,%r8d + 411516: 49 21 c7 and %rax,%r15 + 411519: 4c 89 fe mov %r15,%rsi + 41151c: e8 cf e6 02 00 callq 43fbf0 <__mmap> + 411521: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 411525: 49 89 c6 mov %rax,%r14 + 411528: 74 36 je 411560 <__libc_message.constprop.0+0x160> + 41152a: 48 8b 53 08 mov 0x8(%rbx),%rdx + 41152e: 48 8b 33 mov (%rbx),%rsi + 411531: 48 8d 78 04 lea 0x4(%rax),%rdi + 411535: 44 89 38 mov %r15d,(%rax) + 411538: e8 83 50 01 00 callq 4265c0 <__mempcpy> + 41153d: 4c 89 f7 mov %r14,%rdi + 411540: c6 00 00 movb $0x0,(%rax) + 411543: 48 87 3d d6 ab 2b 00 xchg %rdi,0x2babd6(%rip) # 6cc120 <__abort_msg> + 41154a: 48 85 ff test %rdi,%rdi + 41154d: 74 11 je 411560 <__libc_message.constprop.0+0x160> + 41154f: 8b 37 mov (%rdi),%esi + 411551: e8 5a e7 02 00 callq 43fcb0 <__munmap> + 411556: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41155d: 00 00 00 + 411560: 41 0f b6 f4 movzbl %r12b,%esi + 411564: 44 89 ea mov %r13d,%edx + 411567: bf 01 00 00 00 mov $0x1,%edi + 41156c: e8 1f ee fe ff callq 400390 + 411571: e8 8a c6 ff ff callq 40dc00 + 411576: 41 bc 02 00 00 00 mov $0x2,%r12d + 41157c: 41 bd 02 00 00 00 mov $0x2,%r13d + 411582: e9 f5 fe ff ff jmpq 41147c <__libc_message.constprop.0+0x7c> + 411587: 48 8b 55 90 mov -0x70(%rbp),%rdx + 41158b: 48 8d 42 08 lea 0x8(%rdx),%rax + 41158f: 48 89 45 90 mov %rax,-0x70(%rbp) + 411593: e9 fc fe ff ff jmpq 411494 <__libc_message.constprop.0+0x94> + 411598: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx + 41159f: f7 d8 neg %eax + 4115a1: 41 bc 02 00 00 00 mov $0x2,%r12d + 4115a7: 41 bd 02 00 00 00 mov $0x2,%r13d + 4115ad: 64 89 02 mov %eax,%fs:(%rdx) + 4115b0: e9 c7 fe ff ff jmpq 41147c <__libc_message.constprop.0+0x7c> + 4115b5: 90 nop + 4115b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4115bd: 00 00 00 + +00000000004115c0 <__libc_message>: + 4115c0: 55 push %rbp + 4115c1: 48 89 e5 mov %rsp,%rbp + 4115c4: 41 57 push %r15 + 4115c6: 41 56 push %r14 + 4115c8: 48 8d 45 10 lea 0x10(%rbp),%rax + 4115cc: 41 55 push %r13 + 4115ce: 41 54 push %r12 + 4115d0: 53 push %rbx + 4115d1: 41 89 ff mov %edi,%r15d + 4115d4: bf 14 1c 4a 00 mov $0x4a1c14,%edi + 4115d9: 48 89 f3 mov %rsi,%rbx + 4115dc: 48 83 ec 68 sub $0x68,%rsp + 4115e0: 48 89 45 90 mov %rax,-0x70(%rbp) + 4115e4: 48 8d 45 a0 lea -0x60(%rbp),%rax + 4115e8: 48 89 55 b0 mov %rdx,-0x50(%rbp) + 4115ec: 48 89 4d b8 mov %rcx,-0x48(%rbp) + 4115f0: 4c 89 45 c0 mov %r8,-0x40(%rbp) + 4115f4: 4c 89 4d c8 mov %r9,-0x38(%rbp) + 4115f8: c7 45 88 10 00 00 00 movl $0x10,-0x78(%rbp) + 4115ff: 48 89 45 98 mov %rax,-0x68(%rbp) + 411603: e8 98 03 04 00 callq 4519a0 <__libc_secure_getenv> + 411608: 48 85 c0 test %rax,%rax + 41160b: 74 09 je 411616 <__libc_message+0x56> + 41160d: 80 38 00 cmpb $0x0,(%rax) + 411610: 0f 85 81 01 00 00 jne 411797 <__libc_message+0x1d7> + 411616: be 02 09 00 00 mov $0x902,%esi + 41161b: bf 27 1c 4a 00 mov $0x4a1c27,%edi + 411620: b8 02 00 00 00 mov $0x2,%eax + 411625: 0f 05 syscall + 411627: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 41162d: 0f 87 58 01 00 00 ja 41178b <__libc_message+0x1cb> + 411633: 83 f8 ff cmp $0xffffffff,%eax + 411636: 89 85 7c ff ff ff mov %eax,-0x84(%rbp) + 41163c: 0f 84 55 01 00 00 je 411797 <__libc_message+0x1d7> + 411642: 44 0f b6 2b movzbl (%rbx),%r13d + 411646: 45 31 e4 xor %r12d,%r12d + 411649: 45 31 f6 xor %r14d,%r14d + 41164c: 45 84 ed test %r13b,%r13b + 41164f: 0f 84 5f 01 00 00 je 4117b4 <__libc_message+0x1f4> + 411655: 0f 1f 00 nopl (%rax) + 411658: 44 89 ea mov %r13d,%edx + 41165b: 48 89 d8 mov %rbx,%rax + 41165e: eb 15 jmp 411675 <__libc_message+0xb5> + 411660: 48 8d 78 01 lea 0x1(%rax),%rdi + 411664: be 25 00 00 00 mov $0x25,%esi + 411669: e8 72 b5 01 00 callq 42cbe0 <__strchrnul> + 41166e: 0f b6 10 movzbl (%rax),%edx + 411671: 84 d2 test %dl,%dl + 411673: 74 0b je 411680 <__libc_message+0xc0> + 411675: 80 fa 25 cmp $0x25,%dl + 411678: 75 e6 jne 411660 <__libc_message+0xa0> + 41167a: 80 78 01 73 cmpb $0x73,0x1(%rax) + 41167e: 75 e0 jne 411660 <__libc_message+0xa0> + 411680: 41 80 fd 25 cmp $0x25,%r13b + 411684: 74 3a je 4116c0 <__libc_message+0x100> + 411686: 48 89 c6 mov %rax,%rsi + 411689: 48 89 d9 mov %rbx,%rcx + 41168c: 48 29 de sub %rbx,%rsi + 41168f: 48 89 c3 mov %rax,%rbx + 411692: 48 83 ec 30 sub $0x30,%rsp + 411696: 45 8d 54 24 01 lea 0x1(%r12),%r10d + 41169b: 48 8d 54 24 0f lea 0xf(%rsp),%rdx + 4116a0: 48 83 e2 f0 and $0xfffffffffffffff0,%rdx + 4116a4: 48 89 0a mov %rcx,(%rdx) + 4116a7: 48 89 72 08 mov %rsi,0x8(%rdx) + 4116ab: 4c 89 72 10 mov %r14,0x10(%rdx) + 4116af: 44 0f b6 2b movzbl (%rbx),%r13d + 4116b3: 45 84 ed test %r13b,%r13b + 4116b6: 74 48 je 411700 <__libc_message+0x140> + 4116b8: 45 89 d4 mov %r10d,%r12d + 4116bb: 49 89 d6 mov %rdx,%r14 + 4116be: eb 98 jmp 411658 <__libc_message+0x98> + 4116c0: 80 7b 01 73 cmpb $0x73,0x1(%rbx) + 4116c4: 75 c0 jne 411686 <__libc_message+0xc6> + 4116c6: 8b 45 88 mov -0x78(%rbp),%eax + 4116c9: 83 f8 2f cmp $0x2f,%eax + 4116cc: 0f 87 ee 00 00 00 ja 4117c0 <__libc_message+0x200> + 4116d2: 89 c2 mov %eax,%edx + 4116d4: 48 03 55 98 add -0x68(%rbp),%rdx + 4116d8: 83 c0 08 add $0x8,%eax + 4116db: 89 45 88 mov %eax,-0x78(%rbp) + 4116de: 48 8b 0a mov (%rdx),%rcx + 4116e1: 48 83 c3 02 add $0x2,%rbx + 4116e5: 48 89 cf mov %rcx,%rdi + 4116e8: 48 89 8d 70 ff ff ff mov %rcx,-0x90(%rbp) + 4116ef: e8 5c 1f 01 00 callq 423650 + 4116f4: 48 8b 8d 70 ff ff ff mov -0x90(%rbp),%rcx + 4116fb: 48 89 c6 mov %rax,%rsi + 4116fe: eb 92 jmp 411692 <__libc_message+0xd2> + 411700: 4d 63 c2 movslq %r10d,%r8 + 411703: 49 63 d4 movslq %r12d,%rdx + 411706: 4c 89 c0 mov %r8,%rax + 411709: 48 c1 e2 04 shl $0x4,%rdx + 41170d: 48 c1 e0 04 shl $0x4,%rax + 411711: 48 83 c0 10 add $0x10,%rax + 411715: 48 29 c4 sub %rax,%rsp + 411718: 31 c0 xor %eax,%eax + 41171a: 4c 8d 6c 24 0f lea 0xf(%rsp),%r13 + 41171f: 49 83 e5 f0 and $0xfffffffffffffff0,%r13 + 411723: 4c 01 ea add %r13,%rdx + 411726: eb 17 jmp 41173f <__libc_message+0x17f> + 411728: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 41172f: 00 + 411730: 49 8b 0e mov (%r14),%rcx + 411733: 49 8b 76 08 mov 0x8(%r14),%rsi + 411737: 48 83 ea 10 sub $0x10,%rdx + 41173b: 4d 8b 76 10 mov 0x10(%r14),%r14 + 41173f: 48 8d 1c 30 lea (%rax,%rsi,1),%rbx + 411743: 49 39 d5 cmp %rdx,%r13 + 411746: 48 89 0a mov %rcx,(%rdx) + 411749: 48 89 72 08 mov %rsi,0x8(%rdx) + 41174d: 48 89 d8 mov %rbx,%rax + 411750: 75 de jne 411730 <__libc_message+0x170> + 411752: 4c 63 b5 7c ff ff ff movslq -0x84(%rbp),%r14 + 411759: 41 b9 14 00 00 00 mov $0x14,%r9d + 41175f: 90 nop + 411760: 4c 89 c2 mov %r8,%rdx + 411763: 4c 89 ee mov %r13,%rsi + 411766: 4c 89 f7 mov %r14,%rdi + 411769: 44 89 c8 mov %r9d,%eax + 41176c: 0f 05 syscall + 41176e: 48 83 f8 fc cmp $0xfffffffffffffffc,%rax + 411772: 49 89 c4 mov %rax,%r12 + 411775: 74 e9 je 411760 <__libc_message+0x1a0> + 411777: 45 85 ff test %r15d,%r15d + 41177a: 75 55 jne 4117d1 <__libc_message+0x211> + 41177c: 48 8d 65 d8 lea -0x28(%rbp),%rsp + 411780: 5b pop %rbx + 411781: 41 5c pop %r12 + 411783: 41 5d pop %r13 + 411785: 41 5e pop %r14 + 411787: 41 5f pop %r15 + 411789: 5d pop %rbp + 41178a: c3 retq + 41178b: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx + 411792: f7 d8 neg %eax + 411794: 64 89 02 mov %eax,%fs:(%rdx) + 411797: 44 0f b6 2b movzbl (%rbx),%r13d + 41179b: 45 31 e4 xor %r12d,%r12d + 41179e: 45 31 f6 xor %r14d,%r14d + 4117a1: c7 85 7c ff ff ff 02 movl $0x2,-0x84(%rbp) + 4117a8: 00 00 00 + 4117ab: 45 84 ed test %r13b,%r13b + 4117ae: 0f 85 a4 fe ff ff jne 411658 <__libc_message+0x98> + 4117b4: 45 85 ff test %r15d,%r15d + 4117b7: 74 c3 je 41177c <__libc_message+0x1bc> + 4117b9: 31 f6 xor %esi,%esi + 4117bb: e9 b3 00 00 00 jmpq 411873 <__libc_message+0x2b3> + 4117c0: 48 8b 55 90 mov -0x70(%rbp),%rdx + 4117c4: 48 8d 42 08 lea 0x8(%rdx),%rax + 4117c8: 48 89 45 90 mov %rax,-0x70(%rbp) + 4117cc: e9 0d ff ff ff jmpq 4116de <__libc_message+0x11e> + 4117d1: 48 8b 05 a8 99 2b 00 mov 0x2b99a8(%rip),%rax # 6cb180 <_dl_pagesize> + 4117d8: 45 31 c9 xor %r9d,%r9d + 4117db: 31 ff xor %edi,%edi + 4117dd: 41 b8 ff ff ff ff mov $0xffffffff,%r8d + 4117e3: b9 22 00 00 00 mov $0x22,%ecx + 4117e8: ba 03 00 00 00 mov $0x3,%edx + 4117ed: 44 89 95 78 ff ff ff mov %r10d,-0x88(%rbp) + 4117f4: 4c 8d 1c 03 lea (%rbx,%rax,1),%r11 + 4117f8: 48 f7 d8 neg %rax + 4117fb: 49 21 c3 and %rax,%r11 + 4117fe: 4c 89 de mov %r11,%rsi + 411801: 4d 89 de mov %r11,%r14 + 411804: e8 e7 e3 02 00 callq 43fbf0 <__mmap> + 411809: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 41180d: 48 89 85 70 ff ff ff mov %rax,-0x90(%rbp) + 411814: 74 54 je 41186a <__libc_message+0x2aa> + 411816: 44 8b 95 78 ff ff ff mov -0x88(%rbp),%r10d + 41181d: 44 89 30 mov %r14d,(%rax) + 411820: 4d 8d 75 08 lea 0x8(%r13),%r14 + 411824: 48 83 c0 04 add $0x4,%rax + 411828: 41 8d 52 ff lea -0x1(%r10),%edx + 41182c: 48 c1 e2 04 shl $0x4,%rdx + 411830: 4d 8d 6c 15 18 lea 0x18(%r13,%rdx,1),%r13 + 411835: 49 8b 76 f8 mov -0x8(%r14),%rsi + 411839: 49 8b 16 mov (%r14),%rdx + 41183c: 48 89 c7 mov %rax,%rdi + 41183f: 49 83 c6 10 add $0x10,%r14 + 411843: e8 78 4d 01 00 callq 4265c0 <__mempcpy> + 411848: 4d 39 ee cmp %r13,%r14 + 41184b: 75 e8 jne 411835 <__libc_message+0x275> + 41184d: c6 00 00 movb $0x0,(%rax) + 411850: 48 8b bd 70 ff ff ff mov -0x90(%rbp),%rdi + 411857: 48 87 3d c2 a8 2b 00 xchg %rdi,0x2ba8c2(%rip) # 6cc120 <__abort_msg> + 41185e: 48 85 ff test %rdi,%rdi + 411861: 74 07 je 41186a <__libc_message+0x2aa> + 411863: 8b 37 mov (%rdi),%esi + 411865: e8 46 e4 02 00 callq 43fcb0 <__munmap> + 41186a: 31 f6 xor %esi,%esi + 41186c: 4c 39 e3 cmp %r12,%rbx + 41186f: 40 0f 94 c6 sete %sil + 411873: 8b 95 7c ff ff ff mov -0x84(%rbp),%edx + 411879: 44 89 ff mov %r15d,%edi + 41187c: e8 0f eb fe ff callq 400390 + 411881: e8 7a c3 ff ff callq 40dc00 + 411886: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41188d: 00 00 00 + +0000000000411890 <__libc_fatal>: + 411890: 48 89 fa mov %rdi,%rdx + 411893: 48 83 ec 08 sub $0x8,%rsp + 411897: be 99 c4 4b 00 mov $0x4bc499,%esi + 41189c: bf 01 00 00 00 mov $0x1,%edi + 4118a1: 31 c0 xor %eax,%eax + 4118a3: e8 58 fb ff ff callq 411400 <__libc_message.constprop.0> + 4118a8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 4118af: 00 + +00000000004118b0 <__fgets_unlocked>: + 4118b0: 85 f6 test %esi,%esi + 4118b2: 0f 8e 88 00 00 00 jle 411940 <__fgets_unlocked+0x90> + 4118b8: 83 fe 01 cmp $0x1,%esi + 4118bb: 41 54 push %r12 + 4118bd: 55 push %rbp + 4118be: 53 push %rbx + 4118bf: 48 89 fb mov %rdi,%rbx + 4118c2: 74 6c je 411930 <__fgets_unlocked+0x80> + 4118c4: 8b 02 mov (%rdx),%eax + 4118c6: 48 89 d5 mov %rdx,%rbp + 4118c9: 83 ee 01 sub $0x1,%esi + 4118cc: 41 b8 01 00 00 00 mov $0x1,%r8d + 4118d2: b9 0a 00 00 00 mov $0xa,%ecx + 4118d7: 41 89 c4 mov %eax,%r12d + 4118da: 83 e0 df and $0xffffffdf,%eax + 4118dd: 89 02 mov %eax,(%rdx) + 4118df: 48 63 d6 movslq %esi,%rdx + 4118e2: 48 89 fe mov %rdi,%rsi + 4118e5: 48 89 ef mov %rbp,%rdi + 4118e8: 41 83 e4 20 and $0x20,%r12d + 4118ec: e8 1f 1b 05 00 callq 463410 <_IO_getline> + 4118f1: 48 85 c0 test %rax,%rax + 4118f4: 8b 55 00 mov 0x0(%rbp),%edx + 4118f7: 75 17 jne 411910 <__fgets_unlocked+0x60> + 4118f9: 31 db xor %ebx,%ebx + 4118fb: 41 09 d4 or %edx,%r12d + 4118fe: 48 89 d8 mov %rbx,%rax + 411901: 44 89 65 00 mov %r12d,0x0(%rbp) + 411905: 5b pop %rbx + 411906: 5d pop %rbp + 411907: 41 5c pop %r12 + 411909: c3 retq + 41190a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 411910: f6 c2 20 test $0x20,%dl + 411913: 74 0d je 411922 <__fgets_unlocked+0x72> + 411915: 48 c7 c1 d0 ff ff ff mov $0xffffffffffffffd0,%rcx + 41191c: 64 83 39 0b cmpl $0xb,%fs:(%rcx) + 411920: 75 d7 jne 4118f9 <__fgets_unlocked+0x49> + 411922: c6 04 03 00 movb $0x0,(%rbx,%rax,1) + 411926: 8b 55 00 mov 0x0(%rbp),%edx + 411929: eb d0 jmp 4118fb <__fgets_unlocked+0x4b> + 41192b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 411930: c6 07 00 movb $0x0,(%rdi) + 411933: 48 89 f8 mov %rdi,%rax + 411936: eb cd jmp 411905 <__fgets_unlocked+0x55> + 411938: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 41193f: 00 + 411940: 31 c0 xor %eax,%eax + 411942: c3 retq + 411943: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41194a: 00 00 00 + 41194d: 0f 1f 00 nopl (%rax) + +0000000000411950 <_IO_file_seekoff_maybe_mmap>: + 411950: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax + 411957: 53 push %rbx + 411958: 48 89 fb mov %rdi,%rbx + 41195b: ff 90 80 00 00 00 callq *0x80(%rax) + 411961: 48 85 c0 test %rax,%rax + 411964: 78 0a js 411970 <_IO_file_seekoff_maybe_mmap+0x20> + 411966: 48 89 83 90 00 00 00 mov %rax,0x90(%rbx) + 41196d: 5b pop %rbx + 41196e: c3 retq + 41196f: 90 nop + 411970: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax + 411977: 5b pop %rbx + 411978: c3 retq + 411979: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + +0000000000411980 <_IO_file_close>: + 411980: 48 63 7f 70 movslq 0x70(%rdi),%rdi + 411984: b8 03 00 00 00 mov $0x3,%eax + 411989: 0f 05 syscall + 41198b: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 411991: 76 11 jbe 4119a4 <_IO_file_close+0x24> + 411993: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx + 41199a: f7 d8 neg %eax + 41199c: 64 89 02 mov %eax,%fs:(%rdx) + 41199f: b8 ff ff ff ff mov $0xffffffff,%eax + 4119a4: f3 c3 repz retq + 4119a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4119ad: 00 00 00 + +00000000004119b0 <_IO_new_file_setbuf>: + 4119b0: 53 push %rbx + 4119b1: 48 89 fb mov %rdi,%rbx + 4119b4: e8 37 38 00 00 callq 4151f0 <_IO_default_setbuf> + 4119b9: 48 85 c0 test %rax,%rax + 4119bc: 74 1f je 4119dd <_IO_new_file_setbuf+0x2d> + 4119be: 48 8b 43 38 mov 0x38(%rbx),%rax + 4119c2: 48 89 43 30 mov %rax,0x30(%rbx) + 4119c6: 48 89 43 28 mov %rax,0x28(%rbx) + 4119ca: 48 89 43 20 mov %rax,0x20(%rbx) + 4119ce: 48 89 43 18 mov %rax,0x18(%rbx) + 4119d2: 48 89 43 08 mov %rax,0x8(%rbx) + 4119d6: 48 89 43 10 mov %rax,0x10(%rbx) + 4119da: 48 89 d8 mov %rbx,%rax + 4119dd: 5b pop %rbx + 4119de: c3 retq + 4119df: 90 nop + +00000000004119e0 <_IO_file_setbuf_mmap>: + 4119e0: 48 8b 87 a0 00 00 00 mov 0xa0(%rdi),%rax + 4119e7: 53 push %rbx + 4119e8: 48 89 fb mov %rdi,%rbx + 4119eb: 48 c7 87 d8 00 00 00 movq $0x4a1e20,0xd8(%rdi) + 4119f2: 20 1e 4a 00 + 4119f6: 48 c7 80 30 01 00 00 movq $0x4a1b20,0x130(%rax) + 4119fd: 20 1b 4a 00 + 411a01: e8 ea 37 00 00 callq 4151f0 <_IO_default_setbuf> + 411a06: 48 85 c0 test %rax,%rax + 411a09: 74 25 je 411a30 <_IO_file_setbuf_mmap+0x50> + 411a0b: 48 8b 43 38 mov 0x38(%rbx),%rax + 411a0f: 48 89 43 30 mov %rax,0x30(%rbx) + 411a13: 48 89 43 28 mov %rax,0x28(%rbx) + 411a17: 48 89 43 20 mov %rax,0x20(%rbx) + 411a1b: 48 89 43 18 mov %rax,0x18(%rbx) + 411a1f: 48 89 43 08 mov %rax,0x8(%rbx) + 411a23: 48 89 43 10 mov %rax,0x10(%rbx) + 411a27: 48 89 d8 mov %rbx,%rax + 411a2a: 5b pop %rbx + 411a2b: c3 retq + 411a2c: 0f 1f 40 00 nopl 0x0(%rax) + 411a30: 48 8b 93 a0 00 00 00 mov 0xa0(%rbx),%rdx + 411a37: 48 c7 83 d8 00 00 00 movq $0x4a1d60,0xd8(%rbx) + 411a3e: 60 1d 4a 00 + 411a42: 48 c7 82 30 01 00 00 movq $0x4a1a60,0x130(%rdx) + 411a49: 60 1a 4a 00 + 411a4d: 5b pop %rbx + 411a4e: c3 retq + 411a4f: 90 nop + +0000000000411a50 <_IO_new_file_underflow>: + 411a50: 8b 07 mov (%rdi),%eax + 411a52: a8 04 test $0x4,%al + 411a54: 0f 85 16 02 00 00 jne 411c70 <_IO_new_file_underflow+0x220> + 411a5a: 48 8b 57 08 mov 0x8(%rdi),%rdx + 411a5e: 48 3b 57 10 cmp 0x10(%rdi),%rdx + 411a62: 0f 82 68 01 00 00 jb 411bd0 <_IO_new_file_underflow+0x180> + 411a68: 55 push %rbp + 411a69: 53 push %rbx + 411a6a: 48 89 fb mov %rdi,%rbx + 411a6d: 48 83 ec 08 sub $0x8,%rsp + 411a71: 48 83 7f 38 00 cmpq $0x0,0x38(%rdi) + 411a76: 0f 84 b4 01 00 00 je 411c30 <_IO_new_file_underflow+0x1e0> + 411a7c: a9 02 02 00 00 test $0x202,%eax + 411a81: 0f 84 d9 00 00 00 je 411b60 <_IO_new_file_underflow+0x110> + 411a87: 48 8b 2d b2 8c 2b 00 mov 0x2b8cb2(%rip),%rbp # 6ca740 <_IO_stdout> + 411a8e: 8b 55 00 mov 0x0(%rbp),%edx + 411a91: 89 d0 mov %edx,%eax + 411a93: 25 00 80 00 00 and $0x8000,%eax + 411a98: 0f 85 3a 01 00 00 jne 411bd8 <_IO_new_file_underflow+0x188> + 411a9e: 4c 8b 85 88 00 00 00 mov 0x88(%rbp),%r8 + 411aa5: 64 4c 8b 0c 25 10 00 mov %fs:0x10,%r9 + 411aac: 00 00 + 411aae: 4d 3b 48 08 cmp 0x8(%r8),%r9 + 411ab2: 0f 84 a8 01 00 00 je 411c60 <_IO_new_file_underflow+0x210> + 411ab8: be 01 00 00 00 mov $0x1,%esi + 411abd: 83 3d f8 b6 2b 00 00 cmpl $0x0,0x2bb6f8(%rip) # 6cd1bc <__libc_multiple_threads> + 411ac4: 74 09 je 411acf <_IO_new_file_underflow+0x7f> + 411ac6: f0 41 0f b1 30 lock cmpxchg %esi,(%r8) + 411acb: 75 08 jne 411ad5 <_IO_new_file_underflow+0x85> + 411acd: eb 1c jmp 411aeb <_IO_new_file_underflow+0x9b> + 411acf: 41 0f b1 30 cmpxchg %esi,(%r8) + 411ad3: 74 16 je 411aeb <_IO_new_file_underflow+0x9b> + 411ad5: 49 8d 38 lea (%r8),%rdi + 411ad8: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 411adf: e8 ec 0a 03 00 callq 4425d0 <__lll_lock_wait_private> + 411ae4: 48 81 c4 80 00 00 00 add $0x80,%rsp + 411aeb: 48 8b 3d 4e 8c 2b 00 mov 0x2b8c4e(%rip),%rdi # 6ca740 <_IO_stdout> + 411af2: 4c 8b 85 88 00 00 00 mov 0x88(%rbp),%r8 + 411af9: 8b 17 mov (%rdi),%edx + 411afb: 4d 89 48 08 mov %r9,0x8(%r8) + 411aff: 81 e2 88 02 00 00 and $0x288,%edx + 411b05: 41 83 40 04 01 addl $0x1,0x4(%r8) + 411b0a: 81 fa 80 02 00 00 cmp $0x280,%edx + 411b10: 0f 84 d7 00 00 00 je 411bed <_IO_new_file_underflow+0x19d> + 411b16: f7 45 00 00 80 00 00 testl $0x8000,0x0(%rbp) + 411b1d: 75 41 jne 411b60 <_IO_new_file_underflow+0x110> + 411b1f: 48 8b 95 88 00 00 00 mov 0x88(%rbp),%rdx + 411b26: 83 6a 04 01 subl $0x1,0x4(%rdx) + 411b2a: 75 34 jne 411b60 <_IO_new_file_underflow+0x110> + 411b2c: 48 c7 42 08 00 00 00 movq $0x0,0x8(%rdx) + 411b33: 00 + 411b34: 83 3d 81 b6 2b 00 00 cmpl $0x0,0x2bb681(%rip) # 6cd1bc <__libc_multiple_threads> + 411b3b: 74 07 je 411b44 <_IO_new_file_underflow+0xf4> + 411b3d: f0 ff 0a lock decl (%rdx) + 411b40: 75 06 jne 411b48 <_IO_new_file_underflow+0xf8> + 411b42: eb 1a jmp 411b5e <_IO_new_file_underflow+0x10e> + 411b44: ff 0a decl (%rdx) + 411b46: 74 16 je 411b5e <_IO_new_file_underflow+0x10e> + 411b48: 48 8d 3a lea (%rdx),%rdi + 411b4b: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 411b52: e8 a9 0a 03 00 callq 442600 <__lll_unlock_wake_private> + 411b57: 48 81 c4 80 00 00 00 add $0x80,%rsp + 411b5e: 66 90 xchg %ax,%ax + 411b60: 48 89 df mov %rbx,%rdi + 411b63: e8 58 2e 00 00 callq 4149c0 <_IO_switch_to_get_mode> + 411b68: 48 8b 73 38 mov 0x38(%rbx),%rsi + 411b6c: 48 8b 53 40 mov 0x40(%rbx),%rdx + 411b70: 48 89 df mov %rbx,%rdi + 411b73: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 411b7a: 48 29 f2 sub %rsi,%rdx + 411b7d: 48 89 73 08 mov %rsi,0x8(%rbx) + 411b81: 48 89 73 18 mov %rsi,0x18(%rbx) + 411b85: 48 89 73 10 mov %rsi,0x10(%rbx) + 411b89: 48 89 73 30 mov %rsi,0x30(%rbx) + 411b8d: 48 89 73 28 mov %rsi,0x28(%rbx) + 411b91: 48 89 73 20 mov %rsi,0x20(%rbx) + 411b95: ff 50 70 callq *0x70(%rax) + 411b98: 48 83 f8 00 cmp $0x0,%rax + 411b9c: 7e 6a jle 411c08 <_IO_new_file_underflow+0x1b8> + 411b9e: 48 8b 93 90 00 00 00 mov 0x90(%rbx),%rdx + 411ba5: 48 01 43 10 add %rax,0x10(%rbx) + 411ba9: 48 83 fa ff cmp $0xffffffffffffffff,%rdx + 411bad: 74 0a je 411bb9 <_IO_new_file_underflow+0x169> + 411baf: 48 01 c2 add %rax,%rdx + 411bb2: 48 89 93 90 00 00 00 mov %rdx,0x90(%rbx) + 411bb9: 48 8b 43 08 mov 0x8(%rbx),%rax + 411bbd: 0f b6 00 movzbl (%rax),%eax + 411bc0: 48 83 c4 08 add $0x8,%rsp + 411bc4: 5b pop %rbx + 411bc5: 5d pop %rbp + 411bc6: c3 retq + 411bc7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 411bce: 00 00 + 411bd0: 0f b6 02 movzbl (%rdx),%eax + 411bd3: c3 retq + 411bd4: 0f 1f 40 00 nopl 0x0(%rax) + 411bd8: 81 e2 88 02 00 00 and $0x288,%edx + 411bde: 81 fa 80 02 00 00 cmp $0x280,%edx + 411be4: 0f 85 76 ff ff ff jne 411b60 <_IO_new_file_underflow+0x110> + 411bea: 48 89 ef mov %rbp,%rdi + 411bed: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax + 411bf4: be ff ff ff ff mov $0xffffffff,%esi + 411bf9: ff 50 18 callq *0x18(%rax) + 411bfc: e9 15 ff ff ff jmpq 411b16 <_IO_new_file_underflow+0xc6> + 411c01: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 411c08: 8b 03 mov (%rbx),%eax + 411c0a: 75 4c jne 411c58 <_IO_new_file_underflow+0x208> + 411c0c: 83 c8 10 or $0x10,%eax + 411c0f: 89 03 mov %eax,(%rbx) + 411c11: 48 c7 83 90 00 00 00 movq $0xffffffffffffffff,0x90(%rbx) + 411c18: ff ff ff ff + 411c1c: 48 83 c4 08 add $0x8,%rsp + 411c20: b8 ff ff ff ff mov $0xffffffff,%eax + 411c25: 5b pop %rbx + 411c26: 5d pop %rbp + 411c27: c3 retq + 411c28: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 411c2f: 00 + 411c30: 48 8b 7f 48 mov 0x48(%rdi),%rdi + 411c34: 48 85 ff test %rdi,%rdi + 411c37: 74 0b je 411c44 <_IO_new_file_underflow+0x1f4> + 411c39: e8 72 c1 00 00 callq 41ddb0 <__cfree> + 411c3e: 81 23 ff fe ff ff andl $0xfffffeff,(%rbx) + 411c44: 48 89 df mov %rbx,%rdi + 411c47: e8 b4 31 00 00 callq 414e00 <_IO_doallocbuf> + 411c4c: 8b 03 mov (%rbx),%eax + 411c4e: e9 29 fe ff ff jmpq 411a7c <_IO_new_file_underflow+0x2c> + 411c53: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 411c58: 83 c8 20 or $0x20,%eax + 411c5b: eb b2 jmp 411c0f <_IO_new_file_underflow+0x1bf> + 411c5d: 0f 1f 00 nopl (%rax) + 411c60: 48 89 ef mov %rbp,%rdi + 411c63: e9 97 fe ff ff jmpq 411aff <_IO_new_file_underflow+0xaf> + 411c68: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 411c6f: 00 + 411c70: 83 c8 20 or $0x20,%eax + 411c73: 89 07 mov %eax,(%rdi) + 411c75: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 411c7c: 64 c7 00 09 00 00 00 movl $0x9,%fs:(%rax) + 411c83: b8 ff ff ff ff mov $0xffffffff,%eax + 411c88: c3 retq + 411c89: f7 45 00 00 80 00 00 testl $0x8000,0x0(%rbp) + 411c90: 48 89 c6 mov %rax,%rsi + 411c93: 75 3f jne 411cd4 <_IO_new_file_underflow+0x284> + 411c95: 48 8b 95 88 00 00 00 mov 0x88(%rbp),%rdx + 411c9c: 83 6a 04 01 subl $0x1,0x4(%rdx) + 411ca0: 75 32 jne 411cd4 <_IO_new_file_underflow+0x284> + 411ca2: 48 c7 42 08 00 00 00 movq $0x0,0x8(%rdx) + 411ca9: 00 + 411caa: 83 3d 0b b5 2b 00 00 cmpl $0x0,0x2bb50b(%rip) # 6cd1bc <__libc_multiple_threads> + 411cb1: 74 07 je 411cba <_IO_new_file_underflow+0x26a> + 411cb3: f0 ff 0a lock decl (%rdx) + 411cb6: 75 06 jne 411cbe <_IO_new_file_underflow+0x26e> + 411cb8: eb 1a jmp 411cd4 <_IO_new_file_underflow+0x284> + 411cba: ff 0a decl (%rdx) + 411cbc: 74 16 je 411cd4 <_IO_new_file_underflow+0x284> + 411cbe: 48 8d 3a lea (%rdx),%rdi + 411cc1: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 411cc8: e8 33 09 03 00 callq 442600 <__lll_unlock_wake_private> + 411ccd: 48 81 c4 80 00 00 00 add $0x80,%rsp + 411cd4: 48 89 f7 mov %rsi,%rdi + 411cd7: e8 94 a8 08 00 callq 49c570 <_Unwind_Resume> + 411cdc: 0f 1f 40 00 nopl 0x0(%rax) + +0000000000411ce0 <_IO_new_file_seekoff>: + 411ce0: 41 56 push %r14 + 411ce2: 41 55 push %r13 + 411ce4: 41 54 push %r12 + 411ce6: 55 push %rbp + 411ce7: 53 push %rbx + 411ce8: 48 89 fb mov %rdi,%rbx + 411ceb: 48 81 ec 90 00 00 00 sub $0x90,%rsp + 411cf2: 85 c9 test %ecx,%ecx + 411cf4: 0f 84 d6 02 00 00 je 411fd0 <_IO_new_file_seekoff+0x2f0> + 411cfa: 48 8b 47 10 mov 0x10(%rdi),%rax + 411cfe: 48 39 47 18 cmp %rax,0x18(%rdi) + 411d02: 48 89 f5 mov %rsi,%rbp + 411d05: 41 89 d4 mov %edx,%r12d + 411d08: 0f 84 ca 00 00 00 je 411dd8 <_IO_new_file_seekoff+0xf8> + 411d0e: 48 8b 57 28 mov 0x28(%rdi),%rdx + 411d12: 48 8b 47 20 mov 0x20(%rdi),%rax + 411d16: 45 31 ed xor %r13d,%r13d + 411d19: 48 39 c2 cmp %rax,%rdx + 411d1c: 0f 86 ce 00 00 00 jbe 411df0 <_IO_new_file_seekoff+0x110> + 411d22: 48 89 df mov %rbx,%rdi + 411d25: e8 96 2c 00 00 callq 4149c0 <_IO_switch_to_get_mode> + 411d2a: 85 c0 test %eax,%eax + 411d2c: 0f 85 06 03 00 00 jne 412038 <_IO_new_file_seekoff+0x358> + 411d32: 48 83 7b 38 00 cmpq $0x0,0x38(%rbx) + 411d37: 0f 84 ca 00 00 00 je 411e07 <_IO_new_file_seekoff+0x127> + 411d3d: 41 83 fc 01 cmp $0x1,%r12d + 411d41: 0f 84 09 01 00 00 je 411e50 <_IO_new_file_seekoff+0x170> + 411d47: 41 83 fc 02 cmp $0x2,%r12d + 411d4b: 0f 85 bf 01 00 00 jne 411f10 <_IO_new_file_seekoff+0x230> + 411d51: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 411d58: 48 89 e6 mov %rsp,%rsi + 411d5b: 48 89 df mov %rbx,%rdi + 411d5e: ff 90 90 00 00 00 callq *0x90(%rax) + 411d64: 85 c0 test %eax,%eax + 411d66: 0f 84 84 01 00 00 je 411ef0 <_IO_new_file_seekoff+0x210> + 411d6c: 48 89 df mov %rbx,%rdi + 411d6f: e8 2c 46 00 00 callq 4163a0 <_IO_unsave_markers> + 411d74: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 411d7b: 48 89 ee mov %rbp,%rsi + 411d7e: 48 c7 c5 ff ff ff ff mov $0xffffffffffffffff,%rbp + 411d85: 44 89 e2 mov %r12d,%edx + 411d88: 48 89 df mov %rbx,%rdi + 411d8b: ff 90 80 00 00 00 callq *0x80(%rax) + 411d91: 48 39 e8 cmp %rbp,%rax + 411d94: 74 29 je 411dbf <_IO_new_file_seekoff+0xdf> + 411d96: 48 8b 53 38 mov 0x38(%rbx),%rdx + 411d9a: 83 23 ef andl $0xffffffef,(%rbx) + 411d9d: 48 89 c5 mov %rax,%rbp + 411da0: 48 89 83 90 00 00 00 mov %rax,0x90(%rbx) + 411da7: 48 89 53 18 mov %rdx,0x18(%rbx) + 411dab: 48 89 53 08 mov %rdx,0x8(%rbx) + 411daf: 48 89 53 10 mov %rdx,0x10(%rbx) + 411db3: 48 89 53 28 mov %rdx,0x28(%rbx) + 411db7: 48 89 53 20 mov %rdx,0x20(%rbx) + 411dbb: 48 89 53 30 mov %rdx,0x30(%rbx) + 411dbf: 48 81 c4 90 00 00 00 add $0x90,%rsp + 411dc6: 48 89 e8 mov %rbp,%rax + 411dc9: 5b pop %rbx + 411dca: 5d pop %rbp + 411dcb: 41 5c pop %r12 + 411dcd: 41 5d pop %r13 + 411dcf: 41 5e pop %r14 + 411dd1: c3 retq + 411dd2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 411dd8: 48 8b 47 20 mov 0x20(%rdi),%rax + 411ddc: 48 8b 57 28 mov 0x28(%rdi),%rdx + 411de0: 48 39 d0 cmp %rdx,%rax + 411de3: 0f 85 2d ff ff ff jne 411d16 <_IO_new_file_seekoff+0x36> + 411de9: 41 bd 01 00 00 00 mov $0x1,%r13d + 411def: 90 nop + 411df0: f7 03 00 08 00 00 testl $0x800,(%rbx) + 411df6: 0f 85 26 ff ff ff jne 411d22 <_IO_new_file_seekoff+0x42> + 411dfc: 48 83 7b 38 00 cmpq $0x0,0x38(%rbx) + 411e01: 0f 85 36 ff ff ff jne 411d3d <_IO_new_file_seekoff+0x5d> + 411e07: 48 8b 7b 18 mov 0x18(%rbx),%rdi + 411e0b: 48 85 ff test %rdi,%rdi + 411e0e: 74 0b je 411e1b <_IO_new_file_seekoff+0x13b> + 411e10: e8 9b bf 00 00 callq 41ddb0 <__cfree> + 411e15: 81 23 ff fe ff ff andl $0xfffffeff,(%rbx) + 411e1b: 48 89 df mov %rbx,%rdi + 411e1e: e8 dd 2f 00 00 callq 414e00 <_IO_doallocbuf> + 411e23: 48 8b 43 38 mov 0x38(%rbx),%rax + 411e27: 41 83 fc 01 cmp $0x1,%r12d + 411e2b: 48 89 43 28 mov %rax,0x28(%rbx) + 411e2f: 48 89 43 20 mov %rax,0x20(%rbx) + 411e33: 48 89 43 30 mov %rax,0x30(%rbx) + 411e37: 48 89 43 18 mov %rax,0x18(%rbx) + 411e3b: 48 89 43 08 mov %rax,0x8(%rbx) + 411e3f: 48 89 43 10 mov %rax,0x10(%rbx) + 411e43: 0f 85 fe fe ff ff jne 411d47 <_IO_new_file_seekoff+0x67> + 411e49: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 411e50: 48 8b 43 10 mov 0x10(%rbx),%rax + 411e54: 48 2b 43 08 sub 0x8(%rbx),%rax + 411e58: 48 8b b3 90 00 00 00 mov 0x90(%rbx),%rsi + 411e5f: 48 29 c5 sub %rax,%rbp + 411e62: 48 83 fe ff cmp $0xffffffffffffffff,%rsi + 411e66: 0f 84 00 ff ff ff je 411d6c <_IO_new_file_seekoff+0x8c> + 411e6c: 48 01 f5 add %rsi,%rbp + 411e6f: 0f 88 ae 01 00 00 js 412023 <_IO_new_file_seekoff+0x343> + 411e75: 45 31 e4 xor %r12d,%r12d + 411e78: 48 83 7b 18 00 cmpq $0x0,0x18(%rbx) + 411e7d: 8b 03 mov (%rbx),%eax + 411e7f: 0f 84 9e 00 00 00 je 411f23 <_IO_new_file_seekoff+0x243> + 411e85: f6 c4 01 test $0x1,%ah + 411e88: 0f 85 95 00 00 00 jne 411f23 <_IO_new_file_seekoff+0x243> + 411e8e: 48 8b 53 38 mov 0x38(%rbx),%rdx + 411e92: 48 89 d1 mov %rdx,%rcx + 411e95: 48 2b 4b 10 sub 0x10(%rbx),%rcx + 411e99: 48 01 f1 add %rsi,%rcx + 411e9c: 48 39 e9 cmp %rbp,%rcx + 411e9f: 0f 8f 7e 00 00 00 jg 411f23 <_IO_new_file_seekoff+0x243> + 411ea5: 48 39 f5 cmp %rsi,%rbp + 411ea8: 7d 79 jge 411f23 <_IO_new_file_seekoff+0x243> + 411eaa: 48 89 ef mov %rbp,%rdi + 411ead: 83 e0 ef and $0xffffffef,%eax + 411eb0: 48 89 53 18 mov %rdx,0x18(%rbx) + 411eb4: 48 29 cf sub %rcx,%rdi + 411eb7: 48 89 53 28 mov %rdx,0x28(%rbx) + 411ebb: 48 89 53 20 mov %rdx,0x20(%rbx) + 411ebf: 48 89 f9 mov %rdi,%rcx + 411ec2: 48 89 53 30 mov %rdx,0x30(%rbx) + 411ec6: 89 03 mov %eax,(%rbx) + 411ec8: 48 01 d1 add %rdx,%rcx + 411ecb: 48 85 f6 test %rsi,%rsi + 411ece: 48 89 4b 08 mov %rcx,0x8(%rbx) + 411ed2: 0f 88 e7 fe ff ff js 411dbf <_IO_new_file_seekoff+0xdf> + 411ed8: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 411edf: 31 d2 xor %edx,%edx + 411ee1: 48 89 df mov %rbx,%rdi + 411ee4: ff 90 80 00 00 00 callq *0x80(%rax) + 411eea: e9 d0 fe ff ff jmpq 411dbf <_IO_new_file_seekoff+0xdf> + 411eef: 90 nop + 411ef0: 8b 44 24 18 mov 0x18(%rsp),%eax + 411ef4: 25 00 f0 00 00 and $0xf000,%eax + 411ef9: 3d 00 80 00 00 cmp $0x8000,%eax + 411efe: 0f 85 68 fe ff ff jne 411d6c <_IO_new_file_seekoff+0x8c> + 411f04: 48 03 6c 24 30 add 0x30(%rsp),%rbp + 411f09: 45 31 e4 xor %r12d,%r12d + 411f0c: 0f 1f 40 00 nopl 0x0(%rax) + 411f10: 48 8b b3 90 00 00 00 mov 0x90(%rbx),%rsi + 411f17: 48 83 fe ff cmp $0xffffffffffffffff,%rsi + 411f1b: 0f 85 57 ff ff ff jne 411e78 <_IO_new_file_seekoff+0x198> + 411f21: 8b 03 mov (%rbx),%eax + 411f23: a8 04 test $0x4,%al + 411f25: 0f 85 41 fe ff ff jne 411d6c <_IO_new_file_seekoff+0x8c> + 411f2b: 48 8b 53 38 mov 0x38(%rbx),%rdx + 411f2f: 48 8b 43 40 mov 0x40(%rbx),%rax + 411f33: 49 89 ec mov %rbp,%r12 + 411f36: 48 89 d6 mov %rdx,%rsi + 411f39: 48 29 c6 sub %rax,%rsi + 411f3c: 48 29 d0 sub %rdx,%rax + 411f3f: ba 00 00 00 00 mov $0x0,%edx + 411f44: 48 21 ee and %rbp,%rsi + 411f47: 49 29 f4 sub %rsi,%r12 + 411f4a: 49 39 c4 cmp %rax,%r12 + 411f4d: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 411f54: 0f 8f ee 00 00 00 jg 412048 <_IO_new_file_seekoff+0x368> + 411f5a: 48 89 df mov %rbx,%rdi + 411f5d: ff 90 80 00 00 00 callq *0x80(%rax) + 411f63: 48 85 c0 test %rax,%rax + 411f66: 49 89 c6 mov %rax,%r14 + 411f69: 0f 88 c9 00 00 00 js 412038 <_IO_new_file_seekoff+0x358> + 411f6f: 4d 85 e4 test %r12,%r12 + 411f72: 0f 84 e4 00 00 00 je 41205c <_IO_new_file_seekoff+0x37c> + 411f78: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 411f7f: 45 85 ed test %r13d,%r13d + 411f82: 48 8b 73 38 mov 0x38(%rbx),%rsi + 411f86: 4c 89 e2 mov %r12,%rdx + 411f89: 48 8b 40 70 mov 0x70(%rax),%rax + 411f8d: 75 07 jne 411f96 <_IO_new_file_seekoff+0x2b6> + 411f8f: 48 8b 53 40 mov 0x40(%rbx),%rdx + 411f93: 48 29 f2 sub %rsi,%rdx + 411f96: 48 89 df mov %rbx,%rdi + 411f99: ff d0 callq *%rax + 411f9b: 49 39 c4 cmp %rax,%r12 + 411f9e: 48 89 c1 mov %rax,%rcx + 411fa1: 0f 8e bc 00 00 00 jle 412063 <_IO_new_file_seekoff+0x383> + 411fa7: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 411fab: 4c 89 e5 mov %r12,%rbp + 411fae: 41 bc 01 00 00 00 mov $0x1,%r12d + 411fb4: 0f 84 b2 fd ff ff je 411d6c <_IO_new_file_seekoff+0x8c> + 411fba: 48 29 c5 sub %rax,%rbp + 411fbd: 41 bc 01 00 00 00 mov $0x1,%r12d + 411fc3: e9 a4 fd ff ff jmpq 411d6c <_IO_new_file_seekoff+0x8c> + 411fc8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 411fcf: 00 + 411fd0: 48 83 7f 38 00 cmpq $0x0,0x38(%rdi) + 411fd5: 0f 84 1d 01 00 00 je 4120f8 <_IO_new_file_seekoff+0x418> + 411fdb: 4c 8b 6f 28 mov 0x28(%rdi),%r13 + 411fdf: 4c 8b 67 20 mov 0x20(%rdi),%r12 + 411fe3: 8b 2f mov (%rdi),%ebp + 411fe5: 81 e5 00 10 00 00 and $0x1000,%ebp + 411feb: 4d 39 e5 cmp %r12,%r13 + 411fee: 76 08 jbe 411ff8 <_IO_new_file_seekoff+0x318> + 411ff0: 85 ed test %ebp,%ebp + 411ff2: 0f 85 c0 00 00 00 jne 4120b8 <_IO_new_file_seekoff+0x3d8> + 411ff8: 48 8b 83 90 00 00 00 mov 0x90(%rbx),%rax + 411fff: 4d 39 e5 cmp %r12,%r13 + 412002: 0f 87 98 00 00 00 ja 4120a0 <_IO_new_file_seekoff+0x3c0> + 412008: 48 8b 6b 08 mov 0x8(%rbx),%rbp + 41200c: 48 2b 6b 10 sub 0x10(%rbx),%rbp + 412010: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 412014: 0f 84 f6 00 00 00 je 412110 <_IO_new_file_seekoff+0x430> + 41201a: 48 01 c5 add %rax,%rbp + 41201d: 0f 89 9c fd ff ff jns 411dbf <_IO_new_file_seekoff+0xdf> + 412023: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 41202a: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) + 412031: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 412038: 48 c7 c5 ff ff ff ff mov $0xffffffffffffffff,%rbp + 41203f: e9 7b fd ff ff jmpq 411dbf <_IO_new_file_seekoff+0xdf> + 412044: 0f 1f 40 00 nopl 0x0(%rax) + 412048: 48 89 ee mov %rbp,%rsi + 41204b: 48 89 df mov %rbx,%rdi + 41204e: ff 90 80 00 00 00 callq *0x80(%rax) + 412054: 48 85 c0 test %rax,%rax + 412057: 49 89 c6 mov %rax,%r14 + 41205a: 78 dc js 412038 <_IO_new_file_seekoff+0x358> + 41205c: 31 c9 xor %ecx,%ecx + 41205e: 45 31 e4 xor %r12d,%r12d + 412061: 31 c0 xor %eax,%eax + 412063: 48 8b 53 38 mov 0x38(%rbx),%rdx + 412067: 4c 01 f0 add %r14,%rax + 41206a: 83 23 ef andl $0xffffffef,(%rbx) + 41206d: 48 89 83 90 00 00 00 mov %rax,0x90(%rbx) + 412074: 49 01 d4 add %rdx,%r12 + 412077: 48 01 d1 add %rdx,%rcx + 41207a: 48 89 53 18 mov %rdx,0x18(%rbx) + 41207e: 4c 89 63 08 mov %r12,0x8(%rbx) + 412082: 48 89 4b 10 mov %rcx,0x10(%rbx) + 412086: 48 89 53 28 mov %rdx,0x28(%rbx) + 41208a: 48 89 53 20 mov %rdx,0x20(%rbx) + 41208e: 48 89 53 30 mov %rdx,0x30(%rbx) + 412092: e9 28 fd ff ff jmpq 411dbf <_IO_new_file_seekoff+0xdf> + 412097: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 41209e: 00 00 + 4120a0: 85 ed test %ebp,%ebp + 4120a2: 48 8b 6b 28 mov 0x28(%rbx),%rbp + 4120a6: 74 40 je 4120e8 <_IO_new_file_seekoff+0x408> + 4120a8: 48 2b 6b 20 sub 0x20(%rbx),%rbp + 4120ac: e9 5f ff ff ff jmpq 412010 <_IO_new_file_seekoff+0x330> + 4120b1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4120b8: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax + 4120bf: 31 f6 xor %esi,%esi + 4120c1: ba 02 00 00 00 mov $0x2,%edx + 4120c6: ff 90 80 00 00 00 callq *0x80(%rax) + 4120cc: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 4120d0: 0f 84 62 ff ff ff je 412038 <_IO_new_file_seekoff+0x358> + 4120d6: 48 89 83 90 00 00 00 mov %rax,0x90(%rbx) + 4120dd: e9 1d ff ff ff jmpq 411fff <_IO_new_file_seekoff+0x31f> + 4120e2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4120e8: 48 2b 6b 10 sub 0x10(%rbx),%rbp + 4120ec: e9 1f ff ff ff jmpq 412010 <_IO_new_file_seekoff+0x330> + 4120f1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4120f8: 48 8b 87 90 00 00 00 mov 0x90(%rdi),%rax + 4120ff: 31 ed xor %ebp,%ebp + 412101: e9 0a ff ff ff jmpq 412010 <_IO_new_file_seekoff+0x330> + 412106: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41210d: 00 00 00 + 412110: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 412117: 31 f6 xor %esi,%esi + 412119: ba 01 00 00 00 mov $0x1,%edx + 41211e: 48 89 df mov %rbx,%rdi + 412121: ff 90 80 00 00 00 callq *0x80(%rax) + 412127: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 41212b: 0f 84 07 ff ff ff je 412038 <_IO_new_file_seekoff+0x358> + 412131: e9 e4 fe ff ff jmpq 41201a <_IO_new_file_seekoff+0x33a> + 412136: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41213d: 00 00 00 + +0000000000412140 <_IO_file_close_mmap>: + 412140: 53 push %rbx + 412141: 48 89 fb mov %rdi,%rbx + 412144: 48 8b 7f 38 mov 0x38(%rdi),%rdi + 412148: 48 8b 73 40 mov 0x40(%rbx),%rsi + 41214c: 48 29 fe sub %rdi,%rsi + 41214f: e8 5c db 02 00 callq 43fcb0 <__munmap> + 412154: 48 c7 43 40 00 00 00 movq $0x0,0x40(%rbx) + 41215b: 00 + 41215c: 48 c7 43 38 00 00 00 movq $0x0,0x38(%rbx) + 412163: 00 + 412164: b8 03 00 00 00 mov $0x3,%eax + 412169: 48 63 7b 70 movslq 0x70(%rbx),%rdi + 41216d: 0f 05 syscall + 41216f: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 412175: 76 11 jbe 412188 <_IO_file_close_mmap+0x48> + 412177: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx + 41217e: f7 d8 neg %eax + 412180: 64 89 02 mov %eax,%fs:(%rdx) + 412183: b8 ff ff ff ff mov $0xffffffff,%eax + 412188: 5b pop %rbx + 412189: c3 retq + 41218a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + +0000000000412190 <_IO_file_seek>: + 412190: 8b 7f 70 mov 0x70(%rdi),%edi + 412193: e9 98 03 03 00 jmpq 442530 <__libc_lseek> + 412198: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 41219f: 00 + +00000000004121a0 <_IO_file_sync_mmap>: + 4121a0: 53 push %rbx + 4121a1: 48 8b 77 08 mov 0x8(%rdi),%rsi + 4121a5: 48 89 fb mov %rdi,%rbx + 4121a8: 48 3b 77 10 cmp 0x10(%rdi),%rsi + 4121ac: 74 32 je 4121e0 <_IO_file_sync_mmap+0x40> + 4121ae: 48 2b 77 38 sub 0x38(%rdi),%rsi + 4121b2: 8b 7f 70 mov 0x70(%rdi),%edi + 4121b5: 31 d2 xor %edx,%edx + 4121b7: e8 74 03 03 00 callq 442530 <__libc_lseek> + 4121bc: 48 8b 73 08 mov 0x8(%rbx),%rsi + 4121c0: 48 2b 73 38 sub 0x38(%rbx),%rsi + 4121c4: 48 39 f0 cmp %rsi,%rax + 4121c7: 75 27 jne 4121f0 <_IO_file_sync_mmap+0x50> + 4121c9: 48 8b 43 18 mov 0x18(%rbx),%rax + 4121cd: 48 89 b3 90 00 00 00 mov %rsi,0x90(%rbx) + 4121d4: 48 89 43 08 mov %rax,0x8(%rbx) + 4121d8: 48 89 43 10 mov %rax,0x10(%rbx) + 4121dc: 31 c0 xor %eax,%eax + 4121de: 5b pop %rbx + 4121df: c3 retq + 4121e0: 48 2b 77 38 sub 0x38(%rdi),%rsi + 4121e4: eb e3 jmp 4121c9 <_IO_file_sync_mmap+0x29> + 4121e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4121ed: 00 00 00 + 4121f0: 83 0b 20 orl $0x20,(%rbx) + 4121f3: b8 ff ff ff ff mov $0xffffffff,%eax + 4121f8: 5b pop %rbx + 4121f9: c3 retq + 4121fa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + +0000000000412200 <_IO_file_xsgetn_maybe_mmap>: + 412200: 41 55 push %r13 + 412202: 41 54 push %r12 + 412204: 49 89 d4 mov %rdx,%r12 + 412207: 55 push %rbp + 412208: 53 push %rbx + 412209: 48 89 f5 mov %rsi,%rbp + 41220c: 48 89 fb mov %rdi,%rbx + 41220f: 48 81 ec 98 00 00 00 sub $0x98,%rsp + 412216: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax + 41221d: 48 89 e6 mov %rsp,%rsi + 412220: ff 90 90 00 00 00 callq *0x90(%rax) + 412226: 85 c0 test %eax,%eax + 412228: 75 10 jne 41223a <_IO_file_xsgetn_maybe_mmap+0x3a> + 41222a: 8b 44 24 18 mov 0x18(%rsp),%eax + 41222e: 25 00 f0 00 00 and $0xf000,%eax + 412233: 3d 00 80 00 00 cmp $0x8000,%eax + 412238: 74 56 je 412290 <_IO_file_xsgetn_maybe_mmap+0x90> + 41223a: 8b 83 c0 00 00 00 mov 0xc0(%rbx),%eax + 412240: ba 20 1e 4a 00 mov $0x4a1e20,%edx + 412245: 85 c0 test %eax,%eax + 412247: b8 20 1b 4a 00 mov $0x4a1b20,%eax + 41224c: 48 0f 4e c2 cmovle %rdx,%rax + 412250: 48 89 83 d8 00 00 00 mov %rax,0xd8(%rbx) + 412257: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 41225e: 48 c7 80 30 01 00 00 movq $0x4a1b20,0x130(%rax) + 412265: 20 1b 4a 00 + 412269: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 412270: 4c 89 e2 mov %r12,%rdx + 412273: 48 89 ee mov %rbp,%rsi + 412276: 48 89 df mov %rbx,%rdi + 412279: ff 50 40 callq *0x40(%rax) + 41227c: 48 81 c4 98 00 00 00 add $0x98,%rsp + 412283: 5b pop %rbx + 412284: 5d pop %rbp + 412285: 41 5c pop %r12 + 412287: 41 5d pop %r13 + 412289: c3 retq + 41228a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 412290: 48 8b 74 24 30 mov 0x30(%rsp),%rsi + 412295: 48 85 f6 test %rsi,%rsi + 412298: 74 a0 je 41223a <_IO_file_xsgetn_maybe_mmap+0x3a> + 41229a: 48 8b 83 90 00 00 00 mov 0x90(%rbx),%rax + 4122a1: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 4122a5: 74 05 je 4122ac <_IO_file_xsgetn_maybe_mmap+0xac> + 4122a7: 48 39 c6 cmp %rax,%rsi + 4122aa: 7c 8e jl 41223a <_IO_file_xsgetn_maybe_mmap+0x3a> + 4122ac: 44 8b 43 70 mov 0x70(%rbx),%r8d + 4122b0: 45 31 c9 xor %r9d,%r9d + 4122b3: 31 ff xor %edi,%edi + 4122b5: b9 01 00 00 00 mov $0x1,%ecx + 4122ba: ba 01 00 00 00 mov $0x1,%edx + 4122bf: e8 2c d9 02 00 callq 43fbf0 <__mmap> + 4122c4: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 4122c8: 49 89 c5 mov %rax,%r13 + 4122cb: 0f 84 69 ff ff ff je 41223a <_IO_file_xsgetn_maybe_mmap+0x3a> + 4122d1: 48 8b 74 24 30 mov 0x30(%rsp),%rsi + 4122d6: 8b 7b 70 mov 0x70(%rbx),%edi + 4122d9: 31 d2 xor %edx,%edx + 4122db: e8 50 02 03 00 callq 442530 <__libc_lseek> + 4122e0: 48 8b 74 24 30 mov 0x30(%rsp),%rsi + 4122e5: 48 39 f0 cmp %rsi,%rax + 4122e8: 74 18 je 412302 <_IO_file_xsgetn_maybe_mmap+0x102> + 4122ea: 4c 89 ef mov %r13,%rdi + 4122ed: e8 be d9 02 00 callq 43fcb0 <__munmap> + 4122f2: 48 c7 83 90 00 00 00 movq $0xffffffffffffffff,0x90(%rbx) + 4122f9: ff ff ff ff + 4122fd: e9 38 ff ff ff jmpq 41223a <_IO_file_xsgetn_maybe_mmap+0x3a> + 412302: 49 8d 54 05 00 lea 0x0(%r13,%rax,1),%rdx + 412307: 31 c9 xor %ecx,%ecx + 412309: 4c 89 ee mov %r13,%rsi + 41230c: 48 89 df mov %rbx,%rdi + 41230f: e8 8c 2a 00 00 callq 414da0 <_IO_setb> + 412314: 48 8b 83 90 00 00 00 mov 0x90(%rbx),%rax + 41231b: ba 00 00 00 00 mov $0x0,%edx + 412320: 4c 89 6b 18 mov %r13,0x18(%rbx) + 412324: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 412328: 48 0f 44 c2 cmove %rdx,%rax + 41232c: 8b 93 c0 00 00 00 mov 0xc0(%rbx),%edx + 412332: 4c 01 e8 add %r13,%rax + 412335: 48 89 43 08 mov %rax,0x8(%rbx) + 412339: 48 8b 44 24 30 mov 0x30(%rsp),%rax + 41233e: 49 01 c5 add %rax,%r13 + 412341: 48 89 83 90 00 00 00 mov %rax,0x90(%rbx) + 412348: 85 d2 test %edx,%edx + 41234a: b8 60 1a 4a 00 mov $0x4a1a60,%eax + 41234f: ba 60 1d 4a 00 mov $0x4a1d60,%edx + 412354: 4c 89 6b 10 mov %r13,0x10(%rbx) + 412358: 48 0f 4e c2 cmovle %rdx,%rax + 41235c: 48 89 83 d8 00 00 00 mov %rax,0xd8(%rbx) + 412363: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 41236a: 48 c7 80 30 01 00 00 movq $0x4a1a60,0x130(%rax) + 412371: 60 1a 4a 00 + 412375: e9 ef fe ff ff jmpq 412269 <_IO_file_xsgetn_maybe_mmap+0x69> + 41237a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + +0000000000412380 <_IO_file_stat>: + 412380: 48 89 f2 mov %rsi,%rdx + 412383: 8b 77 70 mov 0x70(%rdi),%esi + 412386: bf 01 00 00 00 mov $0x1,%edi + 41238b: e9 40 cd 02 00 jmpq 43f0d0 <__fxstat> + +0000000000412390 <_IO_new_file_write>: + 412390: 48 85 d2 test %rdx,%rdx + 412393: 41 56 push %r14 + 412395: 49 89 fe mov %rdi,%r14 + 412398: 41 55 push %r13 + 41239a: 41 54 push %r12 + 41239c: 55 push %rbp + 41239d: 53 push %rbx + 41239e: 0f 8e 93 00 00 00 jle 412437 <_IO_new_file_write+0xa7> + 4123a4: 48 89 f5 mov %rsi,%rbp + 4123a7: 49 89 d4 mov %rdx,%r12 + 4123aa: 48 89 d3 mov %rdx,%rbx + 4123ad: 41 bd 01 00 00 00 mov $0x1,%r13d + 4123b3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4123b8: 41 f6 46 74 02 testb $0x2,0x74(%r14) + 4123bd: 74 51 je 412410 <_IO_new_file_write+0x80> + 4123bf: 49 63 7e 70 movslq 0x70(%r14),%rdi + 4123c3: 48 89 da mov %rbx,%rdx + 4123c6: 48 89 ee mov %rbp,%rsi + 4123c9: 44 89 e8 mov %r13d,%eax + 4123cc: 0f 05 syscall + 4123ce: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 4123d4: 76 49 jbe 41241f <_IO_new_file_write+0x8f> + 4123d6: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx + 4123dd: f7 d8 neg %eax + 4123df: 64 89 02 mov %eax,%fs:(%rdx) + 4123e2: 41 83 0e 20 orl $0x20,(%r14) + 4123e6: 4c 89 e0 mov %r12,%rax + 4123e9: 48 29 d8 sub %rbx,%rax + 4123ec: 49 8b 96 90 00 00 00 mov 0x90(%r14),%rdx + 4123f3: 48 85 d2 test %rdx,%rdx + 4123f6: 78 0a js 412402 <_IO_new_file_write+0x72> + 4123f8: 48 01 c2 add %rax,%rdx + 4123fb: 49 89 96 90 00 00 00 mov %rdx,0x90(%r14) + 412402: 5b pop %rbx + 412403: 5d pop %rbp + 412404: 41 5c pop %r12 + 412406: 41 5d pop %r13 + 412408: 41 5e pop %r14 + 41240a: c3 retq + 41240b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 412410: 41 8b 7e 70 mov 0x70(%r14),%edi + 412414: 48 89 da mov %rbx,%rdx + 412417: 48 89 ee mov %rbp,%rsi + 41241a: e8 c1 cd 02 00 callq 43f1e0 <__libc_write> + 41241f: 48 85 c0 test %rax,%rax + 412422: 78 be js 4123e2 <_IO_new_file_write+0x52> + 412424: 48 29 c3 sub %rax,%rbx + 412427: 48 01 c5 add %rax,%rbp + 41242a: 48 85 db test %rbx,%rbx + 41242d: 7f 89 jg 4123b8 <_IO_new_file_write+0x28> + 41242f: 4c 89 e0 mov %r12,%rax + 412432: 48 29 d8 sub %rbx,%rax + 412435: eb b5 jmp 4123ec <_IO_new_file_write+0x5c> + 412437: 31 c0 xor %eax,%eax + 412439: eb b1 jmp 4123ec <_IO_new_file_write+0x5c> + 41243b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + +0000000000412440 <_IO_file_xsgetn_mmap>: + 412440: 41 57 push %r15 + 412442: 41 56 push %r14 + 412444: 49 89 d7 mov %rdx,%r15 + 412447: 41 55 push %r13 + 412449: 41 54 push %r12 + 41244b: 49 89 f6 mov %rsi,%r14 + 41244e: 55 push %rbp + 41244f: 53 push %rbx + 412450: 48 89 fd mov %rdi,%rbp + 412453: 49 89 f4 mov %rsi,%r12 + 412456: 48 81 ec 98 00 00 00 sub $0x98,%rsp + 41245d: 4c 8b 6f 08 mov 0x8(%rdi),%r13 + 412461: 48 8b 5f 10 mov 0x10(%rdi),%rbx + 412465: 4c 29 eb sub %r13,%rbx + 412468: 48 39 d3 cmp %rdx,%rbx + 41246b: 0f 83 80 01 00 00 jae 4125f1 <_IO_file_xsgetn_mmap+0x1b1> + 412471: f7 07 00 01 00 00 testl $0x100,(%rdi) + 412477: 0f 85 93 01 00 00 jne 412610 <_IO_file_xsgetn_mmap+0x1d0> + 41247d: 48 8b 85 d8 00 00 00 mov 0xd8(%rbp),%rax + 412484: 48 89 e6 mov %rsp,%rsi + 412487: 48 89 ef mov %rbp,%rdi + 41248a: ff 90 90 00 00 00 callq *0x90(%rax) + 412490: 85 c0 test %eax,%eax + 412492: 75 14 jne 4124a8 <_IO_file_xsgetn_mmap+0x68> + 412494: 8b 44 24 18 mov 0x18(%rsp),%eax + 412498: 25 00 f0 00 00 and $0xf000,%eax + 41249d: 3d 00 80 00 00 cmp $0x8000,%eax + 4124a2: 0f 84 88 00 00 00 je 412530 <_IO_file_xsgetn_mmap+0xf0> + 4124a8: 48 8b 7d 38 mov 0x38(%rbp),%rdi + 4124ac: 48 8b 75 40 mov 0x40(%rbp),%rsi + 4124b0: 48 29 fe sub %rdi,%rsi + 4124b3: e8 f8 d7 02 00 callq 43fcb0 <__munmap> + 4124b8: 8b 85 c0 00 00 00 mov 0xc0(%rbp),%eax + 4124be: ba 20 1e 4a 00 mov $0x4a1e20,%edx + 4124c3: 48 c7 45 40 00 00 00 movq $0x0,0x40(%rbp) + 4124ca: 00 + 4124cb: 48 c7 45 38 00 00 00 movq $0x0,0x38(%rbp) + 4124d2: 00 + 4124d3: 48 c7 45 18 00 00 00 movq $0x0,0x18(%rbp) + 4124da: 00 + 4124db: 4c 89 f6 mov %r14,%rsi + 4124de: 48 c7 45 08 00 00 00 movq $0x0,0x8(%rbp) + 4124e5: 00 + 4124e6: 48 c7 45 10 00 00 00 movq $0x0,0x10(%rbp) + 4124ed: 00 + 4124ee: 48 89 ef mov %rbp,%rdi + 4124f1: 85 c0 test %eax,%eax + 4124f3: b8 20 1b 4a 00 mov $0x4a1b20,%eax + 4124f8: 48 0f 4e c2 cmovle %rdx,%rax + 4124fc: 4d 29 f4 sub %r14,%r12 + 4124ff: 4c 89 fa mov %r15,%rdx + 412502: 48 89 85 d8 00 00 00 mov %rax,0xd8(%rbp) + 412509: 48 8b 85 a0 00 00 00 mov 0xa0(%rbp),%rax + 412510: 48 c7 80 30 01 00 00 movq $0x4a1b20,0x130(%rax) + 412517: 20 1b 4a 00 + 41251b: 48 8b 85 d8 00 00 00 mov 0xd8(%rbp),%rax + 412522: ff 50 40 callq *0x40(%rax) + 412525: 4c 01 e0 add %r12,%rax + 412528: e9 cf 00 00 00 jmpq 4125fc <_IO_file_xsgetn_mmap+0x1bc> + 41252d: 0f 1f 00 nopl (%rax) + 412530: 48 8b 5c 24 30 mov 0x30(%rsp),%rbx + 412535: 48 85 db test %rbx,%rbx + 412538: 0f 84 6a ff ff ff je 4124a8 <_IO_file_xsgetn_mmap+0x68> + 41253e: e8 4d d6 02 00 callq 43fb90 <__getpagesize> + 412543: 48 8b 7d 38 mov 0x38(%rbp),%rdi + 412547: 48 63 c8 movslq %eax,%rcx + 41254a: 48 89 ce mov %rcx,%rsi + 41254d: 48 8d 54 0b ff lea -0x1(%rbx,%rcx,1),%rdx + 412552: 48 f7 de neg %rsi + 412555: 49 89 f8 mov %rdi,%r8 + 412558: 48 21 f2 and %rsi,%rdx + 41255b: 48 89 f8 mov %rdi,%rax + 41255e: 49 f7 d0 not %r8 + 412561: 4c 03 45 40 add 0x40(%rbp),%r8 + 412565: 4c 01 c1 add %r8,%rcx + 412568: 48 21 ce and %rcx,%rsi + 41256b: 48 39 f2 cmp %rsi,%rdx + 41256e: 0f 82 01 01 00 00 jb 412675 <_IO_file_xsgetn_mmap+0x235> + 412574: 0f 87 21 01 00 00 ja 41269b <_IO_file_xsgetn_mmap+0x25b> + 41257a: 48 01 fb add %rdi,%rbx + 41257d: 48 89 5d 40 mov %rbx,0x40(%rbp) + 412581: 49 89 dd mov %rbx,%r13 + 412584: 48 8b 55 10 mov 0x10(%rbp),%rdx + 412588: 48 2b 55 08 sub 0x8(%rbp),%rdx + 41258c: 4c 89 ee mov %r13,%rsi + 41258f: 48 8b 8d 90 00 00 00 mov 0x90(%rbp),%rcx + 412596: 48 29 c6 sub %rax,%rsi + 412599: 48 89 7d 18 mov %rdi,0x18(%rbp) + 41259d: 48 29 d1 sub %rdx,%rcx + 4125a0: 48 39 f1 cmp %rsi,%rcx + 4125a3: 48 89 ca mov %rcx,%rdx + 4125a6: 48 89 8d 90 00 00 00 mov %rcx,0x90(%rbp) + 4125ad: 0f 8d ae 00 00 00 jge 412661 <_IO_file_xsgetn_mmap+0x221> + 4125b3: 48 01 fa add %rdi,%rdx + 4125b6: 8b 7d 70 mov 0x70(%rbp),%edi + 4125b9: 4c 89 6d 10 mov %r13,0x10(%rbp) + 4125bd: 48 89 55 08 mov %rdx,0x8(%rbp) + 4125c1: 31 d2 xor %edx,%edx + 4125c3: e8 68 ff 02 00 callq 442530 <__libc_lseek> + 4125c8: 48 8b 55 40 mov 0x40(%rbp),%rdx + 4125cc: 48 2b 55 38 sub 0x38(%rbp),%rdx + 4125d0: 48 39 d0 cmp %rdx,%rax + 4125d3: 0f 84 f3 00 00 00 je 4126cc <_IO_file_xsgetn_mmap+0x28c> + 4125d9: 83 4d 00 20 orl $0x20,0x0(%rbp) + 4125dd: 4c 8b 6d 08 mov 0x8(%rbp),%r13 + 4125e1: 48 8b 5d 10 mov 0x10(%rbp),%rbx + 4125e5: 4c 29 eb sub %r13,%rbx + 4125e8: 4c 39 fb cmp %r15,%rbx + 4125eb: 73 04 jae 4125f1 <_IO_file_xsgetn_mmap+0x1b1> + 4125ed: 83 4d 00 10 orl $0x10,0x0(%rbp) + 4125f1: 48 85 db test %rbx,%rbx + 4125f4: 75 4a jne 412640 <_IO_file_xsgetn_mmap+0x200> + 4125f6: 4c 89 e0 mov %r12,%rax + 4125f9: 4c 29 f0 sub %r14,%rax + 4125fc: 48 81 c4 98 00 00 00 add $0x98,%rsp + 412603: 5b pop %rbx + 412604: 5d pop %rbp + 412605: 41 5c pop %r12 + 412607: 41 5d pop %r13 + 412609: 41 5e pop %r14 + 41260b: 41 5f pop %r15 + 41260d: c3 retq + 41260e: 66 90 xchg %ax,%ax + 412610: 48 89 da mov %rbx,%rdx + 412613: 4c 89 ee mov %r13,%rsi + 412616: 4c 89 f7 mov %r14,%rdi + 412619: e8 a2 3f 01 00 callq 4265c0 <__mempcpy> + 41261e: 48 89 ef mov %rbp,%rdi + 412621: 49 29 df sub %rbx,%r15 + 412624: 49 89 c4 mov %rax,%r12 + 412627: e8 34 23 00 00 callq 414960 <_IO_switch_to_main_get_area> + 41262c: 4c 8b 6d 08 mov 0x8(%rbp),%r13 + 412630: 48 8b 5d 10 mov 0x10(%rbp),%rbx + 412634: 4c 29 eb sub %r13,%rbx + 412637: 49 39 df cmp %rbx,%r15 + 41263a: 0f 87 3d fe ff ff ja 41247d <_IO_file_xsgetn_mmap+0x3d> + 412640: 4c 39 fb cmp %r15,%rbx + 412643: 4c 89 e7 mov %r12,%rdi + 412646: 4c 89 ee mov %r13,%rsi + 412649: 49 0f 47 df cmova %r15,%rbx + 41264d: 48 89 da mov %rbx,%rdx + 412650: 4c 01 eb add %r13,%rbx + 412653: e8 68 3f 01 00 callq 4265c0 <__mempcpy> + 412658: 48 89 5d 08 mov %rbx,0x8(%rbp) + 41265c: 49 89 c4 mov %rax,%r12 + 41265f: eb 95 jmp 4125f6 <_IO_file_xsgetn_mmap+0x1b6> + 412661: 4d 85 ff test %r15,%r15 + 412664: 4c 89 6d 08 mov %r13,0x8(%rbp) + 412668: 4c 89 6d 10 mov %r13,0x10(%rbp) + 41266c: 74 88 je 4125f6 <_IO_file_xsgetn_mmap+0x1b6> + 41266e: 31 db xor %ebx,%ebx + 412670: e9 78 ff ff ff jmpq 4125ed <_IO_file_xsgetn_mmap+0x1ad> + 412675: 48 01 d7 add %rdx,%rdi + 412678: 48 29 d6 sub %rdx,%rsi + 41267b: e8 30 d6 02 00 callq 43fcb0 <__munmap> + 412680: 48 8b 7d 38 mov 0x38(%rbp),%rdi + 412684: 48 89 fb mov %rdi,%rbx + 412687: 48 03 5c 24 30 add 0x30(%rsp),%rbx + 41268c: 48 89 f8 mov %rdi,%rax + 41268f: 48 89 5d 40 mov %rbx,0x40(%rbp) + 412693: 49 89 dd mov %rbx,%r13 + 412696: e9 e9 fe ff ff jmpq 412584 <_IO_file_xsgetn_mmap+0x144> + 41269b: 31 c0 xor %eax,%eax + 41269d: b9 01 00 00 00 mov $0x1,%ecx + 4126a2: e8 a9 fe 02 00 callq 442550 <__mremap> + 4126a7: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 4126ab: 0f 84 f7 fd ff ff je 4124a8 <_IO_file_xsgetn_mmap+0x68> + 4126b1: 48 89 c3 mov %rax,%rbx + 4126b4: 48 03 5c 24 30 add 0x30(%rsp),%rbx + 4126b9: 48 89 45 38 mov %rax,0x38(%rbp) + 4126bd: 48 89 c7 mov %rax,%rdi + 4126c0: 48 89 5d 40 mov %rbx,0x40(%rbp) + 4126c4: 49 89 dd mov %rbx,%r13 + 4126c7: e9 b8 fe ff ff jmpq 412584 <_IO_file_xsgetn_mmap+0x144> + 4126cc: 48 89 85 90 00 00 00 mov %rax,0x90(%rbp) + 4126d3: e9 05 ff ff ff jmpq 4125dd <_IO_file_xsgetn_mmap+0x19d> + 4126d8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 4126df: 00 + +00000000004126e0 <_IO_file_xsgetn>: + 4126e0: 41 56 push %r14 + 4126e2: 41 55 push %r13 + 4126e4: 49 89 f6 mov %rsi,%r14 + 4126e7: 41 54 push %r12 + 4126e9: 55 push %rbp + 4126ea: 49 89 d5 mov %rdx,%r13 + 4126ed: 53 push %rbx + 4126ee: 48 83 7f 38 00 cmpq $0x0,0x38(%rdi) + 4126f3: 48 89 fb mov %rdi,%rbx + 4126f6: 0f 84 a4 01 00 00 je 4128a0 <_IO_file_xsgetn+0x1c0> + 4126fc: 4d 85 ed test %r13,%r13 + 4126ff: 4d 89 ec mov %r13,%r12 + 412702: 0f 84 c8 00 00 00 je 4127d0 <_IO_file_xsgetn+0xf0> + 412708: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 41270f: 00 + 412710: 48 8b 73 08 mov 0x8(%rbx),%rsi + 412714: 48 8b 6b 10 mov 0x10(%rbx),%rbp + 412718: 48 29 f5 sub %rsi,%rbp + 41271b: 4c 39 e5 cmp %r12,%rbp + 41271e: 0f 83 c4 00 00 00 jae 4127e8 <_IO_file_xsgetn+0x108> + 412724: 48 85 ed test %rbp,%rbp + 412727: 0f 85 23 01 00 00 jne 412850 <_IO_file_xsgetn+0x170> + 41272d: f7 03 00 01 00 00 testl $0x100,(%rbx) + 412733: 0f 85 07 01 00 00 jne 412840 <_IO_file_xsgetn+0x160> + 412739: 48 8b 53 38 mov 0x38(%rbx),%rdx + 41273d: 48 85 d2 test %rdx,%rdx + 412740: 0f 84 ba 00 00 00 je 412800 <_IO_file_xsgetn+0x120> + 412746: 48 8b 4b 40 mov 0x40(%rbx),%rcx + 41274a: 48 29 d1 sub %rdx,%rcx + 41274d: 49 39 cc cmp %rcx,%r12 + 412750: 0f 82 1a 01 00 00 jb 412870 <_IO_file_xsgetn+0x190> + 412756: 48 83 f9 7f cmp $0x7f,%rcx + 41275a: 48 89 53 18 mov %rdx,0x18(%rbx) + 41275e: 48 89 53 08 mov %rdx,0x8(%rbx) + 412762: 48 89 53 10 mov %rdx,0x10(%rbx) + 412766: 48 89 53 28 mov %rdx,0x28(%rbx) + 41276a: 48 89 53 20 mov %rdx,0x20(%rbx) + 41276e: 48 89 53 30 mov %rdx,0x30(%rbx) + 412772: 0f 86 b8 00 00 00 jbe 412830 <_IO_file_xsgetn+0x150> + 412778: 4c 89 e0 mov %r12,%rax + 41277b: 31 d2 xor %edx,%edx + 41277d: 48 f7 f1 div %rcx + 412780: 4c 89 e0 mov %r12,%rax + 412783: 48 29 d0 sub %rdx,%rax + 412786: 48 89 c2 mov %rax,%rdx + 412789: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 412790: 4c 89 f6 mov %r14,%rsi + 412793: 48 89 df mov %rbx,%rdi + 412796: ff 50 70 callq *0x70(%rax) + 412799: 48 83 f8 00 cmp $0x0,%rax + 41279d: 0f 8e ed 00 00 00 jle 412890 <_IO_file_xsgetn+0x1b0> + 4127a3: 48 8b 93 90 00 00 00 mov 0x90(%rbx),%rdx + 4127aa: 49 01 c6 add %rax,%r14 + 4127ad: 49 29 c4 sub %rax,%r12 + 4127b0: 48 83 fa ff cmp $0xffffffffffffffff,%rdx + 4127b4: 74 0a je 4127c0 <_IO_file_xsgetn+0xe0> + 4127b6: 48 01 d0 add %rdx,%rax + 4127b9: 48 89 83 90 00 00 00 mov %rax,0x90(%rbx) + 4127c0: 4d 85 e4 test %r12,%r12 + 4127c3: 0f 85 47 ff ff ff jne 412710 <_IO_file_xsgetn+0x30> + 4127c9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4127d0: 45 31 e4 xor %r12d,%r12d + 4127d3: 4c 89 e8 mov %r13,%rax + 4127d6: 5b pop %rbx + 4127d7: 4c 29 e0 sub %r12,%rax + 4127da: 5d pop %rbp + 4127db: 41 5c pop %r12 + 4127dd: 41 5d pop %r13 + 4127df: 41 5e pop %r14 + 4127e1: c3 retq + 4127e2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4127e8: 4c 89 e2 mov %r12,%rdx + 4127eb: 4c 89 f7 mov %r14,%rdi + 4127ee: e8 2d 98 01 00 callq 42c020 + 4127f3: 4c 01 63 08 add %r12,0x8(%rbx) + 4127f7: eb d7 jmp 4127d0 <_IO_file_xsgetn+0xf0> + 4127f9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 412800: 48 c7 43 18 00 00 00 movq $0x0,0x18(%rbx) + 412807: 00 + 412808: 48 c7 43 08 00 00 00 movq $0x0,0x8(%rbx) + 41280f: 00 + 412810: 48 c7 43 10 00 00 00 movq $0x0,0x10(%rbx) + 412817: 00 + 412818: 48 c7 43 28 00 00 00 movq $0x0,0x28(%rbx) + 41281f: 00 + 412820: 48 c7 43 20 00 00 00 movq $0x0,0x20(%rbx) + 412827: 00 + 412828: 48 c7 43 30 00 00 00 movq $0x0,0x30(%rbx) + 41282f: 00 + 412830: 4c 89 e2 mov %r12,%rdx + 412833: e9 51 ff ff ff jmpq 412789 <_IO_file_xsgetn+0xa9> + 412838: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 41283f: 00 + 412840: 48 89 df mov %rbx,%rdi + 412843: e8 18 21 00 00 callq 414960 <_IO_switch_to_main_get_area> + 412848: e9 73 ff ff ff jmpq 4127c0 <_IO_file_xsgetn+0xe0> + 41284d: 0f 1f 00 nopl (%rax) + 412850: 4c 89 f7 mov %r14,%rdi + 412853: 48 89 ea mov %rbp,%rdx + 412856: 49 29 ec sub %rbp,%r12 + 412859: e8 62 3d 01 00 callq 4265c0 <__mempcpy> + 41285e: 48 01 6b 08 add %rbp,0x8(%rbx) + 412862: 49 89 c6 mov %rax,%r14 + 412865: e9 c3 fe ff ff jmpq 41272d <_IO_file_xsgetn+0x4d> + 41286a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 412870: 48 89 df mov %rbx,%rdi + 412873: e8 48 22 00 00 callq 414ac0 <__underflow> + 412878: 83 f8 ff cmp $0xffffffff,%eax + 41287b: 0f 85 3f ff ff ff jne 4127c0 <_IO_file_xsgetn+0xe0> + 412881: 4c 89 e8 mov %r13,%rax + 412884: 5b pop %rbx + 412885: 4c 29 e0 sub %r12,%rax + 412888: 5d pop %rbp + 412889: 41 5c pop %r12 + 41288b: 41 5d pop %r13 + 41288d: 41 5e pop %r14 + 41288f: c3 retq + 412890: 75 2f jne 4128c1 <_IO_file_xsgetn+0x1e1> + 412892: 83 0b 10 orl $0x10,(%rbx) + 412895: e9 39 ff ff ff jmpq 4127d3 <_IO_file_xsgetn+0xf3> + 41289a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4128a0: 48 8b 7f 48 mov 0x48(%rdi),%rdi + 4128a4: 48 85 ff test %rdi,%rdi + 4128a7: 74 0b je 4128b4 <_IO_file_xsgetn+0x1d4> + 4128a9: e8 02 b5 00 00 callq 41ddb0 <__cfree> + 4128ae: 81 23 ff fe ff ff andl $0xfffffeff,(%rbx) + 4128b4: 48 89 df mov %rbx,%rdi + 4128b7: e8 44 25 00 00 callq 414e00 <_IO_doallocbuf> + 4128bc: e9 3b fe ff ff jmpq 4126fc <_IO_file_xsgetn+0x1c> + 4128c1: 83 0b 20 orl $0x20,(%rbx) + 4128c4: e9 0a ff ff ff jmpq 4127d3 <_IO_file_xsgetn+0xf3> + 4128c9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + +00000000004128d0 <_IO_file_seekoff_mmap>: + 4128d0: 55 push %rbp + 4128d1: 53 push %rbx + 4128d2: 48 89 fb mov %rdi,%rbx + 4128d5: 48 83 ec 08 sub $0x8,%rsp + 4128d9: 85 c9 test %ecx,%ecx + 4128db: 0f 84 87 00 00 00 je 412968 <_IO_file_seekoff_mmap+0x98> + 4128e1: 83 fa 01 cmp $0x1,%edx + 4128e4: 48 89 f5 mov %rsi,%rbp + 4128e7: 74 6f je 412958 <_IO_file_seekoff_mmap+0x88> + 4128e9: 83 fa 02 cmp $0x2,%edx + 4128ec: 75 0b jne 4128f9 <_IO_file_seekoff_mmap+0x29> + 4128ee: 48 8b 47 40 mov 0x40(%rdi),%rax + 4128f2: 48 2b 47 38 sub 0x38(%rdi),%rax + 4128f6: 48 01 c5 add %rax,%rbp + 4128f9: 48 85 ed test %rbp,%rbp + 4128fc: 0f 88 96 00 00 00 js 412998 <_IO_file_seekoff_mmap+0xc8> + 412902: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 412909: 31 d2 xor %edx,%edx + 41290b: 48 89 ee mov %rbp,%rsi + 41290e: 48 89 df mov %rbx,%rdi + 412911: ff 90 80 00 00 00 callq *0x80(%rax) + 412917: 48 85 c0 test %rax,%rax + 41291a: 0f 88 8f 00 00 00 js 4129af <_IO_file_seekoff_mmap+0xdf> + 412920: 48 8b 4b 40 mov 0x40(%rbx),%rcx + 412924: 48 8b 53 38 mov 0x38(%rbx),%rdx + 412928: 48 89 ce mov %rcx,%rsi + 41292b: 48 89 53 18 mov %rdx,0x18(%rbx) + 41292f: 48 29 d6 sub %rdx,%rsi + 412932: 48 39 f5 cmp %rsi,%rbp + 412935: 7e 51 jle 412988 <_IO_file_seekoff_mmap+0xb8> + 412937: 48 89 4b 08 mov %rcx,0x8(%rbx) + 41293b: 48 89 4b 10 mov %rcx,0x10(%rbx) + 41293f: 83 23 ef andl $0xffffffef,(%rbx) + 412942: 48 89 83 90 00 00 00 mov %rax,0x90(%rbx) + 412949: 48 89 e8 mov %rbp,%rax + 41294c: 48 83 c4 08 add $0x8,%rsp + 412950: 5b pop %rbx + 412951: 5d pop %rbp + 412952: c3 retq + 412953: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 412958: 48 8b 47 08 mov 0x8(%rdi),%rax + 41295c: 48 2b 47 18 sub 0x18(%rdi),%rax + 412960: 48 01 c5 add %rax,%rbp + 412963: eb 94 jmp 4128f9 <_IO_file_seekoff_mmap+0x29> + 412965: 0f 1f 00 nopl (%rax) + 412968: 48 8b 57 10 mov 0x10(%rdi),%rdx + 41296c: 48 2b 57 08 sub 0x8(%rdi),%rdx + 412970: 48 8b 87 90 00 00 00 mov 0x90(%rdi),%rax + 412977: 48 83 c4 08 add $0x8,%rsp + 41297b: 5b pop %rbx + 41297c: 5d pop %rbp + 41297d: 48 29 d0 sub %rdx,%rax + 412980: c3 retq + 412981: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 412988: 48 01 ea add %rbp,%rdx + 41298b: 48 89 53 08 mov %rdx,0x8(%rbx) + 41298f: 48 89 53 10 mov %rdx,0x10(%rbx) + 412993: eb aa jmp 41293f <_IO_file_seekoff_mmap+0x6f> + 412995: 0f 1f 00 nopl (%rax) + 412998: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 41299f: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) + 4129a6: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax + 4129ad: eb 9d jmp 41294c <_IO_file_seekoff_mmap+0x7c> + 4129af: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax + 4129b6: eb 94 jmp 41294c <_IO_file_seekoff_mmap+0x7c> + 4129b8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 4129bf: 00 + +00000000004129c0 <_IO_file_read>: + 4129c0: f6 47 74 02 testb $0x2,0x74(%rdi) + 4129c4: 74 32 je 4129f8 <_IO_file_read+0x38> + 4129c6: 48 63 7f 70 movslq 0x70(%rdi),%rdi + 4129ca: 31 c0 xor %eax,%eax + 4129cc: 0f 05 syscall + 4129ce: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 4129d4: 76 1a jbe 4129f0 <_IO_file_read+0x30> + 4129d6: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx + 4129dd: f7 d8 neg %eax + 4129df: 64 89 02 mov %eax,%fs:(%rdx) + 4129e2: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax + 4129e9: c3 retq + 4129ea: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4129f0: f3 c3 repz retq + 4129f2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4129f8: 8b 7f 70 mov 0x70(%rdi),%edi + 4129fb: e9 80 c7 02 00 jmpq 43f180 <__libc_read> + +0000000000412a00 <_IO_new_file_xsputn>: + 412a00: 31 c0 xor %eax,%eax + 412a02: 48 85 d2 test %rdx,%rdx + 412a05: 0f 84 84 00 00 00 je 412a8f <_IO_new_file_xsputn+0x8f> + 412a0b: 41 57 push %r15 + 412a0d: 41 56 push %r14 + 412a0f: 41 55 push %r13 + 412a11: 41 54 push %r12 + 412a13: 49 89 f5 mov %rsi,%r13 + 412a16: 55 push %rbp + 412a17: 53 push %rbx + 412a18: 49 89 d4 mov %rdx,%r12 + 412a1b: 48 89 fb mov %rdi,%rbx + 412a1e: 48 83 ec 08 sub $0x8,%rsp + 412a22: 8b 07 mov (%rdi),%eax + 412a24: 25 00 0a 00 00 and $0xa00,%eax + 412a29: 3d 00 0a 00 00 cmp $0xa00,%eax + 412a2e: 0f 84 bc 00 00 00 je 412af0 <_IO_new_file_xsputn+0xf0> + 412a34: 48 8b 57 30 mov 0x30(%rdi),%rdx + 412a38: 48 8b 7f 28 mov 0x28(%rdi),%rdi + 412a3c: 48 39 fa cmp %rdi,%rdx + 412a3f: 76 57 jbe 412a98 <_IO_new_file_xsputn+0x98> + 412a41: 48 29 fa sub %rdi,%rdx + 412a44: 45 31 f6 xor %r14d,%r14d + 412a47: 48 85 d2 test %rdx,%rdx + 412a4a: 0f 84 f0 00 00 00 je 412b40 <_IO_new_file_xsputn+0x140> + 412a50: 49 39 d4 cmp %rdx,%r12 + 412a53: 4c 89 ee mov %r13,%rsi + 412a56: 49 0f 46 d4 cmovbe %r12,%rdx + 412a5a: 48 89 d5 mov %rdx,%rbp + 412a5d: e8 5e 3b 01 00 callq 4265c0 <__mempcpy> + 412a62: 48 89 43 28 mov %rax,0x28(%rbx) + 412a66: 4c 89 e0 mov %r12,%rax + 412a69: 49 01 ed add %rbp,%r13 + 412a6c: 48 29 e8 sub %rbp,%rax + 412a6f: 48 89 c5 mov %rax,%rbp + 412a72: 49 01 ee add %rbp,%r14 + 412a75: 0f 85 12 02 00 00 jne 412c8d <_IO_new_file_xsputn+0x28d> + 412a7b: 4c 89 e0 mov %r12,%rax + 412a7e: 48 29 e8 sub %rbp,%rax + 412a81: 48 83 c4 08 add $0x8,%rsp + 412a85: 5b pop %rbx + 412a86: 5d pop %rbp + 412a87: 41 5c pop %r12 + 412a89: 41 5d pop %r13 + 412a8b: 41 5e pop %r14 + 412a8d: 41 5f pop %r15 + 412a8f: f3 c3 repz retq + 412a91: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 412a98: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 412a9f: be ff ff ff ff mov $0xffffffff,%esi + 412aa4: 48 89 df mov %rbx,%rdi + 412aa7: 4c 89 e5 mov %r12,%rbp + 412aaa: ff 50 18 callq *0x18(%rax) + 412aad: 83 f8 ff cmp $0xffffffff,%eax + 412ab0: 74 c9 je 412a7b <_IO_new_file_xsputn+0x7b> + 412ab2: 48 8b 4b 40 mov 0x40(%rbx),%rcx + 412ab6: 48 2b 4b 38 sub 0x38(%rbx),%rcx + 412aba: 31 d2 xor %edx,%edx + 412abc: 48 83 f9 7f cmp $0x7f,%rcx + 412ac0: 0f 87 ad 00 00 00 ja 412b73 <_IO_new_file_xsputn+0x173> + 412ac6: 49 89 ee mov %rbp,%r14 + 412ac9: 49 29 d6 sub %rdx,%r14 + 412acc: 0f 85 ae 00 00 00 jne 412b80 <_IO_new_file_xsputn+0x180> + 412ad2: 48 85 ed test %rbp,%rbp + 412ad5: 74 a4 je 412a7b <_IO_new_file_xsputn+0x7b> + 412ad7: 4b 8d 74 35 00 lea 0x0(%r13,%r14,1),%rsi + 412adc: 48 89 ea mov %rbp,%rdx + 412adf: 48 89 df mov %rbx,%rdi + 412ae2: e8 e9 23 00 00 callq 414ed0 <_IO_default_xsputn> + 412ae7: 48 29 c5 sub %rax,%rbp + 412aea: eb 8f jmp 412a7b <_IO_new_file_xsputn+0x7b> + 412aec: 0f 1f 40 00 nopl 0x0(%rax) + 412af0: 48 8b 7f 28 mov 0x28(%rdi),%rdi + 412af4: 48 8b 53 40 mov 0x40(%rbx),%rdx + 412af8: 48 29 fa sub %rdi,%rdx + 412afb: 49 39 d4 cmp %rdx,%r12 + 412afe: 0f 87 40 ff ff ff ja 412a44 <_IO_new_file_xsputn+0x44> + 412b04: 4a 8d 0c 26 lea (%rsi,%r12,1),%rcx + 412b08: 48 39 ce cmp %rcx,%rsi + 412b0b: 73 25 jae 412b32 <_IO_new_file_xsputn+0x132> + 412b0d: 80 79 ff 0a cmpb $0xa,-0x1(%rcx) + 412b11: 48 8d 41 ff lea -0x1(%rcx),%rax + 412b15: 75 16 jne 412b2d <_IO_new_file_xsputn+0x12d> + 412b17: e9 e4 00 00 00 jmpq 412c00 <_IO_new_file_xsputn+0x200> + 412b1c: 0f 1f 40 00 nopl 0x0(%rax) + 412b20: 48 83 e8 01 sub $0x1,%rax + 412b24: 80 38 0a cmpb $0xa,(%rax) + 412b27: 0f 84 d3 00 00 00 je 412c00 <_IO_new_file_xsputn+0x200> + 412b2d: 49 39 c5 cmp %rax,%r13 + 412b30: 75 ee jne 412b20 <_IO_new_file_xsputn+0x120> + 412b32: 45 31 f6 xor %r14d,%r14d + 412b35: e9 16 ff ff ff jmpq 412a50 <_IO_new_file_xsputn+0x50> + 412b3a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 412b40: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 412b47: be ff ff ff ff mov $0xffffffff,%esi + 412b4c: 48 89 df mov %rbx,%rdi + 412b4f: ff 50 18 callq *0x18(%rax) + 412b52: 89 c2 mov %eax,%edx + 412b54: 31 c0 xor %eax,%eax + 412b56: 83 fa ff cmp $0xffffffff,%edx + 412b59: 0f 84 22 ff ff ff je 412a81 <_IO_new_file_xsputn+0x81> + 412b5f: 48 8b 4b 40 mov 0x40(%rbx),%rcx + 412b63: 48 2b 4b 38 sub 0x38(%rbx),%rcx + 412b67: 4c 89 e5 mov %r12,%rbp + 412b6a: 4d 89 e6 mov %r12,%r14 + 412b6d: 48 83 f9 7f cmp $0x7f,%rcx + 412b71: 76 0d jbe 412b80 <_IO_new_file_xsputn+0x180> + 412b73: 48 89 e8 mov %rbp,%rax + 412b76: 31 d2 xor %edx,%edx + 412b78: 48 f7 f1 div %rcx + 412b7b: e9 46 ff ff ff jmpq 412ac6 <_IO_new_file_xsputn+0xc6> + 412b80: f7 03 00 10 00 00 testl $0x1000,(%rbx) + 412b86: 0f 84 94 00 00 00 je 412c20 <_IO_new_file_xsputn+0x220> + 412b8c: 48 c7 83 90 00 00 00 movq $0xffffffffffffffff,0x90(%rbx) + 412b93: ff ff ff ff + 412b97: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 412b9e: 4c 89 f2 mov %r14,%rdx + 412ba1: 4c 89 ee mov %r13,%rsi + 412ba4: 48 89 df mov %rbx,%rdi + 412ba7: ff 50 78 callq *0x78(%rax) + 412baa: 49 89 c7 mov %rax,%r15 + 412bad: 0f b7 83 80 00 00 00 movzwl 0x80(%rbx),%eax + 412bb4: 4d 85 ff test %r15,%r15 + 412bb7: 74 09 je 412bc2 <_IO_new_file_xsputn+0x1c2> + 412bb9: 66 85 c0 test %ax,%ax + 412bbc: 0f 85 ae 00 00 00 jne 412c70 <_IO_new_file_xsputn+0x270> + 412bc2: 8b 93 c0 00 00 00 mov 0xc0(%rbx),%edx + 412bc8: 48 8b 43 38 mov 0x38(%rbx),%rax + 412bcc: 85 d2 test %edx,%edx + 412bce: 48 89 43 18 mov %rax,0x18(%rbx) + 412bd2: 48 89 43 08 mov %rax,0x8(%rbx) + 412bd6: 48 89 43 10 mov %rax,0x10(%rbx) + 412bda: 48 89 43 28 mov %rax,0x28(%rbx) + 412bde: 48 89 43 20 mov %rax,0x20(%rbx) + 412be2: 7e 7b jle 412c5f <_IO_new_file_xsputn+0x25f> + 412be4: 48 8b 43 40 mov 0x40(%rbx),%rax + 412be8: 4c 29 fd sub %r15,%rbp + 412beb: 4d 39 f7 cmp %r14,%r15 + 412bee: 48 89 43 30 mov %rax,0x30(%rbx) + 412bf2: 0f 83 da fe ff ff jae 412ad2 <_IO_new_file_xsputn+0xd2> + 412bf8: e9 7e fe ff ff jmpq 412a7b <_IO_new_file_xsputn+0x7b> + 412bfd: 0f 1f 00 nopl (%rax) + 412c00: 4c 29 e8 sub %r13,%rax + 412c03: 41 be 01 00 00 00 mov $0x1,%r14d + 412c09: 4c 89 e5 mov %r12,%rbp + 412c0c: 48 83 c0 01 add $0x1,%rax + 412c10: 48 89 c2 mov %rax,%rdx + 412c13: 0f 85 37 fe ff ff jne 412a50 <_IO_new_file_xsputn+0x50> + 412c19: e9 54 fe ff ff jmpq 412a72 <_IO_new_file_xsputn+0x72> + 412c1e: 66 90 xchg %ax,%ax + 412c20: 48 8b 43 10 mov 0x10(%rbx),%rax + 412c24: 48 8b 73 20 mov 0x20(%rbx),%rsi + 412c28: 48 39 f0 cmp %rsi,%rax + 412c2b: 0f 84 66 ff ff ff je 412b97 <_IO_new_file_xsputn+0x197> + 412c31: 48 29 c6 sub %rax,%rsi + 412c34: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 412c3b: ba 01 00 00 00 mov $0x1,%edx + 412c40: 48 89 df mov %rbx,%rdi + 412c43: ff 90 80 00 00 00 callq *0x80(%rax) + 412c49: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 412c4d: 0f 84 28 fe ff ff je 412a7b <_IO_new_file_xsputn+0x7b> + 412c53: 48 89 83 90 00 00 00 mov %rax,0x90(%rbx) + 412c5a: e9 38 ff ff ff jmpq 412b97 <_IO_new_file_xsputn+0x197> + 412c5f: f7 03 02 02 00 00 testl $0x202,(%rbx) + 412c65: 0f 85 7d ff ff ff jne 412be8 <_IO_new_file_xsputn+0x1e8> + 412c6b: e9 74 ff ff ff jmpq 412be4 <_IO_new_file_xsputn+0x1e4> + 412c70: 8d 78 ff lea -0x1(%rax),%edi + 412c73: 44 89 fa mov %r15d,%edx + 412c76: 4c 89 ee mov %r13,%rsi + 412c79: e8 42 2d 00 00 callq 4159c0 <_IO_adjust_column> + 412c7e: 83 c0 01 add $0x1,%eax + 412c81: 66 89 83 80 00 00 00 mov %ax,0x80(%rbx) + 412c88: e9 35 ff ff ff jmpq 412bc2 <_IO_new_file_xsputn+0x1c2> + 412c8d: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 412c94: 83 ce ff or $0xffffffff,%esi + 412c97: 48 89 df mov %rbx,%rdi + 412c9a: ff 50 18 callq *0x18(%rax) + 412c9d: 83 c0 01 add $0x1,%eax + 412ca0: 0f 85 0c fe ff ff jne 412ab2 <_IO_new_file_xsputn+0xb2> + 412ca6: 48 85 ed test %rbp,%rbp + 412ca9: 0f 85 cc fd ff ff jne 412a7b <_IO_new_file_xsputn+0x7b> + 412caf: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax + 412cb6: e9 c6 fd ff ff jmpq 412a81 <_IO_new_file_xsputn+0x81> + 412cbb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + +0000000000412cc0 <_IO_file_underflow_maybe_mmap>: + 412cc0: 55 push %rbp + 412cc1: 53 push %rbx + 412cc2: 48 89 fb mov %rdi,%rbx + 412cc5: 48 81 ec 98 00 00 00 sub $0x98,%rsp + 412ccc: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax + 412cd3: 48 89 e6 mov %rsp,%rsi + 412cd6: ff 90 90 00 00 00 callq *0x90(%rax) + 412cdc: 85 c0 test %eax,%eax + 412cde: 75 10 jne 412cf0 <_IO_file_underflow_maybe_mmap+0x30> + 412ce0: 8b 44 24 18 mov 0x18(%rsp),%eax + 412ce4: 25 00 f0 00 00 and $0xf000,%eax + 412ce9: 3d 00 80 00 00 cmp $0x8000,%eax + 412cee: 74 50 je 412d40 <_IO_file_underflow_maybe_mmap+0x80> + 412cf0: 8b 83 c0 00 00 00 mov 0xc0(%rbx),%eax + 412cf6: ba 20 1e 4a 00 mov $0x4a1e20,%edx + 412cfb: 85 c0 test %eax,%eax + 412cfd: b8 20 1b 4a 00 mov $0x4a1b20,%eax + 412d02: 48 0f 4e c2 cmovle %rdx,%rax + 412d06: 48 89 83 d8 00 00 00 mov %rax,0xd8(%rbx) + 412d0d: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 412d14: 48 c7 80 30 01 00 00 movq $0x4a1b20,0x130(%rax) + 412d1b: 20 1b 4a 00 + 412d1f: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 412d26: 48 89 df mov %rbx,%rdi + 412d29: ff 50 20 callq *0x20(%rax) + 412d2c: 48 81 c4 98 00 00 00 add $0x98,%rsp + 412d33: 5b pop %rbx + 412d34: 5d pop %rbp + 412d35: c3 retq + 412d36: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 412d3d: 00 00 00 + 412d40: 48 8b 74 24 30 mov 0x30(%rsp),%rsi + 412d45: 48 85 f6 test %rsi,%rsi + 412d48: 74 a6 je 412cf0 <_IO_file_underflow_maybe_mmap+0x30> + 412d4a: 48 8b 83 90 00 00 00 mov 0x90(%rbx),%rax + 412d51: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 412d55: 74 05 je 412d5c <_IO_file_underflow_maybe_mmap+0x9c> + 412d57: 48 39 c6 cmp %rax,%rsi + 412d5a: 7c 94 jl 412cf0 <_IO_file_underflow_maybe_mmap+0x30> + 412d5c: 44 8b 43 70 mov 0x70(%rbx),%r8d + 412d60: 45 31 c9 xor %r9d,%r9d + 412d63: 31 ff xor %edi,%edi + 412d65: b9 01 00 00 00 mov $0x1,%ecx + 412d6a: ba 01 00 00 00 mov $0x1,%edx + 412d6f: e8 7c ce 02 00 callq 43fbf0 <__mmap> + 412d74: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 412d78: 48 89 c5 mov %rax,%rbp + 412d7b: 0f 84 6f ff ff ff je 412cf0 <_IO_file_underflow_maybe_mmap+0x30> + 412d81: 48 8b 74 24 30 mov 0x30(%rsp),%rsi + 412d86: 8b 7b 70 mov 0x70(%rbx),%edi + 412d89: 31 d2 xor %edx,%edx + 412d8b: e8 a0 f7 02 00 callq 442530 <__libc_lseek> + 412d90: 48 8b 74 24 30 mov 0x30(%rsp),%rsi + 412d95: 48 39 f0 cmp %rsi,%rax + 412d98: 74 18 je 412db2 <_IO_file_underflow_maybe_mmap+0xf2> + 412d9a: 48 89 ef mov %rbp,%rdi + 412d9d: e8 0e cf 02 00 callq 43fcb0 <__munmap> + 412da2: 48 c7 83 90 00 00 00 movq $0xffffffffffffffff,0x90(%rbx) + 412da9: ff ff ff ff + 412dad: e9 3e ff ff ff jmpq 412cf0 <_IO_file_underflow_maybe_mmap+0x30> + 412db2: 48 8d 54 05 00 lea 0x0(%rbp,%rax,1),%rdx + 412db7: 31 c9 xor %ecx,%ecx + 412db9: 48 89 ee mov %rbp,%rsi + 412dbc: 48 89 df mov %rbx,%rdi + 412dbf: e8 dc 1f 00 00 callq 414da0 <_IO_setb> + 412dc4: 48 8b 83 90 00 00 00 mov 0x90(%rbx),%rax + 412dcb: ba 00 00 00 00 mov $0x0,%edx + 412dd0: 48 89 6b 18 mov %rbp,0x18(%rbx) + 412dd4: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 412dd8: 48 0f 44 c2 cmove %rdx,%rax + 412ddc: 8b 93 c0 00 00 00 mov 0xc0(%rbx),%edx + 412de2: 48 01 e8 add %rbp,%rax + 412de5: 48 89 43 08 mov %rax,0x8(%rbx) + 412de9: 48 8b 44 24 30 mov 0x30(%rsp),%rax + 412dee: 48 01 c5 add %rax,%rbp + 412df1: 48 89 83 90 00 00 00 mov %rax,0x90(%rbx) + 412df8: 85 d2 test %edx,%edx + 412dfa: b8 60 1a 4a 00 mov $0x4a1a60,%eax + 412dff: ba 60 1d 4a 00 mov $0x4a1d60,%edx + 412e04: 48 89 6b 10 mov %rbp,0x10(%rbx) + 412e08: 48 0f 4e c2 cmovle %rdx,%rax + 412e0c: 48 89 83 d8 00 00 00 mov %rax,0xd8(%rbx) + 412e13: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 412e1a: 48 c7 80 30 01 00 00 movq $0x4a1a60,0x130(%rax) + 412e21: 60 1a 4a 00 + 412e25: e9 f5 fe ff ff jmpq 412d1f <_IO_file_underflow_maybe_mmap+0x5f> + 412e2a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + +0000000000412e30 <_IO_file_underflow_mmap>: + 412e30: 48 8b 47 08 mov 0x8(%rdi),%rax + 412e34: 48 3b 47 10 cmp 0x10(%rdi),%rax + 412e38: 73 06 jae 412e40 <_IO_file_underflow_mmap+0x10> + 412e3a: 0f b6 00 movzbl (%rax),%eax + 412e3d: c3 retq + 412e3e: 66 90 xchg %ax,%ax + 412e40: 55 push %rbp + 412e41: 53 push %rbx + 412e42: 48 89 fb mov %rdi,%rbx + 412e45: 48 81 ec 98 00 00 00 sub $0x98,%rsp + 412e4c: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax + 412e53: 48 89 e6 mov %rsp,%rsi + 412e56: ff 90 90 00 00 00 callq *0x90(%rax) + 412e5c: 85 c0 test %eax,%eax + 412e5e: 75 14 jne 412e74 <_IO_file_underflow_mmap+0x44> + 412e60: 8b 44 24 18 mov 0x18(%rsp),%eax + 412e64: 25 00 f0 00 00 and $0xf000,%eax + 412e69: 3d 00 80 00 00 cmp $0x8000,%eax + 412e6e: 0f 84 84 00 00 00 je 412ef8 <_IO_file_underflow_mmap+0xc8> + 412e74: 48 8b 7b 38 mov 0x38(%rbx),%rdi + 412e78: 48 8b 73 40 mov 0x40(%rbx),%rsi + 412e7c: 48 29 fe sub %rdi,%rsi + 412e7f: e8 2c ce 02 00 callq 43fcb0 <__munmap> + 412e84: 8b 83 c0 00 00 00 mov 0xc0(%rbx),%eax + 412e8a: ba 20 1e 4a 00 mov $0x4a1e20,%edx + 412e8f: 48 c7 43 40 00 00 00 movq $0x0,0x40(%rbx) + 412e96: 00 + 412e97: 48 c7 43 38 00 00 00 movq $0x0,0x38(%rbx) + 412e9e: 00 + 412e9f: 48 c7 43 18 00 00 00 movq $0x0,0x18(%rbx) + 412ea6: 00 + 412ea7: 48 89 df mov %rbx,%rdi + 412eaa: 48 c7 43 08 00 00 00 movq $0x0,0x8(%rbx) + 412eb1: 00 + 412eb2: 48 c7 43 10 00 00 00 movq $0x0,0x10(%rbx) + 412eb9: 00 + 412eba: 85 c0 test %eax,%eax + 412ebc: b8 20 1b 4a 00 mov $0x4a1b20,%eax + 412ec1: 48 0f 4e c2 cmovle %rdx,%rax + 412ec5: 48 89 83 d8 00 00 00 mov %rax,0xd8(%rbx) + 412ecc: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 412ed3: 48 c7 80 30 01 00 00 movq $0x4a1b20,0x130(%rax) + 412eda: 20 1b 4a 00 + 412ede: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 412ee5: ff 50 20 callq *0x20(%rax) + 412ee8: 48 81 c4 98 00 00 00 add $0x98,%rsp + 412eef: 5b pop %rbx + 412ef0: 5d pop %rbp + 412ef1: c3 retq + 412ef2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 412ef8: 48 8b 6c 24 30 mov 0x30(%rsp),%rbp + 412efd: 48 85 ed test %rbp,%rbp + 412f00: 0f 84 6e ff ff ff je 412e74 <_IO_file_underflow_mmap+0x44> + 412f06: e8 85 cc 02 00 callq 43fb90 <__getpagesize> + 412f0b: 48 8b 7b 38 mov 0x38(%rbx),%rdi + 412f0f: 48 98 cltq + 412f11: 48 89 c6 mov %rax,%rsi + 412f14: 48 8d 54 05 ff lea -0x1(%rbp,%rax,1),%rdx + 412f19: 48 f7 de neg %rsi + 412f1c: 48 89 f9 mov %rdi,%rcx + 412f1f: 48 21 f2 and %rsi,%rdx + 412f22: 49 89 f8 mov %rdi,%r8 + 412f25: 48 f7 d1 not %rcx + 412f28: 48 03 4b 40 add 0x40(%rbx),%rcx + 412f2c: 48 01 c8 add %rcx,%rax + 412f2f: 48 21 c6 and %rax,%rsi + 412f32: 48 39 f2 cmp %rsi,%rdx + 412f35: 0f 82 8d 00 00 00 jb 412fc8 <_IO_file_underflow_mmap+0x198> + 412f3b: 0f 87 aa 00 00 00 ja 412feb <_IO_file_underflow_mmap+0x1bb> + 412f41: 48 01 fd add %rdi,%rbp + 412f44: 48 89 6b 40 mov %rbp,0x40(%rbx) + 412f48: 48 8b 53 10 mov 0x10(%rbx),%rdx + 412f4c: 48 2b 53 08 sub 0x8(%rbx),%rdx + 412f50: 48 89 ee mov %rbp,%rsi + 412f53: 48 8b 83 90 00 00 00 mov 0x90(%rbx),%rax + 412f5a: 4c 29 c6 sub %r8,%rsi + 412f5d: 48 89 7b 18 mov %rdi,0x18(%rbx) + 412f61: 48 29 d0 sub %rdx,%rax + 412f64: 48 39 f0 cmp %rsi,%rax + 412f67: 48 89 83 90 00 00 00 mov %rax,0x90(%rbx) + 412f6e: 7d 40 jge 412fb0 <_IO_file_underflow_mmap+0x180> + 412f70: 48 01 c7 add %rax,%rdi + 412f73: 31 d2 xor %edx,%edx + 412f75: 48 89 6b 10 mov %rbp,0x10(%rbx) + 412f79: 48 89 7b 08 mov %rdi,0x8(%rbx) + 412f7d: 8b 7b 70 mov 0x70(%rbx),%edi + 412f80: e8 ab f5 02 00 callq 442530 <__libc_lseek> + 412f85: 48 8b 53 40 mov 0x40(%rbx),%rdx + 412f89: 48 2b 53 38 sub 0x38(%rbx),%rdx + 412f8d: 48 39 d0 cmp %rdx,%rax + 412f90: 0f 84 86 00 00 00 je 41301c <_IO_file_underflow_mmap+0x1ec> + 412f96: 83 0b 20 orl $0x20,(%rbx) + 412f99: 48 8b 43 08 mov 0x8(%rbx),%rax + 412f9d: 48 3b 43 10 cmp 0x10(%rbx),%rax + 412fa1: 73 15 jae 412fb8 <_IO_file_underflow_mmap+0x188> + 412fa3: 0f b6 00 movzbl (%rax),%eax + 412fa6: 48 81 c4 98 00 00 00 add $0x98,%rsp + 412fad: 5b pop %rbx + 412fae: 5d pop %rbp + 412faf: c3 retq + 412fb0: 48 89 6b 08 mov %rbp,0x8(%rbx) + 412fb4: 48 89 6b 10 mov %rbp,0x10(%rbx) + 412fb8: 83 0b 10 orl $0x10,(%rbx) + 412fbb: b8 ff ff ff ff mov $0xffffffff,%eax + 412fc0: e9 23 ff ff ff jmpq 412ee8 <_IO_file_underflow_mmap+0xb8> + 412fc5: 0f 1f 00 nopl (%rax) + 412fc8: 48 01 d7 add %rdx,%rdi + 412fcb: 48 29 d6 sub %rdx,%rsi + 412fce: e8 dd cc 02 00 callq 43fcb0 <__munmap> + 412fd3: 48 8b 7b 38 mov 0x38(%rbx),%rdi + 412fd7: 48 89 fd mov %rdi,%rbp + 412fda: 48 03 6c 24 30 add 0x30(%rsp),%rbp + 412fdf: 49 89 f8 mov %rdi,%r8 + 412fe2: 48 89 6b 40 mov %rbp,0x40(%rbx) + 412fe6: e9 5d ff ff ff jmpq 412f48 <_IO_file_underflow_mmap+0x118> + 412feb: 31 c0 xor %eax,%eax + 412fed: b9 01 00 00 00 mov $0x1,%ecx + 412ff2: e8 59 f5 02 00 callq 442550 <__mremap> + 412ff7: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 412ffb: 0f 84 73 fe ff ff je 412e74 <_IO_file_underflow_mmap+0x44> + 413001: 48 89 c5 mov %rax,%rbp + 413004: 48 03 6c 24 30 add 0x30(%rsp),%rbp + 413009: 48 89 43 38 mov %rax,0x38(%rbx) + 41300d: 49 89 c0 mov %rax,%r8 + 413010: 48 89 c7 mov %rax,%rdi + 413013: 48 89 6b 40 mov %rbp,0x40(%rbx) + 413017: e9 2c ff ff ff jmpq 412f48 <_IO_file_underflow_mmap+0x118> + 41301c: 48 89 83 90 00 00 00 mov %rax,0x90(%rbx) + 413023: e9 71 ff ff ff jmpq 412f99 <_IO_file_underflow_mmap+0x169> + 413028: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 41302f: 00 + +0000000000413030 <_IO_new_file_init>: + 413030: 55 push %rbp + 413031: 53 push %rbx + 413032: 48 c7 c5 ff ff ff ff mov $0xffffffffffffffff,%rbp + 413039: 48 89 fb mov %rdi,%rbx + 41303c: 48 83 ec 08 sub $0x8,%rsp + 413040: 81 0f 0c 24 00 00 orl $0x240c,(%rdi) + 413046: 48 89 af 90 00 00 00 mov %rbp,0x90(%rdi) + 41304d: e8 9e 16 00 00 callq 4146f0 <_IO_link_in> + 413052: 89 6b 70 mov %ebp,0x70(%rbx) + 413055: 48 83 c4 08 add $0x8,%rsp + 413059: 5b pop %rbx + 41305a: 5d pop %rbp + 41305b: c3 retq + 41305c: 0f 1f 40 00 nopl 0x0(%rax) + +0000000000413060 <_IO_file_open>: + 413060: 55 push %rbp + 413061: 53 push %rbx + 413062: 48 89 fb mov %rdi,%rbx + 413065: 48 89 f7 mov %rsi,%rdi + 413068: 48 63 f2 movslq %edx,%rsi + 41306b: 48 83 ec 18 sub $0x18,%rsp + 41306f: f6 43 74 02 testb $0x2,0x74(%rbx) + 413073: 74 6b je 4130e0 <_IO_file_open+0x80> + 413075: 48 63 d1 movslq %ecx,%rdx + 413078: b8 02 00 00 00 mov $0x2,%eax + 41307d: 0f 05 syscall + 41307f: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 413085: 89 c5 mov %eax,%ebp + 413087: 77 47 ja 4130d0 <_IO_file_open+0x70> + 413089: 85 ed test %ebp,%ebp + 41308b: 78 4f js 4130dc <_IO_file_open+0x7c> + 41308d: 8b 13 mov (%rbx),%edx + 41308f: 44 89 c0 mov %r8d,%eax + 413092: 41 81 e0 04 10 00 00 and $0x1004,%r8d + 413099: 25 0c 10 00 00 and $0x100c,%eax + 41309e: 89 6b 70 mov %ebp,0x70(%rbx) + 4130a1: 81 e2 f3 ef ff ff and $0xffffeff3,%edx + 4130a7: 09 d0 or %edx,%eax + 4130a9: 41 81 f8 04 10 00 00 cmp $0x1004,%r8d + 4130b0: 89 03 mov %eax,(%rbx) + 4130b2: 74 4c je 413100 <_IO_file_open+0xa0> + 4130b4: 48 89 df mov %rbx,%rdi + 4130b7: e8 34 16 00 00 callq 4146f0 <_IO_link_in> + 4130bc: 48 89 d8 mov %rbx,%rax + 4130bf: 48 83 c4 18 add $0x18,%rsp + 4130c3: 5b pop %rbx + 4130c4: 5d pop %rbp + 4130c5: c3 retq + 4130c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4130cd: 00 00 00 + 4130d0: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx + 4130d7: f7 d8 neg %eax + 4130d9: 64 89 02 mov %eax,%fs:(%rdx) + 4130dc: 31 c0 xor %eax,%eax + 4130de: eb df jmp 4130bf <_IO_file_open+0x5f> + 4130e0: 89 ca mov %ecx,%edx + 4130e2: 31 c0 xor %eax,%eax + 4130e4: 44 89 44 24 0c mov %r8d,0xc(%rsp) + 4130e9: e8 32 c0 02 00 callq 43f120 <__libc_open> + 4130ee: 44 8b 44 24 0c mov 0xc(%rsp),%r8d + 4130f3: 89 c5 mov %eax,%ebp + 4130f5: eb 92 jmp 413089 <_IO_file_open+0x29> + 4130f7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 4130fe: 00 00 + 413100: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 413107: 31 f6 xor %esi,%esi + 413109: ba 02 00 00 00 mov $0x2,%edx + 41310e: 48 89 df mov %rbx,%rdi + 413111: ff 90 80 00 00 00 callq *0x80(%rax) + 413117: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 41311b: 75 97 jne 4130b4 <_IO_file_open+0x54> + 41311d: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx + 413124: 64 83 3a 1d cmpl $0x1d,%fs:(%rdx) + 413128: 74 8a je 4130b4 <_IO_file_open+0x54> + 41312a: 48 63 fd movslq %ebp,%rdi + 41312d: b8 03 00 00 00 mov $0x3,%eax + 413132: 0f 05 syscall + 413134: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 41313a: 76 a0 jbe 4130dc <_IO_file_open+0x7c> + 41313c: f7 d8 neg %eax + 41313e: 64 89 02 mov %eax,%fs:(%rdx) + 413141: 31 c0 xor %eax,%eax + 413143: e9 77 ff ff ff jmpq 4130bf <_IO_file_open+0x5f> + 413148: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 41314f: 00 + +0000000000413150 <_IO_new_file_attach>: + 413150: 83 7f 70 ff cmpl $0xffffffff,0x70(%rdi) + 413154: 75 5a jne 4131b0 <_IO_new_file_attach+0x60> + 413156: 8b 07 mov (%rdi),%eax + 413158: 41 54 push %r12 + 41315a: b9 03 00 00 00 mov $0x3,%ecx + 41315f: 55 push %rbp + 413160: 48 c7 c5 d0 ff ff ff mov $0xffffffffffffffd0,%rbp + 413167: ba 01 00 00 00 mov $0x1,%edx + 41316c: 53 push %rbx + 41316d: 89 77 70 mov %esi,0x70(%rdi) + 413170: 48 89 fb mov %rdi,%rbx + 413173: 83 e0 f3 and $0xfffffff3,%eax + 413176: 31 f6 xor %esi,%esi + 413178: 48 c7 87 90 00 00 00 movq $0xffffffffffffffff,0x90(%rdi) + 41317f: ff ff ff ff + 413183: 83 c8 40 or $0x40,%eax + 413186: 64 44 8b 65 00 mov %fs:0x0(%rbp),%r12d + 41318b: 89 07 mov %eax,(%rdi) + 41318d: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax + 413194: ff 50 48 callq *0x48(%rax) + 413197: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 41319b: 74 1b je 4131b8 <_IO_new_file_attach+0x68> + 41319d: 64 44 89 65 00 mov %r12d,%fs:0x0(%rbp) + 4131a2: 48 89 d8 mov %rbx,%rax + 4131a5: 5b pop %rbx + 4131a6: 5d pop %rbp + 4131a7: 41 5c pop %r12 + 4131a9: c3 retq + 4131aa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4131b0: 31 c0 xor %eax,%eax + 4131b2: c3 retq + 4131b3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4131b8: 31 c0 xor %eax,%eax + 4131ba: 64 83 7d 00 1d cmpl $0x1d,%fs:0x0(%rbp) + 4131bf: 74 dc je 41319d <_IO_new_file_attach+0x4d> + 4131c1: eb e2 jmp 4131a5 <_IO_new_file_attach+0x55> + 4131c3: 0f 1f 00 nopl (%rax) + 4131c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4131cd: 00 00 00 + +00000000004131d0 <_IO_new_do_write>: + 4131d0: 31 c0 xor %eax,%eax + 4131d2: 48 85 d2 test %rdx,%rdx + 4131d5: 75 09 jne 4131e0 <_IO_new_do_write+0x10> + 4131d7: c3 retq + 4131d8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 4131df: 00 + 4131e0: 41 55 push %r13 + 4131e2: 41 54 push %r12 + 4131e4: 49 89 f4 mov %rsi,%r12 + 4131e7: 55 push %rbp + 4131e8: 53 push %rbx + 4131e9: 48 89 d5 mov %rdx,%rbp + 4131ec: 48 89 fb mov %rdi,%rbx + 4131ef: 48 83 ec 08 sub $0x8,%rsp + 4131f3: f7 07 00 10 00 00 testl $0x1000,(%rdi) + 4131f9: 0f 85 a1 00 00 00 jne 4132a0 <_IO_new_do_write+0xd0> + 4131ff: 48 8b 47 10 mov 0x10(%rdi),%rax + 413203: 48 8b 77 20 mov 0x20(%rdi),%rsi + 413207: 48 39 f0 cmp %rsi,%rax + 41320a: 74 2a je 413236 <_IO_new_do_write+0x66> + 41320c: 48 29 c6 sub %rax,%rsi + 41320f: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax + 413216: ba 01 00 00 00 mov $0x1,%edx + 41321b: ff 90 80 00 00 00 callq *0x80(%rax) + 413221: 48 89 c2 mov %rax,%rdx + 413224: b8 ff ff ff ff mov $0xffffffff,%eax + 413229: 48 83 fa ff cmp $0xffffffffffffffff,%rdx + 41322d: 74 62 je 413291 <_IO_new_do_write+0xc1> + 41322f: 48 89 93 90 00 00 00 mov %rdx,0x90(%rbx) + 413236: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 41323d: 48 89 ea mov %rbp,%rdx + 413240: 4c 89 e6 mov %r12,%rsi + 413243: 48 89 df mov %rbx,%rdi + 413246: ff 50 78 callq *0x78(%rax) + 413249: 49 89 c5 mov %rax,%r13 + 41324c: 0f b7 83 80 00 00 00 movzwl 0x80(%rbx),%eax + 413253: 4d 85 ed test %r13,%r13 + 413256: 74 05 je 41325d <_IO_new_do_write+0x8d> + 413258: 66 85 c0 test %ax,%ax + 41325b: 75 63 jne 4132c0 <_IO_new_do_write+0xf0> + 41325d: 8b 93 c0 00 00 00 mov 0xc0(%rbx),%edx + 413263: 48 8b 43 38 mov 0x38(%rbx),%rax + 413267: 85 d2 test %edx,%edx + 413269: 48 89 43 18 mov %rax,0x18(%rbx) + 41326d: 48 89 43 08 mov %rax,0x8(%rbx) + 413271: 48 89 43 10 mov %rax,0x10(%rbx) + 413275: 48 89 43 28 mov %rax,0x28(%rbx) + 413279: 48 89 43 20 mov %rax,0x20(%rbx) + 41327d: 7e 31 jle 4132b0 <_IO_new_do_write+0xe0> + 41327f: 48 8b 43 40 mov 0x40(%rbx),%rax + 413283: 48 89 43 30 mov %rax,0x30(%rbx) + 413287: 31 c0 xor %eax,%eax + 413289: 4c 39 ed cmp %r13,%rbp + 41328c: 0f 95 c0 setne %al + 41328f: f7 d8 neg %eax + 413291: 48 83 c4 08 add $0x8,%rsp + 413295: 5b pop %rbx + 413296: 5d pop %rbp + 413297: 41 5c pop %r12 + 413299: 41 5d pop %r13 + 41329b: c3 retq + 41329c: 0f 1f 40 00 nopl 0x0(%rax) + 4132a0: 48 c7 87 90 00 00 00 movq $0xffffffffffffffff,0x90(%rdi) + 4132a7: ff ff ff ff + 4132ab: eb 89 jmp 413236 <_IO_new_do_write+0x66> + 4132ad: 0f 1f 00 nopl (%rax) + 4132b0: f7 03 02 02 00 00 testl $0x202,(%rbx) + 4132b6: 75 cb jne 413283 <_IO_new_do_write+0xb3> + 4132b8: eb c5 jmp 41327f <_IO_new_do_write+0xaf> + 4132ba: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4132c0: 8d 78 ff lea -0x1(%rax),%edi + 4132c3: 44 89 ea mov %r13d,%edx + 4132c6: 4c 89 e6 mov %r12,%rsi + 4132c9: e8 f2 26 00 00 callq 4159c0 <_IO_adjust_column> + 4132ce: 83 c0 01 add $0x1,%eax + 4132d1: 66 89 83 80 00 00 00 mov %ax,0x80(%rbx) + 4132d8: e9 80 ff ff ff jmpq 41325d <_IO_new_do_write+0x8d> + 4132dd: 0f 1f 00 nopl (%rax) + +00000000004132e0 <_IO_new_file_close_it>: + 4132e0: 8b 47 70 mov 0x70(%rdi),%eax + 4132e3: 83 f8 ff cmp $0xffffffff,%eax + 4132e6: 0f 84 fe 00 00 00 je 4133ea <_IO_new_file_close_it+0x10a> + 4132ec: 41 54 push %r12 + 4132ee: 55 push %rbp + 4132ef: 45 31 e4 xor %r12d,%r12d + 4132f2: 53 push %rbx + 4132f3: 8b 07 mov (%rdi),%eax + 4132f5: 48 89 fb mov %rdi,%rbx + 4132f8: 25 08 08 00 00 and $0x808,%eax + 4132fd: 3d 00 08 00 00 cmp $0x800,%eax + 413302: 0f 84 08 01 00 00 je 413410 <_IO_new_file_close_it+0x130> + 413308: 48 89 df mov %rbx,%rdi + 41330b: 31 ed xor %ebp,%ebp + 41330d: e8 8e 30 00 00 callq 4163a0 <_IO_unsave_markers> + 413312: f6 43 74 20 testb $0x20,0x74(%rbx) + 413316: 0f 84 d4 00 00 00 je 4133f0 <_IO_new_file_close_it+0x110> + 41331c: 8b 83 c0 00 00 00 mov 0xc0(%rbx),%eax + 413322: 85 c0 test %eax,%eax + 413324: 7e 5a jle 413380 <_IO_new_file_close_it+0xa0> + 413326: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 41332d: 48 83 78 40 00 cmpq $0x0,0x40(%rax) + 413332: 74 08 je 41333c <_IO_new_file_close_it+0x5c> + 413334: 48 89 df mov %rbx,%rdi + 413337: e8 e4 14 05 00 callq 464820 <_IO_free_wbackup_area> + 41333c: 31 c9 xor %ecx,%ecx + 41333e: 31 d2 xor %edx,%edx + 413340: 31 f6 xor %esi,%esi + 413342: 48 89 df mov %rbx,%rdi + 413345: e8 46 05 05 00 callq 463890 <_IO_wsetb> + 41334a: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 413351: 48 c7 40 10 00 00 00 movq $0x0,0x10(%rax) + 413358: 00 + 413359: 48 c7 00 00 00 00 00 movq $0x0,(%rax) + 413360: 48 c7 40 08 00 00 00 movq $0x0,0x8(%rax) + 413367: 00 + 413368: 48 c7 40 20 00 00 00 movq $0x0,0x20(%rax) + 41336f: 00 + 413370: 48 c7 40 18 00 00 00 movq $0x0,0x18(%rax) + 413377: 00 + 413378: 48 c7 40 28 00 00 00 movq $0x0,0x28(%rax) + 41337f: 00 + 413380: 31 c9 xor %ecx,%ecx + 413382: 31 d2 xor %edx,%edx + 413384: 31 f6 xor %esi,%esi + 413386: 48 89 df mov %rbx,%rdi + 413389: e8 12 1a 00 00 callq 414da0 <_IO_setb> + 41338e: 48 c7 43 18 00 00 00 movq $0x0,0x18(%rbx) + 413395: 00 + 413396: 48 c7 43 08 00 00 00 movq $0x0,0x8(%rbx) + 41339d: 00 + 41339e: 48 89 df mov %rbx,%rdi + 4133a1: 48 c7 43 10 00 00 00 movq $0x0,0x10(%rbx) + 4133a8: 00 + 4133a9: 48 c7 43 28 00 00 00 movq $0x0,0x28(%rbx) + 4133b0: 00 + 4133b1: 48 c7 43 20 00 00 00 movq $0x0,0x20(%rbx) + 4133b8: 00 + 4133b9: 48 c7 43 30 00 00 00 movq $0x0,0x30(%rbx) + 4133c0: 00 + 4133c1: e8 8a 10 00 00 callq 414450 <_IO_un_link> + 4133c6: 85 ed test %ebp,%ebp + 4133c8: 44 89 e0 mov %r12d,%eax + 4133cb: c7 03 0c 24 ad fb movl $0xfbad240c,(%rbx) + 4133d1: c7 43 70 ff ff ff ff movl $0xffffffff,0x70(%rbx) + 4133d8: 48 c7 83 90 00 00 00 movq $0xffffffffffffffff,0x90(%rbx) + 4133df: ff ff ff ff + 4133e3: 0f 45 c5 cmovne %ebp,%eax + 4133e6: 5b pop %rbx + 4133e7: 5d pop %rbp + 4133e8: 41 5c pop %r12 + 4133ea: f3 c3 repz retq + 4133ec: 0f 1f 40 00 nopl 0x0(%rax) + 4133f0: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 4133f7: 48 89 df mov %rbx,%rdi + 4133fa: ff 90 88 00 00 00 callq *0x88(%rax) + 413400: 89 c5 mov %eax,%ebp + 413402: e9 15 ff ff ff jmpq 41331c <_IO_new_file_close_it+0x3c> + 413407: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 41340e: 00 00 + 413410: 8b 97 c0 00 00 00 mov 0xc0(%rdi),%edx + 413416: 85 d2 test %edx,%edx + 413418: 7e 26 jle 413440 <_IO_new_file_close_it+0x160> + 41341a: 48 8b 87 a0 00 00 00 mov 0xa0(%rdi),%rax + 413421: 48 8b 70 18 mov 0x18(%rax),%rsi + 413425: 48 8b 50 20 mov 0x20(%rax),%rdx + 413429: 48 29 f2 sub %rsi,%rdx + 41342c: 48 c1 fa 02 sar $0x2,%rdx + 413430: e8 fb d5 ff ff callq 410a30 <_IO_wdo_write> + 413435: 41 89 c4 mov %eax,%r12d + 413438: e9 cb fe ff ff jmpq 413308 <_IO_new_file_close_it+0x28> + 41343d: 0f 1f 00 nopl (%rax) + 413440: 48 8b 77 20 mov 0x20(%rdi),%rsi + 413444: 48 8b 57 28 mov 0x28(%rdi),%rdx + 413448: 48 29 f2 sub %rsi,%rdx + 41344b: e8 80 fd ff ff callq 4131d0 <_IO_new_do_write> + 413450: 41 89 c4 mov %eax,%r12d + 413453: e9 b0 fe ff ff jmpq 413308 <_IO_new_file_close_it+0x28> + 413458: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 41345f: 00 + +0000000000413460 <_IO_new_file_fopen>: + 413460: 41 57 push %r15 + 413462: 41 56 push %r14 + 413464: 41 55 push %r13 + 413466: 41 54 push %r12 + 413468: 55 push %rbp + 413469: 53 push %rbx + 41346a: 48 83 ec 28 sub $0x28,%rsp + 41346e: 83 7f 70 ff cmpl $0xffffffff,0x70(%rdi) + 413472: 75 54 jne 4134c8 <_IO_new_file_fopen+0x68> + 413474: 0f b6 02 movzbl (%rdx),%eax + 413477: 3c 72 cmp $0x72,%al + 413479: 0f 84 51 05 00 00 je 4139d0 <_IO_new_file_fopen+0x570> + 41347f: 3c 77 cmp $0x77,%al + 413481: 74 5d je 4134e0 <_IO_new_file_fopen+0x80> + 413483: 3c 61 cmp $0x61,%al + 413485: 0f 84 25 05 00 00 je 4139b0 <_IO_new_file_fopen+0x550> + 41348b: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 413492: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) + 413499: 48 83 c4 28 add $0x28,%rsp + 41349d: 31 c0 xor %eax,%eax + 41349f: 5b pop %rbx + 4134a0: 5d pop %rbp + 4134a1: 41 5c pop %r12 + 4134a3: 41 5d pop %r13 + 4134a5: 41 5e pop %r14 + 4134a7: 41 5f pop %r15 + 4134a9: c3 retq + 4134aa: 48 c7 c5 d0 ff ff ff mov $0xffffffffffffffd0,%rbp + 4134b1: 48 89 df mov %rbx,%rdi + 4134b4: 64 44 8b 65 00 mov %fs:0x0(%rbp),%r12d + 4134b9: e8 22 fe ff ff callq 4132e0 <_IO_new_file_close_it> + 4134be: 64 44 89 65 00 mov %r12d,%fs:0x0(%rbp) + 4134c3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4134c8: 31 c0 xor %eax,%eax + 4134ca: 48 83 c4 28 add $0x28,%rsp + 4134ce: 5b pop %rbx + 4134cf: 5d pop %rbp + 4134d0: 41 5c pop %r12 + 4134d2: 41 5d pop %r13 + 4134d4: 41 5e pop %r14 + 4134d6: 41 5f pop %r15 + 4134d8: c3 retq + 4134d9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4134e0: 41 b8 04 00 00 00 mov $0x4,%r8d + 4134e6: b8 01 00 00 00 mov $0x1,%eax + 4134eb: 41 ba 40 02 00 00 mov $0x240,%r10d + 4134f1: 44 0f b6 4a 01 movzbl 0x1(%rdx),%r9d + 4134f6: 4c 8d 62 01 lea 0x1(%rdx),%r12 + 4134fa: 41 80 f9 63 cmp $0x63,%r9b + 4134fe: 0f 84 bb 05 00 00 je 413abf <_IO_new_file_fopen+0x65f> + 413504: 0f 8f ee 03 00 00 jg 4138f8 <_IO_new_file_fopen+0x498> + 41350a: 41 80 f9 2b cmp $0x2b,%r9b + 41350e: 0f 84 c3 05 00 00 je 413ad7 <_IO_new_file_fopen+0x677> + 413514: 41 80 f9 62 cmp $0x62,%r9b + 413518: 74 16 je 413530 <_IO_new_file_fopen+0xd0> + 41351a: 45 84 c9 test %r9b,%r9b + 41351d: 49 89 d4 mov %rdx,%r12 + 413520: 0f 84 2a 01 00 00 je 413650 <_IO_new_file_fopen+0x1f0> + 413526: 49 89 d4 mov %rdx,%r12 + 413529: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 413530: 44 0f b6 4a 02 movzbl 0x2(%rdx),%r9d + 413535: 4c 8d 5a 02 lea 0x2(%rdx),%r11 + 413539: 41 80 f9 63 cmp $0x63,%r9b + 41353d: 0f 84 ae 05 00 00 je 413af1 <_IO_new_file_fopen+0x691> + 413543: 0f 8f 07 04 00 00 jg 413950 <_IO_new_file_fopen+0x4f0> + 413549: 41 80 f9 2b cmp $0x2b,%r9b + 41354d: 0f 84 a7 05 00 00 je 413afa <_IO_new_file_fopen+0x69a> + 413553: 41 80 f9 62 cmp $0x62,%r9b + 413557: 0f 84 12 05 00 00 je 413a6f <_IO_new_file_fopen+0x60f> + 41355d: 45 84 c9 test %r9b,%r9b + 413560: 0f 84 ea 00 00 00 je 413650 <_IO_new_file_fopen+0x1f0> + 413566: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41356d: 00 00 00 + 413570: 44 0f b6 4a 03 movzbl 0x3(%rdx),%r9d + 413575: 4c 8d 5a 03 lea 0x3(%rdx),%r11 + 413579: 41 80 f9 63 cmp $0x63,%r9b + 41357d: 0f 84 9f 05 00 00 je 413b22 <_IO_new_file_fopen+0x6c2> + 413583: 0f 8f f7 03 00 00 jg 413980 <_IO_new_file_fopen+0x520> + 413589: 41 80 f9 2b cmp $0x2b,%r9b + 41358d: 0f 84 7b 05 00 00 je 413b0e <_IO_new_file_fopen+0x6ae> + 413593: 41 80 f9 62 cmp $0x62,%r9b + 413597: 0f 84 f9 04 00 00 je 413a96 <_IO_new_file_fopen+0x636> + 41359d: 45 84 c9 test %r9b,%r9b + 4135a0: 0f 84 aa 00 00 00 je 413650 <_IO_new_file_fopen+0x1f0> + 4135a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4135ad: 00 00 00 + 4135b0: 44 0f b6 4a 04 movzbl 0x4(%rdx),%r9d + 4135b5: 4c 8d 5a 04 lea 0x4(%rdx),%r11 + 4135b9: 41 80 f9 63 cmp $0x63,%r9b + 4135bd: 0f 84 85 05 00 00 je 413b48 <_IO_new_file_fopen+0x6e8> + 4135c3: 0f 8f 17 04 00 00 jg 4139e0 <_IO_new_file_fopen+0x580> + 4135c9: 41 80 f9 2b cmp $0x2b,%r9b + 4135cd: 0f 84 61 05 00 00 je 413b34 <_IO_new_file_fopen+0x6d4> + 4135d3: 41 80 f9 62 cmp $0x62,%r9b + 4135d7: 0f 84 c5 04 00 00 je 413aa2 <_IO_new_file_fopen+0x642> + 4135dd: 45 84 c9 test %r9b,%r9b + 4135e0: 74 6e je 413650 <_IO_new_file_fopen+0x1f0> + 4135e2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4135e8: 44 0f b6 4a 05 movzbl 0x5(%rdx),%r9d + 4135ed: 4c 8d 5a 05 lea 0x5(%rdx),%r11 + 4135f1: 41 80 f9 63 cmp $0x63,%r9b + 4135f5: 0f 84 7c 05 00 00 je 413b77 <_IO_new_file_fopen+0x717> + 4135fb: 0f 8f 0f 04 00 00 jg 413a10 <_IO_new_file_fopen+0x5b0> + 413601: 41 80 f9 2b cmp $0x2b,%r9b + 413605: 0f 84 58 05 00 00 je 413b63 <_IO_new_file_fopen+0x703> + 41360b: 41 80 f9 62 cmp $0x62,%r9b + 41360f: 0f 84 99 04 00 00 je 413aae <_IO_new_file_fopen+0x64e> + 413615: 45 84 c9 test %r9b,%r9b + 413618: 74 36 je 413650 <_IO_new_file_fopen+0x1f0> + 41361a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 413620: 4c 8d 4a 06 lea 0x6(%rdx),%r9 + 413624: 0f b6 52 06 movzbl 0x6(%rdx),%edx + 413628: 80 fa 63 cmp $0x63,%dl + 41362b: 0f 84 88 05 00 00 je 413bb9 <_IO_new_file_fopen+0x759> + 413631: 0f 8f 09 04 00 00 jg 413a40 <_IO_new_file_fopen+0x5e0> + 413637: 80 fa 2b cmp $0x2b,%dl + 41363a: 0f 84 65 05 00 00 je 413ba5 <_IO_new_file_fopen+0x745> + 413640: 80 fa 62 cmp $0x62,%dl + 413643: 4d 0f 44 e1 cmove %r9,%r12 + 413647: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 41364e: 00 00 + 413650: 44 89 d2 mov %r10d,%edx + 413653: 41 89 c9 mov %ecx,%r9d + 413656: b9 b6 01 00 00 mov $0x1b6,%ecx + 41365b: 09 c2 or %eax,%edx + 41365d: 48 89 fb mov %rdi,%rbx + 413660: e8 fb f9 ff ff callq 413060 <_IO_file_open> + 413665: 48 85 c0 test %rax,%rax + 413668: 48 89 c5 mov %rax,%rbp + 41366b: 0f 84 57 fe ff ff je 4134c8 <_IO_new_file_fopen+0x68> + 413671: 49 8d 7c 24 01 lea 0x1(%r12),%rdi + 413676: be 30 1c 4a 00 mov $0x4a1c30,%esi + 41367b: e8 a0 cc fe ff callq 400320 <__rela_iplt_end+0x58> + 413680: 48 85 c0 test %rax,%rax + 413683: 49 89 c5 mov %rax,%r13 + 413686: 0f 84 f4 03 00 00 je 413a80 <_IO_new_file_fopen+0x620> + 41368c: 4c 8d 78 05 lea 0x5(%rax),%r15 + 413690: be 2c 00 00 00 mov $0x2c,%esi + 413695: 4c 89 ff mov %r15,%rdi + 413698: e8 43 95 01 00 callq 42cbe0 <__strchrnul> + 41369d: 4c 29 f8 sub %r15,%rax + 4136a0: 48 8d 78 03 lea 0x3(%rax),%rdi + 4136a4: 49 89 c6 mov %rax,%r14 + 4136a7: e8 64 a3 00 00 callq 41da10 <__libc_malloc> + 4136ac: 48 85 c0 test %rax,%rax + 4136af: 49 89 c4 mov %rax,%r12 + 4136b2: 0f 84 f2 fd ff ff je 4134aa <_IO_new_file_fopen+0x4a> + 4136b8: 4c 89 f2 mov %r14,%rdx + 4136bb: 4c 89 fe mov %r15,%rsi + 4136be: 48 89 c7 mov %rax,%rdi + 4136c1: e8 fa 2e 01 00 callq 4265c0 <__mempcpy> + 4136c6: c6 00 00 movb $0x0,(%rax) + 4136c9: 45 0f b6 04 24 movzbl (%r12),%r8d + 4136ce: 45 84 c0 test %r8b,%r8b + 4136d1: 0f 84 08 05 00 00 je 413bdf <_IO_new_file_fopen+0x77f> + 4136d7: 4c 8b 1d 0a f0 09 00 mov 0x9f00a(%rip),%r11 # 4b26e8 <_nl_C_locobj+0x68> + 4136de: 4c 8b 35 13 f0 09 00 mov 0x9f013(%rip),%r14 # 4b26f8 <_nl_C_locobj+0x78> + 4136e5: 4d 89 e1 mov %r12,%r9 + 4136e8: 4c 89 e0 mov %r12,%rax + 4136eb: 45 31 ff xor %r15d,%r15d + 4136ee: 49 ba 07 40 00 00 00 movabs $0x8000000004007,%r10 + 4136f5: 00 08 00 + 4136f8: eb 26 jmp 413720 <_IO_new_file_fopen+0x2c0> + 4136fa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 413700: 41 80 f8 2f cmp $0x2f,%r8b + 413704: 0f 84 26 02 00 00 je 413930 <_IO_new_file_fopen+0x4d0> + 41370a: 49 83 c1 01 add $0x1,%r9 + 41370e: 45 0f b6 01 movzbl (%r9),%r8d + 413712: 45 84 c0 test %r8b,%r8b + 413715: 74 54 je 41376b <_IO_new_file_fopen+0x30b> + 413717: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 41371e: 00 00 + 413720: 49 0f be f8 movsbq %r8b,%rdi + 413724: 41 8d 48 d4 lea -0x2c(%r8),%ecx + 413728: ba 01 00 00 00 mov $0x1,%edx + 41372d: 41 0f b7 34 7b movzwl (%r11,%rdi,2),%esi + 413732: 66 c1 ee 03 shr $0x3,%si + 413736: 83 e6 01 and $0x1,%esi + 413739: 80 f9 33 cmp $0x33,%cl + 41373c: 77 10 ja 41374e <_IO_new_file_fopen+0x2ee> + 41373e: 4c 89 d2 mov %r10,%rdx + 413741: 48 d3 ea shr %cl,%rdx + 413744: 83 e2 01 and $0x1,%edx + 413747: 48 83 f2 01 xor $0x1,%rdx + 41374b: 83 e2 01 and $0x1,%edx + 41374e: 40 38 f2 cmp %sil,%dl + 413751: 77 ad ja 413700 <_IO_new_file_fopen+0x2a0> + 413753: 41 8b 14 be mov (%r14,%rdi,4),%edx + 413757: 49 83 c1 01 add $0x1,%r9 + 41375b: 48 83 c0 01 add $0x1,%rax + 41375f: 88 50 ff mov %dl,-0x1(%rax) + 413762: 45 0f b6 01 movzbl (%r9),%r8d + 413766: 45 84 c0 test %r8b,%r8b + 413769: 75 b5 jne 413720 <_IO_new_file_fopen+0x2c0> + 41376b: 41 83 ff 01 cmp $0x1,%r15d + 41376f: 7f 17 jg 413788 <_IO_new_file_fopen+0x328> + 413771: 45 85 ff test %r15d,%r15d + 413774: 48 8d 50 01 lea 0x1(%rax),%rdx + 413778: c6 00 2f movb $0x2f,(%rax) + 41377b: 0f 85 56 04 00 00 jne 413bd7 <_IO_new_file_fopen+0x777> + 413781: 48 8d 42 01 lea 0x1(%rdx),%rax + 413785: c6 02 2f movb $0x2f,(%rdx) + 413788: c6 00 00 movb $0x0,(%rax) + 41378b: 41 80 7c 24 02 00 cmpb $0x0,0x2(%r12) + 413791: 75 22 jne 4137b5 <_IO_new_file_fopen+0x355> + 413793: 48 8b 0d 5e ef 09 00 mov 0x9ef5e(%rip),%rcx # 4b26f8 <_nl_C_locobj+0x78> + 41379a: 31 c0 xor %eax,%eax + 41379c: 0f 1f 40 00 nopl 0x0(%rax) + 4137a0: 49 0f be 54 05 05 movsbq 0x5(%r13,%rax,1),%rdx + 4137a6: 8b 14 91 mov (%rcx,%rdx,4),%edx + 4137a9: 41 88 14 04 mov %dl,(%r12,%rax,1) + 4137ad: 48 83 c0 01 add $0x1,%rax + 4137b1: 84 d2 test %dl,%dl + 4137b3: 75 eb jne 4137a0 <_IO_new_file_fopen+0x340> + 4137b5: 4c 89 e6 mov %r12,%rsi + 4137b8: 48 89 e7 mov %rsp,%rdi + 4137bb: e8 10 af 02 00 callq 43e6d0 <__wcsmbs_named_conv> + 4137c0: 85 c0 test %eax,%eax + 4137c2: 0f 85 b8 03 00 00 jne 413b80 <_IO_new_file_fopen+0x720> + 4137c8: 4c 89 e7 mov %r12,%rdi + 4137cb: e8 e0 a5 00 00 callq 41ddb0 <__cfree> + 4137d0: 48 83 7c 24 08 01 cmpq $0x1,0x8(%rsp) + 4137d6: 0f 85 2b 04 00 00 jne 413c07 <_IO_new_file_fopen+0x7a7> + 4137dc: 48 83 7c 24 18 01 cmpq $0x1,0x18(%rsp) + 4137e2: 0f 85 06 04 00 00 jne 413bee <_IO_new_file_fopen+0x78e> + 4137e8: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 4137ef: be e0 45 4b 00 mov $0x4b45e0,%esi + 4137f4: b9 18 00 00 00 mov $0x18,%ecx + 4137f9: 48 8b 50 08 mov 0x8(%rax),%rdx + 4137fd: 48 c7 40 58 00 00 00 movq $0x0,0x58(%rax) + 413804: 00 + 413805: 48 89 10 mov %rdx,(%rax) + 413808: 48 8b 50 18 mov 0x18(%rax),%rdx + 41380c: 48 89 50 20 mov %rdx,0x20(%rax) + 413810: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 413817: 48 c7 40 60 00 00 00 movq $0x0,0x60(%rax) + 41381e: 00 + 41381f: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 413826: 48 8d 50 68 lea 0x68(%rax),%rdx + 41382a: 48 89 93 98 00 00 00 mov %rdx,0x98(%rbx) + 413831: 48 89 d7 mov %rdx,%rdi + 413834: 48 8b 14 24 mov (%rsp),%rdx + 413838: f3 48 a5 rep movsq %ds:(%rsi),%es:(%rdi) + 41383b: 48 c7 80 a8 00 00 00 movq $0x1,0xa8(%rax) + 413842: 01 00 00 00 + 413846: c7 80 cc 00 00 00 00 movl $0x0,0xcc(%rax) + 41384d: 00 00 00 + 413850: 48 89 90 b0 00 00 00 mov %rdx,0xb0(%rax) + 413857: c7 80 d0 00 00 00 01 movl $0x1,0xd0(%rax) + 41385e: 00 00 00 + 413861: c7 80 c8 00 00 00 01 movl $0x1,0xc8(%rax) + 413868: 00 00 00 + 41386b: 48 8b 8d a0 00 00 00 mov 0xa0(%rbp),%rcx + 413872: 48 c7 80 e8 00 00 00 movq $0x1,0xe8(%rax) + 413879: 01 00 00 00 + 41387d: c7 80 0c 01 00 00 00 movl $0x0,0x10c(%rax) + 413884: 00 00 00 + 413887: c7 80 10 01 00 00 01 movl $0x1,0x110(%rax) + 41388e: 00 00 00 + 413891: c7 80 08 01 00 00 09 movl $0x9,0x108(%rax) + 413898: 00 00 00 + 41389b: 48 8d 51 58 lea 0x58(%rcx),%rdx + 41389f: 48 89 90 d8 00 00 00 mov %rdx,0xd8(%rax) + 4138a6: 48 8b 54 24 10 mov 0x10(%rsp),%rdx + 4138ab: 48 89 90 f0 00 00 00 mov %rdx,0xf0(%rax) + 4138b2: 48 8b 8d a0 00 00 00 mov 0xa0(%rbp),%rcx + 4138b9: 48 8d 51 58 lea 0x58(%rcx),%rdx + 4138bd: 48 89 90 18 01 00 00 mov %rdx,0x118(%rax) + 4138c4: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 4138cb: 48 8b 80 30 01 00 00 mov 0x130(%rax),%rax + 4138d2: 48 89 83 d8 00 00 00 mov %rax,0xd8(%rbx) + 4138d9: c7 85 c0 00 00 00 01 movl $0x1,0xc0(%rbp) + 4138e0: 00 00 00 + 4138e3: 48 83 c4 28 add $0x28,%rsp + 4138e7: 5b pop %rbx + 4138e8: 48 89 e8 mov %rbp,%rax + 4138eb: 5d pop %rbp + 4138ec: 41 5c pop %r12 + 4138ee: 41 5d pop %r13 + 4138f0: 41 5e pop %r14 + 4138f2: 41 5f pop %r15 + 4138f4: c3 retq + 4138f5: 0f 1f 00 nopl (%rax) + 4138f8: 41 80 f9 6d cmp $0x6d,%r9b + 4138fc: 0f 84 c9 01 00 00 je 413acb <_IO_new_file_fopen+0x66b> + 413902: 41 80 f9 78 cmp $0x78,%r9b + 413906: 0f 84 aa 01 00 00 je 413ab6 <_IO_new_file_fopen+0x656> + 41390c: 41 80 f9 65 cmp $0x65,%r9b + 413910: 0f 85 10 fc ff ff jne 413526 <_IO_new_file_fopen+0xc6> + 413916: 41 81 ca 00 00 08 00 or $0x80000,%r10d + 41391d: 83 4f 74 40 orl $0x40,0x74(%rdi) + 413921: 49 89 d4 mov %rdx,%r12 + 413924: e9 07 fc ff ff jmpq 413530 <_IO_new_file_fopen+0xd0> + 413929: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 413930: 41 83 c7 01 add $0x1,%r15d + 413934: 41 83 ff 03 cmp $0x3,%r15d + 413938: 0f 84 4a fe ff ff je 413788 <_IO_new_file_fopen+0x328> + 41393e: c6 00 2f movb $0x2f,(%rax) + 413941: 48 83 c0 01 add $0x1,%rax + 413945: e9 c0 fd ff ff jmpq 41370a <_IO_new_file_fopen+0x2aa> + 41394a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 413950: 41 80 f9 6d cmp $0x6d,%r9b + 413954: 0f 84 8e 01 00 00 je 413ae8 <_IO_new_file_fopen+0x688> + 41395a: 41 80 f9 78 cmp $0x78,%r9b + 41395e: 0f 84 07 01 00 00 je 413a6b <_IO_new_file_fopen+0x60b> + 413964: 41 80 f9 65 cmp $0x65,%r9b + 413968: 0f 85 02 fc ff ff jne 413570 <_IO_new_file_fopen+0x110> + 41396e: 41 81 ca 00 00 08 00 or $0x80000,%r10d + 413975: 83 4f 74 40 orl $0x40,0x74(%rdi) + 413979: e9 f2 fb ff ff jmpq 413570 <_IO_new_file_fopen+0x110> + 41397e: 66 90 xchg %ax,%ax + 413980: 41 80 f9 6d cmp $0x6d,%r9b + 413984: 0f 84 a1 01 00 00 je 413b2b <_IO_new_file_fopen+0x6cb> + 41398a: 41 80 f9 78 cmp $0x78,%r9b + 41398e: 0f 84 fe 00 00 00 je 413a92 <_IO_new_file_fopen+0x632> + 413994: 41 80 f9 65 cmp $0x65,%r9b + 413998: 0f 85 12 fc ff ff jne 4135b0 <_IO_new_file_fopen+0x150> + 41399e: 41 81 ca 00 00 08 00 or $0x80000,%r10d + 4139a5: 83 4f 74 40 orl $0x40,0x74(%rdi) + 4139a9: e9 02 fc ff ff jmpq 4135b0 <_IO_new_file_fopen+0x150> + 4139ae: 66 90 xchg %ax,%ax + 4139b0: 41 b8 04 10 00 00 mov $0x1004,%r8d + 4139b6: b8 01 00 00 00 mov $0x1,%eax + 4139bb: 41 ba 40 04 00 00 mov $0x440,%r10d + 4139c1: e9 2b fb ff ff jmpq 4134f1 <_IO_new_file_fopen+0x91> + 4139c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4139cd: 00 00 00 + 4139d0: 41 b8 08 00 00 00 mov $0x8,%r8d + 4139d6: 31 c0 xor %eax,%eax + 4139d8: 45 31 d2 xor %r10d,%r10d + 4139db: e9 11 fb ff ff jmpq 4134f1 <_IO_new_file_fopen+0x91> + 4139e0: 41 80 f9 6d cmp $0x6d,%r9b + 4139e4: 0f 84 67 01 00 00 je 413b51 <_IO_new_file_fopen+0x6f1> + 4139ea: 41 80 f9 78 cmp $0x78,%r9b + 4139ee: 0f 84 aa 00 00 00 je 413a9e <_IO_new_file_fopen+0x63e> + 4139f4: 41 80 f9 65 cmp $0x65,%r9b + 4139f8: 0f 85 ea fb ff ff jne 4135e8 <_IO_new_file_fopen+0x188> + 4139fe: 41 81 ca 00 00 08 00 or $0x80000,%r10d + 413a05: 83 4f 74 40 orl $0x40,0x74(%rdi) + 413a09: e9 da fb ff ff jmpq 4135e8 <_IO_new_file_fopen+0x188> + 413a0e: 66 90 xchg %ax,%ax + 413a10: 41 80 f9 6d cmp $0x6d,%r9b + 413a14: 0f 84 40 01 00 00 je 413b5a <_IO_new_file_fopen+0x6fa> + 413a1a: 41 80 f9 78 cmp $0x78,%r9b + 413a1e: 0f 84 86 00 00 00 je 413aaa <_IO_new_file_fopen+0x64a> + 413a24: 41 80 f9 65 cmp $0x65,%r9b + 413a28: 0f 85 f2 fb ff ff jne 413620 <_IO_new_file_fopen+0x1c0> + 413a2e: 41 81 ca 00 00 08 00 or $0x80000,%r10d + 413a35: 83 4f 74 40 orl $0x40,0x74(%rdi) + 413a39: e9 e2 fb ff ff jmpq 413620 <_IO_new_file_fopen+0x1c0> + 413a3e: 66 90 xchg %ax,%ax + 413a40: 80 fa 6d cmp $0x6d,%dl + 413a43: 0f 84 79 01 00 00 je 413bc2 <_IO_new_file_fopen+0x762> + 413a49: 80 fa 78 cmp $0x78,%dl + 413a4c: 0f 84 79 01 00 00 je 413bcb <_IO_new_file_fopen+0x76b> + 413a52: 80 fa 65 cmp $0x65,%dl + 413a55: 0f 85 f5 fb ff ff jne 413650 <_IO_new_file_fopen+0x1f0> + 413a5b: 41 81 ca 00 00 08 00 or $0x80000,%r10d + 413a62: 83 4f 74 40 orl $0x40,0x74(%rdi) + 413a66: e9 e5 fb ff ff jmpq 413650 <_IO_new_file_fopen+0x1f0> + 413a6b: 41 80 ca 80 or $0x80,%r10b + 413a6f: 4d 89 dc mov %r11,%r12 + 413a72: e9 f9 fa ff ff jmpq 413570 <_IO_new_file_fopen+0x110> + 413a77: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 413a7e: 00 00 + 413a80: 48 83 c4 28 add $0x28,%rsp + 413a84: 48 89 e8 mov %rbp,%rax + 413a87: 5b pop %rbx + 413a88: 5d pop %rbp + 413a89: 41 5c pop %r12 + 413a8b: 41 5d pop %r13 + 413a8d: 41 5e pop %r14 + 413a8f: 41 5f pop %r15 + 413a91: c3 retq + 413a92: 41 80 ca 80 or $0x80,%r10b + 413a96: 4d 89 dc mov %r11,%r12 + 413a99: e9 12 fb ff ff jmpq 4135b0 <_IO_new_file_fopen+0x150> + 413a9e: 41 80 ca 80 or $0x80,%r10b + 413aa2: 4d 89 dc mov %r11,%r12 + 413aa5: e9 3e fb ff ff jmpq 4135e8 <_IO_new_file_fopen+0x188> + 413aaa: 41 80 ca 80 or $0x80,%r10b + 413aae: 4d 89 dc mov %r11,%r12 + 413ab1: e9 6a fb ff ff jmpq 413620 <_IO_new_file_fopen+0x1c0> + 413ab6: 41 80 ca 80 or $0x80,%r10b + 413aba: e9 71 fa ff ff jmpq 413530 <_IO_new_file_fopen+0xd0> + 413abf: 83 4f 74 02 orl $0x2,0x74(%rdi) + 413ac3: 49 89 d4 mov %rdx,%r12 + 413ac6: e9 65 fa ff ff jmpq 413530 <_IO_new_file_fopen+0xd0> + 413acb: 83 4f 74 01 orl $0x1,0x74(%rdi) + 413acf: 49 89 d4 mov %rdx,%r12 + 413ad2: e9 59 fa ff ff jmpq 413530 <_IO_new_file_fopen+0xd0> + 413ad7: 41 81 e0 00 10 00 00 and $0x1000,%r8d + 413ade: b8 02 00 00 00 mov $0x2,%eax + 413ae3: e9 48 fa ff ff jmpq 413530 <_IO_new_file_fopen+0xd0> + 413ae8: 83 4f 74 01 orl $0x1,0x74(%rdi) + 413aec: e9 7f fa ff ff jmpq 413570 <_IO_new_file_fopen+0x110> + 413af1: 83 4f 74 02 orl $0x2,0x74(%rdi) + 413af5: e9 76 fa ff ff jmpq 413570 <_IO_new_file_fopen+0x110> + 413afa: 41 81 e0 00 10 00 00 and $0x1000,%r8d + 413b01: 4d 89 dc mov %r11,%r12 + 413b04: b8 02 00 00 00 mov $0x2,%eax + 413b09: e9 62 fa ff ff jmpq 413570 <_IO_new_file_fopen+0x110> + 413b0e: 41 81 e0 00 10 00 00 and $0x1000,%r8d + 413b15: 4d 89 dc mov %r11,%r12 + 413b18: b8 02 00 00 00 mov $0x2,%eax + 413b1d: e9 8e fa ff ff jmpq 4135b0 <_IO_new_file_fopen+0x150> + 413b22: 83 4f 74 02 orl $0x2,0x74(%rdi) + 413b26: e9 85 fa ff ff jmpq 4135b0 <_IO_new_file_fopen+0x150> + 413b2b: 83 4f 74 01 orl $0x1,0x74(%rdi) + 413b2f: e9 7c fa ff ff jmpq 4135b0 <_IO_new_file_fopen+0x150> + 413b34: 41 81 e0 00 10 00 00 and $0x1000,%r8d + 413b3b: 4d 89 dc mov %r11,%r12 + 413b3e: b8 02 00 00 00 mov $0x2,%eax + 413b43: e9 a0 fa ff ff jmpq 4135e8 <_IO_new_file_fopen+0x188> + 413b48: 83 4f 74 02 orl $0x2,0x74(%rdi) + 413b4c: e9 97 fa ff ff jmpq 4135e8 <_IO_new_file_fopen+0x188> + 413b51: 83 4f 74 01 orl $0x1,0x74(%rdi) + 413b55: e9 8e fa ff ff jmpq 4135e8 <_IO_new_file_fopen+0x188> + 413b5a: 83 4f 74 01 orl $0x1,0x74(%rdi) + 413b5e: e9 bd fa ff ff jmpq 413620 <_IO_new_file_fopen+0x1c0> + 413b63: 41 81 e0 00 10 00 00 and $0x1000,%r8d + 413b6a: 4d 89 dc mov %r11,%r12 + 413b6d: b8 02 00 00 00 mov $0x2,%eax + 413b72: e9 a9 fa ff ff jmpq 413620 <_IO_new_file_fopen+0x1c0> + 413b77: 83 4f 74 02 orl $0x2,0x74(%rdi) + 413b7b: e9 a0 fa ff ff jmpq 413620 <_IO_new_file_fopen+0x1c0> + 413b80: 48 89 df mov %rbx,%rdi + 413b83: e8 58 f7 ff ff callq 4132e0 <_IO_new_file_close_it> + 413b88: 4c 89 e7 mov %r12,%rdi + 413b8b: e8 20 a2 00 00 callq 41ddb0 <__cfree> + 413b90: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 413b97: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) + 413b9e: 31 c0 xor %eax,%eax + 413ba0: e9 25 f9 ff ff jmpq 4134ca <_IO_new_file_fopen+0x6a> + 413ba5: 41 81 e0 00 10 00 00 and $0x1000,%r8d + 413bac: 4d 89 cc mov %r9,%r12 + 413baf: b8 02 00 00 00 mov $0x2,%eax + 413bb4: e9 97 fa ff ff jmpq 413650 <_IO_new_file_fopen+0x1f0> + 413bb9: 83 4f 74 02 orl $0x2,0x74(%rdi) + 413bbd: e9 8e fa ff ff jmpq 413650 <_IO_new_file_fopen+0x1f0> + 413bc2: 83 4f 74 01 orl $0x1,0x74(%rdi) + 413bc6: e9 85 fa ff ff jmpq 413650 <_IO_new_file_fopen+0x1f0> + 413bcb: 41 80 ca 80 or $0x80,%r10b + 413bcf: 4d 89 cc mov %r9,%r12 + 413bd2: e9 79 fa ff ff jmpq 413650 <_IO_new_file_fopen+0x1f0> + 413bd7: 48 89 d0 mov %rdx,%rax + 413bda: e9 a9 fb ff ff jmpq 413788 <_IO_new_file_fopen+0x328> + 413bdf: 49 8d 54 24 01 lea 0x1(%r12),%rdx + 413be4: 41 c6 04 24 2f movb $0x2f,(%r12) + 413be9: e9 93 fb ff ff jmpq 413781 <_IO_new_file_fopen+0x321> + 413bee: b9 70 1c 4a 00 mov $0x4a1c70,%ecx + 413bf3: ba 80 01 00 00 mov $0x180,%edx + 413bf8: be 54 19 4a 00 mov $0x4a1954,%esi + 413bfd: bf 4c 1c 4a 00 mov $0x4a1c4c,%edi + 413c02: e8 39 db fe ff callq 401740 <__assert_fail> + 413c07: b9 70 1c 4a 00 mov $0x4a1c70,%ecx + 413c0c: ba 7f 01 00 00 mov $0x17f,%edx + 413c11: be 54 19 4a 00 mov $0x4a1954,%esi + 413c16: bf 36 1c 4a 00 mov $0x4a1c36,%edi + 413c1b: e8 20 db fe ff callq 401740 <__assert_fail> + +0000000000413c20 <_IO_new_file_finish>: + 413c20: 53 push %rbx + 413c21: 83 7f 70 ff cmpl $0xffffffff,0x70(%rdi) + 413c25: 48 89 fb mov %rdi,%rbx + 413c28: 74 2a je 413c54 <_IO_new_file_finish+0x34> + 413c2a: 8b 87 c0 00 00 00 mov 0xc0(%rdi),%eax + 413c30: 85 c0 test %eax,%eax + 413c32: 7e 4c jle 413c80 <_IO_new_file_finish+0x60> + 413c34: 48 8b 87 a0 00 00 00 mov 0xa0(%rdi),%rax + 413c3b: 48 8b 70 18 mov 0x18(%rax),%rsi + 413c3f: 48 8b 50 20 mov 0x20(%rax),%rdx + 413c43: 48 29 f2 sub %rsi,%rdx + 413c46: 48 c1 fa 02 sar $0x2,%rdx + 413c4a: e8 e1 cd ff ff callq 410a30 <_IO_wdo_write> + 413c4f: f6 03 40 testb $0x40,(%rbx) + 413c52: 74 0c je 413c60 <_IO_new_file_finish+0x40> + 413c54: 48 89 df mov %rbx,%rdi + 413c57: 31 f6 xor %esi,%esi + 413c59: 5b pop %rbx + 413c5a: e9 b1 19 00 00 jmpq 415610 <_IO_default_finish> + 413c5f: 90 nop + 413c60: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 413c67: 48 89 df mov %rbx,%rdi + 413c6a: ff 90 88 00 00 00 callq *0x88(%rax) + 413c70: 48 89 df mov %rbx,%rdi + 413c73: 31 f6 xor %esi,%esi + 413c75: 5b pop %rbx + 413c76: e9 95 19 00 00 jmpq 415610 <_IO_default_finish> + 413c7b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 413c80: 48 8b 77 20 mov 0x20(%rdi),%rsi + 413c84: 48 8b 57 28 mov 0x28(%rdi),%rdx + 413c88: 48 29 f2 sub %rsi,%rdx + 413c8b: e8 40 f5 ff ff callq 4131d0 <_IO_new_do_write> + 413c90: eb bd jmp 413c4f <_IO_new_file_finish+0x2f> + 413c92: 0f 1f 40 00 nopl 0x0(%rax) + 413c96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 413c9d: 00 00 00 + +0000000000413ca0 <_IO_new_file_overflow>: + 413ca0: 8b 0f mov (%rdi),%ecx + 413ca2: f6 c1 08 test $0x8,%cl + 413ca5: 0f 85 95 01 00 00 jne 413e40 <_IO_new_file_overflow+0x1a0> + 413cab: f6 c5 08 test $0x8,%ch + 413cae: 41 54 push %r12 + 413cb0: 55 push %rbp + 413cb1: 89 f5 mov %esi,%ebp + 413cb3: 53 push %rbx + 413cb4: 48 89 fb mov %rdi,%rbx + 413cb7: 74 4f je 413d08 <_IO_new_file_overflow+0x68> + 413cb9: 48 8b 77 20 mov 0x20(%rdi),%rsi + 413cbd: 48 85 f6 test %rsi,%rsi + 413cc0: 0f 84 9a 01 00 00 je 413e60 <_IO_new_file_overflow+0x1c0> + 413cc6: 48 8b 57 28 mov 0x28(%rdi),%rdx + 413cca: 83 fd ff cmp $0xffffffff,%ebp + 413ccd: 0f 84 4d 01 00 00 je 413e20 <_IO_new_file_overflow+0x180> + 413cd3: 48 39 53 40 cmp %rdx,0x40(%rbx) + 413cd7: 0f 84 fb 00 00 00 je 413dd8 <_IO_new_file_overflow+0x138> + 413cdd: 48 8d 42 01 lea 0x1(%rdx),%rax + 413ce1: 48 89 43 28 mov %rax,0x28(%rbx) + 413ce5: 40 88 2a mov %bpl,(%rdx) + 413ce8: 8b 03 mov (%rbx),%eax + 413cea: a8 02 test $0x2,%al + 413cec: 0f 85 86 00 00 00 jne 413d78 <_IO_new_file_overflow+0xd8> + 413cf2: f6 c4 02 test $0x2,%ah + 413cf5: 74 05 je 413cfc <_IO_new_file_overflow+0x5c> + 413cf7: 83 fd 0a cmp $0xa,%ebp + 413cfa: 74 7c je 413d78 <_IO_new_file_overflow+0xd8> + 413cfc: 40 0f b6 c5 movzbl %bpl,%eax + 413d00: 5b pop %rbx + 413d01: 5d pop %rbp + 413d02: 41 5c pop %r12 + 413d04: c3 retq + 413d05: 0f 1f 00 nopl (%rax) + 413d08: 48 83 7f 20 00 cmpq $0x0,0x20(%rdi) + 413d0d: 0f 84 4d 01 00 00 je 413e60 <_IO_new_file_overflow+0x1c0> + 413d13: 48 8b 57 08 mov 0x8(%rdi),%rdx + 413d17: f6 c5 01 test $0x1,%ch + 413d1a: 0f 85 80 00 00 00 jne 413da0 <_IO_new_file_overflow+0x100> + 413d20: 48 8b 43 40 mov 0x40(%rbx),%rax + 413d24: 48 39 d0 cmp %rdx,%rax + 413d27: 0f 84 03 01 00 00 je 413e30 <_IO_new_file_overflow+0x190> + 413d2d: 48 8b 73 10 mov 0x10(%rbx),%rsi + 413d31: 8b bb c0 00 00 00 mov 0xc0(%rbx),%edi + 413d37: 48 89 43 30 mov %rax,0x30(%rbx) + 413d3b: 89 c8 mov %ecx,%eax + 413d3d: 80 cc 08 or $0x8,%ah + 413d40: 48 89 73 08 mov %rsi,0x8(%rbx) + 413d44: 48 89 73 18 mov %rsi,0x18(%rbx) + 413d48: 48 89 53 28 mov %rdx,0x28(%rbx) + 413d4c: 48 89 53 20 mov %rdx,0x20(%rbx) + 413d50: 48 89 d6 mov %rdx,%rsi + 413d53: 85 ff test %edi,%edi + 413d55: 89 03 mov %eax,(%rbx) + 413d57: 0f 8f 6d ff ff ff jg 413cca <_IO_new_file_overflow+0x2a> + 413d5d: 81 e1 02 02 00 00 and $0x202,%ecx + 413d63: 0f 84 61 ff ff ff je 413cca <_IO_new_file_overflow+0x2a> + 413d69: 48 89 53 30 mov %rdx,0x30(%rbx) + 413d6d: e9 58 ff ff ff jmpq 413cca <_IO_new_file_overflow+0x2a> + 413d72: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 413d78: 48 8b 73 20 mov 0x20(%rbx),%rsi + 413d7c: 48 8b 53 28 mov 0x28(%rbx),%rdx + 413d80: 48 89 df mov %rbx,%rdi + 413d83: 48 29 f2 sub %rsi,%rdx + 413d86: e8 45 f4 ff ff callq 4131d0 <_IO_new_do_write> + 413d8b: 83 f8 ff cmp $0xffffffff,%eax + 413d8e: 0f 85 68 ff ff ff jne 413cfc <_IO_new_file_overflow+0x5c> + 413d94: b8 ff ff ff ff mov $0xffffffff,%eax + 413d99: e9 62 ff ff ff jmpq 413d00 <_IO_new_file_overflow+0x60> + 413d9e: 66 90 xchg %ax,%ax + 413da0: 4c 8b 63 10 mov 0x10(%rbx),%r12 + 413da4: 48 89 df mov %rbx,%rdi + 413da7: 49 29 d4 sub %rdx,%r12 + 413daa: e8 81 0c 00 00 callq 414a30 <_IO_free_backup_area> + 413daf: 48 8b 53 18 mov 0x18(%rbx),%rdx + 413db3: 8b 0b mov (%rbx),%ecx + 413db5: 48 89 d0 mov %rdx,%rax + 413db8: 48 2b 43 38 sub 0x38(%rbx),%rax + 413dbc: 4c 39 e0 cmp %r12,%rax + 413dbf: 49 0f 47 c4 cmova %r12,%rax + 413dc3: 48 29 c2 sub %rax,%rdx + 413dc6: 48 89 53 18 mov %rdx,0x18(%rbx) + 413dca: 48 89 53 08 mov %rdx,0x8(%rbx) + 413dce: e9 4d ff ff ff jmpq 413d20 <_IO_new_file_overflow+0x80> + 413dd3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 413dd8: 8b 83 c0 00 00 00 mov 0xc0(%rbx),%eax + 413dde: 85 c0 test %eax,%eax + 413de0: 0f 8e 9a 00 00 00 jle 413e80 <_IO_new_file_overflow+0x1e0> + 413de6: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 413ded: 48 89 df mov %rbx,%rdi + 413df0: 48 8b 70 18 mov 0x18(%rax),%rsi + 413df4: 48 8b 50 20 mov 0x20(%rax),%rdx + 413df8: 48 29 f2 sub %rsi,%rdx + 413dfb: 48 c1 fa 02 sar $0x2,%rdx + 413dff: e8 2c cc ff ff callq 410a30 <_IO_wdo_write> + 413e04: 83 f8 ff cmp $0xffffffff,%eax + 413e07: 0f 94 c0 sete %al + 413e0a: 84 c0 test %al,%al + 413e0c: 0f 85 82 ff ff ff jne 413d94 <_IO_new_file_overflow+0xf4> + 413e12: 48 8b 53 28 mov 0x28(%rbx),%rdx + 413e16: e9 c2 fe ff ff jmpq 413cdd <_IO_new_file_overflow+0x3d> + 413e1b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 413e20: 48 89 df mov %rbx,%rdi + 413e23: 48 29 f2 sub %rsi,%rdx + 413e26: 5b pop %rbx + 413e27: 5d pop %rbp + 413e28: 41 5c pop %r12 + 413e2a: e9 a1 f3 ff ff jmpq 4131d0 <_IO_new_do_write> + 413e2f: 90 nop + 413e30: 48 8b 53 38 mov 0x38(%rbx),%rdx + 413e34: 48 89 53 10 mov %rdx,0x10(%rbx) + 413e38: 48 89 d6 mov %rdx,%rsi + 413e3b: e9 f1 fe ff ff jmpq 413d31 <_IO_new_file_overflow+0x91> + 413e40: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 413e47: 83 c9 20 or $0x20,%ecx + 413e4a: 89 0f mov %ecx,(%rdi) + 413e4c: 64 c7 00 09 00 00 00 movl $0x9,%fs:(%rax) + 413e53: b8 ff ff ff ff mov $0xffffffff,%eax + 413e58: c3 retq + 413e59: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 413e60: 48 89 df mov %rbx,%rdi + 413e63: e8 98 0f 00 00 callq 414e00 <_IO_doallocbuf> + 413e68: 48 8b 53 38 mov 0x38(%rbx),%rdx + 413e6c: 8b 0b mov (%rbx),%ecx + 413e6e: 48 89 53 18 mov %rdx,0x18(%rbx) + 413e72: 48 89 53 08 mov %rdx,0x8(%rbx) + 413e76: 48 89 53 10 mov %rdx,0x10(%rbx) + 413e7a: e9 98 fe ff ff jmpq 413d17 <_IO_new_file_overflow+0x77> + 413e7f: 90 nop + 413e80: 48 29 f2 sub %rsi,%rdx + 413e83: 48 89 df mov %rbx,%rdi + 413e86: e8 45 f3 ff ff callq 4131d0 <_IO_new_do_write> + 413e8b: 83 f8 ff cmp $0xffffffff,%eax + 413e8e: 0f 94 c0 sete %al + 413e91: e9 74 ff ff ff jmpq 413e0a <_IO_new_file_overflow+0x16a> + 413e96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 413e9d: 00 00 00 + +0000000000413ea0 <_IO_new_file_sync>: + 413ea0: 53 push %rbx + 413ea1: 48 8b 57 28 mov 0x28(%rdi),%rdx + 413ea5: 48 89 fb mov %rdi,%rbx + 413ea8: 48 8b 77 20 mov 0x20(%rdi),%rsi + 413eac: 48 39 f2 cmp %rsi,%rdx + 413eaf: 76 2e jbe 413edf <_IO_new_file_sync+0x3f> + 413eb1: 8b 87 c0 00 00 00 mov 0xc0(%rdi),%eax + 413eb7: 85 c0 test %eax,%eax + 413eb9: 7e 6d jle 413f28 <_IO_new_file_sync+0x88> + 413ebb: 48 8b 87 a0 00 00 00 mov 0xa0(%rdi),%rax + 413ec2: 48 8b 70 18 mov 0x18(%rax),%rsi + 413ec6: 48 8b 50 20 mov 0x20(%rax),%rdx + 413eca: 48 29 f2 sub %rsi,%rdx + 413ecd: 48 c1 fa 02 sar $0x2,%rdx + 413ed1: e8 5a cb ff ff callq 410a30 <_IO_wdo_write> + 413ed6: 85 c0 test %eax,%eax + 413ed8: 0f 95 c0 setne %al + 413edb: 84 c0 test %al,%al + 413edd: 75 6e jne 413f4d <_IO_new_file_sync+0xad> + 413edf: 48 8b 73 08 mov 0x8(%rbx),%rsi + 413ee3: 48 2b 73 10 sub 0x10(%rbx),%rsi + 413ee7: 75 17 jne 413f00 <_IO_new_file_sync+0x60> + 413ee9: 48 c7 83 90 00 00 00 movq $0xffffffffffffffff,0x90(%rbx) + 413ef0: ff ff ff ff + 413ef4: 31 c0 xor %eax,%eax + 413ef6: 5b pop %rbx + 413ef7: c3 retq + 413ef8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 413eff: 00 + 413f00: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 413f07: ba 01 00 00 00 mov $0x1,%edx + 413f0c: 48 89 df mov %rbx,%rdi + 413f0f: ff 90 80 00 00 00 callq *0x80(%rax) + 413f15: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 413f19: 74 25 je 413f40 <_IO_new_file_sync+0xa0> + 413f1b: 48 8b 43 08 mov 0x8(%rbx),%rax + 413f1f: 48 89 43 10 mov %rax,0x10(%rbx) + 413f23: eb c4 jmp 413ee9 <_IO_new_file_sync+0x49> + 413f25: 0f 1f 00 nopl (%rax) + 413f28: 48 29 f2 sub %rsi,%rdx + 413f2b: e8 a0 f2 ff ff callq 4131d0 <_IO_new_do_write> + 413f30: 85 c0 test %eax,%eax + 413f32: 0f 95 c0 setne %al + 413f35: eb a4 jmp 413edb <_IO_new_file_sync+0x3b> + 413f37: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 413f3e: 00 00 + 413f40: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 413f47: 64 83 38 1d cmpl $0x1d,%fs:(%rax) + 413f4b: 74 9c je 413ee9 <_IO_new_file_sync+0x49> + 413f4d: b8 ff ff ff ff mov $0xffffffff,%eax + 413f52: 5b pop %rbx + 413f53: c3 retq + 413f54: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 413f5b: 00 00 00 + 413f5e: 66 90 xchg %ax,%ax + +0000000000413f60 : + 413f60: 41 57 push %r15 + 413f62: 41 56 push %r14 + 413f64: 41 55 push %r13 + 413f66: 41 54 push %r12 + 413f68: 49 89 f4 mov %rsi,%r12 + 413f6b: 55 push %rbp + 413f6c: 53 push %rbx + 413f6d: 49 89 fd mov %rdi,%r13 + 413f70: 48 89 f5 mov %rsi,%rbp + 413f73: 48 83 ec 28 sub $0x28,%rsp + 413f77: 4c 8b 47 18 mov 0x18(%rdi),%r8 + 413f7b: 48 8b 47 60 mov 0x60(%rdi),%rax + 413f7f: 4d 29 c4 sub %r8,%r12 + 413f82: 48 85 c0 test %rax,%rax + 413f85: 0f 84 36 01 00 00 je 4140c1 + 413f8b: 4c 89 e3 mov %r12,%rbx + 413f8e: 48 89 c1 mov %rax,%rcx + 413f91: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 413f98: 48 63 79 10 movslq 0x10(%rcx),%rdi + 413f9c: 48 8b 09 mov (%rcx),%rcx + 413f9f: 48 39 fb cmp %rdi,%rbx + 413fa2: 48 0f 4f df cmovg %rdi,%rbx + 413fa6: 48 85 c9 test %rcx,%rcx + 413fa9: 75 ed jne 413f98 + 413fab: 49 8b 75 58 mov 0x58(%r13),%rsi + 413faf: 4d 8b 7d 48 mov 0x48(%r13),%r15 + 413fb3: 4c 89 e2 mov %r12,%rdx + 413fb6: 48 29 da sub %rbx,%rdx + 413fb9: 49 89 f6 mov %rsi,%r14 + 413fbc: 4d 29 fe sub %r15,%r14 + 413fbf: 4c 39 f2 cmp %r14,%rdx + 413fc2: 77 4c ja 414010 + 413fc4: 49 29 d6 sub %rdx,%r14 + 413fc7: 48 85 db test %rbx,%rbx + 413fca: 0f 88 0b 01 00 00 js 4140db + 413fd0: 48 85 d2 test %rdx,%rdx + 413fd3: 0f 85 c7 00 00 00 jne 4140a0 + 413fd9: 4d 01 fe add %r15,%r14 + 413fdc: 4c 89 e6 mov %r12,%rsi + 413fdf: 48 85 c0 test %rax,%rax + 413fe2: 4d 89 75 50 mov %r14,0x50(%r13) + 413fe6: 74 13 je 413ffb + 413fe8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 413fef: 00 + 413ff0: 29 70 10 sub %esi,0x10(%rax) + 413ff3: 48 8b 00 mov (%rax),%rax + 413ff6: 48 85 c0 test %rax,%rax + 413ff9: 75 f5 jne 413ff0 + 413ffb: 31 c0 xor %eax,%eax + 413ffd: 48 83 c4 28 add $0x28,%rsp + 414001: 5b pop %rbx + 414002: 5d pop %rbp + 414003: 41 5c pop %r12 + 414005: 41 5d pop %r13 + 414007: 41 5e pop %r14 + 414009: 41 5f pop %r15 + 41400b: c3 retq + 41400c: 0f 1f 40 00 nopl 0x0(%rax) + 414010: 48 8d 42 64 lea 0x64(%rdx),%rax + 414014: 4c 89 44 24 18 mov %r8,0x18(%rsp) + 414019: 48 89 74 24 10 mov %rsi,0x10(%rsp) + 41401e: 48 89 54 24 08 mov %rdx,0x8(%rsp) + 414023: 48 89 c7 mov %rax,%rdi + 414026: 48 89 04 24 mov %rax,(%rsp) + 41402a: e8 e1 99 00 00 callq 41da10 <__libc_malloc> + 41402f: 48 85 c0 test %rax,%rax + 414032: 0f 84 0b 01 00 00 je 414143 + 414038: 48 85 db test %rbx,%rbx + 41403b: 48 8b 54 24 08 mov 0x8(%rsp),%rdx + 414040: 48 8b 74 24 10 mov 0x10(%rsp),%rsi + 414045: 4c 8b 44 24 18 mov 0x18(%rsp),%r8 + 41404a: 0f 88 b3 00 00 00 js 414103 + 414050: 4c 8d 70 64 lea 0x64(%rax),%r14 + 414054: 49 8d 34 18 lea (%r8,%rbx,1),%rsi + 414058: 48 89 44 24 08 mov %rax,0x8(%rsp) + 41405d: 4c 89 f7 mov %r14,%rdi + 414060: e8 bb 7f 01 00 callq 42c020 + 414065: 4c 8b 4c 24 08 mov 0x8(%rsp),%r9 + 41406a: 4c 89 ff mov %r15,%rdi + 41406d: 4c 89 4c 24 08 mov %r9,0x8(%rsp) + 414072: e8 39 9d 00 00 callq 41ddb0 <__cfree> + 414077: 4c 8b 4c 24 08 mov 0x8(%rsp),%r9 + 41407c: 4c 8b 3c 24 mov (%rsp),%r15 + 414080: 48 89 ee mov %rbp,%rsi + 414083: 49 8b 45 60 mov 0x60(%r13),%rax + 414087: 49 2b 75 18 sub 0x18(%r13),%rsi + 41408b: 4d 01 cf add %r9,%r15 + 41408e: 4d 89 4d 48 mov %r9,0x48(%r13) + 414092: 4d 89 7d 58 mov %r15,0x58(%r13) + 414096: e9 44 ff ff ff jmpq 413fdf + 41409b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4140a0: 4b 8d 3c 37 lea (%r15,%r14,1),%rdi + 4140a4: 49 8d 34 18 lea (%r8,%rbx,1),%rsi + 4140a8: e8 73 7f 01 00 callq 42c020 + 4140ad: 48 89 ee mov %rbp,%rsi + 4140b0: 4d 03 75 48 add 0x48(%r13),%r14 + 4140b4: 49 2b 75 18 sub 0x18(%r13),%rsi + 4140b8: 49 8b 45 60 mov 0x60(%r13),%rax + 4140bc: e9 1e ff ff ff jmpq 413fdf + 4140c1: 48 8b 77 58 mov 0x58(%rdi),%rsi + 4140c5: 4c 8b 7f 48 mov 0x48(%rdi),%r15 + 4140c9: 49 89 f6 mov %rsi,%r14 + 4140cc: 4d 29 fe sub %r15,%r14 + 4140cf: 4d 85 e4 test %r12,%r12 + 4140d2: 0f 89 01 ff ff ff jns 413fd9 + 4140d8: 4c 89 e3 mov %r12,%rbx + 4140db: 4b 8d 3c 37 lea (%r15,%r14,1),%rdi + 4140df: 48 89 da mov %rbx,%rdx + 4140e2: 48 01 de add %rbx,%rsi + 4140e5: 48 f7 da neg %rdx + 4140e8: e8 13 c2 fe ff callq 400300 <__rela_iplt_end+0x38> + 4140ed: 49 8b 75 18 mov 0x18(%r13),%rsi + 4140f1: 4c 89 f7 mov %r14,%rdi + 4140f4: 48 89 ea mov %rbp,%rdx + 4140f7: 48 29 df sub %rbx,%rdi + 4140fa: 49 03 7d 48 add 0x48(%r13),%rdi + 4140fe: 48 29 f2 sub %rsi,%rdx + 414101: eb a5 jmp 4140a8 + 414103: 4c 8d 70 64 lea 0x64(%rax),%r14 + 414107: 48 89 da mov %rbx,%rdx + 41410a: 48 01 de add %rbx,%rsi + 41410d: 48 f7 da neg %rdx + 414110: 4c 89 44 24 10 mov %r8,0x10(%rsp) + 414115: 48 89 44 24 08 mov %rax,0x8(%rsp) + 41411a: 4c 89 f7 mov %r14,%rdi + 41411d: e8 9e 24 01 00 callq 4265c0 <__mempcpy> + 414122: 4c 8b 44 24 10 mov 0x10(%rsp),%r8 + 414127: 4c 89 e2 mov %r12,%rdx + 41412a: 48 89 c7 mov %rax,%rdi + 41412d: 4c 89 c6 mov %r8,%rsi + 414130: e8 8b 24 01 00 callq 4265c0 <__mempcpy> + 414135: 4d 8b 7d 48 mov 0x48(%r13),%r15 + 414139: 4c 8b 4c 24 08 mov 0x8(%rsp),%r9 + 41413e: e9 27 ff ff ff jmpq 41406a + 414143: b8 ff ff ff ff mov $0xffffffff,%eax + 414148: e9 b0 fe ff ff jmpq 413ffd + 41414d: 0f 1f 00 nopl (%rax) + +0000000000414150 : + 414150: 48 8b 05 39 84 2b 00 mov 0x2b8439(%rip),%rax # 6cc590 + 414157: 48 85 c0 test %rax,%rax + 41415a: 74 47 je 4141a3 + 41415c: f7 00 00 80 00 00 testl $0x8000,(%rax) + 414162: 75 3f jne 4141a3 + 414164: 48 8b 90 88 00 00 00 mov 0x88(%rax),%rdx + 41416b: 83 6a 04 01 subl $0x1,0x4(%rdx) + 41416f: 75 32 jne 4141a3 + 414171: 48 c7 42 08 00 00 00 movq $0x0,0x8(%rdx) + 414178: 00 + 414179: 83 3d 3c 90 2b 00 00 cmpl $0x0,0x2b903c(%rip) # 6cd1bc <__libc_multiple_threads> + 414180: 74 07 je 414189 + 414182: f0 ff 0a lock decl (%rdx) + 414185: 75 06 jne 41418d + 414187: eb 1a jmp 4141a3 + 414189: ff 0a decl (%rdx) + 41418b: 74 16 je 4141a3 + 41418d: 48 8d 3a lea (%rdx),%rdi + 414190: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 414197: e8 64 e4 02 00 callq 442600 <__lll_unlock_wake_private> + 41419c: 48 81 c4 80 00 00 00 add $0x80,%rsp + 4141a3: 83 2d fa 83 2b 00 01 subl $0x1,0x2b83fa(%rip) # 6cc5a4 + 4141aa: 75 41 jne 4141ed + 4141ac: 48 c7 05 f1 83 2b 00 movq $0x0,0x2b83f1(%rip) # 6cc5a8 + 4141b3: 00 00 00 00 + 4141b7: 83 3d fe 8f 2b 00 00 cmpl $0x0,0x2b8ffe(%rip) # 6cd1bc <__libc_multiple_threads> + 4141be: 74 0b je 4141cb + 4141c0: f0 ff 0d d9 83 2b 00 lock decl 0x2b83d9(%rip) # 6cc5a0 + 4141c7: 75 0a jne 4141d3 + 4141c9: eb 22 jmp 4141ed + 4141cb: ff 0d cf 83 2b 00 decl 0x2b83cf(%rip) # 6cc5a0 + 4141d1: 74 1a je 4141ed + 4141d3: 48 8d 3d c6 83 2b 00 lea 0x2b83c6(%rip),%rdi # 6cc5a0 + 4141da: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 4141e1: e8 1a e4 02 00 callq 442600 <__lll_unlock_wake_private> + 4141e6: 48 81 c4 80 00 00 00 add $0x80,%rsp + 4141ed: f3 c3 repz retq + 4141ef: 90 nop + +00000000004141f0 <_IO_cleanup>: + 4141f0: 41 55 push %r13 + 4141f2: 41 54 push %r12 + 4141f4: 45 31 e4 xor %r12d,%r12d + 4141f7: 55 push %rbp + 4141f8: 53 push %rbx + 4141f9: 48 83 ec 08 sub $0x8,%rsp + 4141fd: 48 8b 1d bc 5e 2b 00 mov 0x2b5ebc(%rip),%rbx # 6ca0c0 <_IO_list_all> + 414204: 8b 2d 8e 83 2b 00 mov 0x2b838e(%rip),%ebp # 6cc598 <_IO_list_all_stamp> + 41420a: 48 85 db test %rbx,%rbx + 41420d: 75 47 jne 414256 <_IO_cleanup+0x66> + 41420f: e9 bc 01 00 00 jmpq 4143d0 <_IO_cleanup+0x1e0> + 414214: 0f 1f 40 00 nopl 0x0(%rax) + 414218: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 41421f: be ff ff ff ff mov $0xffffffff,%esi + 414224: 48 89 df mov %rbx,%rdi + 414227: ff 50 18 callq *0x18(%rax) + 41422a: 83 f8 ff cmp $0xffffffff,%eax + 41422d: 8b 15 65 83 2b 00 mov 0x2b8365(%rip),%edx # 6cc598 <_IO_list_all_stamp> + 414233: 0f 84 8f 01 00 00 je 4143c8 <_IO_cleanup+0x1d8> + 414239: 39 d5 cmp %edx,%ebp + 41423b: 48 c7 05 4a 83 2b 00 movq $0x0,0x2b834a(%rip) # 6cc590 + 414242: 00 00 00 00 + 414246: 74 41 je 414289 <_IO_cleanup+0x99> + 414248: 48 8b 1d 71 5e 2b 00 mov 0x2b5e71(%rip),%rbx # 6ca0c0 <_IO_list_all> + 41424f: 89 d5 mov %edx,%ebp + 414251: 48 85 db test %rbx,%rbx + 414254: 74 3e je 414294 <_IO_cleanup+0xa4> + 414256: 8b 8b c0 00 00 00 mov 0xc0(%rbx),%ecx + 41425c: 48 89 1d 2d 83 2b 00 mov %rbx,0x2b832d(%rip) # 6cc590 + 414263: 85 c9 test %ecx,%ecx + 414265: 0f 8e 45 01 00 00 jle 4143b0 <_IO_cleanup+0x1c0> + 41426b: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 414272: 48 8b 70 18 mov 0x18(%rax),%rsi + 414276: 48 39 70 20 cmp %rsi,0x20(%rax) + 41427a: 77 9c ja 414218 <_IO_cleanup+0x28> + 41427c: 48 c7 05 09 83 2b 00 movq $0x0,0x2b8309(%rip) # 6cc590 + 414283: 00 00 00 00 + 414287: 89 ea mov %ebp,%edx + 414289: 48 8b 5b 68 mov 0x68(%rbx),%rbx + 41428d: 89 d5 mov %edx,%ebp + 41428f: 48 85 db test %rbx,%rbx + 414292: 75 c2 jne 414256 <_IO_cleanup+0x66> + 414294: 48 8b 1d 25 5e 2b 00 mov 0x2b5e25(%rip),%rbx # 6ca0c0 <_IO_list_all> + 41429b: 48 85 db test %rbx,%rbx + 41429e: 0f 84 2c 01 00 00 je 4143d0 <_IO_cleanup+0x1e0> + 4142a4: 64 4c 8b 2c 25 10 00 mov %fs:0x10,%r13 + 4142ab: 00 00 + 4142ad: e9 95 00 00 00 jmpq 414347 <_IO_cleanup+0x157> + 4142b2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4142b8: 48 8b 83 88 00 00 00 mov 0x88(%rbx),%rax + 4142bf: 4c 89 68 08 mov %r13,0x8(%rax) + 4142c3: c7 40 04 01 00 00 00 movl $0x1,0x4(%rax) + 4142ca: 80 3d b7 82 2b 00 00 cmpb $0x0,0x2b82b7(%rip) # 6cc588 + 4142d1: 75 2b jne 4142fe <_IO_cleanup+0x10e> + 4142d3: 8b 03 mov (%rbx),%eax + 4142d5: a8 01 test $0x1,%al + 4142d7: 75 25 jne 4142fe <_IO_cleanup+0x10e> + 4142d9: 83 c8 01 or $0x1,%eax + 4142dc: 89 03 mov %eax,(%rbx) + 4142de: 48 8b 05 9b 82 2b 00 mov 0x2b829b(%rip),%rax # 6cc580 + 4142e5: 48 89 1d 94 82 2b 00 mov %rbx,0x2b8294(%rip) # 6cc580 + 4142ec: 48 89 83 a8 00 00 00 mov %rax,0xa8(%rbx) + 4142f3: 48 8b 43 38 mov 0x38(%rbx),%rax + 4142f7: 48 89 83 b0 00 00 00 mov %rax,0xb0(%rbx) + 4142fe: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 414305: 31 d2 xor %edx,%edx + 414307: 31 f6 xor %esi,%esi + 414309: 48 89 df mov %rbx,%rdi + 41430c: ff 50 58 callq *0x58(%rax) + 41430f: 8b 83 c0 00 00 00 mov 0xc0(%rbx),%eax + 414315: 85 c0 test %eax,%eax + 414317: 7e 0e jle 414327 <_IO_cleanup+0x137> + 414319: 31 c9 xor %ecx,%ecx + 41431b: 31 d2 xor %edx,%edx + 41431d: 31 f6 xor %esi,%esi + 41431f: 48 89 df mov %rbx,%rdi + 414322: e8 69 f5 04 00 callq 463890 <_IO_wsetb> + 414327: 83 fd 02 cmp $0x2,%ebp + 41432a: 0f 85 b0 00 00 00 jne 4143e0 <_IO_cleanup+0x1f0> + 414330: c7 83 c0 00 00 00 ff movl $0xffffffff,0xc0(%rbx) + 414337: ff ff ff + 41433a: 48 8b 5b 68 mov 0x68(%rbx),%rbx + 41433e: 48 85 db test %rbx,%rbx + 414341: 0f 84 89 00 00 00 je 4143d0 <_IO_cleanup+0x1e0> + 414347: f6 03 02 testb $0x2,(%rbx) + 41434a: 75 e4 jne 414330 <_IO_cleanup+0x140> + 41434c: 8b 93 c0 00 00 00 mov 0xc0(%rbx),%edx + 414352: 85 d2 test %edx,%edx + 414354: 74 da je 414330 <_IO_cleanup+0x140> + 414356: 31 ed xor %ebp,%ebp + 414358: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx + 41435f: 48 85 d2 test %rdx,%rdx + 414362: 0f 84 62 ff ff ff je 4142ca <_IO_cleanup+0xda> + 414368: 4c 3b 6a 08 cmp 0x8(%rdx),%r13 + 41436c: 0f 84 c6 00 00 00 je 414438 <_IO_cleanup+0x248> + 414372: 31 c0 xor %eax,%eax + 414374: b9 01 00 00 00 mov $0x1,%ecx + 414379: 83 3d 3c 8e 2b 00 00 cmpl $0x0,0x2b8e3c(%rip) # 6cd1bc <__libc_multiple_threads> + 414380: 74 06 je 414388 <_IO_cleanup+0x198> + 414382: f0 0f b1 0a lock cmpxchg %ecx,(%rdx) + 414386: eb 03 jmp 41438b <_IO_cleanup+0x19b> + 414388: 0f b1 0a cmpxchg %ecx,(%rdx) + 41438b: 85 c0 test %eax,%eax + 41438d: 0f 84 25 ff ff ff je 4142b8 <_IO_cleanup+0xc8> + 414393: 83 c5 01 add $0x1,%ebp + 414396: e8 95 ac 02 00 callq 43f030 <__sched_yield> + 41439b: 83 fd 02 cmp $0x2,%ebp + 41439e: 0f 84 26 ff ff ff je 4142ca <_IO_cleanup+0xda> + 4143a4: eb b2 jmp 414358 <_IO_cleanup+0x168> + 4143a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4143ad: 00 00 00 + 4143b0: 48 8b 43 20 mov 0x20(%rbx),%rax + 4143b4: 48 39 43 28 cmp %rax,0x28(%rbx) + 4143b8: 0f 87 5a fe ff ff ja 414218 <_IO_cleanup+0x28> + 4143be: e9 b9 fe ff ff jmpq 41427c <_IO_cleanup+0x8c> + 4143c3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4143c8: 41 89 c4 mov %eax,%r12d + 4143cb: e9 69 fe ff ff jmpq 414239 <_IO_cleanup+0x49> + 4143d0: 48 83 c4 08 add $0x8,%rsp + 4143d4: 44 89 e0 mov %r12d,%eax + 4143d7: 5b pop %rbx + 4143d8: 5d pop %rbp + 4143d9: 41 5c pop %r12 + 4143db: 41 5d pop %r13 + 4143dd: c3 retq + 4143de: 66 90 xchg %ax,%ax + 4143e0: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx + 4143e7: 48 85 d2 test %rdx,%rdx + 4143ea: 0f 84 40 ff ff ff je 414330 <_IO_cleanup+0x140> + 4143f0: 83 6a 04 01 subl $0x1,0x4(%rdx) + 4143f4: 0f 85 36 ff ff ff jne 414330 <_IO_cleanup+0x140> + 4143fa: 48 c7 42 08 00 00 00 movq $0x0,0x8(%rdx) + 414401: 00 + 414402: 83 3d b3 8d 2b 00 00 cmpl $0x0,0x2b8db3(%rip) # 6cd1bc <__libc_multiple_threads> + 414409: 74 07 je 414412 <_IO_cleanup+0x222> + 41440b: f0 ff 0a lock decl (%rdx) + 41440e: 75 06 jne 414416 <_IO_cleanup+0x226> + 414410: eb 1a jmp 41442c <_IO_cleanup+0x23c> + 414412: ff 0a decl (%rdx) + 414414: 74 16 je 41442c <_IO_cleanup+0x23c> + 414416: 48 8d 3a lea (%rdx),%rdi + 414419: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 414420: e8 db e1 02 00 callq 442600 <__lll_unlock_wake_private> + 414425: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41442c: e9 ff fe ff ff jmpq 414330 <_IO_cleanup+0x140> + 414431: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 414438: 83 42 04 01 addl $0x1,0x4(%rdx) + 41443c: e9 89 fe ff ff jmpq 4142ca <_IO_cleanup+0xda> + 414441: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 414446: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41444d: 00 00 00 + +0000000000414450 <_IO_un_link>: + 414450: f6 07 80 testb $0x80,(%rdi) + 414453: 0f 84 da 01 00 00 je 414633 <_IO_un_link+0x1e3> + 414459: 55 push %rbp + 41445a: 53 push %rbx + 41445b: bd 00 00 00 00 mov $0x0,%ebp + 414460: 48 89 fb mov %rdi,%rbx + 414463: 48 83 ec 28 sub $0x28,%rsp + 414467: 48 85 ed test %rbp,%rbp + 41446a: 0f 84 28 02 00 00 je 414698 <_IO_un_link+0x248> + 414470: 31 d2 xor %edx,%edx + 414472: be 50 41 41 00 mov $0x414150,%esi + 414477: 48 89 e7 mov %rsp,%rdi + 41447a: e8 81 bb be ff callq 0 <_nl_current_LC_CTYPE> + 41447f: 64 48 8b 14 25 10 00 mov %fs:0x10,%rdx + 414486: 00 00 + 414488: 48 3b 15 19 81 2b 00 cmp 0x2b8119(%rip),%rdx # 6cc5a8 + 41448f: 74 46 je 4144d7 <_IO_un_link+0x87> + 414491: be 01 00 00 00 mov $0x1,%esi + 414496: 31 c0 xor %eax,%eax + 414498: 83 3d 1d 8d 2b 00 00 cmpl $0x0,0x2b8d1d(%rip) # 6cd1bc <__libc_multiple_threads> + 41449f: 74 0c je 4144ad <_IO_un_link+0x5d> + 4144a1: f0 0f b1 35 f7 80 2b lock cmpxchg %esi,0x2b80f7(%rip) # 6cc5a0 + 4144a8: 00 + 4144a9: 75 0b jne 4144b6 <_IO_un_link+0x66> + 4144ab: eb 23 jmp 4144d0 <_IO_un_link+0x80> + 4144ad: 0f b1 35 ec 80 2b 00 cmpxchg %esi,0x2b80ec(%rip) # 6cc5a0 + 4144b4: 74 1a je 4144d0 <_IO_un_link+0x80> + 4144b6: 48 8d 3d e3 80 2b 00 lea 0x2b80e3(%rip),%rdi # 6cc5a0 + 4144bd: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 4144c4: e8 07 e1 02 00 callq 4425d0 <__lll_lock_wait_private> + 4144c9: 48 81 c4 80 00 00 00 add $0x80,%rsp + 4144d0: 48 89 15 d1 80 2b 00 mov %rdx,0x2b80d1(%rip) # 6cc5a8 + 4144d7: 8b 33 mov (%rbx),%esi + 4144d9: 8b 15 c5 80 2b 00 mov 0x2b80c5(%rip),%edx # 6cc5a4 + 4144df: 48 89 1d aa 80 2b 00 mov %rbx,0x2b80aa(%rip) # 6cc590 + 4144e6: 89 f0 mov %esi,%eax + 4144e8: 83 c2 01 add $0x1,%edx + 4144eb: 25 00 80 00 00 and $0x8000,%eax + 4144f0: 89 15 ae 80 2b 00 mov %edx,0x2b80ae(%rip) # 6cc5a4 + 4144f6: 0f 85 7c 01 00 00 jne 414678 <_IO_un_link+0x228> + 4144fc: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx + 414503: 64 4c 8b 04 25 10 00 mov %fs:0x10,%r8 + 41450a: 00 00 + 41450c: 4c 3b 42 08 cmp 0x8(%rdx),%r8 + 414510: 74 3c je 41454e <_IO_un_link+0xfe> + 414512: be 01 00 00 00 mov $0x1,%esi + 414517: 83 3d 9e 8c 2b 00 00 cmpl $0x0,0x2b8c9e(%rip) # 6cd1bc <__libc_multiple_threads> + 41451e: 74 08 je 414528 <_IO_un_link+0xd8> + 414520: f0 0f b1 32 lock cmpxchg %esi,(%rdx) + 414524: 75 07 jne 41452d <_IO_un_link+0xdd> + 414526: eb 1b jmp 414543 <_IO_un_link+0xf3> + 414528: 0f b1 32 cmpxchg %esi,(%rdx) + 41452b: 74 16 je 414543 <_IO_un_link+0xf3> + 41452d: 48 8d 3a lea (%rdx),%rdi + 414530: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 414537: e8 94 e0 02 00 callq 4425d0 <__lll_lock_wait_private> + 41453c: 48 81 c4 80 00 00 00 add $0x80,%rsp + 414543: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx + 41454a: 4c 89 42 08 mov %r8,0x8(%rdx) + 41454e: 8b 33 mov (%rbx),%esi + 414550: 48 8b 3d 69 5b 2b 00 mov 0x2b5b69(%rip),%rdi # 6ca0c0 <_IO_list_all> + 414557: 83 42 04 01 addl $0x1,0x4(%rdx) + 41455b: 89 f0 mov %esi,%eax + 41455d: 25 00 80 00 00 and $0x8000,%eax + 414562: 48 85 ff test %rdi,%rdi + 414565: 74 36 je 41459d <_IO_un_link+0x14d> + 414567: 48 39 fb cmp %rdi,%rbx + 41456a: 0f 84 60 01 00 00 je 4146d0 <_IO_un_link+0x280> + 414570: 48 8b 4f 68 mov 0x68(%rdi),%rcx + 414574: 48 85 c9 test %rcx,%rcx + 414577: 74 24 je 41459d <_IO_un_link+0x14d> + 414579: 48 39 cb cmp %rcx,%rbx + 41457c: 75 16 jne 414594 <_IO_un_link+0x144> + 41457e: e9 64 01 00 00 jmpq 4146e7 <_IO_un_link+0x297> + 414583: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 414588: 48 39 d3 cmp %rdx,%rbx + 41458b: 0f 84 1f 01 00 00 je 4146b0 <_IO_un_link+0x260> + 414591: 48 89 d1 mov %rdx,%rcx + 414594: 48 8b 51 68 mov 0x68(%rcx),%rdx + 414598: 48 85 d2 test %rdx,%rdx + 41459b: 75 eb jne 414588 <_IO_un_link+0x138> + 41459d: 40 80 e6 7f and $0x7f,%sil + 4145a1: 85 c0 test %eax,%eax + 4145a3: 89 33 mov %esi,(%rbx) + 4145a5: 0f 85 bf 00 00 00 jne 41466a <_IO_un_link+0x21a> + 4145ab: 48 8b b3 88 00 00 00 mov 0x88(%rbx),%rsi + 4145b2: 8b 46 04 mov 0x4(%rsi),%eax + 4145b5: 83 e8 01 sub $0x1,%eax + 4145b8: 85 c0 test %eax,%eax + 4145ba: 89 46 04 mov %eax,0x4(%rsi) + 4145bd: 8b 15 e1 7f 2b 00 mov 0x2b7fe1(%rip),%edx # 6cc5a4 + 4145c3: 74 73 je 414638 <_IO_un_link+0x1e8> + 4145c5: 83 ea 01 sub $0x1,%edx + 4145c8: 48 c7 05 bd 7f 2b 00 movq $0x0,0x2b7fbd(%rip) # 6cc590 + 4145cf: 00 00 00 00 + 4145d3: 85 d2 test %edx,%edx + 4145d5: 89 15 c9 7f 2b 00 mov %edx,0x2b7fc9(%rip) # 6cc5a4 + 4145db: 75 41 jne 41461e <_IO_un_link+0x1ce> + 4145dd: 48 c7 05 c0 7f 2b 00 movq $0x0,0x2b7fc0(%rip) # 6cc5a8 + 4145e4: 00 00 00 00 + 4145e8: 83 3d cd 8b 2b 00 00 cmpl $0x0,0x2b8bcd(%rip) # 6cd1bc <__libc_multiple_threads> + 4145ef: 74 0b je 4145fc <_IO_un_link+0x1ac> + 4145f1: f0 ff 0d a8 7f 2b 00 lock decl 0x2b7fa8(%rip) # 6cc5a0 + 4145f8: 75 0a jne 414604 <_IO_un_link+0x1b4> + 4145fa: eb 22 jmp 41461e <_IO_un_link+0x1ce> + 4145fc: ff 0d 9e 7f 2b 00 decl 0x2b7f9e(%rip) # 6cc5a0 + 414602: 74 1a je 41461e <_IO_un_link+0x1ce> + 414604: 48 8d 3d 95 7f 2b 00 lea 0x2b7f95(%rip),%rdi # 6cc5a0 + 41460b: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 414612: e8 e9 df 02 00 callq 442600 <__lll_unlock_wake_private> + 414617: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41461e: 48 85 ed test %rbp,%rbp + 414621: 74 0a je 41462d <_IO_un_link+0x1dd> + 414623: 31 f6 xor %esi,%esi + 414625: 48 89 e7 mov %rsp,%rdi + 414628: e8 d3 b9 be ff callq 0 <_nl_current_LC_CTYPE> + 41462d: 48 83 c4 28 add $0x28,%rsp + 414631: 5b pop %rbx + 414632: 5d pop %rbp + 414633: f3 c3 repz retq + 414635: 0f 1f 00 nopl (%rax) + 414638: 48 c7 46 08 00 00 00 movq $0x0,0x8(%rsi) + 41463f: 00 + 414640: 83 3d 75 8b 2b 00 00 cmpl $0x0,0x2b8b75(%rip) # 6cd1bc <__libc_multiple_threads> + 414647: 74 07 je 414650 <_IO_un_link+0x200> + 414649: f0 ff 0e lock decl (%rsi) + 41464c: 75 06 jne 414654 <_IO_un_link+0x204> + 41464e: eb 1a jmp 41466a <_IO_un_link+0x21a> + 414650: ff 0e decl (%rsi) + 414652: 74 16 je 41466a <_IO_un_link+0x21a> + 414654: 48 8d 3e lea (%rsi),%rdi + 414657: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41465e: e8 9d df 02 00 callq 442600 <__lll_unlock_wake_private> + 414663: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41466a: 8b 15 34 7f 2b 00 mov 0x2b7f34(%rip),%edx # 6cc5a4 + 414670: e9 50 ff ff ff jmpq 4145c5 <_IO_un_link+0x175> + 414675: 0f 1f 00 nopl (%rax) + 414678: 48 8b 3d 41 5a 2b 00 mov 0x2b5a41(%rip),%rdi # 6ca0c0 <_IO_list_all> + 41467f: 48 85 ff test %rdi,%rdi + 414682: 0f 85 df fe ff ff jne 414567 <_IO_un_link+0x117> + 414688: 40 80 e6 7f and $0x7f,%sil + 41468c: 89 33 mov %esi,(%rbx) + 41468e: e9 32 ff ff ff jmpq 4145c5 <_IO_un_link+0x175> + 414693: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 414698: 48 c7 04 24 50 41 41 movq $0x414150,(%rsp) + 41469f: 00 + 4146a0: 48 c7 44 24 08 00 00 movq $0x0,0x8(%rsp) + 4146a7: 00 00 + 4146a9: e9 d1 fd ff ff jmpq 41447f <_IO_un_link+0x2f> + 4146ae: 66 90 xchg %ax,%ax + 4146b0: 48 83 c1 68 add $0x68,%rcx + 4146b4: 48 8b 53 68 mov 0x68(%rbx),%rdx + 4146b8: 83 05 d9 7e 2b 00 01 addl $0x1,0x2b7ed9(%rip) # 6cc598 <_IO_list_all_stamp> + 4146bf: 48 89 11 mov %rdx,(%rcx) + 4146c2: e9 d6 fe ff ff jmpq 41459d <_IO_un_link+0x14d> + 4146c7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 4146ce: 00 00 + 4146d0: 48 8b 53 68 mov 0x68(%rbx),%rdx + 4146d4: 83 05 bd 7e 2b 00 01 addl $0x1,0x2b7ebd(%rip) # 6cc598 <_IO_list_all_stamp> + 4146db: 48 89 15 de 59 2b 00 mov %rdx,0x2b59de(%rip) # 6ca0c0 <_IO_list_all> + 4146e2: e9 b6 fe ff ff jmpq 41459d <_IO_un_link+0x14d> + 4146e7: 48 8d 4f 68 lea 0x68(%rdi),%rcx + 4146eb: eb c7 jmp 4146b4 <_IO_un_link+0x264> + 4146ed: 0f 1f 00 nopl (%rax) + +00000000004146f0 <_IO_link_in>: + 4146f0: 8b 07 mov (%rdi),%eax + 4146f2: a8 80 test $0x80,%al + 4146f4: 0f 85 ab 01 00 00 jne 4148a5 <_IO_link_in+0x1b5> + 4146fa: 55 push %rbp + 4146fb: 53 push %rbx + 4146fc: bd 00 00 00 00 mov $0x0,%ebp + 414701: 0c 80 or $0x80,%al + 414703: 48 89 fb mov %rdi,%rbx + 414706: 48 83 ec 28 sub $0x28,%rsp + 41470a: 48 85 ed test %rbp,%rbp + 41470d: 89 07 mov %eax,(%rdi) + 41470f: 0f 84 bb 01 00 00 je 4148d0 <_IO_link_in+0x1e0> + 414715: 31 d2 xor %edx,%edx + 414717: be 50 41 41 00 mov $0x414150,%esi + 41471c: 48 89 e7 mov %rsp,%rdi + 41471f: e8 dc b8 be ff callq 0 <_nl_current_LC_CTYPE> + 414724: 64 48 8b 14 25 10 00 mov %fs:0x10,%rdx + 41472b: 00 00 + 41472d: 48 3b 15 74 7e 2b 00 cmp 0x2b7e74(%rip),%rdx # 6cc5a8 + 414734: 74 46 je 41477c <_IO_link_in+0x8c> + 414736: be 01 00 00 00 mov $0x1,%esi + 41473b: 31 c0 xor %eax,%eax + 41473d: 83 3d 78 8a 2b 00 00 cmpl $0x0,0x2b8a78(%rip) # 6cd1bc <__libc_multiple_threads> + 414744: 74 0c je 414752 <_IO_link_in+0x62> + 414746: f0 0f b1 35 52 7e 2b lock cmpxchg %esi,0x2b7e52(%rip) # 6cc5a0 + 41474d: 00 + 41474e: 75 0b jne 41475b <_IO_link_in+0x6b> + 414750: eb 23 jmp 414775 <_IO_link_in+0x85> + 414752: 0f b1 35 47 7e 2b 00 cmpxchg %esi,0x2b7e47(%rip) # 6cc5a0 + 414759: 74 1a je 414775 <_IO_link_in+0x85> + 41475b: 48 8d 3d 3e 7e 2b 00 lea 0x2b7e3e(%rip),%rdi # 6cc5a0 + 414762: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 414769: e8 62 de 02 00 callq 4425d0 <__lll_lock_wait_private> + 41476e: 48 81 c4 80 00 00 00 add $0x80,%rsp + 414775: 48 89 15 2c 7e 2b 00 mov %rdx,0x2b7e2c(%rip) # 6cc5a8 + 41477c: 8b 0b mov (%rbx),%ecx + 41477e: 8b 15 20 7e 2b 00 mov 0x2b7e20(%rip),%edx # 6cc5a4 + 414784: 48 89 1d 05 7e 2b 00 mov %rbx,0x2b7e05(%rip) # 6cc590 + 41478b: 89 c8 mov %ecx,%eax + 41478d: 83 c2 01 add $0x1,%edx + 414790: 25 00 80 00 00 and $0x8000,%eax + 414795: 89 15 09 7e 2b 00 mov %edx,0x2b7e09(%rip) # 6cc5a4 + 41479b: 0f 85 0f 01 00 00 jne 4148b0 <_IO_link_in+0x1c0> + 4147a1: 4c 8b 83 88 00 00 00 mov 0x88(%rbx),%r8 + 4147a8: 64 48 8b 14 25 10 00 mov %fs:0x10,%rdx + 4147af: 00 00 + 4147b1: 49 3b 50 08 cmp 0x8(%r8),%rdx + 4147b5: 74 40 je 4147f7 <_IO_link_in+0x107> + 4147b7: be 01 00 00 00 mov $0x1,%esi + 4147bc: 83 3d f9 89 2b 00 00 cmpl $0x0,0x2b89f9(%rip) # 6cd1bc <__libc_multiple_threads> + 4147c3: 74 09 je 4147ce <_IO_link_in+0xde> + 4147c5: f0 41 0f b1 30 lock cmpxchg %esi,(%r8) + 4147ca: 75 08 jne 4147d4 <_IO_link_in+0xe4> + 4147cc: eb 1c jmp 4147ea <_IO_link_in+0xfa> + 4147ce: 41 0f b1 30 cmpxchg %esi,(%r8) + 4147d2: 74 16 je 4147ea <_IO_link_in+0xfa> + 4147d4: 49 8d 38 lea (%r8),%rdi + 4147d7: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 4147de: e8 ed dd 02 00 callq 4425d0 <__lll_lock_wait_private> + 4147e3: 48 81 c4 80 00 00 00 add $0x80,%rsp + 4147ea: 4c 8b 83 88 00 00 00 mov 0x88(%rbx),%r8 + 4147f1: 8b 0b mov (%rbx),%ecx + 4147f3: 49 89 50 08 mov %rdx,0x8(%r8) + 4147f7: 48 8b 05 c2 58 2b 00 mov 0x2b58c2(%rip),%rax # 6ca0c0 <_IO_list_all> + 4147fe: 41 83 40 04 01 addl $0x1,0x4(%r8) + 414803: 83 05 8e 7d 2b 00 01 addl $0x1,0x2b7d8e(%rip) # 6cc598 <_IO_list_all_stamp> + 41480a: 80 e5 80 and $0x80,%ch + 41480d: 48 89 1d ac 58 2b 00 mov %rbx,0x2b58ac(%rip) # 6ca0c0 <_IO_list_all> + 414814: 48 89 43 68 mov %rax,0x68(%rbx) + 414818: 0f 85 06 01 00 00 jne 414924 <_IO_link_in+0x234> + 41481e: 41 8b 40 04 mov 0x4(%r8),%eax + 414822: 83 e8 01 sub $0x1,%eax + 414825: 85 c0 test %eax,%eax + 414827: 41 89 40 04 mov %eax,0x4(%r8) + 41482b: 8b 15 73 7d 2b 00 mov 0x2b7d73(%rip),%edx # 6cc5a4 + 414831: 0f 84 b9 00 00 00 je 4148f0 <_IO_link_in+0x200> + 414837: 83 ea 01 sub $0x1,%edx + 41483a: 48 c7 05 4b 7d 2b 00 movq $0x0,0x2b7d4b(%rip) # 6cc590 + 414841: 00 00 00 00 + 414845: 85 d2 test %edx,%edx + 414847: 89 15 57 7d 2b 00 mov %edx,0x2b7d57(%rip) # 6cc5a4 + 41484d: 75 41 jne 414890 <_IO_link_in+0x1a0> + 41484f: 48 c7 05 4e 7d 2b 00 movq $0x0,0x2b7d4e(%rip) # 6cc5a8 + 414856: 00 00 00 00 + 41485a: 83 3d 5b 89 2b 00 00 cmpl $0x0,0x2b895b(%rip) # 6cd1bc <__libc_multiple_threads> + 414861: 74 0b je 41486e <_IO_link_in+0x17e> + 414863: f0 ff 0d 36 7d 2b 00 lock decl 0x2b7d36(%rip) # 6cc5a0 + 41486a: 75 0a jne 414876 <_IO_link_in+0x186> + 41486c: eb 22 jmp 414890 <_IO_link_in+0x1a0> + 41486e: ff 0d 2c 7d 2b 00 decl 0x2b7d2c(%rip) # 6cc5a0 + 414874: 74 1a je 414890 <_IO_link_in+0x1a0> + 414876: 48 8d 3d 23 7d 2b 00 lea 0x2b7d23(%rip),%rdi # 6cc5a0 + 41487d: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 414884: e8 77 dd 02 00 callq 442600 <__lll_unlock_wake_private> + 414889: 48 81 c4 80 00 00 00 add $0x80,%rsp + 414890: 48 85 ed test %rbp,%rbp + 414893: 74 0a je 41489f <_IO_link_in+0x1af> + 414895: 31 f6 xor %esi,%esi + 414897: 48 89 e7 mov %rsp,%rdi + 41489a: e8 61 b7 be ff callq 0 <_nl_current_LC_CTYPE> + 41489f: 48 83 c4 28 add $0x28,%rsp + 4148a3: 5b pop %rbx + 4148a4: 5d pop %rbp + 4148a5: f3 c3 repz retq + 4148a7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 4148ae: 00 00 + 4148b0: 48 8b 05 09 58 2b 00 mov 0x2b5809(%rip),%rax # 6ca0c0 <_IO_list_all> + 4148b7: 83 05 da 7c 2b 00 01 addl $0x1,0x2b7cda(%rip) # 6cc598 <_IO_list_all_stamp> + 4148be: 48 89 1d fb 57 2b 00 mov %rbx,0x2b57fb(%rip) # 6ca0c0 <_IO_list_all> + 4148c5: 48 89 43 68 mov %rax,0x68(%rbx) + 4148c9: e9 69 ff ff ff jmpq 414837 <_IO_link_in+0x147> + 4148ce: 66 90 xchg %ax,%ax + 4148d0: 48 c7 04 24 50 41 41 movq $0x414150,(%rsp) + 4148d7: 00 + 4148d8: 48 c7 44 24 08 00 00 movq $0x0,0x8(%rsp) + 4148df: 00 00 + 4148e1: e9 3e fe ff ff jmpq 414724 <_IO_link_in+0x34> + 4148e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4148ed: 00 00 00 + 4148f0: 49 c7 40 08 00 00 00 movq $0x0,0x8(%r8) + 4148f7: 00 + 4148f8: 83 3d bd 88 2b 00 00 cmpl $0x0,0x2b88bd(%rip) # 6cd1bc <__libc_multiple_threads> + 4148ff: 74 08 je 414909 <_IO_link_in+0x219> + 414901: f0 41 ff 08 lock decl (%r8) + 414905: 75 07 jne 41490e <_IO_link_in+0x21e> + 414907: eb 1b jmp 414924 <_IO_link_in+0x234> + 414909: 41 ff 08 decl (%r8) + 41490c: 74 16 je 414924 <_IO_link_in+0x234> + 41490e: 49 8d 38 lea (%r8),%rdi + 414911: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 414918: e8 e3 dc 02 00 callq 442600 <__lll_unlock_wake_private> + 41491d: 48 81 c4 80 00 00 00 add $0x80,%rsp + 414924: 8b 15 7a 7c 2b 00 mov 0x2b7c7a(%rip),%edx # 6cc5a4 + 41492a: e9 08 ff ff ff jmpq 414837 <_IO_link_in+0x147> + 41492f: 90 nop + +0000000000414930 <_IO_least_marker>: + 414930: 48 8b 57 60 mov 0x60(%rdi),%rdx + 414934: 48 89 f0 mov %rsi,%rax + 414937: 48 2b 47 18 sub 0x18(%rdi),%rax + 41493b: 48 85 d2 test %rdx,%rdx + 41493e: 74 13 je 414953 <_IO_least_marker+0x23> + 414940: 48 63 4a 10 movslq 0x10(%rdx),%rcx + 414944: 48 8b 12 mov (%rdx),%rdx + 414947: 48 39 c8 cmp %rcx,%rax + 41494a: 48 0f 4f c1 cmovg %rcx,%rax + 41494e: 48 85 d2 test %rdx,%rdx + 414951: 75 ed jne 414940 <_IO_least_marker+0x10> + 414953: f3 c3 repz retq + 414955: 90 nop + 414956: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41495d: 00 00 00 + +0000000000414960 <_IO_switch_to_main_get_area>: + 414960: 48 8b 47 10 mov 0x10(%rdi),%rax + 414964: 48 8b 57 58 mov 0x58(%rdi),%rdx + 414968: 81 27 ff fe ff ff andl $0xfffffeff,(%rdi) + 41496e: 48 89 57 10 mov %rdx,0x10(%rdi) + 414972: 48 89 47 58 mov %rax,0x58(%rdi) + 414976: 48 8b 57 18 mov 0x18(%rdi),%rdx + 41497a: 48 8b 47 48 mov 0x48(%rdi),%rax + 41497e: 48 89 57 48 mov %rdx,0x48(%rdi) + 414982: 48 89 47 18 mov %rax,0x18(%rdi) + 414986: 48 89 47 08 mov %rax,0x8(%rdi) + 41498a: c3 retq + 41498b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + +0000000000414990 <_IO_switch_to_backup_area>: + 414990: 48 8b 57 10 mov 0x10(%rdi),%rdx + 414994: 48 8b 47 58 mov 0x58(%rdi),%rax + 414998: 48 8b 4f 48 mov 0x48(%rdi),%rcx + 41499c: 81 0f 00 01 00 00 orl $0x100,(%rdi) + 4149a2: 48 89 57 58 mov %rdx,0x58(%rdi) + 4149a6: 48 8b 57 18 mov 0x18(%rdi),%rdx + 4149aa: 48 89 47 10 mov %rax,0x10(%rdi) + 4149ae: 48 89 4f 18 mov %rcx,0x18(%rdi) + 4149b2: 48 89 57 48 mov %rdx,0x48(%rdi) + 4149b6: 48 89 47 08 mov %rax,0x8(%rdi) + 4149ba: c3 retq + 4149bb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + +00000000004149c0 <_IO_switch_to_get_mode>: + 4149c0: 48 8b 47 28 mov 0x28(%rdi),%rax + 4149c4: 48 3b 47 20 cmp 0x20(%rdi),%rax + 4149c8: 53 push %rbx + 4149c9: 48 89 fb mov %rdi,%rbx + 4149cc: 77 42 ja 414a10 <_IO_switch_to_get_mode+0x50> + 4149ce: 8b 13 mov (%rbx),%edx + 4149d0: f6 c6 01 test $0x1,%dh + 4149d3: 75 2b jne 414a00 <_IO_switch_to_get_mode+0x40> + 4149d5: 48 39 43 10 cmp %rax,0x10(%rbx) + 4149d9: 48 8b 4b 38 mov 0x38(%rbx),%rcx + 4149dd: 48 89 4b 18 mov %rcx,0x18(%rbx) + 4149e1: 73 04 jae 4149e7 <_IO_switch_to_get_mode+0x27> + 4149e3: 48 89 43 10 mov %rax,0x10(%rbx) + 4149e7: 80 e6 f7 and $0xf7,%dh + 4149ea: 48 89 43 08 mov %rax,0x8(%rbx) + 4149ee: 48 89 43 30 mov %rax,0x30(%rbx) + 4149f2: 48 89 43 20 mov %rax,0x20(%rbx) + 4149f6: 89 13 mov %edx,(%rbx) + 4149f8: 31 c0 xor %eax,%eax + 4149fa: 5b pop %rbx + 4149fb: c3 retq + 4149fc: 0f 1f 40 00 nopl 0x0(%rax) + 414a00: 48 8b 4b 50 mov 0x50(%rbx),%rcx + 414a04: 48 89 4b 18 mov %rcx,0x18(%rbx) + 414a08: eb dd jmp 4149e7 <_IO_switch_to_get_mode+0x27> + 414a0a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 414a10: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax + 414a17: be ff ff ff ff mov $0xffffffff,%esi + 414a1c: ff 50 18 callq *0x18(%rax) + 414a1f: 83 f8 ff cmp $0xffffffff,%eax + 414a22: 74 d6 je 4149fa <_IO_switch_to_get_mode+0x3a> + 414a24: 48 8b 43 28 mov 0x28(%rbx),%rax + 414a28: eb a4 jmp 4149ce <_IO_switch_to_get_mode+0xe> + 414a2a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + +0000000000414a30 <_IO_free_backup_area>: + 414a30: 53 push %rbx + 414a31: 8b 07 mov (%rdi),%eax + 414a33: 48 89 fb mov %rdi,%rbx + 414a36: f6 c4 01 test $0x1,%ah + 414a39: 74 45 je 414a80 <_IO_free_backup_area+0x50> + 414a3b: 80 e4 fe and $0xfe,%ah + 414a3e: 89 07 mov %eax,(%rdi) + 414a40: 48 8b 47 58 mov 0x58(%rdi),%rax + 414a44: 48 89 47 10 mov %rax,0x10(%rdi) + 414a48: 48 8b 43 48 mov 0x48(%rbx),%rax + 414a4c: 48 8b 7f 18 mov 0x18(%rdi),%rdi + 414a50: 48 89 43 18 mov %rax,0x18(%rbx) + 414a54: 48 89 43 08 mov %rax,0x8(%rbx) + 414a58: e8 53 93 00 00 callq 41ddb0 <__cfree> + 414a5d: 48 c7 43 48 00 00 00 movq $0x0,0x48(%rbx) + 414a64: 00 + 414a65: 48 c7 43 58 00 00 00 movq $0x0,0x58(%rbx) + 414a6c: 00 + 414a6d: 48 c7 43 50 00 00 00 movq $0x0,0x50(%rbx) + 414a74: 00 + 414a75: 5b pop %rbx + 414a76: c3 retq + 414a77: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 414a7e: 00 00 + 414a80: 48 8b 7f 48 mov 0x48(%rdi),%rdi + 414a84: eb d2 jmp 414a58 <_IO_free_backup_area+0x28> + 414a86: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 414a8d: 00 00 00 + +0000000000414a90 <__overflow>: + 414a90: 8b 87 c0 00 00 00 mov 0xc0(%rdi),%eax + 414a96: 85 c0 test %eax,%eax + 414a98: 75 0a jne 414aa4 <__overflow+0x14> + 414a9a: c7 87 c0 00 00 00 ff movl $0xffffffff,0xc0(%rdi) + 414aa1: ff ff ff + 414aa4: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax + 414aab: 48 8b 40 18 mov 0x18(%rax),%rax + 414aaf: ff e0 jmpq *%rax + 414ab1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 414ab6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 414abd: 00 00 00 + +0000000000414ac0 <__underflow>: + 414ac0: 53 push %rbx + 414ac1: 8b 87 c0 00 00 00 mov 0xc0(%rdi),%eax + 414ac7: 85 c0 test %eax,%eax + 414ac9: 75 55 jne 414b20 <__underflow+0x60> + 414acb: c7 87 c0 00 00 00 ff movl $0xffffffff,0xc0(%rdi) + 414ad2: ff ff ff + 414ad5: 8b 07 mov (%rdi),%eax + 414ad7: 48 89 fb mov %rdi,%rbx + 414ada: f6 c4 08 test $0x8,%ah + 414add: 0f 85 85 00 00 00 jne 414b68 <__underflow+0xa8> + 414ae3: 48 8b 57 08 mov 0x8(%rdi),%rdx + 414ae7: 48 8b 77 10 mov 0x10(%rdi),%rsi + 414aeb: 48 39 f2 cmp %rsi,%rdx + 414aee: 72 6d jb 414b5d <__underflow+0x9d> + 414af0: f6 c4 01 test $0x1,%ah + 414af3: 75 3b jne 414b30 <__underflow+0x70> + 414af5: 48 83 7b 60 00 cmpq $0x0,0x60(%rbx) + 414afa: 0f 84 e0 00 00 00 je 414be0 <__underflow+0x120> + 414b00: 48 89 df mov %rbx,%rdi + 414b03: e8 58 f4 ff ff callq 413f60 + 414b08: 85 c0 test %eax,%eax + 414b0a: 75 19 jne 414b25 <__underflow+0x65> + 414b0c: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 414b13: 48 89 df mov %rbx,%rdi + 414b16: 5b pop %rbx + 414b17: 48 8b 40 20 mov 0x20(%rax),%rax + 414b1b: ff e0 jmpq *%rax + 414b1d: 0f 1f 00 nopl (%rax) + 414b20: 83 f8 ff cmp $0xffffffff,%eax + 414b23: 74 b0 je 414ad5 <__underflow+0x15> + 414b25: b8 ff ff ff ff mov $0xffffffff,%eax + 414b2a: 5b pop %rbx + 414b2b: c3 retq + 414b2c: 0f 1f 40 00 nopl 0x0(%rax) + 414b30: 48 8b 4b 58 mov 0x58(%rbx),%rcx + 414b34: 48 8b 53 48 mov 0x48(%rbx),%rdx + 414b38: 80 e4 fe and $0xfe,%ah + 414b3b: 48 89 73 58 mov %rsi,0x58(%rbx) + 414b3f: 48 8b 73 18 mov 0x18(%rbx),%rsi + 414b43: 89 03 mov %eax,(%rbx) + 414b45: 48 39 d1 cmp %rdx,%rcx + 414b48: 48 89 4b 10 mov %rcx,0x10(%rbx) + 414b4c: 48 89 53 18 mov %rdx,0x18(%rbx) + 414b50: 48 89 73 48 mov %rsi,0x48(%rbx) + 414b54: 48 89 53 08 mov %rdx,0x8(%rbx) + 414b58: 48 89 ce mov %rcx,%rsi + 414b5b: 76 98 jbe 414af5 <__underflow+0x35> + 414b5d: 0f b6 02 movzbl (%rdx),%eax + 414b60: 5b pop %rbx + 414b61: c3 retq + 414b62: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 414b68: 48 8b 57 28 mov 0x28(%rdi),%rdx + 414b6c: 48 3b 57 20 cmp 0x20(%rdi),%rdx + 414b70: 77 4e ja 414bc0 <__underflow+0x100> + 414b72: f6 c4 01 test $0x1,%ah + 414b75: 75 31 jne 414ba8 <__underflow+0xe8> + 414b77: 48 8b 73 10 mov 0x10(%rbx),%rsi + 414b7b: 48 8b 4b 38 mov 0x38(%rbx),%rcx + 414b7f: 48 39 d6 cmp %rdx,%rsi + 414b82: 48 89 4b 18 mov %rcx,0x18(%rbx) + 414b86: 73 07 jae 414b8f <__underflow+0xcf> + 414b88: 48 89 53 10 mov %rdx,0x10(%rbx) + 414b8c: 48 89 d6 mov %rdx,%rsi + 414b8f: 80 e4 f7 and $0xf7,%ah + 414b92: 48 89 53 08 mov %rdx,0x8(%rbx) + 414b96: 48 89 53 30 mov %rdx,0x30(%rbx) + 414b9a: 48 89 53 20 mov %rdx,0x20(%rbx) + 414b9e: 89 03 mov %eax,(%rbx) + 414ba0: e9 46 ff ff ff jmpq 414aeb <__underflow+0x2b> + 414ba5: 0f 1f 00 nopl (%rax) + 414ba8: 48 8b 4b 50 mov 0x50(%rbx),%rcx + 414bac: 48 8b 73 10 mov 0x10(%rbx),%rsi + 414bb0: 48 89 4b 18 mov %rcx,0x18(%rbx) + 414bb4: eb d9 jmp 414b8f <__underflow+0xcf> + 414bb6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 414bbd: 00 00 00 + 414bc0: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax + 414bc7: be ff ff ff ff mov $0xffffffff,%esi + 414bcc: ff 50 18 callq *0x18(%rax) + 414bcf: 83 f8 ff cmp $0xffffffff,%eax + 414bd2: 0f 84 4d ff ff ff je 414b25 <__underflow+0x65> + 414bd8: 8b 03 mov (%rbx),%eax + 414bda: 48 8b 53 28 mov 0x28(%rbx),%rdx + 414bde: eb 92 jmp 414b72 <__underflow+0xb2> + 414be0: 48 8b 7b 48 mov 0x48(%rbx),%rdi + 414be4: 48 85 ff test %rdi,%rdi + 414be7: 0f 84 1f ff ff ff je 414b0c <__underflow+0x4c> + 414bed: f6 c4 01 test $0x1,%ah + 414bf0: 74 1c je 414c0e <__underflow+0x14e> + 414bf2: 80 e4 fe and $0xfe,%ah + 414bf5: 48 89 7b 08 mov %rdi,0x8(%rbx) + 414bf9: 89 03 mov %eax,(%rbx) + 414bfb: 48 8b 43 58 mov 0x58(%rbx),%rax + 414bff: 48 89 43 10 mov %rax,0x10(%rbx) + 414c03: 48 8b 43 18 mov 0x18(%rbx),%rax + 414c07: 48 89 7b 18 mov %rdi,0x18(%rbx) + 414c0b: 48 89 c7 mov %rax,%rdi + 414c0e: e8 9d 91 00 00 callq 41ddb0 <__cfree> + 414c13: 48 c7 43 48 00 00 00 movq $0x0,0x48(%rbx) + 414c1a: 00 + 414c1b: 48 c7 43 58 00 00 00 movq $0x0,0x58(%rbx) + 414c22: 00 + 414c23: 48 c7 43 50 00 00 00 movq $0x0,0x50(%rbx) + 414c2a: 00 + 414c2b: e9 dc fe ff ff jmpq 414b0c <__underflow+0x4c> + +0000000000414c30 <__uflow>: + 414c30: 53 push %rbx + 414c31: 8b 87 c0 00 00 00 mov 0xc0(%rdi),%eax + 414c37: 85 c0 test %eax,%eax + 414c39: 75 55 jne 414c90 <__uflow+0x60> + 414c3b: c7 87 c0 00 00 00 ff movl $0xffffffff,0xc0(%rdi) + 414c42: ff ff ff + 414c45: 8b 07 mov (%rdi),%eax + 414c47: 48 89 fb mov %rdi,%rbx + 414c4a: f6 c4 08 test $0x8,%ah + 414c4d: 0f 85 dd 00 00 00 jne 414d30 <__uflow+0x100> + 414c53: 48 8b 57 08 mov 0x8(%rdi),%rdx + 414c57: 48 8b 77 10 mov 0x10(%rdi),%rsi + 414c5b: 48 39 f2 cmp %rsi,%rdx + 414c5e: 0f 82 bc 00 00 00 jb 414d20 <__uflow+0xf0> + 414c64: f6 c4 01 test $0x1,%ah + 414c67: 75 37 jne 414ca0 <__uflow+0x70> + 414c69: 48 83 7b 60 00 cmpq $0x0,0x60(%rbx) + 414c6e: 74 64 je 414cd4 <__uflow+0xa4> + 414c70: 48 89 df mov %rbx,%rdi + 414c73: e8 e8 f2 ff ff callq 413f60 + 414c78: 85 c0 test %eax,%eax + 414c7a: 75 19 jne 414c95 <__uflow+0x65> + 414c7c: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 414c83: 48 89 df mov %rbx,%rdi + 414c86: 5b pop %rbx + 414c87: 48 8b 40 28 mov 0x28(%rax),%rax + 414c8b: ff e0 jmpq *%rax + 414c8d: 0f 1f 00 nopl (%rax) + 414c90: 83 f8 ff cmp $0xffffffff,%eax + 414c93: 74 b0 je 414c45 <__uflow+0x15> + 414c95: b8 ff ff ff ff mov $0xffffffff,%eax + 414c9a: 5b pop %rbx + 414c9b: c3 retq + 414c9c: 0f 1f 40 00 nopl 0x0(%rax) + 414ca0: 48 8b 4b 58 mov 0x58(%rbx),%rcx + 414ca4: 48 8b 53 48 mov 0x48(%rbx),%rdx + 414ca8: 80 e4 fe and $0xfe,%ah + 414cab: 48 89 73 58 mov %rsi,0x58(%rbx) + 414caf: 48 8b 73 18 mov 0x18(%rbx),%rsi + 414cb3: 89 03 mov %eax,(%rbx) + 414cb5: 48 39 d1 cmp %rdx,%rcx + 414cb8: 48 89 4b 10 mov %rcx,0x10(%rbx) + 414cbc: 48 89 53 18 mov %rdx,0x18(%rbx) + 414cc0: 48 89 73 48 mov %rsi,0x48(%rbx) + 414cc4: 77 5a ja 414d20 <__uflow+0xf0> + 414cc6: 48 83 7b 60 00 cmpq $0x0,0x60(%rbx) + 414ccb: 48 89 53 08 mov %rdx,0x8(%rbx) + 414ccf: 48 89 ce mov %rcx,%rsi + 414cd2: 75 9c jne 414c70 <__uflow+0x40> + 414cd4: 48 8b 7b 48 mov 0x48(%rbx),%rdi + 414cd8: 48 85 ff test %rdi,%rdi + 414cdb: 74 9f je 414c7c <__uflow+0x4c> + 414cdd: f6 c4 01 test $0x1,%ah + 414ce0: 74 1c je 414cfe <__uflow+0xce> + 414ce2: 80 e4 fe and $0xfe,%ah + 414ce5: 48 89 7b 08 mov %rdi,0x8(%rbx) + 414ce9: 89 03 mov %eax,(%rbx) + 414ceb: 48 8b 43 58 mov 0x58(%rbx),%rax + 414cef: 48 89 43 10 mov %rax,0x10(%rbx) + 414cf3: 48 8b 43 18 mov 0x18(%rbx),%rax + 414cf7: 48 89 7b 18 mov %rdi,0x18(%rbx) + 414cfb: 48 89 c7 mov %rax,%rdi + 414cfe: e8 ad 90 00 00 callq 41ddb0 <__cfree> + 414d03: 48 c7 43 48 00 00 00 movq $0x0,0x48(%rbx) + 414d0a: 00 + 414d0b: 48 c7 43 58 00 00 00 movq $0x0,0x58(%rbx) + 414d12: 00 + 414d13: 48 c7 43 50 00 00 00 movq $0x0,0x50(%rbx) + 414d1a: 00 + 414d1b: e9 5c ff ff ff jmpq 414c7c <__uflow+0x4c> + 414d20: 48 8d 42 01 lea 0x1(%rdx),%rax + 414d24: 48 89 43 08 mov %rax,0x8(%rbx) + 414d28: 0f b6 02 movzbl (%rdx),%eax + 414d2b: 5b pop %rbx + 414d2c: c3 retq + 414d2d: 0f 1f 00 nopl (%rax) + 414d30: 48 8b 57 28 mov 0x28(%rdi),%rdx + 414d34: 48 3b 57 20 cmp 0x20(%rdi),%rdx + 414d38: 77 46 ja 414d80 <__uflow+0x150> + 414d3a: f6 c4 01 test $0x1,%ah + 414d3d: 75 31 jne 414d70 <__uflow+0x140> + 414d3f: 48 8b 73 10 mov 0x10(%rbx),%rsi + 414d43: 48 8b 4b 38 mov 0x38(%rbx),%rcx + 414d47: 48 39 d6 cmp %rdx,%rsi + 414d4a: 48 89 4b 18 mov %rcx,0x18(%rbx) + 414d4e: 73 07 jae 414d57 <__uflow+0x127> + 414d50: 48 89 53 10 mov %rdx,0x10(%rbx) + 414d54: 48 89 d6 mov %rdx,%rsi + 414d57: 80 e4 f7 and $0xf7,%ah + 414d5a: 48 89 53 08 mov %rdx,0x8(%rbx) + 414d5e: 48 89 53 30 mov %rdx,0x30(%rbx) + 414d62: 48 89 53 20 mov %rdx,0x20(%rbx) + 414d66: 89 03 mov %eax,(%rbx) + 414d68: e9 ee fe ff ff jmpq 414c5b <__uflow+0x2b> + 414d6d: 0f 1f 00 nopl (%rax) + 414d70: 48 8b 4b 50 mov 0x50(%rbx),%rcx + 414d74: 48 8b 73 10 mov 0x10(%rbx),%rsi + 414d78: 48 89 4b 18 mov %rcx,0x18(%rbx) + 414d7c: eb d9 jmp 414d57 <__uflow+0x127> + 414d7e: 66 90 xchg %ax,%ax + 414d80: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax + 414d87: be ff ff ff ff mov $0xffffffff,%esi + 414d8c: ff 50 18 callq *0x18(%rax) + 414d8f: 83 f8 ff cmp $0xffffffff,%eax + 414d92: 0f 84 fd fe ff ff je 414c95 <__uflow+0x65> + 414d98: 8b 03 mov (%rbx),%eax + 414d9a: 48 8b 53 28 mov 0x28(%rbx),%rdx + 414d9e: eb 9a jmp 414d3a <__uflow+0x10a> + +0000000000414da0 <_IO_setb>: + 414da0: 53 push %rbx + 414da1: 48 89 fb mov %rdi,%rbx + 414da4: 48 83 ec 20 sub $0x20,%rsp + 414da8: 48 8b 7f 38 mov 0x38(%rdi),%rdi + 414dac: 8b 03 mov (%rbx),%eax + 414dae: 48 85 ff test %rdi,%rdi + 414db1: 74 04 je 414db7 <_IO_setb+0x17> + 414db3: a8 01 test $0x1,%al + 414db5: 74 21 je 414dd8 <_IO_setb+0x38> + 414db7: 48 89 53 40 mov %rdx,0x40(%rbx) + 414dbb: 89 c2 mov %eax,%edx + 414dbd: 83 c8 01 or $0x1,%eax + 414dc0: 83 e2 fe and $0xfffffffe,%edx + 414dc3: 85 c9 test %ecx,%ecx + 414dc5: 48 89 73 38 mov %rsi,0x38(%rbx) + 414dc9: 0f 45 c2 cmovne %edx,%eax + 414dcc: 89 03 mov %eax,(%rbx) + 414dce: 48 83 c4 20 add $0x20,%rsp + 414dd2: 5b pop %rbx + 414dd3: c3 retq + 414dd4: 0f 1f 40 00 nopl 0x0(%rax) + 414dd8: 89 4c 24 1c mov %ecx,0x1c(%rsp) + 414ddc: 48 89 54 24 10 mov %rdx,0x10(%rsp) + 414de1: 48 89 74 24 08 mov %rsi,0x8(%rsp) + 414de6: e8 c5 8f 00 00 callq 41ddb0 <__cfree> + 414deb: 8b 03 mov (%rbx),%eax + 414ded: 8b 4c 24 1c mov 0x1c(%rsp),%ecx + 414df1: 48 8b 54 24 10 mov 0x10(%rsp),%rdx + 414df6: 48 8b 74 24 08 mov 0x8(%rsp),%rsi + 414dfb: eb ba jmp 414db7 <_IO_setb+0x17> + 414dfd: 0f 1f 00 nopl (%rax) + +0000000000414e00 <_IO_doallocbuf>: + 414e00: 48 83 7f 38 00 cmpq $0x0,0x38(%rdi) + 414e05: 74 09 je 414e10 <_IO_doallocbuf+0x10> + 414e07: c3 retq + 414e08: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 414e0f: 00 + 414e10: 41 54 push %r12 + 414e12: 55 push %rbp + 414e13: 53 push %rbx + 414e14: 8b 07 mov (%rdi),%eax + 414e16: 48 89 fb mov %rdi,%rbx + 414e19: a8 02 test $0x2,%al + 414e1b: 74 0a je 414e27 <_IO_doallocbuf+0x27> + 414e1d: 8b 97 c0 00 00 00 mov 0xc0(%rdi),%edx + 414e23: 85 d2 test %edx,%edx + 414e25: 7e 49 jle 414e70 <_IO_doallocbuf+0x70> + 414e27: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 414e2e: 48 89 df mov %rbx,%rdi + 414e31: ff 50 68 callq *0x68(%rax) + 414e34: 83 f8 ff cmp $0xffffffff,%eax + 414e37: 74 07 je 414e40 <_IO_doallocbuf+0x40> + 414e39: 5b pop %rbx + 414e3a: 5d pop %rbp + 414e3b: 41 5c pop %r12 + 414e3d: c3 retq + 414e3e: 66 90 xchg %ax,%ax + 414e40: 48 8b 7b 38 mov 0x38(%rbx),%rdi + 414e44: 4c 8d a3 84 00 00 00 lea 0x84(%rbx),%r12 + 414e4b: 48 8d ab 83 00 00 00 lea 0x83(%rbx),%rbp + 414e52: 8b 03 mov (%rbx),%eax + 414e54: 48 85 ff test %rdi,%rdi + 414e57: 74 04 je 414e5d <_IO_doallocbuf+0x5d> + 414e59: a8 01 test $0x1,%al + 414e5b: 74 23 je 414e80 <_IO_doallocbuf+0x80> + 414e5d: 83 c8 01 or $0x1,%eax + 414e60: 48 89 6b 38 mov %rbp,0x38(%rbx) + 414e64: 4c 89 63 40 mov %r12,0x40(%rbx) + 414e68: 89 03 mov %eax,(%rbx) + 414e6a: eb cd jmp 414e39 <_IO_doallocbuf+0x39> + 414e6c: 0f 1f 40 00 nopl 0x0(%rax) + 414e70: 4c 8d a7 84 00 00 00 lea 0x84(%rdi),%r12 + 414e77: 48 8d af 83 00 00 00 lea 0x83(%rdi),%rbp + 414e7e: eb dd jmp 414e5d <_IO_doallocbuf+0x5d> + 414e80: e8 2b 8f 00 00 callq 41ddb0 <__cfree> + 414e85: 8b 03 mov (%rbx),%eax + 414e87: eb d4 jmp 414e5d <_IO_doallocbuf+0x5d> + 414e89: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + +0000000000414e90 <_IO_default_underflow>: + 414e90: b8 ff ff ff ff mov $0xffffffff,%eax + 414e95: c3 retq + 414e96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 414e9d: 00 00 00 + +0000000000414ea0 <_IO_default_uflow>: + 414ea0: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax + 414ea7: 53 push %rbx + 414ea8: 48 89 fb mov %rdi,%rbx + 414eab: ff 50 20 callq *0x20(%rax) + 414eae: 83 f8 ff cmp $0xffffffff,%eax + 414eb1: 74 0f je 414ec2 <_IO_default_uflow+0x22> + 414eb3: 48 8b 43 08 mov 0x8(%rbx),%rax + 414eb7: 48 8d 50 01 lea 0x1(%rax),%rdx + 414ebb: 48 89 53 08 mov %rdx,0x8(%rbx) + 414ebf: 0f b6 00 movzbl (%rax),%eax + 414ec2: 5b pop %rbx + 414ec3: c3 retq + 414ec4: 66 90 xchg %ax,%ax + 414ec6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 414ecd: 00 00 00 + +0000000000414ed0 <_IO_default_xsputn>: + 414ed0: 48 85 d2 test %rdx,%rdx + 414ed3: 0f 84 b7 00 00 00 je 414f90 <_IO_default_xsputn+0xc0> + 414ed9: 41 56 push %r14 + 414edb: 41 55 push %r13 + 414edd: 49 89 f6 mov %rsi,%r14 + 414ee0: 41 54 push %r12 + 414ee2: 55 push %rbp + 414ee3: 49 89 fc mov %rdi,%r12 + 414ee6: 53 push %rbx + 414ee7: 49 89 d5 mov %rdx,%r13 + 414eea: 48 89 d5 mov %rdx,%rbp + 414eed: 0f 1f 00 nopl (%rax) + 414ef0: 49 8b 7c 24 28 mov 0x28(%r12),%rdi + 414ef5: 49 8b 5c 24 30 mov 0x30(%r12),%rbx + 414efa: 48 39 df cmp %rbx,%rdi + 414efd: 73 36 jae 414f35 <_IO_default_xsputn+0x65> + 414eff: 48 29 fb sub %rdi,%rbx + 414f02: 48 39 dd cmp %rbx,%rbp + 414f05: 48 0f 46 dd cmovbe %rbp,%rbx + 414f09: 48 83 fb 14 cmp $0x14,%rbx + 414f0d: 77 51 ja 414f60 <_IO_default_xsputn+0x90> + 414f0f: 48 85 db test %rbx,%rbx + 414f12: 74 1e je 414f32 <_IO_default_xsputn+0x62> + 414f14: 31 c0 xor %eax,%eax + 414f16: 41 0f b6 14 06 movzbl (%r14,%rax,1),%edx + 414f1b: 88 14 07 mov %dl,(%rdi,%rax,1) + 414f1e: 48 83 c0 01 add $0x1,%rax + 414f22: 48 39 c3 cmp %rax,%rbx + 414f25: 75 ef jne 414f16 <_IO_default_xsputn+0x46> + 414f27: 48 01 df add %rbx,%rdi + 414f2a: 49 01 de add %rbx,%r14 + 414f2d: 49 89 7c 24 28 mov %rdi,0x28(%r12) + 414f32: 48 29 dd sub %rbx,%rbp + 414f35: 48 85 ed test %rbp,%rbp + 414f38: 74 3e je 414f78 <_IO_default_xsputn+0xa8> + 414f3a: 49 8b 84 24 d8 00 00 mov 0xd8(%r12),%rax + 414f41: 00 + 414f42: 41 0f b6 36 movzbl (%r14),%esi + 414f46: 4c 89 e7 mov %r12,%rdi + 414f49: 49 8d 5e 01 lea 0x1(%r14),%rbx + 414f4d: ff 50 18 callq *0x18(%rax) + 414f50: 83 f8 ff cmp $0xffffffff,%eax + 414f53: 74 23 je 414f78 <_IO_default_xsputn+0xa8> + 414f55: 48 83 ed 01 sub $0x1,%rbp + 414f59: 49 89 de mov %rbx,%r14 + 414f5c: eb 92 jmp 414ef0 <_IO_default_xsputn+0x20> + 414f5e: 66 90 xchg %ax,%ax + 414f60: 4c 89 f6 mov %r14,%rsi + 414f63: 48 89 da mov %rbx,%rdx + 414f66: 49 01 de add %rbx,%r14 + 414f69: e8 52 16 01 00 callq 4265c0 <__mempcpy> + 414f6e: 49 89 44 24 28 mov %rax,0x28(%r12) + 414f73: eb bd jmp 414f32 <_IO_default_xsputn+0x62> + 414f75: 0f 1f 00 nopl (%rax) + 414f78: 4c 89 e8 mov %r13,%rax + 414f7b: 5b pop %rbx + 414f7c: 48 29 e8 sub %rbp,%rax + 414f7f: 5d pop %rbp + 414f80: 41 5c pop %r12 + 414f82: 41 5d pop %r13 + 414f84: 41 5e pop %r14 + 414f86: c3 retq + 414f87: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 414f8e: 00 00 + 414f90: 31 c0 xor %eax,%eax + 414f92: c3 retq + 414f93: 0f 1f 00 nopl (%rax) + 414f96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 414f9d: 00 00 00 + +0000000000414fa0 <_IO_sgetn>: + 414fa0: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax + 414fa7: 48 8b 40 40 mov 0x40(%rax),%rax + 414fab: ff e0 jmpq *%rax + 414fad: 0f 1f 00 nopl (%rax) + +0000000000414fb0 <_IO_default_xsgetn>: + 414fb0: 41 56 push %r14 + 414fb2: 41 55 push %r13 + 414fb4: 49 89 d6 mov %rdx,%r14 + 414fb7: 41 54 push %r12 + 414fb9: 49 89 f4 mov %rsi,%r12 + 414fbc: 55 push %rbp + 414fbd: 53 push %rbx + 414fbe: 48 8b 4f 08 mov 0x8(%rdi),%rcx + 414fc2: 48 89 fb mov %rdi,%rbx + 414fc5: 48 8b 77 10 mov 0x10(%rdi),%rsi + 414fc9: 49 89 d5 mov %rdx,%r13 + 414fcc: 0f 1f 40 00 nopl 0x0(%rax) + 414fd0: 48 39 ce cmp %rcx,%rsi + 414fd3: 76 4a jbe 41501f <_IO_default_xsgetn+0x6f> + 414fd5: 48 29 ce sub %rcx,%rsi + 414fd8: 49 39 f6 cmp %rsi,%r14 + 414fdb: 49 0f 46 f6 cmovbe %r14,%rsi + 414fdf: 48 83 fe 14 cmp $0x14,%rsi + 414fe3: 48 89 f5 mov %rsi,%rbp + 414fe6: 0f 87 44 01 00 00 ja 415130 <_IO_default_xsgetn+0x180> + 414fec: 48 85 f6 test %rsi,%rsi + 414fef: 74 2b je 41501c <_IO_default_xsgetn+0x6c> + 414ff1: 8d 76 ff lea -0x1(%rsi),%esi + 414ff4: 31 c0 xor %eax,%eax + 414ff6: 48 89 f2 mov %rsi,%rdx + 414ff9: 48 83 c6 01 add $0x1,%rsi + 414ffd: 0f b6 3c 01 movzbl (%rcx,%rax,1),%edi + 415001: 41 88 3c 04 mov %dil,(%r12,%rax,1) + 415005: 48 83 c0 01 add $0x1,%rax + 415009: 48 39 f0 cmp %rsi,%rax + 41500c: 75 ef jne 414ffd <_IO_default_xsgetn+0x4d> + 41500e: 48 83 c2 01 add $0x1,%rdx + 415012: 49 01 d4 add %rdx,%r12 + 415015: 48 01 ca add %rcx,%rdx + 415018: 48 89 53 08 mov %rdx,0x8(%rbx) + 41501c: 49 29 ee sub %rbp,%r14 + 41501f: 4d 85 f6 test %r14,%r14 + 415022: 0f 84 b1 00 00 00 je 4150d9 <_IO_default_xsgetn+0x129> + 415028: 8b 83 c0 00 00 00 mov 0xc0(%rbx),%eax + 41502e: 85 c0 test %eax,%eax + 415030: 0f 85 9a 00 00 00 jne 4150d0 <_IO_default_xsgetn+0x120> + 415036: c7 83 c0 00 00 00 ff movl $0xffffffff,0xc0(%rbx) + 41503d: ff ff ff + 415040: 8b 03 mov (%rbx),%eax + 415042: f6 c4 08 test $0x8,%ah + 415045: 0f 85 a5 00 00 00 jne 4150f0 <_IO_default_xsgetn+0x140> + 41504b: 48 8b 4b 08 mov 0x8(%rbx),%rcx + 41504f: 48 8b 73 10 mov 0x10(%rbx),%rsi + 415053: 48 39 ce cmp %rcx,%rsi + 415056: 0f 87 74 ff ff ff ja 414fd0 <_IO_default_xsgetn+0x20> + 41505c: f6 c4 01 test $0x1,%ah + 41505f: 74 31 je 415092 <_IO_default_xsgetn+0xe2> + 415061: 48 8b 53 58 mov 0x58(%rbx),%rdx + 415065: 48 8b 4b 48 mov 0x48(%rbx),%rcx + 415069: 80 e4 fe and $0xfe,%ah + 41506c: 48 89 73 58 mov %rsi,0x58(%rbx) + 415070: 48 8b 73 18 mov 0x18(%rbx),%rsi + 415074: 89 03 mov %eax,(%rbx) + 415076: 48 39 ca cmp %rcx,%rdx + 415079: 48 89 53 10 mov %rdx,0x10(%rbx) + 41507d: 48 89 4b 18 mov %rcx,0x18(%rbx) + 415081: 48 89 73 48 mov %rsi,0x48(%rbx) + 415085: 48 89 4b 08 mov %rcx,0x8(%rbx) + 415089: 48 89 d6 mov %rdx,%rsi + 41508c: 0f 87 3e ff ff ff ja 414fd0 <_IO_default_xsgetn+0x20> + 415092: 48 83 7b 60 00 cmpq $0x0,0x60(%rbx) + 415097: 0f 84 b3 00 00 00 je 415150 <_IO_default_xsgetn+0x1a0> + 41509d: 48 89 df mov %rbx,%rdi + 4150a0: e8 bb ee ff ff callq 413f60 + 4150a5: 85 c0 test %eax,%eax + 4150a7: 75 30 jne 4150d9 <_IO_default_xsgetn+0x129> + 4150a9: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 4150b0: 48 89 df mov %rbx,%rdi + 4150b3: ff 50 20 callq *0x20(%rax) + 4150b6: 83 f8 ff cmp $0xffffffff,%eax + 4150b9: 74 1e je 4150d9 <_IO_default_xsgetn+0x129> + 4150bb: 48 8b 4b 08 mov 0x8(%rbx),%rcx + 4150bf: 48 8b 73 10 mov 0x10(%rbx),%rsi + 4150c3: e9 08 ff ff ff jmpq 414fd0 <_IO_default_xsgetn+0x20> + 4150c8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 4150cf: 00 + 4150d0: 83 f8 ff cmp $0xffffffff,%eax + 4150d3: 0f 84 67 ff ff ff je 415040 <_IO_default_xsgetn+0x90> + 4150d9: 4c 89 e8 mov %r13,%rax + 4150dc: 5b pop %rbx + 4150dd: 4c 29 f0 sub %r14,%rax + 4150e0: 5d pop %rbp + 4150e1: 41 5c pop %r12 + 4150e3: 41 5d pop %r13 + 4150e5: 41 5e pop %r14 + 4150e7: c3 retq + 4150e8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 4150ef: 00 + 4150f0: 48 8b 4b 28 mov 0x28(%rbx),%rcx + 4150f4: 48 3b 4b 20 cmp 0x20(%rbx),%rcx + 4150f8: 0f 87 ca 00 00 00 ja 4151c8 <_IO_default_xsgetn+0x218> + 4150fe: f6 c4 01 test $0x1,%ah + 415101: 0f 84 99 00 00 00 je 4151a0 <_IO_default_xsgetn+0x1f0> + 415107: 48 8b 53 50 mov 0x50(%rbx),%rdx + 41510b: 48 8b 73 10 mov 0x10(%rbx),%rsi + 41510f: 48 89 53 18 mov %rdx,0x18(%rbx) + 415113: 80 e4 f7 and $0xf7,%ah + 415116: 48 89 4b 08 mov %rcx,0x8(%rbx) + 41511a: 48 89 4b 30 mov %rcx,0x30(%rbx) + 41511e: 48 89 4b 20 mov %rcx,0x20(%rbx) + 415122: 89 03 mov %eax,(%rbx) + 415124: e9 2a ff ff ff jmpq 415053 <_IO_default_xsgetn+0xa3> + 415129: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 415130: 48 89 f2 mov %rsi,%rdx + 415133: 4c 89 e7 mov %r12,%rdi + 415136: 48 89 ce mov %rcx,%rsi + 415139: e8 82 14 01 00 callq 4265c0 <__mempcpy> + 41513e: 48 01 6b 08 add %rbp,0x8(%rbx) + 415142: 49 89 c4 mov %rax,%r12 + 415145: e9 d2 fe ff ff jmpq 41501c <_IO_default_xsgetn+0x6c> + 41514a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 415150: 48 8b 7b 48 mov 0x48(%rbx),%rdi + 415154: 48 85 ff test %rdi,%rdi + 415157: 0f 84 4c ff ff ff je 4150a9 <_IO_default_xsgetn+0xf9> + 41515d: f6 c4 01 test $0x1,%ah + 415160: 74 1c je 41517e <_IO_default_xsgetn+0x1ce> + 415162: 80 e4 fe and $0xfe,%ah + 415165: 48 89 7b 08 mov %rdi,0x8(%rbx) + 415169: 89 03 mov %eax,(%rbx) + 41516b: 48 8b 43 58 mov 0x58(%rbx),%rax + 41516f: 48 89 43 10 mov %rax,0x10(%rbx) + 415173: 48 8b 43 18 mov 0x18(%rbx),%rax + 415177: 48 89 7b 18 mov %rdi,0x18(%rbx) + 41517b: 48 89 c7 mov %rax,%rdi + 41517e: e8 2d 8c 00 00 callq 41ddb0 <__cfree> + 415183: 48 c7 43 48 00 00 00 movq $0x0,0x48(%rbx) + 41518a: 00 + 41518b: 48 c7 43 58 00 00 00 movq $0x0,0x58(%rbx) + 415192: 00 + 415193: 48 c7 43 50 00 00 00 movq $0x0,0x50(%rbx) + 41519a: 00 + 41519b: e9 09 ff ff ff jmpq 4150a9 <_IO_default_xsgetn+0xf9> + 4151a0: 48 8b 73 10 mov 0x10(%rbx),%rsi + 4151a4: 48 8b 53 38 mov 0x38(%rbx),%rdx + 4151a8: 48 39 ce cmp %rcx,%rsi + 4151ab: 48 89 53 18 mov %rdx,0x18(%rbx) + 4151af: 0f 83 5e ff ff ff jae 415113 <_IO_default_xsgetn+0x163> + 4151b5: 48 89 4b 10 mov %rcx,0x10(%rbx) + 4151b9: 48 89 ce mov %rcx,%rsi + 4151bc: e9 52 ff ff ff jmpq 415113 <_IO_default_xsgetn+0x163> + 4151c1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4151c8: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 4151cf: be ff ff ff ff mov $0xffffffff,%esi + 4151d4: 48 89 df mov %rbx,%rdi + 4151d7: ff 50 18 callq *0x18(%rax) + 4151da: 83 f8 ff cmp $0xffffffff,%eax + 4151dd: 0f 84 f6 fe ff ff je 4150d9 <_IO_default_xsgetn+0x129> + 4151e3: 8b 03 mov (%rbx),%eax + 4151e5: 48 8b 4b 28 mov 0x28(%rbx),%rcx + 4151e9: e9 10 ff ff ff jmpq 4150fe <_IO_default_xsgetn+0x14e> + 4151ee: 66 90 xchg %ax,%ax + +00000000004151f0 <_IO_default_setbuf>: + 4151f0: 41 54 push %r12 + 4151f2: 55 push %rbp + 4151f3: 49 89 f4 mov %rsi,%r12 + 4151f6: 53 push %rbx + 4151f7: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax + 4151fe: 48 89 fb mov %rdi,%rbx + 415201: 48 89 d5 mov %rdx,%rbp + 415204: ff 50 60 callq *0x60(%rax) + 415207: 83 f8 ff cmp $0xffffffff,%eax + 41520a: 0f 84 a0 00 00 00 je 4152b0 <_IO_default_setbuf+0xc0> + 415210: 8b 13 mov (%rbx),%edx + 415212: 4d 85 e4 test %r12,%r12 + 415215: 89 d0 mov %edx,%eax + 415217: 74 67 je 415280 <_IO_default_setbuf+0x90> + 415219: 48 85 ed test %rbp,%rbp + 41521c: 74 62 je 415280 <_IO_default_setbuf+0x90> + 41521e: 48 8b 7b 38 mov 0x38(%rbx),%rdi + 415222: 83 e0 fd and $0xfffffffd,%eax + 415225: 4c 01 e5 add %r12,%rbp + 415228: 89 03 mov %eax,(%rbx) + 41522a: 48 85 ff test %rdi,%rdi + 41522d: 74 05 je 415234 <_IO_default_setbuf+0x44> + 41522f: 83 e2 01 and $0x1,%edx + 415232: 74 6d je 4152a1 <_IO_default_setbuf+0xb1> + 415234: 83 c8 01 or $0x1,%eax + 415237: 4c 89 63 38 mov %r12,0x38(%rbx) + 41523b: 48 89 6b 40 mov %rbp,0x40(%rbx) + 41523f: 89 03 mov %eax,(%rbx) + 415241: 48 c7 43 30 00 00 00 movq $0x0,0x30(%rbx) + 415248: 00 + 415249: 48 89 d8 mov %rbx,%rax + 41524c: 48 c7 43 28 00 00 00 movq $0x0,0x28(%rbx) + 415253: 00 + 415254: 48 c7 43 20 00 00 00 movq $0x0,0x20(%rbx) + 41525b: 00 + 41525c: 48 c7 43 10 00 00 00 movq $0x0,0x10(%rbx) + 415263: 00 + 415264: 48 c7 43 08 00 00 00 movq $0x0,0x8(%rbx) + 41526b: 00 + 41526c: 48 c7 43 18 00 00 00 movq $0x0,0x18(%rbx) + 415273: 00 + 415274: 5b pop %rbx + 415275: 5d pop %rbp + 415276: 41 5c pop %r12 + 415278: c3 retq + 415279: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 415280: 48 8b 7b 38 mov 0x38(%rbx),%rdi + 415284: 83 c8 02 or $0x2,%eax + 415287: 48 8d ab 84 00 00 00 lea 0x84(%rbx),%rbp + 41528e: 89 03 mov %eax,(%rbx) + 415290: 4c 8d a3 83 00 00 00 lea 0x83(%rbx),%r12 + 415297: 48 85 ff test %rdi,%rdi + 41529a: 74 98 je 415234 <_IO_default_setbuf+0x44> + 41529c: 83 e2 01 and $0x1,%edx + 41529f: 75 93 jne 415234 <_IO_default_setbuf+0x44> + 4152a1: e8 0a 8b 00 00 callq 41ddb0 <__cfree> + 4152a6: 8b 03 mov (%rbx),%eax + 4152a8: eb 8a jmp 415234 <_IO_default_setbuf+0x44> + 4152aa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4152b0: 31 c0 xor %eax,%eax + 4152b2: eb c0 jmp 415274 <_IO_default_setbuf+0x84> + 4152b4: 66 90 xchg %ax,%ax + 4152b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4152bd: 00 00 00 + +00000000004152c0 <_IO_default_seekpos>: + 4152c0: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax + 4152c7: 89 d1 mov %edx,%ecx + 4152c9: 31 d2 xor %edx,%edx + 4152cb: 48 8b 40 48 mov 0x48(%rax),%rax + 4152cf: ff e0 jmpq *%rax + 4152d1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4152d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4152dd: 00 00 00 + +00000000004152e0 <_IO_default_doallocate>: + 4152e0: 41 54 push %r12 + 4152e2: 55 push %rbp + 4152e3: 53 push %rbx + 4152e4: 48 89 fb mov %rdi,%rbx + 4152e7: bf 00 20 00 00 mov $0x2000,%edi + 4152ec: e8 1f 87 00 00 callq 41da10 <__libc_malloc> + 4152f1: 48 89 c5 mov %rax,%rbp + 4152f4: b8 ff ff ff ff mov $0xffffffff,%eax + 4152f9: 48 85 ed test %rbp,%rbp + 4152fc: 74 29 je 415327 <_IO_default_doallocate+0x47> + 4152fe: 48 8b 7b 38 mov 0x38(%rbx),%rdi + 415302: 4c 8d a5 00 20 00 00 lea 0x2000(%rbp),%r12 + 415309: 8b 13 mov (%rbx),%edx + 41530b: 48 85 ff test %rdi,%rdi + 41530e: 74 05 je 415315 <_IO_default_doallocate+0x35> + 415310: f6 c2 01 test $0x1,%dl + 415313: 74 1b je 415330 <_IO_default_doallocate+0x50> + 415315: 83 e2 fe and $0xfffffffe,%edx + 415318: 48 89 6b 38 mov %rbp,0x38(%rbx) + 41531c: 4c 89 63 40 mov %r12,0x40(%rbx) + 415320: 89 13 mov %edx,(%rbx) + 415322: b8 01 00 00 00 mov $0x1,%eax + 415327: 5b pop %rbx + 415328: 5d pop %rbp + 415329: 41 5c pop %r12 + 41532b: c3 retq + 41532c: 0f 1f 40 00 nopl 0x0(%rax) + 415330: e8 7b 8a 00 00 callq 41ddb0 <__cfree> + 415335: 8b 13 mov (%rbx),%edx + 415337: eb dc jmp 415315 <_IO_default_doallocate+0x35> + 415339: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + +0000000000415340 <_IO_init>: + 415340: 31 c0 xor %eax,%eax + 415342: 81 ce 00 00 ad fb or $0xfbad0000,%esi + 415348: c7 47 74 00 00 00 00 movl $0x0,0x74(%rdi) + 41534f: 66 89 87 80 00 00 00 mov %ax,0x80(%rdi) + 415356: 48 8b 87 88 00 00 00 mov 0x88(%rdi),%rax + 41535d: 89 37 mov %esi,(%rdi) + 41535f: 48 c7 47 38 00 00 00 movq $0x0,0x38(%rdi) + 415366: 00 + 415367: 48 c7 47 40 00 00 00 movq $0x0,0x40(%rdi) + 41536e: 00 + 41536f: 48 c7 47 18 00 00 00 movq $0x0,0x18(%rdi) + 415376: 00 + 415377: 48 85 c0 test %rax,%rax + 41537a: 48 c7 47 08 00 00 00 movq $0x0,0x8(%rdi) + 415381: 00 + 415382: 48 c7 47 10 00 00 00 movq $0x0,0x10(%rdi) + 415389: 00 + 41538a: 48 c7 47 20 00 00 00 movq $0x0,0x20(%rdi) + 415391: 00 + 415392: 48 c7 47 28 00 00 00 movq $0x0,0x28(%rdi) + 415399: 00 + 41539a: 48 c7 47 30 00 00 00 movq $0x0,0x30(%rdi) + 4153a1: 00 + 4153a2: 48 c7 47 68 00 00 00 movq $0x0,0x68(%rdi) + 4153a9: 00 + 4153aa: 48 c7 47 48 00 00 00 movq $0x0,0x48(%rdi) + 4153b1: 00 + 4153b2: 48 c7 47 50 00 00 00 movq $0x0,0x50(%rdi) + 4153b9: 00 + 4153ba: 48 c7 47 58 00 00 00 movq $0x0,0x58(%rdi) + 4153c1: 00 + 4153c2: 48 c7 47 60 00 00 00 movq $0x0,0x60(%rdi) + 4153c9: 00 + 4153ca: 74 15 je 4153e1 <_IO_init+0xa1> + 4153cc: c7 00 00 00 00 00 movl $0x0,(%rax) + 4153d2: c7 40 04 00 00 00 00 movl $0x0,0x4(%rax) + 4153d9: 48 c7 40 08 00 00 00 movq $0x0,0x8(%rax) + 4153e0: 00 + 4153e1: c7 87 c0 00 00 00 ff movl $0xffffffff,0xc0(%rdi) + 4153e8: ff ff ff + 4153eb: 48 c7 87 a0 00 00 00 movq $0xffffffffffffffff,0xa0(%rdi) + 4153f2: ff ff ff ff + 4153f6: 48 c7 87 a8 00 00 00 movq $0x0,0xa8(%rdi) + 4153fd: 00 00 00 00 + 415401: c3 retq + 415402: 0f 1f 40 00 nopl 0x0(%rax) + 415406: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41540d: 00 00 00 + +0000000000415410 <_IO_old_init>: + 415410: 31 c0 xor %eax,%eax + 415412: 81 ce 00 00 ad fb or $0xfbad0000,%esi + 415418: c7 47 74 00 00 00 00 movl $0x0,0x74(%rdi) + 41541f: 66 89 87 80 00 00 00 mov %ax,0x80(%rdi) + 415426: 48 8b 87 88 00 00 00 mov 0x88(%rdi),%rax + 41542d: 89 37 mov %esi,(%rdi) + 41542f: 48 c7 47 38 00 00 00 movq $0x0,0x38(%rdi) + 415436: 00 + 415437: 48 c7 47 40 00 00 00 movq $0x0,0x40(%rdi) + 41543e: 00 + 41543f: 48 c7 47 18 00 00 00 movq $0x0,0x18(%rdi) + 415446: 00 + 415447: 48 85 c0 test %rax,%rax + 41544a: 48 c7 47 08 00 00 00 movq $0x0,0x8(%rdi) + 415451: 00 + 415452: 48 c7 47 10 00 00 00 movq $0x0,0x10(%rdi) + 415459: 00 + 41545a: 48 c7 47 20 00 00 00 movq $0x0,0x20(%rdi) + 415461: 00 + 415462: 48 c7 47 28 00 00 00 movq $0x0,0x28(%rdi) + 415469: 00 + 41546a: 48 c7 47 30 00 00 00 movq $0x0,0x30(%rdi) + 415471: 00 + 415472: 48 c7 47 68 00 00 00 movq $0x0,0x68(%rdi) + 415479: 00 + 41547a: 48 c7 47 48 00 00 00 movq $0x0,0x48(%rdi) + 415481: 00 + 415482: 48 c7 47 50 00 00 00 movq $0x0,0x50(%rdi) + 415489: 00 + 41548a: 48 c7 47 58 00 00 00 movq $0x0,0x58(%rdi) + 415491: 00 + 415492: 48 c7 47 60 00 00 00 movq $0x0,0x60(%rdi) + 415499: 00 + 41549a: 74 15 je 4154b1 <_IO_old_init+0xa1> + 41549c: c7 00 00 00 00 00 movl $0x0,(%rax) + 4154a2: c7 40 04 00 00 00 00 movl $0x0,0x4(%rax) + 4154a9: 48 c7 40 08 00 00 00 movq $0x0,0x8(%rax) + 4154b0: 00 + 4154b1: f3 c3 repz retq + 4154b3: 0f 1f 00 nopl (%rax) + 4154b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4154bd: 00 00 00 + +00000000004154c0 <_IO_no_init>: + 4154c0: 31 c0 xor %eax,%eax + 4154c2: 81 ce 00 00 ad fb or $0xfbad0000,%esi + 4154c8: c7 47 74 00 00 00 00 movl $0x0,0x74(%rdi) + 4154cf: 66 89 87 80 00 00 00 mov %ax,0x80(%rdi) + 4154d6: 48 8b 87 88 00 00 00 mov 0x88(%rdi),%rax + 4154dd: 89 37 mov %esi,(%rdi) + 4154df: 48 c7 47 38 00 00 00 movq $0x0,0x38(%rdi) + 4154e6: 00 + 4154e7: 48 c7 47 40 00 00 00 movq $0x0,0x40(%rdi) + 4154ee: 00 + 4154ef: 48 c7 47 18 00 00 00 movq $0x0,0x18(%rdi) + 4154f6: 00 + 4154f7: 48 85 c0 test %rax,%rax + 4154fa: 48 c7 47 08 00 00 00 movq $0x0,0x8(%rdi) + 415501: 00 + 415502: 48 c7 47 10 00 00 00 movq $0x0,0x10(%rdi) + 415509: 00 + 41550a: 48 c7 47 20 00 00 00 movq $0x0,0x20(%rdi) + 415511: 00 + 415512: 48 c7 47 28 00 00 00 movq $0x0,0x28(%rdi) + 415519: 00 + 41551a: 48 c7 47 30 00 00 00 movq $0x0,0x30(%rdi) + 415521: 00 + 415522: 48 c7 47 68 00 00 00 movq $0x0,0x68(%rdi) + 415529: 00 + 41552a: 48 c7 47 48 00 00 00 movq $0x0,0x48(%rdi) + 415531: 00 + 415532: 48 c7 47 50 00 00 00 movq $0x0,0x50(%rdi) + 415539: 00 + 41553a: 48 c7 47 58 00 00 00 movq $0x0,0x58(%rdi) + 415541: 00 + 415542: 48 c7 47 60 00 00 00 movq $0x0,0x60(%rdi) + 415549: 00 + 41554a: 74 15 je 415561 <_IO_no_init+0xa1> + 41554c: c7 00 00 00 00 00 movl $0x0,(%rax) + 415552: c7 40 04 00 00 00 00 movl $0x0,0x4(%rax) + 415559: 48 c7 40 08 00 00 00 movq $0x0,0x8(%rax) + 415560: 00 + 415561: 85 d2 test %edx,%edx + 415563: 89 97 c0 00 00 00 mov %edx,0xc0(%rdi) + 415569: 78 75 js 4155e0 <_IO_no_init+0x120> + 41556b: 48 89 8f a0 00 00 00 mov %rcx,0xa0(%rdi) + 415572: 48 c7 41 30 00 00 00 movq $0x0,0x30(%rcx) + 415579: 00 + 41557a: 48 c7 41 38 00 00 00 movq $0x0,0x38(%rcx) + 415581: 00 + 415582: 48 c7 41 10 00 00 00 movq $0x0,0x10(%rcx) + 415589: 00 + 41558a: 48 c7 01 00 00 00 00 movq $0x0,(%rcx) + 415591: 48 c7 41 08 00 00 00 movq $0x0,0x8(%rcx) + 415598: 00 + 415599: 48 c7 41 18 00 00 00 movq $0x0,0x18(%rcx) + 4155a0: 00 + 4155a1: 48 c7 41 20 00 00 00 movq $0x0,0x20(%rcx) + 4155a8: 00 + 4155a9: 48 c7 41 28 00 00 00 movq $0x0,0x28(%rcx) + 4155b0: 00 + 4155b1: 48 c7 41 40 00 00 00 movq $0x0,0x40(%rcx) + 4155b8: 00 + 4155b9: 48 c7 41 48 00 00 00 movq $0x0,0x48(%rcx) + 4155c0: 00 + 4155c1: 48 c7 41 50 00 00 00 movq $0x0,0x50(%rcx) + 4155c8: 00 + 4155c9: 4c 89 81 30 01 00 00 mov %r8,0x130(%rcx) + 4155d0: 48 c7 87 a8 00 00 00 movq $0x0,0xa8(%rdi) + 4155d7: 00 00 00 00 + 4155db: c3 retq + 4155dc: 0f 1f 40 00 nopl 0x0(%rax) + 4155e0: 48 c7 87 a0 00 00 00 movq $0xffffffffffffffff,0xa0(%rdi) + 4155e7: ff ff ff ff + 4155eb: 48 c7 87 a8 00 00 00 movq $0x0,0xa8(%rdi) + 4155f2: 00 00 00 00 + 4155f6: c3 retq + 4155f7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 4155fe: 00 00 + +0000000000415600 <_IO_default_sync>: + 415600: 31 c0 xor %eax,%eax + 415602: c3 retq + 415603: 0f 1f 00 nopl (%rax) + 415606: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41560d: 00 00 00 + +0000000000415610 <_IO_default_finish>: + 415610: 55 push %rbp + 415611: 53 push %rbx + 415612: 48 89 fb mov %rdi,%rbx + 415615: 48 83 ec 28 sub $0x28,%rsp + 415619: 48 8b 7f 38 mov 0x38(%rdi),%rdi + 41561d: 48 85 ff test %rdi,%rdi + 415620: 74 09 je 41562b <_IO_default_finish+0x1b> + 415622: f6 03 01 testb $0x1,(%rbx) + 415625: 0f 84 fd 01 00 00 je 415828 <_IO_default_finish+0x218> + 41562b: 48 8b 43 60 mov 0x60(%rbx),%rax + 41562f: 48 85 c0 test %rax,%rax + 415632: 74 14 je 415648 <_IO_default_finish+0x38> + 415634: 0f 1f 40 00 nopl 0x0(%rax) + 415638: 48 c7 40 08 00 00 00 movq $0x0,0x8(%rax) + 41563f: 00 + 415640: 48 8b 00 mov (%rax),%rax + 415643: 48 85 c0 test %rax,%rax + 415646: 75 f0 jne 415638 <_IO_default_finish+0x28> + 415648: 48 8b 7b 48 mov 0x48(%rbx),%rdi + 41564c: 48 85 ff test %rdi,%rdi + 41564f: 74 0d je 41565e <_IO_default_finish+0x4e> + 415651: e8 5a 87 00 00 callq 41ddb0 <__cfree> + 415656: 48 c7 43 48 00 00 00 movq $0x0,0x48(%rbx) + 41565d: 00 + 41565e: f6 03 80 testb $0x80,(%rbx) + 415661: 75 0d jne 415670 <_IO_default_finish+0x60> + 415663: 48 83 c4 28 add $0x28,%rsp + 415667: 5b pop %rbx + 415668: 5d pop %rbp + 415669: c3 retq + 41566a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 415670: bd 00 00 00 00 mov $0x0,%ebp + 415675: 48 85 ed test %rbp,%rbp + 415678: 0f 84 62 02 00 00 je 4158e0 <_IO_default_finish+0x2d0> + 41567e: 31 d2 xor %edx,%edx + 415680: be 50 41 41 00 mov $0x414150,%esi + 415685: 48 89 e7 mov %rsp,%rdi + 415688: e8 73 a9 be ff callq 0 <_nl_current_LC_CTYPE> + 41568d: 64 48 8b 14 25 10 00 mov %fs:0x10,%rdx + 415694: 00 00 + 415696: 48 3b 15 0b 6f 2b 00 cmp 0x2b6f0b(%rip),%rdx # 6cc5a8 + 41569d: 74 46 je 4156e5 <_IO_default_finish+0xd5> + 41569f: be 01 00 00 00 mov $0x1,%esi + 4156a4: 31 c0 xor %eax,%eax + 4156a6: 83 3d 0f 7b 2b 00 00 cmpl $0x0,0x2b7b0f(%rip) # 6cd1bc <__libc_multiple_threads> + 4156ad: 74 0c je 4156bb <_IO_default_finish+0xab> + 4156af: f0 0f b1 35 e9 6e 2b lock cmpxchg %esi,0x2b6ee9(%rip) # 6cc5a0 + 4156b6: 00 + 4156b7: 75 0b jne 4156c4 <_IO_default_finish+0xb4> + 4156b9: eb 23 jmp 4156de <_IO_default_finish+0xce> + 4156bb: 0f b1 35 de 6e 2b 00 cmpxchg %esi,0x2b6ede(%rip) # 6cc5a0 + 4156c2: 74 1a je 4156de <_IO_default_finish+0xce> + 4156c4: 48 8d 3d d5 6e 2b 00 lea 0x2b6ed5(%rip),%rdi # 6cc5a0 + 4156cb: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 4156d2: e8 f9 ce 02 00 callq 4425d0 <__lll_lock_wait_private> + 4156d7: 48 81 c4 80 00 00 00 add $0x80,%rsp + 4156de: 48 89 15 c3 6e 2b 00 mov %rdx,0x2b6ec3(%rip) # 6cc5a8 + 4156e5: 8b 33 mov (%rbx),%esi + 4156e7: 8b 15 b7 6e 2b 00 mov 0x2b6eb7(%rip),%edx # 6cc5a4 + 4156ed: 48 89 1d 9c 6e 2b 00 mov %rbx,0x2b6e9c(%rip) # 6cc590 + 4156f4: 89 f0 mov %esi,%eax + 4156f6: 83 c2 01 add $0x1,%edx + 4156f9: 25 00 80 00 00 and $0x8000,%eax + 4156fe: 89 15 a0 6e 2b 00 mov %edx,0x2b6ea0(%rip) # 6cc5a4 + 415704: 0f 84 3e 01 00 00 je 415848 <_IO_default_finish+0x238> + 41570a: 48 8b 3d af 49 2b 00 mov 0x2b49af(%rip),%rdi # 6ca0c0 <_IO_list_all> + 415711: 48 85 ff test %rdi,%rdi + 415714: 0f 84 f3 01 00 00 je 41590d <_IO_default_finish+0x2fd> + 41571a: 48 39 fb cmp %rdi,%rbx + 41571d: 0f 84 d3 01 00 00 je 4158f6 <_IO_default_finish+0x2e6> + 415723: 48 8b 4f 68 mov 0x68(%rdi),%rcx + 415727: 48 85 c9 test %rcx,%rcx + 41572a: 74 29 je 415755 <_IO_default_finish+0x145> + 41572c: 48 39 cb cmp %rcx,%rbx + 41572f: 75 1b jne 41574c <_IO_default_finish+0x13c> + 415731: e9 e2 01 00 00 jmpq 415918 <_IO_default_finish+0x308> + 415736: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41573d: 00 00 00 + 415740: 48 39 d3 cmp %rdx,%rbx + 415743: 0f 84 77 01 00 00 je 4158c0 <_IO_default_finish+0x2b0> + 415749: 48 89 d1 mov %rdx,%rcx + 41574c: 48 8b 51 68 mov 0x68(%rcx),%rdx + 415750: 48 85 d2 test %rdx,%rdx + 415753: 75 eb jne 415740 <_IO_default_finish+0x130> + 415755: 40 80 e6 7f and $0x7f,%sil + 415759: 85 c0 test %eax,%eax + 41575b: 89 33 mov %esi,(%rbx) + 41575d: 75 4c jne 4157ab <_IO_default_finish+0x19b> + 41575f: 48 8b b3 88 00 00 00 mov 0x88(%rbx),%rsi + 415766: 8b 46 04 mov 0x4(%rsi),%eax + 415769: 83 e8 01 sub $0x1,%eax + 41576c: 85 c0 test %eax,%eax + 41576e: 89 46 04 mov %eax,0x4(%rsi) + 415771: 8b 15 2d 6e 2b 00 mov 0x2b6e2d(%rip),%edx # 6cc5a4 + 415777: 75 38 jne 4157b1 <_IO_default_finish+0x1a1> + 415779: 48 c7 46 08 00 00 00 movq $0x0,0x8(%rsi) + 415780: 00 + 415781: 83 3d 34 7a 2b 00 00 cmpl $0x0,0x2b7a34(%rip) # 6cd1bc <__libc_multiple_threads> + 415788: 74 07 je 415791 <_IO_default_finish+0x181> + 41578a: f0 ff 0e lock decl (%rsi) + 41578d: 75 06 jne 415795 <_IO_default_finish+0x185> + 41578f: eb 1a jmp 4157ab <_IO_default_finish+0x19b> + 415791: ff 0e decl (%rsi) + 415793: 74 16 je 4157ab <_IO_default_finish+0x19b> + 415795: 48 8d 3e lea (%rsi),%rdi + 415798: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41579f: e8 5c ce 02 00 callq 442600 <__lll_unlock_wake_private> + 4157a4: 48 81 c4 80 00 00 00 add $0x80,%rsp + 4157ab: 8b 15 f3 6d 2b 00 mov 0x2b6df3(%rip),%edx # 6cc5a4 + 4157b1: 83 ea 01 sub $0x1,%edx + 4157b4: 48 c7 05 d1 6d 2b 00 movq $0x0,0x2b6dd1(%rip) # 6cc590 + 4157bb: 00 00 00 00 + 4157bf: 85 d2 test %edx,%edx + 4157c1: 89 15 dd 6d 2b 00 mov %edx,0x2b6ddd(%rip) # 6cc5a4 + 4157c7: 75 41 jne 41580a <_IO_default_finish+0x1fa> + 4157c9: 48 c7 05 d4 6d 2b 00 movq $0x0,0x2b6dd4(%rip) # 6cc5a8 + 4157d0: 00 00 00 00 + 4157d4: 83 3d e1 79 2b 00 00 cmpl $0x0,0x2b79e1(%rip) # 6cd1bc <__libc_multiple_threads> + 4157db: 74 0b je 4157e8 <_IO_default_finish+0x1d8> + 4157dd: f0 ff 0d bc 6d 2b 00 lock decl 0x2b6dbc(%rip) # 6cc5a0 + 4157e4: 75 0a jne 4157f0 <_IO_default_finish+0x1e0> + 4157e6: eb 22 jmp 41580a <_IO_default_finish+0x1fa> + 4157e8: ff 0d b2 6d 2b 00 decl 0x2b6db2(%rip) # 6cc5a0 + 4157ee: 74 1a je 41580a <_IO_default_finish+0x1fa> + 4157f0: 48 8d 3d a9 6d 2b 00 lea 0x2b6da9(%rip),%rdi # 6cc5a0 + 4157f7: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 4157fe: e8 fd cd 02 00 callq 442600 <__lll_unlock_wake_private> + 415803: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41580a: 48 85 ed test %rbp,%rbp + 41580d: 0f 84 50 fe ff ff je 415663 <_IO_default_finish+0x53> + 415813: 48 89 e7 mov %rsp,%rdi + 415816: 31 f6 xor %esi,%esi + 415818: e8 e3 a7 be ff callq 0 <_nl_current_LC_CTYPE> + 41581d: 48 83 c4 28 add $0x28,%rsp + 415821: 5b pop %rbx + 415822: 5d pop %rbp + 415823: c3 retq + 415824: 0f 1f 40 00 nopl 0x0(%rax) + 415828: e8 83 85 00 00 callq 41ddb0 <__cfree> + 41582d: 48 c7 43 40 00 00 00 movq $0x0,0x40(%rbx) + 415834: 00 + 415835: 48 c7 43 38 00 00 00 movq $0x0,0x38(%rbx) + 41583c: 00 + 41583d: e9 e9 fd ff ff jmpq 41562b <_IO_default_finish+0x1b> + 415842: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 415848: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx + 41584f: 64 4c 8b 04 25 10 00 mov %fs:0x10,%r8 + 415856: 00 00 + 415858: 4c 3b 42 08 cmp 0x8(%rdx),%r8 + 41585c: 74 3c je 41589a <_IO_default_finish+0x28a> + 41585e: be 01 00 00 00 mov $0x1,%esi + 415863: 83 3d 52 79 2b 00 00 cmpl $0x0,0x2b7952(%rip) # 6cd1bc <__libc_multiple_threads> + 41586a: 74 08 je 415874 <_IO_default_finish+0x264> + 41586c: f0 0f b1 32 lock cmpxchg %esi,(%rdx) + 415870: 75 07 jne 415879 <_IO_default_finish+0x269> + 415872: eb 1b jmp 41588f <_IO_default_finish+0x27f> + 415874: 0f b1 32 cmpxchg %esi,(%rdx) + 415877: 74 16 je 41588f <_IO_default_finish+0x27f> + 415879: 48 8d 3a lea (%rdx),%rdi + 41587c: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 415883: e8 48 cd 02 00 callq 4425d0 <__lll_lock_wait_private> + 415888: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41588f: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx + 415896: 4c 89 42 08 mov %r8,0x8(%rdx) + 41589a: 8b 33 mov (%rbx),%esi + 41589c: 48 8b 3d 1d 48 2b 00 mov 0x2b481d(%rip),%rdi # 6ca0c0 <_IO_list_all> + 4158a3: 83 42 04 01 addl $0x1,0x4(%rdx) + 4158a7: 89 f0 mov %esi,%eax + 4158a9: 25 00 80 00 00 and $0x8000,%eax + 4158ae: 48 85 ff test %rdi,%rdi + 4158b1: 0f 85 63 fe ff ff jne 41571a <_IO_default_finish+0x10a> + 4158b7: e9 99 fe ff ff jmpq 415755 <_IO_default_finish+0x145> + 4158bc: 0f 1f 40 00 nopl 0x0(%rax) + 4158c0: 48 83 c1 68 add $0x68,%rcx + 4158c4: 48 8b 53 68 mov 0x68(%rbx),%rdx + 4158c8: 83 05 c9 6c 2b 00 01 addl $0x1,0x2b6cc9(%rip) # 6cc598 <_IO_list_all_stamp> + 4158cf: 48 89 11 mov %rdx,(%rcx) + 4158d2: e9 7e fe ff ff jmpq 415755 <_IO_default_finish+0x145> + 4158d7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 4158de: 00 00 + 4158e0: 48 c7 04 24 50 41 41 movq $0x414150,(%rsp) + 4158e7: 00 + 4158e8: 48 c7 44 24 08 00 00 movq $0x0,0x8(%rsp) + 4158ef: 00 00 + 4158f1: e9 97 fd ff ff jmpq 41568d <_IO_default_finish+0x7d> + 4158f6: 48 8b 53 68 mov 0x68(%rbx),%rdx + 4158fa: 83 05 97 6c 2b 00 01 addl $0x1,0x2b6c97(%rip) # 6cc598 <_IO_list_all_stamp> + 415901: 48 89 15 b8 47 2b 00 mov %rdx,0x2b47b8(%rip) # 6ca0c0 <_IO_list_all> + 415908: e9 48 fe ff ff jmpq 415755 <_IO_default_finish+0x145> + 41590d: 40 80 e6 7f and $0x7f,%sil + 415911: 89 33 mov %esi,(%rbx) + 415913: e9 99 fe ff ff jmpq 4157b1 <_IO_default_finish+0x1a1> + 415918: 48 8d 4f 68 lea 0x68(%rdi),%rcx + 41591c: eb a6 jmp 4158c4 <_IO_default_finish+0x2b4> + 41591e: 66 90 xchg %ax,%ax + +0000000000415920 <_IO_default_seekoff>: + 415920: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax + 415927: c3 retq + 415928: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 41592f: 00 + +0000000000415930 <_IO_sputbackc>: + 415930: 53 push %rbx + 415931: 48 8b 57 08 mov 0x8(%rdi),%rdx + 415935: 48 89 fb mov %rdi,%rbx + 415938: 48 3b 57 18 cmp 0x18(%rdi),%rdx + 41593c: 76 0c jbe 41594a <_IO_sputbackc+0x1a> + 41593e: 0f b6 42 ff movzbl -0x1(%rdx),%eax + 415942: 40 0f b6 ce movzbl %sil,%ecx + 415946: 39 c8 cmp %ecx,%eax + 415948: 74 1e je 415968 <_IO_sputbackc+0x38> + 41594a: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 415951: 48 89 df mov %rbx,%rdi + 415954: ff 50 30 callq *0x30(%rax) + 415957: 83 f8 ff cmp $0xffffffff,%eax + 41595a: 74 03 je 41595f <_IO_sputbackc+0x2f> + 41595c: 83 23 ef andl $0xffffffef,(%rbx) + 41595f: 5b pop %rbx + 415960: c3 retq + 415961: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 415968: 48 83 ea 01 sub $0x1,%rdx + 41596c: 48 89 57 08 mov %rdx,0x8(%rdi) + 415970: eb ea jmp 41595c <_IO_sputbackc+0x2c> + 415972: 0f 1f 40 00 nopl 0x0(%rax) + 415976: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41597d: 00 00 00 + +0000000000415980 <_IO_sungetc>: + 415980: 48 8b 47 08 mov 0x8(%rdi),%rax + 415984: 48 3b 47 18 cmp 0x18(%rdi),%rax + 415988: 53 push %rbx + 415989: 48 89 fb mov %rdi,%rbx + 41598c: 76 12 jbe 4159a0 <_IO_sungetc+0x20> + 41598e: 48 8d 50 ff lea -0x1(%rax),%rdx + 415992: 48 89 57 08 mov %rdx,0x8(%rdi) + 415996: 0f b6 40 ff movzbl -0x1(%rax),%eax + 41599a: 83 23 ef andl $0xffffffef,(%rbx) + 41599d: 5b pop %rbx + 41599e: c3 retq + 41599f: 90 nop + 4159a0: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax + 4159a7: be ff ff ff ff mov $0xffffffff,%esi + 4159ac: ff 50 30 callq *0x30(%rax) + 4159af: 83 f8 ff cmp $0xffffffff,%eax + 4159b2: 75 e6 jne 41599a <_IO_sungetc+0x1a> + 4159b4: 5b pop %rbx + 4159b5: c3 retq + 4159b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4159bd: 00 00 00 + +00000000004159c0 <_IO_adjust_column>: + 4159c0: 4c 63 c2 movslq %edx,%r8 + 4159c3: 49 01 f0 add %rsi,%r8 + 4159c6: 4c 39 c6 cmp %r8,%rsi + 4159c9: 73 23 jae 4159ee <_IO_adjust_column+0x2e> + 4159cb: 41 80 78 ff 0a cmpb $0xa,-0x1(%r8) + 4159d0: 49 8d 48 ff lea -0x1(%r8),%rcx + 4159d4: 75 13 jne 4159e9 <_IO_adjust_column+0x29> + 4159d6: eb 20 jmp 4159f8 <_IO_adjust_column+0x38> + 4159d8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 4159df: 00 + 4159e0: 48 83 e9 01 sub $0x1,%rcx + 4159e4: 80 39 0a cmpb $0xa,(%rcx) + 4159e7: 74 0f je 4159f8 <_IO_adjust_column+0x38> + 4159e9: 48 39 ce cmp %rcx,%rsi + 4159ec: 75 f2 jne 4159e0 <_IO_adjust_column+0x20> + 4159ee: 8d 04 3a lea (%rdx,%rdi,1),%eax + 4159f1: c3 retq + 4159f2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4159f8: 49 29 c8 sub %rcx,%r8 + 4159fb: 41 8d 40 ff lea -0x1(%r8),%eax + 4159ff: c3 retq + +0000000000415a00 <_IO_flush_all_lockp>: + 415a00: 41 57 push %r15 + 415a02: 41 56 push %r14 + 415a04: 41 89 fe mov %edi,%r14d + 415a07: 41 55 push %r13 + 415a09: 41 54 push %r12 + 415a0b: 55 push %rbp + 415a0c: 53 push %rbx + 415a0d: 48 83 ec 28 sub $0x28,%rsp + 415a11: 85 ff test %edi,%edi + 415a13: 0f 84 17 02 00 00 je 415c30 <_IO_flush_all_lockp+0x230> + 415a19: b8 00 00 00 00 mov $0x0,%eax + 415a1e: 45 31 ed xor %r13d,%r13d + 415a21: 48 85 c0 test %rax,%rax + 415a24: 41 0f 95 c5 setne %r13b + 415a28: 0f 84 82 02 00 00 je 415cb0 <_IO_flush_all_lockp+0x2b0> + 415a2e: 31 d2 xor %edx,%edx + 415a30: be 50 41 41 00 mov $0x414150,%esi + 415a35: 48 89 e7 mov %rsp,%rdi + 415a38: e8 c3 a5 be ff callq 0 <_nl_current_LC_CTYPE> + 415a3d: 64 48 8b 14 25 10 00 mov %fs:0x10,%rdx + 415a44: 00 00 + 415a46: 48 3b 15 5b 6b 2b 00 cmp 0x2b6b5b(%rip),%rdx # 6cc5a8 + 415a4d: 74 46 je 415a95 <_IO_flush_all_lockp+0x95> + 415a4f: be 01 00 00 00 mov $0x1,%esi + 415a54: 31 c0 xor %eax,%eax + 415a56: 83 3d 5f 77 2b 00 00 cmpl $0x0,0x2b775f(%rip) # 6cd1bc <__libc_multiple_threads> + 415a5d: 74 0c je 415a6b <_IO_flush_all_lockp+0x6b> + 415a5f: f0 0f b1 35 39 6b 2b lock cmpxchg %esi,0x2b6b39(%rip) # 6cc5a0 + 415a66: 00 + 415a67: 75 0b jne 415a74 <_IO_flush_all_lockp+0x74> + 415a69: eb 23 jmp 415a8e <_IO_flush_all_lockp+0x8e> + 415a6b: 0f b1 35 2e 6b 2b 00 cmpxchg %esi,0x2b6b2e(%rip) # 6cc5a0 + 415a72: 74 1a je 415a8e <_IO_flush_all_lockp+0x8e> + 415a74: 48 8d 3d 25 6b 2b 00 lea 0x2b6b25(%rip),%rdi # 6cc5a0 + 415a7b: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 415a82: e8 49 cb 02 00 callq 4425d0 <__lll_lock_wait_private> + 415a87: 48 81 c4 80 00 00 00 add $0x80,%rsp + 415a8e: 48 89 15 13 6b 2b 00 mov %rdx,0x2b6b13(%rip) # 6cc5a8 + 415a95: 8b 05 09 6b 2b 00 mov 0x2b6b09(%rip),%eax # 6cc5a4 + 415a9b: 48 8b 1d 1e 46 2b 00 mov 0x2b461e(%rip),%rbx # 6ca0c0 <_IO_list_all> + 415aa2: 44 8b 3d ef 6a 2b 00 mov 0x2b6aef(%rip),%r15d # 6cc598 <_IO_list_all_stamp> + 415aa9: 83 c0 01 add $0x1,%eax + 415aac: 48 85 db test %rbx,%rbx + 415aaf: 89 05 ef 6a 2b 00 mov %eax,0x2b6aef(%rip) # 6cc5a4 + 415ab5: 0f 84 0b 02 00 00 je 415cc6 <_IO_flush_all_lockp+0x2c6> + 415abb: 31 ed xor %ebp,%ebp + 415abd: 64 4c 8b 24 25 10 00 mov %fs:0x10,%r12 + 415ac4: 00 00 + 415ac6: eb 1b jmp 415ae3 <_IO_flush_all_lockp+0xe3> + 415ac8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 415acf: 00 + 415ad0: 48 8b 1d e9 45 2b 00 mov 0x2b45e9(%rip),%rbx # 6ca0c0 <_IO_list_all> + 415ad7: 41 89 c7 mov %eax,%r15d + 415ada: 48 85 db test %rbx,%rbx + 415add: 0f 84 14 01 00 00 je 415bf7 <_IO_flush_all_lockp+0x1f7> + 415ae3: 45 85 f6 test %r14d,%r14d + 415ae6: 48 89 1d a3 6a 2b 00 mov %rbx,0x2b6aa3(%rip) # 6cc590 + 415aed: 74 56 je 415b45 <_IO_flush_all_lockp+0x145> + 415aef: 8b 03 mov (%rbx),%eax + 415af1: 25 00 80 00 00 and $0x8000,%eax + 415af6: 75 4d jne 415b45 <_IO_flush_all_lockp+0x145> + 415af8: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx + 415aff: 4c 3b 62 08 cmp 0x8(%rdx),%r12 + 415b03: 74 3c je 415b41 <_IO_flush_all_lockp+0x141> + 415b05: be 01 00 00 00 mov $0x1,%esi + 415b0a: 83 3d ab 76 2b 00 00 cmpl $0x0,0x2b76ab(%rip) # 6cd1bc <__libc_multiple_threads> + 415b11: 74 08 je 415b1b <_IO_flush_all_lockp+0x11b> + 415b13: f0 0f b1 32 lock cmpxchg %esi,(%rdx) + 415b17: 75 07 jne 415b20 <_IO_flush_all_lockp+0x120> + 415b19: eb 1b jmp 415b36 <_IO_flush_all_lockp+0x136> + 415b1b: 0f b1 32 cmpxchg %esi,(%rdx) + 415b1e: 74 16 je 415b36 <_IO_flush_all_lockp+0x136> + 415b20: 48 8d 3a lea (%rdx),%rdi + 415b23: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 415b2a: e8 a1 ca 02 00 callq 4425d0 <__lll_lock_wait_private> + 415b2f: 48 81 c4 80 00 00 00 add $0x80,%rsp + 415b36: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx + 415b3d: 4c 89 62 08 mov %r12,0x8(%rdx) + 415b41: 83 42 04 01 addl $0x1,0x4(%rdx) + 415b45: 8b 83 c0 00 00 00 mov 0xc0(%rbx),%eax + 415b4b: 85 c0 test %eax,%eax + 415b4d: 0f 8e fd 00 00 00 jle 415c50 <_IO_flush_all_lockp+0x250> + 415b53: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 415b5a: 48 8b 48 18 mov 0x18(%rax),%rcx + 415b5e: 48 39 48 20 cmp %rcx,0x20(%rax) + 415b62: 76 1d jbe 415b81 <_IO_flush_all_lockp+0x181> + 415b64: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 415b6b: be ff ff ff ff mov $0xffffffff,%esi + 415b70: 48 89 df mov %rbx,%rdi + 415b73: ff 50 18 callq *0x18(%rax) + 415b76: 83 f8 ff cmp $0xffffffff,%eax + 415b79: b8 ff ff ff ff mov $0xffffffff,%eax + 415b7e: 0f 44 e8 cmove %eax,%ebp + 415b81: 45 85 f6 test %r14d,%r14d + 415b84: 74 4a je 415bd0 <_IO_flush_all_lockp+0x1d0> + 415b86: f7 03 00 80 00 00 testl $0x8000,(%rbx) + 415b8c: 75 42 jne 415bd0 <_IO_flush_all_lockp+0x1d0> + 415b8e: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx + 415b95: 83 6a 04 01 subl $0x1,0x4(%rdx) + 415b99: 75 35 jne 415bd0 <_IO_flush_all_lockp+0x1d0> + 415b9b: 48 c7 42 08 00 00 00 movq $0x0,0x8(%rdx) + 415ba2: 00 + 415ba3: 83 3d 12 76 2b 00 00 cmpl $0x0,0x2b7612(%rip) # 6cd1bc <__libc_multiple_threads> + 415baa: 74 07 je 415bb3 <_IO_flush_all_lockp+0x1b3> + 415bac: f0 ff 0a lock decl (%rdx) + 415baf: 75 06 jne 415bb7 <_IO_flush_all_lockp+0x1b7> + 415bb1: eb 1a jmp 415bcd <_IO_flush_all_lockp+0x1cd> + 415bb3: ff 0a decl (%rdx) + 415bb5: 74 16 je 415bcd <_IO_flush_all_lockp+0x1cd> + 415bb7: 48 8d 3a lea (%rdx),%rdi + 415bba: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 415bc1: e8 3a ca 02 00 callq 442600 <__lll_unlock_wake_private> + 415bc6: 48 81 c4 80 00 00 00 add $0x80,%rsp + 415bcd: 0f 1f 00 nopl (%rax) + 415bd0: 8b 05 c2 69 2b 00 mov 0x2b69c2(%rip),%eax # 6cc598 <_IO_list_all_stamp> + 415bd6: 48 c7 05 af 69 2b 00 movq $0x0,0x2b69af(%rip) # 6cc590 + 415bdd: 00 00 00 00 + 415be1: 41 39 c7 cmp %eax,%r15d + 415be4: 0f 85 e6 fe ff ff jne 415ad0 <_IO_flush_all_lockp+0xd0> + 415bea: 48 8b 5b 68 mov 0x68(%rbx),%rbx + 415bee: 48 85 db test %rbx,%rbx + 415bf1: 0f 85 ec fe ff ff jne 415ae3 <_IO_flush_all_lockp+0xe3> + 415bf7: 45 85 f6 test %r14d,%r14d + 415bfa: 8b 05 a4 69 2b 00 mov 0x2b69a4(%rip),%eax # 6cc5a4 + 415c00: 74 0d je 415c0f <_IO_flush_all_lockp+0x20f> + 415c02: 83 e8 01 sub $0x1,%eax + 415c05: 85 c0 test %eax,%eax + 415c07: 89 05 97 69 2b 00 mov %eax,0x2b6997(%rip) # 6cc5a4 + 415c0d: 74 59 je 415c68 <_IO_flush_all_lockp+0x268> + 415c0f: 45 85 ed test %r13d,%r13d + 415c12: 74 0a je 415c1e <_IO_flush_all_lockp+0x21e> + 415c14: 31 f6 xor %esi,%esi + 415c16: 48 89 e7 mov %rsp,%rdi + 415c19: e8 e2 a3 be ff callq 0 <_nl_current_LC_CTYPE> + 415c1e: 48 83 c4 28 add $0x28,%rsp + 415c22: 89 e8 mov %ebp,%eax + 415c24: 5b pop %rbx + 415c25: 5d pop %rbp + 415c26: 41 5c pop %r12 + 415c28: 41 5d pop %r13 + 415c2a: 41 5e pop %r14 + 415c2c: 41 5f pop %r15 + 415c2e: c3 retq + 415c2f: 90 nop + 415c30: 48 8b 1d 89 44 2b 00 mov 0x2b4489(%rip),%rbx # 6ca0c0 <_IO_list_all> + 415c37: 45 31 ed xor %r13d,%r13d + 415c3a: 44 8b 3d 57 69 2b 00 mov 0x2b6957(%rip),%r15d # 6cc598 <_IO_list_all_stamp> + 415c41: 48 85 db test %rbx,%rbx + 415c44: 0f 85 71 fe ff ff jne 415abb <_IO_flush_all_lockp+0xbb> + 415c4a: 31 ed xor %ebp,%ebp + 415c4c: eb d0 jmp 415c1e <_IO_flush_all_lockp+0x21e> + 415c4e: 66 90 xchg %ax,%ax + 415c50: 48 8b 43 20 mov 0x20(%rbx),%rax + 415c54: 48 39 43 28 cmp %rax,0x28(%rbx) + 415c58: 0f 87 06 ff ff ff ja 415b64 <_IO_flush_all_lockp+0x164> + 415c5e: e9 1e ff ff ff jmpq 415b81 <_IO_flush_all_lockp+0x181> + 415c63: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 415c68: 48 c7 05 35 69 2b 00 movq $0x0,0x2b6935(%rip) # 6cc5a8 + 415c6f: 00 00 00 00 + 415c73: 83 3d 42 75 2b 00 00 cmpl $0x0,0x2b7542(%rip) # 6cd1bc <__libc_multiple_threads> + 415c7a: 74 0b je 415c87 <_IO_flush_all_lockp+0x287> + 415c7c: f0 ff 0d 1d 69 2b 00 lock decl 0x2b691d(%rip) # 6cc5a0 + 415c83: 75 0a jne 415c8f <_IO_flush_all_lockp+0x28f> + 415c85: eb 22 jmp 415ca9 <_IO_flush_all_lockp+0x2a9> + 415c87: ff 0d 13 69 2b 00 decl 0x2b6913(%rip) # 6cc5a0 + 415c8d: 74 1a je 415ca9 <_IO_flush_all_lockp+0x2a9> + 415c8f: 48 8d 3d 0a 69 2b 00 lea 0x2b690a(%rip),%rdi # 6cc5a0 + 415c96: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 415c9d: e8 5e c9 02 00 callq 442600 <__lll_unlock_wake_private> + 415ca2: 48 81 c4 80 00 00 00 add $0x80,%rsp + 415ca9: e9 61 ff ff ff jmpq 415c0f <_IO_flush_all_lockp+0x20f> + 415cae: 66 90 xchg %ax,%ax + 415cb0: 48 c7 04 24 50 41 41 movq $0x414150,(%rsp) + 415cb7: 00 + 415cb8: 48 c7 44 24 08 00 00 movq $0x0,0x8(%rsp) + 415cbf: 00 00 + 415cc1: e9 77 fd ff ff jmpq 415a3d <_IO_flush_all_lockp+0x3d> + 415cc6: 31 ed xor %ebp,%ebp + 415cc8: e9 35 ff ff ff jmpq 415c02 <_IO_flush_all_lockp+0x202> + 415ccd: 0f 1f 00 nopl (%rax) + +0000000000415cd0 <_IO_flush_all>: + 415cd0: 41 56 push %r14 + 415cd2: 41 55 push %r13 + 415cd4: 41 54 push %r12 + 415cd6: 55 push %rbp + 415cd7: 41 bc 00 00 00 00 mov $0x0,%r12d + 415cdd: 53 push %rbx + 415cde: 48 83 ec 20 sub $0x20,%rsp + 415ce2: 4d 85 e4 test %r12,%r12 + 415ce5: 0f 84 45 02 00 00 je 415f30 <_IO_flush_all+0x260> + 415ceb: 31 d2 xor %edx,%edx + 415ced: be 50 41 41 00 mov $0x414150,%esi + 415cf2: 48 89 e7 mov %rsp,%rdi + 415cf5: e8 06 a3 be ff callq 0 <_nl_current_LC_CTYPE> + 415cfa: 64 48 8b 14 25 10 00 mov %fs:0x10,%rdx + 415d01: 00 00 + 415d03: 48 3b 15 9e 68 2b 00 cmp 0x2b689e(%rip),%rdx # 6cc5a8 + 415d0a: 74 46 je 415d52 <_IO_flush_all+0x82> + 415d0c: be 01 00 00 00 mov $0x1,%esi + 415d11: 31 c0 xor %eax,%eax + 415d13: 83 3d a2 74 2b 00 00 cmpl $0x0,0x2b74a2(%rip) # 6cd1bc <__libc_multiple_threads> + 415d1a: 74 0c je 415d28 <_IO_flush_all+0x58> + 415d1c: f0 0f b1 35 7c 68 2b lock cmpxchg %esi,0x2b687c(%rip) # 6cc5a0 + 415d23: 00 + 415d24: 75 0b jne 415d31 <_IO_flush_all+0x61> + 415d26: eb 23 jmp 415d4b <_IO_flush_all+0x7b> + 415d28: 0f b1 35 71 68 2b 00 cmpxchg %esi,0x2b6871(%rip) # 6cc5a0 + 415d2f: 74 1a je 415d4b <_IO_flush_all+0x7b> + 415d31: 48 8d 3d 68 68 2b 00 lea 0x2b6868(%rip),%rdi # 6cc5a0 + 415d38: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 415d3f: e8 8c c8 02 00 callq 4425d0 <__lll_lock_wait_private> + 415d44: 48 81 c4 80 00 00 00 add $0x80,%rsp + 415d4b: 48 89 15 56 68 2b 00 mov %rdx,0x2b6856(%rip) # 6cc5a8 + 415d52: 8b 05 4c 68 2b 00 mov 0x2b684c(%rip),%eax # 6cc5a4 + 415d58: 48 8b 1d 61 43 2b 00 mov 0x2b4361(%rip),%rbx # 6ca0c0 <_IO_list_all> + 415d5f: 31 ed xor %ebp,%ebp + 415d61: 44 8b 2d 30 68 2b 00 mov 0x2b6830(%rip),%r13d # 6cc598 <_IO_list_all_stamp> + 415d68: 83 c0 01 add $0x1,%eax + 415d6b: 48 85 db test %rbx,%rbx + 415d6e: 89 05 30 68 2b 00 mov %eax,0x2b6830(%rip) # 6cc5a4 + 415d74: 0f 84 2e 01 00 00 je 415ea8 <_IO_flush_all+0x1d8> + 415d7a: 64 4c 8b 34 25 10 00 mov %fs:0x10,%r14 + 415d81: 00 00 + 415d83: eb 16 jmp 415d9b <_IO_flush_all+0xcb> + 415d85: 0f 1f 00 nopl (%rax) + 415d88: 48 8b 1d 31 43 2b 00 mov 0x2b4331(%rip),%rbx # 6ca0c0 <_IO_list_all> + 415d8f: 48 85 db test %rbx,%rbx + 415d92: 0f 84 0a 01 00 00 je 415ea2 <_IO_flush_all+0x1d2> + 415d98: 41 89 c5 mov %eax,%r13d + 415d9b: 8b 03 mov (%rbx),%eax + 415d9d: 48 89 1d ec 67 2b 00 mov %rbx,0x2b67ec(%rip) # 6cc590 + 415da4: 25 00 80 00 00 and $0x8000,%eax + 415da9: 75 4d jne 415df8 <_IO_flush_all+0x128> + 415dab: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx + 415db2: 4c 3b 72 08 cmp 0x8(%rdx),%r14 + 415db6: 74 3c je 415df4 <_IO_flush_all+0x124> + 415db8: be 01 00 00 00 mov $0x1,%esi + 415dbd: 83 3d f8 73 2b 00 00 cmpl $0x0,0x2b73f8(%rip) # 6cd1bc <__libc_multiple_threads> + 415dc4: 74 08 je 415dce <_IO_flush_all+0xfe> + 415dc6: f0 0f b1 32 lock cmpxchg %esi,(%rdx) + 415dca: 75 07 jne 415dd3 <_IO_flush_all+0x103> + 415dcc: eb 1b jmp 415de9 <_IO_flush_all+0x119> + 415dce: 0f b1 32 cmpxchg %esi,(%rdx) + 415dd1: 74 16 je 415de9 <_IO_flush_all+0x119> + 415dd3: 48 8d 3a lea (%rdx),%rdi + 415dd6: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 415ddd: e8 ee c7 02 00 callq 4425d0 <__lll_lock_wait_private> + 415de2: 48 81 c4 80 00 00 00 add $0x80,%rsp + 415de9: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx + 415df0: 4c 89 72 08 mov %r14,0x8(%rdx) + 415df4: 83 42 04 01 addl $0x1,0x4(%rdx) + 415df8: 8b 83 c0 00 00 00 mov 0xc0(%rbx),%eax + 415dfe: 85 c0 test %eax,%eax + 415e00: 0f 8e 12 01 00 00 jle 415f18 <_IO_flush_all+0x248> + 415e06: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax + 415e0d: 48 8b 48 18 mov 0x18(%rax),%rcx + 415e11: 48 39 48 20 cmp %rcx,0x20(%rax) + 415e15: 76 1d jbe 415e34 <_IO_flush_all+0x164> + 415e17: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 415e1e: be ff ff ff ff mov $0xffffffff,%esi + 415e23: 48 89 df mov %rbx,%rdi + 415e26: ff 50 18 callq *0x18(%rax) + 415e29: 83 f8 ff cmp $0xffffffff,%eax + 415e2c: b8 ff ff ff ff mov $0xffffffff,%eax + 415e31: 0f 44 e8 cmove %eax,%ebp + 415e34: f7 03 00 80 00 00 testl $0x8000,(%rbx) + 415e3a: 75 3f jne 415e7b <_IO_flush_all+0x1ab> + 415e3c: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx + 415e43: 83 6a 04 01 subl $0x1,0x4(%rdx) + 415e47: 75 32 jne 415e7b <_IO_flush_all+0x1ab> + 415e49: 48 c7 42 08 00 00 00 movq $0x0,0x8(%rdx) + 415e50: 00 + 415e51: 83 3d 64 73 2b 00 00 cmpl $0x0,0x2b7364(%rip) # 6cd1bc <__libc_multiple_threads> + 415e58: 74 07 je 415e61 <_IO_flush_all+0x191> + 415e5a: f0 ff 0a lock decl (%rdx) + 415e5d: 75 06 jne 415e65 <_IO_flush_all+0x195> + 415e5f: eb 1a jmp 415e7b <_IO_flush_all+0x1ab> + 415e61: ff 0a decl (%rdx) + 415e63: 74 16 je 415e7b <_IO_flush_all+0x1ab> + 415e65: 48 8d 3a lea (%rdx),%rdi + 415e68: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 415e6f: e8 8c c7 02 00 callq 442600 <__lll_unlock_wake_private> + 415e74: 48 81 c4 80 00 00 00 add $0x80,%rsp + 415e7b: 8b 05 17 67 2b 00 mov 0x2b6717(%rip),%eax # 6cc598 <_IO_list_all_stamp> + 415e81: 48 c7 05 04 67 2b 00 movq $0x0,0x2b6704(%rip) # 6cc590 + 415e88: 00 00 00 00 + 415e8c: 44 39 e8 cmp %r13d,%eax + 415e8f: 0f 85 f3 fe ff ff jne 415d88 <_IO_flush_all+0xb8> + 415e95: 48 8b 5b 68 mov 0x68(%rbx),%rbx + 415e99: 48 85 db test %rbx,%rbx + 415e9c: 0f 85 f6 fe ff ff jne 415d98 <_IO_flush_all+0xc8> + 415ea2: 8b 05 fc 66 2b 00 mov 0x2b66fc(%rip),%eax # 6cc5a4 + 415ea8: 83 e8 01 sub $0x1,%eax + 415eab: 85 c0 test %eax,%eax + 415ead: 89 05 f1 66 2b 00 mov %eax,0x2b66f1(%rip) # 6cc5a4 + 415eb3: 75 41 jne 415ef6 <_IO_flush_all+0x226> + 415eb5: 48 c7 05 e8 66 2b 00 movq $0x0,0x2b66e8(%rip) # 6cc5a8 + 415ebc: 00 00 00 00 + 415ec0: 83 3d f5 72 2b 00 00 cmpl $0x0,0x2b72f5(%rip) # 6cd1bc <__libc_multiple_threads> + 415ec7: 74 0b je 415ed4 <_IO_flush_all+0x204> + 415ec9: f0 ff 0d d0 66 2b 00 lock decl 0x2b66d0(%rip) # 6cc5a0 + 415ed0: 75 0a jne 415edc <_IO_flush_all+0x20c> + 415ed2: eb 22 jmp 415ef6 <_IO_flush_all+0x226> + 415ed4: ff 0d c6 66 2b 00 decl 0x2b66c6(%rip) # 6cc5a0 + 415eda: 74 1a je 415ef6 <_IO_flush_all+0x226> + 415edc: 48 8d 3d bd 66 2b 00 lea 0x2b66bd(%rip),%rdi # 6cc5a0 + 415ee3: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 415eea: e8 11 c7 02 00 callq 442600 <__lll_unlock_wake_private> + 415eef: 48 81 c4 80 00 00 00 add $0x80,%rsp + 415ef6: 4d 85 e4 test %r12,%r12 + 415ef9: 74 0a je 415f05 <_IO_flush_all+0x235> + 415efb: 31 f6 xor %esi,%esi + 415efd: 48 89 e7 mov %rsp,%rdi + 415f00: e8 fb a0 be ff callq 0 <_nl_current_LC_CTYPE> + 415f05: 48 83 c4 20 add $0x20,%rsp + 415f09: 89 e8 mov %ebp,%eax + 415f0b: 5b pop %rbx + 415f0c: 5d pop %rbp + 415f0d: 41 5c pop %r12 + 415f0f: 41 5d pop %r13 + 415f11: 41 5e pop %r14 + 415f13: c3 retq + 415f14: 0f 1f 40 00 nopl 0x0(%rax) + 415f18: 48 8b 43 20 mov 0x20(%rbx),%rax + 415f1c: 48 39 43 28 cmp %rax,0x28(%rbx) + 415f20: 0f 87 f1 fe ff ff ja 415e17 <_IO_flush_all+0x147> + 415f26: e9 09 ff ff ff jmpq 415e34 <_IO_flush_all+0x164> + 415f2b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 415f30: 48 c7 04 24 50 41 41 movq $0x414150,(%rsp) + 415f37: 00 + 415f38: 48 c7 44 24 08 00 00 movq $0x0,0x8(%rsp) + 415f3f: 00 00 + 415f41: e9 b4 fd ff ff jmpq 415cfa <_IO_flush_all+0x2a> + 415f46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 415f4d: 00 00 00 + +0000000000415f50 <_IO_flush_all_linebuffered>: + 415f50: 41 55 push %r13 + 415f52: 41 54 push %r12 + 415f54: 55 push %rbp + 415f55: 53 push %rbx + 415f56: bd 00 00 00 00 mov $0x0,%ebp + 415f5b: 48 83 ec 28 sub $0x28,%rsp + 415f5f: 48 85 ed test %rbp,%rbp + 415f62: 0f 84 38 02 00 00 je 4161a0 <_IO_flush_all_linebuffered+0x250> + 415f68: 31 d2 xor %edx,%edx + 415f6a: be 50 41 41 00 mov $0x414150,%esi + 415f6f: 48 89 e7 mov %rsp,%rdi + 415f72: e8 89 a0 be ff callq 0 <_nl_current_LC_CTYPE> + 415f77: 64 48 8b 14 25 10 00 mov %fs:0x10,%rdx + 415f7e: 00 00 + 415f80: 48 3b 15 21 66 2b 00 cmp 0x2b6621(%rip),%rdx # 6cc5a8 + 415f87: 74 46 je 415fcf <_IO_flush_all_linebuffered+0x7f> + 415f89: be 01 00 00 00 mov $0x1,%esi + 415f8e: 31 c0 xor %eax,%eax + 415f90: 83 3d 25 72 2b 00 00 cmpl $0x0,0x2b7225(%rip) # 6cd1bc <__libc_multiple_threads> + 415f97: 74 0c je 415fa5 <_IO_flush_all_linebuffered+0x55> + 415f99: f0 0f b1 35 ff 65 2b lock cmpxchg %esi,0x2b65ff(%rip) # 6cc5a0 + 415fa0: 00 + 415fa1: 75 0b jne 415fae <_IO_flush_all_linebuffered+0x5e> + 415fa3: eb 23 jmp 415fc8 <_IO_flush_all_linebuffered+0x78> + 415fa5: 0f b1 35 f4 65 2b 00 cmpxchg %esi,0x2b65f4(%rip) # 6cc5a0 + 415fac: 74 1a je 415fc8 <_IO_flush_all_linebuffered+0x78> + 415fae: 48 8d 3d eb 65 2b 00 lea 0x2b65eb(%rip),%rdi # 6cc5a0 + 415fb5: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 415fbc: e8 0f c6 02 00 callq 4425d0 <__lll_lock_wait_private> + 415fc1: 48 81 c4 80 00 00 00 add $0x80,%rsp + 415fc8: 48 89 15 d9 65 2b 00 mov %rdx,0x2b65d9(%rip) # 6cc5a8 + 415fcf: 8b 05 cf 65 2b 00 mov 0x2b65cf(%rip),%eax # 6cc5a4 + 415fd5: 48 8b 1d e4 40 2b 00 mov 0x2b40e4(%rip),%rbx # 6ca0c0 <_IO_list_all> + 415fdc: 44 8b 25 b5 65 2b 00 mov 0x2b65b5(%rip),%r12d # 6cc598 <_IO_list_all_stamp> + 415fe3: 83 c0 01 add $0x1,%eax + 415fe6: 48 85 db test %rbx,%rbx + 415fe9: 89 05 b5 65 2b 00 mov %eax,0x2b65b5(%rip) # 6cc5a4 + 415fef: 0f 84 3a 01 00 00 je 41612f <_IO_flush_all_linebuffered+0x1df> + 415ff5: 44 89 e0 mov %r12d,%eax + 415ff8: 64 4c 8b 2c 25 10 00 mov %fs:0x10,%r13 + 415fff: 00 00 + 416001: e9 d7 00 00 00 jmpq 4160dd <_IO_flush_all_linebuffered+0x18d> + 416006: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41600d: 00 00 00 + 416010: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx + 416017: 4c 3b 6a 08 cmp 0x8(%rdx),%r13 + 41601b: 74 3e je 41605b <_IO_flush_all_linebuffered+0x10b> + 41601d: be 01 00 00 00 mov $0x1,%esi + 416022: 89 c8 mov %ecx,%eax + 416024: 83 3d 91 71 2b 00 00 cmpl $0x0,0x2b7191(%rip) # 6cd1bc <__libc_multiple_threads> + 41602b: 74 08 je 416035 <_IO_flush_all_linebuffered+0xe5> + 41602d: f0 0f b1 32 lock cmpxchg %esi,(%rdx) + 416031: 75 07 jne 41603a <_IO_flush_all_linebuffered+0xea> + 416033: eb 1b jmp 416050 <_IO_flush_all_linebuffered+0x100> + 416035: 0f b1 32 cmpxchg %esi,(%rdx) + 416038: 74 16 je 416050 <_IO_flush_all_linebuffered+0x100> + 41603a: 48 8d 3a lea (%rdx),%rdi + 41603d: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 416044: e8 87 c5 02 00 callq 4425d0 <__lll_lock_wait_private> + 416049: 48 81 c4 80 00 00 00 add $0x80,%rsp + 416050: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx + 416057: 4c 89 6a 08 mov %r13,0x8(%rdx) + 41605b: 83 42 04 01 addl $0x1,0x4(%rdx) + 41605f: 8b 03 mov (%rbx),%eax + 416061: 25 08 02 00 00 and $0x208,%eax + 416066: 3d 00 02 00 00 cmp $0x200,%eax + 41606b: 0f 84 91 00 00 00 je 416102 <_IO_flush_all_linebuffered+0x1b2> + 416071: f7 03 00 80 00 00 testl $0x8000,(%rbx) + 416077: 75 3f jne 4160b8 <_IO_flush_all_linebuffered+0x168> + 416079: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx + 416080: 83 6a 04 01 subl $0x1,0x4(%rdx) + 416084: 75 32 jne 4160b8 <_IO_flush_all_linebuffered+0x168> + 416086: 48 c7 42 08 00 00 00 movq $0x0,0x8(%rdx) + 41608d: 00 + 41608e: 83 3d 27 71 2b 00 00 cmpl $0x0,0x2b7127(%rip) # 6cd1bc <__libc_multiple_threads> + 416095: 74 07 je 41609e <_IO_flush_all_linebuffered+0x14e> + 416097: f0 ff 0a lock decl (%rdx) + 41609a: 75 06 jne 4160a2 <_IO_flush_all_linebuffered+0x152> + 41609c: eb 1a jmp 4160b8 <_IO_flush_all_linebuffered+0x168> + 41609e: ff 0a decl (%rdx) + 4160a0: 74 16 je 4160b8 <_IO_flush_all_linebuffered+0x168> + 4160a2: 48 8d 3a lea (%rdx),%rdi + 4160a5: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 4160ac: e8 4f c5 02 00 callq 442600 <__lll_unlock_wake_private> + 4160b1: 48 81 c4 80 00 00 00 add $0x80,%rsp + 4160b8: 8b 05 da 64 2b 00 mov 0x2b64da(%rip),%eax # 6cc598 <_IO_list_all_stamp> + 4160be: 41 39 c4 cmp %eax,%r12d + 4160c1: 48 c7 05 c4 64 2b 00 movq $0x0,0x2b64c4(%rip) # 6cc590 + 4160c8: 00 00 00 00 + 4160cc: 74 52 je 416120 <_IO_flush_all_linebuffered+0x1d0> + 4160ce: 48 8b 1d eb 3f 2b 00 mov 0x2b3feb(%rip),%rbx # 6ca0c0 <_IO_list_all> + 4160d5: 41 89 c4 mov %eax,%r12d + 4160d8: 48 85 db test %rbx,%rbx + 4160db: 74 4c je 416129 <_IO_flush_all_linebuffered+0x1d9> + 4160dd: 8b 13 mov (%rbx),%edx + 4160df: 48 89 1d aa 64 2b 00 mov %rbx,0x2b64aa(%rip) # 6cc590 + 4160e6: 89 d1 mov %edx,%ecx + 4160e8: 81 e1 00 80 00 00 and $0x8000,%ecx + 4160ee: 0f 84 1c ff ff ff je 416010 <_IO_flush_all_linebuffered+0xc0> + 4160f4: 81 e2 08 02 00 00 and $0x208,%edx + 4160fa: 81 fa 00 02 00 00 cmp $0x200,%edx + 416100: 75 bc jne 4160be <_IO_flush_all_linebuffered+0x16e> + 416102: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax + 416109: be ff ff ff ff mov $0xffffffff,%esi + 41610e: 48 89 df mov %rbx,%rdi + 416111: ff 50 18 callq *0x18(%rax) + 416114: e9 58 ff ff ff jmpq 416071 <_IO_flush_all_linebuffered+0x121> + 416119: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 416120: 48 8b 5b 68 mov 0x68(%rbx),%rbx + 416124: 48 85 db test %rbx,%rbx + 416127: 75 b4 jne 4160dd <_IO_flush_all_linebuffered+0x18d> + 416129: 8b 05 75 64 2b 00 mov 0x2b6475(%rip),%eax # 6cc5a4 + 41612f: 83 e8 01 sub $0x1,%eax + 416132: 85 c0 test %eax,%eax + 416134: 89 05 6a 64 2b 00 mov %eax,0x2b646a(%rip) # 6cc5a4 + 41613a: 75 41 jne 41617d <_IO_flush_all_linebuffered+0x22d> + 41613c: 48 c7 05 61 64 2b 00 movq $0x0,0x2b6461(%rip) # 6cc5a8 + 416143: 00 00 00 00 + 416147: 83 3d 6e 70 2b 00 00 cmpl $0x0,0x2b706e(%rip) # 6cd1bc <__libc_multiple_threads> + 41614e: 74 0b je 41615b <_IO_flush_all_linebuffered+0x20b> + 416150: f0 ff 0d 49 64 2b 00 lock decl 0x2b6449(%rip) # 6cc5a0 + 416157: 75 0a jne 416163 <_IO_flush_all_linebuffered+0x213> + 416159: eb 22 jmp 41617d <_IO_flush_all_linebuffered+0x22d> + 41615b: ff 0d 3f 64 2b 00 decl 0x2b643f(%rip) # 6cc5a0 + 416161: 74 1a je 41617d <_IO_flush_all_linebuffered+0x22d> + 416163: 48 8d 3d 36 64 2b 00 lea 0x2b6436(%rip),%rdi # 6cc5a0 + 41616a: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 416171: e8 8a c4 02 00 callq 442600 <__lll_unlock_wake_private> + 416176: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41617d: 48 85 ed test %rbp,%rbp + 416180: 74 0a je 41618c <_IO_flush_all_linebuffered+0x23c> + 416182: 31 f6 xor %esi,%esi + 416184: 48 89 e7 mov %rsp,%rdi + 416187: e8 74 9e be ff callq 0 <_nl_current_LC_CTYPE> + 41618c: 48 83 c4 28 add $0x28,%rsp + 416190: 5b pop %rbx + 416191: 5d pop %rbp + 416192: 41 5c pop %r12 + 416194: 41 5d pop %r13 + 416196: c3 retq + 416197: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 41619e: 00 00 + 4161a0: 48 c7 04 24 50 41 41 movq $0x414150,(%rsp) + 4161a7: 00 + 4161a8: 48 c7 44 24 08 00 00 movq $0x0,0x8(%rsp) + 4161af: 00 00 + 4161b1: e9 c1 fd ff ff jmpq 415f77 <_IO_flush_all_linebuffered+0x27> + 4161b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4161bd: 00 00 00 + +00000000004161c0 <_IO_init_marker>: + 4161c0: 55 push %rbp + 4161c1: 53 push %rbx + 4161c2: 48 89 fd mov %rdi,%rbp + 4161c5: 48 89 f3 mov %rsi,%rbx + 4161c8: 48 83 ec 08 sub $0x8,%rsp + 4161cc: 8b 06 mov (%rsi),%eax + 4161ce: 48 89 77 08 mov %rsi,0x8(%rdi) + 4161d2: f6 c4 08 test $0x8,%ah + 4161d5: 75 31 jne 416208 <_IO_init_marker+0x48> + 4161d7: 48 8b 53 08 mov 0x8(%rbx),%rdx + 4161db: f6 c4 01 test $0x1,%ah + 4161de: 89 d0 mov %edx,%eax + 4161e0: 75 1e jne 416200 <_IO_init_marker+0x40> + 4161e2: 2b 43 18 sub 0x18(%rbx),%eax + 4161e5: 89 45 10 mov %eax,0x10(%rbp) + 4161e8: 48 8b 43 60 mov 0x60(%rbx),%rax + 4161ec: 48 89 45 00 mov %rax,0x0(%rbp) + 4161f0: 48 89 6b 60 mov %rbp,0x60(%rbx) + 4161f4: 48 83 c4 08 add $0x8,%rsp + 4161f8: 5b pop %rbx + 4161f9: 5d pop %rbp + 4161fa: c3 retq + 4161fb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 416200: 2b 43 10 sub 0x10(%rbx),%eax + 416203: eb e0 jmp 4161e5 <_IO_init_marker+0x25> + 416205: 0f 1f 00 nopl (%rax) + 416208: 48 8b 4e 28 mov 0x28(%rsi),%rcx + 41620c: 48 3b 4e 20 cmp 0x20(%rsi),%rcx + 416210: 77 3e ja 416250 <_IO_init_marker+0x90> + 416212: f6 c4 01 test $0x1,%ah + 416215: 75 29 jne 416240 <_IO_init_marker+0x80> + 416217: 48 3b 4b 10 cmp 0x10(%rbx),%rcx + 41621b: 48 8b 53 38 mov 0x38(%rbx),%rdx + 41621f: 48 89 53 18 mov %rdx,0x18(%rbx) + 416223: 48 89 ca mov %rcx,%rdx + 416226: 76 04 jbe 41622c <_IO_init_marker+0x6c> + 416228: 48 89 4b 10 mov %rcx,0x10(%rbx) + 41622c: 80 e4 f7 and $0xf7,%ah + 41622f: 48 89 4b 08 mov %rcx,0x8(%rbx) + 416233: 48 89 4b 30 mov %rcx,0x30(%rbx) + 416237: 48 89 4b 20 mov %rcx,0x20(%rbx) + 41623b: 89 03 mov %eax,(%rbx) + 41623d: eb 9c jmp 4161db <_IO_init_marker+0x1b> + 41623f: 90 nop + 416240: 48 8b 53 50 mov 0x50(%rbx),%rdx + 416244: 48 89 53 18 mov %rdx,0x18(%rbx) + 416248: 48 89 ca mov %rcx,%rdx + 41624b: eb df jmp 41622c <_IO_init_marker+0x6c> + 41624d: 0f 1f 00 nopl (%rax) + 416250: 48 8b 86 d8 00 00 00 mov 0xd8(%rsi),%rax + 416257: 48 89 df mov %rbx,%rdi + 41625a: be ff ff ff ff mov $0xffffffff,%esi + 41625f: ff 50 18 callq *0x18(%rax) + 416262: 83 f8 ff cmp $0xffffffff,%eax + 416265: 8b 03 mov (%rbx),%eax + 416267: 0f 84 6a ff ff ff je 4161d7 <_IO_init_marker+0x17> + 41626d: 48 8b 4b 28 mov 0x28(%rbx),%rcx + 416271: eb 9f jmp 416212 <_IO_init_marker+0x52> + 416273: 0f 1f 00 nopl (%rax) + 416276: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41627d: 00 00 00 + +0000000000416280 <_IO_remove_marker>: + 416280: 48 8b 47 08 mov 0x8(%rdi),%rax + 416284: 48 8b 50 60 mov 0x60(%rax),%rdx + 416288: 48 85 d2 test %rdx,%rdx + 41628b: 74 1b je 4162a8 <_IO_remove_marker+0x28> + 41628d: 48 39 d7 cmp %rdx,%rdi + 416290: 75 0e jne 4162a0 <_IO_remove_marker+0x20> + 416292: eb 16 jmp 4162aa <_IO_remove_marker+0x2a> + 416294: 0f 1f 40 00 nopl 0x0(%rax) + 416298: 48 39 c7 cmp %rax,%rdi + 41629b: 74 11 je 4162ae <_IO_remove_marker+0x2e> + 41629d: 48 89 c2 mov %rax,%rdx + 4162a0: 48 8b 02 mov (%rdx),%rax + 4162a3: 48 85 c0 test %rax,%rax + 4162a6: 75 f0 jne 416298 <_IO_remove_marker+0x18> + 4162a8: f3 c3 repz retq + 4162aa: 48 8d 50 60 lea 0x60(%rax),%rdx + 4162ae: 48 8b 07 mov (%rdi),%rax + 4162b1: 48 89 02 mov %rax,(%rdx) + 4162b4: c3 retq + 4162b5: 90 nop + 4162b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4162bd: 00 00 00 + +00000000004162c0 <_IO_marker_difference>: + 4162c0: 8b 47 10 mov 0x10(%rdi),%eax + 4162c3: 2b 46 10 sub 0x10(%rsi),%eax + 4162c6: c3 retq + 4162c7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 4162ce: 00 00 + +00000000004162d0 <_IO_marker_delta>: + 4162d0: 48 8b 47 08 mov 0x8(%rdi),%rax + 4162d4: 48 85 c0 test %rax,%rax + 4162d7: 74 20 je 4162f9 <_IO_marker_delta+0x29> + 4162d9: f7 00 00 01 00 00 testl $0x100,(%rax) + 4162df: 48 8b 50 08 mov 0x8(%rax),%rdx + 4162e3: 75 0b jne 4162f0 <_IO_marker_delta+0x20> + 4162e5: 2b 50 18 sub 0x18(%rax),%edx + 4162e8: 8b 47 10 mov 0x10(%rdi),%eax + 4162eb: 29 d0 sub %edx,%eax + 4162ed: c3 retq + 4162ee: 66 90 xchg %ax,%ax + 4162f0: 2b 50 10 sub 0x10(%rax),%edx + 4162f3: 8b 47 10 mov 0x10(%rdi),%eax + 4162f6: 29 d0 sub %edx,%eax + 4162f8: c3 retq + 4162f9: b8 ff ff ff ff mov $0xffffffff,%eax + 4162fe: c3 retq + 4162ff: 90 nop + +0000000000416300 <_IO_seekmark>: + 416300: 48 8b 56 08 mov 0x8(%rsi),%rdx + 416304: b8 ff ff ff ff mov $0xffffffff,%eax + 416309: 48 39 fa cmp %rdi,%rdx + 41630c: 75 3d jne 41634b <_IO_seekmark+0x4b> + 41630e: 48 63 46 10 movslq 0x10(%rsi),%rax + 416312: 8b 0a mov (%rdx),%ecx + 416314: 85 c0 test %eax,%eax + 416316: 78 48 js 416360 <_IO_seekmark+0x60> + 416318: f6 c5 01 test $0x1,%ch + 41631b: 74 33 je 416350 <_IO_seekmark+0x50> + 41631d: 80 e5 fe and $0xfe,%ch + 416320: 48 8b 72 58 mov 0x58(%rdx),%rsi + 416324: 89 0a mov %ecx,(%rdx) + 416326: 48 8b 4a 10 mov 0x10(%rdx),%rcx + 41632a: 48 89 72 10 mov %rsi,0x10(%rdx) + 41632e: 48 8b 72 18 mov 0x18(%rdx),%rsi + 416332: 48 89 4a 58 mov %rcx,0x58(%rdx) + 416336: 48 8b 4a 48 mov 0x48(%rdx),%rcx + 41633a: 48 89 72 48 mov %rsi,0x48(%rdx) + 41633e: 48 89 4a 18 mov %rcx,0x18(%rdx) + 416342: 48 01 c8 add %rcx,%rax + 416345: 48 89 42 08 mov %rax,0x8(%rdx) + 416349: 31 c0 xor %eax,%eax + 41634b: f3 c3 repz retq + 41634d: 0f 1f 00 nopl (%rax) + 416350: 48 8b 4a 18 mov 0x18(%rdx),%rcx + 416354: eb ec jmp 416342 <_IO_seekmark+0x42> + 416356: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41635d: 00 00 00 + 416360: f6 c5 01 test $0x1,%ch + 416363: 75 2b jne 416390 <_IO_seekmark+0x90> + 416365: 48 8b 72 10 mov 0x10(%rdx),%rsi + 416369: 80 cd 01 or $0x1,%ch + 41636c: 48 8b 7a 48 mov 0x48(%rdx),%rdi + 416370: 89 0a mov %ecx,(%rdx) + 416372: 48 8b 4a 58 mov 0x58(%rdx),%rcx + 416376: 48 89 72 58 mov %rsi,0x58(%rdx) + 41637a: 48 8b 72 18 mov 0x18(%rdx),%rsi + 41637e: 48 89 4a 10 mov %rcx,0x10(%rdx) + 416382: 48 89 7a 18 mov %rdi,0x18(%rdx) + 416386: 48 89 72 48 mov %rsi,0x48(%rdx) + 41638a: eb b6 jmp 416342 <_IO_seekmark+0x42> + 41638c: 0f 1f 40 00 nopl 0x0(%rax) + 416390: 48 8b 4a 10 mov 0x10(%rdx),%rcx + 416394: eb ac jmp 416342 <_IO_seekmark+0x42> + 416396: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41639d: 00 00 00 + +00000000004163a0 <_IO_unsave_markers>: + 4163a0: 48 83 7f 60 00 cmpq $0x0,0x60(%rdi) + 4163a5: 48 89 f8 mov %rdi,%rax + 4163a8: 74 08 je 4163b2 <_IO_unsave_markers+0x12> + 4163aa: 48 c7 47 60 00 00 00 movq $0x0,0x60(%rdi) + 4163b1: 00 + 4163b2: 48 8b 78 48 mov 0x48(%rax),%rdi + 4163b6: 48 85 ff test %rdi,%rdi + 4163b9: 74 45 je 416400 <_IO_unsave_markers+0x60> + 4163bb: 8b 10 mov (%rax),%edx + 4163bd: 53 push %rbx + 4163be: f6 c6 01 test $0x1,%dh + 4163c1: 74 1c je 4163df <_IO_unsave_markers+0x3f> + 4163c3: 80 e6 fe and $0xfe,%dh + 4163c6: 48 89 78 08 mov %rdi,0x8(%rax) + 4163ca: 89 10 mov %edx,(%rax) + 4163cc: 48 8b 50 58 mov 0x58(%rax),%rdx + 4163d0: 48 89 50 10 mov %rdx,0x10(%rax) + 4163d4: 48 8b 50 18 mov 0x18(%rax),%rdx + 4163d8: 48 89 78 18 mov %rdi,0x18(%rax) + 4163dc: 48 89 d7 mov %rdx,%rdi + 4163df: 48 89 c3 mov %rax,%rbx + 4163e2: e8 c9 79 00 00 callq 41ddb0 <__cfree> + 4163e7: 48 c7 43 48 00 00 00 movq $0x0,0x48(%rbx) + 4163ee: 00 + 4163ef: 48 c7 43 58 00 00 00 movq $0x0,0x58(%rbx) + 4163f6: 00 + 4163f7: 48 c7 43 50 00 00 00 movq $0x0,0x50(%rbx) + 4163fe: 00 + 4163ff: 5b pop %rbx + 416400: f3 c3 repz retq + 416402: 0f 1f 40 00 nopl 0x0(%rax) + 416406: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41640d: 00 00 00 + +0000000000416410 <_IO_default_pbackfail>: + 416410: 41 57 push %r15 + 416412: 41 56 push %r14 + 416414: 41 55 push %r13 + 416416: 41 54 push %r12 + 416418: 41 89 f4 mov %esi,%r12d + 41641b: 55 push %rbp + 41641c: 53 push %rbx + 41641d: 48 89 fb mov %rdi,%rbx + 416420: 48 83 ec 08 sub $0x8,%rsp + 416424: 48 8b 6f 08 mov 0x8(%rdi),%rbp + 416428: 4c 8b 77 18 mov 0x18(%rdi),%r14 + 41642c: 44 8b 2f mov (%rdi),%r13d + 41642f: 4c 39 f5 cmp %r14,%rbp + 416432: 76 2c jbe 416460 <_IO_default_pbackfail+0x50> + 416434: 41 f7 c5 00 01 00 00 test $0x100,%r13d + 41643b: 74 7b je 4164b8 <_IO_default_pbackfail+0xa8> + 41643d: 48 8d 45 ff lea -0x1(%rbp),%rax + 416441: 48 89 43 08 mov %rax,0x8(%rbx) + 416445: 44 88 65 ff mov %r12b,-0x1(%rbp) + 416449: 41 0f b6 c4 movzbl %r12b,%eax + 41644d: 48 83 c4 08 add $0x8,%rsp + 416451: 5b pop %rbx + 416452: 5d pop %rbp + 416453: 41 5c pop %r12 + 416455: 41 5d pop %r13 + 416457: 41 5e pop %r14 + 416459: 41 5f pop %r15 + 41645b: c3 retq + 41645c: 0f 1f 40 00 nopl 0x0(%rax) + 416460: 41 f7 c5 00 01 00 00 test $0x100,%r13d + 416467: 0f 84 83 00 00 00 je 4164f0 <_IO_default_pbackfail+0xe0> + 41646d: 4c 8b 6b 10 mov 0x10(%rbx),%r13 + 416471: 4d 29 f5 sub %r14,%r13 + 416474: 4b 8d 7c 2d 00 lea 0x0(%r13,%r13,1),%rdi + 416479: e8 92 75 00 00 callq 41da10 <__libc_malloc> + 41647e: 48 85 c0 test %rax,%rax + 416481: 49 89 c7 mov %rax,%r15 + 416484: 0f 84 d0 00 00 00 je 41655a <_IO_default_pbackfail+0x14a> + 41648a: 4a 8d 2c 28 lea (%rax,%r13,1),%rbp + 41648e: 4c 89 ea mov %r13,%rdx + 416491: 4c 89 f6 mov %r14,%rsi + 416494: 48 89 ef mov %rbp,%rdi + 416497: 49 01 ed add %rbp,%r13 + 41649a: e8 81 5b 01 00 callq 42c020 + 41649f: 4c 89 f7 mov %r14,%rdi + 4164a2: e8 09 79 00 00 callq 41ddb0 <__cfree> + 4164a7: 4c 89 7b 18 mov %r15,0x18(%rbx) + 4164ab: 4c 89 6b 10 mov %r13,0x10(%rbx) + 4164af: 48 89 6b 50 mov %rbp,0x50(%rbx) + 4164b3: eb 88 jmp 41643d <_IO_default_pbackfail+0x2d> + 4164b5: 0f 1f 00 nopl (%rax) + 4164b8: 0f b6 45 ff movzbl -0x1(%rbp),%eax + 4164bc: 39 f0 cmp %esi,%eax + 4164be: 74 68 je 416528 <_IO_default_pbackfail+0x118> + 4164c0: 48 83 7f 48 00 cmpq $0x0,0x48(%rdi) + 4164c5: 74 71 je 416538 <_IO_default_pbackfail+0x128> + 4164c7: 48 89 ee mov %rbp,%rsi + 4164ca: 48 89 df mov %rbx,%rdi + 4164cd: e8 8e da ff ff callq 413f60 + 4164d2: 85 c0 test %eax,%eax + 4164d4: 0f 85 80 00 00 00 jne 41655a <_IO_default_pbackfail+0x14a> + 4164da: 48 8b 4b 08 mov 0x8(%rbx),%rcx + 4164de: 44 8b 2b mov (%rbx),%r13d + 4164e1: 48 8b 6b 58 mov 0x58(%rbx),%rbp + 4164e5: 48 8b 43 48 mov 0x48(%rbx),%rax + 4164e9: eb 15 jmp 416500 <_IO_default_pbackfail+0xf0> + 4164eb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4164f0: 48 8b 43 48 mov 0x48(%rbx),%rax + 4164f4: 48 85 c0 test %rax,%rax + 4164f7: 74 3f je 416538 <_IO_default_pbackfail+0x128> + 4164f9: 48 89 e9 mov %rbp,%rcx + 4164fc: 48 8b 6b 58 mov 0x58(%rbx),%rbp + 416500: 48 8b 53 10 mov 0x10(%rbx),%rdx + 416504: 41 81 cd 00 01 00 00 or $0x100,%r13d + 41650b: 48 89 6b 10 mov %rbp,0x10(%rbx) + 41650f: 44 89 2b mov %r13d,(%rbx) + 416512: 48 89 43 18 mov %rax,0x18(%rbx) + 416516: 48 89 4b 48 mov %rcx,0x48(%rbx) + 41651a: 48 89 53 58 mov %rdx,0x58(%rbx) + 41651e: e9 1a ff ff ff jmpq 41643d <_IO_default_pbackfail+0x2d> + 416523: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 416528: 48 83 ed 01 sub $0x1,%rbp + 41652c: 48 89 6f 08 mov %rbp,0x8(%rdi) + 416530: e9 14 ff ff ff jmpq 416449 <_IO_default_pbackfail+0x39> + 416535: 0f 1f 00 nopl (%rax) + 416538: bf 80 00 00 00 mov $0x80,%edi + 41653d: e8 ce 74 00 00 callq 41da10 <__libc_malloc> + 416542: 48 85 c0 test %rax,%rax + 416545: 74 13 je 41655a <_IO_default_pbackfail+0x14a> + 416547: 48 8d 90 80 00 00 00 lea 0x80(%rax),%rdx + 41654e: 48 89 e9 mov %rbp,%rcx + 416551: 48 89 53 50 mov %rdx,0x50(%rbx) + 416555: 48 89 d5 mov %rdx,%rbp + 416558: eb a6 jmp 416500 <_IO_default_pbackfail+0xf0> + 41655a: b8 ff ff ff ff mov $0xffffffff,%eax + 41655f: e9 e9 fe ff ff jmpq 41644d <_IO_default_pbackfail+0x3d> + 416564: 66 90 xchg %ax,%ax + 416566: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41656d: 00 00 00 + +0000000000416570 <_IO_default_seek>: + 416570: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax + 416577: c3 retq + 416578: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 41657f: 00 + +0000000000416580 <_IO_default_stat>: + 416580: b8 ff ff ff ff mov $0xffffffff,%eax + 416585: c3 retq + 416586: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41658d: 00 00 00 + +0000000000416590 <_IO_default_read>: + 416590: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax + 416597: c3 retq + 416598: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 41659f: 00 + +00000000004165a0 <_IO_default_write>: + 4165a0: 31 c0 xor %eax,%eax + 4165a2: c3 retq + 4165a3: 0f 1f 00 nopl (%rax) + 4165a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4165ad: 00 00 00 + +00000000004165b0 <_IO_default_showmanyc>: + 4165b0: b8 ff ff ff ff mov $0xffffffff,%eax + 4165b5: c3 retq + 4165b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4165bd: 00 00 00 + +00000000004165c0 <_IO_default_imbue>: + 4165c0: f3 c3 repz retq + 4165c2: 0f 1f 40 00 nopl 0x0(%rax) + 4165c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4165cd: 00 00 00 + +00000000004165d0 <_IO_iter_begin>: + 4165d0: 48 8b 05 e9 3a 2b 00 mov 0x2b3ae9(%rip),%rax # 6ca0c0 <_IO_list_all> + 4165d7: c3 retq + 4165d8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 4165df: 00 + +00000000004165e0 <_IO_iter_end>: + 4165e0: 31 c0 xor %eax,%eax + 4165e2: c3 retq + 4165e3: 0f 1f 00 nopl (%rax) + 4165e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4165ed: 00 00 00 + +00000000004165f0 <_IO_iter_next>: + 4165f0: 48 8b 47 68 mov 0x68(%rdi),%rax + 4165f4: c3 retq + 4165f5: 90 nop + 4165f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4165fd: 00 00 00 + +0000000000416600 <_IO_iter_file>: + 416600: 48 89 f8 mov %rdi,%rax + 416603: c3 retq + 416604: 66 90 xchg %ax,%ax + 416606: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41660d: 00 00 00 + +0000000000416610 <_IO_list_lock>: + 416610: 64 48 8b 14 25 10 00 mov %fs:0x10,%rdx + 416617: 00 00 + 416619: 48 3b 15 88 5f 2b 00 cmp 0x2b5f88(%rip),%rdx # 6cc5a8 + 416620: 74 46 je 416668 <_IO_list_lock+0x58> + 416622: be 01 00 00 00 mov $0x1,%esi + 416627: 31 c0 xor %eax,%eax + 416629: 83 3d 8c 6b 2b 00 00 cmpl $0x0,0x2b6b8c(%rip) # 6cd1bc <__libc_multiple_threads> + 416630: 74 0c je 41663e <_IO_list_lock+0x2e> + 416632: f0 0f b1 35 66 5f 2b lock cmpxchg %esi,0x2b5f66(%rip) # 6cc5a0 + 416639: 00 + 41663a: 75 0b jne 416647 <_IO_list_lock+0x37> + 41663c: eb 23 jmp 416661 <_IO_list_lock+0x51> + 41663e: 0f b1 35 5b 5f 2b 00 cmpxchg %esi,0x2b5f5b(%rip) # 6cc5a0 + 416645: 74 1a je 416661 <_IO_list_lock+0x51> + 416647: 48 8d 3d 52 5f 2b 00 lea 0x2b5f52(%rip),%rdi # 6cc5a0 + 41664e: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 416655: e8 76 bf 02 00 callq 4425d0 <__lll_lock_wait_private> + 41665a: 48 81 c4 80 00 00 00 add $0x80,%rsp + 416661: 48 89 15 40 5f 2b 00 mov %rdx,0x2b5f40(%rip) # 6cc5a8 + 416668: 83 05 35 5f 2b 00 01 addl $0x1,0x2b5f35(%rip) # 6cc5a4 + 41666f: c3 retq + +0000000000416670 <_IO_list_unlock>: + 416670: 83 2d 2d 5f 2b 00 01 subl $0x1,0x2b5f2d(%rip) # 6cc5a4 + 416677: 75 41 jne 4166ba <_IO_list_unlock+0x4a> + 416679: 48 c7 05 24 5f 2b 00 movq $0x0,0x2b5f24(%rip) # 6cc5a8 + 416680: 00 00 00 00 + 416684: 83 3d 31 6b 2b 00 00 cmpl $0x0,0x2b6b31(%rip) # 6cd1bc <__libc_multiple_threads> + 41668b: 74 0b je 416698 <_IO_list_unlock+0x28> + 41668d: f0 ff 0d 0c 5f 2b 00 lock decl 0x2b5f0c(%rip) # 6cc5a0 + 416694: 75 0a jne 4166a0 <_IO_list_unlock+0x30> + 416696: eb 22 jmp 4166ba <_IO_list_unlock+0x4a> + 416698: ff 0d 02 5f 2b 00 decl 0x2b5f02(%rip) # 6cc5a0 + 41669e: 74 1a je 4166ba <_IO_list_unlock+0x4a> + 4166a0: 48 8d 3d f9 5e 2b 00 lea 0x2b5ef9(%rip),%rdi # 6cc5a0 + 4166a7: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 4166ae: e8 4d bf 02 00 callq 442600 <__lll_unlock_wake_private> + 4166b3: 48 81 c4 80 00 00 00 add $0x80,%rsp + 4166ba: f3 c3 repz retq + 4166bc: 0f 1f 40 00 nopl 0x0(%rax) + +00000000004166c0 <_IO_list_resetlock>: + 4166c0: c7 05 d6 5e 2b 00 00 movl $0x0,0x2b5ed6(%rip) # 6cc5a0 + 4166c7: 00 00 00 + 4166ca: c7 05 d0 5e 2b 00 00 movl $0x0,0x2b5ed0(%rip) # 6cc5a4 + 4166d1: 00 00 00 + 4166d4: 48 c7 05 c9 5e 2b 00 movq $0x0,0x2b5ec9(%rip) # 6cc5a8 + 4166db: 00 00 00 00 + 4166df: c3 retq + +00000000004166e0 <_IO_str_underflow>: + 4166e0: 48 8b 47 28 mov 0x28(%rdi),%rax + 4166e4: 48 8b 4f 10 mov 0x10(%rdi),%rcx + 4166e8: 48 39 c8 cmp %rcx,%rax + 4166eb: 76 07 jbe 4166f4 <_IO_str_underflow+0x14> + 4166ed: 48 89 47 10 mov %rax,0x10(%rdi) + 4166f1: 48 89 c1 mov %rax,%rcx + 4166f4: 8b 17 mov (%rdi),%edx + 4166f6: 81 e2 00 0c 00 00 and $0xc00,%edx + 4166fc: 81 fa 00 0c 00 00 cmp $0xc00,%edx + 416702: 74 14 je 416718 <_IO_str_underflow+0x38> + 416704: 48 8b 47 08 mov 0x8(%rdi),%rax + 416708: 48 39 c8 cmp %rcx,%rax + 41670b: 73 23 jae 416730 <_IO_str_underflow+0x50> + 41670d: 0f b6 00 movzbl (%rax),%eax + 416710: c3 retq + 416711: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 416718: 48 8b 57 30 mov 0x30(%rdi),%rdx + 41671c: 81 27 ff f7 ff ff andl $0xfffff7ff,(%rdi) + 416722: 48 89 47 08 mov %rax,0x8(%rdi) + 416726: 48 89 57 28 mov %rdx,0x28(%rdi) + 41672a: eb dc jmp 416708 <_IO_str_underflow+0x28> + 41672c: 0f 1f 40 00 nopl 0x0(%rax) + 416730: b8 ff ff ff ff mov $0xffffffff,%eax + 416735: c3 retq + 416736: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41673d: 00 00 00 + +0000000000416740 <_IO_str_overflow>: + 416740: 8b 0f mov (%rdi),%ecx + 416742: f6 c1 08 test $0x8,%cl + 416745: 74 11 je 416758 <_IO_str_overflow+0x18> + 416747: 31 c0 xor %eax,%eax + 416749: 83 fe ff cmp $0xffffffff,%esi + 41674c: 0f 95 c0 setne %al + 41674f: f7 d8 neg %eax + 416751: c3 retq + 416752: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 416758: 41 57 push %r15 + 41675a: 89 c8 mov %ecx,%eax + 41675c: 41 56 push %r14 + 41675e: 41 55 push %r13 + 416760: 41 54 push %r12 + 416762: 25 00 0c 00 00 and $0xc00,%eax + 416767: 55 push %rbp + 416768: 53 push %rbx + 416769: 48 83 ec 08 sub $0x8,%rsp + 41676d: 3d 00 04 00 00 cmp $0x400,%eax + 416772: 0f 84 08 01 00 00 je 416880 <_IO_str_overflow+0x140> + 416778: 48 8b 57 28 mov 0x28(%rdi),%rdx + 41677c: 4c 8b 67 38 mov 0x38(%rdi),%r12 + 416780: 4c 8b 6f 40 mov 0x40(%rdi),%r13 + 416784: 89 f5 mov %esi,%ebp + 416786: 48 89 d6 mov %rdx,%rsi + 416789: 48 2b 77 20 sub 0x20(%rdi),%rsi + 41678d: 31 c0 xor %eax,%eax + 41678f: 48 89 fb mov %rdi,%rbx + 416792: 4d 29 e5 sub %r12,%r13 + 416795: 83 fd ff cmp $0xffffffff,%ebp + 416798: 0f 94 c0 sete %al + 41679b: 4c 01 e8 add %r13,%rax + 41679e: 48 39 c6 cmp %rax,%rsi + 4167a1: 0f 82 aa 00 00 00 jb 416851 <_IO_str_overflow+0x111> + 4167a7: 83 e1 01 and $0x1,%ecx + 4167aa: 0f 85 f0 00 00 00 jne 4168a0 <_IO_str_overflow+0x160> + 4167b0: 4f 8d 74 2d 64 lea 0x64(%r13,%r13,1),%r14 + 4167b5: 4d 39 f5 cmp %r14,%r13 + 4167b8: 0f 87 e2 00 00 00 ja 4168a0 <_IO_str_overflow+0x160> + 4167be: 4c 89 f7 mov %r14,%rdi + 4167c1: ff 93 e0 00 00 00 callq *0xe0(%rbx) + 4167c7: 48 85 c0 test %rax,%rax + 4167ca: 49 89 c7 mov %rax,%r15 + 4167cd: 0f 84 cd 00 00 00 je 4168a0 <_IO_str_overflow+0x160> + 4167d3: 4d 85 e4 test %r12,%r12 + 4167d6: 74 1f je 4167f7 <_IO_str_overflow+0xb7> + 4167d8: 4c 89 ea mov %r13,%rdx + 4167db: 4c 89 e6 mov %r12,%rsi + 4167de: 48 89 c7 mov %rax,%rdi + 4167e1: e8 3a 58 01 00 callq 42c020 + 4167e6: 4c 89 e7 mov %r12,%rdi + 4167e9: ff 93 e8 00 00 00 callq *0xe8(%rbx) + 4167ef: 48 c7 43 38 00 00 00 movq $0x0,0x38(%rbx) + 4167f6: 00 + 4167f7: 4b 8d 3c 2f lea (%r15,%r13,1),%rdi + 4167fb: 4c 89 f2 mov %r14,%rdx + 4167fe: 31 f6 xor %esi,%esi + 416800: 4c 29 ea sub %r13,%rdx + 416803: e8 48 9b fe ff callq 400350 <__rela_iplt_end+0x88> + 416808: 4b 8d 14 37 lea (%r15,%r14,1),%rdx + 41680c: b9 01 00 00 00 mov $0x1,%ecx + 416811: 4c 89 fe mov %r15,%rsi + 416814: 48 89 df mov %rbx,%rdi + 416817: e8 84 e5 ff ff callq 414da0 <_IO_setb> + 41681c: 4c 89 f8 mov %r15,%rax + 41681f: 4c 89 7b 20 mov %r15,0x20(%rbx) + 416823: 4c 29 e0 sub %r12,%rax + 416826: 48 01 43 18 add %rax,0x18(%rbx) + 41682a: 4c 89 f8 mov %r15,%rax + 41682d: 4c 29 e0 sub %r12,%rax + 416830: 48 01 43 08 add %rax,0x8(%rbx) + 416834: 4c 89 f8 mov %r15,%rax + 416837: 4c 29 e0 sub %r12,%rax + 41683a: 48 01 43 10 add %rax,0x10(%rbx) + 41683e: 48 89 c2 mov %rax,%rdx + 416841: 48 03 53 28 add 0x28(%rbx),%rdx + 416845: 48 8b 43 40 mov 0x40(%rbx),%rax + 416849: 48 89 53 28 mov %rdx,0x28(%rbx) + 41684d: 48 89 43 30 mov %rax,0x30(%rbx) + 416851: 83 fd ff cmp $0xffffffff,%ebp + 416854: 74 0f je 416865 <_IO_str_overflow+0x125> + 416856: 48 8d 42 01 lea 0x1(%rdx),%rax + 41685a: 48 89 43 28 mov %rax,0x28(%rbx) + 41685e: 40 88 2a mov %bpl,(%rdx) + 416861: 48 8b 53 28 mov 0x28(%rbx),%rdx + 416865: 48 39 53 10 cmp %rdx,0x10(%rbx) + 416869: 89 e8 mov %ebp,%eax + 41686b: 73 04 jae 416871 <_IO_str_overflow+0x131> + 41686d: 48 89 53 10 mov %rdx,0x10(%rbx) + 416871: 48 83 c4 08 add $0x8,%rsp + 416875: 5b pop %rbx + 416876: 5d pop %rbp + 416877: 41 5c pop %r12 + 416879: 41 5d pop %r13 + 41687b: 41 5e pop %r14 + 41687d: 41 5f pop %r15 + 41687f: c3 retq + 416880: 48 8b 57 08 mov 0x8(%rdi),%rdx + 416884: 48 8b 47 10 mov 0x10(%rdi),%rax + 416888: 80 cd 08 or $0x8,%ch + 41688b: 89 0f mov %ecx,(%rdi) + 41688d: 48 89 57 28 mov %rdx,0x28(%rdi) + 416891: 48 89 47 08 mov %rax,0x8(%rdi) + 416895: e9 e2 fe ff ff jmpq 41677c <_IO_str_overflow+0x3c> + 41689a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4168a0: b8 ff ff ff ff mov $0xffffffff,%eax + 4168a5: eb ca jmp 416871 <_IO_str_overflow+0x131> + 4168a7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 4168ae: 00 00 + +00000000004168b0 : + 4168b0: 41 57 push %r15 + 4168b2: 41 56 push %r14 + 4168b4: 41 55 push %r13 + 4168b6: 41 54 push %r12 + 4168b8: 55 push %rbp + 4168b9: 53 push %rbx + 4168ba: 48 83 ec 28 sub $0x28,%rsp + 4168be: 4c 8b 77 38 mov 0x38(%rdi),%r14 + 4168c2: 48 8b 47 40 mov 0x40(%rdi),%rax + 4168c6: 4c 29 f0 sub %r14,%rax + 4168c9: 48 39 f0 cmp %rsi,%rax + 4168cc: 0f 8d fe 00 00 00 jge 4169d0 + 4168d2: 44 8b 3f mov (%rdi),%r15d + 4168d5: 41 83 e7 01 and $0x1,%r15d + 4168d9: 74 1d je 4168f8 + 4168db: 41 bf 01 00 00 00 mov $0x1,%r15d + 4168e1: 48 83 c4 28 add $0x28,%rsp + 4168e5: 44 89 f8 mov %r15d,%eax + 4168e8: 5b pop %rbx + 4168e9: 5d pop %rbp + 4168ea: 41 5c pop %r12 + 4168ec: 41 5d pop %r13 + 4168ee: 41 5e pop %r14 + 4168f0: 41 5f pop %r15 + 4168f2: c3 retq + 4168f3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4168f8: 48 8b 47 20 mov 0x20(%rdi),%rax + 4168fc: 48 89 fb mov %rdi,%rbx + 4168ff: 4c 8b 67 30 mov 0x30(%rdi),%r12 + 416903: 89 54 24 1c mov %edx,0x1c(%rsp) + 416907: 48 89 f5 mov %rsi,%rbp + 41690a: 48 89 44 24 08 mov %rax,0x8(%rsp) + 41690f: 48 8d 46 64 lea 0x64(%rsi),%rax + 416913: 48 89 44 24 10 mov %rax,0x10(%rsp) + 416918: 48 89 c7 mov %rax,%rdi + 41691b: ff 93 e0 00 00 00 callq *0xe0(%rbx) + 416921: 48 85 c0 test %rax,%rax + 416924: 49 89 c5 mov %rax,%r13 + 416927: 74 b2 je 4168db + 416929: 4d 85 f6 test %r14,%r14 + 41692c: 74 24 je 416952 + 41692e: 48 8b 53 40 mov 0x40(%rbx),%rdx + 416932: 48 2b 53 38 sub 0x38(%rbx),%rdx + 416936: 4c 89 f6 mov %r14,%rsi + 416939: 48 89 c7 mov %rax,%rdi + 41693c: e8 df 56 01 00 callq 42c020 + 416941: 4c 89 f7 mov %r14,%rdi + 416944: ff 93 e8 00 00 00 callq *0xe8(%rbx) + 41694a: 48 c7 43 38 00 00 00 movq $0x0,0x38(%rbx) + 416951: 00 + 416952: 48 8b 54 24 10 mov 0x10(%rsp),%rdx + 416957: b9 01 00 00 00 mov $0x1,%ecx + 41695c: 4c 89 ee mov %r13,%rsi + 41695f: 48 89 df mov %rbx,%rdi + 416962: 4c 2b 64 24 08 sub 0x8(%rsp),%r12 + 416967: 4c 01 ea add %r13,%rdx + 41696a: e8 31 e4 ff ff callq 414da0 <_IO_setb> + 41696f: 8b 54 24 1c mov 0x1c(%rsp),%edx + 416973: 4c 89 e8 mov %r13,%rax + 416976: 4c 29 f0 sub %r14,%rax + 416979: 85 d2 test %edx,%edx + 41697b: 75 63 jne 4169e0 + 41697d: 48 01 43 18 add %rax,0x18(%rbx) + 416981: 4c 89 e8 mov %r13,%rax + 416984: 4c 89 6b 20 mov %r13,0x20(%rbx) + 416988: 4c 29 f0 sub %r14,%rax + 41698b: 48 01 43 08 add %rax,0x8(%rbx) + 41698f: 4c 89 e8 mov %r13,%rax + 416992: 4c 29 f0 sub %r14,%rax + 416995: 48 01 43 10 add %rax,0x10(%rbx) + 416999: 4c 89 e8 mov %r13,%rax + 41699c: 4c 29 f0 sub %r14,%rax + 41699f: 48 01 43 28 add %rax,0x28(%rbx) + 4169a3: 4c 39 e5 cmp %r12,%rbp + 4169a6: 48 8b 43 40 mov 0x40(%rbx),%rax + 4169aa: 48 89 43 30 mov %rax,0x30(%rbx) + 4169ae: 7c 63 jl 416a13 + 4169b0: 48 89 ea mov %rbp,%rdx + 4169b3: 4b 8d 7c 25 00 lea 0x0(%r13,%r12,1),%rdi + 4169b8: 31 f6 xor %esi,%esi + 4169ba: 4c 29 e2 sub %r12,%rdx + 4169bd: e8 8e 99 fe ff callq 400350 <__rela_iplt_end+0x88> + 4169c2: e9 1a ff ff ff jmpq 4168e1 + 4169c7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 4169ce: 00 00 + 4169d0: 45 31 ff xor %r15d,%r15d + 4169d3: e9 09 ff ff ff jmpq 4168e1 + 4169d8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 4169df: 00 + 4169e0: 48 01 43 20 add %rax,0x20(%rbx) + 4169e4: 4c 89 e8 mov %r13,%rax + 4169e7: 4c 89 6b 18 mov %r13,0x18(%rbx) + 4169eb: 4c 29 f0 sub %r14,%rax + 4169ee: 48 01 43 28 add %rax,0x28(%rbx) + 4169f2: 4c 89 e8 mov %r13,%rax + 4169f5: 4c 29 f0 sub %r14,%rax + 4169f8: 48 01 43 30 add %rax,0x30(%rbx) + 4169fc: 4c 89 e8 mov %r13,%rax + 4169ff: 4c 29 f0 sub %r14,%rax + 416a02: 48 01 43 08 add %rax,0x8(%rbx) + 416a06: 4c 39 e5 cmp %r12,%rbp + 416a09: 48 8b 43 40 mov 0x40(%rbx),%rax + 416a0d: 48 89 43 10 mov %rax,0x10(%rbx) + 416a11: 7d 9d jge 4169b0 + 416a13: b9 f0 1e 4a 00 mov $0x4a1ef0,%ecx + 416a18: ba e0 00 00 00 mov $0xe0,%edx + 416a1d: be c8 1e 4a 00 mov $0x4a1ec8,%esi + 416a22: bf d1 1e 4a 00 mov $0x4a1ed1,%edi + 416a27: e8 14 ad fe ff callq 401740 <__assert_fail> + 416a2c: 0f 1f 40 00 nopl 0x0(%rax) + +0000000000416a30 <_IO_str_seekoff>: + 416a30: 41 55 push %r13 + 416a32: 41 54 push %r12 + 416a34: 41 89 d5 mov %edx,%r13d + 416a37: 55 push %rbp + 416a38: 53 push %rbx + 416a39: 49 89 f4 mov %rsi,%r12 + 416a3c: 48 89 fb mov %rdi,%rbx + 416a3f: 48 83 ec 18 sub $0x18,%rsp + 416a43: 85 c9 test %ecx,%ecx + 416a45: 0f 85 85 00 00 00 jne 416ad0 <_IO_str_seekoff+0xa0> + 416a4b: 8b 07 mov (%rdi),%eax + 416a4d: f6 c4 04 test $0x4,%ah + 416a50: 74 5e je 416ab0 <_IO_str_seekoff+0x80> + 416a52: f6 c4 08 test $0x8,%ah + 416a55: 0f 84 b5 00 00 00 je 416b10 <_IO_str_seekoff+0xe0> + 416a5b: 48 8b 6f 28 mov 0x28(%rdi),%rbp + 416a5f: 48 39 6f 10 cmp %rbp,0x10(%rdi) + 416a63: 48 0f 43 6f 10 cmovae 0x10(%rdi),%rbp + 416a68: 48 2b 6f 18 sub 0x18(%rdi),%rbp + 416a6c: 41 83 fd 01 cmp $0x1,%r13d + 416a70: 0f 84 12 01 00 00 je 416b88 <_IO_str_seekoff+0x158> + 416a76: 49 8d 04 2c lea (%r12,%rbp,1),%rax + 416a7a: 41 83 fd 02 cmp $0x2,%r13d + 416a7e: 4c 0f 44 e0 cmove %rax,%r12 + 416a82: 4d 85 e4 test %r12,%r12 + 416a85: 0f 88 2a 01 00 00 js 416bb5 <_IO_str_seekoff+0x185> + 416a8b: 49 39 ec cmp %rbp,%r12 + 416a8e: 0f 8f 0c 01 00 00 jg 416ba0 <_IO_str_seekoff+0x170> + 416a94: 4c 89 e0 mov %r12,%rax + 416a97: 48 03 43 20 add 0x20(%rbx),%rax + 416a9b: 48 89 43 28 mov %rax,0x28(%rbx) + 416a9f: 48 83 c4 18 add $0x18,%rsp + 416aa3: 4c 89 e0 mov %r12,%rax + 416aa6: 5b pop %rbx + 416aa7: 5d pop %rbp + 416aa8: 41 5c pop %r12 + 416aaa: 41 5d pop %r13 + 416aac: c3 retq + 416aad: 0f 1f 00 nopl (%rax) + 416ab0: a8 08 test $0x8,%al + 416ab2: 0f 85 a8 00 00 00 jne 416b60 <_IO_str_seekoff+0x130> + 416ab8: 48 8b 43 28 mov 0x28(%rbx),%rax + 416abc: 48 2b 43 20 sub 0x20(%rbx),%rax + 416ac0: 48 83 c4 18 add $0x18,%rsp + 416ac4: 5b pop %rbx + 416ac5: 5d pop %rbp + 416ac6: 41 5c pop %r12 + 416ac8: 41 5d pop %r13 + 416aca: c3 retq + 416acb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 416ad0: 48 8b 6f 28 mov 0x28(%rdi),%rbp + 416ad4: 48 39 6f 10 cmp %rbp,0x10(%rdi) + 416ad8: 48 0f 43 6f 10 cmovae 0x10(%rdi),%rbp + 416add: 48 8b 47 18 mov 0x18(%rdi),%rax + 416ae1: 48 29 c5 sub %rax,%rbp + 416ae4: f6 c1 01 test $0x1,%cl + 416ae7: 75 40 jne 416b29 <_IO_str_seekoff+0xf9> + 416ae9: 83 e1 02 and $0x2,%ecx + 416aec: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax + 416af3: 85 c9 test %ecx,%ecx + 416af5: 0f 85 71 ff ff ff jne 416a6c <_IO_str_seekoff+0x3c> + 416afb: 48 83 c4 18 add $0x18,%rsp + 416aff: 5b pop %rbx + 416b00: 5d pop %rbp + 416b01: 41 5c pop %r12 + 416b03: 41 5d pop %r13 + 416b05: c3 retq + 416b06: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 416b0d: 00 00 00 + 416b10: 48 8b 6f 28 mov 0x28(%rdi),%rbp + 416b14: 48 39 6f 10 cmp %rbp,0x10(%rdi) + 416b18: b9 01 00 00 00 mov $0x1,%ecx + 416b1d: 48 0f 43 6f 10 cmovae 0x10(%rdi),%rbp + 416b22: 48 8b 47 18 mov 0x18(%rdi),%rax + 416b26: 48 29 c5 sub %rax,%rbp + 416b29: 41 83 fd 01 cmp $0x1,%r13d + 416b2d: 74 49 je 416b78 <_IO_str_seekoff+0x148> + 416b2f: 49 8d 14 2c lea (%r12,%rbp,1),%rdx + 416b33: 41 83 fd 02 cmp $0x2,%r13d + 416b37: 4c 0f 44 e2 cmove %rdx,%r12 + 416b3b: 4d 85 e4 test %r12,%r12 + 416b3e: 78 75 js 416bb5 <_IO_str_seekoff+0x185> + 416b40: 49 39 ec cmp %rbp,%r12 + 416b43: 0f 8f 7f 00 00 00 jg 416bc8 <_IO_str_seekoff+0x198> + 416b49: 4a 8d 14 20 lea (%rax,%r12,1),%rdx + 416b4d: 48 01 e8 add %rbp,%rax + 416b50: 83 e1 02 and $0x2,%ecx + 416b53: 48 89 43 10 mov %rax,0x10(%rbx) + 416b57: 4c 89 e0 mov %r12,%rax + 416b5a: 48 89 53 08 mov %rdx,0x8(%rbx) + 416b5e: eb 93 jmp 416af3 <_IO_str_seekoff+0xc3> + 416b60: 48 8b 43 08 mov 0x8(%rbx),%rax + 416b64: 48 2b 43 18 sub 0x18(%rbx),%rax + 416b68: 48 83 c4 18 add $0x18,%rsp + 416b6c: 5b pop %rbx + 416b6d: 5d pop %rbp + 416b6e: 41 5c pop %r12 + 416b70: 41 5d pop %r13 + 416b72: c3 retq + 416b73: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 416b78: 48 8b 53 08 mov 0x8(%rbx),%rdx + 416b7c: 48 29 c2 sub %rax,%rdx + 416b7f: 49 01 d4 add %rdx,%r12 + 416b82: eb b7 jmp 416b3b <_IO_str_seekoff+0x10b> + 416b84: 0f 1f 40 00 nopl 0x0(%rax) + 416b88: 48 8b 43 28 mov 0x28(%rbx),%rax + 416b8c: 48 2b 43 20 sub 0x20(%rbx),%rax + 416b90: 49 01 c4 add %rax,%r12 + 416b93: e9 ea fe ff ff jmpq 416a82 <_IO_str_seekoff+0x52> + 416b98: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 416b9f: 00 + 416ba0: 31 d2 xor %edx,%edx + 416ba2: 4c 89 e6 mov %r12,%rsi + 416ba5: 48 89 df mov %rbx,%rdi + 416ba8: e8 03 fd ff ff callq 4168b0 + 416bad: 85 c0 test %eax,%eax + 416baf: 0f 84 df fe ff ff je 416a94 <_IO_str_seekoff+0x64> + 416bb5: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax + 416bbc: e9 ff fe ff ff jmpq 416ac0 <_IO_str_seekoff+0x90> + 416bc1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 416bc8: ba 01 00 00 00 mov $0x1,%edx + 416bcd: 4c 89 e6 mov %r12,%rsi + 416bd0: 48 89 df mov %rbx,%rdi + 416bd3: 89 4c 24 0c mov %ecx,0xc(%rsp) + 416bd7: e8 d4 fc ff ff callq 4168b0 + 416bdc: 85 c0 test %eax,%eax + 416bde: 75 d5 jne 416bb5 <_IO_str_seekoff+0x185> + 416be0: 48 8b 43 18 mov 0x18(%rbx),%rax + 416be4: 8b 4c 24 0c mov 0xc(%rsp),%ecx + 416be8: e9 5c ff ff ff jmpq 416b49 <_IO_str_seekoff+0x119> + 416bed: 0f 1f 00 nopl (%rax) + +0000000000416bf0 <_IO_str_pbackfail>: + 416bf0: f6 07 08 testb $0x8,(%rdi) + 416bf3: 74 05 je 416bfa <_IO_str_pbackfail+0xa> + 416bf5: 83 fe ff cmp $0xffffffff,%esi + 416bf8: 75 06 jne 416c00 <_IO_str_pbackfail+0x10> + 416bfa: e9 11 f8 ff ff jmpq 416410 <_IO_default_pbackfail> + 416bff: 90 nop + 416c00: b8 ff ff ff ff mov $0xffffffff,%eax + 416c05: c3 retq + 416c06: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 416c0d: 00 00 00 + +0000000000416c10 <_IO_str_finish>: + 416c10: 53 push %rbx + 416c11: 48 89 fb mov %rdi,%rbx + 416c14: 48 8b 7f 38 mov 0x38(%rdi),%rdi + 416c18: 48 85 ff test %rdi,%rdi + 416c1b: 74 0b je 416c28 <_IO_str_finish+0x18> + 416c1d: f6 03 01 testb $0x1,(%rbx) + 416c20: 75 06 jne 416c28 <_IO_str_finish+0x18> + 416c22: ff 93 e8 00 00 00 callq *0xe8(%rbx) + 416c28: 48 c7 43 38 00 00 00 movq $0x0,0x38(%rbx) + 416c2f: 00 + 416c30: 48 89 df mov %rbx,%rdi + 416c33: 31 f6 xor %esi,%esi + 416c35: 5b pop %rbx + 416c36: e9 d5 e9 ff ff jmpq 415610 <_IO_default_finish> + 416c3b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + +0000000000416c40 <_IO_str_init_static_internal>: + 416c40: 41 55 push %r13 + 416c42: 41 54 push %r12 + 416c44: 49 89 cd mov %rcx,%r13 + 416c47: 55 push %rbp + 416c48: 53 push %rbx + 416c49: 49 89 f4 mov %rsi,%r12 + 416c4c: 48 89 fb mov %rdi,%rbx + 416c4f: 48 83 ec 08 sub $0x8,%rsp + 416c53: 48 85 d2 test %rdx,%rdx + 416c56: 75 58 jne 416cb0 <_IO_str_init_static_internal+0x70> + 416c58: 31 f6 xor %esi,%esi + 416c5a: 4c 89 e7 mov %r12,%rdi + 416c5d: e8 6e 5d 01 00 callq 42c9d0 <__rawmemchr> + 416c62: 48 89 c5 mov %rax,%rbp + 416c65: 31 c9 xor %ecx,%ecx + 416c67: 48 89 ea mov %rbp,%rdx + 416c6a: 4c 89 e6 mov %r12,%rsi + 416c6d: 48 89 df mov %rbx,%rdi + 416c70: e8 2b e1 ff ff callq 414da0 <_IO_setb> + 416c75: 4d 85 ed test %r13,%r13 + 416c78: 4c 89 63 20 mov %r12,0x20(%rbx) + 416c7c: 4c 89 63 18 mov %r12,0x18(%rbx) + 416c80: 4c 89 63 08 mov %r12,0x8(%rbx) + 416c84: 74 42 je 416cc8 <_IO_str_init_static_internal+0x88> + 416c86: 4c 89 6b 28 mov %r13,0x28(%rbx) + 416c8a: 48 89 6b 30 mov %rbp,0x30(%rbx) + 416c8e: 4c 89 6b 10 mov %r13,0x10(%rbx) + 416c92: 48 c7 83 e0 00 00 00 movq $0x0,0xe0(%rbx) + 416c99: 00 00 00 00 + 416c9d: 48 83 c4 08 add $0x8,%rsp + 416ca1: 5b pop %rbx + 416ca2: 5d pop %rbp + 416ca3: 41 5c pop %r12 + 416ca5: 41 5d pop %r13 + 416ca7: c3 retq + 416ca8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 416caf: 00 + 416cb0: 48 01 f2 add %rsi,%rdx + 416cb3: 48 c7 c5 ff ff ff ff mov $0xffffffffffffffff,%rbp + 416cba: 48 39 d6 cmp %rdx,%rsi + 416cbd: 48 0f 42 ea cmovb %rdx,%rbp + 416cc1: eb a2 jmp 416c65 <_IO_str_init_static_internal+0x25> + 416cc3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 416cc8: 4c 89 63 28 mov %r12,0x28(%rbx) + 416ccc: 4c 89 63 30 mov %r12,0x30(%rbx) + 416cd0: 48 89 6b 10 mov %rbp,0x10(%rbx) + 416cd4: eb bc jmp 416c92 <_IO_str_init_static_internal+0x52> + 416cd6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 416cdd: 00 00 00 + +0000000000416ce0 <_IO_str_init_static>: + 416ce0: 41 55 push %r13 + 416ce2: 41 54 push %r12 + 416ce4: 49 89 cd mov %rcx,%r13 + 416ce7: 55 push %rbp + 416ce8: 53 push %rbx + 416ce9: bb ff ff ff ff mov $0xffffffff,%ebx + 416cee: 48 89 fd mov %rdi,%rbp + 416cf1: 49 89 f4 mov %rsi,%r12 + 416cf4: 48 83 ec 08 sub $0x8,%rsp + 416cf8: 85 d2 test %edx,%edx + 416cfa: 0f 48 d3 cmovs %ebx,%edx + 416cfd: 48 63 d2 movslq %edx,%rdx + 416d00: 48 85 d2 test %rdx,%rdx + 416d03: 75 53 jne 416d58 <_IO_str_init_static+0x78> + 416d05: 31 f6 xor %esi,%esi + 416d07: 4c 89 e7 mov %r12,%rdi + 416d0a: e8 c1 5c 01 00 callq 42c9d0 <__rawmemchr> + 416d0f: 48 89 c3 mov %rax,%rbx + 416d12: 31 c9 xor %ecx,%ecx + 416d14: 48 89 da mov %rbx,%rdx + 416d17: 4c 89 e6 mov %r12,%rsi + 416d1a: 48 89 ef mov %rbp,%rdi + 416d1d: e8 7e e0 ff ff callq 414da0 <_IO_setb> + 416d22: 4d 85 ed test %r13,%r13 + 416d25: 4c 89 65 20 mov %r12,0x20(%rbp) + 416d29: 4c 89 65 18 mov %r12,0x18(%rbp) + 416d2d: 4c 89 65 08 mov %r12,0x8(%rbp) + 416d31: 74 3d je 416d70 <_IO_str_init_static+0x90> + 416d33: 4c 89 6d 28 mov %r13,0x28(%rbp) + 416d37: 48 89 5d 30 mov %rbx,0x30(%rbp) + 416d3b: 4c 89 6d 10 mov %r13,0x10(%rbp) + 416d3f: 48 c7 85 e0 00 00 00 movq $0x0,0xe0(%rbp) + 416d46: 00 00 00 00 + 416d4a: 48 83 c4 08 add $0x8,%rsp + 416d4e: 5b pop %rbx + 416d4f: 5d pop %rbp + 416d50: 41 5c pop %r12 + 416d52: 41 5d pop %r13 + 416d54: c3 retq + 416d55: 0f 1f 00 nopl (%rax) + 416d58: 48 01 f2 add %rsi,%rdx + 416d5b: 48 c7 c3 ff ff ff ff mov $0xffffffffffffffff,%rbx + 416d62: 48 39 d6 cmp %rdx,%rsi + 416d65: 48 0f 42 da cmovb %rdx,%rbx + 416d69: eb a7 jmp 416d12 <_IO_str_init_static+0x32> + 416d6b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 416d70: 4c 89 65 28 mov %r12,0x28(%rbp) + 416d74: 4c 89 65 30 mov %r12,0x30(%rbp) + 416d78: 48 89 5d 10 mov %rbx,0x10(%rbp) + 416d7c: eb c1 jmp 416d3f <_IO_str_init_static+0x5f> + 416d7e: 66 90 xchg %ax,%ax + +0000000000416d80 <_IO_str_init_readonly>: + 416d80: 41 54 push %r12 + 416d82: 85 d2 test %edx,%edx + 416d84: 55 push %rbp + 416d85: 53 push %rbx + 416d86: bb ff ff ff ff mov $0xffffffff,%ebx + 416d8b: 48 89 fd mov %rdi,%rbp + 416d8e: 0f 48 d3 cmovs %ebx,%edx + 416d91: 49 89 f4 mov %rsi,%r12 + 416d94: 48 63 d2 movslq %edx,%rdx + 416d97: 48 85 d2 test %rdx,%rdx + 416d9a: 75 4c jne 416de8 <_IO_str_init_readonly+0x68> + 416d9c: 31 f6 xor %esi,%esi + 416d9e: 4c 89 e7 mov %r12,%rdi + 416da1: e8 2a 5c 01 00 callq 42c9d0 <__rawmemchr> + 416da6: 48 89 c3 mov %rax,%rbx + 416da9: 48 89 da mov %rbx,%rdx + 416dac: 4c 89 e6 mov %r12,%rsi + 416daf: 48 89 ef mov %rbp,%rdi + 416db2: 31 c9 xor %ecx,%ecx + 416db4: e8 e7 df ff ff callq 414da0 <_IO_setb> + 416db9: 83 4d 00 08 orl $0x8,0x0(%rbp) + 416dbd: 4c 89 65 20 mov %r12,0x20(%rbp) + 416dc1: 4c 89 65 18 mov %r12,0x18(%rbp) + 416dc5: 4c 89 65 08 mov %r12,0x8(%rbp) + 416dc9: 4c 89 65 28 mov %r12,0x28(%rbp) + 416dcd: 4c 89 65 30 mov %r12,0x30(%rbp) + 416dd1: 48 89 5d 10 mov %rbx,0x10(%rbp) + 416dd5: 48 c7 85 e0 00 00 00 movq $0x0,0xe0(%rbp) + 416ddc: 00 00 00 00 + 416de0: 5b pop %rbx + 416de1: 5d pop %rbp + 416de2: 41 5c pop %r12 + 416de4: c3 retq + 416de5: 0f 1f 00 nopl (%rax) + 416de8: 48 01 f2 add %rsi,%rdx + 416deb: 48 c7 c3 ff ff ff ff mov $0xffffffffffffffff,%rbx + 416df2: 48 39 d6 cmp %rdx,%rsi + 416df5: 48 0f 42 da cmovb %rdx,%rbx + 416df9: eb ae jmp 416da9 <_IO_str_init_readonly+0x29> + 416dfb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + +0000000000416e00 <_IO_str_count>: + 416e00: 48 8b 47 28 mov 0x28(%rdi),%rax + 416e04: 48 39 47 10 cmp %rax,0x10(%rdi) + 416e08: 48 0f 43 47 10 cmovae 0x10(%rdi),%rax + 416e0d: 48 2b 47 18 sub 0x18(%rdi),%rax + 416e11: c3 retq + 416e12: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 416e19: 00 00 00 + 416e1c: 0f 1f 40 00 nopl 0x0(%rax) + +0000000000416e20 <__malloc_assert>: + 416e20: 48 83 ec 10 sub $0x10,%rsp + 416e24: 41 89 d1 mov %edx,%r9d + 416e27: 48 8b 15 b2 42 2b 00 mov 0x2b42b2(%rip),%rdx # 6cb0e0 <__progname> + 416e2e: 41 bb 25 67 4b 00 mov $0x4b6725,%r11d + 416e34: 41 ba 6f 52 4b 00 mov $0x4b526f,%r10d + 416e3a: 48 85 c9 test %rcx,%rcx + 416e3d: 49 89 f0 mov %rsi,%r8 + 416e40: 48 89 c8 mov %rcx,%rax + 416e43: 4c 89 de mov %r11,%rsi + 416e46: 49 0f 45 f2 cmovne %r10,%rsi + 416e4a: 49 0f 44 c3 cmove %r11,%rax + 416e4e: 80 3a 00 cmpb $0x0,(%rdx) + 416e51: 4c 89 d9 mov %r11,%rcx + 416e54: 57 push %rdi + 416e55: 56 push %rsi + 416e56: 50 push %rax + 416e57: be 20 23 4a 00 mov $0x4a2320,%esi + 416e5c: 49 0f 45 ca cmovne %r10,%rcx + 416e60: 31 ff xor %edi,%edi + 416e62: 31 c0 xor %eax,%eax + 416e64: e8 27 85 ff ff callq 40f390 <__fxprintf> + 416e69: 48 8b 3d c8 38 2b 00 mov 0x2b38c8(%rip),%rdi # 6ca738 <_IO_stderr> + 416e70: 48 83 c4 20 add $0x20,%rsp + 416e74: e8 c7 88 ff ff callq 40f740 <_IO_fflush> + 416e79: e8 82 6d ff ff callq 40dc00 + 416e7e: 66 90 xchg %ax,%ax + +0000000000416e80 : + 416e80: 48 01 fe add %rdi,%rsi + 416e83: 41 54 push %r12 + 416e85: 48 8b 05 f4 42 2b 00 mov 0x2b42f4(%rip),%rax # 6cb180 <_dl_pagesize> + 416e8c: 48 81 fe ff 7f 00 00 cmp $0x7fff,%rsi + 416e93: 55 push %rbp + 416e94: 53 push %rbx + 416e95: 0f 86 f5 00 00 00 jbe 416f90 + 416e9b: 48 81 fe 00 00 00 04 cmp $0x4000000,%rsi + 416ea2: 0f 87 f8 00 00 00 ja 416fa0 + 416ea8: 48 8b 3d 61 57 2b 00 mov 0x2b5761(%rip),%rdi # 6cc610 + 416eaf: 48 8d 6c 06 ff lea -0x1(%rsi,%rax,1),%rbp + 416eb4: 48 f7 d8 neg %rax + 416eb7: 48 21 c5 and %rax,%rbp + 416eba: 48 85 ff test %rdi,%rdi + 416ebd: 74 6e je 416f2d + 416ebf: 45 31 c9 xor %r9d,%r9d + 416ec2: 31 d2 xor %edx,%edx + 416ec4: 41 b8 ff ff ff ff mov $0xffffffff,%r8d + 416eca: b9 22 40 00 00 mov $0x4022,%ecx + 416ecf: be 00 00 00 04 mov $0x4000000,%esi + 416ed4: e8 17 8d 02 00 callq 43fbf0 <__mmap> + 416ed9: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 416edd: 48 89 c3 mov %rax,%rbx + 416ee0: 48 c7 05 25 57 2b 00 movq $0x0,0x2b5725(%rip) # 6cc610 + 416ee7: 00 00 00 00 + 416eeb: 74 40 je 416f2d + 416eed: a9 ff ff ff 03 test $0x3ffffff,%eax + 416ef2: 75 2c jne 416f20 + 416ef4: ba 03 00 00 00 mov $0x3,%edx + 416ef9: 48 89 ee mov %rbp,%rsi + 416efc: 48 89 df mov %rbx,%rdi + 416eff: e8 cc 8d 02 00 callq 43fcd0 <__mprotect> + 416f04: 85 c0 test %eax,%eax + 416f06: 0f 85 fc 00 00 00 jne 417008 + 416f0c: 48 89 6b 10 mov %rbp,0x10(%rbx) + 416f10: 48 89 6b 18 mov %rbp,0x18(%rbx) + 416f14: 90 nop + 416f15: 48 89 d8 mov %rbx,%rax + 416f18: 5b pop %rbx + 416f19: 5d pop %rbp + 416f1a: 41 5c pop %r12 + 416f1c: c3 retq + 416f1d: 0f 1f 00 nopl (%rax) + 416f20: be 00 00 00 04 mov $0x4000000,%esi + 416f25: 48 89 c7 mov %rax,%rdi + 416f28: e8 83 8d 02 00 callq 43fcb0 <__munmap> + 416f2d: 45 31 c9 xor %r9d,%r9d + 416f30: 31 d2 xor %edx,%edx + 416f32: 31 ff xor %edi,%edi + 416f34: 41 b8 ff ff ff ff mov $0xffffffff,%r8d + 416f3a: b9 22 40 00 00 mov $0x4022,%ecx + 416f3f: be 00 00 00 08 mov $0x8000000,%esi + 416f44: e8 a7 8c 02 00 callq 43fbf0 <__mmap> + 416f49: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 416f4d: 0f 84 85 00 00 00 je 416fd8 + 416f53: 48 8d 98 ff ff ff 03 lea 0x3ffffff(%rax),%rbx + 416f5a: 48 81 e3 00 00 00 fc and $0xfffffffffc000000,%rbx + 416f61: 49 89 dc mov %rbx,%r12 + 416f64: 49 29 c4 sub %rax,%r12 + 416f67: 75 57 jne 416fc0 + 416f69: 48 8d bb 00 00 00 04 lea 0x4000000(%rbx),%rdi + 416f70: 48 89 3d 99 56 2b 00 mov %rdi,0x2b5699(%rip) # 6cc610 + 416f77: be 00 00 00 04 mov $0x4000000,%esi + 416f7c: 4c 29 e6 sub %r12,%rsi + 416f7f: e8 2c 8d 02 00 callq 43fcb0 <__munmap> + 416f84: e9 6b ff ff ff jmpq 416ef4 + 416f89: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 416f90: be 00 80 00 00 mov $0x8000,%esi + 416f95: e9 0e ff ff ff jmpq 416ea8 + 416f9a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 416fa0: 48 81 ff 00 00 00 04 cmp $0x4000000,%rdi + 416fa7: be 00 00 00 04 mov $0x4000000,%esi + 416fac: 0f 86 f6 fe ff ff jbe 416ea8 + 416fb2: 31 c0 xor %eax,%eax + 416fb4: e9 5f ff ff ff jmpq 416f18 + 416fb9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 416fc0: 48 89 c7 mov %rax,%rdi + 416fc3: 4c 89 e6 mov %r12,%rsi + 416fc6: e8 e5 8c 02 00 callq 43fcb0 <__munmap> + 416fcb: 48 8d bb 00 00 00 04 lea 0x4000000(%rbx),%rdi + 416fd2: eb a3 jmp 416f77 + 416fd4: 0f 1f 40 00 nopl 0x0(%rax) + 416fd8: 45 31 c9 xor %r9d,%r9d + 416fdb: 31 d2 xor %edx,%edx + 416fdd: 31 ff xor %edi,%edi + 416fdf: 41 89 c0 mov %eax,%r8d + 416fe2: b9 22 40 00 00 mov $0x4022,%ecx + 416fe7: be 00 00 00 04 mov $0x4000000,%esi + 416fec: e8 ff 8b 02 00 callq 43fbf0 <__mmap> + 416ff1: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 416ff5: 48 89 c3 mov %rax,%rbx + 416ff8: 74 b8 je 416fb2 + 416ffa: a9 ff ff ff 03 test $0x3ffffff,%eax + 416fff: 0f 84 ef fe ff ff je 416ef4 + 417005: 0f 1f 00 nopl (%rax) + 417008: be 00 00 00 04 mov $0x4000000,%esi + 41700d: 48 89 df mov %rbx,%rdi + 417010: e8 9b 8c 02 00 callq 43fcb0 <__munmap> + 417015: 31 c0 xor %eax,%eax + 417017: e9 fc fe ff ff jmpq 416f18 + 41701c: 0f 1f 40 00 nopl 0x0(%rax) + +0000000000417020 : + 417020: 41 55 push %r13 + 417022: 41 54 push %r12 + 417024: 55 push %rbp + 417025: 53 push %rbx + 417026: 48 83 ec 08 sub $0x8,%rsp + 41702a: 48 8b 57 08 mov 0x8(%rdi),%rdx + 41702e: 48 8b 05 4b 41 2b 00 mov 0x2b414b(%rip),%rax # 6cb180 <_dl_pagesize> + 417035: 48 8b 2f mov (%rdi),%rbp + 417038: 49 89 d5 mov %rdx,%r13 + 41703b: 49 83 e5 f8 and $0xfffffffffffffff8,%r13 + 41703f: 83 e2 02 and $0x2,%edx + 417042: 0f 84 c5 00 00 00 je 41710d + 417048: 4e 8d 64 2d 00 lea 0x0(%rbp,%r13,1),%r12 + 41704d: 48 8d 50 ff lea -0x1(%rax),%rdx + 417051: 4c 85 e2 test %r12,%rdx + 417054: 0f 85 9a 00 00 00 jne 4170f4 + 41705a: 48 8d 5c 28 07 lea 0x7(%rax,%rbp,1),%rbx + 41705f: 48 f7 d8 neg %rax + 417062: 48 01 f3 add %rsi,%rbx + 417065: 48 21 c3 and %rax,%rbx + 417068: 49 39 dc cmp %rbx,%r12 + 41706b: 74 6f je 4170dc + 41706d: 48 29 ef sub %rbp,%rdi + 417070: 31 c0 xor %eax,%eax + 417072: b9 01 00 00 00 mov $0x1,%ecx + 417077: 48 89 da mov %rbx,%rdx + 41707a: 4c 89 e6 mov %r12,%rsi + 41707d: e8 ce b4 02 00 callq 442550 <__mremap> + 417082: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 417086: 74 68 je 4170f0 + 417088: 48 8d 3c 28 lea (%rax,%rbp,1),%rdi + 41708c: 40 f6 c7 0f test $0xf,%dil + 417090: 0f 85 a9 00 00 00 jne 41713f + 417096: 48 3b 2f cmp (%rdi),%rbp + 417099: 0f 85 87 00 00 00 jne 417126 + 41709f: 48 89 d8 mov %rbx,%rax + 4170a2: 48 29 e8 sub %rbp,%rax + 4170a5: 48 83 c8 02 or $0x2,%rax + 4170a9: 48 89 47 08 mov %rax,0x8(%rdi) + 4170ad: 48 89 d8 mov %rbx,%rax + 4170b0: 4c 29 e8 sub %r13,%rax + 4170b3: 48 29 e8 sub %rbp,%rax + 4170b6: f0 48 0f c1 05 19 37 lock xadd %rax,0x2b3719(%rip) # 6ca7d8 + 4170bd: 2b 00 + 4170bf: 4c 29 e3 sub %r12,%rbx + 4170c2: 48 01 c3 add %rax,%rbx + 4170c5: 48 8b 05 14 37 2b 00 mov 0x2b3714(%rip),%rax # 6ca7e0 + 4170cc: 48 39 c3 cmp %rax,%rbx + 4170cf: 76 0b jbe 4170dc + 4170d1: f0 48 0f b1 1d 06 37 lock cmpxchg %rbx,0x2b3706(%rip) # 6ca7e0 + 4170d8: 2b 00 + 4170da: 75 e9 jne 4170c5 + 4170dc: 48 89 f8 mov %rdi,%rax + 4170df: 48 83 c4 08 add $0x8,%rsp + 4170e3: 5b pop %rbx + 4170e4: 5d pop %rbp + 4170e5: 41 5c pop %r12 + 4170e7: 41 5d pop %r13 + 4170e9: c3 retq + 4170ea: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4170f0: 31 c0 xor %eax,%eax + 4170f2: eb eb jmp 4170df + 4170f4: b9 68 2e 4a 00 mov $0x4a2e68,%ecx + 4170f9: ba 34 0b 00 00 mov $0xb34,%edx + 4170fe: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 417103: bf 48 23 4a 00 mov $0x4a2348,%edi + 417108: e8 13 fd ff ff callq 416e20 <__malloc_assert> + 41710d: b9 68 2e 4a 00 mov $0x4a2e68,%ecx + 417112: ba 33 0b 00 00 mov $0xb33,%edx + 417117: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 41711c: bf d1 1f 4a 00 mov $0x4a1fd1,%edi + 417121: e8 fa fc ff ff callq 416e20 <__malloc_assert> + 417126: b9 68 2e 4a 00 mov $0x4a2e68,%ecx + 41712b: ba 47 0b 00 00 mov $0xb47,%edx + 417130: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 417135: bf 01 20 4a 00 mov $0x4a2001,%edi + 41713a: e8 e1 fc ff ff callq 416e20 <__malloc_assert> + 41713f: b9 68 2e 4a 00 mov $0x4a2e68,%ecx + 417144: ba 45 0b 00 00 mov $0xb45,%edx + 417149: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 41714e: bf e6 1f 4a 00 mov $0x4a1fe6,%edi + 417153: e8 c8 fc ff ff callq 416e20 <__malloc_assert> + 417158: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 41715f: 00 + +0000000000417160 : + 417160: 48 83 ec 08 sub $0x8,%rsp + 417164: 48 8b 15 bd 54 2b 00 mov 0x2b54bd(%rip),%rdx # 6cc628 + 41716b: 49 c7 c1 d8 ff ff ff mov $0xffffffffffffffd8,%r9 + 417172: 48 85 d2 test %rdx,%rdx + 417175: 64 4d 8b 01 mov %fs:(%r9),%r8 + 417179: 0f 84 05 01 00 00 je 417284 + 41717f: be 01 00 00 00 mov $0x1,%esi + 417184: 31 c0 xor %eax,%eax + 417186: 83 3d 2f 60 2b 00 00 cmpl $0x0,0x2b602f(%rip) # 6cd1bc <__libc_multiple_threads> + 41718d: 74 0c je 41719b + 41718f: f0 0f b1 35 99 54 2b lock cmpxchg %esi,0x2b5499(%rip) # 6cc630 + 417196: 00 + 417197: 75 0b jne 4171a4 + 417199: eb 23 jmp 4171be + 41719b: 0f b1 35 8e 54 2b 00 cmpxchg %esi,0x2b548e(%rip) # 6cc630 + 4171a2: 74 1a je 4171be + 4171a4: 48 8d 3d 85 54 2b 00 lea 0x2b5485(%rip),%rdi # 6cc630 + 4171ab: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 4171b2: e8 19 b4 02 00 callq 4425d0 <__lll_lock_wait_private> + 4171b7: 48 81 c4 80 00 00 00 add $0x80,%rsp + 4171be: 48 8b 15 63 54 2b 00 mov 0x2b5463(%rip),%rdx # 6cc628 + 4171c5: 48 85 d2 test %rdx,%rdx + 4171c8: 74 47 je 417211 + 4171ca: 48 83 ba 78 08 00 00 cmpq $0x0,0x878(%rdx) + 4171d1: 00 + 4171d2: 48 8b 82 70 08 00 00 mov 0x870(%rdx),%rax + 4171d9: 48 89 05 48 54 2b 00 mov %rax,0x2b5448(%rip) # 6cc628 + 4171e0: 0f 85 a6 00 00 00 jne 41728c + 4171e6: 4d 85 c0 test %r8,%r8 + 4171e9: 48 c7 82 78 08 00 00 movq $0x1,0x878(%rdx) + 4171f0: 01 00 00 00 + 4171f4: 74 1b je 417211 + 4171f6: 49 8b 80 78 08 00 00 mov 0x878(%r8),%rax + 4171fd: 48 85 c0 test %rax,%rax + 417200: 0f 84 9f 00 00 00 je 4172a5 + 417206: 48 83 e8 01 sub $0x1,%rax + 41720a: 49 89 80 78 08 00 00 mov %rax,0x878(%r8) + 417211: 83 3d a4 5f 2b 00 00 cmpl $0x0,0x2b5fa4(%rip) # 6cd1bc <__libc_multiple_threads> + 417218: 74 0b je 417225 + 41721a: f0 ff 0d 0f 54 2b 00 lock decl 0x2b540f(%rip) # 6cc630 + 417221: 75 0a jne 41722d + 417223: eb 22 jmp 417247 + 417225: ff 0d 05 54 2b 00 decl 0x2b5405(%rip) # 6cc630 + 41722b: 74 1a je 417247 + 41722d: 48 8d 3d fc 53 2b 00 lea 0x2b53fc(%rip),%rdi # 6cc630 + 417234: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41723b: e8 c0 b3 02 00 callq 442600 <__lll_unlock_wake_private> + 417240: 48 81 c4 80 00 00 00 add $0x80,%rsp + 417247: 48 85 d2 test %rdx,%rdx + 41724a: 74 38 je 417284 + 41724c: 90 nop + 41724d: be 01 00 00 00 mov $0x1,%esi + 417252: 31 c0 xor %eax,%eax + 417254: 83 3d 61 5f 2b 00 00 cmpl $0x0,0x2b5f61(%rip) # 6cd1bc <__libc_multiple_threads> + 41725b: 74 08 je 417265 + 41725d: f0 0f b1 32 lock cmpxchg %esi,(%rdx) + 417261: 75 07 jne 41726a + 417263: eb 1b jmp 417280 + 417265: 0f b1 32 cmpxchg %esi,(%rdx) + 417268: 74 16 je 417280 + 41726a: 48 8d 3a lea (%rdx),%rdi + 41726d: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 417274: e8 57 b3 02 00 callq 4425d0 <__lll_lock_wait_private> + 417279: 48 81 c4 80 00 00 00 add $0x80,%rsp + 417280: 64 49 89 11 mov %rdx,%fs:(%r9) + 417284: 48 89 d0 mov %rdx,%rax + 417287: 48 83 c4 08 add $0x8,%rsp + 41728b: c3 retq + 41728c: b9 38 2e 4a 00 mov $0x4a2e38,%ecx + 417291: ba d4 02 00 00 mov $0x2d4,%edx + 417296: be a8 1f 4a 00 mov $0x4a1fa8,%esi + 41729b: bf 1a 20 4a 00 mov $0x4a201a,%edi + 4172a0: e8 7b fb ff ff callq 416e20 <__malloc_assert> + 4172a5: e8 29 92 fe ff callq 4004d3 + 4172aa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + +00000000004172b0 : + 4172b0: 41 56 push %r14 + 4172b2: 41 55 push %r13 + 4172b4: 41 54 push %r12 + 4172b6: 55 push %rbp + 4172b7: 49 89 f4 mov %rsi,%r12 + 4172ba: 53 push %rbx + 4172bb: 89 fb mov %edi,%ebx + 4172bd: 48 89 d7 mov %rdx,%rdi + 4172c0: 48 83 ec 20 sub $0x20,%rsp + 4172c4: 48 85 c9 test %rcx,%rcx + 4172c7: 74 04 je 4172cd + 4172c9: 83 49 04 04 orl $0x4,0x4(%rcx) + 4172cd: 89 d8 mov %ebx,%eax + 4172cf: 83 e0 05 and $0x5,%eax + 4172d2: 83 f8 05 cmp $0x5,%eax + 4172d5: 0f 84 a5 00 00 00 je 417380 + 4172db: f6 c3 01 test $0x1,%bl + 4172de: 75 20 jne 417300 + 4172e0: 83 e3 02 and $0x2,%ebx + 4172e3: 0f 85 b0 00 00 00 jne 417399 + 4172e9: 48 83 c4 20 add $0x20,%rsp + 4172ed: 5b pop %rbx + 4172ee: 5d pop %rbp + 4172ef: 41 5c pop %r12 + 4172f1: 41 5d pop %r13 + 4172f3: 41 5e pop %r14 + 4172f5: c3 retq + 4172f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4172fd: 00 00 00 + 417300: 48 8d 74 24 10 lea 0x10(%rsp),%rsi + 417305: 31 c9 xor %ecx,%ecx + 417307: ba 10 00 00 00 mov $0x10,%edx + 41730c: c6 44 24 10 00 movb $0x0,0x10(%rsp) + 417311: e8 9a ab 03 00 callq 451eb0 <_itoa_word> + 417316: 48 39 e0 cmp %rsp,%rax + 417319: 48 89 c5 mov %rax,%rbp + 41731c: 76 25 jbe 417343 + 41731e: 48 89 c2 mov %rax,%rdx + 417321: 48 89 c7 mov %rax,%rdi + 417324: be 30 00 00 00 mov $0x30,%esi + 417329: 48 29 e2 sub %rsp,%rdx + 41732c: 4c 8d 70 ff lea -0x1(%rax),%r14 + 417330: 48 29 d7 sub %rdx,%rdi + 417333: e8 18 90 fe ff callq 400350 <__rela_iplt_end+0x88> + 417338: 48 8d 44 24 ff lea -0x1(%rsp),%rax + 41733d: 4c 29 f0 sub %r14,%rax + 417340: 48 01 c5 add %rax,%rbp + 417343: 48 8b 05 76 5f 2b 00 mov 0x2b5f76(%rip),%rax # 6cd2c0 <__libc_argv> + 41734a: ba 38 20 4a 00 mov $0x4a2038,%edx + 41734f: 49 89 e8 mov %rbp,%r8 + 417352: 4c 89 e1 mov %r12,%rcx + 417355: be a8 23 4a 00 mov $0x4a23a8,%esi + 41735a: 48 8b 00 mov (%rax),%rax + 41735d: 48 85 c0 test %rax,%rax + 417360: 48 0f 45 d0 cmovne %rax,%rdx + 417364: 83 e3 02 and $0x2,%ebx + 417367: 31 c0 xor %eax,%eax + 417369: 89 df mov %ebx,%edi + 41736b: e8 50 a2 ff ff callq 4115c0 <__libc_message> + 417370: 48 83 c4 20 add $0x20,%rsp + 417374: 5b pop %rbx + 417375: 5d pop %rbp + 417376: 41 5c pop %r12 + 417378: 41 5d pop %r13 + 41737a: 41 5e pop %r14 + 41737c: c3 retq + 41737d: 0f 1f 00 nopl (%rax) + 417380: 83 e3 02 and $0x2,%ebx + 417383: 4c 89 e2 mov %r12,%rdx + 417386: be 3c ca 4b 00 mov $0x4bca3c,%esi + 41738b: 89 df mov %ebx,%edi + 41738d: 31 c0 xor %eax,%eax + 41738f: e8 2c a2 ff ff callq 4115c0 <__libc_message> + 417394: e9 50 ff ff ff jmpq 4172e9 + 417399: e8 62 68 ff ff callq 40dc00 + 41739e: 66 90 xchg %ax,%ax + +00000000004173a0 : + 4173a0: 48 8b 06 mov (%rsi),%rax + 4173a3: 41 56 push %r14 + 4173a5: 41 55 push %r13 + 4173a7: 41 54 push %r12 + 4173a9: 55 push %rbp + 4173aa: 53 push %rbx + 4173ab: 48 8b 68 08 mov 0x8(%rax),%rbp + 4173af: 48 83 e5 f8 and $0xfffffffffffffff8,%rbp + 4173b3: 48 8d 45 df lea -0x21(%rbp),%rax + 4173b7: 48 39 f8 cmp %rdi,%rax + 4173ba: 76 12 jbe 4173ce + 4173bc: 48 8b 1d bd 3d 2b 00 mov 0x2b3dbd(%rip),%rbx # 6cb180 <_dl_pagesize> + 4173c3: 48 29 f8 sub %rdi,%rax + 4173c6: 48 f7 db neg %rbx + 4173c9: 48 21 c3 and %rax,%rbx + 4173cc: 75 12 jne 4173e0 + 4173ce: 31 c0 xor %eax,%eax + 4173d0: 5b pop %rbx + 4173d1: 5d pop %rbp + 4173d2: 41 5c pop %r12 + 4173d4: 41 5d pop %r13 + 4173d6: 41 5e pop %r14 + 4173d8: c3 retq + 4173d9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4173e0: 49 89 f4 mov %rsi,%r12 + 4173e3: 31 ff xor %edi,%edi + 4173e5: 49 89 d5 mov %rdx,%r13 + 4173e8: ff 15 a2 3c 2b 00 callq *0x2b3ca2(%rip) # 6cb090 <__morecore> + 4173ee: 49 89 c6 mov %rax,%r14 + 4173f1: 48 89 e8 mov %rbp,%rax + 4173f4: 49 03 04 24 add (%r12),%rax + 4173f8: 49 39 c6 cmp %rax,%r14 + 4173fb: 75 d1 jne 4173ce + 4173fd: 48 89 df mov %rbx,%rdi + 417400: 48 f7 df neg %rdi + 417403: ff 15 87 3c 2b 00 callq *0x2b3c87(%rip) # 6cb090 <__morecore> + 417409: 48 8b 05 d0 51 2b 00 mov 0x2b51d0(%rip),%rax # 6cc5e0 <__after_morecore_hook> + 417410: 48 85 c0 test %rax,%rax + 417413: 75 2d jne 417442 + 417415: 31 ff xor %edi,%edi + 417417: ff 15 73 3c 2b 00 callq *0x2b3c73(%rip) # 6cb090 <__morecore> + 41741d: 90 nop + 41741e: 48 85 c0 test %rax,%rax + 417421: 74 ab je 4173ce + 417423: 49 29 c6 sub %rax,%r14 + 417426: 74 a6 je 4173ce + 417428: 49 8b 04 24 mov (%r12),%rax + 41742c: 4c 29 f5 sub %r14,%rbp + 41742f: 4d 29 75 00 sub %r14,0x0(%r13) + 417433: 48 83 cd 01 or $0x1,%rbp + 417437: 48 89 68 08 mov %rbp,0x8(%rax) + 41743b: b8 01 00 00 00 mov $0x1,%eax + 417440: eb 8e jmp 4173d0 + 417442: ff d0 callq *%rax + 417444: eb cf jmp 417415 + 417446: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41744d: 00 00 00 + +0000000000417450 : + 417450: 55 push %rbp + 417451: 53 push %rbx + 417452: 48 89 fd mov %rdi,%rbp + 417455: 48 89 f3 mov %rsi,%rbx + 417458: 48 83 ec 08 sub $0x8,%rsp + 41745c: 48 8b 05 9d 51 2b 00 mov 0x2b519d(%rip),%rax # 6cc600 + 417463: 48 85 c0 test %rax,%rax + 417466: 75 17 jne 41747f + 417468: 48 8b 05 51 33 2b 00 mov 0x2b3351(%rip),%rax # 6ca7c0 + 41746f: 48 85 c0 test %rax,%rax + 417472: 0f 84 00 02 00 00 je 417678 + 417478: 48 89 05 81 51 2b 00 mov %rax,0x2b5181(%rip) # 6cc600 + 41747f: 48 8b 15 e2 32 2b 00 mov 0x2b32e2(%rip),%rdx # 6ca768 + 417486: 48 83 e8 01 sub $0x1,%rax + 41748a: 48 39 d0 cmp %rdx,%rax + 41748d: 0f 83 50 02 00 00 jae 4176e3 + 417493: 48 8b 15 5e 51 2b 00 mov 0x2b515e(%rip),%rdx # 6cc5f8 + 41749a: 48 85 d2 test %rdx,%rdx + 41749d: 0f 84 2b 02 00 00 je 4176ce + 4174a3: 48 89 d1 mov %rdx,%rcx + 4174a6: be 01 00 00 00 mov $0x1,%esi + 4174ab: eb 33 jmp 4174e0 + 4174ad: 0f 1f 00 nopl (%rax) + 4174b0: 83 3d 05 5d 2b 00 00 cmpl $0x0,0x2b5d05(%rip) # 6cd1bc <__libc_multiple_threads> + 4174b7: 74 06 je 4174bf + 4174b9: f0 0f b1 32 lock cmpxchg %esi,(%rdx) + 4174bd: eb 03 jmp 4174c2 + 4174bf: 0f b1 32 cmpxchg %esi,(%rdx) + 4174c2: 85 c0 test %eax,%eax + 4174c4: 0f 84 95 00 00 00 je 41755f + 4174ca: 48 8b 05 27 51 2b 00 mov 0x2b5127(%rip),%rax # 6cc5f8 + 4174d1: 48 8b 92 68 08 00 00 mov 0x868(%rdx),%rdx + 4174d8: 48 39 c2 cmp %rax,%rdx + 4174db: 48 89 c1 mov %rax,%rcx + 4174de: 74 1a je 4174fa + 4174e0: 8b 42 04 mov 0x4(%rdx),%eax + 4174e3: 83 e0 04 and $0x4,%eax + 4174e6: 74 c8 je 4174b0 + 4174e8: 48 8b 92 68 08 00 00 mov 0x868(%rdx),%rdx + 4174ef: 48 89 c8 mov %rcx,%rax + 4174f2: 48 89 c1 mov %rax,%rcx + 4174f5: 48 39 c2 cmp %rax,%rdx + 4174f8: 75 e6 jne 4174e0 + 4174fa: 48 39 c3 cmp %rax,%rbx + 4174fd: 0f 84 13 02 00 00 je 417716 + 417503: 48 89 c2 mov %rax,%rdx + 417506: eb 18 jmp 417520 + 417508: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 41750f: 00 + 417510: 48 8b 92 68 08 00 00 mov 0x868(%rdx),%rdx + 417517: 48 39 c2 cmp %rax,%rdx + 41751a: 0f 84 88 01 00 00 je 4176a8 + 417520: f6 42 04 04 testb $0x4,0x4(%rdx) + 417524: 75 ea jne 417510 + 417526: 48 39 d3 cmp %rdx,%rbx + 417529: 74 e5 je 417510 + 41752b: 90 nop + 41752c: be 01 00 00 00 mov $0x1,%esi + 417531: 31 c0 xor %eax,%eax + 417533: 83 3d 82 5c 2b 00 00 cmpl $0x0,0x2b5c82(%rip) # 6cd1bc <__libc_multiple_threads> + 41753a: 74 08 je 417544 + 41753c: f0 0f b1 32 lock cmpxchg %esi,(%rdx) + 417540: 75 07 jne 417549 + 417542: eb 1b jmp 41755f + 417544: 0f b1 32 cmpxchg %esi,(%rdx) + 417547: 74 16 je 41755f + 417549: 48 8d 3a lea (%rdx),%rdi + 41754c: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 417553: e8 78 b0 02 00 callq 4425d0 <__lll_lock_wait_private> + 417558: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41755f: 49 c7 c0 d8 ff ff ff mov $0xffffffffffffffd8,%r8 + 417566: be 01 00 00 00 mov $0x1,%esi + 41756b: 31 c0 xor %eax,%eax + 41756d: 64 4d 8b 08 mov %fs:(%r8),%r9 + 417571: 83 3d 44 5c 2b 00 00 cmpl $0x0,0x2b5c44(%rip) # 6cd1bc <__libc_multiple_threads> + 417578: 74 0c je 417586 + 41757a: f0 0f b1 35 ae 50 2b lock cmpxchg %esi,0x2b50ae(%rip) # 6cc630 + 417581: 00 + 417582: 75 0b jne 41758f + 417584: eb 23 jmp 4175a9 + 417586: 0f b1 35 a3 50 2b 00 cmpxchg %esi,0x2b50a3(%rip) # 6cc630 + 41758d: 74 1a je 4175a9 + 41758f: 48 8d 3d 9a 50 2b 00 lea 0x2b509a(%rip),%rdi # 6cc630 + 417596: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41759d: e8 2e b0 02 00 callq 4425d0 <__lll_lock_wait_private> + 4175a2: 48 81 c4 80 00 00 00 add $0x80,%rsp + 4175a9: 4d 85 c9 test %r9,%r9 + 4175ac: 74 1b je 4175c9 + 4175ae: 49 8b 81 78 08 00 00 mov 0x878(%r9),%rax + 4175b5: 48 85 c0 test %rax,%rax + 4175b8: 0f 84 ff 03 00 00 je 4179bd + 4175be: 48 83 e8 01 sub $0x1,%rax + 4175c2: 49 89 81 78 08 00 00 mov %rax,0x878(%r9) + 4175c9: 48 8b 0d 58 50 2b 00 mov 0x2b5058(%rip),%rcx # 6cc628 + 4175d0: 48 85 c9 test %rcx,%rcx + 4175d3: 74 41 je 417616 + 4175d5: 48 83 b9 78 08 00 00 cmpq $0x0,0x878(%rcx) + 4175dc: 00 + 4175dd: 0f 85 ad 03 00 00 jne 417990 + 4175e3: 48 39 d1 cmp %rdx,%rcx + 4175e6: 75 22 jne 41760a + 4175e8: e9 51 01 00 00 jmpq 41773e + 4175ed: 0f 1f 00 nopl (%rax) + 4175f0: 48 83 b8 78 08 00 00 cmpq $0x0,0x878(%rax) + 4175f7: 00 + 4175f8: 0f 85 92 03 00 00 jne 417990 + 4175fe: 48 39 c2 cmp %rax,%rdx + 417601: 0f 84 b1 00 00 00 je 4176b8 + 417607: 48 89 c1 mov %rax,%rcx + 41760a: 48 8b 81 70 08 00 00 mov 0x870(%rcx),%rax + 417611: 48 85 c0 test %rax,%rax + 417614: 75 da jne 4175f0 + 417616: 48 83 82 78 08 00 00 addq $0x1,0x878(%rdx) + 41761d: 01 + 41761e: 83 3d 97 5b 2b 00 00 cmpl $0x0,0x2b5b97(%rip) # 6cd1bc <__libc_multiple_threads> + 417625: 74 0b je 417632 + 417627: f0 ff 0d 02 50 2b 00 lock decl 0x2b5002(%rip) # 6cc630 + 41762e: 75 0a jne 41763a + 417630: eb 22 jmp 417654 + 417632: ff 0d f8 4f 2b 00 decl 0x2b4ff8(%rip) # 6cc630 + 417638: 74 1a je 417654 + 41763a: 48 8d 3d ef 4f 2b 00 lea 0x2b4fef(%rip),%rdi # 6cc630 + 417641: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 417648: e8 b3 af 02 00 callq 442600 <__lll_unlock_wake_private> + 41764d: 48 81 c4 80 00 00 00 add $0x80,%rsp + 417654: 90 nop + 417655: 48 8b 82 68 08 00 00 mov 0x868(%rdx),%rax + 41765c: 64 49 89 10 mov %rdx,%fs:(%r8) + 417660: 48 89 05 91 4f 2b 00 mov %rax,0x2b4f91(%rip) # 6cc5f8 + 417667: 48 83 c4 08 add $0x8,%rsp + 41766b: 48 89 d0 mov %rdx,%rax + 41766e: 5b pop %rbx + 41766f: 5d pop %rbp + 417670: c3 retq + 417671: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 417678: 48 8b 15 e9 30 2b 00 mov 0x2b30e9(%rip),%rdx # 6ca768 + 41767f: 48 39 15 32 31 2b 00 cmp %rdx,0x2b3132(%rip) # 6ca7b8 + 417686: 0f 83 fa fd ff ff jae 417486 + 41768c: e8 af a9 02 00 callq 442040 <__get_nprocs> + 417691: 85 c0 test %eax,%eax + 417693: 0f 8e 89 00 00 00 jle 417722 + 417699: c1 e0 03 shl $0x3,%eax + 41769c: 48 98 cltq + 41769e: e9 d5 fd ff ff jmpq 417478 + 4176a3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4176a8: 48 83 c4 08 add $0x8,%rsp + 4176ac: 31 d2 xor %edx,%edx + 4176ae: 48 89 d0 mov %rdx,%rax + 4176b1: 5b pop %rbx + 4176b2: 5d pop %rbp + 4176b3: c3 retq + 4176b4: 0f 1f 40 00 nopl 0x0(%rax) + 4176b8: 48 81 c1 70 08 00 00 add $0x870,%rcx + 4176bf: 48 8b 80 70 08 00 00 mov 0x870(%rax),%rax + 4176c6: 48 89 01 mov %rax,(%rcx) + 4176c9: e9 48 ff ff ff jmpq 417616 + 4176ce: 48 c7 05 1f 4f 2b 00 movq $0x6ca800,0x2b4f1f(%rip) # 6cc5f8 + 4176d5: 00 a8 6c 00 + 4176d9: ba 00 a8 6c 00 mov $0x6ca800,%edx + 4176de: e9 c0 fd ff ff jmpq 4174a3 + 4176e3: 48 8d 4a 01 lea 0x1(%rdx),%rcx + 4176e7: 48 89 d0 mov %rdx,%rax + 4176ea: 64 83 3c 25 18 00 00 cmpl $0x0,%fs:0x18 + 4176f1: 00 00 + 4176f3: 74 01 je 4176f6 + 4176f5: f0 48 0f b1 0d 6a 30 lock cmpxchg %rcx,0x2b306a(%rip) # 6ca768 + 4176fc: 2b 00 + 4176fe: 48 39 d0 cmp %rdx,%rax + 417701: 74 48 je 41774b + 417703: 48 8b 15 5e 30 2b 00 mov 0x2b305e(%rip),%rdx # 6ca768 + 41770a: 48 8b 05 ef 4e 2b 00 mov 0x2b4eef(%rip),%rax # 6cc600 + 417711: e9 70 fd ff ff jmpq 417486 + 417716: 48 8b 83 68 08 00 00 mov 0x868(%rbx),%rax + 41771d: e9 e1 fd ff ff jmpq 417503 + 417722: 48 c7 05 d3 4e 2b 00 movq $0x10,0x2b4ed3(%rip) # 6cc600 + 417729: 10 00 00 00 + 41772d: 48 8b 15 34 30 2b 00 mov 0x2b3034(%rip),%rdx # 6ca768 + 417734: b8 10 00 00 00 mov $0x10,%eax + 417739: e9 48 fd ff ff jmpq 417486 + 41773e: 48 89 d0 mov %rdx,%rax + 417741: b9 28 c6 6c 00 mov $0x6cc628,%ecx + 417746: e9 74 ff ff ff jmpq 4176bf + 41774b: 48 8b 35 56 30 2b 00 mov 0x2b3056(%rip),%rsi # 6ca7a8 + 417752: 48 8d bd c0 08 00 00 lea 0x8c0(%rbp),%rdi + 417759: e8 22 f7 ff ff callq 416e80 + 41775e: 48 85 c0 test %rax,%rax + 417761: 49 89 c0 mov %rax,%r8 + 417764: 0f 84 58 02 00 00 je 4179c2 + 41776a: 49 8d 50 20 lea 0x20(%r8),%rdx + 41776e: 49 8d 40 78 lea 0x78(%r8),%rax + 417772: 49 8d 88 68 08 00 00 lea 0x868(%r8),%rcx + 417779: 49 89 10 mov %rdx,(%r8) + 41777c: 0f 1f 40 00 nopl 0x0(%rax) + 417780: 48 89 40 18 mov %rax,0x18(%rax) + 417784: 48 89 40 10 mov %rax,0x10(%rax) + 417788: 48 83 c0 10 add $0x10,%rax + 41778c: 48 39 c8 cmp %rcx,%rax + 41778f: 75 ef jne 417780 + 417791: 48 81 fa 00 a8 6c 00 cmp $0x6ca800,%rdx + 417798: 0f 84 0b 02 00 00 je 4179a9 + 41779e: 41 8b 40 24 mov 0x24(%r8),%eax + 4177a2: 83 c8 02 or $0x2,%eax + 4177a5: 83 c8 01 or $0x1,%eax + 4177a8: 4c 89 c6 mov %r8,%rsi + 4177ab: 49 c7 80 98 08 00 00 movq $0x1,0x898(%r8) + 4177b2: 01 00 00 00 + 4177b6: 41 89 40 24 mov %eax,0x24(%r8) + 4177ba: 49 8b 40 10 mov 0x10(%r8),%rax + 4177be: 49 8d 88 b0 08 00 00 lea 0x8b0(%r8),%rcx + 4177c5: 48 01 05 4c 4e 2b 00 add %rax,0x2b4e4c(%rip) # 6cc618 + 4177cc: 83 e6 0f and $0xf,%esi + 4177cf: 49 89 80 a8 08 00 00 mov %rax,0x8a8(%r8) + 4177d6: 49 89 80 a0 08 00 00 mov %rax,0x8a0(%r8) + 4177dd: 74 07 je 4177e6 + 4177df: 48 29 f1 sub %rsi,%rcx + 4177e2: 48 83 c1 10 add $0x10,%rcx + 4177e6: 4c 01 c0 add %r8,%rax + 4177e9: 49 89 48 78 mov %rcx,0x78(%r8) + 4177ed: 48 29 c8 sub %rcx,%rax + 4177f0: 48 83 c8 01 or $0x1,%rax + 4177f4: 48 89 41 08 mov %rax,0x8(%rcx) + 4177f8: 90 nop + 4177f9: 48 c7 c0 d8 ff ff ff mov $0xffffffffffffffd8,%rax + 417800: 41 b9 01 00 00 00 mov $0x1,%r9d + 417806: 45 31 d2 xor %r10d,%r10d + 417809: 41 c7 40 20 00 00 00 movl $0x0,0x20(%r8) + 417810: 00 + 417811: 44 89 ce mov %r9d,%esi + 417814: 64 48 8b 18 mov %fs:(%rax),%rbx + 417818: 64 48 89 10 mov %rdx,%fs:(%rax) + 41781c: 44 89 d0 mov %r10d,%eax + 41781f: 83 3d 96 59 2b 00 00 cmpl $0x0,0x2b5996(%rip) # 6cd1bc <__libc_multiple_threads> + 417826: 74 0c je 417834 + 417828: f0 0f b1 35 f0 4d 2b lock cmpxchg %esi,0x2b4df0(%rip) # 6cc620 + 41782f: 00 + 417830: 75 0b jne 41783d + 417832: eb 23 jmp 417857 + 417834: 0f b1 35 e5 4d 2b 00 cmpxchg %esi,0x2b4de5(%rip) # 6cc620 + 41783b: 74 1a je 417857 + 41783d: 48 8d 3d dc 4d 2b 00 lea 0x2b4ddc(%rip),%rdi # 6cc620 + 417844: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41784b: e8 80 ad 02 00 callq 4425d0 <__lll_lock_wait_private> + 417850: 48 81 c4 80 00 00 00 add $0x80,%rsp + 417857: 48 8b 05 0a 38 2b 00 mov 0x2b380a(%rip),%rax # 6cb068 + 41785e: 49 89 80 88 08 00 00 mov %rax,0x888(%r8) + 417865: 48 89 15 fc 37 2b 00 mov %rdx,0x2b37fc(%rip) # 6cb068 + 41786c: 83 3d 49 59 2b 00 00 cmpl $0x0,0x2b5949(%rip) # 6cd1bc <__libc_multiple_threads> + 417873: 74 0b je 417880 + 417875: f0 ff 0d a4 4d 2b 00 lock decl 0x2b4da4(%rip) # 6cc620 + 41787c: 75 0a jne 417888 + 41787e: eb 22 jmp 4178a2 + 417880: ff 0d 9a 4d 2b 00 decl 0x2b4d9a(%rip) # 6cc620 + 417886: 74 1a je 4178a2 + 417888: 48 8d 3d 91 4d 2b 00 lea 0x2b4d91(%rip),%rdi # 6cc620 + 41788f: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 417896: e8 65 ad 02 00 callq 442600 <__lll_unlock_wake_private> + 41789b: 48 81 c4 80 00 00 00 add $0x80,%rsp + 4178a2: 44 89 ce mov %r9d,%esi + 4178a5: 44 89 d0 mov %r10d,%eax + 4178a8: 83 3d 0d 59 2b 00 00 cmpl $0x0,0x2b590d(%rip) # 6cd1bc <__libc_multiple_threads> + 4178af: 74 0c je 4178bd + 4178b1: f0 0f b1 35 77 4d 2b lock cmpxchg %esi,0x2b4d77(%rip) # 6cc630 + 4178b8: 00 + 4178b9: 75 0b jne 4178c6 + 4178bb: eb 23 jmp 4178e0 + 4178bd: 0f b1 35 6c 4d 2b 00 cmpxchg %esi,0x2b4d6c(%rip) # 6cc630 + 4178c4: 74 1a je 4178e0 + 4178c6: 48 8d 3d 63 4d 2b 00 lea 0x2b4d63(%rip),%rdi # 6cc630 + 4178cd: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 4178d4: e8 f7 ac 02 00 callq 4425d0 <__lll_lock_wait_private> + 4178d9: 48 81 c4 80 00 00 00 add $0x80,%rsp + 4178e0: 48 85 db test %rbx,%rbx + 4178e3: 74 1b je 417900 + 4178e5: 48 8b 83 78 08 00 00 mov 0x878(%rbx),%rax + 4178ec: 48 85 c0 test %rax,%rax + 4178ef: 0f 84 c8 00 00 00 je 4179bd + 4178f5: 48 83 e8 01 sub $0x1,%rax + 4178f9: 48 89 83 78 08 00 00 mov %rax,0x878(%rbx) + 417900: 83 3d b5 58 2b 00 00 cmpl $0x0,0x2b58b5(%rip) # 6cd1bc <__libc_multiple_threads> + 417907: 74 0b je 417914 + 417909: f0 ff 0d 20 4d 2b 00 lock decl 0x2b4d20(%rip) # 6cc630 + 417910: 75 0a jne 41791c + 417912: eb 22 jmp 417936 + 417914: ff 0d 16 4d 2b 00 decl 0x2b4d16(%rip) # 6cc630 + 41791a: 74 1a je 417936 + 41791c: 48 8d 3d 0d 4d 2b 00 lea 0x2b4d0d(%rip),%rdi # 6cc630 + 417923: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41792a: e8 d1 ac 02 00 callq 442600 <__lll_unlock_wake_private> + 41792f: 48 81 c4 80 00 00 00 add $0x80,%rsp + 417936: be 01 00 00 00 mov $0x1,%esi + 41793b: 31 c0 xor %eax,%eax + 41793d: 83 3d 78 58 2b 00 00 cmpl $0x0,0x2b5878(%rip) # 6cd1bc <__libc_multiple_threads> + 417944: 74 08 je 41794e + 417946: f0 0f b1 32 lock cmpxchg %esi,(%rdx) + 41794a: 75 07 jne 417953 + 41794c: eb 1b jmp 417969 + 41794e: 0f b1 32 cmpxchg %esi,(%rdx) + 417951: 74 16 je 417969 + 417953: 48 8d 3a lea (%rdx),%rdi + 417956: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41795d: e8 6e ac 02 00 callq 4425d0 <__lll_lock_wait_private> + 417962: 48 81 c4 80 00 00 00 add $0x80,%rsp + 417969: 48 85 d2 test %rdx,%rdx + 41796c: 0f 85 f5 fc ff ff jne 417667 + 417972: 64 83 3c 25 18 00 00 cmpl $0x0,%fs:0x18 + 417979: 00 00 + 41797b: 74 01 je 41797e + 41797d: f0 48 ff 0d e3 2d 2b lock decq 0x2b2de3(%rip) # 6ca768 + 417984: 00 + 417985: 31 d2 xor %edx,%edx + 417987: e9 db fc ff ff jmpq 417667 + 41798c: 0f 1f 40 00 nopl 0x0(%rax) + 417990: b9 80 2f 4a 00 mov $0x4a2f80,%ecx + 417995: ba ee 02 00 00 mov $0x2ee,%edx + 41799a: be a8 1f 4a 00 mov $0x4a1fa8,%esi + 41799f: bf 42 20 4a 00 mov $0x4a2042,%edi + 4179a4: e8 77 f4 ff ff callq 416e20 <__malloc_assert> + 4179a9: 48 c7 05 84 4c 2b 00 movq $0x80,0x2b4c84(%rip) # 6cc638 + 4179b0: 80 00 00 00 + 4179b4: 41 8b 40 24 mov 0x24(%r8),%eax + 4179b8: e9 e8 fd ff ff jmpq 4177a5 + 4179bd: e8 11 8b fe ff callq 4004d3 + 4179c2: 48 8b 35 df 2d 2b 00 mov 0x2b2ddf(%rip),%rsi # 6ca7a8 + 4179c9: bf c0 08 00 00 mov $0x8c0,%edi + 4179ce: e8 ad f4 ff ff callq 416e80 + 4179d3: 48 85 c0 test %rax,%rax + 4179d6: 49 89 c0 mov %rax,%r8 + 4179d9: 0f 85 8b fd ff ff jne 41776a + 4179df: eb 91 jmp 417972 + 4179e1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4179e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4179ed: 00 00 00 + +00000000004179f0 : + 4179f0: 90 nop + 4179f1: 48 81 ff 00 a8 6c 00 cmp $0x6ca800,%rdi + 4179f8: 0f 84 8a 00 00 00 je 417a88 + 4179fe: 48 89 fa mov %rdi,%rdx + 417a01: 83 3d b4 57 2b 00 00 cmpl $0x0,0x2b57b4(%rip) # 6cd1bc <__libc_multiple_threads> + 417a08: 74 07 je 417a11 + 417a0a: f0 ff 0a lock decl (%rdx) + 417a0d: 75 06 jne 417a15 + 417a0f: eb 1a jmp 417a2b + 417a11: ff 0a decl (%rdx) + 417a13: 74 16 je 417a2b + 417a15: 48 8d 3a lea (%rdx),%rdi + 417a18: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 417a1f: e8 dc ab 02 00 callq 442600 <__lll_unlock_wake_private> + 417a24: 48 81 c4 80 00 00 00 add $0x80,%rsp + 417a2b: 8b 05 d3 2d 2b 00 mov 0x2b2dd3(%rip),%eax # 6ca804 + 417a31: 83 e0 04 and $0x4,%eax + 417a34: 75 4a jne 417a80 + 417a36: be 01 00 00 00 mov $0x1,%esi + 417a3b: 83 3d 7a 57 2b 00 00 cmpl $0x0,0x2b577a(%rip) # 6cd1bc <__libc_multiple_threads> + 417a42: 74 0c je 417a50 + 417a44: f0 0f b1 35 b4 2d 2b lock cmpxchg %esi,0x2b2db4(%rip) # 6ca800 + 417a4b: 00 + 417a4c: 75 0b jne 417a59 + 417a4e: eb 23 jmp 417a73 + 417a50: 0f b1 35 a9 2d 2b 00 cmpxchg %esi,0x2b2da9(%rip) # 6ca800 + 417a57: 74 1a je 417a73 + 417a59: 48 8d 3d a0 2d 2b 00 lea 0x2b2da0(%rip),%rdi # 6ca800 + 417a60: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 417a67: e8 64 ab 02 00 callq 4425d0 <__lll_lock_wait_private> + 417a6c: 48 81 c4 80 00 00 00 add $0x80,%rsp + 417a73: b8 00 a8 6c 00 mov $0x6ca800,%eax + 417a78: c3 retq + 417a79: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 417a80: 31 c0 xor %eax,%eax + 417a82: c3 retq + 417a83: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 417a88: 53 push %rbx + 417a89: 48 89 f3 mov %rsi,%rbx + 417a8c: 83 3d 29 57 2b 00 00 cmpl $0x0,0x2b5729(%rip) # 6cd1bc <__libc_multiple_threads> + 417a93: 74 0b je 417aa0 + 417a95: f0 ff 0d 64 2d 2b 00 lock decl 0x2b2d64(%rip) # 6ca800 + 417a9c: 75 0a jne 417aa8 + 417a9e: eb 22 jmp 417ac2 + 417aa0: ff 0d 5a 2d 2b 00 decl 0x2b2d5a(%rip) # 6ca800 + 417aa6: 74 1a je 417ac2 + 417aa8: 48 8d 3d 51 2d 2b 00 lea 0x2b2d51(%rip),%rdi # 6ca800 + 417aaf: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 417ab6: e8 45 ab 02 00 callq 442600 <__lll_unlock_wake_private> + 417abb: 48 81 c4 80 00 00 00 add $0x80,%rsp + 417ac2: e8 99 f6 ff ff callq 417160 + 417ac7: 48 85 c0 test %rax,%rax + 417aca: 74 02 je 417ace + 417acc: 5b pop %rbx + 417acd: c3 retq + 417ace: 48 89 df mov %rbx,%rdi + 417ad1: be 00 a8 6c 00 mov $0x6ca800,%esi + 417ad6: 5b pop %rbx + 417ad7: e9 74 f9 ff ff jmpq 417450 + 417adc: 0f 1f 40 00 nopl 0x0(%rax) + +0000000000417ae0 : + 417ae0: 41 56 push %r14 + 417ae2: 41 55 push %r13 + 417ae4: 41 54 push %r12 + 417ae6: 55 push %rbp + 417ae7: 53 push %rbx + 417ae8: 48 83 ec 20 sub $0x20,%rsp + 417aec: 48 8b 3d 65 2d 2b 00 mov 0x2b2d65(%rip),%rdi # 6ca858 + 417af3: 48 8b 1d 86 36 2b 00 mov 0x2b3686(%rip),%rbx # 6cb180 <_dl_pagesize> + 417afa: 48 81 ff 58 a8 6c 00 cmp $0x6ca858,%rdi + 417b01: 0f 84 15 01 00 00 je 417c1c + 417b07: 48 8b 47 08 mov 0x8(%rdi),%rax + 417b0b: a8 02 test $0x2,%al + 417b0d: 75 11 jne 417b20 + 417b0f: 48 89 c2 mov %rax,%rdx + 417b12: 48 83 e2 f8 and $0xfffffffffffffff8,%rdx + 417b16: 48 83 fa 1f cmp $0x1f,%rdx + 417b1a: 0f 87 d0 00 00 00 ja 417bf0 + 417b20: 8b 05 de 2c 2b 00 mov 0x2b2cde(%rip),%eax # 6ca804 + 417b26: 8b 2d 44 2c 2b 00 mov 0x2b2c44(%rip),%ebp # 6ca770 + 417b2c: 83 c8 04 or $0x4,%eax + 417b2f: 89 05 cf 2c 2b 00 mov %eax,0x2b2ccf(%rip) # 6ca804 + 417b35: 89 e8 mov %ebp,%eax + 417b37: 83 e0 05 and $0x5,%eax + 417b3a: 83 f8 05 cmp $0x5,%eax + 417b3d: 0f 84 6d 01 00 00 je 417cb0 + 417b43: 40 f6 c5 01 test $0x1,%bpl + 417b47: 0f 85 e3 00 00 00 jne 417c30 + 417b4d: 83 e5 02 and $0x2,%ebp + 417b50: 0f 85 8d 01 00 00 jne 417ce3 + 417b56: 31 ff xor %edi,%edi + 417b58: ff 15 32 35 2b 00 callq *0x2b3532(%rip) # 6cb090 <__morecore> + 417b5e: 49 89 c5 mov %rax,%r13 + 417b61: 48 89 c5 mov %rax,%rbp + 417b64: 41 83 e5 0f and $0xf,%r13d + 417b68: 75 76 jne 417be0 + 417b6a: 48 8b 05 37 2c 2b 00 mov 0x2b2c37(%rip),%rax # 6ca7a8 + 417b71: 48 8d 53 ff lea -0x1(%rbx),%rdx + 417b75: 49 8d 44 05 20 lea 0x20(%r13,%rax,1),%rax + 417b7a: 48 8d 4c 05 00 lea 0x0(%rbp,%rax,1),%rcx + 417b7f: 48 01 c3 add %rax,%rbx + 417b82: 48 21 ca and %rcx,%rdx + 417b85: 48 29 d3 sub %rdx,%rbx + 417b88: 48 89 df mov %rbx,%rdi + 417b8b: ff 15 ff 34 2b 00 callq *0x2b34ff(%rip) # 6cb090 <__morecore> + 417b91: 48 85 c0 test %rax,%rax + 417b94: 49 89 c4 mov %rax,%r12 + 417b97: 0f 84 2e 01 00 00 je 417ccb + 417b9d: 48 8b 05 3c 4a 2b 00 mov 0x2b4a3c(%rip),%rax # 6cc5e0 <__after_morecore_hook> + 417ba4: 48 85 c0 test %rax,%rax + 417ba7: 74 02 je 417bab + 417ba9: ff d0 callq *%rax + 417bab: 4c 2b 25 3e 2c 2b 00 sub 0x2b2c3e(%rip),%r12 # 6ca7f0 + 417bb2: 4c 01 ed add %r13,%rbp + 417bb5: 31 c0 xor %eax,%eax + 417bb7: 48 89 2d 9a 2c 2b 00 mov %rbp,0x2b2c9a(%rip) # 6ca858 + 417bbe: 49 01 dc add %rbx,%r12 + 417bc1: 4c 29 eb sub %r13,%rbx + 417bc4: 48 83 cb 01 or $0x1,%rbx + 417bc8: 4c 89 25 b1 34 2b 00 mov %r12,0x2b34b1(%rip) # 6cb080 + 417bcf: 48 89 5d 08 mov %rbx,0x8(%rbp) + 417bd3: 48 83 c4 20 add $0x20,%rsp + 417bd7: 5b pop %rbx + 417bd8: 5d pop %rbp + 417bd9: 41 5c pop %r12 + 417bdb: 41 5d pop %r13 + 417bdd: 41 5e pop %r14 + 417bdf: c3 retq + 417be0: b8 10 00 00 00 mov $0x10,%eax + 417be5: 4c 29 e8 sub %r13,%rax + 417be8: 49 89 c5 mov %rax,%r13 + 417beb: e9 7a ff ff ff jmpq 417b6a + 417bf0: a8 01 test $0x1,%al + 417bf2: 0f 84 28 ff ff ff je 417b20 + 417bf8: 8b 05 06 2c 2b 00 mov 0x2b2c06(%rip),%eax # 6ca804 + 417bfe: a8 02 test $0x2,%al + 417c00: 75 1a jne 417c1c + 417c02: 48 8b 0d 77 34 2b 00 mov 0x2b3477(%rip),%rcx # 6cb080 + 417c09: 48 03 0d e0 2b 2b 00 add 0x2b2be0(%rip),%rcx # 6ca7f0 + 417c10: 48 01 fa add %rdi,%rdx + 417c13: 48 39 ca cmp %rcx,%rdx + 417c16: 0f 85 0a ff ff ff jne 417b26 + 417c1c: 48 83 c4 20 add $0x20,%rsp + 417c20: 31 c0 xor %eax,%eax + 417c22: 5b pop %rbx + 417c23: 5d pop %rbp + 417c24: 41 5c pop %r12 + 417c26: 41 5d pop %r13 + 417c28: 41 5e pop %r14 + 417c2a: c3 retq + 417c2b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 417c30: 48 8d 74 24 10 lea 0x10(%rsp),%rsi + 417c35: 31 c9 xor %ecx,%ecx + 417c37: ba 10 00 00 00 mov $0x10,%edx + 417c3c: c6 44 24 10 00 movb $0x0,0x10(%rsp) + 417c41: e8 6a a2 03 00 callq 451eb0 <_itoa_word> + 417c46: 48 39 e0 cmp %rsp,%rax + 417c49: 49 89 c4 mov %rax,%r12 + 417c4c: 76 25 jbe 417c73 + 417c4e: 48 89 c2 mov %rax,%rdx + 417c51: 48 89 c7 mov %rax,%rdi + 417c54: be 30 00 00 00 mov $0x30,%esi + 417c59: 48 29 e2 sub %rsp,%rdx + 417c5c: 4c 8d 70 ff lea -0x1(%rax),%r14 + 417c60: 48 29 d7 sub %rdx,%rdi + 417c63: e8 e8 86 fe ff callq 400350 <__rela_iplt_end+0x88> + 417c68: 48 8d 44 24 ff lea -0x1(%rsp),%rax + 417c6d: 4c 29 f0 sub %r14,%rax + 417c70: 49 01 c4 add %rax,%r12 + 417c73: 48 8b 05 46 56 2b 00 mov 0x2b5646(%rip),%rax # 6cd2c0 <__libc_argv> + 417c7a: 89 ef mov %ebp,%edi + 417c7c: ba 38 20 4a 00 mov $0x4a2038,%edx + 417c81: 4d 89 e0 mov %r12,%r8 + 417c84: b9 5b 20 4a 00 mov $0x4a205b,%ecx + 417c89: be a8 23 4a 00 mov $0x4a23a8,%esi + 417c8e: 48 8b 00 mov (%rax),%rax + 417c91: 48 85 c0 test %rax,%rax + 417c94: 48 0f 45 d0 cmovne %rax,%rdx + 417c98: 83 e7 02 and $0x2,%edi + 417c9b: 31 c0 xor %eax,%eax + 417c9d: e8 1e 99 ff ff callq 4115c0 <__libc_message> + 417ca2: e9 af fe ff ff jmpq 417b56 + 417ca7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 417cae: 00 00 + 417cb0: 89 ef mov %ebp,%edi + 417cb2: ba 5b 20 4a 00 mov $0x4a205b,%edx + 417cb7: be 3c ca 4b 00 mov $0x4bca3c,%esi + 417cbc: 83 e7 02 and $0x2,%edi + 417cbf: 31 c0 xor %eax,%eax + 417cc1: e8 fa 98 ff ff callq 4115c0 <__libc_message> + 417cc6: e9 8b fe ff ff jmpq 417b56 + 417ccb: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 417cd2: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) + 417cd9: b8 ff ff ff ff mov $0xffffffff,%eax + 417cde: e9 f0 fe ff ff jmpq 417bd3 + 417ce3: e8 18 5f ff ff callq 40dc00 + 417ce8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 417cef: 00 + +0000000000417cf0 : + 417cf0: 41 55 push %r13 + 417cf2: 41 54 push %r12 + 417cf4: 55 push %rbp + 417cf5: 53 push %rbx + 417cf6: 48 83 ec 28 sub $0x28,%rsp + 417cfa: 48 8b 47 08 mov 0x8(%rdi),%rax + 417cfe: 48 89 c6 mov %rax,%rsi + 417d01: 48 83 e6 f8 and $0xfffffffffffffff8,%rsi + 417d05: a8 02 test $0x2,%al + 417d07: 0f 84 09 01 00 00 je 417e16 + 417d0d: 48 8b 07 mov (%rdi),%rax + 417d10: 48 89 fa mov %rdi,%rdx + 417d13: 48 01 c6 add %rax,%rsi + 417d16: 48 29 c7 sub %rax,%rdi + 417d19: 48 8b 05 60 34 2b 00 mov 0x2b3460(%rip),%rax # 6cb180 <_dl_pagesize> + 417d20: 48 89 f9 mov %rdi,%rcx + 417d23: 48 09 f1 or %rsi,%rcx + 417d26: 48 83 e8 01 sub $0x1,%rax + 417d2a: 48 85 c8 test %rcx,%rax + 417d2d: 75 29 jne 417d58 + 417d2f: f0 ff 0d 92 2a 2b 00 lock decl 0x2b2a92(%rip) # 6ca7c8 + 417d36: 48 89 f0 mov %rsi,%rax + 417d39: 48 f7 d8 neg %rax + 417d3c: f0 48 01 05 94 2a 2b lock add %rax,0x2b2a94(%rip) # 6ca7d8 + 417d43: 00 + 417d44: e8 67 7f 02 00 callq 43fcb0 <__munmap> + 417d49: 48 83 c4 28 add $0x28,%rsp + 417d4d: 5b pop %rbx + 417d4e: 5d pop %rbp + 417d4f: 41 5c pop %r12 + 417d51: 41 5d pop %r13 + 417d53: c3 retq + 417d54: 0f 1f 40 00 nopl 0x0(%rax) + 417d58: 8b 1d 12 2a 2b 00 mov 0x2b2a12(%rip),%ebx # 6ca770 + 417d5e: 89 d8 mov %ebx,%eax + 417d60: 83 e0 05 and $0x5,%eax + 417d63: 83 f8 05 cmp $0x5,%eax + 417d66: 0f 84 8f 00 00 00 je 417dfb + 417d6c: f6 c3 01 test $0x1,%bl + 417d6f: 75 0f jne 417d80 + 417d71: 83 e3 02 and $0x2,%ebx + 417d74: 74 d3 je 417d49 + 417d76: e8 85 5e ff ff callq 40dc00 + 417d7b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 417d80: 48 8d 7a 10 lea 0x10(%rdx),%rdi + 417d84: 48 8d 74 24 10 lea 0x10(%rsp),%rsi + 417d89: 31 c9 xor %ecx,%ecx + 417d8b: ba 10 00 00 00 mov $0x10,%edx + 417d90: c6 44 24 10 00 movb $0x0,0x10(%rsp) + 417d95: e8 16 a1 03 00 callq 451eb0 <_itoa_word> + 417d9a: 48 39 e0 cmp %rsp,%rax + 417d9d: 48 89 c5 mov %rax,%rbp + 417da0: 76 25 jbe 417dc7 + 417da2: 48 89 c2 mov %rax,%rdx + 417da5: 48 89 c7 mov %rax,%rdi + 417da8: be 30 00 00 00 mov $0x30,%esi + 417dad: 48 29 e2 sub %rsp,%rdx + 417db0: 4c 8d 68 ff lea -0x1(%rax),%r13 + 417db4: 48 29 d7 sub %rdx,%rdi + 417db7: e8 94 85 fe ff callq 400350 <__rela_iplt_end+0x88> + 417dbc: 48 8d 44 24 ff lea -0x1(%rsp),%rax + 417dc1: 4c 29 e8 sub %r13,%rax + 417dc4: 48 01 c5 add %rax,%rbp + 417dc7: 48 8b 05 f2 54 2b 00 mov 0x2b54f2(%rip),%rax # 6cd2c0 <__libc_argv> + 417dce: ba 38 20 4a 00 mov $0x4a2038,%edx + 417dd3: 49 89 e8 mov %rbp,%r8 + 417dd6: b9 d0 23 4a 00 mov $0x4a23d0,%ecx + 417ddb: be a8 23 4a 00 mov $0x4a23a8,%esi + 417de0: 48 8b 00 mov (%rax),%rax + 417de3: 48 85 c0 test %rax,%rax + 417de6: 48 0f 45 d0 cmovne %rax,%rdx + 417dea: 83 e3 02 and $0x2,%ebx + 417ded: 31 c0 xor %eax,%eax + 417def: 89 df mov %ebx,%edi + 417df1: e8 ca 97 ff ff callq 4115c0 <__libc_message> + 417df6: e9 4e ff ff ff jmpq 417d49 + 417dfb: 83 e3 02 and $0x2,%ebx + 417dfe: ba d0 23 4a 00 mov $0x4a23d0,%edx + 417e03: be 3c ca 4b 00 mov $0x4bca3c,%esi + 417e08: 89 df mov %ebx,%edi + 417e0a: 31 c0 xor %eax,%eax + 417e0c: e8 af 97 ff ff callq 4115c0 <__libc_message> + 417e11: e9 33 ff ff ff jmpq 417d49 + 417e16: b9 78 2e 4a 00 mov $0x4a2e78,%ecx + 417e1b: ba 0f 0b 00 00 mov $0xb0f,%edx + 417e20: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 417e25: bf d1 1f 4a 00 mov $0x4a1fd1,%edi + 417e2a: e8 f1 ef ff ff callq 416e20 <__malloc_assert> + 417e2f: 90 nop + +0000000000417e30 : + 417e30: 48 83 3d 00 48 2b 00 cmpq $0x0,0x2b4800(%rip) # 6cc638 + 417e37: 00 + 417e38: 0f 84 26 07 00 00 je 418564 + 417e3e: 41 57 push %r15 + 417e40: 41 56 push %r14 + 417e42: 49 89 fe mov %rdi,%r14 + 417e45: 41 55 push %r13 + 417e47: 41 54 push %r12 + 417e49: 55 push %rbp + 417e4a: 53 push %rbx + 417e4b: 48 83 ec 68 sub $0x68,%rsp + 417e4f: 64 83 3c 25 18 00 00 cmpl $0x0,%fs:0x18 + 417e56: 00 00 + 417e58: 74 01 je 417e5b + 417e5a: f0 83 4f 04 01 lock orl $0x1,0x4(%rdi) + 417e5f: 48 8d 47 50 lea 0x50(%rdi),%rax + 417e63: 48 8d 74 24 40 lea 0x40(%rsp),%rsi + 417e68: 4c 8d 57 58 lea 0x58(%rdi),%r10 + 417e6c: 4c 8d 5f 08 lea 0x8(%rdi),%r11 + 417e70: 48 89 44 24 08 mov %rax,0x8(%rsp) + 417e75: b8 01 00 00 00 mov $0x1,%eax + 417e7a: 48 29 f0 sub %rsi,%rax + 417e7d: 48 89 44 24 10 mov %rax,0x10(%rsp) + 417e82: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 417e88: 31 db xor %ebx,%ebx + 417e8a: 49 87 1b xchg %rbx,(%r11) + 417e8d: 48 85 db test %rbx,%rbx + 417e90: 0f 84 71 01 00 00 je 418007 + 417e96: 4c 89 1c 24 mov %r11,(%rsp) + 417e9a: 4d 89 d7 mov %r10,%r15 + 417e9d: e9 a6 00 00 00 jmpq 417f48 + 417ea2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 417ea8: 48 8b 45 08 mov 0x8(%rbp),%rax + 417eac: 4d 01 ec add %r13,%r12 + 417eaf: 48 83 e0 f8 and $0xfffffffffffffff8,%rax + 417eb3: 48 3b 44 05 00 cmp 0x0(%rbp,%rax,1),%rax + 417eb8: 0f 85 22 02 00 00 jne 4180e0 + 417ebe: 4c 8b 6d 10 mov 0x10(%rbp),%r13 + 417ec2: 48 8b 45 18 mov 0x18(%rbp),%rax + 417ec6: 49 3b 6d 18 cmp 0x18(%r13),%rbp + 417eca: 0f 85 a0 01 00 00 jne 418070 + 417ed0: 48 3b 68 10 cmp 0x10(%rax),%rbp + 417ed4: 0f 85 96 01 00 00 jne 418070 + 417eda: 48 81 7d 08 ff 03 00 cmpq $0x3ff,0x8(%rbp) + 417ee1: 00 + 417ee2: 49 89 45 18 mov %rax,0x18(%r13) + 417ee6: 4c 89 68 10 mov %r13,0x10(%rax) + 417eea: 76 14 jbe 417f00 + 417eec: 48 8b 45 20 mov 0x20(%rbp),%rax + 417ef0: 48 85 c0 test %rax,%rax + 417ef3: 0f 85 07 04 00 00 jne 418300 + 417ef9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 417f00: 49 8b 46 68 mov 0x68(%r14),%rax + 417f04: 49 81 fc ff 03 00 00 cmp $0x3ff,%r12 + 417f0b: 49 89 5e 68 mov %rbx,0x68(%r14) + 417f0f: 48 89 58 18 mov %rbx,0x18(%rax) + 417f13: 76 10 jbe 417f25 + 417f15: 48 c7 43 20 00 00 00 movq $0x0,0x20(%rbx) + 417f1c: 00 + 417f1d: 48 c7 43 28 00 00 00 movq $0x0,0x28(%rbx) + 417f24: 00 + 417f25: 4c 89 e2 mov %r12,%rdx + 417f28: 4c 89 7b 18 mov %r15,0x18(%rbx) + 417f2c: 48 89 43 10 mov %rax,0x10(%rbx) + 417f30: 48 83 ca 01 or $0x1,%rdx + 417f34: 4d 85 c9 test %r9,%r9 + 417f37: 48 89 53 08 mov %rdx,0x8(%rbx) + 417f3b: 4e 89 24 23 mov %r12,(%rbx,%r12,1) + 417f3f: 4c 89 cb mov %r9,%rbx + 417f42: 0f 84 b8 00 00 00 je 418000 + 417f48: 48 8b 43 08 mov 0x8(%rbx),%rax + 417f4c: 4c 8b 4b 10 mov 0x10(%rbx),%r9 + 417f50: 49 89 c4 mov %rax,%r12 + 417f53: 49 83 e4 fa and $0xfffffffffffffffa,%r12 + 417f57: 4a 8d 2c 23 lea (%rbx,%r12,1),%rbp + 417f5b: 4c 8b 6d 08 mov 0x8(%rbp),%r13 + 417f5f: 49 83 e5 f8 and $0xfffffffffffffff8,%r13 + 417f63: a8 01 test $0x1,%al + 417f65: 75 59 jne 417fc0 + 417f67: 48 8b 03 mov (%rbx),%rax + 417f6a: 48 29 c3 sub %rax,%rbx + 417f6d: 49 01 c4 add %rax,%r12 + 417f70: 48 8b 43 08 mov 0x8(%rbx),%rax + 417f74: 48 83 e0 f8 and $0xfffffffffffffff8,%rax + 417f78: 48 3b 04 03 cmp (%rbx,%rax,1),%rax + 417f7c: 0f 85 26 01 00 00 jne 4180a8 + 417f82: 4c 8b 5b 10 mov 0x10(%rbx),%r11 + 417f86: 48 8b 43 18 mov 0x18(%rbx),%rax + 417f8a: 49 3b 5b 18 cmp 0x18(%r11),%rbx + 417f8e: 0f 85 9c 00 00 00 jne 418030 + 417f94: 48 3b 58 10 cmp 0x10(%rax),%rbx + 417f98: 0f 85 92 00 00 00 jne 418030 + 417f9e: 48 81 7b 08 ff 03 00 cmpq $0x3ff,0x8(%rbx) + 417fa5: 00 + 417fa6: 49 89 43 18 mov %rax,0x18(%r11) + 417faa: 4c 89 58 10 mov %r11,0x10(%rax) + 417fae: 76 10 jbe 417fc0 + 417fb0: 48 8b 43 20 mov 0x20(%rbx),%rax + 417fb4: 48 85 c0 test %rax,%rax + 417fb7: 0f 85 03 03 00 00 jne 4182c0 + 417fbd: 0f 1f 00 nopl (%rax) + 417fc0: 49 3b 6e 58 cmp 0x58(%r14),%rbp + 417fc4: 74 1a je 417fe0 + 417fc6: 42 f6 44 2d 08 01 testb $0x1,0x8(%rbp,%r13,1) + 417fcc: 0f 84 d6 fe ff ff je 417ea8 + 417fd2: 48 83 65 08 fe andq $0xfffffffffffffffe,0x8(%rbp) + 417fd7: e9 24 ff ff ff jmpq 417f00 + 417fdc: 0f 1f 40 00 nopl 0x0(%rax) + 417fe0: 4d 01 ec add %r13,%r12 + 417fe3: 49 83 cc 01 or $0x1,%r12 + 417fe7: 4d 85 c9 test %r9,%r9 + 417fea: 4c 89 63 08 mov %r12,0x8(%rbx) + 417fee: 49 89 5e 58 mov %rbx,0x58(%r14) + 417ff2: 4c 89 cb mov %r9,%rbx + 417ff5: 0f 85 4d ff ff ff jne 417f48 + 417ffb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 418000: 4c 8b 1c 24 mov (%rsp),%r11 + 418004: 4d 89 fa mov %r15,%r10 + 418007: 49 83 c3 08 add $0x8,%r11 + 41800b: 49 8d 43 f8 lea -0x8(%r11),%rax + 41800f: 48 39 44 24 08 cmp %rax,0x8(%rsp) + 418014: 0f 85 6e fe ff ff jne 417e88 + 41801a: 48 83 c4 68 add $0x68,%rsp + 41801e: 5b pop %rbx + 41801f: 5d pop %rbp + 418020: 41 5c pop %r12 + 418022: 41 5d pop %r13 + 418024: 41 5e pop %r14 + 418026: 41 5f pop %r15 + 418028: c3 retq + 418029: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 418030: 4d 85 f6 test %r14,%r14 + 418033: 44 8b 1d 36 27 2b 00 mov 0x2b2736(%rip),%r11d # 6ca770 + 41803a: 74 05 je 418041 + 41803c: 41 83 4e 04 04 orl $0x4,0x4(%r14) + 418041: 44 89 d8 mov %r11d,%eax + 418044: 83 e0 05 and $0x5,%eax + 418047: 83 f8 05 cmp $0x5,%eax + 41804a: 0f 84 7f 04 00 00 je 4184cf + 418050: 41 f6 c3 01 test $0x1,%r11b + 418054: 0f 85 96 01 00 00 jne 4181f0 + 41805a: 41 83 e3 02 and $0x2,%r11d + 41805e: 0f 84 5c ff ff ff je 417fc0 + 418064: e8 97 5b ff ff callq 40dc00 + 418069: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 418070: 8b 3d fa 26 2b 00 mov 0x2b26fa(%rip),%edi # 6ca770 + 418076: 41 83 4e 04 04 orl $0x4,0x4(%r14) + 41807b: 89 f8 mov %edi,%eax + 41807d: 83 e0 05 and $0x5,%eax + 418080: 83 f8 05 cmp $0x5,%eax + 418083: 0f 84 6c 04 00 00 je 4184f5 + 418089: 41 89 fd mov %edi,%r13d + 41808c: 41 83 e5 02 and $0x2,%r13d + 418090: 83 e7 01 and $0x1,%edi + 418093: 0f 85 af 00 00 00 jne 418148 + 418099: 45 85 ed test %r13d,%r13d + 41809c: 0f 84 5e fe ff ff je 417f00 + 4180a2: eb c0 jmp 418064 + 4180a4: 0f 1f 40 00 nopl 0x0(%rax) + 4180a8: 4d 85 f6 test %r14,%r14 + 4180ab: 44 8b 1d be 26 2b 00 mov 0x2b26be(%rip),%r11d # 6ca770 + 4180b2: 74 05 je 4180b9 + 4180b4: 41 83 4e 04 04 orl $0x4,0x4(%r14) + 4180b9: 44 89 d8 mov %r11d,%eax + 4180bc: 83 e0 05 and $0x5,%eax + 4180bf: 83 f8 05 cmp $0x5,%eax + 4180c2: 0f 84 50 04 00 00 je 418518 + 4180c8: 41 f6 c3 01 test $0x1,%r11b + 4180cc: 0f 85 6e 02 00 00 jne 418340 + 4180d2: 41 83 e3 02 and $0x2,%r11d + 4180d6: 0f 84 a6 fe ff ff je 417f82 + 4180dc: eb 86 jmp 418064 + 4180de: 66 90 xchg %ax,%ax + 4180e0: 44 8b 1d 89 26 2b 00 mov 0x2b2689(%rip),%r11d # 6ca770 + 4180e7: 41 83 4e 04 04 orl $0x4,0x4(%r14) + 4180ec: 44 89 d8 mov %r11d,%eax + 4180ef: 83 e0 05 and $0x5,%eax + 4180f2: 83 f8 05 cmp $0x5,%eax + 4180f5: 0f 84 43 04 00 00 je 41853e + 4180fb: 41 f6 c3 01 test $0x1,%r11b + 4180ff: 0f 85 0b 03 00 00 jne 418410 + 418105: 41 f6 c3 02 test $0x2,%r11b + 418109: 0f 85 55 ff ff ff jne 418064 + 41810f: 4c 8b 6d 10 mov 0x10(%rbp),%r13 + 418113: 48 8b 45 18 mov 0x18(%rbp),%rax + 418117: 49 39 6d 18 cmp %rbp,0x18(%r13) + 41811b: 0f 85 df fd ff ff jne 417f00 + 418121: 48 3b 68 10 cmp 0x10(%rax),%rbp + 418125: 0f 84 af fd ff ff je 417eda + 41812b: 44 89 df mov %r11d,%edi + 41812e: 41 83 4e 04 04 orl $0x4,0x4(%r14) + 418133: 41 89 fd mov %edi,%r13d + 418136: 41 83 e5 02 and $0x2,%r13d + 41813a: 83 e7 01 and $0x1,%edi + 41813d: 0f 84 56 ff ff ff je 418099 + 418143: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 418148: 48 8d 74 24 50 lea 0x50(%rsp),%rsi + 41814d: 31 c9 xor %ecx,%ecx + 41814f: 48 89 ef mov %rbp,%rdi + 418152: ba 10 00 00 00 mov $0x10,%edx + 418157: 4c 89 4c 24 18 mov %r9,0x18(%rsp) + 41815c: c6 44 24 50 00 movb $0x0,0x50(%rsp) + 418161: e8 4a 9d 03 00 callq 451eb0 <_itoa_word> + 418166: 48 89 c5 mov %rax,%rbp + 418169: 48 8d 44 24 40 lea 0x40(%rsp),%rax + 41816e: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 + 418173: 48 39 c5 cmp %rax,%rbp + 418176: 76 3c jbe 4181b4 + 418178: 48 8b 44 24 10 mov 0x10(%rsp),%rax + 41817d: 48 8d 4d ff lea -0x1(%rbp),%rcx + 418181: 48 89 ef mov %rbp,%rdi + 418184: be 30 00 00 00 mov $0x30,%esi + 418189: 4c 89 4c 24 20 mov %r9,0x20(%rsp) + 41818e: 48 89 4c 24 18 mov %rcx,0x18(%rsp) + 418193: 48 8d 14 08 lea (%rax,%rcx,1),%rdx + 418197: 48 29 d7 sub %rdx,%rdi + 41819a: e8 b1 81 fe ff callq 400350 <__rela_iplt_end+0x88> + 41819f: 48 8b 4c 24 18 mov 0x18(%rsp),%rcx + 4181a4: 48 8d 44 24 3f lea 0x3f(%rsp),%rax + 4181a9: 4c 8b 4c 24 20 mov 0x20(%rsp),%r9 + 4181ae: 48 29 c8 sub %rcx,%rax + 4181b1: 48 01 c5 add %rax,%rbp + 4181b4: 48 8b 05 05 51 2b 00 mov 0x2b5105(%rip),%rax # 6cd2c0 <__libc_argv> + 4181bb: ba 38 20 4a 00 mov $0x4a2038,%edx + 4181c0: 49 89 e8 mov %rbp,%r8 + 4181c3: b9 95 20 4a 00 mov $0x4a2095,%ecx + 4181c8: be a8 23 4a 00 mov $0x4a23a8,%esi + 4181cd: 44 89 ef mov %r13d,%edi + 4181d0: 4c 89 4c 24 18 mov %r9,0x18(%rsp) + 4181d5: 48 8b 00 mov (%rax),%rax + 4181d8: 48 85 c0 test %rax,%rax + 4181db: 48 0f 45 d0 cmovne %rax,%rdx + 4181df: 31 c0 xor %eax,%eax + 4181e1: e8 da 93 ff ff callq 4115c0 <__libc_message> + 4181e6: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 + 4181eb: e9 10 fd ff ff jmpq 417f00 + 4181f0: 48 8d 74 24 50 lea 0x50(%rsp),%rsi + 4181f5: 31 c9 xor %ecx,%ecx + 4181f7: ba 10 00 00 00 mov $0x10,%edx + 4181fc: 48 89 df mov %rbx,%rdi + 4181ff: 44 89 5c 24 20 mov %r11d,0x20(%rsp) + 418204: 4c 89 4c 24 18 mov %r9,0x18(%rsp) + 418209: c6 44 24 50 00 movb $0x0,0x50(%rsp) + 41820e: e8 9d 9c 03 00 callq 451eb0 <_itoa_word> + 418213: 49 89 c0 mov %rax,%r8 + 418216: 48 8d 44 24 40 lea 0x40(%rsp),%rax + 41821b: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 + 418220: 44 8b 5c 24 20 mov 0x20(%rsp),%r11d + 418225: 49 39 c0 cmp %rax,%r8 + 418228: 76 50 jbe 41827a + 41822a: 48 8b 44 24 10 mov 0x10(%rsp),%rax + 41822f: 49 8d 48 ff lea -0x1(%r8),%rcx + 418233: 4c 89 c7 mov %r8,%rdi + 418236: be 30 00 00 00 mov $0x30,%esi + 41823b: 44 89 5c 24 30 mov %r11d,0x30(%rsp) + 418240: 4c 89 4c 24 28 mov %r9,0x28(%rsp) + 418245: 48 89 4c 24 20 mov %rcx,0x20(%rsp) + 41824a: 4c 89 44 24 18 mov %r8,0x18(%rsp) + 41824f: 48 8d 14 08 lea (%rax,%rcx,1),%rdx + 418253: 48 29 d7 sub %rdx,%rdi + 418256: e8 f5 80 fe ff callq 400350 <__rela_iplt_end+0x88> + 41825b: 48 8b 4c 24 20 mov 0x20(%rsp),%rcx + 418260: 48 8d 44 24 3f lea 0x3f(%rsp),%rax + 418265: 4c 8b 44 24 18 mov 0x18(%rsp),%r8 + 41826a: 44 8b 5c 24 30 mov 0x30(%rsp),%r11d + 41826f: 4c 8b 4c 24 28 mov 0x28(%rsp),%r9 + 418274: 48 29 c8 sub %rcx,%rax + 418277: 49 01 c0 add %rax,%r8 + 41827a: 48 8b 05 3f 50 2b 00 mov 0x2b503f(%rip),%rax # 6cd2c0 <__libc_argv> + 418281: 44 89 df mov %r11d,%edi + 418284: ba 38 20 4a 00 mov $0x4a2038,%edx + 418289: b9 95 20 4a 00 mov $0x4a2095,%ecx + 41828e: be a8 23 4a 00 mov $0x4a23a8,%esi + 418293: 4c 89 4c 24 18 mov %r9,0x18(%rsp) + 418298: 48 8b 00 mov (%rax),%rax + 41829b: 48 85 c0 test %rax,%rax + 41829e: 48 0f 45 d0 cmovne %rax,%rdx + 4182a2: 83 e7 02 and $0x2,%edi + 4182a5: 31 c0 xor %eax,%eax + 4182a7: e8 14 93 ff ff callq 4115c0 <__libc_message> + 4182ac: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 + 4182b1: e9 0a fd ff ff jmpq 417fc0 + 4182b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4182bd: 00 00 00 + 4182c0: 48 3b 58 28 cmp 0x28(%rax),%rbx + 4182c4: 0f 85 dd 02 00 00 jne 4185a7 + 4182ca: 48 8b 53 28 mov 0x28(%rbx),%rdx + 4182ce: 48 3b 5a 20 cmp 0x20(%rdx),%rbx + 4182d2: 0f 85 cf 02 00 00 jne 4185a7 + 4182d8: 49 83 7b 20 00 cmpq $0x0,0x20(%r11) + 4182dd: 0f 84 03 03 00 00 je 4185e6 + 4182e3: 48 8b 53 28 mov 0x28(%rbx),%rdx + 4182e7: 48 89 50 28 mov %rdx,0x28(%rax) + 4182eb: 48 8b 53 28 mov 0x28(%rbx),%rdx + 4182ef: 48 89 42 20 mov %rax,0x20(%rdx) + 4182f3: e9 c8 fc ff ff jmpq 417fc0 + 4182f8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 4182ff: 00 + 418300: 48 3b 68 28 cmp 0x28(%rax),%rbp + 418304: 0f 85 06 03 00 00 jne 418610 + 41830a: 48 8b 55 28 mov 0x28(%rbp),%rdx + 41830e: 48 3b 6a 20 cmp 0x20(%rdx),%rbp + 418312: 0f 85 f8 02 00 00 jne 418610 + 418318: 49 83 7d 20 00 cmpq $0x0,0x20(%r13) + 41831d: 0f 84 27 03 00 00 je 41864a + 418323: 48 8b 55 28 mov 0x28(%rbp),%rdx + 418327: 48 89 50 28 mov %rdx,0x28(%rax) + 41832b: 48 8b 55 28 mov 0x28(%rbp),%rdx + 41832f: 48 89 42 20 mov %rax,0x20(%rdx) + 418333: e9 c8 fb ff ff jmpq 417f00 + 418338: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 41833f: 00 + 418340: 48 8d 74 24 50 lea 0x50(%rsp),%rsi + 418345: 31 c9 xor %ecx,%ecx + 418347: ba 10 00 00 00 mov $0x10,%edx + 41834c: 48 89 df mov %rbx,%rdi + 41834f: 44 89 5c 24 20 mov %r11d,0x20(%rsp) + 418354: 4c 89 4c 24 18 mov %r9,0x18(%rsp) + 418359: c6 44 24 50 00 movb $0x0,0x50(%rsp) + 41835e: e8 4d 9b 03 00 callq 451eb0 <_itoa_word> + 418363: 49 89 c0 mov %rax,%r8 + 418366: 48 8d 44 24 40 lea 0x40(%rsp),%rax + 41836b: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 + 418370: 44 8b 5c 24 20 mov 0x20(%rsp),%r11d + 418375: 49 39 c0 cmp %rax,%r8 + 418378: 76 50 jbe 4183ca + 41837a: 48 8b 44 24 10 mov 0x10(%rsp),%rax + 41837f: 49 8d 48 ff lea -0x1(%r8),%rcx + 418383: 4c 89 c7 mov %r8,%rdi + 418386: be 30 00 00 00 mov $0x30,%esi + 41838b: 44 89 5c 24 30 mov %r11d,0x30(%rsp) + 418390: 4c 89 4c 24 28 mov %r9,0x28(%rsp) + 418395: 48 89 4c 24 20 mov %rcx,0x20(%rsp) + 41839a: 4c 89 44 24 18 mov %r8,0x18(%rsp) + 41839f: 48 8d 14 08 lea (%rax,%rcx,1),%rdx + 4183a3: 48 29 d7 sub %rdx,%rdi + 4183a6: e8 a5 7f fe ff callq 400350 <__rela_iplt_end+0x88> + 4183ab: 48 8b 4c 24 20 mov 0x20(%rsp),%rcx + 4183b0: 48 8d 44 24 3f lea 0x3f(%rsp),%rax + 4183b5: 4c 8b 44 24 18 mov 0x18(%rsp),%r8 + 4183ba: 44 8b 5c 24 30 mov 0x30(%rsp),%r11d + 4183bf: 4c 8b 4c 24 28 mov 0x28(%rsp),%r9 + 4183c4: 48 29 c8 sub %rcx,%rax + 4183c7: 49 01 c0 add %rax,%r8 + 4183ca: 48 8b 05 ef 4e 2b 00 mov 0x2b4eef(%rip),%rax # 6cd2c0 <__libc_argv> + 4183d1: 44 89 df mov %r11d,%edi + 4183d4: ba 38 20 4a 00 mov $0x4a2038,%edx + 4183d9: b9 78 20 4a 00 mov $0x4a2078,%ecx + 4183de: be a8 23 4a 00 mov $0x4a23a8,%esi + 4183e3: 4c 89 4c 24 18 mov %r9,0x18(%rsp) + 4183e8: 48 8b 00 mov (%rax),%rax + 4183eb: 48 85 c0 test %rax,%rax + 4183ee: 48 0f 45 d0 cmovne %rax,%rdx + 4183f2: 83 e7 02 and $0x2,%edi + 4183f5: 31 c0 xor %eax,%eax + 4183f7: e8 c4 91 ff ff callq 4115c0 <__libc_message> + 4183fc: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 + 418401: e9 7c fb ff ff jmpq 417f82 + 418406: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41840d: 00 00 00 + 418410: 48 8d 74 24 50 lea 0x50(%rsp),%rsi + 418415: 31 c9 xor %ecx,%ecx + 418417: ba 10 00 00 00 mov $0x10,%edx + 41841c: 48 89 ef mov %rbp,%rdi + 41841f: 44 89 5c 24 20 mov %r11d,0x20(%rsp) + 418424: 4c 89 4c 24 18 mov %r9,0x18(%rsp) + 418429: c6 44 24 50 00 movb $0x0,0x50(%rsp) + 41842e: e8 7d 9a 03 00 callq 451eb0 <_itoa_word> + 418433: 49 89 c5 mov %rax,%r13 + 418436: 48 8d 44 24 40 lea 0x40(%rsp),%rax + 41843b: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 + 418440: 44 8b 5c 24 20 mov 0x20(%rsp),%r11d + 418445: 49 39 c5 cmp %rax,%r13 + 418448: 76 46 jbe 418490 + 41844a: 48 8b 44 24 10 mov 0x10(%rsp),%rax + 41844f: 49 8d 4d ff lea -0x1(%r13),%rcx + 418453: 4c 89 ef mov %r13,%rdi + 418456: be 30 00 00 00 mov $0x30,%esi + 41845b: 44 89 5c 24 28 mov %r11d,0x28(%rsp) + 418460: 4c 89 4c 24 20 mov %r9,0x20(%rsp) + 418465: 48 89 4c 24 18 mov %rcx,0x18(%rsp) + 41846a: 48 8d 14 08 lea (%rax,%rcx,1),%rdx + 41846e: 48 29 d7 sub %rdx,%rdi + 418471: e8 da 7e fe ff callq 400350 <__rela_iplt_end+0x88> + 418476: 48 8b 4c 24 18 mov 0x18(%rsp),%rcx + 41847b: 48 8d 44 24 3f lea 0x3f(%rsp),%rax + 418480: 44 8b 5c 24 28 mov 0x28(%rsp),%r11d + 418485: 4c 8b 4c 24 20 mov 0x20(%rsp),%r9 + 41848a: 48 29 c8 sub %rcx,%rax + 41848d: 49 01 c5 add %rax,%r13 + 418490: 48 8b 05 29 4e 2b 00 mov 0x2b4e29(%rip),%rax # 6cd2c0 <__libc_argv> + 418497: 44 89 df mov %r11d,%edi + 41849a: ba 38 20 4a 00 mov $0x4a2038,%edx + 41849f: 4d 89 e8 mov %r13,%r8 + 4184a2: b9 78 20 4a 00 mov $0x4a2078,%ecx + 4184a7: be a8 23 4a 00 mov $0x4a23a8,%esi + 4184ac: 4c 89 4c 24 18 mov %r9,0x18(%rsp) + 4184b1: 48 8b 00 mov (%rax),%rax + 4184b4: 48 85 c0 test %rax,%rax + 4184b7: 48 0f 45 d0 cmovne %rax,%rdx + 4184bb: 83 e7 02 and $0x2,%edi + 4184be: 31 c0 xor %eax,%eax + 4184c0: e8 fb 90 ff ff callq 4115c0 <__libc_message> + 4184c5: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 + 4184ca: e9 ef f9 ff ff jmpq 417ebe + 4184cf: 44 89 df mov %r11d,%edi + 4184d2: ba 95 20 4a 00 mov $0x4a2095,%edx + 4184d7: be 3c ca 4b 00 mov $0x4bca3c,%esi + 4184dc: 83 e7 02 and $0x2,%edi + 4184df: 31 c0 xor %eax,%eax + 4184e1: 4c 89 4c 24 18 mov %r9,0x18(%rsp) + 4184e6: e8 d5 90 ff ff callq 4115c0 <__libc_message> + 4184eb: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 + 4184f0: e9 cb fa ff ff jmpq 417fc0 + 4184f5: 83 e7 02 and $0x2,%edi + 4184f8: ba 95 20 4a 00 mov $0x4a2095,%edx + 4184fd: be 3c ca 4b 00 mov $0x4bca3c,%esi + 418502: 31 c0 xor %eax,%eax + 418504: 4c 89 4c 24 18 mov %r9,0x18(%rsp) + 418509: e8 b2 90 ff ff callq 4115c0 <__libc_message> + 41850e: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 + 418513: e9 e8 f9 ff ff jmpq 417f00 + 418518: 44 89 df mov %r11d,%edi + 41851b: ba 78 20 4a 00 mov $0x4a2078,%edx + 418520: be 3c ca 4b 00 mov $0x4bca3c,%esi + 418525: 83 e7 02 and $0x2,%edi + 418528: 31 c0 xor %eax,%eax + 41852a: 4c 89 4c 24 18 mov %r9,0x18(%rsp) + 41852f: e8 8c 90 ff ff callq 4115c0 <__libc_message> + 418534: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 + 418539: e9 44 fa ff ff jmpq 417f82 + 41853e: 44 89 df mov %r11d,%edi + 418541: ba 78 20 4a 00 mov $0x4a2078,%edx + 418546: be 3c ca 4b 00 mov $0x4bca3c,%esi + 41854b: 83 e7 02 and $0x2,%edi + 41854e: 31 c0 xor %eax,%eax + 418550: 4c 89 4c 24 18 mov %r9,0x18(%rsp) + 418555: e8 66 90 ff ff callq 4115c0 <__libc_message> + 41855a: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 + 41855f: e9 5a f9 ff ff jmpq 417ebe + 418564: 48 8d 4f 58 lea 0x58(%rdi),%rcx + 418568: 48 8d 97 48 08 00 00 lea 0x848(%rdi),%rdx + 41856f: 48 89 c8 mov %rcx,%rax + 418572: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 418578: 48 89 40 18 mov %rax,0x18(%rax) + 41857c: 48 89 40 10 mov %rax,0x10(%rax) + 418580: 48 83 c0 10 add $0x10,%rax + 418584: 48 39 c2 cmp %rax,%rdx + 418587: 75 ef jne 418578 + 418589: 48 81 ff 00 a8 6c 00 cmp $0x6ca800,%rdi + 418590: 0f 84 93 02 00 00 je 418829 + 418596: 8b 47 04 mov 0x4(%rdi),%eax + 418599: 83 c8 02 or $0x2,%eax + 41859c: 83 c8 01 or $0x1,%eax + 41859f: 48 89 4f 58 mov %rcx,0x58(%rdi) + 4185a3: 89 47 04 mov %eax,0x4(%rdi) + 4185a6: c3 retq + 4185a7: 4d 85 f6 test %r14,%r14 + 4185aa: 44 8b 05 bf 21 2b 00 mov 0x2b21bf(%rip),%r8d # 6ca770 + 4185b1: 74 05 je 4185b8 + 4185b3: 41 83 4e 04 04 orl $0x4,0x4(%r14) + 4185b8: 44 89 c2 mov %r8d,%edx + 4185bb: 83 e2 05 and $0x5,%edx + 4185be: 83 fa 05 cmp $0x5,%edx + 4185c1: 0f 84 85 02 00 00 je 41884c + 4185c7: 41 f6 c0 01 test $0x1,%r8b + 4185cb: 0f 85 a3 00 00 00 jne 418674 + 4185d1: 41 83 e0 02 and $0x2,%r8d + 4185d5: 0f 85 89 fa ff ff jne 418064 + 4185db: 49 83 7b 20 00 cmpq $0x0,0x20(%r11) + 4185e0: 0f 85 fd fc ff ff jne 4182e3 + 4185e6: 48 39 c3 cmp %rax,%rbx + 4185e9: 0f 84 50 02 00 00 je 41883f + 4185ef: 49 89 43 20 mov %rax,0x20(%r11) + 4185f3: 48 8b 43 28 mov 0x28(%rbx),%rax + 4185f7: 49 89 43 28 mov %rax,0x28(%r11) + 4185fb: 48 8b 43 20 mov 0x20(%rbx),%rax + 4185ff: 4c 89 58 28 mov %r11,0x28(%rax) + 418603: 48 8b 43 28 mov 0x28(%rbx),%rax + 418607: 4c 89 58 20 mov %r11,0x20(%rax) + 41860b: e9 b0 f9 ff ff jmpq 417fc0 + 418610: 44 8b 1d 59 21 2b 00 mov 0x2b2159(%rip),%r11d # 6ca770 + 418617: 41 83 4e 04 04 orl $0x4,0x4(%r14) + 41861c: 44 89 da mov %r11d,%edx + 41861f: 83 e2 05 and $0x5,%edx + 418622: 83 fa 05 cmp $0x5,%edx + 418625: 0f 84 62 02 00 00 je 41888d + 41862b: 41 f6 c3 01 test $0x1,%r11b + 41862f: 0f 85 2a 01 00 00 jne 41875f + 418635: 41 83 e3 02 and $0x2,%r11d + 418639: 0f 85 25 fa ff ff jne 418064 + 41863f: 49 83 7d 20 00 cmpq $0x0,0x20(%r13) + 418644: 0f 85 d9 fc ff ff jne 418323 + 41864a: 48 39 c5 cmp %rax,%rbp + 41864d: 0f 84 2d 02 00 00 je 418880 + 418653: 49 89 45 20 mov %rax,0x20(%r13) + 418657: 48 8b 45 28 mov 0x28(%rbp),%rax + 41865b: 49 89 45 28 mov %rax,0x28(%r13) + 41865f: 48 8b 45 20 mov 0x20(%rbp),%rax + 418663: 4c 89 68 28 mov %r13,0x28(%rax) + 418667: 48 8b 45 28 mov 0x28(%rbp),%rax + 41866b: 4c 89 68 20 mov %r13,0x20(%rax) + 41866f: e9 8c f8 ff ff jmpq 417f00 + 418674: 48 8d 74 24 50 lea 0x50(%rsp),%rsi + 418679: 31 c9 xor %ecx,%ecx + 41867b: ba 10 00 00 00 mov $0x10,%edx + 418680: 48 89 df mov %rbx,%rdi + 418683: 44 89 44 24 28 mov %r8d,0x28(%rsp) + 418688: 4c 89 5c 24 20 mov %r11,0x20(%rsp) + 41868d: 4c 89 4c 24 18 mov %r9,0x18(%rsp) + 418692: c6 44 24 50 00 movb $0x0,0x50(%rsp) + 418697: e8 14 98 03 00 callq 451eb0 <_itoa_word> + 41869c: 48 89 c1 mov %rax,%rcx + 41869f: 48 8d 44 24 40 lea 0x40(%rsp),%rax + 4186a4: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 + 4186a9: 4c 8b 5c 24 20 mov 0x20(%rsp),%r11 + 4186ae: 44 8b 44 24 28 mov 0x28(%rsp),%r8d + 4186b3: 48 39 c1 cmp %rax,%rcx + 4186b6: 76 5a jbe 418712 + 4186b8: 48 8b 44 24 10 mov 0x10(%rsp),%rax + 4186bd: 4c 8d 51 ff lea -0x1(%rcx),%r10 + 4186c1: 48 89 cf mov %rcx,%rdi + 4186c4: be 30 00 00 00 mov $0x30,%esi + 4186c9: 44 89 44 24 3c mov %r8d,0x3c(%rsp) + 4186ce: 4c 89 5c 24 30 mov %r11,0x30(%rsp) + 4186d3: 4c 89 4c 24 28 mov %r9,0x28(%rsp) + 4186d8: 4c 89 54 24 20 mov %r10,0x20(%rsp) + 4186dd: 4a 8d 14 10 lea (%rax,%r10,1),%rdx + 4186e1: 48 89 4c 24 18 mov %rcx,0x18(%rsp) + 4186e6: 48 29 d7 sub %rdx,%rdi + 4186e9: e8 62 7c fe ff callq 400350 <__rela_iplt_end+0x88> + 4186ee: 4c 8b 54 24 20 mov 0x20(%rsp),%r10 + 4186f3: 48 8d 44 24 3f lea 0x3f(%rsp),%rax + 4186f8: 48 8b 4c 24 18 mov 0x18(%rsp),%rcx + 4186fd: 44 8b 44 24 3c mov 0x3c(%rsp),%r8d + 418702: 4c 8b 5c 24 30 mov 0x30(%rsp),%r11 + 418707: 4c 8b 4c 24 28 mov 0x28(%rsp),%r9 + 41870c: 4c 29 d0 sub %r10,%rax + 41870f: 48 01 c1 add %rax,%rcx + 418712: 48 8b 05 a7 4b 2b 00 mov 0x2b4ba7(%rip),%rax # 6cd2c0 <__libc_argv> + 418719: 44 89 c7 mov %r8d,%edi + 41871c: ba 38 20 4a 00 mov $0x4a2038,%edx + 418721: 49 89 c8 mov %rcx,%r8 + 418724: be a8 23 4a 00 mov $0x4a23a8,%esi + 418729: b9 f0 23 4a 00 mov $0x4a23f0,%ecx + 41872e: 4c 89 5c 24 20 mov %r11,0x20(%rsp) + 418733: 4c 89 4c 24 18 mov %r9,0x18(%rsp) + 418738: 48 8b 00 mov (%rax),%rax + 41873b: 48 85 c0 test %rax,%rax + 41873e: 48 0f 45 d0 cmovne %rax,%rdx + 418742: 31 c0 xor %eax,%eax + 418744: 83 e7 02 and $0x2,%edi + 418747: e8 74 8e ff ff callq 4115c0 <__libc_message> + 41874c: 48 8b 43 20 mov 0x20(%rbx),%rax + 418750: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 + 418755: 4c 8b 5c 24 20 mov 0x20(%rsp),%r11 + 41875a: e9 79 fb ff ff jmpq 4182d8 + 41875f: 48 8d 74 24 50 lea 0x50(%rsp),%rsi + 418764: 31 c9 xor %ecx,%ecx + 418766: ba 10 00 00 00 mov $0x10,%edx + 41876b: 48 89 ef mov %rbp,%rdi + 41876e: 44 89 5c 24 20 mov %r11d,0x20(%rsp) + 418773: 4c 89 4c 24 18 mov %r9,0x18(%rsp) + 418778: c6 44 24 50 00 movb $0x0,0x50(%rsp) + 41877d: e8 2e 97 03 00 callq 451eb0 <_itoa_word> + 418782: 49 89 c0 mov %rax,%r8 + 418785: 48 8d 44 24 40 lea 0x40(%rsp),%rax + 41878a: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 + 41878f: 44 8b 5c 24 20 mov 0x20(%rsp),%r11d + 418794: 49 39 c0 cmp %rax,%r8 + 418797: 76 50 jbe 4187e9 + 418799: 48 8b 44 24 10 mov 0x10(%rsp),%rax + 41879e: 49 8d 48 ff lea -0x1(%r8),%rcx + 4187a2: 4c 89 c7 mov %r8,%rdi + 4187a5: be 30 00 00 00 mov $0x30,%esi + 4187aa: 44 89 5c 24 30 mov %r11d,0x30(%rsp) + 4187af: 4c 89 4c 24 28 mov %r9,0x28(%rsp) + 4187b4: 48 89 4c 24 20 mov %rcx,0x20(%rsp) + 4187b9: 4c 89 44 24 18 mov %r8,0x18(%rsp) + 4187be: 48 8d 14 08 lea (%rax,%rcx,1),%rdx + 4187c2: 48 29 d7 sub %rdx,%rdi + 4187c5: e8 86 7b fe ff callq 400350 <__rela_iplt_end+0x88> + 4187ca: 48 8b 4c 24 20 mov 0x20(%rsp),%rcx + 4187cf: 48 8d 44 24 3f lea 0x3f(%rsp),%rax + 4187d4: 4c 8b 44 24 18 mov 0x18(%rsp),%r8 + 4187d9: 44 8b 5c 24 30 mov 0x30(%rsp),%r11d + 4187de: 4c 8b 4c 24 28 mov 0x28(%rsp),%r9 + 4187e3: 48 29 c8 sub %rcx,%rax + 4187e6: 49 01 c0 add %rax,%r8 + 4187e9: 48 8b 05 d0 4a 2b 00 mov 0x2b4ad0(%rip),%rax # 6cd2c0 <__libc_argv> + 4187f0: 44 89 df mov %r11d,%edi + 4187f3: ba 38 20 4a 00 mov $0x4a2038,%edx + 4187f8: b9 f0 23 4a 00 mov $0x4a23f0,%ecx + 4187fd: be a8 23 4a 00 mov $0x4a23a8,%esi + 418802: 4c 89 4c 24 18 mov %r9,0x18(%rsp) + 418807: 48 8b 00 mov (%rax),%rax + 41880a: 48 85 c0 test %rax,%rax + 41880d: 48 0f 45 d0 cmovne %rax,%rdx + 418811: 31 c0 xor %eax,%eax + 418813: 83 e7 02 and $0x2,%edi + 418816: e8 a5 8d ff ff callq 4115c0 <__libc_message> + 41881b: 48 8b 45 20 mov 0x20(%rbp),%rax + 41881f: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 + 418824: e9 ef fa ff ff jmpq 418318 + 418829: 48 c7 05 04 3e 2b 00 movq $0x80,0x2b3e04(%rip) # 6cc638 + 418830: 80 00 00 00 + 418834: 8b 05 ca 1f 2b 00 mov 0x2b1fca(%rip),%eax # 6ca804 + 41883a: e9 5d fd ff ff jmpq 41859c + 41883f: 4d 89 5b 28 mov %r11,0x28(%r11) + 418843: 4d 89 5b 20 mov %r11,0x20(%r11) + 418847: e9 74 f7 ff ff jmpq 417fc0 + 41884c: 44 89 c7 mov %r8d,%edi + 41884f: 31 c0 xor %eax,%eax + 418851: ba f0 23 4a 00 mov $0x4a23f0,%edx + 418856: 83 e7 02 and $0x2,%edi + 418859: be 3c ca 4b 00 mov $0x4bca3c,%esi + 41885e: 4c 89 5c 24 20 mov %r11,0x20(%rsp) + 418863: 4c 89 4c 24 18 mov %r9,0x18(%rsp) + 418868: e8 53 8d ff ff callq 4115c0 <__libc_message> + 41886d: 48 8b 43 20 mov 0x20(%rbx),%rax + 418871: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 + 418876: 4c 8b 5c 24 20 mov 0x20(%rsp),%r11 + 41887b: e9 58 fa ff ff jmpq 4182d8 + 418880: 4d 89 6d 28 mov %r13,0x28(%r13) + 418884: 4d 89 6d 20 mov %r13,0x20(%r13) + 418888: e9 73 f6 ff ff jmpq 417f00 + 41888d: 44 89 df mov %r11d,%edi + 418890: 31 c0 xor %eax,%eax + 418892: ba f0 23 4a 00 mov $0x4a23f0,%edx + 418897: 83 e7 02 and $0x2,%edi + 41889a: be 3c ca 4b 00 mov $0x4bca3c,%esi + 41889f: 4c 89 4c 24 18 mov %r9,0x18(%rsp) + 4188a4: e8 17 8d ff ff callq 4115c0 <__libc_message> + 4188a9: 48 8b 45 20 mov 0x20(%rbp),%rax + 4188ad: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 + 4188b2: e9 61 fa ff ff jmpq 418318 + 4188b7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 4188be: 00 00 + +00000000004188c0 : + 4188c0: 41 54 push %r12 + 4188c2: 55 push %rbp + 4188c3: 49 89 f4 mov %rsi,%r12 + 4188c6: 53 push %rbx + 4188c7: 48 8b 47 58 mov 0x58(%rdi),%rax + 4188cb: 48 89 fb mov %rdi,%rbx + 4188ce: 48 85 c0 test %rax,%rax + 4188d1: 0f 84 f4 00 00 00 je 4189cb + 4188d7: 48 8b 68 08 mov 0x8(%rax),%rbp + 4188db: 48 8d 7b 08 lea 0x8(%rbx),%rdi + 4188df: 4c 8d 43 58 lea 0x58(%rbx),%r8 + 4188e3: 45 31 d2 xor %r10d,%r10d + 4188e6: 45 31 c9 xor %r9d,%r9d + 4188e9: 48 89 e9 mov %rbp,%rcx + 4188ec: 48 83 e1 f8 and $0xfffffffffffffff8,%rcx + 4188f0: 48 8b 07 mov (%rdi),%rax + 4188f3: 48 85 c0 test %rax,%rax + 4188f6: 74 20 je 418918 + 4188f8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 4188ff: 00 + 418900: 48 8b 50 08 mov 0x8(%rax),%rdx + 418904: 48 8b 40 10 mov 0x10(%rax),%rax + 418908: 41 83 c2 01 add $0x1,%r10d + 41890c: 48 83 e2 f8 and $0xfffffffffffffff8,%rdx + 418910: 49 01 d1 add %rdx,%r9 + 418913: 48 85 c0 test %rax,%rax + 418916: 75 e8 jne 418900 + 418918: 48 83 c7 08 add $0x8,%rdi + 41891c: 4c 39 c7 cmp %r8,%rdi + 41891f: 75 cf jne 4188f0 + 418921: 4c 8d 9b 48 08 00 00 lea 0x848(%rbx),%r11 + 418928: 4c 01 c9 add %r9,%rcx + 41892b: bf 01 00 00 00 mov $0x1,%edi + 418930: 49 8b 40 18 mov 0x18(%r8),%rax + 418934: 49 39 c0 cmp %rax,%r8 + 418937: 74 1e je 418957 + 418939: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 418940: 48 8b 50 08 mov 0x8(%rax),%rdx + 418944: 48 8b 40 18 mov 0x18(%rax),%rax + 418948: 83 c7 01 add $0x1,%edi + 41894b: 48 83 e2 f8 and $0xfffffffffffffff8,%rdx + 41894f: 48 01 d1 add %rdx,%rcx + 418952: 49 39 c0 cmp %rax,%r8 + 418955: 75 e9 jne 418940 + 418957: 49 83 c0 10 add $0x10,%r8 + 41895b: 4d 39 c3 cmp %r8,%r11 + 41895e: 75 d0 jne 418930 + 418960: 48 8b 93 80 08 00 00 mov 0x880(%rbx),%rdx + 418967: 41 8b 44 24 1c mov 0x1c(%r12),%eax + 41896c: 45 01 54 24 08 add %r10d,0x8(%r12) + 418971: 41 01 7c 24 04 add %edi,0x4(%r12) + 418976: 01 d0 add %edx,%eax + 418978: 41 01 4c 24 20 add %ecx,0x20(%r12) + 41897d: 41 01 14 24 add %edx,(%r12) + 418981: 29 c8 sub %ecx,%eax + 418983: 45 01 4c 24 18 add %r9d,0x18(%r12) + 418988: 48 81 fb 00 a8 6c 00 cmp $0x6ca800,%rbx + 41898f: 41 89 44 24 1c mov %eax,0x1c(%r12) + 418994: 74 05 je 41899b + 418996: 5b pop %rbx + 418997: 5d pop %rbp + 418998: 41 5c pop %r12 + 41899a: c3 retq + 41899b: 8b 05 27 1e 2b 00 mov 0x2b1e27(%rip),%eax # 6ca7c8 + 4189a1: 83 e5 f8 and $0xfffffff8,%ebp + 4189a4: 5b pop %rbx + 4189a5: 41 89 44 24 0c mov %eax,0xc(%r12) + 4189aa: 48 8b 05 27 1e 2b 00 mov 0x2b1e27(%rip),%rax # 6ca7d8 + 4189b1: 41 89 44 24 10 mov %eax,0x10(%r12) + 4189b6: 48 8b 05 2b 1e 2b 00 mov 0x2b1e2b(%rip),%rax # 6ca7e8 + 4189bd: 41 89 6c 24 24 mov %ebp,0x24(%r12) + 4189c2: 5d pop %rbp + 4189c3: 41 89 44 24 14 mov %eax,0x14(%r12) + 4189c8: 41 5c pop %r12 + 4189ca: c3 retq + 4189cb: e8 60 f4 ff ff callq 417e30 + 4189d0: 48 8b 43 58 mov 0x58(%rbx),%rax + 4189d4: e9 fe fe ff ff jmpq 4188d7 + 4189d9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + +00000000004189e0 : + 4189e0: 48 85 ff test %rdi,%rdi + 4189e3: 0f 84 1b 04 00 00 je 418e04 + 4189e9: 41 57 push %r15 + 4189eb: 41 56 push %r14 + 4189ed: 49 89 f8 mov %rdi,%r8 + 4189f0: 41 55 push %r13 + 4189f2: 41 54 push %r12 + 4189f4: be 01 00 00 00 mov $0x1,%esi + 4189f9: 55 push %rbp + 4189fa: 53 push %rbx + 4189fb: 31 c0 xor %eax,%eax + 4189fd: 48 83 ec 38 sub $0x38,%rsp + 418a01: 83 3d b4 47 2b 00 00 cmpl $0x0,0x2b47b4(%rip) # 6cd1bc <__libc_multiple_threads> + 418a08: 74 0c je 418a16 + 418a0a: f0 0f b1 35 ee 1d 2b lock cmpxchg %esi,0x2b1dee(%rip) # 6ca800 + 418a11: 00 + 418a12: 75 0b jne 418a1f + 418a14: eb 23 jmp 418a39 + 418a16: 0f b1 35 e3 1d 2b 00 cmpxchg %esi,0x2b1de3(%rip) # 6ca800 + 418a1d: 74 1a je 418a39 + 418a1f: 48 8d 3d da 1d 2b 00 lea 0x2b1dda(%rip),%rdi # 6ca800 + 418a26: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 418a2d: e8 9e 9b 02 00 callq 4425d0 <__lll_lock_wait_private> + 418a32: 48 81 c4 80 00 00 00 add $0x80,%rsp + 418a39: 41 f6 c0 0f test $0xf,%r8b + 418a3d: 0f 85 35 04 00 00 jne 418e78 + 418a43: 49 8d 58 f0 lea -0x10(%r8),%rbx + 418a47: 49 8b 40 f8 mov -0x8(%r8),%rax + 418a4b: 48 89 df mov %rbx,%rdi + 418a4e: 48 89 d9 mov %rbx,%rcx + 418a51: 48 c1 e9 0b shr $0xb,%rcx + 418a55: 48 c1 ef 03 shr $0x3,%rdi + 418a59: 48 89 c2 mov %rax,%rdx + 418a5c: 31 cf xor %ecx,%edi + 418a5e: 48 83 e2 f8 and $0xfffffffffffffff8,%rdx + 418a62: b9 02 00 00 00 mov $0x2,%ecx + 418a67: 40 80 ff 01 cmp $0x1,%dil + 418a6b: 0f 44 f9 cmove %ecx,%edi + 418a6e: a8 02 test $0x2,%al + 418a70: 0f 84 9a 03 00 00 je 418e10 + 418a76: 48 8b 05 03 27 2b 00 mov 0x2b2703(%rip),%rax # 6cb180 <_dl_pagesize> + 418a7d: 48 8d 48 ff lea -0x1(%rax),%rcx + 418a81: 4c 89 c0 mov %r8,%rax + 418a84: 48 21 c8 and %rcx,%rax + 418a87: 48 8d 70 f0 lea -0x10(%rax),%rsi + 418a8b: 48 f7 c6 ef ff ff ff test $0xffffffffffffffef,%rsi + 418a92: 74 34 je 418ac8 + 418a94: 48 8d 70 ff lea -0x1(%rax),%rsi + 418a98: 48 81 fe fe 1f 00 00 cmp $0x1ffe,%rsi + 418a9f: 77 27 ja 418ac8 + 418aa1: 48 8d 70 c0 lea -0x40(%rax),%rsi + 418aa5: 48 f7 c6 bf ff ff ff test $0xffffffffffffffbf,%rsi + 418aac: 74 1a je 418ac8 + 418aae: 48 8d b0 00 ff ff ff lea -0x100(%rax),%rsi + 418ab5: 48 f7 c6 ff fe ff ff test $0xfffffffffffffeff,%rsi + 418abc: 0f 85 5e 06 00 00 jne 419120 + 418ac2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 418ac8: 49 8b 40 f8 mov -0x8(%r8),%rax + 418acc: 83 e0 03 and $0x3,%eax + 418acf: 48 83 f8 02 cmp $0x2,%rax + 418ad3: 0f 85 9f 03 00 00 jne 418e78 + 418ad9: 49 8b 40 f0 mov -0x10(%r8),%rax + 418add: 48 89 de mov %rbx,%rsi + 418ae0: 48 29 c6 sub %rax,%rsi + 418ae3: 48 01 d0 add %rdx,%rax + 418ae6: 48 09 f0 or %rsi,%rax + 418ae9: 48 85 c8 test %rcx,%rax + 418aec: 0f 85 86 03 00 00 jne 418e78 + 418af2: 48 83 ea 01 sub $0x1,%rdx + 418af6: 40 0f b6 ff movzbl %dil,%edi + 418afa: 48 8d 34 13 lea (%rbx,%rdx,1),%rsi + 418afe: 0f b6 06 movzbl (%rsi),%eax + 418b01: 48 39 f8 cmp %rdi,%rax + 418b04: 48 89 c1 mov %rax,%rcx + 418b07: 74 3f je 418b48 + 418b09: 48 85 c0 test %rax,%rax + 418b0c: 0f 84 66 03 00 00 je 418e78 + 418b12: 48 8d 48 10 lea 0x10(%rax),%rcx + 418b16: 48 39 ca cmp %rcx,%rdx + 418b19: 73 1b jae 418b36 + 418b1b: e9 58 03 00 00 jmpq 418e78 + 418b20: 48 85 c0 test %rax,%rax + 418b23: 0f 84 4f 03 00 00 je 418e78 + 418b29: 48 8d 48 10 lea 0x10(%rax),%rcx + 418b2d: 48 39 d1 cmp %rdx,%rcx + 418b30: 0f 87 42 03 00 00 ja 418e78 + 418b36: 48 29 c2 sub %rax,%rdx + 418b39: 48 8d 34 13 lea (%rbx,%rdx,1),%rsi + 418b3d: 0f b6 06 movzbl (%rsi),%eax + 418b40: 48 39 f8 cmp %rdi,%rax + 418b43: 48 89 c1 mov %rax,%rcx + 418b46: 75 d8 jne 418b20 + 418b48: f7 d1 not %ecx + 418b4a: 48 85 db test %rbx,%rbx + 418b4d: 88 0e mov %cl,(%rsi) + 418b4f: 0f 84 23 03 00 00 je 418e78 + 418b55: 4d 8b 60 f8 mov -0x8(%r8),%r12 + 418b59: 41 f6 c4 02 test $0x2,%r12b + 418b5d: 0f 85 55 02 00 00 jne 418db8 + 418b63: 4c 89 e5 mov %r12,%rbp + 418b66: 48 83 e5 f8 and $0xfffffffffffffff8,%rbp + 418b6a: 48 89 e8 mov %rbp,%rax + 418b6d: 48 f7 d8 neg %rax + 418b70: 48 39 c3 cmp %rax,%rbx + 418b73: 0f 87 e7 04 00 00 ja 419060 + 418b79: f6 c3 0f test $0xf,%bl + 418b7c: 0f 85 de 04 00 00 jne 419060 + 418b82: 48 83 fd 1f cmp $0x1f,%rbp + 418b86: 0f 86 64 05 00 00 jbe 4190f0 + 418b8c: 41 f6 c4 08 test $0x8,%r12b + 418b90: 0f 85 5a 05 00 00 jne 4190f0 + 418b96: 48 3b 2d 9b 3a 2b 00 cmp 0x2b3a9b(%rip),%rbp # 6cc638 + 418b9d: 0f 86 a5 03 00 00 jbe 418f48 + 418ba3: 48 8b 05 ae 1c 2b 00 mov 0x2b1cae(%rip),%rax # 6ca858 + 418baa: 4c 8d 34 2b lea (%rbx,%rbp,1),%r14 + 418bae: 44 8b 2d 4f 1c 2b 00 mov 0x2b1c4f(%rip),%r13d # 6ca804 + 418bb5: 48 39 c3 cmp %rax,%rbx + 418bb8: 0f 84 94 06 00 00 je 419252 + 418bbe: 41 f6 c5 02 test $0x2,%r13b + 418bc2: 0f 84 af 06 00 00 je 419277 + 418bc8: 49 8b 46 08 mov 0x8(%r14),%rax + 418bcc: a8 01 test $0x1,%al + 418bce: 0f 84 c2 06 00 00 je 419296 + 418bd4: 49 89 c7 mov %rax,%r15 + 418bd7: 49 83 e7 f8 and $0xfffffffffffffff8,%r15 + 418bdb: 48 83 f8 10 cmp $0x10,%rax + 418bdf: 0f 86 4e 06 00 00 jbe 419233 + 418be5: 4c 3b 3d 94 24 2b 00 cmp 0x2b2494(%rip),%r15 # 6cb080 + 418bec: 0f 83 41 06 00 00 jae 419233 + 418bf2: 8b 35 3c 3a 2b 00 mov 0x2b3a3c(%rip),%esi # 6cc634 + 418bf8: 85 f6 test %esi,%esi + 418bfa: 0f 85 b0 06 00 00 jne 4192b0 + 418c00: 41 83 e4 01 and $0x1,%r12d + 418c04: 0f 85 8e 00 00 00 jne 418c98 + 418c0a: 49 8b 40 f0 mov -0x10(%r8),%rax + 418c0e: 48 29 c3 sub %rax,%rbx + 418c11: 48 01 c5 add %rax,%rbp + 418c14: 48 8b 43 08 mov 0x8(%rbx),%rax + 418c18: 48 83 e0 f8 and $0xfffffffffffffff8,%rax + 418c1c: 48 3b 04 03 cmp (%rbx,%rax,1),%rax + 418c20: 0f 85 1a 07 00 00 jne 419340 + 418c26: 4c 8b 63 10 mov 0x10(%rbx),%r12 + 418c2a: 48 8b 43 18 mov 0x18(%rbx),%rax + 418c2e: 49 3b 5c 24 18 cmp 0x18(%r12),%rbx + 418c33: 0f 85 8b 06 00 00 jne 4192c4 + 418c39: 48 3b 58 10 cmp 0x10(%rax),%rbx + 418c3d: 0f 85 81 06 00 00 jne 4192c4 + 418c43: 48 81 7b 08 ff 03 00 cmpq $0x3ff,0x8(%rbx) + 418c4a: 00 + 418c4b: 49 89 44 24 18 mov %rax,0x18(%r12) + 418c50: 4c 89 60 10 mov %r12,0x10(%rax) + 418c54: 76 42 jbe 418c98 + 418c56: 48 8b 43 20 mov 0x20(%rbx),%rax + 418c5a: 48 85 c0 test %rax,%rax + 418c5d: 74 39 je 418c98 + 418c5f: 48 3b 58 28 cmp 0x28(%rax),%rbx + 418c63: 0f 85 92 0a 00 00 jne 4196fb + 418c69: 48 8b 53 28 mov 0x28(%rbx),%rdx + 418c6d: 48 3b 5a 20 cmp 0x20(%rdx),%rbx + 418c71: 0f 85 84 0a 00 00 jne 4196fb + 418c77: 49 83 7c 24 20 00 cmpq $0x0,0x20(%r12) + 418c7d: 0f 84 4c 0a 00 00 je 4196cf + 418c83: 48 8b 53 28 mov 0x28(%rbx),%rdx + 418c87: 48 89 50 28 mov %rdx,0x28(%rax) + 418c8b: 48 8b 53 28 mov 0x28(%rbx),%rdx + 418c8f: 48 89 42 20 mov %rax,0x20(%rdx) + 418c93: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 418c98: 4c 3b 35 b9 1b 2b 00 cmp 0x2b1bb9(%rip),%r14 # 6ca858 + 418c9f: 0f 84 b8 05 00 00 je 41925d + 418ca5: 43 f6 44 3e 08 01 testb $0x1,0x8(%r14,%r15,1) + 418cab: 0f 85 97 04 00 00 jne 419148 + 418cb1: 49 8b 46 08 mov 0x8(%r14),%rax + 418cb5: 48 83 e0 f8 and $0xfffffffffffffff8,%rax + 418cb9: 49 3b 04 06 cmp (%r14,%rax,1),%rax + 418cbd: 0f 85 f8 06 00 00 jne 4193bb + 418cc3: 4d 8b 66 10 mov 0x10(%r14),%r12 + 418cc7: 49 8b 46 18 mov 0x18(%r14),%rax + 418ccb: 4d 3b 74 24 18 cmp 0x18(%r12),%r14 + 418cd0: 0f 85 2a 06 00 00 jne 419300 + 418cd6: 4c 3b 70 10 cmp 0x10(%rax),%r14 + 418cda: 0f 85 20 06 00 00 jne 419300 + 418ce0: 49 81 7e 08 ff 03 00 cmpq $0x3ff,0x8(%r14) + 418ce7: 00 + 418ce8: 49 89 44 24 18 mov %rax,0x18(%r12) + 418ced: 4c 89 60 10 mov %r12,0x10(%rax) + 418cf1: 76 0d jbe 418d00 + 418cf3: 49 8b 46 20 mov 0x20(%r14),%rax + 418cf7: 48 85 c0 test %rax,%rax + 418cfa: 0f 85 3b 08 00 00 jne 41953b + 418d00: 4c 01 fd add %r15,%rbp + 418d03: 48 8b 05 5e 1b 2b 00 mov 0x2b1b5e(%rip),%rax # 6ca868 + 418d0a: 44 8b 2d f3 1a 2b 00 mov 0x2b1af3(%rip),%r13d # 6ca804 + 418d11: 41 bc 48 24 4a 00 mov $0x4a2448,%r12d + 418d17: 48 81 78 18 58 a8 6c cmpq $0x6ca858,0x18(%rax) + 418d1e: 00 + 418d1f: 0f 85 cd 02 00 00 jne 418ff2 + 418d25: 48 81 fd ff 03 00 00 cmp $0x3ff,%rbp + 418d2c: 48 89 43 10 mov %rax,0x10(%rbx) + 418d30: 48 c7 43 18 58 a8 6c movq $0x6ca858,0x18(%rbx) + 418d37: 00 + 418d38: 76 10 jbe 418d4a + 418d3a: 48 c7 43 20 00 00 00 movq $0x0,0x20(%rbx) + 418d41: 00 + 418d42: 48 c7 43 28 00 00 00 movq $0x0,0x28(%rbx) + 418d49: 00 + 418d4a: 48 89 1d 17 1b 2b 00 mov %rbx,0x2b1b17(%rip) # 6ca868 + 418d51: 48 89 58 18 mov %rbx,0x18(%rax) + 418d55: 48 89 e8 mov %rbp,%rax + 418d58: 48 83 c8 01 or $0x1,%rax + 418d5c: 48 89 43 08 mov %rax,0x8(%rbx) + 418d60: 48 89 2c 2b mov %rbp,(%rbx,%rbp,1) + 418d64: 48 81 fd ff ff 00 00 cmp $0xffff,%rbp + 418d6b: 0f 86 af 02 00 00 jbe 419020 + 418d71: f6 05 8c 1a 2b 00 01 testb $0x1,0x2b1a8c(%rip) # 6ca804 + 418d78: 0f 84 23 05 00 00 je 4192a1 + 418d7e: 48 8b 05 d3 1a 2b 00 mov 0x2b1ad3(%rip),%rax # 6ca858 + 418d85: 48 8b 40 08 mov 0x8(%rax),%rax + 418d89: 48 83 e0 f8 and $0xfffffffffffffff8,%rax + 418d8d: 48 3b 05 0c 1a 2b 00 cmp 0x2b1a0c(%rip),%rax # 6ca7a0 + 418d94: 0f 82 86 02 00 00 jb 419020 + 418d9a: 48 8b 3d 07 1a 2b 00 mov 0x2b1a07(%rip),%rdi # 6ca7a8 + 418da1: ba 80 b0 6c 00 mov $0x6cb080,%edx + 418da6: be 58 a8 6c 00 mov $0x6ca858,%esi + 418dab: e8 f0 e5 ff ff callq 4173a0 + 418db0: e9 6b 02 00 00 jmpq 419020 + 418db5: 0f 1f 00 nopl (%rax) + 418db8: 83 3d fd 43 2b 00 00 cmpl $0x0,0x2b43fd(%rip) # 6cd1bc <__libc_multiple_threads> + 418dbf: 74 0b je 418dcc + 418dc1: f0 ff 0d 38 1a 2b 00 lock decl 0x2b1a38(%rip) # 6ca800 + 418dc8: 75 0a jne 418dd4 + 418dca: eb 22 jmp 418dee + 418dcc: ff 0d 2e 1a 2b 00 decl 0x2b1a2e(%rip) # 6ca800 + 418dd2: 74 1a je 418dee + 418dd4: 48 8d 3d 25 1a 2b 00 lea 0x2b1a25(%rip),%rdi # 6ca800 + 418ddb: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 418de2: e8 19 98 02 00 callq 442600 <__lll_unlock_wake_private> + 418de7: 48 81 c4 80 00 00 00 add $0x80,%rsp + 418dee: 48 89 df mov %rbx,%rdi + 418df1: e8 fa ee ff ff callq 417cf0 + 418df6: 48 83 c4 38 add $0x38,%rsp + 418dfa: 5b pop %rbx + 418dfb: 5d pop %rbp + 418dfc: 41 5c pop %r12 + 418dfe: 41 5d pop %r13 + 418e00: 41 5e pop %r14 + 418e02: 41 5f pop %r15 + 418e04: f3 c3 repz retq + 418e06: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 418e0d: 00 00 00 + 418e10: 8b 0d ee 19 2b 00 mov 0x2b19ee(%rip),%ecx # 6ca804 + 418e16: 83 e1 02 and $0x2,%ecx + 418e19: 75 1c jne 418e37 + 418e1b: 48 8b 35 ce 19 2b 00 mov 0x2b19ce(%rip),%rsi # 6ca7f0 + 418e22: 48 39 f3 cmp %rsi,%rbx + 418e25: 72 51 jb 418e78 + 418e27: 48 03 35 52 22 2b 00 add 0x2b2252(%rip),%rsi # 6cb080 + 418e2e: 4c 8d 0c 13 lea (%rbx,%rdx,1),%r9 + 418e32: 49 39 f1 cmp %rsi,%r9 + 418e35: 73 41 jae 418e78 + 418e37: 48 83 fa 1f cmp $0x1f,%rdx + 418e3b: 76 3b jbe 418e78 + 418e3d: a8 08 test $0x8,%al + 418e3f: 75 37 jne 418e78 + 418e41: 41 f6 44 10 f8 01 testb $0x1,-0x8(%r8,%rdx,1) + 418e47: 74 2f je 418e78 + 418e49: a8 01 test $0x1,%al + 418e4b: 0f 85 8f 00 00 00 jne 418ee0 + 418e51: 49 8b 40 f0 mov -0x10(%r8),%rax + 418e55: a8 0f test $0xf,%al + 418e57: 75 1f jne 418e78 + 418e59: 85 c9 test %ecx,%ecx + 418e5b: 48 89 d9 mov %rbx,%rcx + 418e5e: 0f 84 a4 02 00 00 je 419108 + 418e64: 48 29 c1 sub %rax,%rcx + 418e67: 48 8b 49 08 mov 0x8(%rcx),%rcx + 418e6b: 48 83 e1 f8 and $0xfffffffffffffff8,%rcx + 418e6f: 48 39 c8 cmp %rcx,%rax + 418e72: 74 6c je 418ee0 + 418e74: 0f 1f 40 00 nopl 0x0(%rax) + 418e78: 83 3d 3d 43 2b 00 00 cmpl $0x0,0x2b433d(%rip) # 6cd1bc <__libc_multiple_threads> + 418e7f: 74 0b je 418e8c + 418e81: f0 ff 0d 78 19 2b 00 lock decl 0x2b1978(%rip) # 6ca800 + 418e88: 75 0a jne 418e94 + 418e8a: eb 22 jmp 418eae + 418e8c: ff 0d 6e 19 2b 00 decl 0x2b196e(%rip) # 6ca800 + 418e92: 74 1a je 418eae + 418e94: 48 8d 3d 65 19 2b 00 lea 0x2b1965(%rip),%rdi # 6ca800 + 418e9b: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 418ea2: e8 59 97 02 00 callq 442600 <__lll_unlock_wake_private> + 418ea7: 48 81 c4 80 00 00 00 add $0x80,%rsp + 418eae: 8b 1d bc 18 2b 00 mov 0x2b18bc(%rip),%ebx # 6ca770 + 418eb4: 83 0d 49 19 2b 00 04 orl $0x4,0x2b1949(%rip) # 6ca804 + 418ebb: 89 d8 mov %ebx,%eax + 418ebd: 83 e0 05 and $0x5,%eax + 418ec0: 83 f8 05 cmp $0x5,%eax + 418ec3: 0f 84 d7 04 00 00 je 4193a0 + 418ec9: f6 c3 01 test $0x1,%bl + 418ecc: 0f 85 80 02 00 00 jne 419152 + 418ed2: 83 e3 02 and $0x2,%ebx + 418ed5: 0f 84 1b ff ff ff je 418df6 + 418edb: e8 20 4d ff ff callq 40dc00 + 418ee0: 48 83 c2 07 add $0x7,%rdx + 418ee4: 40 0f b6 ff movzbl %dil,%edi + 418ee8: 48 8d 34 13 lea (%rbx,%rdx,1),%rsi + 418eec: 0f b6 06 movzbl (%rsi),%eax + 418eef: 48 39 f8 cmp %rdi,%rax + 418ef2: 48 89 c1 mov %rax,%rcx + 418ef5: 0f 84 4d fc ff ff je 418b48 + 418efb: 48 85 c0 test %rax,%rax + 418efe: 0f 84 74 ff ff ff je 418e78 + 418f04: 48 8d 48 10 lea 0x10(%rax),%rcx + 418f08: 48 39 ca cmp %rcx,%rdx + 418f0b: 73 21 jae 418f2e + 418f0d: e9 66 ff ff ff jmpq 418e78 + 418f12: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 418f18: 48 85 c0 test %rax,%rax + 418f1b: 0f 84 57 ff ff ff je 418e78 + 418f21: 48 8d 48 10 lea 0x10(%rax),%rcx + 418f25: 48 39 d1 cmp %rdx,%rcx + 418f28: 0f 87 4a ff ff ff ja 418e78 + 418f2e: 48 29 c2 sub %rax,%rdx + 418f31: 48 8d 34 13 lea (%rbx,%rdx,1),%rsi + 418f35: 0f b6 06 movzbl (%rsi),%eax + 418f38: 48 39 f8 cmp %rdi,%rax + 418f3b: 48 89 c1 mov %rax,%rcx + 418f3e: 75 d8 jne 418f18 + 418f40: e9 03 fc ff ff jmpq 418b48 + 418f45: 0f 1f 00 nopl (%rax) + 418f48: 49 8b 44 28 f8 mov -0x8(%r8,%rbp,1),%rax + 418f4d: 48 83 f8 10 cmp $0x10,%rax + 418f51: 0f 86 a1 02 00 00 jbe 4191f8 + 418f57: 48 83 e0 f8 and $0xfffffffffffffff8,%rax + 418f5b: 48 3b 05 1e 21 2b 00 cmp 0x2b211e(%rip),%rax # 6cb080 + 418f62: 0f 83 90 02 00 00 jae 4191f8 + 418f68: 8b 35 c6 36 2b 00 mov 0x2b36c6(%rip),%esi # 6cc634 + 418f6e: 85 f6 test %esi,%esi + 418f70: 0f 85 c8 02 00 00 jne 41923e + 418f76: 64 83 3c 25 18 00 00 cmpl $0x0,%fs:0x18 + 418f7d: 00 00 + 418f7f: 74 01 je 418f82 + 418f81: f0 83 25 7b 18 2b 00 lock andl $0xfffffffe,0x2b187b(%rip) # 6ca804 + 418f88: fe + 418f89: c1 ed 04 shr $0x4,%ebp + 418f8c: be ff ff ff ff mov $0xffffffff,%esi + 418f91: 8d 45 fe lea -0x2(%rbp),%eax + 418f94: 48 8b 14 c5 08 a8 6c mov 0x6ca808(,%rax,8),%rdx + 418f9b: 00 + 418f9c: 48 89 c5 mov %rax,%rbp + 418f9f: 48 8d 0c c5 08 a8 6c lea 0x6ca808(,%rax,8),%rcx + 418fa6: 00 + 418fa7: 48 39 d3 cmp %rdx,%rbx + 418faa: 75 07 jne 418fb3 + 418fac: eb 37 jmp 418fe5 + 418fae: 66 90 xchg %ax,%ax + 418fb0: 48 89 c2 mov %rax,%rdx + 418fb3: 48 85 d2 test %rdx,%rdx + 418fb6: 74 09 je 418fc1 + 418fb8: 8b 42 08 mov 0x8(%rdx),%eax + 418fbb: c1 e8 04 shr $0x4,%eax + 418fbe: 8d 70 fe lea -0x2(%rax),%esi + 418fc1: 49 89 10 mov %rdx,(%r8) + 418fc4: 48 89 d0 mov %rdx,%rax + 418fc7: 64 83 3c 25 18 00 00 cmpl $0x0,%fs:0x18 + 418fce: 00 00 + 418fd0: 74 01 je 418fd3 + 418fd2: f0 48 0f b1 19 lock cmpxchg %rbx,(%rcx) + 418fd7: 48 39 d0 cmp %rdx,%rax + 418fda: 0f 84 30 02 00 00 je 419210 + 418fe0: 48 39 c3 cmp %rax,%rbx + 418fe3: 75 cb jne 418fb0 + 418fe5: 44 8b 2d 18 18 2b 00 mov 0x2b1818(%rip),%r13d # 6ca804 + 418fec: 41 bc 70 24 4a 00 mov $0x4a2470,%r12d + 418ff2: 8b 2d 78 17 2b 00 mov 0x2b1778(%rip),%ebp # 6ca770 + 418ff8: 41 83 cd 04 or $0x4,%r13d + 418ffc: 44 89 2d 01 18 2b 00 mov %r13d,0x2b1801(%rip) # 6ca804 + 419003: 89 e8 mov %ebp,%eax + 419005: 83 e0 05 and $0x5,%eax + 419008: 83 f8 05 cmp $0x5,%eax + 41900b: 0f 84 c7 01 00 00 je 4191d8 + 419011: 40 f6 c5 01 test $0x1,%bpl + 419015: 75 59 jne 419070 + 419017: 83 e5 02 and $0x2,%ebp + 41901a: 0f 85 bb fe ff ff jne 418edb + 419020: 83 3d 95 41 2b 00 00 cmpl $0x0,0x2b4195(%rip) # 6cd1bc <__libc_multiple_threads> + 419027: 74 0b je 419034 + 419029: f0 ff 0d d0 17 2b 00 lock decl 0x2b17d0(%rip) # 6ca800 + 419030: 75 0a jne 41903c + 419032: eb 22 jmp 419056 + 419034: ff 0d c6 17 2b 00 decl 0x2b17c6(%rip) # 6ca800 + 41903a: 74 1a je 419056 + 41903c: 48 8d 3d bd 17 2b 00 lea 0x2b17bd(%rip),%rdi # 6ca800 + 419043: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41904a: e8 b1 95 02 00 callq 442600 <__lll_unlock_wake_private> + 41904f: 48 81 c4 80 00 00 00 add $0x80,%rsp + 419056: e9 9b fd ff ff jmpq 418df6 + 41905b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 419060: 44 8b 2d 9d 17 2b 00 mov 0x2b179d(%rip),%r13d # 6ca804 + 419067: 41 bc b2 20 4a 00 mov $0x4a20b2,%r12d + 41906d: eb 83 jmp 418ff2 + 41906f: 90 nop + 419070: 48 8d 7b 10 lea 0x10(%rbx),%rdi + 419074: 4c 8d 6c 24 10 lea 0x10(%rsp),%r13 + 419079: 48 8d 74 24 20 lea 0x20(%rsp),%rsi + 41907e: 31 c9 xor %ecx,%ecx + 419080: ba 10 00 00 00 mov $0x10,%edx + 419085: c6 44 24 20 00 movb $0x0,0x20(%rsp) + 41908a: e8 21 8e 03 00 callq 451eb0 <_itoa_word> + 41908f: 4c 39 e8 cmp %r13,%rax + 419092: 48 89 c3 mov %rax,%rbx + 419095: 76 25 jbe 4190bc + 419097: 48 89 c2 mov %rax,%rdx + 41909a: 48 89 c7 mov %rax,%rdi + 41909d: be 30 00 00 00 mov $0x30,%esi + 4190a2: 4c 29 ea sub %r13,%rdx + 4190a5: 4c 8d 70 ff lea -0x1(%rax),%r14 + 4190a9: 48 29 d7 sub %rdx,%rdi + 4190ac: e8 9f 72 fe ff callq 400350 <__rela_iplt_end+0x88> + 4190b1: 48 8d 44 24 0f lea 0xf(%rsp),%rax + 4190b6: 4c 29 f0 sub %r14,%rax + 4190b9: 48 01 c3 add %rax,%rbx + 4190bc: 48 8b 05 fd 41 2b 00 mov 0x2b41fd(%rip),%rax # 6cd2c0 <__libc_argv> + 4190c3: 89 ef mov %ebp,%edi + 4190c5: ba 38 20 4a 00 mov $0x4a2038,%edx + 4190ca: 49 89 d8 mov %rbx,%r8 + 4190cd: 4c 89 e1 mov %r12,%rcx + 4190d0: be a8 23 4a 00 mov $0x4a23a8,%esi + 4190d5: 48 8b 00 mov (%rax),%rax + 4190d8: 48 85 c0 test %rax,%rax + 4190db: 48 0f 45 d0 cmovne %rax,%rdx + 4190df: 83 e7 02 and $0x2,%edi + 4190e2: 31 c0 xor %eax,%eax + 4190e4: e8 d7 84 ff ff callq 4115c0 <__libc_message> + 4190e9: e9 32 ff ff ff jmpq 419020 + 4190ee: 66 90 xchg %ax,%ax + 4190f0: 44 8b 2d 0d 17 2b 00 mov 0x2b170d(%rip),%r13d # 6ca804 + 4190f7: 41 bc ca 20 4a 00 mov $0x4a20ca,%r12d + 4190fd: e9 f0 fe ff ff jmpq 418ff2 + 419102: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 419108: 48 29 c1 sub %rax,%rcx + 41910b: 48 3b 0d de 16 2b 00 cmp 0x2b16de(%rip),%rcx # 6ca7f0 + 419112: 0f 83 4f fd ff ff jae 418e67 + 419118: e9 5b fd ff ff jmpq 418e78 + 41911d: 0f 1f 00 nopl (%rax) + 419120: 48 8d b0 00 fc ff ff lea -0x400(%rax),%rsi + 419127: 48 f7 c6 ff fb ff ff test $0xfffffffffffffbff,%rsi + 41912e: 0f 84 94 f9 ff ff je 418ac8 + 419134: 48 3d 00 10 00 00 cmp $0x1000,%rax + 41913a: 0f 84 88 f9 ff ff je 418ac8 + 419140: e9 33 fd ff ff jmpq 418e78 + 419145: 0f 1f 00 nopl (%rax) + 419148: 49 83 66 08 fe andq $0xfffffffffffffffe,0x8(%r14) + 41914d: e9 b1 fb ff ff jmpq 418d03 + 419152: 4c 8d 64 24 10 lea 0x10(%rsp),%r12 + 419157: 48 8d 74 24 20 lea 0x20(%rsp),%rsi + 41915c: 31 c9 xor %ecx,%ecx + 41915e: ba 10 00 00 00 mov $0x10,%edx + 419163: 4c 89 c7 mov %r8,%rdi + 419166: c6 44 24 20 00 movb $0x0,0x20(%rsp) + 41916b: e8 40 8d 03 00 callq 451eb0 <_itoa_word> + 419170: 4c 39 e0 cmp %r12,%rax + 419173: 48 89 c5 mov %rax,%rbp + 419176: 76 25 jbe 41919d + 419178: 48 89 c2 mov %rax,%rdx + 41917b: 48 89 c7 mov %rax,%rdi + 41917e: be 30 00 00 00 mov $0x30,%esi + 419183: 4c 29 e2 sub %r12,%rdx + 419186: 4c 8d 68 ff lea -0x1(%rax),%r13 + 41918a: 48 29 d7 sub %rdx,%rdi + 41918d: e8 be 71 fe ff callq 400350 <__rela_iplt_end+0x88> + 419192: 48 8d 44 24 0f lea 0xf(%rsp),%rax + 419197: 4c 29 e8 sub %r13,%rax + 41919a: 48 01 c5 add %rax,%rbp + 41919d: 48 8b 05 1c 41 2b 00 mov 0x2b411c(%rip),%rax # 6cd2c0 <__libc_argv> + 4191a4: ba 38 20 4a 00 mov $0x4a2038,%edx + 4191a9: 49 89 e8 mov %rbp,%r8 + 4191ac: b9 b2 20 4a 00 mov $0x4a20b2,%ecx + 4191b1: be a8 23 4a 00 mov $0x4a23a8,%esi + 4191b6: 48 8b 00 mov (%rax),%rax + 4191b9: 48 85 c0 test %rax,%rax + 4191bc: 48 0f 45 d0 cmovne %rax,%rdx + 4191c0: 83 e3 02 and $0x2,%ebx + 4191c3: 31 c0 xor %eax,%eax + 4191c5: 89 df mov %ebx,%edi + 4191c7: e8 f4 83 ff ff callq 4115c0 <__libc_message> + 4191cc: e9 25 fc ff ff jmpq 418df6 + 4191d1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4191d8: 89 ef mov %ebp,%edi + 4191da: 4c 89 e2 mov %r12,%rdx + 4191dd: be 3c ca 4b 00 mov $0x4bca3c,%esi + 4191e2: 83 e7 02 and $0x2,%edi + 4191e5: 31 c0 xor %eax,%eax + 4191e7: e8 d4 83 ff ff callq 4115c0 <__libc_message> + 4191ec: e9 2f fe ff ff jmpq 419020 + 4191f1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4191f8: 44 8b 2d 05 16 2b 00 mov 0x2b1605(%rip),%r13d # 6ca804 + 4191ff: 41 bc 20 24 4a 00 mov $0x4a2420,%r12d + 419205: e9 e8 fd ff ff jmpq 418ff2 + 41920a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 419210: 39 f5 cmp %esi,%ebp + 419212: 0f 84 08 fe ff ff je 419020 + 419218: 48 85 d2 test %rdx,%rdx + 41921b: 44 8b 2d e2 15 2b 00 mov 0x2b15e2(%rip),%r13d # 6ca804 + 419222: 41 bc df 20 4a 00 mov $0x4a20df,%r12d + 419228: 0f 84 f2 fd ff ff je 419020 + 41922e: e9 bf fd ff ff jmpq 418ff2 + 419233: 41 bc 00 25 4a 00 mov $0x4a2500,%r12d + 419239: e9 b4 fd ff ff jmpq 418ff2 + 41923e: 48 8d 55 f0 lea -0x10(%rbp),%rdx + 419242: 4c 89 c7 mov %r8,%rdi + 419245: e8 06 71 fe ff callq 400350 <__rela_iplt_end+0x88> + 41924a: 49 89 c0 mov %rax,%r8 + 41924d: e9 24 fd ff ff jmpq 418f76 + 419252: 41 bc 98 24 4a 00 mov $0x4a2498,%r12d + 419258: e9 95 fd ff ff jmpq 418ff2 + 41925d: 4c 01 fd add %r15,%rbp + 419260: 48 89 e8 mov %rbp,%rax + 419263: 48 83 c8 01 or $0x1,%rax + 419267: 48 89 43 08 mov %rax,0x8(%rbx) + 41926b: 48 89 1d e6 15 2b 00 mov %rbx,0x2b15e6(%rip) # 6ca858 + 419272: e9 ed fa ff ff jmpq 418d64 + 419277: 48 8b 50 08 mov 0x8(%rax),%rdx + 41927b: 48 83 e2 f8 and $0xfffffffffffffff8,%rdx + 41927f: 48 01 d0 add %rdx,%rax + 419282: 49 39 c6 cmp %rax,%r14 + 419285: 0f 82 3d f9 ff ff jb 418bc8 + 41928b: 41 bc b8 24 4a 00 mov $0x4a24b8,%r12d + 419291: e9 5c fd ff ff jmpq 418ff2 + 419296: 41 bc d8 24 4a 00 mov $0x4a24d8,%r12d + 41929c: e9 51 fd ff ff jmpq 418ff2 + 4192a1: bf 00 a8 6c 00 mov $0x6ca800,%edi + 4192a6: e8 85 eb ff ff callq 417e30 + 4192ab: e9 ce fa ff ff jmpq 418d7e + 4192b0: 48 8d 55 f0 lea -0x10(%rbp),%rdx + 4192b4: 4c 89 c7 mov %r8,%rdi + 4192b7: e8 94 70 fe ff callq 400350 <__rela_iplt_end+0x88> + 4192bc: 49 89 c0 mov %rax,%r8 + 4192bf: e9 3c f9 ff ff jmpq 418c00 + 4192c4: 44 8b 0d a5 14 2b 00 mov 0x2b14a5(%rip),%r9d # 6ca770 + 4192cb: 83 0d 32 15 2b 00 04 orl $0x4,0x2b1532(%rip) # 6ca804 + 4192d2: 44 89 c8 mov %r9d,%eax + 4192d5: 83 e0 05 and $0x5,%eax + 4192d8: 83 f8 05 cmp $0x5,%eax + 4192db: 0f 84 d2 03 00 00 je 4196b3 + 4192e1: 41 f6 c1 01 test $0x1,%r9b + 4192e5: 0f 85 31 01 00 00 jne 41941c + 4192eb: 41 83 e1 02 and $0x2,%r9d + 4192ef: 0f 84 a3 f9 ff ff je 418c98 + 4192f5: e9 e1 fb ff ff jmpq 418edb + 4192fa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 419300: 44 8b 2d 69 14 2b 00 mov 0x2b1469(%rip),%r13d # 6ca770 + 419307: 83 0d f6 14 2b 00 04 orl $0x4,0x2b14f6(%rip) # 6ca804 + 41930e: 44 89 e8 mov %r13d,%eax + 419311: 83 e0 05 and $0x5,%eax + 419314: 83 f8 05 cmp $0x5,%eax + 419317: 0f 84 7a 03 00 00 je 419697 + 41931d: 41 f6 c5 01 test $0x1,%r13b + 419321: 0f 85 8c 01 00 00 jne 4194b3 + 419327: 41 83 e5 02 and $0x2,%r13d + 41932b: 0f 84 cf f9 ff ff je 418d00 + 419331: e9 a5 fb ff ff jmpq 418edb + 419336: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41933d: 00 00 00 + 419340: 44 8b 0d 29 14 2b 00 mov 0x2b1429(%rip),%r9d # 6ca770 + 419347: 41 83 cd 04 or $0x4,%r13d + 41934b: 44 89 2d b2 14 2b 00 mov %r13d,0x2b14b2(%rip) # 6ca804 + 419352: 44 89 c8 mov %r9d,%eax + 419355: 83 e0 05 and $0x5,%eax + 419358: 83 f8 05 cmp $0x5,%eax + 41935b: 0f 84 bb 03 00 00 je 41971c + 419361: 41 f6 c1 01 test $0x1,%r9b + 419365: 0f 85 09 02 00 00 jne 419574 + 41936b: 41 f6 c1 02 test $0x2,%r9b + 41936f: 0f 85 66 fb ff ff jne 418edb + 419375: 4c 8b 63 10 mov 0x10(%rbx),%r12 + 419379: 48 8b 43 18 mov 0x18(%rbx),%rax + 41937d: 49 39 5c 24 18 cmp %rbx,0x18(%r12) + 419382: 0f 85 63 ff ff ff jne 4192eb + 419388: 48 3b 58 10 cmp 0x10(%rax),%rbx + 41938c: 0f 84 b1 f8 ff ff je 418c43 + 419392: 44 89 2d 6b 14 2b 00 mov %r13d,0x2b146b(%rip) # 6ca804 + 419399: e9 43 ff ff ff jmpq 4192e1 + 41939e: 66 90 xchg %ax,%ax + 4193a0: 83 e3 02 and $0x2,%ebx + 4193a3: ba b2 20 4a 00 mov $0x4a20b2,%edx + 4193a8: be 3c ca 4b 00 mov $0x4bca3c,%esi + 4193ad: 89 df mov %ebx,%edi + 4193af: 31 c0 xor %eax,%eax + 4193b1: e8 0a 82 ff ff callq 4115c0 <__libc_message> + 4193b6: e9 3b fa ff ff jmpq 418df6 + 4193bb: 44 8b 2d ae 13 2b 00 mov 0x2b13ae(%rip),%r13d # 6ca770 + 4193c2: 8b 15 3c 14 2b 00 mov 0x2b143c(%rip),%edx # 6ca804 + 4193c8: 44 89 e8 mov %r13d,%eax + 4193cb: 83 ca 04 or $0x4,%edx + 4193ce: 83 e0 05 and $0x5,%eax + 4193d1: 89 15 2d 14 2b 00 mov %edx,0x2b142d(%rip) # 6ca804 + 4193d7: 83 f8 05 cmp $0x5,%eax + 4193da: 0f 84 58 03 00 00 je 419738 + 4193e0: 41 f6 c5 01 test $0x1,%r13b + 4193e4: 0f 85 21 02 00 00 jne 41960b + 4193ea: 41 f6 c5 02 test $0x2,%r13b + 4193ee: 0f 85 e7 fa ff ff jne 418edb + 4193f4: 4d 8b 66 10 mov 0x10(%r14),%r12 + 4193f8: 49 8b 46 18 mov 0x18(%r14),%rax + 4193fc: 4d 3b 74 24 18 cmp 0x18(%r12),%r14 + 419401: 0f 85 20 ff ff ff jne 419327 + 419407: 4c 3b 70 10 cmp 0x10(%rax),%r14 + 41940b: 0f 84 cf f8 ff ff je 418ce0 + 419411: 89 15 ed 13 2b 00 mov %edx,0x2b13ed(%rip) # 6ca804 + 419417: e9 01 ff ff ff jmpq 41931d + 41941c: 4c 8d 64 24 10 lea 0x10(%rsp),%r12 + 419421: 48 8d 74 24 20 lea 0x20(%rsp),%rsi + 419426: 31 c9 xor %ecx,%ecx + 419428: ba 10 00 00 00 mov $0x10,%edx + 41942d: 48 89 df mov %rbx,%rdi + 419430: 44 89 0c 24 mov %r9d,(%rsp) + 419434: c6 44 24 20 00 movb $0x0,0x20(%rsp) + 419439: e8 72 8a 03 00 callq 451eb0 <_itoa_word> + 41943e: 4c 39 e0 cmp %r12,%rax + 419441: 49 89 c5 mov %rax,%r13 + 419444: 44 8b 0c 24 mov (%rsp),%r9d + 419448: 76 34 jbe 41947e + 41944a: 4c 89 ea mov %r13,%rdx + 41944d: 48 8d 40 ff lea -0x1(%rax),%rax + 419451: 4c 89 ef mov %r13,%rdi + 419454: 4c 29 e2 sub %r12,%rdx + 419457: be 30 00 00 00 mov $0x30,%esi + 41945c: 44 89 4c 24 08 mov %r9d,0x8(%rsp) + 419461: 48 29 d7 sub %rdx,%rdi + 419464: 48 89 04 24 mov %rax,(%rsp) + 419468: e8 e3 6e fe ff callq 400350 <__rela_iplt_end+0x88> + 41946d: 48 8d 44 24 0f lea 0xf(%rsp),%rax + 419472: 48 2b 04 24 sub (%rsp),%rax + 419476: 44 8b 4c 24 08 mov 0x8(%rsp),%r9d + 41947b: 49 01 c5 add %rax,%r13 + 41947e: 48 8b 05 3b 3e 2b 00 mov 0x2b3e3b(%rip),%rax # 6cd2c0 <__libc_argv> + 419485: 44 89 cf mov %r9d,%edi + 419488: ba 38 20 4a 00 mov $0x4a2038,%edx + 41948d: 4d 89 e8 mov %r13,%r8 + 419490: b9 95 20 4a 00 mov $0x4a2095,%ecx + 419495: be a8 23 4a 00 mov $0x4a23a8,%esi + 41949a: 48 8b 00 mov (%rax),%rax + 41949d: 48 85 c0 test %rax,%rax + 4194a0: 48 0f 45 d0 cmovne %rax,%rdx + 4194a4: 83 e7 02 and $0x2,%edi + 4194a7: 31 c0 xor %eax,%eax + 4194a9: e8 12 81 ff ff callq 4115c0 <__libc_message> + 4194ae: e9 e5 f7 ff ff jmpq 418c98 + 4194b3: 4c 8d 44 24 10 lea 0x10(%rsp),%r8 + 4194b8: 48 8d 74 24 20 lea 0x20(%rsp),%rsi + 4194bd: 31 c9 xor %ecx,%ecx + 4194bf: ba 10 00 00 00 mov $0x10,%edx + 4194c4: 4c 89 f7 mov %r14,%rdi + 4194c7: c6 44 24 20 00 movb $0x0,0x20(%rsp) + 4194cc: 4c 89 04 24 mov %r8,(%rsp) + 4194d0: e8 db 89 03 00 callq 451eb0 <_itoa_word> + 4194d5: 4c 8b 04 24 mov (%rsp),%r8 + 4194d9: 49 89 c4 mov %rax,%r12 + 4194dc: 4c 39 c0 cmp %r8,%rax + 4194df: 76 25 jbe 419506 + 4194e1: 48 89 c2 mov %rax,%rdx + 4194e4: 48 89 c7 mov %rax,%rdi + 4194e7: be 30 00 00 00 mov $0x30,%esi + 4194ec: 4c 29 c2 sub %r8,%rdx + 4194ef: 4c 8d 70 ff lea -0x1(%rax),%r14 + 4194f3: 48 29 d7 sub %rdx,%rdi + 4194f6: e8 55 6e fe ff callq 400350 <__rela_iplt_end+0x88> + 4194fb: 48 8d 44 24 0f lea 0xf(%rsp),%rax + 419500: 4c 29 f0 sub %r14,%rax + 419503: 49 01 c4 add %rax,%r12 + 419506: 48 8b 05 b3 3d 2b 00 mov 0x2b3db3(%rip),%rax # 6cd2c0 <__libc_argv> + 41950d: 44 89 ef mov %r13d,%edi + 419510: ba 38 20 4a 00 mov $0x4a2038,%edx + 419515: 4d 89 e0 mov %r12,%r8 + 419518: b9 95 20 4a 00 mov $0x4a2095,%ecx + 41951d: be a8 23 4a 00 mov $0x4a23a8,%esi + 419522: 48 8b 00 mov (%rax),%rax + 419525: 48 85 c0 test %rax,%rax + 419528: 48 0f 45 d0 cmovne %rax,%rdx + 41952c: 83 e7 02 and $0x2,%edi + 41952f: 31 c0 xor %eax,%eax + 419531: e8 8a 80 ff ff callq 4115c0 <__libc_message> + 419536: e9 c5 f7 ff ff jmpq 418d00 + 41953b: 4c 3b 70 28 cmp 0x28(%rax),%r14 + 41953f: 0f 85 37 02 00 00 jne 41977c + 419545: 49 8b 56 28 mov 0x28(%r14),%rdx + 419549: 4c 3b 72 20 cmp 0x20(%rdx),%r14 + 41954d: 0f 85 29 02 00 00 jne 41977c + 419553: 49 83 7c 24 20 00 cmpq $0x0,0x20(%r12) + 419559: 0f 84 f5 01 00 00 je 419754 + 41955f: 49 8b 56 28 mov 0x28(%r14),%rdx + 419563: 48 89 50 28 mov %rdx,0x28(%rax) + 419567: 49 8b 56 28 mov 0x28(%r14),%rdx + 41956b: 48 89 42 20 mov %rax,0x20(%rdx) + 41956f: e9 8c f7 ff ff jmpq 418d00 + 419574: 4c 8d 64 24 10 lea 0x10(%rsp),%r12 + 419579: 48 8d 74 24 20 lea 0x20(%rsp),%rsi + 41957e: 31 c9 xor %ecx,%ecx + 419580: ba 10 00 00 00 mov $0x10,%edx + 419585: 48 89 df mov %rbx,%rdi + 419588: 44 89 0c 24 mov %r9d,(%rsp) + 41958c: c6 44 24 20 00 movb $0x0,0x20(%rsp) + 419591: e8 1a 89 03 00 callq 451eb0 <_itoa_word> + 419596: 4c 39 e0 cmp %r12,%rax + 419599: 49 89 c5 mov %rax,%r13 + 41959c: 44 8b 0c 24 mov (%rsp),%r9d + 4195a0: 76 34 jbe 4195d6 + 4195a2: 4c 89 ea mov %r13,%rdx + 4195a5: 48 8d 40 ff lea -0x1(%rax),%rax + 4195a9: 4c 89 ef mov %r13,%rdi + 4195ac: 4c 29 e2 sub %r12,%rdx + 4195af: be 30 00 00 00 mov $0x30,%esi + 4195b4: 44 89 4c 24 08 mov %r9d,0x8(%rsp) + 4195b9: 48 29 d7 sub %rdx,%rdi + 4195bc: 48 89 04 24 mov %rax,(%rsp) + 4195c0: e8 8b 6d fe ff callq 400350 <__rela_iplt_end+0x88> + 4195c5: 48 8d 44 24 0f lea 0xf(%rsp),%rax + 4195ca: 48 2b 04 24 sub (%rsp),%rax + 4195ce: 44 8b 4c 24 08 mov 0x8(%rsp),%r9d + 4195d3: 49 01 c5 add %rax,%r13 + 4195d6: 48 8b 05 e3 3c 2b 00 mov 0x2b3ce3(%rip),%rax # 6cd2c0 <__libc_argv> + 4195dd: 44 89 cf mov %r9d,%edi + 4195e0: ba 38 20 4a 00 mov $0x4a2038,%edx + 4195e5: 4d 89 e8 mov %r13,%r8 + 4195e8: b9 78 20 4a 00 mov $0x4a2078,%ecx + 4195ed: be a8 23 4a 00 mov $0x4a23a8,%esi + 4195f2: 48 8b 00 mov (%rax),%rax + 4195f5: 48 85 c0 test %rax,%rax + 4195f8: 48 0f 45 d0 cmovne %rax,%rdx + 4195fc: 83 e7 02 and $0x2,%edi + 4195ff: 31 c0 xor %eax,%eax + 419601: e8 ba 7f ff ff callq 4115c0 <__libc_message> + 419606: e9 1b f6 ff ff jmpq 418c26 + 41960b: 4c 8d 64 24 10 lea 0x10(%rsp),%r12 + 419610: 48 8d 74 24 20 lea 0x20(%rsp),%rsi + 419615: 31 c9 xor %ecx,%ecx + 419617: ba 10 00 00 00 mov $0x10,%edx + 41961c: 4c 89 f7 mov %r14,%rdi + 41961f: c6 44 24 20 00 movb $0x0,0x20(%rsp) + 419624: e8 87 88 03 00 callq 451eb0 <_itoa_word> + 419629: 4c 39 e0 cmp %r12,%rax + 41962c: 49 89 c0 mov %rax,%r8 + 41962f: 76 34 jbe 419665 + 419631: 4c 89 c2 mov %r8,%rdx + 419634: 4c 89 c7 mov %r8,%rdi + 419637: 48 8d 40 ff lea -0x1(%rax),%rax + 41963b: 4c 29 e2 sub %r12,%rdx + 41963e: be 30 00 00 00 mov $0x30,%esi + 419643: 4c 89 44 24 08 mov %r8,0x8(%rsp) + 419648: 48 29 d7 sub %rdx,%rdi + 41964b: 48 89 04 24 mov %rax,(%rsp) + 41964f: e8 fc 6c fe ff callq 400350 <__rela_iplt_end+0x88> + 419654: 48 8d 44 24 0f lea 0xf(%rsp),%rax + 419659: 48 2b 04 24 sub (%rsp),%rax + 41965d: 4c 8b 44 24 08 mov 0x8(%rsp),%r8 + 419662: 49 01 c0 add %rax,%r8 + 419665: 48 8b 05 54 3c 2b 00 mov 0x2b3c54(%rip),%rax # 6cd2c0 <__libc_argv> + 41966c: 44 89 ef mov %r13d,%edi + 41966f: ba 38 20 4a 00 mov $0x4a2038,%edx + 419674: b9 78 20 4a 00 mov $0x4a2078,%ecx + 419679: be a8 23 4a 00 mov $0x4a23a8,%esi + 41967e: 48 8b 00 mov (%rax),%rax + 419681: 48 85 c0 test %rax,%rax + 419684: 48 0f 45 d0 cmovne %rax,%rdx + 419688: 83 e7 02 and $0x2,%edi + 41968b: 31 c0 xor %eax,%eax + 41968d: e8 2e 7f ff ff callq 4115c0 <__libc_message> + 419692: e9 2c f6 ff ff jmpq 418cc3 + 419697: 44 89 ef mov %r13d,%edi + 41969a: ba 95 20 4a 00 mov $0x4a2095,%edx + 41969f: be 3c ca 4b 00 mov $0x4bca3c,%esi + 4196a4: 83 e7 02 and $0x2,%edi + 4196a7: 31 c0 xor %eax,%eax + 4196a9: e8 12 7f ff ff callq 4115c0 <__libc_message> + 4196ae: e9 4d f6 ff ff jmpq 418d00 + 4196b3: 44 89 cf mov %r9d,%edi + 4196b6: ba 95 20 4a 00 mov $0x4a2095,%edx + 4196bb: be 3c ca 4b 00 mov $0x4bca3c,%esi + 4196c0: 83 e7 02 and $0x2,%edi + 4196c3: 31 c0 xor %eax,%eax + 4196c5: e8 f6 7e ff ff callq 4115c0 <__libc_message> + 4196ca: e9 c9 f5 ff ff jmpq 418c98 + 4196cf: 48 39 c3 cmp %rax,%rbx + 4196d2: 0f 84 c5 00 00 00 je 41979d + 4196d8: 49 89 44 24 20 mov %rax,0x20(%r12) + 4196dd: 48 8b 43 28 mov 0x28(%rbx),%rax + 4196e1: 49 89 44 24 28 mov %rax,0x28(%r12) + 4196e6: 48 8b 43 20 mov 0x20(%rbx),%rax + 4196ea: 4c 89 60 28 mov %r12,0x28(%rax) + 4196ee: 48 8b 43 28 mov 0x28(%rbx),%rax + 4196f2: 4c 89 60 20 mov %r12,0x20(%rax) + 4196f6: e9 9d f5 ff ff jmpq 418c98 + 4196fb: 8b 3d 6f 10 2b 00 mov 0x2b106f(%rip),%edi # 6ca770 + 419701: b9 00 a8 6c 00 mov $0x6ca800,%ecx + 419706: 48 89 da mov %rbx,%rdx + 419709: be f0 23 4a 00 mov $0x4a23f0,%esi + 41970e: e8 9d db ff ff callq 4172b0 + 419713: 48 8b 43 20 mov 0x20(%rbx),%rax + 419717: e9 5b f5 ff ff jmpq 418c77 + 41971c: 44 89 cf mov %r9d,%edi + 41971f: ba 78 20 4a 00 mov $0x4a2078,%edx + 419724: be 3c ca 4b 00 mov $0x4bca3c,%esi + 419729: 83 e7 02 and $0x2,%edi + 41972c: 31 c0 xor %eax,%eax + 41972e: e8 8d 7e ff ff callq 4115c0 <__libc_message> + 419733: e9 ee f4 ff ff jmpq 418c26 + 419738: 44 89 ef mov %r13d,%edi + 41973b: ba 78 20 4a 00 mov $0x4a2078,%edx + 419740: be 3c ca 4b 00 mov $0x4bca3c,%esi + 419745: 83 e7 02 and $0x2,%edi + 419748: 31 c0 xor %eax,%eax + 41974a: e8 71 7e ff ff callq 4115c0 <__libc_message> + 41974f: e9 6f f5 ff ff jmpq 418cc3 + 419754: 49 39 c6 cmp %rax,%r14 + 419757: 74 53 je 4197ac + 419759: 49 89 44 24 20 mov %rax,0x20(%r12) + 41975e: 49 8b 46 28 mov 0x28(%r14),%rax + 419762: 49 89 44 24 28 mov %rax,0x28(%r12) + 419767: 49 8b 46 20 mov 0x20(%r14),%rax + 41976b: 4c 89 60 28 mov %r12,0x28(%rax) + 41976f: 49 8b 46 28 mov 0x28(%r14),%rax + 419773: 4c 89 60 20 mov %r12,0x20(%rax) + 419777: e9 84 f5 ff ff jmpq 418d00 + 41977c: 8b 3d ee 0f 2b 00 mov 0x2b0fee(%rip),%edi # 6ca770 + 419782: b9 00 a8 6c 00 mov $0x6ca800,%ecx + 419787: 4c 89 f2 mov %r14,%rdx + 41978a: be f0 23 4a 00 mov $0x4a23f0,%esi + 41978f: e8 1c db ff ff callq 4172b0 + 419794: 49 8b 46 20 mov 0x20(%r14),%rax + 419798: e9 b6 fd ff ff jmpq 419553 + 41979d: 4d 89 64 24 28 mov %r12,0x28(%r12) + 4197a2: 4d 89 64 24 20 mov %r12,0x20(%r12) + 4197a7: e9 ec f4 ff ff jmpq 418c98 + 4197ac: 4d 89 64 24 28 mov %r12,0x28(%r12) + 4197b1: 4d 89 64 24 20 mov %r12,0x20(%r12) + 4197b6: e9 45 f5 ff ff jmpq 418d00 + 4197bb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + +00000000004197c0 <_int_free>: + 4197c0: 41 57 push %r15 + 4197c2: 41 56 push %r14 + 4197c4: 41 55 push %r13 + 4197c6: 41 54 push %r12 + 4197c8: 55 push %rbp + 4197c9: 53 push %rbx + 4197ca: 48 89 fd mov %rdi,%rbp + 4197cd: 48 89 f3 mov %rsi,%rbx + 4197d0: 48 83 ec 58 sub $0x58,%rsp + 4197d4: 48 8b 46 08 mov 0x8(%rsi),%rax + 4197d8: 89 54 24 04 mov %edx,0x4(%rsp) + 4197dc: 49 89 c4 mov %rax,%r12 + 4197df: 49 83 e4 f8 and $0xfffffffffffffff8,%r12 + 4197e3: 4c 89 e2 mov %r12,%rdx + 4197e6: 48 f7 da neg %rdx + 4197e9: 48 39 d6 cmp %rdx,%rsi + 4197ec: 0f 87 4e 05 00 00 ja 419d40 <_int_free+0x580> + 4197f2: 40 f6 c6 0f test $0xf,%sil + 4197f6: 0f 85 44 05 00 00 jne 419d40 <_int_free+0x580> + 4197fc: 49 83 fc 1f cmp $0x1f,%r12 + 419800: 0f 86 d2 05 00 00 jbe 419dd8 <_int_free+0x618> + 419806: a8 08 test $0x8,%al + 419808: 0f 85 ca 05 00 00 jne 419dd8 <_int_free+0x618> + 41980e: 4c 3b 25 23 2e 2b 00 cmp 0x2b2e23(%rip),%r12 # 6cc638 + 419815: 0f 87 05 01 00 00 ja 419920 <_int_free+0x160> + 41981b: 4a 8d 14 26 lea (%rsi,%r12,1),%rdx + 41981f: 48 8b 42 08 mov 0x8(%rdx),%rax + 419823: 48 83 f8 10 cmp $0x10,%rax + 419827: 0f 86 a3 07 00 00 jbe 419fd0 <_int_free+0x810> + 41982d: 48 83 e0 f8 and $0xfffffffffffffff8,%rax + 419831: 48 3b 87 80 08 00 00 cmp 0x880(%rdi),%rax + 419838: 0f 83 92 07 00 00 jae 419fd0 <_int_free+0x810> + 41983e: 8b 35 f0 2d 2b 00 mov 0x2b2df0(%rip),%esi # 6cc634 + 419844: 4c 8d 43 10 lea 0x10(%rbx),%r8 + 419848: 85 f6 test %esi,%esi + 41984a: 0f 85 50 0a 00 00 jne 41a2a0 <_int_free+0xae0> + 419850: 64 83 3c 25 18 00 00 cmpl $0x0,%fs:0x18 + 419857: 00 00 + 419859: 74 01 je 41985c <_int_free+0x9c> + 41985b: f0 83 65 04 fe lock andl $0xfffffffe,0x4(%rbp) + 419860: 41 c1 ec 04 shr $0x4,%r12d + 419864: 41 8d 44 24 fe lea -0x2(%r12),%eax + 419869: 48 8b 54 c5 08 mov 0x8(%rbp,%rax,8),%rdx + 41986e: 49 89 c4 mov %rax,%r12 + 419871: 48 8d 74 c5 08 lea 0x8(%rbp,%rax,8),%rsi + 419876: 48 39 d3 cmp %rdx,%rbx + 419879: 74 51 je 4198cc <_int_free+0x10c> + 41987b: 8b 7c 24 04 mov 0x4(%rsp),%edi + 41987f: 85 ff test %edi,%edi + 419881: bf ff ff ff ff mov $0xffffffff,%edi + 419886: 41 0f 95 c1 setne %r9b + 41988a: eb 07 jmp 419893 <_int_free+0xd3> + 41988c: 0f 1f 40 00 nopl 0x0(%rax) + 419890: 48 89 c2 mov %rax,%rdx + 419893: 48 85 d2 test %rdx,%rdx + 419896: 0f 95 c1 setne %cl + 419899: 44 20 c9 and %r9b,%cl + 41989c: 74 09 je 4198a7 <_int_free+0xe7> + 41989e: 8b 7a 08 mov 0x8(%rdx),%edi + 4198a1: c1 ef 04 shr $0x4,%edi + 4198a4: 83 ef 02 sub $0x2,%edi + 4198a7: 48 89 53 10 mov %rdx,0x10(%rbx) + 4198ab: 48 89 d0 mov %rdx,%rax + 4198ae: 64 83 3c 25 18 00 00 cmpl $0x0,%fs:0x18 + 4198b5: 00 00 + 4198b7: 74 01 je 4198ba <_int_free+0xfa> + 4198b9: f0 48 0f b1 1e lock cmpxchg %rbx,(%rsi) + 4198be: 48 39 d0 cmp %rdx,%rax + 4198c1: 0f 84 59 06 00 00 je 419f20 <_int_free+0x760> + 4198c7: 48 39 c3 cmp %rax,%rbx + 4198ca: 75 c4 jne 419890 <_int_free+0xd0> + 4198cc: 4c 89 c7 mov %r8,%rdi + 4198cf: 41 bd 70 24 4a 00 mov $0x4a2470,%r13d + 4198d5: 0f 1f 00 nopl (%rax) + 4198d8: 48 85 ed test %rbp,%rbp + 4198db: 44 8b 25 8e 0e 2b 00 mov 0x2b0e8e(%rip),%r12d # 6ca770 + 4198e2: 74 04 je 4198e8 <_int_free+0x128> + 4198e4: 83 4d 04 04 orl $0x4,0x4(%rbp) + 4198e8: 44 89 e0 mov %r12d,%eax + 4198eb: 83 e0 05 and $0x5,%eax + 4198ee: 83 f8 05 cmp $0x5,%eax + 4198f1: 0f 84 b9 06 00 00 je 419fb0 <_int_free+0x7f0> + 4198f7: 41 f6 c4 01 test $0x1,%r12b + 4198fb: 0f 85 4f 04 00 00 jne 419d50 <_int_free+0x590> + 419901: 41 83 e4 02 and $0x2,%r12d + 419905: 0f 85 99 08 00 00 jne 41a1a4 <_int_free+0x9e4> + 41990b: 48 83 c4 58 add $0x58,%rsp + 41990f: 5b pop %rbx + 419910: 5d pop %rbp + 419911: 41 5c pop %r12 + 419913: 41 5d pop %r13 + 419915: 41 5e pop %r14 + 419917: 41 5f pop %r15 + 419919: c3 retq + 41991a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 419920: a8 02 test $0x2,%al + 419922: 0f 85 e8 05 00 00 jne 419f10 <_int_free+0x750> + 419928: 8b 44 24 04 mov 0x4(%rsp),%eax + 41992c: 85 c0 test %eax,%eax + 41992e: 0f 84 ac 03 00 00 je 419ce0 <_int_free+0x520> + 419934: 48 8b 47 58 mov 0x58(%rdi),%rax + 419938: 4e 8d 2c 26 lea (%rsi,%r12,1),%r13 + 41993c: 48 39 c6 cmp %rax,%rsi + 41993f: 0f 84 b1 12 00 00 je 41abf6 <_int_free+0x1436> + 419945: 45 31 c9 xor %r9d,%r9d + 419948: c7 44 24 28 00 00 00 movl $0x0,0x28(%rsp) + 41994f: 00 + 419950: f6 45 04 02 testb $0x2,0x4(%rbp) + 419954: 0f 84 d6 09 00 00 je 41a330 <_int_free+0xb70> + 41995a: 49 8b 45 08 mov 0x8(%r13),%rax + 41995e: a8 01 test $0x1,%al + 419960: 0f 84 ea 09 00 00 je 41a350 <_int_free+0xb90> + 419966: 49 89 c7 mov %rax,%r15 + 419969: 49 83 e7 f8 and $0xfffffffffffffff8,%r15 + 41996d: 48 83 f8 10 cmp $0x10,%rax + 419971: 0f 86 39 08 00 00 jbe 41a1b0 <_int_free+0x9f0> + 419977: 4c 3b bd 80 08 00 00 cmp 0x880(%rbp),%r15 + 41997e: 0f 83 2c 08 00 00 jae 41a1b0 <_int_free+0x9f0> + 419984: 8b 35 aa 2c 2b 00 mov 0x2b2caa(%rip),%esi # 6cc634 + 41998a: 85 f6 test %esi,%esi + 41998c: 0f 85 c9 09 00 00 jne 41a35b <_int_free+0xb9b> + 419992: f6 43 08 01 testb $0x1,0x8(%rbx) + 419996: 0f 85 8c 00 00 00 jne 419a28 <_int_free+0x268> + 41999c: 48 8b 03 mov (%rbx),%rax + 41999f: 48 29 c3 sub %rax,%rbx + 4199a2: 49 01 c4 add %rax,%r12 + 4199a5: 48 8b 43 08 mov 0x8(%rbx),%rax + 4199a9: 48 83 e0 f8 and $0xfffffffffffffff8,%rax + 4199ad: 48 3b 04 03 cmp (%rbx,%rax,1),%rax + 4199b1: 0f 85 54 0a 00 00 jne 41a40b <_int_free+0xc4b> + 4199b7: 48 8b 43 10 mov 0x10(%rbx),%rax + 4199bb: 48 8b 53 18 mov 0x18(%rbx),%rdx + 4199bf: 48 3b 58 18 cmp 0x18(%rax),%rbx + 4199c3: 0f 85 b0 09 00 00 jne 41a379 <_int_free+0xbb9> + 4199c9: 48 3b 5a 10 cmp 0x10(%rdx),%rbx + 4199cd: 0f 85 a6 09 00 00 jne 41a379 <_int_free+0xbb9> + 4199d3: 48 81 7b 08 ff 03 00 cmpq $0x3ff,0x8(%rbx) + 4199da: 00 + 4199db: 48 89 50 18 mov %rdx,0x18(%rax) + 4199df: 48 89 42 10 mov %rax,0x10(%rdx) + 4199e3: 76 43 jbe 419a28 <_int_free+0x268> + 4199e5: 48 8b 53 20 mov 0x20(%rbx),%rdx + 4199e9: 48 85 d2 test %rdx,%rdx + 4199ec: 74 3a je 419a28 <_int_free+0x268> + 4199ee: 48 3b 5a 28 cmp 0x28(%rdx),%rbx + 4199f2: 0f 85 c3 10 00 00 jne 41aabb <_int_free+0x12fb> + 4199f8: 48 8b 4b 28 mov 0x28(%rbx),%rcx + 4199fc: 48 3b 59 20 cmp 0x20(%rcx),%rbx + 419a00: 0f 85 b5 10 00 00 jne 41aabb <_int_free+0x12fb> + 419a06: 48 83 78 20 00 cmpq $0x0,0x20(%rax) + 419a0b: 0f 84 ff 10 00 00 je 41ab10 <_int_free+0x1350> + 419a11: 48 8b 43 28 mov 0x28(%rbx),%rax + 419a15: 48 89 42 28 mov %rax,0x28(%rdx) + 419a19: 48 8b 43 28 mov 0x28(%rbx),%rax + 419a1d: 48 89 50 20 mov %rdx,0x20(%rax) + 419a21: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 419a28: 4c 39 6d 58 cmp %r13,0x58(%rbp) + 419a2c: 0f 84 e6 08 00 00 je 41a318 <_int_free+0xb58> + 419a32: 43 f6 44 3d 08 01 testb $0x1,0x8(%r13,%r15,1) + 419a38: 0f 85 62 05 00 00 jne 419fa0 <_int_free+0x7e0> + 419a3e: 49 8b 45 08 mov 0x8(%r13),%rax + 419a42: 48 83 e0 f8 and $0xfffffffffffffff8,%rax + 419a46: 49 3b 44 05 00 cmp 0x0(%r13,%rax,1),%rax + 419a4b: 0f 85 0f 0a 00 00 jne 41a460 <_int_free+0xca0> + 419a51: 49 8b 45 10 mov 0x10(%r13),%rax + 419a55: 49 8b 55 18 mov 0x18(%r13),%rdx + 419a59: 4c 39 68 18 cmp %r13,0x18(%rax) + 419a5d: 0f 85 13 07 00 00 jne 41a176 <_int_free+0x9b6> + 419a63: 4c 8b 42 10 mov 0x10(%rdx),%r8 + 419a67: 4d 39 e8 cmp %r13,%r8 + 419a6a: 0f 85 06 07 00 00 jne 41a176 <_int_free+0x9b6> + 419a70: 49 81 78 08 ff 03 00 cmpq $0x3ff,0x8(%r8) + 419a77: 00 + 419a78: 48 89 50 18 mov %rdx,0x18(%rax) + 419a7c: 48 89 42 10 mov %rax,0x10(%rdx) + 419a80: 0f 87 fa 05 00 00 ja 41a080 <_int_free+0x8c0> + 419a86: 4d 01 fc add %r15,%r12 + 419a89: 48 8b 45 68 mov 0x68(%rbp),%rax + 419a8d: 48 8d 55 58 lea 0x58(%rbp),%rdx + 419a91: 48 3b 50 18 cmp 0x18(%rax),%rdx + 419a95: 0f 85 15 09 00 00 jne 41a3b0 <_int_free+0xbf0> + 419a9b: 49 81 fc ff 03 00 00 cmp $0x3ff,%r12 + 419aa2: 48 89 43 10 mov %rax,0x10(%rbx) + 419aa6: 48 89 53 18 mov %rdx,0x18(%rbx) + 419aaa: 76 10 jbe 419abc <_int_free+0x2fc> + 419aac: 48 c7 43 20 00 00 00 movq $0x0,0x20(%rbx) + 419ab3: 00 + 419ab4: 48 c7 43 28 00 00 00 movq $0x0,0x28(%rbx) + 419abb: 00 + 419abc: 48 89 5d 68 mov %rbx,0x68(%rbp) + 419ac0: 48 89 58 18 mov %rbx,0x18(%rax) + 419ac4: 4c 89 e0 mov %r12,%rax + 419ac7: 48 83 c8 01 or $0x1,%rax + 419acb: 48 89 43 08 mov %rax,0x8(%rbx) + 419acf: 4e 89 24 23 mov %r12,(%rbx,%r12,1) + 419ad3: 49 81 fc ff ff 00 00 cmp $0xffff,%r12 + 419ada: 0f 86 a0 03 00 00 jbe 419e80 <_int_free+0x6c0> + 419ae0: f6 45 04 01 testb $0x1,0x4(%rbp) + 419ae4: 0f 84 de 05 00 00 je 41a0c8 <_int_free+0x908> + 419aea: 48 81 fd 00 a8 6c 00 cmp $0x6ca800,%rbp + 419af1: 0f 84 dd 08 00 00 je 41a3d4 <_int_free+0xc14> + 419af7: 4c 8b 65 58 mov 0x58(%rbp),%r12 + 419afb: 4c 89 e7 mov %r12,%rdi + 419afe: 48 81 e7 00 00 00 fc and $0xfffffffffc000000,%rdi + 419b05: 48 3b 2f cmp (%rdi),%rbp + 419b08: 0f 85 cf 10 00 00 jne 41abdd <_int_free+0x141d> + 419b0e: 48 8b 05 93 0c 2b 00 mov 0x2b0c93(%rip),%rax # 6ca7a8 + 419b15: 4c 8b 2d 64 16 2b 00 mov 0x2b1664(%rip),%r13 # 6cb180 <_dl_pagesize> + 419b1c: 48 89 44 24 08 mov %rax,0x8(%rsp) + 419b21: 48 8d 47 20 lea 0x20(%rdi),%rax + 419b25: 49 39 c4 cmp %rax,%r12 + 419b28: 0f 85 c2 02 00 00 jne 419df0 <_int_free+0x630> + 419b2e: 4c 8b 7f 08 mov 0x8(%rdi),%r15 + 419b32: 49 8b 4f 10 mov 0x10(%r15),%rcx + 419b36: 48 8d 51 f0 lea -0x10(%rcx),%rdx + 419b3a: 49 8d 04 17 lea (%r15,%rdx,1),%rax + 419b3e: 83 e0 0f and $0xf,%eax + 419b41: 48 29 c2 sub %rax,%rdx + 419b44: 4c 01 fa add %r15,%rdx + 419b47: 48 83 7a 08 01 cmpq $0x1,0x8(%rdx) + 419b4c: 0f 85 aa 0e 00 00 jne 41a9fc <_int_free+0x123c> + 419b52: 48 8d 5c 24 30 lea 0x30(%rsp),%rbx + 419b57: be 01 00 00 00 mov $0x1,%esi + 419b5c: 49 89 d6 mov %rdx,%r14 + 419b5f: 48 29 de sub %rbx,%rsi + 419b62: 48 89 74 24 10 mov %rsi,0x10(%rsp) + 419b67: e9 d9 00 00 00 jmpq 419c45 <_int_free+0x485> + 419b6c: 0f 1f 40 00 nopl 0x0(%rax) + 419b70: be 00 00 00 04 mov $0x4000000,%esi + 419b75: 4d 89 f4 mov %r14,%r12 + 419b78: e8 33 61 02 00 callq 43fcb0 <__munmap> + 419b7d: 41 f6 46 08 01 testb $0x1,0x8(%r14) + 419b82: 75 5c jne 419be0 <_int_free+0x420> + 419b84: 4d 2b 26 sub (%r14),%r12 + 419b87: 49 8b 44 24 08 mov 0x8(%r12),%rax + 419b8c: 48 83 e0 f8 and $0xfffffffffffffff8,%rax + 419b90: 49 3b 04 04 cmp (%r12,%rax,1),%rax + 419b94: 0f 85 a6 03 00 00 jne 419f40 <_int_free+0x780> + 419b9a: 4d 8b 74 24 10 mov 0x10(%r12),%r14 + 419b9f: 49 8b 44 24 18 mov 0x18(%r12),%rax + 419ba4: 4d 3b 66 18 cmp 0x18(%r14),%r12 + 419ba8: 0f 85 22 03 00 00 jne 419ed0 <_int_free+0x710> + 419bae: 4c 3b 60 10 cmp 0x10(%rax),%r12 + 419bb2: 0f 85 18 03 00 00 jne 419ed0 <_int_free+0x710> + 419bb8: 49 81 7c 24 08 ff 03 cmpq $0x3ff,0x8(%r12) + 419bbf: 00 00 + 419bc1: 49 89 46 18 mov %rax,0x18(%r14) + 419bc5: 4c 89 70 10 mov %r14,0x10(%rax) + 419bc9: 76 15 jbe 419be0 <_int_free+0x420> + 419bcb: 49 8b 44 24 20 mov 0x20(%r12),%rax + 419bd0: 48 85 c0 test %rax,%rax + 419bd3: 0f 85 df 06 00 00 jne 41a2b8 <_int_free+0xaf8> + 419bd9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 419be0: 49 8d 04 1c lea (%r12,%rbx,1),%rax + 419be4: 49 8d 55 ff lea -0x1(%r13),%rdx + 419be8: 48 85 d0 test %rdx,%rax + 419beb: 0f 85 a4 0e 00 00 jne 41aa95 <_int_free+0x12d5> + 419bf1: 4c 89 fa mov %r15,%rdx + 419bf4: 49 03 57 10 add 0x10(%r15),%rdx + 419bf8: 48 39 d0 cmp %rdx,%rax + 419bfb: 0f 85 7b 0e 00 00 jne 41aa7c <_int_free+0x12bc> + 419c01: 49 8d 47 20 lea 0x20(%r15),%rax + 419c05: 48 83 cb 01 or $0x1,%rbx + 419c09: 4c 89 65 58 mov %r12,0x58(%rbp) + 419c0d: 49 89 5c 24 08 mov %rbx,0x8(%r12) + 419c12: 49 39 c4 cmp %rax,%r12 + 419c15: 0f 85 dd 01 00 00 jne 419df8 <_int_free+0x638> + 419c1b: 49 8b 57 08 mov 0x8(%r15),%rdx + 419c1f: 4c 89 ff mov %r15,%rdi + 419c22: 48 8b 4a 10 mov 0x10(%rdx),%rcx + 419c26: 4c 8d 71 f0 lea -0x10(%rcx),%r14 + 419c2a: 4a 8d 04 32 lea (%rdx,%r14,1),%rax + 419c2e: 83 e0 0f and $0xf,%eax + 419c31: 49 29 c6 sub %rax,%r14 + 419c34: 49 01 d6 add %rdx,%r14 + 419c37: 49 83 7e 08 01 cmpq $0x1,0x8(%r14) + 419c3c: 0f 85 ba 0d 00 00 jne 41a9fc <_int_free+0x123c> + 419c42: 49 89 d7 mov %rdx,%r15 + 419c45: 4d 2b 36 sub (%r14),%r14 + 419c48: 49 8b 56 08 mov 0x8(%r14),%rdx + 419c4c: 48 89 d6 mov %rdx,%rsi + 419c4f: 48 83 e6 f8 and $0xfffffffffffffff8,%rsi + 419c53: 48 01 f0 add %rsi,%rax + 419c56: 4c 8d 48 10 lea 0x10(%rax),%r9 + 419c5a: 48 83 c0 0f add $0xf,%rax + 419c5e: 48 83 f8 3e cmp $0x3e,%rax + 419c62: 0f 87 7b 0d 00 00 ja 41a9e3 <_int_free+0x1223> + 419c68: 83 e2 01 and $0x1,%edx + 419c6b: 4c 89 cb mov %r9,%rbx + 419c6e: 75 03 jne 419c73 <_int_free+0x4b3> + 419c70: 49 03 1e add (%r14),%rbx + 419c73: 48 8d 43 ff lea -0x1(%rbx),%rax + 419c77: 48 3d fe ff ff 03 cmp $0x3fffffe,%rax + 419c7d: 0f 87 e0 0d 00 00 ja 41aa63 <_int_free+0x12a3> + 419c83: 48 89 d8 mov %rbx,%rax + 419c86: 48 29 c8 sub %rcx,%rax + 419c89: 48 8d 90 00 00 00 04 lea 0x4000000(%rax),%rdx + 419c90: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 419c95: 4a 8d 44 28 20 lea 0x20(%rax,%r13,1),%rax + 419c9a: 48 39 c2 cmp %rax,%rdx + 419c9d: 0f 82 4d 01 00 00 jb 419df0 <_int_free+0x630> + 419ca3: 48 8b 47 10 mov 0x10(%rdi),%rax + 419ca7: 48 29 85 80 08 00 00 sub %rax,0x880(%rbp) + 419cae: 48 29 05 63 29 2b 00 sub %rax,0x2b2963(%rip) # 6cc618 + 419cb5: 90 nop + 419cb6: 48 8d 87 00 00 00 04 lea 0x4000000(%rdi),%rax + 419cbd: 48 39 05 4c 29 2b 00 cmp %rax,0x2b294c(%rip) # 6cc610 + 419cc4: 0f 85 a6 fe ff ff jne 419b70 <_int_free+0x3b0> + 419cca: 48 c7 05 3b 29 2b 00 movq $0x0,0x2b293b(%rip) # 6cc610 + 419cd1: 00 00 00 00 + 419cd5: e9 96 fe ff ff jmpq 419b70 <_int_free+0x3b0> + 419cda: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 419ce0: be 01 00 00 00 mov $0x1,%esi + 419ce5: 83 3d d0 34 2b 00 00 cmpl $0x0,0x2b34d0(%rip) # 6cd1bc <__libc_multiple_threads> + 419cec: 74 09 je 419cf7 <_int_free+0x537> + 419cee: f0 0f b1 75 00 lock cmpxchg %esi,0x0(%rbp) + 419cf3: 75 08 jne 419cfd <_int_free+0x53d> + 419cf5: eb 1d jmp 419d14 <_int_free+0x554> + 419cf7: 0f b1 75 00 cmpxchg %esi,0x0(%rbp) + 419cfb: 74 17 je 419d14 <_int_free+0x554> + 419cfd: 48 8d 7d 00 lea 0x0(%rbp),%rdi + 419d01: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 419d08: e8 c3 88 02 00 callq 4425d0 <__lll_lock_wait_private> + 419d0d: 48 81 c4 80 00 00 00 add $0x80,%rsp + 419d14: 48 8b 45 58 mov 0x58(%rbp),%rax + 419d18: 4e 8d 2c 23 lea (%rbx,%r12,1),%r13 + 419d1c: 48 39 c3 cmp %rax,%rbx + 419d1f: 0f 84 e3 05 00 00 je 41a308 <_int_free+0xb48> + 419d25: 41 b9 01 00 00 00 mov $0x1,%r9d + 419d2b: c7 44 24 28 01 00 00 movl $0x1,0x28(%rsp) + 419d32: 00 + 419d33: e9 18 fc ff ff jmpq 419950 <_int_free+0x190> + 419d38: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 419d3f: 00 + 419d40: 48 8d 7b 10 lea 0x10(%rbx),%rdi + 419d44: 41 bd b2 20 4a 00 mov $0x4a20b2,%r13d + 419d4a: e9 89 fb ff ff jmpq 4198d8 <_int_free+0x118> + 419d4f: 90 nop + 419d50: 48 8d 6c 24 30 lea 0x30(%rsp),%rbp + 419d55: 48 8d 74 24 40 lea 0x40(%rsp),%rsi + 419d5a: 31 c9 xor %ecx,%ecx + 419d5c: ba 10 00 00 00 mov $0x10,%edx + 419d61: c6 44 24 40 00 movb $0x0,0x40(%rsp) + 419d66: e8 45 81 03 00 callq 451eb0 <_itoa_word> + 419d6b: 48 39 e8 cmp %rbp,%rax + 419d6e: 48 89 c3 mov %rax,%rbx + 419d71: 76 25 jbe 419d98 <_int_free+0x5d8> + 419d73: 48 89 c2 mov %rax,%rdx + 419d76: 48 89 c7 mov %rax,%rdi + 419d79: be 30 00 00 00 mov $0x30,%esi + 419d7e: 48 29 ea sub %rbp,%rdx + 419d81: 4c 8d 70 ff lea -0x1(%rax),%r14 + 419d85: 48 29 d7 sub %rdx,%rdi + 419d88: e8 c3 65 fe ff callq 400350 <__rela_iplt_end+0x88> + 419d8d: 48 8d 44 24 2f lea 0x2f(%rsp),%rax + 419d92: 4c 29 f0 sub %r14,%rax + 419d95: 48 01 c3 add %rax,%rbx + 419d98: 48 8b 05 21 35 2b 00 mov 0x2b3521(%rip),%rax # 6cd2c0 <__libc_argv> + 419d9f: 44 89 e7 mov %r12d,%edi + 419da2: ba 38 20 4a 00 mov $0x4a2038,%edx + 419da7: 49 89 d8 mov %rbx,%r8 + 419daa: 4c 89 e9 mov %r13,%rcx + 419dad: be a8 23 4a 00 mov $0x4a23a8,%esi + 419db2: 48 8b 00 mov (%rax),%rax + 419db5: 48 85 c0 test %rax,%rax + 419db8: 48 0f 45 d0 cmovne %rax,%rdx + 419dbc: 83 e7 02 and $0x2,%edi + 419dbf: 31 c0 xor %eax,%eax + 419dc1: e8 fa 77 ff ff callq 4115c0 <__libc_message> + 419dc6: 48 83 c4 58 add $0x58,%rsp + 419dca: 5b pop %rbx + 419dcb: 5d pop %rbp + 419dcc: 41 5c pop %r12 + 419dce: 41 5d pop %r13 + 419dd0: 41 5e pop %r14 + 419dd2: 41 5f pop %r15 + 419dd4: c3 retq + 419dd5: 0f 1f 00 nopl (%rax) + 419dd8: 48 8d 7b 10 lea 0x10(%rbx),%rdi + 419ddc: 41 bd ca 20 4a 00 mov $0x4a20ca,%r13d + 419de2: e9 f1 fa ff ff jmpq 4198d8 <_int_free+0x118> + 419de7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 419dee: 00 00 + 419df0: 49 8b 5c 24 08 mov 0x8(%r12),%rbx + 419df5: 49 89 ff mov %rdi,%r15 + 419df8: 48 83 e3 f8 and $0xfffffffffffffff8,%rbx + 419dfc: 48 39 1d 9d 09 2b 00 cmp %rbx,0x2b099d(%rip) # 6ca7a0 + 419e03: 77 7b ja 419e80 <_int_free+0x6c0> + 419e05: 48 89 d8 mov %rbx,%rax + 419e08: 48 83 e8 21 sub $0x21,%rax + 419e0c: 78 72 js 419e80 <_int_free+0x6c0> + 419e0e: 48 8b 4c 24 08 mov 0x8(%rsp),%rcx + 419e13: 48 39 c1 cmp %rax,%rcx + 419e16: 73 68 jae 419e80 <_int_free+0x6c0> + 419e18: 48 29 c8 sub %rcx,%rax + 419e1b: 49 f7 dd neg %r13 + 419e1e: 49 21 c5 and %rax,%r13 + 419e21: 74 5d je 419e80 <_int_free+0x6c0> + 419e23: 4d 8b 77 10 mov 0x10(%r15),%r14 + 419e27: 4d 29 ee sub %r13,%r14 + 419e2a: 49 83 fe 1f cmp $0x1f,%r14 + 419e2e: 7e 50 jle 419e80 <_int_free+0x6c0> + 419e30: 8b 35 2a 09 2b 00 mov 0x2b092a(%rip),%esi # 6ca760 + 419e36: 85 f6 test %esi,%esi + 419e38: 0f 88 1e 0b 00 00 js 41a95c <_int_free+0x119c> + 419e3e: 0f 95 c0 setne %al + 419e41: 84 c0 test %al,%al + 419e43: 4b 8d 3c 37 lea (%r15,%r14,1),%rdi + 419e47: 0f 85 e4 0a 00 00 jne 41a931 <_int_free+0x1171> + 419e4d: ba 04 00 00 00 mov $0x4,%edx + 419e52: 4c 89 ee mov %r13,%rsi + 419e55: e8 96 5e 02 00 callq 43fcf0 <__madvise> + 419e5a: 4d 89 77 10 mov %r14,0x10(%r15) + 419e5e: 90 nop + 419e5f: 4c 29 2d b2 27 2b 00 sub %r13,0x2b27b2(%rip) # 6cc618 + 419e66: 4c 29 eb sub %r13,%rbx + 419e69: 4c 29 ad 80 08 00 00 sub %r13,0x880(%rbp) + 419e70: 48 83 cb 01 or $0x1,%rbx + 419e74: 49 89 5c 24 08 mov %rbx,0x8(%r12) + 419e79: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 419e80: 8b 54 24 04 mov 0x4(%rsp),%edx + 419e84: 85 d2 test %edx,%edx + 419e86: 0f 85 7f fa ff ff jne 41990b <_int_free+0x14b> + 419e8c: 8b 44 24 28 mov 0x28(%rsp),%eax + 419e90: 85 c0 test %eax,%eax + 419e92: 0f 84 2c 0d 00 00 je 41abc4 <_int_free+0x1404> + 419e98: 83 3d 1d 33 2b 00 00 cmpl $0x0,0x2b331d(%rip) # 6cd1bc <__libc_multiple_threads> + 419e9f: 74 08 je 419ea9 <_int_free+0x6e9> + 419ea1: f0 ff 4d 00 lock decl 0x0(%rbp) + 419ea5: 75 07 jne 419eae <_int_free+0x6ee> + 419ea7: eb 1c jmp 419ec5 <_int_free+0x705> + 419ea9: ff 4d 00 decl 0x0(%rbp) + 419eac: 74 17 je 419ec5 <_int_free+0x705> + 419eae: 48 8d 7d 00 lea 0x0(%rbp),%rdi + 419eb2: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 419eb9: e8 42 87 02 00 callq 442600 <__lll_unlock_wake_private> + 419ebe: 48 81 c4 80 00 00 00 add $0x80,%rsp + 419ec5: e9 41 fa ff ff jmpq 41990b <_int_free+0x14b> + 419eca: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 419ed0: 8b 3d 9a 08 2b 00 mov 0x2b089a(%rip),%edi # 6ca770 + 419ed6: 83 4d 04 04 orl $0x4,0x4(%rbp) + 419eda: 89 f8 mov %edi,%eax + 419edc: 83 e0 05 and $0x5,%eax + 419edf: 83 f8 05 cmp $0x5,%eax + 419ee2: 0f 84 d3 04 00 00 je 41a3bb <_int_free+0xbfb> + 419ee8: 41 89 fe mov %edi,%r14d + 419eeb: 41 83 e6 02 and $0x2,%r14d + 419eef: 83 e7 01 and $0x1,%edi + 419ef2: 0f 85 10 03 00 00 jne 41a208 <_int_free+0xa48> + 419ef8: 45 85 f6 test %r14d,%r14d + 419efb: 0f 84 df fc ff ff je 419be0 <_int_free+0x420> + 419f01: e9 9e 02 00 00 jmpq 41a1a4 <_int_free+0x9e4> + 419f06: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 419f0d: 00 00 00 + 419f10: 48 89 f7 mov %rsi,%rdi + 419f13: e8 d8 dd ff ff callq 417cf0 + 419f18: e9 ee f9 ff ff jmpq 41990b <_int_free+0x14b> + 419f1d: 0f 1f 00 nopl (%rax) + 419f20: 44 39 e7 cmp %r12d,%edi + 419f23: 0f 84 e2 f9 ff ff je 41990b <_int_free+0x14b> + 419f29: 84 c9 test %cl,%cl + 419f2b: 0f 84 da f9 ff ff je 41990b <_int_free+0x14b> + 419f31: 4c 89 c7 mov %r8,%rdi + 419f34: 41 bd df 20 4a 00 mov $0x4a20df,%r13d + 419f3a: e9 99 f9 ff ff jmpq 4198d8 <_int_free+0x118> + 419f3f: 90 nop + 419f40: 44 8b 15 29 08 2b 00 mov 0x2b0829(%rip),%r10d # 6ca770 + 419f47: 83 4d 04 04 orl $0x4,0x4(%rbp) + 419f4b: 44 89 d0 mov %r10d,%eax + 419f4e: 83 e0 05 and $0x5,%eax + 419f51: 83 f8 05 cmp $0x5,%eax + 419f54: 0f 84 66 05 00 00 je 41a4c0 <_int_free+0xd00> + 419f5a: 41 f6 c2 01 test $0x1,%r10b + 419f5e: 0f 85 71 01 00 00 jne 41a0d5 <_int_free+0x915> + 419f64: 41 f6 c2 02 test $0x2,%r10b + 419f68: 0f 85 36 02 00 00 jne 41a1a4 <_int_free+0x9e4> + 419f6e: 4d 8b 74 24 10 mov 0x10(%r12),%r14 + 419f73: 49 8b 44 24 18 mov 0x18(%r12),%rax + 419f78: 4d 3b 66 18 cmp 0x18(%r14),%r12 + 419f7c: 0f 85 5e fc ff ff jne 419be0 <_int_free+0x420> + 419f82: 4c 3b 60 10 cmp 0x10(%rax),%r12 + 419f86: 0f 84 2c fc ff ff je 419bb8 <_int_free+0x3f8> + 419f8c: 44 89 d7 mov %r10d,%edi + 419f8f: 83 4d 04 04 orl $0x4,0x4(%rbp) + 419f93: e9 50 ff ff ff jmpq 419ee8 <_int_free+0x728> + 419f98: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 419f9f: 00 + 419fa0: 49 83 65 08 fe andq $0xfffffffffffffffe,0x8(%r13) + 419fa5: e9 df fa ff ff jmpq 419a89 <_int_free+0x2c9> + 419faa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 419fb0: 44 89 e7 mov %r12d,%edi + 419fb3: 4c 89 ea mov %r13,%rdx + 419fb6: be 3c ca 4b 00 mov $0x4bca3c,%esi + 419fbb: 83 e7 02 and $0x2,%edi + 419fbe: 31 c0 xor %eax,%eax + 419fc0: e8 fb 75 ff ff callq 4115c0 <__libc_message> + 419fc5: e9 41 f9 ff ff jmpq 41990b <_int_free+0x14b> + 419fca: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 419fd0: 44 8b 44 24 04 mov 0x4(%rsp),%r8d + 419fd5: 45 85 c0 test %r8d,%r8d + 419fd8: 0f 85 92 00 00 00 jne 41a070 <_int_free+0x8b0> + 419fde: be 01 00 00 00 mov $0x1,%esi + 419fe3: 8b 44 24 04 mov 0x4(%rsp),%eax + 419fe7: 83 3d ce 31 2b 00 00 cmpl $0x0,0x2b31ce(%rip) # 6cd1bc <__libc_multiple_threads> + 419fee: 74 09 je 419ff9 <_int_free+0x839> + 419ff0: f0 0f b1 75 00 lock cmpxchg %esi,0x0(%rbp) + 419ff5: 75 08 jne 419fff <_int_free+0x83f> + 419ff7: eb 1d jmp 41a016 <_int_free+0x856> + 419ff9: 0f b1 75 00 cmpxchg %esi,0x0(%rbp) + 419ffd: 74 17 je 41a016 <_int_free+0x856> + 419fff: 48 8d 7d 00 lea 0x0(%rbp),%rdi + 41a003: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41a00a: e8 c1 85 02 00 callq 4425d0 <__lll_lock_wait_private> + 41a00f: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41a016: 48 8b 42 08 mov 0x8(%rdx),%rax + 41a01a: 48 83 f8 10 cmp $0x10,%rax + 41a01e: 0f 86 d4 02 00 00 jbe 41a2f8 <_int_free+0xb38> + 41a024: 48 83 e0 f8 and $0xfffffffffffffff8,%rax + 41a028: 48 3b 85 80 08 00 00 cmp 0x880(%rbp),%rax + 41a02f: 0f 83 c3 02 00 00 jae 41a2f8 <_int_free+0xb38> + 41a035: 83 3d 80 31 2b 00 00 cmpl $0x0,0x2b3180(%rip) # 6cd1bc <__libc_multiple_threads> + 41a03c: 74 08 je 41a046 <_int_free+0x886> + 41a03e: f0 ff 4d 00 lock decl 0x0(%rbp) + 41a042: 75 07 jne 41a04b <_int_free+0x88b> + 41a044: eb 1c jmp 41a062 <_int_free+0x8a2> + 41a046: ff 4d 00 decl 0x0(%rbp) + 41a049: 74 17 je 41a062 <_int_free+0x8a2> + 41a04b: 48 8d 7d 00 lea 0x0(%rbp),%rdi + 41a04f: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41a056: e8 a5 85 02 00 callq 442600 <__lll_unlock_wake_private> + 41a05b: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41a062: e9 d7 f7 ff ff jmpq 41983e <_int_free+0x7e> + 41a067: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 41a06e: 00 00 + 41a070: 48 8d 7b 10 lea 0x10(%rbx),%rdi + 41a074: 41 bd 20 24 4a 00 mov $0x4a2420,%r13d + 41a07a: e9 59 f8 ff ff jmpq 4198d8 <_int_free+0x118> + 41a07f: 90 nop + 41a080: 49 8b 50 20 mov 0x20(%r8),%rdx + 41a084: 48 85 d2 test %rdx,%rdx + 41a087: 0f 84 f9 f9 ff ff je 419a86 <_int_free+0x2c6> + 41a08d: 4c 39 42 28 cmp %r8,0x28(%rdx) + 41a091: 0f 85 cd 0a 00 00 jne 41ab64 <_int_free+0x13a4> + 41a097: 49 8b 48 28 mov 0x28(%r8),%rcx + 41a09b: 4c 39 41 20 cmp %r8,0x20(%rcx) + 41a09f: 0f 85 bf 0a 00 00 jne 41ab64 <_int_free+0x13a4> + 41a0a5: 48 83 78 20 00 cmpq $0x0,0x20(%rax) + 41a0aa: 0f 84 8a 0a 00 00 je 41ab3a <_int_free+0x137a> + 41a0b0: 49 8b 40 28 mov 0x28(%r8),%rax + 41a0b4: 48 89 42 28 mov %rax,0x28(%rdx) + 41a0b8: 49 8b 40 28 mov 0x28(%r8),%rax + 41a0bc: 48 89 50 20 mov %rdx,0x20(%rax) + 41a0c0: e9 c1 f9 ff ff jmpq 419a86 <_int_free+0x2c6> + 41a0c5: 0f 1f 00 nopl (%rax) + 41a0c8: 48 89 ef mov %rbp,%rdi + 41a0cb: e8 60 dd ff ff callq 417e30 + 41a0d0: e9 15 fa ff ff jmpq 419aea <_int_free+0x32a> + 41a0d5: 48 8d 74 24 40 lea 0x40(%rsp),%rsi + 41a0da: 31 c9 xor %ecx,%ecx + 41a0dc: ba 10 00 00 00 mov $0x10,%edx + 41a0e1: 4c 89 e7 mov %r12,%rdi + 41a0e4: 44 89 54 24 18 mov %r10d,0x18(%rsp) + 41a0e9: c6 44 24 40 00 movb $0x0,0x40(%rsp) + 41a0ee: e8 bd 7d 03 00 callq 451eb0 <_itoa_word> + 41a0f3: 49 89 c6 mov %rax,%r14 + 41a0f6: 48 8d 44 24 30 lea 0x30(%rsp),%rax + 41a0fb: 44 8b 54 24 18 mov 0x18(%rsp),%r10d + 41a100: 49 39 c6 cmp %rax,%r14 + 41a103: 76 3c jbe 41a141 <_int_free+0x981> + 41a105: 48 8b 44 24 10 mov 0x10(%rsp),%rax + 41a10a: 49 8d 4e ff lea -0x1(%r14),%rcx + 41a10e: 4c 89 f7 mov %r14,%rdi + 41a111: be 30 00 00 00 mov $0x30,%esi + 41a116: 44 89 54 24 20 mov %r10d,0x20(%rsp) + 41a11b: 48 89 4c 24 18 mov %rcx,0x18(%rsp) + 41a120: 48 8d 14 08 lea (%rax,%rcx,1),%rdx + 41a124: 48 29 d7 sub %rdx,%rdi + 41a127: e8 24 62 fe ff callq 400350 <__rela_iplt_end+0x88> + 41a12c: 48 8b 4c 24 18 mov 0x18(%rsp),%rcx + 41a131: 48 8d 44 24 2f lea 0x2f(%rsp),%rax + 41a136: 44 8b 54 24 20 mov 0x20(%rsp),%r10d + 41a13b: 48 29 c8 sub %rcx,%rax + 41a13e: 49 01 c6 add %rax,%r14 + 41a141: 48 8b 05 78 31 2b 00 mov 0x2b3178(%rip),%rax # 6cd2c0 <__libc_argv> + 41a148: 44 89 d7 mov %r10d,%edi + 41a14b: ba 38 20 4a 00 mov $0x4a2038,%edx + 41a150: 4d 89 f0 mov %r14,%r8 + 41a153: b9 78 20 4a 00 mov $0x4a2078,%ecx + 41a158: be a8 23 4a 00 mov $0x4a23a8,%esi + 41a15d: 48 8b 00 mov (%rax),%rax + 41a160: 48 85 c0 test %rax,%rax + 41a163: 48 0f 45 d0 cmovne %rax,%rdx + 41a167: 83 e7 02 and $0x2,%edi + 41a16a: 31 c0 xor %eax,%eax + 41a16c: e8 4f 74 ff ff callq 4115c0 <__libc_message> + 41a171: e9 24 fa ff ff jmpq 419b9a <_int_free+0x3da> + 41a176: 44 8b 15 f3 05 2b 00 mov 0x2b05f3(%rip),%r10d # 6ca770 + 41a17d: 83 4d 04 04 orl $0x4,0x4(%rbp) + 41a181: 44 89 d0 mov %r10d,%eax + 41a184: 83 e0 05 and $0x5,%eax + 41a187: 83 f8 05 cmp $0x5,%eax + 41a18a: 0f 84 7a 07 00 00 je 41a90a <_int_free+0x114a> + 41a190: 41 f6 c2 01 test $0x1,%r10b + 41a194: 0f 85 62 04 00 00 jne 41a5fc <_int_free+0xe3c> + 41a19a: 41 83 e2 02 and $0x2,%r10d + 41a19e: 0f 84 e2 f8 ff ff je 419a86 <_int_free+0x2c6> + 41a1a4: e8 57 3a ff ff callq 40dc00 + 41a1a9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 41a1b0: 41 bd 00 25 4a 00 mov $0x4a2500,%r13d + 41a1b6: 44 8b 54 24 04 mov 0x4(%rsp),%r10d + 41a1bb: 45 85 d2 test %r10d,%r10d + 41a1be: 0f 85 48 0a 00 00 jne 41ac0c <_int_free+0x144c> + 41a1c4: 45 84 c9 test %r9b,%r9b + 41a1c7: 0f 84 3f 0a 00 00 je 41ac0c <_int_free+0x144c> + 41a1cd: 83 3d e8 2f 2b 00 00 cmpl $0x0,0x2b2fe8(%rip) # 6cd1bc <__libc_multiple_threads> + 41a1d4: 74 08 je 41a1de <_int_free+0xa1e> + 41a1d6: f0 ff 4d 00 lock decl 0x0(%rbp) + 41a1da: 75 07 jne 41a1e3 <_int_free+0xa23> + 41a1dc: eb 1c jmp 41a1fa <_int_free+0xa3a> + 41a1de: ff 4d 00 decl 0x0(%rbp) + 41a1e1: 74 17 je 41a1fa <_int_free+0xa3a> + 41a1e3: 48 8d 7d 00 lea 0x0(%rbp),%rdi + 41a1e7: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41a1ee: e8 0d 84 02 00 callq 442600 <__lll_unlock_wake_private> + 41a1f3: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41a1fa: 48 8d 7b 10 lea 0x10(%rbx),%rdi + 41a1fe: e9 d5 f6 ff ff jmpq 4198d8 <_int_free+0x118> + 41a203: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41a208: 48 8d 74 24 40 lea 0x40(%rsp),%rsi + 41a20d: 31 c9 xor %ecx,%ecx + 41a20f: ba 10 00 00 00 mov $0x10,%edx + 41a214: 4c 89 e7 mov %r12,%rdi + 41a217: c6 44 24 40 00 movb $0x0,0x40(%rsp) + 41a21c: e8 8f 7c 03 00 callq 451eb0 <_itoa_word> + 41a221: 49 89 c0 mov %rax,%r8 + 41a224: 48 8d 44 24 30 lea 0x30(%rsp),%rax + 41a229: 49 39 c0 cmp %rax,%r8 + 41a22c: 76 3c jbe 41a26a <_int_free+0xaaa> + 41a22e: 48 8b 44 24 10 mov 0x10(%rsp),%rax + 41a233: 49 8d 48 ff lea -0x1(%r8),%rcx + 41a237: 4c 89 c7 mov %r8,%rdi + 41a23a: be 30 00 00 00 mov $0x30,%esi + 41a23f: 4c 89 44 24 18 mov %r8,0x18(%rsp) + 41a244: 48 89 4c 24 20 mov %rcx,0x20(%rsp) + 41a249: 48 8d 14 08 lea (%rax,%rcx,1),%rdx + 41a24d: 48 29 d7 sub %rdx,%rdi + 41a250: e8 fb 60 fe ff callq 400350 <__rela_iplt_end+0x88> + 41a255: 48 8b 4c 24 20 mov 0x20(%rsp),%rcx + 41a25a: 48 8d 44 24 2f lea 0x2f(%rsp),%rax + 41a25f: 4c 8b 44 24 18 mov 0x18(%rsp),%r8 + 41a264: 48 29 c8 sub %rcx,%rax + 41a267: 49 01 c0 add %rax,%r8 + 41a26a: 48 8b 05 4f 30 2b 00 mov 0x2b304f(%rip),%rax # 6cd2c0 <__libc_argv> + 41a271: ba 38 20 4a 00 mov $0x4a2038,%edx + 41a276: b9 95 20 4a 00 mov $0x4a2095,%ecx + 41a27b: be a8 23 4a 00 mov $0x4a23a8,%esi + 41a280: 44 89 f7 mov %r14d,%edi + 41a283: 48 8b 00 mov (%rax),%rax + 41a286: 48 85 c0 test %rax,%rax + 41a289: 48 0f 45 d0 cmovne %rax,%rdx + 41a28d: 31 c0 xor %eax,%eax + 41a28f: e8 2c 73 ff ff callq 4115c0 <__libc_message> + 41a294: e9 47 f9 ff ff jmpq 419be0 <_int_free+0x420> + 41a299: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 41a2a0: 49 8d 54 24 f0 lea -0x10(%r12),%rdx + 41a2a5: 4c 89 c7 mov %r8,%rdi + 41a2a8: e8 a3 60 fe ff callq 400350 <__rela_iplt_end+0x88> + 41a2ad: 49 89 c0 mov %rax,%r8 + 41a2b0: e9 9b f5 ff ff jmpq 419850 <_int_free+0x90> + 41a2b5: 0f 1f 00 nopl (%rax) + 41a2b8: 4c 3b 60 28 cmp 0x28(%rax),%r12 + 41a2bc: 0f 85 1a 02 00 00 jne 41a4dc <_int_free+0xd1c> + 41a2c2: 49 8b 54 24 28 mov 0x28(%r12),%rdx + 41a2c7: 4c 3b 62 20 cmp 0x20(%rdx),%r12 + 41a2cb: 0f 85 0b 02 00 00 jne 41a4dc <_int_free+0xd1c> + 41a2d1: 49 83 7e 20 00 cmpq $0x0,0x20(%r14) + 41a2d6: 0f 84 34 02 00 00 je 41a510 <_int_free+0xd50> + 41a2dc: 49 8b 54 24 28 mov 0x28(%r12),%rdx + 41a2e1: 48 89 50 28 mov %rdx,0x28(%rax) + 41a2e5: 49 8b 54 24 28 mov 0x28(%r12),%rdx + 41a2ea: 48 89 42 20 mov %rax,0x20(%rdx) + 41a2ee: e9 ed f8 ff ff jmpq 419be0 <_int_free+0x420> + 41a2f3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41a2f8: 41 bd 20 24 4a 00 mov $0x4a2420,%r13d + 41a2fe: e9 ca fe ff ff jmpq 41a1cd <_int_free+0xa0d> + 41a303: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41a308: 41 bd 98 24 4a 00 mov $0x4a2498,%r13d + 41a30e: e9 ba fe ff ff jmpq 41a1cd <_int_free+0xa0d> + 41a313: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41a318: 4d 01 fc add %r15,%r12 + 41a31b: 4c 89 e0 mov %r12,%rax + 41a31e: 48 83 c8 01 or $0x1,%rax + 41a322: 48 89 43 08 mov %rax,0x8(%rbx) + 41a326: 48 89 5d 58 mov %rbx,0x58(%rbp) + 41a32a: e9 a4 f7 ff ff jmpq 419ad3 <_int_free+0x313> + 41a32f: 90 nop + 41a330: 48 8b 50 08 mov 0x8(%rax),%rdx + 41a334: 48 83 e2 f8 and $0xfffffffffffffff8,%rdx + 41a338: 48 01 d0 add %rdx,%rax + 41a33b: 49 39 c5 cmp %rax,%r13 + 41a33e: 0f 82 16 f6 ff ff jb 41995a <_int_free+0x19a> + 41a344: 41 bd b8 24 4a 00 mov $0x4a24b8,%r13d + 41a34a: e9 67 fe ff ff jmpq 41a1b6 <_int_free+0x9f6> + 41a34f: 90 nop + 41a350: 41 bd d8 24 4a 00 mov $0x4a24d8,%r13d + 41a356: e9 5b fe ff ff jmpq 41a1b6 <_int_free+0x9f6> + 41a35b: 49 8d 54 24 f0 lea -0x10(%r12),%rdx + 41a360: 48 8d 7b 10 lea 0x10(%rbx),%rdi + 41a364: 44 88 4c 24 08 mov %r9b,0x8(%rsp) + 41a369: e8 e2 5f fe ff callq 400350 <__rela_iplt_end+0x88> + 41a36e: 44 0f b6 4c 24 08 movzbl 0x8(%rsp),%r9d + 41a374: e9 19 f6 ff ff jmpq 419992 <_int_free+0x1d2> + 41a379: 44 8b 15 f0 03 2b 00 mov 0x2b03f0(%rip),%r10d # 6ca770 + 41a380: 83 4d 04 04 orl $0x4,0x4(%rbp) + 41a384: 44 89 d0 mov %r10d,%eax + 41a387: 83 e0 05 and $0x5,%eax + 41a38a: 83 f8 05 cmp $0x5,%eax + 41a38d: 0f 84 50 05 00 00 je 41a8e3 <_int_free+0x1123> + 41a393: 41 f6 c2 01 test $0x1,%r10b + 41a397: 0f 85 a0 01 00 00 jne 41a53d <_int_free+0xd7d> + 41a39d: 41 83 e2 02 and $0x2,%r10d + 41a3a1: 0f 84 81 f6 ff ff je 419a28 <_int_free+0x268> + 41a3a7: e9 f8 fd ff ff jmpq 41a1a4 <_int_free+0x9e4> + 41a3ac: 0f 1f 40 00 nopl 0x0(%rax) + 41a3b0: 41 bd 48 24 4a 00 mov $0x4a2448,%r13d + 41a3b6: e9 fb fd ff ff jmpq 41a1b6 <_int_free+0x9f6> + 41a3bb: 83 e7 02 and $0x2,%edi + 41a3be: ba 95 20 4a 00 mov $0x4a2095,%edx + 41a3c3: be 3c ca 4b 00 mov $0x4bca3c,%esi + 41a3c8: 31 c0 xor %eax,%eax + 41a3ca: e8 f1 71 ff ff callq 4115c0 <__libc_message> + 41a3cf: e9 0c f8 ff ff jmpq 419be0 <_int_free+0x420> + 41a3d4: 48 8b 05 7d 04 2b 00 mov 0x2b047d(%rip),%rax # 6ca858 + 41a3db: 48 8b 40 08 mov 0x8(%rax),%rax + 41a3df: 48 83 e0 f8 and $0xfffffffffffffff8,%rax + 41a3e3: 48 3b 05 b6 03 2b 00 cmp 0x2b03b6(%rip),%rax # 6ca7a0 + 41a3ea: 0f 82 90 fa ff ff jb 419e80 <_int_free+0x6c0> + 41a3f0: 48 8b 3d b1 03 2b 00 mov 0x2b03b1(%rip),%rdi # 6ca7a8 + 41a3f7: ba 80 b0 6c 00 mov $0x6cb080,%edx + 41a3fc: be 58 a8 6c 00 mov $0x6ca858,%esi + 41a401: e8 9a cf ff ff callq 4173a0 + 41a406: e9 75 fa ff ff jmpq 419e80 <_int_free+0x6c0> + 41a40b: 44 8b 15 5e 03 2b 00 mov 0x2b035e(%rip),%r10d # 6ca770 + 41a412: 83 4d 04 04 orl $0x4,0x4(%rbp) + 41a416: 44 89 d0 mov %r10d,%eax + 41a419: 83 e0 05 and $0x5,%eax + 41a41c: 83 f8 05 cmp $0x5,%eax + 41a41f: 0f 84 f0 05 00 00 je 41aa15 <_int_free+0x1255> + 41a425: 41 f6 c2 01 test $0x1,%r10b + 41a429: 0f 85 89 02 00 00 jne 41a6b8 <_int_free+0xef8> + 41a42f: 41 f6 c2 02 test $0x2,%r10b + 41a433: 0f 85 6b fd ff ff jne 41a1a4 <_int_free+0x9e4> + 41a439: 48 8b 43 10 mov 0x10(%rbx),%rax + 41a43d: 48 8b 53 18 mov 0x18(%rbx),%rdx + 41a441: 48 3b 58 18 cmp 0x18(%rax),%rbx + 41a445: 0f 85 52 ff ff ff jne 41a39d <_int_free+0xbdd> + 41a44b: 48 3b 5a 10 cmp 0x10(%rdx),%rbx + 41a44f: 0f 84 7e f5 ff ff je 4199d3 <_int_free+0x213> + 41a455: 83 4d 04 04 orl $0x4,0x4(%rbp) + 41a459: e9 35 ff ff ff jmpq 41a393 <_int_free+0xbd3> + 41a45e: 66 90 xchg %ax,%ax + 41a460: 44 8b 15 09 03 2b 00 mov 0x2b0309(%rip),%r10d # 6ca770 + 41a467: 83 4d 04 04 orl $0x4,0x4(%rbp) + 41a46b: 44 89 d0 mov %r10d,%eax + 41a46e: 83 e0 05 and $0x5,%eax + 41a471: 83 f8 05 cmp $0x5,%eax + 41a474: 0f 84 c2 05 00 00 je 41aa3c <_int_free+0x127c> + 41a47a: 41 f6 c2 01 test $0x1,%r10b + 41a47e: 0f 85 f3 02 00 00 jne 41a777 <_int_free+0xfb7> + 41a484: 41 f6 c2 02 test $0x2,%r10b + 41a488: 0f 85 16 fd ff ff jne 41a1a4 <_int_free+0x9e4> + 41a48e: 49 8b 45 10 mov 0x10(%r13),%rax + 41a492: 49 8b 55 18 mov 0x18(%r13),%rdx + 41a496: 4c 39 68 18 cmp %r13,0x18(%rax) + 41a49a: 0f 85 fa fc ff ff jne 41a19a <_int_free+0x9da> + 41a4a0: 4c 8b 42 10 mov 0x10(%rdx),%r8 + 41a4a4: 4d 39 c5 cmp %r8,%r13 + 41a4a7: 0f 84 c3 f5 ff ff je 419a70 <_int_free+0x2b0> + 41a4ad: 83 4d 04 04 orl $0x4,0x4(%rbp) + 41a4b1: e9 da fc ff ff jmpq 41a190 <_int_free+0x9d0> + 41a4b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41a4bd: 00 00 00 + 41a4c0: 44 89 d7 mov %r10d,%edi + 41a4c3: ba 78 20 4a 00 mov $0x4a2078,%edx + 41a4c8: be 3c ca 4b 00 mov $0x4bca3c,%esi + 41a4cd: 83 e7 02 and $0x2,%edi + 41a4d0: 31 c0 xor %eax,%eax + 41a4d2: e8 e9 70 ff ff callq 4115c0 <__libc_message> + 41a4d7: e9 be f6 ff ff jmpq 419b9a <_int_free+0x3da> + 41a4dc: 44 8b 15 8d 02 2b 00 mov 0x2b028d(%rip),%r10d # 6ca770 + 41a4e3: 83 4d 04 04 orl $0x4,0x4(%rbp) + 41a4e7: 44 89 d2 mov %r10d,%edx + 41a4ea: 83 e2 05 and $0x5,%edx + 41a4ed: 83 fa 05 cmp $0x5,%edx + 41a4f0: 0f 84 f9 05 00 00 je 41aaef <_int_free+0x132f> + 41a4f6: 41 f6 c2 01 test $0x1,%r10b + 41a4fa: 0f 85 36 03 00 00 jne 41a836 <_int_free+0x1076> + 41a500: 41 83 e2 02 and $0x2,%r10d + 41a504: 0f 84 c7 fd ff ff je 41a2d1 <_int_free+0xb11> + 41a50a: e9 95 fc ff ff jmpq 41a1a4 <_int_free+0x9e4> + 41a50f: 90 nop + 41a510: 49 39 c4 cmp %rax,%r12 + 41a513: 0f 84 95 05 00 00 je 41aaae <_int_free+0x12ee> + 41a519: 49 89 46 20 mov %rax,0x20(%r14) + 41a51d: 49 8b 44 24 28 mov 0x28(%r12),%rax + 41a522: 49 89 46 28 mov %rax,0x28(%r14) + 41a526: 49 8b 44 24 20 mov 0x20(%r12),%rax + 41a52b: 4c 89 70 28 mov %r14,0x28(%rax) + 41a52f: 49 8b 44 24 28 mov 0x28(%r12),%rax + 41a534: 4c 89 70 20 mov %r14,0x20(%rax) + 41a538: e9 a3 f6 ff ff jmpq 419be0 <_int_free+0x420> + 41a53d: 4c 8d 5c 24 30 lea 0x30(%rsp),%r11 + 41a542: 48 8d 74 24 40 lea 0x40(%rsp),%rsi + 41a547: 31 c9 xor %ecx,%ecx + 41a549: ba 10 00 00 00 mov $0x10,%edx + 41a54e: 48 89 df mov %rbx,%rdi + 41a551: 44 88 4c 24 18 mov %r9b,0x18(%rsp) + 41a556: 44 89 54 24 10 mov %r10d,0x10(%rsp) + 41a55b: 4c 89 5c 24 08 mov %r11,0x8(%rsp) + 41a560: c6 44 24 40 00 movb $0x0,0x40(%rsp) + 41a565: e8 46 79 03 00 callq 451eb0 <_itoa_word> + 41a56a: 4c 8b 5c 24 08 mov 0x8(%rsp),%r11 + 41a56f: 49 89 c0 mov %rax,%r8 + 41a572: 44 8b 54 24 10 mov 0x10(%rsp),%r10d + 41a577: 44 0f b6 4c 24 18 movzbl 0x18(%rsp),%r9d + 41a57d: 4c 39 d8 cmp %r11,%rax + 41a580: 76 3d jbe 41a5bf <_int_free+0xdff> + 41a582: 4c 89 c2 mov %r8,%rdx + 41a585: 4c 89 c7 mov %r8,%rdi + 41a588: 48 8d 40 ff lea -0x1(%rax),%rax + 41a58c: 4c 29 da sub %r11,%rdx + 41a58f: be 30 00 00 00 mov $0x30,%esi + 41a594: 4c 89 44 24 08 mov %r8,0x8(%rsp) + 41a599: 48 29 d7 sub %rdx,%rdi + 41a59c: 49 89 c6 mov %rax,%r14 + 41a59f: e8 ac 5d fe ff callq 400350 <__rela_iplt_end+0x88> + 41a5a4: 48 8d 44 24 2f lea 0x2f(%rsp),%rax + 41a5a9: 4c 8b 44 24 08 mov 0x8(%rsp),%r8 + 41a5ae: 44 0f b6 4c 24 18 movzbl 0x18(%rsp),%r9d + 41a5b4: 44 8b 54 24 10 mov 0x10(%rsp),%r10d + 41a5b9: 4c 29 f0 sub %r14,%rax + 41a5bc: 49 01 c0 add %rax,%r8 + 41a5bf: 48 8b 05 fa 2c 2b 00 mov 0x2b2cfa(%rip),%rax # 6cd2c0 <__libc_argv> + 41a5c6: 44 89 d7 mov %r10d,%edi + 41a5c9: ba 38 20 4a 00 mov $0x4a2038,%edx + 41a5ce: b9 95 20 4a 00 mov $0x4a2095,%ecx + 41a5d3: be a8 23 4a 00 mov $0x4a23a8,%esi + 41a5d8: 44 88 4c 24 08 mov %r9b,0x8(%rsp) + 41a5dd: 48 8b 00 mov (%rax),%rax + 41a5e0: 48 85 c0 test %rax,%rax + 41a5e3: 48 0f 45 d0 cmovne %rax,%rdx + 41a5e7: 83 e7 02 and $0x2,%edi + 41a5ea: 31 c0 xor %eax,%eax + 41a5ec: e8 cf 6f ff ff callq 4115c0 <__libc_message> + 41a5f1: 44 0f b6 4c 24 08 movzbl 0x8(%rsp),%r9d + 41a5f7: e9 2c f4 ff ff jmpq 419a28 <_int_free+0x268> + 41a5fc: 4c 8d 5c 24 30 lea 0x30(%rsp),%r11 + 41a601: 48 8d 74 24 40 lea 0x40(%rsp),%rsi + 41a606: 31 c9 xor %ecx,%ecx + 41a608: ba 10 00 00 00 mov $0x10,%edx + 41a60d: 4c 89 ef mov %r13,%rdi + 41a610: 44 88 4c 24 18 mov %r9b,0x18(%rsp) + 41a615: 44 89 54 24 10 mov %r10d,0x10(%rsp) + 41a61a: 4c 89 5c 24 08 mov %r11,0x8(%rsp) + 41a61f: c6 44 24 40 00 movb $0x0,0x40(%rsp) + 41a624: e8 87 78 03 00 callq 451eb0 <_itoa_word> + 41a629: 4c 8b 5c 24 08 mov 0x8(%rsp),%r11 + 41a62e: 49 89 c0 mov %rax,%r8 + 41a631: 44 8b 54 24 10 mov 0x10(%rsp),%r10d + 41a636: 44 0f b6 4c 24 18 movzbl 0x18(%rsp),%r9d + 41a63c: 4c 39 d8 cmp %r11,%rax + 41a63f: 76 3a jbe 41a67b <_int_free+0xebb> + 41a641: 48 89 c2 mov %rax,%rdx + 41a644: 48 89 c7 mov %rax,%rdi + 41a647: be 30 00 00 00 mov $0x30,%esi + 41a64c: 4c 29 da sub %r11,%rdx + 41a64f: 4c 8d 68 ff lea -0x1(%rax),%r13 + 41a653: 48 89 44 24 08 mov %rax,0x8(%rsp) + 41a658: 48 29 d7 sub %rdx,%rdi + 41a65b: e8 f0 5c fe ff callq 400350 <__rela_iplt_end+0x88> + 41a660: 48 8d 44 24 2f lea 0x2f(%rsp),%rax + 41a665: 4c 8b 44 24 08 mov 0x8(%rsp),%r8 + 41a66a: 44 0f b6 4c 24 18 movzbl 0x18(%rsp),%r9d + 41a670: 44 8b 54 24 10 mov 0x10(%rsp),%r10d + 41a675: 4c 29 e8 sub %r13,%rax + 41a678: 49 01 c0 add %rax,%r8 + 41a67b: 48 8b 05 3e 2c 2b 00 mov 0x2b2c3e(%rip),%rax # 6cd2c0 <__libc_argv> + 41a682: 44 89 d7 mov %r10d,%edi + 41a685: ba 38 20 4a 00 mov $0x4a2038,%edx + 41a68a: b9 95 20 4a 00 mov $0x4a2095,%ecx + 41a68f: be a8 23 4a 00 mov $0x4a23a8,%esi + 41a694: 44 88 4c 24 08 mov %r9b,0x8(%rsp) + 41a699: 48 8b 00 mov (%rax),%rax + 41a69c: 48 85 c0 test %rax,%rax + 41a69f: 48 0f 45 d0 cmovne %rax,%rdx + 41a6a3: 83 e7 02 and $0x2,%edi + 41a6a6: 31 c0 xor %eax,%eax + 41a6a8: e8 13 6f ff ff callq 4115c0 <__libc_message> + 41a6ad: 44 0f b6 4c 24 08 movzbl 0x8(%rsp),%r9d + 41a6b3: e9 ce f3 ff ff jmpq 419a86 <_int_free+0x2c6> + 41a6b8: 4c 8d 5c 24 30 lea 0x30(%rsp),%r11 + 41a6bd: 48 8d 74 24 40 lea 0x40(%rsp),%rsi + 41a6c2: 31 c9 xor %ecx,%ecx + 41a6c4: ba 10 00 00 00 mov $0x10,%edx + 41a6c9: 48 89 df mov %rbx,%rdi + 41a6cc: 44 88 4c 24 18 mov %r9b,0x18(%rsp) + 41a6d1: 44 89 54 24 10 mov %r10d,0x10(%rsp) + 41a6d6: 4c 89 5c 24 08 mov %r11,0x8(%rsp) + 41a6db: c6 44 24 40 00 movb $0x0,0x40(%rsp) + 41a6e0: e8 cb 77 03 00 callq 451eb0 <_itoa_word> + 41a6e5: 4c 8b 5c 24 08 mov 0x8(%rsp),%r11 + 41a6ea: 49 89 c0 mov %rax,%r8 + 41a6ed: 44 8b 54 24 10 mov 0x10(%rsp),%r10d + 41a6f2: 44 0f b6 4c 24 18 movzbl 0x18(%rsp),%r9d + 41a6f8: 4c 39 d8 cmp %r11,%rax + 41a6fb: 76 3d jbe 41a73a <_int_free+0xf7a> + 41a6fd: 4c 89 c2 mov %r8,%rdx + 41a700: 4c 89 c7 mov %r8,%rdi + 41a703: 48 8d 40 ff lea -0x1(%rax),%rax + 41a707: 4c 29 da sub %r11,%rdx + 41a70a: be 30 00 00 00 mov $0x30,%esi + 41a70f: 4c 89 44 24 08 mov %r8,0x8(%rsp) + 41a714: 48 29 d7 sub %rdx,%rdi + 41a717: 49 89 c6 mov %rax,%r14 + 41a71a: e8 31 5c fe ff callq 400350 <__rela_iplt_end+0x88> + 41a71f: 48 8d 44 24 2f lea 0x2f(%rsp),%rax + 41a724: 4c 8b 44 24 08 mov 0x8(%rsp),%r8 + 41a729: 44 0f b6 4c 24 18 movzbl 0x18(%rsp),%r9d + 41a72f: 44 8b 54 24 10 mov 0x10(%rsp),%r10d + 41a734: 4c 29 f0 sub %r14,%rax + 41a737: 49 01 c0 add %rax,%r8 + 41a73a: 48 8b 05 7f 2b 2b 00 mov 0x2b2b7f(%rip),%rax # 6cd2c0 <__libc_argv> + 41a741: 44 89 d7 mov %r10d,%edi + 41a744: ba 38 20 4a 00 mov $0x4a2038,%edx + 41a749: b9 78 20 4a 00 mov $0x4a2078,%ecx + 41a74e: be a8 23 4a 00 mov $0x4a23a8,%esi + 41a753: 44 88 4c 24 08 mov %r9b,0x8(%rsp) + 41a758: 48 8b 00 mov (%rax),%rax + 41a75b: 48 85 c0 test %rax,%rax + 41a75e: 48 0f 45 d0 cmovne %rax,%rdx + 41a762: 83 e7 02 and $0x2,%edi + 41a765: 31 c0 xor %eax,%eax + 41a767: e8 54 6e ff ff callq 4115c0 <__libc_message> + 41a76c: 44 0f b6 4c 24 08 movzbl 0x8(%rsp),%r9d + 41a772: e9 40 f2 ff ff jmpq 4199b7 <_int_free+0x1f7> + 41a777: 4c 8d 5c 24 30 lea 0x30(%rsp),%r11 + 41a77c: 48 8d 74 24 40 lea 0x40(%rsp),%rsi + 41a781: 31 c9 xor %ecx,%ecx + 41a783: ba 10 00 00 00 mov $0x10,%edx + 41a788: 4c 89 ef mov %r13,%rdi + 41a78b: 44 88 4c 24 18 mov %r9b,0x18(%rsp) + 41a790: 44 89 54 24 10 mov %r10d,0x10(%rsp) + 41a795: 4c 89 5c 24 08 mov %r11,0x8(%rsp) + 41a79a: c6 44 24 40 00 movb $0x0,0x40(%rsp) + 41a79f: e8 0c 77 03 00 callq 451eb0 <_itoa_word> + 41a7a4: 4c 8b 5c 24 08 mov 0x8(%rsp),%r11 + 41a7a9: 49 89 c0 mov %rax,%r8 + 41a7ac: 44 8b 54 24 10 mov 0x10(%rsp),%r10d + 41a7b1: 44 0f b6 4c 24 18 movzbl 0x18(%rsp),%r9d + 41a7b7: 4c 39 d8 cmp %r11,%rax + 41a7ba: 76 3d jbe 41a7f9 <_int_free+0x1039> + 41a7bc: 4c 89 c2 mov %r8,%rdx + 41a7bf: 4c 89 c7 mov %r8,%rdi + 41a7c2: 48 8d 40 ff lea -0x1(%rax),%rax + 41a7c6: 4c 29 da sub %r11,%rdx + 41a7c9: be 30 00 00 00 mov $0x30,%esi + 41a7ce: 4c 89 44 24 08 mov %r8,0x8(%rsp) + 41a7d3: 48 29 d7 sub %rdx,%rdi + 41a7d6: 49 89 c6 mov %rax,%r14 + 41a7d9: e8 72 5b fe ff callq 400350 <__rela_iplt_end+0x88> + 41a7de: 48 8d 44 24 2f lea 0x2f(%rsp),%rax + 41a7e3: 4c 8b 44 24 08 mov 0x8(%rsp),%r8 + 41a7e8: 44 0f b6 4c 24 18 movzbl 0x18(%rsp),%r9d + 41a7ee: 44 8b 54 24 10 mov 0x10(%rsp),%r10d + 41a7f3: 4c 29 f0 sub %r14,%rax + 41a7f6: 49 01 c0 add %rax,%r8 + 41a7f9: 48 8b 05 c0 2a 2b 00 mov 0x2b2ac0(%rip),%rax # 6cd2c0 <__libc_argv> + 41a800: 44 89 d7 mov %r10d,%edi + 41a803: ba 38 20 4a 00 mov $0x4a2038,%edx + 41a808: b9 78 20 4a 00 mov $0x4a2078,%ecx + 41a80d: be a8 23 4a 00 mov $0x4a23a8,%esi + 41a812: 44 88 4c 24 08 mov %r9b,0x8(%rsp) + 41a817: 48 8b 00 mov (%rax),%rax + 41a81a: 48 85 c0 test %rax,%rax + 41a81d: 48 0f 45 d0 cmovne %rax,%rdx + 41a821: 83 e7 02 and $0x2,%edi + 41a824: 31 c0 xor %eax,%eax + 41a826: e8 95 6d ff ff callq 4115c0 <__libc_message> + 41a82b: 44 0f b6 4c 24 08 movzbl 0x8(%rsp),%r9d + 41a831: e9 1b f2 ff ff jmpq 419a51 <_int_free+0x291> + 41a836: 48 8d 74 24 40 lea 0x40(%rsp),%rsi + 41a83b: 31 c9 xor %ecx,%ecx + 41a83d: ba 10 00 00 00 mov $0x10,%edx + 41a842: 4c 89 e7 mov %r12,%rdi + 41a845: 44 89 54 24 18 mov %r10d,0x18(%rsp) + 41a84a: c6 44 24 40 00 movb $0x0,0x40(%rsp) + 41a84f: e8 5c 76 03 00 callq 451eb0 <_itoa_word> + 41a854: 49 89 c0 mov %rax,%r8 + 41a857: 48 8d 44 24 30 lea 0x30(%rsp),%rax + 41a85c: 44 8b 54 24 18 mov 0x18(%rsp),%r10d + 41a861: 49 39 c0 cmp %rax,%r8 + 41a864: 76 46 jbe 41a8ac <_int_free+0x10ec> + 41a866: 48 8b 44 24 10 mov 0x10(%rsp),%rax + 41a86b: 49 8d 48 ff lea -0x1(%r8),%rcx + 41a86f: 4c 89 c7 mov %r8,%rdi + 41a872: be 30 00 00 00 mov $0x30,%esi + 41a877: 44 89 54 24 2c mov %r10d,0x2c(%rsp) + 41a87c: 4c 89 44 24 18 mov %r8,0x18(%rsp) + 41a881: 48 89 4c 24 20 mov %rcx,0x20(%rsp) + 41a886: 48 8d 14 08 lea (%rax,%rcx,1),%rdx + 41a88a: 48 29 d7 sub %rdx,%rdi + 41a88d: e8 be 5a fe ff callq 400350 <__rela_iplt_end+0x88> + 41a892: 48 8b 4c 24 20 mov 0x20(%rsp),%rcx + 41a897: 48 8d 44 24 2f lea 0x2f(%rsp),%rax + 41a89c: 4c 8b 44 24 18 mov 0x18(%rsp),%r8 + 41a8a1: 44 8b 54 24 2c mov 0x2c(%rsp),%r10d + 41a8a6: 48 29 c8 sub %rcx,%rax + 41a8a9: 49 01 c0 add %rax,%r8 + 41a8ac: 48 8b 05 0d 2a 2b 00 mov 0x2b2a0d(%rip),%rax # 6cd2c0 <__libc_argv> + 41a8b3: 44 89 d7 mov %r10d,%edi + 41a8b6: ba 38 20 4a 00 mov $0x4a2038,%edx + 41a8bb: b9 f0 23 4a 00 mov $0x4a23f0,%ecx + 41a8c0: be a8 23 4a 00 mov $0x4a23a8,%esi + 41a8c5: 48 8b 00 mov (%rax),%rax + 41a8c8: 48 85 c0 test %rax,%rax + 41a8cb: 48 0f 45 d0 cmovne %rax,%rdx + 41a8cf: 31 c0 xor %eax,%eax + 41a8d1: 83 e7 02 and $0x2,%edi + 41a8d4: e8 e7 6c ff ff callq 4115c0 <__libc_message> + 41a8d9: 49 8b 44 24 20 mov 0x20(%r12),%rax + 41a8de: e9 ee f9 ff ff jmpq 41a2d1 <_int_free+0xb11> + 41a8e3: 44 89 d7 mov %r10d,%edi + 41a8e6: ba 95 20 4a 00 mov $0x4a2095,%edx + 41a8eb: be 3c ca 4b 00 mov $0x4bca3c,%esi + 41a8f0: 83 e7 02 and $0x2,%edi + 41a8f3: 31 c0 xor %eax,%eax + 41a8f5: 44 88 4c 24 08 mov %r9b,0x8(%rsp) + 41a8fa: e8 c1 6c ff ff callq 4115c0 <__libc_message> + 41a8ff: 44 0f b6 4c 24 08 movzbl 0x8(%rsp),%r9d + 41a905: e9 1e f1 ff ff jmpq 419a28 <_int_free+0x268> + 41a90a: 44 89 d7 mov %r10d,%edi + 41a90d: ba 95 20 4a 00 mov $0x4a2095,%edx + 41a912: be 3c ca 4b 00 mov $0x4bca3c,%esi + 41a917: 83 e7 02 and $0x2,%edi + 41a91a: 31 c0 xor %eax,%eax + 41a91c: 44 88 4c 24 08 mov %r9b,0x8(%rsp) + 41a921: e8 9a 6c ff ff callq 4115c0 <__libc_message> + 41a926: 44 0f b6 4c 24 08 movzbl 0x8(%rsp),%r9d + 41a92c: e9 55 f1 ff ff jmpq 419a86 <_int_free+0x2c6> + 41a931: 45 31 c9 xor %r9d,%r9d + 41a934: 31 d2 xor %edx,%edx + 41a936: 41 b8 ff ff ff ff mov $0xffffffff,%r8d + 41a93c: b9 32 00 00 00 mov $0x32,%ecx + 41a941: 4c 89 ee mov %r13,%rsi + 41a944: e8 a7 52 02 00 callq 43fbf0 <__mmap> + 41a949: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 41a94d: 0f 84 2d f5 ff ff je 419e80 <_int_free+0x6c0> + 41a953: 4d 89 77 18 mov %r14,0x18(%r15) + 41a957: e9 fe f4 ff ff jmpq 419e5a <_int_free+0x69a> + 41a95c: 44 8b 05 35 f6 2a 00 mov 0x2af635(%rip),%r8d # 6c9f98 <__libc_enable_secure> + 41a963: 45 85 c0 test %r8d,%r8d + 41a966: 44 89 05 f3 fd 2a 00 mov %r8d,0x2afdf3(%rip) # 6ca760 + 41a96d: 75 64 jne 41a9d3 <_int_free+0x1213> + 41a96f: be 00 00 08 00 mov $0x80000,%esi + 41a974: bf 00 26 4a 00 mov $0x4a2600,%edi + 41a979: b8 02 00 00 00 mov $0x2,%eax + 41a97e: 0f 05 syscall + 41a980: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 41a986: 0f 87 27 02 00 00 ja 41abb3 <_int_free+0x13f3> + 41a98c: 85 c0 test %eax,%eax + 41a98e: 78 43 js 41a9d3 <_int_free+0x1213> + 41a990: 4c 63 c8 movslq %eax,%r9 + 41a993: ba 01 00 00 00 mov $0x1,%edx + 41a998: 48 8d 74 24 30 lea 0x30(%rsp),%rsi + 41a99d: 4c 89 cf mov %r9,%rdi + 41a9a0: 44 89 c0 mov %r8d,%eax + 41a9a3: 0f 05 syscall + 41a9a5: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 41a9ab: 0f 87 f1 01 00 00 ja 41aba2 <_int_free+0x13e2> + 41a9b1: 48 85 c0 test %rax,%rax + 41a9b4: 7e 0c jle 41a9c2 <_int_free+0x1202> + 41a9b6: 45 31 c0 xor %r8d,%r8d + 41a9b9: 80 7c 24 30 32 cmpb $0x32,0x30(%rsp) + 41a9be: 41 0f 94 c0 sete %r8b + 41a9c2: 44 89 05 97 fd 2a 00 mov %r8d,0x2afd97(%rip) # 6ca760 + 41a9c9: 4c 89 cf mov %r9,%rdi + 41a9cc: b8 03 00 00 00 mov $0x3,%eax + 41a9d1: 0f 05 syscall + 41a9d3: 8b 0d 87 fd 2a 00 mov 0x2afd87(%rip),%ecx # 6ca760 + 41a9d9: 85 c9 test %ecx,%ecx + 41a9db: 0f 95 c0 setne %al + 41a9de: e9 5e f4 ff ff jmpq 419e41 <_int_free+0x681> + 41a9e3: b9 88 2e 4a 00 mov $0x4a2e88,%ecx + 41a9e8: ba 37 02 00 00 mov $0x237,%edx + 41a9ed: be a8 1f 4a 00 mov $0x4a1fa8,%esi + 41a9f2: bf 28 25 4a 00 mov $0x4a2528,%edi + 41a9f7: e8 24 c4 ff ff callq 416e20 <__malloc_assert> + 41a9fc: b9 88 2e 4a 00 mov $0x4a2e88,%ecx + 41aa01: ba 34 02 00 00 mov $0x234,%edx + 41aa06: be a8 1f 4a 00 mov $0x4a1fa8,%esi + 41aa0b: bf 0f 21 4a 00 mov $0x4a210f,%edi + 41aa10: e8 0b c4 ff ff callq 416e20 <__malloc_assert> + 41aa15: 44 89 d7 mov %r10d,%edi + 41aa18: ba 78 20 4a 00 mov $0x4a2078,%edx + 41aa1d: be 3c ca 4b 00 mov $0x4bca3c,%esi + 41aa22: 83 e7 02 and $0x2,%edi + 41aa25: 31 c0 xor %eax,%eax + 41aa27: 44 88 4c 24 08 mov %r9b,0x8(%rsp) + 41aa2c: e8 8f 6b ff ff callq 4115c0 <__libc_message> + 41aa31: 44 0f b6 4c 24 08 movzbl 0x8(%rsp),%r9d + 41aa37: e9 7b ef ff ff jmpq 4199b7 <_int_free+0x1f7> + 41aa3c: 44 89 d7 mov %r10d,%edi + 41aa3f: ba 78 20 4a 00 mov $0x4a2078,%edx + 41aa44: be 3c ca 4b 00 mov $0x4bca3c,%esi + 41aa49: 83 e7 02 and $0x2,%edi + 41aa4c: 31 c0 xor %eax,%eax + 41aa4e: 44 88 4c 24 08 mov %r9b,0x8(%rsp) + 41aa53: e8 68 6b ff ff callq 4115c0 <__libc_message> + 41aa58: 44 0f b6 4c 24 08 movzbl 0x8(%rsp),%r9d + 41aa5e: e9 ee ef ff ff jmpq 419a51 <_int_free+0x291> + 41aa63: b9 88 2e 4a 00 mov $0x4a2e88,%ecx + 41aa68: ba 3a 02 00 00 mov $0x23a,%edx + 41aa6d: be a8 1f 4a 00 mov $0x4a1fa8,%esi + 41aa72: bf 58 25 4a 00 mov $0x4a2558,%edi + 41aa77: e8 a4 c3 ff ff callq 416e20 <__malloc_assert> + 41aa7c: b9 88 2e 4a 00 mov $0x4a2e88,%ecx + 41aa81: ba 48 02 00 00 mov $0x248,%edx + 41aa86: be a8 1f 4a 00 mov $0x4a1fa8,%esi + 41aa8b: bf c8 25 4a 00 mov $0x4a25c8,%edi + 41aa90: e8 8b c3 ff ff callq 416e20 <__malloc_assert> + 41aa95: b9 88 2e 4a 00 mov $0x4a2e88,%ecx + 41aa9a: ba 47 02 00 00 mov $0x247,%edx + 41aa9f: be a8 1f 4a 00 mov $0x4a1fa8,%esi + 41aaa4: bf 88 25 4a 00 mov $0x4a2588,%edi + 41aaa9: e8 72 c3 ff ff callq 416e20 <__malloc_assert> + 41aaae: 4d 89 76 28 mov %r14,0x28(%r14) + 41aab2: 4d 89 76 20 mov %r14,0x20(%r14) + 41aab6: e9 25 f1 ff ff jmpq 419be0 <_int_free+0x420> + 41aabb: 8b 3d af fc 2a 00 mov 0x2afcaf(%rip),%edi # 6ca770 + 41aac1: 48 89 da mov %rbx,%rdx + 41aac4: 48 89 e9 mov %rbp,%rcx + 41aac7: be f0 23 4a 00 mov $0x4a23f0,%esi + 41aacc: 44 88 4c 24 10 mov %r9b,0x10(%rsp) + 41aad1: 48 89 44 24 08 mov %rax,0x8(%rsp) + 41aad6: e8 d5 c7 ff ff callq 4172b0 + 41aadb: 48 8b 53 20 mov 0x20(%rbx),%rdx + 41aadf: 44 0f b6 4c 24 10 movzbl 0x10(%rsp),%r9d + 41aae5: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 41aaea: e9 17 ef ff ff jmpq 419a06 <_int_free+0x246> + 41aaef: 44 89 d7 mov %r10d,%edi + 41aaf2: 31 c0 xor %eax,%eax + 41aaf4: ba f0 23 4a 00 mov $0x4a23f0,%edx + 41aaf9: 83 e7 02 and $0x2,%edi + 41aafc: be 3c ca 4b 00 mov $0x4bca3c,%esi + 41ab01: e8 ba 6a ff ff callq 4115c0 <__libc_message> + 41ab06: 49 8b 44 24 20 mov 0x20(%r12),%rax + 41ab0b: e9 c1 f7 ff ff jmpq 41a2d1 <_int_free+0xb11> + 41ab10: 48 39 d3 cmp %rdx,%rbx + 41ab13: 0f 84 f9 00 00 00 je 41ac12 <_int_free+0x1452> + 41ab19: 48 89 50 20 mov %rdx,0x20(%rax) + 41ab1d: 48 8b 53 28 mov 0x28(%rbx),%rdx + 41ab21: 48 89 50 28 mov %rdx,0x28(%rax) + 41ab25: 48 8b 53 20 mov 0x20(%rbx),%rdx + 41ab29: 48 89 42 28 mov %rax,0x28(%rdx) + 41ab2d: 48 8b 53 28 mov 0x28(%rbx),%rdx + 41ab31: 48 89 42 20 mov %rax,0x20(%rdx) + 41ab35: e9 ee ee ff ff jmpq 419a28 <_int_free+0x268> + 41ab3a: 49 39 d0 cmp %rdx,%r8 + 41ab3d: 0f 84 dc 00 00 00 je 41ac1f <_int_free+0x145f> + 41ab43: 48 89 50 20 mov %rdx,0x20(%rax) + 41ab47: 49 8b 50 28 mov 0x28(%r8),%rdx + 41ab4b: 48 89 50 28 mov %rdx,0x28(%rax) + 41ab4f: 49 8b 50 20 mov 0x20(%r8),%rdx + 41ab53: 48 89 42 28 mov %rax,0x28(%rdx) + 41ab57: 49 8b 50 28 mov 0x28(%r8),%rdx + 41ab5b: 48 89 42 20 mov %rax,0x20(%rdx) + 41ab5f: e9 22 ef ff ff jmpq 419a86 <_int_free+0x2c6> + 41ab64: 8b 3d 06 fc 2a 00 mov 0x2afc06(%rip),%edi # 6ca770 + 41ab6a: 4c 89 c2 mov %r8,%rdx + 41ab6d: 48 89 e9 mov %rbp,%rcx + 41ab70: be f0 23 4a 00 mov $0x4a23f0,%esi + 41ab75: 44 88 4c 24 18 mov %r9b,0x18(%rsp) + 41ab7a: 48 89 44 24 10 mov %rax,0x10(%rsp) + 41ab7f: 4c 89 44 24 08 mov %r8,0x8(%rsp) + 41ab84: e8 27 c7 ff ff callq 4172b0 + 41ab89: 4c 8b 44 24 08 mov 0x8(%rsp),%r8 + 41ab8e: 44 0f b6 4c 24 18 movzbl 0x18(%rsp),%r9d + 41ab94: 48 8b 44 24 10 mov 0x10(%rsp),%rax + 41ab99: 49 8b 50 20 mov 0x20(%r8),%rdx + 41ab9d: e9 03 f5 ff ff jmpq 41a0a5 <_int_free+0x8e5> + 41aba2: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx + 41aba9: f7 d8 neg %eax + 41abab: 64 89 02 mov %eax,%fs:(%rdx) + 41abae: e9 0f fe ff ff jmpq 41a9c2 <_int_free+0x1202> + 41abb3: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx + 41abba: f7 d8 neg %eax + 41abbc: 64 89 02 mov %eax,%fs:(%rdx) + 41abbf: e9 0f fe ff ff jmpq 41a9d3 <_int_free+0x1213> + 41abc4: b9 98 2e 4a 00 mov $0x4a2e98,%ecx + 41abc9: ba fe 0f 00 00 mov $0xffe,%edx + 41abce: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 41abd3: bf 2b 21 4a 00 mov $0x4a212b,%edi + 41abd8: e8 43 c2 ff ff callq 416e20 <__malloc_assert> + 41abdd: b9 98 2e 4a 00 mov $0x4a2e98,%ecx + 41abe2: ba f8 0f 00 00 mov $0xff8,%edx + 41abe7: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 41abec: bf fc 20 4a 00 mov $0x4a20fc,%edi + 41abf1: e8 2a c2 ff ff callq 416e20 <__malloc_assert> + 41abf6: 48 8d 7e 10 lea 0x10(%rsi),%rdi + 41abfa: 41 bd 98 24 4a 00 mov $0x4a2498,%r13d + 41ac00: 44 8b 25 69 fb 2a 00 mov 0x2afb69(%rip),%r12d # 6ca770 + 41ac07: e9 d8 ec ff ff jmpq 4198e4 <_int_free+0x124> + 41ac0c: 48 8d 7b 10 lea 0x10(%rbx),%rdi + 41ac10: eb ee jmp 41ac00 <_int_free+0x1440> + 41ac12: 48 89 40 28 mov %rax,0x28(%rax) + 41ac16: 48 89 40 20 mov %rax,0x20(%rax) + 41ac1a: e9 09 ee ff ff jmpq 419a28 <_int_free+0x268> + 41ac1f: 48 89 40 28 mov %rax,0x28(%rax) + 41ac23: 48 89 40 20 mov %rax,0x20(%rax) + 41ac27: e9 5a ee ff ff jmpq 419a86 <_int_free+0x2c6> + 41ac2c: 0f 1f 40 00 nopl 0x0(%rax) + +000000000041ac30 : + 41ac30: 41 57 push %r15 + 41ac32: 41 56 push %r14 + 41ac34: 41 55 push %r13 + 41ac36: 41 54 push %r12 + 41ac38: 55 push %rbp + 41ac39: 53 push %rbx + 41ac3a: 48 89 fd mov %rdi,%rbp + 41ac3d: 48 83 ec 58 sub $0x58,%rsp + 41ac41: 48 85 f6 test %rsi,%rsi + 41ac44: 4c 8b 3d 35 05 2b 00 mov 0x2b0535(%rip),%r15 # 6cb180 <_dl_pagesize> + 41ac4b: 0f 84 bf 02 00 00 je 41af10 + 41ac51: 48 39 3d 58 fb 2a 00 cmp %rdi,0x2afb58(%rip) # 6ca7b0 + 41ac58: 48 89 f3 mov %rsi,%rbx + 41ac5b: 0f 86 8f 01 00 00 jbe 41adf0 + 41ac61: c6 44 24 08 00 movb $0x0,0x8(%rsp) + 41ac66: 48 8d 43 58 lea 0x58(%rbx),%rax + 41ac6a: 4d 8d 74 2f 07 lea 0x7(%r15,%rbp,1),%r14 + 41ac6f: 48 89 04 24 mov %rax,(%rsp) + 41ac73: 4c 89 f8 mov %r15,%rax + 41ac76: 48 f7 d8 neg %rax + 41ac79: 49 21 c6 and %rax,%r14 + 41ac7c: 4c 89 74 24 18 mov %r14,0x18(%rsp) + 41ac81: 4c 8b 6b 58 mov 0x58(%rbx),%r13 + 41ac85: 49 8b 45 08 mov 0x8(%r13),%rax + 41ac89: 49 89 c4 mov %rax,%r12 + 41ac8c: 49 83 e4 f8 and $0xfffffffffffffff8,%r12 + 41ac90: 4d 85 e4 test %r12,%r12 + 41ac93: 4f 8d 54 25 00 lea 0x0(%r13,%r12,1),%r10 + 41ac98: 41 0f 95 c3 setne %r11b + 41ac9c: 4c 3b 2c 24 cmp (%rsp),%r13 + 41aca0: 0f 85 1a 01 00 00 jne 41adc0 + 41aca6: 45 84 db test %r11b,%r11b + 41aca9: 0f 85 11 01 00 00 jne 41adc0 + 41acaf: 4c 8d 45 20 lea 0x20(%rbp),%r8 + 41acb3: 4d 39 c4 cmp %r8,%r12 + 41acb6: 0f 83 b7 07 00 00 jae 41b473 + 41acbc: 48 81 fb 00 a8 6c 00 cmp $0x6ca800,%rbx + 41acc3: 0f 84 f7 02 00 00 je 41afc0 + 41acc9: 48 89 ea mov %rbp,%rdx + 41accc: 4d 89 ee mov %r13,%r14 + 41accf: 4c 29 e2 sub %r12,%rdx + 41acd2: 49 81 e6 00 00 00 fc and $0xfffffffffc000000,%r14 + 41acd9: 48 83 c2 20 add $0x20,%rdx + 41acdd: 48 85 d2 test %rdx,%rdx + 41ace0: 0f 8e 42 01 00 00 jle 41ae28 + 41ace6: 48 8b 05 93 04 2b 00 mov 0x2b0493(%rip),%rax # 6cb180 <_dl_pagesize> + 41aced: 4d 8b 4e 10 mov 0x10(%r14),%r9 + 41acf1: 48 8d 4c 02 ff lea -0x1(%rdx,%rax,1),%rcx + 41acf6: 48 f7 d8 neg %rax + 41acf9: 48 21 c8 and %rcx,%rax + 41acfc: 4a 8d 0c 08 lea (%rax,%r9,1),%rcx + 41ad00: 48 81 f9 00 00 00 04 cmp $0x4000000,%rcx + 41ad07: 0f 87 1b 01 00 00 ja 41ae28 + 41ad0d: 49 8b 7e 18 mov 0x18(%r14),%rdi + 41ad11: 48 39 f9 cmp %rdi,%rcx + 41ad14: 0f 87 a6 01 00 00 ja 41aec0 + 41ad1a: 4c 89 f0 mov %r14,%rax + 41ad1d: 4c 89 ea mov %r13,%rdx + 41ad20: 4d 89 c6 mov %r8,%r14 + 41ad23: 49 89 c0 mov %rax,%r8 + 41ad26: 49 89 48 10 mov %rcx,0x10(%r8) + 41ad2a: 90 nop + 41ad2b: 48 89 c8 mov %rcx,%rax + 41ad2e: 4c 01 c1 add %r8,%rcx + 41ad31: 4c 29 c8 sub %r9,%rax + 41ad34: 48 01 05 dd 18 2b 00 add %rax,0x2b18dd(%rip) # 6cc618 + 41ad3b: 4c 29 e9 sub %r13,%rcx + 41ad3e: 48 89 c6 mov %rax,%rsi + 41ad41: 48 03 b3 80 08 00 00 add 0x880(%rbx),%rsi + 41ad48: 48 83 c9 01 or $0x1,%rcx + 41ad4c: 48 89 b3 80 08 00 00 mov %rsi,0x880(%rbx) + 41ad53: 49 89 4d 08 mov %rcx,0x8(%r13) + 41ad57: 48 39 b3 88 08 00 00 cmp %rsi,0x888(%rbx) + 41ad5e: 73 07 jae 41ad67 + 41ad60: 48 89 b3 88 08 00 00 mov %rsi,0x888(%rbx) + 41ad67: 48 8b 42 08 mov 0x8(%rdx),%rax + 41ad6b: 48 83 e0 f8 and $0xfffffffffffffff8,%rax + 41ad6f: 49 39 c6 cmp %rax,%r14 + 41ad72: 0f 87 58 03 00 00 ja 41b0d0 + 41ad78: 48 29 e8 sub %rbp,%rax + 41ad7b: 31 c9 xor %ecx,%ecx + 41ad7d: 48 81 fb 00 a8 6c 00 cmp $0x6ca800,%rbx + 41ad84: 0f 95 c1 setne %cl + 41ad87: 48 8d 34 2a lea (%rdx,%rbp,1),%rsi + 41ad8b: 48 83 cd 01 or $0x1,%rbp + 41ad8f: 48 c1 e1 02 shl $0x2,%rcx + 41ad93: 48 83 c8 01 or $0x1,%rax + 41ad97: 48 83 c2 10 add $0x10,%rdx + 41ad9b: 48 09 e9 or %rbp,%rcx + 41ad9e: 48 89 73 58 mov %rsi,0x58(%rbx) + 41ada2: 48 89 4a f8 mov %rcx,-0x8(%rdx) + 41ada6: 48 89 46 08 mov %rax,0x8(%rsi) + 41adaa: 48 83 c4 58 add $0x58,%rsp + 41adae: 48 89 d0 mov %rdx,%rax + 41adb1: 5b pop %rbx + 41adb2: 5d pop %rbp + 41adb3: 41 5c pop %r12 + 41adb5: 41 5d pop %r13 + 41adb7: 41 5e pop %r14 + 41adb9: 41 5f pop %r15 + 41adbb: c3 retq + 41adbc: 0f 1f 40 00 nopl 0x0(%rax) + 41adc0: 49 83 fc 1f cmp $0x1f,%r12 + 41adc4: 76 11 jbe 41add7 + 41adc6: a8 01 test $0x1,%al + 41adc8: 74 0d je 41add7 + 41adca: 49 8d 47 ff lea -0x1(%r15),%rax + 41adce: 49 85 c2 test %rax,%r10 + 41add1: 0f 84 d8 fe ff ff je 41acaf + 41add7: b9 a8 2e 4a 00 mov $0x4a2ea8,%ecx + 41addc: ba 5a 09 00 00 mov $0x95a,%edx + 41ade1: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 41ade6: bf 60 26 4a 00 mov $0x4a2660,%edi + 41adeb: e8 30 c0 ff ff callq 416e20 <__malloc_assert> + 41adf0: 8b 05 d6 f9 2a 00 mov 0x2af9d6(%rip),%eax # 6ca7cc + 41adf6: 39 05 cc f9 2a 00 cmp %eax,0x2af9cc(%rip) # 6ca7c8 + 41adfc: 0f 8d 5f fe ff ff jge 41ac61 + 41ae02: 4d 8d 64 3f 07 lea 0x7(%r15,%rdi,1),%r12 + 41ae07: 4c 89 f8 mov %r15,%rax + 41ae0a: 48 f7 d8 neg %rax + 41ae0d: 49 21 c4 and %rax,%r12 + 41ae10: 4c 39 e7 cmp %r12,%rdi + 41ae13: 0f 82 9e 06 00 00 jb 41b4b7 + 41ae19: c6 44 24 08 01 movb $0x1,0x8(%rsp) + 41ae1e: e9 43 fe ff ff jmpq 41ac66 + 41ae23: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41ae28: 48 8b 35 79 f9 2a 00 mov 0x2af979(%rip),%rsi # 6ca7a8 + 41ae2f: 48 8d 7d 40 lea 0x40(%rbp),%rdi + 41ae33: 4c 89 44 24 10 mov %r8,0x10(%rsp) + 41ae38: e8 43 c0 ff ff callq 416e80 + 41ae3d: 48 85 c0 test %rax,%rax + 41ae40: 4c 8b 44 24 10 mov 0x10(%rsp),%r8 + 41ae45: 0f 84 9d 02 00 00 je 41b0e8 + 41ae4b: 48 8b 48 10 mov 0x10(%rax),%rcx + 41ae4f: 48 8d 50 20 lea 0x20(%rax),%rdx + 41ae53: 48 01 0d be 17 2b 00 add %rcx,0x2b17be(%rip) # 6cc618 + 41ae5a: 49 83 ec 20 sub $0x20,%r12 + 41ae5e: 4c 89 f7 mov %r14,%rdi + 41ae61: 48 89 18 mov %rbx,(%rax) + 41ae64: 49 83 e4 f0 and $0xfffffffffffffff0,%r12 + 41ae68: 48 89 78 08 mov %rdi,0x8(%rax) + 41ae6c: 48 89 53 58 mov %rdx,0x58(%rbx) + 41ae70: 48 89 ce mov %rcx,%rsi + 41ae73: 48 03 b3 80 08 00 00 add 0x880(%rbx),%rsi + 41ae7a: 48 83 e9 20 sub $0x20,%rcx + 41ae7e: 48 83 c9 01 or $0x1,%rcx + 41ae82: 49 83 fc 1f cmp $0x1f,%r12 + 41ae86: 4d 89 c6 mov %r8,%r14 + 41ae89: 48 89 b3 80 08 00 00 mov %rsi,0x880(%rbx) + 41ae90: 48 89 48 28 mov %rcx,0x28(%rax) + 41ae94: 49 8d 44 24 10 lea 0x10(%r12),%rax + 41ae99: 49 8d 4c 05 00 lea 0x0(%r13,%rax,1),%rcx + 41ae9e: 48 c7 41 08 01 00 00 movq $0x1,0x8(%rcx) + 41aea5: 00 + 41aea6: 0f 87 ec 01 00 00 ja 41b098 + 41aeac: 48 89 c7 mov %rax,%rdi + 41aeaf: 48 83 cf 01 or $0x1,%rdi + 41aeb3: 49 89 7d 08 mov %rdi,0x8(%r13) + 41aeb7: 48 89 01 mov %rax,(%rcx) + 41aeba: e9 98 fe ff ff jmpq 41ad57 + 41aebf: 90 nop + 41aec0: 48 89 ce mov %rcx,%rsi + 41aec3: ba 03 00 00 00 mov $0x3,%edx + 41aec8: 4c 89 44 24 10 mov %r8,0x10(%rsp) + 41aecd: 48 29 fe sub %rdi,%rsi + 41aed0: 4c 01 f7 add %r14,%rdi + 41aed3: 4c 89 4c 24 28 mov %r9,0x28(%rsp) + 41aed8: 48 89 4c 24 20 mov %rcx,0x20(%rsp) + 41aedd: e8 ee 4d 02 00 callq 43fcd0 <__mprotect> + 41aee2: 85 c0 test %eax,%eax + 41aee4: 4c 8b 44 24 10 mov 0x10(%rsp),%r8 + 41aee9: 0f 85 39 ff ff ff jne 41ae28 + 41aeef: 48 8b 4c 24 20 mov 0x20(%rsp),%rcx + 41aef4: 4c 89 f0 mov %r14,%rax + 41aef7: 4c 8b 4c 24 28 mov 0x28(%rsp),%r9 + 41aefc: 4d 89 c6 mov %r8,%r14 + 41aeff: 48 8b 53 58 mov 0x58(%rbx),%rdx + 41af03: 49 89 c0 mov %rax,%r8 + 41af06: 48 89 48 18 mov %rcx,0x18(%rax) + 41af0a: e9 17 fe ff ff jmpq 41ad26 + 41af0f: 90 nop + 41af10: 4d 8d 64 3f 07 lea 0x7(%r15,%rdi,1),%r12 + 41af15: 4d 89 fa mov %r15,%r10 + 41af18: 49 f7 da neg %r10 + 41af1b: 4d 21 d4 and %r10,%r12 + 41af1e: 4c 39 e7 cmp %r12,%rdi + 41af21: 0f 83 b7 01 00 00 jae 41b0de + 41af27: 45 31 c9 xor %r9d,%r9d + 41af2a: 31 ff xor %edi,%edi + 41af2c: 41 b8 ff ff ff ff mov $0xffffffff,%r8d + 41af32: b9 22 00 00 00 mov $0x22,%ecx + 41af37: ba 03 00 00 00 mov $0x3,%edx + 41af3c: 4c 89 e6 mov %r12,%rsi + 41af3f: e8 ac 4c 02 00 callq 43fbf0 <__mmap> + 41af44: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 41af48: 0f 84 90 01 00 00 je 41b0de + 41af4e: 48 8d 50 10 lea 0x10(%rax),%rdx + 41af52: f6 c2 0f test $0xf,%dl + 41af55: 0f 85 86 05 00 00 jne 41b4e1 + 41af5b: 4c 89 e1 mov %r12,%rcx + 41af5e: 48 83 c9 02 or $0x2,%rcx + 41af62: 48 89 48 08 mov %rcx,0x8(%rax) + 41af66: b9 01 00 00 00 mov $0x1,%ecx + 41af6b: f0 0f c1 0d 55 f8 2a lock xadd %ecx,0x2af855(%rip) # 6ca7c8 + 41af72: 00 + 41af73: 83 c1 01 add $0x1,%ecx + 41af76: 8b 05 54 f8 2a 00 mov 0x2af854(%rip),%eax # 6ca7d0 + 41af7c: 39 c1 cmp %eax,%ecx + 41af7e: 7e 0a jle 41af8a + 41af80: f0 0f b1 0d 48 f8 2a lock cmpxchg %ecx,0x2af848(%rip) # 6ca7d0 + 41af87: 00 + 41af88: 75 ec jne 41af76 + 41af8a: 4d 89 e2 mov %r12,%r10 + 41af8d: f0 4c 0f c1 15 42 f8 lock xadd %r10,0x2af842(%rip) # 6ca7d8 + 41af94: 2a 00 + 41af96: 4d 01 e2 add %r12,%r10 + 41af99: 48 8b 05 40 f8 2a 00 mov 0x2af840(%rip),%rax # 6ca7e0 + 41afa0: 49 39 c2 cmp %rax,%r10 + 41afa3: 0f 86 01 fe ff ff jbe 41adaa + 41afa9: f0 4c 0f b1 15 2e f8 lock cmpxchg %r10,0x2af82e(%rip) # 6ca7e0 + 41afb0: 2a 00 + 41afb2: 0f 84 f2 fd ff ff je 41adaa + 41afb8: eb df jmp 41af99 + 41afba: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 41afc0: f6 05 3d f8 2a 00 02 testb $0x2,0x2af83d(%rip) # 6ca804 + 41afc7: 48 8b 05 da f7 2a 00 mov 0x2af7da(%rip),%rax # 6ca7a8 + 41afce: 4d 89 c6 mov %r8,%r14 + 41afd1: 48 8d 54 05 20 lea 0x20(%rbp,%rax,1),%rdx + 41afd6: 0f 84 34 01 00 00 je 41b110 + 41afdc: 49 8d 47 ff lea -0x1(%r15),%rax + 41afe0: 49 f7 df neg %r15 + 41afe3: 4c 89 7c 24 08 mov %r15,0x8(%rsp) + 41afe8: 48 01 c2 add %rax,%rdx + 41afeb: 48 89 04 24 mov %rax,(%rsp) + 41afef: 4c 21 fa and %r15,%rdx + 41aff2: 48 85 d2 test %rdx,%rdx + 41aff5: 49 89 d7 mov %rdx,%r15 + 41aff8: 0f 8e 49 01 00 00 jle 41b147 + 41affe: 48 89 d7 mov %rdx,%rdi + 41b001: 48 89 54 24 10 mov %rdx,0x10(%rsp) + 41b006: 44 88 5c 24 20 mov %r11b,0x20(%rsp) + 41b00b: 4c 89 54 24 18 mov %r10,0x18(%rsp) + 41b010: ff 15 7a 00 2b 00 callq *0x2b007a(%rip) # 6cb090 <__morecore> + 41b016: 48 8b 54 24 10 mov 0x10(%rsp),%rdx + 41b01b: 49 89 c0 mov %rax,%r8 + 41b01e: 90 nop + 41b01f: 48 85 c0 test %rax,%rax + 41b022: 4c 8b 54 24 18 mov 0x18(%rsp),%r10 + 41b027: 44 0f b6 5c 24 20 movzbl 0x20(%rsp),%r11d + 41b02d: 0f 84 72 04 00 00 je 41b4a5 + 41b033: 48 8b 05 a6 15 2b 00 mov 0x2b15a6(%rip),%rax # 6cc5e0 <__after_morecore_hook> + 41b03a: 48 85 c0 test %rax,%rax + 41b03d: 0f 85 3d 03 00 00 jne 41b380 + 41b043: ba 01 00 00 00 mov $0x1,%edx + 41b048: 31 c0 xor %eax,%eax + 41b04a: 48 83 3d 9e f7 2a 00 cmpq $0x0,0x2af79e(%rip) # 6ca7f0 + 41b051: 00 + 41b052: 0f 84 08 03 00 00 je 41b360 + 41b058: 4c 89 fe mov %r15,%rsi + 41b05b: 48 03 35 1e 00 2b 00 add 0x2b001e(%rip),%rsi # 6cb080 + 41b062: 4d 39 c2 cmp %r8,%r10 + 41b065: 48 89 35 14 00 2b 00 mov %rsi,0x2b0014(%rip) # 6cb080 + 41b06c: 0f 85 5e 01 00 00 jne 41b1d0 + 41b072: 84 d2 test %dl,%dl + 41b074: 0f 84 56 01 00 00 je 41b1d0 + 41b07a: 4d 01 fc add %r15,%r12 + 41b07d: 48 8b 15 d4 f7 2a 00 mov 0x2af7d4(%rip),%rdx # 6ca858 + 41b084: 49 83 cc 01 or $0x1,%r12 + 41b088: 4d 89 65 08 mov %r12,0x8(%r13) + 41b08c: e9 c6 fc ff ff jmpq 41ad57 + 41b091: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 41b098: 4b c7 44 25 08 11 00 movq $0x11,0x8(%r13,%r12,1) + 41b09f: 00 00 + 41b0a1: 49 83 cc 05 or $0x5,%r12 + 41b0a5: 48 c7 01 10 00 00 00 movq $0x10,(%rcx) + 41b0ac: ba 01 00 00 00 mov $0x1,%edx + 41b0b1: 4c 89 ee mov %r13,%rsi + 41b0b4: 4d 89 65 08 mov %r12,0x8(%r13) + 41b0b8: 48 89 df mov %rbx,%rdi + 41b0bb: e8 00 e7 ff ff callq 4197c0 <_int_free> + 41b0c0: 48 8b b3 80 08 00 00 mov 0x880(%rbx),%rsi + 41b0c7: 48 8b 53 58 mov 0x58(%rbx),%rdx + 41b0cb: e9 87 fc ff ff jmpq 41ad57 + 41b0d0: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 41b0d7: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) + 41b0de: 31 d2 xor %edx,%edx + 41b0e0: e9 c5 fc ff ff jmpq 41adaa + 41b0e5: 0f 1f 00 nopl (%rax) + 41b0e8: 80 7c 24 08 00 cmpb $0x0,0x8(%rsp) + 41b0ed: 0f 85 0d 02 00 00 jne 41b300 + 41b0f3: 48 8b 44 24 18 mov 0x18(%rsp),%rax + 41b0f8: 48 39 c5 cmp %rax,%rbp + 41b0fb: 49 89 c4 mov %rax,%r12 + 41b0fe: 0f 82 f6 03 00 00 jb 41b4fa + 41b104: c6 44 24 08 01 movb $0x1,0x8(%rsp) + 41b109: e9 73 fb ff ff jmpq 41ac81 + 41b10e: 66 90 xchg %ax,%ax + 41b110: 49 8d 47 ff lea -0x1(%r15),%rax + 41b114: 4c 29 e2 sub %r12,%rdx + 41b117: 49 f7 df neg %r15 + 41b11a: 4c 89 7c 24 08 mov %r15,0x8(%rsp) + 41b11f: 48 01 c2 add %rax,%rdx + 41b122: 48 89 04 24 mov %rax,(%rsp) + 41b126: 4c 21 fa and %r15,%rdx + 41b129: 48 85 d2 test %rdx,%rdx + 41b12c: 49 89 d7 mov %rdx,%r15 + 41b12f: 0f 8f c9 fe ff ff jg 41affe + 41b135: 48 8b 04 24 mov (%rsp),%rax + 41b139: 4c 01 e0 add %r12,%rax + 41b13c: 48 01 d0 add %rdx,%rax + 41b13f: 48 23 44 24 08 and 0x8(%rsp),%rax + 41b144: 49 89 c7 mov %rax,%r15 + 41b147: 49 81 ff ff ff 0f 00 cmp $0xfffff,%r15 + 41b14e: 4c 89 7c 24 10 mov %r15,0x10(%rsp) + 41b153: 77 0f ja 41b164 + 41b155: 48 c7 44 24 10 00 00 movq $0x100000,0x10(%rsp) + 41b15c: 10 00 + 41b15e: 41 bf 00 00 10 00 mov $0x100000,%r15d + 41b164: 48 3b 6c 24 10 cmp 0x10(%rsp),%rbp + 41b169: 0f 83 7e 01 00 00 jae 41b2ed + 41b16f: 48 8b 74 24 10 mov 0x10(%rsp),%rsi + 41b174: 45 31 c9 xor %r9d,%r9d + 41b177: 41 b8 ff ff ff ff mov $0xffffffff,%r8d + 41b17d: 31 ff xor %edi,%edi + 41b17f: b9 22 00 00 00 mov $0x22,%ecx + 41b184: ba 03 00 00 00 mov $0x3,%edx + 41b189: 44 88 5c 24 20 mov %r11b,0x20(%rsp) + 41b18e: 4c 89 54 24 18 mov %r10,0x18(%rsp) + 41b193: e8 58 4a 02 00 callq 43fbf0 <__mmap> + 41b198: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 41b19c: 49 89 c0 mov %rax,%r8 + 41b19f: 0f 84 48 01 00 00 je 41b2ed + 41b1a5: 83 0d 58 f6 2a 00 02 orl $0x2,0x2af658(%rip) # 6ca804 + 41b1ac: 48 85 c0 test %rax,%rax + 41b1af: 4c 8b 54 24 18 mov 0x18(%rsp),%r10 + 41b1b4: 44 0f b6 5c 24 20 movzbl 0x20(%rsp),%r11d + 41b1ba: 0f 84 2d 01 00 00 je 41b2ed + 41b1c0: 48 8b 44 24 10 mov 0x10(%rsp),%rax + 41b1c5: 4c 01 c0 add %r8,%rax + 41b1c8: 0f 94 c2 sete %dl + 41b1cb: e9 7a fe ff ff jmpq 41b04a + 41b1d0: 8b 15 2e f6 2a 00 mov 0x2af62e(%rip),%edx # 6ca804 + 41b1d6: f6 c2 02 test $0x2,%dl + 41b1d9: 0f 85 39 01 00 00 jne 41b318 + 41b1df: 4d 39 c2 cmp %r8,%r10 + 41b1e2: 76 09 jbe 41b1ed + 41b1e4: 45 84 db test %r11b,%r11b + 41b1e7: 0f 85 b9 01 00 00 jne 41b3a6 + 41b1ed: 4d 85 e4 test %r12,%r12 + 41b1f0: 74 10 je 41b202 + 41b1f2: 4c 89 c0 mov %r8,%rax + 41b1f5: 4c 29 d0 sub %r10,%rax + 41b1f8: 48 01 c6 add %rax,%rsi + 41b1fb: 48 89 35 7e fe 2a 00 mov %rsi,0x2afe7e(%rip) # 6cb080 + 41b202: 4c 89 c2 mov %r8,%rdx + 41b205: 83 e2 0f and $0xf,%edx + 41b208: 0f 84 62 01 00 00 je 41b370 + 41b20e: b8 10 00 00 00 mov $0x10,%eax + 41b213: 48 29 d0 sub %rdx,%rax + 41b216: 49 8d 3c 00 lea (%r8,%rax,1),%rdi + 41b21a: 48 89 7c 24 10 mov %rdi,0x10(%rsp) + 41b21f: 4c 01 e0 add %r12,%rax + 41b222: 48 8b 0c 24 mov (%rsp),%rcx + 41b226: 4c 8b 54 24 08 mov 0x8(%rsp),%r10 + 41b22b: 49 8d 14 07 lea (%r15,%rax,1),%rdx + 41b22f: 4c 01 c2 add %r8,%rdx + 41b232: 48 01 d1 add %rdx,%rcx + 41b235: 48 29 d0 sub %rdx,%rax + 41b238: 49 21 ca and %rcx,%r10 + 41b23b: 49 8d 0c 02 lea (%r10,%rax,1),%rcx + 41b23f: 48 85 c9 test %rcx,%rcx + 41b242: 49 89 cf mov %rcx,%r15 + 41b245: 0f 88 41 02 00 00 js 41b48c + 41b24b: 48 89 cf mov %rcx,%rdi + 41b24e: 48 89 0c 24 mov %rcx,(%rsp) + 41b252: ff 15 38 fe 2a 00 callq *0x2afe38(%rip) # 6cb090 <__morecore> + 41b258: 48 85 c0 test %rax,%rax + 41b25b: 48 8b 0c 24 mov (%rsp),%rcx + 41b25f: 0f 84 01 02 00 00 je 41b466 + 41b265: 48 8b 15 74 13 2b 00 mov 0x2b1374(%rip),%rdx # 6cc5e0 <__after_morecore_hook> + 41b26c: 48 8b 35 0d fe 2a 00 mov 0x2afe0d(%rip),%rsi # 6cb080 + 41b273: 48 85 d2 test %rdx,%rdx + 41b276: 4c 8b 44 24 10 mov 0x10(%rsp),%r8 + 41b27b: 0f 85 bb 01 00 00 jne 41b43c + 41b281: 4c 29 c0 sub %r8,%rax + 41b284: 48 01 ce add %rcx,%rsi + 41b287: 4c 89 05 ca f5 2a 00 mov %r8,0x2af5ca(%rip) # 6ca858 + 41b28e: 49 01 c7 add %rax,%r15 + 41b291: 4c 89 c2 mov %r8,%rdx + 41b294: 49 83 cf 01 or $0x1,%r15 + 41b298: 4d 85 e4 test %r12,%r12 + 41b29b: 4d 89 78 08 mov %r15,0x8(%r8) + 41b29f: 48 89 35 da fd 2a 00 mov %rsi,0x2afdda(%rip) # 6cb080 + 41b2a6: 0f 84 ab fa ff ff je 41ad57 + 41b2ac: 49 83 ec 20 sub $0x20,%r12 + 41b2b0: 49 83 e4 f0 and $0xfffffffffffffff0,%r12 + 41b2b4: 4c 89 e0 mov %r12,%rax + 41b2b7: 48 83 c8 01 or $0x1,%rax + 41b2bb: 49 83 fc 1f cmp $0x1f,%r12 + 41b2bf: 49 89 45 08 mov %rax,0x8(%r13) + 41b2c3: 4b c7 44 25 08 11 00 movq $0x11,0x8(%r13,%r12,1) + 41b2ca: 00 00 + 41b2cc: 4b c7 44 25 18 11 00 movq $0x11,0x18(%r13,%r12,1) + 41b2d3: 00 00 + 41b2d5: 0f 86 7c fa ff ff jbe 41ad57 + 41b2db: ba 01 00 00 00 mov $0x1,%edx + 41b2e0: 4c 89 ee mov %r13,%rsi + 41b2e3: bf 00 a8 6c 00 mov $0x6ca800,%edi + 41b2e8: e8 d3 e4 ff ff callq 4197c0 <_int_free> + 41b2ed: 48 8b 35 8c fd 2a 00 mov 0x2afd8c(%rip),%rsi # 6cb080 + 41b2f4: 48 8b 15 5d f5 2a 00 mov 0x2af55d(%rip),%rdx # 6ca858 + 41b2fb: e9 57 fa ff ff jmpq 41ad57 + 41b300: 4d 89 c6 mov %r8,%r14 + 41b303: 48 8b b3 80 08 00 00 mov 0x880(%rbx),%rsi + 41b30a: 48 8b 53 58 mov 0x58(%rbx),%rdx + 41b30e: e9 44 fa ff ff jmpq 41ad57 + 41b313: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41b318: 4c 89 c1 mov %r8,%rcx + 41b31b: 83 e1 0f and $0xf,%ecx + 41b31e: 0f 85 00 02 00 00 jne 41b524 + 41b324: 45 31 ff xor %r15d,%r15d + 41b327: 48 85 c0 test %rax,%rax + 41b32a: 0f 85 51 ff ff ff jne 41b281 + 41b330: 4c 89 04 24 mov %r8,(%rsp) + 41b334: 31 ff xor %edi,%edi + 41b336: ff 15 54 fd 2a 00 callq *0x2afd54(%rip) # 6cb090 <__morecore> + 41b33c: 4c 8b 04 24 mov (%rsp),%r8 + 41b340: 4c 89 44 24 10 mov %r8,0x10(%rsp) + 41b345: 48 85 c0 test %rax,%rax + 41b348: 48 8b 35 31 fd 2a 00 mov 0x2afd31(%rip),%rsi # 6cb080 + 41b34f: 74 a3 je 41b2f4 + 41b351: 4c 8b 44 24 10 mov 0x10(%rsp),%r8 + 41b356: 31 c9 xor %ecx,%ecx + 41b358: 45 31 ff xor %r15d,%r15d + 41b35b: e9 21 ff ff ff jmpq 41b281 + 41b360: 4c 89 05 89 f4 2a 00 mov %r8,0x2af489(%rip) # 6ca7f0 + 41b367: e9 ec fc ff ff jmpq 41b058 + 41b36c: 0f 1f 40 00 nopl 0x0(%rax) + 41b370: 4c 89 44 24 10 mov %r8,0x10(%rsp) + 41b375: 31 c0 xor %eax,%eax + 41b377: e9 a3 fe ff ff jmpq 41b21f + 41b37c: 0f 1f 40 00 nopl 0x0(%rax) + 41b380: 44 88 5c 24 20 mov %r11b,0x20(%rsp) + 41b385: 4c 89 44 24 18 mov %r8,0x18(%rsp) + 41b38a: 4c 89 54 24 10 mov %r10,0x10(%rsp) + 41b38f: ff d0 callq *%rax + 41b391: 4c 8b 54 24 10 mov 0x10(%rsp),%r10 + 41b396: 4c 8b 44 24 18 mov 0x18(%rsp),%r8 + 41b39b: 44 0f b6 5c 24 20 movzbl 0x20(%rsp),%r11d + 41b3a1: e9 9d fc ff ff jmpq 41b043 + 41b3a6: 83 ca 04 or $0x4,%edx + 41b3a9: 4c 8d 6c 24 30 lea 0x30(%rsp),%r13 + 41b3ae: 48 8d 74 24 40 lea 0x40(%rsp),%rsi + 41b3b3: 89 15 4b f4 2a 00 mov %edx,0x2af44b(%rip) # 6ca804 + 41b3b9: 31 c9 xor %ecx,%ecx + 41b3bb: ba 10 00 00 00 mov $0x10,%edx + 41b3c0: 4c 89 c7 mov %r8,%rdi + 41b3c3: c6 44 24 40 00 movb $0x0,0x40(%rsp) + 41b3c8: e8 e3 6a 03 00 callq 451eb0 <_itoa_word> + 41b3cd: 4c 39 e8 cmp %r13,%rax + 41b3d0: 49 89 c4 mov %rax,%r12 + 41b3d3: 76 25 jbe 41b3fa + 41b3d5: 48 89 c2 mov %rax,%rdx + 41b3d8: 48 89 c7 mov %rax,%rdi + 41b3db: be 30 00 00 00 mov $0x30,%esi + 41b3e0: 4c 29 ea sub %r13,%rdx + 41b3e3: 4c 8d 78 ff lea -0x1(%rax),%r15 + 41b3e7: 48 29 d7 sub %rdx,%rdi + 41b3ea: e8 61 4f fe ff callq 400350 <__rela_iplt_end+0x88> + 41b3ef: 48 8d 44 24 2f lea 0x2f(%rsp),%rax + 41b3f4: 4c 29 f8 sub %r15,%rax + 41b3f7: 49 01 c4 add %rax,%r12 + 41b3fa: 48 8b 05 bf 1e 2b 00 mov 0x2b1ebf(%rip),%rax # 6cd2c0 <__libc_argv> + 41b401: ba 38 20 4a 00 mov $0x4a2038,%edx + 41b406: be a8 23 4a 00 mov $0x4a23a8,%esi + 41b40b: 4d 89 e0 mov %r12,%r8 + 41b40e: b9 48 27 4a 00 mov $0x4a2748,%ecx + 41b413: bf 02 00 00 00 mov $0x2,%edi + 41b418: 48 8b 00 mov (%rax),%rax + 41b41b: 48 85 c0 test %rax,%rax + 41b41e: 48 0f 45 d0 cmovne %rax,%rdx + 41b422: 31 c0 xor %eax,%eax + 41b424: e8 97 61 ff ff callq 4115c0 <__libc_message> + 41b429: 48 8b 35 50 fc 2a 00 mov 0x2afc50(%rip),%rsi # 6cb080 + 41b430: 48 8b 15 21 f4 2a 00 mov 0x2af421(%rip),%rdx # 6ca858 + 41b437: e9 1b f9 ff ff jmpq 41ad57 + 41b43c: 48 89 44 24 10 mov %rax,0x10(%rsp) + 41b441: 4c 89 44 24 08 mov %r8,0x8(%rsp) + 41b446: 48 89 0c 24 mov %rcx,(%rsp) + 41b44a: ff d2 callq *%rdx + 41b44c: 48 8b 35 2d fc 2a 00 mov 0x2afc2d(%rip),%rsi # 6cb080 + 41b453: 48 8b 0c 24 mov (%rsp),%rcx + 41b457: 4c 8b 44 24 08 mov 0x8(%rsp),%r8 + 41b45c: 48 8b 44 24 10 mov 0x10(%rsp),%rax + 41b461: e9 1b fe ff ff jmpq 41b281 + 41b466: 31 ff xor %edi,%edi + 41b468: ff 15 22 fc 2a 00 callq *0x2afc22(%rip) # 6cb090 <__morecore> + 41b46e: e9 d2 fe ff ff jmpq 41b345 + 41b473: b9 a8 2e 4a 00 mov $0x4a2ea8,%ecx + 41b478: ba 5d 09 00 00 mov $0x95d,%edx + 41b47d: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 41b482: bf 08 27 4a 00 mov $0x4a2708,%edi + 41b487: e8 94 b9 ff ff callq 416e20 <__malloc_assert> + 41b48c: b9 a8 2e 4a 00 mov $0x4a2ea8,%ecx + 41b491: ba 39 0a 00 00 mov $0xa39,%edx + 41b496: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 41b49b: bf 32 21 4a 00 mov $0x4a2132,%edi + 41b4a0: e8 7b b9 ff ff callq 416e20 <__malloc_assert> + 41b4a5: f6 05 58 f3 2a 00 02 testb $0x2,0x2af358(%rip) # 6ca804 + 41b4ac: 0f 84 83 fc ff ff je 41b135 + 41b4b2: e9 90 fc ff ff jmpq 41b147 + 41b4b7: 45 31 c9 xor %r9d,%r9d + 41b4ba: 41 83 c8 ff or $0xffffffff,%r8d + 41b4be: 31 ff xor %edi,%edi + 41b4c0: b9 22 00 00 00 mov $0x22,%ecx + 41b4c5: ba 03 00 00 00 mov $0x3,%edx + 41b4ca: 4c 89 e6 mov %r12,%rsi + 41b4cd: e8 1e 47 02 00 callq 43fbf0 <__mmap> + 41b4d2: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 41b4d6: 0f 85 72 fa ff ff jne 41af4e + 41b4dc: e9 38 f9 ff ff jmpq 41ae19 + 41b4e1: b9 a8 2e 4a 00 mov $0x4a2ea8,%ecx + 41b4e6: ba 24 09 00 00 mov $0x924,%edx + 41b4eb: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 41b4f0: bf 20 26 4a 00 mov $0x4a2620,%edi + 41b4f5: e8 26 b9 ff ff callq 416e20 <__malloc_assert> + 41b4fa: 45 31 c9 xor %r9d,%r9d + 41b4fd: 41 83 c8 ff or $0xffffffff,%r8d + 41b501: 31 ff xor %edi,%edi + 41b503: b9 22 00 00 00 mov $0x22,%ecx + 41b508: ba 03 00 00 00 mov $0x3,%edx + 41b50d: 48 89 c6 mov %rax,%rsi + 41b510: e8 db 46 02 00 callq 43fbf0 <__mmap> + 41b515: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 41b519: 0f 85 2f fa ff ff jne 41af4e + 41b51f: e9 e0 fb ff ff jmpq 41b104 + 41b524: b9 a8 2e 4a 00 mov $0x4a2ea8,%ecx + 41b529: ba 59 0a 00 00 mov $0xa59,%edx + 41b52e: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 41b533: bf 70 27 4a 00 mov $0x4a2770,%edi + 41b538: e8 e3 b8 ff ff callq 416e20 <__malloc_assert> + 41b53d: 0f 1f 00 nopl (%rax) + +000000000041b540 <_int_malloc>: + 41b540: 48 83 fe bf cmp $0xffffffffffffffbf,%rsi + 41b544: 0f 87 63 08 00 00 ja 41bdad <_int_malloc+0x86d> + 41b54a: 48 89 f0 mov %rsi,%rax + 41b54d: 41 57 push %r15 + 41b54f: 41 56 push %r14 + 41b551: 48 83 c0 17 add $0x17,%rax + 41b555: 41 55 push %r13 + 41b557: 41 54 push %r12 + 41b559: 55 push %rbp + 41b55a: 53 push %rbx + 41b55b: 48 89 c5 mov %rax,%rbp + 41b55e: 48 83 e5 f0 and $0xfffffffffffffff0,%rbp + 41b562: 48 89 fb mov %rdi,%rbx + 41b565: 48 81 ec 98 00 00 00 sub $0x98,%rsp + 41b56c: 48 83 f8 20 cmp $0x20,%rax + 41b570: b8 20 00 00 00 mov $0x20,%eax + 41b575: 48 0f 42 e8 cmovb %rax,%rbp + 41b579: 48 85 ff test %rdi,%rdi + 41b57c: 48 89 74 24 08 mov %rsi,0x8(%rsp) + 41b581: 0f 84 3a 08 00 00 je 41bdc1 <_int_malloc+0x881> + 41b587: 48 3b 2d aa 10 2b 00 cmp 0x2b10aa(%rip),%rbp # 6cc638 + 41b58e: 77 70 ja 41b600 <_int_malloc+0xc0> + 41b590: 89 ef mov %ebp,%edi + 41b592: c1 ef 04 shr $0x4,%edi + 41b595: 8d 47 fe lea -0x2(%rdi),%eax + 41b598: 48 8b 4c c3 08 mov 0x8(%rbx,%rax,8),%rcx + 41b59d: 48 8d 34 c3 lea (%rbx,%rax,8),%rsi + 41b5a1: 48 89 c7 mov %rax,%rdi + 41b5a4: 48 8d 56 08 lea 0x8(%rsi),%rdx + 41b5a8: 48 85 c9 test %rcx,%rcx + 41b5ab: 74 53 je 41b600 <_int_malloc+0xc0> + 41b5ad: 4c 8b 41 10 mov 0x10(%rcx),%r8 + 41b5b1: 48 89 c8 mov %rcx,%rax + 41b5b4: 64 83 3c 25 18 00 00 cmpl $0x0,%fs:0x18 + 41b5bb: 00 00 + 41b5bd: 74 01 je 41b5c0 <_int_malloc+0x80> + 41b5bf: f0 4c 0f b1 46 08 lock cmpxchg %r8,0x8(%rsi) + 41b5c5: 48 39 c8 cmp %rcx,%rax + 41b5c8: 49 89 c7 mov %rax,%r15 + 41b5cb: 75 2e jne 41b5fb <_int_malloc+0xbb> + 41b5cd: e9 64 02 00 00 jmpq 41b836 <_int_malloc+0x2f6> + 41b5d2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 41b5d8: 49 8b 4f 10 mov 0x10(%r15),%rcx + 41b5dc: 4c 89 f8 mov %r15,%rax + 41b5df: 64 83 3c 25 18 00 00 cmpl $0x0,%fs:0x18 + 41b5e6: 00 00 + 41b5e8: 74 01 je 41b5eb <_int_malloc+0xab> + 41b5ea: f0 48 0f b1 0a lock cmpxchg %rcx,(%rdx) + 41b5ef: 4c 39 f8 cmp %r15,%rax + 41b5f2: 0f 84 3e 02 00 00 je 41b836 <_int_malloc+0x2f6> + 41b5f8: 49 89 c7 mov %rax,%r15 + 41b5fb: 4d 85 ff test %r15,%r15 + 41b5fe: 75 d8 jne 41b5d8 <_int_malloc+0x98> + 41b600: 48 81 fd ff 03 00 00 cmp $0x3ff,%rbp + 41b607: 77 5a ja 41b663 <_int_malloc+0x123> + 41b609: 89 e8 mov %ebp,%eax + 41b60b: c1 e8 04 shr $0x4,%eax + 41b60e: 89 04 24 mov %eax,(%rsp) + 41b611: 8d 44 00 fe lea -0x2(%rax,%rax,1),%eax + 41b615: 48 8d 44 c3 60 lea 0x60(%rbx,%rax,8),%rax + 41b61a: 48 8d 48 08 lea 0x8(%rax),%rcx + 41b61e: 4c 8b 79 08 mov 0x8(%rcx),%r15 + 41b622: 48 83 e8 08 sub $0x8,%rax + 41b626: 4c 39 f8 cmp %r15,%rax + 41b629: 74 70 je 41b69b <_int_malloc+0x15b> + 41b62b: 4d 85 ff test %r15,%r15 + 41b62e: 74 63 je 41b693 <_int_malloc+0x153> + 41b630: 49 8b 57 18 mov 0x18(%r15),%rdx + 41b634: 4c 3b 7a 10 cmp 0x10(%rdx),%r15 + 41b638: 0f 85 13 09 00 00 jne 41bf51 <_int_malloc+0xa11> + 41b63e: 49 83 4c 2f 08 01 orq $0x1,0x8(%r15,%rbp,1) + 41b644: 48 81 fb 00 a8 6c 00 cmp $0x6ca800,%rbx + 41b64b: 48 89 51 08 mov %rdx,0x8(%rcx) + 41b64f: 48 89 42 10 mov %rax,0x10(%rdx) + 41b653: 0f 84 ef 01 00 00 je 41b848 <_int_malloc+0x308> + 41b659: 49 83 4f 08 04 orq $0x4,0x8(%r15) + 41b65e: e9 e5 01 00 00 jmpq 41b848 <_int_malloc+0x308> + 41b663: 49 89 ec mov %rbp,%r12 + 41b666: 49 c1 ec 06 shr $0x6,%r12 + 41b66a: 49 83 fc 30 cmp $0x30,%r12 + 41b66e: 0f 86 0c 07 00 00 jbe 41bd80 <_int_malloc+0x840> + 41b674: 49 89 ec mov %rbp,%r12 + 41b677: 49 c1 ec 09 shr $0x9,%r12 + 41b67b: 49 83 fc 14 cmp $0x14,%r12 + 41b67f: 0f 87 7b 07 00 00 ja 41be00 <_int_malloc+0x8c0> + 41b685: 41 8d 44 24 5b lea 0x5b(%r12),%eax + 41b68a: 89 04 24 mov %eax,(%rsp) + 41b68d: f6 43 04 01 testb $0x1,0x4(%rbx) + 41b691: 75 08 jne 41b69b <_int_malloc+0x15b> + 41b693: 48 89 df mov %rbx,%rdi + 41b696: e8 95 c7 ff ff callq 417e30 + 41b69b: 48 89 e9 mov %rbp,%rcx + 41b69e: 48 89 e8 mov %rbp,%rax + 41b6a1: 48 89 ef mov %rbp,%rdi + 41b6a4: 48 c1 e9 0c shr $0xc,%rcx + 41b6a8: 48 c1 e8 06 shr $0x6,%rax + 41b6ac: 48 c1 ef 09 shr $0x9,%rdi + 41b6b0: 48 89 4c 24 48 mov %rcx,0x48(%rsp) + 41b6b5: 83 c1 6e add $0x6e,%ecx + 41b6b8: 48 89 44 24 30 mov %rax,0x30(%rsp) + 41b6bd: 89 4c 24 54 mov %ecx,0x54(%rsp) + 41b6c1: 48 89 e9 mov %rbp,%rcx + 41b6c4: 83 c0 30 add $0x30,%eax + 41b6c7: 48 c1 e9 0f shr $0xf,%rcx + 41b6cb: 48 89 7c 24 40 mov %rdi,0x40(%rsp) + 41b6d0: 89 44 24 3c mov %eax,0x3c(%rsp) + 41b6d4: 83 c7 5b add $0x5b,%edi + 41b6d7: 48 89 4c 24 58 mov %rcx,0x58(%rsp) + 41b6dc: 89 e8 mov %ebp,%eax + 41b6de: 83 c1 77 add $0x77,%ecx + 41b6e1: c1 e8 04 shr $0x4,%eax + 41b6e4: 89 7c 24 50 mov %edi,0x50(%rsp) + 41b6e8: 89 4c 24 68 mov %ecx,0x68(%rsp) + 41b6ec: 48 8d 7c 24 70 lea 0x70(%rsp),%rdi + 41b6f1: 48 89 e9 mov %rbp,%rcx + 41b6f4: 48 c1 e9 12 shr $0x12,%rcx + 41b6f8: 89 44 24 38 mov %eax,0x38(%rsp) + 41b6fc: b8 01 00 00 00 mov $0x1,%eax + 41b701: 48 89 4c 24 60 mov %rcx,0x60(%rsp) + 41b706: 48 29 f8 sub %rdi,%rax + 41b709: 83 c1 7c add $0x7c,%ecx + 41b70c: 4c 8d 63 58 lea 0x58(%rbx),%r12 + 41b710: 89 4c 24 6c mov %ecx,0x6c(%rsp) + 41b714: 48 89 44 24 28 mov %rax,0x28(%rsp) + 41b719: 41 bf 10 27 00 00 mov $0x2710,%r15d + 41b71f: eb 4e jmp 41b76f <_int_malloc+0x22f> + 41b721: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 41b728: 89 f1 mov %esi,%ecx + 41b72a: c1 e9 04 shr $0x4,%ecx + 41b72d: 8d 44 09 fe lea -0x2(%rcx,%rcx,1),%eax + 41b731: 48 98 cltq + 41b733: 48 8d 44 c3 60 lea 0x60(%rbx,%rax,8),%rax + 41b738: 48 8b 78 08 mov 0x8(%rax),%rdi + 41b73c: 4c 8d 40 f8 lea -0x8(%rax),%r8 + 41b740: 89 c8 mov %ecx,%eax + 41b742: ba 01 00 00 00 mov $0x1,%edx + 41b747: c1 f8 05 sar $0x5,%eax + 41b74a: d3 e2 shl %cl,%edx + 41b74c: 48 98 cltq + 41b74e: 09 94 83 58 08 00 00 or %edx,0x858(%rbx,%rax,4) + 41b755: 41 83 ef 01 sub $0x1,%r15d + 41b759: 4d 89 45 18 mov %r8,0x18(%r13) + 41b75d: 49 89 7d 10 mov %rdi,0x10(%r13) + 41b761: 4c 89 6f 18 mov %r13,0x18(%rdi) + 41b765: 4d 89 68 10 mov %r13,0x10(%r8) + 41b769: 0f 84 94 03 00 00 je 41bb03 <_int_malloc+0x5c3> + 41b76f: 4c 8b 6b 70 mov 0x70(%rbx),%r13 + 41b773: 4d 39 e5 cmp %r12,%r13 + 41b776: 0f 84 87 03 00 00 je 41bb03 <_int_malloc+0x5c3> + 41b77c: 49 8b 75 08 mov 0x8(%r13),%rsi + 41b780: 4d 8b 75 18 mov 0x18(%r13),%r14 + 41b784: 48 83 fe 10 cmp $0x10,%rsi + 41b788: 0f 86 52 01 00 00 jbe 41b8e0 <_int_malloc+0x3a0> + 41b78e: 48 3b b3 80 08 00 00 cmp 0x880(%rbx),%rsi + 41b795: 0f 87 45 01 00 00 ja 41b8e0 <_int_malloc+0x3a0> + 41b79b: 48 83 e6 f8 and $0xfffffffffffffff8,%rsi + 41b79f: 48 81 fd ff 03 00 00 cmp $0x3ff,%rbp + 41b7a6: 77 09 ja 41b7b1 <_int_malloc+0x271> + 41b7a8: 4d 39 e6 cmp %r12,%r14 + 41b7ab: 0f 84 8f 01 00 00 je 41b940 <_int_malloc+0x400> + 41b7b1: 48 39 f5 cmp %rsi,%rbp + 41b7b4: 4c 89 73 70 mov %r14,0x70(%rbx) + 41b7b8: 4d 89 66 10 mov %r12,0x10(%r14) + 41b7bc: 0f 84 a6 04 00 00 je 41bc68 <_int_malloc+0x728> + 41b7c2: 48 81 fe ff 03 00 00 cmp $0x3ff,%rsi + 41b7c9: 0f 86 59 ff ff ff jbe 41b728 <_int_malloc+0x1e8> + 41b7cf: 48 89 f0 mov %rsi,%rax + 41b7d2: 48 c1 e8 06 shr $0x6,%rax + 41b7d6: 48 83 f8 30 cmp $0x30,%rax + 41b7da: 0f 87 90 00 00 00 ja 41b870 <_int_malloc+0x330> + 41b7e0: 8d 48 30 lea 0x30(%rax),%ecx + 41b7e3: 8d 44 00 5e lea 0x5e(%rax,%rax,1),%eax + 41b7e7: 48 98 cltq + 41b7e9: 48 8d 44 c3 60 lea 0x60(%rbx,%rax,8),%rax + 41b7ee: 48 8d 78 f8 lea -0x8(%rax),%rdi + 41b7f2: 48 8d 50 08 lea 0x8(%rax),%rdx + 41b7f6: 48 8b 40 08 mov 0x8(%rax),%rax + 41b7fa: 48 39 c7 cmp %rax,%rdi + 41b7fd: 0f 84 e5 01 00 00 je 41b9e8 <_int_malloc+0x4a8> + 41b803: 4c 8b 42 08 mov 0x8(%rdx),%r8 + 41b807: 48 83 ce 01 or $0x1,%rsi + 41b80b: 49 8b 50 08 mov 0x8(%r8),%rdx + 41b80f: f6 c2 04 test $0x4,%dl + 41b812: 0f 85 f1 09 00 00 jne 41c209 <_int_malloc+0xcc9> + 41b818: 48 39 d6 cmp %rdx,%rsi + 41b81b: 73 73 jae 41b890 <_int_malloc+0x350> + 41b81d: 48 8b 50 28 mov 0x28(%rax),%rdx + 41b821: 49 89 45 20 mov %rax,0x20(%r13) + 41b825: 49 89 55 28 mov %rdx,0x28(%r13) + 41b829: 4c 89 6a 20 mov %r13,0x20(%rdx) + 41b82d: 4c 89 68 28 mov %r13,0x28(%rax) + 41b831: e9 0a ff ff ff jmpq 41b740 <_int_malloc+0x200> + 41b836: 41 8b 47 08 mov 0x8(%r15),%eax + 41b83a: c1 e8 04 shr $0x4,%eax + 41b83d: 83 e8 02 sub $0x2,%eax + 41b840: 39 c7 cmp %eax,%edi + 41b842: 0f 85 26 06 00 00 jne 41be6e <_int_malloc+0x92e> + 41b848: 8b 05 e6 0d 2b 00 mov 0x2b0de6(%rip),%eax # 6cc634 + 41b84e: 49 8d 4f 10 lea 0x10(%r15),%rcx + 41b852: 85 c0 test %eax,%eax + 41b854: 0f 85 71 01 00 00 jne 41b9cb <_int_malloc+0x48b> + 41b85a: 48 81 c4 98 00 00 00 add $0x98,%rsp + 41b861: 48 89 c8 mov %rcx,%rax + 41b864: 5b pop %rbx + 41b865: 5d pop %rbp + 41b866: 41 5c pop %r12 + 41b868: 41 5d pop %r13 + 41b86a: 41 5e pop %r14 + 41b86c: 41 5f pop %r15 + 41b86e: c3 retq + 41b86f: 90 nop + 41b870: 48 89 f0 mov %rsi,%rax + 41b873: 48 c1 e8 09 shr $0x9,%rax + 41b877: 48 83 f8 14 cmp $0x14,%rax + 41b87b: 0f 87 97 00 00 00 ja 41b918 <_int_malloc+0x3d8> + 41b881: 8d 48 5b lea 0x5b(%rax),%ecx + 41b884: 8d 84 00 b4 00 00 00 lea 0xb4(%rax,%rax,1),%eax + 41b88b: e9 57 ff ff ff jmpq 41b7e7 <_int_malloc+0x2a7> + 41b890: 48 8b 50 08 mov 0x8(%rax),%rdx + 41b894: f6 c2 04 test $0x4,%dl + 41b897: 74 18 je 41b8b1 <_int_malloc+0x371> + 41b899: e9 84 09 00 00 jmpq 41c222 <_int_malloc+0xce2> + 41b89e: 66 90 xchg %ax,%ax + 41b8a0: 48 8b 40 20 mov 0x20(%rax),%rax + 41b8a4: 48 8b 50 08 mov 0x8(%rax),%rdx + 41b8a8: f6 c2 04 test $0x4,%dl + 41b8ab: 0f 85 87 06 00 00 jne 41bf38 <_int_malloc+0x9f8> + 41b8b1: 48 39 d6 cmp %rdx,%rsi + 41b8b4: 72 ea jb 41b8a0 <_int_malloc+0x360> + 41b8b6: 0f 84 64 01 00 00 je 41ba20 <_int_malloc+0x4e0> + 41b8bc: 48 8b 50 28 mov 0x28(%rax),%rdx + 41b8c0: 49 89 45 20 mov %rax,0x20(%r13) + 41b8c4: 48 89 c7 mov %rax,%rdi + 41b8c7: 49 89 55 28 mov %rdx,0x28(%r13) + 41b8cb: 4c 89 68 28 mov %r13,0x28(%rax) + 41b8cf: 49 8b 55 28 mov 0x28(%r13),%rdx + 41b8d3: 4c 89 6a 20 mov %r13,0x20(%rdx) + 41b8d7: 4c 8b 47 18 mov 0x18(%rdi),%r8 + 41b8db: e9 60 fe ff ff jmpq 41b740 <_int_malloc+0x200> + 41b8e0: 44 8b 0d 89 ee 2a 00 mov 0x2aee89(%rip),%r9d # 6ca770 + 41b8e7: 83 4b 04 04 orl $0x4,0x4(%rbx) + 41b8eb: 44 89 c8 mov %r9d,%eax + 41b8ee: 83 e0 05 and $0x5,%eax + 41b8f1: 83 f8 05 cmp $0x5,%eax + 41b8f4: 0f 84 93 04 00 00 je 41bd8d <_int_malloc+0x84d> + 41b8fa: 41 f6 c1 01 test $0x1,%r9b + 41b8fe: 0f 85 2c 01 00 00 jne 41ba30 <_int_malloc+0x4f0> + 41b904: 41 83 e1 02 and $0x2,%r9d + 41b908: 0f 84 8d fe ff ff je 41b79b <_int_malloc+0x25b> + 41b90e: e9 84 05 00 00 jmpq 41be97 <_int_malloc+0x957> + 41b913: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41b918: 48 89 f0 mov %rsi,%rax + 41b91b: 48 c1 e8 0c shr $0xc,%rax + 41b91f: 48 83 f8 0a cmp $0xa,%rax + 41b923: 0f 87 d7 00 00 00 ja 41ba00 <_int_malloc+0x4c0> + 41b929: 8d 48 6e lea 0x6e(%rax),%ecx + 41b92c: 8d 84 00 da 00 00 00 lea 0xda(%rax,%rax,1),%eax + 41b933: e9 af fe ff ff jmpq 41b7e7 <_int_malloc+0x2a7> + 41b938: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 41b93f: 00 + 41b940: 4c 3b 6b 60 cmp 0x60(%rbx),%r13 + 41b944: 0f 85 67 fe ff ff jne 41b7b1 <_int_malloc+0x271> + 41b94a: 48 8d 45 20 lea 0x20(%rbp),%rax + 41b94e: 48 39 c6 cmp %rax,%rsi + 41b951: 0f 86 5a fe ff ff jbe 41b7b1 <_int_malloc+0x271> + 41b957: 48 89 f2 mov %rsi,%rdx + 41b95a: 49 8d 44 2d 00 lea 0x0(%r13,%rbp,1),%rax + 41b95f: 48 29 ea sub %rbp,%rdx + 41b962: 48 81 fa ff 03 00 00 cmp $0x3ff,%rdx + 41b969: 48 89 43 68 mov %rax,0x68(%rbx) + 41b96d: 48 89 43 70 mov %rax,0x70(%rbx) + 41b971: 48 89 43 60 mov %rax,0x60(%rbx) + 41b975: 4c 89 60 10 mov %r12,0x10(%rax) + 41b979: 4c 89 60 18 mov %r12,0x18(%rax) + 41b97d: 76 10 jbe 41b98f <_int_malloc+0x44f> + 41b97f: 48 c7 40 20 00 00 00 movq $0x0,0x20(%rax) + 41b986: 00 + 41b987: 48 c7 40 28 00 00 00 movq $0x0,0x28(%rax) + 41b98e: 00 + 41b98f: 31 c9 xor %ecx,%ecx + 41b991: 48 81 fb 00 a8 6c 00 cmp $0x6ca800,%rbx + 41b998: 0f 95 c1 setne %cl + 41b99b: 48 83 cd 01 or $0x1,%rbp + 41b99f: 48 c1 e1 02 shl $0x2,%rcx + 41b9a3: 48 09 e9 or %rbp,%rcx + 41b9a6: 49 89 4d 08 mov %rcx,0x8(%r13) + 41b9aa: 48 89 d1 mov %rdx,%rcx + 41b9ad: 48 83 c9 01 or $0x1,%rcx + 41b9b1: 48 89 48 08 mov %rcx,0x8(%rax) + 41b9b5: 48 89 14 10 mov %rdx,(%rax,%rdx,1) + 41b9b9: 49 8d 4d 10 lea 0x10(%r13),%rcx + 41b9bd: 8b 05 71 0c 2b 00 mov 0x2b0c71(%rip),%eax # 6cc634 + 41b9c3: 85 c0 test %eax,%eax + 41b9c5: 0f 84 8f fe ff ff je 41b85a <_int_malloc+0x31a> + 41b9cb: 48 8b 54 24 08 mov 0x8(%rsp),%rdx + 41b9d0: 34 ff xor $0xff,%al + 41b9d2: 48 89 cf mov %rcx,%rdi + 41b9d5: 89 c6 mov %eax,%esi + 41b9d7: e8 74 49 fe ff callq 400350 <__rela_iplt_end+0x88> + 41b9dc: 48 89 c1 mov %rax,%rcx + 41b9df: e9 76 fe ff ff jmpq 41b85a <_int_malloc+0x31a> + 41b9e4: 0f 1f 40 00 nopl 0x0(%rax) + 41b9e8: 4d 89 6d 28 mov %r13,0x28(%r13) + 41b9ec: 4d 89 6d 20 mov %r13,0x20(%r13) + 41b9f0: 49 89 f8 mov %rdi,%r8 + 41b9f3: e9 48 fd ff ff jmpq 41b740 <_int_malloc+0x200> + 41b9f8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 41b9ff: 00 + 41ba00: 48 89 f0 mov %rsi,%rax + 41ba03: 48 c1 e8 0f shr $0xf,%rax + 41ba07: 48 83 f8 04 cmp $0x4,%rax + 41ba0b: 0f 87 d2 00 00 00 ja 41bae3 <_int_malloc+0x5a3> + 41ba11: 8d 48 77 lea 0x77(%rax),%ecx + 41ba14: 8d 84 00 ec 00 00 00 lea 0xec(%rax,%rax,1),%eax + 41ba1b: e9 c7 fd ff ff jmpq 41b7e7 <_int_malloc+0x2a7> + 41ba20: 48 8b 78 10 mov 0x10(%rax),%rdi + 41ba24: e9 ae fe ff ff jmpq 41b8d7 <_int_malloc+0x397> + 41ba29: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 41ba30: 48 8d b4 24 80 00 00 lea 0x80(%rsp),%rsi + 41ba37: 00 + 41ba38: 49 8d 7d 10 lea 0x10(%r13),%rdi + 41ba3c: 31 c9 xor %ecx,%ecx + 41ba3e: ba 10 00 00 00 mov $0x10,%edx + 41ba43: 44 89 4c 24 10 mov %r9d,0x10(%rsp) + 41ba48: c6 84 24 80 00 00 00 movb $0x0,0x80(%rsp) + 41ba4f: 00 + 41ba50: e8 5b 64 03 00 callq 451eb0 <_itoa_word> + 41ba55: 49 89 c0 mov %rax,%r8 + 41ba58: 48 8d 44 24 70 lea 0x70(%rsp),%rax + 41ba5d: 44 8b 4c 24 10 mov 0x10(%rsp),%r9d + 41ba62: 49 39 c0 cmp %rax,%r8 + 41ba65: 76 46 jbe 41baad <_int_malloc+0x56d> + 41ba67: 48 8b 44 24 28 mov 0x28(%rsp),%rax + 41ba6c: 49 8d 48 ff lea -0x1(%r8),%rcx + 41ba70: 4c 89 c7 mov %r8,%rdi + 41ba73: be 30 00 00 00 mov $0x30,%esi + 41ba78: 44 89 4c 24 24 mov %r9d,0x24(%rsp) + 41ba7d: 4c 89 44 24 10 mov %r8,0x10(%rsp) + 41ba82: 48 89 4c 24 18 mov %rcx,0x18(%rsp) + 41ba87: 48 8d 14 08 lea (%rax,%rcx,1),%rdx + 41ba8b: 48 29 d7 sub %rdx,%rdi + 41ba8e: e8 bd 48 fe ff callq 400350 <__rela_iplt_end+0x88> + 41ba93: 48 8b 4c 24 18 mov 0x18(%rsp),%rcx + 41ba98: 48 8d 44 24 6f lea 0x6f(%rsp),%rax + 41ba9d: 4c 8b 44 24 10 mov 0x10(%rsp),%r8 + 41baa2: 44 8b 4c 24 24 mov 0x24(%rsp),%r9d + 41baa7: 48 29 c8 sub %rcx,%rax + 41baaa: 49 01 c0 add %rax,%r8 + 41baad: 48 8b 05 0c 18 2b 00 mov 0x2b180c(%rip),%rax # 6cd2c0 <__libc_argv> + 41bab4: 44 89 cf mov %r9d,%edi + 41bab7: ba 38 20 4a 00 mov $0x4a2038,%edx + 41babc: be a8 23 4a 00 mov $0x4a23a8,%esi + 41bac1: b9 42 21 4a 00 mov $0x4a2142,%ecx + 41bac6: 48 8b 00 mov (%rax),%rax + 41bac9: 48 85 c0 test %rax,%rax + 41bacc: 48 0f 45 d0 cmovne %rax,%rdx + 41bad0: 83 e7 02 and $0x2,%edi + 41bad3: 31 c0 xor %eax,%eax + 41bad5: e8 e6 5a ff ff callq 4115c0 <__libc_message> + 41bada: 49 8b 75 08 mov 0x8(%r13),%rsi + 41bade: e9 b8 fc ff ff jmpq 41b79b <_int_malloc+0x25b> + 41bae3: 48 89 f0 mov %rsi,%rax + 41bae6: 48 c1 e8 12 shr $0x12,%rax + 41baea: 48 83 f8 02 cmp $0x2,%rax + 41baee: 0f 87 9f 01 00 00 ja 41bc93 <_int_malloc+0x753> + 41baf4: 8d 48 7c lea 0x7c(%rax),%ecx + 41baf7: 8d 84 00 f6 00 00 00 lea 0xf6(%rax,%rax,1),%eax + 41bafe: e9 e4 fc ff ff jmpq 41b7e7 <_int_malloc+0x2a7> + 41bb03: 48 81 fd ff 03 00 00 cmp $0x3ff,%rbp + 41bb0a: 0f 87 92 01 00 00 ja 41bca2 <_int_malloc+0x762> + 41bb10: 8b 04 24 mov (%rsp),%eax + 41bb13: 8d 48 01 lea 0x1(%rax),%ecx + 41bb16: 01 c0 add %eax,%eax + 41bb18: 48 8d 54 c3 58 lea 0x58(%rbx,%rax,8),%rdx + 41bb1d: 89 cf mov %ecx,%edi + 41bb1f: c1 ef 05 shr $0x5,%edi + 41bb22: 89 f8 mov %edi,%eax + 41bb24: 8b b4 83 58 08 00 00 mov 0x858(%rbx,%rax,4),%esi + 41bb2b: b8 01 00 00 00 mov $0x1,%eax + 41bb30: d3 e0 shl %cl,%eax + 41bb32: 39 f0 cmp %esi,%eax + 41bb34: 77 40 ja 41bb76 <_int_malloc+0x636> + 41bb36: 85 c0 test %eax,%eax + 41bb38: 75 12 jne 41bb4c <_int_malloc+0x60c> + 41bb3a: eb 3a jmp 41bb76 <_int_malloc+0x636> + 41bb3c: 0f 1f 40 00 nopl 0x0(%rax) + 41bb40: 48 83 c2 10 add $0x10,%rdx + 41bb44: 01 c0 add %eax,%eax + 41bb46: 0f 84 dc 05 00 00 je 41c128 <_int_malloc+0xbe8> + 41bb4c: 85 f0 test %esi,%eax + 41bb4e: 74 f0 je 41bb40 <_int_malloc+0x600> + 41bb50: 4c 8b 7a 18 mov 0x18(%rdx),%r15 + 41bb54: 4c 39 fa cmp %r15,%rdx + 41bb57: 0f 85 4f 03 00 00 jne 41beac <_int_malloc+0x96c> + 41bb5d: 89 c1 mov %eax,%ecx + 41bb5f: 01 c0 add %eax,%eax + 41bb61: 48 83 c2 10 add $0x10,%rdx + 41bb65: f7 d1 not %ecx + 41bb67: 21 ce and %ecx,%esi + 41bb69: 89 f9 mov %edi,%ecx + 41bb6b: 39 f0 cmp %esi,%eax + 41bb6d: 89 b4 8b 58 08 00 00 mov %esi,0x858(%rbx,%rcx,4) + 41bb74: 76 c0 jbe 41bb36 <_int_malloc+0x5f6> + 41bb76: 8d 47 01 lea 0x1(%rdi),%eax + 41bb79: 83 f8 03 cmp $0x3,%eax + 41bb7c: 77 3d ja 41bbbb <_int_malloc+0x67b> + 41bb7e: 89 c2 mov %eax,%edx + 41bb80: 8b b4 93 58 08 00 00 mov 0x858(%rbx,%rdx,4),%esi + 41bb87: 85 f6 test %esi,%esi + 41bb89: 0f 85 9c 02 00 00 jne 41be2b <_int_malloc+0x8eb> + 41bb8f: 8d 47 02 lea 0x2(%rdi),%eax + 41bb92: 83 f8 04 cmp $0x4,%eax + 41bb95: 74 24 je 41bbbb <_int_malloc+0x67b> + 41bb97: 89 c2 mov %eax,%edx + 41bb99: 8b b4 93 58 08 00 00 mov 0x858(%rbx,%rdx,4),%esi + 41bba0: 85 f6 test %esi,%esi + 41bba2: 0f 85 83 02 00 00 jne 41be2b <_int_malloc+0x8eb> + 41bba8: 83 ff 01 cmp $0x1,%edi + 41bbab: 74 0e je 41bbbb <_int_malloc+0x67b> + 41bbad: 8b b3 64 08 00 00 mov 0x864(%rbx),%esi + 41bbb3: 85 f6 test %esi,%esi + 41bbb5: 0f 85 e5 02 00 00 jne 41bea0 <_int_malloc+0x960> + 41bbbb: 48 8b 53 58 mov 0x58(%rbx),%rdx + 41bbbf: 48 8d 4d 20 lea 0x20(%rbp),%rcx + 41bbc3: 48 8b 42 08 mov 0x8(%rdx),%rax + 41bbc7: 48 83 e0 f8 and $0xfffffffffffffff8,%rax + 41bbcb: 48 39 c8 cmp %rcx,%rax + 41bbce: 0f 83 0c 05 00 00 jae 41c0e0 <_int_malloc+0xba0> + 41bbd4: f6 43 04 01 testb $0x1,0x4(%rbx) + 41bbd8: 0f 85 e2 04 00 00 jne 41c0c0 <_int_malloc+0xb80> + 41bbde: 48 89 df mov %rbx,%rdi + 41bbe1: e8 4a c2 ff ff callq 417e30 + 41bbe6: 8b 44 24 38 mov 0x38(%rsp),%eax + 41bbea: 48 81 fd ff 03 00 00 cmp $0x3ff,%rbp + 41bbf1: 89 04 24 mov %eax,(%rsp) + 41bbf4: 0f 86 1f fb ff ff jbe 41b719 <_int_malloc+0x1d9> + 41bbfa: 48 83 7c 24 30 30 cmpq $0x30,0x30(%rsp) + 41bc00: 8b 44 24 3c mov 0x3c(%rsp),%eax + 41bc04: 89 04 24 mov %eax,(%rsp) + 41bc07: 0f 86 0c fb ff ff jbe 41b719 <_int_malloc+0x1d9> + 41bc0d: 48 83 7c 24 40 14 cmpq $0x14,0x40(%rsp) + 41bc13: 8b 44 24 50 mov 0x50(%rsp),%eax + 41bc17: 89 04 24 mov %eax,(%rsp) + 41bc1a: 0f 86 f9 fa ff ff jbe 41b719 <_int_malloc+0x1d9> + 41bc20: 48 83 7c 24 48 0a cmpq $0xa,0x48(%rsp) + 41bc26: 8b 44 24 54 mov 0x54(%rsp),%eax + 41bc2a: 89 04 24 mov %eax,(%rsp) + 41bc2d: 0f 86 e6 fa ff ff jbe 41b719 <_int_malloc+0x1d9> + 41bc33: 48 83 7c 24 58 04 cmpq $0x4,0x58(%rsp) + 41bc39: 8b 44 24 68 mov 0x68(%rsp),%eax + 41bc3d: 89 04 24 mov %eax,(%rsp) + 41bc40: 0f 86 d3 fa ff ff jbe 41b719 <_int_malloc+0x1d9> + 41bc46: 48 83 7c 24 60 02 cmpq $0x2,0x60(%rsp) + 41bc4c: 41 be 7e 00 00 00 mov $0x7e,%r14d + 41bc52: 44 0f 46 74 24 6c cmovbe 0x6c(%rsp),%r14d + 41bc58: 44 89 34 24 mov %r14d,(%rsp) + 41bc5c: e9 b8 fa ff ff jmpq 41b719 <_int_malloc+0x1d9> + 41bc61: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 41bc68: 49 83 4c 2d 08 01 orq $0x1,0x8(%r13,%rbp,1) + 41bc6e: 48 81 fb 00 a8 6c 00 cmp $0x6ca800,%rbx + 41bc75: 74 05 je 41bc7c <_int_malloc+0x73c> + 41bc77: 49 83 4d 08 04 orq $0x4,0x8(%r13) + 41bc7c: 8b 05 b2 09 2b 00 mov 0x2b09b2(%rip),%eax # 6cc634 + 41bc82: 49 8d 4d 10 lea 0x10(%r13),%rcx + 41bc86: 85 c0 test %eax,%eax + 41bc88: 0f 84 cc fb ff ff je 41b85a <_int_malloc+0x31a> + 41bc8e: e9 38 fd ff ff jmpq 41b9cb <_int_malloc+0x48b> + 41bc93: b8 fa 00 00 00 mov $0xfa,%eax + 41bc98: b9 7e 00 00 00 mov $0x7e,%ecx + 41bc9d: e9 45 fb ff ff jmpq 41b7e7 <_int_malloc+0x2a7> + 41bca2: 8b 04 24 mov (%rsp),%eax + 41bca5: 8d 44 00 fe lea -0x2(%rax,%rax,1),%eax + 41bca9: 48 8d 44 c3 60 lea 0x60(%rbx,%rax,8),%rax + 41bcae: 48 8b 50 08 mov 0x8(%rax),%rdx + 41bcb2: 48 8d 48 08 lea 0x8(%rax),%rcx + 41bcb6: 48 83 e8 08 sub $0x8,%rax + 41bcba: 48 39 c2 cmp %rax,%rdx + 41bcbd: 0f 84 4d fe ff ff je 41bb10 <_int_malloc+0x5d0> + 41bcc3: 48 3b 6a 08 cmp 0x8(%rdx),%rbp + 41bcc7: 0f 87 43 fe ff ff ja 41bb10 <_int_malloc+0x5d0> + 41bccd: 4c 8b 7a 28 mov 0x28(%rdx),%r15 + 41bcd1: eb 04 jmp 41bcd7 <_int_malloc+0x797> + 41bcd3: 4d 8b 7f 28 mov 0x28(%r15),%r15 + 41bcd7: 49 8b 57 08 mov 0x8(%r15),%rdx + 41bcdb: 49 89 d6 mov %rdx,%r14 + 41bcde: 49 83 e6 f8 and $0xfffffffffffffff8,%r14 + 41bce2: 4c 39 f5 cmp %r14,%rbp + 41bce5: 77 ec ja 41bcd3 <_int_malloc+0x793> + 41bce7: 4c 3b 79 08 cmp 0x8(%rcx),%r15 + 41bceb: 0f 84 da 04 00 00 je 41c1cb <_int_malloc+0xc8b> + 41bcf1: 49 8b 4f 10 mov 0x10(%r15),%rcx + 41bcf5: 4c 89 f0 mov %r14,%rax + 41bcf8: 48 3b 51 08 cmp 0x8(%rcx),%rdx + 41bcfc: 75 0a jne 41bd08 <_int_malloc+0x7c8> + 41bcfe: 48 89 d0 mov %rdx,%rax + 41bd01: 49 89 cf mov %rcx,%r15 + 41bd04: 48 83 e0 f8 and $0xfffffffffffffff8,%rax + 41bd08: 4c 89 f7 mov %r14,%rdi + 41bd0b: 48 29 ef sub %rbp,%rdi + 41bd0e: 49 39 04 07 cmp %rax,(%r15,%rax,1) + 41bd12: 48 89 3c 24 mov %rdi,(%rsp) + 41bd16: 0f 85 26 06 00 00 jne 41c342 <_int_malloc+0xe02> + 41bd1c: 4d 8b 6f 10 mov 0x10(%r15),%r13 + 41bd20: 49 8b 47 18 mov 0x18(%r15),%rax + 41bd24: 4d 3b 7d 18 cmp 0x18(%r13),%r15 + 41bd28: 0f 85 c0 04 00 00 jne 41c1ee <_int_malloc+0xcae> + 41bd2e: 4c 3b 78 10 cmp 0x10(%rax),%r15 + 41bd32: 0f 85 b6 04 00 00 jne 41c1ee <_int_malloc+0xcae> + 41bd38: 49 81 7f 08 ff 03 00 cmpq $0x3ff,0x8(%r15) + 41bd3f: 00 + 41bd40: 49 89 45 18 mov %rax,0x18(%r13) + 41bd44: 4c 89 68 10 mov %r13,0x10(%rax) + 41bd48: 76 0d jbe 41bd57 <_int_malloc+0x817> + 41bd4a: 49 8b 47 20 mov 0x20(%r15),%rax + 41bd4e: 48 85 c0 test %rax,%rax + 41bd51: 0f 85 06 06 00 00 jne 41c35d <_int_malloc+0xe1d> + 41bd57: 48 83 3c 24 1f cmpq $0x1f,(%rsp) + 41bd5c: 0f 87 38 04 00 00 ja 41c19a <_int_malloc+0xc5a> + 41bd62: 4b 83 4c 37 08 01 orq $0x1,0x8(%r15,%r14,1) + 41bd68: 48 81 fb 00 a8 6c 00 cmp $0x6ca800,%rbx + 41bd6f: 0f 85 e4 f8 ff ff jne 41b659 <_int_malloc+0x119> + 41bd75: e9 ce fa ff ff jmpq 41b848 <_int_malloc+0x308> + 41bd7a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 41bd80: 41 8d 44 24 30 lea 0x30(%r12),%eax + 41bd85: 89 04 24 mov %eax,(%rsp) + 41bd88: e9 00 f9 ff ff jmpq 41b68d <_int_malloc+0x14d> + 41bd8d: 44 89 cf mov %r9d,%edi + 41bd90: be 3c ca 4b 00 mov $0x4bca3c,%esi + 41bd95: ba 42 21 4a 00 mov $0x4a2142,%edx + 41bd9a: 83 e7 02 and $0x2,%edi + 41bd9d: 31 c0 xor %eax,%eax + 41bd9f: e8 1c 58 ff ff callq 4115c0 <__libc_message> + 41bda4: 49 8b 75 08 mov 0x8(%r13),%rsi + 41bda8: e9 ee f9 ff ff jmpq 41b79b <_int_malloc+0x25b> + 41bdad: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 41bdb4: 31 c9 xor %ecx,%ecx + 41bdb6: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) + 41bdbd: 48 89 c8 mov %rcx,%rax + 41bdc0: c3 retq + 41bdc1: 31 f6 xor %esi,%esi + 41bdc3: 48 89 ef mov %rbp,%rdi + 41bdc6: e8 65 ee ff ff callq 41ac30 + 41bdcb: 48 85 c0 test %rax,%rax + 41bdce: 0f 84 86 00 00 00 je 41be5a <_int_malloc+0x91a> + 41bdd4: 8b 15 5a 08 2b 00 mov 0x2b085a(%rip),%edx # 6cc634 + 41bdda: 48 89 c1 mov %rax,%rcx + 41bddd: 85 d2 test %edx,%edx + 41bddf: 0f 84 75 fa ff ff je 41b85a <_int_malloc+0x31a> + 41bde5: 89 d6 mov %edx,%esi + 41bde7: 48 8b 54 24 08 mov 0x8(%rsp),%rdx + 41bdec: 48 89 c7 mov %rax,%rdi + 41bdef: 40 80 f6 ff xor $0xff,%sil + 41bdf3: e8 58 45 fe ff callq 400350 <__rela_iplt_end+0x88> + 41bdf8: 48 89 c1 mov %rax,%rcx + 41bdfb: e9 5a fa ff ff jmpq 41b85a <_int_malloc+0x31a> + 41be00: 49 89 ec mov %rbp,%r12 + 41be03: 49 c1 ec 0c shr $0xc,%r12 + 41be07: 49 83 fc 0a cmp $0xa,%r12 + 41be0b: 76 54 jbe 41be61 <_int_malloc+0x921> + 41be0d: 49 89 ec mov %rbp,%r12 + 41be10: 49 c1 ec 0f shr $0xf,%r12 + 41be14: 49 83 fc 04 cmp $0x4,%r12 + 41be18: 0f 87 43 02 00 00 ja 41c061 <_int_malloc+0xb21> + 41be1e: 41 8d 44 24 77 lea 0x77(%r12),%eax + 41be23: 89 04 24 mov %eax,(%rsp) + 41be26: e9 62 f8 ff ff jmpq 41b68d <_int_malloc+0x14d> + 41be2b: 89 c2 mov %eax,%edx + 41be2d: 89 c7 mov %eax,%edi + 41be2f: c1 e2 06 shl $0x6,%edx + 41be32: 83 ea 02 sub $0x2,%edx + 41be35: 89 d0 mov %edx,%eax + 41be37: 48 8d 54 c3 58 lea 0x58(%rbx,%rax,8),%rdx + 41be3c: b8 01 00 00 00 mov $0x1,%eax + 41be41: e9 06 fd ff ff jmpq 41bb4c <_int_malloc+0x60c> + 41be46: 89 ef mov %ebp,%edi + 41be48: 4c 89 e2 mov %r12,%rdx + 41be4b: be 3c ca 4b 00 mov $0x4bca3c,%esi + 41be50: 83 e7 02 and $0x2,%edi + 41be53: 31 c0 xor %eax,%eax + 41be55: e8 66 57 ff ff callq 4115c0 <__libc_message> + 41be5a: 31 c9 xor %ecx,%ecx + 41be5c: e9 f9 f9 ff ff jmpq 41b85a <_int_malloc+0x31a> + 41be61: 41 8d 44 24 6e lea 0x6e(%r12),%eax + 41be66: 89 04 24 mov %eax,(%rsp) + 41be69: e9 1f f8 ff ff jmpq 41b68d <_int_malloc+0x14d> + 41be6e: 41 bc b0 27 4a 00 mov $0x4a27b0,%r12d + 41be74: 8b 2d f6 e8 2a 00 mov 0x2ae8f6(%rip),%ebp # 6ca770 + 41be7a: 83 4b 04 04 orl $0x4,0x4(%rbx) + 41be7e: 89 e8 mov %ebp,%eax + 41be80: 83 e0 05 and $0x5,%eax + 41be83: 83 f8 05 cmp $0x5,%eax + 41be86: 74 be je 41be46 <_int_malloc+0x906> + 41be88: 40 f6 c5 01 test $0x1,%bpl + 41be8c: 0f 85 ca 00 00 00 jne 41bf5c <_int_malloc+0xa1c> + 41be92: 83 e5 02 and $0x2,%ebp + 41be95: 74 c3 je 41be5a <_int_malloc+0x91a> + 41be97: e8 64 1d ff ff callq 40dc00 + 41be9c: 0f 1f 40 00 nopl 0x0(%rax) + 41bea0: ba be 00 00 00 mov $0xbe,%edx + 41bea5: bf 03 00 00 00 mov $0x3,%edi + 41beaa: eb 89 jmp 41be35 <_int_malloc+0x8f5> + 41beac: 49 8b 47 08 mov 0x8(%r15),%rax + 41beb0: 48 83 e0 f8 and $0xfffffffffffffff8,%rax + 41beb4: 48 39 c5 cmp %rax,%rbp + 41beb7: 0f 87 34 04 00 00 ja 41c2f1 <_int_malloc+0xdb1> + 41bebd: 4d 8d 2c 07 lea (%r15,%rax,1),%r13 + 41bec1: 48 89 c7 mov %rax,%rdi + 41bec4: 48 29 ef sub %rbp,%rdi + 41bec7: 49 3b 45 00 cmp 0x0(%r13),%rax + 41becb: 48 89 3c 24 mov %rdi,(%rsp) + 41becf: 0f 85 6c 02 00 00 jne 41c141 <_int_malloc+0xc01> + 41bed5: 49 8b 47 10 mov 0x10(%r15),%rax + 41bed9: 49 8b 57 18 mov 0x18(%r15),%rdx + 41bedd: 4c 3b 78 18 cmp 0x18(%rax),%r15 + 41bee1: 0f 85 9a 01 00 00 jne 41c081 <_int_malloc+0xb41> + 41bee7: 4c 8b 72 10 mov 0x10(%rdx),%r14 + 41beeb: 4d 39 f7 cmp %r14,%r15 + 41beee: 0f 85 8d 01 00 00 jne 41c081 <_int_malloc+0xb41> + 41bef4: 49 81 7e 08 ff 03 00 cmpq $0x3ff,0x8(%r14) + 41befb: 00 + 41befc: 48 89 50 18 mov %rdx,0x18(%rax) + 41bf00: 48 89 42 10 mov %rax,0x10(%rdx) + 41bf04: 76 0d jbe 41bf13 <_int_malloc+0x9d3> + 41bf06: 49 8b 56 20 mov 0x20(%r14),%rdx + 41bf0a: 48 85 d2 test %rdx,%rdx + 41bf0d: 0f 85 f7 03 00 00 jne 41c30a <_int_malloc+0xdca> + 41bf13: 48 83 3c 24 1f cmpq $0x1f,(%rsp) + 41bf18: 0f 87 c4 00 00 00 ja 41bfe2 <_int_malloc+0xaa2> + 41bf1e: 49 83 4d 08 01 orq $0x1,0x8(%r13) + 41bf23: 48 81 fb 00 a8 6c 00 cmp $0x6ca800,%rbx + 41bf2a: 0f 85 29 f7 ff ff jne 41b659 <_int_malloc+0x119> + 41bf30: e9 13 f9 ff ff jmpq 41b848 <_int_malloc+0x308> + 41bf35: 0f 1f 00 nopl (%rax) + 41bf38: b9 b8 2e 4a 00 mov $0x4a2eb8,%ecx + 41bf3d: ba ef 0d 00 00 mov $0xdef,%edx + 41bf42: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 41bf47: bf 80 28 4a 00 mov $0x4a2880,%edi + 41bf4c: e8 cf ae ff ff callq 416e20 <__malloc_assert> + 41bf51: 41 bc d8 27 4a 00 mov $0x4a27d8,%r12d + 41bf57: e9 18 ff ff ff jmpq 41be74 <_int_malloc+0x934> + 41bf5c: 4c 8d 6c 24 70 lea 0x70(%rsp),%r13 + 41bf61: 48 8d b4 24 80 00 00 lea 0x80(%rsp),%rsi + 41bf68: 00 + 41bf69: 49 8d 7f 10 lea 0x10(%r15),%rdi + 41bf6d: 31 c9 xor %ecx,%ecx + 41bf6f: ba 10 00 00 00 mov $0x10,%edx + 41bf74: c6 84 24 80 00 00 00 movb $0x0,0x80(%rsp) + 41bf7b: 00 + 41bf7c: e8 2f 5f 03 00 callq 451eb0 <_itoa_word> + 41bf81: 4c 39 e8 cmp %r13,%rax + 41bf84: 48 89 c3 mov %rax,%rbx + 41bf87: 76 25 jbe 41bfae <_int_malloc+0xa6e> + 41bf89: 48 89 c2 mov %rax,%rdx + 41bf8c: 48 89 c7 mov %rax,%rdi + 41bf8f: be 30 00 00 00 mov $0x30,%esi + 41bf94: 4c 29 ea sub %r13,%rdx + 41bf97: 4c 8d 70 ff lea -0x1(%rax),%r14 + 41bf9b: 48 29 d7 sub %rdx,%rdi + 41bf9e: e8 ad 43 fe ff callq 400350 <__rela_iplt_end+0x88> + 41bfa3: 48 8d 44 24 6f lea 0x6f(%rsp),%rax + 41bfa8: 4c 29 f0 sub %r14,%rax + 41bfab: 48 01 c3 add %rax,%rbx + 41bfae: 48 8b 05 0b 13 2b 00 mov 0x2b130b(%rip),%rax # 6cd2c0 <__libc_argv> + 41bfb5: ba 38 20 4a 00 mov $0x4a2038,%edx + 41bfba: 89 ef mov %ebp,%edi + 41bfbc: 4c 89 e1 mov %r12,%rcx + 41bfbf: 49 89 d8 mov %rbx,%r8 + 41bfc2: be a8 23 4a 00 mov $0x4a23a8,%esi + 41bfc7: 48 8b 00 mov (%rax),%rax + 41bfca: 48 85 c0 test %rax,%rax + 41bfcd: 48 0f 45 d0 cmovne %rax,%rdx + 41bfd1: 83 e7 02 and $0x2,%edi + 41bfd4: 31 c0 xor %eax,%eax + 41bfd6: e8 e5 55 ff ff callq 4115c0 <__libc_message> + 41bfdb: 31 c9 xor %ecx,%ecx + 41bfdd: e9 78 f8 ff ff jmpq 41b85a <_int_malloc+0x31a> + 41bfe2: 48 8b 53 68 mov 0x68(%rbx),%rdx + 41bfe6: 4c 39 62 18 cmp %r12,0x18(%rdx) + 41bfea: 0f 85 f3 01 00 00 jne 41c1e3 <_int_malloc+0xca3> + 41bff0: 49 8d 04 2f lea (%r15,%rbp,1),%rax + 41bff4: 48 81 fd ff 03 00 00 cmp $0x3ff,%rbp + 41bffb: 4c 89 60 18 mov %r12,0x18(%rax) + 41bfff: 48 89 50 10 mov %rdx,0x10(%rax) + 41c003: 48 89 43 68 mov %rax,0x68(%rbx) + 41c007: 48 89 42 18 mov %rax,0x18(%rdx) + 41c00b: 77 04 ja 41c011 <_int_malloc+0xad1> + 41c00d: 48 89 43 60 mov %rax,0x60(%rbx) + 41c011: 48 81 3c 24 ff 03 00 cmpq $0x3ff,(%rsp) + 41c018: 00 + 41c019: 76 10 jbe 41c02b <_int_malloc+0xaeb> + 41c01b: 48 c7 40 20 00 00 00 movq $0x0,0x20(%rax) + 41c022: 00 + 41c023: 48 c7 40 28 00 00 00 movq $0x0,0x28(%rax) + 41c02a: 00 + 41c02b: 31 d2 xor %edx,%edx + 41c02d: 48 81 fb 00 a8 6c 00 cmp $0x6ca800,%rbx + 41c034: 48 8b 3c 24 mov (%rsp),%rdi + 41c038: 0f 95 c2 setne %dl + 41c03b: 48 83 cd 01 or $0x1,%rbp + 41c03f: 48 c1 e2 02 shl $0x2,%rdx + 41c043: 48 09 ea or %rbp,%rdx + 41c046: 49 89 57 08 mov %rdx,0x8(%r15) + 41c04a: 48 89 fa mov %rdi,%rdx + 41c04d: 48 83 ca 01 or $0x1,%rdx + 41c051: 48 89 50 08 mov %rdx,0x8(%rax) + 41c055: 48 89 fa mov %rdi,%rdx + 41c058: 48 89 3c 10 mov %rdi,(%rax,%rdx,1) + 41c05c: e9 e7 f7 ff ff jmpq 41b848 <_int_malloc+0x308> + 41c061: 48 89 e8 mov %rbp,%rax + 41c064: 48 c1 e8 12 shr $0x12,%rax + 41c068: 44 8d 60 7c lea 0x7c(%rax),%r12d + 41c06c: 48 83 f8 02 cmp $0x2,%rax + 41c070: b8 7e 00 00 00 mov $0x7e,%eax + 41c075: 41 0f 46 c4 cmovbe %r12d,%eax + 41c079: 89 04 24 mov %eax,(%rsp) + 41c07c: e9 0c f6 ff ff jmpq 41b68d <_int_malloc+0x14d> + 41c081: 8b 15 e9 e6 2a 00 mov 0x2ae6e9(%rip),%edx # 6ca770 + 41c087: 83 4b 04 04 orl $0x4,0x4(%rbx) + 41c08b: 89 d0 mov %edx,%eax + 41c08d: 83 e0 05 and $0x5,%eax + 41c090: 83 f8 05 cmp $0x5,%eax + 41c093: 0f 84 3d 02 00 00 je 41c2d6 <_int_malloc+0xd96> + 41c099: 41 89 d6 mov %edx,%r14d + 41c09c: 41 83 e6 02 and $0x2,%r14d + 41c0a0: 83 e2 01 and $0x1,%edx + 41c0a3: 0f 85 92 01 00 00 jne 41c23b <_int_malloc+0xcfb> + 41c0a9: 45 85 f6 test %r14d,%r14d + 41c0ac: 0f 84 61 fe ff ff je 41bf13 <_int_malloc+0x9d3> + 41c0b2: e9 e0 fd ff ff jmpq 41be97 <_int_malloc+0x957> + 41c0b7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 41c0be: 00 00 + 41c0c0: 48 89 de mov %rbx,%rsi + 41c0c3: 48 89 ef mov %rbp,%rdi + 41c0c6: e8 65 eb ff ff callq 41ac30 + 41c0cb: 48 85 c0 test %rax,%rax + 41c0ce: 0f 85 00 fd ff ff jne 41bdd4 <_int_malloc+0x894> + 41c0d4: 31 c9 xor %ecx,%ecx + 41c0d6: e9 7f f7 ff ff jmpq 41b85a <_int_malloc+0x31a> + 41c0db: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41c0e0: 48 29 e8 sub %rbp,%rax + 41c0e3: 31 c9 xor %ecx,%ecx + 41c0e5: 48 81 fb 00 a8 6c 00 cmp $0x6ca800,%rbx + 41c0ec: 0f 95 c1 setne %cl + 41c0ef: 48 8d 34 2a lea (%rdx,%rbp,1),%rsi + 41c0f3: 48 83 cd 01 or $0x1,%rbp + 41c0f7: 48 c1 e1 02 shl $0x2,%rcx + 41c0fb: 48 83 c8 01 or $0x1,%rax + 41c0ff: 48 09 e9 or %rbp,%rcx + 41c102: 48 89 73 58 mov %rsi,0x58(%rbx) + 41c106: 48 89 4a 08 mov %rcx,0x8(%rdx) + 41c10a: 48 89 46 08 mov %rax,0x8(%rsi) + 41c10e: 48 8d 4a 10 lea 0x10(%rdx),%rcx + 41c112: 8b 05 1c 05 2b 00 mov 0x2b051c(%rip),%eax # 6cc634 + 41c118: 85 c0 test %eax,%eax + 41c11a: 0f 84 3a f7 ff ff je 41b85a <_int_malloc+0x31a> + 41c120: e9 a6 f8 ff ff jmpq 41b9cb <_int_malloc+0x48b> + 41c125: 0f 1f 00 nopl (%rax) + 41c128: b9 b8 2e 4a 00 mov $0x4a2eb8,%ecx + 41c12d: ba 77 0e 00 00 mov $0xe77,%edx + 41c132: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 41c137: bf 5e 21 4a 00 mov $0x4a215e,%edi + 41c13c: e8 df ac ff ff callq 416e20 <__malloc_assert> + 41c141: 44 8b 0d 28 e6 2a 00 mov 0x2ae628(%rip),%r9d # 6ca770 + 41c148: 83 4b 04 04 orl $0x4,0x4(%rbx) + 41c14c: 44 89 c8 mov %r9d,%eax + 41c14f: 83 e0 05 and $0x5,%eax + 41c152: 83 f8 05 cmp $0x5,%eax + 41c155: 0f 84 e2 02 00 00 je 41c43d <_int_malloc+0xefd> + 41c15b: 41 f6 c1 01 test $0x1,%r9b + 41c15f: 0f 85 30 02 00 00 jne 41c395 <_int_malloc+0xe55> + 41c165: 41 f6 c1 02 test $0x2,%r9b + 41c169: 0f 85 28 fd ff ff jne 41be97 <_int_malloc+0x957> + 41c16f: 49 8b 47 10 mov 0x10(%r15),%rax + 41c173: 49 8b 57 18 mov 0x18(%r15),%rdx + 41c177: 4c 3b 78 18 cmp 0x18(%rax),%r15 + 41c17b: 0f 85 92 fd ff ff jne 41bf13 <_int_malloc+0x9d3> + 41c181: 4c 8b 72 10 mov 0x10(%rdx),%r14 + 41c185: 4d 39 f7 cmp %r14,%r15 + 41c188: 0f 84 66 fd ff ff je 41bef4 <_int_malloc+0x9b4> + 41c18e: 44 89 ca mov %r9d,%edx + 41c191: 83 4b 04 04 orl $0x4,0x4(%rbx) + 41c195: e9 ff fe ff ff jmpq 41c099 <_int_malloc+0xb59> + 41c19a: 48 8b 53 68 mov 0x68(%rbx),%rdx + 41c19e: 49 8d 04 2f lea (%r15,%rbp,1),%rax + 41c1a2: 4c 39 62 18 cmp %r12,0x18(%rdx) + 41c1a6: 75 30 jne 41c1d8 <_int_malloc+0xc98> + 41c1a8: 48 81 3c 24 ff 03 00 cmpq $0x3ff,(%rsp) + 41c1af: 00 + 41c1b0: 4c 89 60 18 mov %r12,0x18(%rax) + 41c1b4: 48 89 50 10 mov %rdx,0x10(%rax) + 41c1b8: 48 89 43 68 mov %rax,0x68(%rbx) + 41c1bc: 48 89 42 18 mov %rax,0x18(%rdx) + 41c1c0: 0f 86 65 fe ff ff jbe 41c02b <_int_malloc+0xaeb> + 41c1c6: e9 50 fe ff ff jmpq 41c01b <_int_malloc+0xadb> + 41c1cb: 49 8b 47 08 mov 0x8(%r15),%rax + 41c1cf: 48 83 e0 f8 and $0xfffffffffffffff8,%rax + 41c1d3: e9 30 fb ff ff jmpq 41bd08 <_int_malloc+0x7c8> + 41c1d8: 41 bc 08 28 4a 00 mov $0x4a2808,%r12d + 41c1de: e9 91 fc ff ff jmpq 41be74 <_int_malloc+0x934> + 41c1e3: 41 bc 30 28 4a 00 mov $0x4a2830,%r12d + 41c1e9: e9 86 fc ff ff jmpq 41be74 <_int_malloc+0x934> + 41c1ee: 8b 3d 7c e5 2a 00 mov 0x2ae57c(%rip),%edi # 6ca770 + 41c1f4: 48 89 d9 mov %rbx,%rcx + 41c1f7: 4c 89 fa mov %r15,%rdx + 41c1fa: be 95 20 4a 00 mov $0x4a2095,%esi + 41c1ff: e8 ac b0 ff ff callq 4172b0 + 41c204: e9 4e fb ff ff jmpq 41bd57 <_int_malloc+0x817> + 41c209: b9 b8 2e 4a 00 mov $0x4a2eb8,%ecx + 41c20e: ba df 0d 00 00 mov $0xddf,%edx + 41c213: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 41c218: bf 58 28 4a 00 mov $0x4a2858,%edi + 41c21d: e8 fe ab ff ff callq 416e20 <__malloc_assert> + 41c222: b9 b8 2e 4a 00 mov $0x4a2eb8,%ecx + 41c227: ba eb 0d 00 00 mov $0xdeb,%edx + 41c22c: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 41c231: bf 80 28 4a 00 mov $0x4a2880,%edi + 41c236: e8 e5 ab ff ff callq 416e20 <__malloc_assert> + 41c23b: 4c 8d 5c 24 70 lea 0x70(%rsp),%r11 + 41c240: 48 8d b4 24 80 00 00 lea 0x80(%rsp),%rsi + 41c247: 00 + 41c248: 31 c9 xor %ecx,%ecx + 41c24a: ba 10 00 00 00 mov $0x10,%edx + 41c24f: 4c 89 ff mov %r15,%rdi + 41c252: c6 84 24 80 00 00 00 movb $0x0,0x80(%rsp) + 41c259: 00 + 41c25a: 4c 89 5c 24 10 mov %r11,0x10(%rsp) + 41c25f: e8 4c 5c 03 00 callq 451eb0 <_itoa_word> + 41c264: 4c 8b 5c 24 10 mov 0x10(%rsp),%r11 + 41c269: 49 89 c0 mov %rax,%r8 + 41c26c: 4c 39 d8 cmp %r11,%rax + 41c26f: 76 36 jbe 41c2a7 <_int_malloc+0xd67> + 41c271: 4c 89 c2 mov %r8,%rdx + 41c274: 4c 89 c7 mov %r8,%rdi + 41c277: 48 8d 40 ff lea -0x1(%rax),%rax + 41c27b: 4c 29 da sub %r11,%rdx + 41c27e: be 30 00 00 00 mov $0x30,%esi + 41c283: 4c 89 44 24 18 mov %r8,0x18(%rsp) + 41c288: 48 29 d7 sub %rdx,%rdi + 41c28b: 48 89 44 24 10 mov %rax,0x10(%rsp) + 41c290: e8 bb 40 fe ff callq 400350 <__rela_iplt_end+0x88> + 41c295: 48 8d 44 24 6f lea 0x6f(%rsp),%rax + 41c29a: 48 2b 44 24 10 sub 0x10(%rsp),%rax + 41c29f: 4c 8b 44 24 18 mov 0x18(%rsp),%r8 + 41c2a4: 49 01 c0 add %rax,%r8 + 41c2a7: 48 8b 05 12 10 2b 00 mov 0x2b1012(%rip),%rax # 6cd2c0 <__libc_argv> + 41c2ae: ba 38 20 4a 00 mov $0x4a2038,%edx + 41c2b3: b9 95 20 4a 00 mov $0x4a2095,%ecx + 41c2b8: be a8 23 4a 00 mov $0x4a23a8,%esi + 41c2bd: 44 89 f7 mov %r14d,%edi + 41c2c0: 48 8b 00 mov (%rax),%rax + 41c2c3: 48 85 c0 test %rax,%rax + 41c2c6: 48 0f 45 d0 cmovne %rax,%rdx + 41c2ca: 31 c0 xor %eax,%eax + 41c2cc: e8 ef 52 ff ff callq 4115c0 <__libc_message> + 41c2d1: e9 3d fc ff ff jmpq 41bf13 <_int_malloc+0x9d3> + 41c2d6: 89 d7 mov %edx,%edi + 41c2d8: be 3c ca 4b 00 mov $0x4bca3c,%esi + 41c2dd: ba 95 20 4a 00 mov $0x4a2095,%edx + 41c2e2: 83 e7 02 and $0x2,%edi + 41c2e5: 31 c0 xor %eax,%eax + 41c2e7: e8 d4 52 ff ff callq 4115c0 <__libc_message> + 41c2ec: e9 22 fc ff ff jmpq 41bf13 <_int_malloc+0x9d3> + 41c2f1: b9 b8 2e 4a 00 mov $0x4a2eb8,%ecx + 41c2f6: ba 8a 0e 00 00 mov $0xe8a,%edx + 41c2fb: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 41c300: bf a8 28 4a 00 mov $0x4a28a8,%edi + 41c305: e8 16 ab ff ff callq 416e20 <__malloc_assert> + 41c30a: 4c 39 72 28 cmp %r14,0x28(%rdx) + 41c30e: 0f 85 6b 01 00 00 jne 41c47f <_int_malloc+0xf3f> + 41c314: 49 8b 4e 28 mov 0x28(%r14),%rcx + 41c318: 4c 39 71 20 cmp %r14,0x20(%rcx) + 41c31c: 0f 85 5d 01 00 00 jne 41c47f <_int_malloc+0xf3f> + 41c322: 48 83 78 20 00 cmpq $0x0,0x20(%rax) + 41c327: 0f 84 2c 01 00 00 je 41c459 <_int_malloc+0xf19> + 41c32d: 49 8b 46 28 mov 0x28(%r14),%rax + 41c331: 48 89 42 28 mov %rax,0x28(%rdx) + 41c335: 49 8b 46 28 mov 0x28(%r14),%rax + 41c339: 48 89 50 20 mov %rdx,0x20(%rax) + 41c33d: e9 d1 fb ff ff jmpq 41bf13 <_int_malloc+0x9d3> + 41c342: 8b 3d 28 e4 2a 00 mov 0x2ae428(%rip),%edi # 6ca770 + 41c348: 48 89 d9 mov %rbx,%rcx + 41c34b: 4c 89 fa mov %r15,%rdx + 41c34e: be 78 20 4a 00 mov $0x4a2078,%esi + 41c353: e8 58 af ff ff callq 4172b0 + 41c358: e9 bf f9 ff ff jmpq 41bd1c <_int_malloc+0x7dc> + 41c35d: 4c 3b 78 28 cmp 0x28(%rax),%r15 + 41c361: 0f 85 74 01 00 00 jne 41c4db <_int_malloc+0xf9b> + 41c367: 49 8b 57 28 mov 0x28(%r15),%rdx + 41c36b: 4c 3b 7a 20 cmp 0x20(%rdx),%r15 + 41c36f: 0f 85 66 01 00 00 jne 41c4db <_int_malloc+0xf9b> + 41c375: 49 83 7d 20 00 cmpq $0x0,0x20(%r13) + 41c37a: 0f 84 35 01 00 00 je 41c4b5 <_int_malloc+0xf75> + 41c380: 49 8b 57 28 mov 0x28(%r15),%rdx + 41c384: 48 89 50 28 mov %rdx,0x28(%rax) + 41c388: 49 8b 57 28 mov 0x28(%r15),%rdx + 41c38c: 48 89 42 20 mov %rax,0x20(%rdx) + 41c390: e9 c2 f9 ff ff jmpq 41bd57 <_int_malloc+0x817> + 41c395: 4c 8d 74 24 70 lea 0x70(%rsp),%r14 + 41c39a: 48 8d b4 24 80 00 00 lea 0x80(%rsp),%rsi + 41c3a1: 00 + 41c3a2: 31 c9 xor %ecx,%ecx + 41c3a4: ba 10 00 00 00 mov $0x10,%edx + 41c3a9: 4c 89 ff mov %r15,%rdi + 41c3ac: 44 89 4c 24 10 mov %r9d,0x10(%rsp) + 41c3b1: c6 84 24 80 00 00 00 movb $0x0,0x80(%rsp) + 41c3b8: 00 + 41c3b9: e8 f2 5a 03 00 callq 451eb0 <_itoa_word> + 41c3be: 4c 39 f0 cmp %r14,%rax + 41c3c1: 49 89 c0 mov %rax,%r8 + 41c3c4: 44 8b 4c 24 10 mov 0x10(%rsp),%r9d + 41c3c9: 76 40 jbe 41c40b <_int_malloc+0xecb> + 41c3cb: 4c 89 c2 mov %r8,%rdx + 41c3ce: 4c 89 c7 mov %r8,%rdi + 41c3d1: 48 8d 40 ff lea -0x1(%rax),%rax + 41c3d5: 4c 29 f2 sub %r14,%rdx + 41c3d8: be 30 00 00 00 mov $0x30,%esi + 41c3dd: 44 89 4c 24 24 mov %r9d,0x24(%rsp) + 41c3e2: 48 29 d7 sub %rdx,%rdi + 41c3e5: 4c 89 44 24 18 mov %r8,0x18(%rsp) + 41c3ea: 48 89 44 24 10 mov %rax,0x10(%rsp) + 41c3ef: e8 5c 3f fe ff callq 400350 <__rela_iplt_end+0x88> + 41c3f4: 48 8d 44 24 6f lea 0x6f(%rsp),%rax + 41c3f9: 48 2b 44 24 10 sub 0x10(%rsp),%rax + 41c3fe: 4c 8b 44 24 18 mov 0x18(%rsp),%r8 + 41c403: 44 8b 4c 24 24 mov 0x24(%rsp),%r9d + 41c408: 49 01 c0 add %rax,%r8 + 41c40b: 48 8b 05 ae 0e 2b 00 mov 0x2b0eae(%rip),%rax # 6cd2c0 <__libc_argv> + 41c412: 44 89 cf mov %r9d,%edi + 41c415: ba 38 20 4a 00 mov $0x4a2038,%edx + 41c41a: b9 78 20 4a 00 mov $0x4a2078,%ecx + 41c41f: be a8 23 4a 00 mov $0x4a23a8,%esi + 41c424: 48 8b 00 mov (%rax),%rax + 41c427: 48 85 c0 test %rax,%rax + 41c42a: 48 0f 45 d0 cmovne %rax,%rdx + 41c42e: 83 e7 02 and $0x2,%edi + 41c431: 31 c0 xor %eax,%eax + 41c433: e8 88 51 ff ff callq 4115c0 <__libc_message> + 41c438: e9 98 fa ff ff jmpq 41bed5 <_int_malloc+0x995> + 41c43d: 44 89 cf mov %r9d,%edi + 41c440: ba 78 20 4a 00 mov $0x4a2078,%edx + 41c445: be 3c ca 4b 00 mov $0x4bca3c,%esi + 41c44a: 83 e7 02 and $0x2,%edi + 41c44d: 31 c0 xor %eax,%eax + 41c44f: e8 6c 51 ff ff callq 4115c0 <__libc_message> + 41c454: e9 7c fa ff ff jmpq 41bed5 <_int_malloc+0x995> + 41c459: 4c 39 f2 cmp %r14,%rdx + 41c45c: 74 4a je 41c4a8 <_int_malloc+0xf68> + 41c45e: 48 89 50 20 mov %rdx,0x20(%rax) + 41c462: 49 8b 56 28 mov 0x28(%r14),%rdx + 41c466: 48 89 50 28 mov %rdx,0x28(%rax) + 41c46a: 49 8b 56 20 mov 0x20(%r14),%rdx + 41c46e: 48 89 42 28 mov %rax,0x28(%rdx) + 41c472: 49 8b 56 28 mov 0x28(%r14),%rdx + 41c476: 48 89 42 20 mov %rax,0x20(%rdx) + 41c47a: e9 94 fa ff ff jmpq 41bf13 <_int_malloc+0x9d3> + 41c47f: 8b 3d eb e2 2a 00 mov 0x2ae2eb(%rip),%edi # 6ca770 + 41c485: 4c 89 f2 mov %r14,%rdx + 41c488: 48 89 d9 mov %rbx,%rcx + 41c48b: be f0 23 4a 00 mov $0x4a23f0,%esi + 41c490: 48 89 44 24 10 mov %rax,0x10(%rsp) + 41c495: e8 16 ae ff ff callq 4172b0 + 41c49a: 49 8b 56 20 mov 0x20(%r14),%rdx + 41c49e: 48 8b 44 24 10 mov 0x10(%rsp),%rax + 41c4a3: e9 7a fe ff ff jmpq 41c322 <_int_malloc+0xde2> + 41c4a8: 48 89 40 28 mov %rax,0x28(%rax) + 41c4ac: 48 89 40 20 mov %rax,0x20(%rax) + 41c4b0: e9 5e fa ff ff jmpq 41bf13 <_int_malloc+0x9d3> + 41c4b5: 49 39 c7 cmp %rax,%r15 + 41c4b8: 74 40 je 41c4fa <_int_malloc+0xfba> + 41c4ba: 49 89 45 20 mov %rax,0x20(%r13) + 41c4be: 49 8b 47 28 mov 0x28(%r15),%rax + 41c4c2: 49 89 45 28 mov %rax,0x28(%r13) + 41c4c6: 49 8b 47 20 mov 0x20(%r15),%rax + 41c4ca: 4c 89 68 28 mov %r13,0x28(%rax) + 41c4ce: 49 8b 47 28 mov 0x28(%r15),%rax + 41c4d2: 4c 89 68 20 mov %r13,0x20(%rax) + 41c4d6: e9 7c f8 ff ff jmpq 41bd57 <_int_malloc+0x817> + 41c4db: 8b 3d 8f e2 2a 00 mov 0x2ae28f(%rip),%edi # 6ca770 + 41c4e1: 48 89 d9 mov %rbx,%rcx + 41c4e4: 4c 89 fa mov %r15,%rdx + 41c4e7: be f0 23 4a 00 mov $0x4a23f0,%esi + 41c4ec: e8 bf ad ff ff callq 4172b0 + 41c4f1: 49 8b 47 20 mov 0x20(%r15),%rax + 41c4f5: e9 7b fe ff ff jmpq 41c375 <_int_malloc+0xe35> + 41c4fa: 4d 89 6d 28 mov %r13,0x28(%r13) + 41c4fe: 4d 89 6d 20 mov %r13,0x20(%r13) + 41c502: e9 50 f8 ff ff jmpq 41bd57 <_int_malloc+0x817> + 41c507: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 41c50e: 00 00 + +000000000041c510 <_int_memalign>: + 41c510: 48 83 fa bf cmp $0xffffffffffffffbf,%rdx + 41c514: 0f 87 a6 01 00 00 ja 41c6c0 <_int_memalign+0x1b0> + 41c51a: 48 83 c2 17 add $0x17,%rdx + 41c51e: 41 56 push %r14 + 41c520: 41 55 push %r13 + 41c522: 41 54 push %r12 + 41c524: 55 push %rbp + 41c525: 48 89 d5 mov %rdx,%rbp + 41c528: 48 83 e5 f0 and $0xfffffffffffffff0,%rbp + 41c52c: b8 20 00 00 00 mov $0x20,%eax + 41c531: 48 83 fa 20 cmp $0x20,%rdx + 41c535: 48 0f 42 e8 cmovb %rax,%rbp + 41c539: 53 push %rbx + 41c53a: 49 89 f5 mov %rsi,%r13 + 41c53d: 48 8d 74 35 20 lea 0x20(%rbp,%rsi,1),%rsi + 41c542: 48 89 fb mov %rdi,%rbx + 41c545: e8 f6 ef ff ff callq 41b540 <_int_malloc> + 41c54a: 48 85 c0 test %rax,%rax + 41c54d: 48 89 c1 mov %rax,%rcx + 41c550: 0f 84 aa 01 00 00 je 41c700 <_int_memalign+0x1f0> + 41c556: 31 d2 xor %edx,%edx + 41c558: 48 8d 70 f0 lea -0x10(%rax),%rsi + 41c55c: 49 f7 f5 div %r13 + 41c55f: 48 85 d2 test %rdx,%rdx + 41c562: 0f 84 c8 00 00 00 je 41c630 <_int_memalign+0x120> + 41c568: 4a 8d 44 29 ff lea -0x1(%rcx,%r13,1),%rax + 41c56d: 4c 89 ea mov %r13,%rdx + 41c570: 48 f7 da neg %rdx + 41c573: 48 21 d0 and %rdx,%rax + 41c576: 48 83 e8 10 sub $0x10,%rax + 41c57a: 48 89 c2 mov %rax,%rdx + 41c57d: 4e 8d 24 28 lea (%rax,%r13,1),%r12 + 41c581: 48 29 f2 sub %rsi,%rdx + 41c584: 48 83 fa 1f cmp $0x1f,%rdx + 41c588: 4c 0f 47 e0 cmova %rax,%r12 + 41c58c: 48 8b 41 f8 mov -0x8(%rcx),%rax + 41c590: 4c 89 e2 mov %r12,%rdx + 41c593: 48 29 f2 sub %rsi,%rdx + 41c596: 49 89 c6 mov %rax,%r14 + 41c599: 49 83 e6 f8 and $0xfffffffffffffff8,%r14 + 41c59d: 49 29 d6 sub %rdx,%r14 + 41c5a0: 83 e0 02 and $0x2,%eax + 41c5a3: 0f 85 ef 00 00 00 jne 41c698 <_int_memalign+0x188> + 41c5a9: 48 81 fb 00 a8 6c 00 cmp $0x6ca800,%rbx + 41c5b0: 0f 84 22 01 00 00 je 41c6d8 <_int_memalign+0x1c8> + 41c5b6: 4c 89 f0 mov %r14,%rax + 41c5b9: 48 83 c8 05 or $0x5,%rax + 41c5bd: 49 89 44 24 08 mov %rax,0x8(%r12) + 41c5c2: 4b 83 4c 34 08 01 orq $0x1,0x8(%r12,%r14,1) + 41c5c8: b8 04 00 00 00 mov $0x4,%eax + 41c5cd: 48 8b 79 f8 mov -0x8(%rcx),%rdi + 41c5d1: 83 e7 07 and $0x7,%edi + 41c5d4: 48 09 f8 or %rdi,%rax + 41c5d7: 48 89 df mov %rbx,%rdi + 41c5da: 48 09 c2 or %rax,%rdx + 41c5dd: 48 89 51 f8 mov %rdx,-0x8(%rcx) + 41c5e1: ba 01 00 00 00 mov $0x1,%edx + 41c5e6: e8 d5 d1 ff ff callq 4197c0 <_int_free> + 41c5eb: 4c 39 f5 cmp %r14,%rbp + 41c5ee: 0f 87 13 01 00 00 ja 41c707 <_int_memalign+0x1f7> + 41c5f4: 49 8d 4c 24 10 lea 0x10(%r12),%rcx + 41c5f9: 31 d2 xor %edx,%edx + 41c5fb: 48 89 c8 mov %rcx,%rax + 41c5fe: 49 f7 f5 div %r13 + 41c601: 48 85 d2 test %rdx,%rdx + 41c604: 0f 85 fd 00 00 00 jne 41c707 <_int_memalign+0x1f7> + 41c60a: 49 8b 54 24 08 mov 0x8(%r12),%rdx + 41c60f: 49 89 cd mov %rcx,%r13 + 41c612: 48 89 d1 mov %rdx,%rcx + 41c615: 83 e1 02 and $0x2,%ecx + 41c618: 74 29 je 41c643 <_int_memalign+0x133> + 41c61a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 41c620: 4c 89 e8 mov %r13,%rax + 41c623: 5b pop %rbx + 41c624: 5d pop %rbp + 41c625: 41 5c pop %r12 + 41c627: 41 5d pop %r13 + 41c629: 41 5e pop %r14 + 41c62b: c3 retq + 41c62c: 0f 1f 40 00 nopl 0x0(%rax) + 41c630: 49 89 f4 mov %rsi,%r12 + 41c633: 49 89 cd mov %rcx,%r13 + 41c636: 49 8b 54 24 08 mov 0x8(%r12),%rdx + 41c63b: 48 89 d1 mov %rdx,%rcx + 41c63e: 83 e1 02 and $0x2,%ecx + 41c641: 75 dd jne 41c620 <_int_memalign+0x110> + 41c643: 48 8d 75 20 lea 0x20(%rbp),%rsi + 41c647: 48 83 e2 f8 and $0xfffffffffffffff8,%rdx + 41c64b: 48 39 f2 cmp %rsi,%rdx + 41c64e: 76 d0 jbe 41c620 <_int_memalign+0x110> + 41c650: 48 29 ea sub %rbp,%rdx + 41c653: bf 04 00 00 00 mov $0x4,%edi + 41c658: 48 81 fb 00 a8 6c 00 cmp $0x6ca800,%rbx + 41c65f: 48 0f 45 cf cmovne %rdi,%rcx + 41c663: 49 8d 34 2c lea (%r12,%rbp,1),%rsi + 41c667: 48 83 ca 01 or $0x1,%rdx + 41c66b: 48 09 ca or %rcx,%rdx + 41c66e: 48 89 df mov %rbx,%rdi + 41c671: 48 89 56 08 mov %rdx,0x8(%rsi) + 41c675: 49 8b 54 24 08 mov 0x8(%r12),%rdx + 41c67a: 83 e2 07 and $0x7,%edx + 41c67d: 48 09 d5 or %rdx,%rbp + 41c680: ba 01 00 00 00 mov $0x1,%edx + 41c685: 49 89 6c 24 08 mov %rbp,0x8(%r12) + 41c68a: e8 31 d1 ff ff callq 4197c0 <_int_free> + 41c68f: eb 8f jmp 41c620 <_int_memalign+0x110> + 41c691: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 41c698: 48 03 51 f0 add -0x10(%rcx),%rdx + 41c69c: 49 83 ce 02 or $0x2,%r14 + 41c6a0: 49 8d 44 24 10 lea 0x10(%r12),%rax + 41c6a5: 4d 89 74 24 08 mov %r14,0x8(%r12) + 41c6aa: 49 89 14 24 mov %rdx,(%r12) + 41c6ae: 5b pop %rbx + 41c6af: 5d pop %rbp + 41c6b0: 41 5c pop %r12 + 41c6b2: 41 5d pop %r13 + 41c6b4: 41 5e pop %r14 + 41c6b6: c3 retq + 41c6b7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 41c6be: 00 00 + 41c6c0: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 41c6c7: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) + 41c6ce: 31 c0 xor %eax,%eax + 41c6d0: c3 retq + 41c6d1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 41c6d8: 4c 89 f7 mov %r14,%rdi + 41c6db: 48 83 cf 01 or $0x1,%rdi + 41c6df: 49 89 7c 24 08 mov %rdi,0x8(%r12) + 41c6e4: 4b 83 4c 34 08 01 orq $0x1,0x8(%r12,%r14,1) + 41c6ea: 48 8b 79 f8 mov -0x8(%rcx),%rdi + 41c6ee: 83 e7 07 and $0x7,%edi + 41c6f1: e9 de fe ff ff jmpq 41c5d4 <_int_memalign+0xc4> + 41c6f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41c6fd: 00 00 00 + 41c700: 31 c0 xor %eax,%eax + 41c702: e9 1c ff ff ff jmpq 41c623 <_int_memalign+0x113> + 41c707: b9 c8 2e 4a 00 mov $0x4a2ec8,%ecx + 41c70c: ba 6f 11 00 00 mov $0x116f,%edx + 41c711: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 41c716: bf d8 28 4a 00 mov $0x4a28d8,%edi + 41c71b: e8 00 a7 ff ff callq 416e20 <__malloc_assert> + +000000000041c720 : + 41c720: 48 83 ff ff cmp $0xffffffffffffffff,%rdi + 41c724: 0f 84 26 01 00 00 je 41c850 + 41c72a: 53 push %rbx + 41c72b: be 01 00 00 00 mov $0x1,%esi + 41c730: 48 89 fb mov %rdi,%rbx + 41c733: 31 c0 xor %eax,%eax + 41c735: 83 3d 80 0a 2b 00 00 cmpl $0x0,0x2b0a80(%rip) # 6cd1bc <__libc_multiple_threads> + 41c73c: 74 0c je 41c74a + 41c73e: f0 0f b1 35 ba e0 2a lock cmpxchg %esi,0x2ae0ba(%rip) # 6ca800 + 41c745: 00 + 41c746: 75 0b jne 41c753 + 41c748: eb 23 jmp 41c76d + 41c74a: 0f b1 35 af e0 2a 00 cmpxchg %esi,0x2ae0af(%rip) # 6ca800 + 41c751: 74 1a je 41c76d + 41c753: 48 8d 3d a6 e0 2a 00 lea 0x2ae0a6(%rip),%rdi # 6ca800 + 41c75a: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41c761: e8 6a 5e 02 00 callq 4425d0 <__lll_lock_wait_private> + 41c766: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41c76d: e8 6e b3 ff ff callq 417ae0 + 41c772: 45 31 c0 xor %r8d,%r8d + 41c775: 85 c0 test %eax,%eax + 41c777: 78 11 js 41c78a + 41c779: 48 8d 73 01 lea 0x1(%rbx),%rsi + 41c77d: bf 00 a8 6c 00 mov $0x6ca800,%edi + 41c782: e8 b9 ed ff ff callq 41b540 <_int_malloc> + 41c787: 49 89 c0 mov %rax,%r8 + 41c78a: 83 3d 2b 0a 2b 00 00 cmpl $0x0,0x2b0a2b(%rip) # 6cd1bc <__libc_multiple_threads> + 41c791: 74 0b je 41c79e + 41c793: f0 ff 0d 66 e0 2a 00 lock decl 0x2ae066(%rip) # 6ca800 + 41c79a: 75 0a jne 41c7a6 + 41c79c: eb 22 jmp 41c7c0 + 41c79e: ff 0d 5c e0 2a 00 decl 0x2ae05c(%rip) # 6ca800 + 41c7a4: 74 1a je 41c7c0 + 41c7a6: 48 8d 3d 53 e0 2a 00 lea 0x2ae053(%rip),%rdi # 6ca800 + 41c7ad: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41c7b4: e8 47 5e 02 00 callq 442600 <__lll_unlock_wake_private> + 41c7b9: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41c7c0: 4d 85 c0 test %r8,%r8 + 41c7c3: 0f 84 9f 00 00 00 je 41c868 + 41c7c9: 49 8d 40 f0 lea -0x10(%r8),%rax + 41c7cd: 49 89 c1 mov %rax,%r9 + 41c7d0: 48 c1 e8 0b shr $0xb,%rax + 41c7d4: 49 c1 e9 03 shr $0x3,%r9 + 41c7d8: 41 31 c1 xor %eax,%r9d + 41c7db: b8 02 00 00 00 mov $0x2,%eax + 41c7e0: 41 80 f9 01 cmp $0x1,%r9b + 41c7e4: 44 0f 44 c8 cmove %eax,%r9d + 41c7e8: 49 8b 40 f8 mov -0x8(%r8),%rax + 41c7ec: 41 0f b6 f9 movzbl %r9b,%edi + 41c7f0: 48 89 c2 mov %rax,%rdx + 41c7f3: 48 83 e2 f8 and $0xfffffffffffffff8,%rdx + 41c7f7: 48 8d 4a f0 lea -0x10(%rdx),%rcx + 41c7fb: 48 83 ea 08 sub $0x8,%rdx + 41c7ff: a8 02 test $0x2,%al + 41c801: b8 ff 00 00 00 mov $0xff,%eax + 41c806: 48 0f 44 ca cmove %rdx,%rcx + 41c80a: 48 83 e9 01 sub $0x1,%rcx + 41c80e: 48 39 cb cmp %rcx,%rbx + 41c811: 73 2d jae 41c840 + 41c813: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41c818: 48 89 ca mov %rcx,%rdx + 41c81b: 48 29 da sub %rbx,%rdx + 41c81e: 48 81 fa ff 00 00 00 cmp $0xff,%rdx + 41c825: 48 0f 47 d0 cmova %rax,%rdx + 41c829: 48 8d 72 ff lea -0x1(%rdx),%rsi + 41c82d: 48 39 fa cmp %rdi,%rdx + 41c830: 48 0f 44 d6 cmove %rsi,%rdx + 41c834: 41 88 14 08 mov %dl,(%r8,%rcx,1) + 41c838: 48 29 d1 sub %rdx,%rcx + 41c83b: 48 39 cb cmp %rcx,%rbx + 41c83e: 72 d8 jb 41c818 + 41c840: 45 88 0c 18 mov %r9b,(%r8,%rbx,1) + 41c844: 4c 89 c0 mov %r8,%rax + 41c847: 5b pop %rbx + 41c848: c3 retq + 41c849: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 41c850: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 41c857: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) + 41c85e: 31 c0 xor %eax,%eax + 41c860: c3 retq + 41c861: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 41c868: 31 c0 xor %eax,%eax + 41c86a: 5b pop %rbx + 41c86b: c3 retq + 41c86c: 0f 1f 40 00 nopl 0x0(%rax) + +000000000041c870 : + 41c870: 55 push %rbp + 41c871: 53 push %rbx + 41c872: 48 89 f3 mov %rsi,%rbx + 41c875: 48 83 ec 08 sub $0x8,%rsp + 41c879: 48 83 ff 10 cmp $0x10,%rdi + 41c87d: 0f 86 8d 01 00 00 jbe 41ca10 + 41c883: 48 83 ff 1f cmp $0x1f,%rdi + 41c887: 0f 87 33 01 00 00 ja 41c9c0 + 41c88d: 48 83 fe bf cmp $0xffffffffffffffbf,%rsi + 41c891: 0f 87 a1 01 00 00 ja 41ca38 + 41c897: bd 20 00 00 00 mov $0x20,%ebp + 41c89c: be 01 00 00 00 mov $0x1,%esi + 41c8a1: 31 c0 xor %eax,%eax + 41c8a3: 83 3d 12 09 2b 00 00 cmpl $0x0,0x2b0912(%rip) # 6cd1bc <__libc_multiple_threads> + 41c8aa: 74 0c je 41c8b8 + 41c8ac: f0 0f b1 35 4c df 2a lock cmpxchg %esi,0x2adf4c(%rip) # 6ca800 + 41c8b3: 00 + 41c8b4: 75 0b jne 41c8c1 + 41c8b6: eb 23 jmp 41c8db + 41c8b8: 0f b1 35 41 df 2a 00 cmpxchg %esi,0x2adf41(%rip) # 6ca800 + 41c8bf: 74 1a je 41c8db + 41c8c1: 48 8d 3d 38 df 2a 00 lea 0x2adf38(%rip),%rdi # 6ca800 + 41c8c8: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41c8cf: e8 fc 5c 02 00 callq 4425d0 <__lll_lock_wait_private> + 41c8d4: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41c8db: e8 00 b2 ff ff callq 417ae0 + 41c8e0: 45 31 c0 xor %r8d,%r8d + 41c8e3: 85 c0 test %eax,%eax + 41c8e5: 78 14 js 41c8fb + 41c8e7: 48 8d 53 01 lea 0x1(%rbx),%rdx + 41c8eb: 48 89 ee mov %rbp,%rsi + 41c8ee: bf 00 a8 6c 00 mov $0x6ca800,%edi + 41c8f3: e8 18 fc ff ff callq 41c510 <_int_memalign> + 41c8f8: 49 89 c0 mov %rax,%r8 + 41c8fb: 83 3d ba 08 2b 00 00 cmpl $0x0,0x2b08ba(%rip) # 6cd1bc <__libc_multiple_threads> + 41c902: 74 0b je 41c90f + 41c904: f0 ff 0d f5 de 2a 00 lock decl 0x2adef5(%rip) # 6ca800 + 41c90b: 75 0a jne 41c917 + 41c90d: eb 22 jmp 41c931 + 41c90f: ff 0d eb de 2a 00 decl 0x2adeeb(%rip) # 6ca800 + 41c915: 74 1a je 41c931 + 41c917: 48 8d 3d e2 de 2a 00 lea 0x2adee2(%rip),%rdi # 6ca800 + 41c91e: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41c925: e8 d6 5c 02 00 callq 442600 <__lll_unlock_wake_private> + 41c92a: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41c931: 4d 85 c0 test %r8,%r8 + 41c934: 0f 84 16 01 00 00 je 41ca50 + 41c93a: 49 8d 40 f0 lea -0x10(%r8),%rax + 41c93e: 49 89 c1 mov %rax,%r9 + 41c941: 48 c1 e8 0b shr $0xb,%rax + 41c945: 49 c1 e9 03 shr $0x3,%r9 + 41c949: 41 31 c1 xor %eax,%r9d + 41c94c: b8 02 00 00 00 mov $0x2,%eax + 41c951: 41 80 f9 01 cmp $0x1,%r9b + 41c955: 44 0f 44 c8 cmove %eax,%r9d + 41c959: 49 8b 40 f8 mov -0x8(%r8),%rax + 41c95d: 41 0f b6 f9 movzbl %r9b,%edi + 41c961: 48 89 c2 mov %rax,%rdx + 41c964: 48 83 e2 f8 and $0xfffffffffffffff8,%rdx + 41c968: 48 8d 4a f0 lea -0x10(%rdx),%rcx + 41c96c: 48 83 ea 08 sub $0x8,%rdx + 41c970: a8 02 test $0x2,%al + 41c972: b8 ff 00 00 00 mov $0xff,%eax + 41c977: 48 0f 44 ca cmove %rdx,%rcx + 41c97b: 48 83 e9 01 sub $0x1,%rcx + 41c97f: 48 39 cb cmp %rcx,%rbx + 41c982: 73 2c jae 41c9b0 + 41c984: 0f 1f 40 00 nopl 0x0(%rax) + 41c988: 48 89 ca mov %rcx,%rdx + 41c98b: 48 29 da sub %rbx,%rdx + 41c98e: 48 81 fa ff 00 00 00 cmp $0xff,%rdx + 41c995: 48 0f 47 d0 cmova %rax,%rdx + 41c999: 48 8d 72 ff lea -0x1(%rdx),%rsi + 41c99d: 48 39 fa cmp %rdi,%rdx + 41c9a0: 48 0f 44 d6 cmove %rsi,%rdx + 41c9a4: 41 88 14 08 mov %dl,(%r8,%rcx,1) + 41c9a8: 48 29 d1 sub %rdx,%rcx + 41c9ab: 48 39 cb cmp %rcx,%rbx + 41c9ae: 72 d8 jb 41c988 + 41c9b0: 45 88 0c 18 mov %r9b,(%r8,%rbx,1) + 41c9b4: 4c 89 c0 mov %r8,%rax + 41c9b7: 48 83 c4 08 add $0x8,%rsp + 41c9bb: 5b pop %rbx + 41c9bc: 5d pop %rbp + 41c9bd: c3 retq + 41c9be: 66 90 xchg %ax,%ax + 41c9c0: 48 b8 00 00 00 00 00 movabs $0x8000000000000000,%rax + 41c9c7: 00 00 80 + 41c9ca: 48 39 c7 cmp %rax,%rdi + 41c9cd: 77 51 ja 41ca20 + 41c9cf: 48 c7 c0 df ff ff ff mov $0xffffffffffffffdf,%rax + 41c9d6: 48 29 f8 sub %rdi,%rax + 41c9d9: 48 39 c6 cmp %rax,%rsi + 41c9dc: 77 5a ja 41ca38 + 41c9de: 48 8d 47 ff lea -0x1(%rdi),%rax + 41c9e2: 48 85 f8 test %rdi,%rax + 41c9e5: 74 70 je 41ca57 + 41c9e7: 48 83 ff 20 cmp $0x20,%rdi + 41c9eb: bd 20 00 00 00 mov $0x20,%ebp + 41c9f0: 0f 84 a6 fe ff ff je 41c89c + 41c9f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41c9fd: 00 00 00 + 41ca00: 48 01 ed add %rbp,%rbp + 41ca03: 48 39 ef cmp %rbp,%rdi + 41ca06: 77 f8 ja 41ca00 + 41ca08: e9 8f fe ff ff jmpq 41c89c + 41ca0d: 0f 1f 00 nopl (%rax) + 41ca10: 48 83 c4 08 add $0x8,%rsp + 41ca14: 48 89 df mov %rbx,%rdi + 41ca17: 31 f6 xor %esi,%esi + 41ca19: 5b pop %rbx + 41ca1a: 5d pop %rbp + 41ca1b: e9 00 fd ff ff jmpq 41c720 + 41ca20: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 41ca27: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) + 41ca2e: 31 c0 xor %eax,%eax + 41ca30: e9 82 ff ff ff jmpq 41c9b7 + 41ca35: 0f 1f 00 nopl (%rax) + 41ca38: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 41ca3f: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) + 41ca46: 31 c0 xor %eax,%eax + 41ca48: e9 6a ff ff ff jmpq 41c9b7 + 41ca4d: 0f 1f 00 nopl (%rax) + 41ca50: 31 c0 xor %eax,%eax + 41ca52: e9 60 ff ff ff jmpq 41c9b7 + 41ca57: 48 89 fd mov %rdi,%rbp + 41ca5a: e9 3d fe ff ff jmpq 41c89c + 41ca5f: 90 nop + +000000000041ca60 <_int_realloc>: + 41ca60: 41 57 push %r15 + 41ca62: 41 56 push %r14 + 41ca64: 41 55 push %r13 + 41ca66: 41 54 push %r12 + 41ca68: 49 89 cd mov %rcx,%r13 + 41ca6b: 55 push %rbp + 41ca6c: 53 push %rbx + 41ca6d: 48 89 fd mov %rdi,%rbp + 41ca70: 48 89 f3 mov %rsi,%rbx + 41ca73: 48 83 ec 48 sub $0x48,%rsp + 41ca77: 48 8b 4e 08 mov 0x8(%rsi),%rcx + 41ca7b: 48 83 f9 10 cmp $0x10,%rcx + 41ca7f: 0f 86 03 02 00 00 jbe 41cc88 <_int_realloc+0x228> + 41ca85: 48 8b 87 80 08 00 00 mov 0x880(%rdi),%rax + 41ca8c: 48 39 d0 cmp %rdx,%rax + 41ca8f: 0f 86 9b 02 00 00 jbe 41cd30 <_int_realloc+0x2d0> + 41ca95: 49 89 cc mov %rcx,%r12 + 41ca98: 41 83 e4 02 and $0x2,%r12d + 41ca9c: 0f 85 77 06 00 00 jne 41d119 <_int_realloc+0x6b9> + 41caa2: 4c 8d 3c 16 lea (%rsi,%rdx,1),%r15 + 41caa6: 49 8b 77 08 mov 0x8(%r15),%rsi + 41caaa: 48 89 f7 mov %rsi,%rdi + 41caad: 48 83 e7 f8 and $0xfffffffffffffff8,%rdi + 41cab1: 48 39 f8 cmp %rdi,%rax + 41cab4: 0f 86 16 03 00 00 jbe 41cdd0 <_int_realloc+0x370> + 41caba: 48 83 fe 10 cmp $0x10,%rsi + 41cabe: 0f 86 0c 03 00 00 jbe 41cdd0 <_int_realloc+0x370> + 41cac4: 4c 39 ea cmp %r13,%rdx + 41cac7: 72 47 jb 41cb10 <_int_realloc+0xb0> + 41cac9: 48 89 d0 mov %rdx,%rax + 41cacc: 4c 29 e8 sub %r13,%rax + 41cacf: 48 83 f8 1f cmp $0x1f,%rax + 41cad3: 0f 87 07 02 00 00 ja 41cce0 <_int_realloc+0x280> + 41cad9: 83 e1 07 and $0x7,%ecx + 41cadc: b8 04 00 00 00 mov $0x4,%eax + 41cae1: 48 81 fd 00 a8 6c 00 cmp $0x6ca800,%rbp + 41cae8: 4c 0f 45 e0 cmovne %rax,%r12 + 41caec: 48 09 d1 or %rdx,%rcx + 41caef: 4c 09 e1 or %r12,%rcx + 41caf2: 48 89 4b 08 mov %rcx,0x8(%rbx) + 41caf6: 48 83 4c 13 08 01 orq $0x1,0x8(%rbx,%rdx,1) + 41cafc: 48 8d 43 10 lea 0x10(%rbx),%rax + 41cb00: 48 83 c4 48 add $0x48,%rsp + 41cb04: 5b pop %rbx + 41cb05: 5d pop %rbp + 41cb06: 41 5c pop %r12 + 41cb08: 41 5d pop %r13 + 41cb0a: 41 5e pop %r14 + 41cb0c: 41 5f pop %r15 + 41cb0e: c3 retq + 41cb0f: 90 nop + 41cb10: 4c 3b 7d 58 cmp 0x58(%rbp),%r15 + 41cb14: 0f 84 3e 03 00 00 je 41ce58 <_int_realloc+0x3f8> + 41cb1a: 49 8d 04 3f lea (%r15,%rdi,1),%rax + 41cb1e: f6 40 08 01 testb $0x1,0x8(%rax) + 41cb22: 0f 85 98 00 00 00 jne 41cbc0 <_int_realloc+0x160> + 41cb28: 4c 8d 0c 3a lea (%rdx,%rdi,1),%r9 + 41cb2c: 4d 39 cd cmp %r9,%r13 + 41cb2f: 0f 87 8b 00 00 00 ja 41cbc0 <_int_realloc+0x160> + 41cb35: 48 3b 38 cmp (%rax),%rdi + 41cb38: 0f 85 86 03 00 00 jne 41cec4 <_int_realloc+0x464> + 41cb3e: 4d 8b 77 10 mov 0x10(%r15),%r14 + 41cb42: 49 8b 47 18 mov 0x18(%r15),%rax + 41cb46: 4d 3b 7e 18 cmp 0x18(%r14),%r15 + 41cb4a: 0f 85 d0 02 00 00 jne 41ce20 <_int_realloc+0x3c0> + 41cb50: 4c 3b 78 10 cmp 0x10(%rax),%r15 + 41cb54: 0f 85 c6 02 00 00 jne 41ce20 <_int_realloc+0x3c0> + 41cb5a: 49 81 7f 08 ff 03 00 cmpq $0x3ff,0x8(%r15) + 41cb61: 00 + 41cb62: 49 89 46 18 mov %rax,0x18(%r14) + 41cb66: 4c 89 70 10 mov %r14,0x10(%rax) + 41cb6a: 76 44 jbe 41cbb0 <_int_realloc+0x150> + 41cb6c: 49 8b 47 20 mov 0x20(%r15),%rax + 41cb70: 48 85 c0 test %rax,%rax + 41cb73: 74 3b je 41cbb0 <_int_realloc+0x150> + 41cb75: 4c 3b 78 28 cmp 0x28(%rax),%r15 + 41cb79: 0f 85 4d 05 00 00 jne 41d0cc <_int_realloc+0x66c> + 41cb7f: 49 8b 57 28 mov 0x28(%r15),%rdx + 41cb83: 4c 3b 7a 20 cmp 0x20(%rdx),%r15 + 41cb87: 0f 85 3f 05 00 00 jne 41d0cc <_int_realloc+0x66c> + 41cb8d: 49 83 7e 20 00 cmpq $0x0,0x20(%r14) + 41cb92: 0f 84 5b 05 00 00 je 41d0f3 <_int_realloc+0x693> + 41cb98: 49 8b 57 28 mov 0x28(%r15),%rdx + 41cb9c: 48 89 50 28 mov %rdx,0x28(%rax) + 41cba0: 49 8b 57 28 mov 0x28(%r15),%rdx + 41cba4: 48 89 42 20 mov %rax,0x20(%rdx) + 41cba8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 41cbaf: 00 + 41cbb0: 48 8b 4b 08 mov 0x8(%rbx),%rcx + 41cbb4: 4c 89 ca mov %r9,%rdx + 41cbb7: e9 0d ff ff ff jmpq 41cac9 <_int_realloc+0x69> + 41cbbc: 0f 1f 40 00 nopl 0x0(%rax) + 41cbc0: 49 8d 75 f1 lea -0xf(%r13),%rsi + 41cbc4: 48 89 ef mov %rbp,%rdi + 41cbc7: 48 89 14 24 mov %rdx,(%rsp) + 41cbcb: e8 70 e9 ff ff callq 41b540 <_int_malloc> + 41cbd0: 48 85 c0 test %rax,%rax + 41cbd3: 49 89 c6 mov %rax,%r14 + 41cbd6: 0f 84 ef 00 00 00 je 41cccb <_int_realloc+0x26b> + 41cbdc: 48 8d 40 f0 lea -0x10(%rax),%rax + 41cbe0: 48 8b 14 24 mov (%rsp),%rdx + 41cbe4: 49 39 c7 cmp %rax,%r15 + 41cbe7: 0f 84 0b 02 00 00 je 41cdf8 <_int_realloc+0x398> + 41cbed: 48 83 ea 08 sub $0x8,%rdx + 41cbf1: 48 89 d0 mov %rdx,%rax + 41cbf4: 48 c1 e8 03 shr $0x3,%rax + 41cbf8: 83 f8 02 cmp $0x2,%eax + 41cbfb: 0f 86 4a 05 00 00 jbe 41d14b <_int_realloc+0x6eb> + 41cc01: 83 f8 09 cmp $0x9,%eax + 41cc04: 0f 87 d6 01 00 00 ja 41cde0 <_int_realloc+0x380> + 41cc0a: 48 8b 53 10 mov 0x10(%rbx),%rdx + 41cc0e: 83 f8 04 cmp $0x4,%eax + 41cc11: 49 89 16 mov %rdx,(%r14) + 41cc14: 48 8b 53 18 mov 0x18(%rbx),%rdx + 41cc18: 49 89 56 08 mov %rdx,0x8(%r14) + 41cc1c: 48 8b 53 20 mov 0x20(%rbx),%rdx + 41cc20: 49 89 56 10 mov %rdx,0x10(%r14) + 41cc24: 76 3a jbe 41cc60 <_int_realloc+0x200> + 41cc26: 48 8b 53 28 mov 0x28(%rbx),%rdx + 41cc2a: 83 f8 06 cmp $0x6,%eax + 41cc2d: 49 89 56 18 mov %rdx,0x18(%r14) + 41cc31: 48 8b 53 30 mov 0x30(%rbx),%rdx + 41cc35: 49 89 56 20 mov %rdx,0x20(%r14) + 41cc39: 76 25 jbe 41cc60 <_int_realloc+0x200> + 41cc3b: 48 8b 53 38 mov 0x38(%rbx),%rdx + 41cc3f: 83 f8 09 cmp $0x9,%eax + 41cc42: 49 89 56 28 mov %rdx,0x28(%r14) + 41cc46: 48 8b 53 40 mov 0x40(%rbx),%rdx + 41cc4a: 49 89 56 30 mov %rdx,0x30(%r14) + 41cc4e: 75 10 jne 41cc60 <_int_realloc+0x200> + 41cc50: 48 8b 43 48 mov 0x48(%rbx),%rax + 41cc54: 49 89 46 38 mov %rax,0x38(%r14) + 41cc58: 48 8b 43 50 mov 0x50(%rbx),%rax + 41cc5c: 49 89 46 40 mov %rax,0x40(%r14) + 41cc60: 48 89 de mov %rbx,%rsi + 41cc63: 48 89 ef mov %rbp,%rdi + 41cc66: ba 01 00 00 00 mov $0x1,%edx + 41cc6b: e8 50 cb ff ff callq 4197c0 <_int_free> + 41cc70: 48 83 c4 48 add $0x48,%rsp + 41cc74: 4c 89 f0 mov %r14,%rax + 41cc77: 5b pop %rbx + 41cc78: 5d pop %rbp + 41cc79: 41 5c pop %r12 + 41cc7b: 41 5d pop %r13 + 41cc7d: 41 5e pop %r14 + 41cc7f: 41 5f pop %r15 + 41cc81: c3 retq + 41cc82: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 41cc88: 48 85 ed test %rbp,%rbp + 41cc8b: 48 8d 7e 10 lea 0x10(%rsi),%rdi + 41cc8f: 44 8b 25 da da 2a 00 mov 0x2adada(%rip),%r12d # 6ca770 + 41cc96: 41 bd 67 21 4a 00 mov $0x4a2167,%r13d + 41cc9c: 0f 85 9f 00 00 00 jne 41cd41 <_int_realloc+0x2e1> + 41cca2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 41cca8: 44 89 e2 mov %r12d,%edx + 41ccab: 83 e2 05 and $0x5,%edx + 41ccae: 83 fa 05 cmp $0x5,%edx + 41ccb1: 0f 84 f1 01 00 00 je 41cea8 <_int_realloc+0x448> + 41ccb7: 41 f6 c4 01 test $0x1,%r12b + 41ccbb: 0f 85 8f 00 00 00 jne 41cd50 <_int_realloc+0x2f0> + 41ccc1: 41 83 e4 02 and $0x2,%r12d + 41ccc5: 0f 85 83 01 00 00 jne 41ce4e <_int_realloc+0x3ee> + 41cccb: 48 83 c4 48 add $0x48,%rsp + 41cccf: 31 c0 xor %eax,%eax + 41ccd1: 5b pop %rbx + 41ccd2: 5d pop %rbp + 41ccd3: 41 5c pop %r12 + 41ccd5: 41 5d pop %r13 + 41ccd7: 41 5e pop %r14 + 41ccd9: 41 5f pop %r15 + 41ccdb: c3 retq + 41ccdc: 0f 1f 40 00 nopl 0x0(%rax) + 41cce0: 83 e1 07 and $0x7,%ecx + 41cce3: 48 81 fd 00 a8 6c 00 cmp $0x6ca800,%rbp + 41ccea: 4a 8d 34 2b lea (%rbx,%r13,1),%rsi + 41ccee: 0f 84 24 01 00 00 je 41ce18 <_int_realloc+0x3b8> + 41ccf4: 49 83 cd 04 or $0x4,%r13 + 41ccf8: 41 bc 04 00 00 00 mov $0x4,%r12d + 41ccfe: 4c 09 e9 or %r13,%rcx + 41cd01: 48 89 4b 08 mov %rcx,0x8(%rbx) + 41cd05: 48 89 c1 mov %rax,%rcx + 41cd08: ba 01 00 00 00 mov $0x1,%edx + 41cd0d: 48 83 c9 01 or $0x1,%rcx + 41cd11: 48 89 ef mov %rbp,%rdi + 41cd14: 4c 09 e1 or %r12,%rcx + 41cd17: 48 89 4e 08 mov %rcx,0x8(%rsi) + 41cd1b: 48 83 4c 06 08 01 orq $0x1,0x8(%rsi,%rax,1) + 41cd21: e8 9a ca ff ff callq 4197c0 <_int_free> + 41cd26: e9 d1 fd ff ff jmpq 41cafc <_int_realloc+0x9c> + 41cd2b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41cd30: 41 bd 67 21 4a 00 mov $0x4a2167,%r13d + 41cd36: 44 8b 25 33 da 2a 00 mov 0x2ada33(%rip),%r12d # 6ca770 + 41cd3d: 48 8d 7b 10 lea 0x10(%rbx),%rdi + 41cd41: 83 4d 04 04 orl $0x4,0x4(%rbp) + 41cd45: e9 5e ff ff ff jmpq 41cca8 <_int_realloc+0x248> + 41cd4a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 41cd50: 48 8d 6c 24 20 lea 0x20(%rsp),%rbp + 41cd55: 48 8d 74 24 30 lea 0x30(%rsp),%rsi + 41cd5a: 31 c9 xor %ecx,%ecx + 41cd5c: ba 10 00 00 00 mov $0x10,%edx + 41cd61: c6 44 24 30 00 movb $0x0,0x30(%rsp) + 41cd66: e8 45 51 03 00 callq 451eb0 <_itoa_word> + 41cd6b: 48 39 e8 cmp %rbp,%rax + 41cd6e: 48 89 c3 mov %rax,%rbx + 41cd71: 76 25 jbe 41cd98 <_int_realloc+0x338> + 41cd73: 48 89 c2 mov %rax,%rdx + 41cd76: 48 89 c7 mov %rax,%rdi + 41cd79: be 30 00 00 00 mov $0x30,%esi + 41cd7e: 48 29 ea sub %rbp,%rdx + 41cd81: 4c 8d 70 ff lea -0x1(%rax),%r14 + 41cd85: 48 29 d7 sub %rdx,%rdi + 41cd88: e8 c3 35 fe ff callq 400350 <__rela_iplt_end+0x88> + 41cd8d: 48 8d 44 24 1f lea 0x1f(%rsp),%rax + 41cd92: 4c 29 f0 sub %r14,%rax + 41cd95: 48 01 c3 add %rax,%rbx + 41cd98: 48 8b 05 21 05 2b 00 mov 0x2b0521(%rip),%rax # 6cd2c0 <__libc_argv> + 41cd9f: ba 38 20 4a 00 mov $0x4a2038,%edx + 41cda4: 44 89 e7 mov %r12d,%edi + 41cda7: 49 89 d8 mov %rbx,%r8 + 41cdaa: 4c 89 e9 mov %r13,%rcx + 41cdad: be a8 23 4a 00 mov $0x4a23a8,%esi + 41cdb2: 48 8b 00 mov (%rax),%rax + 41cdb5: 48 85 c0 test %rax,%rax + 41cdb8: 48 0f 45 d0 cmovne %rax,%rdx + 41cdbc: 31 c0 xor %eax,%eax + 41cdbe: 83 e7 02 and $0x2,%edi + 41cdc1: e8 fa 47 ff ff callq 4115c0 <__libc_message> + 41cdc6: 31 c0 xor %eax,%eax + 41cdc8: e9 33 fd ff ff jmpq 41cb00 <_int_realloc+0xa0> + 41cdcd: 0f 1f 00 nopl (%rax) + 41cdd0: 41 bd 83 21 4a 00 mov $0x4a2183,%r13d + 41cdd6: e9 5b ff ff ff jmpq 41cd36 <_int_realloc+0x2d6> + 41cddb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41cde0: 48 8d 73 10 lea 0x10(%rbx),%rsi + 41cde4: 4c 89 f7 mov %r14,%rdi + 41cde7: e8 34 f2 00 00 callq 42c020 + 41cdec: e9 6f fe ff ff jmpq 41cc60 <_int_realloc+0x200> + 41cdf1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 41cdf8: 49 8b 46 f8 mov -0x8(%r14),%rax + 41cdfc: 48 83 e0 f8 and $0xfffffffffffffff8,%rax + 41ce00: 48 01 c2 add %rax,%rdx + 41ce03: 49 39 d5 cmp %rdx,%r13 + 41ce06: 0f 87 26 03 00 00 ja 41d132 <_int_realloc+0x6d2> + 41ce0c: 48 8b 4b 08 mov 0x8(%rbx),%rcx + 41ce10: e9 b4 fc ff ff jmpq 41cac9 <_int_realloc+0x69> + 41ce15: 0f 1f 00 nopl (%rax) + 41ce18: 4c 09 e9 or %r13,%rcx + 41ce1b: e9 e1 fe ff ff jmpq 41cd01 <_int_realloc+0x2a1> + 41ce20: 44 8b 15 49 d9 2a 00 mov 0x2ad949(%rip),%r10d # 6ca770 + 41ce27: 83 4d 04 04 orl $0x4,0x4(%rbp) + 41ce2b: 44 89 d0 mov %r10d,%eax + 41ce2e: 83 e0 05 and $0x5,%eax + 41ce31: 83 f8 05 cmp $0x5,%eax + 41ce34: 0f 84 4a 02 00 00 je 41d084 <_int_realloc+0x624> + 41ce3a: 41 f6 c2 01 test $0x1,%r10b + 41ce3e: 0f 85 d3 00 00 00 jne 41cf17 <_int_realloc+0x4b7> + 41ce44: 41 83 e2 02 and $0x2,%r10d + 41ce48: 0f 84 62 fd ff ff je 41cbb0 <_int_realloc+0x150> + 41ce4e: e8 ad 0d ff ff callq 40dc00 + 41ce53: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41ce58: 49 8d 45 20 lea 0x20(%r13),%rax + 41ce5c: 48 01 d7 add %rdx,%rdi + 41ce5f: 48 39 c7 cmp %rax,%rdi + 41ce62: 0f 82 58 fd ff ff jb 41cbc0 <_int_realloc+0x160> + 41ce68: 83 e1 07 and $0x7,%ecx + 41ce6b: b8 04 00 00 00 mov $0x4,%eax + 41ce70: 48 81 fd 00 a8 6c 00 cmp $0x6ca800,%rbp + 41ce77: 48 89 ca mov %rcx,%rdx + 41ce7a: 4c 0f 45 e0 cmovne %rax,%r12 + 41ce7e: 4a 8d 04 2b lea (%rbx,%r13,1),%rax + 41ce82: 4c 09 ea or %r13,%rdx + 41ce85: 4c 29 ef sub %r13,%rdi + 41ce88: 4c 09 e2 or %r12,%rdx + 41ce8b: 48 83 cf 01 or $0x1,%rdi + 41ce8f: 48 89 53 08 mov %rdx,0x8(%rbx) + 41ce93: 48 89 45 58 mov %rax,0x58(%rbp) + 41ce97: 48 89 78 08 mov %rdi,0x8(%rax) + 41ce9b: 48 8d 43 10 lea 0x10(%rbx),%rax + 41ce9f: e9 5c fc ff ff jmpq 41cb00 <_int_realloc+0xa0> + 41cea4: 0f 1f 40 00 nopl 0x0(%rax) + 41cea8: 44 89 e7 mov %r12d,%edi + 41ceab: 31 c0 xor %eax,%eax + 41cead: 4c 89 ea mov %r13,%rdx + 41ceb0: 83 e7 02 and $0x2,%edi + 41ceb3: be 3c ca 4b 00 mov $0x4bca3c,%esi + 41ceb8: e8 03 47 ff ff callq 4115c0 <__libc_message> + 41cebd: 31 c0 xor %eax,%eax + 41cebf: e9 3c fc ff ff jmpq 41cb00 <_int_realloc+0xa0> + 41cec4: 44 8b 15 a5 d8 2a 00 mov 0x2ad8a5(%rip),%r10d # 6ca770 + 41cecb: 83 4d 04 04 orl $0x4,0x4(%rbp) + 41cecf: 44 89 d0 mov %r10d,%eax + 41ced2: 83 e0 05 and $0x5,%eax + 41ced5: 83 f8 05 cmp $0x5,%eax + 41ced8: 0f 84 ca 01 00 00 je 41d0a8 <_int_realloc+0x648> + 41cede: 41 f6 c2 01 test $0x1,%r10b + 41cee2: 0f 85 e2 00 00 00 jne 41cfca <_int_realloc+0x56a> + 41cee8: 41 f6 c2 02 test $0x2,%r10b + 41ceec: 0f 85 5c ff ff ff jne 41ce4e <_int_realloc+0x3ee> + 41cef2: 4d 8b 77 10 mov 0x10(%r15),%r14 + 41cef6: 49 8b 47 18 mov 0x18(%r15),%rax + 41cefa: 4d 3b 7e 18 cmp 0x18(%r14),%r15 + 41cefe: 0f 85 40 ff ff ff jne 41ce44 <_int_realloc+0x3e4> + 41cf04: 4c 3b 78 10 cmp 0x10(%rax),%r15 + 41cf08: 0f 84 4c fc ff ff je 41cb5a <_int_realloc+0xfa> + 41cf0e: 83 4d 04 04 orl $0x4,0x4(%rbp) + 41cf12: e9 23 ff ff ff jmpq 41ce3a <_int_realloc+0x3da> + 41cf17: 4c 8d 74 24 20 lea 0x20(%rsp),%r14 + 41cf1c: 48 8d 74 24 30 lea 0x30(%rsp),%rsi + 41cf21: 31 c9 xor %ecx,%ecx + 41cf23: 4c 89 ff mov %r15,%rdi + 41cf26: ba 10 00 00 00 mov $0x10,%edx + 41cf2b: 44 89 54 24 08 mov %r10d,0x8(%rsp) + 41cf30: 4c 89 0c 24 mov %r9,(%rsp) + 41cf34: c6 44 24 30 00 movb $0x0,0x30(%rsp) + 41cf39: e8 72 4f 03 00 callq 451eb0 <_itoa_word> + 41cf3e: 4c 39 f0 cmp %r14,%rax + 41cf41: 49 89 c7 mov %rax,%r15 + 41cf44: 4c 8b 0c 24 mov (%rsp),%r9 + 41cf48: 44 8b 54 24 08 mov 0x8(%rsp),%r10d + 41cf4d: 76 3e jbe 41cf8d <_int_realloc+0x52d> + 41cf4f: 4c 89 fa mov %r15,%rdx + 41cf52: 48 8d 40 ff lea -0x1(%rax),%rax + 41cf56: 4c 89 ff mov %r15,%rdi + 41cf59: 4c 29 f2 sub %r14,%rdx + 41cf5c: be 30 00 00 00 mov $0x30,%esi + 41cf61: 44 89 54 24 10 mov %r10d,0x10(%rsp) + 41cf66: 48 29 d7 sub %rdx,%rdi + 41cf69: 4c 89 4c 24 08 mov %r9,0x8(%rsp) + 41cf6e: 48 89 04 24 mov %rax,(%rsp) + 41cf72: e8 d9 33 fe ff callq 400350 <__rela_iplt_end+0x88> + 41cf77: 48 8d 44 24 1f lea 0x1f(%rsp),%rax + 41cf7c: 48 2b 04 24 sub (%rsp),%rax + 41cf80: 44 8b 54 24 10 mov 0x10(%rsp),%r10d + 41cf85: 4c 8b 4c 24 08 mov 0x8(%rsp),%r9 + 41cf8a: 49 01 c7 add %rax,%r15 + 41cf8d: 48 8b 05 2c 03 2b 00 mov 0x2b032c(%rip),%rax # 6cd2c0 <__libc_argv> + 41cf94: 44 89 d7 mov %r10d,%edi + 41cf97: ba 38 20 4a 00 mov $0x4a2038,%edx + 41cf9c: 4d 89 f8 mov %r15,%r8 + 41cf9f: b9 95 20 4a 00 mov $0x4a2095,%ecx + 41cfa4: be a8 23 4a 00 mov $0x4a23a8,%esi + 41cfa9: 4c 89 0c 24 mov %r9,(%rsp) + 41cfad: 48 8b 00 mov (%rax),%rax + 41cfb0: 48 85 c0 test %rax,%rax + 41cfb3: 48 0f 45 d0 cmovne %rax,%rdx + 41cfb7: 83 e7 02 and $0x2,%edi + 41cfba: 31 c0 xor %eax,%eax + 41cfbc: e8 ff 45 ff ff callq 4115c0 <__libc_message> + 41cfc1: 4c 8b 0c 24 mov (%rsp),%r9 + 41cfc5: e9 e6 fb ff ff jmpq 41cbb0 <_int_realloc+0x150> + 41cfca: 4c 8d 74 24 20 lea 0x20(%rsp),%r14 + 41cfcf: 48 8d 74 24 30 lea 0x30(%rsp),%rsi + 41cfd4: 31 c9 xor %ecx,%ecx + 41cfd6: ba 10 00 00 00 mov $0x10,%edx + 41cfdb: 4c 89 ff mov %r15,%rdi + 41cfde: 44 89 54 24 08 mov %r10d,0x8(%rsp) + 41cfe3: 4c 89 0c 24 mov %r9,(%rsp) + 41cfe7: c6 44 24 30 00 movb $0x0,0x30(%rsp) + 41cfec: e8 bf 4e 03 00 callq 451eb0 <_itoa_word> + 41cff1: 4c 39 f0 cmp %r14,%rax + 41cff4: 49 89 c0 mov %rax,%r8 + 41cff7: 4c 8b 0c 24 mov (%rsp),%r9 + 41cffb: 44 8b 54 24 08 mov 0x8(%rsp),%r10d + 41d000: 76 48 jbe 41d04a <_int_realloc+0x5ea> + 41d002: 4c 89 c2 mov %r8,%rdx + 41d005: 4c 89 c7 mov %r8,%rdi + 41d008: 48 8d 40 ff lea -0x1(%rax),%rax + 41d00c: 4c 29 f2 sub %r14,%rdx + 41d00f: be 30 00 00 00 mov $0x30,%esi + 41d014: 44 89 54 24 1c mov %r10d,0x1c(%rsp) + 41d019: 48 29 d7 sub %rdx,%rdi + 41d01c: 4c 89 4c 24 10 mov %r9,0x10(%rsp) + 41d021: 4c 89 44 24 08 mov %r8,0x8(%rsp) + 41d026: 48 89 04 24 mov %rax,(%rsp) + 41d02a: e8 21 33 fe ff callq 400350 <__rela_iplt_end+0x88> + 41d02f: 48 8d 44 24 1f lea 0x1f(%rsp),%rax + 41d034: 48 2b 04 24 sub (%rsp),%rax + 41d038: 4c 8b 44 24 08 mov 0x8(%rsp),%r8 + 41d03d: 44 8b 54 24 1c mov 0x1c(%rsp),%r10d + 41d042: 4c 8b 4c 24 10 mov 0x10(%rsp),%r9 + 41d047: 49 01 c0 add %rax,%r8 + 41d04a: 48 8b 05 6f 02 2b 00 mov 0x2b026f(%rip),%rax # 6cd2c0 <__libc_argv> + 41d051: 44 89 d7 mov %r10d,%edi + 41d054: ba 38 20 4a 00 mov $0x4a2038,%edx + 41d059: b9 78 20 4a 00 mov $0x4a2078,%ecx + 41d05e: be a8 23 4a 00 mov $0x4a23a8,%esi + 41d063: 4c 89 0c 24 mov %r9,(%rsp) + 41d067: 48 8b 00 mov (%rax),%rax + 41d06a: 48 85 c0 test %rax,%rax + 41d06d: 48 0f 45 d0 cmovne %rax,%rdx + 41d071: 83 e7 02 and $0x2,%edi + 41d074: 31 c0 xor %eax,%eax + 41d076: e8 45 45 ff ff callq 4115c0 <__libc_message> + 41d07b: 4c 8b 0c 24 mov (%rsp),%r9 + 41d07f: e9 ba fa ff ff jmpq 41cb3e <_int_realloc+0xde> + 41d084: 44 89 d7 mov %r10d,%edi + 41d087: ba 95 20 4a 00 mov $0x4a2095,%edx + 41d08c: be 3c ca 4b 00 mov $0x4bca3c,%esi + 41d091: 83 e7 02 and $0x2,%edi + 41d094: 31 c0 xor %eax,%eax + 41d096: 4c 89 0c 24 mov %r9,(%rsp) + 41d09a: e8 21 45 ff ff callq 4115c0 <__libc_message> + 41d09f: 4c 8b 0c 24 mov (%rsp),%r9 + 41d0a3: e9 08 fb ff ff jmpq 41cbb0 <_int_realloc+0x150> + 41d0a8: 44 89 d7 mov %r10d,%edi + 41d0ab: ba 78 20 4a 00 mov $0x4a2078,%edx + 41d0b0: be 3c ca 4b 00 mov $0x4bca3c,%esi + 41d0b5: 83 e7 02 and $0x2,%edi + 41d0b8: 31 c0 xor %eax,%eax + 41d0ba: 4c 89 0c 24 mov %r9,(%rsp) + 41d0be: e8 fd 44 ff ff callq 4115c0 <__libc_message> + 41d0c3: 4c 8b 0c 24 mov (%rsp),%r9 + 41d0c7: e9 72 fa ff ff jmpq 41cb3e <_int_realloc+0xde> + 41d0cc: 8b 3d 9e d6 2a 00 mov 0x2ad69e(%rip),%edi # 6ca770 + 41d0d2: 48 89 e9 mov %rbp,%rcx + 41d0d5: 4c 89 fa mov %r15,%rdx + 41d0d8: be f0 23 4a 00 mov $0x4a23f0,%esi + 41d0dd: 4c 89 0c 24 mov %r9,(%rsp) + 41d0e1: e8 ca a1 ff ff callq 4172b0 + 41d0e6: 49 8b 47 20 mov 0x20(%r15),%rax + 41d0ea: 4c 8b 0c 24 mov (%rsp),%r9 + 41d0ee: e9 9a fa ff ff jmpq 41cb8d <_int_realloc+0x12d> + 41d0f3: 49 39 c7 cmp %rax,%r15 + 41d0f6: 74 6c je 41d164 <_int_realloc+0x704> + 41d0f8: 49 89 46 20 mov %rax,0x20(%r14) + 41d0fc: 49 8b 47 28 mov 0x28(%r15),%rax + 41d100: 49 89 46 28 mov %rax,0x28(%r14) + 41d104: 49 8b 47 20 mov 0x20(%r15),%rax + 41d108: 4c 89 70 28 mov %r14,0x28(%rax) + 41d10c: 49 8b 47 28 mov 0x28(%r15),%rax + 41d110: 4c 89 70 20 mov %r14,0x20(%rax) + 41d114: e9 97 fa ff ff jmpq 41cbb0 <_int_realloc+0x150> + 41d119: b9 58 2e 4a 00 mov $0x4a2e58,%ecx + 41d11e: ba a3 10 00 00 mov $0x10a3,%edx + 41d123: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 41d128: bf a0 21 4a 00 mov $0x4a21a0,%edi + 41d12d: e8 ee 9c ff ff callq 416e20 <__malloc_assert> + 41d132: b9 58 2e 4a 00 mov $0x4a2e58,%ecx + 41d137: ba 0f 11 00 00 mov $0x110f,%edx + 41d13c: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 41d141: bf 20 29 4a 00 mov $0x4a2920,%edi + 41d146: e8 d5 9c ff ff callq 416e20 <__malloc_assert> + 41d14b: b9 58 2e 4a 00 mov $0x4a2e58,%ecx + 41d150: ba eb 10 00 00 mov $0x10eb,%edx + 41d155: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 41d15a: bf b9 21 4a 00 mov $0x4a21b9,%edi + 41d15f: e8 bc 9c ff ff callq 416e20 <__malloc_assert> + 41d164: 4d 89 76 28 mov %r14,0x28(%r14) + 41d168: 4d 89 76 20 mov %r14,0x20(%r14) + 41d16c: e9 3f fa ff ff jmpq 41cbb0 <_int_realloc+0x150> + 41d171: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41d176: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41d17d: 00 00 00 + +000000000041d180 : + 41d180: 41 57 push %r15 + 41d182: 41 56 push %r14 + 41d184: 41 55 push %r13 + 41d186: 41 54 push %r12 + 41d188: 55 push %rbp + 41d189: 53 push %rbx + 41d18a: 48 83 ec 48 sub $0x48,%rsp + 41d18e: 48 83 fe ff cmp $0xffffffffffffffff,%rsi + 41d192: 0f 84 98 04 00 00 je 41d630 + 41d198: 48 85 ff test %rdi,%rdi + 41d19b: 48 89 fd mov %rdi,%rbp + 41d19e: 48 89 f3 mov %rsi,%rbx + 41d1a1: 0f 84 49 05 00 00 je 41d6f0 + 41d1a7: 48 85 f6 test %rsi,%rsi + 41d1aa: 0f 84 b0 04 00 00 je 41d660 + 41d1b0: be 01 00 00 00 mov $0x1,%esi + 41d1b5: 31 c0 xor %eax,%eax + 41d1b7: 83 3d fe ff 2a 00 00 cmpl $0x0,0x2afffe(%rip) # 6cd1bc <__libc_multiple_threads> + 41d1be: 74 0c je 41d1cc + 41d1c0: f0 0f b1 35 38 d6 2a lock cmpxchg %esi,0x2ad638(%rip) # 6ca800 + 41d1c7: 00 + 41d1c8: 75 0b jne 41d1d5 + 41d1ca: eb 23 jmp 41d1ef + 41d1cc: 0f b1 35 2d d6 2a 00 cmpxchg %esi,0x2ad62d(%rip) # 6ca800 + 41d1d3: 74 1a je 41d1ef + 41d1d5: 48 8d 3d 24 d6 2a 00 lea 0x2ad624(%rip),%rdi # 6ca800 + 41d1dc: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41d1e3: e8 e8 53 02 00 callq 4425d0 <__lll_lock_wait_private> + 41d1e8: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41d1ef: 40 f6 c5 0f test $0xf,%bpl + 41d1f3: 0f 85 37 01 00 00 jne 41d330 + 41d1f9: 48 8d 7d f0 lea -0x10(%rbp),%rdi + 41d1fd: 48 8b 45 f8 mov -0x8(%rbp),%rax + 41d201: 48 89 fe mov %rdi,%rsi + 41d204: 48 89 f9 mov %rdi,%rcx + 41d207: 48 c1 e9 0b shr $0xb,%rcx + 41d20b: 48 c1 ee 03 shr $0x3,%rsi + 41d20f: 48 89 c2 mov %rax,%rdx + 41d212: 31 ce xor %ecx,%esi + 41d214: 48 83 e2 f8 and $0xfffffffffffffff8,%rdx + 41d218: b9 02 00 00 00 mov $0x2,%ecx + 41d21d: 40 80 fe 01 cmp $0x1,%sil + 41d221: 0f 44 f1 cmove %ecx,%esi + 41d224: a8 02 test $0x2,%al + 41d226: 0f 84 d4 02 00 00 je 41d500 + 41d22c: 48 8b 05 4d df 2a 00 mov 0x2adf4d(%rip),%rax # 6cb180 <_dl_pagesize> + 41d233: 48 8d 48 ff lea -0x1(%rax),%rcx + 41d237: 48 89 e8 mov %rbp,%rax + 41d23a: 48 21 c8 and %rcx,%rax + 41d23d: 4c 8d 40 f0 lea -0x10(%rax),%r8 + 41d241: 49 f7 c0 ef ff ff ff test $0xffffffffffffffef,%r8 + 41d248: 74 36 je 41d280 + 41d24a: 4c 8d 40 ff lea -0x1(%rax),%r8 + 41d24e: 49 81 f8 fe 1f 00 00 cmp $0x1ffe,%r8 + 41d255: 77 29 ja 41d280 + 41d257: 4c 8d 40 c0 lea -0x40(%rax),%r8 + 41d25b: 49 f7 c0 bf ff ff ff test $0xffffffffffffffbf,%r8 + 41d262: 74 1c je 41d280 + 41d264: 4c 8d 80 00 ff ff ff lea -0x100(%rax),%r8 + 41d26b: 49 f7 c0 ff fe ff ff test $0xfffffffffffffeff,%r8 + 41d272: 0f 85 90 00 00 00 jne 41d308 + 41d278: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 41d27f: 00 + 41d280: 48 8b 45 f8 mov -0x8(%rbp),%rax + 41d284: 45 31 ed xor %r13d,%r13d + 41d287: 83 e0 03 and $0x3,%eax + 41d28a: 48 83 f8 02 cmp $0x2,%rax + 41d28e: 0f 85 9f 00 00 00 jne 41d333 + 41d294: 48 8b 45 f0 mov -0x10(%rbp),%rax + 41d298: 49 89 f8 mov %rdi,%r8 + 41d29b: 49 29 c0 sub %rax,%r8 + 41d29e: 48 01 d0 add %rdx,%rax + 41d2a1: 4c 09 c0 or %r8,%rax + 41d2a4: 48 85 c8 test %rcx,%rax + 41d2a7: 0f 85 86 00 00 00 jne 41d333 + 41d2ad: 48 83 ea 01 sub $0x1,%rdx + 41d2b1: 40 0f b6 f6 movzbl %sil,%esi + 41d2b5: 4c 8d 04 17 lea (%rdi,%rdx,1),%r8 + 41d2b9: 41 0f b6 00 movzbl (%r8),%eax + 41d2bd: 48 39 f0 cmp %rsi,%rax + 41d2c0: 48 89 c1 mov %rax,%rcx + 41d2c3: 74 34 je 41d2f9 + 41d2c5: 48 85 c0 test %rax,%rax + 41d2c8: 74 69 je 41d333 + 41d2ca: 48 8d 48 10 lea 0x10(%rax),%rcx + 41d2ce: 48 39 ca cmp %rcx,%rdx + 41d2d1: 73 13 jae 41d2e6 + 41d2d3: eb 5e jmp 41d333 + 41d2d5: 0f 1f 00 nopl (%rax) + 41d2d8: 48 85 c0 test %rax,%rax + 41d2db: 74 53 je 41d330 + 41d2dd: 48 8d 48 10 lea 0x10(%rax),%rcx + 41d2e1: 48 39 d1 cmp %rdx,%rcx + 41d2e4: 77 4a ja 41d330 + 41d2e6: 48 29 c2 sub %rax,%rdx + 41d2e9: 4c 8d 04 17 lea (%rdi,%rdx,1),%r8 + 41d2ed: 41 0f b6 00 movzbl (%r8),%eax + 41d2f1: 48 39 f0 cmp %rsi,%rax + 41d2f4: 48 89 c1 mov %rax,%rcx + 41d2f7: 75 df jne 41d2d8 + 41d2f9: f7 d1 not %ecx + 41d2fb: 4c 89 44 24 18 mov %r8,0x18(%rsp) + 41d300: 49 89 fd mov %rdi,%r13 + 41d303: 41 88 08 mov %cl,(%r8) + 41d306: eb 2b jmp 41d333 + 41d308: 4c 8d 80 00 fc ff ff lea -0x400(%rax),%r8 + 41d30f: 49 f7 c0 ff fb ff ff test $0xfffffffffffffbff,%r8 + 41d316: 0f 84 64 ff ff ff je 41d280 + 41d31c: 48 3d 00 10 00 00 cmp $0x1000,%rax + 41d322: 0f 84 58 ff ff ff je 41d280 + 41d328: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 41d32f: 00 + 41d330: 45 31 ed xor %r13d,%r13d + 41d333: 83 3d 82 fe 2a 00 00 cmpl $0x0,0x2afe82(%rip) # 6cd1bc <__libc_multiple_threads> + 41d33a: 74 0b je 41d347 + 41d33c: f0 ff 0d bd d4 2a 00 lock decl 0x2ad4bd(%rip) # 6ca800 + 41d343: 75 0a jne 41d34f + 41d345: eb 22 jmp 41d369 + 41d347: ff 0d b3 d4 2a 00 decl 0x2ad4b3(%rip) # 6ca800 + 41d34d: 74 1a je 41d369 + 41d34f: 48 8d 3d aa d4 2a 00 lea 0x2ad4aa(%rip),%rdi # 6ca800 + 41d356: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41d35d: e8 9e 52 02 00 callq 442600 <__lll_unlock_wake_private> + 41d362: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41d369: 4d 85 ed test %r13,%r13 + 41d36c: 0f 84 06 04 00 00 je 41d778 + 41d372: 4d 8b 75 08 mov 0x8(%r13),%r14 + 41d376: 4c 8d 4b 01 lea 0x1(%rbx),%r9 + 41d37a: 4c 89 4c 24 08 mov %r9,0x8(%rsp) + 41d37f: 49 83 e6 f8 and $0xfffffffffffffff8,%r14 + 41d383: 49 83 f9 bf cmp $0xffffffffffffffbf,%r9 + 41d387: 0f 87 a3 02 00 00 ja 41d630 + 41d38d: 4c 8d 7b 18 lea 0x18(%rbx),%r15 + 41d391: 41 bc 20 00 00 00 mov $0x20,%r12d + 41d397: be 01 00 00 00 mov $0x1,%esi + 41d39c: 4d 89 e2 mov %r12,%r10 + 41d39f: 4c 89 fa mov %r15,%rdx + 41d3a2: 48 83 e2 f0 and $0xfffffffffffffff0,%rdx + 41d3a6: 49 83 ff 20 cmp $0x20,%r15 + 41d3aa: 4c 0f 43 d2 cmovae %rdx,%r10 + 41d3ae: 31 c0 xor %eax,%eax + 41d3b0: 83 3d 05 fe 2a 00 00 cmpl $0x0,0x2afe05(%rip) # 6cd1bc <__libc_multiple_threads> + 41d3b7: 74 0c je 41d3c5 + 41d3b9: f0 0f b1 35 3f d4 2a lock cmpxchg %esi,0x2ad43f(%rip) # 6ca800 + 41d3c0: 00 + 41d3c1: 75 0b jne 41d3ce + 41d3c3: eb 23 jmp 41d3e8 + 41d3c5: 0f b1 35 34 d4 2a 00 cmpxchg %esi,0x2ad434(%rip) # 6ca800 + 41d3cc: 74 1a je 41d3e8 + 41d3ce: 48 8d 3d 2b d4 2a 00 lea 0x2ad42b(%rip),%rdi # 6ca800 + 41d3d5: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41d3dc: e8 ef 51 02 00 callq 4425d0 <__lll_lock_wait_private> + 41d3e1: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41d3e8: 41 f6 45 08 02 testb $0x2,0x8(%r13) + 41d3ed: 0f 85 dd 01 00 00 jne 41d5d0 + 41d3f3: 48 89 54 24 08 mov %rdx,0x8(%rsp) + 41d3f8: e8 e3 a6 ff ff callq 417ae0 + 41d3fd: 85 c0 test %eax,%eax + 41d3ff: 0f 88 4b 02 00 00 js 41d650 + 41d405: 48 8b 54 24 08 mov 0x8(%rsp),%rdx + 41d40a: 49 83 ff 20 cmp $0x20,%r15 + 41d40e: 4c 89 e1 mov %r12,%rcx + 41d411: 4c 89 ee mov %r13,%rsi + 41d414: bf 00 a8 6c 00 mov $0x6ca800,%edi + 41d419: 48 0f 43 ca cmovae %rdx,%rcx + 41d41d: 4c 89 f2 mov %r14,%rdx + 41d420: e8 3b f6 ff ff callq 41ca60 <_int_realloc> + 41d425: 48 89 c5 mov %rax,%rbp + 41d428: 48 85 ed test %rbp,%rbp + 41d42b: 0f 84 1f 02 00 00 je 41d650 + 41d431: 83 3d 84 fd 2a 00 00 cmpl $0x0,0x2afd84(%rip) # 6cd1bc <__libc_multiple_threads> + 41d438: 74 0b je 41d445 + 41d43a: f0 ff 0d bf d3 2a 00 lock decl 0x2ad3bf(%rip) # 6ca800 + 41d441: 75 0a jne 41d44d + 41d443: eb 22 jmp 41d467 + 41d445: ff 0d b5 d3 2a 00 decl 0x2ad3b5(%rip) # 6ca800 + 41d44b: 74 1a je 41d467 + 41d44d: 48 8d 3d ac d3 2a 00 lea 0x2ad3ac(%rip),%rdi # 6ca800 + 41d454: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41d45b: e8 a0 51 02 00 callq 442600 <__lll_unlock_wake_private> + 41d460: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41d467: 48 85 ed test %rbp,%rbp + 41d46a: 0f 84 90 02 00 00 je 41d700 + 41d470: 48 8d 45 f0 lea -0x10(%rbp),%rax + 41d474: be ff 00 00 00 mov $0xff,%esi + 41d479: 49 89 c0 mov %rax,%r8 + 41d47c: 48 c1 e8 0b shr $0xb,%rax + 41d480: 49 c1 e8 03 shr $0x3,%r8 + 41d484: 41 31 c0 xor %eax,%r8d + 41d487: b8 02 00 00 00 mov $0x2,%eax + 41d48c: 41 80 f8 01 cmp $0x1,%r8b + 41d490: 44 0f 44 c0 cmove %eax,%r8d + 41d494: 48 8b 45 f8 mov -0x8(%rbp),%rax + 41d498: 41 0f b6 f8 movzbl %r8b,%edi + 41d49c: 48 89 c2 mov %rax,%rdx + 41d49f: 48 83 e2 f8 and $0xfffffffffffffff8,%rdx + 41d4a3: 48 8d 4a f0 lea -0x10(%rdx),%rcx + 41d4a7: 48 83 ea 08 sub $0x8,%rdx + 41d4ab: a8 02 test $0x2,%al + 41d4ad: 48 0f 44 ca cmove %rdx,%rcx + 41d4b1: 48 83 e9 01 sub $0x1,%rcx + 41d4b5: 48 39 cb cmp %rcx,%rbx + 41d4b8: 73 2e jae 41d4e8 + 41d4ba: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 41d4c0: 48 89 ca mov %rcx,%rdx + 41d4c3: 48 29 da sub %rbx,%rdx + 41d4c6: 48 81 fa ff 00 00 00 cmp $0xff,%rdx + 41d4cd: 48 0f 47 d6 cmova %rsi,%rdx + 41d4d1: 48 8d 42 ff lea -0x1(%rdx),%rax + 41d4d5: 48 39 fa cmp %rdi,%rdx + 41d4d8: 48 0f 44 d0 cmove %rax,%rdx + 41d4dc: 88 54 0d 00 mov %dl,0x0(%rbp,%rcx,1) + 41d4e0: 48 29 d1 sub %rdx,%rcx + 41d4e3: 48 39 cb cmp %rcx,%rbx + 41d4e6: 72 d8 jb 41d4c0 + 41d4e8: 44 88 44 1d 00 mov %r8b,0x0(%rbp,%rbx,1) + 41d4ed: 48 89 e8 mov %rbp,%rax + 41d4f0: 48 83 c4 48 add $0x48,%rsp + 41d4f4: 5b pop %rbx + 41d4f5: 5d pop %rbp + 41d4f6: 41 5c pop %r12 + 41d4f8: 41 5d pop %r13 + 41d4fa: 41 5e pop %r14 + 41d4fc: 41 5f pop %r15 + 41d4fe: c3 retq + 41d4ff: 90 nop + 41d500: 8b 0d fe d2 2a 00 mov 0x2ad2fe(%rip),%ecx # 6ca804 + 41d506: 83 e1 02 and $0x2,%ecx + 41d509: 0f 84 f1 00 00 00 je 41d600 + 41d50f: 48 83 fa 1f cmp $0x1f,%rdx + 41d513: 0f 86 17 fe ff ff jbe 41d330 + 41d519: a8 08 test $0x8,%al + 41d51b: 0f 85 0f fe ff ff jne 41d330 + 41d521: f6 44 17 08 01 testb $0x1,0x8(%rdi,%rdx,1) + 41d526: 0f 84 04 fe ff ff je 41d330 + 41d52c: a8 01 test $0x1,%al + 41d52e: 75 2e jne 41d55e + 41d530: 48 8b 45 f0 mov -0x10(%rbp),%rax + 41d534: a8 0f test $0xf,%al + 41d536: 0f 85 f4 fd ff ff jne 41d330 + 41d53c: 85 c9 test %ecx,%ecx + 41d53e: 48 89 f9 mov %rdi,%rcx + 41d541: 0f 84 c0 01 00 00 je 41d707 + 41d547: 48 29 c1 sub %rax,%rcx + 41d54a: 48 8b 49 08 mov 0x8(%rcx),%rcx + 41d54e: 45 31 ed xor %r13d,%r13d + 41d551: 48 83 e1 f8 and $0xfffffffffffffff8,%rcx + 41d555: 48 39 c8 cmp %rcx,%rax + 41d558: 0f 85 d5 fd ff ff jne 41d333 + 41d55e: 48 83 c2 07 add $0x7,%rdx + 41d562: 40 0f b6 f6 movzbl %sil,%esi + 41d566: 4c 8d 04 17 lea (%rdi,%rdx,1),%r8 + 41d56a: 41 0f b6 00 movzbl (%r8),%eax + 41d56e: 48 39 c6 cmp %rax,%rsi + 41d571: 48 89 c1 mov %rax,%rcx + 41d574: 0f 84 7f fd ff ff je 41d2f9 + 41d57a: 48 85 c0 test %rax,%rax + 41d57d: 0f 84 ad fd ff ff je 41d330 + 41d583: 48 8d 48 10 lea 0x10(%rax),%rcx + 41d587: 48 39 ca cmp %rcx,%rdx + 41d58a: 73 22 jae 41d5ae + 41d58c: e9 9f fd ff ff jmpq 41d330 + 41d591: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 41d598: 48 85 c0 test %rax,%rax + 41d59b: 0f 84 8f fd ff ff je 41d330 + 41d5a1: 48 8d 48 10 lea 0x10(%rax),%rcx + 41d5a5: 48 39 d1 cmp %rdx,%rcx + 41d5a8: 0f 87 82 fd ff ff ja 41d330 + 41d5ae: 48 29 c2 sub %rax,%rdx + 41d5b1: 4c 8d 04 17 lea (%rdi,%rdx,1),%r8 + 41d5b5: 41 0f b6 00 movzbl (%r8),%eax + 41d5b9: 48 39 c6 cmp %rax,%rsi + 41d5bc: 48 89 c1 mov %rax,%rcx + 41d5bf: 75 d7 jne 41d598 + 41d5c1: e9 33 fd ff ff jmpq 41d2f9 + 41d5c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41d5cd: 00 00 00 + 41d5d0: 4c 89 d6 mov %r10,%rsi + 41d5d3: 4c 89 ef mov %r13,%rdi + 41d5d6: 4c 89 54 24 10 mov %r10,0x10(%rsp) + 41d5db: e8 40 9a ff ff callq 417020 + 41d5e0: 48 85 c0 test %rax,%rax + 41d5e3: 4c 8b 54 24 10 mov 0x10(%rsp),%r10 + 41d5e8: 4c 8b 4c 24 08 mov 0x8(%rsp),%r9 + 41d5ed: 0f 84 29 01 00 00 je 41d71c + 41d5f3: 48 8d 68 10 lea 0x10(%rax),%rbp + 41d5f7: e9 2c fe ff ff jmpq 41d428 + 41d5fc: 0f 1f 40 00 nopl 0x0(%rax) + 41d600: 4c 8b 05 e9 d1 2a 00 mov 0x2ad1e9(%rip),%r8 # 6ca7f0 + 41d607: 4c 39 c7 cmp %r8,%rdi + 41d60a: 0f 82 20 fd ff ff jb 41d330 + 41d610: 4c 03 05 69 da 2a 00 add 0x2ada69(%rip),%r8 # 6cb080 + 41d617: 4c 8d 0c 17 lea (%rdi,%rdx,1),%r9 + 41d61b: 4d 39 c1 cmp %r8,%r9 + 41d61e: 0f 82 eb fe ff ff jb 41d50f + 41d624: e9 07 fd ff ff jmpq 41d330 + 41d629: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 41d630: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 41d637: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) + 41d63e: 48 83 c4 48 add $0x48,%rsp + 41d642: 31 c0 xor %eax,%eax + 41d644: 5b pop %rbx + 41d645: 5d pop %rbp + 41d646: 41 5c pop %r12 + 41d648: 41 5d pop %r13 + 41d64a: 41 5e pop %r14 + 41d64c: 41 5f pop %r15 + 41d64e: c3 retq + 41d64f: 90 nop + 41d650: 48 8b 44 24 18 mov 0x18(%rsp),%rax + 41d655: 31 ed xor %ebp,%ebp + 41d657: f6 10 notb (%rax) + 41d659: e9 d3 fd ff ff jmpq 41d431 + 41d65e: 66 90 xchg %ax,%ax + 41d660: 31 f6 xor %esi,%esi + 41d662: e8 79 b3 ff ff callq 4189e0 + 41d667: 31 c0 xor %eax,%eax + 41d669: e9 82 fe ff ff jmpq 41d4f0 + 41d66e: 4c 8d 6c 24 20 lea 0x20(%rsp),%r13 + 41d673: 48 8d 74 24 30 lea 0x30(%rsp),%rsi + 41d678: 31 c9 xor %ecx,%ecx + 41d67a: 48 89 ef mov %rbp,%rdi + 41d67d: ba 10 00 00 00 mov $0x10,%edx + 41d682: c6 44 24 30 00 movb $0x0,0x30(%rsp) + 41d687: e8 24 48 03 00 callq 451eb0 <_itoa_word> + 41d68c: 4c 39 e8 cmp %r13,%rax + 41d68f: 48 89 c5 mov %rax,%rbp + 41d692: 76 25 jbe 41d6b9 + 41d694: 48 89 c2 mov %rax,%rdx + 41d697: 48 89 c7 mov %rax,%rdi + 41d69a: be 30 00 00 00 mov $0x30,%esi + 41d69f: 4c 29 ea sub %r13,%rdx + 41d6a2: 4c 8d 70 ff lea -0x1(%rax),%r14 + 41d6a6: 48 29 d7 sub %rdx,%rdi + 41d6a9: e8 a2 2c fe ff callq 400350 <__rela_iplt_end+0x88> + 41d6ae: 48 8d 44 24 1f lea 0x1f(%rsp),%rax + 41d6b3: 4c 29 f0 sub %r14,%rax + 41d6b6: 48 01 c5 add %rax,%rbp + 41d6b9: 48 8b 05 00 fc 2a 00 mov 0x2afc00(%rip),%rax # 6cd2c0 <__libc_argv> + 41d6c0: ba 38 20 4a 00 mov $0x4a2038,%edx + 41d6c5: 44 89 e7 mov %r12d,%edi + 41d6c8: 49 89 e8 mov %rbp,%r8 + 41d6cb: b9 c6 21 4a 00 mov $0x4a21c6,%ecx + 41d6d0: be a8 23 4a 00 mov $0x4a23a8,%esi + 41d6d5: 48 8b 00 mov (%rax),%rax + 41d6d8: 48 85 c0 test %rax,%rax + 41d6db: 48 0f 45 d0 cmovne %rax,%rdx + 41d6df: 83 e7 02 and $0x2,%edi + 41d6e2: 31 c0 xor %eax,%eax + 41d6e4: e8 d7 3e ff ff callq 4115c0 <__libc_message> + 41d6e9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 41d6f0: 31 f6 xor %esi,%esi + 41d6f2: 48 89 df mov %rbx,%rdi + 41d6f5: e8 26 f0 ff ff callq 41c720 + 41d6fa: e9 f1 fd ff ff jmpq 41d4f0 + 41d6ff: 90 nop + 41d700: 31 c0 xor %eax,%eax + 41d702: e9 e9 fd ff ff jmpq 41d4f0 + 41d707: 48 29 c1 sub %rax,%rcx + 41d70a: 48 3b 0d df d0 2a 00 cmp 0x2ad0df(%rip),%rcx # 6ca7f0 + 41d711: 0f 83 33 fe ff ff jae 41d54a + 41d717: e9 14 fc ff ff jmpq 41d330 + 41d71c: 49 8d 46 f8 lea -0x8(%r14),%rax + 41d720: 49 39 c2 cmp %rax,%r10 + 41d723: 0f 86 08 fd ff ff jbe 41d431 + 41d729: 4c 89 4c 24 08 mov %r9,0x8(%rsp) + 41d72e: e8 ad a3 ff ff callq 417ae0 + 41d733: 85 c0 test %eax,%eax + 41d735: 0f 88 15 ff ff ff js 41d650 + 41d73b: 4c 8b 4c 24 08 mov 0x8(%rsp),%r9 + 41d740: bf 00 a8 6c 00 mov $0x6ca800,%edi + 41d745: 4c 89 ce mov %r9,%rsi + 41d748: e8 f3 dd ff ff callq 41b540 <_int_malloc> + 41d74d: 48 85 c0 test %rax,%rax + 41d750: 49 89 c7 mov %rax,%r15 + 41d753: 0f 84 f7 fe ff ff je 41d650 + 41d759: 49 8d 56 f0 lea -0x10(%r14),%rdx + 41d75d: 48 89 ee mov %rbp,%rsi + 41d760: 48 89 c7 mov %rax,%rdi + 41d763: 4c 89 fd mov %r15,%rbp + 41d766: e8 b5 e8 00 00 callq 42c020 + 41d76b: 4c 89 ef mov %r13,%rdi + 41d76e: e8 7d a5 ff ff callq 417cf0 + 41d773: e9 b9 fc ff ff jmpq 41d431 + 41d778: 44 8b 25 f1 cf 2a 00 mov 0x2acff1(%rip),%r12d # 6ca770 + 41d77f: 83 0d 7e d0 2a 00 04 orl $0x4,0x2ad07e(%rip) # 6ca804 + 41d786: 44 89 e0 mov %r12d,%eax + 41d789: 83 e0 05 and $0x5,%eax + 41d78c: 83 f8 05 cmp $0x5,%eax + 41d78f: 74 1f je 41d7b0 + 41d791: 41 f6 c4 01 test $0x1,%r12b + 41d795: 0f 85 d3 fe ff ff jne 41d66e + 41d79b: 41 83 e4 02 and $0x2,%r12d + 41d79f: 0f 84 4b ff ff ff je 41d6f0 + 41d7a5: e8 56 04 ff ff callq 40dc00 + 41d7aa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 41d7b0: 44 89 e7 mov %r12d,%edi + 41d7b3: ba c6 21 4a 00 mov $0x4a21c6,%edx + 41d7b8: be 3c ca 4b 00 mov $0x4bca3c,%esi + 41d7bd: 83 e7 02 and $0x2,%edi + 41d7c0: 31 c0 xor %eax,%eax + 41d7c2: e8 f9 3d ff ff callq 4115c0 <__libc_message> + 41d7c7: e9 24 ff ff ff jmpq 41d6f0 + 41d7cc: 0f 1f 40 00 nopl 0x0(%rax) + +000000000041d7d0 <__malloc_fork_lock_parent>: + 41d7d0: 8b 05 8e cf 2a 00 mov 0x2acf8e(%rip),%eax # 6ca764 <__libc_malloc_initialized> + 41d7d6: 85 c0 test %eax,%eax + 41d7d8: 0f 8e 94 00 00 00 jle 41d872 <__malloc_fork_lock_parent+0xa2> + 41d7de: be 01 00 00 00 mov $0x1,%esi + 41d7e3: 31 c0 xor %eax,%eax + 41d7e5: 83 3d d0 f9 2a 00 00 cmpl $0x0,0x2af9d0(%rip) # 6cd1bc <__libc_multiple_threads> + 41d7ec: 74 0c je 41d7fa <__malloc_fork_lock_parent+0x2a> + 41d7ee: f0 0f b1 35 2a ee 2a lock cmpxchg %esi,0x2aee2a(%rip) # 6cc620 + 41d7f5: 00 + 41d7f6: 75 0b jne 41d803 <__malloc_fork_lock_parent+0x33> + 41d7f8: eb 23 jmp 41d81d <__malloc_fork_lock_parent+0x4d> + 41d7fa: 0f b1 35 1f ee 2a 00 cmpxchg %esi,0x2aee1f(%rip) # 6cc620 + 41d801: 74 1a je 41d81d <__malloc_fork_lock_parent+0x4d> + 41d803: 48 8d 3d 16 ee 2a 00 lea 0x2aee16(%rip),%rdi # 6cc620 + 41d80a: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41d811: e8 ba 4d 02 00 callq 4425d0 <__lll_lock_wait_private> + 41d816: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41d81d: ba 00 a8 6c 00 mov $0x6ca800,%edx + 41d822: 41 b9 01 00 00 00 mov $0x1,%r9d + 41d828: 45 31 c0 xor %r8d,%r8d + 41d82b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41d830: 44 89 ce mov %r9d,%esi + 41d833: 44 89 c0 mov %r8d,%eax + 41d836: 83 3d 7f f9 2a 00 00 cmpl $0x0,0x2af97f(%rip) # 6cd1bc <__libc_multiple_threads> + 41d83d: 74 08 je 41d847 <__malloc_fork_lock_parent+0x77> + 41d83f: f0 0f b1 32 lock cmpxchg %esi,(%rdx) + 41d843: 75 07 jne 41d84c <__malloc_fork_lock_parent+0x7c> + 41d845: eb 1b jmp 41d862 <__malloc_fork_lock_parent+0x92> + 41d847: 0f b1 32 cmpxchg %esi,(%rdx) + 41d84a: 74 16 je 41d862 <__malloc_fork_lock_parent+0x92> + 41d84c: 48 8d 3a lea (%rdx),%rdi + 41d84f: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41d856: e8 75 4d 02 00 callq 4425d0 <__lll_lock_wait_private> + 41d85b: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41d862: 48 8b 92 68 08 00 00 mov 0x868(%rdx),%rdx + 41d869: 48 81 fa 00 a8 6c 00 cmp $0x6ca800,%rdx + 41d870: 75 be jne 41d830 <__malloc_fork_lock_parent+0x60> + 41d872: f3 c3 repz retq + 41d874: 66 90 xchg %ax,%ax + 41d876: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41d87d: 00 00 00 + +000000000041d880 <__malloc_fork_unlock_parent>: + 41d880: 8b 05 de ce 2a 00 mov 0x2acede(%rip),%eax # 6ca764 <__libc_malloc_initialized> + 41d886: 85 c0 test %eax,%eax + 41d888: 7e 76 jle 41d900 <__malloc_fork_unlock_parent+0x80> + 41d88a: ba 00 a8 6c 00 mov $0x6ca800,%edx + 41d88f: 90 nop + 41d890: 83 3d 25 f9 2a 00 00 cmpl $0x0,0x2af925(%rip) # 6cd1bc <__libc_multiple_threads> + 41d897: 74 07 je 41d8a0 <__malloc_fork_unlock_parent+0x20> + 41d899: f0 ff 0a lock decl (%rdx) + 41d89c: 75 06 jne 41d8a4 <__malloc_fork_unlock_parent+0x24> + 41d89e: eb 1a jmp 41d8ba <__malloc_fork_unlock_parent+0x3a> + 41d8a0: ff 0a decl (%rdx) + 41d8a2: 74 16 je 41d8ba <__malloc_fork_unlock_parent+0x3a> + 41d8a4: 48 8d 3a lea (%rdx),%rdi + 41d8a7: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41d8ae: e8 4d 4d 02 00 callq 442600 <__lll_unlock_wake_private> + 41d8b3: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41d8ba: 48 8b 92 68 08 00 00 mov 0x868(%rdx),%rdx + 41d8c1: 48 81 fa 00 a8 6c 00 cmp $0x6ca800,%rdx + 41d8c8: 75 c6 jne 41d890 <__malloc_fork_unlock_parent+0x10> + 41d8ca: 83 3d eb f8 2a 00 00 cmpl $0x0,0x2af8eb(%rip) # 6cd1bc <__libc_multiple_threads> + 41d8d1: 74 0b je 41d8de <__malloc_fork_unlock_parent+0x5e> + 41d8d3: f0 ff 0d 46 ed 2a 00 lock decl 0x2aed46(%rip) # 6cc620 + 41d8da: 75 0a jne 41d8e6 <__malloc_fork_unlock_parent+0x66> + 41d8dc: eb 22 jmp 41d900 <__malloc_fork_unlock_parent+0x80> + 41d8de: ff 0d 3c ed 2a 00 decl 0x2aed3c(%rip) # 6cc620 + 41d8e4: 74 1a je 41d900 <__malloc_fork_unlock_parent+0x80> + 41d8e6: 48 8d 3d 33 ed 2a 00 lea 0x2aed33(%rip),%rdi # 6cc620 + 41d8ed: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41d8f4: e8 07 4d 02 00 callq 442600 <__lll_unlock_wake_private> + 41d8f9: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41d900: f3 c3 repz retq + 41d902: 0f 1f 40 00 nopl 0x0(%rax) + 41d906: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41d90d: 00 00 00 + +000000000041d910 <__malloc_fork_unlock_child>: + 41d910: 8b 05 4e ce 2a 00 mov 0x2ace4e(%rip),%eax # 6ca764 <__libc_malloc_initialized> + 41d916: 85 c0 test %eax,%eax + 41d918: 0f 8e 85 00 00 00 jle 41d9a3 <__malloc_fork_unlock_child+0x93> + 41d91e: 48 c7 c0 d8 ff ff ff mov $0xffffffffffffffd8,%rax + 41d925: c7 05 01 ed 2a 00 00 movl $0x0,0x2aed01(%rip) # 6cc630 + 41d92c: 00 00 00 + 41d92f: 64 48 8b 08 mov %fs:(%rax),%rcx + 41d933: 48 85 c9 test %rcx,%rcx + 41d936: 74 0b je 41d943 <__malloc_fork_unlock_child+0x33> + 41d938: 48 c7 81 78 08 00 00 movq $0x1,0x878(%rcx) + 41d93f: 01 00 00 00 + 41d943: 48 c7 05 da ec 2a 00 movq $0x0,0x2aecda(%rip) # 6cc628 + 41d94a: 00 00 00 00 + 41d94e: 31 f6 xor %esi,%esi + 41d950: 31 d2 xor %edx,%edx + 41d952: b8 00 a8 6c 00 mov $0x6ca800,%eax + 41d957: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 41d95e: 00 00 + 41d960: 48 39 c8 cmp %rcx,%rax + 41d963: c7 00 00 00 00 00 movl $0x0,(%rax) + 41d969: 74 1a je 41d985 <__malloc_fork_unlock_child+0x75> + 41d96b: 48 89 90 70 08 00 00 mov %rdx,0x870(%rax) + 41d972: 48 c7 80 78 08 00 00 movq $0x0,0x878(%rax) + 41d979: 00 00 00 00 + 41d97d: 48 89 c2 mov %rax,%rdx + 41d980: be 01 00 00 00 mov $0x1,%esi + 41d985: 48 8b 80 68 08 00 00 mov 0x868(%rax),%rax + 41d98c: 48 3d 00 a8 6c 00 cmp $0x6ca800,%rax + 41d992: 75 cc jne 41d960 <__malloc_fork_unlock_child+0x50> + 41d994: 40 84 f6 test %sil,%sil + 41d997: 75 0c jne 41d9a5 <__malloc_fork_unlock_child+0x95> + 41d999: c7 05 7d ec 2a 00 00 movl $0x0,0x2aec7d(%rip) # 6cc620 + 41d9a0: 00 00 00 + 41d9a3: f3 c3 repz retq + 41d9a5: 48 89 15 7c ec 2a 00 mov %rdx,0x2aec7c(%rip) # 6cc628 + 41d9ac: eb eb jmp 41d999 <__malloc_fork_unlock_child+0x89> + 41d9ae: 66 90 xchg %ax,%ax + +000000000041d9b0 <__malloc_check_init>: + 41d9b0: 8b 05 52 ec 2a 00 mov 0x2aec52(%rip),%eax # 6cc608 + 41d9b6: 85 c0 test %eax,%eax + 41d9b8: 75 3e jne 41d9f8 <__malloc_check_init+0x48> + 41d9ba: c7 05 48 ec 2a 00 01 movl $0x1,0x2aec48(%rip) # 6cc60c + 41d9c1: 00 00 00 + 41d9c4: 48 c7 05 b9 cd 2a 00 movq $0x41c720,0x2acdb9(%rip) # 6ca788 <__malloc_hook> + 41d9cb: 20 c7 41 00 + 41d9cf: 48 c7 05 0e ec 2a 00 movq $0x4189e0,0x2aec0e(%rip) # 6cc5e8 <__free_hook> + 41d9d6: e0 89 41 00 + 41d9da: 48 c7 05 9b cd 2a 00 movq $0x41d180,0x2acd9b(%rip) # 6ca780 <__realloc_hook> + 41d9e1: 80 d1 41 00 + 41d9e5: 48 c7 05 88 cd 2a 00 movq $0x41c870,0x2acd88(%rip) # 6ca778 <__memalign_hook> + 41d9ec: 70 c8 41 00 + 41d9f0: c3 retq + 41d9f1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 41d9f8: c7 05 06 ec 2a 00 00 movl $0x0,0x2aec06(%rip) # 6cc608 + 41d9ff: 00 00 00 + 41da02: c3 retq + 41da03: 0f 1f 00 nopl (%rax) + 41da06: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41da0d: 00 00 00 + +000000000041da10 <__libc_malloc>: + 41da10: 55 push %rbp + 41da11: 53 push %rbx + 41da12: 48 83 ec 08 sub $0x8,%rsp + 41da16: 48 8b 05 6b cd 2a 00 mov 0x2acd6b(%rip),%rax # 6ca788 <__malloc_hook> + 41da1d: 48 85 c0 test %rax,%rax + 41da20: 0f 85 42 01 00 00 jne 41db68 <__libc_malloc+0x158> + 41da26: 48 c7 c0 d8 ff ff ff mov $0xffffffffffffffd8,%rax + 41da2d: 48 89 fd mov %rdi,%rbp + 41da30: 64 48 8b 18 mov %fs:(%rax),%rbx + 41da34: 48 85 db test %rbx,%rbx + 41da37: 74 0c je 41da45 <__libc_malloc+0x35> + 41da39: 8b 43 04 mov 0x4(%rbx),%eax + 41da3c: 83 e0 04 and $0x4,%eax + 41da3f: 0f 84 93 00 00 00 je 41dad8 <__libc_malloc+0xc8> + 41da45: e8 16 97 ff ff callq 417160 + 41da4a: 48 85 c0 test %rax,%rax + 41da4d: 48 89 c3 mov %rax,%rbx + 41da50: 0f 84 ba 00 00 00 je 41db10 <__libc_malloc+0x100> + 41da56: 48 89 ee mov %rbp,%rsi + 41da59: 48 89 df mov %rbx,%rdi + 41da5c: e8 df da ff ff callq 41b540 <_int_malloc> + 41da61: 48 85 c0 test %rax,%rax + 41da64: 48 89 c2 mov %rax,%rdx + 41da67: 0f 84 cb 00 00 00 je 41db38 <__libc_malloc+0x128> + 41da6d: 83 3d 48 f7 2a 00 00 cmpl $0x0,0x2af748(%rip) # 6cd1bc <__libc_multiple_threads> + 41da74: 74 07 je 41da7d <__libc_malloc+0x6d> + 41da76: f0 ff 0b lock decl (%rbx) + 41da79: 75 06 jne 41da81 <__libc_malloc+0x71> + 41da7b: eb 1a jmp 41da97 <__libc_malloc+0x87> + 41da7d: ff 0b decl (%rbx) + 41da7f: 74 16 je 41da97 <__libc_malloc+0x87> + 41da81: 48 8d 3b lea (%rbx),%rdi + 41da84: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41da8b: e8 70 4b 02 00 callq 442600 <__lll_unlock_wake_private> + 41da90: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41da97: 48 85 d2 test %rdx,%rdx + 41da9a: 0f 84 d8 00 00 00 je 41db78 <__libc_malloc+0x168> + 41daa0: 48 8b 42 f8 mov -0x8(%rdx),%rax + 41daa4: a8 02 test $0x2,%al + 41daa6: 75 1f jne 41dac7 <__libc_malloc+0xb7> + 41daa8: a8 04 test $0x4,%al + 41daaa: b9 00 a8 6c 00 mov $0x6ca800,%ecx + 41daaf: 74 0d je 41dabe <__libc_malloc+0xae> + 41dab1: 48 8d 42 f0 lea -0x10(%rdx),%rax + 41dab5: 48 25 00 00 00 fc and $0xfffffffffc000000,%rax + 41dabb: 48 8b 08 mov (%rax),%rcx + 41dabe: 48 39 d9 cmp %rbx,%rcx + 41dac1: 0f 85 b8 00 00 00 jne 41db7f <__libc_malloc+0x16f> + 41dac7: 48 89 d0 mov %rdx,%rax + 41daca: 48 83 c4 08 add $0x8,%rsp + 41dace: 5b pop %rbx + 41dacf: 5d pop %rbp + 41dad0: c3 retq + 41dad1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 41dad8: be 01 00 00 00 mov $0x1,%esi + 41dadd: 83 3d d8 f6 2a 00 00 cmpl $0x0,0x2af6d8(%rip) # 6cd1bc <__libc_multiple_threads> + 41dae4: 74 08 je 41daee <__libc_malloc+0xde> + 41dae6: f0 0f b1 33 lock cmpxchg %esi,(%rbx) + 41daea: 75 07 jne 41daf3 <__libc_malloc+0xe3> + 41daec: eb 1b jmp 41db09 <__libc_malloc+0xf9> + 41daee: 0f b1 33 cmpxchg %esi,(%rbx) + 41daf1: 74 16 je 41db09 <__libc_malloc+0xf9> + 41daf3: 48 8d 3b lea (%rbx),%rdi + 41daf6: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41dafd: e8 ce 4a 02 00 callq 4425d0 <__lll_lock_wait_private> + 41db02: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41db09: e9 48 ff ff ff jmpq 41da56 <__libc_malloc+0x46> + 41db0e: 66 90 xchg %ax,%ax + 41db10: 31 f6 xor %esi,%esi + 41db12: 48 89 ef mov %rbp,%rdi + 41db15: e8 36 99 ff ff callq 417450 + 41db1a: 48 89 ee mov %rbp,%rsi + 41db1d: 48 89 c7 mov %rax,%rdi + 41db20: 48 89 c3 mov %rax,%rbx + 41db23: e8 18 da ff ff callq 41b540 <_int_malloc> + 41db28: 48 85 c0 test %rax,%rax + 41db2b: 48 89 c2 mov %rax,%rdx + 41db2e: 75 25 jne 41db55 <__libc_malloc+0x145> + 41db30: 48 85 db test %rbx,%rbx + 41db33: 74 20 je 41db55 <__libc_malloc+0x145> + 41db35: 0f 1f 00 nopl (%rax) + 41db38: 90 nop + 41db39: 48 89 df mov %rbx,%rdi + 41db3c: 48 89 ee mov %rbp,%rsi + 41db3f: e8 ac 9e ff ff callq 4179f0 + 41db44: 48 89 ee mov %rbp,%rsi + 41db47: 48 89 c7 mov %rax,%rdi + 41db4a: 48 89 c3 mov %rax,%rbx + 41db4d: e8 ee d9 ff ff callq 41b540 <_int_malloc> + 41db52: 48 89 c2 mov %rax,%rdx + 41db55: 48 85 db test %rbx,%rbx + 41db58: 0f 85 0f ff ff ff jne 41da6d <__libc_malloc+0x5d> + 41db5e: e9 34 ff ff ff jmpq 41da97 <__libc_malloc+0x87> + 41db63: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41db68: 48 8b 74 24 18 mov 0x18(%rsp),%rsi + 41db6d: 48 83 c4 08 add $0x8,%rsp + 41db71: 5b pop %rbx + 41db72: 5d pop %rbp + 41db73: ff e0 jmpq *%rax + 41db75: 0f 1f 00 nopl (%rax) + 41db78: 31 c0 xor %eax,%eax + 41db7a: e9 4b ff ff ff jmpq 41daca <__libc_malloc+0xba> + 41db7f: b9 48 2e 4a 00 mov $0x4a2e48,%ecx + 41db84: ba 6f 0b 00 00 mov $0xb6f,%edx + 41db89: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 41db8e: bf 58 29 4a 00 mov $0x4a2958,%edi + 41db93: e8 88 92 ff ff callq 416e20 <__malloc_assert> + 41db98: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 41db9f: 00 + +000000000041dba0 <__malloc_get_state>: + 41dba0: 53 push %rbx + 41dba1: bf a8 08 00 00 mov $0x8a8,%edi + 41dba6: e8 65 fe ff ff callq 41da10 <__libc_malloc> + 41dbab: 48 85 c0 test %rax,%rax + 41dbae: 0f 84 f5 01 00 00 je 41dda9 <__malloc_get_state+0x209> + 41dbb4: 48 89 c3 mov %rax,%rbx + 41dbb7: be 01 00 00 00 mov $0x1,%esi + 41dbbc: 31 c0 xor %eax,%eax + 41dbbe: 83 3d f7 f5 2a 00 00 cmpl $0x0,0x2af5f7(%rip) # 6cd1bc <__libc_multiple_threads> + 41dbc5: 74 0c je 41dbd3 <__malloc_get_state+0x33> + 41dbc7: f0 0f b1 35 31 cc 2a lock cmpxchg %esi,0x2acc31(%rip) # 6ca800 + 41dbce: 00 + 41dbcf: 75 0b jne 41dbdc <__malloc_get_state+0x3c> + 41dbd1: eb 23 jmp 41dbf6 <__malloc_get_state+0x56> + 41dbd3: 0f b1 35 26 cc 2a 00 cmpxchg %esi,0x2acc26(%rip) # 6ca800 + 41dbda: 74 1a je 41dbf6 <__malloc_get_state+0x56> + 41dbdc: 48 8d 3d 1d cc 2a 00 lea 0x2acc1d(%rip),%rdi # 6ca800 + 41dbe3: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41dbea: e8 e1 49 02 00 callq 4425d0 <__lll_lock_wait_private> + 41dbef: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41dbf6: bf 00 a8 6c 00 mov $0x6ca800,%edi + 41dbfb: e8 30 a2 ff ff callq 417e30 + 41dc00: 48 8b 05 51 cc 2a 00 mov 0x2acc51(%rip),%rax # 6ca858 + 41dc07: 48 c7 03 41 45 4c 44 movq $0x444c4541,(%rbx) + 41dc0e: ba 58 a8 6c 00 mov $0x6ca858,%edx + 41dc13: 48 c7 43 08 04 00 00 movq $0x4,0x8(%rbx) + 41dc1a: 00 + 41dc1b: 48 c7 43 10 00 00 00 movq $0x0,0x10(%rbx) + 41dc22: 00 + 41dc23: 48 8d 4b 38 lea 0x38(%rbx),%rcx + 41dc27: 48 c7 43 18 00 00 00 movq $0x0,0x18(%rbx) + 41dc2e: 00 + 41dc2f: 48 c7 43 28 00 00 00 movq $0x0,0x28(%rbx) + 41dc36: 00 + 41dc37: 48 89 43 20 mov %rax,0x20(%rbx) + 41dc3b: eb 1f jmp 41dc5c <__malloc_get_state+0xbc> + 41dc3d: 0f 1f 00 nopl (%rax) + 41dc40: 48 89 71 f8 mov %rsi,-0x8(%rcx) + 41dc44: 48 8b 72 18 mov 0x18(%rdx),%rsi + 41dc48: 48 89 31 mov %rsi,(%rcx) + 41dc4b: 48 83 c2 10 add $0x10,%rdx + 41dc4f: 48 83 c1 10 add $0x10,%rcx + 41dc53: 48 81 fa 48 b0 6c 00 cmp $0x6cb048,%rdx + 41dc5a: 74 24 je 41dc80 <__malloc_get_state+0xe0> + 41dc5c: 48 8b 72 10 mov 0x10(%rdx),%rsi + 41dc60: 48 39 f2 cmp %rsi,%rdx + 41dc63: 75 db jne 41dc40 <__malloc_get_state+0xa0> + 41dc65: 48 c7 01 00 00 00 00 movq $0x0,(%rcx) + 41dc6c: 48 c7 41 f8 00 00 00 movq $0x0,-0x8(%rcx) + 41dc73: 00 + 41dc74: eb d5 jmp 41dc4b <__malloc_get_state+0xab> + 41dc76: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41dc7d: 00 00 00 + 41dc80: 48 8b 05 69 cb 2a 00 mov 0x2acb69(%rip),%rax # 6ca7f0 + 41dc87: 48 89 83 20 08 00 00 mov %rax,0x820(%rbx) + 41dc8e: 48 8b 05 eb d3 2a 00 mov 0x2ad3eb(%rip),%rax # 6cb080 + 41dc95: 89 83 28 08 00 00 mov %eax,0x828(%rbx) + 41dc9b: 48 8b 05 fe ca 2a 00 mov 0x2acafe(%rip),%rax # 6ca7a0 + 41dca2: 48 89 83 30 08 00 00 mov %rax,0x830(%rbx) + 41dca9: 48 8b 05 f8 ca 2a 00 mov 0x2acaf8(%rip),%rax # 6ca7a8 + 41dcb0: 48 89 83 38 08 00 00 mov %rax,0x838(%rbx) + 41dcb7: 8b 05 0f cb 2a 00 mov 0x2acb0f(%rip),%eax # 6ca7cc + 41dcbd: 89 83 40 08 00 00 mov %eax,0x840(%rbx) + 41dcc3: 48 8b 05 e6 ca 2a 00 mov 0x2acae6(%rip),%rax # 6ca7b0 + 41dcca: 48 89 83 48 08 00 00 mov %rax,0x848(%rbx) + 41dcd1: 8b 05 99 ca 2a 00 mov 0x2aca99(%rip),%eax # 6ca770 + 41dcd7: 89 83 50 08 00 00 mov %eax,0x850(%rbx) + 41dcdd: 48 8b 05 a4 d3 2a 00 mov 0x2ad3a4(%rip),%rax # 6cb088 + 41dce4: 48 c7 83 60 08 00 00 movq $0x0,0x860(%rbx) + 41dceb: 00 00 00 00 + 41dcef: 48 89 83 58 08 00 00 mov %rax,0x858(%rbx) + 41dcf6: 8b 05 cc ca 2a 00 mov 0x2acacc(%rip),%eax # 6ca7c8 + 41dcfc: 89 83 68 08 00 00 mov %eax,0x868(%rbx) + 41dd02: 8b 05 c8 ca 2a 00 mov 0x2acac8(%rip),%eax # 6ca7d0 + 41dd08: 89 83 6c 08 00 00 mov %eax,0x86c(%rbx) + 41dd0e: 48 8b 05 c3 ca 2a 00 mov 0x2acac3(%rip),%rax # 6ca7d8 + 41dd15: 48 89 83 70 08 00 00 mov %rax,0x870(%rbx) + 41dd1c: 48 8b 05 bd ca 2a 00 mov 0x2acabd(%rip),%rax # 6ca7e0 + 41dd23: 48 89 83 78 08 00 00 mov %rax,0x878(%rbx) + 41dd2a: 8b 05 dc e8 2a 00 mov 0x2ae8dc(%rip),%eax # 6cc60c + 41dd30: 89 83 80 08 00 00 mov %eax,0x880(%rbx) + 41dd36: 48 8b 05 fb e8 2a 00 mov 0x2ae8fb(%rip),%rax # 6cc638 + 41dd3d: 48 89 83 88 08 00 00 mov %rax,0x888(%rbx) + 41dd44: 48 8b 05 6d ca 2a 00 mov 0x2aca6d(%rip),%rax # 6ca7b8 + 41dd4b: 48 89 83 90 08 00 00 mov %rax,0x890(%rbx) + 41dd52: 48 8b 05 67 ca 2a 00 mov 0x2aca67(%rip),%rax # 6ca7c0 + 41dd59: 48 89 83 98 08 00 00 mov %rax,0x898(%rbx) + 41dd60: 48 8b 05 01 ca 2a 00 mov 0x2aca01(%rip),%rax # 6ca768 + 41dd67: 48 89 83 a0 08 00 00 mov %rax,0x8a0(%rbx) + 41dd6e: 83 3d 47 f4 2a 00 00 cmpl $0x0,0x2af447(%rip) # 6cd1bc <__libc_multiple_threads> + 41dd75: 74 0b je 41dd82 <__malloc_get_state+0x1e2> + 41dd77: f0 ff 0d 82 ca 2a 00 lock decl 0x2aca82(%rip) # 6ca800 + 41dd7e: 75 0a jne 41dd8a <__malloc_get_state+0x1ea> + 41dd80: eb 22 jmp 41dda4 <__malloc_get_state+0x204> + 41dd82: ff 0d 78 ca 2a 00 decl 0x2aca78(%rip) # 6ca800 + 41dd88: 74 1a je 41dda4 <__malloc_get_state+0x204> + 41dd8a: 48 8d 3d 6f ca 2a 00 lea 0x2aca6f(%rip),%rdi # 6ca800 + 41dd91: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41dd98: e8 63 48 02 00 callq 442600 <__lll_unlock_wake_private> + 41dd9d: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41dda4: 48 89 d8 mov %rbx,%rax + 41dda7: 5b pop %rbx + 41dda8: c3 retq + 41dda9: 31 c0 xor %eax,%eax + 41ddab: 5b pop %rbx + 41ddac: c3 retq + 41ddad: 0f 1f 00 nopl (%rax) + +000000000041ddb0 <__cfree>: + 41ddb0: 41 55 push %r13 + 41ddb2: 41 54 push %r12 + 41ddb4: 55 push %rbp + 41ddb5: 53 push %rbx + 41ddb6: 48 83 ec 28 sub $0x28,%rsp + 41ddba: 48 8b 05 27 e8 2a 00 mov 0x2ae827(%rip),%rax # 6cc5e8 <__free_hook> + 41ddc1: 48 85 c0 test %rax,%rax + 41ddc4: 0f 85 c6 00 00 00 jne 41de90 <__cfree+0xe0> + 41ddca: 48 85 ff test %rdi,%rdi + 41ddcd: 74 28 je 41ddf7 <__cfree+0x47> + 41ddcf: 48 8b 47 f8 mov -0x8(%rdi),%rax + 41ddd3: 48 8d 77 f0 lea -0x10(%rdi),%rsi + 41ddd7: a8 02 test $0x2,%al + 41ddd9: 75 2d jne 41de08 <__cfree+0x58> + 41dddb: a8 04 test $0x4,%al + 41dddd: bf 00 a8 6c 00 mov $0x6ca800,%edi + 41dde2: 74 0c je 41ddf0 <__cfree+0x40> + 41dde4: 48 89 f0 mov %rsi,%rax + 41dde7: 48 25 00 00 00 fc and $0xfffffffffc000000,%rax + 41dded: 48 8b 38 mov (%rax),%rdi + 41ddf0: 31 d2 xor %edx,%edx + 41ddf2: e8 c9 b9 ff ff callq 4197c0 <_int_free> + 41ddf7: 48 83 c4 28 add $0x28,%rsp + 41ddfb: 5b pop %rbx + 41ddfc: 5d pop %rbp + 41ddfd: 41 5c pop %r12 + 41ddff: 41 5d pop %r13 + 41de01: c3 retq + 41de02: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 41de08: 8b 15 c6 c9 2a 00 mov 0x2ac9c6(%rip),%edx # 6ca7d4 + 41de0e: 85 d2 test %edx,%edx + 41de10: 75 2e jne 41de40 <__cfree+0x90> + 41de12: 48 3b 05 97 c9 2a 00 cmp 0x2ac997(%rip),%rax # 6ca7b0 + 41de19: 76 25 jbe 41de40 <__cfree+0x90> + 41de1b: 48 3d 00 00 00 02 cmp $0x2000000,%rax + 41de21: 77 1d ja 41de40 <__cfree+0x90> + 41de23: 48 83 e0 f8 and $0xfffffffffffffff8,%rax + 41de27: 48 8d 14 00 lea (%rax,%rax,1),%rdx + 41de2b: 48 89 05 7e c9 2a 00 mov %rax,0x2ac97e(%rip) # 6ca7b0 + 41de32: 48 89 15 67 c9 2a 00 mov %rdx,0x2ac967(%rip) # 6ca7a0 + 41de39: 90 nop + 41de3a: eb 08 jmp 41de44 <__cfree+0x94> + 41de3c: 0f 1f 40 00 nopl 0x0(%rax) + 41de40: 48 83 e0 f8 and $0xfffffffffffffff8,%rax + 41de44: 48 8b 4f f0 mov -0x10(%rdi),%rcx + 41de48: 48 89 f2 mov %rsi,%rdx + 41de4b: 48 8d 34 01 lea (%rcx,%rax,1),%rsi + 41de4f: 48 8b 05 2a d3 2a 00 mov 0x2ad32a(%rip),%rax # 6cb180 <_dl_pagesize> + 41de56: 48 29 ca sub %rcx,%rdx + 41de59: 48 89 d1 mov %rdx,%rcx + 41de5c: 48 09 f1 or %rsi,%rcx + 41de5f: 48 83 e8 01 sub $0x1,%rax + 41de63: 48 85 c8 test %rcx,%rax + 41de66: 75 40 jne 41dea8 <__cfree+0xf8> + 41de68: f0 ff 0d 59 c9 2a 00 lock decl 0x2ac959(%rip) # 6ca7c8 + 41de6f: 48 89 f0 mov %rsi,%rax + 41de72: 48 f7 d8 neg %rax + 41de75: f0 48 01 05 5b c9 2a lock add %rax,0x2ac95b(%rip) # 6ca7d8 + 41de7c: 00 + 41de7d: 48 89 d7 mov %rdx,%rdi + 41de80: e8 2b 1e 02 00 callq 43fcb0 <__munmap> + 41de85: 48 83 c4 28 add $0x28,%rsp + 41de89: 5b pop %rbx + 41de8a: 5d pop %rbp + 41de8b: 41 5c pop %r12 + 41de8d: 41 5d pop %r13 + 41de8f: c3 retq + 41de90: 48 8b 74 24 48 mov 0x48(%rsp),%rsi + 41de95: ff d0 callq *%rax + 41de97: 48 83 c4 28 add $0x28,%rsp + 41de9b: 5b pop %rbx + 41de9c: 5d pop %rbp + 41de9d: 41 5c pop %r12 + 41de9f: 41 5d pop %r13 + 41dea1: c3 retq + 41dea2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 41dea8: 8b 1d c2 c8 2a 00 mov 0x2ac8c2(%rip),%ebx # 6ca770 + 41deae: 89 d8 mov %ebx,%eax + 41deb0: 83 e0 05 and $0x5,%eax + 41deb3: 83 f8 05 cmp $0x5,%eax + 41deb6: 0f 84 8b 00 00 00 je 41df47 <__cfree+0x197> + 41debc: f6 c3 01 test $0x1,%bl + 41debf: 75 0f jne 41ded0 <__cfree+0x120> + 41dec1: 83 e3 02 and $0x2,%ebx + 41dec4: 0f 84 2d ff ff ff je 41ddf7 <__cfree+0x47> + 41deca: e8 31 fd fe ff callq 40dc00 + 41decf: 90 nop + 41ded0: 48 8d 74 24 10 lea 0x10(%rsp),%rsi + 41ded5: 31 c9 xor %ecx,%ecx + 41ded7: ba 10 00 00 00 mov $0x10,%edx + 41dedc: c6 44 24 10 00 movb $0x0,0x10(%rsp) + 41dee1: e8 ca 3f 03 00 callq 451eb0 <_itoa_word> + 41dee6: 48 39 e0 cmp %rsp,%rax + 41dee9: 48 89 c5 mov %rax,%rbp + 41deec: 76 25 jbe 41df13 <__cfree+0x163> + 41deee: 48 89 c2 mov %rax,%rdx + 41def1: 48 89 c7 mov %rax,%rdi + 41def4: be 30 00 00 00 mov $0x30,%esi + 41def9: 48 29 e2 sub %rsp,%rdx + 41defc: 4c 8d 68 ff lea -0x1(%rax),%r13 + 41df00: 48 29 d7 sub %rdx,%rdi + 41df03: e8 48 24 fe ff callq 400350 <__rela_iplt_end+0x88> + 41df08: 48 8d 44 24 ff lea -0x1(%rsp),%rax + 41df0d: 4c 29 e8 sub %r13,%rax + 41df10: 48 01 c5 add %rax,%rbp + 41df13: 48 8b 05 a6 f3 2a 00 mov 0x2af3a6(%rip),%rax # 6cd2c0 <__libc_argv> + 41df1a: ba 38 20 4a 00 mov $0x4a2038,%edx + 41df1f: 49 89 e8 mov %rbp,%r8 + 41df22: b9 d0 23 4a 00 mov $0x4a23d0,%ecx + 41df27: be a8 23 4a 00 mov $0x4a23a8,%esi + 41df2c: 48 8b 00 mov (%rax),%rax + 41df2f: 48 85 c0 test %rax,%rax + 41df32: 48 0f 45 d0 cmovne %rax,%rdx + 41df36: 83 e3 02 and $0x2,%ebx + 41df39: 31 c0 xor %eax,%eax + 41df3b: 89 df mov %ebx,%edi + 41df3d: e8 7e 36 ff ff callq 4115c0 <__libc_message> + 41df42: e9 b0 fe ff ff jmpq 41ddf7 <__cfree+0x47> + 41df47: 83 e3 02 and $0x2,%ebx + 41df4a: ba d0 23 4a 00 mov $0x4a23d0,%edx + 41df4f: be 3c ca 4b 00 mov $0x4bca3c,%esi + 41df54: 89 df mov %ebx,%edi + 41df56: 31 c0 xor %eax,%eax + 41df58: e8 63 36 ff ff callq 4115c0 <__libc_message> + 41df5d: e9 95 fe ff ff jmpq 41ddf7 <__cfree+0x47> + 41df62: 0f 1f 40 00 nopl 0x0(%rax) + 41df66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41df6d: 00 00 00 + +000000000041df70 <__libc_realloc>: + 41df70: 41 57 push %r15 + 41df72: 41 56 push %r14 + 41df74: 41 55 push %r13 + 41df76: 41 54 push %r12 + 41df78: 49 89 f5 mov %rsi,%r13 + 41df7b: 55 push %rbp + 41df7c: 53 push %rbx + 41df7d: 48 89 fb mov %rdi,%rbx + 41df80: 48 83 ec 38 sub $0x38,%rsp + 41df84: 48 8b 05 f5 c7 2a 00 mov 0x2ac7f5(%rip),%rax # 6ca780 <__realloc_hook> + 41df8b: 48 85 c0 test %rax,%rax + 41df8e: 0f 85 04 02 00 00 jne 41e198 <__libc_realloc+0x228> + 41df94: 48 85 f6 test %rsi,%rsi + 41df97: 75 09 jne 41dfa2 <__libc_realloc+0x32> + 41df99: 48 85 ff test %rdi,%rdi + 41df9c: 0f 85 6e 02 00 00 jne 41e210 <__libc_realloc+0x2a0> + 41dfa2: 48 85 db test %rbx,%rbx + 41dfa5: 0f 84 15 03 00 00 je 41e2c0 <__libc_realloc+0x350> + 41dfab: 48 8b 43 f8 mov -0x8(%rbx),%rax + 41dfaf: 4c 8d 73 f0 lea -0x10(%rbx),%r14 + 41dfb3: 49 89 c7 mov %rax,%r15 + 41dfb6: 48 89 c1 mov %rax,%rcx + 41dfb9: 49 83 e7 f8 and $0xfffffffffffffff8,%r15 + 41dfbd: 83 e1 02 and $0x2,%ecx + 41dfc0: 74 7e je 41e040 <__libc_realloc+0xd0> + 41dfc2: 4c 89 f8 mov %r15,%rax + 41dfc5: 48 f7 d8 neg %rax + 41dfc8: 49 39 c6 cmp %rax,%r14 + 41dfcb: 0f 87 3f 03 00 00 ja 41e310 <__libc_realloc+0x3a0> + 41dfd1: 41 f6 c6 0f test $0xf,%r14b + 41dfd5: 0f 85 35 03 00 00 jne 41e310 <__libc_realloc+0x3a0> + 41dfdb: 45 31 e4 xor %r12d,%r12d + 41dfde: 49 83 fd bf cmp $0xffffffffffffffbf,%r13 + 41dfe2: 0f 87 c8 01 00 00 ja 41e1b0 <__libc_realloc+0x240> + 41dfe8: 49 8d 45 17 lea 0x17(%r13),%rax + 41dfec: 48 89 c2 mov %rax,%rdx + 41dfef: 48 83 e2 f0 and $0xfffffffffffffff0,%rdx + 41dff3: 48 83 f8 20 cmp $0x20,%rax + 41dff7: b8 20 00 00 00 mov $0x20,%eax + 41dffc: 48 0f 42 d0 cmovb %rax,%rdx + 41e000: 48 85 c9 test %rcx,%rcx + 41e003: 0f 84 97 00 00 00 je 41e0a0 <__libc_realloc+0x130> + 41e009: 48 89 d6 mov %rdx,%rsi + 41e00c: 4c 89 f7 mov %r14,%rdi + 41e00f: 48 89 54 24 08 mov %rdx,0x8(%rsp) + 41e014: e8 07 90 ff ff callq 417020 + 41e019: 48 85 c0 test %rax,%rax + 41e01c: 48 8d 68 10 lea 0x10(%rax),%rbp + 41e020: 48 8b 54 24 08 mov 0x8(%rsp),%rdx + 41e025: 0f 84 9d 01 00 00 je 41e1c8 <__libc_realloc+0x258> + 41e02b: 48 83 c4 38 add $0x38,%rsp + 41e02f: 48 89 e8 mov %rbp,%rax + 41e032: 5b pop %rbx + 41e033: 5d pop %rbp + 41e034: 41 5c pop %r12 + 41e036: 41 5d pop %r13 + 41e038: 41 5e pop %r14 + 41e03a: 41 5f pop %r15 + 41e03c: c3 retq + 41e03d: 0f 1f 00 nopl (%rax) + 41e040: a8 04 test $0x4,%al + 41e042: 0f 84 28 01 00 00 je 41e170 <__libc_realloc+0x200> + 41e048: 4c 89 f0 mov %r14,%rax + 41e04b: 48 25 00 00 00 fc and $0xfffffffffc000000,%rax + 41e051: 4c 8b 20 mov (%rax),%r12 + 41e054: 4c 89 f8 mov %r15,%rax + 41e057: 48 f7 d8 neg %rax + 41e05a: 49 39 c6 cmp %rax,%r14 + 41e05d: 77 0a ja 41e069 <__libc_realloc+0xf9> + 41e05f: 41 f6 c6 0f test $0xf,%r14b + 41e063: 0f 84 75 ff ff ff je 41dfde <__libc_realloc+0x6e> + 41e069: 4d 85 e4 test %r12,%r12 + 41e06c: 8b 2d fe c6 2a 00 mov 0x2ac6fe(%rip),%ebp # 6ca770 + 41e072: 74 06 je 41e07a <__libc_realloc+0x10a> + 41e074: 41 83 4c 24 04 04 orl $0x4,0x4(%r12) + 41e07a: 89 e8 mov %ebp,%eax + 41e07c: 83 e0 05 and $0x5,%eax + 41e07f: 83 f8 05 cmp $0x5,%eax + 41e082: 0f 84 98 02 00 00 je 41e320 <__libc_realloc+0x3b0> + 41e088: 40 f6 c5 01 test $0x1,%bpl + 41e08c: 0f 85 a6 01 00 00 jne 41e238 <__libc_realloc+0x2c8> + 41e092: 83 e5 02 and $0x2,%ebp + 41e095: 0f 85 a2 02 00 00 jne 41e33d <__libc_realloc+0x3cd> + 41e09b: 31 ed xor %ebp,%ebp + 41e09d: eb 8c jmp 41e02b <__libc_realloc+0xbb> + 41e09f: 90 nop + 41e0a0: be 01 00 00 00 mov $0x1,%esi + 41e0a5: 31 c0 xor %eax,%eax + 41e0a7: 83 3d 0e f1 2a 00 00 cmpl $0x0,0x2af10e(%rip) # 6cd1bc <__libc_multiple_threads> + 41e0ae: 74 0a je 41e0ba <__libc_realloc+0x14a> + 41e0b0: f0 41 0f b1 34 24 lock cmpxchg %esi,(%r12) + 41e0b6: 75 09 jne 41e0c1 <__libc_realloc+0x151> + 41e0b8: eb 1e jmp 41e0d8 <__libc_realloc+0x168> + 41e0ba: 41 0f b1 34 24 cmpxchg %esi,(%r12) + 41e0bf: 74 17 je 41e0d8 <__libc_realloc+0x168> + 41e0c1: 49 8d 3c 24 lea (%r12),%rdi + 41e0c5: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41e0cc: e8 ff 44 02 00 callq 4425d0 <__lll_lock_wait_private> + 41e0d1: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41e0d8: 48 89 d1 mov %rdx,%rcx + 41e0db: 4c 89 f6 mov %r14,%rsi + 41e0de: 4c 89 fa mov %r15,%rdx + 41e0e1: 4c 89 e7 mov %r12,%rdi + 41e0e4: e8 77 e9 ff ff callq 41ca60 <_int_realloc> + 41e0e9: 48 89 c5 mov %rax,%rbp + 41e0ec: 83 3d c9 f0 2a 00 00 cmpl $0x0,0x2af0c9(%rip) # 6cd1bc <__libc_multiple_threads> + 41e0f3: 74 09 je 41e0fe <__libc_realloc+0x18e> + 41e0f5: f0 41 ff 0c 24 lock decl (%r12) + 41e0fa: 75 08 jne 41e104 <__libc_realloc+0x194> + 41e0fc: eb 1d jmp 41e11b <__libc_realloc+0x1ab> + 41e0fe: 41 ff 0c 24 decl (%r12) + 41e102: 74 17 je 41e11b <__libc_realloc+0x1ab> + 41e104: 49 8d 3c 24 lea (%r12),%rdi + 41e108: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41e10f: e8 ec 44 02 00 callq 442600 <__lll_unlock_wake_private> + 41e114: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41e11b: 48 85 ed test %rbp,%rbp + 41e11e: 0f 84 ac 01 00 00 je 41e2d0 <__libc_realloc+0x360> + 41e124: 48 8b 45 f8 mov -0x8(%rbp),%rax + 41e128: a8 02 test $0x2,%al + 41e12a: 0f 85 fb fe ff ff jne 41e02b <__libc_realloc+0xbb> + 41e130: a8 04 test $0x4,%al + 41e132: ba 00 a8 6c 00 mov $0x6ca800,%edx + 41e137: 74 0d je 41e146 <__libc_realloc+0x1d6> + 41e139: 48 8d 45 f0 lea -0x10(%rbp),%rax + 41e13d: 48 25 00 00 00 fc and $0xfffffffffc000000,%rax + 41e143: 48 8b 10 mov (%rax),%rdx + 41e146: 4c 39 e2 cmp %r12,%rdx + 41e149: 0f 84 dc fe ff ff je 41e02b <__libc_realloc+0xbb> + 41e14f: b9 18 2e 4a 00 mov $0x4a2e18,%ecx + 41e154: ba e9 0b 00 00 mov $0xbe9,%edx + 41e159: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 41e15e: bf c0 29 4a 00 mov $0x4a29c0,%edi + 41e163: e8 b8 8c ff ff callq 416e20 <__malloc_assert> + 41e168: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 41e16f: 00 + 41e170: 4c 89 f8 mov %r15,%rax + 41e173: 48 f7 d8 neg %rax + 41e176: 49 39 c6 cmp %rax,%r14 + 41e179: 0f 87 a1 00 00 00 ja 41e220 <__libc_realloc+0x2b0> + 41e17f: 41 f6 c6 0f test $0xf,%r14b + 41e183: 0f 85 97 00 00 00 jne 41e220 <__libc_realloc+0x2b0> + 41e189: 41 bc 00 a8 6c 00 mov $0x6ca800,%r12d + 41e18f: e9 4a fe ff ff jmpq 41dfde <__libc_realloc+0x6e> + 41e194: 0f 1f 40 00 nopl 0x0(%rax) + 41e198: 48 8b 54 24 68 mov 0x68(%rsp),%rdx + 41e19d: ff d0 callq *%rax + 41e19f: 48 89 c5 mov %rax,%rbp + 41e1a2: e9 84 fe ff ff jmpq 41e02b <__libc_realloc+0xbb> + 41e1a7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 41e1ae: 00 00 + 41e1b0: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 41e1b7: 31 ed xor %ebp,%ebp + 41e1b9: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) + 41e1c0: e9 66 fe ff ff jmpq 41e02b <__libc_realloc+0xbb> + 41e1c5: 0f 1f 00 nopl (%rax) + 41e1c8: 49 8d 47 f8 lea -0x8(%r15),%rax + 41e1cc: 48 89 dd mov %rbx,%rbp + 41e1cf: 48 39 c2 cmp %rax,%rdx + 41e1d2: 0f 86 53 fe ff ff jbe 41e02b <__libc_realloc+0xbb> + 41e1d8: 4c 89 ef mov %r13,%rdi + 41e1db: e8 30 f8 ff ff callq 41da10 <__libc_malloc> + 41e1e0: 48 85 c0 test %rax,%rax + 41e1e3: 48 89 c3 mov %rax,%rbx + 41e1e6: 0f 84 af fe ff ff je 41e09b <__libc_realloc+0x12b> + 41e1ec: 49 8d 57 f0 lea -0x10(%r15),%rdx + 41e1f0: 48 89 ee mov %rbp,%rsi + 41e1f3: 48 89 c7 mov %rax,%rdi + 41e1f6: 48 89 dd mov %rbx,%rbp + 41e1f9: e8 22 de 00 00 callq 42c020 + 41e1fe: 4c 89 f7 mov %r14,%rdi + 41e201: e8 ea 9a ff ff callq 417cf0 + 41e206: e9 20 fe ff ff jmpq 41e02b <__libc_realloc+0xbb> + 41e20b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41e210: e8 9b fb ff ff callq 41ddb0 <__cfree> + 41e215: 31 ed xor %ebp,%ebp + 41e217: e9 0f fe ff ff jmpq 41e02b <__libc_realloc+0xbb> + 41e21c: 0f 1f 40 00 nopl 0x0(%rax) + 41e220: 8b 2d 4a c5 2a 00 mov 0x2ac54a(%rip),%ebp # 6ca770 + 41e226: 41 bc 00 a8 6c 00 mov $0x6ca800,%r12d + 41e22c: e9 43 fe ff ff jmpq 41e074 <__libc_realloc+0x104> + 41e231: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 41e238: 4c 8d 64 24 10 lea 0x10(%rsp),%r12 + 41e23d: 48 8d 74 24 20 lea 0x20(%rsp),%rsi + 41e242: 31 c9 xor %ecx,%ecx + 41e244: 48 89 df mov %rbx,%rdi + 41e247: ba 10 00 00 00 mov $0x10,%edx + 41e24c: c6 44 24 20 00 movb $0x0,0x20(%rsp) + 41e251: e8 5a 3c 03 00 callq 451eb0 <_itoa_word> + 41e256: 4c 39 e0 cmp %r12,%rax + 41e259: 48 89 c3 mov %rax,%rbx + 41e25c: 76 25 jbe 41e283 <__libc_realloc+0x313> + 41e25e: 48 89 c2 mov %rax,%rdx + 41e261: 48 89 c7 mov %rax,%rdi + 41e264: be 30 00 00 00 mov $0x30,%esi + 41e269: 4c 29 e2 sub %r12,%rdx + 41e26c: 4c 8d 68 ff lea -0x1(%rax),%r13 + 41e270: 48 29 d7 sub %rdx,%rdi + 41e273: e8 d8 20 fe ff callq 400350 <__rela_iplt_end+0x88> + 41e278: 48 8d 44 24 0f lea 0xf(%rsp),%rax + 41e27d: 4c 29 e8 sub %r13,%rax + 41e280: 48 01 c3 add %rax,%rbx + 41e283: 48 8b 05 36 f0 2a 00 mov 0x2af036(%rip),%rax # 6cd2c0 <__libc_argv> + 41e28a: 89 ef mov %ebp,%edi + 41e28c: ba 38 20 4a 00 mov $0x4a2038,%edx + 41e291: 49 89 d8 mov %rbx,%r8 + 41e294: b9 c6 21 4a 00 mov $0x4a21c6,%ecx + 41e299: be a8 23 4a 00 mov $0x4a23a8,%esi + 41e29e: 48 8b 00 mov (%rax),%rax + 41e2a1: 48 85 c0 test %rax,%rax + 41e2a4: 48 0f 45 d0 cmovne %rax,%rdx + 41e2a8: 83 e7 02 and $0x2,%edi + 41e2ab: 31 c0 xor %eax,%eax + 41e2ad: e8 0e 33 ff ff callq 4115c0 <__libc_message> + 41e2b2: 31 ed xor %ebp,%ebp + 41e2b4: e9 72 fd ff ff jmpq 41e02b <__libc_realloc+0xbb> + 41e2b9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 41e2c0: 4c 89 ef mov %r13,%rdi + 41e2c3: e8 48 f7 ff ff callq 41da10 <__libc_malloc> + 41e2c8: 48 89 c5 mov %rax,%rbp + 41e2cb: e9 5b fd ff ff jmpq 41e02b <__libc_realloc+0xbb> + 41e2d0: 90 nop + 41e2d1: 4c 89 ef mov %r13,%rdi + 41e2d4: 31 ed xor %ebp,%ebp + 41e2d6: e8 35 f7 ff ff callq 41da10 <__libc_malloc> + 41e2db: 48 85 c0 test %rax,%rax + 41e2de: 49 89 c5 mov %rax,%r13 + 41e2e1: 0f 84 44 fd ff ff je 41e02b <__libc_realloc+0xbb> + 41e2e7: 49 8d 57 f8 lea -0x8(%r15),%rdx + 41e2eb: 48 89 de mov %rbx,%rsi + 41e2ee: 48 89 c7 mov %rax,%rdi + 41e2f1: 4c 89 ed mov %r13,%rbp + 41e2f4: e8 27 dd 00 00 callq 42c020 + 41e2f9: 31 d2 xor %edx,%edx + 41e2fb: 4c 89 f6 mov %r14,%rsi + 41e2fe: 4c 89 e7 mov %r12,%rdi + 41e301: e8 ba b4 ff ff callq 4197c0 <_int_free> + 41e306: e9 20 fd ff ff jmpq 41e02b <__libc_realloc+0xbb> + 41e30b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41e310: 8b 2d 5a c4 2a 00 mov 0x2ac45a(%rip),%ebp # 6ca770 + 41e316: e9 5f fd ff ff jmpq 41e07a <__libc_realloc+0x10a> + 41e31b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41e320: 89 ef mov %ebp,%edi + 41e322: ba c6 21 4a 00 mov $0x4a21c6,%edx + 41e327: be 3c ca 4b 00 mov $0x4bca3c,%esi + 41e32c: 83 e7 02 and $0x2,%edi + 41e32f: 31 c0 xor %eax,%eax + 41e331: 31 ed xor %ebp,%ebp + 41e333: e8 88 32 ff ff callq 4115c0 <__libc_message> + 41e338: e9 ee fc ff ff jmpq 41e02b <__libc_realloc+0xbb> + 41e33d: e8 be f8 fe ff callq 40dc00 + 41e342: 0f 1f 40 00 nopl 0x0(%rax) + 41e346: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41e34d: 00 00 00 + +000000000041e350 <__libc_memalign>: + 41e350: 48 8b 05 21 c4 2a 00 mov 0x2ac421(%rip),%rax # 6ca778 <__memalign_hook> + 41e357: 41 54 push %r12 + 41e359: 48 85 c0 test %rax,%rax + 41e35c: 55 push %rbp + 41e35d: 53 push %rbx + 41e35e: 48 8b 54 24 18 mov 0x18(%rsp),%rdx + 41e363: 0f 85 ef 01 00 00 jne 41e558 <__libc_memalign+0x208> + 41e369: 48 83 ff 10 cmp $0x10,%rdi + 41e36d: 0f 86 d5 01 00 00 jbe 41e548 <__libc_memalign+0x1f8> + 41e373: 48 83 ff 1f cmp $0x1f,%rdi + 41e377: 0f 87 e3 00 00 00 ja 41e460 <__libc_memalign+0x110> + 41e37d: 48 83 fe bf cmp $0xffffffffffffffbf,%rsi + 41e381: 0f 87 f1 01 00 00 ja 41e578 <__libc_memalign+0x228> + 41e387: bb 20 00 00 00 mov $0x20,%ebx + 41e38c: 48 c7 c0 d8 ff ff ff mov $0xffffffffffffffd8,%rax + 41e393: 49 89 f4 mov %rsi,%r12 + 41e396: 64 48 8b 28 mov %fs:(%rax),%rbp + 41e39a: 48 85 ed test %rbp,%rbp + 41e39d: 0f 84 15 01 00 00 je 41e4b8 <__libc_memalign+0x168> + 41e3a3: 8b 45 04 mov 0x4(%rbp),%eax + 41e3a6: 83 e0 04 and $0x4,%eax + 41e3a9: 0f 85 09 01 00 00 jne 41e4b8 <__libc_memalign+0x168> + 41e3af: be 01 00 00 00 mov $0x1,%esi + 41e3b4: 83 3d 01 ee 2a 00 00 cmpl $0x0,0x2aee01(%rip) # 6cd1bc <__libc_multiple_threads> + 41e3bb: 74 09 je 41e3c6 <__libc_memalign+0x76> + 41e3bd: f0 0f b1 75 00 lock cmpxchg %esi,0x0(%rbp) + 41e3c2: 75 08 jne 41e3cc <__libc_memalign+0x7c> + 41e3c4: eb 1d jmp 41e3e3 <__libc_memalign+0x93> + 41e3c6: 0f b1 75 00 cmpxchg %esi,0x0(%rbp) + 41e3ca: 74 17 je 41e3e3 <__libc_memalign+0x93> + 41e3cc: 48 8d 7d 00 lea 0x0(%rbp),%rdi + 41e3d0: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41e3d7: e8 f4 41 02 00 callq 4425d0 <__lll_lock_wait_private> + 41e3dc: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41e3e3: 4c 89 e2 mov %r12,%rdx + 41e3e6: 48 89 de mov %rbx,%rsi + 41e3e9: 48 89 ef mov %rbp,%rdi + 41e3ec: e8 1f e1 ff ff callq 41c510 <_int_memalign> + 41e3f1: 48 85 c0 test %rax,%rax + 41e3f4: 48 89 c2 mov %rax,%rdx + 41e3f7: 0f 84 fb 00 00 00 je 41e4f8 <__libc_memalign+0x1a8> + 41e3fd: 83 3d b8 ed 2a 00 00 cmpl $0x0,0x2aedb8(%rip) # 6cd1bc <__libc_multiple_threads> + 41e404: 74 08 je 41e40e <__libc_memalign+0xbe> + 41e406: f0 ff 4d 00 lock decl 0x0(%rbp) + 41e40a: 75 07 jne 41e413 <__libc_memalign+0xc3> + 41e40c: eb 1c jmp 41e42a <__libc_memalign+0xda> + 41e40e: ff 4d 00 decl 0x0(%rbp) + 41e411: 74 17 je 41e42a <__libc_memalign+0xda> + 41e413: 48 8d 7d 00 lea 0x0(%rbp),%rdi + 41e417: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41e41e: e8 dd 41 02 00 callq 442600 <__lll_unlock_wake_private> + 41e423: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41e42a: 48 85 d2 test %rdx,%rdx + 41e42d: 0f 84 5d 01 00 00 je 41e590 <__libc_memalign+0x240> + 41e433: 48 8b 42 f8 mov -0x8(%rdx),%rax + 41e437: a8 02 test $0x2,%al + 41e439: 75 16 jne 41e451 <__libc_memalign+0x101> + 41e43b: a8 04 test $0x4,%al + 41e43d: b9 00 a8 6c 00 mov $0x6ca800,%ecx + 41e442: 0f 85 e8 00 00 00 jne 41e530 <__libc_memalign+0x1e0> + 41e448: 48 39 e9 cmp %rbp,%rcx + 41e44b: 0f 85 46 01 00 00 jne 41e597 <__libc_memalign+0x247> + 41e451: 48 89 d0 mov %rdx,%rax + 41e454: 5b pop %rbx + 41e455: 5d pop %rbp + 41e456: 41 5c pop %r12 + 41e458: c3 retq + 41e459: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 41e460: 48 b8 00 00 00 00 00 movabs $0x8000000000000000,%rax + 41e467: 00 00 80 + 41e46a: 48 39 c7 cmp %rax,%rdi + 41e46d: 0f 87 ed 00 00 00 ja 41e560 <__libc_memalign+0x210> + 41e473: 48 c7 c0 df ff ff ff mov $0xffffffffffffffdf,%rax + 41e47a: 48 29 f8 sub %rdi,%rax + 41e47d: 48 39 c6 cmp %rax,%rsi + 41e480: 0f 87 f2 00 00 00 ja 41e578 <__libc_memalign+0x228> + 41e486: 48 8d 47 ff lea -0x1(%rdi),%rax + 41e48a: 48 85 f8 test %rdi,%rax + 41e48d: 0f 84 1d 01 00 00 je 41e5b0 <__libc_memalign+0x260> + 41e493: 48 83 ff 20 cmp $0x20,%rdi + 41e497: bb 20 00 00 00 mov $0x20,%ebx + 41e49c: 0f 84 ea fe ff ff je 41e38c <__libc_memalign+0x3c> + 41e4a2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 41e4a8: 48 01 db add %rbx,%rbx + 41e4ab: 48 39 df cmp %rbx,%rdi + 41e4ae: 77 f8 ja 41e4a8 <__libc_memalign+0x158> + 41e4b0: e9 d7 fe ff ff jmpq 41e38c <__libc_memalign+0x3c> + 41e4b5: 0f 1f 00 nopl (%rax) + 41e4b8: e8 a3 8c ff ff callq 417160 + 41e4bd: 48 85 c0 test %rax,%rax + 41e4c0: 48 89 c5 mov %rax,%rbp + 41e4c3: 0f 85 1a ff ff ff jne 41e3e3 <__libc_memalign+0x93> + 41e4c9: 4a 8d 7c 23 20 lea 0x20(%rbx,%r12,1),%rdi + 41e4ce: 31 f6 xor %esi,%esi + 41e4d0: e8 7b 8f ff ff callq 417450 + 41e4d5: 4c 89 e2 mov %r12,%rdx + 41e4d8: 48 89 de mov %rbx,%rsi + 41e4db: 48 89 c7 mov %rax,%rdi + 41e4de: 48 89 c5 mov %rax,%rbp + 41e4e1: e8 2a e0 ff ff callq 41c510 <_int_memalign> + 41e4e6: 48 85 c0 test %rax,%rax + 41e4e9: 48 89 c2 mov %rax,%rdx + 41e4ec: 75 2a jne 41e518 <__libc_memalign+0x1c8> + 41e4ee: 48 85 ed test %rbp,%rbp + 41e4f1: 74 25 je 41e518 <__libc_memalign+0x1c8> + 41e4f3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41e4f8: 90 nop + 41e4f9: 48 89 ef mov %rbp,%rdi + 41e4fc: 4c 89 e6 mov %r12,%rsi + 41e4ff: e8 ec 94 ff ff callq 4179f0 + 41e504: 4c 89 e2 mov %r12,%rdx + 41e507: 48 89 de mov %rbx,%rsi + 41e50a: 48 89 c7 mov %rax,%rdi + 41e50d: 48 89 c5 mov %rax,%rbp + 41e510: e8 fb df ff ff callq 41c510 <_int_memalign> + 41e515: 48 89 c2 mov %rax,%rdx + 41e518: 48 85 ed test %rbp,%rbp + 41e51b: 0f 85 dc fe ff ff jne 41e3fd <__libc_memalign+0xad> + 41e521: e9 04 ff ff ff jmpq 41e42a <__libc_memalign+0xda> + 41e526: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41e52d: 00 00 00 + 41e530: 48 8d 42 f0 lea -0x10(%rdx),%rax + 41e534: 48 25 00 00 00 fc and $0xfffffffffc000000,%rax + 41e53a: 48 8b 08 mov (%rax),%rcx + 41e53d: e9 06 ff ff ff jmpq 41e448 <__libc_memalign+0xf8> + 41e542: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 41e548: 5b pop %rbx + 41e549: 5d pop %rbp + 41e54a: 41 5c pop %r12 + 41e54c: 48 89 f7 mov %rsi,%rdi + 41e54f: e9 bc f4 ff ff jmpq 41da10 <__libc_malloc> + 41e554: 0f 1f 40 00 nopl 0x0(%rax) + 41e558: 5b pop %rbx + 41e559: 5d pop %rbp + 41e55a: 41 5c pop %r12 + 41e55c: ff e0 jmpq *%rax + 41e55e: 66 90 xchg %ax,%ax + 41e560: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 41e567: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) + 41e56e: 31 c0 xor %eax,%eax + 41e570: e9 df fe ff ff jmpq 41e454 <__libc_memalign+0x104> + 41e575: 0f 1f 00 nopl (%rax) + 41e578: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 41e57f: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) + 41e586: 31 c0 xor %eax,%eax + 41e588: e9 c7 fe ff ff jmpq 41e454 <__libc_memalign+0x104> + 41e58d: 0f 1f 00 nopl (%rax) + 41e590: 31 c0 xor %eax,%eax + 41e592: e9 bd fe ff ff jmpq 41e454 <__libc_memalign+0x104> + 41e597: b9 08 2e 4a 00 mov $0x4a2e08,%ecx + 41e59c: ba 3c 0c 00 00 mov $0xc3c,%edx + 41e5a1: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 41e5a6: bf 20 2a 4a 00 mov $0x4a2a20,%edi + 41e5ab: e8 70 88 ff ff callq 416e20 <__malloc_assert> + 41e5b0: 48 89 fb mov %rdi,%rbx + 41e5b3: e9 d4 fd ff ff jmpq 41e38c <__libc_memalign+0x3c> + 41e5b8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 41e5bf: 00 + +000000000041e5c0 <__calloc>: + 41e5c0: 41 55 push %r13 + 41e5c2: 48 89 fa mov %rdi,%rdx + 41e5c5: 41 54 push %r12 + 41e5c7: 55 push %rbp + 41e5c8: 53 push %rbx + 41e5c9: 48 89 fd mov %rdi,%rbp + 41e5cc: 48 09 f2 or %rsi,%rdx + 41e5cf: b8 ff ff ff ff mov $0xffffffff,%eax + 41e5d4: 48 83 ec 08 sub $0x8,%rsp + 41e5d8: 48 0f af ee imul %rsi,%rbp + 41e5dc: 48 39 c2 cmp %rax,%rdx + 41e5df: 76 1f jbe 41e600 <__calloc+0x40> + 41e5e1: 48 85 f6 test %rsi,%rsi + 41e5e4: 74 1a je 41e600 <__calloc+0x40> + 41e5e6: 31 d2 xor %edx,%edx + 41e5e8: 48 89 e8 mov %rbp,%rax + 41e5eb: 48 f7 f6 div %rsi + 41e5ee: 48 39 c7 cmp %rax,%rdi + 41e5f1: 0f 85 a9 02 00 00 jne 41e8a0 <__calloc+0x2e0> + 41e5f7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 41e5fe: 00 00 + 41e600: 48 8b 05 81 c1 2a 00 mov 0x2ac181(%rip),%rax # 6ca788 <__malloc_hook> + 41e607: 48 85 c0 test %rax,%rax + 41e60a: 0f 85 70 02 00 00 jne 41e880 <__calloc+0x2c0> + 41e610: 48 c7 c0 d8 ff ff ff mov $0xffffffffffffffd8,%rax + 41e617: 64 48 8b 18 mov %fs:(%rax),%rbx + 41e61b: 48 85 db test %rbx,%rbx + 41e61e: 74 0c je 41e62c <__calloc+0x6c> + 41e620: 8b 43 04 mov 0x4(%rbx),%eax + 41e623: 83 e0 04 and $0x4,%eax + 41e626: 0f 84 d4 00 00 00 je 41e700 <__calloc+0x140> + 41e62c: e8 2f 8b ff ff callq 417160 + 41e631: 48 85 c0 test %rax,%rax + 41e634: 48 89 c3 mov %rax,%rbx + 41e637: 0f 84 7b 02 00 00 je 41e8b8 <__calloc+0x2f8> + 41e63d: 4c 8b 6b 58 mov 0x58(%rbx),%r13 + 41e641: 4d 8b 65 08 mov 0x8(%r13),%r12 + 41e645: 49 83 e4 f8 and $0xfffffffffffffff8,%r12 + 41e649: 48 81 fb 00 a8 6c 00 cmp $0x6ca800,%rbx + 41e650: 0f 84 9a 01 00 00 je 41e7f0 <__calloc+0x230> + 41e656: 4c 89 e8 mov %r13,%rax + 41e659: 48 89 ee mov %rbp,%rsi + 41e65c: 48 89 df mov %rbx,%rdi + 41e65f: 48 25 00 00 00 fc and $0xfffffffffc000000,%rax + 41e665: 48 03 40 18 add 0x18(%rax),%rax + 41e669: 4c 29 e8 sub %r13,%rax + 41e66c: 49 39 c4 cmp %rax,%r12 + 41e66f: 4c 0f 42 e0 cmovb %rax,%r12 + 41e673: e8 c8 ce ff ff callq 41b540 <_int_malloc> + 41e678: 48 85 c0 test %rax,%rax + 41e67b: 49 89 c0 mov %rax,%r8 + 41e67e: 0f 84 8c 01 00 00 je 41e810 <__calloc+0x250> + 41e684: 49 8b 40 f8 mov -0x8(%r8),%rax + 41e688: a8 02 test $0x2,%al + 41e68a: 75 16 jne 41e6a2 <__calloc+0xe2> + 41e68c: a8 04 test $0x4,%al + 41e68e: ba 00 a8 6c 00 mov $0x6ca800,%edx + 41e693: 0f 85 b7 01 00 00 jne 41e850 <__calloc+0x290> + 41e699: 48 39 da cmp %rbx,%rdx + 41e69c: 0f 85 55 02 00 00 jne 41e8f7 <__calloc+0x337> + 41e6a2: 48 85 db test %rbx,%rbx + 41e6a5: 74 33 je 41e6da <__calloc+0x11a> + 41e6a7: 83 3d 0e eb 2a 00 00 cmpl $0x0,0x2aeb0e(%rip) # 6cd1bc <__libc_multiple_threads> + 41e6ae: 74 07 je 41e6b7 <__calloc+0xf7> + 41e6b0: f0 ff 0b lock decl (%rbx) + 41e6b3: 75 06 jne 41e6bb <__calloc+0xfb> + 41e6b5: eb 1a jmp 41e6d1 <__calloc+0x111> + 41e6b7: ff 0b decl (%rbx) + 41e6b9: 74 16 je 41e6d1 <__calloc+0x111> + 41e6bb: 48 8d 3b lea (%rbx),%rdi + 41e6be: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41e6c5: e8 36 3f 02 00 callq 442600 <__lll_unlock_wake_private> + 41e6ca: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41e6d1: 4d 85 c0 test %r8,%r8 + 41e6d4: 0f 84 bd 01 00 00 je 41e897 <__calloc+0x2d7> + 41e6da: 49 8b 50 f8 mov -0x8(%r8),%rdx + 41e6de: f6 c2 02 test $0x2,%dl + 41e6e1: 74 5d je 41e740 <__calloc+0x180> + 41e6e3: 8b 15 4b df 2a 00 mov 0x2adf4b(%rip),%edx # 6cc634 + 41e6e9: 4c 89 c0 mov %r8,%rax + 41e6ec: 85 d2 test %edx,%edx + 41e6ee: 0f 85 74 01 00 00 jne 41e868 <__calloc+0x2a8> + 41e6f4: 48 83 c4 08 add $0x8,%rsp + 41e6f8: 5b pop %rbx + 41e6f9: 5d pop %rbp + 41e6fa: 41 5c pop %r12 + 41e6fc: 41 5d pop %r13 + 41e6fe: c3 retq + 41e6ff: 90 nop + 41e700: be 01 00 00 00 mov $0x1,%esi + 41e705: 83 3d b0 ea 2a 00 00 cmpl $0x0,0x2aeab0(%rip) # 6cd1bc <__libc_multiple_threads> + 41e70c: 74 08 je 41e716 <__calloc+0x156> + 41e70e: f0 0f b1 33 lock cmpxchg %esi,(%rbx) + 41e712: 75 07 jne 41e71b <__calloc+0x15b> + 41e714: eb 1b jmp 41e731 <__calloc+0x171> + 41e716: 0f b1 33 cmpxchg %esi,(%rbx) + 41e719: 74 16 je 41e731 <__calloc+0x171> + 41e71b: 48 8d 3b lea (%rbx),%rdi + 41e71e: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41e725: e8 a6 3e 02 00 callq 4425d0 <__lll_lock_wait_private> + 41e72a: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41e731: e9 07 ff ff ff jmpq 41e63d <__calloc+0x7d> + 41e736: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41e73d: 00 00 00 + 41e740: 8b 05 ee de 2a 00 mov 0x2adeee(%rip),%eax # 6cc634 + 41e746: 48 83 e2 f8 and $0xfffffffffffffff8,%rdx + 41e74a: 85 c0 test %eax,%eax + 41e74c: 75 10 jne 41e75e <__calloc+0x19e> + 41e74e: 49 8d 40 f0 lea -0x10(%r8),%rax + 41e752: 49 39 c5 cmp %rax,%r13 + 41e755: 75 07 jne 41e75e <__calloc+0x19e> + 41e757: 4c 39 e2 cmp %r12,%rdx + 41e75a: 49 0f 47 d4 cmova %r12,%rdx + 41e75e: 48 83 ea 08 sub $0x8,%rdx + 41e762: 48 89 d1 mov %rdx,%rcx + 41e765: 48 c1 e9 03 shr $0x3,%rcx + 41e769: 48 83 f9 02 cmp $0x2,%rcx + 41e76d: 0f 86 9d 01 00 00 jbe 41e910 <__calloc+0x350> + 41e773: 48 83 f9 09 cmp $0x9,%rcx + 41e777: 0f 87 ee 00 00 00 ja 41e86b <__calloc+0x2ab> + 41e77d: 48 83 f9 04 cmp $0x4,%rcx + 41e781: 49 c7 00 00 00 00 00 movq $0x0,(%r8) + 41e788: 49 c7 40 08 00 00 00 movq $0x0,0x8(%r8) + 41e78f: 00 + 41e790: 49 c7 40 10 00 00 00 movq $0x0,0x10(%r8) + 41e797: 00 + 41e798: 4c 89 c0 mov %r8,%rax + 41e79b: 0f 86 53 ff ff ff jbe 41e6f4 <__calloc+0x134> + 41e7a1: 48 83 f9 06 cmp $0x6,%rcx + 41e7a5: 49 c7 40 18 00 00 00 movq $0x0,0x18(%r8) + 41e7ac: 00 + 41e7ad: 49 c7 40 20 00 00 00 movq $0x0,0x20(%r8) + 41e7b4: 00 + 41e7b5: 0f 86 39 ff ff ff jbe 41e6f4 <__calloc+0x134> + 41e7bb: 48 83 f9 09 cmp $0x9,%rcx + 41e7bf: 49 c7 40 28 00 00 00 movq $0x0,0x28(%r8) + 41e7c6: 00 + 41e7c7: 49 c7 40 30 00 00 00 movq $0x0,0x30(%r8) + 41e7ce: 00 + 41e7cf: 0f 85 1f ff ff ff jne 41e6f4 <__calloc+0x134> + 41e7d5: 49 c7 40 38 00 00 00 movq $0x0,0x38(%r8) + 41e7dc: 00 + 41e7dd: 49 c7 40 40 00 00 00 movq $0x0,0x40(%r8) + 41e7e4: 00 + 41e7e5: e9 0a ff ff ff jmpq 41e6f4 <__calloc+0x134> + 41e7ea: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 41e7f0: 48 89 ee mov %rbp,%rsi + 41e7f3: bf 00 a8 6c 00 mov $0x6ca800,%edi + 41e7f8: e8 43 cd ff ff callq 41b540 <_int_malloc> + 41e7fd: 48 85 c0 test %rax,%rax + 41e800: 49 89 c0 mov %rax,%r8 + 41e803: 0f 85 7b fe ff ff jne 41e684 <__calloc+0xc4> + 41e809: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 41e810: 90 nop + 41e811: 48 89 df mov %rbx,%rdi + 41e814: 48 89 ee mov %rbp,%rsi + 41e817: e8 d4 91 ff ff callq 4179f0 + 41e81c: 48 89 ee mov %rbp,%rsi + 41e81f: 48 89 c3 mov %rax,%rbx + 41e822: 48 89 c7 mov %rax,%rdi + 41e825: e8 16 cd ff ff callq 41b540 <_int_malloc> + 41e82a: 48 85 db test %rbx,%rbx + 41e82d: 49 89 c0 mov %rax,%r8 + 41e830: 0f 85 71 fe ff ff jne 41e6a7 <__calloc+0xe7> + 41e836: e9 96 fe ff ff jmpq 41e6d1 <__calloc+0x111> + 41e83b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41e840: a8 04 test $0x4,%al + 41e842: 0f 84 af 00 00 00 je 41e8f7 <__calloc+0x337> + 41e848: 45 31 e4 xor %r12d,%r12d + 41e84b: 45 31 ed xor %r13d,%r13d + 41e84e: 66 90 xchg %ax,%ax + 41e850: 49 8d 40 f0 lea -0x10(%r8),%rax + 41e854: 48 25 00 00 00 fc and $0xfffffffffc000000,%rax + 41e85a: 48 8b 10 mov (%rax),%rdx + 41e85d: e9 37 fe ff ff jmpq 41e699 <__calloc+0xd9> + 41e862: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 41e868: 48 89 ea mov %rbp,%rdx + 41e86b: 31 f6 xor %esi,%esi + 41e86d: 4c 89 c7 mov %r8,%rdi + 41e870: 48 83 c4 08 add $0x8,%rsp + 41e874: 5b pop %rbx + 41e875: 5d pop %rbp + 41e876: 41 5c pop %r12 + 41e878: 41 5d pop %r13 + 41e87a: e9 d1 1a fe ff jmpq 400350 <__rela_iplt_end+0x88> + 41e87f: 90 nop + 41e880: 48 8b 74 24 28 mov 0x28(%rsp),%rsi + 41e885: 48 89 ef mov %rbp,%rdi + 41e888: ff d0 callq *%rax + 41e88a: 31 f6 xor %esi,%esi + 41e88c: 48 85 c0 test %rax,%rax + 41e88f: 48 89 ea mov %rbp,%rdx + 41e892: 48 89 c7 mov %rax,%rdi + 41e895: 75 d9 jne 41e870 <__calloc+0x2b0> + 41e897: 31 c0 xor %eax,%eax + 41e899: e9 56 fe ff ff jmpq 41e6f4 <__calloc+0x134> + 41e89e: 66 90 xchg %ax,%ax + 41e8a0: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 41e8a7: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) + 41e8ae: 31 c0 xor %eax,%eax + 41e8b0: e9 3f fe ff ff jmpq 41e6f4 <__calloc+0x134> + 41e8b5: 0f 1f 00 nopl (%rax) + 41e8b8: 31 f6 xor %esi,%esi + 41e8ba: 48 89 ef mov %rbp,%rdi + 41e8bd: e8 8e 8b ff ff callq 417450 + 41e8c2: 48 85 c0 test %rax,%rax + 41e8c5: 48 89 c3 mov %rax,%rbx + 41e8c8: 0f 85 6f fd ff ff jne 41e63d <__calloc+0x7d> + 41e8ce: 31 ff xor %edi,%edi + 41e8d0: 48 89 ee mov %rbp,%rsi + 41e8d3: e8 68 cc ff ff callq 41b540 <_int_malloc> + 41e8d8: 48 85 c0 test %rax,%rax + 41e8db: 49 89 c0 mov %rax,%r8 + 41e8de: 74 b7 je 41e897 <__calloc+0x2d7> + 41e8e0: 48 8b 40 f8 mov -0x8(%rax),%rax + 41e8e4: a8 02 test $0x2,%al + 41e8e6: 0f 84 54 ff ff ff je 41e840 <__calloc+0x280> + 41e8ec: 45 31 e4 xor %r12d,%r12d + 41e8ef: 45 31 ed xor %r13d,%r13d + 41e8f2: e9 e3 fd ff ff jmpq 41e6da <__calloc+0x11a> + 41e8f7: b9 f8 2d 4a 00 mov $0x4a2df8,%ecx + 41e8fc: ba a8 0c 00 00 mov $0xca8,%edx + 41e901: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 41e906: bf 78 2a 4a 00 mov $0x4a2a78,%edi + 41e90b: e8 10 85 ff ff callq 416e20 <__malloc_assert> + 41e910: b9 f8 2d 4a 00 mov $0x4a2df8,%ecx + 41e915: ba d3 0c 00 00 mov $0xcd3,%edx + 41e91a: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 41e91f: bf e1 21 4a 00 mov $0x4a21e1,%edi + 41e924: e8 f7 84 ff ff callq 416e20 <__malloc_assert> + 41e929: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + +000000000041e930 <__malloc_usable_size>: + 41e930: 41 55 push %r13 + 41e932: 41 54 push %r12 + 41e934: 55 push %rbp + 41e935: 53 push %rbx + 41e936: 48 83 ec 28 sub $0x28,%rsp + 41e93a: 48 85 ff test %rdi,%rdi + 41e93d: 74 5a je 41e999 <__malloc_usable_size+0x69> + 41e93f: 83 3d c6 dc 2a 00 01 cmpl $0x1,0x2adcc6(%rip) # 6cc60c + 41e946: 48 8d 4f f0 lea -0x10(%rdi),%rcx + 41e94a: 74 64 je 41e9b0 <__malloc_usable_size+0x80> + 41e94c: 48 8b 47 f8 mov -0x8(%rdi),%rax + 41e950: a8 02 test $0x2,%al + 41e952: 75 1c jne 41e970 <__malloc_usable_size+0x40> + 41e954: 48 83 e0 f8 and $0xfffffffffffffff8,%rax + 41e958: f6 44 07 f8 01 testb $0x1,-0x8(%rdi,%rax,1) + 41e95d: 74 3a je 41e999 <__malloc_usable_size+0x69> + 41e95f: 48 83 e8 08 sub $0x8,%rax + 41e963: 48 83 c4 28 add $0x28,%rsp + 41e967: 5b pop %rbx + 41e968: 5d pop %rbp + 41e969: 41 5c pop %r12 + 41e96b: 41 5d pop %r13 + 41e96d: c3 retq + 41e96e: 66 90 xchg %ax,%ax + 41e970: 48 83 e0 f8 and $0xfffffffffffffff8,%rax + 41e974: 48 83 c4 28 add $0x28,%rsp + 41e978: 48 83 e8 10 sub $0x10,%rax + 41e97c: 5b pop %rbx + 41e97d: 5d pop %rbp + 41e97e: 41 5c pop %r12 + 41e980: 41 5d pop %r13 + 41e982: c3 retq + 41e983: 83 e3 02 and $0x2,%ebx + 41e986: ba d0 2a 4a 00 mov $0x4a2ad0,%edx + 41e98b: be 3c ca 4b 00 mov $0x4bca3c,%esi + 41e990: 89 df mov %ebx,%edi + 41e992: 31 c0 xor %eax,%eax + 41e994: e8 27 2c ff ff callq 4115c0 <__libc_message> + 41e999: 48 83 c4 28 add $0x28,%rsp + 41e99d: 31 c0 xor %eax,%eax + 41e99f: 5b pop %rbx + 41e9a0: 5d pop %rbp + 41e9a1: 41 5c pop %r12 + 41e9a3: 41 5d pop %r13 + 41e9a5: c3 retq + 41e9a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41e9ad: 00 00 00 + 41e9b0: 4c 8b 4f f8 mov -0x8(%rdi),%r9 + 41e9b4: 49 89 c8 mov %rcx,%r8 + 41e9b7: 48 89 c8 mov %rcx,%rax + 41e9ba: 48 c1 e8 0b shr $0xb,%rax + 41e9be: 49 c1 e8 03 shr $0x3,%r8 + 41e9c2: 41 31 c0 xor %eax,%r8d + 41e9c5: b8 02 00 00 00 mov $0x2,%eax + 41e9ca: 41 80 f8 01 cmp $0x1,%r8b + 41e9ce: 4d 89 ca mov %r9,%r10 + 41e9d1: 4c 89 ca mov %r9,%rdx + 41e9d4: 44 0f 44 c0 cmove %eax,%r8d + 41e9d8: 41 83 e2 02 and $0x2,%r10d + 41e9dc: 48 83 e2 f8 and $0xfffffffffffffff8,%rdx + 41e9e0: 49 83 fa 01 cmp $0x1,%r10 + 41e9e4: 48 19 c0 sbb %rax,%rax + 41e9e7: 83 e0 08 and $0x8,%eax + 41e9ea: 48 8d 44 02 ff lea -0x1(%rdx,%rax,1),%rax + 41e9ef: 0f b6 54 07 f0 movzbl -0x10(%rdi,%rax,1),%edx + 41e9f4: 44 38 c2 cmp %r8b,%dl + 41e9f7: 0f 84 77 ff ff ff je 41e974 <__malloc_usable_size+0x44> + 41e9fd: 84 d2 test %dl,%dl + 41e9ff: 74 2c je 41ea2d <__malloc_usable_size+0xfd> + 41ea01: 48 8d 72 10 lea 0x10(%rdx),%rsi + 41ea05: 48 39 f0 cmp %rsi,%rax + 41ea08: 73 0f jae 41ea19 <__malloc_usable_size+0xe9> + 41ea0a: eb 21 jmp 41ea2d <__malloc_usable_size+0xfd> + 41ea0c: 0f 1f 40 00 nopl 0x0(%rax) + 41ea10: 48 8d 72 10 lea 0x10(%rdx),%rsi + 41ea14: 48 39 c6 cmp %rax,%rsi + 41ea17: 77 14 ja 41ea2d <__malloc_usable_size+0xfd> + 41ea19: 48 29 d0 sub %rdx,%rax + 41ea1c: 0f b6 14 01 movzbl (%rcx,%rax,1),%edx + 41ea20: 44 38 c2 cmp %r8b,%dl + 41ea23: 0f 84 4b ff ff ff je 41e974 <__malloc_usable_size+0x44> + 41ea29: 84 d2 test %dl,%dl + 41ea2b: 75 e3 jne 41ea10 <__malloc_usable_size+0xe0> + 41ea2d: 4d 85 d2 test %r10,%r10 + 41ea30: 8b 1d 3a bd 2a 00 mov 0x2abd3a(%rip),%ebx # 6ca770 + 41ea36: 75 1d jne 41ea55 <__malloc_usable_size+0x125> + 41ea38: 41 83 e1 04 and $0x4,%r9d + 41ea3c: 0f 84 be 00 00 00 je 41eb00 <__malloc_usable_size+0x1d0> + 41ea42: 48 81 e1 00 00 00 fc and $0xfffffffffc000000,%rcx + 41ea49: 48 8b 01 mov (%rcx),%rax + 41ea4c: 48 85 c0 test %rax,%rax + 41ea4f: 74 04 je 41ea55 <__malloc_usable_size+0x125> + 41ea51: 83 48 04 04 orl $0x4,0x4(%rax) + 41ea55: 89 d8 mov %ebx,%eax + 41ea57: 83 e0 05 and $0x5,%eax + 41ea5a: 83 f8 05 cmp $0x5,%eax + 41ea5d: 0f 84 20 ff ff ff je 41e983 <__malloc_usable_size+0x53> + 41ea63: f6 c3 01 test $0x1,%bl + 41ea66: 75 18 jne 41ea80 <__malloc_usable_size+0x150> + 41ea68: 83 e3 02 and $0x2,%ebx + 41ea6b: 0f 84 28 ff ff ff je 41e999 <__malloc_usable_size+0x69> + 41ea71: e8 8a f1 fe ff callq 40dc00 + 41ea76: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41ea7d: 00 00 00 + 41ea80: 48 8d 74 24 10 lea 0x10(%rsp),%rsi + 41ea85: 31 c9 xor %ecx,%ecx + 41ea87: ba 10 00 00 00 mov $0x10,%edx + 41ea8c: c6 44 24 10 00 movb $0x0,0x10(%rsp) + 41ea91: e8 1a 34 03 00 callq 451eb0 <_itoa_word> + 41ea96: 48 39 e0 cmp %rsp,%rax + 41ea99: 48 89 c5 mov %rax,%rbp + 41ea9c: 76 25 jbe 41eac3 <__malloc_usable_size+0x193> + 41ea9e: 48 89 c2 mov %rax,%rdx + 41eaa1: 48 89 c7 mov %rax,%rdi + 41eaa4: be 30 00 00 00 mov $0x30,%esi + 41eaa9: 48 29 e2 sub %rsp,%rdx + 41eaac: 4c 8d 68 ff lea -0x1(%rax),%r13 + 41eab0: 48 29 d7 sub %rdx,%rdi + 41eab3: e8 98 18 fe ff callq 400350 <__rela_iplt_end+0x88> + 41eab8: 48 8d 44 24 ff lea -0x1(%rsp),%rax + 41eabd: 4c 29 e8 sub %r13,%rax + 41eac0: 48 01 c5 add %rax,%rbp + 41eac3: 48 8b 05 f6 e7 2a 00 mov 0x2ae7f6(%rip),%rax # 6cd2c0 <__libc_argv> + 41eaca: ba 38 20 4a 00 mov $0x4a2038,%edx + 41eacf: 49 89 e8 mov %rbp,%r8 + 41ead2: b9 d0 2a 4a 00 mov $0x4a2ad0,%ecx + 41ead7: be a8 23 4a 00 mov $0x4a23a8,%esi + 41eadc: 48 8b 00 mov (%rax),%rax + 41eadf: 48 85 c0 test %rax,%rax + 41eae2: 48 0f 45 d0 cmovne %rax,%rdx + 41eae6: 83 e3 02 and $0x2,%ebx + 41eae9: 31 c0 xor %eax,%eax + 41eaeb: 89 df mov %ebx,%edi + 41eaed: e8 ce 2a ff ff callq 4115c0 <__libc_message> + 41eaf2: 31 c0 xor %eax,%eax + 41eaf4: e9 6a fe ff ff jmpq 41e963 <__malloc_usable_size+0x33> + 41eaf9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 41eb00: b8 00 a8 6c 00 mov $0x6ca800,%eax + 41eb05: e9 47 ff ff ff jmpq 41ea51 <__malloc_usable_size+0x121> + 41eb0a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + +000000000041eb10 <__libc_mallopt>: + 41eb10: 55 push %rbp + 41eb11: 53 push %rbx + 41eb12: 48 63 ee movslq %esi,%rbp + 41eb15: 89 fb mov %edi,%ebx + 41eb17: 48 83 ec 08 sub $0x8,%rsp + 41eb1b: 8b 05 43 bc 2a 00 mov 0x2abc43(%rip),%eax # 6ca764 <__libc_malloc_initialized> + 41eb21: 85 c0 test %eax,%eax + 41eb23: 0f 88 b7 01 00 00 js 41ece0 <__libc_mallopt+0x1d0> + 41eb29: be 01 00 00 00 mov $0x1,%esi + 41eb2e: 31 c0 xor %eax,%eax + 41eb30: 83 3d 85 e6 2a 00 00 cmpl $0x0,0x2ae685(%rip) # 6cd1bc <__libc_multiple_threads> + 41eb37: 74 0c je 41eb45 <__libc_mallopt+0x35> + 41eb39: f0 0f b1 35 bf bc 2a lock cmpxchg %esi,0x2abcbf(%rip) # 6ca800 + 41eb40: 00 + 41eb41: 75 0b jne 41eb4e <__libc_mallopt+0x3e> + 41eb43: eb 23 jmp 41eb68 <__libc_mallopt+0x58> + 41eb45: 0f b1 35 b4 bc 2a 00 cmpxchg %esi,0x2abcb4(%rip) # 6ca800 + 41eb4c: 74 1a je 41eb68 <__libc_mallopt+0x58> + 41eb4e: 48 8d 3d ab bc 2a 00 lea 0x2abcab(%rip),%rdi # 6ca800 + 41eb55: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41eb5c: e8 6f 3a 02 00 callq 4425d0 <__lll_lock_wait_private> + 41eb61: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41eb68: bf 00 a8 6c 00 mov $0x6ca800,%edi + 41eb6d: e8 be 92 ff ff callq 417e30 + 41eb72: 90 nop + 41eb73: 83 c3 08 add $0x8,%ebx + 41eb76: 83 fb 09 cmp $0x9,%ebx + 41eb79: 0f 87 ba 00 00 00 ja 41ec39 <__libc_mallopt+0x129> + 41eb7f: ff 24 dd d8 2e 4a 00 jmpq *0x4a2ed8(,%rbx,8) + 41eb86: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41eb8d: 00 00 00 + 41eb90: 31 d2 xor %edx,%edx + 41eb92: 81 fd a0 00 00 00 cmp $0xa0,%ebp + 41eb98: 77 37 ja 41ebd1 <__libc_mallopt+0xc1> + 41eb9a: 90 nop + 41eb9b: 85 ed test %ebp,%ebp + 41eb9d: b8 10 00 00 00 mov $0x10,%eax + 41eba2: 74 08 je 41ebac <__libc_mallopt+0x9c> + 41eba4: 48 8d 45 08 lea 0x8(%rbp),%rax + 41eba8: 48 83 e0 f0 and $0xfffffffffffffff0,%rax + 41ebac: 48 89 05 85 da 2a 00 mov %rax,0x2ada85(%rip) # 6cc638 + 41ebb3: ba 01 00 00 00 mov $0x1,%edx + 41ebb8: eb 17 jmp 41ebd1 <__libc_mallopt+0xc1> + 41ebba: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 41ebc0: 85 ed test %ebp,%ebp + 41ebc2: 7e 75 jle 41ec39 <__libc_mallopt+0x129> + 41ebc4: 90 nop + 41ebc5: ba 01 00 00 00 mov $0x1,%edx + 41ebca: 48 89 2d ef bb 2a 00 mov %rbp,0x2abbef(%rip) # 6ca7c0 + 41ebd1: 83 3d e4 e5 2a 00 00 cmpl $0x0,0x2ae5e4(%rip) # 6cd1bc <__libc_multiple_threads> + 41ebd8: 74 0b je 41ebe5 <__libc_mallopt+0xd5> + 41ebda: f0 ff 0d 1f bc 2a 00 lock decl 0x2abc1f(%rip) # 6ca800 + 41ebe1: 75 0a jne 41ebed <__libc_mallopt+0xdd> + 41ebe3: eb 22 jmp 41ec07 <__libc_mallopt+0xf7> + 41ebe5: ff 0d 15 bc 2a 00 decl 0x2abc15(%rip) # 6ca800 + 41ebeb: 74 1a je 41ec07 <__libc_mallopt+0xf7> + 41ebed: 48 8d 3d 0c bc 2a 00 lea 0x2abc0c(%rip),%rdi # 6ca800 + 41ebf4: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41ebfb: e8 00 3a 02 00 callq 442600 <__lll_unlock_wake_private> + 41ec00: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41ec07: 48 83 c4 08 add $0x8,%rsp + 41ec0b: 89 d0 mov %edx,%eax + 41ec0d: 5b pop %rbx + 41ec0e: 5d pop %rbp + 41ec0f: c3 retq + 41ec10: 85 ed test %ebp,%ebp + 41ec12: 7e 25 jle 41ec39 <__libc_mallopt+0x129> + 41ec14: 90 nop + 41ec15: ba 01 00 00 00 mov $0x1,%edx + 41ec1a: 48 89 2d 97 bb 2a 00 mov %rbp,0x2abb97(%rip) # 6ca7b8 + 41ec21: eb ae jmp 41ebd1 <__libc_mallopt+0xc1> + 41ec23: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41ec28: 90 nop + 41ec29: c7 05 a1 bb 2a 00 01 movl $0x1,0x2abba1(%rip) # 6ca7d4 + 41ec30: 00 00 00 + 41ec33: 89 2d 93 bb 2a 00 mov %ebp,0x2abb93(%rip) # 6ca7cc + 41ec39: ba 01 00 00 00 mov $0x1,%edx + 41ec3e: eb 91 jmp 41ebd1 <__libc_mallopt+0xc1> + 41ec40: 31 d2 xor %edx,%edx + 41ec42: 81 fd 00 00 00 02 cmp $0x2000000,%ebp + 41ec48: 0f 87 83 ff ff ff ja 41ebd1 <__libc_mallopt+0xc1> + 41ec4e: 90 nop + 41ec4f: c7 05 7b bb 2a 00 01 movl $0x1,0x2abb7b(%rip) # 6ca7d4 + 41ec56: 00 00 00 + 41ec59: 48 89 2d 50 bb 2a 00 mov %rbp,0x2abb50(%rip) # 6ca7b0 + 41ec60: ba 01 00 00 00 mov $0x1,%edx + 41ec65: e9 67 ff ff ff jmpq 41ebd1 <__libc_mallopt+0xc1> + 41ec6a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 41ec70: 90 nop + 41ec71: c7 05 59 bb 2a 00 01 movl $0x1,0x2abb59(%rip) # 6ca7d4 + 41ec78: 00 00 00 + 41ec7b: 48 89 2d 26 bb 2a 00 mov %rbp,0x2abb26(%rip) # 6ca7a8 + 41ec82: ba 01 00 00 00 mov $0x1,%edx + 41ec87: e9 45 ff ff ff jmpq 41ebd1 <__libc_mallopt+0xc1> + 41ec8c: 0f 1f 40 00 nopl 0x0(%rax) + 41ec90: 90 nop + 41ec91: c7 05 39 bb 2a 00 01 movl $0x1,0x2abb39(%rip) # 6ca7d4 + 41ec98: 00 00 00 + 41ec9b: 48 89 2d fe ba 2a 00 mov %rbp,0x2abafe(%rip) # 6ca7a0 + 41eca2: ba 01 00 00 00 mov $0x1,%edx + 41eca7: e9 25 ff ff ff jmpq 41ebd1 <__libc_mallopt+0xc1> + 41ecac: 0f 1f 40 00 nopl 0x0(%rax) + 41ecb0: 90 nop + 41ecb1: ba 01 00 00 00 mov $0x1,%edx + 41ecb6: 89 2d 78 d9 2a 00 mov %ebp,0x2ad978(%rip) # 6cc634 + 41ecbc: e9 10 ff ff ff jmpq 41ebd1 <__libc_mallopt+0xc1> + 41ecc1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 41ecc8: 90 nop + 41ecc9: ba 01 00 00 00 mov $0x1,%edx + 41ecce: 89 2d 9c ba 2a 00 mov %ebp,0x2aba9c(%rip) # 6ca770 + 41ecd4: e9 f8 fe ff ff jmpq 41ebd1 <__libc_mallopt+0xc1> + 41ecd9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 41ece0: e8 0b 00 00 00 callq 41ecf0 + 41ece5: e9 3f fe ff ff jmpq 41eb29 <__libc_mallopt+0x19> + 41ecea: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + +000000000041ecf0 : + 41ecf0: 41 55 push %r13 + 41ecf2: 41 54 push %r12 + 41ecf4: 55 push %rbp + 41ecf5: 53 push %rbx + 41ecf6: 48 83 ec 08 sub $0x8,%rsp + 41ecfa: 4c 8b 25 3f d9 2a 00 mov 0x2ad93f(%rip),%r12 # 6cc640 <__environ> + 41ed01: 48 c7 c0 d8 ff ff ff mov $0xffffffffffffffd8,%rax + 41ed08: c7 05 52 ba 2a 00 00 movl $0x0,0x2aba52(%rip) # 6ca764 <__libc_malloc_initialized> + 41ed0f: 00 00 00 + 41ed12: 4d 85 e4 test %r12,%r12 + 41ed15: 64 48 c7 00 00 a8 6c movq $0x6ca800,%fs:(%rax) + 41ed1c: 00 + 41ed1d: 0f 84 9b 00 00 00 je 41edbe + 41ed23: 45 31 ed xor %r13d,%r13d + 41ed26: eb 0c jmp 41ed34 + 41ed28: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 41ed2f: 00 + 41ed30: 49 83 c4 08 add $0x8,%r12 + 41ed34: 49 8b 1c 24 mov (%r12),%rbx + 41ed38: 48 85 db test %rbx,%rbx + 41ed3b: 74 73 je 41edb0 + 41ed3d: 80 3b 4d cmpb $0x4d,(%rbx) + 41ed40: 75 ee jne 41ed30 + 41ed42: 80 7b 01 41 cmpb $0x41,0x1(%rbx) + 41ed46: 75 e8 jne 41ed30 + 41ed48: 80 7b 02 4c cmpb $0x4c,0x2(%rbx) + 41ed4c: 75 e2 jne 41ed30 + 41ed4e: 80 7b 03 4c cmpb $0x4c,0x3(%rbx) + 41ed52: 75 dc jne 41ed30 + 41ed54: 80 7b 04 4f cmpb $0x4f,0x4(%rbx) + 41ed58: 75 d6 jne 41ed30 + 41ed5a: 80 7b 05 43 cmpb $0x43,0x5(%rbx) + 41ed5e: 75 d0 jne 41ed30 + 41ed60: 80 7b 06 5f cmpb $0x5f,0x6(%rbx) + 41ed64: 75 ca jne 41ed30 + 41ed66: 48 89 dd mov %rbx,%rbp + 41ed69: 49 83 c4 08 add $0x8,%r12 + 41ed6d: 48 83 c5 07 add $0x7,%rbp + 41ed71: 74 3d je 41edb0 + 41ed73: 0f b6 53 07 movzbl 0x7(%rbx),%edx + 41ed77: 84 d2 test %dl,%dl + 41ed79: 74 b9 je 41ed34 + 41ed7b: 31 c0 xor %eax,%eax + 41ed7d: 80 fa 3d cmp $0x3d,%dl + 41ed80: 74 b2 je 41ed34 + 41ed82: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 41ed88: 48 83 c0 01 add $0x1,%rax + 41ed8c: 0f b6 54 03 07 movzbl 0x7(%rbx,%rax,1),%edx + 41ed91: 84 d2 test %dl,%dl + 41ed93: 74 9f je 41ed34 + 41ed95: 80 fa 3d cmp $0x3d,%dl + 41ed98: 75 ee jne 41ed88 + 41ed9a: 48 83 e8 06 sub $0x6,%rax + 41ed9e: 48 83 f8 09 cmp $0x9,%rax + 41eda2: 77 90 ja 41ed34 + 41eda4: ff 24 c5 28 2f 4a 00 jmpq *0x4a2f28(,%rax,8) + 41edab: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41edb0: 4d 85 ed test %r13,%r13 + 41edb3: 74 09 je 41edbe + 41edb5: 41 0f be 45 00 movsbl 0x0(%r13),%eax + 41edba: 84 c0 test %al,%al + 41edbc: 75 2a jne 41ede8 + 41edbe: 48 8b 05 2b d8 2a 00 mov 0x2ad82b(%rip),%rax # 6cc5f0 <__malloc_initialize_hook> + 41edc5: 48 85 c0 test %rax,%rax + 41edc8: 74 02 je 41edcc + 41edca: ff d0 callq *%rax + 41edcc: c7 05 8e b9 2a 00 01 movl $0x1,0x2ab98e(%rip) # 6ca764 <__libc_malloc_initialized> + 41edd3: 00 00 00 + 41edd6: 48 83 c4 08 add $0x8,%rsp + 41edda: 5b pop %rbx + 41eddb: 5d pop %rbp + 41eddc: 41 5c pop %r12 + 41edde: 41 5d pop %r13 + 41ede0: c3 retq + 41ede1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 41ede8: 8d 70 d0 lea -0x30(%rax),%esi + 41edeb: bf fb ff ff ff mov $0xfffffffb,%edi + 41edf0: e8 1b fd ff ff callq 41eb10 <__libc_mallopt> + 41edf5: 8b 15 75 b9 2a 00 mov 0x2ab975(%rip),%edx # 6ca770 + 41edfb: 85 d2 test %edx,%edx + 41edfd: 74 bf je 41edbe + 41edff: 8b 05 03 d8 2a 00 mov 0x2ad803(%rip),%eax # 6cc608 + 41ee05: 85 c0 test %eax,%eax + 41ee07: 0f 84 ac 01 00 00 je 41efb9 + 41ee0d: c7 05 f1 d7 2a 00 00 movl $0x0,0x2ad7f1(%rip) # 6cc608 + 41ee14: 00 00 00 + 41ee17: eb a5 jmp 41edbe + 41ee19: 8b 0d 79 b1 2a 00 mov 0x2ab179(%rip),%ecx # 6c9f98 <__libc_enable_secure> + 41ee1f: 85 c9 test %ecx,%ecx + 41ee21: 0f 85 0d ff ff ff jne 41ed34 + 41ee27: ba 0f 00 00 00 mov $0xf,%edx + 41ee2c: be 1f 22 4a 00 mov $0x4a221f,%esi + 41ee31: 48 89 ef mov %rbp,%rdi + 41ee34: e8 f7 14 fe ff callq 400330 <__rela_iplt_end+0x68> + 41ee39: 85 c0 test %eax,%eax + 41ee3b: 0f 84 d4 01 00 00 je 41f015 + 41ee41: ba 0f 00 00 00 mov $0xf,%edx + 41ee46: be 2f 22 4a 00 mov $0x4a222f,%esi + 41ee4b: 48 89 ef mov %rbp,%rdi + 41ee4e: e8 dd 14 fe ff callq 400330 <__rela_iplt_end+0x68> + 41ee53: 85 c0 test %eax,%eax + 41ee55: 0f 85 d9 fe ff ff jne 41ed34 + 41ee5b: 48 8d 7b 17 lea 0x17(%rbx),%rdi + 41ee5f: 31 f6 xor %esi,%esi + 41ee61: ba 0a 00 00 00 mov $0xa,%edx + 41ee66: e8 65 2b 03 00 callq 4519d0 <__strtol> + 41ee6b: bf fd ff ff ff mov $0xfffffffd,%edi + 41ee70: 89 c6 mov %eax,%esi + 41ee72: e8 99 fc ff ff callq 41eb10 <__libc_mallopt> + 41ee77: e9 b8 fe ff ff jmpq 41ed34 + 41ee7c: 0f 1f 40 00 nopl 0x0(%rax) + 41ee80: 8b 35 12 b1 2a 00 mov 0x2ab112(%rip),%esi # 6c9f98 <__libc_enable_secure> + 41ee86: 85 f6 test %esi,%esi + 41ee88: 0f 85 a6 fe ff ff jne 41ed34 + 41ee8e: ba 0a 00 00 00 mov $0xa,%edx + 41ee93: be 14 22 4a 00 mov $0x4a2214,%esi + 41ee98: 48 89 ef mov %rbp,%rdi + 41ee9b: e8 90 14 fe ff callq 400330 <__rela_iplt_end+0x68> + 41eea0: 85 c0 test %eax,%eax + 41eea2: 0f 85 8c fe ff ff jne 41ed34 + 41eea8: 48 8d 7b 12 lea 0x12(%rbx),%rdi + 41eeac: 31 f6 xor %esi,%esi + 41eeae: ba 0a 00 00 00 mov $0xa,%edx + 41eeb3: e8 18 2b 03 00 callq 4519d0 <__strtol> + 41eeb8: bf f9 ff ff ff mov $0xfffffff9,%edi + 41eebd: 89 c6 mov %eax,%esi + 41eebf: e8 4c fc ff ff callq 41eb10 <__libc_mallopt> + 41eec4: e9 6b fe ff ff jmpq 41ed34 + 41eec9: 8b 3d c9 b0 2a 00 mov 0x2ab0c9(%rip),%edi # 6c9f98 <__libc_enable_secure> + 41eecf: 85 ff test %edi,%edi + 41eed1: 0f 85 5d fe ff ff jne 41ed34 + 41eed7: ba 09 00 00 00 mov $0x9,%edx + 41eedc: be 00 22 4a 00 mov $0x4a2200,%esi + 41eee1: 48 89 ef mov %rbp,%rdi + 41eee4: e8 47 14 fe ff callq 400330 <__rela_iplt_end+0x68> + 41eee9: 85 c0 test %eax,%eax + 41eeeb: 0f 84 45 01 00 00 je 41f036 + 41eef1: ba 09 00 00 00 mov $0x9,%edx + 41eef6: be 0a 22 4a 00 mov $0x4a220a,%esi + 41eefb: 48 89 ef mov %rbp,%rdi + 41eefe: e8 2d 14 fe ff callq 400330 <__rela_iplt_end+0x68> + 41ef03: 85 c0 test %eax,%eax + 41ef05: 0f 85 29 fe ff ff jne 41ed34 + 41ef0b: 48 8d 7b 11 lea 0x11(%rbx),%rdi + 41ef0f: 31 f6 xor %esi,%esi + 41ef11: ba 0a 00 00 00 mov $0xa,%edx + 41ef16: e8 b5 2a 03 00 callq 4519d0 <__strtol> + 41ef1b: bf f8 ff ff ff mov $0xfffffff8,%edi + 41ef20: 89 c6 mov %eax,%esi + 41ef22: e8 e9 fb ff ff callq 41eb10 <__libc_mallopt> + 41ef27: e9 08 fe ff ff jmpq 41ed34 + 41ef2c: 0f 1f 40 00 nopl 0x0(%rax) + 41ef30: 44 8b 05 61 b0 2a 00 mov 0x2ab061(%rip),%r8d # 6c9f98 <__libc_enable_secure> + 41ef37: 45 85 c0 test %r8d,%r8d + 41ef3a: 0f 85 f4 fd ff ff jne 41ed34 + 41ef40: ba 08 00 00 00 mov $0x8,%edx + 41ef45: be ee 21 4a 00 mov $0x4a21ee,%esi + 41ef4a: 48 89 ef mov %rbp,%rdi + 41ef4d: e8 de 13 fe ff callq 400330 <__rela_iplt_end+0x68> + 41ef52: 85 c0 test %eax,%eax + 41ef54: 0f 84 9a 00 00 00 je 41eff4 + 41ef5a: ba 08 00 00 00 mov $0x8,%edx + 41ef5f: be f7 21 4a 00 mov $0x4a21f7,%esi + 41ef64: 48 89 ef mov %rbp,%rdi + 41ef67: e8 c4 13 fe ff callq 400330 <__rela_iplt_end+0x68> + 41ef6c: 85 c0 test %eax,%eax + 41ef6e: 0f 85 c0 fd ff ff jne 41ed34 + 41ef74: 48 8d 7b 10 lea 0x10(%rbx),%rdi + 41ef78: 31 f6 xor %esi,%esi + 41ef7a: ba 0a 00 00 00 mov $0xa,%edx + 41ef7f: e8 4c 2a 03 00 callq 4519d0 <__strtol> + 41ef84: bf fa ff ff ff mov $0xfffffffa,%edi + 41ef89: 89 c6 mov %eax,%esi + 41ef8b: e8 80 fb ff ff callq 41eb10 <__libc_mallopt> + 41ef90: e9 9f fd ff ff jmpq 41ed34 + 41ef95: 0f 1f 00 nopl (%rax) + 41ef98: ba 06 00 00 00 mov $0x6,%edx + 41ef9d: be b9 4f 4a 00 mov $0x4a4fb9,%esi + 41efa2: 48 89 ef mov %rbp,%rdi + 41efa5: 48 83 c3 0e add $0xe,%rbx + 41efa9: e8 82 13 fe ff callq 400330 <__rela_iplt_end+0x68> + 41efae: 85 c0 test %eax,%eax + 41efb0: 4c 0f 44 eb cmove %rbx,%r13 + 41efb4: e9 7b fd ff ff jmpq 41ed34 + 41efb9: c7 05 49 d6 2a 00 01 movl $0x1,0x2ad649(%rip) # 6cc60c + 41efc0: 00 00 00 + 41efc3: 48 c7 05 ba b7 2a 00 movq $0x41c720,0x2ab7ba(%rip) # 6ca788 <__malloc_hook> + 41efca: 20 c7 41 00 + 41efce: 48 c7 05 0f d6 2a 00 movq $0x4189e0,0x2ad60f(%rip) # 6cc5e8 <__free_hook> + 41efd5: e0 89 41 00 + 41efd9: 48 c7 05 9c b7 2a 00 movq $0x41d180,0x2ab79c(%rip) # 6ca780 <__realloc_hook> + 41efe0: 80 d1 41 00 + 41efe4: 48 c7 05 89 b7 2a 00 movq $0x41c870,0x2ab789(%rip) # 6ca778 <__memalign_hook> + 41efeb: 70 c8 41 00 + 41efef: e9 ca fd ff ff jmpq 41edbe + 41eff4: 48 8d 7b 10 lea 0x10(%rbx),%rdi + 41eff8: 31 f6 xor %esi,%esi + 41effa: ba 0a 00 00 00 mov $0xa,%edx + 41efff: e8 cc 29 03 00 callq 4519d0 <__strtol> + 41f004: bf fe ff ff ff mov $0xfffffffe,%edi + 41f009: 89 c6 mov %eax,%esi + 41f00b: e8 00 fb ff ff callq 41eb10 <__libc_mallopt> + 41f010: e9 1f fd ff ff jmpq 41ed34 + 41f015: 48 8d 7b 17 lea 0x17(%rbx),%rdi + 41f019: 31 f6 xor %esi,%esi + 41f01b: ba 0a 00 00 00 mov $0xa,%edx + 41f020: e8 ab 29 03 00 callq 4519d0 <__strtol> + 41f025: bf ff ff ff ff mov $0xffffffff,%edi + 41f02a: 89 c6 mov %eax,%esi + 41f02c: e8 df fa ff ff callq 41eb10 <__libc_mallopt> + 41f031: e9 fe fc ff ff jmpq 41ed34 + 41f036: 48 8d 7b 11 lea 0x11(%rbx),%rdi + 41f03a: 31 f6 xor %esi,%esi + 41f03c: ba 0a 00 00 00 mov $0xa,%edx + 41f041: e8 8a 29 03 00 callq 4519d0 <__strtol> + 41f046: bf fc ff ff ff mov $0xfffffffc,%edi + 41f04b: 89 c6 mov %eax,%esi + 41f04d: e8 be fa ff ff callq 41eb10 <__libc_mallopt> + 41f052: e9 dd fc ff ff jmpq 41ed34 + 41f057: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 41f05e: 00 00 + +000000000041f060 : + 41f060: 55 push %rbp + 41f061: 53 push %rbx + 41f062: 48 89 fd mov %rdi,%rbp + 41f065: 48 83 ec 08 sub $0x8,%rsp + 41f069: 8b 05 f5 b6 2a 00 mov 0x2ab6f5(%rip),%eax # 6ca764 <__libc_malloc_initialized> + 41f06f: 48 c7 05 0e b7 2a 00 movq $0x0,0x2ab70e(%rip) # 6ca788 <__malloc_hook> + 41f076: 00 00 00 00 + 41f07a: 85 c0 test %eax,%eax + 41f07c: 0f 88 46 01 00 00 js 41f1c8 + 41f082: 31 c0 xor %eax,%eax + 41f084: 48 85 c0 test %rax,%rax + 41f087: 0f 85 50 01 00 00 jne 41f1dd + 41f08d: 48 c7 c0 d8 ff ff ff mov $0xffffffffffffffd8,%rax + 41f094: 64 48 8b 18 mov %fs:(%rax),%rbx + 41f098: 48 85 db test %rbx,%rbx + 41f09b: 74 0c je 41f0a9 + 41f09d: 8b 43 04 mov 0x4(%rbx),%eax + 41f0a0: 83 e0 04 and $0x4,%eax + 41f0a3: 0f 84 8f 00 00 00 je 41f138 + 41f0a9: e8 b2 80 ff ff callq 417160 + 41f0ae: 48 85 c0 test %rax,%rax + 41f0b1: 48 89 c3 mov %rax,%rbx + 41f0b4: 0f 84 b6 00 00 00 je 41f170 + 41f0ba: 48 89 ee mov %rbp,%rsi + 41f0bd: 48 89 df mov %rbx,%rdi + 41f0c0: e8 7b c4 ff ff callq 41b540 <_int_malloc> + 41f0c5: 48 85 c0 test %rax,%rax + 41f0c8: 48 89 c2 mov %rax,%rdx + 41f0cb: 0f 84 c7 00 00 00 je 41f198 + 41f0d1: 83 3d e4 e0 2a 00 00 cmpl $0x0,0x2ae0e4(%rip) # 6cd1bc <__libc_multiple_threads> + 41f0d8: 74 07 je 41f0e1 + 41f0da: f0 ff 0b lock decl (%rbx) + 41f0dd: 75 06 jne 41f0e5 + 41f0df: eb 1a jmp 41f0fb + 41f0e1: ff 0b decl (%rbx) + 41f0e3: 74 16 je 41f0fb + 41f0e5: 48 8d 3b lea (%rbx),%rdi + 41f0e8: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41f0ef: e8 0c 35 02 00 callq 442600 <__lll_unlock_wake_private> + 41f0f4: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41f0fb: 48 85 d2 test %rdx,%rdx + 41f0fe: 0f 84 ec 00 00 00 je 41f1f0 + 41f104: 48 8b 42 f8 mov -0x8(%rdx),%rax + 41f108: a8 02 test $0x2,%al + 41f10a: 75 1f jne 41f12b + 41f10c: a8 04 test $0x4,%al + 41f10e: b9 00 a8 6c 00 mov $0x6ca800,%ecx + 41f113: 74 0d je 41f122 + 41f115: 48 8d 42 f0 lea -0x10(%rdx),%rax + 41f119: 48 25 00 00 00 fc and $0xfffffffffc000000,%rax + 41f11f: 48 8b 08 mov (%rax),%rcx + 41f122: 48 39 d9 cmp %rbx,%rcx + 41f125: 0f 85 cc 00 00 00 jne 41f1f7 + 41f12b: 48 89 d0 mov %rdx,%rax + 41f12e: 48 83 c4 08 add $0x8,%rsp + 41f132: 5b pop %rbx + 41f133: 5d pop %rbp + 41f134: c3 retq + 41f135: 0f 1f 00 nopl (%rax) + 41f138: be 01 00 00 00 mov $0x1,%esi + 41f13d: 83 3d 78 e0 2a 00 00 cmpl $0x0,0x2ae078(%rip) # 6cd1bc <__libc_multiple_threads> + 41f144: 74 08 je 41f14e + 41f146: f0 0f b1 33 lock cmpxchg %esi,(%rbx) + 41f14a: 75 07 jne 41f153 + 41f14c: eb 1b jmp 41f169 + 41f14e: 0f b1 33 cmpxchg %esi,(%rbx) + 41f151: 74 16 je 41f169 + 41f153: 48 8d 3b lea (%rbx),%rdi + 41f156: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41f15d: e8 6e 34 02 00 callq 4425d0 <__lll_lock_wait_private> + 41f162: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41f169: e9 4c ff ff ff jmpq 41f0ba + 41f16e: 66 90 xchg %ax,%ax + 41f170: 31 f6 xor %esi,%esi + 41f172: 48 89 ef mov %rbp,%rdi + 41f175: e8 d6 82 ff ff callq 417450 + 41f17a: 48 89 ee mov %rbp,%rsi + 41f17d: 48 89 c7 mov %rax,%rdi + 41f180: 48 89 c3 mov %rax,%rbx + 41f183: e8 b8 c3 ff ff callq 41b540 <_int_malloc> + 41f188: 48 85 c0 test %rax,%rax + 41f18b: 48 89 c2 mov %rax,%rdx + 41f18e: 75 25 jne 41f1b5 + 41f190: 48 85 db test %rbx,%rbx + 41f193: 74 20 je 41f1b5 + 41f195: 0f 1f 00 nopl (%rax) + 41f198: 90 nop + 41f199: 48 89 df mov %rbx,%rdi + 41f19c: 48 89 ee mov %rbp,%rsi + 41f19f: e8 4c 88 ff ff callq 4179f0 + 41f1a4: 48 89 ee mov %rbp,%rsi + 41f1a7: 48 89 c7 mov %rax,%rdi + 41f1aa: 48 89 c3 mov %rax,%rbx + 41f1ad: e8 8e c3 ff ff callq 41b540 <_int_malloc> + 41f1b2: 48 89 c2 mov %rax,%rdx + 41f1b5: 48 85 db test %rbx,%rbx + 41f1b8: 0f 85 13 ff ff ff jne 41f0d1 + 41f1be: e9 38 ff ff ff jmpq 41f0fb + 41f1c3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41f1c8: e8 23 fb ff ff callq 41ecf0 + 41f1cd: 48 8b 05 b4 b5 2a 00 mov 0x2ab5b4(%rip),%rax # 6ca788 <__malloc_hook> + 41f1d4: 48 85 c0 test %rax,%rax + 41f1d7: 0f 84 b0 fe ff ff je 41f08d + 41f1dd: 48 8b 74 24 18 mov 0x18(%rsp),%rsi + 41f1e2: 48 83 c4 08 add $0x8,%rsp + 41f1e6: 48 89 ef mov %rbp,%rdi + 41f1e9: 5b pop %rbx + 41f1ea: 5d pop %rbp + 41f1eb: ff e0 jmpq *%rax + 41f1ed: 0f 1f 00 nopl (%rax) + 41f1f0: 31 c0 xor %eax,%eax + 41f1f2: e9 37 ff ff ff jmpq 41f12e + 41f1f7: b9 48 2e 4a 00 mov $0x4a2e48,%ecx + 41f1fc: ba 6f 0b 00 00 mov $0xb6f,%edx + 41f201: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 41f206: bf 58 29 4a 00 mov $0x4a2958,%edi + 41f20b: e8 10 7c ff ff callq 416e20 <__malloc_assert> + +000000000041f210 : + 41f210: 41 57 push %r15 + 41f212: 41 56 push %r14 + 41f214: 41 55 push %r13 + 41f216: 41 54 push %r12 + 41f218: 49 89 f5 mov %rsi,%r13 + 41f21b: 55 push %rbp + 41f21c: 53 push %rbx + 41f21d: 48 89 fb mov %rdi,%rbx + 41f220: 48 83 ec 38 sub $0x38,%rsp + 41f224: 8b 05 3a b5 2a 00 mov 0x2ab53a(%rip),%eax # 6ca764 <__libc_malloc_initialized> + 41f22a: 48 c7 05 53 b5 2a 00 movq $0x0,0x2ab553(%rip) # 6ca788 <__malloc_hook> + 41f231: 00 00 00 00 + 41f235: 48 c7 05 40 b5 2a 00 movq $0x0,0x2ab540(%rip) # 6ca780 <__realloc_hook> + 41f23c: 00 00 00 00 + 41f240: 85 c0 test %eax,%eax + 41f242: 0f 88 18 02 00 00 js 41f460 + 41f248: 31 c0 xor %eax,%eax + 41f24a: 48 85 c0 test %rax,%rax + 41f24d: 0f 85 25 02 00 00 jne 41f478 + 41f253: 4d 85 ed test %r13,%r13 + 41f256: 75 09 jne 41f261 + 41f258: 48 85 db test %rbx,%rbx + 41f25b: 0f 85 8f 02 00 00 jne 41f4f0 + 41f261: 48 85 db test %rbx,%rbx + 41f264: 0f 84 1e 03 00 00 je 41f588 + 41f26a: 48 8b 43 f8 mov -0x8(%rbx),%rax + 41f26e: 4c 8d 73 f0 lea -0x10(%rbx),%r14 + 41f272: 49 89 c7 mov %rax,%r15 + 41f275: 48 89 c1 mov %rax,%rcx + 41f278: 49 83 e7 f8 and $0xfffffffffffffff8,%r15 + 41f27c: 83 e1 02 and $0x2,%ecx + 41f27f: 74 7f je 41f300 + 41f281: 4c 89 f8 mov %r15,%rax + 41f284: 48 f7 d8 neg %rax + 41f287: 49 39 c6 cmp %rax,%r14 + 41f28a: 0f 87 50 03 00 00 ja 41f5e0 + 41f290: 41 f6 c6 0f test $0xf,%r14b + 41f294: 0f 85 46 03 00 00 jne 41f5e0 + 41f29a: 45 31 e4 xor %r12d,%r12d + 41f29d: 49 83 fd bf cmp $0xffffffffffffffbf,%r13 + 41f2a1: 0f 87 e9 01 00 00 ja 41f490 + 41f2a7: 49 8d 45 17 lea 0x17(%r13),%rax + 41f2ab: 48 89 c2 mov %rax,%rdx + 41f2ae: 48 83 e2 f0 and $0xfffffffffffffff0,%rdx + 41f2b2: 48 83 f8 20 cmp $0x20,%rax + 41f2b6: b8 20 00 00 00 mov $0x20,%eax + 41f2bb: 48 0f 42 d0 cmovb %rax,%rdx + 41f2bf: 48 85 c9 test %rcx,%rcx + 41f2c2: 0f 84 98 00 00 00 je 41f360 + 41f2c8: 48 89 d6 mov %rdx,%rsi + 41f2cb: 4c 89 f7 mov %r14,%rdi + 41f2ce: 48 89 54 24 08 mov %rdx,0x8(%rsp) + 41f2d3: e8 48 7d ff ff callq 417020 + 41f2d8: 48 85 c0 test %rax,%rax + 41f2db: 48 8d 68 10 lea 0x10(%rax),%rbp + 41f2df: 48 8b 54 24 08 mov 0x8(%rsp),%rdx + 41f2e4: 0f 84 be 01 00 00 je 41f4a8 + 41f2ea: 48 83 c4 38 add $0x38,%rsp + 41f2ee: 48 89 e8 mov %rbp,%rax + 41f2f1: 5b pop %rbx + 41f2f2: 5d pop %rbp + 41f2f3: 41 5c pop %r12 + 41f2f5: 41 5d pop %r13 + 41f2f7: 41 5e pop %r14 + 41f2f9: 41 5f pop %r15 + 41f2fb: c3 retq + 41f2fc: 0f 1f 40 00 nopl 0x0(%rax) + 41f300: a8 04 test $0x4,%al + 41f302: 0f 84 28 01 00 00 je 41f430 + 41f308: 4c 89 f0 mov %r14,%rax + 41f30b: 48 25 00 00 00 fc and $0xfffffffffc000000,%rax + 41f311: 4c 8b 20 mov (%rax),%r12 + 41f314: 4c 89 f8 mov %r15,%rax + 41f317: 48 f7 d8 neg %rax + 41f31a: 49 39 c6 cmp %rax,%r14 + 41f31d: 77 0a ja 41f329 + 41f31f: 41 f6 c6 0f test $0xf,%r14b + 41f323: 0f 84 74 ff ff ff je 41f29d + 41f329: 4d 85 e4 test %r12,%r12 + 41f32c: 8b 2d 3e b4 2a 00 mov 0x2ab43e(%rip),%ebp # 6ca770 + 41f332: 74 06 je 41f33a + 41f334: 41 83 4c 24 04 04 orl $0x4,0x4(%r12) + 41f33a: 89 e8 mov %ebp,%eax + 41f33c: 83 e0 05 and $0x5,%eax + 41f33f: 83 f8 05 cmp $0x5,%eax + 41f342: 0f 84 a8 02 00 00 je 41f5f0 + 41f348: 40 f6 c5 01 test $0x1,%bpl + 41f34c: 0f 85 ae 01 00 00 jne 41f500 + 41f352: 83 e5 02 and $0x2,%ebp + 41f355: 0f 85 b2 02 00 00 jne 41f60d + 41f35b: 31 ed xor %ebp,%ebp + 41f35d: eb 8b jmp 41f2ea + 41f35f: 90 nop + 41f360: be 01 00 00 00 mov $0x1,%esi + 41f365: 31 c0 xor %eax,%eax + 41f367: 83 3d 4e de 2a 00 00 cmpl $0x0,0x2ade4e(%rip) # 6cd1bc <__libc_multiple_threads> + 41f36e: 74 0a je 41f37a + 41f370: f0 41 0f b1 34 24 lock cmpxchg %esi,(%r12) + 41f376: 75 09 jne 41f381 + 41f378: eb 1e jmp 41f398 + 41f37a: 41 0f b1 34 24 cmpxchg %esi,(%r12) + 41f37f: 74 17 je 41f398 + 41f381: 49 8d 3c 24 lea (%r12),%rdi + 41f385: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41f38c: e8 3f 32 02 00 callq 4425d0 <__lll_lock_wait_private> + 41f391: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41f398: 48 89 d1 mov %rdx,%rcx + 41f39b: 4c 89 f6 mov %r14,%rsi + 41f39e: 4c 89 fa mov %r15,%rdx + 41f3a1: 4c 89 e7 mov %r12,%rdi + 41f3a4: e8 b7 d6 ff ff callq 41ca60 <_int_realloc> + 41f3a9: 48 89 c5 mov %rax,%rbp + 41f3ac: 83 3d 09 de 2a 00 00 cmpl $0x0,0x2ade09(%rip) # 6cd1bc <__libc_multiple_threads> + 41f3b3: 74 09 je 41f3be + 41f3b5: f0 41 ff 0c 24 lock decl (%r12) + 41f3ba: 75 08 jne 41f3c4 + 41f3bc: eb 1d jmp 41f3db + 41f3be: 41 ff 0c 24 decl (%r12) + 41f3c2: 74 17 je 41f3db + 41f3c4: 49 8d 3c 24 lea (%r12),%rdi + 41f3c8: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41f3cf: e8 2c 32 02 00 callq 442600 <__lll_unlock_wake_private> + 41f3d4: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41f3db: 48 85 ed test %rbp,%rbp + 41f3de: 0f 84 bc 01 00 00 je 41f5a0 + 41f3e4: 48 8b 45 f8 mov -0x8(%rbp),%rax + 41f3e8: a8 02 test $0x2,%al + 41f3ea: 0f 85 fa fe ff ff jne 41f2ea + 41f3f0: a8 04 test $0x4,%al + 41f3f2: ba 00 a8 6c 00 mov $0x6ca800,%edx + 41f3f7: 74 0d je 41f406 + 41f3f9: 48 8d 45 f0 lea -0x10(%rbp),%rax + 41f3fd: 48 25 00 00 00 fc and $0xfffffffffc000000,%rax + 41f403: 48 8b 10 mov (%rax),%rdx + 41f406: 4c 39 e2 cmp %r12,%rdx + 41f409: 0f 84 db fe ff ff je 41f2ea + 41f40f: b9 18 2e 4a 00 mov $0x4a2e18,%ecx + 41f414: ba e9 0b 00 00 mov $0xbe9,%edx + 41f419: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 41f41e: bf c0 29 4a 00 mov $0x4a29c0,%edi + 41f423: e8 f8 79 ff ff callq 416e20 <__malloc_assert> + 41f428: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 41f42f: 00 + 41f430: 4c 89 f8 mov %r15,%rax + 41f433: 48 f7 d8 neg %rax + 41f436: 49 39 c6 cmp %rax,%r14 + 41f439: 77 10 ja 41f44b + 41f43b: 41 f6 c6 0f test $0xf,%r14b + 41f43f: 41 bc 00 a8 6c 00 mov $0x6ca800,%r12d + 41f445: 0f 84 52 fe ff ff je 41f29d + 41f44b: 8b 2d 1f b3 2a 00 mov 0x2ab31f(%rip),%ebp # 6ca770 + 41f451: 41 bc 00 a8 6c 00 mov $0x6ca800,%r12d + 41f457: e9 d8 fe ff ff jmpq 41f334 + 41f45c: 0f 1f 40 00 nopl 0x0(%rax) + 41f460: e8 8b f8 ff ff callq 41ecf0 + 41f465: 48 8b 05 14 b3 2a 00 mov 0x2ab314(%rip),%rax # 6ca780 <__realloc_hook> + 41f46c: 48 85 c0 test %rax,%rax + 41f46f: 0f 84 de fd ff ff je 41f253 + 41f475: 0f 1f 00 nopl (%rax) + 41f478: 48 8b 54 24 68 mov 0x68(%rsp),%rdx + 41f47d: 4c 89 ee mov %r13,%rsi + 41f480: 48 89 df mov %rbx,%rdi + 41f483: ff d0 callq *%rax + 41f485: 48 89 c5 mov %rax,%rbp + 41f488: e9 5d fe ff ff jmpq 41f2ea + 41f48d: 0f 1f 00 nopl (%rax) + 41f490: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 41f497: 31 ed xor %ebp,%ebp + 41f499: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) + 41f4a0: e9 45 fe ff ff jmpq 41f2ea + 41f4a5: 0f 1f 00 nopl (%rax) + 41f4a8: 49 8d 47 f8 lea -0x8(%r15),%rax + 41f4ac: 48 89 dd mov %rbx,%rbp + 41f4af: 48 39 c2 cmp %rax,%rdx + 41f4b2: 0f 86 32 fe ff ff jbe 41f2ea + 41f4b8: 4c 89 ef mov %r13,%rdi + 41f4bb: e8 50 e5 ff ff callq 41da10 <__libc_malloc> + 41f4c0: 48 85 c0 test %rax,%rax + 41f4c3: 48 89 c3 mov %rax,%rbx + 41f4c6: 0f 84 8f fe ff ff je 41f35b + 41f4cc: 49 8d 57 f0 lea -0x10(%r15),%rdx + 41f4d0: 48 89 ee mov %rbp,%rsi + 41f4d3: 48 89 c7 mov %rax,%rdi + 41f4d6: 48 89 dd mov %rbx,%rbp + 41f4d9: e8 42 cb 00 00 callq 42c020 + 41f4de: 4c 89 f7 mov %r14,%rdi + 41f4e1: e8 0a 88 ff ff callq 417cf0 + 41f4e6: e9 ff fd ff ff jmpq 41f2ea + 41f4eb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41f4f0: 48 89 df mov %rbx,%rdi + 41f4f3: 31 ed xor %ebp,%ebp + 41f4f5: e8 b6 e8 ff ff callq 41ddb0 <__cfree> + 41f4fa: e9 eb fd ff ff jmpq 41f2ea + 41f4ff: 90 nop + 41f500: 4c 8d 64 24 10 lea 0x10(%rsp),%r12 + 41f505: 48 8d 74 24 20 lea 0x20(%rsp),%rsi + 41f50a: 31 c9 xor %ecx,%ecx + 41f50c: 48 89 df mov %rbx,%rdi + 41f50f: ba 10 00 00 00 mov $0x10,%edx + 41f514: c6 44 24 20 00 movb $0x0,0x20(%rsp) + 41f519: e8 92 29 03 00 callq 451eb0 <_itoa_word> + 41f51e: 4c 39 e0 cmp %r12,%rax + 41f521: 48 89 c3 mov %rax,%rbx + 41f524: 76 25 jbe 41f54b + 41f526: 48 89 c2 mov %rax,%rdx + 41f529: 48 89 c7 mov %rax,%rdi + 41f52c: be 30 00 00 00 mov $0x30,%esi + 41f531: 4c 29 e2 sub %r12,%rdx + 41f534: 4c 8d 68 ff lea -0x1(%rax),%r13 + 41f538: 48 29 d7 sub %rdx,%rdi + 41f53b: e8 10 0e fe ff callq 400350 <__rela_iplt_end+0x88> + 41f540: 48 8d 44 24 0f lea 0xf(%rsp),%rax + 41f545: 4c 29 e8 sub %r13,%rax + 41f548: 48 01 c3 add %rax,%rbx + 41f54b: 48 8b 05 6e dd 2a 00 mov 0x2add6e(%rip),%rax # 6cd2c0 <__libc_argv> + 41f552: 89 ef mov %ebp,%edi + 41f554: ba 38 20 4a 00 mov $0x4a2038,%edx + 41f559: 49 89 d8 mov %rbx,%r8 + 41f55c: b9 c6 21 4a 00 mov $0x4a21c6,%ecx + 41f561: be a8 23 4a 00 mov $0x4a23a8,%esi + 41f566: 48 8b 00 mov (%rax),%rax + 41f569: 48 85 c0 test %rax,%rax + 41f56c: 48 0f 45 d0 cmovne %rax,%rdx + 41f570: 83 e7 02 and $0x2,%edi + 41f573: 31 c0 xor %eax,%eax + 41f575: e8 46 20 ff ff callq 4115c0 <__libc_message> + 41f57a: 31 ed xor %ebp,%ebp + 41f57c: e9 69 fd ff ff jmpq 41f2ea + 41f581: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 41f588: 4c 89 ef mov %r13,%rdi + 41f58b: e8 80 e4 ff ff callq 41da10 <__libc_malloc> + 41f590: 48 89 c5 mov %rax,%rbp + 41f593: e9 52 fd ff ff jmpq 41f2ea + 41f598: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 41f59f: 00 + 41f5a0: 90 nop + 41f5a1: 4c 89 ef mov %r13,%rdi + 41f5a4: 31 ed xor %ebp,%ebp + 41f5a6: e8 65 e4 ff ff callq 41da10 <__libc_malloc> + 41f5ab: 48 85 c0 test %rax,%rax + 41f5ae: 49 89 c5 mov %rax,%r13 + 41f5b1: 0f 84 33 fd ff ff je 41f2ea + 41f5b7: 49 8d 57 f8 lea -0x8(%r15),%rdx + 41f5bb: 48 89 de mov %rbx,%rsi + 41f5be: 48 89 c7 mov %rax,%rdi + 41f5c1: 4c 89 ed mov %r13,%rbp + 41f5c4: e8 57 ca 00 00 callq 42c020 + 41f5c9: 31 d2 xor %edx,%edx + 41f5cb: 4c 89 f6 mov %r14,%rsi + 41f5ce: 4c 89 e7 mov %r12,%rdi + 41f5d1: e8 ea a1 ff ff callq 4197c0 <_int_free> + 41f5d6: e9 0f fd ff ff jmpq 41f2ea + 41f5db: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41f5e0: 8b 2d 8a b1 2a 00 mov 0x2ab18a(%rip),%ebp # 6ca770 + 41f5e6: e9 4f fd ff ff jmpq 41f33a + 41f5eb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41f5f0: 89 ef mov %ebp,%edi + 41f5f2: ba c6 21 4a 00 mov $0x4a21c6,%edx + 41f5f7: be 3c ca 4b 00 mov $0x4bca3c,%esi + 41f5fc: 83 e7 02 and $0x2,%edi + 41f5ff: 31 c0 xor %eax,%eax + 41f601: 31 ed xor %ebp,%ebp + 41f603: e8 b8 1f ff ff callq 4115c0 <__libc_message> + 41f608: e9 dd fc ff ff jmpq 41f2ea + 41f60d: e8 ee e5 fe ff callq 40dc00 + 41f612: 0f 1f 40 00 nopl 0x0(%rax) + 41f616: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41f61d: 00 00 00 + +000000000041f620 : + 41f620: 41 54 push %r12 + 41f622: 55 push %rbp + 41f623: 49 89 f4 mov %rsi,%r12 + 41f626: 53 push %rbx + 41f627: 48 83 ec 10 sub $0x10,%rsp + 41f62b: 8b 05 33 b1 2a 00 mov 0x2ab133(%rip),%eax # 6ca764 <__libc_malloc_initialized> + 41f631: 48 c7 05 3c b1 2a 00 movq $0x0,0x2ab13c(%rip) # 6ca778 <__memalign_hook> + 41f638: 00 00 00 00 + 41f63c: 85 c0 test %eax,%eax + 41f63e: 0f 88 f4 01 00 00 js 41f838 + 41f644: 48 8b 05 2d b1 2a 00 mov 0x2ab12d(%rip),%rax # 6ca778 <__memalign_hook> + 41f64b: 48 8b 54 24 28 mov 0x28(%rsp),%rdx + 41f650: 48 85 c0 test %rax,%rax + 41f653: 0f 85 07 02 00 00 jne 41f860 + 41f659: 48 83 ff 10 cmp $0x10,%rdi + 41f65d: 0f 86 ed 01 00 00 jbe 41f850 + 41f663: 48 83 ff 1f cmp $0x1f,%rdi + 41f667: 0f 87 e3 00 00 00 ja 41f750 + 41f66d: 49 83 fc bf cmp $0xffffffffffffffbf,%r12 + 41f671: 0f 87 11 02 00 00 ja 41f888 + 41f677: bb 20 00 00 00 mov $0x20,%ebx + 41f67c: 48 c7 c0 d8 ff ff ff mov $0xffffffffffffffd8,%rax + 41f683: 64 48 8b 28 mov %fs:(%rax),%rbp + 41f687: 48 85 ed test %rbp,%rbp + 41f68a: 0f 84 18 01 00 00 je 41f7a8 + 41f690: 8b 45 04 mov 0x4(%rbp),%eax + 41f693: 83 e0 04 and $0x4,%eax + 41f696: 0f 85 0c 01 00 00 jne 41f7a8 + 41f69c: be 01 00 00 00 mov $0x1,%esi + 41f6a1: 83 3d 14 db 2a 00 00 cmpl $0x0,0x2adb14(%rip) # 6cd1bc <__libc_multiple_threads> + 41f6a8: 74 09 je 41f6b3 + 41f6aa: f0 0f b1 75 00 lock cmpxchg %esi,0x0(%rbp) + 41f6af: 75 08 jne 41f6b9 + 41f6b1: eb 1d jmp 41f6d0 + 41f6b3: 0f b1 75 00 cmpxchg %esi,0x0(%rbp) + 41f6b7: 74 17 je 41f6d0 + 41f6b9: 48 8d 7d 00 lea 0x0(%rbp),%rdi + 41f6bd: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41f6c4: e8 07 2f 02 00 callq 4425d0 <__lll_lock_wait_private> + 41f6c9: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41f6d0: 4c 89 e2 mov %r12,%rdx + 41f6d3: 48 89 de mov %rbx,%rsi + 41f6d6: 48 89 ef mov %rbp,%rdi + 41f6d9: e8 32 ce ff ff callq 41c510 <_int_memalign> + 41f6de: 48 85 c0 test %rax,%rax + 41f6e1: 48 89 c2 mov %rax,%rdx + 41f6e4: 0f 84 fe 00 00 00 je 41f7e8 + 41f6ea: 83 3d cb da 2a 00 00 cmpl $0x0,0x2adacb(%rip) # 6cd1bc <__libc_multiple_threads> + 41f6f1: 74 08 je 41f6fb + 41f6f3: f0 ff 4d 00 lock decl 0x0(%rbp) + 41f6f7: 75 07 jne 41f700 + 41f6f9: eb 1c jmp 41f717 + 41f6fb: ff 4d 00 decl 0x0(%rbp) + 41f6fe: 74 17 je 41f717 + 41f700: 48 8d 7d 00 lea 0x0(%rbp),%rdi + 41f704: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41f70b: e8 f0 2e 02 00 callq 442600 <__lll_unlock_wake_private> + 41f710: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41f717: 48 85 d2 test %rdx,%rdx + 41f71a: 0f 84 80 01 00 00 je 41f8a0 + 41f720: 48 8b 42 f8 mov -0x8(%rdx),%rax + 41f724: a8 02 test $0x2,%al + 41f726: 75 16 jne 41f73e + 41f728: a8 04 test $0x4,%al + 41f72a: b9 00 a8 6c 00 mov $0x6ca800,%ecx + 41f72f: 0f 85 eb 00 00 00 jne 41f820 + 41f735: 48 39 e9 cmp %rbp,%rcx + 41f738: 0f 85 69 01 00 00 jne 41f8a7 + 41f73e: 48 89 d0 mov %rdx,%rax + 41f741: 48 83 c4 10 add $0x10,%rsp + 41f745: 5b pop %rbx + 41f746: 5d pop %rbp + 41f747: 41 5c pop %r12 + 41f749: c3 retq + 41f74a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 41f750: 48 b8 00 00 00 00 00 movabs $0x8000000000000000,%rax + 41f757: 00 00 80 + 41f75a: 48 39 c7 cmp %rax,%rdi + 41f75d: 0f 87 0d 01 00 00 ja 41f870 + 41f763: 48 c7 c0 df ff ff ff mov $0xffffffffffffffdf,%rax + 41f76a: 48 29 f8 sub %rdi,%rax + 41f76d: 49 39 c4 cmp %rax,%r12 + 41f770: 0f 87 12 01 00 00 ja 41f888 + 41f776: 48 8d 47 ff lea -0x1(%rdi),%rax + 41f77a: 48 85 f8 test %rdi,%rax + 41f77d: 0f 84 3d 01 00 00 je 41f8c0 + 41f783: 48 83 ff 20 cmp $0x20,%rdi + 41f787: bb 20 00 00 00 mov $0x20,%ebx + 41f78c: 0f 84 ea fe ff ff je 41f67c + 41f792: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 41f798: 48 01 db add %rbx,%rbx + 41f79b: 48 39 df cmp %rbx,%rdi + 41f79e: 77 f8 ja 41f798 + 41f7a0: e9 d7 fe ff ff jmpq 41f67c + 41f7a5: 0f 1f 00 nopl (%rax) + 41f7a8: e8 b3 79 ff ff callq 417160 + 41f7ad: 48 85 c0 test %rax,%rax + 41f7b0: 48 89 c5 mov %rax,%rbp + 41f7b3: 0f 85 17 ff ff ff jne 41f6d0 + 41f7b9: 4a 8d 7c 23 20 lea 0x20(%rbx,%r12,1),%rdi + 41f7be: 31 f6 xor %esi,%esi + 41f7c0: e8 8b 7c ff ff callq 417450 + 41f7c5: 4c 89 e2 mov %r12,%rdx + 41f7c8: 48 89 de mov %rbx,%rsi + 41f7cb: 48 89 c7 mov %rax,%rdi + 41f7ce: 48 89 c5 mov %rax,%rbp + 41f7d1: e8 3a cd ff ff callq 41c510 <_int_memalign> + 41f7d6: 48 85 c0 test %rax,%rax + 41f7d9: 48 89 c2 mov %rax,%rdx + 41f7dc: 75 2a jne 41f808 + 41f7de: 48 85 ed test %rbp,%rbp + 41f7e1: 74 25 je 41f808 + 41f7e3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41f7e8: 90 nop + 41f7e9: 48 89 ef mov %rbp,%rdi + 41f7ec: 4c 89 e6 mov %r12,%rsi + 41f7ef: e8 fc 81 ff ff callq 4179f0 + 41f7f4: 4c 89 e2 mov %r12,%rdx + 41f7f7: 48 89 de mov %rbx,%rsi + 41f7fa: 48 89 c7 mov %rax,%rdi + 41f7fd: 48 89 c5 mov %rax,%rbp + 41f800: e8 0b cd ff ff callq 41c510 <_int_memalign> + 41f805: 48 89 c2 mov %rax,%rdx + 41f808: 48 85 ed test %rbp,%rbp + 41f80b: 0f 85 d9 fe ff ff jne 41f6ea + 41f811: e9 01 ff ff ff jmpq 41f717 + 41f816: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41f81d: 00 00 00 + 41f820: 48 8d 42 f0 lea -0x10(%rdx),%rax + 41f824: 48 25 00 00 00 fc and $0xfffffffffc000000,%rax + 41f82a: 48 8b 08 mov (%rax),%rcx + 41f82d: e9 03 ff ff ff jmpq 41f735 + 41f832: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 41f838: 48 89 7c 24 08 mov %rdi,0x8(%rsp) + 41f83d: e8 ae f4 ff ff callq 41ecf0 + 41f842: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi + 41f847: e9 f8 fd ff ff jmpq 41f644 + 41f84c: 0f 1f 40 00 nopl 0x0(%rax) + 41f850: 48 83 c4 10 add $0x10,%rsp + 41f854: 4c 89 e7 mov %r12,%rdi + 41f857: 5b pop %rbx + 41f858: 5d pop %rbp + 41f859: 41 5c pop %r12 + 41f85b: e9 b0 e1 ff ff jmpq 41da10 <__libc_malloc> + 41f860: 48 83 c4 10 add $0x10,%rsp + 41f864: 4c 89 e6 mov %r12,%rsi + 41f867: 5b pop %rbx + 41f868: 5d pop %rbp + 41f869: 41 5c pop %r12 + 41f86b: ff e0 jmpq *%rax + 41f86d: 0f 1f 00 nopl (%rax) + 41f870: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 41f877: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) + 41f87e: 31 c0 xor %eax,%eax + 41f880: e9 bc fe ff ff jmpq 41f741 + 41f885: 0f 1f 00 nopl (%rax) + 41f888: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 41f88f: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) + 41f896: 31 c0 xor %eax,%eax + 41f898: e9 a4 fe ff ff jmpq 41f741 + 41f89d: 0f 1f 00 nopl (%rax) + 41f8a0: 31 c0 xor %eax,%eax + 41f8a2: e9 9a fe ff ff jmpq 41f741 + 41f8a7: b9 08 2e 4a 00 mov $0x4a2e08,%ecx + 41f8ac: ba 3c 0c 00 00 mov $0xc3c,%edx + 41f8b1: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 41f8b6: bf 20 2a 4a 00 mov $0x4a2a20,%edi + 41f8bb: e8 60 75 ff ff callq 416e20 <__malloc_assert> + 41f8c0: 48 89 fb mov %rdi,%rbx + 41f8c3: e9 b4 fd ff ff jmpq 41f67c + 41f8c8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 41f8cf: 00 + +000000000041f8d0 <__malloc_set_state>: + 41f8d0: 44 8b 05 8d ae 2a 00 mov 0x2aae8d(%rip),%r8d # 6ca764 <__libc_malloc_initialized> + 41f8d7: 53 push %rbx + 41f8d8: 48 89 fb mov %rdi,%rbx + 41f8db: c7 05 23 cd 2a 00 01 movl $0x1,0x2acd23(%rip) # 6cc608 + 41f8e2: 00 00 00 + 41f8e5: 45 85 c0 test %r8d,%r8d + 41f8e8: 0f 88 df 04 00 00 js 41fdcd <__malloc_set_state+0x4fd> + 41f8ee: 48 81 3b 41 45 4c 44 cmpq $0x444c4541,(%rbx) + 41f8f5: 0f 85 e4 04 00 00 jne 41fddf <__malloc_set_state+0x50f> + 41f8fb: 48 f7 43 08 00 ff ff testq $0xffffffffffffff00,0x8(%rbx) + 41f902: ff + 41f903: 0f 8f dd 04 00 00 jg 41fde6 <__malloc_set_state+0x516> + 41f909: be 01 00 00 00 mov $0x1,%esi + 41f90e: 31 c0 xor %eax,%eax + 41f910: 83 3d a5 d8 2a 00 00 cmpl $0x0,0x2ad8a5(%rip) # 6cd1bc <__libc_multiple_threads> + 41f917: 74 0c je 41f925 <__malloc_set_state+0x55> + 41f919: f0 0f b1 35 df ae 2a lock cmpxchg %esi,0x2aaedf(%rip) # 6ca800 + 41f920: 00 + 41f921: 75 0b jne 41f92e <__malloc_set_state+0x5e> + 41f923: eb 23 jmp 41f948 <__malloc_set_state+0x78> + 41f925: 0f b1 35 d4 ae 2a 00 cmpxchg %esi,0x2aaed4(%rip) # 6ca800 + 41f92c: 74 1a je 41f948 <__malloc_set_state+0x78> + 41f92e: 48 8d 3d cb ae 2a 00 lea 0x2aaecb(%rip),%rdi # 6ca800 + 41f935: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41f93c: e8 8f 2c 02 00 callq 4425d0 <__lll_lock_wait_private> + 41f941: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41f948: 64 83 3c 25 18 00 00 cmpl $0x0,%fs:0x18 + 41f94f: 00 00 + 41f951: 74 01 je 41f954 <__malloc_set_state+0x84> + 41f953: f0 83 0d a9 ae 2a 00 lock orl $0x1,0x2aaea9(%rip) # 6ca804 + 41f95a: 01 + 41f95b: 48 83 7b 08 03 cmpq $0x3,0x8(%rbx) + 41f960: 0f 8f 0d 01 00 00 jg 41fa73 <__malloc_set_state+0x1a3> + 41f966: 48 c7 05 c7 cc 2a 00 movq $0x40,0x2accc7(%rip) # 6cc638 + 41f96d: 40 00 00 00 + 41f971: ba 08 a8 6c 00 mov $0x6ca808,%edx + 41f976: 31 c0 xor %eax,%eax + 41f978: b9 0a 00 00 00 mov $0xa,%ecx + 41f97d: 48 89 d7 mov %rdx,%rdi + 41f980: c7 05 ce b6 2a 00 00 movl $0x0,0x2ab6ce(%rip) # 6cb058 + 41f987: 00 00 00 + 41f98a: c7 05 c8 b6 2a 00 00 movl $0x0,0x2ab6c8(%rip) # 6cb05c + 41f991: 00 00 00 + 41f994: f3 48 ab rep stos %rax,%es:(%rdi) + 41f997: c7 05 bf b6 2a 00 00 movl $0x0,0x2ab6bf(%rip) # 6cb060 + 41f99e: 00 00 00 + 41f9a1: c7 05 b9 b6 2a 00 00 movl $0x0,0x2ab6b9(%rip) # 6cb064 + 41f9a8: 00 00 00 + 41f9ab: 48 8d 53 38 lea 0x38(%rbx),%rdx + 41f9af: b9 01 00 00 00 mov $0x1,%ecx + 41f9b4: 41 b8 01 00 00 00 mov $0x1,%r8d + 41f9ba: 41 b9 7e 00 00 00 mov $0x7e,%r9d + 41f9c0: 48 8b 43 20 mov 0x20(%rbx),%rax + 41f9c4: 48 c7 05 91 ae 2a 00 movq $0x0,0x2aae91(%rip) # 6ca860 + 41f9cb: 00 00 00 00 + 41f9cf: 48 89 05 82 ae 2a 00 mov %rax,0x2aae82(%rip) # 6ca858 + 41f9d6: b8 58 a8 6c 00 mov $0x6ca858,%eax + 41f9db: eb 50 jmp 41fa2d <__malloc_set_state+0x15d> + 41f9dd: 0f 1f 00 nopl (%rax) + 41f9e0: 48 83 f9 3f cmp $0x3f,%rcx + 41f9e4: 0f 87 b6 00 00 00 ja 41faa0 <__malloc_set_state+0x1d0> + 41f9ea: 48 8b 3a mov (%rdx),%rdi + 41f9ed: 48 89 78 18 mov %rdi,0x18(%rax) + 41f9f1: 48 89 70 10 mov %rsi,0x10(%rax) + 41f9f5: 44 89 c7 mov %r8d,%edi + 41f9f8: 48 89 46 18 mov %rax,0x18(%rsi) + 41f9fc: 48 8b 70 18 mov 0x18(%rax),%rsi + 41fa00: d3 e7 shl %cl,%edi + 41fa02: 48 89 46 10 mov %rax,0x10(%rsi) + 41fa06: 48 89 ce mov %rcx,%rsi + 41fa09: 48 c1 ee 05 shr $0x5,%rsi + 41fa0d: 09 3c b5 58 b0 6c 00 or %edi,0x6cb058(,%rsi,4) + 41fa14: 48 83 c1 01 add $0x1,%rcx + 41fa18: 48 83 c0 10 add $0x10,%rax + 41fa1c: 48 83 c2 10 add $0x10,%rdx + 41fa20: 48 81 f9 80 00 00 00 cmp $0x80,%rcx + 41fa27: 0f 84 6b 01 00 00 je 41fb98 <__malloc_set_state+0x2c8> + 41fa2d: 48 8b 72 f8 mov -0x8(%rdx),%rsi + 41fa31: 48 85 f6 test %rsi,%rsi + 41fa34: 0f 84 a6 00 00 00 je 41fae0 <__malloc_set_state+0x210> + 41fa3a: 48 83 7b 08 02 cmpq $0x2,0x8(%rbx) + 41fa3f: 7f 9f jg 41f9e0 <__malloc_set_state+0x110> + 41fa41: 48 8b 3a mov (%rdx),%rdi + 41fa44: 48 89 40 18 mov %rax,0x18(%rax) + 41fa48: 48 89 40 10 mov %rax,0x10(%rax) + 41fa4c: 48 c7 46 18 58 a8 6c movq $0x6ca858,0x18(%rsi) + 41fa53: 00 + 41fa54: 4c 8b 15 0d ae 2a 00 mov 0x2aae0d(%rip),%r10 # 6ca868 + 41fa5b: 4c 89 57 10 mov %r10,0x10(%rdi) + 41fa5f: 4c 8b 15 02 ae 2a 00 mov 0x2aae02(%rip),%r10 # 6ca868 + 41fa66: 49 89 7a 18 mov %rdi,0x18(%r10) + 41fa6a: 48 89 35 f7 ad 2a 00 mov %rsi,0x2aadf7(%rip) # 6ca868 + 41fa71: eb a1 jmp 41fa14 <__malloc_set_state+0x144> + 41fa73: 48 8b 93 88 08 00 00 mov 0x888(%rbx),%rdx + 41fa7a: b8 10 00 00 00 mov $0x10,%eax + 41fa7f: 48 85 d2 test %rdx,%rdx + 41fa82: 74 08 je 41fa8c <__malloc_set_state+0x1bc> + 41fa84: 48 8d 42 08 lea 0x8(%rdx),%rax + 41fa88: 48 83 e0 f0 and $0xfffffffffffffff0,%rax + 41fa8c: 48 89 05 a5 cb 2a 00 mov %rax,0x2acba5(%rip) # 6cc638 + 41fa93: e9 d9 fe ff ff jmpq 41f971 <__malloc_set_state+0xa1> + 41fa98: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 41fa9f: 00 + 41faa0: 4c 8b 56 08 mov 0x8(%rsi),%r10 + 41faa4: 4c 89 d7 mov %r10,%rdi + 41faa7: 48 c1 ef 06 shr $0x6,%rdi + 41faab: 48 83 ff 30 cmp $0x30,%rdi + 41faaf: 77 4f ja 41fb00 <__malloc_set_state+0x230> + 41fab1: 48 83 c7 30 add $0x30,%rdi + 41fab5: 48 39 cf cmp %rcx,%rdi + 41fab8: 48 8b 3a mov (%rdx),%rdi + 41fabb: 75 87 jne 41fa44 <__malloc_set_state+0x174> + 41fabd: 4c 8b 5f 08 mov 0x8(%rdi),%r11 + 41fac1: 4d 89 da mov %r11,%r10 + 41fac4: 49 c1 ea 06 shr $0x6,%r10 + 41fac8: 49 83 fa 30 cmp $0x30,%r10 + 41facc: 77 62 ja 41fb30 <__malloc_set_state+0x260> + 41face: 49 83 c2 30 add $0x30,%r10 + 41fad2: 49 39 ca cmp %rcx,%r10 + 41fad5: 0f 85 69 ff ff ff jne 41fa44 <__malloc_set_state+0x174> + 41fadb: e9 0d ff ff ff jmpq 41f9ed <__malloc_set_state+0x11d> + 41fae0: 48 83 3a 00 cmpq $0x0,(%rdx) + 41fae4: 0f 85 03 03 00 00 jne 41fded <__malloc_set_state+0x51d> + 41faea: 48 89 40 18 mov %rax,0x18(%rax) + 41faee: 48 89 40 10 mov %rax,0x10(%rax) + 41faf2: e9 1d ff ff ff jmpq 41fa14 <__malloc_set_state+0x144> + 41faf7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 41fafe: 00 00 + 41fb00: 4c 89 d7 mov %r10,%rdi + 41fb03: 48 c1 ef 09 shr $0x9,%rdi + 41fb07: 48 83 ff 14 cmp $0x14,%rdi + 41fb0b: 77 0b ja 41fb18 <__malloc_set_state+0x248> + 41fb0d: 48 83 c7 5b add $0x5b,%rdi + 41fb11: eb a2 jmp 41fab5 <__malloc_set_state+0x1e5> + 41fb13: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41fb18: 4c 89 d7 mov %r10,%rdi + 41fb1b: 48 c1 ef 0c shr $0xc,%rdi + 41fb1f: 48 83 ff 0a cmp $0xa,%rdi + 41fb23: 77 23 ja 41fb48 <__malloc_set_state+0x278> + 41fb25: 48 83 c7 6e add $0x6e,%rdi + 41fb29: eb 8a jmp 41fab5 <__malloc_set_state+0x1e5> + 41fb2b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41fb30: 4d 89 da mov %r11,%r10 + 41fb33: 49 c1 ea 09 shr $0x9,%r10 + 41fb37: 49 83 fa 14 cmp $0x14,%r10 + 41fb3b: 77 23 ja 41fb60 <__malloc_set_state+0x290> + 41fb3d: 49 83 c2 5b add $0x5b,%r10 + 41fb41: eb 8f jmp 41fad2 <__malloc_set_state+0x202> + 41fb43: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41fb48: 4c 89 d7 mov %r10,%rdi + 41fb4b: 48 c1 ef 0f shr $0xf,%rdi + 41fb4f: 48 83 ff 04 cmp $0x4,%rdi + 41fb53: 77 2b ja 41fb80 <__malloc_set_state+0x2b0> + 41fb55: 48 83 c7 77 add $0x77,%rdi + 41fb59: e9 57 ff ff ff jmpq 41fab5 <__malloc_set_state+0x1e5> + 41fb5e: 66 90 xchg %ax,%ax + 41fb60: 4d 89 da mov %r11,%r10 + 41fb63: 49 c1 ea 0c shr $0xc,%r10 + 41fb67: 49 83 fa 0a cmp $0xa,%r10 + 41fb6b: 0f 87 9f 01 00 00 ja 41fd10 <__malloc_set_state+0x440> + 41fb71: 49 83 c2 6e add $0x6e,%r10 + 41fb75: e9 58 ff ff ff jmpq 41fad2 <__malloc_set_state+0x202> + 41fb7a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 41fb80: 49 c1 ea 12 shr $0x12,%r10 + 41fb84: 49 8d 7a 7c lea 0x7c(%r10),%rdi + 41fb88: 49 83 fa 02 cmp $0x2,%r10 + 41fb8c: 49 0f 47 f9 cmova %r9,%rdi + 41fb90: e9 20 ff ff ff jmpq 41fab5 <__malloc_set_state+0x1e5> + 41fb95: 0f 1f 00 nopl (%rax) + 41fb98: 48 8b 4b 08 mov 0x8(%rbx),%rcx + 41fb9c: 48 83 f9 02 cmp $0x2,%rcx + 41fba0: 7f 43 jg 41fbe5 <__malloc_set_state+0x315> + 41fba2: 48 8b 05 bf ac 2a 00 mov 0x2aacbf(%rip),%rax # 6ca868 + 41fba9: 48 3d 58 a8 6c 00 cmp $0x6ca858,%rax + 41fbaf: 74 34 je 41fbe5 <__malloc_set_state+0x315> + 41fbb1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 41fbb8: 48 8b 50 08 mov 0x8(%rax),%rdx + 41fbbc: 48 83 e2 f8 and $0xfffffffffffffff8,%rdx + 41fbc0: 48 81 fa ff 03 00 00 cmp $0x3ff,%rdx + 41fbc7: 76 10 jbe 41fbd9 <__malloc_set_state+0x309> + 41fbc9: 48 c7 40 20 00 00 00 movq $0x0,0x20(%rax) + 41fbd0: 00 + 41fbd1: 48 c7 40 28 00 00 00 movq $0x0,0x28(%rax) + 41fbd8: 00 + 41fbd9: 48 8b 40 10 mov 0x10(%rax),%rax + 41fbdd: 48 3d 58 a8 6c 00 cmp $0x6ca858,%rax + 41fbe3: 75 d3 jne 41fbb8 <__malloc_set_state+0x2e8> + 41fbe5: 48 8b 83 20 08 00 00 mov 0x820(%rbx),%rax + 41fbec: 48 85 c9 test %rcx,%rcx + 41fbef: 48 89 05 fa ab 2a 00 mov %rax,0x2aabfa(%rip) # 6ca7f0 + 41fbf6: 48 63 83 28 08 00 00 movslq 0x828(%rbx),%rax + 41fbfd: 48 89 05 7c b4 2a 00 mov %rax,0x2ab47c(%rip) # 6cb080 + 41fc04: 48 8b 83 30 08 00 00 mov 0x830(%rbx),%rax + 41fc0b: 48 89 05 8e ab 2a 00 mov %rax,0x2aab8e(%rip) # 6ca7a0 + 41fc12: 48 8b 83 38 08 00 00 mov 0x838(%rbx),%rax + 41fc19: 48 89 05 88 ab 2a 00 mov %rax,0x2aab88(%rip) # 6ca7a8 + 41fc20: 8b 83 40 08 00 00 mov 0x840(%rbx),%eax + 41fc26: 89 05 a0 ab 2a 00 mov %eax,0x2aaba0(%rip) # 6ca7cc + 41fc2c: 48 8b 83 48 08 00 00 mov 0x848(%rbx),%rax + 41fc33: 48 89 05 76 ab 2a 00 mov %rax,0x2aab76(%rip) # 6ca7b0 + 41fc3a: 8b 83 50 08 00 00 mov 0x850(%rbx),%eax + 41fc40: 89 05 2a ab 2a 00 mov %eax,0x2aab2a(%rip) # 6ca770 + 41fc46: 48 8b 83 58 08 00 00 mov 0x858(%rbx),%rax + 41fc4d: 48 89 05 34 b4 2a 00 mov %rax,0x2ab434(%rip) # 6cb088 + 41fc54: 8b 83 68 08 00 00 mov 0x868(%rbx),%eax + 41fc5a: 89 05 68 ab 2a 00 mov %eax,0x2aab68(%rip) # 6ca7c8 + 41fc60: 8b 83 6c 08 00 00 mov 0x86c(%rbx),%eax + 41fc66: 89 05 64 ab 2a 00 mov %eax,0x2aab64(%rip) # 6ca7d0 + 41fc6c: 48 8b 83 70 08 00 00 mov 0x870(%rbx),%rax + 41fc73: 48 89 05 5e ab 2a 00 mov %rax,0x2aab5e(%rip) # 6ca7d8 + 41fc7a: 48 8b 83 78 08 00 00 mov 0x878(%rbx),%rax + 41fc81: 48 89 05 58 ab 2a 00 mov %rax,0x2aab58(%rip) # 6ca7e0 + 41fc88: 7e 4c jle 41fcd6 <__malloc_set_state+0x406> + 41fc8a: 8b bb 80 08 00 00 mov 0x880(%rbx),%edi + 41fc90: 85 ff test %edi,%edi + 41fc92: 0f 85 a3 00 00 00 jne 41fd3b <__malloc_set_state+0x46b> + 41fc98: 8b 05 6e c9 2a 00 mov 0x2ac96e(%rip),%eax # 6cc60c + 41fc9e: 85 c0 test %eax,%eax + 41fca0: 0f 85 ec 00 00 00 jne 41fd92 <__malloc_set_state+0x4c2> + 41fca6: 48 83 f9 03 cmp $0x3,%rcx + 41fcaa: 7e 2a jle 41fcd6 <__malloc_set_state+0x406> + 41fcac: 48 8b 83 90 08 00 00 mov 0x890(%rbx),%rax + 41fcb3: 48 89 05 fe aa 2a 00 mov %rax,0x2aaafe(%rip) # 6ca7b8 + 41fcba: 48 8b 83 98 08 00 00 mov 0x898(%rbx),%rax + 41fcc1: 48 89 05 f8 aa 2a 00 mov %rax,0x2aaaf8(%rip) # 6ca7c0 + 41fcc8: 48 8b 83 a0 08 00 00 mov 0x8a0(%rbx),%rax + 41fccf: 48 89 05 92 aa 2a 00 mov %rax,0x2aaa92(%rip) # 6ca768 + 41fcd6: 83 3d df d4 2a 00 00 cmpl $0x0,0x2ad4df(%rip) # 6cd1bc <__libc_multiple_threads> + 41fcdd: 74 0b je 41fcea <__malloc_set_state+0x41a> + 41fcdf: f0 ff 0d 1a ab 2a 00 lock decl 0x2aab1a(%rip) # 6ca800 + 41fce6: 75 0a jne 41fcf2 <__malloc_set_state+0x422> + 41fce8: eb 22 jmp 41fd0c <__malloc_set_state+0x43c> + 41fcea: ff 0d 10 ab 2a 00 decl 0x2aab10(%rip) # 6ca800 + 41fcf0: 74 1a je 41fd0c <__malloc_set_state+0x43c> + 41fcf2: 48 8d 3d 07 ab 2a 00 lea 0x2aab07(%rip),%rdi # 6ca800 + 41fcf9: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41fd00: e8 fb 28 02 00 callq 442600 <__lll_unlock_wake_private> + 41fd05: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41fd0c: 31 c0 xor %eax,%eax + 41fd0e: 5b pop %rbx + 41fd0f: c3 retq + 41fd10: 4d 89 da mov %r11,%r10 + 41fd13: 49 c1 ea 0f shr $0xf,%r10 + 41fd17: 49 83 fa 04 cmp $0x4,%r10 + 41fd1b: 77 09 ja 41fd26 <__malloc_set_state+0x456> + 41fd1d: 49 83 c2 77 add $0x77,%r10 + 41fd21: e9 ac fd ff ff jmpq 41fad2 <__malloc_set_state+0x202> + 41fd26: 49 c1 eb 12 shr $0x12,%r11 + 41fd2a: 4d 8d 53 7c lea 0x7c(%r11),%r10 + 41fd2e: 49 83 fb 02 cmp $0x2,%r11 + 41fd32: 4d 0f 47 d1 cmova %r9,%r10 + 41fd36: e9 97 fd ff ff jmpq 41fad2 <__malloc_set_state+0x202> + 41fd3b: 8b 35 cb c8 2a 00 mov 0x2ac8cb(%rip),%esi # 6cc60c + 41fd41: 85 f6 test %esi,%esi + 41fd43: 0f 85 5d ff ff ff jne 41fca6 <__malloc_set_state+0x3d6> + 41fd49: 8b 15 b9 c8 2a 00 mov 0x2ac8b9(%rip),%edx # 6cc608 + 41fd4f: 85 d2 test %edx,%edx + 41fd51: 0f 85 4f ff ff ff jne 41fca6 <__malloc_set_state+0x3d6> + 41fd57: c7 05 ab c8 2a 00 01 movl $0x1,0x2ac8ab(%rip) # 6cc60c + 41fd5e: 00 00 00 + 41fd61: 48 c7 05 1c aa 2a 00 movq $0x41c720,0x2aaa1c(%rip) # 6ca788 <__malloc_hook> + 41fd68: 20 c7 41 00 + 41fd6c: 48 c7 05 71 c8 2a 00 movq $0x4189e0,0x2ac871(%rip) # 6cc5e8 <__free_hook> + 41fd73: e0 89 41 00 + 41fd77: 48 c7 05 fe a9 2a 00 movq $0x41d180,0x2aa9fe(%rip) # 6ca780 <__realloc_hook> + 41fd7e: 80 d1 41 00 + 41fd82: 48 c7 05 eb a9 2a 00 movq $0x41c870,0x2aa9eb(%rip) # 6ca778 <__memalign_hook> + 41fd89: 70 c8 41 00 + 41fd8d: e9 14 ff ff ff jmpq 41fca6 <__malloc_set_state+0x3d6> + 41fd92: 48 c7 05 eb a9 2a 00 movq $0x0,0x2aa9eb(%rip) # 6ca788 <__malloc_hook> + 41fd99: 00 00 00 00 + 41fd9d: 48 c7 05 40 c8 2a 00 movq $0x0,0x2ac840(%rip) # 6cc5e8 <__free_hook> + 41fda4: 00 00 00 00 + 41fda8: 48 c7 05 cd a9 2a 00 movq $0x0,0x2aa9cd(%rip) # 6ca780 <__realloc_hook> + 41fdaf: 00 00 00 00 + 41fdb3: 48 c7 05 ba a9 2a 00 movq $0x0,0x2aa9ba(%rip) # 6ca778 <__memalign_hook> + 41fdba: 00 00 00 00 + 41fdbe: c7 05 44 c8 2a 00 00 movl $0x0,0x2ac844(%rip) # 6cc60c + 41fdc5: 00 00 00 + 41fdc8: e9 d9 fe ff ff jmpq 41fca6 <__malloc_set_state+0x3d6> + 41fdcd: e8 1e ef ff ff callq 41ecf0 + 41fdd2: 48 81 3b 41 45 4c 44 cmpq $0x444c4541,(%rbx) + 41fdd9: 0f 84 1c fb ff ff je 41f8fb <__malloc_set_state+0x2b> + 41fddf: b8 ff ff ff ff mov $0xffffffff,%eax + 41fde4: 5b pop %rbx + 41fde5: c3 retq + 41fde6: b8 fe ff ff ff mov $0xfffffffe,%eax + 41fdeb: 5b pop %rbx + 41fdec: c3 retq + 41fded: b9 a0 2f 4a 00 mov $0x4a2fa0,%ecx + 41fdf2: ba 45 02 00 00 mov $0x245,%edx + 41fdf7: be 3f 22 4a 00 mov $0x4a223f,%esi + 41fdfc: bf 47 22 4a 00 mov $0x4a2247,%edi + 41fe01: e8 1a 70 ff ff callq 416e20 <__malloc_assert> + 41fe06: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41fe0d: 00 00 00 + +000000000041fe10 <__libc_valloc>: + 41fe10: 8b 05 4e a9 2a 00 mov 0x2aa94e(%rip),%eax # 6ca764 <__libc_malloc_initialized> + 41fe16: 41 54 push %r12 + 41fe18: 49 89 fc mov %rdi,%r12 + 41fe1b: 55 push %rbp + 41fe1c: 53 push %rbx + 41fe1d: 85 c0 test %eax,%eax + 41fe1f: 0f 88 2b 02 00 00 js 420050 <__libc_valloc+0x240> + 41fe25: 48 8b 05 4c a9 2a 00 mov 0x2aa94c(%rip),%rax # 6ca778 <__memalign_hook> + 41fe2c: 48 8b 54 24 18 mov 0x18(%rsp),%rdx + 41fe31: 48 85 c0 test %rax,%rax + 41fe34: 48 8b 3d 45 b3 2a 00 mov 0x2ab345(%rip),%rdi # 6cb180 <_dl_pagesize> + 41fe3b: 0f 85 e7 01 00 00 jne 420028 <__libc_valloc+0x218> + 41fe41: 48 83 ff 10 cmp $0x10,%rdi + 41fe45: 0f 86 cd 01 00 00 jbe 420018 <__libc_valloc+0x208> + 41fe4b: 48 83 ff 1f cmp $0x1f,%rdi + 41fe4f: 0f 87 db 00 00 00 ja 41ff30 <__libc_valloc+0x120> + 41fe55: 49 83 fc bf cmp $0xffffffffffffffbf,%r12 + 41fe59: 0f 87 01 02 00 00 ja 420060 <__libc_valloc+0x250> + 41fe5f: bb 20 00 00 00 mov $0x20,%ebx + 41fe64: 48 c7 c0 d8 ff ff ff mov $0xffffffffffffffd8,%rax + 41fe6b: 64 48 8b 28 mov %fs:(%rax),%rbp + 41fe6f: 48 85 ed test %rbp,%rbp + 41fe72: 0f 84 10 01 00 00 je 41ff88 <__libc_valloc+0x178> + 41fe78: 8b 45 04 mov 0x4(%rbp),%eax + 41fe7b: 83 e0 04 and $0x4,%eax + 41fe7e: 0f 85 04 01 00 00 jne 41ff88 <__libc_valloc+0x178> + 41fe84: be 01 00 00 00 mov $0x1,%esi + 41fe89: 83 3d 2c d3 2a 00 00 cmpl $0x0,0x2ad32c(%rip) # 6cd1bc <__libc_multiple_threads> + 41fe90: 74 09 je 41fe9b <__libc_valloc+0x8b> + 41fe92: f0 0f b1 75 00 lock cmpxchg %esi,0x0(%rbp) + 41fe97: 75 08 jne 41fea1 <__libc_valloc+0x91> + 41fe99: eb 1d jmp 41feb8 <__libc_valloc+0xa8> + 41fe9b: 0f b1 75 00 cmpxchg %esi,0x0(%rbp) + 41fe9f: 74 17 je 41feb8 <__libc_valloc+0xa8> + 41fea1: 48 8d 7d 00 lea 0x0(%rbp),%rdi + 41fea5: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41feac: e8 1f 27 02 00 callq 4425d0 <__lll_lock_wait_private> + 41feb1: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41feb8: 4c 89 e2 mov %r12,%rdx + 41febb: 48 89 de mov %rbx,%rsi + 41febe: 48 89 ef mov %rbp,%rdi + 41fec1: e8 4a c6 ff ff callq 41c510 <_int_memalign> + 41fec6: 48 85 c0 test %rax,%rax + 41fec9: 48 89 c2 mov %rax,%rdx + 41fecc: 0f 84 f6 00 00 00 je 41ffc8 <__libc_valloc+0x1b8> + 41fed2: 83 3d e3 d2 2a 00 00 cmpl $0x0,0x2ad2e3(%rip) # 6cd1bc <__libc_multiple_threads> + 41fed9: 74 08 je 41fee3 <__libc_valloc+0xd3> + 41fedb: f0 ff 4d 00 lock decl 0x0(%rbp) + 41fedf: 75 07 jne 41fee8 <__libc_valloc+0xd8> + 41fee1: eb 1c jmp 41feff <__libc_valloc+0xef> + 41fee3: ff 4d 00 decl 0x0(%rbp) + 41fee6: 74 17 je 41feff <__libc_valloc+0xef> + 41fee8: 48 8d 7d 00 lea 0x0(%rbp),%rdi + 41feec: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 41fef3: e8 08 27 02 00 callq 442600 <__lll_unlock_wake_private> + 41fef8: 48 81 c4 80 00 00 00 add $0x80,%rsp + 41feff: 48 85 d2 test %rdx,%rdx + 41ff02: 0f 84 70 01 00 00 je 420078 <__libc_valloc+0x268> + 41ff08: 48 8b 42 f8 mov -0x8(%rdx),%rax + 41ff0c: a8 02 test $0x2,%al + 41ff0e: 75 16 jne 41ff26 <__libc_valloc+0x116> + 41ff10: a8 04 test $0x4,%al + 41ff12: b9 00 a8 6c 00 mov $0x6ca800,%ecx + 41ff17: 0f 85 e3 00 00 00 jne 420000 <__libc_valloc+0x1f0> + 41ff1d: 48 39 e9 cmp %rbp,%rcx + 41ff20: 0f 85 59 01 00 00 jne 42007f <__libc_valloc+0x26f> + 41ff26: 48 89 d0 mov %rdx,%rax + 41ff29: 5b pop %rbx + 41ff2a: 5d pop %rbp + 41ff2b: 41 5c pop %r12 + 41ff2d: c3 retq + 41ff2e: 66 90 xchg %ax,%ax + 41ff30: 48 b8 00 00 00 00 00 movabs $0x8000000000000000,%rax + 41ff37: 00 00 80 + 41ff3a: 48 39 c7 cmp %rax,%rdi + 41ff3d: 0f 87 f5 00 00 00 ja 420038 <__libc_valloc+0x228> + 41ff43: 48 c7 c0 df ff ff ff mov $0xffffffffffffffdf,%rax + 41ff4a: 48 29 f8 sub %rdi,%rax + 41ff4d: 49 39 c4 cmp %rax,%r12 + 41ff50: 0f 87 0a 01 00 00 ja 420060 <__libc_valloc+0x250> + 41ff56: 48 8d 47 ff lea -0x1(%rdi),%rax + 41ff5a: 48 85 f8 test %rdi,%rax + 41ff5d: 0f 84 35 01 00 00 je 420098 <__libc_valloc+0x288> + 41ff63: 48 83 ff 20 cmp $0x20,%rdi + 41ff67: bb 20 00 00 00 mov $0x20,%ebx + 41ff6c: 0f 84 f2 fe ff ff je 41fe64 <__libc_valloc+0x54> + 41ff72: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 41ff78: 48 01 db add %rbx,%rbx + 41ff7b: 48 39 df cmp %rbx,%rdi + 41ff7e: 77 f8 ja 41ff78 <__libc_valloc+0x168> + 41ff80: e9 df fe ff ff jmpq 41fe64 <__libc_valloc+0x54> + 41ff85: 0f 1f 00 nopl (%rax) + 41ff88: e8 d3 71 ff ff callq 417160 + 41ff8d: 48 85 c0 test %rax,%rax + 41ff90: 48 89 c5 mov %rax,%rbp + 41ff93: 0f 85 1f ff ff ff jne 41feb8 <__libc_valloc+0xa8> + 41ff99: 4a 8d 7c 23 20 lea 0x20(%rbx,%r12,1),%rdi + 41ff9e: 31 f6 xor %esi,%esi + 41ffa0: e8 ab 74 ff ff callq 417450 + 41ffa5: 4c 89 e2 mov %r12,%rdx + 41ffa8: 48 89 de mov %rbx,%rsi + 41ffab: 48 89 c7 mov %rax,%rdi + 41ffae: 48 89 c5 mov %rax,%rbp + 41ffb1: e8 5a c5 ff ff callq 41c510 <_int_memalign> + 41ffb6: 48 85 c0 test %rax,%rax + 41ffb9: 48 89 c2 mov %rax,%rdx + 41ffbc: 75 2a jne 41ffe8 <__libc_valloc+0x1d8> + 41ffbe: 48 85 ed test %rbp,%rbp + 41ffc1: 74 25 je 41ffe8 <__libc_valloc+0x1d8> + 41ffc3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 41ffc8: 90 nop + 41ffc9: 48 89 ef mov %rbp,%rdi + 41ffcc: 4c 89 e6 mov %r12,%rsi + 41ffcf: e8 1c 7a ff ff callq 4179f0 + 41ffd4: 4c 89 e2 mov %r12,%rdx + 41ffd7: 48 89 de mov %rbx,%rsi + 41ffda: 48 89 c7 mov %rax,%rdi + 41ffdd: 48 89 c5 mov %rax,%rbp + 41ffe0: e8 2b c5 ff ff callq 41c510 <_int_memalign> + 41ffe5: 48 89 c2 mov %rax,%rdx + 41ffe8: 48 85 ed test %rbp,%rbp + 41ffeb: 0f 85 e1 fe ff ff jne 41fed2 <__libc_valloc+0xc2> + 41fff1: e9 09 ff ff ff jmpq 41feff <__libc_valloc+0xef> + 41fff6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 41fffd: 00 00 00 + 420000: 48 8d 42 f0 lea -0x10(%rdx),%rax + 420004: 48 25 00 00 00 fc and $0xfffffffffc000000,%rax + 42000a: 48 8b 08 mov (%rax),%rcx + 42000d: e9 0b ff ff ff jmpq 41ff1d <__libc_valloc+0x10d> + 420012: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 420018: 5b pop %rbx + 420019: 4c 89 e7 mov %r12,%rdi + 42001c: 5d pop %rbp + 42001d: 41 5c pop %r12 + 42001f: e9 ec d9 ff ff jmpq 41da10 <__libc_malloc> + 420024: 0f 1f 40 00 nopl 0x0(%rax) + 420028: 5b pop %rbx + 420029: 4c 89 e6 mov %r12,%rsi + 42002c: 5d pop %rbp + 42002d: 41 5c pop %r12 + 42002f: ff e0 jmpq *%rax + 420031: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 420038: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 42003f: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) + 420046: 31 c0 xor %eax,%eax + 420048: e9 dc fe ff ff jmpq 41ff29 <__libc_valloc+0x119> + 42004d: 0f 1f 00 nopl (%rax) + 420050: e8 9b ec ff ff callq 41ecf0 + 420055: e9 cb fd ff ff jmpq 41fe25 <__libc_valloc+0x15> + 42005a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 420060: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 420067: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) + 42006e: 31 c0 xor %eax,%eax + 420070: e9 b4 fe ff ff jmpq 41ff29 <__libc_valloc+0x119> + 420075: 0f 1f 00 nopl (%rax) + 420078: 31 c0 xor %eax,%eax + 42007a: e9 aa fe ff ff jmpq 41ff29 <__libc_valloc+0x119> + 42007f: b9 08 2e 4a 00 mov $0x4a2e08,%ecx + 420084: ba 3c 0c 00 00 mov $0xc3c,%edx + 420089: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 42008e: bf 20 2a 4a 00 mov $0x4a2a20,%edi + 420093: e8 88 6d ff ff callq 416e20 <__malloc_assert> + 420098: 48 89 fb mov %rdi,%rbx + 42009b: e9 c4 fd ff ff jmpq 41fe64 <__libc_valloc+0x54> + +00000000004200a0 <__libc_pvalloc>: + 4200a0: 41 54 push %r12 + 4200a2: 55 push %rbp + 4200a3: 53 push %rbx + 4200a4: 48 83 ec 10 sub $0x10,%rsp + 4200a8: 8b 05 b6 a6 2a 00 mov 0x2aa6b6(%rip),%eax # 6ca764 <__libc_malloc_initialized> + 4200ae: 85 c0 test %eax,%eax + 4200b0: 0f 88 7a 02 00 00 js 420330 <__libc_pvalloc+0x290> + 4200b6: 48 8b 05 c3 b0 2a 00 mov 0x2ab0c3(%rip),%rax # 6cb180 <_dl_pagesize> + 4200bd: 48 c7 c6 df ff ff ff mov $0xffffffffffffffdf,%rsi + 4200c4: 48 8b 54 24 28 mov 0x28(%rsp),%rdx + 4200c9: 48 89 f3 mov %rsi,%rbx + 4200cc: 4c 8d 40 ff lea -0x1(%rax),%r8 + 4200d0: 48 89 c1 mov %rax,%rcx + 4200d3: 48 f7 d9 neg %rcx + 4200d6: 4e 8d 24 07 lea (%rdi,%r8,1),%r12 + 4200da: 49 21 cc and %rcx,%r12 + 4200dd: 48 8d 0c 00 lea (%rax,%rax,1),%rcx + 4200e1: 48 29 cb sub %rcx,%rbx + 4200e4: 48 39 df cmp %rbx,%rdi + 4200e7: 0f 87 4b 01 00 00 ja 420238 <__libc_pvalloc+0x198> + 4200ed: 48 8b 0d 84 a6 2a 00 mov 0x2aa684(%rip),%rcx # 6ca778 <__memalign_hook> + 4200f4: 48 85 c9 test %rcx,%rcx + 4200f7: 0f 85 03 02 00 00 jne 420300 <__libc_pvalloc+0x260> + 4200fd: 48 83 f8 10 cmp $0x10,%rax + 420101: 0f 86 e1 01 00 00 jbe 4202e8 <__libc_pvalloc+0x248> + 420107: 48 83 f8 1f cmp $0x1f,%rax + 42010b: 0f 87 df 00 00 00 ja 4201f0 <__libc_pvalloc+0x150> + 420111: 49 83 fc bf cmp $0xffffffffffffffbf,%r12 + 420115: 0f 87 1d 01 00 00 ja 420238 <__libc_pvalloc+0x198> + 42011b: bb 20 00 00 00 mov $0x20,%ebx + 420120: 48 c7 c0 d8 ff ff ff mov $0xffffffffffffffd8,%rax + 420127: 64 48 8b 28 mov %fs:(%rax),%rbp + 42012b: 48 85 ed test %rbp,%rbp + 42012e: 0f 84 24 01 00 00 je 420258 <__libc_pvalloc+0x1b8> + 420134: 8b 45 04 mov 0x4(%rbp),%eax + 420137: 83 e0 04 and $0x4,%eax + 42013a: 0f 85 18 01 00 00 jne 420258 <__libc_pvalloc+0x1b8> + 420140: be 01 00 00 00 mov $0x1,%esi + 420145: 83 3d 70 d0 2a 00 00 cmpl $0x0,0x2ad070(%rip) # 6cd1bc <__libc_multiple_threads> + 42014c: 74 09 je 420157 <__libc_pvalloc+0xb7> + 42014e: f0 0f b1 75 00 lock cmpxchg %esi,0x0(%rbp) + 420153: 75 08 jne 42015d <__libc_pvalloc+0xbd> + 420155: eb 1d jmp 420174 <__libc_pvalloc+0xd4> + 420157: 0f b1 75 00 cmpxchg %esi,0x0(%rbp) + 42015b: 74 17 je 420174 <__libc_pvalloc+0xd4> + 42015d: 48 8d 7d 00 lea 0x0(%rbp),%rdi + 420161: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 420168: e8 63 24 02 00 callq 4425d0 <__lll_lock_wait_private> + 42016d: 48 81 c4 80 00 00 00 add $0x80,%rsp + 420174: 4c 89 e2 mov %r12,%rdx + 420177: 48 89 de mov %rbx,%rsi + 42017a: 48 89 ef mov %rbp,%rdi + 42017d: e8 8e c3 ff ff callq 41c510 <_int_memalign> + 420182: 48 85 c0 test %rax,%rax + 420185: 48 89 c2 mov %rax,%rdx + 420188: 0f 84 0a 01 00 00 je 420298 <__libc_pvalloc+0x1f8> + 42018e: 83 3d 27 d0 2a 00 00 cmpl $0x0,0x2ad027(%rip) # 6cd1bc <__libc_multiple_threads> + 420195: 74 08 je 42019f <__libc_pvalloc+0xff> + 420197: f0 ff 4d 00 lock decl 0x0(%rbp) + 42019b: 75 07 jne 4201a4 <__libc_pvalloc+0x104> + 42019d: eb 1c jmp 4201bb <__libc_pvalloc+0x11b> + 42019f: ff 4d 00 decl 0x0(%rbp) + 4201a2: 74 17 je 4201bb <__libc_pvalloc+0x11b> + 4201a4: 48 8d 7d 00 lea 0x0(%rbp),%rdi + 4201a8: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 4201af: e8 4c 24 02 00 callq 442600 <__lll_unlock_wake_private> + 4201b4: 48 81 c4 80 00 00 00 add $0x80,%rsp + 4201bb: 48 85 d2 test %rdx,%rdx + 4201be: 0f 84 64 01 00 00 je 420328 <__libc_pvalloc+0x288> + 4201c4: 48 8b 42 f8 mov -0x8(%rdx),%rax + 4201c8: a8 02 test $0x2,%al + 4201ca: 75 16 jne 4201e2 <__libc_pvalloc+0x142> + 4201cc: a8 04 test $0x4,%al + 4201ce: b9 00 a8 6c 00 mov $0x6ca800,%ecx + 4201d3: 0f 85 f7 00 00 00 jne 4202d0 <__libc_pvalloc+0x230> + 4201d9: 48 39 cd cmp %rcx,%rbp + 4201dc: 0f 85 6a 01 00 00 jne 42034c <__libc_pvalloc+0x2ac> + 4201e2: 48 89 d0 mov %rdx,%rax + 4201e5: 48 83 c4 10 add $0x10,%rsp + 4201e9: 5b pop %rbx + 4201ea: 5d pop %rbp + 4201eb: 41 5c pop %r12 + 4201ed: c3 retq + 4201ee: 66 90 xchg %ax,%ax + 4201f0: 48 ba 00 00 00 00 00 movabs $0x8000000000000000,%rdx + 4201f7: 00 00 80 + 4201fa: 48 39 d0 cmp %rdx,%rax + 4201fd: 0f 87 0d 01 00 00 ja 420310 <__libc_pvalloc+0x270> + 420203: 48 29 c6 sub %rax,%rsi + 420206: 49 39 f4 cmp %rsi,%r12 + 420209: 77 2d ja 420238 <__libc_pvalloc+0x198> + 42020b: 4c 85 c0 test %r8,%rax + 42020e: 0f 84 30 01 00 00 je 420344 <__libc_pvalloc+0x2a4> + 420214: 48 83 f8 20 cmp $0x20,%rax + 420218: bb 20 00 00 00 mov $0x20,%ebx + 42021d: 0f 84 fd fe ff ff je 420120 <__libc_pvalloc+0x80> + 420223: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 420228: 48 01 db add %rbx,%rbx + 42022b: 48 39 d8 cmp %rbx,%rax + 42022e: 77 f8 ja 420228 <__libc_pvalloc+0x188> + 420230: e9 eb fe ff ff jmpq 420120 <__libc_pvalloc+0x80> + 420235: 0f 1f 00 nopl (%rax) + 420238: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 42023f: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) + 420246: 48 83 c4 10 add $0x10,%rsp + 42024a: 31 c0 xor %eax,%eax + 42024c: 5b pop %rbx + 42024d: 5d pop %rbp + 42024e: 41 5c pop %r12 + 420250: c3 retq + 420251: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 420258: e8 03 6f ff ff callq 417160 + 42025d: 48 85 c0 test %rax,%rax + 420260: 48 89 c5 mov %rax,%rbp + 420263: 0f 85 0b ff ff ff jne 420174 <__libc_pvalloc+0xd4> + 420269: 49 8d 7c 1c 20 lea 0x20(%r12,%rbx,1),%rdi + 42026e: 31 f6 xor %esi,%esi + 420270: e8 db 71 ff ff callq 417450 + 420275: 4c 89 e2 mov %r12,%rdx + 420278: 48 89 de mov %rbx,%rsi + 42027b: 48 89 c7 mov %rax,%rdi + 42027e: 48 89 c5 mov %rax,%rbp + 420281: e8 8a c2 ff ff callq 41c510 <_int_memalign> + 420286: 48 85 c0 test %rax,%rax + 420289: 48 89 c2 mov %rax,%rdx + 42028c: 75 2a jne 4202b8 <__libc_pvalloc+0x218> + 42028e: 48 85 ed test %rbp,%rbp + 420291: 74 25 je 4202b8 <__libc_pvalloc+0x218> + 420293: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 420298: 90 nop + 420299: 48 89 ef mov %rbp,%rdi + 42029c: 4c 89 e6 mov %r12,%rsi + 42029f: e8 4c 77 ff ff callq 4179f0 + 4202a4: 4c 89 e2 mov %r12,%rdx + 4202a7: 48 89 de mov %rbx,%rsi + 4202aa: 48 89 c7 mov %rax,%rdi + 4202ad: 48 89 c5 mov %rax,%rbp + 4202b0: e8 5b c2 ff ff callq 41c510 <_int_memalign> + 4202b5: 48 89 c2 mov %rax,%rdx + 4202b8: 48 85 ed test %rbp,%rbp + 4202bb: 0f 85 cd fe ff ff jne 42018e <__libc_pvalloc+0xee> + 4202c1: e9 f5 fe ff ff jmpq 4201bb <__libc_pvalloc+0x11b> + 4202c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4202cd: 00 00 00 + 4202d0: 48 8d 42 f0 lea -0x10(%rdx),%rax + 4202d4: 48 25 00 00 00 fc and $0xfffffffffc000000,%rax + 4202da: 48 8b 08 mov (%rax),%rcx + 4202dd: e9 f7 fe ff ff jmpq 4201d9 <__libc_pvalloc+0x139> + 4202e2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4202e8: 48 83 c4 10 add $0x10,%rsp + 4202ec: 4c 89 e7 mov %r12,%rdi + 4202ef: 5b pop %rbx + 4202f0: 5d pop %rbp + 4202f1: 41 5c pop %r12 + 4202f3: e9 18 d7 ff ff jmpq 41da10 <__libc_malloc> + 4202f8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 4202ff: 00 + 420300: 48 83 c4 10 add $0x10,%rsp + 420304: 4c 89 e6 mov %r12,%rsi + 420307: 48 89 c7 mov %rax,%rdi + 42030a: 5b pop %rbx + 42030b: 5d pop %rbp + 42030c: 41 5c pop %r12 + 42030e: ff e1 jmpq *%rcx + 420310: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 420317: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) + 42031e: 31 c0 xor %eax,%eax + 420320: e9 c0 fe ff ff jmpq 4201e5 <__libc_pvalloc+0x145> + 420325: 0f 1f 00 nopl (%rax) + 420328: 31 c0 xor %eax,%eax + 42032a: e9 b6 fe ff ff jmpq 4201e5 <__libc_pvalloc+0x145> + 42032f: 90 nop + 420330: 48 89 7c 24 08 mov %rdi,0x8(%rsp) + 420335: e8 b6 e9 ff ff callq 41ecf0 + 42033a: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi + 42033f: e9 72 fd ff ff jmpq 4200b6 <__libc_pvalloc+0x16> + 420344: 48 89 c3 mov %rax,%rbx + 420347: e9 d4 fd ff ff jmpq 420120 <__libc_pvalloc+0x80> + 42034c: b9 08 2e 4a 00 mov $0x4a2e08,%ecx + 420351: ba 3c 0c 00 00 mov $0xc3c,%edx + 420356: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 42035b: bf 20 2a 4a 00 mov $0x4a2a20,%edi + 420360: e8 bb 6a ff ff callq 416e20 <__malloc_assert> + 420365: 90 nop + 420366: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42036d: 00 00 00 + +0000000000420370 <__malloc_trim>: + 420370: 41 57 push %r15 + 420372: 41 56 push %r14 + 420374: 41 55 push %r13 + 420376: 41 54 push %r12 + 420378: 55 push %rbp + 420379: 53 push %rbx + 42037a: 48 83 ec 28 sub $0x28,%rsp + 42037e: 8b 05 e0 a3 2a 00 mov 0x2aa3e0(%rip),%eax # 6ca764 <__libc_malloc_initialized> + 420384: 48 89 7c 24 18 mov %rdi,0x18(%rsp) + 420389: 85 c0 test %eax,%eax + 42038b: 0f 88 40 02 00 00 js 4205d1 <__malloc_trim+0x261> + 420391: 48 c7 44 24 08 00 a8 movq $0x6ca800,0x8(%rsp) + 420398: 6c 00 + 42039a: c7 44 24 14 00 00 00 movl $0x0,0x14(%rsp) + 4203a1: 00 + 4203a2: be 01 00 00 00 mov $0x1,%esi + 4203a7: 31 c0 xor %eax,%eax + 4203a9: 48 8b 54 24 08 mov 0x8(%rsp),%rdx + 4203ae: 83 3d 07 ce 2a 00 00 cmpl $0x0,0x2ace07(%rip) # 6cd1bc <__libc_multiple_threads> + 4203b5: 74 08 je 4203bf <__malloc_trim+0x4f> + 4203b7: f0 0f b1 32 lock cmpxchg %esi,(%rdx) + 4203bb: 75 07 jne 4203c4 <__malloc_trim+0x54> + 4203bd: eb 1b jmp 4203da <__malloc_trim+0x6a> + 4203bf: 0f b1 32 cmpxchg %esi,(%rdx) + 4203c2: 74 16 je 4203da <__malloc_trim+0x6a> + 4203c4: 48 8d 3a lea (%rdx),%rdi + 4203c7: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 4203ce: e8 fd 21 02 00 callq 4425d0 <__lll_lock_wait_private> + 4203d3: 48 81 c4 80 00 00 00 add $0x80,%rsp + 4203da: 45 31 db xor %r11d,%r11d + 4203dd: f6 42 04 04 testb $0x4,0x4(%rdx) + 4203e1: 74 5f je 420442 <__malloc_trim+0xd2> + 4203e3: 44 09 5c 24 14 or %r11d,0x14(%rsp) + 4203e8: 48 8b 54 24 08 mov 0x8(%rsp),%rdx + 4203ed: 83 3d c8 cd 2a 00 00 cmpl $0x0,0x2acdc8(%rip) # 6cd1bc <__libc_multiple_threads> + 4203f4: 74 07 je 4203fd <__malloc_trim+0x8d> + 4203f6: f0 ff 0a lock decl (%rdx) + 4203f9: 75 06 jne 420401 <__malloc_trim+0x91> + 4203fb: eb 1a jmp 420417 <__malloc_trim+0xa7> + 4203fd: ff 0a decl (%rdx) + 4203ff: 74 16 je 420417 <__malloc_trim+0xa7> + 420401: 48 8d 3a lea (%rdx),%rdi + 420404: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 42040b: e8 f0 21 02 00 callq 442600 <__lll_unlock_wake_private> + 420410: 48 81 c4 80 00 00 00 add $0x80,%rsp + 420417: 48 8b 82 68 08 00 00 mov 0x868(%rdx),%rax + 42041e: 48 3d 00 a8 6c 00 cmp $0x6ca800,%rax + 420424: 48 89 44 24 08 mov %rax,0x8(%rsp) + 420429: 0f 85 73 ff ff ff jne 4203a2 <__malloc_trim+0x32> + 42042f: 8b 44 24 14 mov 0x14(%rsp),%eax + 420433: 48 83 c4 28 add $0x28,%rsp + 420437: 5b pop %rbx + 420438: 5d pop %rbp + 420439: 41 5c pop %r12 + 42043b: 41 5d pop %r13 + 42043d: 41 5e pop %r14 + 42043f: 41 5f pop %r15 + 420441: c3 retq + 420442: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi + 420447: e8 e4 79 ff ff callq 417e30 + 42044c: 48 8b 0d 2d ad 2a 00 mov 0x2aad2d(%rip),%rcx # 6cb180 <_dl_pagesize> + 420453: 48 81 f9 ff 03 00 00 cmp $0x3ff,%rcx + 42045a: 0f 87 d3 00 00 00 ja 420533 <__malloc_trim+0x1c3> + 420460: 89 c8 mov %ecx,%eax + 420462: c1 e8 04 shr $0x4,%eax + 420465: 89 44 24 10 mov %eax,0x10(%rsp) + 420469: 4c 8d 71 ff lea -0x1(%rcx),%r14 + 42046d: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 420472: 45 31 db xor %r11d,%r11d + 420475: bd 01 00 00 00 mov $0x1,%ebp + 42047a: 4c 8d 69 2f lea 0x2f(%rcx),%r13 + 42047e: 4d 89 f7 mov %r14,%r15 + 420481: 4c 8d 60 58 lea 0x58(%rax),%r12 + 420485: 49 f7 d7 not %r15 + 420488: eb 1b jmp 4204a5 <__malloc_trim+0x135> + 42048a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 420490: 39 6c 24 10 cmp %ebp,0x10(%rsp) + 420494: 7e 14 jle 4204aa <__malloc_trim+0x13a> + 420496: 83 c5 01 add $0x1,%ebp + 420499: 49 83 c4 10 add $0x10,%r12 + 42049d: 81 fd 80 00 00 00 cmp $0x80,%ebp + 4204a3: 74 75 je 42051a <__malloc_trim+0x1aa> + 4204a5: 83 fd 01 cmp $0x1,%ebp + 4204a8: 75 e6 jne 420490 <__malloc_trim+0x120> + 4204aa: 49 8b 5c 24 18 mov 0x18(%r12),%rbx + 4204af: 49 39 dc cmp %rbx,%r12 + 4204b2: 75 15 jne 4204c9 <__malloc_trim+0x159> + 4204b4: eb e0 jmp 420496 <__malloc_trim+0x126> + 4204b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4204bd: 00 00 00 + 4204c0: 48 8b 5b 18 mov 0x18(%rbx),%rbx + 4204c4: 49 39 dc cmp %rbx,%r12 + 4204c7: 74 cd je 420496 <__malloc_trim+0x126> + 4204c9: 48 8b 73 08 mov 0x8(%rbx),%rsi + 4204cd: 48 83 e6 f8 and $0xfffffffffffffff8,%rsi + 4204d1: 4c 39 ee cmp %r13,%rsi + 4204d4: 76 ea jbe 4204c0 <__malloc_trim+0x150> + 4204d6: 4a 8d 3c 2b lea (%rbx,%r13,1),%rdi + 4204da: 48 8d 43 30 lea 0x30(%rbx),%rax + 4204de: 4c 21 ff and %r15,%rdi + 4204e1: 48 39 c7 cmp %rax,%rdi + 4204e4: 0f 82 b3 00 00 00 jb 42059d <__malloc_trim+0x22d> + 4204ea: 48 8d 04 33 lea (%rbx,%rsi,1),%rax + 4204ee: 48 39 c7 cmp %rax,%rdi + 4204f1: 0f 83 8d 00 00 00 jae 420584 <__malloc_trim+0x214> + 4204f7: 48 89 f8 mov %rdi,%rax + 4204fa: 48 29 d8 sub %rbx,%rax + 4204fd: 48 29 c6 sub %rax,%rsi + 420500: 49 39 f6 cmp %rsi,%r14 + 420503: 73 bb jae 4204c0 <__malloc_trim+0x150> + 420505: 4c 21 fe and %r15,%rsi + 420508: ba 04 00 00 00 mov $0x4,%edx + 42050d: e8 de f7 01 00 callq 43fcf0 <__madvise> + 420512: 41 bb 01 00 00 00 mov $0x1,%r11d + 420518: eb a6 jmp 4204c0 <__malloc_trim+0x150> + 42051a: 31 c0 xor %eax,%eax + 42051c: 48 81 7c 24 08 00 a8 cmpq $0x6ca800,0x8(%rsp) + 420523: 6c 00 + 420525: 0f 84 d1 00 00 00 je 4205fc <__malloc_trim+0x28c> + 42052b: 41 09 c3 or %eax,%r11d + 42052e: e9 b0 fe ff ff jmpq 4203e3 <__malloc_trim+0x73> + 420533: 49 89 cc mov %rcx,%r12 + 420536: 49 c1 ec 06 shr $0x6,%r12 + 42053a: 49 83 fc 30 cmp $0x30,%r12 + 42053e: 77 0e ja 42054e <__malloc_trim+0x1de> + 420540: 41 8d 44 24 30 lea 0x30(%r12),%eax + 420545: 89 44 24 10 mov %eax,0x10(%rsp) + 420549: e9 1b ff ff ff jmpq 420469 <__malloc_trim+0xf9> + 42054e: 49 89 cc mov %rcx,%r12 + 420551: 49 c1 ec 09 shr $0x9,%r12 + 420555: 49 83 fc 14 cmp $0x14,%r12 + 420559: 76 1b jbe 420576 <__malloc_trim+0x206> + 42055b: 49 89 cc mov %rcx,%r12 + 42055e: 49 c1 ec 0c shr $0xc,%r12 + 420562: 49 83 fc 0a cmp $0xa,%r12 + 420566: 77 4e ja 4205b6 <__malloc_trim+0x246> + 420568: 41 8d 44 24 6e lea 0x6e(%r12),%eax + 42056d: 89 44 24 10 mov %eax,0x10(%rsp) + 420571: e9 f3 fe ff ff jmpq 420469 <__malloc_trim+0xf9> + 420576: 41 8d 44 24 5b lea 0x5b(%r12),%eax + 42057b: 89 44 24 10 mov %eax,0x10(%rsp) + 42057f: e9 e5 fe ff ff jmpq 420469 <__malloc_trim+0xf9> + 420584: b9 1a 23 4a 00 mov $0x4a231a,%ecx + 420589: ba aa 11 00 00 mov $0x11aa,%edx + 42058e: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 420593: bf 38 2b 4a 00 mov $0x4a2b38,%edi + 420598: e8 83 68 ff ff callq 416e20 <__malloc_assert> + 42059d: b9 1a 23 4a 00 mov $0x4a231a,%ecx + 4205a2: ba a9 11 00 00 mov $0x11a9,%edx + 4205a7: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 4205ac: bf 00 2b 4a 00 mov $0x4a2b00,%edi + 4205b1: e8 6a 68 ff ff callq 416e20 <__malloc_assert> + 4205b6: 49 89 cc mov %rcx,%r12 + 4205b9: 49 c1 ec 0f shr $0xf,%r12 + 4205bd: 49 83 fc 04 cmp $0x4,%r12 + 4205c1: 77 18 ja 4205db <__malloc_trim+0x26b> + 4205c3: 41 8d 44 24 77 lea 0x77(%r12),%eax + 4205c8: 89 44 24 10 mov %eax,0x10(%rsp) + 4205cc: e9 98 fe ff ff jmpq 420469 <__malloc_trim+0xf9> + 4205d1: e8 1a e7 ff ff callq 41ecf0 + 4205d6: e9 b6 fd ff ff jmpq 420391 <__malloc_trim+0x21> + 4205db: 48 89 c8 mov %rcx,%rax + 4205de: 48 c1 e8 12 shr $0x12,%rax + 4205e2: 44 8d 60 7c lea 0x7c(%rax),%r12d + 4205e6: 48 83 f8 02 cmp $0x2,%rax + 4205ea: b8 7e 00 00 00 mov $0x7e,%eax + 4205ef: 41 0f 46 c4 cmovbe %r12d,%eax + 4205f3: 89 44 24 10 mov %eax,0x10(%rsp) + 4205f7: e9 6d fe ff ff jmpq 420469 <__malloc_trim+0xf9> + 4205fc: 48 8b 7c 24 18 mov 0x18(%rsp),%rdi + 420601: ba 80 b0 6c 00 mov $0x6cb080,%edx + 420606: be 58 a8 6c 00 mov $0x6ca858,%esi + 42060b: 44 89 5c 24 10 mov %r11d,0x10(%rsp) + 420610: e8 8b 6d ff ff callq 4173a0 + 420615: 44 8b 5c 24 10 mov 0x10(%rsp),%r11d + 42061a: e9 0c ff ff ff jmpq 42052b <__malloc_trim+0x1bb> + 42061f: 90 nop + +0000000000420620 <__libc_mallinfo>: + 420620: 41 54 push %r12 + 420622: 55 push %rbp + 420623: 49 89 fc mov %rdi,%r12 + 420626: 53 push %rbx + 420627: 48 83 ec 30 sub $0x30,%rsp + 42062b: 8b 05 33 a1 2a 00 mov 0x2aa133(%rip),%eax # 6ca764 <__libc_malloc_initialized> + 420631: 85 c0 test %eax,%eax + 420633: 0f 88 ef 00 00 00 js 420728 <__libc_mallinfo+0x108> + 420639: 48 c7 04 24 00 00 00 movq $0x0,(%rsp) + 420640: 00 + 420641: 48 c7 44 24 08 00 00 movq $0x0,0x8(%rsp) + 420648: 00 00 + 42064a: bb 00 a8 6c 00 mov $0x6ca800,%ebx + 42064f: 48 c7 44 24 10 00 00 movq $0x0,0x10(%rsp) + 420656: 00 00 + 420658: 48 c7 44 24 18 00 00 movq $0x0,0x18(%rsp) + 42065f: 00 00 + 420661: bd 01 00 00 00 mov $0x1,%ebp + 420666: 48 c7 44 24 20 00 00 movq $0x0,0x20(%rsp) + 42066d: 00 00 + 42066f: 90 nop + 420670: 89 ee mov %ebp,%esi + 420672: 31 c0 xor %eax,%eax + 420674: 83 3d 41 cb 2a 00 00 cmpl $0x0,0x2acb41(%rip) # 6cd1bc <__libc_multiple_threads> + 42067b: 74 08 je 420685 <__libc_mallinfo+0x65> + 42067d: f0 0f b1 33 lock cmpxchg %esi,(%rbx) + 420681: 75 07 jne 42068a <__libc_mallinfo+0x6a> + 420683: eb 1b jmp 4206a0 <__libc_mallinfo+0x80> + 420685: 0f b1 33 cmpxchg %esi,(%rbx) + 420688: 74 16 je 4206a0 <__libc_mallinfo+0x80> + 42068a: 48 8d 3b lea (%rbx),%rdi + 42068d: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 420694: e8 37 1f 02 00 callq 4425d0 <__lll_lock_wait_private> + 420699: 48 81 c4 80 00 00 00 add $0x80,%rsp + 4206a0: 48 89 e6 mov %rsp,%rsi + 4206a3: 48 89 df mov %rbx,%rdi + 4206a6: e8 15 82 ff ff callq 4188c0 + 4206ab: 83 3d 0a cb 2a 00 00 cmpl $0x0,0x2acb0a(%rip) # 6cd1bc <__libc_multiple_threads> + 4206b2: 74 07 je 4206bb <__libc_mallinfo+0x9b> + 4206b4: f0 ff 0b lock decl (%rbx) + 4206b7: 75 06 jne 4206bf <__libc_mallinfo+0x9f> + 4206b9: eb 1a jmp 4206d5 <__libc_mallinfo+0xb5> + 4206bb: ff 0b decl (%rbx) + 4206bd: 74 16 je 4206d5 <__libc_mallinfo+0xb5> + 4206bf: 48 8d 3b lea (%rbx),%rdi + 4206c2: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 4206c9: e8 32 1f 02 00 callq 442600 <__lll_unlock_wake_private> + 4206ce: 48 81 c4 80 00 00 00 add $0x80,%rsp + 4206d5: 48 8b 9b 68 08 00 00 mov 0x868(%rbx),%rbx + 4206dc: 48 81 fb 00 a8 6c 00 cmp $0x6ca800,%rbx + 4206e3: 75 8b jne 420670 <__libc_mallinfo+0x50> + 4206e5: 48 8b 04 24 mov (%rsp),%rax + 4206e9: 49 89 04 24 mov %rax,(%r12) + 4206ed: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4206f2: 49 89 44 24 08 mov %rax,0x8(%r12) + 4206f7: 48 8b 44 24 10 mov 0x10(%rsp),%rax + 4206fc: 49 89 44 24 10 mov %rax,0x10(%r12) + 420701: 48 8b 44 24 18 mov 0x18(%rsp),%rax + 420706: 49 89 44 24 18 mov %rax,0x18(%r12) + 42070b: 48 8b 44 24 20 mov 0x20(%rsp),%rax + 420710: 49 89 44 24 20 mov %rax,0x20(%r12) + 420715: 48 83 c4 30 add $0x30,%rsp + 420719: 4c 89 e0 mov %r12,%rax + 42071c: 5b pop %rbx + 42071d: 5d pop %rbp + 42071e: 41 5c pop %r12 + 420720: c3 retq + 420721: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 420728: e8 c3 e5 ff ff callq 41ecf0 + 42072d: e9 07 ff ff ff jmpq 420639 <__libc_mallinfo+0x19> + 420732: 0f 1f 40 00 nopl 0x0(%rax) + 420736: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42073d: 00 00 00 + +0000000000420740 <__malloc_stats>: + 420740: 41 57 push %r15 + 420742: 41 56 push %r14 + 420744: 41 55 push %r13 + 420746: 41 54 push %r12 + 420748: 55 push %rbp + 420749: 53 push %rbx + 42074a: 48 83 ec 38 sub $0x38,%rsp + 42074e: 8b 05 10 a0 2a 00 mov 0x2aa010(%rip),%eax # 6ca764 <__libc_malloc_initialized> + 420754: 4c 8b 25 7d a0 2a 00 mov 0x2aa07d(%rip),%r12 # 6ca7d8 + 42075b: 85 c0 test %eax,%eax + 42075d: 45 89 e5 mov %r12d,%r13d + 420760: 0f 88 ba 01 00 00 js 420920 <__malloc_stats+0x1e0> + 420766: 48 8b 05 cb 9f 2a 00 mov 0x2a9fcb(%rip),%rax # 6ca738 <_IO_stderr> + 42076d: bb 00 a8 6c 00 mov $0x6ca800,%ebx + 420772: 31 ed xor %ebp,%ebp + 420774: 41 be 01 00 00 00 mov $0x1,%r14d + 42077a: 44 8b 78 74 mov 0x74(%rax),%r15d + 42077e: 44 89 fa mov %r15d,%edx + 420781: 83 ca 02 or $0x2,%edx + 420784: 89 50 74 mov %edx,0x74(%rax) + 420787: eb 0a jmp 420793 <__malloc_stats+0x53> + 420789: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 420790: 83 c5 01 add $0x1,%ebp + 420793: 48 c7 04 24 00 00 00 movq $0x0,(%rsp) + 42079a: 00 + 42079b: 48 c7 44 24 08 00 00 movq $0x0,0x8(%rsp) + 4207a2: 00 00 + 4207a4: 44 89 f6 mov %r14d,%esi + 4207a7: 48 c7 44 24 10 00 00 movq $0x0,0x10(%rsp) + 4207ae: 00 00 + 4207b0: 48 c7 44 24 18 00 00 movq $0x0,0x18(%rsp) + 4207b7: 00 00 + 4207b9: 31 c0 xor %eax,%eax + 4207bb: 48 c7 44 24 20 00 00 movq $0x0,0x20(%rsp) + 4207c2: 00 00 + 4207c4: 83 3d f1 c9 2a 00 00 cmpl $0x0,0x2ac9f1(%rip) # 6cd1bc <__libc_multiple_threads> + 4207cb: 74 08 je 4207d5 <__malloc_stats+0x95> + 4207cd: f0 0f b1 33 lock cmpxchg %esi,(%rbx) + 4207d1: 75 07 jne 4207da <__malloc_stats+0x9a> + 4207d3: eb 1b jmp 4207f0 <__malloc_stats+0xb0> + 4207d5: 0f b1 33 cmpxchg %esi,(%rbx) + 4207d8: 74 16 je 4207f0 <__malloc_stats+0xb0> + 4207da: 48 8d 3b lea (%rbx),%rdi + 4207dd: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 4207e4: e8 e7 1d 02 00 callq 4425d0 <__lll_lock_wait_private> + 4207e9: 48 81 c4 80 00 00 00 add $0x80,%rsp + 4207f0: 48 89 e6 mov %rsp,%rsi + 4207f3: 48 89 df mov %rbx,%rdi + 4207f6: e8 c5 80 ff ff callq 4188c0 + 4207fb: 48 8b 3d 36 9f 2a 00 mov 0x2a9f36(%rip),%rdi # 6ca738 <_IO_stderr> + 420802: 89 ea mov %ebp,%edx + 420804: be 5e 22 4a 00 mov $0x4a225e,%esi + 420809: 31 c0 xor %eax,%eax + 42080b: e8 90 bb 03 00 callq 45c3a0 <__fprintf> + 420810: 8b 14 24 mov (%rsp),%edx + 420813: 48 8b 3d 1e 9f 2a 00 mov 0x2a9f1e(%rip),%rdi # 6ca738 <_IO_stderr> + 42081a: be 69 22 4a 00 mov $0x4a2269,%esi + 42081f: 31 c0 xor %eax,%eax + 420821: e8 7a bb 03 00 callq 45c3a0 <__fprintf> + 420826: 8b 54 24 1c mov 0x1c(%rsp),%edx + 42082a: 48 8b 3d 07 9f 2a 00 mov 0x2a9f07(%rip),%rdi # 6ca738 <_IO_stderr> + 420831: be 82 22 4a 00 mov $0x4a2282,%esi + 420836: 31 c0 xor %eax,%eax + 420838: e8 63 bb 03 00 callq 45c3a0 <__fprintf> + 42083d: 44 03 24 24 add (%rsp),%r12d + 420841: 44 03 6c 24 1c add 0x1c(%rsp),%r13d + 420846: 83 3d 6f c9 2a 00 00 cmpl $0x0,0x2ac96f(%rip) # 6cd1bc <__libc_multiple_threads> + 42084d: 74 07 je 420856 <__malloc_stats+0x116> + 42084f: f0 ff 0b lock decl (%rbx) + 420852: 75 06 jne 42085a <__malloc_stats+0x11a> + 420854: eb 1a jmp 420870 <__malloc_stats+0x130> + 420856: ff 0b decl (%rbx) + 420858: 74 16 je 420870 <__malloc_stats+0x130> + 42085a: 48 8d 3b lea (%rbx),%rdi + 42085d: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 420864: e8 97 1d 02 00 callq 442600 <__lll_unlock_wake_private> + 420869: 48 81 c4 80 00 00 00 add $0x80,%rsp + 420870: 48 8b 9b 68 08 00 00 mov 0x868(%rbx),%rbx + 420877: 48 81 fb 00 a8 6c 00 cmp $0x6ca800,%rbx + 42087e: 0f 85 0c ff ff ff jne 420790 <__malloc_stats+0x50> + 420884: 48 8b 0d ad 9e 2a 00 mov 0x2a9ead(%rip),%rcx # 6ca738 <_IO_stderr> + 42088b: ba 14 00 00 00 mov $0x14,%edx + 420890: be 01 00 00 00 mov $0x1,%esi + 420895: bf 9b 22 4a 00 mov $0x4a229b,%edi + 42089a: e8 e1 24 04 00 callq 462d80 <_IO_fwrite> + 42089f: 48 8b 3d 92 9e 2a 00 mov 0x2a9e92(%rip),%rdi # 6ca738 <_IO_stderr> + 4208a6: 44 89 e2 mov %r12d,%edx + 4208a9: be 69 22 4a 00 mov $0x4a2269,%esi + 4208ae: 31 c0 xor %eax,%eax + 4208b0: e8 eb ba 03 00 callq 45c3a0 <__fprintf> + 4208b5: 48 8b 3d 7c 9e 2a 00 mov 0x2a9e7c(%rip),%rdi # 6ca738 <_IO_stderr> + 4208bc: 44 89 ea mov %r13d,%edx + 4208bf: be 82 22 4a 00 mov $0x4a2282,%esi + 4208c4: 31 c0 xor %eax,%eax + 4208c6: e8 d5 ba 03 00 callq 45c3a0 <__fprintf> + 4208cb: 8b 15 ff 9e 2a 00 mov 0x2a9eff(%rip),%edx # 6ca7d0 + 4208d1: 48 8b 3d 60 9e 2a 00 mov 0x2a9e60(%rip),%rdi # 6ca738 <_IO_stderr> + 4208d8: be b0 22 4a 00 mov $0x4a22b0,%esi + 4208dd: 31 c0 xor %eax,%eax + 4208df: e8 bc ba 03 00 callq 45c3a0 <__fprintf> + 4208e4: 48 8b 15 f5 9e 2a 00 mov 0x2a9ef5(%rip),%rdx # 6ca7e0 + 4208eb: 48 8b 3d 46 9e 2a 00 mov 0x2a9e46(%rip),%rdi # 6ca738 <_IO_stderr> + 4208f2: be c9 22 4a 00 mov $0x4a22c9,%esi + 4208f7: 31 c0 xor %eax,%eax + 4208f9: e8 a2 ba 03 00 callq 45c3a0 <__fprintf> + 4208fe: 48 8b 05 33 9e 2a 00 mov 0x2a9e33(%rip),%rax # 6ca738 <_IO_stderr> + 420905: 44 09 78 74 or %r15d,0x74(%rax) + 420909: 48 83 c4 38 add $0x38,%rsp + 42090d: 5b pop %rbx + 42090e: 5d pop %rbp + 42090f: 41 5c pop %r12 + 420911: 41 5d pop %r13 + 420913: 41 5e pop %r14 + 420915: 41 5f pop %r15 + 420917: c3 retq + 420918: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 42091f: 00 + 420920: e8 cb e3 ff ff callq 41ecf0 + 420925: e9 3c fe ff ff jmpq 420766 <__malloc_stats+0x26> + 42092a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + +0000000000420930 <__malloc_info.part.7>: + 420930: 41 57 push %r15 + 420932: 41 56 push %r14 + 420934: 41 55 push %r13 + 420936: 41 54 push %r12 + 420938: 55 push %rbp + 420939: 53 push %rbx + 42093a: 48 89 fb mov %rdi,%rbx + 42093d: 48 81 ec 98 11 00 00 sub $0x1198,%rsp + 420944: 8b 0d 1a 9e 2a 00 mov 0x2a9e1a(%rip),%ecx # 6ca764 <__libc_malloc_initialized> + 42094a: 85 c9 test %ecx,%ecx + 42094c: 0f 88 55 04 00 00 js 420da7 <__malloc_info.part.7+0x477> + 420952: 48 89 de mov %rbx,%rsi + 420955: bf e3 22 4a 00 mov $0x4a22e3,%edi + 42095a: e8 31 22 04 00 callq 462b90 <_IO_fputs> + 42095f: 48 8d 84 24 b8 01 00 lea 0x1b8(%rsp),%rax + 420966: 00 + 420967: 48 c7 44 24 10 00 a8 movq $0x6ca800,0x10(%rsp) + 42096e: 6c 00 + 420970: 48 c7 44 24 20 00 00 movq $0x0,0x20(%rsp) + 420977: 00 00 + 420979: 48 c7 44 24 18 00 00 movq $0x0,0x18(%rsp) + 420980: 00 00 + 420982: 48 c7 44 24 50 00 00 movq $0x0,0x50(%rsp) + 420989: 00 00 + 42098b: 31 d2 xor %edx,%edx + 42098d: 48 c7 44 24 48 00 00 movq $0x0,0x48(%rsp) + 420994: 00 00 + 420996: 48 c7 44 24 30 00 00 movq $0x0,0x30(%rsp) + 42099d: 00 00 + 42099f: 48 c7 44 24 40 00 00 movq $0x0,0x40(%rsp) + 4209a6: 00 00 + 4209a8: 48 c7 44 24 28 00 00 movq $0x0,0x28(%rsp) + 4209af: 00 00 + 4209b1: 48 c7 44 24 38 00 00 movq $0x0,0x38(%rsp) + 4209b8: 00 00 + 4209ba: 48 89 44 24 68 mov %rax,0x68(%rsp) + 4209bf: 8d 42 01 lea 0x1(%rdx),%eax + 4209c2: be f9 22 4a 00 mov $0x4a22f9,%esi + 4209c7: 48 89 df mov %rbx,%rdi + 4209ca: 89 44 24 64 mov %eax,0x64(%rsp) + 4209ce: 31 c0 xor %eax,%eax + 4209d0: e8 cb b9 03 00 callq 45c3a0 <__fprintf> + 4209d5: be 01 00 00 00 mov $0x1,%esi + 4209da: 31 c0 xor %eax,%eax + 4209dc: 48 8b 54 24 10 mov 0x10(%rsp),%rdx + 4209e1: 83 3d d4 c7 2a 00 00 cmpl $0x0,0x2ac7d4(%rip) # 6cd1bc <__libc_multiple_threads> + 4209e8: 74 08 je 4209f2 <__malloc_info.part.7+0xc2> + 4209ea: f0 0f b1 32 lock cmpxchg %esi,(%rdx) + 4209ee: 75 07 jne 4209f7 <__malloc_info.part.7+0xc7> + 4209f0: eb 1b jmp 420a0d <__malloc_info.part.7+0xdd> + 4209f2: 0f b1 32 cmpxchg %esi,(%rdx) + 4209f5: 74 16 je 420a0d <__malloc_info.part.7+0xdd> + 4209f7: 48 8d 3a lea (%rdx),%rdi + 4209fa: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 420a01: e8 ca 1b 02 00 callq 4425d0 <__lll_lock_wait_private> + 420a06: 48 81 c4 80 00 00 00 add $0x80,%rsp + 420a0d: 4c 8b 4c 24 68 mov 0x68(%rsp),%r9 + 420a12: 48 8d 7a 08 lea 0x8(%rdx),%rdi + 420a16: 48 8d 4c 24 78 lea 0x78(%rsp),%rcx + 420a1b: 45 31 c0 xor %r8d,%r8d + 420a1e: 45 31 e4 xor %r12d,%r12d + 420a21: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 420a28: 48 8b 07 mov (%rdi),%rax + 420a2b: 48 85 c0 test %rax,%rax + 420a2e: 0f 84 fa 02 00 00 je 420d2e <__malloc_info.part.7+0x3fe> + 420a34: 48 8b 70 08 mov 0x8(%rax),%rsi + 420a38: 31 d2 xor %edx,%edx + 420a3a: 48 83 e6 f8 and $0xfffffffffffffff8,%rsi + 420a3e: 66 90 xchg %ax,%ax + 420a40: 48 8b 40 10 mov 0x10(%rax),%rax + 420a44: 48 83 c2 01 add $0x1,%rdx + 420a48: 48 85 c0 test %rax,%rax + 420a4b: 75 f3 jne 420a40 <__malloc_info.part.7+0x110> + 420a4d: 48 89 f0 mov %rsi,%rax + 420a50: 49 01 d0 add %rdx,%r8 + 420a53: 48 89 31 mov %rsi,(%rcx) + 420a56: 48 0f af c2 imul %rdx,%rax + 420a5a: 48 89 51 10 mov %rdx,0x10(%rcx) + 420a5e: 49 01 c4 add %rax,%r12 + 420a61: 48 8d 46 f1 lea -0xf(%rsi),%rax + 420a65: 48 89 41 f8 mov %rax,-0x8(%rcx) + 420a69: 48 0f af 11 imul (%rcx),%rdx + 420a6d: 48 83 c1 20 add $0x20,%rcx + 420a71: 48 83 c7 08 add $0x8,%rdi + 420a75: 48 89 51 e8 mov %rdx,-0x18(%rcx) + 420a79: 49 39 c9 cmp %rcx,%r9 + 420a7c: 75 aa jne 420a28 <__malloc_info.part.7+0xf8> + 420a7e: 48 8b 44 24 10 mov 0x10(%rsp),%rax + 420a83: 4c 8d 94 24 b0 01 00 lea 0x1b0(%rsp),%r10 + 420a8a: 00 + 420a8b: 4c 8d 9c 24 90 11 00 lea 0x1190(%rsp),%r11 + 420a92: 00 + 420a93: 4c 89 44 24 58 mov %r8,0x58(%rsp) + 420a98: 45 31 f6 xor %r14d,%r14d + 420a9b: 45 31 c0 xor %r8d,%r8d + 420a9e: 4c 8d 48 58 lea 0x58(%rax),%r9 + 420aa2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 420aa8: 49 8b 51 10 mov 0x10(%r9),%rdx + 420aac: 66 0f ef d2 pxor %xmm2,%xmm2 + 420ab0: 66 0f 6f 0d 28 25 08 movdqa 0x82528(%rip),%xmm1 # 4a2fe0 <__func__.10972+0x20> + 420ab7: 00 + 420ab8: 48 85 d2 test %rdx,%rdx + 420abb: 41 0f 29 0a movaps %xmm1,(%r10) + 420abf: 41 0f 29 52 10 movaps %xmm2,0x10(%r10) + 420ac4: 0f 84 56 02 00 00 je 420d20 <__malloc_info.part.7+0x3f0> + 420aca: 49 39 d1 cmp %rdx,%r9 + 420acd: 0f 84 4d 02 00 00 je 420d20 <__malloc_info.part.7+0x3f0> + 420ad3: 49 8b 42 18 mov 0x18(%r10),%rax + 420ad7: 49 8b 6a 10 mov 0x10(%r10),%rbp + 420adb: 31 c9 xor %ecx,%ecx + 420add: 49 8b 32 mov (%r10),%rsi + 420ae0: 48 8d 78 01 lea 0x1(%rax),%rdi + 420ae4: eb 0d jmp 420af3 <__malloc_info.part.7+0x1c3> + 420ae6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 420aed: 00 00 00 + 420af0: 48 89 c7 mov %rax,%rdi + 420af3: 48 8b 42 08 mov 0x8(%rdx),%rax + 420af7: 48 8b 52 10 mov 0x10(%rdx),%rdx + 420afb: 48 01 c5 add %rax,%rbp + 420afe: 48 39 c6 cmp %rax,%rsi + 420b01: 48 0f 47 f0 cmova %rax,%rsi + 420b05: 48 39 c1 cmp %rax,%rcx + 420b08: 48 0f 42 c8 cmovb %rax,%rcx + 420b0c: 49 39 d1 cmp %rdx,%r9 + 420b0f: 48 8d 47 01 lea 0x1(%rdi),%rax + 420b13: 75 db jne 420af0 <__malloc_info.part.7+0x1c0> + 420b15: 48 89 74 24 08 mov %rsi,0x8(%rsp) + 420b1a: 48 85 ff test %rdi,%rdi + 420b1d: f3 0f 7e 44 24 08 movq 0x8(%rsp),%xmm0 + 420b23: 48 89 4c 24 08 mov %rcx,0x8(%rsp) + 420b28: 0f 16 44 24 08 movhps 0x8(%rsp),%xmm0 + 420b2d: 48 89 6c 24 08 mov %rbp,0x8(%rsp) + 420b32: 41 0f 29 02 movaps %xmm0,(%r10) + 420b36: f3 0f 7e 44 24 08 movq 0x8(%rsp),%xmm0 + 420b3c: 48 89 7c 24 08 mov %rdi,0x8(%rsp) + 420b41: 0f 16 44 24 08 movhps 0x8(%rsp),%xmm0 + 420b46: 41 0f 29 42 10 movaps %xmm0,0x10(%r10) + 420b4b: 0f 84 cf 01 00 00 je 420d20 <__malloc_info.part.7+0x3f0> + 420b51: 4d 89 c7 mov %r8,%r15 + 420b54: 49 83 c2 20 add $0x20,%r10 + 420b58: 49 01 fe add %rdi,%r14 + 420b5b: 49 83 c1 10 add $0x10,%r9 + 420b5f: 4d 03 7a f0 add -0x10(%r10),%r15 + 420b63: 4d 39 d3 cmp %r10,%r11 + 420b66: 4d 89 f8 mov %r15,%r8 + 420b69: 0f 85 39 ff ff ff jne 420aa8 <__malloc_info.part.7+0x178> + 420b6f: 48 8b 74 24 10 mov 0x10(%rsp),%rsi + 420b74: 83 3d 41 c6 2a 00 00 cmpl $0x0,0x2ac641(%rip) # 6cd1bc <__libc_multiple_threads> + 420b7b: 74 07 je 420b84 <__malloc_info.part.7+0x254> + 420b7d: f0 ff 0e lock decl (%rsi) + 420b80: 75 06 jne 420b88 <__malloc_info.part.7+0x258> + 420b82: eb 1a jmp 420b9e <__malloc_info.part.7+0x26e> + 420b84: ff 0e decl (%rsi) + 420b86: 74 16 je 420b9e <__malloc_info.part.7+0x26e> + 420b88: 48 8d 3e lea (%rsi),%rdi + 420b8b: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 420b92: e8 69 1a 02 00 callq 442600 <__lll_unlock_wake_private> + 420b97: 48 81 c4 80 00 00 00 add $0x80,%rsp + 420b9e: 48 8b 74 24 58 mov 0x58(%rsp),%rsi + 420ba3: 4c 01 64 24 30 add %r12,0x30(%rsp) + 420ba8: 48 8d ac 24 88 00 00 lea 0x88(%rsp),%rbp + 420baf: 00 + 420bb0: 48 01 74 24 28 add %rsi,0x28(%rsp) + 420bb5: 45 31 ed xor %r13d,%r13d + 420bb8: 4c 01 74 24 38 add %r14,0x38(%rsp) + 420bbd: 4c 01 7c 24 40 add %r15,0x40(%rsp) + 420bc2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 420bc8: 49 83 fd 0a cmp $0xa,%r13 + 420bcc: 4c 8b 4d 00 mov 0x0(%rbp),%r9 + 420bd0: 74 20 je 420bf2 <__malloc_info.part.7+0x2c2> + 420bd2: 4d 85 c9 test %r9,%r9 + 420bd5: 74 1b je 420bf2 <__malloc_info.part.7+0x2c2> + 420bd7: 48 8b 4d f0 mov -0x10(%rbp),%rcx + 420bdb: 48 8b 55 e8 mov -0x18(%rbp),%rdx + 420bdf: be 60 2b 4a 00 mov $0x4a2b60,%esi + 420be4: 4c 8b 45 f8 mov -0x8(%rbp),%r8 + 420be8: 48 89 df mov %rbx,%rdi + 420beb: 31 c0 xor %eax,%eax + 420bed: e8 ae b7 03 00 callq 45c3a0 <__fprintf> + 420bf2: 49 83 c5 01 add $0x1,%r13 + 420bf6: 48 83 c5 20 add $0x20,%rbp + 420bfa: 49 81 fd 89 00 00 00 cmp $0x89,%r13 + 420c01: 75 c5 jne 420bc8 <__malloc_info.part.7+0x298> + 420c03: 4c 8b 8c 24 c8 01 00 mov 0x1c8(%rsp),%r9 + 420c0a: 00 + 420c0b: 4d 85 c9 test %r9,%r9 + 420c0e: 0f 85 38 01 00 00 jne 420d4c <__malloc_info.part.7+0x41c> + 420c14: 48 8b 6c 24 10 mov 0x10(%rsp),%rbp + 420c19: 4d 89 f9 mov %r15,%r9 + 420c1c: 4d 89 f0 mov %r14,%r8 + 420c1f: 4c 89 e1 mov %r12,%rcx + 420c22: be e8 2b 4a 00 mov $0x4a2be8,%esi + 420c27: 48 89 df mov %rbx,%rdi + 420c2a: 48 8b 85 80 08 00 00 mov 0x880(%rbp),%rax + 420c31: 48 8b 95 88 08 00 00 mov 0x888(%rbp),%rdx + 420c38: 48 01 44 24 48 add %rax,0x48(%rsp) + 420c3d: 48 01 54 24 50 add %rdx,0x50(%rsp) + 420c42: 52 push %rdx + 420c43: 50 push %rax + 420c44: 31 c0 xor %eax,%eax + 420c46: 48 8b 54 24 68 mov 0x68(%rsp),%rdx + 420c4b: e8 50 b7 03 00 callq 45c3a0 <__fprintf> + 420c50: 48 81 fd 00 a8 6c 00 cmp $0x6ca800,%rbp + 420c57: 58 pop %rax + 420c58: 5a pop %rdx + 420c59: 0f 84 19 01 00 00 je 420d78 <__malloc_info.part.7+0x448> + 420c5f: 48 8b 45 58 mov 0x58(%rbp),%rax + 420c63: be 90 2c 4a 00 mov $0x4a2c90,%esi + 420c68: 48 89 df mov %rbx,%rdi + 420c6b: 48 89 c5 mov %rax,%rbp + 420c6e: 48 89 44 24 08 mov %rax,0x8(%rsp) + 420c73: 31 c0 xor %eax,%eax + 420c75: 48 81 e5 00 00 00 fc and $0xfffffffffc000000,%rbp + 420c7c: 48 8b 4d 18 mov 0x18(%rbp),%rcx + 420c80: 48 8b 55 10 mov 0x10(%rbp),%rdx + 420c84: e8 17 b7 03 00 callq 45c3a0 <__fprintf> + 420c89: 48 8b 75 10 mov 0x10(%rbp),%rsi + 420c8d: 48 01 74 24 18 add %rsi,0x18(%rsp) + 420c92: 48 8b 75 18 mov 0x18(%rbp),%rsi + 420c96: 48 01 74 24 20 add %rsi,0x20(%rsp) + 420c9b: 48 89 de mov %rbx,%rsi + 420c9e: bf 11 23 4a 00 mov $0x4a2311,%edi + 420ca3: e8 e8 1e 04 00 callq 462b90 <_IO_fputs> + 420ca8: 48 8b 44 24 10 mov 0x10(%rsp),%rax + 420cad: 8b 54 24 64 mov 0x64(%rsp),%edx + 420cb1: 48 8b 80 68 08 00 00 mov 0x868(%rax),%rax + 420cb8: 48 3d 00 a8 6c 00 cmp $0x6ca800,%rax + 420cbe: 48 89 44 24 10 mov %rax,0x10(%rsp) + 420cc3: 0f 85 f6 fc ff ff jne 4209bf <__malloc_info.part.7+0x8f> + 420cc9: 8b 05 f9 9a 2a 00 mov 0x2a9af9(%rip),%eax # 6ca7c8 + 420ccf: ff 74 24 20 pushq 0x20(%rsp) + 420cd3: 48 89 df mov %rbx,%rdi + 420cd6: ff 74 24 20 pushq 0x20(%rsp) + 420cda: ff 74 24 60 pushq 0x60(%rsp) + 420cde: be d8 2c 4a 00 mov $0x4a2cd8,%esi + 420ce3: ff 74 24 60 pushq 0x60(%rsp) + 420ce7: ff 35 eb 9a 2a 00 pushq 0x2a9aeb(%rip) # 6ca7d8 + 420ced: 50 push %rax + 420cee: 4c 8b 4c 24 70 mov 0x70(%rsp),%r9 + 420cf3: 31 c0 xor %eax,%eax + 420cf5: 4c 8b 44 24 68 mov 0x68(%rsp),%r8 + 420cfa: 48 8b 4c 24 60 mov 0x60(%rsp),%rcx + 420cff: 48 8b 54 24 58 mov 0x58(%rsp),%rdx + 420d04: e8 97 b6 03 00 callq 45c3a0 <__fprintf> + 420d09: 48 81 c4 c8 11 00 00 add $0x11c8,%rsp + 420d10: 31 c0 xor %eax,%eax + 420d12: 5b pop %rbx + 420d13: 5d pop %rbp + 420d14: 41 5c pop %r12 + 420d16: 41 5d pop %r13 + 420d18: 41 5e pop %r14 + 420d1a: 41 5f pop %r15 + 420d1c: c3 retq + 420d1d: 0f 1f 00 nopl (%rax) + 420d20: 49 c7 02 00 00 00 00 movq $0x0,(%r10) + 420d27: 31 ff xor %edi,%edi + 420d29: e9 23 fe ff ff jmpq 420b51 <__malloc_info.part.7+0x221> + 420d2e: 48 c7 41 10 00 00 00 movq $0x0,0x10(%rcx) + 420d35: 00 + 420d36: 48 c7 01 00 00 00 00 movq $0x0,(%rcx) + 420d3d: 31 d2 xor %edx,%edx + 420d3f: 48 c7 41 f8 00 00 00 movq $0x0,-0x8(%rcx) + 420d46: 00 + 420d47: e9 1d fd ff ff jmpq 420a69 <__malloc_info.part.7+0x139> + 420d4c: 4c 8b 84 24 c0 01 00 mov 0x1c0(%rsp),%r8 + 420d53: 00 + 420d54: 48 8b 8c 24 b8 01 00 mov 0x1b8(%rsp),%rcx + 420d5b: 00 + 420d5c: be a8 2b 4a 00 mov $0x4a2ba8,%esi + 420d61: 48 8b 94 24 b0 01 00 mov 0x1b0(%rsp),%rdx + 420d68: 00 + 420d69: 48 89 df mov %rbx,%rdi + 420d6c: 31 c0 xor %eax,%eax + 420d6e: e8 2d b6 03 00 callq 45c3a0 <__fprintf> + 420d73: e9 9c fe ff ff jmpq 420c14 <__malloc_info.part.7+0x2e4> + 420d78: 48 8b 15 01 a3 2a 00 mov 0x2aa301(%rip),%rdx # 6cb080 + 420d7f: be 90 2c 4a 00 mov $0x4a2c90,%esi + 420d84: 48 89 df mov %rbx,%rdi + 420d87: 31 c0 xor %eax,%eax + 420d89: 48 89 d1 mov %rdx,%rcx + 420d8c: e8 0f b6 03 00 callq 45c3a0 <__fprintf> + 420d91: 48 8b 05 e8 a2 2a 00 mov 0x2aa2e8(%rip),%rax # 6cb080 + 420d98: 48 01 44 24 18 add %rax,0x18(%rsp) + 420d9d: 48 01 44 24 20 add %rax,0x20(%rsp) + 420da2: e9 f4 fe ff ff jmpq 420c9b <__malloc_info.part.7+0x36b> + 420da7: e8 44 df ff ff callq 41ecf0 + 420dac: e9 a1 fb ff ff jmpq 420952 <__malloc_info.part.7+0x22> + 420db1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 420db6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 420dbd: 00 00 00 + +0000000000420dc0 <__posix_memalign>: + 420dc0: 40 f6 c6 07 test $0x7,%sil + 420dc4: b8 16 00 00 00 mov $0x16,%eax + 420dc9: 74 05 je 420dd0 <__posix_memalign+0x10> + 420dcb: c3 retq + 420dcc: 0f 1f 40 00 nopl 0x0(%rax) + 420dd0: 48 89 f0 mov %rsi,%rax + 420dd3: 48 c1 e8 03 shr $0x3,%rax + 420dd7: 48 8d 48 ff lea -0x1(%rax),%rcx + 420ddb: 48 85 c1 test %rax,%rcx + 420dde: 0f 85 7c 01 00 00 jne 420f60 <__posix_memalign+0x1a0> + 420de4: 48 85 f6 test %rsi,%rsi + 420de7: 0f 84 73 01 00 00 je 420f60 <__posix_memalign+0x1a0> + 420ded: 41 55 push %r13 + 420def: 41 54 push %r12 + 420df1: 48 89 f0 mov %rsi,%rax + 420df4: 55 push %rbp + 420df5: 53 push %rbx + 420df6: 48 89 fd mov %rdi,%rbp + 420df9: 48 89 d3 mov %rdx,%rbx + 420dfc: 48 83 ec 08 sub $0x8,%rsp + 420e00: 48 8b 0d 71 99 2a 00 mov 0x2a9971(%rip),%rcx # 6ca778 <__memalign_hook> + 420e07: 48 85 c9 test %rcx,%rcx + 420e0a: 48 8b 54 24 28 mov 0x28(%rsp),%rdx + 420e0f: 0f 85 51 01 00 00 jne 420f66 <__posix_memalign+0x1a6> + 420e15: 48 83 fe 10 cmp $0x10,%rsi + 420e19: 0f 86 b9 01 00 00 jbe 420fd8 <__posix_memalign+0x218> + 420e1f: 48 83 fe 1f cmp $0x1f,%rsi + 420e23: 0f 86 51 01 00 00 jbe 420f7a <__posix_memalign+0x1ba> + 420e29: 48 ba 00 00 00 00 00 movabs $0x8000000000000000,%rdx + 420e30: 00 00 80 + 420e33: 48 39 d6 cmp %rdx,%rsi + 420e36: 0f 87 c8 01 00 00 ja 421004 <__posix_memalign+0x244> + 420e3c: 48 c7 c2 df ff ff ff mov $0xffffffffffffffdf,%rdx + 420e43: 48 29 f2 sub %rsi,%rdx + 420e46: 48 39 d3 cmp %rdx,%rbx + 420e49: 0f 87 c8 01 00 00 ja 421017 <__posix_memalign+0x257> + 420e4f: 48 8d 56 ff lea -0x1(%rsi),%rdx + 420e53: 48 85 f2 test %rsi,%rdx + 420e56: 0f 84 e7 01 00 00 je 421043 <__posix_memalign+0x283> + 420e5c: 48 83 fe 20 cmp $0x20,%rsi + 420e60: 41 bc 20 00 00 00 mov $0x20,%r12d + 420e66: 74 10 je 420e78 <__posix_memalign+0xb8> + 420e68: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 420e6f: 00 + 420e70: 4d 01 e4 add %r12,%r12 + 420e73: 4c 39 e0 cmp %r12,%rax + 420e76: 77 f8 ja 420e70 <__posix_memalign+0xb0> + 420e78: 48 c7 c0 d8 ff ff ff mov $0xffffffffffffffd8,%rax + 420e7f: 64 4c 8b 28 mov %fs:(%rax),%r13 + 420e83: 4d 85 ed test %r13,%r13 + 420e86: 0f 84 03 01 00 00 je 420f8f <__posix_memalign+0x1cf> + 420e8c: 41 8b 45 04 mov 0x4(%r13),%eax + 420e90: 83 e0 04 and $0x4,%eax + 420e93: 0f 85 f6 00 00 00 jne 420f8f <__posix_memalign+0x1cf> + 420e99: be 01 00 00 00 mov $0x1,%esi + 420e9e: 83 3d 17 c3 2a 00 00 cmpl $0x0,0x2ac317(%rip) # 6cd1bc <__libc_multiple_threads> + 420ea5: 74 0a je 420eb1 <__posix_memalign+0xf1> + 420ea7: f0 41 0f b1 75 00 lock cmpxchg %esi,0x0(%r13) + 420ead: 75 09 jne 420eb8 <__posix_memalign+0xf8> + 420eaf: eb 1e jmp 420ecf <__posix_memalign+0x10f> + 420eb1: 41 0f b1 75 00 cmpxchg %esi,0x0(%r13) + 420eb6: 74 17 je 420ecf <__posix_memalign+0x10f> + 420eb8: 49 8d 7d 00 lea 0x0(%r13),%rdi + 420ebc: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 420ec3: e8 08 17 02 00 callq 4425d0 <__lll_lock_wait_private> + 420ec8: 48 81 c4 80 00 00 00 add $0x80,%rsp + 420ecf: 48 89 da mov %rbx,%rdx + 420ed2: 4c 89 e6 mov %r12,%rsi + 420ed5: 4c 89 ef mov %r13,%rdi + 420ed8: e8 33 b6 ff ff callq 41c510 <_int_memalign> + 420edd: 48 85 c0 test %rax,%rax + 420ee0: 48 89 c2 mov %rax,%rdx + 420ee3: 0f 84 f9 00 00 00 je 420fe2 <__posix_memalign+0x222> + 420ee9: 83 3d cc c2 2a 00 00 cmpl $0x0,0x2ac2cc(%rip) # 6cd1bc <__libc_multiple_threads> + 420ef0: 74 09 je 420efb <__posix_memalign+0x13b> + 420ef2: f0 41 ff 4d 00 lock decl 0x0(%r13) + 420ef7: 75 08 jne 420f01 <__posix_memalign+0x141> + 420ef9: eb 1d jmp 420f18 <__posix_memalign+0x158> + 420efb: 41 ff 4d 00 decl 0x0(%r13) + 420eff: 74 17 je 420f18 <__posix_memalign+0x158> + 420f01: 49 8d 7d 00 lea 0x0(%r13),%rdi + 420f05: 48 81 ec 80 00 00 00 sub $0x80,%rsp + 420f0c: e8 ef 16 02 00 callq 442600 <__lll_unlock_wake_private> + 420f11: 48 81 c4 80 00 00 00 add $0x80,%rsp + 420f18: 48 85 d2 test %rdx,%rdx + 420f1b: 74 56 je 420f73 <__posix_memalign+0x1b3> + 420f1d: 48 8b 42 f8 mov -0x8(%rdx),%rax + 420f21: a8 02 test $0x2,%al + 420f23: 75 1f jne 420f44 <__posix_memalign+0x184> + 420f25: a8 04 test $0x4,%al + 420f27: b9 00 a8 6c 00 mov $0x6ca800,%ecx + 420f2c: 74 0d je 420f3b <__posix_memalign+0x17b> + 420f2e: 48 8d 42 f0 lea -0x10(%rdx),%rax + 420f32: 48 25 00 00 00 fc and $0xfffffffffc000000,%rax + 420f38: 48 8b 08 mov (%rax),%rcx + 420f3b: 4c 39 e9 cmp %r13,%rcx + 420f3e: 0f 85 e6 00 00 00 jne 42102a <__posix_memalign+0x26a> + 420f44: 48 89 d0 mov %rdx,%rax + 420f47: 48 89 45 00 mov %rax,0x0(%rbp) + 420f4b: 31 c0 xor %eax,%eax + 420f4d: 48 83 c4 08 add $0x8,%rsp + 420f51: 5b pop %rbx + 420f52: 5d pop %rbp + 420f53: 41 5c pop %r12 + 420f55: 41 5d pop %r13 + 420f57: c3 retq + 420f58: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 420f5f: 00 + 420f60: b8 16 00 00 00 mov $0x16,%eax + 420f65: c3 retq + 420f66: 48 89 de mov %rbx,%rsi + 420f69: 48 89 c7 mov %rax,%rdi + 420f6c: ff d1 callq *%rcx + 420f6e: 48 85 c0 test %rax,%rax + 420f71: 75 d4 jne 420f47 <__posix_memalign+0x187> + 420f73: b8 0c 00 00 00 mov $0xc,%eax + 420f78: eb d3 jmp 420f4d <__posix_memalign+0x18d> + 420f7a: 48 83 fb bf cmp $0xffffffffffffffbf,%rbx + 420f7e: 0f 87 93 00 00 00 ja 421017 <__posix_memalign+0x257> + 420f84: 41 bc 20 00 00 00 mov $0x20,%r12d + 420f8a: e9 e9 fe ff ff jmpq 420e78 <__posix_memalign+0xb8> + 420f8f: e8 cc 61 ff ff callq 417160 + 420f94: 48 85 c0 test %rax,%rax + 420f97: 49 89 c5 mov %rax,%r13 + 420f9a: 0f 85 2f ff ff ff jne 420ecf <__posix_memalign+0x10f> + 420fa0: 49 8d 7c 1c 20 lea 0x20(%r12,%rbx,1),%rdi + 420fa5: 31 f6 xor %esi,%esi + 420fa7: e8 a4 64 ff ff callq 417450 + 420fac: 48 89 da mov %rbx,%rdx + 420faf: 4c 89 e6 mov %r12,%rsi + 420fb2: 48 89 c7 mov %rax,%rdi + 420fb5: 49 89 c5 mov %rax,%r13 + 420fb8: e8 53 b5 ff ff callq 41c510 <_int_memalign> + 420fbd: 48 85 c0 test %rax,%rax + 420fc0: 48 89 c2 mov %rax,%rdx + 420fc3: 75 05 jne 420fca <__posix_memalign+0x20a> + 420fc5: 4d 85 ed test %r13,%r13 + 420fc8: 75 18 jne 420fe2 <__posix_memalign+0x222> + 420fca: 4d 85 ed test %r13,%r13 + 420fcd: 0f 85 16 ff ff ff jne 420ee9 <__posix_memalign+0x129> + 420fd3: e9 40 ff ff ff jmpq 420f18 <__posix_memalign+0x158> + 420fd8: 48 89 df mov %rbx,%rdi + 420fdb: e8 30 ca ff ff callq 41da10 <__libc_malloc> + 420fe0: eb 8c jmp 420f6e <__posix_memalign+0x1ae> + 420fe2: 90 nop + 420fe3: 4c 89 ef mov %r13,%rdi + 420fe6: 48 89 de mov %rbx,%rsi + 420fe9: e8 02 6a ff ff callq 4179f0 + 420fee: 48 89 da mov %rbx,%rdx + 420ff1: 4c 89 e6 mov %r12,%rsi + 420ff4: 48 89 c7 mov %rax,%rdi + 420ff7: 49 89 c5 mov %rax,%r13 + 420ffa: e8 11 b5 ff ff callq 41c510 <_int_memalign> + 420fff: 48 89 c2 mov %rax,%rdx + 421002: eb c6 jmp 420fca <__posix_memalign+0x20a> + 421004: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 42100b: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) + 421012: e9 5c ff ff ff jmpq 420f73 <__posix_memalign+0x1b3> + 421017: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 42101e: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) + 421025: e9 49 ff ff ff jmpq 420f73 <__posix_memalign+0x1b3> + 42102a: b9 08 2e 4a 00 mov $0x4a2e08,%ecx + 42102f: ba 3c 0c 00 00 mov $0xc3c,%edx + 421034: be c8 1f 4a 00 mov $0x4a1fc8,%esi + 421039: bf 20 2a 4a 00 mov $0x4a2a20,%edi + 42103e: e8 dd 5d ff ff callq 416e20 <__malloc_assert> + 421043: 49 89 f4 mov %rsi,%r12 + 421046: e9 2d fe ff ff jmpq 420e78 <__posix_memalign+0xb8> + 42104b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + +0000000000421050 <__malloc_info>: + 421050: 85 ff test %edi,%edi + 421052: 74 0c je 421060 <__malloc_info+0x10> + 421054: b8 16 00 00 00 mov $0x16,%eax + 421059: c3 retq + 42105a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 421060: 48 89 f7 mov %rsi,%rdi + 421063: e9 c8 f8 ff ff jmpq 420930 <__malloc_info.part.7> + 421068: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 42106f: 00 + +0000000000421070 <__default_morecore>: + 421070: 48 83 ec 08 sub $0x8,%rsp + 421074: e8 77 ea 01 00 callq 43faf0 <__sbrk> + 421079: ba 00 00 00 00 mov $0x0,%edx + 42107e: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 421082: 48 0f 44 c2 cmove %rdx,%rax + 421086: 48 83 c4 08 add $0x8,%rsp + 42108a: c3 retq + 42108b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + +0000000000421090 : + 421090: 48 8d 05 19 00 00 00 lea 0x19(%rip),%rax # 4210b0 <__GI_strchr> + 421097: f7 05 1f b6 2a 00 04 testl $0x4,0x2ab61f(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> + 42109e: 00 00 00 + 4210a1: 74 07 je 4210aa + 4210a3: 48 8d 05 66 a9 01 00 lea 0x1a966(%rip),%rax # 43ba10 <__strchr_sse2_no_bsf> + 4210aa: c3 retq + 4210ab: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + +00000000004210b0 <__GI_strchr>: + 4210b0: 66 0f 6e ce movd %esi,%xmm1 + 4210b4: 89 f8 mov %edi,%eax + 4210b6: 25 ff 0f 00 00 and $0xfff,%eax + 4210bb: 66 0f 60 c9 punpcklbw %xmm1,%xmm1 + 4210bf: 3d c0 0f 00 00 cmp $0xfc0,%eax + 4210c4: 66 0f 61 c9 punpcklwd %xmm1,%xmm1 + 4210c8: 66 0f 70 c9 00 pshufd $0x0,%xmm1,%xmm1 + 4210cd: 0f 8f 5d 01 00 00 jg 421230 <__GI_strchr+0x180> + 4210d3: f3 0f 6f 07 movdqu (%rdi),%xmm0 + 4210d7: 66 0f ef db pxor %xmm3,%xmm3 + 4210db: 66 0f 6f e0 movdqa %xmm0,%xmm4 + 4210df: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4210e3: 66 0f 74 e3 pcmpeqb %xmm3,%xmm4 + 4210e7: 66 0f eb c4 por %xmm4,%xmm0 + 4210eb: 66 0f d7 c0 pmovmskb %xmm0,%eax + 4210ef: 85 c0 test %eax,%eax + 4210f1: 74 15 je 421108 <__GI_strchr+0x58> + 4210f3: 0f bc c0 bsf %eax,%eax + 4210f6: ba 00 00 00 00 mov $0x0,%edx + 4210fb: 48 8d 04 07 lea (%rdi,%rax,1),%rax + 4210ff: 40 38 30 cmp %sil,(%rax) + 421102: 48 0f 45 c2 cmovne %rdx,%rax + 421106: c3 retq + 421107: 90 nop + 421108: f3 0f 6f 47 10 movdqu 0x10(%rdi),%xmm0 + 42110d: 66 0f 6f e0 movdqa %xmm0,%xmm4 + 421111: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 421115: 66 0f 74 e3 pcmpeqb %xmm3,%xmm4 + 421119: 66 0f eb c4 por %xmm4,%xmm0 + 42111d: 66 0f d7 c8 pmovmskb %xmm0,%ecx + 421121: f3 0f 6f 47 20 movdqu 0x20(%rdi),%xmm0 + 421126: 66 0f 6f e0 movdqa %xmm0,%xmm4 + 42112a: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42112e: 48 c1 e1 10 shl $0x10,%rcx + 421132: 66 0f 74 e3 pcmpeqb %xmm3,%xmm4 + 421136: 66 0f eb c4 por %xmm4,%xmm0 + 42113a: 66 0f d7 c0 pmovmskb %xmm0,%eax + 42113e: f3 0f 6f 47 30 movdqu 0x30(%rdi),%xmm0 + 421143: 66 0f 74 d8 pcmpeqb %xmm0,%xmm3 + 421147: 48 c1 e0 20 shl $0x20,%rax + 42114b: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42114f: 48 09 c8 or %rcx,%rax + 421152: 66 0f eb c3 por %xmm3,%xmm0 + 421156: 66 0f d7 c8 pmovmskb %xmm0,%ecx + 42115a: 48 c1 e1 30 shl $0x30,%rcx + 42115e: 48 09 c8 or %rcx,%rax + 421161: 48 85 c0 test %rax,%rax + 421164: 0f 85 a6 00 00 00 jne 421210 <__GI_strchr+0x160> + 42116a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 421170: 66 0f ef f6 pxor %xmm6,%xmm6 + 421174: 48 83 e7 c0 and $0xffffffffffffffc0,%rdi + 421178: 48 83 c7 40 add $0x40,%rdi + 42117c: 66 0f 6f 2f movdqa (%rdi),%xmm5 + 421180: 66 0f 6f 57 10 movdqa 0x10(%rdi),%xmm2 + 421185: 66 0f 6f 5f 20 movdqa 0x20(%rdi),%xmm3 + 42118a: 66 0f ef e9 pxor %xmm1,%xmm5 + 42118e: 66 0f 6f 67 30 movdqa 0x30(%rdi),%xmm4 + 421193: 66 0f ef d1 pxor %xmm1,%xmm2 + 421197: 66 0f ef d9 pxor %xmm1,%xmm3 + 42119b: 66 0f da 2f pminub (%rdi),%xmm5 + 42119f: 66 0f ef e1 pxor %xmm1,%xmm4 + 4211a3: 66 0f da 57 10 pminub 0x10(%rdi),%xmm2 + 4211a8: 66 0f da 5f 20 pminub 0x20(%rdi),%xmm3 + 4211ad: 66 0f da ea pminub %xmm2,%xmm5 + 4211b1: 66 0f da 67 30 pminub 0x30(%rdi),%xmm4 + 4211b6: 66 0f da eb pminub %xmm3,%xmm5 + 4211ba: 66 0f da ec pminub %xmm4,%xmm5 + 4211be: 66 0f 74 ee pcmpeqb %xmm6,%xmm5 + 4211c2: 66 0f d7 c5 pmovmskb %xmm5,%eax + 4211c6: 85 c0 test %eax,%eax + 4211c8: 74 ae je 421178 <__GI_strchr+0xc8> + 4211ca: 66 0f 6f 2f movdqa (%rdi),%xmm5 + 4211ce: 66 0f 6f c5 movdqa %xmm5,%xmm0 + 4211d2: 66 0f 74 e9 pcmpeqb %xmm1,%xmm5 + 4211d6: 66 0f 74 c6 pcmpeqb %xmm6,%xmm0 + 4211da: 66 0f eb e8 por %xmm0,%xmm5 + 4211de: 66 0f 74 d6 pcmpeqb %xmm6,%xmm2 + 4211e2: 66 0f 74 de pcmpeqb %xmm6,%xmm3 + 4211e6: 66 0f 74 e6 pcmpeqb %xmm6,%xmm4 + 4211ea: 66 0f d7 cd pmovmskb %xmm5,%ecx + 4211ee: 66 0f d7 c2 pmovmskb %xmm2,%eax + 4211f2: 48 c1 e0 10 shl $0x10,%rax + 4211f6: 66 44 0f d7 c3 pmovmskb %xmm3,%r8d + 4211fb: 66 0f d7 d4 pmovmskb %xmm4,%edx + 4211ff: 49 c1 e0 20 shl $0x20,%r8 + 421203: 4c 09 c0 or %r8,%rax + 421206: 48 09 c8 or %rcx,%rax + 421209: 48 c1 e2 30 shl $0x30,%rdx + 42120d: 48 09 d0 or %rdx,%rax + 421210: 48 0f bc c0 bsf %rax,%rax + 421214: ba 00 00 00 00 mov $0x0,%edx + 421219: 48 8d 04 07 lea (%rdi,%rax,1),%rax + 42121d: 40 38 30 cmp %sil,(%rax) + 421220: 48 0f 45 c2 cmovne %rdx,%rax + 421224: c3 retq + 421225: 90 nop + 421226: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42122d: 00 00 00 + 421230: 48 89 fa mov %rdi,%rdx + 421233: 66 0f ef d2 pxor %xmm2,%xmm2 + 421237: 48 83 e2 c0 and $0xffffffffffffffc0,%rdx + 42123b: 66 0f 6f c1 movdqa %xmm1,%xmm0 + 42123f: 66 0f 6f 1a movdqa (%rdx),%xmm3 + 421243: 66 0f 6f e3 movdqa %xmm3,%xmm4 + 421247: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 + 42124b: 66 0f 74 e2 pcmpeqb %xmm2,%xmm4 + 42124f: 66 0f eb dc por %xmm4,%xmm3 + 421253: 66 44 0f d7 c3 pmovmskb %xmm3,%r8d + 421258: 66 0f 6f 5a 10 movdqa 0x10(%rdx),%xmm3 + 42125d: 66 0f 6f e3 movdqa %xmm3,%xmm4 + 421261: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 + 421265: 66 0f 74 e2 pcmpeqb %xmm2,%xmm4 + 421269: 66 0f eb dc por %xmm4,%xmm3 + 42126d: 66 0f d7 c3 pmovmskb %xmm3,%eax + 421271: 66 0f 6f 5a 20 movdqa 0x20(%rdx),%xmm3 + 421276: 66 0f 6f e3 movdqa %xmm3,%xmm4 + 42127a: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 + 42127e: 48 c1 e0 10 shl $0x10,%rax + 421282: 66 0f 74 e2 pcmpeqb %xmm2,%xmm4 + 421286: 66 0f eb dc por %xmm4,%xmm3 + 42128a: 66 44 0f d7 cb pmovmskb %xmm3,%r9d + 42128f: 66 0f 6f 5a 30 movdqa 0x30(%rdx),%xmm3 + 421294: 66 0f 74 d3 pcmpeqb %xmm3,%xmm2 + 421298: 49 c1 e1 20 shl $0x20,%r9 + 42129c: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 4212a0: 4c 09 c8 or %r9,%rax + 4212a3: 4c 09 c0 or %r8,%rax + 4212a6: 66 0f eb c2 por %xmm2,%xmm0 + 4212aa: 66 0f d7 c8 pmovmskb %xmm0,%ecx + 4212ae: 48 c1 e1 30 shl $0x30,%rcx + 4212b2: 48 09 c8 or %rcx,%rax + 4212b5: 89 f9 mov %edi,%ecx + 4212b7: 28 d1 sub %dl,%cl + 4212b9: 48 d3 e8 shr %cl,%rax + 4212bc: 48 85 c0 test %rax,%rax + 4212bf: 0f 85 4b ff ff ff jne 421210 <__GI_strchr+0x160> + 4212c5: e9 a0 fe ff ff jmpq 42116a <__GI_strchr+0xba> + 4212ca: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + +00000000004212d0 : + 4212d0: 48 8d 05 79 cd 00 00 lea 0xcd79(%rip),%rax # 42e050 <__strcmp_sse2_unaligned> + 4212d7: f7 05 df b3 2a 00 10 testl $0x10,0x2ab3df(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> + 4212de: 00 00 00 + 4212e1: 75 1a jne 4212fd + 4212e3: 48 8d 05 06 bb 00 00 lea 0xbb06(%rip),%rax # 42cdf0 <__strcmp_ssse3> + 4212ea: f7 05 9c b3 2a 00 00 testl $0x200,0x2ab39c(%rip) # 6cc690 <_dl_x86_cpu_features+0x10> + 4212f1: 02 00 00 + 4212f4: 75 07 jne 4212fd + 4212f6: 48 8d 05 03 00 00 00 lea 0x3(%rip),%rax # 421300 <__GI_strcmp> + 4212fd: c3 retq + 4212fe: 66 90 xchg %ax,%ax + +0000000000421300 <__GI_strcmp>: + 421300: 89 f1 mov %esi,%ecx + 421302: 89 f8 mov %edi,%eax + 421304: 48 83 e1 3f and $0x3f,%rcx + 421308: 48 83 e0 3f and $0x3f,%rax + 42130c: 83 f9 30 cmp $0x30,%ecx + 42130f: 77 3f ja 421350 <__GI_strcmp+0x50> + 421311: 83 f8 30 cmp $0x30,%eax + 421314: 77 3a ja 421350 <__GI_strcmp+0x50> + 421316: 66 0f 12 0f movlpd (%rdi),%xmm1 + 42131a: 66 0f 12 16 movlpd (%rsi),%xmm2 + 42131e: 66 0f 16 4f 08 movhpd 0x8(%rdi),%xmm1 + 421323: 66 0f 16 56 08 movhpd 0x8(%rsi),%xmm2 + 421328: 66 0f ef c0 pxor %xmm0,%xmm0 + 42132c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 421330: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 421334: 66 0f f8 c8 psubb %xmm0,%xmm1 + 421338: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42133c: 81 ea ff ff 00 00 sub $0xffff,%edx + 421342: 0f 85 c8 13 00 00 jne 422710 <__GI_strcmp+0x1410> + 421348: 48 83 c6 10 add $0x10,%rsi + 42134c: 48 83 c7 10 add $0x10,%rdi + 421350: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi + 421354: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi + 421358: ba ff ff 00 00 mov $0xffff,%edx + 42135d: 45 31 c0 xor %r8d,%r8d + 421360: 83 e1 0f and $0xf,%ecx + 421363: 83 e0 0f and $0xf,%eax + 421366: 39 c1 cmp %eax,%ecx + 421368: 74 26 je 421390 <__GI_strcmp+0x90> + 42136a: 77 07 ja 421373 <__GI_strcmp+0x73> + 42136c: 41 89 d0 mov %edx,%r8d + 42136f: 91 xchg %eax,%ecx + 421370: 48 87 f7 xchg %rsi,%rdi + 421373: 4c 8d 48 0f lea 0xf(%rax),%r9 + 421377: 49 29 c9 sub %rcx,%r9 + 42137a: 4c 8d 15 af 1c 08 00 lea 0x81caf(%rip),%r10 # 4a3030 <__func__.10972+0x70> + 421381: 4f 63 0c 8a movslq (%r10,%r9,4),%r9 + 421385: 4f 8d 14 0a lea (%r10,%r9,1),%r10 + 421389: 41 ff e2 jmpq *%r10 + 42138c: 0f 1f 40 00 nopl 0x0(%rax) + 421390: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 421394: 66 0f ef c0 pxor %xmm0,%xmm0 + 421398: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42139c: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 + 4213a0: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4213a4: 66 44 0f d7 c9 pmovmskb %xmm1,%r9d + 4213a9: d3 ea shr %cl,%edx + 4213ab: 41 d3 e9 shr %cl,%r9d + 4213ae: 44 29 ca sub %r9d,%edx + 4213b1: 0f 85 3e 13 00 00 jne 4226f5 <__GI_strcmp+0x13f5> + 4213b7: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 4213be: 49 c7 c1 10 00 00 00 mov $0x10,%r9 + 4213c5: 66 0f ef c0 pxor %xmm0,%xmm0 + 4213c9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4213d0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4213d5: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4213da: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4213de: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 4213e2: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4213e6: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4213ea: 81 ea ff ff 00 00 sub $0xffff,%edx + 4213f0: 0f 85 fa 12 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 4213f6: 48 83 c1 10 add $0x10,%rcx + 4213fa: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4213ff: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 421404: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 421408: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42140c: 66 0f f8 c8 psubb %xmm0,%xmm1 + 421410: 66 0f d7 d1 pmovmskb %xmm1,%edx + 421414: 81 ea ff ff 00 00 sub $0xffff,%edx + 42141a: 0f 85 d0 12 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 421420: 48 83 c1 10 add $0x10,%rcx + 421424: eb aa jmp 4213d0 <__GI_strcmp+0xd0> + 421426: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42142d: 00 00 00 + 421430: 66 0f ef c0 pxor %xmm0,%xmm0 + 421434: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 421438: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42143c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 421440: 66 0f 73 fa 0f pslldq $0xf,%xmm2 + 421445: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 421449: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42144d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 421452: d3 ea shr %cl,%edx + 421454: 41 d3 e9 shr %cl,%r9d + 421457: 44 29 ca sub %r9d,%edx + 42145a: 0f 85 95 12 00 00 jne 4226f5 <__GI_strcmp+0x13f5> + 421460: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 421464: 66 0f ef c0 pxor %xmm0,%xmm0 + 421468: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42146f: 41 b9 01 00 00 00 mov $0x1,%r9d + 421475: 4c 8d 57 01 lea 0x1(%rdi),%r10 + 421479: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 421480: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 421487: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 42148e: 00 00 + 421490: 49 83 c2 10 add $0x10,%r10 + 421494: 0f 8f 96 00 00 00 jg 421530 <__GI_strcmp+0x230> + 42149a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42149f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4214a4: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 4214a8: 66 0f 73 db 01 psrldq $0x1,%xmm3 + 4214ad: 66 0f 73 fa 0f pslldq $0xf,%xmm2 + 4214b2: 66 0f eb d3 por %xmm3,%xmm2 + 4214b6: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4214ba: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 4214be: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4214c2: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4214c6: 81 ea ff ff 00 00 sub $0xffff,%edx + 4214cc: 0f 85 1e 12 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 4214d2: 48 83 c1 10 add $0x10,%rcx + 4214d6: 66 0f 6f dc movdqa %xmm4,%xmm3 + 4214da: 49 83 c2 10 add $0x10,%r10 + 4214de: 7f 50 jg 421530 <__GI_strcmp+0x230> + 4214e0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4214e5: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4214ea: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 4214ee: 66 0f 73 db 01 psrldq $0x1,%xmm3 + 4214f3: 66 0f 73 fa 0f pslldq $0xf,%xmm2 + 4214f8: 66 0f eb d3 por %xmm3,%xmm2 + 4214fc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 421500: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 421504: 66 0f f8 c8 psubb %xmm0,%xmm1 + 421508: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42150c: 81 ea ff ff 00 00 sub $0xffff,%edx + 421512: 0f 85 d8 11 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 421518: 48 83 c1 10 add $0x10,%rcx + 42151c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 421520: e9 6b ff ff ff jmpq 421490 <__GI_strcmp+0x190> + 421525: 90 nop + 421526: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42152d: 00 00 00 + 421530: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 421534: 66 0f d7 d0 pmovmskb %xmm0,%edx + 421538: f7 c2 fe ff 00 00 test $0xfffe,%edx + 42153e: 75 10 jne 421550 <__GI_strcmp+0x250> + 421540: 66 0f ef c0 pxor %xmm0,%xmm0 + 421544: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42154b: e9 4a ff ff ff jmpq 42149a <__GI_strcmp+0x19a> + 421550: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 421555: 66 0f 73 d8 01 psrldq $0x1,%xmm0 + 42155a: 66 0f 73 db 01 psrldq $0x1,%xmm3 + 42155f: e9 7c 11 00 00 jmpq 4226e0 <__GI_strcmp+0x13e0> + 421564: 66 90 xchg %ax,%ax + 421566: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42156d: 00 00 00 + 421570: 66 0f ef c0 pxor %xmm0,%xmm0 + 421574: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 421578: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42157c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 421580: 66 0f 73 fa 0e pslldq $0xe,%xmm2 + 421585: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 421589: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42158d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 421592: d3 ea shr %cl,%edx + 421594: 41 d3 e9 shr %cl,%r9d + 421597: 44 29 ca sub %r9d,%edx + 42159a: 0f 85 55 11 00 00 jne 4226f5 <__GI_strcmp+0x13f5> + 4215a0: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 4215a4: 66 0f ef c0 pxor %xmm0,%xmm0 + 4215a8: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 4215af: 41 b9 02 00 00 00 mov $0x2,%r9d + 4215b5: 4c 8d 57 02 lea 0x2(%rdi),%r10 + 4215b9: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 4215c0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 4215c7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 4215ce: 00 00 + 4215d0: 49 83 c2 10 add $0x10,%r10 + 4215d4: 0f 8f 96 00 00 00 jg 421670 <__GI_strcmp+0x370> + 4215da: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4215df: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4215e4: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 4215e8: 66 0f 73 db 02 psrldq $0x2,%xmm3 + 4215ed: 66 0f 73 fa 0e pslldq $0xe,%xmm2 + 4215f2: 66 0f eb d3 por %xmm3,%xmm2 + 4215f6: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4215fa: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 4215fe: 66 0f f8 c8 psubb %xmm0,%xmm1 + 421602: 66 0f d7 d1 pmovmskb %xmm1,%edx + 421606: 81 ea ff ff 00 00 sub $0xffff,%edx + 42160c: 0f 85 de 10 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 421612: 48 83 c1 10 add $0x10,%rcx + 421616: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42161a: 49 83 c2 10 add $0x10,%r10 + 42161e: 7f 50 jg 421670 <__GI_strcmp+0x370> + 421620: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 421625: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42162a: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42162e: 66 0f 73 db 02 psrldq $0x2,%xmm3 + 421633: 66 0f 73 fa 0e pslldq $0xe,%xmm2 + 421638: 66 0f eb d3 por %xmm3,%xmm2 + 42163c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 421640: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 421644: 66 0f f8 c8 psubb %xmm0,%xmm1 + 421648: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42164c: 81 ea ff ff 00 00 sub $0xffff,%edx + 421652: 0f 85 98 10 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 421658: 48 83 c1 10 add $0x10,%rcx + 42165c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 421660: e9 6b ff ff ff jmpq 4215d0 <__GI_strcmp+0x2d0> + 421665: 90 nop + 421666: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42166d: 00 00 00 + 421670: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 421674: 66 0f d7 d0 pmovmskb %xmm0,%edx + 421678: f7 c2 fc ff 00 00 test $0xfffc,%edx + 42167e: 75 10 jne 421690 <__GI_strcmp+0x390> + 421680: 66 0f ef c0 pxor %xmm0,%xmm0 + 421684: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42168b: e9 4a ff ff ff jmpq 4215da <__GI_strcmp+0x2da> + 421690: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 421695: 66 0f 73 d8 02 psrldq $0x2,%xmm0 + 42169a: 66 0f 73 db 02 psrldq $0x2,%xmm3 + 42169f: e9 3c 10 00 00 jmpq 4226e0 <__GI_strcmp+0x13e0> + 4216a4: 66 90 xchg %ax,%ax + 4216a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4216ad: 00 00 00 + 4216b0: 66 0f ef c0 pxor %xmm0,%xmm0 + 4216b4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 4216b8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 4216bc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4216c0: 66 0f 73 fa 0d pslldq $0xd,%xmm2 + 4216c5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 4216c9: 66 0f f8 d0 psubb %xmm0,%xmm2 + 4216cd: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 4216d2: d3 ea shr %cl,%edx + 4216d4: 41 d3 e9 shr %cl,%r9d + 4216d7: 44 29 ca sub %r9d,%edx + 4216da: 0f 85 15 10 00 00 jne 4226f5 <__GI_strcmp+0x13f5> + 4216e0: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 4216e4: 66 0f ef c0 pxor %xmm0,%xmm0 + 4216e8: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 4216ef: 41 b9 03 00 00 00 mov $0x3,%r9d + 4216f5: 4c 8d 57 03 lea 0x3(%rdi),%r10 + 4216f9: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 421700: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 421707: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 42170e: 00 00 + 421710: 49 83 c2 10 add $0x10,%r10 + 421714: 0f 8f 96 00 00 00 jg 4217b0 <__GI_strcmp+0x4b0> + 42171a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42171f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 421724: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 421728: 66 0f 73 db 03 psrldq $0x3,%xmm3 + 42172d: 66 0f 73 fa 0d pslldq $0xd,%xmm2 + 421732: 66 0f eb d3 por %xmm3,%xmm2 + 421736: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42173a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42173e: 66 0f f8 c8 psubb %xmm0,%xmm1 + 421742: 66 0f d7 d1 pmovmskb %xmm1,%edx + 421746: 81 ea ff ff 00 00 sub $0xffff,%edx + 42174c: 0f 85 9e 0f 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 421752: 48 83 c1 10 add $0x10,%rcx + 421756: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42175a: 49 83 c2 10 add $0x10,%r10 + 42175e: 7f 50 jg 4217b0 <__GI_strcmp+0x4b0> + 421760: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 421765: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42176a: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42176e: 66 0f 73 db 03 psrldq $0x3,%xmm3 + 421773: 66 0f 73 fa 0d pslldq $0xd,%xmm2 + 421778: 66 0f eb d3 por %xmm3,%xmm2 + 42177c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 421780: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 421784: 66 0f f8 c8 psubb %xmm0,%xmm1 + 421788: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42178c: 81 ea ff ff 00 00 sub $0xffff,%edx + 421792: 0f 85 58 0f 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 421798: 48 83 c1 10 add $0x10,%rcx + 42179c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 4217a0: e9 6b ff ff ff jmpq 421710 <__GI_strcmp+0x410> + 4217a5: 90 nop + 4217a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4217ad: 00 00 00 + 4217b0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 4217b4: 66 0f d7 d0 pmovmskb %xmm0,%edx + 4217b8: f7 c2 f8 ff 00 00 test $0xfff8,%edx + 4217be: 75 10 jne 4217d0 <__GI_strcmp+0x4d0> + 4217c0: 66 0f ef c0 pxor %xmm0,%xmm0 + 4217c4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 4217cb: e9 4a ff ff ff jmpq 42171a <__GI_strcmp+0x41a> + 4217d0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4217d5: 66 0f 73 d8 03 psrldq $0x3,%xmm0 + 4217da: 66 0f 73 db 03 psrldq $0x3,%xmm3 + 4217df: e9 fc 0e 00 00 jmpq 4226e0 <__GI_strcmp+0x13e0> + 4217e4: 66 90 xchg %ax,%ax + 4217e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4217ed: 00 00 00 + 4217f0: 66 0f ef c0 pxor %xmm0,%xmm0 + 4217f4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 4217f8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 4217fc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 421800: 66 0f 73 fa 0c pslldq $0xc,%xmm2 + 421805: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 421809: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42180d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 421812: d3 ea shr %cl,%edx + 421814: 41 d3 e9 shr %cl,%r9d + 421817: 44 29 ca sub %r9d,%edx + 42181a: 0f 85 d5 0e 00 00 jne 4226f5 <__GI_strcmp+0x13f5> + 421820: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 421824: 66 0f ef c0 pxor %xmm0,%xmm0 + 421828: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42182f: 41 b9 04 00 00 00 mov $0x4,%r9d + 421835: 4c 8d 57 04 lea 0x4(%rdi),%r10 + 421839: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 421840: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 421847: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 42184e: 00 00 + 421850: 49 83 c2 10 add $0x10,%r10 + 421854: 0f 8f 96 00 00 00 jg 4218f0 <__GI_strcmp+0x5f0> + 42185a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42185f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 421864: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 421868: 66 0f 73 db 04 psrldq $0x4,%xmm3 + 42186d: 66 0f 73 fa 0c pslldq $0xc,%xmm2 + 421872: 66 0f eb d3 por %xmm3,%xmm2 + 421876: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42187a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42187e: 66 0f f8 c8 psubb %xmm0,%xmm1 + 421882: 66 0f d7 d1 pmovmskb %xmm1,%edx + 421886: 81 ea ff ff 00 00 sub $0xffff,%edx + 42188c: 0f 85 5e 0e 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 421892: 48 83 c1 10 add $0x10,%rcx + 421896: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42189a: 49 83 c2 10 add $0x10,%r10 + 42189e: 7f 50 jg 4218f0 <__GI_strcmp+0x5f0> + 4218a0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4218a5: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4218aa: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 4218ae: 66 0f 73 db 04 psrldq $0x4,%xmm3 + 4218b3: 66 0f 73 fa 0c pslldq $0xc,%xmm2 + 4218b8: 66 0f eb d3 por %xmm3,%xmm2 + 4218bc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4218c0: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 4218c4: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4218c8: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4218cc: 81 ea ff ff 00 00 sub $0xffff,%edx + 4218d2: 0f 85 18 0e 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 4218d8: 48 83 c1 10 add $0x10,%rcx + 4218dc: 66 0f 6f dc movdqa %xmm4,%xmm3 + 4218e0: e9 6b ff ff ff jmpq 421850 <__GI_strcmp+0x550> + 4218e5: 90 nop + 4218e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4218ed: 00 00 00 + 4218f0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 4218f4: 66 0f d7 d0 pmovmskb %xmm0,%edx + 4218f8: f7 c2 f0 ff 00 00 test $0xfff0,%edx + 4218fe: 75 10 jne 421910 <__GI_strcmp+0x610> + 421900: 66 0f ef c0 pxor %xmm0,%xmm0 + 421904: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42190b: e9 4a ff ff ff jmpq 42185a <__GI_strcmp+0x55a> + 421910: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 421915: 66 0f 73 d8 04 psrldq $0x4,%xmm0 + 42191a: 66 0f 73 db 04 psrldq $0x4,%xmm3 + 42191f: e9 bc 0d 00 00 jmpq 4226e0 <__GI_strcmp+0x13e0> + 421924: 66 90 xchg %ax,%ax + 421926: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42192d: 00 00 00 + 421930: 66 0f ef c0 pxor %xmm0,%xmm0 + 421934: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 421938: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42193c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 421940: 66 0f 73 fa 0b pslldq $0xb,%xmm2 + 421945: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 421949: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42194d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 421952: d3 ea shr %cl,%edx + 421954: 41 d3 e9 shr %cl,%r9d + 421957: 44 29 ca sub %r9d,%edx + 42195a: 0f 85 95 0d 00 00 jne 4226f5 <__GI_strcmp+0x13f5> + 421960: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 421964: 66 0f ef c0 pxor %xmm0,%xmm0 + 421968: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42196f: 41 b9 05 00 00 00 mov $0x5,%r9d + 421975: 4c 8d 57 05 lea 0x5(%rdi),%r10 + 421979: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 421980: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 421987: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 42198e: 00 00 + 421990: 49 83 c2 10 add $0x10,%r10 + 421994: 0f 8f 96 00 00 00 jg 421a30 <__GI_strcmp+0x730> + 42199a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42199f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4219a4: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 4219a8: 66 0f 73 db 05 psrldq $0x5,%xmm3 + 4219ad: 66 0f 73 fa 0b pslldq $0xb,%xmm2 + 4219b2: 66 0f eb d3 por %xmm3,%xmm2 + 4219b6: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4219ba: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 4219be: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4219c2: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4219c6: 81 ea ff ff 00 00 sub $0xffff,%edx + 4219cc: 0f 85 1e 0d 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 4219d2: 48 83 c1 10 add $0x10,%rcx + 4219d6: 66 0f 6f dc movdqa %xmm4,%xmm3 + 4219da: 49 83 c2 10 add $0x10,%r10 + 4219de: 7f 50 jg 421a30 <__GI_strcmp+0x730> + 4219e0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4219e5: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4219ea: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 4219ee: 66 0f 73 db 05 psrldq $0x5,%xmm3 + 4219f3: 66 0f 73 fa 0b pslldq $0xb,%xmm2 + 4219f8: 66 0f eb d3 por %xmm3,%xmm2 + 4219fc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 421a00: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 421a04: 66 0f f8 c8 psubb %xmm0,%xmm1 + 421a08: 66 0f d7 d1 pmovmskb %xmm1,%edx + 421a0c: 81 ea ff ff 00 00 sub $0xffff,%edx + 421a12: 0f 85 d8 0c 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 421a18: 48 83 c1 10 add $0x10,%rcx + 421a1c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 421a20: e9 6b ff ff ff jmpq 421990 <__GI_strcmp+0x690> + 421a25: 90 nop + 421a26: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 421a2d: 00 00 00 + 421a30: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 421a34: 66 0f d7 d0 pmovmskb %xmm0,%edx + 421a38: f7 c2 e0 ff 00 00 test $0xffe0,%edx + 421a3e: 75 10 jne 421a50 <__GI_strcmp+0x750> + 421a40: 66 0f ef c0 pxor %xmm0,%xmm0 + 421a44: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 421a4b: e9 4a ff ff ff jmpq 42199a <__GI_strcmp+0x69a> + 421a50: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 421a55: 66 0f 73 d8 05 psrldq $0x5,%xmm0 + 421a5a: 66 0f 73 db 05 psrldq $0x5,%xmm3 + 421a5f: e9 7c 0c 00 00 jmpq 4226e0 <__GI_strcmp+0x13e0> + 421a64: 66 90 xchg %ax,%ax + 421a66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 421a6d: 00 00 00 + 421a70: 66 0f ef c0 pxor %xmm0,%xmm0 + 421a74: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 421a78: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 421a7c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 421a80: 66 0f 73 fa 0a pslldq $0xa,%xmm2 + 421a85: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 421a89: 66 0f f8 d0 psubb %xmm0,%xmm2 + 421a8d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 421a92: d3 ea shr %cl,%edx + 421a94: 41 d3 e9 shr %cl,%r9d + 421a97: 44 29 ca sub %r9d,%edx + 421a9a: 0f 85 55 0c 00 00 jne 4226f5 <__GI_strcmp+0x13f5> + 421aa0: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 421aa4: 66 0f ef c0 pxor %xmm0,%xmm0 + 421aa8: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 421aaf: 41 b9 06 00 00 00 mov $0x6,%r9d + 421ab5: 4c 8d 57 06 lea 0x6(%rdi),%r10 + 421ab9: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 421ac0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 421ac7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 421ace: 00 00 + 421ad0: 49 83 c2 10 add $0x10,%r10 + 421ad4: 0f 8f 96 00 00 00 jg 421b70 <__GI_strcmp+0x870> + 421ada: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 421adf: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 421ae4: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 421ae8: 66 0f 73 db 06 psrldq $0x6,%xmm3 + 421aed: 66 0f 73 fa 0a pslldq $0xa,%xmm2 + 421af2: 66 0f eb d3 por %xmm3,%xmm2 + 421af6: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 421afa: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 421afe: 66 0f f8 c8 psubb %xmm0,%xmm1 + 421b02: 66 0f d7 d1 pmovmskb %xmm1,%edx + 421b06: 81 ea ff ff 00 00 sub $0xffff,%edx + 421b0c: 0f 85 de 0b 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 421b12: 48 83 c1 10 add $0x10,%rcx + 421b16: 66 0f 6f dc movdqa %xmm4,%xmm3 + 421b1a: 49 83 c2 10 add $0x10,%r10 + 421b1e: 7f 50 jg 421b70 <__GI_strcmp+0x870> + 421b20: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 421b25: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 421b2a: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 421b2e: 66 0f 73 db 06 psrldq $0x6,%xmm3 + 421b33: 66 0f 73 fa 0a pslldq $0xa,%xmm2 + 421b38: 66 0f eb d3 por %xmm3,%xmm2 + 421b3c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 421b40: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 421b44: 66 0f f8 c8 psubb %xmm0,%xmm1 + 421b48: 66 0f d7 d1 pmovmskb %xmm1,%edx + 421b4c: 81 ea ff ff 00 00 sub $0xffff,%edx + 421b52: 0f 85 98 0b 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 421b58: 48 83 c1 10 add $0x10,%rcx + 421b5c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 421b60: e9 6b ff ff ff jmpq 421ad0 <__GI_strcmp+0x7d0> + 421b65: 90 nop + 421b66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 421b6d: 00 00 00 + 421b70: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 421b74: 66 0f d7 d0 pmovmskb %xmm0,%edx + 421b78: f7 c2 c0 ff 00 00 test $0xffc0,%edx + 421b7e: 75 10 jne 421b90 <__GI_strcmp+0x890> + 421b80: 66 0f ef c0 pxor %xmm0,%xmm0 + 421b84: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 421b8b: e9 4a ff ff ff jmpq 421ada <__GI_strcmp+0x7da> + 421b90: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 421b95: 66 0f 73 d8 06 psrldq $0x6,%xmm0 + 421b9a: 66 0f 73 db 06 psrldq $0x6,%xmm3 + 421b9f: e9 3c 0b 00 00 jmpq 4226e0 <__GI_strcmp+0x13e0> + 421ba4: 66 90 xchg %ax,%ax + 421ba6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 421bad: 00 00 00 + 421bb0: 66 0f ef c0 pxor %xmm0,%xmm0 + 421bb4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 421bb8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 421bbc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 421bc0: 66 0f 73 fa 09 pslldq $0x9,%xmm2 + 421bc5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 421bc9: 66 0f f8 d0 psubb %xmm0,%xmm2 + 421bcd: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 421bd2: d3 ea shr %cl,%edx + 421bd4: 41 d3 e9 shr %cl,%r9d + 421bd7: 44 29 ca sub %r9d,%edx + 421bda: 0f 85 15 0b 00 00 jne 4226f5 <__GI_strcmp+0x13f5> + 421be0: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 421be4: 66 0f ef c0 pxor %xmm0,%xmm0 + 421be8: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 421bef: 41 b9 07 00 00 00 mov $0x7,%r9d + 421bf5: 4c 8d 57 07 lea 0x7(%rdi),%r10 + 421bf9: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 421c00: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 421c07: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 421c0e: 00 00 + 421c10: 49 83 c2 10 add $0x10,%r10 + 421c14: 0f 8f 96 00 00 00 jg 421cb0 <__GI_strcmp+0x9b0> + 421c1a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 421c1f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 421c24: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 421c28: 66 0f 73 db 07 psrldq $0x7,%xmm3 + 421c2d: 66 0f 73 fa 09 pslldq $0x9,%xmm2 + 421c32: 66 0f eb d3 por %xmm3,%xmm2 + 421c36: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 421c3a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 421c3e: 66 0f f8 c8 psubb %xmm0,%xmm1 + 421c42: 66 0f d7 d1 pmovmskb %xmm1,%edx + 421c46: 81 ea ff ff 00 00 sub $0xffff,%edx + 421c4c: 0f 85 9e 0a 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 421c52: 48 83 c1 10 add $0x10,%rcx + 421c56: 66 0f 6f dc movdqa %xmm4,%xmm3 + 421c5a: 49 83 c2 10 add $0x10,%r10 + 421c5e: 7f 50 jg 421cb0 <__GI_strcmp+0x9b0> + 421c60: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 421c65: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 421c6a: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 421c6e: 66 0f 73 db 07 psrldq $0x7,%xmm3 + 421c73: 66 0f 73 fa 09 pslldq $0x9,%xmm2 + 421c78: 66 0f eb d3 por %xmm3,%xmm2 + 421c7c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 421c80: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 421c84: 66 0f f8 c8 psubb %xmm0,%xmm1 + 421c88: 66 0f d7 d1 pmovmskb %xmm1,%edx + 421c8c: 81 ea ff ff 00 00 sub $0xffff,%edx + 421c92: 0f 85 58 0a 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 421c98: 48 83 c1 10 add $0x10,%rcx + 421c9c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 421ca0: e9 6b ff ff ff jmpq 421c10 <__GI_strcmp+0x910> + 421ca5: 90 nop + 421ca6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 421cad: 00 00 00 + 421cb0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 421cb4: 66 0f d7 d0 pmovmskb %xmm0,%edx + 421cb8: f7 c2 80 ff 00 00 test $0xff80,%edx + 421cbe: 75 10 jne 421cd0 <__GI_strcmp+0x9d0> + 421cc0: 66 0f ef c0 pxor %xmm0,%xmm0 + 421cc4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 421ccb: e9 4a ff ff ff jmpq 421c1a <__GI_strcmp+0x91a> + 421cd0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 421cd5: 66 0f 73 d8 07 psrldq $0x7,%xmm0 + 421cda: 66 0f 73 db 07 psrldq $0x7,%xmm3 + 421cdf: e9 fc 09 00 00 jmpq 4226e0 <__GI_strcmp+0x13e0> + 421ce4: 66 90 xchg %ax,%ax + 421ce6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 421ced: 00 00 00 + 421cf0: 66 0f ef c0 pxor %xmm0,%xmm0 + 421cf4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 421cf8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 421cfc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 421d00: 66 0f 73 fa 08 pslldq $0x8,%xmm2 + 421d05: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 421d09: 66 0f f8 d0 psubb %xmm0,%xmm2 + 421d0d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 421d12: d3 ea shr %cl,%edx + 421d14: 41 d3 e9 shr %cl,%r9d + 421d17: 44 29 ca sub %r9d,%edx + 421d1a: 0f 85 d5 09 00 00 jne 4226f5 <__GI_strcmp+0x13f5> + 421d20: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 421d24: 66 0f ef c0 pxor %xmm0,%xmm0 + 421d28: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 421d2f: 41 b9 08 00 00 00 mov $0x8,%r9d + 421d35: 4c 8d 57 08 lea 0x8(%rdi),%r10 + 421d39: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 421d40: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 421d47: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 421d4e: 00 00 + 421d50: 49 83 c2 10 add $0x10,%r10 + 421d54: 0f 8f 96 00 00 00 jg 421df0 <__GI_strcmp+0xaf0> + 421d5a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 421d5f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 421d64: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 421d68: 66 0f 73 db 08 psrldq $0x8,%xmm3 + 421d6d: 66 0f 73 fa 08 pslldq $0x8,%xmm2 + 421d72: 66 0f eb d3 por %xmm3,%xmm2 + 421d76: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 421d7a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 421d7e: 66 0f f8 c8 psubb %xmm0,%xmm1 + 421d82: 66 0f d7 d1 pmovmskb %xmm1,%edx + 421d86: 81 ea ff ff 00 00 sub $0xffff,%edx + 421d8c: 0f 85 5e 09 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 421d92: 48 83 c1 10 add $0x10,%rcx + 421d96: 66 0f 6f dc movdqa %xmm4,%xmm3 + 421d9a: 49 83 c2 10 add $0x10,%r10 + 421d9e: 7f 50 jg 421df0 <__GI_strcmp+0xaf0> + 421da0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 421da5: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 421daa: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 421dae: 66 0f 73 db 08 psrldq $0x8,%xmm3 + 421db3: 66 0f 73 fa 08 pslldq $0x8,%xmm2 + 421db8: 66 0f eb d3 por %xmm3,%xmm2 + 421dbc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 421dc0: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 421dc4: 66 0f f8 c8 psubb %xmm0,%xmm1 + 421dc8: 66 0f d7 d1 pmovmskb %xmm1,%edx + 421dcc: 81 ea ff ff 00 00 sub $0xffff,%edx + 421dd2: 0f 85 18 09 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 421dd8: 48 83 c1 10 add $0x10,%rcx + 421ddc: 66 0f 6f dc movdqa %xmm4,%xmm3 + 421de0: e9 6b ff ff ff jmpq 421d50 <__GI_strcmp+0xa50> + 421de5: 90 nop + 421de6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 421ded: 00 00 00 + 421df0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 421df4: 66 0f d7 d0 pmovmskb %xmm0,%edx + 421df8: f7 c2 00 ff 00 00 test $0xff00,%edx + 421dfe: 75 10 jne 421e10 <__GI_strcmp+0xb10> + 421e00: 66 0f ef c0 pxor %xmm0,%xmm0 + 421e04: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 421e0b: e9 4a ff ff ff jmpq 421d5a <__GI_strcmp+0xa5a> + 421e10: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 421e15: 66 0f 73 d8 08 psrldq $0x8,%xmm0 + 421e1a: 66 0f 73 db 08 psrldq $0x8,%xmm3 + 421e1f: e9 bc 08 00 00 jmpq 4226e0 <__GI_strcmp+0x13e0> + 421e24: 66 90 xchg %ax,%ax + 421e26: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 421e2d: 00 00 00 + 421e30: 66 0f ef c0 pxor %xmm0,%xmm0 + 421e34: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 421e38: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 421e3c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 421e40: 66 0f 73 fa 07 pslldq $0x7,%xmm2 + 421e45: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 421e49: 66 0f f8 d0 psubb %xmm0,%xmm2 + 421e4d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 421e52: d3 ea shr %cl,%edx + 421e54: 41 d3 e9 shr %cl,%r9d + 421e57: 44 29 ca sub %r9d,%edx + 421e5a: 0f 85 95 08 00 00 jne 4226f5 <__GI_strcmp+0x13f5> + 421e60: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 421e64: 66 0f ef c0 pxor %xmm0,%xmm0 + 421e68: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 421e6f: 41 b9 09 00 00 00 mov $0x9,%r9d + 421e75: 4c 8d 57 09 lea 0x9(%rdi),%r10 + 421e79: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 421e80: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 421e87: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 421e8e: 00 00 + 421e90: 49 83 c2 10 add $0x10,%r10 + 421e94: 0f 8f 96 00 00 00 jg 421f30 <__GI_strcmp+0xc30> + 421e9a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 421e9f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 421ea4: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 421ea8: 66 0f 73 db 09 psrldq $0x9,%xmm3 + 421ead: 66 0f 73 fa 07 pslldq $0x7,%xmm2 + 421eb2: 66 0f eb d3 por %xmm3,%xmm2 + 421eb6: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 421eba: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 421ebe: 66 0f f8 c8 psubb %xmm0,%xmm1 + 421ec2: 66 0f d7 d1 pmovmskb %xmm1,%edx + 421ec6: 81 ea ff ff 00 00 sub $0xffff,%edx + 421ecc: 0f 85 1e 08 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 421ed2: 48 83 c1 10 add $0x10,%rcx + 421ed6: 66 0f 6f dc movdqa %xmm4,%xmm3 + 421eda: 49 83 c2 10 add $0x10,%r10 + 421ede: 7f 50 jg 421f30 <__GI_strcmp+0xc30> + 421ee0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 421ee5: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 421eea: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 421eee: 66 0f 73 db 09 psrldq $0x9,%xmm3 + 421ef3: 66 0f 73 fa 07 pslldq $0x7,%xmm2 + 421ef8: 66 0f eb d3 por %xmm3,%xmm2 + 421efc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 421f00: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 421f04: 66 0f f8 c8 psubb %xmm0,%xmm1 + 421f08: 66 0f d7 d1 pmovmskb %xmm1,%edx + 421f0c: 81 ea ff ff 00 00 sub $0xffff,%edx + 421f12: 0f 85 d8 07 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 421f18: 48 83 c1 10 add $0x10,%rcx + 421f1c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 421f20: e9 6b ff ff ff jmpq 421e90 <__GI_strcmp+0xb90> + 421f25: 90 nop + 421f26: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 421f2d: 00 00 00 + 421f30: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 421f34: 66 0f d7 d0 pmovmskb %xmm0,%edx + 421f38: f7 c2 00 fe 00 00 test $0xfe00,%edx + 421f3e: 75 10 jne 421f50 <__GI_strcmp+0xc50> + 421f40: 66 0f ef c0 pxor %xmm0,%xmm0 + 421f44: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 421f4b: e9 4a ff ff ff jmpq 421e9a <__GI_strcmp+0xb9a> + 421f50: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 421f55: 66 0f 73 d8 09 psrldq $0x9,%xmm0 + 421f5a: 66 0f 73 db 09 psrldq $0x9,%xmm3 + 421f5f: e9 7c 07 00 00 jmpq 4226e0 <__GI_strcmp+0x13e0> + 421f64: 66 90 xchg %ax,%ax + 421f66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 421f6d: 00 00 00 + 421f70: 66 0f ef c0 pxor %xmm0,%xmm0 + 421f74: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 421f78: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 421f7c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 421f80: 66 0f 73 fa 06 pslldq $0x6,%xmm2 + 421f85: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 421f89: 66 0f f8 d0 psubb %xmm0,%xmm2 + 421f8d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 421f92: d3 ea shr %cl,%edx + 421f94: 41 d3 e9 shr %cl,%r9d + 421f97: 44 29 ca sub %r9d,%edx + 421f9a: 0f 85 55 07 00 00 jne 4226f5 <__GI_strcmp+0x13f5> + 421fa0: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 421fa4: 66 0f ef c0 pxor %xmm0,%xmm0 + 421fa8: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 421faf: 41 b9 0a 00 00 00 mov $0xa,%r9d + 421fb5: 4c 8d 57 0a lea 0xa(%rdi),%r10 + 421fb9: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 421fc0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 421fc7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 421fce: 00 00 + 421fd0: 49 83 c2 10 add $0x10,%r10 + 421fd4: 0f 8f 96 00 00 00 jg 422070 <__GI_strcmp+0xd70> + 421fda: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 421fdf: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 421fe4: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 421fe8: 66 0f 73 db 0a psrldq $0xa,%xmm3 + 421fed: 66 0f 73 fa 06 pslldq $0x6,%xmm2 + 421ff2: 66 0f eb d3 por %xmm3,%xmm2 + 421ff6: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 421ffa: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 421ffe: 66 0f f8 c8 psubb %xmm0,%xmm1 + 422002: 66 0f d7 d1 pmovmskb %xmm1,%edx + 422006: 81 ea ff ff 00 00 sub $0xffff,%edx + 42200c: 0f 85 de 06 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 422012: 48 83 c1 10 add $0x10,%rcx + 422016: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42201a: 49 83 c2 10 add $0x10,%r10 + 42201e: 7f 50 jg 422070 <__GI_strcmp+0xd70> + 422020: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 422025: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42202a: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42202e: 66 0f 73 db 0a psrldq $0xa,%xmm3 + 422033: 66 0f 73 fa 06 pslldq $0x6,%xmm2 + 422038: 66 0f eb d3 por %xmm3,%xmm2 + 42203c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 422040: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 422044: 66 0f f8 c8 psubb %xmm0,%xmm1 + 422048: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42204c: 81 ea ff ff 00 00 sub $0xffff,%edx + 422052: 0f 85 98 06 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 422058: 48 83 c1 10 add $0x10,%rcx + 42205c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 422060: e9 6b ff ff ff jmpq 421fd0 <__GI_strcmp+0xcd0> + 422065: 90 nop + 422066: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42206d: 00 00 00 + 422070: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 422074: 66 0f d7 d0 pmovmskb %xmm0,%edx + 422078: f7 c2 00 fc 00 00 test $0xfc00,%edx + 42207e: 75 10 jne 422090 <__GI_strcmp+0xd90> + 422080: 66 0f ef c0 pxor %xmm0,%xmm0 + 422084: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42208b: e9 4a ff ff ff jmpq 421fda <__GI_strcmp+0xcda> + 422090: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 422095: 66 0f 73 d8 0a psrldq $0xa,%xmm0 + 42209a: 66 0f 73 db 0a psrldq $0xa,%xmm3 + 42209f: e9 3c 06 00 00 jmpq 4226e0 <__GI_strcmp+0x13e0> + 4220a4: 66 90 xchg %ax,%ax + 4220a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4220ad: 00 00 00 + 4220b0: 66 0f ef c0 pxor %xmm0,%xmm0 + 4220b4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 4220b8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 4220bc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4220c0: 66 0f 73 fa 05 pslldq $0x5,%xmm2 + 4220c5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 4220c9: 66 0f f8 d0 psubb %xmm0,%xmm2 + 4220cd: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 4220d2: d3 ea shr %cl,%edx + 4220d4: 41 d3 e9 shr %cl,%r9d + 4220d7: 44 29 ca sub %r9d,%edx + 4220da: 0f 85 15 06 00 00 jne 4226f5 <__GI_strcmp+0x13f5> + 4220e0: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 4220e4: 66 0f ef c0 pxor %xmm0,%xmm0 + 4220e8: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 4220ef: 41 b9 0b 00 00 00 mov $0xb,%r9d + 4220f5: 4c 8d 57 0b lea 0xb(%rdi),%r10 + 4220f9: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 422100: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 422107: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 42210e: 00 00 + 422110: 49 83 c2 10 add $0x10,%r10 + 422114: 0f 8f 96 00 00 00 jg 4221b0 <__GI_strcmp+0xeb0> + 42211a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42211f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 422124: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 422128: 66 0f 73 db 0b psrldq $0xb,%xmm3 + 42212d: 66 0f 73 fa 05 pslldq $0x5,%xmm2 + 422132: 66 0f eb d3 por %xmm3,%xmm2 + 422136: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42213a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42213e: 66 0f f8 c8 psubb %xmm0,%xmm1 + 422142: 66 0f d7 d1 pmovmskb %xmm1,%edx + 422146: 81 ea ff ff 00 00 sub $0xffff,%edx + 42214c: 0f 85 9e 05 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 422152: 48 83 c1 10 add $0x10,%rcx + 422156: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42215a: 49 83 c2 10 add $0x10,%r10 + 42215e: 7f 50 jg 4221b0 <__GI_strcmp+0xeb0> + 422160: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 422165: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42216a: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42216e: 66 0f 73 db 0b psrldq $0xb,%xmm3 + 422173: 66 0f 73 fa 05 pslldq $0x5,%xmm2 + 422178: 66 0f eb d3 por %xmm3,%xmm2 + 42217c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 422180: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 422184: 66 0f f8 c8 psubb %xmm0,%xmm1 + 422188: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42218c: 81 ea ff ff 00 00 sub $0xffff,%edx + 422192: 0f 85 58 05 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 422198: 48 83 c1 10 add $0x10,%rcx + 42219c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 4221a0: e9 6b ff ff ff jmpq 422110 <__GI_strcmp+0xe10> + 4221a5: 90 nop + 4221a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4221ad: 00 00 00 + 4221b0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 4221b4: 66 0f d7 d0 pmovmskb %xmm0,%edx + 4221b8: f7 c2 00 f8 00 00 test $0xf800,%edx + 4221be: 75 10 jne 4221d0 <__GI_strcmp+0xed0> + 4221c0: 66 0f ef c0 pxor %xmm0,%xmm0 + 4221c4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 4221cb: e9 4a ff ff ff jmpq 42211a <__GI_strcmp+0xe1a> + 4221d0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4221d5: 66 0f 73 d8 0b psrldq $0xb,%xmm0 + 4221da: 66 0f 73 db 0b psrldq $0xb,%xmm3 + 4221df: e9 fc 04 00 00 jmpq 4226e0 <__GI_strcmp+0x13e0> + 4221e4: 66 90 xchg %ax,%ax + 4221e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4221ed: 00 00 00 + 4221f0: 66 0f ef c0 pxor %xmm0,%xmm0 + 4221f4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 4221f8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 4221fc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 422200: 66 0f 73 fa 04 pslldq $0x4,%xmm2 + 422205: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 422209: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42220d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 422212: d3 ea shr %cl,%edx + 422214: 41 d3 e9 shr %cl,%r9d + 422217: 44 29 ca sub %r9d,%edx + 42221a: 0f 85 d5 04 00 00 jne 4226f5 <__GI_strcmp+0x13f5> + 422220: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 422224: 66 0f ef c0 pxor %xmm0,%xmm0 + 422228: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42222f: 41 b9 0c 00 00 00 mov $0xc,%r9d + 422235: 4c 8d 57 0c lea 0xc(%rdi),%r10 + 422239: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 422240: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 422247: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 42224e: 00 00 + 422250: 49 83 c2 10 add $0x10,%r10 + 422254: 0f 8f 96 00 00 00 jg 4222f0 <__GI_strcmp+0xff0> + 42225a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42225f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 422264: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 422268: 66 0f 73 db 0c psrldq $0xc,%xmm3 + 42226d: 66 0f 73 fa 04 pslldq $0x4,%xmm2 + 422272: 66 0f eb d3 por %xmm3,%xmm2 + 422276: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42227a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42227e: 66 0f f8 c8 psubb %xmm0,%xmm1 + 422282: 66 0f d7 d1 pmovmskb %xmm1,%edx + 422286: 81 ea ff ff 00 00 sub $0xffff,%edx + 42228c: 0f 85 5e 04 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 422292: 48 83 c1 10 add $0x10,%rcx + 422296: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42229a: 49 83 c2 10 add $0x10,%r10 + 42229e: 7f 50 jg 4222f0 <__GI_strcmp+0xff0> + 4222a0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4222a5: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4222aa: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 4222ae: 66 0f 73 db 0c psrldq $0xc,%xmm3 + 4222b3: 66 0f 73 fa 04 pslldq $0x4,%xmm2 + 4222b8: 66 0f eb d3 por %xmm3,%xmm2 + 4222bc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4222c0: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 4222c4: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4222c8: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4222cc: 81 ea ff ff 00 00 sub $0xffff,%edx + 4222d2: 0f 85 18 04 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 4222d8: 48 83 c1 10 add $0x10,%rcx + 4222dc: 66 0f 6f dc movdqa %xmm4,%xmm3 + 4222e0: e9 6b ff ff ff jmpq 422250 <__GI_strcmp+0xf50> + 4222e5: 90 nop + 4222e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4222ed: 00 00 00 + 4222f0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 4222f4: 66 0f d7 d0 pmovmskb %xmm0,%edx + 4222f8: f7 c2 00 f0 00 00 test $0xf000,%edx + 4222fe: 75 10 jne 422310 <__GI_strcmp+0x1010> + 422300: 66 0f ef c0 pxor %xmm0,%xmm0 + 422304: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42230b: e9 4a ff ff ff jmpq 42225a <__GI_strcmp+0xf5a> + 422310: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 422315: 66 0f 73 d8 0c psrldq $0xc,%xmm0 + 42231a: 66 0f 73 db 0c psrldq $0xc,%xmm3 + 42231f: e9 bc 03 00 00 jmpq 4226e0 <__GI_strcmp+0x13e0> + 422324: 66 90 xchg %ax,%ax + 422326: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42232d: 00 00 00 + 422330: 66 0f ef c0 pxor %xmm0,%xmm0 + 422334: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 422338: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42233c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 422340: 66 0f 73 fa 03 pslldq $0x3,%xmm2 + 422345: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 422349: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42234d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 422352: d3 ea shr %cl,%edx + 422354: 41 d3 e9 shr %cl,%r9d + 422357: 44 29 ca sub %r9d,%edx + 42235a: 0f 85 95 03 00 00 jne 4226f5 <__GI_strcmp+0x13f5> + 422360: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 422364: 66 0f ef c0 pxor %xmm0,%xmm0 + 422368: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42236f: 41 b9 0d 00 00 00 mov $0xd,%r9d + 422375: 4c 8d 57 0d lea 0xd(%rdi),%r10 + 422379: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 422380: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 422387: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 42238e: 00 00 + 422390: 49 83 c2 10 add $0x10,%r10 + 422394: 0f 8f 96 00 00 00 jg 422430 <__GI_strcmp+0x1130> + 42239a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42239f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4223a4: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 4223a8: 66 0f 73 db 0d psrldq $0xd,%xmm3 + 4223ad: 66 0f 73 fa 03 pslldq $0x3,%xmm2 + 4223b2: 66 0f eb d3 por %xmm3,%xmm2 + 4223b6: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4223ba: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 4223be: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4223c2: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4223c6: 81 ea ff ff 00 00 sub $0xffff,%edx + 4223cc: 0f 85 1e 03 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 4223d2: 48 83 c1 10 add $0x10,%rcx + 4223d6: 66 0f 6f dc movdqa %xmm4,%xmm3 + 4223da: 49 83 c2 10 add $0x10,%r10 + 4223de: 7f 50 jg 422430 <__GI_strcmp+0x1130> + 4223e0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4223e5: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4223ea: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 4223ee: 66 0f 73 db 0d psrldq $0xd,%xmm3 + 4223f3: 66 0f 73 fa 03 pslldq $0x3,%xmm2 + 4223f8: 66 0f eb d3 por %xmm3,%xmm2 + 4223fc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 422400: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 422404: 66 0f f8 c8 psubb %xmm0,%xmm1 + 422408: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42240c: 81 ea ff ff 00 00 sub $0xffff,%edx + 422412: 0f 85 d8 02 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 422418: 48 83 c1 10 add $0x10,%rcx + 42241c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 422420: e9 6b ff ff ff jmpq 422390 <__GI_strcmp+0x1090> + 422425: 90 nop + 422426: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42242d: 00 00 00 + 422430: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 422434: 66 0f d7 d0 pmovmskb %xmm0,%edx + 422438: f7 c2 00 e0 00 00 test $0xe000,%edx + 42243e: 75 10 jne 422450 <__GI_strcmp+0x1150> + 422440: 66 0f ef c0 pxor %xmm0,%xmm0 + 422444: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42244b: e9 4a ff ff ff jmpq 42239a <__GI_strcmp+0x109a> + 422450: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 422455: 66 0f 73 d8 0d psrldq $0xd,%xmm0 + 42245a: 66 0f 73 db 0d psrldq $0xd,%xmm3 + 42245f: e9 7c 02 00 00 jmpq 4226e0 <__GI_strcmp+0x13e0> + 422464: 66 90 xchg %ax,%ax + 422466: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42246d: 00 00 00 + 422470: 66 0f ef c0 pxor %xmm0,%xmm0 + 422474: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 422478: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42247c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 422480: 66 0f 73 fa 02 pslldq $0x2,%xmm2 + 422485: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 422489: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42248d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 422492: d3 ea shr %cl,%edx + 422494: 41 d3 e9 shr %cl,%r9d + 422497: 44 29 ca sub %r9d,%edx + 42249a: 0f 85 55 02 00 00 jne 4226f5 <__GI_strcmp+0x13f5> + 4224a0: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 4224a4: 66 0f ef c0 pxor %xmm0,%xmm0 + 4224a8: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 4224af: 41 b9 0e 00 00 00 mov $0xe,%r9d + 4224b5: 4c 8d 57 0e lea 0xe(%rdi),%r10 + 4224b9: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 4224c0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 4224c7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 4224ce: 00 00 + 4224d0: 49 83 c2 10 add $0x10,%r10 + 4224d4: 0f 8f 96 00 00 00 jg 422570 <__GI_strcmp+0x1270> + 4224da: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4224df: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4224e4: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 4224e8: 66 0f 73 db 0e psrldq $0xe,%xmm3 + 4224ed: 66 0f 73 fa 02 pslldq $0x2,%xmm2 + 4224f2: 66 0f eb d3 por %xmm3,%xmm2 + 4224f6: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4224fa: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 4224fe: 66 0f f8 c8 psubb %xmm0,%xmm1 + 422502: 66 0f d7 d1 pmovmskb %xmm1,%edx + 422506: 81 ea ff ff 00 00 sub $0xffff,%edx + 42250c: 0f 85 de 01 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 422512: 48 83 c1 10 add $0x10,%rcx + 422516: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42251a: 49 83 c2 10 add $0x10,%r10 + 42251e: 7f 50 jg 422570 <__GI_strcmp+0x1270> + 422520: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 422525: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42252a: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42252e: 66 0f 73 db 0e psrldq $0xe,%xmm3 + 422533: 66 0f 73 fa 02 pslldq $0x2,%xmm2 + 422538: 66 0f eb d3 por %xmm3,%xmm2 + 42253c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 422540: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 422544: 66 0f f8 c8 psubb %xmm0,%xmm1 + 422548: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42254c: 81 ea ff ff 00 00 sub $0xffff,%edx + 422552: 0f 85 98 01 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 422558: 48 83 c1 10 add $0x10,%rcx + 42255c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 422560: e9 6b ff ff ff jmpq 4224d0 <__GI_strcmp+0x11d0> + 422565: 90 nop + 422566: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42256d: 00 00 00 + 422570: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 422574: 66 0f d7 d0 pmovmskb %xmm0,%edx + 422578: f7 c2 00 c0 00 00 test $0xc000,%edx + 42257e: 75 10 jne 422590 <__GI_strcmp+0x1290> + 422580: 66 0f ef c0 pxor %xmm0,%xmm0 + 422584: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42258b: e9 4a ff ff ff jmpq 4224da <__GI_strcmp+0x11da> + 422590: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 422595: 66 0f 73 d8 0e psrldq $0xe,%xmm0 + 42259a: 66 0f 73 db 0e psrldq $0xe,%xmm3 + 42259f: e9 3c 01 00 00 jmpq 4226e0 <__GI_strcmp+0x13e0> + 4225a4: 66 90 xchg %ax,%ax + 4225a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4225ad: 00 00 00 + 4225b0: 66 0f ef c0 pxor %xmm0,%xmm0 + 4225b4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 4225b8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 4225bc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4225c0: 66 0f 73 fa 01 pslldq $0x1,%xmm2 + 4225c5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 4225c9: 66 0f f8 d0 psubb %xmm0,%xmm2 + 4225cd: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 4225d2: d3 ea shr %cl,%edx + 4225d4: 41 d3 e9 shr %cl,%r9d + 4225d7: 44 29 ca sub %r9d,%edx + 4225da: 0f 85 15 01 00 00 jne 4226f5 <__GI_strcmp+0x13f5> + 4225e0: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 4225e4: 66 0f ef c0 pxor %xmm0,%xmm0 + 4225e8: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 4225ef: 41 b9 0f 00 00 00 mov $0xf,%r9d + 4225f5: 4c 8d 57 0f lea 0xf(%rdi),%r10 + 4225f9: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 422600: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 422607: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 42260e: 00 00 + 422610: 49 83 c2 10 add $0x10,%r10 + 422614: 0f 8f 96 00 00 00 jg 4226b0 <__GI_strcmp+0x13b0> + 42261a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42261f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 422624: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 422628: 66 0f 73 db 0f psrldq $0xf,%xmm3 + 42262d: 66 0f 73 fa 01 pslldq $0x1,%xmm2 + 422632: 66 0f eb d3 por %xmm3,%xmm2 + 422636: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42263a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42263e: 66 0f f8 c8 psubb %xmm0,%xmm1 + 422642: 66 0f d7 d1 pmovmskb %xmm1,%edx + 422646: 81 ea ff ff 00 00 sub $0xffff,%edx + 42264c: 0f 85 9e 00 00 00 jne 4226f0 <__GI_strcmp+0x13f0> + 422652: 48 83 c1 10 add $0x10,%rcx + 422656: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42265a: 49 83 c2 10 add $0x10,%r10 + 42265e: 7f 50 jg 4226b0 <__GI_strcmp+0x13b0> + 422660: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 422665: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42266a: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42266e: 66 0f 73 db 0f psrldq $0xf,%xmm3 + 422673: 66 0f 73 fa 01 pslldq $0x1,%xmm2 + 422678: 66 0f eb d3 por %xmm3,%xmm2 + 42267c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 422680: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 422684: 66 0f f8 c8 psubb %xmm0,%xmm1 + 422688: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42268c: 81 ea ff ff 00 00 sub $0xffff,%edx + 422692: 75 5c jne 4226f0 <__GI_strcmp+0x13f0> + 422694: 48 83 c1 10 add $0x10,%rcx + 422698: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42269c: e9 6f ff ff ff jmpq 422610 <__GI_strcmp+0x1310> + 4226a1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4226a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4226ad: 00 00 00 + 4226b0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 4226b4: 66 0f d7 d0 pmovmskb %xmm0,%edx + 4226b8: f7 c2 00 80 00 00 test $0x8000,%edx + 4226be: 75 10 jne 4226d0 <__GI_strcmp+0x13d0> + 4226c0: 66 0f ef c0 pxor %xmm0,%xmm0 + 4226c4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 4226cb: e9 4a ff ff ff jmpq 42261a <__GI_strcmp+0x131a> + 4226d0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4226d5: 66 0f 73 db 0f psrldq $0xf,%xmm3 + 4226da: 66 0f 73 d8 0f psrldq $0xf,%xmm0 + 4226df: 90 nop + 4226e0: 66 0f 74 cb pcmpeqb %xmm3,%xmm1 + 4226e4: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4226e8: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4226ec: f7 d2 not %edx + 4226ee: 66 90 xchg %ax,%ax + 4226f0: 49 8d 44 09 f0 lea -0x10(%r9,%rcx,1),%rax + 4226f5: 48 8d 3c 07 lea (%rdi,%rax,1),%rdi + 4226f9: 48 8d 34 0e lea (%rsi,%rcx,1),%rsi + 4226fd: 45 85 c0 test %r8d,%r8d + 422700: 74 0e je 422710 <__GI_strcmp+0x1410> + 422702: 48 87 f7 xchg %rsi,%rdi + 422705: 90 nop + 422706: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42270d: 00 00 00 + 422710: 48 0f bc d2 bsf %rdx,%rdx + 422714: 0f b6 0c 16 movzbl (%rsi,%rdx,1),%ecx + 422718: 0f b6 04 17 movzbl (%rdi,%rdx,1),%eax + 42271c: 29 c8 sub %ecx,%eax + 42271e: c3 retq + 42271f: 31 c0 xor %eax,%eax + 422721: c3 retq + 422722: 0f 1f 40 00 nopl 0x0(%rax) + 422726: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42272d: 00 00 00 + 422730: 0f b6 0e movzbl (%rsi),%ecx + 422733: 0f b6 07 movzbl (%rdi),%eax + 422736: 29 c8 sub %ecx,%eax + 422738: c3 retq + 422739: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + +0000000000422740 <__strcmp_sse42>: + 422740: 89 f1 mov %esi,%ecx + 422742: 89 f8 mov %edi,%eax + 422744: 48 83 e1 3f and $0x3f,%rcx + 422748: 48 83 e0 3f and $0x3f,%rax + 42274c: 83 f9 30 cmp $0x30,%ecx + 42274f: 77 3f ja 422790 <__strcmp_sse42+0x50> + 422751: 83 f8 30 cmp $0x30,%eax + 422754: 77 3a ja 422790 <__strcmp_sse42+0x50> + 422756: f3 0f 6f 0f movdqu (%rdi),%xmm1 + 42275a: f3 0f 6f 16 movdqu (%rsi),%xmm2 + 42275e: 66 0f ef c0 pxor %xmm0,%xmm0 + 422762: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 422766: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42276a: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42276e: 66 0f d7 d1 pmovmskb %xmm1,%edx + 422772: 81 ea ff ff 00 00 sub $0xffff,%edx + 422778: 0f 85 42 0d 00 00 jne 4234c0 <__strcmp_sse42+0xd80> + 42277e: 48 83 c6 10 add $0x10,%rsi + 422782: 48 83 c7 10 add $0x10,%rdi + 422786: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42278d: 00 00 00 + 422790: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi + 422794: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi + 422798: ba ff ff 00 00 mov $0xffff,%edx + 42279d: 45 31 c0 xor %r8d,%r8d + 4227a0: 83 e1 0f and $0xf,%ecx + 4227a3: 83 e0 0f and $0xf,%eax + 4227a6: 66 0f ef c0 pxor %xmm0,%xmm0 + 4227aa: 39 c1 cmp %eax,%ecx + 4227ac: 74 32 je 4227e0 <__strcmp_sse42+0xa0> + 4227ae: 77 07 ja 4227b7 <__strcmp_sse42+0x77> + 4227b0: 41 89 d0 mov %edx,%r8d + 4227b3: 91 xchg %eax,%ecx + 4227b4: 48 87 f7 xchg %rsi,%rdi + 4227b7: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 4227bb: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 4227bf: 4c 8d 48 0f lea 0xf(%rax),%r9 + 4227c3: 49 29 c9 sub %rcx,%r9 + 4227c6: 4c 8d 15 23 08 08 00 lea 0x80823(%rip),%r10 # 4a2ff0 <__func__.10972+0x30> + 4227cd: 4f 63 0c 8a movslq (%r10,%r9,4),%r9 + 4227d1: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4227d5: 4f 8d 14 0a lea (%r10,%r9,1),%r10 + 4227d9: 41 ff e2 jmpq *%r10 + 4227dc: 0f 1f 40 00 nopl 0x0(%rax) + 4227e0: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 4227e4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4227e8: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 + 4227ec: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4227f0: 66 44 0f d7 c9 pmovmskb %xmm1,%r9d + 4227f5: d3 ea shr %cl,%edx + 4227f7: 41 d3 e9 shr %cl,%r9d + 4227fa: 44 29 ca sub %r9d,%edx + 4227fd: 0f 85 a8 0c 00 00 jne 4234ab <__strcmp_sse42+0xd6b> + 422803: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42280a: 49 c7 c1 10 00 00 00 mov $0x10,%r9 + 422811: 48 89 ca mov %rcx,%rdx + 422814: 66 90 xchg %ax,%ax + 422816: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42281d: 00 00 00 + 422820: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 422825: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 42282c: 48 8d 52 10 lea 0x10(%rdx),%rdx + 422830: 76 1e jbe 422850 <__strcmp_sse42+0x110> + 422832: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 422837: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 42283e: 48 8d 52 10 lea 0x10(%rdx),%rdx + 422842: 76 0c jbe 422850 <__strcmp_sse42+0x110> + 422844: eb da jmp 422820 <__strcmp_sse42+0xe0> + 422846: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42284d: 00 00 00 + 422850: 0f 83 79 0c 00 00 jae 4234cf <__strcmp_sse42+0xd8f> + 422856: 48 8d 4c 0a f0 lea -0x10(%rdx,%rcx,1),%rcx + 42285b: 0f b6 04 0f movzbl (%rdi,%rcx,1),%eax + 42285f: 0f b6 14 0e movzbl (%rsi,%rcx,1),%edx + 422863: 29 d0 sub %edx,%eax + 422865: c3 retq + 422866: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42286d: 00 00 00 + 422870: 66 0f 73 fa 0f pslldq $0xf,%xmm2 + 422875: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 422879: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42287d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 422882: d3 ea shr %cl,%edx + 422884: 41 d3 e9 shr %cl,%r9d + 422887: 44 29 ca sub %r9d,%edx + 42288a: 0f 85 1b 0c 00 00 jne 4234ab <__strcmp_sse42+0xd6b> + 422890: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 422894: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42289b: 41 b9 01 00 00 00 mov $0x1,%r9d + 4228a1: 4c 8d 57 01 lea 0x1(%rdi),%r10 + 4228a5: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 4228ac: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 4228b3: 48 89 ca mov %rcx,%rdx + 4228b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4228bd: 00 00 00 + 4228c0: 49 83 c2 10 add $0x10,%r10 + 4228c4: 7f 4a jg 422910 <__strcmp_sse42+0x1d0> + 4228c6: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 4228cb: 66 0f 3a 0f 44 17 f0 palignr $0x1,-0x10(%rdi,%rdx,1),%xmm0 + 4228d2: 01 + 4228d3: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 4228da: 0f 86 b0 0b 00 00 jbe 423490 <__strcmp_sse42+0xd50> + 4228e0: 48 83 c2 10 add $0x10,%rdx + 4228e4: 49 83 c2 10 add $0x10,%r10 + 4228e8: 7f 26 jg 422910 <__strcmp_sse42+0x1d0> + 4228ea: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 4228ef: 66 0f 3a 0f 44 17 f0 palignr $0x1,-0x10(%rdi,%rdx,1),%xmm0 + 4228f6: 01 + 4228f7: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 4228fe: 0f 86 8c 0b 00 00 jbe 423490 <__strcmp_sse42+0xd50> + 422904: 48 83 c2 10 add $0x10,%rdx + 422908: eb b6 jmp 4228c0 <__strcmp_sse42+0x180> + 42290a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 422910: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 422917: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 + 42291d: 66 0f 73 d8 01 psrldq $0x1,%xmm0 + 422922: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 + 422928: 83 f9 0e cmp $0xe,%ecx + 42292b: 77 99 ja 4228c6 <__strcmp_sse42+0x186> + 42292d: e9 4b 0b 00 00 jmpq 42347d <__strcmp_sse42+0xd3d> + 422932: 0f 1f 40 00 nopl 0x0(%rax) + 422936: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42293d: 00 00 00 + 422940: 66 0f 73 fa 0e pslldq $0xe,%xmm2 + 422945: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 422949: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42294d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 422952: d3 ea shr %cl,%edx + 422954: 41 d3 e9 shr %cl,%r9d + 422957: 44 29 ca sub %r9d,%edx + 42295a: 0f 85 4b 0b 00 00 jne 4234ab <__strcmp_sse42+0xd6b> + 422960: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 422964: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42296b: 41 b9 02 00 00 00 mov $0x2,%r9d + 422971: 4c 8d 57 02 lea 0x2(%rdi),%r10 + 422975: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42297c: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 422983: 48 89 ca mov %rcx,%rdx + 422986: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42298d: 00 00 00 + 422990: 49 83 c2 10 add $0x10,%r10 + 422994: 7f 4a jg 4229e0 <__strcmp_sse42+0x2a0> + 422996: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 42299b: 66 0f 3a 0f 44 17 f0 palignr $0x2,-0x10(%rdi,%rdx,1),%xmm0 + 4229a2: 02 + 4229a3: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 4229aa: 0f 86 e0 0a 00 00 jbe 423490 <__strcmp_sse42+0xd50> + 4229b0: 48 83 c2 10 add $0x10,%rdx + 4229b4: 49 83 c2 10 add $0x10,%r10 + 4229b8: 7f 26 jg 4229e0 <__strcmp_sse42+0x2a0> + 4229ba: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 4229bf: 66 0f 3a 0f 44 17 f0 palignr $0x2,-0x10(%rdi,%rdx,1),%xmm0 + 4229c6: 02 + 4229c7: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 4229ce: 0f 86 bc 0a 00 00 jbe 423490 <__strcmp_sse42+0xd50> + 4229d4: 48 83 c2 10 add $0x10,%rdx + 4229d8: eb b6 jmp 422990 <__strcmp_sse42+0x250> + 4229da: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4229e0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 4229e7: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 + 4229ed: 66 0f 73 d8 02 psrldq $0x2,%xmm0 + 4229f2: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 + 4229f8: 83 f9 0d cmp $0xd,%ecx + 4229fb: 77 99 ja 422996 <__strcmp_sse42+0x256> + 4229fd: e9 7b 0a 00 00 jmpq 42347d <__strcmp_sse42+0xd3d> + 422a02: 0f 1f 40 00 nopl 0x0(%rax) + 422a06: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 422a0d: 00 00 00 + 422a10: 66 0f 73 fa 0d pslldq $0xd,%xmm2 + 422a15: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 422a19: 66 0f f8 d0 psubb %xmm0,%xmm2 + 422a1d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 422a22: d3 ea shr %cl,%edx + 422a24: 41 d3 e9 shr %cl,%r9d + 422a27: 44 29 ca sub %r9d,%edx + 422a2a: 0f 85 7b 0a 00 00 jne 4234ab <__strcmp_sse42+0xd6b> + 422a30: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 422a34: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 422a3b: 41 b9 03 00 00 00 mov $0x3,%r9d + 422a41: 4c 8d 57 03 lea 0x3(%rdi),%r10 + 422a45: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 422a4c: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 422a53: 48 89 ca mov %rcx,%rdx + 422a56: 49 83 c2 10 add $0x10,%r10 + 422a5a: 7f 44 jg 422aa0 <__strcmp_sse42+0x360> + 422a5c: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 422a61: 66 0f 3a 0f 44 17 f0 palignr $0x3,-0x10(%rdi,%rdx,1),%xmm0 + 422a68: 03 + 422a69: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 422a70: 0f 86 1a 0a 00 00 jbe 423490 <__strcmp_sse42+0xd50> + 422a76: 48 83 c2 10 add $0x10,%rdx + 422a7a: 49 83 c2 10 add $0x10,%r10 + 422a7e: 7f 20 jg 422aa0 <__strcmp_sse42+0x360> + 422a80: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 422a85: 66 0f 3a 0f 44 17 f0 palignr $0x3,-0x10(%rdi,%rdx,1),%xmm0 + 422a8c: 03 + 422a8d: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 422a94: 0f 86 f6 09 00 00 jbe 423490 <__strcmp_sse42+0xd50> + 422a9a: 48 83 c2 10 add $0x10,%rdx + 422a9e: eb b6 jmp 422a56 <__strcmp_sse42+0x316> + 422aa0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 422aa7: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 + 422aad: 66 0f 73 d8 03 psrldq $0x3,%xmm0 + 422ab2: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 + 422ab8: 83 f9 0c cmp $0xc,%ecx + 422abb: 77 9f ja 422a5c <__strcmp_sse42+0x31c> + 422abd: e9 bb 09 00 00 jmpq 42347d <__strcmp_sse42+0xd3d> + 422ac2: 0f 1f 40 00 nopl 0x0(%rax) + 422ac6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 422acd: 00 00 00 + 422ad0: 66 0f 73 fa 0c pslldq $0xc,%xmm2 + 422ad5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 422ad9: 66 0f f8 d0 psubb %xmm0,%xmm2 + 422add: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 422ae2: d3 ea shr %cl,%edx + 422ae4: 41 d3 e9 shr %cl,%r9d + 422ae7: 44 29 ca sub %r9d,%edx + 422aea: 0f 85 bb 09 00 00 jne 4234ab <__strcmp_sse42+0xd6b> + 422af0: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 422af4: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 422afb: 41 b9 04 00 00 00 mov $0x4,%r9d + 422b01: 4c 8d 57 04 lea 0x4(%rdi),%r10 + 422b05: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 422b0c: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 422b13: 48 89 ca mov %rcx,%rdx + 422b16: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 422b1d: 00 00 00 + 422b20: 49 83 c2 10 add $0x10,%r10 + 422b24: 7f 4a jg 422b70 <__strcmp_sse42+0x430> + 422b26: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 422b2b: 66 0f 3a 0f 44 17 f0 palignr $0x4,-0x10(%rdi,%rdx,1),%xmm0 + 422b32: 04 + 422b33: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 422b3a: 0f 86 50 09 00 00 jbe 423490 <__strcmp_sse42+0xd50> + 422b40: 48 83 c2 10 add $0x10,%rdx + 422b44: 49 83 c2 10 add $0x10,%r10 + 422b48: 7f 26 jg 422b70 <__strcmp_sse42+0x430> + 422b4a: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 422b4f: 66 0f 3a 0f 44 17 f0 palignr $0x4,-0x10(%rdi,%rdx,1),%xmm0 + 422b56: 04 + 422b57: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 422b5e: 0f 86 2c 09 00 00 jbe 423490 <__strcmp_sse42+0xd50> + 422b64: 48 83 c2 10 add $0x10,%rdx + 422b68: eb b6 jmp 422b20 <__strcmp_sse42+0x3e0> + 422b6a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 422b70: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 422b77: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 + 422b7d: 66 0f 73 d8 04 psrldq $0x4,%xmm0 + 422b82: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 + 422b88: 83 f9 0b cmp $0xb,%ecx + 422b8b: 77 99 ja 422b26 <__strcmp_sse42+0x3e6> + 422b8d: e9 eb 08 00 00 jmpq 42347d <__strcmp_sse42+0xd3d> + 422b92: 0f 1f 40 00 nopl 0x0(%rax) + 422b96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 422b9d: 00 00 00 + 422ba0: 66 0f 73 fa 0b pslldq $0xb,%xmm2 + 422ba5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 422ba9: 66 0f f8 d0 psubb %xmm0,%xmm2 + 422bad: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 422bb2: d3 ea shr %cl,%edx + 422bb4: 41 d3 e9 shr %cl,%r9d + 422bb7: 44 29 ca sub %r9d,%edx + 422bba: 0f 85 eb 08 00 00 jne 4234ab <__strcmp_sse42+0xd6b> + 422bc0: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 422bc4: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 422bcb: 41 b9 05 00 00 00 mov $0x5,%r9d + 422bd1: 4c 8d 57 05 lea 0x5(%rdi),%r10 + 422bd5: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 422bdc: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 422be3: 48 89 ca mov %rcx,%rdx + 422be6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 422bed: 00 00 00 + 422bf0: 49 83 c2 10 add $0x10,%r10 + 422bf4: 7f 4a jg 422c40 <__strcmp_sse42+0x500> + 422bf6: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 422bfb: 66 0f 3a 0f 44 17 f0 palignr $0x5,-0x10(%rdi,%rdx,1),%xmm0 + 422c02: 05 + 422c03: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 422c0a: 0f 86 80 08 00 00 jbe 423490 <__strcmp_sse42+0xd50> + 422c10: 48 83 c2 10 add $0x10,%rdx + 422c14: 49 83 c2 10 add $0x10,%r10 + 422c18: 7f 26 jg 422c40 <__strcmp_sse42+0x500> + 422c1a: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 422c1f: 66 0f 3a 0f 44 17 f0 palignr $0x5,-0x10(%rdi,%rdx,1),%xmm0 + 422c26: 05 + 422c27: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 422c2e: 0f 86 5c 08 00 00 jbe 423490 <__strcmp_sse42+0xd50> + 422c34: 48 83 c2 10 add $0x10,%rdx + 422c38: eb b6 jmp 422bf0 <__strcmp_sse42+0x4b0> + 422c3a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 422c40: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 422c47: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 + 422c4d: 66 0f 73 d8 05 psrldq $0x5,%xmm0 + 422c52: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 + 422c58: 83 f9 0a cmp $0xa,%ecx + 422c5b: 77 99 ja 422bf6 <__strcmp_sse42+0x4b6> + 422c5d: e9 1b 08 00 00 jmpq 42347d <__strcmp_sse42+0xd3d> + 422c62: 0f 1f 40 00 nopl 0x0(%rax) + 422c66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 422c6d: 00 00 00 + 422c70: 66 0f 73 fa 0a pslldq $0xa,%xmm2 + 422c75: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 422c79: 66 0f f8 d0 psubb %xmm0,%xmm2 + 422c7d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 422c82: d3 ea shr %cl,%edx + 422c84: 41 d3 e9 shr %cl,%r9d + 422c87: 44 29 ca sub %r9d,%edx + 422c8a: 0f 85 1b 08 00 00 jne 4234ab <__strcmp_sse42+0xd6b> + 422c90: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 422c94: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 422c9b: 41 b9 06 00 00 00 mov $0x6,%r9d + 422ca1: 4c 8d 57 06 lea 0x6(%rdi),%r10 + 422ca5: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 422cac: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 422cb3: 48 89 ca mov %rcx,%rdx + 422cb6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 422cbd: 00 00 00 + 422cc0: 49 83 c2 10 add $0x10,%r10 + 422cc4: 7f 4a jg 422d10 <__strcmp_sse42+0x5d0> + 422cc6: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 422ccb: 66 0f 3a 0f 44 17 f0 palignr $0x6,-0x10(%rdi,%rdx,1),%xmm0 + 422cd2: 06 + 422cd3: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 422cda: 0f 86 b0 07 00 00 jbe 423490 <__strcmp_sse42+0xd50> + 422ce0: 48 83 c2 10 add $0x10,%rdx + 422ce4: 49 83 c2 10 add $0x10,%r10 + 422ce8: 7f 26 jg 422d10 <__strcmp_sse42+0x5d0> + 422cea: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 422cef: 66 0f 3a 0f 44 17 f0 palignr $0x6,-0x10(%rdi,%rdx,1),%xmm0 + 422cf6: 06 + 422cf7: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 422cfe: 0f 86 8c 07 00 00 jbe 423490 <__strcmp_sse42+0xd50> + 422d04: 48 83 c2 10 add $0x10,%rdx + 422d08: eb b6 jmp 422cc0 <__strcmp_sse42+0x580> + 422d0a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 422d10: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 422d17: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 + 422d1d: 66 0f 73 d8 06 psrldq $0x6,%xmm0 + 422d22: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 + 422d28: 83 f9 09 cmp $0x9,%ecx + 422d2b: 77 99 ja 422cc6 <__strcmp_sse42+0x586> + 422d2d: e9 4b 07 00 00 jmpq 42347d <__strcmp_sse42+0xd3d> + 422d32: 0f 1f 40 00 nopl 0x0(%rax) + 422d36: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 422d3d: 00 00 00 + 422d40: 66 0f 73 fa 09 pslldq $0x9,%xmm2 + 422d45: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 422d49: 66 0f f8 d0 psubb %xmm0,%xmm2 + 422d4d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 422d52: d3 ea shr %cl,%edx + 422d54: 41 d3 e9 shr %cl,%r9d + 422d57: 44 29 ca sub %r9d,%edx + 422d5a: 0f 85 4b 07 00 00 jne 4234ab <__strcmp_sse42+0xd6b> + 422d60: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 422d64: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 422d6b: 41 b9 07 00 00 00 mov $0x7,%r9d + 422d71: 4c 8d 57 07 lea 0x7(%rdi),%r10 + 422d75: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 422d7c: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 422d83: 48 89 ca mov %rcx,%rdx + 422d86: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 422d8d: 00 00 00 + 422d90: 49 83 c2 10 add $0x10,%r10 + 422d94: 7f 4a jg 422de0 <__strcmp_sse42+0x6a0> + 422d96: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 422d9b: 66 0f 3a 0f 44 17 f0 palignr $0x7,-0x10(%rdi,%rdx,1),%xmm0 + 422da2: 07 + 422da3: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 422daa: 0f 86 e0 06 00 00 jbe 423490 <__strcmp_sse42+0xd50> + 422db0: 48 83 c2 10 add $0x10,%rdx + 422db4: 49 83 c2 10 add $0x10,%r10 + 422db8: 7f 26 jg 422de0 <__strcmp_sse42+0x6a0> + 422dba: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 422dbf: 66 0f 3a 0f 44 17 f0 palignr $0x7,-0x10(%rdi,%rdx,1),%xmm0 + 422dc6: 07 + 422dc7: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 422dce: 0f 86 bc 06 00 00 jbe 423490 <__strcmp_sse42+0xd50> + 422dd4: 48 83 c2 10 add $0x10,%rdx + 422dd8: eb b6 jmp 422d90 <__strcmp_sse42+0x650> + 422dda: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 422de0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 422de7: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 + 422ded: 66 0f 73 d8 07 psrldq $0x7,%xmm0 + 422df2: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 + 422df8: 83 f9 08 cmp $0x8,%ecx + 422dfb: 77 99 ja 422d96 <__strcmp_sse42+0x656> + 422dfd: e9 7b 06 00 00 jmpq 42347d <__strcmp_sse42+0xd3d> + 422e02: 0f 1f 40 00 nopl 0x0(%rax) + 422e06: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 422e0d: 00 00 00 + 422e10: 66 0f 73 fa 08 pslldq $0x8,%xmm2 + 422e15: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 422e19: 66 0f f8 d0 psubb %xmm0,%xmm2 + 422e1d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 422e22: d3 ea shr %cl,%edx + 422e24: 41 d3 e9 shr %cl,%r9d + 422e27: 44 29 ca sub %r9d,%edx + 422e2a: 0f 85 7b 06 00 00 jne 4234ab <__strcmp_sse42+0xd6b> + 422e30: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 422e34: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 422e3b: 41 b9 08 00 00 00 mov $0x8,%r9d + 422e41: 4c 8d 57 08 lea 0x8(%rdi),%r10 + 422e45: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 422e4c: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 422e53: 48 89 ca mov %rcx,%rdx + 422e56: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 422e5d: 00 00 00 + 422e60: 49 83 c2 10 add $0x10,%r10 + 422e64: 7f 4a jg 422eb0 <__strcmp_sse42+0x770> + 422e66: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 422e6b: 66 0f 3a 0f 44 17 f0 palignr $0x8,-0x10(%rdi,%rdx,1),%xmm0 + 422e72: 08 + 422e73: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 422e7a: 0f 86 10 06 00 00 jbe 423490 <__strcmp_sse42+0xd50> + 422e80: 48 83 c2 10 add $0x10,%rdx + 422e84: 49 83 c2 10 add $0x10,%r10 + 422e88: 7f 26 jg 422eb0 <__strcmp_sse42+0x770> + 422e8a: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 422e8f: 66 0f 3a 0f 44 17 f0 palignr $0x8,-0x10(%rdi,%rdx,1),%xmm0 + 422e96: 08 + 422e97: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 422e9e: 0f 86 ec 05 00 00 jbe 423490 <__strcmp_sse42+0xd50> + 422ea4: 48 83 c2 10 add $0x10,%rdx + 422ea8: eb b6 jmp 422e60 <__strcmp_sse42+0x720> + 422eaa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 422eb0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 422eb7: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 + 422ebd: 66 0f 73 d8 08 psrldq $0x8,%xmm0 + 422ec2: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 + 422ec8: 83 f9 07 cmp $0x7,%ecx + 422ecb: 77 99 ja 422e66 <__strcmp_sse42+0x726> + 422ecd: e9 ab 05 00 00 jmpq 42347d <__strcmp_sse42+0xd3d> + 422ed2: 0f 1f 40 00 nopl 0x0(%rax) + 422ed6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 422edd: 00 00 00 + 422ee0: 66 0f 73 fa 07 pslldq $0x7,%xmm2 + 422ee5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 422ee9: 66 0f f8 d0 psubb %xmm0,%xmm2 + 422eed: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 422ef2: d3 ea shr %cl,%edx + 422ef4: 41 d3 e9 shr %cl,%r9d + 422ef7: 44 29 ca sub %r9d,%edx + 422efa: 0f 85 ab 05 00 00 jne 4234ab <__strcmp_sse42+0xd6b> + 422f00: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 422f04: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 422f0b: 41 b9 09 00 00 00 mov $0x9,%r9d + 422f11: 4c 8d 57 09 lea 0x9(%rdi),%r10 + 422f15: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 422f1c: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 422f23: 48 89 ca mov %rcx,%rdx + 422f26: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 422f2d: 00 00 00 + 422f30: 49 83 c2 10 add $0x10,%r10 + 422f34: 7f 4a jg 422f80 <__strcmp_sse42+0x840> + 422f36: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 422f3b: 66 0f 3a 0f 44 17 f0 palignr $0x9,-0x10(%rdi,%rdx,1),%xmm0 + 422f42: 09 + 422f43: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 422f4a: 0f 86 40 05 00 00 jbe 423490 <__strcmp_sse42+0xd50> + 422f50: 48 83 c2 10 add $0x10,%rdx + 422f54: 49 83 c2 10 add $0x10,%r10 + 422f58: 7f 26 jg 422f80 <__strcmp_sse42+0x840> + 422f5a: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 422f5f: 66 0f 3a 0f 44 17 f0 palignr $0x9,-0x10(%rdi,%rdx,1),%xmm0 + 422f66: 09 + 422f67: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 422f6e: 0f 86 1c 05 00 00 jbe 423490 <__strcmp_sse42+0xd50> + 422f74: 48 83 c2 10 add $0x10,%rdx + 422f78: eb b6 jmp 422f30 <__strcmp_sse42+0x7f0> + 422f7a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 422f80: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 422f87: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 + 422f8d: 66 0f 73 d8 09 psrldq $0x9,%xmm0 + 422f92: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 + 422f98: 83 f9 06 cmp $0x6,%ecx + 422f9b: 77 99 ja 422f36 <__strcmp_sse42+0x7f6> + 422f9d: e9 db 04 00 00 jmpq 42347d <__strcmp_sse42+0xd3d> + 422fa2: 0f 1f 40 00 nopl 0x0(%rax) + 422fa6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 422fad: 00 00 00 + 422fb0: 66 0f 73 fa 06 pslldq $0x6,%xmm2 + 422fb5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 422fb9: 66 0f f8 d0 psubb %xmm0,%xmm2 + 422fbd: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 422fc2: d3 ea shr %cl,%edx + 422fc4: 41 d3 e9 shr %cl,%r9d + 422fc7: 44 29 ca sub %r9d,%edx + 422fca: 0f 85 db 04 00 00 jne 4234ab <__strcmp_sse42+0xd6b> + 422fd0: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 422fd4: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 422fdb: 41 b9 0a 00 00 00 mov $0xa,%r9d + 422fe1: 4c 8d 57 0a lea 0xa(%rdi),%r10 + 422fe5: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 422fec: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 422ff3: 48 89 ca mov %rcx,%rdx + 422ff6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 422ffd: 00 00 00 + 423000: 49 83 c2 10 add $0x10,%r10 + 423004: 7f 4a jg 423050 <__strcmp_sse42+0x910> + 423006: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 42300b: 66 0f 3a 0f 44 17 f0 palignr $0xa,-0x10(%rdi,%rdx,1),%xmm0 + 423012: 0a + 423013: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 42301a: 0f 86 70 04 00 00 jbe 423490 <__strcmp_sse42+0xd50> + 423020: 48 83 c2 10 add $0x10,%rdx + 423024: 49 83 c2 10 add $0x10,%r10 + 423028: 7f 26 jg 423050 <__strcmp_sse42+0x910> + 42302a: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 42302f: 66 0f 3a 0f 44 17 f0 palignr $0xa,-0x10(%rdi,%rdx,1),%xmm0 + 423036: 0a + 423037: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 42303e: 0f 86 4c 04 00 00 jbe 423490 <__strcmp_sse42+0xd50> + 423044: 48 83 c2 10 add $0x10,%rdx + 423048: eb b6 jmp 423000 <__strcmp_sse42+0x8c0> + 42304a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 423050: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 423057: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 + 42305d: 66 0f 73 d8 0a psrldq $0xa,%xmm0 + 423062: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 + 423068: 83 f9 05 cmp $0x5,%ecx + 42306b: 77 99 ja 423006 <__strcmp_sse42+0x8c6> + 42306d: e9 0b 04 00 00 jmpq 42347d <__strcmp_sse42+0xd3d> + 423072: 0f 1f 40 00 nopl 0x0(%rax) + 423076: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42307d: 00 00 00 + 423080: 66 0f 73 fa 05 pslldq $0x5,%xmm2 + 423085: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 423089: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42308d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 423092: d3 ea shr %cl,%edx + 423094: 41 d3 e9 shr %cl,%r9d + 423097: 44 29 ca sub %r9d,%edx + 42309a: 0f 85 0b 04 00 00 jne 4234ab <__strcmp_sse42+0xd6b> + 4230a0: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 4230a4: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 4230ab: 41 b9 0b 00 00 00 mov $0xb,%r9d + 4230b1: 4c 8d 57 0b lea 0xb(%rdi),%r10 + 4230b5: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 4230bc: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 4230c3: 48 89 ca mov %rcx,%rdx + 4230c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4230cd: 00 00 00 + 4230d0: 49 83 c2 10 add $0x10,%r10 + 4230d4: 7f 4a jg 423120 <__strcmp_sse42+0x9e0> + 4230d6: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 4230db: 66 0f 3a 0f 44 17 f0 palignr $0xb,-0x10(%rdi,%rdx,1),%xmm0 + 4230e2: 0b + 4230e3: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 4230ea: 0f 86 a0 03 00 00 jbe 423490 <__strcmp_sse42+0xd50> + 4230f0: 48 83 c2 10 add $0x10,%rdx + 4230f4: 49 83 c2 10 add $0x10,%r10 + 4230f8: 7f 26 jg 423120 <__strcmp_sse42+0x9e0> + 4230fa: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 4230ff: 66 0f 3a 0f 44 17 f0 palignr $0xb,-0x10(%rdi,%rdx,1),%xmm0 + 423106: 0b + 423107: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 42310e: 0f 86 7c 03 00 00 jbe 423490 <__strcmp_sse42+0xd50> + 423114: 48 83 c2 10 add $0x10,%rdx + 423118: eb b6 jmp 4230d0 <__strcmp_sse42+0x990> + 42311a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 423120: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 423127: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 + 42312d: 66 0f 73 d8 0b psrldq $0xb,%xmm0 + 423132: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 + 423138: 83 f9 04 cmp $0x4,%ecx + 42313b: 77 99 ja 4230d6 <__strcmp_sse42+0x996> + 42313d: e9 3b 03 00 00 jmpq 42347d <__strcmp_sse42+0xd3d> + 423142: 0f 1f 40 00 nopl 0x0(%rax) + 423146: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42314d: 00 00 00 + 423150: 66 0f 73 fa 04 pslldq $0x4,%xmm2 + 423155: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 423159: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42315d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 423162: d3 ea shr %cl,%edx + 423164: 41 d3 e9 shr %cl,%r9d + 423167: 44 29 ca sub %r9d,%edx + 42316a: 0f 85 3b 03 00 00 jne 4234ab <__strcmp_sse42+0xd6b> + 423170: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 423174: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42317b: 41 b9 0c 00 00 00 mov $0xc,%r9d + 423181: 4c 8d 57 0c lea 0xc(%rdi),%r10 + 423185: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42318c: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 423193: 48 89 ca mov %rcx,%rdx + 423196: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42319d: 00 00 00 + 4231a0: 49 83 c2 10 add $0x10,%r10 + 4231a4: 7f 4a jg 4231f0 <__strcmp_sse42+0xab0> + 4231a6: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 4231ab: 66 0f 3a 0f 44 17 f0 palignr $0xc,-0x10(%rdi,%rdx,1),%xmm0 + 4231b2: 0c + 4231b3: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 4231ba: 0f 86 d0 02 00 00 jbe 423490 <__strcmp_sse42+0xd50> + 4231c0: 48 83 c2 10 add $0x10,%rdx + 4231c4: 49 83 c2 10 add $0x10,%r10 + 4231c8: 7f 26 jg 4231f0 <__strcmp_sse42+0xab0> + 4231ca: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 4231cf: 66 0f 3a 0f 44 17 f0 palignr $0xc,-0x10(%rdi,%rdx,1),%xmm0 + 4231d6: 0c + 4231d7: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 4231de: 0f 86 ac 02 00 00 jbe 423490 <__strcmp_sse42+0xd50> + 4231e4: 48 83 c2 10 add $0x10,%rdx + 4231e8: eb b6 jmp 4231a0 <__strcmp_sse42+0xa60> + 4231ea: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4231f0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 4231f7: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 + 4231fd: 66 0f 73 d8 0c psrldq $0xc,%xmm0 + 423202: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 + 423208: 83 f9 03 cmp $0x3,%ecx + 42320b: 77 99 ja 4231a6 <__strcmp_sse42+0xa66> + 42320d: e9 6b 02 00 00 jmpq 42347d <__strcmp_sse42+0xd3d> + 423212: 0f 1f 40 00 nopl 0x0(%rax) + 423216: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42321d: 00 00 00 + 423220: 66 0f 73 fa 03 pslldq $0x3,%xmm2 + 423225: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 423229: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42322d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 423232: d3 ea shr %cl,%edx + 423234: 41 d3 e9 shr %cl,%r9d + 423237: 44 29 ca sub %r9d,%edx + 42323a: 0f 85 6b 02 00 00 jne 4234ab <__strcmp_sse42+0xd6b> + 423240: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 423244: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42324b: 41 b9 0d 00 00 00 mov $0xd,%r9d + 423251: 4c 8d 57 0d lea 0xd(%rdi),%r10 + 423255: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42325c: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 423263: 48 89 ca mov %rcx,%rdx + 423266: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42326d: 00 00 00 + 423270: 49 83 c2 10 add $0x10,%r10 + 423274: 7f 4a jg 4232c0 <__strcmp_sse42+0xb80> + 423276: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 42327b: 66 0f 3a 0f 44 17 f0 palignr $0xd,-0x10(%rdi,%rdx,1),%xmm0 + 423282: 0d + 423283: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 42328a: 0f 86 00 02 00 00 jbe 423490 <__strcmp_sse42+0xd50> + 423290: 48 83 c2 10 add $0x10,%rdx + 423294: 49 83 c2 10 add $0x10,%r10 + 423298: 7f 26 jg 4232c0 <__strcmp_sse42+0xb80> + 42329a: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 42329f: 66 0f 3a 0f 44 17 f0 palignr $0xd,-0x10(%rdi,%rdx,1),%xmm0 + 4232a6: 0d + 4232a7: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 4232ae: 0f 86 dc 01 00 00 jbe 423490 <__strcmp_sse42+0xd50> + 4232b4: 48 83 c2 10 add $0x10,%rdx + 4232b8: eb b6 jmp 423270 <__strcmp_sse42+0xb30> + 4232ba: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4232c0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 4232c7: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 + 4232cd: 66 0f 73 d8 0d psrldq $0xd,%xmm0 + 4232d2: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 + 4232d8: 83 f9 02 cmp $0x2,%ecx + 4232db: 77 99 ja 423276 <__strcmp_sse42+0xb36> + 4232dd: e9 9b 01 00 00 jmpq 42347d <__strcmp_sse42+0xd3d> + 4232e2: 0f 1f 40 00 nopl 0x0(%rax) + 4232e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4232ed: 00 00 00 + 4232f0: 66 0f 73 fa 02 pslldq $0x2,%xmm2 + 4232f5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 4232f9: 66 0f f8 d0 psubb %xmm0,%xmm2 + 4232fd: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 423302: d3 ea shr %cl,%edx + 423304: 41 d3 e9 shr %cl,%r9d + 423307: 44 29 ca sub %r9d,%edx + 42330a: 0f 85 9b 01 00 00 jne 4234ab <__strcmp_sse42+0xd6b> + 423310: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 423314: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42331b: 41 b9 0e 00 00 00 mov $0xe,%r9d + 423321: 4c 8d 57 0e lea 0xe(%rdi),%r10 + 423325: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42332c: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 423333: 48 89 ca mov %rcx,%rdx + 423336: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42333d: 00 00 00 + 423340: 49 83 c2 10 add $0x10,%r10 + 423344: 7f 4a jg 423390 <__strcmp_sse42+0xc50> + 423346: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 42334b: 66 0f 3a 0f 44 17 f0 palignr $0xe,-0x10(%rdi,%rdx,1),%xmm0 + 423352: 0e + 423353: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 42335a: 0f 86 30 01 00 00 jbe 423490 <__strcmp_sse42+0xd50> + 423360: 48 83 c2 10 add $0x10,%rdx + 423364: 49 83 c2 10 add $0x10,%r10 + 423368: 7f 26 jg 423390 <__strcmp_sse42+0xc50> + 42336a: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 42336f: 66 0f 3a 0f 44 17 f0 palignr $0xe,-0x10(%rdi,%rdx,1),%xmm0 + 423376: 0e + 423377: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 42337e: 0f 86 0c 01 00 00 jbe 423490 <__strcmp_sse42+0xd50> + 423384: 48 83 c2 10 add $0x10,%rdx + 423388: eb b6 jmp 423340 <__strcmp_sse42+0xc00> + 42338a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 423390: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 423397: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 + 42339d: 66 0f 73 d8 0e psrldq $0xe,%xmm0 + 4233a2: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 + 4233a8: 83 f9 01 cmp $0x1,%ecx + 4233ab: 77 99 ja 423346 <__strcmp_sse42+0xc06> + 4233ad: e9 cb 00 00 00 jmpq 42347d <__strcmp_sse42+0xd3d> + 4233b2: 0f 1f 40 00 nopl 0x0(%rax) + 4233b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4233bd: 00 00 00 + 4233c0: 66 0f 73 fa 01 pslldq $0x1,%xmm2 + 4233c5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 4233c9: 66 0f f8 d0 psubb %xmm0,%xmm2 + 4233cd: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 4233d2: d3 ea shr %cl,%edx + 4233d4: 41 d3 e9 shr %cl,%r9d + 4233d7: 44 29 ca sub %r9d,%edx + 4233da: 0f 85 cb 00 00 00 jne 4234ab <__strcmp_sse42+0xd6b> + 4233e0: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 4233e4: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 4233eb: 41 b9 0f 00 00 00 mov $0xf,%r9d + 4233f1: 4c 8d 57 0f lea 0xf(%rdi),%r10 + 4233f5: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 4233fc: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 423403: 48 89 ca mov %rcx,%rdx + 423406: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42340d: 00 00 00 + 423410: 49 83 c2 10 add $0x10,%r10 + 423414: 7f 4a jg 423460 <__strcmp_sse42+0xd20> + 423416: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 42341b: 66 0f 3a 0f 44 17 f0 palignr $0xf,-0x10(%rdi,%rdx,1),%xmm0 + 423422: 0f + 423423: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 42342a: 76 64 jbe 423490 <__strcmp_sse42+0xd50> + 42342c: 48 83 c2 10 add $0x10,%rdx + 423430: 49 83 c2 10 add $0x10,%r10 + 423434: 7f 2a jg 423460 <__strcmp_sse42+0xd20> + 423436: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 42343b: 66 0f 3a 0f 44 17 f0 palignr $0xf,-0x10(%rdi,%rdx,1),%xmm0 + 423442: 0f + 423443: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 42344a: 76 44 jbe 423490 <__strcmp_sse42+0xd50> + 42344c: 48 83 c2 10 add $0x10,%rdx + 423450: eb be jmp 423410 <__strcmp_sse42+0xcd0> + 423452: 0f 1f 40 00 nopl 0x0(%rax) + 423456: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42345d: 00 00 00 + 423460: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 423467: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 + 42346d: 66 0f 73 d8 0f psrldq $0xf,%xmm0 + 423472: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 + 423478: 83 f9 00 cmp $0x0,%ecx + 42347b: 77 99 ja 423416 <__strcmp_sse42+0xcd6> + 42347d: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 + 423484: 66 90 xchg %ax,%ax + 423486: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42348d: 00 00 00 + 423490: 73 3d jae 4234cf <__strcmp_sse42+0xd8f> + 423492: 48 01 ca add %rcx,%rdx + 423495: 4a 8d 7c 0f f0 lea -0x10(%rdi,%r9,1),%rdi + 42349a: 0f b6 04 17 movzbl (%rdi,%rdx,1),%eax + 42349e: 0f b6 14 16 movzbl (%rsi,%rdx,1),%edx + 4234a2: 45 85 c0 test %r8d,%r8d + 4234a5: 74 01 je 4234a8 <__strcmp_sse42+0xd68> + 4234a7: 92 xchg %eax,%edx + 4234a8: 29 d0 sub %edx,%eax + 4234aa: c3 retq + 4234ab: 48 8d 3c 07 lea (%rdi,%rax,1),%rdi + 4234af: 48 8d 34 0e lea (%rsi,%rcx,1),%rsi + 4234b3: 45 85 c0 test %r8d,%r8d + 4234b6: 74 08 je 4234c0 <__strcmp_sse42+0xd80> + 4234b8: 48 87 f7 xchg %rsi,%rdi + 4234bb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4234c0: 48 0f bc d2 bsf %rdx,%rdx + 4234c4: 0f b6 0c 16 movzbl (%rsi,%rdx,1),%ecx + 4234c8: 0f b6 04 17 movzbl (%rdi,%rdx,1),%eax + 4234cc: 29 c8 sub %ecx,%eax + 4234ce: c3 retq + 4234cf: 31 c0 xor %eax,%eax + 4234d1: c3 retq + 4234d2: 0f 1f 40 00 nopl 0x0(%rax) + 4234d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4234dd: 00 00 00 + 4234e0: 0f b6 0e movzbl (%rsi),%ecx + 4234e3: 0f b6 07 movzbl (%rdi),%eax + 4234e6: 29 c8 sub %ecx,%eax + 4234e8: c3 retq + 4234e9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + +00000000004234f0 : + 4234f0: 48 8d 05 39 78 01 00 lea 0x17839(%rip),%rax # 43ad30 <__strcpy_sse2_unaligned> + 4234f7: f7 05 bf 91 2a 00 10 testl $0x10,0x2a91bf(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> + 4234fe: 00 00 00 + 423501: 75 1a jne 42351d + 423503: 48 8d 05 16 00 00 00 lea 0x16(%rip),%rax # 423520 <__GI_strcpy> + 42350a: f7 05 7c 91 2a 00 00 testl $0x200,0x2a917c(%rip) # 6cc690 <_dl_x86_cpu_features+0x10> + 423511: 02 00 00 + 423514: 74 07 je 42351d + 423516: 48 8d 05 53 48 01 00 lea 0x14853(%rip),%rax # 437d70 <__strcpy_ssse3> + 42351d: c3 retq + 42351e: 66 90 xchg %ax,%ax + +0000000000423520 <__GI_strcpy>: + 423520: 48 89 f1 mov %rsi,%rcx + 423523: 83 e1 07 and $0x7,%ecx + 423526: 48 89 fa mov %rdi,%rdx + 423529: 74 1b je 423546 <__GI_strcpy+0x26> + 42352b: f7 d9 neg %ecx + 42352d: 83 c1 08 add $0x8,%ecx + 423530: 8a 06 mov (%rsi),%al + 423532: 84 c0 test %al,%al + 423534: 88 02 mov %al,(%rdx) + 423536: 0f 84 bc 00 00 00 je 4235f8 <__GI_strcpy+0xd8> + 42353c: 48 ff c6 inc %rsi + 42353f: 48 ff c2 inc %rdx + 423542: ff c9 dec %ecx + 423544: 75 ea jne 423530 <__GI_strcpy+0x10> + 423546: 49 b8 ff fe fe fe fe movabs $0xfefefefefefefeff,%r8 + 42354d: fe fe fe + 423550: 48 8b 06 mov (%rsi),%rax + 423553: 48 83 c6 08 add $0x8,%rsi + 423557: 49 89 c1 mov %rax,%r9 + 42355a: 4d 01 c1 add %r8,%r9 + 42355d: 0f 83 7d 00 00 00 jae 4235e0 <__GI_strcpy+0xc0> + 423563: 49 31 c1 xor %rax,%r9 + 423566: 4d 09 c1 or %r8,%r9 + 423569: 49 ff c1 inc %r9 + 42356c: 75 72 jne 4235e0 <__GI_strcpy+0xc0> + 42356e: 48 89 02 mov %rax,(%rdx) + 423571: 48 83 c2 08 add $0x8,%rdx + 423575: 48 8b 06 mov (%rsi),%rax + 423578: 48 83 c6 08 add $0x8,%rsi + 42357c: 49 89 c1 mov %rax,%r9 + 42357f: 4d 01 c1 add %r8,%r9 + 423582: 73 5c jae 4235e0 <__GI_strcpy+0xc0> + 423584: 49 31 c1 xor %rax,%r9 + 423587: 4d 09 c1 or %r8,%r9 + 42358a: 49 ff c1 inc %r9 + 42358d: 75 51 jne 4235e0 <__GI_strcpy+0xc0> + 42358f: 48 89 02 mov %rax,(%rdx) + 423592: 48 83 c2 08 add $0x8,%rdx + 423596: 48 8b 06 mov (%rsi),%rax + 423599: 48 83 c6 08 add $0x8,%rsi + 42359d: 49 89 c1 mov %rax,%r9 + 4235a0: 4d 01 c1 add %r8,%r9 + 4235a3: 73 3b jae 4235e0 <__GI_strcpy+0xc0> + 4235a5: 49 31 c1 xor %rax,%r9 + 4235a8: 4d 09 c1 or %r8,%r9 + 4235ab: 49 ff c1 inc %r9 + 4235ae: 75 30 jne 4235e0 <__GI_strcpy+0xc0> + 4235b0: 48 89 02 mov %rax,(%rdx) + 4235b3: 48 83 c2 08 add $0x8,%rdx + 4235b7: 48 8b 06 mov (%rsi),%rax + 4235ba: 48 83 c6 08 add $0x8,%rsi + 4235be: 49 89 c1 mov %rax,%r9 + 4235c1: 4d 01 c1 add %r8,%r9 + 4235c4: 73 1a jae 4235e0 <__GI_strcpy+0xc0> + 4235c6: 49 31 c1 xor %rax,%r9 + 4235c9: 4d 09 c1 or %r8,%r9 + 4235cc: 49 ff c1 inc %r9 + 4235cf: 75 0f jne 4235e0 <__GI_strcpy+0xc0> + 4235d1: 48 89 02 mov %rax,(%rdx) + 4235d4: 48 83 c2 08 add $0x8,%rdx + 4235d8: e9 73 ff ff ff jmpq 423550 <__GI_strcpy+0x30> + 4235dd: 0f 1f 00 nopl (%rax) + 4235e0: 88 02 mov %al,(%rdx) + 4235e2: 84 c0 test %al,%al + 4235e4: 74 12 je 4235f8 <__GI_strcpy+0xd8> + 4235e6: 48 ff c2 inc %rdx + 4235e9: 88 22 mov %ah,(%rdx) + 4235eb: 84 e4 test %ah,%ah + 4235ed: 74 09 je 4235f8 <__GI_strcpy+0xd8> + 4235ef: 48 ff c2 inc %rdx + 4235f2: 48 c1 e8 10 shr $0x10,%rax + 4235f6: eb e8 jmp 4235e0 <__GI_strcpy+0xc0> + 4235f8: 48 89 f8 mov %rdi,%rax + 4235fb: c3 retq + 4235fc: 0f 1f 40 00 nopl 0x0(%rax) + +0000000000423600 <__strdup>: + 423600: 55 push %rbp + 423601: 53 push %rbx + 423602: 48 89 fd mov %rdi,%rbp + 423605: 48 83 ec 08 sub $0x8,%rsp + 423609: e8 42 00 00 00 callq 423650 + 42360e: 48 8d 58 01 lea 0x1(%rax),%rbx + 423612: 48 89 df mov %rbx,%rdi + 423615: e8 f6 a3 ff ff callq 41da10 <__libc_malloc> + 42361a: 48 85 c0 test %rax,%rax + 42361d: 74 19 je 423638 <__strdup+0x38> + 42361f: 48 83 c4 08 add $0x8,%rsp + 423623: 48 89 da mov %rbx,%rdx + 423626: 48 89 ee mov %rbp,%rsi + 423629: 5b pop %rbx + 42362a: 5d pop %rbp + 42362b: 48 89 c7 mov %rax,%rdi + 42362e: e9 ed 89 00 00 jmpq 42c020 + 423633: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 423638: 48 83 c4 08 add $0x8,%rsp + 42363c: 31 c0 xor %eax,%eax + 42363e: 5b pop %rbx + 42363f: 5d pop %rbp + 423640: c3 retq + 423641: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 423648: 00 00 00 + 42364b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + +0000000000423650 : + 423650: 66 0f ef c0 pxor %xmm0,%xmm0 + 423654: 66 0f ef c9 pxor %xmm1,%xmm1 + 423658: 66 0f ef d2 pxor %xmm2,%xmm2 + 42365c: 66 0f ef db pxor %xmm3,%xmm3 + 423660: 48 89 f8 mov %rdi,%rax + 423663: 48 89 f9 mov %rdi,%rcx + 423666: 48 81 e1 ff 0f 00 00 and $0xfff,%rcx + 42366d: 48 81 f9 cf 0f 00 00 cmp $0xfcf,%rcx + 423674: 77 6a ja 4236e0 + 423676: f3 0f 6f 20 movdqu (%rax),%xmm4 + 42367a: 66 0f 74 e0 pcmpeqb %xmm0,%xmm4 + 42367e: 66 0f d7 d4 pmovmskb %xmm4,%edx + 423682: 85 d2 test %edx,%edx + 423684: 74 04 je 42368a + 423686: 0f bc c2 bsf %edx,%eax + 423689: c3 retq + 42368a: 48 83 e0 f0 and $0xfffffffffffffff0,%rax + 42368e: 66 0f 74 48 10 pcmpeqb 0x10(%rax),%xmm1 + 423693: 66 0f 74 50 20 pcmpeqb 0x20(%rax),%xmm2 + 423698: 66 0f 74 58 30 pcmpeqb 0x30(%rax),%xmm3 + 42369d: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4236a1: 66 44 0f d7 c2 pmovmskb %xmm2,%r8d + 4236a6: 66 0f d7 cb pmovmskb %xmm3,%ecx + 4236aa: 48 c1 e2 10 shl $0x10,%rdx + 4236ae: 48 c1 e1 10 shl $0x10,%rcx + 4236b2: 4c 09 c1 or %r8,%rcx + 4236b5: 48 c1 e1 20 shl $0x20,%rcx + 4236b9: 48 09 ca or %rcx,%rdx + 4236bc: 48 89 f9 mov %rdi,%rcx + 4236bf: 48 31 c1 xor %rax,%rcx + 4236c2: 48 83 e0 c0 and $0xffffffffffffffc0,%rax + 4236c6: 48 d3 fa sar %cl,%rdx + 4236c9: 48 85 d2 test %rdx,%rdx + 4236cc: 0f 84 7e 00 00 00 je 423750 + 4236d2: 48 0f bc c2 bsf %rdx,%rax + 4236d6: c3 retq + 4236d7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 4236de: 00 00 + 4236e0: 48 83 e0 c0 and $0xffffffffffffffc0,%rax + 4236e4: 66 0f 74 00 pcmpeqb (%rax),%xmm0 + 4236e8: 66 0f 74 48 10 pcmpeqb 0x10(%rax),%xmm1 + 4236ed: 66 0f 74 50 20 pcmpeqb 0x20(%rax),%xmm2 + 4236f2: 66 0f 74 58 30 pcmpeqb 0x30(%rax),%xmm3 + 4236f7: 66 0f d7 f0 pmovmskb %xmm0,%esi + 4236fb: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4236ff: 66 44 0f d7 c2 pmovmskb %xmm2,%r8d + 423704: 66 0f d7 cb pmovmskb %xmm3,%ecx + 423708: 48 c1 e2 10 shl $0x10,%rdx + 42370c: 48 c1 e1 10 shl $0x10,%rcx + 423710: 48 09 f2 or %rsi,%rdx + 423713: 4c 09 c1 or %r8,%rcx + 423716: 48 c1 e1 20 shl $0x20,%rcx + 42371a: 48 09 ca or %rcx,%rdx + 42371d: 48 89 f9 mov %rdi,%rcx + 423720: 48 31 c1 xor %rax,%rcx + 423723: 48 83 e0 c0 and $0xffffffffffffffc0,%rax + 423727: 48 d3 fa sar %cl,%rdx + 42372a: 48 85 d2 test %rdx,%rdx + 42372d: 74 11 je 423740 + 42372f: 48 0f bc c2 bsf %rdx,%rax + 423733: c3 retq + 423734: 66 90 xchg %ax,%ax + 423736: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42373d: 00 00 00 + 423740: 66 0f ef c9 pxor %xmm1,%xmm1 + 423744: 66 0f ef d2 pxor %xmm2,%xmm2 + 423748: 66 0f ef db pxor %xmm3,%xmm3 + 42374c: 0f 1f 40 00 nopl 0x0(%rax) + 423750: 66 0f 6f 40 40 movdqa 0x40(%rax),%xmm0 + 423755: 66 0f da 40 50 pminub 0x50(%rax),%xmm0 + 42375a: 66 0f da 40 60 pminub 0x60(%rax),%xmm0 + 42375f: 66 0f da 40 70 pminub 0x70(%rax),%xmm0 + 423764: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 423768: 66 0f d7 d0 pmovmskb %xmm0,%edx + 42376c: 85 d2 test %edx,%edx + 42376e: 75 30 jne 4237a0 + 423770: 48 83 e8 80 sub $0xffffffffffffff80,%rax + 423774: 66 0f 6f 00 movdqa (%rax),%xmm0 + 423778: 66 0f da 40 10 pminub 0x10(%rax),%xmm0 + 42377d: 66 0f da 40 20 pminub 0x20(%rax),%xmm0 + 423782: 66 0f da 40 30 pminub 0x30(%rax),%xmm0 + 423787: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 42378b: 66 0f d7 d0 pmovmskb %xmm0,%edx + 42378f: 85 d2 test %edx,%edx + 423791: 75 11 jne 4237a4 + 423793: eb bb jmp 423750 + 423795: 90 nop + 423796: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42379d: 00 00 00 + 4237a0: 48 83 c0 40 add $0x40,%rax + 4237a4: 66 0f ef c0 pxor %xmm0,%xmm0 + 4237a8: 66 0f 74 00 pcmpeqb (%rax),%xmm0 + 4237ac: 66 0f 74 48 10 pcmpeqb 0x10(%rax),%xmm1 + 4237b1: 66 0f 74 50 20 pcmpeqb 0x20(%rax),%xmm2 + 4237b6: 66 0f 74 58 30 pcmpeqb 0x30(%rax),%xmm3 + 4237bb: 66 0f d7 f0 pmovmskb %xmm0,%esi + 4237bf: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4237c3: 66 44 0f d7 c2 pmovmskb %xmm2,%r8d + 4237c8: 66 0f d7 cb pmovmskb %xmm3,%ecx + 4237cc: 48 c1 e2 10 shl $0x10,%rdx + 4237d0: 48 c1 e1 10 shl $0x10,%rcx + 4237d4: 48 09 f2 or %rsi,%rdx + 4237d7: 4c 09 c1 or %r8,%rcx + 4237da: 48 c1 e1 20 shl $0x20,%rcx + 4237de: 48 09 ca or %rcx,%rdx + 4237e1: 48 0f bc d2 bsf %rdx,%rdx + 4237e5: 48 01 d0 add %rdx,%rax + 4237e8: 48 29 f8 sub %rdi,%rax + 4237eb: c3 retq + 4237ec: 0f 1f 40 00 nopl 0x0(%rax) + +00000000004237f0 : + 4237f0: 48 85 d2 test %rdx,%rdx + 4237f3: 0f 84 2b 18 00 00 je 425024 + 4237f9: 48 83 fa 01 cmp $0x1,%rdx + 4237fd: 0f 84 2d 18 00 00 je 425030 + 423803: 49 89 d3 mov %rdx,%r11 + 423806: 89 f1 mov %esi,%ecx + 423808: 89 f8 mov %edi,%eax + 42380a: 48 83 e1 3f and $0x3f,%rcx + 42380e: 48 83 e0 3f and $0x3f,%rax + 423812: 83 f9 30 cmp $0x30,%ecx + 423815: 77 49 ja 423860 + 423817: 83 f8 30 cmp $0x30,%eax + 42381a: 77 44 ja 423860 + 42381c: 66 0f 12 0f movlpd (%rdi),%xmm1 + 423820: 66 0f 12 16 movlpd (%rsi),%xmm2 + 423824: 66 0f 16 4f 08 movhpd 0x8(%rdi),%xmm1 + 423829: 66 0f 16 56 08 movhpd 0x8(%rsi),%xmm2 + 42382e: 66 0f ef c0 pxor %xmm0,%xmm0 + 423832: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 423836: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42383a: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42383e: 66 0f d7 d1 pmovmskb %xmm1,%edx + 423842: 81 ea ff ff 00 00 sub $0xffff,%edx + 423848: 0f 85 c2 17 00 00 jne 425010 + 42384e: 49 83 eb 10 sub $0x10,%r11 + 423852: 0f 86 cc 17 00 00 jbe 425024 + 423858: 48 83 c6 10 add $0x10,%rsi + 42385c: 48 83 c7 10 add $0x10,%rdi + 423860: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi + 423864: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi + 423868: ba ff ff 00 00 mov $0xffff,%edx + 42386d: 45 31 c0 xor %r8d,%r8d + 423870: 83 e1 0f and $0xf,%ecx + 423873: 83 e0 0f and $0xf,%eax + 423876: 39 c1 cmp %eax,%ecx + 423878: 74 26 je 4238a0 + 42387a: 77 07 ja 423883 + 42387c: 41 89 d0 mov %edx,%r8d + 42387f: 91 xchg %eax,%ecx + 423880: 48 87 f7 xchg %rsi,%rdi + 423883: 4c 8d 48 0f lea 0xf(%rax),%r9 + 423887: 49 29 c9 sub %rcx,%r9 + 42388a: 4c 8d 15 df f7 07 00 lea 0x7f7df(%rip),%r10 # 4a3070 <__func__.10972+0xb0> + 423891: 4f 63 0c 8a movslq (%r10,%r9,4),%r9 + 423895: 4f 8d 14 0a lea (%r10,%r9,1),%r10 + 423899: 41 ff e2 jmpq *%r10 + 42389c: 0f 1f 40 00 nopl 0x0(%rax) + 4238a0: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 4238a4: 66 0f ef c0 pxor %xmm0,%xmm0 + 4238a8: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4238ac: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 + 4238b0: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4238b4: 66 44 0f d7 c9 pmovmskb %xmm1,%r9d + 4238b9: d3 ea shr %cl,%edx + 4238bb: 41 d3 e9 shr %cl,%r9d + 4238be: 44 29 ca sub %r9d,%edx + 4238c1: 0f 85 2e 17 00 00 jne 424ff5 + 4238c7: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 + 4238cc: 4d 39 cb cmp %r9,%r11 + 4238cf: 0f 82 4f 17 00 00 jb 425024 + 4238d5: 4d 85 c9 test %r9,%r9 + 4238d8: 0f 84 46 17 00 00 je 425024 + 4238de: 4d 89 cb mov %r9,%r11 + 4238e1: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 4238e8: 49 c7 c1 10 00 00 00 mov $0x10,%r9 + 4238ef: 66 0f ef c0 pxor %xmm0,%xmm0 + 4238f3: 0f 1f 00 nopl (%rax) + 4238f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4238fd: 00 00 00 + 423900: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 423905: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42390a: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42390e: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 423912: 66 0f f8 c8 psubb %xmm0,%xmm1 + 423916: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42391a: 81 ea ff ff 00 00 sub $0xffff,%edx + 423920: 0f 85 ca 16 00 00 jne 424ff0 + 423926: 49 83 eb 10 sub $0x10,%r11 + 42392a: 0f 86 f4 16 00 00 jbe 425024 + 423930: 48 83 c1 10 add $0x10,%rcx + 423934: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 423939: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42393e: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 423942: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 423946: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42394a: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42394e: 81 ea ff ff 00 00 sub $0xffff,%edx + 423954: 0f 85 96 16 00 00 jne 424ff0 + 42395a: 49 83 eb 10 sub $0x10,%r11 + 42395e: 0f 86 c0 16 00 00 jbe 425024 + 423964: 48 83 c1 10 add $0x10,%rcx + 423968: eb 96 jmp 423900 + 42396a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 423970: 66 0f ef c0 pxor %xmm0,%xmm0 + 423974: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 423978: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42397c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 423980: 66 0f 73 fa 0f pslldq $0xf,%xmm2 + 423985: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 423989: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42398d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 423992: d3 ea shr %cl,%edx + 423994: 41 d3 e9 shr %cl,%r9d + 423997: 44 29 ca sub %r9d,%edx + 42399a: 0f 85 55 16 00 00 jne 424ff5 + 4239a0: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 4239a4: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 + 4239a9: 4d 39 cb cmp %r9,%r11 + 4239ac: 0f 82 72 16 00 00 jb 425024 + 4239b2: 4d 85 c9 test %r9,%r9 + 4239b5: 0f 84 69 16 00 00 je 425024 + 4239bb: 4d 89 cb mov %r9,%r11 + 4239be: 66 0f ef c0 pxor %xmm0,%xmm0 + 4239c2: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 4239c9: 41 b9 01 00 00 00 mov $0x1,%r9d + 4239cf: 4c 8d 57 01 lea 0x1(%rdi),%r10 + 4239d3: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 4239da: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 4239e1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4239e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4239ed: 00 00 00 + 4239f0: 49 83 c2 10 add $0x10,%r10 + 4239f4: 0f 8f a6 00 00 00 jg 423aa0 + 4239fa: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4239ff: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 423a04: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 423a08: 66 0f 73 db 01 psrldq $0x1,%xmm3 + 423a0d: 66 0f 73 fa 0f pslldq $0xf,%xmm2 + 423a12: 66 0f eb d3 por %xmm3,%xmm2 + 423a16: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 423a1a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 423a1e: 66 0f f8 c8 psubb %xmm0,%xmm1 + 423a22: 66 0f d7 d1 pmovmskb %xmm1,%edx + 423a26: 81 ea ff ff 00 00 sub $0xffff,%edx + 423a2c: 0f 85 be 15 00 00 jne 424ff0 + 423a32: 49 83 eb 10 sub $0x10,%r11 + 423a36: 0f 86 e8 15 00 00 jbe 425024 + 423a3c: 48 83 c1 10 add $0x10,%rcx + 423a40: 66 0f 6f dc movdqa %xmm4,%xmm3 + 423a44: 49 83 c2 10 add $0x10,%r10 + 423a48: 7f 56 jg 423aa0 + 423a4a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 423a4f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 423a54: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 423a58: 66 0f 73 db 01 psrldq $0x1,%xmm3 + 423a5d: 66 0f 73 fa 0f pslldq $0xf,%xmm2 + 423a62: 66 0f eb d3 por %xmm3,%xmm2 + 423a66: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 423a6a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 423a6e: 66 0f f8 c8 psubb %xmm0,%xmm1 + 423a72: 66 0f d7 d1 pmovmskb %xmm1,%edx + 423a76: 81 ea ff ff 00 00 sub $0xffff,%edx + 423a7c: 0f 85 6e 15 00 00 jne 424ff0 + 423a82: 49 83 eb 10 sub $0x10,%r11 + 423a86: 0f 86 98 15 00 00 jbe 425024 + 423a8c: 48 83 c1 10 add $0x10,%rcx + 423a90: 66 0f 6f dc movdqa %xmm4,%xmm3 + 423a94: e9 57 ff ff ff jmpq 4239f0 + 423a99: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 423aa0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 423aa4: 66 0f d7 d0 pmovmskb %xmm0,%edx + 423aa8: f7 c2 fe ff 00 00 test $0xfffe,%edx + 423aae: 75 20 jne 423ad0 + 423ab0: 49 83 fb 0f cmp $0xf,%r11 + 423ab4: 76 1a jbe 423ad0 + 423ab6: 66 0f ef c0 pxor %xmm0,%xmm0 + 423aba: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 423ac1: e9 34 ff ff ff jmpq 4239fa + 423ac6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 423acd: 00 00 00 + 423ad0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 423ad5: 66 0f 73 d8 01 psrldq $0x1,%xmm0 + 423ada: 66 0f 73 db 01 psrldq $0x1,%xmm3 + 423adf: e9 fc 14 00 00 jmpq 424fe0 + 423ae4: 66 90 xchg %ax,%ax + 423ae6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 423aed: 00 00 00 + 423af0: 66 0f ef c0 pxor %xmm0,%xmm0 + 423af4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 423af8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 423afc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 423b00: 66 0f 73 fa 0e pslldq $0xe,%xmm2 + 423b05: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 423b09: 66 0f f8 d0 psubb %xmm0,%xmm2 + 423b0d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 423b12: d3 ea shr %cl,%edx + 423b14: 41 d3 e9 shr %cl,%r9d + 423b17: 44 29 ca sub %r9d,%edx + 423b1a: 0f 85 d5 14 00 00 jne 424ff5 + 423b20: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 423b24: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 + 423b29: 4d 39 cb cmp %r9,%r11 + 423b2c: 0f 82 f2 14 00 00 jb 425024 + 423b32: 4d 85 c9 test %r9,%r9 + 423b35: 0f 84 e9 14 00 00 je 425024 + 423b3b: 4d 89 cb mov %r9,%r11 + 423b3e: 66 0f ef c0 pxor %xmm0,%xmm0 + 423b42: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 423b49: 41 b9 02 00 00 00 mov $0x2,%r9d + 423b4f: 4c 8d 57 02 lea 0x2(%rdi),%r10 + 423b53: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 423b5a: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 423b61: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 423b66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 423b6d: 00 00 00 + 423b70: 49 83 c2 10 add $0x10,%r10 + 423b74: 0f 8f a6 00 00 00 jg 423c20 + 423b7a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 423b7f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 423b84: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 423b88: 66 0f 73 db 02 psrldq $0x2,%xmm3 + 423b8d: 66 0f 73 fa 0e pslldq $0xe,%xmm2 + 423b92: 66 0f eb d3 por %xmm3,%xmm2 + 423b96: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 423b9a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 423b9e: 66 0f f8 c8 psubb %xmm0,%xmm1 + 423ba2: 66 0f d7 d1 pmovmskb %xmm1,%edx + 423ba6: 81 ea ff ff 00 00 sub $0xffff,%edx + 423bac: 0f 85 3e 14 00 00 jne 424ff0 + 423bb2: 49 83 eb 10 sub $0x10,%r11 + 423bb6: 0f 86 68 14 00 00 jbe 425024 + 423bbc: 48 83 c1 10 add $0x10,%rcx + 423bc0: 66 0f 6f dc movdqa %xmm4,%xmm3 + 423bc4: 49 83 c2 10 add $0x10,%r10 + 423bc8: 7f 56 jg 423c20 + 423bca: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 423bcf: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 423bd4: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 423bd8: 66 0f 73 db 02 psrldq $0x2,%xmm3 + 423bdd: 66 0f 73 fa 0e pslldq $0xe,%xmm2 + 423be2: 66 0f eb d3 por %xmm3,%xmm2 + 423be6: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 423bea: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 423bee: 66 0f f8 c8 psubb %xmm0,%xmm1 + 423bf2: 66 0f d7 d1 pmovmskb %xmm1,%edx + 423bf6: 81 ea ff ff 00 00 sub $0xffff,%edx + 423bfc: 0f 85 ee 13 00 00 jne 424ff0 + 423c02: 49 83 eb 10 sub $0x10,%r11 + 423c06: 0f 86 18 14 00 00 jbe 425024 + 423c0c: 48 83 c1 10 add $0x10,%rcx + 423c10: 66 0f 6f dc movdqa %xmm4,%xmm3 + 423c14: e9 57 ff ff ff jmpq 423b70 + 423c19: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 423c20: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 423c24: 66 0f d7 d0 pmovmskb %xmm0,%edx + 423c28: f7 c2 fc ff 00 00 test $0xfffc,%edx + 423c2e: 75 20 jne 423c50 + 423c30: 49 83 fb 0e cmp $0xe,%r11 + 423c34: 76 1a jbe 423c50 + 423c36: 66 0f ef c0 pxor %xmm0,%xmm0 + 423c3a: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 423c41: e9 34 ff ff ff jmpq 423b7a + 423c46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 423c4d: 00 00 00 + 423c50: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 423c55: 66 0f 73 d8 02 psrldq $0x2,%xmm0 + 423c5a: 66 0f 73 db 02 psrldq $0x2,%xmm3 + 423c5f: e9 7c 13 00 00 jmpq 424fe0 + 423c64: 66 90 xchg %ax,%ax + 423c66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 423c6d: 00 00 00 + 423c70: 66 0f ef c0 pxor %xmm0,%xmm0 + 423c74: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 423c78: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 423c7c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 423c80: 66 0f 73 fa 0d pslldq $0xd,%xmm2 + 423c85: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 423c89: 66 0f f8 d0 psubb %xmm0,%xmm2 + 423c8d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 423c92: d3 ea shr %cl,%edx + 423c94: 41 d3 e9 shr %cl,%r9d + 423c97: 44 29 ca sub %r9d,%edx + 423c9a: 0f 85 55 13 00 00 jne 424ff5 + 423ca0: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 423ca4: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 + 423ca9: 4d 39 cb cmp %r9,%r11 + 423cac: 0f 82 72 13 00 00 jb 425024 + 423cb2: 4d 85 c9 test %r9,%r9 + 423cb5: 0f 84 69 13 00 00 je 425024 + 423cbb: 4d 89 cb mov %r9,%r11 + 423cbe: 66 0f ef c0 pxor %xmm0,%xmm0 + 423cc2: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 423cc9: 41 b9 03 00 00 00 mov $0x3,%r9d + 423ccf: 4c 8d 57 03 lea 0x3(%rdi),%r10 + 423cd3: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 423cda: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 423ce1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 423ce6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 423ced: 00 00 00 + 423cf0: 49 83 c2 10 add $0x10,%r10 + 423cf4: 0f 8f a6 00 00 00 jg 423da0 + 423cfa: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 423cff: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 423d04: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 423d08: 66 0f 73 db 03 psrldq $0x3,%xmm3 + 423d0d: 66 0f 73 fa 0d pslldq $0xd,%xmm2 + 423d12: 66 0f eb d3 por %xmm3,%xmm2 + 423d16: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 423d1a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 423d1e: 66 0f f8 c8 psubb %xmm0,%xmm1 + 423d22: 66 0f d7 d1 pmovmskb %xmm1,%edx + 423d26: 81 ea ff ff 00 00 sub $0xffff,%edx + 423d2c: 0f 85 be 12 00 00 jne 424ff0 + 423d32: 49 83 eb 10 sub $0x10,%r11 + 423d36: 0f 86 e8 12 00 00 jbe 425024 + 423d3c: 48 83 c1 10 add $0x10,%rcx + 423d40: 66 0f 6f dc movdqa %xmm4,%xmm3 + 423d44: 49 83 c2 10 add $0x10,%r10 + 423d48: 7f 56 jg 423da0 + 423d4a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 423d4f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 423d54: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 423d58: 66 0f 73 db 03 psrldq $0x3,%xmm3 + 423d5d: 66 0f 73 fa 0d pslldq $0xd,%xmm2 + 423d62: 66 0f eb d3 por %xmm3,%xmm2 + 423d66: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 423d6a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 423d6e: 66 0f f8 c8 psubb %xmm0,%xmm1 + 423d72: 66 0f d7 d1 pmovmskb %xmm1,%edx + 423d76: 81 ea ff ff 00 00 sub $0xffff,%edx + 423d7c: 0f 85 6e 12 00 00 jne 424ff0 + 423d82: 49 83 eb 10 sub $0x10,%r11 + 423d86: 0f 86 98 12 00 00 jbe 425024 + 423d8c: 48 83 c1 10 add $0x10,%rcx + 423d90: 66 0f 6f dc movdqa %xmm4,%xmm3 + 423d94: e9 57 ff ff ff jmpq 423cf0 + 423d99: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 423da0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 423da4: 66 0f d7 d0 pmovmskb %xmm0,%edx + 423da8: f7 c2 f8 ff 00 00 test $0xfff8,%edx + 423dae: 75 20 jne 423dd0 + 423db0: 49 83 fb 0d cmp $0xd,%r11 + 423db4: 76 1a jbe 423dd0 + 423db6: 66 0f ef c0 pxor %xmm0,%xmm0 + 423dba: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 423dc1: e9 34 ff ff ff jmpq 423cfa + 423dc6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 423dcd: 00 00 00 + 423dd0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 423dd5: 66 0f 73 d8 03 psrldq $0x3,%xmm0 + 423dda: 66 0f 73 db 03 psrldq $0x3,%xmm3 + 423ddf: e9 fc 11 00 00 jmpq 424fe0 + 423de4: 66 90 xchg %ax,%ax + 423de6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 423ded: 00 00 00 + 423df0: 66 0f ef c0 pxor %xmm0,%xmm0 + 423df4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 423df8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 423dfc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 423e00: 66 0f 73 fa 0c pslldq $0xc,%xmm2 + 423e05: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 423e09: 66 0f f8 d0 psubb %xmm0,%xmm2 + 423e0d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 423e12: d3 ea shr %cl,%edx + 423e14: 41 d3 e9 shr %cl,%r9d + 423e17: 44 29 ca sub %r9d,%edx + 423e1a: 0f 85 d5 11 00 00 jne 424ff5 + 423e20: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 423e24: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 + 423e29: 4d 39 cb cmp %r9,%r11 + 423e2c: 0f 82 f2 11 00 00 jb 425024 + 423e32: 4d 85 c9 test %r9,%r9 + 423e35: 0f 84 e9 11 00 00 je 425024 + 423e3b: 4d 89 cb mov %r9,%r11 + 423e3e: 66 0f ef c0 pxor %xmm0,%xmm0 + 423e42: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 423e49: 41 b9 04 00 00 00 mov $0x4,%r9d + 423e4f: 4c 8d 57 04 lea 0x4(%rdi),%r10 + 423e53: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 423e5a: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 423e61: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 423e66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 423e6d: 00 00 00 + 423e70: 49 83 c2 10 add $0x10,%r10 + 423e74: 0f 8f a6 00 00 00 jg 423f20 + 423e7a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 423e7f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 423e84: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 423e88: 66 0f 73 db 04 psrldq $0x4,%xmm3 + 423e8d: 66 0f 73 fa 0c pslldq $0xc,%xmm2 + 423e92: 66 0f eb d3 por %xmm3,%xmm2 + 423e96: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 423e9a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 423e9e: 66 0f f8 c8 psubb %xmm0,%xmm1 + 423ea2: 66 0f d7 d1 pmovmskb %xmm1,%edx + 423ea6: 81 ea ff ff 00 00 sub $0xffff,%edx + 423eac: 0f 85 3e 11 00 00 jne 424ff0 + 423eb2: 49 83 eb 10 sub $0x10,%r11 + 423eb6: 0f 86 68 11 00 00 jbe 425024 + 423ebc: 48 83 c1 10 add $0x10,%rcx + 423ec0: 66 0f 6f dc movdqa %xmm4,%xmm3 + 423ec4: 49 83 c2 10 add $0x10,%r10 + 423ec8: 7f 56 jg 423f20 + 423eca: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 423ecf: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 423ed4: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 423ed8: 66 0f 73 db 04 psrldq $0x4,%xmm3 + 423edd: 66 0f 73 fa 0c pslldq $0xc,%xmm2 + 423ee2: 66 0f eb d3 por %xmm3,%xmm2 + 423ee6: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 423eea: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 423eee: 66 0f f8 c8 psubb %xmm0,%xmm1 + 423ef2: 66 0f d7 d1 pmovmskb %xmm1,%edx + 423ef6: 81 ea ff ff 00 00 sub $0xffff,%edx + 423efc: 0f 85 ee 10 00 00 jne 424ff0 + 423f02: 49 83 eb 10 sub $0x10,%r11 + 423f06: 0f 86 18 11 00 00 jbe 425024 + 423f0c: 48 83 c1 10 add $0x10,%rcx + 423f10: 66 0f 6f dc movdqa %xmm4,%xmm3 + 423f14: e9 57 ff ff ff jmpq 423e70 + 423f19: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 423f20: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 423f24: 66 0f d7 d0 pmovmskb %xmm0,%edx + 423f28: f7 c2 f0 ff 00 00 test $0xfff0,%edx + 423f2e: 75 20 jne 423f50 + 423f30: 49 83 fb 0c cmp $0xc,%r11 + 423f34: 76 1a jbe 423f50 + 423f36: 66 0f ef c0 pxor %xmm0,%xmm0 + 423f3a: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 423f41: e9 34 ff ff ff jmpq 423e7a + 423f46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 423f4d: 00 00 00 + 423f50: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 423f55: 66 0f 73 d8 04 psrldq $0x4,%xmm0 + 423f5a: 66 0f 73 db 04 psrldq $0x4,%xmm3 + 423f5f: e9 7c 10 00 00 jmpq 424fe0 + 423f64: 66 90 xchg %ax,%ax + 423f66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 423f6d: 00 00 00 + 423f70: 66 0f ef c0 pxor %xmm0,%xmm0 + 423f74: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 423f78: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 423f7c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 423f80: 66 0f 73 fa 0b pslldq $0xb,%xmm2 + 423f85: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 423f89: 66 0f f8 d0 psubb %xmm0,%xmm2 + 423f8d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 423f92: d3 ea shr %cl,%edx + 423f94: 41 d3 e9 shr %cl,%r9d + 423f97: 44 29 ca sub %r9d,%edx + 423f9a: 0f 85 55 10 00 00 jne 424ff5 + 423fa0: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 423fa4: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 + 423fa9: 4d 39 cb cmp %r9,%r11 + 423fac: 0f 82 72 10 00 00 jb 425024 + 423fb2: 4d 85 c9 test %r9,%r9 + 423fb5: 0f 84 69 10 00 00 je 425024 + 423fbb: 4d 89 cb mov %r9,%r11 + 423fbe: 66 0f ef c0 pxor %xmm0,%xmm0 + 423fc2: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 423fc9: 41 b9 05 00 00 00 mov $0x5,%r9d + 423fcf: 4c 8d 57 05 lea 0x5(%rdi),%r10 + 423fd3: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 423fda: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 423fe1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 423fe6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 423fed: 00 00 00 + 423ff0: 49 83 c2 10 add $0x10,%r10 + 423ff4: 0f 8f a6 00 00 00 jg 4240a0 + 423ffa: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 423fff: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 424004: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 424008: 66 0f 73 db 05 psrldq $0x5,%xmm3 + 42400d: 66 0f 73 fa 0b pslldq $0xb,%xmm2 + 424012: 66 0f eb d3 por %xmm3,%xmm2 + 424016: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42401a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42401e: 66 0f f8 c8 psubb %xmm0,%xmm1 + 424022: 66 0f d7 d1 pmovmskb %xmm1,%edx + 424026: 81 ea ff ff 00 00 sub $0xffff,%edx + 42402c: 0f 85 be 0f 00 00 jne 424ff0 + 424032: 49 83 eb 10 sub $0x10,%r11 + 424036: 0f 86 e8 0f 00 00 jbe 425024 + 42403c: 48 83 c1 10 add $0x10,%rcx + 424040: 66 0f 6f dc movdqa %xmm4,%xmm3 + 424044: 49 83 c2 10 add $0x10,%r10 + 424048: 7f 56 jg 4240a0 + 42404a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42404f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 424054: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 424058: 66 0f 73 db 05 psrldq $0x5,%xmm3 + 42405d: 66 0f 73 fa 0b pslldq $0xb,%xmm2 + 424062: 66 0f eb d3 por %xmm3,%xmm2 + 424066: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42406a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42406e: 66 0f f8 c8 psubb %xmm0,%xmm1 + 424072: 66 0f d7 d1 pmovmskb %xmm1,%edx + 424076: 81 ea ff ff 00 00 sub $0xffff,%edx + 42407c: 0f 85 6e 0f 00 00 jne 424ff0 + 424082: 49 83 eb 10 sub $0x10,%r11 + 424086: 0f 86 98 0f 00 00 jbe 425024 + 42408c: 48 83 c1 10 add $0x10,%rcx + 424090: 66 0f 6f dc movdqa %xmm4,%xmm3 + 424094: e9 57 ff ff ff jmpq 423ff0 + 424099: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4240a0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 4240a4: 66 0f d7 d0 pmovmskb %xmm0,%edx + 4240a8: f7 c2 e0 ff 00 00 test $0xffe0,%edx + 4240ae: 75 20 jne 4240d0 + 4240b0: 49 83 fb 0b cmp $0xb,%r11 + 4240b4: 76 1a jbe 4240d0 + 4240b6: 66 0f ef c0 pxor %xmm0,%xmm0 + 4240ba: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 4240c1: e9 34 ff ff ff jmpq 423ffa + 4240c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4240cd: 00 00 00 + 4240d0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4240d5: 66 0f 73 d8 05 psrldq $0x5,%xmm0 + 4240da: 66 0f 73 db 05 psrldq $0x5,%xmm3 + 4240df: e9 fc 0e 00 00 jmpq 424fe0 + 4240e4: 66 90 xchg %ax,%ax + 4240e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4240ed: 00 00 00 + 4240f0: 66 0f ef c0 pxor %xmm0,%xmm0 + 4240f4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 4240f8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 4240fc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 424100: 66 0f 73 fa 0a pslldq $0xa,%xmm2 + 424105: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 424109: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42410d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 424112: d3 ea shr %cl,%edx + 424114: 41 d3 e9 shr %cl,%r9d + 424117: 44 29 ca sub %r9d,%edx + 42411a: 0f 85 d5 0e 00 00 jne 424ff5 + 424120: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 424124: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 + 424129: 4d 39 cb cmp %r9,%r11 + 42412c: 0f 82 f2 0e 00 00 jb 425024 + 424132: 4d 85 c9 test %r9,%r9 + 424135: 0f 84 e9 0e 00 00 je 425024 + 42413b: 4d 89 cb mov %r9,%r11 + 42413e: 66 0f ef c0 pxor %xmm0,%xmm0 + 424142: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 424149: 41 b9 06 00 00 00 mov $0x6,%r9d + 42414f: 4c 8d 57 06 lea 0x6(%rdi),%r10 + 424153: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42415a: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 424161: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 424166: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42416d: 00 00 00 + 424170: 49 83 c2 10 add $0x10,%r10 + 424174: 0f 8f a6 00 00 00 jg 424220 + 42417a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42417f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 424184: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 424188: 66 0f 73 db 06 psrldq $0x6,%xmm3 + 42418d: 66 0f 73 fa 0a pslldq $0xa,%xmm2 + 424192: 66 0f eb d3 por %xmm3,%xmm2 + 424196: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42419a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42419e: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4241a2: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4241a6: 81 ea ff ff 00 00 sub $0xffff,%edx + 4241ac: 0f 85 3e 0e 00 00 jne 424ff0 + 4241b2: 49 83 eb 10 sub $0x10,%r11 + 4241b6: 0f 86 68 0e 00 00 jbe 425024 + 4241bc: 48 83 c1 10 add $0x10,%rcx + 4241c0: 66 0f 6f dc movdqa %xmm4,%xmm3 + 4241c4: 49 83 c2 10 add $0x10,%r10 + 4241c8: 7f 56 jg 424220 + 4241ca: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4241cf: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4241d4: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 4241d8: 66 0f 73 db 06 psrldq $0x6,%xmm3 + 4241dd: 66 0f 73 fa 0a pslldq $0xa,%xmm2 + 4241e2: 66 0f eb d3 por %xmm3,%xmm2 + 4241e6: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4241ea: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 4241ee: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4241f2: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4241f6: 81 ea ff ff 00 00 sub $0xffff,%edx + 4241fc: 0f 85 ee 0d 00 00 jne 424ff0 + 424202: 49 83 eb 10 sub $0x10,%r11 + 424206: 0f 86 18 0e 00 00 jbe 425024 + 42420c: 48 83 c1 10 add $0x10,%rcx + 424210: 66 0f 6f dc movdqa %xmm4,%xmm3 + 424214: e9 57 ff ff ff jmpq 424170 + 424219: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 424220: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 424224: 66 0f d7 d0 pmovmskb %xmm0,%edx + 424228: f7 c2 c0 ff 00 00 test $0xffc0,%edx + 42422e: 75 20 jne 424250 + 424230: 49 83 fb 0a cmp $0xa,%r11 + 424234: 76 1a jbe 424250 + 424236: 66 0f ef c0 pxor %xmm0,%xmm0 + 42423a: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 424241: e9 34 ff ff ff jmpq 42417a + 424246: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42424d: 00 00 00 + 424250: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 424255: 66 0f 73 d8 06 psrldq $0x6,%xmm0 + 42425a: 66 0f 73 db 06 psrldq $0x6,%xmm3 + 42425f: e9 7c 0d 00 00 jmpq 424fe0 + 424264: 66 90 xchg %ax,%ax + 424266: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42426d: 00 00 00 + 424270: 66 0f ef c0 pxor %xmm0,%xmm0 + 424274: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 424278: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42427c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 424280: 66 0f 73 fa 09 pslldq $0x9,%xmm2 + 424285: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 424289: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42428d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 424292: d3 ea shr %cl,%edx + 424294: 41 d3 e9 shr %cl,%r9d + 424297: 44 29 ca sub %r9d,%edx + 42429a: 0f 85 55 0d 00 00 jne 424ff5 + 4242a0: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 4242a4: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 + 4242a9: 4d 39 cb cmp %r9,%r11 + 4242ac: 0f 82 72 0d 00 00 jb 425024 + 4242b2: 4d 85 c9 test %r9,%r9 + 4242b5: 0f 84 69 0d 00 00 je 425024 + 4242bb: 4d 89 cb mov %r9,%r11 + 4242be: 66 0f ef c0 pxor %xmm0,%xmm0 + 4242c2: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 4242c9: 41 b9 07 00 00 00 mov $0x7,%r9d + 4242cf: 4c 8d 57 07 lea 0x7(%rdi),%r10 + 4242d3: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 4242da: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 4242e1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4242e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4242ed: 00 00 00 + 4242f0: 49 83 c2 10 add $0x10,%r10 + 4242f4: 0f 8f a6 00 00 00 jg 4243a0 + 4242fa: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4242ff: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 424304: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 424308: 66 0f 73 db 07 psrldq $0x7,%xmm3 + 42430d: 66 0f 73 fa 09 pslldq $0x9,%xmm2 + 424312: 66 0f eb d3 por %xmm3,%xmm2 + 424316: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42431a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42431e: 66 0f f8 c8 psubb %xmm0,%xmm1 + 424322: 66 0f d7 d1 pmovmskb %xmm1,%edx + 424326: 81 ea ff ff 00 00 sub $0xffff,%edx + 42432c: 0f 85 be 0c 00 00 jne 424ff0 + 424332: 49 83 eb 10 sub $0x10,%r11 + 424336: 0f 86 e8 0c 00 00 jbe 425024 + 42433c: 48 83 c1 10 add $0x10,%rcx + 424340: 66 0f 6f dc movdqa %xmm4,%xmm3 + 424344: 49 83 c2 10 add $0x10,%r10 + 424348: 7f 56 jg 4243a0 + 42434a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42434f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 424354: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 424358: 66 0f 73 db 07 psrldq $0x7,%xmm3 + 42435d: 66 0f 73 fa 09 pslldq $0x9,%xmm2 + 424362: 66 0f eb d3 por %xmm3,%xmm2 + 424366: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42436a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42436e: 66 0f f8 c8 psubb %xmm0,%xmm1 + 424372: 66 0f d7 d1 pmovmskb %xmm1,%edx + 424376: 81 ea ff ff 00 00 sub $0xffff,%edx + 42437c: 0f 85 6e 0c 00 00 jne 424ff0 + 424382: 49 83 eb 10 sub $0x10,%r11 + 424386: 0f 86 98 0c 00 00 jbe 425024 + 42438c: 48 83 c1 10 add $0x10,%rcx + 424390: 66 0f 6f dc movdqa %xmm4,%xmm3 + 424394: e9 57 ff ff ff jmpq 4242f0 + 424399: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4243a0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 4243a4: 66 0f d7 d0 pmovmskb %xmm0,%edx + 4243a8: f7 c2 80 ff 00 00 test $0xff80,%edx + 4243ae: 75 20 jne 4243d0 + 4243b0: 49 83 fb 09 cmp $0x9,%r11 + 4243b4: 76 1a jbe 4243d0 + 4243b6: 66 0f ef c0 pxor %xmm0,%xmm0 + 4243ba: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 4243c1: e9 34 ff ff ff jmpq 4242fa + 4243c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4243cd: 00 00 00 + 4243d0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4243d5: 66 0f 73 d8 07 psrldq $0x7,%xmm0 + 4243da: 66 0f 73 db 07 psrldq $0x7,%xmm3 + 4243df: e9 fc 0b 00 00 jmpq 424fe0 + 4243e4: 66 90 xchg %ax,%ax + 4243e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4243ed: 00 00 00 + 4243f0: 66 0f ef c0 pxor %xmm0,%xmm0 + 4243f4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 4243f8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 4243fc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 424400: 66 0f 73 fa 08 pslldq $0x8,%xmm2 + 424405: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 424409: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42440d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 424412: d3 ea shr %cl,%edx + 424414: 41 d3 e9 shr %cl,%r9d + 424417: 44 29 ca sub %r9d,%edx + 42441a: 0f 85 d5 0b 00 00 jne 424ff5 + 424420: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 424424: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 + 424429: 4d 39 cb cmp %r9,%r11 + 42442c: 0f 82 f2 0b 00 00 jb 425024 + 424432: 4d 85 c9 test %r9,%r9 + 424435: 0f 84 e9 0b 00 00 je 425024 + 42443b: 4d 89 cb mov %r9,%r11 + 42443e: 66 0f ef c0 pxor %xmm0,%xmm0 + 424442: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 424449: 41 b9 08 00 00 00 mov $0x8,%r9d + 42444f: 4c 8d 57 08 lea 0x8(%rdi),%r10 + 424453: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42445a: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 424461: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 424466: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42446d: 00 00 00 + 424470: 49 83 c2 10 add $0x10,%r10 + 424474: 0f 8f a6 00 00 00 jg 424520 + 42447a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42447f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 424484: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 424488: 66 0f 73 db 08 psrldq $0x8,%xmm3 + 42448d: 66 0f 73 fa 08 pslldq $0x8,%xmm2 + 424492: 66 0f eb d3 por %xmm3,%xmm2 + 424496: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42449a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42449e: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4244a2: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4244a6: 81 ea ff ff 00 00 sub $0xffff,%edx + 4244ac: 0f 85 3e 0b 00 00 jne 424ff0 + 4244b2: 49 83 eb 10 sub $0x10,%r11 + 4244b6: 0f 86 68 0b 00 00 jbe 425024 + 4244bc: 48 83 c1 10 add $0x10,%rcx + 4244c0: 66 0f 6f dc movdqa %xmm4,%xmm3 + 4244c4: 49 83 c2 10 add $0x10,%r10 + 4244c8: 7f 56 jg 424520 + 4244ca: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4244cf: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4244d4: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 4244d8: 66 0f 73 db 08 psrldq $0x8,%xmm3 + 4244dd: 66 0f 73 fa 08 pslldq $0x8,%xmm2 + 4244e2: 66 0f eb d3 por %xmm3,%xmm2 + 4244e6: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4244ea: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 4244ee: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4244f2: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4244f6: 81 ea ff ff 00 00 sub $0xffff,%edx + 4244fc: 0f 85 ee 0a 00 00 jne 424ff0 + 424502: 49 83 eb 10 sub $0x10,%r11 + 424506: 0f 86 18 0b 00 00 jbe 425024 + 42450c: 48 83 c1 10 add $0x10,%rcx + 424510: 66 0f 6f dc movdqa %xmm4,%xmm3 + 424514: e9 57 ff ff ff jmpq 424470 + 424519: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 424520: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 424524: 66 0f d7 d0 pmovmskb %xmm0,%edx + 424528: f7 c2 00 ff 00 00 test $0xff00,%edx + 42452e: 75 20 jne 424550 + 424530: 49 83 fb 08 cmp $0x8,%r11 + 424534: 76 1a jbe 424550 + 424536: 66 0f ef c0 pxor %xmm0,%xmm0 + 42453a: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 424541: e9 34 ff ff ff jmpq 42447a + 424546: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42454d: 00 00 00 + 424550: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 424555: 66 0f 73 d8 08 psrldq $0x8,%xmm0 + 42455a: 66 0f 73 db 08 psrldq $0x8,%xmm3 + 42455f: e9 7c 0a 00 00 jmpq 424fe0 + 424564: 66 90 xchg %ax,%ax + 424566: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42456d: 00 00 00 + 424570: 66 0f ef c0 pxor %xmm0,%xmm0 + 424574: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 424578: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42457c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 424580: 66 0f 73 fa 07 pslldq $0x7,%xmm2 + 424585: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 424589: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42458d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 424592: d3 ea shr %cl,%edx + 424594: 41 d3 e9 shr %cl,%r9d + 424597: 44 29 ca sub %r9d,%edx + 42459a: 0f 85 55 0a 00 00 jne 424ff5 + 4245a0: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 4245a4: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 + 4245a9: 4d 39 cb cmp %r9,%r11 + 4245ac: 0f 82 72 0a 00 00 jb 425024 + 4245b2: 4d 85 c9 test %r9,%r9 + 4245b5: 0f 84 69 0a 00 00 je 425024 + 4245bb: 4d 89 cb mov %r9,%r11 + 4245be: 66 0f ef c0 pxor %xmm0,%xmm0 + 4245c2: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 4245c9: 41 b9 09 00 00 00 mov $0x9,%r9d + 4245cf: 4c 8d 57 09 lea 0x9(%rdi),%r10 + 4245d3: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 4245da: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 4245e1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4245e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4245ed: 00 00 00 + 4245f0: 49 83 c2 10 add $0x10,%r10 + 4245f4: 0f 8f a6 00 00 00 jg 4246a0 + 4245fa: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4245ff: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 424604: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 424608: 66 0f 73 db 09 psrldq $0x9,%xmm3 + 42460d: 66 0f 73 fa 07 pslldq $0x7,%xmm2 + 424612: 66 0f eb d3 por %xmm3,%xmm2 + 424616: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42461a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42461e: 66 0f f8 c8 psubb %xmm0,%xmm1 + 424622: 66 0f d7 d1 pmovmskb %xmm1,%edx + 424626: 81 ea ff ff 00 00 sub $0xffff,%edx + 42462c: 0f 85 be 09 00 00 jne 424ff0 + 424632: 49 83 eb 10 sub $0x10,%r11 + 424636: 0f 86 e8 09 00 00 jbe 425024 + 42463c: 48 83 c1 10 add $0x10,%rcx + 424640: 66 0f 6f dc movdqa %xmm4,%xmm3 + 424644: 49 83 c2 10 add $0x10,%r10 + 424648: 7f 56 jg 4246a0 + 42464a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42464f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 424654: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 424658: 66 0f 73 db 09 psrldq $0x9,%xmm3 + 42465d: 66 0f 73 fa 07 pslldq $0x7,%xmm2 + 424662: 66 0f eb d3 por %xmm3,%xmm2 + 424666: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42466a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42466e: 66 0f f8 c8 psubb %xmm0,%xmm1 + 424672: 66 0f d7 d1 pmovmskb %xmm1,%edx + 424676: 81 ea ff ff 00 00 sub $0xffff,%edx + 42467c: 0f 85 6e 09 00 00 jne 424ff0 + 424682: 49 83 eb 10 sub $0x10,%r11 + 424686: 0f 86 98 09 00 00 jbe 425024 + 42468c: 48 83 c1 10 add $0x10,%rcx + 424690: 66 0f 6f dc movdqa %xmm4,%xmm3 + 424694: e9 57 ff ff ff jmpq 4245f0 + 424699: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4246a0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 4246a4: 66 0f d7 d0 pmovmskb %xmm0,%edx + 4246a8: f7 c2 00 fe 00 00 test $0xfe00,%edx + 4246ae: 75 20 jne 4246d0 + 4246b0: 49 83 fb 07 cmp $0x7,%r11 + 4246b4: 76 1a jbe 4246d0 + 4246b6: 66 0f ef c0 pxor %xmm0,%xmm0 + 4246ba: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 4246c1: e9 34 ff ff ff jmpq 4245fa + 4246c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4246cd: 00 00 00 + 4246d0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4246d5: 66 0f 73 d8 09 psrldq $0x9,%xmm0 + 4246da: 66 0f 73 db 09 psrldq $0x9,%xmm3 + 4246df: e9 fc 08 00 00 jmpq 424fe0 + 4246e4: 66 90 xchg %ax,%ax + 4246e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4246ed: 00 00 00 + 4246f0: 66 0f ef c0 pxor %xmm0,%xmm0 + 4246f4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 4246f8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 4246fc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 424700: 66 0f 73 fa 06 pslldq $0x6,%xmm2 + 424705: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 424709: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42470d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 424712: d3 ea shr %cl,%edx + 424714: 41 d3 e9 shr %cl,%r9d + 424717: 44 29 ca sub %r9d,%edx + 42471a: 0f 85 d5 08 00 00 jne 424ff5 + 424720: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 424724: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 + 424729: 4d 39 cb cmp %r9,%r11 + 42472c: 0f 82 f2 08 00 00 jb 425024 + 424732: 4d 85 c9 test %r9,%r9 + 424735: 0f 84 e9 08 00 00 je 425024 + 42473b: 4d 89 cb mov %r9,%r11 + 42473e: 66 0f ef c0 pxor %xmm0,%xmm0 + 424742: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 424749: 41 b9 0a 00 00 00 mov $0xa,%r9d + 42474f: 4c 8d 57 0a lea 0xa(%rdi),%r10 + 424753: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42475a: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 424761: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 424766: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42476d: 00 00 00 + 424770: 49 83 c2 10 add $0x10,%r10 + 424774: 0f 8f a6 00 00 00 jg 424820 + 42477a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42477f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 424784: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 424788: 66 0f 73 db 0a psrldq $0xa,%xmm3 + 42478d: 66 0f 73 fa 06 pslldq $0x6,%xmm2 + 424792: 66 0f eb d3 por %xmm3,%xmm2 + 424796: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42479a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42479e: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4247a2: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4247a6: 81 ea ff ff 00 00 sub $0xffff,%edx + 4247ac: 0f 85 3e 08 00 00 jne 424ff0 + 4247b2: 49 83 eb 10 sub $0x10,%r11 + 4247b6: 0f 86 68 08 00 00 jbe 425024 + 4247bc: 48 83 c1 10 add $0x10,%rcx + 4247c0: 66 0f 6f dc movdqa %xmm4,%xmm3 + 4247c4: 49 83 c2 10 add $0x10,%r10 + 4247c8: 7f 56 jg 424820 + 4247ca: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4247cf: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4247d4: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 4247d8: 66 0f 73 db 0a psrldq $0xa,%xmm3 + 4247dd: 66 0f 73 fa 06 pslldq $0x6,%xmm2 + 4247e2: 66 0f eb d3 por %xmm3,%xmm2 + 4247e6: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4247ea: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 4247ee: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4247f2: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4247f6: 81 ea ff ff 00 00 sub $0xffff,%edx + 4247fc: 0f 85 ee 07 00 00 jne 424ff0 + 424802: 49 83 eb 10 sub $0x10,%r11 + 424806: 0f 86 18 08 00 00 jbe 425024 + 42480c: 48 83 c1 10 add $0x10,%rcx + 424810: 66 0f 6f dc movdqa %xmm4,%xmm3 + 424814: e9 57 ff ff ff jmpq 424770 + 424819: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 424820: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 424824: 66 0f d7 d0 pmovmskb %xmm0,%edx + 424828: f7 c2 00 fc 00 00 test $0xfc00,%edx + 42482e: 75 20 jne 424850 + 424830: 49 83 fb 06 cmp $0x6,%r11 + 424834: 76 1a jbe 424850 + 424836: 66 0f ef c0 pxor %xmm0,%xmm0 + 42483a: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 424841: e9 34 ff ff ff jmpq 42477a + 424846: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42484d: 00 00 00 + 424850: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 424855: 66 0f 73 d8 0a psrldq $0xa,%xmm0 + 42485a: 66 0f 73 db 0a psrldq $0xa,%xmm3 + 42485f: e9 7c 07 00 00 jmpq 424fe0 + 424864: 66 90 xchg %ax,%ax + 424866: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42486d: 00 00 00 + 424870: 66 0f ef c0 pxor %xmm0,%xmm0 + 424874: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 424878: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42487c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 424880: 66 0f 73 fa 05 pslldq $0x5,%xmm2 + 424885: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 424889: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42488d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 424892: d3 ea shr %cl,%edx + 424894: 41 d3 e9 shr %cl,%r9d + 424897: 44 29 ca sub %r9d,%edx + 42489a: 0f 85 55 07 00 00 jne 424ff5 + 4248a0: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 4248a4: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 + 4248a9: 4d 39 cb cmp %r9,%r11 + 4248ac: 0f 82 72 07 00 00 jb 425024 + 4248b2: 4d 85 c9 test %r9,%r9 + 4248b5: 0f 84 69 07 00 00 je 425024 + 4248bb: 4d 89 cb mov %r9,%r11 + 4248be: 66 0f ef c0 pxor %xmm0,%xmm0 + 4248c2: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 4248c9: 41 b9 0b 00 00 00 mov $0xb,%r9d + 4248cf: 4c 8d 57 0b lea 0xb(%rdi),%r10 + 4248d3: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 4248da: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 4248e1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4248e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4248ed: 00 00 00 + 4248f0: 49 83 c2 10 add $0x10,%r10 + 4248f4: 0f 8f a6 00 00 00 jg 4249a0 + 4248fa: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4248ff: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 424904: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 424908: 66 0f 73 db 0b psrldq $0xb,%xmm3 + 42490d: 66 0f 73 fa 05 pslldq $0x5,%xmm2 + 424912: 66 0f eb d3 por %xmm3,%xmm2 + 424916: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42491a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42491e: 66 0f f8 c8 psubb %xmm0,%xmm1 + 424922: 66 0f d7 d1 pmovmskb %xmm1,%edx + 424926: 81 ea ff ff 00 00 sub $0xffff,%edx + 42492c: 0f 85 be 06 00 00 jne 424ff0 + 424932: 49 83 eb 10 sub $0x10,%r11 + 424936: 0f 86 e8 06 00 00 jbe 425024 + 42493c: 48 83 c1 10 add $0x10,%rcx + 424940: 66 0f 6f dc movdqa %xmm4,%xmm3 + 424944: 49 83 c2 10 add $0x10,%r10 + 424948: 7f 56 jg 4249a0 + 42494a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42494f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 424954: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 424958: 66 0f 73 db 0b psrldq $0xb,%xmm3 + 42495d: 66 0f 73 fa 05 pslldq $0x5,%xmm2 + 424962: 66 0f eb d3 por %xmm3,%xmm2 + 424966: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42496a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42496e: 66 0f f8 c8 psubb %xmm0,%xmm1 + 424972: 66 0f d7 d1 pmovmskb %xmm1,%edx + 424976: 81 ea ff ff 00 00 sub $0xffff,%edx + 42497c: 0f 85 6e 06 00 00 jne 424ff0 + 424982: 49 83 eb 10 sub $0x10,%r11 + 424986: 0f 86 98 06 00 00 jbe 425024 + 42498c: 48 83 c1 10 add $0x10,%rcx + 424990: 66 0f 6f dc movdqa %xmm4,%xmm3 + 424994: e9 57 ff ff ff jmpq 4248f0 + 424999: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4249a0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 4249a4: 66 0f d7 d0 pmovmskb %xmm0,%edx + 4249a8: f7 c2 00 f8 00 00 test $0xf800,%edx + 4249ae: 75 20 jne 4249d0 + 4249b0: 49 83 fb 05 cmp $0x5,%r11 + 4249b4: 76 1a jbe 4249d0 + 4249b6: 66 0f ef c0 pxor %xmm0,%xmm0 + 4249ba: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 4249c1: e9 34 ff ff ff jmpq 4248fa + 4249c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4249cd: 00 00 00 + 4249d0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4249d5: 66 0f 73 d8 0b psrldq $0xb,%xmm0 + 4249da: 66 0f 73 db 0b psrldq $0xb,%xmm3 + 4249df: e9 fc 05 00 00 jmpq 424fe0 + 4249e4: 66 90 xchg %ax,%ax + 4249e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4249ed: 00 00 00 + 4249f0: 66 0f ef c0 pxor %xmm0,%xmm0 + 4249f4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 4249f8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 4249fc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 424a00: 66 0f 73 fa 04 pslldq $0x4,%xmm2 + 424a05: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 424a09: 66 0f f8 d0 psubb %xmm0,%xmm2 + 424a0d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 424a12: d3 ea shr %cl,%edx + 424a14: 41 d3 e9 shr %cl,%r9d + 424a17: 44 29 ca sub %r9d,%edx + 424a1a: 0f 85 d5 05 00 00 jne 424ff5 + 424a20: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 424a24: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 + 424a29: 4d 39 cb cmp %r9,%r11 + 424a2c: 0f 82 f2 05 00 00 jb 425024 + 424a32: 4d 85 c9 test %r9,%r9 + 424a35: 0f 84 e9 05 00 00 je 425024 + 424a3b: 4d 89 cb mov %r9,%r11 + 424a3e: 66 0f ef c0 pxor %xmm0,%xmm0 + 424a42: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 424a49: 41 b9 0c 00 00 00 mov $0xc,%r9d + 424a4f: 4c 8d 57 0c lea 0xc(%rdi),%r10 + 424a53: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 424a5a: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 424a61: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 424a66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 424a6d: 00 00 00 + 424a70: 49 83 c2 10 add $0x10,%r10 + 424a74: 0f 8f a6 00 00 00 jg 424b20 + 424a7a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 424a7f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 424a84: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 424a88: 66 0f 73 db 0c psrldq $0xc,%xmm3 + 424a8d: 66 0f 73 fa 04 pslldq $0x4,%xmm2 + 424a92: 66 0f eb d3 por %xmm3,%xmm2 + 424a96: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 424a9a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 424a9e: 66 0f f8 c8 psubb %xmm0,%xmm1 + 424aa2: 66 0f d7 d1 pmovmskb %xmm1,%edx + 424aa6: 81 ea ff ff 00 00 sub $0xffff,%edx + 424aac: 0f 85 3e 05 00 00 jne 424ff0 + 424ab2: 49 83 eb 10 sub $0x10,%r11 + 424ab6: 0f 86 68 05 00 00 jbe 425024 + 424abc: 48 83 c1 10 add $0x10,%rcx + 424ac0: 66 0f 6f dc movdqa %xmm4,%xmm3 + 424ac4: 49 83 c2 10 add $0x10,%r10 + 424ac8: 7f 56 jg 424b20 + 424aca: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 424acf: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 424ad4: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 424ad8: 66 0f 73 db 0c psrldq $0xc,%xmm3 + 424add: 66 0f 73 fa 04 pslldq $0x4,%xmm2 + 424ae2: 66 0f eb d3 por %xmm3,%xmm2 + 424ae6: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 424aea: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 424aee: 66 0f f8 c8 psubb %xmm0,%xmm1 + 424af2: 66 0f d7 d1 pmovmskb %xmm1,%edx + 424af6: 81 ea ff ff 00 00 sub $0xffff,%edx + 424afc: 0f 85 ee 04 00 00 jne 424ff0 + 424b02: 49 83 eb 10 sub $0x10,%r11 + 424b06: 0f 86 18 05 00 00 jbe 425024 + 424b0c: 48 83 c1 10 add $0x10,%rcx + 424b10: 66 0f 6f dc movdqa %xmm4,%xmm3 + 424b14: e9 57 ff ff ff jmpq 424a70 + 424b19: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 424b20: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 424b24: 66 0f d7 d0 pmovmskb %xmm0,%edx + 424b28: f7 c2 00 f0 00 00 test $0xf000,%edx + 424b2e: 75 20 jne 424b50 + 424b30: 49 83 fb 04 cmp $0x4,%r11 + 424b34: 76 1a jbe 424b50 + 424b36: 66 0f ef c0 pxor %xmm0,%xmm0 + 424b3a: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 424b41: e9 34 ff ff ff jmpq 424a7a + 424b46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 424b4d: 00 00 00 + 424b50: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 424b55: 66 0f 73 d8 0c psrldq $0xc,%xmm0 + 424b5a: 66 0f 73 db 0c psrldq $0xc,%xmm3 + 424b5f: e9 7c 04 00 00 jmpq 424fe0 + 424b64: 66 90 xchg %ax,%ax + 424b66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 424b6d: 00 00 00 + 424b70: 66 0f ef c0 pxor %xmm0,%xmm0 + 424b74: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 424b78: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 424b7c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 424b80: 66 0f 73 fa 03 pslldq $0x3,%xmm2 + 424b85: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 424b89: 66 0f f8 d0 psubb %xmm0,%xmm2 + 424b8d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 424b92: d3 ea shr %cl,%edx + 424b94: 41 d3 e9 shr %cl,%r9d + 424b97: 44 29 ca sub %r9d,%edx + 424b9a: 0f 85 55 04 00 00 jne 424ff5 + 424ba0: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 424ba4: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 + 424ba9: 4d 39 cb cmp %r9,%r11 + 424bac: 0f 82 72 04 00 00 jb 425024 + 424bb2: 4d 85 c9 test %r9,%r9 + 424bb5: 0f 84 69 04 00 00 je 425024 + 424bbb: 4d 89 cb mov %r9,%r11 + 424bbe: 66 0f ef c0 pxor %xmm0,%xmm0 + 424bc2: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 424bc9: 41 b9 0d 00 00 00 mov $0xd,%r9d + 424bcf: 4c 8d 57 0d lea 0xd(%rdi),%r10 + 424bd3: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 424bda: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 424be1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 424be6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 424bed: 00 00 00 + 424bf0: 49 83 c2 10 add $0x10,%r10 + 424bf4: 0f 8f a6 00 00 00 jg 424ca0 + 424bfa: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 424bff: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 424c04: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 424c08: 66 0f 73 db 0d psrldq $0xd,%xmm3 + 424c0d: 66 0f 73 fa 03 pslldq $0x3,%xmm2 + 424c12: 66 0f eb d3 por %xmm3,%xmm2 + 424c16: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 424c1a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 424c1e: 66 0f f8 c8 psubb %xmm0,%xmm1 + 424c22: 66 0f d7 d1 pmovmskb %xmm1,%edx + 424c26: 81 ea ff ff 00 00 sub $0xffff,%edx + 424c2c: 0f 85 be 03 00 00 jne 424ff0 + 424c32: 49 83 eb 10 sub $0x10,%r11 + 424c36: 0f 86 e8 03 00 00 jbe 425024 + 424c3c: 48 83 c1 10 add $0x10,%rcx + 424c40: 66 0f 6f dc movdqa %xmm4,%xmm3 + 424c44: 49 83 c2 10 add $0x10,%r10 + 424c48: 7f 56 jg 424ca0 + 424c4a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 424c4f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 424c54: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 424c58: 66 0f 73 db 0d psrldq $0xd,%xmm3 + 424c5d: 66 0f 73 fa 03 pslldq $0x3,%xmm2 + 424c62: 66 0f eb d3 por %xmm3,%xmm2 + 424c66: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 424c6a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 424c6e: 66 0f f8 c8 psubb %xmm0,%xmm1 + 424c72: 66 0f d7 d1 pmovmskb %xmm1,%edx + 424c76: 81 ea ff ff 00 00 sub $0xffff,%edx + 424c7c: 0f 85 6e 03 00 00 jne 424ff0 + 424c82: 49 83 eb 10 sub $0x10,%r11 + 424c86: 0f 86 98 03 00 00 jbe 425024 + 424c8c: 48 83 c1 10 add $0x10,%rcx + 424c90: 66 0f 6f dc movdqa %xmm4,%xmm3 + 424c94: e9 57 ff ff ff jmpq 424bf0 + 424c99: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 424ca0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 424ca4: 66 0f d7 d0 pmovmskb %xmm0,%edx + 424ca8: f7 c2 00 e0 00 00 test $0xe000,%edx + 424cae: 75 20 jne 424cd0 + 424cb0: 49 83 fb 03 cmp $0x3,%r11 + 424cb4: 76 1a jbe 424cd0 + 424cb6: 66 0f ef c0 pxor %xmm0,%xmm0 + 424cba: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 424cc1: e9 34 ff ff ff jmpq 424bfa + 424cc6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 424ccd: 00 00 00 + 424cd0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 424cd5: 66 0f 73 d8 0d psrldq $0xd,%xmm0 + 424cda: 66 0f 73 db 0d psrldq $0xd,%xmm3 + 424cdf: e9 fc 02 00 00 jmpq 424fe0 + 424ce4: 66 90 xchg %ax,%ax + 424ce6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 424ced: 00 00 00 + 424cf0: 66 0f ef c0 pxor %xmm0,%xmm0 + 424cf4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 424cf8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 424cfc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 424d00: 66 0f 73 fa 02 pslldq $0x2,%xmm2 + 424d05: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 424d09: 66 0f f8 d0 psubb %xmm0,%xmm2 + 424d0d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 424d12: d3 ea shr %cl,%edx + 424d14: 41 d3 e9 shr %cl,%r9d + 424d17: 44 29 ca sub %r9d,%edx + 424d1a: 0f 85 d5 02 00 00 jne 424ff5 + 424d20: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 424d24: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 + 424d29: 4d 39 cb cmp %r9,%r11 + 424d2c: 0f 82 f2 02 00 00 jb 425024 + 424d32: 4d 85 c9 test %r9,%r9 + 424d35: 0f 84 e9 02 00 00 je 425024 + 424d3b: 4d 89 cb mov %r9,%r11 + 424d3e: 66 0f ef c0 pxor %xmm0,%xmm0 + 424d42: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 424d49: 41 b9 0e 00 00 00 mov $0xe,%r9d + 424d4f: 4c 8d 57 0e lea 0xe(%rdi),%r10 + 424d53: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 424d5a: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 424d61: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 424d66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 424d6d: 00 00 00 + 424d70: 49 83 c2 10 add $0x10,%r10 + 424d74: 0f 8f a6 00 00 00 jg 424e20 + 424d7a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 424d7f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 424d84: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 424d88: 66 0f 73 db 0e psrldq $0xe,%xmm3 + 424d8d: 66 0f 73 fa 02 pslldq $0x2,%xmm2 + 424d92: 66 0f eb d3 por %xmm3,%xmm2 + 424d96: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 424d9a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 424d9e: 66 0f f8 c8 psubb %xmm0,%xmm1 + 424da2: 66 0f d7 d1 pmovmskb %xmm1,%edx + 424da6: 81 ea ff ff 00 00 sub $0xffff,%edx + 424dac: 0f 85 3e 02 00 00 jne 424ff0 + 424db2: 49 83 eb 10 sub $0x10,%r11 + 424db6: 0f 86 68 02 00 00 jbe 425024 + 424dbc: 48 83 c1 10 add $0x10,%rcx + 424dc0: 66 0f 6f dc movdqa %xmm4,%xmm3 + 424dc4: 49 83 c2 10 add $0x10,%r10 + 424dc8: 7f 56 jg 424e20 + 424dca: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 424dcf: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 424dd4: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 424dd8: 66 0f 73 db 0e psrldq $0xe,%xmm3 + 424ddd: 66 0f 73 fa 02 pslldq $0x2,%xmm2 + 424de2: 66 0f eb d3 por %xmm3,%xmm2 + 424de6: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 424dea: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 424dee: 66 0f f8 c8 psubb %xmm0,%xmm1 + 424df2: 66 0f d7 d1 pmovmskb %xmm1,%edx + 424df6: 81 ea ff ff 00 00 sub $0xffff,%edx + 424dfc: 0f 85 ee 01 00 00 jne 424ff0 + 424e02: 49 83 eb 10 sub $0x10,%r11 + 424e06: 0f 86 18 02 00 00 jbe 425024 + 424e0c: 48 83 c1 10 add $0x10,%rcx + 424e10: 66 0f 6f dc movdqa %xmm4,%xmm3 + 424e14: e9 57 ff ff ff jmpq 424d70 + 424e19: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 424e20: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 424e24: 66 0f d7 d0 pmovmskb %xmm0,%edx + 424e28: f7 c2 00 c0 00 00 test $0xc000,%edx + 424e2e: 75 20 jne 424e50 + 424e30: 49 83 fb 02 cmp $0x2,%r11 + 424e34: 76 1a jbe 424e50 + 424e36: 66 0f ef c0 pxor %xmm0,%xmm0 + 424e3a: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 424e41: e9 34 ff ff ff jmpq 424d7a + 424e46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 424e4d: 00 00 00 + 424e50: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 424e55: 66 0f 73 d8 0e psrldq $0xe,%xmm0 + 424e5a: 66 0f 73 db 0e psrldq $0xe,%xmm3 + 424e5f: e9 7c 01 00 00 jmpq 424fe0 + 424e64: 66 90 xchg %ax,%ax + 424e66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 424e6d: 00 00 00 + 424e70: 66 0f ef c0 pxor %xmm0,%xmm0 + 424e74: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 424e78: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 424e7c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 424e80: 66 0f 73 fa 01 pslldq $0x1,%xmm2 + 424e85: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 424e89: 66 0f f8 d0 psubb %xmm0,%xmm2 + 424e8d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 424e92: d3 ea shr %cl,%edx + 424e94: 41 d3 e9 shr %cl,%r9d + 424e97: 44 29 ca sub %r9d,%edx + 424e9a: 0f 85 55 01 00 00 jne 424ff5 + 424ea0: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 424ea4: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 + 424ea9: 4d 39 cb cmp %r9,%r11 + 424eac: 0f 82 72 01 00 00 jb 425024 + 424eb2: 4d 85 c9 test %r9,%r9 + 424eb5: 0f 84 69 01 00 00 je 425024 + 424ebb: 4d 89 cb mov %r9,%r11 + 424ebe: 66 0f ef c0 pxor %xmm0,%xmm0 + 424ec2: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 424ec9: 41 b9 0f 00 00 00 mov $0xf,%r9d + 424ecf: 4c 8d 57 0f lea 0xf(%rdi),%r10 + 424ed3: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 424eda: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 424ee1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 424ee6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 424eed: 00 00 00 + 424ef0: 49 83 c2 10 add $0x10,%r10 + 424ef4: 0f 8f a6 00 00 00 jg 424fa0 + 424efa: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 424eff: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 424f04: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 424f08: 66 0f 73 db 0f psrldq $0xf,%xmm3 + 424f0d: 66 0f 73 fa 01 pslldq $0x1,%xmm2 + 424f12: 66 0f eb d3 por %xmm3,%xmm2 + 424f16: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 424f1a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 424f1e: 66 0f f8 c8 psubb %xmm0,%xmm1 + 424f22: 66 0f d7 d1 pmovmskb %xmm1,%edx + 424f26: 81 ea ff ff 00 00 sub $0xffff,%edx + 424f2c: 0f 85 be 00 00 00 jne 424ff0 + 424f32: 49 83 eb 10 sub $0x10,%r11 + 424f36: 0f 86 e8 00 00 00 jbe 425024 + 424f3c: 48 83 c1 10 add $0x10,%rcx + 424f40: 66 0f 6f dc movdqa %xmm4,%xmm3 + 424f44: 49 83 c2 10 add $0x10,%r10 + 424f48: 7f 56 jg 424fa0 + 424f4a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 424f4f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 424f54: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 424f58: 66 0f 73 db 0f psrldq $0xf,%xmm3 + 424f5d: 66 0f 73 fa 01 pslldq $0x1,%xmm2 + 424f62: 66 0f eb d3 por %xmm3,%xmm2 + 424f66: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 424f6a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 424f6e: 66 0f f8 c8 psubb %xmm0,%xmm1 + 424f72: 66 0f d7 d1 pmovmskb %xmm1,%edx + 424f76: 81 ea ff ff 00 00 sub $0xffff,%edx + 424f7c: 75 72 jne 424ff0 + 424f7e: 49 83 eb 10 sub $0x10,%r11 + 424f82: 0f 86 9c 00 00 00 jbe 425024 + 424f88: 48 83 c1 10 add $0x10,%rcx + 424f8c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 424f90: e9 5b ff ff ff jmpq 424ef0 + 424f95: 90 nop + 424f96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 424f9d: 00 00 00 + 424fa0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 424fa4: 66 0f d7 d0 pmovmskb %xmm0,%edx + 424fa8: f7 c2 00 80 00 00 test $0x8000,%edx + 424fae: 75 20 jne 424fd0 + 424fb0: 49 83 fb 01 cmp $0x1,%r11 + 424fb4: 76 1a jbe 424fd0 + 424fb6: 66 0f ef c0 pxor %xmm0,%xmm0 + 424fba: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 424fc1: e9 34 ff ff ff jmpq 424efa + 424fc6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 424fcd: 00 00 00 + 424fd0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 424fd5: 66 0f 73 db 0f psrldq $0xf,%xmm3 + 424fda: 66 0f 73 d8 0f psrldq $0xf,%xmm0 + 424fdf: 90 nop + 424fe0: 66 0f 74 cb pcmpeqb %xmm3,%xmm1 + 424fe4: 66 0f f8 c8 psubb %xmm0,%xmm1 + 424fe8: 66 0f d7 d1 pmovmskb %xmm1,%edx + 424fec: f7 d2 not %edx + 424fee: 66 90 xchg %ax,%ax + 424ff0: 49 8d 44 09 f0 lea -0x10(%r9,%rcx,1),%rax + 424ff5: 48 8d 3c 07 lea (%rdi,%rax,1),%rdi + 424ff9: 48 8d 34 0e lea (%rsi,%rcx,1),%rsi + 424ffd: 45 85 c0 test %r8d,%r8d + 425000: 74 0e je 425010 + 425002: 48 87 f7 xchg %rsi,%rdi + 425005: 90 nop + 425006: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42500d: 00 00 00 + 425010: 48 0f bc d2 bsf %rdx,%rdx + 425014: 49 29 d3 sub %rdx,%r11 + 425017: 76 0b jbe 425024 + 425019: 0f b6 0c 16 movzbl (%rsi,%rdx,1),%ecx + 42501d: 0f b6 04 17 movzbl (%rdi,%rdx,1),%eax + 425021: 29 c8 sub %ecx,%eax + 425023: c3 retq + 425024: 31 c0 xor %eax,%eax + 425026: c3 retq + 425027: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 42502e: 00 00 + 425030: 0f b6 0e movzbl (%rsi),%ecx + 425033: 0f b6 07 movzbl (%rdi),%eax + 425036: 29 c8 sub %ecx,%eax + 425038: c3 retq + 425039: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + +0000000000425040 : + 425040: 41 57 push %r15 + 425042: 41 56 push %r14 + 425044: 41 55 push %r13 + 425046: 41 54 push %r12 + 425048: 49 89 fd mov %rdi,%r13 + 42504b: 55 push %rbp + 42504c: 53 push %rbx + 42504d: 48 89 d5 mov %rdx,%rbp + 425050: 48 89 f3 mov %rsi,%rbx + 425053: 49 89 cc mov %rcx,%r12 + 425056: bf 01 00 00 00 mov $0x1,%edi + 42505b: 48 81 ec 58 08 00 00 sub $0x858,%rsp + 425062: ba 01 00 00 00 mov $0x1,%edx + 425067: 31 c9 xor %ecx,%ecx + 425069: 48 c7 c6 ff ff ff ff mov $0xffffffffffffffff,%rsi + 425070: 48 8d 04 0a lea (%rdx,%rcx,1),%rax + 425074: 49 39 c4 cmp %rax,%r12 + 425077: 76 2c jbe 4250a5 + 425079: 4c 8d 44 35 00 lea 0x0(%rbp,%rsi,1),%r8 + 42507e: 45 0f b6 14 10 movzbl (%r8,%rdx,1),%r10d + 425083: 44 38 54 05 00 cmp %r10b,0x0(%rbp,%rax,1) + 425088: 0f 83 8a 02 00 00 jae 425318 + 42508e: 48 89 c1 mov %rax,%rcx + 425091: ba 01 00 00 00 mov $0x1,%edx + 425096: 48 89 c7 mov %rax,%rdi + 425099: 48 8d 04 0a lea (%rdx,%rcx,1),%rax + 42509d: 48 29 f7 sub %rsi,%rdi + 4250a0: 49 39 c4 cmp %rax,%r12 + 4250a3: 77 d4 ja 425079 + 4250a5: 48 c7 44 24 08 01 00 movq $0x1,0x8(%rsp) + 4250ac: 00 00 + 4250ae: ba 01 00 00 00 mov $0x1,%edx + 4250b3: 31 c9 xor %ecx,%ecx + 4250b5: 49 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%r8 + 4250bc: 0f 1f 40 00 nopl 0x0(%rax) + 4250c0: 48 8d 04 0a lea (%rdx,%rcx,1),%rax + 4250c4: 49 39 c4 cmp %rax,%r12 + 4250c7: 76 31 jbe 4250fa + 4250c9: 4e 8d 4c 05 00 lea 0x0(%rbp,%r8,1),%r9 + 4250ce: 45 0f b6 1c 11 movzbl (%r9,%rdx,1),%r11d + 4250d3: 44 38 5c 05 00 cmp %r11b,0x0(%rbp,%rax,1) + 4250d8: 0f 86 52 02 00 00 jbe 425330 + 4250de: 48 89 c1 mov %rax,%rcx + 4250e1: ba 01 00 00 00 mov $0x1,%edx + 4250e6: 4c 29 c1 sub %r8,%rcx + 4250e9: 48 89 4c 24 08 mov %rcx,0x8(%rsp) + 4250ee: 48 89 c1 mov %rax,%rcx + 4250f1: 48 8d 04 0a lea (%rdx,%rcx,1),%rax + 4250f5: 49 39 c4 cmp %rax,%r12 + 4250f8: 77 cf ja 4250c9 + 4250fa: 49 8d 40 01 lea 0x1(%r8),%rax + 4250fe: 48 83 c6 01 add $0x1,%rsi + 425102: 48 39 f0 cmp %rsi,%rax + 425105: 48 89 44 24 10 mov %rax,0x10(%rsp) + 42510a: 73 0a jae 425116 + 42510c: 48 89 7c 24 08 mov %rdi,0x8(%rsp) + 425111: 48 89 74 24 10 mov %rsi,0x10(%rsp) + 425116: 4c 89 64 24 18 mov %r12,0x18(%rsp) + 42511b: 48 8d 44 24 50 lea 0x50(%rsp),%rax + 425120: 48 8d 94 24 50 08 00 lea 0x850(%rsp),%rdx + 425127: 00 + 425128: f3 0f 7e 44 24 18 movq 0x18(%rsp),%xmm0 + 42512e: 66 0f 6c c0 punpcklqdq %xmm0,%xmm0 + 425132: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 425138: 0f 29 00 movaps %xmm0,(%rax) + 42513b: 48 83 c0 10 add $0x10,%rax + 42513f: 48 39 d0 cmp %rdx,%rax + 425142: 75 f4 jne 425138 + 425144: 4d 85 e4 test %r12,%r12 + 425147: 49 8d 44 24 ff lea -0x1(%r12),%rax + 42514c: 48 89 ea mov %rbp,%rdx + 42514f: 74 1d je 42516e + 425151: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 425158: 0f b6 0a movzbl (%rdx),%ecx + 42515b: 48 83 c2 01 add $0x1,%rdx + 42515f: 48 89 44 cc 50 mov %rax,0x50(%rsp,%rcx,8) + 425164: 48 83 e8 01 sub $0x1,%rax + 425168: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 42516c: 75 ea jne 425158 + 42516e: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 425173: 48 8b 54 24 10 mov 0x10(%rsp),%rdx + 425178: 48 89 ef mov %rbp,%rdi + 42517b: 48 8d 74 05 00 lea 0x0(%rbp,%rax,1),%rsi + 425180: e8 ab b1 fd ff callq 400330 <__rela_iplt_end+0x68> + 425185: 85 c0 test %eax,%eax + 425187: 0f 85 0b 02 00 00 jne 425398 + 42518d: 48 8b 4c 24 10 mov 0x10(%rsp),%rcx + 425192: 4d 8d 7c 24 ff lea -0x1(%r12),%r15 + 425197: b8 01 00 00 00 mov $0x1,%eax + 42519c: 45 31 c0 xor %r8d,%r8d + 42519f: 48 89 6c 24 20 mov %rbp,0x20(%rsp) + 4251a4: 45 31 f6 xor %r14d,%r14d + 4251a7: 4c 89 64 24 18 mov %r12,0x18(%rsp) + 4251ac: 48 8d 71 ff lea -0x1(%rcx),%rsi + 4251b0: 48 89 cf mov %rcx,%rdi + 4251b3: 48 29 c8 sub %rcx,%rax + 4251b6: 48 f7 df neg %rdi + 4251b9: 48 89 44 24 40 mov %rax,0x40(%rsp) + 4251be: 4c 89 e0 mov %r12,%rax + 4251c1: 48 89 74 24 28 mov %rsi,0x28(%rsp) + 4251c6: 48 01 ee add %rbp,%rsi + 4251c9: 48 89 7c 24 48 mov %rdi,0x48(%rsp) + 4251ce: 49 89 f1 mov %rsi,%r9 + 4251d1: 48 89 74 24 38 mov %rsi,0x38(%rsp) + 4251d6: 4c 89 e6 mov %r12,%rsi + 4251d9: 48 2b 74 24 08 sub 0x8(%rsp),%rsi + 4251de: 49 01 f9 add %rdi,%r9 + 4251e1: 4c 89 fd mov %r15,%rbp + 4251e4: 48 89 df mov %rbx,%rdi + 4251e7: 4d 89 c7 mov %r8,%r15 + 4251ea: 4c 89 cb mov %r9,%rbx + 4251ed: 48 89 74 24 30 mov %rsi,0x30(%rsp) + 4251f2: eb 22 jmp 425216 + 4251f4: 0f 1f 40 00 nopl 0x0(%rax) + 4251f8: 4d 85 f6 test %r14,%r14 + 4251fb: 74 0b je 425208 + 4251fd: 48 3b 44 24 08 cmp 0x8(%rsp),%rax + 425202: 48 0f 42 44 24 30 cmovb 0x30(%rsp),%rax + 425208: 49 01 c7 add %rax,%r15 + 42520b: 45 31 f6 xor %r14d,%r14d + 42520e: 48 8b 44 24 18 mov 0x18(%rsp),%rax + 425213: 4c 89 e7 mov %r12,%rdi + 425216: 4d 8d 24 07 lea (%r15,%rax,1),%r12 + 42521a: 31 f6 xor %esi,%esi + 42521c: 4c 89 e2 mov %r12,%rdx + 42521f: 48 29 fa sub %rdi,%rdx + 425222: 4c 01 ef add %r13,%rdi + 425225: e8 16 09 00 00 callq 425b40 <__memchr> + 42522a: 4d 85 e4 test %r12,%r12 + 42522d: 0f 84 d7 02 00 00 je 42550a + 425233: 48 85 c0 test %rax,%rax + 425236: 0f 85 ce 02 00 00 jne 42550a + 42523c: 43 0f b6 44 25 ff movzbl -0x1(%r13,%r12,1),%eax + 425242: 48 8b 44 c4 50 mov 0x50(%rsp,%rax,8),%rax + 425247: 48 85 c0 test %rax,%rax + 42524a: 75 ac jne 4251f8 + 42524c: 48 8b 44 24 10 mov 0x10(%rsp),%rax + 425251: 48 8b 74 24 20 mov 0x20(%rsp),%rsi + 425256: 49 39 c6 cmp %rax,%r14 + 425259: 49 0f 43 c6 cmovae %r14,%rax + 42525d: 48 8d 14 06 lea (%rsi,%rax,1),%rdx + 425261: 49 8d 34 07 lea (%r15,%rax,1),%rsi + 425265: 48 39 e8 cmp %rbp,%rax + 425268: 49 8d 7c 35 00 lea 0x0(%r13,%rsi,1),%rdi + 42526d: 73 37 jae 4252a6 + 42526f: 0f b6 32 movzbl (%rdx),%esi + 425272: 40 38 37 cmp %sil,(%rdi) + 425275: 0f 85 d5 00 00 00 jne 425350 + 42527b: 48 89 c6 mov %rax,%rsi + 42527e: 48 f7 de neg %rsi + 425281: 48 01 f2 add %rsi,%rdx + 425284: 48 01 fe add %rdi,%rsi + 425287: eb 14 jmp 42529d + 425289: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 425290: 0f b6 0c 06 movzbl (%rsi,%rax,1),%ecx + 425294: 38 0c 02 cmp %cl,(%rdx,%rax,1) + 425297: 0f 85 b3 00 00 00 jne 425350 + 42529d: 48 83 c0 01 add $0x1,%rax + 4252a1: 48 39 e8 cmp %rbp,%rax + 4252a4: 72 ea jb 425290 + 4252a6: 48 8b 44 24 28 mov 0x28(%rsp),%rax + 4252ab: 49 8d 34 07 lea (%r15,%rax,1),%rsi + 4252af: 4c 01 ee add %r13,%rsi + 4252b2: 4c 3b 74 24 10 cmp 0x10(%rsp),%r14 + 4252b7: 0f 83 73 02 00 00 jae 425530 + 4252bd: 48 8b 44 24 38 mov 0x38(%rsp),%rax + 4252c2: 0f b6 00 movzbl (%rax),%eax + 4252c5: 38 06 cmp %al,(%rsi) + 4252c7: 0f 85 63 02 00 00 jne 425530 + 4252cd: 48 8b 44 24 28 mov 0x28(%rsp),%rax + 4252d2: 48 03 74 24 48 add 0x48(%rsp),%rsi + 4252d7: eb 18 jmp 4252f1 + 4252d9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4252e0: 48 8d 50 ff lea -0x1(%rax),%rdx + 4252e4: 0f b6 4c 32 01 movzbl 0x1(%rdx,%rsi,1),%ecx + 4252e9: 38 0c 03 cmp %cl,(%rbx,%rax,1) + 4252ec: 75 08 jne 4252f6 + 4252ee: 48 89 d0 mov %rdx,%rax + 4252f1: 49 39 c6 cmp %rax,%r14 + 4252f4: 75 ea jne 4252e0 + 4252f6: 49 83 c6 01 add $0x1,%r14 + 4252fa: 49 39 c6 cmp %rax,%r14 + 4252fd: 0f 87 37 02 00 00 ja 42553a + 425303: 4c 03 7c 24 08 add 0x8(%rsp),%r15 + 425308: 4c 8b 74 24 30 mov 0x30(%rsp),%r14 + 42530d: e9 fc fe ff ff jmpq 42520e + 425312: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 425318: 74 4e je 425368 + 42531a: 48 89 ce mov %rcx,%rsi + 42531d: bf 01 00 00 00 mov $0x1,%edi + 425322: 48 83 c1 01 add $0x1,%rcx + 425326: ba 01 00 00 00 mov $0x1,%edx + 42532b: e9 40 fd ff ff jmpq 425070 + 425330: 74 4e je 425380 + 425332: 49 89 c8 mov %rcx,%r8 + 425335: 48 c7 44 24 08 01 00 movq $0x1,0x8(%rsp) + 42533c: 00 00 + 42533e: 48 83 c1 01 add $0x1,%rcx + 425342: ba 01 00 00 00 mov $0x1,%edx + 425347: e9 74 fd ff ff jmpq 4250c0 + 42534c: 0f 1f 40 00 nopl 0x0(%rax) + 425350: 48 8b 7c 24 40 mov 0x40(%rsp),%rdi + 425355: 45 31 f6 xor %r14d,%r14d + 425358: 4e 8d 04 3f lea (%rdi,%r15,1),%r8 + 42535c: 4e 8d 3c 00 lea (%rax,%r8,1),%r15 + 425360: e9 a9 fe ff ff jmpq 42520e + 425365: 0f 1f 00 nopl (%rax) + 425368: 48 39 fa cmp %rdi,%rdx + 42536b: 0f 84 af 01 00 00 je 425520 + 425371: 48 83 c2 01 add $0x1,%rdx + 425375: e9 f6 fc ff ff jmpq 425070 + 42537a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 425380: 48 3b 54 24 08 cmp 0x8(%rsp),%rdx + 425385: 0f 84 83 01 00 00 je 42550e + 42538b: 48 83 c2 01 add $0x1,%rdx + 42538f: e9 2c fd ff ff jmpq 4250c0 + 425394: 0f 1f 40 00 nopl 0x0(%rax) + 425398: 48 8b 74 24 10 mov 0x10(%rsp),%rsi + 42539d: 4c 89 e0 mov %r12,%rax + 4253a0: 41 bb 01 00 00 00 mov $0x1,%r11d + 4253a6: 49 8d 4c 24 ff lea -0x1(%r12),%rcx + 4253ab: 4c 89 64 24 08 mov %r12,0x8(%rsp) + 4253b0: 48 29 f0 sub %rsi,%rax + 4253b3: 48 39 f0 cmp %rsi,%rax + 4253b6: 48 0f 42 c6 cmovb %rsi,%rax + 4253ba: 49 29 f3 sub %rsi,%r11 + 4253bd: 45 31 ff xor %r15d,%r15d + 4253c0: 48 83 c0 01 add $0x1,%rax + 4253c4: 48 89 44 24 38 mov %rax,0x38(%rsp) + 4253c9: 48 8d 46 ff lea -0x1(%rsi),%rax + 4253cd: 48 89 c7 mov %rax,%rdi + 4253d0: 48 89 44 24 30 mov %rax,0x30(%rsp) + 4253d5: 48 8d 44 35 00 lea 0x0(%rbp,%rsi,1),%rax + 4253da: 48 f7 de neg %rsi + 4253dd: 48 01 fd add %rdi,%rbp + 4253e0: 48 89 df mov %rbx,%rdi + 4253e3: 49 89 c6 mov %rax,%r14 + 4253e6: 48 89 44 24 18 mov %rax,0x18(%rsp) + 4253eb: 4c 89 e8 mov %r13,%rax + 4253ee: 49 01 f6 add %rsi,%r14 + 4253f1: 4d 89 fd mov %r15,%r13 + 4253f4: 48 89 74 24 20 mov %rsi,0x20(%rsp) + 4253f9: 4c 89 74 24 28 mov %r14,0x28(%rsp) + 4253fe: 48 89 cb mov %rcx,%rbx + 425401: 49 89 ec mov %rbp,%r12 + 425404: 4d 89 de mov %r11,%r14 + 425407: 49 89 c7 mov %rax,%r15 + 42540a: eb 0a jmp 425416 + 42540c: 0f 1f 40 00 nopl 0x0(%rax) + 425410: 49 01 c5 add %rax,%r13 + 425413: 48 89 ef mov %rbp,%rdi + 425416: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 42541b: 31 f6 xor %esi,%esi + 42541d: 49 8d 6c 05 00 lea 0x0(%r13,%rax,1),%rbp + 425422: 48 89 ea mov %rbp,%rdx + 425425: 48 29 fa sub %rdi,%rdx + 425428: 4c 01 ff add %r15,%rdi + 42542b: e8 10 07 00 00 callq 425b40 <__memchr> + 425430: 48 85 c0 test %rax,%rax + 425433: 0f 85 d1 00 00 00 jne 42550a + 425439: 48 85 ed test %rbp,%rbp + 42543c: 0f 84 c8 00 00 00 je 42550a + 425442: 41 0f b6 44 2f ff movzbl -0x1(%r15,%rbp,1),%eax + 425448: 48 8b 44 c4 50 mov 0x50(%rsp,%rax,8),%rax + 42544d: 48 85 c0 test %rax,%rax + 425450: 75 be jne 425410 + 425452: 48 8b 44 24 10 mov 0x10(%rsp),%rax + 425457: 49 8d 54 05 00 lea 0x0(%r13,%rax,1),%rdx + 42545c: 4c 01 fa add %r15,%rdx + 42545f: 48 39 d8 cmp %rbx,%rax + 425462: 73 2f jae 425493 + 425464: 48 8b 74 24 18 mov 0x18(%rsp),%rsi + 425469: 0f b6 36 movzbl (%rsi),%esi + 42546c: 40 38 32 cmp %sil,(%rdx) + 42546f: 75 7f jne 4254f0 + 425471: 48 03 54 24 20 add 0x20(%rsp),%rdx + 425476: 48 8b 4c 24 28 mov 0x28(%rsp),%rcx + 42547b: eb 0d jmp 42548a + 42547d: 0f 1f 00 nopl (%rax) + 425480: 0f b6 3c 02 movzbl (%rdx,%rax,1),%edi + 425484: 40 38 3c 01 cmp %dil,(%rcx,%rax,1) + 425488: 75 66 jne 4254f0 + 42548a: 48 83 c0 01 add $0x1,%rax + 42548e: 48 39 d8 cmp %rbx,%rax + 425491: 72 ed jb 425480 + 425493: 48 8b 44 24 30 mov 0x30(%rsp),%rax + 425498: 49 8d 74 05 00 lea 0x0(%r13,%rax,1),%rsi + 42549d: 4c 01 fe add %r15,%rsi + 4254a0: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 4254a4: 74 26 je 4254cc + 4254a6: 41 0f b6 04 24 movzbl (%r12),%eax + 4254ab: 38 06 cmp %al,(%rsi) + 4254ad: 75 51 jne 425500 + 4254af: 31 c0 xor %eax,%eax + 4254b1: eb 14 jmp 4254c7 + 4254b3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4254b8: 41 0f b6 54 04 ff movzbl -0x1(%r12,%rax,1),%edx + 4254be: 48 83 e8 01 sub $0x1,%rax + 4254c2: 3a 14 06 cmp (%rsi,%rax,1),%dl + 4254c5: 75 39 jne 425500 + 4254c7: 49 39 c6 cmp %rax,%r14 + 4254ca: 75 ec jne 4254b8 + 4254cc: 4c 89 f8 mov %r15,%rax + 4254cf: 4d 89 ef mov %r13,%r15 + 4254d2: 4a 8d 04 38 lea (%rax,%r15,1),%rax + 4254d6: 48 81 c4 58 08 00 00 add $0x858,%rsp + 4254dd: 5b pop %rbx + 4254de: 5d pop %rbp + 4254df: 41 5c pop %r12 + 4254e1: 41 5d pop %r13 + 4254e3: 41 5e pop %r14 + 4254e5: 41 5f pop %r15 + 4254e7: c3 retq + 4254e8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 4254ef: 00 + 4254f0: 4f 8d 04 2e lea (%r14,%r13,1),%r8 + 4254f4: 4e 8d 2c 00 lea (%rax,%r8,1),%r13 + 4254f8: e9 16 ff ff ff jmpq 425413 + 4254fd: 0f 1f 00 nopl (%rax) + 425500: 4c 03 6c 24 38 add 0x38(%rsp),%r13 + 425505: e9 09 ff ff ff jmpq 425413 + 42550a: 31 c0 xor %eax,%eax + 42550c: eb c8 jmp 4254d6 + 42550e: 48 89 54 24 08 mov %rdx,0x8(%rsp) + 425513: 48 89 c1 mov %rax,%rcx + 425516: ba 01 00 00 00 mov $0x1,%edx + 42551b: e9 a0 fb ff ff jmpq 4250c0 + 425520: 48 89 d7 mov %rdx,%rdi + 425523: 48 89 c1 mov %rax,%rcx + 425526: ba 01 00 00 00 mov $0x1,%edx + 42552b: e9 40 fb ff ff jmpq 425070 + 425530: 48 8b 44 24 10 mov 0x10(%rsp),%rax + 425535: e9 bc fd ff ff jmpq 4252f6 + 42553a: 4b 8d 44 3d 00 lea 0x0(%r13,%r15,1),%rax + 42553f: eb 95 jmp 4254d6 + 425541: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 425546: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42554d: 00 00 00 + +0000000000425550 <__strstr_sse2>: + 425550: 41 57 push %r15 + 425552: 41 56 push %r14 + 425554: 41 55 push %r13 + 425556: 41 54 push %r12 + 425558: 55 push %rbp + 425559: 53 push %rbx + 42555a: 48 83 ec 58 sub $0x58,%rsp + 42555e: 0f b6 17 movzbl (%rdi),%edx + 425561: 84 d2 test %dl,%dl + 425563: 0f 84 93 05 00 00 je 425afc <__strstr_sse2+0x5ac> + 425569: 0f b6 0e movzbl (%rsi),%ecx + 42556c: 84 c9 test %cl,%cl + 42556e: 0f 84 bc 00 00 00 je 425630 <__strstr_sse2+0xe0> + 425574: 48 89 f3 mov %rsi,%rbx + 425577: 49 89 f8 mov %rdi,%r8 + 42557a: 41 b9 01 00 00 00 mov $0x1,%r9d + 425580: eb 0d jmp 42558f <__strstr_sse2+0x3f> + 425582: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 425588: 0f b6 0b movzbl (%rbx),%ecx + 42558b: 84 c9 test %cl,%cl + 42558d: 74 1d je 4255ac <__strstr_sse2+0x5c> + 42558f: 49 83 c0 01 add $0x1,%r8 + 425593: 48 83 c3 01 add $0x1,%rbx + 425597: 38 ca cmp %cl,%dl + 425599: 41 0f b6 10 movzbl (%r8),%edx + 42559d: 0f 94 c0 sete %al + 4255a0: 41 21 c1 and %eax,%r9d + 4255a3: 84 d2 test %dl,%dl + 4255a5: 75 e1 jne 425588 <__strstr_sse2+0x38> + 4255a7: 80 3b 00 cmpb $0x0,(%rbx) + 4255aa: 75 6c jne 425618 <__strstr_sse2+0xc8> + 4255ac: 45 84 c9 test %r9b,%r9b + 4255af: 75 7f jne 425630 <__strstr_sse2+0xe0> + 4255b1: 49 89 dc mov %rbx,%r12 + 4255b4: 48 89 fd mov %rdi,%rbp + 4255b7: 48 8d 7f 01 lea 0x1(%rdi),%rdi + 4255bb: 49 29 f4 sub %rsi,%r12 + 4255be: 0f be 36 movsbl (%rsi),%esi + 4255c1: e8 ba ad fd ff callq 400380 <__rela_iplt_end+0xb8> + 4255c6: 48 85 c0 test %rax,%rax + 4255c9: 49 89 c7 mov %rax,%r15 + 4255cc: 74 4a je 425618 <__strstr_sse2+0xc8> + 4255ce: 49 83 fc 01 cmp $0x1,%r12 + 4255d2: 74 46 je 42561a <__strstr_sse2+0xca> + 4255d4: 4a 8d 7c 25 00 lea 0x0(%rbp,%r12,1),%rdi + 4255d9: 4c 29 e3 sub %r12,%rbx + 4255dc: 49 89 f8 mov %rdi,%r8 + 4255df: 49 29 c0 sub %rax,%r8 + 4255e2: 48 39 f8 cmp %rdi,%rax + 4255e5: b8 01 00 00 00 mov $0x1,%eax + 4255ea: 4c 0f 47 c0 cmova %rax,%r8 + 4255ee: 49 83 fc 1f cmp $0x1f,%r12 + 4255f2: 76 54 jbe 425648 <__strstr_sse2+0xf8> + 4255f4: 48 83 c4 58 add $0x58,%rsp + 4255f8: 4c 89 e1 mov %r12,%rcx + 4255fb: 48 89 da mov %rbx,%rdx + 4255fe: 4c 89 ff mov %r15,%rdi + 425601: 4c 89 c6 mov %r8,%rsi + 425604: 5b pop %rbx + 425605: 5d pop %rbp + 425606: 41 5c pop %r12 + 425608: 41 5d pop %r13 + 42560a: 41 5e pop %r14 + 42560c: 41 5f pop %r15 + 42560e: e9 2d fa ff ff jmpq 425040 + 425613: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 425618: 31 c0 xor %eax,%eax + 42561a: 48 83 c4 58 add $0x58,%rsp + 42561e: 5b pop %rbx + 42561f: 5d pop %rbp + 425620: 41 5c pop %r12 + 425622: 41 5d pop %r13 + 425624: 41 5e pop %r14 + 425626: 41 5f pop %r15 + 425628: c3 retq + 425629: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 425630: 48 83 c4 58 add $0x58,%rsp + 425634: 48 89 f8 mov %rdi,%rax + 425637: 5b pop %rbx + 425638: 5d pop %rbp + 425639: 41 5c pop %r12 + 42563b: 41 5d pop %r13 + 42563d: 41 5e pop %r14 + 42563f: 41 5f pop %r15 + 425641: c3 retq + 425642: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 425648: 41 be 01 00 00 00 mov $0x1,%r14d + 42564e: ba 01 00 00 00 mov $0x1,%edx + 425653: 31 f6 xor %esi,%esi + 425655: 48 c7 c1 ff ff ff ff mov $0xffffffffffffffff,%rcx + 42565c: 0f 1f 40 00 nopl 0x0(%rax) + 425660: 48 8d 04 32 lea (%rdx,%rsi,1),%rax + 425664: 49 39 c4 cmp %rax,%r12 + 425667: 76 29 jbe 425692 <__strstr_sse2+0x142> + 425669: 48 8d 3c 0b lea (%rbx,%rcx,1),%rdi + 42566d: 0f b6 3c 17 movzbl (%rdi,%rdx,1),%edi + 425671: 40 38 3c 03 cmp %dil,(%rbx,%rax,1) + 425675: 0f 83 f5 01 00 00 jae 425870 <__strstr_sse2+0x320> + 42567b: 48 89 c6 mov %rax,%rsi + 42567e: ba 01 00 00 00 mov $0x1,%edx + 425683: 49 89 c6 mov %rax,%r14 + 425686: 48 8d 04 32 lea (%rdx,%rsi,1),%rax + 42568a: 49 29 ce sub %rcx,%r14 + 42568d: 49 39 c4 cmp %rax,%r12 + 425690: 77 d7 ja 425669 <__strstr_sse2+0x119> + 425692: 41 bb 01 00 00 00 mov $0x1,%r11d + 425698: ba 01 00 00 00 mov $0x1,%edx + 42569d: 31 f6 xor %esi,%esi + 42569f: 48 c7 c7 ff ff ff ff mov $0xffffffffffffffff,%rdi + 4256a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4256ad: 00 00 00 + 4256b0: 48 8d 04 32 lea (%rdx,%rsi,1),%rax + 4256b4: 49 39 c4 cmp %rax,%r12 + 4256b7: 76 2a jbe 4256e3 <__strstr_sse2+0x193> + 4256b9: 4c 8d 0c 3b lea (%rbx,%rdi,1),%r9 + 4256bd: 45 0f b6 14 11 movzbl (%r9,%rdx,1),%r10d + 4256c2: 44 38 14 03 cmp %r10b,(%rbx,%rax,1) + 4256c6: 0f 86 c4 01 00 00 jbe 425890 <__strstr_sse2+0x340> + 4256cc: 48 89 c6 mov %rax,%rsi + 4256cf: ba 01 00 00 00 mov $0x1,%edx + 4256d4: 49 89 c3 mov %rax,%r11 + 4256d7: 48 8d 04 32 lea (%rdx,%rsi,1),%rax + 4256db: 49 29 fb sub %rdi,%r11 + 4256de: 49 39 c4 cmp %rax,%r12 + 4256e1: 77 d6 ja 4256b9 <__strstr_sse2+0x169> + 4256e3: 48 83 c7 01 add $0x1,%rdi + 4256e7: 48 83 c1 01 add $0x1,%rcx + 4256eb: 48 39 cf cmp %rcx,%rdi + 4256ee: 72 06 jb 4256f6 <__strstr_sse2+0x1a6> + 4256f0: 4d 89 de mov %r11,%r14 + 4256f3: 48 89 f9 mov %rdi,%rcx + 4256f6: 4a 8d 34 33 lea (%rbx,%r14,1),%rsi + 4256fa: 48 89 ca mov %rcx,%rdx + 4256fd: 48 89 df mov %rbx,%rdi + 425700: 4c 89 44 24 10 mov %r8,0x10(%rsp) + 425705: 48 89 4c 24 08 mov %rcx,0x8(%rsp) + 42570a: e8 21 ac fd ff callq 400330 <__rela_iplt_end+0x68> + 42570f: 85 c0 test %eax,%eax + 425711: 48 8b 4c 24 08 mov 0x8(%rsp),%rcx + 425716: 4c 8b 44 24 10 mov 0x10(%rsp),%r8 + 42571b: 0f 85 d1 01 00 00 jne 4258f2 <__strstr_sse2+0x3a2> + 425721: 48 8d 41 ff lea -0x1(%rcx),%rax + 425725: 4c 89 e7 mov %r12,%rdi + 425728: 45 31 ed xor %r13d,%r13d + 42572b: 4c 29 f7 sub %r14,%rdi + 42572e: 31 ed xor %ebp,%ebp + 425730: 4c 89 74 24 38 mov %r14,0x38(%rsp) + 425735: 48 89 44 24 18 mov %rax,0x18(%rsp) + 42573a: 48 89 7c 24 30 mov %rdi,0x30(%rsp) + 42573f: 48 01 d8 add %rbx,%rax + 425742: 48 89 cf mov %rcx,%rdi + 425745: 49 89 c2 mov %rax,%r10 + 425748: 48 89 44 24 28 mov %rax,0x28(%rsp) + 42574d: 48 f7 df neg %rdi + 425750: b8 01 00 00 00 mov $0x1,%eax + 425755: 4d 89 ee mov %r13,%r14 + 425758: 49 01 fa add %rdi,%r10 + 42575b: 48 29 c8 sub %rcx,%rax + 42575e: 48 89 7c 24 40 mov %rdi,0x40(%rsp) + 425763: 4d 89 e5 mov %r12,%r13 + 425766: 48 89 44 24 20 mov %rax,0x20(%rsp) + 42576b: 49 89 ec mov %rbp,%r12 + 42576e: 4c 89 c7 mov %r8,%rdi + 425771: 48 89 5c 24 10 mov %rbx,0x10(%rsp) + 425776: 4c 89 d5 mov %r10,%rbp + 425779: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 425780: 4b 8d 5c 25 00 lea 0x0(%r13,%r12,1),%rbx + 425785: 31 f6 xor %esi,%esi + 425787: 48 89 da mov %rbx,%rdx + 42578a: 48 29 fa sub %rdi,%rdx + 42578d: 4c 01 ff add %r15,%rdi + 425790: e8 ab 03 00 00 callq 425b40 <__memchr> + 425795: 48 85 c0 test %rax,%rax + 425798: 0f 85 7a fe ff ff jne 425618 <__strstr_sse2+0xc8> + 42579e: 48 85 db test %rbx,%rbx + 4257a1: 0f 84 71 fe ff ff je 425618 <__strstr_sse2+0xc8> + 4257a7: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 4257ac: 48 8b 4c 24 10 mov 0x10(%rsp),%rcx + 4257b1: 49 39 c6 cmp %rax,%r14 + 4257b4: 49 0f 43 c6 cmovae %r14,%rax + 4257b8: 4a 8d 34 20 lea (%rax,%r12,1),%rsi + 4257bc: 49 39 c5 cmp %rax,%r13 + 4257bf: 48 8d 14 01 lea (%rcx,%rax,1),%rdx + 4257c3: 49 8d 3c 37 lea (%r15,%rsi,1),%rdi + 4257c7: 76 36 jbe 4257ff <__strstr_sse2+0x2af> + 4257c9: 0f b6 0f movzbl (%rdi),%ecx + 4257cc: 38 0a cmp %cl,(%rdx) + 4257ce: 0f 85 dc 00 00 00 jne 4258b0 <__strstr_sse2+0x360> + 4257d4: 48 89 c6 mov %rax,%rsi + 4257d7: 48 f7 de neg %rsi + 4257da: 48 01 f2 add %rsi,%rdx + 4257dd: 48 01 fe add %rdi,%rsi + 4257e0: eb 14 jmp 4257f6 <__strstr_sse2+0x2a6> + 4257e2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4257e8: 0f b6 3c 06 movzbl (%rsi,%rax,1),%edi + 4257ec: 40 38 3c 02 cmp %dil,(%rdx,%rax,1) + 4257f0: 0f 85 ba 00 00 00 jne 4258b0 <__strstr_sse2+0x360> + 4257f6: 48 83 c0 01 add $0x1,%rax + 4257fa: 49 39 c5 cmp %rax,%r13 + 4257fd: 77 e9 ja 4257e8 <__strstr_sse2+0x298> + 4257ff: 48 8b 44 24 18 mov 0x18(%rsp),%rax + 425804: 49 8d 34 04 lea (%r12,%rax,1),%rsi + 425808: 4c 01 fe add %r15,%rsi + 42580b: 4c 3b 74 24 08 cmp 0x8(%rsp),%r14 + 425810: 0f 83 9d 02 00 00 jae 425ab3 <__strstr_sse2+0x563> + 425816: 48 8b 7c 24 28 mov 0x28(%rsp),%rdi + 42581b: 0f b6 0e movzbl (%rsi),%ecx + 42581e: 38 0f cmp %cl,(%rdi) + 425820: 0f 85 8d 02 00 00 jne 425ab3 <__strstr_sse2+0x563> + 425826: 48 03 74 24 40 add 0x40(%rsp),%rsi + 42582b: eb 15 jmp 425842 <__strstr_sse2+0x2f2> + 42582d: 0f 1f 00 nopl (%rax) + 425830: 48 8d 50 ff lea -0x1(%rax),%rdx + 425834: 0f b6 4c 32 01 movzbl 0x1(%rdx,%rsi,1),%ecx + 425839: 38 4c 05 00 cmp %cl,0x0(%rbp,%rax,1) + 42583d: 75 08 jne 425847 <__strstr_sse2+0x2f7> + 42583f: 48 89 d0 mov %rdx,%rax + 425842: 49 39 c6 cmp %rax,%r14 + 425845: 75 e9 jne 425830 <__strstr_sse2+0x2e0> + 425847: 4d 8d 4e 01 lea 0x1(%r14),%r9 + 42584b: 49 39 c1 cmp %rax,%r9 + 42584e: 0f 87 b6 02 00 00 ja 425b0a <__strstr_sse2+0x5ba> + 425854: 4c 03 64 24 38 add 0x38(%rsp),%r12 + 425859: 4c 8b 74 24 30 mov 0x30(%rsp),%r14 + 42585e: 48 89 df mov %rbx,%rdi + 425861: e9 1a ff ff ff jmpq 425780 <__strstr_sse2+0x230> + 425866: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42586d: 00 00 00 + 425870: 74 56 je 4258c8 <__strstr_sse2+0x378> + 425872: 48 89 f1 mov %rsi,%rcx + 425875: 41 be 01 00 00 00 mov $0x1,%r14d + 42587b: 48 83 c6 01 add $0x1,%rsi + 42587f: ba 01 00 00 00 mov $0x1,%edx + 425884: e9 d7 fd ff ff jmpq 425660 <__strstr_sse2+0x110> + 425889: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 425890: 74 4e je 4258e0 <__strstr_sse2+0x390> + 425892: 48 89 f7 mov %rsi,%rdi + 425895: 41 bb 01 00 00 00 mov $0x1,%r11d + 42589b: 48 83 c6 01 add $0x1,%rsi + 42589f: ba 01 00 00 00 mov $0x1,%edx + 4258a4: e9 07 fe ff ff jmpq 4256b0 <__strstr_sse2+0x160> + 4258a9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4258b0: 48 8b 4c 24 20 mov 0x20(%rsp),%rcx + 4258b5: 45 31 f6 xor %r14d,%r14d + 4258b8: 4e 8d 1c 21 lea (%rcx,%r12,1),%r11 + 4258bc: 4e 8d 24 18 lea (%rax,%r11,1),%r12 + 4258c0: eb 9c jmp 42585e <__strstr_sse2+0x30e> + 4258c2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4258c8: 4c 39 f2 cmp %r14,%rdx + 4258cb: 0f 84 ae 01 00 00 je 425a7f <__strstr_sse2+0x52f> + 4258d1: 48 83 c2 01 add $0x1,%rdx + 4258d5: e9 86 fd ff ff jmpq 425660 <__strstr_sse2+0x110> + 4258da: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4258e0: 4c 39 da cmp %r11,%rdx + 4258e3: 0f 84 a6 01 00 00 je 425a8f <__strstr_sse2+0x53f> + 4258e9: 48 83 c2 01 add $0x1,%rdx + 4258ed: e9 be fd ff ff jmpq 4256b0 <__strstr_sse2+0x160> + 4258f2: 4c 8d 51 01 lea 0x1(%rcx),%r10 + 4258f6: 49 8d 04 0f lea (%r15,%rcx,1),%rax + 4258fa: 48 8d 2c 0b lea (%rbx,%rcx,1),%rbp + 4258fe: 4d 39 d0 cmp %r10,%r8 + 425901: 48 89 44 24 18 mov %rax,0x18(%rsp) + 425906: 0f 82 b1 01 00 00 jb 425abd <__strstr_sse2+0x56d> + 42590c: 4c 89 e0 mov %r12,%rax + 42590f: 44 0f b6 4d 00 movzbl 0x0(%rbp),%r9d + 425914: 41 be 01 00 00 00 mov $0x1,%r14d + 42591a: 48 29 c8 sub %rcx,%rax + 42591d: 48 89 4c 24 38 mov %rcx,0x38(%rsp) + 425922: 48 8b 54 24 18 mov 0x18(%rsp),%rdx + 425927: 48 39 c8 cmp %rcx,%rax + 42592a: 4c 89 54 24 20 mov %r10,0x20(%rsp) + 42592f: 48 0f 42 c1 cmovb %rcx,%rax + 425933: 49 29 ce sub %rcx,%r14 + 425936: 48 83 c0 01 add $0x1,%rax + 42593a: 48 89 44 24 40 mov %rax,0x40(%rsp) + 42593f: 48 8d 41 ff lea -0x1(%rcx),%rax + 425943: 48 89 c7 mov %rax,%rdi + 425946: 48 89 44 24 48 mov %rax,0x48(%rsp) + 42594b: 4a 8d 04 13 lea (%rbx,%r10,1),%rax + 42594f: 48 01 fb add %rdi,%rbx + 425952: 48 89 cf mov %rcx,%rdi + 425955: 4c 89 f1 mov %r14,%rcx + 425958: 48 f7 df neg %rdi + 42595b: 49 89 c5 mov %rax,%r13 + 42595e: 4d 89 fe mov %r15,%r14 + 425961: 48 89 7c 24 30 mov %rdi,0x30(%rsp) + 425966: 49 01 fd add %rdi,%r13 + 425969: 49 89 df mov %rbx,%r15 + 42596c: 48 89 44 24 28 mov %rax,0x28(%rsp) + 425971: 4c 89 c7 mov %r8,%rdi + 425974: 44 89 cb mov %r9d,%ebx + 425977: eb 12 jmp 42598b <__strstr_sse2+0x43b> + 425979: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 425980: 84 c0 test %al,%al + 425982: 0f 84 90 fc ff ff je 425618 <__strstr_sse2+0xc8> + 425988: 48 89 ea mov %rbp,%rdx + 42598b: 0f b6 02 movzbl (%rdx),%eax + 42598e: 48 8d 6a 01 lea 0x1(%rdx),%rbp + 425992: 38 c3 cmp %al,%bl + 425994: 75 ea jne 425980 <__strstr_sse2+0x430> + 425996: 48 2b 6c 24 18 sub 0x18(%rsp),%rbp + 42599b: 4c 8b 54 24 20 mov 0x20(%rsp),%r10 + 4259a0: 4d 39 d4 cmp %r10,%r12 + 4259a3: 48 8d 45 ff lea -0x1(%rbp),%rax + 4259a7: 76 35 jbe 4259de <__strstr_sse2+0x48e> + 4259a9: 0f b6 72 01 movzbl 0x1(%rdx),%esi + 4259ad: 4c 8d 42 02 lea 0x2(%rdx),%r8 + 4259b1: 48 8b 54 24 28 mov 0x28(%rsp),%rdx + 4259b6: 40 38 32 cmp %sil,(%rdx) + 4259b9: 4c 89 d2 mov %r10,%rdx + 4259bc: 75 67 jne 425a25 <__strstr_sse2+0x4d5> + 4259be: 4c 03 44 24 30 add 0x30(%rsp),%r8 + 4259c3: eb 10 jmp 4259d5 <__strstr_sse2+0x485> + 4259c5: 0f 1f 00 nopl (%rax) + 4259c8: 41 0f b6 74 10 fe movzbl -0x2(%r8,%rdx,1),%esi + 4259ce: 41 38 74 15 ff cmp %sil,-0x1(%r13,%rdx,1) + 4259d3: 75 50 jne 425a25 <__strstr_sse2+0x4d5> + 4259d5: 48 83 c2 01 add $0x1,%rdx + 4259d9: 49 39 d4 cmp %rdx,%r12 + 4259dc: 77 ea ja 4259c8 <__strstr_sse2+0x478> + 4259de: 48 8b 74 24 48 mov 0x48(%rsp),%rsi + 4259e3: 48 8d 2c 30 lea (%rax,%rsi,1),%rbp + 4259e7: 4c 01 f5 add %r14,%rbp + 4259ea: 48 83 fe ff cmp $0xffffffffffffffff,%rsi + 4259ee: 74 2d je 425a1d <__strstr_sse2+0x4cd> + 4259f0: 0f b6 75 00 movzbl 0x0(%rbp),%esi + 4259f4: 31 d2 xor %edx,%edx + 4259f6: 41 3a 37 cmp (%r15),%sil + 4259f9: 74 1d je 425a18 <__strstr_sse2+0x4c8> + 4259fb: e9 9f 00 00 00 jmpq 425a9f <__strstr_sse2+0x54f> + 425a00: 45 0f b6 44 17 ff movzbl -0x1(%r15,%rdx,1),%r8d + 425a06: 48 83 ea 01 sub $0x1,%rdx + 425a0a: 0f b6 74 15 00 movzbl 0x0(%rbp,%rdx,1),%esi + 425a0f: 41 38 f0 cmp %sil,%r8b + 425a12: 0f 85 87 00 00 00 jne 425a9f <__strstr_sse2+0x54f> + 425a18: 48 39 d1 cmp %rdx,%rcx + 425a1b: 75 e3 jne 425a00 <__strstr_sse2+0x4b0> + 425a1d: 4c 01 f0 add %r14,%rax + 425a20: e9 f5 fb ff ff jmpq 42561a <__strstr_sse2+0xca> + 425a25: 40 84 f6 test %sil,%sil + 425a28: 0f 84 ea fb ff ff je 425618 <__strstr_sse2+0xc8> + 425a2e: 48 8d 2c 01 lea (%rcx,%rax,1),%rbp + 425a32: 48 01 d5 add %rdx,%rbp + 425a35: 4d 8d 04 2c lea (%r12,%rbp,1),%r8 + 425a39: 31 f6 xor %esi,%esi + 425a3b: 48 89 4c 24 10 mov %rcx,0x10(%rsp) + 425a40: 4c 89 c2 mov %r8,%rdx + 425a43: 4c 89 44 24 08 mov %r8,0x8(%rsp) + 425a48: 48 29 fa sub %rdi,%rdx + 425a4b: 4c 01 f7 add %r14,%rdi + 425a4e: e8 ed 00 00 00 callq 425b40 <__memchr> + 425a53: 4c 8b 44 24 08 mov 0x8(%rsp),%r8 + 425a58: 4d 85 c0 test %r8,%r8 + 425a5b: 0f 84 b7 fb ff ff je 425618 <__strstr_sse2+0xc8> + 425a61: 48 85 c0 test %rax,%rax + 425a64: 0f 85 ae fb ff ff jne 425618 <__strstr_sse2+0xc8> + 425a6a: 48 03 6c 24 38 add 0x38(%rsp),%rbp + 425a6f: 4c 89 c7 mov %r8,%rdi + 425a72: 48 8b 4c 24 10 mov 0x10(%rsp),%rcx + 425a77: 4c 01 f5 add %r14,%rbp + 425a7a: e9 09 ff ff ff jmpq 425988 <__strstr_sse2+0x438> + 425a7f: 49 89 d6 mov %rdx,%r14 + 425a82: 48 89 c6 mov %rax,%rsi + 425a85: ba 01 00 00 00 mov $0x1,%edx + 425a8a: e9 d1 fb ff ff jmpq 425660 <__strstr_sse2+0x110> + 425a8f: 49 89 d3 mov %rdx,%r11 + 425a92: 48 89 c6 mov %rax,%rsi + 425a95: ba 01 00 00 00 mov $0x1,%edx + 425a9a: e9 11 fc ff ff jmpq 4256b0 <__strstr_sse2+0x160> + 425a9f: 40 84 f6 test %sil,%sil + 425aa2: 0f 84 70 fb ff ff je 425618 <__strstr_sse2+0xc8> + 425aa8: 48 8b 74 24 40 mov 0x40(%rsp),%rsi + 425aad: 48 8d 2c 06 lea (%rsi,%rax,1),%rbp + 425ab1: eb 82 jmp 425a35 <__strstr_sse2+0x4e5> + 425ab3: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 425ab8: e9 8a fd ff ff jmpq 425847 <__strstr_sse2+0x2f7> + 425abd: 48 89 c8 mov %rcx,%rax + 425ac0: 4b 8d 3c 07 lea (%r15,%r8,1),%rdi + 425ac4: 31 f6 xor %esi,%esi + 425ac6: 4c 29 c0 sub %r8,%rax + 425ac9: 4c 89 54 24 10 mov %r10,0x10(%rsp) + 425ace: 48 89 4c 24 08 mov %rcx,0x8(%rsp) + 425ad3: 48 8d 50 01 lea 0x1(%rax),%rdx + 425ad7: e8 64 00 00 00 callq 425b40 <__memchr> + 425adc: 48 89 c2 mov %rax,%rdx + 425adf: 31 c0 xor %eax,%eax + 425ae1: 48 85 d2 test %rdx,%rdx + 425ae4: 0f 85 30 fb ff ff jne 42561a <__strstr_sse2+0xca> + 425aea: 4c 8b 54 24 10 mov 0x10(%rsp),%r10 + 425aef: 48 8b 4c 24 08 mov 0x8(%rsp),%rcx + 425af4: 4d 89 d0 mov %r10,%r8 + 425af7: e9 10 fe ff ff jmpq 42590c <__strstr_sse2+0x3bc> + 425afc: 48 89 f3 mov %rsi,%rbx + 425aff: 41 b9 01 00 00 00 mov $0x1,%r9d + 425b05: e9 9d fa ff ff jmpq 4255a7 <__strstr_sse2+0x57> + 425b0a: 4b 8d 04 27 lea (%r15,%r12,1),%rax + 425b0e: e9 07 fb ff ff jmpq 42561a <__strstr_sse2+0xca> + 425b13: 0f 1f 00 nopl (%rax) + 425b16: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 425b1d: 00 00 00 + +0000000000425b20 <__libc_strstr>: + 425b20: f6 05 99 6b 2a 00 10 testb $0x10,0x2a6b99(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> + 425b27: ba 50 55 42 00 mov $0x425550,%edx + 425b2c: b8 a0 d4 43 00 mov $0x43d4a0,%eax + 425b31: 48 0f 44 c2 cmove %rdx,%rax + 425b35: c3 retq + 425b36: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 425b3d: 00 00 00 + +0000000000425b40 <__memchr>: + 425b40: 66 48 0f 6e ce movq %rsi,%xmm1 + 425b45: 48 89 f9 mov %rdi,%rcx + 425b48: 66 0f 60 c9 punpcklbw %xmm1,%xmm1 + 425b4c: 48 85 d2 test %rdx,%rdx + 425b4f: 0f 84 2b 03 00 00 je 425e80 <__memchr+0x340> + 425b55: 66 0f 60 c9 punpcklbw %xmm1,%xmm1 + 425b59: 48 83 e1 3f and $0x3f,%rcx + 425b5d: 66 0f 70 c9 00 pshufd $0x0,%xmm1,%xmm1 + 425b62: 48 83 f9 30 cmp $0x30,%rcx + 425b66: 77 48 ja 425bb0 <__memchr+0x70> + 425b68: f3 0f 6f 07 movdqu (%rdi),%xmm0 + 425b6c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 425b70: 66 0f d7 c0 pmovmskb %xmm0,%eax + 425b74: 85 c0 test %eax,%eax + 425b76: 0f 85 c4 02 00 00 jne 425e40 <__memchr+0x300> + 425b7c: 48 83 ea 10 sub $0x10,%rdx + 425b80: 0f 86 fa 02 00 00 jbe 425e80 <__memchr+0x340> + 425b86: 48 83 c7 10 add $0x10,%rdi + 425b8a: 48 83 e1 0f and $0xf,%rcx + 425b8e: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi + 425b92: 48 01 ca add %rcx,%rdx + 425b95: 48 83 ea 40 sub $0x40,%rdx + 425b99: 0f 86 c1 01 00 00 jbe 425d60 <__memchr+0x220> + 425b9f: eb 5f jmp 425c00 <__memchr+0xc0> + 425ba1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 425ba6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 425bad: 00 00 00 + 425bb0: 48 83 e1 0f and $0xf,%rcx + 425bb4: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi + 425bb8: 66 0f 6f 07 movdqa (%rdi),%xmm0 + 425bbc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 425bc0: 66 0f d7 c0 pmovmskb %xmm0,%eax + 425bc4: d3 f8 sar %cl,%eax + 425bc6: 85 c0 test %eax,%eax + 425bc8: 74 16 je 425be0 <__memchr+0xa0> + 425bca: 0f bc c0 bsf %eax,%eax + 425bcd: 48 29 c2 sub %rax,%rdx + 425bd0: 0f 86 aa 02 00 00 jbe 425e80 <__memchr+0x340> + 425bd6: 48 01 f8 add %rdi,%rax + 425bd9: 48 01 c8 add %rcx,%rax + 425bdc: c3 retq + 425bdd: 0f 1f 00 nopl (%rax) + 425be0: 48 01 ca add %rcx,%rdx + 425be3: 48 83 ea 10 sub $0x10,%rdx + 425be7: 0f 86 93 02 00 00 jbe 425e80 <__memchr+0x340> + 425bed: 48 83 c7 10 add $0x10,%rdi + 425bf1: 48 83 ea 40 sub $0x40,%rdx + 425bf5: 0f 86 65 01 00 00 jbe 425d60 <__memchr+0x220> + 425bfb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 425c00: 66 0f 6f 07 movdqa (%rdi),%xmm0 + 425c04: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 425c08: 66 0f d7 c0 pmovmskb %xmm0,%eax + 425c0c: 85 c0 test %eax,%eax + 425c0e: 0f 85 fc 01 00 00 jne 425e10 <__memchr+0x2d0> + 425c14: 66 0f 6f 57 10 movdqa 0x10(%rdi),%xmm2 + 425c19: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 425c1d: 66 0f d7 c2 pmovmskb %xmm2,%eax + 425c21: 85 c0 test %eax,%eax + 425c23: 0f 85 f7 01 00 00 jne 425e20 <__memchr+0x2e0> + 425c29: 66 0f 6f 5f 20 movdqa 0x20(%rdi),%xmm3 + 425c2e: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 + 425c32: 66 0f d7 c3 pmovmskb %xmm3,%eax + 425c36: 85 c0 test %eax,%eax + 425c38: 0f 85 f2 01 00 00 jne 425e30 <__memchr+0x2f0> + 425c3e: 66 0f 6f 67 30 movdqa 0x30(%rdi),%xmm4 + 425c43: 66 0f 74 e1 pcmpeqb %xmm1,%xmm4 + 425c47: 48 83 c7 40 add $0x40,%rdi + 425c4b: 66 0f d7 c4 pmovmskb %xmm4,%eax + 425c4f: 85 c0 test %eax,%eax + 425c51: 0f 85 a9 01 00 00 jne 425e00 <__memchr+0x2c0> + 425c57: 48 f7 c7 3f 00 00 00 test $0x3f,%rdi + 425c5e: 74 70 je 425cd0 <__memchr+0x190> + 425c60: 48 83 ea 40 sub $0x40,%rdx + 425c64: 0f 86 f6 00 00 00 jbe 425d60 <__memchr+0x220> + 425c6a: 66 0f 6f 07 movdqa (%rdi),%xmm0 + 425c6e: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 425c72: 66 0f d7 c0 pmovmskb %xmm0,%eax + 425c76: 85 c0 test %eax,%eax + 425c78: 0f 85 92 01 00 00 jne 425e10 <__memchr+0x2d0> + 425c7e: 66 0f 6f 57 10 movdqa 0x10(%rdi),%xmm2 + 425c83: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 425c87: 66 0f d7 c2 pmovmskb %xmm2,%eax + 425c8b: 85 c0 test %eax,%eax + 425c8d: 0f 85 8d 01 00 00 jne 425e20 <__memchr+0x2e0> + 425c93: 66 0f 6f 5f 20 movdqa 0x20(%rdi),%xmm3 + 425c98: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 + 425c9c: 66 0f d7 c3 pmovmskb %xmm3,%eax + 425ca0: 85 c0 test %eax,%eax + 425ca2: 0f 85 88 01 00 00 jne 425e30 <__memchr+0x2f0> + 425ca8: 66 0f 6f 5f 30 movdqa 0x30(%rdi),%xmm3 + 425cad: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 + 425cb1: 66 0f d7 c3 pmovmskb %xmm3,%eax + 425cb5: 48 83 c7 40 add $0x40,%rdi + 425cb9: 85 c0 test %eax,%eax + 425cbb: 0f 85 3f 01 00 00 jne 425e00 <__memchr+0x2c0> + 425cc1: 48 89 f9 mov %rdi,%rcx + 425cc4: 48 83 e7 c0 and $0xffffffffffffffc0,%rdi + 425cc8: 48 83 e1 3f and $0x3f,%rcx + 425ccc: 48 01 ca add %rcx,%rdx + 425ccf: 90 nop + 425cd0: 48 83 ea 40 sub $0x40,%rdx + 425cd4: 0f 86 86 00 00 00 jbe 425d60 <__memchr+0x220> + 425cda: 66 0f 6f 07 movdqa (%rdi),%xmm0 + 425cde: 66 0f 6f 57 10 movdqa 0x10(%rdi),%xmm2 + 425ce3: 66 0f 6f 5f 20 movdqa 0x20(%rdi),%xmm3 + 425ce8: 66 0f 6f 67 30 movdqa 0x30(%rdi),%xmm4 + 425ced: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 425cf1: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 425cf5: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 + 425cf9: 66 0f 74 e1 pcmpeqb %xmm1,%xmm4 + 425cfd: 66 0f de d8 pmaxub %xmm0,%xmm3 + 425d01: 66 0f de e2 pmaxub %xmm2,%xmm4 + 425d05: 66 0f de e3 pmaxub %xmm3,%xmm4 + 425d09: 66 0f d7 c4 pmovmskb %xmm4,%eax + 425d0d: 48 83 c7 40 add $0x40,%rdi + 425d11: 85 c0 test %eax,%eax + 425d13: 74 bb je 425cd0 <__memchr+0x190> + 425d15: 48 83 ef 40 sub $0x40,%rdi + 425d19: 66 0f d7 c0 pmovmskb %xmm0,%eax + 425d1d: 85 c0 test %eax,%eax + 425d1f: 0f 85 eb 00 00 00 jne 425e10 <__memchr+0x2d0> + 425d25: 66 0f d7 c2 pmovmskb %xmm2,%eax + 425d29: 85 c0 test %eax,%eax + 425d2b: 0f 85 ef 00 00 00 jne 425e20 <__memchr+0x2e0> + 425d31: 66 0f 6f 5f 20 movdqa 0x20(%rdi),%xmm3 + 425d36: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 + 425d3a: 66 0f 74 4f 30 pcmpeqb 0x30(%rdi),%xmm1 + 425d3f: 66 0f d7 c3 pmovmskb %xmm3,%eax + 425d43: 85 c0 test %eax,%eax + 425d45: 0f 85 e5 00 00 00 jne 425e30 <__memchr+0x2f0> + 425d4b: 66 0f d7 c1 pmovmskb %xmm1,%eax + 425d4f: 0f bc c0 bsf %eax,%eax + 425d52: 48 8d 44 07 30 lea 0x30(%rdi,%rax,1),%rax + 425d57: c3 retq + 425d58: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 425d5f: 00 + 425d60: 48 83 c2 20 add $0x20,%rdx + 425d64: 7e 6a jle 425dd0 <__memchr+0x290> + 425d66: 66 0f 6f 07 movdqa (%rdi),%xmm0 + 425d6a: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 425d6e: 66 0f d7 c0 pmovmskb %xmm0,%eax + 425d72: 85 c0 test %eax,%eax + 425d74: 0f 85 96 00 00 00 jne 425e10 <__memchr+0x2d0> + 425d7a: 66 0f 6f 57 10 movdqa 0x10(%rdi),%xmm2 + 425d7f: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 425d83: 66 0f d7 c2 pmovmskb %xmm2,%eax + 425d87: 85 c0 test %eax,%eax + 425d89: 0f 85 91 00 00 00 jne 425e20 <__memchr+0x2e0> + 425d8f: 66 0f 6f 5f 20 movdqa 0x20(%rdi),%xmm3 + 425d94: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 + 425d98: 66 0f d7 c3 pmovmskb %xmm3,%eax + 425d9c: 85 c0 test %eax,%eax + 425d9e: 0f 85 bc 00 00 00 jne 425e60 <__memchr+0x320> + 425da4: 48 83 ea 10 sub $0x10,%rdx + 425da8: 0f 8e d2 00 00 00 jle 425e80 <__memchr+0x340> + 425dae: 66 0f 74 4f 30 pcmpeqb 0x30(%rdi),%xmm1 + 425db3: 66 0f d7 c1 pmovmskb %xmm1,%eax + 425db7: 85 c0 test %eax,%eax + 425db9: 0f 85 b1 00 00 00 jne 425e70 <__memchr+0x330> + 425dbf: 48 31 c0 xor %rax,%rax + 425dc2: c3 retq + 425dc3: 0f 1f 00 nopl (%rax) + 425dc6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 425dcd: 00 00 00 + 425dd0: 48 83 c2 20 add $0x20,%rdx + 425dd4: 66 0f 6f 07 movdqa (%rdi),%xmm0 + 425dd8: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 425ddc: 66 0f d7 c0 pmovmskb %xmm0,%eax + 425de0: 85 c0 test %eax,%eax + 425de2: 75 5c jne 425e40 <__memchr+0x300> + 425de4: 48 83 ea 10 sub $0x10,%rdx + 425de8: 0f 86 92 00 00 00 jbe 425e80 <__memchr+0x340> + 425dee: 66 0f 74 4f 10 pcmpeqb 0x10(%rdi),%xmm1 + 425df3: 66 0f d7 c1 pmovmskb %xmm1,%eax + 425df7: 85 c0 test %eax,%eax + 425df9: 75 55 jne 425e50 <__memchr+0x310> + 425dfb: 48 31 c0 xor %rax,%rax + 425dfe: c3 retq + 425dff: 90 nop + 425e00: 0f bc c0 bsf %eax,%eax + 425e03: 48 8d 44 38 f0 lea -0x10(%rax,%rdi,1),%rax + 425e08: c3 retq + 425e09: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 425e10: 0f bc c0 bsf %eax,%eax + 425e13: 48 01 f8 add %rdi,%rax + 425e16: c3 retq + 425e17: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 425e1e: 00 00 + 425e20: 0f bc c0 bsf %eax,%eax + 425e23: 48 8d 44 38 10 lea 0x10(%rax,%rdi,1),%rax + 425e28: c3 retq + 425e29: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 425e30: 0f bc c0 bsf %eax,%eax + 425e33: 48 8d 44 38 20 lea 0x20(%rax,%rdi,1),%rax + 425e38: c3 retq + 425e39: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 425e40: 0f bc c0 bsf %eax,%eax + 425e43: 48 29 c2 sub %rax,%rdx + 425e46: 76 38 jbe 425e80 <__memchr+0x340> + 425e48: 48 01 f8 add %rdi,%rax + 425e4b: c3 retq + 425e4c: 0f 1f 40 00 nopl 0x0(%rax) + 425e50: 0f bc c0 bsf %eax,%eax + 425e53: 48 29 c2 sub %rax,%rdx + 425e56: 76 28 jbe 425e80 <__memchr+0x340> + 425e58: 48 8d 44 07 10 lea 0x10(%rdi,%rax,1),%rax + 425e5d: c3 retq + 425e5e: 66 90 xchg %ax,%ax + 425e60: 0f bc c0 bsf %eax,%eax + 425e63: 48 29 c2 sub %rax,%rdx + 425e66: 76 18 jbe 425e80 <__memchr+0x340> + 425e68: 48 8d 44 07 20 lea 0x20(%rdi,%rax,1),%rax + 425e6d: c3 retq + 425e6e: 66 90 xchg %ax,%ax + 425e70: 0f bc c0 bsf %eax,%eax + 425e73: 48 29 c2 sub %rax,%rdx + 425e76: 76 08 jbe 425e80 <__memchr+0x340> + 425e78: 48 8d 44 07 30 lea 0x30(%rdi,%rax,1),%rax + 425e7d: c3 retq + 425e7e: 66 90 xchg %ax,%ax + 425e80: 48 31 c0 xor %rax,%rax + 425e83: c3 retq + 425e84: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 425e8b: 00 00 00 + 425e8e: 66 90 xchg %ax,%ax + +0000000000425e90 : + 425e90: f7 05 f6 67 2a 00 00 testl $0x200,0x2a67f6(%rip) # 6cc690 <_dl_x86_cpu_features+0x10> + 425e97: 02 00 00 + 425e9a: 75 08 jne 425ea4 + 425e9c: 48 8d 05 1d 00 00 00 lea 0x1d(%rip),%rax # 425ec0 <__memcmp_sse2> + 425ea3: c3 retq + 425ea4: f7 05 e2 67 2a 00 00 testl $0x80000,0x2a67e2(%rip) # 6cc690 <_dl_x86_cpu_features+0x10> + 425eab: 00 08 00 + 425eae: 74 08 je 425eb8 + 425eb0: 48 8d 05 49 84 00 00 lea 0x8449(%rip),%rax # 42e300 <__memcmp_sse4_1> + 425eb7: c3 retq + 425eb8: 48 8d 05 71 5e 01 00 lea 0x15e71(%rip),%rax # 43bd30 <__memcmp_ssse3> + 425ebf: c3 retq + +0000000000425ec0 <__memcmp_sse2>: + 425ec0: 48 85 d2 test %rdx,%rdx + 425ec3: 0f 84 f7 00 00 00 je 425fc0 <__memcmp_sse2+0x100> + 425ec9: 48 83 fa 01 cmp $0x1,%rdx + 425ecd: 0f 8e bd 00 00 00 jle 425f90 <__memcmp_sse2+0xd0> + 425ed3: 48 29 fe sub %rdi,%rsi + 425ed6: 49 89 d2 mov %rdx,%r10 + 425ed9: 49 83 fa 20 cmp $0x20,%r10 + 425edd: 0f 8d e0 00 00 00 jge 425fc3 <__memcmp_sse2+0x103> + 425ee3: 49 f7 c2 01 00 00 00 test $0x1,%r10 + 425eea: 74 1d je 425f09 <__memcmp_sse2+0x49> + 425eec: 0f b6 07 movzbl (%rdi),%eax + 425eef: 0f b6 14 37 movzbl (%rdi,%rsi,1),%edx + 425ef3: 49 83 ea 01 sub $0x1,%r10 + 425ef7: 0f 84 99 00 00 00 je 425f96 <__memcmp_sse2+0xd6> + 425efd: 48 83 c7 01 add $0x1,%rdi + 425f01: 29 d0 sub %edx,%eax + 425f03: 0f 85 8f 00 00 00 jne 425f98 <__memcmp_sse2+0xd8> + 425f09: 49 f7 c2 02 00 00 00 test $0x2,%r10 + 425f10: 74 15 je 425f27 <__memcmp_sse2+0x67> + 425f12: 0f b7 07 movzwl (%rdi),%eax + 425f15: 0f b7 14 37 movzwl (%rdi,%rsi,1),%edx + 425f19: 49 83 ea 02 sub $0x2,%r10 + 425f1d: 74 7a je 425f99 <__memcmp_sse2+0xd9> + 425f1f: 48 83 c7 02 add $0x2,%rdi + 425f23: 39 d0 cmp %edx,%eax + 425f25: 75 72 jne 425f99 <__memcmp_sse2+0xd9> + 425f27: 49 f7 c2 04 00 00 00 test $0x4,%r10 + 425f2e: 74 13 je 425f43 <__memcmp_sse2+0x83> + 425f30: 8b 07 mov (%rdi),%eax + 425f32: 8b 14 37 mov (%rdi,%rsi,1),%edx + 425f35: 49 83 ea 04 sub $0x4,%r10 + 425f39: 74 5e je 425f99 <__memcmp_sse2+0xd9> + 425f3b: 48 83 c7 04 add $0x4,%rdi + 425f3f: 39 d0 cmp %edx,%eax + 425f41: 75 56 jne 425f99 <__memcmp_sse2+0xd9> + 425f43: 49 f7 c2 08 00 00 00 test $0x8,%r10 + 425f4a: 74 16 je 425f62 <__memcmp_sse2+0xa2> + 425f4c: 48 8b 07 mov (%rdi),%rax + 425f4f: 48 8b 14 37 mov (%rdi,%rsi,1),%rdx + 425f53: 49 83 ea 08 sub $0x8,%r10 + 425f57: 74 40 je 425f99 <__memcmp_sse2+0xd9> + 425f59: 48 83 c7 08 add $0x8,%rdi + 425f5d: 48 39 d0 cmp %rdx,%rax + 425f60: 75 37 jne 425f99 <__memcmp_sse2+0xd9> + 425f62: f3 0f 6f 0f movdqu (%rdi),%xmm1 + 425f66: f3 0f 6f 04 37 movdqu (%rdi,%rsi,1),%xmm0 + 425f6b: 66 0f 74 c8 pcmpeqb %xmm0,%xmm1 + 425f6f: 66 0f d7 d1 pmovmskb %xmm1,%edx + 425f73: 31 c0 xor %eax,%eax + 425f75: 81 ea ff ff 00 00 sub $0xffff,%edx + 425f7b: 74 43 je 425fc0 <__memcmp_sse2+0x100> + 425f7d: 0f bc ca bsf %edx,%ecx + 425f80: 48 8d 0c 0f lea (%rdi,%rcx,1),%rcx + 425f84: 0f b6 01 movzbl (%rcx),%eax + 425f87: 0f b6 14 0e movzbl (%rsi,%rcx,1),%edx + 425f8b: eb 09 jmp 425f96 <__memcmp_sse2+0xd6> + 425f8d: 0f 1f 00 nopl (%rax) + 425f90: 0f b6 07 movzbl (%rdi),%eax + 425f93: 0f b6 16 movzbl (%rsi),%edx + 425f96: 29 d0 sub %edx,%eax + 425f98: c3 retq + 425f99: 48 39 d0 cmp %rdx,%rax + 425f9c: 74 22 je 425fc0 <__memcmp_sse2+0x100> + 425f9e: 49 89 c3 mov %rax,%r11 + 425fa1: 49 29 d3 sub %rdx,%r11 + 425fa4: 49 0f bc cb bsf %r11,%rcx + 425fa8: 48 c1 f9 03 sar $0x3,%rcx + 425fac: 48 c1 e1 03 shl $0x3,%rcx + 425fb0: 48 d3 f8 sar %cl,%rax + 425fb3: 0f b6 c0 movzbl %al,%eax + 425fb6: 48 d3 fa sar %cl,%rdx + 425fb9: 0f b6 d2 movzbl %dl,%edx + 425fbc: 29 d0 sub %edx,%eax + 425fbe: c3 retq + 425fbf: 90 nop + 425fc0: 31 c0 xor %eax,%eax + 425fc2: c3 retq + 425fc3: 49 89 d3 mov %rdx,%r11 + 425fc6: 49 01 fb add %rdi,%r11 + 425fc9: 49 89 f8 mov %rdi,%r8 + 425fcc: 49 83 e0 0f and $0xf,%r8 + 425fd0: 74 25 je 425ff7 <__memcmp_sse2+0x137> + 425fd2: f3 0f 6f 0f movdqu (%rdi),%xmm1 + 425fd6: f3 0f 6f 04 37 movdqu (%rdi,%rsi,1),%xmm0 + 425fdb: 66 0f 74 c8 pcmpeqb %xmm0,%xmm1 + 425fdf: 66 0f d7 d1 pmovmskb %xmm1,%edx + 425fe3: 81 ea ff ff 00 00 sub $0xffff,%edx + 425fe9: 0f 85 61 01 00 00 jne 426150 <__memcmp_sse2+0x290> + 425fef: 49 f7 d8 neg %r8 + 425ff2: 4a 8d 7c 07 10 lea 0x10(%rdi,%r8,1),%rdi + 425ff7: 48 f7 c6 0f 00 00 00 test $0xf,%rsi + 425ffe: 0f 84 5f 01 00 00 je 426163 <__memcmp_sse2+0x2a3> + 426004: 48 f7 c7 10 00 00 00 test $0x10,%rdi + 42600b: 74 1d je 42602a <__memcmp_sse2+0x16a> + 42600d: f3 0f 6f 04 37 movdqu (%rdi,%rsi,1),%xmm0 + 426012: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 426016: 66 0f d7 d0 pmovmskb %xmm0,%edx + 42601a: 81 ea ff ff 00 00 sub $0xffff,%edx + 426020: 0f 85 2a 01 00 00 jne 426150 <__memcmp_sse2+0x290> + 426026: 48 83 c7 10 add $0x10,%rdi + 42602a: 4d 89 da mov %r11,%r10 + 42602d: 49 83 e2 e0 and $0xffffffffffffffe0,%r10 + 426031: 4c 39 d7 cmp %r10,%rdi + 426034: 0f 8d 03 01 00 00 jge 42613d <__memcmp_sse2+0x27d> + 42603a: 48 f7 c7 20 00 00 00 test $0x20,%rdi + 426041: 74 3a je 42607d <__memcmp_sse2+0x1bd> + 426043: f3 0f 6f 04 37 movdqu (%rdi,%rsi,1),%xmm0 + 426048: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 42604c: 66 0f d7 d0 pmovmskb %xmm0,%edx + 426050: 81 ea ff ff 00 00 sub $0xffff,%edx + 426056: 0f 85 f4 00 00 00 jne 426150 <__memcmp_sse2+0x290> + 42605c: 48 83 c7 10 add $0x10,%rdi + 426060: f3 0f 6f 04 37 movdqu (%rdi,%rsi,1),%xmm0 + 426065: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 426069: 66 0f d7 d0 pmovmskb %xmm0,%edx + 42606d: 81 ea ff ff 00 00 sub $0xffff,%edx + 426073: 0f 85 d7 00 00 00 jne 426150 <__memcmp_sse2+0x290> + 426079: 48 83 c7 10 add $0x10,%rdi + 42607d: 4d 89 da mov %r11,%r10 + 426080: 49 83 e2 c0 and $0xffffffffffffffc0,%r10 + 426084: 4c 39 d7 cmp %r10,%rdi + 426087: 7d 71 jge 4260fa <__memcmp_sse2+0x23a> + 426089: f3 0f 6f 04 37 movdqu (%rdi,%rsi,1),%xmm0 + 42608e: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 426092: 66 0f d7 d0 pmovmskb %xmm0,%edx + 426096: 81 ea ff ff 00 00 sub $0xffff,%edx + 42609c: 0f 85 ae 00 00 00 jne 426150 <__memcmp_sse2+0x290> + 4260a2: 48 83 c7 10 add $0x10,%rdi + 4260a6: f3 0f 6f 04 37 movdqu (%rdi,%rsi,1),%xmm0 + 4260ab: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 4260af: 66 0f d7 d0 pmovmskb %xmm0,%edx + 4260b3: 81 ea ff ff 00 00 sub $0xffff,%edx + 4260b9: 0f 85 91 00 00 00 jne 426150 <__memcmp_sse2+0x290> + 4260bf: 48 83 c7 10 add $0x10,%rdi + 4260c3: f3 0f 6f 04 37 movdqu (%rdi,%rsi,1),%xmm0 + 4260c8: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 4260cc: 66 0f d7 d0 pmovmskb %xmm0,%edx + 4260d0: 81 ea ff ff 00 00 sub $0xffff,%edx + 4260d6: 75 78 jne 426150 <__memcmp_sse2+0x290> + 4260d8: 48 83 c7 10 add $0x10,%rdi + 4260dc: f3 0f 6f 04 37 movdqu (%rdi,%rsi,1),%xmm0 + 4260e1: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 4260e5: 66 0f d7 d0 pmovmskb %xmm0,%edx + 4260e9: 81 ea ff ff 00 00 sub $0xffff,%edx + 4260ef: 75 5f jne 426150 <__memcmp_sse2+0x290> + 4260f1: 48 83 c7 10 add $0x10,%rdi + 4260f5: 49 39 fa cmp %rdi,%r10 + 4260f8: 75 8f jne 426089 <__memcmp_sse2+0x1c9> + 4260fa: 4d 89 da mov %r11,%r10 + 4260fd: 49 83 e2 e0 and $0xffffffffffffffe0,%r10 + 426101: 4c 39 d7 cmp %r10,%rdi + 426104: 7d 37 jge 42613d <__memcmp_sse2+0x27d> + 426106: f3 0f 6f 04 37 movdqu (%rdi,%rsi,1),%xmm0 + 42610b: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 42610f: 66 0f d7 d0 pmovmskb %xmm0,%edx + 426113: 81 ea ff ff 00 00 sub $0xffff,%edx + 426119: 75 35 jne 426150 <__memcmp_sse2+0x290> + 42611b: 48 83 c7 10 add $0x10,%rdi + 42611f: f3 0f 6f 04 37 movdqu (%rdi,%rsi,1),%xmm0 + 426124: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 426128: 66 0f d7 d0 pmovmskb %xmm0,%edx + 42612c: 81 ea ff ff 00 00 sub $0xffff,%edx + 426132: 75 1c jne 426150 <__memcmp_sse2+0x290> + 426134: 48 83 c7 10 add $0x10,%rdi + 426138: 49 39 fa cmp %rdi,%r10 + 42613b: 75 c9 jne 426106 <__memcmp_sse2+0x246> + 42613d: 49 29 fb sub %rdi,%r11 + 426140: 0f 84 7a fe ff ff je 425fc0 <__memcmp_sse2+0x100> + 426146: 4d 89 da mov %r11,%r10 + 426149: e9 95 fd ff ff jmpq 425ee3 <__memcmp_sse2+0x23> + 42614e: 66 90 xchg %ax,%ax + 426150: 0f bc ca bsf %edx,%ecx + 426153: 0f b6 04 0f movzbl (%rdi,%rcx,1),%eax + 426157: 48 01 fe add %rdi,%rsi + 42615a: 0f b6 14 0e movzbl (%rsi,%rcx,1),%edx + 42615e: e9 33 fe ff ff jmpq 425f96 <__memcmp_sse2+0xd6> + 426163: 4d 89 da mov %r11,%r10 + 426166: 49 83 e2 e0 and $0xffffffffffffffe0,%r10 + 42616a: 4c 39 d7 cmp %r10,%rdi + 42616d: 7d ce jge 42613d <__memcmp_sse2+0x27d> + 42616f: 48 f7 c7 10 00 00 00 test $0x10,%rdi + 426176: 74 1e je 426196 <__memcmp_sse2+0x2d6> + 426178: 66 0f 6f 04 37 movdqa (%rdi,%rsi,1),%xmm0 + 42617d: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 426181: 66 0f d7 d0 pmovmskb %xmm0,%edx + 426185: 81 ea ff ff 00 00 sub $0xffff,%edx + 42618b: 75 c3 jne 426150 <__memcmp_sse2+0x290> + 42618d: 48 83 c7 10 add $0x10,%rdi + 426191: 49 39 fa cmp %rdi,%r10 + 426194: 74 a7 je 42613d <__memcmp_sse2+0x27d> + 426196: 4d 89 da mov %r11,%r10 + 426199: 49 83 e2 c0 and $0xffffffffffffffc0,%r10 + 42619d: 48 f7 c7 20 00 00 00 test $0x20,%rdi + 4261a4: 74 36 je 4261dc <__memcmp_sse2+0x31c> + 4261a6: 66 0f 6f 04 37 movdqa (%rdi,%rsi,1),%xmm0 + 4261ab: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 4261af: 66 0f d7 d0 pmovmskb %xmm0,%edx + 4261b3: 81 ea ff ff 00 00 sub $0xffff,%edx + 4261b9: 75 95 jne 426150 <__memcmp_sse2+0x290> + 4261bb: 48 83 c7 10 add $0x10,%rdi + 4261bf: 66 0f 6f 04 37 movdqa (%rdi,%rsi,1),%xmm0 + 4261c4: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 4261c8: 66 0f d7 d0 pmovmskb %xmm0,%edx + 4261cc: 81 ea ff ff 00 00 sub $0xffff,%edx + 4261d2: 0f 85 78 ff ff ff jne 426150 <__memcmp_sse2+0x290> + 4261d8: 48 83 c7 10 add $0x10,%rdi + 4261dc: 49 39 fa cmp %rdi,%r10 + 4261df: 0f 84 15 ff ff ff je 4260fa <__memcmp_sse2+0x23a> + 4261e5: 66 0f 6f 04 37 movdqa (%rdi,%rsi,1),%xmm0 + 4261ea: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 4261ee: 66 0f d7 d0 pmovmskb %xmm0,%edx + 4261f2: 81 ea ff ff 00 00 sub $0xffff,%edx + 4261f8: 0f 85 52 ff ff ff jne 426150 <__memcmp_sse2+0x290> + 4261fe: 48 83 c7 10 add $0x10,%rdi + 426202: 66 0f 6f 04 37 movdqa (%rdi,%rsi,1),%xmm0 + 426207: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 42620b: 66 0f d7 d0 pmovmskb %xmm0,%edx + 42620f: 81 ea ff ff 00 00 sub $0xffff,%edx + 426215: 0f 85 35 ff ff ff jne 426150 <__memcmp_sse2+0x290> + 42621b: 48 83 c7 10 add $0x10,%rdi + 42621f: 66 0f 6f 04 37 movdqa (%rdi,%rsi,1),%xmm0 + 426224: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 426228: 66 0f d7 d0 pmovmskb %xmm0,%edx + 42622c: 81 ea ff ff 00 00 sub $0xffff,%edx + 426232: 0f 85 18 ff ff ff jne 426150 <__memcmp_sse2+0x290> + 426238: 48 83 c7 10 add $0x10,%rdi + 42623c: 66 0f 6f 04 37 movdqa (%rdi,%rsi,1),%xmm0 + 426241: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 426245: 66 0f d7 d0 pmovmskb %xmm0,%edx + 426249: 81 ea ff ff 00 00 sub $0xffff,%edx + 42624f: 0f 85 fb fe ff ff jne 426150 <__memcmp_sse2+0x290> + 426255: 48 83 c7 10 add $0x10,%rdi + 426259: 49 39 fa cmp %rdi,%r10 + 42625c: 75 87 jne 4261e5 <__memcmp_sse2+0x325> + 42625e: 4d 89 da mov %r11,%r10 + 426261: 49 83 e2 e0 and $0xffffffffffffffe0,%r10 + 426265: 4c 39 d7 cmp %r10,%rdi + 426268: 0f 8d cf fe ff ff jge 42613d <__memcmp_sse2+0x27d> + 42626e: 66 0f 6f 04 37 movdqa (%rdi,%rsi,1),%xmm0 + 426273: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 426277: 66 0f d7 d0 pmovmskb %xmm0,%edx + 42627b: 81 ea ff ff 00 00 sub $0xffff,%edx + 426281: 0f 85 c9 fe ff ff jne 426150 <__memcmp_sse2+0x290> + 426287: 48 83 c7 10 add $0x10,%rdi + 42628b: 66 0f 6f 04 37 movdqa (%rdi,%rsi,1),%xmm0 + 426290: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 426294: 66 0f d7 d0 pmovmskb %xmm0,%edx + 426298: 81 ea ff ff 00 00 sub $0xffff,%edx + 42629e: 0f 85 ac fe ff ff jne 426150 <__memcmp_sse2+0x290> + 4262a4: 48 83 c7 10 add $0x10,%rdi + 4262a8: 4c 39 d7 cmp %r10,%rdi + 4262ab: 75 c1 jne 42626e <__memcmp_sse2+0x3ae> + 4262ad: 49 29 fb sub %rdi,%r11 + 4262b0: 0f 84 0a fd ff ff je 425fc0 <__memcmp_sse2+0x100> + 4262b6: 4d 89 da mov %r11,%r10 + 4262b9: e9 25 fc ff ff jmpq 425ee3 <__memcmp_sse2+0x23> + 4262be: 66 90 xchg %ax,%ax + +00000000004262c0 <__memmove_sse2>: + 4262c0: 41 55 push %r13 + 4262c2: 48 89 f8 mov %rdi,%rax + 4262c5: 41 54 push %r12 + 4262c7: 55 push %rbp + 4262c8: 53 push %rbx + 4262c9: 48 29 f0 sub %rsi,%rax + 4262cc: 49 89 fc mov %rdi,%r12 + 4262cf: 48 83 ec 08 sub $0x8,%rsp + 4262d3: 48 39 d0 cmp %rdx,%rax + 4262d6: 0f 82 99 00 00 00 jb 426375 <__memmove_sse2+0xb5> + 4262dc: 48 83 fa 0f cmp $0xf,%rdx + 4262e0: 48 89 fb mov %rdi,%rbx + 4262e3: 49 89 f5 mov %rsi,%r13 + 4262e6: 76 5e jbe 426346 <__memmove_sse2+0x86> + 4262e8: 48 89 f9 mov %rdi,%rcx + 4262eb: 48 f7 d9 neg %rcx + 4262ee: 83 e1 07 and $0x7,%ecx + 4262f1: 48 29 ca sub %rcx,%rdx + 4262f4: 48 85 c9 test %rcx,%rcx + 4262f7: 48 89 d5 mov %rdx,%rbp + 4262fa: 74 1b je 426317 <__memmove_sse2+0x57> + 4262fc: 31 c0 xor %eax,%eax + 4262fe: 0f b6 14 06 movzbl (%rsi,%rax,1),%edx + 426302: 41 88 14 04 mov %dl,(%r12,%rax,1) + 426306: 48 83 c0 01 add $0x1,%rax + 42630a: 48 39 c1 cmp %rax,%rcx + 42630d: 75 ef jne 4262fe <__memmove_sse2+0x3e> + 42630f: 4c 8d 2c 0e lea (%rsi,%rcx,1),%r13 + 426313: 49 8d 1c 0c lea (%r12,%rcx,1),%rbx + 426317: 48 89 ea mov %rbp,%rdx + 42631a: 4c 89 ee mov %r13,%rsi + 42631d: 48 89 df mov %rbx,%rdi + 426320: 48 c1 ea 03 shr $0x3,%rdx + 426324: 41 f6 c5 07 test $0x7,%r13b + 426328: 0f 84 dc 00 00 00 je 42640a <__memmove_sse2+0x14a> + 42632e: e8 8d 62 00 00 callq 42c5c0 <_wordcopy_fwd_dest_aligned> + 426333: 48 89 e8 mov %rbp,%rax + 426336: 48 89 ea mov %rbp,%rdx + 426339: 48 83 e0 f8 and $0xfffffffffffffff8,%rax + 42633d: 83 e2 07 and $0x7,%edx + 426340: 49 01 c5 add %rax,%r13 + 426343: 48 01 c3 add %rax,%rbx + 426346: 49 29 dd sub %rbx,%r13 + 426349: 48 85 d2 test %rdx,%rdx + 42634c: 48 8d 0c 13 lea (%rbx,%rdx,1),%rcx + 426350: 48 89 df mov %rbx,%rdi + 426353: 74 12 je 426367 <__memmove_sse2+0xa7> + 426355: 41 0f b6 44 3d 00 movzbl 0x0(%r13,%rdi,1),%eax + 42635b: 48 83 c7 01 add $0x1,%rdi + 42635f: 88 47 ff mov %al,-0x1(%rdi) + 426362: 48 39 cf cmp %rcx,%rdi + 426365: 75 ee jne 426355 <__memmove_sse2+0x95> + 426367: 48 83 c4 08 add $0x8,%rsp + 42636b: 4c 89 e0 mov %r12,%rax + 42636e: 5b pop %rbx + 42636f: 5d pop %rbp + 426370: 41 5c pop %r12 + 426372: 41 5d pop %r13 + 426374: c3 retq + 426375: 48 01 d6 add %rdx,%rsi + 426378: 48 83 fa 0f cmp $0xf,%rdx + 42637c: 48 8d 2c 17 lea (%rdi,%rdx,1),%rbp + 426380: 76 5f jbe 4263e1 <__memmove_sse2+0x121> + 426382: 48 89 e9 mov %rbp,%rcx + 426385: 48 89 d3 mov %rdx,%rbx + 426388: 49 89 f5 mov %rsi,%r13 + 42638b: 83 e1 07 and $0x7,%ecx + 42638e: 48 29 cb sub %rcx,%rbx + 426391: 48 85 c9 test %rcx,%rcx + 426394: 74 1b je 4263b1 <__memmove_sse2+0xf1> + 426396: 48 89 ea mov %rbp,%rdx + 426399: 49 29 cd sub %rcx,%r13 + 42639c: 48 29 f2 sub %rsi,%rdx + 42639f: 48 83 ee 01 sub $0x1,%rsi + 4263a3: 0f b6 06 movzbl (%rsi),%eax + 4263a6: 4c 39 ee cmp %r13,%rsi + 4263a9: 88 04 32 mov %al,(%rdx,%rsi,1) + 4263ac: 75 f1 jne 42639f <__memmove_sse2+0xdf> + 4263ae: 48 29 cd sub %rcx,%rbp + 4263b1: 48 89 da mov %rbx,%rdx + 4263b4: 4c 89 ee mov %r13,%rsi + 4263b7: 48 89 ef mov %rbp,%rdi + 4263ba: 48 c1 ea 03 shr $0x3,%rdx + 4263be: 41 f6 c5 07 test $0x7,%r13b + 4263c2: 74 50 je 426414 <__memmove_sse2+0x154> + 4263c4: e8 a7 64 00 00 callq 42c870 <_wordcopy_bwd_dest_aligned> + 4263c9: 48 89 d8 mov %rbx,%rax + 4263cc: 4c 89 ee mov %r13,%rsi + 4263cf: 48 83 e0 f8 and $0xfffffffffffffff8,%rax + 4263d3: 48 29 c6 sub %rax,%rsi + 4263d6: 48 29 c5 sub %rax,%rbp + 4263d9: 83 e3 07 and $0x7,%ebx + 4263dc: 48 89 da mov %rbx,%rdx + 4263df: 74 86 je 426367 <__memmove_sse2+0xa7> + 4263e1: 48 89 f0 mov %rsi,%rax + 4263e4: 48 89 ef mov %rbp,%rdi + 4263e7: 48 29 d0 sub %rdx,%rax + 4263ea: 48 29 f7 sub %rsi,%rdi + 4263ed: 48 83 ee 01 sub $0x1,%rsi + 4263f1: 0f b6 16 movzbl (%rsi),%edx + 4263f4: 48 39 c6 cmp %rax,%rsi + 4263f7: 88 14 37 mov %dl,(%rdi,%rsi,1) + 4263fa: 75 f1 jne 4263ed <__memmove_sse2+0x12d> + 4263fc: 48 83 c4 08 add $0x8,%rsp + 426400: 4c 89 e0 mov %r12,%rax + 426403: 5b pop %rbx + 426404: 5d pop %rbp + 426405: 41 5c pop %r12 + 426407: 41 5d pop %r13 + 426409: c3 retq + 42640a: e8 81 60 00 00 callq 42c490 <_wordcopy_fwd_aligned> + 42640f: e9 1f ff ff ff jmpq 426333 <__memmove_sse2+0x73> + 426414: e8 d7 62 00 00 callq 42c6f0 <_wordcopy_bwd_aligned> + 426419: eb ae jmp 4263c9 <__memmove_sse2+0x109> + +000000000042641b <__libc_memmove>: + 42641b: 8b 15 9f 62 2a 00 mov 0x2a629f(%rip),%edx # 6cc6c0 <_dl_x86_cpu_features+0x40> + 426421: 89 d0 mov %edx,%eax + 426423: 25 00 10 02 00 and $0x21000,%eax + 426428: 3d 00 10 02 00 cmp $0x21000,%eax + 42642d: 74 2a je 426459 <__libc_memmove+0x3e> + 42642f: f6 c6 08 test $0x8,%dh + 426432: b8 d0 24 43 00 mov $0x4324d0,%eax + 426437: 75 25 jne 42645e <__libc_memmove+0x43> + 426439: f6 05 51 62 2a 00 02 testb $0x2,0x2a6251(%rip) # 6cc691 <_dl_x86_cpu_features+0x11> + 426440: b8 c0 62 42 00 mov $0x4262c0,%eax + 426445: 74 17 je 42645e <__libc_memmove+0x43> + 426447: 83 e2 02 and $0x2,%edx + 42644a: b8 c0 29 43 00 mov $0x4329c0,%eax + 42644f: ba 50 f9 42 00 mov $0x42f950,%edx + 426454: 48 0f 44 c2 cmove %rdx,%rax + 426458: c3 retq + 426459: b8 e0 54 43 00 mov $0x4354e0,%eax + 42645e: f3 c3 repz retq + +0000000000426460 : + 426460: 48 8d 05 69 00 00 00 lea 0x69(%rip),%rax # 4264d0 <__memset_sse2> + 426467: f7 05 4f 62 2a 00 00 testl $0x400,0x2a624f(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> + 42646e: 04 00 00 + 426471: 74 26 je 426499 + 426473: 48 8d 05 c6 74 01 00 lea 0x174c6(%rip),%rax # 43d940 <__memset_avx2> + 42647a: f7 05 3c 62 2a 00 00 testl $0x1000,0x2a623c(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> + 426481: 10 00 00 + 426484: 74 13 je 426499 + 426486: f7 05 30 62 2a 00 00 testl $0x20000,0x2a6230(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> + 42648d: 00 02 00 + 426490: 74 07 je 426499 + 426492: 48 8d 05 47 76 01 00 lea 0x17647(%rip),%rax # 43dae0 <__memset_avx512_no_vzeroupper> + 426499: c3 retq + 42649a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + +00000000004264a0 <__bzero>: + 4264a0: 48 89 f8 mov %rdi,%rax + 4264a3: 48 89 f2 mov %rsi,%rdx + 4264a6: 66 0f ef c0 pxor %xmm0,%xmm0 + 4264aa: eb 38 jmp 4264e4 <__memset_sse2+0x14> + 4264ac: 0f 1f 40 00 nopl 0x0(%rax) + +00000000004264b0 <__memset_tail>: + 4264b0: 48 89 c8 mov %rcx,%rax + 4264b3: 66 0f 6e c6 movd %esi,%xmm0 + 4264b7: 66 0f 60 c0 punpcklbw %xmm0,%xmm0 + 4264bb: 66 0f 61 c0 punpcklwd %xmm0,%xmm0 + 4264bf: 66 0f 70 c0 00 pshufd $0x0,%xmm0,%xmm0 + 4264c4: eb 1e jmp 4264e4 <__memset_sse2+0x14> + 4264c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4264cd: 00 00 00 + +00000000004264d0 <__memset_sse2>: + 4264d0: 66 0f 6e c6 movd %esi,%xmm0 + 4264d4: 48 89 f8 mov %rdi,%rax + 4264d7: 66 0f 60 c0 punpcklbw %xmm0,%xmm0 + 4264db: 66 0f 61 c0 punpcklwd %xmm0,%xmm0 + 4264df: 66 0f 70 c0 00 pshufd $0x0,%xmm0,%xmm0 + 4264e4: 48 83 fa 40 cmp $0x40,%rdx + 4264e8: 77 36 ja 426520 <__memset_sse2+0x50> + 4264ea: 48 83 fa 10 cmp $0x10,%rdx + 4264ee: 0f 86 8a 00 00 00 jbe 42657e <__memset_sse2+0xae> + 4264f4: 48 83 fa 20 cmp $0x20,%rdx + 4264f8: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 4264fc: f3 0f 7f 44 17 f0 movdqu %xmm0,-0x10(%rdi,%rdx,1) + 426502: 77 0c ja 426510 <__memset_sse2+0x40> + 426504: f3 c3 repz retq + 426506: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42650d: 00 00 00 + 426510: f3 0f 7f 47 10 movdqu %xmm0,0x10(%rdi) + 426515: f3 0f 7f 44 17 e0 movdqu %xmm0,-0x20(%rdi,%rdx,1) + 42651b: c3 retq + 42651c: 0f 1f 40 00 nopl 0x0(%rax) + 426520: 48 8d 4f 40 lea 0x40(%rdi),%rcx + 426524: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 426528: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 42652c: f3 0f 7f 44 17 f0 movdqu %xmm0,-0x10(%rdi,%rdx,1) + 426532: f3 0f 7f 47 10 movdqu %xmm0,0x10(%rdi) + 426537: f3 0f 7f 44 17 e0 movdqu %xmm0,-0x20(%rdi,%rdx,1) + 42653d: f3 0f 7f 47 20 movdqu %xmm0,0x20(%rdi) + 426542: f3 0f 7f 44 17 d0 movdqu %xmm0,-0x30(%rdi,%rdx,1) + 426548: f3 0f 7f 47 30 movdqu %xmm0,0x30(%rdi) + 42654d: f3 0f 7f 44 17 c0 movdqu %xmm0,-0x40(%rdi,%rdx,1) + 426553: 48 01 fa add %rdi,%rdx + 426556: 48 83 e2 c0 and $0xffffffffffffffc0,%rdx + 42655a: 48 39 d1 cmp %rdx,%rcx + 42655d: 74 a5 je 426504 <__memset_sse2+0x34> + 42655f: 90 nop + 426560: 66 0f 7f 01 movdqa %xmm0,(%rcx) + 426564: 66 0f 7f 41 10 movdqa %xmm0,0x10(%rcx) + 426569: 66 0f 7f 41 20 movdqa %xmm0,0x20(%rcx) + 42656e: 66 0f 7f 41 30 movdqa %xmm0,0x30(%rcx) + 426573: 48 83 c1 40 add $0x40,%rcx + 426577: 48 39 ca cmp %rcx,%rdx + 42657a: 75 e4 jne 426560 <__memset_sse2+0x90> + 42657c: f3 c3 repz retq + 42657e: 66 48 0f 7e c1 movq %xmm0,%rcx + 426583: f6 c2 18 test $0x18,%dl + 426586: 75 22 jne 4265aa <__memset_sse2+0xda> + 426588: f6 c2 04 test $0x4,%dl + 42658b: 75 16 jne 4265a3 <__memset_sse2+0xd3> + 42658d: f6 c2 01 test $0x1,%dl + 426590: 74 02 je 426594 <__memset_sse2+0xc4> + 426592: 88 0f mov %cl,(%rdi) + 426594: f6 c2 02 test $0x2,%dl + 426597: 0f 84 67 ff ff ff je 426504 <__memset_sse2+0x34> + 42659d: 66 89 4c 10 fe mov %cx,-0x2(%rax,%rdx,1) + 4265a2: c3 retq + 4265a3: 89 0f mov %ecx,(%rdi) + 4265a5: 89 4c 17 fc mov %ecx,-0x4(%rdi,%rdx,1) + 4265a9: c3 retq + 4265aa: 48 89 0f mov %rcx,(%rdi) + 4265ad: 48 89 4c 17 f8 mov %rcx,-0x8(%rdi,%rdx,1) + 4265b2: c3 retq + 4265b3: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4265ba: 00 00 00 + 4265bd: 0f 1f 00 nopl (%rax) + +00000000004265c0 <__mempcpy>: + 4265c0: 48 83 fa 20 cmp $0x20,%rdx + 4265c4: 73 7a jae 426640 <__mempcpy+0x80> + 4265c6: f6 c2 01 test $0x1,%dl + 4265c9: 74 0b je 4265d6 <__mempcpy+0x16> + 4265cb: 0f b6 0e movzbl (%rsi),%ecx + 4265ce: 88 0f mov %cl,(%rdi) + 4265d0: 48 ff c6 inc %rsi + 4265d3: 48 ff c7 inc %rdi + 4265d6: f6 c2 02 test $0x2,%dl + 4265d9: 74 0e je 4265e9 <__mempcpy+0x29> + 4265db: 0f b7 0e movzwl (%rsi),%ecx + 4265de: 66 89 0f mov %cx,(%rdi) + 4265e1: 48 83 c6 02 add $0x2,%rsi + 4265e5: 48 83 c7 02 add $0x2,%rdi + 4265e9: f6 c2 04 test $0x4,%dl + 4265ec: 74 0c je 4265fa <__mempcpy+0x3a> + 4265ee: 8b 0e mov (%rsi),%ecx + 4265f0: 89 0f mov %ecx,(%rdi) + 4265f2: 48 83 c6 04 add $0x4,%rsi + 4265f6: 48 83 c7 04 add $0x4,%rdi + 4265fa: f6 c2 08 test $0x8,%dl + 4265fd: 74 11 je 426610 <__mempcpy+0x50> + 4265ff: 48 8b 0e mov (%rsi),%rcx + 426602: 48 89 0f mov %rcx,(%rdi) + 426605: 48 83 c6 08 add $0x8,%rsi + 426609: 48 83 c7 08 add $0x8,%rdi + 42660d: 0f 1f 00 nopl (%rax) + 426610: 81 e2 f0 00 00 00 and $0xf0,%edx + 426616: 74 23 je 42663b <__mempcpy+0x7b> + 426618: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 42661f: 00 + 426620: 48 8b 0e mov (%rsi),%rcx + 426623: 4c 8b 46 08 mov 0x8(%rsi),%r8 + 426627: 48 89 0f mov %rcx,(%rdi) + 42662a: 4c 89 47 08 mov %r8,0x8(%rdi) + 42662e: 83 ea 10 sub $0x10,%edx + 426631: 48 8d 76 10 lea 0x10(%rsi),%rsi + 426635: 48 8d 7f 10 lea 0x10(%rdi),%rdi + 426639: 75 e5 jne 426620 <__mempcpy+0x60> + 42663b: 48 89 f8 mov %rdi,%rax + 42663e: c3 retq + 42663f: 90 nop + 426640: 89 f1 mov %esi,%ecx + 426642: 83 e1 07 and $0x7,%ecx + 426645: 74 29 je 426670 <__mempcpy+0xb0> + 426647: 48 8d 54 11 f8 lea -0x8(%rcx,%rdx,1),%rdx + 42664c: 83 e9 08 sub $0x8,%ecx + 42664f: 90 nop + 426650: 0f b6 06 movzbl (%rsi),%eax + 426653: 88 07 mov %al,(%rdi) + 426655: ff c1 inc %ecx + 426657: 48 8d 76 01 lea 0x1(%rsi),%rsi + 42665b: 48 8d 7f 01 lea 0x1(%rdi),%rdi + 42665f: 75 ef jne 426650 <__mempcpy+0x90> + 426661: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 426666: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42666d: 00 00 00 + 426670: 48 81 fa 00 04 00 00 cmp $0x400,%rdx + 426677: 77 77 ja 4266f0 <__mempcpy+0x130> + 426679: 89 d1 mov %edx,%ecx + 42667b: c1 e9 05 shr $0x5,%ecx + 42667e: 74 60 je 4266e0 <__mempcpy+0x120> + 426680: ff c9 dec %ecx + 426682: 48 8b 06 mov (%rsi),%rax + 426685: 4c 8b 46 08 mov 0x8(%rsi),%r8 + 426689: 4c 8b 4e 10 mov 0x10(%rsi),%r9 + 42668d: 4c 8b 56 18 mov 0x18(%rsi),%r10 + 426691: 48 89 07 mov %rax,(%rdi) + 426694: 4c 89 47 08 mov %r8,0x8(%rdi) + 426698: 4c 89 4f 10 mov %r9,0x10(%rdi) + 42669c: 4c 89 57 18 mov %r10,0x18(%rdi) + 4266a0: 48 8d 76 20 lea 0x20(%rsi),%rsi + 4266a4: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 4266a8: 74 36 je 4266e0 <__mempcpy+0x120> + 4266aa: ff c9 dec %ecx + 4266ac: 48 8b 06 mov (%rsi),%rax + 4266af: 4c 8b 46 08 mov 0x8(%rsi),%r8 + 4266b3: 4c 8b 4e 10 mov 0x10(%rsi),%r9 + 4266b7: 4c 8b 56 18 mov 0x18(%rsi),%r10 + 4266bb: 48 89 07 mov %rax,(%rdi) + 4266be: 4c 89 47 08 mov %r8,0x8(%rdi) + 4266c2: 4c 89 4f 10 mov %r9,0x10(%rdi) + 4266c6: 4c 89 57 18 mov %r10,0x18(%rdi) + 4266ca: 48 8d 76 20 lea 0x20(%rsi),%rsi + 4266ce: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 4266d2: 75 ac jne 426680 <__mempcpy+0xc0> + 4266d4: 66 90 xchg %ax,%ax + 4266d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4266dd: 00 00 00 + 4266e0: 83 e2 1f and $0x1f,%edx + 4266e3: 0f 85 dd fe ff ff jne 4265c6 <__mempcpy+0x6> + 4266e9: 48 89 f8 mov %rdi,%rax + 4266ec: c3 retq + 4266ed: 0f 1f 00 nopl (%rax) + 4266f0: 4c 8b 1d d9 49 2a 00 mov 0x2a49d9(%rip),%r11 # 6cb0d0 <__x86_data_cache_size_half> + 4266f7: 49 39 d3 cmp %rdx,%r11 + 4266fa: 4c 0f 47 da cmova %rdx,%r11 + 4266fe: 4c 89 d9 mov %r11,%rcx + 426701: 49 83 e3 f8 and $0xfffffffffffffff8,%r11 + 426705: 48 c1 e9 03 shr $0x3,%rcx + 426709: 74 05 je 426710 <__mempcpy+0x150> + 42670b: f3 48 a5 rep movsq %ds:(%rsi),%es:(%rdi) + 42670e: 66 90 xchg %ax,%ax + 426710: 4c 29 da sub %r11,%rdx + 426713: 48 f7 c2 f8 ff ff ff test $0xfffffffffffffff8,%rdx + 42671a: 75 14 jne 426730 <__mempcpy+0x170> + 42671c: 83 e2 07 and $0x7,%edx + 42671f: 0f 85 a1 fe ff ff jne 4265c6 <__mempcpy+0x6> + 426725: 48 89 f8 mov %rdi,%rax + 426728: c3 retq + 426729: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 426730: 4c 8b 05 79 49 2a 00 mov 0x2a4979(%rip),%r8 # 6cb0b0 <__x86_shared_cache_size_half> + 426737: 49 39 d0 cmp %rdx,%r8 + 42673a: 4c 0f 47 c2 cmova %rdx,%r8 + 42673e: 4c 89 c1 mov %r8,%rcx + 426741: 49 83 e0 c0 and $0xffffffffffffffc0,%r8 + 426745: 48 c1 e9 06 shr $0x6,%rcx + 426749: 0f 84 ab 01 00 00 je 4268fa <__mempcpy+0x33a> + 42674f: 4c 89 74 24 f8 mov %r14,-0x8(%rsp) + 426754: 4c 89 6c 24 f0 mov %r13,-0x10(%rsp) + 426759: 4c 89 64 24 e8 mov %r12,-0x18(%rsp) + 42675e: 48 89 5c 24 e0 mov %rbx,-0x20(%rsp) + 426763: 83 3d 4e 6a 2a 00 00 cmpl $0x0,0x2a6a4e(%rip) # 6cd1b8 <__x86_prefetchw> + 42676a: 0f 84 c0 00 00 00 je 426830 <__mempcpy+0x270> + 426770: 48 ff c9 dec %rcx + 426773: 48 8b 06 mov (%rsi),%rax + 426776: 48 8b 5e 08 mov 0x8(%rsi),%rbx + 42677a: 4c 8b 4e 10 mov 0x10(%rsi),%r9 + 42677e: 4c 8b 56 18 mov 0x18(%rsi),%r10 + 426782: 4c 8b 5e 20 mov 0x20(%rsi),%r11 + 426786: 4c 8b 66 28 mov 0x28(%rsi),%r12 + 42678a: 4c 8b 6e 30 mov 0x30(%rsi),%r13 + 42678e: 4c 8b 76 38 mov 0x38(%rsi),%r14 + 426792: 0f 18 8e 80 03 00 00 prefetcht0 0x380(%rsi) + 426799: 0f 18 8e c0 03 00 00 prefetcht0 0x3c0(%rsi) + 4267a0: 48 89 07 mov %rax,(%rdi) + 4267a3: 48 89 5f 08 mov %rbx,0x8(%rdi) + 4267a7: 4c 89 4f 10 mov %r9,0x10(%rdi) + 4267ab: 4c 89 57 18 mov %r10,0x18(%rdi) + 4267af: 4c 89 5f 20 mov %r11,0x20(%rdi) + 4267b3: 4c 89 67 28 mov %r12,0x28(%rdi) + 4267b7: 4c 89 6f 30 mov %r13,0x30(%rdi) + 4267bb: 4c 89 77 38 mov %r14,0x38(%rdi) + 4267bf: 48 8d 76 40 lea 0x40(%rsi),%rsi + 4267c3: 48 8d 7f 40 lea 0x40(%rdi),%rdi + 4267c7: 0f 84 19 01 00 00 je 4268e6 <__mempcpy+0x326> + 4267cd: 48 ff c9 dec %rcx + 4267d0: 48 8b 06 mov (%rsi),%rax + 4267d3: 48 8b 5e 08 mov 0x8(%rsi),%rbx + 4267d7: 4c 8b 4e 10 mov 0x10(%rsi),%r9 + 4267db: 4c 8b 56 18 mov 0x18(%rsi),%r10 + 4267df: 4c 8b 5e 20 mov 0x20(%rsi),%r11 + 4267e3: 4c 8b 66 28 mov 0x28(%rsi),%r12 + 4267e7: 4c 8b 6e 30 mov 0x30(%rsi),%r13 + 4267eb: 4c 8b 76 38 mov 0x38(%rsi),%r14 + 4267ef: 48 89 07 mov %rax,(%rdi) + 4267f2: 48 89 5f 08 mov %rbx,0x8(%rdi) + 4267f6: 4c 89 4f 10 mov %r9,0x10(%rdi) + 4267fa: 4c 89 57 18 mov %r10,0x18(%rdi) + 4267fe: 4c 89 5f 20 mov %r11,0x20(%rdi) + 426802: 4c 89 67 28 mov %r12,0x28(%rdi) + 426806: 4c 89 6f 30 mov %r13,0x30(%rdi) + 42680a: 4c 89 77 38 mov %r14,0x38(%rdi) + 42680e: 0f 0d 8f 40 03 00 00 prefetchw 0x340(%rdi) + 426815: 0f 0d 8f 80 03 00 00 prefetchw 0x380(%rdi) + 42681c: 48 8d 76 40 lea 0x40(%rsi),%rsi + 426820: 48 8d 7f 40 lea 0x40(%rdi),%rdi + 426824: 0f 85 46 ff ff ff jne 426770 <__mempcpy+0x1b0> + 42682a: e9 b7 00 00 00 jmpq 4268e6 <__mempcpy+0x326> + 42682f: 90 nop + 426830: 48 ff c9 dec %rcx + 426833: 48 8b 06 mov (%rsi),%rax + 426836: 48 8b 5e 08 mov 0x8(%rsi),%rbx + 42683a: 4c 8b 4e 10 mov 0x10(%rsi),%r9 + 42683e: 4c 8b 56 18 mov 0x18(%rsi),%r10 + 426842: 4c 8b 5e 20 mov 0x20(%rsi),%r11 + 426846: 4c 8b 66 28 mov 0x28(%rsi),%r12 + 42684a: 4c 8b 6e 30 mov 0x30(%rsi),%r13 + 42684e: 4c 8b 76 38 mov 0x38(%rsi),%r14 + 426852: 0f 18 8e 80 03 00 00 prefetcht0 0x380(%rsi) + 426859: 0f 18 8e c0 03 00 00 prefetcht0 0x3c0(%rsi) + 426860: 48 89 07 mov %rax,(%rdi) + 426863: 48 89 5f 08 mov %rbx,0x8(%rdi) + 426867: 4c 89 4f 10 mov %r9,0x10(%rdi) + 42686b: 4c 89 57 18 mov %r10,0x18(%rdi) + 42686f: 4c 89 5f 20 mov %r11,0x20(%rdi) + 426873: 4c 89 67 28 mov %r12,0x28(%rdi) + 426877: 4c 89 6f 30 mov %r13,0x30(%rdi) + 42687b: 4c 89 77 38 mov %r14,0x38(%rdi) + 42687f: 48 8d 76 40 lea 0x40(%rsi),%rsi + 426883: 48 8d 7f 40 lea 0x40(%rdi),%rdi + 426887: 74 5d je 4268e6 <__mempcpy+0x326> + 426889: 48 ff c9 dec %rcx + 42688c: 48 8b 06 mov (%rsi),%rax + 42688f: 48 8b 5e 08 mov 0x8(%rsi),%rbx + 426893: 4c 8b 4e 10 mov 0x10(%rsi),%r9 + 426897: 4c 8b 56 18 mov 0x18(%rsi),%r10 + 42689b: 4c 8b 5e 20 mov 0x20(%rsi),%r11 + 42689f: 4c 8b 66 28 mov 0x28(%rsi),%r12 + 4268a3: 4c 8b 6e 30 mov 0x30(%rsi),%r13 + 4268a7: 4c 8b 76 38 mov 0x38(%rsi),%r14 + 4268ab: 0f 18 8f 40 03 00 00 prefetcht0 0x340(%rdi) + 4268b2: 0f 18 8f 80 03 00 00 prefetcht0 0x380(%rdi) + 4268b9: 48 89 07 mov %rax,(%rdi) + 4268bc: 48 89 5f 08 mov %rbx,0x8(%rdi) + 4268c0: 4c 89 4f 10 mov %r9,0x10(%rdi) + 4268c4: 4c 89 57 18 mov %r10,0x18(%rdi) + 4268c8: 4c 89 5f 20 mov %r11,0x20(%rdi) + 4268cc: 4c 89 67 28 mov %r12,0x28(%rdi) + 4268d0: 4c 89 6f 30 mov %r13,0x30(%rdi) + 4268d4: 4c 89 77 38 mov %r14,0x38(%rdi) + 4268d8: 48 8d 76 40 lea 0x40(%rsi),%rsi + 4268dc: 48 8d 7f 40 lea 0x40(%rdi),%rdi + 4268e0: 0f 85 4a ff ff ff jne 426830 <__mempcpy+0x270> + 4268e6: 48 8b 5c 24 e0 mov -0x20(%rsp),%rbx + 4268eb: 4c 8b 64 24 e8 mov -0x18(%rsp),%r12 + 4268f0: 4c 8b 6c 24 f0 mov -0x10(%rsp),%r13 + 4268f5: 4c 8b 74 24 f8 mov -0x8(%rsp),%r14 + 4268fa: 4c 29 c2 sub %r8,%rdx + 4268fd: 48 f7 c2 c0 ff ff ff test $0xffffffffffffffc0,%rdx + 426904: 75 1a jne 426920 <__mempcpy+0x360> + 426906: 83 e2 3f and $0x3f,%edx + 426909: 0f 85 b7 fc ff ff jne 4265c6 <__mempcpy+0x6> + 42690f: 48 89 f8 mov %rdi,%rax + 426912: c3 retq + 426913: 0f 1f 00 nopl (%rax) + 426916: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42691d: 00 00 00 + 426920: 48 89 d1 mov %rdx,%rcx + 426923: 48 c1 e9 07 shr $0x7,%rcx + 426927: 0f 84 d8 00 00 00 je 426a05 <__mempcpy+0x445> + 42692d: 4c 89 74 24 f8 mov %r14,-0x8(%rsp) + 426932: 4c 89 6c 24 f0 mov %r13,-0x10(%rsp) + 426937: 4c 89 64 24 e8 mov %r12,-0x18(%rsp) + 42693c: 0f 1f 40 00 nopl 0x0(%rax) + 426940: 0f 18 86 00 03 00 00 prefetchnta 0x300(%rsi) + 426947: 0f 18 86 40 03 00 00 prefetchnta 0x340(%rsi) + 42694e: 48 ff c9 dec %rcx + 426951: 48 8b 06 mov (%rsi),%rax + 426954: 4c 8b 46 08 mov 0x8(%rsi),%r8 + 426958: 4c 8b 4e 10 mov 0x10(%rsi),%r9 + 42695c: 4c 8b 56 18 mov 0x18(%rsi),%r10 + 426960: 4c 8b 5e 20 mov 0x20(%rsi),%r11 + 426964: 4c 8b 66 28 mov 0x28(%rsi),%r12 + 426968: 4c 8b 6e 30 mov 0x30(%rsi),%r13 + 42696c: 4c 8b 76 38 mov 0x38(%rsi),%r14 + 426970: 48 0f c3 07 movnti %rax,(%rdi) + 426974: 4c 0f c3 47 08 movnti %r8,0x8(%rdi) + 426979: 4c 0f c3 4f 10 movnti %r9,0x10(%rdi) + 42697e: 4c 0f c3 57 18 movnti %r10,0x18(%rdi) + 426983: 4c 0f c3 5f 20 movnti %r11,0x20(%rdi) + 426988: 4c 0f c3 67 28 movnti %r12,0x28(%rdi) + 42698d: 4c 0f c3 6f 30 movnti %r13,0x30(%rdi) + 426992: 4c 0f c3 77 38 movnti %r14,0x38(%rdi) + 426997: 48 8b 46 40 mov 0x40(%rsi),%rax + 42699b: 4c 8b 46 48 mov 0x48(%rsi),%r8 + 42699f: 4c 8b 4e 50 mov 0x50(%rsi),%r9 + 4269a3: 4c 8b 56 58 mov 0x58(%rsi),%r10 + 4269a7: 4c 8b 5e 60 mov 0x60(%rsi),%r11 + 4269ab: 4c 8b 66 68 mov 0x68(%rsi),%r12 + 4269af: 4c 8b 6e 70 mov 0x70(%rsi),%r13 + 4269b3: 4c 8b 76 78 mov 0x78(%rsi),%r14 + 4269b7: 48 0f c3 47 40 movnti %rax,0x40(%rdi) + 4269bc: 4c 0f c3 47 48 movnti %r8,0x48(%rdi) + 4269c1: 4c 0f c3 4f 50 movnti %r9,0x50(%rdi) + 4269c6: 4c 0f c3 57 58 movnti %r10,0x58(%rdi) + 4269cb: 4c 0f c3 5f 60 movnti %r11,0x60(%rdi) + 4269d0: 4c 0f c3 67 68 movnti %r12,0x68(%rdi) + 4269d5: 4c 0f c3 6f 70 movnti %r13,0x70(%rdi) + 4269da: 4c 0f c3 77 78 movnti %r14,0x78(%rdi) + 4269df: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi + 4269e6: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi + 4269ed: 0f 85 4d ff ff ff jne 426940 <__mempcpy+0x380> + 4269f3: 0f ae f8 sfence + 4269f6: 4c 8b 64 24 e8 mov -0x18(%rsp),%r12 + 4269fb: 4c 8b 6c 24 f0 mov -0x10(%rsp),%r13 + 426a00: 4c 8b 74 24 f8 mov -0x8(%rsp),%r14 + 426a05: 83 e2 7f and $0x7f,%edx + 426a08: 0f 85 b8 fb ff ff jne 4265c6 <__mempcpy+0x6> + 426a0e: 48 89 f8 mov %rdi,%rax + 426a11: c3 retq + 426a12: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 426a19: 00 00 00 + 426a1c: 0f 1f 40 00 nopl 0x0(%rax) + +0000000000426a20 <__stpcpy>: + 426a20: 48 8d 05 39 49 01 00 lea 0x14939(%rip),%rax # 43b360 <__stpcpy_sse2_unaligned> + 426a27: f7 05 8f 5c 2a 00 10 testl $0x10,0x2a5c8f(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> + 426a2e: 00 00 00 + 426a31: 75 1a jne 426a4d <__stpcpy+0x2d> + 426a33: 48 8d 05 16 00 00 00 lea 0x16(%rip),%rax # 426a50 <__GI___stpcpy> + 426a3a: f7 05 4c 5c 2a 00 00 testl $0x200,0x2a5c4c(%rip) # 6cc690 <_dl_x86_cpu_features+0x10> + 426a41: 02 00 00 + 426a44: 74 07 je 426a4d <__stpcpy+0x2d> + 426a46: 48 8d 05 d3 2a 01 00 lea 0x12ad3(%rip),%rax # 439520 <__stpcpy_ssse3> + 426a4d: c3 retq + 426a4e: 66 90 xchg %ax,%ax + +0000000000426a50 <__GI___stpcpy>: + 426a50: 48 89 f1 mov %rsi,%rcx + 426a53: 83 e1 07 and $0x7,%ecx + 426a56: 48 89 fa mov %rdi,%rdx + 426a59: 74 1b je 426a76 <__GI___stpcpy+0x26> + 426a5b: f7 d9 neg %ecx + 426a5d: 83 c1 08 add $0x8,%ecx + 426a60: 8a 06 mov (%rsi),%al + 426a62: 84 c0 test %al,%al + 426a64: 88 02 mov %al,(%rdx) + 426a66: 0f 84 bc 00 00 00 je 426b28 <__GI___stpcpy+0xd8> + 426a6c: 48 ff c6 inc %rsi + 426a6f: 48 ff c2 inc %rdx + 426a72: ff c9 dec %ecx + 426a74: 75 ea jne 426a60 <__GI___stpcpy+0x10> + 426a76: 49 b8 ff fe fe fe fe movabs $0xfefefefefefefeff,%r8 + 426a7d: fe fe fe + 426a80: 48 8b 06 mov (%rsi),%rax + 426a83: 48 83 c6 08 add $0x8,%rsi + 426a87: 49 89 c1 mov %rax,%r9 + 426a8a: 4d 01 c1 add %r8,%r9 + 426a8d: 0f 83 7d 00 00 00 jae 426b10 <__GI___stpcpy+0xc0> + 426a93: 49 31 c1 xor %rax,%r9 + 426a96: 4d 09 c1 or %r8,%r9 + 426a99: 49 ff c1 inc %r9 + 426a9c: 75 72 jne 426b10 <__GI___stpcpy+0xc0> + 426a9e: 48 89 02 mov %rax,(%rdx) + 426aa1: 48 83 c2 08 add $0x8,%rdx + 426aa5: 48 8b 06 mov (%rsi),%rax + 426aa8: 48 83 c6 08 add $0x8,%rsi + 426aac: 49 89 c1 mov %rax,%r9 + 426aaf: 4d 01 c1 add %r8,%r9 + 426ab2: 73 5c jae 426b10 <__GI___stpcpy+0xc0> + 426ab4: 49 31 c1 xor %rax,%r9 + 426ab7: 4d 09 c1 or %r8,%r9 + 426aba: 49 ff c1 inc %r9 + 426abd: 75 51 jne 426b10 <__GI___stpcpy+0xc0> + 426abf: 48 89 02 mov %rax,(%rdx) + 426ac2: 48 83 c2 08 add $0x8,%rdx + 426ac6: 48 8b 06 mov (%rsi),%rax + 426ac9: 48 83 c6 08 add $0x8,%rsi + 426acd: 49 89 c1 mov %rax,%r9 + 426ad0: 4d 01 c1 add %r8,%r9 + 426ad3: 73 3b jae 426b10 <__GI___stpcpy+0xc0> + 426ad5: 49 31 c1 xor %rax,%r9 + 426ad8: 4d 09 c1 or %r8,%r9 + 426adb: 49 ff c1 inc %r9 + 426ade: 75 30 jne 426b10 <__GI___stpcpy+0xc0> + 426ae0: 48 89 02 mov %rax,(%rdx) + 426ae3: 48 83 c2 08 add $0x8,%rdx + 426ae7: 48 8b 06 mov (%rsi),%rax + 426aea: 48 83 c6 08 add $0x8,%rsi + 426aee: 49 89 c1 mov %rax,%r9 + 426af1: 4d 01 c1 add %r8,%r9 + 426af4: 73 1a jae 426b10 <__GI___stpcpy+0xc0> + 426af6: 49 31 c1 xor %rax,%r9 + 426af9: 4d 09 c1 or %r8,%r9 + 426afc: 49 ff c1 inc %r9 + 426aff: 75 0f jne 426b10 <__GI___stpcpy+0xc0> + 426b01: 48 89 02 mov %rax,(%rdx) + 426b04: 48 83 c2 08 add $0x8,%rdx + 426b08: e9 73 ff ff ff jmpq 426a80 <__GI___stpcpy+0x30> + 426b0d: 0f 1f 00 nopl (%rax) + 426b10: 88 02 mov %al,(%rdx) + 426b12: 84 c0 test %al,%al + 426b14: 74 12 je 426b28 <__GI___stpcpy+0xd8> + 426b16: 48 ff c2 inc %rdx + 426b19: 88 22 mov %ah,(%rdx) + 426b1b: 84 e4 test %ah,%ah + 426b1d: 74 09 je 426b28 <__GI___stpcpy+0xd8> + 426b1f: 48 ff c2 inc %rdx + 426b22: 48 c1 e8 10 shr $0x10,%rax + 426b26: eb e8 jmp 426b10 <__GI___stpcpy+0xc0> + 426b28: 48 89 d0 mov %rdx,%rax + 426b2b: c3 retq + 426b2c: 0f 1f 40 00 nopl 0x0(%rax) + +0000000000426b30 <__strcasecmp_l>: + 426b30: f7 05 86 5b 2a 00 00 testl $0x200,0x2a5b86(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> + 426b37: 02 00 00 + 426b3a: 75 13 jne 426b4f <__strcasecmp_l+0x1f> + 426b3c: 48 8d 05 cd 22 00 00 lea 0x22cd(%rip),%rax # 428e10 <__strcasecmp_l_sse42> + 426b43: f7 05 43 5b 2a 00 00 testl $0x100000,0x2a5b43(%rip) # 6cc690 <_dl_x86_cpu_features+0x10> + 426b4a: 00 10 00 + 426b4d: 75 1a jne 426b69 <__strcasecmp_l+0x39> + 426b4f: 48 8d 05 da f0 00 00 lea 0xf0da(%rip),%rax # 435c30 <__strcasecmp_l_ssse3> + 426b56: f7 05 30 5b 2a 00 00 testl $0x200,0x2a5b30(%rip) # 6cc690 <_dl_x86_cpu_features+0x10> + 426b5d: 02 00 00 + 426b60: 75 07 jne 426b69 <__strcasecmp_l+0x39> + 426b62: 48 8d 05 67 00 00 00 lea 0x67(%rip),%rax # 426bd0 <__GI___strcasecmp_l> + 426b69: c3 retq + 426b6a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + +0000000000426b70 <__strcasecmp>: + 426b70: 48 8d 05 39 3e 00 00 lea 0x3e39(%rip),%rax # 42a9b0 <__strcasecmp_avx> + 426b77: f7 05 3f 5b 2a 00 40 testl $0x40,0x2a5b3f(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> + 426b7e: 00 00 00 + 426b81: 75 39 jne 426bbc <__strcasecmp+0x4c> + 426b83: f7 05 33 5b 2a 00 00 testl $0x200,0x2a5b33(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> + 426b8a: 02 00 00 + 426b8d: 75 13 jne 426ba2 <__strcasecmp+0x32> + 426b8f: 48 8d 05 6a 22 00 00 lea 0x226a(%rip),%rax # 428e00 <__strcasecmp_sse42> + 426b96: f7 05 f0 5a 2a 00 00 testl $0x100000,0x2a5af0(%rip) # 6cc690 <_dl_x86_cpu_features+0x10> + 426b9d: 00 10 00 + 426ba0: 75 1a jne 426bbc <__strcasecmp+0x4c> + 426ba2: 48 8d 05 77 f0 00 00 lea 0xf077(%rip),%rax # 435c20 <__strcasecmp_ssse3> + 426ba9: f7 05 dd 5a 2a 00 00 testl $0x200,0x2a5add(%rip) # 6cc690 <_dl_x86_cpu_features+0x10> + 426bb0: 02 00 00 + 426bb3: 75 07 jne 426bbc <__strcasecmp+0x4c> + 426bb5: 48 8d 05 04 00 00 00 lea 0x4(%rip),%rax # 426bc0 <__strcasecmp_sse2> + 426bbc: c3 retq + 426bbd: 0f 1f 00 nopl (%rax) + +0000000000426bc0 <__strcasecmp_sse2>: + 426bc0: 48 c7 c0 b8 ff ff ff mov $0xffffffffffffffb8,%rax + 426bc7: 64 48 8b 10 mov %fs:(%rax),%rdx + 426bcb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + +0000000000426bd0 <__GI___strcasecmp_l>: + 426bd0: 48 8b 02 mov (%rdx),%rax + 426bd3: f7 80 78 02 00 00 01 testl $0x1,0x278(%rax) + 426bda: 00 00 00 + 426bdd: 0f 85 1d 77 01 00 jne 43e300 <__strcasecmp_l_nonascii> + 426be3: 89 f1 mov %esi,%ecx + 426be5: 89 f8 mov %edi,%eax + 426be7: 48 83 e1 3f and $0x3f,%rcx + 426beb: 48 83 e0 3f and $0x3f,%rax + 426bef: 66 0f 6f 2d b9 c4 07 movdqa 0x7c4b9(%rip),%xmm5 # 4a30b0 <__func__.10972+0xf0> + 426bf6: 00 + 426bf7: 66 0f 6f 35 c1 c4 07 movdqa 0x7c4c1(%rip),%xmm6 # 4a30c0 <__func__.10972+0x100> + 426bfe: 00 + 426bff: 66 0f 6f 3d c9 c4 07 movdqa 0x7c4c9(%rip),%xmm7 # 4a30d0 + 426c06: 00 + 426c07: 83 f9 30 cmp $0x30,%ecx + 426c0a: 0f 87 90 00 00 00 ja 426ca0 <__GI___strcasecmp_l+0xd0> + 426c10: 83 f8 30 cmp $0x30,%eax + 426c13: 0f 87 87 00 00 00 ja 426ca0 <__GI___strcasecmp_l+0xd0> + 426c19: 66 0f 12 0f movlpd (%rdi),%xmm1 + 426c1d: 66 0f 12 16 movlpd (%rsi),%xmm2 + 426c21: 66 0f 16 4f 08 movhpd 0x8(%rdi),%xmm1 + 426c26: 66 0f 16 56 08 movhpd 0x8(%rsi),%xmm2 + 426c2b: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 426c30: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 426c35: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 426c3a: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 426c3f: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 426c44: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 426c49: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 426c4e: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 426c53: 66 45 0f db c1 pand %xmm9,%xmm8 + 426c58: 66 45 0f db d3 pand %xmm11,%xmm10 + 426c5d: 66 44 0f db c7 pand %xmm7,%xmm8 + 426c62: 66 44 0f db d7 pand %xmm7,%xmm10 + 426c67: 66 41 0f eb c8 por %xmm8,%xmm1 + 426c6c: 66 41 0f eb d2 por %xmm10,%xmm2 + 426c71: 66 0f ef c0 pxor %xmm0,%xmm0 + 426c75: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 426c79: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 426c7d: 66 0f f8 c8 psubb %xmm0,%xmm1 + 426c81: 66 0f d7 d1 pmovmskb %xmm1,%edx + 426c85: 81 ea ff ff 00 00 sub $0xffff,%edx + 426c8b: 0f 85 2f 21 00 00 jne 428dc0 <__GI___strcasecmp_l+0x21f0> + 426c91: 48 83 c6 10 add $0x10,%rsi + 426c95: 48 83 c7 10 add $0x10,%rdi + 426c99: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 426ca0: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi + 426ca4: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi + 426ca8: ba ff ff 00 00 mov $0xffff,%edx + 426cad: 45 31 c0 xor %r8d,%r8d + 426cb0: 83 e1 0f and $0xf,%ecx + 426cb3: 83 e0 0f and $0xf,%eax + 426cb6: 39 c1 cmp %eax,%ecx + 426cb8: 74 26 je 426ce0 <__GI___strcasecmp_l+0x110> + 426cba: 77 07 ja 426cc3 <__GI___strcasecmp_l+0xf3> + 426cbc: 41 89 d0 mov %edx,%r8d + 426cbf: 91 xchg %eax,%ecx + 426cc0: 48 87 f7 xchg %rsi,%rdi + 426cc3: 4c 8d 48 0f lea 0xf(%rax),%r9 + 426cc7: 49 29 c9 sub %rcx,%r9 + 426cca: 4c 8d 15 9f c4 07 00 lea 0x7c49f(%rip),%r10 # 4a3170 + 426cd1: 4f 63 0c 8a movslq (%r10,%r9,4),%r9 + 426cd5: 4f 8d 14 0a lea (%r10,%r9,1),%r10 + 426cd9: 41 ff e2 jmpq *%r10 + 426cdc: 0f 1f 40 00 nopl 0x0(%rax) + 426ce0: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 426ce4: 66 0f ef c0 pxor %xmm0,%xmm0 + 426ce8: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 426cec: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 426cf0: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 426cf5: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 426cfa: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 426cff: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 426d04: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 426d09: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 426d0e: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 426d13: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 426d18: 66 45 0f db c1 pand %xmm9,%xmm8 + 426d1d: 66 45 0f db d3 pand %xmm11,%xmm10 + 426d22: 66 44 0f db c7 pand %xmm7,%xmm8 + 426d27: 66 44 0f db d7 pand %xmm7,%xmm10 + 426d2c: 66 41 0f eb c8 por %xmm8,%xmm1 + 426d31: 66 41 0f eb d2 por %xmm10,%xmm2 + 426d36: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 426d3a: 66 0f f8 c8 psubb %xmm0,%xmm1 + 426d3e: 66 44 0f d7 c9 pmovmskb %xmm1,%r9d + 426d43: d3 ea shr %cl,%edx + 426d45: 41 d3 e9 shr %cl,%r9d + 426d48: 44 29 ca sub %r9d,%edx + 426d4b: 0f 85 54 20 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> + 426d51: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 426d58: 49 c7 c1 10 00 00 00 mov $0x10,%r9 + 426d5f: 66 0f ef c0 pxor %xmm0,%xmm0 + 426d63: 0f 1f 00 nopl (%rax) + 426d66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 426d6d: 00 00 00 + 426d70: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 426d75: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 426d7a: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 426d7f: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 426d84: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 426d89: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 426d8e: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 426d93: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 426d98: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 426d9d: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 426da2: 66 45 0f db c1 pand %xmm9,%xmm8 + 426da7: 66 45 0f db d3 pand %xmm11,%xmm10 + 426dac: 66 44 0f db c7 pand %xmm7,%xmm8 + 426db1: 66 44 0f db d7 pand %xmm7,%xmm10 + 426db6: 66 41 0f eb c8 por %xmm8,%xmm1 + 426dbb: 66 41 0f eb d2 por %xmm10,%xmm2 + 426dc0: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 426dc4: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 426dc8: 66 0f f8 c8 psubb %xmm0,%xmm1 + 426dcc: 66 0f d7 d1 pmovmskb %xmm1,%edx + 426dd0: 81 ea ff ff 00 00 sub $0xffff,%edx + 426dd6: 0f 85 c4 1f 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 426ddc: 48 83 c1 10 add $0x10,%rcx + 426de0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 426de5: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 426dea: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 426def: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 426df4: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 426df9: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 426dfe: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 426e03: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 426e08: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 426e0d: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 426e12: 66 45 0f db c1 pand %xmm9,%xmm8 + 426e17: 66 45 0f db d3 pand %xmm11,%xmm10 + 426e1c: 66 44 0f db c7 pand %xmm7,%xmm8 + 426e21: 66 44 0f db d7 pand %xmm7,%xmm10 + 426e26: 66 41 0f eb c8 por %xmm8,%xmm1 + 426e2b: 66 41 0f eb d2 por %xmm10,%xmm2 + 426e30: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 426e34: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 426e38: 66 0f f8 c8 psubb %xmm0,%xmm1 + 426e3c: 66 0f d7 d1 pmovmskb %xmm1,%edx + 426e40: 81 ea ff ff 00 00 sub $0xffff,%edx + 426e46: 0f 85 54 1f 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 426e4c: 48 83 c1 10 add $0x10,%rcx + 426e50: e9 1b ff ff ff jmpq 426d70 <__GI___strcasecmp_l+0x1a0> + 426e55: 90 nop + 426e56: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 426e5d: 00 00 00 + 426e60: 66 0f ef c0 pxor %xmm0,%xmm0 + 426e64: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 426e68: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 426e6c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 426e70: 66 0f 73 fa 0f pslldq $0xf,%xmm2 + 426e75: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 426e7a: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 426e7f: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 426e84: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 426e89: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 426e8e: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 426e93: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 426e98: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 426e9d: 66 45 0f db c1 pand %xmm9,%xmm8 + 426ea2: 66 45 0f db d3 pand %xmm11,%xmm10 + 426ea7: 66 44 0f db c7 pand %xmm7,%xmm8 + 426eac: 66 44 0f db d7 pand %xmm7,%xmm10 + 426eb1: 66 41 0f eb c8 por %xmm8,%xmm1 + 426eb6: 66 41 0f eb d2 por %xmm10,%xmm2 + 426ebb: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 426ebf: 66 0f f8 d0 psubb %xmm0,%xmm2 + 426ec3: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 426ec8: d3 ea shr %cl,%edx + 426eca: 41 d3 e9 shr %cl,%r9d + 426ecd: 44 29 ca sub %r9d,%edx + 426ed0: 0f 85 cf 1e 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> + 426ed6: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 426eda: 66 0f ef c0 pxor %xmm0,%xmm0 + 426ede: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 426ee5: 41 b9 01 00 00 00 mov $0x1,%r9d + 426eeb: 4c 8d 57 01 lea 0x1(%rdi),%r10 + 426eef: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 426ef6: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 426efd: 0f 1f 00 nopl (%rax) + 426f00: 49 83 c2 10 add $0x10,%r10 + 426f04: 0f 8f 26 01 00 00 jg 427030 <__GI___strcasecmp_l+0x460> + 426f0a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 426f0f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 426f14: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 426f18: 66 0f 73 db 01 psrldq $0x1,%xmm3 + 426f1d: 66 0f 73 fa 0f pslldq $0xf,%xmm2 + 426f22: 66 0f eb d3 por %xmm3,%xmm2 + 426f26: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 426f2b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 426f30: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 426f35: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 426f3a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 426f3f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 426f44: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 426f49: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 426f4e: 66 45 0f db c1 pand %xmm9,%xmm8 + 426f53: 66 45 0f db d3 pand %xmm11,%xmm10 + 426f58: 66 44 0f db c7 pand %xmm7,%xmm8 + 426f5d: 66 44 0f db d7 pand %xmm7,%xmm10 + 426f62: 66 41 0f eb c8 por %xmm8,%xmm1 + 426f67: 66 41 0f eb d2 por %xmm10,%xmm2 + 426f6c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 426f70: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 426f74: 66 0f f8 c8 psubb %xmm0,%xmm1 + 426f78: 66 0f d7 d1 pmovmskb %xmm1,%edx + 426f7c: 81 ea ff ff 00 00 sub $0xffff,%edx + 426f82: 0f 85 18 1e 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 426f88: 48 83 c1 10 add $0x10,%rcx + 426f8c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 426f90: 49 83 c2 10 add $0x10,%r10 + 426f94: 0f 8f 96 00 00 00 jg 427030 <__GI___strcasecmp_l+0x460> + 426f9a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 426f9f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 426fa4: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 426fa8: 66 0f 73 db 01 psrldq $0x1,%xmm3 + 426fad: 66 0f 73 fa 0f pslldq $0xf,%xmm2 + 426fb2: 66 0f eb d3 por %xmm3,%xmm2 + 426fb6: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 426fbb: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 426fc0: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 426fc5: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 426fca: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 426fcf: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 426fd4: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 426fd9: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 426fde: 66 45 0f db c1 pand %xmm9,%xmm8 + 426fe3: 66 45 0f db d3 pand %xmm11,%xmm10 + 426fe8: 66 44 0f db c7 pand %xmm7,%xmm8 + 426fed: 66 44 0f db d7 pand %xmm7,%xmm10 + 426ff2: 66 41 0f eb c8 por %xmm8,%xmm1 + 426ff7: 66 41 0f eb d2 por %xmm10,%xmm2 + 426ffc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 427000: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 427004: 66 0f f8 c8 psubb %xmm0,%xmm1 + 427008: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42700c: 81 ea ff ff 00 00 sub $0xffff,%edx + 427012: 0f 85 88 1d 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 427018: 48 83 c1 10 add $0x10,%rcx + 42701c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 427020: e9 db fe ff ff jmpq 426f00 <__GI___strcasecmp_l+0x330> + 427025: 90 nop + 427026: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42702d: 00 00 00 + 427030: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 427034: 66 0f d7 d0 pmovmskb %xmm0,%edx + 427038: f7 c2 fe ff 00 00 test $0xfffe,%edx + 42703e: 75 10 jne 427050 <__GI___strcasecmp_l+0x480> + 427040: 66 0f ef c0 pxor %xmm0,%xmm0 + 427044: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42704b: e9 ba fe ff ff jmpq 426f0a <__GI___strcasecmp_l+0x33a> + 427050: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 427055: 66 0f 73 d8 01 psrldq $0x1,%xmm0 + 42705a: 66 0f 73 db 01 psrldq $0x1,%xmm3 + 42705f: e9 dc 1c 00 00 jmpq 428d40 <__GI___strcasecmp_l+0x2170> + 427064: 66 90 xchg %ax,%ax + 427066: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42706d: 00 00 00 + 427070: 66 0f ef c0 pxor %xmm0,%xmm0 + 427074: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 427078: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42707c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 427080: 66 0f 73 fa 0e pslldq $0xe,%xmm2 + 427085: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 42708a: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 42708f: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 427094: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 427099: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 42709e: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 4270a3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 4270a8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 4270ad: 66 45 0f db c1 pand %xmm9,%xmm8 + 4270b2: 66 45 0f db d3 pand %xmm11,%xmm10 + 4270b7: 66 44 0f db c7 pand %xmm7,%xmm8 + 4270bc: 66 44 0f db d7 pand %xmm7,%xmm10 + 4270c1: 66 41 0f eb c8 por %xmm8,%xmm1 + 4270c6: 66 41 0f eb d2 por %xmm10,%xmm2 + 4270cb: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 4270cf: 66 0f f8 d0 psubb %xmm0,%xmm2 + 4270d3: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 4270d8: d3 ea shr %cl,%edx + 4270da: 41 d3 e9 shr %cl,%r9d + 4270dd: 44 29 ca sub %r9d,%edx + 4270e0: 0f 85 bf 1c 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> + 4270e6: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 4270ea: 66 0f ef c0 pxor %xmm0,%xmm0 + 4270ee: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 4270f5: 41 b9 02 00 00 00 mov $0x2,%r9d + 4270fb: 4c 8d 57 02 lea 0x2(%rdi),%r10 + 4270ff: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 427106: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42710d: 0f 1f 00 nopl (%rax) + 427110: 49 83 c2 10 add $0x10,%r10 + 427114: 0f 8f 26 01 00 00 jg 427240 <__GI___strcasecmp_l+0x670> + 42711a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42711f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 427124: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 427128: 66 0f 73 db 02 psrldq $0x2,%xmm3 + 42712d: 66 0f 73 fa 0e pslldq $0xe,%xmm2 + 427132: 66 0f eb d3 por %xmm3,%xmm2 + 427136: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 42713b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 427140: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 427145: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 42714a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 42714f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 427154: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 427159: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 42715e: 66 45 0f db c1 pand %xmm9,%xmm8 + 427163: 66 45 0f db d3 pand %xmm11,%xmm10 + 427168: 66 44 0f db c7 pand %xmm7,%xmm8 + 42716d: 66 44 0f db d7 pand %xmm7,%xmm10 + 427172: 66 41 0f eb c8 por %xmm8,%xmm1 + 427177: 66 41 0f eb d2 por %xmm10,%xmm2 + 42717c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 427180: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 427184: 66 0f f8 c8 psubb %xmm0,%xmm1 + 427188: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42718c: 81 ea ff ff 00 00 sub $0xffff,%edx + 427192: 0f 85 08 1c 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 427198: 48 83 c1 10 add $0x10,%rcx + 42719c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 4271a0: 49 83 c2 10 add $0x10,%r10 + 4271a4: 0f 8f 96 00 00 00 jg 427240 <__GI___strcasecmp_l+0x670> + 4271aa: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4271af: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4271b4: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 4271b8: 66 0f 73 db 02 psrldq $0x2,%xmm3 + 4271bd: 66 0f 73 fa 0e pslldq $0xe,%xmm2 + 4271c2: 66 0f eb d3 por %xmm3,%xmm2 + 4271c6: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 4271cb: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 4271d0: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 4271d5: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 4271da: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 4271df: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 4271e4: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 4271e9: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 4271ee: 66 45 0f db c1 pand %xmm9,%xmm8 + 4271f3: 66 45 0f db d3 pand %xmm11,%xmm10 + 4271f8: 66 44 0f db c7 pand %xmm7,%xmm8 + 4271fd: 66 44 0f db d7 pand %xmm7,%xmm10 + 427202: 66 41 0f eb c8 por %xmm8,%xmm1 + 427207: 66 41 0f eb d2 por %xmm10,%xmm2 + 42720c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 427210: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 427214: 66 0f f8 c8 psubb %xmm0,%xmm1 + 427218: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42721c: 81 ea ff ff 00 00 sub $0xffff,%edx + 427222: 0f 85 78 1b 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 427228: 48 83 c1 10 add $0x10,%rcx + 42722c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 427230: e9 db fe ff ff jmpq 427110 <__GI___strcasecmp_l+0x540> + 427235: 90 nop + 427236: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42723d: 00 00 00 + 427240: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 427244: 66 0f d7 d0 pmovmskb %xmm0,%edx + 427248: f7 c2 fc ff 00 00 test $0xfffc,%edx + 42724e: 75 10 jne 427260 <__GI___strcasecmp_l+0x690> + 427250: 66 0f ef c0 pxor %xmm0,%xmm0 + 427254: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42725b: e9 ba fe ff ff jmpq 42711a <__GI___strcasecmp_l+0x54a> + 427260: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 427265: 66 0f 73 d8 02 psrldq $0x2,%xmm0 + 42726a: 66 0f 73 db 02 psrldq $0x2,%xmm3 + 42726f: e9 cc 1a 00 00 jmpq 428d40 <__GI___strcasecmp_l+0x2170> + 427274: 66 90 xchg %ax,%ax + 427276: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42727d: 00 00 00 + 427280: 66 0f ef c0 pxor %xmm0,%xmm0 + 427284: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 427288: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42728c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 427290: 66 0f 73 fa 0d pslldq $0xd,%xmm2 + 427295: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 42729a: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 42729f: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 4272a4: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 4272a9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 4272ae: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 4272b3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 4272b8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 4272bd: 66 45 0f db c1 pand %xmm9,%xmm8 + 4272c2: 66 45 0f db d3 pand %xmm11,%xmm10 + 4272c7: 66 44 0f db c7 pand %xmm7,%xmm8 + 4272cc: 66 44 0f db d7 pand %xmm7,%xmm10 + 4272d1: 66 41 0f eb c8 por %xmm8,%xmm1 + 4272d6: 66 41 0f eb d2 por %xmm10,%xmm2 + 4272db: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 4272df: 66 0f f8 d0 psubb %xmm0,%xmm2 + 4272e3: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 4272e8: d3 ea shr %cl,%edx + 4272ea: 41 d3 e9 shr %cl,%r9d + 4272ed: 44 29 ca sub %r9d,%edx + 4272f0: 0f 85 af 1a 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> + 4272f6: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 4272fa: 66 0f ef c0 pxor %xmm0,%xmm0 + 4272fe: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 427305: 41 b9 03 00 00 00 mov $0x3,%r9d + 42730b: 4c 8d 57 03 lea 0x3(%rdi),%r10 + 42730f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 427316: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42731d: 0f 1f 00 nopl (%rax) + 427320: 49 83 c2 10 add $0x10,%r10 + 427324: 0f 8f 26 01 00 00 jg 427450 <__GI___strcasecmp_l+0x880> + 42732a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42732f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 427334: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 427338: 66 0f 73 db 03 psrldq $0x3,%xmm3 + 42733d: 66 0f 73 fa 0d pslldq $0xd,%xmm2 + 427342: 66 0f eb d3 por %xmm3,%xmm2 + 427346: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 42734b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 427350: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 427355: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 42735a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 42735f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 427364: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 427369: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 42736e: 66 45 0f db c1 pand %xmm9,%xmm8 + 427373: 66 45 0f db d3 pand %xmm11,%xmm10 + 427378: 66 44 0f db c7 pand %xmm7,%xmm8 + 42737d: 66 44 0f db d7 pand %xmm7,%xmm10 + 427382: 66 41 0f eb c8 por %xmm8,%xmm1 + 427387: 66 41 0f eb d2 por %xmm10,%xmm2 + 42738c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 427390: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 427394: 66 0f f8 c8 psubb %xmm0,%xmm1 + 427398: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42739c: 81 ea ff ff 00 00 sub $0xffff,%edx + 4273a2: 0f 85 f8 19 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 4273a8: 48 83 c1 10 add $0x10,%rcx + 4273ac: 66 0f 6f dc movdqa %xmm4,%xmm3 + 4273b0: 49 83 c2 10 add $0x10,%r10 + 4273b4: 0f 8f 96 00 00 00 jg 427450 <__GI___strcasecmp_l+0x880> + 4273ba: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4273bf: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4273c4: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 4273c8: 66 0f 73 db 03 psrldq $0x3,%xmm3 + 4273cd: 66 0f 73 fa 0d pslldq $0xd,%xmm2 + 4273d2: 66 0f eb d3 por %xmm3,%xmm2 + 4273d6: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 4273db: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 4273e0: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 4273e5: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 4273ea: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 4273ef: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 4273f4: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 4273f9: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 4273fe: 66 45 0f db c1 pand %xmm9,%xmm8 + 427403: 66 45 0f db d3 pand %xmm11,%xmm10 + 427408: 66 44 0f db c7 pand %xmm7,%xmm8 + 42740d: 66 44 0f db d7 pand %xmm7,%xmm10 + 427412: 66 41 0f eb c8 por %xmm8,%xmm1 + 427417: 66 41 0f eb d2 por %xmm10,%xmm2 + 42741c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 427420: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 427424: 66 0f f8 c8 psubb %xmm0,%xmm1 + 427428: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42742c: 81 ea ff ff 00 00 sub $0xffff,%edx + 427432: 0f 85 68 19 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 427438: 48 83 c1 10 add $0x10,%rcx + 42743c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 427440: e9 db fe ff ff jmpq 427320 <__GI___strcasecmp_l+0x750> + 427445: 90 nop + 427446: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42744d: 00 00 00 + 427450: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 427454: 66 0f d7 d0 pmovmskb %xmm0,%edx + 427458: f7 c2 f8 ff 00 00 test $0xfff8,%edx + 42745e: 75 10 jne 427470 <__GI___strcasecmp_l+0x8a0> + 427460: 66 0f ef c0 pxor %xmm0,%xmm0 + 427464: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42746b: e9 ba fe ff ff jmpq 42732a <__GI___strcasecmp_l+0x75a> + 427470: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 427475: 66 0f 73 d8 03 psrldq $0x3,%xmm0 + 42747a: 66 0f 73 db 03 psrldq $0x3,%xmm3 + 42747f: e9 bc 18 00 00 jmpq 428d40 <__GI___strcasecmp_l+0x2170> + 427484: 66 90 xchg %ax,%ax + 427486: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42748d: 00 00 00 + 427490: 66 0f ef c0 pxor %xmm0,%xmm0 + 427494: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 427498: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42749c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4274a0: 66 0f 73 fa 0c pslldq $0xc,%xmm2 + 4274a5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 4274aa: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 4274af: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 4274b4: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 4274b9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 4274be: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 4274c3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 4274c8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 4274cd: 66 45 0f db c1 pand %xmm9,%xmm8 + 4274d2: 66 45 0f db d3 pand %xmm11,%xmm10 + 4274d7: 66 44 0f db c7 pand %xmm7,%xmm8 + 4274dc: 66 44 0f db d7 pand %xmm7,%xmm10 + 4274e1: 66 41 0f eb c8 por %xmm8,%xmm1 + 4274e6: 66 41 0f eb d2 por %xmm10,%xmm2 + 4274eb: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 4274ef: 66 0f f8 d0 psubb %xmm0,%xmm2 + 4274f3: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 4274f8: d3 ea shr %cl,%edx + 4274fa: 41 d3 e9 shr %cl,%r9d + 4274fd: 44 29 ca sub %r9d,%edx + 427500: 0f 85 9f 18 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> + 427506: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 42750a: 66 0f ef c0 pxor %xmm0,%xmm0 + 42750e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 427515: 41 b9 04 00 00 00 mov $0x4,%r9d + 42751b: 4c 8d 57 04 lea 0x4(%rdi),%r10 + 42751f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 427526: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42752d: 0f 1f 00 nopl (%rax) + 427530: 49 83 c2 10 add $0x10,%r10 + 427534: 0f 8f 26 01 00 00 jg 427660 <__GI___strcasecmp_l+0xa90> + 42753a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42753f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 427544: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 427548: 66 0f 73 db 04 psrldq $0x4,%xmm3 + 42754d: 66 0f 73 fa 0c pslldq $0xc,%xmm2 + 427552: 66 0f eb d3 por %xmm3,%xmm2 + 427556: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 42755b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 427560: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 427565: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 42756a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 42756f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 427574: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 427579: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 42757e: 66 45 0f db c1 pand %xmm9,%xmm8 + 427583: 66 45 0f db d3 pand %xmm11,%xmm10 + 427588: 66 44 0f db c7 pand %xmm7,%xmm8 + 42758d: 66 44 0f db d7 pand %xmm7,%xmm10 + 427592: 66 41 0f eb c8 por %xmm8,%xmm1 + 427597: 66 41 0f eb d2 por %xmm10,%xmm2 + 42759c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4275a0: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 4275a4: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4275a8: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4275ac: 81 ea ff ff 00 00 sub $0xffff,%edx + 4275b2: 0f 85 e8 17 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 4275b8: 48 83 c1 10 add $0x10,%rcx + 4275bc: 66 0f 6f dc movdqa %xmm4,%xmm3 + 4275c0: 49 83 c2 10 add $0x10,%r10 + 4275c4: 0f 8f 96 00 00 00 jg 427660 <__GI___strcasecmp_l+0xa90> + 4275ca: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4275cf: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4275d4: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 4275d8: 66 0f 73 db 04 psrldq $0x4,%xmm3 + 4275dd: 66 0f 73 fa 0c pslldq $0xc,%xmm2 + 4275e2: 66 0f eb d3 por %xmm3,%xmm2 + 4275e6: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 4275eb: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 4275f0: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 4275f5: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 4275fa: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 4275ff: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 427604: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 427609: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 42760e: 66 45 0f db c1 pand %xmm9,%xmm8 + 427613: 66 45 0f db d3 pand %xmm11,%xmm10 + 427618: 66 44 0f db c7 pand %xmm7,%xmm8 + 42761d: 66 44 0f db d7 pand %xmm7,%xmm10 + 427622: 66 41 0f eb c8 por %xmm8,%xmm1 + 427627: 66 41 0f eb d2 por %xmm10,%xmm2 + 42762c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 427630: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 427634: 66 0f f8 c8 psubb %xmm0,%xmm1 + 427638: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42763c: 81 ea ff ff 00 00 sub $0xffff,%edx + 427642: 0f 85 58 17 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 427648: 48 83 c1 10 add $0x10,%rcx + 42764c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 427650: e9 db fe ff ff jmpq 427530 <__GI___strcasecmp_l+0x960> + 427655: 90 nop + 427656: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42765d: 00 00 00 + 427660: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 427664: 66 0f d7 d0 pmovmskb %xmm0,%edx + 427668: f7 c2 f0 ff 00 00 test $0xfff0,%edx + 42766e: 75 10 jne 427680 <__GI___strcasecmp_l+0xab0> + 427670: 66 0f ef c0 pxor %xmm0,%xmm0 + 427674: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42767b: e9 ba fe ff ff jmpq 42753a <__GI___strcasecmp_l+0x96a> + 427680: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 427685: 66 0f 73 d8 04 psrldq $0x4,%xmm0 + 42768a: 66 0f 73 db 04 psrldq $0x4,%xmm3 + 42768f: e9 ac 16 00 00 jmpq 428d40 <__GI___strcasecmp_l+0x2170> + 427694: 66 90 xchg %ax,%ax + 427696: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42769d: 00 00 00 + 4276a0: 66 0f ef c0 pxor %xmm0,%xmm0 + 4276a4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 4276a8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 4276ac: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4276b0: 66 0f 73 fa 0b pslldq $0xb,%xmm2 + 4276b5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 4276ba: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 4276bf: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 4276c4: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 4276c9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 4276ce: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 4276d3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 4276d8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 4276dd: 66 45 0f db c1 pand %xmm9,%xmm8 + 4276e2: 66 45 0f db d3 pand %xmm11,%xmm10 + 4276e7: 66 44 0f db c7 pand %xmm7,%xmm8 + 4276ec: 66 44 0f db d7 pand %xmm7,%xmm10 + 4276f1: 66 41 0f eb c8 por %xmm8,%xmm1 + 4276f6: 66 41 0f eb d2 por %xmm10,%xmm2 + 4276fb: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 4276ff: 66 0f f8 d0 psubb %xmm0,%xmm2 + 427703: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 427708: d3 ea shr %cl,%edx + 42770a: 41 d3 e9 shr %cl,%r9d + 42770d: 44 29 ca sub %r9d,%edx + 427710: 0f 85 8f 16 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> + 427716: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 42771a: 66 0f ef c0 pxor %xmm0,%xmm0 + 42771e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 427725: 41 b9 05 00 00 00 mov $0x5,%r9d + 42772b: 4c 8d 57 05 lea 0x5(%rdi),%r10 + 42772f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 427736: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42773d: 0f 1f 00 nopl (%rax) + 427740: 49 83 c2 10 add $0x10,%r10 + 427744: 0f 8f 26 01 00 00 jg 427870 <__GI___strcasecmp_l+0xca0> + 42774a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42774f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 427754: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 427758: 66 0f 73 db 05 psrldq $0x5,%xmm3 + 42775d: 66 0f 73 fa 0b pslldq $0xb,%xmm2 + 427762: 66 0f eb d3 por %xmm3,%xmm2 + 427766: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 42776b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 427770: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 427775: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 42777a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 42777f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 427784: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 427789: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 42778e: 66 45 0f db c1 pand %xmm9,%xmm8 + 427793: 66 45 0f db d3 pand %xmm11,%xmm10 + 427798: 66 44 0f db c7 pand %xmm7,%xmm8 + 42779d: 66 44 0f db d7 pand %xmm7,%xmm10 + 4277a2: 66 41 0f eb c8 por %xmm8,%xmm1 + 4277a7: 66 41 0f eb d2 por %xmm10,%xmm2 + 4277ac: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4277b0: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 4277b4: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4277b8: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4277bc: 81 ea ff ff 00 00 sub $0xffff,%edx + 4277c2: 0f 85 d8 15 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 4277c8: 48 83 c1 10 add $0x10,%rcx + 4277cc: 66 0f 6f dc movdqa %xmm4,%xmm3 + 4277d0: 49 83 c2 10 add $0x10,%r10 + 4277d4: 0f 8f 96 00 00 00 jg 427870 <__GI___strcasecmp_l+0xca0> + 4277da: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4277df: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4277e4: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 4277e8: 66 0f 73 db 05 psrldq $0x5,%xmm3 + 4277ed: 66 0f 73 fa 0b pslldq $0xb,%xmm2 + 4277f2: 66 0f eb d3 por %xmm3,%xmm2 + 4277f6: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 4277fb: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 427800: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 427805: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 42780a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 42780f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 427814: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 427819: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 42781e: 66 45 0f db c1 pand %xmm9,%xmm8 + 427823: 66 45 0f db d3 pand %xmm11,%xmm10 + 427828: 66 44 0f db c7 pand %xmm7,%xmm8 + 42782d: 66 44 0f db d7 pand %xmm7,%xmm10 + 427832: 66 41 0f eb c8 por %xmm8,%xmm1 + 427837: 66 41 0f eb d2 por %xmm10,%xmm2 + 42783c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 427840: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 427844: 66 0f f8 c8 psubb %xmm0,%xmm1 + 427848: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42784c: 81 ea ff ff 00 00 sub $0xffff,%edx + 427852: 0f 85 48 15 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 427858: 48 83 c1 10 add $0x10,%rcx + 42785c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 427860: e9 db fe ff ff jmpq 427740 <__GI___strcasecmp_l+0xb70> + 427865: 90 nop + 427866: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42786d: 00 00 00 + 427870: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 427874: 66 0f d7 d0 pmovmskb %xmm0,%edx + 427878: f7 c2 e0 ff 00 00 test $0xffe0,%edx + 42787e: 75 10 jne 427890 <__GI___strcasecmp_l+0xcc0> + 427880: 66 0f ef c0 pxor %xmm0,%xmm0 + 427884: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42788b: e9 ba fe ff ff jmpq 42774a <__GI___strcasecmp_l+0xb7a> + 427890: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 427895: 66 0f 73 d8 05 psrldq $0x5,%xmm0 + 42789a: 66 0f 73 db 05 psrldq $0x5,%xmm3 + 42789f: e9 9c 14 00 00 jmpq 428d40 <__GI___strcasecmp_l+0x2170> + 4278a4: 66 90 xchg %ax,%ax + 4278a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4278ad: 00 00 00 + 4278b0: 66 0f ef c0 pxor %xmm0,%xmm0 + 4278b4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 4278b8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 4278bc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4278c0: 66 0f 73 fa 0a pslldq $0xa,%xmm2 + 4278c5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 4278ca: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 4278cf: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 4278d4: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 4278d9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 4278de: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 4278e3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 4278e8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 4278ed: 66 45 0f db c1 pand %xmm9,%xmm8 + 4278f2: 66 45 0f db d3 pand %xmm11,%xmm10 + 4278f7: 66 44 0f db c7 pand %xmm7,%xmm8 + 4278fc: 66 44 0f db d7 pand %xmm7,%xmm10 + 427901: 66 41 0f eb c8 por %xmm8,%xmm1 + 427906: 66 41 0f eb d2 por %xmm10,%xmm2 + 42790b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42790f: 66 0f f8 d0 psubb %xmm0,%xmm2 + 427913: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 427918: d3 ea shr %cl,%edx + 42791a: 41 d3 e9 shr %cl,%r9d + 42791d: 44 29 ca sub %r9d,%edx + 427920: 0f 85 7f 14 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> + 427926: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 42792a: 66 0f ef c0 pxor %xmm0,%xmm0 + 42792e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 427935: 41 b9 06 00 00 00 mov $0x6,%r9d + 42793b: 4c 8d 57 06 lea 0x6(%rdi),%r10 + 42793f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 427946: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42794d: 0f 1f 00 nopl (%rax) + 427950: 49 83 c2 10 add $0x10,%r10 + 427954: 0f 8f 26 01 00 00 jg 427a80 <__GI___strcasecmp_l+0xeb0> + 42795a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42795f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 427964: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 427968: 66 0f 73 db 06 psrldq $0x6,%xmm3 + 42796d: 66 0f 73 fa 0a pslldq $0xa,%xmm2 + 427972: 66 0f eb d3 por %xmm3,%xmm2 + 427976: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 42797b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 427980: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 427985: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 42798a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 42798f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 427994: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 427999: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 42799e: 66 45 0f db c1 pand %xmm9,%xmm8 + 4279a3: 66 45 0f db d3 pand %xmm11,%xmm10 + 4279a8: 66 44 0f db c7 pand %xmm7,%xmm8 + 4279ad: 66 44 0f db d7 pand %xmm7,%xmm10 + 4279b2: 66 41 0f eb c8 por %xmm8,%xmm1 + 4279b7: 66 41 0f eb d2 por %xmm10,%xmm2 + 4279bc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4279c0: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 4279c4: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4279c8: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4279cc: 81 ea ff ff 00 00 sub $0xffff,%edx + 4279d2: 0f 85 c8 13 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 4279d8: 48 83 c1 10 add $0x10,%rcx + 4279dc: 66 0f 6f dc movdqa %xmm4,%xmm3 + 4279e0: 49 83 c2 10 add $0x10,%r10 + 4279e4: 0f 8f 96 00 00 00 jg 427a80 <__GI___strcasecmp_l+0xeb0> + 4279ea: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4279ef: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4279f4: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 4279f8: 66 0f 73 db 06 psrldq $0x6,%xmm3 + 4279fd: 66 0f 73 fa 0a pslldq $0xa,%xmm2 + 427a02: 66 0f eb d3 por %xmm3,%xmm2 + 427a06: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 427a0b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 427a10: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 427a15: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 427a1a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 427a1f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 427a24: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 427a29: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 427a2e: 66 45 0f db c1 pand %xmm9,%xmm8 + 427a33: 66 45 0f db d3 pand %xmm11,%xmm10 + 427a38: 66 44 0f db c7 pand %xmm7,%xmm8 + 427a3d: 66 44 0f db d7 pand %xmm7,%xmm10 + 427a42: 66 41 0f eb c8 por %xmm8,%xmm1 + 427a47: 66 41 0f eb d2 por %xmm10,%xmm2 + 427a4c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 427a50: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 427a54: 66 0f f8 c8 psubb %xmm0,%xmm1 + 427a58: 66 0f d7 d1 pmovmskb %xmm1,%edx + 427a5c: 81 ea ff ff 00 00 sub $0xffff,%edx + 427a62: 0f 85 38 13 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 427a68: 48 83 c1 10 add $0x10,%rcx + 427a6c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 427a70: e9 db fe ff ff jmpq 427950 <__GI___strcasecmp_l+0xd80> + 427a75: 90 nop + 427a76: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 427a7d: 00 00 00 + 427a80: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 427a84: 66 0f d7 d0 pmovmskb %xmm0,%edx + 427a88: f7 c2 c0 ff 00 00 test $0xffc0,%edx + 427a8e: 75 10 jne 427aa0 <__GI___strcasecmp_l+0xed0> + 427a90: 66 0f ef c0 pxor %xmm0,%xmm0 + 427a94: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 427a9b: e9 ba fe ff ff jmpq 42795a <__GI___strcasecmp_l+0xd8a> + 427aa0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 427aa5: 66 0f 73 d8 06 psrldq $0x6,%xmm0 + 427aaa: 66 0f 73 db 06 psrldq $0x6,%xmm3 + 427aaf: e9 8c 12 00 00 jmpq 428d40 <__GI___strcasecmp_l+0x2170> + 427ab4: 66 90 xchg %ax,%ax + 427ab6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 427abd: 00 00 00 + 427ac0: 66 0f ef c0 pxor %xmm0,%xmm0 + 427ac4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 427ac8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 427acc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 427ad0: 66 0f 73 fa 09 pslldq $0x9,%xmm2 + 427ad5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 427ada: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 427adf: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 427ae4: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 427ae9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 427aee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 427af3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 427af8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 427afd: 66 45 0f db c1 pand %xmm9,%xmm8 + 427b02: 66 45 0f db d3 pand %xmm11,%xmm10 + 427b07: 66 44 0f db c7 pand %xmm7,%xmm8 + 427b0c: 66 44 0f db d7 pand %xmm7,%xmm10 + 427b11: 66 41 0f eb c8 por %xmm8,%xmm1 + 427b16: 66 41 0f eb d2 por %xmm10,%xmm2 + 427b1b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 427b1f: 66 0f f8 d0 psubb %xmm0,%xmm2 + 427b23: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 427b28: d3 ea shr %cl,%edx + 427b2a: 41 d3 e9 shr %cl,%r9d + 427b2d: 44 29 ca sub %r9d,%edx + 427b30: 0f 85 6f 12 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> + 427b36: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 427b3a: 66 0f ef c0 pxor %xmm0,%xmm0 + 427b3e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 427b45: 41 b9 07 00 00 00 mov $0x7,%r9d + 427b4b: 4c 8d 57 07 lea 0x7(%rdi),%r10 + 427b4f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 427b56: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 427b5d: 0f 1f 00 nopl (%rax) + 427b60: 49 83 c2 10 add $0x10,%r10 + 427b64: 0f 8f 26 01 00 00 jg 427c90 <__GI___strcasecmp_l+0x10c0> + 427b6a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 427b6f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 427b74: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 427b78: 66 0f 73 db 07 psrldq $0x7,%xmm3 + 427b7d: 66 0f 73 fa 09 pslldq $0x9,%xmm2 + 427b82: 66 0f eb d3 por %xmm3,%xmm2 + 427b86: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 427b8b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 427b90: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 427b95: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 427b9a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 427b9f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 427ba4: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 427ba9: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 427bae: 66 45 0f db c1 pand %xmm9,%xmm8 + 427bb3: 66 45 0f db d3 pand %xmm11,%xmm10 + 427bb8: 66 44 0f db c7 pand %xmm7,%xmm8 + 427bbd: 66 44 0f db d7 pand %xmm7,%xmm10 + 427bc2: 66 41 0f eb c8 por %xmm8,%xmm1 + 427bc7: 66 41 0f eb d2 por %xmm10,%xmm2 + 427bcc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 427bd0: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 427bd4: 66 0f f8 c8 psubb %xmm0,%xmm1 + 427bd8: 66 0f d7 d1 pmovmskb %xmm1,%edx + 427bdc: 81 ea ff ff 00 00 sub $0xffff,%edx + 427be2: 0f 85 b8 11 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 427be8: 48 83 c1 10 add $0x10,%rcx + 427bec: 66 0f 6f dc movdqa %xmm4,%xmm3 + 427bf0: 49 83 c2 10 add $0x10,%r10 + 427bf4: 0f 8f 96 00 00 00 jg 427c90 <__GI___strcasecmp_l+0x10c0> + 427bfa: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 427bff: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 427c04: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 427c08: 66 0f 73 db 07 psrldq $0x7,%xmm3 + 427c0d: 66 0f 73 fa 09 pslldq $0x9,%xmm2 + 427c12: 66 0f eb d3 por %xmm3,%xmm2 + 427c16: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 427c1b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 427c20: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 427c25: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 427c2a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 427c2f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 427c34: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 427c39: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 427c3e: 66 45 0f db c1 pand %xmm9,%xmm8 + 427c43: 66 45 0f db d3 pand %xmm11,%xmm10 + 427c48: 66 44 0f db c7 pand %xmm7,%xmm8 + 427c4d: 66 44 0f db d7 pand %xmm7,%xmm10 + 427c52: 66 41 0f eb c8 por %xmm8,%xmm1 + 427c57: 66 41 0f eb d2 por %xmm10,%xmm2 + 427c5c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 427c60: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 427c64: 66 0f f8 c8 psubb %xmm0,%xmm1 + 427c68: 66 0f d7 d1 pmovmskb %xmm1,%edx + 427c6c: 81 ea ff ff 00 00 sub $0xffff,%edx + 427c72: 0f 85 28 11 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 427c78: 48 83 c1 10 add $0x10,%rcx + 427c7c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 427c80: e9 db fe ff ff jmpq 427b60 <__GI___strcasecmp_l+0xf90> + 427c85: 90 nop + 427c86: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 427c8d: 00 00 00 + 427c90: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 427c94: 66 0f d7 d0 pmovmskb %xmm0,%edx + 427c98: f7 c2 80 ff 00 00 test $0xff80,%edx + 427c9e: 75 10 jne 427cb0 <__GI___strcasecmp_l+0x10e0> + 427ca0: 66 0f ef c0 pxor %xmm0,%xmm0 + 427ca4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 427cab: e9 ba fe ff ff jmpq 427b6a <__GI___strcasecmp_l+0xf9a> + 427cb0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 427cb5: 66 0f 73 d8 07 psrldq $0x7,%xmm0 + 427cba: 66 0f 73 db 07 psrldq $0x7,%xmm3 + 427cbf: e9 7c 10 00 00 jmpq 428d40 <__GI___strcasecmp_l+0x2170> + 427cc4: 66 90 xchg %ax,%ax + 427cc6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 427ccd: 00 00 00 + 427cd0: 66 0f ef c0 pxor %xmm0,%xmm0 + 427cd4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 427cd8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 427cdc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 427ce0: 66 0f 73 fa 08 pslldq $0x8,%xmm2 + 427ce5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 427cea: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 427cef: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 427cf4: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 427cf9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 427cfe: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 427d03: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 427d08: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 427d0d: 66 45 0f db c1 pand %xmm9,%xmm8 + 427d12: 66 45 0f db d3 pand %xmm11,%xmm10 + 427d17: 66 44 0f db c7 pand %xmm7,%xmm8 + 427d1c: 66 44 0f db d7 pand %xmm7,%xmm10 + 427d21: 66 41 0f eb c8 por %xmm8,%xmm1 + 427d26: 66 41 0f eb d2 por %xmm10,%xmm2 + 427d2b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 427d2f: 66 0f f8 d0 psubb %xmm0,%xmm2 + 427d33: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 427d38: d3 ea shr %cl,%edx + 427d3a: 41 d3 e9 shr %cl,%r9d + 427d3d: 44 29 ca sub %r9d,%edx + 427d40: 0f 85 5f 10 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> + 427d46: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 427d4a: 66 0f ef c0 pxor %xmm0,%xmm0 + 427d4e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 427d55: 41 b9 08 00 00 00 mov $0x8,%r9d + 427d5b: 4c 8d 57 08 lea 0x8(%rdi),%r10 + 427d5f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 427d66: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 427d6d: 0f 1f 00 nopl (%rax) + 427d70: 49 83 c2 10 add $0x10,%r10 + 427d74: 0f 8f 26 01 00 00 jg 427ea0 <__GI___strcasecmp_l+0x12d0> + 427d7a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 427d7f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 427d84: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 427d88: 66 0f 73 db 08 psrldq $0x8,%xmm3 + 427d8d: 66 0f 73 fa 08 pslldq $0x8,%xmm2 + 427d92: 66 0f eb d3 por %xmm3,%xmm2 + 427d96: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 427d9b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 427da0: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 427da5: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 427daa: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 427daf: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 427db4: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 427db9: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 427dbe: 66 45 0f db c1 pand %xmm9,%xmm8 + 427dc3: 66 45 0f db d3 pand %xmm11,%xmm10 + 427dc8: 66 44 0f db c7 pand %xmm7,%xmm8 + 427dcd: 66 44 0f db d7 pand %xmm7,%xmm10 + 427dd2: 66 41 0f eb c8 por %xmm8,%xmm1 + 427dd7: 66 41 0f eb d2 por %xmm10,%xmm2 + 427ddc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 427de0: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 427de4: 66 0f f8 c8 psubb %xmm0,%xmm1 + 427de8: 66 0f d7 d1 pmovmskb %xmm1,%edx + 427dec: 81 ea ff ff 00 00 sub $0xffff,%edx + 427df2: 0f 85 a8 0f 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 427df8: 48 83 c1 10 add $0x10,%rcx + 427dfc: 66 0f 6f dc movdqa %xmm4,%xmm3 + 427e00: 49 83 c2 10 add $0x10,%r10 + 427e04: 0f 8f 96 00 00 00 jg 427ea0 <__GI___strcasecmp_l+0x12d0> + 427e0a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 427e0f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 427e14: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 427e18: 66 0f 73 db 08 psrldq $0x8,%xmm3 + 427e1d: 66 0f 73 fa 08 pslldq $0x8,%xmm2 + 427e22: 66 0f eb d3 por %xmm3,%xmm2 + 427e26: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 427e2b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 427e30: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 427e35: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 427e3a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 427e3f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 427e44: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 427e49: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 427e4e: 66 45 0f db c1 pand %xmm9,%xmm8 + 427e53: 66 45 0f db d3 pand %xmm11,%xmm10 + 427e58: 66 44 0f db c7 pand %xmm7,%xmm8 + 427e5d: 66 44 0f db d7 pand %xmm7,%xmm10 + 427e62: 66 41 0f eb c8 por %xmm8,%xmm1 + 427e67: 66 41 0f eb d2 por %xmm10,%xmm2 + 427e6c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 427e70: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 427e74: 66 0f f8 c8 psubb %xmm0,%xmm1 + 427e78: 66 0f d7 d1 pmovmskb %xmm1,%edx + 427e7c: 81 ea ff ff 00 00 sub $0xffff,%edx + 427e82: 0f 85 18 0f 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 427e88: 48 83 c1 10 add $0x10,%rcx + 427e8c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 427e90: e9 db fe ff ff jmpq 427d70 <__GI___strcasecmp_l+0x11a0> + 427e95: 90 nop + 427e96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 427e9d: 00 00 00 + 427ea0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 427ea4: 66 0f d7 d0 pmovmskb %xmm0,%edx + 427ea8: f7 c2 00 ff 00 00 test $0xff00,%edx + 427eae: 75 10 jne 427ec0 <__GI___strcasecmp_l+0x12f0> + 427eb0: 66 0f ef c0 pxor %xmm0,%xmm0 + 427eb4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 427ebb: e9 ba fe ff ff jmpq 427d7a <__GI___strcasecmp_l+0x11aa> + 427ec0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 427ec5: 66 0f 73 d8 08 psrldq $0x8,%xmm0 + 427eca: 66 0f 73 db 08 psrldq $0x8,%xmm3 + 427ecf: e9 6c 0e 00 00 jmpq 428d40 <__GI___strcasecmp_l+0x2170> + 427ed4: 66 90 xchg %ax,%ax + 427ed6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 427edd: 00 00 00 + 427ee0: 66 0f ef c0 pxor %xmm0,%xmm0 + 427ee4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 427ee8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 427eec: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 427ef0: 66 0f 73 fa 07 pslldq $0x7,%xmm2 + 427ef5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 427efa: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 427eff: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 427f04: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 427f09: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 427f0e: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 427f13: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 427f18: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 427f1d: 66 45 0f db c1 pand %xmm9,%xmm8 + 427f22: 66 45 0f db d3 pand %xmm11,%xmm10 + 427f27: 66 44 0f db c7 pand %xmm7,%xmm8 + 427f2c: 66 44 0f db d7 pand %xmm7,%xmm10 + 427f31: 66 41 0f eb c8 por %xmm8,%xmm1 + 427f36: 66 41 0f eb d2 por %xmm10,%xmm2 + 427f3b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 427f3f: 66 0f f8 d0 psubb %xmm0,%xmm2 + 427f43: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 427f48: d3 ea shr %cl,%edx + 427f4a: 41 d3 e9 shr %cl,%r9d + 427f4d: 44 29 ca sub %r9d,%edx + 427f50: 0f 85 4f 0e 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> + 427f56: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 427f5a: 66 0f ef c0 pxor %xmm0,%xmm0 + 427f5e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 427f65: 41 b9 09 00 00 00 mov $0x9,%r9d + 427f6b: 4c 8d 57 09 lea 0x9(%rdi),%r10 + 427f6f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 427f76: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 427f7d: 0f 1f 00 nopl (%rax) + 427f80: 49 83 c2 10 add $0x10,%r10 + 427f84: 0f 8f 26 01 00 00 jg 4280b0 <__GI___strcasecmp_l+0x14e0> + 427f8a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 427f8f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 427f94: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 427f98: 66 0f 73 db 09 psrldq $0x9,%xmm3 + 427f9d: 66 0f 73 fa 07 pslldq $0x7,%xmm2 + 427fa2: 66 0f eb d3 por %xmm3,%xmm2 + 427fa6: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 427fab: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 427fb0: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 427fb5: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 427fba: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 427fbf: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 427fc4: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 427fc9: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 427fce: 66 45 0f db c1 pand %xmm9,%xmm8 + 427fd3: 66 45 0f db d3 pand %xmm11,%xmm10 + 427fd8: 66 44 0f db c7 pand %xmm7,%xmm8 + 427fdd: 66 44 0f db d7 pand %xmm7,%xmm10 + 427fe2: 66 41 0f eb c8 por %xmm8,%xmm1 + 427fe7: 66 41 0f eb d2 por %xmm10,%xmm2 + 427fec: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 427ff0: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 427ff4: 66 0f f8 c8 psubb %xmm0,%xmm1 + 427ff8: 66 0f d7 d1 pmovmskb %xmm1,%edx + 427ffc: 81 ea ff ff 00 00 sub $0xffff,%edx + 428002: 0f 85 98 0d 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 428008: 48 83 c1 10 add $0x10,%rcx + 42800c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 428010: 49 83 c2 10 add $0x10,%r10 + 428014: 0f 8f 96 00 00 00 jg 4280b0 <__GI___strcasecmp_l+0x14e0> + 42801a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42801f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 428024: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 428028: 66 0f 73 db 09 psrldq $0x9,%xmm3 + 42802d: 66 0f 73 fa 07 pslldq $0x7,%xmm2 + 428032: 66 0f eb d3 por %xmm3,%xmm2 + 428036: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 42803b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 428040: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 428045: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 42804a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 42804f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 428054: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 428059: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 42805e: 66 45 0f db c1 pand %xmm9,%xmm8 + 428063: 66 45 0f db d3 pand %xmm11,%xmm10 + 428068: 66 44 0f db c7 pand %xmm7,%xmm8 + 42806d: 66 44 0f db d7 pand %xmm7,%xmm10 + 428072: 66 41 0f eb c8 por %xmm8,%xmm1 + 428077: 66 41 0f eb d2 por %xmm10,%xmm2 + 42807c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 428080: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 428084: 66 0f f8 c8 psubb %xmm0,%xmm1 + 428088: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42808c: 81 ea ff ff 00 00 sub $0xffff,%edx + 428092: 0f 85 08 0d 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 428098: 48 83 c1 10 add $0x10,%rcx + 42809c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 4280a0: e9 db fe ff ff jmpq 427f80 <__GI___strcasecmp_l+0x13b0> + 4280a5: 90 nop + 4280a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4280ad: 00 00 00 + 4280b0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 4280b4: 66 0f d7 d0 pmovmskb %xmm0,%edx + 4280b8: f7 c2 00 fe 00 00 test $0xfe00,%edx + 4280be: 75 10 jne 4280d0 <__GI___strcasecmp_l+0x1500> + 4280c0: 66 0f ef c0 pxor %xmm0,%xmm0 + 4280c4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 4280cb: e9 ba fe ff ff jmpq 427f8a <__GI___strcasecmp_l+0x13ba> + 4280d0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4280d5: 66 0f 73 d8 09 psrldq $0x9,%xmm0 + 4280da: 66 0f 73 db 09 psrldq $0x9,%xmm3 + 4280df: e9 5c 0c 00 00 jmpq 428d40 <__GI___strcasecmp_l+0x2170> + 4280e4: 66 90 xchg %ax,%ax + 4280e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4280ed: 00 00 00 + 4280f0: 66 0f ef c0 pxor %xmm0,%xmm0 + 4280f4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 4280f8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 4280fc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 428100: 66 0f 73 fa 06 pslldq $0x6,%xmm2 + 428105: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 42810a: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 42810f: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 428114: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 428119: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 42811e: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 428123: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 428128: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 42812d: 66 45 0f db c1 pand %xmm9,%xmm8 + 428132: 66 45 0f db d3 pand %xmm11,%xmm10 + 428137: 66 44 0f db c7 pand %xmm7,%xmm8 + 42813c: 66 44 0f db d7 pand %xmm7,%xmm10 + 428141: 66 41 0f eb c8 por %xmm8,%xmm1 + 428146: 66 41 0f eb d2 por %xmm10,%xmm2 + 42814b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42814f: 66 0f f8 d0 psubb %xmm0,%xmm2 + 428153: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 428158: d3 ea shr %cl,%edx + 42815a: 41 d3 e9 shr %cl,%r9d + 42815d: 44 29 ca sub %r9d,%edx + 428160: 0f 85 3f 0c 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> + 428166: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 42816a: 66 0f ef c0 pxor %xmm0,%xmm0 + 42816e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 428175: 41 b9 0a 00 00 00 mov $0xa,%r9d + 42817b: 4c 8d 57 0a lea 0xa(%rdi),%r10 + 42817f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 428186: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42818d: 0f 1f 00 nopl (%rax) + 428190: 49 83 c2 10 add $0x10,%r10 + 428194: 0f 8f 26 01 00 00 jg 4282c0 <__GI___strcasecmp_l+0x16f0> + 42819a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42819f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4281a4: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 4281a8: 66 0f 73 db 0a psrldq $0xa,%xmm3 + 4281ad: 66 0f 73 fa 06 pslldq $0x6,%xmm2 + 4281b2: 66 0f eb d3 por %xmm3,%xmm2 + 4281b6: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 4281bb: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 4281c0: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 4281c5: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 4281ca: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 4281cf: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 4281d4: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 4281d9: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 4281de: 66 45 0f db c1 pand %xmm9,%xmm8 + 4281e3: 66 45 0f db d3 pand %xmm11,%xmm10 + 4281e8: 66 44 0f db c7 pand %xmm7,%xmm8 + 4281ed: 66 44 0f db d7 pand %xmm7,%xmm10 + 4281f2: 66 41 0f eb c8 por %xmm8,%xmm1 + 4281f7: 66 41 0f eb d2 por %xmm10,%xmm2 + 4281fc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 428200: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 428204: 66 0f f8 c8 psubb %xmm0,%xmm1 + 428208: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42820c: 81 ea ff ff 00 00 sub $0xffff,%edx + 428212: 0f 85 88 0b 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 428218: 48 83 c1 10 add $0x10,%rcx + 42821c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 428220: 49 83 c2 10 add $0x10,%r10 + 428224: 0f 8f 96 00 00 00 jg 4282c0 <__GI___strcasecmp_l+0x16f0> + 42822a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42822f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 428234: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 428238: 66 0f 73 db 0a psrldq $0xa,%xmm3 + 42823d: 66 0f 73 fa 06 pslldq $0x6,%xmm2 + 428242: 66 0f eb d3 por %xmm3,%xmm2 + 428246: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 42824b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 428250: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 428255: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 42825a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 42825f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 428264: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 428269: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 42826e: 66 45 0f db c1 pand %xmm9,%xmm8 + 428273: 66 45 0f db d3 pand %xmm11,%xmm10 + 428278: 66 44 0f db c7 pand %xmm7,%xmm8 + 42827d: 66 44 0f db d7 pand %xmm7,%xmm10 + 428282: 66 41 0f eb c8 por %xmm8,%xmm1 + 428287: 66 41 0f eb d2 por %xmm10,%xmm2 + 42828c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 428290: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 428294: 66 0f f8 c8 psubb %xmm0,%xmm1 + 428298: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42829c: 81 ea ff ff 00 00 sub $0xffff,%edx + 4282a2: 0f 85 f8 0a 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 4282a8: 48 83 c1 10 add $0x10,%rcx + 4282ac: 66 0f 6f dc movdqa %xmm4,%xmm3 + 4282b0: e9 db fe ff ff jmpq 428190 <__GI___strcasecmp_l+0x15c0> + 4282b5: 90 nop + 4282b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4282bd: 00 00 00 + 4282c0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 4282c4: 66 0f d7 d0 pmovmskb %xmm0,%edx + 4282c8: f7 c2 00 fc 00 00 test $0xfc00,%edx + 4282ce: 75 10 jne 4282e0 <__GI___strcasecmp_l+0x1710> + 4282d0: 66 0f ef c0 pxor %xmm0,%xmm0 + 4282d4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 4282db: e9 ba fe ff ff jmpq 42819a <__GI___strcasecmp_l+0x15ca> + 4282e0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4282e5: 66 0f 73 d8 0a psrldq $0xa,%xmm0 + 4282ea: 66 0f 73 db 0a psrldq $0xa,%xmm3 + 4282ef: e9 4c 0a 00 00 jmpq 428d40 <__GI___strcasecmp_l+0x2170> + 4282f4: 66 90 xchg %ax,%ax + 4282f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4282fd: 00 00 00 + 428300: 66 0f ef c0 pxor %xmm0,%xmm0 + 428304: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 428308: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42830c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 428310: 66 0f 73 fa 05 pslldq $0x5,%xmm2 + 428315: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 42831a: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 42831f: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 428324: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 428329: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 42832e: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 428333: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 428338: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 42833d: 66 45 0f db c1 pand %xmm9,%xmm8 + 428342: 66 45 0f db d3 pand %xmm11,%xmm10 + 428347: 66 44 0f db c7 pand %xmm7,%xmm8 + 42834c: 66 44 0f db d7 pand %xmm7,%xmm10 + 428351: 66 41 0f eb c8 por %xmm8,%xmm1 + 428356: 66 41 0f eb d2 por %xmm10,%xmm2 + 42835b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42835f: 66 0f f8 d0 psubb %xmm0,%xmm2 + 428363: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 428368: d3 ea shr %cl,%edx + 42836a: 41 d3 e9 shr %cl,%r9d + 42836d: 44 29 ca sub %r9d,%edx + 428370: 0f 85 2f 0a 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> + 428376: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 42837a: 66 0f ef c0 pxor %xmm0,%xmm0 + 42837e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 428385: 41 b9 0b 00 00 00 mov $0xb,%r9d + 42838b: 4c 8d 57 0b lea 0xb(%rdi),%r10 + 42838f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 428396: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42839d: 0f 1f 00 nopl (%rax) + 4283a0: 49 83 c2 10 add $0x10,%r10 + 4283a4: 0f 8f 26 01 00 00 jg 4284d0 <__GI___strcasecmp_l+0x1900> + 4283aa: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4283af: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4283b4: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 4283b8: 66 0f 73 db 0b psrldq $0xb,%xmm3 + 4283bd: 66 0f 73 fa 05 pslldq $0x5,%xmm2 + 4283c2: 66 0f eb d3 por %xmm3,%xmm2 + 4283c6: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 4283cb: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 4283d0: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 4283d5: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 4283da: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 4283df: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 4283e4: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 4283e9: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 4283ee: 66 45 0f db c1 pand %xmm9,%xmm8 + 4283f3: 66 45 0f db d3 pand %xmm11,%xmm10 + 4283f8: 66 44 0f db c7 pand %xmm7,%xmm8 + 4283fd: 66 44 0f db d7 pand %xmm7,%xmm10 + 428402: 66 41 0f eb c8 por %xmm8,%xmm1 + 428407: 66 41 0f eb d2 por %xmm10,%xmm2 + 42840c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 428410: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 428414: 66 0f f8 c8 psubb %xmm0,%xmm1 + 428418: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42841c: 81 ea ff ff 00 00 sub $0xffff,%edx + 428422: 0f 85 78 09 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 428428: 48 83 c1 10 add $0x10,%rcx + 42842c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 428430: 49 83 c2 10 add $0x10,%r10 + 428434: 0f 8f 96 00 00 00 jg 4284d0 <__GI___strcasecmp_l+0x1900> + 42843a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42843f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 428444: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 428448: 66 0f 73 db 0b psrldq $0xb,%xmm3 + 42844d: 66 0f 73 fa 05 pslldq $0x5,%xmm2 + 428452: 66 0f eb d3 por %xmm3,%xmm2 + 428456: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 42845b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 428460: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 428465: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 42846a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 42846f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 428474: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 428479: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 42847e: 66 45 0f db c1 pand %xmm9,%xmm8 + 428483: 66 45 0f db d3 pand %xmm11,%xmm10 + 428488: 66 44 0f db c7 pand %xmm7,%xmm8 + 42848d: 66 44 0f db d7 pand %xmm7,%xmm10 + 428492: 66 41 0f eb c8 por %xmm8,%xmm1 + 428497: 66 41 0f eb d2 por %xmm10,%xmm2 + 42849c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4284a0: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 4284a4: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4284a8: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4284ac: 81 ea ff ff 00 00 sub $0xffff,%edx + 4284b2: 0f 85 e8 08 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 4284b8: 48 83 c1 10 add $0x10,%rcx + 4284bc: 66 0f 6f dc movdqa %xmm4,%xmm3 + 4284c0: e9 db fe ff ff jmpq 4283a0 <__GI___strcasecmp_l+0x17d0> + 4284c5: 90 nop + 4284c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4284cd: 00 00 00 + 4284d0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 4284d4: 66 0f d7 d0 pmovmskb %xmm0,%edx + 4284d8: f7 c2 00 f8 00 00 test $0xf800,%edx + 4284de: 75 10 jne 4284f0 <__GI___strcasecmp_l+0x1920> + 4284e0: 66 0f ef c0 pxor %xmm0,%xmm0 + 4284e4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 4284eb: e9 ba fe ff ff jmpq 4283aa <__GI___strcasecmp_l+0x17da> + 4284f0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4284f5: 66 0f 73 d8 0b psrldq $0xb,%xmm0 + 4284fa: 66 0f 73 db 0b psrldq $0xb,%xmm3 + 4284ff: e9 3c 08 00 00 jmpq 428d40 <__GI___strcasecmp_l+0x2170> + 428504: 66 90 xchg %ax,%ax + 428506: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42850d: 00 00 00 + 428510: 66 0f ef c0 pxor %xmm0,%xmm0 + 428514: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 428518: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42851c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 428520: 66 0f 73 fa 04 pslldq $0x4,%xmm2 + 428525: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 42852a: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 42852f: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 428534: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 428539: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 42853e: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 428543: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 428548: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 42854d: 66 45 0f db c1 pand %xmm9,%xmm8 + 428552: 66 45 0f db d3 pand %xmm11,%xmm10 + 428557: 66 44 0f db c7 pand %xmm7,%xmm8 + 42855c: 66 44 0f db d7 pand %xmm7,%xmm10 + 428561: 66 41 0f eb c8 por %xmm8,%xmm1 + 428566: 66 41 0f eb d2 por %xmm10,%xmm2 + 42856b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42856f: 66 0f f8 d0 psubb %xmm0,%xmm2 + 428573: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 428578: d3 ea shr %cl,%edx + 42857a: 41 d3 e9 shr %cl,%r9d + 42857d: 44 29 ca sub %r9d,%edx + 428580: 0f 85 1f 08 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> + 428586: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 42858a: 66 0f ef c0 pxor %xmm0,%xmm0 + 42858e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 428595: 41 b9 0c 00 00 00 mov $0xc,%r9d + 42859b: 4c 8d 57 0c lea 0xc(%rdi),%r10 + 42859f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 4285a6: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 4285ad: 0f 1f 00 nopl (%rax) + 4285b0: 49 83 c2 10 add $0x10,%r10 + 4285b4: 0f 8f 26 01 00 00 jg 4286e0 <__GI___strcasecmp_l+0x1b10> + 4285ba: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4285bf: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4285c4: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 4285c8: 66 0f 73 db 0c psrldq $0xc,%xmm3 + 4285cd: 66 0f 73 fa 04 pslldq $0x4,%xmm2 + 4285d2: 66 0f eb d3 por %xmm3,%xmm2 + 4285d6: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 4285db: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 4285e0: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 4285e5: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 4285ea: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 4285ef: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 4285f4: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 4285f9: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 4285fe: 66 45 0f db c1 pand %xmm9,%xmm8 + 428603: 66 45 0f db d3 pand %xmm11,%xmm10 + 428608: 66 44 0f db c7 pand %xmm7,%xmm8 + 42860d: 66 44 0f db d7 pand %xmm7,%xmm10 + 428612: 66 41 0f eb c8 por %xmm8,%xmm1 + 428617: 66 41 0f eb d2 por %xmm10,%xmm2 + 42861c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 428620: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 428624: 66 0f f8 c8 psubb %xmm0,%xmm1 + 428628: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42862c: 81 ea ff ff 00 00 sub $0xffff,%edx + 428632: 0f 85 68 07 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 428638: 48 83 c1 10 add $0x10,%rcx + 42863c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 428640: 49 83 c2 10 add $0x10,%r10 + 428644: 0f 8f 96 00 00 00 jg 4286e0 <__GI___strcasecmp_l+0x1b10> + 42864a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42864f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 428654: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 428658: 66 0f 73 db 0c psrldq $0xc,%xmm3 + 42865d: 66 0f 73 fa 04 pslldq $0x4,%xmm2 + 428662: 66 0f eb d3 por %xmm3,%xmm2 + 428666: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 42866b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 428670: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 428675: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 42867a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 42867f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 428684: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 428689: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 42868e: 66 45 0f db c1 pand %xmm9,%xmm8 + 428693: 66 45 0f db d3 pand %xmm11,%xmm10 + 428698: 66 44 0f db c7 pand %xmm7,%xmm8 + 42869d: 66 44 0f db d7 pand %xmm7,%xmm10 + 4286a2: 66 41 0f eb c8 por %xmm8,%xmm1 + 4286a7: 66 41 0f eb d2 por %xmm10,%xmm2 + 4286ac: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4286b0: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 4286b4: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4286b8: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4286bc: 81 ea ff ff 00 00 sub $0xffff,%edx + 4286c2: 0f 85 d8 06 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 4286c8: 48 83 c1 10 add $0x10,%rcx + 4286cc: 66 0f 6f dc movdqa %xmm4,%xmm3 + 4286d0: e9 db fe ff ff jmpq 4285b0 <__GI___strcasecmp_l+0x19e0> + 4286d5: 90 nop + 4286d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4286dd: 00 00 00 + 4286e0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 4286e4: 66 0f d7 d0 pmovmskb %xmm0,%edx + 4286e8: f7 c2 00 f0 00 00 test $0xf000,%edx + 4286ee: 75 10 jne 428700 <__GI___strcasecmp_l+0x1b30> + 4286f0: 66 0f ef c0 pxor %xmm0,%xmm0 + 4286f4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 4286fb: e9 ba fe ff ff jmpq 4285ba <__GI___strcasecmp_l+0x19ea> + 428700: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 428705: 66 0f 73 d8 0c psrldq $0xc,%xmm0 + 42870a: 66 0f 73 db 0c psrldq $0xc,%xmm3 + 42870f: e9 2c 06 00 00 jmpq 428d40 <__GI___strcasecmp_l+0x2170> + 428714: 66 90 xchg %ax,%ax + 428716: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42871d: 00 00 00 + 428720: 66 0f ef c0 pxor %xmm0,%xmm0 + 428724: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 428728: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42872c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 428730: 66 0f 73 fa 03 pslldq $0x3,%xmm2 + 428735: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 42873a: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 42873f: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 428744: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 428749: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 42874e: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 428753: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 428758: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 42875d: 66 45 0f db c1 pand %xmm9,%xmm8 + 428762: 66 45 0f db d3 pand %xmm11,%xmm10 + 428767: 66 44 0f db c7 pand %xmm7,%xmm8 + 42876c: 66 44 0f db d7 pand %xmm7,%xmm10 + 428771: 66 41 0f eb c8 por %xmm8,%xmm1 + 428776: 66 41 0f eb d2 por %xmm10,%xmm2 + 42877b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42877f: 66 0f f8 d0 psubb %xmm0,%xmm2 + 428783: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 428788: d3 ea shr %cl,%edx + 42878a: 41 d3 e9 shr %cl,%r9d + 42878d: 44 29 ca sub %r9d,%edx + 428790: 0f 85 0f 06 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> + 428796: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 42879a: 66 0f ef c0 pxor %xmm0,%xmm0 + 42879e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 4287a5: 41 b9 0d 00 00 00 mov $0xd,%r9d + 4287ab: 4c 8d 57 0d lea 0xd(%rdi),%r10 + 4287af: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 4287b6: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 4287bd: 0f 1f 00 nopl (%rax) + 4287c0: 49 83 c2 10 add $0x10,%r10 + 4287c4: 0f 8f 26 01 00 00 jg 4288f0 <__GI___strcasecmp_l+0x1d20> + 4287ca: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4287cf: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4287d4: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 4287d8: 66 0f 73 db 0d psrldq $0xd,%xmm3 + 4287dd: 66 0f 73 fa 03 pslldq $0x3,%xmm2 + 4287e2: 66 0f eb d3 por %xmm3,%xmm2 + 4287e6: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 4287eb: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 4287f0: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 4287f5: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 4287fa: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 4287ff: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 428804: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 428809: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 42880e: 66 45 0f db c1 pand %xmm9,%xmm8 + 428813: 66 45 0f db d3 pand %xmm11,%xmm10 + 428818: 66 44 0f db c7 pand %xmm7,%xmm8 + 42881d: 66 44 0f db d7 pand %xmm7,%xmm10 + 428822: 66 41 0f eb c8 por %xmm8,%xmm1 + 428827: 66 41 0f eb d2 por %xmm10,%xmm2 + 42882c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 428830: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 428834: 66 0f f8 c8 psubb %xmm0,%xmm1 + 428838: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42883c: 81 ea ff ff 00 00 sub $0xffff,%edx + 428842: 0f 85 58 05 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 428848: 48 83 c1 10 add $0x10,%rcx + 42884c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 428850: 49 83 c2 10 add $0x10,%r10 + 428854: 0f 8f 96 00 00 00 jg 4288f0 <__GI___strcasecmp_l+0x1d20> + 42885a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42885f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 428864: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 428868: 66 0f 73 db 0d psrldq $0xd,%xmm3 + 42886d: 66 0f 73 fa 03 pslldq $0x3,%xmm2 + 428872: 66 0f eb d3 por %xmm3,%xmm2 + 428876: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 42887b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 428880: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 428885: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 42888a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 42888f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 428894: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 428899: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 42889e: 66 45 0f db c1 pand %xmm9,%xmm8 + 4288a3: 66 45 0f db d3 pand %xmm11,%xmm10 + 4288a8: 66 44 0f db c7 pand %xmm7,%xmm8 + 4288ad: 66 44 0f db d7 pand %xmm7,%xmm10 + 4288b2: 66 41 0f eb c8 por %xmm8,%xmm1 + 4288b7: 66 41 0f eb d2 por %xmm10,%xmm2 + 4288bc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4288c0: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 4288c4: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4288c8: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4288cc: 81 ea ff ff 00 00 sub $0xffff,%edx + 4288d2: 0f 85 c8 04 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 4288d8: 48 83 c1 10 add $0x10,%rcx + 4288dc: 66 0f 6f dc movdqa %xmm4,%xmm3 + 4288e0: e9 db fe ff ff jmpq 4287c0 <__GI___strcasecmp_l+0x1bf0> + 4288e5: 90 nop + 4288e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4288ed: 00 00 00 + 4288f0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 4288f4: 66 0f d7 d0 pmovmskb %xmm0,%edx + 4288f8: f7 c2 00 e0 00 00 test $0xe000,%edx + 4288fe: 75 10 jne 428910 <__GI___strcasecmp_l+0x1d40> + 428900: 66 0f ef c0 pxor %xmm0,%xmm0 + 428904: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42890b: e9 ba fe ff ff jmpq 4287ca <__GI___strcasecmp_l+0x1bfa> + 428910: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 428915: 66 0f 73 d8 0d psrldq $0xd,%xmm0 + 42891a: 66 0f 73 db 0d psrldq $0xd,%xmm3 + 42891f: e9 1c 04 00 00 jmpq 428d40 <__GI___strcasecmp_l+0x2170> + 428924: 66 90 xchg %ax,%ax + 428926: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42892d: 00 00 00 + 428930: 66 0f ef c0 pxor %xmm0,%xmm0 + 428934: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 428938: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42893c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 428940: 66 0f 73 fa 02 pslldq $0x2,%xmm2 + 428945: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 42894a: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 42894f: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 428954: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 428959: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 42895e: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 428963: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 428968: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 42896d: 66 45 0f db c1 pand %xmm9,%xmm8 + 428972: 66 45 0f db d3 pand %xmm11,%xmm10 + 428977: 66 44 0f db c7 pand %xmm7,%xmm8 + 42897c: 66 44 0f db d7 pand %xmm7,%xmm10 + 428981: 66 41 0f eb c8 por %xmm8,%xmm1 + 428986: 66 41 0f eb d2 por %xmm10,%xmm2 + 42898b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42898f: 66 0f f8 d0 psubb %xmm0,%xmm2 + 428993: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 428998: d3 ea shr %cl,%edx + 42899a: 41 d3 e9 shr %cl,%r9d + 42899d: 44 29 ca sub %r9d,%edx + 4289a0: 0f 85 ff 03 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> + 4289a6: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 4289aa: 66 0f ef c0 pxor %xmm0,%xmm0 + 4289ae: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 4289b5: 41 b9 0e 00 00 00 mov $0xe,%r9d + 4289bb: 4c 8d 57 0e lea 0xe(%rdi),%r10 + 4289bf: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 4289c6: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 4289cd: 0f 1f 00 nopl (%rax) + 4289d0: 49 83 c2 10 add $0x10,%r10 + 4289d4: 0f 8f 26 01 00 00 jg 428b00 <__GI___strcasecmp_l+0x1f30> + 4289da: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4289df: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4289e4: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 4289e8: 66 0f 73 db 0e psrldq $0xe,%xmm3 + 4289ed: 66 0f 73 fa 02 pslldq $0x2,%xmm2 + 4289f2: 66 0f eb d3 por %xmm3,%xmm2 + 4289f6: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 4289fb: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 428a00: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 428a05: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 428a0a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 428a0f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 428a14: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 428a19: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 428a1e: 66 45 0f db c1 pand %xmm9,%xmm8 + 428a23: 66 45 0f db d3 pand %xmm11,%xmm10 + 428a28: 66 44 0f db c7 pand %xmm7,%xmm8 + 428a2d: 66 44 0f db d7 pand %xmm7,%xmm10 + 428a32: 66 41 0f eb c8 por %xmm8,%xmm1 + 428a37: 66 41 0f eb d2 por %xmm10,%xmm2 + 428a3c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 428a40: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 428a44: 66 0f f8 c8 psubb %xmm0,%xmm1 + 428a48: 66 0f d7 d1 pmovmskb %xmm1,%edx + 428a4c: 81 ea ff ff 00 00 sub $0xffff,%edx + 428a52: 0f 85 48 03 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 428a58: 48 83 c1 10 add $0x10,%rcx + 428a5c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 428a60: 49 83 c2 10 add $0x10,%r10 + 428a64: 0f 8f 96 00 00 00 jg 428b00 <__GI___strcasecmp_l+0x1f30> + 428a6a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 428a6f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 428a74: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 428a78: 66 0f 73 db 0e psrldq $0xe,%xmm3 + 428a7d: 66 0f 73 fa 02 pslldq $0x2,%xmm2 + 428a82: 66 0f eb d3 por %xmm3,%xmm2 + 428a86: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 428a8b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 428a90: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 428a95: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 428a9a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 428a9f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 428aa4: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 428aa9: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 428aae: 66 45 0f db c1 pand %xmm9,%xmm8 + 428ab3: 66 45 0f db d3 pand %xmm11,%xmm10 + 428ab8: 66 44 0f db c7 pand %xmm7,%xmm8 + 428abd: 66 44 0f db d7 pand %xmm7,%xmm10 + 428ac2: 66 41 0f eb c8 por %xmm8,%xmm1 + 428ac7: 66 41 0f eb d2 por %xmm10,%xmm2 + 428acc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 428ad0: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 428ad4: 66 0f f8 c8 psubb %xmm0,%xmm1 + 428ad8: 66 0f d7 d1 pmovmskb %xmm1,%edx + 428adc: 81 ea ff ff 00 00 sub $0xffff,%edx + 428ae2: 0f 85 b8 02 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 428ae8: 48 83 c1 10 add $0x10,%rcx + 428aec: 66 0f 6f dc movdqa %xmm4,%xmm3 + 428af0: e9 db fe ff ff jmpq 4289d0 <__GI___strcasecmp_l+0x1e00> + 428af5: 90 nop + 428af6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 428afd: 00 00 00 + 428b00: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 428b04: 66 0f d7 d0 pmovmskb %xmm0,%edx + 428b08: f7 c2 00 c0 00 00 test $0xc000,%edx + 428b0e: 75 10 jne 428b20 <__GI___strcasecmp_l+0x1f50> + 428b10: 66 0f ef c0 pxor %xmm0,%xmm0 + 428b14: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 428b1b: e9 ba fe ff ff jmpq 4289da <__GI___strcasecmp_l+0x1e0a> + 428b20: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 428b25: 66 0f 73 d8 0e psrldq $0xe,%xmm0 + 428b2a: 66 0f 73 db 0e psrldq $0xe,%xmm3 + 428b2f: e9 0c 02 00 00 jmpq 428d40 <__GI___strcasecmp_l+0x2170> + 428b34: 66 90 xchg %ax,%ax + 428b36: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 428b3d: 00 00 00 + 428b40: 66 0f ef c0 pxor %xmm0,%xmm0 + 428b44: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 428b48: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 428b4c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 428b50: 66 0f 73 fa 01 pslldq $0x1,%xmm2 + 428b55: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 428b5a: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 428b5f: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 428b64: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 428b69: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 428b6e: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 428b73: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 428b78: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 428b7d: 66 45 0f db c1 pand %xmm9,%xmm8 + 428b82: 66 45 0f db d3 pand %xmm11,%xmm10 + 428b87: 66 44 0f db c7 pand %xmm7,%xmm8 + 428b8c: 66 44 0f db d7 pand %xmm7,%xmm10 + 428b91: 66 41 0f eb c8 por %xmm8,%xmm1 + 428b96: 66 41 0f eb d2 por %xmm10,%xmm2 + 428b9b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 428b9f: 66 0f f8 d0 psubb %xmm0,%xmm2 + 428ba3: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 428ba8: d3 ea shr %cl,%edx + 428baa: 41 d3 e9 shr %cl,%r9d + 428bad: 44 29 ca sub %r9d,%edx + 428bb0: 0f 85 ef 01 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> + 428bb6: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 428bba: 66 0f ef c0 pxor %xmm0,%xmm0 + 428bbe: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 428bc5: 41 b9 0f 00 00 00 mov $0xf,%r9d + 428bcb: 4c 8d 57 0f lea 0xf(%rdi),%r10 + 428bcf: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 428bd6: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 428bdd: 0f 1f 00 nopl (%rax) + 428be0: 49 83 c2 10 add $0x10,%r10 + 428be4: 0f 8f 26 01 00 00 jg 428d10 <__GI___strcasecmp_l+0x2140> + 428bea: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 428bef: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 428bf4: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 428bf8: 66 0f 73 db 0f psrldq $0xf,%xmm3 + 428bfd: 66 0f 73 fa 01 pslldq $0x1,%xmm2 + 428c02: 66 0f eb d3 por %xmm3,%xmm2 + 428c06: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 428c0b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 428c10: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 428c15: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 428c1a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 428c1f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 428c24: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 428c29: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 428c2e: 66 45 0f db c1 pand %xmm9,%xmm8 + 428c33: 66 45 0f db d3 pand %xmm11,%xmm10 + 428c38: 66 44 0f db c7 pand %xmm7,%xmm8 + 428c3d: 66 44 0f db d7 pand %xmm7,%xmm10 + 428c42: 66 41 0f eb c8 por %xmm8,%xmm1 + 428c47: 66 41 0f eb d2 por %xmm10,%xmm2 + 428c4c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 428c50: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 428c54: 66 0f f8 c8 psubb %xmm0,%xmm1 + 428c58: 66 0f d7 d1 pmovmskb %xmm1,%edx + 428c5c: 81 ea ff ff 00 00 sub $0xffff,%edx + 428c62: 0f 85 38 01 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 428c68: 48 83 c1 10 add $0x10,%rcx + 428c6c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 428c70: 49 83 c2 10 add $0x10,%r10 + 428c74: 0f 8f 96 00 00 00 jg 428d10 <__GI___strcasecmp_l+0x2140> + 428c7a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 428c7f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 428c84: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 428c88: 66 0f 73 db 0f psrldq $0xf,%xmm3 + 428c8d: 66 0f 73 fa 01 pslldq $0x1,%xmm2 + 428c92: 66 0f eb d3 por %xmm3,%xmm2 + 428c96: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 428c9b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 428ca0: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 428ca5: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 428caa: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 428caf: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 428cb4: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 428cb9: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 428cbe: 66 45 0f db c1 pand %xmm9,%xmm8 + 428cc3: 66 45 0f db d3 pand %xmm11,%xmm10 + 428cc8: 66 44 0f db c7 pand %xmm7,%xmm8 + 428ccd: 66 44 0f db d7 pand %xmm7,%xmm10 + 428cd2: 66 41 0f eb c8 por %xmm8,%xmm1 + 428cd7: 66 41 0f eb d2 por %xmm10,%xmm2 + 428cdc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 428ce0: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 428ce4: 66 0f f8 c8 psubb %xmm0,%xmm1 + 428ce8: 66 0f d7 d1 pmovmskb %xmm1,%edx + 428cec: 81 ea ff ff 00 00 sub $0xffff,%edx + 428cf2: 0f 85 a8 00 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> + 428cf8: 48 83 c1 10 add $0x10,%rcx + 428cfc: 66 0f 6f dc movdqa %xmm4,%xmm3 + 428d00: e9 db fe ff ff jmpq 428be0 <__GI___strcasecmp_l+0x2010> + 428d05: 90 nop + 428d06: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 428d0d: 00 00 00 + 428d10: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 428d14: 66 0f d7 d0 pmovmskb %xmm0,%edx + 428d18: f7 c2 00 80 00 00 test $0x8000,%edx + 428d1e: 75 10 jne 428d30 <__GI___strcasecmp_l+0x2160> + 428d20: 66 0f ef c0 pxor %xmm0,%xmm0 + 428d24: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 428d2b: e9 ba fe ff ff jmpq 428bea <__GI___strcasecmp_l+0x201a> + 428d30: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 428d35: 66 0f 73 db 0f psrldq $0xf,%xmm3 + 428d3a: 66 0f 73 d8 0f psrldq $0xf,%xmm0 + 428d3f: 90 nop + 428d40: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 428d45: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 428d4a: 66 44 0f 6f d3 movdqa %xmm3,%xmm10 + 428d4f: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 428d54: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 428d59: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 428d5e: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 428d63: 66 44 0f 64 db pcmpgtb %xmm3,%xmm11 + 428d68: 66 45 0f db c1 pand %xmm9,%xmm8 + 428d6d: 66 45 0f db d3 pand %xmm11,%xmm10 + 428d72: 66 44 0f db c7 pand %xmm7,%xmm8 + 428d77: 66 44 0f db d7 pand %xmm7,%xmm10 + 428d7c: 66 41 0f eb c8 por %xmm8,%xmm1 + 428d81: 66 41 0f eb da por %xmm10,%xmm3 + 428d86: 66 0f 74 cb pcmpeqb %xmm3,%xmm1 + 428d8a: 66 0f f8 c8 psubb %xmm0,%xmm1 + 428d8e: 66 0f d7 d1 pmovmskb %xmm1,%edx + 428d92: f7 d2 not %edx + 428d94: 66 90 xchg %ax,%ax + 428d96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 428d9d: 00 00 00 + 428da0: 49 8d 44 09 f0 lea -0x10(%r9,%rcx,1),%rax + 428da5: 48 8d 3c 07 lea (%rdi,%rax,1),%rdi + 428da9: 48 8d 34 0e lea (%rsi,%rcx,1),%rsi + 428dad: 45 85 c0 test %r8d,%r8d + 428db0: 74 0e je 428dc0 <__GI___strcasecmp_l+0x21f0> + 428db2: 48 87 f7 xchg %rsi,%rdi + 428db5: 90 nop + 428db6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 428dbd: 00 00 00 + 428dc0: 48 0f bc d2 bsf %rdx,%rdx + 428dc4: 0f b6 0c 16 movzbl (%rsi,%rdx,1),%ecx + 428dc8: 0f b6 04 17 movzbl (%rdi,%rdx,1),%eax + 428dcc: 48 8d 15 6d e7 07 00 lea 0x7e76d(%rip),%rdx # 4a7540 <_nl_C_LC_CTYPE_tolower+0x200> + 428dd3: 8b 0c 8a mov (%rdx,%rcx,4),%ecx + 428dd6: 8b 04 82 mov (%rdx,%rax,4),%eax + 428dd9: 29 c8 sub %ecx,%eax + 428ddb: c3 retq + 428ddc: 31 c0 xor %eax,%eax + 428dde: c3 retq + 428ddf: 90 nop + 428de0: 0f b6 0e movzbl (%rsi),%ecx + 428de3: 0f b6 07 movzbl (%rdi),%eax + 428de6: 48 8d 15 53 e7 07 00 lea 0x7e753(%rip),%rdx # 4a7540 <_nl_C_LC_CTYPE_tolower+0x200> + 428ded: 8b 0c 8a mov (%rdx,%rcx,4),%ecx + 428df0: 8b 04 82 mov (%rdx,%rax,4),%eax + 428df3: 29 c8 sub %ecx,%eax + 428df5: c3 retq + 428df6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 428dfd: 00 00 00 + +0000000000428e00 <__strcasecmp_sse42>: + 428e00: 48 c7 c0 b8 ff ff ff mov $0xffffffffffffffb8,%rax + 428e07: 64 48 8b 10 mov %fs:(%rax),%rdx + 428e0b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + +0000000000428e10 <__strcasecmp_l_sse42>: + 428e10: 48 8b 02 mov (%rdx),%rax + 428e13: f7 80 78 02 00 00 01 testl $0x1,0x278(%rax) + 428e1a: 00 00 00 + 428e1d: 0f 85 dd 54 01 00 jne 43e300 <__strcasecmp_l_nonascii> + 428e23: 89 f1 mov %esi,%ecx + 428e25: 89 f8 mov %edi,%eax + 428e27: 48 83 e1 3f and $0x3f,%rcx + 428e2b: 48 83 e0 3f and $0x3f,%rax + 428e2f: 66 0f 6f 25 79 a2 07 movdqa 0x7a279(%rip),%xmm4 # 4a30b0 <__func__.10972+0xf0> + 428e36: 00 + 428e37: 66 0f 6f 2d 81 a2 07 movdqa 0x7a281(%rip),%xmm5 # 4a30c0 <__func__.10972+0x100> + 428e3e: 00 + 428e3f: 66 0f 6f 35 89 a2 07 movdqa 0x7a289(%rip),%xmm6 # 4a30d0 + 428e46: 00 + 428e47: 83 f9 30 cmp $0x30,%ecx + 428e4a: 0f 87 80 00 00 00 ja 428ed0 <__strcasecmp_l_sse42+0xc0> + 428e50: 83 f8 30 cmp $0x30,%eax + 428e53: 77 7b ja 428ed0 <__strcasecmp_l_sse42+0xc0> + 428e55: f3 0f 6f 0f movdqu (%rdi),%xmm1 + 428e59: f3 0f 6f 16 movdqu (%rsi),%xmm2 + 428e5d: 66 0f 6f f9 movdqa %xmm1,%xmm7 + 428e61: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 428e66: 66 44 0f 6f ca movdqa %xmm2,%xmm9 + 428e6b: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 428e70: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 428e74: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 + 428e79: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 428e7e: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 + 428e83: 66 41 0f db f8 pand %xmm8,%xmm7 + 428e88: 66 45 0f db ca pand %xmm10,%xmm9 + 428e8d: 66 0f db fe pand %xmm6,%xmm7 + 428e91: 66 44 0f db ce pand %xmm6,%xmm9 + 428e96: 66 0f eb cf por %xmm7,%xmm1 + 428e9a: 66 41 0f eb d1 por %xmm9,%xmm2 + 428e9f: 66 0f ef c0 pxor %xmm0,%xmm0 + 428ea3: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 428ea7: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 428eab: 66 0f f8 c8 psubb %xmm0,%xmm1 + 428eaf: 66 0f d7 d1 pmovmskb %xmm1,%edx + 428eb3: 81 ea ff ff 00 00 sub $0xffff,%edx + 428eb9: 0f 85 b1 1a 00 00 jne 42a970 <__strcasecmp_l_sse42+0x1b60> + 428ebf: 48 83 c6 10 add $0x10,%rsi + 428ec3: 48 83 c7 10 add $0x10,%rdi + 428ec7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 428ece: 00 00 + 428ed0: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi + 428ed4: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi + 428ed8: ba ff ff 00 00 mov $0xffff,%edx + 428edd: 45 31 c0 xor %r8d,%r8d + 428ee0: 83 e1 0f and $0xf,%ecx + 428ee3: 83 e0 0f and $0xf,%eax + 428ee6: 66 0f ef c0 pxor %xmm0,%xmm0 + 428eea: 39 c1 cmp %eax,%ecx + 428eec: 74 32 je 428f20 <__strcasecmp_l_sse42+0x110> + 428eee: 77 07 ja 428ef7 <__strcasecmp_l_sse42+0xe7> + 428ef0: 41 89 d0 mov %edx,%r8d + 428ef3: 91 xchg %eax,%ecx + 428ef4: 48 87 f7 xchg %rsi,%rdi + 428ef7: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 428efb: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 428eff: 4c 8d 48 0f lea 0xf(%rax),%r9 + 428f03: 49 29 c9 sub %rcx,%r9 + 428f06: 4c 8d 15 e3 a1 07 00 lea 0x7a1e3(%rip),%r10 # 4a30f0 + 428f0d: 4f 63 0c 8a movslq (%r10,%r9,4),%r9 + 428f11: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 428f15: 4f 8d 14 0a lea (%r10,%r9,1),%r10 + 428f19: 41 ff e2 jmpq *%r10 + 428f1c: 0f 1f 40 00 nopl 0x0(%rax) + 428f20: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 428f24: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 428f28: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 428f2c: 66 0f 6f f9 movdqa %xmm1,%xmm7 + 428f30: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 428f35: 66 44 0f 6f ca movdqa %xmm2,%xmm9 + 428f3a: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 428f3f: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 428f43: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 + 428f48: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 428f4d: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 + 428f52: 66 41 0f db f8 pand %xmm8,%xmm7 + 428f57: 66 45 0f db ca pand %xmm10,%xmm9 + 428f5c: 66 0f db fe pand %xmm6,%xmm7 + 428f60: 66 44 0f db ce pand %xmm6,%xmm9 + 428f65: 66 0f eb cf por %xmm7,%xmm1 + 428f69: 66 41 0f eb d1 por %xmm9,%xmm2 + 428f6e: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 428f72: 66 0f f8 c8 psubb %xmm0,%xmm1 + 428f76: 66 44 0f d7 c9 pmovmskb %xmm1,%r9d + 428f7b: d3 ea shr %cl,%edx + 428f7d: 41 d3 e9 shr %cl,%r9d + 428f80: 44 29 ca sub %r9d,%edx + 428f83: 0f 85 cf 19 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> + 428f89: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 428f90: 49 c7 c1 10 00 00 00 mov $0x10,%r9 + 428f97: 48 89 ca mov %rcx,%rdx + 428f9a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 428fa0: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 428fa5: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 428faa: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 428fae: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 428fb3: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 428fb8: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 428fbd: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 428fc1: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 428fc6: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 428fcb: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 428fd0: 66 41 0f db f8 pand %xmm8,%xmm7 + 428fd5: 66 45 0f db ca pand %xmm10,%xmm9 + 428fda: 66 0f db fe pand %xmm6,%xmm7 + 428fde: 66 44 0f db ce pand %xmm6,%xmm9 + 428fe3: 66 0f eb c7 por %xmm7,%xmm0 + 428fe7: 66 41 0f eb c9 por %xmm9,%xmm1 + 428fec: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 428ff2: 48 8d 52 10 lea 0x10(%rdx),%rdx + 428ff6: 76 68 jbe 429060 <__strcasecmp_l_sse42+0x250> + 428ff8: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 428ffd: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 429002: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 429006: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 42900b: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 429010: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 429015: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 429019: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 42901e: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 429023: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 429028: 66 41 0f db f8 pand %xmm8,%xmm7 + 42902d: 66 45 0f db ca pand %xmm10,%xmm9 + 429032: 66 0f db fe pand %xmm6,%xmm7 + 429036: 66 44 0f db ce pand %xmm6,%xmm9 + 42903b: 66 0f eb c7 por %xmm7,%xmm0 + 42903f: 66 41 0f eb c9 por %xmm9,%xmm1 + 429044: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 42904a: 48 8d 52 10 lea 0x10(%rdx),%rdx + 42904e: 76 10 jbe 429060 <__strcasecmp_l_sse42+0x250> + 429050: e9 4b ff ff ff jmpq 428fa0 <__strcasecmp_l_sse42+0x190> + 429055: 90 nop + 429056: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42905d: 00 00 00 + 429060: 0f 83 26 19 00 00 jae 42a98c <__strcasecmp_l_sse42+0x1b7c> + 429066: 48 8d 4c 0a f0 lea -0x10(%rdx,%rcx,1),%rcx + 42906b: 0f b6 04 0f movzbl (%rdi,%rcx,1),%eax + 42906f: 0f b6 14 0e movzbl (%rsi,%rcx,1),%edx + 429073: 48 8d 0d c6 e4 07 00 lea 0x7e4c6(%rip),%rcx # 4a7540 <_nl_C_LC_CTYPE_tolower+0x200> + 42907a: 8b 04 81 mov (%rcx,%rax,4),%eax + 42907d: 8b 14 91 mov (%rcx,%rdx,4),%edx + 429080: 29 d0 sub %edx,%eax + 429082: c3 retq + 429083: 0f 1f 00 nopl (%rax) + 429086: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42908d: 00 00 00 + 429090: 66 0f 73 fa 0f pslldq $0xf,%xmm2 + 429095: 66 0f 6f f9 movdqa %xmm1,%xmm7 + 429099: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 42909e: 66 44 0f 6f ca movdqa %xmm2,%xmm9 + 4290a3: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 4290a8: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 4290ac: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 + 4290b1: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 4290b6: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 + 4290bb: 66 41 0f db f8 pand %xmm8,%xmm7 + 4290c0: 66 45 0f db ca pand %xmm10,%xmm9 + 4290c5: 66 0f db fe pand %xmm6,%xmm7 + 4290c9: 66 44 0f db ce pand %xmm6,%xmm9 + 4290ce: 66 0f eb cf por %xmm7,%xmm1 + 4290d2: 66 41 0f eb d1 por %xmm9,%xmm2 + 4290d7: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 4290db: 66 0f f8 d0 psubb %xmm0,%xmm2 + 4290df: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 4290e4: d3 ea shr %cl,%edx + 4290e6: 41 d3 e9 shr %cl,%r9d + 4290e9: 44 29 ca sub %r9d,%edx + 4290ec: 0f 85 66 18 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> + 4290f2: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 4290f6: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 4290fd: 41 b9 01 00 00 00 mov $0x1,%r9d + 429103: 4c 8d 57 01 lea 0x1(%rdi),%r10 + 429107: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42910e: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 429115: 48 89 ca mov %rcx,%rdx + 429118: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 42911f: 00 + 429120: 49 83 c2 10 add $0x10,%r10 + 429124: 0f 8f d6 00 00 00 jg 429200 <__strcasecmp_l_sse42+0x3f0> + 42912a: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 42912f: 66 0f 3a 0f 44 17 f0 palignr $0x1,-0x10(%rdi,%rdx,1),%xmm0 + 429136: 01 + 429137: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 42913c: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 429140: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 429145: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 42914a: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 42914f: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 429153: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 429158: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 42915d: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 429162: 66 41 0f db f8 pand %xmm8,%xmm7 + 429167: 66 45 0f db ca pand %xmm10,%xmm9 + 42916c: 66 0f db fe pand %xmm6,%xmm7 + 429170: 66 44 0f db ce pand %xmm6,%xmm9 + 429175: 66 0f eb c7 por %xmm7,%xmm0 + 429179: 66 41 0f eb c9 por %xmm9,%xmm1 + 42917e: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 429184: 0f 86 a6 17 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> + 42918a: 48 83 c2 10 add $0x10,%rdx + 42918e: 49 83 c2 10 add $0x10,%r10 + 429192: 7f 6c jg 429200 <__strcasecmp_l_sse42+0x3f0> + 429194: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 429199: 66 0f 3a 0f 44 17 f0 palignr $0x1,-0x10(%rdi,%rdx,1),%xmm0 + 4291a0: 01 + 4291a1: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 4291a6: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 4291aa: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 4291af: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 4291b4: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 4291b9: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 4291bd: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 4291c2: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 4291c7: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 4291cc: 66 41 0f db f8 pand %xmm8,%xmm7 + 4291d1: 66 45 0f db ca pand %xmm10,%xmm9 + 4291d6: 66 0f db fe pand %xmm6,%xmm7 + 4291da: 66 44 0f db ce pand %xmm6,%xmm9 + 4291df: 66 0f eb c7 por %xmm7,%xmm0 + 4291e3: 66 41 0f eb c9 por %xmm9,%xmm1 + 4291e8: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 4291ee: 0f 86 3c 17 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> + 4291f4: 48 83 c2 10 add $0x10,%rdx + 4291f8: e9 23 ff ff ff jmpq 429120 <__strcasecmp_l_sse42+0x310> + 4291fd: 0f 1f 00 nopl (%rax) + 429200: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 429207: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 + 42920d: 66 0f 73 d8 01 psrldq $0x1,%xmm0 + 429212: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 + 429218: 83 f9 0e cmp $0xe,%ecx + 42921b: 0f 87 09 ff ff ff ja 42912a <__strcasecmp_l_sse42+0x31a> + 429221: e9 bb 16 00 00 jmpq 42a8e1 <__strcasecmp_l_sse42+0x1ad1> + 429226: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42922d: 00 00 00 + 429230: 66 0f 73 fa 0e pslldq $0xe,%xmm2 + 429235: 66 0f 6f f9 movdqa %xmm1,%xmm7 + 429239: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 42923e: 66 44 0f 6f ca movdqa %xmm2,%xmm9 + 429243: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 429248: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 42924c: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 + 429251: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 429256: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 + 42925b: 66 41 0f db f8 pand %xmm8,%xmm7 + 429260: 66 45 0f db ca pand %xmm10,%xmm9 + 429265: 66 0f db fe pand %xmm6,%xmm7 + 429269: 66 44 0f db ce pand %xmm6,%xmm9 + 42926e: 66 0f eb cf por %xmm7,%xmm1 + 429272: 66 41 0f eb d1 por %xmm9,%xmm2 + 429277: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42927b: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42927f: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 429284: d3 ea shr %cl,%edx + 429286: 41 d3 e9 shr %cl,%r9d + 429289: 44 29 ca sub %r9d,%edx + 42928c: 0f 85 c6 16 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> + 429292: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 429296: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42929d: 41 b9 02 00 00 00 mov $0x2,%r9d + 4292a3: 4c 8d 57 02 lea 0x2(%rdi),%r10 + 4292a7: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 4292ae: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 4292b5: 48 89 ca mov %rcx,%rdx + 4292b8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 4292bf: 00 + 4292c0: 49 83 c2 10 add $0x10,%r10 + 4292c4: 0f 8f d6 00 00 00 jg 4293a0 <__strcasecmp_l_sse42+0x590> + 4292ca: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 4292cf: 66 0f 3a 0f 44 17 f0 palignr $0x2,-0x10(%rdi,%rdx,1),%xmm0 + 4292d6: 02 + 4292d7: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 4292dc: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 4292e0: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 4292e5: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 4292ea: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 4292ef: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 4292f3: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 4292f8: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 4292fd: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 429302: 66 41 0f db f8 pand %xmm8,%xmm7 + 429307: 66 45 0f db ca pand %xmm10,%xmm9 + 42930c: 66 0f db fe pand %xmm6,%xmm7 + 429310: 66 44 0f db ce pand %xmm6,%xmm9 + 429315: 66 0f eb c7 por %xmm7,%xmm0 + 429319: 66 41 0f eb c9 por %xmm9,%xmm1 + 42931e: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 429324: 0f 86 06 16 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> + 42932a: 48 83 c2 10 add $0x10,%rdx + 42932e: 49 83 c2 10 add $0x10,%r10 + 429332: 7f 6c jg 4293a0 <__strcasecmp_l_sse42+0x590> + 429334: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 429339: 66 0f 3a 0f 44 17 f0 palignr $0x2,-0x10(%rdi,%rdx,1),%xmm0 + 429340: 02 + 429341: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 429346: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 42934a: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 42934f: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 429354: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 429359: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 42935d: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 429362: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 429367: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 42936c: 66 41 0f db f8 pand %xmm8,%xmm7 + 429371: 66 45 0f db ca pand %xmm10,%xmm9 + 429376: 66 0f db fe pand %xmm6,%xmm7 + 42937a: 66 44 0f db ce pand %xmm6,%xmm9 + 42937f: 66 0f eb c7 por %xmm7,%xmm0 + 429383: 66 41 0f eb c9 por %xmm9,%xmm1 + 429388: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 42938e: 0f 86 9c 15 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> + 429394: 48 83 c2 10 add $0x10,%rdx + 429398: e9 23 ff ff ff jmpq 4292c0 <__strcasecmp_l_sse42+0x4b0> + 42939d: 0f 1f 00 nopl (%rax) + 4293a0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 4293a7: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 + 4293ad: 66 0f 73 d8 02 psrldq $0x2,%xmm0 + 4293b2: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 + 4293b8: 83 f9 0d cmp $0xd,%ecx + 4293bb: 0f 87 09 ff ff ff ja 4292ca <__strcasecmp_l_sse42+0x4ba> + 4293c1: e9 1b 15 00 00 jmpq 42a8e1 <__strcasecmp_l_sse42+0x1ad1> + 4293c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4293cd: 00 00 00 + 4293d0: 66 0f 73 fa 0d pslldq $0xd,%xmm2 + 4293d5: 66 0f 6f f9 movdqa %xmm1,%xmm7 + 4293d9: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 4293de: 66 44 0f 6f ca movdqa %xmm2,%xmm9 + 4293e3: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 4293e8: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 4293ec: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 + 4293f1: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 4293f6: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 + 4293fb: 66 41 0f db f8 pand %xmm8,%xmm7 + 429400: 66 45 0f db ca pand %xmm10,%xmm9 + 429405: 66 0f db fe pand %xmm6,%xmm7 + 429409: 66 44 0f db ce pand %xmm6,%xmm9 + 42940e: 66 0f eb cf por %xmm7,%xmm1 + 429412: 66 41 0f eb d1 por %xmm9,%xmm2 + 429417: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42941b: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42941f: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 429424: d3 ea shr %cl,%edx + 429426: 41 d3 e9 shr %cl,%r9d + 429429: 44 29 ca sub %r9d,%edx + 42942c: 0f 85 26 15 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> + 429432: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 429436: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42943d: 41 b9 03 00 00 00 mov $0x3,%r9d + 429443: 4c 8d 57 03 lea 0x3(%rdi),%r10 + 429447: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42944e: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 429455: 48 89 ca mov %rcx,%rdx + 429458: 49 83 c2 10 add $0x10,%r10 + 42945c: 0f 8f de 00 00 00 jg 429540 <__strcasecmp_l_sse42+0x730> + 429462: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 429467: 66 0f 3a 0f 44 17 f0 palignr $0x3,-0x10(%rdi,%rdx,1),%xmm0 + 42946e: 03 + 42946f: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 429474: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 429478: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 42947d: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 429482: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 429487: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 42948b: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 429490: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 429495: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 42949a: 66 41 0f db f8 pand %xmm8,%xmm7 + 42949f: 66 45 0f db ca pand %xmm10,%xmm9 + 4294a4: 66 0f db fe pand %xmm6,%xmm7 + 4294a8: 66 44 0f db ce pand %xmm6,%xmm9 + 4294ad: 66 0f eb c7 por %xmm7,%xmm0 + 4294b1: 66 41 0f eb c9 por %xmm9,%xmm1 + 4294b6: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 4294bc: 0f 86 6e 14 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> + 4294c2: 48 83 c2 10 add $0x10,%rdx + 4294c6: 49 83 c2 10 add $0x10,%r10 + 4294ca: 7f 74 jg 429540 <__strcasecmp_l_sse42+0x730> + 4294cc: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 4294d1: 66 0f 3a 0f 44 17 f0 palignr $0x3,-0x10(%rdi,%rdx,1),%xmm0 + 4294d8: 03 + 4294d9: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 4294de: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 4294e2: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 4294e7: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 4294ec: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 4294f1: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 4294f5: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 4294fa: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 4294ff: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 429504: 66 41 0f db f8 pand %xmm8,%xmm7 + 429509: 66 45 0f db ca pand %xmm10,%xmm9 + 42950e: 66 0f db fe pand %xmm6,%xmm7 + 429512: 66 44 0f db ce pand %xmm6,%xmm9 + 429517: 66 0f eb c7 por %xmm7,%xmm0 + 42951b: 66 41 0f eb c9 por %xmm9,%xmm1 + 429520: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 429526: 0f 86 04 14 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> + 42952c: 48 83 c2 10 add $0x10,%rdx + 429530: e9 23 ff ff ff jmpq 429458 <__strcasecmp_l_sse42+0x648> + 429535: 90 nop + 429536: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42953d: 00 00 00 + 429540: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 429547: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 + 42954d: 66 0f 73 d8 03 psrldq $0x3,%xmm0 + 429552: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 + 429558: 83 f9 0c cmp $0xc,%ecx + 42955b: 0f 87 01 ff ff ff ja 429462 <__strcasecmp_l_sse42+0x652> + 429561: e9 7b 13 00 00 jmpq 42a8e1 <__strcasecmp_l_sse42+0x1ad1> + 429566: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42956d: 00 00 00 + 429570: 66 0f 73 fa 0c pslldq $0xc,%xmm2 + 429575: 66 0f 6f f9 movdqa %xmm1,%xmm7 + 429579: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 42957e: 66 44 0f 6f ca movdqa %xmm2,%xmm9 + 429583: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 429588: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 42958c: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 + 429591: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 429596: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 + 42959b: 66 41 0f db f8 pand %xmm8,%xmm7 + 4295a0: 66 45 0f db ca pand %xmm10,%xmm9 + 4295a5: 66 0f db fe pand %xmm6,%xmm7 + 4295a9: 66 44 0f db ce pand %xmm6,%xmm9 + 4295ae: 66 0f eb cf por %xmm7,%xmm1 + 4295b2: 66 41 0f eb d1 por %xmm9,%xmm2 + 4295b7: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 4295bb: 66 0f f8 d0 psubb %xmm0,%xmm2 + 4295bf: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 4295c4: d3 ea shr %cl,%edx + 4295c6: 41 d3 e9 shr %cl,%r9d + 4295c9: 44 29 ca sub %r9d,%edx + 4295cc: 0f 85 86 13 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> + 4295d2: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 4295d6: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 4295dd: 41 b9 04 00 00 00 mov $0x4,%r9d + 4295e3: 4c 8d 57 04 lea 0x4(%rdi),%r10 + 4295e7: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 4295ee: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 4295f5: 48 89 ca mov %rcx,%rdx + 4295f8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 4295ff: 00 + 429600: 49 83 c2 10 add $0x10,%r10 + 429604: 0f 8f d6 00 00 00 jg 4296e0 <__strcasecmp_l_sse42+0x8d0> + 42960a: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 42960f: 66 0f 3a 0f 44 17 f0 palignr $0x4,-0x10(%rdi,%rdx,1),%xmm0 + 429616: 04 + 429617: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 42961c: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 429620: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 429625: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 42962a: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 42962f: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 429633: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 429638: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 42963d: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 429642: 66 41 0f db f8 pand %xmm8,%xmm7 + 429647: 66 45 0f db ca pand %xmm10,%xmm9 + 42964c: 66 0f db fe pand %xmm6,%xmm7 + 429650: 66 44 0f db ce pand %xmm6,%xmm9 + 429655: 66 0f eb c7 por %xmm7,%xmm0 + 429659: 66 41 0f eb c9 por %xmm9,%xmm1 + 42965e: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 429664: 0f 86 c6 12 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> + 42966a: 48 83 c2 10 add $0x10,%rdx + 42966e: 49 83 c2 10 add $0x10,%r10 + 429672: 7f 6c jg 4296e0 <__strcasecmp_l_sse42+0x8d0> + 429674: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 429679: 66 0f 3a 0f 44 17 f0 palignr $0x4,-0x10(%rdi,%rdx,1),%xmm0 + 429680: 04 + 429681: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 429686: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 42968a: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 42968f: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 429694: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 429699: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 42969d: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 4296a2: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 4296a7: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 4296ac: 66 41 0f db f8 pand %xmm8,%xmm7 + 4296b1: 66 45 0f db ca pand %xmm10,%xmm9 + 4296b6: 66 0f db fe pand %xmm6,%xmm7 + 4296ba: 66 44 0f db ce pand %xmm6,%xmm9 + 4296bf: 66 0f eb c7 por %xmm7,%xmm0 + 4296c3: 66 41 0f eb c9 por %xmm9,%xmm1 + 4296c8: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 4296ce: 0f 86 5c 12 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> + 4296d4: 48 83 c2 10 add $0x10,%rdx + 4296d8: e9 23 ff ff ff jmpq 429600 <__strcasecmp_l_sse42+0x7f0> + 4296dd: 0f 1f 00 nopl (%rax) + 4296e0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 4296e7: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 + 4296ed: 66 0f 73 d8 04 psrldq $0x4,%xmm0 + 4296f2: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 + 4296f8: 83 f9 0b cmp $0xb,%ecx + 4296fb: 0f 87 09 ff ff ff ja 42960a <__strcasecmp_l_sse42+0x7fa> + 429701: e9 db 11 00 00 jmpq 42a8e1 <__strcasecmp_l_sse42+0x1ad1> + 429706: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42970d: 00 00 00 + 429710: 66 0f 73 fa 0b pslldq $0xb,%xmm2 + 429715: 66 0f 6f f9 movdqa %xmm1,%xmm7 + 429719: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 42971e: 66 44 0f 6f ca movdqa %xmm2,%xmm9 + 429723: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 429728: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 42972c: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 + 429731: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 429736: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 + 42973b: 66 41 0f db f8 pand %xmm8,%xmm7 + 429740: 66 45 0f db ca pand %xmm10,%xmm9 + 429745: 66 0f db fe pand %xmm6,%xmm7 + 429749: 66 44 0f db ce pand %xmm6,%xmm9 + 42974e: 66 0f eb cf por %xmm7,%xmm1 + 429752: 66 41 0f eb d1 por %xmm9,%xmm2 + 429757: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42975b: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42975f: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 429764: d3 ea shr %cl,%edx + 429766: 41 d3 e9 shr %cl,%r9d + 429769: 44 29 ca sub %r9d,%edx + 42976c: 0f 85 e6 11 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> + 429772: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 429776: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42977d: 41 b9 05 00 00 00 mov $0x5,%r9d + 429783: 4c 8d 57 05 lea 0x5(%rdi),%r10 + 429787: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42978e: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 429795: 48 89 ca mov %rcx,%rdx + 429798: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 42979f: 00 + 4297a0: 49 83 c2 10 add $0x10,%r10 + 4297a4: 0f 8f d6 00 00 00 jg 429880 <__strcasecmp_l_sse42+0xa70> + 4297aa: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 4297af: 66 0f 3a 0f 44 17 f0 palignr $0x5,-0x10(%rdi,%rdx,1),%xmm0 + 4297b6: 05 + 4297b7: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 4297bc: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 4297c0: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 4297c5: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 4297ca: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 4297cf: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 4297d3: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 4297d8: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 4297dd: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 4297e2: 66 41 0f db f8 pand %xmm8,%xmm7 + 4297e7: 66 45 0f db ca pand %xmm10,%xmm9 + 4297ec: 66 0f db fe pand %xmm6,%xmm7 + 4297f0: 66 44 0f db ce pand %xmm6,%xmm9 + 4297f5: 66 0f eb c7 por %xmm7,%xmm0 + 4297f9: 66 41 0f eb c9 por %xmm9,%xmm1 + 4297fe: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 429804: 0f 86 26 11 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> + 42980a: 48 83 c2 10 add $0x10,%rdx + 42980e: 49 83 c2 10 add $0x10,%r10 + 429812: 7f 6c jg 429880 <__strcasecmp_l_sse42+0xa70> + 429814: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 429819: 66 0f 3a 0f 44 17 f0 palignr $0x5,-0x10(%rdi,%rdx,1),%xmm0 + 429820: 05 + 429821: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 429826: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 42982a: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 42982f: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 429834: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 429839: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 42983d: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 429842: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 429847: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 42984c: 66 41 0f db f8 pand %xmm8,%xmm7 + 429851: 66 45 0f db ca pand %xmm10,%xmm9 + 429856: 66 0f db fe pand %xmm6,%xmm7 + 42985a: 66 44 0f db ce pand %xmm6,%xmm9 + 42985f: 66 0f eb c7 por %xmm7,%xmm0 + 429863: 66 41 0f eb c9 por %xmm9,%xmm1 + 429868: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 42986e: 0f 86 bc 10 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> + 429874: 48 83 c2 10 add $0x10,%rdx + 429878: e9 23 ff ff ff jmpq 4297a0 <__strcasecmp_l_sse42+0x990> + 42987d: 0f 1f 00 nopl (%rax) + 429880: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 429887: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 + 42988d: 66 0f 73 d8 05 psrldq $0x5,%xmm0 + 429892: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 + 429898: 83 f9 0a cmp $0xa,%ecx + 42989b: 0f 87 09 ff ff ff ja 4297aa <__strcasecmp_l_sse42+0x99a> + 4298a1: e9 3b 10 00 00 jmpq 42a8e1 <__strcasecmp_l_sse42+0x1ad1> + 4298a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4298ad: 00 00 00 + 4298b0: 66 0f 73 fa 0a pslldq $0xa,%xmm2 + 4298b5: 66 0f 6f f9 movdqa %xmm1,%xmm7 + 4298b9: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 4298be: 66 44 0f 6f ca movdqa %xmm2,%xmm9 + 4298c3: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 4298c8: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 4298cc: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 + 4298d1: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 4298d6: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 + 4298db: 66 41 0f db f8 pand %xmm8,%xmm7 + 4298e0: 66 45 0f db ca pand %xmm10,%xmm9 + 4298e5: 66 0f db fe pand %xmm6,%xmm7 + 4298e9: 66 44 0f db ce pand %xmm6,%xmm9 + 4298ee: 66 0f eb cf por %xmm7,%xmm1 + 4298f2: 66 41 0f eb d1 por %xmm9,%xmm2 + 4298f7: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 4298fb: 66 0f f8 d0 psubb %xmm0,%xmm2 + 4298ff: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 429904: d3 ea shr %cl,%edx + 429906: 41 d3 e9 shr %cl,%r9d + 429909: 44 29 ca sub %r9d,%edx + 42990c: 0f 85 46 10 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> + 429912: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 429916: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42991d: 41 b9 06 00 00 00 mov $0x6,%r9d + 429923: 4c 8d 57 06 lea 0x6(%rdi),%r10 + 429927: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42992e: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 429935: 48 89 ca mov %rcx,%rdx + 429938: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 42993f: 00 + 429940: 49 83 c2 10 add $0x10,%r10 + 429944: 0f 8f d6 00 00 00 jg 429a20 <__strcasecmp_l_sse42+0xc10> + 42994a: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 42994f: 66 0f 3a 0f 44 17 f0 palignr $0x6,-0x10(%rdi,%rdx,1),%xmm0 + 429956: 06 + 429957: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 42995c: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 429960: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 429965: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 42996a: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 42996f: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 429973: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 429978: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 42997d: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 429982: 66 41 0f db f8 pand %xmm8,%xmm7 + 429987: 66 45 0f db ca pand %xmm10,%xmm9 + 42998c: 66 0f db fe pand %xmm6,%xmm7 + 429990: 66 44 0f db ce pand %xmm6,%xmm9 + 429995: 66 0f eb c7 por %xmm7,%xmm0 + 429999: 66 41 0f eb c9 por %xmm9,%xmm1 + 42999e: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 4299a4: 0f 86 86 0f 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> + 4299aa: 48 83 c2 10 add $0x10,%rdx + 4299ae: 49 83 c2 10 add $0x10,%r10 + 4299b2: 7f 6c jg 429a20 <__strcasecmp_l_sse42+0xc10> + 4299b4: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 4299b9: 66 0f 3a 0f 44 17 f0 palignr $0x6,-0x10(%rdi,%rdx,1),%xmm0 + 4299c0: 06 + 4299c1: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 4299c6: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 4299ca: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 4299cf: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 4299d4: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 4299d9: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 4299dd: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 4299e2: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 4299e7: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 4299ec: 66 41 0f db f8 pand %xmm8,%xmm7 + 4299f1: 66 45 0f db ca pand %xmm10,%xmm9 + 4299f6: 66 0f db fe pand %xmm6,%xmm7 + 4299fa: 66 44 0f db ce pand %xmm6,%xmm9 + 4299ff: 66 0f eb c7 por %xmm7,%xmm0 + 429a03: 66 41 0f eb c9 por %xmm9,%xmm1 + 429a08: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 429a0e: 0f 86 1c 0f 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> + 429a14: 48 83 c2 10 add $0x10,%rdx + 429a18: e9 23 ff ff ff jmpq 429940 <__strcasecmp_l_sse42+0xb30> + 429a1d: 0f 1f 00 nopl (%rax) + 429a20: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 429a27: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 + 429a2d: 66 0f 73 d8 06 psrldq $0x6,%xmm0 + 429a32: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 + 429a38: 83 f9 09 cmp $0x9,%ecx + 429a3b: 0f 87 09 ff ff ff ja 42994a <__strcasecmp_l_sse42+0xb3a> + 429a41: e9 9b 0e 00 00 jmpq 42a8e1 <__strcasecmp_l_sse42+0x1ad1> + 429a46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 429a4d: 00 00 00 + 429a50: 66 0f 73 fa 09 pslldq $0x9,%xmm2 + 429a55: 66 0f 6f f9 movdqa %xmm1,%xmm7 + 429a59: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 429a5e: 66 44 0f 6f ca movdqa %xmm2,%xmm9 + 429a63: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 429a68: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 429a6c: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 + 429a71: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 429a76: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 + 429a7b: 66 41 0f db f8 pand %xmm8,%xmm7 + 429a80: 66 45 0f db ca pand %xmm10,%xmm9 + 429a85: 66 0f db fe pand %xmm6,%xmm7 + 429a89: 66 44 0f db ce pand %xmm6,%xmm9 + 429a8e: 66 0f eb cf por %xmm7,%xmm1 + 429a92: 66 41 0f eb d1 por %xmm9,%xmm2 + 429a97: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 429a9b: 66 0f f8 d0 psubb %xmm0,%xmm2 + 429a9f: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 429aa4: d3 ea shr %cl,%edx + 429aa6: 41 d3 e9 shr %cl,%r9d + 429aa9: 44 29 ca sub %r9d,%edx + 429aac: 0f 85 a6 0e 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> + 429ab2: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 429ab6: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 429abd: 41 b9 07 00 00 00 mov $0x7,%r9d + 429ac3: 4c 8d 57 07 lea 0x7(%rdi),%r10 + 429ac7: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 429ace: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 429ad5: 48 89 ca mov %rcx,%rdx + 429ad8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 429adf: 00 + 429ae0: 49 83 c2 10 add $0x10,%r10 + 429ae4: 0f 8f d6 00 00 00 jg 429bc0 <__strcasecmp_l_sse42+0xdb0> + 429aea: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 429aef: 66 0f 3a 0f 44 17 f0 palignr $0x7,-0x10(%rdi,%rdx,1),%xmm0 + 429af6: 07 + 429af7: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 429afc: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 429b00: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 429b05: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 429b0a: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 429b0f: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 429b13: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 429b18: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 429b1d: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 429b22: 66 41 0f db f8 pand %xmm8,%xmm7 + 429b27: 66 45 0f db ca pand %xmm10,%xmm9 + 429b2c: 66 0f db fe pand %xmm6,%xmm7 + 429b30: 66 44 0f db ce pand %xmm6,%xmm9 + 429b35: 66 0f eb c7 por %xmm7,%xmm0 + 429b39: 66 41 0f eb c9 por %xmm9,%xmm1 + 429b3e: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 429b44: 0f 86 e6 0d 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> + 429b4a: 48 83 c2 10 add $0x10,%rdx + 429b4e: 49 83 c2 10 add $0x10,%r10 + 429b52: 7f 6c jg 429bc0 <__strcasecmp_l_sse42+0xdb0> + 429b54: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 429b59: 66 0f 3a 0f 44 17 f0 palignr $0x7,-0x10(%rdi,%rdx,1),%xmm0 + 429b60: 07 + 429b61: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 429b66: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 429b6a: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 429b6f: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 429b74: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 429b79: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 429b7d: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 429b82: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 429b87: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 429b8c: 66 41 0f db f8 pand %xmm8,%xmm7 + 429b91: 66 45 0f db ca pand %xmm10,%xmm9 + 429b96: 66 0f db fe pand %xmm6,%xmm7 + 429b9a: 66 44 0f db ce pand %xmm6,%xmm9 + 429b9f: 66 0f eb c7 por %xmm7,%xmm0 + 429ba3: 66 41 0f eb c9 por %xmm9,%xmm1 + 429ba8: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 429bae: 0f 86 7c 0d 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> + 429bb4: 48 83 c2 10 add $0x10,%rdx + 429bb8: e9 23 ff ff ff jmpq 429ae0 <__strcasecmp_l_sse42+0xcd0> + 429bbd: 0f 1f 00 nopl (%rax) + 429bc0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 429bc7: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 + 429bcd: 66 0f 73 d8 07 psrldq $0x7,%xmm0 + 429bd2: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 + 429bd8: 83 f9 08 cmp $0x8,%ecx + 429bdb: 0f 87 09 ff ff ff ja 429aea <__strcasecmp_l_sse42+0xcda> + 429be1: e9 fb 0c 00 00 jmpq 42a8e1 <__strcasecmp_l_sse42+0x1ad1> + 429be6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 429bed: 00 00 00 + 429bf0: 66 0f 73 fa 08 pslldq $0x8,%xmm2 + 429bf5: 66 0f 6f f9 movdqa %xmm1,%xmm7 + 429bf9: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 429bfe: 66 44 0f 6f ca movdqa %xmm2,%xmm9 + 429c03: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 429c08: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 429c0c: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 + 429c11: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 429c16: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 + 429c1b: 66 41 0f db f8 pand %xmm8,%xmm7 + 429c20: 66 45 0f db ca pand %xmm10,%xmm9 + 429c25: 66 0f db fe pand %xmm6,%xmm7 + 429c29: 66 44 0f db ce pand %xmm6,%xmm9 + 429c2e: 66 0f eb cf por %xmm7,%xmm1 + 429c32: 66 41 0f eb d1 por %xmm9,%xmm2 + 429c37: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 429c3b: 66 0f f8 d0 psubb %xmm0,%xmm2 + 429c3f: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 429c44: d3 ea shr %cl,%edx + 429c46: 41 d3 e9 shr %cl,%r9d + 429c49: 44 29 ca sub %r9d,%edx + 429c4c: 0f 85 06 0d 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> + 429c52: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 429c56: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 429c5d: 41 b9 08 00 00 00 mov $0x8,%r9d + 429c63: 4c 8d 57 08 lea 0x8(%rdi),%r10 + 429c67: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 429c6e: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 429c75: 48 89 ca mov %rcx,%rdx + 429c78: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 429c7f: 00 + 429c80: 49 83 c2 10 add $0x10,%r10 + 429c84: 0f 8f d6 00 00 00 jg 429d60 <__strcasecmp_l_sse42+0xf50> + 429c8a: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 429c8f: 66 0f 3a 0f 44 17 f0 palignr $0x8,-0x10(%rdi,%rdx,1),%xmm0 + 429c96: 08 + 429c97: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 429c9c: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 429ca0: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 429ca5: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 429caa: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 429caf: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 429cb3: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 429cb8: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 429cbd: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 429cc2: 66 41 0f db f8 pand %xmm8,%xmm7 + 429cc7: 66 45 0f db ca pand %xmm10,%xmm9 + 429ccc: 66 0f db fe pand %xmm6,%xmm7 + 429cd0: 66 44 0f db ce pand %xmm6,%xmm9 + 429cd5: 66 0f eb c7 por %xmm7,%xmm0 + 429cd9: 66 41 0f eb c9 por %xmm9,%xmm1 + 429cde: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 429ce4: 0f 86 46 0c 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> + 429cea: 48 83 c2 10 add $0x10,%rdx + 429cee: 49 83 c2 10 add $0x10,%r10 + 429cf2: 7f 6c jg 429d60 <__strcasecmp_l_sse42+0xf50> + 429cf4: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 429cf9: 66 0f 3a 0f 44 17 f0 palignr $0x8,-0x10(%rdi,%rdx,1),%xmm0 + 429d00: 08 + 429d01: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 429d06: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 429d0a: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 429d0f: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 429d14: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 429d19: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 429d1d: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 429d22: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 429d27: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 429d2c: 66 41 0f db f8 pand %xmm8,%xmm7 + 429d31: 66 45 0f db ca pand %xmm10,%xmm9 + 429d36: 66 0f db fe pand %xmm6,%xmm7 + 429d3a: 66 44 0f db ce pand %xmm6,%xmm9 + 429d3f: 66 0f eb c7 por %xmm7,%xmm0 + 429d43: 66 41 0f eb c9 por %xmm9,%xmm1 + 429d48: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 429d4e: 0f 86 dc 0b 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> + 429d54: 48 83 c2 10 add $0x10,%rdx + 429d58: e9 23 ff ff ff jmpq 429c80 <__strcasecmp_l_sse42+0xe70> + 429d5d: 0f 1f 00 nopl (%rax) + 429d60: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 429d67: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 + 429d6d: 66 0f 73 d8 08 psrldq $0x8,%xmm0 + 429d72: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 + 429d78: 83 f9 07 cmp $0x7,%ecx + 429d7b: 0f 87 09 ff ff ff ja 429c8a <__strcasecmp_l_sse42+0xe7a> + 429d81: e9 5b 0b 00 00 jmpq 42a8e1 <__strcasecmp_l_sse42+0x1ad1> + 429d86: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 429d8d: 00 00 00 + 429d90: 66 0f 73 fa 07 pslldq $0x7,%xmm2 + 429d95: 66 0f 6f f9 movdqa %xmm1,%xmm7 + 429d99: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 429d9e: 66 44 0f 6f ca movdqa %xmm2,%xmm9 + 429da3: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 429da8: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 429dac: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 + 429db1: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 429db6: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 + 429dbb: 66 41 0f db f8 pand %xmm8,%xmm7 + 429dc0: 66 45 0f db ca pand %xmm10,%xmm9 + 429dc5: 66 0f db fe pand %xmm6,%xmm7 + 429dc9: 66 44 0f db ce pand %xmm6,%xmm9 + 429dce: 66 0f eb cf por %xmm7,%xmm1 + 429dd2: 66 41 0f eb d1 por %xmm9,%xmm2 + 429dd7: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 429ddb: 66 0f f8 d0 psubb %xmm0,%xmm2 + 429ddf: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 429de4: d3 ea shr %cl,%edx + 429de6: 41 d3 e9 shr %cl,%r9d + 429de9: 44 29 ca sub %r9d,%edx + 429dec: 0f 85 66 0b 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> + 429df2: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 429df6: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 429dfd: 41 b9 09 00 00 00 mov $0x9,%r9d + 429e03: 4c 8d 57 09 lea 0x9(%rdi),%r10 + 429e07: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 429e0e: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 429e15: 48 89 ca mov %rcx,%rdx + 429e18: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 429e1f: 00 + 429e20: 49 83 c2 10 add $0x10,%r10 + 429e24: 0f 8f d6 00 00 00 jg 429f00 <__strcasecmp_l_sse42+0x10f0> + 429e2a: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 429e2f: 66 0f 3a 0f 44 17 f0 palignr $0x9,-0x10(%rdi,%rdx,1),%xmm0 + 429e36: 09 + 429e37: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 429e3c: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 429e40: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 429e45: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 429e4a: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 429e4f: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 429e53: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 429e58: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 429e5d: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 429e62: 66 41 0f db f8 pand %xmm8,%xmm7 + 429e67: 66 45 0f db ca pand %xmm10,%xmm9 + 429e6c: 66 0f db fe pand %xmm6,%xmm7 + 429e70: 66 44 0f db ce pand %xmm6,%xmm9 + 429e75: 66 0f eb c7 por %xmm7,%xmm0 + 429e79: 66 41 0f eb c9 por %xmm9,%xmm1 + 429e7e: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 429e84: 0f 86 a6 0a 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> + 429e8a: 48 83 c2 10 add $0x10,%rdx + 429e8e: 49 83 c2 10 add $0x10,%r10 + 429e92: 7f 6c jg 429f00 <__strcasecmp_l_sse42+0x10f0> + 429e94: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 429e99: 66 0f 3a 0f 44 17 f0 palignr $0x9,-0x10(%rdi,%rdx,1),%xmm0 + 429ea0: 09 + 429ea1: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 429ea6: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 429eaa: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 429eaf: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 429eb4: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 429eb9: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 429ebd: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 429ec2: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 429ec7: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 429ecc: 66 41 0f db f8 pand %xmm8,%xmm7 + 429ed1: 66 45 0f db ca pand %xmm10,%xmm9 + 429ed6: 66 0f db fe pand %xmm6,%xmm7 + 429eda: 66 44 0f db ce pand %xmm6,%xmm9 + 429edf: 66 0f eb c7 por %xmm7,%xmm0 + 429ee3: 66 41 0f eb c9 por %xmm9,%xmm1 + 429ee8: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 429eee: 0f 86 3c 0a 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> + 429ef4: 48 83 c2 10 add $0x10,%rdx + 429ef8: e9 23 ff ff ff jmpq 429e20 <__strcasecmp_l_sse42+0x1010> + 429efd: 0f 1f 00 nopl (%rax) + 429f00: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 429f07: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 + 429f0d: 66 0f 73 d8 09 psrldq $0x9,%xmm0 + 429f12: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 + 429f18: 83 f9 06 cmp $0x6,%ecx + 429f1b: 0f 87 09 ff ff ff ja 429e2a <__strcasecmp_l_sse42+0x101a> + 429f21: e9 bb 09 00 00 jmpq 42a8e1 <__strcasecmp_l_sse42+0x1ad1> + 429f26: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 429f2d: 00 00 00 + 429f30: 66 0f 73 fa 06 pslldq $0x6,%xmm2 + 429f35: 66 0f 6f f9 movdqa %xmm1,%xmm7 + 429f39: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 429f3e: 66 44 0f 6f ca movdqa %xmm2,%xmm9 + 429f43: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 429f48: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 429f4c: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 + 429f51: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 429f56: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 + 429f5b: 66 41 0f db f8 pand %xmm8,%xmm7 + 429f60: 66 45 0f db ca pand %xmm10,%xmm9 + 429f65: 66 0f db fe pand %xmm6,%xmm7 + 429f69: 66 44 0f db ce pand %xmm6,%xmm9 + 429f6e: 66 0f eb cf por %xmm7,%xmm1 + 429f72: 66 41 0f eb d1 por %xmm9,%xmm2 + 429f77: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 429f7b: 66 0f f8 d0 psubb %xmm0,%xmm2 + 429f7f: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 429f84: d3 ea shr %cl,%edx + 429f86: 41 d3 e9 shr %cl,%r9d + 429f89: 44 29 ca sub %r9d,%edx + 429f8c: 0f 85 c6 09 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> + 429f92: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 429f96: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 429f9d: 41 b9 0a 00 00 00 mov $0xa,%r9d + 429fa3: 4c 8d 57 0a lea 0xa(%rdi),%r10 + 429fa7: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 429fae: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 429fb5: 48 89 ca mov %rcx,%rdx + 429fb8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 429fbf: 00 + 429fc0: 49 83 c2 10 add $0x10,%r10 + 429fc4: 0f 8f d6 00 00 00 jg 42a0a0 <__strcasecmp_l_sse42+0x1290> + 429fca: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 429fcf: 66 0f 3a 0f 44 17 f0 palignr $0xa,-0x10(%rdi,%rdx,1),%xmm0 + 429fd6: 0a + 429fd7: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 429fdc: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 429fe0: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 429fe5: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 429fea: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 429fef: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 429ff3: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 429ff8: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 429ffd: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 42a002: 66 41 0f db f8 pand %xmm8,%xmm7 + 42a007: 66 45 0f db ca pand %xmm10,%xmm9 + 42a00c: 66 0f db fe pand %xmm6,%xmm7 + 42a010: 66 44 0f db ce pand %xmm6,%xmm9 + 42a015: 66 0f eb c7 por %xmm7,%xmm0 + 42a019: 66 41 0f eb c9 por %xmm9,%xmm1 + 42a01e: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 42a024: 0f 86 06 09 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> + 42a02a: 48 83 c2 10 add $0x10,%rdx + 42a02e: 49 83 c2 10 add $0x10,%r10 + 42a032: 7f 6c jg 42a0a0 <__strcasecmp_l_sse42+0x1290> + 42a034: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 42a039: 66 0f 3a 0f 44 17 f0 palignr $0xa,-0x10(%rdi,%rdx,1),%xmm0 + 42a040: 0a + 42a041: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 42a046: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 42a04a: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 42a04f: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 42a054: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 42a059: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 42a05d: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 42a062: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 42a067: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 42a06c: 66 41 0f db f8 pand %xmm8,%xmm7 + 42a071: 66 45 0f db ca pand %xmm10,%xmm9 + 42a076: 66 0f db fe pand %xmm6,%xmm7 + 42a07a: 66 44 0f db ce pand %xmm6,%xmm9 + 42a07f: 66 0f eb c7 por %xmm7,%xmm0 + 42a083: 66 41 0f eb c9 por %xmm9,%xmm1 + 42a088: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 42a08e: 0f 86 9c 08 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> + 42a094: 48 83 c2 10 add $0x10,%rdx + 42a098: e9 23 ff ff ff jmpq 429fc0 <__strcasecmp_l_sse42+0x11b0> + 42a09d: 0f 1f 00 nopl (%rax) + 42a0a0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42a0a7: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 + 42a0ad: 66 0f 73 d8 0a psrldq $0xa,%xmm0 + 42a0b2: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 + 42a0b8: 83 f9 05 cmp $0x5,%ecx + 42a0bb: 0f 87 09 ff ff ff ja 429fca <__strcasecmp_l_sse42+0x11ba> + 42a0c1: e9 1b 08 00 00 jmpq 42a8e1 <__strcasecmp_l_sse42+0x1ad1> + 42a0c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42a0cd: 00 00 00 + 42a0d0: 66 0f 73 fa 05 pslldq $0x5,%xmm2 + 42a0d5: 66 0f 6f f9 movdqa %xmm1,%xmm7 + 42a0d9: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 42a0de: 66 44 0f 6f ca movdqa %xmm2,%xmm9 + 42a0e3: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 42a0e8: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 42a0ec: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 + 42a0f1: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 42a0f6: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 + 42a0fb: 66 41 0f db f8 pand %xmm8,%xmm7 + 42a100: 66 45 0f db ca pand %xmm10,%xmm9 + 42a105: 66 0f db fe pand %xmm6,%xmm7 + 42a109: 66 44 0f db ce pand %xmm6,%xmm9 + 42a10e: 66 0f eb cf por %xmm7,%xmm1 + 42a112: 66 41 0f eb d1 por %xmm9,%xmm2 + 42a117: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42a11b: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42a11f: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 42a124: d3 ea shr %cl,%edx + 42a126: 41 d3 e9 shr %cl,%r9d + 42a129: 44 29 ca sub %r9d,%edx + 42a12c: 0f 85 26 08 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> + 42a132: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 42a136: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42a13d: 41 b9 0b 00 00 00 mov $0xb,%r9d + 42a143: 4c 8d 57 0b lea 0xb(%rdi),%r10 + 42a147: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42a14e: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42a155: 48 89 ca mov %rcx,%rdx + 42a158: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 42a15f: 00 + 42a160: 49 83 c2 10 add $0x10,%r10 + 42a164: 0f 8f d6 00 00 00 jg 42a240 <__strcasecmp_l_sse42+0x1430> + 42a16a: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 42a16f: 66 0f 3a 0f 44 17 f0 palignr $0xb,-0x10(%rdi,%rdx,1),%xmm0 + 42a176: 0b + 42a177: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 42a17c: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 42a180: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 42a185: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 42a18a: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 42a18f: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 42a193: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 42a198: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 42a19d: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 42a1a2: 66 41 0f db f8 pand %xmm8,%xmm7 + 42a1a7: 66 45 0f db ca pand %xmm10,%xmm9 + 42a1ac: 66 0f db fe pand %xmm6,%xmm7 + 42a1b0: 66 44 0f db ce pand %xmm6,%xmm9 + 42a1b5: 66 0f eb c7 por %xmm7,%xmm0 + 42a1b9: 66 41 0f eb c9 por %xmm9,%xmm1 + 42a1be: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 42a1c4: 0f 86 66 07 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> + 42a1ca: 48 83 c2 10 add $0x10,%rdx + 42a1ce: 49 83 c2 10 add $0x10,%r10 + 42a1d2: 7f 6c jg 42a240 <__strcasecmp_l_sse42+0x1430> + 42a1d4: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 42a1d9: 66 0f 3a 0f 44 17 f0 palignr $0xb,-0x10(%rdi,%rdx,1),%xmm0 + 42a1e0: 0b + 42a1e1: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 42a1e6: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 42a1ea: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 42a1ef: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 42a1f4: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 42a1f9: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 42a1fd: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 42a202: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 42a207: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 42a20c: 66 41 0f db f8 pand %xmm8,%xmm7 + 42a211: 66 45 0f db ca pand %xmm10,%xmm9 + 42a216: 66 0f db fe pand %xmm6,%xmm7 + 42a21a: 66 44 0f db ce pand %xmm6,%xmm9 + 42a21f: 66 0f eb c7 por %xmm7,%xmm0 + 42a223: 66 41 0f eb c9 por %xmm9,%xmm1 + 42a228: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 42a22e: 0f 86 fc 06 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> + 42a234: 48 83 c2 10 add $0x10,%rdx + 42a238: e9 23 ff ff ff jmpq 42a160 <__strcasecmp_l_sse42+0x1350> + 42a23d: 0f 1f 00 nopl (%rax) + 42a240: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42a247: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 + 42a24d: 66 0f 73 d8 0b psrldq $0xb,%xmm0 + 42a252: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 + 42a258: 83 f9 04 cmp $0x4,%ecx + 42a25b: 0f 87 09 ff ff ff ja 42a16a <__strcasecmp_l_sse42+0x135a> + 42a261: e9 7b 06 00 00 jmpq 42a8e1 <__strcasecmp_l_sse42+0x1ad1> + 42a266: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42a26d: 00 00 00 + 42a270: 66 0f 73 fa 04 pslldq $0x4,%xmm2 + 42a275: 66 0f 6f f9 movdqa %xmm1,%xmm7 + 42a279: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 42a27e: 66 44 0f 6f ca movdqa %xmm2,%xmm9 + 42a283: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 42a288: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 42a28c: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 + 42a291: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 42a296: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 + 42a29b: 66 41 0f db f8 pand %xmm8,%xmm7 + 42a2a0: 66 45 0f db ca pand %xmm10,%xmm9 + 42a2a5: 66 0f db fe pand %xmm6,%xmm7 + 42a2a9: 66 44 0f db ce pand %xmm6,%xmm9 + 42a2ae: 66 0f eb cf por %xmm7,%xmm1 + 42a2b2: 66 41 0f eb d1 por %xmm9,%xmm2 + 42a2b7: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42a2bb: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42a2bf: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 42a2c4: d3 ea shr %cl,%edx + 42a2c6: 41 d3 e9 shr %cl,%r9d + 42a2c9: 44 29 ca sub %r9d,%edx + 42a2cc: 0f 85 86 06 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> + 42a2d2: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 42a2d6: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42a2dd: 41 b9 0c 00 00 00 mov $0xc,%r9d + 42a2e3: 4c 8d 57 0c lea 0xc(%rdi),%r10 + 42a2e7: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42a2ee: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42a2f5: 48 89 ca mov %rcx,%rdx + 42a2f8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 42a2ff: 00 + 42a300: 49 83 c2 10 add $0x10,%r10 + 42a304: 0f 8f d6 00 00 00 jg 42a3e0 <__strcasecmp_l_sse42+0x15d0> + 42a30a: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 42a30f: 66 0f 3a 0f 44 17 f0 palignr $0xc,-0x10(%rdi,%rdx,1),%xmm0 + 42a316: 0c + 42a317: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 42a31c: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 42a320: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 42a325: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 42a32a: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 42a32f: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 42a333: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 42a338: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 42a33d: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 42a342: 66 41 0f db f8 pand %xmm8,%xmm7 + 42a347: 66 45 0f db ca pand %xmm10,%xmm9 + 42a34c: 66 0f db fe pand %xmm6,%xmm7 + 42a350: 66 44 0f db ce pand %xmm6,%xmm9 + 42a355: 66 0f eb c7 por %xmm7,%xmm0 + 42a359: 66 41 0f eb c9 por %xmm9,%xmm1 + 42a35e: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 42a364: 0f 86 c6 05 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> + 42a36a: 48 83 c2 10 add $0x10,%rdx + 42a36e: 49 83 c2 10 add $0x10,%r10 + 42a372: 7f 6c jg 42a3e0 <__strcasecmp_l_sse42+0x15d0> + 42a374: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 42a379: 66 0f 3a 0f 44 17 f0 palignr $0xc,-0x10(%rdi,%rdx,1),%xmm0 + 42a380: 0c + 42a381: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 42a386: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 42a38a: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 42a38f: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 42a394: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 42a399: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 42a39d: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 42a3a2: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 42a3a7: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 42a3ac: 66 41 0f db f8 pand %xmm8,%xmm7 + 42a3b1: 66 45 0f db ca pand %xmm10,%xmm9 + 42a3b6: 66 0f db fe pand %xmm6,%xmm7 + 42a3ba: 66 44 0f db ce pand %xmm6,%xmm9 + 42a3bf: 66 0f eb c7 por %xmm7,%xmm0 + 42a3c3: 66 41 0f eb c9 por %xmm9,%xmm1 + 42a3c8: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 42a3ce: 0f 86 5c 05 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> + 42a3d4: 48 83 c2 10 add $0x10,%rdx + 42a3d8: e9 23 ff ff ff jmpq 42a300 <__strcasecmp_l_sse42+0x14f0> + 42a3dd: 0f 1f 00 nopl (%rax) + 42a3e0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42a3e7: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 + 42a3ed: 66 0f 73 d8 0c psrldq $0xc,%xmm0 + 42a3f2: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 + 42a3f8: 83 f9 03 cmp $0x3,%ecx + 42a3fb: 0f 87 09 ff ff ff ja 42a30a <__strcasecmp_l_sse42+0x14fa> + 42a401: e9 db 04 00 00 jmpq 42a8e1 <__strcasecmp_l_sse42+0x1ad1> + 42a406: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42a40d: 00 00 00 + 42a410: 66 0f 73 fa 03 pslldq $0x3,%xmm2 + 42a415: 66 0f 6f f9 movdqa %xmm1,%xmm7 + 42a419: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 42a41e: 66 44 0f 6f ca movdqa %xmm2,%xmm9 + 42a423: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 42a428: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 42a42c: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 + 42a431: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 42a436: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 + 42a43b: 66 41 0f db f8 pand %xmm8,%xmm7 + 42a440: 66 45 0f db ca pand %xmm10,%xmm9 + 42a445: 66 0f db fe pand %xmm6,%xmm7 + 42a449: 66 44 0f db ce pand %xmm6,%xmm9 + 42a44e: 66 0f eb cf por %xmm7,%xmm1 + 42a452: 66 41 0f eb d1 por %xmm9,%xmm2 + 42a457: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42a45b: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42a45f: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 42a464: d3 ea shr %cl,%edx + 42a466: 41 d3 e9 shr %cl,%r9d + 42a469: 44 29 ca sub %r9d,%edx + 42a46c: 0f 85 e6 04 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> + 42a472: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 42a476: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42a47d: 41 b9 0d 00 00 00 mov $0xd,%r9d + 42a483: 4c 8d 57 0d lea 0xd(%rdi),%r10 + 42a487: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42a48e: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42a495: 48 89 ca mov %rcx,%rdx + 42a498: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 42a49f: 00 + 42a4a0: 49 83 c2 10 add $0x10,%r10 + 42a4a4: 0f 8f d6 00 00 00 jg 42a580 <__strcasecmp_l_sse42+0x1770> + 42a4aa: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 42a4af: 66 0f 3a 0f 44 17 f0 palignr $0xd,-0x10(%rdi,%rdx,1),%xmm0 + 42a4b6: 0d + 42a4b7: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 42a4bc: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 42a4c0: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 42a4c5: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 42a4ca: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 42a4cf: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 42a4d3: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 42a4d8: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 42a4dd: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 42a4e2: 66 41 0f db f8 pand %xmm8,%xmm7 + 42a4e7: 66 45 0f db ca pand %xmm10,%xmm9 + 42a4ec: 66 0f db fe pand %xmm6,%xmm7 + 42a4f0: 66 44 0f db ce pand %xmm6,%xmm9 + 42a4f5: 66 0f eb c7 por %xmm7,%xmm0 + 42a4f9: 66 41 0f eb c9 por %xmm9,%xmm1 + 42a4fe: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 42a504: 0f 86 26 04 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> + 42a50a: 48 83 c2 10 add $0x10,%rdx + 42a50e: 49 83 c2 10 add $0x10,%r10 + 42a512: 7f 6c jg 42a580 <__strcasecmp_l_sse42+0x1770> + 42a514: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 42a519: 66 0f 3a 0f 44 17 f0 palignr $0xd,-0x10(%rdi,%rdx,1),%xmm0 + 42a520: 0d + 42a521: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 42a526: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 42a52a: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 42a52f: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 42a534: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 42a539: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 42a53d: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 42a542: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 42a547: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 42a54c: 66 41 0f db f8 pand %xmm8,%xmm7 + 42a551: 66 45 0f db ca pand %xmm10,%xmm9 + 42a556: 66 0f db fe pand %xmm6,%xmm7 + 42a55a: 66 44 0f db ce pand %xmm6,%xmm9 + 42a55f: 66 0f eb c7 por %xmm7,%xmm0 + 42a563: 66 41 0f eb c9 por %xmm9,%xmm1 + 42a568: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 42a56e: 0f 86 bc 03 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> + 42a574: 48 83 c2 10 add $0x10,%rdx + 42a578: e9 23 ff ff ff jmpq 42a4a0 <__strcasecmp_l_sse42+0x1690> + 42a57d: 0f 1f 00 nopl (%rax) + 42a580: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42a587: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 + 42a58d: 66 0f 73 d8 0d psrldq $0xd,%xmm0 + 42a592: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 + 42a598: 83 f9 02 cmp $0x2,%ecx + 42a59b: 0f 87 09 ff ff ff ja 42a4aa <__strcasecmp_l_sse42+0x169a> + 42a5a1: e9 3b 03 00 00 jmpq 42a8e1 <__strcasecmp_l_sse42+0x1ad1> + 42a5a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42a5ad: 00 00 00 + 42a5b0: 66 0f 73 fa 02 pslldq $0x2,%xmm2 + 42a5b5: 66 0f 6f f9 movdqa %xmm1,%xmm7 + 42a5b9: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 42a5be: 66 44 0f 6f ca movdqa %xmm2,%xmm9 + 42a5c3: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 42a5c8: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 42a5cc: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 + 42a5d1: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 42a5d6: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 + 42a5db: 66 41 0f db f8 pand %xmm8,%xmm7 + 42a5e0: 66 45 0f db ca pand %xmm10,%xmm9 + 42a5e5: 66 0f db fe pand %xmm6,%xmm7 + 42a5e9: 66 44 0f db ce pand %xmm6,%xmm9 + 42a5ee: 66 0f eb cf por %xmm7,%xmm1 + 42a5f2: 66 41 0f eb d1 por %xmm9,%xmm2 + 42a5f7: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42a5fb: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42a5ff: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 42a604: d3 ea shr %cl,%edx + 42a606: 41 d3 e9 shr %cl,%r9d + 42a609: 44 29 ca sub %r9d,%edx + 42a60c: 0f 85 46 03 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> + 42a612: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 42a616: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42a61d: 41 b9 0e 00 00 00 mov $0xe,%r9d + 42a623: 4c 8d 57 0e lea 0xe(%rdi),%r10 + 42a627: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42a62e: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42a635: 48 89 ca mov %rcx,%rdx + 42a638: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 42a63f: 00 + 42a640: 49 83 c2 10 add $0x10,%r10 + 42a644: 0f 8f d6 00 00 00 jg 42a720 <__strcasecmp_l_sse42+0x1910> + 42a64a: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 42a64f: 66 0f 3a 0f 44 17 f0 palignr $0xe,-0x10(%rdi,%rdx,1),%xmm0 + 42a656: 0e + 42a657: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 42a65c: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 42a660: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 42a665: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 42a66a: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 42a66f: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 42a673: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 42a678: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 42a67d: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 42a682: 66 41 0f db f8 pand %xmm8,%xmm7 + 42a687: 66 45 0f db ca pand %xmm10,%xmm9 + 42a68c: 66 0f db fe pand %xmm6,%xmm7 + 42a690: 66 44 0f db ce pand %xmm6,%xmm9 + 42a695: 66 0f eb c7 por %xmm7,%xmm0 + 42a699: 66 41 0f eb c9 por %xmm9,%xmm1 + 42a69e: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 42a6a4: 0f 86 86 02 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> + 42a6aa: 48 83 c2 10 add $0x10,%rdx + 42a6ae: 49 83 c2 10 add $0x10,%r10 + 42a6b2: 7f 6c jg 42a720 <__strcasecmp_l_sse42+0x1910> + 42a6b4: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 42a6b9: 66 0f 3a 0f 44 17 f0 palignr $0xe,-0x10(%rdi,%rdx,1),%xmm0 + 42a6c0: 0e + 42a6c1: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 42a6c6: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 42a6ca: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 42a6cf: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 42a6d4: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 42a6d9: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 42a6dd: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 42a6e2: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 42a6e7: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 42a6ec: 66 41 0f db f8 pand %xmm8,%xmm7 + 42a6f1: 66 45 0f db ca pand %xmm10,%xmm9 + 42a6f6: 66 0f db fe pand %xmm6,%xmm7 + 42a6fa: 66 44 0f db ce pand %xmm6,%xmm9 + 42a6ff: 66 0f eb c7 por %xmm7,%xmm0 + 42a703: 66 41 0f eb c9 por %xmm9,%xmm1 + 42a708: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 42a70e: 0f 86 1c 02 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> + 42a714: 48 83 c2 10 add $0x10,%rdx + 42a718: e9 23 ff ff ff jmpq 42a640 <__strcasecmp_l_sse42+0x1830> + 42a71d: 0f 1f 00 nopl (%rax) + 42a720: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42a727: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 + 42a72d: 66 0f 73 d8 0e psrldq $0xe,%xmm0 + 42a732: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 + 42a738: 83 f9 01 cmp $0x1,%ecx + 42a73b: 0f 87 09 ff ff ff ja 42a64a <__strcasecmp_l_sse42+0x183a> + 42a741: e9 9b 01 00 00 jmpq 42a8e1 <__strcasecmp_l_sse42+0x1ad1> + 42a746: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42a74d: 00 00 00 + 42a750: 66 0f 73 fa 01 pslldq $0x1,%xmm2 + 42a755: 66 0f 6f f9 movdqa %xmm1,%xmm7 + 42a759: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 42a75e: 66 44 0f 6f ca movdqa %xmm2,%xmm9 + 42a763: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 42a768: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 42a76c: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 + 42a771: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 42a776: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 + 42a77b: 66 41 0f db f8 pand %xmm8,%xmm7 + 42a780: 66 45 0f db ca pand %xmm10,%xmm9 + 42a785: 66 0f db fe pand %xmm6,%xmm7 + 42a789: 66 44 0f db ce pand %xmm6,%xmm9 + 42a78e: 66 0f eb cf por %xmm7,%xmm1 + 42a792: 66 41 0f eb d1 por %xmm9,%xmm2 + 42a797: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42a79b: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42a79f: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 42a7a4: d3 ea shr %cl,%edx + 42a7a6: 41 d3 e9 shr %cl,%r9d + 42a7a9: 44 29 ca sub %r9d,%edx + 42a7ac: 0f 85 a6 01 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> + 42a7b2: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 42a7b6: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42a7bd: 41 b9 0f 00 00 00 mov $0xf,%r9d + 42a7c3: 4c 8d 57 0f lea 0xf(%rdi),%r10 + 42a7c7: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42a7ce: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42a7d5: 48 89 ca mov %rcx,%rdx + 42a7d8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 42a7df: 00 + 42a7e0: 49 83 c2 10 add $0x10,%r10 + 42a7e4: 0f 8f d6 00 00 00 jg 42a8c0 <__strcasecmp_l_sse42+0x1ab0> + 42a7ea: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 42a7ef: 66 0f 3a 0f 44 17 f0 palignr $0xf,-0x10(%rdi,%rdx,1),%xmm0 + 42a7f6: 0f + 42a7f7: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 42a7fc: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 42a800: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 42a805: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 42a80a: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 42a80f: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 42a813: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 42a818: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 42a81d: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 42a822: 66 41 0f db f8 pand %xmm8,%xmm7 + 42a827: 66 45 0f db ca pand %xmm10,%xmm9 + 42a82c: 66 0f db fe pand %xmm6,%xmm7 + 42a830: 66 44 0f db ce pand %xmm6,%xmm9 + 42a835: 66 0f eb c7 por %xmm7,%xmm0 + 42a839: 66 41 0f eb c9 por %xmm9,%xmm1 + 42a83e: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 42a844: 0f 86 e6 00 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> + 42a84a: 48 83 c2 10 add $0x10,%rdx + 42a84e: 49 83 c2 10 add $0x10,%r10 + 42a852: 7f 6c jg 42a8c0 <__strcasecmp_l_sse42+0x1ab0> + 42a854: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 + 42a859: 66 0f 3a 0f 44 17 f0 palignr $0xf,-0x10(%rdi,%rdx,1),%xmm0 + 42a860: 0f + 42a861: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 42a866: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 42a86a: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 42a86f: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 42a874: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 42a879: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 42a87d: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 42a882: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 42a887: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 42a88c: 66 41 0f db f8 pand %xmm8,%xmm7 + 42a891: 66 45 0f db ca pand %xmm10,%xmm9 + 42a896: 66 0f db fe pand %xmm6,%xmm7 + 42a89a: 66 44 0f db ce pand %xmm6,%xmm9 + 42a89f: 66 0f eb c7 por %xmm7,%xmm0 + 42a8a3: 66 41 0f eb c9 por %xmm9,%xmm1 + 42a8a8: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 42a8ae: 0f 86 7c 00 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> + 42a8b4: 48 83 c2 10 add $0x10,%rdx + 42a8b8: e9 23 ff ff ff jmpq 42a7e0 <__strcasecmp_l_sse42+0x19d0> + 42a8bd: 0f 1f 00 nopl (%rax) + 42a8c0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42a8c7: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 + 42a8cd: 66 0f 73 d8 0f psrldq $0xf,%xmm0 + 42a8d2: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 + 42a8d8: 83 f9 00 cmp $0x0,%ecx + 42a8db: 0f 87 09 ff ff ff ja 42a7ea <__strcasecmp_l_sse42+0x19da> + 42a8e1: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 + 42a8e6: 66 0f 6f f8 movdqa %xmm0,%xmm7 + 42a8ea: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 + 42a8ef: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 + 42a8f4: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 + 42a8f9: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 + 42a8fd: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 + 42a902: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 + 42a907: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 + 42a90c: 66 41 0f db f8 pand %xmm8,%xmm7 + 42a911: 66 45 0f db ca pand %xmm10,%xmm9 + 42a916: 66 0f db fe pand %xmm6,%xmm7 + 42a91a: 66 44 0f db ce pand %xmm6,%xmm9 + 42a91f: 66 0f eb c7 por %xmm7,%xmm0 + 42a923: 66 41 0f eb c9 por %xmm9,%xmm1 + 42a928: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 + 42a92e: 66 90 xchg %ax,%ax + 42a930: 73 5a jae 42a98c <__strcasecmp_l_sse42+0x1b7c> + 42a932: 48 01 ca add %rcx,%rdx + 42a935: 4a 8d 7c 0f f0 lea -0x10(%rdi,%r9,1),%rdi + 42a93a: 0f b6 04 17 movzbl (%rdi,%rdx,1),%eax + 42a93e: 0f b6 14 16 movzbl (%rsi,%rdx,1),%edx + 42a942: 45 85 c0 test %r8d,%r8d + 42a945: 74 01 je 42a948 <__strcasecmp_l_sse42+0x1b38> + 42a947: 92 xchg %eax,%edx + 42a948: 48 8d 0d f1 cb 07 00 lea 0x7cbf1(%rip),%rcx # 4a7540 <_nl_C_LC_CTYPE_tolower+0x200> + 42a94f: 8b 14 91 mov (%rcx,%rdx,4),%edx + 42a952: 8b 04 81 mov (%rcx,%rax,4),%eax + 42a955: 29 d0 sub %edx,%eax + 42a957: c3 retq + 42a958: 48 8d 3c 07 lea (%rdi,%rax,1),%rdi + 42a95c: 48 8d 34 0e lea (%rsi,%rcx,1),%rsi + 42a960: 45 85 c0 test %r8d,%r8d + 42a963: 74 0b je 42a970 <__strcasecmp_l_sse42+0x1b60> + 42a965: 48 87 f7 xchg %rsi,%rdi + 42a968: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 42a96f: 00 + 42a970: 48 0f bc d2 bsf %rdx,%rdx + 42a974: 0f b6 0c 16 movzbl (%rsi,%rdx,1),%ecx + 42a978: 0f b6 04 17 movzbl (%rdi,%rdx,1),%eax + 42a97c: 48 8d 15 bd cb 07 00 lea 0x7cbbd(%rip),%rdx # 4a7540 <_nl_C_LC_CTYPE_tolower+0x200> + 42a983: 8b 0c 8a mov (%rdx,%rcx,4),%ecx + 42a986: 8b 04 82 mov (%rdx,%rax,4),%eax + 42a989: 29 c8 sub %ecx,%eax + 42a98b: c3 retq + 42a98c: 31 c0 xor %eax,%eax + 42a98e: c3 retq + 42a98f: 90 nop + 42a990: 0f b6 0e movzbl (%rsi),%ecx + 42a993: 0f b6 07 movzbl (%rdi),%eax + 42a996: 48 8d 15 a3 cb 07 00 lea 0x7cba3(%rip),%rdx # 4a7540 <_nl_C_LC_CTYPE_tolower+0x200> + 42a99d: 8b 0c 8a mov (%rdx,%rcx,4),%ecx + 42a9a0: 8b 04 82 mov (%rdx,%rax,4),%eax + 42a9a3: 29 c8 sub %ecx,%eax + 42a9a5: c3 retq + 42a9a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42a9ad: 00 00 00 + +000000000042a9b0 <__strcasecmp_avx>: + 42a9b0: 48 c7 c0 b8 ff ff ff mov $0xffffffffffffffb8,%rax + 42a9b7: 64 48 8b 10 mov %fs:(%rax),%rdx + 42a9bb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + +000000000042a9c0 <__strcasecmp_l_avx>: + 42a9c0: 48 8b 02 mov (%rdx),%rax + 42a9c3: f7 80 78 02 00 00 01 testl $0x1,0x278(%rax) + 42a9ca: 00 00 00 + 42a9cd: 0f 85 2d 39 01 00 jne 43e300 <__strcasecmp_l_nonascii> + 42a9d3: 89 f1 mov %esi,%ecx + 42a9d5: 89 f8 mov %edi,%eax + 42a9d7: 48 83 e1 3f and $0x3f,%rcx + 42a9db: 48 83 e0 3f and $0x3f,%rax + 42a9df: c5 f9 6f 25 c9 86 07 vmovdqa 0x786c9(%rip),%xmm4 # 4a30b0 <__func__.10972+0xf0> + 42a9e6: 00 + 42a9e7: c5 f9 6f 2d f1 86 07 vmovdqa 0x786f1(%rip),%xmm5 # 4a30e0 + 42a9ee: 00 + 42a9ef: c5 f9 6f 35 d9 86 07 vmovdqa 0x786d9(%rip),%xmm6 # 4a30d0 + 42a9f6: 00 + 42a9f7: 83 f9 30 cmp $0x30,%ecx + 42a9fa: 77 64 ja 42aa60 <__strcasecmp_l_avx+0xa0> + 42a9fc: 83 f8 30 cmp $0x30,%eax + 42a9ff: 77 5f ja 42aa60 <__strcasecmp_l_avx+0xa0> + 42aa01: c5 fa 6f 0f vmovdqu (%rdi),%xmm1 + 42aa05: c5 fa 6f 16 vmovdqu (%rsi),%xmm2 + 42aa09: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 + 42aa0d: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 + 42aa11: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 + 42aa15: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 + 42aa19: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42aa1d: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42aa22: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42aa26: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42aa2a: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 + 42aa2e: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 + 42aa32: c5 f9 ef c0 vpxor %xmm0,%xmm0,%xmm0 + 42aa36: c5 f9 74 c1 vpcmpeqb %xmm1,%xmm0,%xmm0 + 42aa3a: c5 f1 74 ca vpcmpeqb %xmm2,%xmm1,%xmm1 + 42aa3e: c5 f1 f8 c8 vpsubb %xmm0,%xmm1,%xmm1 + 42aa42: c5 f9 d7 d1 vpmovmskb %xmm1,%edx + 42aa46: 81 ea ff ff 00 00 sub $0xffff,%edx + 42aa4c: 0f 85 8e 15 00 00 jne 42bfe0 <__strcasecmp_l_avx+0x1620> + 42aa52: 48 83 c6 10 add $0x10,%rsi + 42aa56: 48 83 c7 10 add $0x10,%rdi + 42aa5a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 42aa60: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi + 42aa64: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi + 42aa68: ba ff ff 00 00 mov $0xffff,%edx + 42aa6d: 45 31 c0 xor %r8d,%r8d + 42aa70: 83 e1 0f and $0xf,%ecx + 42aa73: 83 e0 0f and $0xf,%eax + 42aa76: c5 f9 ef c0 vpxor %xmm0,%xmm0,%xmm0 + 42aa7a: 39 c1 cmp %eax,%ecx + 42aa7c: 74 32 je 42aab0 <__strcasecmp_l_avx+0xf0> + 42aa7e: 77 07 ja 42aa87 <__strcasecmp_l_avx+0xc7> + 42aa80: 41 89 d0 mov %edx,%r8d + 42aa83: 91 xchg %eax,%ecx + 42aa84: 48 87 f7 xchg %rsi,%rdi + 42aa87: c5 f9 6f 17 vmovdqa (%rdi),%xmm2 + 42aa8b: c5 f9 6f 0e vmovdqa (%rsi),%xmm1 + 42aa8f: 4c 8d 48 0f lea 0xf(%rax),%r9 + 42aa93: 49 29 c9 sub %rcx,%r9 + 42aa96: 4c 8d 15 93 86 07 00 lea 0x78693(%rip),%r10 # 4a3130 + 42aa9d: 4f 63 0c 8a movslq (%r10,%r9,4),%r9 + 42aaa1: c5 f9 74 c1 vpcmpeqb %xmm1,%xmm0,%xmm0 + 42aaa5: 4f 8d 14 0a lea (%r10,%r9,1),%r10 + 42aaa9: 41 ff e2 jmpq *%r10 + 42aaac: 0f 1f 40 00 nopl 0x0(%rax) + 42aab0: c5 f9 6f 0e vmovdqa (%rsi),%xmm1 + 42aab4: c5 f9 74 c1 vpcmpeqb %xmm1,%xmm0,%xmm0 + 42aab8: c5 f9 6f 17 vmovdqa (%rdi),%xmm2 + 42aabc: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 + 42aac0: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 + 42aac4: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 + 42aac8: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 + 42aacc: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42aad0: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42aad5: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42aad9: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42aadd: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 + 42aae1: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 + 42aae5: c5 f1 74 ca vpcmpeqb %xmm2,%xmm1,%xmm1 + 42aae9: c5 f1 f8 c8 vpsubb %xmm0,%xmm1,%xmm1 + 42aaed: c5 79 d7 c9 vpmovmskb %xmm1,%r9d + 42aaf1: d3 ea shr %cl,%edx + 42aaf3: 41 d3 e9 shr %cl,%r9d + 42aaf6: 44 29 ca sub %r9d,%edx + 42aaf9: 0f 85 c9 14 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> + 42aaff: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42ab06: 49 c7 c1 10 00 00 00 mov $0x10,%r9 + 42ab0d: 48 89 ca mov %rcx,%rdx + 42ab10: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42ab15: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42ab1a: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42ab1e: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42ab22: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42ab26: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42ab2a: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42ab2e: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42ab33: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42ab37: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42ab3b: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42ab3f: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42ab43: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42ab49: 48 8d 52 10 lea 0x10(%rdx),%rdx + 42ab4d: 76 41 jbe 42ab90 <__strcasecmp_l_avx+0x1d0> + 42ab4f: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42ab54: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42ab59: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42ab5d: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42ab61: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42ab65: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42ab69: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42ab6d: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42ab72: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42ab76: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42ab7a: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42ab7e: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42ab82: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42ab88: 48 8d 52 10 lea 0x10(%rdx),%rdx + 42ab8c: 76 02 jbe 42ab90 <__strcasecmp_l_avx+0x1d0> + 42ab8e: eb 80 jmp 42ab10 <__strcasecmp_l_avx+0x150> + 42ab90: 0f 83 66 14 00 00 jae 42bffc <__strcasecmp_l_avx+0x163c> + 42ab96: 48 8d 4c 0a f0 lea -0x10(%rdx,%rcx,1),%rcx + 42ab9b: 0f b6 04 0f movzbl (%rdi,%rcx,1),%eax + 42ab9f: 0f b6 14 0e movzbl (%rsi,%rcx,1),%edx + 42aba3: 48 8d 0d 96 c9 07 00 lea 0x7c996(%rip),%rcx # 4a7540 <_nl_C_LC_CTYPE_tolower+0x200> + 42abaa: 8b 04 81 mov (%rcx,%rax,4),%eax + 42abad: 8b 14 91 mov (%rcx,%rdx,4),%edx + 42abb0: 29 d0 sub %edx,%eax + 42abb2: c3 retq + 42abb3: 0f 1f 00 nopl (%rax) + 42abb6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42abbd: 00 00 00 + 42abc0: c5 e9 73 fa 0f vpslldq $0xf,%xmm2,%xmm2 + 42abc5: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 + 42abc9: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 + 42abcd: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 + 42abd1: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 + 42abd5: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42abd9: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42abde: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42abe2: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42abe6: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 + 42abea: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 + 42abee: c5 e9 74 d1 vpcmpeqb %xmm1,%xmm2,%xmm2 + 42abf2: c5 e9 f8 d0 vpsubb %xmm0,%xmm2,%xmm2 + 42abf6: c5 79 d7 ca vpmovmskb %xmm2,%r9d + 42abfa: d3 ea shr %cl,%edx + 42abfc: 41 d3 e9 shr %cl,%r9d + 42abff: 44 29 ca sub %r9d,%edx + 42ac02: 0f 85 c0 13 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> + 42ac08: c5 f9 6f 1f vmovdqa (%rdi),%xmm3 + 42ac0c: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42ac13: 41 b9 01 00 00 00 mov $0x1,%r9d + 42ac19: 4c 8d 57 01 lea 0x1(%rdi),%r10 + 42ac1d: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42ac24: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42ac2b: 48 89 ca mov %rcx,%rdx + 42ac2e: 66 90 xchg %ax,%ax + 42ac30: 49 83 c2 10 add $0x10,%r10 + 42ac34: 0f 8f a6 00 00 00 jg 42ace0 <__strcasecmp_l_avx+0x320> + 42ac3a: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42ac3f: c4 e3 79 0f 44 17 f0 vpalignr $0x1,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 + 42ac46: 01 + 42ac47: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42ac4c: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42ac50: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42ac54: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42ac58: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42ac5c: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42ac60: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42ac65: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42ac69: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42ac6d: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42ac71: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42ac75: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42ac7b: 0f 86 1f 13 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> + 42ac81: 48 83 c2 10 add $0x10,%rdx + 42ac85: 49 83 c2 10 add $0x10,%r10 + 42ac89: 7f 55 jg 42ace0 <__strcasecmp_l_avx+0x320> + 42ac8b: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42ac90: c4 e3 79 0f 44 17 f0 vpalignr $0x1,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 + 42ac97: 01 + 42ac98: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42ac9d: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42aca1: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42aca5: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42aca9: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42acad: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42acb1: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42acb6: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42acba: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42acbe: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42acc2: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42acc6: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42accc: 0f 86 ce 12 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> + 42acd2: 48 83 c2 10 add $0x10,%rdx + 42acd6: e9 55 ff ff ff jmpq 42ac30 <__strcasecmp_l_avx+0x270> + 42acdb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 42ace0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42ace7: c5 f9 6f 44 17 f0 vmovdqa -0x10(%rdi,%rdx,1),%xmm0 + 42aced: c5 f9 73 d8 01 vpsrldq $0x1,%xmm0,%xmm0 + 42acf2: c4 e3 79 63 c0 3a vpcmpistri $0x3a,%xmm0,%xmm0 + 42acf8: 83 f9 0e cmp $0xe,%ecx + 42acfb: 0f 87 39 ff ff ff ja 42ac3a <__strcasecmp_l_avx+0x27a> + 42ad01: e9 5b 12 00 00 jmpq 42bf61 <__strcasecmp_l_avx+0x15a1> + 42ad06: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42ad0d: 00 00 00 + 42ad10: c5 e9 73 fa 0e vpslldq $0xe,%xmm2,%xmm2 + 42ad15: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 + 42ad19: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 + 42ad1d: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 + 42ad21: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 + 42ad25: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42ad29: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42ad2e: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42ad32: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42ad36: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 + 42ad3a: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 + 42ad3e: c5 e9 74 d1 vpcmpeqb %xmm1,%xmm2,%xmm2 + 42ad42: c5 e9 f8 d0 vpsubb %xmm0,%xmm2,%xmm2 + 42ad46: c5 79 d7 ca vpmovmskb %xmm2,%r9d + 42ad4a: d3 ea shr %cl,%edx + 42ad4c: 41 d3 e9 shr %cl,%r9d + 42ad4f: 44 29 ca sub %r9d,%edx + 42ad52: 0f 85 70 12 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> + 42ad58: c5 f9 6f 1f vmovdqa (%rdi),%xmm3 + 42ad5c: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42ad63: 41 b9 02 00 00 00 mov $0x2,%r9d + 42ad69: 4c 8d 57 02 lea 0x2(%rdi),%r10 + 42ad6d: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42ad74: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42ad7b: 48 89 ca mov %rcx,%rdx + 42ad7e: 66 90 xchg %ax,%ax + 42ad80: 49 83 c2 10 add $0x10,%r10 + 42ad84: 0f 8f a6 00 00 00 jg 42ae30 <__strcasecmp_l_avx+0x470> + 42ad8a: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42ad8f: c4 e3 79 0f 44 17 f0 vpalignr $0x2,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 + 42ad96: 02 + 42ad97: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42ad9c: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42ada0: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42ada4: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42ada8: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42adac: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42adb0: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42adb5: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42adb9: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42adbd: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42adc1: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42adc5: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42adcb: 0f 86 cf 11 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> + 42add1: 48 83 c2 10 add $0x10,%rdx + 42add5: 49 83 c2 10 add $0x10,%r10 + 42add9: 7f 55 jg 42ae30 <__strcasecmp_l_avx+0x470> + 42addb: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42ade0: c4 e3 79 0f 44 17 f0 vpalignr $0x2,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 + 42ade7: 02 + 42ade8: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42aded: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42adf1: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42adf5: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42adf9: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42adfd: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42ae01: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42ae06: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42ae0a: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42ae0e: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42ae12: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42ae16: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42ae1c: 0f 86 7e 11 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> + 42ae22: 48 83 c2 10 add $0x10,%rdx + 42ae26: e9 55 ff ff ff jmpq 42ad80 <__strcasecmp_l_avx+0x3c0> + 42ae2b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 42ae30: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42ae37: c5 f9 6f 44 17 f0 vmovdqa -0x10(%rdi,%rdx,1),%xmm0 + 42ae3d: c5 f9 73 d8 02 vpsrldq $0x2,%xmm0,%xmm0 + 42ae42: c4 e3 79 63 c0 3a vpcmpistri $0x3a,%xmm0,%xmm0 + 42ae48: 83 f9 0d cmp $0xd,%ecx + 42ae4b: 0f 87 39 ff ff ff ja 42ad8a <__strcasecmp_l_avx+0x3ca> + 42ae51: e9 0b 11 00 00 jmpq 42bf61 <__strcasecmp_l_avx+0x15a1> + 42ae56: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42ae5d: 00 00 00 + 42ae60: c5 e9 73 fa 0d vpslldq $0xd,%xmm2,%xmm2 + 42ae65: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 + 42ae69: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 + 42ae6d: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 + 42ae71: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 + 42ae75: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42ae79: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42ae7e: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42ae82: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42ae86: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 + 42ae8a: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 + 42ae8e: c5 e9 74 d1 vpcmpeqb %xmm1,%xmm2,%xmm2 + 42ae92: c5 e9 f8 d0 vpsubb %xmm0,%xmm2,%xmm2 + 42ae96: c5 79 d7 ca vpmovmskb %xmm2,%r9d + 42ae9a: d3 ea shr %cl,%edx + 42ae9c: 41 d3 e9 shr %cl,%r9d + 42ae9f: 44 29 ca sub %r9d,%edx + 42aea2: 0f 85 20 11 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> + 42aea8: c5 f9 6f 1f vmovdqa (%rdi),%xmm3 + 42aeac: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42aeb3: 41 b9 03 00 00 00 mov $0x3,%r9d + 42aeb9: 4c 8d 57 03 lea 0x3(%rdi),%r10 + 42aebd: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42aec4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42aecb: 48 89 ca mov %rcx,%rdx + 42aece: 49 83 c2 10 add $0x10,%r10 + 42aed2: 0f 8f a8 00 00 00 jg 42af80 <__strcasecmp_l_avx+0x5c0> + 42aed8: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42aedd: c4 e3 79 0f 44 17 f0 vpalignr $0x3,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 + 42aee4: 03 + 42aee5: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42aeea: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42aeee: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42aef2: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42aef6: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42aefa: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42aefe: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42af03: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42af07: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42af0b: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42af0f: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42af13: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42af19: 0f 86 81 10 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> + 42af1f: 48 83 c2 10 add $0x10,%rdx + 42af23: 49 83 c2 10 add $0x10,%r10 + 42af27: 7f 57 jg 42af80 <__strcasecmp_l_avx+0x5c0> + 42af29: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42af2e: c4 e3 79 0f 44 17 f0 vpalignr $0x3,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 + 42af35: 03 + 42af36: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42af3b: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42af3f: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42af43: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42af47: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42af4b: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42af4f: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42af54: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42af58: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42af5c: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42af60: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42af64: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42af6a: 0f 86 30 10 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> + 42af70: 48 83 c2 10 add $0x10,%rdx + 42af74: e9 55 ff ff ff jmpq 42aece <__strcasecmp_l_avx+0x50e> + 42af79: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 42af80: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42af87: c5 f9 6f 44 17 f0 vmovdqa -0x10(%rdi,%rdx,1),%xmm0 + 42af8d: c5 f9 73 d8 03 vpsrldq $0x3,%xmm0,%xmm0 + 42af92: c4 e3 79 63 c0 3a vpcmpistri $0x3a,%xmm0,%xmm0 + 42af98: 83 f9 0c cmp $0xc,%ecx + 42af9b: 0f 87 37 ff ff ff ja 42aed8 <__strcasecmp_l_avx+0x518> + 42afa1: e9 bb 0f 00 00 jmpq 42bf61 <__strcasecmp_l_avx+0x15a1> + 42afa6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42afad: 00 00 00 + 42afb0: c5 e9 73 fa 0c vpslldq $0xc,%xmm2,%xmm2 + 42afb5: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 + 42afb9: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 + 42afbd: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 + 42afc1: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 + 42afc5: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42afc9: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42afce: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42afd2: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42afd6: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 + 42afda: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 + 42afde: c5 e9 74 d1 vpcmpeqb %xmm1,%xmm2,%xmm2 + 42afe2: c5 e9 f8 d0 vpsubb %xmm0,%xmm2,%xmm2 + 42afe6: c5 79 d7 ca vpmovmskb %xmm2,%r9d + 42afea: d3 ea shr %cl,%edx + 42afec: 41 d3 e9 shr %cl,%r9d + 42afef: 44 29 ca sub %r9d,%edx + 42aff2: 0f 85 d0 0f 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> + 42aff8: c5 f9 6f 1f vmovdqa (%rdi),%xmm3 + 42affc: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42b003: 41 b9 04 00 00 00 mov $0x4,%r9d + 42b009: 4c 8d 57 04 lea 0x4(%rdi),%r10 + 42b00d: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42b014: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42b01b: 48 89 ca mov %rcx,%rdx + 42b01e: 66 90 xchg %ax,%ax + 42b020: 49 83 c2 10 add $0x10,%r10 + 42b024: 0f 8f a6 00 00 00 jg 42b0d0 <__strcasecmp_l_avx+0x710> + 42b02a: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42b02f: c4 e3 79 0f 44 17 f0 vpalignr $0x4,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 + 42b036: 04 + 42b037: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42b03c: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42b040: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42b044: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42b048: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42b04c: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42b050: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42b055: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42b059: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42b05d: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42b061: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42b065: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42b06b: 0f 86 2f 0f 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> + 42b071: 48 83 c2 10 add $0x10,%rdx + 42b075: 49 83 c2 10 add $0x10,%r10 + 42b079: 7f 55 jg 42b0d0 <__strcasecmp_l_avx+0x710> + 42b07b: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42b080: c4 e3 79 0f 44 17 f0 vpalignr $0x4,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 + 42b087: 04 + 42b088: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42b08d: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42b091: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42b095: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42b099: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42b09d: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42b0a1: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42b0a6: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42b0aa: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42b0ae: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42b0b2: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42b0b6: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42b0bc: 0f 86 de 0e 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> + 42b0c2: 48 83 c2 10 add $0x10,%rdx + 42b0c6: e9 55 ff ff ff jmpq 42b020 <__strcasecmp_l_avx+0x660> + 42b0cb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 42b0d0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42b0d7: c5 f9 6f 44 17 f0 vmovdqa -0x10(%rdi,%rdx,1),%xmm0 + 42b0dd: c5 f9 73 d8 04 vpsrldq $0x4,%xmm0,%xmm0 + 42b0e2: c4 e3 79 63 c0 3a vpcmpistri $0x3a,%xmm0,%xmm0 + 42b0e8: 83 f9 0b cmp $0xb,%ecx + 42b0eb: 0f 87 39 ff ff ff ja 42b02a <__strcasecmp_l_avx+0x66a> + 42b0f1: e9 6b 0e 00 00 jmpq 42bf61 <__strcasecmp_l_avx+0x15a1> + 42b0f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42b0fd: 00 00 00 + 42b100: c5 e9 73 fa 0b vpslldq $0xb,%xmm2,%xmm2 + 42b105: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 + 42b109: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 + 42b10d: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 + 42b111: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 + 42b115: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42b119: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42b11e: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42b122: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42b126: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 + 42b12a: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 + 42b12e: c5 e9 74 d1 vpcmpeqb %xmm1,%xmm2,%xmm2 + 42b132: c5 e9 f8 d0 vpsubb %xmm0,%xmm2,%xmm2 + 42b136: c5 79 d7 ca vpmovmskb %xmm2,%r9d + 42b13a: d3 ea shr %cl,%edx + 42b13c: 41 d3 e9 shr %cl,%r9d + 42b13f: 44 29 ca sub %r9d,%edx + 42b142: 0f 85 80 0e 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> + 42b148: c5 f9 6f 1f vmovdqa (%rdi),%xmm3 + 42b14c: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42b153: 41 b9 05 00 00 00 mov $0x5,%r9d + 42b159: 4c 8d 57 05 lea 0x5(%rdi),%r10 + 42b15d: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42b164: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42b16b: 48 89 ca mov %rcx,%rdx + 42b16e: 66 90 xchg %ax,%ax + 42b170: 49 83 c2 10 add $0x10,%r10 + 42b174: 0f 8f a6 00 00 00 jg 42b220 <__strcasecmp_l_avx+0x860> + 42b17a: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42b17f: c4 e3 79 0f 44 17 f0 vpalignr $0x5,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 + 42b186: 05 + 42b187: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42b18c: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42b190: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42b194: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42b198: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42b19c: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42b1a0: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42b1a5: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42b1a9: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42b1ad: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42b1b1: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42b1b5: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42b1bb: 0f 86 df 0d 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> + 42b1c1: 48 83 c2 10 add $0x10,%rdx + 42b1c5: 49 83 c2 10 add $0x10,%r10 + 42b1c9: 7f 55 jg 42b220 <__strcasecmp_l_avx+0x860> + 42b1cb: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42b1d0: c4 e3 79 0f 44 17 f0 vpalignr $0x5,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 + 42b1d7: 05 + 42b1d8: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42b1dd: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42b1e1: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42b1e5: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42b1e9: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42b1ed: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42b1f1: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42b1f6: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42b1fa: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42b1fe: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42b202: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42b206: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42b20c: 0f 86 8e 0d 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> + 42b212: 48 83 c2 10 add $0x10,%rdx + 42b216: e9 55 ff ff ff jmpq 42b170 <__strcasecmp_l_avx+0x7b0> + 42b21b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 42b220: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42b227: c5 f9 6f 44 17 f0 vmovdqa -0x10(%rdi,%rdx,1),%xmm0 + 42b22d: c5 f9 73 d8 05 vpsrldq $0x5,%xmm0,%xmm0 + 42b232: c4 e3 79 63 c0 3a vpcmpistri $0x3a,%xmm0,%xmm0 + 42b238: 83 f9 0a cmp $0xa,%ecx + 42b23b: 0f 87 39 ff ff ff ja 42b17a <__strcasecmp_l_avx+0x7ba> + 42b241: e9 1b 0d 00 00 jmpq 42bf61 <__strcasecmp_l_avx+0x15a1> + 42b246: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42b24d: 00 00 00 + 42b250: c5 e9 73 fa 0a vpslldq $0xa,%xmm2,%xmm2 + 42b255: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 + 42b259: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 + 42b25d: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 + 42b261: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 + 42b265: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42b269: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42b26e: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42b272: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42b276: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 + 42b27a: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 + 42b27e: c5 e9 74 d1 vpcmpeqb %xmm1,%xmm2,%xmm2 + 42b282: c5 e9 f8 d0 vpsubb %xmm0,%xmm2,%xmm2 + 42b286: c5 79 d7 ca vpmovmskb %xmm2,%r9d + 42b28a: d3 ea shr %cl,%edx + 42b28c: 41 d3 e9 shr %cl,%r9d + 42b28f: 44 29 ca sub %r9d,%edx + 42b292: 0f 85 30 0d 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> + 42b298: c5 f9 6f 1f vmovdqa (%rdi),%xmm3 + 42b29c: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42b2a3: 41 b9 06 00 00 00 mov $0x6,%r9d + 42b2a9: 4c 8d 57 06 lea 0x6(%rdi),%r10 + 42b2ad: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42b2b4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42b2bb: 48 89 ca mov %rcx,%rdx + 42b2be: 66 90 xchg %ax,%ax + 42b2c0: 49 83 c2 10 add $0x10,%r10 + 42b2c4: 0f 8f a6 00 00 00 jg 42b370 <__strcasecmp_l_avx+0x9b0> + 42b2ca: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42b2cf: c4 e3 79 0f 44 17 f0 vpalignr $0x6,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 + 42b2d6: 06 + 42b2d7: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42b2dc: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42b2e0: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42b2e4: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42b2e8: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42b2ec: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42b2f0: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42b2f5: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42b2f9: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42b2fd: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42b301: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42b305: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42b30b: 0f 86 8f 0c 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> + 42b311: 48 83 c2 10 add $0x10,%rdx + 42b315: 49 83 c2 10 add $0x10,%r10 + 42b319: 7f 55 jg 42b370 <__strcasecmp_l_avx+0x9b0> + 42b31b: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42b320: c4 e3 79 0f 44 17 f0 vpalignr $0x6,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 + 42b327: 06 + 42b328: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42b32d: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42b331: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42b335: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42b339: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42b33d: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42b341: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42b346: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42b34a: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42b34e: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42b352: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42b356: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42b35c: 0f 86 3e 0c 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> + 42b362: 48 83 c2 10 add $0x10,%rdx + 42b366: e9 55 ff ff ff jmpq 42b2c0 <__strcasecmp_l_avx+0x900> + 42b36b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 42b370: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42b377: c5 f9 6f 44 17 f0 vmovdqa -0x10(%rdi,%rdx,1),%xmm0 + 42b37d: c5 f9 73 d8 06 vpsrldq $0x6,%xmm0,%xmm0 + 42b382: c4 e3 79 63 c0 3a vpcmpistri $0x3a,%xmm0,%xmm0 + 42b388: 83 f9 09 cmp $0x9,%ecx + 42b38b: 0f 87 39 ff ff ff ja 42b2ca <__strcasecmp_l_avx+0x90a> + 42b391: e9 cb 0b 00 00 jmpq 42bf61 <__strcasecmp_l_avx+0x15a1> + 42b396: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42b39d: 00 00 00 + 42b3a0: c5 e9 73 fa 09 vpslldq $0x9,%xmm2,%xmm2 + 42b3a5: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 + 42b3a9: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 + 42b3ad: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 + 42b3b1: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 + 42b3b5: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42b3b9: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42b3be: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42b3c2: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42b3c6: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 + 42b3ca: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 + 42b3ce: c5 e9 74 d1 vpcmpeqb %xmm1,%xmm2,%xmm2 + 42b3d2: c5 e9 f8 d0 vpsubb %xmm0,%xmm2,%xmm2 + 42b3d6: c5 79 d7 ca vpmovmskb %xmm2,%r9d + 42b3da: d3 ea shr %cl,%edx + 42b3dc: 41 d3 e9 shr %cl,%r9d + 42b3df: 44 29 ca sub %r9d,%edx + 42b3e2: 0f 85 e0 0b 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> + 42b3e8: c5 f9 6f 1f vmovdqa (%rdi),%xmm3 + 42b3ec: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42b3f3: 41 b9 07 00 00 00 mov $0x7,%r9d + 42b3f9: 4c 8d 57 07 lea 0x7(%rdi),%r10 + 42b3fd: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42b404: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42b40b: 48 89 ca mov %rcx,%rdx + 42b40e: 66 90 xchg %ax,%ax + 42b410: 49 83 c2 10 add $0x10,%r10 + 42b414: 0f 8f a6 00 00 00 jg 42b4c0 <__strcasecmp_l_avx+0xb00> + 42b41a: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42b41f: c4 e3 79 0f 44 17 f0 vpalignr $0x7,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 + 42b426: 07 + 42b427: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42b42c: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42b430: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42b434: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42b438: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42b43c: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42b440: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42b445: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42b449: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42b44d: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42b451: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42b455: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42b45b: 0f 86 3f 0b 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> + 42b461: 48 83 c2 10 add $0x10,%rdx + 42b465: 49 83 c2 10 add $0x10,%r10 + 42b469: 7f 55 jg 42b4c0 <__strcasecmp_l_avx+0xb00> + 42b46b: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42b470: c4 e3 79 0f 44 17 f0 vpalignr $0x7,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 + 42b477: 07 + 42b478: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42b47d: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42b481: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42b485: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42b489: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42b48d: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42b491: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42b496: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42b49a: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42b49e: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42b4a2: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42b4a6: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42b4ac: 0f 86 ee 0a 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> + 42b4b2: 48 83 c2 10 add $0x10,%rdx + 42b4b6: e9 55 ff ff ff jmpq 42b410 <__strcasecmp_l_avx+0xa50> + 42b4bb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 42b4c0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42b4c7: c5 f9 6f 44 17 f0 vmovdqa -0x10(%rdi,%rdx,1),%xmm0 + 42b4cd: c5 f9 73 d8 07 vpsrldq $0x7,%xmm0,%xmm0 + 42b4d2: c4 e3 79 63 c0 3a vpcmpistri $0x3a,%xmm0,%xmm0 + 42b4d8: 83 f9 08 cmp $0x8,%ecx + 42b4db: 0f 87 39 ff ff ff ja 42b41a <__strcasecmp_l_avx+0xa5a> + 42b4e1: e9 7b 0a 00 00 jmpq 42bf61 <__strcasecmp_l_avx+0x15a1> + 42b4e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42b4ed: 00 00 00 + 42b4f0: c5 e9 73 fa 08 vpslldq $0x8,%xmm2,%xmm2 + 42b4f5: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 + 42b4f9: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 + 42b4fd: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 + 42b501: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 + 42b505: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42b509: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42b50e: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42b512: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42b516: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 + 42b51a: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 + 42b51e: c5 e9 74 d1 vpcmpeqb %xmm1,%xmm2,%xmm2 + 42b522: c5 e9 f8 d0 vpsubb %xmm0,%xmm2,%xmm2 + 42b526: c5 79 d7 ca vpmovmskb %xmm2,%r9d + 42b52a: d3 ea shr %cl,%edx + 42b52c: 41 d3 e9 shr %cl,%r9d + 42b52f: 44 29 ca sub %r9d,%edx + 42b532: 0f 85 90 0a 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> + 42b538: c5 f9 6f 1f vmovdqa (%rdi),%xmm3 + 42b53c: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42b543: 41 b9 08 00 00 00 mov $0x8,%r9d + 42b549: 4c 8d 57 08 lea 0x8(%rdi),%r10 + 42b54d: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42b554: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42b55b: 48 89 ca mov %rcx,%rdx + 42b55e: 66 90 xchg %ax,%ax + 42b560: 49 83 c2 10 add $0x10,%r10 + 42b564: 0f 8f a6 00 00 00 jg 42b610 <__strcasecmp_l_avx+0xc50> + 42b56a: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42b56f: c4 e3 79 0f 44 17 f0 vpalignr $0x8,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 + 42b576: 08 + 42b577: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42b57c: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42b580: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42b584: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42b588: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42b58c: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42b590: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42b595: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42b599: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42b59d: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42b5a1: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42b5a5: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42b5ab: 0f 86 ef 09 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> + 42b5b1: 48 83 c2 10 add $0x10,%rdx + 42b5b5: 49 83 c2 10 add $0x10,%r10 + 42b5b9: 7f 55 jg 42b610 <__strcasecmp_l_avx+0xc50> + 42b5bb: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42b5c0: c4 e3 79 0f 44 17 f0 vpalignr $0x8,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 + 42b5c7: 08 + 42b5c8: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42b5cd: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42b5d1: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42b5d5: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42b5d9: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42b5dd: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42b5e1: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42b5e6: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42b5ea: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42b5ee: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42b5f2: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42b5f6: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42b5fc: 0f 86 9e 09 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> + 42b602: 48 83 c2 10 add $0x10,%rdx + 42b606: e9 55 ff ff ff jmpq 42b560 <__strcasecmp_l_avx+0xba0> + 42b60b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 42b610: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42b617: c5 f9 6f 44 17 f0 vmovdqa -0x10(%rdi,%rdx,1),%xmm0 + 42b61d: c5 f9 73 d8 08 vpsrldq $0x8,%xmm0,%xmm0 + 42b622: c4 e3 79 63 c0 3a vpcmpistri $0x3a,%xmm0,%xmm0 + 42b628: 83 f9 07 cmp $0x7,%ecx + 42b62b: 0f 87 39 ff ff ff ja 42b56a <__strcasecmp_l_avx+0xbaa> + 42b631: e9 2b 09 00 00 jmpq 42bf61 <__strcasecmp_l_avx+0x15a1> + 42b636: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42b63d: 00 00 00 + 42b640: c5 e9 73 fa 07 vpslldq $0x7,%xmm2,%xmm2 + 42b645: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 + 42b649: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 + 42b64d: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 + 42b651: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 + 42b655: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42b659: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42b65e: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42b662: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42b666: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 + 42b66a: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 + 42b66e: c5 e9 74 d1 vpcmpeqb %xmm1,%xmm2,%xmm2 + 42b672: c5 e9 f8 d0 vpsubb %xmm0,%xmm2,%xmm2 + 42b676: c5 79 d7 ca vpmovmskb %xmm2,%r9d + 42b67a: d3 ea shr %cl,%edx + 42b67c: 41 d3 e9 shr %cl,%r9d + 42b67f: 44 29 ca sub %r9d,%edx + 42b682: 0f 85 40 09 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> + 42b688: c5 f9 6f 1f vmovdqa (%rdi),%xmm3 + 42b68c: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42b693: 41 b9 09 00 00 00 mov $0x9,%r9d + 42b699: 4c 8d 57 09 lea 0x9(%rdi),%r10 + 42b69d: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42b6a4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42b6ab: 48 89 ca mov %rcx,%rdx + 42b6ae: 66 90 xchg %ax,%ax + 42b6b0: 49 83 c2 10 add $0x10,%r10 + 42b6b4: 0f 8f a6 00 00 00 jg 42b760 <__strcasecmp_l_avx+0xda0> + 42b6ba: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42b6bf: c4 e3 79 0f 44 17 f0 vpalignr $0x9,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 + 42b6c6: 09 + 42b6c7: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42b6cc: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42b6d0: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42b6d4: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42b6d8: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42b6dc: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42b6e0: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42b6e5: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42b6e9: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42b6ed: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42b6f1: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42b6f5: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42b6fb: 0f 86 9f 08 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> + 42b701: 48 83 c2 10 add $0x10,%rdx + 42b705: 49 83 c2 10 add $0x10,%r10 + 42b709: 7f 55 jg 42b760 <__strcasecmp_l_avx+0xda0> + 42b70b: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42b710: c4 e3 79 0f 44 17 f0 vpalignr $0x9,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 + 42b717: 09 + 42b718: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42b71d: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42b721: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42b725: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42b729: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42b72d: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42b731: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42b736: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42b73a: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42b73e: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42b742: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42b746: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42b74c: 0f 86 4e 08 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> + 42b752: 48 83 c2 10 add $0x10,%rdx + 42b756: e9 55 ff ff ff jmpq 42b6b0 <__strcasecmp_l_avx+0xcf0> + 42b75b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 42b760: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42b767: c5 f9 6f 44 17 f0 vmovdqa -0x10(%rdi,%rdx,1),%xmm0 + 42b76d: c5 f9 73 d8 09 vpsrldq $0x9,%xmm0,%xmm0 + 42b772: c4 e3 79 63 c0 3a vpcmpistri $0x3a,%xmm0,%xmm0 + 42b778: 83 f9 06 cmp $0x6,%ecx + 42b77b: 0f 87 39 ff ff ff ja 42b6ba <__strcasecmp_l_avx+0xcfa> + 42b781: e9 db 07 00 00 jmpq 42bf61 <__strcasecmp_l_avx+0x15a1> + 42b786: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42b78d: 00 00 00 + 42b790: c5 e9 73 fa 06 vpslldq $0x6,%xmm2,%xmm2 + 42b795: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 + 42b799: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 + 42b79d: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 + 42b7a1: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 + 42b7a5: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42b7a9: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42b7ae: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42b7b2: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42b7b6: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 + 42b7ba: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 + 42b7be: c5 e9 74 d1 vpcmpeqb %xmm1,%xmm2,%xmm2 + 42b7c2: c5 e9 f8 d0 vpsubb %xmm0,%xmm2,%xmm2 + 42b7c6: c5 79 d7 ca vpmovmskb %xmm2,%r9d + 42b7ca: d3 ea shr %cl,%edx + 42b7cc: 41 d3 e9 shr %cl,%r9d + 42b7cf: 44 29 ca sub %r9d,%edx + 42b7d2: 0f 85 f0 07 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> + 42b7d8: c5 f9 6f 1f vmovdqa (%rdi),%xmm3 + 42b7dc: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42b7e3: 41 b9 0a 00 00 00 mov $0xa,%r9d + 42b7e9: 4c 8d 57 0a lea 0xa(%rdi),%r10 + 42b7ed: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42b7f4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42b7fb: 48 89 ca mov %rcx,%rdx + 42b7fe: 66 90 xchg %ax,%ax + 42b800: 49 83 c2 10 add $0x10,%r10 + 42b804: 0f 8f a6 00 00 00 jg 42b8b0 <__strcasecmp_l_avx+0xef0> + 42b80a: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42b80f: c4 e3 79 0f 44 17 f0 vpalignr $0xa,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 + 42b816: 0a + 42b817: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42b81c: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42b820: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42b824: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42b828: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42b82c: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42b830: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42b835: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42b839: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42b83d: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42b841: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42b845: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42b84b: 0f 86 4f 07 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> + 42b851: 48 83 c2 10 add $0x10,%rdx + 42b855: 49 83 c2 10 add $0x10,%r10 + 42b859: 7f 55 jg 42b8b0 <__strcasecmp_l_avx+0xef0> + 42b85b: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42b860: c4 e3 79 0f 44 17 f0 vpalignr $0xa,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 + 42b867: 0a + 42b868: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42b86d: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42b871: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42b875: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42b879: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42b87d: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42b881: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42b886: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42b88a: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42b88e: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42b892: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42b896: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42b89c: 0f 86 fe 06 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> + 42b8a2: 48 83 c2 10 add $0x10,%rdx + 42b8a6: e9 55 ff ff ff jmpq 42b800 <__strcasecmp_l_avx+0xe40> + 42b8ab: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 42b8b0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42b8b7: c5 f9 6f 44 17 f0 vmovdqa -0x10(%rdi,%rdx,1),%xmm0 + 42b8bd: c5 f9 73 d8 0a vpsrldq $0xa,%xmm0,%xmm0 + 42b8c2: c4 e3 79 63 c0 3a vpcmpistri $0x3a,%xmm0,%xmm0 + 42b8c8: 83 f9 05 cmp $0x5,%ecx + 42b8cb: 0f 87 39 ff ff ff ja 42b80a <__strcasecmp_l_avx+0xe4a> + 42b8d1: e9 8b 06 00 00 jmpq 42bf61 <__strcasecmp_l_avx+0x15a1> + 42b8d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42b8dd: 00 00 00 + 42b8e0: c5 e9 73 fa 05 vpslldq $0x5,%xmm2,%xmm2 + 42b8e5: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 + 42b8e9: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 + 42b8ed: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 + 42b8f1: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 + 42b8f5: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42b8f9: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42b8fe: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42b902: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42b906: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 + 42b90a: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 + 42b90e: c5 e9 74 d1 vpcmpeqb %xmm1,%xmm2,%xmm2 + 42b912: c5 e9 f8 d0 vpsubb %xmm0,%xmm2,%xmm2 + 42b916: c5 79 d7 ca vpmovmskb %xmm2,%r9d + 42b91a: d3 ea shr %cl,%edx + 42b91c: 41 d3 e9 shr %cl,%r9d + 42b91f: 44 29 ca sub %r9d,%edx + 42b922: 0f 85 a0 06 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> + 42b928: c5 f9 6f 1f vmovdqa (%rdi),%xmm3 + 42b92c: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42b933: 41 b9 0b 00 00 00 mov $0xb,%r9d + 42b939: 4c 8d 57 0b lea 0xb(%rdi),%r10 + 42b93d: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42b944: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42b94b: 48 89 ca mov %rcx,%rdx + 42b94e: 66 90 xchg %ax,%ax + 42b950: 49 83 c2 10 add $0x10,%r10 + 42b954: 0f 8f a6 00 00 00 jg 42ba00 <__strcasecmp_l_avx+0x1040> + 42b95a: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42b95f: c4 e3 79 0f 44 17 f0 vpalignr $0xb,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 + 42b966: 0b + 42b967: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42b96c: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42b970: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42b974: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42b978: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42b97c: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42b980: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42b985: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42b989: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42b98d: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42b991: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42b995: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42b99b: 0f 86 ff 05 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> + 42b9a1: 48 83 c2 10 add $0x10,%rdx + 42b9a5: 49 83 c2 10 add $0x10,%r10 + 42b9a9: 7f 55 jg 42ba00 <__strcasecmp_l_avx+0x1040> + 42b9ab: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42b9b0: c4 e3 79 0f 44 17 f0 vpalignr $0xb,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 + 42b9b7: 0b + 42b9b8: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42b9bd: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42b9c1: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42b9c5: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42b9c9: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42b9cd: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42b9d1: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42b9d6: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42b9da: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42b9de: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42b9e2: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42b9e6: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42b9ec: 0f 86 ae 05 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> + 42b9f2: 48 83 c2 10 add $0x10,%rdx + 42b9f6: e9 55 ff ff ff jmpq 42b950 <__strcasecmp_l_avx+0xf90> + 42b9fb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 42ba00: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42ba07: c5 f9 6f 44 17 f0 vmovdqa -0x10(%rdi,%rdx,1),%xmm0 + 42ba0d: c5 f9 73 d8 0b vpsrldq $0xb,%xmm0,%xmm0 + 42ba12: c4 e3 79 63 c0 3a vpcmpistri $0x3a,%xmm0,%xmm0 + 42ba18: 83 f9 04 cmp $0x4,%ecx + 42ba1b: 0f 87 39 ff ff ff ja 42b95a <__strcasecmp_l_avx+0xf9a> + 42ba21: e9 3b 05 00 00 jmpq 42bf61 <__strcasecmp_l_avx+0x15a1> + 42ba26: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42ba2d: 00 00 00 + 42ba30: c5 e9 73 fa 04 vpslldq $0x4,%xmm2,%xmm2 + 42ba35: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 + 42ba39: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 + 42ba3d: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 + 42ba41: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 + 42ba45: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42ba49: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42ba4e: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42ba52: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42ba56: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 + 42ba5a: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 + 42ba5e: c5 e9 74 d1 vpcmpeqb %xmm1,%xmm2,%xmm2 + 42ba62: c5 e9 f8 d0 vpsubb %xmm0,%xmm2,%xmm2 + 42ba66: c5 79 d7 ca vpmovmskb %xmm2,%r9d + 42ba6a: d3 ea shr %cl,%edx + 42ba6c: 41 d3 e9 shr %cl,%r9d + 42ba6f: 44 29 ca sub %r9d,%edx + 42ba72: 0f 85 50 05 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> + 42ba78: c5 f9 6f 1f vmovdqa (%rdi),%xmm3 + 42ba7c: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42ba83: 41 b9 0c 00 00 00 mov $0xc,%r9d + 42ba89: 4c 8d 57 0c lea 0xc(%rdi),%r10 + 42ba8d: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42ba94: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42ba9b: 48 89 ca mov %rcx,%rdx + 42ba9e: 66 90 xchg %ax,%ax + 42baa0: 49 83 c2 10 add $0x10,%r10 + 42baa4: 0f 8f a6 00 00 00 jg 42bb50 <__strcasecmp_l_avx+0x1190> + 42baaa: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42baaf: c4 e3 79 0f 44 17 f0 vpalignr $0xc,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 + 42bab6: 0c + 42bab7: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42babc: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42bac0: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42bac4: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42bac8: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42bacc: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42bad0: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42bad5: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42bad9: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42badd: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42bae1: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42bae5: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42baeb: 0f 86 af 04 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> + 42baf1: 48 83 c2 10 add $0x10,%rdx + 42baf5: 49 83 c2 10 add $0x10,%r10 + 42baf9: 7f 55 jg 42bb50 <__strcasecmp_l_avx+0x1190> + 42bafb: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42bb00: c4 e3 79 0f 44 17 f0 vpalignr $0xc,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 + 42bb07: 0c + 42bb08: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42bb0d: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42bb11: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42bb15: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42bb19: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42bb1d: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42bb21: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42bb26: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42bb2a: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42bb2e: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42bb32: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42bb36: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42bb3c: 0f 86 5e 04 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> + 42bb42: 48 83 c2 10 add $0x10,%rdx + 42bb46: e9 55 ff ff ff jmpq 42baa0 <__strcasecmp_l_avx+0x10e0> + 42bb4b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 42bb50: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42bb57: c5 f9 6f 44 17 f0 vmovdqa -0x10(%rdi,%rdx,1),%xmm0 + 42bb5d: c5 f9 73 d8 0c vpsrldq $0xc,%xmm0,%xmm0 + 42bb62: c4 e3 79 63 c0 3a vpcmpistri $0x3a,%xmm0,%xmm0 + 42bb68: 83 f9 03 cmp $0x3,%ecx + 42bb6b: 0f 87 39 ff ff ff ja 42baaa <__strcasecmp_l_avx+0x10ea> + 42bb71: e9 eb 03 00 00 jmpq 42bf61 <__strcasecmp_l_avx+0x15a1> + 42bb76: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42bb7d: 00 00 00 + 42bb80: c5 e9 73 fa 03 vpslldq $0x3,%xmm2,%xmm2 + 42bb85: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 + 42bb89: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 + 42bb8d: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 + 42bb91: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 + 42bb95: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42bb99: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42bb9e: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42bba2: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42bba6: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 + 42bbaa: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 + 42bbae: c5 e9 74 d1 vpcmpeqb %xmm1,%xmm2,%xmm2 + 42bbb2: c5 e9 f8 d0 vpsubb %xmm0,%xmm2,%xmm2 + 42bbb6: c5 79 d7 ca vpmovmskb %xmm2,%r9d + 42bbba: d3 ea shr %cl,%edx + 42bbbc: 41 d3 e9 shr %cl,%r9d + 42bbbf: 44 29 ca sub %r9d,%edx + 42bbc2: 0f 85 00 04 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> + 42bbc8: c5 f9 6f 1f vmovdqa (%rdi),%xmm3 + 42bbcc: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42bbd3: 41 b9 0d 00 00 00 mov $0xd,%r9d + 42bbd9: 4c 8d 57 0d lea 0xd(%rdi),%r10 + 42bbdd: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42bbe4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42bbeb: 48 89 ca mov %rcx,%rdx + 42bbee: 66 90 xchg %ax,%ax + 42bbf0: 49 83 c2 10 add $0x10,%r10 + 42bbf4: 0f 8f a6 00 00 00 jg 42bca0 <__strcasecmp_l_avx+0x12e0> + 42bbfa: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42bbff: c4 e3 79 0f 44 17 f0 vpalignr $0xd,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 + 42bc06: 0d + 42bc07: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42bc0c: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42bc10: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42bc14: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42bc18: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42bc1c: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42bc20: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42bc25: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42bc29: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42bc2d: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42bc31: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42bc35: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42bc3b: 0f 86 5f 03 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> + 42bc41: 48 83 c2 10 add $0x10,%rdx + 42bc45: 49 83 c2 10 add $0x10,%r10 + 42bc49: 7f 55 jg 42bca0 <__strcasecmp_l_avx+0x12e0> + 42bc4b: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42bc50: c4 e3 79 0f 44 17 f0 vpalignr $0xd,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 + 42bc57: 0d + 42bc58: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42bc5d: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42bc61: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42bc65: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42bc69: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42bc6d: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42bc71: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42bc76: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42bc7a: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42bc7e: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42bc82: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42bc86: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42bc8c: 0f 86 0e 03 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> + 42bc92: 48 83 c2 10 add $0x10,%rdx + 42bc96: e9 55 ff ff ff jmpq 42bbf0 <__strcasecmp_l_avx+0x1230> + 42bc9b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 42bca0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42bca7: c5 f9 6f 44 17 f0 vmovdqa -0x10(%rdi,%rdx,1),%xmm0 + 42bcad: c5 f9 73 d8 0d vpsrldq $0xd,%xmm0,%xmm0 + 42bcb2: c4 e3 79 63 c0 3a vpcmpistri $0x3a,%xmm0,%xmm0 + 42bcb8: 83 f9 02 cmp $0x2,%ecx + 42bcbb: 0f 87 39 ff ff ff ja 42bbfa <__strcasecmp_l_avx+0x123a> + 42bcc1: e9 9b 02 00 00 jmpq 42bf61 <__strcasecmp_l_avx+0x15a1> + 42bcc6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42bccd: 00 00 00 + 42bcd0: c5 e9 73 fa 02 vpslldq $0x2,%xmm2,%xmm2 + 42bcd5: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 + 42bcd9: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 + 42bcdd: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 + 42bce1: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 + 42bce5: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42bce9: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42bcee: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42bcf2: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42bcf6: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 + 42bcfa: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 + 42bcfe: c5 e9 74 d1 vpcmpeqb %xmm1,%xmm2,%xmm2 + 42bd02: c5 e9 f8 d0 vpsubb %xmm0,%xmm2,%xmm2 + 42bd06: c5 79 d7 ca vpmovmskb %xmm2,%r9d + 42bd0a: d3 ea shr %cl,%edx + 42bd0c: 41 d3 e9 shr %cl,%r9d + 42bd0f: 44 29 ca sub %r9d,%edx + 42bd12: 0f 85 b0 02 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> + 42bd18: c5 f9 6f 1f vmovdqa (%rdi),%xmm3 + 42bd1c: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42bd23: 41 b9 0e 00 00 00 mov $0xe,%r9d + 42bd29: 4c 8d 57 0e lea 0xe(%rdi),%r10 + 42bd2d: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42bd34: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42bd3b: 48 89 ca mov %rcx,%rdx + 42bd3e: 66 90 xchg %ax,%ax + 42bd40: 49 83 c2 10 add $0x10,%r10 + 42bd44: 0f 8f a6 00 00 00 jg 42bdf0 <__strcasecmp_l_avx+0x1430> + 42bd4a: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42bd4f: c4 e3 79 0f 44 17 f0 vpalignr $0xe,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 + 42bd56: 0e + 42bd57: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42bd5c: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42bd60: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42bd64: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42bd68: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42bd6c: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42bd70: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42bd75: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42bd79: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42bd7d: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42bd81: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42bd85: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42bd8b: 0f 86 0f 02 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> + 42bd91: 48 83 c2 10 add $0x10,%rdx + 42bd95: 49 83 c2 10 add $0x10,%r10 + 42bd99: 7f 55 jg 42bdf0 <__strcasecmp_l_avx+0x1430> + 42bd9b: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42bda0: c4 e3 79 0f 44 17 f0 vpalignr $0xe,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 + 42bda7: 0e + 42bda8: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42bdad: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42bdb1: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42bdb5: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42bdb9: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42bdbd: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42bdc1: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42bdc6: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42bdca: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42bdce: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42bdd2: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42bdd6: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42bddc: 0f 86 be 01 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> + 42bde2: 48 83 c2 10 add $0x10,%rdx + 42bde6: e9 55 ff ff ff jmpq 42bd40 <__strcasecmp_l_avx+0x1380> + 42bdeb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 42bdf0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42bdf7: c5 f9 6f 44 17 f0 vmovdqa -0x10(%rdi,%rdx,1),%xmm0 + 42bdfd: c5 f9 73 d8 0e vpsrldq $0xe,%xmm0,%xmm0 + 42be02: c4 e3 79 63 c0 3a vpcmpistri $0x3a,%xmm0,%xmm0 + 42be08: 83 f9 01 cmp $0x1,%ecx + 42be0b: 0f 87 39 ff ff ff ja 42bd4a <__strcasecmp_l_avx+0x138a> + 42be11: e9 4b 01 00 00 jmpq 42bf61 <__strcasecmp_l_avx+0x15a1> + 42be16: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42be1d: 00 00 00 + 42be20: c5 e9 73 fa 01 vpslldq $0x1,%xmm2,%xmm2 + 42be25: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 + 42be29: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 + 42be2d: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 + 42be31: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 + 42be35: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42be39: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42be3e: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42be42: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42be46: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 + 42be4a: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 + 42be4e: c5 e9 74 d1 vpcmpeqb %xmm1,%xmm2,%xmm2 + 42be52: c5 e9 f8 d0 vpsubb %xmm0,%xmm2,%xmm2 + 42be56: c5 79 d7 ca vpmovmskb %xmm2,%r9d + 42be5a: d3 ea shr %cl,%edx + 42be5c: 41 d3 e9 shr %cl,%r9d + 42be5f: 44 29 ca sub %r9d,%edx + 42be62: 0f 85 60 01 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> + 42be68: c5 f9 6f 1f vmovdqa (%rdi),%xmm3 + 42be6c: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42be73: 41 b9 0f 00 00 00 mov $0xf,%r9d + 42be79: 4c 8d 57 0f lea 0xf(%rdi),%r10 + 42be7d: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42be84: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42be8b: 48 89 ca mov %rcx,%rdx + 42be8e: 66 90 xchg %ax,%ax + 42be90: 49 83 c2 10 add $0x10,%r10 + 42be94: 0f 8f a6 00 00 00 jg 42bf40 <__strcasecmp_l_avx+0x1580> + 42be9a: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42be9f: c4 e3 79 0f 44 17 f0 vpalignr $0xf,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 + 42bea6: 0f + 42bea7: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42beac: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42beb0: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42beb4: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42beb8: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42bebc: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42bec0: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42bec5: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42bec9: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42becd: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42bed1: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42bed5: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42bedb: 0f 86 bf 00 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> + 42bee1: 48 83 c2 10 add $0x10,%rdx + 42bee5: 49 83 c2 10 add $0x10,%r10 + 42bee9: 7f 55 jg 42bf40 <__strcasecmp_l_avx+0x1580> + 42beeb: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 + 42bef0: c4 e3 79 0f 44 17 f0 vpalignr $0xf,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 + 42bef7: 0f + 42bef8: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42befd: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42bf01: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42bf05: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42bf09: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42bf0d: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42bf11: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42bf16: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42bf1a: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42bf1e: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42bf22: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42bf26: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42bf2c: 76 72 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> + 42bf2e: 48 83 c2 10 add $0x10,%rdx + 42bf32: e9 59 ff ff ff jmpq 42be90 <__strcasecmp_l_avx+0x14d0> + 42bf37: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 42bf3e: 00 00 + 42bf40: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42bf47: c5 f9 6f 44 17 f0 vmovdqa -0x10(%rdi,%rdx,1),%xmm0 + 42bf4d: c5 f9 73 d8 0f vpsrldq $0xf,%xmm0,%xmm0 + 42bf52: c4 e3 79 63 c0 3a vpcmpistri $0x3a,%xmm0,%xmm0 + 42bf58: 83 f9 00 cmp $0x0,%ecx + 42bf5b: 0f 87 39 ff ff ff ja 42be9a <__strcasecmp_l_avx+0x14da> + 42bf61: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 + 42bf66: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 + 42bf6a: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 + 42bf6e: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 + 42bf72: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 + 42bf76: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 + 42bf7a: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 + 42bf7f: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 + 42bf83: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 + 42bf87: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 + 42bf8b: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 + 42bf8f: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 + 42bf95: 90 nop + 42bf96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42bf9d: 00 00 00 + 42bfa0: 73 5a jae 42bffc <__strcasecmp_l_avx+0x163c> + 42bfa2: 48 01 ca add %rcx,%rdx + 42bfa5: 4a 8d 7c 0f f0 lea -0x10(%rdi,%r9,1),%rdi + 42bfaa: 0f b6 04 17 movzbl (%rdi,%rdx,1),%eax + 42bfae: 0f b6 14 16 movzbl (%rsi,%rdx,1),%edx + 42bfb2: 45 85 c0 test %r8d,%r8d + 42bfb5: 74 01 je 42bfb8 <__strcasecmp_l_avx+0x15f8> + 42bfb7: 92 xchg %eax,%edx + 42bfb8: 48 8d 0d 81 b5 07 00 lea 0x7b581(%rip),%rcx # 4a7540 <_nl_C_LC_CTYPE_tolower+0x200> + 42bfbf: 8b 14 91 mov (%rcx,%rdx,4),%edx + 42bfc2: 8b 04 81 mov (%rcx,%rax,4),%eax + 42bfc5: 29 d0 sub %edx,%eax + 42bfc7: c3 retq + 42bfc8: 48 8d 3c 07 lea (%rdi,%rax,1),%rdi + 42bfcc: 48 8d 34 0e lea (%rsi,%rcx,1),%rsi + 42bfd0: 45 85 c0 test %r8d,%r8d + 42bfd3: 74 0b je 42bfe0 <__strcasecmp_l_avx+0x1620> + 42bfd5: 48 87 f7 xchg %rsi,%rdi + 42bfd8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 42bfdf: 00 + 42bfe0: 48 0f bc d2 bsf %rdx,%rdx + 42bfe4: 0f b6 0c 16 movzbl (%rsi,%rdx,1),%ecx + 42bfe8: 0f b6 04 17 movzbl (%rdi,%rdx,1),%eax + 42bfec: 48 8d 15 4d b5 07 00 lea 0x7b54d(%rip),%rdx # 4a7540 <_nl_C_LC_CTYPE_tolower+0x200> + 42bff3: 8b 0c 8a mov (%rdx,%rcx,4),%ecx + 42bff6: 8b 04 82 mov (%rdx,%rax,4),%eax + 42bff9: 29 c8 sub %ecx,%eax + 42bffb: c3 retq + 42bffc: 31 c0 xor %eax,%eax + 42bffe: c3 retq + 42bfff: 90 nop + 42c000: 0f b6 0e movzbl (%rsi),%ecx + 42c003: 0f b6 07 movzbl (%rdi),%eax + 42c006: 48 8d 15 33 b5 07 00 lea 0x7b533(%rip),%rdx # 4a7540 <_nl_C_LC_CTYPE_tolower+0x200> + 42c00d: 8b 0c 8a mov (%rdx,%rcx,4),%ecx + 42c010: 8b 04 82 mov (%rdx,%rax,4),%eax + 42c013: 29 c8 sub %ecx,%eax + 42c015: c3 retq + 42c016: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42c01d: 00 00 00 + +000000000042c020 : + 42c020: 48 83 fa 20 cmp $0x20,%rdx + 42c024: 48 89 f8 mov %rdi,%rax + 42c027: 73 77 jae 42c0a0 + 42c029: f6 c2 01 test $0x1,%dl + 42c02c: 74 0b je 42c039 + 42c02e: 0f b6 0e movzbl (%rsi),%ecx + 42c031: 88 0f mov %cl,(%rdi) + 42c033: 48 ff c6 inc %rsi + 42c036: 48 ff c7 inc %rdi + 42c039: f6 c2 02 test $0x2,%dl + 42c03c: 74 12 je 42c050 + 42c03e: 0f b7 0e movzwl (%rsi),%ecx + 42c041: 66 89 0f mov %cx,(%rdi) + 42c044: 48 83 c6 02 add $0x2,%rsi + 42c048: 48 83 c7 02 add $0x2,%rdi + 42c04c: 0f 1f 40 00 nopl 0x0(%rax) + 42c050: f6 c2 04 test $0x4,%dl + 42c053: 74 0c je 42c061 + 42c055: 8b 0e mov (%rsi),%ecx + 42c057: 89 0f mov %ecx,(%rdi) + 42c059: 48 83 c6 04 add $0x4,%rsi + 42c05d: 48 83 c7 04 add $0x4,%rdi + 42c061: f6 c2 08 test $0x8,%dl + 42c064: 74 0e je 42c074 + 42c066: 48 8b 0e mov (%rsi),%rcx + 42c069: 48 89 0f mov %rcx,(%rdi) + 42c06c: 48 83 c6 08 add $0x8,%rsi + 42c070: 48 83 c7 08 add $0x8,%rdi + 42c074: 81 e2 f0 00 00 00 and $0xf0,%edx + 42c07a: 74 1f je 42c09b + 42c07c: 0f 1f 40 00 nopl 0x0(%rax) + 42c080: 48 8b 0e mov (%rsi),%rcx + 42c083: 4c 8b 46 08 mov 0x8(%rsi),%r8 + 42c087: 48 89 0f mov %rcx,(%rdi) + 42c08a: 4c 89 47 08 mov %r8,0x8(%rdi) + 42c08e: 83 ea 10 sub $0x10,%edx + 42c091: 48 8d 76 10 lea 0x10(%rsi),%rsi + 42c095: 48 8d 7f 10 lea 0x10(%rdi),%rdi + 42c099: 75 e5 jne 42c080 + 42c09b: f3 c3 repz retq + 42c09d: 0f 1f 00 nopl (%rax) + 42c0a0: 48 89 44 24 f8 mov %rax,-0x8(%rsp) + 42c0a5: 89 f1 mov %esi,%ecx + 42c0a7: 83 e1 07 and $0x7,%ecx + 42c0aa: 74 34 je 42c0e0 + 42c0ac: 48 8d 54 11 f8 lea -0x8(%rcx,%rdx,1),%rdx + 42c0b1: 83 e9 08 sub $0x8,%ecx + 42c0b4: 66 90 xchg %ax,%ax + 42c0b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42c0bd: 00 00 00 + 42c0c0: 0f b6 06 movzbl (%rsi),%eax + 42c0c3: 88 07 mov %al,(%rdi) + 42c0c5: ff c1 inc %ecx + 42c0c7: 48 8d 76 01 lea 0x1(%rsi),%rsi + 42c0cb: 48 8d 7f 01 lea 0x1(%rdi),%rdi + 42c0cf: 75 ef jne 42c0c0 + 42c0d1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 42c0d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42c0dd: 00 00 00 + 42c0e0: 48 81 fa 00 04 00 00 cmp $0x400,%rdx + 42c0e7: 77 77 ja 42c160 + 42c0e9: 89 d1 mov %edx,%ecx + 42c0eb: c1 e9 05 shr $0x5,%ecx + 42c0ee: 74 60 je 42c150 + 42c0f0: ff c9 dec %ecx + 42c0f2: 48 8b 06 mov (%rsi),%rax + 42c0f5: 4c 8b 46 08 mov 0x8(%rsi),%r8 + 42c0f9: 4c 8b 4e 10 mov 0x10(%rsi),%r9 + 42c0fd: 4c 8b 56 18 mov 0x18(%rsi),%r10 + 42c101: 48 89 07 mov %rax,(%rdi) + 42c104: 4c 89 47 08 mov %r8,0x8(%rdi) + 42c108: 4c 89 4f 10 mov %r9,0x10(%rdi) + 42c10c: 4c 89 57 18 mov %r10,0x18(%rdi) + 42c110: 48 8d 76 20 lea 0x20(%rsi),%rsi + 42c114: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 42c118: 74 36 je 42c150 + 42c11a: ff c9 dec %ecx + 42c11c: 48 8b 06 mov (%rsi),%rax + 42c11f: 4c 8b 46 08 mov 0x8(%rsi),%r8 + 42c123: 4c 8b 4e 10 mov 0x10(%rsi),%r9 + 42c127: 4c 8b 56 18 mov 0x18(%rsi),%r10 + 42c12b: 48 89 07 mov %rax,(%rdi) + 42c12e: 4c 89 47 08 mov %r8,0x8(%rdi) + 42c132: 4c 89 4f 10 mov %r9,0x10(%rdi) + 42c136: 4c 89 57 18 mov %r10,0x18(%rdi) + 42c13a: 48 8d 76 20 lea 0x20(%rsi),%rsi + 42c13e: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 42c142: 75 ac jne 42c0f0 + 42c144: 66 90 xchg %ax,%ax + 42c146: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42c14d: 00 00 00 + 42c150: 83 e2 1f and $0x1f,%edx + 42c153: 48 8b 44 24 f8 mov -0x8(%rsp),%rax + 42c158: 0f 85 cb fe ff ff jne 42c029 + 42c15e: f3 c3 repz retq + 42c160: 4c 8b 1d 69 ef 29 00 mov 0x29ef69(%rip),%r11 # 6cb0d0 <__x86_data_cache_size_half> + 42c167: 49 39 d3 cmp %rdx,%r11 + 42c16a: 4c 0f 47 da cmova %rdx,%r11 + 42c16e: 4c 89 d9 mov %r11,%rcx + 42c171: 49 83 e3 f8 and $0xfffffffffffffff8,%r11 + 42c175: 48 c1 e9 03 shr $0x3,%rcx + 42c179: 74 05 je 42c180 + 42c17b: f3 48 a5 rep movsq %ds:(%rsi),%es:(%rdi) + 42c17e: 66 90 xchg %ax,%ax + 42c180: 4c 29 da sub %r11,%rdx + 42c183: 48 f7 c2 f8 ff ff ff test $0xfffffffffffffff8,%rdx + 42c18a: 75 14 jne 42c1a0 + 42c18c: 83 e2 07 and $0x7,%edx + 42c18f: 48 8b 44 24 f8 mov -0x8(%rsp),%rax + 42c194: 0f 85 8f fe ff ff jne 42c029 + 42c19a: f3 c3 repz retq + 42c19c: 0f 1f 40 00 nopl 0x0(%rax) + 42c1a0: 4c 8b 05 09 ef 29 00 mov 0x29ef09(%rip),%r8 # 6cb0b0 <__x86_shared_cache_size_half> + 42c1a7: 49 39 d0 cmp %rdx,%r8 + 42c1aa: 4c 0f 47 c2 cmova %rdx,%r8 + 42c1ae: 4c 89 c1 mov %r8,%rcx + 42c1b1: 49 83 e0 c0 and $0xffffffffffffffc0,%r8 + 42c1b5: 48 c1 e9 06 shr $0x6,%rcx + 42c1b9: 0f 84 ab 01 00 00 je 42c36a + 42c1bf: 4c 89 74 24 f0 mov %r14,-0x10(%rsp) + 42c1c4: 4c 89 6c 24 e8 mov %r13,-0x18(%rsp) + 42c1c9: 4c 89 64 24 e0 mov %r12,-0x20(%rsp) + 42c1ce: 48 89 5c 24 d8 mov %rbx,-0x28(%rsp) + 42c1d3: 83 3d de 0f 2a 00 00 cmpl $0x0,0x2a0fde(%rip) # 6cd1b8 <__x86_prefetchw> + 42c1da: 0f 84 c0 00 00 00 je 42c2a0 + 42c1e0: 48 ff c9 dec %rcx + 42c1e3: 48 8b 06 mov (%rsi),%rax + 42c1e6: 48 8b 5e 08 mov 0x8(%rsi),%rbx + 42c1ea: 4c 8b 4e 10 mov 0x10(%rsi),%r9 + 42c1ee: 4c 8b 56 18 mov 0x18(%rsi),%r10 + 42c1f2: 4c 8b 5e 20 mov 0x20(%rsi),%r11 + 42c1f6: 4c 8b 66 28 mov 0x28(%rsi),%r12 + 42c1fa: 4c 8b 6e 30 mov 0x30(%rsi),%r13 + 42c1fe: 4c 8b 76 38 mov 0x38(%rsi),%r14 + 42c202: 0f 18 8e 80 03 00 00 prefetcht0 0x380(%rsi) + 42c209: 0f 18 8e c0 03 00 00 prefetcht0 0x3c0(%rsi) + 42c210: 48 89 07 mov %rax,(%rdi) + 42c213: 48 89 5f 08 mov %rbx,0x8(%rdi) + 42c217: 4c 89 4f 10 mov %r9,0x10(%rdi) + 42c21b: 4c 89 57 18 mov %r10,0x18(%rdi) + 42c21f: 4c 89 5f 20 mov %r11,0x20(%rdi) + 42c223: 4c 89 67 28 mov %r12,0x28(%rdi) + 42c227: 4c 89 6f 30 mov %r13,0x30(%rdi) + 42c22b: 4c 89 77 38 mov %r14,0x38(%rdi) + 42c22f: 48 8d 76 40 lea 0x40(%rsi),%rsi + 42c233: 48 8d 7f 40 lea 0x40(%rdi),%rdi + 42c237: 0f 84 19 01 00 00 je 42c356 + 42c23d: 48 ff c9 dec %rcx + 42c240: 48 8b 06 mov (%rsi),%rax + 42c243: 48 8b 5e 08 mov 0x8(%rsi),%rbx + 42c247: 4c 8b 4e 10 mov 0x10(%rsi),%r9 + 42c24b: 4c 8b 56 18 mov 0x18(%rsi),%r10 + 42c24f: 4c 8b 5e 20 mov 0x20(%rsi),%r11 + 42c253: 4c 8b 66 28 mov 0x28(%rsi),%r12 + 42c257: 4c 8b 6e 30 mov 0x30(%rsi),%r13 + 42c25b: 4c 8b 76 38 mov 0x38(%rsi),%r14 + 42c25f: 48 89 07 mov %rax,(%rdi) + 42c262: 48 89 5f 08 mov %rbx,0x8(%rdi) + 42c266: 4c 89 4f 10 mov %r9,0x10(%rdi) + 42c26a: 4c 89 57 18 mov %r10,0x18(%rdi) + 42c26e: 4c 89 5f 20 mov %r11,0x20(%rdi) + 42c272: 4c 89 67 28 mov %r12,0x28(%rdi) + 42c276: 4c 89 6f 30 mov %r13,0x30(%rdi) + 42c27a: 4c 89 77 38 mov %r14,0x38(%rdi) + 42c27e: 0f 0d 8f 40 03 00 00 prefetchw 0x340(%rdi) + 42c285: 0f 0d 8f 80 03 00 00 prefetchw 0x380(%rdi) + 42c28c: 48 8d 76 40 lea 0x40(%rsi),%rsi + 42c290: 48 8d 7f 40 lea 0x40(%rdi),%rdi + 42c294: 0f 85 46 ff ff ff jne 42c1e0 + 42c29a: e9 b7 00 00 00 jmpq 42c356 + 42c29f: 90 nop + 42c2a0: 48 ff c9 dec %rcx + 42c2a3: 48 8b 06 mov (%rsi),%rax + 42c2a6: 48 8b 5e 08 mov 0x8(%rsi),%rbx + 42c2aa: 4c 8b 4e 10 mov 0x10(%rsi),%r9 + 42c2ae: 4c 8b 56 18 mov 0x18(%rsi),%r10 + 42c2b2: 4c 8b 5e 20 mov 0x20(%rsi),%r11 + 42c2b6: 4c 8b 66 28 mov 0x28(%rsi),%r12 + 42c2ba: 4c 8b 6e 30 mov 0x30(%rsi),%r13 + 42c2be: 4c 8b 76 38 mov 0x38(%rsi),%r14 + 42c2c2: 0f 18 8e 80 03 00 00 prefetcht0 0x380(%rsi) + 42c2c9: 0f 18 8e c0 03 00 00 prefetcht0 0x3c0(%rsi) + 42c2d0: 48 89 07 mov %rax,(%rdi) + 42c2d3: 48 89 5f 08 mov %rbx,0x8(%rdi) + 42c2d7: 4c 89 4f 10 mov %r9,0x10(%rdi) + 42c2db: 4c 89 57 18 mov %r10,0x18(%rdi) + 42c2df: 4c 89 5f 20 mov %r11,0x20(%rdi) + 42c2e3: 4c 89 67 28 mov %r12,0x28(%rdi) + 42c2e7: 4c 89 6f 30 mov %r13,0x30(%rdi) + 42c2eb: 4c 89 77 38 mov %r14,0x38(%rdi) + 42c2ef: 48 8d 76 40 lea 0x40(%rsi),%rsi + 42c2f3: 48 8d 7f 40 lea 0x40(%rdi),%rdi + 42c2f7: 74 5d je 42c356 + 42c2f9: 48 ff c9 dec %rcx + 42c2fc: 48 8b 06 mov (%rsi),%rax + 42c2ff: 48 8b 5e 08 mov 0x8(%rsi),%rbx + 42c303: 4c 8b 4e 10 mov 0x10(%rsi),%r9 + 42c307: 4c 8b 56 18 mov 0x18(%rsi),%r10 + 42c30b: 4c 8b 5e 20 mov 0x20(%rsi),%r11 + 42c30f: 4c 8b 66 28 mov 0x28(%rsi),%r12 + 42c313: 4c 8b 6e 30 mov 0x30(%rsi),%r13 + 42c317: 4c 8b 76 38 mov 0x38(%rsi),%r14 + 42c31b: 0f 18 8f 40 03 00 00 prefetcht0 0x340(%rdi) + 42c322: 0f 18 8f 80 03 00 00 prefetcht0 0x380(%rdi) + 42c329: 48 89 07 mov %rax,(%rdi) + 42c32c: 48 89 5f 08 mov %rbx,0x8(%rdi) + 42c330: 4c 89 4f 10 mov %r9,0x10(%rdi) + 42c334: 4c 89 57 18 mov %r10,0x18(%rdi) + 42c338: 4c 89 5f 20 mov %r11,0x20(%rdi) + 42c33c: 4c 89 67 28 mov %r12,0x28(%rdi) + 42c340: 4c 89 6f 30 mov %r13,0x30(%rdi) + 42c344: 4c 89 77 38 mov %r14,0x38(%rdi) + 42c348: 48 8d 76 40 lea 0x40(%rsi),%rsi + 42c34c: 48 8d 7f 40 lea 0x40(%rdi),%rdi + 42c350: 0f 85 4a ff ff ff jne 42c2a0 + 42c356: 48 8b 5c 24 d8 mov -0x28(%rsp),%rbx + 42c35b: 4c 8b 64 24 e0 mov -0x20(%rsp),%r12 + 42c360: 4c 8b 6c 24 e8 mov -0x18(%rsp),%r13 + 42c365: 4c 8b 74 24 f0 mov -0x10(%rsp),%r14 + 42c36a: 4c 29 c2 sub %r8,%rdx + 42c36d: 48 f7 c2 c0 ff ff ff test $0xffffffffffffffc0,%rdx + 42c374: 75 1a jne 42c390 + 42c376: 83 e2 3f and $0x3f,%edx + 42c379: 48 8b 44 24 f8 mov -0x8(%rsp),%rax + 42c37e: 0f 85 a5 fc ff ff jne 42c029 + 42c384: f3 c3 repz retq + 42c386: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42c38d: 00 00 00 + 42c390: 48 89 d1 mov %rdx,%rcx + 42c393: 48 c1 e9 07 shr $0x7,%rcx + 42c397: 0f 84 d8 00 00 00 je 42c475 + 42c39d: 4c 89 74 24 f0 mov %r14,-0x10(%rsp) + 42c3a2: 4c 89 6c 24 e8 mov %r13,-0x18(%rsp) + 42c3a7: 4c 89 64 24 e0 mov %r12,-0x20(%rsp) + 42c3ac: 0f 1f 40 00 nopl 0x0(%rax) + 42c3b0: 0f 18 86 00 03 00 00 prefetchnta 0x300(%rsi) + 42c3b7: 0f 18 86 40 03 00 00 prefetchnta 0x340(%rsi) + 42c3be: 48 ff c9 dec %rcx + 42c3c1: 48 8b 06 mov (%rsi),%rax + 42c3c4: 4c 8b 46 08 mov 0x8(%rsi),%r8 + 42c3c8: 4c 8b 4e 10 mov 0x10(%rsi),%r9 + 42c3cc: 4c 8b 56 18 mov 0x18(%rsi),%r10 + 42c3d0: 4c 8b 5e 20 mov 0x20(%rsi),%r11 + 42c3d4: 4c 8b 66 28 mov 0x28(%rsi),%r12 + 42c3d8: 4c 8b 6e 30 mov 0x30(%rsi),%r13 + 42c3dc: 4c 8b 76 38 mov 0x38(%rsi),%r14 + 42c3e0: 48 0f c3 07 movnti %rax,(%rdi) + 42c3e4: 4c 0f c3 47 08 movnti %r8,0x8(%rdi) + 42c3e9: 4c 0f c3 4f 10 movnti %r9,0x10(%rdi) + 42c3ee: 4c 0f c3 57 18 movnti %r10,0x18(%rdi) + 42c3f3: 4c 0f c3 5f 20 movnti %r11,0x20(%rdi) + 42c3f8: 4c 0f c3 67 28 movnti %r12,0x28(%rdi) + 42c3fd: 4c 0f c3 6f 30 movnti %r13,0x30(%rdi) + 42c402: 4c 0f c3 77 38 movnti %r14,0x38(%rdi) + 42c407: 48 8b 46 40 mov 0x40(%rsi),%rax + 42c40b: 4c 8b 46 48 mov 0x48(%rsi),%r8 + 42c40f: 4c 8b 4e 50 mov 0x50(%rsi),%r9 + 42c413: 4c 8b 56 58 mov 0x58(%rsi),%r10 + 42c417: 4c 8b 5e 60 mov 0x60(%rsi),%r11 + 42c41b: 4c 8b 66 68 mov 0x68(%rsi),%r12 + 42c41f: 4c 8b 6e 70 mov 0x70(%rsi),%r13 + 42c423: 4c 8b 76 78 mov 0x78(%rsi),%r14 + 42c427: 48 0f c3 47 40 movnti %rax,0x40(%rdi) + 42c42c: 4c 0f c3 47 48 movnti %r8,0x48(%rdi) + 42c431: 4c 0f c3 4f 50 movnti %r9,0x50(%rdi) + 42c436: 4c 0f c3 57 58 movnti %r10,0x58(%rdi) + 42c43b: 4c 0f c3 5f 60 movnti %r11,0x60(%rdi) + 42c440: 4c 0f c3 67 68 movnti %r12,0x68(%rdi) + 42c445: 4c 0f c3 6f 70 movnti %r13,0x70(%rdi) + 42c44a: 4c 0f c3 77 78 movnti %r14,0x78(%rdi) + 42c44f: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi + 42c456: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi + 42c45d: 0f 85 4d ff ff ff jne 42c3b0 + 42c463: 0f ae f8 sfence + 42c466: 4c 8b 64 24 e0 mov -0x20(%rsp),%r12 + 42c46b: 4c 8b 6c 24 e8 mov -0x18(%rsp),%r13 + 42c470: 4c 8b 74 24 f0 mov -0x10(%rsp),%r14 + 42c475: 83 e2 7f and $0x7f,%edx + 42c478: 48 8b 44 24 f8 mov -0x8(%rsp),%rax + 42c47d: 0f 85 a6 fb ff ff jne 42c029 + 42c483: f3 c3 repz retq + 42c485: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42c48c: 00 00 00 + 42c48f: 90 nop + +000000000042c490 <_wordcopy_fwd_aligned>: + 42c490: 48 89 d0 mov %rdx,%rax + 42c493: 83 e0 07 and $0x7,%eax + 42c496: ff 24 c5 b0 31 4a 00 jmpq *0x4a31b0(,%rax,8) + 42c49d: 0f 1f 00 nopl (%rax) + 42c4a0: 48 8b 06 mov (%rsi),%rax + 42c4a3: 48 83 ef 18 sub $0x18,%rdi + 42c4a7: 48 83 ee 10 sub $0x10,%rsi + 42c4ab: 48 8b 4e 18 mov 0x18(%rsi),%rcx + 42c4af: 48 83 c2 02 add $0x2,%rdx + 42c4b3: 48 89 47 18 mov %rax,0x18(%rdi) + 42c4b7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 42c4be: 00 00 + 42c4c0: 48 8b 46 20 mov 0x20(%rsi),%rax + 42c4c4: 48 89 4f 20 mov %rcx,0x20(%rdi) + 42c4c8: 48 8b 4e 28 mov 0x28(%rsi),%rcx + 42c4cc: 48 89 47 28 mov %rax,0x28(%rdi) + 42c4d0: 48 8b 46 30 mov 0x30(%rsi),%rax + 42c4d4: 48 89 4f 30 mov %rcx,0x30(%rdi) + 42c4d8: 48 8b 4e 38 mov 0x38(%rsi),%rcx + 42c4dc: 48 83 c7 40 add $0x40,%rdi + 42c4e0: 48 89 47 f8 mov %rax,-0x8(%rdi) + 42c4e4: 48 83 ea 08 sub $0x8,%rdx + 42c4e8: 0f 84 ca 00 00 00 je 42c5b8 <_wordcopy_fwd_aligned+0x128> + 42c4ee: 48 83 c6 40 add $0x40,%rsi + 42c4f2: 48 8b 06 mov (%rsi),%rax + 42c4f5: 48 89 0f mov %rcx,(%rdi) + 42c4f8: 48 8b 4e 08 mov 0x8(%rsi),%rcx + 42c4fc: 48 89 47 08 mov %rax,0x8(%rdi) + 42c500: 48 8b 46 10 mov 0x10(%rsi),%rax + 42c504: 48 89 4f 10 mov %rcx,0x10(%rdi) + 42c508: 48 8b 4e 18 mov 0x18(%rsi),%rcx + 42c50c: 48 89 47 18 mov %rax,0x18(%rdi) + 42c510: eb ae jmp 42c4c0 <_wordcopy_fwd_aligned+0x30> + 42c512: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 42c518: 48 85 d2 test %rdx,%rdx + 42c51b: 0f 84 9a 00 00 00 je 42c5bb <_wordcopy_fwd_aligned+0x12b> + 42c521: 48 8b 06 mov (%rsi),%rax + 42c524: 48 83 ef 08 sub $0x8,%rdi + 42c528: eb ce jmp 42c4f8 <_wordcopy_fwd_aligned+0x68> + 42c52a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 42c530: 48 83 ea 01 sub $0x1,%rdx + 42c534: 48 8b 0e mov (%rsi),%rcx + 42c537: 74 7f je 42c5b8 <_wordcopy_fwd_aligned+0x128> + 42c539: 48 83 c6 08 add $0x8,%rsi + 42c53d: eb b3 jmp 42c4f2 <_wordcopy_fwd_aligned+0x62> + 42c53f: 90 nop + 42c540: 48 8b 06 mov (%rsi),%rax + 42c543: 48 83 c2 06 add $0x6,%rdx + 42c547: 48 83 ee 30 sub $0x30,%rsi + 42c54b: 48 83 ef 38 sub $0x38,%rdi + 42c54f: eb 87 jmp 42c4d8 <_wordcopy_fwd_aligned+0x48> + 42c551: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 42c558: 48 8b 0e mov (%rsi),%rcx + 42c55b: 48 83 c2 05 add $0x5,%rdx + 42c55f: 48 83 ee 28 sub $0x28,%rsi + 42c563: 48 83 ef 30 sub $0x30,%rdi + 42c567: e9 64 ff ff ff jmpq 42c4d0 <_wordcopy_fwd_aligned+0x40> + 42c56c: 0f 1f 40 00 nopl 0x0(%rax) + 42c570: 48 8b 06 mov (%rsi),%rax + 42c573: 48 83 c2 04 add $0x4,%rdx + 42c577: 48 83 ee 20 sub $0x20,%rsi + 42c57b: 48 83 ef 28 sub $0x28,%rdi + 42c57f: e9 44 ff ff ff jmpq 42c4c8 <_wordcopy_fwd_aligned+0x38> + 42c584: 0f 1f 40 00 nopl 0x0(%rax) + 42c588: 48 8b 0e mov (%rsi),%rcx + 42c58b: 48 83 c2 03 add $0x3,%rdx + 42c58f: 48 83 ee 18 sub $0x18,%rsi + 42c593: 48 83 ef 20 sub $0x20,%rdi + 42c597: e9 24 ff ff ff jmpq 42c4c0 <_wordcopy_fwd_aligned+0x30> + 42c59c: 0f 1f 40 00 nopl 0x0(%rax) + 42c5a0: 48 8b 0e mov (%rsi),%rcx + 42c5a3: 48 83 c2 01 add $0x1,%rdx + 42c5a7: 48 83 ee 08 sub $0x8,%rsi + 42c5ab: 48 83 ef 10 sub $0x10,%rdi + 42c5af: e9 4c ff ff ff jmpq 42c500 <_wordcopy_fwd_aligned+0x70> + 42c5b4: 0f 1f 40 00 nopl 0x0(%rax) + 42c5b8: 48 89 0f mov %rcx,(%rdi) + 42c5bb: f3 c3 repz retq + 42c5bd: 0f 1f 00 nopl (%rax) + +000000000042c5c0 <_wordcopy_fwd_dest_aligned>: + 42c5c0: 89 f0 mov %esi,%eax + 42c5c2: 48 89 d1 mov %rdx,%rcx + 42c5c5: 41 b8 40 00 00 00 mov $0x40,%r8d + 42c5cb: 83 e0 07 and $0x7,%eax + 42c5ce: 83 e1 03 and $0x3,%ecx + 42c5d1: 48 83 e6 f8 and $0xfffffffffffffff8,%rsi + 42c5d5: c1 e0 03 shl $0x3,%eax + 42c5d8: 53 push %rbx + 42c5d9: 41 29 c0 sub %eax,%r8d + 42c5dc: 48 83 f9 02 cmp $0x2,%rcx + 42c5e0: 0f 84 e2 00 00 00 je 42c6c8 <_wordcopy_fwd_dest_aligned+0x108> + 42c5e6: 48 83 f9 03 cmp $0x3,%rcx + 42c5ea: 74 54 je 42c640 <_wordcopy_fwd_dest_aligned+0x80> + 42c5ec: 48 83 f9 01 cmp $0x1,%rcx + 42c5f0: 74 1e je 42c610 <_wordcopy_fwd_dest_aligned+0x50> + 42c5f2: 48 85 d2 test %rdx,%rdx + 42c5f5: 74 42 je 42c639 <_wordcopy_fwd_dest_aligned+0x79> + 42c5f7: 4c 8b 0e mov (%rsi),%r9 + 42c5fa: 48 8b 5e 08 mov 0x8(%rsi),%rbx + 42c5fe: 48 83 ef 08 sub $0x8,%rdi + 42c602: 48 83 c6 08 add $0x8,%rsi + 42c606: e9 9b 00 00 00 jmpq 42c6a6 <_wordcopy_fwd_dest_aligned+0xe6> + 42c60b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 42c610: 48 83 ea 01 sub $0x1,%rdx + 42c614: 4c 8b 16 mov (%rsi),%r10 + 42c617: 4c 8b 4e 08 mov 0x8(%rsi),%r9 + 42c61b: 0f 85 bf 00 00 00 jne 42c6e0 <_wordcopy_fwd_dest_aligned+0x120> + 42c621: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 42c628: 89 c1 mov %eax,%ecx + 42c62a: 49 d3 ea shr %cl,%r10 + 42c62d: 44 89 c1 mov %r8d,%ecx + 42c630: 49 d3 e1 shl %cl,%r9 + 42c633: 4d 09 d1 or %r10,%r9 + 42c636: 4c 89 0f mov %r9,(%rdi) + 42c639: 5b pop %rbx + 42c63a: c3 retq + 42c63b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 42c640: 48 8b 1e mov (%rsi),%rbx + 42c643: 4c 8b 5e 08 mov 0x8(%rsi),%r11 + 42c647: 48 83 c2 01 add $0x1,%rdx + 42c64b: 48 83 ef 10 sub $0x10,%rdi + 42c64f: 89 c1 mov %eax,%ecx + 42c651: 4d 89 d9 mov %r11,%r9 + 42c654: 4c 8b 56 10 mov 0x10(%rsi),%r10 + 42c658: 48 d3 eb shr %cl,%rbx + 42c65b: 44 89 c1 mov %r8d,%ecx + 42c65e: 49 d3 e1 shl %cl,%r9 + 42c661: 4c 09 cb or %r9,%rbx + 42c664: 48 89 5f 10 mov %rbx,0x10(%rdi) + 42c668: 89 c1 mov %eax,%ecx + 42c66a: 4c 89 d3 mov %r10,%rbx + 42c66d: 4c 8b 4e 18 mov 0x18(%rsi),%r9 + 42c671: 49 d3 eb shr %cl,%r11 + 42c674: 44 89 c1 mov %r8d,%ecx + 42c677: 48 83 c7 20 add $0x20,%rdi + 42c67b: 48 d3 e3 shl %cl,%rbx + 42c67e: 49 09 db or %rbx,%r11 + 42c681: 4c 89 5f f8 mov %r11,-0x8(%rdi) + 42c685: 48 83 ea 04 sub $0x4,%rdx + 42c689: 74 9d je 42c628 <_wordcopy_fwd_dest_aligned+0x68> + 42c68b: 48 83 c6 20 add $0x20,%rsi + 42c68f: 89 c1 mov %eax,%ecx + 42c691: 4d 89 cb mov %r9,%r11 + 42c694: 48 8b 1e mov (%rsi),%rbx + 42c697: 49 d3 ea shr %cl,%r10 + 42c69a: 44 89 c1 mov %r8d,%ecx + 42c69d: 49 d3 e3 shl %cl,%r11 + 42c6a0: 4d 09 da or %r11,%r10 + 42c6a3: 4c 89 17 mov %r10,(%rdi) + 42c6a6: 89 c1 mov %eax,%ecx + 42c6a8: 49 89 da mov %rbx,%r10 + 42c6ab: 4c 8b 5e 08 mov 0x8(%rsi),%r11 + 42c6af: 49 d3 e9 shr %cl,%r9 + 42c6b2: 44 89 c1 mov %r8d,%ecx + 42c6b5: 49 d3 e2 shl %cl,%r10 + 42c6b8: 4d 09 d1 or %r10,%r9 + 42c6bb: 4c 89 4f 08 mov %r9,0x8(%rdi) + 42c6bf: eb 8e jmp 42c64f <_wordcopy_fwd_dest_aligned+0x8f> + 42c6c1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 42c6c8: 4c 8b 1e mov (%rsi),%r11 + 42c6cb: 4c 8b 56 08 mov 0x8(%rsi),%r10 + 42c6cf: 48 83 c2 02 add $0x2,%rdx + 42c6d3: 48 83 ee 08 sub $0x8,%rsi + 42c6d7: 48 83 ef 18 sub $0x18,%rdi + 42c6db: eb 8b jmp 42c668 <_wordcopy_fwd_dest_aligned+0xa8> + 42c6dd: 0f 1f 00 nopl (%rax) + 42c6e0: 48 83 c6 10 add $0x10,%rsi + 42c6e4: eb a9 jmp 42c68f <_wordcopy_fwd_dest_aligned+0xcf> + 42c6e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42c6ed: 00 00 00 + +000000000042c6f0 <_wordcopy_bwd_aligned>: + 42c6f0: 48 89 d0 mov %rdx,%rax + 42c6f3: 83 e0 07 and $0x7,%eax + 42c6f6: ff 24 c5 f0 31 4a 00 jmpq *0x4a31f0(,%rax,8) + 42c6fd: 0f 1f 00 nopl (%rax) + 42c700: 4c 8d 46 d0 lea -0x30(%rsi),%r8 + 42c704: 48 8b 76 f8 mov -0x8(%rsi),%rsi + 42c708: 48 83 ef 28 sub $0x28,%rdi + 42c70c: 48 89 f8 mov %rdi,%rax + 42c70f: 48 83 c2 02 add $0x2,%rdx + 42c713: 4c 89 c1 mov %r8,%rcx + 42c716: 4c 8b 49 20 mov 0x20(%rcx),%r9 + 42c71a: 48 89 70 20 mov %rsi,0x20(%rax) + 42c71e: 66 90 xchg %ax,%ax + 42c720: 48 8b 71 18 mov 0x18(%rcx),%rsi + 42c724: 4c 89 48 18 mov %r9,0x18(%rax) + 42c728: 4c 8b 49 10 mov 0x10(%rcx),%r9 + 42c72c: 48 89 70 10 mov %rsi,0x10(%rax) + 42c730: 48 8b 71 08 mov 0x8(%rcx),%rsi + 42c734: 4c 89 48 08 mov %r9,0x8(%rax) + 42c738: 48 83 ea 08 sub $0x8,%rdx + 42c73c: 4d 8b 08 mov (%r8),%r9 + 42c73f: 48 89 37 mov %rsi,(%rdi) + 42c742: 4c 8d 41 c0 lea -0x40(%rcx),%r8 + 42c746: 48 8d 78 c0 lea -0x40(%rax),%rdi + 42c74a: 0f 84 10 01 00 00 je 42c860 <_wordcopy_bwd_aligned+0x170> + 42c750: 49 8b 70 38 mov 0x38(%r8),%rsi + 42c754: 4c 89 c1 mov %r8,%rcx + 42c757: 48 89 f8 mov %rdi,%rax + 42c75a: 4c 89 4f 38 mov %r9,0x38(%rdi) + 42c75e: 4c 8b 49 30 mov 0x30(%rcx),%r9 + 42c762: 48 89 70 30 mov %rsi,0x30(%rax) + 42c766: 48 8b 71 28 mov 0x28(%rcx),%rsi + 42c76a: 4c 89 48 28 mov %r9,0x28(%rax) + 42c76e: 4c 8b 49 20 mov 0x20(%rcx),%r9 + 42c772: 48 89 70 20 mov %rsi,0x20(%rax) + 42c776: eb a8 jmp 42c720 <_wordcopy_bwd_aligned+0x30> + 42c778: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 42c77f: 00 + 42c780: 48 85 d2 test %rdx,%rdx + 42c783: 0f 84 db 00 00 00 je 42c864 <_wordcopy_bwd_aligned+0x174> + 42c789: 4c 8d 46 c0 lea -0x40(%rsi),%r8 + 42c78d: 48 83 ef 38 sub $0x38,%rdi + 42c791: 48 8b 76 f8 mov -0x8(%rsi),%rsi + 42c795: 48 89 f8 mov %rdi,%rax + 42c798: 4c 89 c1 mov %r8,%rcx + 42c79b: eb c1 jmp 42c75e <_wordcopy_bwd_aligned+0x6e> + 42c79d: 0f 1f 00 nopl (%rax) + 42c7a0: 48 83 ef 40 sub $0x40,%rdi + 42c7a4: 48 83 ea 01 sub $0x1,%rdx + 42c7a8: 4c 8b 4e f8 mov -0x8(%rsi),%r9 + 42c7ac: 0f 84 ae 00 00 00 je 42c860 <_wordcopy_bwd_aligned+0x170> + 42c7b2: 4c 8d 46 b8 lea -0x48(%rsi),%r8 + 42c7b6: eb 98 jmp 42c750 <_wordcopy_bwd_aligned+0x60> + 42c7b8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 42c7bf: 00 + 42c7c0: 48 8d 4e f0 lea -0x10(%rsi),%rcx + 42c7c4: 48 8d 47 f8 lea -0x8(%rdi),%rax + 42c7c8: 48 8b 76 f8 mov -0x8(%rsi),%rsi + 42c7cc: 48 83 c2 06 add $0x6,%rdx + 42c7d0: 49 89 c8 mov %rcx,%r8 + 42c7d3: 48 89 c7 mov %rax,%rdi + 42c7d6: e9 5d ff ff ff jmpq 42c738 <_wordcopy_bwd_aligned+0x48> + 42c7db: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 42c7e0: 4c 8d 46 e8 lea -0x18(%rsi),%r8 + 42c7e4: 48 83 ef 10 sub $0x10,%rdi + 42c7e8: 4c 8b 4e f8 mov -0x8(%rsi),%r9 + 42c7ec: 48 83 c2 05 add $0x5,%rdx + 42c7f0: 48 89 f8 mov %rdi,%rax + 42c7f3: 4c 89 c1 mov %r8,%rcx + 42c7f6: e9 35 ff ff ff jmpq 42c730 <_wordcopy_bwd_aligned+0x40> + 42c7fb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 42c800: 4c 8d 46 e0 lea -0x20(%rsi),%r8 + 42c804: 48 83 ef 18 sub $0x18,%rdi + 42c808: 48 8b 76 f8 mov -0x8(%rsi),%rsi + 42c80c: 48 83 c2 04 add $0x4,%rdx + 42c810: 48 89 f8 mov %rdi,%rax + 42c813: 4c 89 c1 mov %r8,%rcx + 42c816: e9 0d ff ff ff jmpq 42c728 <_wordcopy_bwd_aligned+0x38> + 42c81b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 42c820: 4c 8d 46 d8 lea -0x28(%rsi),%r8 + 42c824: 48 83 ef 20 sub $0x20,%rdi + 42c828: 4c 8b 4e f8 mov -0x8(%rsi),%r9 + 42c82c: 48 83 c2 03 add $0x3,%rdx + 42c830: 48 89 f8 mov %rdi,%rax + 42c833: 4c 89 c1 mov %r8,%rcx + 42c836: e9 e5 fe ff ff jmpq 42c720 <_wordcopy_bwd_aligned+0x30> + 42c83b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 42c840: 4c 8d 46 c8 lea -0x38(%rsi),%r8 + 42c844: 48 83 ef 30 sub $0x30,%rdi + 42c848: 4c 8b 4e f8 mov -0x8(%rsi),%r9 + 42c84c: 48 83 c2 01 add $0x1,%rdx + 42c850: 48 89 f8 mov %rdi,%rax + 42c853: 4c 89 c1 mov %r8,%rcx + 42c856: e9 0b ff ff ff jmpq 42c766 <_wordcopy_bwd_aligned+0x76> + 42c85b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 42c860: 4c 89 4f 38 mov %r9,0x38(%rdi) + 42c864: f3 c3 repz retq + 42c866: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42c86d: 00 00 00 + +000000000042c870 <_wordcopy_bwd_dest_aligned>: + 42c870: 89 f0 mov %esi,%eax + 42c872: 48 89 d1 mov %rdx,%rcx + 42c875: 41 bb 40 00 00 00 mov $0x40,%r11d + 42c87b: 83 e0 07 and $0x7,%eax + 42c87e: 83 e1 03 and $0x3,%ecx + 42c881: 48 83 e6 f8 and $0xfffffffffffffff8,%rsi + 42c885: c1 e0 03 shl $0x3,%eax + 42c888: 41 54 push %r12 + 42c88a: 55 push %rbp + 42c88b: 41 29 c3 sub %eax,%r11d + 42c88e: 48 83 f9 02 cmp $0x2,%rcx + 42c892: 53 push %rbx + 42c893: 0f 84 07 01 00 00 je 42c9a0 <_wordcopy_bwd_dest_aligned+0x130> + 42c899: 48 83 f9 03 cmp $0x3,%rcx + 42c89d: 74 61 je 42c900 <_wordcopy_bwd_dest_aligned+0x90> + 42c89f: 48 83 f9 01 cmp $0x1,%rcx + 42c8a3: 74 23 je 42c8c8 <_wordcopy_bwd_dest_aligned+0x58> + 42c8a5: 48 85 d2 test %rdx,%rdx + 42c8a8: 74 48 je 42c8f2 <_wordcopy_bwd_dest_aligned+0x82> + 42c8aa: 48 8d 6e e0 lea -0x20(%rsi),%rbp + 42c8ae: 4c 8d 57 e8 lea -0x18(%rdi),%r10 + 42c8b2: 4c 8b 26 mov (%rsi),%r12 + 42c8b5: 4c 8b 4e f8 mov -0x8(%rsi),%r9 + 42c8b9: 4c 89 d7 mov %r10,%rdi + 42c8bc: 48 89 ee mov %rbp,%rsi + 42c8bf: e9 b9 00 00 00 jmpq 42c97d <_wordcopy_bwd_dest_aligned+0x10d> + 42c8c4: 0f 1f 40 00 nopl 0x0(%rax) + 42c8c8: 48 83 ea 01 sub $0x1,%rdx + 42c8cc: 4c 8d 57 e0 lea -0x20(%rdi),%r10 + 42c8d0: 4c 8b 06 mov (%rsi),%r8 + 42c8d3: 4c 8b 66 f8 mov -0x8(%rsi),%r12 + 42c8d7: 0f 85 e3 00 00 00 jne 42c9c0 <_wordcopy_bwd_dest_aligned+0x150> + 42c8dd: 0f 1f 00 nopl (%rax) + 42c8e0: 89 c1 mov %eax,%ecx + 42c8e2: 49 d3 ec shr %cl,%r12 + 42c8e5: 44 89 d9 mov %r11d,%ecx + 42c8e8: 49 d3 e0 shl %cl,%r8 + 42c8eb: 4d 09 e0 or %r12,%r8 + 42c8ee: 4d 89 42 18 mov %r8,0x18(%r10) + 42c8f2: 5b pop %rbx + 42c8f3: 5d pop %rbp + 42c8f4: 41 5c pop %r12 + 42c8f6: c3 retq + 42c8f7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 42c8fe: 00 00 + 42c900: 48 8d 6e e8 lea -0x18(%rsi),%rbp + 42c904: 4c 8d 57 f0 lea -0x10(%rdi),%r10 + 42c908: 4c 8b 0e mov (%rsi),%r9 + 42c90b: 48 8b 5e f8 mov -0x8(%rsi),%rbx + 42c90f: 48 83 c2 01 add $0x1,%rdx + 42c913: 48 89 ee mov %rbp,%rsi + 42c916: 4c 89 d7 mov %r10,%rdi + 42c919: 89 c1 mov %eax,%ecx + 42c91b: 49 89 dc mov %rbx,%r12 + 42c91e: 4c 8b 46 08 mov 0x8(%rsi),%r8 + 42c922: 49 d3 ec shr %cl,%r12 + 42c925: 44 89 d9 mov %r11d,%ecx + 42c928: 49 d3 e1 shl %cl,%r9 + 42c92b: 4d 09 e1 or %r12,%r9 + 42c92e: 4c 89 4f 08 mov %r9,0x8(%rdi) + 42c932: 49 89 f1 mov %rsi,%r9 + 42c935: 89 c1 mov %eax,%ecx + 42c937: 4c 89 c6 mov %r8,%rsi + 42c93a: 4c 8b 65 00 mov 0x0(%rbp),%r12 + 42c93e: 48 d3 ee shr %cl,%rsi + 42c941: 44 89 d9 mov %r11d,%ecx + 42c944: 49 8d 69 e0 lea -0x20(%r9),%rbp + 42c948: 48 d3 e3 shl %cl,%rbx + 42c94b: 48 89 d9 mov %rbx,%rcx + 42c94e: 48 09 f1 or %rsi,%rcx + 42c951: 48 83 ea 04 sub $0x4,%rdx + 42c955: 49 89 0a mov %rcx,(%r10) + 42c958: 4c 8d 57 e0 lea -0x20(%rdi),%r10 + 42c95c: 74 82 je 42c8e0 <_wordcopy_bwd_dest_aligned+0x70> + 42c95e: 89 c1 mov %eax,%ecx + 42c960: 4c 89 e3 mov %r12,%rbx + 42c963: 4c 8b 4d 18 mov 0x18(%rbp),%r9 + 42c967: 48 d3 eb shr %cl,%rbx + 42c96a: 44 89 d9 mov %r11d,%ecx + 42c96d: 48 89 ee mov %rbp,%rsi + 42c970: 49 d3 e0 shl %cl,%r8 + 42c973: 4c 89 d7 mov %r10,%rdi + 42c976: 49 09 d8 or %rbx,%r8 + 42c979: 4d 89 42 18 mov %r8,0x18(%r10) + 42c97d: 89 c1 mov %eax,%ecx + 42c97f: 4d 89 c8 mov %r9,%r8 + 42c982: 48 8b 5e 10 mov 0x10(%rsi),%rbx + 42c986: 49 d3 e8 shr %cl,%r8 + 42c989: 44 89 d9 mov %r11d,%ecx + 42c98c: 49 d3 e4 shl %cl,%r12 + 42c98f: 4d 09 c4 or %r8,%r12 + 42c992: 4c 89 67 10 mov %r12,0x10(%rdi) + 42c996: eb 81 jmp 42c919 <_wordcopy_bwd_dest_aligned+0xa9> + 42c998: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 42c99f: 00 + 42c9a0: 4c 8d 4e f0 lea -0x10(%rsi),%r9 + 42c9a4: 48 83 ef 08 sub $0x8,%rdi + 42c9a8: 48 8b 1e mov (%rsi),%rbx + 42c9ab: 49 89 fa mov %rdi,%r10 + 42c9ae: 4c 8b 46 f8 mov -0x8(%rsi),%r8 + 42c9b2: 48 83 c2 02 add $0x2,%rdx + 42c9b6: 4c 89 cd mov %r9,%rbp + 42c9b9: e9 77 ff ff ff jmpq 42c935 <_wordcopy_bwd_dest_aligned+0xc5> + 42c9be: 66 90 xchg %ax,%ax + 42c9c0: 48 8d 6e d8 lea -0x28(%rsi),%rbp + 42c9c4: eb 98 jmp 42c95e <_wordcopy_bwd_dest_aligned+0xee> + 42c9c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42c9cd: 00 00 00 + +000000000042c9d0 <__rawmemchr>: + 42c9d0: 66 48 0f 6e ce movq %rsi,%xmm1 + 42c9d5: 48 89 f9 mov %rdi,%rcx + 42c9d8: 66 0f 60 c9 punpcklbw %xmm1,%xmm1 + 42c9dc: 66 0f 60 c9 punpcklbw %xmm1,%xmm1 + 42c9e0: 48 83 e1 3f and $0x3f,%rcx + 42c9e4: 66 0f 70 c9 00 pshufd $0x0,%xmm1,%xmm1 + 42c9e9: 48 83 f9 30 cmp $0x30,%rcx + 42c9ed: 77 21 ja 42ca10 <__rawmemchr+0x40> + 42c9ef: f3 0f 6f 07 movdqu (%rdi),%xmm0 + 42c9f3: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42c9f7: 66 0f d7 c0 pmovmskb %xmm0,%eax + 42c9fb: 85 c0 test %eax,%eax + 42c9fd: 0f 85 9d 01 00 00 jne 42cba0 <__rawmemchr+0x1d0> + 42ca03: 48 83 c7 10 add $0x10,%rdi + 42ca07: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi + 42ca0b: eb 43 jmp 42ca50 <__rawmemchr+0x80> + 42ca0d: 0f 1f 00 nopl (%rax) + 42ca10: 48 83 e1 0f and $0xf,%rcx + 42ca14: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi + 42ca18: 66 0f 6f 07 movdqa (%rdi),%xmm0 + 42ca1c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42ca20: 66 0f d7 c0 pmovmskb %xmm0,%eax + 42ca24: d3 f8 sar %cl,%eax + 42ca26: 85 c0 test %eax,%eax + 42ca28: 74 16 je 42ca40 <__rawmemchr+0x70> + 42ca2a: 0f bc c0 bsf %eax,%eax + 42ca2d: 48 01 f8 add %rdi,%rax + 42ca30: 48 01 c8 add %rcx,%rax + 42ca33: c3 retq + 42ca34: 66 90 xchg %ax,%ax + 42ca36: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42ca3d: 00 00 00 + 42ca40: 48 83 c7 10 add $0x10,%rdi + 42ca44: 66 90 xchg %ax,%ax + 42ca46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42ca4d: 00 00 00 + 42ca50: 66 0f 6f 07 movdqa (%rdi),%xmm0 + 42ca54: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42ca58: 66 0f d7 c0 pmovmskb %xmm0,%eax + 42ca5c: 85 c0 test %eax,%eax + 42ca5e: 0f 85 3c 01 00 00 jne 42cba0 <__rawmemchr+0x1d0> + 42ca64: 66 0f 6f 57 10 movdqa 0x10(%rdi),%xmm2 + 42ca69: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42ca6d: 66 0f d7 c2 pmovmskb %xmm2,%eax + 42ca71: 85 c0 test %eax,%eax + 42ca73: 0f 85 37 01 00 00 jne 42cbb0 <__rawmemchr+0x1e0> + 42ca79: 66 0f 6f 5f 20 movdqa 0x20(%rdi),%xmm3 + 42ca7e: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 + 42ca82: 66 0f d7 c3 pmovmskb %xmm3,%eax + 42ca86: 85 c0 test %eax,%eax + 42ca88: 0f 85 32 01 00 00 jne 42cbc0 <__rawmemchr+0x1f0> + 42ca8e: 66 0f 6f 67 30 movdqa 0x30(%rdi),%xmm4 + 42ca93: 66 0f 74 e1 pcmpeqb %xmm1,%xmm4 + 42ca97: 48 83 c7 40 add $0x40,%rdi + 42ca9b: 66 0f d7 c4 pmovmskb %xmm4,%eax + 42ca9f: 85 c0 test %eax,%eax + 42caa1: 0f 85 e9 00 00 00 jne 42cb90 <__rawmemchr+0x1c0> + 42caa7: 48 f7 c7 3f 00 00 00 test $0x3f,%rdi + 42caae: 74 60 je 42cb10 <__rawmemchr+0x140> + 42cab0: 66 0f 6f 07 movdqa (%rdi),%xmm0 + 42cab4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42cab8: 66 0f d7 c0 pmovmskb %xmm0,%eax + 42cabc: 85 c0 test %eax,%eax + 42cabe: 0f 85 dc 00 00 00 jne 42cba0 <__rawmemchr+0x1d0> + 42cac4: 66 0f 6f 57 10 movdqa 0x10(%rdi),%xmm2 + 42cac9: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42cacd: 66 0f d7 c2 pmovmskb %xmm2,%eax + 42cad1: 85 c0 test %eax,%eax + 42cad3: 0f 85 d7 00 00 00 jne 42cbb0 <__rawmemchr+0x1e0> + 42cad9: 66 0f 6f 5f 20 movdqa 0x20(%rdi),%xmm3 + 42cade: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 + 42cae2: 66 0f d7 c3 pmovmskb %xmm3,%eax + 42cae6: 85 c0 test %eax,%eax + 42cae8: 0f 85 d2 00 00 00 jne 42cbc0 <__rawmemchr+0x1f0> + 42caee: 66 0f 6f 5f 30 movdqa 0x30(%rdi),%xmm3 + 42caf3: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 + 42caf7: 66 0f d7 c3 pmovmskb %xmm3,%eax + 42cafb: 48 83 c7 40 add $0x40,%rdi + 42caff: 85 c0 test %eax,%eax + 42cb01: 0f 85 89 00 00 00 jne 42cb90 <__rawmemchr+0x1c0> + 42cb07: 48 83 e7 c0 and $0xffffffffffffffc0,%rdi + 42cb0b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 42cb10: 66 0f 6f 07 movdqa (%rdi),%xmm0 + 42cb14: 66 0f 6f 57 10 movdqa 0x10(%rdi),%xmm2 + 42cb19: 66 0f 6f 5f 20 movdqa 0x20(%rdi),%xmm3 + 42cb1e: 66 0f 6f 67 30 movdqa 0x30(%rdi),%xmm4 + 42cb23: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42cb27: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42cb2b: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 + 42cb2f: 66 0f 74 e1 pcmpeqb %xmm1,%xmm4 + 42cb33: 66 0f de d8 pmaxub %xmm0,%xmm3 + 42cb37: 66 0f de e2 pmaxub %xmm2,%xmm4 + 42cb3b: 66 0f de e3 pmaxub %xmm3,%xmm4 + 42cb3f: 66 0f d7 c4 pmovmskb %xmm4,%eax + 42cb43: 48 83 c7 40 add $0x40,%rdi + 42cb47: 85 c0 test %eax,%eax + 42cb49: 74 c5 je 42cb10 <__rawmemchr+0x140> + 42cb4b: 48 83 ef 40 sub $0x40,%rdi + 42cb4f: 66 0f d7 c0 pmovmskb %xmm0,%eax + 42cb53: 85 c0 test %eax,%eax + 42cb55: 75 49 jne 42cba0 <__rawmemchr+0x1d0> + 42cb57: 66 0f d7 c2 pmovmskb %xmm2,%eax + 42cb5b: 85 c0 test %eax,%eax + 42cb5d: 75 51 jne 42cbb0 <__rawmemchr+0x1e0> + 42cb5f: 66 0f 6f 5f 20 movdqa 0x20(%rdi),%xmm3 + 42cb64: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 + 42cb68: 66 0f 74 4f 30 pcmpeqb 0x30(%rdi),%xmm1 + 42cb6d: 66 0f d7 c3 pmovmskb %xmm3,%eax + 42cb71: 85 c0 test %eax,%eax + 42cb73: 75 4b jne 42cbc0 <__rawmemchr+0x1f0> + 42cb75: 66 0f d7 c1 pmovmskb %xmm1,%eax + 42cb79: 0f bc c0 bsf %eax,%eax + 42cb7c: 48 8d 44 07 30 lea 0x30(%rdi,%rax,1),%rax + 42cb81: c3 retq + 42cb82: 0f 1f 40 00 nopl 0x0(%rax) + 42cb86: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42cb8d: 00 00 00 + 42cb90: 0f bc c0 bsf %eax,%eax + 42cb93: 48 8d 44 38 f0 lea -0x10(%rax,%rdi,1),%rax + 42cb98: c3 retq + 42cb99: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 42cba0: 0f bc c0 bsf %eax,%eax + 42cba3: 48 01 f8 add %rdi,%rax + 42cba6: c3 retq + 42cba7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 42cbae: 00 00 + 42cbb0: 0f bc c0 bsf %eax,%eax + 42cbb3: 48 8d 44 38 10 lea 0x10(%rax,%rdi,1),%rax + 42cbb8: c3 retq + 42cbb9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 42cbc0: 0f bc c0 bsf %eax,%eax + 42cbc3: 48 8d 44 38 20 lea 0x20(%rax,%rdi,1),%rax + 42cbc8: c3 retq + 42cbc9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 42cbd0: 48 31 c0 xor %rax,%rax + 42cbd3: c3 retq + 42cbd4: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42cbdb: 00 00 00 + 42cbde: 66 90 xchg %ax,%ax + +000000000042cbe0 <__strchrnul>: + 42cbe0: 66 0f 6e ce movd %esi,%xmm1 + 42cbe4: 89 f8 mov %edi,%eax + 42cbe6: 25 ff 0f 00 00 and $0xfff,%eax + 42cbeb: 66 0f 60 c9 punpcklbw %xmm1,%xmm1 + 42cbef: 3d c0 0f 00 00 cmp $0xfc0,%eax + 42cbf4: 66 0f 61 c9 punpcklwd %xmm1,%xmm1 + 42cbf8: 66 0f 70 c9 00 pshufd $0x0,%xmm1,%xmm1 + 42cbfd: 0f 8f 4d 01 00 00 jg 42cd50 <__strchrnul+0x170> + 42cc03: f3 0f 6f 07 movdqu (%rdi),%xmm0 + 42cc07: 66 0f ef db pxor %xmm3,%xmm3 + 42cc0b: 66 0f 6f e0 movdqa %xmm0,%xmm4 + 42cc0f: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42cc13: 66 0f 74 e3 pcmpeqb %xmm3,%xmm4 + 42cc17: 66 0f eb c4 por %xmm4,%xmm0 + 42cc1b: 66 0f d7 c0 pmovmskb %xmm0,%eax + 42cc1f: 85 c0 test %eax,%eax + 42cc21: 74 0d je 42cc30 <__strchrnul+0x50> + 42cc23: 0f bc c0 bsf %eax,%eax + 42cc26: 48 8d 04 07 lea (%rdi,%rax,1),%rax + 42cc2a: c3 retq + 42cc2b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 42cc30: f3 0f 6f 47 10 movdqu 0x10(%rdi),%xmm0 + 42cc35: 66 0f 6f e0 movdqa %xmm0,%xmm4 + 42cc39: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42cc3d: 66 0f 74 e3 pcmpeqb %xmm3,%xmm4 + 42cc41: 66 0f eb c4 por %xmm4,%xmm0 + 42cc45: 66 0f d7 c8 pmovmskb %xmm0,%ecx + 42cc49: f3 0f 6f 47 20 movdqu 0x20(%rdi),%xmm0 + 42cc4e: 66 0f 6f e0 movdqa %xmm0,%xmm4 + 42cc52: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42cc56: 48 c1 e1 10 shl $0x10,%rcx + 42cc5a: 66 0f 74 e3 pcmpeqb %xmm3,%xmm4 + 42cc5e: 66 0f eb c4 por %xmm4,%xmm0 + 42cc62: 66 0f d7 c0 pmovmskb %xmm0,%eax + 42cc66: f3 0f 6f 47 30 movdqu 0x30(%rdi),%xmm0 + 42cc6b: 66 0f 74 d8 pcmpeqb %xmm0,%xmm3 + 42cc6f: 48 c1 e0 20 shl $0x20,%rax + 42cc73: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42cc77: 48 09 c8 or %rcx,%rax + 42cc7a: 66 0f eb c3 por %xmm3,%xmm0 + 42cc7e: 66 0f d7 c8 pmovmskb %xmm0,%ecx + 42cc82: 48 c1 e1 30 shl $0x30,%rcx + 42cc86: 48 09 c8 or %rcx,%rax + 42cc89: 48 85 c0 test %rax,%rax + 42cc8c: 0f 85 ae 00 00 00 jne 42cd40 <__strchrnul+0x160> + 42cc92: 0f 1f 40 00 nopl 0x0(%rax) + 42cc96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42cc9d: 00 00 00 + 42cca0: 66 0f ef f6 pxor %xmm6,%xmm6 + 42cca4: 48 83 e7 c0 and $0xffffffffffffffc0,%rdi + 42cca8: 48 83 c7 40 add $0x40,%rdi + 42ccac: 66 0f 6f 2f movdqa (%rdi),%xmm5 + 42ccb0: 66 0f 6f 57 10 movdqa 0x10(%rdi),%xmm2 + 42ccb5: 66 0f 6f 5f 20 movdqa 0x20(%rdi),%xmm3 + 42ccba: 66 0f ef e9 pxor %xmm1,%xmm5 + 42ccbe: 66 0f 6f 67 30 movdqa 0x30(%rdi),%xmm4 + 42ccc3: 66 0f ef d1 pxor %xmm1,%xmm2 + 42ccc7: 66 0f ef d9 pxor %xmm1,%xmm3 + 42cccb: 66 0f da 2f pminub (%rdi),%xmm5 + 42cccf: 66 0f ef e1 pxor %xmm1,%xmm4 + 42ccd3: 66 0f da 57 10 pminub 0x10(%rdi),%xmm2 + 42ccd8: 66 0f da 5f 20 pminub 0x20(%rdi),%xmm3 + 42ccdd: 66 0f da ea pminub %xmm2,%xmm5 + 42cce1: 66 0f da 67 30 pminub 0x30(%rdi),%xmm4 + 42cce6: 66 0f da eb pminub %xmm3,%xmm5 + 42ccea: 66 0f da ec pminub %xmm4,%xmm5 + 42ccee: 66 0f 74 ee pcmpeqb %xmm6,%xmm5 + 42ccf2: 66 0f d7 c5 pmovmskb %xmm5,%eax + 42ccf6: 85 c0 test %eax,%eax + 42ccf8: 74 ae je 42cca8 <__strchrnul+0xc8> + 42ccfa: 66 0f 6f 2f movdqa (%rdi),%xmm5 + 42ccfe: 66 0f 6f c5 movdqa %xmm5,%xmm0 + 42cd02: 66 0f 74 e9 pcmpeqb %xmm1,%xmm5 + 42cd06: 66 0f 74 c6 pcmpeqb %xmm6,%xmm0 + 42cd0a: 66 0f eb e8 por %xmm0,%xmm5 + 42cd0e: 66 0f 74 d6 pcmpeqb %xmm6,%xmm2 + 42cd12: 66 0f 74 de pcmpeqb %xmm6,%xmm3 + 42cd16: 66 0f 74 e6 pcmpeqb %xmm6,%xmm4 + 42cd1a: 66 0f d7 cd pmovmskb %xmm5,%ecx + 42cd1e: 66 0f d7 c2 pmovmskb %xmm2,%eax + 42cd22: 48 c1 e0 10 shl $0x10,%rax + 42cd26: 66 44 0f d7 c3 pmovmskb %xmm3,%r8d + 42cd2b: 66 0f d7 d4 pmovmskb %xmm4,%edx + 42cd2f: 49 c1 e0 20 shl $0x20,%r8 + 42cd33: 4c 09 c0 or %r8,%rax + 42cd36: 48 09 c8 or %rcx,%rax + 42cd39: 48 c1 e2 30 shl $0x30,%rdx + 42cd3d: 48 09 d0 or %rdx,%rax + 42cd40: 48 0f bc c0 bsf %rax,%rax + 42cd44: 48 8d 04 07 lea (%rdi,%rax,1),%rax + 42cd48: c3 retq + 42cd49: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 42cd50: 48 89 fa mov %rdi,%rdx + 42cd53: 66 0f ef d2 pxor %xmm2,%xmm2 + 42cd57: 48 83 e2 c0 and $0xffffffffffffffc0,%rdx + 42cd5b: 66 0f 6f c1 movdqa %xmm1,%xmm0 + 42cd5f: 66 0f 6f 1a movdqa (%rdx),%xmm3 + 42cd63: 66 0f 6f e3 movdqa %xmm3,%xmm4 + 42cd67: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 + 42cd6b: 66 0f 74 e2 pcmpeqb %xmm2,%xmm4 + 42cd6f: 66 0f eb dc por %xmm4,%xmm3 + 42cd73: 66 44 0f d7 c3 pmovmskb %xmm3,%r8d + 42cd78: 66 0f 6f 5a 10 movdqa 0x10(%rdx),%xmm3 + 42cd7d: 66 0f 6f e3 movdqa %xmm3,%xmm4 + 42cd81: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 + 42cd85: 66 0f 74 e2 pcmpeqb %xmm2,%xmm4 + 42cd89: 66 0f eb dc por %xmm4,%xmm3 + 42cd8d: 66 0f d7 c3 pmovmskb %xmm3,%eax + 42cd91: 66 0f 6f 5a 20 movdqa 0x20(%rdx),%xmm3 + 42cd96: 66 0f 6f e3 movdqa %xmm3,%xmm4 + 42cd9a: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 + 42cd9e: 48 c1 e0 10 shl $0x10,%rax + 42cda2: 66 0f 74 e2 pcmpeqb %xmm2,%xmm4 + 42cda6: 66 0f eb dc por %xmm4,%xmm3 + 42cdaa: 66 44 0f d7 cb pmovmskb %xmm3,%r9d + 42cdaf: 66 0f 6f 5a 30 movdqa 0x30(%rdx),%xmm3 + 42cdb4: 66 0f 74 d3 pcmpeqb %xmm3,%xmm2 + 42cdb8: 49 c1 e1 20 shl $0x20,%r9 + 42cdbc: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 42cdc0: 4c 09 c8 or %r9,%rax + 42cdc3: 4c 09 c0 or %r8,%rax + 42cdc6: 66 0f eb c2 por %xmm2,%xmm0 + 42cdca: 66 0f d7 c8 pmovmskb %xmm0,%ecx + 42cdce: 48 c1 e1 30 shl $0x30,%rcx + 42cdd2: 48 09 c8 or %rcx,%rax + 42cdd5: 89 f9 mov %edi,%ecx + 42cdd7: 28 d1 sub %dl,%cl + 42cdd9: 48 d3 e8 shr %cl,%rax + 42cddc: 48 85 c0 test %rax,%rax + 42cddf: 0f 85 5b ff ff ff jne 42cd40 <__strchrnul+0x160> + 42cde5: e9 a8 fe ff ff jmpq 42cc92 <__strchrnul+0xb2> + 42cdea: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + +000000000042cdf0 <__strcmp_ssse3>: + 42cdf0: 89 f1 mov %esi,%ecx + 42cdf2: 89 f8 mov %edi,%eax + 42cdf4: 48 83 e1 3f and $0x3f,%rcx + 42cdf8: 48 83 e0 3f and $0x3f,%rax + 42cdfc: 83 f9 30 cmp $0x30,%ecx + 42cdff: 77 3f ja 42ce40 <__strcmp_ssse3+0x50> + 42ce01: 83 f8 30 cmp $0x30,%eax + 42ce04: 77 3a ja 42ce40 <__strcmp_ssse3+0x50> + 42ce06: 66 0f 12 0f movlpd (%rdi),%xmm1 + 42ce0a: 66 0f 12 16 movlpd (%rsi),%xmm2 + 42ce0e: 66 0f 16 4f 08 movhpd 0x8(%rdi),%xmm1 + 42ce13: 66 0f 16 56 08 movhpd 0x8(%rsi),%xmm2 + 42ce18: 66 0f ef c0 pxor %xmm0,%xmm0 + 42ce1c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42ce20: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42ce24: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42ce28: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42ce2c: 81 ea ff ff 00 00 sub $0xffff,%edx + 42ce32: 0f 85 e8 11 00 00 jne 42e020 <__strcmp_ssse3+0x1230> + 42ce38: 48 83 c6 10 add $0x10,%rsi + 42ce3c: 48 83 c7 10 add $0x10,%rdi + 42ce40: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi + 42ce44: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi + 42ce48: ba ff ff 00 00 mov $0xffff,%edx + 42ce4d: 45 31 c0 xor %r8d,%r8d + 42ce50: 83 e1 0f and $0xf,%ecx + 42ce53: 83 e0 0f and $0xf,%eax + 42ce56: 39 c1 cmp %eax,%ecx + 42ce58: 74 26 je 42ce80 <__strcmp_ssse3+0x90> + 42ce5a: 77 07 ja 42ce63 <__strcmp_ssse3+0x73> + 42ce5c: 41 89 d0 mov %edx,%r8d + 42ce5f: 91 xchg %eax,%ecx + 42ce60: 48 87 f7 xchg %rsi,%rdi + 42ce63: 4c 8d 48 0f lea 0xf(%rax),%r9 + 42ce67: 49 29 c9 sub %rcx,%r9 + 42ce6a: 4c 8d 15 bf 63 07 00 lea 0x763bf(%rip),%r10 # 4a3230 + 42ce71: 4f 63 0c 8a movslq (%r10,%r9,4),%r9 + 42ce75: 4f 8d 14 0a lea (%r10,%r9,1),%r10 + 42ce79: 41 ff e2 jmpq *%r10 + 42ce7c: 0f 1f 40 00 nopl 0x0(%rax) + 42ce80: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42ce84: 66 0f ef c0 pxor %xmm0,%xmm0 + 42ce88: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42ce8c: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 + 42ce90: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42ce94: 66 44 0f d7 c9 pmovmskb %xmm1,%r9d + 42ce99: d3 ea shr %cl,%edx + 42ce9b: 41 d3 e9 shr %cl,%r9d + 42ce9e: 44 29 ca sub %r9d,%edx + 42cea1: 0f 85 5e 11 00 00 jne 42e005 <__strcmp_ssse3+0x1215> + 42cea7: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42ceae: 49 c7 c1 10 00 00 00 mov $0x10,%r9 + 42ceb5: 66 0f ef c0 pxor %xmm0,%xmm0 + 42ceb9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 42cec0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42cec5: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42ceca: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42cece: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42ced2: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42ced6: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42ceda: 81 ea ff ff 00 00 sub $0xffff,%edx + 42cee0: 0f 85 1a 11 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42cee6: 48 83 c1 10 add $0x10,%rcx + 42ceea: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42ceef: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42cef4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42cef8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42cefc: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42cf00: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42cf04: 81 ea ff ff 00 00 sub $0xffff,%edx + 42cf0a: 0f 85 f0 10 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42cf10: 48 83 c1 10 add $0x10,%rcx + 42cf14: eb aa jmp 42cec0 <__strcmp_ssse3+0xd0> + 42cf16: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42cf1d: 00 00 00 + 42cf20: 66 0f ef c0 pxor %xmm0,%xmm0 + 42cf24: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 42cf28: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42cf2c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42cf30: 66 0f 73 fa 0f pslldq $0xf,%xmm2 + 42cf35: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42cf39: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42cf3d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 42cf42: d3 ea shr %cl,%edx + 42cf44: 41 d3 e9 shr %cl,%r9d + 42cf47: 44 29 ca sub %r9d,%edx + 42cf4a: 0f 85 b5 10 00 00 jne 42e005 <__strcmp_ssse3+0x1215> + 42cf50: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 42cf54: 66 0f ef c0 pxor %xmm0,%xmm0 + 42cf58: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42cf5f: 41 b9 01 00 00 00 mov $0x1,%r9d + 42cf65: 4c 8d 57 01 lea 0x1(%rdi),%r10 + 42cf69: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42cf70: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42cf77: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 42cf7e: 00 00 + 42cf80: 49 83 c2 10 add $0x10,%r10 + 42cf84: 7f 7a jg 42d000 <__strcmp_ssse3+0x210> + 42cf86: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42cf8b: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42cf90: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42cf94: 66 0f 3a 0f d3 01 palignr $0x1,%xmm3,%xmm2 + 42cf9a: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42cf9e: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42cfa2: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42cfa6: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42cfaa: 81 ea ff ff 00 00 sub $0xffff,%edx + 42cfb0: 0f 85 4a 10 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42cfb6: 48 83 c1 10 add $0x10,%rcx + 42cfba: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42cfbe: 49 83 c2 10 add $0x10,%r10 + 42cfc2: 7f 3c jg 42d000 <__strcmp_ssse3+0x210> + 42cfc4: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42cfc9: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42cfce: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42cfd2: 66 0f 3a 0f d3 01 palignr $0x1,%xmm3,%xmm2 + 42cfd8: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42cfdc: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42cfe0: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42cfe4: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42cfe8: 81 ea ff ff 00 00 sub $0xffff,%edx + 42cfee: 0f 85 0c 10 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42cff4: 48 83 c1 10 add $0x10,%rcx + 42cff8: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42cffc: eb 82 jmp 42cf80 <__strcmp_ssse3+0x190> + 42cffe: 66 90 xchg %ax,%ax + 42d000: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 42d004: 66 0f d7 d0 pmovmskb %xmm0,%edx + 42d008: f7 c2 fe ff 00 00 test $0xfffe,%edx + 42d00e: 75 10 jne 42d020 <__strcmp_ssse3+0x230> + 42d010: 66 0f ef c0 pxor %xmm0,%xmm0 + 42d014: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42d01b: e9 66 ff ff ff jmpq 42cf86 <__strcmp_ssse3+0x196> + 42d020: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42d025: 66 0f 73 d8 01 psrldq $0x1,%xmm0 + 42d02a: 66 0f 73 db 01 psrldq $0x1,%xmm3 + 42d02f: e9 bc 0f 00 00 jmpq 42dff0 <__strcmp_ssse3+0x1200> + 42d034: 66 90 xchg %ax,%ax + 42d036: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42d03d: 00 00 00 + 42d040: 66 0f ef c0 pxor %xmm0,%xmm0 + 42d044: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 42d048: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42d04c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42d050: 66 0f 73 fa 0e pslldq $0xe,%xmm2 + 42d055: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42d059: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42d05d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 42d062: d3 ea shr %cl,%edx + 42d064: 41 d3 e9 shr %cl,%r9d + 42d067: 44 29 ca sub %r9d,%edx + 42d06a: 0f 85 95 0f 00 00 jne 42e005 <__strcmp_ssse3+0x1215> + 42d070: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 42d074: 66 0f ef c0 pxor %xmm0,%xmm0 + 42d078: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42d07f: 41 b9 02 00 00 00 mov $0x2,%r9d + 42d085: 4c 8d 57 02 lea 0x2(%rdi),%r10 + 42d089: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42d090: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42d097: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 42d09e: 00 00 + 42d0a0: 49 83 c2 10 add $0x10,%r10 + 42d0a4: 7f 7a jg 42d120 <__strcmp_ssse3+0x330> + 42d0a6: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42d0ab: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42d0b0: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42d0b4: 66 0f 3a 0f d3 02 palignr $0x2,%xmm3,%xmm2 + 42d0ba: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42d0be: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42d0c2: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42d0c6: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42d0ca: 81 ea ff ff 00 00 sub $0xffff,%edx + 42d0d0: 0f 85 2a 0f 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42d0d6: 48 83 c1 10 add $0x10,%rcx + 42d0da: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42d0de: 49 83 c2 10 add $0x10,%r10 + 42d0e2: 7f 3c jg 42d120 <__strcmp_ssse3+0x330> + 42d0e4: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42d0e9: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42d0ee: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42d0f2: 66 0f 3a 0f d3 02 palignr $0x2,%xmm3,%xmm2 + 42d0f8: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42d0fc: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42d100: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42d104: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42d108: 81 ea ff ff 00 00 sub $0xffff,%edx + 42d10e: 0f 85 ec 0e 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42d114: 48 83 c1 10 add $0x10,%rcx + 42d118: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42d11c: eb 82 jmp 42d0a0 <__strcmp_ssse3+0x2b0> + 42d11e: 66 90 xchg %ax,%ax + 42d120: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 42d124: 66 0f d7 d0 pmovmskb %xmm0,%edx + 42d128: f7 c2 fc ff 00 00 test $0xfffc,%edx + 42d12e: 75 10 jne 42d140 <__strcmp_ssse3+0x350> + 42d130: 66 0f ef c0 pxor %xmm0,%xmm0 + 42d134: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42d13b: e9 66 ff ff ff jmpq 42d0a6 <__strcmp_ssse3+0x2b6> + 42d140: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42d145: 66 0f 73 d8 02 psrldq $0x2,%xmm0 + 42d14a: 66 0f 73 db 02 psrldq $0x2,%xmm3 + 42d14f: e9 9c 0e 00 00 jmpq 42dff0 <__strcmp_ssse3+0x1200> + 42d154: 66 90 xchg %ax,%ax + 42d156: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42d15d: 00 00 00 + 42d160: 66 0f ef c0 pxor %xmm0,%xmm0 + 42d164: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 42d168: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42d16c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42d170: 66 0f 73 fa 0d pslldq $0xd,%xmm2 + 42d175: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42d179: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42d17d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 42d182: d3 ea shr %cl,%edx + 42d184: 41 d3 e9 shr %cl,%r9d + 42d187: 44 29 ca sub %r9d,%edx + 42d18a: 0f 85 75 0e 00 00 jne 42e005 <__strcmp_ssse3+0x1215> + 42d190: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 42d194: 66 0f ef c0 pxor %xmm0,%xmm0 + 42d198: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42d19f: 41 b9 03 00 00 00 mov $0x3,%r9d + 42d1a5: 4c 8d 57 03 lea 0x3(%rdi),%r10 + 42d1a9: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42d1b0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42d1b7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 42d1be: 00 00 + 42d1c0: 49 83 c2 10 add $0x10,%r10 + 42d1c4: 7f 7a jg 42d240 <__strcmp_ssse3+0x450> + 42d1c6: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42d1cb: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42d1d0: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42d1d4: 66 0f 3a 0f d3 03 palignr $0x3,%xmm3,%xmm2 + 42d1da: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42d1de: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42d1e2: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42d1e6: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42d1ea: 81 ea ff ff 00 00 sub $0xffff,%edx + 42d1f0: 0f 85 0a 0e 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42d1f6: 48 83 c1 10 add $0x10,%rcx + 42d1fa: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42d1fe: 49 83 c2 10 add $0x10,%r10 + 42d202: 7f 3c jg 42d240 <__strcmp_ssse3+0x450> + 42d204: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42d209: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42d20e: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42d212: 66 0f 3a 0f d3 03 palignr $0x3,%xmm3,%xmm2 + 42d218: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42d21c: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42d220: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42d224: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42d228: 81 ea ff ff 00 00 sub $0xffff,%edx + 42d22e: 0f 85 cc 0d 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42d234: 48 83 c1 10 add $0x10,%rcx + 42d238: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42d23c: eb 82 jmp 42d1c0 <__strcmp_ssse3+0x3d0> + 42d23e: 66 90 xchg %ax,%ax + 42d240: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 42d244: 66 0f d7 d0 pmovmskb %xmm0,%edx + 42d248: f7 c2 f8 ff 00 00 test $0xfff8,%edx + 42d24e: 75 10 jne 42d260 <__strcmp_ssse3+0x470> + 42d250: 66 0f ef c0 pxor %xmm0,%xmm0 + 42d254: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42d25b: e9 66 ff ff ff jmpq 42d1c6 <__strcmp_ssse3+0x3d6> + 42d260: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42d265: 66 0f 73 d8 03 psrldq $0x3,%xmm0 + 42d26a: 66 0f 73 db 03 psrldq $0x3,%xmm3 + 42d26f: e9 7c 0d 00 00 jmpq 42dff0 <__strcmp_ssse3+0x1200> + 42d274: 66 90 xchg %ax,%ax + 42d276: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42d27d: 00 00 00 + 42d280: 66 0f ef c0 pxor %xmm0,%xmm0 + 42d284: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 42d288: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42d28c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42d290: 66 0f 73 fa 0c pslldq $0xc,%xmm2 + 42d295: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42d299: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42d29d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 42d2a2: d3 ea shr %cl,%edx + 42d2a4: 41 d3 e9 shr %cl,%r9d + 42d2a7: 44 29 ca sub %r9d,%edx + 42d2aa: 0f 85 55 0d 00 00 jne 42e005 <__strcmp_ssse3+0x1215> + 42d2b0: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 42d2b4: 66 0f ef c0 pxor %xmm0,%xmm0 + 42d2b8: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42d2bf: 41 b9 04 00 00 00 mov $0x4,%r9d + 42d2c5: 4c 8d 57 04 lea 0x4(%rdi),%r10 + 42d2c9: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42d2d0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42d2d7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 42d2de: 00 00 + 42d2e0: 49 83 c2 10 add $0x10,%r10 + 42d2e4: 7f 7a jg 42d360 <__strcmp_ssse3+0x570> + 42d2e6: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42d2eb: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42d2f0: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42d2f4: 66 0f 3a 0f d3 04 palignr $0x4,%xmm3,%xmm2 + 42d2fa: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42d2fe: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42d302: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42d306: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42d30a: 81 ea ff ff 00 00 sub $0xffff,%edx + 42d310: 0f 85 ea 0c 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42d316: 48 83 c1 10 add $0x10,%rcx + 42d31a: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42d31e: 49 83 c2 10 add $0x10,%r10 + 42d322: 7f 3c jg 42d360 <__strcmp_ssse3+0x570> + 42d324: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42d329: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42d32e: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42d332: 66 0f 3a 0f d3 04 palignr $0x4,%xmm3,%xmm2 + 42d338: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42d33c: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42d340: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42d344: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42d348: 81 ea ff ff 00 00 sub $0xffff,%edx + 42d34e: 0f 85 ac 0c 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42d354: 48 83 c1 10 add $0x10,%rcx + 42d358: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42d35c: eb 82 jmp 42d2e0 <__strcmp_ssse3+0x4f0> + 42d35e: 66 90 xchg %ax,%ax + 42d360: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 42d364: 66 0f d7 d0 pmovmskb %xmm0,%edx + 42d368: f7 c2 f0 ff 00 00 test $0xfff0,%edx + 42d36e: 75 10 jne 42d380 <__strcmp_ssse3+0x590> + 42d370: 66 0f ef c0 pxor %xmm0,%xmm0 + 42d374: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42d37b: e9 66 ff ff ff jmpq 42d2e6 <__strcmp_ssse3+0x4f6> + 42d380: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42d385: 66 0f 73 d8 04 psrldq $0x4,%xmm0 + 42d38a: 66 0f 73 db 04 psrldq $0x4,%xmm3 + 42d38f: e9 5c 0c 00 00 jmpq 42dff0 <__strcmp_ssse3+0x1200> + 42d394: 66 90 xchg %ax,%ax + 42d396: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42d39d: 00 00 00 + 42d3a0: 66 0f ef c0 pxor %xmm0,%xmm0 + 42d3a4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 42d3a8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42d3ac: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42d3b0: 66 0f 73 fa 0b pslldq $0xb,%xmm2 + 42d3b5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42d3b9: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42d3bd: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 42d3c2: d3 ea shr %cl,%edx + 42d3c4: 41 d3 e9 shr %cl,%r9d + 42d3c7: 44 29 ca sub %r9d,%edx + 42d3ca: 0f 85 35 0c 00 00 jne 42e005 <__strcmp_ssse3+0x1215> + 42d3d0: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 42d3d4: 66 0f ef c0 pxor %xmm0,%xmm0 + 42d3d8: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42d3df: 41 b9 05 00 00 00 mov $0x5,%r9d + 42d3e5: 4c 8d 57 05 lea 0x5(%rdi),%r10 + 42d3e9: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42d3f0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42d3f7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 42d3fe: 00 00 + 42d400: 49 83 c2 10 add $0x10,%r10 + 42d404: 7f 7a jg 42d480 <__strcmp_ssse3+0x690> + 42d406: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42d40b: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42d410: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42d414: 66 0f 3a 0f d3 05 palignr $0x5,%xmm3,%xmm2 + 42d41a: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42d41e: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42d422: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42d426: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42d42a: 81 ea ff ff 00 00 sub $0xffff,%edx + 42d430: 0f 85 ca 0b 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42d436: 48 83 c1 10 add $0x10,%rcx + 42d43a: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42d43e: 49 83 c2 10 add $0x10,%r10 + 42d442: 7f 3c jg 42d480 <__strcmp_ssse3+0x690> + 42d444: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42d449: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42d44e: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42d452: 66 0f 3a 0f d3 05 palignr $0x5,%xmm3,%xmm2 + 42d458: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42d45c: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42d460: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42d464: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42d468: 81 ea ff ff 00 00 sub $0xffff,%edx + 42d46e: 0f 85 8c 0b 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42d474: 48 83 c1 10 add $0x10,%rcx + 42d478: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42d47c: eb 82 jmp 42d400 <__strcmp_ssse3+0x610> + 42d47e: 66 90 xchg %ax,%ax + 42d480: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 42d484: 66 0f d7 d0 pmovmskb %xmm0,%edx + 42d488: f7 c2 e0 ff 00 00 test $0xffe0,%edx + 42d48e: 75 10 jne 42d4a0 <__strcmp_ssse3+0x6b0> + 42d490: 66 0f ef c0 pxor %xmm0,%xmm0 + 42d494: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42d49b: e9 66 ff ff ff jmpq 42d406 <__strcmp_ssse3+0x616> + 42d4a0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42d4a5: 66 0f 73 d8 05 psrldq $0x5,%xmm0 + 42d4aa: 66 0f 73 db 05 psrldq $0x5,%xmm3 + 42d4af: e9 3c 0b 00 00 jmpq 42dff0 <__strcmp_ssse3+0x1200> + 42d4b4: 66 90 xchg %ax,%ax + 42d4b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42d4bd: 00 00 00 + 42d4c0: 66 0f ef c0 pxor %xmm0,%xmm0 + 42d4c4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 42d4c8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42d4cc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42d4d0: 66 0f 73 fa 0a pslldq $0xa,%xmm2 + 42d4d5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42d4d9: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42d4dd: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 42d4e2: d3 ea shr %cl,%edx + 42d4e4: 41 d3 e9 shr %cl,%r9d + 42d4e7: 44 29 ca sub %r9d,%edx + 42d4ea: 0f 85 15 0b 00 00 jne 42e005 <__strcmp_ssse3+0x1215> + 42d4f0: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 42d4f4: 66 0f ef c0 pxor %xmm0,%xmm0 + 42d4f8: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42d4ff: 41 b9 06 00 00 00 mov $0x6,%r9d + 42d505: 4c 8d 57 06 lea 0x6(%rdi),%r10 + 42d509: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42d510: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42d517: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 42d51e: 00 00 + 42d520: 49 83 c2 10 add $0x10,%r10 + 42d524: 7f 7a jg 42d5a0 <__strcmp_ssse3+0x7b0> + 42d526: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42d52b: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42d530: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42d534: 66 0f 3a 0f d3 06 palignr $0x6,%xmm3,%xmm2 + 42d53a: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42d53e: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42d542: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42d546: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42d54a: 81 ea ff ff 00 00 sub $0xffff,%edx + 42d550: 0f 85 aa 0a 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42d556: 48 83 c1 10 add $0x10,%rcx + 42d55a: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42d55e: 49 83 c2 10 add $0x10,%r10 + 42d562: 7f 3c jg 42d5a0 <__strcmp_ssse3+0x7b0> + 42d564: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42d569: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42d56e: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42d572: 66 0f 3a 0f d3 06 palignr $0x6,%xmm3,%xmm2 + 42d578: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42d57c: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42d580: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42d584: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42d588: 81 ea ff ff 00 00 sub $0xffff,%edx + 42d58e: 0f 85 6c 0a 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42d594: 48 83 c1 10 add $0x10,%rcx + 42d598: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42d59c: eb 82 jmp 42d520 <__strcmp_ssse3+0x730> + 42d59e: 66 90 xchg %ax,%ax + 42d5a0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 42d5a4: 66 0f d7 d0 pmovmskb %xmm0,%edx + 42d5a8: f7 c2 c0 ff 00 00 test $0xffc0,%edx + 42d5ae: 75 10 jne 42d5c0 <__strcmp_ssse3+0x7d0> + 42d5b0: 66 0f ef c0 pxor %xmm0,%xmm0 + 42d5b4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42d5bb: e9 66 ff ff ff jmpq 42d526 <__strcmp_ssse3+0x736> + 42d5c0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42d5c5: 66 0f 73 d8 06 psrldq $0x6,%xmm0 + 42d5ca: 66 0f 73 db 06 psrldq $0x6,%xmm3 + 42d5cf: e9 1c 0a 00 00 jmpq 42dff0 <__strcmp_ssse3+0x1200> + 42d5d4: 66 90 xchg %ax,%ax + 42d5d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42d5dd: 00 00 00 + 42d5e0: 66 0f ef c0 pxor %xmm0,%xmm0 + 42d5e4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 42d5e8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42d5ec: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42d5f0: 66 0f 73 fa 09 pslldq $0x9,%xmm2 + 42d5f5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42d5f9: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42d5fd: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 42d602: d3 ea shr %cl,%edx + 42d604: 41 d3 e9 shr %cl,%r9d + 42d607: 44 29 ca sub %r9d,%edx + 42d60a: 0f 85 f5 09 00 00 jne 42e005 <__strcmp_ssse3+0x1215> + 42d610: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 42d614: 66 0f ef c0 pxor %xmm0,%xmm0 + 42d618: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42d61f: 41 b9 07 00 00 00 mov $0x7,%r9d + 42d625: 4c 8d 57 07 lea 0x7(%rdi),%r10 + 42d629: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42d630: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42d637: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 42d63e: 00 00 + 42d640: 49 83 c2 10 add $0x10,%r10 + 42d644: 7f 7a jg 42d6c0 <__strcmp_ssse3+0x8d0> + 42d646: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42d64b: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42d650: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42d654: 66 0f 3a 0f d3 07 palignr $0x7,%xmm3,%xmm2 + 42d65a: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42d65e: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42d662: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42d666: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42d66a: 81 ea ff ff 00 00 sub $0xffff,%edx + 42d670: 0f 85 8a 09 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42d676: 48 83 c1 10 add $0x10,%rcx + 42d67a: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42d67e: 49 83 c2 10 add $0x10,%r10 + 42d682: 7f 3c jg 42d6c0 <__strcmp_ssse3+0x8d0> + 42d684: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42d689: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42d68e: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42d692: 66 0f 3a 0f d3 07 palignr $0x7,%xmm3,%xmm2 + 42d698: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42d69c: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42d6a0: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42d6a4: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42d6a8: 81 ea ff ff 00 00 sub $0xffff,%edx + 42d6ae: 0f 85 4c 09 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42d6b4: 48 83 c1 10 add $0x10,%rcx + 42d6b8: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42d6bc: eb 82 jmp 42d640 <__strcmp_ssse3+0x850> + 42d6be: 66 90 xchg %ax,%ax + 42d6c0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 42d6c4: 66 0f d7 d0 pmovmskb %xmm0,%edx + 42d6c8: f7 c2 80 ff 00 00 test $0xff80,%edx + 42d6ce: 75 10 jne 42d6e0 <__strcmp_ssse3+0x8f0> + 42d6d0: 66 0f ef c0 pxor %xmm0,%xmm0 + 42d6d4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42d6db: e9 66 ff ff ff jmpq 42d646 <__strcmp_ssse3+0x856> + 42d6e0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42d6e5: 66 0f 73 d8 07 psrldq $0x7,%xmm0 + 42d6ea: 66 0f 73 db 07 psrldq $0x7,%xmm3 + 42d6ef: e9 fc 08 00 00 jmpq 42dff0 <__strcmp_ssse3+0x1200> + 42d6f4: 66 90 xchg %ax,%ax + 42d6f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42d6fd: 00 00 00 + 42d700: 66 0f ef c0 pxor %xmm0,%xmm0 + 42d704: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 42d708: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42d70c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42d710: 66 0f 73 fa 08 pslldq $0x8,%xmm2 + 42d715: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42d719: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42d71d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 42d722: d3 ea shr %cl,%edx + 42d724: 41 d3 e9 shr %cl,%r9d + 42d727: 44 29 ca sub %r9d,%edx + 42d72a: 0f 85 d5 08 00 00 jne 42e005 <__strcmp_ssse3+0x1215> + 42d730: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 42d734: 66 0f ef c0 pxor %xmm0,%xmm0 + 42d738: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42d73f: 41 b9 08 00 00 00 mov $0x8,%r9d + 42d745: 4c 8d 57 08 lea 0x8(%rdi),%r10 + 42d749: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42d750: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42d757: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 42d75e: 00 00 + 42d760: 49 83 c2 10 add $0x10,%r10 + 42d764: 7f 7a jg 42d7e0 <__strcmp_ssse3+0x9f0> + 42d766: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42d76b: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42d770: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42d774: 66 0f 3a 0f d3 08 palignr $0x8,%xmm3,%xmm2 + 42d77a: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42d77e: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42d782: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42d786: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42d78a: 81 ea ff ff 00 00 sub $0xffff,%edx + 42d790: 0f 85 6a 08 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42d796: 48 83 c1 10 add $0x10,%rcx + 42d79a: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42d79e: 49 83 c2 10 add $0x10,%r10 + 42d7a2: 7f 3c jg 42d7e0 <__strcmp_ssse3+0x9f0> + 42d7a4: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42d7a9: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42d7ae: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42d7b2: 66 0f 3a 0f d3 08 palignr $0x8,%xmm3,%xmm2 + 42d7b8: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42d7bc: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42d7c0: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42d7c4: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42d7c8: 81 ea ff ff 00 00 sub $0xffff,%edx + 42d7ce: 0f 85 2c 08 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42d7d4: 48 83 c1 10 add $0x10,%rcx + 42d7d8: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42d7dc: eb 82 jmp 42d760 <__strcmp_ssse3+0x970> + 42d7de: 66 90 xchg %ax,%ax + 42d7e0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 42d7e4: 66 0f d7 d0 pmovmskb %xmm0,%edx + 42d7e8: f7 c2 00 ff 00 00 test $0xff00,%edx + 42d7ee: 75 10 jne 42d800 <__strcmp_ssse3+0xa10> + 42d7f0: 66 0f ef c0 pxor %xmm0,%xmm0 + 42d7f4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42d7fb: e9 66 ff ff ff jmpq 42d766 <__strcmp_ssse3+0x976> + 42d800: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42d805: 66 0f 73 d8 08 psrldq $0x8,%xmm0 + 42d80a: 66 0f 73 db 08 psrldq $0x8,%xmm3 + 42d80f: e9 dc 07 00 00 jmpq 42dff0 <__strcmp_ssse3+0x1200> + 42d814: 66 90 xchg %ax,%ax + 42d816: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42d81d: 00 00 00 + 42d820: 66 0f ef c0 pxor %xmm0,%xmm0 + 42d824: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 42d828: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42d82c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42d830: 66 0f 73 fa 07 pslldq $0x7,%xmm2 + 42d835: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42d839: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42d83d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 42d842: d3 ea shr %cl,%edx + 42d844: 41 d3 e9 shr %cl,%r9d + 42d847: 44 29 ca sub %r9d,%edx + 42d84a: 0f 85 b5 07 00 00 jne 42e005 <__strcmp_ssse3+0x1215> + 42d850: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 42d854: 66 0f ef c0 pxor %xmm0,%xmm0 + 42d858: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42d85f: 41 b9 09 00 00 00 mov $0x9,%r9d + 42d865: 4c 8d 57 09 lea 0x9(%rdi),%r10 + 42d869: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42d870: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42d877: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 42d87e: 00 00 + 42d880: 49 83 c2 10 add $0x10,%r10 + 42d884: 7f 7a jg 42d900 <__strcmp_ssse3+0xb10> + 42d886: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42d88b: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42d890: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42d894: 66 0f 3a 0f d3 09 palignr $0x9,%xmm3,%xmm2 + 42d89a: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42d89e: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42d8a2: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42d8a6: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42d8aa: 81 ea ff ff 00 00 sub $0xffff,%edx + 42d8b0: 0f 85 4a 07 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42d8b6: 48 83 c1 10 add $0x10,%rcx + 42d8ba: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42d8be: 49 83 c2 10 add $0x10,%r10 + 42d8c2: 7f 3c jg 42d900 <__strcmp_ssse3+0xb10> + 42d8c4: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42d8c9: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42d8ce: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42d8d2: 66 0f 3a 0f d3 09 palignr $0x9,%xmm3,%xmm2 + 42d8d8: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42d8dc: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42d8e0: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42d8e4: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42d8e8: 81 ea ff ff 00 00 sub $0xffff,%edx + 42d8ee: 0f 85 0c 07 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42d8f4: 48 83 c1 10 add $0x10,%rcx + 42d8f8: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42d8fc: eb 82 jmp 42d880 <__strcmp_ssse3+0xa90> + 42d8fe: 66 90 xchg %ax,%ax + 42d900: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 42d904: 66 0f d7 d0 pmovmskb %xmm0,%edx + 42d908: f7 c2 00 fe 00 00 test $0xfe00,%edx + 42d90e: 75 10 jne 42d920 <__strcmp_ssse3+0xb30> + 42d910: 66 0f ef c0 pxor %xmm0,%xmm0 + 42d914: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42d91b: e9 66 ff ff ff jmpq 42d886 <__strcmp_ssse3+0xa96> + 42d920: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42d925: 66 0f 73 d8 09 psrldq $0x9,%xmm0 + 42d92a: 66 0f 73 db 09 psrldq $0x9,%xmm3 + 42d92f: e9 bc 06 00 00 jmpq 42dff0 <__strcmp_ssse3+0x1200> + 42d934: 66 90 xchg %ax,%ax + 42d936: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42d93d: 00 00 00 + 42d940: 66 0f ef c0 pxor %xmm0,%xmm0 + 42d944: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 42d948: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42d94c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42d950: 66 0f 73 fa 06 pslldq $0x6,%xmm2 + 42d955: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42d959: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42d95d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 42d962: d3 ea shr %cl,%edx + 42d964: 41 d3 e9 shr %cl,%r9d + 42d967: 44 29 ca sub %r9d,%edx + 42d96a: 0f 85 95 06 00 00 jne 42e005 <__strcmp_ssse3+0x1215> + 42d970: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 42d974: 66 0f ef c0 pxor %xmm0,%xmm0 + 42d978: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42d97f: 41 b9 0a 00 00 00 mov $0xa,%r9d + 42d985: 4c 8d 57 0a lea 0xa(%rdi),%r10 + 42d989: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42d990: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42d997: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 42d99e: 00 00 + 42d9a0: 49 83 c2 10 add $0x10,%r10 + 42d9a4: 7f 7a jg 42da20 <__strcmp_ssse3+0xc30> + 42d9a6: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42d9ab: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42d9b0: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42d9b4: 66 0f 3a 0f d3 0a palignr $0xa,%xmm3,%xmm2 + 42d9ba: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42d9be: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42d9c2: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42d9c6: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42d9ca: 81 ea ff ff 00 00 sub $0xffff,%edx + 42d9d0: 0f 85 2a 06 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42d9d6: 48 83 c1 10 add $0x10,%rcx + 42d9da: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42d9de: 49 83 c2 10 add $0x10,%r10 + 42d9e2: 7f 3c jg 42da20 <__strcmp_ssse3+0xc30> + 42d9e4: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42d9e9: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42d9ee: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42d9f2: 66 0f 3a 0f d3 0a palignr $0xa,%xmm3,%xmm2 + 42d9f8: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42d9fc: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42da00: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42da04: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42da08: 81 ea ff ff 00 00 sub $0xffff,%edx + 42da0e: 0f 85 ec 05 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42da14: 48 83 c1 10 add $0x10,%rcx + 42da18: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42da1c: eb 82 jmp 42d9a0 <__strcmp_ssse3+0xbb0> + 42da1e: 66 90 xchg %ax,%ax + 42da20: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 42da24: 66 0f d7 d0 pmovmskb %xmm0,%edx + 42da28: f7 c2 00 fc 00 00 test $0xfc00,%edx + 42da2e: 75 10 jne 42da40 <__strcmp_ssse3+0xc50> + 42da30: 66 0f ef c0 pxor %xmm0,%xmm0 + 42da34: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42da3b: e9 66 ff ff ff jmpq 42d9a6 <__strcmp_ssse3+0xbb6> + 42da40: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42da45: 66 0f 73 d8 0a psrldq $0xa,%xmm0 + 42da4a: 66 0f 73 db 0a psrldq $0xa,%xmm3 + 42da4f: e9 9c 05 00 00 jmpq 42dff0 <__strcmp_ssse3+0x1200> + 42da54: 66 90 xchg %ax,%ax + 42da56: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42da5d: 00 00 00 + 42da60: 66 0f ef c0 pxor %xmm0,%xmm0 + 42da64: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 42da68: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42da6c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42da70: 66 0f 73 fa 05 pslldq $0x5,%xmm2 + 42da75: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42da79: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42da7d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 42da82: d3 ea shr %cl,%edx + 42da84: 41 d3 e9 shr %cl,%r9d + 42da87: 44 29 ca sub %r9d,%edx + 42da8a: 0f 85 75 05 00 00 jne 42e005 <__strcmp_ssse3+0x1215> + 42da90: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 42da94: 66 0f ef c0 pxor %xmm0,%xmm0 + 42da98: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42da9f: 41 b9 0b 00 00 00 mov $0xb,%r9d + 42daa5: 4c 8d 57 0b lea 0xb(%rdi),%r10 + 42daa9: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42dab0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42dab7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 42dabe: 00 00 + 42dac0: 49 83 c2 10 add $0x10,%r10 + 42dac4: 7f 7a jg 42db40 <__strcmp_ssse3+0xd50> + 42dac6: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42dacb: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42dad0: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42dad4: 66 0f 3a 0f d3 0b palignr $0xb,%xmm3,%xmm2 + 42dada: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42dade: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42dae2: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42dae6: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42daea: 81 ea ff ff 00 00 sub $0xffff,%edx + 42daf0: 0f 85 0a 05 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42daf6: 48 83 c1 10 add $0x10,%rcx + 42dafa: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42dafe: 49 83 c2 10 add $0x10,%r10 + 42db02: 7f 3c jg 42db40 <__strcmp_ssse3+0xd50> + 42db04: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42db09: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42db0e: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42db12: 66 0f 3a 0f d3 0b palignr $0xb,%xmm3,%xmm2 + 42db18: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42db1c: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42db20: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42db24: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42db28: 81 ea ff ff 00 00 sub $0xffff,%edx + 42db2e: 0f 85 cc 04 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42db34: 48 83 c1 10 add $0x10,%rcx + 42db38: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42db3c: eb 82 jmp 42dac0 <__strcmp_ssse3+0xcd0> + 42db3e: 66 90 xchg %ax,%ax + 42db40: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 42db44: 66 0f d7 d0 pmovmskb %xmm0,%edx + 42db48: f7 c2 00 f8 00 00 test $0xf800,%edx + 42db4e: 75 10 jne 42db60 <__strcmp_ssse3+0xd70> + 42db50: 66 0f ef c0 pxor %xmm0,%xmm0 + 42db54: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42db5b: e9 66 ff ff ff jmpq 42dac6 <__strcmp_ssse3+0xcd6> + 42db60: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42db65: 66 0f 73 d8 0b psrldq $0xb,%xmm0 + 42db6a: 66 0f 73 db 0b psrldq $0xb,%xmm3 + 42db6f: e9 7c 04 00 00 jmpq 42dff0 <__strcmp_ssse3+0x1200> + 42db74: 66 90 xchg %ax,%ax + 42db76: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42db7d: 00 00 00 + 42db80: 66 0f ef c0 pxor %xmm0,%xmm0 + 42db84: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 42db88: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42db8c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42db90: 66 0f 73 fa 04 pslldq $0x4,%xmm2 + 42db95: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42db99: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42db9d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 42dba2: d3 ea shr %cl,%edx + 42dba4: 41 d3 e9 shr %cl,%r9d + 42dba7: 44 29 ca sub %r9d,%edx + 42dbaa: 0f 85 55 04 00 00 jne 42e005 <__strcmp_ssse3+0x1215> + 42dbb0: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 42dbb4: 66 0f ef c0 pxor %xmm0,%xmm0 + 42dbb8: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42dbbf: 41 b9 0c 00 00 00 mov $0xc,%r9d + 42dbc5: 4c 8d 57 0c lea 0xc(%rdi),%r10 + 42dbc9: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42dbd0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42dbd7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 42dbde: 00 00 + 42dbe0: 49 83 c2 10 add $0x10,%r10 + 42dbe4: 7f 7a jg 42dc60 <__strcmp_ssse3+0xe70> + 42dbe6: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42dbeb: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42dbf0: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42dbf4: 66 0f 3a 0f d3 0c palignr $0xc,%xmm3,%xmm2 + 42dbfa: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42dbfe: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42dc02: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42dc06: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42dc0a: 81 ea ff ff 00 00 sub $0xffff,%edx + 42dc10: 0f 85 ea 03 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42dc16: 48 83 c1 10 add $0x10,%rcx + 42dc1a: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42dc1e: 49 83 c2 10 add $0x10,%r10 + 42dc22: 7f 3c jg 42dc60 <__strcmp_ssse3+0xe70> + 42dc24: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42dc29: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42dc2e: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42dc32: 66 0f 3a 0f d3 0c palignr $0xc,%xmm3,%xmm2 + 42dc38: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42dc3c: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42dc40: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42dc44: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42dc48: 81 ea ff ff 00 00 sub $0xffff,%edx + 42dc4e: 0f 85 ac 03 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42dc54: 48 83 c1 10 add $0x10,%rcx + 42dc58: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42dc5c: eb 82 jmp 42dbe0 <__strcmp_ssse3+0xdf0> + 42dc5e: 66 90 xchg %ax,%ax + 42dc60: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 42dc64: 66 0f d7 d0 pmovmskb %xmm0,%edx + 42dc68: f7 c2 00 f0 00 00 test $0xf000,%edx + 42dc6e: 75 10 jne 42dc80 <__strcmp_ssse3+0xe90> + 42dc70: 66 0f ef c0 pxor %xmm0,%xmm0 + 42dc74: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42dc7b: e9 66 ff ff ff jmpq 42dbe6 <__strcmp_ssse3+0xdf6> + 42dc80: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42dc85: 66 0f 73 d8 0c psrldq $0xc,%xmm0 + 42dc8a: 66 0f 73 db 0c psrldq $0xc,%xmm3 + 42dc8f: e9 5c 03 00 00 jmpq 42dff0 <__strcmp_ssse3+0x1200> + 42dc94: 66 90 xchg %ax,%ax + 42dc96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42dc9d: 00 00 00 + 42dca0: 66 0f ef c0 pxor %xmm0,%xmm0 + 42dca4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 42dca8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42dcac: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42dcb0: 66 0f 73 fa 03 pslldq $0x3,%xmm2 + 42dcb5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42dcb9: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42dcbd: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 42dcc2: d3 ea shr %cl,%edx + 42dcc4: 41 d3 e9 shr %cl,%r9d + 42dcc7: 44 29 ca sub %r9d,%edx + 42dcca: 0f 85 35 03 00 00 jne 42e005 <__strcmp_ssse3+0x1215> + 42dcd0: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 42dcd4: 66 0f ef c0 pxor %xmm0,%xmm0 + 42dcd8: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42dcdf: 41 b9 0d 00 00 00 mov $0xd,%r9d + 42dce5: 4c 8d 57 0d lea 0xd(%rdi),%r10 + 42dce9: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42dcf0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42dcf7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 42dcfe: 00 00 + 42dd00: 49 83 c2 10 add $0x10,%r10 + 42dd04: 7f 7a jg 42dd80 <__strcmp_ssse3+0xf90> + 42dd06: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42dd0b: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42dd10: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42dd14: 66 0f 3a 0f d3 0d palignr $0xd,%xmm3,%xmm2 + 42dd1a: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42dd1e: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42dd22: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42dd26: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42dd2a: 81 ea ff ff 00 00 sub $0xffff,%edx + 42dd30: 0f 85 ca 02 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42dd36: 48 83 c1 10 add $0x10,%rcx + 42dd3a: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42dd3e: 49 83 c2 10 add $0x10,%r10 + 42dd42: 7f 3c jg 42dd80 <__strcmp_ssse3+0xf90> + 42dd44: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42dd49: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42dd4e: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42dd52: 66 0f 3a 0f d3 0d palignr $0xd,%xmm3,%xmm2 + 42dd58: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42dd5c: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42dd60: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42dd64: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42dd68: 81 ea ff ff 00 00 sub $0xffff,%edx + 42dd6e: 0f 85 8c 02 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42dd74: 48 83 c1 10 add $0x10,%rcx + 42dd78: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42dd7c: eb 82 jmp 42dd00 <__strcmp_ssse3+0xf10> + 42dd7e: 66 90 xchg %ax,%ax + 42dd80: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 42dd84: 66 0f d7 d0 pmovmskb %xmm0,%edx + 42dd88: f7 c2 00 e0 00 00 test $0xe000,%edx + 42dd8e: 75 10 jne 42dda0 <__strcmp_ssse3+0xfb0> + 42dd90: 66 0f ef c0 pxor %xmm0,%xmm0 + 42dd94: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42dd9b: e9 66 ff ff ff jmpq 42dd06 <__strcmp_ssse3+0xf16> + 42dda0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42dda5: 66 0f 73 d8 0d psrldq $0xd,%xmm0 + 42ddaa: 66 0f 73 db 0d psrldq $0xd,%xmm3 + 42ddaf: e9 3c 02 00 00 jmpq 42dff0 <__strcmp_ssse3+0x1200> + 42ddb4: 66 90 xchg %ax,%ax + 42ddb6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42ddbd: 00 00 00 + 42ddc0: 66 0f ef c0 pxor %xmm0,%xmm0 + 42ddc4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 42ddc8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42ddcc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42ddd0: 66 0f 73 fa 02 pslldq $0x2,%xmm2 + 42ddd5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42ddd9: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42dddd: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 42dde2: d3 ea shr %cl,%edx + 42dde4: 41 d3 e9 shr %cl,%r9d + 42dde7: 44 29 ca sub %r9d,%edx + 42ddea: 0f 85 15 02 00 00 jne 42e005 <__strcmp_ssse3+0x1215> + 42ddf0: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 42ddf4: 66 0f ef c0 pxor %xmm0,%xmm0 + 42ddf8: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42ddff: 41 b9 0e 00 00 00 mov $0xe,%r9d + 42de05: 4c 8d 57 0e lea 0xe(%rdi),%r10 + 42de09: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42de10: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42de17: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 42de1e: 00 00 + 42de20: 49 83 c2 10 add $0x10,%r10 + 42de24: 7f 7a jg 42dea0 <__strcmp_ssse3+0x10b0> + 42de26: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42de2b: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42de30: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42de34: 66 0f 3a 0f d3 0e palignr $0xe,%xmm3,%xmm2 + 42de3a: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42de3e: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42de42: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42de46: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42de4a: 81 ea ff ff 00 00 sub $0xffff,%edx + 42de50: 0f 85 aa 01 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42de56: 48 83 c1 10 add $0x10,%rcx + 42de5a: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42de5e: 49 83 c2 10 add $0x10,%r10 + 42de62: 7f 3c jg 42dea0 <__strcmp_ssse3+0x10b0> + 42de64: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42de69: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42de6e: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42de72: 66 0f 3a 0f d3 0e palignr $0xe,%xmm3,%xmm2 + 42de78: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42de7c: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42de80: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42de84: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42de88: 81 ea ff ff 00 00 sub $0xffff,%edx + 42de8e: 0f 85 6c 01 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42de94: 48 83 c1 10 add $0x10,%rcx + 42de98: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42de9c: eb 82 jmp 42de20 <__strcmp_ssse3+0x1030> + 42de9e: 66 90 xchg %ax,%ax + 42dea0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 42dea4: 66 0f d7 d0 pmovmskb %xmm0,%edx + 42dea8: f7 c2 00 c0 00 00 test $0xc000,%edx + 42deae: 75 10 jne 42dec0 <__strcmp_ssse3+0x10d0> + 42deb0: 66 0f ef c0 pxor %xmm0,%xmm0 + 42deb4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42debb: e9 66 ff ff ff jmpq 42de26 <__strcmp_ssse3+0x1036> + 42dec0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42dec5: 66 0f 73 d8 0e psrldq $0xe,%xmm0 + 42deca: 66 0f 73 db 0e psrldq $0xe,%xmm3 + 42decf: e9 1c 01 00 00 jmpq 42dff0 <__strcmp_ssse3+0x1200> + 42ded4: 66 90 xchg %ax,%ax + 42ded6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42dedd: 00 00 00 + 42dee0: 66 0f ef c0 pxor %xmm0,%xmm0 + 42dee4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 42dee8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42deec: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42def0: 66 0f 73 fa 01 pslldq $0x1,%xmm2 + 42def5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42def9: 66 0f f8 d0 psubb %xmm0,%xmm2 + 42defd: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 42df02: d3 ea shr %cl,%edx + 42df04: 41 d3 e9 shr %cl,%r9d + 42df07: 44 29 ca sub %r9d,%edx + 42df0a: 0f 85 f5 00 00 00 jne 42e005 <__strcmp_ssse3+0x1215> + 42df10: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 42df14: 66 0f ef c0 pxor %xmm0,%xmm0 + 42df18: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 42df1f: 41 b9 0f 00 00 00 mov $0xf,%r9d + 42df25: 4c 8d 57 0f lea 0xf(%rdi),%r10 + 42df29: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 42df30: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42df37: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 42df3e: 00 00 + 42df40: 49 83 c2 10 add $0x10,%r10 + 42df44: 7f 7a jg 42dfc0 <__strcmp_ssse3+0x11d0> + 42df46: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42df4b: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42df50: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42df54: 66 0f 3a 0f d3 0f palignr $0xf,%xmm3,%xmm2 + 42df5a: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42df5e: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42df62: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42df66: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42df6a: 81 ea ff ff 00 00 sub $0xffff,%edx + 42df70: 0f 85 8a 00 00 00 jne 42e000 <__strcmp_ssse3+0x1210> + 42df76: 48 83 c1 10 add $0x10,%rcx + 42df7a: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42df7e: 49 83 c2 10 add $0x10,%r10 + 42df82: 7f 3c jg 42dfc0 <__strcmp_ssse3+0x11d0> + 42df84: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42df89: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 42df8e: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 42df92: 66 0f 3a 0f d3 0f palignr $0xf,%xmm3,%xmm2 + 42df98: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42df9c: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 42dfa0: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42dfa4: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42dfa8: 81 ea ff ff 00 00 sub $0xffff,%edx + 42dfae: 75 50 jne 42e000 <__strcmp_ssse3+0x1210> + 42dfb0: 48 83 c1 10 add $0x10,%rcx + 42dfb4: 66 0f 6f dc movdqa %xmm4,%xmm3 + 42dfb8: eb 86 jmp 42df40 <__strcmp_ssse3+0x1150> + 42dfba: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 42dfc0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 42dfc4: 66 0f d7 d0 pmovmskb %xmm0,%edx + 42dfc8: f7 c2 00 80 00 00 test $0x8000,%edx + 42dfce: 75 10 jne 42dfe0 <__strcmp_ssse3+0x11f0> + 42dfd0: 66 0f ef c0 pxor %xmm0,%xmm0 + 42dfd4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 42dfdb: e9 66 ff ff ff jmpq 42df46 <__strcmp_ssse3+0x1156> + 42dfe0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 42dfe5: 66 0f 73 db 0f psrldq $0xf,%xmm3 + 42dfea: 66 0f 73 d8 0f psrldq $0xf,%xmm0 + 42dfef: 90 nop + 42dff0: 66 0f 74 cb pcmpeqb %xmm3,%xmm1 + 42dff4: 66 0f f8 c8 psubb %xmm0,%xmm1 + 42dff8: 66 0f d7 d1 pmovmskb %xmm1,%edx + 42dffc: f7 d2 not %edx + 42dffe: 66 90 xchg %ax,%ax + 42e000: 49 8d 44 09 f0 lea -0x10(%r9,%rcx,1),%rax + 42e005: 48 8d 3c 07 lea (%rdi,%rax,1),%rdi + 42e009: 48 8d 34 0e lea (%rsi,%rcx,1),%rsi + 42e00d: 45 85 c0 test %r8d,%r8d + 42e010: 74 0e je 42e020 <__strcmp_ssse3+0x1230> + 42e012: 48 87 f7 xchg %rsi,%rdi + 42e015: 90 nop + 42e016: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42e01d: 00 00 00 + 42e020: 48 0f bc d2 bsf %rdx,%rdx + 42e024: 0f b6 0c 16 movzbl (%rsi,%rdx,1),%ecx + 42e028: 0f b6 04 17 movzbl (%rdi,%rdx,1),%eax + 42e02c: 29 c8 sub %ecx,%eax + 42e02e: c3 retq + 42e02f: 31 c0 xor %eax,%eax + 42e031: c3 retq + 42e032: 0f 1f 40 00 nopl 0x0(%rax) + 42e036: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42e03d: 00 00 00 + 42e040: 0f b6 0e movzbl (%rsi),%ecx + 42e043: 0f b6 07 movzbl (%rdi),%eax + 42e046: 29 c8 sub %ecx,%eax + 42e048: c3 retq + 42e049: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + +000000000042e050 <__strcmp_sse2_unaligned>: + 42e050: 89 f8 mov %edi,%eax + 42e052: 31 d2 xor %edx,%edx + 42e054: 66 0f ef ff pxor %xmm7,%xmm7 + 42e058: 09 f0 or %esi,%eax + 42e05a: 25 ff 0f 00 00 and $0xfff,%eax + 42e05f: 3d c0 0f 00 00 cmp $0xfc0,%eax + 42e064: 0f 8f 78 02 00 00 jg 42e2e2 <__strcmp_sse2_unaligned+0x292> + 42e06a: f3 0f 6f 0f movdqu (%rdi),%xmm1 + 42e06e: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 42e072: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42e076: 66 0f da c1 pminub %xmm1,%xmm0 + 42e07a: 66 0f ef c9 pxor %xmm1,%xmm1 + 42e07e: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42e082: 66 0f d7 c0 pmovmskb %xmm0,%eax + 42e086: 48 85 c0 test %rax,%rax + 42e089: 74 15 je 42e0a0 <__strcmp_sse2_unaligned+0x50> + 42e08b: 48 0f bc d0 bsf %rax,%rdx + 42e08f: 0f b6 04 17 movzbl (%rdi,%rdx,1),%eax + 42e093: 0f b6 14 16 movzbl (%rsi,%rdx,1),%edx + 42e097: 29 d0 sub %edx,%eax + 42e099: c3 retq + 42e09a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 42e0a0: f3 0f 6f 77 10 movdqu 0x10(%rdi),%xmm6 + 42e0a5: f3 0f 6f 5e 10 movdqu 0x10(%rsi),%xmm3 + 42e0aa: f3 0f 6f 6f 20 movdqu 0x20(%rdi),%xmm5 + 42e0af: 66 0f 74 de pcmpeqb %xmm6,%xmm3 + 42e0b3: f3 0f 6f 56 20 movdqu 0x20(%rsi),%xmm2 + 42e0b8: 66 0f da de pminub %xmm6,%xmm3 + 42e0bc: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 + 42e0c0: f3 0f 6f 67 30 movdqu 0x30(%rdi),%xmm4 + 42e0c5: 66 0f 74 d5 pcmpeqb %xmm5,%xmm2 + 42e0c9: 66 0f d7 d3 pmovmskb %xmm3,%edx + 42e0cd: f3 0f 6f 46 30 movdqu 0x30(%rsi),%xmm0 + 42e0d2: 66 0f da d5 pminub %xmm5,%xmm2 + 42e0d6: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 42e0da: 66 0f 74 c4 pcmpeqb %xmm4,%xmm0 + 42e0de: 66 0f d7 c2 pmovmskb %xmm2,%eax + 42e0e2: 48 c1 e2 10 shl $0x10,%rdx + 42e0e6: 66 0f da c4 pminub %xmm4,%xmm0 + 42e0ea: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 42e0ee: 48 c1 e0 20 shl $0x20,%rax + 42e0f2: 48 09 d0 or %rdx,%rax + 42e0f5: 66 0f d7 c8 pmovmskb %xmm0,%ecx + 42e0f9: 48 89 ca mov %rcx,%rdx + 42e0fc: 48 c1 e2 30 shl $0x30,%rdx + 42e100: 48 09 d0 or %rdx,%rax + 42e103: 75 86 jne 42e08b <__strcmp_sse2_unaligned+0x3b> + 42e105: 48 8d 57 40 lea 0x40(%rdi),%rdx + 42e109: b9 00 10 00 00 mov $0x1000,%ecx + 42e10e: 66 45 0f ef c9 pxor %xmm9,%xmm9 + 42e113: 48 83 e2 c0 and $0xffffffffffffffc0,%rdx + 42e117: 48 29 fa sub %rdi,%rdx + 42e11a: 48 8d 04 17 lea (%rdi,%rdx,1),%rax + 42e11e: 48 01 f2 add %rsi,%rdx + 42e121: 48 89 d6 mov %rdx,%rsi + 42e124: 81 e6 ff 0f 00 00 and $0xfff,%esi + 42e12a: 48 29 f1 sub %rsi,%rcx + 42e12d: 48 c1 e9 06 shr $0x6,%rcx + 42e131: 48 89 ce mov %rcx,%rsi + 42e134: eb 12 jmp 42e148 <__strcmp_sse2_unaligned+0xf8> + 42e136: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42e13d: 00 00 00 + 42e140: 48 83 c0 40 add $0x40,%rax + 42e144: 48 83 c2 40 add $0x40,%rdx + 42e148: 48 85 f6 test %rsi,%rsi + 42e14b: 48 8d 76 ff lea -0x1(%rsi),%rsi + 42e14f: 0f 84 bb 00 00 00 je 42e210 <__strcmp_sse2_unaligned+0x1c0> + 42e155: f3 0f 6f 02 movdqu (%rdx),%xmm0 + 42e159: f3 0f 6f 4a 10 movdqu 0x10(%rdx),%xmm1 + 42e15e: 66 0f 6f 10 movdqa (%rax),%xmm2 + 42e162: 66 0f 6f 58 10 movdqa 0x10(%rax),%xmm3 + 42e167: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 42e16b: f3 0f 6f 6a 20 movdqu 0x20(%rdx),%xmm5 + 42e170: 66 0f 74 cb pcmpeqb %xmm3,%xmm1 + 42e174: 66 0f da c2 pminub %xmm2,%xmm0 + 42e178: f3 0f 6f 72 30 movdqu 0x30(%rdx),%xmm6 + 42e17d: 66 0f da cb pminub %xmm3,%xmm1 + 42e181: 66 0f 6f 50 20 movdqa 0x20(%rax),%xmm2 + 42e186: 66 0f da c1 pminub %xmm1,%xmm0 + 42e18a: 66 0f 6f 58 30 movdqa 0x30(%rax),%xmm3 + 42e18f: 66 0f 74 ea pcmpeqb %xmm2,%xmm5 + 42e193: 66 0f 74 f3 pcmpeqb %xmm3,%xmm6 + 42e197: 66 0f da ea pminub %xmm2,%xmm5 + 42e19b: 66 0f da f3 pminub %xmm3,%xmm6 + 42e19f: 66 0f da c5 pminub %xmm5,%xmm0 + 42e1a3: 66 0f da c6 pminub %xmm6,%xmm0 + 42e1a7: 66 0f 74 c7 pcmpeqb %xmm7,%xmm0 + 42e1ab: 66 0f d7 c8 pmovmskb %xmm0,%ecx + 42e1af: 85 c9 test %ecx,%ecx + 42e1b1: 74 8d je 42e140 <__strcmp_sse2_unaligned+0xf0> + 42e1b3: 66 0f 74 ef pcmpeqb %xmm7,%xmm5 + 42e1b7: f3 0f 6f 02 movdqu (%rdx),%xmm0 + 42e1bb: 66 0f 74 cf pcmpeqb %xmm7,%xmm1 + 42e1bf: 66 0f 6f 10 movdqa (%rax),%xmm2 + 42e1c3: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 42e1c7: 66 0f da c2 pminub %xmm2,%xmm0 + 42e1cb: 66 0f 74 f7 pcmpeqb %xmm7,%xmm6 + 42e1cf: 66 0f 74 c7 pcmpeqb %xmm7,%xmm0 + 42e1d3: 66 0f d7 c9 pmovmskb %xmm1,%ecx + 42e1d7: 66 44 0f d7 c5 pmovmskb %xmm5,%r8d + 42e1dc: 66 0f d7 f8 pmovmskb %xmm0,%edi + 42e1e0: 48 c1 e1 10 shl $0x10,%rcx + 42e1e4: 49 c1 e0 20 shl $0x20,%r8 + 42e1e8: 66 0f d7 f6 pmovmskb %xmm6,%esi + 42e1ec: 4c 09 c1 or %r8,%rcx + 42e1ef: 48 09 f9 or %rdi,%rcx + 42e1f2: 48 c1 e6 30 shl $0x30,%rsi + 42e1f6: 48 09 f1 or %rsi,%rcx + 42e1f9: 48 0f bc c9 bsf %rcx,%rcx + 42e1fd: 0f b6 04 08 movzbl (%rax,%rcx,1),%eax + 42e201: 0f b6 14 0a movzbl (%rdx,%rcx,1),%edx + 42e205: 29 d0 sub %edx,%eax + 42e207: c3 retq + 42e208: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 42e20f: 00 + 42e210: 4d 31 d2 xor %r10,%r10 + 42e213: 49 89 d1 mov %rdx,%r9 + 42e216: 49 83 e1 3f and $0x3f,%r9 + 42e21a: 4d 29 ca sub %r9,%r10 + 42e21d: 66 42 0f 6f 04 12 movdqa (%rdx,%r10,1),%xmm0 + 42e223: 66 42 0f 6f 4c 12 10 movdqa 0x10(%rdx,%r10,1),%xmm1 + 42e22a: f3 42 0f 6f 14 10 movdqu (%rax,%r10,1),%xmm2 + 42e230: f3 42 0f 6f 5c 10 10 movdqu 0x10(%rax,%r10,1),%xmm3 + 42e237: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 42e23b: 66 42 0f 6f 6c 12 20 movdqa 0x20(%rdx,%r10,1),%xmm5 + 42e242: 66 0f 74 cb pcmpeqb %xmm3,%xmm1 + 42e246: 66 0f da c2 pminub %xmm2,%xmm0 + 42e24a: 66 42 0f 6f 74 12 30 movdqa 0x30(%rdx,%r10,1),%xmm6 + 42e251: 66 0f da cb pminub %xmm3,%xmm1 + 42e255: f3 42 0f 6f 54 10 20 movdqu 0x20(%rax,%r10,1),%xmm2 + 42e25c: f3 42 0f 6f 5c 10 30 movdqu 0x30(%rax,%r10,1),%xmm3 + 42e263: 66 0f 74 ea pcmpeqb %xmm2,%xmm5 + 42e267: 66 0f 74 f3 pcmpeqb %xmm3,%xmm6 + 42e26b: 66 0f da ea pminub %xmm2,%xmm5 + 42e26f: 66 0f da f3 pminub %xmm3,%xmm6 + 42e273: 66 0f 74 c7 pcmpeqb %xmm7,%xmm0 + 42e277: 66 0f 74 cf pcmpeqb %xmm7,%xmm1 + 42e27b: 66 0f 74 ef pcmpeqb %xmm7,%xmm5 + 42e27f: 66 0f 74 f7 pcmpeqb %xmm7,%xmm6 + 42e283: 66 0f d7 c9 pmovmskb %xmm1,%ecx + 42e287: 66 44 0f d7 c5 pmovmskb %xmm5,%r8d + 42e28c: 66 0f d7 f8 pmovmskb %xmm0,%edi + 42e290: 48 c1 e1 10 shl $0x10,%rcx + 42e294: 49 c1 e0 20 shl $0x20,%r8 + 42e298: 66 0f d7 f6 pmovmskb %xmm6,%esi + 42e29c: 4c 09 c7 or %r8,%rdi + 42e29f: 48 09 cf or %rcx,%rdi + 42e2a2: 48 c1 e6 30 shl $0x30,%rsi + 42e2a6: 48 09 f7 or %rsi,%rdi + 42e2a9: 4c 89 c9 mov %r9,%rcx + 42e2ac: 48 c7 c6 3f 00 00 00 mov $0x3f,%rsi + 42e2b3: 48 d3 ef shr %cl,%rdi + 42e2b6: 48 85 ff test %rdi,%rdi + 42e2b9: 0f 84 96 fe ff ff je 42e155 <__strcmp_sse2_unaligned+0x105> + 42e2bf: 48 0f bc cf bsf %rdi,%rcx + 42e2c3: 0f b6 04 08 movzbl (%rax,%rcx,1),%eax + 42e2c7: 0f b6 14 0a movzbl (%rdx,%rcx,1),%edx + 42e2cb: 29 d0 sub %edx,%eax + 42e2cd: c3 retq + 42e2ce: 66 90 xchg %ax,%ax + 42e2d0: 38 c8 cmp %cl,%al + 42e2d2: 75 1c jne 42e2f0 <__strcmp_sse2_unaligned+0x2a0> + 42e2d4: 48 83 c2 01 add $0x1,%rdx + 42e2d8: 48 83 fa 40 cmp $0x40,%rdx + 42e2dc: 0f 84 23 fe ff ff je 42e105 <__strcmp_sse2_unaligned+0xb5> + 42e2e2: 0f b6 04 17 movzbl (%rdi,%rdx,1),%eax + 42e2e6: 0f b6 0c 16 movzbl (%rsi,%rdx,1),%ecx + 42e2ea: 84 c0 test %al,%al + 42e2ec: 75 e2 jne 42e2d0 <__strcmp_sse2_unaligned+0x280> + 42e2ee: 31 c0 xor %eax,%eax + 42e2f0: 29 c8 sub %ecx,%eax + 42e2f2: c3 retq + 42e2f3: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42e2fa: 00 00 00 + 42e2fd: 0f 1f 00 nopl (%rax) + +000000000042e300 <__memcmp_sse4_1>: + 42e300: 66 0f ef c0 pxor %xmm0,%xmm0 + 42e304: 48 83 fa 4f cmp $0x4f,%rdx + 42e308: 77 36 ja 42e340 <__memcmp_sse4_1+0x40> + 42e30a: 48 83 fa 01 cmp $0x1,%rdx + 42e30e: 74 20 je 42e330 <__memcmp_sse4_1+0x30> + 42e310: 48 01 d6 add %rdx,%rsi + 42e313: 48 01 d7 add %rdx,%rdi + 42e316: 4c 8d 1d 53 4f 07 00 lea 0x74f53(%rip),%r11 # 4a3270 + 42e31d: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx + 42e321: 4c 01 d9 add %r11,%rcx + 42e324: ff e1 jmpq *%rcx + 42e326: 0f 0b ud2 + 42e328: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 42e32f: 00 + 42e330: 0f b6 07 movzbl (%rdi),%eax + 42e333: 0f b6 0e movzbl (%rsi),%ecx + 42e336: 29 c8 sub %ecx,%eax + 42e338: c3 retq + 42e339: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 42e340: f3 0f 6f 0e movdqu (%rsi),%xmm1 + 42e344: f3 0f 6f 17 movdqu (%rdi),%xmm2 + 42e348: 66 0f ef d1 pxor %xmm1,%xmm2 + 42e34c: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e351: 0f 83 56 0b 00 00 jae 42eead <__memcmp_sse4_1+0xbad> + 42e357: 48 89 f1 mov %rsi,%rcx + 42e35a: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi + 42e35e: 48 83 c6 10 add $0x10,%rsi + 42e362: 48 29 f1 sub %rsi,%rcx + 42e365: 48 29 cf sub %rcx,%rdi + 42e368: 48 01 ca add %rcx,%rdx + 42e36b: 48 f7 c7 0f 00 00 00 test $0xf,%rdi + 42e372: 0f 84 08 05 00 00 je 42e880 <__memcmp_sse4_1+0x580> + 42e378: 48 81 fa 80 00 00 00 cmp $0x80,%rdx + 42e37f: 0f 87 b2 00 00 00 ja 42e437 <__memcmp_sse4_1+0x137> + 42e385: 48 83 ea 40 sub $0x40,%rdx + 42e389: f3 0f 6f 17 movdqu (%rdi),%xmm2 + 42e38d: 66 0f ef 16 pxor (%rsi),%xmm2 + 42e391: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e396: 0f 83 11 0b 00 00 jae 42eead <__memcmp_sse4_1+0xbad> + 42e39c: f3 0f 6f 57 10 movdqu 0x10(%rdi),%xmm2 + 42e3a1: 66 0f ef 56 10 pxor 0x10(%rsi),%xmm2 + 42e3a6: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e3ab: 0f 83 f4 0a 00 00 jae 42eea5 <__memcmp_sse4_1+0xba5> + 42e3b1: f3 0f 6f 57 20 movdqu 0x20(%rdi),%xmm2 + 42e3b6: 66 0f ef 56 20 pxor 0x20(%rsi),%xmm2 + 42e3bb: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e3c0: 0f 83 d7 0a 00 00 jae 42ee9d <__memcmp_sse4_1+0xb9d> + 42e3c6: f3 0f 6f 57 30 movdqu 0x30(%rdi),%xmm2 + 42e3cb: 66 0f ef 56 30 pxor 0x30(%rsi),%xmm2 + 42e3d0: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e3d5: 0f 83 b8 0a 00 00 jae 42ee93 <__memcmp_sse4_1+0xb93> + 42e3db: 48 83 fa 20 cmp $0x20,%rdx + 42e3df: 72 36 jb 42e417 <__memcmp_sse4_1+0x117> + 42e3e1: f3 0f 6f 57 40 movdqu 0x40(%rdi),%xmm2 + 42e3e6: 66 0f ef 56 40 pxor 0x40(%rsi),%xmm2 + 42e3eb: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e3f0: 0f 83 93 0a 00 00 jae 42ee89 <__memcmp_sse4_1+0xb89> + 42e3f6: f3 0f 6f 57 50 movdqu 0x50(%rdi),%xmm2 + 42e3fb: 66 0f ef 56 50 pxor 0x50(%rsi),%xmm2 + 42e400: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e405: 0f 83 74 0a 00 00 jae 42ee7f <__memcmp_sse4_1+0xb7f> + 42e40b: 48 83 ea 20 sub $0x20,%rdx + 42e40f: 48 83 c7 20 add $0x20,%rdi + 42e413: 48 83 c6 20 add $0x20,%rsi + 42e417: 48 83 c7 40 add $0x40,%rdi + 42e41b: 48 83 c6 40 add $0x40,%rsi + 42e41f: 48 01 d6 add %rdx,%rsi + 42e422: 48 01 d7 add %rdx,%rdi + 42e425: 4c 8d 1d 44 4e 07 00 lea 0x74e44(%rip),%r11 # 4a3270 + 42e42c: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx + 42e430: 4c 01 d9 add %r11,%rcx + 42e433: ff e1 jmpq *%rcx + 42e435: 0f 0b ud2 + 42e437: 48 81 fa 00 02 00 00 cmp $0x200,%rdx + 42e43e: 0f 87 2c 03 00 00 ja 42e770 <__memcmp_sse4_1+0x470> + 42e444: 48 81 fa 00 01 00 00 cmp $0x100,%rdx + 42e44b: 0f 87 17 01 00 00 ja 42e568 <__memcmp_sse4_1+0x268> + 42e451: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 42e458: f3 0f 6f 17 movdqu (%rdi),%xmm2 + 42e45c: 66 0f ef 16 pxor (%rsi),%xmm2 + 42e460: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e465: 0f 83 42 0a 00 00 jae 42eead <__memcmp_sse4_1+0xbad> + 42e46b: f3 0f 6f 57 10 movdqu 0x10(%rdi),%xmm2 + 42e470: 66 0f ef 56 10 pxor 0x10(%rsi),%xmm2 + 42e475: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e47a: 0f 83 25 0a 00 00 jae 42eea5 <__memcmp_sse4_1+0xba5> + 42e480: f3 0f 6f 57 20 movdqu 0x20(%rdi),%xmm2 + 42e485: 66 0f ef 56 20 pxor 0x20(%rsi),%xmm2 + 42e48a: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e48f: 0f 83 08 0a 00 00 jae 42ee9d <__memcmp_sse4_1+0xb9d> + 42e495: f3 0f 6f 57 30 movdqu 0x30(%rdi),%xmm2 + 42e49a: 66 0f ef 56 30 pxor 0x30(%rsi),%xmm2 + 42e49f: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e4a4: 0f 83 e9 09 00 00 jae 42ee93 <__memcmp_sse4_1+0xb93> + 42e4aa: f3 0f 6f 57 40 movdqu 0x40(%rdi),%xmm2 + 42e4af: 66 0f ef 56 40 pxor 0x40(%rsi),%xmm2 + 42e4b4: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e4b9: 0f 83 ca 09 00 00 jae 42ee89 <__memcmp_sse4_1+0xb89> + 42e4bf: f3 0f 6f 57 50 movdqu 0x50(%rdi),%xmm2 + 42e4c4: 66 0f ef 56 50 pxor 0x50(%rsi),%xmm2 + 42e4c9: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e4ce: 0f 83 ab 09 00 00 jae 42ee7f <__memcmp_sse4_1+0xb7f> + 42e4d4: f3 0f 6f 57 60 movdqu 0x60(%rdi),%xmm2 + 42e4d9: 66 0f ef 56 60 pxor 0x60(%rsi),%xmm2 + 42e4de: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e4e3: 0f 83 8c 09 00 00 jae 42ee75 <__memcmp_sse4_1+0xb75> + 42e4e9: f3 0f 6f 57 70 movdqu 0x70(%rdi),%xmm2 + 42e4ee: 66 0f ef 56 70 pxor 0x70(%rsi),%xmm2 + 42e4f3: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e4f8: 0f 83 67 09 00 00 jae 42ee65 <__memcmp_sse4_1+0xb65> + 42e4fe: 48 81 c6 80 00 00 00 add $0x80,%rsi + 42e505: 48 81 c7 80 00 00 00 add $0x80,%rdi + 42e50c: 48 83 fa 40 cmp $0x40,%rdx + 42e510: 0f 83 6f fe ff ff jae 42e385 <__memcmp_sse4_1+0x85> + 42e516: 48 83 fa 20 cmp $0x20,%rdx + 42e51a: 72 34 jb 42e550 <__memcmp_sse4_1+0x250> + 42e51c: f3 0f 6f 17 movdqu (%rdi),%xmm2 + 42e520: 66 0f ef 16 pxor (%rsi),%xmm2 + 42e524: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e529: 0f 83 7e 09 00 00 jae 42eead <__memcmp_sse4_1+0xbad> + 42e52f: f3 0f 6f 57 10 movdqu 0x10(%rdi),%xmm2 + 42e534: 66 0f ef 56 10 pxor 0x10(%rsi),%xmm2 + 42e539: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e53e: 0f 83 61 09 00 00 jae 42eea5 <__memcmp_sse4_1+0xba5> + 42e544: 48 83 ea 20 sub $0x20,%rdx + 42e548: 48 83 c7 20 add $0x20,%rdi + 42e54c: 48 83 c6 20 add $0x20,%rsi + 42e550: 48 01 d6 add %rdx,%rsi + 42e553: 48 01 d7 add %rdx,%rdi + 42e556: 4c 8d 1d 13 4d 07 00 lea 0x74d13(%rip),%r11 # 4a3270 + 42e55d: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx + 42e561: 4c 01 d9 add %r11,%rcx + 42e564: ff e1 jmpq *%rcx + 42e566: 0f 0b ud2 + 42e568: 48 81 ea 00 01 00 00 sub $0x100,%rdx + 42e56f: f3 0f 6f 17 movdqu (%rdi),%xmm2 + 42e573: 66 0f ef 16 pxor (%rsi),%xmm2 + 42e577: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e57c: 0f 83 2b 09 00 00 jae 42eead <__memcmp_sse4_1+0xbad> + 42e582: f3 0f 6f 57 10 movdqu 0x10(%rdi),%xmm2 + 42e587: 66 0f ef 56 10 pxor 0x10(%rsi),%xmm2 + 42e58c: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e591: 0f 83 0e 09 00 00 jae 42eea5 <__memcmp_sse4_1+0xba5> + 42e597: f3 0f 6f 57 20 movdqu 0x20(%rdi),%xmm2 + 42e59c: 66 0f ef 56 20 pxor 0x20(%rsi),%xmm2 + 42e5a1: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e5a6: 0f 83 f1 08 00 00 jae 42ee9d <__memcmp_sse4_1+0xb9d> + 42e5ac: f3 0f 6f 57 30 movdqu 0x30(%rdi),%xmm2 + 42e5b1: 66 0f ef 56 30 pxor 0x30(%rsi),%xmm2 + 42e5b6: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e5bb: 0f 83 d2 08 00 00 jae 42ee93 <__memcmp_sse4_1+0xb93> + 42e5c1: f3 0f 6f 57 40 movdqu 0x40(%rdi),%xmm2 + 42e5c6: 66 0f ef 56 40 pxor 0x40(%rsi),%xmm2 + 42e5cb: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e5d0: 0f 83 b3 08 00 00 jae 42ee89 <__memcmp_sse4_1+0xb89> + 42e5d6: f3 0f 6f 57 50 movdqu 0x50(%rdi),%xmm2 + 42e5db: 66 0f ef 56 50 pxor 0x50(%rsi),%xmm2 + 42e5e0: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e5e5: 0f 83 94 08 00 00 jae 42ee7f <__memcmp_sse4_1+0xb7f> + 42e5eb: f3 0f 6f 57 60 movdqu 0x60(%rdi),%xmm2 + 42e5f0: 66 0f ef 56 60 pxor 0x60(%rsi),%xmm2 + 42e5f5: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e5fa: 0f 83 75 08 00 00 jae 42ee75 <__memcmp_sse4_1+0xb75> + 42e600: f3 0f 6f 57 70 movdqu 0x70(%rdi),%xmm2 + 42e605: 66 0f ef 56 70 pxor 0x70(%rsi),%xmm2 + 42e60a: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e60f: 0f 83 50 08 00 00 jae 42ee65 <__memcmp_sse4_1+0xb65> + 42e615: f3 0f 6f 97 80 00 00 movdqu 0x80(%rdi),%xmm2 + 42e61c: 00 + 42e61d: 66 0f ef 96 80 00 00 pxor 0x80(%rsi),%xmm2 + 42e624: 00 + 42e625: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e62a: 0f 83 25 08 00 00 jae 42ee55 <__memcmp_sse4_1+0xb55> + 42e630: f3 0f 6f 97 90 00 00 movdqu 0x90(%rdi),%xmm2 + 42e637: 00 + 42e638: 66 0f ef 96 90 00 00 pxor 0x90(%rsi),%xmm2 + 42e63f: 00 + 42e640: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e645: 0f 83 fa 07 00 00 jae 42ee45 <__memcmp_sse4_1+0xb45> + 42e64b: f3 0f 6f 97 a0 00 00 movdqu 0xa0(%rdi),%xmm2 + 42e652: 00 + 42e653: 66 0f ef 96 a0 00 00 pxor 0xa0(%rsi),%xmm2 + 42e65a: 00 + 42e65b: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e660: 0f 83 cf 07 00 00 jae 42ee35 <__memcmp_sse4_1+0xb35> + 42e666: f3 0f 6f 97 b0 00 00 movdqu 0xb0(%rdi),%xmm2 + 42e66d: 00 + 42e66e: 66 0f ef 96 b0 00 00 pxor 0xb0(%rsi),%xmm2 + 42e675: 00 + 42e676: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e67b: 0f 83 a1 07 00 00 jae 42ee22 <__memcmp_sse4_1+0xb22> + 42e681: f3 0f 6f 97 c0 00 00 movdqu 0xc0(%rdi),%xmm2 + 42e688: 00 + 42e689: 66 0f ef 96 c0 00 00 pxor 0xc0(%rsi),%xmm2 + 42e690: 00 + 42e691: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e696: 0f 83 73 07 00 00 jae 42ee0f <__memcmp_sse4_1+0xb0f> + 42e69c: f3 0f 6f 97 d0 00 00 movdqu 0xd0(%rdi),%xmm2 + 42e6a3: 00 + 42e6a4: 66 0f ef 96 d0 00 00 pxor 0xd0(%rsi),%xmm2 + 42e6ab: 00 + 42e6ac: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e6b1: 0f 83 45 07 00 00 jae 42edfc <__memcmp_sse4_1+0xafc> + 42e6b7: f3 0f 6f 97 e0 00 00 movdqu 0xe0(%rdi),%xmm2 + 42e6be: 00 + 42e6bf: 66 0f ef 96 e0 00 00 pxor 0xe0(%rsi),%xmm2 + 42e6c6: 00 + 42e6c7: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e6cc: 0f 83 17 07 00 00 jae 42ede9 <__memcmp_sse4_1+0xae9> + 42e6d2: f3 0f 6f 97 f0 00 00 movdqu 0xf0(%rdi),%xmm2 + 42e6d9: 00 + 42e6da: 66 0f ef 96 f0 00 00 pxor 0xf0(%rsi),%xmm2 + 42e6e1: 00 + 42e6e2: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e6e7: 0f 83 e9 06 00 00 jae 42edd6 <__memcmp_sse4_1+0xad6> + 42e6ed: 48 81 c6 00 01 00 00 add $0x100,%rsi + 42e6f4: 48 81 c7 00 01 00 00 add $0x100,%rdi + 42e6fb: 48 81 fa 80 00 00 00 cmp $0x80,%rdx + 42e702: 0f 83 49 fd ff ff jae 42e451 <__memcmp_sse4_1+0x151> + 42e708: 48 83 fa 40 cmp $0x40,%rdx + 42e70c: 0f 83 73 fc ff ff jae 42e385 <__memcmp_sse4_1+0x85> + 42e712: 48 83 fa 20 cmp $0x20,%rdx + 42e716: 72 34 jb 42e74c <__memcmp_sse4_1+0x44c> + 42e718: f3 0f 6f 17 movdqu (%rdi),%xmm2 + 42e71c: 66 0f ef 16 pxor (%rsi),%xmm2 + 42e720: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e725: 0f 83 82 07 00 00 jae 42eead <__memcmp_sse4_1+0xbad> + 42e72b: f3 0f 6f 57 10 movdqu 0x10(%rdi),%xmm2 + 42e730: 66 0f ef 56 10 pxor 0x10(%rsi),%xmm2 + 42e735: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e73a: 0f 83 65 07 00 00 jae 42eea5 <__memcmp_sse4_1+0xba5> + 42e740: 48 83 ea 20 sub $0x20,%rdx + 42e744: 48 83 c7 20 add $0x20,%rdi + 42e748: 48 83 c6 20 add $0x20,%rsi + 42e74c: 48 01 d6 add %rdx,%rsi + 42e74f: 48 01 d7 add %rdx,%rdi + 42e752: 4c 8d 1d 17 4b 07 00 lea 0x74b17(%rip),%r11 # 4a3270 + 42e759: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx + 42e75d: 4c 01 d9 add %r11,%rcx + 42e760: ff e1 jmpq *%rcx + 42e762: 0f 0b ud2 + 42e764: 66 90 xchg %ax,%ax + 42e766: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42e76d: 00 00 00 + 42e770: 4c 8b 05 59 c9 29 00 mov 0x29c959(%rip),%r8 # 6cb0d0 <__x86_data_cache_size_half> + 42e777: 4d 89 c1 mov %r8,%r9 + 42e77a: 49 d1 e8 shr %r8 + 42e77d: 4d 01 c8 add %r9,%r8 + 42e780: 4c 39 c2 cmp %r8,%rdx + 42e783: 77 76 ja 42e7fb <__memcmp_sse4_1+0x4fb> + 42e785: 48 83 ea 40 sub $0x40,%rdx + 42e789: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 42e790: f3 0f 6f 17 movdqu (%rdi),%xmm2 + 42e794: 66 0f ef 16 pxor (%rsi),%xmm2 + 42e798: 66 0f 6f ca movdqa %xmm2,%xmm1 + 42e79c: f3 0f 6f 5f 10 movdqu 0x10(%rdi),%xmm3 + 42e7a1: 66 0f ef 5e 10 pxor 0x10(%rsi),%xmm3 + 42e7a6: 66 0f eb cb por %xmm3,%xmm1 + 42e7aa: f3 0f 6f 67 20 movdqu 0x20(%rdi),%xmm4 + 42e7af: 66 0f ef 66 20 pxor 0x20(%rsi),%xmm4 + 42e7b4: 66 0f eb cc por %xmm4,%xmm1 + 42e7b8: f3 0f 6f 6f 30 movdqu 0x30(%rdi),%xmm5 + 42e7bd: 66 0f ef 6e 30 pxor 0x30(%rsi),%xmm5 + 42e7c2: 66 0f eb cd por %xmm5,%xmm1 + 42e7c6: 66 0f 38 17 c1 ptest %xmm1,%xmm0 + 42e7cb: 0f 83 bf 05 00 00 jae 42ed90 <__memcmp_sse4_1+0xa90> + 42e7d1: 48 83 c6 40 add $0x40,%rsi + 42e7d5: 48 83 c7 40 add $0x40,%rdi + 42e7d9: 48 83 ea 40 sub $0x40,%rdx + 42e7dd: 73 b1 jae 42e790 <__memcmp_sse4_1+0x490> + 42e7df: 48 83 c2 40 add $0x40,%rdx + 42e7e3: 48 01 d6 add %rdx,%rsi + 42e7e6: 48 01 d7 add %rdx,%rdi + 42e7e9: 4c 8d 1d 80 4a 07 00 lea 0x74a80(%rip),%r11 # 4a3270 + 42e7f0: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx + 42e7f4: 4c 01 d9 add %r11,%rcx + 42e7f7: ff e1 jmpq *%rcx + 42e7f9: 0f 0b ud2 + 42e7fb: 48 83 ea 40 sub $0x40,%rdx + 42e7ff: 90 nop + 42e800: 0f 18 87 c0 01 00 00 prefetchnta 0x1c0(%rdi) + 42e807: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) + 42e80e: f3 0f 6f 17 movdqu (%rdi),%xmm2 + 42e812: 66 0f ef 16 pxor (%rsi),%xmm2 + 42e816: 66 0f 6f ca movdqa %xmm2,%xmm1 + 42e81a: f3 0f 6f 5f 10 movdqu 0x10(%rdi),%xmm3 + 42e81f: 66 0f ef 5e 10 pxor 0x10(%rsi),%xmm3 + 42e824: 66 0f eb cb por %xmm3,%xmm1 + 42e828: f3 0f 6f 67 20 movdqu 0x20(%rdi),%xmm4 + 42e82d: 66 0f ef 66 20 pxor 0x20(%rsi),%xmm4 + 42e832: 66 0f eb cc por %xmm4,%xmm1 + 42e836: f3 0f 6f 6f 30 movdqu 0x30(%rdi),%xmm5 + 42e83b: 66 0f ef 6e 30 pxor 0x30(%rsi),%xmm5 + 42e840: 66 0f eb cd por %xmm5,%xmm1 + 42e844: 66 0f 38 17 c1 ptest %xmm1,%xmm0 + 42e849: 0f 83 41 05 00 00 jae 42ed90 <__memcmp_sse4_1+0xa90> + 42e84f: 48 83 c6 40 add $0x40,%rsi + 42e853: 48 83 c7 40 add $0x40,%rdi + 42e857: 48 83 ea 40 sub $0x40,%rdx + 42e85b: 73 a3 jae 42e800 <__memcmp_sse4_1+0x500> + 42e85d: 48 83 c2 40 add $0x40,%rdx + 42e861: 48 01 d6 add %rdx,%rsi + 42e864: 48 01 d7 add %rdx,%rdi + 42e867: 4c 8d 1d 02 4a 07 00 lea 0x74a02(%rip),%r11 # 4a3270 + 42e86e: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx + 42e872: 4c 01 d9 add %r11,%rcx + 42e875: ff e1 jmpq *%rcx + 42e877: 0f 0b ud2 + 42e879: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 42e880: 48 81 fa 80 00 00 00 cmp $0x80,%rdx + 42e887: 0f 87 b3 00 00 00 ja 42e940 <__memcmp_sse4_1+0x640> + 42e88d: 48 83 ea 40 sub $0x40,%rdx + 42e891: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 42e895: 66 0f ef 16 pxor (%rsi),%xmm2 + 42e899: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e89e: 0f 83 09 06 00 00 jae 42eead <__memcmp_sse4_1+0xbad> + 42e8a4: 66 0f 6f 57 10 movdqa 0x10(%rdi),%xmm2 + 42e8a9: 66 0f ef 56 10 pxor 0x10(%rsi),%xmm2 + 42e8ae: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e8b3: 0f 83 ec 05 00 00 jae 42eea5 <__memcmp_sse4_1+0xba5> + 42e8b9: 66 0f 6f 57 20 movdqa 0x20(%rdi),%xmm2 + 42e8be: 66 0f ef 56 20 pxor 0x20(%rsi),%xmm2 + 42e8c3: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e8c8: 0f 83 cf 05 00 00 jae 42ee9d <__memcmp_sse4_1+0xb9d> + 42e8ce: 66 0f 6f 57 30 movdqa 0x30(%rdi),%xmm2 + 42e8d3: 66 0f ef 56 30 pxor 0x30(%rsi),%xmm2 + 42e8d8: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e8dd: 0f 83 b0 05 00 00 jae 42ee93 <__memcmp_sse4_1+0xb93> + 42e8e3: 48 83 fa 20 cmp $0x20,%rdx + 42e8e7: 72 36 jb 42e91f <__memcmp_sse4_1+0x61f> + 42e8e9: 66 0f 6f 57 40 movdqa 0x40(%rdi),%xmm2 + 42e8ee: 66 0f ef 56 40 pxor 0x40(%rsi),%xmm2 + 42e8f3: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e8f8: 0f 83 8b 05 00 00 jae 42ee89 <__memcmp_sse4_1+0xb89> + 42e8fe: 66 0f 6f 57 50 movdqa 0x50(%rdi),%xmm2 + 42e903: 66 0f ef 56 50 pxor 0x50(%rsi),%xmm2 + 42e908: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e90d: 0f 83 6c 05 00 00 jae 42ee7f <__memcmp_sse4_1+0xb7f> + 42e913: 48 83 ea 20 sub $0x20,%rdx + 42e917: 48 83 c7 20 add $0x20,%rdi + 42e91b: 48 83 c6 20 add $0x20,%rsi + 42e91f: 48 83 c7 40 add $0x40,%rdi + 42e923: 48 83 c6 40 add $0x40,%rsi + 42e927: 48 01 d6 add %rdx,%rsi + 42e92a: 48 01 d7 add %rdx,%rdi + 42e92d: 4c 8d 1d 3c 49 07 00 lea 0x7493c(%rip),%r11 # 4a3270 + 42e934: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx + 42e938: 4c 01 d9 add %r11,%rcx + 42e93b: ff e1 jmpq *%rcx + 42e93d: 0f 0b ud2 + 42e93f: 90 nop + 42e940: 48 81 fa 00 02 00 00 cmp $0x200,%rdx + 42e947: 0f 87 33 03 00 00 ja 42ec80 <__memcmp_sse4_1+0x980> + 42e94d: 48 81 fa 00 01 00 00 cmp $0x100,%rdx + 42e954: 0f 87 26 01 00 00 ja 42ea80 <__memcmp_sse4_1+0x780> + 42e95a: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 42e961: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 42e965: 66 0f ef 16 pxor (%rsi),%xmm2 + 42e969: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e96e: 0f 83 39 05 00 00 jae 42eead <__memcmp_sse4_1+0xbad> + 42e974: 66 0f 6f 57 10 movdqa 0x10(%rdi),%xmm2 + 42e979: 66 0f ef 56 10 pxor 0x10(%rsi),%xmm2 + 42e97e: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e983: 0f 83 1c 05 00 00 jae 42eea5 <__memcmp_sse4_1+0xba5> + 42e989: 66 0f 6f 57 20 movdqa 0x20(%rdi),%xmm2 + 42e98e: 66 0f ef 56 20 pxor 0x20(%rsi),%xmm2 + 42e993: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e998: 0f 83 ff 04 00 00 jae 42ee9d <__memcmp_sse4_1+0xb9d> + 42e99e: 66 0f 6f 57 30 movdqa 0x30(%rdi),%xmm2 + 42e9a3: 66 0f ef 56 30 pxor 0x30(%rsi),%xmm2 + 42e9a8: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e9ad: 0f 83 e0 04 00 00 jae 42ee93 <__memcmp_sse4_1+0xb93> + 42e9b3: 66 0f 6f 57 40 movdqa 0x40(%rdi),%xmm2 + 42e9b8: 66 0f ef 56 40 pxor 0x40(%rsi),%xmm2 + 42e9bd: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e9c2: 0f 83 c1 04 00 00 jae 42ee89 <__memcmp_sse4_1+0xb89> + 42e9c8: 66 0f 6f 57 50 movdqa 0x50(%rdi),%xmm2 + 42e9cd: 66 0f ef 56 50 pxor 0x50(%rsi),%xmm2 + 42e9d2: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e9d7: 0f 83 a2 04 00 00 jae 42ee7f <__memcmp_sse4_1+0xb7f> + 42e9dd: 66 0f 6f 57 60 movdqa 0x60(%rdi),%xmm2 + 42e9e2: 66 0f ef 56 60 pxor 0x60(%rsi),%xmm2 + 42e9e7: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42e9ec: 0f 83 83 04 00 00 jae 42ee75 <__memcmp_sse4_1+0xb75> + 42e9f2: 66 0f 6f 57 70 movdqa 0x70(%rdi),%xmm2 + 42e9f7: 66 0f ef 56 70 pxor 0x70(%rsi),%xmm2 + 42e9fc: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42ea01: 0f 83 5e 04 00 00 jae 42ee65 <__memcmp_sse4_1+0xb65> + 42ea07: 48 81 c6 80 00 00 00 add $0x80,%rsi + 42ea0e: 48 81 c7 80 00 00 00 add $0x80,%rdi + 42ea15: 48 83 fa 40 cmp $0x40,%rdx + 42ea19: 0f 83 6e fe ff ff jae 42e88d <__memcmp_sse4_1+0x58d> + 42ea1f: 48 83 fa 20 cmp $0x20,%rdx + 42ea23: 72 34 jb 42ea59 <__memcmp_sse4_1+0x759> + 42ea25: f3 0f 6f 17 movdqu (%rdi),%xmm2 + 42ea29: 66 0f ef 16 pxor (%rsi),%xmm2 + 42ea2d: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42ea32: 0f 83 75 04 00 00 jae 42eead <__memcmp_sse4_1+0xbad> + 42ea38: f3 0f 6f 57 10 movdqu 0x10(%rdi),%xmm2 + 42ea3d: 66 0f ef 56 10 pxor 0x10(%rsi),%xmm2 + 42ea42: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42ea47: 0f 83 58 04 00 00 jae 42eea5 <__memcmp_sse4_1+0xba5> + 42ea4d: 48 83 ea 20 sub $0x20,%rdx + 42ea51: 48 83 c7 20 add $0x20,%rdi + 42ea55: 48 83 c6 20 add $0x20,%rsi + 42ea59: 48 01 d6 add %rdx,%rsi + 42ea5c: 48 01 d7 add %rdx,%rdi + 42ea5f: 4c 8d 1d 0a 48 07 00 lea 0x7480a(%rip),%r11 # 4a3270 + 42ea66: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx + 42ea6a: 4c 01 d9 add %r11,%rcx + 42ea6d: ff e1 jmpq *%rcx + 42ea6f: 0f 0b ud2 + 42ea71: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 42ea76: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42ea7d: 00 00 00 + 42ea80: 48 81 ea 00 01 00 00 sub $0x100,%rdx + 42ea87: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 42ea8b: 66 0f ef 16 pxor (%rsi),%xmm2 + 42ea8f: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42ea94: 0f 83 13 04 00 00 jae 42eead <__memcmp_sse4_1+0xbad> + 42ea9a: 66 0f 6f 57 10 movdqa 0x10(%rdi),%xmm2 + 42ea9f: 66 0f ef 56 10 pxor 0x10(%rsi),%xmm2 + 42eaa4: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42eaa9: 0f 83 f6 03 00 00 jae 42eea5 <__memcmp_sse4_1+0xba5> + 42eaaf: 66 0f 6f 57 20 movdqa 0x20(%rdi),%xmm2 + 42eab4: 66 0f ef 56 20 pxor 0x20(%rsi),%xmm2 + 42eab9: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42eabe: 0f 83 d9 03 00 00 jae 42ee9d <__memcmp_sse4_1+0xb9d> + 42eac4: 66 0f 6f 57 30 movdqa 0x30(%rdi),%xmm2 + 42eac9: 66 0f ef 56 30 pxor 0x30(%rsi),%xmm2 + 42eace: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42ead3: 0f 83 ba 03 00 00 jae 42ee93 <__memcmp_sse4_1+0xb93> + 42ead9: 66 0f 6f 57 40 movdqa 0x40(%rdi),%xmm2 + 42eade: 66 0f ef 56 40 pxor 0x40(%rsi),%xmm2 + 42eae3: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42eae8: 0f 83 9b 03 00 00 jae 42ee89 <__memcmp_sse4_1+0xb89> + 42eaee: 66 0f 6f 57 50 movdqa 0x50(%rdi),%xmm2 + 42eaf3: 66 0f ef 56 50 pxor 0x50(%rsi),%xmm2 + 42eaf8: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42eafd: 0f 83 7c 03 00 00 jae 42ee7f <__memcmp_sse4_1+0xb7f> + 42eb03: 66 0f 6f 57 60 movdqa 0x60(%rdi),%xmm2 + 42eb08: 66 0f ef 56 60 pxor 0x60(%rsi),%xmm2 + 42eb0d: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42eb12: 0f 83 5d 03 00 00 jae 42ee75 <__memcmp_sse4_1+0xb75> + 42eb18: 66 0f 6f 57 70 movdqa 0x70(%rdi),%xmm2 + 42eb1d: 66 0f ef 56 70 pxor 0x70(%rsi),%xmm2 + 42eb22: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42eb27: 0f 83 38 03 00 00 jae 42ee65 <__memcmp_sse4_1+0xb65> + 42eb2d: 66 0f 6f 97 80 00 00 movdqa 0x80(%rdi),%xmm2 + 42eb34: 00 + 42eb35: 66 0f ef 96 80 00 00 pxor 0x80(%rsi),%xmm2 + 42eb3c: 00 + 42eb3d: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42eb42: 0f 83 0d 03 00 00 jae 42ee55 <__memcmp_sse4_1+0xb55> + 42eb48: 66 0f 6f 97 90 00 00 movdqa 0x90(%rdi),%xmm2 + 42eb4f: 00 + 42eb50: 66 0f ef 96 90 00 00 pxor 0x90(%rsi),%xmm2 + 42eb57: 00 + 42eb58: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42eb5d: 0f 83 e2 02 00 00 jae 42ee45 <__memcmp_sse4_1+0xb45> + 42eb63: 66 0f 6f 97 a0 00 00 movdqa 0xa0(%rdi),%xmm2 + 42eb6a: 00 + 42eb6b: 66 0f ef 96 a0 00 00 pxor 0xa0(%rsi),%xmm2 + 42eb72: 00 + 42eb73: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42eb78: 0f 83 b7 02 00 00 jae 42ee35 <__memcmp_sse4_1+0xb35> + 42eb7e: 66 0f 6f 97 b0 00 00 movdqa 0xb0(%rdi),%xmm2 + 42eb85: 00 + 42eb86: 66 0f ef 96 b0 00 00 pxor 0xb0(%rsi),%xmm2 + 42eb8d: 00 + 42eb8e: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42eb93: 0f 83 89 02 00 00 jae 42ee22 <__memcmp_sse4_1+0xb22> + 42eb99: 66 0f 6f 97 c0 00 00 movdqa 0xc0(%rdi),%xmm2 + 42eba0: 00 + 42eba1: 66 0f ef 96 c0 00 00 pxor 0xc0(%rsi),%xmm2 + 42eba8: 00 + 42eba9: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42ebae: 0f 83 5b 02 00 00 jae 42ee0f <__memcmp_sse4_1+0xb0f> + 42ebb4: 66 0f 6f 97 d0 00 00 movdqa 0xd0(%rdi),%xmm2 + 42ebbb: 00 + 42ebbc: 66 0f ef 96 d0 00 00 pxor 0xd0(%rsi),%xmm2 + 42ebc3: 00 + 42ebc4: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42ebc9: 0f 83 2d 02 00 00 jae 42edfc <__memcmp_sse4_1+0xafc> + 42ebcf: 66 0f 6f 97 e0 00 00 movdqa 0xe0(%rdi),%xmm2 + 42ebd6: 00 + 42ebd7: 66 0f ef 96 e0 00 00 pxor 0xe0(%rsi),%xmm2 + 42ebde: 00 + 42ebdf: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42ebe4: 0f 83 ff 01 00 00 jae 42ede9 <__memcmp_sse4_1+0xae9> + 42ebea: 66 0f 6f 97 f0 00 00 movdqa 0xf0(%rdi),%xmm2 + 42ebf1: 00 + 42ebf2: 66 0f ef 96 f0 00 00 pxor 0xf0(%rsi),%xmm2 + 42ebf9: 00 + 42ebfa: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42ebff: 0f 83 d1 01 00 00 jae 42edd6 <__memcmp_sse4_1+0xad6> + 42ec05: 48 81 c6 00 01 00 00 add $0x100,%rsi + 42ec0c: 48 81 c7 00 01 00 00 add $0x100,%rdi + 42ec13: 48 81 fa 80 00 00 00 cmp $0x80,%rdx + 42ec1a: 0f 83 3a fd ff ff jae 42e95a <__memcmp_sse4_1+0x65a> + 42ec20: 48 83 fa 40 cmp $0x40,%rdx + 42ec24: 0f 83 63 fc ff ff jae 42e88d <__memcmp_sse4_1+0x58d> + 42ec2a: 48 83 fa 20 cmp $0x20,%rdx + 42ec2e: 72 34 jb 42ec64 <__memcmp_sse4_1+0x964> + 42ec30: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 42ec34: 66 0f ef 16 pxor (%rsi),%xmm2 + 42ec38: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42ec3d: 0f 83 6a 02 00 00 jae 42eead <__memcmp_sse4_1+0xbad> + 42ec43: 66 0f 6f 57 10 movdqa 0x10(%rdi),%xmm2 + 42ec48: 66 0f ef 56 10 pxor 0x10(%rsi),%xmm2 + 42ec4d: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42ec52: 0f 83 4d 02 00 00 jae 42eea5 <__memcmp_sse4_1+0xba5> + 42ec58: 48 83 ea 20 sub $0x20,%rdx + 42ec5c: 48 83 c7 20 add $0x20,%rdi + 42ec60: 48 83 c6 20 add $0x20,%rsi + 42ec64: 48 01 d6 add %rdx,%rsi + 42ec67: 48 01 d7 add %rdx,%rdi + 42ec6a: 4c 8d 1d ff 45 07 00 lea 0x745ff(%rip),%r11 # 4a3270 + 42ec71: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx + 42ec75: 4c 01 d9 add %r11,%rcx + 42ec78: ff e1 jmpq *%rcx + 42ec7a: 0f 0b ud2 + 42ec7c: 0f 1f 40 00 nopl 0x0(%rax) + 42ec80: 4c 8b 05 49 c4 29 00 mov 0x29c449(%rip),%r8 # 6cb0d0 <__x86_data_cache_size_half> + 42ec87: 4d 89 c1 mov %r8,%r9 + 42ec8a: 49 d1 e8 shr %r8 + 42ec8d: 4d 01 c8 add %r9,%r8 + 42ec90: 4c 39 c2 cmp %r8,%rdx + 42ec93: 77 76 ja 42ed0b <__memcmp_sse4_1+0xa0b> + 42ec95: 48 83 ea 40 sub $0x40,%rdx + 42ec99: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 42eca0: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 42eca4: 66 0f ef 16 pxor (%rsi),%xmm2 + 42eca8: 66 0f 6f ca movdqa %xmm2,%xmm1 + 42ecac: 66 0f 6f 5f 10 movdqa 0x10(%rdi),%xmm3 + 42ecb1: 66 0f ef 5e 10 pxor 0x10(%rsi),%xmm3 + 42ecb6: 66 0f eb cb por %xmm3,%xmm1 + 42ecba: 66 0f 6f 67 20 movdqa 0x20(%rdi),%xmm4 + 42ecbf: 66 0f ef 66 20 pxor 0x20(%rsi),%xmm4 + 42ecc4: 66 0f eb cc por %xmm4,%xmm1 + 42ecc8: 66 0f 6f 6f 30 movdqa 0x30(%rdi),%xmm5 + 42eccd: 66 0f ef 6e 30 pxor 0x30(%rsi),%xmm5 + 42ecd2: 66 0f eb cd por %xmm5,%xmm1 + 42ecd6: 66 0f 38 17 c1 ptest %xmm1,%xmm0 + 42ecdb: 0f 83 af 00 00 00 jae 42ed90 <__memcmp_sse4_1+0xa90> + 42ece1: 48 83 c6 40 add $0x40,%rsi + 42ece5: 48 83 c7 40 add $0x40,%rdi + 42ece9: 48 83 ea 40 sub $0x40,%rdx + 42eced: 73 b1 jae 42eca0 <__memcmp_sse4_1+0x9a0> + 42ecef: 48 83 c2 40 add $0x40,%rdx + 42ecf3: 48 01 d6 add %rdx,%rsi + 42ecf6: 48 01 d7 add %rdx,%rdi + 42ecf9: 4c 8d 1d 70 45 07 00 lea 0x74570(%rip),%r11 # 4a3270 + 42ed00: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx + 42ed04: 4c 01 d9 add %r11,%rcx + 42ed07: ff e1 jmpq *%rcx + 42ed09: 0f 0b ud2 + 42ed0b: 48 83 ea 40 sub $0x40,%rdx + 42ed0f: 90 nop + 42ed10: 0f 18 87 c0 01 00 00 prefetchnta 0x1c0(%rdi) + 42ed17: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) + 42ed1e: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 42ed22: 66 0f ef 16 pxor (%rsi),%xmm2 + 42ed26: 66 0f 6f ca movdqa %xmm2,%xmm1 + 42ed2a: 66 0f 6f 5f 10 movdqa 0x10(%rdi),%xmm3 + 42ed2f: 66 0f ef 5e 10 pxor 0x10(%rsi),%xmm3 + 42ed34: 66 0f eb cb por %xmm3,%xmm1 + 42ed38: 66 0f 6f 67 20 movdqa 0x20(%rdi),%xmm4 + 42ed3d: 66 0f ef 66 20 pxor 0x20(%rsi),%xmm4 + 42ed42: 66 0f eb cc por %xmm4,%xmm1 + 42ed46: 66 0f 6f 6f 30 movdqa 0x30(%rdi),%xmm5 + 42ed4b: 66 0f ef 6e 30 pxor 0x30(%rsi),%xmm5 + 42ed50: 66 0f eb cd por %xmm5,%xmm1 + 42ed54: 66 0f 38 17 c1 ptest %xmm1,%xmm0 + 42ed59: 73 35 jae 42ed90 <__memcmp_sse4_1+0xa90> + 42ed5b: 48 83 c6 40 add $0x40,%rsi + 42ed5f: 48 83 c7 40 add $0x40,%rdi + 42ed63: 48 83 ea 40 sub $0x40,%rdx + 42ed67: 73 a7 jae 42ed10 <__memcmp_sse4_1+0xa10> + 42ed69: 48 83 c2 40 add $0x40,%rdx + 42ed6d: 48 01 d6 add %rdx,%rsi + 42ed70: 48 01 d7 add %rdx,%rdi + 42ed73: 4c 8d 1d f6 44 07 00 lea 0x744f6(%rip),%r11 # 4a3270 + 42ed7a: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx + 42ed7e: 4c 01 d9 add %r11,%rcx + 42ed81: ff e1 jmpq *%rcx + 42ed83: 0f 0b ud2 + 42ed85: 90 nop + 42ed86: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42ed8d: 00 00 00 + 42ed90: 48 83 c7 10 add $0x10,%rdi + 42ed94: 48 83 c6 10 add $0x10,%rsi + 42ed98: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42ed9d: 0f 83 12 01 00 00 jae 42eeb5 <__memcmp_sse4_1+0xbb5> + 42eda3: 48 83 c7 10 add $0x10,%rdi + 42eda7: 48 83 c6 10 add $0x10,%rsi + 42edab: 66 0f 38 17 c3 ptest %xmm3,%xmm0 + 42edb0: 0f 83 ff 00 00 00 jae 42eeb5 <__memcmp_sse4_1+0xbb5> + 42edb6: 48 83 c7 10 add $0x10,%rdi + 42edba: 48 83 c6 10 add $0x10,%rsi + 42edbe: 66 0f 38 17 c4 ptest %xmm4,%xmm0 + 42edc3: 0f 83 ec 00 00 00 jae 42eeb5 <__memcmp_sse4_1+0xbb5> + 42edc9: 48 83 c7 10 add $0x10,%rdi + 42edcd: 48 83 c6 10 add $0x10,%rsi + 42edd1: e9 df 00 00 00 jmpq 42eeb5 <__memcmp_sse4_1+0xbb5> + 42edd6: 48 81 c7 00 01 00 00 add $0x100,%rdi + 42eddd: 48 81 c6 00 01 00 00 add $0x100,%rsi + 42ede4: e9 cc 00 00 00 jmpq 42eeb5 <__memcmp_sse4_1+0xbb5> + 42ede9: 48 81 c7 f0 00 00 00 add $0xf0,%rdi + 42edf0: 48 81 c6 f0 00 00 00 add $0xf0,%rsi + 42edf7: e9 b9 00 00 00 jmpq 42eeb5 <__memcmp_sse4_1+0xbb5> + 42edfc: 48 81 c7 e0 00 00 00 add $0xe0,%rdi + 42ee03: 48 81 c6 e0 00 00 00 add $0xe0,%rsi + 42ee0a: e9 a6 00 00 00 jmpq 42eeb5 <__memcmp_sse4_1+0xbb5> + 42ee0f: 48 81 c7 d0 00 00 00 add $0xd0,%rdi + 42ee16: 48 81 c6 d0 00 00 00 add $0xd0,%rsi + 42ee1d: e9 93 00 00 00 jmpq 42eeb5 <__memcmp_sse4_1+0xbb5> + 42ee22: 48 81 c7 c0 00 00 00 add $0xc0,%rdi + 42ee29: 48 81 c6 c0 00 00 00 add $0xc0,%rsi + 42ee30: e9 80 00 00 00 jmpq 42eeb5 <__memcmp_sse4_1+0xbb5> + 42ee35: 48 81 c7 b0 00 00 00 add $0xb0,%rdi + 42ee3c: 48 81 c6 b0 00 00 00 add $0xb0,%rsi + 42ee43: eb 70 jmp 42eeb5 <__memcmp_sse4_1+0xbb5> + 42ee45: 48 81 c7 a0 00 00 00 add $0xa0,%rdi + 42ee4c: 48 81 c6 a0 00 00 00 add $0xa0,%rsi + 42ee53: eb 60 jmp 42eeb5 <__memcmp_sse4_1+0xbb5> + 42ee55: 48 81 c7 90 00 00 00 add $0x90,%rdi + 42ee5c: 48 81 c6 90 00 00 00 add $0x90,%rsi + 42ee63: eb 50 jmp 42eeb5 <__memcmp_sse4_1+0xbb5> + 42ee65: 48 81 c7 80 00 00 00 add $0x80,%rdi + 42ee6c: 48 81 c6 80 00 00 00 add $0x80,%rsi + 42ee73: eb 40 jmp 42eeb5 <__memcmp_sse4_1+0xbb5> + 42ee75: 48 83 c7 70 add $0x70,%rdi + 42ee79: 48 83 c6 70 add $0x70,%rsi + 42ee7d: eb 36 jmp 42eeb5 <__memcmp_sse4_1+0xbb5> + 42ee7f: 48 83 c7 60 add $0x60,%rdi + 42ee83: 48 83 c6 60 add $0x60,%rsi + 42ee87: eb 2c jmp 42eeb5 <__memcmp_sse4_1+0xbb5> + 42ee89: 48 83 c7 50 add $0x50,%rdi + 42ee8d: 48 83 c6 50 add $0x50,%rsi + 42ee91: eb 22 jmp 42eeb5 <__memcmp_sse4_1+0xbb5> + 42ee93: 48 83 c7 40 add $0x40,%rdi + 42ee97: 48 83 c6 40 add $0x40,%rsi + 42ee9b: eb 18 jmp 42eeb5 <__memcmp_sse4_1+0xbb5> + 42ee9d: 48 83 c7 10 add $0x10,%rdi + 42eea1: 48 83 c6 10 add $0x10,%rsi + 42eea5: 48 83 c7 10 add $0x10,%rdi + 42eea9: 48 83 c6 10 add $0x10,%rsi + 42eead: 48 83 c7 10 add $0x10,%rdi + 42eeb1: 48 83 c6 10 add $0x10,%rsi + 42eeb5: 48 8b 47 f0 mov -0x10(%rdi),%rax + 42eeb9: 48 8b 4e f0 mov -0x10(%rsi),%rcx + 42eebd: 48 39 c1 cmp %rax,%rcx + 42eec0: 0f 85 3d 0a 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> + 42eec6: 48 8b 47 f8 mov -0x8(%rdi),%rax + 42eeca: 48 8b 4e f8 mov -0x8(%rsi),%rcx + 42eece: 48 39 c1 cmp %rax,%rcx + 42eed1: 0f 85 2c 0a 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> + 42eed7: 31 c0 xor %eax,%eax + 42eed9: c3 retq + 42eeda: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 42eee0: 48 8b 47 f4 mov -0xc(%rdi),%rax + 42eee4: 48 8b 4e f4 mov -0xc(%rsi),%rcx + 42eee8: 48 39 c1 cmp %rax,%rcx + 42eeeb: 0f 85 12 0a 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> + 42eef1: 8b 4e fc mov -0x4(%rsi),%ecx + 42eef4: 8b 47 fc mov -0x4(%rdi),%eax + 42eef7: 39 c1 cmp %eax,%ecx + 42eef9: 0f 85 10 0a 00 00 jne 42f90f <__memcmp_sse4_1+0x160f> + 42eeff: 31 c0 xor %eax,%eax + 42ef01: c3 retq + 42ef02: 0f 1f 40 00 nopl 0x0(%rax) + 42ef06: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42ef0d: 00 00 00 + 42ef10: f3 0f 6f 4f bf movdqu -0x41(%rdi),%xmm1 + 42ef15: f3 0f 6f 56 bf movdqu -0x41(%rsi),%xmm2 + 42ef1a: b2 bf mov $0xbf,%dl + 42ef1c: 66 0f ef d1 pxor %xmm1,%xmm2 + 42ef20: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42ef25: 0f 83 bd 09 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42ef2b: f3 0f 6f 4f cf movdqu -0x31(%rdi),%xmm1 + 42ef30: f3 0f 6f 56 cf movdqu -0x31(%rsi),%xmm2 + 42ef35: b2 cf mov $0xcf,%dl + 42ef37: 66 0f ef d1 pxor %xmm1,%xmm2 + 42ef3b: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42ef40: 0f 83 a2 09 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42ef46: f3 0f 6f 4f df movdqu -0x21(%rdi),%xmm1 + 42ef4b: f3 0f 6f 56 df movdqu -0x21(%rsi),%xmm2 + 42ef50: b2 df mov $0xdf,%dl + 42ef52: 66 0f ef d1 pxor %xmm1,%xmm2 + 42ef56: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42ef5b: 0f 83 87 09 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42ef61: 48 8b 47 ef mov -0x11(%rdi),%rax + 42ef65: 48 8b 4e ef mov -0x11(%rsi),%rcx + 42ef69: 48 39 c1 cmp %rax,%rcx + 42ef6c: 0f 85 91 09 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> + 42ef72: 48 8b 47 f7 mov -0x9(%rdi),%rax + 42ef76: 48 8b 4e f7 mov -0x9(%rsi),%rcx + 42ef7a: 48 39 c1 cmp %rax,%rcx + 42ef7d: 0f 85 80 09 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> + 42ef83: 0f b6 47 ff movzbl -0x1(%rdi),%eax + 42ef87: 0f b6 56 ff movzbl -0x1(%rsi),%edx + 42ef8b: 29 d0 sub %edx,%eax + 42ef8d: c3 retq + 42ef8e: 66 90 xchg %ax,%ax + 42ef90: 48 8b 47 f3 mov -0xd(%rdi),%rax + 42ef94: 48 8b 4e f3 mov -0xd(%rsi),%rcx + 42ef98: 48 39 c1 cmp %rax,%rcx + 42ef9b: 0f 85 62 09 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> + 42efa1: 48 8b 47 f8 mov -0x8(%rdi),%rax + 42efa5: 48 8b 4e f8 mov -0x8(%rsi),%rcx + 42efa9: 48 39 c1 cmp %rax,%rcx + 42efac: 0f 85 51 09 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> + 42efb2: 31 c0 xor %eax,%eax + 42efb4: c3 retq + 42efb5: 90 nop + 42efb6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42efbd: 00 00 00 + 42efc0: 8b 47 fb mov -0x5(%rdi),%eax + 42efc3: 8b 4e fb mov -0x5(%rsi),%ecx + 42efc6: 39 c1 cmp %eax,%ecx + 42efc8: 0f 85 41 09 00 00 jne 42f90f <__memcmp_sse4_1+0x160f> + 42efce: 0f b6 47 ff movzbl -0x1(%rdi),%eax + 42efd2: 0f b6 56 ff movzbl -0x1(%rsi),%edx + 42efd6: 29 d0 sub %edx,%eax + 42efd8: c3 retq + 42efd9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 42efe0: f3 0f 6f 4f be movdqu -0x42(%rdi),%xmm1 + 42efe5: f3 0f 6f 56 be movdqu -0x42(%rsi),%xmm2 + 42efea: b2 be mov $0xbe,%dl + 42efec: 66 0f ef d1 pxor %xmm1,%xmm2 + 42eff0: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42eff5: 0f 83 ed 08 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42effb: f3 0f 6f 4f ce movdqu -0x32(%rdi),%xmm1 + 42f000: f3 0f 6f 56 ce movdqu -0x32(%rsi),%xmm2 + 42f005: b2 ce mov $0xce,%dl + 42f007: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f00b: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f010: 0f 83 d2 08 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f016: f3 0f 6f 4f de movdqu -0x22(%rdi),%xmm1 + 42f01b: f3 0f 6f 56 de movdqu -0x22(%rsi),%xmm2 + 42f020: b2 de mov $0xde,%dl + 42f022: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f026: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f02b: 0f 83 b7 08 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f031: 48 8b 47 ee mov -0x12(%rdi),%rax + 42f035: 48 8b 4e ee mov -0x12(%rsi),%rcx + 42f039: 48 39 c1 cmp %rax,%rcx + 42f03c: 0f 85 c1 08 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> + 42f042: 48 8b 47 f6 mov -0xa(%rdi),%rax + 42f046: 48 8b 4e f6 mov -0xa(%rsi),%rcx + 42f04a: 48 39 c1 cmp %rax,%rcx + 42f04d: 0f 85 b0 08 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> + 42f053: 0f b7 47 fe movzwl -0x2(%rdi),%eax + 42f057: 0f b7 4e fe movzwl -0x2(%rsi),%ecx + 42f05b: 38 c8 cmp %cl,%al + 42f05d: 0f 85 cd 08 00 00 jne 42f930 <__memcmp_sse4_1+0x1630> + 42f063: 25 ff ff 00 00 and $0xffff,%eax + 42f068: 81 e1 ff ff 00 00 and $0xffff,%ecx + 42f06e: 29 c8 sub %ecx,%eax + 42f070: c3 retq + 42f071: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 42f076: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42f07d: 00 00 00 + 42f080: 48 8b 47 f2 mov -0xe(%rdi),%rax + 42f084: 48 8b 4e f2 mov -0xe(%rsi),%rcx + 42f088: 48 39 c1 cmp %rax,%rcx + 42f08b: 0f 85 72 08 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> + 42f091: 48 8b 47 f8 mov -0x8(%rdi),%rax + 42f095: 48 8b 4e f8 mov -0x8(%rsi),%rcx + 42f099: 48 39 c1 cmp %rax,%rcx + 42f09c: 0f 85 61 08 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> + 42f0a2: 31 c0 xor %eax,%eax + 42f0a4: c3 retq + 42f0a5: 90 nop + 42f0a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42f0ad: 00 00 00 + 42f0b0: 8b 47 fa mov -0x6(%rdi),%eax + 42f0b3: 8b 4e fa mov -0x6(%rsi),%ecx + 42f0b6: 39 c1 cmp %eax,%ecx + 42f0b8: 0f 85 51 08 00 00 jne 42f90f <__memcmp_sse4_1+0x160f> + 42f0be: 0f b7 4e fe movzwl -0x2(%rsi),%ecx + 42f0c2: 0f b7 47 fe movzwl -0x2(%rdi),%eax + 42f0c6: 38 c8 cmp %cl,%al + 42f0c8: 0f 85 62 08 00 00 jne 42f930 <__memcmp_sse4_1+0x1630> + 42f0ce: 25 ff ff 00 00 and $0xffff,%eax + 42f0d3: 81 e1 ff ff 00 00 and $0xffff,%ecx + 42f0d9: 29 c8 sub %ecx,%eax + 42f0db: c3 retq + 42f0dc: 0f 1f 40 00 nopl 0x0(%rax) + 42f0e0: f3 0f 6f 57 bd movdqu -0x43(%rdi),%xmm2 + 42f0e5: f3 0f 6f 4e bd movdqu -0x43(%rsi),%xmm1 + 42f0ea: b2 bd mov $0xbd,%dl + 42f0ec: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f0f0: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f0f5: 0f 83 ed 07 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f0fb: f3 0f 6f 57 cd movdqu -0x33(%rdi),%xmm2 + 42f100: f3 0f 6f 4e cd movdqu -0x33(%rsi),%xmm1 + 42f105: b2 cd mov $0xcd,%dl + 42f107: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f10b: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f110: 0f 83 d2 07 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f116: f3 0f 6f 4e dd movdqu -0x23(%rsi),%xmm1 + 42f11b: f3 0f 6f 57 dd movdqu -0x23(%rdi),%xmm2 + 42f120: b2 dd mov $0xdd,%dl + 42f122: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f126: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f12b: 0f 83 b7 07 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f131: 48 8b 47 ed mov -0x13(%rdi),%rax + 42f135: 48 8b 4e ed mov -0x13(%rsi),%rcx + 42f139: 48 39 c1 cmp %rax,%rcx + 42f13c: 0f 85 c1 07 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> + 42f142: 48 8b 47 f5 mov -0xb(%rdi),%rax + 42f146: 48 8b 4e f5 mov -0xb(%rsi),%rcx + 42f14a: 48 39 c1 cmp %rax,%rcx + 42f14d: 0f 85 b0 07 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> + 42f153: 8b 47 fc mov -0x4(%rdi),%eax + 42f156: 8b 4e fc mov -0x4(%rsi),%ecx + 42f159: 39 c1 cmp %eax,%ecx + 42f15b: 0f 85 ae 07 00 00 jne 42f90f <__memcmp_sse4_1+0x160f> + 42f161: 31 c0 xor %eax,%eax + 42f163: c3 retq + 42f164: 66 90 xchg %ax,%ax + 42f166: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42f16d: 00 00 00 + 42f170: 48 8b 47 f1 mov -0xf(%rdi),%rax + 42f174: 48 8b 4e f1 mov -0xf(%rsi),%rcx + 42f178: 48 39 c1 cmp %rax,%rcx + 42f17b: 0f 85 82 07 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> + 42f181: 48 8b 47 f8 mov -0x8(%rdi),%rax + 42f185: 48 8b 4e f8 mov -0x8(%rsi),%rcx + 42f189: 48 39 c1 cmp %rax,%rcx + 42f18c: 0f 85 71 07 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> + 42f192: 31 c0 xor %eax,%eax + 42f194: c3 retq + 42f195: 90 nop + 42f196: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42f19d: 00 00 00 + 42f1a0: 8b 47 f9 mov -0x7(%rdi),%eax + 42f1a3: 8b 4e f9 mov -0x7(%rsi),%ecx + 42f1a6: 39 c1 cmp %eax,%ecx + 42f1a8: 0f 85 61 07 00 00 jne 42f90f <__memcmp_sse4_1+0x160f> + 42f1ae: 8b 47 fc mov -0x4(%rdi),%eax + 42f1b1: 8b 4e fc mov -0x4(%rsi),%ecx + 42f1b4: 39 c1 cmp %eax,%ecx + 42f1b6: 0f 85 53 07 00 00 jne 42f90f <__memcmp_sse4_1+0x160f> + 42f1bc: 31 c0 xor %eax,%eax + 42f1be: c3 retq + 42f1bf: 90 nop + 42f1c0: 0f b7 47 fd movzwl -0x3(%rdi),%eax + 42f1c4: 0f b7 4e fd movzwl -0x3(%rsi),%ecx + 42f1c8: 39 c1 cmp %eax,%ecx + 42f1ca: 0f 85 4a 07 00 00 jne 42f91a <__memcmp_sse4_1+0x161a> + 42f1d0: 0f b6 47 ff movzbl -0x1(%rdi),%eax + 42f1d4: 0f b6 4e ff movzbl -0x1(%rsi),%ecx + 42f1d8: 29 c8 sub %ecx,%eax + 42f1da: c3 retq + 42f1db: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 42f1e0: f3 0f 6f 57 bc movdqu -0x44(%rdi),%xmm2 + 42f1e5: f3 0f 6f 4e bc movdqu -0x44(%rsi),%xmm1 + 42f1ea: b2 bc mov $0xbc,%dl + 42f1ec: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f1f0: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f1f5: 0f 83 ed 06 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f1fb: f3 0f 6f 57 cc movdqu -0x34(%rdi),%xmm2 + 42f200: f3 0f 6f 4e cc movdqu -0x34(%rsi),%xmm1 + 42f205: b2 cc mov $0xcc,%dl + 42f207: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f20b: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f210: 0f 83 d2 06 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f216: f3 0f 6f 57 dc movdqu -0x24(%rdi),%xmm2 + 42f21b: f3 0f 6f 4e dc movdqu -0x24(%rsi),%xmm1 + 42f220: b2 dc mov $0xdc,%dl + 42f222: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f226: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f22b: 0f 83 b7 06 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f231: f3 0f 6f 57 ec movdqu -0x14(%rdi),%xmm2 + 42f236: f3 0f 6f 4e ec movdqu -0x14(%rsi),%xmm1 + 42f23b: b2 ec mov $0xec,%dl + 42f23d: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f241: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f246: 0f 83 9c 06 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f24c: 8b 4e fc mov -0x4(%rsi),%ecx + 42f24f: 8b 47 fc mov -0x4(%rdi),%eax + 42f252: 39 c1 cmp %eax,%ecx + 42f254: 0f 85 b5 06 00 00 jne 42f90f <__memcmp_sse4_1+0x160f> + 42f25a: 31 c0 xor %eax,%eax + 42f25c: c3 retq + 42f25d: 0f 1f 00 nopl (%rax) + 42f260: f3 0f 6f 4e bb movdqu -0x45(%rsi),%xmm1 + 42f265: f3 0f 6f 57 bb movdqu -0x45(%rdi),%xmm2 + 42f26a: b2 bb mov $0xbb,%dl + 42f26c: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f270: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f275: 0f 83 6d 06 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f27b: f3 0f 6f 4e cb movdqu -0x35(%rsi),%xmm1 + 42f280: f3 0f 6f 57 cb movdqu -0x35(%rdi),%xmm2 + 42f285: b2 cb mov $0xcb,%dl + 42f287: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f28b: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f290: 0f 83 52 06 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f296: f3 0f 6f 4e db movdqu -0x25(%rsi),%xmm1 + 42f29b: f3 0f 6f 57 db movdqu -0x25(%rdi),%xmm2 + 42f2a0: b2 db mov $0xdb,%dl + 42f2a2: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f2a6: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f2ab: 0f 83 37 06 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f2b1: f3 0f 6f 4e eb movdqu -0x15(%rsi),%xmm1 + 42f2b6: f3 0f 6f 57 eb movdqu -0x15(%rdi),%xmm2 + 42f2bb: b2 eb mov $0xeb,%dl + 42f2bd: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f2c1: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f2c6: 0f 83 1c 06 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f2cc: 48 8b 47 f8 mov -0x8(%rdi),%rax + 42f2d0: 48 8b 4e f8 mov -0x8(%rsi),%rcx + 42f2d4: 48 39 c1 cmp %rax,%rcx + 42f2d7: 0f 85 26 06 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> + 42f2dd: 31 c0 xor %eax,%eax + 42f2df: c3 retq + 42f2e0: f3 0f 6f 4e ba movdqu -0x46(%rsi),%xmm1 + 42f2e5: f3 0f 6f 57 ba movdqu -0x46(%rdi),%xmm2 + 42f2ea: b2 ba mov $0xba,%dl + 42f2ec: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f2f0: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f2f5: 0f 83 ed 05 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f2fb: f3 0f 6f 4e ca movdqu -0x36(%rsi),%xmm1 + 42f300: f3 0f 6f 57 ca movdqu -0x36(%rdi),%xmm2 + 42f305: b2 ca mov $0xca,%dl + 42f307: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f30b: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f310: 0f 83 d2 05 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f316: f3 0f 6f 4e da movdqu -0x26(%rsi),%xmm1 + 42f31b: f3 0f 6f 57 da movdqu -0x26(%rdi),%xmm2 + 42f320: b2 da mov $0xda,%dl + 42f322: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f326: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f32b: 0f 83 b7 05 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f331: f3 0f 6f 4e ea movdqu -0x16(%rsi),%xmm1 + 42f336: f3 0f 6f 57 ea movdqu -0x16(%rdi),%xmm2 + 42f33b: b2 ea mov $0xea,%dl + 42f33d: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f341: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f346: 0f 83 9c 05 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f34c: 48 8b 47 f8 mov -0x8(%rdi),%rax + 42f350: 48 8b 4e f8 mov -0x8(%rsi),%rcx + 42f354: 48 39 c1 cmp %rax,%rcx + 42f357: 0f 85 a6 05 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> + 42f35d: 31 c0 xor %eax,%eax + 42f35f: c3 retq + 42f360: f3 0f 6f 4e b9 movdqu -0x47(%rsi),%xmm1 + 42f365: f3 0f 6f 57 b9 movdqu -0x47(%rdi),%xmm2 + 42f36a: b2 b9 mov $0xb9,%dl + 42f36c: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f370: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f375: 0f 83 6d 05 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f37b: f3 0f 6f 57 c9 movdqu -0x37(%rdi),%xmm2 + 42f380: f3 0f 6f 4e c9 movdqu -0x37(%rsi),%xmm1 + 42f385: b2 c9 mov $0xc9,%dl + 42f387: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f38b: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f390: 0f 83 52 05 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f396: f3 0f 6f 57 d9 movdqu -0x27(%rdi),%xmm2 + 42f39b: f3 0f 6f 4e d9 movdqu -0x27(%rsi),%xmm1 + 42f3a0: b2 d9 mov $0xd9,%dl + 42f3a2: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f3a6: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f3ab: 0f 83 37 05 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f3b1: f3 0f 6f 57 e9 movdqu -0x17(%rdi),%xmm2 + 42f3b6: f3 0f 6f 4e e9 movdqu -0x17(%rsi),%xmm1 + 42f3bb: b2 e9 mov $0xe9,%dl + 42f3bd: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f3c1: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f3c6: 0f 83 1c 05 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f3cc: 48 8b 47 f8 mov -0x8(%rdi),%rax + 42f3d0: 48 8b 4e f8 mov -0x8(%rsi),%rcx + 42f3d4: 48 39 c1 cmp %rax,%rcx + 42f3d7: 0f 85 26 05 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> + 42f3dd: 31 c0 xor %eax,%eax + 42f3df: c3 retq + 42f3e0: f3 0f 6f 4e b8 movdqu -0x48(%rsi),%xmm1 + 42f3e5: f3 0f 6f 57 b8 movdqu -0x48(%rdi),%xmm2 + 42f3ea: b2 b8 mov $0xb8,%dl + 42f3ec: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f3f0: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f3f5: 0f 83 ed 04 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f3fb: f3 0f 6f 57 c8 movdqu -0x38(%rdi),%xmm2 + 42f400: f3 0f 6f 4e c8 movdqu -0x38(%rsi),%xmm1 + 42f405: b2 c8 mov $0xc8,%dl + 42f407: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f40b: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f410: 0f 83 d2 04 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f416: f3 0f 6f 57 d8 movdqu -0x28(%rdi),%xmm2 + 42f41b: f3 0f 6f 4e d8 movdqu -0x28(%rsi),%xmm1 + 42f420: b2 d8 mov $0xd8,%dl + 42f422: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f426: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f42b: 0f 83 b7 04 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f431: f3 0f 6f 57 e8 movdqu -0x18(%rdi),%xmm2 + 42f436: f3 0f 6f 4e e8 movdqu -0x18(%rsi),%xmm1 + 42f43b: b2 e8 mov $0xe8,%dl + 42f43d: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f441: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f446: 0f 83 9c 04 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f44c: 48 8b 4e f8 mov -0x8(%rsi),%rcx + 42f450: 48 8b 47 f8 mov -0x8(%rdi),%rax + 42f454: 48 39 c1 cmp %rax,%rcx + 42f457: 0f 85 a6 04 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> + 42f45d: 31 c0 xor %eax,%eax + 42f45f: c3 retq + 42f460: f3 0f 6f 4e b7 movdqu -0x49(%rsi),%xmm1 + 42f465: f3 0f 6f 57 b7 movdqu -0x49(%rdi),%xmm2 + 42f46a: b2 b7 mov $0xb7,%dl + 42f46c: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f470: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f475: 0f 83 6d 04 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f47b: f3 0f 6f 57 c7 movdqu -0x39(%rdi),%xmm2 + 42f480: f3 0f 6f 4e c7 movdqu -0x39(%rsi),%xmm1 + 42f485: b2 c7 mov $0xc7,%dl + 42f487: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f48b: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f490: 0f 83 52 04 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f496: f3 0f 6f 57 d7 movdqu -0x29(%rdi),%xmm2 + 42f49b: f3 0f 6f 4e d7 movdqu -0x29(%rsi),%xmm1 + 42f4a0: b2 d7 mov $0xd7,%dl + 42f4a2: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f4a6: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f4ab: 0f 83 37 04 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f4b1: f3 0f 6f 57 e7 movdqu -0x19(%rdi),%xmm2 + 42f4b6: f3 0f 6f 4e e7 movdqu -0x19(%rsi),%xmm1 + 42f4bb: b2 e7 mov $0xe7,%dl + 42f4bd: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f4c1: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f4c6: 0f 83 1c 04 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f4cc: 48 8b 47 f7 mov -0x9(%rdi),%rax + 42f4d0: 48 8b 4e f7 mov -0x9(%rsi),%rcx + 42f4d4: 48 39 c1 cmp %rax,%rcx + 42f4d7: 0f 85 26 04 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> + 42f4dd: 0f b6 47 ff movzbl -0x1(%rdi),%eax + 42f4e1: 0f b6 4e ff movzbl -0x1(%rsi),%ecx + 42f4e5: 29 c8 sub %ecx,%eax + 42f4e7: c3 retq + 42f4e8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 42f4ef: 00 + 42f4f0: f3 0f 6f 4e b6 movdqu -0x4a(%rsi),%xmm1 + 42f4f5: f3 0f 6f 57 b6 movdqu -0x4a(%rdi),%xmm2 + 42f4fa: b2 b6 mov $0xb6,%dl + 42f4fc: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f500: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f505: 0f 83 dd 03 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f50b: f3 0f 6f 57 c6 movdqu -0x3a(%rdi),%xmm2 + 42f510: f3 0f 6f 4e c6 movdqu -0x3a(%rsi),%xmm1 + 42f515: b2 c6 mov $0xc6,%dl + 42f517: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f51b: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f520: 0f 83 c2 03 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f526: f3 0f 6f 57 d6 movdqu -0x2a(%rdi),%xmm2 + 42f52b: f3 0f 6f 4e d6 movdqu -0x2a(%rsi),%xmm1 + 42f530: b2 d6 mov $0xd6,%dl + 42f532: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f536: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f53b: 0f 83 a7 03 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f541: f3 0f 6f 57 e6 movdqu -0x1a(%rdi),%xmm2 + 42f546: f3 0f 6f 4e e6 movdqu -0x1a(%rsi),%xmm1 + 42f54b: b2 e6 mov $0xe6,%dl + 42f54d: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f551: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f556: 0f 83 8c 03 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f55c: 48 8b 47 f6 mov -0xa(%rdi),%rax + 42f560: 48 8b 4e f6 mov -0xa(%rsi),%rcx + 42f564: 48 39 c1 cmp %rax,%rcx + 42f567: 0f 85 96 03 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> + 42f56d: 0f b7 47 fe movzwl -0x2(%rdi),%eax + 42f571: 0f b7 4e fe movzwl -0x2(%rsi),%ecx + 42f575: e9 a0 03 00 00 jmpq 42f91a <__memcmp_sse4_1+0x161a> + 42f57a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 42f580: f3 0f 6f 4e b5 movdqu -0x4b(%rsi),%xmm1 + 42f585: f3 0f 6f 57 b5 movdqu -0x4b(%rdi),%xmm2 + 42f58a: b2 b5 mov $0xb5,%dl + 42f58c: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f590: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f595: 0f 83 4d 03 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f59b: f3 0f 6f 57 c5 movdqu -0x3b(%rdi),%xmm2 + 42f5a0: f3 0f 6f 4e c5 movdqu -0x3b(%rsi),%xmm1 + 42f5a5: b2 c5 mov $0xc5,%dl + 42f5a7: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f5ab: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f5b0: 0f 83 32 03 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f5b6: f3 0f 6f 57 d5 movdqu -0x2b(%rdi),%xmm2 + 42f5bb: f3 0f 6f 4e d5 movdqu -0x2b(%rsi),%xmm1 + 42f5c0: b2 d5 mov $0xd5,%dl + 42f5c2: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f5c6: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f5cb: 0f 83 17 03 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f5d1: f3 0f 6f 57 e5 movdqu -0x1b(%rdi),%xmm2 + 42f5d6: f3 0f 6f 4e e5 movdqu -0x1b(%rsi),%xmm1 + 42f5db: b2 e5 mov $0xe5,%dl + 42f5dd: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f5e1: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f5e6: 0f 83 fc 02 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f5ec: 48 8b 47 f5 mov -0xb(%rdi),%rax + 42f5f0: 48 8b 4e f5 mov -0xb(%rsi),%rcx + 42f5f4: 48 39 c1 cmp %rax,%rcx + 42f5f7: 0f 85 06 03 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> + 42f5fd: 8b 47 fc mov -0x4(%rdi),%eax + 42f600: 8b 4e fc mov -0x4(%rsi),%ecx + 42f603: 39 c1 cmp %eax,%ecx + 42f605: 0f 85 04 03 00 00 jne 42f90f <__memcmp_sse4_1+0x160f> + 42f60b: 31 c0 xor %eax,%eax + 42f60d: c3 retq + 42f60e: 66 90 xchg %ax,%ax + 42f610: f3 0f 6f 4e b4 movdqu -0x4c(%rsi),%xmm1 + 42f615: f3 0f 6f 57 b4 movdqu -0x4c(%rdi),%xmm2 + 42f61a: b2 b4 mov $0xb4,%dl + 42f61c: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f620: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f625: 0f 83 bd 02 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f62b: f3 0f 6f 57 c4 movdqu -0x3c(%rdi),%xmm2 + 42f630: f3 0f 6f 4e c4 movdqu -0x3c(%rsi),%xmm1 + 42f635: b2 c4 mov $0xc4,%dl + 42f637: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f63b: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f640: 0f 83 a2 02 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f646: f3 0f 6f 57 d4 movdqu -0x2c(%rdi),%xmm2 + 42f64b: f3 0f 6f 4e d4 movdqu -0x2c(%rsi),%xmm1 + 42f650: b2 d4 mov $0xd4,%dl + 42f652: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f656: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f65b: 0f 83 87 02 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f661: f3 0f 6f 57 e4 movdqu -0x1c(%rdi),%xmm2 + 42f666: f3 0f 6f 4e e4 movdqu -0x1c(%rsi),%xmm1 + 42f66b: b2 e4 mov $0xe4,%dl + 42f66d: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f671: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f676: 0f 83 6c 02 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f67c: 48 8b 47 f4 mov -0xc(%rdi),%rax + 42f680: 48 8b 4e f4 mov -0xc(%rsi),%rcx + 42f684: 48 39 c1 cmp %rax,%rcx + 42f687: 0f 85 76 02 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> + 42f68d: 8b 4e fc mov -0x4(%rsi),%ecx + 42f690: 8b 47 fc mov -0x4(%rdi),%eax + 42f693: 39 c1 cmp %eax,%ecx + 42f695: 0f 85 74 02 00 00 jne 42f90f <__memcmp_sse4_1+0x160f> + 42f69b: 31 c0 xor %eax,%eax + 42f69d: c3 retq + 42f69e: 66 90 xchg %ax,%ax + 42f6a0: f3 0f 6f 4e b3 movdqu -0x4d(%rsi),%xmm1 + 42f6a5: f3 0f 6f 57 b3 movdqu -0x4d(%rdi),%xmm2 + 42f6aa: b2 b3 mov $0xb3,%dl + 42f6ac: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f6b0: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f6b5: 0f 83 2d 02 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f6bb: f3 0f 6f 57 c3 movdqu -0x3d(%rdi),%xmm2 + 42f6c0: f3 0f 6f 4e c3 movdqu -0x3d(%rsi),%xmm1 + 42f6c5: b2 c3 mov $0xc3,%dl + 42f6c7: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f6cb: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f6d0: 0f 83 12 02 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f6d6: f3 0f 6f 57 d3 movdqu -0x2d(%rdi),%xmm2 + 42f6db: f3 0f 6f 4e d3 movdqu -0x2d(%rsi),%xmm1 + 42f6e0: b2 d3 mov $0xd3,%dl + 42f6e2: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f6e6: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f6eb: 0f 83 f7 01 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f6f1: f3 0f 6f 57 e3 movdqu -0x1d(%rdi),%xmm2 + 42f6f6: f3 0f 6f 4e e3 movdqu -0x1d(%rsi),%xmm1 + 42f6fb: b2 e3 mov $0xe3,%dl + 42f6fd: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f701: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f706: 0f 83 dc 01 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f70c: 48 8b 47 f3 mov -0xd(%rdi),%rax + 42f710: 48 8b 4e f3 mov -0xd(%rsi),%rcx + 42f714: 48 39 c1 cmp %rax,%rcx + 42f717: 0f 85 e6 01 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> + 42f71d: 48 8b 47 f8 mov -0x8(%rdi),%rax + 42f721: 48 8b 4e f8 mov -0x8(%rsi),%rcx + 42f725: 48 39 c1 cmp %rax,%rcx + 42f728: 0f 85 d5 01 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> + 42f72e: 31 c0 xor %eax,%eax + 42f730: c3 retq + 42f731: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 42f736: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42f73d: 00 00 00 + 42f740: f3 0f 6f 4e b2 movdqu -0x4e(%rsi),%xmm1 + 42f745: f3 0f 6f 57 b2 movdqu -0x4e(%rdi),%xmm2 + 42f74a: b2 b2 mov $0xb2,%dl + 42f74c: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f750: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f755: 0f 83 8d 01 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f75b: f3 0f 6f 57 c2 movdqu -0x3e(%rdi),%xmm2 + 42f760: f3 0f 6f 4e c2 movdqu -0x3e(%rsi),%xmm1 + 42f765: b2 c2 mov $0xc2,%dl + 42f767: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f76b: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f770: 0f 83 72 01 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f776: f3 0f 6f 57 d2 movdqu -0x2e(%rdi),%xmm2 + 42f77b: f3 0f 6f 4e d2 movdqu -0x2e(%rsi),%xmm1 + 42f780: b2 d2 mov $0xd2,%dl + 42f782: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f786: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f78b: 0f 83 57 01 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f791: f3 0f 6f 57 e2 movdqu -0x1e(%rdi),%xmm2 + 42f796: f3 0f 6f 4e e2 movdqu -0x1e(%rsi),%xmm1 + 42f79b: b2 e2 mov $0xe2,%dl + 42f79d: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f7a1: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f7a6: 0f 83 3c 01 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f7ac: 48 8b 47 f2 mov -0xe(%rdi),%rax + 42f7b0: 48 8b 4e f2 mov -0xe(%rsi),%rcx + 42f7b4: 48 39 c1 cmp %rax,%rcx + 42f7b7: 0f 85 46 01 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> + 42f7bd: 48 8b 47 f8 mov -0x8(%rdi),%rax + 42f7c1: 48 8b 4e f8 mov -0x8(%rsi),%rcx + 42f7c5: 48 39 c1 cmp %rax,%rcx + 42f7c8: 0f 85 35 01 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> + 42f7ce: 31 c0 xor %eax,%eax + 42f7d0: c3 retq + 42f7d1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 42f7d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42f7dd: 00 00 00 + 42f7e0: f3 0f 6f 4e b1 movdqu -0x4f(%rsi),%xmm1 + 42f7e5: f3 0f 6f 57 b1 movdqu -0x4f(%rdi),%xmm2 + 42f7ea: b2 b1 mov $0xb1,%dl + 42f7ec: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f7f0: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f7f5: 0f 83 ed 00 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f7fb: f3 0f 6f 57 c1 movdqu -0x3f(%rdi),%xmm2 + 42f800: f3 0f 6f 4e c1 movdqu -0x3f(%rsi),%xmm1 + 42f805: b2 c1 mov $0xc1,%dl + 42f807: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f80b: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f810: 0f 83 d2 00 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f816: f3 0f 6f 57 d1 movdqu -0x2f(%rdi),%xmm2 + 42f81b: f3 0f 6f 4e d1 movdqu -0x2f(%rsi),%xmm1 + 42f820: b2 d1 mov $0xd1,%dl + 42f822: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f826: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f82b: 0f 83 b7 00 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f831: f3 0f 6f 57 e1 movdqu -0x1f(%rdi),%xmm2 + 42f836: f3 0f 6f 4e e1 movdqu -0x1f(%rsi),%xmm1 + 42f83b: b2 e1 mov $0xe1,%dl + 42f83d: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f841: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f846: 0f 83 9c 00 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f84c: 48 8b 47 f1 mov -0xf(%rdi),%rax + 42f850: 48 8b 4e f1 mov -0xf(%rsi),%rcx + 42f854: 48 39 c1 cmp %rax,%rcx + 42f857: 0f 85 a6 00 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> + 42f85d: 48 8b 47 f8 mov -0x8(%rdi),%rax + 42f861: 48 8b 4e f8 mov -0x8(%rsi),%rcx + 42f865: 48 39 c1 cmp %rax,%rcx + 42f868: 0f 85 95 00 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> + 42f86e: 31 c0 xor %eax,%eax + 42f870: c3 retq + 42f871: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 42f876: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42f87d: 00 00 00 + 42f880: f3 0f 6f 57 c0 movdqu -0x40(%rdi),%xmm2 + 42f885: f3 0f 6f 4e c0 movdqu -0x40(%rsi),%xmm1 + 42f88a: b2 c0 mov $0xc0,%dl + 42f88c: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f890: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f895: 73 51 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f897: f3 0f 6f 57 d0 movdqu -0x30(%rdi),%xmm2 + 42f89c: f3 0f 6f 4e d0 movdqu -0x30(%rsi),%xmm1 + 42f8a1: b2 d0 mov $0xd0,%dl + 42f8a3: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f8a7: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f8ac: 73 3a jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f8ae: f3 0f 6f 57 e0 movdqu -0x20(%rdi),%xmm2 + 42f8b3: f3 0f 6f 4e e0 movdqu -0x20(%rsi),%xmm1 + 42f8b8: b2 e0 mov $0xe0,%dl + 42f8ba: 66 0f ef d1 pxor %xmm1,%xmm2 + 42f8be: 66 0f 38 17 c2 ptest %xmm2,%xmm0 + 42f8c3: 73 23 jae 42f8e8 <__memcmp_sse4_1+0x15e8> + 42f8c5: 48 8b 47 f0 mov -0x10(%rdi),%rax + 42f8c9: 48 8b 4e f0 mov -0x10(%rsi),%rcx + 42f8cd: 48 39 c1 cmp %rax,%rcx + 42f8d0: 75 31 jne 42f903 <__memcmp_sse4_1+0x1603> + 42f8d2: 48 8b 47 f8 mov -0x8(%rdi),%rax + 42f8d6: 48 8b 4e f8 mov -0x8(%rsi),%rcx + 42f8da: 48 39 c1 cmp %rax,%rcx + 42f8dd: 75 24 jne 42f903 <__memcmp_sse4_1+0x1603> + 42f8df: 31 c0 xor %eax,%eax + 42f8e1: c3 retq + 42f8e2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 42f8e8: 48 0f be d2 movsbq %dl,%rdx + 42f8ec: 48 8b 0c 16 mov (%rsi,%rdx,1),%rcx + 42f8f0: 48 8b 04 17 mov (%rdi,%rdx,1),%rax + 42f8f4: 48 39 c1 cmp %rax,%rcx + 42f8f7: 75 0a jne 42f903 <__memcmp_sse4_1+0x1603> + 42f8f9: 48 8b 4c 16 08 mov 0x8(%rsi,%rdx,1),%rcx + 42f8fe: 48 8b 44 17 08 mov 0x8(%rdi,%rdx,1),%rax + 42f903: 39 c1 cmp %eax,%ecx + 42f905: 75 08 jne 42f90f <__memcmp_sse4_1+0x160f> + 42f907: 48 c1 e9 20 shr $0x20,%rcx + 42f90b: 48 c1 e8 20 shr $0x20,%rax + 42f90f: 66 39 c8 cmp %cx,%ax + 42f912: 75 06 jne 42f91a <__memcmp_sse4_1+0x161a> + 42f914: c1 e9 10 shr $0x10,%ecx + 42f917: c1 e8 10 shr $0x10,%eax + 42f91a: 38 c8 cmp %cl,%al + 42f91c: 75 12 jne 42f930 <__memcmp_sse4_1+0x1630> + 42f91e: 25 ff ff 00 00 and $0xffff,%eax + 42f923: 81 e1 ff ff 00 00 and $0xffff,%ecx + 42f929: 29 c8 sub %ecx,%eax + 42f92b: c3 retq + 42f92c: 0f 1f 40 00 nopl 0x0(%rax) + 42f930: 25 ff 00 00 00 and $0xff,%eax + 42f935: 81 e1 ff 00 00 00 and $0xff,%ecx + 42f93b: 29 c8 sub %ecx,%eax + 42f93d: c3 retq + 42f93e: 66 90 xchg %ax,%ax + +000000000042f940 <__memmove_chk_ssse3>: + 42f940: 48 39 d1 cmp %rdx,%rcx + 42f943: 0f 82 67 31 01 00 jb 442ab0 <__chk_fail> + 42f949: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + +000000000042f950 <__memmove_ssse3>: + 42f950: 48 89 f8 mov %rdi,%rax + 42f953: 48 39 f7 cmp %rsi,%rdi + 42f956: 72 0e jb 42f966 <__memmove_ssse3+0x16> + 42f958: 0f 84 7a 1a 00 00 je 4313d8 <__memmove_ssse3+0x1a88> + 42f95e: 48 83 fa 4f cmp $0x4f,%rdx + 42f962: 76 02 jbe 42f966 <__memmove_ssse3+0x16> + 42f964: eb 7a jmp 42f9e0 <__memmove_ssse3+0x90> + 42f966: 48 83 fa 4f cmp $0x4f,%rdx + 42f96a: 4c 8d 1d 3f 3a 07 00 lea 0x73a3f(%rip),%r11 # 4a33b0 + 42f971: 77 1d ja 42f990 <__memmove_ssse3+0x40> + 42f973: 4d 63 0c 93 movslq (%r11,%rdx,4),%r9 + 42f977: 48 01 d6 add %rdx,%rsi + 42f97a: 48 01 d7 add %rdx,%rdi + 42f97d: 4d 01 d9 add %r11,%r9 + 42f980: 41 ff e1 jmpq *%r9 + 42f983: 0f 0b ud2 + 42f985: 90 nop + 42f986: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42f98d: 00 00 00 + 42f990: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 42f994: 48 89 f9 mov %rdi,%rcx + 42f997: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi + 42f99b: 48 83 c7 10 add $0x10,%rdi + 42f99f: 49 89 c8 mov %rcx,%r8 + 42f9a2: 48 29 f9 sub %rdi,%rcx + 42f9a5: 48 01 ca add %rcx,%rdx + 42f9a8: 48 29 ce sub %rcx,%rsi + 42f9ab: 48 8b 0d fe b6 29 00 mov 0x29b6fe(%rip),%rcx # 6cb0b0 <__x86_shared_cache_size_half> + 42f9b2: 48 39 ca cmp %rcx,%rdx + 42f9b5: 49 89 f1 mov %rsi,%r9 + 42f9b8: 0f 87 92 27 00 00 ja 432150 <__memmove_ssse3+0x2800> + 42f9be: 49 83 e1 0f and $0xf,%r9 + 42f9c2: 74 7c je 42fa40 <__memmove_ssse3+0xf0> + 42f9c4: 48 8b 0d 05 b7 29 00 mov 0x29b705(%rip),%rcx # 6cb0d0 <__x86_data_cache_size_half> + 42f9cb: 4c 8d 1d 1e 3b 07 00 lea 0x73b1e(%rip),%r11 # 4a34f0 + 42f9d2: 4f 63 0c 8b movslq (%r11,%r9,4),%r9 + 42f9d6: 4f 8d 0c 0b lea (%r11,%r9,1),%r9 + 42f9da: 41 ff e1 jmpq *%r9 + 42f9dd: 0f 0b ud2 + 42f9df: 90 nop + 42f9e0: f3 0f 6f 44 16 f0 movdqu -0x10(%rsi,%rdx,1),%xmm0 + 42f9e6: 48 01 d6 add %rdx,%rsi + 42f9e9: 4c 8d 44 17 f0 lea -0x10(%rdi,%rdx,1),%r8 + 42f9ee: 48 01 d7 add %rdx,%rdi + 42f9f1: 48 89 f9 mov %rdi,%rcx + 42f9f4: 48 83 e1 0f and $0xf,%rcx + 42f9f8: 48 31 cf xor %rcx,%rdi + 42f9fb: 48 29 ca sub %rcx,%rdx + 42f9fe: 48 29 ce sub %rcx,%rsi + 42fa01: 48 8b 0d a8 b6 29 00 mov 0x29b6a8(%rip),%rcx # 6cb0b0 <__x86_shared_cache_size_half> + 42fa08: 48 39 ca cmp %rcx,%rdx + 42fa0b: 49 89 f1 mov %rsi,%r9 + 42fa0e: 0f 87 fc 28 00 00 ja 432310 <__memmove_ssse3+0x29c0> + 42fa14: 49 83 e1 0f and $0xf,%r9 + 42fa18: 0f 84 42 02 00 00 je 42fc60 <__memmove_ssse3+0x310> + 42fa1e: 48 8b 0d ab b6 29 00 mov 0x29b6ab(%rip),%rcx # 6cb0d0 <__x86_data_cache_size_half> + 42fa25: 4c 8d 1d 04 3b 07 00 lea 0x73b04(%rip),%r11 # 4a3530 + 42fa2c: 4f 63 0c 8b movslq (%r11,%r9,4),%r9 + 42fa30: 4f 8d 0c 0b lea (%r11,%r9,1),%r9 + 42fa34: 41 ff e1 jmpq *%r9 + 42fa37: 0f 0b ud2 + 42fa39: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 42fa40: 48 83 ea 10 sub $0x10,%rdx + 42fa44: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 42fa48: 48 83 c6 10 add $0x10,%rsi + 42fa4c: 66 0f 7f 0f movdqa %xmm1,(%rdi) + 42fa50: 48 83 c7 10 add $0x10,%rdi + 42fa54: 48 81 fa 80 00 00 00 cmp $0x80,%rdx + 42fa5b: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 42fa60: 77 4e ja 42fab0 <__memmove_ssse3+0x160> + 42fa62: 48 83 fa 40 cmp $0x40,%rdx + 42fa66: 72 2a jb 42fa92 <__memmove_ssse3+0x142> + 42fa68: 0f 28 26 movaps (%rsi),%xmm4 + 42fa6b: 0f 28 4e 10 movaps 0x10(%rsi),%xmm1 + 42fa6f: 0f 28 56 20 movaps 0x20(%rsi),%xmm2 + 42fa73: 0f 28 5e 30 movaps 0x30(%rsi),%xmm3 + 42fa77: 0f 29 27 movaps %xmm4,(%rdi) + 42fa7a: 0f 29 4f 10 movaps %xmm1,0x10(%rdi) + 42fa7e: 0f 29 57 20 movaps %xmm2,0x20(%rdi) + 42fa82: 0f 29 5f 30 movaps %xmm3,0x30(%rdi) + 42fa86: 48 83 ea 40 sub $0x40,%rdx + 42fa8a: 48 83 c6 40 add $0x40,%rsi + 42fa8e: 48 83 c7 40 add $0x40,%rdi + 42fa92: 48 01 d6 add %rdx,%rsi + 42fa95: 48 01 d7 add %rdx,%rdi + 42fa98: 4c 8d 1d 11 39 07 00 lea 0x73911(%rip),%r11 # 4a33b0 + 42fa9f: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 42faa3: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 42faa7: ff e2 jmpq *%rdx + 42faa9: 0f 0b ud2 + 42faab: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 42fab0: 48 3b 15 19 b6 29 00 cmp 0x29b619(%rip),%rdx # 6cb0d0 <__x86_data_cache_size_half> + 42fab7: 48 8d 52 80 lea -0x80(%rdx),%rdx + 42fabb: 0f 83 af 00 00 00 jae 42fb70 <__memmove_ssse3+0x220> + 42fac1: 66 0f 6f 26 movdqa (%rsi),%xmm4 + 42fac5: 0f 28 4e 10 movaps 0x10(%rsi),%xmm1 + 42fac9: 0f 28 56 20 movaps 0x20(%rsi),%xmm2 + 42facd: 0f 28 5e 30 movaps 0x30(%rsi),%xmm3 + 42fad1: 66 0f 7f 27 movdqa %xmm4,(%rdi) + 42fad5: 0f 29 4f 10 movaps %xmm1,0x10(%rdi) + 42fad9: 0f 29 57 20 movaps %xmm2,0x20(%rdi) + 42fadd: 0f 29 5f 30 movaps %xmm3,0x30(%rdi) + 42fae1: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 42fae8: 0f 28 66 40 movaps 0x40(%rsi),%xmm4 + 42faec: 0f 28 6e 50 movaps 0x50(%rsi),%xmm5 + 42faf0: 0f 28 76 60 movaps 0x60(%rsi),%xmm6 + 42faf4: 0f 28 7e 70 movaps 0x70(%rsi),%xmm7 + 42faf8: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi + 42faff: 0f 29 67 40 movaps %xmm4,0x40(%rdi) + 42fb03: 0f 29 6f 50 movaps %xmm5,0x50(%rdi) + 42fb07: 0f 29 77 60 movaps %xmm6,0x60(%rdi) + 42fb0b: 0f 29 7f 70 movaps %xmm7,0x70(%rdi) + 42fb0f: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi + 42fb16: 73 a9 jae 42fac1 <__memmove_ssse3+0x171> + 42fb18: 48 83 fa c0 cmp $0xffffffffffffffc0,%rdx + 42fb1c: 48 8d 92 80 00 00 00 lea 0x80(%rdx),%rdx + 42fb23: 7c 32 jl 42fb57 <__memmove_ssse3+0x207> + 42fb25: 66 0f 6f 26 movdqa (%rsi),%xmm4 + 42fb29: 48 83 ea 40 sub $0x40,%rdx + 42fb2d: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 + 42fb32: 66 0f 7f 27 movdqa %xmm4,(%rdi) + 42fb36: 66 0f 7f 4f 10 movdqa %xmm1,0x10(%rdi) + 42fb3b: 66 0f 6f 66 20 movdqa 0x20(%rsi),%xmm4 + 42fb40: 66 0f 6f 4e 30 movdqa 0x30(%rsi),%xmm1 + 42fb45: 48 83 c6 40 add $0x40,%rsi + 42fb49: 66 0f 7f 67 20 movdqa %xmm4,0x20(%rdi) + 42fb4e: 66 0f 7f 4f 30 movdqa %xmm1,0x30(%rdi) + 42fb53: 48 83 c7 40 add $0x40,%rdi + 42fb57: 48 01 d6 add %rdx,%rsi + 42fb5a: 48 01 d7 add %rdx,%rdi + 42fb5d: 4c 8d 1d 4c 38 07 00 lea 0x7384c(%rip),%r11 # 4a33b0 + 42fb64: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 42fb68: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 42fb6c: ff e2 jmpq *%rdx + 42fb6e: 0f 0b ud2 + 42fb70: 0f 18 8e c0 01 00 00 prefetcht0 0x1c0(%rsi) + 42fb77: 0f 18 8e 80 02 00 00 prefetcht0 0x280(%rsi) + 42fb7e: 66 0f 6f 06 movdqa (%rsi),%xmm0 + 42fb82: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 + 42fb87: 66 0f 6f 56 20 movdqa 0x20(%rsi),%xmm2 + 42fb8c: 66 0f 6f 5e 30 movdqa 0x30(%rsi),%xmm3 + 42fb91: 66 0f 6f 66 40 movdqa 0x40(%rsi),%xmm4 + 42fb96: 66 0f 6f 6e 50 movdqa 0x50(%rsi),%xmm5 + 42fb9b: 66 0f 6f 76 60 movdqa 0x60(%rsi),%xmm6 + 42fba0: 66 0f 6f 7e 70 movdqa 0x70(%rsi),%xmm7 + 42fba5: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi + 42fbac: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 42fbb3: 66 0f 7f 07 movdqa %xmm0,(%rdi) + 42fbb7: 66 0f 7f 4f 10 movdqa %xmm1,0x10(%rdi) + 42fbbc: 66 0f 7f 57 20 movdqa %xmm2,0x20(%rdi) + 42fbc1: 66 0f 7f 5f 30 movdqa %xmm3,0x30(%rdi) + 42fbc6: 66 0f 7f 67 40 movdqa %xmm4,0x40(%rdi) + 42fbcb: 66 0f 7f 6f 50 movdqa %xmm5,0x50(%rdi) + 42fbd0: 66 0f 7f 77 60 movdqa %xmm6,0x60(%rdi) + 42fbd5: 66 0f 7f 7f 70 movdqa %xmm7,0x70(%rdi) + 42fbda: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi + 42fbe1: 73 8d jae 42fb70 <__memmove_ssse3+0x220> + 42fbe3: 48 83 fa c0 cmp $0xffffffffffffffc0,%rdx + 42fbe7: 48 8d 92 80 00 00 00 lea 0x80(%rdx),%rdx + 42fbee: 7c 32 jl 42fc22 <__memmove_ssse3+0x2d2> + 42fbf0: 66 0f 6f 06 movdqa (%rsi),%xmm0 + 42fbf4: 48 83 ea 40 sub $0x40,%rdx + 42fbf8: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 + 42fbfd: 66 0f 7f 07 movdqa %xmm0,(%rdi) + 42fc01: 66 0f 7f 4f 10 movdqa %xmm1,0x10(%rdi) + 42fc06: 66 0f 6f 46 20 movdqa 0x20(%rsi),%xmm0 + 42fc0b: 66 0f 6f 4e 30 movdqa 0x30(%rsi),%xmm1 + 42fc10: 48 83 c6 40 add $0x40,%rsi + 42fc14: 66 0f 7f 47 20 movdqa %xmm0,0x20(%rdi) + 42fc19: 66 0f 7f 4f 30 movdqa %xmm1,0x30(%rdi) + 42fc1e: 48 83 c7 40 add $0x40,%rdi + 42fc22: 48 83 fa 20 cmp $0x20,%rdx + 42fc26: 72 1e jb 42fc46 <__memmove_ssse3+0x2f6> + 42fc28: 66 0f 6f 06 movdqa (%rsi),%xmm0 + 42fc2c: 48 83 ea 20 sub $0x20,%rdx + 42fc30: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 + 42fc35: 48 83 c6 20 add $0x20,%rsi + 42fc39: 66 0f 7f 07 movdqa %xmm0,(%rdi) + 42fc3d: 66 0f 7f 4f 10 movdqa %xmm1,0x10(%rdi) + 42fc42: 48 83 c7 20 add $0x20,%rdi + 42fc46: 48 01 d7 add %rdx,%rdi + 42fc49: 48 01 d6 add %rdx,%rsi + 42fc4c: 4c 8d 1d 5d 37 07 00 lea 0x7375d(%rip),%r11 # 4a33b0 + 42fc53: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 42fc57: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 42fc5b: ff e2 jmpq *%rdx + 42fc5d: 0f 0b ud2 + 42fc5f: 90 nop + 42fc60: 48 83 ea 10 sub $0x10,%rdx + 42fc64: 66 0f 6f 4e f0 movdqa -0x10(%rsi),%xmm1 + 42fc69: 48 83 ee 10 sub $0x10,%rsi + 42fc6d: 66 0f 7f 4f f0 movdqa %xmm1,-0x10(%rdi) + 42fc72: 48 83 ef 10 sub $0x10,%rdi + 42fc76: 48 81 fa 80 00 00 00 cmp $0x80,%rdx + 42fc7d: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 42fc82: 77 4c ja 42fcd0 <__memmove_ssse3+0x380> + 42fc84: 48 83 fa 40 cmp $0x40,%rdx + 42fc88: 72 2c jb 42fcb6 <__memmove_ssse3+0x366> + 42fc8a: 0f 28 46 f0 movaps -0x10(%rsi),%xmm0 + 42fc8e: 0f 28 4e e0 movaps -0x20(%rsi),%xmm1 + 42fc92: 0f 28 56 d0 movaps -0x30(%rsi),%xmm2 + 42fc96: 0f 28 5e c0 movaps -0x40(%rsi),%xmm3 + 42fc9a: 0f 29 47 f0 movaps %xmm0,-0x10(%rdi) + 42fc9e: 0f 29 4f e0 movaps %xmm1,-0x20(%rdi) + 42fca2: 0f 29 57 d0 movaps %xmm2,-0x30(%rdi) + 42fca6: 0f 29 5f c0 movaps %xmm3,-0x40(%rdi) + 42fcaa: 48 83 ea 40 sub $0x40,%rdx + 42fcae: 48 83 ee 40 sub $0x40,%rsi + 42fcb2: 48 83 ef 40 sub $0x40,%rdi + 42fcb6: 4c 8d 1d f3 36 07 00 lea 0x736f3(%rip),%r11 # 4a33b0 + 42fcbd: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 42fcc1: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 42fcc5: ff e2 jmpq *%rdx + 42fcc7: 0f 0b ud2 + 42fcc9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 42fcd0: 48 3b 15 f9 b3 29 00 cmp 0x29b3f9(%rip),%rdx # 6cb0d0 <__x86_data_cache_size_half> + 42fcd7: 48 8d 52 80 lea -0x80(%rdx),%rdx + 42fcdb: 0f 83 af 00 00 00 jae 42fd90 <__memmove_ssse3+0x440> + 42fce1: 66 0f 6f 46 f0 movdqa -0x10(%rsi),%xmm0 + 42fce6: 0f 28 4e e0 movaps -0x20(%rsi),%xmm1 + 42fcea: 0f 28 56 d0 movaps -0x30(%rsi),%xmm2 + 42fcee: 0f 28 5e c0 movaps -0x40(%rsi),%xmm3 + 42fcf2: 66 0f 7f 47 f0 movdqa %xmm0,-0x10(%rdi) + 42fcf7: 0f 29 4f e0 movaps %xmm1,-0x20(%rdi) + 42fcfb: 0f 29 57 d0 movaps %xmm2,-0x30(%rdi) + 42fcff: 0f 29 5f c0 movaps %xmm3,-0x40(%rdi) + 42fd03: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 42fd0a: 0f 28 66 b0 movaps -0x50(%rsi),%xmm4 + 42fd0e: 0f 28 6e a0 movaps -0x60(%rsi),%xmm5 + 42fd12: 0f 28 76 90 movaps -0x70(%rsi),%xmm6 + 42fd16: 0f 28 7e 80 movaps -0x80(%rsi),%xmm7 + 42fd1a: 48 8d 76 80 lea -0x80(%rsi),%rsi + 42fd1e: 0f 29 67 b0 movaps %xmm4,-0x50(%rdi) + 42fd22: 0f 29 6f a0 movaps %xmm5,-0x60(%rdi) + 42fd26: 0f 29 77 90 movaps %xmm6,-0x70(%rdi) + 42fd2a: 0f 29 7f 80 movaps %xmm7,-0x80(%rdi) + 42fd2e: 48 8d 7f 80 lea -0x80(%rdi),%rdi + 42fd32: 73 ad jae 42fce1 <__memmove_ssse3+0x391> + 42fd34: 48 83 fa c0 cmp $0xffffffffffffffc0,%rdx + 42fd38: 48 8d 92 80 00 00 00 lea 0x80(%rdx),%rdx + 42fd3f: 7c 34 jl 42fd75 <__memmove_ssse3+0x425> + 42fd41: 66 0f 6f 46 f0 movdqa -0x10(%rsi),%xmm0 + 42fd46: 48 83 ea 40 sub $0x40,%rdx + 42fd4a: 66 0f 6f 4e e0 movdqa -0x20(%rsi),%xmm1 + 42fd4f: 66 0f 7f 47 f0 movdqa %xmm0,-0x10(%rdi) + 42fd54: 66 0f 7f 4f e0 movdqa %xmm1,-0x20(%rdi) + 42fd59: 66 0f 6f 46 d0 movdqa -0x30(%rsi),%xmm0 + 42fd5e: 66 0f 6f 4e c0 movdqa -0x40(%rsi),%xmm1 + 42fd63: 48 83 ee 40 sub $0x40,%rsi + 42fd67: 66 0f 7f 47 d0 movdqa %xmm0,-0x30(%rdi) + 42fd6c: 66 0f 7f 4f c0 movdqa %xmm1,-0x40(%rdi) + 42fd71: 48 83 ef 40 sub $0x40,%rdi + 42fd75: 4c 8d 1d 34 36 07 00 lea 0x73634(%rip),%r11 # 4a33b0 + 42fd7c: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 42fd80: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 42fd84: ff e2 jmpq *%rdx + 42fd86: 0f 0b ud2 + 42fd88: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 42fd8f: 00 + 42fd90: 0f 18 8e 40 fe ff ff prefetcht0 -0x1c0(%rsi) + 42fd97: 0f 18 8e 80 fd ff ff prefetcht0 -0x280(%rsi) + 42fd9e: 66 0f 6f 46 f0 movdqa -0x10(%rsi),%xmm0 + 42fda3: 66 0f 6f 4e e0 movdqa -0x20(%rsi),%xmm1 + 42fda8: 66 0f 6f 56 d0 movdqa -0x30(%rsi),%xmm2 + 42fdad: 66 0f 6f 5e c0 movdqa -0x40(%rsi),%xmm3 + 42fdb2: 66 0f 6f 66 b0 movdqa -0x50(%rsi),%xmm4 + 42fdb7: 66 0f 6f 6e a0 movdqa -0x60(%rsi),%xmm5 + 42fdbc: 66 0f 6f 76 90 movdqa -0x70(%rsi),%xmm6 + 42fdc1: 66 0f 6f 7e 80 movdqa -0x80(%rsi),%xmm7 + 42fdc6: 48 8d 76 80 lea -0x80(%rsi),%rsi + 42fdca: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 42fdd1: 66 0f 7f 47 f0 movdqa %xmm0,-0x10(%rdi) + 42fdd6: 66 0f 7f 4f e0 movdqa %xmm1,-0x20(%rdi) + 42fddb: 66 0f 7f 57 d0 movdqa %xmm2,-0x30(%rdi) + 42fde0: 66 0f 7f 5f c0 movdqa %xmm3,-0x40(%rdi) + 42fde5: 66 0f 7f 67 b0 movdqa %xmm4,-0x50(%rdi) + 42fdea: 66 0f 7f 6f a0 movdqa %xmm5,-0x60(%rdi) + 42fdef: 66 0f 7f 77 90 movdqa %xmm6,-0x70(%rdi) + 42fdf4: 66 0f 7f 7f 80 movdqa %xmm7,-0x80(%rdi) + 42fdf9: 48 8d 7f 80 lea -0x80(%rdi),%rdi + 42fdfd: 73 91 jae 42fd90 <__memmove_ssse3+0x440> + 42fdff: 48 83 fa c0 cmp $0xffffffffffffffc0,%rdx + 42fe03: 48 8d 92 80 00 00 00 lea 0x80(%rdx),%rdx + 42fe0a: 7c 34 jl 42fe40 <__memmove_ssse3+0x4f0> + 42fe0c: 66 0f 6f 46 f0 movdqa -0x10(%rsi),%xmm0 + 42fe11: 48 83 ea 40 sub $0x40,%rdx + 42fe15: 66 0f 6f 4e e0 movdqa -0x20(%rsi),%xmm1 + 42fe1a: 66 0f 7f 47 f0 movdqa %xmm0,-0x10(%rdi) + 42fe1f: 66 0f 7f 4f e0 movdqa %xmm1,-0x20(%rdi) + 42fe24: 66 0f 6f 46 d0 movdqa -0x30(%rsi),%xmm0 + 42fe29: 66 0f 6f 4e c0 movdqa -0x40(%rsi),%xmm1 + 42fe2e: 48 83 ee 40 sub $0x40,%rsi + 42fe32: 66 0f 7f 47 d0 movdqa %xmm0,-0x30(%rdi) + 42fe37: 66 0f 7f 4f c0 movdqa %xmm1,-0x40(%rdi) + 42fe3c: 48 83 ef 40 sub $0x40,%rdi + 42fe40: 48 83 fa 20 cmp $0x20,%rdx + 42fe44: 72 20 jb 42fe66 <__memmove_ssse3+0x516> + 42fe46: 66 0f 6f 46 f0 movdqa -0x10(%rsi),%xmm0 + 42fe4b: 48 83 ea 20 sub $0x20,%rdx + 42fe4f: 66 0f 6f 4e e0 movdqa -0x20(%rsi),%xmm1 + 42fe54: 48 83 ee 20 sub $0x20,%rsi + 42fe58: 66 0f 7f 47 f0 movdqa %xmm0,-0x10(%rdi) + 42fe5d: 66 0f 7f 4f e0 movdqa %xmm1,-0x20(%rdi) + 42fe62: 48 83 ef 20 sub $0x20,%rdi + 42fe66: 4c 8d 1d 43 35 07 00 lea 0x73543(%rip),%r11 # 4a33b0 + 42fe6d: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 42fe71: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 42fe75: ff e2 jmpq *%rdx + 42fe77: 0f 0b ud2 + 42fe79: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 42fe80: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 + 42fe87: 48 39 ca cmp %rcx,%rdx + 42fe8a: 0f 28 4e ff movaps -0x1(%rsi),%xmm1 + 42fe8e: 72 07 jb 42fe97 <__memmove_ssse3+0x547> + 42fe90: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 + 42fe97: 48 8d 52 c0 lea -0x40(%rdx),%rdx + 42fe9b: 41 ff e1 jmpq *%r9 + 42fe9e: 0f 0b ud2 + 42fea0: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) + 42fea7: 48 83 ea 40 sub $0x40,%rdx + 42feab: 0f 28 56 0f movaps 0xf(%rsi),%xmm2 + 42feaf: 0f 28 5e 1f movaps 0x1f(%rsi),%xmm3 + 42feb3: 0f 28 66 2f movaps 0x2f(%rsi),%xmm4 + 42feb7: 0f 28 6e 3f movaps 0x3f(%rsi),%xmm5 + 42febb: 66 0f 6f f5 movdqa %xmm5,%xmm6 + 42febf: 66 0f 3a 0f ec 01 palignr $0x1,%xmm4,%xmm5 + 42fec5: 48 8d 76 40 lea 0x40(%rsi),%rsi + 42fec9: 66 0f 3a 0f e3 01 palignr $0x1,%xmm3,%xmm4 + 42fecf: 66 0f 3a 0f da 01 palignr $0x1,%xmm2,%xmm3 + 42fed5: 48 8d 7f 40 lea 0x40(%rdi),%rdi + 42fed9: 66 0f 3a 0f d1 01 palignr $0x1,%xmm1,%xmm2 + 42fedf: 66 0f 6f ce movdqa %xmm6,%xmm1 + 42fee3: 66 0f 7f 57 c0 movdqa %xmm2,-0x40(%rdi) + 42fee8: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 42feec: 72 0d jb 42fefb <__memmove_ssse3+0x5ab> + 42feee: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) + 42fef2: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) + 42fef6: 41 ff e1 jmpq *%r9 + 42fef9: 0f 0b ud2 + 42fefb: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) + 42feff: 48 8d 52 40 lea 0x40(%rdx),%rdx + 42ff03: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) + 42ff07: 48 01 d7 add %rdx,%rdi + 42ff0a: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 42ff0f: 48 01 d6 add %rdx,%rsi + 42ff12: 4c 8d 1d 97 34 07 00 lea 0x73497(%rip),%r11 # 4a33b0 + 42ff19: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 42ff1d: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 42ff21: ff e2 jmpq *%rdx + 42ff23: 0f 0b ud2 + 42ff25: 90 nop + 42ff26: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42ff2d: 00 00 00 + 42ff30: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 + 42ff37: 48 39 ca cmp %rcx,%rdx + 42ff3a: 0f 28 4e ff movaps -0x1(%rsi),%xmm1 + 42ff3e: 72 07 jb 42ff47 <__memmove_ssse3+0x5f7> + 42ff40: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 + 42ff47: 48 8d 52 c0 lea -0x40(%rdx),%rdx + 42ff4b: 41 ff e1 jmpq *%r9 + 42ff4e: 0f 0b ud2 + 42ff50: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) + 42ff57: 0f 28 56 ef movaps -0x11(%rsi),%xmm2 + 42ff5b: 48 83 ea 40 sub $0x40,%rdx + 42ff5f: 0f 28 5e df movaps -0x21(%rsi),%xmm3 + 42ff63: 0f 28 66 cf movaps -0x31(%rsi),%xmm4 + 42ff67: 0f 28 6e bf movaps -0x41(%rsi),%xmm5 + 42ff6b: 48 8d 76 c0 lea -0x40(%rsi),%rsi + 42ff6f: 66 0f 3a 0f ca 01 palignr $0x1,%xmm2,%xmm1 + 42ff75: 66 0f 3a 0f d3 01 palignr $0x1,%xmm3,%xmm2 + 42ff7b: 66 0f 3a 0f dc 01 palignr $0x1,%xmm4,%xmm3 + 42ff81: 66 0f 3a 0f e5 01 palignr $0x1,%xmm5,%xmm4 + 42ff87: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 42ff8b: 0f 28 cd movaps %xmm5,%xmm1 + 42ff8e: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 42ff92: 48 8d 7f c0 lea -0x40(%rdi),%rdi + 42ff96: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) + 42ff9a: 72 08 jb 42ffa4 <__memmove_ssse3+0x654> + 42ff9c: 0f 29 27 movaps %xmm4,(%rdi) + 42ff9f: 41 ff e1 jmpq *%r9 + 42ffa2: 0f 0b ud2 + 42ffa4: 0f 29 27 movaps %xmm4,(%rdi) + 42ffa7: 48 8d 52 40 lea 0x40(%rdx),%rdx + 42ffab: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 42ffb0: 4c 8d 1d f9 33 07 00 lea 0x733f9(%rip),%r11 # 4a33b0 + 42ffb7: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 42ffbb: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 42ffbf: ff e2 jmpq *%rdx + 42ffc1: 0f 0b ud2 + 42ffc3: 0f 1f 00 nopl (%rax) + 42ffc6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 42ffcd: 00 00 00 + 42ffd0: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 + 42ffd7: 48 39 ca cmp %rcx,%rdx + 42ffda: 0f 28 4e fe movaps -0x2(%rsi),%xmm1 + 42ffde: 72 07 jb 42ffe7 <__memmove_ssse3+0x697> + 42ffe0: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 + 42ffe7: 48 8d 52 c0 lea -0x40(%rdx),%rdx + 42ffeb: 41 ff e1 jmpq *%r9 + 42ffee: 0f 0b ud2 + 42fff0: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) + 42fff7: 48 83 ea 40 sub $0x40,%rdx + 42fffb: 0f 28 56 0e movaps 0xe(%rsi),%xmm2 + 42ffff: 0f 28 5e 1e movaps 0x1e(%rsi),%xmm3 + 430003: 0f 28 66 2e movaps 0x2e(%rsi),%xmm4 + 430007: 0f 28 6e 3e movaps 0x3e(%rsi),%xmm5 + 43000b: 66 0f 6f f5 movdqa %xmm5,%xmm6 + 43000f: 66 0f 3a 0f ec 02 palignr $0x2,%xmm4,%xmm5 + 430015: 48 8d 76 40 lea 0x40(%rsi),%rsi + 430019: 66 0f 3a 0f e3 02 palignr $0x2,%xmm3,%xmm4 + 43001f: 66 0f 3a 0f da 02 palignr $0x2,%xmm2,%xmm3 + 430025: 48 8d 7f 40 lea 0x40(%rdi),%rdi + 430029: 66 0f 3a 0f d1 02 palignr $0x2,%xmm1,%xmm2 + 43002f: 66 0f 6f ce movdqa %xmm6,%xmm1 + 430033: 66 0f 7f 57 c0 movdqa %xmm2,-0x40(%rdi) + 430038: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 43003c: 72 0d jb 43004b <__memmove_ssse3+0x6fb> + 43003e: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) + 430042: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) + 430046: 41 ff e1 jmpq *%r9 + 430049: 0f 0b ud2 + 43004b: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) + 43004f: 48 8d 52 40 lea 0x40(%rdx),%rdx + 430053: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) + 430057: 48 01 d7 add %rdx,%rdi + 43005a: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 43005f: 48 01 d6 add %rdx,%rsi + 430062: 4c 8d 1d 47 33 07 00 lea 0x73347(%rip),%r11 # 4a33b0 + 430069: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 43006d: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 430071: ff e2 jmpq *%rdx + 430073: 0f 0b ud2 + 430075: 90 nop + 430076: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43007d: 00 00 00 + 430080: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 + 430087: 48 39 ca cmp %rcx,%rdx + 43008a: 0f 28 4e fe movaps -0x2(%rsi),%xmm1 + 43008e: 72 07 jb 430097 <__memmove_ssse3+0x747> + 430090: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 + 430097: 48 8d 52 c0 lea -0x40(%rdx),%rdx + 43009b: 41 ff e1 jmpq *%r9 + 43009e: 0f 0b ud2 + 4300a0: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) + 4300a7: 0f 28 56 ee movaps -0x12(%rsi),%xmm2 + 4300ab: 48 83 ea 40 sub $0x40,%rdx + 4300af: 0f 28 5e de movaps -0x22(%rsi),%xmm3 + 4300b3: 0f 28 66 ce movaps -0x32(%rsi),%xmm4 + 4300b7: 0f 28 6e be movaps -0x42(%rsi),%xmm5 + 4300bb: 48 8d 76 c0 lea -0x40(%rsi),%rsi + 4300bf: 66 0f 3a 0f ca 02 palignr $0x2,%xmm2,%xmm1 + 4300c5: 66 0f 3a 0f d3 02 palignr $0x2,%xmm3,%xmm2 + 4300cb: 66 0f 3a 0f dc 02 palignr $0x2,%xmm4,%xmm3 + 4300d1: 66 0f 3a 0f e5 02 palignr $0x2,%xmm5,%xmm4 + 4300d7: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 4300db: 0f 28 cd movaps %xmm5,%xmm1 + 4300de: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 4300e2: 48 8d 7f c0 lea -0x40(%rdi),%rdi + 4300e6: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) + 4300ea: 72 08 jb 4300f4 <__memmove_ssse3+0x7a4> + 4300ec: 0f 29 27 movaps %xmm4,(%rdi) + 4300ef: 41 ff e1 jmpq *%r9 + 4300f2: 0f 0b ud2 + 4300f4: 0f 29 27 movaps %xmm4,(%rdi) + 4300f7: 48 8d 52 40 lea 0x40(%rdx),%rdx + 4300fb: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 430100: 4c 8d 1d a9 32 07 00 lea 0x732a9(%rip),%r11 # 4a33b0 + 430107: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 43010b: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 43010f: ff e2 jmpq *%rdx + 430111: 0f 0b ud2 + 430113: 0f 1f 00 nopl (%rax) + 430116: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43011d: 00 00 00 + 430120: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 + 430127: 48 39 ca cmp %rcx,%rdx + 43012a: 0f 28 4e fd movaps -0x3(%rsi),%xmm1 + 43012e: 72 07 jb 430137 <__memmove_ssse3+0x7e7> + 430130: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 + 430137: 48 8d 52 c0 lea -0x40(%rdx),%rdx + 43013b: 41 ff e1 jmpq *%r9 + 43013e: 0f 0b ud2 + 430140: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) + 430147: 48 83 ea 40 sub $0x40,%rdx + 43014b: 0f 28 56 0d movaps 0xd(%rsi),%xmm2 + 43014f: 0f 28 5e 1d movaps 0x1d(%rsi),%xmm3 + 430153: 0f 28 66 2d movaps 0x2d(%rsi),%xmm4 + 430157: 0f 28 6e 3d movaps 0x3d(%rsi),%xmm5 + 43015b: 66 0f 6f f5 movdqa %xmm5,%xmm6 + 43015f: 66 0f 3a 0f ec 03 palignr $0x3,%xmm4,%xmm5 + 430165: 48 8d 76 40 lea 0x40(%rsi),%rsi + 430169: 66 0f 3a 0f e3 03 palignr $0x3,%xmm3,%xmm4 + 43016f: 66 0f 3a 0f da 03 palignr $0x3,%xmm2,%xmm3 + 430175: 48 8d 7f 40 lea 0x40(%rdi),%rdi + 430179: 66 0f 3a 0f d1 03 palignr $0x3,%xmm1,%xmm2 + 43017f: 66 0f 6f ce movdqa %xmm6,%xmm1 + 430183: 66 0f 7f 57 c0 movdqa %xmm2,-0x40(%rdi) + 430188: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 43018c: 72 0d jb 43019b <__memmove_ssse3+0x84b> + 43018e: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) + 430192: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) + 430196: 41 ff e1 jmpq *%r9 + 430199: 0f 0b ud2 + 43019b: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) + 43019f: 48 8d 52 40 lea 0x40(%rdx),%rdx + 4301a3: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) + 4301a7: 48 01 d7 add %rdx,%rdi + 4301aa: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 4301af: 48 01 d6 add %rdx,%rsi + 4301b2: 4c 8d 1d f7 31 07 00 lea 0x731f7(%rip),%r11 # 4a33b0 + 4301b9: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 4301bd: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 4301c1: ff e2 jmpq *%rdx + 4301c3: 0f 0b ud2 + 4301c5: 90 nop + 4301c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4301cd: 00 00 00 + 4301d0: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 + 4301d7: 48 39 ca cmp %rcx,%rdx + 4301da: 0f 28 4e fd movaps -0x3(%rsi),%xmm1 + 4301de: 72 07 jb 4301e7 <__memmove_ssse3+0x897> + 4301e0: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 + 4301e7: 48 8d 52 c0 lea -0x40(%rdx),%rdx + 4301eb: 41 ff e1 jmpq *%r9 + 4301ee: 0f 0b ud2 + 4301f0: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) + 4301f7: 0f 28 56 ed movaps -0x13(%rsi),%xmm2 + 4301fb: 48 83 ea 40 sub $0x40,%rdx + 4301ff: 0f 28 5e dd movaps -0x23(%rsi),%xmm3 + 430203: 0f 28 66 cd movaps -0x33(%rsi),%xmm4 + 430207: 0f 28 6e bd movaps -0x43(%rsi),%xmm5 + 43020b: 48 8d 76 c0 lea -0x40(%rsi),%rsi + 43020f: 66 0f 3a 0f ca 03 palignr $0x3,%xmm2,%xmm1 + 430215: 66 0f 3a 0f d3 03 palignr $0x3,%xmm3,%xmm2 + 43021b: 66 0f 3a 0f dc 03 palignr $0x3,%xmm4,%xmm3 + 430221: 66 0f 3a 0f e5 03 palignr $0x3,%xmm5,%xmm4 + 430227: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 43022b: 0f 28 cd movaps %xmm5,%xmm1 + 43022e: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 430232: 48 8d 7f c0 lea -0x40(%rdi),%rdi + 430236: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) + 43023a: 72 08 jb 430244 <__memmove_ssse3+0x8f4> + 43023c: 0f 29 27 movaps %xmm4,(%rdi) + 43023f: 41 ff e1 jmpq *%r9 + 430242: 0f 0b ud2 + 430244: 0f 29 27 movaps %xmm4,(%rdi) + 430247: 48 8d 52 40 lea 0x40(%rdx),%rdx + 43024b: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 430250: 4c 8d 1d 59 31 07 00 lea 0x73159(%rip),%r11 # 4a33b0 + 430257: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 43025b: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 43025f: ff e2 jmpq *%rdx + 430261: 0f 0b ud2 + 430263: 0f 1f 00 nopl (%rax) + 430266: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43026d: 00 00 00 + 430270: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 + 430277: 48 39 ca cmp %rcx,%rdx + 43027a: 0f 28 4e fc movaps -0x4(%rsi),%xmm1 + 43027e: 72 07 jb 430287 <__memmove_ssse3+0x937> + 430280: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 + 430287: 48 8d 52 c0 lea -0x40(%rdx),%rdx + 43028b: 41 ff e1 jmpq *%r9 + 43028e: 0f 0b ud2 + 430290: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) + 430297: 48 83 ea 40 sub $0x40,%rdx + 43029b: 0f 28 56 0c movaps 0xc(%rsi),%xmm2 + 43029f: 0f 28 5e 1c movaps 0x1c(%rsi),%xmm3 + 4302a3: 0f 28 66 2c movaps 0x2c(%rsi),%xmm4 + 4302a7: 0f 28 6e 3c movaps 0x3c(%rsi),%xmm5 + 4302ab: 66 0f 6f f5 movdqa %xmm5,%xmm6 + 4302af: 66 0f 3a 0f ec 04 palignr $0x4,%xmm4,%xmm5 + 4302b5: 48 8d 76 40 lea 0x40(%rsi),%rsi + 4302b9: 66 0f 3a 0f e3 04 palignr $0x4,%xmm3,%xmm4 + 4302bf: 66 0f 3a 0f da 04 palignr $0x4,%xmm2,%xmm3 + 4302c5: 48 8d 7f 40 lea 0x40(%rdi),%rdi + 4302c9: 66 0f 3a 0f d1 04 palignr $0x4,%xmm1,%xmm2 + 4302cf: 66 0f 6f ce movdqa %xmm6,%xmm1 + 4302d3: 66 0f 7f 57 c0 movdqa %xmm2,-0x40(%rdi) + 4302d8: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 4302dc: 72 0d jb 4302eb <__memmove_ssse3+0x99b> + 4302de: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) + 4302e2: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) + 4302e6: 41 ff e1 jmpq *%r9 + 4302e9: 0f 0b ud2 + 4302eb: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) + 4302ef: 48 8d 52 40 lea 0x40(%rdx),%rdx + 4302f3: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) + 4302f7: 48 01 d7 add %rdx,%rdi + 4302fa: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 4302ff: 48 01 d6 add %rdx,%rsi + 430302: 4c 8d 1d a7 30 07 00 lea 0x730a7(%rip),%r11 # 4a33b0 + 430309: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 43030d: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 430311: ff e2 jmpq *%rdx + 430313: 0f 0b ud2 + 430315: 90 nop + 430316: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43031d: 00 00 00 + 430320: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 + 430327: 48 39 ca cmp %rcx,%rdx + 43032a: 0f 28 4e fc movaps -0x4(%rsi),%xmm1 + 43032e: 72 07 jb 430337 <__memmove_ssse3+0x9e7> + 430330: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 + 430337: 48 8d 52 c0 lea -0x40(%rdx),%rdx + 43033b: 41 ff e1 jmpq *%r9 + 43033e: 0f 0b ud2 + 430340: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) + 430347: 0f 28 56 ec movaps -0x14(%rsi),%xmm2 + 43034b: 48 83 ea 40 sub $0x40,%rdx + 43034f: 0f 28 5e dc movaps -0x24(%rsi),%xmm3 + 430353: 0f 28 66 cc movaps -0x34(%rsi),%xmm4 + 430357: 0f 28 6e bc movaps -0x44(%rsi),%xmm5 + 43035b: 48 8d 76 c0 lea -0x40(%rsi),%rsi + 43035f: 66 0f 3a 0f ca 04 palignr $0x4,%xmm2,%xmm1 + 430365: 66 0f 3a 0f d3 04 palignr $0x4,%xmm3,%xmm2 + 43036b: 66 0f 3a 0f dc 04 palignr $0x4,%xmm4,%xmm3 + 430371: 66 0f 3a 0f e5 04 palignr $0x4,%xmm5,%xmm4 + 430377: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 43037b: 0f 28 cd movaps %xmm5,%xmm1 + 43037e: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 430382: 48 8d 7f c0 lea -0x40(%rdi),%rdi + 430386: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) + 43038a: 72 08 jb 430394 <__memmove_ssse3+0xa44> + 43038c: 0f 29 27 movaps %xmm4,(%rdi) + 43038f: 41 ff e1 jmpq *%r9 + 430392: 0f 0b ud2 + 430394: 0f 29 27 movaps %xmm4,(%rdi) + 430397: 48 8d 52 40 lea 0x40(%rdx),%rdx + 43039b: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 4303a0: 4c 8d 1d 09 30 07 00 lea 0x73009(%rip),%r11 # 4a33b0 + 4303a7: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 4303ab: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 4303af: ff e2 jmpq *%rdx + 4303b1: 0f 0b ud2 + 4303b3: 0f 1f 00 nopl (%rax) + 4303b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4303bd: 00 00 00 + 4303c0: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 + 4303c7: 48 39 ca cmp %rcx,%rdx + 4303ca: 0f 28 4e fb movaps -0x5(%rsi),%xmm1 + 4303ce: 72 07 jb 4303d7 <__memmove_ssse3+0xa87> + 4303d0: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 + 4303d7: 48 8d 52 c0 lea -0x40(%rdx),%rdx + 4303db: 41 ff e1 jmpq *%r9 + 4303de: 0f 0b ud2 + 4303e0: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) + 4303e7: 48 83 ea 40 sub $0x40,%rdx + 4303eb: 0f 28 56 0b movaps 0xb(%rsi),%xmm2 + 4303ef: 0f 28 5e 1b movaps 0x1b(%rsi),%xmm3 + 4303f3: 0f 28 66 2b movaps 0x2b(%rsi),%xmm4 + 4303f7: 0f 28 6e 3b movaps 0x3b(%rsi),%xmm5 + 4303fb: 66 0f 6f f5 movdqa %xmm5,%xmm6 + 4303ff: 66 0f 3a 0f ec 05 palignr $0x5,%xmm4,%xmm5 + 430405: 48 8d 76 40 lea 0x40(%rsi),%rsi + 430409: 66 0f 3a 0f e3 05 palignr $0x5,%xmm3,%xmm4 + 43040f: 66 0f 3a 0f da 05 palignr $0x5,%xmm2,%xmm3 + 430415: 48 8d 7f 40 lea 0x40(%rdi),%rdi + 430419: 66 0f 3a 0f d1 05 palignr $0x5,%xmm1,%xmm2 + 43041f: 66 0f 6f ce movdqa %xmm6,%xmm1 + 430423: 66 0f 7f 57 c0 movdqa %xmm2,-0x40(%rdi) + 430428: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 43042c: 72 0d jb 43043b <__memmove_ssse3+0xaeb> + 43042e: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) + 430432: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) + 430436: 41 ff e1 jmpq *%r9 + 430439: 0f 0b ud2 + 43043b: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) + 43043f: 48 8d 52 40 lea 0x40(%rdx),%rdx + 430443: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) + 430447: 48 01 d7 add %rdx,%rdi + 43044a: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 43044f: 48 01 d6 add %rdx,%rsi + 430452: 4c 8d 1d 57 2f 07 00 lea 0x72f57(%rip),%r11 # 4a33b0 + 430459: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 43045d: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 430461: ff e2 jmpq *%rdx + 430463: 0f 0b ud2 + 430465: 90 nop + 430466: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43046d: 00 00 00 + 430470: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 + 430477: 48 39 ca cmp %rcx,%rdx + 43047a: 0f 28 4e fb movaps -0x5(%rsi),%xmm1 + 43047e: 72 07 jb 430487 <__memmove_ssse3+0xb37> + 430480: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 + 430487: 48 8d 52 c0 lea -0x40(%rdx),%rdx + 43048b: 41 ff e1 jmpq *%r9 + 43048e: 0f 0b ud2 + 430490: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) + 430497: 0f 28 56 eb movaps -0x15(%rsi),%xmm2 + 43049b: 48 83 ea 40 sub $0x40,%rdx + 43049f: 0f 28 5e db movaps -0x25(%rsi),%xmm3 + 4304a3: 0f 28 66 cb movaps -0x35(%rsi),%xmm4 + 4304a7: 0f 28 6e bb movaps -0x45(%rsi),%xmm5 + 4304ab: 48 8d 76 c0 lea -0x40(%rsi),%rsi + 4304af: 66 0f 3a 0f ca 05 palignr $0x5,%xmm2,%xmm1 + 4304b5: 66 0f 3a 0f d3 05 palignr $0x5,%xmm3,%xmm2 + 4304bb: 66 0f 3a 0f dc 05 palignr $0x5,%xmm4,%xmm3 + 4304c1: 66 0f 3a 0f e5 05 palignr $0x5,%xmm5,%xmm4 + 4304c7: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 4304cb: 0f 28 cd movaps %xmm5,%xmm1 + 4304ce: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 4304d2: 48 8d 7f c0 lea -0x40(%rdi),%rdi + 4304d6: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) + 4304da: 72 08 jb 4304e4 <__memmove_ssse3+0xb94> + 4304dc: 0f 29 27 movaps %xmm4,(%rdi) + 4304df: 41 ff e1 jmpq *%r9 + 4304e2: 0f 0b ud2 + 4304e4: 0f 29 27 movaps %xmm4,(%rdi) + 4304e7: 48 8d 52 40 lea 0x40(%rdx),%rdx + 4304eb: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 4304f0: 4c 8d 1d b9 2e 07 00 lea 0x72eb9(%rip),%r11 # 4a33b0 + 4304f7: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 4304fb: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 4304ff: ff e2 jmpq *%rdx + 430501: 0f 0b ud2 + 430503: 0f 1f 00 nopl (%rax) + 430506: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43050d: 00 00 00 + 430510: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 + 430517: 48 39 ca cmp %rcx,%rdx + 43051a: 0f 28 4e fa movaps -0x6(%rsi),%xmm1 + 43051e: 72 07 jb 430527 <__memmove_ssse3+0xbd7> + 430520: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 + 430527: 48 8d 52 c0 lea -0x40(%rdx),%rdx + 43052b: 41 ff e1 jmpq *%r9 + 43052e: 0f 0b ud2 + 430530: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) + 430537: 48 83 ea 40 sub $0x40,%rdx + 43053b: 0f 28 56 0a movaps 0xa(%rsi),%xmm2 + 43053f: 0f 28 5e 1a movaps 0x1a(%rsi),%xmm3 + 430543: 0f 28 66 2a movaps 0x2a(%rsi),%xmm4 + 430547: 0f 28 6e 3a movaps 0x3a(%rsi),%xmm5 + 43054b: 66 0f 6f f5 movdqa %xmm5,%xmm6 + 43054f: 66 0f 3a 0f ec 06 palignr $0x6,%xmm4,%xmm5 + 430555: 48 8d 76 40 lea 0x40(%rsi),%rsi + 430559: 66 0f 3a 0f e3 06 palignr $0x6,%xmm3,%xmm4 + 43055f: 66 0f 3a 0f da 06 palignr $0x6,%xmm2,%xmm3 + 430565: 48 8d 7f 40 lea 0x40(%rdi),%rdi + 430569: 66 0f 3a 0f d1 06 palignr $0x6,%xmm1,%xmm2 + 43056f: 66 0f 6f ce movdqa %xmm6,%xmm1 + 430573: 66 0f 7f 57 c0 movdqa %xmm2,-0x40(%rdi) + 430578: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 43057c: 72 0d jb 43058b <__memmove_ssse3+0xc3b> + 43057e: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) + 430582: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) + 430586: 41 ff e1 jmpq *%r9 + 430589: 0f 0b ud2 + 43058b: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) + 43058f: 48 8d 52 40 lea 0x40(%rdx),%rdx + 430593: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) + 430597: 48 01 d7 add %rdx,%rdi + 43059a: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 43059f: 48 01 d6 add %rdx,%rsi + 4305a2: 4c 8d 1d 07 2e 07 00 lea 0x72e07(%rip),%r11 # 4a33b0 + 4305a9: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 4305ad: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 4305b1: ff e2 jmpq *%rdx + 4305b3: 0f 0b ud2 + 4305b5: 90 nop + 4305b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4305bd: 00 00 00 + 4305c0: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 + 4305c7: 48 39 ca cmp %rcx,%rdx + 4305ca: 0f 28 4e fa movaps -0x6(%rsi),%xmm1 + 4305ce: 72 07 jb 4305d7 <__memmove_ssse3+0xc87> + 4305d0: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 + 4305d7: 48 8d 52 c0 lea -0x40(%rdx),%rdx + 4305db: 41 ff e1 jmpq *%r9 + 4305de: 0f 0b ud2 + 4305e0: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) + 4305e7: 0f 28 56 ea movaps -0x16(%rsi),%xmm2 + 4305eb: 48 83 ea 40 sub $0x40,%rdx + 4305ef: 0f 28 5e da movaps -0x26(%rsi),%xmm3 + 4305f3: 0f 28 66 ca movaps -0x36(%rsi),%xmm4 + 4305f7: 0f 28 6e ba movaps -0x46(%rsi),%xmm5 + 4305fb: 48 8d 76 c0 lea -0x40(%rsi),%rsi + 4305ff: 66 0f 3a 0f ca 06 palignr $0x6,%xmm2,%xmm1 + 430605: 66 0f 3a 0f d3 06 palignr $0x6,%xmm3,%xmm2 + 43060b: 66 0f 3a 0f dc 06 palignr $0x6,%xmm4,%xmm3 + 430611: 66 0f 3a 0f e5 06 palignr $0x6,%xmm5,%xmm4 + 430617: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 43061b: 0f 28 cd movaps %xmm5,%xmm1 + 43061e: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 430622: 48 8d 7f c0 lea -0x40(%rdi),%rdi + 430626: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) + 43062a: 72 08 jb 430634 <__memmove_ssse3+0xce4> + 43062c: 0f 29 27 movaps %xmm4,(%rdi) + 43062f: 41 ff e1 jmpq *%r9 + 430632: 0f 0b ud2 + 430634: 0f 29 27 movaps %xmm4,(%rdi) + 430637: 48 8d 52 40 lea 0x40(%rdx),%rdx + 43063b: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 430640: 4c 8d 1d 69 2d 07 00 lea 0x72d69(%rip),%r11 # 4a33b0 + 430647: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 43064b: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 43064f: ff e2 jmpq *%rdx + 430651: 0f 0b ud2 + 430653: 0f 1f 00 nopl (%rax) + 430656: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43065d: 00 00 00 + 430660: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 + 430667: 48 39 ca cmp %rcx,%rdx + 43066a: 0f 28 4e f9 movaps -0x7(%rsi),%xmm1 + 43066e: 72 07 jb 430677 <__memmove_ssse3+0xd27> + 430670: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 + 430677: 48 8d 52 c0 lea -0x40(%rdx),%rdx + 43067b: 41 ff e1 jmpq *%r9 + 43067e: 0f 0b ud2 + 430680: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) + 430687: 48 83 ea 40 sub $0x40,%rdx + 43068b: 0f 28 56 09 movaps 0x9(%rsi),%xmm2 + 43068f: 0f 28 5e 19 movaps 0x19(%rsi),%xmm3 + 430693: 0f 28 66 29 movaps 0x29(%rsi),%xmm4 + 430697: 0f 28 6e 39 movaps 0x39(%rsi),%xmm5 + 43069b: 66 0f 6f f5 movdqa %xmm5,%xmm6 + 43069f: 66 0f 3a 0f ec 07 palignr $0x7,%xmm4,%xmm5 + 4306a5: 48 8d 76 40 lea 0x40(%rsi),%rsi + 4306a9: 66 0f 3a 0f e3 07 palignr $0x7,%xmm3,%xmm4 + 4306af: 66 0f 3a 0f da 07 palignr $0x7,%xmm2,%xmm3 + 4306b5: 48 8d 7f 40 lea 0x40(%rdi),%rdi + 4306b9: 66 0f 3a 0f d1 07 palignr $0x7,%xmm1,%xmm2 + 4306bf: 66 0f 6f ce movdqa %xmm6,%xmm1 + 4306c3: 66 0f 7f 57 c0 movdqa %xmm2,-0x40(%rdi) + 4306c8: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 4306cc: 72 0d jb 4306db <__memmove_ssse3+0xd8b> + 4306ce: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) + 4306d2: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) + 4306d6: 41 ff e1 jmpq *%r9 + 4306d9: 0f 0b ud2 + 4306db: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) + 4306df: 48 8d 52 40 lea 0x40(%rdx),%rdx + 4306e3: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) + 4306e7: 48 01 d7 add %rdx,%rdi + 4306ea: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 4306ef: 48 01 d6 add %rdx,%rsi + 4306f2: 4c 8d 1d b7 2c 07 00 lea 0x72cb7(%rip),%r11 # 4a33b0 + 4306f9: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 4306fd: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 430701: ff e2 jmpq *%rdx + 430703: 0f 0b ud2 + 430705: 90 nop + 430706: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43070d: 00 00 00 + 430710: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 + 430717: 48 39 ca cmp %rcx,%rdx + 43071a: 0f 28 4e f9 movaps -0x7(%rsi),%xmm1 + 43071e: 72 07 jb 430727 <__memmove_ssse3+0xdd7> + 430720: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 + 430727: 48 8d 52 c0 lea -0x40(%rdx),%rdx + 43072b: 41 ff e1 jmpq *%r9 + 43072e: 0f 0b ud2 + 430730: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) + 430737: 0f 28 56 e9 movaps -0x17(%rsi),%xmm2 + 43073b: 48 83 ea 40 sub $0x40,%rdx + 43073f: 0f 28 5e d9 movaps -0x27(%rsi),%xmm3 + 430743: 0f 28 66 c9 movaps -0x37(%rsi),%xmm4 + 430747: 0f 28 6e b9 movaps -0x47(%rsi),%xmm5 + 43074b: 48 8d 76 c0 lea -0x40(%rsi),%rsi + 43074f: 66 0f 3a 0f ca 07 palignr $0x7,%xmm2,%xmm1 + 430755: 66 0f 3a 0f d3 07 palignr $0x7,%xmm3,%xmm2 + 43075b: 66 0f 3a 0f dc 07 palignr $0x7,%xmm4,%xmm3 + 430761: 66 0f 3a 0f e5 07 palignr $0x7,%xmm5,%xmm4 + 430767: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 43076b: 0f 28 cd movaps %xmm5,%xmm1 + 43076e: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 430772: 48 8d 7f c0 lea -0x40(%rdi),%rdi + 430776: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) + 43077a: 72 08 jb 430784 <__memmove_ssse3+0xe34> + 43077c: 0f 29 27 movaps %xmm4,(%rdi) + 43077f: 41 ff e1 jmpq *%r9 + 430782: 0f 0b ud2 + 430784: 0f 29 27 movaps %xmm4,(%rdi) + 430787: 48 8d 52 40 lea 0x40(%rdx),%rdx + 43078b: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 430790: 4c 8d 1d 19 2c 07 00 lea 0x72c19(%rip),%r11 # 4a33b0 + 430797: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 43079b: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 43079f: ff e2 jmpq *%rdx + 4307a1: 0f 0b ud2 + 4307a3: 0f 1f 00 nopl (%rax) + 4307a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4307ad: 00 00 00 + 4307b0: 4d 8d 89 25 00 00 00 lea 0x25(%r9),%r9 + 4307b7: 48 39 ca cmp %rcx,%rdx + 4307ba: 0f 28 4e f8 movaps -0x8(%rsi),%xmm1 + 4307be: 72 07 jb 4307c7 <__memmove_ssse3+0xe77> + 4307c0: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 + 4307c7: 48 8d 52 c0 lea -0x40(%rdx),%rdx + 4307cb: 41 ff e1 jmpq *%r9 + 4307ce: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) + 4307d5: 48 83 ea 40 sub $0x40,%rdx + 4307d9: 0f 28 56 08 movaps 0x8(%rsi),%xmm2 + 4307dd: 0f 28 5e 18 movaps 0x18(%rsi),%xmm3 + 4307e1: 0f 28 66 28 movaps 0x28(%rsi),%xmm4 + 4307e5: 0f 28 6e 38 movaps 0x38(%rsi),%xmm5 + 4307e9: 66 0f 6f f5 movdqa %xmm5,%xmm6 + 4307ed: 66 0f 3a 0f ec 08 palignr $0x8,%xmm4,%xmm5 + 4307f3: 48 8d 76 40 lea 0x40(%rsi),%rsi + 4307f7: 66 0f 3a 0f e3 08 palignr $0x8,%xmm3,%xmm4 + 4307fd: 66 0f 3a 0f da 08 palignr $0x8,%xmm2,%xmm3 + 430803: 48 8d 7f 40 lea 0x40(%rdi),%rdi + 430807: 66 0f 3a 0f d1 08 palignr $0x8,%xmm1,%xmm2 + 43080d: 66 0f 6f ce movdqa %xmm6,%xmm1 + 430811: 66 0f 7f 57 c0 movdqa %xmm2,-0x40(%rdi) + 430816: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 43081a: 72 14 jb 430830 <__memmove_ssse3+0xee0> + 43081c: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) + 430820: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) + 430824: 41 ff e1 jmpq *%r9 + 430827: 0f 0b ud2 + 430829: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 430830: 48 8d 52 40 lea 0x40(%rdx),%rdx + 430834: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) + 430838: 48 01 d6 add %rdx,%rsi + 43083b: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) + 43083f: 48 01 d7 add %rdx,%rdi + 430842: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 430847: 4c 8d 1d 62 2b 07 00 lea 0x72b62(%rip),%r11 # 4a33b0 + 43084e: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 430852: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 430856: ff e2 jmpq *%rdx + 430858: 0f 0b ud2 + 43085a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 430860: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 + 430867: 48 39 ca cmp %rcx,%rdx + 43086a: 0f 28 4e f8 movaps -0x8(%rsi),%xmm1 + 43086e: 72 07 jb 430877 <__memmove_ssse3+0xf27> + 430870: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 + 430877: 48 8d 52 c0 lea -0x40(%rdx),%rdx + 43087b: 41 ff e1 jmpq *%r9 + 43087e: 0f 0b ud2 + 430880: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) + 430887: 0f 28 56 e8 movaps -0x18(%rsi),%xmm2 + 43088b: 48 83 ea 40 sub $0x40,%rdx + 43088f: 0f 28 5e d8 movaps -0x28(%rsi),%xmm3 + 430893: 0f 28 66 c8 movaps -0x38(%rsi),%xmm4 + 430897: 0f 28 6e b8 movaps -0x48(%rsi),%xmm5 + 43089b: 48 8d 76 c0 lea -0x40(%rsi),%rsi + 43089f: 66 0f 3a 0f ca 08 palignr $0x8,%xmm2,%xmm1 + 4308a5: 66 0f 3a 0f d3 08 palignr $0x8,%xmm3,%xmm2 + 4308ab: 66 0f 3a 0f dc 08 palignr $0x8,%xmm4,%xmm3 + 4308b1: 66 0f 3a 0f e5 08 palignr $0x8,%xmm5,%xmm4 + 4308b7: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 4308bb: 0f 28 cd movaps %xmm5,%xmm1 + 4308be: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 4308c2: 48 8d 7f c0 lea -0x40(%rdi),%rdi + 4308c6: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) + 4308ca: 72 08 jb 4308d4 <__memmove_ssse3+0xf84> + 4308cc: 0f 29 27 movaps %xmm4,(%rdi) + 4308cf: 41 ff e1 jmpq *%r9 + 4308d2: 0f 0b ud2 + 4308d4: 0f 29 27 movaps %xmm4,(%rdi) + 4308d7: 48 8d 52 40 lea 0x40(%rdx),%rdx + 4308db: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 4308e0: 4c 8d 1d c9 2a 07 00 lea 0x72ac9(%rip),%r11 # 4a33b0 + 4308e7: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 4308eb: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 4308ef: ff e2 jmpq *%rdx + 4308f1: 0f 0b ud2 + 4308f3: 0f 1f 00 nopl (%rax) + 4308f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4308fd: 00 00 00 + 430900: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 + 430907: 48 39 ca cmp %rcx,%rdx + 43090a: 0f 28 4e f7 movaps -0x9(%rsi),%xmm1 + 43090e: 72 07 jb 430917 <__memmove_ssse3+0xfc7> + 430910: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 + 430917: 48 8d 52 c0 lea -0x40(%rdx),%rdx + 43091b: 41 ff e1 jmpq *%r9 + 43091e: 0f 0b ud2 + 430920: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) + 430927: 48 83 ea 40 sub $0x40,%rdx + 43092b: 0f 28 56 07 movaps 0x7(%rsi),%xmm2 + 43092f: 0f 28 5e 17 movaps 0x17(%rsi),%xmm3 + 430933: 0f 28 66 27 movaps 0x27(%rsi),%xmm4 + 430937: 0f 28 6e 37 movaps 0x37(%rsi),%xmm5 + 43093b: 66 0f 6f f5 movdqa %xmm5,%xmm6 + 43093f: 66 0f 3a 0f ec 09 palignr $0x9,%xmm4,%xmm5 + 430945: 48 8d 76 40 lea 0x40(%rsi),%rsi + 430949: 66 0f 3a 0f e3 09 palignr $0x9,%xmm3,%xmm4 + 43094f: 66 0f 3a 0f da 09 palignr $0x9,%xmm2,%xmm3 + 430955: 48 8d 7f 40 lea 0x40(%rdi),%rdi + 430959: 66 0f 3a 0f d1 09 palignr $0x9,%xmm1,%xmm2 + 43095f: 66 0f 6f ce movdqa %xmm6,%xmm1 + 430963: 66 0f 7f 57 c0 movdqa %xmm2,-0x40(%rdi) + 430968: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 43096c: 72 0d jb 43097b <__memmove_ssse3+0x102b> + 43096e: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) + 430972: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) + 430976: 41 ff e1 jmpq *%r9 + 430979: 0f 0b ud2 + 43097b: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) + 43097f: 48 8d 52 40 lea 0x40(%rdx),%rdx + 430983: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) + 430987: 48 01 d7 add %rdx,%rdi + 43098a: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 43098f: 48 01 d6 add %rdx,%rsi + 430992: 4c 8d 1d 17 2a 07 00 lea 0x72a17(%rip),%r11 # 4a33b0 + 430999: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 43099d: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 4309a1: ff e2 jmpq *%rdx + 4309a3: 0f 0b ud2 + 4309a5: 90 nop + 4309a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4309ad: 00 00 00 + 4309b0: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 + 4309b7: 48 39 ca cmp %rcx,%rdx + 4309ba: 0f 28 4e f7 movaps -0x9(%rsi),%xmm1 + 4309be: 72 07 jb 4309c7 <__memmove_ssse3+0x1077> + 4309c0: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 + 4309c7: 48 8d 52 c0 lea -0x40(%rdx),%rdx + 4309cb: 41 ff e1 jmpq *%r9 + 4309ce: 0f 0b ud2 + 4309d0: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) + 4309d7: 0f 28 56 e7 movaps -0x19(%rsi),%xmm2 + 4309db: 48 83 ea 40 sub $0x40,%rdx + 4309df: 0f 28 5e d7 movaps -0x29(%rsi),%xmm3 + 4309e3: 0f 28 66 c7 movaps -0x39(%rsi),%xmm4 + 4309e7: 0f 28 6e b7 movaps -0x49(%rsi),%xmm5 + 4309eb: 48 8d 76 c0 lea -0x40(%rsi),%rsi + 4309ef: 66 0f 3a 0f ca 09 palignr $0x9,%xmm2,%xmm1 + 4309f5: 66 0f 3a 0f d3 09 palignr $0x9,%xmm3,%xmm2 + 4309fb: 66 0f 3a 0f dc 09 palignr $0x9,%xmm4,%xmm3 + 430a01: 66 0f 3a 0f e5 09 palignr $0x9,%xmm5,%xmm4 + 430a07: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 430a0b: 0f 28 cd movaps %xmm5,%xmm1 + 430a0e: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 430a12: 48 8d 7f c0 lea -0x40(%rdi),%rdi + 430a16: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) + 430a1a: 72 08 jb 430a24 <__memmove_ssse3+0x10d4> + 430a1c: 0f 29 27 movaps %xmm4,(%rdi) + 430a1f: 41 ff e1 jmpq *%r9 + 430a22: 0f 0b ud2 + 430a24: 0f 29 27 movaps %xmm4,(%rdi) + 430a27: 48 8d 52 40 lea 0x40(%rdx),%rdx + 430a2b: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 430a30: 4c 8d 1d 79 29 07 00 lea 0x72979(%rip),%r11 # 4a33b0 + 430a37: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 430a3b: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 430a3f: ff e2 jmpq *%rdx + 430a41: 0f 0b ud2 + 430a43: 0f 1f 00 nopl (%rax) + 430a46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 430a4d: 00 00 00 + 430a50: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 + 430a57: 48 39 ca cmp %rcx,%rdx + 430a5a: 0f 28 4e f6 movaps -0xa(%rsi),%xmm1 + 430a5e: 72 07 jb 430a67 <__memmove_ssse3+0x1117> + 430a60: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 + 430a67: 48 8d 52 c0 lea -0x40(%rdx),%rdx + 430a6b: 41 ff e1 jmpq *%r9 + 430a6e: 0f 0b ud2 + 430a70: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) + 430a77: 48 83 ea 40 sub $0x40,%rdx + 430a7b: 0f 28 56 06 movaps 0x6(%rsi),%xmm2 + 430a7f: 0f 28 5e 16 movaps 0x16(%rsi),%xmm3 + 430a83: 0f 28 66 26 movaps 0x26(%rsi),%xmm4 + 430a87: 0f 28 6e 36 movaps 0x36(%rsi),%xmm5 + 430a8b: 66 0f 6f f5 movdqa %xmm5,%xmm6 + 430a8f: 66 0f 3a 0f ec 0a palignr $0xa,%xmm4,%xmm5 + 430a95: 48 8d 76 40 lea 0x40(%rsi),%rsi + 430a99: 66 0f 3a 0f e3 0a palignr $0xa,%xmm3,%xmm4 + 430a9f: 66 0f 3a 0f da 0a palignr $0xa,%xmm2,%xmm3 + 430aa5: 48 8d 7f 40 lea 0x40(%rdi),%rdi + 430aa9: 66 0f 3a 0f d1 0a palignr $0xa,%xmm1,%xmm2 + 430aaf: 66 0f 6f ce movdqa %xmm6,%xmm1 + 430ab3: 66 0f 7f 57 c0 movdqa %xmm2,-0x40(%rdi) + 430ab8: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 430abc: 72 0d jb 430acb <__memmove_ssse3+0x117b> + 430abe: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) + 430ac2: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) + 430ac6: 41 ff e1 jmpq *%r9 + 430ac9: 0f 0b ud2 + 430acb: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) + 430acf: 48 8d 52 40 lea 0x40(%rdx),%rdx + 430ad3: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) + 430ad7: 48 01 d7 add %rdx,%rdi + 430ada: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 430adf: 48 01 d6 add %rdx,%rsi + 430ae2: 4c 8d 1d c7 28 07 00 lea 0x728c7(%rip),%r11 # 4a33b0 + 430ae9: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 430aed: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 430af1: ff e2 jmpq *%rdx + 430af3: 0f 0b ud2 + 430af5: 90 nop + 430af6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 430afd: 00 00 00 + 430b00: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 + 430b07: 48 39 ca cmp %rcx,%rdx + 430b0a: 0f 28 4e f6 movaps -0xa(%rsi),%xmm1 + 430b0e: 72 07 jb 430b17 <__memmove_ssse3+0x11c7> + 430b10: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 + 430b17: 48 8d 52 c0 lea -0x40(%rdx),%rdx + 430b1b: 41 ff e1 jmpq *%r9 + 430b1e: 0f 0b ud2 + 430b20: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) + 430b27: 0f 28 56 e6 movaps -0x1a(%rsi),%xmm2 + 430b2b: 48 83 ea 40 sub $0x40,%rdx + 430b2f: 0f 28 5e d6 movaps -0x2a(%rsi),%xmm3 + 430b33: 0f 28 66 c6 movaps -0x3a(%rsi),%xmm4 + 430b37: 0f 28 6e b6 movaps -0x4a(%rsi),%xmm5 + 430b3b: 48 8d 76 c0 lea -0x40(%rsi),%rsi + 430b3f: 66 0f 3a 0f ca 0a palignr $0xa,%xmm2,%xmm1 + 430b45: 66 0f 3a 0f d3 0a palignr $0xa,%xmm3,%xmm2 + 430b4b: 66 0f 3a 0f dc 0a palignr $0xa,%xmm4,%xmm3 + 430b51: 66 0f 3a 0f e5 0a palignr $0xa,%xmm5,%xmm4 + 430b57: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 430b5b: 0f 28 cd movaps %xmm5,%xmm1 + 430b5e: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 430b62: 48 8d 7f c0 lea -0x40(%rdi),%rdi + 430b66: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) + 430b6a: 72 08 jb 430b74 <__memmove_ssse3+0x1224> + 430b6c: 0f 29 27 movaps %xmm4,(%rdi) + 430b6f: 41 ff e1 jmpq *%r9 + 430b72: 0f 0b ud2 + 430b74: 0f 29 27 movaps %xmm4,(%rdi) + 430b77: 48 8d 52 40 lea 0x40(%rdx),%rdx + 430b7b: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 430b80: 4c 8d 1d 29 28 07 00 lea 0x72829(%rip),%r11 # 4a33b0 + 430b87: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 430b8b: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 430b8f: ff e2 jmpq *%rdx + 430b91: 0f 0b ud2 + 430b93: 0f 1f 00 nopl (%rax) + 430b96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 430b9d: 00 00 00 + 430ba0: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 + 430ba7: 48 39 ca cmp %rcx,%rdx + 430baa: 0f 28 4e f5 movaps -0xb(%rsi),%xmm1 + 430bae: 72 07 jb 430bb7 <__memmove_ssse3+0x1267> + 430bb0: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 + 430bb7: 48 8d 52 c0 lea -0x40(%rdx),%rdx + 430bbb: 41 ff e1 jmpq *%r9 + 430bbe: 0f 0b ud2 + 430bc0: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) + 430bc7: 48 83 ea 40 sub $0x40,%rdx + 430bcb: 0f 28 56 05 movaps 0x5(%rsi),%xmm2 + 430bcf: 0f 28 5e 15 movaps 0x15(%rsi),%xmm3 + 430bd3: 0f 28 66 25 movaps 0x25(%rsi),%xmm4 + 430bd7: 0f 28 6e 35 movaps 0x35(%rsi),%xmm5 + 430bdb: 66 0f 6f f5 movdqa %xmm5,%xmm6 + 430bdf: 66 0f 3a 0f ec 0b palignr $0xb,%xmm4,%xmm5 + 430be5: 48 8d 76 40 lea 0x40(%rsi),%rsi + 430be9: 66 0f 3a 0f e3 0b palignr $0xb,%xmm3,%xmm4 + 430bef: 66 0f 3a 0f da 0b palignr $0xb,%xmm2,%xmm3 + 430bf5: 48 8d 7f 40 lea 0x40(%rdi),%rdi + 430bf9: 66 0f 3a 0f d1 0b palignr $0xb,%xmm1,%xmm2 + 430bff: 66 0f 6f ce movdqa %xmm6,%xmm1 + 430c03: 66 0f 7f 57 c0 movdqa %xmm2,-0x40(%rdi) + 430c08: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 430c0c: 72 0d jb 430c1b <__memmove_ssse3+0x12cb> + 430c0e: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) + 430c12: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) + 430c16: 41 ff e1 jmpq *%r9 + 430c19: 0f 0b ud2 + 430c1b: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) + 430c1f: 48 8d 52 40 lea 0x40(%rdx),%rdx + 430c23: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) + 430c27: 48 01 d7 add %rdx,%rdi + 430c2a: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 430c2f: 48 01 d6 add %rdx,%rsi + 430c32: 4c 8d 1d 77 27 07 00 lea 0x72777(%rip),%r11 # 4a33b0 + 430c39: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 430c3d: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 430c41: ff e2 jmpq *%rdx + 430c43: 0f 0b ud2 + 430c45: 90 nop + 430c46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 430c4d: 00 00 00 + 430c50: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 + 430c57: 48 39 ca cmp %rcx,%rdx + 430c5a: 0f 28 4e f5 movaps -0xb(%rsi),%xmm1 + 430c5e: 72 07 jb 430c67 <__memmove_ssse3+0x1317> + 430c60: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 + 430c67: 48 8d 52 c0 lea -0x40(%rdx),%rdx + 430c6b: 41 ff e1 jmpq *%r9 + 430c6e: 0f 0b ud2 + 430c70: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) + 430c77: 0f 28 56 e5 movaps -0x1b(%rsi),%xmm2 + 430c7b: 48 83 ea 40 sub $0x40,%rdx + 430c7f: 0f 28 5e d5 movaps -0x2b(%rsi),%xmm3 + 430c83: 0f 28 66 c5 movaps -0x3b(%rsi),%xmm4 + 430c87: 0f 28 6e b5 movaps -0x4b(%rsi),%xmm5 + 430c8b: 48 8d 76 c0 lea -0x40(%rsi),%rsi + 430c8f: 66 0f 3a 0f ca 0b palignr $0xb,%xmm2,%xmm1 + 430c95: 66 0f 3a 0f d3 0b palignr $0xb,%xmm3,%xmm2 + 430c9b: 66 0f 3a 0f dc 0b palignr $0xb,%xmm4,%xmm3 + 430ca1: 66 0f 3a 0f e5 0b palignr $0xb,%xmm5,%xmm4 + 430ca7: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 430cab: 0f 28 cd movaps %xmm5,%xmm1 + 430cae: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 430cb2: 48 8d 7f c0 lea -0x40(%rdi),%rdi + 430cb6: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) + 430cba: 72 08 jb 430cc4 <__memmove_ssse3+0x1374> + 430cbc: 0f 29 27 movaps %xmm4,(%rdi) + 430cbf: 41 ff e1 jmpq *%r9 + 430cc2: 0f 0b ud2 + 430cc4: 0f 29 27 movaps %xmm4,(%rdi) + 430cc7: 48 8d 52 40 lea 0x40(%rdx),%rdx + 430ccb: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 430cd0: 4c 8d 1d d9 26 07 00 lea 0x726d9(%rip),%r11 # 4a33b0 + 430cd7: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 430cdb: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 430cdf: ff e2 jmpq *%rdx + 430ce1: 0f 0b ud2 + 430ce3: 0f 1f 00 nopl (%rax) + 430ce6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 430ced: 00 00 00 + 430cf0: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 + 430cf7: 48 39 ca cmp %rcx,%rdx + 430cfa: 0f 28 4e f4 movaps -0xc(%rsi),%xmm1 + 430cfe: 72 07 jb 430d07 <__memmove_ssse3+0x13b7> + 430d00: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 + 430d07: 48 8d 52 c0 lea -0x40(%rdx),%rdx + 430d0b: 41 ff e1 jmpq *%r9 + 430d0e: 0f 0b ud2 + 430d10: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) + 430d17: 48 83 ea 40 sub $0x40,%rdx + 430d1b: 0f 28 56 04 movaps 0x4(%rsi),%xmm2 + 430d1f: 0f 28 5e 14 movaps 0x14(%rsi),%xmm3 + 430d23: 0f 28 66 24 movaps 0x24(%rsi),%xmm4 + 430d27: 0f 28 6e 34 movaps 0x34(%rsi),%xmm5 + 430d2b: 66 0f 6f f5 movdqa %xmm5,%xmm6 + 430d2f: 66 0f 3a 0f ec 0c palignr $0xc,%xmm4,%xmm5 + 430d35: 48 8d 76 40 lea 0x40(%rsi),%rsi + 430d39: 66 0f 3a 0f e3 0c palignr $0xc,%xmm3,%xmm4 + 430d3f: 66 0f 3a 0f da 0c palignr $0xc,%xmm2,%xmm3 + 430d45: 48 8d 7f 40 lea 0x40(%rdi),%rdi + 430d49: 66 0f 3a 0f d1 0c palignr $0xc,%xmm1,%xmm2 + 430d4f: 66 0f 6f ce movdqa %xmm6,%xmm1 + 430d53: 66 0f 7f 57 c0 movdqa %xmm2,-0x40(%rdi) + 430d58: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 430d5c: 72 0d jb 430d6b <__memmove_ssse3+0x141b> + 430d5e: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) + 430d62: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) + 430d66: 41 ff e1 jmpq *%r9 + 430d69: 0f 0b ud2 + 430d6b: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) + 430d6f: 48 8d 52 40 lea 0x40(%rdx),%rdx + 430d73: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) + 430d77: 48 01 d7 add %rdx,%rdi + 430d7a: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 430d7f: 48 01 d6 add %rdx,%rsi + 430d82: 4c 8d 1d 27 26 07 00 lea 0x72627(%rip),%r11 # 4a33b0 + 430d89: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 430d8d: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 430d91: ff e2 jmpq *%rdx + 430d93: 0f 0b ud2 + 430d95: 90 nop + 430d96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 430d9d: 00 00 00 + 430da0: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 + 430da7: 48 39 ca cmp %rcx,%rdx + 430daa: 0f 28 4e f4 movaps -0xc(%rsi),%xmm1 + 430dae: 72 07 jb 430db7 <__memmove_ssse3+0x1467> + 430db0: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 + 430db7: 48 8d 52 c0 lea -0x40(%rdx),%rdx + 430dbb: 41 ff e1 jmpq *%r9 + 430dbe: 0f 0b ud2 + 430dc0: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) + 430dc7: 0f 28 56 e4 movaps -0x1c(%rsi),%xmm2 + 430dcb: 48 83 ea 40 sub $0x40,%rdx + 430dcf: 0f 28 5e d4 movaps -0x2c(%rsi),%xmm3 + 430dd3: 0f 28 66 c4 movaps -0x3c(%rsi),%xmm4 + 430dd7: 0f 28 6e b4 movaps -0x4c(%rsi),%xmm5 + 430ddb: 48 8d 76 c0 lea -0x40(%rsi),%rsi + 430ddf: 66 0f 3a 0f ca 0c palignr $0xc,%xmm2,%xmm1 + 430de5: 66 0f 3a 0f d3 0c palignr $0xc,%xmm3,%xmm2 + 430deb: 66 0f 3a 0f dc 0c palignr $0xc,%xmm4,%xmm3 + 430df1: 66 0f 3a 0f e5 0c palignr $0xc,%xmm5,%xmm4 + 430df7: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 430dfb: 0f 28 cd movaps %xmm5,%xmm1 + 430dfe: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 430e02: 48 8d 7f c0 lea -0x40(%rdi),%rdi + 430e06: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) + 430e0a: 72 08 jb 430e14 <__memmove_ssse3+0x14c4> + 430e0c: 0f 29 27 movaps %xmm4,(%rdi) + 430e0f: 41 ff e1 jmpq *%r9 + 430e12: 0f 0b ud2 + 430e14: 0f 29 27 movaps %xmm4,(%rdi) + 430e17: 48 8d 52 40 lea 0x40(%rdx),%rdx + 430e1b: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 430e20: 4c 8d 1d 89 25 07 00 lea 0x72589(%rip),%r11 # 4a33b0 + 430e27: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 430e2b: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 430e2f: ff e2 jmpq *%rdx + 430e31: 0f 0b ud2 + 430e33: 0f 1f 00 nopl (%rax) + 430e36: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 430e3d: 00 00 00 + 430e40: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 + 430e47: 48 39 ca cmp %rcx,%rdx + 430e4a: 0f 28 4e f3 movaps -0xd(%rsi),%xmm1 + 430e4e: 72 07 jb 430e57 <__memmove_ssse3+0x1507> + 430e50: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 + 430e57: 48 8d 52 c0 lea -0x40(%rdx),%rdx + 430e5b: 41 ff e1 jmpq *%r9 + 430e5e: 0f 0b ud2 + 430e60: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) + 430e67: 48 83 ea 40 sub $0x40,%rdx + 430e6b: 0f 28 56 03 movaps 0x3(%rsi),%xmm2 + 430e6f: 0f 28 5e 13 movaps 0x13(%rsi),%xmm3 + 430e73: 0f 28 66 23 movaps 0x23(%rsi),%xmm4 + 430e77: 0f 28 6e 33 movaps 0x33(%rsi),%xmm5 + 430e7b: 66 0f 6f f5 movdqa %xmm5,%xmm6 + 430e7f: 66 0f 3a 0f ec 0d palignr $0xd,%xmm4,%xmm5 + 430e85: 48 8d 76 40 lea 0x40(%rsi),%rsi + 430e89: 66 0f 3a 0f e3 0d palignr $0xd,%xmm3,%xmm4 + 430e8f: 66 0f 3a 0f da 0d palignr $0xd,%xmm2,%xmm3 + 430e95: 48 8d 7f 40 lea 0x40(%rdi),%rdi + 430e99: 66 0f 3a 0f d1 0d palignr $0xd,%xmm1,%xmm2 + 430e9f: 66 0f 6f ce movdqa %xmm6,%xmm1 + 430ea3: 66 0f 7f 57 c0 movdqa %xmm2,-0x40(%rdi) + 430ea8: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 430eac: 72 0d jb 430ebb <__memmove_ssse3+0x156b> + 430eae: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) + 430eb2: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) + 430eb6: 41 ff e1 jmpq *%r9 + 430eb9: 0f 0b ud2 + 430ebb: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) + 430ebf: 48 8d 52 40 lea 0x40(%rdx),%rdx + 430ec3: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) + 430ec7: 48 01 d7 add %rdx,%rdi + 430eca: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 430ecf: 48 01 d6 add %rdx,%rsi + 430ed2: 4c 8d 1d d7 24 07 00 lea 0x724d7(%rip),%r11 # 4a33b0 + 430ed9: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 430edd: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 430ee1: ff e2 jmpq *%rdx + 430ee3: 0f 0b ud2 + 430ee5: 90 nop + 430ee6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 430eed: 00 00 00 + 430ef0: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 + 430ef7: 48 39 ca cmp %rcx,%rdx + 430efa: 0f 28 4e f3 movaps -0xd(%rsi),%xmm1 + 430efe: 72 07 jb 430f07 <__memmove_ssse3+0x15b7> + 430f00: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 + 430f07: 48 8d 52 c0 lea -0x40(%rdx),%rdx + 430f0b: 41 ff e1 jmpq *%r9 + 430f0e: 0f 0b ud2 + 430f10: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) + 430f17: 0f 28 56 e3 movaps -0x1d(%rsi),%xmm2 + 430f1b: 48 83 ea 40 sub $0x40,%rdx + 430f1f: 0f 28 5e d3 movaps -0x2d(%rsi),%xmm3 + 430f23: 0f 28 66 c3 movaps -0x3d(%rsi),%xmm4 + 430f27: 0f 28 6e b3 movaps -0x4d(%rsi),%xmm5 + 430f2b: 48 8d 76 c0 lea -0x40(%rsi),%rsi + 430f2f: 66 0f 3a 0f ca 0d palignr $0xd,%xmm2,%xmm1 + 430f35: 66 0f 3a 0f d3 0d palignr $0xd,%xmm3,%xmm2 + 430f3b: 66 0f 3a 0f dc 0d palignr $0xd,%xmm4,%xmm3 + 430f41: 66 0f 3a 0f e5 0d palignr $0xd,%xmm5,%xmm4 + 430f47: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 430f4b: 0f 28 cd movaps %xmm5,%xmm1 + 430f4e: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 430f52: 48 8d 7f c0 lea -0x40(%rdi),%rdi + 430f56: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) + 430f5a: 72 08 jb 430f64 <__memmove_ssse3+0x1614> + 430f5c: 0f 29 27 movaps %xmm4,(%rdi) + 430f5f: 41 ff e1 jmpq *%r9 + 430f62: 0f 0b ud2 + 430f64: 0f 29 27 movaps %xmm4,(%rdi) + 430f67: 48 8d 52 40 lea 0x40(%rdx),%rdx + 430f6b: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 430f70: 4c 8d 1d 39 24 07 00 lea 0x72439(%rip),%r11 # 4a33b0 + 430f77: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 430f7b: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 430f7f: ff e2 jmpq *%rdx + 430f81: 0f 0b ud2 + 430f83: 0f 1f 00 nopl (%rax) + 430f86: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 430f8d: 00 00 00 + 430f90: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 + 430f97: 48 39 ca cmp %rcx,%rdx + 430f9a: 0f 28 4e f2 movaps -0xe(%rsi),%xmm1 + 430f9e: 72 07 jb 430fa7 <__memmove_ssse3+0x1657> + 430fa0: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 + 430fa7: 48 8d 52 c0 lea -0x40(%rdx),%rdx + 430fab: 41 ff e1 jmpq *%r9 + 430fae: 0f 0b ud2 + 430fb0: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) + 430fb7: 48 83 ea 40 sub $0x40,%rdx + 430fbb: 0f 28 56 02 movaps 0x2(%rsi),%xmm2 + 430fbf: 0f 28 5e 12 movaps 0x12(%rsi),%xmm3 + 430fc3: 0f 28 66 22 movaps 0x22(%rsi),%xmm4 + 430fc7: 0f 28 6e 32 movaps 0x32(%rsi),%xmm5 + 430fcb: 66 0f 6f f5 movdqa %xmm5,%xmm6 + 430fcf: 66 0f 3a 0f ec 0e palignr $0xe,%xmm4,%xmm5 + 430fd5: 48 8d 76 40 lea 0x40(%rsi),%rsi + 430fd9: 66 0f 3a 0f e3 0e palignr $0xe,%xmm3,%xmm4 + 430fdf: 66 0f 3a 0f da 0e palignr $0xe,%xmm2,%xmm3 + 430fe5: 48 8d 7f 40 lea 0x40(%rdi),%rdi + 430fe9: 66 0f 3a 0f d1 0e palignr $0xe,%xmm1,%xmm2 + 430fef: 66 0f 6f ce movdqa %xmm6,%xmm1 + 430ff3: 66 0f 7f 57 c0 movdqa %xmm2,-0x40(%rdi) + 430ff8: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 430ffc: 72 0d jb 43100b <__memmove_ssse3+0x16bb> + 430ffe: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) + 431002: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) + 431006: 41 ff e1 jmpq *%r9 + 431009: 0f 0b ud2 + 43100b: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) + 43100f: 48 8d 52 40 lea 0x40(%rdx),%rdx + 431013: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) + 431017: 48 01 d7 add %rdx,%rdi + 43101a: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 43101f: 48 01 d6 add %rdx,%rsi + 431022: 4c 8d 1d 87 23 07 00 lea 0x72387(%rip),%r11 # 4a33b0 + 431029: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 43102d: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 431031: ff e2 jmpq *%rdx + 431033: 0f 0b ud2 + 431035: 90 nop + 431036: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43103d: 00 00 00 + 431040: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 + 431047: 48 39 ca cmp %rcx,%rdx + 43104a: 0f 28 4e f2 movaps -0xe(%rsi),%xmm1 + 43104e: 72 07 jb 431057 <__memmove_ssse3+0x1707> + 431050: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 + 431057: 48 8d 52 c0 lea -0x40(%rdx),%rdx + 43105b: 41 ff e1 jmpq *%r9 + 43105e: 0f 0b ud2 + 431060: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) + 431067: 0f 28 56 e2 movaps -0x1e(%rsi),%xmm2 + 43106b: 48 83 ea 40 sub $0x40,%rdx + 43106f: 0f 28 5e d2 movaps -0x2e(%rsi),%xmm3 + 431073: 0f 28 66 c2 movaps -0x3e(%rsi),%xmm4 + 431077: 0f 28 6e b2 movaps -0x4e(%rsi),%xmm5 + 43107b: 48 8d 76 c0 lea -0x40(%rsi),%rsi + 43107f: 66 0f 3a 0f ca 0e palignr $0xe,%xmm2,%xmm1 + 431085: 66 0f 3a 0f d3 0e palignr $0xe,%xmm3,%xmm2 + 43108b: 66 0f 3a 0f dc 0e palignr $0xe,%xmm4,%xmm3 + 431091: 66 0f 3a 0f e5 0e palignr $0xe,%xmm5,%xmm4 + 431097: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 43109b: 0f 28 cd movaps %xmm5,%xmm1 + 43109e: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 4310a2: 48 8d 7f c0 lea -0x40(%rdi),%rdi + 4310a6: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) + 4310aa: 72 08 jb 4310b4 <__memmove_ssse3+0x1764> + 4310ac: 0f 29 27 movaps %xmm4,(%rdi) + 4310af: 41 ff e1 jmpq *%r9 + 4310b2: 0f 0b ud2 + 4310b4: 0f 29 27 movaps %xmm4,(%rdi) + 4310b7: 48 8d 52 40 lea 0x40(%rdx),%rdx + 4310bb: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 4310c0: 4c 8d 1d e9 22 07 00 lea 0x722e9(%rip),%r11 # 4a33b0 + 4310c7: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 4310cb: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 4310cf: ff e2 jmpq *%rdx + 4310d1: 0f 0b ud2 + 4310d3: 0f 1f 00 nopl (%rax) + 4310d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4310dd: 00 00 00 + 4310e0: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 + 4310e7: 48 39 ca cmp %rcx,%rdx + 4310ea: 0f 28 4e f1 movaps -0xf(%rsi),%xmm1 + 4310ee: 72 07 jb 4310f7 <__memmove_ssse3+0x17a7> + 4310f0: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 + 4310f7: 48 8d 52 c0 lea -0x40(%rdx),%rdx + 4310fb: 41 ff e1 jmpq *%r9 + 4310fe: 0f 0b ud2 + 431100: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) + 431107: 48 83 ea 40 sub $0x40,%rdx + 43110b: 0f 28 56 01 movaps 0x1(%rsi),%xmm2 + 43110f: 0f 28 5e 11 movaps 0x11(%rsi),%xmm3 + 431113: 0f 28 66 21 movaps 0x21(%rsi),%xmm4 + 431117: 0f 28 6e 31 movaps 0x31(%rsi),%xmm5 + 43111b: 66 0f 6f f5 movdqa %xmm5,%xmm6 + 43111f: 66 0f 3a 0f ec 0f palignr $0xf,%xmm4,%xmm5 + 431125: 48 8d 76 40 lea 0x40(%rsi),%rsi + 431129: 66 0f 3a 0f e3 0f palignr $0xf,%xmm3,%xmm4 + 43112f: 66 0f 3a 0f da 0f palignr $0xf,%xmm2,%xmm3 + 431135: 48 8d 7f 40 lea 0x40(%rdi),%rdi + 431139: 66 0f 3a 0f d1 0f palignr $0xf,%xmm1,%xmm2 + 43113f: 66 0f 6f ce movdqa %xmm6,%xmm1 + 431143: 66 0f 7f 57 c0 movdqa %xmm2,-0x40(%rdi) + 431148: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 43114c: 72 0d jb 43115b <__memmove_ssse3+0x180b> + 43114e: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) + 431152: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) + 431156: 41 ff e1 jmpq *%r9 + 431159: 0f 0b ud2 + 43115b: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) + 43115f: 48 8d 52 40 lea 0x40(%rdx),%rdx + 431163: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) + 431167: 48 01 d7 add %rdx,%rdi + 43116a: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 43116f: 48 01 d6 add %rdx,%rsi + 431172: 4c 8d 1d 37 22 07 00 lea 0x72237(%rip),%r11 # 4a33b0 + 431179: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 43117d: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 431181: ff e2 jmpq *%rdx + 431183: 0f 0b ud2 + 431185: 90 nop + 431186: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43118d: 00 00 00 + 431190: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 + 431197: 48 39 ca cmp %rcx,%rdx + 43119a: 0f 28 4e f1 movaps -0xf(%rsi),%xmm1 + 43119e: 72 07 jb 4311a7 <__memmove_ssse3+0x1857> + 4311a0: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 + 4311a7: 48 8d 52 c0 lea -0x40(%rdx),%rdx + 4311ab: 41 ff e1 jmpq *%r9 + 4311ae: 0f 0b ud2 + 4311b0: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) + 4311b7: 0f 28 56 e1 movaps -0x1f(%rsi),%xmm2 + 4311bb: 48 83 ea 40 sub $0x40,%rdx + 4311bf: 0f 28 5e d1 movaps -0x2f(%rsi),%xmm3 + 4311c3: 0f 28 66 c1 movaps -0x3f(%rsi),%xmm4 + 4311c7: 0f 28 6e b1 movaps -0x4f(%rsi),%xmm5 + 4311cb: 48 8d 76 c0 lea -0x40(%rsi),%rsi + 4311cf: 66 0f 3a 0f ca 0f palignr $0xf,%xmm2,%xmm1 + 4311d5: 66 0f 3a 0f d3 0f palignr $0xf,%xmm3,%xmm2 + 4311db: 66 0f 3a 0f dc 0f palignr $0xf,%xmm4,%xmm3 + 4311e1: 66 0f 3a 0f e5 0f palignr $0xf,%xmm5,%xmm4 + 4311e7: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 4311eb: 0f 28 cd movaps %xmm5,%xmm1 + 4311ee: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 4311f2: 48 8d 7f c0 lea -0x40(%rdi),%rdi + 4311f6: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) + 4311fa: 72 08 jb 431204 <__memmove_ssse3+0x18b4> + 4311fc: 0f 29 27 movaps %xmm4,(%rdi) + 4311ff: 41 ff e1 jmpq *%r9 + 431202: 0f 0b ud2 + 431204: 0f 29 27 movaps %xmm4,(%rdi) + 431207: 48 8d 52 40 lea 0x40(%rdx),%rdx + 43120b: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 431210: 4c 8d 1d 99 21 07 00 lea 0x72199(%rip),%r11 # 4a33b0 + 431217: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 43121b: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 43121f: ff e2 jmpq *%rdx + 431221: 0f 0b ud2 + 431223: 0f 1f 00 nopl (%rax) + 431226: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43122d: 00 00 00 + 431230: f3 0f 6f 46 b8 movdqu -0x48(%rsi),%xmm0 + 431235: f3 0f 6f 4e c8 movdqu -0x38(%rsi),%xmm1 + 43123a: 4c 8b 46 d8 mov -0x28(%rsi),%r8 + 43123e: 4c 8b 4e e0 mov -0x20(%rsi),%r9 + 431242: 4c 8b 56 e8 mov -0x18(%rsi),%r10 + 431246: 4c 8b 5e f0 mov -0x10(%rsi),%r11 + 43124a: 48 8b 4e f8 mov -0x8(%rsi),%rcx + 43124e: f3 0f 7f 47 b8 movdqu %xmm0,-0x48(%rdi) + 431253: f3 0f 7f 4f c8 movdqu %xmm1,-0x38(%rdi) + 431258: 4c 89 47 d8 mov %r8,-0x28(%rdi) + 43125c: 4c 89 4f e0 mov %r9,-0x20(%rdi) + 431260: 4c 89 57 e8 mov %r10,-0x18(%rdi) + 431264: 4c 89 5f f0 mov %r11,-0x10(%rdi) + 431268: 48 89 4f f8 mov %rcx,-0x8(%rdi) + 43126c: c3 retq + 43126d: 0f 1f 00 nopl (%rax) + 431270: f3 0f 6f 46 c0 movdqu -0x40(%rsi),%xmm0 + 431275: 48 8b 4e d0 mov -0x30(%rsi),%rcx + 431279: 4c 8b 46 d8 mov -0x28(%rsi),%r8 + 43127d: 4c 8b 4e e0 mov -0x20(%rsi),%r9 + 431281: 4c 8b 56 e8 mov -0x18(%rsi),%r10 + 431285: 4c 8b 5e f0 mov -0x10(%rsi),%r11 + 431289: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 43128d: f3 0f 7f 47 c0 movdqu %xmm0,-0x40(%rdi) + 431292: 48 89 4f d0 mov %rcx,-0x30(%rdi) + 431296: 4c 89 47 d8 mov %r8,-0x28(%rdi) + 43129a: 4c 89 4f e0 mov %r9,-0x20(%rdi) + 43129e: 4c 89 57 e8 mov %r10,-0x18(%rdi) + 4312a2: 4c 89 5f f0 mov %r11,-0x10(%rdi) + 4312a6: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 4312aa: c3 retq + 4312ab: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4312b0: f3 0f 6f 46 c8 movdqu -0x38(%rsi),%xmm0 + 4312b5: 4c 8b 46 d8 mov -0x28(%rsi),%r8 + 4312b9: 4c 8b 4e e0 mov -0x20(%rsi),%r9 + 4312bd: 4c 8b 56 e8 mov -0x18(%rsi),%r10 + 4312c1: 4c 8b 5e f0 mov -0x10(%rsi),%r11 + 4312c5: 48 8b 4e f8 mov -0x8(%rsi),%rcx + 4312c9: f3 0f 7f 47 c8 movdqu %xmm0,-0x38(%rdi) + 4312ce: 4c 89 47 d8 mov %r8,-0x28(%rdi) + 4312d2: 4c 89 4f e0 mov %r9,-0x20(%rdi) + 4312d6: 4c 89 57 e8 mov %r10,-0x18(%rdi) + 4312da: 4c 89 5f f0 mov %r11,-0x10(%rdi) + 4312de: 48 89 4f f8 mov %rcx,-0x8(%rdi) + 4312e2: c3 retq + 4312e3: 0f 1f 00 nopl (%rax) + 4312e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4312ed: 00 00 00 + 4312f0: 48 8b 4e d0 mov -0x30(%rsi),%rcx + 4312f4: 4c 8b 46 d8 mov -0x28(%rsi),%r8 + 4312f8: 4c 8b 4e e0 mov -0x20(%rsi),%r9 + 4312fc: 4c 8b 56 e8 mov -0x18(%rsi),%r10 + 431300: 4c 8b 5e f0 mov -0x10(%rsi),%r11 + 431304: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 431308: 48 89 4f d0 mov %rcx,-0x30(%rdi) + 43130c: 4c 89 47 d8 mov %r8,-0x28(%rdi) + 431310: 4c 89 4f e0 mov %r9,-0x20(%rdi) + 431314: 4c 89 57 e8 mov %r10,-0x18(%rdi) + 431318: 4c 89 5f f0 mov %r11,-0x10(%rdi) + 43131c: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 431320: c3 retq + 431321: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 431326: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43132d: 00 00 00 + 431330: 4c 8b 46 d8 mov -0x28(%rsi),%r8 + 431334: 4c 8b 4e e0 mov -0x20(%rsi),%r9 + 431338: 4c 8b 56 e8 mov -0x18(%rsi),%r10 + 43133c: 4c 8b 5e f0 mov -0x10(%rsi),%r11 + 431340: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 431344: 4c 89 47 d8 mov %r8,-0x28(%rdi) + 431348: 4c 89 4f e0 mov %r9,-0x20(%rdi) + 43134c: 4c 89 57 e8 mov %r10,-0x18(%rdi) + 431350: 4c 89 5f f0 mov %r11,-0x10(%rdi) + 431354: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 431358: c3 retq + 431359: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 431360: 4c 8b 4e e0 mov -0x20(%rsi),%r9 + 431364: 4c 8b 56 e8 mov -0x18(%rsi),%r10 + 431368: 4c 8b 5e f0 mov -0x10(%rsi),%r11 + 43136c: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 431370: 4c 89 4f e0 mov %r9,-0x20(%rdi) + 431374: 4c 89 57 e8 mov %r10,-0x18(%rdi) + 431378: 4c 89 5f f0 mov %r11,-0x10(%rdi) + 43137c: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 431380: c3 retq + 431381: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 431386: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43138d: 00 00 00 + 431390: 4c 8b 56 e8 mov -0x18(%rsi),%r10 + 431394: 4c 8b 5e f0 mov -0x10(%rsi),%r11 + 431398: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 43139c: 4c 89 57 e8 mov %r10,-0x18(%rdi) + 4313a0: 4c 89 5f f0 mov %r11,-0x10(%rdi) + 4313a4: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 4313a8: c3 retq + 4313a9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4313b0: 4c 8b 5e f0 mov -0x10(%rsi),%r11 + 4313b4: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 4313b8: 4c 89 5f f0 mov %r11,-0x10(%rdi) + 4313bc: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 4313c0: c3 retq + 4313c1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4313c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4313cd: 00 00 00 + 4313d0: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 4313d4: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 4313d8: c3 retq + 4313d9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4313e0: f3 0f 6f 46 b7 movdqu -0x49(%rsi),%xmm0 + 4313e5: f3 0f 6f 4e c7 movdqu -0x39(%rsi),%xmm1 + 4313ea: 48 8b 4e d7 mov -0x29(%rsi),%rcx + 4313ee: 4c 8b 4e df mov -0x21(%rsi),%r9 + 4313f2: 4c 8b 56 e7 mov -0x19(%rsi),%r10 + 4313f6: 4c 8b 5e ef mov -0x11(%rsi),%r11 + 4313fa: 4c 8b 46 f7 mov -0x9(%rsi),%r8 + 4313fe: 8b 56 fc mov -0x4(%rsi),%edx + 431401: f3 0f 7f 47 b7 movdqu %xmm0,-0x49(%rdi) + 431406: f3 0f 7f 4f c7 movdqu %xmm1,-0x39(%rdi) + 43140b: 48 89 4f d7 mov %rcx,-0x29(%rdi) + 43140f: 4c 89 4f df mov %r9,-0x21(%rdi) + 431413: 4c 89 57 e7 mov %r10,-0x19(%rdi) + 431417: 4c 89 5f ef mov %r11,-0x11(%rdi) + 43141b: 4c 89 47 f7 mov %r8,-0x9(%rdi) + 43141f: 89 57 fc mov %edx,-0x4(%rdi) + 431422: c3 retq + 431423: 0f 1f 00 nopl (%rax) + 431426: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43142d: 00 00 00 + 431430: f3 0f 6f 46 bf movdqu -0x41(%rsi),%xmm0 + 431435: f3 0f 6f 4e cf movdqu -0x31(%rsi),%xmm1 + 43143a: 4c 8b 4e df mov -0x21(%rsi),%r9 + 43143e: 4c 8b 56 e7 mov -0x19(%rsi),%r10 + 431442: 4c 8b 5e ef mov -0x11(%rsi),%r11 + 431446: 48 8b 4e f7 mov -0x9(%rsi),%rcx + 43144a: 8b 56 fc mov -0x4(%rsi),%edx + 43144d: f3 0f 7f 47 bf movdqu %xmm0,-0x41(%rdi) + 431452: f3 0f 7f 4f cf movdqu %xmm1,-0x31(%rdi) + 431457: 4c 89 4f df mov %r9,-0x21(%rdi) + 43145b: 4c 89 57 e7 mov %r10,-0x19(%rdi) + 43145f: 4c 89 5f ef mov %r11,-0x11(%rdi) + 431463: 48 89 4f f7 mov %rcx,-0x9(%rdi) + 431467: 89 57 fc mov %edx,-0x4(%rdi) + 43146a: c3 retq + 43146b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 431470: f3 0f 6f 46 c7 movdqu -0x39(%rsi),%xmm0 + 431475: 4c 8b 46 d7 mov -0x29(%rsi),%r8 + 431479: 4c 8b 4e df mov -0x21(%rsi),%r9 + 43147d: 4c 8b 56 e7 mov -0x19(%rsi),%r10 + 431481: 4c 8b 5e ef mov -0x11(%rsi),%r11 + 431485: 48 8b 4e f7 mov -0x9(%rsi),%rcx + 431489: 8b 56 fc mov -0x4(%rsi),%edx + 43148c: f3 0f 7f 47 c7 movdqu %xmm0,-0x39(%rdi) + 431491: 4c 89 47 d7 mov %r8,-0x29(%rdi) + 431495: 4c 89 4f df mov %r9,-0x21(%rdi) + 431499: 4c 89 57 e7 mov %r10,-0x19(%rdi) + 43149d: 4c 89 5f ef mov %r11,-0x11(%rdi) + 4314a1: 48 89 4f f7 mov %rcx,-0x9(%rdi) + 4314a5: 89 57 fc mov %edx,-0x4(%rdi) + 4314a8: c3 retq + 4314a9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4314b0: f3 0f 6f 46 cf movdqu -0x31(%rsi),%xmm0 + 4314b5: 4c 8b 4e df mov -0x21(%rsi),%r9 + 4314b9: 4c 8b 56 e7 mov -0x19(%rsi),%r10 + 4314bd: 4c 8b 5e ef mov -0x11(%rsi),%r11 + 4314c1: 48 8b 4e f7 mov -0x9(%rsi),%rcx + 4314c5: 8b 56 fc mov -0x4(%rsi),%edx + 4314c8: f3 0f 7f 47 cf movdqu %xmm0,-0x31(%rdi) + 4314cd: 4c 89 4f df mov %r9,-0x21(%rdi) + 4314d1: 4c 89 57 e7 mov %r10,-0x19(%rdi) + 4314d5: 4c 89 5f ef mov %r11,-0x11(%rdi) + 4314d9: 48 89 4f f7 mov %rcx,-0x9(%rdi) + 4314dd: 89 57 fc mov %edx,-0x4(%rdi) + 4314e0: c3 retq + 4314e1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4314e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4314ed: 00 00 00 + 4314f0: 4c 8b 46 d7 mov -0x29(%rsi),%r8 + 4314f4: 4c 8b 4e df mov -0x21(%rsi),%r9 + 4314f8: 4c 8b 56 e7 mov -0x19(%rsi),%r10 + 4314fc: 4c 8b 5e ef mov -0x11(%rsi),%r11 + 431500: 48 8b 4e f7 mov -0x9(%rsi),%rcx + 431504: 8a 56 ff mov -0x1(%rsi),%dl + 431507: 4c 89 47 d7 mov %r8,-0x29(%rdi) + 43150b: 4c 89 4f df mov %r9,-0x21(%rdi) + 43150f: 4c 89 57 e7 mov %r10,-0x19(%rdi) + 431513: 4c 89 5f ef mov %r11,-0x11(%rdi) + 431517: 48 89 4f f7 mov %rcx,-0x9(%rdi) + 43151b: 88 57 ff mov %dl,-0x1(%rdi) + 43151e: c3 retq + 43151f: 90 nop + 431520: 4c 8b 4e df mov -0x21(%rsi),%r9 + 431524: 4c 8b 56 e7 mov -0x19(%rsi),%r10 + 431528: 4c 8b 5e ef mov -0x11(%rsi),%r11 + 43152c: 48 8b 4e f7 mov -0x9(%rsi),%rcx + 431530: 8a 56 ff mov -0x1(%rsi),%dl + 431533: 4c 89 4f df mov %r9,-0x21(%rdi) + 431537: 4c 89 57 e7 mov %r10,-0x19(%rdi) + 43153b: 4c 89 5f ef mov %r11,-0x11(%rdi) + 43153f: 48 89 4f f7 mov %rcx,-0x9(%rdi) + 431543: 88 57 ff mov %dl,-0x1(%rdi) + 431546: c3 retq + 431547: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 43154e: 00 00 + 431550: 4c 8b 56 e7 mov -0x19(%rsi),%r10 + 431554: 4c 8b 5e ef mov -0x11(%rsi),%r11 + 431558: 48 8b 4e f7 mov -0x9(%rsi),%rcx + 43155c: 8a 56 ff mov -0x1(%rsi),%dl + 43155f: 4c 89 57 e7 mov %r10,-0x19(%rdi) + 431563: 4c 89 5f ef mov %r11,-0x11(%rdi) + 431567: 48 89 4f f7 mov %rcx,-0x9(%rdi) + 43156b: 88 57 ff mov %dl,-0x1(%rdi) + 43156e: c3 retq + 43156f: 90 nop + 431570: 4c 8b 5e ef mov -0x11(%rsi),%r11 + 431574: 48 8b 4e f7 mov -0x9(%rsi),%rcx + 431578: 8b 56 fc mov -0x4(%rsi),%edx + 43157b: 4c 89 5f ef mov %r11,-0x11(%rdi) + 43157f: 48 89 4f f7 mov %rcx,-0x9(%rdi) + 431583: 89 57 fc mov %edx,-0x4(%rdi) + 431586: c3 retq + 431587: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 43158e: 00 00 + 431590: 48 8b 4e f7 mov -0x9(%rsi),%rcx + 431594: 8b 56 fc mov -0x4(%rsi),%edx + 431597: 48 89 4f f7 mov %rcx,-0x9(%rdi) + 43159b: 89 57 fc mov %edx,-0x4(%rdi) + 43159e: c3 retq + 43159f: 90 nop + 4315a0: 8a 56 ff mov -0x1(%rsi),%dl + 4315a3: 88 57 ff mov %dl,-0x1(%rdi) + 4315a6: c3 retq + 4315a7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 4315ae: 00 00 + 4315b0: f3 0f 6f 46 b6 movdqu -0x4a(%rsi),%xmm0 + 4315b5: f3 0f 6f 4e c6 movdqu -0x3a(%rsi),%xmm1 + 4315ba: 4c 8b 46 d6 mov -0x2a(%rsi),%r8 + 4315be: 4c 8b 4e de mov -0x22(%rsi),%r9 + 4315c2: 4c 8b 56 e6 mov -0x1a(%rsi),%r10 + 4315c6: 4c 8b 5e ee mov -0x12(%rsi),%r11 + 4315ca: 48 8b 4e f6 mov -0xa(%rsi),%rcx + 4315ce: 8b 56 fc mov -0x4(%rsi),%edx + 4315d1: f3 0f 7f 47 b6 movdqu %xmm0,-0x4a(%rdi) + 4315d6: f3 0f 7f 4f c6 movdqu %xmm1,-0x3a(%rdi) + 4315db: 4c 89 47 d6 mov %r8,-0x2a(%rdi) + 4315df: 4c 89 4f de mov %r9,-0x22(%rdi) + 4315e3: 4c 89 57 e6 mov %r10,-0x1a(%rdi) + 4315e7: 4c 89 5f ee mov %r11,-0x12(%rdi) + 4315eb: 48 89 4f f6 mov %rcx,-0xa(%rdi) + 4315ef: 89 57 fc mov %edx,-0x4(%rdi) + 4315f2: c3 retq + 4315f3: 0f 1f 00 nopl (%rax) + 4315f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4315fd: 00 00 00 + 431600: f3 0f 6f 46 be movdqu -0x42(%rsi),%xmm0 + 431605: f3 0f 6f 4e ce movdqu -0x32(%rsi),%xmm1 + 43160a: 4c 8b 46 d6 mov -0x2a(%rsi),%r8 + 43160e: 4c 8b 4e de mov -0x22(%rsi),%r9 + 431612: 4c 8b 56 e6 mov -0x1a(%rsi),%r10 + 431616: 4c 8b 5e ee mov -0x12(%rsi),%r11 + 43161a: 48 8b 4e f6 mov -0xa(%rsi),%rcx + 43161e: 8b 56 fc mov -0x4(%rsi),%edx + 431621: f3 0f 7f 47 be movdqu %xmm0,-0x42(%rdi) + 431626: f3 0f 7f 4f ce movdqu %xmm1,-0x32(%rdi) + 43162b: 4c 89 47 d6 mov %r8,-0x2a(%rdi) + 43162f: 4c 89 4f de mov %r9,-0x22(%rdi) + 431633: 4c 89 57 e6 mov %r10,-0x1a(%rdi) + 431637: 4c 89 5f ee mov %r11,-0x12(%rdi) + 43163b: 48 89 4f f6 mov %rcx,-0xa(%rdi) + 43163f: 89 57 fc mov %edx,-0x4(%rdi) + 431642: c3 retq + 431643: 0f 1f 00 nopl (%rax) + 431646: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43164d: 00 00 00 + 431650: f3 0f 6f 4e c6 movdqu -0x3a(%rsi),%xmm1 + 431655: 4c 8b 46 d6 mov -0x2a(%rsi),%r8 + 431659: 4c 8b 4e de mov -0x22(%rsi),%r9 + 43165d: 4c 8b 56 e6 mov -0x1a(%rsi),%r10 + 431661: 4c 8b 5e ee mov -0x12(%rsi),%r11 + 431665: 48 8b 4e f6 mov -0xa(%rsi),%rcx + 431669: 8b 56 fc mov -0x4(%rsi),%edx + 43166c: f3 0f 7f 4f c6 movdqu %xmm1,-0x3a(%rdi) + 431671: 4c 89 47 d6 mov %r8,-0x2a(%rdi) + 431675: 4c 89 4f de mov %r9,-0x22(%rdi) + 431679: 4c 89 57 e6 mov %r10,-0x1a(%rdi) + 43167d: 4c 89 5f ee mov %r11,-0x12(%rdi) + 431681: 48 89 4f f6 mov %rcx,-0xa(%rdi) + 431685: 89 57 fc mov %edx,-0x4(%rdi) + 431688: c3 retq + 431689: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 431690: f3 0f 6f 46 ce movdqu -0x32(%rsi),%xmm0 + 431695: 4c 8b 4e de mov -0x22(%rsi),%r9 + 431699: 4c 8b 56 e6 mov -0x1a(%rsi),%r10 + 43169d: 4c 8b 5e ee mov -0x12(%rsi),%r11 + 4316a1: 48 8b 4e f6 mov -0xa(%rsi),%rcx + 4316a5: 8b 56 fc mov -0x4(%rsi),%edx + 4316a8: f3 0f 7f 47 ce movdqu %xmm0,-0x32(%rdi) + 4316ad: 4c 89 4f de mov %r9,-0x22(%rdi) + 4316b1: 4c 89 57 e6 mov %r10,-0x1a(%rdi) + 4316b5: 4c 89 5f ee mov %r11,-0x12(%rdi) + 4316b9: 48 89 4f f6 mov %rcx,-0xa(%rdi) + 4316bd: 89 57 fc mov %edx,-0x4(%rdi) + 4316c0: c3 retq + 4316c1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4316c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4316cd: 00 00 00 + 4316d0: 4c 8b 46 d6 mov -0x2a(%rsi),%r8 + 4316d4: 4c 8b 4e de mov -0x22(%rsi),%r9 + 4316d8: 4c 8b 56 e6 mov -0x1a(%rsi),%r10 + 4316dc: 4c 8b 5e ee mov -0x12(%rsi),%r11 + 4316e0: 48 8b 4e f6 mov -0xa(%rsi),%rcx + 4316e4: 8b 56 fc mov -0x4(%rsi),%edx + 4316e7: 4c 89 47 d6 mov %r8,-0x2a(%rdi) + 4316eb: 4c 89 4f de mov %r9,-0x22(%rdi) + 4316ef: 4c 89 57 e6 mov %r10,-0x1a(%rdi) + 4316f3: 4c 89 5f ee mov %r11,-0x12(%rdi) + 4316f7: 48 89 4f f6 mov %rcx,-0xa(%rdi) + 4316fb: 89 57 fc mov %edx,-0x4(%rdi) + 4316fe: c3 retq + 4316ff: 90 nop + 431700: 4c 8b 4e de mov -0x22(%rsi),%r9 + 431704: 4c 8b 56 e6 mov -0x1a(%rsi),%r10 + 431708: 4c 8b 5e ee mov -0x12(%rsi),%r11 + 43170c: 48 8b 4e f6 mov -0xa(%rsi),%rcx + 431710: 8b 56 fc mov -0x4(%rsi),%edx + 431713: 4c 89 4f de mov %r9,-0x22(%rdi) + 431717: 4c 89 57 e6 mov %r10,-0x1a(%rdi) + 43171b: 4c 89 5f ee mov %r11,-0x12(%rdi) + 43171f: 48 89 4f f6 mov %rcx,-0xa(%rdi) + 431723: 89 57 fc mov %edx,-0x4(%rdi) + 431726: c3 retq + 431727: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 43172e: 00 00 + 431730: 4c 8b 56 e6 mov -0x1a(%rsi),%r10 + 431734: 4c 8b 5e ee mov -0x12(%rsi),%r11 + 431738: 48 8b 4e f6 mov -0xa(%rsi),%rcx + 43173c: 8b 56 fc mov -0x4(%rsi),%edx + 43173f: 4c 89 57 e6 mov %r10,-0x1a(%rdi) + 431743: 4c 89 5f ee mov %r11,-0x12(%rdi) + 431747: 48 89 4f f6 mov %rcx,-0xa(%rdi) + 43174b: 89 57 fc mov %edx,-0x4(%rdi) + 43174e: c3 retq + 43174f: 90 nop + 431750: 4c 8b 5e ee mov -0x12(%rsi),%r11 + 431754: 48 8b 4e f6 mov -0xa(%rsi),%rcx + 431758: 8b 56 fc mov -0x4(%rsi),%edx + 43175b: 4c 89 5f ee mov %r11,-0x12(%rdi) + 43175f: 48 89 4f f6 mov %rcx,-0xa(%rdi) + 431763: 89 57 fc mov %edx,-0x4(%rdi) + 431766: c3 retq + 431767: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 43176e: 00 00 + 431770: 48 8b 4e f6 mov -0xa(%rsi),%rcx + 431774: 8b 56 fc mov -0x4(%rsi),%edx + 431777: 48 89 4f f6 mov %rcx,-0xa(%rdi) + 43177b: 89 57 fc mov %edx,-0x4(%rdi) + 43177e: c3 retq + 43177f: 90 nop + 431780: 66 8b 56 fe mov -0x2(%rsi),%dx + 431784: 66 89 57 fe mov %dx,-0x2(%rdi) + 431788: c3 retq + 431789: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 431790: f3 0f 6f 46 b5 movdqu -0x4b(%rsi),%xmm0 + 431795: f3 0f 6f 4e c5 movdqu -0x3b(%rsi),%xmm1 + 43179a: 4c 8b 46 d5 mov -0x2b(%rsi),%r8 + 43179e: 4c 8b 4e dd mov -0x23(%rsi),%r9 + 4317a2: 4c 8b 56 e5 mov -0x1b(%rsi),%r10 + 4317a6: 4c 8b 5e ed mov -0x13(%rsi),%r11 + 4317aa: 48 8b 4e f5 mov -0xb(%rsi),%rcx + 4317ae: 8b 56 fc mov -0x4(%rsi),%edx + 4317b1: f3 0f 7f 47 b5 movdqu %xmm0,-0x4b(%rdi) + 4317b6: f3 0f 7f 4f c5 movdqu %xmm1,-0x3b(%rdi) + 4317bb: 4c 89 47 d5 mov %r8,-0x2b(%rdi) + 4317bf: 4c 89 4f dd mov %r9,-0x23(%rdi) + 4317c3: 4c 89 57 e5 mov %r10,-0x1b(%rdi) + 4317c7: 4c 89 5f ed mov %r11,-0x13(%rdi) + 4317cb: 48 89 4f f5 mov %rcx,-0xb(%rdi) + 4317cf: 89 57 fc mov %edx,-0x4(%rdi) + 4317d2: c3 retq + 4317d3: 0f 1f 00 nopl (%rax) + 4317d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4317dd: 00 00 00 + 4317e0: f3 0f 6f 46 bd movdqu -0x43(%rsi),%xmm0 + 4317e5: f3 0f 6f 4e c5 movdqu -0x3b(%rsi),%xmm1 + 4317ea: 4c 8b 46 d5 mov -0x2b(%rsi),%r8 + 4317ee: 4c 8b 4e dd mov -0x23(%rsi),%r9 + 4317f2: 4c 8b 56 e5 mov -0x1b(%rsi),%r10 + 4317f6: 4c 8b 5e ed mov -0x13(%rsi),%r11 + 4317fa: 48 8b 4e f5 mov -0xb(%rsi),%rcx + 4317fe: 8b 56 fc mov -0x4(%rsi),%edx + 431801: f3 0f 7f 47 bd movdqu %xmm0,-0x43(%rdi) + 431806: f3 0f 7f 4f c5 movdqu %xmm1,-0x3b(%rdi) + 43180b: 4c 89 47 d5 mov %r8,-0x2b(%rdi) + 43180f: 4c 89 4f dd mov %r9,-0x23(%rdi) + 431813: 4c 89 57 e5 mov %r10,-0x1b(%rdi) + 431817: 4c 89 5f ed mov %r11,-0x13(%rdi) + 43181b: 48 89 4f f5 mov %rcx,-0xb(%rdi) + 43181f: 89 57 fc mov %edx,-0x4(%rdi) + 431822: c3 retq + 431823: 0f 1f 00 nopl (%rax) + 431826: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43182d: 00 00 00 + 431830: f3 0f 6f 46 c5 movdqu -0x3b(%rsi),%xmm0 + 431835: 4c 8b 46 d5 mov -0x2b(%rsi),%r8 + 431839: 4c 8b 4e dd mov -0x23(%rsi),%r9 + 43183d: 4c 8b 56 e5 mov -0x1b(%rsi),%r10 + 431841: 4c 8b 5e ed mov -0x13(%rsi),%r11 + 431845: 48 8b 4e f5 mov -0xb(%rsi),%rcx + 431849: 8b 56 fc mov -0x4(%rsi),%edx + 43184c: f3 0f 7f 47 c5 movdqu %xmm0,-0x3b(%rdi) + 431851: 4c 89 47 d5 mov %r8,-0x2b(%rdi) + 431855: 4c 89 4f dd mov %r9,-0x23(%rdi) + 431859: 4c 89 57 e5 mov %r10,-0x1b(%rdi) + 43185d: 4c 89 5f ed mov %r11,-0x13(%rdi) + 431861: 48 89 4f f5 mov %rcx,-0xb(%rdi) + 431865: 89 57 fc mov %edx,-0x4(%rdi) + 431868: c3 retq + 431869: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 431870: f3 0f 6f 46 cd movdqu -0x33(%rsi),%xmm0 + 431875: 4c 8b 4e dd mov -0x23(%rsi),%r9 + 431879: 4c 8b 56 e5 mov -0x1b(%rsi),%r10 + 43187d: 4c 8b 5e ed mov -0x13(%rsi),%r11 + 431881: 48 8b 4e f5 mov -0xb(%rsi),%rcx + 431885: 8b 56 fc mov -0x4(%rsi),%edx + 431888: f3 0f 7f 47 cd movdqu %xmm0,-0x33(%rdi) + 43188d: 4c 89 4f dd mov %r9,-0x23(%rdi) + 431891: 4c 89 57 e5 mov %r10,-0x1b(%rdi) + 431895: 4c 89 5f ed mov %r11,-0x13(%rdi) + 431899: 48 89 4f f5 mov %rcx,-0xb(%rdi) + 43189d: 89 57 fc mov %edx,-0x4(%rdi) + 4318a0: c3 retq + 4318a1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4318a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4318ad: 00 00 00 + 4318b0: 4c 8b 46 d5 mov -0x2b(%rsi),%r8 + 4318b4: 4c 8b 4e dd mov -0x23(%rsi),%r9 + 4318b8: 4c 8b 56 e5 mov -0x1b(%rsi),%r10 + 4318bc: 4c 8b 5e ed mov -0x13(%rsi),%r11 + 4318c0: 48 8b 4e f5 mov -0xb(%rsi),%rcx + 4318c4: 8b 56 fc mov -0x4(%rsi),%edx + 4318c7: 4c 89 47 d5 mov %r8,-0x2b(%rdi) + 4318cb: 4c 89 4f dd mov %r9,-0x23(%rdi) + 4318cf: 4c 89 57 e5 mov %r10,-0x1b(%rdi) + 4318d3: 4c 89 5f ed mov %r11,-0x13(%rdi) + 4318d7: 48 89 4f f5 mov %rcx,-0xb(%rdi) + 4318db: 89 57 fc mov %edx,-0x4(%rdi) + 4318de: c3 retq + 4318df: 90 nop + 4318e0: 4c 8b 4e dd mov -0x23(%rsi),%r9 + 4318e4: 4c 8b 56 e5 mov -0x1b(%rsi),%r10 + 4318e8: 4c 8b 5e ed mov -0x13(%rsi),%r11 + 4318ec: 48 8b 4e f5 mov -0xb(%rsi),%rcx + 4318f0: 8b 56 fc mov -0x4(%rsi),%edx + 4318f3: 4c 89 4f dd mov %r9,-0x23(%rdi) + 4318f7: 4c 89 57 e5 mov %r10,-0x1b(%rdi) + 4318fb: 4c 89 5f ed mov %r11,-0x13(%rdi) + 4318ff: 48 89 4f f5 mov %rcx,-0xb(%rdi) + 431903: 89 57 fc mov %edx,-0x4(%rdi) + 431906: c3 retq + 431907: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 43190e: 00 00 + 431910: 4c 8b 56 e5 mov -0x1b(%rsi),%r10 + 431914: 4c 8b 5e ed mov -0x13(%rsi),%r11 + 431918: 48 8b 4e f5 mov -0xb(%rsi),%rcx + 43191c: 8b 56 fc mov -0x4(%rsi),%edx + 43191f: 4c 89 57 e5 mov %r10,-0x1b(%rdi) + 431923: 4c 89 5f ed mov %r11,-0x13(%rdi) + 431927: 48 89 4f f5 mov %rcx,-0xb(%rdi) + 43192b: 89 57 fc mov %edx,-0x4(%rdi) + 43192e: c3 retq + 43192f: 90 nop + 431930: 4c 8b 5e ed mov -0x13(%rsi),%r11 + 431934: 48 8b 4e f5 mov -0xb(%rsi),%rcx + 431938: 8b 56 fc mov -0x4(%rsi),%edx + 43193b: 4c 89 5f ed mov %r11,-0x13(%rdi) + 43193f: 48 89 4f f5 mov %rcx,-0xb(%rdi) + 431943: 89 57 fc mov %edx,-0x4(%rdi) + 431946: c3 retq + 431947: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 43194e: 00 00 + 431950: 48 8b 4e f5 mov -0xb(%rsi),%rcx + 431954: 8b 56 fc mov -0x4(%rsi),%edx + 431957: 48 89 4f f5 mov %rcx,-0xb(%rdi) + 43195b: 89 57 fc mov %edx,-0x4(%rdi) + 43195e: c3 retq + 43195f: 90 nop + 431960: 66 8b 56 fd mov -0x3(%rsi),%dx + 431964: 66 8b 4e fe mov -0x2(%rsi),%cx + 431968: 66 89 57 fd mov %dx,-0x3(%rdi) + 43196c: 66 89 4f fe mov %cx,-0x2(%rdi) + 431970: c3 retq + 431971: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 431976: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43197d: 00 00 00 + 431980: f3 0f 6f 46 b4 movdqu -0x4c(%rsi),%xmm0 + 431985: f3 0f 6f 4e c4 movdqu -0x3c(%rsi),%xmm1 + 43198a: 4c 8b 46 d4 mov -0x2c(%rsi),%r8 + 43198e: 4c 8b 4e dc mov -0x24(%rsi),%r9 + 431992: 4c 8b 56 e4 mov -0x1c(%rsi),%r10 + 431996: 4c 8b 5e ec mov -0x14(%rsi),%r11 + 43199a: 48 8b 4e f4 mov -0xc(%rsi),%rcx + 43199e: 8b 56 fc mov -0x4(%rsi),%edx + 4319a1: f3 0f 7f 47 b4 movdqu %xmm0,-0x4c(%rdi) + 4319a6: f3 0f 7f 4f c4 movdqu %xmm1,-0x3c(%rdi) + 4319ab: 4c 89 47 d4 mov %r8,-0x2c(%rdi) + 4319af: 4c 89 4f dc mov %r9,-0x24(%rdi) + 4319b3: 4c 89 57 e4 mov %r10,-0x1c(%rdi) + 4319b7: 4c 89 5f ec mov %r11,-0x14(%rdi) + 4319bb: 48 89 4f f4 mov %rcx,-0xc(%rdi) + 4319bf: 89 57 fc mov %edx,-0x4(%rdi) + 4319c2: c3 retq + 4319c3: 0f 1f 00 nopl (%rax) + 4319c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4319cd: 00 00 00 + 4319d0: f3 0f 6f 46 bc movdqu -0x44(%rsi),%xmm0 + 4319d5: f3 0f 6f 4e cc movdqu -0x34(%rsi),%xmm1 + 4319da: 4c 8b 4e dc mov -0x24(%rsi),%r9 + 4319de: 4c 8b 56 e4 mov -0x1c(%rsi),%r10 + 4319e2: 4c 8b 5e ec mov -0x14(%rsi),%r11 + 4319e6: 48 8b 4e f4 mov -0xc(%rsi),%rcx + 4319ea: 8b 56 fc mov -0x4(%rsi),%edx + 4319ed: f3 0f 7f 47 bc movdqu %xmm0,-0x44(%rdi) + 4319f2: f3 0f 7f 4f cc movdqu %xmm1,-0x34(%rdi) + 4319f7: 4c 89 4f dc mov %r9,-0x24(%rdi) + 4319fb: 4c 89 57 e4 mov %r10,-0x1c(%rdi) + 4319ff: 4c 89 5f ec mov %r11,-0x14(%rdi) + 431a03: 48 89 4f f4 mov %rcx,-0xc(%rdi) + 431a07: 89 57 fc mov %edx,-0x4(%rdi) + 431a0a: c3 retq + 431a0b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 431a10: f3 0f 6f 46 c4 movdqu -0x3c(%rsi),%xmm0 + 431a15: 4c 8b 46 d4 mov -0x2c(%rsi),%r8 + 431a19: 4c 8b 4e dc mov -0x24(%rsi),%r9 + 431a1d: 4c 8b 56 e4 mov -0x1c(%rsi),%r10 + 431a21: 4c 8b 5e ec mov -0x14(%rsi),%r11 + 431a25: 48 8b 4e f4 mov -0xc(%rsi),%rcx + 431a29: 8b 56 fc mov -0x4(%rsi),%edx + 431a2c: f3 0f 7f 47 c4 movdqu %xmm0,-0x3c(%rdi) + 431a31: 4c 89 47 d4 mov %r8,-0x2c(%rdi) + 431a35: 4c 89 4f dc mov %r9,-0x24(%rdi) + 431a39: 4c 89 57 e4 mov %r10,-0x1c(%rdi) + 431a3d: 4c 89 5f ec mov %r11,-0x14(%rdi) + 431a41: 48 89 4f f4 mov %rcx,-0xc(%rdi) + 431a45: 89 57 fc mov %edx,-0x4(%rdi) + 431a48: c3 retq + 431a49: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 431a50: f3 0f 6f 46 cc movdqu -0x34(%rsi),%xmm0 + 431a55: 4c 8b 4e dc mov -0x24(%rsi),%r9 + 431a59: 4c 8b 56 e4 mov -0x1c(%rsi),%r10 + 431a5d: 4c 8b 5e ec mov -0x14(%rsi),%r11 + 431a61: 48 8b 4e f4 mov -0xc(%rsi),%rcx + 431a65: 8b 56 fc mov -0x4(%rsi),%edx + 431a68: f3 0f 7f 47 cc movdqu %xmm0,-0x34(%rdi) + 431a6d: 4c 89 4f dc mov %r9,-0x24(%rdi) + 431a71: 4c 89 57 e4 mov %r10,-0x1c(%rdi) + 431a75: 4c 89 5f ec mov %r11,-0x14(%rdi) + 431a79: 48 89 4f f4 mov %rcx,-0xc(%rdi) + 431a7d: 89 57 fc mov %edx,-0x4(%rdi) + 431a80: c3 retq + 431a81: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 431a86: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 431a8d: 00 00 00 + 431a90: 4c 8b 46 d4 mov -0x2c(%rsi),%r8 + 431a94: 4c 8b 4e dc mov -0x24(%rsi),%r9 + 431a98: 4c 8b 56 e4 mov -0x1c(%rsi),%r10 + 431a9c: 4c 8b 5e ec mov -0x14(%rsi),%r11 + 431aa0: 48 8b 4e f4 mov -0xc(%rsi),%rcx + 431aa4: 8b 56 fc mov -0x4(%rsi),%edx + 431aa7: 4c 89 47 d4 mov %r8,-0x2c(%rdi) + 431aab: 4c 89 4f dc mov %r9,-0x24(%rdi) + 431aaf: 4c 89 57 e4 mov %r10,-0x1c(%rdi) + 431ab3: 4c 89 5f ec mov %r11,-0x14(%rdi) + 431ab7: 48 89 4f f4 mov %rcx,-0xc(%rdi) + 431abb: 89 57 fc mov %edx,-0x4(%rdi) + 431abe: c3 retq + 431abf: 90 nop + 431ac0: 4c 8b 4e dc mov -0x24(%rsi),%r9 + 431ac4: 4c 8b 56 e4 mov -0x1c(%rsi),%r10 + 431ac8: 4c 8b 5e ec mov -0x14(%rsi),%r11 + 431acc: 48 8b 4e f4 mov -0xc(%rsi),%rcx + 431ad0: 8b 56 fc mov -0x4(%rsi),%edx + 431ad3: 4c 89 4f dc mov %r9,-0x24(%rdi) + 431ad7: 4c 89 57 e4 mov %r10,-0x1c(%rdi) + 431adb: 4c 89 5f ec mov %r11,-0x14(%rdi) + 431adf: 48 89 4f f4 mov %rcx,-0xc(%rdi) + 431ae3: 89 57 fc mov %edx,-0x4(%rdi) + 431ae6: c3 retq + 431ae7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 431aee: 00 00 + 431af0: 4c 8b 56 e4 mov -0x1c(%rsi),%r10 + 431af4: 4c 8b 5e ec mov -0x14(%rsi),%r11 + 431af8: 48 8b 4e f4 mov -0xc(%rsi),%rcx + 431afc: 8b 56 fc mov -0x4(%rsi),%edx + 431aff: 4c 89 57 e4 mov %r10,-0x1c(%rdi) + 431b03: 4c 89 5f ec mov %r11,-0x14(%rdi) + 431b07: 48 89 4f f4 mov %rcx,-0xc(%rdi) + 431b0b: 89 57 fc mov %edx,-0x4(%rdi) + 431b0e: c3 retq + 431b0f: 90 nop + 431b10: 4c 8b 5e ec mov -0x14(%rsi),%r11 + 431b14: 48 8b 4e f4 mov -0xc(%rsi),%rcx + 431b18: 8b 56 fc mov -0x4(%rsi),%edx + 431b1b: 4c 89 5f ec mov %r11,-0x14(%rdi) + 431b1f: 48 89 4f f4 mov %rcx,-0xc(%rdi) + 431b23: 89 57 fc mov %edx,-0x4(%rdi) + 431b26: c3 retq + 431b27: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 431b2e: 00 00 + 431b30: 48 8b 4e f4 mov -0xc(%rsi),%rcx + 431b34: 8b 56 fc mov -0x4(%rsi),%edx + 431b37: 48 89 4f f4 mov %rcx,-0xc(%rdi) + 431b3b: 89 57 fc mov %edx,-0x4(%rdi) + 431b3e: c3 retq + 431b3f: 90 nop + 431b40: 8b 56 fc mov -0x4(%rsi),%edx + 431b43: 89 57 fc mov %edx,-0x4(%rdi) + 431b46: c3 retq + 431b47: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 431b4e: 00 00 + 431b50: f3 0f 6f 46 b3 movdqu -0x4d(%rsi),%xmm0 + 431b55: f3 0f 6f 4e c3 movdqu -0x3d(%rsi),%xmm1 + 431b5a: 4c 8b 46 d3 mov -0x2d(%rsi),%r8 + 431b5e: 4c 8b 4e db mov -0x25(%rsi),%r9 + 431b62: 4c 8b 56 e3 mov -0x1d(%rsi),%r10 + 431b66: 4c 8b 5e eb mov -0x15(%rsi),%r11 + 431b6a: 48 8b 4e f3 mov -0xd(%rsi),%rcx + 431b6e: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 431b72: f3 0f 7f 47 b3 movdqu %xmm0,-0x4d(%rdi) + 431b77: f3 0f 7f 4f c3 movdqu %xmm1,-0x3d(%rdi) + 431b7c: 4c 89 47 d3 mov %r8,-0x2d(%rdi) + 431b80: 4c 89 4f db mov %r9,-0x25(%rdi) + 431b84: 4c 89 57 e3 mov %r10,-0x1d(%rdi) + 431b88: 4c 89 5f eb mov %r11,-0x15(%rdi) + 431b8c: 48 89 4f f3 mov %rcx,-0xd(%rdi) + 431b90: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 431b94: c3 retq + 431b95: 90 nop + 431b96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 431b9d: 00 00 00 + 431ba0: f3 0f 6f 46 bb movdqu -0x45(%rsi),%xmm0 + 431ba5: f3 0f 6f 4e cb movdqu -0x35(%rsi),%xmm1 + 431baa: 4c 8b 4e db mov -0x25(%rsi),%r9 + 431bae: 4c 8b 56 e3 mov -0x1d(%rsi),%r10 + 431bb2: 4c 8b 5e eb mov -0x15(%rsi),%r11 + 431bb6: 48 8b 4e f3 mov -0xd(%rsi),%rcx + 431bba: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 431bbe: f3 0f 7f 47 bb movdqu %xmm0,-0x45(%rdi) + 431bc3: f3 0f 7f 4f cb movdqu %xmm1,-0x35(%rdi) + 431bc8: 4c 89 4f db mov %r9,-0x25(%rdi) + 431bcc: 4c 89 57 e3 mov %r10,-0x1d(%rdi) + 431bd0: 4c 89 5f eb mov %r11,-0x15(%rdi) + 431bd4: 48 89 4f f3 mov %rcx,-0xd(%rdi) + 431bd8: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 431bdc: c3 retq + 431bdd: 0f 1f 00 nopl (%rax) + 431be0: f3 0f 6f 46 c3 movdqu -0x3d(%rsi),%xmm0 + 431be5: 4c 8b 46 d3 mov -0x2d(%rsi),%r8 + 431be9: 4c 8b 4e db mov -0x25(%rsi),%r9 + 431bed: 4c 8b 56 e3 mov -0x1d(%rsi),%r10 + 431bf1: 4c 8b 5e eb mov -0x15(%rsi),%r11 + 431bf5: 48 8b 4e f3 mov -0xd(%rsi),%rcx + 431bf9: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 431bfd: f3 0f 7f 47 c3 movdqu %xmm0,-0x3d(%rdi) + 431c02: 4c 89 47 d3 mov %r8,-0x2d(%rdi) + 431c06: 4c 89 4f db mov %r9,-0x25(%rdi) + 431c0a: 4c 89 57 e3 mov %r10,-0x1d(%rdi) + 431c0e: 4c 89 5f eb mov %r11,-0x15(%rdi) + 431c12: 48 89 4f f3 mov %rcx,-0xd(%rdi) + 431c16: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 431c1a: c3 retq + 431c1b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 431c20: f3 0f 6f 46 cb movdqu -0x35(%rsi),%xmm0 + 431c25: 4c 8b 46 d3 mov -0x2d(%rsi),%r8 + 431c29: 4c 8b 4e db mov -0x25(%rsi),%r9 + 431c2d: 4c 8b 56 e3 mov -0x1d(%rsi),%r10 + 431c31: 4c 8b 5e eb mov -0x15(%rsi),%r11 + 431c35: 48 8b 4e f3 mov -0xd(%rsi),%rcx + 431c39: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 431c3d: f3 0f 7f 47 cb movdqu %xmm0,-0x35(%rdi) + 431c42: 4c 89 4f db mov %r9,-0x25(%rdi) + 431c46: 4c 89 57 e3 mov %r10,-0x1d(%rdi) + 431c4a: 4c 89 5f eb mov %r11,-0x15(%rdi) + 431c4e: 48 89 4f f3 mov %rcx,-0xd(%rdi) + 431c52: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 431c56: c3 retq + 431c57: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 431c5e: 00 00 + 431c60: 4c 8b 46 d3 mov -0x2d(%rsi),%r8 + 431c64: 4c 8b 4e db mov -0x25(%rsi),%r9 + 431c68: 4c 8b 56 e3 mov -0x1d(%rsi),%r10 + 431c6c: 4c 8b 5e eb mov -0x15(%rsi),%r11 + 431c70: 48 8b 4e f3 mov -0xd(%rsi),%rcx + 431c74: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 431c78: 4c 89 47 d3 mov %r8,-0x2d(%rdi) + 431c7c: 4c 89 4f db mov %r9,-0x25(%rdi) + 431c80: 4c 89 57 e3 mov %r10,-0x1d(%rdi) + 431c84: 4c 89 5f eb mov %r11,-0x15(%rdi) + 431c88: 48 89 4f f3 mov %rcx,-0xd(%rdi) + 431c8c: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 431c90: c3 retq + 431c91: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 431c96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 431c9d: 00 00 00 + 431ca0: 4c 8b 4e db mov -0x25(%rsi),%r9 + 431ca4: 4c 8b 56 e3 mov -0x1d(%rsi),%r10 + 431ca8: 4c 8b 5e eb mov -0x15(%rsi),%r11 + 431cac: 48 8b 4e f3 mov -0xd(%rsi),%rcx + 431cb0: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 431cb4: 4c 89 4f db mov %r9,-0x25(%rdi) + 431cb8: 4c 89 57 e3 mov %r10,-0x1d(%rdi) + 431cbc: 4c 89 5f eb mov %r11,-0x15(%rdi) + 431cc0: 48 89 4f f3 mov %rcx,-0xd(%rdi) + 431cc4: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 431cc8: c3 retq + 431cc9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 431cd0: 4c 8b 56 e3 mov -0x1d(%rsi),%r10 + 431cd4: 4c 8b 5e eb mov -0x15(%rsi),%r11 + 431cd8: 48 8b 4e f3 mov -0xd(%rsi),%rcx + 431cdc: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 431ce0: 4c 89 57 e3 mov %r10,-0x1d(%rdi) + 431ce4: 4c 89 5f eb mov %r11,-0x15(%rdi) + 431ce8: 48 89 4f f3 mov %rcx,-0xd(%rdi) + 431cec: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 431cf0: c3 retq + 431cf1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 431cf6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 431cfd: 00 00 00 + 431d00: 4c 8b 5e eb mov -0x15(%rsi),%r11 + 431d04: 48 8b 4e f3 mov -0xd(%rsi),%rcx + 431d08: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 431d0c: 4c 89 5f eb mov %r11,-0x15(%rdi) + 431d10: 48 89 4f f3 mov %rcx,-0xd(%rdi) + 431d14: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 431d18: c3 retq + 431d19: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 431d20: 48 8b 4e f3 mov -0xd(%rsi),%rcx + 431d24: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 431d28: 48 89 4f f3 mov %rcx,-0xd(%rdi) + 431d2c: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 431d30: c3 retq + 431d31: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 431d36: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 431d3d: 00 00 00 + 431d40: 8b 56 fb mov -0x5(%rsi),%edx + 431d43: 8b 4e fc mov -0x4(%rsi),%ecx + 431d46: 89 57 fb mov %edx,-0x5(%rdi) + 431d49: 89 4f fc mov %ecx,-0x4(%rdi) + 431d4c: c3 retq + 431d4d: 0f 1f 00 nopl (%rax) + 431d50: f3 0f 6f 46 b2 movdqu -0x4e(%rsi),%xmm0 + 431d55: f3 0f 6f 4e c2 movdqu -0x3e(%rsi),%xmm1 + 431d5a: 4c 8b 46 d2 mov -0x2e(%rsi),%r8 + 431d5e: 4c 8b 4e da mov -0x26(%rsi),%r9 + 431d62: 4c 8b 56 e2 mov -0x1e(%rsi),%r10 + 431d66: 4c 8b 5e ea mov -0x16(%rsi),%r11 + 431d6a: 48 8b 4e f2 mov -0xe(%rsi),%rcx + 431d6e: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 431d72: f3 0f 7f 47 b2 movdqu %xmm0,-0x4e(%rdi) + 431d77: f3 0f 7f 4f c2 movdqu %xmm1,-0x3e(%rdi) + 431d7c: 4c 89 47 d2 mov %r8,-0x2e(%rdi) + 431d80: 4c 89 4f da mov %r9,-0x26(%rdi) + 431d84: 4c 89 57 e2 mov %r10,-0x1e(%rdi) + 431d88: 4c 89 5f ea mov %r11,-0x16(%rdi) + 431d8c: 48 89 4f f2 mov %rcx,-0xe(%rdi) + 431d90: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 431d94: c3 retq + 431d95: 90 nop + 431d96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 431d9d: 00 00 00 + 431da0: f3 0f 6f 46 ba movdqu -0x46(%rsi),%xmm0 + 431da5: f3 0f 6f 4e ca movdqu -0x36(%rsi),%xmm1 + 431daa: 4c 8b 4e da mov -0x26(%rsi),%r9 + 431dae: 4c 8b 56 e2 mov -0x1e(%rsi),%r10 + 431db2: 4c 8b 5e ea mov -0x16(%rsi),%r11 + 431db6: 48 8b 4e f2 mov -0xe(%rsi),%rcx + 431dba: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 431dbe: f3 0f 7f 47 ba movdqu %xmm0,-0x46(%rdi) + 431dc3: f3 0f 7f 4f ca movdqu %xmm1,-0x36(%rdi) + 431dc8: 4c 89 4f da mov %r9,-0x26(%rdi) + 431dcc: 4c 89 57 e2 mov %r10,-0x1e(%rdi) + 431dd0: 4c 89 5f ea mov %r11,-0x16(%rdi) + 431dd4: 48 89 4f f2 mov %rcx,-0xe(%rdi) + 431dd8: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 431ddc: c3 retq + 431ddd: 0f 1f 00 nopl (%rax) + 431de0: f3 0f 6f 46 c2 movdqu -0x3e(%rsi),%xmm0 + 431de5: 4c 8b 46 d2 mov -0x2e(%rsi),%r8 + 431de9: 4c 8b 4e da mov -0x26(%rsi),%r9 + 431ded: 4c 8b 56 e2 mov -0x1e(%rsi),%r10 + 431df1: 4c 8b 5e ea mov -0x16(%rsi),%r11 + 431df5: 48 8b 4e f2 mov -0xe(%rsi),%rcx + 431df9: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 431dfd: f3 0f 7f 47 c2 movdqu %xmm0,-0x3e(%rdi) + 431e02: 4c 89 47 d2 mov %r8,-0x2e(%rdi) + 431e06: 4c 89 4f da mov %r9,-0x26(%rdi) + 431e0a: 4c 89 57 e2 mov %r10,-0x1e(%rdi) + 431e0e: 4c 89 5f ea mov %r11,-0x16(%rdi) + 431e12: 48 89 4f f2 mov %rcx,-0xe(%rdi) + 431e16: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 431e1a: c3 retq + 431e1b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 431e20: f3 0f 6f 46 ca movdqu -0x36(%rsi),%xmm0 + 431e25: 4c 8b 4e da mov -0x26(%rsi),%r9 + 431e29: 4c 8b 56 e2 mov -0x1e(%rsi),%r10 + 431e2d: 4c 8b 5e ea mov -0x16(%rsi),%r11 + 431e31: 48 8b 4e f2 mov -0xe(%rsi),%rcx + 431e35: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 431e39: f3 0f 7f 47 ca movdqu %xmm0,-0x36(%rdi) + 431e3e: 4c 89 4f da mov %r9,-0x26(%rdi) + 431e42: 4c 89 57 e2 mov %r10,-0x1e(%rdi) + 431e46: 4c 89 5f ea mov %r11,-0x16(%rdi) + 431e4a: 48 89 4f f2 mov %rcx,-0xe(%rdi) + 431e4e: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 431e52: c3 retq + 431e53: 0f 1f 00 nopl (%rax) + 431e56: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 431e5d: 00 00 00 + 431e60: 4c 8b 46 d2 mov -0x2e(%rsi),%r8 + 431e64: 4c 8b 4e da mov -0x26(%rsi),%r9 + 431e68: 4c 8b 56 e2 mov -0x1e(%rsi),%r10 + 431e6c: 4c 8b 5e ea mov -0x16(%rsi),%r11 + 431e70: 48 8b 4e f2 mov -0xe(%rsi),%rcx + 431e74: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 431e78: 4c 89 47 d2 mov %r8,-0x2e(%rdi) + 431e7c: 4c 89 4f da mov %r9,-0x26(%rdi) + 431e80: 4c 89 57 e2 mov %r10,-0x1e(%rdi) + 431e84: 4c 89 5f ea mov %r11,-0x16(%rdi) + 431e88: 48 89 4f f2 mov %rcx,-0xe(%rdi) + 431e8c: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 431e90: c3 retq + 431e91: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 431e96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 431e9d: 00 00 00 + 431ea0: 4c 8b 4e da mov -0x26(%rsi),%r9 + 431ea4: 4c 8b 56 e2 mov -0x1e(%rsi),%r10 + 431ea8: 4c 8b 5e ea mov -0x16(%rsi),%r11 + 431eac: 48 8b 4e f2 mov -0xe(%rsi),%rcx + 431eb0: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 431eb4: 4c 89 4f da mov %r9,-0x26(%rdi) + 431eb8: 4c 89 57 e2 mov %r10,-0x1e(%rdi) + 431ebc: 4c 89 5f ea mov %r11,-0x16(%rdi) + 431ec0: 48 89 4f f2 mov %rcx,-0xe(%rdi) + 431ec4: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 431ec8: c3 retq + 431ec9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 431ed0: 4c 8b 56 e2 mov -0x1e(%rsi),%r10 + 431ed4: 4c 8b 5e ea mov -0x16(%rsi),%r11 + 431ed8: 48 8b 4e f2 mov -0xe(%rsi),%rcx + 431edc: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 431ee0: 4c 89 57 e2 mov %r10,-0x1e(%rdi) + 431ee4: 4c 89 5f ea mov %r11,-0x16(%rdi) + 431ee8: 48 89 4f f2 mov %rcx,-0xe(%rdi) + 431eec: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 431ef0: c3 retq + 431ef1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 431ef6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 431efd: 00 00 00 + 431f00: 4c 8b 5e ea mov -0x16(%rsi),%r11 + 431f04: 48 8b 4e f2 mov -0xe(%rsi),%rcx + 431f08: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 431f0c: 4c 89 5f ea mov %r11,-0x16(%rdi) + 431f10: 48 89 4f f2 mov %rcx,-0xe(%rdi) + 431f14: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 431f18: c3 retq + 431f19: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 431f20: 48 8b 4e f2 mov -0xe(%rsi),%rcx + 431f24: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 431f28: 48 89 4f f2 mov %rcx,-0xe(%rdi) + 431f2c: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 431f30: c3 retq + 431f31: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 431f36: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 431f3d: 00 00 00 + 431f40: 8b 56 fa mov -0x6(%rsi),%edx + 431f43: 8b 4e fc mov -0x4(%rsi),%ecx + 431f46: 89 57 fa mov %edx,-0x6(%rdi) + 431f49: 89 4f fc mov %ecx,-0x4(%rdi) + 431f4c: c3 retq + 431f4d: 0f 1f 00 nopl (%rax) + 431f50: f3 0f 6f 46 b1 movdqu -0x4f(%rsi),%xmm0 + 431f55: f3 0f 6f 4e c1 movdqu -0x3f(%rsi),%xmm1 + 431f5a: 4c 8b 46 d1 mov -0x2f(%rsi),%r8 + 431f5e: 4c 8b 4e d9 mov -0x27(%rsi),%r9 + 431f62: 4c 8b 56 e1 mov -0x1f(%rsi),%r10 + 431f66: 4c 8b 5e e9 mov -0x17(%rsi),%r11 + 431f6a: 48 8b 4e f1 mov -0xf(%rsi),%rcx + 431f6e: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 431f72: f3 0f 7f 47 b1 movdqu %xmm0,-0x4f(%rdi) + 431f77: f3 0f 7f 4f c1 movdqu %xmm1,-0x3f(%rdi) + 431f7c: 4c 89 47 d1 mov %r8,-0x2f(%rdi) + 431f80: 4c 89 4f d9 mov %r9,-0x27(%rdi) + 431f84: 4c 89 57 e1 mov %r10,-0x1f(%rdi) + 431f88: 4c 89 5f e9 mov %r11,-0x17(%rdi) + 431f8c: 48 89 4f f1 mov %rcx,-0xf(%rdi) + 431f90: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 431f94: c3 retq + 431f95: 90 nop + 431f96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 431f9d: 00 00 00 + 431fa0: f3 0f 6f 46 b9 movdqu -0x47(%rsi),%xmm0 + 431fa5: f3 0f 6f 4e c9 movdqu -0x37(%rsi),%xmm1 + 431faa: 4c 8b 4e d9 mov -0x27(%rsi),%r9 + 431fae: 4c 8b 56 e1 mov -0x1f(%rsi),%r10 + 431fb2: 4c 8b 5e e9 mov -0x17(%rsi),%r11 + 431fb6: 48 8b 4e f1 mov -0xf(%rsi),%rcx + 431fba: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 431fbe: f3 0f 7f 47 b9 movdqu %xmm0,-0x47(%rdi) + 431fc3: f3 0f 7f 4f c9 movdqu %xmm1,-0x37(%rdi) + 431fc8: 4c 89 4f d9 mov %r9,-0x27(%rdi) + 431fcc: 4c 89 57 e1 mov %r10,-0x1f(%rdi) + 431fd0: 4c 89 5f e9 mov %r11,-0x17(%rdi) + 431fd4: 48 89 4f f1 mov %rcx,-0xf(%rdi) + 431fd8: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 431fdc: c3 retq + 431fdd: 0f 1f 00 nopl (%rax) + 431fe0: f3 0f 6f 46 c1 movdqu -0x3f(%rsi),%xmm0 + 431fe5: 4c 8b 46 d1 mov -0x2f(%rsi),%r8 + 431fe9: 4c 8b 4e d9 mov -0x27(%rsi),%r9 + 431fed: 4c 8b 56 e1 mov -0x1f(%rsi),%r10 + 431ff1: 4c 8b 5e e9 mov -0x17(%rsi),%r11 + 431ff5: 48 8b 4e f1 mov -0xf(%rsi),%rcx + 431ff9: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 431ffd: f3 0f 7f 47 c1 movdqu %xmm0,-0x3f(%rdi) + 432002: 4c 89 47 d1 mov %r8,-0x2f(%rdi) + 432006: 4c 89 4f d9 mov %r9,-0x27(%rdi) + 43200a: 4c 89 57 e1 mov %r10,-0x1f(%rdi) + 43200e: 4c 89 5f e9 mov %r11,-0x17(%rdi) + 432012: 48 89 4f f1 mov %rcx,-0xf(%rdi) + 432016: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 43201a: c3 retq + 43201b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 432020: f3 0f 6f 46 c9 movdqu -0x37(%rsi),%xmm0 + 432025: 4c 8b 4e d9 mov -0x27(%rsi),%r9 + 432029: 4c 8b 56 e1 mov -0x1f(%rsi),%r10 + 43202d: 4c 8b 5e e9 mov -0x17(%rsi),%r11 + 432031: 48 8b 4e f1 mov -0xf(%rsi),%rcx + 432035: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 432039: f3 0f 7f 47 c9 movdqu %xmm0,-0x37(%rdi) + 43203e: 4c 89 4f d9 mov %r9,-0x27(%rdi) + 432042: 4c 89 57 e1 mov %r10,-0x1f(%rdi) + 432046: 4c 89 5f e9 mov %r11,-0x17(%rdi) + 43204a: 48 89 4f f1 mov %rcx,-0xf(%rdi) + 43204e: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 432052: c3 retq + 432053: 0f 1f 00 nopl (%rax) + 432056: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43205d: 00 00 00 + 432060: 4c 8b 46 d1 mov -0x2f(%rsi),%r8 + 432064: 4c 8b 4e d9 mov -0x27(%rsi),%r9 + 432068: 4c 8b 56 e1 mov -0x1f(%rsi),%r10 + 43206c: 4c 8b 5e e9 mov -0x17(%rsi),%r11 + 432070: 48 8b 4e f1 mov -0xf(%rsi),%rcx + 432074: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 432078: 4c 89 47 d1 mov %r8,-0x2f(%rdi) + 43207c: 4c 89 4f d9 mov %r9,-0x27(%rdi) + 432080: 4c 89 57 e1 mov %r10,-0x1f(%rdi) + 432084: 4c 89 5f e9 mov %r11,-0x17(%rdi) + 432088: 48 89 4f f1 mov %rcx,-0xf(%rdi) + 43208c: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 432090: c3 retq + 432091: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 432096: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43209d: 00 00 00 + 4320a0: 4c 8b 4e d9 mov -0x27(%rsi),%r9 + 4320a4: 4c 8b 56 e1 mov -0x1f(%rsi),%r10 + 4320a8: 4c 8b 5e e9 mov -0x17(%rsi),%r11 + 4320ac: 48 8b 4e f1 mov -0xf(%rsi),%rcx + 4320b0: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 4320b4: 4c 89 4f d9 mov %r9,-0x27(%rdi) + 4320b8: 4c 89 57 e1 mov %r10,-0x1f(%rdi) + 4320bc: 4c 89 5f e9 mov %r11,-0x17(%rdi) + 4320c0: 48 89 4f f1 mov %rcx,-0xf(%rdi) + 4320c4: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 4320c8: c3 retq + 4320c9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4320d0: 4c 8b 56 e1 mov -0x1f(%rsi),%r10 + 4320d4: 4c 8b 5e e9 mov -0x17(%rsi),%r11 + 4320d8: 48 8b 4e f1 mov -0xf(%rsi),%rcx + 4320dc: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 4320e0: 4c 89 57 e1 mov %r10,-0x1f(%rdi) + 4320e4: 4c 89 5f e9 mov %r11,-0x17(%rdi) + 4320e8: 48 89 4f f1 mov %rcx,-0xf(%rdi) + 4320ec: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 4320f0: c3 retq + 4320f1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4320f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4320fd: 00 00 00 + 432100: 4c 8b 5e e9 mov -0x17(%rsi),%r11 + 432104: 48 8b 4e f1 mov -0xf(%rsi),%rcx + 432108: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 43210c: 4c 89 5f e9 mov %r11,-0x17(%rdi) + 432110: 48 89 4f f1 mov %rcx,-0xf(%rdi) + 432114: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 432118: c3 retq + 432119: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 432120: 48 8b 4e f1 mov -0xf(%rsi),%rcx + 432124: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 432128: 48 89 4f f1 mov %rcx,-0xf(%rdi) + 43212c: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 432130: c3 retq + 432131: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 432136: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43213d: 00 00 00 + 432140: 8b 56 f9 mov -0x7(%rsi),%edx + 432143: 8b 4e fc mov -0x4(%rsi),%ecx + 432146: 89 57 f9 mov %edx,-0x7(%rdi) + 432149: 89 4f fc mov %ecx,-0x4(%rdi) + 43214c: c3 retq + 43214d: 0f 1f 00 nopl (%rax) + 432150: f3 0f 6f 0e movdqu (%rsi),%xmm1 + 432154: 48 8d 76 10 lea 0x10(%rsi),%rsi + 432158: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 43215d: 66 0f e7 0f movntdq %xmm1,(%rdi) + 432161: 48 8d 7f 10 lea 0x10(%rdi),%rdi + 432165: 48 8d 92 70 ff ff ff lea -0x90(%rdx),%rdx + 43216c: 49 89 f1 mov %rsi,%r9 + 43216f: 49 29 f9 sub %rdi,%r9 + 432172: 49 39 d1 cmp %rdx,%r9 + 432175: 73 0d jae 432184 <__memmove_ssse3+0x2834> + 432177: 48 c1 e1 02 shl $0x2,%rcx + 43217b: 48 39 ca cmp %rcx,%rdx + 43217e: 0f 82 cc 00 00 00 jb 432250 <__memmove_ssse3+0x2900> + 432184: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 432188: f3 0f 6f 4e 10 movdqu 0x10(%rsi),%xmm1 + 43218d: f3 0f 6f 56 20 movdqu 0x20(%rsi),%xmm2 + 432192: f3 0f 6f 5e 30 movdqu 0x30(%rsi),%xmm3 + 432197: f3 0f 6f 66 40 movdqu 0x40(%rsi),%xmm4 + 43219c: f3 0f 6f 6e 50 movdqu 0x50(%rsi),%xmm5 + 4321a1: f3 0f 6f 76 60 movdqu 0x60(%rsi),%xmm6 + 4321a6: f3 0f 6f 7e 70 movdqu 0x70(%rsi),%xmm7 + 4321ab: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi + 4321b2: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 4321b9: 66 0f e7 07 movntdq %xmm0,(%rdi) + 4321bd: 66 0f e7 4f 10 movntdq %xmm1,0x10(%rdi) + 4321c2: 66 0f e7 57 20 movntdq %xmm2,0x20(%rdi) + 4321c7: 66 0f e7 5f 30 movntdq %xmm3,0x30(%rdi) + 4321cc: 66 0f e7 67 40 movntdq %xmm4,0x40(%rdi) + 4321d1: 66 0f e7 6f 50 movntdq %xmm5,0x50(%rdi) + 4321d6: 66 0f e7 77 60 movntdq %xmm6,0x60(%rdi) + 4321db: 66 0f e7 7f 70 movntdq %xmm7,0x70(%rdi) + 4321e0: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi + 4321e7: 73 9b jae 432184 <__memmove_ssse3+0x2834> + 4321e9: 48 83 fa c0 cmp $0xffffffffffffffc0,%rdx + 4321ed: 48 8d 92 80 00 00 00 lea 0x80(%rdx),%rdx + 4321f4: 7c 32 jl 432228 <__memmove_ssse3+0x28d8> + 4321f6: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 4321fa: f3 0f 6f 4e 10 movdqu 0x10(%rsi),%xmm1 + 4321ff: f3 0f 6f 56 20 movdqu 0x20(%rsi),%xmm2 + 432204: f3 0f 6f 5e 30 movdqu 0x30(%rsi),%xmm3 + 432209: 48 8d 76 40 lea 0x40(%rsi),%rsi + 43220d: 66 0f e7 07 movntdq %xmm0,(%rdi) + 432211: 66 0f e7 4f 10 movntdq %xmm1,0x10(%rdi) + 432216: 66 0f e7 57 20 movntdq %xmm2,0x20(%rdi) + 43221b: 66 0f e7 5f 30 movntdq %xmm3,0x30(%rdi) + 432220: 48 8d 7f 40 lea 0x40(%rdi),%rdi + 432224: 48 83 ea 40 sub $0x40,%rdx + 432228: 48 01 d6 add %rdx,%rsi + 43222b: 48 01 d7 add %rdx,%rdi + 43222e: 0f ae f8 sfence + 432231: 4c 8d 1d 78 11 07 00 lea 0x71178(%rip),%r11 # 4a33b0 + 432238: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 43223c: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 432240: ff e2 jmpq *%rdx + 432242: 0f 0b ud2 + 432244: 66 90 xchg %ax,%ax + 432246: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43224d: 00 00 00 + 432250: 0f 18 8e c0 01 00 00 prefetcht0 0x1c0(%rsi) + 432257: 0f 18 8e 00 02 00 00 prefetcht0 0x200(%rsi) + 43225e: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 432262: f3 0f 6f 4e 10 movdqu 0x10(%rsi),%xmm1 + 432267: f3 0f 6f 56 20 movdqu 0x20(%rsi),%xmm2 + 43226c: f3 0f 6f 5e 30 movdqu 0x30(%rsi),%xmm3 + 432271: f3 0f 6f 66 40 movdqu 0x40(%rsi),%xmm4 + 432276: f3 0f 6f 6e 50 movdqu 0x50(%rsi),%xmm5 + 43227b: f3 0f 6f 76 60 movdqu 0x60(%rsi),%xmm6 + 432280: f3 0f 6f 7e 70 movdqu 0x70(%rsi),%xmm7 + 432285: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi + 43228c: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 432293: 0f 29 07 movaps %xmm0,(%rdi) + 432296: 0f 29 4f 10 movaps %xmm1,0x10(%rdi) + 43229a: 0f 29 57 20 movaps %xmm2,0x20(%rdi) + 43229e: 0f 29 5f 30 movaps %xmm3,0x30(%rdi) + 4322a2: 0f 29 67 40 movaps %xmm4,0x40(%rdi) + 4322a6: 0f 29 6f 50 movaps %xmm5,0x50(%rdi) + 4322aa: 0f 29 77 60 movaps %xmm6,0x60(%rdi) + 4322ae: 0f 29 7f 70 movaps %xmm7,0x70(%rdi) + 4322b2: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi + 4322b9: 73 95 jae 432250 <__memmove_ssse3+0x2900> + 4322bb: 48 83 fa c0 cmp $0xffffffffffffffc0,%rdx + 4322bf: 48 8d 92 80 00 00 00 lea 0x80(%rdx),%rdx + 4322c6: 7c 2e jl 4322f6 <__memmove_ssse3+0x29a6> + 4322c8: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 4322cc: f3 0f 6f 4e 10 movdqu 0x10(%rsi),%xmm1 + 4322d1: f3 0f 6f 56 20 movdqu 0x20(%rsi),%xmm2 + 4322d6: f3 0f 6f 5e 30 movdqu 0x30(%rsi),%xmm3 + 4322db: 48 8d 76 40 lea 0x40(%rsi),%rsi + 4322df: 0f 29 07 movaps %xmm0,(%rdi) + 4322e2: 0f 29 4f 10 movaps %xmm1,0x10(%rdi) + 4322e6: 0f 29 57 20 movaps %xmm2,0x20(%rdi) + 4322ea: 0f 29 5f 30 movaps %xmm3,0x30(%rdi) + 4322ee: 48 8d 7f 40 lea 0x40(%rdi),%rdi + 4322f2: 48 83 ea 40 sub $0x40,%rdx + 4322f6: 48 01 d6 add %rdx,%rsi + 4322f9: 48 01 d7 add %rdx,%rdi + 4322fc: 4c 8d 1d ad 10 07 00 lea 0x710ad(%rip),%r11 # 4a33b0 + 432303: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 432307: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 43230b: ff e2 jmpq *%rdx + 43230d: 0f 0b ud2 + 43230f: 90 nop + 432310: f3 0f 6f 4e f0 movdqu -0x10(%rsi),%xmm1 + 432315: 48 8d 76 f0 lea -0x10(%rsi),%rsi + 432319: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 43231e: 66 0f 7f 4f f0 movdqa %xmm1,-0x10(%rdi) + 432323: 48 8d 7f f0 lea -0x10(%rdi),%rdi + 432327: 48 8d 92 70 ff ff ff lea -0x90(%rdx),%rdx + 43232e: 49 89 f9 mov %rdi,%r9 + 432331: 49 29 f1 sub %rsi,%r9 + 432334: 49 39 d1 cmp %rdx,%r9 + 432337: 73 09 jae 432342 <__memmove_ssse3+0x29f2> + 432339: 49 39 c9 cmp %rcx,%r9 + 43233c: 0f 82 be 00 00 00 jb 432400 <__memmove_ssse3+0x2ab0> + 432342: f3 0f 6f 46 f0 movdqu -0x10(%rsi),%xmm0 + 432347: f3 0f 6f 4e e0 movdqu -0x20(%rsi),%xmm1 + 43234c: f3 0f 6f 56 d0 movdqu -0x30(%rsi),%xmm2 + 432351: f3 0f 6f 5e c0 movdqu -0x40(%rsi),%xmm3 + 432356: f3 0f 6f 66 b0 movdqu -0x50(%rsi),%xmm4 + 43235b: f3 0f 6f 6e a0 movdqu -0x60(%rsi),%xmm5 + 432360: f3 0f 6f 76 90 movdqu -0x70(%rsi),%xmm6 + 432365: f3 0f 6f 7e 80 movdqu -0x80(%rsi),%xmm7 + 43236a: 48 8d 76 80 lea -0x80(%rsi),%rsi + 43236e: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 432375: 66 0f e7 47 f0 movntdq %xmm0,-0x10(%rdi) + 43237a: 66 0f e7 4f e0 movntdq %xmm1,-0x20(%rdi) + 43237f: 66 0f e7 57 d0 movntdq %xmm2,-0x30(%rdi) + 432384: 66 0f e7 5f c0 movntdq %xmm3,-0x40(%rdi) + 432389: 66 0f e7 67 b0 movntdq %xmm4,-0x50(%rdi) + 43238e: 66 0f e7 6f a0 movntdq %xmm5,-0x60(%rdi) + 432393: 66 0f e7 77 90 movntdq %xmm6,-0x70(%rdi) + 432398: 66 0f e7 7f 80 movntdq %xmm7,-0x80(%rdi) + 43239d: 48 8d 7f 80 lea -0x80(%rdi),%rdi + 4323a1: 73 9f jae 432342 <__memmove_ssse3+0x29f2> + 4323a3: 48 83 fa c0 cmp $0xffffffffffffffc0,%rdx + 4323a7: 48 8d 92 80 00 00 00 lea 0x80(%rdx),%rdx + 4323ae: 7c 34 jl 4323e4 <__memmove_ssse3+0x2a94> + 4323b0: f3 0f 6f 46 f0 movdqu -0x10(%rsi),%xmm0 + 4323b5: f3 0f 6f 4e e0 movdqu -0x20(%rsi),%xmm1 + 4323ba: f3 0f 6f 56 d0 movdqu -0x30(%rsi),%xmm2 + 4323bf: f3 0f 6f 5e c0 movdqu -0x40(%rsi),%xmm3 + 4323c4: 48 8d 76 c0 lea -0x40(%rsi),%rsi + 4323c8: 66 0f e7 47 f0 movntdq %xmm0,-0x10(%rdi) + 4323cd: 66 0f e7 4f e0 movntdq %xmm1,-0x20(%rdi) + 4323d2: 66 0f e7 57 d0 movntdq %xmm2,-0x30(%rdi) + 4323d7: 66 0f e7 5f c0 movntdq %xmm3,-0x40(%rdi) + 4323dc: 48 8d 7f c0 lea -0x40(%rdi),%rdi + 4323e0: 48 83 ea 40 sub $0x40,%rdx + 4323e4: 0f ae f8 sfence + 4323e7: 4c 8d 1d c2 0f 07 00 lea 0x70fc2(%rip),%r11 # 4a33b0 + 4323ee: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 4323f2: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 4323f6: ff e2 jmpq *%rdx + 4323f8: 0f 0b ud2 + 4323fa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 432400: 0f 18 8e 40 fe ff ff prefetcht0 -0x1c0(%rsi) + 432407: 0f 18 8e 00 fe ff ff prefetcht0 -0x200(%rsi) + 43240e: f3 0f 6f 46 f0 movdqu -0x10(%rsi),%xmm0 + 432413: f3 0f 6f 4e e0 movdqu -0x20(%rsi),%xmm1 + 432418: f3 0f 6f 56 d0 movdqu -0x30(%rsi),%xmm2 + 43241d: f3 0f 6f 5e c0 movdqu -0x40(%rsi),%xmm3 + 432422: f3 0f 6f 66 b0 movdqu -0x50(%rsi),%xmm4 + 432427: f3 0f 6f 6e a0 movdqu -0x60(%rsi),%xmm5 + 43242c: f3 0f 6f 76 90 movdqu -0x70(%rsi),%xmm6 + 432431: f3 0f 6f 7e 80 movdqu -0x80(%rsi),%xmm7 + 432436: 48 8d 76 80 lea -0x80(%rsi),%rsi + 43243a: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 432441: 0f 29 47 f0 movaps %xmm0,-0x10(%rdi) + 432445: 0f 29 4f e0 movaps %xmm1,-0x20(%rdi) + 432449: 0f 29 57 d0 movaps %xmm2,-0x30(%rdi) + 43244d: 0f 29 5f c0 movaps %xmm3,-0x40(%rdi) + 432451: 0f 29 67 b0 movaps %xmm4,-0x50(%rdi) + 432455: 0f 29 6f a0 movaps %xmm5,-0x60(%rdi) + 432459: 0f 29 77 90 movaps %xmm6,-0x70(%rdi) + 43245d: 0f 29 7f 80 movaps %xmm7,-0x80(%rdi) + 432461: 48 8d 7f 80 lea -0x80(%rdi),%rdi + 432465: 73 99 jae 432400 <__memmove_ssse3+0x2ab0> + 432467: 48 83 fa c0 cmp $0xffffffffffffffc0,%rdx + 43246b: 48 8d 92 80 00 00 00 lea 0x80(%rdx),%rdx + 432472: 7c 30 jl 4324a4 <__memmove_ssse3+0x2b54> + 432474: f3 0f 6f 46 f0 movdqu -0x10(%rsi),%xmm0 + 432479: f3 0f 6f 4e e0 movdqu -0x20(%rsi),%xmm1 + 43247e: f3 0f 6f 56 d0 movdqu -0x30(%rsi),%xmm2 + 432483: f3 0f 6f 5e c0 movdqu -0x40(%rsi),%xmm3 + 432488: 48 8d 76 c0 lea -0x40(%rsi),%rsi + 43248c: 0f 29 47 f0 movaps %xmm0,-0x10(%rdi) + 432490: 0f 29 4f e0 movaps %xmm1,-0x20(%rdi) + 432494: 0f 29 57 d0 movaps %xmm2,-0x30(%rdi) + 432498: 0f 29 5f c0 movaps %xmm3,-0x40(%rdi) + 43249c: 48 8d 7f c0 lea -0x40(%rdi),%rdi + 4324a0: 48 83 ea 40 sub $0x40,%rdx + 4324a4: 4c 8d 1d 05 0f 07 00 lea 0x70f05(%rip),%r11 # 4a33b0 + 4324ab: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 4324af: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 4324b3: ff e2 jmpq *%rdx + 4324b5: 0f 0b ud2 + 4324b7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 4324be: 00 00 + +00000000004324c0 <__memmove_chk_avx_unaligned>: + 4324c0: 48 39 d1 cmp %rdx,%rcx + 4324c3: 0f 82 e7 05 01 00 jb 442ab0 <__chk_fail> + 4324c9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + +00000000004324d0 <__memmove_avx_unaligned>: + 4324d0: 48 89 f8 mov %rdi,%rax + 4324d3: 48 81 fa 00 01 00 00 cmp $0x100,%rdx + 4324da: 0f 83 c0 01 00 00 jae 4326a0 <__memmove_avx_unaligned+0x1d0> + 4324e0: 80 fa 10 cmp $0x10,%dl + 4324e3: 0f 82 67 01 00 00 jb 432650 <__memmove_avx_unaligned+0x180> + 4324e9: 80 fa 80 cmp $0x80,%dl + 4324ec: 0f 82 ae 00 00 00 jb 4325a0 <__memmove_avx_unaligned+0xd0> + 4324f2: c5 fa 6f 06 vmovdqu (%rsi),%xmm0 + 4324f6: 48 8d 0c 16 lea (%rsi,%rdx,1),%rcx + 4324fa: c5 fa 6f 4e 10 vmovdqu 0x10(%rsi),%xmm1 + 4324ff: c5 fa 6f 56 20 vmovdqu 0x20(%rsi),%xmm2 + 432504: c5 fa 6f 5e 30 vmovdqu 0x30(%rsi),%xmm3 + 432509: c5 fa 6f 66 40 vmovdqu 0x40(%rsi),%xmm4 + 43250e: c5 fa 6f 6e 50 vmovdqu 0x50(%rsi),%xmm5 + 432513: c5 fa 6f 76 60 vmovdqu 0x60(%rsi),%xmm6 + 432518: c5 fa 6f 7e 70 vmovdqu 0x70(%rsi),%xmm7 + 43251d: c5 7a 6f 41 80 vmovdqu -0x80(%rcx),%xmm8 + 432522: c5 7a 6f 49 90 vmovdqu -0x70(%rcx),%xmm9 + 432527: c5 7a 6f 51 a0 vmovdqu -0x60(%rcx),%xmm10 + 43252c: c5 7a 6f 59 b0 vmovdqu -0x50(%rcx),%xmm11 + 432531: c5 7a 6f 61 c0 vmovdqu -0x40(%rcx),%xmm12 + 432536: c5 7a 6f 69 d0 vmovdqu -0x30(%rcx),%xmm13 + 43253b: c5 7a 6f 71 e0 vmovdqu -0x20(%rcx),%xmm14 + 432540: c5 7a 6f 79 f0 vmovdqu -0x10(%rcx),%xmm15 + 432545: 48 8d 14 17 lea (%rdi,%rdx,1),%rdx + 432549: c5 fa 7f 07 vmovdqu %xmm0,(%rdi) + 43254d: c5 fa 7f 4f 10 vmovdqu %xmm1,0x10(%rdi) + 432552: c5 fa 7f 57 20 vmovdqu %xmm2,0x20(%rdi) + 432557: c5 fa 7f 5f 30 vmovdqu %xmm3,0x30(%rdi) + 43255c: c5 fa 7f 67 40 vmovdqu %xmm4,0x40(%rdi) + 432561: c5 fa 7f 6f 50 vmovdqu %xmm5,0x50(%rdi) + 432566: c5 fa 7f 77 60 vmovdqu %xmm6,0x60(%rdi) + 43256b: c5 fa 7f 7f 70 vmovdqu %xmm7,0x70(%rdi) + 432570: c5 7a 7f 42 80 vmovdqu %xmm8,-0x80(%rdx) + 432575: c5 7a 7f 4a 90 vmovdqu %xmm9,-0x70(%rdx) + 43257a: c5 7a 7f 52 a0 vmovdqu %xmm10,-0x60(%rdx) + 43257f: c5 7a 7f 5a b0 vmovdqu %xmm11,-0x50(%rdx) + 432584: c5 7a 7f 62 c0 vmovdqu %xmm12,-0x40(%rdx) + 432589: c5 7a 7f 6a d0 vmovdqu %xmm13,-0x30(%rdx) + 43258e: c5 7a 7f 72 e0 vmovdqu %xmm14,-0x20(%rdx) + 432593: c5 7a 7f 7a f0 vmovdqu %xmm15,-0x10(%rdx) + 432598: c3 retq + 432599: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4325a0: 80 fa 40 cmp $0x40,%dl + 4325a3: 72 5b jb 432600 <__memmove_avx_unaligned+0x130> + 4325a5: c5 fa 6f 06 vmovdqu (%rsi),%xmm0 + 4325a9: 48 8d 0c 16 lea (%rsi,%rdx,1),%rcx + 4325ad: c5 fa 6f 4e 10 vmovdqu 0x10(%rsi),%xmm1 + 4325b2: c5 fa 6f 56 20 vmovdqu 0x20(%rsi),%xmm2 + 4325b7: 48 8d 14 17 lea (%rdi,%rdx,1),%rdx + 4325bb: c5 fa 6f 5e 30 vmovdqu 0x30(%rsi),%xmm3 + 4325c0: c5 fa 6f 61 c0 vmovdqu -0x40(%rcx),%xmm4 + 4325c5: c5 fa 6f 69 d0 vmovdqu -0x30(%rcx),%xmm5 + 4325ca: c5 fa 6f 71 e0 vmovdqu -0x20(%rcx),%xmm6 + 4325cf: c5 fa 6f 79 f0 vmovdqu -0x10(%rcx),%xmm7 + 4325d4: c5 fa 7f 07 vmovdqu %xmm0,(%rdi) + 4325d8: c5 fa 7f 4f 10 vmovdqu %xmm1,0x10(%rdi) + 4325dd: c5 fa 7f 57 20 vmovdqu %xmm2,0x20(%rdi) + 4325e2: c5 fa 7f 5f 30 vmovdqu %xmm3,0x30(%rdi) + 4325e7: c5 fa 7f 62 c0 vmovdqu %xmm4,-0x40(%rdx) + 4325ec: c5 fa 7f 6a d0 vmovdqu %xmm5,-0x30(%rdx) + 4325f1: c5 fa 7f 72 e0 vmovdqu %xmm6,-0x20(%rdx) + 4325f6: c5 fa 7f 7a f0 vmovdqu %xmm7,-0x10(%rdx) + 4325fb: c3 retq + 4325fc: 0f 1f 40 00 nopl 0x0(%rax) + 432600: 80 fa 20 cmp $0x20,%dl + 432603: 72 2b jb 432630 <__memmove_avx_unaligned+0x160> + 432605: c5 fa 6f 06 vmovdqu (%rsi),%xmm0 + 432609: c5 fa 6f 4e 10 vmovdqu 0x10(%rsi),%xmm1 + 43260e: c5 fa 6f 74 16 e0 vmovdqu -0x20(%rsi,%rdx,1),%xmm6 + 432614: c5 fa 6f 7c 16 f0 vmovdqu -0x10(%rsi,%rdx,1),%xmm7 + 43261a: c5 fa 7f 07 vmovdqu %xmm0,(%rdi) + 43261e: c5 fa 7f 4f 10 vmovdqu %xmm1,0x10(%rdi) + 432623: c5 fa 7f 74 17 e0 vmovdqu %xmm6,-0x20(%rdi,%rdx,1) + 432629: c5 fa 7f 7c 17 f0 vmovdqu %xmm7,-0x10(%rdi,%rdx,1) + 43262f: c3 retq + 432630: c5 fa 6f 06 vmovdqu (%rsi),%xmm0 + 432634: c5 fa 6f 7c 16 f0 vmovdqu -0x10(%rsi,%rdx,1),%xmm7 + 43263a: c5 fa 7f 07 vmovdqu %xmm0,(%rdi) + 43263e: c5 fa 7f 7c 17 f0 vmovdqu %xmm7,-0x10(%rdi,%rdx,1) + 432644: c3 retq + 432645: 90 nop + 432646: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43264d: 00 00 00 + 432650: 80 fa 08 cmp $0x8,%dl + 432653: 72 1b jb 432670 <__memmove_avx_unaligned+0x1a0> + 432655: 48 8b 4c 16 f8 mov -0x8(%rsi,%rdx,1),%rcx + 43265a: 48 8b 36 mov (%rsi),%rsi + 43265d: 48 89 37 mov %rsi,(%rdi) + 432660: 48 89 4c 17 f8 mov %rcx,-0x8(%rdi,%rdx,1) + 432665: c3 retq + 432666: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43266d: 00 00 00 + 432670: 80 fa 04 cmp $0x4,%dl + 432673: 72 0d jb 432682 <__memmove_avx_unaligned+0x1b2> + 432675: 8b 4c 16 fc mov -0x4(%rsi,%rdx,1),%ecx + 432679: 8b 36 mov (%rsi),%esi + 43267b: 89 37 mov %esi,(%rdi) + 43267d: 89 4c 17 fc mov %ecx,-0x4(%rdi,%rdx,1) + 432681: c3 retq + 432682: 80 fa 01 cmp $0x1,%dl + 432685: 76 11 jbe 432698 <__memmove_avx_unaligned+0x1c8> + 432687: 66 8b 4c 16 fe mov -0x2(%rsi,%rdx,1),%cx + 43268c: 66 8b 36 mov (%rsi),%si + 43268f: 66 89 37 mov %si,(%rdi) + 432692: 66 89 4c 17 fe mov %cx,-0x2(%rdi,%rdx,1) + 432697: c3 retq + 432698: 72 04 jb 43269e <__memmove_avx_unaligned+0x1ce> + 43269a: 8a 0e mov (%rsi),%cl + 43269c: 88 0f mov %cl,(%rdi) + 43269e: c3 retq + 43269f: 90 nop + 4326a0: 48 89 f9 mov %rdi,%rcx + 4326a3: 48 29 f1 sub %rsi,%rcx + 4326a6: 48 39 d1 cmp %rdx,%rcx + 4326a9: 0f 82 c1 01 00 00 jb 432870 <__memmove_avx_unaligned+0x3a0> + 4326af: 48 81 fa 00 08 00 00 cmp $0x800,%rdx + 4326b6: 0f 83 c4 00 00 00 jae 432780 <__memmove_avx_unaligned+0x2b0> + 4326bc: 49 89 c0 mov %rax,%r8 + 4326bf: 48 8d 0c 16 lea (%rsi,%rdx,1),%rcx + 4326c3: 49 89 fa mov %rdi,%r10 + 4326c6: c5 fa 6f 69 80 vmovdqu -0x80(%rcx),%xmm5 + 4326cb: c5 fa 6f 71 90 vmovdqu -0x70(%rcx),%xmm6 + 4326d0: 48 c7 c0 80 00 00 00 mov $0x80,%rax + 4326d7: 48 83 e7 e0 and $0xffffffffffffffe0,%rdi + 4326db: 48 83 c7 20 add $0x20,%rdi + 4326df: c5 fa 6f 79 a0 vmovdqu -0x60(%rcx),%xmm7 + 4326e4: c5 7a 6f 41 b0 vmovdqu -0x50(%rcx),%xmm8 + 4326e9: 49 89 fb mov %rdi,%r11 + 4326ec: 4d 29 d3 sub %r10,%r11 + 4326ef: c5 7a 6f 49 c0 vmovdqu -0x40(%rcx),%xmm9 + 4326f4: c5 7a 6f 51 d0 vmovdqu -0x30(%rcx),%xmm10 + 4326f9: 4c 29 da sub %r11,%rdx + 4326fc: c5 7a 6f 59 e0 vmovdqu -0x20(%rcx),%xmm11 + 432701: c5 7a 6f 61 f0 vmovdqu -0x10(%rcx),%xmm12 + 432706: c5 fe 6f 26 vmovdqu (%rsi),%ymm4 + 43270a: 4c 01 de add %r11,%rsi + 43270d: 29 c2 sub %eax,%edx + 43270f: c5 fe 6f 06 vmovdqu (%rsi),%ymm0 + 432713: c5 fe 6f 4e 20 vmovdqu 0x20(%rsi),%ymm1 + 432718: c5 fe 6f 56 40 vmovdqu 0x40(%rsi),%ymm2 + 43271d: c5 fe 6f 5e 60 vmovdqu 0x60(%rsi),%ymm3 + 432722: 48 01 c6 add %rax,%rsi + 432725: c5 fd 7f 07 vmovdqa %ymm0,(%rdi) + 432729: c5 fd 7f 4f 20 vmovdqa %ymm1,0x20(%rdi) + 43272e: c5 fd 7f 57 40 vmovdqa %ymm2,0x40(%rdi) + 432733: c5 fd 7f 5f 60 vmovdqa %ymm3,0x60(%rdi) + 432738: 48 01 c7 add %rax,%rdi + 43273b: 29 c2 sub %eax,%edx + 43273d: 73 d0 jae 43270f <__memmove_avx_unaligned+0x23f> + 43273f: 01 c2 add %eax,%edx + 432741: 48 01 fa add %rdi,%rdx + 432744: c4 c1 7e 7f 22 vmovdqu %ymm4,(%r10) + 432749: c5 f8 77 vzeroupper + 43274c: c5 fa 7f 6a 80 vmovdqu %xmm5,-0x80(%rdx) + 432751: c5 fa 7f 72 90 vmovdqu %xmm6,-0x70(%rdx) + 432756: c5 fa 7f 7a a0 vmovdqu %xmm7,-0x60(%rdx) + 43275b: c5 7a 7f 42 b0 vmovdqu %xmm8,-0x50(%rdx) + 432760: c5 7a 7f 4a c0 vmovdqu %xmm9,-0x40(%rdx) + 432765: c5 7a 7f 52 d0 vmovdqu %xmm10,-0x30(%rdx) + 43276a: c5 7a 7f 5a e0 vmovdqu %xmm11,-0x20(%rdx) + 43276f: c5 7a 7f 62 f0 vmovdqu %xmm12,-0x10(%rdx) + 432774: 4c 89 c0 mov %r8,%rax + 432777: c3 retq + 432778: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 43277f: 00 + 432780: 48 8b 0d 29 89 29 00 mov 0x298929(%rip),%rcx # 6cb0b0 <__x86_shared_cache_size_half> + 432787: 48 c1 e1 03 shl $0x3,%rcx + 43278b: 48 39 ca cmp %rcx,%rdx + 43278e: 73 10 jae 4327a0 <__memmove_avx_unaligned+0x2d0> + 432790: 48 89 d1 mov %rdx,%rcx + 432793: 48 89 d1 mov %rdx,%rcx + 432796: f3 a4 rep movsb %ds:(%rsi),%es:(%rdi) + 432798: c3 retq + 432799: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4327a0: 48 8d 0c 16 lea (%rsi,%rdx,1),%rcx + 4327a4: c5 fe 6f 26 vmovdqu (%rsi),%ymm4 + 4327a8: c5 fa 6f 6c 16 80 vmovdqu -0x80(%rsi,%rdx,1),%xmm5 + 4327ae: c5 fa 6f 71 90 vmovdqu -0x70(%rcx),%xmm6 + 4327b3: c5 fa 6f 79 a0 vmovdqu -0x60(%rcx),%xmm7 + 4327b8: c5 7a 6f 41 b0 vmovdqu -0x50(%rcx),%xmm8 + 4327bd: c5 7a 6f 49 c0 vmovdqu -0x40(%rcx),%xmm9 + 4327c2: c5 7a 6f 51 d0 vmovdqu -0x30(%rcx),%xmm10 + 4327c7: c5 7a 6f 59 e0 vmovdqu -0x20(%rcx),%xmm11 + 4327cc: c5 7a 6f 61 f0 vmovdqu -0x10(%rcx),%xmm12 + 4327d1: 49 89 f8 mov %rdi,%r8 + 4327d4: 48 83 e7 e0 and $0xffffffffffffffe0,%rdi + 4327d8: 48 83 c7 20 add $0x20,%rdi + 4327dc: 49 89 fa mov %rdi,%r10 + 4327df: 4d 29 c2 sub %r8,%r10 + 4327e2: 4c 29 d2 sub %r10,%rdx + 4327e5: 4c 01 d6 add %r10,%rsi + 4327e8: 48 8d 0c 17 lea (%rdi,%rdx,1),%rcx + 4327ec: 48 83 c2 80 add $0xffffffffffffff80,%rdx + 4327f0: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) + 4327f7: 0f 18 86 80 02 00 00 prefetchnta 0x280(%rsi) + 4327fe: c5 fe 6f 06 vmovdqu (%rsi),%ymm0 + 432802: c5 fe 6f 4e 20 vmovdqu 0x20(%rsi),%ymm1 + 432807: c5 fe 6f 56 40 vmovdqu 0x40(%rsi),%ymm2 + 43280c: c5 fe 6f 5e 60 vmovdqu 0x60(%rsi),%ymm3 + 432811: 48 83 ee 80 sub $0xffffffffffffff80,%rsi + 432815: c5 fd e7 07 vmovntdq %ymm0,(%rdi) + 432819: c5 fd e7 4f 20 vmovntdq %ymm1,0x20(%rdi) + 43281e: c5 fd e7 57 40 vmovntdq %ymm2,0x40(%rdi) + 432823: c5 fd e7 5f 60 vmovntdq %ymm3,0x60(%rdi) + 432828: 48 83 ef 80 sub $0xffffffffffffff80,%rdi + 43282c: 48 83 c2 80 add $0xffffffffffffff80,%rdx + 432830: 72 be jb 4327f0 <__memmove_avx_unaligned+0x320> + 432832: 0f ae f8 sfence + 432835: c4 c1 7e 7f 20 vmovdqu %ymm4,(%r8) + 43283a: c5 f8 77 vzeroupper + 43283d: c5 fa 7f 69 80 vmovdqu %xmm5,-0x80(%rcx) + 432842: c5 fa 7f 71 90 vmovdqu %xmm6,-0x70(%rcx) + 432847: c5 fa 7f 79 a0 vmovdqu %xmm7,-0x60(%rcx) + 43284c: c5 7a 7f 41 b0 vmovdqu %xmm8,-0x50(%rcx) + 432851: c5 7a 7f 49 c0 vmovdqu %xmm9,-0x40(%rcx) + 432856: c5 7a 7f 51 d0 vmovdqu %xmm10,-0x30(%rcx) + 43285b: c5 7a 7f 59 e0 vmovdqu %xmm11,-0x20(%rcx) + 432860: c5 7a 7f 61 f0 vmovdqu %xmm12,-0x10(%rcx) + 432865: c3 retq + 432866: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43286d: 00 00 00 + 432870: 48 8b 0d 39 88 29 00 mov 0x298839(%rip),%rcx # 6cb0b0 <__x86_shared_cache_size_half> + 432877: 48 c1 e1 03 shl $0x3,%rcx + 43287b: c5 fa 6f 2e vmovdqu (%rsi),%xmm5 + 43287f: c5 fa 6f 76 10 vmovdqu 0x10(%rsi),%xmm6 + 432884: 48 01 d7 add %rdx,%rdi + 432887: c5 fa 6f 7e 20 vmovdqu 0x20(%rsi),%xmm7 + 43288c: c5 7a 6f 46 30 vmovdqu 0x30(%rsi),%xmm8 + 432891: 4c 8d 57 e0 lea -0x20(%rdi),%r10 + 432895: 49 89 fb mov %rdi,%r11 + 432898: c5 7a 6f 4e 40 vmovdqu 0x40(%rsi),%xmm9 + 43289d: c5 7a 6f 56 50 vmovdqu 0x50(%rsi),%xmm10 + 4328a2: 49 83 e3 1f and $0x1f,%r11 + 4328a6: c5 7a 6f 5e 60 vmovdqu 0x60(%rsi),%xmm11 + 4328ab: c5 7a 6f 66 70 vmovdqu 0x70(%rsi),%xmm12 + 4328b0: 4c 31 df xor %r11,%rdi + 4328b3: 48 01 d6 add %rdx,%rsi + 4328b6: c5 fe 6f 66 e0 vmovdqu -0x20(%rsi),%ymm4 + 4328bb: 4c 29 de sub %r11,%rsi + 4328be: 4c 29 da sub %r11,%rdx + 4328c1: 48 39 ca cmp %rcx,%rdx + 4328c4: 77 6a ja 432930 <__memmove_avx_unaligned+0x460> + 4328c6: 48 83 c2 80 add $0xffffffffffffff80,%rdx + 4328ca: c5 fe 6f 46 e0 vmovdqu -0x20(%rsi),%ymm0 + 4328cf: c5 fe 6f 4e c0 vmovdqu -0x40(%rsi),%ymm1 + 4328d4: c5 fe 6f 56 a0 vmovdqu -0x60(%rsi),%ymm2 + 4328d9: c5 fe 6f 5e 80 vmovdqu -0x80(%rsi),%ymm3 + 4328de: 48 8d 76 80 lea -0x80(%rsi),%rsi + 4328e2: c5 fd 7f 47 e0 vmovdqa %ymm0,-0x20(%rdi) + 4328e7: c5 fd 7f 4f c0 vmovdqa %ymm1,-0x40(%rdi) + 4328ec: c5 fd 7f 57 a0 vmovdqa %ymm2,-0x60(%rdi) + 4328f1: c5 fd 7f 5f 80 vmovdqa %ymm3,-0x80(%rdi) + 4328f6: 48 8d 7f 80 lea -0x80(%rdi),%rdi + 4328fa: 48 83 c2 80 add $0xffffffffffffff80,%rdx + 4328fe: 72 ca jb 4328ca <__memmove_avx_unaligned+0x3fa> + 432900: c4 c1 7e 7f 22 vmovdqu %ymm4,(%r10) + 432905: c5 f8 77 vzeroupper + 432908: c5 fa 7f 28 vmovdqu %xmm5,(%rax) + 43290c: c5 fa 7f 70 10 vmovdqu %xmm6,0x10(%rax) + 432911: c5 fa 7f 78 20 vmovdqu %xmm7,0x20(%rax) + 432916: c5 7a 7f 40 30 vmovdqu %xmm8,0x30(%rax) + 43291b: c5 7a 7f 48 40 vmovdqu %xmm9,0x40(%rax) + 432920: c5 7a 7f 50 50 vmovdqu %xmm10,0x50(%rax) + 432925: c5 7a 7f 58 60 vmovdqu %xmm11,0x60(%rax) + 43292a: c5 7a 7f 60 70 vmovdqu %xmm12,0x70(%rax) + 43292f: c3 retq + 432930: 48 83 c2 80 add $0xffffffffffffff80,%rdx + 432934: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) + 43293b: 0f 18 86 80 fd ff ff prefetchnta -0x280(%rsi) + 432942: c5 fe 6f 46 e0 vmovdqu -0x20(%rsi),%ymm0 + 432947: c5 fe 6f 4e c0 vmovdqu -0x40(%rsi),%ymm1 + 43294c: c5 fe 6f 56 a0 vmovdqu -0x60(%rsi),%ymm2 + 432951: c5 fe 6f 5e 80 vmovdqu -0x80(%rsi),%ymm3 + 432956: 48 8d 76 80 lea -0x80(%rsi),%rsi + 43295a: c5 fd e7 47 e0 vmovntdq %ymm0,-0x20(%rdi) + 43295f: c5 fd e7 4f c0 vmovntdq %ymm1,-0x40(%rdi) + 432964: c5 fd e7 57 a0 vmovntdq %ymm2,-0x60(%rdi) + 432969: c5 fd e7 5f 80 vmovntdq %ymm3,-0x80(%rdi) + 43296e: 48 8d 7f 80 lea -0x80(%rdi),%rdi + 432972: 48 83 c2 80 add $0xffffffffffffff80,%rdx + 432976: 72 bc jb 432934 <__memmove_avx_unaligned+0x464> + 432978: 0f ae f8 sfence + 43297b: c4 c1 7e 7f 22 vmovdqu %ymm4,(%r10) + 432980: c5 f8 77 vzeroupper + 432983: c5 fa 7f 28 vmovdqu %xmm5,(%rax) + 432987: c5 fa 7f 70 10 vmovdqu %xmm6,0x10(%rax) + 43298c: c5 fa 7f 78 20 vmovdqu %xmm7,0x20(%rax) + 432991: c5 7a 7f 40 30 vmovdqu %xmm8,0x30(%rax) + 432996: c5 7a 7f 48 40 vmovdqu %xmm9,0x40(%rax) + 43299b: c5 7a 7f 50 50 vmovdqu %xmm10,0x50(%rax) + 4329a0: c5 7a 7f 58 60 vmovdqu %xmm11,0x60(%rax) + 4329a5: c5 7a 7f 60 70 vmovdqu %xmm12,0x70(%rax) + 4329aa: c3 retq + 4329ab: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + +00000000004329b0 <__memmove_chk_ssse3_back>: + 4329b0: 48 39 d1 cmp %rdx,%rcx + 4329b3: 0f 82 f7 00 01 00 jb 442ab0 <__chk_fail> + 4329b9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + +00000000004329c0 <__memmove_ssse3_back>: + 4329c0: 48 89 f8 mov %rdi,%rax + 4329c3: 48 39 f7 cmp %rsi,%rdi + 4329c6: 72 26 jb 4329ee <__memmove_ssse3_back+0x2e> + 4329c8: 0f 84 70 24 00 00 je 434e3e <__memmove_ssse3_back+0x247e> + 4329ce: 48 81 fa 90 00 00 00 cmp $0x90,%rdx + 4329d5: 0f 83 95 00 00 00 jae 432a70 <__memmove_ssse3_back+0xb0> + 4329db: 4c 8d 1d 8e 0b 07 00 lea 0x70b8e(%rip),%r11 # 4a3570 + 4329e2: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 4329e6: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 4329ea: ff e2 jmpq *%rdx + 4329ec: 0f 0b ud2 + 4329ee: 48 81 fa 90 00 00 00 cmp $0x90,%rdx + 4329f5: 73 19 jae 432a10 <__memmove_ssse3_back+0x50> + 4329f7: 48 01 d6 add %rdx,%rsi + 4329fa: 48 01 d7 add %rdx,%rdi + 4329fd: 4c 8d 1d ac 0d 07 00 lea 0x70dac(%rip),%r11 # 4a37b0 + 432a04: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 432a08: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 432a0c: ff e2 jmpq *%rdx + 432a0e: 0f 0b ud2 + 432a10: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 432a14: 49 89 f8 mov %rdi,%r8 + 432a17: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi + 432a1b: 48 83 c7 10 add $0x10,%rdi + 432a1f: 49 89 f9 mov %rdi,%r9 + 432a22: 4d 29 c1 sub %r8,%r9 + 432a25: 4c 29 ca sub %r9,%rdx + 432a28: 4c 01 ce add %r9,%rsi + 432a2b: 49 89 f1 mov %rsi,%r9 + 432a2e: 49 83 e1 0f and $0xf,%r9 + 432a32: 0f 84 98 00 00 00 je 432ad0 <__memmove_ssse3_back+0x110> + 432a38: 48 8b 0d 89 86 29 00 mov 0x298689(%rip),%rcx # 6cb0c8 <__x86_data_cache_size> + 432a3f: 48 39 ca cmp %rcx,%rdx + 432a42: 0f 83 28 18 00 00 jae 434270 <__memmove_ssse3_back+0x18b0> + 432a48: 4c 8d 1d a1 0f 07 00 lea 0x70fa1(%rip),%r11 # 4a39f0 + 432a4f: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 432a56: 4f 63 0c 8b movslq (%r11,%r9,4),%r9 + 432a5a: 4d 01 d9 add %r11,%r9 + 432a5d: 41 ff e1 jmpq *%r9 + 432a60: 0f 0b ud2 + 432a62: 0f 1f 40 00 nopl 0x0(%rax) + 432a66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 432a6d: 00 00 00 + 432a70: 48 8b 0d 51 86 29 00 mov 0x298651(%rip),%rcx # 6cb0c8 <__x86_data_cache_size> + 432a77: 48 d1 e1 shl %rcx + 432a7a: 48 39 ca cmp %rcx,%rdx + 432a7d: 0f 87 9d 19 00 00 ja 434420 <__memmove_ssse3_back+0x1a60> + 432a83: 48 01 d7 add %rdx,%rdi + 432a86: 48 01 d6 add %rdx,%rsi + 432a89: f3 0f 6f 46 f0 movdqu -0x10(%rsi),%xmm0 + 432a8e: 4c 8d 47 f0 lea -0x10(%rdi),%r8 + 432a92: 49 89 f9 mov %rdi,%r9 + 432a95: 49 83 e1 0f and $0xf,%r9 + 432a99: 4c 31 cf xor %r9,%rdi + 432a9c: 4c 29 ce sub %r9,%rsi + 432a9f: 4c 29 ca sub %r9,%rdx + 432aa2: 49 89 f1 mov %rsi,%r9 + 432aa5: 49 83 e1 0f and $0xf,%r9 + 432aa9: 0f 84 c1 00 00 00 je 432b70 <__memmove_ssse3_back+0x1b0> + 432aaf: 4c 8d 1d 7a 0f 07 00 lea 0x70f7a(%rip),%r11 # 4a3a30 + 432ab6: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 432abd: 4f 63 0c 8b movslq (%r11,%r9,4),%r9 + 432ac1: 4d 01 d9 add %r11,%r9 + 432ac4: 41 ff e1 jmpq *%r9 + 432ac7: 0f 0b ud2 + 432ac9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 432ad0: 49 89 d1 mov %rdx,%r9 + 432ad3: 49 c1 e9 08 shr $0x8,%r9 + 432ad7: 49 01 d1 add %rdx,%r9 + 432ada: 4c 3b 0d ef 85 29 00 cmp 0x2985ef(%rip),%r9 # 6cb0d0 <__x86_data_cache_size_half> + 432ae1: 0f 83 89 17 00 00 jae 434270 <__memmove_ssse3_back+0x18b0> + 432ae7: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 432aee: 66 90 xchg %ax,%ax + 432af0: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 432af4: 66 0f 7f 0f movdqa %xmm1,(%rdi) + 432af8: 0f 28 56 10 movaps 0x10(%rsi),%xmm2 + 432afc: 0f 29 57 10 movaps %xmm2,0x10(%rdi) + 432b00: 0f 28 5e 20 movaps 0x20(%rsi),%xmm3 + 432b04: 0f 29 5f 20 movaps %xmm3,0x20(%rdi) + 432b08: 0f 28 66 30 movaps 0x30(%rsi),%xmm4 + 432b0c: 0f 29 67 30 movaps %xmm4,0x30(%rdi) + 432b10: 0f 28 4e 40 movaps 0x40(%rsi),%xmm1 + 432b14: 0f 29 4f 40 movaps %xmm1,0x40(%rdi) + 432b18: 0f 28 56 50 movaps 0x50(%rsi),%xmm2 + 432b1c: 0f 29 57 50 movaps %xmm2,0x50(%rdi) + 432b20: 0f 28 5e 60 movaps 0x60(%rsi),%xmm3 + 432b24: 0f 29 5f 60 movaps %xmm3,0x60(%rdi) + 432b28: 0f 28 66 70 movaps 0x70(%rsi),%xmm4 + 432b2c: 0f 29 67 70 movaps %xmm4,0x70(%rdi) + 432b30: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 432b37: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi + 432b3e: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi + 432b45: 73 a9 jae 432af0 <__memmove_ssse3_back+0x130> + 432b47: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 432b4c: 48 81 c2 80 00 00 00 add $0x80,%rdx + 432b53: 48 01 d6 add %rdx,%rsi + 432b56: 48 01 d7 add %rdx,%rdi + 432b59: 4c 8d 1d 50 0c 07 00 lea 0x70c50(%rip),%r11 # 4a37b0 + 432b60: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 432b64: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 432b68: ff e2 jmpq *%rdx + 432b6a: 0f 0b ud2 + 432b6c: 0f 1f 40 00 nopl 0x0(%rax) + 432b70: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 432b77: 0f 28 4e f0 movaps -0x10(%rsi),%xmm1 + 432b7b: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 432b7f: 0f 28 56 e0 movaps -0x20(%rsi),%xmm2 + 432b83: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 432b87: 0f 28 5e d0 movaps -0x30(%rsi),%xmm3 + 432b8b: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 432b8f: 0f 28 66 c0 movaps -0x40(%rsi),%xmm4 + 432b93: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) + 432b97: 0f 28 6e b0 movaps -0x50(%rsi),%xmm5 + 432b9b: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) + 432b9f: 0f 28 6e a0 movaps -0x60(%rsi),%xmm5 + 432ba3: 0f 29 6f a0 movaps %xmm5,-0x60(%rdi) + 432ba7: 0f 28 6e 90 movaps -0x70(%rsi),%xmm5 + 432bab: 0f 29 6f 90 movaps %xmm5,-0x70(%rdi) + 432baf: 0f 28 6e 80 movaps -0x80(%rsi),%xmm5 + 432bb3: 0f 29 6f 80 movaps %xmm5,-0x80(%rdi) + 432bb7: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 432bbe: 48 8d 7f 80 lea -0x80(%rdi),%rdi + 432bc2: 48 8d 76 80 lea -0x80(%rsi),%rsi + 432bc6: 73 af jae 432b77 <__memmove_ssse3_back+0x1b7> + 432bc8: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 432bcd: 48 81 c2 80 00 00 00 add $0x80,%rdx + 432bd4: 48 29 d7 sub %rdx,%rdi + 432bd7: 48 29 d6 sub %rdx,%rsi + 432bda: 4c 8d 1d 8f 09 07 00 lea 0x7098f(%rip),%r11 # 4a3570 + 432be1: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 432be5: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 432be9: ff e2 jmpq *%rdx + 432beb: 0f 0b ud2 + 432bed: 0f 1f 00 nopl (%rax) + 432bf0: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 432bf7: 0f 28 4e ff movaps -0x1(%rsi),%xmm1 + 432bfb: 0f 28 56 0f movaps 0xf(%rsi),%xmm2 + 432bff: 0f 28 5e 1f movaps 0x1f(%rsi),%xmm3 + 432c03: 0f 28 66 2f movaps 0x2f(%rsi),%xmm4 + 432c07: 0f 28 6e 3f movaps 0x3f(%rsi),%xmm5 + 432c0b: 0f 28 76 4f movaps 0x4f(%rsi),%xmm6 + 432c0f: 0f 28 7e 5f movaps 0x5f(%rsi),%xmm7 + 432c13: 44 0f 28 46 6f movaps 0x6f(%rsi),%xmm8 + 432c18: 44 0f 28 4e 7f movaps 0x7f(%rsi),%xmm9 + 432c1d: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi + 432c24: 66 45 0f 3a 0f c8 01 palignr $0x1,%xmm8,%xmm9 + 432c2b: 44 0f 29 4f 70 movaps %xmm9,0x70(%rdi) + 432c30: 66 44 0f 3a 0f c7 01 palignr $0x1,%xmm7,%xmm8 + 432c37: 44 0f 29 47 60 movaps %xmm8,0x60(%rdi) + 432c3c: 66 0f 3a 0f fe 01 palignr $0x1,%xmm6,%xmm7 + 432c42: 0f 29 7f 50 movaps %xmm7,0x50(%rdi) + 432c46: 66 0f 3a 0f f5 01 palignr $0x1,%xmm5,%xmm6 + 432c4c: 0f 29 77 40 movaps %xmm6,0x40(%rdi) + 432c50: 66 0f 3a 0f ec 01 palignr $0x1,%xmm4,%xmm5 + 432c56: 0f 29 6f 30 movaps %xmm5,0x30(%rdi) + 432c5a: 66 0f 3a 0f e3 01 palignr $0x1,%xmm3,%xmm4 + 432c60: 0f 29 67 20 movaps %xmm4,0x20(%rdi) + 432c64: 66 0f 3a 0f da 01 palignr $0x1,%xmm2,%xmm3 + 432c6a: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) + 432c6e: 66 0f 3a 0f d1 01 palignr $0x1,%xmm1,%xmm2 + 432c74: 0f 29 17 movaps %xmm2,(%rdi) + 432c77: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi + 432c7e: 0f 83 6c ff ff ff jae 432bf0 <__memmove_ssse3_back+0x230> + 432c84: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 432c89: 48 81 c2 80 00 00 00 add $0x80,%rdx + 432c90: 48 01 d7 add %rdx,%rdi + 432c93: 48 01 d6 add %rdx,%rsi + 432c96: 4c 8d 1d 13 0b 07 00 lea 0x70b13(%rip),%r11 # 4a37b0 + 432c9d: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 432ca1: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 432ca5: ff e2 jmpq *%rdx + 432ca7: 0f 0b ud2 + 432ca9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 432cb0: 0f 28 4e ff movaps -0x1(%rsi),%xmm1 + 432cb4: 0f 28 56 ef movaps -0x11(%rsi),%xmm2 + 432cb8: 66 0f 3a 0f ca 01 palignr $0x1,%xmm2,%xmm1 + 432cbe: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 432cc2: 0f 28 5e df movaps -0x21(%rsi),%xmm3 + 432cc6: 66 0f 3a 0f d3 01 palignr $0x1,%xmm3,%xmm2 + 432ccc: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 432cd0: 0f 28 66 cf movaps -0x31(%rsi),%xmm4 + 432cd4: 66 0f 3a 0f dc 01 palignr $0x1,%xmm4,%xmm3 + 432cda: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 432cde: 0f 28 6e bf movaps -0x41(%rsi),%xmm5 + 432ce2: 66 0f 3a 0f e5 01 palignr $0x1,%xmm5,%xmm4 + 432ce8: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) + 432cec: 0f 28 76 af movaps -0x51(%rsi),%xmm6 + 432cf0: 66 0f 3a 0f ee 01 palignr $0x1,%xmm6,%xmm5 + 432cf6: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) + 432cfa: 0f 28 7e 9f movaps -0x61(%rsi),%xmm7 + 432cfe: 66 0f 3a 0f f7 01 palignr $0x1,%xmm7,%xmm6 + 432d04: 0f 29 77 a0 movaps %xmm6,-0x60(%rdi) + 432d08: 44 0f 28 46 8f movaps -0x71(%rsi),%xmm8 + 432d0d: 66 41 0f 3a 0f f8 01 palignr $0x1,%xmm8,%xmm7 + 432d14: 0f 29 7f 90 movaps %xmm7,-0x70(%rdi) + 432d18: 44 0f 28 8e 7f ff ff movaps -0x81(%rsi),%xmm9 + 432d1f: ff + 432d20: 66 45 0f 3a 0f c1 01 palignr $0x1,%xmm9,%xmm8 + 432d27: 44 0f 29 47 80 movaps %xmm8,-0x80(%rdi) + 432d2c: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 432d33: 48 8d 7f 80 lea -0x80(%rdi),%rdi + 432d37: 48 8d 76 80 lea -0x80(%rsi),%rsi + 432d3b: 0f 83 6f ff ff ff jae 432cb0 <__memmove_ssse3_back+0x2f0> + 432d41: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 432d46: 48 81 c2 80 00 00 00 add $0x80,%rdx + 432d4d: 48 29 d7 sub %rdx,%rdi + 432d50: 48 29 d6 sub %rdx,%rsi + 432d53: 4c 8d 1d 16 08 07 00 lea 0x70816(%rip),%r11 # 4a3570 + 432d5a: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 432d5e: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 432d62: ff e2 jmpq *%rdx + 432d64: 0f 0b ud2 + 432d66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 432d6d: 00 00 00 + 432d70: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 432d77: 0f 28 4e fe movaps -0x2(%rsi),%xmm1 + 432d7b: 0f 28 56 0e movaps 0xe(%rsi),%xmm2 + 432d7f: 0f 28 5e 1e movaps 0x1e(%rsi),%xmm3 + 432d83: 0f 28 66 2e movaps 0x2e(%rsi),%xmm4 + 432d87: 0f 28 6e 3e movaps 0x3e(%rsi),%xmm5 + 432d8b: 0f 28 76 4e movaps 0x4e(%rsi),%xmm6 + 432d8f: 0f 28 7e 5e movaps 0x5e(%rsi),%xmm7 + 432d93: 44 0f 28 46 6e movaps 0x6e(%rsi),%xmm8 + 432d98: 44 0f 28 4e 7e movaps 0x7e(%rsi),%xmm9 + 432d9d: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi + 432da4: 66 45 0f 3a 0f c8 02 palignr $0x2,%xmm8,%xmm9 + 432dab: 44 0f 29 4f 70 movaps %xmm9,0x70(%rdi) + 432db0: 66 44 0f 3a 0f c7 02 palignr $0x2,%xmm7,%xmm8 + 432db7: 44 0f 29 47 60 movaps %xmm8,0x60(%rdi) + 432dbc: 66 0f 3a 0f fe 02 palignr $0x2,%xmm6,%xmm7 + 432dc2: 0f 29 7f 50 movaps %xmm7,0x50(%rdi) + 432dc6: 66 0f 3a 0f f5 02 palignr $0x2,%xmm5,%xmm6 + 432dcc: 0f 29 77 40 movaps %xmm6,0x40(%rdi) + 432dd0: 66 0f 3a 0f ec 02 palignr $0x2,%xmm4,%xmm5 + 432dd6: 0f 29 6f 30 movaps %xmm5,0x30(%rdi) + 432dda: 66 0f 3a 0f e3 02 palignr $0x2,%xmm3,%xmm4 + 432de0: 0f 29 67 20 movaps %xmm4,0x20(%rdi) + 432de4: 66 0f 3a 0f da 02 palignr $0x2,%xmm2,%xmm3 + 432dea: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) + 432dee: 66 0f 3a 0f d1 02 palignr $0x2,%xmm1,%xmm2 + 432df4: 0f 29 17 movaps %xmm2,(%rdi) + 432df7: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi + 432dfe: 0f 83 6c ff ff ff jae 432d70 <__memmove_ssse3_back+0x3b0> + 432e04: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 432e09: 48 81 c2 80 00 00 00 add $0x80,%rdx + 432e10: 48 01 d7 add %rdx,%rdi + 432e13: 48 01 d6 add %rdx,%rsi + 432e16: 4c 8d 1d 93 09 07 00 lea 0x70993(%rip),%r11 # 4a37b0 + 432e1d: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 432e21: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 432e25: ff e2 jmpq *%rdx + 432e27: 0f 0b ud2 + 432e29: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 432e30: 0f 28 4e fe movaps -0x2(%rsi),%xmm1 + 432e34: 0f 28 56 ee movaps -0x12(%rsi),%xmm2 + 432e38: 66 0f 3a 0f ca 02 palignr $0x2,%xmm2,%xmm1 + 432e3e: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 432e42: 0f 28 5e de movaps -0x22(%rsi),%xmm3 + 432e46: 66 0f 3a 0f d3 02 palignr $0x2,%xmm3,%xmm2 + 432e4c: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 432e50: 0f 28 66 ce movaps -0x32(%rsi),%xmm4 + 432e54: 66 0f 3a 0f dc 02 palignr $0x2,%xmm4,%xmm3 + 432e5a: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 432e5e: 0f 28 6e be movaps -0x42(%rsi),%xmm5 + 432e62: 66 0f 3a 0f e5 02 palignr $0x2,%xmm5,%xmm4 + 432e68: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) + 432e6c: 0f 28 76 ae movaps -0x52(%rsi),%xmm6 + 432e70: 66 0f 3a 0f ee 02 palignr $0x2,%xmm6,%xmm5 + 432e76: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) + 432e7a: 0f 28 7e 9e movaps -0x62(%rsi),%xmm7 + 432e7e: 66 0f 3a 0f f7 02 palignr $0x2,%xmm7,%xmm6 + 432e84: 0f 29 77 a0 movaps %xmm6,-0x60(%rdi) + 432e88: 44 0f 28 46 8e movaps -0x72(%rsi),%xmm8 + 432e8d: 66 41 0f 3a 0f f8 02 palignr $0x2,%xmm8,%xmm7 + 432e94: 0f 29 7f 90 movaps %xmm7,-0x70(%rdi) + 432e98: 44 0f 28 8e 7e ff ff movaps -0x82(%rsi),%xmm9 + 432e9f: ff + 432ea0: 66 45 0f 3a 0f c1 02 palignr $0x2,%xmm9,%xmm8 + 432ea7: 44 0f 29 47 80 movaps %xmm8,-0x80(%rdi) + 432eac: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 432eb3: 48 8d 7f 80 lea -0x80(%rdi),%rdi + 432eb7: 48 8d 76 80 lea -0x80(%rsi),%rsi + 432ebb: 0f 83 6f ff ff ff jae 432e30 <__memmove_ssse3_back+0x470> + 432ec1: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 432ec6: 48 81 c2 80 00 00 00 add $0x80,%rdx + 432ecd: 48 29 d7 sub %rdx,%rdi + 432ed0: 48 29 d6 sub %rdx,%rsi + 432ed3: 4c 8d 1d 96 06 07 00 lea 0x70696(%rip),%r11 # 4a3570 + 432eda: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 432ede: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 432ee2: ff e2 jmpq *%rdx + 432ee4: 0f 0b ud2 + 432ee6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 432eed: 00 00 00 + 432ef0: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 432ef7: 0f 28 4e fd movaps -0x3(%rsi),%xmm1 + 432efb: 0f 28 56 0d movaps 0xd(%rsi),%xmm2 + 432eff: 0f 28 5e 1d movaps 0x1d(%rsi),%xmm3 + 432f03: 0f 28 66 2d movaps 0x2d(%rsi),%xmm4 + 432f07: 0f 28 6e 3d movaps 0x3d(%rsi),%xmm5 + 432f0b: 0f 28 76 4d movaps 0x4d(%rsi),%xmm6 + 432f0f: 0f 28 7e 5d movaps 0x5d(%rsi),%xmm7 + 432f13: 44 0f 28 46 6d movaps 0x6d(%rsi),%xmm8 + 432f18: 44 0f 28 4e 7d movaps 0x7d(%rsi),%xmm9 + 432f1d: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi + 432f24: 66 45 0f 3a 0f c8 03 palignr $0x3,%xmm8,%xmm9 + 432f2b: 44 0f 29 4f 70 movaps %xmm9,0x70(%rdi) + 432f30: 66 44 0f 3a 0f c7 03 palignr $0x3,%xmm7,%xmm8 + 432f37: 44 0f 29 47 60 movaps %xmm8,0x60(%rdi) + 432f3c: 66 0f 3a 0f fe 03 palignr $0x3,%xmm6,%xmm7 + 432f42: 0f 29 7f 50 movaps %xmm7,0x50(%rdi) + 432f46: 66 0f 3a 0f f5 03 palignr $0x3,%xmm5,%xmm6 + 432f4c: 0f 29 77 40 movaps %xmm6,0x40(%rdi) + 432f50: 66 0f 3a 0f ec 03 palignr $0x3,%xmm4,%xmm5 + 432f56: 0f 29 6f 30 movaps %xmm5,0x30(%rdi) + 432f5a: 66 0f 3a 0f e3 03 palignr $0x3,%xmm3,%xmm4 + 432f60: 0f 29 67 20 movaps %xmm4,0x20(%rdi) + 432f64: 66 0f 3a 0f da 03 palignr $0x3,%xmm2,%xmm3 + 432f6a: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) + 432f6e: 66 0f 3a 0f d1 03 palignr $0x3,%xmm1,%xmm2 + 432f74: 0f 29 17 movaps %xmm2,(%rdi) + 432f77: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi + 432f7e: 0f 83 6c ff ff ff jae 432ef0 <__memmove_ssse3_back+0x530> + 432f84: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 432f89: 48 81 c2 80 00 00 00 add $0x80,%rdx + 432f90: 48 01 d7 add %rdx,%rdi + 432f93: 48 01 d6 add %rdx,%rsi + 432f96: 4c 8d 1d 13 08 07 00 lea 0x70813(%rip),%r11 # 4a37b0 + 432f9d: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 432fa1: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 432fa5: ff e2 jmpq *%rdx + 432fa7: 0f 0b ud2 + 432fa9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 432fb0: 0f 28 4e fd movaps -0x3(%rsi),%xmm1 + 432fb4: 0f 28 56 ed movaps -0x13(%rsi),%xmm2 + 432fb8: 66 0f 3a 0f ca 03 palignr $0x3,%xmm2,%xmm1 + 432fbe: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 432fc2: 0f 28 5e dd movaps -0x23(%rsi),%xmm3 + 432fc6: 66 0f 3a 0f d3 03 palignr $0x3,%xmm3,%xmm2 + 432fcc: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 432fd0: 0f 28 66 cd movaps -0x33(%rsi),%xmm4 + 432fd4: 66 0f 3a 0f dc 03 palignr $0x3,%xmm4,%xmm3 + 432fda: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 432fde: 0f 28 6e bd movaps -0x43(%rsi),%xmm5 + 432fe2: 66 0f 3a 0f e5 03 palignr $0x3,%xmm5,%xmm4 + 432fe8: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) + 432fec: 0f 28 76 ad movaps -0x53(%rsi),%xmm6 + 432ff0: 66 0f 3a 0f ee 03 palignr $0x3,%xmm6,%xmm5 + 432ff6: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) + 432ffa: 0f 28 7e 9d movaps -0x63(%rsi),%xmm7 + 432ffe: 66 0f 3a 0f f7 03 palignr $0x3,%xmm7,%xmm6 + 433004: 0f 29 77 a0 movaps %xmm6,-0x60(%rdi) + 433008: 44 0f 28 46 8d movaps -0x73(%rsi),%xmm8 + 43300d: 66 41 0f 3a 0f f8 03 palignr $0x3,%xmm8,%xmm7 + 433014: 0f 29 7f 90 movaps %xmm7,-0x70(%rdi) + 433018: 44 0f 28 8e 7d ff ff movaps -0x83(%rsi),%xmm9 + 43301f: ff + 433020: 66 45 0f 3a 0f c1 03 palignr $0x3,%xmm9,%xmm8 + 433027: 44 0f 29 47 80 movaps %xmm8,-0x80(%rdi) + 43302c: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 433033: 48 8d 7f 80 lea -0x80(%rdi),%rdi + 433037: 48 8d 76 80 lea -0x80(%rsi),%rsi + 43303b: 0f 83 6f ff ff ff jae 432fb0 <__memmove_ssse3_back+0x5f0> + 433041: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 433046: 48 81 c2 80 00 00 00 add $0x80,%rdx + 43304d: 48 29 d7 sub %rdx,%rdi + 433050: 48 29 d6 sub %rdx,%rsi + 433053: 4c 8d 1d 16 05 07 00 lea 0x70516(%rip),%r11 # 4a3570 + 43305a: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 43305e: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 433062: ff e2 jmpq *%rdx + 433064: 0f 0b ud2 + 433066: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43306d: 00 00 00 + 433070: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 433077: 0f 28 4e fc movaps -0x4(%rsi),%xmm1 + 43307b: 0f 28 56 0c movaps 0xc(%rsi),%xmm2 + 43307f: 0f 28 5e 1c movaps 0x1c(%rsi),%xmm3 + 433083: 0f 28 66 2c movaps 0x2c(%rsi),%xmm4 + 433087: 0f 28 6e 3c movaps 0x3c(%rsi),%xmm5 + 43308b: 0f 28 76 4c movaps 0x4c(%rsi),%xmm6 + 43308f: 0f 28 7e 5c movaps 0x5c(%rsi),%xmm7 + 433093: 44 0f 28 46 6c movaps 0x6c(%rsi),%xmm8 + 433098: 44 0f 28 4e 7c movaps 0x7c(%rsi),%xmm9 + 43309d: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi + 4330a4: 66 45 0f 3a 0f c8 04 palignr $0x4,%xmm8,%xmm9 + 4330ab: 44 0f 29 4f 70 movaps %xmm9,0x70(%rdi) + 4330b0: 66 44 0f 3a 0f c7 04 palignr $0x4,%xmm7,%xmm8 + 4330b7: 44 0f 29 47 60 movaps %xmm8,0x60(%rdi) + 4330bc: 66 0f 3a 0f fe 04 palignr $0x4,%xmm6,%xmm7 + 4330c2: 0f 29 7f 50 movaps %xmm7,0x50(%rdi) + 4330c6: 66 0f 3a 0f f5 04 palignr $0x4,%xmm5,%xmm6 + 4330cc: 0f 29 77 40 movaps %xmm6,0x40(%rdi) + 4330d0: 66 0f 3a 0f ec 04 palignr $0x4,%xmm4,%xmm5 + 4330d6: 0f 29 6f 30 movaps %xmm5,0x30(%rdi) + 4330da: 66 0f 3a 0f e3 04 palignr $0x4,%xmm3,%xmm4 + 4330e0: 0f 29 67 20 movaps %xmm4,0x20(%rdi) + 4330e4: 66 0f 3a 0f da 04 palignr $0x4,%xmm2,%xmm3 + 4330ea: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) + 4330ee: 66 0f 3a 0f d1 04 palignr $0x4,%xmm1,%xmm2 + 4330f4: 0f 29 17 movaps %xmm2,(%rdi) + 4330f7: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi + 4330fe: 0f 83 6c ff ff ff jae 433070 <__memmove_ssse3_back+0x6b0> + 433104: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 433109: 48 81 c2 80 00 00 00 add $0x80,%rdx + 433110: 48 01 d7 add %rdx,%rdi + 433113: 48 01 d6 add %rdx,%rsi + 433116: 4c 8d 1d 93 06 07 00 lea 0x70693(%rip),%r11 # 4a37b0 + 43311d: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 433121: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 433125: ff e2 jmpq *%rdx + 433127: 0f 0b ud2 + 433129: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 433130: 0f 28 4e fc movaps -0x4(%rsi),%xmm1 + 433134: 0f 28 56 ec movaps -0x14(%rsi),%xmm2 + 433138: 66 0f 3a 0f ca 04 palignr $0x4,%xmm2,%xmm1 + 43313e: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 433142: 0f 28 5e dc movaps -0x24(%rsi),%xmm3 + 433146: 66 0f 3a 0f d3 04 palignr $0x4,%xmm3,%xmm2 + 43314c: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 433150: 0f 28 66 cc movaps -0x34(%rsi),%xmm4 + 433154: 66 0f 3a 0f dc 04 palignr $0x4,%xmm4,%xmm3 + 43315a: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 43315e: 0f 28 6e bc movaps -0x44(%rsi),%xmm5 + 433162: 66 0f 3a 0f e5 04 palignr $0x4,%xmm5,%xmm4 + 433168: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) + 43316c: 0f 28 76 ac movaps -0x54(%rsi),%xmm6 + 433170: 66 0f 3a 0f ee 04 palignr $0x4,%xmm6,%xmm5 + 433176: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) + 43317a: 0f 28 7e 9c movaps -0x64(%rsi),%xmm7 + 43317e: 66 0f 3a 0f f7 04 palignr $0x4,%xmm7,%xmm6 + 433184: 0f 29 77 a0 movaps %xmm6,-0x60(%rdi) + 433188: 44 0f 28 46 8c movaps -0x74(%rsi),%xmm8 + 43318d: 66 41 0f 3a 0f f8 04 palignr $0x4,%xmm8,%xmm7 + 433194: 0f 29 7f 90 movaps %xmm7,-0x70(%rdi) + 433198: 44 0f 28 8e 7c ff ff movaps -0x84(%rsi),%xmm9 + 43319f: ff + 4331a0: 66 45 0f 3a 0f c1 04 palignr $0x4,%xmm9,%xmm8 + 4331a7: 44 0f 29 47 80 movaps %xmm8,-0x80(%rdi) + 4331ac: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 4331b3: 48 8d 7f 80 lea -0x80(%rdi),%rdi + 4331b7: 48 8d 76 80 lea -0x80(%rsi),%rsi + 4331bb: 0f 83 6f ff ff ff jae 433130 <__memmove_ssse3_back+0x770> + 4331c1: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 4331c6: 48 81 c2 80 00 00 00 add $0x80,%rdx + 4331cd: 48 29 d7 sub %rdx,%rdi + 4331d0: 48 29 d6 sub %rdx,%rsi + 4331d3: 4c 8d 1d 96 03 07 00 lea 0x70396(%rip),%r11 # 4a3570 + 4331da: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 4331de: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 4331e2: ff e2 jmpq *%rdx + 4331e4: 0f 0b ud2 + 4331e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4331ed: 00 00 00 + 4331f0: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 4331f7: 0f 28 4e fb movaps -0x5(%rsi),%xmm1 + 4331fb: 0f 28 56 0b movaps 0xb(%rsi),%xmm2 + 4331ff: 0f 28 5e 1b movaps 0x1b(%rsi),%xmm3 + 433203: 0f 28 66 2b movaps 0x2b(%rsi),%xmm4 + 433207: 0f 28 6e 3b movaps 0x3b(%rsi),%xmm5 + 43320b: 0f 28 76 4b movaps 0x4b(%rsi),%xmm6 + 43320f: 0f 28 7e 5b movaps 0x5b(%rsi),%xmm7 + 433213: 44 0f 28 46 6b movaps 0x6b(%rsi),%xmm8 + 433218: 44 0f 28 4e 7b movaps 0x7b(%rsi),%xmm9 + 43321d: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi + 433224: 66 45 0f 3a 0f c8 05 palignr $0x5,%xmm8,%xmm9 + 43322b: 44 0f 29 4f 70 movaps %xmm9,0x70(%rdi) + 433230: 66 44 0f 3a 0f c7 05 palignr $0x5,%xmm7,%xmm8 + 433237: 44 0f 29 47 60 movaps %xmm8,0x60(%rdi) + 43323c: 66 0f 3a 0f fe 05 palignr $0x5,%xmm6,%xmm7 + 433242: 0f 29 7f 50 movaps %xmm7,0x50(%rdi) + 433246: 66 0f 3a 0f f5 05 palignr $0x5,%xmm5,%xmm6 + 43324c: 0f 29 77 40 movaps %xmm6,0x40(%rdi) + 433250: 66 0f 3a 0f ec 05 palignr $0x5,%xmm4,%xmm5 + 433256: 0f 29 6f 30 movaps %xmm5,0x30(%rdi) + 43325a: 66 0f 3a 0f e3 05 palignr $0x5,%xmm3,%xmm4 + 433260: 0f 29 67 20 movaps %xmm4,0x20(%rdi) + 433264: 66 0f 3a 0f da 05 palignr $0x5,%xmm2,%xmm3 + 43326a: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) + 43326e: 66 0f 3a 0f d1 05 palignr $0x5,%xmm1,%xmm2 + 433274: 0f 29 17 movaps %xmm2,(%rdi) + 433277: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi + 43327e: 0f 83 6c ff ff ff jae 4331f0 <__memmove_ssse3_back+0x830> + 433284: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 433289: 48 81 c2 80 00 00 00 add $0x80,%rdx + 433290: 48 01 d7 add %rdx,%rdi + 433293: 48 01 d6 add %rdx,%rsi + 433296: 4c 8d 1d 13 05 07 00 lea 0x70513(%rip),%r11 # 4a37b0 + 43329d: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 4332a1: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 4332a5: ff e2 jmpq *%rdx + 4332a7: 0f 0b ud2 + 4332a9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4332b0: 0f 28 4e fb movaps -0x5(%rsi),%xmm1 + 4332b4: 0f 28 56 eb movaps -0x15(%rsi),%xmm2 + 4332b8: 66 0f 3a 0f ca 05 palignr $0x5,%xmm2,%xmm1 + 4332be: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 4332c2: 0f 28 5e db movaps -0x25(%rsi),%xmm3 + 4332c6: 66 0f 3a 0f d3 05 palignr $0x5,%xmm3,%xmm2 + 4332cc: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 4332d0: 0f 28 66 cb movaps -0x35(%rsi),%xmm4 + 4332d4: 66 0f 3a 0f dc 05 palignr $0x5,%xmm4,%xmm3 + 4332da: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 4332de: 0f 28 6e bb movaps -0x45(%rsi),%xmm5 + 4332e2: 66 0f 3a 0f e5 05 palignr $0x5,%xmm5,%xmm4 + 4332e8: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) + 4332ec: 0f 28 76 ab movaps -0x55(%rsi),%xmm6 + 4332f0: 66 0f 3a 0f ee 05 palignr $0x5,%xmm6,%xmm5 + 4332f6: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) + 4332fa: 0f 28 7e 9b movaps -0x65(%rsi),%xmm7 + 4332fe: 66 0f 3a 0f f7 05 palignr $0x5,%xmm7,%xmm6 + 433304: 0f 29 77 a0 movaps %xmm6,-0x60(%rdi) + 433308: 44 0f 28 46 8b movaps -0x75(%rsi),%xmm8 + 43330d: 66 41 0f 3a 0f f8 05 palignr $0x5,%xmm8,%xmm7 + 433314: 0f 29 7f 90 movaps %xmm7,-0x70(%rdi) + 433318: 44 0f 28 8e 7b ff ff movaps -0x85(%rsi),%xmm9 + 43331f: ff + 433320: 66 45 0f 3a 0f c1 05 palignr $0x5,%xmm9,%xmm8 + 433327: 44 0f 29 47 80 movaps %xmm8,-0x80(%rdi) + 43332c: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 433333: 48 8d 7f 80 lea -0x80(%rdi),%rdi + 433337: 48 8d 76 80 lea -0x80(%rsi),%rsi + 43333b: 0f 83 6f ff ff ff jae 4332b0 <__memmove_ssse3_back+0x8f0> + 433341: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 433346: 48 81 c2 80 00 00 00 add $0x80,%rdx + 43334d: 48 29 d7 sub %rdx,%rdi + 433350: 48 29 d6 sub %rdx,%rsi + 433353: 4c 8d 1d 16 02 07 00 lea 0x70216(%rip),%r11 # 4a3570 + 43335a: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 43335e: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 433362: ff e2 jmpq *%rdx + 433364: 0f 0b ud2 + 433366: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43336d: 00 00 00 + 433370: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 433377: 0f 28 4e fa movaps -0x6(%rsi),%xmm1 + 43337b: 0f 28 56 0a movaps 0xa(%rsi),%xmm2 + 43337f: 0f 28 5e 1a movaps 0x1a(%rsi),%xmm3 + 433383: 0f 28 66 2a movaps 0x2a(%rsi),%xmm4 + 433387: 0f 28 6e 3a movaps 0x3a(%rsi),%xmm5 + 43338b: 0f 28 76 4a movaps 0x4a(%rsi),%xmm6 + 43338f: 0f 28 7e 5a movaps 0x5a(%rsi),%xmm7 + 433393: 44 0f 28 46 6a movaps 0x6a(%rsi),%xmm8 + 433398: 44 0f 28 4e 7a movaps 0x7a(%rsi),%xmm9 + 43339d: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi + 4333a4: 66 45 0f 3a 0f c8 06 palignr $0x6,%xmm8,%xmm9 + 4333ab: 44 0f 29 4f 70 movaps %xmm9,0x70(%rdi) + 4333b0: 66 44 0f 3a 0f c7 06 palignr $0x6,%xmm7,%xmm8 + 4333b7: 44 0f 29 47 60 movaps %xmm8,0x60(%rdi) + 4333bc: 66 0f 3a 0f fe 06 palignr $0x6,%xmm6,%xmm7 + 4333c2: 0f 29 7f 50 movaps %xmm7,0x50(%rdi) + 4333c6: 66 0f 3a 0f f5 06 palignr $0x6,%xmm5,%xmm6 + 4333cc: 0f 29 77 40 movaps %xmm6,0x40(%rdi) + 4333d0: 66 0f 3a 0f ec 06 palignr $0x6,%xmm4,%xmm5 + 4333d6: 0f 29 6f 30 movaps %xmm5,0x30(%rdi) + 4333da: 66 0f 3a 0f e3 06 palignr $0x6,%xmm3,%xmm4 + 4333e0: 0f 29 67 20 movaps %xmm4,0x20(%rdi) + 4333e4: 66 0f 3a 0f da 06 palignr $0x6,%xmm2,%xmm3 + 4333ea: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) + 4333ee: 66 0f 3a 0f d1 06 palignr $0x6,%xmm1,%xmm2 + 4333f4: 0f 29 17 movaps %xmm2,(%rdi) + 4333f7: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi + 4333fe: 0f 83 6c ff ff ff jae 433370 <__memmove_ssse3_back+0x9b0> + 433404: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 433409: 48 81 c2 80 00 00 00 add $0x80,%rdx + 433410: 48 01 d7 add %rdx,%rdi + 433413: 48 01 d6 add %rdx,%rsi + 433416: 4c 8d 1d 93 03 07 00 lea 0x70393(%rip),%r11 # 4a37b0 + 43341d: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 433421: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 433425: ff e2 jmpq *%rdx + 433427: 0f 0b ud2 + 433429: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 433430: 0f 28 4e fa movaps -0x6(%rsi),%xmm1 + 433434: 0f 28 56 ea movaps -0x16(%rsi),%xmm2 + 433438: 66 0f 3a 0f ca 06 palignr $0x6,%xmm2,%xmm1 + 43343e: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 433442: 0f 28 5e da movaps -0x26(%rsi),%xmm3 + 433446: 66 0f 3a 0f d3 06 palignr $0x6,%xmm3,%xmm2 + 43344c: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 433450: 0f 28 66 ca movaps -0x36(%rsi),%xmm4 + 433454: 66 0f 3a 0f dc 06 palignr $0x6,%xmm4,%xmm3 + 43345a: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 43345e: 0f 28 6e ba movaps -0x46(%rsi),%xmm5 + 433462: 66 0f 3a 0f e5 06 palignr $0x6,%xmm5,%xmm4 + 433468: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) + 43346c: 0f 28 76 aa movaps -0x56(%rsi),%xmm6 + 433470: 66 0f 3a 0f ee 06 palignr $0x6,%xmm6,%xmm5 + 433476: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) + 43347a: 0f 28 7e 9a movaps -0x66(%rsi),%xmm7 + 43347e: 66 0f 3a 0f f7 06 palignr $0x6,%xmm7,%xmm6 + 433484: 0f 29 77 a0 movaps %xmm6,-0x60(%rdi) + 433488: 44 0f 28 46 8a movaps -0x76(%rsi),%xmm8 + 43348d: 66 41 0f 3a 0f f8 06 palignr $0x6,%xmm8,%xmm7 + 433494: 0f 29 7f 90 movaps %xmm7,-0x70(%rdi) + 433498: 44 0f 28 8e 7a ff ff movaps -0x86(%rsi),%xmm9 + 43349f: ff + 4334a0: 66 45 0f 3a 0f c1 06 palignr $0x6,%xmm9,%xmm8 + 4334a7: 44 0f 29 47 80 movaps %xmm8,-0x80(%rdi) + 4334ac: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 4334b3: 48 8d 7f 80 lea -0x80(%rdi),%rdi + 4334b7: 48 8d 76 80 lea -0x80(%rsi),%rsi + 4334bb: 0f 83 6f ff ff ff jae 433430 <__memmove_ssse3_back+0xa70> + 4334c1: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 4334c6: 48 81 c2 80 00 00 00 add $0x80,%rdx + 4334cd: 48 29 d7 sub %rdx,%rdi + 4334d0: 48 29 d6 sub %rdx,%rsi + 4334d3: 4c 8d 1d 96 00 07 00 lea 0x70096(%rip),%r11 # 4a3570 + 4334da: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 4334de: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 4334e2: ff e2 jmpq *%rdx + 4334e4: 0f 0b ud2 + 4334e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4334ed: 00 00 00 + 4334f0: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 4334f7: 0f 28 4e f9 movaps -0x7(%rsi),%xmm1 + 4334fb: 0f 28 56 09 movaps 0x9(%rsi),%xmm2 + 4334ff: 0f 28 5e 19 movaps 0x19(%rsi),%xmm3 + 433503: 0f 28 66 29 movaps 0x29(%rsi),%xmm4 + 433507: 0f 28 6e 39 movaps 0x39(%rsi),%xmm5 + 43350b: 0f 28 76 49 movaps 0x49(%rsi),%xmm6 + 43350f: 0f 28 7e 59 movaps 0x59(%rsi),%xmm7 + 433513: 44 0f 28 46 69 movaps 0x69(%rsi),%xmm8 + 433518: 44 0f 28 4e 79 movaps 0x79(%rsi),%xmm9 + 43351d: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi + 433524: 66 45 0f 3a 0f c8 07 palignr $0x7,%xmm8,%xmm9 + 43352b: 44 0f 29 4f 70 movaps %xmm9,0x70(%rdi) + 433530: 66 44 0f 3a 0f c7 07 palignr $0x7,%xmm7,%xmm8 + 433537: 44 0f 29 47 60 movaps %xmm8,0x60(%rdi) + 43353c: 66 0f 3a 0f fe 07 palignr $0x7,%xmm6,%xmm7 + 433542: 0f 29 7f 50 movaps %xmm7,0x50(%rdi) + 433546: 66 0f 3a 0f f5 07 palignr $0x7,%xmm5,%xmm6 + 43354c: 0f 29 77 40 movaps %xmm6,0x40(%rdi) + 433550: 66 0f 3a 0f ec 07 palignr $0x7,%xmm4,%xmm5 + 433556: 0f 29 6f 30 movaps %xmm5,0x30(%rdi) + 43355a: 66 0f 3a 0f e3 07 palignr $0x7,%xmm3,%xmm4 + 433560: 0f 29 67 20 movaps %xmm4,0x20(%rdi) + 433564: 66 0f 3a 0f da 07 palignr $0x7,%xmm2,%xmm3 + 43356a: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) + 43356e: 66 0f 3a 0f d1 07 palignr $0x7,%xmm1,%xmm2 + 433574: 0f 29 17 movaps %xmm2,(%rdi) + 433577: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi + 43357e: 0f 83 6c ff ff ff jae 4334f0 <__memmove_ssse3_back+0xb30> + 433584: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 433589: 48 81 c2 80 00 00 00 add $0x80,%rdx + 433590: 48 01 d7 add %rdx,%rdi + 433593: 48 01 d6 add %rdx,%rsi + 433596: 4c 8d 1d 13 02 07 00 lea 0x70213(%rip),%r11 # 4a37b0 + 43359d: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 4335a1: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 4335a5: ff e2 jmpq *%rdx + 4335a7: 0f 0b ud2 + 4335a9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4335b0: 0f 28 4e f9 movaps -0x7(%rsi),%xmm1 + 4335b4: 0f 28 56 e9 movaps -0x17(%rsi),%xmm2 + 4335b8: 66 0f 3a 0f ca 07 palignr $0x7,%xmm2,%xmm1 + 4335be: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 4335c2: 0f 28 5e d9 movaps -0x27(%rsi),%xmm3 + 4335c6: 66 0f 3a 0f d3 07 palignr $0x7,%xmm3,%xmm2 + 4335cc: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 4335d0: 0f 28 66 c9 movaps -0x37(%rsi),%xmm4 + 4335d4: 66 0f 3a 0f dc 07 palignr $0x7,%xmm4,%xmm3 + 4335da: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 4335de: 0f 28 6e b9 movaps -0x47(%rsi),%xmm5 + 4335e2: 66 0f 3a 0f e5 07 palignr $0x7,%xmm5,%xmm4 + 4335e8: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) + 4335ec: 0f 28 76 a9 movaps -0x57(%rsi),%xmm6 + 4335f0: 66 0f 3a 0f ee 07 palignr $0x7,%xmm6,%xmm5 + 4335f6: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) + 4335fa: 0f 28 7e 99 movaps -0x67(%rsi),%xmm7 + 4335fe: 66 0f 3a 0f f7 07 palignr $0x7,%xmm7,%xmm6 + 433604: 0f 29 77 a0 movaps %xmm6,-0x60(%rdi) + 433608: 44 0f 28 46 89 movaps -0x77(%rsi),%xmm8 + 43360d: 66 41 0f 3a 0f f8 07 palignr $0x7,%xmm8,%xmm7 + 433614: 0f 29 7f 90 movaps %xmm7,-0x70(%rdi) + 433618: 44 0f 28 8e 79 ff ff movaps -0x87(%rsi),%xmm9 + 43361f: ff + 433620: 66 45 0f 3a 0f c1 07 palignr $0x7,%xmm9,%xmm8 + 433627: 44 0f 29 47 80 movaps %xmm8,-0x80(%rdi) + 43362c: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 433633: 48 8d 7f 80 lea -0x80(%rdi),%rdi + 433637: 48 8d 76 80 lea -0x80(%rsi),%rsi + 43363b: 0f 83 6f ff ff ff jae 4335b0 <__memmove_ssse3_back+0xbf0> + 433641: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 433646: 48 81 c2 80 00 00 00 add $0x80,%rdx + 43364d: 48 29 d7 sub %rdx,%rdi + 433650: 48 29 d6 sub %rdx,%rsi + 433653: 4c 8d 1d 16 ff 06 00 lea 0x6ff16(%rip),%r11 # 4a3570 + 43365a: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 43365e: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 433662: ff e2 jmpq *%rdx + 433664: 0f 0b ud2 + 433666: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43366d: 00 00 00 + 433670: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 433677: 0f 28 4e f8 movaps -0x8(%rsi),%xmm1 + 43367b: 0f 28 56 08 movaps 0x8(%rsi),%xmm2 + 43367f: 0f 28 5e 18 movaps 0x18(%rsi),%xmm3 + 433683: 0f 28 66 28 movaps 0x28(%rsi),%xmm4 + 433687: 0f 28 6e 38 movaps 0x38(%rsi),%xmm5 + 43368b: 0f 28 76 48 movaps 0x48(%rsi),%xmm6 + 43368f: 0f 28 7e 58 movaps 0x58(%rsi),%xmm7 + 433693: 44 0f 28 46 68 movaps 0x68(%rsi),%xmm8 + 433698: 44 0f 28 4e 78 movaps 0x78(%rsi),%xmm9 + 43369d: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi + 4336a4: 66 45 0f 3a 0f c8 08 palignr $0x8,%xmm8,%xmm9 + 4336ab: 44 0f 29 4f 70 movaps %xmm9,0x70(%rdi) + 4336b0: 66 44 0f 3a 0f c7 08 palignr $0x8,%xmm7,%xmm8 + 4336b7: 44 0f 29 47 60 movaps %xmm8,0x60(%rdi) + 4336bc: 66 0f 3a 0f fe 08 palignr $0x8,%xmm6,%xmm7 + 4336c2: 0f 29 7f 50 movaps %xmm7,0x50(%rdi) + 4336c6: 66 0f 3a 0f f5 08 palignr $0x8,%xmm5,%xmm6 + 4336cc: 0f 29 77 40 movaps %xmm6,0x40(%rdi) + 4336d0: 66 0f 3a 0f ec 08 palignr $0x8,%xmm4,%xmm5 + 4336d6: 0f 29 6f 30 movaps %xmm5,0x30(%rdi) + 4336da: 66 0f 3a 0f e3 08 palignr $0x8,%xmm3,%xmm4 + 4336e0: 0f 29 67 20 movaps %xmm4,0x20(%rdi) + 4336e4: 66 0f 3a 0f da 08 palignr $0x8,%xmm2,%xmm3 + 4336ea: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) + 4336ee: 66 0f 3a 0f d1 08 palignr $0x8,%xmm1,%xmm2 + 4336f4: 0f 29 17 movaps %xmm2,(%rdi) + 4336f7: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi + 4336fe: 0f 83 6c ff ff ff jae 433670 <__memmove_ssse3_back+0xcb0> + 433704: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 433709: 48 81 c2 80 00 00 00 add $0x80,%rdx + 433710: 48 01 d7 add %rdx,%rdi + 433713: 48 01 d6 add %rdx,%rsi + 433716: 4c 8d 1d 93 00 07 00 lea 0x70093(%rip),%r11 # 4a37b0 + 43371d: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 433721: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 433725: ff e2 jmpq *%rdx + 433727: 0f 0b ud2 + 433729: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 433730: 0f 28 4e f8 movaps -0x8(%rsi),%xmm1 + 433734: 0f 28 56 e8 movaps -0x18(%rsi),%xmm2 + 433738: 66 0f 3a 0f ca 08 palignr $0x8,%xmm2,%xmm1 + 43373e: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 433742: 0f 28 5e d8 movaps -0x28(%rsi),%xmm3 + 433746: 66 0f 3a 0f d3 08 palignr $0x8,%xmm3,%xmm2 + 43374c: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 433750: 0f 28 66 c8 movaps -0x38(%rsi),%xmm4 + 433754: 66 0f 3a 0f dc 08 palignr $0x8,%xmm4,%xmm3 + 43375a: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 43375e: 0f 28 6e b8 movaps -0x48(%rsi),%xmm5 + 433762: 66 0f 3a 0f e5 08 palignr $0x8,%xmm5,%xmm4 + 433768: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) + 43376c: 0f 28 76 a8 movaps -0x58(%rsi),%xmm6 + 433770: 66 0f 3a 0f ee 08 palignr $0x8,%xmm6,%xmm5 + 433776: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) + 43377a: 0f 28 7e 98 movaps -0x68(%rsi),%xmm7 + 43377e: 66 0f 3a 0f f7 08 palignr $0x8,%xmm7,%xmm6 + 433784: 0f 29 77 a0 movaps %xmm6,-0x60(%rdi) + 433788: 44 0f 28 46 88 movaps -0x78(%rsi),%xmm8 + 43378d: 66 41 0f 3a 0f f8 08 palignr $0x8,%xmm8,%xmm7 + 433794: 0f 29 7f 90 movaps %xmm7,-0x70(%rdi) + 433798: 44 0f 28 8e 78 ff ff movaps -0x88(%rsi),%xmm9 + 43379f: ff + 4337a0: 66 45 0f 3a 0f c1 08 palignr $0x8,%xmm9,%xmm8 + 4337a7: 44 0f 29 47 80 movaps %xmm8,-0x80(%rdi) + 4337ac: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 4337b3: 48 8d 7f 80 lea -0x80(%rdi),%rdi + 4337b7: 48 8d 76 80 lea -0x80(%rsi),%rsi + 4337bb: 0f 83 6f ff ff ff jae 433730 <__memmove_ssse3_back+0xd70> + 4337c1: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 4337c6: 48 81 c2 80 00 00 00 add $0x80,%rdx + 4337cd: 48 29 d7 sub %rdx,%rdi + 4337d0: 48 29 d6 sub %rdx,%rsi + 4337d3: 4c 8d 1d 96 fd 06 00 lea 0x6fd96(%rip),%r11 # 4a3570 + 4337da: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 4337de: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 4337e2: ff e2 jmpq *%rdx + 4337e4: 0f 0b ud2 + 4337e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4337ed: 00 00 00 + 4337f0: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 4337f7: 0f 28 4e f7 movaps -0x9(%rsi),%xmm1 + 4337fb: 0f 28 56 07 movaps 0x7(%rsi),%xmm2 + 4337ff: 0f 28 5e 17 movaps 0x17(%rsi),%xmm3 + 433803: 0f 28 66 27 movaps 0x27(%rsi),%xmm4 + 433807: 0f 28 6e 37 movaps 0x37(%rsi),%xmm5 + 43380b: 0f 28 76 47 movaps 0x47(%rsi),%xmm6 + 43380f: 0f 28 7e 57 movaps 0x57(%rsi),%xmm7 + 433813: 44 0f 28 46 67 movaps 0x67(%rsi),%xmm8 + 433818: 44 0f 28 4e 77 movaps 0x77(%rsi),%xmm9 + 43381d: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi + 433824: 66 45 0f 3a 0f c8 09 palignr $0x9,%xmm8,%xmm9 + 43382b: 44 0f 29 4f 70 movaps %xmm9,0x70(%rdi) + 433830: 66 44 0f 3a 0f c7 09 palignr $0x9,%xmm7,%xmm8 + 433837: 44 0f 29 47 60 movaps %xmm8,0x60(%rdi) + 43383c: 66 0f 3a 0f fe 09 palignr $0x9,%xmm6,%xmm7 + 433842: 0f 29 7f 50 movaps %xmm7,0x50(%rdi) + 433846: 66 0f 3a 0f f5 09 palignr $0x9,%xmm5,%xmm6 + 43384c: 0f 29 77 40 movaps %xmm6,0x40(%rdi) + 433850: 66 0f 3a 0f ec 09 palignr $0x9,%xmm4,%xmm5 + 433856: 0f 29 6f 30 movaps %xmm5,0x30(%rdi) + 43385a: 66 0f 3a 0f e3 09 palignr $0x9,%xmm3,%xmm4 + 433860: 0f 29 67 20 movaps %xmm4,0x20(%rdi) + 433864: 66 0f 3a 0f da 09 palignr $0x9,%xmm2,%xmm3 + 43386a: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) + 43386e: 66 0f 3a 0f d1 09 palignr $0x9,%xmm1,%xmm2 + 433874: 0f 29 17 movaps %xmm2,(%rdi) + 433877: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi + 43387e: 0f 83 6c ff ff ff jae 4337f0 <__memmove_ssse3_back+0xe30> + 433884: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 433889: 48 81 c2 80 00 00 00 add $0x80,%rdx + 433890: 48 01 d7 add %rdx,%rdi + 433893: 48 01 d6 add %rdx,%rsi + 433896: 4c 8d 1d 13 ff 06 00 lea 0x6ff13(%rip),%r11 # 4a37b0 + 43389d: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 4338a1: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 4338a5: ff e2 jmpq *%rdx + 4338a7: 0f 0b ud2 + 4338a9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4338b0: 0f 28 4e f7 movaps -0x9(%rsi),%xmm1 + 4338b4: 0f 28 56 e7 movaps -0x19(%rsi),%xmm2 + 4338b8: 66 0f 3a 0f ca 09 palignr $0x9,%xmm2,%xmm1 + 4338be: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 4338c2: 0f 28 5e d7 movaps -0x29(%rsi),%xmm3 + 4338c6: 66 0f 3a 0f d3 09 palignr $0x9,%xmm3,%xmm2 + 4338cc: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 4338d0: 0f 28 66 c7 movaps -0x39(%rsi),%xmm4 + 4338d4: 66 0f 3a 0f dc 09 palignr $0x9,%xmm4,%xmm3 + 4338da: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 4338de: 0f 28 6e b7 movaps -0x49(%rsi),%xmm5 + 4338e2: 66 0f 3a 0f e5 09 palignr $0x9,%xmm5,%xmm4 + 4338e8: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) + 4338ec: 0f 28 76 a7 movaps -0x59(%rsi),%xmm6 + 4338f0: 66 0f 3a 0f ee 09 palignr $0x9,%xmm6,%xmm5 + 4338f6: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) + 4338fa: 0f 28 7e 97 movaps -0x69(%rsi),%xmm7 + 4338fe: 66 0f 3a 0f f7 09 palignr $0x9,%xmm7,%xmm6 + 433904: 0f 29 77 a0 movaps %xmm6,-0x60(%rdi) + 433908: 44 0f 28 46 87 movaps -0x79(%rsi),%xmm8 + 43390d: 66 41 0f 3a 0f f8 09 palignr $0x9,%xmm8,%xmm7 + 433914: 0f 29 7f 90 movaps %xmm7,-0x70(%rdi) + 433918: 44 0f 28 8e 77 ff ff movaps -0x89(%rsi),%xmm9 + 43391f: ff + 433920: 66 45 0f 3a 0f c1 09 palignr $0x9,%xmm9,%xmm8 + 433927: 44 0f 29 47 80 movaps %xmm8,-0x80(%rdi) + 43392c: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 433933: 48 8d 7f 80 lea -0x80(%rdi),%rdi + 433937: 48 8d 76 80 lea -0x80(%rsi),%rsi + 43393b: 0f 83 6f ff ff ff jae 4338b0 <__memmove_ssse3_back+0xef0> + 433941: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 433946: 48 81 c2 80 00 00 00 add $0x80,%rdx + 43394d: 48 29 d7 sub %rdx,%rdi + 433950: 48 29 d6 sub %rdx,%rsi + 433953: 4c 8d 1d 16 fc 06 00 lea 0x6fc16(%rip),%r11 # 4a3570 + 43395a: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 43395e: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 433962: ff e2 jmpq *%rdx + 433964: 0f 0b ud2 + 433966: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43396d: 00 00 00 + 433970: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 433977: 0f 28 4e f6 movaps -0xa(%rsi),%xmm1 + 43397b: 0f 28 56 06 movaps 0x6(%rsi),%xmm2 + 43397f: 0f 28 5e 16 movaps 0x16(%rsi),%xmm3 + 433983: 0f 28 66 26 movaps 0x26(%rsi),%xmm4 + 433987: 0f 28 6e 36 movaps 0x36(%rsi),%xmm5 + 43398b: 0f 28 76 46 movaps 0x46(%rsi),%xmm6 + 43398f: 0f 28 7e 56 movaps 0x56(%rsi),%xmm7 + 433993: 44 0f 28 46 66 movaps 0x66(%rsi),%xmm8 + 433998: 44 0f 28 4e 76 movaps 0x76(%rsi),%xmm9 + 43399d: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi + 4339a4: 66 45 0f 3a 0f c8 0a palignr $0xa,%xmm8,%xmm9 + 4339ab: 44 0f 29 4f 70 movaps %xmm9,0x70(%rdi) + 4339b0: 66 44 0f 3a 0f c7 0a palignr $0xa,%xmm7,%xmm8 + 4339b7: 44 0f 29 47 60 movaps %xmm8,0x60(%rdi) + 4339bc: 66 0f 3a 0f fe 0a palignr $0xa,%xmm6,%xmm7 + 4339c2: 0f 29 7f 50 movaps %xmm7,0x50(%rdi) + 4339c6: 66 0f 3a 0f f5 0a palignr $0xa,%xmm5,%xmm6 + 4339cc: 0f 29 77 40 movaps %xmm6,0x40(%rdi) + 4339d0: 66 0f 3a 0f ec 0a palignr $0xa,%xmm4,%xmm5 + 4339d6: 0f 29 6f 30 movaps %xmm5,0x30(%rdi) + 4339da: 66 0f 3a 0f e3 0a palignr $0xa,%xmm3,%xmm4 + 4339e0: 0f 29 67 20 movaps %xmm4,0x20(%rdi) + 4339e4: 66 0f 3a 0f da 0a palignr $0xa,%xmm2,%xmm3 + 4339ea: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) + 4339ee: 66 0f 3a 0f d1 0a palignr $0xa,%xmm1,%xmm2 + 4339f4: 0f 29 17 movaps %xmm2,(%rdi) + 4339f7: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi + 4339fe: 0f 83 6c ff ff ff jae 433970 <__memmove_ssse3_back+0xfb0> + 433a04: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 433a09: 48 81 c2 80 00 00 00 add $0x80,%rdx + 433a10: 48 01 d7 add %rdx,%rdi + 433a13: 48 01 d6 add %rdx,%rsi + 433a16: 4c 8d 1d 93 fd 06 00 lea 0x6fd93(%rip),%r11 # 4a37b0 + 433a1d: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 433a21: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 433a25: ff e2 jmpq *%rdx + 433a27: 0f 0b ud2 + 433a29: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 433a30: 0f 28 4e f6 movaps -0xa(%rsi),%xmm1 + 433a34: 0f 28 56 e6 movaps -0x1a(%rsi),%xmm2 + 433a38: 66 0f 3a 0f ca 0a palignr $0xa,%xmm2,%xmm1 + 433a3e: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 433a42: 0f 28 5e d6 movaps -0x2a(%rsi),%xmm3 + 433a46: 66 0f 3a 0f d3 0a palignr $0xa,%xmm3,%xmm2 + 433a4c: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 433a50: 0f 28 66 c6 movaps -0x3a(%rsi),%xmm4 + 433a54: 66 0f 3a 0f dc 0a palignr $0xa,%xmm4,%xmm3 + 433a5a: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 433a5e: 0f 28 6e b6 movaps -0x4a(%rsi),%xmm5 + 433a62: 66 0f 3a 0f e5 0a palignr $0xa,%xmm5,%xmm4 + 433a68: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) + 433a6c: 0f 28 76 a6 movaps -0x5a(%rsi),%xmm6 + 433a70: 66 0f 3a 0f ee 0a palignr $0xa,%xmm6,%xmm5 + 433a76: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) + 433a7a: 0f 28 7e 96 movaps -0x6a(%rsi),%xmm7 + 433a7e: 66 0f 3a 0f f7 0a palignr $0xa,%xmm7,%xmm6 + 433a84: 0f 29 77 a0 movaps %xmm6,-0x60(%rdi) + 433a88: 44 0f 28 46 86 movaps -0x7a(%rsi),%xmm8 + 433a8d: 66 41 0f 3a 0f f8 0a palignr $0xa,%xmm8,%xmm7 + 433a94: 0f 29 7f 90 movaps %xmm7,-0x70(%rdi) + 433a98: 44 0f 28 8e 76 ff ff movaps -0x8a(%rsi),%xmm9 + 433a9f: ff + 433aa0: 66 45 0f 3a 0f c1 0a palignr $0xa,%xmm9,%xmm8 + 433aa7: 44 0f 29 47 80 movaps %xmm8,-0x80(%rdi) + 433aac: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 433ab3: 48 8d 7f 80 lea -0x80(%rdi),%rdi + 433ab7: 48 8d 76 80 lea -0x80(%rsi),%rsi + 433abb: 0f 83 6f ff ff ff jae 433a30 <__memmove_ssse3_back+0x1070> + 433ac1: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 433ac6: 48 81 c2 80 00 00 00 add $0x80,%rdx + 433acd: 48 29 d7 sub %rdx,%rdi + 433ad0: 48 29 d6 sub %rdx,%rsi + 433ad3: 4c 8d 1d 96 fa 06 00 lea 0x6fa96(%rip),%r11 # 4a3570 + 433ada: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 433ade: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 433ae2: ff e2 jmpq *%rdx + 433ae4: 0f 0b ud2 + 433ae6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 433aed: 00 00 00 + 433af0: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 433af7: 0f 28 4e f5 movaps -0xb(%rsi),%xmm1 + 433afb: 0f 28 56 05 movaps 0x5(%rsi),%xmm2 + 433aff: 0f 28 5e 15 movaps 0x15(%rsi),%xmm3 + 433b03: 0f 28 66 25 movaps 0x25(%rsi),%xmm4 + 433b07: 0f 28 6e 35 movaps 0x35(%rsi),%xmm5 + 433b0b: 0f 28 76 45 movaps 0x45(%rsi),%xmm6 + 433b0f: 0f 28 7e 55 movaps 0x55(%rsi),%xmm7 + 433b13: 44 0f 28 46 65 movaps 0x65(%rsi),%xmm8 + 433b18: 44 0f 28 4e 75 movaps 0x75(%rsi),%xmm9 + 433b1d: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi + 433b24: 66 45 0f 3a 0f c8 0b palignr $0xb,%xmm8,%xmm9 + 433b2b: 44 0f 29 4f 70 movaps %xmm9,0x70(%rdi) + 433b30: 66 44 0f 3a 0f c7 0b palignr $0xb,%xmm7,%xmm8 + 433b37: 44 0f 29 47 60 movaps %xmm8,0x60(%rdi) + 433b3c: 66 0f 3a 0f fe 0b palignr $0xb,%xmm6,%xmm7 + 433b42: 0f 29 7f 50 movaps %xmm7,0x50(%rdi) + 433b46: 66 0f 3a 0f f5 0b palignr $0xb,%xmm5,%xmm6 + 433b4c: 0f 29 77 40 movaps %xmm6,0x40(%rdi) + 433b50: 66 0f 3a 0f ec 0b palignr $0xb,%xmm4,%xmm5 + 433b56: 0f 29 6f 30 movaps %xmm5,0x30(%rdi) + 433b5a: 66 0f 3a 0f e3 0b palignr $0xb,%xmm3,%xmm4 + 433b60: 0f 29 67 20 movaps %xmm4,0x20(%rdi) + 433b64: 66 0f 3a 0f da 0b palignr $0xb,%xmm2,%xmm3 + 433b6a: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) + 433b6e: 66 0f 3a 0f d1 0b palignr $0xb,%xmm1,%xmm2 + 433b74: 0f 29 17 movaps %xmm2,(%rdi) + 433b77: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi + 433b7e: 0f 83 6c ff ff ff jae 433af0 <__memmove_ssse3_back+0x1130> + 433b84: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 433b89: 48 81 c2 80 00 00 00 add $0x80,%rdx + 433b90: 48 01 d7 add %rdx,%rdi + 433b93: 48 01 d6 add %rdx,%rsi + 433b96: 4c 8d 1d 13 fc 06 00 lea 0x6fc13(%rip),%r11 # 4a37b0 + 433b9d: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 433ba1: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 433ba5: ff e2 jmpq *%rdx + 433ba7: 0f 0b ud2 + 433ba9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 433bb0: 0f 28 4e f5 movaps -0xb(%rsi),%xmm1 + 433bb4: 0f 28 56 e5 movaps -0x1b(%rsi),%xmm2 + 433bb8: 66 0f 3a 0f ca 0b palignr $0xb,%xmm2,%xmm1 + 433bbe: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 433bc2: 0f 28 5e d5 movaps -0x2b(%rsi),%xmm3 + 433bc6: 66 0f 3a 0f d3 0b palignr $0xb,%xmm3,%xmm2 + 433bcc: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 433bd0: 0f 28 66 c5 movaps -0x3b(%rsi),%xmm4 + 433bd4: 66 0f 3a 0f dc 0b palignr $0xb,%xmm4,%xmm3 + 433bda: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 433bde: 0f 28 6e b5 movaps -0x4b(%rsi),%xmm5 + 433be2: 66 0f 3a 0f e5 0b palignr $0xb,%xmm5,%xmm4 + 433be8: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) + 433bec: 0f 28 76 a5 movaps -0x5b(%rsi),%xmm6 + 433bf0: 66 0f 3a 0f ee 0b palignr $0xb,%xmm6,%xmm5 + 433bf6: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) + 433bfa: 0f 28 7e 95 movaps -0x6b(%rsi),%xmm7 + 433bfe: 66 0f 3a 0f f7 0b palignr $0xb,%xmm7,%xmm6 + 433c04: 0f 29 77 a0 movaps %xmm6,-0x60(%rdi) + 433c08: 44 0f 28 46 85 movaps -0x7b(%rsi),%xmm8 + 433c0d: 66 41 0f 3a 0f f8 0b palignr $0xb,%xmm8,%xmm7 + 433c14: 0f 29 7f 90 movaps %xmm7,-0x70(%rdi) + 433c18: 44 0f 28 8e 75 ff ff movaps -0x8b(%rsi),%xmm9 + 433c1f: ff + 433c20: 66 45 0f 3a 0f c1 0b palignr $0xb,%xmm9,%xmm8 + 433c27: 44 0f 29 47 80 movaps %xmm8,-0x80(%rdi) + 433c2c: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 433c33: 48 8d 7f 80 lea -0x80(%rdi),%rdi + 433c37: 48 8d 76 80 lea -0x80(%rsi),%rsi + 433c3b: 0f 83 6f ff ff ff jae 433bb0 <__memmove_ssse3_back+0x11f0> + 433c41: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 433c46: 48 81 c2 80 00 00 00 add $0x80,%rdx + 433c4d: 48 29 d7 sub %rdx,%rdi + 433c50: 48 29 d6 sub %rdx,%rsi + 433c53: 4c 8d 1d 16 f9 06 00 lea 0x6f916(%rip),%r11 # 4a3570 + 433c5a: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 433c5e: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 433c62: ff e2 jmpq *%rdx + 433c64: 0f 0b ud2 + 433c66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 433c6d: 00 00 00 + 433c70: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 433c77: 66 0f 6f 4e f4 movdqa -0xc(%rsi),%xmm1 + 433c7c: 0f 28 56 04 movaps 0x4(%rsi),%xmm2 + 433c80: 0f 28 5e 14 movaps 0x14(%rsi),%xmm3 + 433c84: 0f 28 66 24 movaps 0x24(%rsi),%xmm4 + 433c88: 0f 28 6e 34 movaps 0x34(%rsi),%xmm5 + 433c8c: 0f 28 76 44 movaps 0x44(%rsi),%xmm6 + 433c90: 0f 28 7e 54 movaps 0x54(%rsi),%xmm7 + 433c94: 44 0f 28 46 64 movaps 0x64(%rsi),%xmm8 + 433c99: 44 0f 28 4e 74 movaps 0x74(%rsi),%xmm9 + 433c9e: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi + 433ca5: 66 45 0f 3a 0f c8 0c palignr $0xc,%xmm8,%xmm9 + 433cac: 44 0f 29 4f 70 movaps %xmm9,0x70(%rdi) + 433cb1: 66 44 0f 3a 0f c7 0c palignr $0xc,%xmm7,%xmm8 + 433cb8: 44 0f 29 47 60 movaps %xmm8,0x60(%rdi) + 433cbd: 66 0f 3a 0f fe 0c palignr $0xc,%xmm6,%xmm7 + 433cc3: 0f 29 7f 50 movaps %xmm7,0x50(%rdi) + 433cc7: 66 0f 3a 0f f5 0c palignr $0xc,%xmm5,%xmm6 + 433ccd: 0f 29 77 40 movaps %xmm6,0x40(%rdi) + 433cd1: 66 0f 3a 0f ec 0c palignr $0xc,%xmm4,%xmm5 + 433cd7: 0f 29 6f 30 movaps %xmm5,0x30(%rdi) + 433cdb: 66 0f 3a 0f e3 0c palignr $0xc,%xmm3,%xmm4 + 433ce1: 0f 29 67 20 movaps %xmm4,0x20(%rdi) + 433ce5: 66 0f 3a 0f da 0c palignr $0xc,%xmm2,%xmm3 + 433ceb: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) + 433cef: 66 0f 3a 0f d1 0c palignr $0xc,%xmm1,%xmm2 + 433cf5: 0f 29 17 movaps %xmm2,(%rdi) + 433cf8: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi + 433cff: 0f 83 6b ff ff ff jae 433c70 <__memmove_ssse3_back+0x12b0> + 433d05: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 433d0a: 48 81 c2 80 00 00 00 add $0x80,%rdx + 433d11: 48 01 d7 add %rdx,%rdi + 433d14: 48 01 d6 add %rdx,%rsi + 433d17: 4c 8d 1d 92 fa 06 00 lea 0x6fa92(%rip),%r11 # 4a37b0 + 433d1e: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 433d22: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 433d26: ff e2 jmpq *%rdx + 433d28: 0f 0b ud2 + 433d2a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 433d30: 0f 28 4e f4 movaps -0xc(%rsi),%xmm1 + 433d34: 0f 28 56 e4 movaps -0x1c(%rsi),%xmm2 + 433d38: 66 0f 3a 0f ca 0c palignr $0xc,%xmm2,%xmm1 + 433d3e: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 433d42: 0f 28 5e d4 movaps -0x2c(%rsi),%xmm3 + 433d46: 66 0f 3a 0f d3 0c palignr $0xc,%xmm3,%xmm2 + 433d4c: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 433d50: 0f 28 66 c4 movaps -0x3c(%rsi),%xmm4 + 433d54: 66 0f 3a 0f dc 0c palignr $0xc,%xmm4,%xmm3 + 433d5a: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 433d5e: 0f 28 6e b4 movaps -0x4c(%rsi),%xmm5 + 433d62: 66 0f 3a 0f e5 0c palignr $0xc,%xmm5,%xmm4 + 433d68: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) + 433d6c: 0f 28 76 a4 movaps -0x5c(%rsi),%xmm6 + 433d70: 66 0f 3a 0f ee 0c palignr $0xc,%xmm6,%xmm5 + 433d76: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) + 433d7a: 0f 28 7e 94 movaps -0x6c(%rsi),%xmm7 + 433d7e: 66 0f 3a 0f f7 0c palignr $0xc,%xmm7,%xmm6 + 433d84: 0f 29 77 a0 movaps %xmm6,-0x60(%rdi) + 433d88: 44 0f 28 46 84 movaps -0x7c(%rsi),%xmm8 + 433d8d: 66 41 0f 3a 0f f8 0c palignr $0xc,%xmm8,%xmm7 + 433d94: 0f 29 7f 90 movaps %xmm7,-0x70(%rdi) + 433d98: 44 0f 28 8e 74 ff ff movaps -0x8c(%rsi),%xmm9 + 433d9f: ff + 433da0: 66 45 0f 3a 0f c1 0c palignr $0xc,%xmm9,%xmm8 + 433da7: 44 0f 29 47 80 movaps %xmm8,-0x80(%rdi) + 433dac: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 433db3: 48 8d 7f 80 lea -0x80(%rdi),%rdi + 433db7: 48 8d 76 80 lea -0x80(%rsi),%rsi + 433dbb: 0f 83 6f ff ff ff jae 433d30 <__memmove_ssse3_back+0x1370> + 433dc1: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 433dc6: 48 81 c2 80 00 00 00 add $0x80,%rdx + 433dcd: 48 29 d7 sub %rdx,%rdi + 433dd0: 48 29 d6 sub %rdx,%rsi + 433dd3: 4c 8d 1d 96 f7 06 00 lea 0x6f796(%rip),%r11 # 4a3570 + 433dda: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 433dde: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 433de2: ff e2 jmpq *%rdx + 433de4: 0f 0b ud2 + 433de6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 433ded: 00 00 00 + 433df0: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 433df7: 0f 28 4e f3 movaps -0xd(%rsi),%xmm1 + 433dfb: 0f 28 56 03 movaps 0x3(%rsi),%xmm2 + 433dff: 0f 28 5e 13 movaps 0x13(%rsi),%xmm3 + 433e03: 0f 28 66 23 movaps 0x23(%rsi),%xmm4 + 433e07: 0f 28 6e 33 movaps 0x33(%rsi),%xmm5 + 433e0b: 0f 28 76 43 movaps 0x43(%rsi),%xmm6 + 433e0f: 0f 28 7e 53 movaps 0x53(%rsi),%xmm7 + 433e13: 44 0f 28 46 63 movaps 0x63(%rsi),%xmm8 + 433e18: 44 0f 28 4e 73 movaps 0x73(%rsi),%xmm9 + 433e1d: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi + 433e24: 66 45 0f 3a 0f c8 0d palignr $0xd,%xmm8,%xmm9 + 433e2b: 44 0f 29 4f 70 movaps %xmm9,0x70(%rdi) + 433e30: 66 44 0f 3a 0f c7 0d palignr $0xd,%xmm7,%xmm8 + 433e37: 44 0f 29 47 60 movaps %xmm8,0x60(%rdi) + 433e3c: 66 0f 3a 0f fe 0d palignr $0xd,%xmm6,%xmm7 + 433e42: 0f 29 7f 50 movaps %xmm7,0x50(%rdi) + 433e46: 66 0f 3a 0f f5 0d palignr $0xd,%xmm5,%xmm6 + 433e4c: 0f 29 77 40 movaps %xmm6,0x40(%rdi) + 433e50: 66 0f 3a 0f ec 0d palignr $0xd,%xmm4,%xmm5 + 433e56: 0f 29 6f 30 movaps %xmm5,0x30(%rdi) + 433e5a: 66 0f 3a 0f e3 0d palignr $0xd,%xmm3,%xmm4 + 433e60: 0f 29 67 20 movaps %xmm4,0x20(%rdi) + 433e64: 66 0f 3a 0f da 0d palignr $0xd,%xmm2,%xmm3 + 433e6a: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) + 433e6e: 66 0f 3a 0f d1 0d palignr $0xd,%xmm1,%xmm2 + 433e74: 0f 29 17 movaps %xmm2,(%rdi) + 433e77: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi + 433e7e: 0f 83 6c ff ff ff jae 433df0 <__memmove_ssse3_back+0x1430> + 433e84: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 433e89: 48 81 c2 80 00 00 00 add $0x80,%rdx + 433e90: 48 01 d7 add %rdx,%rdi + 433e93: 48 01 d6 add %rdx,%rsi + 433e96: 4c 8d 1d 13 f9 06 00 lea 0x6f913(%rip),%r11 # 4a37b0 + 433e9d: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 433ea1: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 433ea5: ff e2 jmpq *%rdx + 433ea7: 0f 0b ud2 + 433ea9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 433eb0: 0f 28 4e f3 movaps -0xd(%rsi),%xmm1 + 433eb4: 0f 28 56 e3 movaps -0x1d(%rsi),%xmm2 + 433eb8: 66 0f 3a 0f ca 0d palignr $0xd,%xmm2,%xmm1 + 433ebe: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 433ec2: 0f 28 5e d3 movaps -0x2d(%rsi),%xmm3 + 433ec6: 66 0f 3a 0f d3 0d palignr $0xd,%xmm3,%xmm2 + 433ecc: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 433ed0: 0f 28 66 c3 movaps -0x3d(%rsi),%xmm4 + 433ed4: 66 0f 3a 0f dc 0d palignr $0xd,%xmm4,%xmm3 + 433eda: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 433ede: 0f 28 6e b3 movaps -0x4d(%rsi),%xmm5 + 433ee2: 66 0f 3a 0f e5 0d palignr $0xd,%xmm5,%xmm4 + 433ee8: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) + 433eec: 0f 28 76 a3 movaps -0x5d(%rsi),%xmm6 + 433ef0: 66 0f 3a 0f ee 0d palignr $0xd,%xmm6,%xmm5 + 433ef6: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) + 433efa: 0f 28 7e 93 movaps -0x6d(%rsi),%xmm7 + 433efe: 66 0f 3a 0f f7 0d palignr $0xd,%xmm7,%xmm6 + 433f04: 0f 29 77 a0 movaps %xmm6,-0x60(%rdi) + 433f08: 44 0f 28 46 83 movaps -0x7d(%rsi),%xmm8 + 433f0d: 66 41 0f 3a 0f f8 0d palignr $0xd,%xmm8,%xmm7 + 433f14: 0f 29 7f 90 movaps %xmm7,-0x70(%rdi) + 433f18: 44 0f 28 8e 73 ff ff movaps -0x8d(%rsi),%xmm9 + 433f1f: ff + 433f20: 66 45 0f 3a 0f c1 0d palignr $0xd,%xmm9,%xmm8 + 433f27: 44 0f 29 47 80 movaps %xmm8,-0x80(%rdi) + 433f2c: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 433f33: 48 8d 7f 80 lea -0x80(%rdi),%rdi + 433f37: 48 8d 76 80 lea -0x80(%rsi),%rsi + 433f3b: 0f 83 6f ff ff ff jae 433eb0 <__memmove_ssse3_back+0x14f0> + 433f41: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 433f46: 48 81 c2 80 00 00 00 add $0x80,%rdx + 433f4d: 48 29 d7 sub %rdx,%rdi + 433f50: 48 29 d6 sub %rdx,%rsi + 433f53: 4c 8d 1d 16 f6 06 00 lea 0x6f616(%rip),%r11 # 4a3570 + 433f5a: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 433f5e: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 433f62: ff e2 jmpq *%rdx + 433f64: 0f 0b ud2 + 433f66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 433f6d: 00 00 00 + 433f70: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 433f77: 0f 28 4e f2 movaps -0xe(%rsi),%xmm1 + 433f7b: 0f 28 56 02 movaps 0x2(%rsi),%xmm2 + 433f7f: 0f 28 5e 12 movaps 0x12(%rsi),%xmm3 + 433f83: 0f 28 66 22 movaps 0x22(%rsi),%xmm4 + 433f87: 0f 28 6e 32 movaps 0x32(%rsi),%xmm5 + 433f8b: 0f 28 76 42 movaps 0x42(%rsi),%xmm6 + 433f8f: 0f 28 7e 52 movaps 0x52(%rsi),%xmm7 + 433f93: 44 0f 28 46 62 movaps 0x62(%rsi),%xmm8 + 433f98: 44 0f 28 4e 72 movaps 0x72(%rsi),%xmm9 + 433f9d: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi + 433fa4: 66 45 0f 3a 0f c8 0e palignr $0xe,%xmm8,%xmm9 + 433fab: 44 0f 29 4f 70 movaps %xmm9,0x70(%rdi) + 433fb0: 66 44 0f 3a 0f c7 0e palignr $0xe,%xmm7,%xmm8 + 433fb7: 44 0f 29 47 60 movaps %xmm8,0x60(%rdi) + 433fbc: 66 0f 3a 0f fe 0e palignr $0xe,%xmm6,%xmm7 + 433fc2: 0f 29 7f 50 movaps %xmm7,0x50(%rdi) + 433fc6: 66 0f 3a 0f f5 0e palignr $0xe,%xmm5,%xmm6 + 433fcc: 0f 29 77 40 movaps %xmm6,0x40(%rdi) + 433fd0: 66 0f 3a 0f ec 0e palignr $0xe,%xmm4,%xmm5 + 433fd6: 0f 29 6f 30 movaps %xmm5,0x30(%rdi) + 433fda: 66 0f 3a 0f e3 0e palignr $0xe,%xmm3,%xmm4 + 433fe0: 0f 29 67 20 movaps %xmm4,0x20(%rdi) + 433fe4: 66 0f 3a 0f da 0e palignr $0xe,%xmm2,%xmm3 + 433fea: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) + 433fee: 66 0f 3a 0f d1 0e palignr $0xe,%xmm1,%xmm2 + 433ff4: 0f 29 17 movaps %xmm2,(%rdi) + 433ff7: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi + 433ffe: 0f 83 6c ff ff ff jae 433f70 <__memmove_ssse3_back+0x15b0> + 434004: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 434009: 48 81 c2 80 00 00 00 add $0x80,%rdx + 434010: 48 01 d7 add %rdx,%rdi + 434013: 48 01 d6 add %rdx,%rsi + 434016: 4c 8d 1d 93 f7 06 00 lea 0x6f793(%rip),%r11 # 4a37b0 + 43401d: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 434021: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 434025: ff e2 jmpq *%rdx + 434027: 0f 0b ud2 + 434029: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 434030: 0f 28 4e f2 movaps -0xe(%rsi),%xmm1 + 434034: 0f 28 56 e2 movaps -0x1e(%rsi),%xmm2 + 434038: 66 0f 3a 0f ca 0e palignr $0xe,%xmm2,%xmm1 + 43403e: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 434042: 0f 28 5e d2 movaps -0x2e(%rsi),%xmm3 + 434046: 66 0f 3a 0f d3 0e palignr $0xe,%xmm3,%xmm2 + 43404c: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 434050: 0f 28 66 c2 movaps -0x3e(%rsi),%xmm4 + 434054: 66 0f 3a 0f dc 0e palignr $0xe,%xmm4,%xmm3 + 43405a: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 43405e: 0f 28 6e b2 movaps -0x4e(%rsi),%xmm5 + 434062: 66 0f 3a 0f e5 0e palignr $0xe,%xmm5,%xmm4 + 434068: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) + 43406c: 0f 28 76 a2 movaps -0x5e(%rsi),%xmm6 + 434070: 66 0f 3a 0f ee 0e palignr $0xe,%xmm6,%xmm5 + 434076: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) + 43407a: 0f 28 7e 92 movaps -0x6e(%rsi),%xmm7 + 43407e: 66 0f 3a 0f f7 0e palignr $0xe,%xmm7,%xmm6 + 434084: 0f 29 77 a0 movaps %xmm6,-0x60(%rdi) + 434088: 44 0f 28 46 82 movaps -0x7e(%rsi),%xmm8 + 43408d: 66 41 0f 3a 0f f8 0e palignr $0xe,%xmm8,%xmm7 + 434094: 0f 29 7f 90 movaps %xmm7,-0x70(%rdi) + 434098: 44 0f 28 8e 72 ff ff movaps -0x8e(%rsi),%xmm9 + 43409f: ff + 4340a0: 66 45 0f 3a 0f c1 0e palignr $0xe,%xmm9,%xmm8 + 4340a7: 44 0f 29 47 80 movaps %xmm8,-0x80(%rdi) + 4340ac: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 4340b3: 48 8d 7f 80 lea -0x80(%rdi),%rdi + 4340b7: 48 8d 76 80 lea -0x80(%rsi),%rsi + 4340bb: 0f 83 6f ff ff ff jae 434030 <__memmove_ssse3_back+0x1670> + 4340c1: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 4340c6: 48 81 c2 80 00 00 00 add $0x80,%rdx + 4340cd: 48 29 d7 sub %rdx,%rdi + 4340d0: 48 29 d6 sub %rdx,%rsi + 4340d3: 4c 8d 1d 96 f4 06 00 lea 0x6f496(%rip),%r11 # 4a3570 + 4340da: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 4340de: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 4340e2: ff e2 jmpq *%rdx + 4340e4: 0f 0b ud2 + 4340e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4340ed: 00 00 00 + 4340f0: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 4340f7: 0f 28 4e f1 movaps -0xf(%rsi),%xmm1 + 4340fb: 0f 28 56 01 movaps 0x1(%rsi),%xmm2 + 4340ff: 0f 28 5e 11 movaps 0x11(%rsi),%xmm3 + 434103: 0f 28 66 21 movaps 0x21(%rsi),%xmm4 + 434107: 0f 28 6e 31 movaps 0x31(%rsi),%xmm5 + 43410b: 0f 28 76 41 movaps 0x41(%rsi),%xmm6 + 43410f: 0f 28 7e 51 movaps 0x51(%rsi),%xmm7 + 434113: 44 0f 28 46 61 movaps 0x61(%rsi),%xmm8 + 434118: 44 0f 28 4e 71 movaps 0x71(%rsi),%xmm9 + 43411d: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi + 434124: 66 45 0f 3a 0f c8 0f palignr $0xf,%xmm8,%xmm9 + 43412b: 44 0f 29 4f 70 movaps %xmm9,0x70(%rdi) + 434130: 66 44 0f 3a 0f c7 0f palignr $0xf,%xmm7,%xmm8 + 434137: 44 0f 29 47 60 movaps %xmm8,0x60(%rdi) + 43413c: 66 0f 3a 0f fe 0f palignr $0xf,%xmm6,%xmm7 + 434142: 0f 29 7f 50 movaps %xmm7,0x50(%rdi) + 434146: 66 0f 3a 0f f5 0f palignr $0xf,%xmm5,%xmm6 + 43414c: 0f 29 77 40 movaps %xmm6,0x40(%rdi) + 434150: 66 0f 3a 0f ec 0f palignr $0xf,%xmm4,%xmm5 + 434156: 0f 29 6f 30 movaps %xmm5,0x30(%rdi) + 43415a: 66 0f 3a 0f e3 0f palignr $0xf,%xmm3,%xmm4 + 434160: 0f 29 67 20 movaps %xmm4,0x20(%rdi) + 434164: 66 0f 3a 0f da 0f palignr $0xf,%xmm2,%xmm3 + 43416a: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) + 43416e: 66 0f 3a 0f d1 0f palignr $0xf,%xmm1,%xmm2 + 434174: 0f 29 17 movaps %xmm2,(%rdi) + 434177: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi + 43417e: 0f 83 6c ff ff ff jae 4340f0 <__memmove_ssse3_back+0x1730> + 434184: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 434189: 48 81 c2 80 00 00 00 add $0x80,%rdx + 434190: 48 01 d7 add %rdx,%rdi + 434193: 48 01 d6 add %rdx,%rsi + 434196: 4c 8d 1d 13 f6 06 00 lea 0x6f613(%rip),%r11 # 4a37b0 + 43419d: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 4341a1: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 4341a5: ff e2 jmpq *%rdx + 4341a7: 0f 0b ud2 + 4341a9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4341b0: 0f 28 4e f1 movaps -0xf(%rsi),%xmm1 + 4341b4: 0f 28 56 e1 movaps -0x1f(%rsi),%xmm2 + 4341b8: 66 0f 3a 0f ca 0f palignr $0xf,%xmm2,%xmm1 + 4341be: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) + 4341c2: 0f 28 5e d1 movaps -0x2f(%rsi),%xmm3 + 4341c6: 66 0f 3a 0f d3 0f palignr $0xf,%xmm3,%xmm2 + 4341cc: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) + 4341d0: 0f 28 66 c1 movaps -0x3f(%rsi),%xmm4 + 4341d4: 66 0f 3a 0f dc 0f palignr $0xf,%xmm4,%xmm3 + 4341da: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) + 4341de: 0f 28 6e b1 movaps -0x4f(%rsi),%xmm5 + 4341e2: 66 0f 3a 0f e5 0f palignr $0xf,%xmm5,%xmm4 + 4341e8: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) + 4341ec: 0f 28 76 a1 movaps -0x5f(%rsi),%xmm6 + 4341f0: 66 0f 3a 0f ee 0f palignr $0xf,%xmm6,%xmm5 + 4341f6: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) + 4341fa: 0f 28 7e 91 movaps -0x6f(%rsi),%xmm7 + 4341fe: 66 0f 3a 0f f7 0f palignr $0xf,%xmm7,%xmm6 + 434204: 0f 29 77 a0 movaps %xmm6,-0x60(%rdi) + 434208: 44 0f 28 46 81 movaps -0x7f(%rsi),%xmm8 + 43420d: 66 41 0f 3a 0f f8 0f palignr $0xf,%xmm8,%xmm7 + 434214: 0f 29 7f 90 movaps %xmm7,-0x70(%rdi) + 434218: 44 0f 28 8e 71 ff ff movaps -0x8f(%rsi),%xmm9 + 43421f: ff + 434220: 66 45 0f 3a 0f c1 0f palignr $0xf,%xmm9,%xmm8 + 434227: 44 0f 29 47 80 movaps %xmm8,-0x80(%rdi) + 43422c: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 434233: 48 8d 7f 80 lea -0x80(%rdi),%rdi + 434237: 48 8d 76 80 lea -0x80(%rsi),%rsi + 43423b: 0f 83 6f ff ff ff jae 4341b0 <__memmove_ssse3_back+0x17f0> + 434241: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 434246: 48 81 c2 80 00 00 00 add $0x80,%rdx + 43424d: 48 29 d7 sub %rdx,%rdi + 434250: 48 29 d6 sub %rdx,%rsi + 434253: 4c 8d 1d 16 f3 06 00 lea 0x6f316(%rip),%r11 # 4a3570 + 43425a: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 43425e: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 434262: ff e2 jmpq *%rdx + 434264: 0f 0b ud2 + 434266: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43426d: 00 00 00 + 434270: f3 0f 6f 0e movdqu (%rsi),%xmm1 + 434274: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 434279: 66 0f 7f 0f movdqa %xmm1,(%rdi) + 43427d: 48 83 ea 10 sub $0x10,%rdx + 434281: 48 83 c6 10 add $0x10,%rsi + 434285: 48 83 c7 10 add $0x10,%rdi + 434289: 48 8b 0d 20 6e 29 00 mov 0x296e20(%rip),%rcx # 6cb0b0 <__x86_shared_cache_size_half> + 434290: 49 89 f1 mov %rsi,%r9 + 434293: 49 29 f9 sub %rdi,%r9 + 434296: 49 39 d1 cmp %rdx,%r9 + 434299: 73 09 jae 4342a4 <__memmove_ssse3_back+0x18e4> + 43429b: 49 39 c9 cmp %rcx,%r9 + 43429e: 0f 86 c1 00 00 00 jbe 434365 <__memmove_ssse3_back+0x19a5> + 4342a4: 48 39 ca cmp %rcx,%rdx + 4342a7: 77 03 ja 4342ac <__memmove_ssse3_back+0x18ec> + 4342a9: 48 89 d1 mov %rdx,%rcx + 4342ac: 48 29 ca sub %rcx,%rdx + 4342af: 48 81 fa 00 10 00 00 cmp $0x1000,%rdx + 4342b6: 0f 86 a6 00 00 00 jbe 434362 <__memmove_ssse3_back+0x19a2> + 4342bc: 49 89 c9 mov %rcx,%r9 + 4342bf: 49 c1 e1 03 shl $0x3,%r9 + 4342c3: 4c 39 ca cmp %r9,%rdx + 4342c6: 76 06 jbe 4342ce <__memmove_ssse3_back+0x190e> + 4342c8: 48 01 ca add %rcx,%rdx + 4342cb: 48 31 c9 xor %rcx,%rcx + 4342ce: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 4342d5: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 4342dc: 0f 18 8e 00 02 00 00 prefetcht0 0x200(%rsi) + 4342e3: 0f 18 8e 00 03 00 00 prefetcht0 0x300(%rsi) + 4342ea: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 4342ee: f3 0f 6f 4e 10 movdqu 0x10(%rsi),%xmm1 + 4342f3: f3 0f 6f 56 20 movdqu 0x20(%rsi),%xmm2 + 4342f8: f3 0f 6f 5e 30 movdqu 0x30(%rsi),%xmm3 + 4342fd: f3 0f 6f 66 40 movdqu 0x40(%rsi),%xmm4 + 434302: f3 0f 6f 6e 50 movdqu 0x50(%rsi),%xmm5 + 434307: f3 0f 6f 76 60 movdqu 0x60(%rsi),%xmm6 + 43430c: f3 0f 6f 7e 70 movdqu 0x70(%rsi),%xmm7 + 434311: 0f ae e8 lfence + 434314: 66 0f e7 07 movntdq %xmm0,(%rdi) + 434318: 66 0f e7 4f 10 movntdq %xmm1,0x10(%rdi) + 43431d: 66 0f e7 57 20 movntdq %xmm2,0x20(%rdi) + 434322: 66 0f e7 5f 30 movntdq %xmm3,0x30(%rdi) + 434327: 66 0f e7 67 40 movntdq %xmm4,0x40(%rdi) + 43432c: 66 0f e7 6f 50 movntdq %xmm5,0x50(%rdi) + 434331: 66 0f e7 77 60 movntdq %xmm6,0x60(%rdi) + 434336: 66 0f e7 7f 70 movntdq %xmm7,0x70(%rdi) + 43433b: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi + 434342: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi + 434349: 73 8a jae 4342d5 <__memmove_ssse3_back+0x1915> + 43434b: 0f ae f8 sfence + 43434e: 48 81 f9 80 00 00 00 cmp $0x80,%rcx + 434355: 0f 82 96 00 00 00 jb 4343f1 <__memmove_ssse3_back+0x1a31> + 43435b: 48 81 c2 80 00 00 00 add $0x80,%rdx + 434362: 48 01 ca add %rcx,%rdx + 434365: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 43436c: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) + 434373: 0f 18 86 80 02 00 00 prefetchnta 0x280(%rsi) + 43437a: 0f 18 87 c0 01 00 00 prefetchnta 0x1c0(%rdi) + 434381: 0f 18 87 80 02 00 00 prefetchnta 0x280(%rdi) + 434388: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 43438f: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 434393: f3 0f 6f 4e 10 movdqu 0x10(%rsi),%xmm1 + 434398: f3 0f 6f 56 20 movdqu 0x20(%rsi),%xmm2 + 43439d: f3 0f 6f 5e 30 movdqu 0x30(%rsi),%xmm3 + 4343a2: f3 0f 6f 66 40 movdqu 0x40(%rsi),%xmm4 + 4343a7: f3 0f 6f 6e 50 movdqu 0x50(%rsi),%xmm5 + 4343ac: f3 0f 6f 76 60 movdqu 0x60(%rsi),%xmm6 + 4343b1: f3 0f 6f 7e 70 movdqu 0x70(%rsi),%xmm7 + 4343b6: 66 0f 7f 07 movdqa %xmm0,(%rdi) + 4343ba: 66 0f 7f 4f 10 movdqa %xmm1,0x10(%rdi) + 4343bf: 66 0f 7f 57 20 movdqa %xmm2,0x20(%rdi) + 4343c4: 66 0f 7f 5f 30 movdqa %xmm3,0x30(%rdi) + 4343c9: 66 0f 7f 67 40 movdqa %xmm4,0x40(%rdi) + 4343ce: 66 0f 7f 6f 50 movdqa %xmm5,0x50(%rdi) + 4343d3: 66 0f 7f 77 60 movdqa %xmm6,0x60(%rdi) + 4343d8: 66 0f 7f 7f 70 movdqa %xmm7,0x70(%rdi) + 4343dd: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi + 4343e4: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi + 4343eb: 0f 83 7b ff ff ff jae 43436c <__memmove_ssse3_back+0x19ac> + 4343f1: 48 81 c2 80 00 00 00 add $0x80,%rdx + 4343f8: 48 01 d6 add %rdx,%rsi + 4343fb: 48 01 d7 add %rdx,%rdi + 4343fe: 4c 8d 1d ab f3 06 00 lea 0x6f3ab(%rip),%r11 # 4a37b0 + 434405: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 434409: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 43440d: ff e2 jmpq *%rdx + 43440f: 0f 0b ud2 + 434411: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 434416: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43441d: 00 00 00 + 434420: 48 01 d6 add %rdx,%rsi + 434423: 48 01 d7 add %rdx,%rdi + 434426: f3 0f 6f 46 f0 movdqu -0x10(%rsi),%xmm0 + 43442b: 4c 8d 47 f0 lea -0x10(%rdi),%r8 + 43442f: 49 89 f9 mov %rdi,%r9 + 434432: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi + 434436: 49 29 f9 sub %rdi,%r9 + 434439: 4c 29 ce sub %r9,%rsi + 43443c: 4c 29 ca sub %r9,%rdx + 43443f: 48 8b 0d 6a 6c 29 00 mov 0x296c6a(%rip),%rcx # 6cb0b0 <__x86_shared_cache_size_half> + 434446: 49 89 f9 mov %rdi,%r9 + 434449: 49 29 f1 sub %rsi,%r9 + 43444c: 49 39 d1 cmp %rdx,%r9 + 43444f: 73 09 jae 43445a <__memmove_ssse3_back+0x1a9a> + 434451: 49 39 c9 cmp %rcx,%r9 + 434454: 0f 86 bf 00 00 00 jbe 434519 <__memmove_ssse3_back+0x1b59> + 43445a: 48 39 ca cmp %rcx,%rdx + 43445d: 77 03 ja 434462 <__memmove_ssse3_back+0x1aa2> + 43445f: 48 89 d1 mov %rdx,%rcx + 434462: 48 29 ca sub %rcx,%rdx + 434465: 48 81 fa 00 10 00 00 cmp $0x1000,%rdx + 43446c: 0f 86 a4 00 00 00 jbe 434516 <__memmove_ssse3_back+0x1b56> + 434472: 49 89 c9 mov %rcx,%r9 + 434475: 49 c1 e1 03 shl $0x3,%r9 + 434479: 4c 39 ca cmp %r9,%rdx + 43447c: 76 06 jbe 434484 <__memmove_ssse3_back+0x1ac4> + 43447e: 48 01 ca add %rcx,%rdx + 434481: 48 31 c9 xor %rcx,%rcx + 434484: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 43448b: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 434492: 0f 18 8e 00 fe ff ff prefetcht0 -0x200(%rsi) + 434499: 0f 18 8e 00 fd ff ff prefetcht0 -0x300(%rsi) + 4344a0: f3 0f 6f 4e f0 movdqu -0x10(%rsi),%xmm1 + 4344a5: f3 0f 6f 56 e0 movdqu -0x20(%rsi),%xmm2 + 4344aa: f3 0f 6f 5e d0 movdqu -0x30(%rsi),%xmm3 + 4344af: f3 0f 6f 66 c0 movdqu -0x40(%rsi),%xmm4 + 4344b4: f3 0f 6f 6e b0 movdqu -0x50(%rsi),%xmm5 + 4344b9: f3 0f 6f 76 a0 movdqu -0x60(%rsi),%xmm6 + 4344be: f3 0f 6f 7e 90 movdqu -0x70(%rsi),%xmm7 + 4344c3: f3 44 0f 6f 46 80 movdqu -0x80(%rsi),%xmm8 + 4344c9: 0f ae e8 lfence + 4344cc: 66 0f e7 4f f0 movntdq %xmm1,-0x10(%rdi) + 4344d1: 66 0f e7 57 e0 movntdq %xmm2,-0x20(%rdi) + 4344d6: 66 0f e7 5f d0 movntdq %xmm3,-0x30(%rdi) + 4344db: 66 0f e7 67 c0 movntdq %xmm4,-0x40(%rdi) + 4344e0: 66 0f e7 6f b0 movntdq %xmm5,-0x50(%rdi) + 4344e5: 66 0f e7 77 a0 movntdq %xmm6,-0x60(%rdi) + 4344ea: 66 0f e7 7f 90 movntdq %xmm7,-0x70(%rdi) + 4344ef: 66 44 0f e7 47 80 movntdq %xmm8,-0x80(%rdi) + 4344f5: 48 8d 76 80 lea -0x80(%rsi),%rsi + 4344f9: 48 8d 7f 80 lea -0x80(%rdi),%rdi + 4344fd: 73 8c jae 43448b <__memmove_ssse3_back+0x1acb> + 4344ff: 0f ae f8 sfence + 434502: 48 81 f9 80 00 00 00 cmp $0x80,%rcx + 434509: 0f 82 90 00 00 00 jb 43459f <__memmove_ssse3_back+0x1bdf> + 43450f: 48 81 c2 80 00 00 00 add $0x80,%rdx + 434516: 48 01 ca add %rcx,%rdx + 434519: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 434520: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) + 434527: 0f 18 86 80 fd ff ff prefetchnta -0x280(%rsi) + 43452e: 0f 18 87 40 fe ff ff prefetchnta -0x1c0(%rdi) + 434535: 0f 18 87 80 fd ff ff prefetchnta -0x280(%rdi) + 43453c: 48 81 ea 80 00 00 00 sub $0x80,%rdx + 434543: f3 0f 6f 4e f0 movdqu -0x10(%rsi),%xmm1 + 434548: f3 0f 6f 56 e0 movdqu -0x20(%rsi),%xmm2 + 43454d: f3 0f 6f 5e d0 movdqu -0x30(%rsi),%xmm3 + 434552: f3 0f 6f 66 c0 movdqu -0x40(%rsi),%xmm4 + 434557: f3 0f 6f 6e b0 movdqu -0x50(%rsi),%xmm5 + 43455c: f3 0f 6f 76 a0 movdqu -0x60(%rsi),%xmm6 + 434561: f3 0f 6f 7e 90 movdqu -0x70(%rsi),%xmm7 + 434566: f3 44 0f 6f 46 80 movdqu -0x80(%rsi),%xmm8 + 43456c: 66 0f 7f 4f f0 movdqa %xmm1,-0x10(%rdi) + 434571: 66 0f 7f 57 e0 movdqa %xmm2,-0x20(%rdi) + 434576: 66 0f 7f 5f d0 movdqa %xmm3,-0x30(%rdi) + 43457b: 66 0f 7f 67 c0 movdqa %xmm4,-0x40(%rdi) + 434580: 66 0f 7f 6f b0 movdqa %xmm5,-0x50(%rdi) + 434585: 66 0f 7f 77 a0 movdqa %xmm6,-0x60(%rdi) + 43458a: 66 0f 7f 7f 90 movdqa %xmm7,-0x70(%rdi) + 43458f: 66 44 0f 7f 47 80 movdqa %xmm8,-0x80(%rdi) + 434595: 48 8d 76 80 lea -0x80(%rsi),%rsi + 434599: 48 8d 7f 80 lea -0x80(%rdi),%rdi + 43459d: 73 81 jae 434520 <__memmove_ssse3_back+0x1b60> + 43459f: f3 41 0f 7f 00 movdqu %xmm0,(%r8) + 4345a4: 48 81 c2 80 00 00 00 add $0x80,%rdx + 4345ab: 48 29 d6 sub %rdx,%rsi + 4345ae: 48 29 d7 sub %rdx,%rdi + 4345b1: 4c 8d 1d b8 ef 06 00 lea 0x6efb8(%rip),%r11 # 4a3570 + 4345b8: 49 63 14 93 movslq (%r11,%rdx,4),%rdx + 4345bc: 49 8d 14 13 lea (%r11,%rdx,1),%rdx + 4345c0: ff e2 jmpq *%rdx + 4345c2: 0f 0b ud2 + 4345c4: 66 90 xchg %ax,%ax + 4345c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4345cd: 00 00 00 + 4345d0: f2 0f f0 46 80 lddqu -0x80(%rsi),%xmm0 + 4345d5: f3 0f 7f 47 80 movdqu %xmm0,-0x80(%rdi) + 4345da: f2 0f f0 46 90 lddqu -0x70(%rsi),%xmm0 + 4345df: f3 0f 7f 47 90 movdqu %xmm0,-0x70(%rdi) + 4345e4: f2 0f f0 46 a0 lddqu -0x60(%rsi),%xmm0 + 4345e9: f3 0f 7f 47 a0 movdqu %xmm0,-0x60(%rdi) + 4345ee: f2 0f f0 46 b0 lddqu -0x50(%rsi),%xmm0 + 4345f3: f3 0f 7f 47 b0 movdqu %xmm0,-0x50(%rdi) + 4345f8: f2 0f f0 46 c0 lddqu -0x40(%rsi),%xmm0 + 4345fd: f3 0f 7f 47 c0 movdqu %xmm0,-0x40(%rdi) + 434602: f2 0f f0 46 d0 lddqu -0x30(%rsi),%xmm0 + 434607: f3 0f 7f 47 d0 movdqu %xmm0,-0x30(%rdi) + 43460c: f2 0f f0 46 e0 lddqu -0x20(%rsi),%xmm0 + 434611: f3 0f 7f 47 e0 movdqu %xmm0,-0x20(%rdi) + 434616: f2 0f f0 46 f0 lddqu -0x10(%rsi),%xmm0 + 43461b: f3 0f 7f 47 f0 movdqu %xmm0,-0x10(%rdi) + 434620: c3 retq + 434621: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 434626: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43462d: 00 00 00 + 434630: f2 0f f0 86 71 ff ff lddqu -0x8f(%rsi),%xmm0 + 434637: ff + 434638: f3 0f 7f 87 71 ff ff movdqu %xmm0,-0x8f(%rdi) + 43463f: ff + 434640: f2 0f f0 46 81 lddqu -0x7f(%rsi),%xmm0 + 434645: f3 0f 7f 47 81 movdqu %xmm0,-0x7f(%rdi) + 43464a: f2 0f f0 46 91 lddqu -0x6f(%rsi),%xmm0 + 43464f: f3 0f 7f 47 91 movdqu %xmm0,-0x6f(%rdi) + 434654: f2 0f f0 46 a1 lddqu -0x5f(%rsi),%xmm0 + 434659: f3 0f 7f 47 a1 movdqu %xmm0,-0x5f(%rdi) + 43465e: f2 0f f0 46 b1 lddqu -0x4f(%rsi),%xmm0 + 434663: f3 0f 7f 47 b1 movdqu %xmm0,-0x4f(%rdi) + 434668: f2 0f f0 46 c1 lddqu -0x3f(%rsi),%xmm0 + 43466d: f3 0f 7f 47 c1 movdqu %xmm0,-0x3f(%rdi) + 434672: f2 0f f0 46 d1 lddqu -0x2f(%rsi),%xmm0 + 434677: f3 0f 7f 47 d1 movdqu %xmm0,-0x2f(%rdi) + 43467c: f2 0f f0 46 e1 lddqu -0x1f(%rsi),%xmm0 + 434681: f2 0f f0 4e f0 lddqu -0x10(%rsi),%xmm1 + 434686: f3 0f 7f 47 e1 movdqu %xmm0,-0x1f(%rdi) + 43468b: f3 0f 7f 4f f0 movdqu %xmm1,-0x10(%rdi) + 434690: c3 retq + 434691: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 434696: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43469d: 00 00 00 + 4346a0: 48 8b 56 f1 mov -0xf(%rsi),%rdx + 4346a4: 48 8b 4e f8 mov -0x8(%rsi),%rcx + 4346a8: 48 89 57 f1 mov %rdx,-0xf(%rdi) + 4346ac: 48 89 4f f8 mov %rcx,-0x8(%rdi) + 4346b0: c3 retq + 4346b1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4346b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4346bd: 00 00 00 + 4346c0: f2 0f f0 86 72 ff ff lddqu -0x8e(%rsi),%xmm0 + 4346c7: ff + 4346c8: f3 0f 7f 87 72 ff ff movdqu %xmm0,-0x8e(%rdi) + 4346cf: ff + 4346d0: f2 0f f0 46 82 lddqu -0x7e(%rsi),%xmm0 + 4346d5: f3 0f 7f 47 82 movdqu %xmm0,-0x7e(%rdi) + 4346da: f2 0f f0 46 92 lddqu -0x6e(%rsi),%xmm0 + 4346df: f3 0f 7f 47 92 movdqu %xmm0,-0x6e(%rdi) + 4346e4: f2 0f f0 46 a2 lddqu -0x5e(%rsi),%xmm0 + 4346e9: f3 0f 7f 47 a2 movdqu %xmm0,-0x5e(%rdi) + 4346ee: f2 0f f0 46 b2 lddqu -0x4e(%rsi),%xmm0 + 4346f3: f3 0f 7f 47 b2 movdqu %xmm0,-0x4e(%rdi) + 4346f8: f2 0f f0 46 c2 lddqu -0x3e(%rsi),%xmm0 + 4346fd: f3 0f 7f 47 c2 movdqu %xmm0,-0x3e(%rdi) + 434702: f2 0f f0 46 d2 lddqu -0x2e(%rsi),%xmm0 + 434707: f3 0f 7f 47 d2 movdqu %xmm0,-0x2e(%rdi) + 43470c: f2 0f f0 46 e2 lddqu -0x1e(%rsi),%xmm0 + 434711: f2 0f f0 4e f0 lddqu -0x10(%rsi),%xmm1 + 434716: f3 0f 7f 47 e2 movdqu %xmm0,-0x1e(%rdi) + 43471b: f3 0f 7f 4f f0 movdqu %xmm1,-0x10(%rdi) + 434720: c3 retq + 434721: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 434726: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43472d: 00 00 00 + 434730: 48 8b 56 f2 mov -0xe(%rsi),%rdx + 434734: 48 8b 4e f8 mov -0x8(%rsi),%rcx + 434738: 48 89 57 f2 mov %rdx,-0xe(%rdi) + 43473c: 48 89 4f f8 mov %rcx,-0x8(%rdi) + 434740: c3 retq + 434741: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 434746: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43474d: 00 00 00 + 434750: f2 0f f0 86 73 ff ff lddqu -0x8d(%rsi),%xmm0 + 434757: ff + 434758: f3 0f 7f 87 73 ff ff movdqu %xmm0,-0x8d(%rdi) + 43475f: ff + 434760: f2 0f f0 46 83 lddqu -0x7d(%rsi),%xmm0 + 434765: f3 0f 7f 47 83 movdqu %xmm0,-0x7d(%rdi) + 43476a: f2 0f f0 46 93 lddqu -0x6d(%rsi),%xmm0 + 43476f: f3 0f 7f 47 93 movdqu %xmm0,-0x6d(%rdi) + 434774: f2 0f f0 46 a3 lddqu -0x5d(%rsi),%xmm0 + 434779: f3 0f 7f 47 a3 movdqu %xmm0,-0x5d(%rdi) + 43477e: f2 0f f0 46 b3 lddqu -0x4d(%rsi),%xmm0 + 434783: f3 0f 7f 47 b3 movdqu %xmm0,-0x4d(%rdi) + 434788: f2 0f f0 46 c3 lddqu -0x3d(%rsi),%xmm0 + 43478d: f3 0f 7f 47 c3 movdqu %xmm0,-0x3d(%rdi) + 434792: f2 0f f0 46 d3 lddqu -0x2d(%rsi),%xmm0 + 434797: f3 0f 7f 47 d3 movdqu %xmm0,-0x2d(%rdi) + 43479c: f2 0f f0 46 e3 lddqu -0x1d(%rsi),%xmm0 + 4347a1: f2 0f f0 4e f0 lddqu -0x10(%rsi),%xmm1 + 4347a6: f3 0f 7f 47 e3 movdqu %xmm0,-0x1d(%rdi) + 4347ab: f3 0f 7f 4f f0 movdqu %xmm1,-0x10(%rdi) + 4347b0: c3 retq + 4347b1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4347b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4347bd: 00 00 00 + 4347c0: 48 8b 56 f3 mov -0xd(%rsi),%rdx + 4347c4: 48 8b 4e f8 mov -0x8(%rsi),%rcx + 4347c8: 48 89 57 f3 mov %rdx,-0xd(%rdi) + 4347cc: 48 89 4f f8 mov %rcx,-0x8(%rdi) + 4347d0: c3 retq + 4347d1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4347d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4347dd: 00 00 00 + 4347e0: f2 0f f0 86 74 ff ff lddqu -0x8c(%rsi),%xmm0 + 4347e7: ff + 4347e8: f3 0f 7f 87 74 ff ff movdqu %xmm0,-0x8c(%rdi) + 4347ef: ff + 4347f0: f2 0f f0 46 84 lddqu -0x7c(%rsi),%xmm0 + 4347f5: f3 0f 7f 47 84 movdqu %xmm0,-0x7c(%rdi) + 4347fa: f2 0f f0 46 94 lddqu -0x6c(%rsi),%xmm0 + 4347ff: f3 0f 7f 47 94 movdqu %xmm0,-0x6c(%rdi) + 434804: f2 0f f0 46 a4 lddqu -0x5c(%rsi),%xmm0 + 434809: f3 0f 7f 47 a4 movdqu %xmm0,-0x5c(%rdi) + 43480e: f2 0f f0 46 b4 lddqu -0x4c(%rsi),%xmm0 + 434813: f3 0f 7f 47 b4 movdqu %xmm0,-0x4c(%rdi) + 434818: f2 0f f0 46 c4 lddqu -0x3c(%rsi),%xmm0 + 43481d: f3 0f 7f 47 c4 movdqu %xmm0,-0x3c(%rdi) + 434822: f2 0f f0 46 d4 lddqu -0x2c(%rsi),%xmm0 + 434827: f3 0f 7f 47 d4 movdqu %xmm0,-0x2c(%rdi) + 43482c: f2 0f f0 46 e4 lddqu -0x1c(%rsi),%xmm0 + 434831: f2 0f f0 4e f0 lddqu -0x10(%rsi),%xmm1 + 434836: f3 0f 7f 47 e4 movdqu %xmm0,-0x1c(%rdi) + 43483b: f3 0f 7f 4f f0 movdqu %xmm1,-0x10(%rdi) + 434840: c3 retq + 434841: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 434846: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43484d: 00 00 00 + 434850: 48 8b 56 f4 mov -0xc(%rsi),%rdx + 434854: 8b 4e fc mov -0x4(%rsi),%ecx + 434857: 48 89 57 f4 mov %rdx,-0xc(%rdi) + 43485b: 89 4f fc mov %ecx,-0x4(%rdi) + 43485e: c3 retq + 43485f: 90 nop + 434860: f2 0f f0 86 75 ff ff lddqu -0x8b(%rsi),%xmm0 + 434867: ff + 434868: f3 0f 7f 87 75 ff ff movdqu %xmm0,-0x8b(%rdi) + 43486f: ff + 434870: f2 0f f0 46 85 lddqu -0x7b(%rsi),%xmm0 + 434875: f3 0f 7f 47 85 movdqu %xmm0,-0x7b(%rdi) + 43487a: f2 0f f0 46 95 lddqu -0x6b(%rsi),%xmm0 + 43487f: f3 0f 7f 47 95 movdqu %xmm0,-0x6b(%rdi) + 434884: f2 0f f0 46 a5 lddqu -0x5b(%rsi),%xmm0 + 434889: f3 0f 7f 47 a5 movdqu %xmm0,-0x5b(%rdi) + 43488e: f2 0f f0 46 b5 lddqu -0x4b(%rsi),%xmm0 + 434893: f3 0f 7f 47 b5 movdqu %xmm0,-0x4b(%rdi) + 434898: f2 0f f0 46 c5 lddqu -0x3b(%rsi),%xmm0 + 43489d: f3 0f 7f 47 c5 movdqu %xmm0,-0x3b(%rdi) + 4348a2: f2 0f f0 46 d5 lddqu -0x2b(%rsi),%xmm0 + 4348a7: f3 0f 7f 47 d5 movdqu %xmm0,-0x2b(%rdi) + 4348ac: f2 0f f0 46 e5 lddqu -0x1b(%rsi),%xmm0 + 4348b1: f2 0f f0 4e f0 lddqu -0x10(%rsi),%xmm1 + 4348b6: f3 0f 7f 47 e5 movdqu %xmm0,-0x1b(%rdi) + 4348bb: f3 0f 7f 4f f0 movdqu %xmm1,-0x10(%rdi) + 4348c0: c3 retq + 4348c1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4348c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4348cd: 00 00 00 + 4348d0: 48 8b 56 f5 mov -0xb(%rsi),%rdx + 4348d4: 8b 4e fc mov -0x4(%rsi),%ecx + 4348d7: 48 89 57 f5 mov %rdx,-0xb(%rdi) + 4348db: 89 4f fc mov %ecx,-0x4(%rdi) + 4348de: c3 retq + 4348df: 90 nop + 4348e0: f2 0f f0 86 76 ff ff lddqu -0x8a(%rsi),%xmm0 + 4348e7: ff + 4348e8: f3 0f 7f 87 76 ff ff movdqu %xmm0,-0x8a(%rdi) + 4348ef: ff + 4348f0: f2 0f f0 46 86 lddqu -0x7a(%rsi),%xmm0 + 4348f5: f3 0f 7f 47 86 movdqu %xmm0,-0x7a(%rdi) + 4348fa: f2 0f f0 46 96 lddqu -0x6a(%rsi),%xmm0 + 4348ff: f3 0f 7f 47 96 movdqu %xmm0,-0x6a(%rdi) + 434904: f2 0f f0 46 a6 lddqu -0x5a(%rsi),%xmm0 + 434909: f3 0f 7f 47 a6 movdqu %xmm0,-0x5a(%rdi) + 43490e: f2 0f f0 46 b6 lddqu -0x4a(%rsi),%xmm0 + 434913: f3 0f 7f 47 b6 movdqu %xmm0,-0x4a(%rdi) + 434918: f2 0f f0 46 c6 lddqu -0x3a(%rsi),%xmm0 + 43491d: f3 0f 7f 47 c6 movdqu %xmm0,-0x3a(%rdi) + 434922: f2 0f f0 46 d6 lddqu -0x2a(%rsi),%xmm0 + 434927: f3 0f 7f 47 d6 movdqu %xmm0,-0x2a(%rdi) + 43492c: f2 0f f0 46 e6 lddqu -0x1a(%rsi),%xmm0 + 434931: f2 0f f0 4e f0 lddqu -0x10(%rsi),%xmm1 + 434936: f3 0f 7f 47 e6 movdqu %xmm0,-0x1a(%rdi) + 43493b: f3 0f 7f 4f f0 movdqu %xmm1,-0x10(%rdi) + 434940: c3 retq + 434941: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 434946: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43494d: 00 00 00 + 434950: 48 8b 56 f6 mov -0xa(%rsi),%rdx + 434954: 8b 4e fc mov -0x4(%rsi),%ecx + 434957: 48 89 57 f6 mov %rdx,-0xa(%rdi) + 43495b: 89 4f fc mov %ecx,-0x4(%rdi) + 43495e: c3 retq + 43495f: 90 nop + 434960: f2 0f f0 86 77 ff ff lddqu -0x89(%rsi),%xmm0 + 434967: ff + 434968: f3 0f 7f 87 77 ff ff movdqu %xmm0,-0x89(%rdi) + 43496f: ff + 434970: f2 0f f0 46 87 lddqu -0x79(%rsi),%xmm0 + 434975: f3 0f 7f 47 87 movdqu %xmm0,-0x79(%rdi) + 43497a: f2 0f f0 46 97 lddqu -0x69(%rsi),%xmm0 + 43497f: f3 0f 7f 47 97 movdqu %xmm0,-0x69(%rdi) + 434984: f2 0f f0 46 a7 lddqu -0x59(%rsi),%xmm0 + 434989: f3 0f 7f 47 a7 movdqu %xmm0,-0x59(%rdi) + 43498e: f2 0f f0 46 b7 lddqu -0x49(%rsi),%xmm0 + 434993: f3 0f 7f 47 b7 movdqu %xmm0,-0x49(%rdi) + 434998: f2 0f f0 46 c7 lddqu -0x39(%rsi),%xmm0 + 43499d: f3 0f 7f 47 c7 movdqu %xmm0,-0x39(%rdi) + 4349a2: f2 0f f0 46 d7 lddqu -0x29(%rsi),%xmm0 + 4349a7: f3 0f 7f 47 d7 movdqu %xmm0,-0x29(%rdi) + 4349ac: f2 0f f0 46 e7 lddqu -0x19(%rsi),%xmm0 + 4349b1: f2 0f f0 4e f0 lddqu -0x10(%rsi),%xmm1 + 4349b6: f3 0f 7f 47 e7 movdqu %xmm0,-0x19(%rdi) + 4349bb: f3 0f 7f 4f f0 movdqu %xmm1,-0x10(%rdi) + 4349c0: c3 retq + 4349c1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4349c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4349cd: 00 00 00 + 4349d0: 48 8b 56 f7 mov -0x9(%rsi),%rdx + 4349d4: 8b 4e fc mov -0x4(%rsi),%ecx + 4349d7: 48 89 57 f7 mov %rdx,-0x9(%rdi) + 4349db: 89 4f fc mov %ecx,-0x4(%rdi) + 4349de: c3 retq + 4349df: 90 nop + 4349e0: f2 0f f0 86 78 ff ff lddqu -0x88(%rsi),%xmm0 + 4349e7: ff + 4349e8: f3 0f 7f 87 78 ff ff movdqu %xmm0,-0x88(%rdi) + 4349ef: ff + 4349f0: f2 0f f0 46 88 lddqu -0x78(%rsi),%xmm0 + 4349f5: f3 0f 7f 47 88 movdqu %xmm0,-0x78(%rdi) + 4349fa: f2 0f f0 46 98 lddqu -0x68(%rsi),%xmm0 + 4349ff: f3 0f 7f 47 98 movdqu %xmm0,-0x68(%rdi) + 434a04: f2 0f f0 46 a8 lddqu -0x58(%rsi),%xmm0 + 434a09: f3 0f 7f 47 a8 movdqu %xmm0,-0x58(%rdi) + 434a0e: f2 0f f0 46 b8 lddqu -0x48(%rsi),%xmm0 + 434a13: f3 0f 7f 47 b8 movdqu %xmm0,-0x48(%rdi) + 434a18: f2 0f f0 46 c8 lddqu -0x38(%rsi),%xmm0 + 434a1d: f3 0f 7f 47 c8 movdqu %xmm0,-0x38(%rdi) + 434a22: f2 0f f0 46 d8 lddqu -0x28(%rsi),%xmm0 + 434a27: f3 0f 7f 47 d8 movdqu %xmm0,-0x28(%rdi) + 434a2c: f2 0f f0 46 e8 lddqu -0x18(%rsi),%xmm0 + 434a31: f2 0f f0 4e f0 lddqu -0x10(%rsi),%xmm1 + 434a36: f3 0f 7f 47 e8 movdqu %xmm0,-0x18(%rdi) + 434a3b: f3 0f 7f 4f f0 movdqu %xmm1,-0x10(%rdi) + 434a40: c3 retq + 434a41: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 434a46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 434a4d: 00 00 00 + 434a50: 48 8b 56 f8 mov -0x8(%rsi),%rdx + 434a54: 48 89 57 f8 mov %rdx,-0x8(%rdi) + 434a58: c3 retq + 434a59: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 434a60: f2 0f f0 86 79 ff ff lddqu -0x87(%rsi),%xmm0 + 434a67: ff + 434a68: f3 0f 7f 87 79 ff ff movdqu %xmm0,-0x87(%rdi) + 434a6f: ff + 434a70: f2 0f f0 46 89 lddqu -0x77(%rsi),%xmm0 + 434a75: f3 0f 7f 47 89 movdqu %xmm0,-0x77(%rdi) + 434a7a: f2 0f f0 46 99 lddqu -0x67(%rsi),%xmm0 + 434a7f: f3 0f 7f 47 99 movdqu %xmm0,-0x67(%rdi) + 434a84: f2 0f f0 46 a9 lddqu -0x57(%rsi),%xmm0 + 434a89: f3 0f 7f 47 a9 movdqu %xmm0,-0x57(%rdi) + 434a8e: f2 0f f0 46 b9 lddqu -0x47(%rsi),%xmm0 + 434a93: f3 0f 7f 47 b9 movdqu %xmm0,-0x47(%rdi) + 434a98: f2 0f f0 46 c9 lddqu -0x37(%rsi),%xmm0 + 434a9d: f3 0f 7f 47 c9 movdqu %xmm0,-0x37(%rdi) + 434aa2: f2 0f f0 46 d9 lddqu -0x27(%rsi),%xmm0 + 434aa7: f3 0f 7f 47 d9 movdqu %xmm0,-0x27(%rdi) + 434aac: f2 0f f0 46 e9 lddqu -0x17(%rsi),%xmm0 + 434ab1: f2 0f f0 4e f0 lddqu -0x10(%rsi),%xmm1 + 434ab6: f3 0f 7f 47 e9 movdqu %xmm0,-0x17(%rdi) + 434abb: f3 0f 7f 4f f0 movdqu %xmm1,-0x10(%rdi) + 434ac0: c3 retq + 434ac1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 434ac6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 434acd: 00 00 00 + 434ad0: 8b 56 f9 mov -0x7(%rsi),%edx + 434ad3: 8b 4e fc mov -0x4(%rsi),%ecx + 434ad6: 89 57 f9 mov %edx,-0x7(%rdi) + 434ad9: 89 4f fc mov %ecx,-0x4(%rdi) + 434adc: c3 retq + 434add: 0f 1f 00 nopl (%rax) + 434ae0: f2 0f f0 86 7a ff ff lddqu -0x86(%rsi),%xmm0 + 434ae7: ff + 434ae8: f3 0f 7f 87 7a ff ff movdqu %xmm0,-0x86(%rdi) + 434aef: ff + 434af0: f2 0f f0 46 8a lddqu -0x76(%rsi),%xmm0 + 434af5: f3 0f 7f 47 8a movdqu %xmm0,-0x76(%rdi) + 434afa: f2 0f f0 46 9a lddqu -0x66(%rsi),%xmm0 + 434aff: f3 0f 7f 47 9a movdqu %xmm0,-0x66(%rdi) + 434b04: f2 0f f0 46 aa lddqu -0x56(%rsi),%xmm0 + 434b09: f3 0f 7f 47 aa movdqu %xmm0,-0x56(%rdi) + 434b0e: f2 0f f0 46 ba lddqu -0x46(%rsi),%xmm0 + 434b13: f3 0f 7f 47 ba movdqu %xmm0,-0x46(%rdi) + 434b18: f2 0f f0 46 ca lddqu -0x36(%rsi),%xmm0 + 434b1d: f3 0f 7f 47 ca movdqu %xmm0,-0x36(%rdi) + 434b22: f2 0f f0 46 da lddqu -0x26(%rsi),%xmm0 + 434b27: f3 0f 7f 47 da movdqu %xmm0,-0x26(%rdi) + 434b2c: f2 0f f0 46 ea lddqu -0x16(%rsi),%xmm0 + 434b31: f2 0f f0 4e f0 lddqu -0x10(%rsi),%xmm1 + 434b36: f3 0f 7f 47 ea movdqu %xmm0,-0x16(%rdi) + 434b3b: f3 0f 7f 4f f0 movdqu %xmm1,-0x10(%rdi) + 434b40: c3 retq + 434b41: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 434b46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 434b4d: 00 00 00 + 434b50: 8b 56 fa mov -0x6(%rsi),%edx + 434b53: 8b 4e fc mov -0x4(%rsi),%ecx + 434b56: 89 57 fa mov %edx,-0x6(%rdi) + 434b59: 89 4f fc mov %ecx,-0x4(%rdi) + 434b5c: c3 retq + 434b5d: 0f 1f 00 nopl (%rax) + 434b60: f2 0f f0 86 7b ff ff lddqu -0x85(%rsi),%xmm0 + 434b67: ff + 434b68: f3 0f 7f 87 7b ff ff movdqu %xmm0,-0x85(%rdi) + 434b6f: ff + 434b70: f2 0f f0 46 8b lddqu -0x75(%rsi),%xmm0 + 434b75: f3 0f 7f 47 8b movdqu %xmm0,-0x75(%rdi) + 434b7a: f2 0f f0 46 9b lddqu -0x65(%rsi),%xmm0 + 434b7f: f3 0f 7f 47 9b movdqu %xmm0,-0x65(%rdi) + 434b84: f2 0f f0 46 ab lddqu -0x55(%rsi),%xmm0 + 434b89: f3 0f 7f 47 ab movdqu %xmm0,-0x55(%rdi) + 434b8e: f2 0f f0 46 bb lddqu -0x45(%rsi),%xmm0 + 434b93: f3 0f 7f 47 bb movdqu %xmm0,-0x45(%rdi) + 434b98: f2 0f f0 46 cb lddqu -0x35(%rsi),%xmm0 + 434b9d: f3 0f 7f 47 cb movdqu %xmm0,-0x35(%rdi) + 434ba2: f2 0f f0 46 db lddqu -0x25(%rsi),%xmm0 + 434ba7: f3 0f 7f 47 db movdqu %xmm0,-0x25(%rdi) + 434bac: f2 0f f0 46 eb lddqu -0x15(%rsi),%xmm0 + 434bb1: f2 0f f0 4e f0 lddqu -0x10(%rsi),%xmm1 + 434bb6: f3 0f 7f 47 eb movdqu %xmm0,-0x15(%rdi) + 434bbb: f3 0f 7f 4f f0 movdqu %xmm1,-0x10(%rdi) + 434bc0: c3 retq + 434bc1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 434bc6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 434bcd: 00 00 00 + 434bd0: 8b 56 fb mov -0x5(%rsi),%edx + 434bd3: 8b 4e fc mov -0x4(%rsi),%ecx + 434bd6: 89 57 fb mov %edx,-0x5(%rdi) + 434bd9: 89 4f fc mov %ecx,-0x4(%rdi) + 434bdc: c3 retq + 434bdd: 0f 1f 00 nopl (%rax) + 434be0: f2 0f f0 86 7c ff ff lddqu -0x84(%rsi),%xmm0 + 434be7: ff + 434be8: f3 0f 7f 87 7c ff ff movdqu %xmm0,-0x84(%rdi) + 434bef: ff + 434bf0: f2 0f f0 46 8c lddqu -0x74(%rsi),%xmm0 + 434bf5: f3 0f 7f 47 8c movdqu %xmm0,-0x74(%rdi) + 434bfa: f2 0f f0 46 9c lddqu -0x64(%rsi),%xmm0 + 434bff: f3 0f 7f 47 9c movdqu %xmm0,-0x64(%rdi) + 434c04: f2 0f f0 46 ac lddqu -0x54(%rsi),%xmm0 + 434c09: f3 0f 7f 47 ac movdqu %xmm0,-0x54(%rdi) + 434c0e: f2 0f f0 46 bc lddqu -0x44(%rsi),%xmm0 + 434c13: f3 0f 7f 47 bc movdqu %xmm0,-0x44(%rdi) + 434c18: f2 0f f0 46 cc lddqu -0x34(%rsi),%xmm0 + 434c1d: f3 0f 7f 47 cc movdqu %xmm0,-0x34(%rdi) + 434c22: f2 0f f0 46 dc lddqu -0x24(%rsi),%xmm0 + 434c27: f3 0f 7f 47 dc movdqu %xmm0,-0x24(%rdi) + 434c2c: f2 0f f0 46 ec lddqu -0x14(%rsi),%xmm0 + 434c31: f2 0f f0 4e f0 lddqu -0x10(%rsi),%xmm1 + 434c36: f3 0f 7f 47 ec movdqu %xmm0,-0x14(%rdi) + 434c3b: f3 0f 7f 4f f0 movdqu %xmm1,-0x10(%rdi) + 434c40: c3 retq + 434c41: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 434c46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 434c4d: 00 00 00 + 434c50: 8b 56 fc mov -0x4(%rsi),%edx + 434c53: 89 57 fc mov %edx,-0x4(%rdi) + 434c56: c3 retq + 434c57: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 434c5e: 00 00 + 434c60: f2 0f f0 86 7d ff ff lddqu -0x83(%rsi),%xmm0 + 434c67: ff + 434c68: f3 0f 7f 87 7d ff ff movdqu %xmm0,-0x83(%rdi) + 434c6f: ff + 434c70: f2 0f f0 46 8d lddqu -0x73(%rsi),%xmm0 + 434c75: f3 0f 7f 47 8d movdqu %xmm0,-0x73(%rdi) + 434c7a: f2 0f f0 46 9d lddqu -0x63(%rsi),%xmm0 + 434c7f: f3 0f 7f 47 9d movdqu %xmm0,-0x63(%rdi) + 434c84: f2 0f f0 46 ad lddqu -0x53(%rsi),%xmm0 + 434c89: f3 0f 7f 47 ad movdqu %xmm0,-0x53(%rdi) + 434c8e: f2 0f f0 46 bd lddqu -0x43(%rsi),%xmm0 + 434c93: f3 0f 7f 47 bd movdqu %xmm0,-0x43(%rdi) + 434c98: f2 0f f0 46 cd lddqu -0x33(%rsi),%xmm0 + 434c9d: f3 0f 7f 47 cd movdqu %xmm0,-0x33(%rdi) + 434ca2: f2 0f f0 46 dd lddqu -0x23(%rsi),%xmm0 + 434ca7: f3 0f 7f 47 dd movdqu %xmm0,-0x23(%rdi) + 434cac: f2 0f f0 46 ed lddqu -0x13(%rsi),%xmm0 + 434cb1: f2 0f f0 4e f0 lddqu -0x10(%rsi),%xmm1 + 434cb6: f3 0f 7f 47 ed movdqu %xmm0,-0x13(%rdi) + 434cbb: f3 0f 7f 4f f0 movdqu %xmm1,-0x10(%rdi) + 434cc0: c3 retq + 434cc1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 434cc6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 434ccd: 00 00 00 + 434cd0: 66 8b 56 fd mov -0x3(%rsi),%dx + 434cd4: 66 8b 4e fe mov -0x2(%rsi),%cx + 434cd8: 66 89 57 fd mov %dx,-0x3(%rdi) + 434cdc: 66 89 4f fe mov %cx,-0x2(%rdi) + 434ce0: c3 retq + 434ce1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 434ce6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 434ced: 00 00 00 + 434cf0: f2 0f f0 86 7e ff ff lddqu -0x82(%rsi),%xmm0 + 434cf7: ff + 434cf8: f3 0f 7f 87 7e ff ff movdqu %xmm0,-0x82(%rdi) + 434cff: ff + 434d00: f2 0f f0 46 8e lddqu -0x72(%rsi),%xmm0 + 434d05: f3 0f 7f 47 8e movdqu %xmm0,-0x72(%rdi) + 434d0a: f2 0f f0 46 9e lddqu -0x62(%rsi),%xmm0 + 434d0f: f3 0f 7f 47 9e movdqu %xmm0,-0x62(%rdi) + 434d14: f2 0f f0 46 ae lddqu -0x52(%rsi),%xmm0 + 434d19: f3 0f 7f 47 ae movdqu %xmm0,-0x52(%rdi) + 434d1e: f2 0f f0 46 be lddqu -0x42(%rsi),%xmm0 + 434d23: f3 0f 7f 47 be movdqu %xmm0,-0x42(%rdi) + 434d28: f2 0f f0 46 ce lddqu -0x32(%rsi),%xmm0 + 434d2d: f3 0f 7f 47 ce movdqu %xmm0,-0x32(%rdi) + 434d32: f2 0f f0 46 de lddqu -0x22(%rsi),%xmm0 + 434d37: f3 0f 7f 47 de movdqu %xmm0,-0x22(%rdi) + 434d3c: f2 0f f0 46 ee lddqu -0x12(%rsi),%xmm0 + 434d41: f2 0f f0 4e f0 lddqu -0x10(%rsi),%xmm1 + 434d46: f3 0f 7f 47 ee movdqu %xmm0,-0x12(%rdi) + 434d4b: f3 0f 7f 4f f0 movdqu %xmm1,-0x10(%rdi) + 434d50: c3 retq + 434d51: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 434d56: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 434d5d: 00 00 00 + 434d60: 0f b7 56 fe movzwl -0x2(%rsi),%edx + 434d64: 66 89 57 fe mov %dx,-0x2(%rdi) + 434d68: c3 retq + 434d69: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 434d70: f2 0f f0 86 7f ff ff lddqu -0x81(%rsi),%xmm0 + 434d77: ff + 434d78: f3 0f 7f 87 7f ff ff movdqu %xmm0,-0x81(%rdi) + 434d7f: ff + 434d80: f2 0f f0 46 8f lddqu -0x71(%rsi),%xmm0 + 434d85: f3 0f 7f 47 8f movdqu %xmm0,-0x71(%rdi) + 434d8a: f2 0f f0 46 9f lddqu -0x61(%rsi),%xmm0 + 434d8f: f3 0f 7f 47 9f movdqu %xmm0,-0x61(%rdi) + 434d94: f2 0f f0 46 af lddqu -0x51(%rsi),%xmm0 + 434d99: f3 0f 7f 47 af movdqu %xmm0,-0x51(%rdi) + 434d9e: f2 0f f0 46 bf lddqu -0x41(%rsi),%xmm0 + 434da3: f3 0f 7f 47 bf movdqu %xmm0,-0x41(%rdi) + 434da8: f2 0f f0 46 cf lddqu -0x31(%rsi),%xmm0 + 434dad: f3 0f 7f 47 cf movdqu %xmm0,-0x31(%rdi) + 434db2: f2 0f f0 46 df lddqu -0x21(%rsi),%xmm0 + 434db7: f3 0f 7f 47 df movdqu %xmm0,-0x21(%rdi) + 434dbc: f2 0f f0 46 ef lddqu -0x11(%rsi),%xmm0 + 434dc1: f2 0f f0 4e f0 lddqu -0x10(%rsi),%xmm1 + 434dc6: f3 0f 7f 47 ef movdqu %xmm0,-0x11(%rdi) + 434dcb: f3 0f 7f 4f f0 movdqu %xmm1,-0x10(%rdi) + 434dd0: c3 retq + 434dd1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 434dd6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 434ddd: 00 00 00 + 434de0: 0f b6 56 ff movzbl -0x1(%rsi),%edx + 434de4: 88 57 ff mov %dl,-0x1(%rdi) + 434de7: c3 retq + 434de8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 434def: 00 + 434df0: f2 0f f0 46 70 lddqu 0x70(%rsi),%xmm0 + 434df5: f3 0f 7f 47 70 movdqu %xmm0,0x70(%rdi) + 434dfa: f2 0f f0 46 60 lddqu 0x60(%rsi),%xmm0 + 434dff: f3 0f 7f 47 60 movdqu %xmm0,0x60(%rdi) + 434e04: f2 0f f0 46 50 lddqu 0x50(%rsi),%xmm0 + 434e09: f3 0f 7f 47 50 movdqu %xmm0,0x50(%rdi) + 434e0e: f2 0f f0 46 40 lddqu 0x40(%rsi),%xmm0 + 434e13: f3 0f 7f 47 40 movdqu %xmm0,0x40(%rdi) + 434e18: f2 0f f0 46 30 lddqu 0x30(%rsi),%xmm0 + 434e1d: f3 0f 7f 47 30 movdqu %xmm0,0x30(%rdi) + 434e22: f2 0f f0 46 20 lddqu 0x20(%rsi),%xmm0 + 434e27: f3 0f 7f 47 20 movdqu %xmm0,0x20(%rdi) + 434e2c: f2 0f f0 46 10 lddqu 0x10(%rsi),%xmm0 + 434e31: f3 0f 7f 47 10 movdqu %xmm0,0x10(%rdi) + 434e36: f2 0f f0 06 lddqu (%rsi),%xmm0 + 434e3a: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 434e3e: c3 retq + 434e3f: 90 nop + 434e40: f2 0f f0 46 7f lddqu 0x7f(%rsi),%xmm0 + 434e45: f3 0f 7f 47 7f movdqu %xmm0,0x7f(%rdi) + 434e4a: f2 0f f0 46 6f lddqu 0x6f(%rsi),%xmm0 + 434e4f: f3 0f 7f 47 6f movdqu %xmm0,0x6f(%rdi) + 434e54: f2 0f f0 46 5f lddqu 0x5f(%rsi),%xmm0 + 434e59: f3 0f 7f 47 5f movdqu %xmm0,0x5f(%rdi) + 434e5e: f2 0f f0 46 4f lddqu 0x4f(%rsi),%xmm0 + 434e63: f3 0f 7f 47 4f movdqu %xmm0,0x4f(%rdi) + 434e68: f2 0f f0 46 3f lddqu 0x3f(%rsi),%xmm0 + 434e6d: f3 0f 7f 47 3f movdqu %xmm0,0x3f(%rdi) + 434e72: f2 0f f0 46 2f lddqu 0x2f(%rsi),%xmm0 + 434e77: f3 0f 7f 47 2f movdqu %xmm0,0x2f(%rdi) + 434e7c: f2 0f f0 46 1f lddqu 0x1f(%rsi),%xmm0 + 434e81: f3 0f 7f 47 1f movdqu %xmm0,0x1f(%rdi) + 434e86: f2 0f f0 46 0f lddqu 0xf(%rsi),%xmm0 + 434e8b: f2 0f f0 0e lddqu (%rsi),%xmm1 + 434e8f: f3 0f 7f 47 0f movdqu %xmm0,0xf(%rdi) + 434e94: f3 0f 7f 0f movdqu %xmm1,(%rdi) + 434e98: c3 retq + 434e99: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 434ea0: 48 8b 56 07 mov 0x7(%rsi),%rdx + 434ea4: 48 8b 0e mov (%rsi),%rcx + 434ea7: 48 89 57 07 mov %rdx,0x7(%rdi) + 434eab: 48 89 0f mov %rcx,(%rdi) + 434eae: c3 retq + 434eaf: 90 nop + 434eb0: f2 0f f0 46 7e lddqu 0x7e(%rsi),%xmm0 + 434eb5: f3 0f 7f 47 7e movdqu %xmm0,0x7e(%rdi) + 434eba: f2 0f f0 46 6e lddqu 0x6e(%rsi),%xmm0 + 434ebf: f3 0f 7f 47 6e movdqu %xmm0,0x6e(%rdi) + 434ec4: f2 0f f0 46 5e lddqu 0x5e(%rsi),%xmm0 + 434ec9: f3 0f 7f 47 5e movdqu %xmm0,0x5e(%rdi) + 434ece: f2 0f f0 46 4e lddqu 0x4e(%rsi),%xmm0 + 434ed3: f3 0f 7f 47 4e movdqu %xmm0,0x4e(%rdi) + 434ed8: f2 0f f0 46 3e lddqu 0x3e(%rsi),%xmm0 + 434edd: f3 0f 7f 47 3e movdqu %xmm0,0x3e(%rdi) + 434ee2: f2 0f f0 46 2e lddqu 0x2e(%rsi),%xmm0 + 434ee7: f3 0f 7f 47 2e movdqu %xmm0,0x2e(%rdi) + 434eec: f2 0f f0 46 1e lddqu 0x1e(%rsi),%xmm0 + 434ef1: f3 0f 7f 47 1e movdqu %xmm0,0x1e(%rdi) + 434ef6: f2 0f f0 46 0e lddqu 0xe(%rsi),%xmm0 + 434efb: f2 0f f0 0e lddqu (%rsi),%xmm1 + 434eff: f3 0f 7f 47 0e movdqu %xmm0,0xe(%rdi) + 434f04: f3 0f 7f 0f movdqu %xmm1,(%rdi) + 434f08: c3 retq + 434f09: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 434f10: 48 8b 56 06 mov 0x6(%rsi),%rdx + 434f14: 48 8b 0e mov (%rsi),%rcx + 434f17: 48 89 57 06 mov %rdx,0x6(%rdi) + 434f1b: 48 89 0f mov %rcx,(%rdi) + 434f1e: c3 retq + 434f1f: 90 nop + 434f20: f2 0f f0 46 7d lddqu 0x7d(%rsi),%xmm0 + 434f25: f3 0f 7f 47 7d movdqu %xmm0,0x7d(%rdi) + 434f2a: f2 0f f0 46 6d lddqu 0x6d(%rsi),%xmm0 + 434f2f: f3 0f 7f 47 6d movdqu %xmm0,0x6d(%rdi) + 434f34: f2 0f f0 46 5d lddqu 0x5d(%rsi),%xmm0 + 434f39: f3 0f 7f 47 5d movdqu %xmm0,0x5d(%rdi) + 434f3e: f2 0f f0 46 4d lddqu 0x4d(%rsi),%xmm0 + 434f43: f3 0f 7f 47 4d movdqu %xmm0,0x4d(%rdi) + 434f48: f2 0f f0 46 3d lddqu 0x3d(%rsi),%xmm0 + 434f4d: f3 0f 7f 47 3d movdqu %xmm0,0x3d(%rdi) + 434f52: f2 0f f0 46 2d lddqu 0x2d(%rsi),%xmm0 + 434f57: f3 0f 7f 47 2d movdqu %xmm0,0x2d(%rdi) + 434f5c: f2 0f f0 46 1d lddqu 0x1d(%rsi),%xmm0 + 434f61: f3 0f 7f 47 1d movdqu %xmm0,0x1d(%rdi) + 434f66: f2 0f f0 46 0d lddqu 0xd(%rsi),%xmm0 + 434f6b: f2 0f f0 0e lddqu (%rsi),%xmm1 + 434f6f: f3 0f 7f 47 0d movdqu %xmm0,0xd(%rdi) + 434f74: f3 0f 7f 0f movdqu %xmm1,(%rdi) + 434f78: c3 retq + 434f79: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 434f80: 48 8b 56 05 mov 0x5(%rsi),%rdx + 434f84: 48 8b 0e mov (%rsi),%rcx + 434f87: 48 89 57 05 mov %rdx,0x5(%rdi) + 434f8b: 48 89 0f mov %rcx,(%rdi) + 434f8e: c3 retq + 434f8f: 90 nop + 434f90: f2 0f f0 46 7c lddqu 0x7c(%rsi),%xmm0 + 434f95: f3 0f 7f 47 7c movdqu %xmm0,0x7c(%rdi) + 434f9a: f2 0f f0 46 6c lddqu 0x6c(%rsi),%xmm0 + 434f9f: f3 0f 7f 47 6c movdqu %xmm0,0x6c(%rdi) + 434fa4: f2 0f f0 46 5c lddqu 0x5c(%rsi),%xmm0 + 434fa9: f3 0f 7f 47 5c movdqu %xmm0,0x5c(%rdi) + 434fae: f2 0f f0 46 4c lddqu 0x4c(%rsi),%xmm0 + 434fb3: f3 0f 7f 47 4c movdqu %xmm0,0x4c(%rdi) + 434fb8: f2 0f f0 46 3c lddqu 0x3c(%rsi),%xmm0 + 434fbd: f3 0f 7f 47 3c movdqu %xmm0,0x3c(%rdi) + 434fc2: f2 0f f0 46 2c lddqu 0x2c(%rsi),%xmm0 + 434fc7: f3 0f 7f 47 2c movdqu %xmm0,0x2c(%rdi) + 434fcc: f2 0f f0 46 1c lddqu 0x1c(%rsi),%xmm0 + 434fd1: f3 0f 7f 47 1c movdqu %xmm0,0x1c(%rdi) + 434fd6: f2 0f f0 46 0c lddqu 0xc(%rsi),%xmm0 + 434fdb: f2 0f f0 0e lddqu (%rsi),%xmm1 + 434fdf: f3 0f 7f 47 0c movdqu %xmm0,0xc(%rdi) + 434fe4: f3 0f 7f 0f movdqu %xmm1,(%rdi) + 434fe8: c3 retq + 434fe9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 434ff0: 48 8b 56 04 mov 0x4(%rsi),%rdx + 434ff4: 48 8b 0e mov (%rsi),%rcx + 434ff7: 48 89 57 04 mov %rdx,0x4(%rdi) + 434ffb: 48 89 0f mov %rcx,(%rdi) + 434ffe: c3 retq + 434fff: 90 nop + 435000: f2 0f f0 46 7b lddqu 0x7b(%rsi),%xmm0 + 435005: f3 0f 7f 47 7b movdqu %xmm0,0x7b(%rdi) + 43500a: f2 0f f0 46 6b lddqu 0x6b(%rsi),%xmm0 + 43500f: f3 0f 7f 47 6b movdqu %xmm0,0x6b(%rdi) + 435014: f2 0f f0 46 5b lddqu 0x5b(%rsi),%xmm0 + 435019: f3 0f 7f 47 5b movdqu %xmm0,0x5b(%rdi) + 43501e: f2 0f f0 46 4b lddqu 0x4b(%rsi),%xmm0 + 435023: f3 0f 7f 47 4b movdqu %xmm0,0x4b(%rdi) + 435028: f2 0f f0 46 3b lddqu 0x3b(%rsi),%xmm0 + 43502d: f3 0f 7f 47 3b movdqu %xmm0,0x3b(%rdi) + 435032: f2 0f f0 46 2b lddqu 0x2b(%rsi),%xmm0 + 435037: f3 0f 7f 47 2b movdqu %xmm0,0x2b(%rdi) + 43503c: f2 0f f0 46 1b lddqu 0x1b(%rsi),%xmm0 + 435041: f3 0f 7f 47 1b movdqu %xmm0,0x1b(%rdi) + 435046: f2 0f f0 46 0b lddqu 0xb(%rsi),%xmm0 + 43504b: f2 0f f0 0e lddqu (%rsi),%xmm1 + 43504f: f3 0f 7f 47 0b movdqu %xmm0,0xb(%rdi) + 435054: f3 0f 7f 0f movdqu %xmm1,(%rdi) + 435058: c3 retq + 435059: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 435060: 48 8b 56 03 mov 0x3(%rsi),%rdx + 435064: 48 8b 0e mov (%rsi),%rcx + 435067: 48 89 57 03 mov %rdx,0x3(%rdi) + 43506b: 48 89 0f mov %rcx,(%rdi) + 43506e: c3 retq + 43506f: 90 nop + 435070: f2 0f f0 46 7a lddqu 0x7a(%rsi),%xmm0 + 435075: f3 0f 7f 47 7a movdqu %xmm0,0x7a(%rdi) + 43507a: f2 0f f0 46 6a lddqu 0x6a(%rsi),%xmm0 + 43507f: f3 0f 7f 47 6a movdqu %xmm0,0x6a(%rdi) + 435084: f2 0f f0 46 5a lddqu 0x5a(%rsi),%xmm0 + 435089: f3 0f 7f 47 5a movdqu %xmm0,0x5a(%rdi) + 43508e: f2 0f f0 46 4a lddqu 0x4a(%rsi),%xmm0 + 435093: f3 0f 7f 47 4a movdqu %xmm0,0x4a(%rdi) + 435098: f2 0f f0 46 3a lddqu 0x3a(%rsi),%xmm0 + 43509d: f3 0f 7f 47 3a movdqu %xmm0,0x3a(%rdi) + 4350a2: f2 0f f0 46 2a lddqu 0x2a(%rsi),%xmm0 + 4350a7: f3 0f 7f 47 2a movdqu %xmm0,0x2a(%rdi) + 4350ac: f2 0f f0 46 1a lddqu 0x1a(%rsi),%xmm0 + 4350b1: f3 0f 7f 47 1a movdqu %xmm0,0x1a(%rdi) + 4350b6: f2 0f f0 46 0a lddqu 0xa(%rsi),%xmm0 + 4350bb: f2 0f f0 0e lddqu (%rsi),%xmm1 + 4350bf: f3 0f 7f 47 0a movdqu %xmm0,0xa(%rdi) + 4350c4: f3 0f 7f 0f movdqu %xmm1,(%rdi) + 4350c8: c3 retq + 4350c9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4350d0: 48 8b 56 02 mov 0x2(%rsi),%rdx + 4350d4: 48 8b 0e mov (%rsi),%rcx + 4350d7: 48 89 57 02 mov %rdx,0x2(%rdi) + 4350db: 48 89 0f mov %rcx,(%rdi) + 4350de: c3 retq + 4350df: 90 nop + 4350e0: f2 0f f0 46 79 lddqu 0x79(%rsi),%xmm0 + 4350e5: f3 0f 7f 47 79 movdqu %xmm0,0x79(%rdi) + 4350ea: f2 0f f0 46 69 lddqu 0x69(%rsi),%xmm0 + 4350ef: f3 0f 7f 47 69 movdqu %xmm0,0x69(%rdi) + 4350f4: f2 0f f0 46 59 lddqu 0x59(%rsi),%xmm0 + 4350f9: f3 0f 7f 47 59 movdqu %xmm0,0x59(%rdi) + 4350fe: f2 0f f0 46 49 lddqu 0x49(%rsi),%xmm0 + 435103: f3 0f 7f 47 49 movdqu %xmm0,0x49(%rdi) + 435108: f2 0f f0 46 39 lddqu 0x39(%rsi),%xmm0 + 43510d: f3 0f 7f 47 39 movdqu %xmm0,0x39(%rdi) + 435112: f2 0f f0 46 29 lddqu 0x29(%rsi),%xmm0 + 435117: f3 0f 7f 47 29 movdqu %xmm0,0x29(%rdi) + 43511c: f2 0f f0 46 19 lddqu 0x19(%rsi),%xmm0 + 435121: f3 0f 7f 47 19 movdqu %xmm0,0x19(%rdi) + 435126: f2 0f f0 46 09 lddqu 0x9(%rsi),%xmm0 + 43512b: f2 0f f0 0e lddqu (%rsi),%xmm1 + 43512f: f3 0f 7f 47 09 movdqu %xmm0,0x9(%rdi) + 435134: f3 0f 7f 0f movdqu %xmm1,(%rdi) + 435138: c3 retq + 435139: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 435140: 48 8b 56 01 mov 0x1(%rsi),%rdx + 435144: 48 8b 0e mov (%rsi),%rcx + 435147: 48 89 57 01 mov %rdx,0x1(%rdi) + 43514b: 48 89 0f mov %rcx,(%rdi) + 43514e: c3 retq + 43514f: 90 nop + 435150: f2 0f f0 46 78 lddqu 0x78(%rsi),%xmm0 + 435155: f3 0f 7f 47 78 movdqu %xmm0,0x78(%rdi) + 43515a: f2 0f f0 46 68 lddqu 0x68(%rsi),%xmm0 + 43515f: f3 0f 7f 47 68 movdqu %xmm0,0x68(%rdi) + 435164: f2 0f f0 46 58 lddqu 0x58(%rsi),%xmm0 + 435169: f3 0f 7f 47 58 movdqu %xmm0,0x58(%rdi) + 43516e: f2 0f f0 46 48 lddqu 0x48(%rsi),%xmm0 + 435173: f3 0f 7f 47 48 movdqu %xmm0,0x48(%rdi) + 435178: f2 0f f0 46 38 lddqu 0x38(%rsi),%xmm0 + 43517d: f3 0f 7f 47 38 movdqu %xmm0,0x38(%rdi) + 435182: f2 0f f0 46 28 lddqu 0x28(%rsi),%xmm0 + 435187: f3 0f 7f 47 28 movdqu %xmm0,0x28(%rdi) + 43518c: f2 0f f0 46 18 lddqu 0x18(%rsi),%xmm0 + 435191: f3 0f 7f 47 18 movdqu %xmm0,0x18(%rdi) + 435196: f2 0f f0 46 08 lddqu 0x8(%rsi),%xmm0 + 43519b: f2 0f f0 0e lddqu (%rsi),%xmm1 + 43519f: f3 0f 7f 47 08 movdqu %xmm0,0x8(%rdi) + 4351a4: f3 0f 7f 0f movdqu %xmm1,(%rdi) + 4351a8: c3 retq + 4351a9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4351b0: 48 8b 16 mov (%rsi),%rdx + 4351b3: 48 89 17 mov %rdx,(%rdi) + 4351b6: c3 retq + 4351b7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 4351be: 00 00 + 4351c0: f2 0f f0 46 77 lddqu 0x77(%rsi),%xmm0 + 4351c5: f3 0f 7f 47 77 movdqu %xmm0,0x77(%rdi) + 4351ca: f2 0f f0 46 67 lddqu 0x67(%rsi),%xmm0 + 4351cf: f3 0f 7f 47 67 movdqu %xmm0,0x67(%rdi) + 4351d4: f2 0f f0 46 57 lddqu 0x57(%rsi),%xmm0 + 4351d9: f3 0f 7f 47 57 movdqu %xmm0,0x57(%rdi) + 4351de: f2 0f f0 46 47 lddqu 0x47(%rsi),%xmm0 + 4351e3: f3 0f 7f 47 47 movdqu %xmm0,0x47(%rdi) + 4351e8: f2 0f f0 46 37 lddqu 0x37(%rsi),%xmm0 + 4351ed: f3 0f 7f 47 37 movdqu %xmm0,0x37(%rdi) + 4351f2: f2 0f f0 46 27 lddqu 0x27(%rsi),%xmm0 + 4351f7: f3 0f 7f 47 27 movdqu %xmm0,0x27(%rdi) + 4351fc: f2 0f f0 46 17 lddqu 0x17(%rsi),%xmm0 + 435201: f3 0f 7f 47 17 movdqu %xmm0,0x17(%rdi) + 435206: f2 0f f0 46 07 lddqu 0x7(%rsi),%xmm0 + 43520b: f2 0f f0 0e lddqu (%rsi),%xmm1 + 43520f: f3 0f 7f 47 07 movdqu %xmm0,0x7(%rdi) + 435214: f3 0f 7f 0f movdqu %xmm1,(%rdi) + 435218: c3 retq + 435219: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 435220: 8b 56 03 mov 0x3(%rsi),%edx + 435223: 8b 0e mov (%rsi),%ecx + 435225: 89 57 03 mov %edx,0x3(%rdi) + 435228: 89 0f mov %ecx,(%rdi) + 43522a: c3 retq + 43522b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 435230: f2 0f f0 46 76 lddqu 0x76(%rsi),%xmm0 + 435235: f3 0f 7f 47 76 movdqu %xmm0,0x76(%rdi) + 43523a: f2 0f f0 46 66 lddqu 0x66(%rsi),%xmm0 + 43523f: f3 0f 7f 47 66 movdqu %xmm0,0x66(%rdi) + 435244: f2 0f f0 46 56 lddqu 0x56(%rsi),%xmm0 + 435249: f3 0f 7f 47 56 movdqu %xmm0,0x56(%rdi) + 43524e: f2 0f f0 46 46 lddqu 0x46(%rsi),%xmm0 + 435253: f3 0f 7f 47 46 movdqu %xmm0,0x46(%rdi) + 435258: f2 0f f0 46 36 lddqu 0x36(%rsi),%xmm0 + 43525d: f3 0f 7f 47 36 movdqu %xmm0,0x36(%rdi) + 435262: f2 0f f0 46 26 lddqu 0x26(%rsi),%xmm0 + 435267: f3 0f 7f 47 26 movdqu %xmm0,0x26(%rdi) + 43526c: f2 0f f0 46 16 lddqu 0x16(%rsi),%xmm0 + 435271: f3 0f 7f 47 16 movdqu %xmm0,0x16(%rdi) + 435276: f2 0f f0 46 06 lddqu 0x6(%rsi),%xmm0 + 43527b: f2 0f f0 0e lddqu (%rsi),%xmm1 + 43527f: f3 0f 7f 47 06 movdqu %xmm0,0x6(%rdi) + 435284: f3 0f 7f 0f movdqu %xmm1,(%rdi) + 435288: c3 retq + 435289: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 435290: 8b 56 02 mov 0x2(%rsi),%edx + 435293: 8b 0e mov (%rsi),%ecx + 435295: 89 57 02 mov %edx,0x2(%rdi) + 435298: 89 0f mov %ecx,(%rdi) + 43529a: c3 retq + 43529b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4352a0: f2 0f f0 46 75 lddqu 0x75(%rsi),%xmm0 + 4352a5: f3 0f 7f 47 75 movdqu %xmm0,0x75(%rdi) + 4352aa: f2 0f f0 46 65 lddqu 0x65(%rsi),%xmm0 + 4352af: f3 0f 7f 47 65 movdqu %xmm0,0x65(%rdi) + 4352b4: f2 0f f0 46 55 lddqu 0x55(%rsi),%xmm0 + 4352b9: f3 0f 7f 47 55 movdqu %xmm0,0x55(%rdi) + 4352be: f2 0f f0 46 45 lddqu 0x45(%rsi),%xmm0 + 4352c3: f3 0f 7f 47 45 movdqu %xmm0,0x45(%rdi) + 4352c8: f2 0f f0 46 35 lddqu 0x35(%rsi),%xmm0 + 4352cd: f3 0f 7f 47 35 movdqu %xmm0,0x35(%rdi) + 4352d2: f2 0f f0 46 25 lddqu 0x25(%rsi),%xmm0 + 4352d7: f3 0f 7f 47 25 movdqu %xmm0,0x25(%rdi) + 4352dc: f2 0f f0 46 15 lddqu 0x15(%rsi),%xmm0 + 4352e1: f3 0f 7f 47 15 movdqu %xmm0,0x15(%rdi) + 4352e6: f2 0f f0 46 05 lddqu 0x5(%rsi),%xmm0 + 4352eb: f2 0f f0 0e lddqu (%rsi),%xmm1 + 4352ef: f3 0f 7f 47 05 movdqu %xmm0,0x5(%rdi) + 4352f4: f3 0f 7f 0f movdqu %xmm1,(%rdi) + 4352f8: c3 retq + 4352f9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 435300: 8b 56 01 mov 0x1(%rsi),%edx + 435303: 8b 0e mov (%rsi),%ecx + 435305: 89 57 01 mov %edx,0x1(%rdi) + 435308: 89 0f mov %ecx,(%rdi) + 43530a: c3 retq + 43530b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 435310: f2 0f f0 46 74 lddqu 0x74(%rsi),%xmm0 + 435315: f3 0f 7f 47 74 movdqu %xmm0,0x74(%rdi) + 43531a: f2 0f f0 46 64 lddqu 0x64(%rsi),%xmm0 + 43531f: f3 0f 7f 47 64 movdqu %xmm0,0x64(%rdi) + 435324: f2 0f f0 46 54 lddqu 0x54(%rsi),%xmm0 + 435329: f3 0f 7f 47 54 movdqu %xmm0,0x54(%rdi) + 43532e: f2 0f f0 46 44 lddqu 0x44(%rsi),%xmm0 + 435333: f3 0f 7f 47 44 movdqu %xmm0,0x44(%rdi) + 435338: f2 0f f0 46 34 lddqu 0x34(%rsi),%xmm0 + 43533d: f3 0f 7f 47 34 movdqu %xmm0,0x34(%rdi) + 435342: f2 0f f0 46 24 lddqu 0x24(%rsi),%xmm0 + 435347: f3 0f 7f 47 24 movdqu %xmm0,0x24(%rdi) + 43534c: f2 0f f0 46 14 lddqu 0x14(%rsi),%xmm0 + 435351: f3 0f 7f 47 14 movdqu %xmm0,0x14(%rdi) + 435356: f2 0f f0 46 04 lddqu 0x4(%rsi),%xmm0 + 43535b: f2 0f f0 0e lddqu (%rsi),%xmm1 + 43535f: f3 0f 7f 47 04 movdqu %xmm0,0x4(%rdi) + 435364: f3 0f 7f 0f movdqu %xmm1,(%rdi) + 435368: c3 retq + 435369: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 435370: 8b 16 mov (%rsi),%edx + 435372: 89 17 mov %edx,(%rdi) + 435374: c3 retq + 435375: 90 nop + 435376: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43537d: 00 00 00 + 435380: f2 0f f0 46 73 lddqu 0x73(%rsi),%xmm0 + 435385: f3 0f 7f 47 73 movdqu %xmm0,0x73(%rdi) + 43538a: f2 0f f0 46 63 lddqu 0x63(%rsi),%xmm0 + 43538f: f3 0f 7f 47 63 movdqu %xmm0,0x63(%rdi) + 435394: f2 0f f0 46 53 lddqu 0x53(%rsi),%xmm0 + 435399: f3 0f 7f 47 53 movdqu %xmm0,0x53(%rdi) + 43539e: f2 0f f0 46 43 lddqu 0x43(%rsi),%xmm0 + 4353a3: f3 0f 7f 47 43 movdqu %xmm0,0x43(%rdi) + 4353a8: f2 0f f0 46 33 lddqu 0x33(%rsi),%xmm0 + 4353ad: f3 0f 7f 47 33 movdqu %xmm0,0x33(%rdi) + 4353b2: f2 0f f0 46 23 lddqu 0x23(%rsi),%xmm0 + 4353b7: f3 0f 7f 47 23 movdqu %xmm0,0x23(%rdi) + 4353bc: f2 0f f0 46 13 lddqu 0x13(%rsi),%xmm0 + 4353c1: f3 0f 7f 47 13 movdqu %xmm0,0x13(%rdi) + 4353c6: f2 0f f0 46 03 lddqu 0x3(%rsi),%xmm0 + 4353cb: f2 0f f0 0e lddqu (%rsi),%xmm1 + 4353cf: f3 0f 7f 47 03 movdqu %xmm0,0x3(%rdi) + 4353d4: f3 0f 7f 0f movdqu %xmm1,(%rdi) + 4353d8: c3 retq + 4353d9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4353e0: 66 8b 56 01 mov 0x1(%rsi),%dx + 4353e4: 66 8b 0e mov (%rsi),%cx + 4353e7: 66 89 57 01 mov %dx,0x1(%rdi) + 4353eb: 66 89 0f mov %cx,(%rdi) + 4353ee: c3 retq + 4353ef: 90 nop + 4353f0: f2 0f f0 46 72 lddqu 0x72(%rsi),%xmm0 + 4353f5: f3 0f 7f 47 72 movdqu %xmm0,0x72(%rdi) + 4353fa: f2 0f f0 46 62 lddqu 0x62(%rsi),%xmm0 + 4353ff: f3 0f 7f 47 62 movdqu %xmm0,0x62(%rdi) + 435404: f2 0f f0 46 52 lddqu 0x52(%rsi),%xmm0 + 435409: f3 0f 7f 47 52 movdqu %xmm0,0x52(%rdi) + 43540e: f2 0f f0 46 42 lddqu 0x42(%rsi),%xmm0 + 435413: f3 0f 7f 47 42 movdqu %xmm0,0x42(%rdi) + 435418: f2 0f f0 46 32 lddqu 0x32(%rsi),%xmm0 + 43541d: f3 0f 7f 47 32 movdqu %xmm0,0x32(%rdi) + 435422: f2 0f f0 46 22 lddqu 0x22(%rsi),%xmm0 + 435427: f3 0f 7f 47 22 movdqu %xmm0,0x22(%rdi) + 43542c: f2 0f f0 46 12 lddqu 0x12(%rsi),%xmm0 + 435431: f3 0f 7f 47 12 movdqu %xmm0,0x12(%rdi) + 435436: f2 0f f0 46 02 lddqu 0x2(%rsi),%xmm0 + 43543b: f2 0f f0 0e lddqu (%rsi),%xmm1 + 43543f: f3 0f 7f 47 02 movdqu %xmm0,0x2(%rdi) + 435444: f3 0f 7f 0f movdqu %xmm1,(%rdi) + 435448: c3 retq + 435449: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 435450: 0f b7 16 movzwl (%rsi),%edx + 435453: 66 89 17 mov %dx,(%rdi) + 435456: c3 retq + 435457: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 43545e: 00 00 + 435460: f2 0f f0 46 71 lddqu 0x71(%rsi),%xmm0 + 435465: f3 0f 7f 47 71 movdqu %xmm0,0x71(%rdi) + 43546a: f2 0f f0 46 61 lddqu 0x61(%rsi),%xmm0 + 43546f: f3 0f 7f 47 61 movdqu %xmm0,0x61(%rdi) + 435474: f2 0f f0 46 51 lddqu 0x51(%rsi),%xmm0 + 435479: f3 0f 7f 47 51 movdqu %xmm0,0x51(%rdi) + 43547e: f2 0f f0 46 41 lddqu 0x41(%rsi),%xmm0 + 435483: f3 0f 7f 47 41 movdqu %xmm0,0x41(%rdi) + 435488: f2 0f f0 46 31 lddqu 0x31(%rsi),%xmm0 + 43548d: f3 0f 7f 47 31 movdqu %xmm0,0x31(%rdi) + 435492: f2 0f f0 46 21 lddqu 0x21(%rsi),%xmm0 + 435497: f3 0f 7f 47 21 movdqu %xmm0,0x21(%rdi) + 43549c: f2 0f f0 46 11 lddqu 0x11(%rsi),%xmm0 + 4354a1: f3 0f 7f 47 11 movdqu %xmm0,0x11(%rdi) + 4354a6: f2 0f f0 46 01 lddqu 0x1(%rsi),%xmm0 + 4354ab: f2 0f f0 0e lddqu (%rsi),%xmm1 + 4354af: f3 0f 7f 47 01 movdqu %xmm0,0x1(%rdi) + 4354b4: f3 0f 7f 0f movdqu %xmm1,(%rdi) + 4354b8: c3 retq + 4354b9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4354c0: 0f b6 16 movzbl (%rsi),%edx + 4354c3: 88 17 mov %dl,(%rdi) + 4354c5: c3 retq + 4354c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4354cd: 00 00 00 + +00000000004354d0 <__memmove_chk_avx512_no_vzeroupper>: + 4354d0: 48 39 d1 cmp %rdx,%rcx + 4354d3: 0f 82 d7 d5 00 00 jb 442ab0 <__chk_fail> + 4354d9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + +00000000004354e0 <__memmove_avx512_no_vzeroupper>: + 4354e0: 48 89 f8 mov %rdi,%rax + 4354e3: 48 8d 0c 16 lea (%rsi,%rdx,1),%rcx + 4354e7: 4c 8d 0c 17 lea (%rdi,%rdx,1),%r9 + 4354eb: 48 81 fa 00 02 00 00 cmp $0x200,%rdx + 4354f2: 0f 87 5d 01 00 00 ja 435655 <__memmove_avx512_no_vzeroupper+0x175> + 4354f8: 48 83 fa 10 cmp $0x10,%rdx + 4354fc: 0f 86 0f 01 00 00 jbe 435611 <__memmove_avx512_no_vzeroupper+0x131> + 435502: 48 81 fa 00 01 00 00 cmp $0x100,%rdx + 435509: 72 6f jb 43557a <__memmove_avx512_no_vzeroupper+0x9a> + 43550b: 62 f1 7c 48 10 06 vmovups (%rsi),%zmm0 + 435511: 62 f1 7c 48 10 4e 01 vmovups 0x40(%rsi),%zmm1 + 435518: 62 f1 7c 48 10 56 02 vmovups 0x80(%rsi),%zmm2 + 43551f: 62 f1 7c 48 10 5e 03 vmovups 0xc0(%rsi),%zmm3 + 435526: 62 f1 7c 48 10 61 fc vmovups -0x100(%rcx),%zmm4 + 43552d: 62 f1 7c 48 10 69 fd vmovups -0xc0(%rcx),%zmm5 + 435534: 62 f1 7c 48 10 71 fe vmovups -0x80(%rcx),%zmm6 + 43553b: 62 f1 7c 48 10 79 ff vmovups -0x40(%rcx),%zmm7 + 435542: 62 f1 7c 48 11 07 vmovups %zmm0,(%rdi) + 435548: 62 f1 7c 48 11 4f 01 vmovups %zmm1,0x40(%rdi) + 43554f: 62 f1 7c 48 11 57 02 vmovups %zmm2,0x80(%rdi) + 435556: 62 f1 7c 48 11 5f 03 vmovups %zmm3,0xc0(%rdi) + 43555d: 62 d1 7c 48 11 61 fc vmovups %zmm4,-0x100(%r9) + 435564: 62 d1 7c 48 11 69 fd vmovups %zmm5,-0xc0(%r9) + 43556b: 62 d1 7c 48 11 71 fe vmovups %zmm6,-0x80(%r9) + 435572: 62 d1 7c 48 11 79 ff vmovups %zmm7,-0x40(%r9) + 435579: c3 retq + 43557a: 80 fa 80 cmp $0x80,%dl + 43557d: 72 37 jb 4355b6 <__memmove_avx512_no_vzeroupper+0xd6> + 43557f: 62 f1 7c 48 10 06 vmovups (%rsi),%zmm0 + 435585: 62 f1 7c 48 10 4e 01 vmovups 0x40(%rsi),%zmm1 + 43558c: 62 f1 7c 48 10 51 fe vmovups -0x80(%rcx),%zmm2 + 435593: 62 f1 7c 48 10 59 ff vmovups -0x40(%rcx),%zmm3 + 43559a: 62 f1 7c 48 11 07 vmovups %zmm0,(%rdi) + 4355a0: 62 f1 7c 48 11 4f 01 vmovups %zmm1,0x40(%rdi) + 4355a7: 62 d1 7c 48 11 51 fe vmovups %zmm2,-0x80(%r9) + 4355ae: 62 d1 7c 48 11 59 ff vmovups %zmm3,-0x40(%r9) + 4355b5: c3 retq + 4355b6: 80 fa 40 cmp $0x40,%dl + 4355b9: 72 29 jb 4355e4 <__memmove_avx512_no_vzeroupper+0x104> + 4355bb: c5 fe 6f 06 vmovdqu (%rsi),%ymm0 + 4355bf: c5 fe 6f 4e 20 vmovdqu 0x20(%rsi),%ymm1 + 4355c4: c5 fe 6f 51 c0 vmovdqu -0x40(%rcx),%ymm2 + 4355c9: c5 fe 6f 59 e0 vmovdqu -0x20(%rcx),%ymm3 + 4355ce: c5 fe 7f 07 vmovdqu %ymm0,(%rdi) + 4355d2: c5 fe 7f 4f 20 vmovdqu %ymm1,0x20(%rdi) + 4355d7: c4 c1 7e 7f 51 c0 vmovdqu %ymm2,-0x40(%r9) + 4355dd: c4 c1 7e 7f 59 e0 vmovdqu %ymm3,-0x20(%r9) + 4355e3: c3 retq + 4355e4: 80 fa 20 cmp $0x20,%dl + 4355e7: 72 14 jb 4355fd <__memmove_avx512_no_vzeroupper+0x11d> + 4355e9: c5 fe 6f 06 vmovdqu (%rsi),%ymm0 + 4355ed: c5 fe 6f 49 e0 vmovdqu -0x20(%rcx),%ymm1 + 4355f2: c5 fe 7f 07 vmovdqu %ymm0,(%rdi) + 4355f6: c4 c1 7e 7f 49 e0 vmovdqu %ymm1,-0x20(%r9) + 4355fc: c3 retq + 4355fd: c5 fa 6f 06 vmovdqu (%rsi),%xmm0 + 435601: c5 fa 6f 49 f0 vmovdqu -0x10(%rcx),%xmm1 + 435606: c5 fa 7f 07 vmovdqu %xmm0,(%rdi) + 43560a: c4 c1 7a 7f 49 f0 vmovdqu %xmm1,-0x10(%r9) + 435610: c3 retq + 435611: 80 fa 08 cmp $0x8,%dl + 435614: 72 0f jb 435625 <__memmove_avx512_no_vzeroupper+0x145> + 435616: 48 8b 36 mov (%rsi),%rsi + 435619: 48 8b 49 f8 mov -0x8(%rcx),%rcx + 43561d: 48 89 37 mov %rsi,(%rdi) + 435620: 49 89 49 f8 mov %rcx,-0x8(%r9) + 435624: c3 retq + 435625: 80 fa 04 cmp $0x4,%dl + 435628: 72 0c jb 435636 <__memmove_avx512_no_vzeroupper+0x156> + 43562a: 8b 36 mov (%rsi),%esi + 43562c: 8b 49 fc mov -0x4(%rcx),%ecx + 43562f: 89 37 mov %esi,(%rdi) + 435631: 41 89 49 fc mov %ecx,-0x4(%r9) + 435635: c3 retq + 435636: 80 fa 02 cmp $0x2,%dl + 435639: 72 10 jb 43564b <__memmove_avx512_no_vzeroupper+0x16b> + 43563b: 66 8b 36 mov (%rsi),%si + 43563e: 66 8b 49 fe mov -0x2(%rcx),%cx + 435642: 66 89 37 mov %si,(%rdi) + 435645: 66 41 89 49 fe mov %cx,-0x2(%r9) + 43564a: c3 retq + 43564b: 80 fa 01 cmp $0x1,%dl + 43564e: 72 04 jb 435654 <__memmove_avx512_no_vzeroupper+0x174> + 435650: 8a 0e mov (%rsi),%cl + 435652: 88 0f mov %cl,(%rdi) + 435654: c3 retq + 435655: 4c 8b 05 54 5a 29 00 mov 0x295a54(%rip),%r8 # 6cb0b0 <__x86_shared_cache_size_half> + 43565c: 4c 39 c2 cmp %r8,%rdx + 43565f: 0f 83 18 04 00 00 jae 435a7d <__memmove_avx512_no_vzeroupper+0x59d> + 435665: 48 81 fa 00 04 00 00 cmp $0x400,%rdx + 43566c: 0f 87 42 01 00 00 ja 4357b4 <__memmove_avx512_no_vzeroupper+0x2d4> + 435672: 0f 18 16 prefetcht1 (%rsi) + 435675: 0f 18 56 40 prefetcht1 0x40(%rsi) + 435679: 0f 18 96 80 00 00 00 prefetcht1 0x80(%rsi) + 435680: 0f 18 96 c0 00 00 00 prefetcht1 0xc0(%rsi) + 435687: 0f 18 96 00 01 00 00 prefetcht1 0x100(%rsi) + 43568e: 0f 18 96 40 01 00 00 prefetcht1 0x140(%rsi) + 435695: 0f 18 96 80 01 00 00 prefetcht1 0x180(%rsi) + 43569c: 0f 18 96 c0 01 00 00 prefetcht1 0x1c0(%rsi) + 4356a3: 0f 18 91 00 fe ff ff prefetcht1 -0x200(%rcx) + 4356aa: 0f 18 91 40 fe ff ff prefetcht1 -0x1c0(%rcx) + 4356b1: 0f 18 91 80 fe ff ff prefetcht1 -0x180(%rcx) + 4356b8: 0f 18 91 c0 fe ff ff prefetcht1 -0x140(%rcx) + 4356bf: 0f 18 91 00 ff ff ff prefetcht1 -0x100(%rcx) + 4356c6: 0f 18 91 40 ff ff ff prefetcht1 -0xc0(%rcx) + 4356cd: 0f 18 51 80 prefetcht1 -0x80(%rcx) + 4356d1: 0f 18 51 c0 prefetcht1 -0x40(%rcx) + 4356d5: 62 f1 7c 48 10 06 vmovups (%rsi),%zmm0 + 4356db: 62 f1 7c 48 10 4e 01 vmovups 0x40(%rsi),%zmm1 + 4356e2: 62 f1 7c 48 10 56 02 vmovups 0x80(%rsi),%zmm2 + 4356e9: 62 f1 7c 48 10 5e 03 vmovups 0xc0(%rsi),%zmm3 + 4356f0: 62 f1 7c 48 10 66 04 vmovups 0x100(%rsi),%zmm4 + 4356f7: 62 f1 7c 48 10 6e 05 vmovups 0x140(%rsi),%zmm5 + 4356fe: 62 f1 7c 48 10 76 06 vmovups 0x180(%rsi),%zmm6 + 435705: 62 f1 7c 48 10 7e 07 vmovups 0x1c0(%rsi),%zmm7 + 43570c: 62 71 7c 48 10 41 f8 vmovups -0x200(%rcx),%zmm8 + 435713: 62 71 7c 48 10 49 f9 vmovups -0x1c0(%rcx),%zmm9 + 43571a: 62 71 7c 48 10 51 fa vmovups -0x180(%rcx),%zmm10 + 435721: 62 71 7c 48 10 59 fb vmovups -0x140(%rcx),%zmm11 + 435728: 62 71 7c 48 10 61 fc vmovups -0x100(%rcx),%zmm12 + 43572f: 62 71 7c 48 10 69 fd vmovups -0xc0(%rcx),%zmm13 + 435736: 62 71 7c 48 10 71 fe vmovups -0x80(%rcx),%zmm14 + 43573d: 62 71 7c 48 10 79 ff vmovups -0x40(%rcx),%zmm15 + 435744: 62 f1 7c 48 11 07 vmovups %zmm0,(%rdi) + 43574a: 62 f1 7c 48 11 4f 01 vmovups %zmm1,0x40(%rdi) + 435751: 62 f1 7c 48 11 57 02 vmovups %zmm2,0x80(%rdi) + 435758: 62 f1 7c 48 11 5f 03 vmovups %zmm3,0xc0(%rdi) + 43575f: 62 f1 7c 48 11 67 04 vmovups %zmm4,0x100(%rdi) + 435766: 62 f1 7c 48 11 6f 05 vmovups %zmm5,0x140(%rdi) + 43576d: 62 f1 7c 48 11 77 06 vmovups %zmm6,0x180(%rdi) + 435774: 62 f1 7c 48 11 7f 07 vmovups %zmm7,0x1c0(%rdi) + 43577b: 62 51 7c 48 11 41 f8 vmovups %zmm8,-0x200(%r9) + 435782: 62 51 7c 48 11 49 f9 vmovups %zmm9,-0x1c0(%r9) + 435789: 62 51 7c 48 11 51 fa vmovups %zmm10,-0x180(%r9) + 435790: 62 51 7c 48 11 59 fb vmovups %zmm11,-0x140(%r9) + 435797: 62 51 7c 48 11 61 fc vmovups %zmm12,-0x100(%r9) + 43579e: 62 51 7c 48 11 69 fd vmovups %zmm13,-0xc0(%r9) + 4357a5: 62 51 7c 48 11 71 fe vmovups %zmm14,-0x80(%r9) + 4357ac: 62 51 7c 48 11 79 ff vmovups %zmm15,-0x40(%r9) + 4357b3: c3 retq + 4357b4: 48 39 f7 cmp %rsi,%rdi + 4357b7: 0f 87 5e 01 00 00 ja 43591b <__memmove_avx512_no_vzeroupper+0x43b> + 4357bd: 49 81 e9 00 02 00 00 sub $0x200,%r9 + 4357c4: 62 71 7c 48 10 41 f8 vmovups -0x200(%rcx),%zmm8 + 4357cb: 62 71 7c 48 10 49 f9 vmovups -0x1c0(%rcx),%zmm9 + 4357d2: 62 71 7c 48 10 51 fa vmovups -0x180(%rcx),%zmm10 + 4357d9: 62 71 7c 48 10 59 fb vmovups -0x140(%rcx),%zmm11 + 4357e0: 62 71 7c 48 10 61 fc vmovups -0x100(%rcx),%zmm12 + 4357e7: 62 71 7c 48 10 69 fd vmovups -0xc0(%rcx),%zmm13 + 4357ee: 62 71 7c 48 10 71 fe vmovups -0x80(%rcx),%zmm14 + 4357f5: 62 71 7c 48 10 79 ff vmovups -0x40(%rcx),%zmm15 + 4357fc: 0f 18 16 prefetcht1 (%rsi) + 4357ff: 0f 18 56 40 prefetcht1 0x40(%rsi) + 435803: 0f 18 96 80 00 00 00 prefetcht1 0x80(%rsi) + 43580a: 0f 18 96 c0 00 00 00 prefetcht1 0xc0(%rsi) + 435811: 0f 18 96 00 01 00 00 prefetcht1 0x100(%rsi) + 435818: 0f 18 96 40 01 00 00 prefetcht1 0x140(%rsi) + 43581f: 0f 18 96 80 01 00 00 prefetcht1 0x180(%rsi) + 435826: 0f 18 96 c0 01 00 00 prefetcht1 0x1c0(%rsi) + 43582d: 62 f1 7c 48 10 06 vmovups (%rsi),%zmm0 + 435833: 62 f1 7c 48 10 4e 01 vmovups 0x40(%rsi),%zmm1 + 43583a: 62 f1 7c 48 10 56 02 vmovups 0x80(%rsi),%zmm2 + 435841: 62 f1 7c 48 10 5e 03 vmovups 0xc0(%rsi),%zmm3 + 435848: 62 f1 7c 48 10 66 04 vmovups 0x100(%rsi),%zmm4 + 43584f: 62 f1 7c 48 10 6e 05 vmovups 0x140(%rsi),%zmm5 + 435856: 62 f1 7c 48 10 76 06 vmovups 0x180(%rsi),%zmm6 + 43585d: 62 f1 7c 48 10 7e 07 vmovups 0x1c0(%rsi),%zmm7 + 435864: 48 81 c6 00 02 00 00 add $0x200,%rsi + 43586b: 0f 18 16 prefetcht1 (%rsi) + 43586e: 0f 18 56 40 prefetcht1 0x40(%rsi) + 435872: 0f 18 96 80 00 00 00 prefetcht1 0x80(%rsi) + 435879: 0f 18 96 c0 00 00 00 prefetcht1 0xc0(%rsi) + 435880: 0f 18 96 00 01 00 00 prefetcht1 0x100(%rsi) + 435887: 0f 18 96 40 01 00 00 prefetcht1 0x140(%rsi) + 43588e: 0f 18 96 80 01 00 00 prefetcht1 0x180(%rsi) + 435895: 0f 18 96 c0 01 00 00 prefetcht1 0x1c0(%rsi) + 43589c: 62 f1 7c 48 11 07 vmovups %zmm0,(%rdi) + 4358a2: 62 f1 7c 48 11 4f 01 vmovups %zmm1,0x40(%rdi) + 4358a9: 62 f1 7c 48 11 57 02 vmovups %zmm2,0x80(%rdi) + 4358b0: 62 f1 7c 48 11 5f 03 vmovups %zmm3,0xc0(%rdi) + 4358b7: 62 f1 7c 48 11 67 04 vmovups %zmm4,0x100(%rdi) + 4358be: 62 f1 7c 48 11 6f 05 vmovups %zmm5,0x140(%rdi) + 4358c5: 62 f1 7c 48 11 77 06 vmovups %zmm6,0x180(%rdi) + 4358cc: 62 f1 7c 48 11 7f 07 vmovups %zmm7,0x1c0(%rdi) + 4358d3: 48 81 c7 00 02 00 00 add $0x200,%rdi + 4358da: 4c 39 cf cmp %r9,%rdi + 4358dd: 0f 82 4a ff ff ff jb 43582d <__memmove_avx512_no_vzeroupper+0x34d> + 4358e3: 62 51 7c 48 11 01 vmovups %zmm8,(%r9) + 4358e9: 62 51 7c 48 11 49 01 vmovups %zmm9,0x40(%r9) + 4358f0: 62 51 7c 48 11 51 02 vmovups %zmm10,0x80(%r9) + 4358f7: 62 51 7c 48 11 59 03 vmovups %zmm11,0xc0(%r9) + 4358fe: 62 51 7c 48 11 61 04 vmovups %zmm12,0x100(%r9) + 435905: 62 51 7c 48 11 69 05 vmovups %zmm13,0x140(%r9) + 43590c: 62 51 7c 48 11 71 06 vmovups %zmm14,0x180(%r9) + 435913: 62 51 7c 48 11 79 07 vmovups %zmm15,0x1c0(%r9) + 43591a: c3 retq + 43591b: 48 81 c7 00 02 00 00 add $0x200,%rdi + 435922: 62 71 7c 48 10 46 07 vmovups 0x1c0(%rsi),%zmm8 + 435929: 62 71 7c 48 10 4e 06 vmovups 0x180(%rsi),%zmm9 + 435930: 62 71 7c 48 10 56 05 vmovups 0x140(%rsi),%zmm10 + 435937: 62 71 7c 48 10 5e 04 vmovups 0x100(%rsi),%zmm11 + 43593e: 62 71 7c 48 10 66 03 vmovups 0xc0(%rsi),%zmm12 + 435945: 62 71 7c 48 10 6e 02 vmovups 0x80(%rsi),%zmm13 + 43594c: 62 71 7c 48 10 76 01 vmovups 0x40(%rsi),%zmm14 + 435953: 62 71 7c 48 10 3e vmovups (%rsi),%zmm15 + 435959: 0f 18 51 c0 prefetcht1 -0x40(%rcx) + 43595d: 0f 18 51 80 prefetcht1 -0x80(%rcx) + 435961: 0f 18 91 40 ff ff ff prefetcht1 -0xc0(%rcx) + 435968: 0f 18 91 00 ff ff ff prefetcht1 -0x100(%rcx) + 43596f: 0f 18 91 c0 fe ff ff prefetcht1 -0x140(%rcx) + 435976: 0f 18 91 80 fe ff ff prefetcht1 -0x180(%rcx) + 43597d: 0f 18 91 40 fe ff ff prefetcht1 -0x1c0(%rcx) + 435984: 0f 18 91 00 fe ff ff prefetcht1 -0x200(%rcx) + 43598b: 62 f1 7c 48 10 41 ff vmovups -0x40(%rcx),%zmm0 + 435992: 62 f1 7c 48 10 49 fe vmovups -0x80(%rcx),%zmm1 + 435999: 62 f1 7c 48 10 51 fd vmovups -0xc0(%rcx),%zmm2 + 4359a0: 62 f1 7c 48 10 59 fc vmovups -0x100(%rcx),%zmm3 + 4359a7: 62 f1 7c 48 10 61 fb vmovups -0x140(%rcx),%zmm4 + 4359ae: 62 f1 7c 48 10 69 fa vmovups -0x180(%rcx),%zmm5 + 4359b5: 62 f1 7c 48 10 71 f9 vmovups -0x1c0(%rcx),%zmm6 + 4359bc: 62 f1 7c 48 10 79 f8 vmovups -0x200(%rcx),%zmm7 + 4359c3: 48 81 e9 00 02 00 00 sub $0x200,%rcx + 4359ca: 0f 18 51 c0 prefetcht1 -0x40(%rcx) + 4359ce: 0f 18 51 80 prefetcht1 -0x80(%rcx) + 4359d2: 0f 18 91 40 ff ff ff prefetcht1 -0xc0(%rcx) + 4359d9: 0f 18 91 00 ff ff ff prefetcht1 -0x100(%rcx) + 4359e0: 0f 18 91 c0 fe ff ff prefetcht1 -0x140(%rcx) + 4359e7: 0f 18 91 80 fe ff ff prefetcht1 -0x180(%rcx) + 4359ee: 0f 18 91 40 fe ff ff prefetcht1 -0x1c0(%rcx) + 4359f5: 0f 18 91 00 fe ff ff prefetcht1 -0x200(%rcx) + 4359fc: 62 d1 7c 48 11 41 ff vmovups %zmm0,-0x40(%r9) + 435a03: 62 d1 7c 48 11 49 fe vmovups %zmm1,-0x80(%r9) + 435a0a: 62 d1 7c 48 11 51 fd vmovups %zmm2,-0xc0(%r9) + 435a11: 62 d1 7c 48 11 59 fc vmovups %zmm3,-0x100(%r9) + 435a18: 62 d1 7c 48 11 61 fb vmovups %zmm4,-0x140(%r9) + 435a1f: 62 d1 7c 48 11 69 fa vmovups %zmm5,-0x180(%r9) + 435a26: 62 d1 7c 48 11 71 f9 vmovups %zmm6,-0x1c0(%r9) + 435a2d: 62 d1 7c 48 11 79 f8 vmovups %zmm7,-0x200(%r9) + 435a34: 49 81 e9 00 02 00 00 sub $0x200,%r9 + 435a3b: 49 39 f9 cmp %rdi,%r9 + 435a3e: 0f 87 47 ff ff ff ja 43598b <__memmove_avx512_no_vzeroupper+0x4ab> + 435a44: 62 71 7c 48 11 47 ff vmovups %zmm8,-0x40(%rdi) + 435a4b: 62 71 7c 48 11 4f fe vmovups %zmm9,-0x80(%rdi) + 435a52: 62 71 7c 48 11 57 fd vmovups %zmm10,-0xc0(%rdi) + 435a59: 62 71 7c 48 11 5f fc vmovups %zmm11,-0x100(%rdi) + 435a60: 62 71 7c 48 11 67 fb vmovups %zmm12,-0x140(%rdi) + 435a67: 62 71 7c 48 11 6f fa vmovups %zmm13,-0x180(%rdi) + 435a6e: 62 71 7c 48 11 77 f9 vmovups %zmm14,-0x1c0(%rdi) + 435a75: 62 71 7c 48 11 7f f8 vmovups %zmm15,-0x200(%rdi) + 435a7c: c3 retq + 435a7d: 48 39 f7 cmp %rsi,%rdi + 435a80: 0f 87 c9 00 00 00 ja 435b4f <__memmove_avx512_no_vzeroupper+0x66f> + 435a86: 62 f1 7c 48 10 26 vmovups (%rsi),%zmm4 + 435a8c: 62 f1 7c 48 10 6e 01 vmovups 0x40(%rsi),%zmm5 + 435a93: 49 89 f8 mov %rdi,%r8 + 435a96: 48 83 e7 80 and $0xffffffffffffff80,%rdi + 435a9a: 48 81 c7 80 00 00 00 add $0x80,%rdi + 435aa1: 49 29 f8 sub %rdi,%r8 + 435aa4: 4c 29 c6 sub %r8,%rsi + 435aa7: 4c 01 c2 add %r8,%rdx + 435aaa: 0f 18 96 00 02 00 00 prefetcht1 0x200(%rsi) + 435ab1: 0f 18 96 40 02 00 00 prefetcht1 0x240(%rsi) + 435ab8: 0f 18 96 80 02 00 00 prefetcht1 0x280(%rsi) + 435abf: 0f 18 96 c0 02 00 00 prefetcht1 0x2c0(%rsi) + 435ac6: 0f 18 96 00 03 00 00 prefetcht1 0x300(%rsi) + 435acd: 0f 18 96 40 03 00 00 prefetcht1 0x340(%rsi) + 435ad4: 0f 18 96 80 03 00 00 prefetcht1 0x380(%rsi) + 435adb: 0f 18 96 c0 03 00 00 prefetcht1 0x3c0(%rsi) + 435ae2: 62 f1 fe 48 6f 06 vmovdqu64 (%rsi),%zmm0 + 435ae8: 62 f1 fe 48 6f 4e 01 vmovdqu64 0x40(%rsi),%zmm1 + 435aef: 62 f1 fe 48 6f 56 02 vmovdqu64 0x80(%rsi),%zmm2 + 435af6: 62 f1 fe 48 6f 5e 03 vmovdqu64 0xc0(%rsi),%zmm3 + 435afd: 62 f1 7d 48 e7 07 vmovntdq %zmm0,(%rdi) + 435b03: 62 f1 7d 48 e7 4f 01 vmovntdq %zmm1,0x40(%rdi) + 435b0a: 62 f1 7d 48 e7 57 02 vmovntdq %zmm2,0x80(%rdi) + 435b11: 62 f1 7d 48 e7 5f 03 vmovntdq %zmm3,0xc0(%rdi) + 435b18: 48 81 ea 00 01 00 00 sub $0x100,%rdx + 435b1f: 48 81 c6 00 01 00 00 add $0x100,%rsi + 435b26: 48 81 c7 00 01 00 00 add $0x100,%rdi + 435b2d: 48 81 fa 00 01 00 00 cmp $0x100,%rdx + 435b34: 0f 87 70 ff ff ff ja 435aaa <__memmove_avx512_no_vzeroupper+0x5ca> + 435b3a: 0f ae f8 sfence + 435b3d: 62 f1 7c 48 11 20 vmovups %zmm4,(%rax) + 435b43: 62 f1 7c 48 11 68 01 vmovups %zmm5,0x40(%rax) + 435b4a: e9 a9 f9 ff ff jmpq 4354f8 <__memmove_avx512_no_vzeroupper+0x18> + 435b4f: 62 f1 7c 48 10 61 fe vmovups -0x80(%rcx),%zmm4 + 435b56: 62 f1 7c 48 10 69 ff vmovups -0x40(%rcx),%zmm5 + 435b5d: 4d 89 c8 mov %r9,%r8 + 435b60: 49 83 e1 80 and $0xffffffffffffff80,%r9 + 435b64: 4d 29 c8 sub %r9,%r8 + 435b67: 4c 29 c1 sub %r8,%rcx + 435b6a: 4c 29 c2 sub %r8,%rdx + 435b6d: 4d 01 c8 add %r9,%r8 + 435b70: 0f 18 91 00 fc ff ff prefetcht1 -0x400(%rcx) + 435b77: 0f 18 91 40 fc ff ff prefetcht1 -0x3c0(%rcx) + 435b7e: 0f 18 91 80 fc ff ff prefetcht1 -0x380(%rcx) + 435b85: 0f 18 91 c0 fc ff ff prefetcht1 -0x340(%rcx) + 435b8c: 0f 18 91 00 fd ff ff prefetcht1 -0x300(%rcx) + 435b93: 0f 18 91 40 fd ff ff prefetcht1 -0x2c0(%rcx) + 435b9a: 0f 18 91 80 fd ff ff prefetcht1 -0x280(%rcx) + 435ba1: 0f 18 91 c0 fd ff ff prefetcht1 -0x240(%rcx) + 435ba8: 62 f1 fe 48 6f 41 fc vmovdqu64 -0x100(%rcx),%zmm0 + 435baf: 62 f1 fe 48 6f 49 fd vmovdqu64 -0xc0(%rcx),%zmm1 + 435bb6: 62 f1 fe 48 6f 51 fe vmovdqu64 -0x80(%rcx),%zmm2 + 435bbd: 62 f1 fe 48 6f 59 ff vmovdqu64 -0x40(%rcx),%zmm3 + 435bc4: 62 d1 7d 48 e7 41 fc vmovntdq %zmm0,-0x100(%r9) + 435bcb: 62 d1 7d 48 e7 49 fd vmovntdq %zmm1,-0xc0(%r9) + 435bd2: 62 d1 7d 48 e7 51 fe vmovntdq %zmm2,-0x80(%r9) + 435bd9: 62 d1 7d 48 e7 59 ff vmovntdq %zmm3,-0x40(%r9) + 435be0: 48 81 ea 00 01 00 00 sub $0x100,%rdx + 435be7: 48 81 e9 00 01 00 00 sub $0x100,%rcx + 435bee: 49 81 e9 00 01 00 00 sub $0x100,%r9 + 435bf5: 48 81 fa 00 01 00 00 cmp $0x100,%rdx + 435bfc: 0f 87 6e ff ff ff ja 435b70 <__memmove_avx512_no_vzeroupper+0x690> + 435c02: 0f ae f8 sfence + 435c05: 62 d1 7c 48 11 60 fe vmovups %zmm4,-0x80(%r8) + 435c0c: 62 d1 7c 48 11 68 ff vmovups %zmm5,-0x40(%r8) + 435c13: e9 e0 f8 ff ff jmpq 4354f8 <__memmove_avx512_no_vzeroupper+0x18> + 435c18: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 435c1f: 00 + +0000000000435c20 <__strcasecmp_ssse3>: + 435c20: 48 c7 c0 b8 ff ff ff mov $0xffffffffffffffb8,%rax + 435c27: 64 48 8b 10 mov %fs:(%rax),%rdx + 435c2b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + +0000000000435c30 <__strcasecmp_l_ssse3>: + 435c30: 48 8b 02 mov (%rdx),%rax + 435c33: f7 80 78 02 00 00 01 testl $0x1,0x278(%rax) + 435c3a: 00 00 00 + 435c3d: 0f 85 bd 86 00 00 jne 43e300 <__strcasecmp_l_nonascii> + 435c43: 89 f1 mov %esi,%ecx + 435c45: 89 f8 mov %edi,%eax + 435c47: 48 83 e1 3f and $0x3f,%rcx + 435c4b: 48 83 e0 3f and $0x3f,%rax + 435c4f: 66 0f 6f 2d 59 d4 06 movdqa 0x6d459(%rip),%xmm5 # 4a30b0 <__func__.10972+0xf0> + 435c56: 00 + 435c57: 66 0f 6f 35 61 d4 06 movdqa 0x6d461(%rip),%xmm6 # 4a30c0 <__func__.10972+0x100> + 435c5e: 00 + 435c5f: 66 0f 6f 3d 69 d4 06 movdqa 0x6d469(%rip),%xmm7 # 4a30d0 + 435c66: 00 + 435c67: 83 f9 30 cmp $0x30,%ecx + 435c6a: 0f 87 90 00 00 00 ja 435d00 <__strcasecmp_l_ssse3+0xd0> + 435c70: 83 f8 30 cmp $0x30,%eax + 435c73: 0f 87 87 00 00 00 ja 435d00 <__strcasecmp_l_ssse3+0xd0> + 435c79: 66 0f 12 0f movlpd (%rdi),%xmm1 + 435c7d: 66 0f 12 16 movlpd (%rsi),%xmm2 + 435c81: 66 0f 16 4f 08 movhpd 0x8(%rdi),%xmm1 + 435c86: 66 0f 16 56 08 movhpd 0x8(%rsi),%xmm2 + 435c8b: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 435c90: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 435c95: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 435c9a: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 435c9f: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 435ca4: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 435ca9: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 435cae: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 435cb3: 66 45 0f db c1 pand %xmm9,%xmm8 + 435cb8: 66 45 0f db d3 pand %xmm11,%xmm10 + 435cbd: 66 44 0f db c7 pand %xmm7,%xmm8 + 435cc2: 66 44 0f db d7 pand %xmm7,%xmm10 + 435cc7: 66 41 0f eb c8 por %xmm8,%xmm1 + 435ccc: 66 41 0f eb d2 por %xmm10,%xmm2 + 435cd1: 66 0f ef c0 pxor %xmm0,%xmm0 + 435cd5: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 435cd9: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 435cdd: 66 0f f8 c8 psubb %xmm0,%xmm1 + 435ce1: 66 0f d7 d1 pmovmskb %xmm1,%edx + 435ce5: 81 ea ff ff 00 00 sub $0xffff,%edx + 435ceb: 0f 85 3f 20 00 00 jne 437d30 <__strcasecmp_l_ssse3+0x2100> + 435cf1: 48 83 c6 10 add $0x10,%rsi + 435cf5: 48 83 c7 10 add $0x10,%rdi + 435cf9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 435d00: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi + 435d04: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi + 435d08: ba ff ff 00 00 mov $0xffff,%edx + 435d0d: 45 31 c0 xor %r8d,%r8d + 435d10: 83 e1 0f and $0xf,%ecx + 435d13: 83 e0 0f and $0xf,%eax + 435d16: 39 c1 cmp %eax,%ecx + 435d18: 74 26 je 435d40 <__strcasecmp_l_ssse3+0x110> + 435d1a: 77 07 ja 435d23 <__strcasecmp_l_ssse3+0xf3> + 435d1c: 41 89 d0 mov %edx,%r8d + 435d1f: 91 xchg %eax,%ecx + 435d20: 48 87 f7 xchg %rsi,%rdi + 435d23: 4c 8d 48 0f lea 0xf(%rax),%r9 + 435d27: 49 29 c9 sub %rcx,%r9 + 435d2a: 4c 8d 15 3f dd 06 00 lea 0x6dd3f(%rip),%r10 # 4a3a70 + 435d31: 4f 63 0c 8a movslq (%r10,%r9,4),%r9 + 435d35: 4f 8d 14 0a lea (%r10,%r9,1),%r10 + 435d39: 41 ff e2 jmpq *%r10 + 435d3c: 0f 1f 40 00 nopl 0x0(%rax) + 435d40: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 435d44: 66 0f ef c0 pxor %xmm0,%xmm0 + 435d48: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 435d4c: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 435d50: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 435d55: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 435d5a: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 435d5f: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 435d64: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 435d69: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 435d6e: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 435d73: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 435d78: 66 45 0f db c1 pand %xmm9,%xmm8 + 435d7d: 66 45 0f db d3 pand %xmm11,%xmm10 + 435d82: 66 44 0f db c7 pand %xmm7,%xmm8 + 435d87: 66 44 0f db d7 pand %xmm7,%xmm10 + 435d8c: 66 41 0f eb c8 por %xmm8,%xmm1 + 435d91: 66 41 0f eb d2 por %xmm10,%xmm2 + 435d96: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 435d9a: 66 0f f8 c8 psubb %xmm0,%xmm1 + 435d9e: 66 44 0f d7 c9 pmovmskb %xmm1,%r9d + 435da3: d3 ea shr %cl,%edx + 435da5: 41 d3 e9 shr %cl,%r9d + 435da8: 44 29 ca sub %r9d,%edx + 435dab: 0f 85 64 1f 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> + 435db1: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 435db8: 49 c7 c1 10 00 00 00 mov $0x10,%r9 + 435dbf: 66 0f ef c0 pxor %xmm0,%xmm0 + 435dc3: 0f 1f 00 nopl (%rax) + 435dc6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 435dcd: 00 00 00 + 435dd0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 435dd5: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 435dda: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 435ddf: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 435de4: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 435de9: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 435dee: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 435df3: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 435df8: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 435dfd: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 435e02: 66 45 0f db c1 pand %xmm9,%xmm8 + 435e07: 66 45 0f db d3 pand %xmm11,%xmm10 + 435e0c: 66 44 0f db c7 pand %xmm7,%xmm8 + 435e11: 66 44 0f db d7 pand %xmm7,%xmm10 + 435e16: 66 41 0f eb c8 por %xmm8,%xmm1 + 435e1b: 66 41 0f eb d2 por %xmm10,%xmm2 + 435e20: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 435e24: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 435e28: 66 0f f8 c8 psubb %xmm0,%xmm1 + 435e2c: 66 0f d7 d1 pmovmskb %xmm1,%edx + 435e30: 81 ea ff ff 00 00 sub $0xffff,%edx + 435e36: 0f 85 d4 1e 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 435e3c: 48 83 c1 10 add $0x10,%rcx + 435e40: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 435e45: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 435e4a: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 435e4f: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 435e54: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 435e59: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 435e5e: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 435e63: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 435e68: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 435e6d: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 435e72: 66 45 0f db c1 pand %xmm9,%xmm8 + 435e77: 66 45 0f db d3 pand %xmm11,%xmm10 + 435e7c: 66 44 0f db c7 pand %xmm7,%xmm8 + 435e81: 66 44 0f db d7 pand %xmm7,%xmm10 + 435e86: 66 41 0f eb c8 por %xmm8,%xmm1 + 435e8b: 66 41 0f eb d2 por %xmm10,%xmm2 + 435e90: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 435e94: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 435e98: 66 0f f8 c8 psubb %xmm0,%xmm1 + 435e9c: 66 0f d7 d1 pmovmskb %xmm1,%edx + 435ea0: 81 ea ff ff 00 00 sub $0xffff,%edx + 435ea6: 0f 85 64 1e 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 435eac: 48 83 c1 10 add $0x10,%rcx + 435eb0: e9 1b ff ff ff jmpq 435dd0 <__strcasecmp_l_ssse3+0x1a0> + 435eb5: 90 nop + 435eb6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 435ebd: 00 00 00 + 435ec0: 66 0f ef c0 pxor %xmm0,%xmm0 + 435ec4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 435ec8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 435ecc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 435ed0: 66 0f 73 fa 0f pslldq $0xf,%xmm2 + 435ed5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 435eda: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 435edf: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 435ee4: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 435ee9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 435eee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 435ef3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 435ef8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 435efd: 66 45 0f db c1 pand %xmm9,%xmm8 + 435f02: 66 45 0f db d3 pand %xmm11,%xmm10 + 435f07: 66 44 0f db c7 pand %xmm7,%xmm8 + 435f0c: 66 44 0f db d7 pand %xmm7,%xmm10 + 435f11: 66 41 0f eb c8 por %xmm8,%xmm1 + 435f16: 66 41 0f eb d2 por %xmm10,%xmm2 + 435f1b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 435f1f: 66 0f f8 d0 psubb %xmm0,%xmm2 + 435f23: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 435f28: d3 ea shr %cl,%edx + 435f2a: 41 d3 e9 shr %cl,%r9d + 435f2d: 44 29 ca sub %r9d,%edx + 435f30: 0f 85 df 1d 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> + 435f36: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 435f3a: 66 0f ef c0 pxor %xmm0,%xmm0 + 435f3e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 435f45: 41 b9 01 00 00 00 mov $0x1,%r9d + 435f4b: 4c 8d 57 01 lea 0x1(%rdi),%r10 + 435f4f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 435f56: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 435f5d: 0f 1f 00 nopl (%rax) + 435f60: 49 83 c2 10 add $0x10,%r10 + 435f64: 0f 8f 16 01 00 00 jg 436080 <__strcasecmp_l_ssse3+0x450> + 435f6a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 435f6f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 435f74: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 435f78: 66 0f 3a 0f d3 01 palignr $0x1,%xmm3,%xmm2 + 435f7e: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 435f83: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 435f88: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 435f8d: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 435f92: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 435f97: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 435f9c: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 435fa1: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 435fa6: 66 45 0f db c1 pand %xmm9,%xmm8 + 435fab: 66 45 0f db d3 pand %xmm11,%xmm10 + 435fb0: 66 44 0f db c7 pand %xmm7,%xmm8 + 435fb5: 66 44 0f db d7 pand %xmm7,%xmm10 + 435fba: 66 41 0f eb c8 por %xmm8,%xmm1 + 435fbf: 66 41 0f eb d2 por %xmm10,%xmm2 + 435fc4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 435fc8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 435fcc: 66 0f f8 c8 psubb %xmm0,%xmm1 + 435fd0: 66 0f d7 d1 pmovmskb %xmm1,%edx + 435fd4: 81 ea ff ff 00 00 sub $0xffff,%edx + 435fda: 0f 85 30 1d 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 435fe0: 48 83 c1 10 add $0x10,%rcx + 435fe4: 66 0f 6f dc movdqa %xmm4,%xmm3 + 435fe8: 49 83 c2 10 add $0x10,%r10 + 435fec: 0f 8f 8e 00 00 00 jg 436080 <__strcasecmp_l_ssse3+0x450> + 435ff2: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 435ff7: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 435ffc: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 436000: 66 0f 3a 0f d3 01 palignr $0x1,%xmm3,%xmm2 + 436006: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 43600b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 436010: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 436015: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 43601a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 43601f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 436024: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 436029: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 43602e: 66 45 0f db c1 pand %xmm9,%xmm8 + 436033: 66 45 0f db d3 pand %xmm11,%xmm10 + 436038: 66 44 0f db c7 pand %xmm7,%xmm8 + 43603d: 66 44 0f db d7 pand %xmm7,%xmm10 + 436042: 66 41 0f eb c8 por %xmm8,%xmm1 + 436047: 66 41 0f eb d2 por %xmm10,%xmm2 + 43604c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 436050: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 436054: 66 0f f8 c8 psubb %xmm0,%xmm1 + 436058: 66 0f d7 d1 pmovmskb %xmm1,%edx + 43605c: 81 ea ff ff 00 00 sub $0xffff,%edx + 436062: 0f 85 a8 1c 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 436068: 48 83 c1 10 add $0x10,%rcx + 43606c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 436070: e9 eb fe ff ff jmpq 435f60 <__strcasecmp_l_ssse3+0x330> + 436075: 90 nop + 436076: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43607d: 00 00 00 + 436080: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 436084: 66 0f d7 d0 pmovmskb %xmm0,%edx + 436088: f7 c2 fe ff 00 00 test $0xfffe,%edx + 43608e: 75 10 jne 4360a0 <__strcasecmp_l_ssse3+0x470> + 436090: 66 0f ef c0 pxor %xmm0,%xmm0 + 436094: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 43609b: e9 ca fe ff ff jmpq 435f6a <__strcasecmp_l_ssse3+0x33a> + 4360a0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4360a5: 66 0f 73 d8 01 psrldq $0x1,%xmm0 + 4360aa: 66 0f 73 db 01 psrldq $0x1,%xmm3 + 4360af: e9 fc 1b 00 00 jmpq 437cb0 <__strcasecmp_l_ssse3+0x2080> + 4360b4: 66 90 xchg %ax,%ax + 4360b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4360bd: 00 00 00 + 4360c0: 66 0f ef c0 pxor %xmm0,%xmm0 + 4360c4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 4360c8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 4360cc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4360d0: 66 0f 73 fa 0e pslldq $0xe,%xmm2 + 4360d5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 4360da: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 4360df: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 4360e4: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 4360e9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 4360ee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 4360f3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 4360f8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 4360fd: 66 45 0f db c1 pand %xmm9,%xmm8 + 436102: 66 45 0f db d3 pand %xmm11,%xmm10 + 436107: 66 44 0f db c7 pand %xmm7,%xmm8 + 43610c: 66 44 0f db d7 pand %xmm7,%xmm10 + 436111: 66 41 0f eb c8 por %xmm8,%xmm1 + 436116: 66 41 0f eb d2 por %xmm10,%xmm2 + 43611b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 43611f: 66 0f f8 d0 psubb %xmm0,%xmm2 + 436123: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 436128: d3 ea shr %cl,%edx + 43612a: 41 d3 e9 shr %cl,%r9d + 43612d: 44 29 ca sub %r9d,%edx + 436130: 0f 85 df 1b 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> + 436136: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 43613a: 66 0f ef c0 pxor %xmm0,%xmm0 + 43613e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 436145: 41 b9 02 00 00 00 mov $0x2,%r9d + 43614b: 4c 8d 57 02 lea 0x2(%rdi),%r10 + 43614f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 436156: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 43615d: 0f 1f 00 nopl (%rax) + 436160: 49 83 c2 10 add $0x10,%r10 + 436164: 0f 8f 16 01 00 00 jg 436280 <__strcasecmp_l_ssse3+0x650> + 43616a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 43616f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 436174: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 436178: 66 0f 3a 0f d3 02 palignr $0x2,%xmm3,%xmm2 + 43617e: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 436183: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 436188: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 43618d: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 436192: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 436197: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 43619c: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 4361a1: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 4361a6: 66 45 0f db c1 pand %xmm9,%xmm8 + 4361ab: 66 45 0f db d3 pand %xmm11,%xmm10 + 4361b0: 66 44 0f db c7 pand %xmm7,%xmm8 + 4361b5: 66 44 0f db d7 pand %xmm7,%xmm10 + 4361ba: 66 41 0f eb c8 por %xmm8,%xmm1 + 4361bf: 66 41 0f eb d2 por %xmm10,%xmm2 + 4361c4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4361c8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 4361cc: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4361d0: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4361d4: 81 ea ff ff 00 00 sub $0xffff,%edx + 4361da: 0f 85 30 1b 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 4361e0: 48 83 c1 10 add $0x10,%rcx + 4361e4: 66 0f 6f dc movdqa %xmm4,%xmm3 + 4361e8: 49 83 c2 10 add $0x10,%r10 + 4361ec: 0f 8f 8e 00 00 00 jg 436280 <__strcasecmp_l_ssse3+0x650> + 4361f2: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4361f7: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4361fc: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 436200: 66 0f 3a 0f d3 02 palignr $0x2,%xmm3,%xmm2 + 436206: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 43620b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 436210: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 436215: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 43621a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 43621f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 436224: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 436229: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 43622e: 66 45 0f db c1 pand %xmm9,%xmm8 + 436233: 66 45 0f db d3 pand %xmm11,%xmm10 + 436238: 66 44 0f db c7 pand %xmm7,%xmm8 + 43623d: 66 44 0f db d7 pand %xmm7,%xmm10 + 436242: 66 41 0f eb c8 por %xmm8,%xmm1 + 436247: 66 41 0f eb d2 por %xmm10,%xmm2 + 43624c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 436250: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 436254: 66 0f f8 c8 psubb %xmm0,%xmm1 + 436258: 66 0f d7 d1 pmovmskb %xmm1,%edx + 43625c: 81 ea ff ff 00 00 sub $0xffff,%edx + 436262: 0f 85 a8 1a 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 436268: 48 83 c1 10 add $0x10,%rcx + 43626c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 436270: e9 eb fe ff ff jmpq 436160 <__strcasecmp_l_ssse3+0x530> + 436275: 90 nop + 436276: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43627d: 00 00 00 + 436280: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 436284: 66 0f d7 d0 pmovmskb %xmm0,%edx + 436288: f7 c2 fc ff 00 00 test $0xfffc,%edx + 43628e: 75 10 jne 4362a0 <__strcasecmp_l_ssse3+0x670> + 436290: 66 0f ef c0 pxor %xmm0,%xmm0 + 436294: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 43629b: e9 ca fe ff ff jmpq 43616a <__strcasecmp_l_ssse3+0x53a> + 4362a0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4362a5: 66 0f 73 d8 02 psrldq $0x2,%xmm0 + 4362aa: 66 0f 73 db 02 psrldq $0x2,%xmm3 + 4362af: e9 fc 19 00 00 jmpq 437cb0 <__strcasecmp_l_ssse3+0x2080> + 4362b4: 66 90 xchg %ax,%ax + 4362b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4362bd: 00 00 00 + 4362c0: 66 0f ef c0 pxor %xmm0,%xmm0 + 4362c4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 4362c8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 4362cc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4362d0: 66 0f 73 fa 0d pslldq $0xd,%xmm2 + 4362d5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 4362da: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 4362df: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 4362e4: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 4362e9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 4362ee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 4362f3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 4362f8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 4362fd: 66 45 0f db c1 pand %xmm9,%xmm8 + 436302: 66 45 0f db d3 pand %xmm11,%xmm10 + 436307: 66 44 0f db c7 pand %xmm7,%xmm8 + 43630c: 66 44 0f db d7 pand %xmm7,%xmm10 + 436311: 66 41 0f eb c8 por %xmm8,%xmm1 + 436316: 66 41 0f eb d2 por %xmm10,%xmm2 + 43631b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 43631f: 66 0f f8 d0 psubb %xmm0,%xmm2 + 436323: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 436328: d3 ea shr %cl,%edx + 43632a: 41 d3 e9 shr %cl,%r9d + 43632d: 44 29 ca sub %r9d,%edx + 436330: 0f 85 df 19 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> + 436336: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 43633a: 66 0f ef c0 pxor %xmm0,%xmm0 + 43633e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 436345: 41 b9 03 00 00 00 mov $0x3,%r9d + 43634b: 4c 8d 57 03 lea 0x3(%rdi),%r10 + 43634f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 436356: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 43635d: 0f 1f 00 nopl (%rax) + 436360: 49 83 c2 10 add $0x10,%r10 + 436364: 0f 8f 16 01 00 00 jg 436480 <__strcasecmp_l_ssse3+0x850> + 43636a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 43636f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 436374: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 436378: 66 0f 3a 0f d3 03 palignr $0x3,%xmm3,%xmm2 + 43637e: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 436383: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 436388: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 43638d: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 436392: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 436397: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 43639c: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 4363a1: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 4363a6: 66 45 0f db c1 pand %xmm9,%xmm8 + 4363ab: 66 45 0f db d3 pand %xmm11,%xmm10 + 4363b0: 66 44 0f db c7 pand %xmm7,%xmm8 + 4363b5: 66 44 0f db d7 pand %xmm7,%xmm10 + 4363ba: 66 41 0f eb c8 por %xmm8,%xmm1 + 4363bf: 66 41 0f eb d2 por %xmm10,%xmm2 + 4363c4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4363c8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 4363cc: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4363d0: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4363d4: 81 ea ff ff 00 00 sub $0xffff,%edx + 4363da: 0f 85 30 19 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 4363e0: 48 83 c1 10 add $0x10,%rcx + 4363e4: 66 0f 6f dc movdqa %xmm4,%xmm3 + 4363e8: 49 83 c2 10 add $0x10,%r10 + 4363ec: 0f 8f 8e 00 00 00 jg 436480 <__strcasecmp_l_ssse3+0x850> + 4363f2: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4363f7: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4363fc: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 436400: 66 0f 3a 0f d3 03 palignr $0x3,%xmm3,%xmm2 + 436406: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 43640b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 436410: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 436415: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 43641a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 43641f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 436424: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 436429: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 43642e: 66 45 0f db c1 pand %xmm9,%xmm8 + 436433: 66 45 0f db d3 pand %xmm11,%xmm10 + 436438: 66 44 0f db c7 pand %xmm7,%xmm8 + 43643d: 66 44 0f db d7 pand %xmm7,%xmm10 + 436442: 66 41 0f eb c8 por %xmm8,%xmm1 + 436447: 66 41 0f eb d2 por %xmm10,%xmm2 + 43644c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 436450: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 436454: 66 0f f8 c8 psubb %xmm0,%xmm1 + 436458: 66 0f d7 d1 pmovmskb %xmm1,%edx + 43645c: 81 ea ff ff 00 00 sub $0xffff,%edx + 436462: 0f 85 a8 18 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 436468: 48 83 c1 10 add $0x10,%rcx + 43646c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 436470: e9 eb fe ff ff jmpq 436360 <__strcasecmp_l_ssse3+0x730> + 436475: 90 nop + 436476: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43647d: 00 00 00 + 436480: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 436484: 66 0f d7 d0 pmovmskb %xmm0,%edx + 436488: f7 c2 f8 ff 00 00 test $0xfff8,%edx + 43648e: 75 10 jne 4364a0 <__strcasecmp_l_ssse3+0x870> + 436490: 66 0f ef c0 pxor %xmm0,%xmm0 + 436494: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 43649b: e9 ca fe ff ff jmpq 43636a <__strcasecmp_l_ssse3+0x73a> + 4364a0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4364a5: 66 0f 73 d8 03 psrldq $0x3,%xmm0 + 4364aa: 66 0f 73 db 03 psrldq $0x3,%xmm3 + 4364af: e9 fc 17 00 00 jmpq 437cb0 <__strcasecmp_l_ssse3+0x2080> + 4364b4: 66 90 xchg %ax,%ax + 4364b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4364bd: 00 00 00 + 4364c0: 66 0f ef c0 pxor %xmm0,%xmm0 + 4364c4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 4364c8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 4364cc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4364d0: 66 0f 73 fa 0c pslldq $0xc,%xmm2 + 4364d5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 4364da: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 4364df: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 4364e4: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 4364e9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 4364ee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 4364f3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 4364f8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 4364fd: 66 45 0f db c1 pand %xmm9,%xmm8 + 436502: 66 45 0f db d3 pand %xmm11,%xmm10 + 436507: 66 44 0f db c7 pand %xmm7,%xmm8 + 43650c: 66 44 0f db d7 pand %xmm7,%xmm10 + 436511: 66 41 0f eb c8 por %xmm8,%xmm1 + 436516: 66 41 0f eb d2 por %xmm10,%xmm2 + 43651b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 43651f: 66 0f f8 d0 psubb %xmm0,%xmm2 + 436523: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 436528: d3 ea shr %cl,%edx + 43652a: 41 d3 e9 shr %cl,%r9d + 43652d: 44 29 ca sub %r9d,%edx + 436530: 0f 85 df 17 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> + 436536: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 43653a: 66 0f ef c0 pxor %xmm0,%xmm0 + 43653e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 436545: 41 b9 04 00 00 00 mov $0x4,%r9d + 43654b: 4c 8d 57 04 lea 0x4(%rdi),%r10 + 43654f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 436556: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 43655d: 0f 1f 00 nopl (%rax) + 436560: 49 83 c2 10 add $0x10,%r10 + 436564: 0f 8f 16 01 00 00 jg 436680 <__strcasecmp_l_ssse3+0xa50> + 43656a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 43656f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 436574: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 436578: 66 0f 3a 0f d3 04 palignr $0x4,%xmm3,%xmm2 + 43657e: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 436583: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 436588: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 43658d: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 436592: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 436597: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 43659c: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 4365a1: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 4365a6: 66 45 0f db c1 pand %xmm9,%xmm8 + 4365ab: 66 45 0f db d3 pand %xmm11,%xmm10 + 4365b0: 66 44 0f db c7 pand %xmm7,%xmm8 + 4365b5: 66 44 0f db d7 pand %xmm7,%xmm10 + 4365ba: 66 41 0f eb c8 por %xmm8,%xmm1 + 4365bf: 66 41 0f eb d2 por %xmm10,%xmm2 + 4365c4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4365c8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 4365cc: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4365d0: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4365d4: 81 ea ff ff 00 00 sub $0xffff,%edx + 4365da: 0f 85 30 17 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 4365e0: 48 83 c1 10 add $0x10,%rcx + 4365e4: 66 0f 6f dc movdqa %xmm4,%xmm3 + 4365e8: 49 83 c2 10 add $0x10,%r10 + 4365ec: 0f 8f 8e 00 00 00 jg 436680 <__strcasecmp_l_ssse3+0xa50> + 4365f2: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4365f7: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4365fc: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 436600: 66 0f 3a 0f d3 04 palignr $0x4,%xmm3,%xmm2 + 436606: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 43660b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 436610: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 436615: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 43661a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 43661f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 436624: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 436629: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 43662e: 66 45 0f db c1 pand %xmm9,%xmm8 + 436633: 66 45 0f db d3 pand %xmm11,%xmm10 + 436638: 66 44 0f db c7 pand %xmm7,%xmm8 + 43663d: 66 44 0f db d7 pand %xmm7,%xmm10 + 436642: 66 41 0f eb c8 por %xmm8,%xmm1 + 436647: 66 41 0f eb d2 por %xmm10,%xmm2 + 43664c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 436650: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 436654: 66 0f f8 c8 psubb %xmm0,%xmm1 + 436658: 66 0f d7 d1 pmovmskb %xmm1,%edx + 43665c: 81 ea ff ff 00 00 sub $0xffff,%edx + 436662: 0f 85 a8 16 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 436668: 48 83 c1 10 add $0x10,%rcx + 43666c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 436670: e9 eb fe ff ff jmpq 436560 <__strcasecmp_l_ssse3+0x930> + 436675: 90 nop + 436676: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43667d: 00 00 00 + 436680: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 436684: 66 0f d7 d0 pmovmskb %xmm0,%edx + 436688: f7 c2 f0 ff 00 00 test $0xfff0,%edx + 43668e: 75 10 jne 4366a0 <__strcasecmp_l_ssse3+0xa70> + 436690: 66 0f ef c0 pxor %xmm0,%xmm0 + 436694: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 43669b: e9 ca fe ff ff jmpq 43656a <__strcasecmp_l_ssse3+0x93a> + 4366a0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4366a5: 66 0f 73 d8 04 psrldq $0x4,%xmm0 + 4366aa: 66 0f 73 db 04 psrldq $0x4,%xmm3 + 4366af: e9 fc 15 00 00 jmpq 437cb0 <__strcasecmp_l_ssse3+0x2080> + 4366b4: 66 90 xchg %ax,%ax + 4366b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4366bd: 00 00 00 + 4366c0: 66 0f ef c0 pxor %xmm0,%xmm0 + 4366c4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 4366c8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 4366cc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4366d0: 66 0f 73 fa 0b pslldq $0xb,%xmm2 + 4366d5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 4366da: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 4366df: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 4366e4: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 4366e9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 4366ee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 4366f3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 4366f8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 4366fd: 66 45 0f db c1 pand %xmm9,%xmm8 + 436702: 66 45 0f db d3 pand %xmm11,%xmm10 + 436707: 66 44 0f db c7 pand %xmm7,%xmm8 + 43670c: 66 44 0f db d7 pand %xmm7,%xmm10 + 436711: 66 41 0f eb c8 por %xmm8,%xmm1 + 436716: 66 41 0f eb d2 por %xmm10,%xmm2 + 43671b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 43671f: 66 0f f8 d0 psubb %xmm0,%xmm2 + 436723: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 436728: d3 ea shr %cl,%edx + 43672a: 41 d3 e9 shr %cl,%r9d + 43672d: 44 29 ca sub %r9d,%edx + 436730: 0f 85 df 15 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> + 436736: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 43673a: 66 0f ef c0 pxor %xmm0,%xmm0 + 43673e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 436745: 41 b9 05 00 00 00 mov $0x5,%r9d + 43674b: 4c 8d 57 05 lea 0x5(%rdi),%r10 + 43674f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 436756: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 43675d: 0f 1f 00 nopl (%rax) + 436760: 49 83 c2 10 add $0x10,%r10 + 436764: 0f 8f 16 01 00 00 jg 436880 <__strcasecmp_l_ssse3+0xc50> + 43676a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 43676f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 436774: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 436778: 66 0f 3a 0f d3 05 palignr $0x5,%xmm3,%xmm2 + 43677e: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 436783: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 436788: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 43678d: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 436792: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 436797: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 43679c: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 4367a1: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 4367a6: 66 45 0f db c1 pand %xmm9,%xmm8 + 4367ab: 66 45 0f db d3 pand %xmm11,%xmm10 + 4367b0: 66 44 0f db c7 pand %xmm7,%xmm8 + 4367b5: 66 44 0f db d7 pand %xmm7,%xmm10 + 4367ba: 66 41 0f eb c8 por %xmm8,%xmm1 + 4367bf: 66 41 0f eb d2 por %xmm10,%xmm2 + 4367c4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4367c8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 4367cc: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4367d0: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4367d4: 81 ea ff ff 00 00 sub $0xffff,%edx + 4367da: 0f 85 30 15 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 4367e0: 48 83 c1 10 add $0x10,%rcx + 4367e4: 66 0f 6f dc movdqa %xmm4,%xmm3 + 4367e8: 49 83 c2 10 add $0x10,%r10 + 4367ec: 0f 8f 8e 00 00 00 jg 436880 <__strcasecmp_l_ssse3+0xc50> + 4367f2: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4367f7: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4367fc: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 436800: 66 0f 3a 0f d3 05 palignr $0x5,%xmm3,%xmm2 + 436806: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 43680b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 436810: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 436815: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 43681a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 43681f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 436824: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 436829: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 43682e: 66 45 0f db c1 pand %xmm9,%xmm8 + 436833: 66 45 0f db d3 pand %xmm11,%xmm10 + 436838: 66 44 0f db c7 pand %xmm7,%xmm8 + 43683d: 66 44 0f db d7 pand %xmm7,%xmm10 + 436842: 66 41 0f eb c8 por %xmm8,%xmm1 + 436847: 66 41 0f eb d2 por %xmm10,%xmm2 + 43684c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 436850: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 436854: 66 0f f8 c8 psubb %xmm0,%xmm1 + 436858: 66 0f d7 d1 pmovmskb %xmm1,%edx + 43685c: 81 ea ff ff 00 00 sub $0xffff,%edx + 436862: 0f 85 a8 14 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 436868: 48 83 c1 10 add $0x10,%rcx + 43686c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 436870: e9 eb fe ff ff jmpq 436760 <__strcasecmp_l_ssse3+0xb30> + 436875: 90 nop + 436876: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43687d: 00 00 00 + 436880: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 436884: 66 0f d7 d0 pmovmskb %xmm0,%edx + 436888: f7 c2 e0 ff 00 00 test $0xffe0,%edx + 43688e: 75 10 jne 4368a0 <__strcasecmp_l_ssse3+0xc70> + 436890: 66 0f ef c0 pxor %xmm0,%xmm0 + 436894: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 43689b: e9 ca fe ff ff jmpq 43676a <__strcasecmp_l_ssse3+0xb3a> + 4368a0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4368a5: 66 0f 73 d8 05 psrldq $0x5,%xmm0 + 4368aa: 66 0f 73 db 05 psrldq $0x5,%xmm3 + 4368af: e9 fc 13 00 00 jmpq 437cb0 <__strcasecmp_l_ssse3+0x2080> + 4368b4: 66 90 xchg %ax,%ax + 4368b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4368bd: 00 00 00 + 4368c0: 66 0f ef c0 pxor %xmm0,%xmm0 + 4368c4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 4368c8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 4368cc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4368d0: 66 0f 73 fa 0a pslldq $0xa,%xmm2 + 4368d5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 4368da: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 4368df: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 4368e4: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 4368e9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 4368ee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 4368f3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 4368f8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 4368fd: 66 45 0f db c1 pand %xmm9,%xmm8 + 436902: 66 45 0f db d3 pand %xmm11,%xmm10 + 436907: 66 44 0f db c7 pand %xmm7,%xmm8 + 43690c: 66 44 0f db d7 pand %xmm7,%xmm10 + 436911: 66 41 0f eb c8 por %xmm8,%xmm1 + 436916: 66 41 0f eb d2 por %xmm10,%xmm2 + 43691b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 43691f: 66 0f f8 d0 psubb %xmm0,%xmm2 + 436923: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 436928: d3 ea shr %cl,%edx + 43692a: 41 d3 e9 shr %cl,%r9d + 43692d: 44 29 ca sub %r9d,%edx + 436930: 0f 85 df 13 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> + 436936: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 43693a: 66 0f ef c0 pxor %xmm0,%xmm0 + 43693e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 436945: 41 b9 06 00 00 00 mov $0x6,%r9d + 43694b: 4c 8d 57 06 lea 0x6(%rdi),%r10 + 43694f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 436956: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 43695d: 0f 1f 00 nopl (%rax) + 436960: 49 83 c2 10 add $0x10,%r10 + 436964: 0f 8f 16 01 00 00 jg 436a80 <__strcasecmp_l_ssse3+0xe50> + 43696a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 43696f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 436974: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 436978: 66 0f 3a 0f d3 06 palignr $0x6,%xmm3,%xmm2 + 43697e: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 436983: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 436988: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 43698d: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 436992: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 436997: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 43699c: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 4369a1: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 4369a6: 66 45 0f db c1 pand %xmm9,%xmm8 + 4369ab: 66 45 0f db d3 pand %xmm11,%xmm10 + 4369b0: 66 44 0f db c7 pand %xmm7,%xmm8 + 4369b5: 66 44 0f db d7 pand %xmm7,%xmm10 + 4369ba: 66 41 0f eb c8 por %xmm8,%xmm1 + 4369bf: 66 41 0f eb d2 por %xmm10,%xmm2 + 4369c4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4369c8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 4369cc: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4369d0: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4369d4: 81 ea ff ff 00 00 sub $0xffff,%edx + 4369da: 0f 85 30 13 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 4369e0: 48 83 c1 10 add $0x10,%rcx + 4369e4: 66 0f 6f dc movdqa %xmm4,%xmm3 + 4369e8: 49 83 c2 10 add $0x10,%r10 + 4369ec: 0f 8f 8e 00 00 00 jg 436a80 <__strcasecmp_l_ssse3+0xe50> + 4369f2: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4369f7: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4369fc: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 436a00: 66 0f 3a 0f d3 06 palignr $0x6,%xmm3,%xmm2 + 436a06: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 436a0b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 436a10: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 436a15: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 436a1a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 436a1f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 436a24: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 436a29: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 436a2e: 66 45 0f db c1 pand %xmm9,%xmm8 + 436a33: 66 45 0f db d3 pand %xmm11,%xmm10 + 436a38: 66 44 0f db c7 pand %xmm7,%xmm8 + 436a3d: 66 44 0f db d7 pand %xmm7,%xmm10 + 436a42: 66 41 0f eb c8 por %xmm8,%xmm1 + 436a47: 66 41 0f eb d2 por %xmm10,%xmm2 + 436a4c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 436a50: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 436a54: 66 0f f8 c8 psubb %xmm0,%xmm1 + 436a58: 66 0f d7 d1 pmovmskb %xmm1,%edx + 436a5c: 81 ea ff ff 00 00 sub $0xffff,%edx + 436a62: 0f 85 a8 12 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 436a68: 48 83 c1 10 add $0x10,%rcx + 436a6c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 436a70: e9 eb fe ff ff jmpq 436960 <__strcasecmp_l_ssse3+0xd30> + 436a75: 90 nop + 436a76: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 436a7d: 00 00 00 + 436a80: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 436a84: 66 0f d7 d0 pmovmskb %xmm0,%edx + 436a88: f7 c2 c0 ff 00 00 test $0xffc0,%edx + 436a8e: 75 10 jne 436aa0 <__strcasecmp_l_ssse3+0xe70> + 436a90: 66 0f ef c0 pxor %xmm0,%xmm0 + 436a94: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 436a9b: e9 ca fe ff ff jmpq 43696a <__strcasecmp_l_ssse3+0xd3a> + 436aa0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 436aa5: 66 0f 73 d8 06 psrldq $0x6,%xmm0 + 436aaa: 66 0f 73 db 06 psrldq $0x6,%xmm3 + 436aaf: e9 fc 11 00 00 jmpq 437cb0 <__strcasecmp_l_ssse3+0x2080> + 436ab4: 66 90 xchg %ax,%ax + 436ab6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 436abd: 00 00 00 + 436ac0: 66 0f ef c0 pxor %xmm0,%xmm0 + 436ac4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 436ac8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 436acc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 436ad0: 66 0f 73 fa 09 pslldq $0x9,%xmm2 + 436ad5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 436ada: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 436adf: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 436ae4: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 436ae9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 436aee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 436af3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 436af8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 436afd: 66 45 0f db c1 pand %xmm9,%xmm8 + 436b02: 66 45 0f db d3 pand %xmm11,%xmm10 + 436b07: 66 44 0f db c7 pand %xmm7,%xmm8 + 436b0c: 66 44 0f db d7 pand %xmm7,%xmm10 + 436b11: 66 41 0f eb c8 por %xmm8,%xmm1 + 436b16: 66 41 0f eb d2 por %xmm10,%xmm2 + 436b1b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 436b1f: 66 0f f8 d0 psubb %xmm0,%xmm2 + 436b23: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 436b28: d3 ea shr %cl,%edx + 436b2a: 41 d3 e9 shr %cl,%r9d + 436b2d: 44 29 ca sub %r9d,%edx + 436b30: 0f 85 df 11 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> + 436b36: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 436b3a: 66 0f ef c0 pxor %xmm0,%xmm0 + 436b3e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 436b45: 41 b9 07 00 00 00 mov $0x7,%r9d + 436b4b: 4c 8d 57 07 lea 0x7(%rdi),%r10 + 436b4f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 436b56: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 436b5d: 0f 1f 00 nopl (%rax) + 436b60: 49 83 c2 10 add $0x10,%r10 + 436b64: 0f 8f 16 01 00 00 jg 436c80 <__strcasecmp_l_ssse3+0x1050> + 436b6a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 436b6f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 436b74: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 436b78: 66 0f 3a 0f d3 07 palignr $0x7,%xmm3,%xmm2 + 436b7e: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 436b83: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 436b88: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 436b8d: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 436b92: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 436b97: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 436b9c: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 436ba1: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 436ba6: 66 45 0f db c1 pand %xmm9,%xmm8 + 436bab: 66 45 0f db d3 pand %xmm11,%xmm10 + 436bb0: 66 44 0f db c7 pand %xmm7,%xmm8 + 436bb5: 66 44 0f db d7 pand %xmm7,%xmm10 + 436bba: 66 41 0f eb c8 por %xmm8,%xmm1 + 436bbf: 66 41 0f eb d2 por %xmm10,%xmm2 + 436bc4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 436bc8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 436bcc: 66 0f f8 c8 psubb %xmm0,%xmm1 + 436bd0: 66 0f d7 d1 pmovmskb %xmm1,%edx + 436bd4: 81 ea ff ff 00 00 sub $0xffff,%edx + 436bda: 0f 85 30 11 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 436be0: 48 83 c1 10 add $0x10,%rcx + 436be4: 66 0f 6f dc movdqa %xmm4,%xmm3 + 436be8: 49 83 c2 10 add $0x10,%r10 + 436bec: 0f 8f 8e 00 00 00 jg 436c80 <__strcasecmp_l_ssse3+0x1050> + 436bf2: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 436bf7: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 436bfc: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 436c00: 66 0f 3a 0f d3 07 palignr $0x7,%xmm3,%xmm2 + 436c06: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 436c0b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 436c10: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 436c15: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 436c1a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 436c1f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 436c24: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 436c29: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 436c2e: 66 45 0f db c1 pand %xmm9,%xmm8 + 436c33: 66 45 0f db d3 pand %xmm11,%xmm10 + 436c38: 66 44 0f db c7 pand %xmm7,%xmm8 + 436c3d: 66 44 0f db d7 pand %xmm7,%xmm10 + 436c42: 66 41 0f eb c8 por %xmm8,%xmm1 + 436c47: 66 41 0f eb d2 por %xmm10,%xmm2 + 436c4c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 436c50: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 436c54: 66 0f f8 c8 psubb %xmm0,%xmm1 + 436c58: 66 0f d7 d1 pmovmskb %xmm1,%edx + 436c5c: 81 ea ff ff 00 00 sub $0xffff,%edx + 436c62: 0f 85 a8 10 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 436c68: 48 83 c1 10 add $0x10,%rcx + 436c6c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 436c70: e9 eb fe ff ff jmpq 436b60 <__strcasecmp_l_ssse3+0xf30> + 436c75: 90 nop + 436c76: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 436c7d: 00 00 00 + 436c80: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 436c84: 66 0f d7 d0 pmovmskb %xmm0,%edx + 436c88: f7 c2 80 ff 00 00 test $0xff80,%edx + 436c8e: 75 10 jne 436ca0 <__strcasecmp_l_ssse3+0x1070> + 436c90: 66 0f ef c0 pxor %xmm0,%xmm0 + 436c94: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 436c9b: e9 ca fe ff ff jmpq 436b6a <__strcasecmp_l_ssse3+0xf3a> + 436ca0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 436ca5: 66 0f 73 d8 07 psrldq $0x7,%xmm0 + 436caa: 66 0f 73 db 07 psrldq $0x7,%xmm3 + 436caf: e9 fc 0f 00 00 jmpq 437cb0 <__strcasecmp_l_ssse3+0x2080> + 436cb4: 66 90 xchg %ax,%ax + 436cb6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 436cbd: 00 00 00 + 436cc0: 66 0f ef c0 pxor %xmm0,%xmm0 + 436cc4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 436cc8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 436ccc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 436cd0: 66 0f 73 fa 08 pslldq $0x8,%xmm2 + 436cd5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 436cda: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 436cdf: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 436ce4: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 436ce9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 436cee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 436cf3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 436cf8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 436cfd: 66 45 0f db c1 pand %xmm9,%xmm8 + 436d02: 66 45 0f db d3 pand %xmm11,%xmm10 + 436d07: 66 44 0f db c7 pand %xmm7,%xmm8 + 436d0c: 66 44 0f db d7 pand %xmm7,%xmm10 + 436d11: 66 41 0f eb c8 por %xmm8,%xmm1 + 436d16: 66 41 0f eb d2 por %xmm10,%xmm2 + 436d1b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 436d1f: 66 0f f8 d0 psubb %xmm0,%xmm2 + 436d23: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 436d28: d3 ea shr %cl,%edx + 436d2a: 41 d3 e9 shr %cl,%r9d + 436d2d: 44 29 ca sub %r9d,%edx + 436d30: 0f 85 df 0f 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> + 436d36: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 436d3a: 66 0f ef c0 pxor %xmm0,%xmm0 + 436d3e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 436d45: 41 b9 08 00 00 00 mov $0x8,%r9d + 436d4b: 4c 8d 57 08 lea 0x8(%rdi),%r10 + 436d4f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 436d56: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 436d5d: 0f 1f 00 nopl (%rax) + 436d60: 49 83 c2 10 add $0x10,%r10 + 436d64: 0f 8f 16 01 00 00 jg 436e80 <__strcasecmp_l_ssse3+0x1250> + 436d6a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 436d6f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 436d74: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 436d78: 66 0f 3a 0f d3 08 palignr $0x8,%xmm3,%xmm2 + 436d7e: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 436d83: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 436d88: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 436d8d: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 436d92: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 436d97: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 436d9c: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 436da1: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 436da6: 66 45 0f db c1 pand %xmm9,%xmm8 + 436dab: 66 45 0f db d3 pand %xmm11,%xmm10 + 436db0: 66 44 0f db c7 pand %xmm7,%xmm8 + 436db5: 66 44 0f db d7 pand %xmm7,%xmm10 + 436dba: 66 41 0f eb c8 por %xmm8,%xmm1 + 436dbf: 66 41 0f eb d2 por %xmm10,%xmm2 + 436dc4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 436dc8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 436dcc: 66 0f f8 c8 psubb %xmm0,%xmm1 + 436dd0: 66 0f d7 d1 pmovmskb %xmm1,%edx + 436dd4: 81 ea ff ff 00 00 sub $0xffff,%edx + 436dda: 0f 85 30 0f 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 436de0: 48 83 c1 10 add $0x10,%rcx + 436de4: 66 0f 6f dc movdqa %xmm4,%xmm3 + 436de8: 49 83 c2 10 add $0x10,%r10 + 436dec: 0f 8f 8e 00 00 00 jg 436e80 <__strcasecmp_l_ssse3+0x1250> + 436df2: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 436df7: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 436dfc: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 436e00: 66 0f 3a 0f d3 08 palignr $0x8,%xmm3,%xmm2 + 436e06: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 436e0b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 436e10: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 436e15: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 436e1a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 436e1f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 436e24: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 436e29: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 436e2e: 66 45 0f db c1 pand %xmm9,%xmm8 + 436e33: 66 45 0f db d3 pand %xmm11,%xmm10 + 436e38: 66 44 0f db c7 pand %xmm7,%xmm8 + 436e3d: 66 44 0f db d7 pand %xmm7,%xmm10 + 436e42: 66 41 0f eb c8 por %xmm8,%xmm1 + 436e47: 66 41 0f eb d2 por %xmm10,%xmm2 + 436e4c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 436e50: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 436e54: 66 0f f8 c8 psubb %xmm0,%xmm1 + 436e58: 66 0f d7 d1 pmovmskb %xmm1,%edx + 436e5c: 81 ea ff ff 00 00 sub $0xffff,%edx + 436e62: 0f 85 a8 0e 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 436e68: 48 83 c1 10 add $0x10,%rcx + 436e6c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 436e70: e9 eb fe ff ff jmpq 436d60 <__strcasecmp_l_ssse3+0x1130> + 436e75: 90 nop + 436e76: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 436e7d: 00 00 00 + 436e80: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 436e84: 66 0f d7 d0 pmovmskb %xmm0,%edx + 436e88: f7 c2 00 ff 00 00 test $0xff00,%edx + 436e8e: 75 10 jne 436ea0 <__strcasecmp_l_ssse3+0x1270> + 436e90: 66 0f ef c0 pxor %xmm0,%xmm0 + 436e94: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 436e9b: e9 ca fe ff ff jmpq 436d6a <__strcasecmp_l_ssse3+0x113a> + 436ea0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 436ea5: 66 0f 73 d8 08 psrldq $0x8,%xmm0 + 436eaa: 66 0f 73 db 08 psrldq $0x8,%xmm3 + 436eaf: e9 fc 0d 00 00 jmpq 437cb0 <__strcasecmp_l_ssse3+0x2080> + 436eb4: 66 90 xchg %ax,%ax + 436eb6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 436ebd: 00 00 00 + 436ec0: 66 0f ef c0 pxor %xmm0,%xmm0 + 436ec4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 436ec8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 436ecc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 436ed0: 66 0f 73 fa 07 pslldq $0x7,%xmm2 + 436ed5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 436eda: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 436edf: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 436ee4: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 436ee9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 436eee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 436ef3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 436ef8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 436efd: 66 45 0f db c1 pand %xmm9,%xmm8 + 436f02: 66 45 0f db d3 pand %xmm11,%xmm10 + 436f07: 66 44 0f db c7 pand %xmm7,%xmm8 + 436f0c: 66 44 0f db d7 pand %xmm7,%xmm10 + 436f11: 66 41 0f eb c8 por %xmm8,%xmm1 + 436f16: 66 41 0f eb d2 por %xmm10,%xmm2 + 436f1b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 436f1f: 66 0f f8 d0 psubb %xmm0,%xmm2 + 436f23: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 436f28: d3 ea shr %cl,%edx + 436f2a: 41 d3 e9 shr %cl,%r9d + 436f2d: 44 29 ca sub %r9d,%edx + 436f30: 0f 85 df 0d 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> + 436f36: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 436f3a: 66 0f ef c0 pxor %xmm0,%xmm0 + 436f3e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 436f45: 41 b9 09 00 00 00 mov $0x9,%r9d + 436f4b: 4c 8d 57 09 lea 0x9(%rdi),%r10 + 436f4f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 436f56: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 436f5d: 0f 1f 00 nopl (%rax) + 436f60: 49 83 c2 10 add $0x10,%r10 + 436f64: 0f 8f 16 01 00 00 jg 437080 <__strcasecmp_l_ssse3+0x1450> + 436f6a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 436f6f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 436f74: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 436f78: 66 0f 3a 0f d3 09 palignr $0x9,%xmm3,%xmm2 + 436f7e: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 436f83: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 436f88: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 436f8d: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 436f92: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 436f97: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 436f9c: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 436fa1: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 436fa6: 66 45 0f db c1 pand %xmm9,%xmm8 + 436fab: 66 45 0f db d3 pand %xmm11,%xmm10 + 436fb0: 66 44 0f db c7 pand %xmm7,%xmm8 + 436fb5: 66 44 0f db d7 pand %xmm7,%xmm10 + 436fba: 66 41 0f eb c8 por %xmm8,%xmm1 + 436fbf: 66 41 0f eb d2 por %xmm10,%xmm2 + 436fc4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 436fc8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 436fcc: 66 0f f8 c8 psubb %xmm0,%xmm1 + 436fd0: 66 0f d7 d1 pmovmskb %xmm1,%edx + 436fd4: 81 ea ff ff 00 00 sub $0xffff,%edx + 436fda: 0f 85 30 0d 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 436fe0: 48 83 c1 10 add $0x10,%rcx + 436fe4: 66 0f 6f dc movdqa %xmm4,%xmm3 + 436fe8: 49 83 c2 10 add $0x10,%r10 + 436fec: 0f 8f 8e 00 00 00 jg 437080 <__strcasecmp_l_ssse3+0x1450> + 436ff2: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 436ff7: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 436ffc: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 437000: 66 0f 3a 0f d3 09 palignr $0x9,%xmm3,%xmm2 + 437006: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 43700b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 437010: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 437015: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 43701a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 43701f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 437024: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 437029: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 43702e: 66 45 0f db c1 pand %xmm9,%xmm8 + 437033: 66 45 0f db d3 pand %xmm11,%xmm10 + 437038: 66 44 0f db c7 pand %xmm7,%xmm8 + 43703d: 66 44 0f db d7 pand %xmm7,%xmm10 + 437042: 66 41 0f eb c8 por %xmm8,%xmm1 + 437047: 66 41 0f eb d2 por %xmm10,%xmm2 + 43704c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 437050: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 437054: 66 0f f8 c8 psubb %xmm0,%xmm1 + 437058: 66 0f d7 d1 pmovmskb %xmm1,%edx + 43705c: 81 ea ff ff 00 00 sub $0xffff,%edx + 437062: 0f 85 a8 0c 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 437068: 48 83 c1 10 add $0x10,%rcx + 43706c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 437070: e9 eb fe ff ff jmpq 436f60 <__strcasecmp_l_ssse3+0x1330> + 437075: 90 nop + 437076: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43707d: 00 00 00 + 437080: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 437084: 66 0f d7 d0 pmovmskb %xmm0,%edx + 437088: f7 c2 00 fe 00 00 test $0xfe00,%edx + 43708e: 75 10 jne 4370a0 <__strcasecmp_l_ssse3+0x1470> + 437090: 66 0f ef c0 pxor %xmm0,%xmm0 + 437094: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 43709b: e9 ca fe ff ff jmpq 436f6a <__strcasecmp_l_ssse3+0x133a> + 4370a0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4370a5: 66 0f 73 d8 09 psrldq $0x9,%xmm0 + 4370aa: 66 0f 73 db 09 psrldq $0x9,%xmm3 + 4370af: e9 fc 0b 00 00 jmpq 437cb0 <__strcasecmp_l_ssse3+0x2080> + 4370b4: 66 90 xchg %ax,%ax + 4370b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4370bd: 00 00 00 + 4370c0: 66 0f ef c0 pxor %xmm0,%xmm0 + 4370c4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 4370c8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 4370cc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4370d0: 66 0f 73 fa 06 pslldq $0x6,%xmm2 + 4370d5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 4370da: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 4370df: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 4370e4: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 4370e9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 4370ee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 4370f3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 4370f8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 4370fd: 66 45 0f db c1 pand %xmm9,%xmm8 + 437102: 66 45 0f db d3 pand %xmm11,%xmm10 + 437107: 66 44 0f db c7 pand %xmm7,%xmm8 + 43710c: 66 44 0f db d7 pand %xmm7,%xmm10 + 437111: 66 41 0f eb c8 por %xmm8,%xmm1 + 437116: 66 41 0f eb d2 por %xmm10,%xmm2 + 43711b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 43711f: 66 0f f8 d0 psubb %xmm0,%xmm2 + 437123: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 437128: d3 ea shr %cl,%edx + 43712a: 41 d3 e9 shr %cl,%r9d + 43712d: 44 29 ca sub %r9d,%edx + 437130: 0f 85 df 0b 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> + 437136: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 43713a: 66 0f ef c0 pxor %xmm0,%xmm0 + 43713e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 437145: 41 b9 0a 00 00 00 mov $0xa,%r9d + 43714b: 4c 8d 57 0a lea 0xa(%rdi),%r10 + 43714f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 437156: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 43715d: 0f 1f 00 nopl (%rax) + 437160: 49 83 c2 10 add $0x10,%r10 + 437164: 0f 8f 16 01 00 00 jg 437280 <__strcasecmp_l_ssse3+0x1650> + 43716a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 43716f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 437174: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 437178: 66 0f 3a 0f d3 0a palignr $0xa,%xmm3,%xmm2 + 43717e: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 437183: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 437188: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 43718d: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 437192: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 437197: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 43719c: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 4371a1: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 4371a6: 66 45 0f db c1 pand %xmm9,%xmm8 + 4371ab: 66 45 0f db d3 pand %xmm11,%xmm10 + 4371b0: 66 44 0f db c7 pand %xmm7,%xmm8 + 4371b5: 66 44 0f db d7 pand %xmm7,%xmm10 + 4371ba: 66 41 0f eb c8 por %xmm8,%xmm1 + 4371bf: 66 41 0f eb d2 por %xmm10,%xmm2 + 4371c4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4371c8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 4371cc: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4371d0: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4371d4: 81 ea ff ff 00 00 sub $0xffff,%edx + 4371da: 0f 85 30 0b 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 4371e0: 48 83 c1 10 add $0x10,%rcx + 4371e4: 66 0f 6f dc movdqa %xmm4,%xmm3 + 4371e8: 49 83 c2 10 add $0x10,%r10 + 4371ec: 0f 8f 8e 00 00 00 jg 437280 <__strcasecmp_l_ssse3+0x1650> + 4371f2: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4371f7: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4371fc: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 437200: 66 0f 3a 0f d3 0a palignr $0xa,%xmm3,%xmm2 + 437206: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 43720b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 437210: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 437215: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 43721a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 43721f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 437224: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 437229: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 43722e: 66 45 0f db c1 pand %xmm9,%xmm8 + 437233: 66 45 0f db d3 pand %xmm11,%xmm10 + 437238: 66 44 0f db c7 pand %xmm7,%xmm8 + 43723d: 66 44 0f db d7 pand %xmm7,%xmm10 + 437242: 66 41 0f eb c8 por %xmm8,%xmm1 + 437247: 66 41 0f eb d2 por %xmm10,%xmm2 + 43724c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 437250: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 437254: 66 0f f8 c8 psubb %xmm0,%xmm1 + 437258: 66 0f d7 d1 pmovmskb %xmm1,%edx + 43725c: 81 ea ff ff 00 00 sub $0xffff,%edx + 437262: 0f 85 a8 0a 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 437268: 48 83 c1 10 add $0x10,%rcx + 43726c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 437270: e9 eb fe ff ff jmpq 437160 <__strcasecmp_l_ssse3+0x1530> + 437275: 90 nop + 437276: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43727d: 00 00 00 + 437280: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 437284: 66 0f d7 d0 pmovmskb %xmm0,%edx + 437288: f7 c2 00 fc 00 00 test $0xfc00,%edx + 43728e: 75 10 jne 4372a0 <__strcasecmp_l_ssse3+0x1670> + 437290: 66 0f ef c0 pxor %xmm0,%xmm0 + 437294: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 43729b: e9 ca fe ff ff jmpq 43716a <__strcasecmp_l_ssse3+0x153a> + 4372a0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4372a5: 66 0f 73 d8 0a psrldq $0xa,%xmm0 + 4372aa: 66 0f 73 db 0a psrldq $0xa,%xmm3 + 4372af: e9 fc 09 00 00 jmpq 437cb0 <__strcasecmp_l_ssse3+0x2080> + 4372b4: 66 90 xchg %ax,%ax + 4372b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4372bd: 00 00 00 + 4372c0: 66 0f ef c0 pxor %xmm0,%xmm0 + 4372c4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 4372c8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 4372cc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4372d0: 66 0f 73 fa 05 pslldq $0x5,%xmm2 + 4372d5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 4372da: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 4372df: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 4372e4: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 4372e9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 4372ee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 4372f3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 4372f8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 4372fd: 66 45 0f db c1 pand %xmm9,%xmm8 + 437302: 66 45 0f db d3 pand %xmm11,%xmm10 + 437307: 66 44 0f db c7 pand %xmm7,%xmm8 + 43730c: 66 44 0f db d7 pand %xmm7,%xmm10 + 437311: 66 41 0f eb c8 por %xmm8,%xmm1 + 437316: 66 41 0f eb d2 por %xmm10,%xmm2 + 43731b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 43731f: 66 0f f8 d0 psubb %xmm0,%xmm2 + 437323: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 437328: d3 ea shr %cl,%edx + 43732a: 41 d3 e9 shr %cl,%r9d + 43732d: 44 29 ca sub %r9d,%edx + 437330: 0f 85 df 09 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> + 437336: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 43733a: 66 0f ef c0 pxor %xmm0,%xmm0 + 43733e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 437345: 41 b9 0b 00 00 00 mov $0xb,%r9d + 43734b: 4c 8d 57 0b lea 0xb(%rdi),%r10 + 43734f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 437356: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 43735d: 0f 1f 00 nopl (%rax) + 437360: 49 83 c2 10 add $0x10,%r10 + 437364: 0f 8f 16 01 00 00 jg 437480 <__strcasecmp_l_ssse3+0x1850> + 43736a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 43736f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 437374: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 437378: 66 0f 3a 0f d3 0b palignr $0xb,%xmm3,%xmm2 + 43737e: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 437383: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 437388: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 43738d: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 437392: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 437397: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 43739c: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 4373a1: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 4373a6: 66 45 0f db c1 pand %xmm9,%xmm8 + 4373ab: 66 45 0f db d3 pand %xmm11,%xmm10 + 4373b0: 66 44 0f db c7 pand %xmm7,%xmm8 + 4373b5: 66 44 0f db d7 pand %xmm7,%xmm10 + 4373ba: 66 41 0f eb c8 por %xmm8,%xmm1 + 4373bf: 66 41 0f eb d2 por %xmm10,%xmm2 + 4373c4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4373c8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 4373cc: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4373d0: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4373d4: 81 ea ff ff 00 00 sub $0xffff,%edx + 4373da: 0f 85 30 09 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 4373e0: 48 83 c1 10 add $0x10,%rcx + 4373e4: 66 0f 6f dc movdqa %xmm4,%xmm3 + 4373e8: 49 83 c2 10 add $0x10,%r10 + 4373ec: 0f 8f 8e 00 00 00 jg 437480 <__strcasecmp_l_ssse3+0x1850> + 4373f2: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4373f7: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4373fc: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 437400: 66 0f 3a 0f d3 0b palignr $0xb,%xmm3,%xmm2 + 437406: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 43740b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 437410: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 437415: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 43741a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 43741f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 437424: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 437429: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 43742e: 66 45 0f db c1 pand %xmm9,%xmm8 + 437433: 66 45 0f db d3 pand %xmm11,%xmm10 + 437438: 66 44 0f db c7 pand %xmm7,%xmm8 + 43743d: 66 44 0f db d7 pand %xmm7,%xmm10 + 437442: 66 41 0f eb c8 por %xmm8,%xmm1 + 437447: 66 41 0f eb d2 por %xmm10,%xmm2 + 43744c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 437450: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 437454: 66 0f f8 c8 psubb %xmm0,%xmm1 + 437458: 66 0f d7 d1 pmovmskb %xmm1,%edx + 43745c: 81 ea ff ff 00 00 sub $0xffff,%edx + 437462: 0f 85 a8 08 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 437468: 48 83 c1 10 add $0x10,%rcx + 43746c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 437470: e9 eb fe ff ff jmpq 437360 <__strcasecmp_l_ssse3+0x1730> + 437475: 90 nop + 437476: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43747d: 00 00 00 + 437480: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 437484: 66 0f d7 d0 pmovmskb %xmm0,%edx + 437488: f7 c2 00 f8 00 00 test $0xf800,%edx + 43748e: 75 10 jne 4374a0 <__strcasecmp_l_ssse3+0x1870> + 437490: 66 0f ef c0 pxor %xmm0,%xmm0 + 437494: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 43749b: e9 ca fe ff ff jmpq 43736a <__strcasecmp_l_ssse3+0x173a> + 4374a0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4374a5: 66 0f 73 d8 0b psrldq $0xb,%xmm0 + 4374aa: 66 0f 73 db 0b psrldq $0xb,%xmm3 + 4374af: e9 fc 07 00 00 jmpq 437cb0 <__strcasecmp_l_ssse3+0x2080> + 4374b4: 66 90 xchg %ax,%ax + 4374b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4374bd: 00 00 00 + 4374c0: 66 0f ef c0 pxor %xmm0,%xmm0 + 4374c4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 4374c8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 4374cc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4374d0: 66 0f 73 fa 04 pslldq $0x4,%xmm2 + 4374d5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 4374da: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 4374df: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 4374e4: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 4374e9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 4374ee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 4374f3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 4374f8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 4374fd: 66 45 0f db c1 pand %xmm9,%xmm8 + 437502: 66 45 0f db d3 pand %xmm11,%xmm10 + 437507: 66 44 0f db c7 pand %xmm7,%xmm8 + 43750c: 66 44 0f db d7 pand %xmm7,%xmm10 + 437511: 66 41 0f eb c8 por %xmm8,%xmm1 + 437516: 66 41 0f eb d2 por %xmm10,%xmm2 + 43751b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 43751f: 66 0f f8 d0 psubb %xmm0,%xmm2 + 437523: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 437528: d3 ea shr %cl,%edx + 43752a: 41 d3 e9 shr %cl,%r9d + 43752d: 44 29 ca sub %r9d,%edx + 437530: 0f 85 df 07 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> + 437536: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 43753a: 66 0f ef c0 pxor %xmm0,%xmm0 + 43753e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 437545: 41 b9 0c 00 00 00 mov $0xc,%r9d + 43754b: 4c 8d 57 0c lea 0xc(%rdi),%r10 + 43754f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 437556: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 43755d: 0f 1f 00 nopl (%rax) + 437560: 49 83 c2 10 add $0x10,%r10 + 437564: 0f 8f 16 01 00 00 jg 437680 <__strcasecmp_l_ssse3+0x1a50> + 43756a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 43756f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 437574: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 437578: 66 0f 3a 0f d3 0c palignr $0xc,%xmm3,%xmm2 + 43757e: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 437583: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 437588: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 43758d: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 437592: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 437597: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 43759c: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 4375a1: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 4375a6: 66 45 0f db c1 pand %xmm9,%xmm8 + 4375ab: 66 45 0f db d3 pand %xmm11,%xmm10 + 4375b0: 66 44 0f db c7 pand %xmm7,%xmm8 + 4375b5: 66 44 0f db d7 pand %xmm7,%xmm10 + 4375ba: 66 41 0f eb c8 por %xmm8,%xmm1 + 4375bf: 66 41 0f eb d2 por %xmm10,%xmm2 + 4375c4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4375c8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 4375cc: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4375d0: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4375d4: 81 ea ff ff 00 00 sub $0xffff,%edx + 4375da: 0f 85 30 07 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 4375e0: 48 83 c1 10 add $0x10,%rcx + 4375e4: 66 0f 6f dc movdqa %xmm4,%xmm3 + 4375e8: 49 83 c2 10 add $0x10,%r10 + 4375ec: 0f 8f 8e 00 00 00 jg 437680 <__strcasecmp_l_ssse3+0x1a50> + 4375f2: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4375f7: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4375fc: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 437600: 66 0f 3a 0f d3 0c palignr $0xc,%xmm3,%xmm2 + 437606: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 43760b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 437610: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 437615: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 43761a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 43761f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 437624: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 437629: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 43762e: 66 45 0f db c1 pand %xmm9,%xmm8 + 437633: 66 45 0f db d3 pand %xmm11,%xmm10 + 437638: 66 44 0f db c7 pand %xmm7,%xmm8 + 43763d: 66 44 0f db d7 pand %xmm7,%xmm10 + 437642: 66 41 0f eb c8 por %xmm8,%xmm1 + 437647: 66 41 0f eb d2 por %xmm10,%xmm2 + 43764c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 437650: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 437654: 66 0f f8 c8 psubb %xmm0,%xmm1 + 437658: 66 0f d7 d1 pmovmskb %xmm1,%edx + 43765c: 81 ea ff ff 00 00 sub $0xffff,%edx + 437662: 0f 85 a8 06 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 437668: 48 83 c1 10 add $0x10,%rcx + 43766c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 437670: e9 eb fe ff ff jmpq 437560 <__strcasecmp_l_ssse3+0x1930> + 437675: 90 nop + 437676: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43767d: 00 00 00 + 437680: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 437684: 66 0f d7 d0 pmovmskb %xmm0,%edx + 437688: f7 c2 00 f0 00 00 test $0xf000,%edx + 43768e: 75 10 jne 4376a0 <__strcasecmp_l_ssse3+0x1a70> + 437690: 66 0f ef c0 pxor %xmm0,%xmm0 + 437694: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 43769b: e9 ca fe ff ff jmpq 43756a <__strcasecmp_l_ssse3+0x193a> + 4376a0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4376a5: 66 0f 73 d8 0c psrldq $0xc,%xmm0 + 4376aa: 66 0f 73 db 0c psrldq $0xc,%xmm3 + 4376af: e9 fc 05 00 00 jmpq 437cb0 <__strcasecmp_l_ssse3+0x2080> + 4376b4: 66 90 xchg %ax,%ax + 4376b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4376bd: 00 00 00 + 4376c0: 66 0f ef c0 pxor %xmm0,%xmm0 + 4376c4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 4376c8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 4376cc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4376d0: 66 0f 73 fa 03 pslldq $0x3,%xmm2 + 4376d5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 4376da: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 4376df: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 4376e4: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 4376e9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 4376ee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 4376f3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 4376f8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 4376fd: 66 45 0f db c1 pand %xmm9,%xmm8 + 437702: 66 45 0f db d3 pand %xmm11,%xmm10 + 437707: 66 44 0f db c7 pand %xmm7,%xmm8 + 43770c: 66 44 0f db d7 pand %xmm7,%xmm10 + 437711: 66 41 0f eb c8 por %xmm8,%xmm1 + 437716: 66 41 0f eb d2 por %xmm10,%xmm2 + 43771b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 43771f: 66 0f f8 d0 psubb %xmm0,%xmm2 + 437723: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 437728: d3 ea shr %cl,%edx + 43772a: 41 d3 e9 shr %cl,%r9d + 43772d: 44 29 ca sub %r9d,%edx + 437730: 0f 85 df 05 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> + 437736: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 43773a: 66 0f ef c0 pxor %xmm0,%xmm0 + 43773e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 437745: 41 b9 0d 00 00 00 mov $0xd,%r9d + 43774b: 4c 8d 57 0d lea 0xd(%rdi),%r10 + 43774f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 437756: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 43775d: 0f 1f 00 nopl (%rax) + 437760: 49 83 c2 10 add $0x10,%r10 + 437764: 0f 8f 16 01 00 00 jg 437880 <__strcasecmp_l_ssse3+0x1c50> + 43776a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 43776f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 437774: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 437778: 66 0f 3a 0f d3 0d palignr $0xd,%xmm3,%xmm2 + 43777e: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 437783: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 437788: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 43778d: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 437792: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 437797: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 43779c: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 4377a1: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 4377a6: 66 45 0f db c1 pand %xmm9,%xmm8 + 4377ab: 66 45 0f db d3 pand %xmm11,%xmm10 + 4377b0: 66 44 0f db c7 pand %xmm7,%xmm8 + 4377b5: 66 44 0f db d7 pand %xmm7,%xmm10 + 4377ba: 66 41 0f eb c8 por %xmm8,%xmm1 + 4377bf: 66 41 0f eb d2 por %xmm10,%xmm2 + 4377c4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4377c8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 4377cc: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4377d0: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4377d4: 81 ea ff ff 00 00 sub $0xffff,%edx + 4377da: 0f 85 30 05 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 4377e0: 48 83 c1 10 add $0x10,%rcx + 4377e4: 66 0f 6f dc movdqa %xmm4,%xmm3 + 4377e8: 49 83 c2 10 add $0x10,%r10 + 4377ec: 0f 8f 8e 00 00 00 jg 437880 <__strcasecmp_l_ssse3+0x1c50> + 4377f2: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4377f7: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4377fc: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 437800: 66 0f 3a 0f d3 0d palignr $0xd,%xmm3,%xmm2 + 437806: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 43780b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 437810: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 437815: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 43781a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 43781f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 437824: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 437829: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 43782e: 66 45 0f db c1 pand %xmm9,%xmm8 + 437833: 66 45 0f db d3 pand %xmm11,%xmm10 + 437838: 66 44 0f db c7 pand %xmm7,%xmm8 + 43783d: 66 44 0f db d7 pand %xmm7,%xmm10 + 437842: 66 41 0f eb c8 por %xmm8,%xmm1 + 437847: 66 41 0f eb d2 por %xmm10,%xmm2 + 43784c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 437850: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 437854: 66 0f f8 c8 psubb %xmm0,%xmm1 + 437858: 66 0f d7 d1 pmovmskb %xmm1,%edx + 43785c: 81 ea ff ff 00 00 sub $0xffff,%edx + 437862: 0f 85 a8 04 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 437868: 48 83 c1 10 add $0x10,%rcx + 43786c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 437870: e9 eb fe ff ff jmpq 437760 <__strcasecmp_l_ssse3+0x1b30> + 437875: 90 nop + 437876: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43787d: 00 00 00 + 437880: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 437884: 66 0f d7 d0 pmovmskb %xmm0,%edx + 437888: f7 c2 00 e0 00 00 test $0xe000,%edx + 43788e: 75 10 jne 4378a0 <__strcasecmp_l_ssse3+0x1c70> + 437890: 66 0f ef c0 pxor %xmm0,%xmm0 + 437894: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 43789b: e9 ca fe ff ff jmpq 43776a <__strcasecmp_l_ssse3+0x1b3a> + 4378a0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4378a5: 66 0f 73 d8 0d psrldq $0xd,%xmm0 + 4378aa: 66 0f 73 db 0d psrldq $0xd,%xmm3 + 4378af: e9 fc 03 00 00 jmpq 437cb0 <__strcasecmp_l_ssse3+0x2080> + 4378b4: 66 90 xchg %ax,%ax + 4378b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4378bd: 00 00 00 + 4378c0: 66 0f ef c0 pxor %xmm0,%xmm0 + 4378c4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 4378c8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 4378cc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4378d0: 66 0f 73 fa 02 pslldq $0x2,%xmm2 + 4378d5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 4378da: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 4378df: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 4378e4: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 4378e9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 4378ee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 4378f3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 4378f8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 4378fd: 66 45 0f db c1 pand %xmm9,%xmm8 + 437902: 66 45 0f db d3 pand %xmm11,%xmm10 + 437907: 66 44 0f db c7 pand %xmm7,%xmm8 + 43790c: 66 44 0f db d7 pand %xmm7,%xmm10 + 437911: 66 41 0f eb c8 por %xmm8,%xmm1 + 437916: 66 41 0f eb d2 por %xmm10,%xmm2 + 43791b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 43791f: 66 0f f8 d0 psubb %xmm0,%xmm2 + 437923: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 437928: d3 ea shr %cl,%edx + 43792a: 41 d3 e9 shr %cl,%r9d + 43792d: 44 29 ca sub %r9d,%edx + 437930: 0f 85 df 03 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> + 437936: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 43793a: 66 0f ef c0 pxor %xmm0,%xmm0 + 43793e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 437945: 41 b9 0e 00 00 00 mov $0xe,%r9d + 43794b: 4c 8d 57 0e lea 0xe(%rdi),%r10 + 43794f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 437956: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 43795d: 0f 1f 00 nopl (%rax) + 437960: 49 83 c2 10 add $0x10,%r10 + 437964: 0f 8f 16 01 00 00 jg 437a80 <__strcasecmp_l_ssse3+0x1e50> + 43796a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 43796f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 437974: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 437978: 66 0f 3a 0f d3 0e palignr $0xe,%xmm3,%xmm2 + 43797e: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 437983: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 437988: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 43798d: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 437992: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 437997: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 43799c: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 4379a1: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 4379a6: 66 45 0f db c1 pand %xmm9,%xmm8 + 4379ab: 66 45 0f db d3 pand %xmm11,%xmm10 + 4379b0: 66 44 0f db c7 pand %xmm7,%xmm8 + 4379b5: 66 44 0f db d7 pand %xmm7,%xmm10 + 4379ba: 66 41 0f eb c8 por %xmm8,%xmm1 + 4379bf: 66 41 0f eb d2 por %xmm10,%xmm2 + 4379c4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 4379c8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 4379cc: 66 0f f8 c8 psubb %xmm0,%xmm1 + 4379d0: 66 0f d7 d1 pmovmskb %xmm1,%edx + 4379d4: 81 ea ff ff 00 00 sub $0xffff,%edx + 4379da: 0f 85 30 03 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 4379e0: 48 83 c1 10 add $0x10,%rcx + 4379e4: 66 0f 6f dc movdqa %xmm4,%xmm3 + 4379e8: 49 83 c2 10 add $0x10,%r10 + 4379ec: 0f 8f 8e 00 00 00 jg 437a80 <__strcasecmp_l_ssse3+0x1e50> + 4379f2: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 4379f7: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 4379fc: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 437a00: 66 0f 3a 0f d3 0e palignr $0xe,%xmm3,%xmm2 + 437a06: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 437a0b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 437a10: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 437a15: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 437a1a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 437a1f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 437a24: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 437a29: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 437a2e: 66 45 0f db c1 pand %xmm9,%xmm8 + 437a33: 66 45 0f db d3 pand %xmm11,%xmm10 + 437a38: 66 44 0f db c7 pand %xmm7,%xmm8 + 437a3d: 66 44 0f db d7 pand %xmm7,%xmm10 + 437a42: 66 41 0f eb c8 por %xmm8,%xmm1 + 437a47: 66 41 0f eb d2 por %xmm10,%xmm2 + 437a4c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 437a50: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 437a54: 66 0f f8 c8 psubb %xmm0,%xmm1 + 437a58: 66 0f d7 d1 pmovmskb %xmm1,%edx + 437a5c: 81 ea ff ff 00 00 sub $0xffff,%edx + 437a62: 0f 85 a8 02 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 437a68: 48 83 c1 10 add $0x10,%rcx + 437a6c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 437a70: e9 eb fe ff ff jmpq 437960 <__strcasecmp_l_ssse3+0x1d30> + 437a75: 90 nop + 437a76: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 437a7d: 00 00 00 + 437a80: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 437a84: 66 0f d7 d0 pmovmskb %xmm0,%edx + 437a88: f7 c2 00 c0 00 00 test $0xc000,%edx + 437a8e: 75 10 jne 437aa0 <__strcasecmp_l_ssse3+0x1e70> + 437a90: 66 0f ef c0 pxor %xmm0,%xmm0 + 437a94: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 437a9b: e9 ca fe ff ff jmpq 43796a <__strcasecmp_l_ssse3+0x1d3a> + 437aa0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 437aa5: 66 0f 73 d8 0e psrldq $0xe,%xmm0 + 437aaa: 66 0f 73 db 0e psrldq $0xe,%xmm3 + 437aaf: e9 fc 01 00 00 jmpq 437cb0 <__strcasecmp_l_ssse3+0x2080> + 437ab4: 66 90 xchg %ax,%ax + 437ab6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 437abd: 00 00 00 + 437ac0: 66 0f ef c0 pxor %xmm0,%xmm0 + 437ac4: 66 0f 6f 17 movdqa (%rdi),%xmm2 + 437ac8: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 437acc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 437ad0: 66 0f 73 fa 01 pslldq $0x1,%xmm2 + 437ad5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 437ada: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 437adf: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 437ae4: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 437ae9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 437aee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 437af3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 437af8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 437afd: 66 45 0f db c1 pand %xmm9,%xmm8 + 437b02: 66 45 0f db d3 pand %xmm11,%xmm10 + 437b07: 66 44 0f db c7 pand %xmm7,%xmm8 + 437b0c: 66 44 0f db d7 pand %xmm7,%xmm10 + 437b11: 66 41 0f eb c8 por %xmm8,%xmm1 + 437b16: 66 41 0f eb d2 por %xmm10,%xmm2 + 437b1b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 + 437b1f: 66 0f f8 d0 psubb %xmm0,%xmm2 + 437b23: 66 44 0f d7 ca pmovmskb %xmm2,%r9d + 437b28: d3 ea shr %cl,%edx + 437b2a: 41 d3 e9 shr %cl,%r9d + 437b2d: 44 29 ca sub %r9d,%edx + 437b30: 0f 85 df 01 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> + 437b36: 66 0f 6f 1f movdqa (%rdi),%xmm3 + 437b3a: 66 0f ef c0 pxor %xmm0,%xmm0 + 437b3e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 437b45: 41 b9 0f 00 00 00 mov $0xf,%r9d + 437b4b: 4c 8d 57 0f lea 0xf(%rdi),%r10 + 437b4f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 + 437b56: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 437b5d: 0f 1f 00 nopl (%rax) + 437b60: 49 83 c2 10 add $0x10,%r10 + 437b64: 0f 8f 16 01 00 00 jg 437c80 <__strcasecmp_l_ssse3+0x2050> + 437b6a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 437b6f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 437b74: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 437b78: 66 0f 3a 0f d3 0f palignr $0xf,%xmm3,%xmm2 + 437b7e: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 437b83: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 437b88: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 437b8d: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 437b92: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 437b97: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 437b9c: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 437ba1: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 437ba6: 66 45 0f db c1 pand %xmm9,%xmm8 + 437bab: 66 45 0f db d3 pand %xmm11,%xmm10 + 437bb0: 66 44 0f db c7 pand %xmm7,%xmm8 + 437bb5: 66 44 0f db d7 pand %xmm7,%xmm10 + 437bba: 66 41 0f eb c8 por %xmm8,%xmm1 + 437bbf: 66 41 0f eb d2 por %xmm10,%xmm2 + 437bc4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 437bc8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 437bcc: 66 0f f8 c8 psubb %xmm0,%xmm1 + 437bd0: 66 0f d7 d1 pmovmskb %xmm1,%edx + 437bd4: 81 ea ff ff 00 00 sub $0xffff,%edx + 437bda: 0f 85 30 01 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 437be0: 48 83 c1 10 add $0x10,%rcx + 437be4: 66 0f 6f dc movdqa %xmm4,%xmm3 + 437be8: 49 83 c2 10 add $0x10,%r10 + 437bec: 0f 8f 8e 00 00 00 jg 437c80 <__strcasecmp_l_ssse3+0x2050> + 437bf2: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 437bf7: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 + 437bfc: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 437c00: 66 0f 3a 0f d3 0f palignr $0xf,%xmm3,%xmm2 + 437c06: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 437c0b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 437c10: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 + 437c15: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 437c1a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 437c1f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 437c24: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 437c29: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 + 437c2e: 66 45 0f db c1 pand %xmm9,%xmm8 + 437c33: 66 45 0f db d3 pand %xmm11,%xmm10 + 437c38: 66 44 0f db c7 pand %xmm7,%xmm8 + 437c3d: 66 44 0f db d7 pand %xmm7,%xmm10 + 437c42: 66 41 0f eb c8 por %xmm8,%xmm1 + 437c47: 66 41 0f eb d2 por %xmm10,%xmm2 + 437c4c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 437c50: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 + 437c54: 66 0f f8 c8 psubb %xmm0,%xmm1 + 437c58: 66 0f d7 d1 pmovmskb %xmm1,%edx + 437c5c: 81 ea ff ff 00 00 sub $0xffff,%edx + 437c62: 0f 85 a8 00 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> + 437c68: 48 83 c1 10 add $0x10,%rcx + 437c6c: 66 0f 6f dc movdqa %xmm4,%xmm3 + 437c70: e9 eb fe ff ff jmpq 437b60 <__strcasecmp_l_ssse3+0x1f30> + 437c75: 90 nop + 437c76: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 437c7d: 00 00 00 + 437c80: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 437c84: 66 0f d7 d0 pmovmskb %xmm0,%edx + 437c88: f7 c2 00 80 00 00 test $0x8000,%edx + 437c8e: 75 10 jne 437ca0 <__strcasecmp_l_ssse3+0x2070> + 437c90: 66 0f ef c0 pxor %xmm0,%xmm0 + 437c94: 49 81 ea 00 10 00 00 sub $0x1000,%r10 + 437c9b: e9 ca fe ff ff jmpq 437b6a <__strcasecmp_l_ssse3+0x1f3a> + 437ca0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 437ca5: 66 0f 73 db 0f psrldq $0xf,%xmm3 + 437caa: 66 0f 73 d8 0f psrldq $0xf,%xmm0 + 437caf: 90 nop + 437cb0: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 + 437cb5: 66 44 0f 6f ce movdqa %xmm6,%xmm9 + 437cba: 66 44 0f 6f d3 movdqa %xmm3,%xmm10 + 437cbf: 66 44 0f 6f de movdqa %xmm6,%xmm11 + 437cc4: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 + 437cc9: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 + 437cce: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 + 437cd3: 66 44 0f 64 db pcmpgtb %xmm3,%xmm11 + 437cd8: 66 45 0f db c1 pand %xmm9,%xmm8 + 437cdd: 66 45 0f db d3 pand %xmm11,%xmm10 + 437ce2: 66 44 0f db c7 pand %xmm7,%xmm8 + 437ce7: 66 44 0f db d7 pand %xmm7,%xmm10 + 437cec: 66 41 0f eb c8 por %xmm8,%xmm1 + 437cf1: 66 41 0f eb da por %xmm10,%xmm3 + 437cf6: 66 0f 74 cb pcmpeqb %xmm3,%xmm1 + 437cfa: 66 0f f8 c8 psubb %xmm0,%xmm1 + 437cfe: 66 0f d7 d1 pmovmskb %xmm1,%edx + 437d02: f7 d2 not %edx + 437d04: 66 90 xchg %ax,%ax + 437d06: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 437d0d: 00 00 00 + 437d10: 49 8d 44 09 f0 lea -0x10(%r9,%rcx,1),%rax + 437d15: 48 8d 3c 07 lea (%rdi,%rax,1),%rdi + 437d19: 48 8d 34 0e lea (%rsi,%rcx,1),%rsi + 437d1d: 45 85 c0 test %r8d,%r8d + 437d20: 74 0e je 437d30 <__strcasecmp_l_ssse3+0x2100> + 437d22: 48 87 f7 xchg %rsi,%rdi + 437d25: 90 nop + 437d26: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 437d2d: 00 00 00 + 437d30: 48 0f bc d2 bsf %rdx,%rdx + 437d34: 0f b6 0c 16 movzbl (%rsi,%rdx,1),%ecx + 437d38: 0f b6 04 17 movzbl (%rdi,%rdx,1),%eax + 437d3c: 48 8d 15 fd f7 06 00 lea 0x6f7fd(%rip),%rdx # 4a7540 <_nl_C_LC_CTYPE_tolower+0x200> + 437d43: 8b 0c 8a mov (%rdx,%rcx,4),%ecx + 437d46: 8b 04 82 mov (%rdx,%rax,4),%eax + 437d49: 29 c8 sub %ecx,%eax + 437d4b: c3 retq + 437d4c: 31 c0 xor %eax,%eax + 437d4e: c3 retq + 437d4f: 90 nop + 437d50: 0f b6 0e movzbl (%rsi),%ecx + 437d53: 0f b6 07 movzbl (%rdi),%eax + 437d56: 48 8d 15 e3 f7 06 00 lea 0x6f7e3(%rip),%rdx # 4a7540 <_nl_C_LC_CTYPE_tolower+0x200> + 437d5d: 8b 0c 8a mov (%rdx,%rcx,4),%ecx + 437d60: 8b 04 82 mov (%rdx,%rax,4),%eax + 437d63: 29 c8 sub %ecx,%eax + 437d65: c3 retq + 437d66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 437d6d: 00 00 00 + +0000000000437d70 <__strcpy_ssse3>: + 437d70: 48 89 f1 mov %rsi,%rcx + 437d73: 48 89 fa mov %rdi,%rdx + 437d76: 80 39 00 cmpb $0x0,(%rcx) + 437d79: 0f 84 91 16 00 00 je 439410 <__strcpy_ssse3+0x16a0> + 437d7f: 80 79 01 00 cmpb $0x0,0x1(%rcx) + 437d83: 0f 84 97 16 00 00 je 439420 <__strcpy_ssse3+0x16b0> + 437d89: 80 79 02 00 cmpb $0x0,0x2(%rcx) + 437d8d: 0f 84 9d 16 00 00 je 439430 <__strcpy_ssse3+0x16c0> + 437d93: 80 79 03 00 cmpb $0x0,0x3(%rcx) + 437d97: 0f 84 a3 16 00 00 je 439440 <__strcpy_ssse3+0x16d0> + 437d9d: 80 79 04 00 cmpb $0x0,0x4(%rcx) + 437da1: 0f 84 a9 16 00 00 je 439450 <__strcpy_ssse3+0x16e0> + 437da7: 80 79 05 00 cmpb $0x0,0x5(%rcx) + 437dab: 0f 84 af 16 00 00 je 439460 <__strcpy_ssse3+0x16f0> + 437db1: 80 79 06 00 cmpb $0x0,0x6(%rcx) + 437db5: 0f 84 b5 16 00 00 je 439470 <__strcpy_ssse3+0x1700> + 437dbb: 80 79 07 00 cmpb $0x0,0x7(%rcx) + 437dbf: 0f 84 db 15 00 00 je 4393a0 <__strcpy_ssse3+0x1630> + 437dc5: 80 79 08 00 cmpb $0x0,0x8(%rcx) + 437dc9: 0f 84 b1 16 00 00 je 439480 <__strcpy_ssse3+0x1710> + 437dcf: 80 79 09 00 cmpb $0x0,0x9(%rcx) + 437dd3: 0f 84 b7 16 00 00 je 439490 <__strcpy_ssse3+0x1720> + 437dd9: 80 79 0a 00 cmpb $0x0,0xa(%rcx) + 437ddd: 0f 84 bd 16 00 00 je 4394a0 <__strcpy_ssse3+0x1730> + 437de3: 80 79 0b 00 cmpb $0x0,0xb(%rcx) + 437de7: 0f 84 c3 16 00 00 je 4394b0 <__strcpy_ssse3+0x1740> + 437ded: 80 79 0c 00 cmpb $0x0,0xc(%rcx) + 437df1: 0f 84 c9 16 00 00 je 4394c0 <__strcpy_ssse3+0x1750> + 437df7: 80 79 0d 00 cmpb $0x0,0xd(%rcx) + 437dfb: 0f 84 df 16 00 00 je 4394e0 <__strcpy_ssse3+0x1770> + 437e01: 80 79 0e 00 cmpb $0x0,0xe(%rcx) + 437e05: 0f 84 f5 16 00 00 je 439500 <__strcpy_ssse3+0x1790> + 437e0b: 80 79 0f 00 cmpb $0x0,0xf(%rcx) + 437e0f: 0f 84 db 15 00 00 je 4393f0 <__strcpy_ssse3+0x1680> + 437e15: 48 8d 71 10 lea 0x10(%rcx),%rsi + 437e19: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi + 437e1d: 66 0f ef c0 pxor %xmm0,%xmm0 + 437e21: 4c 8b 09 mov (%rcx),%r9 + 437e24: 4c 89 0a mov %r9,(%rdx) + 437e27: 66 0f 74 06 pcmpeqb (%rsi),%xmm0 + 437e2b: 4c 8b 49 08 mov 0x8(%rcx),%r9 + 437e2f: 4c 89 4a 08 mov %r9,0x8(%rdx) + 437e33: 66 0f d7 c0 pmovmskb %xmm0,%eax + 437e37: 48 29 ce sub %rcx,%rsi + 437e3a: 48 85 c0 test %rax,%rax + 437e3d: 0f 85 0d 15 00 00 jne 439350 <__strcpy_ssse3+0x15e0> + 437e43: 48 89 d0 mov %rdx,%rax + 437e46: 48 8d 52 10 lea 0x10(%rdx),%rdx + 437e4a: 48 83 e2 f0 and $0xfffffffffffffff0,%rdx + 437e4e: 48 29 d0 sub %rdx,%rax + 437e51: 48 29 c1 sub %rax,%rcx + 437e54: 48 89 c8 mov %rcx,%rax + 437e57: 48 83 e0 0f and $0xf,%rax + 437e5b: 48 c7 c6 00 00 00 00 mov $0x0,%rsi + 437e62: 0f 84 8e 00 00 00 je 437ef6 <__strcpy_ssse3+0x186> + 437e68: 48 83 f8 08 cmp $0x8,%rax + 437e6c: 73 41 jae 437eaf <__strcpy_ssse3+0x13f> + 437e6e: 48 83 f8 01 cmp $0x1,%rax + 437e72: 0f 84 f8 01 00 00 je 438070 <__strcpy_ssse3+0x300> + 437e78: 48 83 f8 02 cmp $0x2,%rax + 437e7c: 0f 84 2e 03 00 00 je 4381b0 <__strcpy_ssse3+0x440> + 437e82: 48 83 f8 03 cmp $0x3,%rax + 437e86: 0f 84 64 04 00 00 je 4382f0 <__strcpy_ssse3+0x580> + 437e8c: 48 83 f8 04 cmp $0x4,%rax + 437e90: 0f 84 9a 05 00 00 je 438430 <__strcpy_ssse3+0x6c0> + 437e96: 48 83 f8 05 cmp $0x5,%rax + 437e9a: 0f 84 d0 06 00 00 je 438570 <__strcpy_ssse3+0x800> + 437ea0: 48 83 f8 06 cmp $0x6,%rax + 437ea4: 0f 84 06 08 00 00 je 4386b0 <__strcpy_ssse3+0x940> + 437eaa: e9 51 09 00 00 jmpq 438800 <__strcpy_ssse3+0xa90> + 437eaf: 0f 84 9b 0a 00 00 je 438950 <__strcpy_ssse3+0xbe0> + 437eb5: 48 83 f8 09 cmp $0x9,%rax + 437eb9: 0f 84 d1 0b 00 00 je 438a90 <__strcpy_ssse3+0xd20> + 437ebf: 48 83 f8 0a cmp $0xa,%rax + 437ec3: 0f 84 07 0d 00 00 je 438bd0 <__strcpy_ssse3+0xe60> + 437ec9: 48 83 f8 0b cmp $0xb,%rax + 437ecd: 0f 84 3d 0e 00 00 je 438d10 <__strcpy_ssse3+0xfa0> + 437ed3: 48 83 f8 0c cmp $0xc,%rax + 437ed7: 0f 84 73 0f 00 00 je 438e50 <__strcpy_ssse3+0x10e0> + 437edd: 48 83 f8 0d cmp $0xd,%rax + 437ee1: 0f 84 a9 10 00 00 je 438f90 <__strcpy_ssse3+0x1220> + 437ee7: 48 83 f8 0e cmp $0xe,%rax + 437eeb: 0f 84 df 11 00 00 je 4390d0 <__strcpy_ssse3+0x1360> + 437ef1: e9 1a 13 00 00 jmpq 439210 <__strcpy_ssse3+0x14a0> + 437ef6: 0f 28 09 movaps (%rcx),%xmm1 + 437ef9: 0f 28 51 10 movaps 0x10(%rcx),%xmm2 + 437efd: 0f 29 0a movaps %xmm1,(%rdx) + 437f00: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 437f04: 66 0f d7 c0 pmovmskb %xmm0,%eax + 437f08: 48 8d 76 10 lea 0x10(%rsi),%rsi + 437f0c: 48 85 c0 test %rax,%rax + 437f0f: 0f 85 3b 14 00 00 jne 439350 <__strcpy_ssse3+0x15e0> + 437f15: 0f 28 5c 31 10 movaps 0x10(%rcx,%rsi,1),%xmm3 + 437f1a: 0f 29 14 32 movaps %xmm2,(%rdx,%rsi,1) + 437f1e: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 437f22: 66 0f d7 c0 pmovmskb %xmm0,%eax + 437f26: 48 8d 76 10 lea 0x10(%rsi),%rsi + 437f2a: 48 85 c0 test %rax,%rax + 437f2d: 0f 85 1d 14 00 00 jne 439350 <__strcpy_ssse3+0x15e0> + 437f33: 0f 28 64 31 10 movaps 0x10(%rcx,%rsi,1),%xmm4 + 437f38: 0f 29 1c 32 movaps %xmm3,(%rdx,%rsi,1) + 437f3c: 66 0f 74 c4 pcmpeqb %xmm4,%xmm0 + 437f40: 66 0f d7 c0 pmovmskb %xmm0,%eax + 437f44: 48 8d 76 10 lea 0x10(%rsi),%rsi + 437f48: 48 85 c0 test %rax,%rax + 437f4b: 0f 85 ff 13 00 00 jne 439350 <__strcpy_ssse3+0x15e0> + 437f51: 0f 28 4c 31 10 movaps 0x10(%rcx,%rsi,1),%xmm1 + 437f56: 0f 29 24 32 movaps %xmm4,(%rdx,%rsi,1) + 437f5a: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 437f5e: 66 0f d7 c0 pmovmskb %xmm0,%eax + 437f62: 48 8d 76 10 lea 0x10(%rsi),%rsi + 437f66: 48 85 c0 test %rax,%rax + 437f69: 0f 85 e1 13 00 00 jne 439350 <__strcpy_ssse3+0x15e0> + 437f6f: 0f 28 54 31 10 movaps 0x10(%rcx,%rsi,1),%xmm2 + 437f74: 0f 29 0c 32 movaps %xmm1,(%rdx,%rsi,1) + 437f78: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 437f7c: 66 0f d7 c0 pmovmskb %xmm0,%eax + 437f80: 48 8d 76 10 lea 0x10(%rsi),%rsi + 437f84: 48 85 c0 test %rax,%rax + 437f87: 0f 85 c3 13 00 00 jne 439350 <__strcpy_ssse3+0x15e0> + 437f8d: 0f 28 5c 31 10 movaps 0x10(%rcx,%rsi,1),%xmm3 + 437f92: 0f 29 14 32 movaps %xmm2,(%rdx,%rsi,1) + 437f96: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 437f9a: 66 0f d7 c0 pmovmskb %xmm0,%eax + 437f9e: 48 8d 76 10 lea 0x10(%rsi),%rsi + 437fa2: 48 85 c0 test %rax,%rax + 437fa5: 0f 85 a5 13 00 00 jne 439350 <__strcpy_ssse3+0x15e0> + 437fab: 0f 29 1c 32 movaps %xmm3,(%rdx,%rsi,1) + 437faf: 48 89 c8 mov %rcx,%rax + 437fb2: 48 8d 4c 31 10 lea 0x10(%rcx,%rsi,1),%rcx + 437fb7: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 437fbb: 48 29 c8 sub %rcx,%rax + 437fbe: 48 29 c2 sub %rax,%rdx + 437fc1: 48 c7 c6 c0 ff ff ff mov $0xffffffffffffffc0,%rsi + 437fc8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 437fcf: 00 + 437fd0: 0f 28 11 movaps (%rcx),%xmm2 + 437fd3: 0f 28 e2 movaps %xmm2,%xmm4 + 437fd6: 0f 28 69 10 movaps 0x10(%rcx),%xmm5 + 437fda: 0f 28 59 20 movaps 0x20(%rcx),%xmm3 + 437fde: 0f 28 f3 movaps %xmm3,%xmm6 + 437fe1: 0f 28 79 30 movaps 0x30(%rcx),%xmm7 + 437fe5: 66 0f da d5 pminub %xmm5,%xmm2 + 437fe9: 66 0f da df pminub %xmm7,%xmm3 + 437fed: 66 0f da da pminub %xmm2,%xmm3 + 437ff1: 66 0f 74 d8 pcmpeqb %xmm0,%xmm3 + 437ff5: 66 0f d7 c3 pmovmskb %xmm3,%eax + 437ff9: 48 8d 52 40 lea 0x40(%rdx),%rdx + 437ffd: 48 8d 49 40 lea 0x40(%rcx),%rcx + 438001: 48 85 c0 test %rax,%rax + 438004: 75 12 jne 438018 <__strcpy_ssse3+0x2a8> + 438006: 0f 29 62 c0 movaps %xmm4,-0x40(%rdx) + 43800a: 0f 29 6a d0 movaps %xmm5,-0x30(%rdx) + 43800e: 0f 29 72 e0 movaps %xmm6,-0x20(%rdx) + 438012: 0f 29 7a f0 movaps %xmm7,-0x10(%rdx) + 438016: eb b8 jmp 437fd0 <__strcpy_ssse3+0x260> + 438018: 66 0f 74 c4 pcmpeqb %xmm4,%xmm0 + 43801c: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438020: 48 85 c0 test %rax,%rax + 438023: 0f 85 27 13 00 00 jne 439350 <__strcpy_ssse3+0x15e0> + 438029: 66 0f 74 c5 pcmpeqb %xmm5,%xmm0 + 43802d: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438031: 0f 29 62 c0 movaps %xmm4,-0x40(%rdx) + 438035: 48 85 c0 test %rax,%rax + 438038: 48 8d 76 10 lea 0x10(%rsi),%rsi + 43803c: 0f 85 0e 13 00 00 jne 439350 <__strcpy_ssse3+0x15e0> + 438042: 66 0f 74 c6 pcmpeqb %xmm6,%xmm0 + 438046: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43804a: 0f 29 6a d0 movaps %xmm5,-0x30(%rdx) + 43804e: 48 85 c0 test %rax,%rax + 438051: 48 8d 76 10 lea 0x10(%rsi),%rsi + 438055: 0f 85 f5 12 00 00 jne 439350 <__strcpy_ssse3+0x15e0> + 43805b: 0f 29 72 e0 movaps %xmm6,-0x20(%rdx) + 43805f: 66 0f 74 c7 pcmpeqb %xmm7,%xmm0 + 438063: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438067: 48 8d 76 10 lea 0x10(%rsi),%rsi + 43806b: e9 e0 12 00 00 jmpq 439350 <__strcpy_ssse3+0x15e0> + 438070: 0f 28 49 ff movaps -0x1(%rcx),%xmm1 + 438074: 0f 28 51 0f movaps 0xf(%rcx),%xmm2 + 438078: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43807c: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438080: 0f 28 da movaps %xmm2,%xmm3 + 438083: 48 85 c0 test %rax,%rax + 438086: 0f 85 0e 01 00 00 jne 43819a <__strcpy_ssse3+0x42a> + 43808c: 66 0f 3a 0f d1 01 palignr $0x1,%xmm1,%xmm2 + 438092: 0f 29 12 movaps %xmm2,(%rdx) + 438095: 0f 28 51 1f movaps 0x1f(%rcx),%xmm2 + 438099: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43809d: 48 8d 52 10 lea 0x10(%rdx),%rdx + 4380a1: 66 0f d7 c0 pmovmskb %xmm0,%eax + 4380a5: 48 8d 49 10 lea 0x10(%rcx),%rcx + 4380a9: 0f 28 ca movaps %xmm2,%xmm1 + 4380ac: 48 85 c0 test %rax,%rax + 4380af: 0f 85 e5 00 00 00 jne 43819a <__strcpy_ssse3+0x42a> + 4380b5: 66 0f 3a 0f d3 01 palignr $0x1,%xmm3,%xmm2 + 4380bb: 0f 29 12 movaps %xmm2,(%rdx) + 4380be: 0f 28 51 1f movaps 0x1f(%rcx),%xmm2 + 4380c2: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 4380c6: 48 8d 52 10 lea 0x10(%rdx),%rdx + 4380ca: 66 0f d7 c0 pmovmskb %xmm0,%eax + 4380ce: 48 8d 49 10 lea 0x10(%rcx),%rcx + 4380d2: 0f 28 da movaps %xmm2,%xmm3 + 4380d5: 48 85 c0 test %rax,%rax + 4380d8: 0f 85 bc 00 00 00 jne 43819a <__strcpy_ssse3+0x42a> + 4380de: 66 0f 3a 0f d1 01 palignr $0x1,%xmm1,%xmm2 + 4380e4: 0f 29 12 movaps %xmm2,(%rdx) + 4380e7: 0f 28 51 1f movaps 0x1f(%rcx),%xmm2 + 4380eb: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 4380ef: 48 8d 52 10 lea 0x10(%rdx),%rdx + 4380f3: 66 0f d7 c0 pmovmskb %xmm0,%eax + 4380f7: 48 8d 49 10 lea 0x10(%rcx),%rcx + 4380fb: 48 85 c0 test %rax,%rax + 4380fe: 0f 85 96 00 00 00 jne 43819a <__strcpy_ssse3+0x42a> + 438104: 66 0f 3a 0f d3 01 palignr $0x1,%xmm3,%xmm2 + 43810a: 0f 29 12 movaps %xmm2,(%rdx) + 43810d: 48 8d 49 1f lea 0x1f(%rcx),%rcx + 438111: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438115: 48 89 c8 mov %rcx,%rax + 438118: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 43811c: 48 29 c8 sub %rcx,%rax + 43811f: 48 8d 49 f1 lea -0xf(%rcx),%rcx + 438123: 48 29 c2 sub %rax,%rdx + 438126: 0f 28 49 ff movaps -0x1(%rcx),%xmm1 + 43812a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 438130: 0f 28 51 0f movaps 0xf(%rcx),%xmm2 + 438134: 0f 28 59 1f movaps 0x1f(%rcx),%xmm3 + 438138: 0f 28 f3 movaps %xmm3,%xmm6 + 43813b: 0f 28 61 2f movaps 0x2f(%rcx),%xmm4 + 43813f: 0f 28 fc movaps %xmm4,%xmm7 + 438142: 0f 28 69 3f movaps 0x3f(%rcx),%xmm5 + 438146: 66 0f da f2 pminub %xmm2,%xmm6 + 43814a: 66 0f da fd pminub %xmm5,%xmm7 + 43814e: 66 0f da fe pminub %xmm6,%xmm7 + 438152: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 438156: 66 0f d7 c7 pmovmskb %xmm7,%eax + 43815a: 0f 28 fd movaps %xmm5,%xmm7 + 43815d: 66 0f 3a 0f ec 01 palignr $0x1,%xmm4,%xmm5 + 438163: 48 85 c0 test %rax,%rax + 438166: 66 0f 3a 0f e3 01 palignr $0x1,%xmm3,%xmm4 + 43816c: 0f 85 06 ff ff ff jne 438078 <__strcpy_ssse3+0x308> + 438172: 66 0f 3a 0f da 01 palignr $0x1,%xmm2,%xmm3 + 438178: 48 8d 49 40 lea 0x40(%rcx),%rcx + 43817c: 66 0f 3a 0f d1 01 palignr $0x1,%xmm1,%xmm2 + 438182: 0f 28 cf movaps %xmm7,%xmm1 + 438185: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) + 438189: 0f 29 62 20 movaps %xmm4,0x20(%rdx) + 43818d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) + 438191: 0f 29 12 movaps %xmm2,(%rdx) + 438194: 48 8d 52 40 lea 0x40(%rdx),%rdx + 438198: eb 96 jmp 438130 <__strcpy_ssse3+0x3c0> + 43819a: f3 0f 6f 49 ff movdqu -0x1(%rcx),%xmm1 + 43819f: 48 c7 c6 0f 00 00 00 mov $0xf,%rsi + 4381a6: f3 0f 7f 4a ff movdqu %xmm1,-0x1(%rdx) + 4381ab: e9 a0 11 00 00 jmpq 439350 <__strcpy_ssse3+0x15e0> + 4381b0: 0f 28 49 fe movaps -0x2(%rcx),%xmm1 + 4381b4: 0f 28 51 0e movaps 0xe(%rcx),%xmm2 + 4381b8: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 4381bc: 66 0f d7 c0 pmovmskb %xmm0,%eax + 4381c0: 0f 28 da movaps %xmm2,%xmm3 + 4381c3: 48 85 c0 test %rax,%rax + 4381c6: 0f 85 0e 01 00 00 jne 4382da <__strcpy_ssse3+0x56a> + 4381cc: 66 0f 3a 0f d1 02 palignr $0x2,%xmm1,%xmm2 + 4381d2: 0f 29 12 movaps %xmm2,(%rdx) + 4381d5: 0f 28 51 1e movaps 0x1e(%rcx),%xmm2 + 4381d9: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 4381dd: 48 8d 52 10 lea 0x10(%rdx),%rdx + 4381e1: 66 0f d7 c0 pmovmskb %xmm0,%eax + 4381e5: 48 8d 49 10 lea 0x10(%rcx),%rcx + 4381e9: 0f 28 ca movaps %xmm2,%xmm1 + 4381ec: 48 85 c0 test %rax,%rax + 4381ef: 0f 85 e5 00 00 00 jne 4382da <__strcpy_ssse3+0x56a> + 4381f5: 66 0f 3a 0f d3 02 palignr $0x2,%xmm3,%xmm2 + 4381fb: 0f 29 12 movaps %xmm2,(%rdx) + 4381fe: 0f 28 51 1e movaps 0x1e(%rcx),%xmm2 + 438202: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 438206: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43820a: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43820e: 48 8d 49 10 lea 0x10(%rcx),%rcx + 438212: 0f 28 da movaps %xmm2,%xmm3 + 438215: 48 85 c0 test %rax,%rax + 438218: 0f 85 bc 00 00 00 jne 4382da <__strcpy_ssse3+0x56a> + 43821e: 66 0f 3a 0f d1 02 palignr $0x2,%xmm1,%xmm2 + 438224: 0f 29 12 movaps %xmm2,(%rdx) + 438227: 0f 28 51 1e movaps 0x1e(%rcx),%xmm2 + 43822b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43822f: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438233: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438237: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43823b: 48 85 c0 test %rax,%rax + 43823e: 0f 85 96 00 00 00 jne 4382da <__strcpy_ssse3+0x56a> + 438244: 66 0f 3a 0f d3 02 palignr $0x2,%xmm3,%xmm2 + 43824a: 0f 29 12 movaps %xmm2,(%rdx) + 43824d: 48 8d 49 1e lea 0x1e(%rcx),%rcx + 438251: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438255: 48 89 c8 mov %rcx,%rax + 438258: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 43825c: 48 29 c8 sub %rcx,%rax + 43825f: 48 8d 49 f2 lea -0xe(%rcx),%rcx + 438263: 48 29 c2 sub %rax,%rdx + 438266: 0f 28 49 fe movaps -0x2(%rcx),%xmm1 + 43826a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 438270: 0f 28 51 0e movaps 0xe(%rcx),%xmm2 + 438274: 0f 28 59 1e movaps 0x1e(%rcx),%xmm3 + 438278: 0f 28 f3 movaps %xmm3,%xmm6 + 43827b: 0f 28 61 2e movaps 0x2e(%rcx),%xmm4 + 43827f: 0f 28 fc movaps %xmm4,%xmm7 + 438282: 0f 28 69 3e movaps 0x3e(%rcx),%xmm5 + 438286: 66 0f da f2 pminub %xmm2,%xmm6 + 43828a: 66 0f da fd pminub %xmm5,%xmm7 + 43828e: 66 0f da fe pminub %xmm6,%xmm7 + 438292: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 438296: 66 0f d7 c7 pmovmskb %xmm7,%eax + 43829a: 0f 28 fd movaps %xmm5,%xmm7 + 43829d: 66 0f 3a 0f ec 02 palignr $0x2,%xmm4,%xmm5 + 4382a3: 48 85 c0 test %rax,%rax + 4382a6: 66 0f 3a 0f e3 02 palignr $0x2,%xmm3,%xmm4 + 4382ac: 0f 85 06 ff ff ff jne 4381b8 <__strcpy_ssse3+0x448> + 4382b2: 66 0f 3a 0f da 02 palignr $0x2,%xmm2,%xmm3 + 4382b8: 48 8d 49 40 lea 0x40(%rcx),%rcx + 4382bc: 66 0f 3a 0f d1 02 palignr $0x2,%xmm1,%xmm2 + 4382c2: 0f 28 cf movaps %xmm7,%xmm1 + 4382c5: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) + 4382c9: 0f 29 62 20 movaps %xmm4,0x20(%rdx) + 4382cd: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) + 4382d1: 0f 29 12 movaps %xmm2,(%rdx) + 4382d4: 48 8d 52 40 lea 0x40(%rdx),%rdx + 4382d8: eb 96 jmp 438270 <__strcpy_ssse3+0x500> + 4382da: f3 0f 6f 49 fe movdqu -0x2(%rcx),%xmm1 + 4382df: 48 c7 c6 0e 00 00 00 mov $0xe,%rsi + 4382e6: f3 0f 7f 4a fe movdqu %xmm1,-0x2(%rdx) + 4382eb: e9 60 10 00 00 jmpq 439350 <__strcpy_ssse3+0x15e0> + 4382f0: 0f 28 49 fd movaps -0x3(%rcx),%xmm1 + 4382f4: 0f 28 51 0d movaps 0xd(%rcx),%xmm2 + 4382f8: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 4382fc: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438300: 0f 28 da movaps %xmm2,%xmm3 + 438303: 48 85 c0 test %rax,%rax + 438306: 0f 85 0e 01 00 00 jne 43841a <__strcpy_ssse3+0x6aa> + 43830c: 66 0f 3a 0f d1 03 palignr $0x3,%xmm1,%xmm2 + 438312: 0f 29 12 movaps %xmm2,(%rdx) + 438315: 0f 28 51 1d movaps 0x1d(%rcx),%xmm2 + 438319: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43831d: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438321: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438325: 48 8d 49 10 lea 0x10(%rcx),%rcx + 438329: 0f 28 ca movaps %xmm2,%xmm1 + 43832c: 48 85 c0 test %rax,%rax + 43832f: 0f 85 e5 00 00 00 jne 43841a <__strcpy_ssse3+0x6aa> + 438335: 66 0f 3a 0f d3 03 palignr $0x3,%xmm3,%xmm2 + 43833b: 0f 29 12 movaps %xmm2,(%rdx) + 43833e: 0f 28 51 1d movaps 0x1d(%rcx),%xmm2 + 438342: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 438346: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43834a: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43834e: 48 8d 49 10 lea 0x10(%rcx),%rcx + 438352: 0f 28 da movaps %xmm2,%xmm3 + 438355: 48 85 c0 test %rax,%rax + 438358: 0f 85 bc 00 00 00 jne 43841a <__strcpy_ssse3+0x6aa> + 43835e: 66 0f 3a 0f d1 03 palignr $0x3,%xmm1,%xmm2 + 438364: 0f 29 12 movaps %xmm2,(%rdx) + 438367: 0f 28 51 1d movaps 0x1d(%rcx),%xmm2 + 43836b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43836f: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438373: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438377: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43837b: 48 85 c0 test %rax,%rax + 43837e: 0f 85 96 00 00 00 jne 43841a <__strcpy_ssse3+0x6aa> + 438384: 66 0f 3a 0f d3 03 palignr $0x3,%xmm3,%xmm2 + 43838a: 0f 29 12 movaps %xmm2,(%rdx) + 43838d: 48 8d 49 1d lea 0x1d(%rcx),%rcx + 438391: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438395: 48 89 c8 mov %rcx,%rax + 438398: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 43839c: 48 29 c8 sub %rcx,%rax + 43839f: 48 8d 49 f3 lea -0xd(%rcx),%rcx + 4383a3: 48 29 c2 sub %rax,%rdx + 4383a6: 0f 28 49 fd movaps -0x3(%rcx),%xmm1 + 4383aa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4383b0: 0f 28 51 0d movaps 0xd(%rcx),%xmm2 + 4383b4: 0f 28 59 1d movaps 0x1d(%rcx),%xmm3 + 4383b8: 0f 28 f3 movaps %xmm3,%xmm6 + 4383bb: 0f 28 61 2d movaps 0x2d(%rcx),%xmm4 + 4383bf: 0f 28 fc movaps %xmm4,%xmm7 + 4383c2: 0f 28 69 3d movaps 0x3d(%rcx),%xmm5 + 4383c6: 66 0f da f2 pminub %xmm2,%xmm6 + 4383ca: 66 0f da fd pminub %xmm5,%xmm7 + 4383ce: 66 0f da fe pminub %xmm6,%xmm7 + 4383d2: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 4383d6: 66 0f d7 c7 pmovmskb %xmm7,%eax + 4383da: 0f 28 fd movaps %xmm5,%xmm7 + 4383dd: 66 0f 3a 0f ec 03 palignr $0x3,%xmm4,%xmm5 + 4383e3: 48 85 c0 test %rax,%rax + 4383e6: 66 0f 3a 0f e3 03 palignr $0x3,%xmm3,%xmm4 + 4383ec: 0f 85 06 ff ff ff jne 4382f8 <__strcpy_ssse3+0x588> + 4383f2: 66 0f 3a 0f da 03 palignr $0x3,%xmm2,%xmm3 + 4383f8: 48 8d 49 40 lea 0x40(%rcx),%rcx + 4383fc: 66 0f 3a 0f d1 03 palignr $0x3,%xmm1,%xmm2 + 438402: 0f 28 cf movaps %xmm7,%xmm1 + 438405: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) + 438409: 0f 29 62 20 movaps %xmm4,0x20(%rdx) + 43840d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) + 438411: 0f 29 12 movaps %xmm2,(%rdx) + 438414: 48 8d 52 40 lea 0x40(%rdx),%rdx + 438418: eb 96 jmp 4383b0 <__strcpy_ssse3+0x640> + 43841a: f3 0f 6f 49 fd movdqu -0x3(%rcx),%xmm1 + 43841f: 48 c7 c6 0d 00 00 00 mov $0xd,%rsi + 438426: f3 0f 7f 4a fd movdqu %xmm1,-0x3(%rdx) + 43842b: e9 20 0f 00 00 jmpq 439350 <__strcpy_ssse3+0x15e0> + 438430: 0f 28 49 fc movaps -0x4(%rcx),%xmm1 + 438434: 0f 28 51 0c movaps 0xc(%rcx),%xmm2 + 438438: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43843c: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438440: 0f 28 da movaps %xmm2,%xmm3 + 438443: 48 85 c0 test %rax,%rax + 438446: 0f 85 0e 01 00 00 jne 43855a <__strcpy_ssse3+0x7ea> + 43844c: 66 0f 3a 0f d1 04 palignr $0x4,%xmm1,%xmm2 + 438452: 0f 29 12 movaps %xmm2,(%rdx) + 438455: 0f 28 51 1c movaps 0x1c(%rcx),%xmm2 + 438459: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43845d: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438461: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438465: 48 8d 49 10 lea 0x10(%rcx),%rcx + 438469: 0f 28 ca movaps %xmm2,%xmm1 + 43846c: 48 85 c0 test %rax,%rax + 43846f: 0f 85 e5 00 00 00 jne 43855a <__strcpy_ssse3+0x7ea> + 438475: 66 0f 3a 0f d3 04 palignr $0x4,%xmm3,%xmm2 + 43847b: 0f 29 12 movaps %xmm2,(%rdx) + 43847e: 0f 28 51 1c movaps 0x1c(%rcx),%xmm2 + 438482: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 438486: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43848a: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43848e: 48 8d 49 10 lea 0x10(%rcx),%rcx + 438492: 0f 28 da movaps %xmm2,%xmm3 + 438495: 48 85 c0 test %rax,%rax + 438498: 0f 85 bc 00 00 00 jne 43855a <__strcpy_ssse3+0x7ea> + 43849e: 66 0f 3a 0f d1 04 palignr $0x4,%xmm1,%xmm2 + 4384a4: 0f 29 12 movaps %xmm2,(%rdx) + 4384a7: 0f 28 51 1c movaps 0x1c(%rcx),%xmm2 + 4384ab: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 4384af: 48 8d 52 10 lea 0x10(%rdx),%rdx + 4384b3: 66 0f d7 c0 pmovmskb %xmm0,%eax + 4384b7: 48 8d 49 10 lea 0x10(%rcx),%rcx + 4384bb: 48 85 c0 test %rax,%rax + 4384be: 0f 85 96 00 00 00 jne 43855a <__strcpy_ssse3+0x7ea> + 4384c4: 66 0f 3a 0f d3 04 palignr $0x4,%xmm3,%xmm2 + 4384ca: 0f 29 12 movaps %xmm2,(%rdx) + 4384cd: 48 8d 49 1c lea 0x1c(%rcx),%rcx + 4384d1: 48 8d 52 10 lea 0x10(%rdx),%rdx + 4384d5: 48 89 c8 mov %rcx,%rax + 4384d8: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 4384dc: 48 29 c8 sub %rcx,%rax + 4384df: 48 8d 49 f4 lea -0xc(%rcx),%rcx + 4384e3: 48 29 c2 sub %rax,%rdx + 4384e6: 0f 28 49 fc movaps -0x4(%rcx),%xmm1 + 4384ea: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4384f0: 0f 28 51 0c movaps 0xc(%rcx),%xmm2 + 4384f4: 0f 28 59 1c movaps 0x1c(%rcx),%xmm3 + 4384f8: 0f 28 f3 movaps %xmm3,%xmm6 + 4384fb: 0f 28 61 2c movaps 0x2c(%rcx),%xmm4 + 4384ff: 0f 28 fc movaps %xmm4,%xmm7 + 438502: 0f 28 69 3c movaps 0x3c(%rcx),%xmm5 + 438506: 66 0f da f2 pminub %xmm2,%xmm6 + 43850a: 66 0f da fd pminub %xmm5,%xmm7 + 43850e: 66 0f da fe pminub %xmm6,%xmm7 + 438512: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 438516: 66 0f d7 c7 pmovmskb %xmm7,%eax + 43851a: 0f 28 fd movaps %xmm5,%xmm7 + 43851d: 66 0f 3a 0f ec 04 palignr $0x4,%xmm4,%xmm5 + 438523: 48 85 c0 test %rax,%rax + 438526: 66 0f 3a 0f e3 04 palignr $0x4,%xmm3,%xmm4 + 43852c: 0f 85 06 ff ff ff jne 438438 <__strcpy_ssse3+0x6c8> + 438532: 66 0f 3a 0f da 04 palignr $0x4,%xmm2,%xmm3 + 438538: 48 8d 49 40 lea 0x40(%rcx),%rcx + 43853c: 66 0f 3a 0f d1 04 palignr $0x4,%xmm1,%xmm2 + 438542: 0f 28 cf movaps %xmm7,%xmm1 + 438545: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) + 438549: 0f 29 62 20 movaps %xmm4,0x20(%rdx) + 43854d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) + 438551: 0f 29 12 movaps %xmm2,(%rdx) + 438554: 48 8d 52 40 lea 0x40(%rdx),%rdx + 438558: eb 96 jmp 4384f0 <__strcpy_ssse3+0x780> + 43855a: f3 0f 6f 49 fc movdqu -0x4(%rcx),%xmm1 + 43855f: 48 c7 c6 0c 00 00 00 mov $0xc,%rsi + 438566: f3 0f 7f 4a fc movdqu %xmm1,-0x4(%rdx) + 43856b: e9 e0 0d 00 00 jmpq 439350 <__strcpy_ssse3+0x15e0> + 438570: 0f 28 49 fb movaps -0x5(%rcx),%xmm1 + 438574: 0f 28 51 0b movaps 0xb(%rcx),%xmm2 + 438578: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43857c: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438580: 0f 28 da movaps %xmm2,%xmm3 + 438583: 48 85 c0 test %rax,%rax + 438586: 0f 85 0e 01 00 00 jne 43869a <__strcpy_ssse3+0x92a> + 43858c: 66 0f 3a 0f d1 05 palignr $0x5,%xmm1,%xmm2 + 438592: 0f 29 12 movaps %xmm2,(%rdx) + 438595: 0f 28 51 1b movaps 0x1b(%rcx),%xmm2 + 438599: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43859d: 48 8d 52 10 lea 0x10(%rdx),%rdx + 4385a1: 66 0f d7 c0 pmovmskb %xmm0,%eax + 4385a5: 48 8d 49 10 lea 0x10(%rcx),%rcx + 4385a9: 0f 28 ca movaps %xmm2,%xmm1 + 4385ac: 48 85 c0 test %rax,%rax + 4385af: 0f 85 e5 00 00 00 jne 43869a <__strcpy_ssse3+0x92a> + 4385b5: 66 0f 3a 0f d3 05 palignr $0x5,%xmm3,%xmm2 + 4385bb: 0f 29 12 movaps %xmm2,(%rdx) + 4385be: 0f 28 51 1b movaps 0x1b(%rcx),%xmm2 + 4385c2: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 4385c6: 48 8d 52 10 lea 0x10(%rdx),%rdx + 4385ca: 66 0f d7 c0 pmovmskb %xmm0,%eax + 4385ce: 48 8d 49 10 lea 0x10(%rcx),%rcx + 4385d2: 0f 28 da movaps %xmm2,%xmm3 + 4385d5: 48 85 c0 test %rax,%rax + 4385d8: 0f 85 bc 00 00 00 jne 43869a <__strcpy_ssse3+0x92a> + 4385de: 66 0f 3a 0f d1 05 palignr $0x5,%xmm1,%xmm2 + 4385e4: 0f 29 12 movaps %xmm2,(%rdx) + 4385e7: 0f 28 51 1b movaps 0x1b(%rcx),%xmm2 + 4385eb: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 4385ef: 48 8d 52 10 lea 0x10(%rdx),%rdx + 4385f3: 66 0f d7 c0 pmovmskb %xmm0,%eax + 4385f7: 48 8d 49 10 lea 0x10(%rcx),%rcx + 4385fb: 48 85 c0 test %rax,%rax + 4385fe: 0f 85 96 00 00 00 jne 43869a <__strcpy_ssse3+0x92a> + 438604: 66 0f 3a 0f d3 05 palignr $0x5,%xmm3,%xmm2 + 43860a: 0f 29 12 movaps %xmm2,(%rdx) + 43860d: 48 8d 49 1b lea 0x1b(%rcx),%rcx + 438611: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438615: 48 89 c8 mov %rcx,%rax + 438618: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 43861c: 48 29 c8 sub %rcx,%rax + 43861f: 48 8d 49 f5 lea -0xb(%rcx),%rcx + 438623: 48 29 c2 sub %rax,%rdx + 438626: 0f 28 49 fb movaps -0x5(%rcx),%xmm1 + 43862a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 438630: 0f 28 51 0b movaps 0xb(%rcx),%xmm2 + 438634: 0f 28 59 1b movaps 0x1b(%rcx),%xmm3 + 438638: 0f 28 f3 movaps %xmm3,%xmm6 + 43863b: 0f 28 61 2b movaps 0x2b(%rcx),%xmm4 + 43863f: 0f 28 fc movaps %xmm4,%xmm7 + 438642: 0f 28 69 3b movaps 0x3b(%rcx),%xmm5 + 438646: 66 0f da f2 pminub %xmm2,%xmm6 + 43864a: 66 0f da fd pminub %xmm5,%xmm7 + 43864e: 66 0f da fe pminub %xmm6,%xmm7 + 438652: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 438656: 66 0f d7 c7 pmovmskb %xmm7,%eax + 43865a: 0f 28 fd movaps %xmm5,%xmm7 + 43865d: 66 0f 3a 0f ec 05 palignr $0x5,%xmm4,%xmm5 + 438663: 48 85 c0 test %rax,%rax + 438666: 66 0f 3a 0f e3 05 palignr $0x5,%xmm3,%xmm4 + 43866c: 0f 85 06 ff ff ff jne 438578 <__strcpy_ssse3+0x808> + 438672: 66 0f 3a 0f da 05 palignr $0x5,%xmm2,%xmm3 + 438678: 48 8d 49 40 lea 0x40(%rcx),%rcx + 43867c: 66 0f 3a 0f d1 05 palignr $0x5,%xmm1,%xmm2 + 438682: 0f 28 cf movaps %xmm7,%xmm1 + 438685: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) + 438689: 0f 29 62 20 movaps %xmm4,0x20(%rdx) + 43868d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) + 438691: 0f 29 12 movaps %xmm2,(%rdx) + 438694: 48 8d 52 40 lea 0x40(%rdx),%rdx + 438698: eb 96 jmp 438630 <__strcpy_ssse3+0x8c0> + 43869a: f3 0f 6f 49 fb movdqu -0x5(%rcx),%xmm1 + 43869f: 48 c7 c6 0b 00 00 00 mov $0xb,%rsi + 4386a6: f3 0f 7f 4a fb movdqu %xmm1,-0x5(%rdx) + 4386ab: e9 a0 0c 00 00 jmpq 439350 <__strcpy_ssse3+0x15e0> + 4386b0: 0f 28 49 fa movaps -0x6(%rcx),%xmm1 + 4386b4: 0f 28 51 0a movaps 0xa(%rcx),%xmm2 + 4386b8: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 4386bc: 66 0f d7 c0 pmovmskb %xmm0,%eax + 4386c0: 0f 28 da movaps %xmm2,%xmm3 + 4386c3: 48 85 c0 test %rax,%rax + 4386c6: 0f 85 0e 01 00 00 jne 4387da <__strcpy_ssse3+0xa6a> + 4386cc: 66 0f 3a 0f d1 06 palignr $0x6,%xmm1,%xmm2 + 4386d2: 0f 29 12 movaps %xmm2,(%rdx) + 4386d5: 0f 28 51 1a movaps 0x1a(%rcx),%xmm2 + 4386d9: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 4386dd: 48 8d 52 10 lea 0x10(%rdx),%rdx + 4386e1: 66 0f d7 c0 pmovmskb %xmm0,%eax + 4386e5: 48 8d 49 10 lea 0x10(%rcx),%rcx + 4386e9: 0f 28 ca movaps %xmm2,%xmm1 + 4386ec: 48 85 c0 test %rax,%rax + 4386ef: 0f 85 e5 00 00 00 jne 4387da <__strcpy_ssse3+0xa6a> + 4386f5: 66 0f 3a 0f d3 06 palignr $0x6,%xmm3,%xmm2 + 4386fb: 0f 29 12 movaps %xmm2,(%rdx) + 4386fe: 0f 28 51 1a movaps 0x1a(%rcx),%xmm2 + 438702: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 438706: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43870a: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43870e: 48 8d 49 10 lea 0x10(%rcx),%rcx + 438712: 0f 28 da movaps %xmm2,%xmm3 + 438715: 48 85 c0 test %rax,%rax + 438718: 0f 85 bc 00 00 00 jne 4387da <__strcpy_ssse3+0xa6a> + 43871e: 66 0f 3a 0f d1 06 palignr $0x6,%xmm1,%xmm2 + 438724: 0f 29 12 movaps %xmm2,(%rdx) + 438727: 0f 28 51 1a movaps 0x1a(%rcx),%xmm2 + 43872b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43872f: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438733: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438737: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43873b: 48 85 c0 test %rax,%rax + 43873e: 0f 85 96 00 00 00 jne 4387da <__strcpy_ssse3+0xa6a> + 438744: 66 0f 3a 0f d3 06 palignr $0x6,%xmm3,%xmm2 + 43874a: 0f 29 12 movaps %xmm2,(%rdx) + 43874d: 48 8d 49 1a lea 0x1a(%rcx),%rcx + 438751: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438755: 48 89 c8 mov %rcx,%rax + 438758: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 43875c: 48 29 c8 sub %rcx,%rax + 43875f: 48 8d 49 f6 lea -0xa(%rcx),%rcx + 438763: 48 29 c2 sub %rax,%rdx + 438766: 0f 28 49 fa movaps -0x6(%rcx),%xmm1 + 43876a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 438770: 0f 28 51 0a movaps 0xa(%rcx),%xmm2 + 438774: 0f 28 59 1a movaps 0x1a(%rcx),%xmm3 + 438778: 0f 28 f3 movaps %xmm3,%xmm6 + 43877b: 0f 28 61 2a movaps 0x2a(%rcx),%xmm4 + 43877f: 0f 28 fc movaps %xmm4,%xmm7 + 438782: 0f 28 69 3a movaps 0x3a(%rcx),%xmm5 + 438786: 66 0f da f2 pminub %xmm2,%xmm6 + 43878a: 66 0f da fd pminub %xmm5,%xmm7 + 43878e: 66 0f da fe pminub %xmm6,%xmm7 + 438792: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 438796: 66 0f d7 c7 pmovmskb %xmm7,%eax + 43879a: 0f 28 fd movaps %xmm5,%xmm7 + 43879d: 66 0f 3a 0f ec 06 palignr $0x6,%xmm4,%xmm5 + 4387a3: 48 85 c0 test %rax,%rax + 4387a6: 66 0f 3a 0f e3 06 palignr $0x6,%xmm3,%xmm4 + 4387ac: 0f 85 06 ff ff ff jne 4386b8 <__strcpy_ssse3+0x948> + 4387b2: 66 0f 3a 0f da 06 palignr $0x6,%xmm2,%xmm3 + 4387b8: 48 8d 49 40 lea 0x40(%rcx),%rcx + 4387bc: 66 0f 3a 0f d1 06 palignr $0x6,%xmm1,%xmm2 + 4387c2: 0f 28 cf movaps %xmm7,%xmm1 + 4387c5: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) + 4387c9: 0f 29 62 20 movaps %xmm4,0x20(%rdx) + 4387cd: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) + 4387d1: 0f 29 12 movaps %xmm2,(%rdx) + 4387d4: 48 8d 52 40 lea 0x40(%rdx),%rdx + 4387d8: eb 96 jmp 438770 <__strcpy_ssse3+0xa00> + 4387da: 4c 8b 09 mov (%rcx),%r9 + 4387dd: 8b 71 06 mov 0x6(%rcx),%esi + 4387e0: 4c 89 0a mov %r9,(%rdx) + 4387e3: 89 72 06 mov %esi,0x6(%rdx) + 4387e6: 48 c7 c6 0a 00 00 00 mov $0xa,%rsi + 4387ed: e9 5e 0b 00 00 jmpq 439350 <__strcpy_ssse3+0x15e0> + 4387f2: 0f 1f 40 00 nopl 0x0(%rax) + 4387f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4387fd: 00 00 00 + 438800: 0f 28 49 f9 movaps -0x7(%rcx),%xmm1 + 438804: 0f 28 51 09 movaps 0x9(%rcx),%xmm2 + 438808: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43880c: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438810: 0f 28 da movaps %xmm2,%xmm3 + 438813: 48 85 c0 test %rax,%rax + 438816: 0f 85 0e 01 00 00 jne 43892a <__strcpy_ssse3+0xbba> + 43881c: 66 0f 3a 0f d1 07 palignr $0x7,%xmm1,%xmm2 + 438822: 0f 29 12 movaps %xmm2,(%rdx) + 438825: 0f 28 51 19 movaps 0x19(%rcx),%xmm2 + 438829: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43882d: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438831: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438835: 48 8d 49 10 lea 0x10(%rcx),%rcx + 438839: 0f 28 ca movaps %xmm2,%xmm1 + 43883c: 48 85 c0 test %rax,%rax + 43883f: 0f 85 e5 00 00 00 jne 43892a <__strcpy_ssse3+0xbba> + 438845: 66 0f 3a 0f d3 07 palignr $0x7,%xmm3,%xmm2 + 43884b: 0f 29 12 movaps %xmm2,(%rdx) + 43884e: 0f 28 51 19 movaps 0x19(%rcx),%xmm2 + 438852: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 438856: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43885a: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43885e: 48 8d 49 10 lea 0x10(%rcx),%rcx + 438862: 0f 28 da movaps %xmm2,%xmm3 + 438865: 48 85 c0 test %rax,%rax + 438868: 0f 85 bc 00 00 00 jne 43892a <__strcpy_ssse3+0xbba> + 43886e: 66 0f 3a 0f d1 07 palignr $0x7,%xmm1,%xmm2 + 438874: 0f 29 12 movaps %xmm2,(%rdx) + 438877: 0f 28 51 19 movaps 0x19(%rcx),%xmm2 + 43887b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43887f: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438883: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438887: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43888b: 48 85 c0 test %rax,%rax + 43888e: 0f 85 96 00 00 00 jne 43892a <__strcpy_ssse3+0xbba> + 438894: 66 0f 3a 0f d3 07 palignr $0x7,%xmm3,%xmm2 + 43889a: 0f 29 12 movaps %xmm2,(%rdx) + 43889d: 48 8d 49 19 lea 0x19(%rcx),%rcx + 4388a1: 48 8d 52 10 lea 0x10(%rdx),%rdx + 4388a5: 48 89 c8 mov %rcx,%rax + 4388a8: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 4388ac: 48 29 c8 sub %rcx,%rax + 4388af: 48 8d 49 f7 lea -0x9(%rcx),%rcx + 4388b3: 48 29 c2 sub %rax,%rdx + 4388b6: 0f 28 49 f9 movaps -0x7(%rcx),%xmm1 + 4388ba: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4388c0: 0f 28 51 09 movaps 0x9(%rcx),%xmm2 + 4388c4: 0f 28 59 19 movaps 0x19(%rcx),%xmm3 + 4388c8: 0f 28 f3 movaps %xmm3,%xmm6 + 4388cb: 0f 28 61 29 movaps 0x29(%rcx),%xmm4 + 4388cf: 0f 28 fc movaps %xmm4,%xmm7 + 4388d2: 0f 28 69 39 movaps 0x39(%rcx),%xmm5 + 4388d6: 66 0f da f2 pminub %xmm2,%xmm6 + 4388da: 66 0f da fd pminub %xmm5,%xmm7 + 4388de: 66 0f da fe pminub %xmm6,%xmm7 + 4388e2: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 4388e6: 66 0f d7 c7 pmovmskb %xmm7,%eax + 4388ea: 0f 28 fd movaps %xmm5,%xmm7 + 4388ed: 66 0f 3a 0f ec 07 palignr $0x7,%xmm4,%xmm5 + 4388f3: 48 85 c0 test %rax,%rax + 4388f6: 66 0f 3a 0f e3 07 palignr $0x7,%xmm3,%xmm4 + 4388fc: 0f 85 06 ff ff ff jne 438808 <__strcpy_ssse3+0xa98> + 438902: 66 0f 3a 0f da 07 palignr $0x7,%xmm2,%xmm3 + 438908: 48 8d 49 40 lea 0x40(%rcx),%rcx + 43890c: 66 0f 3a 0f d1 07 palignr $0x7,%xmm1,%xmm2 + 438912: 0f 28 cf movaps %xmm7,%xmm1 + 438915: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) + 438919: 0f 29 62 20 movaps %xmm4,0x20(%rdx) + 43891d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) + 438921: 0f 29 12 movaps %xmm2,(%rdx) + 438924: 48 8d 52 40 lea 0x40(%rdx),%rdx + 438928: eb 96 jmp 4388c0 <__strcpy_ssse3+0xb50> + 43892a: 4c 8b 09 mov (%rcx),%r9 + 43892d: 8b 71 05 mov 0x5(%rcx),%esi + 438930: 4c 89 0a mov %r9,(%rdx) + 438933: 89 72 05 mov %esi,0x5(%rdx) + 438936: 48 c7 c6 09 00 00 00 mov $0x9,%rsi + 43893d: e9 0e 0a 00 00 jmpq 439350 <__strcpy_ssse3+0x15e0> + 438942: 0f 1f 40 00 nopl 0x0(%rax) + 438946: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43894d: 00 00 00 + 438950: 0f 28 49 f8 movaps -0x8(%rcx),%xmm1 + 438954: 0f 28 51 08 movaps 0x8(%rcx),%xmm2 + 438958: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43895c: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438960: 0f 28 da movaps %xmm2,%xmm3 + 438963: 48 85 c0 test %rax,%rax + 438966: 0f 85 0e 01 00 00 jne 438a7a <__strcpy_ssse3+0xd0a> + 43896c: 66 0f 3a 0f d1 08 palignr $0x8,%xmm1,%xmm2 + 438972: 0f 29 12 movaps %xmm2,(%rdx) + 438975: 0f 28 51 18 movaps 0x18(%rcx),%xmm2 + 438979: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43897d: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438981: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438985: 48 8d 49 10 lea 0x10(%rcx),%rcx + 438989: 0f 28 ca movaps %xmm2,%xmm1 + 43898c: 48 85 c0 test %rax,%rax + 43898f: 0f 85 e5 00 00 00 jne 438a7a <__strcpy_ssse3+0xd0a> + 438995: 66 0f 3a 0f d3 08 palignr $0x8,%xmm3,%xmm2 + 43899b: 0f 29 12 movaps %xmm2,(%rdx) + 43899e: 0f 28 51 18 movaps 0x18(%rcx),%xmm2 + 4389a2: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 4389a6: 48 8d 52 10 lea 0x10(%rdx),%rdx + 4389aa: 66 0f d7 c0 pmovmskb %xmm0,%eax + 4389ae: 48 8d 49 10 lea 0x10(%rcx),%rcx + 4389b2: 0f 28 da movaps %xmm2,%xmm3 + 4389b5: 48 85 c0 test %rax,%rax + 4389b8: 0f 85 bc 00 00 00 jne 438a7a <__strcpy_ssse3+0xd0a> + 4389be: 66 0f 3a 0f d1 08 palignr $0x8,%xmm1,%xmm2 + 4389c4: 0f 29 12 movaps %xmm2,(%rdx) + 4389c7: 0f 28 51 18 movaps 0x18(%rcx),%xmm2 + 4389cb: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 4389cf: 48 8d 52 10 lea 0x10(%rdx),%rdx + 4389d3: 66 0f d7 c0 pmovmskb %xmm0,%eax + 4389d7: 48 8d 49 10 lea 0x10(%rcx),%rcx + 4389db: 48 85 c0 test %rax,%rax + 4389de: 0f 85 96 00 00 00 jne 438a7a <__strcpy_ssse3+0xd0a> + 4389e4: 66 0f 3a 0f d3 08 palignr $0x8,%xmm3,%xmm2 + 4389ea: 0f 29 12 movaps %xmm2,(%rdx) + 4389ed: 48 8d 49 18 lea 0x18(%rcx),%rcx + 4389f1: 48 8d 52 10 lea 0x10(%rdx),%rdx + 4389f5: 48 89 c8 mov %rcx,%rax + 4389f8: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 4389fc: 48 29 c8 sub %rcx,%rax + 4389ff: 48 8d 49 f8 lea -0x8(%rcx),%rcx + 438a03: 48 29 c2 sub %rax,%rdx + 438a06: 0f 28 49 f8 movaps -0x8(%rcx),%xmm1 + 438a0a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 438a10: 0f 28 51 08 movaps 0x8(%rcx),%xmm2 + 438a14: 0f 28 59 18 movaps 0x18(%rcx),%xmm3 + 438a18: 0f 28 f3 movaps %xmm3,%xmm6 + 438a1b: 0f 28 61 28 movaps 0x28(%rcx),%xmm4 + 438a1f: 0f 28 fc movaps %xmm4,%xmm7 + 438a22: 0f 28 69 38 movaps 0x38(%rcx),%xmm5 + 438a26: 66 0f da f2 pminub %xmm2,%xmm6 + 438a2a: 66 0f da fd pminub %xmm5,%xmm7 + 438a2e: 66 0f da fe pminub %xmm6,%xmm7 + 438a32: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 438a36: 66 0f d7 c7 pmovmskb %xmm7,%eax + 438a3a: 0f 28 fd movaps %xmm5,%xmm7 + 438a3d: 66 0f 3a 0f ec 08 palignr $0x8,%xmm4,%xmm5 + 438a43: 48 85 c0 test %rax,%rax + 438a46: 66 0f 3a 0f e3 08 palignr $0x8,%xmm3,%xmm4 + 438a4c: 0f 85 06 ff ff ff jne 438958 <__strcpy_ssse3+0xbe8> + 438a52: 66 0f 3a 0f da 08 palignr $0x8,%xmm2,%xmm3 + 438a58: 48 8d 49 40 lea 0x40(%rcx),%rcx + 438a5c: 66 0f 3a 0f d1 08 palignr $0x8,%xmm1,%xmm2 + 438a62: 0f 28 cf movaps %xmm7,%xmm1 + 438a65: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) + 438a69: 0f 29 62 20 movaps %xmm4,0x20(%rdx) + 438a6d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) + 438a71: 0f 29 12 movaps %xmm2,(%rdx) + 438a74: 48 8d 52 40 lea 0x40(%rdx),%rdx + 438a78: eb 96 jmp 438a10 <__strcpy_ssse3+0xca0> + 438a7a: 4c 8b 09 mov (%rcx),%r9 + 438a7d: 48 c7 c6 08 00 00 00 mov $0x8,%rsi + 438a84: 4c 89 0a mov %r9,(%rdx) + 438a87: e9 c4 08 00 00 jmpq 439350 <__strcpy_ssse3+0x15e0> + 438a8c: 0f 1f 40 00 nopl 0x0(%rax) + 438a90: 0f 28 49 f7 movaps -0x9(%rcx),%xmm1 + 438a94: 0f 28 51 07 movaps 0x7(%rcx),%xmm2 + 438a98: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 438a9c: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438aa0: 0f 28 da movaps %xmm2,%xmm3 + 438aa3: 48 85 c0 test %rax,%rax + 438aa6: 0f 85 0e 01 00 00 jne 438bba <__strcpy_ssse3+0xe4a> + 438aac: 66 0f 3a 0f d1 09 palignr $0x9,%xmm1,%xmm2 + 438ab2: 0f 29 12 movaps %xmm2,(%rdx) + 438ab5: 0f 28 51 17 movaps 0x17(%rcx),%xmm2 + 438ab9: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 438abd: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438ac1: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438ac5: 48 8d 49 10 lea 0x10(%rcx),%rcx + 438ac9: 0f 28 ca movaps %xmm2,%xmm1 + 438acc: 48 85 c0 test %rax,%rax + 438acf: 0f 85 e5 00 00 00 jne 438bba <__strcpy_ssse3+0xe4a> + 438ad5: 66 0f 3a 0f d3 09 palignr $0x9,%xmm3,%xmm2 + 438adb: 0f 29 12 movaps %xmm2,(%rdx) + 438ade: 0f 28 51 17 movaps 0x17(%rcx),%xmm2 + 438ae2: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 438ae6: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438aea: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438aee: 48 8d 49 10 lea 0x10(%rcx),%rcx + 438af2: 0f 28 da movaps %xmm2,%xmm3 + 438af5: 48 85 c0 test %rax,%rax + 438af8: 0f 85 bc 00 00 00 jne 438bba <__strcpy_ssse3+0xe4a> + 438afe: 66 0f 3a 0f d1 09 palignr $0x9,%xmm1,%xmm2 + 438b04: 0f 29 12 movaps %xmm2,(%rdx) + 438b07: 0f 28 51 17 movaps 0x17(%rcx),%xmm2 + 438b0b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 438b0f: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438b13: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438b17: 48 8d 49 10 lea 0x10(%rcx),%rcx + 438b1b: 48 85 c0 test %rax,%rax + 438b1e: 0f 85 96 00 00 00 jne 438bba <__strcpy_ssse3+0xe4a> + 438b24: 66 0f 3a 0f d3 09 palignr $0x9,%xmm3,%xmm2 + 438b2a: 0f 29 12 movaps %xmm2,(%rdx) + 438b2d: 48 8d 49 17 lea 0x17(%rcx),%rcx + 438b31: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438b35: 48 89 c8 mov %rcx,%rax + 438b38: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 438b3c: 48 29 c8 sub %rcx,%rax + 438b3f: 48 8d 49 f9 lea -0x7(%rcx),%rcx + 438b43: 48 29 c2 sub %rax,%rdx + 438b46: 0f 28 49 f7 movaps -0x9(%rcx),%xmm1 + 438b4a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 438b50: 0f 28 51 07 movaps 0x7(%rcx),%xmm2 + 438b54: 0f 28 59 17 movaps 0x17(%rcx),%xmm3 + 438b58: 0f 28 f3 movaps %xmm3,%xmm6 + 438b5b: 0f 28 61 27 movaps 0x27(%rcx),%xmm4 + 438b5f: 0f 28 fc movaps %xmm4,%xmm7 + 438b62: 0f 28 69 37 movaps 0x37(%rcx),%xmm5 + 438b66: 66 0f da f2 pminub %xmm2,%xmm6 + 438b6a: 66 0f da fd pminub %xmm5,%xmm7 + 438b6e: 66 0f da fe pminub %xmm6,%xmm7 + 438b72: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 438b76: 66 0f d7 c7 pmovmskb %xmm7,%eax + 438b7a: 0f 28 fd movaps %xmm5,%xmm7 + 438b7d: 66 0f 3a 0f ec 09 palignr $0x9,%xmm4,%xmm5 + 438b83: 48 85 c0 test %rax,%rax + 438b86: 66 0f 3a 0f e3 09 palignr $0x9,%xmm3,%xmm4 + 438b8c: 0f 85 06 ff ff ff jne 438a98 <__strcpy_ssse3+0xd28> + 438b92: 66 0f 3a 0f da 09 palignr $0x9,%xmm2,%xmm3 + 438b98: 48 8d 49 40 lea 0x40(%rcx),%rcx + 438b9c: 66 0f 3a 0f d1 09 palignr $0x9,%xmm1,%xmm2 + 438ba2: 0f 28 cf movaps %xmm7,%xmm1 + 438ba5: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) + 438ba9: 0f 29 62 20 movaps %xmm4,0x20(%rdx) + 438bad: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) + 438bb1: 0f 29 12 movaps %xmm2,(%rdx) + 438bb4: 48 8d 52 40 lea 0x40(%rdx),%rdx + 438bb8: eb 96 jmp 438b50 <__strcpy_ssse3+0xde0> + 438bba: 4c 8b 49 ff mov -0x1(%rcx),%r9 + 438bbe: 48 c7 c6 07 00 00 00 mov $0x7,%rsi + 438bc5: 4c 89 4a ff mov %r9,-0x1(%rdx) + 438bc9: e9 82 07 00 00 jmpq 439350 <__strcpy_ssse3+0x15e0> + 438bce: 66 90 xchg %ax,%ax + 438bd0: 0f 28 49 f6 movaps -0xa(%rcx),%xmm1 + 438bd4: 0f 28 51 06 movaps 0x6(%rcx),%xmm2 + 438bd8: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 438bdc: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438be0: 0f 28 da movaps %xmm2,%xmm3 + 438be3: 48 85 c0 test %rax,%rax + 438be6: 0f 85 0e 01 00 00 jne 438cfa <__strcpy_ssse3+0xf8a> + 438bec: 66 0f 3a 0f d1 0a palignr $0xa,%xmm1,%xmm2 + 438bf2: 0f 29 12 movaps %xmm2,(%rdx) + 438bf5: 0f 28 51 16 movaps 0x16(%rcx),%xmm2 + 438bf9: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 438bfd: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438c01: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438c05: 48 8d 49 10 lea 0x10(%rcx),%rcx + 438c09: 0f 28 ca movaps %xmm2,%xmm1 + 438c0c: 48 85 c0 test %rax,%rax + 438c0f: 0f 85 e5 00 00 00 jne 438cfa <__strcpy_ssse3+0xf8a> + 438c15: 66 0f 3a 0f d3 0a palignr $0xa,%xmm3,%xmm2 + 438c1b: 0f 29 12 movaps %xmm2,(%rdx) + 438c1e: 0f 28 51 16 movaps 0x16(%rcx),%xmm2 + 438c22: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 438c26: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438c2a: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438c2e: 48 8d 49 10 lea 0x10(%rcx),%rcx + 438c32: 0f 28 da movaps %xmm2,%xmm3 + 438c35: 48 85 c0 test %rax,%rax + 438c38: 0f 85 bc 00 00 00 jne 438cfa <__strcpy_ssse3+0xf8a> + 438c3e: 66 0f 3a 0f d1 0a palignr $0xa,%xmm1,%xmm2 + 438c44: 0f 29 12 movaps %xmm2,(%rdx) + 438c47: 0f 28 51 16 movaps 0x16(%rcx),%xmm2 + 438c4b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 438c4f: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438c53: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438c57: 48 8d 49 10 lea 0x10(%rcx),%rcx + 438c5b: 48 85 c0 test %rax,%rax + 438c5e: 0f 85 96 00 00 00 jne 438cfa <__strcpy_ssse3+0xf8a> + 438c64: 66 0f 3a 0f d3 0a palignr $0xa,%xmm3,%xmm2 + 438c6a: 0f 29 12 movaps %xmm2,(%rdx) + 438c6d: 48 8d 49 16 lea 0x16(%rcx),%rcx + 438c71: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438c75: 48 89 c8 mov %rcx,%rax + 438c78: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 438c7c: 48 29 c8 sub %rcx,%rax + 438c7f: 48 8d 49 fa lea -0x6(%rcx),%rcx + 438c83: 48 29 c2 sub %rax,%rdx + 438c86: 0f 28 49 f6 movaps -0xa(%rcx),%xmm1 + 438c8a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 438c90: 0f 28 51 06 movaps 0x6(%rcx),%xmm2 + 438c94: 0f 28 59 16 movaps 0x16(%rcx),%xmm3 + 438c98: 0f 28 f3 movaps %xmm3,%xmm6 + 438c9b: 0f 28 61 26 movaps 0x26(%rcx),%xmm4 + 438c9f: 0f 28 fc movaps %xmm4,%xmm7 + 438ca2: 0f 28 69 36 movaps 0x36(%rcx),%xmm5 + 438ca6: 66 0f da f2 pminub %xmm2,%xmm6 + 438caa: 66 0f da fd pminub %xmm5,%xmm7 + 438cae: 66 0f da fe pminub %xmm6,%xmm7 + 438cb2: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 438cb6: 66 0f d7 c7 pmovmskb %xmm7,%eax + 438cba: 0f 28 fd movaps %xmm5,%xmm7 + 438cbd: 66 0f 3a 0f ec 0a palignr $0xa,%xmm4,%xmm5 + 438cc3: 48 85 c0 test %rax,%rax + 438cc6: 66 0f 3a 0f e3 0a palignr $0xa,%xmm3,%xmm4 + 438ccc: 0f 85 06 ff ff ff jne 438bd8 <__strcpy_ssse3+0xe68> + 438cd2: 66 0f 3a 0f da 0a palignr $0xa,%xmm2,%xmm3 + 438cd8: 48 8d 49 40 lea 0x40(%rcx),%rcx + 438cdc: 66 0f 3a 0f d1 0a palignr $0xa,%xmm1,%xmm2 + 438ce2: 0f 28 cf movaps %xmm7,%xmm1 + 438ce5: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) + 438ce9: 0f 29 62 20 movaps %xmm4,0x20(%rdx) + 438ced: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) + 438cf1: 0f 29 12 movaps %xmm2,(%rdx) + 438cf4: 48 8d 52 40 lea 0x40(%rdx),%rdx + 438cf8: eb 96 jmp 438c90 <__strcpy_ssse3+0xf20> + 438cfa: 4c 8b 49 fe mov -0x2(%rcx),%r9 + 438cfe: 48 c7 c6 06 00 00 00 mov $0x6,%rsi + 438d05: 4c 89 4a fe mov %r9,-0x2(%rdx) + 438d09: e9 42 06 00 00 jmpq 439350 <__strcpy_ssse3+0x15e0> + 438d0e: 66 90 xchg %ax,%ax + 438d10: 0f 28 49 f5 movaps -0xb(%rcx),%xmm1 + 438d14: 0f 28 51 05 movaps 0x5(%rcx),%xmm2 + 438d18: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 438d1c: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438d20: 0f 28 da movaps %xmm2,%xmm3 + 438d23: 48 85 c0 test %rax,%rax + 438d26: 0f 85 0e 01 00 00 jne 438e3a <__strcpy_ssse3+0x10ca> + 438d2c: 66 0f 3a 0f d1 0b palignr $0xb,%xmm1,%xmm2 + 438d32: 0f 29 12 movaps %xmm2,(%rdx) + 438d35: 0f 28 51 15 movaps 0x15(%rcx),%xmm2 + 438d39: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 438d3d: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438d41: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438d45: 48 8d 49 10 lea 0x10(%rcx),%rcx + 438d49: 0f 28 ca movaps %xmm2,%xmm1 + 438d4c: 48 85 c0 test %rax,%rax + 438d4f: 0f 85 e5 00 00 00 jne 438e3a <__strcpy_ssse3+0x10ca> + 438d55: 66 0f 3a 0f d3 0b palignr $0xb,%xmm3,%xmm2 + 438d5b: 0f 29 12 movaps %xmm2,(%rdx) + 438d5e: 0f 28 51 15 movaps 0x15(%rcx),%xmm2 + 438d62: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 438d66: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438d6a: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438d6e: 48 8d 49 10 lea 0x10(%rcx),%rcx + 438d72: 0f 28 da movaps %xmm2,%xmm3 + 438d75: 48 85 c0 test %rax,%rax + 438d78: 0f 85 bc 00 00 00 jne 438e3a <__strcpy_ssse3+0x10ca> + 438d7e: 66 0f 3a 0f d1 0b palignr $0xb,%xmm1,%xmm2 + 438d84: 0f 29 12 movaps %xmm2,(%rdx) + 438d87: 0f 28 51 15 movaps 0x15(%rcx),%xmm2 + 438d8b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 438d8f: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438d93: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438d97: 48 8d 49 10 lea 0x10(%rcx),%rcx + 438d9b: 48 85 c0 test %rax,%rax + 438d9e: 0f 85 96 00 00 00 jne 438e3a <__strcpy_ssse3+0x10ca> + 438da4: 66 0f 3a 0f d3 0b palignr $0xb,%xmm3,%xmm2 + 438daa: 0f 29 12 movaps %xmm2,(%rdx) + 438dad: 48 8d 49 15 lea 0x15(%rcx),%rcx + 438db1: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438db5: 48 89 c8 mov %rcx,%rax + 438db8: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 438dbc: 48 29 c8 sub %rcx,%rax + 438dbf: 48 8d 49 fb lea -0x5(%rcx),%rcx + 438dc3: 48 29 c2 sub %rax,%rdx + 438dc6: 0f 28 49 f5 movaps -0xb(%rcx),%xmm1 + 438dca: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 438dd0: 0f 28 51 05 movaps 0x5(%rcx),%xmm2 + 438dd4: 0f 28 59 15 movaps 0x15(%rcx),%xmm3 + 438dd8: 0f 28 f3 movaps %xmm3,%xmm6 + 438ddb: 0f 28 61 25 movaps 0x25(%rcx),%xmm4 + 438ddf: 0f 28 fc movaps %xmm4,%xmm7 + 438de2: 0f 28 69 35 movaps 0x35(%rcx),%xmm5 + 438de6: 66 0f da f2 pminub %xmm2,%xmm6 + 438dea: 66 0f da fd pminub %xmm5,%xmm7 + 438dee: 66 0f da fe pminub %xmm6,%xmm7 + 438df2: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 438df6: 66 0f d7 c7 pmovmskb %xmm7,%eax + 438dfa: 0f 28 fd movaps %xmm5,%xmm7 + 438dfd: 66 0f 3a 0f ec 0b palignr $0xb,%xmm4,%xmm5 + 438e03: 48 85 c0 test %rax,%rax + 438e06: 66 0f 3a 0f e3 0b palignr $0xb,%xmm3,%xmm4 + 438e0c: 0f 85 06 ff ff ff jne 438d18 <__strcpy_ssse3+0xfa8> + 438e12: 66 0f 3a 0f da 0b palignr $0xb,%xmm2,%xmm3 + 438e18: 48 8d 49 40 lea 0x40(%rcx),%rcx + 438e1c: 66 0f 3a 0f d1 0b palignr $0xb,%xmm1,%xmm2 + 438e22: 0f 28 cf movaps %xmm7,%xmm1 + 438e25: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) + 438e29: 0f 29 62 20 movaps %xmm4,0x20(%rdx) + 438e2d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) + 438e31: 0f 29 12 movaps %xmm2,(%rdx) + 438e34: 48 8d 52 40 lea 0x40(%rdx),%rdx + 438e38: eb 96 jmp 438dd0 <__strcpy_ssse3+0x1060> + 438e3a: 4c 8b 49 fd mov -0x3(%rcx),%r9 + 438e3e: 48 c7 c6 05 00 00 00 mov $0x5,%rsi + 438e45: 4c 89 4a fd mov %r9,-0x3(%rdx) + 438e49: e9 02 05 00 00 jmpq 439350 <__strcpy_ssse3+0x15e0> + 438e4e: 66 90 xchg %ax,%ax + 438e50: 0f 28 49 f4 movaps -0xc(%rcx),%xmm1 + 438e54: 0f 28 51 04 movaps 0x4(%rcx),%xmm2 + 438e58: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 438e5c: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438e60: 0f 28 da movaps %xmm2,%xmm3 + 438e63: 48 85 c0 test %rax,%rax + 438e66: 0f 85 0e 01 00 00 jne 438f7a <__strcpy_ssse3+0x120a> + 438e6c: 66 0f 3a 0f d1 0c palignr $0xc,%xmm1,%xmm2 + 438e72: 0f 29 12 movaps %xmm2,(%rdx) + 438e75: 0f 28 51 14 movaps 0x14(%rcx),%xmm2 + 438e79: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 438e7d: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438e81: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438e85: 48 8d 49 10 lea 0x10(%rcx),%rcx + 438e89: 0f 28 ca movaps %xmm2,%xmm1 + 438e8c: 48 85 c0 test %rax,%rax + 438e8f: 0f 85 e5 00 00 00 jne 438f7a <__strcpy_ssse3+0x120a> + 438e95: 66 0f 3a 0f d3 0c palignr $0xc,%xmm3,%xmm2 + 438e9b: 0f 29 12 movaps %xmm2,(%rdx) + 438e9e: 0f 28 51 14 movaps 0x14(%rcx),%xmm2 + 438ea2: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 438ea6: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438eaa: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438eae: 48 8d 49 10 lea 0x10(%rcx),%rcx + 438eb2: 0f 28 da movaps %xmm2,%xmm3 + 438eb5: 48 85 c0 test %rax,%rax + 438eb8: 0f 85 bc 00 00 00 jne 438f7a <__strcpy_ssse3+0x120a> + 438ebe: 66 0f 3a 0f d1 0c palignr $0xc,%xmm1,%xmm2 + 438ec4: 0f 29 12 movaps %xmm2,(%rdx) + 438ec7: 0f 28 51 14 movaps 0x14(%rcx),%xmm2 + 438ecb: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 438ecf: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438ed3: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438ed7: 48 8d 49 10 lea 0x10(%rcx),%rcx + 438edb: 48 85 c0 test %rax,%rax + 438ede: 0f 85 96 00 00 00 jne 438f7a <__strcpy_ssse3+0x120a> + 438ee4: 66 0f 3a 0f d3 0c palignr $0xc,%xmm3,%xmm2 + 438eea: 0f 29 12 movaps %xmm2,(%rdx) + 438eed: 48 8d 49 14 lea 0x14(%rcx),%rcx + 438ef1: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438ef5: 48 89 c8 mov %rcx,%rax + 438ef8: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 438efc: 48 29 c8 sub %rcx,%rax + 438eff: 48 8d 49 fc lea -0x4(%rcx),%rcx + 438f03: 48 29 c2 sub %rax,%rdx + 438f06: 0f 28 49 f4 movaps -0xc(%rcx),%xmm1 + 438f0a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 438f10: 0f 28 51 04 movaps 0x4(%rcx),%xmm2 + 438f14: 0f 28 59 14 movaps 0x14(%rcx),%xmm3 + 438f18: 0f 28 f3 movaps %xmm3,%xmm6 + 438f1b: 0f 28 61 24 movaps 0x24(%rcx),%xmm4 + 438f1f: 0f 28 fc movaps %xmm4,%xmm7 + 438f22: 0f 28 69 34 movaps 0x34(%rcx),%xmm5 + 438f26: 66 0f da f2 pminub %xmm2,%xmm6 + 438f2a: 66 0f da fd pminub %xmm5,%xmm7 + 438f2e: 66 0f da fe pminub %xmm6,%xmm7 + 438f32: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 438f36: 66 0f d7 c7 pmovmskb %xmm7,%eax + 438f3a: 0f 28 fd movaps %xmm5,%xmm7 + 438f3d: 66 0f 3a 0f ec 0c palignr $0xc,%xmm4,%xmm5 + 438f43: 48 85 c0 test %rax,%rax + 438f46: 66 0f 3a 0f e3 0c palignr $0xc,%xmm3,%xmm4 + 438f4c: 0f 85 06 ff ff ff jne 438e58 <__strcpy_ssse3+0x10e8> + 438f52: 66 0f 3a 0f da 0c palignr $0xc,%xmm2,%xmm3 + 438f58: 48 8d 49 40 lea 0x40(%rcx),%rcx + 438f5c: 66 0f 3a 0f d1 0c palignr $0xc,%xmm1,%xmm2 + 438f62: 0f 28 cf movaps %xmm7,%xmm1 + 438f65: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) + 438f69: 0f 29 62 20 movaps %xmm4,0x20(%rdx) + 438f6d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) + 438f71: 0f 29 12 movaps %xmm2,(%rdx) + 438f74: 48 8d 52 40 lea 0x40(%rdx),%rdx + 438f78: eb 96 jmp 438f10 <__strcpy_ssse3+0x11a0> + 438f7a: 44 8b 09 mov (%rcx),%r9d + 438f7d: 48 c7 c6 04 00 00 00 mov $0x4,%rsi + 438f84: 44 89 0a mov %r9d,(%rdx) + 438f87: e9 c4 03 00 00 jmpq 439350 <__strcpy_ssse3+0x15e0> + 438f8c: 0f 1f 40 00 nopl 0x0(%rax) + 438f90: 0f 28 49 f3 movaps -0xd(%rcx),%xmm1 + 438f94: 0f 28 51 03 movaps 0x3(%rcx),%xmm2 + 438f98: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 438f9c: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438fa0: 0f 28 da movaps %xmm2,%xmm3 + 438fa3: 48 85 c0 test %rax,%rax + 438fa6: 0f 85 0e 01 00 00 jne 4390ba <__strcpy_ssse3+0x134a> + 438fac: 66 0f 3a 0f d1 0d palignr $0xd,%xmm1,%xmm2 + 438fb2: 0f 29 12 movaps %xmm2,(%rdx) + 438fb5: 0f 28 51 13 movaps 0x13(%rcx),%xmm2 + 438fb9: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 438fbd: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438fc1: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438fc5: 48 8d 49 10 lea 0x10(%rcx),%rcx + 438fc9: 0f 28 ca movaps %xmm2,%xmm1 + 438fcc: 48 85 c0 test %rax,%rax + 438fcf: 0f 85 e5 00 00 00 jne 4390ba <__strcpy_ssse3+0x134a> + 438fd5: 66 0f 3a 0f d3 0d palignr $0xd,%xmm3,%xmm2 + 438fdb: 0f 29 12 movaps %xmm2,(%rdx) + 438fde: 0f 28 51 13 movaps 0x13(%rcx),%xmm2 + 438fe2: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 438fe6: 48 8d 52 10 lea 0x10(%rdx),%rdx + 438fea: 66 0f d7 c0 pmovmskb %xmm0,%eax + 438fee: 48 8d 49 10 lea 0x10(%rcx),%rcx + 438ff2: 0f 28 da movaps %xmm2,%xmm3 + 438ff5: 48 85 c0 test %rax,%rax + 438ff8: 0f 85 bc 00 00 00 jne 4390ba <__strcpy_ssse3+0x134a> + 438ffe: 66 0f 3a 0f d1 0d palignr $0xd,%xmm1,%xmm2 + 439004: 0f 29 12 movaps %xmm2,(%rdx) + 439007: 0f 28 51 13 movaps 0x13(%rcx),%xmm2 + 43900b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43900f: 48 8d 52 10 lea 0x10(%rdx),%rdx + 439013: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439017: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43901b: 48 85 c0 test %rax,%rax + 43901e: 0f 85 96 00 00 00 jne 4390ba <__strcpy_ssse3+0x134a> + 439024: 66 0f 3a 0f d3 0d palignr $0xd,%xmm3,%xmm2 + 43902a: 0f 29 12 movaps %xmm2,(%rdx) + 43902d: 48 8d 49 13 lea 0x13(%rcx),%rcx + 439031: 48 8d 52 10 lea 0x10(%rdx),%rdx + 439035: 48 89 c8 mov %rcx,%rax + 439038: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 43903c: 48 29 c8 sub %rcx,%rax + 43903f: 48 8d 49 fd lea -0x3(%rcx),%rcx + 439043: 48 29 c2 sub %rax,%rdx + 439046: 0f 28 49 f3 movaps -0xd(%rcx),%xmm1 + 43904a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 439050: 0f 28 51 03 movaps 0x3(%rcx),%xmm2 + 439054: 0f 28 59 13 movaps 0x13(%rcx),%xmm3 + 439058: 0f 28 f3 movaps %xmm3,%xmm6 + 43905b: 0f 28 61 23 movaps 0x23(%rcx),%xmm4 + 43905f: 0f 28 fc movaps %xmm4,%xmm7 + 439062: 0f 28 69 33 movaps 0x33(%rcx),%xmm5 + 439066: 66 0f da f2 pminub %xmm2,%xmm6 + 43906a: 66 0f da fd pminub %xmm5,%xmm7 + 43906e: 66 0f da fe pminub %xmm6,%xmm7 + 439072: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 439076: 66 0f d7 c7 pmovmskb %xmm7,%eax + 43907a: 0f 28 fd movaps %xmm5,%xmm7 + 43907d: 66 0f 3a 0f ec 0d palignr $0xd,%xmm4,%xmm5 + 439083: 48 85 c0 test %rax,%rax + 439086: 66 0f 3a 0f e3 0d palignr $0xd,%xmm3,%xmm4 + 43908c: 0f 85 06 ff ff ff jne 438f98 <__strcpy_ssse3+0x1228> + 439092: 66 0f 3a 0f da 0d palignr $0xd,%xmm2,%xmm3 + 439098: 48 8d 49 40 lea 0x40(%rcx),%rcx + 43909c: 66 0f 3a 0f d1 0d palignr $0xd,%xmm1,%xmm2 + 4390a2: 0f 28 cf movaps %xmm7,%xmm1 + 4390a5: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) + 4390a9: 0f 29 62 20 movaps %xmm4,0x20(%rdx) + 4390ad: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) + 4390b1: 0f 29 12 movaps %xmm2,(%rdx) + 4390b4: 48 8d 52 40 lea 0x40(%rdx),%rdx + 4390b8: eb 96 jmp 439050 <__strcpy_ssse3+0x12e0> + 4390ba: 44 8b 49 ff mov -0x1(%rcx),%r9d + 4390be: 48 c7 c6 03 00 00 00 mov $0x3,%rsi + 4390c5: 44 89 4a ff mov %r9d,-0x1(%rdx) + 4390c9: e9 82 02 00 00 jmpq 439350 <__strcpy_ssse3+0x15e0> + 4390ce: 66 90 xchg %ax,%ax + 4390d0: 0f 28 49 f2 movaps -0xe(%rcx),%xmm1 + 4390d4: 0f 28 51 02 movaps 0x2(%rcx),%xmm2 + 4390d8: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 4390dc: 66 0f d7 c0 pmovmskb %xmm0,%eax + 4390e0: 0f 28 da movaps %xmm2,%xmm3 + 4390e3: 48 85 c0 test %rax,%rax + 4390e6: 0f 85 0e 01 00 00 jne 4391fa <__strcpy_ssse3+0x148a> + 4390ec: 66 0f 3a 0f d1 0e palignr $0xe,%xmm1,%xmm2 + 4390f2: 0f 29 12 movaps %xmm2,(%rdx) + 4390f5: 0f 28 51 12 movaps 0x12(%rcx),%xmm2 + 4390f9: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 4390fd: 48 8d 52 10 lea 0x10(%rdx),%rdx + 439101: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439105: 48 8d 49 10 lea 0x10(%rcx),%rcx + 439109: 0f 28 ca movaps %xmm2,%xmm1 + 43910c: 48 85 c0 test %rax,%rax + 43910f: 0f 85 e5 00 00 00 jne 4391fa <__strcpy_ssse3+0x148a> + 439115: 66 0f 3a 0f d3 0e palignr $0xe,%xmm3,%xmm2 + 43911b: 0f 29 12 movaps %xmm2,(%rdx) + 43911e: 0f 28 51 12 movaps 0x12(%rcx),%xmm2 + 439122: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 439126: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43912a: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43912e: 48 8d 49 10 lea 0x10(%rcx),%rcx + 439132: 0f 28 da movaps %xmm2,%xmm3 + 439135: 48 85 c0 test %rax,%rax + 439138: 0f 85 bc 00 00 00 jne 4391fa <__strcpy_ssse3+0x148a> + 43913e: 66 0f 3a 0f d1 0e palignr $0xe,%xmm1,%xmm2 + 439144: 0f 29 12 movaps %xmm2,(%rdx) + 439147: 0f 28 51 12 movaps 0x12(%rcx),%xmm2 + 43914b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43914f: 48 8d 52 10 lea 0x10(%rdx),%rdx + 439153: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439157: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43915b: 48 85 c0 test %rax,%rax + 43915e: 0f 85 96 00 00 00 jne 4391fa <__strcpy_ssse3+0x148a> + 439164: 66 0f 3a 0f d3 0e palignr $0xe,%xmm3,%xmm2 + 43916a: 0f 29 12 movaps %xmm2,(%rdx) + 43916d: 48 8d 49 12 lea 0x12(%rcx),%rcx + 439171: 48 8d 52 10 lea 0x10(%rdx),%rdx + 439175: 48 89 c8 mov %rcx,%rax + 439178: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 43917c: 48 29 c8 sub %rcx,%rax + 43917f: 48 8d 49 fe lea -0x2(%rcx),%rcx + 439183: 48 29 c2 sub %rax,%rdx + 439186: 0f 28 49 f2 movaps -0xe(%rcx),%xmm1 + 43918a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 439190: 0f 28 51 02 movaps 0x2(%rcx),%xmm2 + 439194: 0f 28 59 12 movaps 0x12(%rcx),%xmm3 + 439198: 0f 28 f3 movaps %xmm3,%xmm6 + 43919b: 0f 28 61 22 movaps 0x22(%rcx),%xmm4 + 43919f: 0f 28 fc movaps %xmm4,%xmm7 + 4391a2: 0f 28 69 32 movaps 0x32(%rcx),%xmm5 + 4391a6: 66 0f da f2 pminub %xmm2,%xmm6 + 4391aa: 66 0f da fd pminub %xmm5,%xmm7 + 4391ae: 66 0f da fe pminub %xmm6,%xmm7 + 4391b2: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 4391b6: 66 0f d7 c7 pmovmskb %xmm7,%eax + 4391ba: 0f 28 fd movaps %xmm5,%xmm7 + 4391bd: 66 0f 3a 0f ec 0e palignr $0xe,%xmm4,%xmm5 + 4391c3: 48 85 c0 test %rax,%rax + 4391c6: 66 0f 3a 0f e3 0e palignr $0xe,%xmm3,%xmm4 + 4391cc: 0f 85 06 ff ff ff jne 4390d8 <__strcpy_ssse3+0x1368> + 4391d2: 66 0f 3a 0f da 0e palignr $0xe,%xmm2,%xmm3 + 4391d8: 48 8d 49 40 lea 0x40(%rcx),%rcx + 4391dc: 66 0f 3a 0f d1 0e palignr $0xe,%xmm1,%xmm2 + 4391e2: 0f 28 cf movaps %xmm7,%xmm1 + 4391e5: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) + 4391e9: 0f 29 62 20 movaps %xmm4,0x20(%rdx) + 4391ed: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) + 4391f1: 0f 29 12 movaps %xmm2,(%rdx) + 4391f4: 48 8d 52 40 lea 0x40(%rdx),%rdx + 4391f8: eb 96 jmp 439190 <__strcpy_ssse3+0x1420> + 4391fa: 44 8b 49 fe mov -0x2(%rcx),%r9d + 4391fe: 48 c7 c6 02 00 00 00 mov $0x2,%rsi + 439205: 44 89 4a fe mov %r9d,-0x2(%rdx) + 439209: e9 42 01 00 00 jmpq 439350 <__strcpy_ssse3+0x15e0> + 43920e: 66 90 xchg %ax,%ax + 439210: 0f 28 49 f1 movaps -0xf(%rcx),%xmm1 + 439214: 0f 28 51 01 movaps 0x1(%rcx),%xmm2 + 439218: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43921c: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439220: 0f 28 da movaps %xmm2,%xmm3 + 439223: 48 85 c0 test %rax,%rax + 439226: 0f 85 0e 01 00 00 jne 43933a <__strcpy_ssse3+0x15ca> + 43922c: 66 0f 3a 0f d1 0f palignr $0xf,%xmm1,%xmm2 + 439232: 0f 29 12 movaps %xmm2,(%rdx) + 439235: 0f 28 51 11 movaps 0x11(%rcx),%xmm2 + 439239: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43923d: 48 8d 52 10 lea 0x10(%rdx),%rdx + 439241: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439245: 48 8d 49 10 lea 0x10(%rcx),%rcx + 439249: 0f 28 ca movaps %xmm2,%xmm1 + 43924c: 48 85 c0 test %rax,%rax + 43924f: 0f 85 e5 00 00 00 jne 43933a <__strcpy_ssse3+0x15ca> + 439255: 66 0f 3a 0f d3 0f palignr $0xf,%xmm3,%xmm2 + 43925b: 0f 29 12 movaps %xmm2,(%rdx) + 43925e: 0f 28 51 11 movaps 0x11(%rcx),%xmm2 + 439262: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 439266: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43926a: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43926e: 48 8d 49 10 lea 0x10(%rcx),%rcx + 439272: 0f 28 da movaps %xmm2,%xmm3 + 439275: 48 85 c0 test %rax,%rax + 439278: 0f 85 bc 00 00 00 jne 43933a <__strcpy_ssse3+0x15ca> + 43927e: 66 0f 3a 0f d1 0f palignr $0xf,%xmm1,%xmm2 + 439284: 0f 29 12 movaps %xmm2,(%rdx) + 439287: 0f 28 51 11 movaps 0x11(%rcx),%xmm2 + 43928b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43928f: 48 8d 52 10 lea 0x10(%rdx),%rdx + 439293: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439297: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43929b: 48 85 c0 test %rax,%rax + 43929e: 0f 85 96 00 00 00 jne 43933a <__strcpy_ssse3+0x15ca> + 4392a4: 66 0f 3a 0f d3 0f palignr $0xf,%xmm3,%xmm2 + 4392aa: 0f 29 12 movaps %xmm2,(%rdx) + 4392ad: 48 8d 49 11 lea 0x11(%rcx),%rcx + 4392b1: 48 8d 52 10 lea 0x10(%rdx),%rdx + 4392b5: 48 89 c8 mov %rcx,%rax + 4392b8: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 4392bc: 48 29 c8 sub %rcx,%rax + 4392bf: 48 8d 49 ff lea -0x1(%rcx),%rcx + 4392c3: 48 29 c2 sub %rax,%rdx + 4392c6: 0f 28 49 f1 movaps -0xf(%rcx),%xmm1 + 4392ca: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4392d0: 0f 28 51 01 movaps 0x1(%rcx),%xmm2 + 4392d4: 0f 28 59 11 movaps 0x11(%rcx),%xmm3 + 4392d8: 0f 28 f3 movaps %xmm3,%xmm6 + 4392db: 0f 28 61 21 movaps 0x21(%rcx),%xmm4 + 4392df: 0f 28 fc movaps %xmm4,%xmm7 + 4392e2: 0f 28 69 31 movaps 0x31(%rcx),%xmm5 + 4392e6: 66 0f da f2 pminub %xmm2,%xmm6 + 4392ea: 66 0f da fd pminub %xmm5,%xmm7 + 4392ee: 66 0f da fe pminub %xmm6,%xmm7 + 4392f2: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 4392f6: 66 0f d7 c7 pmovmskb %xmm7,%eax + 4392fa: 0f 28 fd movaps %xmm5,%xmm7 + 4392fd: 66 0f 3a 0f ec 0f palignr $0xf,%xmm4,%xmm5 + 439303: 48 85 c0 test %rax,%rax + 439306: 66 0f 3a 0f e3 0f palignr $0xf,%xmm3,%xmm4 + 43930c: 0f 85 06 ff ff ff jne 439218 <__strcpy_ssse3+0x14a8> + 439312: 66 0f 3a 0f da 0f palignr $0xf,%xmm2,%xmm3 + 439318: 48 8d 49 40 lea 0x40(%rcx),%rcx + 43931c: 66 0f 3a 0f d1 0f palignr $0xf,%xmm1,%xmm2 + 439322: 0f 28 cf movaps %xmm7,%xmm1 + 439325: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) + 439329: 0f 29 62 20 movaps %xmm4,0x20(%rdx) + 43932d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) + 439331: 0f 29 12 movaps %xmm2,(%rdx) + 439334: 48 8d 52 40 lea 0x40(%rdx),%rdx + 439338: eb 96 jmp 4392d0 <__strcpy_ssse3+0x1560> + 43933a: 44 8b 49 fd mov -0x3(%rcx),%r9d + 43933e: 48 c7 c6 01 00 00 00 mov $0x1,%rsi + 439345: 44 89 4a fd mov %r9d,-0x3(%rdx) + 439349: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 439350: 48 01 f2 add %rsi,%rdx + 439353: 48 01 f1 add %rsi,%rcx + 439356: 84 c0 test %al,%al + 439358: 74 56 je 4393b0 <__strcpy_ssse3+0x1640> + 43935a: a8 01 test $0x1,%al + 43935c: 0f 85 ae 00 00 00 jne 439410 <__strcpy_ssse3+0x16a0> + 439362: a8 02 test $0x2,%al + 439364: 0f 85 b6 00 00 00 jne 439420 <__strcpy_ssse3+0x16b0> + 43936a: a8 04 test $0x4,%al + 43936c: 0f 85 be 00 00 00 jne 439430 <__strcpy_ssse3+0x16c0> + 439372: a8 08 test $0x8,%al + 439374: 0f 85 c6 00 00 00 jne 439440 <__strcpy_ssse3+0x16d0> + 43937a: a8 10 test $0x10,%al + 43937c: 0f 85 ce 00 00 00 jne 439450 <__strcpy_ssse3+0x16e0> + 439382: a8 20 test $0x20,%al + 439384: 0f 85 d6 00 00 00 jne 439460 <__strcpy_ssse3+0x16f0> + 43938a: a8 40 test $0x40,%al + 43938c: 0f 85 de 00 00 00 jne 439470 <__strcpy_ssse3+0x1700> + 439392: 0f 1f 40 00 nopl 0x0(%rax) + 439396: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43939d: 00 00 00 + 4393a0: 48 8b 01 mov (%rcx),%rax + 4393a3: 48 89 02 mov %rax,(%rdx) + 4393a6: 48 89 f8 mov %rdi,%rax + 4393a9: c3 retq + 4393aa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4393b0: f6 c4 01 test $0x1,%ah + 4393b3: 0f 85 c7 00 00 00 jne 439480 <__strcpy_ssse3+0x1710> + 4393b9: f6 c4 02 test $0x2,%ah + 4393bc: 0f 85 ce 00 00 00 jne 439490 <__strcpy_ssse3+0x1720> + 4393c2: f6 c4 04 test $0x4,%ah + 4393c5: 0f 85 d5 00 00 00 jne 4394a0 <__strcpy_ssse3+0x1730> + 4393cb: f6 c4 08 test $0x8,%ah + 4393ce: 0f 85 dc 00 00 00 jne 4394b0 <__strcpy_ssse3+0x1740> + 4393d4: f6 c4 10 test $0x10,%ah + 4393d7: 0f 85 e3 00 00 00 jne 4394c0 <__strcpy_ssse3+0x1750> + 4393dd: f6 c4 20 test $0x20,%ah + 4393e0: 0f 85 fa 00 00 00 jne 4394e0 <__strcpy_ssse3+0x1770> + 4393e6: f6 c4 40 test $0x40,%ah + 4393e9: 0f 85 11 01 00 00 jne 439500 <__strcpy_ssse3+0x1790> + 4393ef: 90 nop + 4393f0: 48 8b 01 mov (%rcx),%rax + 4393f3: 48 89 02 mov %rax,(%rdx) + 4393f6: 48 8b 41 08 mov 0x8(%rcx),%rax + 4393fa: 48 89 42 08 mov %rax,0x8(%rdx) + 4393fe: 48 89 f8 mov %rdi,%rax + 439401: c3 retq + 439402: 0f 1f 40 00 nopl 0x0(%rax) + 439406: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43940d: 00 00 00 + 439410: 8a 01 mov (%rcx),%al + 439412: 88 02 mov %al,(%rdx) + 439414: 48 89 f8 mov %rdi,%rax + 439417: c3 retq + 439418: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 43941f: 00 + 439420: 66 8b 01 mov (%rcx),%ax + 439423: 66 89 02 mov %ax,(%rdx) + 439426: 48 89 f8 mov %rdi,%rax + 439429: c3 retq + 43942a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 439430: 66 8b 01 mov (%rcx),%ax + 439433: 66 89 02 mov %ax,(%rdx) + 439436: 8a 41 02 mov 0x2(%rcx),%al + 439439: 88 42 02 mov %al,0x2(%rdx) + 43943c: 48 89 f8 mov %rdi,%rax + 43943f: c3 retq + 439440: 8b 01 mov (%rcx),%eax + 439442: 89 02 mov %eax,(%rdx) + 439444: 48 89 f8 mov %rdi,%rax + 439447: c3 retq + 439448: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 43944f: 00 + 439450: 8b 01 mov (%rcx),%eax + 439452: 89 02 mov %eax,(%rdx) + 439454: 8a 41 04 mov 0x4(%rcx),%al + 439457: 88 42 04 mov %al,0x4(%rdx) + 43945a: 48 89 f8 mov %rdi,%rax + 43945d: c3 retq + 43945e: 66 90 xchg %ax,%ax + 439460: 8b 01 mov (%rcx),%eax + 439462: 89 02 mov %eax,(%rdx) + 439464: 66 8b 41 04 mov 0x4(%rcx),%ax + 439468: 66 89 42 04 mov %ax,0x4(%rdx) + 43946c: 48 89 f8 mov %rdi,%rax + 43946f: c3 retq + 439470: 8b 01 mov (%rcx),%eax + 439472: 89 02 mov %eax,(%rdx) + 439474: 8b 41 03 mov 0x3(%rcx),%eax + 439477: 89 42 03 mov %eax,0x3(%rdx) + 43947a: 48 89 f8 mov %rdi,%rax + 43947d: c3 retq + 43947e: 66 90 xchg %ax,%ax + 439480: 48 8b 01 mov (%rcx),%rax + 439483: 48 89 02 mov %rax,(%rdx) + 439486: 8b 41 05 mov 0x5(%rcx),%eax + 439489: 89 42 05 mov %eax,0x5(%rdx) + 43948c: 48 89 f8 mov %rdi,%rax + 43948f: c3 retq + 439490: 48 8b 01 mov (%rcx),%rax + 439493: 48 89 02 mov %rax,(%rdx) + 439496: 8b 41 06 mov 0x6(%rcx),%eax + 439499: 89 42 06 mov %eax,0x6(%rdx) + 43949c: 48 89 f8 mov %rdi,%rax + 43949f: c3 retq + 4394a0: 48 8b 01 mov (%rcx),%rax + 4394a3: 48 89 02 mov %rax,(%rdx) + 4394a6: 8b 41 07 mov 0x7(%rcx),%eax + 4394a9: 89 42 07 mov %eax,0x7(%rdx) + 4394ac: 48 89 f8 mov %rdi,%rax + 4394af: c3 retq + 4394b0: 48 8b 01 mov (%rcx),%rax + 4394b3: 48 89 02 mov %rax,(%rdx) + 4394b6: 8b 41 08 mov 0x8(%rcx),%eax + 4394b9: 89 42 08 mov %eax,0x8(%rdx) + 4394bc: 48 89 f8 mov %rdi,%rax + 4394bf: c3 retq + 4394c0: 48 8b 01 mov (%rcx),%rax + 4394c3: 48 89 02 mov %rax,(%rdx) + 4394c6: 48 8b 41 05 mov 0x5(%rcx),%rax + 4394ca: 48 89 42 05 mov %rax,0x5(%rdx) + 4394ce: 48 89 f8 mov %rdi,%rax + 4394d1: c3 retq + 4394d2: 0f 1f 40 00 nopl 0x0(%rax) + 4394d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4394dd: 00 00 00 + 4394e0: 48 8b 01 mov (%rcx),%rax + 4394e3: 48 89 02 mov %rax,(%rdx) + 4394e6: 48 8b 41 06 mov 0x6(%rcx),%rax + 4394ea: 48 89 42 06 mov %rax,0x6(%rdx) + 4394ee: 48 89 f8 mov %rdi,%rax + 4394f1: c3 retq + 4394f2: 0f 1f 40 00 nopl 0x0(%rax) + 4394f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4394fd: 00 00 00 + 439500: 48 8b 01 mov (%rcx),%rax + 439503: 48 89 02 mov %rax,(%rdx) + 439506: 48 8b 41 07 mov 0x7(%rcx),%rax + 43950a: 48 89 42 07 mov %rax,0x7(%rdx) + 43950e: 48 89 f8 mov %rdi,%rax + 439511: c3 retq + 439512: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 439519: 00 00 00 + 43951c: 0f 1f 40 00 nopl 0x0(%rax) + +0000000000439520 <__stpcpy_ssse3>: + 439520: 48 89 f1 mov %rsi,%rcx + 439523: 48 89 fa mov %rdi,%rdx + 439526: 80 39 00 cmpb $0x0,(%rcx) + 439529: 0f 84 91 16 00 00 je 43abc0 <__stpcpy_ssse3+0x16a0> + 43952f: 80 79 01 00 cmpb $0x0,0x1(%rcx) + 439533: 0f 84 97 16 00 00 je 43abd0 <__stpcpy_ssse3+0x16b0> + 439539: 80 79 02 00 cmpb $0x0,0x2(%rcx) + 43953d: 0f 84 9d 16 00 00 je 43abe0 <__stpcpy_ssse3+0x16c0> + 439543: 80 79 03 00 cmpb $0x0,0x3(%rcx) + 439547: 0f 84 b3 16 00 00 je 43ac00 <__stpcpy_ssse3+0x16e0> + 43954d: 80 79 04 00 cmpb $0x0,0x4(%rcx) + 439551: 0f 84 b9 16 00 00 je 43ac10 <__stpcpy_ssse3+0x16f0> + 439557: 80 79 05 00 cmpb $0x0,0x5(%rcx) + 43955b: 0f 84 bf 16 00 00 je 43ac20 <__stpcpy_ssse3+0x1700> + 439561: 80 79 06 00 cmpb $0x0,0x6(%rcx) + 439565: 0f 84 d5 16 00 00 je 43ac40 <__stpcpy_ssse3+0x1720> + 43956b: 80 79 07 00 cmpb $0x0,0x7(%rcx) + 43956f: 0f 84 db 15 00 00 je 43ab50 <__stpcpy_ssse3+0x1630> + 439575: 80 79 08 00 cmpb $0x0,0x8(%rcx) + 439579: 0f 84 d1 16 00 00 je 43ac50 <__stpcpy_ssse3+0x1730> + 43957f: 80 79 09 00 cmpb $0x0,0x9(%rcx) + 439583: 0f 84 e7 16 00 00 je 43ac70 <__stpcpy_ssse3+0x1750> + 439589: 80 79 0a 00 cmpb $0x0,0xa(%rcx) + 43958d: 0f 84 fd 16 00 00 je 43ac90 <__stpcpy_ssse3+0x1770> + 439593: 80 79 0b 00 cmpb $0x0,0xb(%rcx) + 439597: 0f 84 13 17 00 00 je 43acb0 <__stpcpy_ssse3+0x1790> + 43959d: 80 79 0c 00 cmpb $0x0,0xc(%rcx) + 4395a1: 0f 84 29 17 00 00 je 43acd0 <__stpcpy_ssse3+0x17b0> + 4395a7: 80 79 0d 00 cmpb $0x0,0xd(%rcx) + 4395ab: 0f 84 3f 17 00 00 je 43acf0 <__stpcpy_ssse3+0x17d0> + 4395b1: 80 79 0e 00 cmpb $0x0,0xe(%rcx) + 4395b5: 0f 84 55 17 00 00 je 43ad10 <__stpcpy_ssse3+0x17f0> + 4395bb: 80 79 0f 00 cmpb $0x0,0xf(%rcx) + 4395bf: 0f 84 db 15 00 00 je 43aba0 <__stpcpy_ssse3+0x1680> + 4395c5: 48 8d 71 10 lea 0x10(%rcx),%rsi + 4395c9: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi + 4395cd: 66 0f ef c0 pxor %xmm0,%xmm0 + 4395d1: 4c 8b 09 mov (%rcx),%r9 + 4395d4: 4c 89 0a mov %r9,(%rdx) + 4395d7: 66 0f 74 06 pcmpeqb (%rsi),%xmm0 + 4395db: 4c 8b 49 08 mov 0x8(%rcx),%r9 + 4395df: 4c 89 4a 08 mov %r9,0x8(%rdx) + 4395e3: 66 0f d7 c0 pmovmskb %xmm0,%eax + 4395e7: 48 29 ce sub %rcx,%rsi + 4395ea: 48 85 c0 test %rax,%rax + 4395ed: 0f 85 0d 15 00 00 jne 43ab00 <__stpcpy_ssse3+0x15e0> + 4395f3: 48 89 d0 mov %rdx,%rax + 4395f6: 48 8d 52 10 lea 0x10(%rdx),%rdx + 4395fa: 48 83 e2 f0 and $0xfffffffffffffff0,%rdx + 4395fe: 48 29 d0 sub %rdx,%rax + 439601: 48 29 c1 sub %rax,%rcx + 439604: 48 89 c8 mov %rcx,%rax + 439607: 48 83 e0 0f and $0xf,%rax + 43960b: 48 c7 c6 00 00 00 00 mov $0x0,%rsi + 439612: 0f 84 8e 00 00 00 je 4396a6 <__stpcpy_ssse3+0x186> + 439618: 48 83 f8 08 cmp $0x8,%rax + 43961c: 73 41 jae 43965f <__stpcpy_ssse3+0x13f> + 43961e: 48 83 f8 01 cmp $0x1,%rax + 439622: 0f 84 f8 01 00 00 je 439820 <__stpcpy_ssse3+0x300> + 439628: 48 83 f8 02 cmp $0x2,%rax + 43962c: 0f 84 2e 03 00 00 je 439960 <__stpcpy_ssse3+0x440> + 439632: 48 83 f8 03 cmp $0x3,%rax + 439636: 0f 84 64 04 00 00 je 439aa0 <__stpcpy_ssse3+0x580> + 43963c: 48 83 f8 04 cmp $0x4,%rax + 439640: 0f 84 9a 05 00 00 je 439be0 <__stpcpy_ssse3+0x6c0> + 439646: 48 83 f8 05 cmp $0x5,%rax + 43964a: 0f 84 d0 06 00 00 je 439d20 <__stpcpy_ssse3+0x800> + 439650: 48 83 f8 06 cmp $0x6,%rax + 439654: 0f 84 06 08 00 00 je 439e60 <__stpcpy_ssse3+0x940> + 43965a: e9 51 09 00 00 jmpq 439fb0 <__stpcpy_ssse3+0xa90> + 43965f: 0f 84 9b 0a 00 00 je 43a100 <__stpcpy_ssse3+0xbe0> + 439665: 48 83 f8 09 cmp $0x9,%rax + 439669: 0f 84 d1 0b 00 00 je 43a240 <__stpcpy_ssse3+0xd20> + 43966f: 48 83 f8 0a cmp $0xa,%rax + 439673: 0f 84 07 0d 00 00 je 43a380 <__stpcpy_ssse3+0xe60> + 439679: 48 83 f8 0b cmp $0xb,%rax + 43967d: 0f 84 3d 0e 00 00 je 43a4c0 <__stpcpy_ssse3+0xfa0> + 439683: 48 83 f8 0c cmp $0xc,%rax + 439687: 0f 84 73 0f 00 00 je 43a600 <__stpcpy_ssse3+0x10e0> + 43968d: 48 83 f8 0d cmp $0xd,%rax + 439691: 0f 84 a9 10 00 00 je 43a740 <__stpcpy_ssse3+0x1220> + 439697: 48 83 f8 0e cmp $0xe,%rax + 43969b: 0f 84 df 11 00 00 je 43a880 <__stpcpy_ssse3+0x1360> + 4396a1: e9 1a 13 00 00 jmpq 43a9c0 <__stpcpy_ssse3+0x14a0> + 4396a6: 0f 28 09 movaps (%rcx),%xmm1 + 4396a9: 0f 28 51 10 movaps 0x10(%rcx),%xmm2 + 4396ad: 0f 29 0a movaps %xmm1,(%rdx) + 4396b0: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 4396b4: 66 0f d7 c0 pmovmskb %xmm0,%eax + 4396b8: 48 8d 76 10 lea 0x10(%rsi),%rsi + 4396bc: 48 85 c0 test %rax,%rax + 4396bf: 0f 85 3b 14 00 00 jne 43ab00 <__stpcpy_ssse3+0x15e0> + 4396c5: 0f 28 5c 31 10 movaps 0x10(%rcx,%rsi,1),%xmm3 + 4396ca: 0f 29 14 32 movaps %xmm2,(%rdx,%rsi,1) + 4396ce: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 4396d2: 66 0f d7 c0 pmovmskb %xmm0,%eax + 4396d6: 48 8d 76 10 lea 0x10(%rsi),%rsi + 4396da: 48 85 c0 test %rax,%rax + 4396dd: 0f 85 1d 14 00 00 jne 43ab00 <__stpcpy_ssse3+0x15e0> + 4396e3: 0f 28 64 31 10 movaps 0x10(%rcx,%rsi,1),%xmm4 + 4396e8: 0f 29 1c 32 movaps %xmm3,(%rdx,%rsi,1) + 4396ec: 66 0f 74 c4 pcmpeqb %xmm4,%xmm0 + 4396f0: 66 0f d7 c0 pmovmskb %xmm0,%eax + 4396f4: 48 8d 76 10 lea 0x10(%rsi),%rsi + 4396f8: 48 85 c0 test %rax,%rax + 4396fb: 0f 85 ff 13 00 00 jne 43ab00 <__stpcpy_ssse3+0x15e0> + 439701: 0f 28 4c 31 10 movaps 0x10(%rcx,%rsi,1),%xmm1 + 439706: 0f 29 24 32 movaps %xmm4,(%rdx,%rsi,1) + 43970a: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 43970e: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439712: 48 8d 76 10 lea 0x10(%rsi),%rsi + 439716: 48 85 c0 test %rax,%rax + 439719: 0f 85 e1 13 00 00 jne 43ab00 <__stpcpy_ssse3+0x15e0> + 43971f: 0f 28 54 31 10 movaps 0x10(%rcx,%rsi,1),%xmm2 + 439724: 0f 29 0c 32 movaps %xmm1,(%rdx,%rsi,1) + 439728: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43972c: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439730: 48 8d 76 10 lea 0x10(%rsi),%rsi + 439734: 48 85 c0 test %rax,%rax + 439737: 0f 85 c3 13 00 00 jne 43ab00 <__stpcpy_ssse3+0x15e0> + 43973d: 0f 28 5c 31 10 movaps 0x10(%rcx,%rsi,1),%xmm3 + 439742: 0f 29 14 32 movaps %xmm2,(%rdx,%rsi,1) + 439746: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 43974a: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43974e: 48 8d 76 10 lea 0x10(%rsi),%rsi + 439752: 48 85 c0 test %rax,%rax + 439755: 0f 85 a5 13 00 00 jne 43ab00 <__stpcpy_ssse3+0x15e0> + 43975b: 0f 29 1c 32 movaps %xmm3,(%rdx,%rsi,1) + 43975f: 48 89 c8 mov %rcx,%rax + 439762: 48 8d 4c 31 10 lea 0x10(%rcx,%rsi,1),%rcx + 439767: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 43976b: 48 29 c8 sub %rcx,%rax + 43976e: 48 29 c2 sub %rax,%rdx + 439771: 48 c7 c6 c0 ff ff ff mov $0xffffffffffffffc0,%rsi + 439778: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 43977f: 00 + 439780: 0f 28 11 movaps (%rcx),%xmm2 + 439783: 0f 28 e2 movaps %xmm2,%xmm4 + 439786: 0f 28 69 10 movaps 0x10(%rcx),%xmm5 + 43978a: 0f 28 59 20 movaps 0x20(%rcx),%xmm3 + 43978e: 0f 28 f3 movaps %xmm3,%xmm6 + 439791: 0f 28 79 30 movaps 0x30(%rcx),%xmm7 + 439795: 66 0f da d5 pminub %xmm5,%xmm2 + 439799: 66 0f da df pminub %xmm7,%xmm3 + 43979d: 66 0f da da pminub %xmm2,%xmm3 + 4397a1: 66 0f 74 d8 pcmpeqb %xmm0,%xmm3 + 4397a5: 66 0f d7 c3 pmovmskb %xmm3,%eax + 4397a9: 48 8d 52 40 lea 0x40(%rdx),%rdx + 4397ad: 48 8d 49 40 lea 0x40(%rcx),%rcx + 4397b1: 48 85 c0 test %rax,%rax + 4397b4: 75 12 jne 4397c8 <__stpcpy_ssse3+0x2a8> + 4397b6: 0f 29 62 c0 movaps %xmm4,-0x40(%rdx) + 4397ba: 0f 29 6a d0 movaps %xmm5,-0x30(%rdx) + 4397be: 0f 29 72 e0 movaps %xmm6,-0x20(%rdx) + 4397c2: 0f 29 7a f0 movaps %xmm7,-0x10(%rdx) + 4397c6: eb b8 jmp 439780 <__stpcpy_ssse3+0x260> + 4397c8: 66 0f 74 c4 pcmpeqb %xmm4,%xmm0 + 4397cc: 66 0f d7 c0 pmovmskb %xmm0,%eax + 4397d0: 48 85 c0 test %rax,%rax + 4397d3: 0f 85 27 13 00 00 jne 43ab00 <__stpcpy_ssse3+0x15e0> + 4397d9: 66 0f 74 c5 pcmpeqb %xmm5,%xmm0 + 4397dd: 66 0f d7 c0 pmovmskb %xmm0,%eax + 4397e1: 0f 29 62 c0 movaps %xmm4,-0x40(%rdx) + 4397e5: 48 85 c0 test %rax,%rax + 4397e8: 48 8d 76 10 lea 0x10(%rsi),%rsi + 4397ec: 0f 85 0e 13 00 00 jne 43ab00 <__stpcpy_ssse3+0x15e0> + 4397f2: 66 0f 74 c6 pcmpeqb %xmm6,%xmm0 + 4397f6: 66 0f d7 c0 pmovmskb %xmm0,%eax + 4397fa: 0f 29 6a d0 movaps %xmm5,-0x30(%rdx) + 4397fe: 48 85 c0 test %rax,%rax + 439801: 48 8d 76 10 lea 0x10(%rsi),%rsi + 439805: 0f 85 f5 12 00 00 jne 43ab00 <__stpcpy_ssse3+0x15e0> + 43980b: 0f 29 72 e0 movaps %xmm6,-0x20(%rdx) + 43980f: 66 0f 74 c7 pcmpeqb %xmm7,%xmm0 + 439813: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439817: 48 8d 76 10 lea 0x10(%rsi),%rsi + 43981b: e9 e0 12 00 00 jmpq 43ab00 <__stpcpy_ssse3+0x15e0> + 439820: 0f 28 49 ff movaps -0x1(%rcx),%xmm1 + 439824: 0f 28 51 0f movaps 0xf(%rcx),%xmm2 + 439828: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43982c: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439830: 0f 28 da movaps %xmm2,%xmm3 + 439833: 48 85 c0 test %rax,%rax + 439836: 0f 85 0e 01 00 00 jne 43994a <__stpcpy_ssse3+0x42a> + 43983c: 66 0f 3a 0f d1 01 palignr $0x1,%xmm1,%xmm2 + 439842: 0f 29 12 movaps %xmm2,(%rdx) + 439845: 0f 28 51 1f movaps 0x1f(%rcx),%xmm2 + 439849: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43984d: 48 8d 52 10 lea 0x10(%rdx),%rdx + 439851: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439855: 48 8d 49 10 lea 0x10(%rcx),%rcx + 439859: 0f 28 ca movaps %xmm2,%xmm1 + 43985c: 48 85 c0 test %rax,%rax + 43985f: 0f 85 e5 00 00 00 jne 43994a <__stpcpy_ssse3+0x42a> + 439865: 66 0f 3a 0f d3 01 palignr $0x1,%xmm3,%xmm2 + 43986b: 0f 29 12 movaps %xmm2,(%rdx) + 43986e: 0f 28 51 1f movaps 0x1f(%rcx),%xmm2 + 439872: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 439876: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43987a: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43987e: 48 8d 49 10 lea 0x10(%rcx),%rcx + 439882: 0f 28 da movaps %xmm2,%xmm3 + 439885: 48 85 c0 test %rax,%rax + 439888: 0f 85 bc 00 00 00 jne 43994a <__stpcpy_ssse3+0x42a> + 43988e: 66 0f 3a 0f d1 01 palignr $0x1,%xmm1,%xmm2 + 439894: 0f 29 12 movaps %xmm2,(%rdx) + 439897: 0f 28 51 1f movaps 0x1f(%rcx),%xmm2 + 43989b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43989f: 48 8d 52 10 lea 0x10(%rdx),%rdx + 4398a3: 66 0f d7 c0 pmovmskb %xmm0,%eax + 4398a7: 48 8d 49 10 lea 0x10(%rcx),%rcx + 4398ab: 48 85 c0 test %rax,%rax + 4398ae: 0f 85 96 00 00 00 jne 43994a <__stpcpy_ssse3+0x42a> + 4398b4: 66 0f 3a 0f d3 01 palignr $0x1,%xmm3,%xmm2 + 4398ba: 0f 29 12 movaps %xmm2,(%rdx) + 4398bd: 48 8d 49 1f lea 0x1f(%rcx),%rcx + 4398c1: 48 8d 52 10 lea 0x10(%rdx),%rdx + 4398c5: 48 89 c8 mov %rcx,%rax + 4398c8: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 4398cc: 48 29 c8 sub %rcx,%rax + 4398cf: 48 8d 49 f1 lea -0xf(%rcx),%rcx + 4398d3: 48 29 c2 sub %rax,%rdx + 4398d6: 0f 28 49 ff movaps -0x1(%rcx),%xmm1 + 4398da: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4398e0: 0f 28 51 0f movaps 0xf(%rcx),%xmm2 + 4398e4: 0f 28 59 1f movaps 0x1f(%rcx),%xmm3 + 4398e8: 0f 28 f3 movaps %xmm3,%xmm6 + 4398eb: 0f 28 61 2f movaps 0x2f(%rcx),%xmm4 + 4398ef: 0f 28 fc movaps %xmm4,%xmm7 + 4398f2: 0f 28 69 3f movaps 0x3f(%rcx),%xmm5 + 4398f6: 66 0f da f2 pminub %xmm2,%xmm6 + 4398fa: 66 0f da fd pminub %xmm5,%xmm7 + 4398fe: 66 0f da fe pminub %xmm6,%xmm7 + 439902: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 439906: 66 0f d7 c7 pmovmskb %xmm7,%eax + 43990a: 0f 28 fd movaps %xmm5,%xmm7 + 43990d: 66 0f 3a 0f ec 01 palignr $0x1,%xmm4,%xmm5 + 439913: 48 85 c0 test %rax,%rax + 439916: 66 0f 3a 0f e3 01 palignr $0x1,%xmm3,%xmm4 + 43991c: 0f 85 06 ff ff ff jne 439828 <__stpcpy_ssse3+0x308> + 439922: 66 0f 3a 0f da 01 palignr $0x1,%xmm2,%xmm3 + 439928: 48 8d 49 40 lea 0x40(%rcx),%rcx + 43992c: 66 0f 3a 0f d1 01 palignr $0x1,%xmm1,%xmm2 + 439932: 0f 28 cf movaps %xmm7,%xmm1 + 439935: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) + 439939: 0f 29 62 20 movaps %xmm4,0x20(%rdx) + 43993d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) + 439941: 0f 29 12 movaps %xmm2,(%rdx) + 439944: 48 8d 52 40 lea 0x40(%rdx),%rdx + 439948: eb 96 jmp 4398e0 <__stpcpy_ssse3+0x3c0> + 43994a: f3 0f 6f 49 ff movdqu -0x1(%rcx),%xmm1 + 43994f: 48 c7 c6 0f 00 00 00 mov $0xf,%rsi + 439956: f3 0f 7f 4a ff movdqu %xmm1,-0x1(%rdx) + 43995b: e9 a0 11 00 00 jmpq 43ab00 <__stpcpy_ssse3+0x15e0> + 439960: 0f 28 49 fe movaps -0x2(%rcx),%xmm1 + 439964: 0f 28 51 0e movaps 0xe(%rcx),%xmm2 + 439968: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43996c: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439970: 0f 28 da movaps %xmm2,%xmm3 + 439973: 48 85 c0 test %rax,%rax + 439976: 0f 85 0e 01 00 00 jne 439a8a <__stpcpy_ssse3+0x56a> + 43997c: 66 0f 3a 0f d1 02 palignr $0x2,%xmm1,%xmm2 + 439982: 0f 29 12 movaps %xmm2,(%rdx) + 439985: 0f 28 51 1e movaps 0x1e(%rcx),%xmm2 + 439989: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43998d: 48 8d 52 10 lea 0x10(%rdx),%rdx + 439991: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439995: 48 8d 49 10 lea 0x10(%rcx),%rcx + 439999: 0f 28 ca movaps %xmm2,%xmm1 + 43999c: 48 85 c0 test %rax,%rax + 43999f: 0f 85 e5 00 00 00 jne 439a8a <__stpcpy_ssse3+0x56a> + 4399a5: 66 0f 3a 0f d3 02 palignr $0x2,%xmm3,%xmm2 + 4399ab: 0f 29 12 movaps %xmm2,(%rdx) + 4399ae: 0f 28 51 1e movaps 0x1e(%rcx),%xmm2 + 4399b2: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 4399b6: 48 8d 52 10 lea 0x10(%rdx),%rdx + 4399ba: 66 0f d7 c0 pmovmskb %xmm0,%eax + 4399be: 48 8d 49 10 lea 0x10(%rcx),%rcx + 4399c2: 0f 28 da movaps %xmm2,%xmm3 + 4399c5: 48 85 c0 test %rax,%rax + 4399c8: 0f 85 bc 00 00 00 jne 439a8a <__stpcpy_ssse3+0x56a> + 4399ce: 66 0f 3a 0f d1 02 palignr $0x2,%xmm1,%xmm2 + 4399d4: 0f 29 12 movaps %xmm2,(%rdx) + 4399d7: 0f 28 51 1e movaps 0x1e(%rcx),%xmm2 + 4399db: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 4399df: 48 8d 52 10 lea 0x10(%rdx),%rdx + 4399e3: 66 0f d7 c0 pmovmskb %xmm0,%eax + 4399e7: 48 8d 49 10 lea 0x10(%rcx),%rcx + 4399eb: 48 85 c0 test %rax,%rax + 4399ee: 0f 85 96 00 00 00 jne 439a8a <__stpcpy_ssse3+0x56a> + 4399f4: 66 0f 3a 0f d3 02 palignr $0x2,%xmm3,%xmm2 + 4399fa: 0f 29 12 movaps %xmm2,(%rdx) + 4399fd: 48 8d 49 1e lea 0x1e(%rcx),%rcx + 439a01: 48 8d 52 10 lea 0x10(%rdx),%rdx + 439a05: 48 89 c8 mov %rcx,%rax + 439a08: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 439a0c: 48 29 c8 sub %rcx,%rax + 439a0f: 48 8d 49 f2 lea -0xe(%rcx),%rcx + 439a13: 48 29 c2 sub %rax,%rdx + 439a16: 0f 28 49 fe movaps -0x2(%rcx),%xmm1 + 439a1a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 439a20: 0f 28 51 0e movaps 0xe(%rcx),%xmm2 + 439a24: 0f 28 59 1e movaps 0x1e(%rcx),%xmm3 + 439a28: 0f 28 f3 movaps %xmm3,%xmm6 + 439a2b: 0f 28 61 2e movaps 0x2e(%rcx),%xmm4 + 439a2f: 0f 28 fc movaps %xmm4,%xmm7 + 439a32: 0f 28 69 3e movaps 0x3e(%rcx),%xmm5 + 439a36: 66 0f da f2 pminub %xmm2,%xmm6 + 439a3a: 66 0f da fd pminub %xmm5,%xmm7 + 439a3e: 66 0f da fe pminub %xmm6,%xmm7 + 439a42: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 439a46: 66 0f d7 c7 pmovmskb %xmm7,%eax + 439a4a: 0f 28 fd movaps %xmm5,%xmm7 + 439a4d: 66 0f 3a 0f ec 02 palignr $0x2,%xmm4,%xmm5 + 439a53: 48 85 c0 test %rax,%rax + 439a56: 66 0f 3a 0f e3 02 palignr $0x2,%xmm3,%xmm4 + 439a5c: 0f 85 06 ff ff ff jne 439968 <__stpcpy_ssse3+0x448> + 439a62: 66 0f 3a 0f da 02 palignr $0x2,%xmm2,%xmm3 + 439a68: 48 8d 49 40 lea 0x40(%rcx),%rcx + 439a6c: 66 0f 3a 0f d1 02 palignr $0x2,%xmm1,%xmm2 + 439a72: 0f 28 cf movaps %xmm7,%xmm1 + 439a75: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) + 439a79: 0f 29 62 20 movaps %xmm4,0x20(%rdx) + 439a7d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) + 439a81: 0f 29 12 movaps %xmm2,(%rdx) + 439a84: 48 8d 52 40 lea 0x40(%rdx),%rdx + 439a88: eb 96 jmp 439a20 <__stpcpy_ssse3+0x500> + 439a8a: f3 0f 6f 49 fe movdqu -0x2(%rcx),%xmm1 + 439a8f: 48 c7 c6 0e 00 00 00 mov $0xe,%rsi + 439a96: f3 0f 7f 4a fe movdqu %xmm1,-0x2(%rdx) + 439a9b: e9 60 10 00 00 jmpq 43ab00 <__stpcpy_ssse3+0x15e0> + 439aa0: 0f 28 49 fd movaps -0x3(%rcx),%xmm1 + 439aa4: 0f 28 51 0d movaps 0xd(%rcx),%xmm2 + 439aa8: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 439aac: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439ab0: 0f 28 da movaps %xmm2,%xmm3 + 439ab3: 48 85 c0 test %rax,%rax + 439ab6: 0f 85 0e 01 00 00 jne 439bca <__stpcpy_ssse3+0x6aa> + 439abc: 66 0f 3a 0f d1 03 palignr $0x3,%xmm1,%xmm2 + 439ac2: 0f 29 12 movaps %xmm2,(%rdx) + 439ac5: 0f 28 51 1d movaps 0x1d(%rcx),%xmm2 + 439ac9: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 439acd: 48 8d 52 10 lea 0x10(%rdx),%rdx + 439ad1: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439ad5: 48 8d 49 10 lea 0x10(%rcx),%rcx + 439ad9: 0f 28 ca movaps %xmm2,%xmm1 + 439adc: 48 85 c0 test %rax,%rax + 439adf: 0f 85 e5 00 00 00 jne 439bca <__stpcpy_ssse3+0x6aa> + 439ae5: 66 0f 3a 0f d3 03 palignr $0x3,%xmm3,%xmm2 + 439aeb: 0f 29 12 movaps %xmm2,(%rdx) + 439aee: 0f 28 51 1d movaps 0x1d(%rcx),%xmm2 + 439af2: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 439af6: 48 8d 52 10 lea 0x10(%rdx),%rdx + 439afa: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439afe: 48 8d 49 10 lea 0x10(%rcx),%rcx + 439b02: 0f 28 da movaps %xmm2,%xmm3 + 439b05: 48 85 c0 test %rax,%rax + 439b08: 0f 85 bc 00 00 00 jne 439bca <__stpcpy_ssse3+0x6aa> + 439b0e: 66 0f 3a 0f d1 03 palignr $0x3,%xmm1,%xmm2 + 439b14: 0f 29 12 movaps %xmm2,(%rdx) + 439b17: 0f 28 51 1d movaps 0x1d(%rcx),%xmm2 + 439b1b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 439b1f: 48 8d 52 10 lea 0x10(%rdx),%rdx + 439b23: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439b27: 48 8d 49 10 lea 0x10(%rcx),%rcx + 439b2b: 48 85 c0 test %rax,%rax + 439b2e: 0f 85 96 00 00 00 jne 439bca <__stpcpy_ssse3+0x6aa> + 439b34: 66 0f 3a 0f d3 03 palignr $0x3,%xmm3,%xmm2 + 439b3a: 0f 29 12 movaps %xmm2,(%rdx) + 439b3d: 48 8d 49 1d lea 0x1d(%rcx),%rcx + 439b41: 48 8d 52 10 lea 0x10(%rdx),%rdx + 439b45: 48 89 c8 mov %rcx,%rax + 439b48: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 439b4c: 48 29 c8 sub %rcx,%rax + 439b4f: 48 8d 49 f3 lea -0xd(%rcx),%rcx + 439b53: 48 29 c2 sub %rax,%rdx + 439b56: 0f 28 49 fd movaps -0x3(%rcx),%xmm1 + 439b5a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 439b60: 0f 28 51 0d movaps 0xd(%rcx),%xmm2 + 439b64: 0f 28 59 1d movaps 0x1d(%rcx),%xmm3 + 439b68: 0f 28 f3 movaps %xmm3,%xmm6 + 439b6b: 0f 28 61 2d movaps 0x2d(%rcx),%xmm4 + 439b6f: 0f 28 fc movaps %xmm4,%xmm7 + 439b72: 0f 28 69 3d movaps 0x3d(%rcx),%xmm5 + 439b76: 66 0f da f2 pminub %xmm2,%xmm6 + 439b7a: 66 0f da fd pminub %xmm5,%xmm7 + 439b7e: 66 0f da fe pminub %xmm6,%xmm7 + 439b82: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 439b86: 66 0f d7 c7 pmovmskb %xmm7,%eax + 439b8a: 0f 28 fd movaps %xmm5,%xmm7 + 439b8d: 66 0f 3a 0f ec 03 palignr $0x3,%xmm4,%xmm5 + 439b93: 48 85 c0 test %rax,%rax + 439b96: 66 0f 3a 0f e3 03 palignr $0x3,%xmm3,%xmm4 + 439b9c: 0f 85 06 ff ff ff jne 439aa8 <__stpcpy_ssse3+0x588> + 439ba2: 66 0f 3a 0f da 03 palignr $0x3,%xmm2,%xmm3 + 439ba8: 48 8d 49 40 lea 0x40(%rcx),%rcx + 439bac: 66 0f 3a 0f d1 03 palignr $0x3,%xmm1,%xmm2 + 439bb2: 0f 28 cf movaps %xmm7,%xmm1 + 439bb5: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) + 439bb9: 0f 29 62 20 movaps %xmm4,0x20(%rdx) + 439bbd: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) + 439bc1: 0f 29 12 movaps %xmm2,(%rdx) + 439bc4: 48 8d 52 40 lea 0x40(%rdx),%rdx + 439bc8: eb 96 jmp 439b60 <__stpcpy_ssse3+0x640> + 439bca: f3 0f 6f 49 fd movdqu -0x3(%rcx),%xmm1 + 439bcf: 48 c7 c6 0d 00 00 00 mov $0xd,%rsi + 439bd6: f3 0f 7f 4a fd movdqu %xmm1,-0x3(%rdx) + 439bdb: e9 20 0f 00 00 jmpq 43ab00 <__stpcpy_ssse3+0x15e0> + 439be0: 0f 28 49 fc movaps -0x4(%rcx),%xmm1 + 439be4: 0f 28 51 0c movaps 0xc(%rcx),%xmm2 + 439be8: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 439bec: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439bf0: 0f 28 da movaps %xmm2,%xmm3 + 439bf3: 48 85 c0 test %rax,%rax + 439bf6: 0f 85 0e 01 00 00 jne 439d0a <__stpcpy_ssse3+0x7ea> + 439bfc: 66 0f 3a 0f d1 04 palignr $0x4,%xmm1,%xmm2 + 439c02: 0f 29 12 movaps %xmm2,(%rdx) + 439c05: 0f 28 51 1c movaps 0x1c(%rcx),%xmm2 + 439c09: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 439c0d: 48 8d 52 10 lea 0x10(%rdx),%rdx + 439c11: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439c15: 48 8d 49 10 lea 0x10(%rcx),%rcx + 439c19: 0f 28 ca movaps %xmm2,%xmm1 + 439c1c: 48 85 c0 test %rax,%rax + 439c1f: 0f 85 e5 00 00 00 jne 439d0a <__stpcpy_ssse3+0x7ea> + 439c25: 66 0f 3a 0f d3 04 palignr $0x4,%xmm3,%xmm2 + 439c2b: 0f 29 12 movaps %xmm2,(%rdx) + 439c2e: 0f 28 51 1c movaps 0x1c(%rcx),%xmm2 + 439c32: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 439c36: 48 8d 52 10 lea 0x10(%rdx),%rdx + 439c3a: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439c3e: 48 8d 49 10 lea 0x10(%rcx),%rcx + 439c42: 0f 28 da movaps %xmm2,%xmm3 + 439c45: 48 85 c0 test %rax,%rax + 439c48: 0f 85 bc 00 00 00 jne 439d0a <__stpcpy_ssse3+0x7ea> + 439c4e: 66 0f 3a 0f d1 04 palignr $0x4,%xmm1,%xmm2 + 439c54: 0f 29 12 movaps %xmm2,(%rdx) + 439c57: 0f 28 51 1c movaps 0x1c(%rcx),%xmm2 + 439c5b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 439c5f: 48 8d 52 10 lea 0x10(%rdx),%rdx + 439c63: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439c67: 48 8d 49 10 lea 0x10(%rcx),%rcx + 439c6b: 48 85 c0 test %rax,%rax + 439c6e: 0f 85 96 00 00 00 jne 439d0a <__stpcpy_ssse3+0x7ea> + 439c74: 66 0f 3a 0f d3 04 palignr $0x4,%xmm3,%xmm2 + 439c7a: 0f 29 12 movaps %xmm2,(%rdx) + 439c7d: 48 8d 49 1c lea 0x1c(%rcx),%rcx + 439c81: 48 8d 52 10 lea 0x10(%rdx),%rdx + 439c85: 48 89 c8 mov %rcx,%rax + 439c88: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 439c8c: 48 29 c8 sub %rcx,%rax + 439c8f: 48 8d 49 f4 lea -0xc(%rcx),%rcx + 439c93: 48 29 c2 sub %rax,%rdx + 439c96: 0f 28 49 fc movaps -0x4(%rcx),%xmm1 + 439c9a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 439ca0: 0f 28 51 0c movaps 0xc(%rcx),%xmm2 + 439ca4: 0f 28 59 1c movaps 0x1c(%rcx),%xmm3 + 439ca8: 0f 28 f3 movaps %xmm3,%xmm6 + 439cab: 0f 28 61 2c movaps 0x2c(%rcx),%xmm4 + 439caf: 0f 28 fc movaps %xmm4,%xmm7 + 439cb2: 0f 28 69 3c movaps 0x3c(%rcx),%xmm5 + 439cb6: 66 0f da f2 pminub %xmm2,%xmm6 + 439cba: 66 0f da fd pminub %xmm5,%xmm7 + 439cbe: 66 0f da fe pminub %xmm6,%xmm7 + 439cc2: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 439cc6: 66 0f d7 c7 pmovmskb %xmm7,%eax + 439cca: 0f 28 fd movaps %xmm5,%xmm7 + 439ccd: 66 0f 3a 0f ec 04 palignr $0x4,%xmm4,%xmm5 + 439cd3: 48 85 c0 test %rax,%rax + 439cd6: 66 0f 3a 0f e3 04 palignr $0x4,%xmm3,%xmm4 + 439cdc: 0f 85 06 ff ff ff jne 439be8 <__stpcpy_ssse3+0x6c8> + 439ce2: 66 0f 3a 0f da 04 palignr $0x4,%xmm2,%xmm3 + 439ce8: 48 8d 49 40 lea 0x40(%rcx),%rcx + 439cec: 66 0f 3a 0f d1 04 palignr $0x4,%xmm1,%xmm2 + 439cf2: 0f 28 cf movaps %xmm7,%xmm1 + 439cf5: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) + 439cf9: 0f 29 62 20 movaps %xmm4,0x20(%rdx) + 439cfd: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) + 439d01: 0f 29 12 movaps %xmm2,(%rdx) + 439d04: 48 8d 52 40 lea 0x40(%rdx),%rdx + 439d08: eb 96 jmp 439ca0 <__stpcpy_ssse3+0x780> + 439d0a: f3 0f 6f 49 fc movdqu -0x4(%rcx),%xmm1 + 439d0f: 48 c7 c6 0c 00 00 00 mov $0xc,%rsi + 439d16: f3 0f 7f 4a fc movdqu %xmm1,-0x4(%rdx) + 439d1b: e9 e0 0d 00 00 jmpq 43ab00 <__stpcpy_ssse3+0x15e0> + 439d20: 0f 28 49 fb movaps -0x5(%rcx),%xmm1 + 439d24: 0f 28 51 0b movaps 0xb(%rcx),%xmm2 + 439d28: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 439d2c: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439d30: 0f 28 da movaps %xmm2,%xmm3 + 439d33: 48 85 c0 test %rax,%rax + 439d36: 0f 85 0e 01 00 00 jne 439e4a <__stpcpy_ssse3+0x92a> + 439d3c: 66 0f 3a 0f d1 05 palignr $0x5,%xmm1,%xmm2 + 439d42: 0f 29 12 movaps %xmm2,(%rdx) + 439d45: 0f 28 51 1b movaps 0x1b(%rcx),%xmm2 + 439d49: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 439d4d: 48 8d 52 10 lea 0x10(%rdx),%rdx + 439d51: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439d55: 48 8d 49 10 lea 0x10(%rcx),%rcx + 439d59: 0f 28 ca movaps %xmm2,%xmm1 + 439d5c: 48 85 c0 test %rax,%rax + 439d5f: 0f 85 e5 00 00 00 jne 439e4a <__stpcpy_ssse3+0x92a> + 439d65: 66 0f 3a 0f d3 05 palignr $0x5,%xmm3,%xmm2 + 439d6b: 0f 29 12 movaps %xmm2,(%rdx) + 439d6e: 0f 28 51 1b movaps 0x1b(%rcx),%xmm2 + 439d72: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 439d76: 48 8d 52 10 lea 0x10(%rdx),%rdx + 439d7a: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439d7e: 48 8d 49 10 lea 0x10(%rcx),%rcx + 439d82: 0f 28 da movaps %xmm2,%xmm3 + 439d85: 48 85 c0 test %rax,%rax + 439d88: 0f 85 bc 00 00 00 jne 439e4a <__stpcpy_ssse3+0x92a> + 439d8e: 66 0f 3a 0f d1 05 palignr $0x5,%xmm1,%xmm2 + 439d94: 0f 29 12 movaps %xmm2,(%rdx) + 439d97: 0f 28 51 1b movaps 0x1b(%rcx),%xmm2 + 439d9b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 439d9f: 48 8d 52 10 lea 0x10(%rdx),%rdx + 439da3: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439da7: 48 8d 49 10 lea 0x10(%rcx),%rcx + 439dab: 48 85 c0 test %rax,%rax + 439dae: 0f 85 96 00 00 00 jne 439e4a <__stpcpy_ssse3+0x92a> + 439db4: 66 0f 3a 0f d3 05 palignr $0x5,%xmm3,%xmm2 + 439dba: 0f 29 12 movaps %xmm2,(%rdx) + 439dbd: 48 8d 49 1b lea 0x1b(%rcx),%rcx + 439dc1: 48 8d 52 10 lea 0x10(%rdx),%rdx + 439dc5: 48 89 c8 mov %rcx,%rax + 439dc8: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 439dcc: 48 29 c8 sub %rcx,%rax + 439dcf: 48 8d 49 f5 lea -0xb(%rcx),%rcx + 439dd3: 48 29 c2 sub %rax,%rdx + 439dd6: 0f 28 49 fb movaps -0x5(%rcx),%xmm1 + 439dda: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 439de0: 0f 28 51 0b movaps 0xb(%rcx),%xmm2 + 439de4: 0f 28 59 1b movaps 0x1b(%rcx),%xmm3 + 439de8: 0f 28 f3 movaps %xmm3,%xmm6 + 439deb: 0f 28 61 2b movaps 0x2b(%rcx),%xmm4 + 439def: 0f 28 fc movaps %xmm4,%xmm7 + 439df2: 0f 28 69 3b movaps 0x3b(%rcx),%xmm5 + 439df6: 66 0f da f2 pminub %xmm2,%xmm6 + 439dfa: 66 0f da fd pminub %xmm5,%xmm7 + 439dfe: 66 0f da fe pminub %xmm6,%xmm7 + 439e02: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 439e06: 66 0f d7 c7 pmovmskb %xmm7,%eax + 439e0a: 0f 28 fd movaps %xmm5,%xmm7 + 439e0d: 66 0f 3a 0f ec 05 palignr $0x5,%xmm4,%xmm5 + 439e13: 48 85 c0 test %rax,%rax + 439e16: 66 0f 3a 0f e3 05 palignr $0x5,%xmm3,%xmm4 + 439e1c: 0f 85 06 ff ff ff jne 439d28 <__stpcpy_ssse3+0x808> + 439e22: 66 0f 3a 0f da 05 palignr $0x5,%xmm2,%xmm3 + 439e28: 48 8d 49 40 lea 0x40(%rcx),%rcx + 439e2c: 66 0f 3a 0f d1 05 palignr $0x5,%xmm1,%xmm2 + 439e32: 0f 28 cf movaps %xmm7,%xmm1 + 439e35: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) + 439e39: 0f 29 62 20 movaps %xmm4,0x20(%rdx) + 439e3d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) + 439e41: 0f 29 12 movaps %xmm2,(%rdx) + 439e44: 48 8d 52 40 lea 0x40(%rdx),%rdx + 439e48: eb 96 jmp 439de0 <__stpcpy_ssse3+0x8c0> + 439e4a: f3 0f 6f 49 fb movdqu -0x5(%rcx),%xmm1 + 439e4f: 48 c7 c6 0b 00 00 00 mov $0xb,%rsi + 439e56: f3 0f 7f 4a fb movdqu %xmm1,-0x5(%rdx) + 439e5b: e9 a0 0c 00 00 jmpq 43ab00 <__stpcpy_ssse3+0x15e0> + 439e60: 0f 28 49 fa movaps -0x6(%rcx),%xmm1 + 439e64: 0f 28 51 0a movaps 0xa(%rcx),%xmm2 + 439e68: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 439e6c: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439e70: 0f 28 da movaps %xmm2,%xmm3 + 439e73: 48 85 c0 test %rax,%rax + 439e76: 0f 85 0e 01 00 00 jne 439f8a <__stpcpy_ssse3+0xa6a> + 439e7c: 66 0f 3a 0f d1 06 palignr $0x6,%xmm1,%xmm2 + 439e82: 0f 29 12 movaps %xmm2,(%rdx) + 439e85: 0f 28 51 1a movaps 0x1a(%rcx),%xmm2 + 439e89: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 439e8d: 48 8d 52 10 lea 0x10(%rdx),%rdx + 439e91: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439e95: 48 8d 49 10 lea 0x10(%rcx),%rcx + 439e99: 0f 28 ca movaps %xmm2,%xmm1 + 439e9c: 48 85 c0 test %rax,%rax + 439e9f: 0f 85 e5 00 00 00 jne 439f8a <__stpcpy_ssse3+0xa6a> + 439ea5: 66 0f 3a 0f d3 06 palignr $0x6,%xmm3,%xmm2 + 439eab: 0f 29 12 movaps %xmm2,(%rdx) + 439eae: 0f 28 51 1a movaps 0x1a(%rcx),%xmm2 + 439eb2: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 439eb6: 48 8d 52 10 lea 0x10(%rdx),%rdx + 439eba: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439ebe: 48 8d 49 10 lea 0x10(%rcx),%rcx + 439ec2: 0f 28 da movaps %xmm2,%xmm3 + 439ec5: 48 85 c0 test %rax,%rax + 439ec8: 0f 85 bc 00 00 00 jne 439f8a <__stpcpy_ssse3+0xa6a> + 439ece: 66 0f 3a 0f d1 06 palignr $0x6,%xmm1,%xmm2 + 439ed4: 0f 29 12 movaps %xmm2,(%rdx) + 439ed7: 0f 28 51 1a movaps 0x1a(%rcx),%xmm2 + 439edb: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 439edf: 48 8d 52 10 lea 0x10(%rdx),%rdx + 439ee3: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439ee7: 48 8d 49 10 lea 0x10(%rcx),%rcx + 439eeb: 48 85 c0 test %rax,%rax + 439eee: 0f 85 96 00 00 00 jne 439f8a <__stpcpy_ssse3+0xa6a> + 439ef4: 66 0f 3a 0f d3 06 palignr $0x6,%xmm3,%xmm2 + 439efa: 0f 29 12 movaps %xmm2,(%rdx) + 439efd: 48 8d 49 1a lea 0x1a(%rcx),%rcx + 439f01: 48 8d 52 10 lea 0x10(%rdx),%rdx + 439f05: 48 89 c8 mov %rcx,%rax + 439f08: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 439f0c: 48 29 c8 sub %rcx,%rax + 439f0f: 48 8d 49 f6 lea -0xa(%rcx),%rcx + 439f13: 48 29 c2 sub %rax,%rdx + 439f16: 0f 28 49 fa movaps -0x6(%rcx),%xmm1 + 439f1a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 439f20: 0f 28 51 0a movaps 0xa(%rcx),%xmm2 + 439f24: 0f 28 59 1a movaps 0x1a(%rcx),%xmm3 + 439f28: 0f 28 f3 movaps %xmm3,%xmm6 + 439f2b: 0f 28 61 2a movaps 0x2a(%rcx),%xmm4 + 439f2f: 0f 28 fc movaps %xmm4,%xmm7 + 439f32: 0f 28 69 3a movaps 0x3a(%rcx),%xmm5 + 439f36: 66 0f da f2 pminub %xmm2,%xmm6 + 439f3a: 66 0f da fd pminub %xmm5,%xmm7 + 439f3e: 66 0f da fe pminub %xmm6,%xmm7 + 439f42: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 439f46: 66 0f d7 c7 pmovmskb %xmm7,%eax + 439f4a: 0f 28 fd movaps %xmm5,%xmm7 + 439f4d: 66 0f 3a 0f ec 06 palignr $0x6,%xmm4,%xmm5 + 439f53: 48 85 c0 test %rax,%rax + 439f56: 66 0f 3a 0f e3 06 palignr $0x6,%xmm3,%xmm4 + 439f5c: 0f 85 06 ff ff ff jne 439e68 <__stpcpy_ssse3+0x948> + 439f62: 66 0f 3a 0f da 06 palignr $0x6,%xmm2,%xmm3 + 439f68: 48 8d 49 40 lea 0x40(%rcx),%rcx + 439f6c: 66 0f 3a 0f d1 06 palignr $0x6,%xmm1,%xmm2 + 439f72: 0f 28 cf movaps %xmm7,%xmm1 + 439f75: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) + 439f79: 0f 29 62 20 movaps %xmm4,0x20(%rdx) + 439f7d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) + 439f81: 0f 29 12 movaps %xmm2,(%rdx) + 439f84: 48 8d 52 40 lea 0x40(%rdx),%rdx + 439f88: eb 96 jmp 439f20 <__stpcpy_ssse3+0xa00> + 439f8a: 4c 8b 09 mov (%rcx),%r9 + 439f8d: 8b 71 06 mov 0x6(%rcx),%esi + 439f90: 4c 89 0a mov %r9,(%rdx) + 439f93: 89 72 06 mov %esi,0x6(%rdx) + 439f96: 48 c7 c6 0a 00 00 00 mov $0xa,%rsi + 439f9d: e9 5e 0b 00 00 jmpq 43ab00 <__stpcpy_ssse3+0x15e0> + 439fa2: 0f 1f 40 00 nopl 0x0(%rax) + 439fa6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 439fad: 00 00 00 + 439fb0: 0f 28 49 f9 movaps -0x7(%rcx),%xmm1 + 439fb4: 0f 28 51 09 movaps 0x9(%rcx),%xmm2 + 439fb8: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 439fbc: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439fc0: 0f 28 da movaps %xmm2,%xmm3 + 439fc3: 48 85 c0 test %rax,%rax + 439fc6: 0f 85 0e 01 00 00 jne 43a0da <__stpcpy_ssse3+0xbba> + 439fcc: 66 0f 3a 0f d1 07 palignr $0x7,%xmm1,%xmm2 + 439fd2: 0f 29 12 movaps %xmm2,(%rdx) + 439fd5: 0f 28 51 19 movaps 0x19(%rcx),%xmm2 + 439fd9: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 439fdd: 48 8d 52 10 lea 0x10(%rdx),%rdx + 439fe1: 66 0f d7 c0 pmovmskb %xmm0,%eax + 439fe5: 48 8d 49 10 lea 0x10(%rcx),%rcx + 439fe9: 0f 28 ca movaps %xmm2,%xmm1 + 439fec: 48 85 c0 test %rax,%rax + 439fef: 0f 85 e5 00 00 00 jne 43a0da <__stpcpy_ssse3+0xbba> + 439ff5: 66 0f 3a 0f d3 07 palignr $0x7,%xmm3,%xmm2 + 439ffb: 0f 29 12 movaps %xmm2,(%rdx) + 439ffe: 0f 28 51 19 movaps 0x19(%rcx),%xmm2 + 43a002: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a006: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a00a: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a00e: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43a012: 0f 28 da movaps %xmm2,%xmm3 + 43a015: 48 85 c0 test %rax,%rax + 43a018: 0f 85 bc 00 00 00 jne 43a0da <__stpcpy_ssse3+0xbba> + 43a01e: 66 0f 3a 0f d1 07 palignr $0x7,%xmm1,%xmm2 + 43a024: 0f 29 12 movaps %xmm2,(%rdx) + 43a027: 0f 28 51 19 movaps 0x19(%rcx),%xmm2 + 43a02b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a02f: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a033: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a037: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43a03b: 48 85 c0 test %rax,%rax + 43a03e: 0f 85 96 00 00 00 jne 43a0da <__stpcpy_ssse3+0xbba> + 43a044: 66 0f 3a 0f d3 07 palignr $0x7,%xmm3,%xmm2 + 43a04a: 0f 29 12 movaps %xmm2,(%rdx) + 43a04d: 48 8d 49 19 lea 0x19(%rcx),%rcx + 43a051: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a055: 48 89 c8 mov %rcx,%rax + 43a058: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 43a05c: 48 29 c8 sub %rcx,%rax + 43a05f: 48 8d 49 f7 lea -0x9(%rcx),%rcx + 43a063: 48 29 c2 sub %rax,%rdx + 43a066: 0f 28 49 f9 movaps -0x7(%rcx),%xmm1 + 43a06a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43a070: 0f 28 51 09 movaps 0x9(%rcx),%xmm2 + 43a074: 0f 28 59 19 movaps 0x19(%rcx),%xmm3 + 43a078: 0f 28 f3 movaps %xmm3,%xmm6 + 43a07b: 0f 28 61 29 movaps 0x29(%rcx),%xmm4 + 43a07f: 0f 28 fc movaps %xmm4,%xmm7 + 43a082: 0f 28 69 39 movaps 0x39(%rcx),%xmm5 + 43a086: 66 0f da f2 pminub %xmm2,%xmm6 + 43a08a: 66 0f da fd pminub %xmm5,%xmm7 + 43a08e: 66 0f da fe pminub %xmm6,%xmm7 + 43a092: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 43a096: 66 0f d7 c7 pmovmskb %xmm7,%eax + 43a09a: 0f 28 fd movaps %xmm5,%xmm7 + 43a09d: 66 0f 3a 0f ec 07 palignr $0x7,%xmm4,%xmm5 + 43a0a3: 48 85 c0 test %rax,%rax + 43a0a6: 66 0f 3a 0f e3 07 palignr $0x7,%xmm3,%xmm4 + 43a0ac: 0f 85 06 ff ff ff jne 439fb8 <__stpcpy_ssse3+0xa98> + 43a0b2: 66 0f 3a 0f da 07 palignr $0x7,%xmm2,%xmm3 + 43a0b8: 48 8d 49 40 lea 0x40(%rcx),%rcx + 43a0bc: 66 0f 3a 0f d1 07 palignr $0x7,%xmm1,%xmm2 + 43a0c2: 0f 28 cf movaps %xmm7,%xmm1 + 43a0c5: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) + 43a0c9: 0f 29 62 20 movaps %xmm4,0x20(%rdx) + 43a0cd: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) + 43a0d1: 0f 29 12 movaps %xmm2,(%rdx) + 43a0d4: 48 8d 52 40 lea 0x40(%rdx),%rdx + 43a0d8: eb 96 jmp 43a070 <__stpcpy_ssse3+0xb50> + 43a0da: 4c 8b 09 mov (%rcx),%r9 + 43a0dd: 8b 71 05 mov 0x5(%rcx),%esi + 43a0e0: 4c 89 0a mov %r9,(%rdx) + 43a0e3: 89 72 05 mov %esi,0x5(%rdx) + 43a0e6: 48 c7 c6 09 00 00 00 mov $0x9,%rsi + 43a0ed: e9 0e 0a 00 00 jmpq 43ab00 <__stpcpy_ssse3+0x15e0> + 43a0f2: 0f 1f 40 00 nopl 0x0(%rax) + 43a0f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43a0fd: 00 00 00 + 43a100: 0f 28 49 f8 movaps -0x8(%rcx),%xmm1 + 43a104: 0f 28 51 08 movaps 0x8(%rcx),%xmm2 + 43a108: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a10c: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a110: 0f 28 da movaps %xmm2,%xmm3 + 43a113: 48 85 c0 test %rax,%rax + 43a116: 0f 85 0e 01 00 00 jne 43a22a <__stpcpy_ssse3+0xd0a> + 43a11c: 66 0f 3a 0f d1 08 palignr $0x8,%xmm1,%xmm2 + 43a122: 0f 29 12 movaps %xmm2,(%rdx) + 43a125: 0f 28 51 18 movaps 0x18(%rcx),%xmm2 + 43a129: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a12d: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a131: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a135: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43a139: 0f 28 ca movaps %xmm2,%xmm1 + 43a13c: 48 85 c0 test %rax,%rax + 43a13f: 0f 85 e5 00 00 00 jne 43a22a <__stpcpy_ssse3+0xd0a> + 43a145: 66 0f 3a 0f d3 08 palignr $0x8,%xmm3,%xmm2 + 43a14b: 0f 29 12 movaps %xmm2,(%rdx) + 43a14e: 0f 28 51 18 movaps 0x18(%rcx),%xmm2 + 43a152: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a156: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a15a: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a15e: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43a162: 0f 28 da movaps %xmm2,%xmm3 + 43a165: 48 85 c0 test %rax,%rax + 43a168: 0f 85 bc 00 00 00 jne 43a22a <__stpcpy_ssse3+0xd0a> + 43a16e: 66 0f 3a 0f d1 08 palignr $0x8,%xmm1,%xmm2 + 43a174: 0f 29 12 movaps %xmm2,(%rdx) + 43a177: 0f 28 51 18 movaps 0x18(%rcx),%xmm2 + 43a17b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a17f: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a183: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a187: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43a18b: 48 85 c0 test %rax,%rax + 43a18e: 0f 85 96 00 00 00 jne 43a22a <__stpcpy_ssse3+0xd0a> + 43a194: 66 0f 3a 0f d3 08 palignr $0x8,%xmm3,%xmm2 + 43a19a: 0f 29 12 movaps %xmm2,(%rdx) + 43a19d: 48 8d 49 18 lea 0x18(%rcx),%rcx + 43a1a1: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a1a5: 48 89 c8 mov %rcx,%rax + 43a1a8: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 43a1ac: 48 29 c8 sub %rcx,%rax + 43a1af: 48 8d 49 f8 lea -0x8(%rcx),%rcx + 43a1b3: 48 29 c2 sub %rax,%rdx + 43a1b6: 0f 28 49 f8 movaps -0x8(%rcx),%xmm1 + 43a1ba: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43a1c0: 0f 28 51 08 movaps 0x8(%rcx),%xmm2 + 43a1c4: 0f 28 59 18 movaps 0x18(%rcx),%xmm3 + 43a1c8: 0f 28 f3 movaps %xmm3,%xmm6 + 43a1cb: 0f 28 61 28 movaps 0x28(%rcx),%xmm4 + 43a1cf: 0f 28 fc movaps %xmm4,%xmm7 + 43a1d2: 0f 28 69 38 movaps 0x38(%rcx),%xmm5 + 43a1d6: 66 0f da f2 pminub %xmm2,%xmm6 + 43a1da: 66 0f da fd pminub %xmm5,%xmm7 + 43a1de: 66 0f da fe pminub %xmm6,%xmm7 + 43a1e2: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 43a1e6: 66 0f d7 c7 pmovmskb %xmm7,%eax + 43a1ea: 0f 28 fd movaps %xmm5,%xmm7 + 43a1ed: 66 0f 3a 0f ec 08 palignr $0x8,%xmm4,%xmm5 + 43a1f3: 48 85 c0 test %rax,%rax + 43a1f6: 66 0f 3a 0f e3 08 palignr $0x8,%xmm3,%xmm4 + 43a1fc: 0f 85 06 ff ff ff jne 43a108 <__stpcpy_ssse3+0xbe8> + 43a202: 66 0f 3a 0f da 08 palignr $0x8,%xmm2,%xmm3 + 43a208: 48 8d 49 40 lea 0x40(%rcx),%rcx + 43a20c: 66 0f 3a 0f d1 08 palignr $0x8,%xmm1,%xmm2 + 43a212: 0f 28 cf movaps %xmm7,%xmm1 + 43a215: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) + 43a219: 0f 29 62 20 movaps %xmm4,0x20(%rdx) + 43a21d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) + 43a221: 0f 29 12 movaps %xmm2,(%rdx) + 43a224: 48 8d 52 40 lea 0x40(%rdx),%rdx + 43a228: eb 96 jmp 43a1c0 <__stpcpy_ssse3+0xca0> + 43a22a: 4c 8b 09 mov (%rcx),%r9 + 43a22d: 48 c7 c6 08 00 00 00 mov $0x8,%rsi + 43a234: 4c 89 0a mov %r9,(%rdx) + 43a237: e9 c4 08 00 00 jmpq 43ab00 <__stpcpy_ssse3+0x15e0> + 43a23c: 0f 1f 40 00 nopl 0x0(%rax) + 43a240: 0f 28 49 f7 movaps -0x9(%rcx),%xmm1 + 43a244: 0f 28 51 07 movaps 0x7(%rcx),%xmm2 + 43a248: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a24c: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a250: 0f 28 da movaps %xmm2,%xmm3 + 43a253: 48 85 c0 test %rax,%rax + 43a256: 0f 85 0e 01 00 00 jne 43a36a <__stpcpy_ssse3+0xe4a> + 43a25c: 66 0f 3a 0f d1 09 palignr $0x9,%xmm1,%xmm2 + 43a262: 0f 29 12 movaps %xmm2,(%rdx) + 43a265: 0f 28 51 17 movaps 0x17(%rcx),%xmm2 + 43a269: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a26d: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a271: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a275: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43a279: 0f 28 ca movaps %xmm2,%xmm1 + 43a27c: 48 85 c0 test %rax,%rax + 43a27f: 0f 85 e5 00 00 00 jne 43a36a <__stpcpy_ssse3+0xe4a> + 43a285: 66 0f 3a 0f d3 09 palignr $0x9,%xmm3,%xmm2 + 43a28b: 0f 29 12 movaps %xmm2,(%rdx) + 43a28e: 0f 28 51 17 movaps 0x17(%rcx),%xmm2 + 43a292: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a296: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a29a: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a29e: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43a2a2: 0f 28 da movaps %xmm2,%xmm3 + 43a2a5: 48 85 c0 test %rax,%rax + 43a2a8: 0f 85 bc 00 00 00 jne 43a36a <__stpcpy_ssse3+0xe4a> + 43a2ae: 66 0f 3a 0f d1 09 palignr $0x9,%xmm1,%xmm2 + 43a2b4: 0f 29 12 movaps %xmm2,(%rdx) + 43a2b7: 0f 28 51 17 movaps 0x17(%rcx),%xmm2 + 43a2bb: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a2bf: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a2c3: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a2c7: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43a2cb: 48 85 c0 test %rax,%rax + 43a2ce: 0f 85 96 00 00 00 jne 43a36a <__stpcpy_ssse3+0xe4a> + 43a2d4: 66 0f 3a 0f d3 09 palignr $0x9,%xmm3,%xmm2 + 43a2da: 0f 29 12 movaps %xmm2,(%rdx) + 43a2dd: 48 8d 49 17 lea 0x17(%rcx),%rcx + 43a2e1: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a2e5: 48 89 c8 mov %rcx,%rax + 43a2e8: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 43a2ec: 48 29 c8 sub %rcx,%rax + 43a2ef: 48 8d 49 f9 lea -0x7(%rcx),%rcx + 43a2f3: 48 29 c2 sub %rax,%rdx + 43a2f6: 0f 28 49 f7 movaps -0x9(%rcx),%xmm1 + 43a2fa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43a300: 0f 28 51 07 movaps 0x7(%rcx),%xmm2 + 43a304: 0f 28 59 17 movaps 0x17(%rcx),%xmm3 + 43a308: 0f 28 f3 movaps %xmm3,%xmm6 + 43a30b: 0f 28 61 27 movaps 0x27(%rcx),%xmm4 + 43a30f: 0f 28 fc movaps %xmm4,%xmm7 + 43a312: 0f 28 69 37 movaps 0x37(%rcx),%xmm5 + 43a316: 66 0f da f2 pminub %xmm2,%xmm6 + 43a31a: 66 0f da fd pminub %xmm5,%xmm7 + 43a31e: 66 0f da fe pminub %xmm6,%xmm7 + 43a322: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 43a326: 66 0f d7 c7 pmovmskb %xmm7,%eax + 43a32a: 0f 28 fd movaps %xmm5,%xmm7 + 43a32d: 66 0f 3a 0f ec 09 palignr $0x9,%xmm4,%xmm5 + 43a333: 48 85 c0 test %rax,%rax + 43a336: 66 0f 3a 0f e3 09 palignr $0x9,%xmm3,%xmm4 + 43a33c: 0f 85 06 ff ff ff jne 43a248 <__stpcpy_ssse3+0xd28> + 43a342: 66 0f 3a 0f da 09 palignr $0x9,%xmm2,%xmm3 + 43a348: 48 8d 49 40 lea 0x40(%rcx),%rcx + 43a34c: 66 0f 3a 0f d1 09 palignr $0x9,%xmm1,%xmm2 + 43a352: 0f 28 cf movaps %xmm7,%xmm1 + 43a355: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) + 43a359: 0f 29 62 20 movaps %xmm4,0x20(%rdx) + 43a35d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) + 43a361: 0f 29 12 movaps %xmm2,(%rdx) + 43a364: 48 8d 52 40 lea 0x40(%rdx),%rdx + 43a368: eb 96 jmp 43a300 <__stpcpy_ssse3+0xde0> + 43a36a: 4c 8b 49 ff mov -0x1(%rcx),%r9 + 43a36e: 48 c7 c6 07 00 00 00 mov $0x7,%rsi + 43a375: 4c 89 4a ff mov %r9,-0x1(%rdx) + 43a379: e9 82 07 00 00 jmpq 43ab00 <__stpcpy_ssse3+0x15e0> + 43a37e: 66 90 xchg %ax,%ax + 43a380: 0f 28 49 f6 movaps -0xa(%rcx),%xmm1 + 43a384: 0f 28 51 06 movaps 0x6(%rcx),%xmm2 + 43a388: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a38c: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a390: 0f 28 da movaps %xmm2,%xmm3 + 43a393: 48 85 c0 test %rax,%rax + 43a396: 0f 85 0e 01 00 00 jne 43a4aa <__stpcpy_ssse3+0xf8a> + 43a39c: 66 0f 3a 0f d1 0a palignr $0xa,%xmm1,%xmm2 + 43a3a2: 0f 29 12 movaps %xmm2,(%rdx) + 43a3a5: 0f 28 51 16 movaps 0x16(%rcx),%xmm2 + 43a3a9: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a3ad: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a3b1: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a3b5: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43a3b9: 0f 28 ca movaps %xmm2,%xmm1 + 43a3bc: 48 85 c0 test %rax,%rax + 43a3bf: 0f 85 e5 00 00 00 jne 43a4aa <__stpcpy_ssse3+0xf8a> + 43a3c5: 66 0f 3a 0f d3 0a palignr $0xa,%xmm3,%xmm2 + 43a3cb: 0f 29 12 movaps %xmm2,(%rdx) + 43a3ce: 0f 28 51 16 movaps 0x16(%rcx),%xmm2 + 43a3d2: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a3d6: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a3da: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a3de: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43a3e2: 0f 28 da movaps %xmm2,%xmm3 + 43a3e5: 48 85 c0 test %rax,%rax + 43a3e8: 0f 85 bc 00 00 00 jne 43a4aa <__stpcpy_ssse3+0xf8a> + 43a3ee: 66 0f 3a 0f d1 0a palignr $0xa,%xmm1,%xmm2 + 43a3f4: 0f 29 12 movaps %xmm2,(%rdx) + 43a3f7: 0f 28 51 16 movaps 0x16(%rcx),%xmm2 + 43a3fb: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a3ff: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a403: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a407: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43a40b: 48 85 c0 test %rax,%rax + 43a40e: 0f 85 96 00 00 00 jne 43a4aa <__stpcpy_ssse3+0xf8a> + 43a414: 66 0f 3a 0f d3 0a palignr $0xa,%xmm3,%xmm2 + 43a41a: 0f 29 12 movaps %xmm2,(%rdx) + 43a41d: 48 8d 49 16 lea 0x16(%rcx),%rcx + 43a421: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a425: 48 89 c8 mov %rcx,%rax + 43a428: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 43a42c: 48 29 c8 sub %rcx,%rax + 43a42f: 48 8d 49 fa lea -0x6(%rcx),%rcx + 43a433: 48 29 c2 sub %rax,%rdx + 43a436: 0f 28 49 f6 movaps -0xa(%rcx),%xmm1 + 43a43a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43a440: 0f 28 51 06 movaps 0x6(%rcx),%xmm2 + 43a444: 0f 28 59 16 movaps 0x16(%rcx),%xmm3 + 43a448: 0f 28 f3 movaps %xmm3,%xmm6 + 43a44b: 0f 28 61 26 movaps 0x26(%rcx),%xmm4 + 43a44f: 0f 28 fc movaps %xmm4,%xmm7 + 43a452: 0f 28 69 36 movaps 0x36(%rcx),%xmm5 + 43a456: 66 0f da f2 pminub %xmm2,%xmm6 + 43a45a: 66 0f da fd pminub %xmm5,%xmm7 + 43a45e: 66 0f da fe pminub %xmm6,%xmm7 + 43a462: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 43a466: 66 0f d7 c7 pmovmskb %xmm7,%eax + 43a46a: 0f 28 fd movaps %xmm5,%xmm7 + 43a46d: 66 0f 3a 0f ec 0a palignr $0xa,%xmm4,%xmm5 + 43a473: 48 85 c0 test %rax,%rax + 43a476: 66 0f 3a 0f e3 0a palignr $0xa,%xmm3,%xmm4 + 43a47c: 0f 85 06 ff ff ff jne 43a388 <__stpcpy_ssse3+0xe68> + 43a482: 66 0f 3a 0f da 0a palignr $0xa,%xmm2,%xmm3 + 43a488: 48 8d 49 40 lea 0x40(%rcx),%rcx + 43a48c: 66 0f 3a 0f d1 0a palignr $0xa,%xmm1,%xmm2 + 43a492: 0f 28 cf movaps %xmm7,%xmm1 + 43a495: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) + 43a499: 0f 29 62 20 movaps %xmm4,0x20(%rdx) + 43a49d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) + 43a4a1: 0f 29 12 movaps %xmm2,(%rdx) + 43a4a4: 48 8d 52 40 lea 0x40(%rdx),%rdx + 43a4a8: eb 96 jmp 43a440 <__stpcpy_ssse3+0xf20> + 43a4aa: 4c 8b 49 fe mov -0x2(%rcx),%r9 + 43a4ae: 48 c7 c6 06 00 00 00 mov $0x6,%rsi + 43a4b5: 4c 89 4a fe mov %r9,-0x2(%rdx) + 43a4b9: e9 42 06 00 00 jmpq 43ab00 <__stpcpy_ssse3+0x15e0> + 43a4be: 66 90 xchg %ax,%ax + 43a4c0: 0f 28 49 f5 movaps -0xb(%rcx),%xmm1 + 43a4c4: 0f 28 51 05 movaps 0x5(%rcx),%xmm2 + 43a4c8: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a4cc: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a4d0: 0f 28 da movaps %xmm2,%xmm3 + 43a4d3: 48 85 c0 test %rax,%rax + 43a4d6: 0f 85 0e 01 00 00 jne 43a5ea <__stpcpy_ssse3+0x10ca> + 43a4dc: 66 0f 3a 0f d1 0b palignr $0xb,%xmm1,%xmm2 + 43a4e2: 0f 29 12 movaps %xmm2,(%rdx) + 43a4e5: 0f 28 51 15 movaps 0x15(%rcx),%xmm2 + 43a4e9: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a4ed: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a4f1: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a4f5: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43a4f9: 0f 28 ca movaps %xmm2,%xmm1 + 43a4fc: 48 85 c0 test %rax,%rax + 43a4ff: 0f 85 e5 00 00 00 jne 43a5ea <__stpcpy_ssse3+0x10ca> + 43a505: 66 0f 3a 0f d3 0b palignr $0xb,%xmm3,%xmm2 + 43a50b: 0f 29 12 movaps %xmm2,(%rdx) + 43a50e: 0f 28 51 15 movaps 0x15(%rcx),%xmm2 + 43a512: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a516: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a51a: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a51e: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43a522: 0f 28 da movaps %xmm2,%xmm3 + 43a525: 48 85 c0 test %rax,%rax + 43a528: 0f 85 bc 00 00 00 jne 43a5ea <__stpcpy_ssse3+0x10ca> + 43a52e: 66 0f 3a 0f d1 0b palignr $0xb,%xmm1,%xmm2 + 43a534: 0f 29 12 movaps %xmm2,(%rdx) + 43a537: 0f 28 51 15 movaps 0x15(%rcx),%xmm2 + 43a53b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a53f: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a543: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a547: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43a54b: 48 85 c0 test %rax,%rax + 43a54e: 0f 85 96 00 00 00 jne 43a5ea <__stpcpy_ssse3+0x10ca> + 43a554: 66 0f 3a 0f d3 0b palignr $0xb,%xmm3,%xmm2 + 43a55a: 0f 29 12 movaps %xmm2,(%rdx) + 43a55d: 48 8d 49 15 lea 0x15(%rcx),%rcx + 43a561: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a565: 48 89 c8 mov %rcx,%rax + 43a568: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 43a56c: 48 29 c8 sub %rcx,%rax + 43a56f: 48 8d 49 fb lea -0x5(%rcx),%rcx + 43a573: 48 29 c2 sub %rax,%rdx + 43a576: 0f 28 49 f5 movaps -0xb(%rcx),%xmm1 + 43a57a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43a580: 0f 28 51 05 movaps 0x5(%rcx),%xmm2 + 43a584: 0f 28 59 15 movaps 0x15(%rcx),%xmm3 + 43a588: 0f 28 f3 movaps %xmm3,%xmm6 + 43a58b: 0f 28 61 25 movaps 0x25(%rcx),%xmm4 + 43a58f: 0f 28 fc movaps %xmm4,%xmm7 + 43a592: 0f 28 69 35 movaps 0x35(%rcx),%xmm5 + 43a596: 66 0f da f2 pminub %xmm2,%xmm6 + 43a59a: 66 0f da fd pminub %xmm5,%xmm7 + 43a59e: 66 0f da fe pminub %xmm6,%xmm7 + 43a5a2: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 43a5a6: 66 0f d7 c7 pmovmskb %xmm7,%eax + 43a5aa: 0f 28 fd movaps %xmm5,%xmm7 + 43a5ad: 66 0f 3a 0f ec 0b palignr $0xb,%xmm4,%xmm5 + 43a5b3: 48 85 c0 test %rax,%rax + 43a5b6: 66 0f 3a 0f e3 0b palignr $0xb,%xmm3,%xmm4 + 43a5bc: 0f 85 06 ff ff ff jne 43a4c8 <__stpcpy_ssse3+0xfa8> + 43a5c2: 66 0f 3a 0f da 0b palignr $0xb,%xmm2,%xmm3 + 43a5c8: 48 8d 49 40 lea 0x40(%rcx),%rcx + 43a5cc: 66 0f 3a 0f d1 0b palignr $0xb,%xmm1,%xmm2 + 43a5d2: 0f 28 cf movaps %xmm7,%xmm1 + 43a5d5: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) + 43a5d9: 0f 29 62 20 movaps %xmm4,0x20(%rdx) + 43a5dd: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) + 43a5e1: 0f 29 12 movaps %xmm2,(%rdx) + 43a5e4: 48 8d 52 40 lea 0x40(%rdx),%rdx + 43a5e8: eb 96 jmp 43a580 <__stpcpy_ssse3+0x1060> + 43a5ea: 4c 8b 49 fd mov -0x3(%rcx),%r9 + 43a5ee: 48 c7 c6 05 00 00 00 mov $0x5,%rsi + 43a5f5: 4c 89 4a fd mov %r9,-0x3(%rdx) + 43a5f9: e9 02 05 00 00 jmpq 43ab00 <__stpcpy_ssse3+0x15e0> + 43a5fe: 66 90 xchg %ax,%ax + 43a600: 0f 28 49 f4 movaps -0xc(%rcx),%xmm1 + 43a604: 0f 28 51 04 movaps 0x4(%rcx),%xmm2 + 43a608: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a60c: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a610: 0f 28 da movaps %xmm2,%xmm3 + 43a613: 48 85 c0 test %rax,%rax + 43a616: 0f 85 0e 01 00 00 jne 43a72a <__stpcpy_ssse3+0x120a> + 43a61c: 66 0f 3a 0f d1 0c palignr $0xc,%xmm1,%xmm2 + 43a622: 0f 29 12 movaps %xmm2,(%rdx) + 43a625: 0f 28 51 14 movaps 0x14(%rcx),%xmm2 + 43a629: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a62d: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a631: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a635: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43a639: 0f 28 ca movaps %xmm2,%xmm1 + 43a63c: 48 85 c0 test %rax,%rax + 43a63f: 0f 85 e5 00 00 00 jne 43a72a <__stpcpy_ssse3+0x120a> + 43a645: 66 0f 3a 0f d3 0c palignr $0xc,%xmm3,%xmm2 + 43a64b: 0f 29 12 movaps %xmm2,(%rdx) + 43a64e: 0f 28 51 14 movaps 0x14(%rcx),%xmm2 + 43a652: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a656: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a65a: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a65e: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43a662: 0f 28 da movaps %xmm2,%xmm3 + 43a665: 48 85 c0 test %rax,%rax + 43a668: 0f 85 bc 00 00 00 jne 43a72a <__stpcpy_ssse3+0x120a> + 43a66e: 66 0f 3a 0f d1 0c palignr $0xc,%xmm1,%xmm2 + 43a674: 0f 29 12 movaps %xmm2,(%rdx) + 43a677: 0f 28 51 14 movaps 0x14(%rcx),%xmm2 + 43a67b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a67f: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a683: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a687: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43a68b: 48 85 c0 test %rax,%rax + 43a68e: 0f 85 96 00 00 00 jne 43a72a <__stpcpy_ssse3+0x120a> + 43a694: 66 0f 3a 0f d3 0c palignr $0xc,%xmm3,%xmm2 + 43a69a: 0f 29 12 movaps %xmm2,(%rdx) + 43a69d: 48 8d 49 14 lea 0x14(%rcx),%rcx + 43a6a1: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a6a5: 48 89 c8 mov %rcx,%rax + 43a6a8: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 43a6ac: 48 29 c8 sub %rcx,%rax + 43a6af: 48 8d 49 fc lea -0x4(%rcx),%rcx + 43a6b3: 48 29 c2 sub %rax,%rdx + 43a6b6: 0f 28 49 f4 movaps -0xc(%rcx),%xmm1 + 43a6ba: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43a6c0: 0f 28 51 04 movaps 0x4(%rcx),%xmm2 + 43a6c4: 0f 28 59 14 movaps 0x14(%rcx),%xmm3 + 43a6c8: 0f 28 f3 movaps %xmm3,%xmm6 + 43a6cb: 0f 28 61 24 movaps 0x24(%rcx),%xmm4 + 43a6cf: 0f 28 fc movaps %xmm4,%xmm7 + 43a6d2: 0f 28 69 34 movaps 0x34(%rcx),%xmm5 + 43a6d6: 66 0f da f2 pminub %xmm2,%xmm6 + 43a6da: 66 0f da fd pminub %xmm5,%xmm7 + 43a6de: 66 0f da fe pminub %xmm6,%xmm7 + 43a6e2: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 43a6e6: 66 0f d7 c7 pmovmskb %xmm7,%eax + 43a6ea: 0f 28 fd movaps %xmm5,%xmm7 + 43a6ed: 66 0f 3a 0f ec 0c palignr $0xc,%xmm4,%xmm5 + 43a6f3: 48 85 c0 test %rax,%rax + 43a6f6: 66 0f 3a 0f e3 0c palignr $0xc,%xmm3,%xmm4 + 43a6fc: 0f 85 06 ff ff ff jne 43a608 <__stpcpy_ssse3+0x10e8> + 43a702: 66 0f 3a 0f da 0c palignr $0xc,%xmm2,%xmm3 + 43a708: 48 8d 49 40 lea 0x40(%rcx),%rcx + 43a70c: 66 0f 3a 0f d1 0c palignr $0xc,%xmm1,%xmm2 + 43a712: 0f 28 cf movaps %xmm7,%xmm1 + 43a715: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) + 43a719: 0f 29 62 20 movaps %xmm4,0x20(%rdx) + 43a71d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) + 43a721: 0f 29 12 movaps %xmm2,(%rdx) + 43a724: 48 8d 52 40 lea 0x40(%rdx),%rdx + 43a728: eb 96 jmp 43a6c0 <__stpcpy_ssse3+0x11a0> + 43a72a: 44 8b 09 mov (%rcx),%r9d + 43a72d: 48 c7 c6 04 00 00 00 mov $0x4,%rsi + 43a734: 44 89 0a mov %r9d,(%rdx) + 43a737: e9 c4 03 00 00 jmpq 43ab00 <__stpcpy_ssse3+0x15e0> + 43a73c: 0f 1f 40 00 nopl 0x0(%rax) + 43a740: 0f 28 49 f3 movaps -0xd(%rcx),%xmm1 + 43a744: 0f 28 51 03 movaps 0x3(%rcx),%xmm2 + 43a748: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a74c: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a750: 0f 28 da movaps %xmm2,%xmm3 + 43a753: 48 85 c0 test %rax,%rax + 43a756: 0f 85 0e 01 00 00 jne 43a86a <__stpcpy_ssse3+0x134a> + 43a75c: 66 0f 3a 0f d1 0d palignr $0xd,%xmm1,%xmm2 + 43a762: 0f 29 12 movaps %xmm2,(%rdx) + 43a765: 0f 28 51 13 movaps 0x13(%rcx),%xmm2 + 43a769: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a76d: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a771: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a775: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43a779: 0f 28 ca movaps %xmm2,%xmm1 + 43a77c: 48 85 c0 test %rax,%rax + 43a77f: 0f 85 e5 00 00 00 jne 43a86a <__stpcpy_ssse3+0x134a> + 43a785: 66 0f 3a 0f d3 0d palignr $0xd,%xmm3,%xmm2 + 43a78b: 0f 29 12 movaps %xmm2,(%rdx) + 43a78e: 0f 28 51 13 movaps 0x13(%rcx),%xmm2 + 43a792: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a796: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a79a: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a79e: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43a7a2: 0f 28 da movaps %xmm2,%xmm3 + 43a7a5: 48 85 c0 test %rax,%rax + 43a7a8: 0f 85 bc 00 00 00 jne 43a86a <__stpcpy_ssse3+0x134a> + 43a7ae: 66 0f 3a 0f d1 0d palignr $0xd,%xmm1,%xmm2 + 43a7b4: 0f 29 12 movaps %xmm2,(%rdx) + 43a7b7: 0f 28 51 13 movaps 0x13(%rcx),%xmm2 + 43a7bb: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a7bf: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a7c3: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a7c7: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43a7cb: 48 85 c0 test %rax,%rax + 43a7ce: 0f 85 96 00 00 00 jne 43a86a <__stpcpy_ssse3+0x134a> + 43a7d4: 66 0f 3a 0f d3 0d palignr $0xd,%xmm3,%xmm2 + 43a7da: 0f 29 12 movaps %xmm2,(%rdx) + 43a7dd: 48 8d 49 13 lea 0x13(%rcx),%rcx + 43a7e1: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a7e5: 48 89 c8 mov %rcx,%rax + 43a7e8: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 43a7ec: 48 29 c8 sub %rcx,%rax + 43a7ef: 48 8d 49 fd lea -0x3(%rcx),%rcx + 43a7f3: 48 29 c2 sub %rax,%rdx + 43a7f6: 0f 28 49 f3 movaps -0xd(%rcx),%xmm1 + 43a7fa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43a800: 0f 28 51 03 movaps 0x3(%rcx),%xmm2 + 43a804: 0f 28 59 13 movaps 0x13(%rcx),%xmm3 + 43a808: 0f 28 f3 movaps %xmm3,%xmm6 + 43a80b: 0f 28 61 23 movaps 0x23(%rcx),%xmm4 + 43a80f: 0f 28 fc movaps %xmm4,%xmm7 + 43a812: 0f 28 69 33 movaps 0x33(%rcx),%xmm5 + 43a816: 66 0f da f2 pminub %xmm2,%xmm6 + 43a81a: 66 0f da fd pminub %xmm5,%xmm7 + 43a81e: 66 0f da fe pminub %xmm6,%xmm7 + 43a822: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 43a826: 66 0f d7 c7 pmovmskb %xmm7,%eax + 43a82a: 0f 28 fd movaps %xmm5,%xmm7 + 43a82d: 66 0f 3a 0f ec 0d palignr $0xd,%xmm4,%xmm5 + 43a833: 48 85 c0 test %rax,%rax + 43a836: 66 0f 3a 0f e3 0d palignr $0xd,%xmm3,%xmm4 + 43a83c: 0f 85 06 ff ff ff jne 43a748 <__stpcpy_ssse3+0x1228> + 43a842: 66 0f 3a 0f da 0d palignr $0xd,%xmm2,%xmm3 + 43a848: 48 8d 49 40 lea 0x40(%rcx),%rcx + 43a84c: 66 0f 3a 0f d1 0d palignr $0xd,%xmm1,%xmm2 + 43a852: 0f 28 cf movaps %xmm7,%xmm1 + 43a855: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) + 43a859: 0f 29 62 20 movaps %xmm4,0x20(%rdx) + 43a85d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) + 43a861: 0f 29 12 movaps %xmm2,(%rdx) + 43a864: 48 8d 52 40 lea 0x40(%rdx),%rdx + 43a868: eb 96 jmp 43a800 <__stpcpy_ssse3+0x12e0> + 43a86a: 44 8b 49 ff mov -0x1(%rcx),%r9d + 43a86e: 48 c7 c6 03 00 00 00 mov $0x3,%rsi + 43a875: 44 89 4a ff mov %r9d,-0x1(%rdx) + 43a879: e9 82 02 00 00 jmpq 43ab00 <__stpcpy_ssse3+0x15e0> + 43a87e: 66 90 xchg %ax,%ax + 43a880: 0f 28 49 f2 movaps -0xe(%rcx),%xmm1 + 43a884: 0f 28 51 02 movaps 0x2(%rcx),%xmm2 + 43a888: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a88c: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a890: 0f 28 da movaps %xmm2,%xmm3 + 43a893: 48 85 c0 test %rax,%rax + 43a896: 0f 85 0e 01 00 00 jne 43a9aa <__stpcpy_ssse3+0x148a> + 43a89c: 66 0f 3a 0f d1 0e palignr $0xe,%xmm1,%xmm2 + 43a8a2: 0f 29 12 movaps %xmm2,(%rdx) + 43a8a5: 0f 28 51 12 movaps 0x12(%rcx),%xmm2 + 43a8a9: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a8ad: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a8b1: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a8b5: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43a8b9: 0f 28 ca movaps %xmm2,%xmm1 + 43a8bc: 48 85 c0 test %rax,%rax + 43a8bf: 0f 85 e5 00 00 00 jne 43a9aa <__stpcpy_ssse3+0x148a> + 43a8c5: 66 0f 3a 0f d3 0e palignr $0xe,%xmm3,%xmm2 + 43a8cb: 0f 29 12 movaps %xmm2,(%rdx) + 43a8ce: 0f 28 51 12 movaps 0x12(%rcx),%xmm2 + 43a8d2: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a8d6: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a8da: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a8de: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43a8e2: 0f 28 da movaps %xmm2,%xmm3 + 43a8e5: 48 85 c0 test %rax,%rax + 43a8e8: 0f 85 bc 00 00 00 jne 43a9aa <__stpcpy_ssse3+0x148a> + 43a8ee: 66 0f 3a 0f d1 0e palignr $0xe,%xmm1,%xmm2 + 43a8f4: 0f 29 12 movaps %xmm2,(%rdx) + 43a8f7: 0f 28 51 12 movaps 0x12(%rcx),%xmm2 + 43a8fb: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a8ff: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a903: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a907: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43a90b: 48 85 c0 test %rax,%rax + 43a90e: 0f 85 96 00 00 00 jne 43a9aa <__stpcpy_ssse3+0x148a> + 43a914: 66 0f 3a 0f d3 0e palignr $0xe,%xmm3,%xmm2 + 43a91a: 0f 29 12 movaps %xmm2,(%rdx) + 43a91d: 48 8d 49 12 lea 0x12(%rcx),%rcx + 43a921: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a925: 48 89 c8 mov %rcx,%rax + 43a928: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 43a92c: 48 29 c8 sub %rcx,%rax + 43a92f: 48 8d 49 fe lea -0x2(%rcx),%rcx + 43a933: 48 29 c2 sub %rax,%rdx + 43a936: 0f 28 49 f2 movaps -0xe(%rcx),%xmm1 + 43a93a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43a940: 0f 28 51 02 movaps 0x2(%rcx),%xmm2 + 43a944: 0f 28 59 12 movaps 0x12(%rcx),%xmm3 + 43a948: 0f 28 f3 movaps %xmm3,%xmm6 + 43a94b: 0f 28 61 22 movaps 0x22(%rcx),%xmm4 + 43a94f: 0f 28 fc movaps %xmm4,%xmm7 + 43a952: 0f 28 69 32 movaps 0x32(%rcx),%xmm5 + 43a956: 66 0f da f2 pminub %xmm2,%xmm6 + 43a95a: 66 0f da fd pminub %xmm5,%xmm7 + 43a95e: 66 0f da fe pminub %xmm6,%xmm7 + 43a962: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 43a966: 66 0f d7 c7 pmovmskb %xmm7,%eax + 43a96a: 0f 28 fd movaps %xmm5,%xmm7 + 43a96d: 66 0f 3a 0f ec 0e palignr $0xe,%xmm4,%xmm5 + 43a973: 48 85 c0 test %rax,%rax + 43a976: 66 0f 3a 0f e3 0e palignr $0xe,%xmm3,%xmm4 + 43a97c: 0f 85 06 ff ff ff jne 43a888 <__stpcpy_ssse3+0x1368> + 43a982: 66 0f 3a 0f da 0e palignr $0xe,%xmm2,%xmm3 + 43a988: 48 8d 49 40 lea 0x40(%rcx),%rcx + 43a98c: 66 0f 3a 0f d1 0e palignr $0xe,%xmm1,%xmm2 + 43a992: 0f 28 cf movaps %xmm7,%xmm1 + 43a995: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) + 43a999: 0f 29 62 20 movaps %xmm4,0x20(%rdx) + 43a99d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) + 43a9a1: 0f 29 12 movaps %xmm2,(%rdx) + 43a9a4: 48 8d 52 40 lea 0x40(%rdx),%rdx + 43a9a8: eb 96 jmp 43a940 <__stpcpy_ssse3+0x1420> + 43a9aa: 44 8b 49 fe mov -0x2(%rcx),%r9d + 43a9ae: 48 c7 c6 02 00 00 00 mov $0x2,%rsi + 43a9b5: 44 89 4a fe mov %r9d,-0x2(%rdx) + 43a9b9: e9 42 01 00 00 jmpq 43ab00 <__stpcpy_ssse3+0x15e0> + 43a9be: 66 90 xchg %ax,%ax + 43a9c0: 0f 28 49 f1 movaps -0xf(%rcx),%xmm1 + 43a9c4: 0f 28 51 01 movaps 0x1(%rcx),%xmm2 + 43a9c8: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a9cc: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a9d0: 0f 28 da movaps %xmm2,%xmm3 + 43a9d3: 48 85 c0 test %rax,%rax + 43a9d6: 0f 85 0e 01 00 00 jne 43aaea <__stpcpy_ssse3+0x15ca> + 43a9dc: 66 0f 3a 0f d1 0f palignr $0xf,%xmm1,%xmm2 + 43a9e2: 0f 29 12 movaps %xmm2,(%rdx) + 43a9e5: 0f 28 51 11 movaps 0x11(%rcx),%xmm2 + 43a9e9: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43a9ed: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43a9f1: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43a9f5: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43a9f9: 0f 28 ca movaps %xmm2,%xmm1 + 43a9fc: 48 85 c0 test %rax,%rax + 43a9ff: 0f 85 e5 00 00 00 jne 43aaea <__stpcpy_ssse3+0x15ca> + 43aa05: 66 0f 3a 0f d3 0f palignr $0xf,%xmm3,%xmm2 + 43aa0b: 0f 29 12 movaps %xmm2,(%rdx) + 43aa0e: 0f 28 51 11 movaps 0x11(%rcx),%xmm2 + 43aa12: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43aa16: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43aa1a: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43aa1e: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43aa22: 0f 28 da movaps %xmm2,%xmm3 + 43aa25: 48 85 c0 test %rax,%rax + 43aa28: 0f 85 bc 00 00 00 jne 43aaea <__stpcpy_ssse3+0x15ca> + 43aa2e: 66 0f 3a 0f d1 0f palignr $0xf,%xmm1,%xmm2 + 43aa34: 0f 29 12 movaps %xmm2,(%rdx) + 43aa37: 0f 28 51 11 movaps 0x11(%rcx),%xmm2 + 43aa3b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43aa3f: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43aa43: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43aa47: 48 8d 49 10 lea 0x10(%rcx),%rcx + 43aa4b: 48 85 c0 test %rax,%rax + 43aa4e: 0f 85 96 00 00 00 jne 43aaea <__stpcpy_ssse3+0x15ca> + 43aa54: 66 0f 3a 0f d3 0f palignr $0xf,%xmm3,%xmm2 + 43aa5a: 0f 29 12 movaps %xmm2,(%rdx) + 43aa5d: 48 8d 49 11 lea 0x11(%rcx),%rcx + 43aa61: 48 8d 52 10 lea 0x10(%rdx),%rdx + 43aa65: 48 89 c8 mov %rcx,%rax + 43aa68: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx + 43aa6c: 48 29 c8 sub %rcx,%rax + 43aa6f: 48 8d 49 ff lea -0x1(%rcx),%rcx + 43aa73: 48 29 c2 sub %rax,%rdx + 43aa76: 0f 28 49 f1 movaps -0xf(%rcx),%xmm1 + 43aa7a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43aa80: 0f 28 51 01 movaps 0x1(%rcx),%xmm2 + 43aa84: 0f 28 59 11 movaps 0x11(%rcx),%xmm3 + 43aa88: 0f 28 f3 movaps %xmm3,%xmm6 + 43aa8b: 0f 28 61 21 movaps 0x21(%rcx),%xmm4 + 43aa8f: 0f 28 fc movaps %xmm4,%xmm7 + 43aa92: 0f 28 69 31 movaps 0x31(%rcx),%xmm5 + 43aa96: 66 0f da f2 pminub %xmm2,%xmm6 + 43aa9a: 66 0f da fd pminub %xmm5,%xmm7 + 43aa9e: 66 0f da fe pminub %xmm6,%xmm7 + 43aaa2: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 43aaa6: 66 0f d7 c7 pmovmskb %xmm7,%eax + 43aaaa: 0f 28 fd movaps %xmm5,%xmm7 + 43aaad: 66 0f 3a 0f ec 0f palignr $0xf,%xmm4,%xmm5 + 43aab3: 48 85 c0 test %rax,%rax + 43aab6: 66 0f 3a 0f e3 0f palignr $0xf,%xmm3,%xmm4 + 43aabc: 0f 85 06 ff ff ff jne 43a9c8 <__stpcpy_ssse3+0x14a8> + 43aac2: 66 0f 3a 0f da 0f palignr $0xf,%xmm2,%xmm3 + 43aac8: 48 8d 49 40 lea 0x40(%rcx),%rcx + 43aacc: 66 0f 3a 0f d1 0f palignr $0xf,%xmm1,%xmm2 + 43aad2: 0f 28 cf movaps %xmm7,%xmm1 + 43aad5: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) + 43aad9: 0f 29 62 20 movaps %xmm4,0x20(%rdx) + 43aadd: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) + 43aae1: 0f 29 12 movaps %xmm2,(%rdx) + 43aae4: 48 8d 52 40 lea 0x40(%rdx),%rdx + 43aae8: eb 96 jmp 43aa80 <__stpcpy_ssse3+0x1560> + 43aaea: 44 8b 49 fd mov -0x3(%rcx),%r9d + 43aaee: 48 c7 c6 01 00 00 00 mov $0x1,%rsi + 43aaf5: 44 89 4a fd mov %r9d,-0x3(%rdx) + 43aaf9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43ab00: 48 01 f2 add %rsi,%rdx + 43ab03: 48 01 f1 add %rsi,%rcx + 43ab06: 84 c0 test %al,%al + 43ab08: 74 56 je 43ab60 <__stpcpy_ssse3+0x1640> + 43ab0a: a8 01 test $0x1,%al + 43ab0c: 0f 85 ae 00 00 00 jne 43abc0 <__stpcpy_ssse3+0x16a0> + 43ab12: a8 02 test $0x2,%al + 43ab14: 0f 85 b6 00 00 00 jne 43abd0 <__stpcpy_ssse3+0x16b0> + 43ab1a: a8 04 test $0x4,%al + 43ab1c: 0f 85 be 00 00 00 jne 43abe0 <__stpcpy_ssse3+0x16c0> + 43ab22: a8 08 test $0x8,%al + 43ab24: 0f 85 d6 00 00 00 jne 43ac00 <__stpcpy_ssse3+0x16e0> + 43ab2a: a8 10 test $0x10,%al + 43ab2c: 0f 85 de 00 00 00 jne 43ac10 <__stpcpy_ssse3+0x16f0> + 43ab32: a8 20 test $0x20,%al + 43ab34: 0f 85 e6 00 00 00 jne 43ac20 <__stpcpy_ssse3+0x1700> + 43ab3a: a8 40 test $0x40,%al + 43ab3c: 0f 85 fe 00 00 00 jne 43ac40 <__stpcpy_ssse3+0x1720> + 43ab42: 0f 1f 40 00 nopl 0x0(%rax) + 43ab46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43ab4d: 00 00 00 + 43ab50: 48 8b 01 mov (%rcx),%rax + 43ab53: 48 89 02 mov %rax,(%rdx) + 43ab56: 48 8d 42 07 lea 0x7(%rdx),%rax + 43ab5a: c3 retq + 43ab5b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43ab60: f6 c4 01 test $0x1,%ah + 43ab63: 0f 85 e7 00 00 00 jne 43ac50 <__stpcpy_ssse3+0x1730> + 43ab69: f6 c4 02 test $0x2,%ah + 43ab6c: 0f 85 fe 00 00 00 jne 43ac70 <__stpcpy_ssse3+0x1750> + 43ab72: f6 c4 04 test $0x4,%ah + 43ab75: 0f 85 15 01 00 00 jne 43ac90 <__stpcpy_ssse3+0x1770> + 43ab7b: f6 c4 08 test $0x8,%ah + 43ab7e: 0f 85 2c 01 00 00 jne 43acb0 <__stpcpy_ssse3+0x1790> + 43ab84: f6 c4 10 test $0x10,%ah + 43ab87: 0f 85 43 01 00 00 jne 43acd0 <__stpcpy_ssse3+0x17b0> + 43ab8d: f6 c4 20 test $0x20,%ah + 43ab90: 0f 85 5a 01 00 00 jne 43acf0 <__stpcpy_ssse3+0x17d0> + 43ab96: f6 c4 40 test $0x40,%ah + 43ab99: 0f 85 71 01 00 00 jne 43ad10 <__stpcpy_ssse3+0x17f0> + 43ab9f: 90 nop + 43aba0: 48 8b 01 mov (%rcx),%rax + 43aba3: 48 89 02 mov %rax,(%rdx) + 43aba6: 48 8b 41 08 mov 0x8(%rcx),%rax + 43abaa: 48 89 42 08 mov %rax,0x8(%rdx) + 43abae: 48 8d 42 0f lea 0xf(%rdx),%rax + 43abb2: c3 retq + 43abb3: 0f 1f 00 nopl (%rax) + 43abb6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43abbd: 00 00 00 + 43abc0: 8a 01 mov (%rcx),%al + 43abc2: 88 02 mov %al,(%rdx) + 43abc4: 48 8d 02 lea (%rdx),%rax + 43abc7: c3 retq + 43abc8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 43abcf: 00 + 43abd0: 66 8b 01 mov (%rcx),%ax + 43abd3: 66 89 02 mov %ax,(%rdx) + 43abd6: 48 8d 42 01 lea 0x1(%rdx),%rax + 43abda: c3 retq + 43abdb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43abe0: 66 8b 01 mov (%rcx),%ax + 43abe3: 66 89 02 mov %ax,(%rdx) + 43abe6: 8a 41 02 mov 0x2(%rcx),%al + 43abe9: 88 42 02 mov %al,0x2(%rdx) + 43abec: 48 8d 42 02 lea 0x2(%rdx),%rax + 43abf0: c3 retq + 43abf1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43abf6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43abfd: 00 00 00 + 43ac00: 8b 01 mov (%rcx),%eax + 43ac02: 89 02 mov %eax,(%rdx) + 43ac04: 48 8d 42 03 lea 0x3(%rdx),%rax + 43ac08: c3 retq + 43ac09: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43ac10: 8b 01 mov (%rcx),%eax + 43ac12: 89 02 mov %eax,(%rdx) + 43ac14: 8a 41 04 mov 0x4(%rcx),%al + 43ac17: 88 42 04 mov %al,0x4(%rdx) + 43ac1a: 48 8d 42 04 lea 0x4(%rdx),%rax + 43ac1e: c3 retq + 43ac1f: 90 nop + 43ac20: 8b 01 mov (%rcx),%eax + 43ac22: 89 02 mov %eax,(%rdx) + 43ac24: 66 8b 41 04 mov 0x4(%rcx),%ax + 43ac28: 66 89 42 04 mov %ax,0x4(%rdx) + 43ac2c: 48 8d 42 05 lea 0x5(%rdx),%rax + 43ac30: c3 retq + 43ac31: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43ac36: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43ac3d: 00 00 00 + 43ac40: 8b 01 mov (%rcx),%eax + 43ac42: 89 02 mov %eax,(%rdx) + 43ac44: 8b 41 03 mov 0x3(%rcx),%eax + 43ac47: 89 42 03 mov %eax,0x3(%rdx) + 43ac4a: 48 8d 42 06 lea 0x6(%rdx),%rax + 43ac4e: c3 retq + 43ac4f: 90 nop + 43ac50: 48 8b 01 mov (%rcx),%rax + 43ac53: 48 89 02 mov %rax,(%rdx) + 43ac56: 8b 41 05 mov 0x5(%rcx),%eax + 43ac59: 89 42 05 mov %eax,0x5(%rdx) + 43ac5c: 48 8d 42 08 lea 0x8(%rdx),%rax + 43ac60: c3 retq + 43ac61: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43ac66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43ac6d: 00 00 00 + 43ac70: 48 8b 01 mov (%rcx),%rax + 43ac73: 48 89 02 mov %rax,(%rdx) + 43ac76: 8b 41 06 mov 0x6(%rcx),%eax + 43ac79: 89 42 06 mov %eax,0x6(%rdx) + 43ac7c: 48 8d 42 09 lea 0x9(%rdx),%rax + 43ac80: c3 retq + 43ac81: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43ac86: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43ac8d: 00 00 00 + 43ac90: 48 8b 01 mov (%rcx),%rax + 43ac93: 48 89 02 mov %rax,(%rdx) + 43ac96: 8b 41 07 mov 0x7(%rcx),%eax + 43ac99: 89 42 07 mov %eax,0x7(%rdx) + 43ac9c: 48 8d 42 0a lea 0xa(%rdx),%rax + 43aca0: c3 retq + 43aca1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43aca6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43acad: 00 00 00 + 43acb0: 48 8b 01 mov (%rcx),%rax + 43acb3: 48 89 02 mov %rax,(%rdx) + 43acb6: 8b 41 08 mov 0x8(%rcx),%eax + 43acb9: 89 42 08 mov %eax,0x8(%rdx) + 43acbc: 48 8d 42 0b lea 0xb(%rdx),%rax + 43acc0: c3 retq + 43acc1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43acc6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43accd: 00 00 00 + 43acd0: 48 8b 01 mov (%rcx),%rax + 43acd3: 48 89 02 mov %rax,(%rdx) + 43acd6: 48 8b 41 05 mov 0x5(%rcx),%rax + 43acda: 48 89 42 05 mov %rax,0x5(%rdx) + 43acde: 48 8d 42 0c lea 0xc(%rdx),%rax + 43ace2: c3 retq + 43ace3: 0f 1f 00 nopl (%rax) + 43ace6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43aced: 00 00 00 + 43acf0: 48 8b 01 mov (%rcx),%rax + 43acf3: 48 89 02 mov %rax,(%rdx) + 43acf6: 48 8b 41 06 mov 0x6(%rcx),%rax + 43acfa: 48 89 42 06 mov %rax,0x6(%rdx) + 43acfe: 48 8d 42 0d lea 0xd(%rdx),%rax + 43ad02: c3 retq + 43ad03: 0f 1f 00 nopl (%rax) + 43ad06: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43ad0d: 00 00 00 + 43ad10: 48 8b 01 mov (%rcx),%rax + 43ad13: 48 89 02 mov %rax,(%rdx) + 43ad16: 48 8b 41 07 mov 0x7(%rcx),%rax + 43ad1a: 48 89 42 07 mov %rax,0x7(%rdx) + 43ad1e: 48 8d 42 0e lea 0xe(%rdx),%rax + 43ad22: c3 retq + 43ad23: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43ad2a: 00 00 00 + 43ad2d: 0f 1f 00 nopl (%rax) + +000000000043ad30 <__strcpy_sse2_unaligned>: + 43ad30: 48 89 f1 mov %rsi,%rcx + 43ad33: 48 89 f8 mov %rdi,%rax + 43ad36: 48 83 e1 3f and $0x3f,%rcx + 43ad3a: 48 83 f9 20 cmp $0x20,%rcx + 43ad3e: 0f 86 0f 02 00 00 jbe 43af53 <__strcpy_sse2_unaligned+0x223> + 43ad44: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi + 43ad48: 48 83 e1 0f and $0xf,%rcx + 43ad4c: 66 0f ef c0 pxor %xmm0,%xmm0 + 43ad50: 66 0f ef c9 pxor %xmm1,%xmm1 + 43ad54: 66 0f 74 0e pcmpeqb (%rsi),%xmm1 + 43ad58: 66 0f d7 d1 pmovmskb %xmm1,%edx + 43ad5c: 48 d3 ea shr %cl,%rdx + 43ad5f: 48 85 d2 test %rdx,%rdx + 43ad62: 0f 85 48 02 00 00 jne 43afb0 <__strcpy_sse2_unaligned+0x280> + 43ad68: 66 0f 74 46 10 pcmpeqb 0x10(%rsi),%xmm0 + 43ad6d: 66 0f d7 d0 pmovmskb %xmm0,%edx + 43ad71: 48 85 d2 test %rdx,%rdx + 43ad74: 0f 85 76 02 00 00 jne 43aff0 <__strcpy_sse2_unaligned+0x2c0> + 43ad7a: f3 0f 6f 0c 0e movdqu (%rsi,%rcx,1),%xmm1 + 43ad7f: f3 0f 7f 0f movdqu %xmm1,(%rdi) + 43ad83: 0f 1f 00 nopl (%rax) + 43ad86: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43ad8d: 00 00 00 + 43ad90: 48 29 cf sub %rcx,%rdi + 43ad93: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 43ad9a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 43ad9f: 0f 28 54 0e 10 movaps 0x10(%rsi,%rcx,1),%xmm2 + 43ada4: f3 0f 7f 0c 0f movdqu %xmm1,(%rdi,%rcx,1) + 43ada9: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43adad: 66 0f d7 d0 pmovmskb %xmm0,%edx + 43adb1: 48 83 c1 10 add $0x10,%rcx + 43adb5: 48 85 d2 test %rdx,%rdx + 43adb8: 0f 85 d2 01 00 00 jne 43af90 <__strcpy_sse2_unaligned+0x260> + 43adbe: 0f 28 5c 0e 10 movaps 0x10(%rsi,%rcx,1),%xmm3 + 43adc3: f3 0f 7f 14 0f movdqu %xmm2,(%rdi,%rcx,1) + 43adc8: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 43adcc: 66 0f d7 d0 pmovmskb %xmm0,%edx + 43add0: 48 83 c1 10 add $0x10,%rcx + 43add4: 48 85 d2 test %rdx,%rdx + 43add7: 0f 85 b3 01 00 00 jne 43af90 <__strcpy_sse2_unaligned+0x260> + 43addd: 0f 28 64 0e 10 movaps 0x10(%rsi,%rcx,1),%xmm4 + 43ade2: f3 0f 7f 1c 0f movdqu %xmm3,(%rdi,%rcx,1) + 43ade7: 66 0f 74 c4 pcmpeqb %xmm4,%xmm0 + 43adeb: 66 0f d7 d0 pmovmskb %xmm0,%edx + 43adef: 48 83 c1 10 add $0x10,%rcx + 43adf3: 48 85 d2 test %rdx,%rdx + 43adf6: 0f 85 94 01 00 00 jne 43af90 <__strcpy_sse2_unaligned+0x260> + 43adfc: 0f 28 4c 0e 10 movaps 0x10(%rsi,%rcx,1),%xmm1 + 43ae01: f3 0f 7f 24 0f movdqu %xmm4,(%rdi,%rcx,1) + 43ae06: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 43ae0a: 66 0f d7 d0 pmovmskb %xmm0,%edx + 43ae0e: 48 83 c1 10 add $0x10,%rcx + 43ae12: 48 85 d2 test %rdx,%rdx + 43ae15: 0f 85 75 01 00 00 jne 43af90 <__strcpy_sse2_unaligned+0x260> + 43ae1b: 0f 28 54 0e 10 movaps 0x10(%rsi,%rcx,1),%xmm2 + 43ae20: f3 0f 7f 0c 0f movdqu %xmm1,(%rdi,%rcx,1) + 43ae25: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43ae29: 66 0f d7 d0 pmovmskb %xmm0,%edx + 43ae2d: 48 83 c1 10 add $0x10,%rcx + 43ae31: 48 85 d2 test %rdx,%rdx + 43ae34: 0f 85 56 01 00 00 jne 43af90 <__strcpy_sse2_unaligned+0x260> + 43ae3a: 0f 28 5c 0e 10 movaps 0x10(%rsi,%rcx,1),%xmm3 + 43ae3f: f3 0f 7f 14 0f movdqu %xmm2,(%rdi,%rcx,1) + 43ae44: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 43ae48: 66 0f d7 d0 pmovmskb %xmm0,%edx + 43ae4c: 48 83 c1 10 add $0x10,%rcx + 43ae50: 48 85 d2 test %rdx,%rdx + 43ae53: 0f 85 37 01 00 00 jne 43af90 <__strcpy_sse2_unaligned+0x260> + 43ae59: f3 0f 7f 1c 0f movdqu %xmm3,(%rdi,%rcx,1) + 43ae5e: 48 89 f2 mov %rsi,%rdx + 43ae61: 48 8d 74 0e 10 lea 0x10(%rsi,%rcx,1),%rsi + 43ae66: 48 83 e6 c0 and $0xffffffffffffffc0,%rsi + 43ae6a: 48 29 f2 sub %rsi,%rdx + 43ae6d: 48 29 d7 sub %rdx,%rdi + 43ae70: 0f 28 16 movaps (%rsi),%xmm2 + 43ae73: 0f 28 e2 movaps %xmm2,%xmm4 + 43ae76: 0f 28 6e 10 movaps 0x10(%rsi),%xmm5 + 43ae7a: 0f 28 5e 20 movaps 0x20(%rsi),%xmm3 + 43ae7e: 0f 28 f3 movaps %xmm3,%xmm6 + 43ae81: 0f 28 7e 30 movaps 0x30(%rsi),%xmm7 + 43ae85: 66 0f da d5 pminub %xmm5,%xmm2 + 43ae89: 66 0f da df pminub %xmm7,%xmm3 + 43ae8d: 66 0f da da pminub %xmm2,%xmm3 + 43ae91: 66 0f 74 d8 pcmpeqb %xmm0,%xmm3 + 43ae95: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43ae99: 48 85 d2 test %rdx,%rdx + 43ae9c: 75 4b jne 43aee9 <__strcpy_sse2_unaligned+0x1b9> + 43ae9e: 48 83 c7 40 add $0x40,%rdi + 43aea2: 48 83 c6 40 add $0x40,%rsi + 43aea6: f3 0f 7f 67 c0 movdqu %xmm4,-0x40(%rdi) + 43aeab: 0f 28 16 movaps (%rsi),%xmm2 + 43aeae: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 43aeb2: f3 0f 7f 6f d0 movdqu %xmm5,-0x30(%rdi) + 43aeb7: 0f 28 6e 10 movaps 0x10(%rsi),%xmm5 + 43aebb: 66 0f da d5 pminub %xmm5,%xmm2 + 43aebf: 0f 28 5e 20 movaps 0x20(%rsi),%xmm3 + 43aec3: f3 0f 7f 77 e0 movdqu %xmm6,-0x20(%rdi) + 43aec8: 0f 28 f3 movaps %xmm3,%xmm6 + 43aecb: f3 0f 7f 7f f0 movdqu %xmm7,-0x10(%rdi) + 43aed0: 0f 28 7e 30 movaps 0x30(%rsi),%xmm7 + 43aed4: 66 0f da df pminub %xmm7,%xmm3 + 43aed8: 66 0f da da pminub %xmm2,%xmm3 + 43aedc: 66 0f 74 d8 pcmpeqb %xmm0,%xmm3 + 43aee0: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43aee4: 48 85 d2 test %rdx,%rdx + 43aee7: 74 b5 je 43ae9e <__strcpy_sse2_unaligned+0x16e> + 43aee9: 66 0f ef c9 pxor %xmm1,%xmm1 + 43aeed: 66 0f 74 c4 pcmpeqb %xmm4,%xmm0 + 43aef1: 66 0f 74 cd pcmpeqb %xmm5,%xmm1 + 43aef5: 66 0f d7 d0 pmovmskb %xmm0,%edx + 43aef9: 66 0f d7 c9 pmovmskb %xmm1,%ecx + 43aefd: 48 85 d2 test %rdx,%rdx + 43af00: 0f 85 0a 01 00 00 jne 43b010 <__strcpy_sse2_unaligned+0x2e0> + 43af06: 48 85 c9 test %rcx,%rcx + 43af09: 0f 85 21 01 00 00 jne 43b030 <__strcpy_sse2_unaligned+0x300> + 43af0f: 66 0f 74 c6 pcmpeqb %xmm6,%xmm0 + 43af13: 66 0f 74 cf pcmpeqb %xmm7,%xmm1 + 43af17: 66 0f d7 d0 pmovmskb %xmm0,%edx + 43af1b: 66 0f d7 c9 pmovmskb %xmm1,%ecx + 43af1f: 48 85 d2 test %rdx,%rdx + 43af22: 0f 85 38 01 00 00 jne 43b060 <__strcpy_sse2_unaligned+0x330> + 43af28: 48 0f bc d1 bsf %rcx,%rdx + 43af2c: f3 0f 7f 27 movdqu %xmm4,(%rdi) + 43af30: f3 0f 7f 6f 10 movdqu %xmm5,0x10(%rdi) + 43af35: f3 0f 7f 77 20 movdqu %xmm6,0x20(%rdi) + 43af3a: 48 83 c6 30 add $0x30,%rsi + 43af3e: 48 83 c7 30 add $0x30,%rdi + 43af42: 4c 8d 1d 67 8b 06 00 lea 0x68b67(%rip),%r11 # 4a3ab0 + 43af49: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx + 43af4d: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx + 43af51: ff e1 jmpq *%rcx + 43af53: 66 0f ef c0 pxor %xmm0,%xmm0 + 43af57: f3 0f 6f 0e movdqu (%rsi),%xmm1 + 43af5b: f3 0f 6f 56 10 movdqu 0x10(%rsi),%xmm2 + 43af60: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 43af64: 66 0f d7 d0 pmovmskb %xmm0,%edx + 43af68: 48 85 d2 test %rdx,%rdx + 43af6b: 75 6b jne 43afd8 <__strcpy_sse2_unaligned+0x2a8> + 43af6d: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43af71: f3 0f 7f 0f movdqu %xmm1,(%rdi) + 43af75: 66 0f d7 d0 pmovmskb %xmm0,%edx + 43af79: 48 85 d2 test %rdx,%rdx + 43af7c: 75 52 jne 43afd0 <__strcpy_sse2_unaligned+0x2a0> + 43af7e: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi + 43af82: 48 83 e1 0f and $0xf,%rcx + 43af86: e9 05 fe ff ff jmpq 43ad90 <__strcpy_sse2_unaligned+0x60> + 43af8b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43af90: 48 01 cf add %rcx,%rdi + 43af93: 48 01 ce add %rcx,%rsi + 43af96: 48 0f bc d2 bsf %rdx,%rdx + 43af9a: 4c 8d 1d 0f 8b 06 00 lea 0x68b0f(%rip),%r11 # 4a3ab0 + 43afa1: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx + 43afa5: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx + 43afa9: ff e1 jmpq *%rcx + 43afab: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43afb0: 48 01 ce add %rcx,%rsi + 43afb3: 48 0f bc d2 bsf %rdx,%rdx + 43afb7: 4c 8d 1d f2 8a 06 00 lea 0x68af2(%rip),%r11 # 4a3ab0 + 43afbe: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx + 43afc2: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx + 43afc6: ff e1 jmpq *%rcx + 43afc8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 43afcf: 00 + 43afd0: 48 83 c6 10 add $0x10,%rsi + 43afd4: 48 83 c7 10 add $0x10,%rdi + 43afd8: 48 0f bc d2 bsf %rdx,%rdx + 43afdc: 4c 8d 1d cd 8a 06 00 lea 0x68acd(%rip),%r11 # 4a3ab0 + 43afe3: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx + 43afe7: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx + 43afeb: ff e1 jmpq *%rcx + 43afed: 0f 1f 00 nopl (%rax) + 43aff0: 48 0f bc d2 bsf %rdx,%rdx + 43aff4: 48 01 ce add %rcx,%rsi + 43aff7: 48 83 c2 10 add $0x10,%rdx + 43affb: 48 29 ca sub %rcx,%rdx + 43affe: 4c 8d 1d ab 8a 06 00 lea 0x68aab(%rip),%r11 # 4a3ab0 + 43b005: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx + 43b009: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx + 43b00d: ff e1 jmpq *%rcx + 43b00f: 90 nop + 43b010: 48 0f bc d2 bsf %rdx,%rdx + 43b014: 4c 8d 1d 95 8a 06 00 lea 0x68a95(%rip),%r11 # 4a3ab0 + 43b01b: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx + 43b01f: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx + 43b023: ff e1 jmpq *%rcx + 43b025: 90 nop + 43b026: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b02d: 00 00 00 + 43b030: 48 0f bc d1 bsf %rcx,%rdx + 43b034: f3 0f 7f 27 movdqu %xmm4,(%rdi) + 43b038: 48 83 c6 10 add $0x10,%rsi + 43b03c: 48 83 c7 10 add $0x10,%rdi + 43b040: 4c 8d 1d 69 8a 06 00 lea 0x68a69(%rip),%r11 # 4a3ab0 + 43b047: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx + 43b04b: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx + 43b04f: ff e1 jmpq *%rcx + 43b051: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43b056: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b05d: 00 00 00 + 43b060: 48 0f bc d2 bsf %rdx,%rdx + 43b064: f3 0f 7f 27 movdqu %xmm4,(%rdi) + 43b068: f3 0f 7f 6f 10 movdqu %xmm5,0x10(%rdi) + 43b06d: 48 83 c6 20 add $0x20,%rsi + 43b071: 48 83 c7 20 add $0x20,%rdi + 43b075: 4c 8d 1d 34 8a 06 00 lea 0x68a34(%rip),%r11 # 4a3ab0 + 43b07c: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx + 43b080: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx + 43b084: ff e1 jmpq *%rcx + 43b086: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b08d: 00 00 00 + 43b090: 88 37 mov %dh,(%rdi) + 43b092: c3 retq + 43b093: 0f 1f 00 nopl (%rax) + 43b096: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b09d: 00 00 00 + 43b0a0: 66 8b 16 mov (%rsi),%dx + 43b0a3: 66 89 17 mov %dx,(%rdi) + 43b0a6: c3 retq + 43b0a7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 43b0ae: 00 00 + 43b0b0: 66 8b 0e mov (%rsi),%cx + 43b0b3: 66 89 0f mov %cx,(%rdi) + 43b0b6: 88 77 02 mov %dh,0x2(%rdi) + 43b0b9: c3 retq + 43b0ba: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43b0c0: 8b 16 mov (%rsi),%edx + 43b0c2: 89 17 mov %edx,(%rdi) + 43b0c4: c3 retq + 43b0c5: 90 nop + 43b0c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b0cd: 00 00 00 + 43b0d0: 8b 0e mov (%rsi),%ecx + 43b0d2: 88 77 04 mov %dh,0x4(%rdi) + 43b0d5: 89 0f mov %ecx,(%rdi) + 43b0d7: c3 retq + 43b0d8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 43b0df: 00 + 43b0e0: 8b 0e mov (%rsi),%ecx + 43b0e2: 66 8b 56 04 mov 0x4(%rsi),%dx + 43b0e6: 89 0f mov %ecx,(%rdi) + 43b0e8: 66 89 57 04 mov %dx,0x4(%rdi) + 43b0ec: c3 retq + 43b0ed: 0f 1f 00 nopl (%rax) + 43b0f0: 8b 0e mov (%rsi),%ecx + 43b0f2: 8b 56 03 mov 0x3(%rsi),%edx + 43b0f5: 89 0f mov %ecx,(%rdi) + 43b0f7: 89 57 03 mov %edx,0x3(%rdi) + 43b0fa: c3 retq + 43b0fb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43b100: 48 8b 16 mov (%rsi),%rdx + 43b103: 48 89 17 mov %rdx,(%rdi) + 43b106: c3 retq + 43b107: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 43b10e: 00 00 + 43b110: 48 8b 0e mov (%rsi),%rcx + 43b113: 88 77 08 mov %dh,0x8(%rdi) + 43b116: 48 89 0f mov %rcx,(%rdi) + 43b119: c3 retq + 43b11a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43b120: 48 8b 0e mov (%rsi),%rcx + 43b123: 66 8b 56 08 mov 0x8(%rsi),%dx + 43b127: 48 89 0f mov %rcx,(%rdi) + 43b12a: 66 89 57 08 mov %dx,0x8(%rdi) + 43b12e: c3 retq + 43b12f: 90 nop + 43b130: 48 8b 0e mov (%rsi),%rcx + 43b133: 8b 56 07 mov 0x7(%rsi),%edx + 43b136: 48 89 0f mov %rcx,(%rdi) + 43b139: 89 57 07 mov %edx,0x7(%rdi) + 43b13c: c3 retq + 43b13d: 0f 1f 00 nopl (%rax) + 43b140: 48 8b 0e mov (%rsi),%rcx + 43b143: 8b 56 08 mov 0x8(%rsi),%edx + 43b146: 48 89 0f mov %rcx,(%rdi) + 43b149: 89 57 08 mov %edx,0x8(%rdi) + 43b14c: c3 retq + 43b14d: 0f 1f 00 nopl (%rax) + 43b150: 48 8b 0e mov (%rsi),%rcx + 43b153: 48 8b 56 05 mov 0x5(%rsi),%rdx + 43b157: 48 89 0f mov %rcx,(%rdi) + 43b15a: 48 89 57 05 mov %rdx,0x5(%rdi) + 43b15e: c3 retq + 43b15f: 90 nop + 43b160: 48 8b 0e mov (%rsi),%rcx + 43b163: 48 8b 56 06 mov 0x6(%rsi),%rdx + 43b167: 48 89 0f mov %rcx,(%rdi) + 43b16a: 48 89 57 06 mov %rdx,0x6(%rdi) + 43b16e: c3 retq + 43b16f: 90 nop + 43b170: 48 8b 0e mov (%rsi),%rcx + 43b173: 48 8b 56 07 mov 0x7(%rsi),%rdx + 43b177: 48 89 0f mov %rcx,(%rdi) + 43b17a: 48 89 57 07 mov %rdx,0x7(%rdi) + 43b17e: c3 retq + 43b17f: 90 nop + 43b180: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b184: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b188: c3 retq + 43b189: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43b190: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b194: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b198: 88 77 10 mov %dh,0x10(%rdi) + 43b19b: c3 retq + 43b19c: 0f 1f 40 00 nopl 0x0(%rax) + 43b1a0: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b1a4: 66 8b 4e 10 mov 0x10(%rsi),%cx + 43b1a8: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b1ac: 66 89 4f 10 mov %cx,0x10(%rdi) + 43b1b0: c3 retq + 43b1b1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43b1b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b1bd: 00 00 00 + 43b1c0: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b1c4: 8b 4e 0f mov 0xf(%rsi),%ecx + 43b1c7: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b1cb: 89 4f 0f mov %ecx,0xf(%rdi) + 43b1ce: c3 retq + 43b1cf: 90 nop + 43b1d0: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b1d4: 8b 4e 10 mov 0x10(%rsi),%ecx + 43b1d7: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b1db: 89 4f 10 mov %ecx,0x10(%rdi) + 43b1de: c3 retq + 43b1df: 90 nop + 43b1e0: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b1e4: 8b 4e 10 mov 0x10(%rsi),%ecx + 43b1e7: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b1eb: 89 4f 10 mov %ecx,0x10(%rdi) + 43b1ee: 88 77 14 mov %dh,0x14(%rdi) + 43b1f1: c3 retq + 43b1f2: 0f 1f 40 00 nopl 0x0(%rax) + 43b1f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b1fd: 00 00 00 + 43b200: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b204: 48 8b 4e 0e mov 0xe(%rsi),%rcx + 43b208: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b20c: 48 89 4f 0e mov %rcx,0xe(%rdi) + 43b210: c3 retq + 43b211: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43b216: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b21d: 00 00 00 + 43b220: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b224: 48 8b 4e 0f mov 0xf(%rsi),%rcx + 43b228: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b22c: 48 89 4f 0f mov %rcx,0xf(%rdi) + 43b230: c3 retq + 43b231: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43b236: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b23d: 00 00 00 + 43b240: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b244: 48 8b 4e 10 mov 0x10(%rsi),%rcx + 43b248: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b24c: 48 89 4f 10 mov %rcx,0x10(%rdi) + 43b250: c3 retq + 43b251: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43b256: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b25d: 00 00 00 + 43b260: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b264: 48 8b 4e 10 mov 0x10(%rsi),%rcx + 43b268: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b26c: 48 89 4f 10 mov %rcx,0x10(%rdi) + 43b270: 88 77 18 mov %dh,0x18(%rdi) + 43b273: c3 retq + 43b274: 66 90 xchg %ax,%ax + 43b276: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b27d: 00 00 00 + 43b280: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b284: 48 8b 56 10 mov 0x10(%rsi),%rdx + 43b288: 66 8b 4e 18 mov 0x18(%rsi),%cx + 43b28c: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b290: 48 89 57 10 mov %rdx,0x10(%rdi) + 43b294: 66 89 4f 18 mov %cx,0x18(%rdi) + 43b298: c3 retq + 43b299: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43b2a0: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b2a4: 48 8b 56 10 mov 0x10(%rsi),%rdx + 43b2a8: 8b 4e 17 mov 0x17(%rsi),%ecx + 43b2ab: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b2af: 48 89 57 10 mov %rdx,0x10(%rdi) + 43b2b3: 89 4f 17 mov %ecx,0x17(%rdi) + 43b2b6: c3 retq + 43b2b7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 43b2be: 00 00 + 43b2c0: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b2c4: 48 8b 56 10 mov 0x10(%rsi),%rdx + 43b2c8: 8b 4e 18 mov 0x18(%rsi),%ecx + 43b2cb: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b2cf: 48 89 57 10 mov %rdx,0x10(%rdi) + 43b2d3: 89 4f 18 mov %ecx,0x18(%rdi) + 43b2d6: c3 retq + 43b2d7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 43b2de: 00 00 + 43b2e0: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b2e4: f3 0f 6f 56 0d movdqu 0xd(%rsi),%xmm2 + 43b2e9: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b2ed: f3 0f 7f 57 0d movdqu %xmm2,0xd(%rdi) + 43b2f2: c3 retq + 43b2f3: 0f 1f 00 nopl (%rax) + 43b2f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b2fd: 00 00 00 + 43b300: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b304: f3 0f 6f 56 0e movdqu 0xe(%rsi),%xmm2 + 43b309: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b30d: f3 0f 7f 57 0e movdqu %xmm2,0xe(%rdi) + 43b312: c3 retq + 43b313: 0f 1f 00 nopl (%rax) + 43b316: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b31d: 00 00 00 + 43b320: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b324: f3 0f 6f 56 0f movdqu 0xf(%rsi),%xmm2 + 43b329: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b32d: f3 0f 7f 57 0f movdqu %xmm2,0xf(%rdi) + 43b332: c3 retq + 43b333: 0f 1f 00 nopl (%rax) + 43b336: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b33d: 00 00 00 + 43b340: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b344: f3 0f 6f 56 10 movdqu 0x10(%rsi),%xmm2 + 43b349: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b34d: f3 0f 7f 57 10 movdqu %xmm2,0x10(%rdi) + 43b352: c3 retq + 43b353: 0f 1f 00 nopl (%rax) + 43b356: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b35d: 00 00 00 + +000000000043b360 <__stpcpy_sse2_unaligned>: + 43b360: 48 89 f1 mov %rsi,%rcx + 43b363: 48 83 e1 3f and $0x3f,%rcx + 43b367: 48 83 f9 20 cmp $0x20,%rcx + 43b36b: 0f 86 02 02 00 00 jbe 43b573 <__stpcpy_sse2_unaligned+0x213> + 43b371: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi + 43b375: 48 83 e1 0f and $0xf,%rcx + 43b379: 66 0f ef c0 pxor %xmm0,%xmm0 + 43b37d: 66 0f ef c9 pxor %xmm1,%xmm1 + 43b381: 66 0f 74 0e pcmpeqb (%rsi),%xmm1 + 43b385: 66 0f d7 d1 pmovmskb %xmm1,%edx + 43b389: 48 d3 ea shr %cl,%rdx + 43b38c: 48 85 d2 test %rdx,%rdx + 43b38f: 0f 85 3b 02 00 00 jne 43b5d0 <__stpcpy_sse2_unaligned+0x270> + 43b395: 66 0f 74 46 10 pcmpeqb 0x10(%rsi),%xmm0 + 43b39a: 66 0f d7 d0 pmovmskb %xmm0,%edx + 43b39e: 48 85 d2 test %rdx,%rdx + 43b3a1: 0f 85 69 02 00 00 jne 43b610 <__stpcpy_sse2_unaligned+0x2b0> + 43b3a7: f3 0f 6f 0c 0e movdqu (%rsi,%rcx,1),%xmm1 + 43b3ac: f3 0f 7f 0f movdqu %xmm1,(%rdi) + 43b3b0: 48 29 cf sub %rcx,%rdi + 43b3b3: 48 c7 c1 10 00 00 00 mov $0x10,%rcx + 43b3ba: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 + 43b3bf: 0f 28 54 0e 10 movaps 0x10(%rsi,%rcx,1),%xmm2 + 43b3c4: f3 0f 7f 0c 0f movdqu %xmm1,(%rdi,%rcx,1) + 43b3c9: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43b3cd: 66 0f d7 d0 pmovmskb %xmm0,%edx + 43b3d1: 48 83 c1 10 add $0x10,%rcx + 43b3d5: 48 85 d2 test %rdx,%rdx + 43b3d8: 0f 85 d2 01 00 00 jne 43b5b0 <__stpcpy_sse2_unaligned+0x250> + 43b3de: 0f 28 5c 0e 10 movaps 0x10(%rsi,%rcx,1),%xmm3 + 43b3e3: f3 0f 7f 14 0f movdqu %xmm2,(%rdi,%rcx,1) + 43b3e8: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 43b3ec: 66 0f d7 d0 pmovmskb %xmm0,%edx + 43b3f0: 48 83 c1 10 add $0x10,%rcx + 43b3f4: 48 85 d2 test %rdx,%rdx + 43b3f7: 0f 85 b3 01 00 00 jne 43b5b0 <__stpcpy_sse2_unaligned+0x250> + 43b3fd: 0f 28 64 0e 10 movaps 0x10(%rsi,%rcx,1),%xmm4 + 43b402: f3 0f 7f 1c 0f movdqu %xmm3,(%rdi,%rcx,1) + 43b407: 66 0f 74 c4 pcmpeqb %xmm4,%xmm0 + 43b40b: 66 0f d7 d0 pmovmskb %xmm0,%edx + 43b40f: 48 83 c1 10 add $0x10,%rcx + 43b413: 48 85 d2 test %rdx,%rdx + 43b416: 0f 85 94 01 00 00 jne 43b5b0 <__stpcpy_sse2_unaligned+0x250> + 43b41c: 0f 28 4c 0e 10 movaps 0x10(%rsi,%rcx,1),%xmm1 + 43b421: f3 0f 7f 24 0f movdqu %xmm4,(%rdi,%rcx,1) + 43b426: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 43b42a: 66 0f d7 d0 pmovmskb %xmm0,%edx + 43b42e: 48 83 c1 10 add $0x10,%rcx + 43b432: 48 85 d2 test %rdx,%rdx + 43b435: 0f 85 75 01 00 00 jne 43b5b0 <__stpcpy_sse2_unaligned+0x250> + 43b43b: 0f 28 54 0e 10 movaps 0x10(%rsi,%rcx,1),%xmm2 + 43b440: f3 0f 7f 0c 0f movdqu %xmm1,(%rdi,%rcx,1) + 43b445: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43b449: 66 0f d7 d0 pmovmskb %xmm0,%edx + 43b44d: 48 83 c1 10 add $0x10,%rcx + 43b451: 48 85 d2 test %rdx,%rdx + 43b454: 0f 85 56 01 00 00 jne 43b5b0 <__stpcpy_sse2_unaligned+0x250> + 43b45a: 0f 28 5c 0e 10 movaps 0x10(%rsi,%rcx,1),%xmm3 + 43b45f: f3 0f 7f 14 0f movdqu %xmm2,(%rdi,%rcx,1) + 43b464: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 + 43b468: 66 0f d7 d0 pmovmskb %xmm0,%edx + 43b46c: 48 83 c1 10 add $0x10,%rcx + 43b470: 48 85 d2 test %rdx,%rdx + 43b473: 0f 85 37 01 00 00 jne 43b5b0 <__stpcpy_sse2_unaligned+0x250> + 43b479: f3 0f 7f 1c 0f movdqu %xmm3,(%rdi,%rcx,1) + 43b47e: 48 89 f2 mov %rsi,%rdx + 43b481: 48 8d 74 0e 10 lea 0x10(%rsi,%rcx,1),%rsi + 43b486: 48 83 e6 c0 and $0xffffffffffffffc0,%rsi + 43b48a: 48 29 f2 sub %rsi,%rdx + 43b48d: 48 29 d7 sub %rdx,%rdi + 43b490: 0f 28 16 movaps (%rsi),%xmm2 + 43b493: 0f 28 e2 movaps %xmm2,%xmm4 + 43b496: 0f 28 6e 10 movaps 0x10(%rsi),%xmm5 + 43b49a: 0f 28 5e 20 movaps 0x20(%rsi),%xmm3 + 43b49e: 0f 28 f3 movaps %xmm3,%xmm6 + 43b4a1: 0f 28 7e 30 movaps 0x30(%rsi),%xmm7 + 43b4a5: 66 0f da d5 pminub %xmm5,%xmm2 + 43b4a9: 66 0f da df pminub %xmm7,%xmm3 + 43b4ad: 66 0f da da pminub %xmm2,%xmm3 + 43b4b1: 66 0f 74 d8 pcmpeqb %xmm0,%xmm3 + 43b4b5: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43b4b9: 48 85 d2 test %rdx,%rdx + 43b4bc: 75 4b jne 43b509 <__stpcpy_sse2_unaligned+0x1a9> + 43b4be: 48 83 c7 40 add $0x40,%rdi + 43b4c2: 48 83 c6 40 add $0x40,%rsi + 43b4c6: f3 0f 7f 67 c0 movdqu %xmm4,-0x40(%rdi) + 43b4cb: 0f 28 16 movaps (%rsi),%xmm2 + 43b4ce: 66 0f 6f e2 movdqa %xmm2,%xmm4 + 43b4d2: f3 0f 7f 6f d0 movdqu %xmm5,-0x30(%rdi) + 43b4d7: 0f 28 6e 10 movaps 0x10(%rsi),%xmm5 + 43b4db: 66 0f da d5 pminub %xmm5,%xmm2 + 43b4df: 0f 28 5e 20 movaps 0x20(%rsi),%xmm3 + 43b4e3: f3 0f 7f 77 e0 movdqu %xmm6,-0x20(%rdi) + 43b4e8: 0f 28 f3 movaps %xmm3,%xmm6 + 43b4eb: f3 0f 7f 7f f0 movdqu %xmm7,-0x10(%rdi) + 43b4f0: 0f 28 7e 30 movaps 0x30(%rsi),%xmm7 + 43b4f4: 66 0f da df pminub %xmm7,%xmm3 + 43b4f8: 66 0f da da pminub %xmm2,%xmm3 + 43b4fc: 66 0f 74 d8 pcmpeqb %xmm0,%xmm3 + 43b500: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43b504: 48 85 d2 test %rdx,%rdx + 43b507: 74 b5 je 43b4be <__stpcpy_sse2_unaligned+0x15e> + 43b509: 66 0f ef c9 pxor %xmm1,%xmm1 + 43b50d: 66 0f 74 c4 pcmpeqb %xmm4,%xmm0 + 43b511: 66 0f 74 cd pcmpeqb %xmm5,%xmm1 + 43b515: 66 0f d7 d0 pmovmskb %xmm0,%edx + 43b519: 66 0f d7 c9 pmovmskb %xmm1,%ecx + 43b51d: 48 85 d2 test %rdx,%rdx + 43b520: 0f 85 0a 01 00 00 jne 43b630 <__stpcpy_sse2_unaligned+0x2d0> + 43b526: 48 85 c9 test %rcx,%rcx + 43b529: 0f 85 21 01 00 00 jne 43b650 <__stpcpy_sse2_unaligned+0x2f0> + 43b52f: 66 0f 74 c6 pcmpeqb %xmm6,%xmm0 + 43b533: 66 0f 74 cf pcmpeqb %xmm7,%xmm1 + 43b537: 66 0f d7 d0 pmovmskb %xmm0,%edx + 43b53b: 66 0f d7 c9 pmovmskb %xmm1,%ecx + 43b53f: 48 85 d2 test %rdx,%rdx + 43b542: 0f 85 38 01 00 00 jne 43b680 <__stpcpy_sse2_unaligned+0x320> + 43b548: 48 0f bc d1 bsf %rcx,%rdx + 43b54c: f3 0f 7f 27 movdqu %xmm4,(%rdi) + 43b550: f3 0f 7f 6f 10 movdqu %xmm5,0x10(%rdi) + 43b555: f3 0f 7f 77 20 movdqu %xmm6,0x20(%rdi) + 43b55a: 48 83 c6 30 add $0x30,%rsi + 43b55e: 48 83 c7 30 add $0x30,%rdi + 43b562: 4c 8d 1d c7 85 06 00 lea 0x685c7(%rip),%r11 # 4a3b30 + 43b569: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx + 43b56d: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx + 43b571: ff e1 jmpq *%rcx + 43b573: 66 0f ef c0 pxor %xmm0,%xmm0 + 43b577: f3 0f 6f 0e movdqu (%rsi),%xmm1 + 43b57b: f3 0f 6f 56 10 movdqu 0x10(%rsi),%xmm2 + 43b580: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 43b584: 66 0f d7 d0 pmovmskb %xmm0,%edx + 43b588: 48 85 d2 test %rdx,%rdx + 43b58b: 75 6b jne 43b5f8 <__stpcpy_sse2_unaligned+0x298> + 43b58d: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 + 43b591: f3 0f 7f 0f movdqu %xmm1,(%rdi) + 43b595: 66 0f d7 d0 pmovmskb %xmm0,%edx + 43b599: 48 85 d2 test %rdx,%rdx + 43b59c: 75 52 jne 43b5f0 <__stpcpy_sse2_unaligned+0x290> + 43b59e: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi + 43b5a2: 48 83 e1 0f and $0xf,%rcx + 43b5a6: e9 05 fe ff ff jmpq 43b3b0 <__stpcpy_sse2_unaligned+0x50> + 43b5ab: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43b5b0: 48 01 cf add %rcx,%rdi + 43b5b3: 48 01 ce add %rcx,%rsi + 43b5b6: 48 0f bc d2 bsf %rdx,%rdx + 43b5ba: 4c 8d 1d 6f 85 06 00 lea 0x6856f(%rip),%r11 # 4a3b30 + 43b5c1: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx + 43b5c5: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx + 43b5c9: ff e1 jmpq *%rcx + 43b5cb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43b5d0: 48 01 ce add %rcx,%rsi + 43b5d3: 48 0f bc d2 bsf %rdx,%rdx + 43b5d7: 4c 8d 1d 52 85 06 00 lea 0x68552(%rip),%r11 # 4a3b30 + 43b5de: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx + 43b5e2: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx + 43b5e6: ff e1 jmpq *%rcx + 43b5e8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 43b5ef: 00 + 43b5f0: 48 83 c6 10 add $0x10,%rsi + 43b5f4: 48 83 c7 10 add $0x10,%rdi + 43b5f8: 48 0f bc d2 bsf %rdx,%rdx + 43b5fc: 4c 8d 1d 2d 85 06 00 lea 0x6852d(%rip),%r11 # 4a3b30 + 43b603: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx + 43b607: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx + 43b60b: ff e1 jmpq *%rcx + 43b60d: 0f 1f 00 nopl (%rax) + 43b610: 48 0f bc d2 bsf %rdx,%rdx + 43b614: 48 01 ce add %rcx,%rsi + 43b617: 48 83 c2 10 add $0x10,%rdx + 43b61b: 48 29 ca sub %rcx,%rdx + 43b61e: 4c 8d 1d 0b 85 06 00 lea 0x6850b(%rip),%r11 # 4a3b30 + 43b625: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx + 43b629: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx + 43b62d: ff e1 jmpq *%rcx + 43b62f: 90 nop + 43b630: 48 0f bc d2 bsf %rdx,%rdx + 43b634: 4c 8d 1d f5 84 06 00 lea 0x684f5(%rip),%r11 # 4a3b30 + 43b63b: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx + 43b63f: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx + 43b643: ff e1 jmpq *%rcx + 43b645: 90 nop + 43b646: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b64d: 00 00 00 + 43b650: 48 0f bc d1 bsf %rcx,%rdx + 43b654: f3 0f 7f 27 movdqu %xmm4,(%rdi) + 43b658: 48 83 c6 10 add $0x10,%rsi + 43b65c: 48 83 c7 10 add $0x10,%rdi + 43b660: 4c 8d 1d c9 84 06 00 lea 0x684c9(%rip),%r11 # 4a3b30 + 43b667: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx + 43b66b: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx + 43b66f: ff e1 jmpq *%rcx + 43b671: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43b676: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b67d: 00 00 00 + 43b680: 48 0f bc d2 bsf %rdx,%rdx + 43b684: f3 0f 7f 27 movdqu %xmm4,(%rdi) + 43b688: f3 0f 7f 6f 10 movdqu %xmm5,0x10(%rdi) + 43b68d: 48 83 c6 20 add $0x20,%rsi + 43b691: 48 83 c7 20 add $0x20,%rdi + 43b695: 4c 8d 1d 94 84 06 00 lea 0x68494(%rip),%r11 # 4a3b30 + 43b69c: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx + 43b6a0: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx + 43b6a4: ff e1 jmpq *%rcx + 43b6a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b6ad: 00 00 00 + 43b6b0: 88 37 mov %dh,(%rdi) + 43b6b2: 48 8d 07 lea (%rdi),%rax + 43b6b5: c3 retq + 43b6b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b6bd: 00 00 00 + 43b6c0: 66 8b 16 mov (%rsi),%dx + 43b6c3: 66 89 17 mov %dx,(%rdi) + 43b6c6: 48 8d 47 01 lea 0x1(%rdi),%rax + 43b6ca: c3 retq + 43b6cb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43b6d0: 66 8b 0e mov (%rsi),%cx + 43b6d3: 66 89 0f mov %cx,(%rdi) + 43b6d6: 88 77 02 mov %dh,0x2(%rdi) + 43b6d9: 48 8d 47 02 lea 0x2(%rdi),%rax + 43b6dd: c3 retq + 43b6de: 66 90 xchg %ax,%ax + 43b6e0: 8b 16 mov (%rsi),%edx + 43b6e2: 89 17 mov %edx,(%rdi) + 43b6e4: 48 8d 47 03 lea 0x3(%rdi),%rax + 43b6e8: c3 retq + 43b6e9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43b6f0: 8b 0e mov (%rsi),%ecx + 43b6f2: 88 77 04 mov %dh,0x4(%rdi) + 43b6f5: 89 0f mov %ecx,(%rdi) + 43b6f7: 48 8d 47 04 lea 0x4(%rdi),%rax + 43b6fb: c3 retq + 43b6fc: 0f 1f 40 00 nopl 0x0(%rax) + 43b700: 8b 0e mov (%rsi),%ecx + 43b702: 66 8b 56 04 mov 0x4(%rsi),%dx + 43b706: 89 0f mov %ecx,(%rdi) + 43b708: 66 89 57 04 mov %dx,0x4(%rdi) + 43b70c: 48 8d 47 05 lea 0x5(%rdi),%rax + 43b710: c3 retq + 43b711: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43b716: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b71d: 00 00 00 + 43b720: 8b 0e mov (%rsi),%ecx + 43b722: 8b 56 03 mov 0x3(%rsi),%edx + 43b725: 89 0f mov %ecx,(%rdi) + 43b727: 89 57 03 mov %edx,0x3(%rdi) + 43b72a: 48 8d 47 06 lea 0x6(%rdi),%rax + 43b72e: c3 retq + 43b72f: 90 nop + 43b730: 48 8b 16 mov (%rsi),%rdx + 43b733: 48 89 17 mov %rdx,(%rdi) + 43b736: 48 8d 47 07 lea 0x7(%rdi),%rax + 43b73a: c3 retq + 43b73b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43b740: 48 8b 0e mov (%rsi),%rcx + 43b743: 88 77 08 mov %dh,0x8(%rdi) + 43b746: 48 89 0f mov %rcx,(%rdi) + 43b749: 48 8d 47 08 lea 0x8(%rdi),%rax + 43b74d: c3 retq + 43b74e: 66 90 xchg %ax,%ax + 43b750: 48 8b 0e mov (%rsi),%rcx + 43b753: 66 8b 56 08 mov 0x8(%rsi),%dx + 43b757: 48 89 0f mov %rcx,(%rdi) + 43b75a: 66 89 57 08 mov %dx,0x8(%rdi) + 43b75e: 48 8d 47 09 lea 0x9(%rdi),%rax + 43b762: c3 retq + 43b763: 0f 1f 00 nopl (%rax) + 43b766: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b76d: 00 00 00 + 43b770: 48 8b 0e mov (%rsi),%rcx + 43b773: 8b 56 07 mov 0x7(%rsi),%edx + 43b776: 48 89 0f mov %rcx,(%rdi) + 43b779: 89 57 07 mov %edx,0x7(%rdi) + 43b77c: 48 8d 47 0a lea 0xa(%rdi),%rax + 43b780: c3 retq + 43b781: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43b786: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b78d: 00 00 00 + 43b790: 48 8b 0e mov (%rsi),%rcx + 43b793: 8b 56 08 mov 0x8(%rsi),%edx + 43b796: 48 89 0f mov %rcx,(%rdi) + 43b799: 89 57 08 mov %edx,0x8(%rdi) + 43b79c: 48 8d 47 0b lea 0xb(%rdi),%rax + 43b7a0: c3 retq + 43b7a1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43b7a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b7ad: 00 00 00 + 43b7b0: 48 8b 0e mov (%rsi),%rcx + 43b7b3: 48 8b 56 05 mov 0x5(%rsi),%rdx + 43b7b7: 48 89 0f mov %rcx,(%rdi) + 43b7ba: 48 89 57 05 mov %rdx,0x5(%rdi) + 43b7be: 48 8d 47 0c lea 0xc(%rdi),%rax + 43b7c2: c3 retq + 43b7c3: 0f 1f 00 nopl (%rax) + 43b7c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b7cd: 00 00 00 + 43b7d0: 48 8b 0e mov (%rsi),%rcx + 43b7d3: 48 8b 56 06 mov 0x6(%rsi),%rdx + 43b7d7: 48 89 0f mov %rcx,(%rdi) + 43b7da: 48 89 57 06 mov %rdx,0x6(%rdi) + 43b7de: 48 8d 47 0d lea 0xd(%rdi),%rax + 43b7e2: c3 retq + 43b7e3: 0f 1f 00 nopl (%rax) + 43b7e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b7ed: 00 00 00 + 43b7f0: 48 8b 0e mov (%rsi),%rcx + 43b7f3: 48 8b 56 07 mov 0x7(%rsi),%rdx + 43b7f7: 48 89 0f mov %rcx,(%rdi) + 43b7fa: 48 89 57 07 mov %rdx,0x7(%rdi) + 43b7fe: 48 8d 47 0e lea 0xe(%rdi),%rax + 43b802: c3 retq + 43b803: 0f 1f 00 nopl (%rax) + 43b806: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b80d: 00 00 00 + 43b810: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b814: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b818: 48 8d 47 0f lea 0xf(%rdi),%rax + 43b81c: c3 retq + 43b81d: 0f 1f 00 nopl (%rax) + 43b820: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b824: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b828: 88 77 10 mov %dh,0x10(%rdi) + 43b82b: 48 8d 47 10 lea 0x10(%rdi),%rax + 43b82f: c3 retq + 43b830: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b834: 66 8b 4e 10 mov 0x10(%rsi),%cx + 43b838: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b83c: 66 89 4f 10 mov %cx,0x10(%rdi) + 43b840: 48 8d 47 11 lea 0x11(%rdi),%rax + 43b844: c3 retq + 43b845: 90 nop + 43b846: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b84d: 00 00 00 + 43b850: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b854: 8b 4e 0f mov 0xf(%rsi),%ecx + 43b857: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b85b: 89 4f 0f mov %ecx,0xf(%rdi) + 43b85e: 48 8d 47 12 lea 0x12(%rdi),%rax + 43b862: c3 retq + 43b863: 0f 1f 00 nopl (%rax) + 43b866: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b86d: 00 00 00 + 43b870: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b874: 8b 4e 10 mov 0x10(%rsi),%ecx + 43b877: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b87b: 89 4f 10 mov %ecx,0x10(%rdi) + 43b87e: 48 8d 47 13 lea 0x13(%rdi),%rax + 43b882: c3 retq + 43b883: 0f 1f 00 nopl (%rax) + 43b886: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b88d: 00 00 00 + 43b890: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b894: 8b 4e 10 mov 0x10(%rsi),%ecx + 43b897: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b89b: 89 4f 10 mov %ecx,0x10(%rdi) + 43b89e: 88 77 14 mov %dh,0x14(%rdi) + 43b8a1: 48 8d 47 14 lea 0x14(%rdi),%rax + 43b8a5: c3 retq + 43b8a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b8ad: 00 00 00 + 43b8b0: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b8b4: 48 8b 4e 0e mov 0xe(%rsi),%rcx + 43b8b8: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b8bc: 48 89 4f 0e mov %rcx,0xe(%rdi) + 43b8c0: 48 8d 47 15 lea 0x15(%rdi),%rax + 43b8c4: c3 retq + 43b8c5: 90 nop + 43b8c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b8cd: 00 00 00 + 43b8d0: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b8d4: 48 8b 4e 0f mov 0xf(%rsi),%rcx + 43b8d8: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b8dc: 48 89 4f 0f mov %rcx,0xf(%rdi) + 43b8e0: 48 8d 47 16 lea 0x16(%rdi),%rax + 43b8e4: c3 retq + 43b8e5: 90 nop + 43b8e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b8ed: 00 00 00 + 43b8f0: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b8f4: 48 8b 4e 10 mov 0x10(%rsi),%rcx + 43b8f8: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b8fc: 48 89 4f 10 mov %rcx,0x10(%rdi) + 43b900: 48 8d 47 17 lea 0x17(%rdi),%rax + 43b904: c3 retq + 43b905: 90 nop + 43b906: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43b90d: 00 00 00 + 43b910: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b914: 48 8b 4e 10 mov 0x10(%rsi),%rcx + 43b918: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b91c: 48 89 4f 10 mov %rcx,0x10(%rdi) + 43b920: 88 77 18 mov %dh,0x18(%rdi) + 43b923: 48 8d 47 18 lea 0x18(%rdi),%rax + 43b927: c3 retq + 43b928: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 43b92f: 00 + 43b930: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b934: 48 8b 56 10 mov 0x10(%rsi),%rdx + 43b938: 66 8b 4e 18 mov 0x18(%rsi),%cx + 43b93c: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b940: 48 89 57 10 mov %rdx,0x10(%rdi) + 43b944: 66 89 4f 18 mov %cx,0x18(%rdi) + 43b948: 48 8d 47 19 lea 0x19(%rdi),%rax + 43b94c: c3 retq + 43b94d: 0f 1f 00 nopl (%rax) + 43b950: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b954: 48 8b 56 10 mov 0x10(%rsi),%rdx + 43b958: 8b 4e 17 mov 0x17(%rsi),%ecx + 43b95b: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b95f: 48 89 57 10 mov %rdx,0x10(%rdi) + 43b963: 89 4f 17 mov %ecx,0x17(%rdi) + 43b966: 48 8d 47 1a lea 0x1a(%rdi),%rax + 43b96a: c3 retq + 43b96b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43b970: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b974: 48 8b 56 10 mov 0x10(%rsi),%rdx + 43b978: 8b 4e 18 mov 0x18(%rsi),%ecx + 43b97b: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b97f: 48 89 57 10 mov %rdx,0x10(%rdi) + 43b983: 89 4f 18 mov %ecx,0x18(%rdi) + 43b986: 48 8d 47 1b lea 0x1b(%rdi),%rax + 43b98a: c3 retq + 43b98b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43b990: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b994: f3 0f 6f 56 0d movdqu 0xd(%rsi),%xmm2 + 43b999: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b99d: f3 0f 7f 57 0d movdqu %xmm2,0xd(%rdi) + 43b9a2: 48 8d 47 1c lea 0x1c(%rdi),%rax + 43b9a6: c3 retq + 43b9a7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 43b9ae: 00 00 + 43b9b0: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b9b4: f3 0f 6f 56 0e movdqu 0xe(%rsi),%xmm2 + 43b9b9: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b9bd: f3 0f 7f 57 0e movdqu %xmm2,0xe(%rdi) + 43b9c2: 48 8d 47 1d lea 0x1d(%rdi),%rax + 43b9c6: c3 retq + 43b9c7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 43b9ce: 00 00 + 43b9d0: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b9d4: f3 0f 6f 56 0f movdqu 0xf(%rsi),%xmm2 + 43b9d9: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b9dd: f3 0f 7f 57 0f movdqu %xmm2,0xf(%rdi) + 43b9e2: 48 8d 47 1e lea 0x1e(%rdi),%rax + 43b9e6: c3 retq + 43b9e7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 43b9ee: 00 00 + 43b9f0: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43b9f4: f3 0f 6f 56 10 movdqu 0x10(%rsi),%xmm2 + 43b9f9: f3 0f 7f 07 movdqu %xmm0,(%rdi) + 43b9fd: f3 0f 7f 57 10 movdqu %xmm2,0x10(%rdi) + 43ba02: 48 8d 47 1f lea 0x1f(%rdi),%rax + 43ba06: c3 retq + 43ba07: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 43ba0e: 00 00 + +000000000043ba10 <__strchr_sse2_no_bsf>: + 43ba10: 66 0f 6e ce movd %esi,%xmm1 + 43ba14: 48 89 f9 mov %rdi,%rcx + 43ba17: 66 0f 60 c9 punpcklbw %xmm1,%xmm1 + 43ba1b: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi + 43ba1f: 66 0f ef d2 pxor %xmm2,%xmm2 + 43ba23: 66 0f 60 c9 punpcklbw %xmm1,%xmm1 + 43ba27: 83 ce ff or $0xffffffff,%esi + 43ba2a: 66 0f 6f 07 movdqa (%rdi),%xmm0 + 43ba2e: 66 0f 70 c9 00 pshufd $0x0,%xmm1,%xmm1 + 43ba33: 48 29 f9 sub %rdi,%rcx + 43ba36: 66 0f 6f d8 movdqa %xmm0,%xmm3 + 43ba3a: 48 8d 7f 10 lea 0x10(%rdi),%rdi + 43ba3e: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 43ba42: 66 0f 74 da pcmpeqb %xmm2,%xmm3 + 43ba46: d3 e6 shl %cl,%esi + 43ba48: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43ba4c: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43ba50: 21 f0 and %esi,%eax + 43ba52: 21 f2 and %esi,%edx + 43ba54: 85 c0 test %eax,%eax + 43ba56: 75 3c jne 43ba94 <__strchr_sse2_no_bsf+0x84> + 43ba58: 85 d2 test %edx,%edx + 43ba5a: 75 34 jne 43ba90 <__strchr_sse2_no_bsf+0x80> + 43ba5c: 66 0f 6f 07 movdqa (%rdi),%xmm0 + 43ba60: 48 8d 7f 10 lea 0x10(%rdi),%rdi + 43ba64: 66 0f 6f d8 movdqa %xmm0,%xmm3 + 43ba68: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 43ba6c: 66 0f 74 da pcmpeqb %xmm2,%xmm3 + 43ba70: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43ba74: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43ba78: 09 c2 or %eax,%edx + 43ba7a: 74 e0 je 43ba5c <__strchr_sse2_no_bsf+0x4c> + 43ba7c: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43ba80: 85 c0 test %eax,%eax + 43ba82: 75 10 jne 43ba94 <__strchr_sse2_no_bsf+0x84> + 43ba84: 66 90 xchg %ax,%ax + 43ba86: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43ba8d: 00 00 00 + 43ba90: 48 31 c0 xor %rax,%rax + 43ba93: c3 retq + 43ba94: 48 8d 7f f0 lea -0x10(%rdi),%rdi + 43ba98: 85 d2 test %edx,%edx + 43ba9a: 0f 84 10 01 00 00 je 43bbb0 <__strchr_sse2_no_bsf+0x1a0> + 43baa0: 84 c0 test %al,%al + 43baa2: 74 6c je 43bb10 <__strchr_sse2_no_bsf+0x100> + 43baa4: 88 c1 mov %al,%cl + 43baa6: 80 e1 0f and $0xf,%cl + 43baa9: 75 35 jne 43bae0 <__strchr_sse2_no_bsf+0xd0> + 43baab: 88 d5 mov %dl,%ch + 43baad: 80 e5 0f and $0xf,%ch + 43bab0: 75 de jne 43ba90 <__strchr_sse2_no_bsf+0x80> + 43bab2: a8 10 test $0x10,%al + 43bab4: 0f 85 d6 01 00 00 jne 43bc90 <__strchr_sse2_no_bsf+0x280> + 43baba: f6 c2 10 test $0x10,%dl + 43babd: 75 d1 jne 43ba90 <__strchr_sse2_no_bsf+0x80> + 43babf: a8 20 test $0x20,%al + 43bac1: 0f 85 d9 01 00 00 jne 43bca0 <__strchr_sse2_no_bsf+0x290> + 43bac7: f6 c2 20 test $0x20,%dl + 43baca: 75 c4 jne 43ba90 <__strchr_sse2_no_bsf+0x80> + 43bacc: a8 40 test $0x40,%al + 43bace: 0f 85 dc 01 00 00 jne 43bcb0 <__strchr_sse2_no_bsf+0x2a0> + 43bad4: f6 c2 40 test $0x40,%dl + 43bad7: 75 b7 jne 43ba90 <__strchr_sse2_no_bsf+0x80> + 43bad9: 48 8d 47 07 lea 0x7(%rdi),%rax + 43badd: c3 retq + 43bade: 66 90 xchg %ax,%ax + 43bae0: a8 01 test $0x1,%al + 43bae2: 0f 85 68 01 00 00 jne 43bc50 <__strchr_sse2_no_bsf+0x240> + 43bae8: f6 c2 01 test $0x1,%dl + 43baeb: 75 a3 jne 43ba90 <__strchr_sse2_no_bsf+0x80> + 43baed: a8 02 test $0x2,%al + 43baef: 0f 85 6b 01 00 00 jne 43bc60 <__strchr_sse2_no_bsf+0x250> + 43baf5: f6 c2 02 test $0x2,%dl + 43baf8: 75 96 jne 43ba90 <__strchr_sse2_no_bsf+0x80> + 43bafa: a8 04 test $0x4,%al + 43bafc: 0f 85 6e 01 00 00 jne 43bc70 <__strchr_sse2_no_bsf+0x260> + 43bb02: f6 c2 04 test $0x4,%dl + 43bb05: 75 89 jne 43ba90 <__strchr_sse2_no_bsf+0x80> + 43bb07: 48 8d 47 03 lea 0x3(%rdi),%rax + 43bb0b: c3 retq + 43bb0c: 0f 1f 40 00 nopl 0x0(%rax) + 43bb10: 84 d2 test %dl,%dl + 43bb12: 0f 85 78 ff ff ff jne 43ba90 <__strchr_sse2_no_bsf+0x80> + 43bb18: 88 e1 mov %ah,%cl + 43bb1a: 80 e1 0f and $0xf,%cl + 43bb1d: 75 51 jne 43bb70 <__strchr_sse2_no_bsf+0x160> + 43bb1f: 88 f5 mov %dh,%ch + 43bb21: 80 e5 0f and $0xf,%ch + 43bb24: 0f 85 66 ff ff ff jne 43ba90 <__strchr_sse2_no_bsf+0x80> + 43bb2a: f6 c4 10 test $0x10,%ah + 43bb2d: 0f 85 cd 01 00 00 jne 43bd00 <__strchr_sse2_no_bsf+0x2f0> + 43bb33: f6 c6 10 test $0x10,%dh + 43bb36: 0f 85 54 ff ff ff jne 43ba90 <__strchr_sse2_no_bsf+0x80> + 43bb3c: f6 c4 20 test $0x20,%ah + 43bb3f: 0f 85 cb 01 00 00 jne 43bd10 <__strchr_sse2_no_bsf+0x300> + 43bb45: f6 c6 20 test $0x20,%dh + 43bb48: 0f 85 42 ff ff ff jne 43ba90 <__strchr_sse2_no_bsf+0x80> + 43bb4e: f6 c4 40 test $0x40,%ah + 43bb51: 0f 85 c9 01 00 00 jne 43bd20 <__strchr_sse2_no_bsf+0x310> + 43bb57: f6 c6 40 test $0x40,%dh + 43bb5a: 0f 85 30 ff ff ff jne 43ba90 <__strchr_sse2_no_bsf+0x80> + 43bb60: 48 8d 47 0f lea 0xf(%rdi),%rax + 43bb64: c3 retq + 43bb65: 90 nop + 43bb66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43bb6d: 00 00 00 + 43bb70: f6 c4 01 test $0x1,%ah + 43bb73: 0f 85 47 01 00 00 jne 43bcc0 <__strchr_sse2_no_bsf+0x2b0> + 43bb79: f6 c6 01 test $0x1,%dh + 43bb7c: 0f 85 0e ff ff ff jne 43ba90 <__strchr_sse2_no_bsf+0x80> + 43bb82: f6 c4 02 test $0x2,%ah + 43bb85: 0f 85 45 01 00 00 jne 43bcd0 <__strchr_sse2_no_bsf+0x2c0> + 43bb8b: f6 c6 02 test $0x2,%dh + 43bb8e: 0f 85 fc fe ff ff jne 43ba90 <__strchr_sse2_no_bsf+0x80> + 43bb94: f6 c4 04 test $0x4,%ah + 43bb97: 0f 85 43 01 00 00 jne 43bce0 <__strchr_sse2_no_bsf+0x2d0> + 43bb9d: f6 c6 04 test $0x4,%dh + 43bba0: 0f 85 ea fe ff ff jne 43ba90 <__strchr_sse2_no_bsf+0x80> + 43bba6: 48 8d 47 0b lea 0xb(%rdi),%rax + 43bbaa: c3 retq + 43bbab: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43bbb0: 84 c0 test %al,%al + 43bbb2: 74 4c je 43bc00 <__strchr_sse2_no_bsf+0x1f0> + 43bbb4: a8 01 test $0x1,%al + 43bbb6: 0f 85 94 00 00 00 jne 43bc50 <__strchr_sse2_no_bsf+0x240> + 43bbbc: a8 02 test $0x2,%al + 43bbbe: 0f 85 9c 00 00 00 jne 43bc60 <__strchr_sse2_no_bsf+0x250> + 43bbc4: a8 04 test $0x4,%al + 43bbc6: 0f 85 a4 00 00 00 jne 43bc70 <__strchr_sse2_no_bsf+0x260> + 43bbcc: a8 08 test $0x8,%al + 43bbce: 0f 85 ac 00 00 00 jne 43bc80 <__strchr_sse2_no_bsf+0x270> + 43bbd4: a8 10 test $0x10,%al + 43bbd6: 0f 85 b4 00 00 00 jne 43bc90 <__strchr_sse2_no_bsf+0x280> + 43bbdc: a8 20 test $0x20,%al + 43bbde: 0f 85 bc 00 00 00 jne 43bca0 <__strchr_sse2_no_bsf+0x290> + 43bbe4: a8 40 test $0x40,%al + 43bbe6: 0f 85 c4 00 00 00 jne 43bcb0 <__strchr_sse2_no_bsf+0x2a0> + 43bbec: 48 8d 47 07 lea 0x7(%rdi),%rax + 43bbf0: c3 retq + 43bbf1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43bbf6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43bbfd: 00 00 00 + 43bc00: f6 c4 01 test $0x1,%ah + 43bc03: 0f 85 b7 00 00 00 jne 43bcc0 <__strchr_sse2_no_bsf+0x2b0> + 43bc09: f6 c4 02 test $0x2,%ah + 43bc0c: 0f 85 be 00 00 00 jne 43bcd0 <__strchr_sse2_no_bsf+0x2c0> + 43bc12: f6 c4 04 test $0x4,%ah + 43bc15: 0f 85 c5 00 00 00 jne 43bce0 <__strchr_sse2_no_bsf+0x2d0> + 43bc1b: f6 c4 08 test $0x8,%ah + 43bc1e: 0f 85 cc 00 00 00 jne 43bcf0 <__strchr_sse2_no_bsf+0x2e0> + 43bc24: f6 c4 10 test $0x10,%ah + 43bc27: 0f 85 d3 00 00 00 jne 43bd00 <__strchr_sse2_no_bsf+0x2f0> + 43bc2d: f6 c4 20 test $0x20,%ah + 43bc30: 0f 85 da 00 00 00 jne 43bd10 <__strchr_sse2_no_bsf+0x300> + 43bc36: f6 c4 40 test $0x40,%ah + 43bc39: 0f 85 e1 00 00 00 jne 43bd20 <__strchr_sse2_no_bsf+0x310> + 43bc3f: 48 8d 47 0f lea 0xf(%rdi),%rax + 43bc43: c3 retq + 43bc44: 66 90 xchg %ax,%ax + 43bc46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43bc4d: 00 00 00 + 43bc50: 48 8d 07 lea (%rdi),%rax + 43bc53: c3 retq + 43bc54: 66 90 xchg %ax,%ax + 43bc56: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43bc5d: 00 00 00 + 43bc60: 48 8d 47 01 lea 0x1(%rdi),%rax + 43bc64: c3 retq + 43bc65: 90 nop + 43bc66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43bc6d: 00 00 00 + 43bc70: 48 8d 47 02 lea 0x2(%rdi),%rax + 43bc74: c3 retq + 43bc75: 90 nop + 43bc76: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43bc7d: 00 00 00 + 43bc80: 48 8d 47 03 lea 0x3(%rdi),%rax + 43bc84: c3 retq + 43bc85: 90 nop + 43bc86: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43bc8d: 00 00 00 + 43bc90: 48 8d 47 04 lea 0x4(%rdi),%rax + 43bc94: c3 retq + 43bc95: 90 nop + 43bc96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43bc9d: 00 00 00 + 43bca0: 48 8d 47 05 lea 0x5(%rdi),%rax + 43bca4: c3 retq + 43bca5: 90 nop + 43bca6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43bcad: 00 00 00 + 43bcb0: 48 8d 47 06 lea 0x6(%rdi),%rax + 43bcb4: c3 retq + 43bcb5: 90 nop + 43bcb6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43bcbd: 00 00 00 + 43bcc0: 48 8d 47 08 lea 0x8(%rdi),%rax + 43bcc4: c3 retq + 43bcc5: 90 nop + 43bcc6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43bccd: 00 00 00 + 43bcd0: 48 8d 47 09 lea 0x9(%rdi),%rax + 43bcd4: c3 retq + 43bcd5: 90 nop + 43bcd6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43bcdd: 00 00 00 + 43bce0: 48 8d 47 0a lea 0xa(%rdi),%rax + 43bce4: c3 retq + 43bce5: 90 nop + 43bce6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43bced: 00 00 00 + 43bcf0: 48 8d 47 0b lea 0xb(%rdi),%rax + 43bcf4: c3 retq + 43bcf5: 90 nop + 43bcf6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43bcfd: 00 00 00 + 43bd00: 48 8d 47 0c lea 0xc(%rdi),%rax + 43bd04: c3 retq + 43bd05: 90 nop + 43bd06: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43bd0d: 00 00 00 + 43bd10: 48 8d 47 0d lea 0xd(%rdi),%rax + 43bd14: c3 retq + 43bd15: 90 nop + 43bd16: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43bd1d: 00 00 00 + 43bd20: 48 8d 47 0e lea 0xe(%rdi),%rax + 43bd24: c3 retq + 43bd25: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43bd2c: 00 00 00 + 43bd2f: 90 nop + +000000000043bd30 <__memcmp_ssse3>: + 43bd30: 48 89 d1 mov %rdx,%rcx + 43bd33: 48 89 fa mov %rdi,%rdx + 43bd36: 48 83 f9 30 cmp $0x30,%rcx + 43bd3a: 73 14 jae 43bd50 <__memcmp_ssse3+0x20> + 43bd3c: 48 01 ce add %rcx,%rsi + 43bd3f: 48 01 cf add %rcx,%rdi + 43bd42: e9 b9 12 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43bd47: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 43bd4e: 00 00 + 43bd50: f3 0f 6f 1f movdqu (%rdi),%xmm3 + 43bd54: f3 0f 6f 06 movdqu (%rsi),%xmm0 + 43bd58: 66 0f 74 d8 pcmpeqb %xmm0,%xmm3 + 43bd5c: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43bd60: 48 8d 7f 10 lea 0x10(%rdi),%rdi + 43bd64: 48 8d 76 10 lea 0x10(%rsi),%rsi + 43bd68: 81 ea ff ff 00 00 sub $0xffff,%edx + 43bd6e: 0f 85 98 11 00 00 jne 43cf0c <__memcmp_ssse3+0x11dc> + 43bd74: 89 fa mov %edi,%edx + 43bd76: 83 e2 0f and $0xf,%edx + 43bd79: 48 31 d7 xor %rdx,%rdi + 43bd7c: 48 29 d6 sub %rdx,%rsi + 43bd7f: 48 01 d1 add %rdx,%rcx + 43bd82: 89 f2 mov %esi,%edx + 43bd84: 83 e2 0f and $0xf,%edx + 43bd87: 0f 84 93 00 00 00 je 43be20 <__memcmp_ssse3+0xf0> + 43bd8d: 48 31 d6 xor %rdx,%rsi + 43bd90: 83 fa 08 cmp $0x8,%edx + 43bd93: 73 47 jae 43bddc <__memcmp_ssse3+0xac> + 43bd95: 83 fa 00 cmp $0x0,%edx + 43bd98: 0f 84 82 00 00 00 je 43be20 <__memcmp_ssse3+0xf0> + 43bd9e: 83 fa 01 cmp $0x1,%edx + 43bda1: 0f 84 59 01 00 00 je 43bf00 <__memcmp_ssse3+0x1d0> + 43bda7: 83 fa 02 cmp $0x2,%edx + 43bdaa: 0f 84 60 02 00 00 je 43c010 <__memcmp_ssse3+0x2e0> + 43bdb0: 83 fa 03 cmp $0x3,%edx + 43bdb3: 0f 84 67 03 00 00 je 43c120 <__memcmp_ssse3+0x3f0> + 43bdb9: 83 fa 04 cmp $0x4,%edx + 43bdbc: 0f 84 6e 04 00 00 je 43c230 <__memcmp_ssse3+0x500> + 43bdc2: 83 fa 05 cmp $0x5,%edx + 43bdc5: 0f 84 75 05 00 00 je 43c340 <__memcmp_ssse3+0x610> + 43bdcb: 83 fa 06 cmp $0x6,%edx + 43bdce: 0f 84 7c 06 00 00 je 43c450 <__memcmp_ssse3+0x720> + 43bdd4: e9 87 07 00 00 jmpq 43c560 <__memcmp_ssse3+0x830> + 43bdd9: 0f 1f 00 nopl (%rax) + 43bddc: 83 fa 08 cmp $0x8,%edx + 43bddf: 0f 84 8b 08 00 00 je 43c670 <__memcmp_ssse3+0x940> + 43bde5: 83 fa 09 cmp $0x9,%edx + 43bde8: 0f 84 92 09 00 00 je 43c780 <__memcmp_ssse3+0xa50> + 43bdee: 83 fa 0a cmp $0xa,%edx + 43bdf1: 0f 84 99 0a 00 00 je 43c890 <__memcmp_ssse3+0xb60> + 43bdf7: 83 fa 0b cmp $0xb,%edx + 43bdfa: 0f 84 a0 0b 00 00 je 43c9a0 <__memcmp_ssse3+0xc70> + 43be00: 83 fa 0c cmp $0xc,%edx + 43be03: 0f 84 a7 0c 00 00 je 43cab0 <__memcmp_ssse3+0xd80> + 43be09: 83 fa 0d cmp $0xd,%edx + 43be0c: 0f 84 ae 0d 00 00 je 43cbc0 <__memcmp_ssse3+0xe90> + 43be12: 83 fa 0e cmp $0xe,%edx + 43be15: 0f 84 b5 0e 00 00 je 43ccd0 <__memcmp_ssse3+0xfa0> + 43be1b: e9 c0 0f 00 00 jmpq 43cde0 <__memcmp_ssse3+0x10b0> + 43be20: 48 83 f9 50 cmp $0x50,%rcx + 43be24: 48 8d 49 d0 lea -0x30(%rcx),%rcx + 43be28: 73 46 jae 43be70 <__memcmp_ssse3+0x140> + 43be2a: 31 c0 xor %eax,%eax + 43be2c: 66 0f 6f 0e movdqa (%rsi),%xmm1 + 43be30: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 + 43be34: 66 0f 6f 56 10 movdqa 0x10(%rsi),%xmm2 + 43be39: 66 0f 74 57 10 pcmpeqb 0x10(%rdi),%xmm2 + 43be3e: 66 0f db d1 pand %xmm1,%xmm2 + 43be42: 66 0f d7 d2 pmovmskb %xmm2,%edx + 43be46: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43be4a: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43be4e: 81 ea ff ff 00 00 sub $0xffff,%edx + 43be54: 0f 85 96 10 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43be5a: 48 01 ce add %rcx,%rsi + 43be5d: 48 01 cf add %rcx,%rdi + 43be60: e9 9b 11 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43be65: 90 nop + 43be66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43be6d: 00 00 00 + 43be70: 66 0f 6f 06 movdqa (%rsi),%xmm0 + 43be74: 31 c0 xor %eax,%eax + 43be76: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 43be7a: 48 83 e9 20 sub $0x20,%rcx + 43be7e: 66 0f 6f 56 10 movdqa 0x10(%rsi),%xmm2 + 43be83: 66 0f 74 57 10 pcmpeqb 0x10(%rdi),%xmm2 + 43be88: 66 0f db d0 pand %xmm0,%xmm2 + 43be8c: 48 83 e9 20 sub $0x20,%rcx + 43be90: 66 0f d7 d2 pmovmskb %xmm2,%edx + 43be94: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43be98: 66 0f 6f 46 20 movdqa 0x20(%rsi),%xmm0 + 43be9d: 66 0f 6f 56 30 movdqa 0x30(%rsi),%xmm2 + 43bea2: 81 da ff ff 00 00 sbb $0xffff,%edx + 43bea8: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 + 43bead: 66 0f 74 57 30 pcmpeqb 0x30(%rdi),%xmm2 + 43beb2: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43beb6: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43beba: 74 cc je 43be88 <__memcmp_ssse3+0x158> + 43bebc: 66 0f db d0 pand %xmm0,%xmm2 + 43bec0: 48 83 f9 00 cmp $0x0,%rcx + 43bec4: 7d 06 jge 43becc <__memcmp_ssse3+0x19c> + 43bec6: ff c2 inc %edx + 43bec8: 48 83 c1 20 add $0x20,%rcx + 43becc: 85 d2 test %edx,%edx + 43bece: 0f 85 1c 10 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43bed4: 66 0f d7 d2 pmovmskb %xmm2,%edx + 43bed8: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43bedc: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43bee0: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43bee4: 81 ea ff ff 00 00 sub $0xffff,%edx + 43beea: 0f 85 00 10 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43bef0: 48 01 ce add %rcx,%rsi + 43bef3: 48 01 cf add %rcx,%rdi + 43bef6: e9 05 11 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43befb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43bf00: 48 83 f9 50 cmp $0x50,%rcx + 43bf04: 48 8d 49 d0 lea -0x30(%rcx),%rcx + 43bf08: 89 d0 mov %edx,%eax + 43bf0a: 73 54 jae 43bf60 <__memcmp_ssse3+0x230> + 43bf0c: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 + 43bf11: 66 0f 6f d1 movdqa %xmm1,%xmm2 + 43bf15: 66 0f 3a 0f 0e 01 palignr $0x1,(%rsi),%xmm1 + 43bf1b: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 + 43bf1f: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 + 43bf24: 66 0f 3a 0f da 01 palignr $0x1,%xmm2,%xmm3 + 43bf2a: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 + 43bf2f: 66 0f db d9 pand %xmm1,%xmm3 + 43bf33: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43bf37: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43bf3b: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43bf3f: 81 ea ff ff 00 00 sub $0xffff,%edx + 43bf45: 0f 85 a5 0f 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43bf4b: 48 83 c6 01 add $0x1,%rsi + 43bf4f: 48 01 ce add %rcx,%rsi + 43bf52: 48 01 cf add %rcx,%rdi + 43bf55: e9 a6 10 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43bf5a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43bf60: 48 83 e9 20 sub $0x20,%rcx + 43bf64: 66 0f 6f 46 10 movdqa 0x10(%rsi),%xmm0 + 43bf69: 66 0f 3a 0f 06 01 palignr $0x1,(%rsi),%xmm0 + 43bf6f: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 43bf73: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 + 43bf78: 66 0f 3a 0f 5e 10 01 palignr $0x1,0x10(%rsi),%xmm3 + 43bf7f: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 + 43bf84: 66 0f db d8 pand %xmm0,%xmm3 + 43bf88: 48 83 e9 20 sub $0x20,%rcx + 43bf8c: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43bf90: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43bf94: 66 0f 6f 5e 40 movdqa 0x40(%rsi),%xmm3 + 43bf99: 66 0f 3a 0f 5e 30 01 palignr $0x1,0x30(%rsi),%xmm3 + 43bfa0: 81 da ff ff 00 00 sbb $0xffff,%edx + 43bfa6: 66 0f 6f 46 30 movdqa 0x30(%rsi),%xmm0 + 43bfab: 66 0f 3a 0f 46 20 01 palignr $0x1,0x20(%rsi),%xmm0 + 43bfb2: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 + 43bfb7: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43bfbb: 66 0f 74 5f 30 pcmpeqb 0x30(%rdi),%xmm3 + 43bfc0: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43bfc4: 74 be je 43bf84 <__memcmp_ssse3+0x254> + 43bfc6: 66 0f db d8 pand %xmm0,%xmm3 + 43bfca: 48 83 f9 00 cmp $0x0,%rcx + 43bfce: 7d 06 jge 43bfd6 <__memcmp_ssse3+0x2a6> + 43bfd0: ff c2 inc %edx + 43bfd2: 48 83 c1 20 add $0x20,%rcx + 43bfd6: 85 d2 test %edx,%edx + 43bfd8: 0f 85 12 0f 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43bfde: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43bfe2: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43bfe6: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43bfea: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43bfee: 81 ea ff ff 00 00 sub $0xffff,%edx + 43bff4: 0f 85 f6 0e 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43bffa: 48 8d 76 01 lea 0x1(%rsi),%rsi + 43bffe: 48 01 ce add %rcx,%rsi + 43c001: 48 01 cf add %rcx,%rdi + 43c004: e9 f7 0f 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43c009: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43c010: 48 83 f9 50 cmp $0x50,%rcx + 43c014: 48 8d 49 d0 lea -0x30(%rcx),%rcx + 43c018: 89 d0 mov %edx,%eax + 43c01a: 73 54 jae 43c070 <__memcmp_ssse3+0x340> + 43c01c: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 + 43c021: 66 0f 6f d1 movdqa %xmm1,%xmm2 + 43c025: 66 0f 3a 0f 0e 02 palignr $0x2,(%rsi),%xmm1 + 43c02b: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 + 43c02f: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 + 43c034: 66 0f 3a 0f da 02 palignr $0x2,%xmm2,%xmm3 + 43c03a: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 + 43c03f: 66 0f db d9 pand %xmm1,%xmm3 + 43c043: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43c047: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43c04b: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43c04f: 81 ea ff ff 00 00 sub $0xffff,%edx + 43c055: 0f 85 95 0e 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43c05b: 48 83 c6 02 add $0x2,%rsi + 43c05f: 48 01 ce add %rcx,%rsi + 43c062: 48 01 cf add %rcx,%rdi + 43c065: e9 96 0f 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43c06a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43c070: 48 83 e9 20 sub $0x20,%rcx + 43c074: 66 0f 6f 46 10 movdqa 0x10(%rsi),%xmm0 + 43c079: 66 0f 3a 0f 06 02 palignr $0x2,(%rsi),%xmm0 + 43c07f: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 43c083: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 + 43c088: 66 0f 3a 0f 5e 10 02 palignr $0x2,0x10(%rsi),%xmm3 + 43c08f: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 + 43c094: 66 0f db d8 pand %xmm0,%xmm3 + 43c098: 48 83 e9 20 sub $0x20,%rcx + 43c09c: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43c0a0: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43c0a4: 66 0f 6f 5e 40 movdqa 0x40(%rsi),%xmm3 + 43c0a9: 66 0f 3a 0f 5e 30 02 palignr $0x2,0x30(%rsi),%xmm3 + 43c0b0: 81 da ff ff 00 00 sbb $0xffff,%edx + 43c0b6: 66 0f 6f 46 30 movdqa 0x30(%rsi),%xmm0 + 43c0bb: 66 0f 3a 0f 46 20 02 palignr $0x2,0x20(%rsi),%xmm0 + 43c0c2: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 + 43c0c7: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43c0cb: 66 0f 74 5f 30 pcmpeqb 0x30(%rdi),%xmm3 + 43c0d0: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43c0d4: 74 be je 43c094 <__memcmp_ssse3+0x364> + 43c0d6: 66 0f db d8 pand %xmm0,%xmm3 + 43c0da: 48 83 f9 00 cmp $0x0,%rcx + 43c0de: 7d 06 jge 43c0e6 <__memcmp_ssse3+0x3b6> + 43c0e0: ff c2 inc %edx + 43c0e2: 48 83 c1 20 add $0x20,%rcx + 43c0e6: 85 d2 test %edx,%edx + 43c0e8: 0f 85 02 0e 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43c0ee: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43c0f2: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43c0f6: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43c0fa: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43c0fe: 81 ea ff ff 00 00 sub $0xffff,%edx + 43c104: 0f 85 e6 0d 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43c10a: 48 8d 76 02 lea 0x2(%rsi),%rsi + 43c10e: 48 01 ce add %rcx,%rsi + 43c111: 48 01 cf add %rcx,%rdi + 43c114: e9 e7 0e 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43c119: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43c120: 48 83 f9 50 cmp $0x50,%rcx + 43c124: 48 8d 49 d0 lea -0x30(%rcx),%rcx + 43c128: 89 d0 mov %edx,%eax + 43c12a: 73 54 jae 43c180 <__memcmp_ssse3+0x450> + 43c12c: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 + 43c131: 66 0f 6f d1 movdqa %xmm1,%xmm2 + 43c135: 66 0f 3a 0f 0e 03 palignr $0x3,(%rsi),%xmm1 + 43c13b: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 + 43c13f: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 + 43c144: 66 0f 3a 0f da 03 palignr $0x3,%xmm2,%xmm3 + 43c14a: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 + 43c14f: 66 0f db d9 pand %xmm1,%xmm3 + 43c153: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43c157: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43c15b: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43c15f: 81 ea ff ff 00 00 sub $0xffff,%edx + 43c165: 0f 85 85 0d 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43c16b: 48 83 c6 03 add $0x3,%rsi + 43c16f: 48 01 ce add %rcx,%rsi + 43c172: 48 01 cf add %rcx,%rdi + 43c175: e9 86 0e 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43c17a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43c180: 48 83 e9 20 sub $0x20,%rcx + 43c184: 66 0f 6f 46 10 movdqa 0x10(%rsi),%xmm0 + 43c189: 66 0f 3a 0f 06 03 palignr $0x3,(%rsi),%xmm0 + 43c18f: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 43c193: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 + 43c198: 66 0f 3a 0f 5e 10 03 palignr $0x3,0x10(%rsi),%xmm3 + 43c19f: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 + 43c1a4: 66 0f db d8 pand %xmm0,%xmm3 + 43c1a8: 48 83 e9 20 sub $0x20,%rcx + 43c1ac: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43c1b0: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43c1b4: 66 0f 6f 5e 40 movdqa 0x40(%rsi),%xmm3 + 43c1b9: 66 0f 3a 0f 5e 30 03 palignr $0x3,0x30(%rsi),%xmm3 + 43c1c0: 81 da ff ff 00 00 sbb $0xffff,%edx + 43c1c6: 66 0f 6f 46 30 movdqa 0x30(%rsi),%xmm0 + 43c1cb: 66 0f 3a 0f 46 20 03 palignr $0x3,0x20(%rsi),%xmm0 + 43c1d2: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 + 43c1d7: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43c1db: 66 0f 74 5f 30 pcmpeqb 0x30(%rdi),%xmm3 + 43c1e0: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43c1e4: 74 be je 43c1a4 <__memcmp_ssse3+0x474> + 43c1e6: 66 0f db d8 pand %xmm0,%xmm3 + 43c1ea: 48 83 f9 00 cmp $0x0,%rcx + 43c1ee: 7d 06 jge 43c1f6 <__memcmp_ssse3+0x4c6> + 43c1f0: ff c2 inc %edx + 43c1f2: 48 83 c1 20 add $0x20,%rcx + 43c1f6: 85 d2 test %edx,%edx + 43c1f8: 0f 85 f2 0c 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43c1fe: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43c202: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43c206: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43c20a: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43c20e: 81 ea ff ff 00 00 sub $0xffff,%edx + 43c214: 0f 85 d6 0c 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43c21a: 48 8d 76 03 lea 0x3(%rsi),%rsi + 43c21e: 48 01 ce add %rcx,%rsi + 43c221: 48 01 cf add %rcx,%rdi + 43c224: e9 d7 0d 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43c229: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43c230: 48 83 f9 50 cmp $0x50,%rcx + 43c234: 48 8d 49 d0 lea -0x30(%rcx),%rcx + 43c238: 89 d0 mov %edx,%eax + 43c23a: 73 54 jae 43c290 <__memcmp_ssse3+0x560> + 43c23c: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 + 43c241: 66 0f 6f d1 movdqa %xmm1,%xmm2 + 43c245: 66 0f 3a 0f 0e 04 palignr $0x4,(%rsi),%xmm1 + 43c24b: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 + 43c24f: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 + 43c254: 66 0f 3a 0f da 04 palignr $0x4,%xmm2,%xmm3 + 43c25a: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 + 43c25f: 66 0f db d9 pand %xmm1,%xmm3 + 43c263: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43c267: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43c26b: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43c26f: 81 ea ff ff 00 00 sub $0xffff,%edx + 43c275: 0f 85 75 0c 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43c27b: 48 83 c6 04 add $0x4,%rsi + 43c27f: 48 01 ce add %rcx,%rsi + 43c282: 48 01 cf add %rcx,%rdi + 43c285: e9 76 0d 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43c28a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43c290: 48 83 e9 20 sub $0x20,%rcx + 43c294: 66 0f 6f 46 10 movdqa 0x10(%rsi),%xmm0 + 43c299: 66 0f 3a 0f 06 04 palignr $0x4,(%rsi),%xmm0 + 43c29f: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 43c2a3: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 + 43c2a8: 66 0f 3a 0f 5e 10 04 palignr $0x4,0x10(%rsi),%xmm3 + 43c2af: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 + 43c2b4: 66 0f db d8 pand %xmm0,%xmm3 + 43c2b8: 48 83 e9 20 sub $0x20,%rcx + 43c2bc: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43c2c0: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43c2c4: 66 0f 6f 5e 40 movdqa 0x40(%rsi),%xmm3 + 43c2c9: 66 0f 3a 0f 5e 30 04 palignr $0x4,0x30(%rsi),%xmm3 + 43c2d0: 81 da ff ff 00 00 sbb $0xffff,%edx + 43c2d6: 66 0f 6f 46 30 movdqa 0x30(%rsi),%xmm0 + 43c2db: 66 0f 3a 0f 46 20 04 palignr $0x4,0x20(%rsi),%xmm0 + 43c2e2: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 + 43c2e7: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43c2eb: 66 0f 74 5f 30 pcmpeqb 0x30(%rdi),%xmm3 + 43c2f0: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43c2f4: 74 be je 43c2b4 <__memcmp_ssse3+0x584> + 43c2f6: 66 0f db d8 pand %xmm0,%xmm3 + 43c2fa: 48 83 f9 00 cmp $0x0,%rcx + 43c2fe: 7d 06 jge 43c306 <__memcmp_ssse3+0x5d6> + 43c300: ff c2 inc %edx + 43c302: 48 83 c1 20 add $0x20,%rcx + 43c306: 85 d2 test %edx,%edx + 43c308: 0f 85 e2 0b 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43c30e: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43c312: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43c316: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43c31a: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43c31e: 81 ea ff ff 00 00 sub $0xffff,%edx + 43c324: 0f 85 c6 0b 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43c32a: 48 8d 76 04 lea 0x4(%rsi),%rsi + 43c32e: 48 01 ce add %rcx,%rsi + 43c331: 48 01 cf add %rcx,%rdi + 43c334: e9 c7 0c 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43c339: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43c340: 48 83 f9 50 cmp $0x50,%rcx + 43c344: 48 8d 49 d0 lea -0x30(%rcx),%rcx + 43c348: 89 d0 mov %edx,%eax + 43c34a: 73 54 jae 43c3a0 <__memcmp_ssse3+0x670> + 43c34c: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 + 43c351: 66 0f 6f d1 movdqa %xmm1,%xmm2 + 43c355: 66 0f 3a 0f 0e 05 palignr $0x5,(%rsi),%xmm1 + 43c35b: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 + 43c35f: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 + 43c364: 66 0f 3a 0f da 05 palignr $0x5,%xmm2,%xmm3 + 43c36a: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 + 43c36f: 66 0f db d9 pand %xmm1,%xmm3 + 43c373: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43c377: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43c37b: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43c37f: 81 ea ff ff 00 00 sub $0xffff,%edx + 43c385: 0f 85 65 0b 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43c38b: 48 83 c6 05 add $0x5,%rsi + 43c38f: 48 01 ce add %rcx,%rsi + 43c392: 48 01 cf add %rcx,%rdi + 43c395: e9 66 0c 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43c39a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43c3a0: 48 83 e9 20 sub $0x20,%rcx + 43c3a4: 66 0f 6f 46 10 movdqa 0x10(%rsi),%xmm0 + 43c3a9: 66 0f 3a 0f 06 05 palignr $0x5,(%rsi),%xmm0 + 43c3af: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 43c3b3: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 + 43c3b8: 66 0f 3a 0f 5e 10 05 palignr $0x5,0x10(%rsi),%xmm3 + 43c3bf: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 + 43c3c4: 66 0f db d8 pand %xmm0,%xmm3 + 43c3c8: 48 83 e9 20 sub $0x20,%rcx + 43c3cc: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43c3d0: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43c3d4: 66 0f 6f 5e 40 movdqa 0x40(%rsi),%xmm3 + 43c3d9: 66 0f 3a 0f 5e 30 05 palignr $0x5,0x30(%rsi),%xmm3 + 43c3e0: 81 da ff ff 00 00 sbb $0xffff,%edx + 43c3e6: 66 0f 6f 46 30 movdqa 0x30(%rsi),%xmm0 + 43c3eb: 66 0f 3a 0f 46 20 05 palignr $0x5,0x20(%rsi),%xmm0 + 43c3f2: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 + 43c3f7: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43c3fb: 66 0f 74 5f 30 pcmpeqb 0x30(%rdi),%xmm3 + 43c400: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43c404: 74 be je 43c3c4 <__memcmp_ssse3+0x694> + 43c406: 66 0f db d8 pand %xmm0,%xmm3 + 43c40a: 48 83 f9 00 cmp $0x0,%rcx + 43c40e: 7d 06 jge 43c416 <__memcmp_ssse3+0x6e6> + 43c410: ff c2 inc %edx + 43c412: 48 83 c1 20 add $0x20,%rcx + 43c416: 85 d2 test %edx,%edx + 43c418: 0f 85 d2 0a 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43c41e: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43c422: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43c426: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43c42a: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43c42e: 81 ea ff ff 00 00 sub $0xffff,%edx + 43c434: 0f 85 b6 0a 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43c43a: 48 8d 76 05 lea 0x5(%rsi),%rsi + 43c43e: 48 01 ce add %rcx,%rsi + 43c441: 48 01 cf add %rcx,%rdi + 43c444: e9 b7 0b 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43c449: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43c450: 48 83 f9 50 cmp $0x50,%rcx + 43c454: 48 8d 49 d0 lea -0x30(%rcx),%rcx + 43c458: 89 d0 mov %edx,%eax + 43c45a: 73 54 jae 43c4b0 <__memcmp_ssse3+0x780> + 43c45c: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 + 43c461: 66 0f 6f d1 movdqa %xmm1,%xmm2 + 43c465: 66 0f 3a 0f 0e 06 palignr $0x6,(%rsi),%xmm1 + 43c46b: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 + 43c46f: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 + 43c474: 66 0f 3a 0f da 06 palignr $0x6,%xmm2,%xmm3 + 43c47a: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 + 43c47f: 66 0f db d9 pand %xmm1,%xmm3 + 43c483: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43c487: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43c48b: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43c48f: 81 ea ff ff 00 00 sub $0xffff,%edx + 43c495: 0f 85 55 0a 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43c49b: 48 83 c6 06 add $0x6,%rsi + 43c49f: 48 01 ce add %rcx,%rsi + 43c4a2: 48 01 cf add %rcx,%rdi + 43c4a5: e9 56 0b 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43c4aa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43c4b0: 48 83 e9 20 sub $0x20,%rcx + 43c4b4: 66 0f 6f 46 10 movdqa 0x10(%rsi),%xmm0 + 43c4b9: 66 0f 3a 0f 06 06 palignr $0x6,(%rsi),%xmm0 + 43c4bf: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 43c4c3: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 + 43c4c8: 66 0f 3a 0f 5e 10 06 palignr $0x6,0x10(%rsi),%xmm3 + 43c4cf: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 + 43c4d4: 66 0f db d8 pand %xmm0,%xmm3 + 43c4d8: 48 83 e9 20 sub $0x20,%rcx + 43c4dc: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43c4e0: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43c4e4: 66 0f 6f 5e 40 movdqa 0x40(%rsi),%xmm3 + 43c4e9: 66 0f 3a 0f 5e 30 06 palignr $0x6,0x30(%rsi),%xmm3 + 43c4f0: 81 da ff ff 00 00 sbb $0xffff,%edx + 43c4f6: 66 0f 6f 46 30 movdqa 0x30(%rsi),%xmm0 + 43c4fb: 66 0f 3a 0f 46 20 06 palignr $0x6,0x20(%rsi),%xmm0 + 43c502: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 + 43c507: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43c50b: 66 0f 74 5f 30 pcmpeqb 0x30(%rdi),%xmm3 + 43c510: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43c514: 74 be je 43c4d4 <__memcmp_ssse3+0x7a4> + 43c516: 66 0f db d8 pand %xmm0,%xmm3 + 43c51a: 48 83 f9 00 cmp $0x0,%rcx + 43c51e: 7d 06 jge 43c526 <__memcmp_ssse3+0x7f6> + 43c520: ff c2 inc %edx + 43c522: 48 83 c1 20 add $0x20,%rcx + 43c526: 85 d2 test %edx,%edx + 43c528: 0f 85 c2 09 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43c52e: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43c532: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43c536: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43c53a: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43c53e: 81 ea ff ff 00 00 sub $0xffff,%edx + 43c544: 0f 85 a6 09 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43c54a: 48 8d 76 06 lea 0x6(%rsi),%rsi + 43c54e: 48 01 ce add %rcx,%rsi + 43c551: 48 01 cf add %rcx,%rdi + 43c554: e9 a7 0a 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43c559: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43c560: 48 83 f9 50 cmp $0x50,%rcx + 43c564: 48 8d 49 d0 lea -0x30(%rcx),%rcx + 43c568: 89 d0 mov %edx,%eax + 43c56a: 73 54 jae 43c5c0 <__memcmp_ssse3+0x890> + 43c56c: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 + 43c571: 66 0f 6f d1 movdqa %xmm1,%xmm2 + 43c575: 66 0f 3a 0f 0e 07 palignr $0x7,(%rsi),%xmm1 + 43c57b: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 + 43c57f: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 + 43c584: 66 0f 3a 0f da 07 palignr $0x7,%xmm2,%xmm3 + 43c58a: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 + 43c58f: 66 0f db d9 pand %xmm1,%xmm3 + 43c593: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43c597: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43c59b: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43c59f: 81 ea ff ff 00 00 sub $0xffff,%edx + 43c5a5: 0f 85 45 09 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43c5ab: 48 83 c6 07 add $0x7,%rsi + 43c5af: 48 01 ce add %rcx,%rsi + 43c5b2: 48 01 cf add %rcx,%rdi + 43c5b5: e9 46 0a 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43c5ba: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43c5c0: 48 83 e9 20 sub $0x20,%rcx + 43c5c4: 66 0f 6f 46 10 movdqa 0x10(%rsi),%xmm0 + 43c5c9: 66 0f 3a 0f 06 07 palignr $0x7,(%rsi),%xmm0 + 43c5cf: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 43c5d3: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 + 43c5d8: 66 0f 3a 0f 5e 10 07 palignr $0x7,0x10(%rsi),%xmm3 + 43c5df: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 + 43c5e4: 66 0f db d8 pand %xmm0,%xmm3 + 43c5e8: 48 83 e9 20 sub $0x20,%rcx + 43c5ec: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43c5f0: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43c5f4: 66 0f 6f 5e 40 movdqa 0x40(%rsi),%xmm3 + 43c5f9: 66 0f 3a 0f 5e 30 07 palignr $0x7,0x30(%rsi),%xmm3 + 43c600: 81 da ff ff 00 00 sbb $0xffff,%edx + 43c606: 66 0f 6f 46 30 movdqa 0x30(%rsi),%xmm0 + 43c60b: 66 0f 3a 0f 46 20 07 palignr $0x7,0x20(%rsi),%xmm0 + 43c612: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 + 43c617: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43c61b: 66 0f 74 5f 30 pcmpeqb 0x30(%rdi),%xmm3 + 43c620: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43c624: 74 be je 43c5e4 <__memcmp_ssse3+0x8b4> + 43c626: 66 0f db d8 pand %xmm0,%xmm3 + 43c62a: 48 83 f9 00 cmp $0x0,%rcx + 43c62e: 7d 06 jge 43c636 <__memcmp_ssse3+0x906> + 43c630: ff c2 inc %edx + 43c632: 48 83 c1 20 add $0x20,%rcx + 43c636: 85 d2 test %edx,%edx + 43c638: 0f 85 b2 08 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43c63e: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43c642: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43c646: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43c64a: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43c64e: 81 ea ff ff 00 00 sub $0xffff,%edx + 43c654: 0f 85 96 08 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43c65a: 48 8d 76 07 lea 0x7(%rsi),%rsi + 43c65e: 48 01 ce add %rcx,%rsi + 43c661: 48 01 cf add %rcx,%rdi + 43c664: e9 97 09 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43c669: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43c670: 48 83 f9 50 cmp $0x50,%rcx + 43c674: 48 8d 49 d0 lea -0x30(%rcx),%rcx + 43c678: 89 d0 mov %edx,%eax + 43c67a: 73 54 jae 43c6d0 <__memcmp_ssse3+0x9a0> + 43c67c: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 + 43c681: 66 0f 6f d1 movdqa %xmm1,%xmm2 + 43c685: 66 0f 3a 0f 0e 08 palignr $0x8,(%rsi),%xmm1 + 43c68b: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 + 43c68f: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 + 43c694: 66 0f 3a 0f da 08 palignr $0x8,%xmm2,%xmm3 + 43c69a: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 + 43c69f: 66 0f db d9 pand %xmm1,%xmm3 + 43c6a3: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43c6a7: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43c6ab: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43c6af: 81 ea ff ff 00 00 sub $0xffff,%edx + 43c6b5: 0f 85 35 08 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43c6bb: 48 83 c6 08 add $0x8,%rsi + 43c6bf: 48 01 ce add %rcx,%rsi + 43c6c2: 48 01 cf add %rcx,%rdi + 43c6c5: e9 36 09 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43c6ca: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43c6d0: 48 83 e9 20 sub $0x20,%rcx + 43c6d4: 66 0f 6f 46 10 movdqa 0x10(%rsi),%xmm0 + 43c6d9: 66 0f 3a 0f 06 08 palignr $0x8,(%rsi),%xmm0 + 43c6df: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 43c6e3: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 + 43c6e8: 66 0f 3a 0f 5e 10 08 palignr $0x8,0x10(%rsi),%xmm3 + 43c6ef: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 + 43c6f4: 66 0f db d8 pand %xmm0,%xmm3 + 43c6f8: 48 83 e9 20 sub $0x20,%rcx + 43c6fc: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43c700: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43c704: 66 0f 6f 5e 40 movdqa 0x40(%rsi),%xmm3 + 43c709: 66 0f 3a 0f 5e 30 08 palignr $0x8,0x30(%rsi),%xmm3 + 43c710: 81 da ff ff 00 00 sbb $0xffff,%edx + 43c716: 66 0f 6f 46 30 movdqa 0x30(%rsi),%xmm0 + 43c71b: 66 0f 3a 0f 46 20 08 palignr $0x8,0x20(%rsi),%xmm0 + 43c722: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 + 43c727: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43c72b: 66 0f 74 5f 30 pcmpeqb 0x30(%rdi),%xmm3 + 43c730: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43c734: 74 be je 43c6f4 <__memcmp_ssse3+0x9c4> + 43c736: 66 0f db d8 pand %xmm0,%xmm3 + 43c73a: 48 83 f9 00 cmp $0x0,%rcx + 43c73e: 7d 06 jge 43c746 <__memcmp_ssse3+0xa16> + 43c740: ff c2 inc %edx + 43c742: 48 83 c1 20 add $0x20,%rcx + 43c746: 85 d2 test %edx,%edx + 43c748: 0f 85 a2 07 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43c74e: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43c752: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43c756: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43c75a: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43c75e: 81 ea ff ff 00 00 sub $0xffff,%edx + 43c764: 0f 85 86 07 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43c76a: 48 8d 76 08 lea 0x8(%rsi),%rsi + 43c76e: 48 01 ce add %rcx,%rsi + 43c771: 48 01 cf add %rcx,%rdi + 43c774: e9 87 08 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43c779: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43c780: 48 83 f9 50 cmp $0x50,%rcx + 43c784: 48 8d 49 d0 lea -0x30(%rcx),%rcx + 43c788: 89 d0 mov %edx,%eax + 43c78a: 73 54 jae 43c7e0 <__memcmp_ssse3+0xab0> + 43c78c: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 + 43c791: 66 0f 6f d1 movdqa %xmm1,%xmm2 + 43c795: 66 0f 3a 0f 0e 09 palignr $0x9,(%rsi),%xmm1 + 43c79b: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 + 43c79f: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 + 43c7a4: 66 0f 3a 0f da 09 palignr $0x9,%xmm2,%xmm3 + 43c7aa: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 + 43c7af: 66 0f db d9 pand %xmm1,%xmm3 + 43c7b3: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43c7b7: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43c7bb: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43c7bf: 81 ea ff ff 00 00 sub $0xffff,%edx + 43c7c5: 0f 85 25 07 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43c7cb: 48 83 c6 09 add $0x9,%rsi + 43c7cf: 48 01 ce add %rcx,%rsi + 43c7d2: 48 01 cf add %rcx,%rdi + 43c7d5: e9 26 08 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43c7da: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43c7e0: 48 83 e9 20 sub $0x20,%rcx + 43c7e4: 66 0f 6f 46 10 movdqa 0x10(%rsi),%xmm0 + 43c7e9: 66 0f 3a 0f 06 09 palignr $0x9,(%rsi),%xmm0 + 43c7ef: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 43c7f3: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 + 43c7f8: 66 0f 3a 0f 5e 10 09 palignr $0x9,0x10(%rsi),%xmm3 + 43c7ff: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 + 43c804: 66 0f db d8 pand %xmm0,%xmm3 + 43c808: 48 83 e9 20 sub $0x20,%rcx + 43c80c: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43c810: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43c814: 66 0f 6f 5e 40 movdqa 0x40(%rsi),%xmm3 + 43c819: 66 0f 3a 0f 5e 30 09 palignr $0x9,0x30(%rsi),%xmm3 + 43c820: 81 da ff ff 00 00 sbb $0xffff,%edx + 43c826: 66 0f 6f 46 30 movdqa 0x30(%rsi),%xmm0 + 43c82b: 66 0f 3a 0f 46 20 09 palignr $0x9,0x20(%rsi),%xmm0 + 43c832: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 + 43c837: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43c83b: 66 0f 74 5f 30 pcmpeqb 0x30(%rdi),%xmm3 + 43c840: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43c844: 74 be je 43c804 <__memcmp_ssse3+0xad4> + 43c846: 66 0f db d8 pand %xmm0,%xmm3 + 43c84a: 48 83 f9 00 cmp $0x0,%rcx + 43c84e: 7d 06 jge 43c856 <__memcmp_ssse3+0xb26> + 43c850: ff c2 inc %edx + 43c852: 48 83 c1 20 add $0x20,%rcx + 43c856: 85 d2 test %edx,%edx + 43c858: 0f 85 92 06 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43c85e: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43c862: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43c866: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43c86a: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43c86e: 81 ea ff ff 00 00 sub $0xffff,%edx + 43c874: 0f 85 76 06 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43c87a: 48 8d 76 09 lea 0x9(%rsi),%rsi + 43c87e: 48 01 ce add %rcx,%rsi + 43c881: 48 01 cf add %rcx,%rdi + 43c884: e9 77 07 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43c889: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43c890: 48 83 f9 50 cmp $0x50,%rcx + 43c894: 48 8d 49 d0 lea -0x30(%rcx),%rcx + 43c898: 89 d0 mov %edx,%eax + 43c89a: 73 54 jae 43c8f0 <__memcmp_ssse3+0xbc0> + 43c89c: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 + 43c8a1: 66 0f 6f d1 movdqa %xmm1,%xmm2 + 43c8a5: 66 0f 3a 0f 0e 0a palignr $0xa,(%rsi),%xmm1 + 43c8ab: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 + 43c8af: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 + 43c8b4: 66 0f 3a 0f da 0a palignr $0xa,%xmm2,%xmm3 + 43c8ba: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 + 43c8bf: 66 0f db d9 pand %xmm1,%xmm3 + 43c8c3: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43c8c7: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43c8cb: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43c8cf: 81 ea ff ff 00 00 sub $0xffff,%edx + 43c8d5: 0f 85 15 06 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43c8db: 48 83 c6 0a add $0xa,%rsi + 43c8df: 48 01 ce add %rcx,%rsi + 43c8e2: 48 01 cf add %rcx,%rdi + 43c8e5: e9 16 07 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43c8ea: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43c8f0: 48 83 e9 20 sub $0x20,%rcx + 43c8f4: 66 0f 6f 46 10 movdqa 0x10(%rsi),%xmm0 + 43c8f9: 66 0f 3a 0f 06 0a palignr $0xa,(%rsi),%xmm0 + 43c8ff: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 43c903: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 + 43c908: 66 0f 3a 0f 5e 10 0a palignr $0xa,0x10(%rsi),%xmm3 + 43c90f: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 + 43c914: 66 0f db d8 pand %xmm0,%xmm3 + 43c918: 48 83 e9 20 sub $0x20,%rcx + 43c91c: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43c920: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43c924: 66 0f 6f 5e 40 movdqa 0x40(%rsi),%xmm3 + 43c929: 66 0f 3a 0f 5e 30 0a palignr $0xa,0x30(%rsi),%xmm3 + 43c930: 81 da ff ff 00 00 sbb $0xffff,%edx + 43c936: 66 0f 6f 46 30 movdqa 0x30(%rsi),%xmm0 + 43c93b: 66 0f 3a 0f 46 20 0a palignr $0xa,0x20(%rsi),%xmm0 + 43c942: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 + 43c947: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43c94b: 66 0f 74 5f 30 pcmpeqb 0x30(%rdi),%xmm3 + 43c950: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43c954: 74 be je 43c914 <__memcmp_ssse3+0xbe4> + 43c956: 66 0f db d8 pand %xmm0,%xmm3 + 43c95a: 48 83 f9 00 cmp $0x0,%rcx + 43c95e: 7d 06 jge 43c966 <__memcmp_ssse3+0xc36> + 43c960: ff c2 inc %edx + 43c962: 48 83 c1 20 add $0x20,%rcx + 43c966: 85 d2 test %edx,%edx + 43c968: 0f 85 82 05 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43c96e: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43c972: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43c976: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43c97a: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43c97e: 81 ea ff ff 00 00 sub $0xffff,%edx + 43c984: 0f 85 66 05 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43c98a: 48 8d 76 0a lea 0xa(%rsi),%rsi + 43c98e: 48 01 ce add %rcx,%rsi + 43c991: 48 01 cf add %rcx,%rdi + 43c994: e9 67 06 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43c999: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43c9a0: 48 83 f9 50 cmp $0x50,%rcx + 43c9a4: 48 8d 49 d0 lea -0x30(%rcx),%rcx + 43c9a8: 89 d0 mov %edx,%eax + 43c9aa: 73 54 jae 43ca00 <__memcmp_ssse3+0xcd0> + 43c9ac: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 + 43c9b1: 66 0f 6f d1 movdqa %xmm1,%xmm2 + 43c9b5: 66 0f 3a 0f 0e 0b palignr $0xb,(%rsi),%xmm1 + 43c9bb: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 + 43c9bf: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 + 43c9c4: 66 0f 3a 0f da 0b palignr $0xb,%xmm2,%xmm3 + 43c9ca: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 + 43c9cf: 66 0f db d9 pand %xmm1,%xmm3 + 43c9d3: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43c9d7: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43c9db: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43c9df: 81 ea ff ff 00 00 sub $0xffff,%edx + 43c9e5: 0f 85 05 05 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43c9eb: 48 83 c6 0b add $0xb,%rsi + 43c9ef: 48 01 ce add %rcx,%rsi + 43c9f2: 48 01 cf add %rcx,%rdi + 43c9f5: e9 06 06 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43c9fa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43ca00: 48 83 e9 20 sub $0x20,%rcx + 43ca04: 66 0f 6f 46 10 movdqa 0x10(%rsi),%xmm0 + 43ca09: 66 0f 3a 0f 06 0b palignr $0xb,(%rsi),%xmm0 + 43ca0f: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 43ca13: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 + 43ca18: 66 0f 3a 0f 5e 10 0b palignr $0xb,0x10(%rsi),%xmm3 + 43ca1f: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 + 43ca24: 66 0f db d8 pand %xmm0,%xmm3 + 43ca28: 48 83 e9 20 sub $0x20,%rcx + 43ca2c: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43ca30: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43ca34: 66 0f 6f 5e 40 movdqa 0x40(%rsi),%xmm3 + 43ca39: 66 0f 3a 0f 5e 30 0b palignr $0xb,0x30(%rsi),%xmm3 + 43ca40: 81 da ff ff 00 00 sbb $0xffff,%edx + 43ca46: 66 0f 6f 46 30 movdqa 0x30(%rsi),%xmm0 + 43ca4b: 66 0f 3a 0f 46 20 0b palignr $0xb,0x20(%rsi),%xmm0 + 43ca52: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 + 43ca57: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43ca5b: 66 0f 74 5f 30 pcmpeqb 0x30(%rdi),%xmm3 + 43ca60: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43ca64: 74 be je 43ca24 <__memcmp_ssse3+0xcf4> + 43ca66: 66 0f db d8 pand %xmm0,%xmm3 + 43ca6a: 48 83 f9 00 cmp $0x0,%rcx + 43ca6e: 7d 06 jge 43ca76 <__memcmp_ssse3+0xd46> + 43ca70: ff c2 inc %edx + 43ca72: 48 83 c1 20 add $0x20,%rcx + 43ca76: 85 d2 test %edx,%edx + 43ca78: 0f 85 72 04 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43ca7e: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43ca82: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43ca86: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43ca8a: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43ca8e: 81 ea ff ff 00 00 sub $0xffff,%edx + 43ca94: 0f 85 56 04 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43ca9a: 48 8d 76 0b lea 0xb(%rsi),%rsi + 43ca9e: 48 01 ce add %rcx,%rsi + 43caa1: 48 01 cf add %rcx,%rdi + 43caa4: e9 57 05 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43caa9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43cab0: 48 83 f9 50 cmp $0x50,%rcx + 43cab4: 48 8d 49 d0 lea -0x30(%rcx),%rcx + 43cab8: 89 d0 mov %edx,%eax + 43caba: 73 54 jae 43cb10 <__memcmp_ssse3+0xde0> + 43cabc: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 + 43cac1: 66 0f 6f d1 movdqa %xmm1,%xmm2 + 43cac5: 66 0f 3a 0f 0e 0c palignr $0xc,(%rsi),%xmm1 + 43cacb: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 + 43cacf: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 + 43cad4: 66 0f 3a 0f da 0c palignr $0xc,%xmm2,%xmm3 + 43cada: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 + 43cadf: 66 0f db d9 pand %xmm1,%xmm3 + 43cae3: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43cae7: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43caeb: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43caef: 81 ea ff ff 00 00 sub $0xffff,%edx + 43caf5: 0f 85 f5 03 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43cafb: 48 83 c6 0c add $0xc,%rsi + 43caff: 48 01 ce add %rcx,%rsi + 43cb02: 48 01 cf add %rcx,%rdi + 43cb05: e9 f6 04 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43cb0a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43cb10: 48 83 e9 20 sub $0x20,%rcx + 43cb14: 66 0f 6f 46 10 movdqa 0x10(%rsi),%xmm0 + 43cb19: 66 0f 3a 0f 06 0c palignr $0xc,(%rsi),%xmm0 + 43cb1f: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 43cb23: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 + 43cb28: 66 0f 3a 0f 5e 10 0c palignr $0xc,0x10(%rsi),%xmm3 + 43cb2f: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 + 43cb34: 66 0f db d8 pand %xmm0,%xmm3 + 43cb38: 48 83 e9 20 sub $0x20,%rcx + 43cb3c: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43cb40: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43cb44: 66 0f 6f 5e 40 movdqa 0x40(%rsi),%xmm3 + 43cb49: 66 0f 3a 0f 5e 30 0c palignr $0xc,0x30(%rsi),%xmm3 + 43cb50: 81 da ff ff 00 00 sbb $0xffff,%edx + 43cb56: 66 0f 6f 46 30 movdqa 0x30(%rsi),%xmm0 + 43cb5b: 66 0f 3a 0f 46 20 0c palignr $0xc,0x20(%rsi),%xmm0 + 43cb62: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 + 43cb67: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43cb6b: 66 0f 74 5f 30 pcmpeqb 0x30(%rdi),%xmm3 + 43cb70: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43cb74: 74 be je 43cb34 <__memcmp_ssse3+0xe04> + 43cb76: 66 0f db d8 pand %xmm0,%xmm3 + 43cb7a: 48 83 f9 00 cmp $0x0,%rcx + 43cb7e: 7d 06 jge 43cb86 <__memcmp_ssse3+0xe56> + 43cb80: ff c2 inc %edx + 43cb82: 48 83 c1 20 add $0x20,%rcx + 43cb86: 85 d2 test %edx,%edx + 43cb88: 0f 85 62 03 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43cb8e: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43cb92: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43cb96: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43cb9a: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43cb9e: 81 ea ff ff 00 00 sub $0xffff,%edx + 43cba4: 0f 85 46 03 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43cbaa: 48 8d 76 0c lea 0xc(%rsi),%rsi + 43cbae: 48 01 ce add %rcx,%rsi + 43cbb1: 48 01 cf add %rcx,%rdi + 43cbb4: e9 47 04 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43cbb9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43cbc0: 48 83 f9 50 cmp $0x50,%rcx + 43cbc4: 48 8d 49 d0 lea -0x30(%rcx),%rcx + 43cbc8: 89 d0 mov %edx,%eax + 43cbca: 73 54 jae 43cc20 <__memcmp_ssse3+0xef0> + 43cbcc: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 + 43cbd1: 66 0f 6f d1 movdqa %xmm1,%xmm2 + 43cbd5: 66 0f 3a 0f 0e 0d palignr $0xd,(%rsi),%xmm1 + 43cbdb: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 + 43cbdf: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 + 43cbe4: 66 0f 3a 0f da 0d palignr $0xd,%xmm2,%xmm3 + 43cbea: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 + 43cbef: 66 0f db d9 pand %xmm1,%xmm3 + 43cbf3: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43cbf7: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43cbfb: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43cbff: 81 ea ff ff 00 00 sub $0xffff,%edx + 43cc05: 0f 85 e5 02 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43cc0b: 48 83 c6 0d add $0xd,%rsi + 43cc0f: 48 01 ce add %rcx,%rsi + 43cc12: 48 01 cf add %rcx,%rdi + 43cc15: e9 e6 03 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43cc1a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43cc20: 48 83 e9 20 sub $0x20,%rcx + 43cc24: 66 0f 6f 46 10 movdqa 0x10(%rsi),%xmm0 + 43cc29: 66 0f 3a 0f 06 0d palignr $0xd,(%rsi),%xmm0 + 43cc2f: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 43cc33: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 + 43cc38: 66 0f 3a 0f 5e 10 0d palignr $0xd,0x10(%rsi),%xmm3 + 43cc3f: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 + 43cc44: 66 0f db d8 pand %xmm0,%xmm3 + 43cc48: 48 83 e9 20 sub $0x20,%rcx + 43cc4c: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43cc50: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43cc54: 66 0f 6f 5e 40 movdqa 0x40(%rsi),%xmm3 + 43cc59: 66 0f 3a 0f 5e 30 0d palignr $0xd,0x30(%rsi),%xmm3 + 43cc60: 81 da ff ff 00 00 sbb $0xffff,%edx + 43cc66: 66 0f 6f 46 30 movdqa 0x30(%rsi),%xmm0 + 43cc6b: 66 0f 3a 0f 46 20 0d palignr $0xd,0x20(%rsi),%xmm0 + 43cc72: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 + 43cc77: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43cc7b: 66 0f 74 5f 30 pcmpeqb 0x30(%rdi),%xmm3 + 43cc80: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43cc84: 74 be je 43cc44 <__memcmp_ssse3+0xf14> + 43cc86: 66 0f db d8 pand %xmm0,%xmm3 + 43cc8a: 48 83 f9 00 cmp $0x0,%rcx + 43cc8e: 7d 06 jge 43cc96 <__memcmp_ssse3+0xf66> + 43cc90: ff c2 inc %edx + 43cc92: 48 83 c1 20 add $0x20,%rcx + 43cc96: 85 d2 test %edx,%edx + 43cc98: 0f 85 52 02 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43cc9e: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43cca2: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43cca6: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43ccaa: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43ccae: 81 ea ff ff 00 00 sub $0xffff,%edx + 43ccb4: 0f 85 36 02 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43ccba: 48 8d 76 0d lea 0xd(%rsi),%rsi + 43ccbe: 48 01 ce add %rcx,%rsi + 43ccc1: 48 01 cf add %rcx,%rdi + 43ccc4: e9 37 03 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43ccc9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43ccd0: 48 83 f9 50 cmp $0x50,%rcx + 43ccd4: 48 8d 49 d0 lea -0x30(%rcx),%rcx + 43ccd8: 89 d0 mov %edx,%eax + 43ccda: 73 54 jae 43cd30 <__memcmp_ssse3+0x1000> + 43ccdc: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 + 43cce1: 66 0f 6f d1 movdqa %xmm1,%xmm2 + 43cce5: 66 0f 3a 0f 0e 0e palignr $0xe,(%rsi),%xmm1 + 43cceb: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 + 43ccef: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 + 43ccf4: 66 0f 3a 0f da 0e palignr $0xe,%xmm2,%xmm3 + 43ccfa: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 + 43ccff: 66 0f db d9 pand %xmm1,%xmm3 + 43cd03: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43cd07: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43cd0b: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43cd0f: 81 ea ff ff 00 00 sub $0xffff,%edx + 43cd15: 0f 85 d5 01 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43cd1b: 48 83 c6 0e add $0xe,%rsi + 43cd1f: 48 01 ce add %rcx,%rsi + 43cd22: 48 01 cf add %rcx,%rdi + 43cd25: e9 d6 02 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43cd2a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43cd30: 48 83 e9 20 sub $0x20,%rcx + 43cd34: 66 0f 6f 46 10 movdqa 0x10(%rsi),%xmm0 + 43cd39: 66 0f 3a 0f 06 0e palignr $0xe,(%rsi),%xmm0 + 43cd3f: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 43cd43: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 + 43cd48: 66 0f 3a 0f 5e 10 0e palignr $0xe,0x10(%rsi),%xmm3 + 43cd4f: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 + 43cd54: 66 0f db d8 pand %xmm0,%xmm3 + 43cd58: 48 83 e9 20 sub $0x20,%rcx + 43cd5c: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43cd60: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43cd64: 66 0f 6f 5e 40 movdqa 0x40(%rsi),%xmm3 + 43cd69: 66 0f 3a 0f 5e 30 0e palignr $0xe,0x30(%rsi),%xmm3 + 43cd70: 81 da ff ff 00 00 sbb $0xffff,%edx + 43cd76: 66 0f 6f 46 30 movdqa 0x30(%rsi),%xmm0 + 43cd7b: 66 0f 3a 0f 46 20 0e palignr $0xe,0x20(%rsi),%xmm0 + 43cd82: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 + 43cd87: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43cd8b: 66 0f 74 5f 30 pcmpeqb 0x30(%rdi),%xmm3 + 43cd90: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43cd94: 74 be je 43cd54 <__memcmp_ssse3+0x1024> + 43cd96: 66 0f db d8 pand %xmm0,%xmm3 + 43cd9a: 48 83 f9 00 cmp $0x0,%rcx + 43cd9e: 7d 06 jge 43cda6 <__memcmp_ssse3+0x1076> + 43cda0: ff c2 inc %edx + 43cda2: 48 83 c1 20 add $0x20,%rcx + 43cda6: 85 d2 test %edx,%edx + 43cda8: 0f 85 42 01 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43cdae: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43cdb2: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43cdb6: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43cdba: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43cdbe: 81 ea ff ff 00 00 sub $0xffff,%edx + 43cdc4: 0f 85 26 01 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43cdca: 48 8d 76 0e lea 0xe(%rsi),%rsi + 43cdce: 48 01 ce add %rcx,%rsi + 43cdd1: 48 01 cf add %rcx,%rdi + 43cdd4: e9 27 02 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43cdd9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43cde0: 48 83 f9 50 cmp $0x50,%rcx + 43cde4: 48 8d 49 d0 lea -0x30(%rcx),%rcx + 43cde8: 89 d0 mov %edx,%eax + 43cdea: 73 54 jae 43ce40 <__memcmp_ssse3+0x1110> + 43cdec: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 + 43cdf1: 66 0f 6f d1 movdqa %xmm1,%xmm2 + 43cdf5: 66 0f 3a 0f 0e 0f palignr $0xf,(%rsi),%xmm1 + 43cdfb: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 + 43cdff: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 + 43ce04: 66 0f 3a 0f da 0f palignr $0xf,%xmm2,%xmm3 + 43ce0a: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 + 43ce0f: 66 0f db d9 pand %xmm1,%xmm3 + 43ce13: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43ce17: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43ce1b: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43ce1f: 81 ea ff ff 00 00 sub $0xffff,%edx + 43ce25: 0f 85 c5 00 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43ce2b: 48 83 c6 0f add $0xf,%rsi + 43ce2f: 48 01 ce add %rcx,%rsi + 43ce32: 48 01 cf add %rcx,%rdi + 43ce35: e9 c6 01 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43ce3a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43ce40: 48 83 e9 20 sub $0x20,%rcx + 43ce44: 66 0f 6f 46 10 movdqa 0x10(%rsi),%xmm0 + 43ce49: 66 0f 3a 0f 06 0f palignr $0xf,(%rsi),%xmm0 + 43ce4f: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 + 43ce53: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 + 43ce58: 66 0f 3a 0f 5e 10 0f palignr $0xf,0x10(%rsi),%xmm3 + 43ce5f: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 + 43ce64: 66 0f db d8 pand %xmm0,%xmm3 + 43ce68: 48 83 e9 20 sub $0x20,%rcx + 43ce6c: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43ce70: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43ce74: 66 0f 6f 5e 40 movdqa 0x40(%rsi),%xmm3 + 43ce79: 66 0f 3a 0f 5e 30 0f palignr $0xf,0x30(%rsi),%xmm3 + 43ce80: 81 da ff ff 00 00 sbb $0xffff,%edx + 43ce86: 66 0f 6f 46 30 movdqa 0x30(%rsi),%xmm0 + 43ce8b: 66 0f 3a 0f 46 20 0f palignr $0xf,0x20(%rsi),%xmm0 + 43ce92: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 + 43ce97: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43ce9b: 66 0f 74 5f 30 pcmpeqb 0x30(%rdi),%xmm3 + 43cea0: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43cea4: 74 be je 43ce64 <__memcmp_ssse3+0x1134> + 43cea6: 66 0f db d8 pand %xmm0,%xmm3 + 43ceaa: 48 83 f9 00 cmp $0x0,%rcx + 43ceae: 7d 06 jge 43ceb6 <__memcmp_ssse3+0x1186> + 43ceb0: ff c2 inc %edx + 43ceb2: 48 83 c1 20 add $0x20,%rcx + 43ceb6: 85 d2 test %edx,%edx + 43ceb8: 75 36 jne 43cef0 <__memcmp_ssse3+0x11c0> + 43ceba: 66 0f d7 d3 pmovmskb %xmm3,%edx + 43cebe: 66 0f 6f c8 movdqa %xmm0,%xmm1 + 43cec2: 48 8d 7f 20 lea 0x20(%rdi),%rdi + 43cec6: 48 8d 76 20 lea 0x20(%rsi),%rsi + 43ceca: 81 ea ff ff 00 00 sub $0xffff,%edx + 43ced0: 75 1e jne 43cef0 <__memcmp_ssse3+0x11c0> + 43ced2: 48 8d 76 0f lea 0xf(%rsi),%rsi + 43ced6: 48 01 ce add %rcx,%rsi + 43ced9: 48 01 cf add %rcx,%rdi + 43cedc: e9 1f 01 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> + 43cee1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43cee6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43ceed: 00 00 00 + 43cef0: 66 44 0f d7 c1 pmovmskb %xmm1,%r8d + 43cef5: 41 81 e8 ff ff 00 00 sub $0xffff,%r8d + 43cefc: 74 0b je 43cf09 <__memcmp_ssse3+0x11d9> + 43cefe: 48 8d 76 f0 lea -0x10(%rsi),%rsi + 43cf02: 48 8d 7f f0 lea -0x10(%rdi),%rdi + 43cf06: 44 89 c2 mov %r8d,%edx + 43cf09: 48 01 c6 add %rax,%rsi + 43cf0c: 84 d2 test %dl,%dl + 43cf0e: 0f 84 ac 00 00 00 je 43cfc0 <__memcmp_ssse3+0x1290> + 43cf14: f6 c2 01 test $0x1,%dl + 43cf17: 75 37 jne 43cf50 <__memcmp_ssse3+0x1220> + 43cf19: f6 c2 02 test $0x2,%dl + 43cf1c: 75 42 jne 43cf60 <__memcmp_ssse3+0x1230> + 43cf1e: f6 c2 04 test $0x4,%dl + 43cf21: 75 4d jne 43cf70 <__memcmp_ssse3+0x1240> + 43cf23: f6 c2 08 test $0x8,%dl + 43cf26: 75 58 jne 43cf80 <__memcmp_ssse3+0x1250> + 43cf28: f6 c2 10 test $0x10,%dl + 43cf2b: 75 63 jne 43cf90 <__memcmp_ssse3+0x1260> + 43cf2d: f6 c2 20 test $0x20,%dl + 43cf30: 75 6e jne 43cfa0 <__memcmp_ssse3+0x1270> + 43cf32: f6 c2 40 test $0x40,%dl + 43cf35: 75 79 jne 43cfb0 <__memcmp_ssse3+0x1280> + 43cf37: 0f b6 47 f7 movzbl -0x9(%rdi),%eax + 43cf3b: 0f b6 56 f7 movzbl -0x9(%rsi),%edx + 43cf3f: 29 d0 sub %edx,%eax + 43cf41: c3 retq + 43cf42: 0f 1f 40 00 nopl 0x0(%rax) + 43cf46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43cf4d: 00 00 00 + 43cf50: 0f b6 47 f0 movzbl -0x10(%rdi),%eax + 43cf54: 0f b6 56 f0 movzbl -0x10(%rsi),%edx + 43cf58: 29 d0 sub %edx,%eax + 43cf5a: c3 retq + 43cf5b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43cf60: 0f b6 47 f1 movzbl -0xf(%rdi),%eax + 43cf64: 0f b6 56 f1 movzbl -0xf(%rsi),%edx + 43cf68: 29 d0 sub %edx,%eax + 43cf6a: c3 retq + 43cf6b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43cf70: 0f b6 47 f2 movzbl -0xe(%rdi),%eax + 43cf74: 0f b6 56 f2 movzbl -0xe(%rsi),%edx + 43cf78: 29 d0 sub %edx,%eax + 43cf7a: c3 retq + 43cf7b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43cf80: 0f b6 47 f3 movzbl -0xd(%rdi),%eax + 43cf84: 0f b6 56 f3 movzbl -0xd(%rsi),%edx + 43cf88: 29 d0 sub %edx,%eax + 43cf8a: c3 retq + 43cf8b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43cf90: 0f b6 47 f4 movzbl -0xc(%rdi),%eax + 43cf94: 0f b6 56 f4 movzbl -0xc(%rsi),%edx + 43cf98: 29 d0 sub %edx,%eax + 43cf9a: c3 retq + 43cf9b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43cfa0: 0f b6 47 f5 movzbl -0xb(%rdi),%eax + 43cfa4: 0f b6 56 f5 movzbl -0xb(%rsi),%edx + 43cfa8: 29 d0 sub %edx,%eax + 43cfaa: c3 retq + 43cfab: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43cfb0: 0f b6 47 f6 movzbl -0xa(%rdi),%eax + 43cfb4: 0f b6 56 f6 movzbl -0xa(%rsi),%edx + 43cfb8: 29 d0 sub %edx,%eax + 43cfba: c3 retq + 43cfbb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43cfc0: 48 8d 7f 08 lea 0x8(%rdi),%rdi + 43cfc4: 48 8d 76 08 lea 0x8(%rsi),%rsi + 43cfc8: f6 c6 01 test $0x1,%dh + 43cfcb: 75 83 jne 43cf50 <__memcmp_ssse3+0x1220> + 43cfcd: f6 c6 02 test $0x2,%dh + 43cfd0: 75 8e jne 43cf60 <__memcmp_ssse3+0x1230> + 43cfd2: f6 c6 04 test $0x4,%dh + 43cfd5: 75 99 jne 43cf70 <__memcmp_ssse3+0x1240> + 43cfd7: f6 c6 08 test $0x8,%dh + 43cfda: 75 a4 jne 43cf80 <__memcmp_ssse3+0x1250> + 43cfdc: f6 c6 10 test $0x10,%dh + 43cfdf: 75 af jne 43cf90 <__memcmp_ssse3+0x1260> + 43cfe1: f6 c6 20 test $0x20,%dh + 43cfe4: 75 ba jne 43cfa0 <__memcmp_ssse3+0x1270> + 43cfe6: f6 c6 40 test $0x40,%dh + 43cfe9: 75 c5 jne 43cfb0 <__memcmp_ssse3+0x1280> + 43cfeb: 0f b6 47 f7 movzbl -0x9(%rdi),%eax + 43cfef: 0f b6 56 f7 movzbl -0x9(%rsi),%edx + 43cff3: 29 d0 sub %edx,%eax + 43cff5: c3 retq + 43cff6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43cffd: 00 00 00 + 43d000: 83 f9 08 cmp $0x8,%ecx + 43d003: 73 4b jae 43d050 <__memcmp_ssse3+0x1320> + 43d005: 83 f9 00 cmp $0x0,%ecx + 43d008: 0f 84 5c 02 00 00 je 43d26a <__memcmp_ssse3+0x153a> + 43d00e: 83 f9 01 cmp $0x1,%ecx + 43d011: 0f 84 f3 02 00 00 je 43d30a <__memcmp_ssse3+0x15da> + 43d017: 83 f9 02 cmp $0x2,%ecx + 43d01a: 0f 84 9a 03 00 00 je 43d3ba <__memcmp_ssse3+0x168a> + 43d020: 83 f9 03 cmp $0x3,%ecx + 43d023: 0f 84 29 04 00 00 je 43d452 <__memcmp_ssse3+0x1722> + 43d029: 83 f9 04 cmp $0x4,%ecx + 43d02c: 0f 84 2a 02 00 00 je 43d25c <__memcmp_ssse3+0x152c> + 43d032: 83 f9 05 cmp $0x5,%ecx + 43d035: 0f 84 c1 02 00 00 je 43d2fc <__memcmp_ssse3+0x15cc> + 43d03b: 83 f9 06 cmp $0x6,%ecx + 43d03e: 0f 84 68 03 00 00 je 43d3ac <__memcmp_ssse3+0x167c> + 43d044: e9 ff 03 00 00 jmpq 43d448 <__memcmp_ssse3+0x1718> + 43d049: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43d050: 83 f9 10 cmp $0x10,%ecx + 43d053: 73 4b jae 43d0a0 <__memcmp_ssse3+0x1370> + 43d055: 83 f9 08 cmp $0x8,%ecx + 43d058: 0f 84 f0 01 00 00 je 43d24e <__memcmp_ssse3+0x151e> + 43d05e: 83 f9 09 cmp $0x9,%ecx + 43d061: 0f 84 87 02 00 00 je 43d2ee <__memcmp_ssse3+0x15be> + 43d067: 83 f9 0a cmp $0xa,%ecx + 43d06a: 0f 84 2e 03 00 00 je 43d39e <__memcmp_ssse3+0x166e> + 43d070: 83 f9 0b cmp $0xb,%ecx + 43d073: 0f 84 c5 03 00 00 je 43d43e <__memcmp_ssse3+0x170e> + 43d079: 83 f9 0c cmp $0xc,%ecx + 43d07c: 0f 84 be 01 00 00 je 43d240 <__memcmp_ssse3+0x1510> + 43d082: 83 f9 0d cmp $0xd,%ecx + 43d085: 0f 84 55 02 00 00 je 43d2e0 <__memcmp_ssse3+0x15b0> + 43d08b: 83 f9 0e cmp $0xe,%ecx + 43d08e: 0f 84 fc 02 00 00 je 43d390 <__memcmp_ssse3+0x1660> + 43d094: e9 9b 03 00 00 jmpq 43d434 <__memcmp_ssse3+0x1704> + 43d099: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43d0a0: 83 f9 18 cmp $0x18,%ecx + 43d0a3: 73 4b jae 43d0f0 <__memcmp_ssse3+0x13c0> + 43d0a5: 83 f9 10 cmp $0x10,%ecx + 43d0a8: 0f 84 84 01 00 00 je 43d232 <__memcmp_ssse3+0x1502> + 43d0ae: 83 f9 11 cmp $0x11,%ecx + 43d0b1: 0f 84 1b 02 00 00 je 43d2d2 <__memcmp_ssse3+0x15a2> + 43d0b7: 83 f9 12 cmp $0x12,%ecx + 43d0ba: 0f 84 c2 02 00 00 je 43d382 <__memcmp_ssse3+0x1652> + 43d0c0: 83 f9 13 cmp $0x13,%ecx + 43d0c3: 0f 84 61 03 00 00 je 43d42a <__memcmp_ssse3+0x16fa> + 43d0c9: 83 f9 14 cmp $0x14,%ecx + 43d0cc: 0f 84 52 01 00 00 je 43d224 <__memcmp_ssse3+0x14f4> + 43d0d2: 83 f9 15 cmp $0x15,%ecx + 43d0d5: 0f 84 e9 01 00 00 je 43d2c4 <__memcmp_ssse3+0x1594> + 43d0db: 83 f9 16 cmp $0x16,%ecx + 43d0de: 0f 84 90 02 00 00 je 43d374 <__memcmp_ssse3+0x1644> + 43d0e4: e9 37 03 00 00 jmpq 43d420 <__memcmp_ssse3+0x16f0> + 43d0e9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43d0f0: 83 f9 20 cmp $0x20,%ecx + 43d0f3: 73 4b jae 43d140 <__memcmp_ssse3+0x1410> + 43d0f5: 83 f9 18 cmp $0x18,%ecx + 43d0f8: 0f 84 18 01 00 00 je 43d216 <__memcmp_ssse3+0x14e6> + 43d0fe: 83 f9 19 cmp $0x19,%ecx + 43d101: 0f 84 af 01 00 00 je 43d2b6 <__memcmp_ssse3+0x1586> + 43d107: 83 f9 1a cmp $0x1a,%ecx + 43d10a: 0f 84 56 02 00 00 je 43d366 <__memcmp_ssse3+0x1636> + 43d110: 83 f9 1b cmp $0x1b,%ecx + 43d113: 0f 84 fd 02 00 00 je 43d416 <__memcmp_ssse3+0x16e6> + 43d119: 83 f9 1c cmp $0x1c,%ecx + 43d11c: 0f 84 e6 00 00 00 je 43d208 <__memcmp_ssse3+0x14d8> + 43d122: 83 f9 1d cmp $0x1d,%ecx + 43d125: 0f 84 7d 01 00 00 je 43d2a8 <__memcmp_ssse3+0x1578> + 43d12b: 83 f9 1e cmp $0x1e,%ecx + 43d12e: 0f 84 24 02 00 00 je 43d358 <__memcmp_ssse3+0x1628> + 43d134: e9 d3 02 00 00 jmpq 43d40c <__memcmp_ssse3+0x16dc> + 43d139: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43d140: 83 f9 28 cmp $0x28,%ecx + 43d143: 73 4b jae 43d190 <__memcmp_ssse3+0x1460> + 43d145: 83 f9 20 cmp $0x20,%ecx + 43d148: 0f 84 ac 00 00 00 je 43d1fa <__memcmp_ssse3+0x14ca> + 43d14e: 83 f9 21 cmp $0x21,%ecx + 43d151: 0f 84 43 01 00 00 je 43d29a <__memcmp_ssse3+0x156a> + 43d157: 83 f9 22 cmp $0x22,%ecx + 43d15a: 0f 84 ea 01 00 00 je 43d34a <__memcmp_ssse3+0x161a> + 43d160: 83 f9 23 cmp $0x23,%ecx + 43d163: 0f 84 99 02 00 00 je 43d402 <__memcmp_ssse3+0x16d2> + 43d169: 83 f9 24 cmp $0x24,%ecx + 43d16c: 74 7e je 43d1ec <__memcmp_ssse3+0x14bc> + 43d16e: 83 f9 25 cmp $0x25,%ecx + 43d171: 0f 84 15 01 00 00 je 43d28c <__memcmp_ssse3+0x155c> + 43d177: 83 f9 26 cmp $0x26,%ecx + 43d17a: 0f 84 bc 01 00 00 je 43d33c <__memcmp_ssse3+0x160c> + 43d180: e9 73 02 00 00 jmpq 43d3f8 <__memcmp_ssse3+0x16c8> + 43d185: 90 nop + 43d186: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43d18d: 00 00 00 + 43d190: 83 f9 28 cmp $0x28,%ecx + 43d193: 74 49 je 43d1de <__memcmp_ssse3+0x14ae> + 43d195: 83 f9 29 cmp $0x29,%ecx + 43d198: 0f 84 e0 00 00 00 je 43d27e <__memcmp_ssse3+0x154e> + 43d19e: 83 f9 2a cmp $0x2a,%ecx + 43d1a1: 0f 84 87 01 00 00 je 43d32e <__memcmp_ssse3+0x15fe> + 43d1a7: 83 f9 2b cmp $0x2b,%ecx + 43d1aa: 0f 84 3e 02 00 00 je 43d3ee <__memcmp_ssse3+0x16be> + 43d1b0: 83 f9 2c cmp $0x2c,%ecx + 43d1b3: 74 1b je 43d1d0 <__memcmp_ssse3+0x14a0> + 43d1b5: 83 f9 2d cmp $0x2d,%ecx + 43d1b8: 0f 84 b2 00 00 00 je 43d270 <__memcmp_ssse3+0x1540> + 43d1be: 83 f9 2e cmp $0x2e,%ecx + 43d1c1: 0f 84 59 01 00 00 je 43d320 <__memcmp_ssse3+0x15f0> + 43d1c7: e9 14 02 00 00 jmpq 43d3e0 <__memcmp_ssse3+0x16b0> + 43d1cc: 0f 1f 40 00 nopl 0x0(%rax) + 43d1d0: 8b 47 d4 mov -0x2c(%rdi),%eax + 43d1d3: 8b 4e d4 mov -0x2c(%rsi),%ecx + 43d1d6: 39 c8 cmp %ecx,%eax + 43d1d8: 0f 85 92 02 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d1de: 8b 47 d8 mov -0x28(%rdi),%eax + 43d1e1: 8b 4e d8 mov -0x28(%rsi),%ecx + 43d1e4: 39 c8 cmp %ecx,%eax + 43d1e6: 0f 85 84 02 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d1ec: 8b 47 dc mov -0x24(%rdi),%eax + 43d1ef: 8b 4e dc mov -0x24(%rsi),%ecx + 43d1f2: 39 c8 cmp %ecx,%eax + 43d1f4: 0f 85 76 02 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d1fa: 8b 47 e0 mov -0x20(%rdi),%eax + 43d1fd: 8b 4e e0 mov -0x20(%rsi),%ecx + 43d200: 39 c8 cmp %ecx,%eax + 43d202: 0f 85 68 02 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d208: 8b 47 e4 mov -0x1c(%rdi),%eax + 43d20b: 8b 4e e4 mov -0x1c(%rsi),%ecx + 43d20e: 39 c8 cmp %ecx,%eax + 43d210: 0f 85 5a 02 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d216: 8b 47 e8 mov -0x18(%rdi),%eax + 43d219: 8b 4e e8 mov -0x18(%rsi),%ecx + 43d21c: 39 c8 cmp %ecx,%eax + 43d21e: 0f 85 4c 02 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d224: 8b 47 ec mov -0x14(%rdi),%eax + 43d227: 8b 4e ec mov -0x14(%rsi),%ecx + 43d22a: 39 c8 cmp %ecx,%eax + 43d22c: 0f 85 3e 02 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d232: 8b 47 f0 mov -0x10(%rdi),%eax + 43d235: 8b 4e f0 mov -0x10(%rsi),%ecx + 43d238: 39 c8 cmp %ecx,%eax + 43d23a: 0f 85 30 02 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d240: 8b 47 f4 mov -0xc(%rdi),%eax + 43d243: 8b 4e f4 mov -0xc(%rsi),%ecx + 43d246: 39 c8 cmp %ecx,%eax + 43d248: 0f 85 22 02 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d24e: 8b 47 f8 mov -0x8(%rdi),%eax + 43d251: 8b 4e f8 mov -0x8(%rsi),%ecx + 43d254: 39 c8 cmp %ecx,%eax + 43d256: 0f 85 14 02 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d25c: 8b 47 fc mov -0x4(%rdi),%eax + 43d25f: 8b 4e fc mov -0x4(%rsi),%ecx + 43d262: 39 c8 cmp %ecx,%eax + 43d264: 0f 85 06 02 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d26a: 31 c0 xor %eax,%eax + 43d26c: c3 retq + 43d26d: 0f 1f 00 nopl (%rax) + 43d270: 8b 47 d3 mov -0x2d(%rdi),%eax + 43d273: 8b 4e d3 mov -0x2d(%rsi),%ecx + 43d276: 39 c8 cmp %ecx,%eax + 43d278: 0f 85 f2 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d27e: 8b 47 d7 mov -0x29(%rdi),%eax + 43d281: 8b 4e d7 mov -0x29(%rsi),%ecx + 43d284: 39 c8 cmp %ecx,%eax + 43d286: 0f 85 e4 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d28c: 8b 47 db mov -0x25(%rdi),%eax + 43d28f: 8b 4e db mov -0x25(%rsi),%ecx + 43d292: 39 c8 cmp %ecx,%eax + 43d294: 0f 85 d6 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d29a: 8b 47 df mov -0x21(%rdi),%eax + 43d29d: 8b 4e df mov -0x21(%rsi),%ecx + 43d2a0: 39 c8 cmp %ecx,%eax + 43d2a2: 0f 85 c8 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d2a8: 8b 47 e3 mov -0x1d(%rdi),%eax + 43d2ab: 8b 4e e3 mov -0x1d(%rsi),%ecx + 43d2ae: 39 c8 cmp %ecx,%eax + 43d2b0: 0f 85 ba 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d2b6: 8b 47 e7 mov -0x19(%rdi),%eax + 43d2b9: 8b 4e e7 mov -0x19(%rsi),%ecx + 43d2bc: 39 c8 cmp %ecx,%eax + 43d2be: 0f 85 ac 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d2c4: 8b 47 eb mov -0x15(%rdi),%eax + 43d2c7: 8b 4e eb mov -0x15(%rsi),%ecx + 43d2ca: 39 c8 cmp %ecx,%eax + 43d2cc: 0f 85 9e 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d2d2: 8b 47 ef mov -0x11(%rdi),%eax + 43d2d5: 8b 4e ef mov -0x11(%rsi),%ecx + 43d2d8: 39 c8 cmp %ecx,%eax + 43d2da: 0f 85 90 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d2e0: 8b 47 f3 mov -0xd(%rdi),%eax + 43d2e3: 8b 4e f3 mov -0xd(%rsi),%ecx + 43d2e6: 39 c8 cmp %ecx,%eax + 43d2e8: 0f 85 82 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d2ee: 8b 47 f7 mov -0x9(%rdi),%eax + 43d2f1: 8b 4e f7 mov -0x9(%rsi),%ecx + 43d2f4: 39 c8 cmp %ecx,%eax + 43d2f6: 0f 85 74 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d2fc: 8b 47 fb mov -0x5(%rdi),%eax + 43d2ff: 8b 4e fb mov -0x5(%rsi),%ecx + 43d302: 39 c8 cmp %ecx,%eax + 43d304: 0f 85 66 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d30a: 0f b6 47 ff movzbl -0x1(%rdi),%eax + 43d30e: 3a 46 ff cmp -0x1(%rsi),%al + 43d311: 0f 85 6e 01 00 00 jne 43d485 <__memcmp_ssse3+0x1755> + 43d317: 31 c0 xor %eax,%eax + 43d319: c3 retq + 43d31a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43d320: 8b 47 d2 mov -0x2e(%rdi),%eax + 43d323: 8b 4e d2 mov -0x2e(%rsi),%ecx + 43d326: 39 c8 cmp %ecx,%eax + 43d328: 0f 85 42 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d32e: 8b 47 d6 mov -0x2a(%rdi),%eax + 43d331: 8b 4e d6 mov -0x2a(%rsi),%ecx + 43d334: 39 c8 cmp %ecx,%eax + 43d336: 0f 85 34 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d33c: 8b 47 da mov -0x26(%rdi),%eax + 43d33f: 8b 4e da mov -0x26(%rsi),%ecx + 43d342: 39 c8 cmp %ecx,%eax + 43d344: 0f 85 26 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d34a: 8b 47 de mov -0x22(%rdi),%eax + 43d34d: 8b 4e de mov -0x22(%rsi),%ecx + 43d350: 39 c8 cmp %ecx,%eax + 43d352: 0f 85 18 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d358: 8b 47 e2 mov -0x1e(%rdi),%eax + 43d35b: 8b 4e e2 mov -0x1e(%rsi),%ecx + 43d35e: 39 c8 cmp %ecx,%eax + 43d360: 0f 85 0a 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d366: 8b 47 e6 mov -0x1a(%rdi),%eax + 43d369: 8b 4e e6 mov -0x1a(%rsi),%ecx + 43d36c: 39 c8 cmp %ecx,%eax + 43d36e: 0f 85 fc 00 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d374: 8b 47 ea mov -0x16(%rdi),%eax + 43d377: 8b 4e ea mov -0x16(%rsi),%ecx + 43d37a: 39 c8 cmp %ecx,%eax + 43d37c: 0f 85 ee 00 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d382: 8b 47 ee mov -0x12(%rdi),%eax + 43d385: 8b 4e ee mov -0x12(%rsi),%ecx + 43d388: 39 c8 cmp %ecx,%eax + 43d38a: 0f 85 e0 00 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d390: 8b 47 f2 mov -0xe(%rdi),%eax + 43d393: 8b 4e f2 mov -0xe(%rsi),%ecx + 43d396: 39 c8 cmp %ecx,%eax + 43d398: 0f 85 d2 00 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d39e: 8b 47 f6 mov -0xa(%rdi),%eax + 43d3a1: 8b 4e f6 mov -0xa(%rsi),%ecx + 43d3a4: 39 c8 cmp %ecx,%eax + 43d3a6: 0f 85 c4 00 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d3ac: 8b 47 fa mov -0x6(%rdi),%eax + 43d3af: 8b 4e fa mov -0x6(%rsi),%ecx + 43d3b2: 39 c8 cmp %ecx,%eax + 43d3b4: 0f 85 b6 00 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d3ba: 0f b7 47 fe movzwl -0x2(%rdi),%eax + 43d3be: 0f b7 4e fe movzwl -0x2(%rsi),%ecx + 43d3c2: 38 c8 cmp %cl,%al + 43d3c4: 0f 85 bb 00 00 00 jne 43d485 <__memcmp_ssse3+0x1755> + 43d3ca: 39 c8 cmp %ecx,%eax + 43d3cc: 0f 85 b3 00 00 00 jne 43d485 <__memcmp_ssse3+0x1755> + 43d3d2: 31 c0 xor %eax,%eax + 43d3d4: c3 retq + 43d3d5: 90 nop + 43d3d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43d3dd: 00 00 00 + 43d3e0: 8b 47 d1 mov -0x2f(%rdi),%eax + 43d3e3: 8b 4e d1 mov -0x2f(%rsi),%ecx + 43d3e6: 39 c8 cmp %ecx,%eax + 43d3e8: 0f 85 82 00 00 00 jne 43d470 <__memcmp_ssse3+0x1740> + 43d3ee: 8b 47 d5 mov -0x2b(%rdi),%eax + 43d3f1: 8b 4e d5 mov -0x2b(%rsi),%ecx + 43d3f4: 39 c8 cmp %ecx,%eax + 43d3f6: 75 78 jne 43d470 <__memcmp_ssse3+0x1740> + 43d3f8: 8b 47 d9 mov -0x27(%rdi),%eax + 43d3fb: 8b 4e d9 mov -0x27(%rsi),%ecx + 43d3fe: 39 c8 cmp %ecx,%eax + 43d400: 75 6e jne 43d470 <__memcmp_ssse3+0x1740> + 43d402: 8b 47 dd mov -0x23(%rdi),%eax + 43d405: 8b 4e dd mov -0x23(%rsi),%ecx + 43d408: 39 c8 cmp %ecx,%eax + 43d40a: 75 64 jne 43d470 <__memcmp_ssse3+0x1740> + 43d40c: 8b 47 e1 mov -0x1f(%rdi),%eax + 43d40f: 8b 4e e1 mov -0x1f(%rsi),%ecx + 43d412: 39 c8 cmp %ecx,%eax + 43d414: 75 5a jne 43d470 <__memcmp_ssse3+0x1740> + 43d416: 8b 47 e5 mov -0x1b(%rdi),%eax + 43d419: 8b 4e e5 mov -0x1b(%rsi),%ecx + 43d41c: 39 c8 cmp %ecx,%eax + 43d41e: 75 50 jne 43d470 <__memcmp_ssse3+0x1740> + 43d420: 8b 47 e9 mov -0x17(%rdi),%eax + 43d423: 8b 4e e9 mov -0x17(%rsi),%ecx + 43d426: 39 c8 cmp %ecx,%eax + 43d428: 75 46 jne 43d470 <__memcmp_ssse3+0x1740> + 43d42a: 8b 47 ed mov -0x13(%rdi),%eax + 43d42d: 8b 4e ed mov -0x13(%rsi),%ecx + 43d430: 39 c8 cmp %ecx,%eax + 43d432: 75 3c jne 43d470 <__memcmp_ssse3+0x1740> + 43d434: 8b 47 f1 mov -0xf(%rdi),%eax + 43d437: 8b 4e f1 mov -0xf(%rsi),%ecx + 43d43a: 39 c8 cmp %ecx,%eax + 43d43c: 75 32 jne 43d470 <__memcmp_ssse3+0x1740> + 43d43e: 8b 47 f5 mov -0xb(%rdi),%eax + 43d441: 8b 4e f5 mov -0xb(%rsi),%ecx + 43d444: 39 c8 cmp %ecx,%eax + 43d446: 75 28 jne 43d470 <__memcmp_ssse3+0x1740> + 43d448: 8b 47 f9 mov -0x7(%rdi),%eax + 43d44b: 8b 4e f9 mov -0x7(%rsi),%ecx + 43d44e: 39 c8 cmp %ecx,%eax + 43d450: 75 1e jne 43d470 <__memcmp_ssse3+0x1740> + 43d452: 0f b7 47 fd movzwl -0x3(%rdi),%eax + 43d456: 0f b7 4e fd movzwl -0x3(%rsi),%ecx + 43d45a: 38 c8 cmp %cl,%al + 43d45c: 75 27 jne 43d485 <__memcmp_ssse3+0x1755> + 43d45e: 39 c8 cmp %ecx,%eax + 43d460: 75 23 jne 43d485 <__memcmp_ssse3+0x1755> + 43d462: 0f b6 47 ff movzbl -0x1(%rdi),%eax + 43d466: 3a 46 ff cmp -0x1(%rsi),%al + 43d469: 75 1a jne 43d485 <__memcmp_ssse3+0x1755> + 43d46b: 31 c0 xor %eax,%eax + 43d46d: c3 retq + 43d46e: 66 90 xchg %ax,%ax + 43d470: 38 c8 cmp %cl,%al + 43d472: 75 11 jne 43d485 <__memcmp_ssse3+0x1755> + 43d474: 66 39 c8 cmp %cx,%ax + 43d477: 75 0c jne 43d485 <__memcmp_ssse3+0x1755> + 43d479: c1 e8 10 shr $0x10,%eax + 43d47c: c1 e9 10 shr $0x10,%ecx + 43d47f: 38 c8 cmp %cl,%al + 43d481: 75 02 jne 43d485 <__memcmp_ssse3+0x1755> + 43d483: 39 c8 cmp %ecx,%eax + 43d485: 19 c0 sbb %eax,%eax + 43d487: 83 d8 ff sbb $0xffffffff,%eax + 43d48a: c3 retq + 43d48b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43d490: 31 c0 xor %eax,%eax + 43d492: c3 retq + 43d493: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43d49a: 00 00 00 + 43d49d: 0f 1f 00 nopl (%rax) + +000000000043d4a0 <__strstr_sse2_unaligned>: + 43d4a0: 0f b6 06 movzbl (%rsi),%eax + 43d4a3: 84 c0 test %al,%al + 43d4a5: 0f 84 9c 01 00 00 je 43d647 <__strstr_sse2_unaligned+0x1a7> + 43d4ab: 0f b6 56 01 movzbl 0x1(%rsi),%edx + 43d4af: 84 d2 test %dl,%dl + 43d4b1: 0f 84 b9 00 00 00 je 43d570 <__strstr_sse2_unaligned+0xd0> + 43d4b7: 66 0f 6e c8 movd %eax,%xmm1 + 43d4bb: 66 0f 6e d2 movd %edx,%xmm2 + 43d4bf: 48 89 f8 mov %rdi,%rax + 43d4c2: 25 ff 0f 00 00 and $0xfff,%eax + 43d4c7: 66 0f 60 c9 punpcklbw %xmm1,%xmm1 + 43d4cb: 48 3d bf 0f 00 00 cmp $0xfbf,%rax + 43d4d1: 66 0f 60 d2 punpcklbw %xmm2,%xmm2 + 43d4d5: 66 0f 61 c9 punpcklwd %xmm1,%xmm1 + 43d4d9: 66 0f 61 d2 punpcklwd %xmm2,%xmm2 + 43d4dd: 66 0f 70 c9 00 pshufd $0x0,%xmm1,%xmm1 + 43d4e2: 66 0f 70 d2 00 pshufd $0x0,%xmm2,%xmm2 + 43d4e7: 0f 87 03 03 00 00 ja 43d7f0 <__strstr_sse2_unaligned+0x350> + 43d4ed: f3 0f 6f 1f movdqu (%rdi),%xmm3 + 43d4f1: 66 0f ef ed pxor %xmm5,%xmm5 + 43d4f5: f3 0f 6f 67 01 movdqu 0x1(%rdi),%xmm4 + 43d4fa: 66 0f 6f f3 movdqa %xmm3,%xmm6 + 43d4fe: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 + 43d502: 66 0f 74 e2 pcmpeqb %xmm2,%xmm4 + 43d506: f3 0f 6f 47 10 movdqu 0x10(%rdi),%xmm0 + 43d50b: 66 0f 74 f5 pcmpeqb %xmm5,%xmm6 + 43d50f: 66 0f da dc pminub %xmm4,%xmm3 + 43d513: 66 0f 6f e3 movdqa %xmm3,%xmm4 + 43d517: f3 0f 6f 5f 11 movdqu 0x11(%rdi),%xmm3 + 43d51c: 66 0f 74 e8 pcmpeqb %xmm0,%xmm5 + 43d520: 66 0f 74 da pcmpeqb %xmm2,%xmm3 + 43d524: 66 0f eb e6 por %xmm6,%xmm4 + 43d528: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 43d52c: 66 0f da c3 pminub %xmm3,%xmm0 + 43d530: 66 0f eb c5 por %xmm5,%xmm0 + 43d534: 66 44 0f d7 c4 pmovmskb %xmm4,%r8d + 43d539: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43d53d: 48 c1 e0 10 shl $0x10,%rax + 43d541: 49 09 c0 or %rax,%r8 + 43d544: 74 6a je 43d5b0 <__strstr_sse2_unaligned+0x110> + 43d546: 49 0f bc c0 bsf %r8,%rax + 43d54a: 48 01 f8 add %rdi,%rax + 43d54d: 80 38 00 cmpb $0x0,(%rax) + 43d550: 74 42 je 43d594 <__strstr_sse2_unaligned+0xf4> + 43d552: 0f b6 56 02 movzbl 0x2(%rsi),%edx + 43d556: 84 d2 test %dl,%dl + 43d558: 74 39 je 43d593 <__strstr_sse2_unaligned+0xf3> + 43d55a: 3a 50 02 cmp 0x2(%rax),%dl + 43d55d: 75 41 jne 43d5a0 <__strstr_sse2_unaligned+0x100> + 43d55f: 31 d2 xor %edx,%edx + 43d561: eb 27 jmp 43d58a <__strstr_sse2_unaligned+0xea> + 43d563: 0f 1f 00 nopl (%rax) + 43d566: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43d56d: 00 00 00 + 43d570: 0f b6 f0 movzbl %al,%esi + 43d573: e9 38 3b fe ff jmpq 4210b0 <__GI_strchr> + 43d578: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 43d57f: 00 + 43d580: 48 83 c2 01 add $0x1,%rdx + 43d584: 3a 4c 10 02 cmp 0x2(%rax,%rdx,1),%cl + 43d588: 75 16 jne 43d5a0 <__strstr_sse2_unaligned+0x100> + 43d58a: 0f b6 4c 16 03 movzbl 0x3(%rsi,%rdx,1),%ecx + 43d58f: 84 c9 test %cl,%cl + 43d591: 75 ed jne 43d580 <__strstr_sse2_unaligned+0xe0> + 43d593: c3 retq + 43d594: 31 c0 xor %eax,%eax + 43d596: c3 retq + 43d597: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 43d59e: 00 00 + 43d5a0: 49 8d 40 ff lea -0x1(%r8),%rax + 43d5a4: 49 21 c0 and %rax,%r8 + 43d5a7: 75 9d jne 43d546 <__strstr_sse2_unaligned+0xa6> + 43d5a9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43d5b0: f3 0f 6f 5f 20 movdqu 0x20(%rdi),%xmm3 + 43d5b5: 66 0f ef ed pxor %xmm5,%xmm5 + 43d5b9: f3 0f 6f 67 21 movdqu 0x21(%rdi),%xmm4 + 43d5be: 66 0f 6f f3 movdqa %xmm3,%xmm6 + 43d5c2: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 + 43d5c6: 66 0f 74 e2 pcmpeqb %xmm2,%xmm4 + 43d5ca: f3 0f 6f 47 30 movdqu 0x30(%rdi),%xmm0 + 43d5cf: 66 0f 74 f5 pcmpeqb %xmm5,%xmm6 + 43d5d3: 66 0f da dc pminub %xmm4,%xmm3 + 43d5d7: 66 0f 6f e3 movdqa %xmm3,%xmm4 + 43d5db: f3 0f 6f 5f 31 movdqu 0x31(%rdi),%xmm3 + 43d5e0: 66 0f 74 e8 pcmpeqb %xmm0,%xmm5 + 43d5e4: 66 0f 74 da pcmpeqb %xmm2,%xmm3 + 43d5e8: 66 0f eb e6 por %xmm6,%xmm4 + 43d5ec: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 43d5f0: 66 0f da c3 pminub %xmm3,%xmm0 + 43d5f4: 66 0f eb c5 por %xmm5,%xmm0 + 43d5f8: 66 0f d7 c4 pmovmskb %xmm4,%eax + 43d5fc: 48 c1 e0 20 shl $0x20,%rax + 43d600: 66 44 0f d7 c0 pmovmskb %xmm0,%r8d + 43d605: 49 c1 e0 30 shl $0x30,%r8 + 43d609: 49 09 c0 or %rax,%r8 + 43d60c: 74 4b je 43d659 <__strstr_sse2_unaligned+0x1b9> + 43d60e: 49 0f bc c0 bsf %r8,%rax + 43d612: 48 01 f8 add %rdi,%rax + 43d615: 80 38 00 cmpb $0x0,(%rax) + 43d618: 74 2a je 43d644 <__strstr_sse2_unaligned+0x1a4> + 43d61a: 0f b6 56 02 movzbl 0x2(%rsi),%edx + 43d61e: 84 d2 test %dl,%dl + 43d620: 74 21 je 43d643 <__strstr_sse2_unaligned+0x1a3> + 43d622: 3a 50 02 cmp 0x2(%rax),%dl + 43d625: 75 29 jne 43d650 <__strstr_sse2_unaligned+0x1b0> + 43d627: 31 d2 xor %edx,%edx + 43d629: eb 0f jmp 43d63a <__strstr_sse2_unaligned+0x19a> + 43d62b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43d630: 48 83 c2 01 add $0x1,%rdx + 43d634: 3a 4c 10 02 cmp 0x2(%rax,%rdx,1),%cl + 43d638: 75 16 jne 43d650 <__strstr_sse2_unaligned+0x1b0> + 43d63a: 0f b6 4c 16 03 movzbl 0x3(%rsi,%rdx,1),%ecx + 43d63f: 84 c9 test %cl,%cl + 43d641: 75 ed jne 43d630 <__strstr_sse2_unaligned+0x190> + 43d643: c3 retq + 43d644: 31 c0 xor %eax,%eax + 43d646: c3 retq + 43d647: 48 89 f8 mov %rdi,%rax + 43d64a: c3 retq + 43d64b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43d650: 49 8d 40 ff lea -0x1(%r8),%rax + 43d654: 49 21 c0 and %rax,%r8 + 43d657: 75 b5 jne 43d60e <__strstr_sse2_unaligned+0x16e> + 43d659: 49 c7 c3 00 fe ff ff mov $0xfffffffffffffe00,%r11 + 43d660: 49 89 f9 mov %rdi,%r9 + 43d663: 66 0f ef ff pxor %xmm7,%xmm7 + 43d667: 48 83 e7 c0 and $0xffffffffffffffc0,%rdi + 43d66b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43d670: 66 0f 6f 5f 40 movdqa 0x40(%rdi),%xmm3 + 43d675: f3 0f 6f 77 3f movdqu 0x3f(%rdi),%xmm6 + 43d67a: 66 0f 6f c3 movdqa %xmm3,%xmm0 + 43d67e: 66 0f ef da pxor %xmm2,%xmm3 + 43d682: 66 0f ef f1 pxor %xmm1,%xmm6 + 43d686: 66 44 0f 6f 57 50 movdqa 0x50(%rdi),%xmm10 + 43d68c: 66 0f eb f3 por %xmm3,%xmm6 + 43d690: 66 41 0f da c2 pminub %xmm10,%xmm0 + 43d695: f3 0f 6f 5f 4f movdqu 0x4f(%rdi),%xmm3 + 43d69a: 66 44 0f ef d2 pxor %xmm2,%xmm10 + 43d69f: 66 0f ef d9 pxor %xmm1,%xmm3 + 43d6a3: 66 44 0f 6f 4f 60 movdqa 0x60(%rdi),%xmm9 + 43d6a9: 66 41 0f eb da por %xmm10,%xmm3 + 43d6ae: 66 41 0f da c1 pminub %xmm9,%xmm0 + 43d6b3: 66 44 0f ef ca pxor %xmm2,%xmm9 + 43d6b8: 66 44 0f 6f 47 70 movdqa 0x70(%rdi),%xmm8 + 43d6be: 48 83 c7 40 add $0x40,%rdi + 43d6c2: 66 0f da de pminub %xmm6,%xmm3 + 43d6c6: f3 0f 6f 67 1f movdqu 0x1f(%rdi),%xmm4 + 43d6cb: 66 41 0f da c0 pminub %xmm8,%xmm0 + 43d6d0: 66 44 0f ef c2 pxor %xmm2,%xmm8 + 43d6d5: 66 0f ef e1 pxor %xmm1,%xmm4 + 43d6d9: 66 41 0f eb e1 por %xmm9,%xmm4 + 43d6de: 66 0f da dc pminub %xmm4,%xmm3 + 43d6e2: f3 0f 6f 6f 2f movdqu 0x2f(%rdi),%xmm5 + 43d6e7: 66 0f ef e9 pxor %xmm1,%xmm5 + 43d6eb: 66 41 0f eb e8 por %xmm8,%xmm5 + 43d6f0: 66 0f da dd pminub %xmm5,%xmm3 + 43d6f4: 66 0f da c3 pminub %xmm3,%xmm0 + 43d6f8: 66 0f 74 c7 pcmpeqb %xmm7,%xmm0 + 43d6fc: 66 0f d7 c0 pmovmskb %xmm0,%eax + 43d700: 85 c0 test %eax,%eax + 43d702: 0f 84 68 ff ff ff je 43d670 <__strstr_sse2_unaligned+0x1d0> + 43d708: 66 0f da 37 pminub (%rdi),%xmm6 + 43d70c: 66 0f da 67 20 pminub 0x20(%rdi),%xmm4 + 43d711: 66 0f da 6f 30 pminub 0x30(%rdi),%xmm5 + 43d716: 66 0f 74 f7 pcmpeqb %xmm7,%xmm6 + 43d71a: 66 0f 74 ef pcmpeqb %xmm7,%xmm5 + 43d71e: 66 0f d7 d6 pmovmskb %xmm6,%edx + 43d722: 66 44 0f 6f 47 10 movdqa 0x10(%rdi),%xmm8 + 43d728: 66 0f 74 e7 pcmpeqb %xmm7,%xmm4 + 43d72c: f3 0f 6f 47 0f movdqu 0xf(%rdi),%xmm0 + 43d731: 66 44 0f d7 c5 pmovmskb %xmm5,%r8d + 43d736: 66 41 0f 6f d8 movdqa %xmm8,%xmm3 + 43d73b: 66 0f d7 cc pmovmskb %xmm4,%ecx + 43d73f: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 + 43d743: 66 0f 74 da pcmpeqb %xmm2,%xmm3 + 43d747: 48 c1 e1 20 shl $0x20,%rcx + 43d74b: 66 44 0f 74 c7 pcmpeqb %xmm7,%xmm8 + 43d750: 49 c1 e0 30 shl $0x30,%r8 + 43d754: 66 0f da d8 pminub %xmm0,%xmm3 + 43d758: 48 09 ca or %rcx,%rdx + 43d75b: 66 44 0f eb c3 por %xmm3,%xmm8 + 43d760: 49 09 d0 or %rdx,%r8 + 43d763: 66 41 0f d7 c0 pmovmskb %xmm8,%eax + 43d768: 48 c1 e0 10 shl $0x10,%rax + 43d76c: 49 09 c0 or %rax,%r8 + 43d76f: 0f 84 fb fe ff ff je 43d670 <__strstr_sse2_unaligned+0x1d0> + 43d775: 49 0f bc c8 bsf %r8,%rcx + 43d779: 48 01 f9 add %rdi,%rcx + 43d77c: 80 39 00 cmpb $0x0,(%rcx) + 43d77f: 0f 84 ab 01 00 00 je 43d930 <__strstr_sse2_unaligned+0x490> + 43d785: 31 c0 xor %eax,%eax + 43d787: 0f b6 56 02 movzbl 0x2(%rsi),%edx + 43d78b: 84 d2 test %dl,%dl + 43d78d: 74 24 je 43d7b3 <__strstr_sse2_unaligned+0x313> + 43d78f: 3a 51 01 cmp 0x1(%rcx),%dl + 43d792: 75 2c jne 43d7c0 <__strstr_sse2_unaligned+0x320> + 43d794: eb 14 jmp 43d7aa <__strstr_sse2_unaligned+0x30a> + 43d796: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43d79d: 00 00 00 + 43d7a0: 48 83 c0 01 add $0x1,%rax + 43d7a4: 3a 54 01 01 cmp 0x1(%rcx,%rax,1),%dl + 43d7a8: 75 16 jne 43d7c0 <__strstr_sse2_unaligned+0x320> + 43d7aa: 0f b6 54 06 03 movzbl 0x3(%rsi,%rax,1),%edx + 43d7af: 84 d2 test %dl,%dl + 43d7b1: 75 ed jne 43d7a0 <__strstr_sse2_unaligned+0x300> + 43d7b3: 48 8d 41 ff lea -0x1(%rcx),%rax + 43d7b7: c3 retq + 43d7b8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 43d7bf: 00 + 43d7c0: 49 01 c3 add %rax,%r11 + 43d7c3: 48 89 f8 mov %rdi,%rax + 43d7c6: 4c 29 c8 sub %r9,%rax + 43d7c9: 4c 39 d8 cmp %r11,%rax + 43d7cc: 7c 12 jl 43d7e0 <__strstr_sse2_unaligned+0x340> + 43d7ce: 49 8d 40 ff lea -0x1(%r8),%rax + 43d7d2: 49 21 c0 and %rax,%r8 + 43d7d5: 75 9e jne 43d775 <__strstr_sse2_unaligned+0x2d5> + 43d7d7: e9 94 fe ff ff jmpq 43d670 <__strstr_sse2_unaligned+0x1d0> + 43d7dc: 0f 1f 40 00 nopl 0x0(%rax) + 43d7e0: 48 89 ff mov %rdi,%rdi + 43d7e3: e9 68 7d fe ff jmpq 425550 <__strstr_sse2> + 43d7e8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 43d7ef: 00 + 43d7f0: 48 89 f8 mov %rdi,%rax + 43d7f3: 66 0f ef c0 pxor %xmm0,%xmm0 + 43d7f7: 48 83 e0 c0 and $0xffffffffffffffc0,%rax + 43d7fb: 66 0f 6f 18 movdqa (%rax),%xmm3 + 43d7ff: f3 0f 6f 60 ff movdqu -0x1(%rax),%xmm4 + 43d804: 66 44 0f 6f c3 movdqa %xmm3,%xmm8 + 43d809: 66 0f 6f 68 10 movdqa 0x10(%rax),%xmm5 + 43d80e: 66 0f 74 e1 pcmpeqb %xmm1,%xmm4 + 43d812: 66 44 0f 74 c0 pcmpeqb %xmm0,%xmm8 + 43d817: 66 0f 74 da pcmpeqb %xmm2,%xmm3 + 43d81b: 66 0f 6f fd movdqa %xmm5,%xmm7 + 43d81f: 66 0f da dc pminub %xmm4,%xmm3 + 43d823: f3 0f 6f 60 0f movdqu 0xf(%rax),%xmm4 + 43d828: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 + 43d82c: 66 44 0f eb c3 por %xmm3,%xmm8 + 43d831: 66 0f 6f dd movdqa %xmm5,%xmm3 + 43d835: 66 0f 6f 68 20 movdqa 0x20(%rax),%xmm5 + 43d83a: 66 0f 74 e1 pcmpeqb %xmm1,%xmm4 + 43d83e: 66 0f 74 da pcmpeqb %xmm2,%xmm3 + 43d842: 66 0f 6f f5 movdqa %xmm5,%xmm6 + 43d846: 66 41 0f d7 c8 pmovmskb %xmm8,%ecx + 43d84b: 66 0f da dc pminub %xmm4,%xmm3 + 43d84f: f3 0f 6f 60 1f movdqu 0x1f(%rax),%xmm4 + 43d854: 66 0f eb fb por %xmm3,%xmm7 + 43d858: 66 0f 6f dd movdqa %xmm5,%xmm3 + 43d85c: 66 0f 74 f0 pcmpeqb %xmm0,%xmm6 + 43d860: 66 0f 6f 68 30 movdqa 0x30(%rax),%xmm5 + 43d865: 66 0f 74 e1 pcmpeqb %xmm1,%xmm4 + 43d869: 66 44 0f d7 c7 pmovmskb %xmm7,%r8d + 43d86e: 66 0f 74 da pcmpeqb %xmm2,%xmm3 + 43d872: 66 0f 74 c5 pcmpeqb %xmm5,%xmm0 + 43d876: 66 0f da dc pminub %xmm4,%xmm3 + 43d87a: f3 0f 6f 60 2f movdqu 0x2f(%rax),%xmm4 + 43d87f: 66 0f eb f3 por %xmm3,%xmm6 + 43d883: 66 0f 6f dd movdqa %xmm5,%xmm3 + 43d887: 49 c1 e0 10 shl $0x10,%r8 + 43d88b: 66 0f 74 e1 pcmpeqb %xmm1,%xmm4 + 43d88f: 66 0f 74 da pcmpeqb %xmm2,%xmm3 + 43d893: 66 44 0f d7 d6 pmovmskb %xmm6,%r10d + 43d898: 66 0f da dc pminub %xmm4,%xmm3 + 43d89c: 66 0f eb c3 por %xmm3,%xmm0 + 43d8a0: 49 c1 e2 20 shl $0x20,%r10 + 43d8a4: 4d 09 d0 or %r10,%r8 + 43d8a7: 49 09 c8 or %rcx,%r8 + 43d8aa: 89 f9 mov %edi,%ecx + 43d8ac: 66 0f d7 d0 pmovmskb %xmm0,%edx + 43d8b0: 29 c1 sub %eax,%ecx + 43d8b2: 48 c1 e2 30 shl $0x30,%rdx + 43d8b6: 49 09 d0 or %rdx,%r8 + 43d8b9: 49 d3 e8 shr %cl,%r8 + 43d8bc: 0f 84 97 fd ff ff je 43d659 <__strstr_sse2_unaligned+0x1b9> + 43d8c2: 49 0f bc c0 bsf %r8,%rax + 43d8c6: 48 01 f8 add %rdi,%rax + 43d8c9: 80 38 00 cmpb $0x0,(%rax) + 43d8cc: 74 62 je 43d930 <__strstr_sse2_unaligned+0x490> + 43d8ce: 48 39 c7 cmp %rax,%rdi + 43d8d1: 74 3d je 43d910 <__strstr_sse2_unaligned+0x470> + 43d8d3: 0f b6 56 02 movzbl 0x2(%rsi),%edx + 43d8d7: 84 d2 test %dl,%dl + 43d8d9: 74 28 je 43d903 <__strstr_sse2_unaligned+0x463> + 43d8db: 3a 50 01 cmp 0x1(%rax),%dl + 43d8de: 75 30 jne 43d910 <__strstr_sse2_unaligned+0x470> + 43d8e0: 31 d2 xor %edx,%edx + 43d8e2: eb 16 jmp 43d8fa <__strstr_sse2_unaligned+0x45a> + 43d8e4: 66 90 xchg %ax,%ax + 43d8e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43d8ed: 00 00 00 + 43d8f0: 48 83 c2 01 add $0x1,%rdx + 43d8f4: 3a 4c 10 01 cmp 0x1(%rax,%rdx,1),%cl + 43d8f8: 75 16 jne 43d910 <__strstr_sse2_unaligned+0x470> + 43d8fa: 0f b6 4c 16 03 movzbl 0x3(%rsi,%rdx,1),%ecx + 43d8ff: 84 c9 test %cl,%cl + 43d901: 75 ed jne 43d8f0 <__strstr_sse2_unaligned+0x450> + 43d903: 48 83 e8 01 sub $0x1,%rax + 43d907: c3 retq + 43d908: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 43d90f: 00 + 43d910: 49 8d 40 ff lea -0x1(%r8),%rax + 43d914: 49 21 c0 and %rax,%r8 + 43d917: 75 a9 jne 43d8c2 <__strstr_sse2_unaligned+0x422> + 43d919: e9 3b fd ff ff jmpq 43d659 <__strstr_sse2_unaligned+0x1b9> + 43d91e: 66 90 xchg %ax,%ax + 43d920: f3 c3 repz retq + 43d922: 0f 1f 40 00 nopl 0x0(%rax) + 43d926: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43d92d: 00 00 00 + 43d930: 31 c0 xor %eax,%eax + 43d932: c3 retq + 43d933: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43d93a: 00 00 00 + 43d93d: 0f 1f 00 nopl (%rax) + +000000000043d940 <__memset_avx2>: + 43d940: c5 f9 ef c0 vpxor %xmm0,%xmm0,%xmm0 + 43d944: c5 f9 6e ce vmovd %esi,%xmm1 + 43d948: 48 8d 34 17 lea (%rdi,%rdx,1),%rsi + 43d94c: 48 89 f8 mov %rdi,%rax + 43d94f: c4 e2 71 00 c0 vpshufb %xmm0,%xmm1,%xmm0 + 43d954: 48 83 fa 10 cmp $0x10,%rdx + 43d958: 0f 82 c2 00 00 00 jb 43da20 <__memset_avx2+0xe0> + 43d95e: 48 81 fa 00 01 00 00 cmp $0x100,%rdx + 43d965: 0f 83 f5 00 00 00 jae 43da60 <__memset_avx2+0x120> + 43d96b: 80 fa 80 cmp $0x80,%dl + 43d96e: 72 50 jb 43d9c0 <__memset_avx2+0x80> + 43d970: c5 fa 7f 07 vmovdqu %xmm0,(%rdi) + 43d974: c5 fa 7f 47 10 vmovdqu %xmm0,0x10(%rdi) + 43d979: c5 fa 7f 47 20 vmovdqu %xmm0,0x20(%rdi) + 43d97e: c5 fa 7f 47 30 vmovdqu %xmm0,0x30(%rdi) + 43d983: c5 fa 7f 47 40 vmovdqu %xmm0,0x40(%rdi) + 43d988: c5 fa 7f 47 50 vmovdqu %xmm0,0x50(%rdi) + 43d98d: c5 fa 7f 47 60 vmovdqu %xmm0,0x60(%rdi) + 43d992: c5 fa 7f 47 70 vmovdqu %xmm0,0x70(%rdi) + 43d997: c5 fa 7f 46 80 vmovdqu %xmm0,-0x80(%rsi) + 43d99c: c5 fa 7f 46 90 vmovdqu %xmm0,-0x70(%rsi) + 43d9a1: c5 fa 7f 46 a0 vmovdqu %xmm0,-0x60(%rsi) + 43d9a6: c5 fa 7f 46 b0 vmovdqu %xmm0,-0x50(%rsi) + 43d9ab: c5 fa 7f 46 c0 vmovdqu %xmm0,-0x40(%rsi) + 43d9b0: c5 fa 7f 46 d0 vmovdqu %xmm0,-0x30(%rsi) + 43d9b5: c5 fa 7f 46 e0 vmovdqu %xmm0,-0x20(%rsi) + 43d9ba: c5 fa 7f 46 f0 vmovdqu %xmm0,-0x10(%rsi) + 43d9bf: c3 retq + 43d9c0: 80 fa 40 cmp $0x40,%dl + 43d9c3: 72 2b jb 43d9f0 <__memset_avx2+0xb0> + 43d9c5: c5 fa 7f 07 vmovdqu %xmm0,(%rdi) + 43d9c9: c5 fa 7f 47 10 vmovdqu %xmm0,0x10(%rdi) + 43d9ce: c5 fa 7f 47 20 vmovdqu %xmm0,0x20(%rdi) + 43d9d3: c5 fa 7f 47 30 vmovdqu %xmm0,0x30(%rdi) + 43d9d8: c5 fa 7f 46 c0 vmovdqu %xmm0,-0x40(%rsi) + 43d9dd: c5 fa 7f 46 d0 vmovdqu %xmm0,-0x30(%rsi) + 43d9e2: c5 fa 7f 46 e0 vmovdqu %xmm0,-0x20(%rsi) + 43d9e7: c5 fa 7f 46 f0 vmovdqu %xmm0,-0x10(%rsi) + 43d9ec: c3 retq + 43d9ed: 0f 1f 00 nopl (%rax) + 43d9f0: 80 fa 20 cmp $0x20,%dl + 43d9f3: 72 1b jb 43da10 <__memset_avx2+0xd0> + 43d9f5: c5 fa 7f 07 vmovdqu %xmm0,(%rdi) + 43d9f9: c5 fa 7f 47 10 vmovdqu %xmm0,0x10(%rdi) + 43d9fe: c5 fa 7f 46 e0 vmovdqu %xmm0,-0x20(%rsi) + 43da03: c5 fa 7f 46 f0 vmovdqu %xmm0,-0x10(%rsi) + 43da08: c3 retq + 43da09: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43da10: c5 fa 7f 07 vmovdqu %xmm0,(%rdi) + 43da14: c5 fa 7f 46 f0 vmovdqu %xmm0,-0x10(%rsi) + 43da19: c3 retq + 43da1a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43da20: 80 fa 08 cmp $0x8,%dl + 43da23: 72 0b jb 43da30 <__memset_avx2+0xf0> + 43da25: c5 f9 d6 07 vmovq %xmm0,(%rdi) + 43da29: c5 f9 d6 46 f8 vmovq %xmm0,-0x8(%rsi) + 43da2e: c3 retq + 43da2f: 90 nop + 43da30: c5 f9 7e c1 vmovd %xmm0,%ecx + 43da34: 80 fa 04 cmp $0x4,%dl + 43da37: 72 07 jb 43da40 <__memset_avx2+0x100> + 43da39: 89 0f mov %ecx,(%rdi) + 43da3b: 89 4e fc mov %ecx,-0x4(%rsi) + 43da3e: c3 retq + 43da3f: 90 nop + 43da40: 80 fa 02 cmp $0x2,%dl + 43da43: 72 0b jb 43da50 <__memset_avx2+0x110> + 43da45: 66 89 0f mov %cx,(%rdi) + 43da48: 66 89 4e fe mov %cx,-0x2(%rsi) + 43da4c: c3 retq + 43da4d: 0f 1f 00 nopl (%rax) + 43da50: 80 fa 01 cmp $0x1,%dl + 43da53: 72 02 jb 43da57 <__memset_avx2+0x117> + 43da55: 88 0f mov %cl,(%rdi) + 43da57: c3 retq + 43da58: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 43da5f: 00 + 43da60: c4 e3 7d 38 c0 01 vinserti128 $0x1,%xmm0,%ymm0,%ymm0 + 43da66: 48 83 e7 e0 and $0xffffffffffffffe0,%rdi + 43da6a: 48 83 c7 20 add $0x20,%rdi + 43da6e: c5 fe 7f 00 vmovdqu %ymm0,(%rax) + 43da72: 48 29 f8 sub %rdi,%rax + 43da75: 48 8d 4c 10 80 lea -0x80(%rax,%rdx,1),%rcx + 43da7a: 48 81 f9 00 10 00 00 cmp $0x1000,%rcx + 43da81: 77 3d ja 43dac0 <__memset_avx2+0x180> + 43da83: c5 fd 7f 07 vmovdqa %ymm0,(%rdi) + 43da87: c5 fd 7f 47 20 vmovdqa %ymm0,0x20(%rdi) + 43da8c: c5 fd 7f 47 40 vmovdqa %ymm0,0x40(%rdi) + 43da91: c5 fd 7f 47 60 vmovdqa %ymm0,0x60(%rdi) + 43da96: 48 83 ef 80 sub $0xffffffffffffff80,%rdi + 43da9a: 83 c1 80 add $0xffffff80,%ecx + 43da9d: 72 e4 jb 43da83 <__memset_avx2+0x143> + 43da9f: 48 89 f0 mov %rsi,%rax + 43daa2: c5 fe 7f 46 80 vmovdqu %ymm0,-0x80(%rsi) + 43daa7: c5 fe 7f 46 a0 vmovdqu %ymm0,-0x60(%rsi) + 43daac: c5 fe 7f 46 c0 vmovdqu %ymm0,-0x40(%rsi) + 43dab1: c5 fe 7f 46 e0 vmovdqu %ymm0,-0x20(%rsi) + 43dab6: 48 29 d0 sub %rdx,%rax + 43dab9: c5 f8 77 vzeroupper + 43dabc: c3 retq + 43dabd: 0f 1f 00 nopl (%rax) + 43dac0: 48 83 e9 80 sub $0xffffffffffffff80,%rcx + 43dac4: c5 f9 7e c0 vmovd %xmm0,%eax + 43dac8: f3 aa rep stos %al,%es:(%rdi) + 43daca: 48 89 f0 mov %rsi,%rax + 43dacd: 48 29 d0 sub %rdx,%rax + 43dad0: c5 f8 77 vzeroupper + 43dad3: c3 retq + 43dad4: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43dadb: 00 00 00 + 43dade: 66 90 xchg %ax,%ax + +000000000043dae0 <__memset_avx512_no_vzeroupper>: + 43dae0: c5 f9 ef c0 vpxor %xmm0,%xmm0,%xmm0 + 43dae4: c5 f9 6e ce vmovd %esi,%xmm1 + 43dae8: 48 8d 34 17 lea (%rdi,%rdx,1),%rsi + 43daec: 48 89 f8 mov %rdi,%rax + 43daef: c4 e2 71 00 c0 vpshufb %xmm0,%xmm1,%xmm0 + 43daf4: 48 83 fa 10 cmp $0x10,%rdx + 43daf8: 0f 82 a1 00 00 00 jb 43db9f <__memset_avx512_no_vzeroupper+0xbf> + 43dafe: 48 81 fa 00 02 00 00 cmp $0x200,%rdx + 43db05: 62 f2 7d 48 18 d0 vbroadcastss %xmm0,%zmm2 + 43db0b: 0f 87 c1 00 00 00 ja 43dbd2 <__memset_avx512_no_vzeroupper+0xf2> + 43db11: 48 81 fa 00 01 00 00 cmp $0x100,%rdx + 43db18: 72 38 jb 43db52 <__memset_avx512_no_vzeroupper+0x72> + 43db1a: 62 f1 7c 48 11 17 vmovups %zmm2,(%rdi) + 43db20: 62 f1 7c 48 11 57 01 vmovups %zmm2,0x40(%rdi) + 43db27: 62 f1 7c 48 11 57 02 vmovups %zmm2,0x80(%rdi) + 43db2e: 62 f1 7c 48 11 57 03 vmovups %zmm2,0xc0(%rdi) + 43db35: 62 f1 7c 48 11 56 fc vmovups %zmm2,-0x100(%rsi) + 43db3c: 62 f1 7c 48 11 56 fd vmovups %zmm2,-0xc0(%rsi) + 43db43: 62 f1 7c 48 11 56 fe vmovups %zmm2,-0x80(%rsi) + 43db4a: 62 f1 7c 48 11 56 ff vmovups %zmm2,-0x40(%rsi) + 43db51: c3 retq + 43db52: 80 fa 80 cmp $0x80,%dl + 43db55: 72 1c jb 43db73 <__memset_avx512_no_vzeroupper+0x93> + 43db57: 62 f1 7c 48 11 17 vmovups %zmm2,(%rdi) + 43db5d: 62 f1 7c 48 11 57 01 vmovups %zmm2,0x40(%rdi) + 43db64: 62 f1 7c 48 11 56 fe vmovups %zmm2,-0x80(%rsi) + 43db6b: 62 f1 7c 48 11 56 ff vmovups %zmm2,-0x40(%rsi) + 43db72: c3 retq + 43db73: 80 fa 40 cmp $0x40,%dl + 43db76: 72 0e jb 43db86 <__memset_avx512_no_vzeroupper+0xa6> + 43db78: 62 f1 7c 48 11 17 vmovups %zmm2,(%rdi) + 43db7e: 62 f1 7c 48 11 56 ff vmovups %zmm2,-0x40(%rsi) + 43db85: c3 retq + 43db86: 80 fa 20 cmp $0x20,%dl + 43db89: 72 0a jb 43db95 <__memset_avx512_no_vzeroupper+0xb5> + 43db8b: c5 fe 7f 17 vmovdqu %ymm2,(%rdi) + 43db8f: c5 fe 7f 56 e0 vmovdqu %ymm2,-0x20(%rsi) + 43db94: c3 retq + 43db95: c5 fa 7f 07 vmovdqu %xmm0,(%rdi) + 43db99: c5 fa 7f 46 f0 vmovdqu %xmm0,-0x10(%rsi) + 43db9e: c3 retq + 43db9f: 80 fa 08 cmp $0x8,%dl + 43dba2: 72 0a jb 43dbae <__memset_avx512_no_vzeroupper+0xce> + 43dba4: c5 f9 d6 07 vmovq %xmm0,(%rdi) + 43dba8: c5 f9 d6 46 f8 vmovq %xmm0,-0x8(%rsi) + 43dbad: c3 retq + 43dbae: c5 f9 7e c1 vmovd %xmm0,%ecx + 43dbb2: 80 fa 04 cmp $0x4,%dl + 43dbb5: 72 06 jb 43dbbd <__memset_avx512_no_vzeroupper+0xdd> + 43dbb7: 89 0f mov %ecx,(%rdi) + 43dbb9: 89 4e fc mov %ecx,-0x4(%rsi) + 43dbbc: c3 retq + 43dbbd: 80 fa 02 cmp $0x2,%dl + 43dbc0: 72 08 jb 43dbca <__memset_avx512_no_vzeroupper+0xea> + 43dbc2: 66 89 0f mov %cx,(%rdi) + 43dbc5: 66 89 4e fe mov %cx,-0x2(%rsi) + 43dbc9: c3 retq + 43dbca: 80 fa 01 cmp $0x1,%dl + 43dbcd: 72 02 jb 43dbd1 <__memset_avx512_no_vzeroupper+0xf1> + 43dbcf: 88 0f mov %cl,(%rdi) + 43dbd1: c3 retq + 43dbd2: 48 8b 0d d7 d4 28 00 mov 0x28d4d7(%rip),%rcx # 6cb0b0 <__x86_shared_cache_size_half> + 43dbd9: 48 39 ca cmp %rcx,%rdx + 43dbdc: 0f 87 d1 00 00 00 ja 43dcb3 <__memset_avx512_no_vzeroupper+0x1d3> + 43dbe2: 48 81 fa 00 04 00 00 cmp $0x400,%rdx + 43dbe9: 77 70 ja 43dc5b <__memset_avx512_no_vzeroupper+0x17b> + 43dbeb: 62 f1 7c 48 11 17 vmovups %zmm2,(%rdi) + 43dbf1: 62 f1 7c 48 11 57 01 vmovups %zmm2,0x40(%rdi) + 43dbf8: 62 f1 7c 48 11 57 02 vmovups %zmm2,0x80(%rdi) + 43dbff: 62 f1 7c 48 11 57 03 vmovups %zmm2,0xc0(%rdi) + 43dc06: 62 f1 7c 48 11 57 04 vmovups %zmm2,0x100(%rdi) + 43dc0d: 62 f1 7c 48 11 57 05 vmovups %zmm2,0x140(%rdi) + 43dc14: 62 f1 7c 48 11 57 06 vmovups %zmm2,0x180(%rdi) + 43dc1b: 62 f1 7c 48 11 57 07 vmovups %zmm2,0x1c0(%rdi) + 43dc22: 62 f1 7c 48 11 56 f8 vmovups %zmm2,-0x200(%rsi) + 43dc29: 62 f1 7c 48 11 56 f9 vmovups %zmm2,-0x1c0(%rsi) + 43dc30: 62 f1 7c 48 11 56 fa vmovups %zmm2,-0x180(%rsi) + 43dc37: 62 f1 7c 48 11 56 fb vmovups %zmm2,-0x140(%rsi) + 43dc3e: 62 f1 7c 48 11 56 fc vmovups %zmm2,-0x100(%rsi) + 43dc45: 62 f1 7c 48 11 56 fd vmovups %zmm2,-0xc0(%rsi) + 43dc4c: 62 f1 7c 48 11 56 fe vmovups %zmm2,-0x80(%rsi) + 43dc53: 62 f1 7c 48 11 56 ff vmovups %zmm2,-0x40(%rsi) + 43dc5a: c3 retq + 43dc5b: 48 81 ee 00 01 00 00 sub $0x100,%rsi + 43dc62: 62 f1 7c 48 11 10 vmovups %zmm2,(%rax) + 43dc68: 48 83 e7 c0 and $0xffffffffffffffc0,%rdi + 43dc6c: 48 83 c7 40 add $0x40,%rdi + 43dc70: 62 f1 7c 48 29 17 vmovaps %zmm2,(%rdi) + 43dc76: 62 f1 7c 48 29 57 01 vmovaps %zmm2,0x40(%rdi) + 43dc7d: 62 f1 7c 48 29 57 02 vmovaps %zmm2,0x80(%rdi) + 43dc84: 62 f1 7c 48 29 57 03 vmovaps %zmm2,0xc0(%rdi) + 43dc8b: 48 81 c7 00 01 00 00 add $0x100,%rdi + 43dc92: 48 39 f7 cmp %rsi,%rdi + 43dc95: 72 d9 jb 43dc70 <__memset_avx512_no_vzeroupper+0x190> + 43dc97: 62 f1 7c 48 11 16 vmovups %zmm2,(%rsi) + 43dc9d: 62 f1 7c 48 11 56 01 vmovups %zmm2,0x40(%rsi) + 43dca4: 62 f1 7c 48 11 56 02 vmovups %zmm2,0x80(%rsi) + 43dcab: 62 f1 7c 48 11 56 03 vmovups %zmm2,0xc0(%rsi) + 43dcb2: c3 retq + 43dcb3: 48 83 e7 80 and $0xffffffffffffff80,%rdi + 43dcb7: 48 81 c7 80 00 00 00 add $0x80,%rdi + 43dcbe: 62 f1 7c 48 11 10 vmovups %zmm2,(%rax) + 43dcc4: 62 f1 7c 48 11 50 01 vmovups %zmm2,0x40(%rax) + 43dccb: 48 81 ee 00 02 00 00 sub $0x200,%rsi + 43dcd2: 62 f1 7d 48 e7 17 vmovntdq %zmm2,(%rdi) + 43dcd8: 62 f1 7d 48 e7 57 01 vmovntdq %zmm2,0x40(%rdi) + 43dcdf: 62 f1 7d 48 e7 57 02 vmovntdq %zmm2,0x80(%rdi) + 43dce6: 62 f1 7d 48 e7 57 03 vmovntdq %zmm2,0xc0(%rdi) + 43dced: 62 f1 7d 48 e7 57 04 vmovntdq %zmm2,0x100(%rdi) + 43dcf4: 62 f1 7d 48 e7 57 05 vmovntdq %zmm2,0x140(%rdi) + 43dcfb: 62 f1 7d 48 e7 57 06 vmovntdq %zmm2,0x180(%rdi) + 43dd02: 62 f1 7d 48 e7 57 07 vmovntdq %zmm2,0x1c0(%rdi) + 43dd09: 48 81 c7 00 02 00 00 add $0x200,%rdi + 43dd10: 48 39 f7 cmp %rsi,%rdi + 43dd13: 72 bd jb 43dcd2 <__memset_avx512_no_vzeroupper+0x1f2> + 43dd15: 0f ae f8 sfence + 43dd18: 62 f1 7c 48 11 16 vmovups %zmm2,(%rsi) + 43dd1e: 62 f1 7c 48 11 56 01 vmovups %zmm2,0x40(%rsi) + 43dd25: 62 f1 7c 48 11 56 02 vmovups %zmm2,0x80(%rsi) + 43dd2c: 62 f1 7c 48 11 56 03 vmovups %zmm2,0xc0(%rsi) + 43dd33: 62 f1 7c 48 11 56 04 vmovups %zmm2,0x100(%rsi) + 43dd3a: 62 f1 7c 48 11 56 05 vmovups %zmm2,0x140(%rsi) + 43dd41: 62 f1 7c 48 11 56 06 vmovups %zmm2,0x180(%rsi) + 43dd48: 62 f1 7c 48 11 56 07 vmovups %zmm2,0x1c0(%rsi) + 43dd4f: c3 retq + +000000000043dd50 : + 43dd50: 85 f6 test %esi,%esi + 43dd52: 0f 88 16 02 00 00 js 43df6e + 43dd58: 44 8d 87 47 ff ff ff lea -0xb9(%rdi),%r8d + 43dd5f: 41 55 push %r13 + 43dd61: 41 54 push %r12 + 43dd63: 55 push %rbp + 43dd64: 53 push %rbx + 43dd65: 48 89 d3 mov %rdx,%rbx + 43dd68: 44 89 c0 mov %r8d,%eax + 43dd6b: ba 56 55 55 55 mov $0x55555556,%edx + 43dd70: 41 c1 f8 1f sar $0x1f,%r8d + 43dd74: f7 ea imul %edx + 43dd76: 48 83 ec 08 sub $0x8,%rsp + 43dd7a: 44 29 c2 sub %r8d,%edx + 43dd7d: 85 f6 test %esi,%esi + 43dd7f: 44 8d 1c 52 lea (%rdx,%rdx,2),%r11d + 43dd83: 0f 84 b8 00 00 00 je 43de41 + 43dd89: 83 3d 28 e9 28 00 0f cmpl $0xf,0x28e928(%rip) # 6cc6b8 <_dl_x86_cpu_features+0x38> + 43dd90: 40 0f 94 c5 sete %bpl + 43dd94: 83 3d 21 e9 28 00 06 cmpl $0x6,0x28e921(%rip) # 6cc6bc <_dl_x86_cpu_features+0x3c> + 43dd9b: 0f 94 c0 sete %al + 43dd9e: 21 c5 and %eax,%ebp + 43dda0: 40 0f b6 c6 movzbl %sil,%eax + 43dda4: 83 f8 40 cmp $0x40,%eax + 43dda7: 0f 84 b3 00 00 00 je 43de60 + 43ddad: 3d ff 00 00 00 cmp $0xff,%eax + 43ddb2: 0f 84 bd 00 00 00 je 43de75 + 43ddb8: 83 f8 49 cmp $0x49,%eax + 43ddbb: 75 14 jne 43ddd1 + 43ddbd: 41 83 fb 09 cmp $0x9,%r11d + 43ddc1: 75 0e jne 43ddd1 + 43ddc3: 40 84 ed test %bpl,%bpl + 43ddc6: 74 09 je 43ddd1 + 43ddc8: 83 ef 03 sub $0x3,%edi + 43ddcb: 41 bb 06 00 00 00 mov $0x6,%r11d + 43ddd1: 41 89 f1 mov %esi,%r9d + 43ddd4: 31 d2 xor %edx,%edx + 43ddd6: 41 ba 44 00 00 00 mov $0x44,%r10d + 43dddc: 0f 1f 40 00 nopl 0x0(%rax) + 43dde0: 49 8d 04 12 lea (%r10,%rdx,1),%rax + 43dde4: 48 d1 e8 shr %rax + 43dde7: 44 3a 0c c5 60 3d 4a cmp 0x4a3d60(,%rax,8),%r9b + 43ddee: 00 + 43ddef: 4c 8d 04 c5 60 3d 4a lea 0x4a3d60(,%rax,8),%r8 + 43ddf6: 00 + 43ddf7: 74 29 je 43de22 + 43ddf9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43de00: 73 4e jae 43de50 + 43de02: 48 39 d0 cmp %rdx,%rax + 43de05: 49 89 c2 mov %rax,%r10 + 43de08: 76 2c jbe 43de36 + 43de0a: 48 01 d0 add %rdx,%rax + 43de0d: 48 d1 e8 shr %rax + 43de10: 44 3a 0c c5 60 3d 4a cmp 0x4a3d60(,%rax,8),%r9b + 43de17: 00 + 43de18: 4c 8d 04 c5 60 3d 4a lea 0x4a3d60(,%rax,8),%r8 + 43de1f: 00 + 43de20: 75 de jne 43de00 + 43de22: 41 0f b6 50 03 movzbl 0x3(%r8),%edx + 43de27: 41 39 d3 cmp %edx,%r11d + 43de2a: 89 d0 mov %edx,%eax + 43de2c: 0f 84 3f 01 00 00 je 43df71 + 43de32: 3c 06 cmp $0x6,%al + 43de34: 74 3a je 43de70 + 43de36: c1 ee 08 shr $0x8,%esi + 43de39: 85 f6 test %esi,%esi + 43de3b: 0f 85 5f ff ff ff jne 43dda0 + 43de41: 31 c0 xor %eax,%eax + 43de43: 48 83 c4 08 add $0x8,%rsp + 43de47: 5b pop %rbx + 43de48: 5d pop %rbp + 43de49: 41 5c pop %r12 + 43de4b: 41 5d pop %r13 + 43de4d: c3 retq + 43de4e: 66 90 xchg %ax,%ax + 43de50: 48 8d 50 01 lea 0x1(%rax),%rdx + 43de54: 4c 39 d2 cmp %r10,%rdx + 43de57: 72 87 jb 43dde0 + 43de59: eb db jmp 43de36 + 43de5b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43de60: 41 83 fb 09 cmp $0x9,%r11d + 43de64: c6 01 01 movb $0x1,(%rcx) + 43de67: 75 cd jne 43de36 + 43de69: eb d6 jmp 43de41 + 43de6b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43de70: c6 03 01 movb $0x1,(%rbx) + 43de73: eb c1 jmp 43de36 + 43de75: 31 c9 xor %ecx,%ecx + 43de77: b8 04 00 00 00 mov $0x4,%eax + 43de7c: 0f a2 cpuid + 43de7e: 89 c6 mov %eax,%esi + 43de80: 83 e6 1f and $0x1f,%esi + 43de83: 74 bc je 43de41 + 43de85: c1 e8 05 shr $0x5,%eax + 43de88: 83 e0 07 and $0x7,%eax + 43de8b: 83 f8 01 cmp $0x1,%eax + 43de8e: 0f 94 c2 sete %dl + 43de91: 41 83 fb 03 cmp $0x3,%r11d + 43de95: 41 0f 94 c1 sete %r9b + 43de99: 83 fe 01 cmp $0x1,%esi + 43de9c: 41 0f 94 c0 sete %r8b + 43dea0: 45 84 c8 test %r9b,%r8b + 43dea3: 74 08 je 43dead + 43dea5: 84 d2 test %dl,%dl + 43dea7: 0f 85 8e 00 00 00 jne 43df3b + 43dead: 45 85 db test %r11d,%r11d + 43deb0: 41 0f 94 c2 sete %r10b + 43deb4: 83 fe 02 cmp $0x2,%esi + 43deb7: 40 0f 94 c6 sete %sil + 43debb: 44 84 d6 test %r10b,%sil + 43debe: 74 04 je 43dec4 + 43dec0: 84 d2 test %dl,%dl + 43dec2: 75 77 jne 43df3b + 43dec4: 41 83 fb 06 cmp $0x6,%r11d + 43dec8: 41 b8 04 00 00 00 mov $0x4,%r8d + 43dece: 40 0f 94 c5 sete %bpl + 43ded2: 31 f6 xor %esi,%esi + 43ded4: 0f 1f 40 00 nopl 0x0(%rax) + 43ded8: 83 f8 02 cmp $0x2,%eax + 43dedb: 75 05 jne 43dee2 + 43dedd: 40 84 ed test %bpl,%bpl + 43dee0: 75 59 jne 43df3b + 43dee2: 83 f8 03 cmp $0x3,%eax + 43dee5: 75 06 jne 43deed + 43dee7: 41 83 fb 09 cmp $0x9,%r11d + 43deeb: 74 4e je 43df3b + 43deed: 83 f8 04 cmp $0x4,%eax + 43def0: 75 06 jne 43def8 + 43def2: 41 83 fb 0c cmp $0xc,%r11d + 43def6: 74 43 je 43df3b + 43def8: 83 c6 01 add $0x1,%esi + 43defb: 44 89 c0 mov %r8d,%eax + 43defe: 89 f1 mov %esi,%ecx + 43df00: 0f a2 cpuid + 43df02: 89 c2 mov %eax,%edx + 43df04: 83 e2 1f and $0x1f,%edx + 43df07: 0f 84 34 ff ff ff je 43de41 + 43df0d: c1 e8 05 shr $0x5,%eax + 43df10: 83 e0 07 and $0x7,%eax + 43df13: 83 f8 01 cmp $0x1,%eax + 43df16: 41 0f 94 c4 sete %r12b + 43df1a: 83 fa 01 cmp $0x1,%edx + 43df1d: 41 0f 94 c5 sete %r13b + 43df21: 45 84 cd test %r9b,%r13b + 43df24: 74 05 je 43df2b + 43df26: 45 84 e4 test %r12b,%r12b + 43df29: 75 10 jne 43df3b + 43df2b: 83 fa 02 cmp $0x2,%edx + 43df2e: 0f 94 c2 sete %dl + 43df31: 44 84 d2 test %r10b,%dl + 43df34: 74 a2 je 43ded8 + 43df36: 45 84 e4 test %r12b,%r12b + 43df39: 74 9d je 43ded8 + 43df3b: 8d 87 47 ff ff ff lea -0xb9(%rdi),%eax + 43df41: 44 29 d8 sub %r11d,%eax + 43df44: 74 59 je 43df9f + 43df46: 83 f8 01 cmp $0x1,%eax + 43df49: 0f 84 82 00 00 00 je 43dfd1 + 43df4f: 83 f8 02 cmp $0x2,%eax + 43df52: 0f 85 a9 00 00 00 jne 43e001 + 43df58: 89 d8 mov %ebx,%eax + 43df5a: 48 83 c4 08 add $0x8,%rsp + 43df5e: 25 ff 0f 00 00 and $0xfff,%eax + 43df63: 5b pop %rbx + 43df64: 48 83 c0 01 add $0x1,%rax + 43df68: 5d pop %rbp + 43df69: 41 5c pop %r12 + 43df6b: 41 5d pop %r13 + 43df6d: c3 retq + 43df6e: 31 c0 xor %eax,%eax + 43df70: c3 retq + 43df71: 8d 87 47 ff ff ff lea -0xb9(%rdi),%eax + 43df77: 44 29 d8 sub %r11d,%eax + 43df7a: 74 14 je 43df90 + 43df7c: 83 f8 01 cmp $0x1,%eax + 43df7f: 74 5d je 43dfde + 43df81: 83 f8 02 cmp $0x2,%eax + 43df84: 75 62 jne 43dfe8 + 43df86: 41 0f b6 40 02 movzbl 0x2(%r8),%eax + 43df8b: e9 b3 fe ff ff jmpq 43de43 + 43df90: 41 8b 40 04 mov 0x4(%r8),%eax + 43df94: 48 83 c4 08 add $0x8,%rsp + 43df98: 5b pop %rbx + 43df99: 5d pop %rbp + 43df9a: 41 5c pop %r12 + 43df9c: 41 5d pop %r13 + 43df9e: c3 retq + 43df9f: 89 d8 mov %ebx,%eax + 43dfa1: 83 c1 01 add $0x1,%ecx + 43dfa4: c1 e8 16 shr $0x16,%eax + 43dfa7: 8d 50 01 lea 0x1(%rax),%edx + 43dfaa: 89 d8 mov %ebx,%eax + 43dfac: 25 ff 0f 00 00 and $0xfff,%eax + 43dfb1: 83 c0 01 add $0x1,%eax + 43dfb4: 0f af c2 imul %edx,%eax + 43dfb7: 0f af c1 imul %ecx,%eax + 43dfba: 89 c2 mov %eax,%edx + 43dfbc: 89 d8 mov %ebx,%eax + 43dfbe: c1 e8 0c shr $0xc,%eax + 43dfc1: 25 ff 03 00 00 and $0x3ff,%eax + 43dfc6: 83 c0 01 add $0x1,%eax + 43dfc9: 0f af c2 imul %edx,%eax + 43dfcc: e9 72 fe ff ff jmpq 43de43 + 43dfd1: 89 d8 mov %ebx,%eax + 43dfd3: c1 e8 16 shr $0x16,%eax + 43dfd6: 83 c0 01 add $0x1,%eax + 43dfd9: e9 65 fe ff ff jmpq 43de43 + 43dfde: 41 0f b6 40 01 movzbl 0x1(%r8),%eax + 43dfe3: e9 5b fe ff ff jmpq 43de43 + 43dfe8: b9 90 3f 4a 00 mov $0x4a3f90,%ecx + 43dfed: ba f1 00 00 00 mov $0xf1,%edx + 43dff2: be b0 3b 4a 00 mov $0x4a3bb0,%esi + 43dff7: bf ce 3b 4a 00 mov $0x4a3bce,%edi + 43dffc: e8 3f 37 fc ff callq 401740 <__assert_fail> + 43e001: b9 90 3f 4a 00 mov $0x4a3f90,%ecx + 43e006: ba c1 00 00 00 mov $0xc1,%edx + 43e00b: be b0 3b 4a 00 mov $0x4a3bb0,%esi + 43e010: bf ce 3b 4a 00 mov $0x4a3bce,%edi + 43e015: e8 26 37 fc ff callq 401740 <__assert_fail> + 43e01a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + +000000000043e020 : + 43e020: 83 fe 01 cmp $0x1,%esi + 43e023: 0f 86 f7 00 00 00 jbe 43e120 + 43e029: 41 57 push %r15 + 43e02b: 41 56 push %r14 + 43e02d: 41 bf 01 00 00 00 mov $0x1,%r15d + 43e033: 41 55 push %r13 + 43e035: 41 54 push %r12 + 43e037: 41 bc 01 00 00 00 mov $0x1,%r12d + 43e03d: 55 push %rbp + 43e03e: 53 push %rbx + 43e03f: 89 fd mov %edi,%ebp + 43e041: 48 83 ec 18 sub $0x18,%rsp + 43e045: c6 44 24 0e 00 movb $0x0,0xe(%rsp) + 43e04a: c6 44 24 0f 00 movb $0x0,0xf(%rsp) + 43e04f: eb 78 jmp 43e0c9 + 43e051: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43e058: 48 8d 4c 24 0e lea 0xe(%rsp),%rcx + 43e05d: 48 8d 54 24 0f lea 0xf(%rsp),%rdx + 43e062: 89 ef mov %ebp,%edi + 43e064: e8 e7 fc ff ff callq 43dd50 + 43e069: 48 85 c0 test %rax,%rax + 43e06c: 0f 85 97 00 00 00 jne 43e109 + 43e072: 48 8d 4c 24 0e lea 0xe(%rsp),%rcx + 43e077: 48 8d 54 24 0f lea 0xf(%rsp),%rdx + 43e07c: 89 de mov %ebx,%esi + 43e07e: 89 ef mov %ebp,%edi + 43e080: e8 cb fc ff ff callq 43dd50 + 43e085: 48 85 c0 test %rax,%rax + 43e088: 75 7f jne 43e109 + 43e08a: 48 8d 4c 24 0e lea 0xe(%rsp),%rcx + 43e08f: 48 8d 54 24 0f lea 0xf(%rsp),%rdx + 43e094: 44 89 ee mov %r13d,%esi + 43e097: 89 ef mov %ebp,%edi + 43e099: e8 b2 fc ff ff callq 43dd50 + 43e09e: 48 85 c0 test %rax,%rax + 43e0a1: 75 66 jne 43e109 + 43e0a3: 48 8d 4c 24 0e lea 0xe(%rsp),%rcx + 43e0a8: 48 8d 54 24 0f lea 0xf(%rsp),%rdx + 43e0ad: 44 89 f6 mov %r14d,%esi + 43e0b0: 89 ef mov %ebp,%edi + 43e0b2: e8 99 fc ff ff callq 43dd50 + 43e0b7: 48 85 c0 test %rax,%rax + 43e0ba: 75 4d jne 43e109 + 43e0bc: 45 39 e7 cmp %r12d,%r15d + 43e0bf: 41 8d 44 24 01 lea 0x1(%r12),%eax + 43e0c4: 76 2a jbe 43e0f0 + 43e0c6: 41 89 c4 mov %eax,%r12d + 43e0c9: b8 02 00 00 00 mov $0x2,%eax + 43e0ce: 0f a2 cpuid + 43e0d0: 41 83 fc 01 cmp $0x1,%r12d + 43e0d4: 41 89 d6 mov %edx,%r14d + 43e0d7: 41 89 cd mov %ecx,%r13d + 43e0da: 89 c6 mov %eax,%esi + 43e0dc: 0f 85 76 ff ff ff jne 43e058 + 43e0e2: 44 0f b6 f8 movzbl %al,%r15d + 43e0e6: 40 80 e6 00 and $0x0,%sil + 43e0ea: e9 69 ff ff ff jmpq 43e058 + 43e0ef: 90 nop + 43e0f0: 81 ed bf 00 00 00 sub $0xbf,%ebp + 43e0f6: 83 fd 05 cmp $0x5,%ebp + 43e0f9: 77 2d ja 43e128 + 43e0fb: 80 7c 24 0e 00 cmpb $0x0,0xe(%rsp) + 43e100: 74 26 je 43e128 + 43e102: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax + 43e109: 48 83 c4 18 add $0x18,%rsp + 43e10d: 5b pop %rbx + 43e10e: 5d pop %rbp + 43e10f: 41 5c pop %r12 + 43e111: 41 5d pop %r13 + 43e113: 41 5e pop %r14 + 43e115: 41 5f pop %r15 + 43e117: c3 retq + 43e118: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 43e11f: 00 + 43e120: 31 c0 xor %eax,%eax + 43e122: c3 retq + 43e123: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43e128: 48 83 c4 18 add $0x18,%rsp + 43e12c: 31 c0 xor %eax,%eax + 43e12e: 5b pop %rbx + 43e12f: 5d pop %rbp + 43e130: 41 5c pop %r12 + 43e132: 41 5d pop %r13 + 43e134: 41 5e pop %r14 + 43e136: 41 5f pop %r15 + 43e138: c3 retq + 43e139: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + +000000000043e140 : + 43e140: 53 push %rbx + 43e141: b8 00 00 00 80 mov $0x80000000,%eax + 43e146: 0f a2 cpuid + 43e148: 81 ff c4 00 00 00 cmp $0xc4,%edi + 43e14e: 7f 40 jg 43e190 + 43e150: 31 d2 xor %edx,%edx + 43e152: 81 ff be 00 00 00 cmp $0xbe,%edi + 43e158: 0f 9f c2 setg %dl + 43e15b: 81 ea fb ff ff 7f sub $0x7ffffffb,%edx + 43e161: 39 c2 cmp %eax,%edx + 43e163: 77 2b ja 43e190 + 43e165: 89 d0 mov %edx,%eax + 43e167: 0f a2 cpuid + 43e169: 81 ff bb 00 00 00 cmp $0xbb,%edi + 43e16f: 7e 27 jle 43e198 + 43e171: 81 ef bc 00 00 00 sub $0xbc,%edi + 43e177: 83 ff 08 cmp $0x8,%edi + 43e17a: 0f 87 30 01 00 00 ja 43e2b0 + 43e180: ff 24 fd 00 3c 4a 00 jmpq *0x4a3c00(,%rdi,8) + 43e187: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 43e18e: 00 00 + 43e190: 31 c0 xor %eax,%eax + 43e192: 5b pop %rbx + 43e193: c3 retq + 43e194: 0f 1f 40 00 nopl 0x0(%rax) + 43e198: 83 c7 03 add $0x3,%edi + 43e19b: 89 d1 mov %edx,%ecx + 43e19d: eb d2 jmp 43e171 + 43e19f: 90 nop + 43e1a0: 31 c0 xor %eax,%eax + 43e1a2: f6 c5 f0 test $0xf0,%ch + 43e1a5: 74 eb je 43e192 + 43e1a7: 0f b6 c1 movzbl %cl,%eax + 43e1aa: 5b pop %rbx + 43e1ab: c3 retq + 43e1ac: 0f 1f 40 00 nopl 0x0(%rax) + 43e1b0: 31 c0 xor %eax,%eax + 43e1b2: f6 c5 f0 test $0xf0,%ch + 43e1b5: 74 db je 43e192 + 43e1b7: 89 c8 mov %ecx,%eax + 43e1b9: c1 e8 06 shr $0x6,%eax + 43e1bc: 25 00 fc ff 03 and $0x3fffc00,%eax + 43e1c1: 5b pop %rbx + 43e1c2: c3 retq + 43e1c3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43e1c8: 31 c0 xor %eax,%eax + 43e1ca: f6 c6 f0 test $0xf0,%dh + 43e1cd: 74 c3 je 43e192 + 43e1cf: 0f b6 c2 movzbl %dl,%eax + 43e1d2: 5b pop %rbx + 43e1d3: c3 retq + 43e1d4: 0f 1f 40 00 nopl 0x0(%rax) + 43e1d8: 89 c8 mov %ecx,%eax + 43e1da: c1 e8 0e shr $0xe,%eax + 43e1dd: 25 00 fc 03 00 and $0x3fc00,%eax + 43e1e2: 5b pop %rbx + 43e1e3: c3 retq + 43e1e4: 0f 1f 40 00 nopl 0x0(%rax) + 43e1e8: c1 e9 10 shr $0x10,%ecx + 43e1eb: 0f b6 c1 movzbl %cl,%eax + 43e1ee: 3d ff 00 00 00 cmp $0xff,%eax + 43e1f3: 75 9d jne 43e192 + 43e1f5: 8d 04 8d 00 00 00 00 lea 0x0(,%rcx,4),%eax + 43e1fc: 5b pop %rbx + 43e1fd: 25 00 fc 03 00 and $0x3fc00,%eax + 43e202: c3 retq + 43e203: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43e208: 89 ca mov %ecx,%edx + 43e20a: c1 ea 0c shr $0xc,%edx + 43e20d: 83 e2 0f and $0xf,%edx + 43e210: ff 24 d5 48 3c 4a 00 jmpq *0x4a3c48(,%rdx,8) + 43e217: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 43e21e: 00 00 + 43e220: 31 c0 xor %eax,%eax + 43e222: f6 c6 f0 test $0xf0,%dh + 43e225: 0f 84 67 ff ff ff je 43e192 + 43e22b: 48 8d 04 12 lea (%rdx,%rdx,1),%rax + 43e22f: 5b pop %rbx + 43e230: 25 00 00 f8 7f and $0x7ff80000,%eax + 43e235: c3 retq + 43e236: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43e23d: 00 00 00 + 43e240: 89 d0 mov %edx,%eax + 43e242: c1 e8 0c shr $0xc,%eax + 43e245: 83 e0 0f and $0xf,%eax + 43e248: ff 24 c5 c8 3c 4a 00 jmpq *0x4a3cc8(,%rax,8) + 43e24f: b8 08 00 00 00 mov $0x8,%eax + 43e254: 5b pop %rbx + 43e255: c3 retq + 43e256: b8 80 00 00 00 mov $0x80,%eax + 43e25b: 5b pop %rbx + 43e25c: c3 retq + 43e25d: b8 60 00 00 00 mov $0x60,%eax + 43e262: 5b pop %rbx + 43e263: c3 retq + 43e264: b8 40 00 00 00 mov $0x40,%eax + 43e269: 5b pop %rbx + 43e26a: c3 retq + 43e26b: b8 30 00 00 00 mov $0x30,%eax + 43e270: 5b pop %rbx + 43e271: c3 retq + 43e272: b8 20 00 00 00 mov $0x20,%eax + 43e277: 5b pop %rbx + 43e278: c3 retq + 43e279: b8 10 00 00 00 mov $0x10,%eax + 43e27e: 5b pop %rbx + 43e27f: c3 retq + 43e280: 89 ca mov %ecx,%edx + 43e282: 0f b6 c9 movzbl %cl,%ecx + 43e285: c1 ea 06 shr $0x6,%edx + 43e288: 89 d0 mov %edx,%eax + 43e28a: 31 d2 xor %edx,%edx + 43e28c: 25 00 fc ff 03 and $0x3fffc00,%eax + 43e291: f7 f1 div %ecx + 43e293: 5b pop %rbx + 43e294: 89 c0 mov %eax,%eax + 43e296: c3 retq + 43e297: 48 89 d0 mov %rdx,%rax + 43e29a: 5b pop %rbx + 43e29b: c3 retq + 43e29c: 89 d0 mov %edx,%eax + 43e29e: 0f b6 ca movzbl %dl,%ecx + 43e2a1: 31 d2 xor %edx,%edx + 43e2a3: 25 00 00 fc 3f and $0x3ffc0000,%eax + 43e2a8: 01 c0 add %eax,%eax + 43e2aa: f7 f1 div %ecx + 43e2ac: 5b pop %rbx + 43e2ad: 89 c0 mov %eax,%eax + 43e2af: c3 retq + 43e2b0: b9 80 3f 4a 00 mov $0x4a3f80,%ecx + 43e2b5: ba b0 01 00 00 mov $0x1b0,%edx + 43e2ba: be b0 3b 4a 00 mov $0x4a3bb0,%esi + 43e2bf: bf da 3b 4a 00 mov $0x4a3bda,%edi + 43e2c4: e8 77 34 fc ff callq 401740 <__assert_fail> + 43e2c9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + +000000000043e2d0 <__cache_sysconf>: + 43e2d0: 8b 05 aa e3 28 00 mov 0x28e3aa(%rip),%eax # 6cc680 <_dl_x86_cpu_features> + 43e2d6: 83 f8 01 cmp $0x1,%eax + 43e2d9: 74 15 je 43e2f0 <__cache_sysconf+0x20> + 43e2db: 83 f8 02 cmp $0x2,%eax + 43e2de: 74 08 je 43e2e8 <__cache_sysconf+0x18> + 43e2e0: 31 c0 xor %eax,%eax + 43e2e2: c3 retq + 43e2e3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43e2e8: e9 53 fe ff ff jmpq 43e140 + 43e2ed: 0f 1f 00 nopl (%rax) + 43e2f0: 8b 35 8e e3 28 00 mov 0x28e38e(%rip),%esi # 6cc684 <_dl_x86_cpu_features+0x4> + 43e2f6: e9 25 fd ff ff jmpq 43e020 + 43e2fb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + +000000000043e300 <__strcasecmp_l_nonascii>: + 43e300: 48 39 f7 cmp %rsi,%rdi + 43e303: 74 33 je 43e338 <__strcasecmp_l_nonascii+0x38> + 43e305: 48 8b 52 70 mov 0x70(%rdx),%rdx + 43e309: eb 0e jmp 43e319 <__strcasecmp_l_nonascii+0x19> + 43e30b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43e310: 48 83 c7 01 add $0x1,%rdi + 43e314: 45 84 c0 test %r8b,%r8b + 43e317: 74 1f je 43e338 <__strcasecmp_l_nonascii+0x38> + 43e319: 48 83 c6 01 add $0x1,%rsi + 43e31d: 0f b6 07 movzbl (%rdi),%eax + 43e320: 0f b6 4e ff movzbl -0x1(%rsi),%ecx + 43e324: 49 89 c0 mov %rax,%r8 + 43e327: 8b 04 82 mov (%rdx,%rax,4),%eax + 43e32a: 2b 04 8a sub (%rdx,%rcx,4),%eax + 43e32d: 74 e1 je 43e310 <__strcasecmp_l_nonascii+0x10> + 43e32f: f3 c3 repz retq + 43e331: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43e338: 31 c0 xor %eax,%eax + 43e33a: c3 retq + 43e33b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + +000000000043e340 <__wmempcpy>: + 43e340: 48 c1 e2 02 shl $0x2,%rdx + 43e344: e9 77 82 fe ff jmpq 4265c0 <__mempcpy> + 43e349: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + +000000000043e350 <_nl_cleanup_ctype>: + 43e350: 53 push %rbx + 43e351: 48 8b 5f 28 mov 0x28(%rdi),%rbx + 43e355: 48 85 db test %rbx,%rbx + 43e358: 74 36 je 43e390 <_nl_cleanup_ctype+0x40> + 43e35a: 48 c7 47 28 00 00 00 movq $0x0,0x28(%rdi) + 43e361: 00 + 43e362: 48 c7 47 20 00 00 00 movq $0x0,0x20(%rdi) + 43e369: 00 + 43e36a: 48 8b 73 18 mov 0x18(%rbx),%rsi + 43e36e: 48 8b 7b 10 mov 0x10(%rbx),%rdi + 43e372: e8 79 75 00 00 callq 4458f0 <__gconv_close_transform> + 43e377: 48 8b 3b mov (%rbx),%rdi + 43e37a: 48 8b 73 08 mov 0x8(%rbx),%rsi + 43e37e: e8 6d 75 00 00 callq 4458f0 <__gconv_close_transform> + 43e383: 48 89 df mov %rbx,%rdi + 43e386: 5b pop %rbx + 43e387: e9 24 fa fd ff jmpq 41ddb0 <__cfree> + 43e38c: 0f 1f 40 00 nopl 0x0(%rax) + 43e390: 5b pop %rbx + 43e391: c3 retq + 43e392: 0f 1f 40 00 nopl 0x0(%rax) + 43e396: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43e39d: 00 00 00 + +000000000043e3a0 <__wcsmbs_getfct>: + 43e3a0: 53 push %rbx + 43e3a1: 48 89 d3 mov %rdx,%rbx + 43e3a4: 45 31 c0 xor %r8d,%r8d + 43e3a7: 48 83 ec 10 sub $0x10,%rsp + 43e3ab: 48 8d 54 24 08 lea 0x8(%rsp),%rdx + 43e3b0: 48 89 e1 mov %rsp,%rcx + 43e3b3: e8 58 72 00 00 callq 445610 <__gconv_find_transform> + 43e3b8: 85 c0 test %eax,%eax + 43e3ba: 75 34 jne 43e3f0 <__wcsmbs_getfct+0x50> + 43e3bc: 48 8b 34 24 mov (%rsp),%rsi + 43e3c0: 48 83 fe 01 cmp $0x1,%rsi + 43e3c4: 76 1a jbe 43e3e0 <__wcsmbs_getfct+0x40> + 43e3c6: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi + 43e3cb: e8 20 75 00 00 callq 4458f0 <__gconv_close_transform> + 43e3d0: 48 83 c4 10 add $0x10,%rsp + 43e3d4: 31 c0 xor %eax,%eax + 43e3d6: 5b pop %rbx + 43e3d7: c3 retq + 43e3d8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 43e3df: 00 + 43e3e0: 48 89 33 mov %rsi,(%rbx) + 43e3e3: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 43e3e8: 48 83 c4 10 add $0x10,%rsp + 43e3ec: 5b pop %rbx + 43e3ed: c3 retq + 43e3ee: 66 90 xchg %ax,%ax + 43e3f0: 48 83 c4 10 add $0x10,%rsp + 43e3f4: 31 c0 xor %eax,%eax + 43e3f6: 5b pop %rbx + 43e3f7: c3 retq + 43e3f8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 43e3ff: 00 + +000000000043e400 <__wcsmbs_load_conv>: + 43e400: 55 push %rbp + 43e401: b8 00 00 00 00 mov $0x0,%eax + 43e406: 48 89 e5 mov %rsp,%rbp + 43e409: 41 55 push %r13 + 43e40b: 41 54 push %r12 + 43e40d: 53 push %rbx + 43e40e: 48 89 fb mov %rdi,%rbx + 43e411: 48 83 ec 18 sub $0x18,%rsp + 43e415: 48 85 c0 test %rax,%rax + 43e418: 74 07 je 43e421 <__wcsmbs_load_conv+0x21> + 43e41a: bf 20 c7 6c 00 mov $0x6cc720,%edi + 43e41f: ff d0 callq *%rax + 43e421: 48 83 7b 28 00 cmpq $0x0,0x28(%rbx) + 43e426: 74 20 je 43e448 <__wcsmbs_load_conv+0x48> + 43e428: b8 00 00 00 00 mov $0x0,%eax + 43e42d: 48 85 c0 test %rax,%rax + 43e430: 74 07 je 43e439 <__wcsmbs_load_conv+0x39> + 43e432: bf 20 c7 6c 00 mov $0x6cc720,%edi + 43e437: ff d0 callq *%rax + 43e439: 48 8d 65 e8 lea -0x18(%rbp),%rsp + 43e43d: 5b pop %rbx + 43e43e: 41 5c pop %r12 + 43e440: 41 5d pop %r13 + 43e442: 5d pop %rbp + 43e443: c3 retq + 43e444: 0f 1f 40 00 nopl 0x0(%rax) + 43e448: be 20 00 00 00 mov $0x20,%esi + 43e44d: bf 01 00 00 00 mov $0x1,%edi + 43e452: e8 69 01 fe ff callq 41e5c0 <__calloc> + 43e457: 48 85 c0 test %rax,%rax + 43e45a: 49 89 c4 mov %rax,%r12 + 43e45d: 0f 84 5d 01 00 00 je 43e5c0 <__wcsmbs_load_conv+0x1c0> + 43e463: 8b 73 34 mov 0x34(%rbx),%esi + 43e466: 4c 8b 83 b0 00 00 00 mov 0xb0(%rbx),%r8 + 43e46d: 83 fe 01 cmp $0x1,%esi + 43e470: 4c 89 c0 mov %r8,%rax + 43e473: 48 19 ff sbb %rdi,%rdi + 43e476: 48 83 e7 f8 and $0xfffffffffffffff8,%rdi + 43e47a: 48 83 c7 0b add $0xb,%rdi + 43e47e: 83 fe 01 cmp $0x1,%esi + 43e481: 48 19 d2 sbb %rdx,%rdx + 43e484: 45 31 c9 xor %r9d,%r9d + 43e487: 48 f7 d2 not %rdx + 43e48a: 83 e2 08 and $0x8,%edx + 43e48d: eb 11 jmp 43e4a0 <__wcsmbs_load_conv+0xa0> + 43e48f: 90 nop + 43e490: 48 83 c0 01 add $0x1,%rax + 43e494: 80 f9 2f cmp $0x2f,%cl + 43e497: 0f 94 c1 sete %cl + 43e49a: 0f b6 c9 movzbl %cl,%ecx + 43e49d: 49 01 c9 add %rcx,%r9 + 43e4a0: 0f b6 08 movzbl (%rax),%ecx + 43e4a3: 84 c9 test %cl,%cl + 43e4a5: 75 e9 jne 43e490 <__wcsmbs_load_conv+0x90> + 43e4a7: 4c 29 c0 sub %r8,%rax + 43e4aa: 49 0f be 08 movsbq (%r8),%rcx + 43e4ae: 48 8d 44 07 1e lea 0x1e(%rdi,%rax,1),%rax + 43e4b3: 48 83 e0 f0 and $0xfffffffffffffff0,%rax + 43e4b7: 48 29 c4 sub %rax,%rsp + 43e4ba: 4c 8d 6c 24 0f lea 0xf(%rsp),%r13 + 43e4bf: 49 83 e5 f0 and $0xfffffffffffffff0,%r13 + 43e4c3: 84 c9 test %cl,%cl + 43e4c5: 0f 84 6c 01 00 00 je 43e637 <__wcsmbs_load_conv+0x237> + 43e4cb: 48 8b 3d 26 42 07 00 mov 0x74226(%rip),%rdi # 4b26f8 <_nl_C_locobj+0x78> + 43e4d2: 4c 89 e8 mov %r13,%rax + 43e4d5: 0f 1f 00 nopl (%rax) + 43e4d8: 8b 0c 8f mov (%rdi,%rcx,4),%ecx + 43e4db: 48 83 c0 01 add $0x1,%rax + 43e4df: 49 83 c0 01 add $0x1,%r8 + 43e4e3: 88 48 ff mov %cl,-0x1(%rax) + 43e4e6: 49 0f be 08 movsbq (%r8),%rcx + 43e4ea: 84 c9 test %cl,%cl + 43e4ec: 75 ea jne 43e4d8 <__wcsmbs_load_conv+0xd8> + 43e4ee: 49 83 f9 01 cmp $0x1,%r9 + 43e4f2: 0f 86 d8 00 00 00 jbe 43e5d0 <__wcsmbs_load_conv+0x1d0> + 43e4f8: 48 8d 4d d0 lea -0x30(%rbp),%rcx + 43e4fc: 48 8d 55 d8 lea -0x28(%rbp),%rdx + 43e500: 45 31 c0 xor %r8d,%r8d + 43e503: c6 00 00 movb $0x0,(%rax) + 43e506: 4c 89 ee mov %r13,%rsi + 43e509: bf 6d 52 4a 00 mov $0x4a526d,%edi + 43e50e: e8 fd 70 00 00 callq 445610 <__gconv_find_transform> + 43e513: 85 c0 test %eax,%eax + 43e515: 0f 85 06 01 00 00 jne 43e621 <__wcsmbs_load_conv+0x221> + 43e51b: 48 8b 75 d0 mov -0x30(%rbp),%rsi + 43e51f: 48 83 fe 01 cmp $0x1,%rsi + 43e523: 76 2b jbe 43e550 <__wcsmbs_load_conv+0x150> + 43e525: 48 8b 7d d8 mov -0x28(%rbp),%rdi + 43e529: e8 c2 73 00 00 callq 4458f0 <__gconv_close_transform> + 43e52e: 49 83 7c 24 10 00 cmpq $0x0,0x10(%r12) + 43e534: 49 c7 04 24 00 00 00 movq $0x0,(%r12) + 43e53b: 00 + 43e53c: 74 7a je 43e5b8 <__wcsmbs_load_conv+0x1b8> + 43e53e: 4c 89 63 28 mov %r12,0x28(%rbx) + 43e542: 48 c7 43 20 50 e3 43 movq $0x43e350,0x20(%rbx) + 43e549: 00 + 43e54a: e9 d9 fe ff ff jmpq 43e428 <__wcsmbs_load_conv+0x28> + 43e54f: 90 nop + 43e550: 48 8b 45 d8 mov -0x28(%rbp),%rax + 43e554: 49 89 74 24 08 mov %rsi,0x8(%r12) + 43e559: 48 85 c0 test %rax,%rax + 43e55c: 49 89 04 24 mov %rax,(%r12) + 43e560: 0f 84 c3 00 00 00 je 43e629 <__wcsmbs_load_conv+0x229> + 43e566: 48 8d 4d d0 lea -0x30(%rbp),%rcx + 43e56a: 48 8d 55 d8 lea -0x28(%rbp),%rdx + 43e56e: 45 31 c0 xor %r8d,%r8d + 43e571: be 6d 52 4a 00 mov $0x4a526d,%esi + 43e576: 4c 89 ef mov %r13,%rdi + 43e579: e8 92 70 00 00 callq 445610 <__gconv_find_transform> + 43e57e: 85 c0 test %eax,%eax + 43e580: 0f 85 b9 00 00 00 jne 43e63f <__wcsmbs_load_conv+0x23f> + 43e586: 48 8b 75 d0 mov -0x30(%rbp),%rsi + 43e58a: 48 83 fe 01 cmp $0x1,%rsi + 43e58e: 76 58 jbe 43e5e8 <__wcsmbs_load_conv+0x1e8> + 43e590: 48 8b 7d d8 mov -0x28(%rbp),%rdi + 43e594: e8 57 73 00 00 callq 4458f0 <__gconv_close_transform> + 43e599: 31 c0 xor %eax,%eax + 43e59b: 48 85 c0 test %rax,%rax + 43e59e: 49 89 44 24 10 mov %rax,0x10(%r12) + 43e5a3: 75 99 jne 43e53e <__wcsmbs_load_conv+0x13e> + 43e5a5: 49 8b 3c 24 mov (%r12),%rdi + 43e5a9: 48 85 ff test %rdi,%rdi + 43e5ac: 74 0a je 43e5b8 <__wcsmbs_load_conv+0x1b8> + 43e5ae: 49 8b 74 24 08 mov 0x8(%r12),%rsi + 43e5b3: e8 38 73 00 00 callq 4458f0 <__gconv_close_transform> + 43e5b8: 4c 89 e7 mov %r12,%rdi + 43e5bb: e8 f0 f7 fd ff callq 41ddb0 <__cfree> + 43e5c0: 48 c7 43 28 c0 3f 4a movq $0x4a3fc0,0x28(%rbx) + 43e5c7: 00 + 43e5c8: e9 5b fe ff ff jmpq 43e428 <__wcsmbs_load_conv+0x28> + 43e5cd: 0f 1f 00 nopl (%rax) + 43e5d0: 4d 85 c9 test %r9,%r9 + 43e5d3: c6 00 2f movb $0x2f,(%rax) + 43e5d6: 74 1b je 43e5f3 <__wcsmbs_load_conv+0x1f3> + 43e5d8: 48 83 c0 01 add $0x1,%rax + 43e5dc: e9 17 ff ff ff jmpq 43e4f8 <__wcsmbs_load_conv+0xf8> + 43e5e1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43e5e8: 49 89 74 24 18 mov %rsi,0x18(%r12) + 43e5ed: 48 8b 45 d8 mov -0x28(%rbp),%rax + 43e5f1: eb a8 jmp 43e59b <__wcsmbs_load_conv+0x19b> + 43e5f3: c6 40 01 2f movb $0x2f,0x1(%rax) + 43e5f7: 48 83 c0 02 add $0x2,%rax + 43e5fb: 48 85 d2 test %rdx,%rdx + 43e5fe: 0f 84 f4 fe ff ff je 43e4f8 <__wcsmbs_load_conv+0xf8> + 43e604: 85 f6 test %esi,%esi + 43e606: b9 25 67 4b 00 mov $0x4b6725,%ecx + 43e60b: be b1 3f 4a 00 mov $0x4a3fb1,%esi + 43e610: 48 0f 44 f1 cmove %rcx,%rsi + 43e614: 48 89 c7 mov %rax,%rdi + 43e617: e8 a4 7f fe ff callq 4265c0 <__mempcpy> + 43e61c: e9 d7 fe ff ff jmpq 43e4f8 <__wcsmbs_load_conv+0xf8> + 43e621: 49 c7 04 24 00 00 00 movq $0x0,(%r12) + 43e628: 00 + 43e629: 49 83 7c 24 10 00 cmpq $0x0,0x10(%r12) + 43e62f: 0f 85 09 ff ff ff jne 43e53e <__wcsmbs_load_conv+0x13e> + 43e635: eb 81 jmp 43e5b8 <__wcsmbs_load_conv+0x1b8> + 43e637: 4c 89 e8 mov %r13,%rax + 43e63a: e9 af fe ff ff jmpq 43e4ee <__wcsmbs_load_conv+0xee> + 43e63f: 31 c0 xor %eax,%eax + 43e641: e9 55 ff ff ff jmpq 43e59b <__wcsmbs_load_conv+0x19b> + 43e646: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43e64d: 00 00 00 + +000000000043e650 <__wcsmbs_clone_conv>: + 43e650: 55 push %rbp + 43e651: 53 push %rbx + 43e652: 48 89 fb mov %rdi,%rbx + 43e655: 48 83 ec 08 sub $0x8,%rsp + 43e659: 48 c7 c0 b0 ff ff ff mov $0xffffffffffffffb0,%rax + 43e660: 64 48 8b 00 mov %fs:(%rax),%rax + 43e664: 48 8b 28 mov (%rax),%rbp + 43e667: 48 8b 45 28 mov 0x28(%rbp),%rax + 43e66b: 48 85 c0 test %rax,%rax + 43e66e: 74 40 je 43e6b0 <__wcsmbs_clone_conv+0x60> + 43e670: 48 8b 10 mov (%rax),%rdx + 43e673: 48 89 13 mov %rdx,(%rbx) + 43e676: 48 8b 48 08 mov 0x8(%rax),%rcx + 43e67a: 48 83 3a 00 cmpq $0x0,(%rdx) + 43e67e: 48 89 4b 08 mov %rcx,0x8(%rbx) + 43e682: 48 8b 48 10 mov 0x10(%rax),%rcx + 43e686: 48 89 4b 10 mov %rcx,0x10(%rbx) + 43e68a: 48 8b 40 18 mov 0x18(%rax),%rax + 43e68e: 48 89 43 18 mov %rax,0x18(%rbx) + 43e692: 74 04 je 43e698 <__wcsmbs_clone_conv+0x48> + 43e694: 83 42 10 01 addl $0x1,0x10(%rdx) + 43e698: 48 8b 43 10 mov 0x10(%rbx),%rax + 43e69c: 48 83 38 00 cmpq $0x0,(%rax) + 43e6a0: 74 04 je 43e6a6 <__wcsmbs_clone_conv+0x56> + 43e6a2: 83 40 10 01 addl $0x1,0x10(%rax) + 43e6a6: 48 83 c4 08 add $0x8,%rsp + 43e6aa: 5b pop %rbx + 43e6ab: 5d pop %rbp + 43e6ac: c3 retq + 43e6ad: 0f 1f 00 nopl (%rax) + 43e6b0: 48 81 fd e0 69 4a 00 cmp $0x4a69e0,%rbp + 43e6b7: b8 c0 3f 4a 00 mov $0x4a3fc0,%eax + 43e6bc: 74 b2 je 43e670 <__wcsmbs_clone_conv+0x20> + 43e6be: 48 89 ef mov %rbp,%rdi + 43e6c1: e8 3a fd ff ff callq 43e400 <__wcsmbs_load_conv> + 43e6c6: 48 8b 45 28 mov 0x28(%rbp),%rax + 43e6ca: eb a4 jmp 43e670 <__wcsmbs_clone_conv+0x20> + 43e6cc: 0f 1f 40 00 nopl 0x0(%rax) + +000000000043e6d0 <__wcsmbs_named_conv>: + 43e6d0: 55 push %rbp + 43e6d1: 53 push %rbx + 43e6d2: 45 31 c0 xor %r8d,%r8d + 43e6d5: 48 89 fb mov %rdi,%rbx + 43e6d8: bf 6d 52 4a 00 mov $0x4a526d,%edi + 43e6dd: 48 89 f5 mov %rsi,%rbp + 43e6e0: 48 83 ec 18 sub $0x18,%rsp + 43e6e4: 48 8d 54 24 08 lea 0x8(%rsp),%rdx + 43e6e9: 48 89 e1 mov %rsp,%rcx + 43e6ec: e8 1f 6f 00 00 callq 445610 <__gconv_find_transform> + 43e6f1: 85 c0 test %eax,%eax + 43e6f3: 0f 85 a7 00 00 00 jne 43e7a0 <__wcsmbs_named_conv+0xd0> + 43e6f9: 48 8b 34 24 mov (%rsp),%rsi + 43e6fd: 48 83 fe 01 cmp $0x1,%rsi + 43e701: 76 1d jbe 43e720 <__wcsmbs_named_conv+0x50> + 43e703: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi + 43e708: e8 e3 71 00 00 callq 4458f0 <__gconv_close_transform> + 43e70d: 48 c7 03 00 00 00 00 movq $0x0,(%rbx) + 43e714: b8 01 00 00 00 mov $0x1,%eax + 43e719: 48 83 c4 18 add $0x18,%rsp + 43e71d: 5b pop %rbx + 43e71e: 5d pop %rbp + 43e71f: c3 retq + 43e720: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 43e725: 48 89 73 08 mov %rsi,0x8(%rbx) + 43e729: 48 85 c0 test %rax,%rax + 43e72c: 48 89 03 mov %rax,(%rbx) + 43e72f: 74 76 je 43e7a7 <__wcsmbs_named_conv+0xd7> + 43e731: 48 8d 54 24 08 lea 0x8(%rsp),%rdx + 43e736: 45 31 c0 xor %r8d,%r8d + 43e739: 48 89 e1 mov %rsp,%rcx + 43e73c: be 6d 52 4a 00 mov $0x4a526d,%esi + 43e741: 48 89 ef mov %rbp,%rdi + 43e744: e8 c7 6e 00 00 callq 445610 <__gconv_find_transform> + 43e749: 85 c0 test %eax,%eax + 43e74b: 75 6b jne 43e7b8 <__wcsmbs_named_conv+0xe8> + 43e74d: 48 8b 34 24 mov (%rsp),%rsi + 43e751: 48 83 fe 01 cmp $0x1,%rsi + 43e755: 76 29 jbe 43e780 <__wcsmbs_named_conv+0xb0> + 43e757: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi + 43e75c: e8 8f 71 00 00 callq 4458f0 <__gconv_close_transform> + 43e761: 48 c7 43 10 00 00 00 movq $0x0,0x10(%rbx) + 43e768: 00 + 43e769: 48 8b 73 08 mov 0x8(%rbx),%rsi + 43e76d: 48 8b 3b mov (%rbx),%rdi + 43e770: e8 7b 71 00 00 callq 4458f0 <__gconv_close_transform> + 43e775: b8 01 00 00 00 mov $0x1,%eax + 43e77a: eb 9d jmp 43e719 <__wcsmbs_named_conv+0x49> + 43e77c: 0f 1f 40 00 nopl 0x0(%rax) + 43e780: 48 8b 54 24 08 mov 0x8(%rsp),%rdx + 43e785: 48 89 73 18 mov %rsi,0x18(%rbx) + 43e789: 48 85 d2 test %rdx,%rdx + 43e78c: 48 89 53 10 mov %rdx,0x10(%rbx) + 43e790: 74 d7 je 43e769 <__wcsmbs_named_conv+0x99> + 43e792: 48 83 c4 18 add $0x18,%rsp + 43e796: 5b pop %rbx + 43e797: 5d pop %rbp + 43e798: c3 retq + 43e799: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43e7a0: 48 c7 03 00 00 00 00 movq $0x0,(%rbx) + 43e7a7: 48 83 c4 18 add $0x18,%rsp + 43e7ab: b8 01 00 00 00 mov $0x1,%eax + 43e7b0: 5b pop %rbx + 43e7b1: 5d pop %rbp + 43e7b2: c3 retq + 43e7b3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43e7b8: 48 c7 43 10 00 00 00 movq $0x0,0x10(%rbx) + 43e7bf: 00 + 43e7c0: eb a7 jmp 43e769 <__wcsmbs_named_conv+0x99> + 43e7c2: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43e7c9: 00 00 00 + 43e7cc: 0f 1f 40 00 nopl 0x0(%rax) + +000000000043e7d0 <_exit>: + 43e7d0: 48 63 d7 movslq %edi,%rdx + 43e7d3: 49 c7 c1 d0 ff ff ff mov $0xffffffffffffffd0,%r9 + 43e7da: 41 b8 e7 00 00 00 mov $0xe7,%r8d + 43e7e0: be 3c 00 00 00 mov $0x3c,%esi + 43e7e5: eb 19 jmp 43e800 <_exit+0x30> + 43e7e7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 43e7ee: 00 00 + 43e7f0: 48 89 d7 mov %rdx,%rdi + 43e7f3: 89 f0 mov %esi,%eax + 43e7f5: 0f 05 syscall + 43e7f7: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 43e7fd: 77 21 ja 43e820 <_exit+0x50> + 43e7ff: f4 hlt + 43e800: 48 89 d7 mov %rdx,%rdi + 43e803: 44 89 c0 mov %r8d,%eax + 43e806: 0f 05 syscall + 43e808: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 43e80e: 76 e0 jbe 43e7f0 <_exit+0x20> + 43e810: f7 d8 neg %eax + 43e812: 64 41 89 01 mov %eax,%fs:(%r9) + 43e816: eb d8 jmp 43e7f0 <_exit+0x20> + 43e818: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 43e81f: 00 + 43e820: f7 d8 neg %eax + 43e822: 64 41 89 01 mov %eax,%fs:(%r9) + 43e826: eb d7 jmp 43e7ff <_exit+0x2f> + 43e828: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 43e82f: 00 + +000000000043e830 <__sysconf_check_spec>: + 43e830: 55 push %rbp + 43e831: 48 89 e5 mov %rsp,%rbp + 43e834: 41 57 push %r15 + 43e836: 41 56 push %r14 + 43e838: 41 55 push %r13 + 43e83a: 41 54 push %r12 + 43e83c: 49 89 fd mov %rdi,%r13 + 43e83f: 53 push %rbx + 43e840: bf d9 40 4a 00 mov $0x4a40d9,%edi + 43e845: 48 81 ec 98 00 00 00 sub $0x98,%rsp + 43e84c: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 43e853: 64 44 8b 20 mov %fs:(%rax),%r12d + 43e857: e8 44 31 01 00 callq 4519a0 <__libc_secure_getenv> + 43e85c: 48 85 c0 test %rax,%rax + 43e85f: 0f 84 9b 00 00 00 je 43e900 <__sysconf_check_spec+0xd0> + 43e865: 48 89 c7 mov %rax,%rdi + 43e868: 49 89 c7 mov %rax,%r15 + 43e86b: e8 e0 4d fe ff callq 423650 + 43e870: 48 89 c3 mov %rax,%rbx + 43e873: 4c 89 ef mov %r13,%rdi + 43e876: e8 d5 4d fe ff callq 423650 + 43e87b: 49 89 c6 mov %rax,%r14 + 43e87e: 48 8d 44 03 1a lea 0x1a(%rbx,%rax,1),%rax + 43e883: 48 89 da mov %rbx,%rdx + 43e886: 4c 89 fe mov %r15,%rsi + 43e889: 48 83 e0 f0 and $0xfffffffffffffff0,%rax + 43e88d: 48 29 c4 sub %rax,%rsp + 43e890: 48 89 e7 mov %rsp,%rdi + 43e893: e8 28 7d fe ff callq 4265c0 <__mempcpy> + 43e898: ba 36 5f 00 00 mov $0x5f36,%edx + 43e89d: 48 b9 2f 50 4f 53 49 movabs $0x565f5849534f502f,%rcx + 43e8a4: 58 5f 56 + 43e8a7: 48 8d 78 0a lea 0xa(%rax),%rdi + 43e8ab: 66 89 50 08 mov %dx,0x8(%rax) + 43e8af: 49 8d 56 01 lea 0x1(%r14),%rdx + 43e8b3: 48 89 08 mov %rcx,(%rax) + 43e8b6: 4c 89 ee mov %r13,%rsi + 43e8b9: e8 62 d7 fe ff callq 42c020 + 43e8be: 48 8d 95 40 ff ff ff lea -0xc0(%rbp),%rdx + 43e8c5: 48 89 e6 mov %rsp,%rsi + 43e8c8: bf 01 00 00 00 mov $0x1,%edi + 43e8cd: e8 ae 07 00 00 callq 43f080 <__xstat> + 43e8d2: 48 c7 c1 d0 ff ff ff mov $0xffffffffffffffd0,%rcx + 43e8d9: 48 98 cltq + 43e8db: 48 c1 f8 3f sar $0x3f,%rax + 43e8df: 48 83 c8 01 or $0x1,%rax + 43e8e3: 64 44 89 21 mov %r12d,%fs:(%rcx) + 43e8e7: 48 8d 65 d8 lea -0x28(%rbp),%rsp + 43e8eb: 5b pop %rbx + 43e8ec: 41 5c pop %r12 + 43e8ee: 41 5d pop %r13 + 43e8f0: 41 5e pop %r14 + 43e8f2: 41 5f pop %r15 + 43e8f4: 5d pop %rbp + 43e8f5: c3 retq + 43e8f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43e8fd: 00 00 00 + 43e900: bb 10 00 00 00 mov $0x10,%ebx + 43e905: 41 bf c8 40 4a 00 mov $0x4a40c8,%r15d + 43e90b: e9 63 ff ff ff jmpq 43e873 <__sysconf_check_spec+0x43> + +000000000043e910 <__sysconf>: + 43e910: 55 push %rbp + 43e911: 53 push %rbx + 43e912: 89 fb mov %edi,%ebx + 43e914: 8d 83 47 ff ff ff lea -0xb9(%rbx),%eax + 43e91a: 48 83 ec 38 sub $0x38,%rsp + 43e91e: 83 f8 0e cmp $0xe,%eax + 43e921: 0f 86 19 01 00 00 jbe 43ea40 <__sysconf+0x130> + 43e927: 83 fb 22 cmp $0x22,%ebx + 43e92a: 0f 84 80 01 00 00 je 43eab0 <__sysconf+0x1a0> + 43e930: 0f 8f ba 00 00 00 jg 43e9f0 <__sysconf+0xe0> + 43e936: 85 db test %ebx,%ebx + 43e938: 0f 84 12 01 00 00 je 43ea50 <__sysconf+0x140> + 43e93e: 83 fb 03 cmp $0x3,%ebx + 43e941: bf 00 41 4a 00 mov $0x4a4100,%edi + 43e946: 0f 85 8c 00 00 00 jne 43e9d8 <__sysconf+0xc8> + 43e94c: 31 f6 xor %esi,%esi + 43e94e: b8 02 00 00 00 mov $0x2,%eax + 43e953: 0f 05 syscall + 43e955: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 43e95b: 0f 87 b7 06 00 00 ja 43f018 <__sysconf+0x708> + 43e961: 83 f8 ff cmp $0xffffffff,%eax + 43e964: 74 72 je 43e9d8 <__sysconf+0xc8> + 43e966: 48 8d 6c 24 10 lea 0x10(%rsp),%rbp + 43e96b: 4c 63 c0 movslq %eax,%r8 + 43e96e: 45 31 c9 xor %r9d,%r9d + 43e971: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43e978: ba 1f 00 00 00 mov $0x1f,%edx + 43e97d: 48 89 ee mov %rbp,%rsi + 43e980: 4c 89 c7 mov %r8,%rdi + 43e983: 44 89 c8 mov %r9d,%eax + 43e986: 0f 05 syscall + 43e988: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 43e98e: 0f 87 f4 00 00 00 ja 43ea88 <__sysconf+0x178> + 43e994: 48 89 c2 mov %rax,%rdx + 43e997: 4c 89 c7 mov %r8,%rdi + 43e99a: b8 03 00 00 00 mov $0x3,%eax + 43e99f: 0f 05 syscall + 43e9a1: 48 85 d2 test %rdx,%rdx + 43e9a4: 7e 32 jle 43e9d8 <__sysconf+0xc8> + 43e9a6: 48 8d 74 24 08 lea 0x8(%rsp),%rsi + 43e9ab: c6 44 14 10 00 movb $0x0,0x10(%rsp,%rdx,1) + 43e9b0: 48 89 ef mov %rbp,%rdi + 43e9b3: ba 0a 00 00 00 mov $0xa,%edx + 43e9b8: e8 13 30 01 00 callq 4519d0 <__strtol> + 43e9bd: 48 8b 54 24 08 mov 0x8(%rsp),%rdx + 43e9c2: 48 39 ea cmp %rbp,%rdx + 43e9c5: 74 11 je 43e9d8 <__sysconf+0xc8> + 43e9c7: 0f b6 12 movzbl (%rdx),%edx + 43e9ca: 84 d2 test %dl,%dl + 43e9cc: 74 61 je 43ea2f <__sysconf+0x11f> + 43e9ce: 80 fa 0a cmp $0xa,%dl + 43e9d1: 74 5c je 43ea2f <__sysconf+0x11f> + 43e9d3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43e9d8: 81 fb f6 00 00 00 cmp $0xf6,%ebx + 43e9de: 0f 87 17 06 00 00 ja 43effb <__sysconf+0x6eb> + 43e9e4: ff 24 dd 38 41 4a 00 jmpq *0x4a4138(,%rbx,8) + 43e9eb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43e9f0: 81 fb 8a 00 00 00 cmp $0x8a,%ebx + 43e9f6: 7c e0 jl 43e9d8 <__sysconf+0xc8> + 43e9f8: 81 fb 8b 00 00 00 cmp $0x8b,%ebx + 43e9fe: b8 69 10 03 00 mov $0x31069,%eax + 43ea03: 7e 2a jle 43ea2f <__sysconf+0x11f> + 43ea05: 81 fb 95 00 00 00 cmp $0x95,%ebx + 43ea0b: 75 cb jne 43e9d8 <__sysconf+0xc8> + 43ea0d: 48 8d 74 24 10 lea 0x10(%rsp),%rsi + 43ea12: bf 01 00 00 00 mov $0x1,%edi + 43ea17: b8 e5 00 00 00 mov $0xe5,%eax + 43ea1c: 0f 05 syscall + 43ea1e: 3d 01 f0 ff ff cmp $0xfffff001,%eax + 43ea23: 48 19 c0 sbb %rax,%rax + 43ea26: 25 6a 10 03 00 and $0x3106a,%eax + 43ea2b: 48 83 e8 01 sub $0x1,%rax + 43ea2f: 48 83 c4 38 add $0x38,%rsp + 43ea33: 5b pop %rbx + 43ea34: 5d pop %rbp + 43ea35: c3 retq + 43ea36: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43ea3d: 00 00 00 + 43ea40: 89 df mov %ebx,%edi + 43ea42: e8 89 f8 ff ff callq 43e2d0 <__cache_sysconf> + 43ea47: 48 83 c4 38 add $0x38,%rsp + 43ea4b: 5b pop %rbx + 43ea4c: 5d pop %rbp + 43ea4d: c3 retq + 43ea4e: 66 90 xchg %ax,%ax + 43ea50: 48 8d 74 24 10 lea 0x10(%rsp),%rsi + 43ea55: bf 03 00 00 00 mov $0x3,%edi + 43ea5a: e8 71 10 00 00 callq 43fad0 <__getrlimit> + 43ea5f: 89 c2 mov %eax,%edx + 43ea61: b8 00 00 02 00 mov $0x20000,%eax + 43ea66: 85 d2 test %edx,%edx + 43ea68: 75 c5 jne 43ea2f <__sysconf+0x11f> + 43ea6a: 48 8b 54 24 10 mov 0x10(%rsp),%rdx + 43ea6f: 48 89 d1 mov %rdx,%rcx + 43ea72: 48 c1 e9 02 shr $0x2,%rcx + 43ea76: 48 81 fa 00 00 08 00 cmp $0x80000,%rdx + 43ea7d: 48 0f 43 c1 cmovae %rcx,%rax + 43ea81: eb ac jmp 43ea2f <__sysconf+0x11f> + 43ea83: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43ea88: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx + 43ea8f: f7 d8 neg %eax + 43ea91: 83 f8 04 cmp $0x4,%eax + 43ea94: 64 89 02 mov %eax,%fs:(%rdx) + 43ea97: 0f 84 db fe ff ff je 43e978 <__sysconf+0x68> + 43ea9d: 48 c7 c2 ff ff ff ff mov $0xffffffffffffffff,%rdx + 43eaa4: e9 ee fe ff ff jmpq 43e997 <__sysconf+0x87> + 43eaa9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43eab0: 48 8d 74 24 10 lea 0x10(%rsp),%rsi + 43eab5: bf 0b 00 00 00 mov $0xb,%edi + 43eaba: e8 11 10 00 00 callq 43fad0 <__getrlimit> + 43eabf: 85 c0 test %eax,%eax + 43eac1: 75 0d jne 43ead0 <__sysconf+0x1c0> + 43eac3: 48 8b 44 24 10 mov 0x10(%rsp),%rax + 43eac8: e9 62 ff ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eacd: 0f 1f 00 nopl (%rax) + 43ead0: bf e5 40 4a 00 mov $0x4a40e5,%edi + 43ead5: e9 72 fe ff ff jmpq 43e94c <__sysconf+0x3c> + 43eada: b8 ff ff ff 7f mov $0x7fffffff,%eax + 43eadf: e9 4b ff ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eae4: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax + 43eaeb: e9 3f ff ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eaf0: e8 5b 05 00 00 callq 43f050 <__get_child_max> + 43eaf5: e9 35 ff ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eafa: e8 c1 39 00 00 callq 4424c0 <__getclktck> + 43eaff: 48 98 cltq + 43eb01: e9 29 ff ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eb06: b8 00 00 01 00 mov $0x10000,%eax + 43eb0b: e9 1f ff ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eb10: e8 ab 10 00 00 callq 43fbc0 <__getdtablesize> + 43eb15: 48 98 cltq + 43eb17: e9 13 ff ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eb1c: b8 10 00 00 00 mov $0x10,%eax + 43eb21: e9 09 ff ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eb26: e8 b5 90 02 00 callq 467be0 <__tzname_max> + 43eb2b: 48 89 c2 mov %rax,%rdx + 43eb2e: b8 06 00 00 00 mov $0x6,%eax + 43eb33: 48 83 fa 06 cmp $0x6,%rdx + 43eb37: 0f 8e f2 fe ff ff jle 43ea2f <__sysconf+0x11f> + 43eb3d: e8 9e 90 02 00 callq 467be0 <__tzname_max> + 43eb42: e9 e8 fe ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eb47: b8 01 00 00 00 mov $0x1,%eax + 43eb4c: e9 de fe ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eb51: b8 01 00 00 00 mov $0x1,%eax + 43eb56: e9 d4 fe ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eb5b: b8 69 10 03 00 mov $0x31069,%eax + 43eb60: e9 ca fe ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eb65: b8 69 10 03 00 mov $0x31069,%eax + 43eb6a: e9 c0 fe ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eb6f: b8 69 10 03 00 mov $0x31069,%eax + 43eb74: e9 b6 fe ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eb79: b8 69 10 03 00 mov $0x31069,%eax + 43eb7e: e9 ac fe ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eb83: b8 69 10 03 00 mov $0x31069,%eax + 43eb88: e9 a2 fe ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eb8d: b8 69 10 03 00 mov $0x31069,%eax + 43eb92: e9 98 fe ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eb97: b8 69 10 03 00 mov $0x31069,%eax + 43eb9c: e9 8e fe ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eba1: b8 69 10 03 00 mov $0x31069,%eax + 43eba6: e9 84 fe ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ebab: b8 69 10 03 00 mov $0x31069,%eax + 43ebb0: e9 7a fe ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ebb5: b8 69 10 03 00 mov $0x31069,%eax + 43ebba: e9 70 fe ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ebbf: b8 69 10 03 00 mov $0x31069,%eax + 43ebc4: e9 66 fe ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ebc9: b8 69 10 03 00 mov $0x31069,%eax + 43ebce: e9 5c fe ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ebd3: b8 69 10 03 00 mov $0x31069,%eax + 43ebd8: e9 52 fe ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ebdd: b8 69 10 03 00 mov $0x31069,%eax + 43ebe2: e9 48 fe ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ebe7: bf 29 41 4a 00 mov $0x4a4129,%edi + 43ebec: e8 3f fc ff ff callq 43e830 <__sysconf_check_spec> + 43ebf1: e9 39 fe ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ebf6: b8 01 00 00 00 mov $0x1,%eax + 43ebfb: e9 2f fe ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ec00: b8 14 00 00 00 mov $0x14,%eax + 43ec05: e9 25 fe ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ec0a: b8 ff ff ff 7f mov $0x7fffffff,%eax + 43ec0f: e9 1b fe ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ec14: b8 01 00 00 00 mov $0x1,%eax + 43ec19: e9 11 fe ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ec1e: b8 00 80 00 00 mov $0x8000,%eax + 43ec23: e9 07 fe ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ec28: b8 69 10 03 00 mov $0x31069,%eax + 43ec2d: e9 fd fd ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ec32: e8 59 0f 00 00 callq 43fb90 <__getpagesize> + 43ec37: 48 98 cltq + 43ec39: e9 f1 fd ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ec3e: b8 20 00 00 00 mov $0x20,%eax + 43ec43: e9 e7 fd ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ec48: bf 29 41 4a 00 mov $0x4a4129,%edi + 43ec4d: e8 de fb ff ff callq 43e830 <__sysconf_check_spec> + 43ec52: e9 d8 fd ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ec57: b8 ff ff ff 7f mov $0x7fffffff,%eax + 43ec5c: e9 ce fd ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ec61: bf 1d 41 4a 00 mov $0x4a411d,%edi + 43ec66: e8 c5 fb ff ff callq 43e830 <__sysconf_check_spec> + 43ec6b: e9 bf fd ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ec70: b8 69 10 03 00 mov $0x31069,%eax + 43ec75: e9 b5 fd ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ec7a: b8 63 00 00 00 mov $0x63,%eax + 43ec7f: e9 ab fd ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ec84: b8 00 08 00 00 mov $0x800,%eax + 43ec89: e9 a1 fd ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ec8e: b8 63 00 00 00 mov $0x63,%eax + 43ec93: e9 97 fd ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ec98: b8 e8 03 00 00 mov $0x3e8,%eax + 43ec9d: e9 8d fd ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eca2: b8 ff 00 00 00 mov $0xff,%eax + 43eca7: e9 83 fd ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ecac: b8 20 00 00 00 mov $0x20,%eax + 43ecb1: e9 79 fd ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ecb6: b8 00 08 00 00 mov $0x800,%eax + 43ecbb: e9 6f fd ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ecc0: b8 ff 7f 00 00 mov $0x7fff,%eax + 43ecc5: e9 65 fd ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ecca: b8 00 08 00 00 mov $0x800,%eax + 43eccf: e9 5b fd ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ecd4: b8 69 10 03 00 mov $0x31069,%eax + 43ecd9: e9 51 fd ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ecde: b8 69 10 03 00 mov $0x31069,%eax + 43ece3: e9 47 fd ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ece8: b8 69 10 03 00 mov $0x31069,%eax + 43eced: e9 3d fd ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ecf2: b8 69 10 03 00 mov $0x31069,%eax + 43ecf7: e9 33 fd ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ecfc: b8 69 10 03 00 mov $0x31069,%eax + 43ed01: e9 29 fd ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ed06: b8 69 10 03 00 mov $0x31069,%eax + 43ed0b: e9 1f fd ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ed10: b8 69 10 03 00 mov $0x31069,%eax + 43ed15: e9 15 fd ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ed1a: b8 69 10 03 00 mov $0x31069,%eax + 43ed1f: e9 0b fd ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ed24: bf 1d 41 4a 00 mov $0x4a411d,%edi + 43ed29: e8 02 fb ff ff callq 43e830 <__sysconf_check_spec> + 43ed2e: e9 fc fc ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ed33: b8 01 00 00 00 mov $0x1,%eax + 43ed38: e9 f2 fc ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ed3d: b8 69 10 03 00 mov $0x31069,%eax + 43ed42: e9 e8 fc ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ed47: b8 01 00 00 00 mov $0x1,%eax + 43ed4c: e9 de fc ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ed51: b8 01 00 00 00 mov $0x1,%eax + 43ed56: e9 d4 fc ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ed5b: b8 40 00 00 00 mov $0x40,%eax + 43ed60: e9 ca fc ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ed65: b8 00 04 00 00 mov $0x400,%eax + 43ed6a: e9 c0 fc ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ed6f: b8 69 10 03 00 mov $0x31069,%eax + 43ed74: e9 b6 fc ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ed79: b8 01 00 00 00 mov $0x1,%eax + 43ed7e: e9 ac fc ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ed83: bf 29 41 4a 00 mov $0x4a4129,%edi + 43ed88: e8 a3 fa ff ff callq 43e830 <__sysconf_check_spec> + 43ed8d: e9 9d fc ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ed92: bf 1d 41 4a 00 mov $0x4a411d,%edi + 43ed97: e8 94 fa ff ff callq 43e830 <__sysconf_check_spec> + 43ed9c: e9 8e fc ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eda1: b8 69 10 03 00 mov $0x31069,%eax + 43eda6: e9 84 fc ff ff jmpq 43ea2f <__sysconf+0x11f> + 43edab: b8 01 00 00 00 mov $0x1,%eax + 43edb0: e9 7a fc ff ff jmpq 43ea2f <__sysconf+0x11f> + 43edb5: b8 69 10 03 00 mov $0x31069,%eax + 43edba: e9 70 fc ff ff jmpq 43ea2f <__sysconf+0x11f> + 43edbf: b8 69 10 03 00 mov $0x31069,%eax + 43edc4: e9 66 fc ff ff jmpq 43ea2f <__sysconf+0x11f> + 43edc9: b8 00 04 00 00 mov $0x400,%eax + 43edce: e9 5c fc ff ff jmpq 43ea2f <__sysconf+0x11f> + 43edd3: b8 00 04 00 00 mov $0x400,%eax + 43edd8: e9 52 fc ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eddd: b8 00 01 00 00 mov $0x100,%eax + 43ede2: e9 48 fc ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ede7: b8 20 00 00 00 mov $0x20,%eax + 43edec: e9 3e fc ff ff jmpq 43ea2f <__sysconf+0x11f> + 43edf1: b8 04 00 00 00 mov $0x4,%eax + 43edf6: e9 34 fc ff ff jmpq 43ea2f <__sysconf+0x11f> + 43edfb: b8 00 04 00 00 mov $0x400,%eax + 43ee00: e9 2a fc ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ee05: b8 00 40 00 00 mov $0x4000,%eax + 43ee0a: e9 20 fc ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ee0f: b8 69 10 03 00 mov $0x31069,%eax + 43ee14: e9 16 fc ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ee19: b8 69 10 03 00 mov $0x31069,%eax + 43ee1e: e9 0c fc ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ee23: b8 69 10 03 00 mov $0x31069,%eax + 43ee28: e9 02 fc ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ee2d: b8 69 10 03 00 mov $0x31069,%eax + 43ee32: e9 f8 fb ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ee37: b8 69 10 03 00 mov $0x31069,%eax + 43ee3c: e9 ee fb ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ee41: b8 69 10 03 00 mov $0x31069,%eax + 43ee46: e9 e4 fb ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ee4b: b8 69 10 03 00 mov $0x31069,%eax + 43ee50: e9 da fb ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ee55: e8 e6 34 00 00 callq 442340 <__get_nprocs_conf> + 43ee5a: 48 98 cltq + 43ee5c: e9 ce fb ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ee61: e8 da 31 00 00 callq 442040 <__get_nprocs> + 43ee66: 48 98 cltq + 43ee68: e9 c2 fb ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ee6d: e8 6e 35 00 00 callq 4423e0 <__get_phys_pages> + 43ee72: e9 b8 fb ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ee77: e8 d4 35 00 00 callq 442450 <__get_avphys_pages> + 43ee7c: e9 ae fb ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ee81: b8 ff ff ff 7f mov $0x7fffffff,%eax + 43ee86: e9 a4 fb ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ee8b: b8 00 20 00 00 mov $0x2000,%eax + 43ee90: e9 9a fb ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ee95: b8 bc 02 00 00 mov $0x2bc,%eax + 43ee9a: e9 90 fb ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ee9f: b8 04 00 00 00 mov $0x4,%eax + 43eea4: e9 86 fb ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eea9: b8 01 00 00 00 mov $0x1,%eax + 43eeae: e9 7c fb ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eeb3: b8 01 00 00 00 mov $0x1,%eax + 43eeb8: e9 72 fb ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eebd: b8 01 00 00 00 mov $0x1,%eax + 43eec2: e9 68 fb ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eec7: b8 01 00 00 00 mov $0x1,%eax + 43eecc: e9 5e fb ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eed1: b8 69 10 03 00 mov $0x31069,%eax + 43eed6: e9 54 fb ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eedb: b8 69 10 03 00 mov $0x31069,%eax + 43eee0: e9 4a fb ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eee5: b8 01 00 00 00 mov $0x1,%eax + 43eeea: e9 40 fb ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eeef: b8 01 00 00 00 mov $0x1,%eax + 43eef4: e9 36 fb ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eef9: b8 01 00 00 00 mov $0x1,%eax + 43eefe: e9 2c fb ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ef03: b8 01 00 00 00 mov $0x1,%eax + 43ef08: e9 22 fb ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ef0d: b8 08 00 00 00 mov $0x8,%eax + 43ef12: e9 18 fb ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ef17: b8 7f 00 00 00 mov $0x7f,%eax + 43ef1c: e9 0e fb ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ef21: 48 c7 c0 80 ff ff ff mov $0xffffffffffffff80,%rax + 43ef28: e9 02 fb ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ef2d: b8 ff ff ff 7f mov $0x7fffffff,%eax + 43ef32: e9 f8 fa ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ef37: 48 c7 c0 00 00 00 80 mov $0xffffffff80000000,%rax + 43ef3e: e9 ec fa ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ef43: b8 40 00 00 00 mov $0x40,%eax + 43ef48: e9 e2 fa ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ef4d: b8 20 00 00 00 mov $0x20,%eax + 43ef52: e9 d8 fa ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ef57: b8 10 00 00 00 mov $0x10,%eax + 43ef5c: e9 ce fa ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ef61: b8 14 00 00 00 mov $0x14,%eax + 43ef66: e9 c4 fa ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ef6b: b8 ff 7f 00 00 mov $0x7fff,%eax + 43ef70: e9 ba fa ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ef75: b8 7f 00 00 00 mov $0x7f,%eax + 43ef7a: e9 b0 fa ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ef7f: 48 c7 c0 80 ff ff ff mov $0xffffffffffffff80,%rax + 43ef86: e9 a4 fa ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ef8b: b8 ff 7f 00 00 mov $0x7fff,%eax + 43ef90: e9 9a fa ff ff jmpq 43ea2f <__sysconf+0x11f> + 43ef95: 48 c7 c0 00 80 ff ff mov $0xffffffffffff8000,%rax + 43ef9c: e9 8e fa ff ff jmpq 43ea2f <__sysconf+0x11f> + 43efa1: b8 ff 00 00 00 mov $0xff,%eax + 43efa6: e9 84 fa ff ff jmpq 43ea2f <__sysconf+0x11f> + 43efab: b8 ff ff ff ff mov $0xffffffff,%eax + 43efb0: e9 7a fa ff ff jmpq 43ea2f <__sysconf+0x11f> + 43efb5: b8 69 10 03 00 mov $0x31069,%eax + 43efba: e9 70 fa ff ff jmpq 43ea2f <__sysconf+0x11f> + 43efbf: b8 ff ff 00 00 mov $0xffff,%eax + 43efc4: e9 66 fa ff ff jmpq 43ea2f <__sysconf+0x11f> + 43efc9: b8 00 10 00 00 mov $0x1000,%eax + 43efce: e9 5c fa ff ff jmpq 43ea2f <__sysconf+0x11f> + 43efd3: b8 00 08 00 00 mov $0x800,%eax + 43efd8: e9 52 fa ff ff jmpq 43ea2f <__sysconf+0x11f> + 43efdd: b8 ff ff ff 7f mov $0x7fffffff,%eax + 43efe2: e9 48 fa ff ff jmpq 43ea2f <__sysconf+0x11f> + 43efe7: b8 ff ff ff 7f mov $0x7fffffff,%eax + 43efec: e9 3e fa ff ff jmpq 43ea2f <__sysconf+0x11f> + 43eff1: b8 ff ff ff 7f mov $0x7fffffff,%eax + 43eff6: e9 34 fa ff ff jmpq 43ea2f <__sysconf+0x11f> + 43effb: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 43f002: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) + 43f009: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax + 43f010: e9 1a fa ff ff jmpq 43ea2f <__sysconf+0x11f> + 43f015: 0f 1f 00 nopl (%rax) + 43f018: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx + 43f01f: f7 d8 neg %eax + 43f021: 64 89 02 mov %eax,%fs:(%rdx) + 43f024: e9 af f9 ff ff jmpq 43e9d8 <__sysconf+0xc8> + 43f029: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + +000000000043f030 <__sched_yield>: + 43f030: b8 18 00 00 00 mov $0x18,%eax + 43f035: 0f 05 syscall + 43f037: 48 3d 01 f0 ff ff cmp $0xfffffffffffff001,%rax + 43f03d: 0f 83 0d 51 00 00 jae 444150 <__syscall_error> + 43f043: c3 retq + 43f044: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43f04b: 00 00 00 + 43f04e: 66 90 xchg %ax,%ax + +000000000043f050 <__get_child_max>: + 43f050: 48 83 ec 18 sub $0x18,%rsp + 43f054: bf 06 00 00 00 mov $0x6,%edi + 43f059: 48 89 e6 mov %rsp,%rsi + 43f05c: e8 6f 0a 00 00 callq 43fad0 <__getrlimit> + 43f061: 85 c0 test %eax,%eax + 43f063: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax + 43f06a: 48 0f 44 04 24 cmove (%rsp),%rax + 43f06f: 48 83 c4 18 add $0x18,%rsp + 43f073: c3 retq + 43f074: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43f07b: 00 00 00 + 43f07e: 66 90 xchg %ax,%ax + +000000000043f080 <__xstat>: + 43f080: 83 ff 01 cmp $0x1,%edi + 43f083: 48 89 f0 mov %rsi,%rax + 43f086: 77 30 ja 43f0b8 <__xstat+0x38> + 43f088: 48 89 c7 mov %rax,%rdi + 43f08b: 48 89 d6 mov %rdx,%rsi + 43f08e: b8 04 00 00 00 mov $0x4,%eax + 43f093: 0f 05 syscall + 43f095: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 43f09b: 77 03 ja 43f0a0 <__xstat+0x20> + 43f09d: f3 c3 repz retq + 43f09f: 90 nop + 43f0a0: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx + 43f0a7: f7 d8 neg %eax + 43f0a9: 64 89 02 mov %eax,%fs:(%rdx) + 43f0ac: b8 ff ff ff ff mov $0xffffffff,%eax + 43f0b1: c3 retq + 43f0b2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43f0b8: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 43f0bf: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) + 43f0c6: b8 ff ff ff ff mov $0xffffffff,%eax + 43f0cb: c3 retq + 43f0cc: 0f 1f 40 00 nopl 0x0(%rax) + +000000000043f0d0 <__fxstat>: + 43f0d0: 83 ff 01 cmp $0x1,%edi + 43f0d3: 89 f0 mov %esi,%eax + 43f0d5: 77 31 ja 43f108 <__fxstat+0x38> + 43f0d7: 48 63 f8 movslq %eax,%rdi + 43f0da: 48 89 d6 mov %rdx,%rsi + 43f0dd: b8 05 00 00 00 mov $0x5,%eax + 43f0e2: 0f 05 syscall + 43f0e4: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 43f0ea: 77 04 ja 43f0f0 <__fxstat+0x20> + 43f0ec: f3 c3 repz retq + 43f0ee: 66 90 xchg %ax,%ax + 43f0f0: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx + 43f0f7: f7 d8 neg %eax + 43f0f9: 64 89 02 mov %eax,%fs:(%rdx) + 43f0fc: b8 ff ff ff ff mov $0xffffffff,%eax + 43f101: c3 retq + 43f102: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43f108: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 43f10f: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) + 43f116: b8 ff ff ff ff mov $0xffffffff,%eax + 43f11b: c3 retq + 43f11c: 0f 1f 40 00 nopl 0x0(%rax) + +000000000043f120 <__libc_open>: + 43f120: 83 3d 95 e0 28 00 00 cmpl $0x0,0x28e095(%rip) # 6cd1bc <__libc_multiple_threads> + 43f127: 75 14 jne 43f13d <__open_nocancel+0x14> + +000000000043f129 <__open_nocancel>: + 43f129: b8 02 00 00 00 mov $0x2,%eax + 43f12e: 0f 05 syscall + 43f130: 48 3d 01 f0 ff ff cmp $0xfffffffffffff001,%rax + 43f136: 0f 83 14 50 00 00 jae 444150 <__syscall_error> + 43f13c: c3 retq + 43f13d: 48 83 ec 08 sub $0x8,%rsp + 43f141: e8 da 34 00 00 callq 442620 <__libc_enable_asynccancel> + 43f146: 48 89 04 24 mov %rax,(%rsp) + 43f14a: b8 02 00 00 00 mov $0x2,%eax + 43f14f: 0f 05 syscall + 43f151: 48 8b 3c 24 mov (%rsp),%rdi + 43f155: 48 89 c2 mov %rax,%rdx + 43f158: e8 23 35 00 00 callq 442680 <__libc_disable_asynccancel> + 43f15d: 48 89 d0 mov %rdx,%rax + 43f160: 48 83 c4 08 add $0x8,%rsp + 43f164: 48 3d 01 f0 ff ff cmp $0xfffffffffffff001,%rax + 43f16a: 0f 83 e0 4f 00 00 jae 444150 <__syscall_error> + 43f170: c3 retq + 43f171: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43f178: 00 00 00 + 43f17b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + +000000000043f180 <__libc_read>: + 43f180: 83 3d 35 e0 28 00 00 cmpl $0x0,0x28e035(%rip) # 6cd1bc <__libc_multiple_threads> + 43f187: 75 14 jne 43f19d <__read_nocancel+0x14> + +000000000043f189 <__read_nocancel>: + 43f189: b8 00 00 00 00 mov $0x0,%eax + 43f18e: 0f 05 syscall + 43f190: 48 3d 01 f0 ff ff cmp $0xfffffffffffff001,%rax + 43f196: 0f 83 b4 4f 00 00 jae 444150 <__syscall_error> + 43f19c: c3 retq + 43f19d: 48 83 ec 08 sub $0x8,%rsp + 43f1a1: e8 7a 34 00 00 callq 442620 <__libc_enable_asynccancel> + 43f1a6: 48 89 04 24 mov %rax,(%rsp) + 43f1aa: b8 00 00 00 00 mov $0x0,%eax + 43f1af: 0f 05 syscall + 43f1b1: 48 8b 3c 24 mov (%rsp),%rdi + 43f1b5: 48 89 c2 mov %rax,%rdx + 43f1b8: e8 c3 34 00 00 callq 442680 <__libc_disable_asynccancel> + 43f1bd: 48 89 d0 mov %rdx,%rax + 43f1c0: 48 83 c4 08 add $0x8,%rsp + 43f1c4: 48 3d 01 f0 ff ff cmp $0xfffffffffffff001,%rax + 43f1ca: 0f 83 80 4f 00 00 jae 444150 <__syscall_error> + 43f1d0: c3 retq + 43f1d1: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43f1d8: 00 00 00 + 43f1db: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + +000000000043f1e0 <__libc_write>: + 43f1e0: 83 3d d5 df 28 00 00 cmpl $0x0,0x28dfd5(%rip) # 6cd1bc <__libc_multiple_threads> + 43f1e7: 75 14 jne 43f1fd <__write_nocancel+0x14> + +000000000043f1e9 <__write_nocancel>: + 43f1e9: b8 01 00 00 00 mov $0x1,%eax + 43f1ee: 0f 05 syscall + 43f1f0: 48 3d 01 f0 ff ff cmp $0xfffffffffffff001,%rax + 43f1f6: 0f 83 54 4f 00 00 jae 444150 <__syscall_error> + 43f1fc: c3 retq + 43f1fd: 48 83 ec 08 sub $0x8,%rsp + 43f201: e8 1a 34 00 00 callq 442620 <__libc_enable_asynccancel> + 43f206: 48 89 04 24 mov %rax,(%rsp) + 43f20a: b8 01 00 00 00 mov $0x1,%eax + 43f20f: 0f 05 syscall + 43f211: 48 8b 3c 24 mov (%rsp),%rdi + 43f215: 48 89 c2 mov %rax,%rdx + 43f218: e8 63 34 00 00 callq 442680 <__libc_disable_asynccancel> + 43f21d: 48 89 d0 mov %rdx,%rax + 43f220: 48 83 c4 08 add $0x8,%rsp + 43f224: 48 3d 01 f0 ff ff cmp $0xfffffffffffff001,%rax + 43f22a: 0f 83 20 4f 00 00 jae 444150 <__syscall_error> + 43f230: c3 retq + 43f231: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43f238: 00 00 00 + 43f23b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + +000000000043f240 <__fcntl_nocancel>: + 43f240: 48 8d 44 24 08 lea 0x8(%rsp),%rax + 43f245: 83 fe 09 cmp $0x9,%esi + 43f248: 48 89 54 24 d8 mov %rdx,-0x28(%rsp) + 43f24d: c7 44 24 b0 10 00 00 movl $0x10,-0x50(%rsp) + 43f254: 00 + 43f255: 48 89 44 24 b8 mov %rax,-0x48(%rsp) + 43f25a: 48 8d 44 24 c8 lea -0x38(%rsp),%rax + 43f25f: 48 89 44 24 c0 mov %rax,-0x40(%rsp) + 43f264: 74 1a je 43f280 <__fcntl_nocancel+0x40> + 43f266: 48 63 f6 movslq %esi,%rsi + 43f269: 48 63 ff movslq %edi,%rdi + 43f26c: b8 48 00 00 00 mov $0x48,%eax + 43f271: 0f 05 syscall + 43f273: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 43f279: 77 35 ja 43f2b0 <__fcntl_nocancel+0x70> + 43f27b: f3 c3 repz retq + 43f27d: 0f 1f 00 nopl (%rax) + 43f280: 48 8d 54 24 a8 lea -0x58(%rsp),%rdx + 43f285: be 10 00 00 00 mov $0x10,%esi + 43f28a: 48 63 ff movslq %edi,%rdi + 43f28d: b8 48 00 00 00 mov $0x48,%eax + 43f292: 0f 05 syscall + 43f294: 3d 00 f0 ff ff cmp $0xfffff000,%eax + 43f299: 77 15 ja 43f2b0 <__fcntl_nocancel+0x70> + 43f29b: 8b 44 24 ac mov -0x54(%rsp),%eax + 43f29f: 89 c2 mov %eax,%edx + 43f2a1: f7 da neg %edx + 43f2a3: 83 7c 24 a8 02 cmpl $0x2,-0x58(%rsp) + 43f2a8: 0f 44 c2 cmove %edx,%eax + 43f2ab: c3 retq + 43f2ac: 0f 1f 40 00 nopl 0x0(%rax) + 43f2b0: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx + 43f2b7: f7 d8 neg %eax + 43f2b9: 64 89 02 mov %eax,%fs:(%rdx) + 43f2bc: b8 ff ff ff ff mov $0xffffffff,%eax + 43f2c1: c3 retq + 43f2c2: 0f 1f 40 00 nopl 0x0(%rax) + 43f2c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43f2cd: 00 00 00 + +000000000043f2d0 <__libc_fcntl>: + 43f2d0: 53 push %rbx + 43f2d1: 48 83 ec 60 sub $0x60,%rsp + 43f2d5: 48 8d 44 24 70 lea 0x70(%rsp),%rax + 43f2da: 48 89 54 24 40 mov %rdx,0x40(%rsp) + 43f2df: c7 44 24 18 10 00 00 movl $0x10,0x18(%rsp) + 43f2e6: 00 + 43f2e7: 48 89 44 24 20 mov %rax,0x20(%rsp) + 43f2ec: 48 8d 44 24 30 lea 0x30(%rsp),%rax + 43f2f1: 48 89 44 24 28 mov %rax,0x28(%rsp) + 43f2f6: 8b 05 c0 de 28 00 mov 0x28dec0(%rip),%eax # 6cd1bc <__libc_multiple_threads> + 43f2fc: 85 c0 test %eax,%eax + 43f2fe: 74 05 je 43f305 <__libc_fcntl+0x35> + 43f300: 83 fe 07 cmp $0x7,%esi + 43f303: 74 73 je 43f378 <__libc_fcntl+0xa8> + 43f305: 83 fe 09 cmp $0x9,%esi + 43f308: 74 1e je 43f328 <__libc_fcntl+0x58> + 43f30a: 48 63 f6 movslq %esi,%rsi + 43f30d: 48 63 ff movslq %edi,%rdi + 43f310: b8 48 00 00 00 mov $0x48,%eax + 43f315: 0f 05 syscall + 43f317: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 43f31d: 77 41 ja 43f360 <__libc_fcntl+0x90> + 43f31f: 48 83 c4 60 add $0x60,%rsp + 43f323: 5b pop %rbx + 43f324: c3 retq + 43f325: 0f 1f 00 nopl (%rax) + 43f328: 48 8d 54 24 10 lea 0x10(%rsp),%rdx + 43f32d: be 10 00 00 00 mov $0x10,%esi + 43f332: 48 63 ff movslq %edi,%rdi + 43f335: b8 48 00 00 00 mov $0x48,%eax + 43f33a: 0f 05 syscall + 43f33c: 3d 00 f0 ff ff cmp $0xfffff000,%eax + 43f341: 77 1d ja 43f360 <__libc_fcntl+0x90> + 43f343: 8b 44 24 14 mov 0x14(%rsp),%eax + 43f347: 89 c2 mov %eax,%edx + 43f349: f7 da neg %edx + 43f34b: 83 7c 24 10 02 cmpl $0x2,0x10(%rsp) + 43f350: 0f 44 c2 cmove %edx,%eax + 43f353: 48 83 c4 60 add $0x60,%rsp + 43f357: 5b pop %rbx + 43f358: c3 retq + 43f359: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43f360: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx + 43f367: f7 d8 neg %eax + 43f369: 64 89 02 mov %eax,%fs:(%rdx) + 43f36c: b8 ff ff ff ff mov $0xffffffff,%eax + 43f371: eb ac jmp 43f31f <__libc_fcntl+0x4f> + 43f373: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43f378: 89 fb mov %edi,%ebx + 43f37a: 48 89 54 24 08 mov %rdx,0x8(%rsp) + 43f37f: e8 9c 32 00 00 callq 442620 <__libc_enable_asynccancel> + 43f384: 48 8b 54 24 08 mov 0x8(%rsp),%rdx + 43f389: 41 89 c0 mov %eax,%r8d + 43f38c: be 07 00 00 00 mov $0x7,%esi + 43f391: 48 63 fb movslq %ebx,%rdi + 43f394: b8 48 00 00 00 mov $0x48,%eax + 43f399: 0f 05 syscall + 43f39b: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 43f3a1: 77 15 ja 43f3b8 <__libc_fcntl+0xe8> + 43f3a3: 44 89 c7 mov %r8d,%edi + 43f3a6: 89 44 24 08 mov %eax,0x8(%rsp) + 43f3aa: e8 d1 32 00 00 callq 442680 <__libc_disable_asynccancel> + 43f3af: 8b 44 24 08 mov 0x8(%rsp),%eax + 43f3b3: e9 67 ff ff ff jmpq 43f31f <__libc_fcntl+0x4f> + 43f3b8: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx + 43f3bf: f7 d8 neg %eax + 43f3c1: 64 89 02 mov %eax,%fs:(%rdx) + 43f3c4: b8 ff ff ff ff mov $0xffffffff,%eax + 43f3c9: eb d8 jmp 43f3a3 <__libc_fcntl+0xd3> + 43f3cb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + +000000000043f3d0 <__getcwd>: + 43f3d0: 41 57 push %r15 + 43f3d2: 41 56 push %r14 + 43f3d4: 49 89 f6 mov %rsi,%r14 + 43f3d7: 41 55 push %r13 + 43f3d9: 41 54 push %r12 + 43f3db: 55 push %rbp + 43f3dc: 53 push %rbx + 43f3dd: 48 89 fb mov %rdi,%rbx + 43f3e0: 48 81 ec f8 00 00 00 sub $0xf8,%rsp + 43f3e7: 48 85 f6 test %rsi,%rsi + 43f3ea: 75 5c jne 43f448 <__getcwd+0x78> + 43f3ec: 48 85 ff test %rdi,%rdi + 43f3ef: 0f 85 2b 04 00 00 jne 43f820 <__getcwd+0x450> + 43f3f5: e8 96 07 00 00 callq 43fb90 <__getpagesize> + 43f3fa: be 00 10 00 00 mov $0x1000,%esi + 43f3ff: 3d 00 10 00 00 cmp $0x1000,%eax + 43f404: 0f 4d f0 cmovge %eax,%esi + 43f407: 48 63 f6 movslq %esi,%rsi + 43f40a: 48 89 f7 mov %rsi,%rdi + 43f40d: 48 89 74 24 10 mov %rsi,0x10(%rsp) + 43f412: e8 f9 e5 fd ff callq 41da10 <__libc_malloc> + 43f417: 48 85 c0 test %rax,%rax + 43f41a: 48 89 44 24 08 mov %rax,0x8(%rsp) + 43f41f: 48 8b 74 24 10 mov 0x10(%rsp),%rsi + 43f424: 75 2c jne 43f452 <__getcwd+0x82> + 43f426: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43f42d: 00 00 00 + 43f430: 31 c0 xor %eax,%eax + 43f432: 48 81 c4 f8 00 00 00 add $0xf8,%rsp + 43f439: 5b pop %rbx + 43f43a: 5d pop %rbp + 43f43b: 41 5c pop %r12 + 43f43d: 41 5d pop %r13 + 43f43f: 41 5e pop %r14 + 43f441: 41 5f pop %r15 + 43f443: c3 retq + 43f444: 0f 1f 40 00 nopl 0x0(%rax) + 43f448: 48 85 ff test %rdi,%rdi + 43f44b: 74 bd je 43f40a <__getcwd+0x3a> + 43f44d: 48 89 7c 24 08 mov %rdi,0x8(%rsp) + 43f452: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi + 43f457: b8 4f 00 00 00 mov $0x4f,%eax + 43f45c: 0f 05 syscall + 43f45e: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 43f464: 0f 87 9d 04 00 00 ja 43f907 <__getcwd+0x537> + 43f46a: 83 f8 00 cmp $0x0,%eax + 43f46d: 0f 8e 3d 04 00 00 jle 43f8b0 <__getcwd+0x4e0> + 43f473: 48 8b 54 24 08 mov 0x8(%rsp),%rdx + 43f478: 80 3a 2f cmpb $0x2f,(%rdx) + 43f47b: 0f 84 b7 03 00 00 je 43f838 <__getcwd+0x468> + 43f481: 48 c7 c5 d0 ff ff ff mov $0xffffffffffffffd0,%rbp + 43f488: 48 85 db test %rbx,%rbx + 43f48b: 0f 94 44 24 43 sete 0x43(%rsp) + 43f490: 4d 85 f6 test %r14,%r14 + 43f493: 0f b6 44 24 43 movzbl 0x43(%rsp),%eax + 43f498: 75 08 jne 43f4a2 <__getcwd+0xd2> + 43f49a: 84 c0 test %al,%al + 43f49c: 0f 85 c6 03 00 00 jne 43f868 <__getcwd+0x498> + 43f4a2: 4d 85 f6 test %r14,%r14 + 43f4a5: 0f 84 45 04 00 00 je 43f8f0 <__getcwd+0x520> + 43f4ab: 64 8b 45 00 mov %fs:0x0(%rbp),%eax + 43f4af: 4c 89 74 24 28 mov %r14,0x28(%rsp) + 43f4b4: 89 44 24 44 mov %eax,0x44(%rsp) + 43f4b8: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 43f4bd: 48 89 44 24 20 mov %rax,0x20(%rsp) + 43f4c2: 48 89 c3 mov %rax,%rbx + 43f4c5: 48 03 5c 24 28 add 0x28(%rsp),%rbx + 43f4ca: 48 8d 54 24 60 lea 0x60(%rsp),%rdx + 43f4cf: be f1 48 4a 00 mov $0x4a48f1,%esi + 43f4d4: bf 01 00 00 00 mov $0x1,%edi + 43f4d9: 48 8d 43 ff lea -0x1(%rbx),%rax + 43f4dd: c6 43 ff 00 movb $0x0,-0x1(%rbx) + 43f4e1: 48 89 44 24 38 mov %rax,0x38(%rsp) + 43f4e6: e8 55 b4 02 00 callq 46a940 <__lxstat> + 43f4eb: 85 c0 test %eax,%eax + 43f4ed: 0f 88 23 04 00 00 js 43f916 <__getcwd+0x546> + 43f4f3: 48 8b 44 24 68 mov 0x68(%rsp),%rax + 43f4f8: 48 8d 54 24 60 lea 0x60(%rsp),%rdx + 43f4fd: be ae 48 4b 00 mov $0x4b48ae,%esi + 43f502: bf 01 00 00 00 mov $0x1,%edi + 43f507: 4c 8b 7c 24 60 mov 0x60(%rsp),%r15 + 43f50c: 49 89 c5 mov %rax,%r13 + 43f50f: 48 89 44 24 18 mov %rax,0x18(%rsp) + 43f514: e8 27 b4 02 00 callq 46a940 <__lxstat> + 43f519: 85 c0 test %eax,%eax + 43f51b: 0f 88 f5 03 00 00 js 43f916 <__getcwd+0x546> + 43f521: 48 8b 44 24 60 mov 0x60(%rsp),%rax + 43f526: 48 89 c1 mov %rax,%rcx + 43f529: 48 89 44 24 48 mov %rax,0x48(%rsp) + 43f52e: 48 8b 44 24 68 mov 0x68(%rsp),%rax + 43f533: 48 89 c2 mov %rax,%rdx + 43f536: 48 89 44 24 50 mov %rax,0x50(%rsp) + 43f53b: 49 39 d5 cmp %rdx,%r13 + 43f53e: 75 09 jne 43f549 <__getcwd+0x179> + 43f540: 49 39 cf cmp %rcx,%r15 + 43f543: 0f 84 00 04 00 00 je 43f949 <__getcwd+0x579> + 43f549: ba 00 00 08 00 mov $0x80000,%edx + 43f54e: be f0 48 4a 00 mov $0x4a48f0,%esi + 43f553: 48 c7 c7 9c ff ff ff mov $0xffffffffffffff9c,%rdi + 43f55a: b8 01 01 00 00 mov $0x101,%eax + 43f55f: 0f 05 syscall + 43f561: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 43f567: 0f 87 44 04 00 00 ja 43f9b1 <__getcwd+0x5e1> + 43f56d: 85 c0 test %eax,%eax + 43f56f: 89 44 24 10 mov %eax,0x10(%rsp) + 43f573: 0f 88 19 05 00 00 js 43fa92 <__getcwd+0x6c2> + 43f579: 45 31 e4 xor %r12d,%r12d + 43f57c: 4c 89 74 24 30 mov %r14,0x30(%rsp) + 43f581: 89 c6 mov %eax,%esi + 43f583: 48 8d 54 24 60 lea 0x60(%rsp),%rdx + 43f588: bf 01 00 00 00 mov $0x1,%edi + 43f58d: e8 3e fb ff ff callq 43f0d0 <__fxstat> + 43f592: 85 c0 test %eax,%eax + 43f594: 0f 88 75 04 00 00 js 43fa0f <__getcwd+0x63f> + 43f59a: 4d 85 e4 test %r12,%r12 + 43f59d: 74 10 je 43f5af <__getcwd+0x1df> + 43f59f: 4c 89 e7 mov %r12,%rdi + 43f5a2: e8 09 b0 02 00 callq 46a5b0 <__closedir> + 43f5a7: 85 c0 test %eax,%eax + 43f5a9: 0f 85 50 04 00 00 jne 43f9ff <__getcwd+0x62f> + 43f5af: 48 8b 44 24 68 mov 0x68(%rsp),%rax + 43f5b4: 8b 7c 24 10 mov 0x10(%rsp),%edi + 43f5b8: 4c 8b 74 24 60 mov 0x60(%rsp),%r14 + 43f5bd: 48 89 44 24 58 mov %rax,0x58(%rsp) + 43f5c2: e8 79 b2 02 00 callq 46a840 <__fdopendir> + 43f5c7: 48 85 c0 test %rax,%rax + 43f5ca: 49 89 c4 mov %rax,%r12 + 43f5cd: 75 2d jne 43f5fc <__getcwd+0x22c> + 43f5cf: e9 2b 04 00 00 jmpq 43f9ff <__getcwd+0x62f> + 43f5d4: 0f 1f 40 00 nopl 0x0(%rax) + 43f5d8: f6 40 12 fb testb $0xfb,0x12(%rax) + 43f5dc: 75 24 jne 43f602 <__getcwd+0x232> + 43f5de: 80 78 13 2e cmpb $0x2e,0x13(%rax) + 43f5e2: 0f 84 b0 01 00 00 je 43f798 <__getcwd+0x3c8> + 43f5e8: 4d 39 f7 cmp %r14,%r15 + 43f5eb: 75 53 jne 43f640 <__getcwd+0x270> + 43f5ed: 45 84 ed test %r13b,%r13b + 43f5f0: 74 4e je 43f640 <__getcwd+0x270> + 43f5f2: 48 8b 4c 24 18 mov 0x18(%rsp),%rcx + 43f5f7: 48 3b 08 cmp (%rax),%rcx + 43f5fa: 74 44 je 43f640 <__getcwd+0x270> + 43f5fc: 41 bd 01 00 00 00 mov $0x1,%r13d + 43f602: 4c 89 e7 mov %r12,%rdi + 43f605: 64 c7 45 00 00 00 00 movl $0x0,%fs:0x0(%rbp) + 43f60c: 00 + 43f60d: e8 fe af 02 00 callq 46a610 <__readdir> + 43f612: 48 85 c0 test %rax,%rax + 43f615: 75 c1 jne 43f5d8 <__getcwd+0x208> + 43f617: 64 8b 45 00 mov %fs:0x0(%rbp),%eax + 43f61b: 85 c0 test %eax,%eax + 43f61d: 0f 85 82 03 00 00 jne 43f9a5 <__getcwd+0x5d5> + 43f623: 45 84 ed test %r13b,%r13b + 43f626: 0f 84 8c 01 00 00 je 43f7b8 <__getcwd+0x3e8> + 43f62c: 4c 89 e7 mov %r12,%rdi + 43f62f: 45 31 ed xor %r13d,%r13d + 43f632: e8 d9 b0 02 00 callq 46a710 <__rewinddir> + 43f637: eb c9 jmp 43f602 <__getcwd+0x232> + 43f639: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43f640: 48 8d 58 13 lea 0x13(%rax),%rbx + 43f644: 8b 74 24 10 mov 0x10(%rsp),%esi + 43f648: 48 8d 4c 24 60 lea 0x60(%rsp),%rcx + 43f64d: 41 b8 00 01 00 00 mov $0x100,%r8d + 43f653: bf 01 00 00 00 mov $0x1,%edi + 43f658: 48 89 da mov %rbx,%rdx + 43f65b: e8 30 b3 02 00 callq 46a990 <__GI___fxstatat64> + 43f660: 85 c0 test %eax,%eax + 43f662: 78 9e js 43f602 <__getcwd+0x232> + 43f664: 8b 44 24 78 mov 0x78(%rsp),%eax + 43f668: 25 00 f0 00 00 and $0xf000,%eax + 43f66d: 3d 00 40 00 00 cmp $0x4000,%eax + 43f672: 75 8e jne 43f602 <__getcwd+0x232> + 43f674: 4c 3b 7c 24 60 cmp 0x60(%rsp),%r15 + 43f679: 75 87 jne 43f602 <__getcwd+0x232> + 43f67b: 48 8b 44 24 18 mov 0x18(%rsp),%rax + 43f680: 48 3b 44 24 68 cmp 0x68(%rsp),%rax + 43f685: 0f 85 77 ff ff ff jne 43f602 <__getcwd+0x232> + 43f68b: 48 89 df mov %rbx,%rdi + 43f68e: e8 bd 3f fe ff callq 423650 + 43f693: 4c 8b 44 24 38 mov 0x38(%rsp),%r8 + 43f698: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi + 43f69d: 49 89 c7 mov %rax,%r15 + 43f6a0: 49 29 f8 sub %rdi,%r8 + 43f6a3: 4d 39 c7 cmp %r8,%r15 + 43f6a6: 4c 89 44 24 18 mov %r8,0x18(%rsp) + 43f6ab: 72 64 jb 43f711 <__getcwd+0x341> + 43f6ad: 48 83 7c 24 30 00 cmpq $0x0,0x30(%rsp) + 43f6b3: 0f 85 fd 03 00 00 jne 43fab6 <__getcwd+0x6e6> + 43f6b9: 48 8b 44 24 28 mov 0x28(%rsp),%rax + 43f6be: 49 39 c7 cmp %rax,%r15 + 43f6c1: 49 0f 43 c7 cmovae %r15,%rax + 43f6c5: 49 89 c5 mov %rax,%r13 + 43f6c8: 4d 01 ed add %r13,%r13 + 43f6cb: 4c 89 ee mov %r13,%rsi + 43f6ce: e8 9d e8 fd ff callq 41df70 <__libc_realloc> + 43f6d3: 48 85 c0 test %rax,%rax + 43f6d6: 4c 8b 44 24 18 mov 0x18(%rsp),%r8 + 43f6db: 0f 84 c7 03 00 00 je 43faa8 <__getcwd+0x6d8> + 43f6e1: 48 8b 54 24 08 mov 0x8(%rsp),%rdx + 43f6e6: 48 03 54 24 28 add 0x28(%rsp),%rdx + 43f6eb: 4c 89 ef mov %r13,%rdi + 43f6ee: 48 2b 54 24 38 sub 0x38(%rsp),%rdx + 43f6f3: 4a 8d 34 00 lea (%rax,%r8,1),%rsi + 43f6f7: 48 89 44 24 08 mov %rax,0x8(%rsp) + 43f6fc: 48 29 d7 sub %rdx,%rdi + 43f6ff: 48 01 c7 add %rax,%rdi + 43f702: e8 19 c9 fe ff callq 42c020 + 43f707: 4c 89 6c 24 28 mov %r13,0x28(%rsp) + 43f70c: 48 89 44 24 38 mov %rax,0x38(%rsp) + 43f711: 48 8b 4c 24 38 mov 0x38(%rsp),%rcx + 43f716: 4c 89 fa mov %r15,%rdx + 43f719: 48 89 de mov %rbx,%rsi + 43f71c: 4c 29 f9 sub %r15,%rcx + 43f71f: 48 89 cf mov %rcx,%rdi + 43f722: e8 f9 c8 fe ff callq 42c020 + 43f727: 4c 39 74 24 48 cmp %r14,0x48(%rsp) + 43f72c: 48 89 c1 mov %rax,%rcx + 43f72f: 48 8d 40 ff lea -0x1(%rax),%rax + 43f733: c6 41 ff 2f movb $0x2f,-0x1(%rcx) + 43f737: 48 89 44 24 38 mov %rax,0x38(%rsp) + 43f73c: 75 10 jne 43f74e <__getcwd+0x37e> + 43f73e: 48 8b 54 24 58 mov 0x58(%rsp),%rdx + 43f743: 48 39 54 24 50 cmp %rdx,0x50(%rsp) + 43f748: 0f 84 dc 01 00 00 je 43f92a <__getcwd+0x55a> + 43f74e: ba 00 00 08 00 mov $0x80000,%edx + 43f753: be f0 48 4a 00 mov $0x4a48f0,%esi + 43f758: 48 63 7c 24 10 movslq 0x10(%rsp),%rdi + 43f75d: b8 01 01 00 00 mov $0x101,%eax + 43f762: 0f 05 syscall + 43f764: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 43f76a: 0f 87 05 03 00 00 ja 43fa75 <__getcwd+0x6a5> + 43f770: 85 c0 test %eax,%eax + 43f772: 89 44 24 10 mov %eax,0x10(%rsp) + 43f776: 0f 88 e8 02 00 00 js 43fa64 <__getcwd+0x694> + 43f77c: 48 8b 44 24 58 mov 0x58(%rsp),%rax + 43f781: 4d 89 f7 mov %r14,%r15 + 43f784: 8b 74 24 10 mov 0x10(%rsp),%esi + 43f788: 48 89 44 24 18 mov %rax,0x18(%rsp) + 43f78d: e9 f1 fd ff ff jmpq 43f583 <__getcwd+0x1b3> + 43f792: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43f798: 80 78 14 00 cmpb $0x0,0x14(%rax) + 43f79c: 0f 84 60 fe ff ff je 43f602 <__getcwd+0x232> + 43f7a2: 66 83 78 14 2e cmpw $0x2e,0x14(%rax) + 43f7a7: 0f 85 3b fe ff ff jne 43f5e8 <__getcwd+0x218> + 43f7ad: e9 50 fe ff ff jmpq 43f602 <__getcwd+0x232> + 43f7b2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 43f7b8: 4c 8b 74 24 30 mov 0x30(%rsp),%r14 + 43f7bd: 64 c7 45 00 02 00 00 movl $0x2,%fs:0x0(%rbp) + 43f7c4: 00 + 43f7c5: bb 02 00 00 00 mov $0x2,%ebx + 43f7ca: 45 31 ed xor %r13d,%r13d + 43f7cd: 4c 89 e7 mov %r12,%rdi + 43f7d0: e8 db ad 02 00 callq 46a5b0 <__closedir> + 43f7d5: 45 84 ed test %r13b,%r13b + 43f7d8: 74 0c je 43f7e6 <__getcwd+0x416> + 43f7da: 48 63 7c 24 10 movslq 0x10(%rsp),%rdi + 43f7df: b8 03 00 00 00 mov $0x3,%eax + 43f7e4: 0f 05 syscall + 43f7e6: 48 83 7c 24 20 00 cmpq $0x0,0x20(%rsp) + 43f7ec: 0f 84 fe 01 00 00 je 43f9f0 <__getcwd+0x620> + 43f7f2: 64 89 5d 00 mov %ebx,%fs:0x0(%rbp) + 43f7f6: 4d 85 f6 test %r14,%r14 + 43f7f9: 0f 84 31 fc ff ff je 43f430 <__getcwd+0x60> + 43f7ff: 80 7c 24 43 00 cmpb $0x0,0x43(%rsp) + 43f804: 0f 84 26 fc ff ff je 43f430 <__getcwd+0x60> + 43f80a: 48 8b 7c 24 20 mov 0x20(%rsp),%rdi + 43f80f: e8 9c e5 fd ff callq 41ddb0 <__cfree> + 43f814: e9 17 fc ff ff jmpq 43f430 <__getcwd+0x60> + 43f819: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43f820: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 43f827: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) + 43f82e: 31 c0 xor %eax,%eax + 43f830: e9 fd fb ff ff jmpq 43f432 <__getcwd+0x62> + 43f835: 0f 1f 00 nopl (%rax) + 43f838: 48 85 db test %rbx,%rbx + 43f83b: 75 13 jne 43f850 <__getcwd+0x480> + 43f83d: 4d 85 f6 test %r14,%r14 + 43f840: 75 0e jne 43f850 <__getcwd+0x480> + 43f842: 48 89 d7 mov %rdx,%rdi + 43f845: 48 63 f0 movslq %eax,%rsi + 43f848: e8 23 e7 fd ff callq 41df70 <__libc_realloc> + 43f84d: 48 89 c3 mov %rax,%rbx + 43f850: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 43f855: 48 85 db test %rbx,%rbx + 43f858: 48 0f 45 c3 cmovne %rbx,%rax + 43f85c: e9 d1 fb ff ff jmpq 43f432 <__getcwd+0x62> + 43f861: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43f868: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi + 43f86d: e8 3e e5 fd ff callq 41ddb0 <__cfree> + 43f872: 64 8b 45 00 mov %fs:0x0(%rbp),%eax + 43f876: bf 01 10 00 00 mov $0x1001,%edi + 43f87b: 89 44 24 44 mov %eax,0x44(%rsp) + 43f87f: e8 8c e1 fd ff callq 41da10 <__libc_malloc> + 43f884: 48 85 c0 test %rax,%rax + 43f887: 48 89 44 24 08 mov %rax,0x8(%rsp) + 43f88c: 0f 84 9e 01 00 00 je 43fa30 <__getcwd+0x660> + 43f892: 48 c7 44 24 28 01 10 movq $0x1001,0x28(%rsp) + 43f899: 00 00 + 43f89b: 48 c7 44 24 20 00 00 movq $0x0,0x20(%rsp) + 43f8a2: 00 00 + 43f8a4: 48 89 c3 mov %rax,%rbx + 43f8a7: e9 19 fc ff ff jmpq 43f4c5 <__getcwd+0xf5> + 43f8ac: 0f 1f 40 00 nopl 0x0(%rax) + 43f8b0: 0f 84 cb fb ff ff je 43f481 <__getcwd+0xb1> + 43f8b6: 48 c7 c5 d0 ff ff ff mov $0xffffffffffffffd0,%rbp + 43f8bd: 64 8b 45 00 mov %fs:0x0(%rbp),%eax + 43f8c1: 83 f8 24 cmp $0x24,%eax + 43f8c4: 0f 84 be fb ff ff je 43f488 <__getcwd+0xb8> + 43f8ca: 83 f8 22 cmp $0x22,%eax + 43f8cd: 0f 84 eb 00 00 00 je 43f9be <__getcwd+0x5ee> + 43f8d3: 48 85 db test %rbx,%rbx + 43f8d6: 0f 85 54 fb ff ff jne 43f430 <__getcwd+0x60> + 43f8dc: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi + 43f8e1: e8 ca e4 fd ff callq 41ddb0 <__cfree> + 43f8e6: 31 c0 xor %eax,%eax + 43f8e8: e9 45 fb ff ff jmpq 43f432 <__getcwd+0x62> + 43f8ed: 0f 1f 00 nopl (%rax) + 43f8f0: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 43f8f5: 64 c7 45 00 16 00 00 movl $0x16,%fs:0x0(%rbp) + 43f8fc: 00 + 43f8fd: 48 89 44 24 20 mov %rax,0x20(%rsp) + 43f902: e9 ef fe ff ff jmpq 43f7f6 <__getcwd+0x426> + 43f907: 48 c7 c5 d0 ff ff ff mov $0xffffffffffffffd0,%rbp + 43f90e: f7 d8 neg %eax + 43f910: 64 89 45 00 mov %eax,%fs:0x0(%rbp) + 43f914: eb ab jmp 43f8c1 <__getcwd+0x4f1> + 43f916: c7 44 24 10 9c ff ff movl $0xffffff9c,0x10(%rsp) + 43f91d: ff + 43f91e: 45 31 ed xor %r13d,%r13d + 43f921: 64 8b 5d 00 mov %fs:0x0(%rbp),%ebx + 43f925: e9 ab fe ff ff jmpq 43f7d5 <__getcwd+0x405> + 43f92a: 4c 89 e7 mov %r12,%rdi + 43f92d: 4c 8b 74 24 30 mov 0x30(%rsp),%r14 + 43f932: e8 79 ac 02 00 callq 46a5b0 <__closedir> + 43f937: 85 c0 test %eax,%eax + 43f939: 0f 85 61 01 00 00 jne 43faa0 <__getcwd+0x6d0> + 43f93f: 48 8b 5c 24 08 mov 0x8(%rsp),%rbx + 43f944: 48 03 5c 24 28 add 0x28(%rsp),%rbx + 43f949: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 43f94e: 48 8b 54 24 28 mov 0x28(%rsp),%rdx + 43f953: 48 8d 44 10 ff lea -0x1(%rax,%rdx,1),%rax + 43f958: 48 3b 44 24 38 cmp 0x38(%rsp),%rax + 43f95d: 0f 84 f2 00 00 00 je 43fa55 <__getcwd+0x685> + 43f963: 48 8b 44 24 38 mov 0x38(%rsp),%rax + 43f968: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi + 43f96d: 48 29 c3 sub %rax,%rbx + 43f970: 48 89 c6 mov %rax,%rsi + 43f973: 48 89 da mov %rbx,%rdx + 43f976: e8 85 09 fc ff callq 400300 <__rela_iplt_end+0x38> + 43f97b: 4d 85 f6 test %r14,%r14 + 43f97e: 0f 84 ba 00 00 00 je 43fa3e <__getcwd+0x66e> + 43f984: 8b 54 24 44 mov 0x44(%rsp),%edx + 43f988: 48 8b 44 24 20 mov 0x20(%rsp),%rax + 43f98d: 64 89 55 00 mov %edx,%fs:0x0(%rbp) + 43f991: 48 8b 54 24 08 mov 0x8(%rsp),%rdx + 43f996: 48 85 c0 test %rax,%rax + 43f999: 48 0f 45 d0 cmovne %rax,%rdx + 43f99d: 48 89 d0 mov %rdx,%rax + 43f9a0: e9 8d fa ff ff jmpq 43f432 <__getcwd+0x62> + 43f9a5: 4c 8b 74 24 30 mov 0x30(%rsp),%r14 + 43f9aa: 89 c3 mov %eax,%ebx + 43f9ac: e9 19 fe ff ff jmpq 43f7ca <__getcwd+0x3fa> + 43f9b1: 89 c3 mov %eax,%ebx + 43f9b3: f7 db neg %ebx + 43f9b5: 64 89 5d 00 mov %ebx,%fs:0x0(%rbp) + 43f9b9: e9 28 fe ff ff jmpq 43f7e6 <__getcwd+0x416> + 43f9be: 48 85 db test %rbx,%rbx + 43f9c1: 0f 85 0c ff ff ff jne 43f8d3 <__getcwd+0x503> + 43f9c7: 4d 85 f6 test %r14,%r14 + 43f9ca: 0f 85 03 ff ff ff jne 43f8d3 <__getcwd+0x503> + 43f9d0: b9 50 49 4a 00 mov $0x4a4950,%ecx + 43f9d5: ba 79 00 00 00 mov $0x79,%edx + 43f9da: be f8 48 4a 00 mov $0x4a48f8,%esi + 43f9df: bf 20 49 4a 00 mov $0x4a4920,%edi + 43f9e4: e8 57 1d fc ff callq 401740 <__assert_fail> + 43f9e9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 43f9f0: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi + 43f9f5: e8 b6 e3 fd ff callq 41ddb0 <__cfree> + 43f9fa: e9 f3 fd ff ff jmpq 43f7f2 <__getcwd+0x422> + 43f9ff: 4c 8b 74 24 30 mov 0x30(%rsp),%r14 + 43fa04: 41 bd 01 00 00 00 mov $0x1,%r13d + 43fa0a: e9 12 ff ff ff jmpq 43f921 <__getcwd+0x551> + 43fa0f: 4d 85 e4 test %r12,%r12 + 43fa12: 4c 8b 74 24 30 mov 0x30(%rsp),%r14 + 43fa17: 64 8b 5d 00 mov %fs:0x0(%rbp),%ebx + 43fa1b: 0f 84 b9 fd ff ff je 43f7da <__getcwd+0x40a> + 43fa21: 41 bd 01 00 00 00 mov $0x1,%r13d + 43fa27: e9 a1 fd ff ff jmpq 43f7cd <__getcwd+0x3fd> + 43fa2c: 0f 1f 40 00 nopl 0x0(%rax) + 43fa30: 48 c7 44 24 20 00 00 movq $0x0,0x20(%rsp) + 43fa37: 00 00 + 43fa39: e9 b8 fd ff ff jmpq 43f7f6 <__getcwd+0x426> + 43fa3e: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi + 43fa43: 48 89 de mov %rbx,%rsi + 43fa46: e8 25 e5 fd ff callq 41df70 <__libc_realloc> + 43fa4b: 48 89 44 24 20 mov %rax,0x20(%rsp) + 43fa50: e9 2f ff ff ff jmpq 43f984 <__getcwd+0x5b4> + 43fa55: 48 83 6c 24 38 01 subq $0x1,0x38(%rsp) + 43fa5b: c6 40 ff 2f movb $0x2f,-0x1(%rax) + 43fa5f: e9 ff fe ff ff jmpq 43f963 <__getcwd+0x593> + 43fa64: 4c 8b 74 24 30 mov 0x30(%rsp),%r14 + 43fa69: 64 8b 5d 00 mov %fs:0x0(%rbp),%ebx + 43fa6d: 45 31 ed xor %r13d,%r13d + 43fa70: e9 58 fd ff ff jmpq 43f7cd <__getcwd+0x3fd> + 43fa75: 89 c3 mov %eax,%ebx + 43fa77: 4c 8b 74 24 30 mov 0x30(%rsp),%r14 + 43fa7c: c7 44 24 10 ff ff ff movl $0xffffffff,0x10(%rsp) + 43fa83: ff + 43fa84: f7 db neg %ebx + 43fa86: 45 31 ed xor %r13d,%r13d + 43fa89: 64 89 5d 00 mov %ebx,%fs:0x0(%rbp) + 43fa8d: e9 3b fd ff ff jmpq 43f7cd <__getcwd+0x3fd> + 43fa92: 64 8b 5d 00 mov %fs:0x0(%rbp),%ebx + 43fa96: e9 4b fd ff ff jmpq 43f7e6 <__getcwd+0x416> + 43fa9b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43faa0: 45 31 ed xor %r13d,%r13d + 43faa3: e9 79 fe ff ff jmpq 43f921 <__getcwd+0x551> + 43faa8: 4c 8b 74 24 30 mov 0x30(%rsp),%r14 + 43faad: 64 8b 5d 00 mov %fs:0x0(%rbp),%ebx + 43fab1: e9 14 fd ff ff jmpq 43f7ca <__getcwd+0x3fa> + 43fab6: 4c 8b 74 24 30 mov 0x30(%rsp),%r14 + 43fabb: 64 c7 45 00 22 00 00 movl $0x22,%fs:0x0(%rbp) + 43fac2: 00 + 43fac3: bb 22 00 00 00 mov $0x22,%ebx + 43fac8: e9 fd fc ff ff jmpq 43f7ca <__getcwd+0x3fa> + 43facd: 0f 1f 00 nopl (%rax) + +000000000043fad0 <__getrlimit>: + 43fad0: b8 61 00 00 00 mov $0x61,%eax + 43fad5: 0f 05 syscall + 43fad7: 48 3d 01 f0 ff ff cmp $0xfffffffffffff001,%rax + 43fadd: 0f 83 6d 46 00 00 jae 444150 <__syscall_error> + 43fae3: c3 retq + 43fae4: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43faeb: 00 00 00 + 43faee: 66 90 xchg %ax,%ax + +000000000043faf0 <__sbrk>: + 43faf0: 55 push %rbp + 43faf1: 53 push %rbx + 43faf2: 48 89 fd mov %rdi,%rbp + 43faf5: 48 83 ec 08 sub $0x8,%rsp + 43faf9: 48 8b 1d 70 ce 28 00 mov 0x28ce70(%rip),%rbx # 6cc970 <__curbrk> + 43fb00: 48 85 db test %rbx,%rbx + 43fb03: 74 43 je 43fb48 <__sbrk+0x58> + 43fb05: 8b 05 f5 bb 28 00 mov 0x28bbf5(%rip),%eax # 6cb700 <__libc_multiple_libcs> + 43fb0b: 85 c0 test %eax,%eax + 43fb0d: 75 39 jne 43fb48 <__sbrk+0x58> + 43fb0f: 48 83 fd 00 cmp $0x0,%rbp + 43fb13: 74 24 je 43fb39 <__sbrk+0x49> + 43fb15: 7e 69 jle 43fb80 <__sbrk+0x90> + 43fb17: 48 89 d8 mov %rbx,%rax + 43fb1a: 48 01 e8 add %rbp,%rax + 43fb1d: 0f 92 c0 setb %al + 43fb20: 84 c0 test %al,%al + 43fb22: 74 3c je 43fb60 <__sbrk+0x70> + 43fb24: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 43fb2b: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) + 43fb32: 48 c7 c3 ff ff ff ff mov $0xffffffffffffffff,%rbx + 43fb39: 48 83 c4 08 add $0x8,%rsp + 43fb3d: 48 89 d8 mov %rbx,%rax + 43fb40: 5b pop %rbx + 43fb41: 5d pop %rbp + 43fb42: c3 retq + 43fb43: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 43fb48: 31 ff xor %edi,%edi + 43fb4a: e8 f1 af 02 00 callq 46ab40 <__brk> + 43fb4f: 85 c0 test %eax,%eax + 43fb51: 48 8b 1d 18 ce 28 00 mov 0x28ce18(%rip),%rbx # 6cc970 <__curbrk> + 43fb58: 79 b5 jns 43fb0f <__sbrk+0x1f> + 43fb5a: eb d6 jmp 43fb32 <__sbrk+0x42> + 43fb5c: 0f 1f 40 00 nopl 0x0(%rax) + 43fb60: 48 8d 3c 2b lea (%rbx,%rbp,1),%rdi + 43fb64: e8 d7 af 02 00 callq 46ab40 <__brk> + 43fb69: 85 c0 test %eax,%eax + 43fb6b: 78 c5 js 43fb32 <__sbrk+0x42> + 43fb6d: 48 83 c4 08 add $0x8,%rsp + 43fb71: 48 89 d8 mov %rbx,%rax + 43fb74: 5b pop %rbx + 43fb75: 5d pop %rbp + 43fb76: c3 retq + 43fb77: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 43fb7e: 00 00 + 43fb80: 48 89 e8 mov %rbp,%rax + 43fb83: 48 f7 d8 neg %rax + 43fb86: 48 39 c3 cmp %rax,%rbx + 43fb89: 0f 92 c0 setb %al + 43fb8c: eb 92 jmp 43fb20 <__sbrk+0x30> + 43fb8e: 66 90 xchg %ax,%ax + +000000000043fb90 <__getpagesize>: + 43fb90: 48 8b 05 e9 b5 28 00 mov 0x28b5e9(%rip),%rax # 6cb180 <_dl_pagesize> + 43fb97: 48 85 c0 test %rax,%rax + 43fb9a: 74 02 je 43fb9e <__getpagesize+0xe> + 43fb9c: f3 c3 repz retq + 43fb9e: 50 push %rax + 43fb9f: b9 90 49 4a 00 mov $0x4a4990,%ecx + 43fba4: ba 1c 00 00 00 mov $0x1c,%edx + 43fba9: be 60 49 4a 00 mov $0x4a4960,%esi + 43fbae: bf 9e 49 4a 00 mov $0x4a499e,%edi + 43fbb3: e8 88 1b fc ff callq 401740 <__assert_fail> + 43fbb8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 43fbbf: 00 + +000000000043fbc0 <__getdtablesize>: + 43fbc0: 48 83 ec 18 sub $0x18,%rsp + 43fbc4: bf 07 00 00 00 mov $0x7,%edi + 43fbc9: 48 89 e6 mov %rsp,%rsi + 43fbcc: e8 ff fe ff ff callq 43fad0 <__getrlimit> + 43fbd1: ba 00 01 00 00 mov $0x100,%edx + 43fbd6: 85 c0 test %eax,%eax + 43fbd8: 0f 49 14 24 cmovns (%rsp),%edx + 43fbdc: 48 83 c4 18 add $0x18,%rsp + 43fbe0: 89 d0 mov %edx,%eax + 43fbe2: c3 retq + 43fbe3: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43fbea: 00 00 00 + 43fbed: 0f 1f 00 nopl (%rax) + +000000000043fbf0 <__mmap>: + 43fbf0: 48 85 ff test %rdi,%rdi + 43fbf3: 41 57 push %r15 + 43fbf5: 4d 89 cf mov %r9,%r15 + 43fbf8: 41 56 push %r14 + 43fbfa: 41 89 ce mov %ecx,%r14d + 43fbfd: 41 55 push %r13 + 43fbff: 49 89 f5 mov %rsi,%r13 + 43fc02: 41 54 push %r12 + 43fc04: 49 89 fc mov %rdi,%r12 + 43fc07: 55 push %rbp + 43fc08: 53 push %rbx + 43fc09: 74 35 je 43fc40 <__mmap+0x50> + 43fc0b: 49 63 e8 movslq %r8d,%rbp + 43fc0e: 48 63 da movslq %edx,%rbx + 43fc11: 4d 89 f9 mov %r15,%r9 + 43fc14: 49 89 e8 mov %rbp,%r8 + 43fc17: 4d 63 d6 movslq %r14d,%r10 + 43fc1a: 48 89 da mov %rbx,%rdx + 43fc1d: 4c 89 ee mov %r13,%rsi + 43fc20: 4c 89 e7 mov %r12,%rdi + 43fc23: b8 09 00 00 00 mov $0x9,%eax + 43fc28: 0f 05 syscall + 43fc2a: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 43fc30: 77 4e ja 43fc80 <__mmap+0x90> + 43fc32: 5b pop %rbx + 43fc33: 5d pop %rbp + 43fc34: 41 5c pop %r12 + 43fc36: 41 5d pop %r13 + 43fc38: 41 5e pop %r14 + 43fc3a: 41 5f pop %r15 + 43fc3c: c3 retq + 43fc3d: 0f 1f 00 nopl (%rax) + 43fc40: f6 c2 04 test $0x4,%dl + 43fc43: 74 c6 je 43fc0b <__mmap+0x1b> + 43fc45: f6 05 76 ca 28 00 01 testb $0x1,0x28ca76(%rip) # 6cc6c2 <_dl_x86_cpu_features+0x42> + 43fc4c: 49 63 e8 movslq %r8d,%rbp + 43fc4f: 48 63 da movslq %edx,%rbx + 43fc52: 74 bd je 43fc11 <__mmap+0x21> + 43fc54: 41 89 ca mov %ecx,%r10d + 43fc57: 49 89 e8 mov %rbp,%r8 + 43fc5a: 48 89 da mov %rbx,%rdx + 43fc5d: 41 83 ca 40 or $0x40,%r10d + 43fc61: 31 ff xor %edi,%edi + 43fc63: b8 09 00 00 00 mov $0x9,%eax + 43fc68: 4d 63 d2 movslq %r10d,%r10 + 43fc6b: 0f 05 syscall + 43fc6d: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 43fc73: 77 20 ja 43fc95 <__mmap+0xa5> + 43fc75: 48 83 f8 ff cmp $0xffffffffffffffff,%rax + 43fc79: 75 b7 jne 43fc32 <__mmap+0x42> + 43fc7b: eb 94 jmp 43fc11 <__mmap+0x21> + 43fc7d: 0f 1f 00 nopl (%rax) + 43fc80: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx + 43fc87: f7 d8 neg %eax + 43fc89: 64 89 02 mov %eax,%fs:(%rdx) + 43fc8c: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax + 43fc93: eb 9d jmp 43fc32 <__mmap+0x42> + 43fc95: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx + 43fc9c: f7 d8 neg %eax + 43fc9e: 64 89 02 mov %eax,%fs:(%rdx) + 43fca1: e9 6b ff ff ff jmpq 43fc11 <__mmap+0x21> + 43fca6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43fcad: 00 00 00 + +000000000043fcb0 <__munmap>: + 43fcb0: b8 0b 00 00 00 mov $0xb,%eax + 43fcb5: 0f 05 syscall + 43fcb7: 48 3d 01 f0 ff ff cmp $0xfffffffffffff001,%rax + 43fcbd: 0f 83 8d 44 00 00 jae 444150 <__syscall_error> + 43fcc3: c3 retq + 43fcc4: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43fccb: 00 00 00 + 43fcce: 66 90 xchg %ax,%ax + +000000000043fcd0 <__mprotect>: + 43fcd0: b8 0a 00 00 00 mov $0xa,%eax + 43fcd5: 0f 05 syscall + 43fcd7: 48 3d 01 f0 ff ff cmp $0xfffffffffffff001,%rax + 43fcdd: 0f 83 6d 44 00 00 jae 444150 <__syscall_error> + 43fce3: c3 retq + 43fce4: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43fceb: 00 00 00 + 43fcee: 66 90 xchg %ax,%ax + +000000000043fcf0 <__madvise>: + 43fcf0: b8 1c 00 00 00 mov $0x1c,%eax + 43fcf5: 0f 05 syscall + 43fcf7: 48 3d 01 f0 ff ff cmp $0xfffffffffffff001,%rax + 43fcfd: 0f 83 4d 44 00 00 jae 444150 <__syscall_error> + 43fd03: c3 retq + 43fd04: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43fd0b: 00 00 00 + 43fd0e: 66 90 xchg %ax,%ax + +000000000043fd10 : + 43fd10: 41 54 push %r12 + 43fd12: 55 push %rbp + 43fd13: 48 89 f0 mov %rsi,%rax + 43fd16: 53 push %rbx + 43fd17: 48 83 7f 08 00 cmpq $0x0,0x8(%rdi) + 43fd1c: 74 62 je 43fd80 + 43fd1e: 48 89 fb mov %rdi,%rbx + 43fd21: 31 f6 xor %esi,%esi + 43fd23: 41 89 d4 mov %edx,%r12d + 43fd26: 48 89 c5 mov %rax,%rbp + 43fd29: ff d0 callq *%rax + 43fd2b: 48 8b 7b 08 mov 0x8(%rbx),%rdi + 43fd2f: 48 85 ff test %rdi,%rdi + 43fd32: 74 0d je 43fd41 + 43fd34: 41 8d 54 24 01 lea 0x1(%r12),%edx + 43fd39: 48 89 ee mov %rbp,%rsi + 43fd3c: e8 cf ff ff ff callq 43fd10 + 43fd41: 48 89 df mov %rbx,%rdi + 43fd44: 44 89 e2 mov %r12d,%edx + 43fd47: be 01 00 00 00 mov $0x1,%esi + 43fd4c: ff d5 callq *%rbp + 43fd4e: 48 8b 7b 10 mov 0x10(%rbx),%rdi + 43fd52: 48 85 ff test %rdi,%rdi + 43fd55: 74 0d je 43fd64 + 43fd57: 41 8d 54 24 01 lea 0x1(%r12),%edx + 43fd5c: 48 89 ee mov %rbp,%rsi + 43fd5f: e8 ac ff ff ff callq 43fd10 + 43fd64: 44 89 e2 mov %r12d,%edx + 43fd67: 48 89 df mov %rbx,%rdi + 43fd6a: 48 89 e8 mov %rbp,%rax + 43fd6d: 5b pop %rbx + 43fd6e: 5d pop %rbp + 43fd6f: 41 5c pop %r12 + 43fd71: be 02 00 00 00 mov $0x2,%esi + 43fd76: ff e0 jmpq *%rax + 43fd78: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 43fd7f: 00 + 43fd80: 48 83 7f 10 00 cmpq $0x0,0x10(%rdi) + 43fd85: 75 97 jne 43fd1e + 43fd87: 5b pop %rbx + 43fd88: 5d pop %rbp + 43fd89: 41 5c pop %r12 + 43fd8b: be 03 00 00 00 mov $0x3,%esi + 43fd90: ff e0 jmpq *%rax + 43fd92: 0f 1f 40 00 nopl 0x0(%rax) + 43fd96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 43fd9d: 00 00 00 + +000000000043fda0 : + 43fda0: 41 57 push %r15 + 43fda2: 41 56 push %r14 + 43fda4: 41 55 push %r13 + 43fda6: 41 54 push %r12 + 43fda8: 49 89 fc mov %rdi,%r12 + 43fdab: 55 push %rbp + 43fdac: 53 push %rbx + 43fdad: 48 89 f3 mov %rsi,%rbx + 43fdb0: 48 83 ec 18 sub $0x18,%rsp + 43fdb4: 48 8b 6f 08 mov 0x8(%rdi),%rbp + 43fdb8: 48 85 ed test %rbp,%rbp + 43fdbb: 0f 84 0b 02 00 00 je 43ffcc + 43fdc1: 4c 8b 6d 08 mov 0x8(%rbp),%r13 + 43fdc5: 4d 85 ed test %r13,%r13 + 43fdc8: 0f 84 c9 00 00 00 je 43fe97 + 43fdce: 4d 8b 75 08 mov 0x8(%r13),%r14 + 43fdd2: 4d 85 f6 test %r14,%r14 + 43fdd5: 74 2c je 43fe03 + 43fdd7: 49 8b 7e 08 mov 0x8(%r14),%rdi + 43fddb: 48 85 ff test %rdi,%rdi + 43fdde: 74 05 je 43fde5 + 43fde0: e8 bb ff ff ff callq 43fda0 + 43fde5: 49 8b 7e 10 mov 0x10(%r14),%rdi + 43fde9: 48 85 ff test %rdi,%rdi + 43fdec: 74 08 je 43fdf6 + 43fdee: 48 89 de mov %rbx,%rsi + 43fdf1: e8 aa ff ff ff callq 43fda0 + 43fdf6: 49 8b 3e mov (%r14),%rdi + 43fdf9: ff d3 callq *%rbx + 43fdfb: 4c 89 f7 mov %r14,%rdi + 43fdfe: e8 ad df fd ff callq 41ddb0 <__cfree> + 43fe03: 4d 8b 75 10 mov 0x10(%r13),%r14 + 43fe07: 4d 85 f6 test %r14,%r14 + 43fe0a: 74 7d je 43fe89 + 43fe0c: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 43fe10: 4d 85 ff test %r15,%r15 + 43fe13: 74 2f je 43fe44 + 43fe15: 49 8b 7f 08 mov 0x8(%r15),%rdi + 43fe19: 48 85 ff test %rdi,%rdi + 43fe1c: 74 08 je 43fe26 + 43fe1e: 48 89 de mov %rbx,%rsi + 43fe21: e8 7a ff ff ff callq 43fda0 + 43fe26: 49 8b 7f 10 mov 0x10(%r15),%rdi + 43fe2a: 48 85 ff test %rdi,%rdi + 43fe2d: 74 08 je 43fe37 + 43fe2f: 48 89 de mov %rbx,%rsi + 43fe32: e8 69 ff ff ff callq 43fda0 + 43fe37: 49 8b 3f mov (%r15),%rdi + 43fe3a: ff d3 callq *%rbx + 43fe3c: 4c 89 ff mov %r15,%rdi + 43fe3f: e8 6c df fd ff callq 41ddb0 <__cfree> + 43fe44: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 43fe48: 4d 85 ff test %r15,%r15 + 43fe4b: 74 2f je 43fe7c + 43fe4d: 49 8b 7f 08 mov 0x8(%r15),%rdi + 43fe51: 48 85 ff test %rdi,%rdi + 43fe54: 74 08 je 43fe5e + 43fe56: 48 89 de mov %rbx,%rsi + 43fe59: e8 42 ff ff ff callq 43fda0 + 43fe5e: 49 8b 7f 10 mov 0x10(%r15),%rdi + 43fe62: 48 85 ff test %rdi,%rdi + 43fe65: 74 08 je 43fe6f + 43fe67: 48 89 de mov %rbx,%rsi + 43fe6a: e8 31 ff ff ff callq 43fda0 + 43fe6f: 49 8b 3f mov (%r15),%rdi + 43fe72: ff d3 callq *%rbx + 43fe74: 4c 89 ff mov %r15,%rdi + 43fe77: e8 34 df fd ff callq 41ddb0 <__cfree> + 43fe7c: 49 8b 3e mov (%r14),%rdi + 43fe7f: ff d3 callq *%rbx + 43fe81: 4c 89 f7 mov %r14,%rdi + 43fe84: e8 27 df fd ff callq 41ddb0 <__cfree> + 43fe89: 49 8b 7d 00 mov 0x0(%r13),%rdi + 43fe8d: ff d3 callq *%rbx + 43fe8f: 4c 89 ef mov %r13,%rdi + 43fe92: e8 19 df fd ff callq 41ddb0 <__cfree> + 43fe97: 4c 8b 6d 10 mov 0x10(%rbp),%r13 + 43fe9b: 4d 85 ed test %r13,%r13 + 43fe9e: 0f 84 1a 01 00 00 je 43ffbe + 43fea4: 4d 8b 75 08 mov 0x8(%r13),%r14 + 43fea8: 4d 85 f6 test %r14,%r14 + 43feab: 74 7d je 43ff2a + 43fead: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 43feb1: 4d 85 ff test %r15,%r15 + 43feb4: 74 2f je 43fee5 + 43feb6: 49 8b 7f 08 mov 0x8(%r15),%rdi + 43feba: 48 85 ff test %rdi,%rdi + 43febd: 74 08 je 43fec7 + 43febf: 48 89 de mov %rbx,%rsi + 43fec2: e8 d9 fe ff ff callq 43fda0 + 43fec7: 49 8b 7f 10 mov 0x10(%r15),%rdi + 43fecb: 48 85 ff test %rdi,%rdi + 43fece: 74 08 je 43fed8 + 43fed0: 48 89 de mov %rbx,%rsi + 43fed3: e8 c8 fe ff ff callq 43fda0 + 43fed8: 49 8b 3f mov (%r15),%rdi + 43fedb: ff d3 callq *%rbx + 43fedd: 4c 89 ff mov %r15,%rdi + 43fee0: e8 cb de fd ff callq 41ddb0 <__cfree> + 43fee5: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 43fee9: 4d 85 ff test %r15,%r15 + 43feec: 74 2f je 43ff1d + 43feee: 49 8b 7f 08 mov 0x8(%r15),%rdi + 43fef2: 48 85 ff test %rdi,%rdi + 43fef5: 74 08 je 43feff + 43fef7: 48 89 de mov %rbx,%rsi + 43fefa: e8 a1 fe ff ff callq 43fda0 + 43feff: 49 8b 7f 10 mov 0x10(%r15),%rdi + 43ff03: 48 85 ff test %rdi,%rdi + 43ff06: 74 08 je 43ff10 + 43ff08: 48 89 de mov %rbx,%rsi + 43ff0b: e8 90 fe ff ff callq 43fda0 + 43ff10: 49 8b 3f mov (%r15),%rdi + 43ff13: ff d3 callq *%rbx + 43ff15: 4c 89 ff mov %r15,%rdi + 43ff18: e8 93 de fd ff callq 41ddb0 <__cfree> + 43ff1d: 49 8b 3e mov (%r14),%rdi + 43ff20: ff d3 callq *%rbx + 43ff22: 4c 89 f7 mov %r14,%rdi + 43ff25: e8 86 de fd ff callq 41ddb0 <__cfree> + 43ff2a: 4d 8b 75 10 mov 0x10(%r13),%r14 + 43ff2e: 4d 85 f6 test %r14,%r14 + 43ff31: 74 7d je 43ffb0 + 43ff33: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 43ff37: 4d 85 ff test %r15,%r15 + 43ff3a: 74 2f je 43ff6b + 43ff3c: 49 8b 7f 08 mov 0x8(%r15),%rdi + 43ff40: 48 85 ff test %rdi,%rdi + 43ff43: 74 08 je 43ff4d + 43ff45: 48 89 de mov %rbx,%rsi + 43ff48: e8 53 fe ff ff callq 43fda0 + 43ff4d: 49 8b 7f 10 mov 0x10(%r15),%rdi + 43ff51: 48 85 ff test %rdi,%rdi + 43ff54: 74 08 je 43ff5e + 43ff56: 48 89 de mov %rbx,%rsi + 43ff59: e8 42 fe ff ff callq 43fda0 + 43ff5e: 49 8b 3f mov (%r15),%rdi + 43ff61: ff d3 callq *%rbx + 43ff63: 4c 89 ff mov %r15,%rdi + 43ff66: e8 45 de fd ff callq 41ddb0 <__cfree> + 43ff6b: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 43ff6f: 4d 85 ff test %r15,%r15 + 43ff72: 74 2f je 43ffa3 + 43ff74: 49 8b 7f 08 mov 0x8(%r15),%rdi + 43ff78: 48 85 ff test %rdi,%rdi + 43ff7b: 74 08 je 43ff85 + 43ff7d: 48 89 de mov %rbx,%rsi + 43ff80: e8 1b fe ff ff callq 43fda0 + 43ff85: 49 8b 7f 10 mov 0x10(%r15),%rdi + 43ff89: 48 85 ff test %rdi,%rdi + 43ff8c: 74 08 je 43ff96 + 43ff8e: 48 89 de mov %rbx,%rsi + 43ff91: e8 0a fe ff ff callq 43fda0 + 43ff96: 49 8b 3f mov (%r15),%rdi + 43ff99: ff d3 callq *%rbx + 43ff9b: 4c 89 ff mov %r15,%rdi + 43ff9e: e8 0d de fd ff callq 41ddb0 <__cfree> + 43ffa3: 49 8b 3e mov (%r14),%rdi + 43ffa6: ff d3 callq *%rbx + 43ffa8: 4c 89 f7 mov %r14,%rdi + 43ffab: e8 00 de fd ff callq 41ddb0 <__cfree> + 43ffb0: 49 8b 7d 00 mov 0x0(%r13),%rdi + 43ffb4: ff d3 callq *%rbx + 43ffb6: 4c 89 ef mov %r13,%rdi + 43ffb9: e8 f2 dd fd ff callq 41ddb0 <__cfree> + 43ffbe: 48 8b 7d 00 mov 0x0(%rbp),%rdi + 43ffc2: ff d3 callq *%rbx + 43ffc4: 48 89 ef mov %rbp,%rdi + 43ffc7: e8 e4 dd fd ff callq 41ddb0 <__cfree> + 43ffcc: 49 8b 6c 24 10 mov 0x10(%r12),%rbp + 43ffd1: 48 85 ed test %rbp,%rbp + 43ffd4: 0f 84 a5 02 00 00 je 44027f + 43ffda: 4c 8b 6d 08 mov 0x8(%rbp),%r13 + 43ffde: 4d 85 ed test %r13,%r13 + 43ffe1: 0f 84 1a 01 00 00 je 440101 + 43ffe7: 4d 8b 75 08 mov 0x8(%r13),%r14 + 43ffeb: 4d 85 f6 test %r14,%r14 + 43ffee: 74 7d je 44006d + 43fff0: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 43fff4: 4d 85 ff test %r15,%r15 + 43fff7: 74 2f je 440028 + 43fff9: 49 8b 7f 08 mov 0x8(%r15),%rdi + 43fffd: 48 85 ff test %rdi,%rdi + 440000: 74 08 je 44000a + 440002: 48 89 de mov %rbx,%rsi + 440005: e8 96 fd ff ff callq 43fda0 + 44000a: 49 8b 7f 10 mov 0x10(%r15),%rdi + 44000e: 48 85 ff test %rdi,%rdi + 440011: 74 08 je 44001b + 440013: 48 89 de mov %rbx,%rsi + 440016: e8 85 fd ff ff callq 43fda0 + 44001b: 49 8b 3f mov (%r15),%rdi + 44001e: ff d3 callq *%rbx + 440020: 4c 89 ff mov %r15,%rdi + 440023: e8 88 dd fd ff callq 41ddb0 <__cfree> + 440028: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 44002c: 4d 85 ff test %r15,%r15 + 44002f: 74 2f je 440060 + 440031: 49 8b 7f 08 mov 0x8(%r15),%rdi + 440035: 48 85 ff test %rdi,%rdi + 440038: 74 08 je 440042 + 44003a: 48 89 de mov %rbx,%rsi + 44003d: e8 5e fd ff ff callq 43fda0 + 440042: 49 8b 7f 10 mov 0x10(%r15),%rdi + 440046: 48 85 ff test %rdi,%rdi + 440049: 74 08 je 440053 + 44004b: 48 89 de mov %rbx,%rsi + 44004e: e8 4d fd ff ff callq 43fda0 + 440053: 49 8b 3f mov (%r15),%rdi + 440056: ff d3 callq *%rbx + 440058: 4c 89 ff mov %r15,%rdi + 44005b: e8 50 dd fd ff callq 41ddb0 <__cfree> + 440060: 49 8b 3e mov (%r14),%rdi + 440063: ff d3 callq *%rbx + 440065: 4c 89 f7 mov %r14,%rdi + 440068: e8 43 dd fd ff callq 41ddb0 <__cfree> + 44006d: 4d 8b 75 10 mov 0x10(%r13),%r14 + 440071: 4d 85 f6 test %r14,%r14 + 440074: 74 7d je 4400f3 + 440076: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 44007a: 4d 85 ff test %r15,%r15 + 44007d: 74 2f je 4400ae + 44007f: 49 8b 7f 08 mov 0x8(%r15),%rdi + 440083: 48 85 ff test %rdi,%rdi + 440086: 74 08 je 440090 + 440088: 48 89 de mov %rbx,%rsi + 44008b: e8 10 fd ff ff callq 43fda0 + 440090: 49 8b 7f 10 mov 0x10(%r15),%rdi + 440094: 48 85 ff test %rdi,%rdi + 440097: 74 08 je 4400a1 + 440099: 48 89 de mov %rbx,%rsi + 44009c: e8 ff fc ff ff callq 43fda0 + 4400a1: 49 8b 3f mov (%r15),%rdi + 4400a4: ff d3 callq *%rbx + 4400a6: 4c 89 ff mov %r15,%rdi + 4400a9: e8 02 dd fd ff callq 41ddb0 <__cfree> + 4400ae: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 4400b2: 4d 85 ff test %r15,%r15 + 4400b5: 74 2f je 4400e6 + 4400b7: 49 8b 7f 08 mov 0x8(%r15),%rdi + 4400bb: 48 85 ff test %rdi,%rdi + 4400be: 74 08 je 4400c8 + 4400c0: 48 89 de mov %rbx,%rsi + 4400c3: e8 d8 fc ff ff callq 43fda0 + 4400c8: 49 8b 7f 10 mov 0x10(%r15),%rdi + 4400cc: 48 85 ff test %rdi,%rdi + 4400cf: 74 08 je 4400d9 + 4400d1: 48 89 de mov %rbx,%rsi + 4400d4: e8 c7 fc ff ff callq 43fda0 + 4400d9: 49 8b 3f mov (%r15),%rdi + 4400dc: ff d3 callq *%rbx + 4400de: 4c 89 ff mov %r15,%rdi + 4400e1: e8 ca dc fd ff callq 41ddb0 <__cfree> + 4400e6: 49 8b 3e mov (%r14),%rdi + 4400e9: ff d3 callq *%rbx + 4400eb: 4c 89 f7 mov %r14,%rdi + 4400ee: e8 bd dc fd ff callq 41ddb0 <__cfree> + 4400f3: 49 8b 7d 00 mov 0x0(%r13),%rdi + 4400f7: ff d3 callq *%rbx + 4400f9: 4c 89 ef mov %r13,%rdi + 4400fc: e8 af dc fd ff callq 41ddb0 <__cfree> + 440101: 4c 8b 6d 10 mov 0x10(%rbp),%r13 + 440105: 4d 85 ed test %r13,%r13 + 440108: 0f 84 63 01 00 00 je 440271 + 44010e: 4d 8b 75 08 mov 0x8(%r13),%r14 + 440112: 4d 85 f6 test %r14,%r14 + 440115: 74 7d je 440194 + 440117: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 44011b: 4d 85 ff test %r15,%r15 + 44011e: 74 2f je 44014f + 440120: 49 8b 7f 08 mov 0x8(%r15),%rdi + 440124: 48 85 ff test %rdi,%rdi + 440127: 74 08 je 440131 + 440129: 48 89 de mov %rbx,%rsi + 44012c: e8 6f fc ff ff callq 43fda0 + 440131: 49 8b 7f 10 mov 0x10(%r15),%rdi + 440135: 48 85 ff test %rdi,%rdi + 440138: 74 08 je 440142 + 44013a: 48 89 de mov %rbx,%rsi + 44013d: e8 5e fc ff ff callq 43fda0 + 440142: 49 8b 3f mov (%r15),%rdi + 440145: ff d3 callq *%rbx + 440147: 4c 89 ff mov %r15,%rdi + 44014a: e8 61 dc fd ff callq 41ddb0 <__cfree> + 44014f: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 440153: 4d 85 ff test %r15,%r15 + 440156: 74 2f je 440187 + 440158: 49 8b 7f 08 mov 0x8(%r15),%rdi + 44015c: 48 85 ff test %rdi,%rdi + 44015f: 74 08 je 440169 + 440161: 48 89 de mov %rbx,%rsi + 440164: e8 37 fc ff ff callq 43fda0 + 440169: 49 8b 7f 10 mov 0x10(%r15),%rdi + 44016d: 48 85 ff test %rdi,%rdi + 440170: 74 08 je 44017a + 440172: 48 89 de mov %rbx,%rsi + 440175: e8 26 fc ff ff callq 43fda0 + 44017a: 49 8b 3f mov (%r15),%rdi + 44017d: ff d3 callq *%rbx + 44017f: 4c 89 ff mov %r15,%rdi + 440182: e8 29 dc fd ff callq 41ddb0 <__cfree> + 440187: 49 8b 3e mov (%r14),%rdi + 44018a: ff d3 callq *%rbx + 44018c: 4c 89 f7 mov %r14,%rdi + 44018f: e8 1c dc fd ff callq 41ddb0 <__cfree> + 440194: 4d 8b 75 10 mov 0x10(%r13),%r14 + 440198: 4d 85 f6 test %r14,%r14 + 44019b: 0f 84 c2 00 00 00 je 440263 + 4401a1: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 4401a5: 4d 85 ff test %r15,%r15 + 4401a8: 74 2f je 4401d9 + 4401aa: 49 8b 7f 08 mov 0x8(%r15),%rdi + 4401ae: 48 85 ff test %rdi,%rdi + 4401b1: 74 08 je 4401bb + 4401b3: 48 89 de mov %rbx,%rsi + 4401b6: e8 e5 fb ff ff callq 43fda0 + 4401bb: 49 8b 7f 10 mov 0x10(%r15),%rdi + 4401bf: 48 85 ff test %rdi,%rdi + 4401c2: 74 08 je 4401cc + 4401c4: 48 89 de mov %rbx,%rsi + 4401c7: e8 d4 fb ff ff callq 43fda0 + 4401cc: 49 8b 3f mov (%r15),%rdi + 4401cf: ff d3 callq *%rbx + 4401d1: 4c 89 ff mov %r15,%rdi + 4401d4: e8 d7 db fd ff callq 41ddb0 <__cfree> + 4401d9: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 4401dd: 4d 85 ff test %r15,%r15 + 4401e0: 74 74 je 440256 + 4401e2: 49 8b 7f 08 mov 0x8(%r15),%rdi + 4401e6: 48 85 ff test %rdi,%rdi + 4401e9: 74 08 je 4401f3 + 4401eb: 48 89 de mov %rbx,%rsi + 4401ee: e8 ad fb ff ff callq 43fda0 + 4401f3: 49 8b 47 10 mov 0x10(%r15),%rax + 4401f7: 48 85 c0 test %rax,%rax + 4401fa: 74 4d je 440249 + 4401fc: 48 8b 78 08 mov 0x8(%rax),%rdi + 440200: 48 85 ff test %rdi,%rdi + 440203: 74 12 je 440217 + 440205: 48 89 de mov %rbx,%rsi + 440208: 48 89 44 24 08 mov %rax,0x8(%rsp) + 44020d: e8 8e fb ff ff callq 43fda0 + 440212: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 440217: 48 8b 78 10 mov 0x10(%rax),%rdi + 44021b: 48 85 ff test %rdi,%rdi + 44021e: 74 12 je 440232 + 440220: 48 89 de mov %rbx,%rsi + 440223: 48 89 44 24 08 mov %rax,0x8(%rsp) + 440228: e8 73 fb ff ff callq 43fda0 + 44022d: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 440232: 48 8b 38 mov (%rax),%rdi + 440235: 48 89 44 24 08 mov %rax,0x8(%rsp) + 44023a: ff d3 callq *%rbx + 44023c: 48 8b 44 24 08 mov 0x8(%rsp),%rax + 440241: 48 89 c7 mov %rax,%rdi + 440244: e8 67 db fd ff callq 41ddb0 <__cfree> + 440249: 49 8b 3f mov (%r15),%rdi + 44024c: ff d3 callq *%rbx + 44024e: 4c 89 ff mov %r15,%rdi + 440251: e8 5a db fd ff callq 41ddb0 <__cfree> + 440256: 49 8b 3e mov (%r14),%rdi + 440259: ff d3 callq *%rbx + 44025b: 4c 89 f7 mov %r14,%rdi + 44025e: e8 4d db fd ff callq 41ddb0 <__cfree> + 440263: 49 8b 7d 00 mov 0x0(%r13),%rdi + 440267: ff d3 callq *%rbx + 440269: 4c 89 ef mov %r13,%rdi + 44026c: e8 3f db fd ff callq 41ddb0 <__cfree> + 440271: 48 8b 7d 00 mov 0x0(%rbp),%rdi + 440275: ff d3 callq *%rbx + 440277: 48 89 ef mov %rbp,%rdi + 44027a: e8 31 db fd ff callq 41ddb0 <__cfree> + 44027f: 49 8b 3c 24 mov (%r12),%rdi + 440283: ff d3 callq *%rbx + 440285: 48 83 c4 18 add $0x18,%rsp + 440289: 4c 89 e7 mov %r12,%rdi + 44028c: 5b pop %rbx + 44028d: 5d pop %rbp + 44028e: 41 5c pop %r12 + 440290: 41 5d pop %r13 + 440292: 41 5e pop %r14 + 440294: 41 5f pop %r15 + 440296: e9 15 db fd ff jmpq 41ddb0 <__cfree> + 44029b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + +00000000004402a0 <__tsearch>: + 4402a0: 41 57 push %r15 + 4402a2: 41 56 push %r14 + 4402a4: 41 55 push %r13 + 4402a6: 41 54 push %r12 + 4402a8: 55 push %rbp + 4402a9: 53 push %rbx + 4402aa: 48 83 ec 28 sub $0x28,%rsp + 4402ae: 48 85 f6 test %rsi,%rsi + 4402b1: 48 89 7c 24 10 mov %rdi,0x10(%rsp) + 4402b6: 48 89 54 24 18 mov %rdx,0x18(%rsp) + 4402bb: 0f 84 12 03 00 00 je 4405d3 <__tsearch+0x333> + 4402c1: 48 8b 06 mov (%rsi),%rax + 4402c4: 49 89 f4 mov %rsi,%r12 + 4402c7: 48 85 c0 test %rax,%rax + 4402ca: 0f 84 60 02 00 00 je 440530 <__tsearch+0x290> + 4402d0: 80 60 18 fe andb $0xfe,0x18(%rax) + 4402d4: c7 44 24 08 00 00 00 movl $0x0,0x8(%rsp) + 4402db: 00 + 4402dc: 45 31 f6 xor %r14d,%r14d + 4402df: 48 8b 1e mov (%rsi),%rbx + 4402e2: 31 ed xor %ebp,%ebp + 4402e4: 45 31 ed xor %r13d,%r13d + 4402e7: eb 29 jmp 440312 <__tsearch+0x72> + 4402e9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4402f0: 48 8d 53 10 lea 0x10(%rbx),%rdx + 4402f4: 48 8b 5b 10 mov 0x10(%rbx),%rbx + 4402f8: 4c 89 ed mov %r13,%rbp + 4402fb: 44 89 74 24 08 mov %r14d,0x8(%rsp) + 440300: 48 85 db test %rbx,%rbx + 440303: 0f 84 f9 00 00 00 je 440402 <__tsearch+0x162> + 440309: 4d 89 e5 mov %r12,%r13 + 44030c: 45 89 fe mov %r15d,%r14d + 44030f: 49 89 d4 mov %rdx,%r12 + 440312: 48 85 db test %rbx,%rbx + 440315: 0f 84 15 02 00 00 je 440530 <__tsearch+0x290> + 44031b: 48 8b 33 mov (%rbx),%rsi + 44031e: 48 8b 7c 24 10 mov 0x10(%rsp),%rdi + 440323: 48 8b 44 24 18 mov 0x18(%rsp),%rax + 440328: ff d0 callq *%rax + 44032a: 85 c0 test %eax,%eax + 44032c: 41 89 c7 mov %eax,%r15d + 44032f: 0f 84 3b 02 00 00 je 440570 <__tsearch+0x2d0> + 440335: 49 8b 04 24 mov (%r12),%rax + 440339: 48 8b 50 10 mov 0x10(%rax),%rdx + 44033d: 48 85 d2 test %rdx,%rdx + 440340: 0f 84 9a 00 00 00 je 4403e0 <__tsearch+0x140> + 440346: 48 8b 70 08 mov 0x8(%rax),%rsi + 44034a: 48 85 f6 test %rsi,%rsi + 44034d: 0f 84 8d 00 00 00 je 4403e0 <__tsearch+0x140> + 440353: f6 42 18 01 testb $0x1,0x18(%rdx) + 440357: 0f 84 83 00 00 00 je 4403e0 <__tsearch+0x140> + 44035d: f6 46 18 01 testb $0x1,0x18(%rsi) + 440361: 74 7d je 4403e0 <__tsearch+0x140> + 440363: 80 48 18 01 orb $0x1,0x18(%rax) + 440367: 80 62 18 fe andb $0xfe,0x18(%rdx) + 44036b: 48 8b 50 08 mov 0x8(%rax),%rdx + 44036f: 48 85 d2 test %rdx,%rdx + 440372: 74 04 je 440378 <__tsearch+0xd8> + 440374: 80 62 18 fe andb $0xfe,0x18(%rdx) + 440378: 4d 85 ed test %r13,%r13 + 44037b: 74 63 je 4403e0 <__tsearch+0x140> + 44037d: 49 8b 55 00 mov 0x0(%r13),%rdx + 440381: 0f b6 72 18 movzbl 0x18(%rdx),%esi + 440385: 40 f6 c6 01 test $0x1,%sil + 440389: 74 55 je 4403e0 <__tsearch+0x140> + 44038b: 8b 4c 24 08 mov 0x8(%rsp),%ecx + 44038f: 45 85 f6 test %r14d,%r14d + 440392: 48 8b 7d 00 mov 0x0(%rbp),%rdi + 440396: 41 0f 9f c3 setg %r11b + 44039a: 85 c9 test %ecx,%ecx + 44039c: 41 0f 9f c2 setg %r10b + 4403a0: 45 38 d3 cmp %r10b,%r11b + 4403a3: 0f 84 37 01 00 00 je 4404e0 <__tsearch+0x240> + 4403a9: 83 ce 01 or $0x1,%esi + 4403ac: 40 88 72 18 mov %sil,0x18(%rdx) + 4403b0: 80 4f 18 01 orb $0x1,0x18(%rdi) + 4403b4: 80 60 18 fe andb $0xfe,0x18(%rax) + 4403b8: 45 85 f6 test %r14d,%r14d + 4403bb: 0f 88 4f 01 00 00 js 440510 <__tsearch+0x270> + 4403c1: 48 8b 70 08 mov 0x8(%rax),%rsi + 4403c5: 48 89 72 10 mov %rsi,0x10(%rdx) + 4403c9: 48 89 50 08 mov %rdx,0x8(%rax) + 4403cd: 48 8b 50 10 mov 0x10(%rax),%rdx + 4403d1: 48 89 57 08 mov %rdx,0x8(%rdi) + 4403d5: 48 89 78 10 mov %rdi,0x10(%rax) + 4403d9: 48 89 45 00 mov %rax,0x0(%rbp) + 4403dd: 0f 1f 00 nopl (%rax) + 4403e0: 45 85 ff test %r15d,%r15d + 4403e3: 0f 89 07 ff ff ff jns 4402f0 <__tsearch+0x50> + 4403e9: 48 8d 53 08 lea 0x8(%rbx),%rdx + 4403ed: 48 8b 5b 08 mov 0x8(%rbx),%rbx + 4403f1: 4c 89 ed mov %r13,%rbp + 4403f4: 44 89 74 24 08 mov %r14d,0x8(%rsp) + 4403f9: 48 85 db test %rbx,%rbx + 4403fc: 0f 85 07 ff ff ff jne 440309 <__tsearch+0x69> + 440402: bf 20 00 00 00 mov $0x20,%edi + 440407: 48 89 54 24 08 mov %rdx,0x8(%rsp) + 44040c: e8 ff d5 fd ff callq 41da10 <__libc_malloc> + 440411: 48 85 c0 test %rax,%rax + 440414: 48 89 c6 mov %rax,%rsi + 440417: 0f 84 b6 01 00 00 je 4405d3 <__tsearch+0x333> + 44041d: 48 8b 54 24 08 mov 0x8(%rsp),%rdx + 440422: 48 89 02 mov %rax,(%rdx) + 440425: 48 8b 44 24 10 mov 0x10(%rsp),%rax + 44042a: 80 4e 18 01 orb $0x1,0x18(%rsi) + 44042e: 49 39 d4 cmp %rdx,%r12 + 440431: 48 c7 46 10 00 00 00 movq $0x0,0x10(%rsi) + 440438: 00 + 440439: 48 c7 46 08 00 00 00 movq $0x0,0x8(%rsi) + 440440: 00 + 440441: 48 89 06 mov %rax,(%rsi) + 440444: 0f 84 a1 01 00 00 je 4405eb <__tsearch+0x34b> + 44044a: 48 8b 12 mov (%rdx),%rdx + 44044d: 48 8b 42 10 mov 0x10(%rdx),%rax + 440451: 80 4a 18 01 orb $0x1,0x18(%rdx) + 440455: 48 85 c0 test %rax,%rax + 440458: 74 04 je 44045e <__tsearch+0x1be> + 44045a: 80 60 18 fe andb $0xfe,0x18(%rax) + 44045e: 48 8b 42 08 mov 0x8(%rdx),%rax + 440462: 48 85 c0 test %rax,%rax + 440465: 74 04 je 44046b <__tsearch+0x1cb> + 440467: 80 60 18 fe andb $0xfe,0x18(%rax) + 44046b: 49 8b 0c 24 mov (%r12),%rcx + 44046f: 48 89 f0 mov %rsi,%rax + 440472: 0f b6 79 18 movzbl 0x18(%rcx),%edi + 440476: 40 f6 c7 01 test $0x1,%dil + 44047a: 74 53 je 4404cf <__tsearch+0x22f> + 44047c: 45 85 ff test %r15d,%r15d + 44047f: 4d 8b 55 00 mov 0x0(%r13),%r10 + 440483: 41 0f 9f c3 setg %r11b + 440487: 45 85 f6 test %r14d,%r14d + 44048a: 41 0f 9f c1 setg %r9b + 44048e: 45 38 cb cmp %r9b,%r11b + 440491: 0f 84 eb 00 00 00 je 440582 <__tsearch+0x2e2> + 440497: 83 cf 01 or $0x1,%edi + 44049a: 40 88 79 18 mov %dil,0x18(%rcx) + 44049e: 41 80 4a 18 01 orb $0x1,0x18(%r10) + 4404a3: 80 62 18 fe andb $0xfe,0x18(%rdx) + 4404a7: 45 85 ff test %r15d,%r15d + 4404aa: 0f 88 06 01 00 00 js 4405b6 <__tsearch+0x316> + 4404b0: 48 8b 42 08 mov 0x8(%rdx),%rax + 4404b4: 48 89 41 10 mov %rax,0x10(%rcx) + 4404b8: 48 8b 42 10 mov 0x10(%rdx),%rax + 4404bc: 48 89 4a 08 mov %rcx,0x8(%rdx) + 4404c0: 49 89 42 08 mov %rax,0x8(%r10) + 4404c4: 4c 89 52 10 mov %r10,0x10(%rdx) + 4404c8: 49 89 55 00 mov %rdx,0x0(%r13) + 4404cc: 48 89 f0 mov %rsi,%rax + 4404cf: 48 83 c4 28 add $0x28,%rsp + 4404d3: 5b pop %rbx + 4404d4: 5d pop %rbp + 4404d5: 41 5c pop %r12 + 4404d7: 41 5d pop %r13 + 4404d9: 41 5e pop %r14 + 4404db: 41 5f pop %r15 + 4404dd: c3 retq + 4404de: 66 90 xchg %ax,%ax + 4404e0: 48 89 55 00 mov %rdx,0x0(%rbp) + 4404e4: 80 62 18 fe andb $0xfe,0x18(%rdx) + 4404e8: 80 4f 18 01 orb $0x1,0x18(%rdi) + 4404ec: 45 85 f6 test %r14d,%r14d + 4404ef: 0f 88 b0 00 00 00 js 4405a5 <__tsearch+0x305> + 4404f5: 48 8b 42 08 mov 0x8(%rdx),%rax + 4404f9: 48 89 47 10 mov %rax,0x10(%rdi) + 4404fd: 48 89 7a 08 mov %rdi,0x8(%rdx) + 440501: e9 da fe ff ff jmpq 4403e0 <__tsearch+0x140> + 440506: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 44050d: 00 00 00 + 440510: 48 8b 70 10 mov 0x10(%rax),%rsi + 440514: 48 89 72 08 mov %rsi,0x8(%rdx) + 440518: 48 89 50 10 mov %rdx,0x10(%rax) + 44051c: 48 8b 50 08 mov 0x8(%rax),%rdx + 440520: 48 89 57 10 mov %rdx,0x10(%rdi) + 440524: 48 89 78 08 mov %rdi,0x8(%rax) + 440528: e9 ac fe ff ff jmpq 4403d9 <__tsearch+0x139> + 44052d: 0f 1f 00 nopl (%rax) + 440530: bf 20 00 00 00 mov $0x20,%edi + 440535: e8 d6 d4 fd ff callq 41da10 <__libc_malloc> + 44053a: 48 85 c0 test %rax,%rax + 44053d: 74 90 je 4404cf <__tsearch+0x22f> + 44053f: 48 8b 4c 24 10 mov 0x10(%rsp),%rcx + 440544: 49 89 04 24 mov %rax,(%r12) + 440548: 80 48 18 01 orb $0x1,0x18(%rax) + 44054c: 48 c7 40 10 00 00 00 movq $0x0,0x10(%rax) + 440553: 00 + 440554: 48 c7 40 08 00 00 00 movq $0x0,0x8(%rax) + 44055b: 00 + 44055c: 48 89 08 mov %rcx,(%rax) + 44055f: 48 83 c4 28 add $0x28,%rsp + 440563: 5b pop %rbx + 440564: 5d pop %rbp + 440565: 41 5c pop %r12 + 440567: 41 5d pop %r13 + 440569: 41 5e pop %r14 + 44056b: 41 5f pop %r15 + 44056d: c3 retq + 44056e: 66 90 xchg %ax,%ax + 440570: 48 83 c4 28 add $0x28,%rsp + 440574: 48 89 d8 mov %rbx,%rax + 440577: 5b pop %rbx + 440578: 5d pop %rbp + 440579: 41 5c pop %r12 + 44057b: 41 5d pop %r13 + 44057d: 41 5e pop %r14 + 44057f: 41 5f pop %r15 + 440581: c3 retq + 440582: 49 89 4d 00 mov %rcx,0x0(%r13) + 440586: 80 61 18 fe andb $0xfe,0x18(%rcx) + 44058a: 41 80 4a 18 01 orb $0x1,0x18(%r10) + 44058f: 45 85 ff test %r15d,%r15d + 440592: 78 46 js 4405da <__tsearch+0x33a> + 440594: 48 8b 51 08 mov 0x8(%rcx),%rdx + 440598: 49 89 52 10 mov %rdx,0x10(%r10) + 44059c: 4c 89 51 08 mov %r10,0x8(%rcx) + 4405a0: e9 2a ff ff ff jmpq 4404cf <__tsearch+0x22f> + 4405a5: 48 8b 42 10 mov 0x10(%rdx),%rax + 4405a9: 48 89 47 08 mov %rax,0x8(%rdi) + 4405ad: 48 89 7a 10 mov %rdi,0x10(%rdx) + 4405b1: e9 2a fe ff ff jmpq 4403e0 <__tsearch+0x140> + 4405b6: 48 8b 42 10 mov 0x10(%rdx),%rax + 4405ba: 48 89 41 08 mov %rax,0x8(%rcx) + 4405be: 48 8b 42 08 mov 0x8(%rdx),%rax + 4405c2: 48 89 4a 10 mov %rcx,0x10(%rdx) + 4405c6: 49 89 42 10 mov %rax,0x10(%r10) + 4405ca: 4c 89 52 08 mov %r10,0x8(%rdx) + 4405ce: e9 f5 fe ff ff jmpq 4404c8 <__tsearch+0x228> + 4405d3: 31 c0 xor %eax,%eax + 4405d5: e9 f5 fe ff ff jmpq 4404cf <__tsearch+0x22f> + 4405da: 48 8b 51 10 mov 0x10(%rcx),%rdx + 4405de: 49 89 52 08 mov %rdx,0x8(%r10) + 4405e2: 4c 89 51 10 mov %r10,0x10(%rcx) + 4405e6: e9 e4 fe ff ff jmpq 4404cf <__tsearch+0x22f> + 4405eb: 48 89 f0 mov %rsi,%rax + 4405ee: e9 dc fe ff ff jmpq 4404cf <__tsearch+0x22f> + 4405f3: 0f 1f 00 nopl (%rax) + 4405f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 4405fd: 00 00 00 + +0000000000440600 <__tfind>: + 440600: 48 85 f6 test %rsi,%rsi + 440603: 74 4b je 440650 <__tfind+0x50> + 440605: 41 54 push %r12 + 440607: 49 89 fc mov %rdi,%r12 + 44060a: 55 push %rbp + 44060b: 48 89 d5 mov %rdx,%rbp + 44060e: 53 push %rbx + 44060f: eb 21 jmp 440632 <__tfind+0x32> + 440611: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 440618: 48 8b 33 mov (%rbx),%rsi + 44061b: 4c 89 e7 mov %r12,%rdi + 44061e: ff d5 callq *%rbp + 440620: 85 c0 test %eax,%eax + 440622: 74 24 je 440648 <__tfind+0x48> + 440624: 48 8d 73 08 lea 0x8(%rbx),%rsi + 440628: 48 83 c3 10 add $0x10,%rbx + 44062c: 85 c0 test %eax,%eax + 44062e: 48 0f 49 f3 cmovns %rbx,%rsi + 440632: 48 8b 1e mov (%rsi),%rbx + 440635: 48 85 db test %rbx,%rbx + 440638: 75 de jne 440618 <__tfind+0x18> + 44063a: 5b pop %rbx + 44063b: 31 c0 xor %eax,%eax + 44063d: 5d pop %rbp + 44063e: 41 5c pop %r12 + 440640: c3 retq + 440641: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 440648: 48 89 d8 mov %rbx,%rax + 44064b: 5b pop %rbx + 44064c: 5d pop %rbp + 44064d: 41 5c pop %r12 + 44064f: c3 retq + 440650: 31 c0 xor %eax,%eax + 440652: c3 retq + 440653: 0f 1f 00 nopl (%rax) + 440656: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 44065d: 00 00 00 + +0000000000440660 <__tdelete>: + 440660: 55 push %rbp + 440661: 48 89 e5 mov %rsp,%rbp + 440664: 41 57 push %r15 + 440666: 41 56 push %r14 + 440668: 41 55 push %r13 + 44066a: 41 54 push %r12 + 44066c: 53 push %rbx + 44066d: 48 83 ec 28 sub $0x28,%rsp + 440671: 48 89 7d c0 mov %rdi,-0x40(%rbp) + 440675: 48 89 55 b8 mov %rdx,-0x48(%rbp) + 440679: 48 81 ec 50 01 00 00 sub $0x150,%rsp + 440680: 4c 8d 64 24 0f lea 0xf(%rsp),%r12 + 440685: 49 83 e4 f0 and $0xfffffffffffffff0,%r12 + 440689: 48 85 f6 test %rsi,%rsi + 44068c: 74 78 je 440706 <__tdelete+0xa6> + 44068e: 4c 8b 06 mov (%rsi),%r8 + 440691: 49 89 f6 mov %rsi,%r14 + 440694: 4d 85 c0 test %r8,%r8 + 440697: 74 6d je 440706 <__tdelete+0xa6> + 440699: 4d 89 c7 mov %r8,%r15 + 44069c: 31 db xor %ebx,%ebx + 44069e: c7 45 cc 28 00 00 00 movl $0x28,-0x34(%rbp) + 4406a5: 4c 89 c0 mov %r8,%rax + 4406a8: eb 17 jmp 4406c1 <__tdelete+0x61> + 4406aa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4406b0: 49 8b 47 10 mov 0x10(%r15),%rax + 4406b4: 48 83 c3 01 add $0x1,%rbx + 4406b8: 4d 8d 77 10 lea 0x10(%r15),%r14 + 4406bc: 48 85 c0 test %rax,%rax + 4406bf: 74 45 je 440706 <__tdelete+0xa6> + 4406c1: 48 8b 30 mov (%rax),%rsi + 4406c4: 48 8b 7d c0 mov -0x40(%rbp),%rdi + 4406c8: 41 89 dd mov %ebx,%r13d + 4406cb: 48 8b 45 b8 mov -0x48(%rbp),%rax + 4406cf: ff d0 callq *%rax + 4406d1: 85 c0 test %eax,%eax + 4406d3: 41 89 c1 mov %eax,%r9d + 4406d6: 0f 84 84 00 00 00 je 440760 <__tdelete+0x100> + 4406dc: 39 5d cc cmp %ebx,-0x34(%rbp) + 4406df: 74 3f je 440720 <__tdelete+0xc0> + 4406e1: 4c 8d 2c dd 00 00 00 lea 0x0(,%rbx,8),%r13 + 4406e8: 00 + 4406e9: 45 85 c9 test %r9d,%r9d + 4406ec: 4f 89 34 2c mov %r14,(%r12,%r13,1) + 4406f0: 4d 8b 3e mov (%r14),%r15 + 4406f3: 79 bb jns 4406b0 <__tdelete+0x50> + 4406f5: 49 8b 47 08 mov 0x8(%r15),%rax + 4406f9: 48 83 c3 01 add $0x1,%rbx + 4406fd: 4d 8d 77 08 lea 0x8(%r15),%r14 + 440701: 48 85 c0 test %rax,%rax + 440704: 75 bb jne 4406c1 <__tdelete+0x61> + 440706: 48 8d 65 d8 lea -0x28(%rbp),%rsp + 44070a: 31 c0 xor %eax,%eax + 44070c: 5b pop %rbx + 44070d: 41 5c pop %r12 + 44070f: 41 5d pop %r13 + 440711: 41 5e pop %r14 + 440713: 41 5f pop %r15 + 440715: 5d pop %rbp + 440716: c3 retq + 440717: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 44071e: 00 00 + 440720: 83 45 cc 14 addl $0x14,-0x34(%rbp) + 440724: 4c 8d 2c dd 00 00 00 lea 0x0(,%rbx,8),%r13 + 44072b: 00 + 44072c: 4c 89 e6 mov %r12,%rsi + 44072f: 48 63 45 cc movslq -0x34(%rbp),%rax + 440733: 44 89 4d b0 mov %r9d,-0x50(%rbp) + 440737: 4c 89 ea mov %r13,%rdx + 44073a: 48 8d 04 c5 1e 00 00 lea 0x1e(,%rax,8),%rax + 440741: 00 + 440742: 48 83 e0 f0 and $0xfffffffffffffff0,%rax + 440746: 48 29 c4 sub %rax,%rsp + 440749: 48 8d 7c 24 0f lea 0xf(%rsp),%rdi + 44074e: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi + 440752: e8 c9 b8 fe ff callq 42c020 + 440757: 44 8b 4d b0 mov -0x50(%rbp),%r9d + 44075b: 49 89 c4 mov %rax,%r12 + 44075e: eb 89 jmp 4406e9 <__tdelete+0x89> + 440760: 4d 8b 06 mov (%r14),%r8 + 440763: 49 8b 70 08 mov 0x8(%r8),%rsi + 440767: 49 8b 58 10 mov 0x10(%r8),%rbx + 44076b: 48 85 f6 test %rsi,%rsi + 44076e: 0f 84 94 00 00 00 je 440808 <__tdelete+0x1a8> + 440774: 48 85 db test %rbx,%rbx + 440777: 0f 84 8b 00 00 00 je 440808 <__tdelete+0x1a8> + 44077d: 49 63 c5 movslq %r13d,%rax + 440780: 4d 8d 48 10 lea 0x10(%r8),%r9 + 440784: 48 8d 0c c5 00 00 00 lea 0x0(,%rax,8),%rcx + 44078b: 00 + 44078c: eb 28 jmp 4407b6 <__tdelete+0x156> + 44078e: 66 90 xchg %ax,%ax + 440790: 48 8b 43 08 mov 0x8(%rbx),%rax + 440794: 41 83 c5 01 add $0x1,%r13d + 440798: 4d 89 34 0c mov %r14,(%r12,%rcx,1) + 44079c: 48 83 c1 08 add $0x8,%rcx + 4407a0: 48 85 c0 test %rax,%rax + 4407a3: 0f 84 2f 02 00 00 je 4409d8 <__tdelete+0x378> + 4407a9: 48 8d 53 08 lea 0x8(%rbx),%rdx + 4407ad: 4d 89 ce mov %r9,%r14 + 4407b0: 48 89 c3 mov %rax,%rbx + 4407b3: 49 89 d1 mov %rdx,%r9 + 4407b6: 44 39 6d cc cmp %r13d,-0x34(%rbp) + 4407ba: 75 d4 jne 440790 <__tdelete+0x130> + 4407bc: 83 45 cc 14 addl $0x14,-0x34(%rbp) + 4407c0: 48 89 ca mov %rcx,%rdx + 4407c3: 4c 89 e6 mov %r12,%rsi + 4407c6: 48 63 45 cc movslq -0x34(%rbp),%rax + 4407ca: 4c 89 45 b0 mov %r8,-0x50(%rbp) + 4407ce: 4c 89 4d b8 mov %r9,-0x48(%rbp) + 4407d2: 48 89 4d c0 mov %rcx,-0x40(%rbp) + 4407d6: 48 8d 04 c5 1e 00 00 lea 0x1e(,%rax,8),%rax + 4407dd: 00 + 4407de: 48 83 e0 f0 and $0xfffffffffffffff0,%rax + 4407e2: 48 29 c4 sub %rax,%rsp + 4407e5: 48 8d 7c 24 0f lea 0xf(%rsp),%rdi + 4407ea: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi + 4407ee: e8 2d b8 fe ff callq 42c020 + 4407f3: 4c 8b 45 b0 mov -0x50(%rbp),%r8 + 4407f7: 49 89 c4 mov %rax,%r12 + 4407fa: 4c 8b 4d b8 mov -0x48(%rbp),%r9 + 4407fe: 48 8b 4d c0 mov -0x40(%rbp),%rcx + 440802: eb 8c jmp 440790 <__tdelete+0x130> + 440804: 0f 1f 40 00 nopl 0x0(%rax) + 440808: 48 85 f6 test %rsi,%rsi + 44080b: 48 0f 44 f3 cmove %rbx,%rsi + 44080f: 45 85 ed test %r13d,%r13d + 440812: 0f 85 69 02 00 00 jne 440a81 <__tdelete+0x421> + 440818: 49 89 36 mov %rsi,(%r14) + 44081b: 4c 89 c3 mov %r8,%rbx + 44081e: 49 39 d8 cmp %rbx,%r8 + 440821: 74 06 je 440829 <__tdelete+0x1c9> + 440823: 48 8b 03 mov (%rbx),%rax + 440826: 49 89 00 mov %rax,(%r8) + 440829: f6 43 18 01 testb $0x1,0x18(%rbx) + 44082d: 0f 85 b6 00 00 00 jne 4408e9 <__tdelete+0x289> + 440833: 45 85 ed test %r13d,%r13d + 440836: 0f 84 56 02 00 00 je 440a92 <__tdelete+0x432> + 44083c: 48 85 f6 test %rsi,%rsi + 44083f: 74 0a je 44084b <__tdelete+0x1eb> + 440841: f6 46 18 01 testb $0x1,0x18(%rsi) + 440845: 0f 85 7d 01 00 00 jne 4409c8 <__tdelete+0x368> + 44084b: 4d 63 cd movslq %r13d,%r9 + 44084e: 4b 8b 7c cc f8 mov -0x8(%r12,%r9,8),%rdi + 440853: 48 8b 17 mov (%rdi),%rdx + 440856: 48 8b 42 08 mov 0x8(%rdx),%rax + 44085a: 48 39 f0 cmp %rsi,%rax + 44085d: 0f 84 ed 00 00 00 je 440950 <__tdelete+0x2f0> + 440863: 0f b6 48 18 movzbl 0x18(%rax),%ecx + 440867: f6 c1 01 test $0x1,%cl + 44086a: 74 29 je 440895 <__tdelete+0x235> + 44086c: 83 e1 fe and $0xfffffffe,%ecx + 44086f: 41 83 c5 01 add $0x1,%r13d + 440873: 88 48 18 mov %cl,0x18(%rax) + 440876: 80 4a 18 01 orb $0x1,0x18(%rdx) + 44087a: 48 8b 48 10 mov 0x10(%rax),%rcx + 44087e: 48 89 4a 08 mov %rcx,0x8(%rdx) + 440882: 48 89 50 10 mov %rdx,0x10(%rax) + 440886: 48 89 07 mov %rax,(%rdi) + 440889: 48 8d 78 10 lea 0x10(%rax),%rdi + 44088d: 48 8b 42 08 mov 0x8(%rdx),%rax + 440891: 4b 89 3c cc mov %rdi,(%r12,%r9,8) + 440895: 48 8b 48 10 mov 0x10(%rax),%rcx + 440899: 48 85 c9 test %rcx,%rcx + 44089c: 74 6a je 440908 <__tdelete+0x2a8> + 44089e: f6 41 18 01 testb $0x1,0x18(%rcx) + 4408a2: 74 64 je 440908 <__tdelete+0x2a8> + 4408a4: 48 8b 70 08 mov 0x8(%rax),%rsi + 4408a8: 48 85 f6 test %rsi,%rsi + 4408ab: 74 06 je 4408b3 <__tdelete+0x253> + 4408ad: f6 46 18 01 testb $0x1,0x18(%rsi) + 4408b1: 75 6c jne 44091f <__tdelete+0x2bf> + 4408b3: 0f b6 72 18 movzbl 0x18(%rdx),%esi + 4408b7: 44 0f b6 49 18 movzbl 0x18(%rcx),%r9d + 4408bc: 83 e6 01 and $0x1,%esi + 4408bf: 41 83 e1 fe and $0xfffffffe,%r9d + 4408c3: 44 09 ce or %r9d,%esi + 4408c6: 40 88 71 18 mov %sil,0x18(%rcx) + 4408ca: 48 8b 71 10 mov 0x10(%rcx),%rsi + 4408ce: 48 89 72 08 mov %rsi,0x8(%rdx) + 4408d2: 48 8b 71 08 mov 0x8(%rcx),%rsi + 4408d6: 48 89 70 10 mov %rsi,0x10(%rax) + 4408da: 48 89 41 08 mov %rax,0x8(%rcx) + 4408de: 48 89 51 10 mov %rdx,0x10(%rcx) + 4408e2: 48 89 0f mov %rcx,(%rdi) + 4408e5: 80 62 18 fe andb $0xfe,0x18(%rdx) + 4408e9: 48 89 df mov %rbx,%rdi + 4408ec: e8 bf d4 fd ff callq 41ddb0 <__cfree> + 4408f1: 48 8d 65 d8 lea -0x28(%rbp),%rsp + 4408f5: 4c 89 f8 mov %r15,%rax + 4408f8: 5b pop %rbx + 4408f9: 41 5c pop %r12 + 4408fb: 41 5d pop %r13 + 4408fd: 41 5e pop %r14 + 4408ff: 41 5f pop %r15 + 440901: 5d pop %rbp + 440902: c3 retq + 440903: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 440908: 48 8b 70 08 mov 0x8(%rax),%rsi + 44090c: 48 85 f6 test %rsi,%rsi + 44090f: 0f 84 9b 00 00 00 je 4409b0 <__tdelete+0x350> + 440915: f6 46 18 01 testb $0x1,0x18(%rsi) + 440919: 0f 84 91 00 00 00 je 4409b0 <__tdelete+0x350> + 44091f: 44 0f b6 4a 18 movzbl 0x18(%rdx),%r9d + 440924: 44 0f b6 50 18 movzbl 0x18(%rax),%r10d + 440929: 41 83 e1 01 and $0x1,%r9d + 44092d: 41 83 e2 fe and $0xfffffffe,%r10d + 440931: 45 09 d1 or %r10d,%r9d + 440934: 44 88 48 18 mov %r9b,0x18(%rax) + 440938: 80 62 18 fe andb $0xfe,0x18(%rdx) + 44093c: 80 66 18 fe andb $0xfe,0x18(%rsi) + 440940: 48 89 4a 08 mov %rcx,0x8(%rdx) + 440944: 48 89 50 10 mov %rdx,0x10(%rax) + 440948: 48 89 07 mov %rax,(%rdi) + 44094b: eb 9c jmp 4408e9 <__tdelete+0x289> + 44094d: 0f 1f 00 nopl (%rax) + 440950: 48 8b 42 10 mov 0x10(%rdx),%rax + 440954: 0f b6 48 18 movzbl 0x18(%rax),%ecx + 440958: f6 c1 01 test $0x1,%cl + 44095b: 74 29 je 440986 <__tdelete+0x326> + 44095d: 83 e1 fe and $0xfffffffe,%ecx + 440960: 41 83 c5 01 add $0x1,%r13d + 440964: 88 48 18 mov %cl,0x18(%rax) + 440967: 80 4a 18 01 orb $0x1,0x18(%rdx) + 44096b: 48 8b 48 08 mov 0x8(%rax),%rcx + 44096f: 48 89 4a 10 mov %rcx,0x10(%rdx) + 440973: 48 89 50 08 mov %rdx,0x8(%rax) + 440977: 48 89 07 mov %rax,(%rdi) + 44097a: 48 8d 78 08 lea 0x8(%rax),%rdi + 44097e: 48 8b 42 10 mov 0x10(%rdx),%rax + 440982: 4b 89 3c cc mov %rdi,(%r12,%r9,8) + 440986: 48 8b 48 08 mov 0x8(%rax),%rcx + 44098a: 48 85 c9 test %rcx,%rcx + 44098d: 74 06 je 440995 <__tdelete+0x335> + 44098f: f6 41 18 01 testb $0x1,0x18(%rcx) + 440993: 75 6b jne 440a00 <__tdelete+0x3a0> + 440995: 48 8b 70 10 mov 0x10(%rax),%rsi + 440999: 48 85 f6 test %rsi,%rsi + 44099c: 74 12 je 4409b0 <__tdelete+0x350> + 44099e: f6 46 18 01 testb $0x1,0x18(%rsi) + 4409a2: 0f 85 a8 00 00 00 jne 440a50 <__tdelete+0x3f0> + 4409a8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 4409af: 00 + 4409b0: 80 48 18 01 orb $0x1,0x18(%rax) + 4409b4: 41 83 ed 01 sub $0x1,%r13d + 4409b8: 48 89 d6 mov %rdx,%rsi + 4409bb: 0f 85 7b fe ff ff jne 44083c <__tdelete+0x1dc> + 4409c1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4409c8: 80 66 18 fe andb $0xfe,0x18(%rsi) + 4409cc: e9 18 ff ff ff jmpq 4408e9 <__tdelete+0x289> + 4409d1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 4409d8: 48 8b 73 10 mov 0x10(%rbx),%rsi + 4409dc: 49 63 c5 movslq %r13d,%rax + 4409df: 49 8b 44 c4 f8 mov -0x8(%r12,%rax,8),%rax + 4409e4: 48 8b 00 mov (%rax),%rax + 4409e7: 48 39 58 10 cmp %rbx,0x10(%rax) + 4409eb: 0f 84 98 00 00 00 je 440a89 <__tdelete+0x429> + 4409f1: 48 89 70 08 mov %rsi,0x8(%rax) + 4409f5: e9 24 fe ff ff jmpq 44081e <__tdelete+0x1be> + 4409fa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 440a00: 48 8b 70 10 mov 0x10(%rax),%rsi + 440a04: 48 85 f6 test %rsi,%rsi + 440a07: 74 06 je 440a0f <__tdelete+0x3af> + 440a09: f6 46 18 01 testb $0x1,0x18(%rsi) + 440a0d: 75 41 jne 440a50 <__tdelete+0x3f0> + 440a0f: 0f b6 72 18 movzbl 0x18(%rdx),%esi + 440a13: 44 0f b6 49 18 movzbl 0x18(%rcx),%r9d + 440a18: 83 e6 01 and $0x1,%esi + 440a1b: 41 83 e1 fe and $0xfffffffe,%r9d + 440a1f: 44 09 ce or %r9d,%esi + 440a22: 40 88 71 18 mov %sil,0x18(%rcx) + 440a26: 48 8b 71 08 mov 0x8(%rcx),%rsi + 440a2a: 48 89 72 10 mov %rsi,0x10(%rdx) + 440a2e: 48 8b 71 10 mov 0x10(%rcx),%rsi + 440a32: 48 89 70 08 mov %rsi,0x8(%rax) + 440a36: 48 89 41 10 mov %rax,0x10(%rcx) + 440a3a: 48 89 51 08 mov %rdx,0x8(%rcx) + 440a3e: 48 89 0f mov %rcx,(%rdi) + 440a41: 80 62 18 fe andb $0xfe,0x18(%rdx) + 440a45: e9 9f fe ff ff jmpq 4408e9 <__tdelete+0x289> + 440a4a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 440a50: 44 0f b6 4a 18 movzbl 0x18(%rdx),%r9d + 440a55: 44 0f b6 50 18 movzbl 0x18(%rax),%r10d + 440a5a: 41 83 e1 01 and $0x1,%r9d + 440a5e: 41 83 e2 fe and $0xfffffffe,%r10d + 440a62: 45 09 d1 or %r10d,%r9d + 440a65: 44 88 48 18 mov %r9b,0x18(%rax) + 440a69: 80 62 18 fe andb $0xfe,0x18(%rdx) + 440a6d: 80 66 18 fe andb $0xfe,0x18(%rsi) + 440a71: 48 89 4a 10 mov %rcx,0x10(%rdx) + 440a75: 48 89 50 08 mov %rdx,0x8(%rax) + 440a79: 48 89 07 mov %rax,(%rdi) + 440a7c: e9 68 fe ff ff jmpq 4408e9 <__tdelete+0x289> + 440a81: 4c 89 c3 mov %r8,%rbx + 440a84: e9 53 ff ff ff jmpq 4409dc <__tdelete+0x37c> + 440a89: 48 89 70 10 mov %rsi,0x10(%rax) + 440a8d: e9 8c fd ff ff jmpq 44081e <__tdelete+0x1be> + 440a92: 48 85 f6 test %rsi,%rsi + 440a95: 0f 85 2d ff ff ff jne 4409c8 <__tdelete+0x368> + 440a9b: e9 49 fe ff ff jmpq 4408e9 <__tdelete+0x289> + +0000000000440aa0 <__twalk>: + 440aa0: 41 57 push %r15 + 440aa2: 41 56 push %r14 + 440aa4: 41 55 push %r13 + 440aa6: 41 54 push %r12 + 440aa8: 55 push %rbp + 440aa9: 53 push %rbx + 440aaa: 48 83 ec 08 sub $0x8,%rsp + 440aae: 48 85 ff test %rdi,%rdi + 440ab1: 0f 84 91 0a 00 00 je 441548 <__twalk+0xaa8> + 440ab7: 48 85 f6 test %rsi,%rsi + 440aba: 48 89 f0 mov %rsi,%rax + 440abd: 0f 84 85 0a 00 00 je 441548 <__twalk+0xaa8> + 440ac3: 48 83 7f 08 00 cmpq $0x0,0x8(%rdi) + 440ac8: 0f 84 d2 0a 00 00 je 4415a0 <__twalk+0xb00> + 440ace: 48 89 fd mov %rdi,%rbp + 440ad1: 31 d2 xor %edx,%edx + 440ad3: 31 f6 xor %esi,%esi + 440ad5: 48 89 c3 mov %rax,%rbx + 440ad8: ff d0 callq *%rax + 440ada: 4c 8b 65 08 mov 0x8(%rbp),%r12 + 440ade: 4d 85 e4 test %r12,%r12 + 440ae1: 0f 84 14 05 00 00 je 440ffb <__twalk+0x55b> + 440ae7: 49 83 7c 24 08 00 cmpq $0x0,0x8(%r12) + 440aed: ba 01 00 00 00 mov $0x1,%edx + 440af2: 0f 84 88 0a 00 00 je 441580 <__twalk+0xae0> + 440af8: 31 f6 xor %esi,%esi + 440afa: 4c 89 e7 mov %r12,%rdi + 440afd: ff d3 callq *%rbx + 440aff: 4d 8b 6c 24 08 mov 0x8(%r12),%r13 + 440b04: 4d 85 ed test %r13,%r13 + 440b07: 0f 84 61 02 00 00 je 440d6e <__twalk+0x2ce> + 440b0d: 49 83 7d 08 00 cmpq $0x0,0x8(%r13) + 440b12: ba 02 00 00 00 mov $0x2,%edx + 440b17: 0f 84 db 0a 00 00 je 4415f8 <__twalk+0xb58> + 440b1d: 31 f6 xor %esi,%esi + 440b1f: 4c 89 ef mov %r13,%rdi + 440b22: ff d3 callq *%rbx + 440b24: 4d 8b 75 08 mov 0x8(%r13),%r14 + 440b28: 4d 85 f6 test %r14,%r14 + 440b2b: 0f 84 09 01 00 00 je 440c3a <__twalk+0x19a> + 440b31: 49 83 7e 08 00 cmpq $0x0,0x8(%r14) + 440b36: ba 03 00 00 00 mov $0x3,%edx + 440b3b: 0f 84 f7 0a 00 00 je 441638 <__twalk+0xb98> + 440b41: 31 f6 xor %esi,%esi + 440b43: 4c 89 f7 mov %r14,%rdi + 440b46: ff d3 callq *%rbx + 440b48: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 440b4c: 4d 85 ff test %r15,%r15 + 440b4f: 74 61 je 440bb2 <__twalk+0x112> + 440b51: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) + 440b56: ba 04 00 00 00 mov $0x4,%edx + 440b5b: 0f 84 17 0d 00 00 je 441878 <__twalk+0xdd8> + 440b61: 31 f6 xor %esi,%esi + 440b63: 4c 89 ff mov %r15,%rdi + 440b66: ff d3 callq *%rbx + 440b68: 49 8b 7f 08 mov 0x8(%r15),%rdi + 440b6c: 48 85 ff test %rdi,%rdi + 440b6f: 74 0d je 440b7e <__twalk+0xde> + 440b71: ba 05 00 00 00 mov $0x5,%edx + 440b76: 48 89 de mov %rbx,%rsi + 440b79: e8 92 f1 ff ff callq 43fd10 + 440b7e: 4c 89 ff mov %r15,%rdi + 440b81: ba 04 00 00 00 mov $0x4,%edx + 440b86: be 01 00 00 00 mov $0x1,%esi + 440b8b: ff d3 callq *%rbx + 440b8d: 49 8b 7f 10 mov 0x10(%r15),%rdi + 440b91: 48 85 ff test %rdi,%rdi + 440b94: 74 0d je 440ba3 <__twalk+0x103> + 440b96: ba 05 00 00 00 mov $0x5,%edx + 440b9b: 48 89 de mov %rbx,%rsi + 440b9e: e8 6d f1 ff ff callq 43fd10 + 440ba3: ba 04 00 00 00 mov $0x4,%edx + 440ba8: be 02 00 00 00 mov $0x2,%esi + 440bad: 4c 89 ff mov %r15,%rdi + 440bb0: ff d3 callq *%rbx + 440bb2: ba 03 00 00 00 mov $0x3,%edx + 440bb7: be 01 00 00 00 mov $0x1,%esi + 440bbc: 4c 89 f7 mov %r14,%rdi + 440bbf: ff d3 callq *%rbx + 440bc1: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 440bc5: 4d 85 ff test %r15,%r15 + 440bc8: 74 61 je 440c2b <__twalk+0x18b> + 440bca: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) + 440bcf: ba 04 00 00 00 mov $0x4,%edx + 440bd4: 0f 84 fe 0c 00 00 je 4418d8 <__twalk+0xe38> + 440bda: 31 f6 xor %esi,%esi + 440bdc: 4c 89 ff mov %r15,%rdi + 440bdf: ff d3 callq *%rbx + 440be1: 49 8b 7f 08 mov 0x8(%r15),%rdi + 440be5: 48 85 ff test %rdi,%rdi + 440be8: 74 0d je 440bf7 <__twalk+0x157> + 440bea: ba 05 00 00 00 mov $0x5,%edx + 440bef: 48 89 de mov %rbx,%rsi + 440bf2: e8 19 f1 ff ff callq 43fd10 + 440bf7: 4c 89 ff mov %r15,%rdi + 440bfa: ba 04 00 00 00 mov $0x4,%edx + 440bff: be 01 00 00 00 mov $0x1,%esi + 440c04: ff d3 callq *%rbx + 440c06: 49 8b 7f 10 mov 0x10(%r15),%rdi + 440c0a: 48 85 ff test %rdi,%rdi + 440c0d: 74 0d je 440c1c <__twalk+0x17c> + 440c0f: ba 05 00 00 00 mov $0x5,%edx + 440c14: 48 89 de mov %rbx,%rsi + 440c17: e8 f4 f0 ff ff callq 43fd10 + 440c1c: ba 04 00 00 00 mov $0x4,%edx + 440c21: be 02 00 00 00 mov $0x2,%esi + 440c26: 4c 89 ff mov %r15,%rdi + 440c29: ff d3 callq *%rbx + 440c2b: ba 03 00 00 00 mov $0x3,%edx + 440c30: be 02 00 00 00 mov $0x2,%esi + 440c35: 4c 89 f7 mov %r14,%rdi + 440c38: ff d3 callq *%rbx + 440c3a: ba 02 00 00 00 mov $0x2,%edx + 440c3f: be 01 00 00 00 mov $0x1,%esi + 440c44: 4c 89 ef mov %r13,%rdi + 440c47: ff d3 callq *%rbx + 440c49: 4d 8b 75 10 mov 0x10(%r13),%r14 + 440c4d: 4d 85 f6 test %r14,%r14 + 440c50: 0f 84 09 01 00 00 je 440d5f <__twalk+0x2bf> + 440c56: 49 83 7e 08 00 cmpq $0x0,0x8(%r14) + 440c5b: ba 03 00 00 00 mov $0x3,%edx + 440c60: 0f 84 32 0a 00 00 je 441698 <__twalk+0xbf8> + 440c66: 31 f6 xor %esi,%esi + 440c68: 4c 89 f7 mov %r14,%rdi + 440c6b: ff d3 callq *%rbx + 440c6d: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 440c71: 4d 85 ff test %r15,%r15 + 440c74: 74 61 je 440cd7 <__twalk+0x237> + 440c76: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) + 440c7b: ba 04 00 00 00 mov $0x4,%edx + 440c80: 0f 84 92 0c 00 00 je 441918 <__twalk+0xe78> + 440c86: 31 f6 xor %esi,%esi + 440c88: 4c 89 ff mov %r15,%rdi + 440c8b: ff d3 callq *%rbx + 440c8d: 49 8b 7f 08 mov 0x8(%r15),%rdi + 440c91: 48 85 ff test %rdi,%rdi + 440c94: 74 0d je 440ca3 <__twalk+0x203> + 440c96: ba 05 00 00 00 mov $0x5,%edx + 440c9b: 48 89 de mov %rbx,%rsi + 440c9e: e8 6d f0 ff ff callq 43fd10 + 440ca3: 4c 89 ff mov %r15,%rdi + 440ca6: ba 04 00 00 00 mov $0x4,%edx + 440cab: be 01 00 00 00 mov $0x1,%esi + 440cb0: ff d3 callq *%rbx + 440cb2: 49 8b 7f 10 mov 0x10(%r15),%rdi + 440cb6: 48 85 ff test %rdi,%rdi + 440cb9: 74 0d je 440cc8 <__twalk+0x228> + 440cbb: ba 05 00 00 00 mov $0x5,%edx + 440cc0: 48 89 de mov %rbx,%rsi + 440cc3: e8 48 f0 ff ff callq 43fd10 + 440cc8: ba 04 00 00 00 mov $0x4,%edx + 440ccd: be 02 00 00 00 mov $0x2,%esi + 440cd2: 4c 89 ff mov %r15,%rdi + 440cd5: ff d3 callq *%rbx + 440cd7: ba 03 00 00 00 mov $0x3,%edx + 440cdc: be 01 00 00 00 mov $0x1,%esi + 440ce1: 4c 89 f7 mov %r14,%rdi + 440ce4: ff d3 callq *%rbx + 440ce6: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 440cea: 4d 85 ff test %r15,%r15 + 440ced: 74 61 je 440d50 <__twalk+0x2b0> + 440cef: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) + 440cf4: ba 04 00 00 00 mov $0x4,%edx + 440cf9: 0f 84 f9 0b 00 00 je 4418f8 <__twalk+0xe58> + 440cff: 31 f6 xor %esi,%esi + 440d01: 4c 89 ff mov %r15,%rdi + 440d04: ff d3 callq *%rbx + 440d06: 49 8b 7f 08 mov 0x8(%r15),%rdi + 440d0a: 48 85 ff test %rdi,%rdi + 440d0d: 74 0d je 440d1c <__twalk+0x27c> + 440d0f: ba 05 00 00 00 mov $0x5,%edx + 440d14: 48 89 de mov %rbx,%rsi + 440d17: e8 f4 ef ff ff callq 43fd10 + 440d1c: 4c 89 ff mov %r15,%rdi + 440d1f: ba 04 00 00 00 mov $0x4,%edx + 440d24: be 01 00 00 00 mov $0x1,%esi + 440d29: ff d3 callq *%rbx + 440d2b: 49 8b 7f 10 mov 0x10(%r15),%rdi + 440d2f: 48 85 ff test %rdi,%rdi + 440d32: 74 0d je 440d41 <__twalk+0x2a1> + 440d34: ba 05 00 00 00 mov $0x5,%edx + 440d39: 48 89 de mov %rbx,%rsi + 440d3c: e8 cf ef ff ff callq 43fd10 + 440d41: ba 04 00 00 00 mov $0x4,%edx + 440d46: be 02 00 00 00 mov $0x2,%esi + 440d4b: 4c 89 ff mov %r15,%rdi + 440d4e: ff d3 callq *%rbx + 440d50: ba 03 00 00 00 mov $0x3,%edx + 440d55: be 02 00 00 00 mov $0x2,%esi + 440d5a: 4c 89 f7 mov %r14,%rdi + 440d5d: ff d3 callq *%rbx + 440d5f: ba 02 00 00 00 mov $0x2,%edx + 440d64: be 02 00 00 00 mov $0x2,%esi + 440d69: 4c 89 ef mov %r13,%rdi + 440d6c: ff d3 callq *%rbx + 440d6e: ba 01 00 00 00 mov $0x1,%edx + 440d73: be 01 00 00 00 mov $0x1,%esi + 440d78: 4c 89 e7 mov %r12,%rdi + 440d7b: ff d3 callq *%rbx + 440d7d: 4d 8b 6c 24 10 mov 0x10(%r12),%r13 + 440d82: 4d 85 ed test %r13,%r13 + 440d85: 0f 84 61 02 00 00 je 440fec <__twalk+0x54c> + 440d8b: 49 83 7d 08 00 cmpq $0x0,0x8(%r13) + 440d90: ba 02 00 00 00 mov $0x2,%edx + 440d95: 0f 84 1d 08 00 00 je 4415b8 <__twalk+0xb18> + 440d9b: 31 f6 xor %esi,%esi + 440d9d: 4c 89 ef mov %r13,%rdi + 440da0: ff d3 callq *%rbx + 440da2: 4d 8b 75 08 mov 0x8(%r13),%r14 + 440da6: 4d 85 f6 test %r14,%r14 + 440da9: 0f 84 09 01 00 00 je 440eb8 <__twalk+0x418> + 440daf: 49 83 7e 08 00 cmpq $0x0,0x8(%r14) + 440db4: ba 03 00 00 00 mov $0x3,%edx + 440db9: 0f 84 b9 08 00 00 je 441678 <__twalk+0xbd8> + 440dbf: 31 f6 xor %esi,%esi + 440dc1: 4c 89 f7 mov %r14,%rdi + 440dc4: ff d3 callq *%rbx + 440dc6: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 440dca: 4d 85 ff test %r15,%r15 + 440dcd: 74 61 je 440e30 <__twalk+0x390> + 440dcf: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) + 440dd4: ba 04 00 00 00 mov $0x4,%edx + 440dd9: 0f 84 d9 0a 00 00 je 4418b8 <__twalk+0xe18> + 440ddf: 31 f6 xor %esi,%esi + 440de1: 4c 89 ff mov %r15,%rdi + 440de4: ff d3 callq *%rbx + 440de6: 49 8b 7f 08 mov 0x8(%r15),%rdi + 440dea: 48 85 ff test %rdi,%rdi + 440ded: 74 0d je 440dfc <__twalk+0x35c> + 440def: ba 05 00 00 00 mov $0x5,%edx + 440df4: 48 89 de mov %rbx,%rsi + 440df7: e8 14 ef ff ff callq 43fd10 + 440dfc: 4c 89 ff mov %r15,%rdi + 440dff: ba 04 00 00 00 mov $0x4,%edx + 440e04: be 01 00 00 00 mov $0x1,%esi + 440e09: ff d3 callq *%rbx + 440e0b: 49 8b 7f 10 mov 0x10(%r15),%rdi + 440e0f: 48 85 ff test %rdi,%rdi + 440e12: 74 0d je 440e21 <__twalk+0x381> + 440e14: ba 05 00 00 00 mov $0x5,%edx + 440e19: 48 89 de mov %rbx,%rsi + 440e1c: e8 ef ee ff ff callq 43fd10 + 440e21: ba 04 00 00 00 mov $0x4,%edx + 440e26: be 02 00 00 00 mov $0x2,%esi + 440e2b: 4c 89 ff mov %r15,%rdi + 440e2e: ff d3 callq *%rbx + 440e30: ba 03 00 00 00 mov $0x3,%edx + 440e35: be 01 00 00 00 mov $0x1,%esi + 440e3a: 4c 89 f7 mov %r14,%rdi + 440e3d: ff d3 callq *%rbx + 440e3f: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 440e43: 4d 85 ff test %r15,%r15 + 440e46: 74 61 je 440ea9 <__twalk+0x409> + 440e48: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) + 440e4d: ba 04 00 00 00 mov $0x4,%edx + 440e52: 0f 84 40 0a 00 00 je 441898 <__twalk+0xdf8> + 440e58: 31 f6 xor %esi,%esi + 440e5a: 4c 89 ff mov %r15,%rdi + 440e5d: ff d3 callq *%rbx + 440e5f: 49 8b 7f 08 mov 0x8(%r15),%rdi + 440e63: 48 85 ff test %rdi,%rdi + 440e66: 74 0d je 440e75 <__twalk+0x3d5> + 440e68: ba 05 00 00 00 mov $0x5,%edx + 440e6d: 48 89 de mov %rbx,%rsi + 440e70: e8 9b ee ff ff callq 43fd10 + 440e75: 4c 89 ff mov %r15,%rdi + 440e78: ba 04 00 00 00 mov $0x4,%edx + 440e7d: be 01 00 00 00 mov $0x1,%esi + 440e82: ff d3 callq *%rbx + 440e84: 49 8b 7f 10 mov 0x10(%r15),%rdi + 440e88: 48 85 ff test %rdi,%rdi + 440e8b: 74 0d je 440e9a <__twalk+0x3fa> + 440e8d: ba 05 00 00 00 mov $0x5,%edx + 440e92: 48 89 de mov %rbx,%rsi + 440e95: e8 76 ee ff ff callq 43fd10 + 440e9a: ba 04 00 00 00 mov $0x4,%edx + 440e9f: be 02 00 00 00 mov $0x2,%esi + 440ea4: 4c 89 ff mov %r15,%rdi + 440ea7: ff d3 callq *%rbx + 440ea9: ba 03 00 00 00 mov $0x3,%edx + 440eae: be 02 00 00 00 mov $0x2,%esi + 440eb3: 4c 89 f7 mov %r14,%rdi + 440eb6: ff d3 callq *%rbx + 440eb8: ba 02 00 00 00 mov $0x2,%edx + 440ebd: be 01 00 00 00 mov $0x1,%esi + 440ec2: 4c 89 ef mov %r13,%rdi + 440ec5: ff d3 callq *%rbx + 440ec7: 4d 8b 75 10 mov 0x10(%r13),%r14 + 440ecb: 4d 85 f6 test %r14,%r14 + 440ece: 0f 84 09 01 00 00 je 440fdd <__twalk+0x53d> + 440ed4: 49 83 7e 08 00 cmpq $0x0,0x8(%r14) + 440ed9: ba 03 00 00 00 mov $0x3,%edx + 440ede: 0f 84 74 07 00 00 je 441658 <__twalk+0xbb8> + 440ee4: 31 f6 xor %esi,%esi + 440ee6: 4c 89 f7 mov %r14,%rdi + 440ee9: ff d3 callq *%rbx + 440eeb: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 440eef: 4d 85 ff test %r15,%r15 + 440ef2: 74 61 je 440f55 <__twalk+0x4b5> + 440ef4: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) + 440ef9: ba 04 00 00 00 mov $0x4,%edx + 440efe: 0f 84 54 09 00 00 je 441858 <__twalk+0xdb8> + 440f04: 31 f6 xor %esi,%esi + 440f06: 4c 89 ff mov %r15,%rdi + 440f09: ff d3 callq *%rbx + 440f0b: 49 8b 7f 08 mov 0x8(%r15),%rdi + 440f0f: 48 85 ff test %rdi,%rdi + 440f12: 74 0d je 440f21 <__twalk+0x481> + 440f14: ba 05 00 00 00 mov $0x5,%edx + 440f19: 48 89 de mov %rbx,%rsi + 440f1c: e8 ef ed ff ff callq 43fd10 + 440f21: 4c 89 ff mov %r15,%rdi + 440f24: ba 04 00 00 00 mov $0x4,%edx + 440f29: be 01 00 00 00 mov $0x1,%esi + 440f2e: ff d3 callq *%rbx + 440f30: 49 8b 7f 10 mov 0x10(%r15),%rdi + 440f34: 48 85 ff test %rdi,%rdi + 440f37: 74 0d je 440f46 <__twalk+0x4a6> + 440f39: ba 05 00 00 00 mov $0x5,%edx + 440f3e: 48 89 de mov %rbx,%rsi + 440f41: e8 ca ed ff ff callq 43fd10 + 440f46: ba 04 00 00 00 mov $0x4,%edx + 440f4b: be 02 00 00 00 mov $0x2,%esi + 440f50: 4c 89 ff mov %r15,%rdi + 440f53: ff d3 callq *%rbx + 440f55: ba 03 00 00 00 mov $0x3,%edx + 440f5a: be 01 00 00 00 mov $0x1,%esi + 440f5f: 4c 89 f7 mov %r14,%rdi + 440f62: ff d3 callq *%rbx + 440f64: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 440f68: 4d 85 ff test %r15,%r15 + 440f6b: 74 61 je 440fce <__twalk+0x52e> + 440f6d: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) + 440f72: ba 04 00 00 00 mov $0x4,%edx + 440f77: 0f 84 bb 08 00 00 je 441838 <__twalk+0xd98> + 440f7d: 31 f6 xor %esi,%esi + 440f7f: 4c 89 ff mov %r15,%rdi + 440f82: ff d3 callq *%rbx + 440f84: 49 8b 7f 08 mov 0x8(%r15),%rdi + 440f88: 48 85 ff test %rdi,%rdi + 440f8b: 74 0d je 440f9a <__twalk+0x4fa> + 440f8d: ba 05 00 00 00 mov $0x5,%edx + 440f92: 48 89 de mov %rbx,%rsi + 440f95: e8 76 ed ff ff callq 43fd10 + 440f9a: 4c 89 ff mov %r15,%rdi + 440f9d: ba 04 00 00 00 mov $0x4,%edx + 440fa2: be 01 00 00 00 mov $0x1,%esi + 440fa7: ff d3 callq *%rbx + 440fa9: 49 8b 7f 10 mov 0x10(%r15),%rdi + 440fad: 48 85 ff test %rdi,%rdi + 440fb0: 74 0d je 440fbf <__twalk+0x51f> + 440fb2: ba 05 00 00 00 mov $0x5,%edx + 440fb7: 48 89 de mov %rbx,%rsi + 440fba: e8 51 ed ff ff callq 43fd10 + 440fbf: ba 04 00 00 00 mov $0x4,%edx + 440fc4: be 02 00 00 00 mov $0x2,%esi + 440fc9: 4c 89 ff mov %r15,%rdi + 440fcc: ff d3 callq *%rbx + 440fce: ba 03 00 00 00 mov $0x3,%edx + 440fd3: be 02 00 00 00 mov $0x2,%esi + 440fd8: 4c 89 f7 mov %r14,%rdi + 440fdb: ff d3 callq *%rbx + 440fdd: ba 02 00 00 00 mov $0x2,%edx + 440fe2: be 02 00 00 00 mov $0x2,%esi + 440fe7: 4c 89 ef mov %r13,%rdi + 440fea: ff d3 callq *%rbx + 440fec: ba 01 00 00 00 mov $0x1,%edx + 440ff1: be 02 00 00 00 mov $0x2,%esi + 440ff6: 4c 89 e7 mov %r12,%rdi + 440ff9: ff d3 callq *%rbx + 440ffb: 31 d2 xor %edx,%edx + 440ffd: be 01 00 00 00 mov $0x1,%esi + 441002: 48 89 ef mov %rbp,%rdi + 441005: ff d3 callq *%rbx + 441007: 4c 8b 65 10 mov 0x10(%rbp),%r12 + 44100b: 4d 85 e4 test %r12,%r12 + 44100e: 0f 84 14 05 00 00 je 441528 <__twalk+0xa88> + 441014: 49 83 7c 24 08 00 cmpq $0x0,0x8(%r12) + 44101a: ba 01 00 00 00 mov $0x1,%edx + 44101f: 0f 84 3b 05 00 00 je 441560 <__twalk+0xac0> + 441025: 31 f6 xor %esi,%esi + 441027: 4c 89 e7 mov %r12,%rdi + 44102a: ff d3 callq *%rbx + 44102c: 4d 8b 6c 24 08 mov 0x8(%r12),%r13 + 441031: 4d 85 ed test %r13,%r13 + 441034: 0f 84 61 02 00 00 je 44129b <__twalk+0x7fb> + 44103a: 49 83 7d 08 00 cmpq $0x0,0x8(%r13) + 44103f: ba 02 00 00 00 mov $0x2,%edx + 441044: 0f 84 8e 05 00 00 je 4415d8 <__twalk+0xb38> + 44104a: 31 f6 xor %esi,%esi + 44104c: 4c 89 ef mov %r13,%rdi + 44104f: ff d3 callq *%rbx + 441051: 4d 8b 75 08 mov 0x8(%r13),%r14 + 441055: 4d 85 f6 test %r14,%r14 + 441058: 0f 84 09 01 00 00 je 441167 <__twalk+0x6c7> + 44105e: 49 83 7e 08 00 cmpq $0x0,0x8(%r14) + 441063: ba 03 00 00 00 mov $0x3,%edx + 441068: 0f 84 aa 06 00 00 je 441718 <__twalk+0xc78> + 44106e: 31 f6 xor %esi,%esi + 441070: 4c 89 f7 mov %r14,%rdi + 441073: ff d3 callq *%rbx + 441075: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 441079: 4d 85 ff test %r15,%r15 + 44107c: 74 61 je 4410df <__twalk+0x63f> + 44107e: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) + 441083: ba 04 00 00 00 mov $0x4,%edx + 441088: 0f 84 ca 06 00 00 je 441758 <__twalk+0xcb8> + 44108e: 31 f6 xor %esi,%esi + 441090: 4c 89 ff mov %r15,%rdi + 441093: ff d3 callq *%rbx + 441095: 49 8b 7f 08 mov 0x8(%r15),%rdi + 441099: 48 85 ff test %rdi,%rdi + 44109c: 74 0d je 4410ab <__twalk+0x60b> + 44109e: ba 05 00 00 00 mov $0x5,%edx + 4410a3: 48 89 de mov %rbx,%rsi + 4410a6: e8 65 ec ff ff callq 43fd10 + 4410ab: 4c 89 ff mov %r15,%rdi + 4410ae: ba 04 00 00 00 mov $0x4,%edx + 4410b3: be 01 00 00 00 mov $0x1,%esi + 4410b8: ff d3 callq *%rbx + 4410ba: 49 8b 7f 10 mov 0x10(%r15),%rdi + 4410be: 48 85 ff test %rdi,%rdi + 4410c1: 74 0d je 4410d0 <__twalk+0x630> + 4410c3: ba 05 00 00 00 mov $0x5,%edx + 4410c8: 48 89 de mov %rbx,%rsi + 4410cb: e8 40 ec ff ff callq 43fd10 + 4410d0: ba 04 00 00 00 mov $0x4,%edx + 4410d5: be 02 00 00 00 mov $0x2,%esi + 4410da: 4c 89 ff mov %r15,%rdi + 4410dd: ff d3 callq *%rbx + 4410df: ba 03 00 00 00 mov $0x3,%edx + 4410e4: be 01 00 00 00 mov $0x1,%esi + 4410e9: 4c 89 f7 mov %r14,%rdi + 4410ec: ff d3 callq *%rbx + 4410ee: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 4410f2: 4d 85 ff test %r15,%r15 + 4410f5: 74 61 je 441158 <__twalk+0x6b8> + 4410f7: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) + 4410fc: ba 04 00 00 00 mov $0x4,%edx + 441101: 0f 84 31 06 00 00 je 441738 <__twalk+0xc98> + 441107: 31 f6 xor %esi,%esi + 441109: 4c 89 ff mov %r15,%rdi + 44110c: ff d3 callq *%rbx + 44110e: 49 8b 7f 08 mov 0x8(%r15),%rdi + 441112: 48 85 ff test %rdi,%rdi + 441115: 74 0d je 441124 <__twalk+0x684> + 441117: ba 05 00 00 00 mov $0x5,%edx + 44111c: 48 89 de mov %rbx,%rsi + 44111f: e8 ec eb ff ff callq 43fd10 + 441124: 4c 89 ff mov %r15,%rdi + 441127: ba 04 00 00 00 mov $0x4,%edx + 44112c: be 01 00 00 00 mov $0x1,%esi + 441131: ff d3 callq *%rbx + 441133: 49 8b 7f 10 mov 0x10(%r15),%rdi + 441137: 48 85 ff test %rdi,%rdi + 44113a: 74 0d je 441149 <__twalk+0x6a9> + 44113c: ba 05 00 00 00 mov $0x5,%edx + 441141: 48 89 de mov %rbx,%rsi + 441144: e8 c7 eb ff ff callq 43fd10 + 441149: ba 04 00 00 00 mov $0x4,%edx + 44114e: be 02 00 00 00 mov $0x2,%esi + 441153: 4c 89 ff mov %r15,%rdi + 441156: ff d3 callq *%rbx + 441158: ba 03 00 00 00 mov $0x3,%edx + 44115d: be 02 00 00 00 mov $0x2,%esi + 441162: 4c 89 f7 mov %r14,%rdi + 441165: ff d3 callq *%rbx + 441167: ba 02 00 00 00 mov $0x2,%edx + 44116c: be 01 00 00 00 mov $0x1,%esi + 441171: 4c 89 ef mov %r13,%rdi + 441174: ff d3 callq *%rbx + 441176: 4d 8b 75 10 mov 0x10(%r13),%r14 + 44117a: 4d 85 f6 test %r14,%r14 + 44117d: 0f 84 09 01 00 00 je 44128c <__twalk+0x7ec> + 441183: 49 83 7e 08 00 cmpq $0x0,0x8(%r14) + 441188: ba 03 00 00 00 mov $0x3,%edx + 44118d: 0f 84 65 05 00 00 je 4416f8 <__twalk+0xc58> + 441193: 31 f6 xor %esi,%esi + 441195: 4c 89 f7 mov %r14,%rdi + 441198: ff d3 callq *%rbx + 44119a: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 44119e: 4d 85 ff test %r15,%r15 + 4411a1: 74 61 je 441204 <__twalk+0x764> + 4411a3: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) + 4411a8: ba 04 00 00 00 mov $0x4,%edx + 4411ad: 0f 84 65 06 00 00 je 441818 <__twalk+0xd78> + 4411b3: 31 f6 xor %esi,%esi + 4411b5: 4c 89 ff mov %r15,%rdi + 4411b8: ff d3 callq *%rbx + 4411ba: 49 8b 7f 08 mov 0x8(%r15),%rdi + 4411be: 48 85 ff test %rdi,%rdi + 4411c1: 74 0d je 4411d0 <__twalk+0x730> + 4411c3: ba 05 00 00 00 mov $0x5,%edx + 4411c8: 48 89 de mov %rbx,%rsi + 4411cb: e8 40 eb ff ff callq 43fd10 + 4411d0: 4c 89 ff mov %r15,%rdi + 4411d3: ba 04 00 00 00 mov $0x4,%edx + 4411d8: be 01 00 00 00 mov $0x1,%esi + 4411dd: ff d3 callq *%rbx + 4411df: 49 8b 7f 10 mov 0x10(%r15),%rdi + 4411e3: 48 85 ff test %rdi,%rdi + 4411e6: 74 0d je 4411f5 <__twalk+0x755> + 4411e8: ba 05 00 00 00 mov $0x5,%edx + 4411ed: 48 89 de mov %rbx,%rsi + 4411f0: e8 1b eb ff ff callq 43fd10 + 4411f5: ba 04 00 00 00 mov $0x4,%edx + 4411fa: be 02 00 00 00 mov $0x2,%esi + 4411ff: 4c 89 ff mov %r15,%rdi + 441202: ff d3 callq *%rbx + 441204: ba 03 00 00 00 mov $0x3,%edx + 441209: be 01 00 00 00 mov $0x1,%esi + 44120e: 4c 89 f7 mov %r14,%rdi + 441211: ff d3 callq *%rbx + 441213: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 441217: 4d 85 ff test %r15,%r15 + 44121a: 74 61 je 44127d <__twalk+0x7dd> + 44121c: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) + 441221: ba 04 00 00 00 mov $0x4,%edx + 441226: 0f 84 cc 05 00 00 je 4417f8 <__twalk+0xd58> + 44122c: 31 f6 xor %esi,%esi + 44122e: 4c 89 ff mov %r15,%rdi + 441231: ff d3 callq *%rbx + 441233: 49 8b 7f 08 mov 0x8(%r15),%rdi + 441237: 48 85 ff test %rdi,%rdi + 44123a: 74 0d je 441249 <__twalk+0x7a9> + 44123c: ba 05 00 00 00 mov $0x5,%edx + 441241: 48 89 de mov %rbx,%rsi + 441244: e8 c7 ea ff ff callq 43fd10 + 441249: 4c 89 ff mov %r15,%rdi + 44124c: ba 04 00 00 00 mov $0x4,%edx + 441251: be 01 00 00 00 mov $0x1,%esi + 441256: ff d3 callq *%rbx + 441258: 49 8b 7f 10 mov 0x10(%r15),%rdi + 44125c: 48 85 ff test %rdi,%rdi + 44125f: 74 0d je 44126e <__twalk+0x7ce> + 441261: ba 05 00 00 00 mov $0x5,%edx + 441266: 48 89 de mov %rbx,%rsi + 441269: e8 a2 ea ff ff callq 43fd10 + 44126e: ba 04 00 00 00 mov $0x4,%edx + 441273: be 02 00 00 00 mov $0x2,%esi + 441278: 4c 89 ff mov %r15,%rdi + 44127b: ff d3 callq *%rbx + 44127d: ba 03 00 00 00 mov $0x3,%edx + 441282: be 02 00 00 00 mov $0x2,%esi + 441287: 4c 89 f7 mov %r14,%rdi + 44128a: ff d3 callq *%rbx + 44128c: ba 02 00 00 00 mov $0x2,%edx + 441291: be 02 00 00 00 mov $0x2,%esi + 441296: 4c 89 ef mov %r13,%rdi + 441299: ff d3 callq *%rbx + 44129b: ba 01 00 00 00 mov $0x1,%edx + 4412a0: be 01 00 00 00 mov $0x1,%esi + 4412a5: 4c 89 e7 mov %r12,%rdi + 4412a8: ff d3 callq *%rbx + 4412aa: 4d 8b 6c 24 10 mov 0x10(%r12),%r13 + 4412af: 4d 85 ed test %r13,%r13 + 4412b2: 0f 84 61 02 00 00 je 441519 <__twalk+0xa79> + 4412b8: 49 83 7d 08 00 cmpq $0x0,0x8(%r13) + 4412bd: ba 02 00 00 00 mov $0x2,%edx + 4412c2: 0f 84 50 03 00 00 je 441618 <__twalk+0xb78> + 4412c8: 31 f6 xor %esi,%esi + 4412ca: 4c 89 ef mov %r13,%rdi + 4412cd: ff d3 callq *%rbx + 4412cf: 4d 8b 75 08 mov 0x8(%r13),%r14 + 4412d3: 4d 85 f6 test %r14,%r14 + 4412d6: 0f 84 09 01 00 00 je 4413e5 <__twalk+0x945> + 4412dc: 49 83 7e 08 00 cmpq $0x0,0x8(%r14) + 4412e1: ba 03 00 00 00 mov $0x3,%edx + 4412e6: 0f 84 ec 03 00 00 je 4416d8 <__twalk+0xc38> + 4412ec: 31 f6 xor %esi,%esi + 4412ee: 4c 89 f7 mov %r14,%rdi + 4412f1: ff d3 callq *%rbx + 4412f3: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 4412f7: 4d 85 ff test %r15,%r15 + 4412fa: 74 61 je 44135d <__twalk+0x8bd> + 4412fc: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) + 441301: ba 04 00 00 00 mov $0x4,%edx + 441306: 0f 84 cc 04 00 00 je 4417d8 <__twalk+0xd38> + 44130c: 31 f6 xor %esi,%esi + 44130e: 4c 89 ff mov %r15,%rdi + 441311: ff d3 callq *%rbx + 441313: 49 8b 7f 08 mov 0x8(%r15),%rdi + 441317: 48 85 ff test %rdi,%rdi + 44131a: 74 0d je 441329 <__twalk+0x889> + 44131c: ba 05 00 00 00 mov $0x5,%edx + 441321: 48 89 de mov %rbx,%rsi + 441324: e8 e7 e9 ff ff callq 43fd10 + 441329: 4c 89 ff mov %r15,%rdi + 44132c: ba 04 00 00 00 mov $0x4,%edx + 441331: be 01 00 00 00 mov $0x1,%esi + 441336: ff d3 callq *%rbx + 441338: 49 8b 7f 10 mov 0x10(%r15),%rdi + 44133c: 48 85 ff test %rdi,%rdi + 44133f: 74 0d je 44134e <__twalk+0x8ae> + 441341: ba 05 00 00 00 mov $0x5,%edx + 441346: 48 89 de mov %rbx,%rsi + 441349: e8 c2 e9 ff ff callq 43fd10 + 44134e: ba 04 00 00 00 mov $0x4,%edx + 441353: be 02 00 00 00 mov $0x2,%esi + 441358: 4c 89 ff mov %r15,%rdi + 44135b: ff d3 callq *%rbx + 44135d: ba 03 00 00 00 mov $0x3,%edx + 441362: be 01 00 00 00 mov $0x1,%esi + 441367: 4c 89 f7 mov %r14,%rdi + 44136a: ff d3 callq *%rbx + 44136c: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 441370: 4d 85 ff test %r15,%r15 + 441373: 74 61 je 4413d6 <__twalk+0x936> + 441375: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) + 44137a: ba 04 00 00 00 mov $0x4,%edx + 44137f: 0f 84 33 04 00 00 je 4417b8 <__twalk+0xd18> + 441385: 31 f6 xor %esi,%esi + 441387: 4c 89 ff mov %r15,%rdi + 44138a: ff d3 callq *%rbx + 44138c: 49 8b 7f 08 mov 0x8(%r15),%rdi + 441390: 48 85 ff test %rdi,%rdi + 441393: 74 0d je 4413a2 <__twalk+0x902> + 441395: ba 05 00 00 00 mov $0x5,%edx + 44139a: 48 89 de mov %rbx,%rsi + 44139d: e8 6e e9 ff ff callq 43fd10 + 4413a2: 4c 89 ff mov %r15,%rdi + 4413a5: ba 04 00 00 00 mov $0x4,%edx + 4413aa: be 01 00 00 00 mov $0x1,%esi + 4413af: ff d3 callq *%rbx + 4413b1: 49 8b 7f 10 mov 0x10(%r15),%rdi + 4413b5: 48 85 ff test %rdi,%rdi + 4413b8: 74 0d je 4413c7 <__twalk+0x927> + 4413ba: ba 05 00 00 00 mov $0x5,%edx + 4413bf: 48 89 de mov %rbx,%rsi + 4413c2: e8 49 e9 ff ff callq 43fd10 + 4413c7: ba 04 00 00 00 mov $0x4,%edx + 4413cc: be 02 00 00 00 mov $0x2,%esi + 4413d1: 4c 89 ff mov %r15,%rdi + 4413d4: ff d3 callq *%rbx + 4413d6: ba 03 00 00 00 mov $0x3,%edx + 4413db: be 02 00 00 00 mov $0x2,%esi + 4413e0: 4c 89 f7 mov %r14,%rdi + 4413e3: ff d3 callq *%rbx + 4413e5: ba 02 00 00 00 mov $0x2,%edx + 4413ea: be 01 00 00 00 mov $0x1,%esi + 4413ef: 4c 89 ef mov %r13,%rdi + 4413f2: ff d3 callq *%rbx + 4413f4: 4d 8b 75 10 mov 0x10(%r13),%r14 + 4413f8: 4d 85 f6 test %r14,%r14 + 4413fb: 0f 84 09 01 00 00 je 44150a <__twalk+0xa6a> + 441401: 49 83 7e 08 00 cmpq $0x0,0x8(%r14) + 441406: ba 03 00 00 00 mov $0x3,%edx + 44140b: 0f 84 a7 02 00 00 je 4416b8 <__twalk+0xc18> + 441411: 31 f6 xor %esi,%esi + 441413: 4c 89 f7 mov %r14,%rdi + 441416: ff d3 callq *%rbx + 441418: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 44141c: 4d 85 ff test %r15,%r15 + 44141f: 74 61 je 441482 <__twalk+0x9e2> + 441421: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) + 441426: ba 04 00 00 00 mov $0x4,%edx + 44142b: 0f 84 67 03 00 00 je 441798 <__twalk+0xcf8> + 441431: 31 f6 xor %esi,%esi + 441433: 4c 89 ff mov %r15,%rdi + 441436: ff d3 callq *%rbx + 441438: 49 8b 7f 08 mov 0x8(%r15),%rdi + 44143c: 48 85 ff test %rdi,%rdi + 44143f: 74 0d je 44144e <__twalk+0x9ae> + 441441: ba 05 00 00 00 mov $0x5,%edx + 441446: 48 89 de mov %rbx,%rsi + 441449: e8 c2 e8 ff ff callq 43fd10 + 44144e: 4c 89 ff mov %r15,%rdi + 441451: ba 04 00 00 00 mov $0x4,%edx + 441456: be 01 00 00 00 mov $0x1,%esi + 44145b: ff d3 callq *%rbx + 44145d: 49 8b 7f 10 mov 0x10(%r15),%rdi + 441461: 48 85 ff test %rdi,%rdi + 441464: 74 0d je 441473 <__twalk+0x9d3> + 441466: ba 05 00 00 00 mov $0x5,%edx + 44146b: 48 89 de mov %rbx,%rsi + 44146e: e8 9d e8 ff ff callq 43fd10 + 441473: ba 04 00 00 00 mov $0x4,%edx + 441478: be 02 00 00 00 mov $0x2,%esi + 44147d: 4c 89 ff mov %r15,%rdi + 441480: ff d3 callq *%rbx + 441482: ba 03 00 00 00 mov $0x3,%edx + 441487: be 01 00 00 00 mov $0x1,%esi + 44148c: 4c 89 f7 mov %r14,%rdi + 44148f: ff d3 callq *%rbx + 441491: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 441495: 4d 85 ff test %r15,%r15 + 441498: 74 61 je 4414fb <__twalk+0xa5b> + 44149a: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) + 44149f: ba 04 00 00 00 mov $0x4,%edx + 4414a4: 0f 84 ce 02 00 00 je 441778 <__twalk+0xcd8> + 4414aa: 31 f6 xor %esi,%esi + 4414ac: 4c 89 ff mov %r15,%rdi + 4414af: ff d3 callq *%rbx + 4414b1: 49 8b 7f 08 mov 0x8(%r15),%rdi + 4414b5: 48 85 ff test %rdi,%rdi + 4414b8: 74 0d je 4414c7 <__twalk+0xa27> + 4414ba: ba 05 00 00 00 mov $0x5,%edx + 4414bf: 48 89 de mov %rbx,%rsi + 4414c2: e8 49 e8 ff ff callq 43fd10 + 4414c7: 4c 89 ff mov %r15,%rdi + 4414ca: ba 04 00 00 00 mov $0x4,%edx + 4414cf: be 01 00 00 00 mov $0x1,%esi + 4414d4: ff d3 callq *%rbx + 4414d6: 49 8b 7f 10 mov 0x10(%r15),%rdi + 4414da: 48 85 ff test %rdi,%rdi + 4414dd: 74 0d je 4414ec <__twalk+0xa4c> + 4414df: ba 05 00 00 00 mov $0x5,%edx + 4414e4: 48 89 de mov %rbx,%rsi + 4414e7: e8 24 e8 ff ff callq 43fd10 + 4414ec: ba 04 00 00 00 mov $0x4,%edx + 4414f1: be 02 00 00 00 mov $0x2,%esi + 4414f6: 4c 89 ff mov %r15,%rdi + 4414f9: ff d3 callq *%rbx + 4414fb: ba 03 00 00 00 mov $0x3,%edx + 441500: be 02 00 00 00 mov $0x2,%esi + 441505: 4c 89 f7 mov %r14,%rdi + 441508: ff d3 callq *%rbx + 44150a: ba 02 00 00 00 mov $0x2,%edx + 44150f: be 02 00 00 00 mov $0x2,%esi + 441514: 4c 89 ef mov %r13,%rdi + 441517: ff d3 callq *%rbx + 441519: ba 01 00 00 00 mov $0x1,%edx + 44151e: be 02 00 00 00 mov $0x2,%esi + 441523: 4c 89 e7 mov %r12,%rdi + 441526: ff d3 callq *%rbx + 441528: 31 d2 xor %edx,%edx + 44152a: be 02 00 00 00 mov $0x2,%esi + 44152f: 48 89 ef mov %rbp,%rdi + 441532: 48 89 d8 mov %rbx,%rax + 441535: 48 83 c4 08 add $0x8,%rsp + 441539: 5b pop %rbx + 44153a: 5d pop %rbp + 44153b: 41 5c pop %r12 + 44153d: 41 5d pop %r13 + 44153f: 41 5e pop %r14 + 441541: 41 5f pop %r15 + 441543: ff e0 jmpq *%rax + 441545: 0f 1f 00 nopl (%rax) + 441548: 48 83 c4 08 add $0x8,%rsp + 44154c: 5b pop %rbx + 44154d: 5d pop %rbp + 44154e: 41 5c pop %r12 + 441550: 41 5d pop %r13 + 441552: 41 5e pop %r14 + 441554: 41 5f pop %r15 + 441556: c3 retq + 441557: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) + 44155e: 00 00 + 441560: 49 83 7c 24 10 00 cmpq $0x0,0x10(%r12) + 441566: 0f 85 b9 fa ff ff jne 441025 <__twalk+0x585> + 44156c: be 03 00 00 00 mov $0x3,%esi + 441571: 4c 89 e7 mov %r12,%rdi + 441574: ff d3 callq *%rbx + 441576: eb b0 jmp 441528 <__twalk+0xa88> + 441578: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) + 44157f: 00 + 441580: 49 83 7c 24 10 00 cmpq $0x0,0x10(%r12) + 441586: 0f 85 6c f5 ff ff jne 440af8 <__twalk+0x58> + 44158c: be 03 00 00 00 mov $0x3,%esi + 441591: 4c 89 e7 mov %r12,%rdi + 441594: ff d3 callq *%rbx + 441596: e9 60 fa ff ff jmpq 440ffb <__twalk+0x55b> + 44159b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) + 4415a0: 31 d2 xor %edx,%edx + 4415a2: 48 83 7f 10 00 cmpq $0x0,0x10(%rdi) + 4415a7: be 03 00 00 00 mov $0x3,%esi + 4415ac: 0f 85 1c f5 ff ff jne 440ace <__twalk+0x2e> + 4415b2: eb 81 jmp 441535 <__twalk+0xa95> + 4415b4: 0f 1f 40 00 nopl 0x0(%rax) + 4415b8: 49 83 7d 10 00 cmpq $0x0,0x10(%r13) + 4415bd: 0f 85 d8 f7 ff ff jne 440d9b <__twalk+0x2fb> + 4415c3: be 03 00 00 00 mov $0x3,%esi + 4415c8: 4c 89 ef mov %r13,%rdi + 4415cb: ff d3 callq *%rbx + 4415cd: e9 1a fa ff ff jmpq 440fec <__twalk+0x54c> + 4415d2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4415d8: 49 83 7d 10 00 cmpq $0x0,0x10(%r13) + 4415dd: 0f 85 67 fa ff ff jne 44104a <__twalk+0x5aa> + 4415e3: be 03 00 00 00 mov $0x3,%esi + 4415e8: 4c 89 ef mov %r13,%rdi + 4415eb: ff d3 callq *%rbx + 4415ed: e9 a9 fc ff ff jmpq 44129b <__twalk+0x7fb> + 4415f2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4415f8: 49 83 7d 10 00 cmpq $0x0,0x10(%r13) + 4415fd: 0f 85 1a f5 ff ff jne 440b1d <__twalk+0x7d> + 441603: be 03 00 00 00 mov $0x3,%esi + 441608: 4c 89 ef mov %r13,%rdi + 44160b: ff d3 callq *%rbx + 44160d: e9 5c f7 ff ff jmpq 440d6e <__twalk+0x2ce> + 441612: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 441618: 49 83 7d 10 00 cmpq $0x0,0x10(%r13) + 44161d: 0f 85 a5 fc ff ff jne 4412c8 <__twalk+0x828> + 441623: be 03 00 00 00 mov $0x3,%esi + 441628: 4c 89 ef mov %r13,%rdi + 44162b: ff d3 callq *%rbx + 44162d: e9 e7 fe ff ff jmpq 441519 <__twalk+0xa79> + 441632: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 441638: 49 83 7e 10 00 cmpq $0x0,0x10(%r14) + 44163d: 0f 85 fe f4 ff ff jne 440b41 <__twalk+0xa1> + 441643: be 03 00 00 00 mov $0x3,%esi + 441648: 4c 89 f7 mov %r14,%rdi + 44164b: ff d3 callq *%rbx + 44164d: e9 e8 f5 ff ff jmpq 440c3a <__twalk+0x19a> + 441652: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 441658: 49 83 7e 10 00 cmpq $0x0,0x10(%r14) + 44165d: 0f 85 81 f8 ff ff jne 440ee4 <__twalk+0x444> + 441663: be 03 00 00 00 mov $0x3,%esi + 441668: 4c 89 f7 mov %r14,%rdi + 44166b: ff d3 callq *%rbx + 44166d: e9 6b f9 ff ff jmpq 440fdd <__twalk+0x53d> + 441672: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 441678: 49 83 7e 10 00 cmpq $0x0,0x10(%r14) + 44167d: 0f 85 3c f7 ff ff jne 440dbf <__twalk+0x31f> + 441683: be 03 00 00 00 mov $0x3,%esi + 441688: 4c 89 f7 mov %r14,%rdi + 44168b: ff d3 callq *%rbx + 44168d: e9 26 f8 ff ff jmpq 440eb8 <__twalk+0x418> + 441692: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 441698: 49 83 7e 10 00 cmpq $0x0,0x10(%r14) + 44169d: 0f 85 c3 f5 ff ff jne 440c66 <__twalk+0x1c6> + 4416a3: be 03 00 00 00 mov $0x3,%esi + 4416a8: 4c 89 f7 mov %r14,%rdi + 4416ab: ff d3 callq *%rbx + 4416ad: e9 ad f6 ff ff jmpq 440d5f <__twalk+0x2bf> + 4416b2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4416b8: 49 83 7e 10 00 cmpq $0x0,0x10(%r14) + 4416bd: 0f 85 4e fd ff ff jne 441411 <__twalk+0x971> + 4416c3: be 03 00 00 00 mov $0x3,%esi + 4416c8: 4c 89 f7 mov %r14,%rdi + 4416cb: ff d3 callq *%rbx + 4416cd: e9 38 fe ff ff jmpq 44150a <__twalk+0xa6a> + 4416d2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4416d8: 49 83 7e 10 00 cmpq $0x0,0x10(%r14) + 4416dd: 0f 85 09 fc ff ff jne 4412ec <__twalk+0x84c> + 4416e3: be 03 00 00 00 mov $0x3,%esi + 4416e8: 4c 89 f7 mov %r14,%rdi + 4416eb: ff d3 callq *%rbx + 4416ed: e9 f3 fc ff ff jmpq 4413e5 <__twalk+0x945> + 4416f2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4416f8: 49 83 7e 10 00 cmpq $0x0,0x10(%r14) + 4416fd: 0f 85 90 fa ff ff jne 441193 <__twalk+0x6f3> + 441703: be 03 00 00 00 mov $0x3,%esi + 441708: 4c 89 f7 mov %r14,%rdi + 44170b: ff d3 callq *%rbx + 44170d: e9 7a fb ff ff jmpq 44128c <__twalk+0x7ec> + 441712: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 441718: 49 83 7e 10 00 cmpq $0x0,0x10(%r14) + 44171d: 0f 85 4b f9 ff ff jne 44106e <__twalk+0x5ce> + 441723: be 03 00 00 00 mov $0x3,%esi + 441728: 4c 89 f7 mov %r14,%rdi + 44172b: ff d3 callq *%rbx + 44172d: e9 35 fa ff ff jmpq 441167 <__twalk+0x6c7> + 441732: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 441738: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) + 44173d: 0f 85 c4 f9 ff ff jne 441107 <__twalk+0x667> + 441743: be 03 00 00 00 mov $0x3,%esi + 441748: 4c 89 ff mov %r15,%rdi + 44174b: ff d3 callq *%rbx + 44174d: e9 06 fa ff ff jmpq 441158 <__twalk+0x6b8> + 441752: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 441758: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) + 44175d: 0f 85 2b f9 ff ff jne 44108e <__twalk+0x5ee> + 441763: be 03 00 00 00 mov $0x3,%esi + 441768: 4c 89 ff mov %r15,%rdi + 44176b: ff d3 callq *%rbx + 44176d: e9 6d f9 ff ff jmpq 4410df <__twalk+0x63f> + 441772: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 441778: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) + 44177d: 0f 85 27 fd ff ff jne 4414aa <__twalk+0xa0a> + 441783: be 03 00 00 00 mov $0x3,%esi + 441788: 4c 89 ff mov %r15,%rdi + 44178b: ff d3 callq *%rbx + 44178d: e9 69 fd ff ff jmpq 4414fb <__twalk+0xa5b> + 441792: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 441798: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) + 44179d: 0f 85 8e fc ff ff jne 441431 <__twalk+0x991> + 4417a3: be 03 00 00 00 mov $0x3,%esi + 4417a8: 4c 89 ff mov %r15,%rdi + 4417ab: ff d3 callq *%rbx + 4417ad: e9 d0 fc ff ff jmpq 441482 <__twalk+0x9e2> + 4417b2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4417b8: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) + 4417bd: 0f 85 c2 fb ff ff jne 441385 <__twalk+0x8e5> + 4417c3: be 03 00 00 00 mov $0x3,%esi + 4417c8: 4c 89 ff mov %r15,%rdi + 4417cb: ff d3 callq *%rbx + 4417cd: e9 04 fc ff ff jmpq 4413d6 <__twalk+0x936> + 4417d2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4417d8: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) + 4417dd: 0f 85 29 fb ff ff jne 44130c <__twalk+0x86c> + 4417e3: be 03 00 00 00 mov $0x3,%esi + 4417e8: 4c 89 ff mov %r15,%rdi + 4417eb: ff d3 callq *%rbx + 4417ed: e9 6b fb ff ff jmpq 44135d <__twalk+0x8bd> + 4417f2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4417f8: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) + 4417fd: 0f 85 29 fa ff ff jne 44122c <__twalk+0x78c> + 441803: be 03 00 00 00 mov $0x3,%esi + 441808: 4c 89 ff mov %r15,%rdi + 44180b: ff d3 callq *%rbx + 44180d: e9 6b fa ff ff jmpq 44127d <__twalk+0x7dd> + 441812: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 441818: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) + 44181d: 0f 85 90 f9 ff ff jne 4411b3 <__twalk+0x713> + 441823: be 03 00 00 00 mov $0x3,%esi + 441828: 4c 89 ff mov %r15,%rdi + 44182b: ff d3 callq *%rbx + 44182d: e9 d2 f9 ff ff jmpq 441204 <__twalk+0x764> + 441832: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 441838: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) + 44183d: 0f 85 3a f7 ff ff jne 440f7d <__twalk+0x4dd> + 441843: be 03 00 00 00 mov $0x3,%esi + 441848: 4c 89 ff mov %r15,%rdi + 44184b: ff d3 callq *%rbx + 44184d: e9 7c f7 ff ff jmpq 440fce <__twalk+0x52e> + 441852: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 441858: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) + 44185d: 0f 85 a1 f6 ff ff jne 440f04 <__twalk+0x464> + 441863: be 03 00 00 00 mov $0x3,%esi + 441868: 4c 89 ff mov %r15,%rdi + 44186b: ff d3 callq *%rbx + 44186d: e9 e3 f6 ff ff jmpq 440f55 <__twalk+0x4b5> + 441872: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 441878: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) + 44187d: 0f 85 de f2 ff ff jne 440b61 <__twalk+0xc1> + 441883: be 03 00 00 00 mov $0x3,%esi + 441888: 4c 89 ff mov %r15,%rdi + 44188b: ff d3 callq *%rbx + 44188d: e9 20 f3 ff ff jmpq 440bb2 <__twalk+0x112> + 441892: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 441898: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) + 44189d: 0f 85 b5 f5 ff ff jne 440e58 <__twalk+0x3b8> + 4418a3: be 03 00 00 00 mov $0x3,%esi + 4418a8: 4c 89 ff mov %r15,%rdi + 4418ab: ff d3 callq *%rbx + 4418ad: e9 f7 f5 ff ff jmpq 440ea9 <__twalk+0x409> + 4418b2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4418b8: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) + 4418bd: 0f 85 1c f5 ff ff jne 440ddf <__twalk+0x33f> + 4418c3: be 03 00 00 00 mov $0x3,%esi + 4418c8: 4c 89 ff mov %r15,%rdi + 4418cb: ff d3 callq *%rbx + 4418cd: e9 5e f5 ff ff jmpq 440e30 <__twalk+0x390> + 4418d2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4418d8: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) + 4418dd: 0f 85 f7 f2 ff ff jne 440bda <__twalk+0x13a> + 4418e3: be 03 00 00 00 mov $0x3,%esi + 4418e8: 4c 89 ff mov %r15,%rdi + 4418eb: ff d3 callq *%rbx + 4418ed: e9 39 f3 ff ff jmpq 440c2b <__twalk+0x18b> + 4418f2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 4418f8: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) + 4418fd: 0f 85 fc f3 ff ff jne 440cff <__twalk+0x25f> + 441903: be 03 00 00 00 mov $0x3,%esi + 441908: 4c 89 ff mov %r15,%rdi + 44190b: ff d3 callq *%rbx + 44190d: e9 3e f4 ff ff jmpq 440d50 <__twalk+0x2b0> + 441912: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 441918: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) + 44191d: 0f 85 63 f3 ff ff jne 440c86 <__twalk+0x1e6> + 441923: be 03 00 00 00 mov $0x3,%esi + 441928: 4c 89 ff mov %r15,%rdi + 44192b: ff d3 callq *%rbx + 44192d: e9 a5 f3 ff ff jmpq 440cd7 <__twalk+0x237> + 441932: 0f 1f 40 00 nopl 0x0(%rax) + 441936: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) + 44193d: 00 00 00 + +0000000000441940 <__tdestroy>: + 441940: 48 85 ff test %rdi,%rdi + 441943: 0f 84 df 04 00 00 je 441e28 <__tdestroy+0x4e8> + 441949: 41 57 push %r15 + 44194b: 41 56 push %r14 + 44194d: 41 55 push %r13 + 44194f: 41 54 push %r12 + 441951: 55 push %rbp + 441952: 53 push %rbx + 441953: 48 89 fd mov %rdi,%rbp + 441956: 48 89 f3 mov %rsi,%rbx + 441959: 48 83 ec 08 sub $0x8,%rsp + 44195d: 4c 8b 67 08 mov 0x8(%rdi),%r12 + 441961: 4d 85 e4 test %r12,%r12 + 441964: 0f 84 5b 02 00 00 je 441bc5 <__tdestroy+0x285> + 44196a: 4d 8b 6c 24 08 mov 0x8(%r12),%r13 + 44196f: 4d 85 ed test %r13,%r13 + 441972: 0f 84 17 01 00 00 je 441a8f <__tdestroy+0x14f> + 441978: 4d 8b 75 08 mov 0x8(%r13),%r14 + 44197c: 4d 85 f6 test %r14,%r14 + 44197f: 74 7a je 4419fb <__tdestroy+0xbb> + 441981: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 441985: 4d 85 ff test %r15,%r15 + 441988: 74 2c je 4419b6 <__tdestroy+0x76> + 44198a: 49 8b 7f 08 mov 0x8(%r15),%rdi + 44198e: 48 85 ff test %rdi,%rdi + 441991: 74 05 je 441998 <__tdestroy+0x58> + 441993: e8 08 e4 ff ff callq 43fda0 + 441998: 49 8b 7f 10 mov 0x10(%r15),%rdi + 44199c: 48 85 ff test %rdi,%rdi + 44199f: 74 08 je 4419a9 <__tdestroy+0x69> + 4419a1: 48 89 de mov %rbx,%rsi + 4419a4: e8 f7 e3 ff ff callq 43fda0 + 4419a9: 49 8b 3f mov (%r15),%rdi + 4419ac: ff d3 callq *%rbx + 4419ae: 4c 89 ff mov %r15,%rdi + 4419b1: e8 fa c3 fd ff callq 41ddb0 <__cfree> + 4419b6: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 4419ba: 4d 85 ff test %r15,%r15 + 4419bd: 74 2f je 4419ee <__tdestroy+0xae> + 4419bf: 49 8b 7f 08 mov 0x8(%r15),%rdi + 4419c3: 48 85 ff test %rdi,%rdi + 4419c6: 74 08 je 4419d0 <__tdestroy+0x90> + 4419c8: 48 89 de mov %rbx,%rsi + 4419cb: e8 d0 e3 ff ff callq 43fda0 + 4419d0: 49 8b 7f 10 mov 0x10(%r15),%rdi + 4419d4: 48 85 ff test %rdi,%rdi + 4419d7: 74 08 je 4419e1 <__tdestroy+0xa1> + 4419d9: 48 89 de mov %rbx,%rsi + 4419dc: e8 bf e3 ff ff callq 43fda0 + 4419e1: 49 8b 3f mov (%r15),%rdi + 4419e4: ff d3 callq *%rbx + 4419e6: 4c 89 ff mov %r15,%rdi + 4419e9: e8 c2 c3 fd ff callq 41ddb0 <__cfree> + 4419ee: 49 8b 3e mov (%r14),%rdi + 4419f1: ff d3 callq *%rbx + 4419f3: 4c 89 f7 mov %r14,%rdi + 4419f6: e8 b5 c3 fd ff callq 41ddb0 <__cfree> + 4419fb: 4d 8b 75 10 mov 0x10(%r13),%r14 + 4419ff: 4d 85 f6 test %r14,%r14 + 441a02: 74 7d je 441a81 <__tdestroy+0x141> + 441a04: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 441a08: 4d 85 ff test %r15,%r15 + 441a0b: 74 2f je 441a3c <__tdestroy+0xfc> + 441a0d: 49 8b 7f 08 mov 0x8(%r15),%rdi + 441a11: 48 85 ff test %rdi,%rdi + 441a14: 74 08 je 441a1e <__tdestroy+0xde> + 441a16: 48 89 de mov %rbx,%rsi + 441a19: e8 82 e3 ff ff callq 43fda0 + 441a1e: 49 8b 7f 10 mov 0x10(%r15),%rdi + 441a22: 48 85 ff test %rdi,%rdi + 441a25: 74 08 je 441a2f <__tdestroy+0xef> + 441a27: 48 89 de mov %rbx,%rsi + 441a2a: e8 71 e3 ff ff callq 43fda0 + 441a2f: 49 8b 3f mov (%r15),%rdi + 441a32: ff d3 callq *%rbx + 441a34: 4c 89 ff mov %r15,%rdi + 441a37: e8 74 c3 fd ff callq 41ddb0 <__cfree> + 441a3c: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 441a40: 4d 85 ff test %r15,%r15 + 441a43: 74 2f je 441a74 <__tdestroy+0x134> + 441a45: 49 8b 7f 08 mov 0x8(%r15),%rdi + 441a49: 48 85 ff test %rdi,%rdi + 441a4c: 74 08 je 441a56 <__tdestroy+0x116> + 441a4e: 48 89 de mov %rbx,%rsi + 441a51: e8 4a e3 ff ff callq 43fda0 + 441a56: 49 8b 7f 10 mov 0x10(%r15),%rdi + 441a5a: 48 85 ff test %rdi,%rdi + 441a5d: 74 08 je 441a67 <__tdestroy+0x127> + 441a5f: 48 89 de mov %rbx,%rsi + 441a62: e8 39 e3 ff ff callq 43fda0 + 441a67: 49 8b 3f mov (%r15),%rdi + 441a6a: ff d3 callq *%rbx + 441a6c: 4c 89 ff mov %r15,%rdi + 441a6f: e8 3c c3 fd ff callq 41ddb0 <__cfree> + 441a74: 49 8b 3e mov (%r14),%rdi + 441a77: ff d3 callq *%rbx + 441a79: 4c 89 f7 mov %r14,%rdi + 441a7c: e8 2f c3 fd ff callq 41ddb0 <__cfree> + 441a81: 49 8b 7d 00 mov 0x0(%r13),%rdi + 441a85: ff d3 callq *%rbx + 441a87: 4c 89 ef mov %r13,%rdi + 441a8a: e8 21 c3 fd ff callq 41ddb0 <__cfree> + 441a8f: 4d 8b 6c 24 10 mov 0x10(%r12),%r13 + 441a94: 4d 85 ed test %r13,%r13 + 441a97: 0f 84 1a 01 00 00 je 441bb7 <__tdestroy+0x277> + 441a9d: 4d 8b 75 08 mov 0x8(%r13),%r14 + 441aa1: 4d 85 f6 test %r14,%r14 + 441aa4: 74 7d je 441b23 <__tdestroy+0x1e3> + 441aa6: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 441aaa: 4d 85 ff test %r15,%r15 + 441aad: 74 2f je 441ade <__tdestroy+0x19e> + 441aaf: 49 8b 7f 08 mov 0x8(%r15),%rdi + 441ab3: 48 85 ff test %rdi,%rdi + 441ab6: 74 08 je 441ac0 <__tdestroy+0x180> + 441ab8: 48 89 de mov %rbx,%rsi + 441abb: e8 e0 e2 ff ff callq 43fda0 + 441ac0: 49 8b 7f 10 mov 0x10(%r15),%rdi + 441ac4: 48 85 ff test %rdi,%rdi + 441ac7: 74 08 je 441ad1 <__tdestroy+0x191> + 441ac9: 48 89 de mov %rbx,%rsi + 441acc: e8 cf e2 ff ff callq 43fda0 + 441ad1: 49 8b 3f mov (%r15),%rdi + 441ad4: ff d3 callq *%rbx + 441ad6: 4c 89 ff mov %r15,%rdi + 441ad9: e8 d2 c2 fd ff callq 41ddb0 <__cfree> + 441ade: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 441ae2: 4d 85 ff test %r15,%r15 + 441ae5: 74 2f je 441b16 <__tdestroy+0x1d6> + 441ae7: 49 8b 7f 08 mov 0x8(%r15),%rdi + 441aeb: 48 85 ff test %rdi,%rdi + 441aee: 74 08 je 441af8 <__tdestroy+0x1b8> + 441af0: 48 89 de mov %rbx,%rsi + 441af3: e8 a8 e2 ff ff callq 43fda0 + 441af8: 49 8b 7f 10 mov 0x10(%r15),%rdi + 441afc: 48 85 ff test %rdi,%rdi + 441aff: 74 08 je 441b09 <__tdestroy+0x1c9> + 441b01: 48 89 de mov %rbx,%rsi + 441b04: e8 97 e2 ff ff callq 43fda0 + 441b09: 49 8b 3f mov (%r15),%rdi + 441b0c: ff d3 callq *%rbx + 441b0e: 4c 89 ff mov %r15,%rdi + 441b11: e8 9a c2 fd ff callq 41ddb0 <__cfree> + 441b16: 49 8b 3e mov (%r14),%rdi + 441b19: ff d3 callq *%rbx + 441b1b: 4c 89 f7 mov %r14,%rdi + 441b1e: e8 8d c2 fd ff callq 41ddb0 <__cfree> + 441b23: 4d 8b 75 10 mov 0x10(%r13),%r14 + 441b27: 4d 85 f6 test %r14,%r14 + 441b2a: 74 7d je 441ba9 <__tdestroy+0x269> + 441b2c: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 441b30: 4d 85 ff test %r15,%r15 + 441b33: 74 2f je 441b64 <__tdestroy+0x224> + 441b35: 49 8b 7f 08 mov 0x8(%r15),%rdi + 441b39: 48 85 ff test %rdi,%rdi + 441b3c: 74 08 je 441b46 <__tdestroy+0x206> + 441b3e: 48 89 de mov %rbx,%rsi + 441b41: e8 5a e2 ff ff callq 43fda0 + 441b46: 49 8b 7f 10 mov 0x10(%r15),%rdi + 441b4a: 48 85 ff test %rdi,%rdi + 441b4d: 74 08 je 441b57 <__tdestroy+0x217> + 441b4f: 48 89 de mov %rbx,%rsi + 441b52: e8 49 e2 ff ff callq 43fda0 + 441b57: 49 8b 3f mov (%r15),%rdi + 441b5a: ff d3 callq *%rbx + 441b5c: 4c 89 ff mov %r15,%rdi + 441b5f: e8 4c c2 fd ff callq 41ddb0 <__cfree> + 441b64: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 441b68: 4d 85 ff test %r15,%r15 + 441b6b: 74 2f je 441b9c <__tdestroy+0x25c> + 441b6d: 49 8b 7f 08 mov 0x8(%r15),%rdi + 441b71: 48 85 ff test %rdi,%rdi + 441b74: 74 08 je 441b7e <__tdestroy+0x23e> + 441b76: 48 89 de mov %rbx,%rsi + 441b79: e8 22 e2 ff ff callq 43fda0 + 441b7e: 49 8b 7f 10 mov 0x10(%r15),%rdi + 441b82: 48 85 ff test %rdi,%rdi + 441b85: 74 08 je 441b8f <__tdestroy+0x24f> + 441b87: 48 89 de mov %rbx,%rsi + 441b8a: e8 11 e2 ff ff callq 43fda0 + 441b8f: 49 8b 3f mov (%r15),%rdi + 441b92: ff d3 callq *%rbx + 441b94: 4c 89 ff mov %r15,%rdi + 441b97: e8 14 c2 fd ff callq 41ddb0 <__cfree> + 441b9c: 49 8b 3e mov (%r14),%rdi + 441b9f: ff d3 callq *%rbx + 441ba1: 4c 89 f7 mov %r14,%rdi + 441ba4: e8 07 c2 fd ff callq 41ddb0 <__cfree> + 441ba9: 49 8b 7d 00 mov 0x0(%r13),%rdi + 441bad: ff d3 callq *%rbx + 441baf: 4c 89 ef mov %r13,%rdi + 441bb2: e8 f9 c1 fd ff callq 41ddb0 <__cfree> + 441bb7: 49 8b 3c 24 mov (%r12),%rdi + 441bbb: ff d3 callq *%rbx + 441bbd: 4c 89 e7 mov %r12,%rdi + 441bc0: e8 eb c1 fd ff callq 41ddb0 <__cfree> + 441bc5: 4c 8b 65 10 mov 0x10(%rbp),%r12 + 441bc9: 4d 85 e4 test %r12,%r12 + 441bcc: 0f 84 37 02 00 00 je 441e09 <__tdestroy+0x4c9> + 441bd2: 4d 8b 6c 24 08 mov 0x8(%r12),%r13 + 441bd7: 4d 85 ed test %r13,%r13 + 441bda: 0f 84 1a 01 00 00 je 441cfa <__tdestroy+0x3ba> + 441be0: 4d 8b 75 08 mov 0x8(%r13),%r14 + 441be4: 4d 85 f6 test %r14,%r14 + 441be7: 74 7d je 441c66 <__tdestroy+0x326> + 441be9: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 441bed: 4d 85 ff test %r15,%r15 + 441bf0: 74 2f je 441c21 <__tdestroy+0x2e1> + 441bf2: 49 8b 7f 08 mov 0x8(%r15),%rdi + 441bf6: 48 85 ff test %rdi,%rdi + 441bf9: 74 08 je 441c03 <__tdestroy+0x2c3> + 441bfb: 48 89 de mov %rbx,%rsi + 441bfe: e8 9d e1 ff ff callq 43fda0 + 441c03: 49 8b 7f 10 mov 0x10(%r15),%rdi + 441c07: 48 85 ff test %rdi,%rdi + 441c0a: 74 08 je 441c14 <__tdestroy+0x2d4> + 441c0c: 48 89 de mov %rbx,%rsi + 441c0f: e8 8c e1 ff ff callq 43fda0 + 441c14: 49 8b 3f mov (%r15),%rdi + 441c17: ff d3 callq *%rbx + 441c19: 4c 89 ff mov %r15,%rdi + 441c1c: e8 8f c1 fd ff callq 41ddb0 <__cfree> + 441c21: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 441c25: 4d 85 ff test %r15,%r15 + 441c28: 74 2f je 441c59 <__tdestroy+0x319> + 441c2a: 49 8b 7f 08 mov 0x8(%r15),%rdi + 441c2e: 48 85 ff test %rdi,%rdi + 441c31: 74 08 je 441c3b <__tdestroy+0x2fb> + 441c33: 48 89 de mov %rbx,%rsi + 441c36: e8 65 e1 ff ff callq 43fda0 + 441c3b: 49 8b 7f 10 mov 0x10(%r15),%rdi + 441c3f: 48 85 ff test %rdi,%rdi + 441c42: 74 08 je 441c4c <__tdestroy+0x30c> + 441c44: 48 89 de mov %rbx,%rsi + 441c47: e8 54 e1 ff ff callq 43fda0 + 441c4c: 49 8b 3f mov (%r15),%rdi + 441c4f: ff d3 callq *%rbx + 441c51: 4c 89 ff mov %r15,%rdi + 441c54: e8 57 c1 fd ff callq 41ddb0 <__cfree> + 441c59: 49 8b 3e mov (%r14),%rdi + 441c5c: ff d3 callq *%rbx + 441c5e: 4c 89 f7 mov %r14,%rdi + 441c61: e8 4a c1 fd ff callq 41ddb0 <__cfree> + 441c66: 4d 8b 75 10 mov 0x10(%r13),%r14 + 441c6a: 4d 85 f6 test %r14,%r14 + 441c6d: 74 7d je 441cec <__tdestroy+0x3ac> + 441c6f: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 441c73: 4d 85 ff test %r15,%r15 + 441c76: 74 2f je 441ca7 <__tdestroy+0x367> + 441c78: 49 8b 7f 08 mov 0x8(%r15),%rdi + 441c7c: 48 85 ff test %rdi,%rdi + 441c7f: 74 08 je 441c89 <__tdestroy+0x349> + 441c81: 48 89 de mov %rbx,%rsi + 441c84: e8 17 e1 ff ff callq 43fda0 + 441c89: 49 8b 7f 10 mov 0x10(%r15),%rdi + 441c8d: 48 85 ff test %rdi,%rdi + 441c90: 74 08 je 441c9a <__tdestroy+0x35a> + 441c92: 48 89 de mov %rbx,%rsi + 441c95: e8 06 e1 ff ff callq 43fda0 + 441c9a: 49 8b 3f mov (%r15),%rdi + 441c9d: ff d3 callq *%rbx + 441c9f: 4c 89 ff mov %r15,%rdi + 441ca2: e8 09 c1 fd ff callq 41ddb0 <__cfree> + 441ca7: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 441cab: 4d 85 ff test %r15,%r15 + 441cae: 74 2f je 441cdf <__tdestroy+0x39f> + 441cb0: 49 8b 7f 08 mov 0x8(%r15),%rdi + 441cb4: 48 85 ff test %rdi,%rdi + 441cb7: 74 08 je 441cc1 <__tdestroy+0x381> + 441cb9: 48 89 de mov %rbx,%rsi + 441cbc: e8 df e0 ff ff callq 43fda0 + 441cc1: 49 8b 7f 10 mov 0x10(%r15),%rdi + 441cc5: 48 85 ff test %rdi,%rdi + 441cc8: 74 08 je 441cd2 <__tdestroy+0x392> + 441cca: 48 89 de mov %rbx,%rsi + 441ccd: e8 ce e0 ff ff callq 43fda0 + 441cd2: 49 8b 3f mov (%r15),%rdi + 441cd5: ff d3 callq *%rbx + 441cd7: 4c 89 ff mov %r15,%rdi + 441cda: e8 d1 c0 fd ff callq 41ddb0 <__cfree> + 441cdf: 49 8b 3e mov (%r14),%rdi + 441ce2: ff d3 callq *%rbx + 441ce4: 4c 89 f7 mov %r14,%rdi + 441ce7: e8 c4 c0 fd ff callq 41ddb0 <__cfree> + 441cec: 49 8b 7d 00 mov 0x0(%r13),%rdi + 441cf0: ff d3 callq *%rbx + 441cf2: 4c 89 ef mov %r13,%rdi + 441cf5: e8 b6 c0 fd ff callq 41ddb0 <__cfree> + 441cfa: 4d 8b 6c 24 10 mov 0x10(%r12),%r13 + 441cff: 4d 85 ed test %r13,%r13 + 441d02: 0f 84 f3 00 00 00 je 441dfb <__tdestroy+0x4bb> + 441d08: 4d 8b 75 08 mov 0x8(%r13),%r14 + 441d0c: 4d 85 f6 test %r14,%r14 + 441d0f: 74 7d je 441d8e <__tdestroy+0x44e> + 441d11: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 441d15: 4d 85 ff test %r15,%r15 + 441d18: 74 2f je 441d49 <__tdestroy+0x409> + 441d1a: 49 8b 7f 08 mov 0x8(%r15),%rdi + 441d1e: 48 85 ff test %rdi,%rdi + 441d21: 74 08 je 441d2b <__tdestroy+0x3eb> + 441d23: 48 89 de mov %rbx,%rsi + 441d26: e8 75 e0 ff ff callq 43fda0 + 441d2b: 49 8b 7f 10 mov 0x10(%r15),%rdi + 441d2f: 48 85 ff test %rdi,%rdi + 441d32: 74 08 je 441d3c <__tdestroy+0x3fc> + 441d34: 48 89 de mov %rbx,%rsi + 441d37: e8 64 e0 ff ff callq 43fda0 + 441d3c: 49 8b 3f mov (%r15),%rdi + 441d3f: ff d3 callq *%rbx + 441d41: 4c 89 ff mov %r15,%rdi + 441d44: e8 67 c0 fd ff callq 41ddb0 <__cfree> + 441d49: 4d 8b 7e 10 mov 0x10(%r14),%r15 + 441d4d: 4d 85 ff test %r15,%r15 + 441d50: 74 2f je 441d81 <__tdestroy+0x441> + 441d52: 49 8b 7f 08 mov 0x8(%r15),%rdi + 441d56: 48 85 ff test %rdi,%rdi + 441d59: 74 08 je 441d63 <__tdestroy+0x423> + 441d5b: 48 89 de mov %rbx,%rsi + 441d5e: e8 3d e0 ff ff callq 43fda0 + 441d63: 49 8b 7f 10 mov 0x10(%r15),%rdi + 441d67: 48 85 ff test %rdi,%rdi + 441d6a: 74 08 je 441d74 <__tdestroy+0x434> + 441d6c: 48 89 de mov %rbx,%rsi + 441d6f: e8 2c e0 ff ff callq 43fda0 + 441d74: 49 8b 3f mov (%r15),%rdi + 441d77: ff d3 callq *%rbx + 441d79: 4c 89 ff mov %r15,%rdi + 441d7c: e8 2f c0 fd ff callq 41ddb0 <__cfree> + 441d81: 49 8b 3e mov (%r14),%rdi + 441d84: ff d3 callq *%rbx + 441d86: 4c 89 f7 mov %r14,%rdi + 441d89: e8 22 c0 fd ff callq 41ddb0 <__cfree> + 441d8e: 4d 8b 75 10 mov 0x10(%r13),%r14 + 441d92: 4d 85 f6 test %r14,%r14 + 441d95: 74 56 je 441ded <__tdestroy+0x4ad> + 441d97: 4d 8b 7e 08 mov 0x8(%r14),%r15 + 441d9b: 4d 85 ff test %r15,%r15 + 441d9e: 74 2f je 441dcf <__tdestroy+0x48f> + 441da0: 49 8b 7f 08 mov 0x8(%r15),%rdi + 441da4: 48 85 ff test %rdi,%rdi + 441da7: 74 08 je 441db1 <__tdestroy+0x471> + 441da9: 48 89 de mov %rbx,%rsi + 441dac: e8 ef df ff ff callq 43fda0 + 441db1: 49 8b 7f 10 mov 0x10(%r15),%rdi + 441db5: 48 85 ff test %rdi,%rdi + 441db8: 74 08 je 441dc2 <__tdestroy+0x482> + 441dba: 48 89 de mov %rbx,%rsi + 441dbd: e8 de df ff ff callq 43fda0 + 441dc2: 49 8b 3f mov (%r15),%rdi + 441dc5: ff d3 callq *%rbx + 441dc7: 4c 89 ff mov %r15,%rdi + 441dca: e8 e1 bf fd ff callq 41ddb0 <__cfree> + 441dcf: 49 8b 7e 10 mov 0x10(%r14),%rdi + 441dd3: 48 85 ff test %rdi,%rdi + 441dd6: 74 08 je 441de0 <__tdestroy+0x4a0> + 441dd8: 48 89 de mov %rbx,%rsi + 441ddb: e8 c0 df ff ff callq 43fda0 + 441de0: 49 8b 3e mov (%r14),%rdi + 441de3: ff d3 callq *%rbx + 441de5: 4c 89 f7 mov %r14,%rdi + 441de8: e8 c3 bf fd ff callq 41ddb0 <__cfree> + 441ded: 49 8b 7d 00 mov 0x0(%r13),%rdi + 441df1: ff d3 callq *%rbx + 441df3: 4c 89 ef mov %r13,%rdi + 441df6: e8 b5 bf fd ff callq 41ddb0 <__cfree> + 441dfb: 49 8b 3c 24 mov (%r12),%rdi + 441dff: ff d3 callq *%rbx + 441e01: 4c 89 e7 mov %r12,%rdi + 441e04: e8 a7 bf fd ff callq 41ddb0 <__cfree> + 441e09: 48 8b 7d 00 mov 0x0(%rbp),%rdi + 441e0d: ff d3 callq *%rbx + 441e0f: 48 83 c4 08 add $0x8,%rsp + 441e13: 48 89 ef mov %rbp,%rdi + 441e16: 5b pop %rbx + 441e17: 5d pop %rbp + 441e18: 41 5c pop %r12 + 441e1a: 41 5d pop %r13 + 441e1c: 41 5e pop %r14 + 441e1e: 41 5f pop %r15 + 441e20: e9 8b bf fd ff jmpq 41ddb0 <__cfree> + 441e25: 0f 1f 00 nopl (%rax) + 441e28: f3 c3 repz retq + 441e2a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + +0000000000441e30 : + 441e30: 41 57 push %r15 + 441e32: 41 56 push %r14 + 441e34: 49 89 d7 mov %rdx,%r15 + 441e37: 41 55 push %r13 + 441e39: 41 54 push %r12 + 441e3b: 4d 89 c6 mov %r8,%r14 + 441e3e: 55 push %rbp + 441e3f: 53 push %rbx + 441e40: 48 89 cb mov %rcx,%rbx + 441e43: 48 83 ec 18 sub $0x18,%rsp + 441e47: 48 8b 29 mov (%rcx),%rbp + 441e4a: 4c 8b 22 mov (%rdx),%r12 + 441e4d: 89 7c 24 08 mov %edi,0x8(%rsp) + 441e51: 48 89 34 24 mov %rsi,(%rsp) + 441e55: be 0a 00 00 00 mov $0xa,%esi + 441e5a: 49 89 ed mov %rbp,%r13 + 441e5d: 4c 89 e7 mov %r12,%rdi + 441e60: 4d 29 e5 sub %r12,%r13 + 441e63: 4c 89 ea mov %r13,%rdx + 441e66: e8 d5 3c fe ff callq 425b40 <__memchr> + 441e6b: 48 85 c0 test %rax,%rax + 441e6e: 74 30 je 441ea0 + 441e70: 48 83 c0 01 add $0x1,%rax + 441e74: 49 89 07 mov %rax,(%r15) + 441e77: 48 8b 13 mov (%rbx),%rdx + 441e7a: 48 39 d0 cmp %rdx,%rax + 441e7d: 0f 87 95 01 00 00 ja 442018 + 441e83: 49 39 d4 cmp %rdx,%r12 + 441e86: 74 30 je 441eb8 + 441e88: 4c 89 e0 mov %r12,%rax + 441e8b: 48 83 c4 18 add $0x18,%rsp + 441e8f: 5b pop %rbx + 441e90: 5d pop %rbp + 441e91: 41 5c pop %r12 + 441e93: 41 5d pop %r13 + 441e95: 41 5e pop %r14 + 441e97: 41 5f pop %r15 + 441e99: c3 retq + 441e9a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) + 441ea0: 4c 3b 24 24 cmp (%rsp),%r12 + 441ea4: 74 05 je 441eab + 441ea6: 4c 39 f5 cmp %r14,%rbp + 441ea9: 74 11 je 441ebc + 441eab: 48 8d 45 ff lea -0x1(%rbp),%rax + 441eaf: eb bf jmp 441e70 + 441eb1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 441eb8: 31 c0 xor %eax,%eax + 441eba: eb cf jmp 441e8b + 441ebc: 4c 8b 34 24 mov (%rsp),%r14 + 441ec0: 4c 89 ea mov %r13,%rdx + 441ec3: 4c 89 e6 mov %r12,%rsi + 441ec6: 45 31 e4 xor %r12d,%r12d + 441ec9: 4c 89 f7 mov %r14,%rdi + 441ecc: e8 2f e4 fb ff callq 400300 <__rela_iplt_end+0x38> + 441ed1: 4c 89 f0 mov %r14,%rax + 441ed4: 49 2b 07 sub (%r15),%rax + 441ed7: 48 89 ea mov %rbp,%rdx + 441eda: 48 01 03 add %rax,(%rbx) + 441edd: 48 63 44 24 08 movslq 0x8(%rsp),%rax + 441ee2: 4d 89 37 mov %r14,(%r15) + 441ee5: 48 8b 33 mov (%rbx),%rsi + 441ee8: 48 89 44 24 08 mov %rax,0x8(%rsp) + 441eed: 48 89 c7 mov %rax,%rdi + 441ef0: 48 29 f2 sub %rsi,%rdx + 441ef3: 44 89 e0 mov %r12d,%eax + 441ef6: 0f 05 syscall + 441ef8: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 441efe: 76 13 jbe 441f13 + 441f00: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx + 441f07: f7 d8 neg %eax + 441f09: 64 89 02 mov %eax,%fs:(%rdx) + 441f0c: 31 c0 xor %eax,%eax + 441f0e: e9 78 ff ff ff jmpq 441e8b + 441f13: 48 85 c0 test %rax,%rax + 441f16: 78 a0 js 441eb8 + 441f18: 48 03 03 add (%rbx),%rax + 441f1b: be 0a 00 00 00 mov $0xa,%esi + 441f20: 48 89 03 mov %rax,(%rbx) + 441f23: 4d 8b 37 mov (%r15),%r14 + 441f26: 48 89 c2 mov %rax,%rdx + 441f29: 49 89 c5 mov %rax,%r13 + 441f2c: 4c 29 f2 sub %r14,%rdx + 441f2f: 4c 89 f7 mov %r14,%rdi + 441f32: e8 09 3c fe ff callq 425b40 <__memchr> + 441f37: 48 85 c0 test %rax,%rax + 441f3a: 0f 85 c5 00 00 00 jne 442005 + 441f40: 4c 39 ed cmp %r13,%rbp + 441f43: 0f 85 e8 00 00 00 jne 442031 + 441f49: 48 8b 0c 24 mov (%rsp),%rcx + 441f4d: 48 89 e8 mov %rbp,%rax + 441f50: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi + 441f55: 48 29 c8 sub %rcx,%rax + 441f58: 4c 8d 34 40 lea (%rax,%rax,2),%r14 + 441f5c: 49 8d 46 03 lea 0x3(%r14),%rax + 441f60: 4d 85 f6 test %r14,%r14 + 441f63: 4c 0f 48 f0 cmovs %rax,%r14 + 441f67: 48 89 e8 mov %rbp,%rax + 441f6a: 49 c1 fe 02 sar $0x2,%r14 + 441f6e: 49 01 ce add %rcx,%r14 + 441f71: 4c 29 f0 sub %r14,%rax + 441f74: 4c 89 33 mov %r14,(%rbx) + 441f77: 4c 89 f6 mov %r14,%rsi + 441f7a: 48 89 04 24 mov %rax,(%rsp) + 441f7e: 48 89 c2 mov %rax,%rdx + 441f81: 44 89 e0 mov %r12d,%eax + 441f84: 0f 05 syscall + 441f86: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 441f8c: 49 89 c5 mov %rax,%r13 + 441f8f: 76 42 jbe 441fd3 + 441f91: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) + 441f98: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax + 441f9f: 44 89 e9 mov %r13d,%ecx + 441fa2: f7 d9 neg %ecx + 441fa4: 64 89 08 mov %ecx,%fs:(%rax) + 441fa7: 31 c0 xor %eax,%eax + 441fa9: e9 dd fe ff ff jmpq 441e8b + 441fae: 66 90 xchg %ax,%ax + 441fb0: 48 39 cd cmp %rcx,%rbp + 441fb3: 75 58 jne 44200d + 441fb5: 4c 89 33 mov %r14,(%rbx) + 441fb8: 48 8b 14 24 mov (%rsp),%rdx + 441fbc: 4c 89 f6 mov %r14,%rsi + 441fbf: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi + 441fc4: 31 c0 xor %eax,%eax + 441fc6: 0f 05 syscall + 441fc8: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax + 441fce: 49 89 c5 mov %rax,%r13 + 441fd1: 77 c5 ja 441f98 + 441fd3: 4d 85 ed test %r13,%r13 + 441fd6: 0f 88 dc fe ff ff js 441eb8 + 441fdc: 4c 8b 23 mov (%rbx),%r12 + 441fdf: 4c 89 ea mov %r13,%rdx + 441fe2: be 0a 00 00 00 mov $0xa,%esi + 441fe7: 4c 89 e7 mov %r12,%rdi + 441fea: e8 51 3b fe ff callq 425b40 <__memchr> + 441fef: 41 c6 04 24 0a movb $0xa,(%r12) + 441ff4: 4c 89 e9 mov %r13,%rcx + 441ff7: 48 03 0b add (%rbx),%rcx + 441ffa: 48 85 c0 test %rax,%rax + 441ffd: 48 89 0b mov %rcx,(%rbx) + 442000: 74 ae je 441fb0 + 442002: 4d 8b 37 mov (%r15),%r14 + 442005: 4d 89 f4 mov %r14,%r12 + 442008: e9 63 fe ff ff jmpq 441e70 + 44200d: 48 89 cd mov %rcx,%rbp + 442010: 4d 8b 27 mov (%r15),%r12 + 442013: e9 93 fe ff ff jmpq 441eab + 442018: b9 08 4a 4a 00 mov $0x4a4a08,%ecx + 44201d: ba 77 00 00 00 mov $0x77,%edx + 442022: be b8 49 4a 00 mov $0x4a49b8,%esi + 442027: bf 12 4a 4a 00 mov $0x4a4a12,%edi + 44202c: e8 0f f7 fb ff callq 401740 <__assert_fail> + 442031: 4c 89 ed mov %r13,%rbp + 442034: 4d 89 f4 mov %r14,%r12 + 442037: e9 6f fe ff ff jmpq 441eab + 44203c: 0f 1f 40 00 nopl 0x0(%rax) + +0000000000442040 <__get_nprocs>: + 442040: 55 push %rbp + 442041: 31 ff xor %edi,%edi + 442043: 48 89 e5 mov %rsp,%rbp + 442046: 41 57 push %r15 + 442048: 41 56 push %r14 + 44204a: 41 55 push %r13 + 44204c: 41 54 push %r12 + 44204e: 53 push %rbx + 44204f: 48 83 ec 48 sub $0x48,%rsp + 442053: e8 68 4f 02 00 callq 466fc0
    : - 4009ae: 55 push %rbp - 4009af: 48 89 e5 mov %rsp,%rbp - 4009b2: c7 45 fc 05 00 00 00 movl $0x5,-0x4(%rbp) - 4009b9: 83 45 fc 01 addl $0x1,-0x4(%rbp) - 4009bd: 83 6d fc 01 subl $0x1,-0x4(%rbp) - 4009c1: b8 00 00 00 00 mov $0x0,%eax - 4009c6: 5d pop %rbp - 4009c7: c3 retq - 4009c8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 4009cf: 00 - -00000000004009d0 : - 4009d0: 41 56 push %r14 - 4009d2: 41 55 push %r13 - 4009d4: b8 00 00 00 00 mov $0x0,%eax - 4009d9: 41 54 push %r12 - 4009db: 55 push %rbp - 4009dc: 49 89 cc mov %rcx,%r12 - 4009df: 53 push %rbx - 4009e0: 4d 89 c5 mov %r8,%r13 - 4009e3: 4d 89 ce mov %r9,%r14 - 4009e6: 48 81 ec 90 00 00 00 sub $0x90,%rsp - 4009ed: 48 85 c0 test %rax,%rax - 4009f0: 48 89 7c 24 18 mov %rdi,0x18(%rsp) - 4009f5: 89 74 24 0c mov %esi,0xc(%rsp) - 4009f9: 48 89 54 24 10 mov %rdx,0x10(%rsp) - 4009fe: 0f 84 2d 01 00 00 je 400b31 - 400a04: 8b 0d f6 f5 bf ff mov -0x400a0a(%rip),%ecx # 0 <_nl_current_LC_CTYPE> - 400a0a: 31 c0 xor %eax,%eax - 400a0c: 85 c9 test %ecx,%ecx - 400a0e: 48 89 d1 mov %rdx,%rcx - 400a11: 0f 94 c0 sete %al - 400a14: 89 05 e6 ac 2c 00 mov %eax,0x2cace6(%rip) # 6cb700 <__libc_multiple_libcs> - 400a1a: 48 63 44 24 0c movslq 0xc(%rsp),%rax - 400a1f: 48 8d 7c c1 08 lea 0x8(%rcx,%rax,8),%rdi - 400a24: 48 8b 84 24 c0 00 00 mov 0xc0(%rsp),%rax - 400a2b: 00 - 400a2c: 48 89 3d 0d bc 2c 00 mov %rdi,0x2cbc0d(%rip) # 6cc640 <__environ> - 400a33: 48 89 05 56 95 2c 00 mov %rax,0x2c9556(%rip) # 6c9f90 <__libc_stack_end> - 400a3a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 400a40: 48 83 c7 08 add $0x8,%rdi - 400a44: 48 83 7f f8 00 cmpq $0x0,-0x8(%rdi) - 400a49: 75 f5 jne 400a40 - 400a4b: e8 50 21 04 00 callq 442ba0 <_dl_aux_init> - 400a50: 48 83 3d f0 c7 2c 00 cmpq $0x0,0x2cc7f0(%rip) # 6cd248 <_dl_phdr> - 400a57: 00 - 400a58: 75 4f jne 400aa9 - 400a5a: b8 00 00 40 00 mov $0x400000,%eax - 400a5f: 48 85 c0 test %rax,%rax - 400a62: 74 45 je 400aa9 - 400a64: 66 83 3d ca f5 ff ff cmpw $0x38,-0xa36(%rip) # 400036 <__ehdr_start+0x36> - 400a6b: 38 - 400a6c: 74 19 je 400a87 - 400a6e: b9 70 0f 4a 00 mov $0x4a0f70,%ecx - 400a73: ba af 00 00 00 mov $0xaf,%edx - 400a78: be c4 0e 4a 00 mov $0x4a0ec4,%esi - 400a7d: bf f0 0e 4a 00 mov $0x4a0ef0,%edi - 400a82: e8 b9 0c 00 00 callq 401740 <__assert_fail> - 400a87: 48 8b 05 92 f5 ff ff mov -0xa6e(%rip),%rax # 400020 <__ehdr_start+0x20> - 400a8e: 48 05 00 00 40 00 add $0x400000,%rax - 400a94: 48 89 05 ad c7 2c 00 mov %rax,0x2cc7ad(%rip) # 6cd248 <_dl_phdr> - 400a9b: 0f b7 05 96 f5 ff ff movzwl -0xa6a(%rip),%eax # 400038 <__ehdr_start+0x38> - 400aa2: 48 89 05 d7 c7 2c 00 mov %rax,0x2cc7d7(%rip) # 6cd280 <_dl_phnum> - 400aa9: 8b 05 51 ac 2c 00 mov 0x2cac51(%rip),%eax # 6cb700 <__libc_multiple_libcs> - 400aaf: 85 c0 test %eax,%eax - 400ab1: 74 4c je 400aff - 400ab3: b8 d8 01 40 00 mov $0x4001d8,%eax - 400ab8: 48 3d c8 02 40 00 cmp $0x4002c8,%rax - 400abe: 73 7b jae 400b3b - 400ac0: 83 3d 19 f7 ff ff 25 cmpl $0x25,-0x8e7(%rip) # 4001e0 <__rela_iplt_start+0x8> - 400ac7: 48 8b 2d 0a f7 ff ff mov -0x8f6(%rip),%rbp # 4001d8 <__rela_iplt_start> - 400ace: bb d8 01 40 00 mov $0x4001d8,%ebx - 400ad3: 75 20 jne 400af5 - 400ad5: 0f 1f 00 nopl (%rax) - 400ad8: ff 53 10 callq *0x10(%rbx) - 400adb: 48 83 c3 18 add $0x18,%rbx - 400adf: 48 89 45 00 mov %rax,0x0(%rbp) - 400ae3: 48 81 fb c8 02 40 00 cmp $0x4002c8,%rbx - 400aea: 73 4f jae 400b3b - 400aec: 83 7b 08 25 cmpl $0x25,0x8(%rbx) - 400af0: 48 8b 2b mov (%rbx),%rbp - 400af3: 74 e3 je 400ad8 - 400af5: bf 48 0f 4a 00 mov $0x4a0f48,%edi - 400afa: e8 91 0d 01 00 callq 411890 <__libc_fatal> - 400aff: e8 9c 34 04 00 callq 443fa0 <_dl_discover_osversion> - 400b04: 85 c0 test %eax,%eax - 400b06: 0f 88 4c 01 00 00 js 400c58 - 400b0c: 8b 15 8e c7 2c 00 mov 0x2cc78e(%rip),%edx # 6cd2a0 <_dl_osversion> - 400b12: 85 d2 test %edx,%edx - 400b14: 0f 85 03 01 00 00 jne 400c1d - 400b1a: 89 05 80 c7 2c 00 mov %eax,0x2cc780(%rip) # 6cd2a0 <_dl_osversion> - 400b20: 3d 1f 06 02 00 cmp $0x2061f,%eax - 400b25: 7f 8c jg 400ab3 - 400b27: bf d8 0e 4a 00 mov $0x4a0ed8,%edi - 400b2c: e8 5f 0d 01 00 callq 411890 <__libc_fatal> - 400b31: 31 c0 xor %eax,%eax - 400b33: 48 89 d1 mov %rdx,%rcx - 400b36: e9 d9 fe ff ff jmpq 400a14 - 400b3b: e8 e0 09 00 00 callq 401520 <__pthread_initialize_minimal> - 400b40: 48 8b 15 39 94 2c 00 mov 0x2c9439(%rip),%rdx # 6c9f80 <_dl_random> - 400b47: 48 8b 02 mov (%rdx),%rax - 400b4a: 30 c0 xor %al,%al - 400b4c: 64 48 89 04 25 28 00 mov %rax,%fs:0x28 - 400b53: 00 00 - 400b55: 48 8b 42 08 mov 0x8(%rdx),%rax - 400b59: 64 48 89 04 25 30 00 mov %rax,%fs:0x30 - 400b60: 00 00 - 400b62: 4d 85 f6 test %r14,%r14 - 400b65: 74 0c je 400b73 - 400b67: 31 d2 xor %edx,%edx - 400b69: 31 f6 xor %esi,%esi - 400b6b: 4c 89 f7 mov %r14,%rdi - 400b6e: e8 7d e0 00 00 callq 40ebf0 <__cxa_atexit> - 400b73: 48 8b 15 c6 ba 2c 00 mov 0x2cbac6(%rip),%rdx # 6cc640 <__environ> - 400b7a: 48 8b 74 24 10 mov 0x10(%rsp),%rsi - 400b7f: 8b 7c 24 0c mov 0xc(%rsp),%edi - 400b83: e8 28 35 04 00 callq 4440b0 <__libc_init_first> - 400b88: 4d 85 ed test %r13,%r13 - 400b8b: 74 0c je 400b99 - 400b8d: 31 d2 xor %edx,%edx - 400b8f: 31 f6 xor %esi,%esi - 400b91: 4c 89 ef mov %r13,%rdi - 400b94: e8 57 e0 00 00 callq 40ebf0 <__cxa_atexit> - 400b99: 83 3d f8 93 2c 00 00 cmpl $0x0,0x2c93f8(%rip) # 6c9f98 <__libc_enable_secure> - 400ba0: 0f 85 bc 00 00 00 jne 400c62 - 400ba6: 4d 85 e4 test %r12,%r12 - 400ba9: 74 13 je 400bbe - 400bab: 48 8b 15 8e ba 2c 00 mov 0x2cba8e(%rip),%rdx # 6cc640 <__environ> - 400bb2: 48 8b 74 24 10 mov 0x10(%rsp),%rsi - 400bb7: 8b 7c 24 0c mov 0xc(%rsp),%edi - 400bbb: 41 ff d4 callq *%r12 - 400bbe: 31 ff xor %edi,%edi - 400bc0: 31 f6 xor %esi,%esi - 400bc2: e8 69 1f 04 00 callq 442b30 <_dl_debug_initialize> - 400bc7: 48 8d 7c 24 20 lea 0x20(%rsp),%rdi - 400bcc: e8 9f cf 00 00 callq 40db70 <_setjmp> - 400bd1: 85 c0 test %eax,%eax - 400bd3: 75 55 jne 400c2a - 400bd5: 64 48 8b 04 25 00 03 mov %fs:0x300,%rax - 400bdc: 00 00 - 400bde: 48 89 44 24 68 mov %rax,0x68(%rsp) - 400be3: 64 48 8b 04 25 f8 02 mov %fs:0x2f8,%rax - 400bea: 00 00 - 400bec: 48 89 44 24 70 mov %rax,0x70(%rsp) - 400bf1: 48 8d 44 24 20 lea 0x20(%rsp),%rax - 400bf6: 64 48 89 04 25 00 03 mov %rax,%fs:0x300 - 400bfd: 00 00 - 400bff: 48 8b 15 3a ba 2c 00 mov 0x2cba3a(%rip),%rdx # 6cc640 <__environ> - 400c06: 48 8b 74 24 10 mov 0x10(%rsp),%rsi - 400c0b: 8b 7c 24 0c mov 0xc(%rsp),%edi - 400c0f: 48 8b 44 24 18 mov 0x18(%rsp),%rax - 400c14: ff d0 callq *%rax - 400c16: 89 c7 mov %eax,%edi - 400c18: e8 d3 dd 00 00 callq 40e9f0 - 400c1d: 39 c2 cmp %eax,%edx - 400c1f: 0f 86 fb fe ff ff jbe 400b20 - 400c25: e9 f0 fe ff ff jmpq 400b1a - 400c2a: e8 d1 f3 bf ff callq 0 <_nl_current_LC_CTYPE> - 400c2f: f0 ff 0d ca f3 bf ff lock decl -0x400c36(%rip) # 0 <_nl_current_LC_CTYPE> - 400c36: 0f 94 c0 sete %al - 400c39: 84 c0 test %al,%al - 400c3b: 74 04 je 400c41 - 400c3d: 31 c0 xor %eax,%eax - 400c3f: eb d5 jmp 400c16 - 400c41: ba 3c 00 00 00 mov $0x3c,%edx - 400c46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 400c4d: 00 00 00 - 400c50: 31 ff xor %edi,%edi - 400c52: 89 d0 mov %edx,%eax - 400c54: 0f 05 syscall - 400c56: eb f8 jmp 400c50 - 400c58: bf 20 0f 4a 00 mov $0x4a0f20,%edi - 400c5d: e8 2e 0c 01 00 callq 411890 <__libc_fatal> - 400c62: e8 59 04 00 00 callq 4010c0 <__libc_check_standard_fds> - 400c67: e9 3a ff ff ff jmpq 400ba6 - 400c6c: 0f 1f 40 00 nopl 0x0(%rax) - -0000000000400c70 : - 400c70: 49 89 d1 mov %rdx,%r9 - 400c73: 53 push %rbx - 400c74: 49 89 c8 mov %rcx,%r8 - 400c77: b8 01 00 00 00 mov $0x1,%eax - 400c7c: 0f a2 cpuid - 400c7e: 89 15 10 ba 2c 00 mov %edx,0x2cba10(%rip) # 6cc694 <_dl_x86_cpu_features+0x14> - 400c84: 89 c2 mov %eax,%edx - 400c86: 89 1d 00 ba 2c 00 mov %ebx,0x2cba00(%rip) # 6cc68c <_dl_x86_cpu_features+0xc> - 400c8c: c1 ea 08 shr $0x8,%edx - 400c8f: 89 0d fb b9 2c 00 mov %ecx,0x2cb9fb(%rip) # 6cc690 <_dl_x86_cpu_features+0x10> - 400c95: 89 05 ed b9 2c 00 mov %eax,0x2cb9ed(%rip) # 6cc688 <_dl_x86_cpu_features+0x8> - 400c9b: 83 e2 0f and $0xf,%edx - 400c9e: 89 17 mov %edx,(%rdi) - 400ca0: 89 c2 mov %eax,%edx - 400ca2: c1 ea 04 shr $0x4,%edx - 400ca5: 83 e2 0f and $0xf,%edx - 400ca8: 89 16 mov %edx,(%rsi) - 400caa: 89 c2 mov %eax,%edx - 400cac: c1 ea 0c shr $0xc,%edx - 400caf: 81 e2 f0 00 00 00 and $0xf0,%edx - 400cb5: 41 89 11 mov %edx,(%r9) - 400cb8: 83 3f 0f cmpl $0xf,(%rdi) - 400cbb: 75 12 jne 400ccf - 400cbd: 89 c2 mov %eax,%edx - 400cbf: c1 ea 14 shr $0x14,%edx - 400cc2: 0f b6 d2 movzbl %dl,%edx - 400cc5: 83 c2 0f add $0xf,%edx - 400cc8: 89 17 mov %edx,(%rdi) - 400cca: 41 8b 11 mov (%r9),%edx - 400ccd: 01 16 add %edx,(%rsi) - 400ccf: 83 e0 0f and $0xf,%eax - 400cd2: 41 89 00 mov %eax,(%r8) - 400cd5: 5b pop %rbx - 400cd6: c3 retq - 400cd7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 400cde: 00 00 - -0000000000400ce0 <__libc_start_main>: - 400ce0: 41 55 push %r13 - 400ce2: 41 54 push %r12 - 400ce4: 31 c0 xor %eax,%eax - 400ce6: 55 push %rbp - 400ce7: 53 push %rbx - 400ce8: 48 89 d5 mov %rdx,%rbp - 400ceb: 49 89 cc mov %rcx,%r12 - 400cee: 41 89 f3 mov %esi,%r11d - 400cf1: 49 89 fa mov %rdi,%r10 - 400cf4: 48 83 ec 28 sub $0x28,%rsp - 400cf8: 0f a2 cpuid - 400cfa: 81 fb 47 65 6e 75 cmp $0x756e6547,%ebx - 400d00: 89 05 7e b9 2c 00 mov %eax,0x2cb97e(%rip) # 6cc684 <_dl_x86_cpu_features+0x4> - 400d06: c7 44 24 10 00 00 00 movl $0x0,0x10(%rsp) - 400d0d: 00 - 400d0e: 40 0f 94 c6 sete %sil - 400d12: 81 f9 6e 74 65 6c cmp $0x6c65746e,%ecx - 400d18: c7 44 24 14 00 00 00 movl $0x0,0x14(%rsp) - 400d1f: 00 - 400d20: 0f 94 c0 sete %al - 400d23: c7 44 24 18 00 00 00 movl $0x0,0x18(%rsp) - 400d2a: 00 - 400d2b: 40 84 c6 test %al,%sil - 400d2e: 74 0c je 400d3c <__libc_start_main+0x5c> - 400d30: 81 fa 69 6e 65 49 cmp $0x49656e69,%edx - 400d36: 0f 84 6d 01 00 00 je 400ea9 <__libc_start_main+0x1c9> - 400d3c: 81 fb 41 75 74 68 cmp $0x68747541,%ebx - 400d42: 40 0f 94 c6 sete %sil - 400d46: 81 f9 63 41 4d 44 cmp $0x444d4163,%ecx - 400d4c: 0f 94 c0 sete %al - 400d4f: 40 84 c6 test %al,%sil - 400d52: 74 0c je 400d60 <__libc_start_main+0x80> - 400d54: 81 fa 65 6e 74 69 cmp $0x69746e65,%edx - 400d5a: 0f 84 94 01 00 00 je 400ef4 <__libc_start_main+0x214> - 400d60: 44 8b 2d 29 b9 2c 00 mov 0x2cb929(%rip),%r13d # 6cc690 <_dl_x86_cpu_features+0x10> - 400d67: 8b 7c 24 14 mov 0x14(%rsp),%edi - 400d6b: be 03 00 00 00 mov $0x3,%esi - 400d70: 8b 05 1e b9 2c 00 mov 0x2cb91e(%rip),%eax # 6cc694 <_dl_x86_cpu_features+0x14> - 400d76: f6 c4 01 test $0x1,%ah - 400d79: 74 0a je 400d85 <__libc_start_main+0xa5> - 400d7b: 81 0d 3b b9 2c 00 00 orl $0x4000,0x2cb93b(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> - 400d82: 40 00 00 - 400d85: f6 c4 80 test $0x80,%ah - 400d88: 74 0a je 400d94 <__libc_start_main+0xb4> - 400d8a: 81 0d 2c b9 2c 00 00 orl $0x8000,0x2cb92c(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> - 400d91: 80 00 00 - 400d94: 83 3d e9 b8 2c 00 06 cmpl $0x6,0x2cb8e9(%rip) # 6cc684 <_dl_x86_cpu_features+0x4> - 400d9b: 7e 21 jle 400dbe <__libc_start_main+0xde> - 400d9d: b8 07 00 00 00 mov $0x7,%eax - 400da2: 31 c9 xor %ecx,%ecx - 400da4: 0f a2 cpuid - 400da6: 89 05 ec b8 2c 00 mov %eax,0x2cb8ec(%rip) # 6cc698 <_dl_x86_cpu_features+0x18> - 400dac: 89 1d ea b8 2c 00 mov %ebx,0x2cb8ea(%rip) # 6cc69c <_dl_x86_cpu_features+0x1c> - 400db2: 89 0d e8 b8 2c 00 mov %ecx,0x2cb8e8(%rip) # 6cc6a0 <_dl_x86_cpu_features+0x20> - 400db8: 89 15 e6 b8 2c 00 mov %edx,0x2cb8e6(%rip) # 6cc6a4 <_dl_x86_cpu_features+0x24> - 400dbe: 41 f7 c5 00 00 00 08 test $0x8000000,%r13d - 400dc5: 74 0f je 400dd6 <__libc_start_main+0xf6> - 400dc7: 31 c9 xor %ecx,%ecx - 400dc9: 0f 01 d0 xgetbv - 400dcc: 89 c2 mov %eax,%edx - 400dce: 83 e2 06 and $0x6,%edx - 400dd1: 83 fa 06 cmp $0x6,%edx - 400dd4: 74 6f je 400e45 <__libc_start_main+0x165> - 400dd6: 83 fe 01 cmp $0x1,%esi - 400dd9: 74 2f je 400e0a <__libc_start_main+0x12a> - 400ddb: 8b 44 24 10 mov 0x10(%rsp),%eax - 400ddf: 48 83 ec 08 sub $0x8,%rsp - 400de3: 89 3d d3 b8 2c 00 mov %edi,0x2cb8d3(%rip) # 6cc6bc <_dl_x86_cpu_features+0x3c> - 400de9: ff 74 24 58 pushq 0x58(%rsp) - 400ded: 89 35 8d b8 2c 00 mov %esi,0x2cb88d(%rip) # 6cc680 <_dl_x86_cpu_features> - 400df3: 4c 89 e1 mov %r12,%rcx - 400df6: 48 89 ea mov %rbp,%rdx - 400df9: 44 89 de mov %r11d,%esi - 400dfc: 4c 89 d7 mov %r10,%rdi - 400dff: 89 05 b3 b8 2c 00 mov %eax,0x2cb8b3(%rip) # 6cc6b8 <_dl_x86_cpu_features+0x38> - 400e05: e8 c6 fb ff ff callq 4009d0 - 400e0a: 83 7c 24 10 06 cmpl $0x6,0x10(%rsp) - 400e0f: 75 ca jne 400ddb <__libc_start_main+0xfb> - 400e11: 83 ff 3f cmp $0x3f,%edi - 400e14: 0f 84 7a 01 00 00 je 400f94 <__libc_start_main+0x2b4> - 400e1a: 83 ff 3c cmp $0x3c,%edi - 400e1d: 0f 84 0b 02 00 00 je 40102e <__libc_start_main+0x34e> - 400e23: 8d 47 bb lea -0x45(%rdi),%eax - 400e26: 83 f8 01 cmp $0x1,%eax - 400e29: 0f 86 3d 01 00 00 jbe 400f6c <__libc_start_main+0x28c> - 400e2f: 83 ff 3d cmp $0x3d,%edi - 400e32: 0f 85 4e 01 00 00 jne 400f86 <__libc_start_main+0x2a6> - 400e38: 83 7c 24 18 04 cmpl $0x4,0x18(%rsp) - 400e3d: 0f 86 34 01 00 00 jbe 400f77 <__libc_start_main+0x297> - 400e43: eb 96 jmp 400ddb <__libc_start_main+0xfb> - 400e45: 41 f7 c5 00 00 00 10 test $0x10000000,%r13d - 400e4c: 74 07 je 400e55 <__libc_start_main+0x175> - 400e4e: 83 0d 6b b8 2c 00 40 orl $0x40,0x2cb86b(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> - 400e55: 8b 15 41 b8 2c 00 mov 0x2cb841(%rip),%edx # 6cc69c <_dl_x86_cpu_features+0x1c> - 400e5b: f6 c2 20 test $0x20,%dl - 400e5e: 74 0a je 400e6a <__libc_start_main+0x18a> - 400e60: 81 0d 56 b8 2c 00 00 orl $0xc00,0x2cb856(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> - 400e67: 0c 00 00 - 400e6a: 25 e0 00 00 00 and $0xe0,%eax - 400e6f: 3d e0 00 00 00 cmp $0xe0,%eax - 400e74: 0f 84 8c 01 00 00 je 401006 <__libc_start_main+0x326> - 400e7a: 41 81 e5 00 10 00 00 and $0x1000,%r13d - 400e81: 74 0a je 400e8d <__libc_start_main+0x1ad> - 400e83: 81 0d 33 b8 2c 00 80 orl $0x80,0x2cb833(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> - 400e8a: 00 00 00 - 400e8d: f6 05 1e b8 2c 00 01 testb $0x1,0x2cb81e(%rip) # 6cc6b2 <_dl_x86_cpu_features+0x32> - 400e94: 0f 84 3c ff ff ff je 400dd6 <__libc_start_main+0xf6> - 400e9a: 81 0d 1c b8 2c 00 00 orl $0x100,0x2cb81c(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> - 400ea1: 01 00 00 - 400ea4: e9 2d ff ff ff jmpq 400dd6 <__libc_start_main+0xf6> - 400ea9: 48 8d 4c 24 18 lea 0x18(%rsp),%rcx - 400eae: 48 8d 54 24 1c lea 0x1c(%rsp),%rdx - 400eb3: 48 8d 74 24 14 lea 0x14(%rsp),%rsi - 400eb8: 48 8d 7c 24 10 lea 0x10(%rsp),%rdi - 400ebd: 4c 89 4c 24 08 mov %r9,0x8(%rsp) - 400ec2: 4c 89 04 24 mov %r8,(%rsp) - 400ec6: e8 a5 fd ff ff callq 400c70 - 400ecb: 83 7c 24 10 06 cmpl $0x6,0x10(%rsp) - 400ed0: 44 8b 2d b9 b7 2c 00 mov 0x2cb7b9(%rip),%r13d # 6cc690 <_dl_x86_cpu_features+0x10> - 400ed7: 4c 8b 04 24 mov (%rsp),%r8 - 400edb: 4c 8b 4c 24 08 mov 0x8(%rsp),%r9 - 400ee0: 0f 84 ba 00 00 00 je 400fa0 <__libc_start_main+0x2c0> - 400ee6: be 01 00 00 00 mov $0x1,%esi - 400eeb: 8b 7c 24 14 mov 0x14(%rsp),%edi - 400eef: e9 7c fe ff ff jmpq 400d70 <__libc_start_main+0x90> - 400ef4: 48 8d 4c 24 18 lea 0x18(%rsp),%rcx - 400ef9: 48 8d 54 24 1c lea 0x1c(%rsp),%rdx - 400efe: 48 8d 74 24 14 lea 0x14(%rsp),%rsi - 400f03: 48 8d 7c 24 10 lea 0x10(%rsp),%rdi - 400f08: 4c 89 4c 24 08 mov %r9,0x8(%rsp) - 400f0d: 4c 89 04 24 mov %r8,(%rsp) - 400f11: e8 5a fd ff ff callq 400c70 - 400f16: b8 00 00 00 80 mov $0x80000000,%eax - 400f1b: 4c 8b 04 24 mov (%rsp),%r8 - 400f1f: 4c 8b 4c 24 08 mov 0x8(%rsp),%r9 - 400f24: 0f a2 cpuid - 400f26: 3d 00 00 00 80 cmp $0x80000000,%eax - 400f2b: 76 1f jbe 400f4c <__libc_start_main+0x26c> - 400f2d: b8 01 00 00 80 mov $0x80000001,%eax - 400f32: 0f a2 cpuid - 400f34: 89 05 6e b7 2c 00 mov %eax,0x2cb76e(%rip) # 6cc6a8 <_dl_x86_cpu_features+0x28> - 400f3a: 89 1d 6c b7 2c 00 mov %ebx,0x2cb76c(%rip) # 6cc6ac <_dl_x86_cpu_features+0x2c> - 400f40: 89 0d 6a b7 2c 00 mov %ecx,0x2cb76a(%rip) # 6cc6b0 <_dl_x86_cpu_features+0x30> - 400f46: 89 15 68 b7 2c 00 mov %edx,0x2cb768(%rip) # 6cc6b4 <_dl_x86_cpu_features+0x34> - 400f4c: 83 7c 24 10 15 cmpl $0x15,0x10(%rsp) - 400f51: 8b 7c 24 14 mov 0x14(%rsp),%edi - 400f55: 0f 84 93 00 00 00 je 400fee <__libc_start_main+0x30e> - 400f5b: be 02 00 00 00 mov $0x2,%esi - 400f60: 44 8b 2d 29 b7 2c 00 mov 0x2cb729(%rip),%r13d # 6cc690 <_dl_x86_cpu_features+0x10> - 400f67: e9 04 fe ff ff jmpq 400d70 <__libc_start_main+0x90> - 400f6c: 83 7c 24 18 01 cmpl $0x1,0x18(%rsp) - 400f71: 0f 87 64 fe ff ff ja 400ddb <__libc_start_main+0xfb> - 400f77: 81 25 1b b7 2c 00 ef andl $0xfffff7ef,0x2cb71b(%rip) # 6cc69c <_dl_x86_cpu_features+0x1c> - 400f7e: f7 ff ff - 400f81: e9 55 fe ff ff jmpq 400ddb <__libc_start_main+0xfb> - 400f86: 83 ff 47 cmp $0x47,%edi - 400f89: 74 e1 je 400f6c <__libc_start_main+0x28c> - 400f8b: 83 ff 56 cmp $0x56,%edi - 400f8e: 0f 85 47 fe ff ff jne 400ddb <__libc_start_main+0xfb> - 400f94: 83 7c 24 18 02 cmpl $0x2,0x18(%rsp) - 400f99: 76 dc jbe 400f77 <__libc_start_main+0x297> - 400f9b: e9 3b fe ff ff jmpq 400ddb <__libc_start_main+0xfb> - 400fa0: 8b 44 24 1c mov 0x1c(%rsp),%eax - 400fa4: 03 44 24 14 add 0x14(%rsp),%eax - 400fa8: 83 f8 2f cmp $0x2f,%eax - 400fab: 89 44 24 14 mov %eax,0x14(%rsp) - 400faf: 0f 87 97 00 00 00 ja 40104c <__libc_start_main+0x36c> - 400fb5: 83 f8 2e cmp $0x2e,%eax - 400fb8: 0f 83 df 00 00 00 jae 40109d <__libc_start_main+0x3bd> - 400fbe: 83 f8 1f cmp $0x1f,%eax - 400fc1: 0f 87 b6 00 00 00 ja 40107d <__libc_start_main+0x39d> - 400fc7: 83 f8 1e cmp $0x1e,%eax - 400fca: 0f 83 cd 00 00 00 jae 40109d <__libc_start_main+0x3bd> - 400fd0: 83 f8 1a cmp $0x1a,%eax - 400fd3: 0f 84 c4 00 00 00 je 40109d <__libc_start_main+0x3bd> - 400fd9: 83 f8 1c cmp $0x1c,%eax - 400fdc: 0f 85 ae 00 00 00 jne 401090 <__libc_start_main+0x3b0> - 400fe2: 83 0d d7 b6 2c 00 04 orl $0x4,0x2cb6d7(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> - 400fe9: e9 f8 fe ff ff jmpq 400ee6 <__libc_start_main+0x206> - 400fee: 8d 47 a0 lea -0x60(%rdi),%eax - 400ff1: 83 f8 1f cmp $0x1f,%eax - 400ff4: 0f 87 61 ff ff ff ja 400f5b <__libc_start_main+0x27b> - 400ffa: 83 0d bf b6 2c 00 10 orl $0x10,0x2cb6bf(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> - 401001: e9 55 ff ff ff jmpq 400f5b <__libc_start_main+0x27b> - 401006: f7 c2 00 00 01 00 test $0x10000,%edx - 40100c: 0f 84 68 fe ff ff je 400e7a <__libc_start_main+0x19a> - 401012: 81 e2 00 00 02 00 and $0x20000,%edx - 401018: 8b 05 a2 b6 2c 00 mov 0x2cb6a2(%rip),%eax # 6cc6c0 <_dl_x86_cpu_features+0x40> - 40101e: 75 1e jne 40103e <__libc_start_main+0x35e> - 401020: 80 cc 10 or $0x10,%ah - 401023: 89 05 97 b6 2c 00 mov %eax,0x2cb697(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> - 401029: e9 4c fe ff ff jmpq 400e7a <__libc_start_main+0x19a> - 40102e: 83 7c 24 18 03 cmpl $0x3,0x18(%rsp) - 401033: 0f 86 3e ff ff ff jbe 400f77 <__libc_start_main+0x297> - 401039: e9 9d fd ff ff jmpq 400ddb <__libc_start_main+0xfb> - 40103e: 80 cc 30 or $0x30,%ah - 401041: 89 05 79 b6 2c 00 mov %eax,0x2cb679(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> - 401047: e9 2e fe ff ff jmpq 400e7a <__libc_start_main+0x19a> - 40104c: 83 f8 4d cmp $0x4d,%eax - 40104f: 74 62 je 4010b3 <__libc_start_main+0x3d3> - 401051: 76 56 jbe 4010a9 <__libc_start_main+0x3c9> - 401053: 83 f8 5a cmp $0x5a,%eax - 401056: 74 5b je 4010b3 <__libc_start_main+0x3d3> - 401058: 83 f8 5d cmp $0x5d,%eax - 40105b: 74 56 je 4010b3 <__libc_start_main+0x3d3> - 40105d: 83 f8 57 cmp $0x57,%eax - 401060: 75 2e jne 401090 <__libc_start_main+0x3b0> - 401062: 8b 05 58 b6 2c 00 mov 0x2cb658(%rip),%eax # 6cc6c0 <_dl_x86_cpu_features+0x40> - 401068: 0d 00 00 02 00 or $0x20000,%eax - 40106d: 0d 30 02 00 00 or $0x230,%eax - 401072: 89 05 48 b6 2c 00 mov %eax,0x2cb648(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> - 401078: e9 69 fe ff ff jmpq 400ee6 <__libc_start_main+0x206> - 40107d: 83 f8 26 cmp $0x26,%eax - 401080: 0f 84 5c ff ff ff je 400fe2 <__libc_start_main+0x302> - 401086: 83 f8 2c cmp $0x2c,%eax - 401089: 74 12 je 40109d <__libc_start_main+0x3bd> - 40108b: 83 f8 25 cmp $0x25,%eax - 40108e: 74 0d je 40109d <__libc_start_main+0x3bd> - 401090: 41 f7 c5 00 00 00 10 test $0x10000000,%r13d - 401097: 0f 84 49 fe ff ff je 400ee6 <__libc_start_main+0x206> - 40109d: 83 0d 1c b6 2c 00 33 orl $0x33,0x2cb61c(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> - 4010a4: e9 3d fe ff ff jmpq 400ee6 <__libc_start_main+0x206> - 4010a9: 83 f8 37 cmp $0x37,%eax - 4010ac: 74 05 je 4010b3 <__libc_start_main+0x3d3> - 4010ae: 83 f8 4a cmp $0x4a,%eax - 4010b1: 75 dd jne 401090 <__libc_start_main+0x3b0> - 4010b3: 8b 05 07 b6 2c 00 mov 0x2cb607(%rip),%eax # 6cc6c0 <_dl_x86_cpu_features+0x40> - 4010b9: eb b2 jmp 40106d <__libc_start_main+0x38d> - 4010bb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - -00000000004010c0 <__libc_check_standard_fds>: - 4010c0: 48 81 ec 98 00 00 00 sub $0x98,%rsp - 4010c7: 31 ff xor %edi,%edi - 4010c9: 31 c0 xor %eax,%eax - 4010cb: be 01 00 00 00 mov $0x1,%esi - 4010d0: e8 fb e1 03 00 callq 43f2d0 <__libc_fcntl> - 4010d5: 83 f8 ff cmp $0xffffffff,%eax - 4010d8: 74 3c je 401116 <__libc_check_standard_fds+0x56> - 4010da: 31 c0 xor %eax,%eax - 4010dc: be 01 00 00 00 mov $0x1,%esi - 4010e1: bf 01 00 00 00 mov $0x1,%edi - 4010e6: e8 e5 e1 03 00 callq 43f2d0 <__libc_fcntl> - 4010eb: 83 f8 ff cmp $0xffffffff,%eax - 4010ee: 0f 84 8f 00 00 00 je 401183 <__libc_check_standard_fds+0xc3> - 4010f4: 31 c0 xor %eax,%eax - 4010f6: be 01 00 00 00 mov $0x1,%esi - 4010fb: bf 02 00 00 00 mov $0x2,%edi - 401100: e8 cb e1 03 00 callq 43f2d0 <__libc_fcntl> - 401105: 83 f8 ff cmp $0xffffffff,%eax - 401108: 0f 84 e5 00 00 00 je 4011f3 <__libc_check_standard_fds+0x133> - 40110e: 48 81 c4 98 00 00 00 add $0x98,%rsp - 401115: c3 retq - 401116: 49 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%r8 - 40111d: 64 41 83 38 09 cmpl $0x9,%fs:(%r8) - 401122: 75 b6 jne 4010da <__libc_check_standard_fds+0x1a> - 401124: 31 d2 xor %edx,%edx - 401126: be 01 00 02 00 mov $0x20001,%esi - 40112b: bf 83 0f 4a 00 mov $0x4a0f83,%edi - 401130: b8 02 00 00 00 mov $0x2,%eax - 401135: 0f 05 syscall - 401137: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 40113d: 0f 87 20 01 00 00 ja 401263 <__libc_check_standard_fds+0x1a3> - 401143: 85 c0 test %eax,%eax - 401145: 75 39 jne 401180 <__libc_check_standard_fds+0xc0> - 401147: 31 f6 xor %esi,%esi - 401149: 48 89 e2 mov %rsp,%rdx - 40114c: bf 01 00 00 00 mov $0x1,%edi - 401151: e8 7a df 03 00 callq 43f0d0 <__fxstat> - 401156: 85 c0 test %eax,%eax - 401158: 75 26 jne 401180 <__libc_check_standard_fds+0xc0> - 40115a: 8b 44 24 18 mov 0x18(%rsp),%eax - 40115e: 25 00 f0 00 00 and $0xf000,%eax - 401163: 3d 00 20 00 00 cmp $0x2000,%eax - 401168: 75 16 jne 401180 <__libc_check_standard_fds+0xc0> - 40116a: 48 81 7c 24 28 07 01 cmpq $0x107,0x28(%rsp) - 401171: 00 00 - 401173: 0f 84 61 ff ff ff je 4010da <__libc_check_standard_fds+0x1a> - 401179: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 401180: f4 hlt - 401181: eb fd jmp 401180 <__libc_check_standard_fds+0xc0> - 401183: 49 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%r8 - 40118a: 64 41 83 38 09 cmpl $0x9,%fs:(%r8) - 40118f: 0f 85 5f ff ff ff jne 4010f4 <__libc_check_standard_fds+0x34> - 401195: 31 d2 xor %edx,%edx - 401197: be 00 00 02 00 mov $0x20000,%esi - 40119c: bf 8d 0f 4a 00 mov $0x4a0f8d,%edi - 4011a1: b8 02 00 00 00 mov $0x2,%eax - 4011a6: 0f 05 syscall - 4011a8: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 4011ae: 0f 87 c2 00 00 00 ja 401276 <__libc_check_standard_fds+0x1b6> - 4011b4: 83 f8 01 cmp $0x1,%eax - 4011b7: 75 37 jne 4011f0 <__libc_check_standard_fds+0x130> - 4011b9: 48 89 e2 mov %rsp,%rdx - 4011bc: be 01 00 00 00 mov $0x1,%esi - 4011c1: bf 01 00 00 00 mov $0x1,%edi - 4011c6: e8 05 df 03 00 callq 43f0d0 <__fxstat> - 4011cb: 85 c0 test %eax,%eax - 4011cd: 75 21 jne 4011f0 <__libc_check_standard_fds+0x130> - 4011cf: 8b 44 24 18 mov 0x18(%rsp),%eax - 4011d3: 25 00 f0 00 00 and $0xf000,%eax - 4011d8: 3d 00 20 00 00 cmp $0x2000,%eax - 4011dd: 75 11 jne 4011f0 <__libc_check_standard_fds+0x130> - 4011df: 48 81 7c 24 28 03 01 cmpq $0x103,0x28(%rsp) - 4011e6: 00 00 - 4011e8: 0f 84 06 ff ff ff je 4010f4 <__libc_check_standard_fds+0x34> - 4011ee: 66 90 xchg %ax,%ax - 4011f0: f4 hlt - 4011f1: eb fd jmp 4011f0 <__libc_check_standard_fds+0x130> - 4011f3: 49 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%r8 - 4011fa: 64 41 83 38 09 cmpl $0x9,%fs:(%r8) - 4011ff: 0f 85 09 ff ff ff jne 40110e <__libc_check_standard_fds+0x4e> - 401205: 31 d2 xor %edx,%edx - 401207: be 00 00 02 00 mov $0x20000,%esi - 40120c: bf 8d 0f 4a 00 mov $0x4a0f8d,%edi - 401211: b8 02 00 00 00 mov $0x2,%eax - 401216: 0f 05 syscall - 401218: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 40121e: 77 4e ja 40126e <__libc_check_standard_fds+0x1ae> - 401220: 83 f8 02 cmp $0x2,%eax - 401223: 75 3b jne 401260 <__libc_check_standard_fds+0x1a0> - 401225: 48 89 e2 mov %rsp,%rdx - 401228: be 02 00 00 00 mov $0x2,%esi - 40122d: bf 01 00 00 00 mov $0x1,%edi - 401232: e8 99 de 03 00 callq 43f0d0 <__fxstat> - 401237: 85 c0 test %eax,%eax - 401239: 75 25 jne 401260 <__libc_check_standard_fds+0x1a0> - 40123b: 8b 44 24 18 mov 0x18(%rsp),%eax - 40123f: 25 00 f0 00 00 and $0xf000,%eax - 401244: 3d 00 20 00 00 cmp $0x2000,%eax - 401249: 75 15 jne 401260 <__libc_check_standard_fds+0x1a0> - 40124b: 48 81 7c 24 28 03 01 cmpq $0x103,0x28(%rsp) - 401252: 00 00 - 401254: 0f 84 b4 fe ff ff je 40110e <__libc_check_standard_fds+0x4e> - 40125a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 401260: f4 hlt - 401261: eb fd jmp 401260 <__libc_check_standard_fds+0x1a0> - 401263: f7 d8 neg %eax - 401265: 64 41 89 00 mov %eax,%fs:(%r8) - 401269: e9 12 ff ff ff jmpq 401180 <__libc_check_standard_fds+0xc0> - 40126e: f7 d8 neg %eax - 401270: 64 41 89 00 mov %eax,%fs:(%r8) - 401274: eb ea jmp 401260 <__libc_check_standard_fds+0x1a0> - 401276: f7 d8 neg %eax - 401278: 64 41 89 00 mov %eax,%fs:(%r8) - 40127c: e9 6f ff ff ff jmpq 4011f0 <__libc_check_standard_fds+0x130> - 401281: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 401288: 00 00 00 - 40128b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - -0000000000401290 <__libc_setup_tls>: - 401290: 41 57 push %r15 - 401292: 41 56 push %r14 - 401294: 41 55 push %r13 - 401296: 41 54 push %r12 - 401298: 55 push %rbp - 401299: 53 push %rbx - 40129a: 48 89 f3 mov %rsi,%rbx - 40129d: 48 83 ec 18 sub $0x18,%rsp - 4012a1: 48 8b 15 a0 bf 2c 00 mov 0x2cbfa0(%rip),%rdx # 6cd248 <_dl_phdr> - 4012a8: 48 85 d2 test %rdx,%rdx - 4012ab: 74 53 je 401300 <__libc_setup_tls+0x70> - 4012ad: 48 8b 05 cc bf 2c 00 mov 0x2cbfcc(%rip),%rax # 6cd280 <_dl_phnum> - 4012b4: 48 8d 0c c5 00 00 00 lea 0x0(,%rax,8),%rcx - 4012bb: 00 - 4012bc: 48 c1 e0 06 shl $0x6,%rax - 4012c0: 48 29 c8 sub %rcx,%rax - 4012c3: 48 01 d0 add %rdx,%rax - 4012c6: 48 39 c2 cmp %rax,%rdx - 4012c9: 72 0e jb 4012d9 <__libc_setup_tls+0x49> - 4012cb: eb 33 jmp 401300 <__libc_setup_tls+0x70> - 4012cd: 0f 1f 00 nopl (%rax) - 4012d0: 48 83 c2 38 add $0x38,%rdx - 4012d4: 48 39 c2 cmp %rax,%rdx - 4012d7: 73 27 jae 401300 <__libc_setup_tls+0x70> - 4012d9: 83 3a 07 cmpl $0x7,(%rdx) - 4012dc: 75 f2 jne 4012d0 <__libc_setup_tls+0x40> - 4012de: 4c 8b 72 30 mov 0x30(%rdx),%r14 - 4012e2: 48 8b 6a 28 mov 0x28(%rdx),%rbp - 4012e6: 4c 8b 62 20 mov 0x20(%rdx),%r12 - 4012ea: 4c 8b 6a 10 mov 0x10(%rdx),%r13 - 4012ee: 4c 39 f3 cmp %r14,%rbx - 4012f1: 49 0f 42 de cmovb %r14,%rbx - 4012f5: eb 14 jmp 40130b <__libc_setup_tls+0x7b> - 4012f7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 4012fe: 00 00 - 401300: 45 31 f6 xor %r14d,%r14d - 401303: 45 31 ed xor %r13d,%r13d - 401306: 45 31 e4 xor %r12d,%r12d - 401309: 31 ed xor %ebp,%ebp - 40130b: 48 89 e8 mov %rbp,%rax - 40130e: 48 03 05 7b 8d 2c 00 add 0x2c8d7b(%rip),%rax # 6ca090 <_dl_tls_static_size> - 401315: 31 d2 xor %edx,%edx - 401317: 48 01 df add %rbx,%rdi - 40131a: 48 8d 44 18 ff lea -0x1(%rax,%rbx,1),%rax - 40131f: 48 f7 f3 div %rbx - 401322: 48 0f af c3 imul %rbx,%rax - 401326: 48 01 c7 add %rax,%rdi - 401329: 49 89 c7 mov %rax,%r15 - 40132c: e8 bf e7 03 00 callq 43faf0 <__sbrk> - 401331: 48 8d 74 18 ff lea -0x1(%rax,%rbx,1),%rsi - 401336: 48 89 d8 mov %rbx,%rax - 401339: 48 c7 05 3c ba 2c 00 movq $0x3e,0x2cba3c(%rip) # 6ccd80 <_dl_static_dtv> - 401340: 3e 00 00 00 - 401344: 48 f7 d8 neg %rax - 401347: 4c 8b 0d 72 9e 2c 00 mov 0x2c9e72(%rip),%r9 # 6cb1c0 <_dl_ns> - 40134e: 48 89 f1 mov %rsi,%rcx - 401351: 48 21 c1 and %rax,%rcx - 401354: 4d 85 f6 test %r14,%r14 - 401357: 74 77 je 4013d0 <__libc_setup_tls+0x140> - 401359: 4a 8d 44 35 ff lea -0x1(%rbp,%r14,1),%rax - 40135e: 31 d2 xor %edx,%edx - 401360: 4c 89 ff mov %r15,%rdi - 401363: 49 f7 f6 div %r14 - 401366: 49 0f af c6 imul %r14,%rax - 40136a: 48 29 c7 sub %rax,%rdi - 40136d: 48 01 cf add %rcx,%rdi - 401370: 4c 89 ee mov %r13,%rsi - 401373: 49 89 81 40 04 00 00 mov %rax,0x440(%r9) - 40137a: 4c 89 e2 mov %r12,%rdx - 40137d: 48 89 0c 24 mov %rcx,(%rsp) - 401381: 48 89 3d 18 ba 2c 00 mov %rdi,0x2cba18(%rip) # 6ccda0 <_dl_static_dtv+0x20> - 401388: 4c 89 4c 24 08 mov %r9,0x8(%rsp) - 40138d: c6 05 14 ba 2c 00 01 movb $0x1,0x2cba14(%rip) # 6ccda8 <_dl_static_dtv+0x28> - 401394: e8 87 ac 02 00 callq 42c020 - 401399: 48 8b 0c 24 mov (%rsp),%rcx - 40139d: bf 02 10 00 00 mov $0x1002,%edi - 4013a2: b8 9e 00 00 00 mov $0x9e,%eax - 4013a7: 4a 8d 34 39 lea (%rcx,%r15,1),%rsi - 4013ab: 48 c7 46 08 90 cd 6c movq $0x6ccd90,0x8(%rsi) - 4013b2: 00 - 4013b3: 48 89 36 mov %rsi,(%rsi) - 4013b6: 48 89 76 10 mov %rsi,0x10(%rsi) - 4013ba: 0f 05 syscall - 4013bc: 85 c0 test %eax,%eax - 4013be: 74 20 je 4013e0 <__libc_setup_tls+0x150> - 4013c0: bf 98 0f 4a 00 mov $0x4a0f98,%edi - 4013c5: e8 c6 04 01 00 callq 411890 <__libc_fatal> - 4013ca: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4013d0: 4c 89 ff mov %r15,%rdi - 4013d3: 48 89 e8 mov %rbp,%rax - 4013d6: 48 29 ef sub %rbp,%rdi - 4013d9: 48 01 cf add %rcx,%rdi - 4013dc: eb 92 jmp 401370 <__libc_setup_tls+0xe0> - 4013de: 66 90 xchg %ax,%ax - 4013e0: 4c 8b 4c 24 08 mov 0x8(%rsp),%r9 - 4013e5: 4d 85 f6 test %r14,%r14 - 4013e8: 48 c7 05 cd a7 2c 00 movq $0x40,0x2ca7cd(%rip) # 6cbbc0 - 4013ef: 40 00 00 00 - 4013f3: 48 c7 05 72 b9 2c 00 movq $0x1,0x2cb972(%rip) # 6ccd70 <_dl_tls_max_dtv_idx> - 4013fa: 01 00 00 00 - 4013fe: 48 c7 05 77 bd 2c 00 movq $0x6cbbc0,0x2cbd77(%rip) # 6cd180 <_dl_tls_dtv_slotinfo_list> - 401405: c0 bb 6c 00 - 401409: 4d 89 b1 30 04 00 00 mov %r14,0x430(%r9) - 401410: 49 89 a9 28 04 00 00 mov %rbp,0x428(%r9) - 401417: 4d 89 a9 18 04 00 00 mov %r13,0x418(%r9) - 40141e: 4d 89 a1 20 04 00 00 mov %r12,0x420(%r9) - 401425: 49 c7 81 48 04 00 00 movq $0x1,0x448(%r9) - 40142c: 01 00 00 00 - 401430: 4c 89 0d b1 a7 2c 00 mov %r9,0x2ca7b1(%rip) # 6cbbe8 - 401437: 75 67 jne 4014a0 <__libc_setup_tls+0x210> - 401439: 48 89 e8 mov %rbp,%rax - 40143c: ba 01 00 00 00 mov $0x1,%edx - 401441: 48 0f af c2 imul %rdx,%rax - 401445: 48 8b 15 44 8c 2c 00 mov 0x2c8c44(%rip),%rdx # 6ca090 <_dl_tls_static_size> - 40144c: 48 c7 05 41 bd 2c 00 movq $0x1,0x2cbd41(%rip) # 6cd198 <_dl_tls_static_nelem> - 401453: 01 00 00 00 - 401457: 48 8d 54 10 3f lea 0x3f(%rax,%rdx,1),%rdx - 40145c: 48 89 05 fd b8 2c 00 mov %rax,0x2cb8fd(%rip) # 6ccd60 <_dl_tls_static_used> - 401463: b8 40 00 00 00 mov $0x40,%eax - 401468: 48 83 e2 c0 and $0xffffffffffffffc0,%rdx - 40146c: 48 81 c2 00 09 00 00 add $0x900,%rdx - 401473: 48 83 fb 40 cmp $0x40,%rbx - 401477: 48 0f 42 d8 cmovb %rax,%rbx - 40147b: 48 89 15 0e 8c 2c 00 mov %rdx,0x2c8c0e(%rip) # 6ca090 <_dl_tls_static_size> - 401482: 48 89 1d df b8 2c 00 mov %rbx,0x2cb8df(%rip) # 6ccd68 <_dl_tls_static_align> - 401489: 48 83 c4 18 add $0x18,%rsp - 40148d: 5b pop %rbx - 40148e: 5d pop %rbp - 40148f: 41 5c pop %r12 - 401491: 41 5d pop %r13 - 401493: 41 5e pop %r14 - 401495: 41 5f pop %r15 - 401497: c3 retq - 401498: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 40149f: 00 - 4014a0: 4a 8d 44 35 ff lea -0x1(%rbp,%r14,1),%rax - 4014a5: 31 d2 xor %edx,%edx - 4014a7: 49 f7 f6 div %r14 - 4014aa: 4c 89 f2 mov %r14,%rdx - 4014ad: eb 92 jmp 401441 <__libc_setup_tls+0x1b1> - 4014af: 90 nop - -00000000004014b0 <_dl_tls_setup>: - 4014b0: 48 8b 05 d9 8b 2c 00 mov 0x2c8bd9(%rip),%rax # 6ca090 <_dl_tls_static_size> - 4014b7: 48 c7 05 fe a6 2c 00 movq $0x40,0x2ca6fe(%rip) # 6cbbc0 - 4014be: 40 00 00 00 - 4014c2: 48 c7 05 a3 b8 2c 00 movq $0x1,0x2cb8a3(%rip) # 6ccd70 <_dl_tls_max_dtv_idx> - 4014c9: 01 00 00 00 - 4014cd: 48 c7 05 a8 bc 2c 00 movq $0x6cbbc0,0x2cbca8(%rip) # 6cd180 <_dl_tls_dtv_slotinfo_list> - 4014d4: c0 bb 6c 00 - 4014d8: 48 c7 05 7d b8 2c 00 movq $0x900,0x2cb87d(%rip) # 6ccd60 <_dl_tls_static_used> - 4014df: 00 09 00 00 - 4014e3: 48 c7 05 7a b8 2c 00 movq $0x40,0x2cb87a(%rip) # 6ccd68 <_dl_tls_static_align> - 4014ea: 40 00 00 00 - 4014ee: 48 05 3f 09 00 00 add $0x93f,%rax - 4014f4: 48 c7 05 99 bc 2c 00 movq $0x1,0x2cbc99(%rip) # 6cd198 <_dl_tls_static_nelem> - 4014fb: 01 00 00 00 - 4014ff: 48 83 e0 c0 and $0xffffffffffffffc0,%rax - 401503: 48 05 00 09 00 00 add $0x900,%rax - 401509: 48 89 05 80 8b 2c 00 mov %rax,0x2c8b80(%rip) # 6ca090 <_dl_tls_static_size> - 401510: 31 c0 xor %eax,%eax - 401512: c3 retq - 401513: 0f 1f 00 nopl (%rax) - 401516: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 40151d: 00 00 00 - -0000000000401520 <__pthread_initialize_minimal>: - 401520: be 40 00 00 00 mov $0x40,%esi - 401525: bf 00 09 00 00 mov $0x900,%edi - 40152a: e9 61 fd ff ff jmpq 401290 <__libc_setup_tls> - 40152f: 90 nop - -0000000000401530 <__libc_csu_init>: - 401530: 41 56 push %r14 - 401532: 41 be d8 9e 6c 00 mov $0x6c9ed8,%r14d - 401538: 41 55 push %r13 - 40153a: 49 81 ee d8 9e 6c 00 sub $0x6c9ed8,%r14 - 401541: 41 54 push %r12 - 401543: 55 push %rbp - 401544: 49 c1 fe 03 sar $0x3,%r14 - 401548: 53 push %rbx - 401549: 31 db xor %ebx,%ebx - 40154b: 4d 85 f6 test %r14,%r14 - 40154e: 89 fd mov %edi,%ebp - 401550: 49 89 f4 mov %rsi,%r12 - 401553: 49 89 d5 mov %rdx,%r13 - 401556: 74 20 je 401578 <__libc_csu_init+0x48> - 401558: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 40155f: 00 - 401560: 4c 89 ea mov %r13,%rdx - 401563: 4c 89 e6 mov %r12,%rsi - 401566: 89 ef mov %ebp,%edi - 401568: ff 14 dd d8 9e 6c 00 callq *0x6c9ed8(,%rbx,8) - 40156f: 48 83 c3 01 add $0x1,%rbx - 401573: 4c 39 f3 cmp %r14,%rbx - 401576: 75 e8 jne 401560 <__libc_csu_init+0x30> - 401578: 41 be e8 9e 6c 00 mov $0x6c9ee8,%r14d - 40157e: 31 db xor %ebx,%ebx - 401580: 49 81 ee d8 9e 6c 00 sub $0x6c9ed8,%r14 - 401587: 49 c1 fe 03 sar $0x3,%r14 - 40158b: e8 38 ed ff ff callq 4002c8 <__rela_iplt_end> - 401590: 4d 85 f6 test %r14,%r14 - 401593: 74 1b je 4015b0 <__libc_csu_init+0x80> - 401595: 0f 1f 00 nopl (%rax) - 401598: 4c 89 ea mov %r13,%rdx - 40159b: 4c 89 e6 mov %r12,%rsi - 40159e: 89 ef mov %ebp,%edi - 4015a0: ff 14 dd d8 9e 6c 00 callq *0x6c9ed8(,%rbx,8) - 4015a7: 48 83 c3 01 add $0x1,%rbx - 4015ab: 4c 39 f3 cmp %r14,%rbx - 4015ae: 75 e8 jne 401598 <__libc_csu_init+0x68> - 4015b0: 5b pop %rbx - 4015b1: 5d pop %rbp - 4015b2: 41 5c pop %r12 - 4015b4: 41 5d pop %r13 - 4015b6: 41 5e pop %r14 - 4015b8: c3 retq - 4015b9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - -00000000004015c0 <__libc_csu_fini>: - 4015c0: 53 push %rbx - 4015c1: bb f8 9e 6c 00 mov $0x6c9ef8,%ebx - 4015c6: 48 81 eb e8 9e 6c 00 sub $0x6c9ee8,%rbx - 4015cd: 48 c1 fb 03 sar $0x3,%rbx - 4015d1: 48 85 db test %rbx,%rbx - 4015d4: 74 17 je 4015ed <__libc_csu_fini+0x2d> - 4015d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4015dd: 00 00 00 - 4015e0: ff 14 dd e0 9e 6c 00 callq *0x6c9ee0(,%rbx,8) - 4015e7: 48 83 eb 01 sub $0x1,%rbx - 4015eb: 75 f3 jne 4015e0 <__libc_csu_fini+0x20> - 4015ed: 5b pop %rbx - 4015ee: e9 ad f8 09 00 jmpq 4a0ea0 <_fini> - 4015f3: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4015fa: 00 00 00 - 4015fd: 0f 1f 00 nopl (%rax) - -0000000000401600 <__assert_fail_base>: - 401600: 41 56 push %r14 - 401602: 41 55 push %r13 - 401604: b8 00 00 00 00 mov $0x0,%eax - 401609: 41 54 push %r12 - 40160b: 55 push %rbp - 40160c: 49 89 f6 mov %rsi,%r14 - 40160f: 53 push %rbx - 401610: 48 89 fd mov %rdi,%rbp - 401613: 49 89 d4 mov %rdx,%r12 - 401616: 41 89 cd mov %ecx,%r13d - 401619: 4c 89 c3 mov %r8,%rbx - 40161c: 48 83 ec 10 sub $0x10,%rsp - 401620: 48 85 c0 test %rax,%rax - 401623: 74 09 je 40162e <__assert_fail_base+0x2e> - 401625: 31 f6 xor %esi,%esi - 401627: bf 01 00 00 00 mov $0x1,%edi - 40162c: ff d0 callq *%rax - 40162e: 48 8b 3d ab 9a 2c 00 mov 0x2c9aab(%rip),%rdi # 6cb0e0 <__progname> - 401635: be 25 67 4b 00 mov $0x4b6725,%esi - 40163a: b8 6f 52 4b 00 mov $0x4b526f,%eax - 40163f: 48 85 db test %rbx,%rbx - 401642: 48 89 f2 mov %rsi,%rdx - 401645: 48 89 c1 mov %rax,%rcx - 401648: 48 0f 44 ce cmove %rsi,%rcx - 40164c: 48 0f 45 d3 cmovne %rbx,%rdx - 401650: 45 89 e9 mov %r13d,%r9d - 401653: 80 3f 00 cmpb $0x0,(%rdi) - 401656: 4d 89 e0 mov %r12,%r8 - 401659: 48 0f 44 c6 cmove %rsi,%rax - 40165d: 48 8d 74 24 04 lea 0x4(%rsp),%rsi - 401662: 56 push %rsi - 401663: 41 56 push %r14 - 401665: 48 89 ee mov %rbp,%rsi - 401668: 51 push %rcx - 401669: 52 push %rdx - 40166a: 48 89 fa mov %rdi,%rdx - 40166d: 48 89 c1 mov %rax,%rcx - 401670: 31 c0 xor %eax,%eax - 401672: 48 8d 7c 24 28 lea 0x28(%rsp),%rdi - 401677: e8 84 dc 00 00 callq 40f300 <___asprintf> - 40167c: 48 83 c4 20 add $0x20,%rsp - 401680: 85 c0 test %eax,%eax - 401682: 0f 88 93 00 00 00 js 40171b <__assert_fail_base+0x11b> - 401688: 48 8b 54 24 08 mov 0x8(%rsp),%rdx - 40168d: be 99 c4 4b 00 mov $0x4bc499,%esi - 401692: 31 ff xor %edi,%edi - 401694: 31 c0 xor %eax,%eax - 401696: e8 f5 dc 00 00 callq 40f390 <__fxprintf> - 40169b: 48 8b 3d 96 90 2c 00 mov 0x2c9096(%rip),%rdi # 6ca738 <_IO_stderr> - 4016a2: e8 99 e0 00 00 callq 40f740 <_IO_fflush> - 4016a7: 48 8b 05 d2 9a 2c 00 mov 0x2c9ad2(%rip),%rax # 6cb180 <_dl_pagesize> - 4016ae: 8b 74 24 04 mov 0x4(%rsp),%esi - 4016b2: 45 31 c9 xor %r9d,%r9d - 4016b5: 31 ff xor %edi,%edi - 4016b7: 41 b8 ff ff ff ff mov $0xffffffff,%r8d - 4016bd: b9 22 00 00 00 mov $0x22,%ecx - 4016c2: ba 03 00 00 00 mov $0x3,%edx - 4016c7: 01 c6 add %eax,%esi - 4016c9: f7 d8 neg %eax - 4016cb: 21 c6 and %eax,%esi - 4016cd: 89 74 24 04 mov %esi,0x4(%rsp) - 4016d1: 48 63 f6 movslq %esi,%rsi - 4016d4: e8 17 e5 03 00 callq 43fbf0 <__mmap> - 4016d9: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 4016dd: 48 89 c3 mov %rax,%rbx - 4016e0: 74 2a je 40170c <__assert_fail_base+0x10c> - 4016e2: 8b 44 24 04 mov 0x4(%rsp),%eax - 4016e6: 48 8b 74 24 08 mov 0x8(%rsp),%rsi - 4016eb: 48 8d 7b 04 lea 0x4(%rbx),%rdi - 4016ef: 89 03 mov %eax,(%rbx) - 4016f1: e8 fa eb ff ff callq 4002f0 <__rela_iplt_end+0x28> - 4016f6: 48 89 df mov %rbx,%rdi - 4016f9: 48 87 3d 20 aa 2c 00 xchg %rdi,0x2caa20(%rip) # 6cc120 <__abort_msg> - 401700: 48 85 ff test %rdi,%rdi - 401703: 74 07 je 40170c <__assert_fail_base+0x10c> - 401705: 8b 37 mov (%rdi),%esi - 401707: e8 a4 e5 03 00 callq 43fcb0 <__munmap> - 40170c: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi - 401711: e8 9a c6 01 00 callq 41ddb0 <__cfree> - 401716: e8 e5 c4 00 00 callq 40dc00 - 40171b: ba 12 00 00 00 mov $0x12,%edx - 401720: be 00 10 4a 00 mov $0x4a1000,%esi - 401725: bf 02 00 00 00 mov $0x2,%edi - 40172a: e8 b1 da 03 00 callq 43f1e0 <__libc_write> - 40172f: eb e5 jmp 401716 <__assert_fail_base+0x116> - 401731: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 401736: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 40173d: 00 00 00 - -0000000000401740 <__assert_fail>: - 401740: 41 55 push %r13 - 401742: 41 54 push %r12 - 401744: 49 89 cd mov %rcx,%r13 - 401747: 55 push %rbp - 401748: 53 push %rbx - 401749: 48 89 f5 mov %rsi,%rbp - 40174c: 48 89 fb mov %rdi,%rbx - 40174f: 41 89 d4 mov %edx,%r12d - 401752: be d0 0f 4a 00 mov $0x4a0fd0,%esi - 401757: ba 05 00 00 00 mov $0x5,%edx - 40175c: bf 5c 26 4b 00 mov $0x4b265c,%edi - 401761: 48 83 ec 08 sub $0x8,%rsp - 401765: e8 16 00 00 00 callq 401780 <__dcgettext> - 40176a: 4d 89 e8 mov %r13,%r8 - 40176d: 44 89 e1 mov %r12d,%ecx - 401770: 48 89 ea mov %rbp,%rdx - 401773: 48 89 de mov %rbx,%rsi - 401776: 48 89 c7 mov %rax,%rdi - 401779: e8 82 fe ff ff callq 401600 <__assert_fail_base> - 40177e: 66 90 xchg %ax,%ax - -0000000000401780 <__dcgettext>: - 401780: 41 89 d1 mov %edx,%r9d - 401783: 45 31 c0 xor %r8d,%r8d - 401786: 31 c9 xor %ecx,%ecx - 401788: 31 d2 xor %edx,%edx - 40178a: e9 e1 13 00 00 jmpq 402b70 <__dcigettext> - 40178f: 90 nop - -0000000000401790 : - 401790: 55 push %rbp - 401791: 53 push %rbx - 401792: 48 89 fd mov %rdi,%rbp - 401795: 48 89 f3 mov %rsi,%rbx - 401798: 48 83 ec 08 sub $0x8,%rsp - 40179c: 48 83 7e 20 00 cmpq $0x0,0x20(%rsi) - 4017a1: 74 5d je 401800 - 4017a3: 48 8d 76 38 lea 0x38(%rsi),%rsi - 4017a7: 48 83 7d 20 00 cmpq $0x0,0x20(%rbp) - 4017ac: 74 42 je 4017f0 - 4017ae: 48 8d 7d 38 lea 0x38(%rbp),%rdi - 4017b2: e8 a9 eb ff ff callq 400360 <__rela_iplt_end+0x98> - 4017b7: 85 c0 test %eax,%eax - 4017b9: 75 27 jne 4017e2 - 4017bb: 48 8b 33 mov (%rbx),%rsi - 4017be: 48 8b 7d 00 mov 0x0(%rbp),%rdi - 4017c2: e8 99 eb ff ff callq 400360 <__rela_iplt_end+0x98> - 4017c7: 85 c0 test %eax,%eax - 4017c9: 75 17 jne 4017e2 - 4017cb: 48 8b 73 10 mov 0x10(%rbx),%rsi - 4017cf: 48 8b 7d 10 mov 0x10(%rbp),%rdi - 4017d3: e8 88 eb ff ff callq 400360 <__rela_iplt_end+0x98> - 4017d8: 85 c0 test %eax,%eax - 4017da: 75 06 jne 4017e2 - 4017dc: 8b 45 08 mov 0x8(%rbp),%eax - 4017df: 2b 43 08 sub 0x8(%rbx),%eax - 4017e2: 48 83 c4 08 add $0x8,%rsp - 4017e6: 5b pop %rbx - 4017e7: 5d pop %rbp - 4017e8: c3 retq - 4017e9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4017f0: 48 8b 7d 38 mov 0x38(%rbp),%rdi - 4017f4: eb bc jmp 4017b2 - 4017f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4017fd: 00 00 00 - 401800: 48 8b 76 38 mov 0x38(%rsi),%rsi - 401804: eb a1 jmp 4017a7 - 401806: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 40180d: 00 00 00 - -0000000000401810 : - 401810: 41 57 push %r15 - 401812: 41 56 push %r14 - 401814: 41 55 push %r13 - 401816: 41 54 push %r12 - 401818: 49 89 f4 mov %rsi,%r12 - 40181b: 55 push %rbp - 40181c: 53 push %rbx - 40181d: 48 89 fb mov %rdi,%rbx - 401820: 48 83 ec 08 sub $0x8,%rsp - 401824: 8b 03 mov (%rbx),%eax - 401826: 83 f8 01 cmp $0x1,%eax - 401829: 0f 84 f9 00 00 00 je 401928 - 40182f: 0f 8e d3 00 00 00 jle 401908 - 401835: 83 f8 02 cmp $0x2,%eax - 401838: 74 56 je 401890 - 40183a: 83 f8 03 cmp $0x3,%eax - 40183d: 0f 85 ad 00 00 00 jne 4018f0 - 401843: 4c 8b 6b 08 mov 0x8(%rbx),%r13 - 401847: 41 8b 6d 00 mov 0x0(%r13),%ebp - 40184b: 83 fd 01 cmp $0x1,%ebp - 40184e: 0f 84 2c 02 00 00 je 401a80 - 401854: 0f 8e 16 01 00 00 jle 401970 - 40185a: 83 fd 02 cmp $0x2,%ebp - 40185d: 0f 84 45 02 00 00 je 401aa8 - 401863: 83 fd 03 cmp $0x3,%ebp - 401866: 0f 85 74 01 00 00 jne 4019e0 - 40186c: 49 8b 7d 08 mov 0x8(%r13),%rdi - 401870: 4c 89 e6 mov %r12,%rsi - 401873: e8 98 ff ff ff callq 401810 - 401878: 48 83 f8 01 cmp $0x1,%rax - 40187c: 19 c0 sbb %eax,%eax - 40187e: f7 d0 not %eax - 401880: 83 c0 02 add $0x2,%eax - 401883: 48 98 cltq - 401885: 4d 8b 6c c5 08 mov 0x8(%r13,%rax,8),%r13 - 40188a: eb bb jmp 401847 - 40188c: 0f 1f 40 00 nopl 0x0(%rax) - 401890: 48 8b 6b 08 mov 0x8(%rbx),%rbp - 401894: 8b 45 00 mov 0x0(%rbp),%eax - 401897: 83 f8 01 cmp $0x1,%eax - 40189a: 0f 84 b8 02 00 00 je 401b58 - 4018a0: 0f 8e ea 00 00 00 jle 401990 - 4018a6: 83 f8 02 cmp $0x2,%eax - 4018a9: 0f 84 41 02 00 00 je 401af0 - 4018af: 83 f8 03 cmp $0x3,%eax - 4018b2: 75 24 jne 4018d8 - 4018b4: 48 8b 7d 08 mov 0x8(%rbp),%rdi - 4018b8: 4c 89 e6 mov %r12,%rsi - 4018bb: e8 50 ff ff ff callq 401810 - 4018c0: 48 83 f8 01 cmp $0x1,%rax - 4018c4: 19 c0 sbb %eax,%eax - 4018c6: f7 d0 not %eax - 4018c8: 83 c0 02 add $0x2,%eax - 4018cb: 48 98 cltq - 4018cd: 48 8b 6c c5 08 mov 0x8(%rbp,%rax,8),%rbp - 4018d2: eb c0 jmp 401894 - 4018d4: 0f 1f 40 00 nopl 0x0(%rax) - 4018d8: 8b 43 04 mov 0x4(%rbx),%eax - 4018db: 83 f8 0f cmp $0xf,%eax - 4018de: 0f 84 a8 02 00 00 je 401b8c - 4018e4: 45 31 ed xor %r13d,%r13d - 4018e7: 83 f8 0e cmp $0xe,%eax - 4018ea: 0f 85 08 01 00 00 jne 4019f8 - 4018f0: 31 c9 xor %ecx,%ecx - 4018f2: 48 83 c4 08 add $0x8,%rsp - 4018f6: 48 89 c8 mov %rcx,%rax - 4018f9: 5b pop %rbx - 4018fa: 5d pop %rbp - 4018fb: 41 5c pop %r12 - 4018fd: 41 5d pop %r13 - 4018ff: 41 5e pop %r14 - 401901: 41 5f pop %r15 - 401903: c3 retq - 401904: 0f 1f 40 00 nopl 0x0(%rax) - 401908: 85 c0 test %eax,%eax - 40190a: 75 e4 jne 4018f0 - 40190c: 8b 43 04 mov 0x4(%rbx),%eax - 40190f: 4c 89 e1 mov %r12,%rcx - 401912: 85 c0 test %eax,%eax - 401914: 74 dc je 4018f2 - 401916: 83 f8 01 cmp $0x1,%eax - 401919: 75 d5 jne 4018f0 - 40191b: 48 8b 4b 08 mov 0x8(%rbx),%rcx - 40191f: eb d1 jmp 4018f2 - 401921: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 401928: 48 8b 5b 08 mov 0x8(%rbx),%rbx - 40192c: 8b 03 mov (%rbx),%eax - 40192e: 83 f8 01 cmp $0x1,%eax - 401931: 0f 84 01 02 00 00 je 401b38 - 401937: 7e 7f jle 4019b8 - 401939: 83 f8 02 cmp $0x2,%eax - 40193c: 0f 84 ee 00 00 00 je 401a30 - 401942: 83 f8 03 cmp $0x3,%eax - 401945: 0f 85 d5 00 00 00 jne 401a20 - 40194b: 48 8b 7b 08 mov 0x8(%rbx),%rdi - 40194f: 4c 89 e6 mov %r12,%rsi - 401952: e8 b9 fe ff ff callq 401810 - 401957: 48 83 f8 01 cmp $0x1,%rax - 40195b: 19 c0 sbb %eax,%eax - 40195d: f7 d0 not %eax - 40195f: 83 c0 02 add $0x2,%eax - 401962: 48 98 cltq - 401964: 48 8b 5c c3 08 mov 0x8(%rbx,%rax,8),%rbx - 401969: eb c1 jmp 40192c - 40196b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 401970: 85 ed test %ebp,%ebp - 401972: 75 6c jne 4019e0 - 401974: 41 8b 45 04 mov 0x4(%r13),%eax - 401978: 85 c0 test %eax,%eax - 40197a: 0f 84 30 02 00 00 je 401bb0 - 401980: 83 f8 01 cmp $0x1,%eax - 401983: 75 5b jne 4019e0 - 401985: 49 8b 4d 08 mov 0x8(%r13),%rcx - 401989: e9 06 01 00 00 jmpq 401a94 - 40198e: 66 90 xchg %ax,%ax - 401990: 85 c0 test %eax,%eax - 401992: 0f 85 40 ff ff ff jne 4018d8 - 401998: 8b 45 04 mov 0x4(%rbp),%eax - 40199b: 85 c0 test %eax,%eax - 40199d: 0f 84 05 02 00 00 je 401ba8 - 4019a3: 83 f8 01 cmp $0x1,%eax - 4019a6: 0f 85 2c ff ff ff jne 4018d8 - 4019ac: 4c 8b 6d 08 mov 0x8(%rbp),%r13 - 4019b0: e9 b9 01 00 00 jmpq 401b6e - 4019b5: 0f 1f 00 nopl (%rax) - 4019b8: 85 c0 test %eax,%eax - 4019ba: 75 64 jne 401a20 - 4019bc: 8b 43 04 mov 0x4(%rbx),%eax - 4019bf: 85 c0 test %eax,%eax - 4019c1: 0f 84 d1 01 00 00 je 401b98 - 4019c7: 83 f8 01 cmp $0x1,%eax - 4019ca: 75 54 jne 401a20 - 4019cc: 31 c9 xor %ecx,%ecx - 4019ce: 48 83 7b 08 00 cmpq $0x0,0x8(%rbx) - 4019d3: 0f 94 c1 sete %cl - 4019d6: e9 17 ff ff ff jmpq 4018f2 - 4019db: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4019e0: bd 02 00 00 00 mov $0x2,%ebp - 4019e5: 48 63 ed movslq %ebp,%rbp - 4019e8: 48 8b 5c eb 08 mov 0x8(%rbx,%rbp,8),%rbx - 4019ed: e9 32 fe ff ff jmpq 401824 - 4019f2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4019f8: 48 8b 7b 10 mov 0x10(%rbx),%rdi - 4019fc: 4c 89 e6 mov %r12,%rsi - 4019ff: e8 0c fe ff ff callq 401810 - 401a04: 8b 4b 04 mov 0x4(%rbx),%ecx - 401a07: 48 89 c5 mov %rax,%rbp - 401a0a: 83 e9 03 sub $0x3,%ecx - 401a0d: 83 f9 0a cmp $0xa,%ecx - 401a10: 0f 87 da fe ff ff ja 4018f0 - 401a16: ff 24 cd 18 10 4a 00 jmpq *0x4a1018(,%rcx,8) - 401a1d: 0f 1f 00 nopl (%rax) - 401a20: b9 01 00 00 00 mov $0x1,%ecx - 401a25: e9 c8 fe ff ff jmpq 4018f2 - 401a2a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 401a30: 48 8b 7b 08 mov 0x8(%rbx),%rdi - 401a34: 4c 89 e6 mov %r12,%rsi - 401a37: e8 d4 fd ff ff callq 401810 - 401a3c: 8b 4b 04 mov 0x4(%rbx),%ecx - 401a3f: 48 89 c5 mov %rax,%rbp - 401a42: 83 f9 0f cmp $0xf,%ecx - 401a45: 0f 84 85 01 00 00 je 401bd0 - 401a4b: 83 f9 0e cmp $0xe,%ecx - 401a4e: 0f 85 1c 04 00 00 jne 401e70 - 401a54: 48 85 c0 test %rax,%rax - 401a57: b9 01 00 00 00 mov $0x1,%ecx - 401a5c: 0f 84 90 fe ff ff je 4018f2 - 401a62: 48 8b 7b 10 mov 0x10(%rbx),%rdi - 401a66: 4c 89 e6 mov %r12,%rsi - 401a69: e8 a2 fd ff ff callq 401810 - 401a6e: 31 c9 xor %ecx,%ecx - 401a70: 48 85 c0 test %rax,%rax - 401a73: 0f 94 c1 sete %cl - 401a76: e9 77 fe ff ff jmpq 4018f2 - 401a7b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 401a80: 49 8b 7d 08 mov 0x8(%r13),%rdi - 401a84: 4c 89 e6 mov %r12,%rsi - 401a87: e8 84 fd ff ff callq 401810 - 401a8c: 31 c9 xor %ecx,%ecx - 401a8e: 48 85 c0 test %rax,%rax - 401a91: 0f 94 c1 sete %cl - 401a94: 48 83 f9 01 cmp $0x1,%rcx - 401a98: 19 ed sbb %ebp,%ebp - 401a9a: f7 d5 not %ebp - 401a9c: 83 c5 02 add $0x2,%ebp - 401a9f: e9 41 ff ff ff jmpq 4019e5 - 401aa4: 0f 1f 40 00 nopl 0x0(%rax) - 401aa8: 49 8b 7d 08 mov 0x8(%r13),%rdi - 401aac: 4c 89 e6 mov %r12,%rsi - 401aaf: e8 5c fd ff ff callq 401810 - 401ab4: 49 89 c6 mov %rax,%r14 - 401ab7: 41 8b 45 04 mov 0x4(%r13),%eax - 401abb: 83 f8 0f cmp $0xf,%eax - 401abe: 0f 84 1c 01 00 00 je 401be0 - 401ac4: 83 f8 0e cmp $0xe,%eax - 401ac7: 0f 85 eb 01 00 00 jne 401cb8 - 401acd: 4d 85 f6 test %r14,%r14 - 401ad0: 0f 84 0f ff ff ff je 4019e5 - 401ad6: 49 8b 7d 10 mov 0x10(%r13),%rdi - 401ada: 4c 89 e6 mov %r12,%rsi - 401add: e8 2e fd ff ff callq 401810 - 401ae2: 31 c9 xor %ecx,%ecx - 401ae4: 48 85 c0 test %rax,%rax - 401ae7: 0f 95 c1 setne %cl - 401aea: eb a8 jmp 401a94 - 401aec: 0f 1f 40 00 nopl 0x0(%rax) - 401af0: 48 8b 7d 08 mov 0x8(%rbp),%rdi - 401af4: 4c 89 e6 mov %r12,%rsi - 401af7: e8 14 fd ff ff callq 401810 - 401afc: 8b 4d 04 mov 0x4(%rbp),%ecx - 401aff: 49 89 c6 mov %rax,%r14 - 401b02: 83 f9 0f cmp $0xf,%ecx - 401b05: 0f 84 b5 00 00 00 je 401bc0 - 401b0b: 83 f9 0e cmp $0xe,%ecx - 401b0e: 0f 85 7c 02 00 00 jne 401d90 - 401b14: 45 31 ed xor %r13d,%r13d - 401b17: 48 85 c0 test %rax,%rax - 401b1a: 74 52 je 401b6e - 401b1c: 48 8b 7d 10 mov 0x10(%rbp),%rdi - 401b20: 4c 89 e6 mov %r12,%rsi - 401b23: 45 31 ed xor %r13d,%r13d - 401b26: e8 e5 fc ff ff callq 401810 - 401b2b: 48 85 c0 test %rax,%rax - 401b2e: 41 0f 95 c5 setne %r13b - 401b32: eb 3a jmp 401b6e - 401b34: 0f 1f 40 00 nopl 0x0(%rax) - 401b38: 48 8b 7b 08 mov 0x8(%rbx),%rdi - 401b3c: 4c 89 e6 mov %r12,%rsi - 401b3f: e8 cc fc ff ff callq 401810 - 401b44: 31 c9 xor %ecx,%ecx - 401b46: 48 85 c0 test %rax,%rax - 401b49: 0f 95 c1 setne %cl - 401b4c: e9 a1 fd ff ff jmpq 4018f2 - 401b51: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 401b58: 48 8b 7d 08 mov 0x8(%rbp),%rdi - 401b5c: 4c 89 e6 mov %r12,%rsi - 401b5f: 45 31 ed xor %r13d,%r13d - 401b62: e8 a9 fc ff ff callq 401810 - 401b67: 48 85 c0 test %rax,%rax - 401b6a: 41 0f 94 c5 sete %r13b - 401b6e: 8b 4b 04 mov 0x4(%rbx),%ecx - 401b71: 83 f9 0f cmp $0xf,%ecx - 401b74: 0f 84 26 01 00 00 je 401ca0 - 401b7a: 83 f9 0e cmp $0xe,%ecx - 401b7d: 0f 85 75 fe ff ff jne 4019f8 - 401b83: 4d 85 ed test %r13,%r13 - 401b86: 0f 84 64 fd ff ff je 4018f0 - 401b8c: 48 8b 7b 10 mov 0x10(%rbx),%rdi - 401b90: eb aa jmp 401b3c - 401b92: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 401b98: 31 c9 xor %ecx,%ecx - 401b9a: 4d 85 e4 test %r12,%r12 - 401b9d: 0f 94 c1 sete %cl - 401ba0: e9 4d fd ff ff jmpq 4018f2 - 401ba5: 0f 1f 00 nopl (%rax) - 401ba8: 4d 89 e5 mov %r12,%r13 - 401bab: eb c1 jmp 401b6e - 401bad: 0f 1f 00 nopl (%rax) - 401bb0: 4c 89 e1 mov %r12,%rcx - 401bb3: e9 dc fe ff ff jmpq 401a94 - 401bb8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 401bbf: 00 - 401bc0: 48 85 c0 test %rax,%rax - 401bc3: 41 bd 01 00 00 00 mov $0x1,%r13d - 401bc9: 75 a3 jne 401b6e - 401bcb: e9 4c ff ff ff jmpq 401b1c - 401bd0: 31 c9 xor %ecx,%ecx - 401bd2: 48 85 c0 test %rax,%rax - 401bd5: 0f 85 17 fd ff ff jne 4018f2 - 401bdb: e9 82 fe ff ff jmpq 401a62 - 401be0: 4d 85 f6 test %r14,%r14 - 401be3: bd 01 00 00 00 mov $0x1,%ebp - 401be8: 0f 85 f7 fd ff ff jne 4019e5 - 401bee: e9 e3 fe ff ff jmpq 401ad6 - 401bf3: 31 c9 xor %ecx,%ecx - 401bf5: 4c 39 e8 cmp %r13,%rax - 401bf8: 0f 95 c1 setne %cl - 401bfb: e9 f2 fc ff ff jmpq 4018f2 - 401c00: 31 c9 xor %ecx,%ecx - 401c02: 4c 39 e8 cmp %r13,%rax - 401c05: 0f 94 c1 sete %cl - 401c08: e9 e5 fc ff ff jmpq 4018f2 - 401c0d: 31 c9 xor %ecx,%ecx - 401c0f: 4c 39 e8 cmp %r13,%rax - 401c12: 0f 96 c1 setbe %cl - 401c15: e9 d8 fc ff ff jmpq 4018f2 - 401c1a: 31 c9 xor %ecx,%ecx - 401c1c: 4c 39 e8 cmp %r13,%rax - 401c1f: 0f 93 c1 setae %cl - 401c22: e9 cb fc ff ff jmpq 4018f2 - 401c27: 31 c9 xor %ecx,%ecx - 401c29: 4c 39 e8 cmp %r13,%rax - 401c2c: 0f 92 c1 setb %cl - 401c2f: e9 be fc ff ff jmpq 4018f2 - 401c34: 31 c9 xor %ecx,%ecx - 401c36: 4c 39 e8 cmp %r13,%rax - 401c39: 0f 97 c1 seta %cl - 401c3c: e9 b1 fc ff ff jmpq 4018f2 - 401c41: 4c 89 e9 mov %r13,%rcx - 401c44: 48 29 c1 sub %rax,%rcx - 401c47: e9 a6 fc ff ff jmpq 4018f2 - 401c4c: 4a 8d 0c 28 lea (%rax,%r13,1),%rcx - 401c50: e9 9d fc ff ff jmpq 4018f2 - 401c55: 48 85 c0 test %rax,%rax - 401c58: 75 0a jne 401c64 - 401c5a: bf 08 00 00 00 mov $0x8,%edi - 401c5f: e8 1c bf 00 00 callq 40db80 - 401c64: 4c 89 e8 mov %r13,%rax - 401c67: 31 d2 xor %edx,%edx - 401c69: 48 f7 f5 div %rbp - 401c6c: 48 89 d1 mov %rdx,%rcx - 401c6f: e9 7e fc ff ff jmpq 4018f2 - 401c74: 48 85 c0 test %rax,%rax - 401c77: 75 0a jne 401c83 - 401c79: bf 08 00 00 00 mov $0x8,%edi - 401c7e: e8 fd be 00 00 callq 40db80 - 401c83: 4c 89 e8 mov %r13,%rax - 401c86: 31 d2 xor %edx,%edx - 401c88: 48 f7 f5 div %rbp - 401c8b: 48 89 c1 mov %rax,%rcx - 401c8e: e9 5f fc ff ff jmpq 4018f2 - 401c93: 48 89 c1 mov %rax,%rcx - 401c96: 49 0f af cd imul %r13,%rcx - 401c9a: e9 53 fc ff ff jmpq 4018f2 - 401c9f: 90 nop - 401ca0: 4d 85 ed test %r13,%r13 - 401ca3: b9 01 00 00 00 mov $0x1,%ecx - 401ca8: 0f 85 44 fc ff ff jne 4018f2 - 401cae: e9 d9 fe ff ff jmpq 401b8c - 401cb3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 401cb8: 49 8b 7d 10 mov 0x10(%r13),%rdi - 401cbc: 4c 89 e6 mov %r12,%rsi - 401cbf: e8 4c fb ff ff callq 401810 - 401cc4: 48 89 c5 mov %rax,%rbp - 401cc7: 41 8b 45 04 mov 0x4(%r13),%eax - 401ccb: 83 e8 03 sub $0x3,%eax - 401cce: 83 f8 0a cmp $0xa,%eax - 401cd1: 0f 87 09 fd ff ff ja 4019e0 - 401cd7: ff 24 c5 70 10 4a 00 jmpq *0x4a1070(,%rax,8) - 401cde: 31 c9 xor %ecx,%ecx - 401ce0: 49 39 ee cmp %rbp,%r14 - 401ce3: 0f 94 c1 sete %cl - 401ce6: e9 a9 fd ff ff jmpq 401a94 - 401ceb: 31 c9 xor %ecx,%ecx - 401ced: 49 39 ee cmp %rbp,%r14 - 401cf0: 0f 93 c1 setae %cl - 401cf3: e9 9c fd ff ff jmpq 401a94 - 401cf8: 31 c9 xor %ecx,%ecx - 401cfa: 49 39 ee cmp %rbp,%r14 - 401cfd: 0f 96 c1 setbe %cl - 401d00: e9 8f fd ff ff jmpq 401a94 - 401d05: 31 c9 xor %ecx,%ecx - 401d07: 49 39 ee cmp %rbp,%r14 - 401d0a: 0f 97 c1 seta %cl - 401d0d: e9 82 fd ff ff jmpq 401a94 - 401d12: 31 c9 xor %ecx,%ecx - 401d14: 49 39 ee cmp %rbp,%r14 - 401d17: 0f 92 c1 setb %cl - 401d1a: e9 75 fd ff ff jmpq 401a94 - 401d1f: 4c 89 f1 mov %r14,%rcx - 401d22: 48 29 e9 sub %rbp,%rcx - 401d25: e9 6a fd ff ff jmpq 401a94 - 401d2a: 49 8d 0c 2e lea (%r14,%rbp,1),%rcx - 401d2e: e9 61 fd ff ff jmpq 401a94 - 401d33: 48 85 ed test %rbp,%rbp - 401d36: 75 0a jne 401d42 - 401d38: bf 08 00 00 00 mov $0x8,%edi - 401d3d: e8 3e be 00 00 callq 40db80 - 401d42: 4c 89 f0 mov %r14,%rax - 401d45: 31 d2 xor %edx,%edx - 401d47: 48 f7 f5 div %rbp - 401d4a: 48 89 d1 mov %rdx,%rcx - 401d4d: e9 42 fd ff ff jmpq 401a94 - 401d52: 48 85 ed test %rbp,%rbp - 401d55: 75 0a jne 401d61 - 401d57: bf 08 00 00 00 mov $0x8,%edi - 401d5c: e8 1f be 00 00 callq 40db80 - 401d61: 4c 89 f0 mov %r14,%rax - 401d64: 31 d2 xor %edx,%edx - 401d66: 48 f7 f5 div %rbp - 401d69: 48 89 c1 mov %rax,%rcx - 401d6c: e9 23 fd ff ff jmpq 401a94 - 401d71: 4c 89 f1 mov %r14,%rcx - 401d74: 48 0f af cd imul %rbp,%rcx - 401d78: e9 17 fd ff ff jmpq 401a94 - 401d7d: 31 c9 xor %ecx,%ecx - 401d7f: 49 39 ee cmp %rbp,%r14 - 401d82: 0f 95 c1 setne %cl - 401d85: e9 0a fd ff ff jmpq 401a94 - 401d8a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 401d90: 48 8b 7d 10 mov 0x10(%rbp),%rdi - 401d94: 4c 89 e6 mov %r12,%rsi - 401d97: e8 74 fa ff ff callq 401810 - 401d9c: 8b 4d 04 mov 0x4(%rbp),%ecx - 401d9f: 49 89 c7 mov %rax,%r15 - 401da2: 83 e9 03 sub $0x3,%ecx - 401da5: 83 f9 0a cmp $0xa,%ecx - 401da8: 0f 87 2a fb ff ff ja 4018d8 - 401dae: ff 24 cd c8 10 4a 00 jmpq *0x4a10c8(,%rcx,8) - 401db5: 45 31 ed xor %r13d,%r13d - 401db8: 49 39 c6 cmp %rax,%r14 - 401dbb: 41 0f 94 c5 sete %r13b - 401dbf: e9 aa fd ff ff jmpq 401b6e - 401dc4: 45 31 ed xor %r13d,%r13d - 401dc7: 49 39 c6 cmp %rax,%r14 - 401dca: 41 0f 93 c5 setae %r13b - 401dce: e9 9b fd ff ff jmpq 401b6e - 401dd3: 45 31 ed xor %r13d,%r13d - 401dd6: 49 39 c6 cmp %rax,%r14 - 401dd9: 41 0f 96 c5 setbe %r13b - 401ddd: e9 8c fd ff ff jmpq 401b6e - 401de2: 45 31 ed xor %r13d,%r13d - 401de5: 49 39 c6 cmp %rax,%r14 - 401de8: 41 0f 97 c5 seta %r13b - 401dec: e9 7d fd ff ff jmpq 401b6e - 401df1: 45 31 ed xor %r13d,%r13d - 401df4: 49 39 c6 cmp %rax,%r14 - 401df7: 41 0f 92 c5 setb %r13b - 401dfb: e9 6e fd ff ff jmpq 401b6e - 401e00: 49 29 c6 sub %rax,%r14 - 401e03: 4d 89 f5 mov %r14,%r13 - 401e06: e9 63 fd ff ff jmpq 401b6e - 401e0b: 4d 8d 2c 06 lea (%r14,%rax,1),%r13 - 401e0f: e9 5a fd ff ff jmpq 401b6e - 401e14: 48 85 c0 test %rax,%rax - 401e17: 75 0a jne 401e23 - 401e19: bf 08 00 00 00 mov $0x8,%edi - 401e1e: e8 5d bd 00 00 callq 40db80 - 401e23: 4c 89 f0 mov %r14,%rax - 401e26: 31 d2 xor %edx,%edx - 401e28: 49 f7 f7 div %r15 - 401e2b: 49 89 d5 mov %rdx,%r13 - 401e2e: e9 3b fd ff ff jmpq 401b6e - 401e33: 48 85 c0 test %rax,%rax - 401e36: 75 0a jne 401e42 - 401e38: bf 08 00 00 00 mov $0x8,%edi - 401e3d: e8 3e bd 00 00 callq 40db80 - 401e42: 4c 89 f0 mov %r14,%rax - 401e45: 31 d2 xor %edx,%edx - 401e47: 49 f7 f7 div %r15 - 401e4a: 49 89 c5 mov %rax,%r13 - 401e4d: e9 1c fd ff ff jmpq 401b6e - 401e52: 4c 0f af f0 imul %rax,%r14 - 401e56: 4d 89 f5 mov %r14,%r13 - 401e59: e9 10 fd ff ff jmpq 401b6e - 401e5e: 45 31 ed xor %r13d,%r13d - 401e61: 49 39 c6 cmp %rax,%r14 - 401e64: 41 0f 95 c5 setne %r13b - 401e68: e9 01 fd ff ff jmpq 401b6e - 401e6d: 0f 1f 00 nopl (%rax) - 401e70: 48 8b 7b 10 mov 0x10(%rbx),%rdi - 401e74: 4c 89 e6 mov %r12,%rsi - 401e77: e8 94 f9 ff ff callq 401810 - 401e7c: 8b 4b 04 mov 0x4(%rbx),%ecx - 401e7f: 49 89 c4 mov %rax,%r12 - 401e82: 83 e9 03 sub $0x3,%ecx - 401e85: 83 f9 0a cmp $0xa,%ecx - 401e88: 0f 87 92 fb ff ff ja 401a20 - 401e8e: ff 24 cd 20 11 4a 00 jmpq *0x4a1120(,%rcx,8) - 401e95: 31 c9 xor %ecx,%ecx - 401e97: 48 39 c5 cmp %rax,%rbp - 401e9a: 0f 94 c1 sete %cl - 401e9d: e9 50 fa ff ff jmpq 4018f2 - 401ea2: 31 c9 xor %ecx,%ecx - 401ea4: 48 39 c5 cmp %rax,%rbp - 401ea7: 0f 92 c1 setb %cl - 401eaa: e9 43 fa ff ff jmpq 4018f2 - 401eaf: 31 c9 xor %ecx,%ecx - 401eb1: 48 39 c5 cmp %rax,%rbp - 401eb4: 0f 97 c1 seta %cl - 401eb7: e9 36 fa ff ff jmpq 4018f2 - 401ebc: 31 c9 xor %ecx,%ecx - 401ebe: 48 39 c5 cmp %rax,%rbp - 401ec1: 0f 96 c1 setbe %cl - 401ec4: e9 29 fa ff ff jmpq 4018f2 - 401ec9: 31 c9 xor %ecx,%ecx - 401ecb: 48 39 c5 cmp %rax,%rbp - 401ece: 0f 93 c1 setae %cl - 401ed1: e9 1c fa ff ff jmpq 4018f2 - 401ed6: 31 c9 xor %ecx,%ecx - 401ed8: 48 39 c5 cmp %rax,%rbp - 401edb: 0f 95 c1 setne %cl - 401ede: e9 0f fa ff ff jmpq 4018f2 - 401ee3: 31 c9 xor %ecx,%ecx - 401ee5: 48 01 c5 add %rax,%rbp - 401ee8: 0f 94 c1 sete %cl - 401eeb: e9 02 fa ff ff jmpq 4018f2 - 401ef0: 48 85 c0 test %rax,%rax - 401ef3: 75 0a jne 401eff - 401ef5: bf 08 00 00 00 mov $0x8,%edi - 401efa: e8 81 bc 00 00 callq 40db80 - 401eff: 31 d2 xor %edx,%edx - 401f01: 48 89 e8 mov %rbp,%rax - 401f04: 31 c9 xor %ecx,%ecx - 401f06: 49 f7 f4 div %r12 - 401f09: 48 85 d2 test %rdx,%rdx - 401f0c: 0f 94 c1 sete %cl - 401f0f: e9 de f9 ff ff jmpq 4018f2 - 401f14: 48 85 c0 test %rax,%rax - 401f17: 75 0a jne 401f23 - 401f19: bf 08 00 00 00 mov $0x8,%edi - 401f1e: e8 5d bc 00 00 callq 40db80 - 401f23: 31 d2 xor %edx,%edx - 401f25: 48 89 e8 mov %rbp,%rax - 401f28: 31 c9 xor %ecx,%ecx - 401f2a: 49 f7 f4 div %r12 - 401f2d: 48 85 c0 test %rax,%rax - 401f30: 0f 94 c1 sete %cl - 401f33: e9 ba f9 ff ff jmpq 4018f2 - 401f38: 48 0f af e8 imul %rax,%rbp - 401f3c: 31 c9 xor %ecx,%ecx - 401f3e: 48 85 ed test %rbp,%rbp - 401f41: 0f 94 c1 sete %cl - 401f44: e9 a9 f9 ff ff jmpq 4018f2 - 401f49: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - -0000000000401f50 <_nl_find_msg>: - 401f50: 55 push %rbp - 401f51: 48 89 f8 mov %rdi,%rax - 401f54: 48 89 e5 mov %rsp,%rbp - 401f57: 41 57 push %r15 - 401f59: 41 56 push %r14 - 401f5b: 41 55 push %r13 - 401f5d: 41 54 push %r12 - 401f5f: 53 push %rbx - 401f60: 48 81 ec 88 00 00 00 sub $0x88,%rsp - 401f67: 4c 89 85 60 ff ff ff mov %r8,-0xa0(%rbp) - 401f6e: 44 8b 47 08 mov 0x8(%rdi),%r8d - 401f72: 48 89 bd 70 ff ff ff mov %rdi,-0x90(%rbp) - 401f79: 48 89 b5 58 ff ff ff mov %rsi,-0xa8(%rbp) - 401f80: 48 89 55 a0 mov %rdx,-0x60(%rbp) - 401f84: 89 8d 68 ff ff ff mov %ecx,-0x98(%rbp) - 401f8a: 45 85 c0 test %r8d,%r8d - 401f8d: 0f 8e dd 03 00 00 jle 402370 <_nl_find_msg+0x420> - 401f93: 48 8b 58 10 mov 0x10(%rax),%rbx - 401f97: 48 85 db test %rbx,%rbx - 401f9a: 0f 84 0c 01 00 00 je 4020ac <_nl_find_msg+0x15c> - 401fa0: 48 83 7b 60 00 cmpq $0x0,0x60(%rbx) - 401fa5: 8b 43 28 mov 0x28(%rbx),%eax - 401fa8: 89 45 a8 mov %eax,-0x58(%rbp) - 401fab: 0f 84 9f 02 00 00 je 402250 <_nl_find_msg+0x300> - 401fb1: 4c 8b 75 a0 mov -0x60(%rbp),%r14 - 401fb5: 4c 89 f7 mov %r14,%rdi - 401fb8: e8 93 16 02 00 callq 423650 - 401fbd: 4c 89 f7 mov %r14,%rdi - 401fc0: 49 89 c7 mov %rax,%r15 - 401fc3: 89 85 78 ff ff ff mov %eax,-0x88(%rbp) - 401fc9: e8 62 bb 00 00 callq 40db30 <__hash_string> - 401fce: 8b 7b 58 mov 0x58(%rbx),%edi - 401fd1: 31 d2 xor %edx,%edx - 401fd3: 89 c6 mov %eax,%esi - 401fd5: 44 8b 73 68 mov 0x68(%rbx),%r14d - 401fd9: f7 f7 div %edi - 401fdb: 44 8d 47 fe lea -0x2(%rdi),%r8d - 401fdf: 89 f0 mov %esi,%eax - 401fe1: 41 89 d5 mov %edx,%r13d - 401fe4: 31 d2 xor %edx,%edx - 401fe6: 41 f7 f0 div %r8d - 401fe9: 48 8b 43 60 mov 0x60(%rbx),%rax - 401fed: 48 89 45 98 mov %rax,-0x68(%rbp) - 401ff1: 44 89 f8 mov %r15d,%eax - 401ff4: 41 89 ff mov %edi,%r15d - 401ff7: 48 89 45 80 mov %rax,-0x80(%rbp) - 401ffb: 44 8d 62 01 lea 0x1(%rdx),%r12d - 401fff: 44 89 e0 mov %r12d,%eax - 402002: 45 29 e7 sub %r12d,%r15d - 402005: 29 f8 sub %edi,%eax - 402007: 89 45 90 mov %eax,-0x70(%rbp) - 40200a: 44 89 f8 mov %r15d,%eax - 40200d: 45 89 e7 mov %r12d,%r15d - 402010: 49 89 dc mov %rbx,%r12 - 402013: 44 89 eb mov %r13d,%ebx - 402016: 41 89 c5 mov %eax,%r13d - 402019: eb 7d jmp 402098 <_nl_find_msg+0x148> - 40201b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 402020: 48 8b 4d 98 mov -0x68(%rbp),%rcx - 402024: 44 8b 14 81 mov (%rcx,%rax,4),%r10d - 402028: 41 0f ca bswap %r10d - 40202b: 45 85 d2 test %r10d,%r10d - 40202e: 74 7c je 4020ac <_nl_find_msg+0x15c> - 402030: 41 83 ea 01 sub $0x1,%r10d - 402034: 44 39 55 a8 cmp %r10d,-0x58(%rbp) - 402038: 0f 86 82 00 00 00 jbe 4020c0 <_nl_find_msg+0x170> - 40203e: 41 8b 7c 24 18 mov 0x18(%r12),%edi - 402043: 49 8b 44 24 30 mov 0x30(%r12),%rax - 402048: 85 ff test %edi,%edi - 40204a: 0f 84 e0 01 00 00 je 402230 <_nl_find_msg+0x2e0> - 402050: 4a 8d 3c d0 lea (%rax,%r10,8),%rdi - 402054: 8b 07 mov (%rdi),%eax - 402056: 0f c8 bswap %eax - 402058: 39 85 78 ff ff ff cmp %eax,-0x88(%rbp) - 40205e: 77 27 ja 402087 <_nl_find_msg+0x137> - 402060: 8b 47 04 mov 0x4(%rdi),%eax - 402063: 49 8b 34 24 mov (%r12),%rsi - 402067: 0f c8 bswap %eax - 402069: 89 c0 mov %eax,%eax - 40206b: 48 8b 7d a0 mov -0x60(%rbp),%rdi - 40206f: 48 01 c6 add %rax,%rsi - 402072: 4c 89 55 88 mov %r10,-0x78(%rbp) - 402076: e8 e5 e2 ff ff callq 400360 <__rela_iplt_end+0x98> - 40207b: 85 c0 test %eax,%eax - 40207d: 4c 8b 55 88 mov -0x78(%rbp),%r10 - 402081: 0f 84 8a 0a 00 00 je 402b11 <_nl_find_msg+0xbc1> - 402087: 8b 45 90 mov -0x70(%rbp),%eax - 40208a: 42 8d 34 3b lea (%rbx,%r15,1),%esi - 40208e: 01 d8 add %ebx,%eax - 402090: 44 39 eb cmp %r13d,%ebx - 402093: 0f 42 c6 cmovb %esi,%eax - 402096: 89 c3 mov %eax,%ebx - 402098: 45 85 f6 test %r14d,%r14d - 40209b: 89 d8 mov %ebx,%eax - 40209d: 75 81 jne 402020 <_nl_find_msg+0xd0> - 40209f: 48 8b 55 98 mov -0x68(%rbp),%rdx - 4020a3: 44 8b 14 82 mov (%rdx,%rax,4),%r10d - 4020a7: 45 85 d2 test %r10d,%r10d - 4020aa: 75 84 jne 402030 <_nl_find_msg+0xe0> - 4020ac: 31 c0 xor %eax,%eax - 4020ae: 48 8d 65 d8 lea -0x28(%rbp),%rsp - 4020b2: 5b pop %rbx - 4020b3: 41 5c pop %r12 - 4020b5: 41 5d pop %r13 - 4020b7: 41 5e pop %r14 - 4020b9: 41 5f pop %r15 - 4020bb: 5d pop %rbp - 4020bc: c3 retq - 4020bd: 0f 1f 00 nopl (%rax) - 4020c0: 44 89 d0 mov %r10d,%eax - 4020c3: 2b 45 a8 sub -0x58(%rbp),%eax - 4020c6: 48 8b 55 80 mov -0x80(%rbp),%rdx - 4020ca: 44 89 55 88 mov %r10d,-0x78(%rbp) - 4020ce: 48 c1 e0 04 shl $0x4,%rax - 4020d2: 49 03 44 24 48 add 0x48(%r12),%rax - 4020d7: 48 3b 10 cmp (%rax),%rdx - 4020da: 73 ab jae 402087 <_nl_find_msg+0x137> - 4020dc: 48 8b 70 08 mov 0x8(%rax),%rsi - 4020e0: 48 8b 7d a0 mov -0x60(%rbp),%rdi - 4020e4: e8 77 e2 ff ff callq 400360 <__rela_iplt_end+0x98> - 4020e9: 85 c0 test %eax,%eax - 4020eb: 75 9a jne 402087 <_nl_find_msg+0x137> - 4020ed: 44 8b 55 88 mov -0x78(%rbp),%r10d - 4020f1: 4c 89 e3 mov %r12,%rbx - 4020f4: 8b 45 a8 mov -0x58(%rbp),%eax - 4020f7: 4d 89 d6 mov %r10,%r14 - 4020fa: 49 39 c6 cmp %rax,%r14 - 4020fd: 0f 83 f5 01 00 00 jae 4022f8 <_nl_find_msg+0x3a8> - 402103: 8b 4b 18 mov 0x18(%rbx),%ecx - 402106: 4c 8b 3b mov (%rbx),%r15 - 402109: 48 8b 43 38 mov 0x38(%rbx),%rax - 40210d: 85 c9 test %ecx,%ecx - 40210f: 0f 84 3b 02 00 00 je 402350 <_nl_find_msg+0x400> - 402115: 4a 8d 14 f0 lea (%rax,%r14,8),%rdx - 402119: 8b 42 04 mov 0x4(%rdx),%eax - 40211c: 0f c8 bswap %eax - 40211e: 89 c0 mov %eax,%eax - 402120: 4c 01 f8 add %r15,%rax - 402123: 48 89 45 a0 mov %rax,-0x60(%rbp) - 402127: 8b 02 mov (%rdx),%eax - 402129: 8b 95 68 ff ff ff mov -0x98(%rbp),%edx - 40212f: 0f c8 bswap %eax - 402131: 83 c0 01 add $0x1,%eax - 402134: 85 d2 test %edx,%edx - 402136: 48 89 45 98 mov %rax,-0x68(%rbp) - 40213a: 0f 84 e6 01 00 00 je 402326 <_nl_find_msg+0x3d6> - 402140: 48 8b 85 58 ff ff ff mov -0xa8(%rbp),%rax - 402147: 48 85 c0 test %rax,%rax - 40214a: 0f 84 f7 02 00 00 je 402447 <_nl_find_msg+0x4f7> - 402150: 48 8b 40 10 mov 0x10(%rax),%rax - 402154: 48 85 c0 test %rax,%rax - 402157: 48 89 45 90 mov %rax,-0x70(%rbp) - 40215b: 0f 84 e6 02 00 00 je 402447 <_nl_find_msg+0x4f7> - 402161: b8 00 00 00 00 mov $0x0,%eax - 402166: 48 85 c0 test %rax,%rax - 402169: 74 09 je 402174 <_nl_find_msg+0x224> - 40216b: 48 8d bb 80 00 00 00 lea 0x80(%rbx),%rdi - 402172: ff d0 callq *%rax - 402174: 4c 8b 6b 78 mov 0x78(%rbx),%r13 - 402178: 4d 85 ed test %r13,%r13 - 40217b: 0f 84 17 02 00 00 je 402398 <_nl_find_msg+0x448> - 402181: 48 8b 53 70 mov 0x70(%rbx),%rdx - 402185: 4b 8d 44 6d 00 lea 0x0(%r13,%r13,2),%rax - 40218a: 48 89 5d 88 mov %rbx,-0x78(%rbp) - 40218e: 4c 8b 65 90 mov -0x70(%rbp),%r12 - 402192: 4c 89 eb mov %r13,%rbx - 402195: 4c 8d 7c c2 e8 lea -0x18(%rdx,%rax,8),%r15 - 40219a: eb 11 jmp 4021ad <_nl_find_msg+0x25d> - 40219c: 0f 1f 40 00 nopl 0x0(%rax) - 4021a0: 49 83 ef 18 sub $0x18,%r15 - 4021a4: 48 85 db test %rbx,%rbx - 4021a7: 0f 84 e7 01 00 00 je 402394 <_nl_find_msg+0x444> - 4021ad: 49 8b 3f mov (%r15),%rdi - 4021b0: 4c 89 e6 mov %r12,%rsi - 4021b3: 48 83 eb 01 sub $0x1,%rbx - 4021b7: e8 a4 e1 ff ff callq 400360 <__rela_iplt_end+0x98> - 4021bc: 85 c0 test %eax,%eax - 4021be: 75 e0 jne 4021a0 <_nl_find_msg+0x250> - 4021c0: b8 00 00 00 00 mov $0x0,%eax - 4021c5: 48 8b 5d 88 mov -0x78(%rbp),%rbx - 4021c9: 4d 89 fc mov %r15,%r12 - 4021cc: 48 85 c0 test %rax,%rax - 4021cf: 48 89 45 88 mov %rax,-0x78(%rbp) - 4021d3: 74 15 je 4021ea <_nl_find_msg+0x29a> - 4021d5: 48 8d bb 80 00 00 00 lea 0x80(%rbx),%rdi - 4021dc: e8 1f de bf ff callq 0 <_nl_current_LC_CTYPE> - 4021e1: 4d 85 e4 test %r12,%r12 - 4021e4: 0f 84 c3 01 00 00 je 4023ad <_nl_find_msg+0x45d> - 4021ea: 49 83 7c 24 08 ff cmpq $0xffffffffffffffff,0x8(%r12) - 4021f0: 0f 84 30 01 00 00 je 402326 <_nl_find_msg+0x3d6> - 4021f6: 49 8b 44 24 10 mov 0x10(%r12),%rax - 4021fb: 48 85 c0 test %rax,%rax - 4021fe: 0f 84 ed 02 00 00 je 4024f1 <_nl_find_msg+0x5a1> - 402204: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 402208: 0f 84 d7 02 00 00 je 4024e5 <_nl_find_msg+0x595> - 40220e: 4a 8b 04 f0 mov (%rax,%r14,8),%rax - 402212: 48 85 c0 test %rax,%rax - 402215: 0f 84 5f 03 00 00 je 40257a <_nl_find_msg+0x62a> - 40221b: 48 8d 78 08 lea 0x8(%rax),%rdi - 40221f: 48 8b 00 mov (%rax),%rax - 402222: 48 89 7d a0 mov %rdi,-0x60(%rbp) - 402226: 48 89 45 98 mov %rax,-0x68(%rbp) - 40222a: e9 f7 00 00 00 jmpq 402326 <_nl_find_msg+0x3d6> - 40222f: 90 nop - 402230: 4a 8d 04 d0 lea (%rax,%r10,8),%rax - 402234: 8b 95 78 ff ff ff mov -0x88(%rbp),%edx - 40223a: 3b 10 cmp (%rax),%edx - 40223c: 0f 87 45 fe ff ff ja 402087 <_nl_find_msg+0x137> - 402242: 49 8b 34 24 mov (%r12),%rsi - 402246: 8b 40 04 mov 0x4(%rax),%eax - 402249: e9 1d fe ff ff jmpq 40206b <_nl_find_msg+0x11b> - 40224e: 66 90 xchg %ax,%ax - 402250: 8b 45 a8 mov -0x58(%rbp),%eax - 402253: 45 31 ff xor %r15d,%r15d - 402256: 49 89 c5 mov %rax,%r13 - 402259: 48 89 45 90 mov %rax,-0x70(%rbp) - 40225d: 48 89 d8 mov %rbx,%rax - 402260: 4c 89 eb mov %r13,%rbx - 402263: 49 89 c5 mov %rax,%r13 - 402266: eb 31 jmp 402299 <_nl_find_msg+0x349> - 402268: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 40226f: 00 - 402270: 4e 8d 34 3b lea (%rbx,%r15,1),%r14 - 402274: 48 8b 7d a0 mov -0x60(%rbp),%rdi - 402278: 49 d1 ee shr %r14 - 40227b: 43 8b 74 f4 04 mov 0x4(%r12,%r14,8),%esi - 402280: 48 03 75 98 add -0x68(%rbp),%rsi - 402284: e8 d7 e0 ff ff callq 400360 <__rela_iplt_end+0x98> - 402289: 85 c0 test %eax,%eax - 40228b: 78 5b js 4022e8 <_nl_find_msg+0x398> - 40228d: 85 c0 test %eax,%eax - 40228f: 0f 84 f3 00 00 00 je 402388 <_nl_find_msg+0x438> - 402295: 4d 8d 7e 01 lea 0x1(%r14),%r15 - 402299: 49 39 df cmp %rbx,%r15 - 40229c: 0f 83 0a fe ff ff jae 4020ac <_nl_find_msg+0x15c> - 4022a2: 41 8b 75 18 mov 0x18(%r13),%esi - 4022a6: 49 8b 45 00 mov 0x0(%r13),%rax - 4022aa: 4d 8b 65 30 mov 0x30(%r13),%r12 - 4022ae: 85 f6 test %esi,%esi - 4022b0: 48 89 45 98 mov %rax,-0x68(%rbp) - 4022b4: 74 ba je 402270 <_nl_find_msg+0x320> - 4022b6: 4d 8d 34 1f lea (%r15,%rbx,1),%r14 - 4022ba: 48 8b 7d a0 mov -0x60(%rbp),%rdi - 4022be: 49 d1 ee shr %r14 - 4022c1: 43 8b 74 f4 04 mov 0x4(%r12,%r14,8),%esi - 4022c6: 0f ce bswap %esi - 4022c8: 89 f6 mov %esi,%esi - 4022ca: 48 03 75 98 add -0x68(%rbp),%rsi - 4022ce: e8 8d e0 ff ff callq 400360 <__rela_iplt_end+0x98> - 4022d3: 85 c0 test %eax,%eax - 4022d5: 79 b6 jns 40228d <_nl_find_msg+0x33d> - 4022d7: 4d 39 f7 cmp %r14,%r15 - 4022da: 4c 89 f3 mov %r14,%rbx - 4022dd: 72 d7 jb 4022b6 <_nl_find_msg+0x366> - 4022df: e9 c8 fd ff ff jmpq 4020ac <_nl_find_msg+0x15c> - 4022e4: 0f 1f 40 00 nopl 0x0(%rax) - 4022e8: 4d 39 f7 cmp %r14,%r15 - 4022eb: 4c 89 f3 mov %r14,%rbx - 4022ee: 72 80 jb 402270 <_nl_find_msg+0x320> - 4022f0: e9 b7 fd ff ff jmpq 4020ac <_nl_find_msg+0x15c> - 4022f5: 0f 1f 00 nopl (%rax) - 4022f8: 4c 89 f1 mov %r14,%rcx - 4022fb: 48 29 c1 sub %rax,%rcx - 4022fe: 48 89 c8 mov %rcx,%rax - 402301: 48 c1 e0 04 shl $0x4,%rax - 402305: 48 03 43 50 add 0x50(%rbx),%rax - 402309: 48 8b 48 08 mov 0x8(%rax),%rcx - 40230d: 48 8b 00 mov (%rax),%rax - 402310: 48 89 4d a0 mov %rcx,-0x60(%rbp) - 402314: 48 89 45 98 mov %rax,-0x68(%rbp) - 402318: 8b 95 68 ff ff ff mov -0x98(%rbp),%edx - 40231e: 85 d2 test %edx,%edx - 402320: 0f 85 1a fe ff ff jne 402140 <_nl_find_msg+0x1f0> - 402326: 48 8b 85 60 ff ff ff mov -0xa0(%rbp),%rax - 40232d: 48 8b 7d 98 mov -0x68(%rbp),%rdi - 402331: 48 89 38 mov %rdi,(%rax) - 402334: 48 8b 45 a0 mov -0x60(%rbp),%rax - 402338: 48 8d 65 d8 lea -0x28(%rbp),%rsp - 40233c: 5b pop %rbx - 40233d: 41 5c pop %r12 - 40233f: 41 5d pop %r13 - 402341: 41 5e pop %r14 - 402343: 41 5f pop %r15 - 402345: 5d pop %rbp - 402346: c3 retq - 402347: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 40234e: 00 00 - 402350: 4a 8d 04 f0 lea (%rax,%r14,8),%rax - 402354: 8b 50 04 mov 0x4(%rax),%edx - 402357: 8b 00 mov (%rax),%eax - 402359: 83 c0 01 add $0x1,%eax - 40235c: 49 8d 3c 17 lea (%r15,%rdx,1),%rdi - 402360: 48 89 45 98 mov %rax,-0x68(%rbp) - 402364: 48 89 7d a0 mov %rdi,-0x60(%rbp) - 402368: eb ae jmp 402318 <_nl_find_msg+0x3c8> - 40236a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 402370: e8 cb 13 00 00 callq 403740 <_nl_load_domain> - 402375: 48 8b 85 70 ff ff ff mov -0x90(%rbp),%rax - 40237c: e9 12 fc ff ff jmpq 401f93 <_nl_find_msg+0x43> - 402381: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 402388: 4c 89 eb mov %r13,%rbx - 40238b: 48 8b 45 90 mov -0x70(%rbp),%rax - 40238f: e9 66 fd ff ff jmpq 4020fa <_nl_find_msg+0x1aa> - 402394: 48 8b 5d 88 mov -0x78(%rbp),%rbx - 402398: b8 00 00 00 00 mov $0x0,%eax - 40239d: 45 31 e4 xor %r12d,%r12d - 4023a0: 48 85 c0 test %rax,%rax - 4023a3: 48 89 45 88 mov %rax,-0x78(%rbp) - 4023a7: 0f 85 28 fe ff ff jne 4021d5 <_nl_find_msg+0x285> - 4023ad: b8 00 00 00 00 mov $0x0,%eax - 4023b2: 48 85 c0 test %rax,%rax - 4023b5: 74 09 je 4023c0 <_nl_find_msg+0x470> - 4023b7: 48 8d bb 80 00 00 00 lea 0x80(%rbx),%rdi - 4023be: ff d0 callq *%rax - 4023c0: 48 8b 43 78 mov 0x78(%rbx),%rax - 4023c4: 48 85 c0 test %rax,%rax - 4023c7: 48 89 45 80 mov %rax,-0x80(%rbp) - 4023cb: 0f 84 cd 06 00 00 je 402a9e <_nl_find_msg+0xb4e> - 4023d1: 48 89 c1 mov %rax,%rcx - 4023d4: 48 8b 43 70 mov 0x70(%rbx),%rax - 4023d8: 48 89 9d 68 ff ff ff mov %rbx,-0x98(%rbp) - 4023df: 4c 8b 7d 90 mov -0x70(%rbp),%r15 - 4023e3: 48 89 cb mov %rcx,%rbx - 4023e6: 48 89 c7 mov %rax,%rdi - 4023e9: 48 89 85 78 ff ff ff mov %rax,-0x88(%rbp) - 4023f0: 48 8d 04 49 lea (%rcx,%rcx,2),%rax - 4023f4: 48 8d 54 c7 e8 lea -0x18(%rdi,%rax,8),%rdx - 4023f9: 49 89 d5 mov %rdx,%r13 - 4023fc: eb 0f jmp 40240d <_nl_find_msg+0x4bd> - 4023fe: 66 90 xchg %ax,%ax - 402400: 49 83 ed 18 sub $0x18,%r13 - 402404: 48 85 db test %rbx,%rbx - 402407: 0f 84 f3 02 00 00 je 402700 <_nl_find_msg+0x7b0> - 40240d: 49 8b 7d 00 mov 0x0(%r13),%rdi - 402411: 4c 89 fe mov %r15,%rsi - 402414: 48 83 eb 01 sub $0x1,%rbx - 402418: 4d 89 ec mov %r13,%r12 - 40241b: e8 40 df ff ff callq 400360 <__rela_iplt_end+0x98> - 402420: 85 c0 test %eax,%eax - 402422: 75 dc jne 402400 <_nl_find_msg+0x4b0> - 402424: 48 8b 9d 68 ff ff ff mov -0x98(%rbp),%rbx - 40242b: 48 83 7d 88 00 cmpq $0x0,-0x78(%rbp) - 402430: 0f 84 b4 fd ff ff je 4021ea <_nl_find_msg+0x29a> - 402436: 48 8d bb 80 00 00 00 lea 0x80(%rbx),%rdi - 40243d: e8 be db bf ff callq 0 <_nl_current_LC_CTYPE> - 402442: e9 a3 fd ff ff jmpq 4021ea <_nl_find_msg+0x29a> - 402447: 8b 05 d3 9b 2c 00 mov 0x2c9bd3(%rip),%eax # 6cc020 - 40244d: 4c 8b 2d c4 9b 2c 00 mov 0x2c9bc4(%rip),%r13 # 6cc018 - 402454: 85 c0 test %eax,%eax - 402456: 0f 84 73 02 00 00 je 4026cf <_nl_find_msg+0x77f> - 40245c: 4d 85 ed test %r13,%r13 - 40245f: 4c 89 6d 90 mov %r13,-0x70(%rbp) - 402463: 0f 85 f8 fc ff ff jne 402161 <_nl_find_msg+0x211> - 402469: 48 c7 c0 b0 ff ff ff mov $0xffffffffffffffb0,%rax - 402470: 64 48 8b 00 mov %fs:(%rax),%rax - 402474: 48 8b 00 mov (%rax),%rax - 402477: 48 8b 80 b0 00 00 00 mov 0xb0(%rax),%rax - 40247e: 48 89 45 90 mov %rax,-0x70(%rbp) - 402482: e9 da fc ff ff jmpq 402161 <_nl_find_msg+0x211> - 402487: 48 8b 03 mov (%rbx),%rax - 40248a: 48 89 df mov %rbx,%rdi - 40248d: 48 89 05 ac 9b 2c 00 mov %rax,0x2c9bac(%rip) # 6cc040 - 402494: e8 17 b9 01 00 callq 41ddb0 <__cfree> - 402499: 48 c7 05 8c 9b 2c 00 movq $0x0,0x2c9b8c(%rip) # 6cc030 - 4024a0: 00 00 00 00 - 4024a4: 48 c7 05 79 9b 2c 00 movq $0x0,0x2c9b79(%rip) # 6cc028 - 4024ab: 00 00 00 00 - 4024af: 83 3d 06 ad 2c 00 00 cmpl $0x0,0x2cad06(%rip) # 6cd1bc <__libc_multiple_threads> - 4024b6: 74 0b je 4024c3 <_nl_find_msg+0x573> - 4024b8: f0 ff 0d 79 9b 2c 00 lock decl 0x2c9b79(%rip) # 6cc038 - 4024bf: 75 0a jne 4024cb <_nl_find_msg+0x57b> - 4024c1: eb 22 jmp 4024e5 <_nl_find_msg+0x595> - 4024c3: ff 0d 6f 9b 2c 00 decl 0x2c9b6f(%rip) # 6cc038 - 4024c9: 74 1a je 4024e5 <_nl_find_msg+0x595> - 4024cb: 48 8d 3d 66 9b 2c 00 lea 0x2c9b66(%rip),%rdi # 6cc038 - 4024d2: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 4024d9: e8 22 01 04 00 callq 442600 <__lll_unlock_wake_private> - 4024de: 48 81 c4 80 00 00 00 add $0x80,%rsp - 4024e5: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax - 4024ec: e9 bd fb ff ff jmpq 4020ae <_nl_find_msg+0x15e> - 4024f1: be 01 00 00 00 mov $0x1,%esi - 4024f6: 83 3d bf ac 2c 00 00 cmpl $0x0,0x2cacbf(%rip) # 6cd1bc <__libc_multiple_threads> - 4024fd: 74 0c je 40250b <_nl_find_msg+0x5bb> - 4024ff: f0 0f b1 35 31 9b 2c lock cmpxchg %esi,0x2c9b31(%rip) # 6cc038 - 402506: 00 - 402507: 75 0b jne 402514 <_nl_find_msg+0x5c4> - 402509: eb 23 jmp 40252e <_nl_find_msg+0x5de> - 40250b: 0f b1 35 26 9b 2c 00 cmpxchg %esi,0x2c9b26(%rip) # 6cc038 - 402512: 74 1a je 40252e <_nl_find_msg+0x5de> - 402514: 48 8d 3d 1d 9b 2c 00 lea 0x2c9b1d(%rip),%rdi # 6cc038 - 40251b: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 402522: e8 a9 00 04 00 callq 4425d0 <__lll_lock_wait_private> - 402527: 48 81 c4 80 00 00 00 add $0x80,%rsp - 40252e: 49 83 7c 24 10 00 cmpq $0x0,0x10(%r12) - 402534: 0f 84 88 05 00 00 je 402ac2 <_nl_find_msg+0xb72> - 40253a: 83 3d 7b ac 2c 00 00 cmpl $0x0,0x2cac7b(%rip) # 6cd1bc <__libc_multiple_threads> - 402541: 74 0b je 40254e <_nl_find_msg+0x5fe> - 402543: f0 ff 0d ee 9a 2c 00 lock decl 0x2c9aee(%rip) # 6cc038 - 40254a: 75 0a jne 402556 <_nl_find_msg+0x606> - 40254c: eb 22 jmp 402570 <_nl_find_msg+0x620> - 40254e: ff 0d e4 9a 2c 00 decl 0x2c9ae4(%rip) # 6cc038 - 402554: 74 1a je 402570 <_nl_find_msg+0x620> - 402556: 48 8d 3d db 9a 2c 00 lea 0x2c9adb(%rip),%rdi # 6cc038 - 40255d: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 402564: e8 97 00 04 00 callq 442600 <__lll_unlock_wake_private> - 402569: 48 81 c4 80 00 00 00 add $0x80,%rsp - 402570: 49 8b 44 24 10 mov 0x10(%r12),%rax - 402575: e9 8a fc ff ff jmpq 402204 <_nl_find_msg+0x2b4> - 40257a: be 01 00 00 00 mov $0x1,%esi - 40257f: 83 3d 36 ac 2c 00 00 cmpl $0x0,0x2cac36(%rip) # 6cd1bc <__libc_multiple_threads> - 402586: 74 0c je 402594 <_nl_find_msg+0x644> - 402588: f0 0f b1 35 a8 9a 2c lock cmpxchg %esi,0x2c9aa8(%rip) # 6cc038 - 40258f: 00 - 402590: 75 0b jne 40259d <_nl_find_msg+0x64d> - 402592: eb 23 jmp 4025b7 <_nl_find_msg+0x667> - 402594: 0f b1 35 9d 9a 2c 00 cmpxchg %esi,0x2c9a9d(%rip) # 6cc038 - 40259b: 74 1a je 4025b7 <_nl_find_msg+0x667> - 40259d: 48 8d 3d 94 9a 2c 00 lea 0x2c9a94(%rip),%rdi # 6cc038 - 4025a4: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 4025ab: e8 20 00 04 00 callq 4425d0 <__lll_lock_wait_private> - 4025b0: 48 81 c4 80 00 00 00 add $0x80,%rsp - 4025b7: 48 8b 45 a0 mov -0x60(%rbp),%rax - 4025bb: 45 31 ed xor %r13d,%r13d - 4025be: 4c 89 75 a8 mov %r14,-0x58(%rbp) - 4025c2: 48 8b 0d 5f 9a 2c 00 mov 0x2c9a5f(%rip),%rcx # 6cc028 - 4025c9: 4c 8b 7d 98 mov -0x68(%rbp),%r15 - 4025cd: 45 89 ee mov %r13d,%r14d - 4025d0: 48 89 45 b8 mov %rax,-0x48(%rbp) - 4025d4: 48 8b 05 55 9a 2c 00 mov 0x2c9a55(%rip),%rax # 6cc030 - 4025db: 48 83 c0 08 add $0x8,%rax - 4025df: 48 89 45 c0 mov %rax,-0x40(%rbp) - 4025e3: eb 61 jmp 402646 <_nl_find_msg+0x6f6> - 4025e5: 0f 1f 00 nopl (%rax) - 4025e8: 45 85 f6 test %r14d,%r14d - 4025eb: 0f 84 9f 00 00 00 je 402690 <_nl_find_msg+0x740> - 4025f1: 41 83 c6 01 add $0x1,%r14d - 4025f5: 48 8b 1d 44 9a 2c 00 mov 0x2c9a44(%rip),%rbx # 6cc040 - 4025fc: 41 69 ce f0 0f 00 00 imul $0xff0,%r14d,%ecx - 402603: 48 89 df mov %rbx,%rdi - 402606: 4c 63 e9 movslq %ecx,%r13 - 402609: 4c 89 ee mov %r13,%rsi - 40260c: 4c 89 2d 15 9a 2c 00 mov %r13,0x2c9a15(%rip) # 6cc028 - 402613: e8 58 b9 01 00 callq 41df70 <__libc_realloc> - 402618: 48 85 c0 test %rax,%rax - 40261b: 0f 84 66 fe ff ff je 402487 <_nl_find_msg+0x537> - 402621: 49 8d 4d f8 lea -0x8(%r13),%rcx - 402625: 48 89 05 14 9a 2c 00 mov %rax,0x2c9a14(%rip) # 6cc040 - 40262c: 48 8d 50 08 lea 0x8(%rax),%rdx - 402630: 48 83 c0 10 add $0x10,%rax - 402634: 48 89 0d ed 99 2c 00 mov %rcx,0x2c99ed(%rip) # 6cc028 - 40263b: 48 89 45 c0 mov %rax,-0x40(%rbp) - 40263f: 48 89 15 ea 99 2c 00 mov %rdx,0x2c99ea(%rip) # 6cc030 - 402646: 48 83 f9 07 cmp $0x7,%rcx - 40264a: 76 9c jbe 4025e8 <_nl_find_msg+0x698> - 40264c: 4c 89 fa mov %r15,%rdx - 40264f: 48 03 55 b8 add -0x48(%rbp),%rdx - 402653: 49 8b 7c 24 08 mov 0x8(%r12),%rdi - 402658: 4c 8d 44 08 f8 lea -0x8(%rax,%rcx,1),%r8 - 40265d: 4c 8d 4d c8 lea -0x38(%rbp),%r9 - 402661: 48 8d 4d c0 lea -0x40(%rbp),%rcx - 402665: 48 8d 75 b8 lea -0x48(%rbp),%rsi - 402669: e8 02 20 04 00 callq 444670 <__gconv> - 40266e: a9 fb ff ff ff test $0xfffffffb,%eax - 402673: 0f 84 46 03 00 00 je 4029bf <_nl_find_msg+0xa6f> - 402679: 83 f8 05 cmp $0x5,%eax - 40267c: 0f 85 02 03 00 00 jne 402984 <_nl_find_msg+0xa34> - 402682: 48 8b 45 a0 mov -0x60(%rbp),%rax - 402686: 48 89 45 b8 mov %rax,-0x48(%rbp) - 40268a: e9 59 ff ff ff jmpq 4025e8 <_nl_find_msg+0x698> - 40268f: 90 nop - 402690: bf f0 0f 00 00 mov $0xff0,%edi - 402695: 48 c7 05 88 99 2c 00 movq $0xff0,0x2c9988(%rip) # 6cc028 - 40269c: f0 0f 00 00 - 4026a0: e8 6b b3 01 00 callq 41da10 <__libc_malloc> - 4026a5: 48 85 c0 test %rax,%rax - 4026a8: 0f 84 eb fd ff ff je 402499 <_nl_find_msg+0x549> - 4026ae: 48 8b 15 8b 99 2c 00 mov 0x2c998b(%rip),%rdx # 6cc040 - 4026b5: b9 e8 0f 00 00 mov $0xfe8,%ecx - 4026ba: 48 89 05 7f 99 2c 00 mov %rax,0x2c997f(%rip) # 6cc040 - 4026c1: 41 be 01 00 00 00 mov $0x1,%r14d - 4026c7: 48 89 10 mov %rdx,(%rax) - 4026ca: e9 5d ff ff ff jmpq 40262c <_nl_find_msg+0x6dc> - 4026cf: bf 78 11 4a 00 mov $0x4a1178,%edi - 4026d4: e8 07 c1 00 00 callq 40e7e0 - 4026d9: 48 85 c0 test %rax,%rax - 4026dc: 49 89 c4 mov %rax,%r12 - 4026df: 74 09 je 4026ea <_nl_find_msg+0x79a> - 4026e1: 80 38 00 cmpb $0x0,(%rax) - 4026e4: 0f 85 64 03 00 00 jne 402a4e <_nl_find_msg+0xafe> - 4026ea: 4c 8b 2d 27 99 2c 00 mov 0x2c9927(%rip),%r13 # 6cc018 - 4026f1: c7 05 25 99 2c 00 01 movl $0x1,0x2c9925(%rip) # 6cc020 - 4026f8: 00 00 00 - 4026fb: e9 5c fd ff ff jmpq 40245c <_nl_find_msg+0x50c> - 402700: 48 8b 9d 68 ff ff ff mov -0x98(%rbp),%rbx - 402707: 48 8b 85 78 ff ff ff mov -0x88(%rbp),%rax - 40270e: 48 85 c0 test %rax,%rax - 402711: 0f 84 6d 03 00 00 je 402a84 <_nl_find_msg+0xb34> - 402717: 48 8b 7d 80 mov -0x80(%rbp),%rdi - 40271b: 48 8d 74 7f 03 lea 0x3(%rdi,%rdi,2),%rsi - 402720: 48 89 c7 mov %rax,%rdi - 402723: 48 c1 e6 03 shl $0x3,%rsi - 402727: e8 44 b8 01 00 callq 41df70 <__libc_realloc> - 40272c: 49 89 c4 mov %rax,%r12 - 40272f: 4d 85 e4 test %r12,%r12 - 402732: 0f 84 0d 02 00 00 je 402945 <_nl_find_msg+0x9f5> - 402738: 48 8b 7d 90 mov -0x70(%rbp),%rdi - 40273c: 4c 89 63 70 mov %r12,0x70(%rbx) - 402740: e8 bb 0e 02 00 callq 423600 <__strdup> - 402745: 48 85 c0 test %rax,%rax - 402748: 49 89 c5 mov %rax,%r13 - 40274b: 0f 84 f4 01 00 00 je 402945 <_nl_find_msg+0x9f5> - 402751: 48 8b 45 80 mov -0x80(%rbp),%rax - 402755: 48 8b bd 70 ff ff ff mov -0x90(%rbp),%rdi - 40275c: 4c 8d 45 c8 lea -0x38(%rbp),%r8 - 402760: 48 8b b5 58 ff ff ff mov -0xa8(%rbp),%rsi - 402767: 31 c9 xor %ecx,%ecx - 402769: ba 25 67 4b 00 mov $0x4b6725,%edx - 40276e: 48 8d 04 40 lea (%rax,%rax,2),%rax - 402772: 4d 8d 24 c4 lea (%r12,%rax,8),%r12 - 402776: 4d 89 2c 24 mov %r13,(%r12) - 40277a: 49 c7 44 24 08 ff ff movq $0xffffffffffffffff,0x8(%r12) - 402781: ff ff - 402783: e8 c8 f7 ff ff callq 401f50 <_nl_find_msg> - 402788: 48 89 c7 mov %rax,%rdi - 40278b: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax - 402792: 48 39 c7 cmp %rax,%rdi - 402795: 0f 84 13 f9 ff ff je 4020ae <_nl_find_msg+0x15e> - 40279b: 48 85 ff test %rdi,%rdi - 40279e: 0f 84 cd 01 00 00 je 402971 <_nl_find_msg+0xa21> - 4027a4: be 87 11 4a 00 mov $0x4a1187,%esi - 4027a9: e8 72 db ff ff callq 400320 <__rela_iplt_end+0x58> - 4027ae: 48 85 c0 test %rax,%rax - 4027b1: 0f 84 ba 01 00 00 je 402971 <_nl_find_msg+0xa21> - 4027b7: 0f b6 50 08 movzbl 0x8(%rax),%edx - 4027bb: 48 8d 70 08 lea 0x8(%rax),%rsi - 4027bf: f6 c2 df test $0xdf,%dl - 4027c2: 0f 84 8b 03 00 00 je 402b53 <_nl_find_msg+0xc03> - 4027c8: 83 ea 09 sub $0x9,%edx - 4027cb: 80 fa 01 cmp $0x1,%dl - 4027ce: ba 00 00 00 00 mov $0x0,%edx - 4027d3: 77 13 ja 4027e8 <_nl_find_msg+0x898> - 4027d5: eb 1f jmp 4027f6 <_nl_find_msg+0x8a6> - 4027d7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 4027de: 00 00 - 4027e0: 83 e9 09 sub $0x9,%ecx - 4027e3: 80 f9 01 cmp $0x1,%cl - 4027e6: 76 0e jbe 4027f6 <_nl_find_msg+0x8a6> - 4027e8: 48 83 c2 01 add $0x1,%rdx - 4027ec: 0f b6 4c 10 08 movzbl 0x8(%rax,%rdx,1),%ecx - 4027f1: f6 c1 df test $0xdf,%cl - 4027f4: 75 ea jne 4027e0 <_nl_find_msg+0x890> - 4027f6: 48 8d 42 1f lea 0x1f(%rdx),%rax - 4027fa: 48 83 e0 f0 and $0xfffffffffffffff0,%rax - 4027fe: 48 29 c4 sub %rax,%rsp - 402801: 4c 8d 44 24 0f lea 0xf(%rsp),%r8 - 402806: 49 83 e0 f0 and $0xfffffffffffffff0,%r8 - 40280a: 4c 89 c7 mov %r8,%rdi - 40280d: 4c 89 45 80 mov %r8,-0x80(%rbp) - 402811: 4c 89 45 90 mov %r8,-0x70(%rbp) - 402815: e8 a6 3d 02 00 callq 4265c0 <__mempcpy> - 40281a: 31 ff xor %edi,%edi - 40281c: c6 00 00 movb $0x0,(%rax) - 40281f: 48 8b 4d 80 mov -0x80(%rbp),%rcx - 402823: 4c 89 e8 mov %r13,%rax - 402826: 4c 8b 45 90 mov -0x70(%rbp),%r8 - 40282a: eb 14 jmp 402840 <_nl_find_msg+0x8f0> - 40282c: 0f 1f 40 00 nopl 0x0(%rax) - 402830: 48 83 c0 01 add $0x1,%rax - 402834: 80 fa 2f cmp $0x2f,%dl - 402837: 0f 94 c2 sete %dl - 40283a: 0f b6 d2 movzbl %dl,%edx - 40283d: 48 01 d7 add %rdx,%rdi - 402840: 0f b6 10 movzbl (%rax),%edx - 402843: 84 d2 test %dl,%dl - 402845: 75 e9 jne 402830 <_nl_find_msg+0x8e0> - 402847: 4c 29 e8 sub %r13,%rax - 40284a: 49 0f be 55 00 movsbq 0x0(%r13),%rdx - 40284f: 48 83 c0 29 add $0x29,%rax - 402853: 48 83 e0 f0 and $0xfffffffffffffff0,%rax - 402857: 48 29 c4 sub %rax,%rsp - 40285a: 48 8d 44 24 0f lea 0xf(%rsp),%rax - 40285f: 48 83 e0 f0 and $0xfffffffffffffff0,%rax - 402863: 84 d2 test %dl,%dl - 402865: 49 89 c1 mov %rax,%r9 - 402868: 74 21 je 40288b <_nl_find_msg+0x93b> - 40286a: 4c 8b 1d 87 fe 0a 00 mov 0xafe87(%rip),%r11 # 4b26f8 <_nl_C_locobj+0x78> - 402871: 4c 89 ee mov %r13,%rsi - 402874: 41 8b 14 93 mov (%r11,%rdx,4),%edx - 402878: 48 83 c0 01 add $0x1,%rax - 40287c: 48 83 c6 01 add $0x1,%rsi - 402880: 88 50 ff mov %dl,-0x1(%rax) - 402883: 48 0f be 16 movsbq (%rsi),%rdx - 402887: 84 d2 test %dl,%dl - 402889: 75 e9 jne 402874 <_nl_find_msg+0x924> - 40288b: 48 83 ff 01 cmp $0x1,%rdi - 40288f: 0f 86 19 02 00 00 jbe 402aae <_nl_find_msg+0xb5e> - 402895: c6 00 00 movb $0x0,(%rax) - 402898: 31 ff xor %edi,%edi - 40289a: 4c 89 c0 mov %r8,%rax - 40289d: eb 11 jmp 4028b0 <_nl_find_msg+0x960> - 40289f: 90 nop - 4028a0: 48 83 c0 01 add $0x1,%rax - 4028a4: 80 fa 2f cmp $0x2f,%dl - 4028a7: 0f 94 c2 sete %dl - 4028aa: 0f b6 d2 movzbl %dl,%edx - 4028ad: 48 01 d7 add %rdx,%rdi - 4028b0: 0f b6 10 movzbl (%rax),%edx - 4028b3: 84 d2 test %dl,%dl - 4028b5: 75 e9 jne 4028a0 <_nl_find_msg+0x950> - 4028b7: 4c 29 c0 sub %r8,%rax - 4028ba: 48 83 c0 21 add $0x21,%rax - 4028be: 48 83 e0 f0 and $0xfffffffffffffff0,%rax - 4028c2: 48 29 c4 sub %rax,%rsp - 4028c5: 49 0f be 00 movsbq (%r8),%rax - 4028c9: 48 8d 74 24 0f lea 0xf(%rsp),%rsi - 4028ce: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi - 4028d2: 84 c0 test %al,%al - 4028d4: 0f 84 80 02 00 00 je 402b5a <_nl_find_msg+0xc0a> - 4028da: 4c 8b 05 17 fe 0a 00 mov 0xafe17(%rip),%r8 # 4b26f8 <_nl_C_locobj+0x78> - 4028e1: 48 89 f2 mov %rsi,%rdx - 4028e4: 41 8b 04 80 mov (%r8,%rax,4),%eax - 4028e8: 48 83 c2 01 add $0x1,%rdx - 4028ec: 48 83 c1 01 add $0x1,%rcx - 4028f0: 88 42 ff mov %al,-0x1(%rdx) - 4028f3: 48 0f be 01 movsbq (%rcx),%rax - 4028f7: 84 c0 test %al,%al - 4028f9: 75 e9 jne 4028e4 <_nl_find_msg+0x994> - 4028fb: 48 83 ff 01 cmp $0x1,%rdi - 4028ff: 0f 86 eb 01 00 00 jbe 402af0 <_nl_find_msg+0xba0> - 402905: c6 02 00 movb $0x0,(%rdx) - 402908: 49 8d 54 24 08 lea 0x8(%r12),%rdx - 40290d: b9 01 00 00 00 mov $0x1,%ecx - 402912: 4c 89 cf mov %r9,%rdi - 402915: e8 46 18 04 00 callq 444160 <__gconv_open> - 40291a: 85 c0 test %eax,%eax - 40291c: 74 53 je 402971 <_nl_find_msg+0xa21> - 40291e: 83 f8 ff cmp $0xffffffff,%eax - 402921: 74 45 je 402968 <_nl_find_msg+0xa18> - 402923: 48 83 7d 88 00 cmpq $0x0,-0x78(%rbp) - 402928: 74 0c je 402936 <_nl_find_msg+0x9e6> - 40292a: 48 8d bb 80 00 00 00 lea 0x80(%rbx),%rdi - 402931: e8 ca d6 bf ff callq 0 <_nl_current_LC_CTYPE> - 402936: 4c 89 ef mov %r13,%rdi - 402939: e8 72 b4 01 00 callq 41ddb0 <__cfree> - 40293e: 31 c0 xor %eax,%eax - 402940: e9 69 f7 ff ff jmpq 4020ae <_nl_find_msg+0x15e> - 402945: 48 83 7d 88 00 cmpq $0x0,-0x78(%rbp) - 40294a: 0f 84 95 fb ff ff je 4024e5 <_nl_find_msg+0x595> - 402950: 48 8d bb 80 00 00 00 lea 0x80(%rbx),%rdi - 402957: e8 a4 d6 bf ff callq 0 <_nl_current_LC_CTYPE> - 40295c: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax - 402963: e9 46 f7 ff ff jmpq 4020ae <_nl_find_msg+0x15e> - 402968: 49 c7 44 24 08 ff ff movq $0xffffffffffffffff,0x8(%r12) - 40296f: ff ff - 402971: 49 c7 44 24 10 00 00 movq $0x0,0x10(%r12) - 402978: 00 00 - 40297a: 48 83 43 78 01 addq $0x1,0x78(%rbx) - 40297f: e9 a7 fa ff ff jmpq 40242b <_nl_find_msg+0x4db> - 402984: 83 3d 31 a8 2c 00 00 cmpl $0x0,0x2ca831(%rip) # 6cd1bc <__libc_multiple_threads> - 40298b: 74 0b je 402998 <_nl_find_msg+0xa48> - 40298d: f0 ff 0d a4 96 2c 00 lock decl 0x2c96a4(%rip) # 6cc038 - 402994: 75 0a jne 4029a0 <_nl_find_msg+0xa50> - 402996: eb 22 jmp 4029ba <_nl_find_msg+0xa6a> - 402998: ff 0d 9a 96 2c 00 decl 0x2c969a(%rip) # 6cc038 - 40299e: 74 1a je 4029ba <_nl_find_msg+0xa6a> - 4029a0: 48 8d 3d 91 96 2c 00 lea 0x2c9691(%rip),%rdi # 6cc038 - 4029a7: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 4029ae: e8 4d fc 03 00 callq 442600 <__lll_unlock_wake_private> - 4029b3: 48 81 c4 80 00 00 00 add $0x80,%rsp - 4029ba: e9 ed f6 ff ff jmpq 4020ac <_nl_find_msg+0x15c> - 4029bf: 48 8b 05 6a 96 2c 00 mov 0x2c966a(%rip),%rax # 6cc030 - 4029c6: 48 8b 55 c0 mov -0x40(%rbp),%rdx - 4029ca: 4c 8b 75 a8 mov -0x58(%rbp),%r14 - 4029ce: 48 29 c2 sub %rax,%rdx - 4029d1: 48 83 ea 08 sub $0x8,%rdx - 4029d5: 48 89 10 mov %rdx,(%rax) - 4029d8: 49 8b 54 24 10 mov 0x10(%r12),%rdx - 4029dd: 4a 89 04 f2 mov %rax,(%rdx,%r14,8) - 4029e1: 48 8b 4d c0 mov -0x40(%rbp),%rcx - 4029e5: 48 29 c8 sub %rcx,%rax - 4029e8: 48 03 05 39 96 2c 00 add 0x2c9639(%rip),%rax # 6cc028 - 4029ef: 48 89 c2 mov %rax,%rdx - 4029f2: 48 83 e0 f8 and $0xfffffffffffffff8,%rax - 4029f6: 83 e2 07 and $0x7,%edx - 4029f9: 48 89 05 28 96 2c 00 mov %rax,0x2c9628(%rip) # 6cc028 - 402a00: 48 01 ca add %rcx,%rdx - 402a03: 48 89 15 26 96 2c 00 mov %rdx,0x2c9626(%rip) # 6cc030 - 402a0a: 83 3d ab a7 2c 00 00 cmpl $0x0,0x2ca7ab(%rip) # 6cd1bc <__libc_multiple_threads> - 402a11: 74 0b je 402a1e <_nl_find_msg+0xace> - 402a13: f0 ff 0d 1e 96 2c 00 lock decl 0x2c961e(%rip) # 6cc038 - 402a1a: 75 0a jne 402a26 <_nl_find_msg+0xad6> - 402a1c: eb 22 jmp 402a40 <_nl_find_msg+0xaf0> - 402a1e: ff 0d 14 96 2c 00 decl 0x2c9614(%rip) # 6cc038 - 402a24: 74 1a je 402a40 <_nl_find_msg+0xaf0> - 402a26: 48 8d 3d 0b 96 2c 00 lea 0x2c960b(%rip),%rdi # 6cc038 - 402a2d: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 402a34: e8 c7 fb 03 00 callq 442600 <__lll_unlock_wake_private> - 402a39: 48 81 c4 80 00 00 00 add $0x80,%rsp - 402a40: 49 8b 44 24 10 mov 0x10(%r12),%rax - 402a45: 4a 8b 04 f0 mov (%rax,%r14,8),%rax - 402a49: e9 cd f7 ff ff jmpq 40221b <_nl_find_msg+0x2cb> - 402a4e: 48 89 c7 mov %rax,%rdi - 402a51: e8 fa 0b 02 00 callq 423650 - 402a56: 4c 8d 78 01 lea 0x1(%rax),%r15 - 402a5a: 4c 89 ff mov %r15,%rdi - 402a5d: e8 ae af 01 00 callq 41da10 <__libc_malloc> - 402a62: 48 85 c0 test %rax,%rax - 402a65: 49 89 c5 mov %rax,%r13 - 402a68: 74 0e je 402a78 <_nl_find_msg+0xb28> - 402a6a: 4c 89 fa mov %r15,%rdx - 402a6d: 4c 89 e6 mov %r12,%rsi - 402a70: 48 89 c7 mov %rax,%rdi - 402a73: e8 a8 95 02 00 callq 42c020 - 402a78: 4c 89 2d 99 95 2c 00 mov %r13,0x2c9599(%rip) # 6cc018 - 402a7f: e9 6d fc ff ff jmpq 4026f1 <_nl_find_msg+0x7a1> - 402a84: 48 8b 45 80 mov -0x80(%rbp),%rax - 402a88: 48 8d 7c 40 03 lea 0x3(%rax,%rax,2),%rdi - 402a8d: 48 c1 e7 03 shl $0x3,%rdi - 402a91: e8 7a af 01 00 callq 41da10 <__libc_malloc> - 402a96: 49 89 c4 mov %rax,%r12 - 402a99: e9 91 fc ff ff jmpq 40272f <_nl_find_msg+0x7df> - 402a9e: 48 8b 43 70 mov 0x70(%rbx),%rax - 402aa2: 48 89 85 78 ff ff ff mov %rax,-0x88(%rbp) - 402aa9: e9 60 fc ff ff jmpq 40270e <_nl_find_msg+0x7be> - 402aae: 48 85 ff test %rdi,%rdi - 402ab1: 48 8d 50 01 lea 0x1(%rax),%rdx - 402ab5: c6 00 2f movb $0x2f,(%rax) - 402ab8: 74 5f je 402b19 <_nl_find_msg+0xbc9> - 402aba: 48 89 d0 mov %rdx,%rax - 402abd: e9 d3 fd ff ff jmpq 402895 <_nl_find_msg+0x945> - 402ac2: 8b 7d a8 mov -0x58(%rbp),%edi - 402ac5: 03 7b 40 add 0x40(%rbx),%edi - 402ac8: be 08 00 00 00 mov $0x8,%esi - 402acd: e8 ee ba 01 00 callq 41e5c0 <__calloc> - 402ad2: 48 85 c0 test %rax,%rax - 402ad5: 49 89 44 24 10 mov %rax,0x10(%r12) - 402ada: 0f 85 d7 fa ff ff jne 4025b7 <_nl_find_msg+0x667> - 402ae0: 49 c7 44 24 10 ff ff movq $0xffffffffffffffff,0x10(%r12) - 402ae7: ff ff - 402ae9: e9 4c fa ff ff jmpq 40253a <_nl_find_msg+0x5ea> - 402aee: 66 90 xchg %ax,%ax - 402af0: 48 85 ff test %rdi,%rdi - 402af3: 48 8d 42 01 lea 0x1(%rdx),%rax - 402af7: c6 02 2f movb $0x2f,(%rdx) - 402afa: 75 0d jne 402b09 <_nl_find_msg+0xbb9> - 402afc: c6 42 01 2f movb $0x2f,0x1(%rdx) - 402b00: 48 83 c2 02 add $0x2,%rdx - 402b04: e9 fc fd ff ff jmpq 402905 <_nl_find_msg+0x9b5> - 402b09: 48 89 c2 mov %rax,%rdx - 402b0c: e9 f4 fd ff ff jmpq 402905 <_nl_find_msg+0x9b5> - 402b11: 4c 89 e3 mov %r12,%rbx - 402b14: e9 db f5 ff ff jmpq 4020f4 <_nl_find_msg+0x1a4> - 402b19: 48 8d 78 02 lea 0x2(%rax),%rdi - 402b1d: c6 40 01 2f movb $0x2f,0x1(%rax) - 402b21: ba 08 00 00 00 mov $0x8,%edx - 402b26: be b1 3f 4a 00 mov $0x4a3fb1,%esi - 402b2b: 4c 89 8d 78 ff ff ff mov %r9,-0x88(%rbp) - 402b32: 4c 89 45 80 mov %r8,-0x80(%rbp) - 402b36: 48 89 4d 90 mov %rcx,-0x70(%rbp) - 402b3a: e8 81 3a 02 00 callq 4265c0 <__mempcpy> - 402b3f: 48 8b 4d 90 mov -0x70(%rbp),%rcx - 402b43: 4c 8b 45 80 mov -0x80(%rbp),%r8 - 402b47: 4c 8b 8d 78 ff ff ff mov -0x88(%rbp),%r9 - 402b4e: e9 42 fd ff ff jmpq 402895 <_nl_find_msg+0x945> - 402b53: 31 d2 xor %edx,%edx - 402b55: e9 9c fc ff ff jmpq 4027f6 <_nl_find_msg+0x8a6> - 402b5a: 48 89 f2 mov %rsi,%rdx - 402b5d: e9 99 fd ff ff jmpq 4028fb <_nl_find_msg+0x9ab> - 402b62: 0f 1f 40 00 nopl 0x0(%rax) - 402b66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 402b6d: 00 00 00 - -0000000000402b70 <__dcigettext>: - 402b70: 55 push %rbp - 402b71: 48 89 e5 mov %rsp,%rbp - 402b74: 41 57 push %r15 - 402b76: 41 56 push %r14 - 402b78: 41 55 push %r13 - 402b7a: 41 54 push %r12 - 402b7c: 53 push %rbx - 402b7d: 48 81 ec b8 00 00 00 sub $0xb8,%rsp - 402b84: 48 85 f6 test %rsi,%rsi - 402b87: 48 89 bd 60 ff ff ff mov %rdi,-0xa0(%rbp) - 402b8e: 48 89 b5 70 ff ff ff mov %rsi,-0x90(%rbp) - 402b95: 48 89 95 48 ff ff ff mov %rdx,-0xb8(%rbp) - 402b9c: 89 8d 58 ff ff ff mov %ecx,-0xa8(%rbp) - 402ba2: 4c 89 85 50 ff ff ff mov %r8,-0xb0(%rbp) - 402ba9: 44 89 8d 5c ff ff ff mov %r9d,-0xa4(%rbp) - 402bb0: 0f 84 9a 08 00 00 je 403450 <__dcigettext+0x8e0> - 402bb6: 41 83 f9 0c cmp $0xc,%r9d - 402bba: 0f 87 46 03 00 00 ja 402f06 <__dcigettext+0x396> - 402bc0: 41 83 f9 06 cmp $0x6,%r9d - 402bc4: 0f 84 3c 03 00 00 je 402f06 <__dcigettext+0x396> - 402bca: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 402bd1: bb 00 00 00 00 mov $0x0,%ebx - 402bd6: 48 85 db test %rbx,%rbx - 402bd9: 64 8b 00 mov %fs:(%rax),%eax - 402bdc: 89 85 3c ff ff ff mov %eax,-0xc4(%rbp) - 402be2: 0f 84 65 04 00 00 je 40304d <__dcigettext+0x4dd> - 402be8: bf 20 c7 6c 00 mov $0x6cc720,%edi - 402bed: ff d3 callq *%rbx - 402bef: bf e0 bf 6c 00 mov $0x6cbfe0,%edi - 402bf4: ff d3 callq *%rbx - 402bf6: 48 83 bd 60 ff ff ff cmpq $0x0,-0xa0(%rbp) - 402bfd: 00 - 402bfe: 0f 84 91 05 00 00 je 403195 <__dcigettext+0x625> - 402c04: 48 8b 85 70 ff ff ff mov -0x90(%rbp),%rax - 402c0b: 48 c7 45 b0 00 00 00 movq $0x0,-0x50(%rbp) - 402c12: 00 - 402c13: 48 89 45 c8 mov %rax,-0x38(%rbp) - 402c17: 48 8b 85 60 ff ff ff mov -0xa0(%rbp),%rax - 402c1e: 48 89 45 90 mov %rax,-0x70(%rbp) - 402c22: 8b 85 5c ff ff ff mov -0xa4(%rbp),%eax - 402c28: 89 c7 mov %eax,%edi - 402c2a: 89 45 98 mov %eax,-0x68(%rbp) - 402c2d: e8 fe c6 04 00 callq 44f330 <__current_locale_name> - 402c32: 48 89 c7 mov %rax,%rdi - 402c35: 48 89 c3 mov %rax,%rbx - 402c38: e8 13 0a 02 00 callq 423650 - 402c3d: 48 8d 50 01 lea 0x1(%rax),%rdx - 402c41: 48 83 c0 1f add $0x1f,%rax - 402c45: 48 89 de mov %rbx,%rsi - 402c48: 48 83 e0 f0 and $0xfffffffffffffff0,%rax - 402c4c: 48 29 c4 sub %rax,%rsp - 402c4f: 48 8d 7c 24 0f lea 0xf(%rsp),%rdi - 402c54: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi - 402c58: e8 c3 93 02 00 callq 42c020 - 402c5d: 48 89 85 30 ff ff ff mov %rax,-0xd0(%rbp) - 402c64: 48 89 45 a0 mov %rax,-0x60(%rbp) - 402c68: bf 60 c0 6c 00 mov $0x6cc060,%edi - 402c6d: e8 8e d3 bf ff callq 0 <_nl_current_LC_CTYPE> - 402c72: 48 8d 7d 90 lea -0x70(%rbp),%rdi - 402c76: ba 90 17 40 00 mov $0x401790,%edx - 402c7b: be 48 c0 6c 00 mov $0x6cc048,%esi - 402c80: e8 7b d9 03 00 callq 440600 <__tfind> - 402c85: 48 89 85 40 ff ff ff mov %rax,-0xc0(%rbp) - 402c8c: b8 00 00 00 00 mov $0x0,%eax - 402c91: 48 85 c0 test %rax,%rax - 402c94: 74 07 je 402c9d <__dcigettext+0x12d> - 402c96: bf 60 c0 6c 00 mov $0x6cc060,%edi - 402c9b: ff d0 callq *%rax - 402c9d: 48 8b 85 40 ff ff ff mov -0xc0(%rbp),%rax - 402ca4: 48 85 c0 test %rax,%rax - 402ca7: 74 12 je 402cbb <__dcigettext+0x14b> - 402ca9: 48 8b 00 mov (%rax),%rax - 402cac: 8b 0d f6 a4 2c 00 mov 0x2ca4f6(%rip),%ecx # 6cd1a8 <_nl_msg_cat_cntr> - 402cb2: 39 48 18 cmp %ecx,0x18(%rax) - 402cb5: 0f 84 02 04 00 00 je 4030bd <__dcigettext+0x54d> - 402cbb: 48 8b 1d de a4 2c 00 mov 0x2ca4de(%rip),%rbx # 6cd1a0 <_nl_domain_bindings> - 402cc2: 48 85 db test %rbx,%rbx - 402cc5: 0f 84 6a 02 00 00 je 402f35 <__dcigettext+0x3c5> - 402ccb: 4c 8b a5 60 ff ff ff mov -0xa0(%rbp),%r12 - 402cd2: eb 16 jmp 402cea <__dcigettext+0x17a> - 402cd4: 0f 1f 40 00 nopl 0x0(%rax) - 402cd8: 0f 88 55 02 00 00 js 402f33 <__dcigettext+0x3c3> - 402cde: 48 8b 1b mov (%rbx),%rbx - 402ce1: 48 85 db test %rbx,%rbx - 402ce4: 0f 84 4b 02 00 00 je 402f35 <__dcigettext+0x3c5> - 402cea: 48 8d 73 18 lea 0x18(%rbx),%rsi - 402cee: 4c 89 e7 mov %r12,%rdi - 402cf1: e8 6a d6 ff ff callq 400360 <__rela_iplt_end+0x98> - 402cf6: 85 c0 test %eax,%eax - 402cf8: 75 de jne 402cd8 <__dcigettext+0x168> - 402cfa: 48 8b 43 08 mov 0x8(%rbx),%rax - 402cfe: 80 38 2f cmpb $0x2f,(%rax) - 402d01: 48 89 85 78 ff ff ff mov %rax,-0x88(%rbp) - 402d08: 0f 84 8d 00 00 00 je 402d9b <__dcigettext+0x22b> - 402d0e: 48 89 c7 mov %rax,%rdi - 402d11: 41 bd 02 10 00 00 mov $0x1002,%r13d - 402d17: e8 34 09 02 00 callq 423650 - 402d1c: 4c 8d 78 01 lea 0x1(%rax),%r15 - 402d20: eb 22 jmp 402d44 <__dcigettext+0x1d4> - 402d22: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 402d28: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 402d2f: 64 83 38 22 cmpl $0x22,%fs:(%rax) - 402d33: 0f 85 a2 01 00 00 jne 402edb <__dcigettext+0x36b> - 402d39: 4c 89 e8 mov %r13,%rax - 402d3c: 48 d1 e8 shr %rax - 402d3f: 4d 8d 6c 05 20 lea 0x20(%r13,%rax,1),%r13 - 402d44: 4b 8d 44 3d 1e lea 0x1e(%r13,%r15,1),%rax - 402d49: 4c 89 ee mov %r13,%rsi - 402d4c: 48 83 e0 f0 and $0xfffffffffffffff0,%rax - 402d50: 48 29 c4 sub %rax,%rsp - 402d53: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 402d5a: 4c 8d 64 24 0f lea 0xf(%rsp),%r12 - 402d5f: 49 83 e4 f0 and $0xfffffffffffffff0,%r12 - 402d63: 64 c7 00 00 00 00 00 movl $0x0,%fs:(%rax) - 402d6a: 4c 89 e7 mov %r12,%rdi - 402d6d: e8 5e c6 03 00 callq 43f3d0 <__getcwd> - 402d72: 48 85 c0 test %rax,%rax - 402d75: 74 b1 je 402d28 <__dcigettext+0x1b8> - 402d77: 31 f6 xor %esi,%esi - 402d79: 4c 89 e7 mov %r12,%rdi - 402d7c: e8 4f 9c 02 00 callq 42c9d0 <__rawmemchr> - 402d81: 48 8b b5 78 ff ff ff mov -0x88(%rbp),%rsi - 402d88: 48 8d 78 01 lea 0x1(%rax),%rdi - 402d8c: c6 00 2f movb $0x2f,(%rax) - 402d8f: e8 5c d5 ff ff callq 4002f0 <__rela_iplt_end+0x28> - 402d94: 4c 89 a5 78 ff ff ff mov %r12,-0x88(%rbp) - 402d9b: 8b bd 5c ff ff ff mov -0xa4(%rbp),%edi - 402da1: 48 63 c7 movslq %edi,%rax - 402da4: 44 0f b6 a0 b8 5f 4a movzbl 0x4a5fb8(%rax),%r12d - 402dab: 00 - 402dac: e8 7f c5 04 00 callq 44f330 <__current_locale_name> - 402db1: 49 89 c5 mov %rax,%r13 - 402db4: 49 81 c4 e0 5f 4a 00 add $0x4a5fe0,%r12 - 402dbb: 80 38 43 cmpb $0x43,(%rax) - 402dbe: 0f 85 81 01 00 00 jne 402f45 <__dcigettext+0x3d5> - 402dc4: 80 78 01 00 cmpb $0x0,0x1(%rax) - 402dc8: 0f 85 77 01 00 00 jne 402f45 <__dcigettext+0x3d5> - 402dce: 4c 8b bd 60 ff ff ff mov -0xa0(%rbp),%r15 - 402dd5: 4c 89 ff mov %r15,%rdi - 402dd8: e8 73 08 02 00 callq 423650 - 402ddd: 4c 89 e7 mov %r12,%rdi - 402de0: 49 89 c6 mov %rax,%r14 - 402de3: 48 89 85 20 ff ff ff mov %rax,-0xe0(%rbp) - 402dea: e8 61 08 02 00 callq 423650 - 402def: 49 8d 44 06 23 lea 0x23(%r14,%rax,1),%rax - 402df4: 4c 89 e6 mov %r12,%rsi - 402df7: 48 83 e0 f0 and $0xfffffffffffffff0,%rax - 402dfb: 48 29 c4 sub %rax,%rsp - 402dfe: 48 8d 44 24 0f lea 0xf(%rsp),%rax - 402e03: 48 83 e0 f0 and $0xfffffffffffffff0,%rax - 402e07: 48 89 c7 mov %rax,%rdi - 402e0a: 48 89 85 68 ff ff ff mov %rax,-0x98(%rbp) - 402e11: e8 fa d4 ff ff callq 400310 <__rela_iplt_end+0x48> - 402e16: b9 2f 00 00 00 mov $0x2f,%ecx - 402e1b: 48 8d 78 01 lea 0x1(%rax),%rdi - 402e1f: 4c 89 f2 mov %r14,%rdx - 402e22: 66 89 08 mov %cx,(%rax) - 402e25: 4c 89 fe mov %r15,%rsi - 402e28: e8 93 37 02 00 callq 4265c0 <__mempcpy> - 402e2d: 4c 89 ef mov %r13,%rdi - 402e30: c7 00 2e 6d 6f 00 movl $0x6f6d2e,(%rax) - 402e36: e8 15 08 02 00 callq 423650 - 402e3b: 48 83 c0 1f add $0x1f,%rax - 402e3f: 48 83 e0 f0 and $0xfffffffffffffff0,%rax - 402e43: 48 29 c4 sub %rax,%rsp - 402e46: 4c 8d 64 24 0f lea 0xf(%rsp),%r12 - 402e4b: 49 83 e4 f0 and $0xfffffffffffffff0,%r12 - 402e4f: 90 nop - 402e50: 41 0f b6 45 00 movzbl 0x0(%r13),%eax - 402e55: 3c 3a cmp $0x3a,%al - 402e57: 0f 84 73 01 00 00 je 402fd0 <__dcigettext+0x460> - 402e5d: 84 c0 test %al,%al - 402e5f: 0f 85 0b 01 00 00 jne 402f70 <__dcigettext+0x400> - 402e65: 41 c6 04 24 43 movb $0x43,(%r12) - 402e6a: 41 c6 44 24 01 00 movb $0x0,0x1(%r12) - 402e70: 41 80 7c 24 01 00 cmpb $0x0,0x1(%r12) - 402e76: 74 63 je 402edb <__dcigettext+0x36b> - 402e78: bf 99 11 4a 00 mov $0x4a1199,%edi - 402e7d: b9 06 00 00 00 mov $0x6,%ecx - 402e82: 4c 89 e6 mov %r12,%rsi - 402e85: f3 a6 repz cmpsb %es:(%rdi),%ds:(%rsi) - 402e87: 74 52 je 402edb <__dcigettext+0x36b> - 402e89: 48 8b 95 68 ff ff ff mov -0x98(%rbp),%rdx - 402e90: 48 8b bd 78 ff ff ff mov -0x88(%rbp),%rdi - 402e97: 48 89 d9 mov %rbx,%rcx - 402e9a: 4c 89 e6 mov %r12,%rsi - 402e9d: e8 2e 06 00 00 callq 4034d0 <_nl_find_domain> - 402ea2: 48 85 c0 test %rax,%rax - 402ea5: 49 89 c7 mov %rax,%r15 - 402ea8: 74 a6 je 402e50 <__dcigettext+0x2e0> - 402eaa: 48 8b 95 70 ff ff ff mov -0x90(%rbp),%rdx - 402eb1: 4c 8d 45 88 lea -0x78(%rbp),%r8 - 402eb5: b9 01 00 00 00 mov $0x1,%ecx - 402eba: 48 89 de mov %rbx,%rsi - 402ebd: 48 89 c7 mov %rax,%rdi - 402ec0: e8 8b f0 ff ff callq 401f50 <_nl_find_msg> - 402ec5: 48 85 c0 test %rax,%rax - 402ec8: 0f 84 12 01 00 00 je 402fe0 <__dcigettext+0x470> - 402ece: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 402ed2: 48 89 c1 mov %rax,%rcx - 402ed5: 0f 85 2f 02 00 00 jne 40310a <__dcigettext+0x59a> - 402edb: b8 00 00 00 00 mov $0x0,%eax - 402ee0: 48 85 c0 test %rax,%rax - 402ee3: 74 11 je 402ef6 <__dcigettext+0x386> - 402ee5: bf e0 bf 6c 00 mov $0x6cbfe0,%edi - 402eea: ff d0 callq *%rax - 402eec: bf 20 c7 6c 00 mov $0x6cc720,%edi - 402ef1: e8 0a d1 bf ff callq 0 <_nl_current_LC_CTYPE> - 402ef6: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 402efd: 8b 8d 3c ff ff ff mov -0xc4(%rbp),%ecx - 402f03: 64 89 08 mov %ecx,%fs:(%rax) - 402f06: 48 83 bd 50 ff ff ff cmpq $0x1,-0xb0(%rbp) - 402f0d: 01 - 402f0e: 74 54 je 402f64 <__dcigettext+0x3f4> - 402f10: 8b bd 58 ff ff ff mov -0xa8(%rbp),%edi - 402f16: 4c 8b ad 48 ff ff ff mov -0xb8(%rbp),%r13 - 402f1d: 85 ff test %edi,%edi - 402f1f: 74 43 je 402f64 <__dcigettext+0x3f4> - 402f21: 48 8d 65 d8 lea -0x28(%rbp),%rsp - 402f25: 4c 89 e8 mov %r13,%rax - 402f28: 5b pop %rbx - 402f29: 41 5c pop %r12 - 402f2b: 41 5d pop %r13 - 402f2d: 41 5e pop %r14 - 402f2f: 41 5f pop %r15 - 402f31: 5d pop %rbp - 402f32: c3 retq - 402f33: 31 db xor %ebx,%ebx - 402f35: 48 c7 85 78 ff ff ff movq $0x4a11a0,-0x88(%rbp) - 402f3c: a0 11 4a 00 - 402f40: e9 56 fe ff ff jmpq 402d9b <__dcigettext+0x22b> - 402f45: bf 90 11 4a 00 mov $0x4a1190,%edi - 402f4a: e8 91 b8 00 00 callq 40e7e0 - 402f4f: 48 85 c0 test %rax,%rax - 402f52: 0f 84 76 fe ff ff je 402dce <__dcigettext+0x25e> - 402f58: 80 38 00 cmpb $0x0,(%rax) - 402f5b: 4c 0f 45 e8 cmovne %rax,%r13 - 402f5f: e9 6a fe ff ff jmpq 402dce <__dcigettext+0x25e> - 402f64: 4c 8b ad 70 ff ff ff mov -0x90(%rbp),%r13 - 402f6b: eb b4 jmp 402f21 <__dcigettext+0x3b1> - 402f6d: 0f 1f 00 nopl (%rax) - 402f70: 4c 89 e2 mov %r12,%rdx - 402f73: eb 07 jmp 402f7c <__dcigettext+0x40c> - 402f75: 0f 1f 00 nopl (%rax) - 402f78: 3c 3a cmp $0x3a,%al - 402f7a: 74 14 je 402f90 <__dcigettext+0x420> - 402f7c: 48 83 c2 01 add $0x1,%rdx - 402f80: 49 83 c5 01 add $0x1,%r13 - 402f84: 88 42 ff mov %al,-0x1(%rdx) - 402f87: 41 0f b6 45 00 movzbl 0x0(%r13),%eax - 402f8c: 84 c0 test %al,%al - 402f8e: 75 e8 jne 402f78 <__dcigettext+0x408> - 402f90: c6 02 00 movb $0x0,(%rdx) - 402f93: 8b 15 ff 6f 2c 00 mov 0x2c6fff(%rip),%edx # 6c9f98 <__libc_enable_secure> - 402f99: 85 d2 test %edx,%edx - 402f9b: 74 1b je 402fb8 <__dcigettext+0x448> - 402f9d: be 2f 00 00 00 mov $0x2f,%esi - 402fa2: 4c 89 e7 mov %r12,%rdi - 402fa5: e8 d6 d3 ff ff callq 400380 <__rela_iplt_end+0xb8> - 402faa: 48 85 c0 test %rax,%rax - 402fad: 0f 85 9d fe ff ff jne 402e50 <__dcigettext+0x2e0> - 402fb3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 402fb8: 41 0f b6 04 24 movzbl (%r12),%eax - 402fbd: 3c 43 cmp $0x43,%al - 402fbf: 0f 85 b3 fe ff ff jne 402e78 <__dcigettext+0x308> - 402fc5: e9 a6 fe ff ff jmpq 402e70 <__dcigettext+0x300> - 402fca: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 402fd0: 49 83 c5 01 add $0x1,%r13 - 402fd4: e9 77 fe ff ff jmpq 402e50 <__dcigettext+0x2e0> - 402fd9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 402fe0: 49 8b 7f 20 mov 0x20(%r15),%rdi - 402fe4: 48 85 ff test %rdi,%rdi - 402fe7: 0f 84 63 fe ff ff je 402e50 <__dcigettext+0x2e0> - 402fed: 45 31 f6 xor %r14d,%r14d - 402ff0: 4c 89 ad 28 ff ff ff mov %r13,-0xd8(%rbp) - 402ff7: 45 89 f5 mov %r14d,%r13d - 402ffa: 4d 89 e6 mov %r12,%r14 - 402ffd: 4c 8b a5 70 ff ff ff mov -0x90(%rbp),%r12 - 403004: eb 28 jmp 40302e <__dcigettext+0x4be> - 403006: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 40300d: 00 00 00 - 403010: 48 85 c0 test %rax,%rax - 403013: 0f 85 e6 00 00 00 jne 4030ff <__dcigettext+0x58f> - 403019: 41 83 c5 01 add $0x1,%r13d - 40301d: 49 63 c5 movslq %r13d,%rax - 403020: 49 8b 7c c7 20 mov 0x20(%r15,%rax,8),%rdi - 403025: 48 85 ff test %rdi,%rdi - 403028: 0f 84 58 01 00 00 je 403186 <__dcigettext+0x616> - 40302e: 4c 8d 45 88 lea -0x78(%rbp),%r8 - 403032: b9 01 00 00 00 mov $0x1,%ecx - 403037: 4c 89 e2 mov %r12,%rdx - 40303a: 48 89 de mov %rbx,%rsi - 40303d: e8 0e ef ff ff callq 401f50 <_nl_find_msg> - 403042: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 403046: 75 c8 jne 403010 <__dcigettext+0x4a0> - 403048: e9 8e fe ff ff jmpq 402edb <__dcigettext+0x36b> - 40304d: 48 83 bd 60 ff ff ff cmpq $0x0,-0xa0(%rbp) - 403054: 00 - 403055: 0f 84 3a 01 00 00 je 403195 <__dcigettext+0x625> - 40305b: 48 8b 85 60 ff ff ff mov -0xa0(%rbp),%rax - 403062: 48 89 75 c8 mov %rsi,-0x38(%rbp) - 403066: 48 c7 45 b0 00 00 00 movq $0x0,-0x50(%rbp) - 40306d: 00 - 40306e: 48 89 45 90 mov %rax,-0x70(%rbp) - 403072: 8b 85 5c ff ff ff mov -0xa4(%rbp),%eax - 403078: 89 c7 mov %eax,%edi - 40307a: 89 45 98 mov %eax,-0x68(%rbp) - 40307d: e8 ae c2 04 00 callq 44f330 <__current_locale_name> - 403082: 48 89 c7 mov %rax,%rdi - 403085: 48 89 c3 mov %rax,%rbx - 403088: e8 c3 05 02 00 callq 423650 - 40308d: 48 8d 50 01 lea 0x1(%rax),%rdx - 403091: 48 83 c0 1f add $0x1f,%rax - 403095: 48 89 de mov %rbx,%rsi - 403098: 48 83 e0 f0 and $0xfffffffffffffff0,%rax - 40309c: 48 29 c4 sub %rax,%rsp - 40309f: 48 8d 7c 24 0f lea 0xf(%rsp),%rdi - 4030a4: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi - 4030a8: e8 73 8f 02 00 callq 42c020 - 4030ad: 48 89 85 30 ff ff ff mov %rax,-0xd0(%rbp) - 4030b4: 48 89 45 a0 mov %rax,-0x60(%rbp) - 4030b8: e9 b5 fb ff ff jmpq 402c72 <__dcigettext+0x102> - 4030bd: 8b b5 58 ff ff ff mov -0xa8(%rbp),%esi - 4030c3: 85 f6 test %esi,%esi - 4030c5: 0f 85 1d 03 00 00 jne 4033e8 <__dcigettext+0x878> - 4030cb: 4c 8b 68 28 mov 0x28(%rax),%r13 - 4030cf: b8 00 00 00 00 mov $0x0,%eax - 4030d4: 48 85 c0 test %rax,%rax - 4030d7: 74 11 je 4030ea <__dcigettext+0x57a> - 4030d9: bf e0 bf 6c 00 mov $0x6cbfe0,%edi - 4030de: ff d0 callq *%rax - 4030e0: bf 20 c7 6c 00 mov $0x6cc720,%edi - 4030e5: e8 16 cf bf ff callq 0 <_nl_current_LC_CTYPE> - 4030ea: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 4030f1: 8b 8d 3c ff ff ff mov -0xc4(%rbp),%ecx - 4030f7: 64 89 08 mov %ecx,%fs:(%rax) - 4030fa: e9 22 fe ff ff jmpq 402f21 <__dcigettext+0x3b1> - 4030ff: 4d 63 d5 movslq %r13d,%r10 - 403102: 48 89 c1 mov %rax,%rcx - 403105: 4f 8b 7c d7 20 mov 0x20(%r15,%r10,8),%r15 - 40310a: 48 83 bd 40 ff ff ff cmpq $0x0,-0xc0(%rbp) - 403111: 00 - 403112: 0f 84 f6 00 00 00 je 40320e <__dcigettext+0x69e> - 403118: 48 8b 9d 40 ff ff ff mov -0xc0(%rbp),%rbx - 40311f: 8b 15 83 a0 2c 00 mov 0x2ca083(%rip),%edx # 6cd1a8 <_nl_msg_cat_cntr> - 403125: 48 8b 03 mov (%rbx),%rax - 403128: 89 50 18 mov %edx,0x18(%rax) - 40312b: 4c 89 78 20 mov %r15,0x20(%rax) - 40312f: 48 8b 03 mov (%rbx),%rax - 403132: 48 8b 55 88 mov -0x78(%rbp),%rdx - 403136: 48 89 48 28 mov %rcx,0x28(%rax) - 40313a: 48 8b 03 mov (%rbx),%rax - 40313d: 48 89 50 30 mov %rdx,0x30(%rax) - 403141: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 403148: 8b 9d 3c ff ff ff mov -0xc4(%rbp),%ebx - 40314e: 64 89 18 mov %ebx,%fs:(%rax) - 403151: 8b 85 58 ff ff ff mov -0xa8(%rbp),%eax - 403157: 85 c0 test %eax,%eax - 403159: 0f 85 f9 02 00 00 jne 403458 <__dcigettext+0x8e8> - 40315f: b8 00 00 00 00 mov $0x0,%eax - 403164: 49 89 cd mov %rcx,%r13 - 403167: 48 85 c0 test %rax,%rax - 40316a: 0f 84 b1 fd ff ff je 402f21 <__dcigettext+0x3b1> - 403170: bf e0 bf 6c 00 mov $0x6cbfe0,%edi - 403175: ff d0 callq *%rax - 403177: bf 20 c7 6c 00 mov $0x6cc720,%edi - 40317c: e8 7f ce bf ff callq 0 <_nl_current_LC_CTYPE> - 403181: e9 9b fd ff ff jmpq 402f21 <__dcigettext+0x3b1> - 403186: 4c 8b ad 28 ff ff ff mov -0xd8(%rbp),%r13 - 40318d: 4d 89 f4 mov %r14,%r12 - 403190: e9 bb fc ff ff jmpq 402e50 <__dcigettext+0x2e0> - 403195: 48 8b 05 fc 6e 2c 00 mov 0x2c6efc(%rip),%rax # 6ca098 <_nl_current_default_domain> - 40319c: 48 8b 8d 70 ff ff ff mov -0x90(%rbp),%rcx - 4031a3: 48 c7 45 b0 00 00 00 movq $0x0,-0x50(%rbp) - 4031aa: 00 - 4031ab: 48 89 85 60 ff ff ff mov %rax,-0xa0(%rbp) - 4031b2: 48 89 45 90 mov %rax,-0x70(%rbp) - 4031b6: 8b 85 5c ff ff ff mov -0xa4(%rbp),%eax - 4031bc: 48 89 4d c8 mov %rcx,-0x38(%rbp) - 4031c0: 89 c7 mov %eax,%edi - 4031c2: 89 45 98 mov %eax,-0x68(%rbp) - 4031c5: e8 66 c1 04 00 callq 44f330 <__current_locale_name> - 4031ca: 48 89 c7 mov %rax,%rdi - 4031cd: 49 89 c4 mov %rax,%r12 - 4031d0: e8 7b 04 02 00 callq 423650 - 4031d5: 48 8d 50 01 lea 0x1(%rax),%rdx - 4031d9: 48 83 c0 1f add $0x1f,%rax - 4031dd: 4c 89 e6 mov %r12,%rsi - 4031e0: 48 83 e0 f0 and $0xfffffffffffffff0,%rax - 4031e4: 48 29 c4 sub %rax,%rsp - 4031e7: 48 8d 7c 24 0f lea 0xf(%rsp),%rdi - 4031ec: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi - 4031f0: e8 2b 8e 02 00 callq 42c020 - 4031f5: 48 85 db test %rbx,%rbx - 4031f8: 48 89 85 30 ff ff ff mov %rax,-0xd0(%rbp) - 4031ff: 48 89 45 a0 mov %rax,-0x60(%rbp) - 403203: 0f 85 5f fa ff ff jne 402c68 <__dcigettext+0xf8> - 403209: e9 64 fa ff ff jmpq 402c72 <__dcigettext+0x102> - 40320e: 48 8b bd 70 ff ff ff mov -0x90(%rbp),%rdi - 403215: 48 89 8d 78 ff ff ff mov %rcx,-0x88(%rbp) - 40321c: e8 2f 04 02 00 callq 423650 - 403221: 4c 8b a5 30 ff ff ff mov -0xd0(%rbp),%r12 - 403228: 48 8b 8d 78 ff ff ff mov -0x88(%rbp),%rcx - 40322f: 48 8d 58 01 lea 0x1(%rax),%rbx - 403233: 41 8b 14 24 mov (%r12),%edx - 403237: 49 83 c4 04 add $0x4,%r12 - 40323b: 8d 82 ff fe fe fe lea -0x1010101(%rdx),%eax - 403241: f7 d2 not %edx - 403243: 21 d0 and %edx,%eax - 403245: 25 80 80 80 80 and $0x80808080,%eax - 40324a: 74 e7 je 403233 <__dcigettext+0x6c3> - 40324c: 89 c2 mov %eax,%edx - 40324e: 48 89 8d 78 ff ff ff mov %rcx,-0x88(%rbp) - 403255: 4c 8b b5 20 ff ff ff mov -0xe0(%rbp),%r14 - 40325c: c1 ea 10 shr $0x10,%edx - 40325f: a9 80 80 00 00 test $0x8080,%eax - 403264: 0f 44 c2 cmove %edx,%eax - 403267: 49 8d 54 24 02 lea 0x2(%r12),%rdx - 40326c: 89 c1 mov %eax,%ecx - 40326e: 4c 0f 44 e2 cmove %rdx,%r12 - 403272: 00 c1 add %al,%cl - 403274: 49 83 dc 03 sbb $0x3,%r12 - 403278: 4c 2b a5 30 ff ff ff sub -0xd0(%rbp),%r12 - 40327f: 4b 8d 7c 34 3a lea 0x3a(%r12,%r14,1),%rdi - 403284: 48 01 df add %rbx,%rdi - 403287: e8 84 a7 01 00 callq 41da10 <__libc_malloc> - 40328c: 48 85 c0 test %rax,%rax - 40328f: 48 8b 8d 78 ff ff ff mov -0x88(%rbp),%rcx - 403296: 0f 84 a5 fe ff ff je 403141 <__dcigettext+0x5d1> - 40329c: 48 8b b5 70 ff ff ff mov -0x90(%rbp),%rsi - 4032a3: 48 8d 78 38 lea 0x38(%rax),%rdi - 4032a7: 48 89 da mov %rbx,%rdx - 4032aa: 48 89 8d 68 ff ff ff mov %rcx,-0x98(%rbp) - 4032b1: 48 89 85 78 ff ff ff mov %rax,-0x88(%rbp) - 4032b8: e8 03 33 02 00 callq 4265c0 <__mempcpy> - 4032bd: 48 8b b5 60 ff ff ff mov -0xa0(%rbp),%rsi - 4032c4: 48 89 c3 mov %rax,%rbx - 4032c7: 4c 89 f0 mov %r14,%rax - 4032ca: 48 83 c0 01 add $0x1,%rax - 4032ce: 48 89 df mov %rbx,%rdi - 4032d1: 49 89 c5 mov %rax,%r13 - 4032d4: 48 89 c2 mov %rax,%rdx - 4032d7: e8 44 8d 02 00 callq 42c020 - 4032dc: 4e 8d 0c 2b lea (%rbx,%r13,1),%r9 - 4032e0: 48 8b b5 30 ff ff ff mov -0xd0(%rbp),%rsi - 4032e7: 49 8d 54 24 01 lea 0x1(%r12),%rdx - 4032ec: 4c 89 cf mov %r9,%rdi - 4032ef: e8 2c 8d 02 00 callq 42c020 - 4032f4: 4c 8b 85 78 ff ff ff mov -0x88(%rbp),%r8 - 4032fb: 49 89 c1 mov %rax,%r9 - 4032fe: 8b 85 5c ff ff ff mov -0xa4(%rbp),%eax - 403304: 48 8b 8d 68 ff ff ff mov -0x98(%rbp),%rcx - 40330b: 41 89 40 08 mov %eax,0x8(%r8) - 40330f: 8b 05 93 9e 2c 00 mov 0x2c9e93(%rip),%eax # 6cd1a8 <_nl_msg_cat_cntr> - 403315: 49 89 18 mov %rbx,(%r8) - 403318: 4d 89 48 10 mov %r9,0x10(%r8) - 40331c: 4d 89 78 20 mov %r15,0x20(%r8) - 403320: 49 89 48 28 mov %rcx,0x28(%r8) - 403324: 41 89 40 18 mov %eax,0x18(%r8) - 403328: 48 8b 45 88 mov -0x78(%rbp),%rax - 40332c: 49 89 40 30 mov %rax,0x30(%r8) - 403330: b8 00 00 00 00 mov $0x0,%eax - 403335: 48 85 c0 test %rax,%rax - 403338: 74 23 je 40335d <__dcigettext+0x7ed> - 40333a: 4c 89 85 70 ff ff ff mov %r8,-0x90(%rbp) - 403341: 48 89 8d 78 ff ff ff mov %rcx,-0x88(%rbp) - 403348: bf 60 c0 6c 00 mov $0x6cc060,%edi - 40334d: ff d0 callq *%rax - 40334f: 4c 8b 85 70 ff ff ff mov -0x90(%rbp),%r8 - 403356: 48 8b 8d 78 ff ff ff mov -0x88(%rbp),%rcx - 40335d: 4c 89 c7 mov %r8,%rdi - 403360: ba 90 17 40 00 mov $0x401790,%edx - 403365: be 48 c0 6c 00 mov $0x6cc048,%esi - 40336a: 48 89 8d 70 ff ff ff mov %rcx,-0x90(%rbp) - 403371: 4c 89 85 78 ff ff ff mov %r8,-0x88(%rbp) - 403378: e8 23 cf 03 00 callq 4402a0 <__tsearch> - 40337d: 48 89 c3 mov %rax,%rbx - 403380: b8 00 00 00 00 mov $0x0,%eax - 403385: 4c 8b 85 78 ff ff ff mov -0x88(%rbp),%r8 - 40338c: 48 85 c0 test %rax,%rax - 40338f: 48 8b 8d 70 ff ff ff mov -0x90(%rbp),%rcx - 403396: 74 23 je 4033bb <__dcigettext+0x84b> - 403398: 4c 89 85 70 ff ff ff mov %r8,-0x90(%rbp) - 40339f: 48 89 8d 78 ff ff ff mov %rcx,-0x88(%rbp) - 4033a6: bf 60 c0 6c 00 mov $0x6cc060,%edi - 4033ab: ff d0 callq *%rax - 4033ad: 4c 8b 85 70 ff ff ff mov -0x90(%rbp),%r8 - 4033b4: 48 8b 8d 78 ff ff ff mov -0x88(%rbp),%rcx - 4033bb: 48 85 db test %rbx,%rbx - 4033be: 74 09 je 4033c9 <__dcigettext+0x859> - 4033c0: 4c 3b 03 cmp (%rbx),%r8 - 4033c3: 0f 84 78 fd ff ff je 403141 <__dcigettext+0x5d1> - 4033c9: 4c 89 c7 mov %r8,%rdi - 4033cc: 48 89 8d 78 ff ff ff mov %rcx,-0x88(%rbp) - 4033d3: e8 d8 a9 01 00 callq 41ddb0 <__cfree> - 4033d8: 48 8b 8d 78 ff ff ff mov -0x88(%rbp),%rcx - 4033df: e9 5d fd ff ff jmpq 403141 <__dcigettext+0x5d1> - 4033e4: 0f 1f 40 00 nopl 0x0(%rax) - 4033e8: 48 8b 58 30 mov 0x30(%rax),%rbx - 4033ec: 4c 8b 68 28 mov 0x28(%rax),%r13 - 4033f0: 48 8b 40 20 mov 0x20(%rax),%rax - 4033f4: 48 8b b5 50 ff ff ff mov -0xb0(%rbp),%rsi - 4033fb: 4c 8b 60 10 mov 0x10(%rax),%r12 - 4033ff: 49 8b bc 24 b8 00 00 mov 0xb8(%r12),%rdi - 403406: 00 - 403407: e8 04 e4 ff ff callq 401810 - 40340c: 49 3b 84 24 c0 00 00 cmp 0xc0(%r12),%rax - 403413: 00 - 403414: 0f 83 b5 fc ff ff jae 4030cf <__dcigettext+0x55f> - 40341a: 4c 89 ef mov %r13,%rdi - 40341d: 49 89 c4 mov %rax,%r12 - 403420: 4c 01 eb add %r13,%rbx - 403423: eb 1b jmp 403440 <__dcigettext+0x8d0> - 403425: 0f 1f 00 nopl (%rax) - 403428: 31 f6 xor %esi,%esi - 40342a: 49 83 ec 01 sub $0x1,%r12 - 40342e: e8 9d 95 02 00 callq 42c9d0 <__rawmemchr> - 403433: 48 8d 78 01 lea 0x1(%rax),%rdi - 403437: 48 39 df cmp %rbx,%rdi - 40343a: 0f 83 8f fc ff ff jae 4030cf <__dcigettext+0x55f> - 403440: 4d 85 e4 test %r12,%r12 - 403443: 75 e3 jne 403428 <__dcigettext+0x8b8> - 403445: 49 89 fd mov %rdi,%r13 - 403448: e9 82 fc ff ff jmpq 4030cf <__dcigettext+0x55f> - 40344d: 0f 1f 00 nopl (%rax) - 403450: 45 31 ed xor %r13d,%r13d - 403453: e9 c9 fa ff ff jmpq 402f21 <__dcigettext+0x3b1> - 403458: 4d 8b 67 10 mov 0x10(%r15),%r12 - 40345c: 48 8b b5 50 ff ff ff mov -0xb0(%rbp),%rsi - 403463: 48 89 8d 78 ff ff ff mov %rcx,-0x88(%rbp) - 40346a: 48 8b 5d 88 mov -0x78(%rbp),%rbx - 40346e: 49 8b bc 24 b8 00 00 mov 0xb8(%r12),%rdi - 403475: 00 - 403476: e8 95 e3 ff ff callq 401810 - 40347b: 49 3b 84 24 c0 00 00 cmp 0xc0(%r12),%rax - 403482: 00 - 403483: 48 8b 8d 78 ff ff ff mov -0x88(%rbp),%rcx - 40348a: 0f 83 cf fc ff ff jae 40315f <__dcigettext+0x5ef> - 403490: 48 89 cf mov %rcx,%rdi - 403493: 49 89 c4 mov %rax,%r12 - 403496: 48 01 cb add %rcx,%rbx - 403499: 49 89 cd mov %rcx,%r13 - 40349c: 4d 85 e4 test %r12,%r12 - 40349f: 74 1c je 4034bd <__dcigettext+0x94d> - 4034a1: 31 f6 xor %esi,%esi - 4034a3: 49 83 ec 01 sub $0x1,%r12 - 4034a7: e8 24 95 02 00 callq 42c9d0 <__rawmemchr> - 4034ac: 48 8d 78 01 lea 0x1(%rax),%rdi - 4034b0: 48 39 df cmp %rbx,%rdi - 4034b3: 72 e7 jb 40349c <__dcigettext+0x92c> - 4034b5: 4c 89 e9 mov %r13,%rcx - 4034b8: e9 a2 fc ff ff jmpq 40315f <__dcigettext+0x5ef> - 4034bd: 48 89 f9 mov %rdi,%rcx - 4034c0: e9 9a fc ff ff jmpq 40315f <__dcigettext+0x5ef> - 4034c5: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4034cc: 00 00 00 - 4034cf: 90 nop - -00000000004034d0 <_nl_find_domain>: - 4034d0: 41 57 push %r15 - 4034d2: 41 56 push %r14 - 4034d4: b8 00 00 00 00 mov $0x0,%eax - 4034d9: 41 55 push %r13 - 4034db: 41 54 push %r12 - 4034dd: 49 89 f5 mov %rsi,%r13 - 4034e0: 55 push %rbp - 4034e1: 53 push %rbx - 4034e2: 48 89 fd mov %rdi,%rbp - 4034e5: 49 89 d6 mov %rdx,%r14 - 4034e8: 49 89 cc mov %rcx,%r12 - 4034eb: 48 83 ec 48 sub $0x48,%rsp - 4034ef: 48 85 c0 test %rax,%rax - 4034f2: 74 07 je 4034fb <_nl_find_domain+0x2b> - 4034f4: bf a0 c0 6c 00 mov $0x6cc0a0,%edi - 4034f9: ff d0 callq *%rax - 4034fb: 48 89 ef mov %rbp,%rdi - 4034fe: 41 bf 00 00 00 00 mov $0x0,%r15d - 403504: e8 47 01 02 00 callq 423650 - 403509: 48 83 ec 08 sub $0x8,%rsp - 40350d: 48 8d 50 01 lea 0x1(%rax),%rdx - 403511: 45 31 c9 xor %r9d,%r9d - 403514: 6a 00 pushq $0x0 - 403516: 41 56 push %r14 - 403518: 31 c9 xor %ecx,%ecx - 40351a: 6a 00 pushq $0x0 - 40351c: 6a 00 pushq $0x0 - 40351e: 4d 89 e8 mov %r13,%r8 - 403521: 6a 00 pushq $0x0 - 403523: 48 89 ee mov %rbp,%rsi - 403526: bf d8 c0 6c 00 mov $0x6cc0d8,%edi - 40352b: e8 b0 1d 00 00 callq 4052e0 <_nl_make_l10nflist> - 403530: 48 83 c4 30 add $0x30,%rsp - 403534: 4d 85 ff test %r15,%r15 - 403537: 48 89 c3 mov %rax,%rbx - 40353a: 74 08 je 403544 <_nl_find_domain+0x74> - 40353c: bf a0 c0 6c 00 mov $0x6cc0a0,%edi - 403541: 41 ff d7 callq *%r15 - 403544: 48 85 db test %rbx,%rbx - 403547: 0f 84 93 00 00 00 je 4035e0 <_nl_find_domain+0x110> - 40354d: 8b 73 08 mov 0x8(%rbx),%esi - 403550: 85 f6 test %esi,%esi - 403552: 7e 74 jle 4035c8 <_nl_find_domain+0xf8> - 403554: 48 83 7b 10 00 cmpq $0x0,0x10(%rbx) - 403559: 48 89 d8 mov %rbx,%rax - 40355c: 74 12 je 403570 <_nl_find_domain+0xa0> - 40355e: 48 83 c4 48 add $0x48,%rsp - 403562: 5b pop %rbx - 403563: 5d pop %rbp - 403564: 41 5c pop %r12 - 403566: 41 5d pop %r13 - 403568: 41 5e pop %r14 - 40356a: 41 5f pop %r15 - 40356c: c3 retq - 40356d: 0f 1f 00 nopl (%rax) - 403570: 48 8b 7b 20 mov 0x20(%rbx),%rdi - 403574: 48 85 ff test %rdi,%rdi - 403577: 74 e5 je 40355e <_nl_find_domain+0x8e> - 403579: 31 ed xor %ebp,%ebp - 40357b: eb 1a jmp 403597 <_nl_find_domain+0xc7> - 40357d: 0f 1f 00 nopl (%rax) - 403580: 48 83 7f 10 00 cmpq $0x0,0x10(%rdi) - 403585: 75 29 jne 4035b0 <_nl_find_domain+0xe0> - 403587: 83 c5 01 add $0x1,%ebp - 40358a: 48 63 c5 movslq %ebp,%rax - 40358d: 48 8b 7c c3 20 mov 0x20(%rbx,%rax,8),%rdi - 403592: 48 85 ff test %rdi,%rdi - 403595: 74 19 je 4035b0 <_nl_find_domain+0xe0> - 403597: 8b 4f 08 mov 0x8(%rdi),%ecx - 40359a: 85 c9 test %ecx,%ecx - 40359c: 7f e2 jg 403580 <_nl_find_domain+0xb0> - 40359e: 4c 89 e6 mov %r12,%rsi - 4035a1: e8 9a 01 00 00 callq 403740 <_nl_load_domain> - 4035a6: 48 63 c5 movslq %ebp,%rax - 4035a9: 48 8b 7c c3 20 mov 0x20(%rbx,%rax,8),%rdi - 4035ae: eb d0 jmp 403580 <_nl_find_domain+0xb0> - 4035b0: 48 83 c4 48 add $0x48,%rsp - 4035b4: 48 89 d8 mov %rbx,%rax - 4035b7: 5b pop %rbx - 4035b8: 5d pop %rbp - 4035b9: 41 5c pop %r12 - 4035bb: 41 5d pop %r13 - 4035bd: 41 5e pop %r14 - 4035bf: 41 5f pop %r15 - 4035c1: c3 retq - 4035c2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4035c8: 4c 89 e6 mov %r12,%rsi - 4035cb: 48 89 df mov %rbx,%rdi - 4035ce: e8 6d 01 00 00 callq 403740 <_nl_load_domain> - 4035d3: e9 7c ff ff ff jmpq 403554 <_nl_find_domain+0x84> - 4035d8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 4035df: 00 - 4035e0: 4c 89 ef mov %r13,%rdi - 4035e3: e8 38 1b 00 00 callq 405120 <_nl_expand_alias> - 4035e8: 48 85 c0 test %rax,%rax - 4035eb: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4035f0: 74 14 je 403606 <_nl_find_domain+0x136> - 4035f2: 48 89 c7 mov %rax,%rdi - 4035f5: e8 06 00 02 00 callq 423600 <__strdup> - 4035fa: 48 85 c0 test %rax,%rax - 4035fd: 49 89 c5 mov %rax,%r13 - 403600: 0f 84 2b 01 00 00 je 403731 <_nl_find_domain+0x261> - 403606: 4c 8d 4c 24 38 lea 0x38(%rsp),%r9 - 40360b: 4c 8d 44 24 30 lea 0x30(%rsp),%r8 - 403610: 48 8d 4c 24 28 lea 0x28(%rsp),%rcx - 403615: 48 8d 54 24 20 lea 0x20(%rsp),%rdx - 40361a: 48 8d 74 24 18 lea 0x18(%rsp),%rsi - 40361f: 4c 89 ef mov %r13,%rdi - 403622: e8 89 23 00 00 callq 4059b0 <_nl_explode_name> - 403627: 83 f8 ff cmp $0xffffffff,%eax - 40362a: 89 c3 mov %eax,%ebx - 40362c: 0f 84 ff 00 00 00 je 403731 <_nl_find_domain+0x261> - 403632: b8 00 00 00 00 mov $0x0,%eax - 403637: 48 85 c0 test %rax,%rax - 40363a: 74 07 je 403643 <_nl_find_domain+0x173> - 40363c: bf a0 c0 6c 00 mov $0x6cc0a0,%edi - 403641: ff d0 callq *%rax - 403643: 48 89 ef mov %rbp,%rdi - 403646: e8 05 00 02 00 callq 423650 - 40364b: 48 83 ec 08 sub $0x8,%rsp - 40364f: 48 8d 50 01 lea 0x1(%rax),%rdx - 403653: 48 89 ee mov %rbp,%rsi - 403656: 6a 01 pushq $0x1 - 403658: 41 56 push %r14 - 40365a: 89 d9 mov %ebx,%ecx - 40365c: ff 74 24 38 pushq 0x38(%rsp) - 403660: ff 74 24 58 pushq 0x58(%rsp) - 403664: bf d8 c0 6c 00 mov $0x6cc0d8,%edi - 403669: ff 74 24 58 pushq 0x58(%rsp) - 40366d: 4c 8b 4c 24 58 mov 0x58(%rsp),%r9 - 403672: 4c 8b 44 24 48 mov 0x48(%rsp),%r8 - 403677: e8 64 1c 00 00 callq 4052e0 <_nl_make_l10nflist> - 40367c: 48 83 c4 30 add $0x30,%rsp - 403680: 4d 85 ff test %r15,%r15 - 403683: 48 89 c5 mov %rax,%rbp - 403686: 74 0a je 403692 <_nl_find_domain+0x1c2> - 403688: bf a0 c0 6c 00 mov $0x6cc0a0,%edi - 40368d: e8 6e c9 bf ff callq 0 <_nl_current_LC_CTYPE> - 403692: 48 85 ed test %rbp,%rbp - 403695: 74 22 je 4036b9 <_nl_find_domain+0x1e9> - 403697: 8b 55 08 mov 0x8(%rbp),%edx - 40369a: 85 d2 test %edx,%edx - 40369c: 0f 8e 7f 00 00 00 jle 403721 <_nl_find_domain+0x251> - 4036a2: 48 83 7d 10 00 cmpq $0x0,0x10(%rbp) - 4036a7: 74 35 je 4036de <_nl_find_domain+0x20e> - 4036a9: 48 83 7c 24 08 00 cmpq $0x0,0x8(%rsp) - 4036af: 74 08 je 4036b9 <_nl_find_domain+0x1e9> - 4036b1: 4c 89 ef mov %r13,%rdi - 4036b4: e8 f7 a6 01 00 callq 41ddb0 <__cfree> - 4036b9: 83 e3 01 and $0x1,%ebx - 4036bc: 48 89 e8 mov %rbp,%rax - 4036bf: 0f 84 99 fe ff ff je 40355e <_nl_find_domain+0x8e> - 4036c5: 48 8b 7c 24 38 mov 0x38(%rsp),%rdi - 4036ca: 48 89 6c 24 08 mov %rbp,0x8(%rsp) - 4036cf: e8 dc a6 01 00 callq 41ddb0 <__cfree> - 4036d4: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4036d9: e9 80 fe ff ff jmpq 40355e <_nl_find_domain+0x8e> - 4036de: 48 8b 7d 20 mov 0x20(%rbp),%rdi - 4036e2: 48 85 ff test %rdi,%rdi - 4036e5: 74 c2 je 4036a9 <_nl_find_domain+0x1d9> - 4036e7: 45 31 f6 xor %r14d,%r14d - 4036ea: eb 1c jmp 403708 <_nl_find_domain+0x238> - 4036ec: 0f 1f 40 00 nopl 0x0(%rax) - 4036f0: 48 83 7f 10 00 cmpq $0x0,0x10(%rdi) - 4036f5: 75 b2 jne 4036a9 <_nl_find_domain+0x1d9> - 4036f7: 41 83 c6 01 add $0x1,%r14d - 4036fb: 49 63 c6 movslq %r14d,%rax - 4036fe: 48 8b 7c c5 20 mov 0x20(%rbp,%rax,8),%rdi - 403703: 48 85 ff test %rdi,%rdi - 403706: 74 a1 je 4036a9 <_nl_find_domain+0x1d9> - 403708: 8b 47 08 mov 0x8(%rdi),%eax - 40370b: 85 c0 test %eax,%eax - 40370d: 7f e1 jg 4036f0 <_nl_find_domain+0x220> - 40370f: 4c 89 e6 mov %r12,%rsi - 403712: e8 29 00 00 00 callq 403740 <_nl_load_domain> - 403717: 49 63 c6 movslq %r14d,%rax - 40371a: 48 8b 7c c5 20 mov 0x20(%rbp,%rax,8),%rdi - 40371f: eb cf jmp 4036f0 <_nl_find_domain+0x220> - 403721: 4c 89 e6 mov %r12,%rsi - 403724: 48 89 ef mov %rbp,%rdi - 403727: e8 14 00 00 00 callq 403740 <_nl_load_domain> - 40372c: e9 71 ff ff ff jmpq 4036a2 <_nl_find_domain+0x1d2> - 403731: 31 c0 xor %eax,%eax - 403733: e9 26 fe ff ff jmpq 40355e <_nl_find_domain+0x8e> - 403738: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 40373f: 00 - -0000000000403740 <_nl_load_domain>: - 403740: 55 push %rbp - 403741: 49 89 f0 mov %rsi,%r8 - 403744: 64 48 8b 14 25 10 00 mov %fs:0x10,%rdx - 40374b: 00 00 - 40374d: 48 89 e5 mov %rsp,%rbp - 403750: 41 57 push %r15 - 403752: 41 56 push %r14 - 403754: 41 55 push %r13 - 403756: 41 54 push %r12 - 403758: 53 push %rbx - 403759: 48 89 fb mov %rdi,%rbx - 40375c: 48 81 ec 38 01 00 00 sub $0x138,%rsp - 403763: 48 3b 15 7e 89 2c 00 cmp 0x2c897e(%rip),%rdx # 6cc0e8 - 40376a: 74 46 je 4037b2 <_nl_load_domain+0x72> - 40376c: be 01 00 00 00 mov $0x1,%esi - 403771: 31 c0 xor %eax,%eax - 403773: 83 3d 42 9a 2c 00 00 cmpl $0x0,0x2c9a42(%rip) # 6cd1bc <__libc_multiple_threads> - 40377a: 74 0c je 403788 <_nl_load_domain+0x48> - 40377c: f0 0f b1 35 5c 89 2c lock cmpxchg %esi,0x2c895c(%rip) # 6cc0e0 - 403783: 00 - 403784: 75 0b jne 403791 <_nl_load_domain+0x51> - 403786: eb 23 jmp 4037ab <_nl_load_domain+0x6b> - 403788: 0f b1 35 51 89 2c 00 cmpxchg %esi,0x2c8951(%rip) # 6cc0e0 - 40378f: 74 1a je 4037ab <_nl_load_domain+0x6b> - 403791: 48 8d 3d 48 89 2c 00 lea 0x2c8948(%rip),%rdi # 6cc0e0 - 403798: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 40379f: e8 2c ee 03 00 callq 4425d0 <__lll_lock_wait_private> - 4037a4: 48 81 c4 80 00 00 00 add $0x80,%rsp - 4037ab: 48 89 15 36 89 2c 00 mov %rdx,0x2c8936(%rip) # 6cc0e8 - 4037b2: 8b 05 2c 89 2c 00 mov 0x2c892c(%rip),%eax # 6cc0e4 - 4037b8: 44 8b 63 08 mov 0x8(%rbx),%r12d - 4037bc: 83 c0 01 add $0x1,%eax - 4037bf: 45 85 e4 test %r12d,%r12d - 4037c2: 89 05 1c 89 2c 00 mov %eax,0x2c891c(%rip) # 6cc0e4 - 4037c8: 75 4b jne 403815 <_nl_load_domain+0xd5> - 4037ca: 48 8b 3b mov (%rbx),%rdi - 4037cd: 4d 89 c6 mov %r8,%r14 - 4037d0: c7 43 08 ff ff ff ff movl $0xffffffff,0x8(%rbx) - 4037d7: 48 c7 43 10 00 00 00 movq $0x0,0x10(%rbx) - 4037de: 00 - 4037df: 48 85 ff test %rdi,%rdi - 4037e2: 74 2a je 40380e <_nl_load_domain+0xce> - 4037e4: b9 02 00 00 00 mov $0x2,%ecx - 4037e9: 31 f6 xor %esi,%esi - 4037eb: 89 c8 mov %ecx,%eax - 4037ed: 0f 05 syscall - 4037ef: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 4037f5: 49 89 c4 mov %rax,%r12 - 4037f8: 76 7e jbe 403878 <_nl_load_domain+0x138> - 4037fa: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 403801: 41 f7 dc neg %r12d - 403804: 64 44 89 20 mov %r12d,%fs:(%rax) - 403808: 8b 05 d6 88 2c 00 mov 0x2c88d6(%rip),%eax # 6cc0e4 - 40380e: c7 43 08 01 00 00 00 movl $0x1,0x8(%rbx) - 403815: 83 e8 01 sub $0x1,%eax - 403818: 85 c0 test %eax,%eax - 40381a: 89 05 c4 88 2c 00 mov %eax,0x2c88c4(%rip) # 6cc0e4 - 403820: 75 41 jne 403863 <_nl_load_domain+0x123> - 403822: 48 c7 05 bb 88 2c 00 movq $0x0,0x2c88bb(%rip) # 6cc0e8 - 403829: 00 00 00 00 - 40382d: 83 3d 88 99 2c 00 00 cmpl $0x0,0x2c9988(%rip) # 6cd1bc <__libc_multiple_threads> - 403834: 74 0b je 403841 <_nl_load_domain+0x101> - 403836: f0 ff 0d a3 88 2c 00 lock decl 0x2c88a3(%rip) # 6cc0e0 - 40383d: 75 0a jne 403849 <_nl_load_domain+0x109> - 40383f: eb 22 jmp 403863 <_nl_load_domain+0x123> - 403841: ff 0d 99 88 2c 00 decl 0x2c8899(%rip) # 6cc0e0 - 403847: 74 1a je 403863 <_nl_load_domain+0x123> - 403849: 48 8d 3d 90 88 2c 00 lea 0x2c8890(%rip),%rdi # 6cc0e0 - 403850: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 403857: e8 a4 ed 03 00 callq 442600 <__lll_unlock_wake_private> - 40385c: 48 81 c4 80 00 00 00 add $0x80,%rsp - 403863: 48 8d 65 d8 lea -0x28(%rbp),%rsp - 403867: 5b pop %rbx - 403868: 41 5c pop %r12 - 40386a: 41 5d pop %r13 - 40386c: 41 5e pop %r14 - 40386e: 41 5f pop %r15 - 403870: 5d pop %rbp - 403871: c3 retq - 403872: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 403878: 83 f8 ff cmp $0xffffffff,%eax - 40387b: 74 24 je 4038a1 <_nl_load_domain+0x161> - 40387d: 48 8d 95 40 ff ff ff lea -0xc0(%rbp),%rdx - 403884: 89 c6 mov %eax,%esi - 403886: bf 01 00 00 00 mov $0x1,%edi - 40388b: e8 40 b8 03 00 callq 43f0d0 <__fxstat> - 403890: 85 c0 test %eax,%eax - 403892: 74 1c je 4038b0 <_nl_load_domain+0x170> - 403894: 4d 63 e4 movslq %r12d,%r12 - 403897: 4c 89 e7 mov %r12,%rdi - 40389a: b8 03 00 00 00 mov $0x3,%eax - 40389f: 0f 05 syscall - 4038a1: 8b 05 3d 88 2c 00 mov 0x2c883d(%rip),%eax # 6cc0e4 - 4038a7: e9 62 ff ff ff jmpq 40380e <_nl_load_domain+0xce> - 4038ac: 0f 1f 40 00 nopl 0x0(%rax) - 4038b0: 4c 8b ad 70 ff ff ff mov -0x90(%rbp),%r13 - 4038b7: 49 83 fd 2f cmp $0x2f,%r13 - 4038bb: 76 d7 jbe 403894 <_nl_load_domain+0x154> - 4038bd: 45 31 c9 xor %r9d,%r9d - 4038c0: 31 ff xor %edi,%edi - 4038c2: 45 89 e0 mov %r12d,%r8d - 4038c5: b9 02 00 00 00 mov $0x2,%ecx - 4038ca: ba 01 00 00 00 mov $0x1,%edx - 4038cf: 4c 89 ee mov %r13,%rsi - 4038d2: e8 19 c3 03 00 callq 43fbf0 <__mmap> - 4038d7: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 4038db: 49 89 c7 mov %rax,%r15 - 4038de: 0f 84 b1 01 00 00 je 403a95 <_nl_load_domain+0x355> - 4038e4: 49 63 fc movslq %r12d,%rdi - 4038e7: b8 03 00 00 00 mov $0x3,%eax - 4038ec: 0f 05 syscall - 4038ee: 41 8b 07 mov (%r15),%eax - 4038f1: 3d de 12 04 95 cmp $0x950412de,%eax - 4038f6: 0f 95 c2 setne %dl - 4038f9: 3d 95 04 12 de cmp $0xde120495,%eax - 4038fe: 88 95 20 ff ff ff mov %dl,-0xe0(%rbp) - 403904: 74 1a je 403920 <_nl_load_domain+0x1e0> - 403906: 84 d2 test %dl,%dl - 403908: 74 16 je 403920 <_nl_load_domain+0x1e0> - 40390a: 4c 89 ee mov %r13,%rsi - 40390d: 4c 89 ff mov %r15,%rdi - 403910: e8 9b c3 03 00 callq 43fcb0 <__munmap> - 403915: eb 8a jmp 4038a1 <_nl_load_domain+0x161> - 403917: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 40391e: 00 00 - 403920: c7 85 1c ff ff ff 01 movl $0x1,-0xe4(%rbp) - 403927: 00 00 00 - 40392a: bf c8 00 00 00 mov $0xc8,%edi - 40392f: e8 dc a0 01 00 callq 41da10 <__libc_malloc> - 403934: 48 85 c0 test %rax,%rax - 403937: 48 89 85 28 ff ff ff mov %rax,-0xd8(%rbp) - 40393e: 0f 84 5d ff ff ff je 4038a1 <_nl_load_domain+0x161> - 403944: 0f b6 95 20 ff ff ff movzbl -0xe0(%rbp),%edx - 40394b: 8b 8d 1c ff ff ff mov -0xe4(%rbp),%ecx - 403951: 48 89 43 10 mov %rax,0x10(%rbx) - 403955: 4c 89 38 mov %r15,(%rax) - 403958: 4c 89 68 10 mov %r13,0x10(%rax) - 40395c: 48 c7 40 20 00 00 00 movq $0x0,0x20(%rax) - 403963: 00 - 403964: 89 48 08 mov %ecx,0x8(%rax) - 403967: 84 d2 test %dl,%dl - 403969: 89 50 18 mov %edx,0x18(%rax) - 40396c: 41 8b 47 04 mov 0x4(%r15),%eax - 403970: 0f 84 bd 01 00 00 je 403b33 <_nl_load_domain+0x3f3> - 403976: 0f c8 bswap %eax - 403978: 3d ff ff 01 00 cmp $0x1ffff,%eax - 40397d: 0f 87 4b 02 00 00 ja 403bce <_nl_load_domain+0x48e> - 403983: 41 8b 4f 08 mov 0x8(%r15),%ecx - 403987: 48 8b b5 28 ff ff ff mov -0xd8(%rbp),%rsi - 40398e: 45 8b 57 14 mov 0x14(%r15),%r10d - 403992: 0f c9 bswap %ecx - 403994: 89 4e 28 mov %ecx,0x28(%rsi) - 403997: 41 8b 4f 0c mov 0xc(%r15),%ecx - 40399b: 41 0f ca bswap %r10d - 40399e: 0f c9 bswap %ecx - 4039a0: 89 c9 mov %ecx,%ecx - 4039a2: 4c 01 f9 add %r15,%rcx - 4039a5: 48 89 4e 30 mov %rcx,0x30(%rsi) - 4039a9: 41 8b 4f 10 mov 0x10(%r15),%ecx - 4039ad: 44 89 56 58 mov %r10d,0x58(%rsi) - 4039b1: 0f c9 bswap %ecx - 4039b3: 89 c9 mov %ecx,%ecx - 4039b5: 4c 01 f9 add %r15,%rcx - 4039b8: 41 83 fa 02 cmp $0x2,%r10d - 4039bc: 48 89 4e 38 mov %rcx,0x38(%rsi) - 4039c0: 0f 86 b3 01 00 00 jbe 403b79 <_nl_load_domain+0x439> - 4039c6: 41 8b 4f 18 mov 0x18(%r15),%ecx - 4039ca: 0f c9 bswap %ecx - 4039cc: 89 c9 mov %ecx,%ecx - 4039ce: 4c 01 f9 add %r15,%rcx - 4039d1: 66 85 c0 test %ax,%ax - 4039d4: 89 56 68 mov %edx,0x68(%rsi) - 4039d7: 48 89 4e 60 mov %rcx,0x60(%rsi) - 4039db: 74 2a je 403a07 <_nl_load_domain+0x2c7> - 4039dd: 48 85 c9 test %rcx,%rcx - 4039e0: 0f 84 e8 01 00 00 je 403bce <_nl_load_domain+0x48e> - 4039e6: 80 bd 20 ff ff ff 00 cmpb $0x0,-0xe0(%rbp) - 4039ed: 41 8b 47 24 mov 0x24(%r15),%eax - 4039f1: 0f 84 02 02 00 00 je 403bf9 <_nl_load_domain+0x4b9> - 4039f7: 0f c8 bswap %eax - 4039f9: 85 c0 test %eax,%eax - 4039fb: 89 85 e0 fe ff ff mov %eax,-0x120(%rbp) - 403a01: 0f 85 9b 03 00 00 jne 403da2 <_nl_load_domain+0x662> - 403a07: 48 8b 85 28 ff ff ff mov -0xd8(%rbp),%rax - 403a0e: c7 40 40 00 00 00 00 movl $0x0,0x40(%rax) - 403a15: 48 c7 40 48 00 00 00 movq $0x0,0x48(%rax) - 403a1c: 00 - 403a1d: 48 89 c1 mov %rax,%rcx - 403a20: 48 c7 40 50 00 00 00 movq $0x0,0x50(%rax) - 403a27: 00 - 403a28: b8 00 00 00 00 mov $0x0,%eax - 403a2d: 48 c7 41 70 00 00 00 movq $0x0,0x70(%rcx) - 403a34: 00 - 403a35: 48 c7 41 78 00 00 00 movq $0x0,0x78(%rcx) - 403a3c: 00 - 403a3d: 48 85 c0 test %rax,%rax - 403a40: 74 0e je 403a50 <_nl_load_domain+0x310> - 403a42: 48 8d b9 80 00 00 00 lea 0x80(%rcx),%rdi - 403a49: 31 f6 xor %esi,%esi - 403a4b: e8 b0 c5 bf ff callq 0 <_nl_current_LC_CTYPE> - 403a50: 4c 8d 85 30 ff ff ff lea -0xd0(%rbp),%r8 - 403a57: 31 c9 xor %ecx,%ecx - 403a59: ba 25 67 4b 00 mov $0x4b6725,%edx - 403a5e: 4c 89 f6 mov %r14,%rsi - 403a61: 48 89 df mov %rbx,%rdi - 403a64: e8 e7 e4 ff ff callq 401f50 <_nl_find_msg> - 403a69: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 403a6d: 0f 84 5f 01 00 00 je 403bd2 <_nl_load_domain+0x492> - 403a73: 48 8b 8d 28 ff ff ff mov -0xd8(%rbp),%rcx - 403a7a: 48 89 c7 mov %rax,%rdi - 403a7d: 48 8d 91 c0 00 00 00 lea 0xc0(%rcx),%rdx - 403a84: 48 8d b1 b8 00 00 00 lea 0xb8(%rcx),%rsi - 403a8b: e8 c0 9f 00 00 callq 40da50 <__gettext_extract_plural> - 403a90: e9 0c fe ff ff jmpq 4038a1 <_nl_load_domain+0x161> - 403a95: 4c 89 ef mov %r13,%rdi - 403a98: e8 73 9f 01 00 callq 41da10 <__libc_malloc> - 403a9d: 48 85 c0 test %rax,%rax - 403aa0: 49 89 c7 mov %rax,%r15 - 403aa3: 0f 84 eb fd ff ff je 403894 <_nl_load_domain+0x154> - 403aa9: 4d 63 e4 movslq %r12d,%r12 - 403aac: 49 89 c1 mov %rax,%r9 - 403aaf: 4d 89 e8 mov %r13,%r8 - 403ab2: 45 31 d2 xor %r10d,%r10d - 403ab5: 4c 89 c2 mov %r8,%rdx - 403ab8: 4c 89 ce mov %r9,%rsi - 403abb: 4c 89 e7 mov %r12,%rdi - 403abe: 44 89 d0 mov %r10d,%eax - 403ac1: 0f 05 syscall - 403ac3: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 403ac9: 76 57 jbe 403b22 <_nl_load_domain+0x3e2> - 403acb: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx - 403ad2: f7 d8 neg %eax - 403ad4: 83 f8 04 cmp $0x4,%eax - 403ad7: 64 89 02 mov %eax,%fs:(%rdx) - 403ada: 0f 85 b7 fd ff ff jne 403897 <_nl_load_domain+0x157> - 403ae0: 4d 85 c0 test %r8,%r8 - 403ae3: 75 d0 jne 403ab5 <_nl_load_domain+0x375> - 403ae5: 4c 89 e7 mov %r12,%rdi - 403ae8: b8 03 00 00 00 mov $0x3,%eax - 403aed: 0f 05 syscall - 403aef: 41 8b 17 mov (%r15),%edx - 403af2: 81 fa de 12 04 95 cmp $0x950412de,%edx - 403af8: 0f 95 c0 setne %al - 403afb: 81 fa 95 04 12 de cmp $0xde120495,%edx - 403b01: 88 85 20 ff ff ff mov %al,-0xe0(%rbp) - 403b07: 0f 84 e5 0a 00 00 je 4045f2 <_nl_load_domain+0xeb2> - 403b0d: 84 c0 test %al,%al - 403b0f: 0f 84 dd 0a 00 00 je 4045f2 <_nl_load_domain+0xeb2> - 403b15: 4c 89 ff mov %r15,%rdi - 403b18: e8 93 a2 01 00 callq 41ddb0 <__cfree> - 403b1d: e9 7f fd ff ff jmpq 4038a1 <_nl_load_domain+0x161> - 403b22: 48 85 c0 test %rax,%rax - 403b25: 0f 8e 6c fd ff ff jle 403897 <_nl_load_domain+0x157> - 403b2b: 49 01 c1 add %rax,%r9 - 403b2e: 49 29 c0 sub %rax,%r8 - 403b31: eb ad jmp 403ae0 <_nl_load_domain+0x3a0> - 403b33: 3d ff ff 01 00 cmp $0x1ffff,%eax - 403b38: 0f 87 90 00 00 00 ja 403bce <_nl_load_domain+0x48e> - 403b3e: 41 8b 4f 08 mov 0x8(%r15),%ecx - 403b42: 48 8b b5 28 ff ff ff mov -0xd8(%rbp),%rsi - 403b49: 45 8b 57 14 mov 0x14(%r15),%r10d - 403b4d: 89 4e 28 mov %ecx,0x28(%rsi) - 403b50: 41 8b 4f 0c mov 0xc(%r15),%ecx - 403b54: 4c 01 f9 add %r15,%rcx - 403b57: 48 89 4e 30 mov %rcx,0x30(%rsi) - 403b5b: 41 8b 4f 10 mov 0x10(%r15),%ecx - 403b5f: 44 89 56 58 mov %r10d,0x58(%rsi) - 403b63: 4c 01 f9 add %r15,%rcx - 403b66: 41 83 fa 02 cmp $0x2,%r10d - 403b6a: 48 89 4e 38 mov %rcx,0x38(%rsi) - 403b6e: 76 09 jbe 403b79 <_nl_load_domain+0x439> - 403b70: 41 8b 4f 18 mov 0x18(%r15),%ecx - 403b74: e9 55 fe ff ff jmpq 4039ce <_nl_load_domain+0x28e> - 403b79: 66 85 c0 test %ax,%ax - 403b7c: 48 c7 46 60 00 00 00 movq $0x0,0x60(%rsi) - 403b83: 00 - 403b84: 89 56 68 mov %edx,0x68(%rsi) - 403b87: 0f 84 7a fe ff ff je 403a07 <_nl_load_domain+0x2c7> - 403b8d: 48 8b 7e 20 mov 0x20(%rsi),%rdi - 403b91: e8 1a a2 01 00 callq 41ddb0 <__cfree> - 403b96: 8b 85 1c ff ff ff mov -0xe4(%rbp),%eax - 403b9c: 85 c0 test %eax,%eax - 403b9e: 74 24 je 403bc4 <_nl_load_domain+0x484> - 403ba0: 4c 89 ee mov %r13,%rsi - 403ba3: 4c 89 ff mov %r15,%rdi - 403ba6: e8 05 c1 03 00 callq 43fcb0 <__munmap> - 403bab: 48 8b bd 28 ff ff ff mov -0xd8(%rbp),%rdi - 403bb2: e8 f9 a1 01 00 callq 41ddb0 <__cfree> - 403bb7: 48 c7 43 10 00 00 00 movq $0x0,0x10(%rbx) - 403bbe: 00 - 403bbf: e9 dd fc ff ff jmpq 4038a1 <_nl_load_domain+0x161> - 403bc4: 4c 89 ff mov %r15,%rdi - 403bc7: e8 e4 a1 01 00 callq 41ddb0 <__cfree> - 403bcc: eb dd jmp 403bab <_nl_load_domain+0x46b> - 403bce: 31 ff xor %edi,%edi - 403bd0: eb bf jmp 403b91 <_nl_load_domain+0x451> - 403bd2: b8 00 00 00 00 mov $0x0,%eax - 403bd7: 48 85 c0 test %rax,%rax - 403bda: 0f 84 e6 05 00 00 je 4041c6 <_nl_load_domain+0xa86> - 403be0: 4c 8b b5 28 ff ff ff mov -0xd8(%rbp),%r14 - 403be7: 49 8d be 80 00 00 00 lea 0x80(%r14),%rdi - 403bee: e8 0d c4 bf ff callq 0 <_nl_current_LC_CTYPE> - 403bf3: 49 8b 7e 20 mov 0x20(%r14),%rdi - 403bf7: eb 98 jmp 403b91 <_nl_load_domain+0x451> - 403bf9: 85 c0 test %eax,%eax - 403bfb: 89 85 e0 fe ff ff mov %eax,-0x120(%rbp) - 403c01: 0f 84 00 fe ff ff je 403a07 <_nl_load_domain+0x2c7> - 403c07: 41 8b 47 1c mov 0x1c(%r15),%eax - 403c0b: 41 8b 77 20 mov 0x20(%r15),%esi - 403c0f: 89 c1 mov %eax,%ecx - 403c11: 89 85 e8 fe ff ff mov %eax,-0x118(%rbp) - 403c17: 48 8d 04 c5 1e 00 00 lea 0x1e(,%rax,8),%rax - 403c1e: 00 - 403c1f: 4c 01 fe add %r15,%rsi - 403c22: 48 c1 e8 04 shr $0x4,%rax - 403c26: 48 c1 e0 04 shl $0x4,%rax - 403c2a: 48 29 c4 sub %rax,%rsp - 403c2d: 48 8d 44 24 0f lea 0xf(%rsp),%rax - 403c32: 48 83 e0 f0 and $0xfffffffffffffff0,%rax - 403c36: 85 c9 test %ecx,%ecx - 403c38: 48 89 85 00 ff ff ff mov %rax,-0x100(%rbp) - 403c3f: 0f 84 b3 05 00 00 je 4041f8 <_nl_load_domain+0xab8> - 403c45: 44 89 95 f8 fe ff ff mov %r10d,-0x108(%rbp) - 403c4c: 48 89 9d 08 ff ff ff mov %rbx,-0xf8(%rbp) - 403c53: 48 83 c6 04 add $0x4,%rsi - 403c57: 45 31 c0 xor %r8d,%r8d - 403c5a: 31 ff xor %edi,%edi - 403c5c: 41 bb cd 11 4a 00 mov $0x4a11cd,%r11d - 403c62: 49 bc 01 10 82 20 01 movabs $0x120821001,%r12 - 403c69: 00 00 00 - 403c6c: 44 8b 95 e8 fe ff ff mov -0x118(%rbp),%r10d - 403c73: 44 0f b6 8d 20 ff ff movzbl -0xe0(%rbp),%r9d - 403c7a: ff - 403c7b: 4c 89 ad 10 ff ff ff mov %r13,-0xf0(%rbp) - 403c82: 48 8b 9d 00 ff ff ff mov -0x100(%rbp),%rbx - 403c89: eb 57 jmp 403ce2 <_nl_load_domain+0x5a2> - 403c8b: 8b 16 mov (%rsi),%edx - 403c8d: 8b 46 fc mov -0x4(%rsi),%eax - 403c90: 0f ca bswap %edx - 403c92: 0f c8 bswap %eax - 403c94: 89 d2 mov %edx,%edx - 403c96: 4c 01 fa add %r15,%rdx - 403c99: 85 c0 test %eax,%eax - 403c9b: 0f 84 e3 00 00 00 je 403d84 <_nl_load_domain+0x644> - 403ca1: 83 e8 01 sub $0x1,%eax - 403ca4: 80 3c 02 00 cmpb $0x0,(%rdx,%rax,1) - 403ca8: 0f 85 d6 00 00 00 jne 403d84 <_nl_load_domain+0x644> - 403cae: 0f b6 02 movzbl (%rdx),%eax - 403cb1: 3c 50 cmp $0x50,%al - 403cb3: 74 3c je 403cf1 <_nl_load_domain+0x5b1> - 403cb5: 3c 49 cmp $0x49,%al - 403cb7: 0f 85 7f 08 00 00 jne 40453c <_nl_load_domain+0xdfc> - 403cbd: 80 7a 01 00 cmpb $0x0,0x1(%rdx) - 403cc1: b8 00 00 00 00 mov $0x0,%eax - 403cc6: 49 0f 44 c3 cmove %r11,%rax - 403cca: 83 c7 01 add $0x1,%edi - 403ccd: 4a 89 04 03 mov %rax,(%rbx,%r8,1) - 403cd1: 48 83 c6 08 add $0x8,%rsi - 403cd5: 49 83 c0 08 add $0x8,%r8 - 403cd9: 41 39 fa cmp %edi,%r10d - 403cdc: 0f 86 f4 04 00 00 jbe 4041d6 <_nl_load_domain+0xa96> - 403ce2: 45 84 c9 test %r9b,%r9b - 403ce5: 75 a4 jne 403c8b <_nl_load_domain+0x54b> - 403ce7: 8b 16 mov (%rsi),%edx - 403ce9: 8b 46 fc mov -0x4(%rsi),%eax - 403cec: 4c 01 fa add %r15,%rdx - 403cef: eb a8 jmp 403c99 <_nl_load_domain+0x559> - 403cf1: 31 c0 xor %eax,%eax - 403cf3: 80 7a 01 52 cmpb $0x52,0x1(%rdx) - 403cf7: 75 d1 jne 403cca <_nl_load_domain+0x58a> - 403cf9: 80 7a 02 49 cmpb $0x49,0x2(%rdx) - 403cfd: 75 cb jne 403cca <_nl_load_domain+0x58a> - 403cff: 0f b6 4a 03 movzbl 0x3(%rdx),%ecx - 403d03: 44 8d 69 a8 lea -0x58(%rcx),%r13d - 403d07: 41 80 fd 20 cmp $0x20,%r13b - 403d0b: 77 bd ja 403cca <_nl_load_domain+0x58a> - 403d0d: 4d 0f a3 ec bt %r13,%r12 - 403d11: 73 b7 jae 403cca <_nl_load_domain+0x58a> - 403d13: 44 0f b6 6a 04 movzbl 0x4(%rdx),%r13d - 403d18: 41 80 fd 38 cmp $0x38,%r13b - 403d1c: 0f 84 b1 05 00 00 je 4042d3 <_nl_load_domain+0xb93> - 403d22: 41 80 fd 31 cmp $0x31,%r13b - 403d26: 0f 84 53 05 00 00 je 40427f <_nl_load_domain+0xb3f> - 403d2c: 31 c0 xor %eax,%eax - 403d2e: 41 80 fd 33 cmp $0x33,%r13b - 403d32: 0f 85 11 09 00 00 jne 404649 <_nl_load_domain+0xf09> - 403d38: 80 7a 05 32 cmpb $0x32,0x5(%rdx) - 403d3c: 75 8c jne 403cca <_nl_load_domain+0x58a> - 403d3e: 80 7a 06 00 cmpb $0x0,0x6(%rdx) - 403d42: 75 86 jne 403cca <_nl_load_domain+0x58a> - 403d44: 80 f9 64 cmp $0x64,%cl - 403d47: 0f 84 f2 08 00 00 je 40463f <_nl_load_domain+0xeff> - 403d4d: 80 f9 69 cmp $0x69,%cl - 403d50: 0f 84 df 08 00 00 je 404635 <_nl_load_domain+0xef5> - 403d56: 80 f9 6f cmp $0x6f,%cl - 403d59: 0f 84 cc 08 00 00 je 40462b <_nl_load_domain+0xeeb> - 403d5f: 80 f9 75 cmp $0x75,%cl - 403d62: 0f 84 b9 08 00 00 je 404621 <_nl_load_domain+0xee1> - 403d68: 80 f9 78 cmp $0x78,%cl - 403d6b: 0f 84 a6 08 00 00 je 404617 <_nl_load_domain+0xed7> - 403d71: 80 f9 58 cmp $0x58,%cl - 403d74: 0f 85 bd 07 00 00 jne 404537 <_nl_load_domain+0xdf7> - 403d7a: b8 a5 5a 4b 00 mov $0x4b5aa5,%eax - 403d7f: e9 46 ff ff ff jmpq 403cca <_nl_load_domain+0x58a> - 403d84: 48 8b 85 28 ff ff ff mov -0xd8(%rbp),%rax - 403d8b: 4c 8b ad 10 ff ff ff mov -0xf0(%rbp),%r13 - 403d92: 48 8b 9d 08 ff ff ff mov -0xf8(%rbp),%rbx - 403d99: 48 8b 78 20 mov 0x20(%rax),%rdi - 403d9d: e9 ef fd ff ff jmpq 403b91 <_nl_load_domain+0x451> - 403da2: 41 8b 47 1c mov 0x1c(%r15),%eax - 403da6: 41 8b 77 20 mov 0x20(%r15),%esi - 403daa: 0f c8 bswap %eax - 403dac: 0f ce bswap %esi - 403dae: 89 c1 mov %eax,%ecx - 403db0: 89 85 e8 fe ff ff mov %eax,-0x118(%rbp) - 403db6: 89 c0 mov %eax,%eax - 403db8: 48 8d 04 c5 1e 00 00 lea 0x1e(,%rax,8),%rax - 403dbf: 00 - 403dc0: 89 f6 mov %esi,%esi - 403dc2: 4c 01 fe add %r15,%rsi - 403dc5: 48 c1 e8 04 shr $0x4,%rax - 403dc9: 48 c1 e0 04 shl $0x4,%rax - 403dcd: 48 29 c4 sub %rax,%rsp - 403dd0: 48 8d 44 24 0f lea 0xf(%rsp),%rax - 403dd5: 48 83 e0 f0 and $0xfffffffffffffff0,%rax - 403dd9: 85 c9 test %ecx,%ecx - 403ddb: 48 89 85 00 ff ff ff mov %rax,-0x100(%rbp) - 403de2: 0f 85 5d fe ff ff jne 403c45 <_nl_load_domain+0x505> - 403de8: 41 8b 47 28 mov 0x28(%r15),%eax - 403dec: 0f c8 bswap %eax - 403dee: 89 c0 mov %eax,%eax - 403df0: 4c 01 f8 add %r15,%rax - 403df3: 48 89 85 f0 fe ff ff mov %rax,-0x110(%rbp) - 403dfa: 41 8b 47 2c mov 0x2c(%r15),%eax - 403dfe: 0f c8 bswap %eax - 403e00: 89 c0 mov %eax,%eax - 403e02: 4c 01 f8 add %r15,%rax - 403e05: 45 89 d2 mov %r10d,%r10d - 403e08: 4c 89 b5 b0 fe ff ff mov %r14,-0x150(%rbp) - 403e0f: 48 89 85 d8 fe ff ff mov %rax,-0x128(%rbp) - 403e16: 4c 8b a5 00 ff ff ff mov -0x100(%rbp),%r12 - 403e1d: 4a 8d 04 95 00 00 00 lea 0x0(,%r10,4),%rax - 403e24: 00 - 403e25: 44 8b b5 e8 fe ff ff mov -0x118(%rbp),%r14d - 403e2c: 48 c7 85 08 ff ff ff movq $0x0,-0xf8(%rbp) - 403e33: 00 00 00 00 - 403e37: 48 89 85 b8 fe ff ff mov %rax,-0x148(%rbp) - 403e3e: 48 89 85 c0 fe ff ff mov %rax,-0x140(%rbp) - 403e45: c7 85 10 ff ff ff 00 movl $0x0,-0xf0(%rbp) - 403e4c: 00 00 00 - 403e4f: 4c 89 ad d0 fe ff ff mov %r13,-0x130(%rbp) - 403e56: 4c 89 bd f8 fe ff ff mov %r15,-0x108(%rbp) - 403e5d: 48 89 9d c8 fe ff ff mov %rbx,-0x138(%rbp) - 403e64: 45 31 ed xor %r13d,%r13d - 403e67: 80 bd 20 ff ff ff 00 cmpb $0x0,-0xe0(%rbp) - 403e6e: 0f 84 ce 02 00 00 je 404142 <_nl_load_domain+0xa02> - 403e74: 4d 85 ed test %r13,%r13 - 403e77: 0f 84 5f 07 00 00 je 4045dc <_nl_load_domain+0xe9c> - 403e7d: 48 8b 85 d8 fe ff ff mov -0x128(%rbp),%rax - 403e84: 48 8b 8d 08 ff ff ff mov -0xf8(%rbp),%rcx - 403e8b: 8b 04 88 mov (%rax,%rcx,4),%eax - 403e8e: 0f c8 bswap %eax - 403e90: 89 c2 mov %eax,%edx - 403e92: 48 03 95 f8 fe ff ff add -0x108(%rbp),%rdx - 403e99: 83 7a 08 ff cmpl $0xffffffff,0x8(%rdx) - 403e9d: 0f 84 07 03 00 00 je 4041aa <_nl_load_domain+0xa6a> - 403ea3: 4c 8d 7a 04 lea 0x4(%rdx),%r15 - 403ea7: 31 db xor %ebx,%ebx - 403ea9: eb 25 jmp 403ed0 <_nl_load_domain+0x790> - 403eab: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 403eb0: 44 39 f0 cmp %r14d,%eax - 403eb3: 0f 83 f8 02 00 00 jae 4041b1 <_nl_load_domain+0xa71> - 403eb9: 89 c0 mov %eax,%eax - 403ebb: 49 8b 3c c4 mov (%r12,%rax,8),%rdi - 403ebf: 48 85 ff test %rdi,%rdi - 403ec2: 74 53 je 403f17 <_nl_load_domain+0x7d7> - 403ec4: e8 87 f7 01 00 callq 423650 - 403ec9: 49 83 c7 08 add $0x8,%r15 - 403ecd: 48 01 c3 add %rax,%rbx - 403ed0: 41 8b 07 mov (%r15),%eax - 403ed3: 0f c8 bswap %eax - 403ed5: 89 c0 mov %eax,%eax - 403ed7: 48 01 c3 add %rax,%rbx - 403eda: 41 8b 47 04 mov 0x4(%r15),%eax - 403ede: 0f c8 bswap %eax - 403ee0: 83 f8 ff cmp $0xffffffff,%eax - 403ee3: 75 cb jne 403eb0 <_nl_load_domain+0x770> - 403ee5: 4a 89 9c ed 30 ff ff mov %rbx,-0xd0(%rbp,%r13,8) - 403eec: ff - 403eed: 49 83 c5 01 add $0x1,%r13 - 403ef1: 49 83 fd 02 cmp $0x2,%r13 - 403ef5: 0f 85 6c ff ff ff jne 403e67 <_nl_load_domain+0x727> - 403efb: 48 8b 85 38 ff ff ff mov -0xc8(%rbp),%rax - 403f02: 48 03 85 30 ff ff ff add -0xd0(%rbp),%rax - 403f09: 83 85 10 ff ff ff 01 addl $0x1,-0xf0(%rbp) - 403f10: 48 01 85 c0 fe ff ff add %rax,-0x140(%rbp) - 403f17: 48 83 85 08 ff ff ff addq $0x1,-0xf8(%rbp) - 403f1e: 01 - 403f1f: 48 8b 85 08 ff ff ff mov -0xf8(%rbp),%rax - 403f26: 39 85 e0 fe ff ff cmp %eax,-0x120(%rbp) - 403f2c: 0f 87 32 ff ff ff ja 403e64 <_nl_load_domain+0x724> - 403f32: 83 bd 10 ff ff ff 00 cmpl $0x0,-0xf0(%rbp) - 403f39: 4c 8b ad d0 fe ff ff mov -0x130(%rbp),%r13 - 403f40: 4c 8b bd f8 fe ff ff mov -0x108(%rbp),%r15 - 403f47: 48 8b 9d c8 fe ff ff mov -0x138(%rbp),%rbx - 403f4e: 4c 8b b5 b0 fe ff ff mov -0x150(%rbp),%r14 - 403f55: 0f 84 ac fa ff ff je 403a07 <_nl_load_domain+0x2c7> - 403f5b: 8b 85 10 ff ff ff mov -0xf0(%rbp),%eax - 403f61: 8d 3c 00 lea (%rax,%rax,1),%edi - 403f64: 48 c1 e7 04 shl $0x4,%rdi - 403f68: 48 03 bd c0 fe ff ff add -0x140(%rbp),%rdi - 403f6f: e8 9c 9a 01 00 callq 41da10 <__libc_malloc> - 403f74: 48 85 c0 test %rax,%rax - 403f77: 48 89 85 20 ff ff ff mov %rax,-0xe0(%rbp) - 403f7e: 0f 84 42 02 00 00 je 4041c6 <_nl_load_domain+0xa86> - 403f84: 8b 85 10 ff ff ff mov -0xf0(%rbp),%eax - 403f8a: 48 8b 8d 20 ff ff ff mov -0xe0(%rbp),%rcx - 403f91: 48 8b 95 28 ff ff ff mov -0xd8(%rbp),%rdx - 403f98: 4c 8b 8d b8 fe ff ff mov -0x148(%rbp),%r9 - 403f9f: 4c 8b 95 f0 fe ff ff mov -0x110(%rbp),%r10 - 403fa6: c7 85 f8 fe ff ff 00 movl $0x0,-0x108(%rbp) - 403fad: 00 00 00 - 403fb0: 4c 89 ad c8 fe ff ff mov %r13,-0x138(%rbp) - 403fb7: 48 89 9d c0 fe ff ff mov %rbx,-0x140(%rbp) - 403fbe: 48 c1 e0 04 shl $0x4,%rax - 403fc2: 48 89 4a 20 mov %rcx,0x20(%rdx) - 403fc6: 4c 89 b5 b8 fe ff ff mov %r14,-0x148(%rbp) - 403fcd: 48 01 c1 add %rax,%rcx - 403fd0: 48 01 c8 add %rcx,%rax - 403fd3: 48 89 8d d0 fe ff ff mov %rcx,-0x130(%rbp) - 403fda: 48 89 85 e8 fe ff ff mov %rax,-0x118(%rbp) - 403fe1: 49 01 c1 add %rax,%r9 - 403fe4: 48 8b 85 d8 fe ff ff mov -0x128(%rbp),%rax - 403feb: 48 89 85 08 ff ff ff mov %rax,-0xf8(%rbp) - 403ff2: 8b 85 e0 fe ff ff mov -0x120(%rbp),%eax - 403ff8: 49 8d 04 82 lea (%r10,%rax,4),%rax - 403ffc: 48 89 85 d8 fe ff ff mov %rax,-0x128(%rbp) - 404003: 4c 3b 95 d8 fe ff ff cmp -0x128(%rbp),%r10 - 40400a: 0f 84 b7 03 00 00 je 4043c7 <_nl_load_domain+0xc87> - 404010: 48 8b 85 28 ff ff ff mov -0xd8(%rbp),%rax - 404017: 48 8b 8d 00 ff ff ff mov -0x100(%rbp),%rcx - 40401e: 31 d2 xor %edx,%edx - 404020: 48 8b b5 08 ff ff ff mov -0xf8(%rbp),%rsi - 404027: 44 8b 58 18 mov 0x18(%rax),%r11d - 40402b: 45 85 db test %r11d,%r11d - 40402e: 0f 84 5a 03 00 00 je 40438e <_nl_load_domain+0xc4e> - 404034: 85 d2 test %edx,%edx - 404036: 0f 84 db 04 00 00 je 404517 <_nl_load_domain+0xdd7> - 40403c: 8b 06 mov (%rsi),%eax - 40403e: 0f c8 bswap %eax - 404040: 89 c0 mov %eax,%eax - 404042: 4c 01 f8 add %r15,%rax - 404045: 83 78 08 ff cmpl $0xffffffff,0x8(%rax) - 404049: 0f 85 19 03 00 00 jne 404368 <_nl_load_domain+0xc28> - 40404f: 83 c2 01 add $0x1,%edx - 404052: 83 fa 02 cmp $0x2,%edx - 404055: 75 d4 jne 40402b <_nl_load_domain+0x8eb> - 404057: 8b 85 f8 fe ff ff mov -0x108(%rbp),%eax - 40405d: 48 8b 8d 20 ff ff ff mov -0xe0(%rbp),%rcx - 404064: 45 31 c0 xor %r8d,%r8d - 404067: 48 c1 e0 04 shl $0x4,%rax - 40406b: 48 01 c1 add %rax,%rcx - 40406e: 48 03 85 d0 fe ff ff add -0x130(%rbp),%rax - 404075: 48 89 8d e0 fe ff ff mov %rcx,-0x120(%rbp) - 40407c: 48 89 85 f0 fe ff ff mov %rax,-0x110(%rbp) - 404083: 45 85 db test %r11d,%r11d - 404086: 0f 84 a1 02 00 00 je 40432d <_nl_load_domain+0xbed> - 40408c: 45 85 c0 test %r8d,%r8d - 40408f: 0f 84 19 05 00 00 je 4045ae <_nl_load_domain+0xe6e> - 404095: 48 8b 85 08 ff ff ff mov -0xf8(%rbp),%rax - 40409c: 4c 8b b5 f0 fe ff ff mov -0x110(%rbp),%r14 - 4040a3: 8b 18 mov (%rax),%ebx - 4040a5: 0f cb bswap %ebx - 4040a7: 89 db mov %ebx,%ebx - 4040a9: 4c 01 fb add %r15,%rbx - 4040ac: 44 8b 23 mov (%rbx),%r12d - 4040af: 41 0f cc bswap %r12d - 4040b2: 45 89 e4 mov %r12d,%r12d - 4040b5: 4d 01 fc add %r15,%r12 - 4040b8: 83 7b 08 ff cmpl $0xffffffff,0x8(%rbx) - 4040bc: 0f 84 0e 05 00 00 je 4045d0 <_nl_load_domain+0xe90> - 4040c2: 4d 89 4e 08 mov %r9,0x8(%r14) - 4040c6: 4c 89 b5 b0 fe ff ff mov %r14,-0x150(%rbp) - 4040cd: 48 83 c3 04 add $0x4,%rbx - 4040d1: 44 89 85 18 ff ff ff mov %r8d,-0xe8(%rbp) - 4040d8: 4c 89 95 a8 fe ff ff mov %r10,-0x158(%rbp) - 4040df: 45 89 de mov %r11d,%r14d - 4040e2: eb 51 jmp 404135 <_nl_load_domain+0x9f5> - 4040e4: 8b 4b 04 mov 0x4(%rbx),%ecx - 4040e7: 41 0f cd bswap %r13d - 4040ea: 0f c9 bswap %ecx - 4040ec: 45 85 ed test %r13d,%r13d - 4040ef: 0f 85 1a 01 00 00 jne 40420f <_nl_load_domain+0xacf> - 4040f5: 83 f9 ff cmp $0xffffffff,%ecx - 4040f8: 0f 84 3c 01 00 00 je 40423a <_nl_load_domain+0xafa> - 4040fe: 48 8b 85 00 ff ff ff mov -0x100(%rbp),%rax - 404105: 89 c9 mov %ecx,%ecx - 404107: 48 83 c3 08 add $0x8,%rbx - 40410b: 48 8b 34 c8 mov (%rax,%rcx,8),%rsi - 40410f: 31 c0 xor %eax,%eax - 404111: 48 83 c9 ff or $0xffffffffffffffff,%rcx - 404115: 48 89 f7 mov %rsi,%rdi - 404118: f2 ae repnz scas %es:(%rdi),%al - 40411a: 4c 89 cf mov %r9,%rdi - 40411d: 48 89 c8 mov %rcx,%rax - 404120: 48 f7 d0 not %rax - 404123: 4c 8d 68 ff lea -0x1(%rax),%r13 - 404127: 4c 89 ea mov %r13,%rdx - 40412a: e8 f1 7e 02 00 callq 42c020 - 40412f: 49 89 c1 mov %rax,%r9 - 404132: 4d 01 e9 add %r13,%r9 - 404135: 45 85 f6 test %r14d,%r14d - 404138: 44 8b 2b mov (%rbx),%r13d - 40413b: 75 a7 jne 4040e4 <_nl_load_domain+0x9a4> - 40413d: 8b 4b 04 mov 0x4(%rbx),%ecx - 404140: eb aa jmp 4040ec <_nl_load_domain+0x9ac> - 404142: 4d 85 ed test %r13,%r13 - 404145: 0f 84 b6 04 00 00 je 404601 <_nl_load_domain+0xec1> - 40414b: 48 8b 85 d8 fe ff ff mov -0x128(%rbp),%rax - 404152: 48 8b 8d 08 ff ff ff mov -0xf8(%rbp),%rcx - 404159: 8b 14 88 mov (%rax,%rcx,4),%edx - 40415c: 48 03 95 f8 fe ff ff add -0x108(%rbp),%rdx - 404163: 83 7a 08 ff cmpl $0xffffffff,0x8(%rdx) - 404167: 74 41 je 4041aa <_nl_load_domain+0xa6a> - 404169: 4c 8d 7a 04 lea 0x4(%rdx),%r15 - 40416d: 31 db xor %ebx,%ebx - 40416f: eb 25 jmp 404196 <_nl_load_domain+0xa56> - 404171: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 404178: 41 39 c6 cmp %eax,%r14d - 40417b: 76 34 jbe 4041b1 <_nl_load_domain+0xa71> - 40417d: 49 8b 3c c4 mov (%r12,%rax,8),%rdi - 404181: 48 85 ff test %rdi,%rdi - 404184: 0f 84 8d fd ff ff je 403f17 <_nl_load_domain+0x7d7> - 40418a: e8 c1 f4 01 00 callq 423650 - 40418f: 49 83 c7 08 add $0x8,%r15 - 404193: 48 01 c3 add %rax,%rbx - 404196: 41 8b 07 mov (%r15),%eax - 404199: 48 01 c3 add %rax,%rbx - 40419c: 41 8b 47 04 mov 0x4(%r15),%eax - 4041a0: 83 f8 ff cmp $0xffffffff,%eax - 4041a3: 75 d3 jne 404178 <_nl_load_domain+0xa38> - 4041a5: e9 3b fd ff ff jmpq 403ee5 <_nl_load_domain+0x7a5> - 4041aa: 31 db xor %ebx,%ebx - 4041ac: e9 34 fd ff ff jmpq 403ee5 <_nl_load_domain+0x7a5> - 4041b1: 4c 8b ad d0 fe ff ff mov -0x130(%rbp),%r13 - 4041b8: 4c 8b bd f8 fe ff ff mov -0x108(%rbp),%r15 - 4041bf: 48 8b 9d c8 fe ff ff mov -0x138(%rbp),%rbx - 4041c6: 48 8b 85 28 ff ff ff mov -0xd8(%rbp),%rax - 4041cd: 48 8b 78 20 mov 0x20(%rax),%rdi - 4041d1: e9 bb f9 ff ff jmpq 403b91 <_nl_load_domain+0x451> - 4041d6: 80 bd 20 ff ff ff 00 cmpb $0x0,-0xe0(%rbp) - 4041dd: 44 8b 95 f8 fe ff ff mov -0x108(%rbp),%r10d - 4041e4: 4c 8b ad 10 ff ff ff mov -0xf0(%rbp),%r13 - 4041eb: 48 8b 9d 08 ff ff ff mov -0xf8(%rbp),%rbx - 4041f2: 0f 85 f0 fb ff ff jne 403de8 <_nl_load_domain+0x6a8> - 4041f8: 41 8b 47 28 mov 0x28(%r15),%eax - 4041fc: 4c 01 f8 add %r15,%rax - 4041ff: 48 89 85 f0 fe ff ff mov %rax,-0x110(%rbp) - 404206: 41 8b 47 2c mov 0x2c(%r15),%eax - 40420a: e9 f3 fb ff ff jmpq 403e02 <_nl_load_domain+0x6c2> - 40420f: 45 89 ed mov %r13d,%r13d - 404212: 4c 89 e6 mov %r12,%rsi - 404215: 4c 89 cf mov %r9,%rdi - 404218: 4c 89 ea mov %r13,%rdx - 40421b: 89 8d a4 fe ff ff mov %ecx,-0x15c(%rbp) - 404221: 4d 01 ec add %r13,%r12 - 404224: e8 f7 7d 02 00 callq 42c020 - 404229: 49 89 c1 mov %rax,%r9 - 40422c: 8b 8d a4 fe ff ff mov -0x15c(%rbp),%ecx - 404232: 4d 01 e9 add %r13,%r9 - 404235: e9 bb fe ff ff jmpq 4040f5 <_nl_load_domain+0x9b5> - 40423a: 4c 8b b5 b0 fe ff ff mov -0x150(%rbp),%r14 - 404241: 4c 89 c8 mov %r9,%rax - 404244: 44 8b 85 18 ff ff ff mov -0xe8(%rbp),%r8d - 40424b: 4c 8b 95 a8 fe ff ff mov -0x158(%rbp),%r10 - 404252: 49 2b 46 08 sub 0x8(%r14),%rax - 404256: 49 89 06 mov %rax,(%r14) - 404259: 41 83 c0 01 add $0x1,%r8d - 40425d: 41 83 f8 02 cmp $0x2,%r8d - 404261: 0f 85 b6 00 00 00 jne 40431d <_nl_load_domain+0xbdd> - 404267: 83 85 f8 fe ff ff 01 addl $0x1,-0x108(%rbp) - 40426e: 49 83 c2 04 add $0x4,%r10 - 404272: 48 83 85 08 ff ff ff addq $0x4,-0xf8(%rbp) - 404279: 04 - 40427a: e9 84 fd ff ff jmpq 404003 <_nl_load_domain+0x8c3> - 40427f: 80 7a 05 36 cmpb $0x36,0x5(%rdx) - 404283: 0f 85 41 fa ff ff jne 403cca <_nl_load_domain+0x58a> - 404289: 80 7a 06 00 cmpb $0x0,0x6(%rdx) - 40428d: 0f 85 e2 02 00 00 jne 404575 <_nl_load_domain+0xe35> - 404293: 80 f9 64 cmp $0x64,%cl - 404296: 0f 84 cf 02 00 00 je 40456b <_nl_load_domain+0xe2b> - 40429c: 80 f9 69 cmp $0x69,%cl - 40429f: 0f 84 bc 02 00 00 je 404561 <_nl_load_domain+0xe21> - 4042a5: 80 f9 6f cmp $0x6f,%cl - 4042a8: 0f 84 a9 02 00 00 je 404557 <_nl_load_domain+0xe17> - 4042ae: 80 f9 75 cmp $0x75,%cl - 4042b1: 0f 84 96 02 00 00 je 40454d <_nl_load_domain+0xe0d> - 4042b7: 80 f9 78 cmp $0x78,%cl - 4042ba: 0f 84 83 02 00 00 je 404543 <_nl_load_domain+0xe03> - 4042c0: 80 f9 58 cmp $0x58,%cl - 4042c3: 0f 85 6e 02 00 00 jne 404537 <_nl_load_domain+0xdf7> - 4042c9: b8 a5 5a 4b 00 mov $0x4b5aa5,%eax - 4042ce: e9 f7 f9 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 4042d3: 80 7a 05 00 cmpb $0x0,0x5(%rdx) - 4042d7: 0f 85 ed f9 ff ff jne 403cca <_nl_load_domain+0x58a> - 4042dd: 80 f9 64 cmp $0x64,%cl - 4042e0: 0f 84 b4 02 00 00 je 40459a <_nl_load_domain+0xe5a> - 4042e6: 80 f9 69 cmp $0x69,%cl - 4042e9: 0f 84 a1 02 00 00 je 404590 <_nl_load_domain+0xe50> - 4042ef: 80 f9 6f cmp $0x6f,%cl - 4042f2: 0f 84 8e 02 00 00 je 404586 <_nl_load_domain+0xe46> - 4042f8: 80 f9 75 cmp $0x75,%cl - 4042fb: 0f 84 7b 02 00 00 je 40457c <_nl_load_domain+0xe3c> - 404301: 80 f9 78 cmp $0x78,%cl - 404304: 0f 84 9a 02 00 00 je 4045a4 <_nl_load_domain+0xe64> - 40430a: 80 f9 58 cmp $0x58,%cl - 40430d: 0f 85 24 02 00 00 jne 404537 <_nl_load_domain+0xdf7> - 404313: b8 a5 5a 4b 00 mov $0x4b5aa5,%eax - 404318: e9 ad f9 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 40431d: 48 8b 85 28 ff ff ff mov -0xd8(%rbp),%rax - 404324: 44 8b 58 18 mov 0x18(%rax),%r11d - 404328: e9 56 fd ff ff jmpq 404083 <_nl_load_domain+0x943> - 40432d: 45 85 c0 test %r8d,%r8d - 404330: 0f 84 e9 01 00 00 je 40451f <_nl_load_domain+0xddf> - 404336: 48 8b 85 08 ff ff ff mov -0xf8(%rbp),%rax - 40433d: 4c 8b b5 f0 fe ff ff mov -0x110(%rbp),%r14 - 404344: 8b 18 mov (%rax),%ebx - 404346: 4c 01 fb add %r15,%rbx - 404349: 44 8b 23 mov (%rbx),%r12d - 40434c: 4d 01 fc add %r15,%r12 - 40434f: 83 7b 08 ff cmpl $0xffffffff,0x8(%rbx) - 404353: 0f 85 69 fd ff ff jne 4040c2 <_nl_load_domain+0x982> - 404359: 8b 43 04 mov 0x4(%rbx),%eax - 40435c: 49 89 06 mov %rax,(%r14) - 40435f: 4d 89 66 08 mov %r12,0x8(%r14) - 404363: e9 f1 fe ff ff jmpq 404259 <_nl_load_domain+0xb19> - 404368: 48 83 c0 04 add $0x4,%rax - 40436c: eb 11 jmp 40437f <_nl_load_domain+0xc3f> - 40436e: 89 ff mov %edi,%edi - 404370: 48 83 3c f9 00 cmpq $0x0,(%rcx,%rdi,8) - 404375: 0f 84 f3 fe ff ff je 40426e <_nl_load_domain+0xb2e> - 40437b: 48 83 c0 08 add $0x8,%rax - 40437f: 8b 78 04 mov 0x4(%rax),%edi - 404382: 0f cf bswap %edi - 404384: 83 ff ff cmp $0xffffffff,%edi - 404387: 75 e5 jne 40436e <_nl_load_domain+0xc2e> - 404389: e9 c1 fc ff ff jmpq 40404f <_nl_load_domain+0x90f> - 40438e: 85 d2 test %edx,%edx - 404390: 0f 84 79 01 00 00 je 40450f <_nl_load_domain+0xdcf> - 404396: 8b 06 mov (%rsi),%eax - 404398: 4c 01 f8 add %r15,%rax - 40439b: 83 78 08 ff cmpl $0xffffffff,0x8(%rax) - 40439f: 0f 84 aa fc ff ff je 40404f <_nl_load_domain+0x90f> - 4043a5: 48 83 c0 04 add $0x4,%rax - 4043a9: eb 0f jmp 4043ba <_nl_load_domain+0xc7a> - 4043ab: 48 83 3c f9 00 cmpq $0x0,(%rcx,%rdi,8) - 4043b0: 0f 84 b8 fe ff ff je 40426e <_nl_load_domain+0xb2e> - 4043b6: 48 83 c0 08 add $0x8,%rax - 4043ba: 8b 78 04 mov 0x4(%rax),%edi - 4043bd: 83 ff ff cmp $0xffffffff,%edi - 4043c0: 75 e9 jne 4043ab <_nl_load_domain+0xc6b> - 4043c2: e9 88 fc ff ff jmpq 40404f <_nl_load_domain+0x90f> - 4043c7: 8b 8d f8 fe ff ff mov -0x108(%rbp),%ecx - 4043cd: 39 8d 10 ff ff ff cmp %ecx,-0xf0(%rbp) - 4043d3: 4c 8b ad c8 fe ff ff mov -0x138(%rbp),%r13 - 4043da: 48 8b 9d c0 fe ff ff mov -0x140(%rbp),%rbx - 4043e1: 4c 8b b5 b8 fe ff ff mov -0x148(%rbp),%r14 - 4043e8: 0f 85 49 01 00 00 jne 404537 <_nl_load_domain+0xdf7> - 4043ee: 48 8b b5 28 ff ff ff mov -0xd8(%rbp),%rsi - 4043f5: 31 c0 xor %eax,%eax - 4043f7: 8b 4e 58 mov 0x58(%rsi),%ecx - 4043fa: eb 1d jmp 404419 <_nl_load_domain+0xcd9> - 4043fc: 83 7e 68 00 cmpl $0x0,0x68(%rsi) - 404400: 48 8b 56 60 mov 0x60(%rsi),%rdx - 404404: 8b 14 82 mov (%rdx,%rax,4),%edx - 404407: 74 02 je 40440b <_nl_load_domain+0xccb> - 404409: 0f ca bswap %edx - 40440b: 48 8b bd e8 fe ff ff mov -0x118(%rbp),%rdi - 404412: 89 14 87 mov %edx,(%rdi,%rax,4) - 404415: 48 83 c0 01 add $0x1,%rax - 404419: 39 c1 cmp %eax,%ecx - 40441b: 77 df ja 4043fc <_nl_load_domain+0xcbc> - 40441d: 49 89 d8 mov %rbx,%r8 - 404420: 48 8b 9d 28 ff ff ff mov -0xd8(%rbp),%rbx - 404427: 45 31 c9 xor %r9d,%r9d - 40442a: 4d 89 cc mov %r9,%r12 - 40442d: 4d 89 f1 mov %r14,%r9 - 404430: 4d 89 ee mov %r13,%r14 - 404433: 48 8b 8d 20 ff ff ff mov -0xe0(%rbp),%rcx - 40443a: 4c 89 e0 mov %r12,%rax - 40443d: 4c 89 8d 00 ff ff ff mov %r9,-0x100(%rbp) - 404444: 48 c1 e0 04 shl $0x4,%rax - 404448: 4c 89 85 08 ff ff ff mov %r8,-0xf8(%rbp) - 40444f: 45 89 e5 mov %r12d,%r13d - 404452: 48 8b 7c 01 08 mov 0x8(%rcx,%rax,1),%rdi - 404457: e8 d4 96 00 00 callq 40db30 <__hash_string> - 40445c: 8b 7b 58 mov 0x58(%rbx),%edi - 40445f: 31 d2 xor %edx,%edx - 404461: 89 c1 mov %eax,%ecx - 404463: 4c 8b 85 08 ff ff ff mov -0xf8(%rbp),%r8 - 40446a: 4c 8b 8d 00 ff ff ff mov -0x100(%rbp),%r9 - 404471: f7 f7 div %edi - 404473: 44 8d 57 fe lea -0x2(%rdi),%r10d - 404477: 89 c8 mov %ecx,%eax - 404479: 89 d6 mov %edx,%esi - 40447b: 31 d2 xor %edx,%edx - 40447d: 41 f7 f2 div %r10d - 404480: 41 89 fa mov %edi,%r10d - 404483: 8d 42 01 lea 0x1(%rdx),%eax - 404486: 89 c1 mov %eax,%ecx - 404488: 41 29 c2 sub %eax,%r10d - 40448b: 29 f9 sub %edi,%ecx - 40448d: eb 0e jmp 40449d <_nl_load_domain+0xd5d> - 40448f: 8d 14 0e lea (%rsi,%rcx,1),%edx - 404492: 8d 3c 06 lea (%rsi,%rax,1),%edi - 404495: 44 39 d6 cmp %r10d,%esi - 404498: 0f 42 d7 cmovb %edi,%edx - 40449b: 89 d6 mov %edx,%esi - 40449d: 48 8b bd e8 fe ff ff mov -0x118(%rbp),%rdi - 4044a4: 89 f2 mov %esi,%edx - 4044a6: 48 8d 14 97 lea (%rdi,%rdx,4),%rdx - 4044aa: 44 8b 1a mov (%rdx),%r11d - 4044ad: 45 85 db test %r11d,%r11d - 4044b0: 75 dd jne 40448f <_nl_load_domain+0xd4f> - 4044b2: 8b 43 28 mov 0x28(%rbx),%eax - 4044b5: 49 83 c4 01 add $0x1,%r12 - 4044b9: 44 39 a5 10 ff ff ff cmp %r12d,-0xf0(%rbp) - 4044c0: 41 8d 44 05 01 lea 0x1(%r13,%rax,1),%eax - 4044c5: 89 02 mov %eax,(%rdx) - 4044c7: 0f 87 66 ff ff ff ja 404433 <_nl_load_domain+0xcf3> - 4044cd: 48 8b 85 28 ff ff ff mov -0xd8(%rbp),%rax - 4044d4: 8b 8d 10 ff ff ff mov -0xf0(%rbp),%ecx - 4044da: 4d 89 f5 mov %r14,%r13 - 4044dd: 4c 89 c3 mov %r8,%rbx - 4044e0: 4d 89 ce mov %r9,%r14 - 4044e3: 89 48 40 mov %ecx,0x40(%rax) - 4044e6: 48 8b 8d 20 ff ff ff mov -0xe0(%rbp),%rcx - 4044ed: 48 89 78 60 mov %rdi,0x60(%rax) - 4044f1: c7 40 68 00 00 00 00 movl $0x0,0x68(%rax) - 4044f8: 48 89 48 48 mov %rcx,0x48(%rax) - 4044fc: 48 8b 8d d0 fe ff ff mov -0x130(%rbp),%rcx - 404503: 48 89 48 50 mov %rcx,0x50(%rax) - 404507: 48 89 c1 mov %rax,%rcx - 40450a: e9 19 f5 ff ff jmpq 403a28 <_nl_load_domain+0x2e8> - 40450f: 41 8b 02 mov (%r10),%eax - 404512: e9 81 fe ff ff jmpq 404398 <_nl_load_domain+0xc58> - 404517: 41 8b 02 mov (%r10),%eax - 40451a: e9 1f fb ff ff jmpq 40403e <_nl_load_domain+0x8fe> - 40451f: 41 8b 1a mov (%r10),%ebx - 404522: 4c 8b b5 e0 fe ff ff mov -0x120(%rbp),%r14 - 404529: 4c 01 fb add %r15,%rbx - 40452c: 44 8b 23 mov (%rbx),%r12d - 40452f: 4d 01 fc add %r15,%r12 - 404532: e9 18 fe ff ff jmpq 40434f <_nl_load_domain+0xc0f> - 404537: e8 c4 96 00 00 callq 40dc00 - 40453c: 31 c0 xor %eax,%eax - 40453e: e9 87 f7 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404543: b8 5a 4a 4a 00 mov $0x4a4a5a,%eax - 404548: e9 7d f7 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 40454d: b8 22 66 4b 00 mov $0x4b6622,%eax - 404552: e9 73 f7 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404557: b8 34 4a 4a 00 mov $0x4a4a34,%eax - 40455c: e9 69 f7 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404561: b8 b7 52 4a 00 mov $0x4a52b7,%eax - 404566: e9 5f f7 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 40456b: b8 43 d4 4b 00 mov $0x4bd443,%eax - 404570: e9 55 f7 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404575: 31 c0 xor %eax,%eax - 404577: e9 4e f7 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 40457c: b8 22 66 4b 00 mov $0x4b6622,%eax - 404581: e9 44 f7 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404586: b8 34 4a 4a 00 mov $0x4a4a34,%eax - 40458b: e9 3a f7 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404590: b8 b7 52 4a 00 mov $0x4a52b7,%eax - 404595: e9 30 f7 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 40459a: b8 43 d4 4b 00 mov $0x4bd443,%eax - 40459f: e9 26 f7 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 4045a4: b8 5a 4a 4a 00 mov $0x4a4a5a,%eax - 4045a9: e9 1c f7 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 4045ae: 41 8b 1a mov (%r10),%ebx - 4045b1: 4c 8b b5 e0 fe ff ff mov -0x120(%rbp),%r14 - 4045b8: 0f cb bswap %ebx - 4045ba: 89 db mov %ebx,%ebx - 4045bc: 4c 01 fb add %r15,%rbx - 4045bf: 44 8b 23 mov (%rbx),%r12d - 4045c2: 41 0f cc bswap %r12d - 4045c5: 45 89 e4 mov %r12d,%r12d - 4045c8: 4d 01 fc add %r15,%r12 - 4045cb: e9 e8 fa ff ff jmpq 4040b8 <_nl_load_domain+0x978> - 4045d0: 8b 43 04 mov 0x4(%rbx),%eax - 4045d3: 0f c8 bswap %eax - 4045d5: 89 c0 mov %eax,%eax - 4045d7: e9 80 fd ff ff jmpq 40435c <_nl_load_domain+0xc1c> - 4045dc: 48 8b 85 f0 fe ff ff mov -0x110(%rbp),%rax - 4045e3: 48 8b 8d 08 ff ff ff mov -0xf8(%rbp),%rcx - 4045ea: 8b 04 88 mov (%rax,%rcx,4),%eax - 4045ed: e9 9c f8 ff ff jmpq 403e8e <_nl_load_domain+0x74e> - 4045f2: c7 85 1c ff ff ff 00 movl $0x0,-0xe4(%rbp) - 4045f9: 00 00 00 - 4045fc: e9 29 f3 ff ff jmpq 40392a <_nl_load_domain+0x1ea> - 404601: 48 8b 85 f0 fe ff ff mov -0x110(%rbp),%rax - 404608: 48 8b 8d 08 ff ff ff mov -0xf8(%rbp),%rcx - 40460f: 8b 14 88 mov (%rax,%rcx,4),%edx - 404612: e9 45 fb ff ff jmpq 40415c <_nl_load_domain+0xa1c> - 404617: b8 5a 4a 4a 00 mov $0x4a4a5a,%eax - 40461c: e9 a9 f6 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404621: b8 22 66 4b 00 mov $0x4b6622,%eax - 404626: e9 9f f6 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 40462b: b8 34 4a 4a 00 mov $0x4a4a34,%eax - 404630: e9 95 f6 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404635: b8 b7 52 4a 00 mov $0x4a52b7,%eax - 40463a: e9 8b f6 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 40463f: b8 43 d4 4b 00 mov $0x4bd443,%eax - 404644: e9 81 f6 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404649: 41 80 fd 36 cmp $0x36,%r13b - 40464d: 75 54 jne 4046a3 <_nl_load_domain+0xf63> - 40464f: 80 7a 05 34 cmpb $0x34,0x5(%rdx) - 404653: 0f 85 71 f6 ff ff jne 403cca <_nl_load_domain+0x58a> - 404659: 80 7a 06 00 cmpb $0x0,0x6(%rdx) - 40465d: 0f 85 67 f6 ff ff jne 403cca <_nl_load_domain+0x58a> - 404663: 80 f9 64 cmp $0x64,%cl - 404666: 0f 84 13 06 00 00 je 404c7f <_nl_load_domain+0x153f> - 40466c: 80 f9 69 cmp $0x69,%cl - 40466f: 0f 84 00 06 00 00 je 404c75 <_nl_load_domain+0x1535> - 404675: 80 f9 6f cmp $0x6f,%cl - 404678: 0f 84 ed 05 00 00 je 404c6b <_nl_load_domain+0x152b> - 40467e: 80 f9 75 cmp $0x75,%cl - 404681: 0f 84 da 05 00 00 je 404c61 <_nl_load_domain+0x1521> - 404687: 80 f9 78 cmp $0x78,%cl - 40468a: 0f 84 85 00 00 00 je 404715 <_nl_load_domain+0xfd5> - 404690: 80 f9 58 cmp $0x58,%cl - 404693: 0f 85 9e fe ff ff jne 404537 <_nl_load_domain+0xdf7> - 404699: b8 ca 11 4a 00 mov $0x4a11ca,%eax - 40469e: e9 27 f6 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 4046a3: 41 80 fd 4c cmp $0x4c,%r13b - 4046a7: 0f 84 a3 01 00 00 je 404850 <_nl_load_domain+0x1110> - 4046ad: 41 80 fd 46 cmp $0x46,%r13b - 4046b1: 0f 84 f8 00 00 00 je 4047af <_nl_load_domain+0x106f> - 4046b7: 41 80 fd 4d cmp $0x4d,%r13b - 4046bb: 0f 84 90 00 00 00 je 404751 <_nl_load_domain+0x1011> - 4046c1: 41 80 fd 50 cmp $0x50,%r13b - 4046c5: 0f 85 ff f5 ff ff jne 403cca <_nl_load_domain+0x58a> - 4046cb: 80 7a 05 54 cmpb $0x54,0x5(%rdx) - 4046cf: 0f 85 f5 f5 ff ff jne 403cca <_nl_load_domain+0x58a> - 4046d5: 80 7a 06 52 cmpb $0x52,0x6(%rdx) - 4046d9: 0f 85 eb f5 ff ff jne 403cca <_nl_load_domain+0x58a> - 4046df: 80 7a 07 00 cmpb $0x0,0x7(%rdx) - 4046e3: 0f 85 e1 f5 ff ff jne 403cca <_nl_load_domain+0x58a> - 4046e9: 80 f9 64 cmp $0x64,%cl - 4046ec: 74 59 je 404747 <_nl_load_domain+0x1007> - 4046ee: 80 f9 69 cmp $0x69,%cl - 4046f1: 74 4a je 40473d <_nl_load_domain+0xffd> - 4046f3: 80 f9 6f cmp $0x6f,%cl - 4046f6: 74 3b je 404733 <_nl_load_domain+0xff3> - 4046f8: 80 f9 75 cmp $0x75,%cl - 4046fb: 74 2c je 404729 <_nl_load_domain+0xfe9> - 4046fd: 80 f9 78 cmp $0x78,%cl - 404700: 74 1d je 40471f <_nl_load_domain+0xfdf> - 404702: 80 f9 58 cmp $0x58,%cl - 404705: 0f 85 2c fe ff ff jne 404537 <_nl_load_domain+0xdf7> - 40470b: b8 ca 11 4a 00 mov $0x4a11ca,%eax - 404710: e9 b5 f5 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404715: b8 c1 11 4a 00 mov $0x4a11c1,%eax - 40471a: e9 ab f5 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 40471f: b8 c1 11 4a 00 mov $0x4a11c1,%eax - 404724: e9 a1 f5 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404729: b8 c7 11 4a 00 mov $0x4a11c7,%eax - 40472e: e9 97 f5 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404733: b8 d2 11 4a 00 mov $0x4a11d2,%eax - 404738: e9 8d f5 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 40473d: b8 cf 11 4a 00 mov $0x4a11cf,%eax - 404742: e9 83 f5 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404747: b8 c4 11 4a 00 mov $0x4a11c4,%eax - 40474c: e9 79 f5 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404751: 80 7a 05 41 cmpb $0x41,0x5(%rdx) - 404755: 0f 85 6f f5 ff ff jne 403cca <_nl_load_domain+0x58a> - 40475b: 80 7a 06 58 cmpb $0x58,0x6(%rdx) - 40475f: 0f 85 65 f5 ff ff jne 403cca <_nl_load_domain+0x58a> - 404765: 80 7a 07 00 cmpb $0x0,0x7(%rdx) - 404769: 0f 85 5b f5 ff ff jne 403cca <_nl_load_domain+0x58a> - 40476f: 80 f9 64 cmp $0x64,%cl - 404772: 0f 84 df 04 00 00 je 404c57 <_nl_load_domain+0x1517> - 404778: 80 f9 69 cmp $0x69,%cl - 40477b: 0f 84 cc 04 00 00 je 404c4d <_nl_load_domain+0x150d> - 404781: 80 f9 6f cmp $0x6f,%cl - 404784: 0f 84 b9 04 00 00 je 404c43 <_nl_load_domain+0x1503> - 40478a: 80 f9 75 cmp $0x75,%cl - 40478d: 0f 84 a6 04 00 00 je 404c39 <_nl_load_domain+0x14f9> - 404793: 80 f9 78 cmp $0x78,%cl - 404796: 0f 84 4b 01 00 00 je 4048e7 <_nl_load_domain+0x11a7> - 40479c: 80 f9 58 cmp $0x58,%cl - 40479f: 0f 85 92 fd ff ff jne 404537 <_nl_load_domain+0xdf7> - 4047a5: b8 ca 11 4a 00 mov $0x4a11ca,%eax - 4047aa: e9 1b f5 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 4047af: 80 7a 05 41 cmpb $0x41,0x5(%rdx) - 4047b3: 0f 85 11 f5 ff ff jne 403cca <_nl_load_domain+0x58a> - 4047b9: 80 7a 06 53 cmpb $0x53,0x6(%rdx) - 4047bd: 0f 85 07 f5 ff ff jne 403cca <_nl_load_domain+0x58a> - 4047c3: 80 7a 07 54 cmpb $0x54,0x7(%rdx) - 4047c7: 0f 85 fd f4 ff ff jne 403cca <_nl_load_domain+0x58a> - 4047cd: 44 0f b6 6a 08 movzbl 0x8(%rdx),%r13d - 4047d2: 41 80 fd 38 cmp $0x38,%r13b - 4047d6: 0f 84 83 03 00 00 je 404b5f <_nl_load_domain+0x141f> - 4047dc: 41 80 fd 31 cmp $0x31,%r13b - 4047e0: 0f 84 35 03 00 00 je 404b1b <_nl_load_domain+0x13db> - 4047e6: 41 80 fd 33 cmp $0x33,%r13b - 4047ea: 0f 84 d7 02 00 00 je 404ac7 <_nl_load_domain+0x1387> - 4047f0: 41 80 fd 36 cmp $0x36,%r13b - 4047f4: 0f 85 d0 f4 ff ff jne 403cca <_nl_load_domain+0x58a> - 4047fa: 31 c0 xor %eax,%eax - 4047fc: 80 7a 09 34 cmpb $0x34,0x9(%rdx) - 404800: 0f 85 c4 f4 ff ff jne 403cca <_nl_load_domain+0x58a> - 404806: 80 7a 0a 00 cmpb $0x0,0xa(%rdx) - 40480a: 0f 85 ba f4 ff ff jne 403cca <_nl_load_domain+0x58a> - 404810: 80 f9 64 cmp $0x64,%cl - 404813: 0f 84 a4 02 00 00 je 404abd <_nl_load_domain+0x137d> - 404819: 80 f9 69 cmp $0x69,%cl - 40481c: 0f 84 91 02 00 00 je 404ab3 <_nl_load_domain+0x1373> - 404822: 80 f9 6f cmp $0x6f,%cl - 404825: 0f 84 7e 02 00 00 je 404aa9 <_nl_load_domain+0x1369> - 40482b: 80 f9 75 cmp $0x75,%cl - 40482e: 0f 84 6b 02 00 00 je 404a9f <_nl_load_domain+0x135f> - 404834: 80 f9 78 cmp $0x78,%cl - 404837: 0f 84 58 02 00 00 je 404a95 <_nl_load_domain+0x1355> - 40483d: 80 f9 58 cmp $0x58,%cl - 404840: 0f 85 f1 fc ff ff jne 404537 <_nl_load_domain+0xdf7> - 404846: b8 ca 11 4a 00 mov $0x4a11ca,%eax - 40484b: e9 7a f4 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404850: 80 7a 05 45 cmpb $0x45,0x5(%rdx) - 404854: 0f 85 70 f4 ff ff jne 403cca <_nl_load_domain+0x58a> - 40485a: 80 7a 06 41 cmpb $0x41,0x6(%rdx) - 40485e: 0f 85 66 f4 ff ff jne 403cca <_nl_load_domain+0x58a> - 404864: 80 7a 07 53 cmpb $0x53,0x7(%rdx) - 404868: 0f 85 5c f4 ff ff jne 403cca <_nl_load_domain+0x58a> - 40486e: 80 7a 08 54 cmpb $0x54,0x8(%rdx) - 404872: 0f 85 52 f4 ff ff jne 403cca <_nl_load_domain+0x58a> - 404878: 44 0f b6 6a 09 movzbl 0x9(%rdx),%r13d - 40487d: 41 80 fd 38 cmp $0x38,%r13b - 404881: 0f 84 34 01 00 00 je 4049bb <_nl_load_domain+0x127b> - 404887: 41 80 fd 31 cmp $0x31,%r13b - 40488b: 0f 84 e6 00 00 00 je 404977 <_nl_load_domain+0x1237> - 404891: 41 80 fd 33 cmp $0x33,%r13b - 404895: 0f 84 88 00 00 00 je 404923 <_nl_load_domain+0x11e3> - 40489b: 41 80 fd 36 cmp $0x36,%r13b - 40489f: 0f 85 25 f4 ff ff jne 403cca <_nl_load_domain+0x58a> - 4048a5: 31 c0 xor %eax,%eax - 4048a7: 80 7a 0a 34 cmpb $0x34,0xa(%rdx) - 4048ab: 0f 85 19 f4 ff ff jne 403cca <_nl_load_domain+0x58a> - 4048b1: 80 7a 0b 00 cmpb $0x0,0xb(%rdx) - 4048b5: 0f 85 0f f4 ff ff jne 403cca <_nl_load_domain+0x58a> - 4048bb: 80 f9 64 cmp $0x64,%cl - 4048be: 74 59 je 404919 <_nl_load_domain+0x11d9> - 4048c0: 80 f9 69 cmp $0x69,%cl - 4048c3: 74 4a je 40490f <_nl_load_domain+0x11cf> - 4048c5: 80 f9 6f cmp $0x6f,%cl - 4048c8: 74 3b je 404905 <_nl_load_domain+0x11c5> - 4048ca: 80 f9 75 cmp $0x75,%cl - 4048cd: 74 2c je 4048fb <_nl_load_domain+0x11bb> - 4048cf: 80 f9 78 cmp $0x78,%cl - 4048d2: 74 1d je 4048f1 <_nl_load_domain+0x11b1> - 4048d4: 80 f9 58 cmp $0x58,%cl - 4048d7: 0f 85 5a fc ff ff jne 404537 <_nl_load_domain+0xdf7> - 4048dd: b8 ca 11 4a 00 mov $0x4a11ca,%eax - 4048e2: e9 e3 f3 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 4048e7: b8 c1 11 4a 00 mov $0x4a11c1,%eax - 4048ec: e9 d9 f3 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 4048f1: b8 c1 11 4a 00 mov $0x4a11c1,%eax - 4048f6: e9 cf f3 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 4048fb: b8 c7 11 4a 00 mov $0x4a11c7,%eax - 404900: e9 c5 f3 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404905: b8 d2 11 4a 00 mov $0x4a11d2,%eax - 40490a: e9 bb f3 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 40490f: b8 cf 11 4a 00 mov $0x4a11cf,%eax - 404914: e9 b1 f3 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404919: b8 c4 11 4a 00 mov $0x4a11c4,%eax - 40491e: e9 a7 f3 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404923: 80 7a 0a 32 cmpb $0x32,0xa(%rdx) - 404927: 0f 85 9d f3 ff ff jne 403cca <_nl_load_domain+0x58a> - 40492d: 80 7a 0b 00 cmpb $0x0,0xb(%rdx) - 404931: 0f 85 57 01 00 00 jne 404a8e <_nl_load_domain+0x134e> - 404937: 80 f9 64 cmp $0x64,%cl - 40493a: 0f 84 44 01 00 00 je 404a84 <_nl_load_domain+0x1344> - 404940: 80 f9 69 cmp $0x69,%cl - 404943: 0f 84 31 01 00 00 je 404a7a <_nl_load_domain+0x133a> - 404949: 80 f9 6f cmp $0x6f,%cl - 40494c: 0f 84 1e 01 00 00 je 404a70 <_nl_load_domain+0x1330> - 404952: 80 f9 75 cmp $0x75,%cl - 404955: 0f 84 0b 01 00 00 je 404a66 <_nl_load_domain+0x1326> - 40495b: 80 f9 78 cmp $0x78,%cl - 40495e: 0f 84 f8 00 00 00 je 404a5c <_nl_load_domain+0x131c> - 404964: 80 f9 58 cmp $0x58,%cl - 404967: 0f 85 ca fb ff ff jne 404537 <_nl_load_domain+0xdf7> - 40496d: b8 a5 5a 4b 00 mov $0x4b5aa5,%eax - 404972: e9 53 f3 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404977: 80 7a 0a 36 cmpb $0x36,0xa(%rdx) - 40497b: 0f 85 49 f3 ff ff jne 403cca <_nl_load_domain+0x58a> - 404981: 80 7a 0b 00 cmpb $0x0,0xb(%rdx) - 404985: 0f 85 ca 00 00 00 jne 404a55 <_nl_load_domain+0x1315> - 40498b: 80 f9 64 cmp $0x64,%cl - 40498e: 0f 84 b7 00 00 00 je 404a4b <_nl_load_domain+0x130b> - 404994: 80 f9 69 cmp $0x69,%cl - 404997: 74 6c je 404a05 <_nl_load_domain+0x12c5> - 404999: 80 f9 6f cmp $0x6f,%cl - 40499c: 74 5d je 4049fb <_nl_load_domain+0x12bb> - 40499e: 80 f9 75 cmp $0x75,%cl - 4049a1: 74 6c je 404a0f <_nl_load_domain+0x12cf> - 4049a3: 80 f9 78 cmp $0x78,%cl - 4049a6: 74 49 je 4049f1 <_nl_load_domain+0x12b1> - 4049a8: 80 f9 58 cmp $0x58,%cl - 4049ab: 0f 85 86 fb ff ff jne 404537 <_nl_load_domain+0xdf7> - 4049b1: b8 a5 5a 4b 00 mov $0x4b5aa5,%eax - 4049b6: e9 0f f3 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 4049bb: 80 7a 0a 00 cmpb $0x0,0xa(%rdx) - 4049bf: 0f 85 05 f3 ff ff jne 403cca <_nl_load_domain+0x58a> - 4049c5: 80 f9 64 cmp $0x64,%cl - 4049c8: 74 77 je 404a41 <_nl_load_domain+0x1301> - 4049ca: 80 f9 69 cmp $0x69,%cl - 4049cd: 74 68 je 404a37 <_nl_load_domain+0x12f7> - 4049cf: 80 f9 6f cmp $0x6f,%cl - 4049d2: 74 59 je 404a2d <_nl_load_domain+0x12ed> - 4049d4: 80 f9 75 cmp $0x75,%cl - 4049d7: 74 4a je 404a23 <_nl_load_domain+0x12e3> - 4049d9: 80 f9 78 cmp $0x78,%cl - 4049dc: 74 3b je 404a19 <_nl_load_domain+0x12d9> - 4049de: 80 f9 58 cmp $0x58,%cl - 4049e1: 0f 85 50 fb ff ff jne 404537 <_nl_load_domain+0xdf7> - 4049e7: b8 a5 5a 4b 00 mov $0x4b5aa5,%eax - 4049ec: e9 d9 f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 4049f1: b8 5a 4a 4a 00 mov $0x4a4a5a,%eax - 4049f6: e9 cf f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 4049fb: b8 34 4a 4a 00 mov $0x4a4a34,%eax - 404a00: e9 c5 f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404a05: b8 b7 52 4a 00 mov $0x4a52b7,%eax - 404a0a: e9 bb f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404a0f: b8 22 66 4b 00 mov $0x4b6622,%eax - 404a14: e9 b1 f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404a19: b8 5a 4a 4a 00 mov $0x4a4a5a,%eax - 404a1e: e9 a7 f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404a23: b8 22 66 4b 00 mov $0x4b6622,%eax - 404a28: e9 9d f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404a2d: b8 34 4a 4a 00 mov $0x4a4a34,%eax - 404a32: e9 93 f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404a37: b8 b7 52 4a 00 mov $0x4a52b7,%eax - 404a3c: e9 89 f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404a41: b8 43 d4 4b 00 mov $0x4bd443,%eax - 404a46: e9 7f f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404a4b: b8 43 d4 4b 00 mov $0x4bd443,%eax - 404a50: e9 75 f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404a55: 31 c0 xor %eax,%eax - 404a57: e9 6e f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404a5c: b8 5a 4a 4a 00 mov $0x4a4a5a,%eax - 404a61: e9 64 f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404a66: b8 22 66 4b 00 mov $0x4b6622,%eax - 404a6b: e9 5a f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404a70: b8 34 4a 4a 00 mov $0x4a4a34,%eax - 404a75: e9 50 f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404a7a: b8 b7 52 4a 00 mov $0x4a52b7,%eax - 404a7f: e9 46 f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404a84: b8 43 d4 4b 00 mov $0x4bd443,%eax - 404a89: e9 3c f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404a8e: 31 c0 xor %eax,%eax - 404a90: e9 35 f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404a95: b8 c1 11 4a 00 mov $0x4a11c1,%eax - 404a9a: e9 2b f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404a9f: b8 c7 11 4a 00 mov $0x4a11c7,%eax - 404aa4: e9 21 f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404aa9: b8 d2 11 4a 00 mov $0x4a11d2,%eax - 404aae: e9 17 f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404ab3: b8 cf 11 4a 00 mov $0x4a11cf,%eax - 404ab8: e9 0d f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404abd: b8 c4 11 4a 00 mov $0x4a11c4,%eax - 404ac2: e9 03 f2 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404ac7: 80 7a 09 32 cmpb $0x32,0x9(%rdx) - 404acb: 0f 85 f9 f1 ff ff jne 403cca <_nl_load_domain+0x58a> - 404ad1: 80 7a 0a 00 cmpb $0x0,0xa(%rdx) - 404ad5: 0f 85 57 01 00 00 jne 404c32 <_nl_load_domain+0x14f2> - 404adb: 80 f9 64 cmp $0x64,%cl - 404ade: 0f 84 44 01 00 00 je 404c28 <_nl_load_domain+0x14e8> - 404ae4: 80 f9 69 cmp $0x69,%cl - 404ae7: 0f 84 31 01 00 00 je 404c1e <_nl_load_domain+0x14de> - 404aed: 80 f9 6f cmp $0x6f,%cl - 404af0: 0f 84 1e 01 00 00 je 404c14 <_nl_load_domain+0x14d4> - 404af6: 80 f9 75 cmp $0x75,%cl - 404af9: 0f 84 0b 01 00 00 je 404c0a <_nl_load_domain+0x14ca> - 404aff: 80 f9 78 cmp $0x78,%cl - 404b02: 0f 84 f8 00 00 00 je 404c00 <_nl_load_domain+0x14c0> - 404b08: 80 f9 58 cmp $0x58,%cl - 404b0b: 0f 85 26 fa ff ff jne 404537 <_nl_load_domain+0xdf7> - 404b11: b8 ca 11 4a 00 mov $0x4a11ca,%eax - 404b16: e9 af f1 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404b1b: 80 7a 09 36 cmpb $0x36,0x9(%rdx) - 404b1f: 0f 85 a5 f1 ff ff jne 403cca <_nl_load_domain+0x58a> - 404b25: 80 7a 0a 00 cmpb $0x0,0xa(%rdx) - 404b29: 0f 85 ca 00 00 00 jne 404bf9 <_nl_load_domain+0x14b9> - 404b2f: 80 f9 64 cmp $0x64,%cl - 404b32: 0f 84 b7 00 00 00 je 404bef <_nl_load_domain+0x14af> - 404b38: 80 f9 69 cmp $0x69,%cl - 404b3b: 74 6c je 404ba9 <_nl_load_domain+0x1469> - 404b3d: 80 f9 6f cmp $0x6f,%cl - 404b40: 74 5d je 404b9f <_nl_load_domain+0x145f> - 404b42: 80 f9 75 cmp $0x75,%cl - 404b45: 74 6c je 404bb3 <_nl_load_domain+0x1473> - 404b47: 80 f9 78 cmp $0x78,%cl - 404b4a: 74 49 je 404b95 <_nl_load_domain+0x1455> - 404b4c: 80 f9 58 cmp $0x58,%cl - 404b4f: 0f 85 e2 f9 ff ff jne 404537 <_nl_load_domain+0xdf7> - 404b55: b8 ca 11 4a 00 mov $0x4a11ca,%eax - 404b5a: e9 6b f1 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404b5f: 80 7a 09 00 cmpb $0x0,0x9(%rdx) - 404b63: 0f 85 61 f1 ff ff jne 403cca <_nl_load_domain+0x58a> - 404b69: 80 f9 64 cmp $0x64,%cl - 404b6c: 74 77 je 404be5 <_nl_load_domain+0x14a5> - 404b6e: 80 f9 69 cmp $0x69,%cl - 404b71: 74 68 je 404bdb <_nl_load_domain+0x149b> - 404b73: 80 f9 6f cmp $0x6f,%cl - 404b76: 74 59 je 404bd1 <_nl_load_domain+0x1491> - 404b78: 80 f9 75 cmp $0x75,%cl - 404b7b: 74 4a je 404bc7 <_nl_load_domain+0x1487> - 404b7d: 80 f9 78 cmp $0x78,%cl - 404b80: 74 3b je 404bbd <_nl_load_domain+0x147d> - 404b82: 80 f9 58 cmp $0x58,%cl - 404b85: 0f 85 ac f9 ff ff jne 404537 <_nl_load_domain+0xdf7> - 404b8b: b8 a5 5a 4b 00 mov $0x4b5aa5,%eax - 404b90: e9 35 f1 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404b95: b8 c1 11 4a 00 mov $0x4a11c1,%eax - 404b9a: e9 2b f1 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404b9f: b8 d2 11 4a 00 mov $0x4a11d2,%eax - 404ba4: e9 21 f1 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404ba9: b8 cf 11 4a 00 mov $0x4a11cf,%eax - 404bae: e9 17 f1 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404bb3: b8 c7 11 4a 00 mov $0x4a11c7,%eax - 404bb8: e9 0d f1 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404bbd: b8 5a 4a 4a 00 mov $0x4a4a5a,%eax - 404bc2: e9 03 f1 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404bc7: b8 22 66 4b 00 mov $0x4b6622,%eax - 404bcc: e9 f9 f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404bd1: b8 34 4a 4a 00 mov $0x4a4a34,%eax - 404bd6: e9 ef f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404bdb: b8 b7 52 4a 00 mov $0x4a52b7,%eax - 404be0: e9 e5 f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404be5: b8 43 d4 4b 00 mov $0x4bd443,%eax - 404bea: e9 db f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404bef: b8 c4 11 4a 00 mov $0x4a11c4,%eax - 404bf4: e9 d1 f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404bf9: 31 c0 xor %eax,%eax - 404bfb: e9 ca f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404c00: b8 c1 11 4a 00 mov $0x4a11c1,%eax - 404c05: e9 c0 f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404c0a: b8 c7 11 4a 00 mov $0x4a11c7,%eax - 404c0f: e9 b6 f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404c14: b8 d2 11 4a 00 mov $0x4a11d2,%eax - 404c19: e9 ac f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404c1e: b8 cf 11 4a 00 mov $0x4a11cf,%eax - 404c23: e9 a2 f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404c28: b8 c4 11 4a 00 mov $0x4a11c4,%eax - 404c2d: e9 98 f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404c32: 31 c0 xor %eax,%eax - 404c34: e9 91 f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404c39: b8 c7 11 4a 00 mov $0x4a11c7,%eax - 404c3e: e9 87 f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404c43: b8 d2 11 4a 00 mov $0x4a11d2,%eax - 404c48: e9 7d f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404c4d: b8 cf 11 4a 00 mov $0x4a11cf,%eax - 404c52: e9 73 f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404c57: b8 c4 11 4a 00 mov $0x4a11c4,%eax - 404c5c: e9 69 f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404c61: b8 c7 11 4a 00 mov $0x4a11c7,%eax - 404c66: e9 5f f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404c6b: b8 d2 11 4a 00 mov $0x4a11d2,%eax - 404c70: e9 55 f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404c75: b8 cf 11 4a 00 mov $0x4a11cf,%eax - 404c7a: e9 4b f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404c7f: b8 c4 11 4a 00 mov $0x4a11c4,%eax - 404c84: e9 41 f0 ff ff jmpq 403cca <_nl_load_domain+0x58a> - 404c89: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - -0000000000404c90 : - 404c90: 48 8b 36 mov (%rsi),%rsi - 404c93: 48 8b 3f mov (%rdi),%rdi - 404c96: ba 80 26 4b 00 mov $0x4b2680,%edx - 404c9b: e9 a0 b6 ff ff jmpq 400340 <__rela_iplt_end+0x78> - -0000000000404ca0 : - 404ca0: 55 push %rbp - 404ca1: 48 63 d6 movslq %esi,%rdx - 404ca4: 48 89 fe mov %rdi,%rsi - 404ca7: 48 8d 42 2c lea 0x2c(%rdx),%rax - 404cab: 48 89 e5 mov %rsp,%rbp - 404cae: 41 57 push %r15 - 404cb0: 41 56 push %r14 - 404cb2: 41 55 push %r13 - 404cb4: 41 54 push %r12 - 404cb6: 48 83 e0 f0 and $0xfffffffffffffff0,%rax - 404cba: 53 push %rbx - 404cbb: 48 81 ec d8 01 00 00 sub $0x1d8,%rsp - 404cc2: 48 29 c4 sub %rax,%rsp - 404cc5: 48 8d 5c 24 0f lea 0xf(%rsp),%rbx - 404cca: 48 83 e3 f0 and $0xfffffffffffffff0,%rbx - 404cce: 48 89 df mov %rbx,%rdi - 404cd1: e8 ea 18 02 00 callq 4265c0 <__mempcpy> - 404cd6: ba 0e 00 00 00 mov $0xe,%edx - 404cdb: be f0 11 4a 00 mov $0x4a11f0,%esi - 404ce0: 48 89 c7 mov %rax,%rdi - 404ce3: e8 d8 18 02 00 callq 4265c0 <__mempcpy> - 404ce8: be d5 11 4a 00 mov $0x4a11d5,%esi - 404ced: 48 89 df mov %rbx,%rdi - 404cf0: e8 bb ac 00 00 callq 40f9b0 <_IO_new_fopen> - 404cf5: 48 85 c0 test %rax,%rax - 404cf8: 0f 84 0d 04 00 00 je 40510b - 404cfe: 49 89 c7 mov %rax,%r15 - 404d01: 8b 00 mov (%rax),%eax - 404d03: 89 c2 mov %eax,%edx - 404d05: 80 ce 80 or $0x80,%dh - 404d08: a8 10 test $0x10,%al - 404d0a: 41 89 17 mov %edx,(%r15) - 404d0d: 0f 85 f0 03 00 00 jne 405103 - 404d13: 48 c7 85 18 fe ff ff movq $0x0,-0x1e8(%rbp) - 404d1a: 00 00 00 00 - 404d1e: 66 90 xchg %ax,%ax - 404d20: 48 8d bd 40 fe ff ff lea -0x1c0(%rbp),%rdi - 404d27: 4c 89 fa mov %r15,%rdx - 404d2a: be 90 01 00 00 mov $0x190,%esi - 404d2f: e8 7c cb 00 00 callq 4118b0 <__fgets_unlocked> - 404d34: 48 85 c0 test %rax,%rax - 404d37: 0f 84 ff 01 00 00 je 404f3c - 404d3d: 48 8d bd 40 fe ff ff lea -0x1c0(%rbp),%rdi - 404d44: be 0a 00 00 00 mov $0xa,%esi - 404d49: e8 32 b6 ff ff callq 400380 <__rela_iplt_end+0xb8> - 404d4e: 49 89 c6 mov %rax,%r14 - 404d51: 48 c7 c0 f0 ff ff ff mov $0xfffffffffffffff0,%rax - 404d58: 0f b6 8d 40 fe ff ff movzbl -0x1c0(%rbp),%ecx - 404d5f: 64 48 8b 00 mov %fs:(%rax),%rax - 404d63: 48 89 ca mov %rcx,%rdx - 404d66: f6 44 48 01 20 testb $0x20,0x1(%rax,%rcx,2) - 404d6b: 48 8d 8d 40 fe ff ff lea -0x1c0(%rbp),%rcx - 404d72: 74 15 je 404d89 - 404d74: 0f 1f 40 00 nopl 0x0(%rax) - 404d78: 48 83 c1 01 add $0x1,%rcx - 404d7c: 0f b6 31 movzbl (%rcx),%esi - 404d7f: f6 44 70 01 20 testb $0x20,0x1(%rax,%rsi,2) - 404d84: 48 89 f2 mov %rsi,%rdx - 404d87: 75 ef jne 404d78 - 404d89: 84 d2 test %dl,%dl - 404d8b: 0f 84 9c 01 00 00 je 404f2d - 404d91: 80 fa 23 cmp $0x23,%dl - 404d94: 0f 84 93 01 00 00 je 404f2d - 404d9a: 0f b6 51 01 movzbl 0x1(%rcx),%edx - 404d9e: 48 8d 59 01 lea 0x1(%rcx),%rbx - 404da2: 84 d2 test %dl,%dl - 404da4: 75 19 jne 404dbf - 404da6: e9 15 02 00 00 jmpq 404fc0 - 404dab: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 404db0: 48 83 c3 01 add $0x1,%rbx - 404db4: 0f b6 13 movzbl (%rbx),%edx - 404db7: 84 d2 test %dl,%dl - 404db9: 0f 84 01 02 00 00 je 404fc0 - 404dbf: f6 44 50 01 20 testb $0x20,0x1(%rax,%rdx,2) - 404dc4: 74 ea je 404db0 - 404dc6: 48 89 da mov %rbx,%rdx - 404dc9: 48 83 c3 01 add $0x1,%rbx - 404dcd: 0f b6 72 01 movzbl 0x1(%rdx),%esi - 404dd1: c6 02 00 movb $0x0,(%rdx) - 404dd4: f6 44 70 01 20 testb $0x20,0x1(%rax,%rsi,2) - 404dd9: 48 89 f2 mov %rsi,%rdx - 404ddc: 74 13 je 404df1 - 404dde: 66 90 xchg %ax,%ax - 404de0: 48 83 c3 01 add $0x1,%rbx - 404de4: 0f b6 33 movzbl (%rbx),%esi - 404de7: f6 44 70 01 20 testb $0x20,0x1(%rax,%rsi,2) - 404dec: 48 89 f2 mov %rsi,%rdx - 404def: 75 ef jne 404de0 - 404df1: 84 d2 test %dl,%dl - 404df3: 0f 84 34 01 00 00 je 404f2d - 404df9: 0f b6 53 01 movzbl 0x1(%rbx),%edx - 404dfd: 48 8d 73 01 lea 0x1(%rbx),%rsi - 404e01: 84 d2 test %dl,%dl - 404e03: 75 16 jne 404e1b - 404e05: eb 2e jmp 404e35 - 404e07: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 404e0e: 00 00 - 404e10: 48 83 c6 01 add $0x1,%rsi - 404e14: 0f b6 16 movzbl (%rsi),%edx - 404e17: 84 d2 test %dl,%dl - 404e19: 74 1a je 404e35 - 404e1b: 0f b6 fa movzbl %dl,%edi - 404e1e: f6 44 78 01 20 testb $0x20,0x1(%rax,%rdi,2) - 404e23: 74 eb je 404e10 - 404e25: 80 fa 0a cmp $0xa,%dl - 404e28: 0f 85 7d 02 00 00 jne 4050ab - 404e2e: c6 06 00 movb $0x0,(%rsi) - 404e31: c6 46 01 0a movb $0xa,0x1(%rsi) - 404e35: 4c 8b 25 c4 72 2c 00 mov 0x2c72c4(%rip),%r12 # 6cc100 - 404e3c: 48 8b 35 b5 72 2c 00 mov 0x2c72b5(%rip),%rsi # 6cc0f8 - 404e43: 49 39 f4 cmp %rsi,%r12 - 404e46: 0f 83 67 02 00 00 jae 4050b3 - 404e4c: 48 89 cf mov %rcx,%rdi - 404e4f: 48 89 8d 28 fe ff ff mov %rcx,-0x1d8(%rbp) - 404e56: e8 f5 e7 01 00 callq 423650 - 404e5b: 48 8d 50 01 lea 0x1(%rax),%rdx - 404e5f: 48 89 df mov %rbx,%rdi - 404e62: 48 89 95 38 fe ff ff mov %rdx,-0x1c8(%rbp) - 404e69: e8 e2 e7 01 00 callq 423650 - 404e6e: 48 8b 95 38 fe ff ff mov -0x1c8(%rbp),%rdx - 404e75: 4c 8b 1d 94 72 2c 00 mov 0x2c7294(%rip),%r11 # 6cc110 - 404e7c: 4c 8d 50 01 lea 0x1(%rax),%r10 - 404e80: 48 8b 8d 28 fe ff ff mov -0x1d8(%rbp),%rcx - 404e87: 4a 8d 04 1a lea (%rdx,%r11,1),%rax - 404e8b: 48 89 85 38 fe ff ff mov %rax,-0x1c8(%rbp) - 404e92: 4c 01 d0 add %r10,%rax - 404e95: 48 89 c7 mov %rax,%rdi - 404e98: 48 89 85 30 fe ff ff mov %rax,-0x1d0(%rbp) - 404e9f: 48 8b 05 62 72 2c 00 mov 0x2c7262(%rip),%rax # 6cc108 - 404ea6: 48 39 c7 cmp %rax,%rdi - 404ea9: 0f 87 21 01 00 00 ja 404fd0 - 404eaf: 4c 8b 0d 2a 85 2c 00 mov 0x2c852a(%rip),%r9 # 6cd3e0 - 404eb6: 48 8b 3d 1b 85 2c 00 mov 0x2c851b(%rip),%rdi # 6cd3d8 - 404ebd: 4d 89 e5 mov %r12,%r13 - 404ec0: 48 89 ce mov %rcx,%rsi - 404ec3: 4c 89 95 20 fe ff ff mov %r10,-0x1e0(%rbp) - 404eca: 49 c1 e5 04 shl $0x4,%r13 - 404ece: 4c 89 8d 28 fe ff ff mov %r9,-0x1d8(%rbp) - 404ed5: 49 83 c4 01 add $0x1,%r12 - 404ed9: 49 01 fd add %rdi,%r13 - 404edc: 4b 8d 3c 19 lea (%r9,%r11,1),%rdi - 404ee0: e8 3b 71 02 00 callq 42c020 - 404ee5: 48 8b bd 38 fe ff ff mov -0x1c8(%rbp),%rdi - 404eec: 4c 8b 8d 28 fe ff ff mov -0x1d8(%rbp),%r9 - 404ef3: 48 89 de mov %rbx,%rsi - 404ef6: 4c 8b 95 20 fe ff ff mov -0x1e0(%rbp),%r10 - 404efd: 49 89 45 00 mov %rax,0x0(%r13) - 404f01: 4c 01 cf add %r9,%rdi - 404f04: 4c 89 d2 mov %r10,%rdx - 404f07: e8 14 71 02 00 callq 42c020 - 404f0c: 48 83 85 18 fe ff ff addq $0x1,-0x1e8(%rbp) - 404f13: 01 - 404f14: 49 89 45 08 mov %rax,0x8(%r13) - 404f18: 48 8b 85 30 fe ff ff mov -0x1d0(%rbp),%rax - 404f1f: 4c 89 25 da 71 2c 00 mov %r12,0x2c71da(%rip) # 6cc100 - 404f26: 48 89 05 e3 71 2c 00 mov %rax,0x2c71e3(%rip) # 6cc110 - 404f2d: 4d 85 f6 test %r14,%r14 - 404f30: 74 6c je 404f9e - 404f32: 41 f6 07 10 testb $0x10,(%r15) - 404f36: 0f 84 e4 fd ff ff je 404d20 - 404f3c: 4c 89 ff mov %r15,%rdi - 404f3f: e8 9c a5 00 00 callq 40f4e0 <_IO_new_fclose> - 404f44: 31 c0 xor %eax,%eax - 404f46: 48 83 bd 18 fe ff ff cmpq $0x0,-0x1e8(%rbp) - 404f4d: 00 - 404f4e: 74 24 je 404f74 - 404f50: 48 8b 35 a9 71 2c 00 mov 0x2c71a9(%rip),%rsi # 6cc100 - 404f57: 48 8b 3d 7a 84 2c 00 mov 0x2c847a(%rip),%rdi # 6cd3d8 - 404f5e: b9 90 4c 40 00 mov $0x404c90,%ecx - 404f63: ba 10 00 00 00 mov $0x10,%edx - 404f68: e8 63 98 00 00 callq 40e7d0 - 404f6d: 48 8b 85 18 fe ff ff mov -0x1e8(%rbp),%rax - 404f74: 48 8d 65 d8 lea -0x28(%rbp),%rsp - 404f78: 5b pop %rbx - 404f79: 41 5c pop %r12 - 404f7b: 41 5d pop %r13 - 404f7d: 41 5e pop %r14 - 404f7f: 41 5f pop %r15 - 404f81: 5d pop %rbp - 404f82: c3 retq - 404f83: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 404f88: 48 8d bd 40 fe ff ff lea -0x1c0(%rbp),%rdi - 404f8f: be 0a 00 00 00 mov $0xa,%esi - 404f94: e8 e7 b3 ff ff callq 400380 <__rela_iplt_end+0xb8> - 404f99: 48 85 c0 test %rax,%rax - 404f9c: 75 94 jne 404f32 - 404f9e: 48 8d bd 40 fe ff ff lea -0x1c0(%rbp),%rdi - 404fa5: 4c 89 fa mov %r15,%rdx - 404fa8: be 90 01 00 00 mov $0x190,%esi - 404fad: e8 fe c8 00 00 callq 4118b0 <__fgets_unlocked> - 404fb2: 48 85 c0 test %rax,%rax - 404fb5: 75 d1 jne 404f88 - 404fb7: e9 76 ff ff ff jmpq 404f32 - 404fbc: 0f 1f 40 00 nopl 0x0(%rax) - 404fc0: 66 f7 00 00 20 testw $0x2000,(%rax) - 404fc5: 0f 85 15 fe ff ff jne 404de0 - 404fcb: e9 5d ff ff ff jmpq 404f2d - 404fd0: 4a 8d 34 12 lea (%rdx,%r10,1),%rsi - 404fd4: bf 00 04 00 00 mov $0x400,%edi - 404fd9: 4c 8b 2d 00 84 2c 00 mov 0x2c8400(%rip),%r13 # 6cd3e0 - 404fe0: 4c 89 9d 00 fe ff ff mov %r11,-0x200(%rbp) - 404fe7: 48 89 8d 08 fe ff ff mov %rcx,-0x1f8(%rbp) - 404fee: 48 81 fe 00 04 00 00 cmp $0x400,%rsi - 404ff5: 4c 89 95 10 fe ff ff mov %r10,-0x1f0(%rbp) - 404ffc: 48 89 95 20 fe ff ff mov %rdx,-0x1e0(%rbp) - 405003: 48 0f 42 f7 cmovb %rdi,%rsi - 405007: 4c 89 ef mov %r13,%rdi - 40500a: 4c 8d 04 06 lea (%rsi,%rax,1),%r8 - 40500e: 4c 89 c6 mov %r8,%rsi - 405011: 4c 89 85 28 fe ff ff mov %r8,-0x1d8(%rbp) - 405018: e8 53 8f 01 00 callq 41df70 <__libc_realloc> - 40501d: 48 85 c0 test %rax,%rax - 405020: 0f 84 16 ff ff ff je 404f3c - 405026: 49 39 c5 cmp %rax,%r13 - 405029: 48 8b 3d a8 83 2c 00 mov 0x2c83a8(%rip),%rdi # 6cd3d8 - 405030: 4c 8b 85 28 fe ff ff mov -0x1d8(%rbp),%r8 - 405037: 48 8b 95 20 fe ff ff mov -0x1e0(%rbp),%rdx - 40503e: 4c 8b 95 10 fe ff ff mov -0x1f0(%rbp),%r10 - 405045: 48 8b 8d 08 fe ff ff mov -0x1f8(%rbp),%rcx - 40504c: 4c 8b 9d 00 fe ff ff mov -0x200(%rbp),%r11 - 405053: 74 40 je 405095 - 405055: 4d 85 e4 test %r12,%r12 - 405058: 74 3b je 405095 - 40505a: 48 89 c6 mov %rax,%rsi - 40505d: 4d 89 e1 mov %r12,%r9 - 405060: 4c 29 ee sub %r13,%rsi - 405063: 49 c1 e1 04 shl $0x4,%r9 - 405067: 48 89 b5 28 fe ff ff mov %rsi,-0x1d8(%rbp) - 40506e: 49 01 f9 add %rdi,%r9 - 405071: 48 89 fe mov %rdi,%rsi - 405074: f3 0f 7e 8d 28 fe ff movq -0x1d8(%rbp),%xmm1 - 40507b: ff - 40507c: 66 0f 6c c9 punpcklqdq %xmm1,%xmm1 - 405080: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 405084: 48 83 c6 10 add $0x10,%rsi - 405088: 66 0f d4 c1 paddq %xmm1,%xmm0 - 40508c: 0f 11 46 f0 movups %xmm0,-0x10(%rsi) - 405090: 4c 39 ce cmp %r9,%rsi - 405093: 75 eb jne 405080 - 405095: 48 89 05 44 83 2c 00 mov %rax,0x2c8344(%rip) # 6cd3e0 - 40509c: 4c 89 05 65 70 2c 00 mov %r8,0x2c7065(%rip) # 6cc108 - 4050a3: 49 89 c1 mov %rax,%r9 - 4050a6: e9 12 fe ff ff jmpq 404ebd - 4050ab: c6 06 00 movb $0x0,(%rsi) - 4050ae: e9 82 fd ff ff jmpq 404e35 - 4050b3: 48 85 f6 test %rsi,%rsi - 4050b6: 74 3e je 4050f6 - 4050b8: 4c 8d 2c 36 lea (%rsi,%rsi,1),%r13 - 4050bc: 48 c1 e6 05 shl $0x5,%rsi - 4050c0: 48 8b 3d 11 83 2c 00 mov 0x2c8311(%rip),%rdi # 6cd3d8 - 4050c7: 48 89 8d 38 fe ff ff mov %rcx,-0x1c8(%rbp) - 4050ce: e8 9d 8e 01 00 callq 41df70 <__libc_realloc> - 4050d3: 48 85 c0 test %rax,%rax - 4050d6: 0f 84 60 fe ff ff je 404f3c - 4050dc: 48 89 05 f5 82 2c 00 mov %rax,0x2c82f5(%rip) # 6cd3d8 - 4050e3: 4c 89 2d 0e 70 2c 00 mov %r13,0x2c700e(%rip) # 6cc0f8 - 4050ea: 48 8b 8d 38 fe ff ff mov -0x1c8(%rbp),%rcx - 4050f1: e9 56 fd ff ff jmpq 404e4c - 4050f6: be 40 06 00 00 mov $0x640,%esi - 4050fb: 41 bd 64 00 00 00 mov $0x64,%r13d - 405101: eb bd jmp 4050c0 - 405103: 4c 89 ff mov %r15,%rdi - 405106: e8 d5 a3 00 00 callq 40f4e0 <_IO_new_fclose> - 40510b: 48 8d 65 d8 lea -0x28(%rbp),%rsp - 40510f: 31 c0 xor %eax,%eax - 405111: 5b pop %rbx - 405112: 41 5c pop %r12 - 405114: 41 5d pop %r13 - 405116: 41 5e pop %r14 - 405118: 41 5f pop %r15 - 40511a: 5d pop %rbp - 40511b: c3 retq - 40511c: 0f 1f 40 00 nopl 0x0(%rax) - -0000000000405120 <_nl_expand_alias>: - 405120: 41 57 push %r15 - 405122: 41 56 push %r14 - 405124: be 01 00 00 00 mov $0x1,%esi - 405129: 41 55 push %r13 - 40512b: 41 54 push %r12 - 40512d: 31 c0 xor %eax,%eax - 40512f: 55 push %rbp - 405130: 53 push %rbx - 405131: 48 89 fb mov %rdi,%rbx - 405134: 48 83 ec 08 sub $0x8,%rsp - 405138: 83 3d 7d 80 2c 00 00 cmpl $0x0,0x2c807d(%rip) # 6cd1bc <__libc_multiple_threads> - 40513f: 74 0c je 40514d <_nl_expand_alias+0x2d> - 405141: f0 0f b1 35 cf 6f 2c lock cmpxchg %esi,0x2c6fcf(%rip) # 6cc118 - 405148: 00 - 405149: 75 0b jne 405156 <_nl_expand_alias+0x36> - 40514b: eb 23 jmp 405170 <_nl_expand_alias+0x50> - 40514d: 0f b1 35 c4 6f 2c 00 cmpxchg %esi,0x2c6fc4(%rip) # 6cc118 - 405154: 74 1a je 405170 <_nl_expand_alias+0x50> - 405156: 48 8d 3d bb 6f 2c 00 lea 0x2c6fbb(%rip),%rdi # 6cc118 - 40515d: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 405164: e8 67 d4 03 00 callq 4425d0 <__lll_lock_wait_private> - 405169: 48 81 c4 80 00 00 00 add $0x80,%rsp - 405170: 48 83 3d 78 6f 2c 00 cmpq $0x0,0x2c6f78(%rip) # 6cc0f0 - 405177: 00 - 405178: 0f 84 51 01 00 00 je 4052cf <_nl_expand_alias+0x1af> - 40517e: 4c 8b 3d 7b 6f 2c 00 mov 0x2c6f7b(%rip),%r15 # 6cc100 - 405185: 4d 85 ff test %r15,%r15 - 405188: 74 54 je 4051de <_nl_expand_alias+0xbe> - 40518a: 4c 8b 35 47 82 2c 00 mov 0x2c8247(%rip),%r14 # 6cd3d8 - 405191: 45 31 ed xor %r13d,%r13d - 405194: eb 19 jmp 4051af <_nl_expand_alias+0x8f> - 405196: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 40519d: 00 00 00 - 4051a0: 0f 84 22 01 00 00 je 4052c8 <_nl_expand_alias+0x1a8> - 4051a6: 4c 8d 6d 01 lea 0x1(%rbp),%r13 - 4051aa: 4d 39 ef cmp %r13,%r15 - 4051ad: 76 2f jbe 4051de <_nl_expand_alias+0xbe> - 4051af: 4b 8d 6c 3d 00 lea 0x0(%r13,%r15,1),%rbp - 4051b4: ba 80 26 4b 00 mov $0x4b2680,%edx - 4051b9: 48 89 df mov %rbx,%rdi - 4051bc: 48 d1 ed shr %rbp - 4051bf: 49 89 ec mov %rbp,%r12 - 4051c2: 49 c1 e4 04 shl $0x4,%r12 - 4051c6: 4d 01 f4 add %r14,%r12 - 4051c9: 49 8b 34 24 mov (%r12),%rsi - 4051cd: e8 6e b1 ff ff callq 400340 <__rela_iplt_end+0x78> - 4051d2: 85 c0 test %eax,%eax - 4051d4: 79 ca jns 4051a0 <_nl_expand_alias+0x80> - 4051d6: 49 89 ef mov %rbp,%r15 - 4051d9: 4d 39 ef cmp %r13,%r15 - 4051dc: 77 d1 ja 4051af <_nl_expand_alias+0x8f> - 4051de: 48 8b 0d 0b 6f 2c 00 mov 0x2c6f0b(%rip),%rcx # 6cc0f0 - 4051e5: 0f b6 01 movzbl (%rcx),%eax - 4051e8: 84 c0 test %al,%al - 4051ea: 74 69 je 405255 <_nl_expand_alias+0x135> - 4051ec: 48 89 cf mov %rcx,%rdi - 4051ef: 31 f6 xor %esi,%esi - 4051f1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4051f8: 3c 3a cmp $0x3a,%al - 4051fa: 48 8d 51 01 lea 0x1(%rcx),%rdx - 4051fe: 75 17 jne 405217 <_nl_expand_alias+0xf7> - 405200: 48 89 d7 mov %rdx,%rdi - 405203: 48 8d 52 01 lea 0x1(%rdx),%rdx - 405207: 0f b6 42 ff movzbl -0x1(%rdx),%eax - 40520b: 3c 3a cmp $0x3a,%al - 40520d: 74 f1 je 405200 <_nl_expand_alias+0xe0> - 40520f: 48 89 f9 mov %rdi,%rcx - 405212: be 01 00 00 00 mov $0x1,%esi - 405217: 84 c0 test %al,%al - 405219: 0f 84 9d 00 00 00 je 4052bc <_nl_expand_alias+0x19c> - 40521f: 48 8d 77 01 lea 0x1(%rdi),%rsi - 405223: eb 0a jmp 40522f <_nl_expand_alias+0x10f> - 405225: 0f 1f 00 nopl (%rax) - 405228: 3c 3a cmp $0x3a,%al - 40522a: 74 11 je 40523d <_nl_expand_alias+0x11d> - 40522c: 48 89 d6 mov %rdx,%rsi - 40522f: 0f b6 06 movzbl (%rsi),%eax - 405232: 48 89 f1 mov %rsi,%rcx - 405235: 48 8d 56 01 lea 0x1(%rsi),%rdx - 405239: 84 c0 test %al,%al - 40523b: 75 eb jne 405228 <_nl_expand_alias+0x108> - 40523d: 48 39 fe cmp %rdi,%rsi - 405240: 77 5d ja 40529f <_nl_expand_alias+0x17f> - 405242: 84 c0 test %al,%al - 405244: 48 89 f7 mov %rsi,%rdi - 405247: be 01 00 00 00 mov $0x1,%esi - 40524c: 75 aa jne 4051f8 <_nl_expand_alias+0xd8> - 40524e: 48 89 0d 9b 6e 2c 00 mov %rcx,0x2c6e9b(%rip) # 6cc0f0 - 405255: 31 d2 xor %edx,%edx - 405257: 83 3d 5e 7f 2c 00 00 cmpl $0x0,0x2c7f5e(%rip) # 6cd1bc <__libc_multiple_threads> - 40525e: 74 0b je 40526b <_nl_expand_alias+0x14b> - 405260: f0 ff 0d b1 6e 2c 00 lock decl 0x2c6eb1(%rip) # 6cc118 - 405267: 75 0a jne 405273 <_nl_expand_alias+0x153> - 405269: eb 22 jmp 40528d <_nl_expand_alias+0x16d> - 40526b: ff 0d a7 6e 2c 00 decl 0x2c6ea7(%rip) # 6cc118 - 405271: 74 1a je 40528d <_nl_expand_alias+0x16d> - 405273: 48 8d 3d 9e 6e 2c 00 lea 0x2c6e9e(%rip),%rdi # 6cc118 - 40527a: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 405281: e8 7a d3 03 00 callq 442600 <__lll_unlock_wake_private> - 405286: 48 81 c4 80 00 00 00 add $0x80,%rsp - 40528d: 48 83 c4 08 add $0x8,%rsp - 405291: 48 89 d0 mov %rdx,%rax - 405294: 5b pop %rbx - 405295: 5d pop %rbp - 405296: 41 5c pop %r12 - 405298: 41 5d pop %r13 - 40529a: 41 5e pop %r14 - 40529c: 41 5f pop %r15 - 40529e: c3 retq - 40529f: 48 89 35 4a 6e 2c 00 mov %rsi,0x2c6e4a(%rip) # 6cc0f0 - 4052a6: 48 29 fe sub %rdi,%rsi - 4052a9: e8 f2 f9 ff ff callq 404ca0 - 4052ae: 48 85 c0 test %rax,%rax - 4052b1: 0f 84 27 ff ff ff je 4051de <_nl_expand_alias+0xbe> - 4052b7: e9 c2 fe ff ff jmpq 40517e <_nl_expand_alias+0x5e> - 4052bc: 40 84 f6 test %sil,%sil - 4052bf: 74 94 je 405255 <_nl_expand_alias+0x135> - 4052c1: eb 8b jmp 40524e <_nl_expand_alias+0x12e> - 4052c3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4052c8: 49 8b 54 24 08 mov 0x8(%r12),%rdx - 4052cd: eb 88 jmp 405257 <_nl_expand_alias+0x137> - 4052cf: 48 c7 05 16 6e 2c 00 movq $0x4a11d9,0x2c6e16(%rip) # 6cc0f0 - 4052d6: d9 11 4a 00 - 4052da: e9 9f fe ff ff jmpq 40517e <_nl_expand_alias+0x5e> - 4052df: 90 nop - -00000000004052e0 <_nl_make_l10nflist>: - 4052e0: 41 57 push %r15 - 4052e2: 41 56 push %r14 - 4052e4: 4d 89 ce mov %r9,%r14 - 4052e7: 41 55 push %r13 - 4052e9: 41 54 push %r12 - 4052eb: 41 89 cc mov %ecx,%r12d - 4052ee: 55 push %rbp - 4052ef: 53 push %rbx - 4052f0: 48 89 d3 mov %rdx,%rbx - 4052f3: 48 83 c3 02 add $0x2,%rbx - 4052f7: 48 83 ec 48 sub $0x48,%rsp - 4052fb: 48 89 7c 24 08 mov %rdi,0x8(%rsp) - 405300: 4c 89 c7 mov %r8,%rdi - 405303: 48 89 74 24 28 mov %rsi,0x28(%rsp) - 405308: 48 89 54 24 18 mov %rdx,0x18(%rsp) - 40530d: 89 4c 24 34 mov %ecx,0x34(%rsp) - 405311: 4c 89 04 24 mov %r8,(%rsp) - 405315: 4c 89 4c 24 10 mov %r9,0x10(%rsp) - 40531a: e8 31 e3 01 00 callq 423650 - 40531f: 41 83 e4 04 and $0x4,%r12d - 405323: 4c 8b bc 24 98 00 00 mov 0x98(%rsp),%r15 - 40532a: 00 - 40532b: 49 89 c5 mov %rax,%r13 - 40532e: 0f 84 5c 04 00 00 je 405790 <_nl_make_l10nflist+0x4b0> - 405334: 4c 89 f7 mov %r14,%rdi - 405337: e8 14 e3 01 00 callq 423650 - 40533c: 48 8d 68 01 lea 0x1(%rax),%rbp - 405340: 8b 44 24 34 mov 0x34(%rsp),%eax - 405344: 49 01 dd add %rbx,%r13 - 405347: 45 31 f6 xor %r14d,%r14d - 40534a: 83 e0 02 and $0x2,%eax - 40534d: 89 44 24 20 mov %eax,0x20(%rsp) - 405351: 74 11 je 405364 <_nl_make_l10nflist+0x84> - 405353: 48 8b bc 24 80 00 00 mov 0x80(%rsp),%rdi - 40535a: 00 - 40535b: e8 f0 e2 01 00 callq 423650 - 405360: 4c 8d 70 01 lea 0x1(%rax),%r14 - 405364: 8b 44 24 34 mov 0x34(%rsp),%eax - 405368: 4c 01 ed add %r13,%rbp - 40536b: 31 db xor %ebx,%ebx - 40536d: 83 e0 01 and $0x1,%eax - 405370: 89 44 24 38 mov %eax,0x38(%rsp) - 405374: 74 11 je 405387 <_nl_make_l10nflist+0xa7> - 405376: 48 8b bc 24 88 00 00 mov 0x88(%rsp),%rdi - 40537d: 00 - 40537e: e8 cd e2 01 00 callq 423650 - 405383: 48 8d 58 01 lea 0x1(%rax),%rbx - 405387: 8b 44 24 34 mov 0x34(%rsp),%eax - 40538b: 4c 01 f5 add %r14,%rbp - 40538e: 45 31 ed xor %r13d,%r13d - 405391: 83 e0 08 and $0x8,%eax - 405394: 89 44 24 3c mov %eax,0x3c(%rsp) - 405398: 74 11 je 4053ab <_nl_make_l10nflist+0xcb> - 40539a: 48 8b bc 24 90 00 00 mov 0x90(%rsp),%rdi - 4053a1: 00 - 4053a2: e8 a9 e2 01 00 callq 423650 - 4053a7: 4c 8d 68 01 lea 0x1(%rax),%r13 - 4053ab: 4c 89 ff mov %r15,%rdi - 4053ae: e8 9d e2 01 00 callq 423650 - 4053b3: 48 8d 3c 2b lea (%rbx,%rbp,1),%rdi - 4053b7: 49 89 c6 mov %rax,%r14 - 4053ba: 4c 01 ef add %r13,%rdi - 4053bd: 48 01 c7 add %rax,%rdi - 4053c0: e8 4b 86 01 00 callq 41da10 <__libc_malloc> - 4053c5: 48 85 c0 test %rax,%rax - 4053c8: 49 89 c5 mov %rax,%r13 - 4053cb: 0f 84 a3 04 00 00 je 405874 <_nl_make_l10nflist+0x594> - 4053d1: 48 8b 5c 24 18 mov 0x18(%rsp),%rbx - 4053d6: 48 8b 74 24 28 mov 0x28(%rsp),%rsi - 4053db: 48 89 c7 mov %rax,%rdi - 4053de: 48 89 da mov %rbx,%rdx - 4053e1: e8 3a 6c 02 00 callq 42c020 - 4053e6: 48 85 db test %rbx,%rbx - 4053e9: 74 25 je 405410 <_nl_make_l10nflist+0x130> - 4053eb: 4c 89 ed mov %r13,%rbp - 4053ee: 66 90 xchg %ax,%ax - 4053f0: 48 89 ef mov %rbp,%rdi - 4053f3: e8 58 e2 01 00 callq 423650 - 4053f8: 48 29 c3 sub %rax,%rbx - 4053fb: 48 83 eb 01 sub $0x1,%rbx - 4053ff: 74 0f je 405410 <_nl_make_l10nflist+0x130> - 405401: 48 01 e8 add %rbp,%rax - 405404: 48 8d 68 01 lea 0x1(%rax),%rbp - 405408: c6 00 3a movb $0x3a,(%rax) - 40540b: eb e3 jmp 4053f0 <_nl_make_l10nflist+0x110> - 40540d: 0f 1f 00 nopl (%rax) - 405410: 48 8b 44 24 18 mov 0x18(%rsp),%rax - 405415: 48 8b 34 24 mov (%rsp),%rsi - 405419: 49 8d 7c 05 00 lea 0x0(%r13,%rax,1),%rdi - 40541e: 41 c6 44 05 ff 2f movb $0x2f,-0x1(%r13,%rax,1) - 405424: e8 e7 ae ff ff callq 400310 <__rela_iplt_end+0x48> - 405429: 45 85 e4 test %r12d,%r12d - 40542c: 0f 85 ce 03 00 00 jne 405800 <_nl_make_l10nflist+0x520> - 405432: 8b 74 24 20 mov 0x20(%rsp),%esi - 405436: 85 f6 test %esi,%esi - 405438: 0f 85 a0 03 00 00 jne 4057de <_nl_make_l10nflist+0x4fe> - 40543e: 8b 4c 24 38 mov 0x38(%rsp),%ecx - 405442: 85 c9 test %ecx,%ecx - 405444: 0f 85 7b 03 00 00 jne 4057c5 <_nl_make_l10nflist+0x4e5> - 40544a: 8b 54 24 3c mov 0x3c(%rsp),%edx - 40544e: 85 d2 test %edx,%edx - 405450: 0f 85 56 03 00 00 jne 4057ac <_nl_make_l10nflist+0x4cc> - 405456: 48 8d 78 01 lea 0x1(%rax),%rdi - 40545a: 49 8d 56 01 lea 0x1(%r14),%rdx - 40545e: c6 00 2f movb $0x2f,(%rax) - 405461: 4c 89 fe mov %r15,%rsi - 405464: e8 b7 6b 02 00 callq 42c020 - 405469: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40546e: 48 8b 00 mov (%rax),%rax - 405471: 48 85 c0 test %rax,%rax - 405474: 48 89 44 24 20 mov %rax,0x20(%rsp) - 405479: 0f 84 fc 03 00 00 je 40587b <_nl_make_l10nflist+0x59b> - 40547f: 49 89 c4 mov %rax,%r12 - 405482: 31 ed xor %ebp,%ebp - 405484: 0f 1f 40 00 nopl 0x0(%rax) - 405488: 49 8b 3c 24 mov (%r12),%rdi - 40548c: 48 85 ff test %rdi,%rdi - 40548f: 74 15 je 4054a6 <_nl_make_l10nflist+0x1c6> - 405491: 4c 89 ee mov %r13,%rsi - 405494: e8 c7 ae ff ff callq 400360 <__rela_iplt_end+0x98> - 405499: 85 c0 test %eax,%eax - 40549b: 0f 84 78 03 00 00 je 405819 <_nl_make_l10nflist+0x539> - 4054a1: 78 0d js 4054b0 <_nl_make_l10nflist+0x1d0> - 4054a3: 4c 89 e5 mov %r12,%rbp - 4054a6: 4d 8b 64 24 18 mov 0x18(%r12),%r12 - 4054ab: 4d 85 e4 test %r12,%r12 - 4054ae: 75 d8 jne 405488 <_nl_make_l10nflist+0x1a8> - 4054b0: 8b 84 24 a0 00 00 00 mov 0xa0(%rsp),%eax - 4054b7: 85 c0 test %eax,%eax - 4054b9: 0f 84 57 03 00 00 je 405816 <_nl_make_l10nflist+0x536> - 4054bf: 48 8b 44 24 18 mov 0x18(%rsp),%rax - 4054c4: 45 31 e4 xor %r12d,%r12d - 4054c7: 4c 8b 74 24 28 mov 0x28(%rsp),%r14 - 4054cc: 48 85 c0 test %rax,%rax - 4054cf: 48 89 c3 mov %rax,%rbx - 4054d2: 0f 84 7c 03 00 00 je 405854 <_nl_make_l10nflist+0x574> - 4054d8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 4054df: 00 - 4054e0: 4c 89 f7 mov %r14,%rdi - 4054e3: 49 83 c4 01 add $0x1,%r12 - 4054e7: e8 64 e1 01 00 callq 423650 - 4054ec: 48 29 c3 sub %rax,%rbx - 4054ef: 4d 8d 74 06 01 lea 0x1(%r14,%rax,1),%r14 - 4054f4: 48 83 eb 01 sub $0x1,%rbx - 4054f8: 75 e6 jne 4054e0 <_nl_make_l10nflist+0x200> - 4054fa: 8b 44 24 34 mov 0x34(%rsp),%eax - 4054fe: 89 c2 mov %eax,%edx - 405500: 25 55 55 00 00 and $0x5555,%eax - 405505: 81 e2 aa aa ff ff and $0xffffaaaa,%edx - 40550b: d1 fa sar %edx - 40550d: 01 c2 add %eax,%edx - 40550f: 89 d0 mov %edx,%eax - 405511: 81 e2 33 33 00 00 and $0x3333,%edx - 405517: 25 cc cc ff ff and $0xffffcccc,%eax - 40551c: c1 f8 02 sar $0x2,%eax - 40551f: 01 d0 add %edx,%eax - 405521: 89 c2 mov %eax,%edx - 405523: c1 fa 04 sar $0x4,%edx - 405526: 01 d0 add %edx,%eax - 405528: 25 0f 0f 00 00 and $0xf0f,%eax - 40552d: 89 c1 mov %eax,%ecx - 40552f: c1 f9 08 sar $0x8,%ecx - 405532: 01 c1 add %eax,%ecx - 405534: b8 01 00 00 00 mov $0x1,%eax - 405539: d3 e0 shl %cl,%eax - 40553b: 48 63 f8 movslq %eax,%rdi - 40553e: 48 c1 e7 04 shl $0x4,%rdi - 405542: 4c 0f af e7 imul %rdi,%r12 - 405546: 49 8d 7c 24 28 lea 0x28(%r12),%rdi - 40554b: e8 c0 84 01 00 callq 41da10 <__libc_malloc> - 405550: 48 85 c0 test %rax,%rax - 405553: 49 89 c4 mov %rax,%r12 - 405556: 0f 84 26 03 00 00 je 405882 <_nl_make_l10nflist+0x5a2> - 40555c: 48 8b 5c 24 18 mov 0x18(%rsp),%rbx - 405561: 4c 8b 74 24 28 mov 0x28(%rsp),%r14 - 405566: 4c 89 28 mov %r13,(%rax) - 405569: 45 31 ed xor %r13d,%r13d - 40556c: 0f 1f 40 00 nopl 0x0(%rax) - 405570: 4c 89 f7 mov %r14,%rdi - 405573: 49 83 c5 01 add $0x1,%r13 - 405577: e8 d4 e0 01 00 callq 423650 - 40557c: 48 29 c3 sub %rax,%rbx - 40557f: 4d 8d 74 06 01 lea 0x1(%r14,%rax,1),%r14 - 405584: 48 83 eb 01 sub $0x1,%rbx - 405588: 75 e6 jne 405570 <_nl_make_l10nflist+0x290> - 40558a: 49 83 fd 01 cmp $0x1,%r13 - 40558e: b8 01 00 00 00 mov $0x1,%eax - 405593: 0f 84 fe 01 00 00 je 405797 <_nl_make_l10nflist+0x4b7> - 405599: 48 85 ed test %rbp,%rbp - 40559c: 41 89 44 24 08 mov %eax,0x8(%r12) - 4055a1: 49 c7 44 24 10 00 00 movq $0x0,0x10(%r12) - 4055a8: 00 00 - 4055aa: 0f 84 83 02 00 00 je 405833 <_nl_make_l10nflist+0x553> - 4055b0: 48 8b 45 18 mov 0x18(%rbp),%rax - 4055b4: 49 89 44 24 18 mov %rax,0x18(%r12) - 4055b9: 4c 89 65 18 mov %r12,0x18(%rbp) - 4055bd: 48 8b 44 24 18 mov 0x18(%rsp),%rax - 4055c2: 48 85 c0 test %rax,%rax - 4055c5: 0f 84 7f 02 00 00 je 40584a <_nl_make_l10nflist+0x56a> - 4055cb: 4c 8b 6c 24 28 mov 0x28(%rsp),%r13 - 4055d0: 48 89 c3 mov %rax,%rbx - 4055d3: 31 ed xor %ebp,%ebp - 4055d5: 0f 1f 00 nopl (%rax) - 4055d8: 4c 89 ef mov %r13,%rdi - 4055db: 48 83 c5 01 add $0x1,%rbp - 4055df: e8 6c e0 01 00 callq 423650 - 4055e4: 48 29 c3 sub %rax,%rbx - 4055e7: 4d 8d 6c 05 01 lea 0x1(%r13,%rax,1),%r13 - 4055ec: 48 83 eb 01 sub $0x1,%rbx - 4055f0: 75 e6 jne 4055d8 <_nl_make_l10nflist+0x2f8> - 4055f2: 44 8b 6c 24 34 mov 0x34(%rsp),%r13d - 4055f7: 31 c0 xor %eax,%eax - 4055f9: 48 83 fd 01 cmp $0x1,%rbp - 4055fd: 0f 94 c0 sete %al - 405600: 41 29 c5 sub %eax,%r13d - 405603: 45 85 ed test %r13d,%r13d - 405606: 0f 88 c4 00 00 00 js 4056d0 <_nl_make_l10nflist+0x3f0> - 40560c: 8b 44 24 34 mov 0x34(%rsp),%eax - 405610: 48 8b 4c 24 18 mov 0x18(%rsp),%rcx - 405615: 31 ed xor %ebp,%ebp - 405617: f7 d0 not %eax - 405619: 89 44 24 20 mov %eax,0x20(%rsp) - 40561d: 48 8b 44 24 28 mov 0x28(%rsp),%rax - 405622: 4c 8d 34 08 lea (%rax,%rcx,1),%r14 - 405626: eb 16 jmp 40563e <_nl_make_l10nflist+0x35e> - 405628: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 40562f: 00 - 405630: 41 83 ed 01 sub $0x1,%r13d - 405634: 41 83 fd ff cmp $0xffffffff,%r13d - 405638: 0f 84 9a 00 00 00 je 4056d8 <_nl_make_l10nflist+0x3f8> - 40563e: 44 85 6c 24 20 test %r13d,0x20(%rsp) - 405643: 75 eb jne 405630 <_nl_make_l10nflist+0x350> - 405645: 48 83 7c 24 18 00 cmpq $0x0,0x18(%rsp) - 40564b: 74 e3 je 405630 <_nl_make_l10nflist+0x350> - 40564d: 48 8b 5c 24 28 mov 0x28(%rsp),%rbx - 405652: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 405658: 48 89 df mov %rbx,%rdi - 40565b: 48 83 c5 01 add $0x1,%rbp - 40565f: e8 ec df 01 00 callq 423650 - 405664: 48 83 ec 08 sub $0x8,%rsp - 405668: 48 8d 50 01 lea 0x1(%rax),%rdx - 40566c: 44 89 e9 mov %r13d,%ecx - 40566f: 6a 01 pushq $0x1 - 405671: 41 57 push %r15 - 405673: 48 89 de mov %rbx,%rsi - 405676: ff b4 24 a8 00 00 00 pushq 0xa8(%rsp) - 40567d: ff b4 24 a8 00 00 00 pushq 0xa8(%rsp) - 405684: ff b4 24 a8 00 00 00 pushq 0xa8(%rsp) - 40568b: 4c 8b 4c 24 40 mov 0x40(%rsp),%r9 - 405690: 4c 8b 44 24 30 mov 0x30(%rsp),%r8 - 405695: 48 8b 7c 24 38 mov 0x38(%rsp),%rdi - 40569a: e8 41 fc ff ff callq 4052e0 <_nl_make_l10nflist> - 40569f: 48 83 c4 30 add $0x30,%rsp - 4056a3: 49 39 de cmp %rbx,%r14 - 4056a6: 49 89 44 ec 18 mov %rax,0x18(%r12,%rbp,8) - 4056ab: 76 83 jbe 405630 <_nl_make_l10nflist+0x350> - 4056ad: 31 f6 xor %esi,%esi - 4056af: 48 89 df mov %rbx,%rdi - 4056b2: e8 19 73 02 00 callq 42c9d0 <__rawmemchr> - 4056b7: 48 8d 58 01 lea 0x1(%rax),%rbx - 4056bb: 4c 39 f3 cmp %r14,%rbx - 4056be: 0f 83 6c ff ff ff jae 405630 <_nl_make_l10nflist+0x350> - 4056c4: 48 85 db test %rbx,%rbx - 4056c7: 75 8f jne 405658 <_nl_make_l10nflist+0x378> - 4056c9: e9 62 ff ff ff jmpq 405630 <_nl_make_l10nflist+0x350> - 4056ce: 66 90 xchg %ax,%ax - 4056d0: 31 ed xor %ebp,%ebp - 4056d2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4056d8: bf fe 11 4a 00 mov $0x4a11fe,%edi - 4056dd: b9 0b 00 00 00 mov $0xb,%ecx - 4056e2: 4c 89 fe mov %r15,%rsi - 4056e5: f3 a6 repz cmpsb %es:(%rdi),%ds:(%rsi) - 4056e7: 0f 85 87 00 00 00 jne 405774 <_nl_make_l10nflist+0x494> - 4056ed: 8b 5c 24 34 mov 0x34(%rsp),%ebx - 4056f1: 85 db test %ebx,%ebx - 4056f3: 78 7f js 405774 <_nl_make_l10nflist+0x494> - 4056f5: 41 89 dd mov %ebx,%r13d - 4056f8: 41 f7 d5 not %r13d - 4056fb: 45 89 ee mov %r13d,%r14d - 4056fe: 49 89 ed mov %rbp,%r13 - 405701: 4c 89 fd mov %r15,%rbp - 405704: eb 12 jmp 405718 <_nl_make_l10nflist+0x438> - 405706: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 40570d: 00 00 00 - 405710: 83 eb 01 sub $0x1,%ebx - 405713: 83 fb ff cmp $0xffffffff,%ebx - 405716: 74 59 je 405771 <_nl_make_l10nflist+0x491> - 405718: 44 85 f3 test %r14d,%ebx - 40571b: 75 f3 jne 405710 <_nl_make_l10nflist+0x430> - 40571d: 48 83 ec 08 sub $0x8,%rsp - 405721: 89 d9 mov %ebx,%ecx - 405723: 4d 8d 7d 01 lea 0x1(%r13),%r15 - 405727: 6a 01 pushq $0x1 - 405729: 55 push %rbp - 40572a: ba 1b 00 00 00 mov $0x1b,%edx - 40572f: ff b4 24 a8 00 00 00 pushq 0xa8(%rsp) - 405736: ff b4 24 a8 00 00 00 pushq 0xa8(%rsp) - 40573d: be 0a 12 4a 00 mov $0x4a120a,%esi - 405742: ff b4 24 a8 00 00 00 pushq 0xa8(%rsp) - 405749: 4c 8b 4c 24 40 mov 0x40(%rsp),%r9 - 40574e: 83 eb 01 sub $0x1,%ebx - 405751: 4c 8b 44 24 30 mov 0x30(%rsp),%r8 - 405756: 48 8b 7c 24 38 mov 0x38(%rsp),%rdi - 40575b: e8 80 fb ff ff callq 4052e0 <_nl_make_l10nflist> - 405760: 48 83 c4 30 add $0x30,%rsp - 405764: 83 fb ff cmp $0xffffffff,%ebx - 405767: 4b 89 44 ec 20 mov %rax,0x20(%r12,%r13,8) - 40576c: 4d 89 fd mov %r15,%r13 - 40576f: 75 a7 jne 405718 <_nl_make_l10nflist+0x438> - 405771: 4c 89 ed mov %r13,%rbp - 405774: 49 c7 44 ec 20 00 00 movq $0x0,0x20(%r12,%rbp,8) - 40577b: 00 00 - 40577d: 4c 89 e0 mov %r12,%rax - 405780: 48 83 c4 48 add $0x48,%rsp - 405784: 5b pop %rbx - 405785: 5d pop %rbp - 405786: 41 5c pop %r12 - 405788: 41 5d pop %r13 - 40578a: 41 5e pop %r14 - 40578c: 41 5f pop %r15 - 40578e: c3 retq - 40578f: 90 nop - 405790: 31 ed xor %ebp,%ebp - 405792: e9 a9 fb ff ff jmpq 405340 <_nl_make_l10nflist+0x60> - 405797: 8b 44 24 34 mov 0x34(%rsp),%eax - 40579b: 83 e0 03 and $0x3,%eax - 40579e: 83 f8 03 cmp $0x3,%eax - 4057a1: 0f 94 c0 sete %al - 4057a4: 0f b6 c0 movzbl %al,%eax - 4057a7: e9 ed fd ff ff jmpq 405599 <_nl_make_l10nflist+0x2b9> - 4057ac: 48 8b b4 24 90 00 00 mov 0x90(%rsp),%rsi - 4057b3: 00 - 4057b4: 48 8d 78 01 lea 0x1(%rax),%rdi - 4057b8: c6 00 40 movb $0x40,(%rax) - 4057bb: e8 50 ab ff ff callq 400310 <__rela_iplt_end+0x48> - 4057c0: e9 91 fc ff ff jmpq 405456 <_nl_make_l10nflist+0x176> - 4057c5: 48 8b b4 24 88 00 00 mov 0x88(%rsp),%rsi - 4057cc: 00 - 4057cd: 48 8d 78 01 lea 0x1(%rax),%rdi - 4057d1: c6 00 2e movb $0x2e,(%rax) - 4057d4: e8 37 ab ff ff callq 400310 <__rela_iplt_end+0x48> - 4057d9: e9 6c fc ff ff jmpq 40544a <_nl_make_l10nflist+0x16a> - 4057de: 48 8b b4 24 80 00 00 mov 0x80(%rsp),%rsi - 4057e5: 00 - 4057e6: 48 8d 78 01 lea 0x1(%rax),%rdi - 4057ea: c6 00 2e movb $0x2e,(%rax) - 4057ed: e8 1e ab ff ff callq 400310 <__rela_iplt_end+0x48> - 4057f2: e9 47 fc ff ff jmpq 40543e <_nl_make_l10nflist+0x15e> - 4057f7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 4057fe: 00 00 - 405800: 48 8b 74 24 10 mov 0x10(%rsp),%rsi - 405805: 48 8d 78 01 lea 0x1(%rax),%rdi - 405809: c6 00 5f movb $0x5f,(%rax) - 40580c: e8 ff aa ff ff callq 400310 <__rela_iplt_end+0x48> - 405811: e9 1c fc ff ff jmpq 405432 <_nl_make_l10nflist+0x152> - 405816: 45 31 e4 xor %r12d,%r12d - 405819: 4c 89 ef mov %r13,%rdi - 40581c: e8 8f 85 01 00 callq 41ddb0 <__cfree> - 405821: 48 83 c4 48 add $0x48,%rsp - 405825: 4c 89 e0 mov %r12,%rax - 405828: 5b pop %rbx - 405829: 5d pop %rbp - 40582a: 41 5c pop %r12 - 40582c: 41 5d pop %r13 - 40582e: 41 5e pop %r14 - 405830: 41 5f pop %r15 - 405832: c3 retq - 405833: 48 8b 44 24 20 mov 0x20(%rsp),%rax - 405838: 49 89 44 24 18 mov %rax,0x18(%r12) - 40583d: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 405842: 4c 89 20 mov %r12,(%rax) - 405845: e9 73 fd ff ff jmpq 4055bd <_nl_make_l10nflist+0x2dd> - 40584a: 44 8b 6c 24 34 mov 0x34(%rsp),%r13d - 40584f: e9 af fd ff ff jmpq 405603 <_nl_make_l10nflist+0x323> - 405854: bf 28 00 00 00 mov $0x28,%edi - 405859: e8 b2 81 01 00 callq 41da10 <__libc_malloc> - 40585e: 48 85 c0 test %rax,%rax - 405861: 49 89 c4 mov %rax,%r12 - 405864: 74 1c je 405882 <_nl_make_l10nflist+0x5a2> - 405866: 4d 89 2c 24 mov %r13,(%r12) - 40586a: b8 01 00 00 00 mov $0x1,%eax - 40586f: e9 25 fd ff ff jmpq 405599 <_nl_make_l10nflist+0x2b9> - 405874: 31 c0 xor %eax,%eax - 405876: e9 05 ff ff ff jmpq 405780 <_nl_make_l10nflist+0x4a0> - 40587b: 31 ed xor %ebp,%ebp - 40587d: e9 2e fc ff ff jmpq 4054b0 <_nl_make_l10nflist+0x1d0> - 405882: 4c 89 ef mov %r13,%rdi - 405885: e8 26 85 01 00 callq 41ddb0 <__cfree> - 40588a: 31 c0 xor %eax,%eax - 40588c: e9 ef fe ff ff jmpq 405780 <_nl_make_l10nflist+0x4a0> - 405891: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 405896: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 40589d: 00 00 00 - -00000000004058a0 <_nl_normalize_codeset>: - 4058a0: 41 55 push %r13 - 4058a2: 41 54 push %r12 - 4058a4: 49 89 f5 mov %rsi,%r13 - 4058a7: 55 push %rbp - 4058a8: 53 push %rbx - 4058a9: 48 89 fb mov %rdi,%rbx - 4058ac: 48 83 ec 08 sub $0x8,%rsp - 4058b0: 48 85 f6 test %rsi,%rsi - 4058b3: 0f 84 e4 00 00 00 je 40599d <_nl_normalize_codeset+0xfd> - 4058b9: 48 8b 2d 28 ce 0a 00 mov 0xace28(%rip),%rbp # 4b26e8 <_nl_C_locobj+0x68> - 4058c0: 4c 8d 24 37 lea (%rdi,%rsi,1),%r12 - 4058c4: 48 89 fa mov %rdi,%rdx - 4058c7: 41 b8 01 00 00 00 mov $0x1,%r8d - 4058cd: 31 ff xor %edi,%edi - 4058cf: 31 f6 xor %esi,%esi - 4058d1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4058d8: 0f b6 0a movzbl (%rdx),%ecx - 4058db: f6 44 4d 00 08 testb $0x8,0x0(%rbp,%rcx,2) - 4058e0: 48 89 c8 mov %rcx,%rax - 4058e3: 74 0e je 4058f3 <_nl_normalize_codeset+0x53> - 4058e5: 83 e8 30 sub $0x30,%eax - 4058e8: 48 83 c7 01 add $0x1,%rdi - 4058ec: 83 f8 0a cmp $0xa,%eax - 4058ef: 44 0f 43 c6 cmovae %esi,%r8d - 4058f3: 48 83 c2 01 add $0x1,%rdx - 4058f7: 4c 39 e2 cmp %r12,%rdx - 4058fa: 75 dc jne 4058d8 <_nl_normalize_codeset+0x38> - 4058fc: 45 85 c0 test %r8d,%r8d - 4058ff: 75 6f jne 405970 <_nl_normalize_codeset+0xd0> - 405901: 48 83 c7 01 add $0x1,%rdi - 405905: e8 06 81 01 00 callq 41da10 <__libc_malloc> - 40590a: 48 85 c0 test %rax,%rax - 40590d: 74 51 je 405960 <_nl_normalize_codeset+0xc0> - 40590f: 49 89 c0 mov %rax,%r8 - 405912: 48 8b 35 d7 cd 0a 00 mov 0xacdd7(%rip),%rsi # 4b26f0 <_nl_C_locobj+0x70> - 405919: 48 89 df mov %rbx,%rdi - 40591c: eb 16 jmp 405934 <_nl_normalize_codeset+0x94> - 40591e: 66 90 xchg %ax,%ax - 405920: 8b 14 8e mov (%rsi,%rcx,4),%edx - 405923: 49 83 c0 01 add $0x1,%r8 - 405927: 41 88 50 ff mov %dl,-0x1(%r8) - 40592b: 48 83 c7 01 add $0x1,%rdi - 40592f: 49 39 fc cmp %rdi,%r12 - 405932: 74 28 je 40595c <_nl_normalize_codeset+0xbc> - 405934: 0f b6 0f movzbl (%rdi),%ecx - 405937: f6 44 4d 01 04 testb $0x4,0x1(%rbp,%rcx,2) - 40593c: 48 89 ca mov %rcx,%rdx - 40593f: 75 df jne 405920 <_nl_normalize_codeset+0x80> - 405941: 0f b6 c9 movzbl %cl,%ecx - 405944: 83 e9 30 sub $0x30,%ecx - 405947: 83 f9 09 cmp $0x9,%ecx - 40594a: 77 df ja 40592b <_nl_normalize_codeset+0x8b> - 40594c: 48 83 c7 01 add $0x1,%rdi - 405950: 41 88 10 mov %dl,(%r8) - 405953: 49 83 c0 01 add $0x1,%r8 - 405957: 49 39 fc cmp %rdi,%r12 - 40595a: 75 d8 jne 405934 <_nl_normalize_codeset+0x94> - 40595c: 41 c6 00 00 movb $0x0,(%r8) - 405960: 48 83 c4 08 add $0x8,%rsp - 405964: 5b pop %rbx - 405965: 5d pop %rbp - 405966: 41 5c pop %r12 - 405968: 41 5d pop %r13 - 40596a: c3 retq - 40596b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 405970: 48 83 c7 04 add $0x4,%rdi - 405974: e8 97 80 01 00 callq 41da10 <__libc_malloc> - 405979: 48 85 c0 test %rax,%rax - 40597c: 74 e2 je 405960 <_nl_normalize_codeset+0xc0> - 40597e: 4d 85 ed test %r13,%r13 - 405981: c7 00 69 73 6f 00 movl $0x6f7369,(%rax) - 405987: 4c 8d 40 03 lea 0x3(%rax),%r8 - 40598b: 74 cf je 40595c <_nl_normalize_codeset+0xbc> - 40598d: 48 8b 2d 54 cd 0a 00 mov 0xacd54(%rip),%rbp # 4b26e8 <_nl_C_locobj+0x68> - 405994: 4e 8d 24 2b lea (%rbx,%r13,1),%r12 - 405998: e9 75 ff ff ff jmpq 405912 <_nl_normalize_codeset+0x72> - 40599d: bf 04 00 00 00 mov $0x4,%edi - 4059a2: e8 69 80 01 00 callq 41da10 <__libc_malloc> - 4059a7: 48 85 c0 test %rax,%rax - 4059aa: 75 d2 jne 40597e <_nl_normalize_codeset+0xde> - 4059ac: eb b2 jmp 405960 <_nl_normalize_codeset+0xc0> - 4059ae: 66 90 xchg %ax,%ax - -00000000004059b0 <_nl_explode_name>: - 4059b0: 41 56 push %r14 - 4059b2: 41 55 push %r13 - 4059b4: 41 54 push %r12 - 4059b6: 55 push %rbp - 4059b7: 53 push %rbx - 4059b8: 48 83 ec 20 sub $0x20,%rsp - 4059bc: 48 c7 02 00 00 00 00 movq $0x0,(%rdx) - 4059c3: 48 c7 01 00 00 00 00 movq $0x0,(%rcx) - 4059ca: 49 c7 00 00 00 00 00 movq $0x0,(%r8) - 4059d1: 49 c7 01 00 00 00 00 movq $0x0,(%r9) - 4059d8: 48 89 3e mov %rdi,(%rsi) - 4059db: 0f b6 07 movzbl (%rdi),%eax - 4059de: a8 bf test $0xbf,%al - 4059e0: 0f 84 aa 01 00 00 je 405b90 <_nl_explode_name+0x1e0> - 4059e6: 3c 5f cmp $0x5f,%al - 4059e8: 0f 84 a2 01 00 00 je 405b90 <_nl_explode_name+0x1e0> - 4059ee: 3c 2e cmp $0x2e,%al - 4059f0: 0f 84 9a 01 00 00 je 405b90 <_nl_explode_name+0x1e0> - 4059f6: 48 89 fb mov %rdi,%rbx - 4059f9: eb 1f jmp 405a1a <_nl_explode_name+0x6a> - 4059fb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 405a00: 40 80 fe 5f cmp $0x5f,%sil - 405a04: 74 20 je 405a26 <_nl_explode_name+0x76> - 405a06: 40 80 fe 40 cmp $0x40,%sil - 405a0a: 0f 84 10 01 00 00 je 405b20 <_nl_explode_name+0x170> - 405a10: 40 80 fe 2e cmp $0x2e,%sil - 405a14: 0f 84 06 01 00 00 je 405b20 <_nl_explode_name+0x170> - 405a1a: 48 83 c3 01 add $0x1,%rbx - 405a1e: 0f b6 33 movzbl (%rbx),%esi - 405a21: 40 84 f6 test %sil,%sil - 405a24: 75 da jne 405a00 <_nl_explode_name+0x50> - 405a26: 48 39 df cmp %rbx,%rdi - 405a29: 0f 84 61 01 00 00 je 405b90 <_nl_explode_name+0x1e0> - 405a2f: 40 80 fe 5f cmp $0x5f,%sil - 405a33: 0f 85 ec 00 00 00 jne 405b25 <_nl_explode_name+0x175> - 405a39: 48 8d 43 01 lea 0x1(%rbx),%rax - 405a3d: c6 03 00 movb $0x0,(%rbx) - 405a40: 48 89 01 mov %rax,(%rcx) - 405a43: 0f b6 73 01 movzbl 0x1(%rbx),%esi - 405a47: 40 f6 c6 bf test $0xbf,%sil - 405a4b: 75 10 jne 405a5d <_nl_explode_name+0xad> - 405a4d: eb 14 jmp 405a63 <_nl_explode_name+0xb3> - 405a4f: 90 nop - 405a50: 48 83 c0 01 add $0x1,%rax - 405a54: 0f b6 30 movzbl (%rax),%esi - 405a57: 40 f6 c6 bf test $0xbf,%sil - 405a5b: 74 06 je 405a63 <_nl_explode_name+0xb3> - 405a5d: 40 80 fe 2e cmp $0x2e,%sil - 405a61: 75 ed jne 405a50 <_nl_explode_name+0xa0> - 405a63: 40 80 fe 2e cmp $0x2e,%sil - 405a67: 48 89 c3 mov %rax,%rbx - 405a6a: 41 bd 06 00 00 00 mov $0x6,%r13d - 405a70: bd 04 00 00 00 mov $0x4,%ebp - 405a75: 0f 85 bc 00 00 00 jne 405b37 <_nl_explode_name+0x187> - 405a7b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 405a80: 48 8d 7b 01 lea 0x1(%rbx),%rdi - 405a84: c6 03 00 movb $0x0,(%rbx) - 405a87: 49 89 38 mov %rdi,(%r8) - 405a8a: 0f b6 73 01 movzbl 0x1(%rbx),%esi - 405a8e: 40 f6 c6 bf test $0xbf,%sil - 405a92: 0f 84 5a 01 00 00 je 405bf2 <_nl_explode_name+0x242> - 405a98: 49 89 fc mov %rdi,%r12 - 405a9b: eb 06 jmp 405aa3 <_nl_explode_name+0xf3> - 405a9d: 0f 1f 00 nopl (%rax) - 405aa0: 49 89 dc mov %rbx,%r12 - 405aa3: 41 f6 44 24 01 bf testb $0xbf,0x1(%r12) - 405aa9: 49 8d 5c 24 01 lea 0x1(%r12),%rbx - 405aae: 75 f0 jne 405aa0 <_nl_explode_name+0xf0> - 405ab0: 48 39 df cmp %rbx,%rdi - 405ab3: 4c 89 0c 24 mov %r9,(%rsp) - 405ab7: 0f 84 40 01 00 00 je 405bfd <_nl_explode_name+0x24d> - 405abd: 48 89 de mov %rbx,%rsi - 405ac0: 4c 89 44 24 18 mov %r8,0x18(%rsp) - 405ac5: 48 89 4c 24 10 mov %rcx,0x10(%rsp) - 405aca: 48 29 fe sub %rdi,%rsi - 405acd: 48 89 54 24 08 mov %rdx,0x8(%rsp) - 405ad2: e8 c9 fd ff ff callq 4058a0 <_nl_normalize_codeset> - 405ad7: 4c 8b 0c 24 mov (%rsp),%r9 - 405adb: 48 85 c0 test %rax,%rax - 405ade: 49 89 c6 mov %rax,%r14 - 405ae1: 49 89 01 mov %rax,(%r9) - 405ae4: 0f 84 1b 01 00 00 je 405c05 <_nl_explode_name+0x255> - 405aea: 4c 8b 44 24 18 mov 0x18(%rsp),%r8 - 405aef: 48 89 c6 mov %rax,%rsi - 405af2: 49 8b 38 mov (%r8),%rdi - 405af5: 4c 89 04 24 mov %r8,(%rsp) - 405af9: e8 62 a8 ff ff callq 400360 <__rela_iplt_end+0x98> - 405afe: 85 c0 test %eax,%eax - 405b00: 4c 8b 04 24 mov (%rsp),%r8 - 405b04: 48 8b 54 24 08 mov 0x8(%rsp),%rdx - 405b09: 48 8b 4c 24 10 mov 0x10(%rsp),%rcx - 405b0e: 0f 84 ac 00 00 00 je 405bc0 <_nl_explode_name+0x210> - 405b14: 83 cd 03 or $0x3,%ebp - 405b17: 41 0f b6 74 24 01 movzbl 0x1(%r12),%esi - 405b1d: eb 18 jmp 405b37 <_nl_explode_name+0x187> - 405b1f: 90 nop - 405b20: 48 39 df cmp %rbx,%rdi - 405b23: 74 6b je 405b90 <_nl_explode_name+0x1e0> - 405b25: 31 ed xor %ebp,%ebp - 405b27: 40 80 fe 2e cmp $0x2e,%sil - 405b2b: 41 bd 02 00 00 00 mov $0x2,%r13d - 405b31: 0f 84 49 ff ff ff je 405a80 <_nl_explode_name+0xd0> - 405b37: 40 80 fe 40 cmp $0x40,%sil - 405b3b: 74 3b je 405b78 <_nl_explode_name+0x1c8> - 405b3d: 48 8b 01 mov (%rcx),%rax - 405b40: 48 85 c0 test %rax,%rax - 405b43: 74 0b je 405b50 <_nl_explode_name+0x1a0> - 405b45: 89 ea mov %ebp,%edx - 405b47: 83 e2 fb and $0xfffffffb,%edx - 405b4a: 80 38 00 cmpb $0x0,(%rax) - 405b4d: 0f 44 ea cmove %edx,%ebp - 405b50: 49 8b 10 mov (%r8),%rdx - 405b53: 89 e8 mov %ebp,%eax - 405b55: 48 85 d2 test %rdx,%rdx - 405b58: 74 0b je 405b65 <_nl_explode_name+0x1b5> - 405b5a: 89 e9 mov %ebp,%ecx - 405b5c: 83 e1 fd and $0xfffffffd,%ecx - 405b5f: 80 3a 00 cmpb $0x0,(%rdx) - 405b62: 0f 44 c1 cmove %ecx,%eax - 405b65: 48 83 c4 20 add $0x20,%rsp - 405b69: 5b pop %rbx - 405b6a: 5d pop %rbp - 405b6b: 41 5c pop %r12 - 405b6d: 41 5d pop %r13 - 405b6f: 41 5e pop %r14 - 405b71: c3 retq - 405b72: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 405b78: 48 8d 43 01 lea 0x1(%rbx),%rax - 405b7c: c6 03 00 movb $0x0,(%rbx) - 405b7f: 48 89 02 mov %rax,(%rdx) - 405b82: 89 e8 mov %ebp,%eax - 405b84: 83 c8 08 or $0x8,%eax - 405b87: 80 7b 01 00 cmpb $0x0,0x1(%rbx) - 405b8b: 0f 45 e8 cmovne %eax,%ebp - 405b8e: eb ad jmp 405b3d <_nl_explode_name+0x18d> - 405b90: 31 f6 xor %esi,%esi - 405b92: 4c 89 44 24 10 mov %r8,0x10(%rsp) - 405b97: 48 89 4c 24 08 mov %rcx,0x8(%rsp) - 405b9c: 48 89 14 24 mov %rdx,(%rsp) - 405ba0: 31 ed xor %ebp,%ebp - 405ba2: e8 29 6e 02 00 callq 42c9d0 <__rawmemchr> - 405ba7: 48 8b 14 24 mov (%rsp),%rdx - 405bab: 48 89 c3 mov %rax,%rbx - 405bae: 0f b6 30 movzbl (%rax),%esi - 405bb1: 48 8b 4c 24 08 mov 0x8(%rsp),%rcx - 405bb6: 4c 8b 44 24 10 mov 0x10(%rsp),%r8 - 405bbb: e9 77 ff ff ff jmpq 405b37 <_nl_explode_name+0x187> - 405bc0: 4c 89 f7 mov %r14,%rdi - 405bc3: 4c 89 44 24 10 mov %r8,0x10(%rsp) - 405bc8: 48 89 4c 24 08 mov %rcx,0x8(%rsp) - 405bcd: 48 89 14 24 mov %rdx,(%rsp) - 405bd1: 44 89 ed mov %r13d,%ebp - 405bd4: e8 d7 81 01 00 callq 41ddb0 <__cfree> - 405bd9: 41 0f b6 74 24 01 movzbl 0x1(%r12),%esi - 405bdf: 48 8b 14 24 mov (%rsp),%rdx - 405be3: 48 8b 4c 24 08 mov 0x8(%rsp),%rcx - 405be8: 4c 8b 44 24 10 mov 0x10(%rsp),%r8 - 405bed: e9 45 ff ff ff jmpq 405b37 <_nl_explode_name+0x187> - 405bf2: 44 89 ed mov %r13d,%ebp - 405bf5: 48 89 fb mov %rdi,%rbx - 405bf8: e9 3a ff ff ff jmpq 405b37 <_nl_explode_name+0x187> - 405bfd: 44 89 ed mov %r13d,%ebp - 405c00: e9 32 ff ff ff jmpq 405b37 <_nl_explode_name+0x187> - 405c05: b8 ff ff ff ff mov $0xffffffff,%eax - 405c0a: e9 56 ff ff ff jmpq 405b65 <_nl_explode_name+0x1b5> - 405c0f: 90 nop - -0000000000405c10 <__gettext_free_exp>: - 405c10: 48 85 ff test %rdi,%rdi - 405c13: 0f 84 af 06 00 00 je 4062c8 <__gettext_free_exp+0x6b8> - 405c19: 41 57 push %r15 - 405c1b: 41 56 push %r14 - 405c1d: 41 55 push %r13 - 405c1f: 41 54 push %r12 - 405c21: 55 push %rbp - 405c22: 53 push %rbx - 405c23: 48 89 fb mov %rdi,%rbx - 405c26: 48 83 ec 08 sub $0x8,%rsp - 405c2a: 8b 07 mov (%rdi),%eax - 405c2c: 83 f8 02 cmp $0x2,%eax - 405c2f: 74 56 je 405c87 <__gettext_free_exp+0x77> - 405c31: 83 f8 03 cmp $0x3,%eax - 405c34: 74 22 je 405c58 <__gettext_free_exp+0x48> - 405c36: 83 f8 01 cmp $0x1,%eax - 405c39: 74 7b je 405cb6 <__gettext_free_exp+0xa6> - 405c3b: 48 83 c4 08 add $0x8,%rsp - 405c3f: 48 89 df mov %rbx,%rdi - 405c42: 5b pop %rbx - 405c43: 5d pop %rbp - 405c44: 41 5c pop %r12 - 405c46: 41 5d pop %r13 - 405c48: 41 5e pop %r14 - 405c4a: 41 5f pop %r15 - 405c4c: e9 5f 81 01 00 jmpq 41ddb0 <__cfree> - 405c51: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 405c58: 48 8b 6f 18 mov 0x18(%rdi),%rbp - 405c5c: 48 85 ed test %rbp,%rbp - 405c5f: 74 26 je 405c87 <__gettext_free_exp+0x77> - 405c61: 8b 45 00 mov 0x0(%rbp),%eax - 405c64: 83 f8 02 cmp $0x2,%eax - 405c67: 0f 84 6c 03 00 00 je 405fd9 <__gettext_free_exp+0x3c9> - 405c6d: 83 f8 03 cmp $0x3,%eax - 405c70: 0f 84 5a 03 00 00 je 405fd0 <__gettext_free_exp+0x3c0> - 405c76: 83 f8 01 cmp $0x1,%eax - 405c79: 0f 84 63 03 00 00 je 405fe2 <__gettext_free_exp+0x3d2> - 405c7f: 48 89 ef mov %rbp,%rdi - 405c82: e8 29 81 01 00 callq 41ddb0 <__cfree> - 405c87: 48 8b 6b 10 mov 0x10(%rbx),%rbp - 405c8b: 48 85 ed test %rbp,%rbp - 405c8e: 74 26 je 405cb6 <__gettext_free_exp+0xa6> - 405c90: 8b 45 00 mov 0x0(%rbp),%eax - 405c93: 83 f8 02 cmp $0x2,%eax - 405c96: 0f 84 5d 01 00 00 je 405df9 <__gettext_free_exp+0x1e9> - 405c9c: 83 f8 03 cmp $0x3,%eax - 405c9f: 0f 84 4b 01 00 00 je 405df0 <__gettext_free_exp+0x1e0> - 405ca5: 83 f8 01 cmp $0x1,%eax - 405ca8: 0f 84 7b 01 00 00 je 405e29 <__gettext_free_exp+0x219> - 405cae: 48 89 ef mov %rbp,%rdi - 405cb1: e8 fa 80 01 00 callq 41ddb0 <__cfree> - 405cb6: 48 8b 6b 08 mov 0x8(%rbx),%rbp - 405cba: 48 85 ed test %rbp,%rbp - 405cbd: 0f 84 78 ff ff ff je 405c3b <__gettext_free_exp+0x2b> - 405cc3: 8b 45 00 mov 0x0(%rbp),%eax - 405cc6: 83 f8 02 cmp $0x2,%eax - 405cc9: 74 4b je 405d16 <__gettext_free_exp+0x106> - 405ccb: 83 f8 03 cmp $0x3,%eax - 405cce: 0f 84 cc 03 00 00 je 4060a0 <__gettext_free_exp+0x490> - 405cd4: 83 f8 01 cmp $0x1,%eax - 405cd7: 74 6d je 405d46 <__gettext_free_exp+0x136> - 405cd9: 48 89 ef mov %rbp,%rdi - 405cdc: e8 cf 80 01 00 callq 41ddb0 <__cfree> - 405ce1: e9 55 ff ff ff jmpq 405c3b <__gettext_free_exp+0x2b> - 405ce6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 405ced: 00 00 00 - 405cf0: 49 8b 7c 24 18 mov 0x18(%r12),%rdi - 405cf5: e8 16 ff ff ff callq 405c10 <__gettext_free_exp> - 405cfa: 49 8b 7c 24 10 mov 0x10(%r12),%rdi - 405cff: e8 0c ff ff ff callq 405c10 <__gettext_free_exp> - 405d04: 49 8b 7c 24 08 mov 0x8(%r12),%rdi - 405d09: e8 02 ff ff ff callq 405c10 <__gettext_free_exp> - 405d0e: 4c 89 e7 mov %r12,%rdi - 405d11: e8 9a 80 01 00 callq 41ddb0 <__cfree> - 405d16: 4c 8b 65 10 mov 0x10(%rbp),%r12 - 405d1a: 4d 85 e4 test %r12,%r12 - 405d1d: 74 27 je 405d46 <__gettext_free_exp+0x136> - 405d1f: 41 8b 04 24 mov (%r12),%eax - 405d23: 83 f8 02 cmp $0x2,%eax - 405d26: 0f 84 36 02 00 00 je 405f62 <__gettext_free_exp+0x352> - 405d2c: 83 f8 03 cmp $0x3,%eax - 405d2f: 0f 84 23 02 00 00 je 405f58 <__gettext_free_exp+0x348> - 405d35: 83 f8 01 cmp $0x1,%eax - 405d38: 0f 84 55 02 00 00 je 405f93 <__gettext_free_exp+0x383> - 405d3e: 4c 89 e7 mov %r12,%rdi - 405d41: e8 6a 80 01 00 callq 41ddb0 <__cfree> - 405d46: 4c 8b 65 08 mov 0x8(%rbp),%r12 - 405d4a: 4d 85 e4 test %r12,%r12 - 405d4d: 74 8a je 405cd9 <__gettext_free_exp+0xc9> - 405d4f: 41 8b 04 24 mov (%r12),%eax - 405d53: 83 f8 02 cmp $0x2,%eax - 405d56: 74 22 je 405d7a <__gettext_free_exp+0x16a> - 405d58: 83 f8 03 cmp $0x3,%eax - 405d5b: 74 13 je 405d70 <__gettext_free_exp+0x160> - 405d5d: 83 f8 01 cmp $0x1,%eax - 405d60: 74 49 je 405dab <__gettext_free_exp+0x19b> - 405d62: 4c 89 e7 mov %r12,%rdi - 405d65: e8 46 80 01 00 callq 41ddb0 <__cfree> - 405d6a: e9 6a ff ff ff jmpq 405cd9 <__gettext_free_exp+0xc9> - 405d6f: 90 nop - 405d70: 49 8b 7c 24 18 mov 0x18(%r12),%rdi - 405d75: e8 96 fe ff ff callq 405c10 <__gettext_free_exp> - 405d7a: 4d 8b 6c 24 10 mov 0x10(%r12),%r13 - 405d7f: 4d 85 ed test %r13,%r13 - 405d82: 74 27 je 405dab <__gettext_free_exp+0x19b> - 405d84: 41 8b 45 00 mov 0x0(%r13),%eax - 405d88: 83 f8 02 cmp $0x2,%eax - 405d8b: 0f 84 b8 03 00 00 je 406149 <__gettext_free_exp+0x539> - 405d91: 83 f8 03 cmp $0x3,%eax - 405d94: 0f 84 a6 03 00 00 je 406140 <__gettext_free_exp+0x530> - 405d9a: 83 f8 01 cmp $0x1,%eax - 405d9d: 0f 84 af 03 00 00 je 406152 <__gettext_free_exp+0x542> - 405da3: 4c 89 ef mov %r13,%rdi - 405da6: e8 05 80 01 00 callq 41ddb0 <__cfree> - 405dab: 4d 8b 6c 24 08 mov 0x8(%r12),%r13 - 405db0: 4d 85 ed test %r13,%r13 - 405db3: 74 ad je 405d62 <__gettext_free_exp+0x152> - 405db5: 41 8b 45 00 mov 0x0(%r13),%eax - 405db9: 83 f8 02 cmp $0x2,%eax - 405dbc: 0f 84 b7 00 00 00 je 405e79 <__gettext_free_exp+0x269> - 405dc2: 83 f8 03 cmp $0x3,%eax - 405dc5: 0f 84 a5 00 00 00 je 405e70 <__gettext_free_exp+0x260> - 405dcb: 83 f8 01 cmp $0x1,%eax - 405dce: 0f 84 d4 00 00 00 je 405ea8 <__gettext_free_exp+0x298> - 405dd4: 4c 89 ef mov %r13,%rdi - 405dd7: e8 d4 7f 01 00 callq 41ddb0 <__cfree> - 405ddc: 4c 89 e7 mov %r12,%rdi - 405ddf: e8 cc 7f 01 00 callq 41ddb0 <__cfree> - 405de4: e9 f0 fe ff ff jmpq 405cd9 <__gettext_free_exp+0xc9> - 405de9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 405df0: 48 8b 7d 18 mov 0x18(%rbp),%rdi - 405df4: e8 17 fe ff ff callq 405c10 <__gettext_free_exp> - 405df9: 4c 8b 65 10 mov 0x10(%rbp),%r12 - 405dfd: 4d 85 e4 test %r12,%r12 - 405e00: 74 27 je 405e29 <__gettext_free_exp+0x219> - 405e02: 41 8b 04 24 mov (%r12),%eax - 405e06: 83 f8 02 cmp $0x2,%eax - 405e09: 0f 84 5b 04 00 00 je 40626a <__gettext_free_exp+0x65a> - 405e0f: 83 f8 03 cmp $0x3,%eax - 405e12: 0f 84 48 04 00 00 je 406260 <__gettext_free_exp+0x650> - 405e18: 83 f8 01 cmp $0x1,%eax - 405e1b: 0f 84 53 04 00 00 je 406274 <__gettext_free_exp+0x664> - 405e21: 4c 89 e7 mov %r12,%rdi - 405e24: e8 87 7f 01 00 callq 41ddb0 <__cfree> - 405e29: 4c 8b 65 08 mov 0x8(%rbp),%r12 - 405e2d: 4d 85 e4 test %r12,%r12 - 405e30: 0f 84 78 fe ff ff je 405cae <__gettext_free_exp+0x9e> - 405e36: 41 8b 04 24 mov (%r12),%eax - 405e3a: 83 f8 02 cmp $0x2,%eax - 405e3d: 0f 84 a7 00 00 00 je 405eea <__gettext_free_exp+0x2da> - 405e43: 83 f8 03 cmp $0x3,%eax - 405e46: 0f 84 94 00 00 00 je 405ee0 <__gettext_free_exp+0x2d0> - 405e4c: 83 f8 01 cmp $0x1,%eax - 405e4f: 0f 84 c6 00 00 00 je 405f1b <__gettext_free_exp+0x30b> - 405e55: 4c 89 e7 mov %r12,%rdi - 405e58: e8 53 7f 01 00 callq 41ddb0 <__cfree> - 405e5d: 48 89 ef mov %rbp,%rdi - 405e60: e8 4b 7f 01 00 callq 41ddb0 <__cfree> - 405e65: e9 4c fe ff ff jmpq 405cb6 <__gettext_free_exp+0xa6> - 405e6a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 405e70: 49 8b 7d 18 mov 0x18(%r13),%rdi - 405e74: e8 97 fd ff ff callq 405c10 <__gettext_free_exp> - 405e79: 4d 8b 75 10 mov 0x10(%r13),%r14 - 405e7d: 4d 85 f6 test %r14,%r14 - 405e80: 74 26 je 405ea8 <__gettext_free_exp+0x298> - 405e82: 41 8b 06 mov (%r14),%eax - 405e85: 83 f8 02 cmp $0x2,%eax - 405e88: 0f 84 bb 01 00 00 je 406049 <__gettext_free_exp+0x439> - 405e8e: 83 f8 03 cmp $0x3,%eax - 405e91: 0f 84 a9 01 00 00 je 406040 <__gettext_free_exp+0x430> - 405e97: 83 f8 01 cmp $0x1,%eax - 405e9a: 0f 84 b2 01 00 00 je 406052 <__gettext_free_exp+0x442> - 405ea0: 4c 89 f7 mov %r14,%rdi - 405ea3: e8 08 7f 01 00 callq 41ddb0 <__cfree> - 405ea8: 4d 8b 75 08 mov 0x8(%r13),%r14 - 405eac: 4d 85 f6 test %r14,%r14 - 405eaf: 0f 84 1f ff ff ff je 405dd4 <__gettext_free_exp+0x1c4> - 405eb5: 41 8b 06 mov (%r14),%eax - 405eb8: 83 f8 02 cmp $0x2,%eax - 405ebb: 0f 84 20 02 00 00 je 4060e1 <__gettext_free_exp+0x4d1> - 405ec1: 83 f8 03 cmp $0x3,%eax - 405ec4: 0f 84 0e 02 00 00 je 4060d8 <__gettext_free_exp+0x4c8> - 405eca: 83 f8 01 cmp $0x1,%eax - 405ecd: 0f 84 17 02 00 00 je 4060ea <__gettext_free_exp+0x4da> - 405ed3: 4c 89 f7 mov %r14,%rdi - 405ed6: e8 d5 7e 01 00 callq 41ddb0 <__cfree> - 405edb: e9 f4 fe ff ff jmpq 405dd4 <__gettext_free_exp+0x1c4> - 405ee0: 49 8b 7c 24 18 mov 0x18(%r12),%rdi - 405ee5: e8 26 fd ff ff callq 405c10 <__gettext_free_exp> - 405eea: 4d 8b 6c 24 10 mov 0x10(%r12),%r13 - 405eef: 4d 85 ed test %r13,%r13 - 405ef2: 74 27 je 405f1b <__gettext_free_exp+0x30b> - 405ef4: 41 8b 45 00 mov 0x0(%r13),%eax - 405ef8: 83 f8 02 cmp $0x2,%eax - 405efb: 0f 84 88 01 00 00 je 406089 <__gettext_free_exp+0x479> - 405f01: 83 f8 03 cmp $0x3,%eax - 405f04: 0f 84 76 01 00 00 je 406080 <__gettext_free_exp+0x470> - 405f0a: 83 f8 01 cmp $0x1,%eax - 405f0d: 0f 84 7f 01 00 00 je 406092 <__gettext_free_exp+0x482> - 405f13: 4c 89 ef mov %r13,%rdi - 405f16: e8 95 7e 01 00 callq 41ddb0 <__cfree> - 405f1b: 4d 8b 6c 24 08 mov 0x8(%r12),%r13 - 405f20: 4d 85 ed test %r13,%r13 - 405f23: 0f 84 2c ff ff ff je 405e55 <__gettext_free_exp+0x245> - 405f29: 41 8b 45 00 mov 0x0(%r13),%eax - 405f2d: 83 f8 02 cmp $0x2,%eax - 405f30: 0f 84 73 02 00 00 je 4061a9 <__gettext_free_exp+0x599> - 405f36: 83 f8 03 cmp $0x3,%eax - 405f39: 0f 84 61 02 00 00 je 4061a0 <__gettext_free_exp+0x590> - 405f3f: 83 f8 01 cmp $0x1,%eax - 405f42: 0f 84 6a 02 00 00 je 4061b2 <__gettext_free_exp+0x5a2> - 405f48: 4c 89 ef mov %r13,%rdi - 405f4b: e8 60 7e 01 00 callq 41ddb0 <__cfree> - 405f50: e9 00 ff ff ff jmpq 405e55 <__gettext_free_exp+0x245> - 405f55: 0f 1f 00 nopl (%rax) - 405f58: 49 8b 7c 24 18 mov 0x18(%r12),%rdi - 405f5d: e8 ae fc ff ff callq 405c10 <__gettext_free_exp> - 405f62: 4d 8b 6c 24 10 mov 0x10(%r12),%r13 - 405f67: 4d 85 ed test %r13,%r13 - 405f6a: 74 27 je 405f93 <__gettext_free_exp+0x383> - 405f6c: 41 8b 45 00 mov 0x0(%r13),%eax - 405f70: 83 f8 02 cmp $0x2,%eax - 405f73: 0f 84 f0 00 00 00 je 406069 <__gettext_free_exp+0x459> - 405f79: 83 f8 03 cmp $0x3,%eax - 405f7c: 0f 84 de 00 00 00 je 406060 <__gettext_free_exp+0x450> - 405f82: 83 f8 01 cmp $0x1,%eax - 405f85: 0f 84 e7 00 00 00 je 406072 <__gettext_free_exp+0x462> - 405f8b: 4c 89 ef mov %r13,%rdi - 405f8e: e8 1d 7e 01 00 callq 41ddb0 <__cfree> - 405f93: 4d 8b 6c 24 08 mov 0x8(%r12),%r13 - 405f98: 4d 85 ed test %r13,%r13 - 405f9b: 0f 84 9d fd ff ff je 405d3e <__gettext_free_exp+0x12e> - 405fa1: 41 8b 45 00 mov 0x0(%r13),%eax - 405fa5: 83 f8 02 cmp $0x2,%eax - 405fa8: 0f 84 5b 02 00 00 je 406209 <__gettext_free_exp+0x5f9> - 405fae: 83 f8 03 cmp $0x3,%eax - 405fb1: 0f 84 49 02 00 00 je 406200 <__gettext_free_exp+0x5f0> - 405fb7: 83 f8 01 cmp $0x1,%eax - 405fba: 0f 84 52 02 00 00 je 406212 <__gettext_free_exp+0x602> - 405fc0: 4c 89 ef mov %r13,%rdi - 405fc3: e8 e8 7d 01 00 callq 41ddb0 <__cfree> - 405fc8: e9 71 fd ff ff jmpq 405d3e <__gettext_free_exp+0x12e> - 405fcd: 0f 1f 00 nopl (%rax) - 405fd0: 48 8b 7d 18 mov 0x18(%rbp),%rdi - 405fd4: e8 37 fc ff ff callq 405c10 <__gettext_free_exp> - 405fd9: 48 8b 7d 10 mov 0x10(%rbp),%rdi - 405fdd: e8 2e fc ff ff callq 405c10 <__gettext_free_exp> - 405fe2: 4c 8b 65 08 mov 0x8(%rbp),%r12 - 405fe6: 4d 85 e4 test %r12,%r12 - 405fe9: 0f 84 90 fc ff ff je 405c7f <__gettext_free_exp+0x6f> - 405fef: 41 8b 04 24 mov (%r12),%eax - 405ff3: 83 f8 02 cmp $0x2,%eax - 405ff6: 74 22 je 40601a <__gettext_free_exp+0x40a> - 405ff8: 83 f8 03 cmp $0x3,%eax - 405ffb: 74 13 je 406010 <__gettext_free_exp+0x400> - 405ffd: 83 f8 01 cmp $0x1,%eax - 406000: 74 22 je 406024 <__gettext_free_exp+0x414> - 406002: 4c 89 e7 mov %r12,%rdi - 406005: e8 a6 7d 01 00 callq 41ddb0 <__cfree> - 40600a: e9 70 fc ff ff jmpq 405c7f <__gettext_free_exp+0x6f> - 40600f: 90 nop - 406010: 49 8b 7c 24 18 mov 0x18(%r12),%rdi - 406015: e8 f6 fb ff ff callq 405c10 <__gettext_free_exp> - 40601a: 49 8b 7c 24 10 mov 0x10(%r12),%rdi - 40601f: e8 ec fb ff ff callq 405c10 <__gettext_free_exp> - 406024: 49 8b 7c 24 08 mov 0x8(%r12),%rdi - 406029: e8 e2 fb ff ff callq 405c10 <__gettext_free_exp> - 40602e: 4c 89 e7 mov %r12,%rdi - 406031: e8 7a 7d 01 00 callq 41ddb0 <__cfree> - 406036: e9 44 fc ff ff jmpq 405c7f <__gettext_free_exp+0x6f> - 40603b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 406040: 49 8b 7e 18 mov 0x18(%r14),%rdi - 406044: e8 c7 fb ff ff callq 405c10 <__gettext_free_exp> - 406049: 49 8b 7e 10 mov 0x10(%r14),%rdi - 40604d: e8 be fb ff ff callq 405c10 <__gettext_free_exp> - 406052: 49 8b 7e 08 mov 0x8(%r14),%rdi - 406056: e8 b5 fb ff ff callq 405c10 <__gettext_free_exp> - 40605b: e9 40 fe ff ff jmpq 405ea0 <__gettext_free_exp+0x290> - 406060: 49 8b 7d 18 mov 0x18(%r13),%rdi - 406064: e8 a7 fb ff ff callq 405c10 <__gettext_free_exp> - 406069: 49 8b 7d 10 mov 0x10(%r13),%rdi - 40606d: e8 9e fb ff ff callq 405c10 <__gettext_free_exp> - 406072: 49 8b 7d 08 mov 0x8(%r13),%rdi - 406076: e8 95 fb ff ff callq 405c10 <__gettext_free_exp> - 40607b: e9 0b ff ff ff jmpq 405f8b <__gettext_free_exp+0x37b> - 406080: 49 8b 7d 18 mov 0x18(%r13),%rdi - 406084: e8 87 fb ff ff callq 405c10 <__gettext_free_exp> - 406089: 49 8b 7d 10 mov 0x10(%r13),%rdi - 40608d: e8 7e fb ff ff callq 405c10 <__gettext_free_exp> - 406092: 49 8b 7d 08 mov 0x8(%r13),%rdi - 406096: e8 75 fb ff ff callq 405c10 <__gettext_free_exp> - 40609b: e9 73 fe ff ff jmpq 405f13 <__gettext_free_exp+0x303> - 4060a0: 4c 8b 65 18 mov 0x18(%rbp),%r12 - 4060a4: 4d 85 e4 test %r12,%r12 - 4060a7: 0f 84 69 fc ff ff je 405d16 <__gettext_free_exp+0x106> - 4060ad: 41 8b 04 24 mov (%r12),%eax - 4060b1: 83 f8 02 cmp $0x2,%eax - 4060b4: 0f 84 40 fc ff ff je 405cfa <__gettext_free_exp+0xea> - 4060ba: 83 f8 03 cmp $0x3,%eax - 4060bd: 0f 84 2d fc ff ff je 405cf0 <__gettext_free_exp+0xe0> - 4060c3: 83 f8 01 cmp $0x1,%eax - 4060c6: 0f 85 42 fc ff ff jne 405d0e <__gettext_free_exp+0xfe> - 4060cc: e9 33 fc ff ff jmpq 405d04 <__gettext_free_exp+0xf4> - 4060d1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4060d8: 49 8b 7e 18 mov 0x18(%r14),%rdi - 4060dc: e8 2f fb ff ff callq 405c10 <__gettext_free_exp> - 4060e1: 49 8b 7e 10 mov 0x10(%r14),%rdi - 4060e5: e8 26 fb ff ff callq 405c10 <__gettext_free_exp> - 4060ea: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 4060ee: 4d 85 ff test %r15,%r15 - 4060f1: 0f 84 dc fd ff ff je 405ed3 <__gettext_free_exp+0x2c3> - 4060f7: 41 8b 07 mov (%r15),%eax - 4060fa: 83 f8 02 cmp $0x2,%eax - 4060fd: 74 2a je 406129 <__gettext_free_exp+0x519> - 4060ff: 83 f8 03 cmp $0x3,%eax - 406102: 74 1c je 406120 <__gettext_free_exp+0x510> - 406104: 83 f8 01 cmp $0x1,%eax - 406107: 74 29 je 406132 <__gettext_free_exp+0x522> - 406109: 4c 89 ff mov %r15,%rdi - 40610c: e8 9f 7c 01 00 callq 41ddb0 <__cfree> - 406111: e9 bd fd ff ff jmpq 405ed3 <__gettext_free_exp+0x2c3> - 406116: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 40611d: 00 00 00 - 406120: 49 8b 7f 18 mov 0x18(%r15),%rdi - 406124: e8 e7 fa ff ff callq 405c10 <__gettext_free_exp> - 406129: 49 8b 7f 10 mov 0x10(%r15),%rdi - 40612d: e8 de fa ff ff callq 405c10 <__gettext_free_exp> - 406132: 49 8b 7f 08 mov 0x8(%r15),%rdi - 406136: e8 d5 fa ff ff callq 405c10 <__gettext_free_exp> - 40613b: eb cc jmp 406109 <__gettext_free_exp+0x4f9> - 40613d: 0f 1f 00 nopl (%rax) - 406140: 49 8b 7d 18 mov 0x18(%r13),%rdi - 406144: e8 c7 fa ff ff callq 405c10 <__gettext_free_exp> - 406149: 49 8b 7d 10 mov 0x10(%r13),%rdi - 40614d: e8 be fa ff ff callq 405c10 <__gettext_free_exp> - 406152: 4d 8b 75 08 mov 0x8(%r13),%r14 - 406156: 4d 85 f6 test %r14,%r14 - 406159: 0f 84 44 fc ff ff je 405da3 <__gettext_free_exp+0x193> - 40615f: 41 8b 06 mov (%r14),%eax - 406162: 83 f8 02 cmp $0x2,%eax - 406165: 74 22 je 406189 <__gettext_free_exp+0x579> - 406167: 83 f8 03 cmp $0x3,%eax - 40616a: 74 14 je 406180 <__gettext_free_exp+0x570> - 40616c: 83 f8 01 cmp $0x1,%eax - 40616f: 74 21 je 406192 <__gettext_free_exp+0x582> - 406171: 4c 89 f7 mov %r14,%rdi - 406174: e8 37 7c 01 00 callq 41ddb0 <__cfree> - 406179: e9 25 fc ff ff jmpq 405da3 <__gettext_free_exp+0x193> - 40617e: 66 90 xchg %ax,%ax - 406180: 49 8b 7e 18 mov 0x18(%r14),%rdi - 406184: e8 87 fa ff ff callq 405c10 <__gettext_free_exp> - 406189: 49 8b 7e 10 mov 0x10(%r14),%rdi - 40618d: e8 7e fa ff ff callq 405c10 <__gettext_free_exp> - 406192: 49 8b 7e 08 mov 0x8(%r14),%rdi - 406196: e8 75 fa ff ff callq 405c10 <__gettext_free_exp> - 40619b: eb d4 jmp 406171 <__gettext_free_exp+0x561> - 40619d: 0f 1f 00 nopl (%rax) - 4061a0: 49 8b 7d 18 mov 0x18(%r13),%rdi - 4061a4: e8 67 fa ff ff callq 405c10 <__gettext_free_exp> - 4061a9: 49 8b 7d 10 mov 0x10(%r13),%rdi - 4061ad: e8 5e fa ff ff callq 405c10 <__gettext_free_exp> - 4061b2: 4d 8b 75 08 mov 0x8(%r13),%r14 - 4061b6: 4d 85 f6 test %r14,%r14 - 4061b9: 0f 84 89 fd ff ff je 405f48 <__gettext_free_exp+0x338> - 4061bf: 41 8b 06 mov (%r14),%eax - 4061c2: 83 f8 02 cmp $0x2,%eax - 4061c5: 74 22 je 4061e9 <__gettext_free_exp+0x5d9> - 4061c7: 83 f8 03 cmp $0x3,%eax - 4061ca: 74 14 je 4061e0 <__gettext_free_exp+0x5d0> - 4061cc: 83 f8 01 cmp $0x1,%eax - 4061cf: 74 21 je 4061f2 <__gettext_free_exp+0x5e2> - 4061d1: 4c 89 f7 mov %r14,%rdi - 4061d4: e8 d7 7b 01 00 callq 41ddb0 <__cfree> - 4061d9: e9 6a fd ff ff jmpq 405f48 <__gettext_free_exp+0x338> - 4061de: 66 90 xchg %ax,%ax - 4061e0: 49 8b 7e 18 mov 0x18(%r14),%rdi - 4061e4: e8 27 fa ff ff callq 405c10 <__gettext_free_exp> - 4061e9: 49 8b 7e 10 mov 0x10(%r14),%rdi - 4061ed: e8 1e fa ff ff callq 405c10 <__gettext_free_exp> - 4061f2: 49 8b 7e 08 mov 0x8(%r14),%rdi - 4061f6: e8 15 fa ff ff callq 405c10 <__gettext_free_exp> - 4061fb: eb d4 jmp 4061d1 <__gettext_free_exp+0x5c1> - 4061fd: 0f 1f 00 nopl (%rax) - 406200: 49 8b 7d 18 mov 0x18(%r13),%rdi - 406204: e8 07 fa ff ff callq 405c10 <__gettext_free_exp> - 406209: 49 8b 7d 10 mov 0x10(%r13),%rdi - 40620d: e8 fe f9 ff ff callq 405c10 <__gettext_free_exp> - 406212: 4d 8b 75 08 mov 0x8(%r13),%r14 - 406216: 4d 85 f6 test %r14,%r14 - 406219: 0f 84 a1 fd ff ff je 405fc0 <__gettext_free_exp+0x3b0> - 40621f: 41 8b 06 mov (%r14),%eax - 406222: 83 f8 02 cmp $0x2,%eax - 406225: 74 22 je 406249 <__gettext_free_exp+0x639> - 406227: 83 f8 03 cmp $0x3,%eax - 40622a: 74 14 je 406240 <__gettext_free_exp+0x630> - 40622c: 83 f8 01 cmp $0x1,%eax - 40622f: 74 21 je 406252 <__gettext_free_exp+0x642> - 406231: 4c 89 f7 mov %r14,%rdi - 406234: e8 77 7b 01 00 callq 41ddb0 <__cfree> - 406239: e9 82 fd ff ff jmpq 405fc0 <__gettext_free_exp+0x3b0> - 40623e: 66 90 xchg %ax,%ax - 406240: 49 8b 7e 18 mov 0x18(%r14),%rdi - 406244: e8 c7 f9 ff ff callq 405c10 <__gettext_free_exp> - 406249: 49 8b 7e 10 mov 0x10(%r14),%rdi - 40624d: e8 be f9 ff ff callq 405c10 <__gettext_free_exp> - 406252: 49 8b 7e 08 mov 0x8(%r14),%rdi - 406256: e8 b5 f9 ff ff callq 405c10 <__gettext_free_exp> - 40625b: eb d4 jmp 406231 <__gettext_free_exp+0x621> - 40625d: 0f 1f 00 nopl (%rax) - 406260: 49 8b 7c 24 18 mov 0x18(%r12),%rdi - 406265: e8 a6 f9 ff ff callq 405c10 <__gettext_free_exp> - 40626a: 49 8b 7c 24 10 mov 0x10(%r12),%rdi - 40626f: e8 9c f9 ff ff callq 405c10 <__gettext_free_exp> - 406274: 4d 8b 6c 24 08 mov 0x8(%r12),%r13 - 406279: 4d 85 ed test %r13,%r13 - 40627c: 0f 84 9f fb ff ff je 405e21 <__gettext_free_exp+0x211> - 406282: 41 8b 45 00 mov 0x0(%r13),%eax - 406286: 83 f8 02 cmp $0x2,%eax - 406289: 74 26 je 4062b1 <__gettext_free_exp+0x6a1> - 40628b: 83 f8 03 cmp $0x3,%eax - 40628e: 74 18 je 4062a8 <__gettext_free_exp+0x698> - 406290: 83 f8 01 cmp $0x1,%eax - 406293: 74 25 je 4062ba <__gettext_free_exp+0x6aa> - 406295: 4c 89 ef mov %r13,%rdi - 406298: e8 13 7b 01 00 callq 41ddb0 <__cfree> - 40629d: e9 7f fb ff ff jmpq 405e21 <__gettext_free_exp+0x211> - 4062a2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4062a8: 49 8b 7d 18 mov 0x18(%r13),%rdi - 4062ac: e8 5f f9 ff ff callq 405c10 <__gettext_free_exp> - 4062b1: 49 8b 7d 10 mov 0x10(%r13),%rdi - 4062b5: e8 56 f9 ff ff callq 405c10 <__gettext_free_exp> - 4062ba: 49 8b 7d 08 mov 0x8(%r13),%rdi - 4062be: e8 4d f9 ff ff callq 405c10 <__gettext_free_exp> - 4062c3: eb d0 jmp 406295 <__gettext_free_exp+0x685> - 4062c5: 0f 1f 00 nopl (%rax) - 4062c8: f3 c3 repz retq - 4062ca: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - -00000000004062d0 : - 4062d0: 41 57 push %r15 - 4062d2: 41 56 push %r14 - 4062d4: 49 89 f6 mov %rsi,%r14 - 4062d7: 41 55 push %r13 - 4062d9: 41 54 push %r12 - 4062db: 55 push %rbp - 4062dc: 53 push %rbx - 4062dd: 48 83 ec 18 sub $0x18,%rsp - 4062e1: 48 8b 5e 08 mov 0x8(%rsi),%rbx - 4062e5: 48 85 db test %rbx,%rbx - 4062e8: 74 3e je 406328 - 4062ea: 48 8b 2e mov (%rsi),%rbp - 4062ed: 48 85 ed test %rbp,%rbp - 4062f0: 74 36 je 406328 - 4062f2: 41 89 fc mov %edi,%r12d - 4062f5: bf 20 00 00 00 mov $0x20,%edi - 4062fa: e8 11 77 01 00 callq 41da10 <__libc_malloc> - 4062ff: 48 85 c0 test %rax,%rax - 406302: 74 24 je 406328 - 406304: c7 00 02 00 00 00 movl $0x2,(%rax) - 40630a: 44 89 60 04 mov %r12d,0x4(%rax) - 40630e: 48 89 58 10 mov %rbx,0x10(%rax) - 406312: 48 89 68 08 mov %rbp,0x8(%rax) - 406316: 48 83 c4 18 add $0x18,%rsp - 40631a: 5b pop %rbx - 40631b: 5d pop %rbp - 40631c: 41 5c pop %r12 - 40631e: 41 5d pop %r13 - 406320: 41 5e pop %r14 - 406322: 41 5f pop %r15 - 406324: c3 retq - 406325: 0f 1f 00 nopl (%rax) - 406328: 31 ed xor %ebp,%ebp - 40632a: eb 28 jmp 406354 - 40632c: 0f 1f 40 00 nopl 0x0(%rax) - 406330: 83 f8 03 cmp $0x3,%eax - 406333: 0f 84 27 03 00 00 je 406660 - 406339: 83 f8 01 cmp $0x1,%eax - 40633c: 74 57 je 406395 - 40633e: 48 89 df mov %rbx,%rdi - 406341: e8 6a 7a 01 00 callq 41ddb0 <__cfree> - 406346: 48 83 ed 08 sub $0x8,%rbp - 40634a: 48 83 fd f0 cmp $0xfffffffffffffff0,%rbp - 40634e: 0f 84 ec 0c 00 00 je 407040 - 406354: 49 8b 5c 2e 08 mov 0x8(%r14,%rbp,1),%rbx - 406359: 48 85 db test %rbx,%rbx - 40635c: 74 e8 je 406346 - 40635e: 8b 03 mov (%rbx),%eax - 406360: 83 f8 02 cmp $0x2,%eax - 406363: 75 cb jne 406330 - 406365: 4c 8b 63 10 mov 0x10(%rbx),%r12 - 406369: 4d 85 e4 test %r12,%r12 - 40636c: 74 27 je 406395 - 40636e: 41 8b 04 24 mov (%r12),%eax - 406372: 83 f8 02 cmp $0x2,%eax - 406375: 0f 84 76 02 00 00 je 4065f1 - 40637b: 83 f8 03 cmp $0x3,%eax - 40637e: 0f 84 7c 0c 00 00 je 407000 - 406384: 83 f8 01 cmp $0x1,%eax - 406387: 0f 84 95 02 00 00 je 406622 - 40638d: 4c 89 e7 mov %r12,%rdi - 406390: e8 1b 7a 01 00 callq 41ddb0 <__cfree> - 406395: 4c 8b 63 08 mov 0x8(%rbx),%r12 - 406399: 4d 85 e4 test %r12,%r12 - 40639c: 74 a0 je 40633e - 40639e: 41 8b 04 24 mov (%r12),%eax - 4063a2: 83 f8 02 cmp $0x2,%eax - 4063a5: 74 4a je 4063f1 - 4063a7: 83 f8 03 cmp $0x3,%eax - 4063aa: 74 14 je 4063c0 - 4063ac: 83 f8 01 cmp $0x1,%eax - 4063af: 74 71 je 406422 - 4063b1: 4c 89 e7 mov %r12,%rdi - 4063b4: e8 f7 79 01 00 callq 41ddb0 <__cfree> - 4063b9: eb 83 jmp 40633e - 4063bb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4063c0: 4d 8b 6c 24 18 mov 0x18(%r12),%r13 - 4063c5: 4d 85 ed test %r13,%r13 - 4063c8: 74 27 je 4063f1 - 4063ca: 41 8b 45 00 mov 0x0(%r13),%eax - 4063ce: 83 f8 02 cmp $0x2,%eax - 4063d1: 0f 84 68 0a 00 00 je 406e3f - 4063d7: 83 f8 03 cmp $0x3,%eax - 4063da: 0f 84 30 0a 00 00 je 406e10 - 4063e0: 83 f8 01 cmp $0x1,%eax - 4063e3: 0f 84 85 0a 00 00 je 406e6e - 4063e9: 4c 89 ef mov %r13,%rdi - 4063ec: e8 bf 79 01 00 callq 41ddb0 <__cfree> - 4063f1: 4d 8b 6c 24 10 mov 0x10(%r12),%r13 - 4063f6: 4d 85 ed test %r13,%r13 - 4063f9: 74 27 je 406422 - 4063fb: 41 8b 45 00 mov 0x0(%r13),%eax - 4063ff: 83 f8 02 cmp $0x2,%eax - 406402: 0f 84 07 04 00 00 je 40680f - 406408: 83 f8 03 cmp $0x3,%eax - 40640b: 0f 84 cf 03 00 00 je 4067e0 - 406411: 83 f8 01 cmp $0x1,%eax - 406414: 0f 84 24 04 00 00 je 40683e - 40641a: 4c 89 ef mov %r13,%rdi - 40641d: e8 8e 79 01 00 callq 41ddb0 <__cfree> - 406422: 4d 8b 6c 24 08 mov 0x8(%r12),%r13 - 406427: 4d 85 ed test %r13,%r13 - 40642a: 74 85 je 4063b1 - 40642c: 41 8b 45 00 mov 0x0(%r13),%eax - 406430: 83 f8 02 cmp $0x2,%eax - 406433: 0f 84 c8 00 00 00 je 406501 - 406439: 83 f8 03 cmp $0x3,%eax - 40643c: 0f 84 0e 0b 00 00 je 406f50 - 406442: 83 f8 01 cmp $0x1,%eax - 406445: 0f 84 e5 00 00 00 je 406530 - 40644b: 4c 89 ef mov %r13,%rdi - 40644e: e8 5d 79 01 00 callq 41ddb0 <__cfree> - 406453: e9 59 ff ff ff jmpq 4063b1 - 406458: 48 8b 78 18 mov 0x18(%rax),%rdi - 40645c: 48 89 04 24 mov %rax,(%rsp) - 406460: e8 ab f7 ff ff callq 405c10 <__gettext_free_exp> - 406465: 48 8b 04 24 mov (%rsp),%rax - 406469: 48 8b 78 10 mov 0x10(%rax),%rdi - 40646d: 48 89 04 24 mov %rax,(%rsp) - 406471: e8 9a f7 ff ff callq 405c10 <__gettext_free_exp> - 406476: 48 8b 04 24 mov (%rsp),%rax - 40647a: 48 8b 78 08 mov 0x8(%rax),%rdi - 40647e: 48 89 04 24 mov %rax,(%rsp) - 406482: e8 89 f7 ff ff callq 405c10 <__gettext_free_exp> - 406487: 48 8b 04 24 mov (%rsp),%rax - 40648b: 48 89 c7 mov %rax,%rdi - 40648e: e8 1d 79 01 00 callq 41ddb0 <__cfree> - 406493: 49 8b 47 10 mov 0x10(%r15),%rax - 406497: 48 85 c0 test %rax,%rax - 40649a: 48 89 04 24 mov %rax,(%rsp) - 40649e: 74 26 je 4064c6 - 4064a0: 8b 00 mov (%rax),%eax - 4064a2: 83 f8 02 cmp $0x2,%eax - 4064a5: 0f 84 9d 20 00 00 je 408548 - 4064ab: 83 f8 03 cmp $0x3,%eax - 4064ae: 0f 84 87 20 00 00 je 40853b - 4064b4: 83 f8 01 cmp $0x1,%eax - 4064b7: 0f 84 bd 20 00 00 je 40857a - 4064bd: 48 8b 3c 24 mov (%rsp),%rdi - 4064c1: e8 ea 78 01 00 callq 41ddb0 <__cfree> - 4064c6: 49 8b 47 08 mov 0x8(%r15),%rax - 4064ca: 48 85 c0 test %rax,%rax - 4064cd: 48 89 04 24 mov %rax,(%rsp) - 4064d1: 74 26 je 4064f9 - 4064d3: 8b 00 mov (%rax),%eax - 4064d5: 83 f8 02 cmp $0x2,%eax - 4064d8: 0f 84 9f 14 00 00 je 40797d - 4064de: 83 f8 03 cmp $0x3,%eax - 4064e1: 0f 84 89 14 00 00 je 407970 - 4064e7: 83 f8 01 cmp $0x1,%eax - 4064ea: 0f 84 bf 14 00 00 je 4079af - 4064f0: 48 8b 3c 24 mov (%rsp),%rdi - 4064f4: e8 b7 78 01 00 callq 41ddb0 <__cfree> - 4064f9: 4c 89 ff mov %r15,%rdi - 4064fc: e8 af 78 01 00 callq 41ddb0 <__cfree> - 406501: 4d 8b 7d 10 mov 0x10(%r13),%r15 - 406505: 4d 85 ff test %r15,%r15 - 406508: 74 26 je 406530 - 40650a: 41 8b 07 mov (%r15),%eax - 40650d: 83 f8 02 cmp $0x2,%eax - 406510: 0f 84 f8 10 00 00 je 40760e - 406516: 83 f8 03 cmp $0x3,%eax - 406519: 0f 84 c1 10 00 00 je 4075e0 - 40651f: 83 f8 01 cmp $0x1,%eax - 406522: 0f 84 12 05 00 00 je 406a3a - 406528: 4c 89 ff mov %r15,%rdi - 40652b: e8 80 78 01 00 callq 41ddb0 <__cfree> - 406530: 4d 8b 7d 08 mov 0x8(%r13),%r15 - 406534: 4d 85 ff test %r15,%r15 - 406537: 0f 84 0e ff ff ff je 40644b - 40653d: 41 8b 07 mov (%r15),%eax - 406540: 83 f8 02 cmp $0x2,%eax - 406543: 0f 84 8a 01 00 00 je 4066d3 - 406549: 83 f8 03 cmp $0x3,%eax - 40654c: 0f 84 4e 01 00 00 je 4066a0 - 406552: 83 f8 01 cmp $0x1,%eax - 406555: 0f 84 ab 01 00 00 je 406706 - 40655b: 4c 89 ff mov %r15,%rdi - 40655e: e8 4d 78 01 00 callq 41ddb0 <__cfree> - 406563: e9 e3 fe ff ff jmpq 40644b - 406568: 49 8b 7f 18 mov 0x18(%r15),%rdi - 40656c: e8 9f f6 ff ff callq 405c10 <__gettext_free_exp> - 406571: 49 8b 7f 10 mov 0x10(%r15),%rdi - 406575: e8 96 f6 ff ff callq 405c10 <__gettext_free_exp> - 40657a: 49 8b 7f 08 mov 0x8(%r15),%rdi - 40657e: e8 8d f6 ff ff callq 405c10 <__gettext_free_exp> - 406583: 4c 89 ff mov %r15,%rdi - 406586: e8 25 78 01 00 callq 41ddb0 <__cfree> - 40658b: 4d 8b 7d 10 mov 0x10(%r13),%r15 - 40658f: 4d 85 ff test %r15,%r15 - 406592: 74 26 je 4065ba - 406594: 41 8b 07 mov (%r15),%eax - 406597: 83 f8 02 cmp $0x2,%eax - 40659a: 0f 84 67 20 00 00 je 408607 - 4065a0: 83 f8 03 cmp $0x3,%eax - 4065a3: 0f 84 55 20 00 00 je 4085fe - 4065a9: 83 f8 01 cmp $0x1,%eax - 4065ac: 0f 84 5e 20 00 00 je 408610 - 4065b2: 4c 89 ff mov %r15,%rdi - 4065b5: e8 f6 77 01 00 callq 41ddb0 <__cfree> - 4065ba: 4d 8b 7d 08 mov 0x8(%r13),%r15 - 4065be: 4d 85 ff test %r15,%r15 - 4065c1: 74 26 je 4065e9 - 4065c3: 41 8b 07 mov (%r15),%eax - 4065c6: 83 f8 02 cmp $0x2,%eax - 4065c9: 0f 84 aa 15 00 00 je 407b79 - 4065cf: 83 f8 03 cmp $0x3,%eax - 4065d2: 0f 84 98 15 00 00 je 407b70 - 4065d8: 83 f8 01 cmp $0x1,%eax - 4065db: 0f 84 c6 15 00 00 je 407ba7 - 4065e1: 4c 89 ff mov %r15,%rdi - 4065e4: e8 c7 77 01 00 callq 41ddb0 <__cfree> - 4065e9: 4c 89 ef mov %r13,%rdi - 4065ec: e8 bf 77 01 00 callq 41ddb0 <__cfree> - 4065f1: 4d 8b 6c 24 10 mov 0x10(%r12),%r13 - 4065f6: 4d 85 ed test %r13,%r13 - 4065f9: 74 27 je 406622 - 4065fb: 41 8b 45 00 mov 0x0(%r13),%eax - 4065ff: 83 f8 02 cmp $0x2,%eax - 406602: 0f 84 27 13 00 00 je 40792f - 406608: 83 f8 03 cmp $0x3,%eax - 40660b: 0f 84 ef 12 00 00 je 407900 - 406611: 83 f8 01 cmp $0x1,%eax - 406614: 0f 84 78 06 00 00 je 406c92 - 40661a: 4c 89 ef mov %r13,%rdi - 40661d: e8 8e 77 01 00 callq 41ddb0 <__cfree> - 406622: 4d 8b 6c 24 08 mov 0x8(%r12),%r13 - 406627: 4d 85 ed test %r13,%r13 - 40662a: 0f 84 5d fd ff ff je 40638d - 406630: 41 8b 45 00 mov 0x0(%r13),%eax - 406634: 83 f8 02 cmp $0x2,%eax - 406637: 0f 84 32 01 00 00 je 40676f - 40663d: 83 f8 03 cmp $0x3,%eax - 406640: 0f 84 fa 00 00 00 je 406740 - 406646: 83 f8 01 cmp $0x1,%eax - 406649: 0f 84 4f 01 00 00 je 40679e - 40664f: 4c 89 ef mov %r13,%rdi - 406652: e8 59 77 01 00 callq 41ddb0 <__cfree> - 406657: e9 31 fd ff ff jmpq 40638d - 40665c: 0f 1f 40 00 nopl 0x0(%rax) - 406660: 4c 8b 63 18 mov 0x18(%rbx),%r12 - 406664: 4d 85 e4 test %r12,%r12 - 406667: 0f 84 f8 fc ff ff je 406365 - 40666d: 41 8b 04 24 mov (%r12),%eax - 406671: 83 f8 02 cmp $0x2,%eax - 406674: 0f 84 47 09 00 00 je 406fc1 - 40667a: 83 f8 03 cmp $0x3,%eax - 40667d: 0f 84 0d 09 00 00 je 406f90 - 406683: 83 f8 01 cmp $0x1,%eax - 406686: 0f 84 73 02 00 00 je 4068ff - 40668c: 4c 89 e7 mov %r12,%rdi - 40668f: e8 1c 77 01 00 callq 41ddb0 <__cfree> - 406694: e9 cc fc ff ff jmpq 406365 - 406699: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4066a0: 49 8b 47 18 mov 0x18(%r15),%rax - 4066a4: 48 85 c0 test %rax,%rax - 4066a7: 48 89 04 24 mov %rax,(%rsp) - 4066ab: 74 26 je 4066d3 - 4066ad: 8b 00 mov (%rax),%eax - 4066af: 83 f8 02 cmp $0x2,%eax - 4066b2: 0f 84 45 13 00 00 je 4079fd - 4066b8: 83 f8 03 cmp $0x3,%eax - 4066bb: 0f 84 2f 13 00 00 je 4079f0 - 4066c1: 83 f8 01 cmp $0x1,%eax - 4066c4: 0f 84 65 13 00 00 je 407a2f - 4066ca: 48 8b 3c 24 mov (%rsp),%rdi - 4066ce: e8 dd 76 01 00 callq 41ddb0 <__cfree> - 4066d3: 49 8b 47 10 mov 0x10(%r15),%rax - 4066d7: 48 85 c0 test %rax,%rax - 4066da: 48 89 04 24 mov %rax,(%rsp) - 4066de: 74 26 je 406706 - 4066e0: 8b 00 mov (%rax),%eax - 4066e2: 83 f8 02 cmp $0x2,%eax - 4066e5: 0f 84 87 0a 00 00 je 407172 - 4066eb: 83 f8 03 cmp $0x3,%eax - 4066ee: 0f 84 4c 0a 00 00 je 407140 - 4066f4: 83 f8 01 cmp $0x1,%eax - 4066f7: 0f 84 a7 0a 00 00 je 4071a4 - 4066fd: 48 8b 3c 24 mov (%rsp),%rdi - 406701: e8 aa 76 01 00 callq 41ddb0 <__cfree> - 406706: 49 8b 47 08 mov 0x8(%r15),%rax - 40670a: 48 85 c0 test %rax,%rax - 40670d: 0f 84 48 fe ff ff je 40655b - 406713: 8b 10 mov (%rax),%edx - 406715: 83 fa 02 cmp $0x2,%edx - 406718: 0f 84 f8 0c 00 00 je 407416 - 40671e: 83 fa 03 cmp $0x3,%edx - 406721: 0f 84 b9 0c 00 00 je 4073e0 - 406727: 83 fa 01 cmp $0x1,%edx - 40672a: 0f 84 71 02 00 00 je 4069a1 - 406730: 48 89 c7 mov %rax,%rdi - 406733: e8 78 76 01 00 callq 41ddb0 <__cfree> - 406738: e9 1e fe ff ff jmpq 40655b - 40673d: 0f 1f 00 nopl (%rax) - 406740: 4d 8b 7d 18 mov 0x18(%r13),%r15 - 406744: 4d 85 ff test %r15,%r15 - 406747: 74 26 je 40676f - 406749: 41 8b 07 mov (%r15),%eax - 40674c: 83 f8 02 cmp $0x2,%eax - 40674f: 0f 84 54 16 00 00 je 407da9 - 406755: 83 f8 03 cmp $0x3,%eax - 406758: 0f 84 42 16 00 00 je 407da0 - 40675e: 83 f8 01 cmp $0x1,%eax - 406761: 0f 84 70 16 00 00 je 407dd7 - 406767: 4c 89 ff mov %r15,%rdi - 40676a: e8 41 76 01 00 callq 41ddb0 <__cfree> - 40676f: 4d 8b 7d 10 mov 0x10(%r13),%r15 - 406773: 4d 85 ff test %r15,%r15 - 406776: 74 26 je 40679e - 406778: 41 8b 07 mov (%r15),%eax - 40677b: 83 f8 02 cmp $0x2,%eax - 40677e: 0f 84 fa 0e 00 00 je 40767e - 406784: 83 f8 03 cmp $0x3,%eax - 406787: 0f 84 c3 0e 00 00 je 407650 - 40678d: 83 f8 01 cmp $0x1,%eax - 406790: 0f 84 1b 0f 00 00 je 4076b1 - 406796: 4c 89 ff mov %r15,%rdi - 406799: e8 12 76 01 00 callq 41ddb0 <__cfree> - 40679e: 4d 8b 7d 08 mov 0x8(%r13),%r15 - 4067a2: 4d 85 ff test %r15,%r15 - 4067a5: 0f 84 a4 fe ff ff je 40664f - 4067ab: 41 8b 07 mov (%r15),%eax - 4067ae: 83 f8 02 cmp $0x2,%eax - 4067b1: 0f 84 07 11 00 00 je 4078be - 4067b7: 83 f8 03 cmp $0x3,%eax - 4067ba: 0f 84 d0 10 00 00 je 407890 - 4067c0: 83 f8 01 cmp $0x1,%eax - 4067c3: 0f 84 11 04 00 00 je 406bda - 4067c9: 4c 89 ff mov %r15,%rdi - 4067cc: e8 df 75 01 00 callq 41ddb0 <__cfree> - 4067d1: e9 79 fe ff ff jmpq 40664f - 4067d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4067dd: 00 00 00 - 4067e0: 4d 8b 7d 18 mov 0x18(%r13),%r15 - 4067e4: 4d 85 ff test %r15,%r15 - 4067e7: 74 26 je 40680f - 4067e9: 41 8b 07 mov (%r15),%eax - 4067ec: 83 f8 02 cmp $0x2,%eax - 4067ef: 0f 84 f4 13 00 00 je 407be9 - 4067f5: 83 f8 03 cmp $0x3,%eax - 4067f8: 0f 84 e2 13 00 00 je 407be0 - 4067fe: 83 f8 01 cmp $0x1,%eax - 406801: 0f 84 10 14 00 00 je 407c17 - 406807: 4c 89 ff mov %r15,%rdi - 40680a: e8 a1 75 01 00 callq 41ddb0 <__cfree> - 40680f: 4d 8b 7d 10 mov 0x10(%r13),%r15 - 406813: 4d 85 ff test %r15,%r15 - 406816: 74 26 je 40683e - 406818: 41 8b 07 mov (%r15),%eax - 40681b: 83 f8 02 cmp $0x2,%eax - 40681e: 0f 84 62 0c 00 00 je 407486 - 406824: 83 f8 03 cmp $0x3,%eax - 406827: 0f 84 2b 0c 00 00 je 407458 - 40682d: 83 f8 01 cmp $0x1,%eax - 406830: 0f 84 83 0c 00 00 je 4074b9 - 406836: 4c 89 ff mov %r15,%rdi - 406839: e8 72 75 01 00 callq 41ddb0 <__cfree> - 40683e: 4d 8b 7d 08 mov 0x8(%r13),%r15 - 406842: 4d 85 ff test %r15,%r15 - 406845: 0f 84 cf fb ff ff je 40641a - 40684b: 41 8b 07 mov (%r15),%eax - 40684e: 83 f8 02 cmp $0x2,%eax - 406851: 0f 84 47 0d 00 00 je 40759e - 406857: 83 f8 03 cmp $0x3,%eax - 40685a: 0f 84 10 0d 00 00 je 407570 - 406860: 83 f8 01 cmp $0x1,%eax - 406863: 0f 84 bb 02 00 00 je 406b24 - 406869: 4c 89 ff mov %r15,%rdi - 40686c: e8 3f 75 01 00 callq 41ddb0 <__cfree> - 406871: e9 a4 fb ff ff jmpq 40641a - 406876: 49 8b 7f 18 mov 0x18(%r15),%rdi - 40687a: e8 91 f3 ff ff callq 405c10 <__gettext_free_exp> - 40687f: 49 8b 7f 10 mov 0x10(%r15),%rdi - 406883: e8 88 f3 ff ff callq 405c10 <__gettext_free_exp> - 406888: 49 8b 7f 08 mov 0x8(%r15),%rdi - 40688c: e8 7f f3 ff ff callq 405c10 <__gettext_free_exp> - 406891: 4c 89 ff mov %r15,%rdi - 406894: e8 17 75 01 00 callq 41ddb0 <__cfree> - 406899: 4d 8b 7d 10 mov 0x10(%r13),%r15 - 40689d: 4d 85 ff test %r15,%r15 - 4068a0: 74 26 je 4068c8 - 4068a2: 41 8b 07 mov (%r15),%eax - 4068a5: 83 f8 02 cmp $0x2,%eax - 4068a8: 0f 84 10 1d 00 00 je 4085be - 4068ae: 83 f8 03 cmp $0x3,%eax - 4068b1: 0f 84 fe 1c 00 00 je 4085b5 - 4068b7: 83 f8 01 cmp $0x1,%eax - 4068ba: 0f 84 07 1d 00 00 je 4085c7 - 4068c0: 4c 89 ff mov %r15,%rdi - 4068c3: e8 e8 74 01 00 callq 41ddb0 <__cfree> - 4068c8: 4d 8b 7d 08 mov 0x8(%r13),%r15 - 4068cc: 4d 85 ff test %r15,%r15 - 4068cf: 74 26 je 4068f7 - 4068d1: 41 8b 07 mov (%r15),%eax - 4068d4: 83 f8 02 cmp $0x2,%eax - 4068d7: 0f 84 7c 13 00 00 je 407c59 - 4068dd: 83 f8 03 cmp $0x3,%eax - 4068e0: 0f 84 6a 13 00 00 je 407c50 - 4068e6: 83 f8 01 cmp $0x1,%eax - 4068e9: 0f 84 98 13 00 00 je 407c87 - 4068ef: 4c 89 ff mov %r15,%rdi - 4068f2: e8 b9 74 01 00 callq 41ddb0 <__cfree> - 4068f7: 4c 89 ef mov %r13,%rdi - 4068fa: e8 b1 74 01 00 callq 41ddb0 <__cfree> - 4068ff: 4d 8b 6c 24 08 mov 0x8(%r12),%r13 - 406904: 4d 85 ed test %r13,%r13 - 406907: 0f 84 7f fd ff ff je 40668c - 40690d: 41 8b 45 00 mov 0x0(%r13),%eax - 406911: 83 f8 02 cmp $0x2,%eax - 406914: 0f 84 e5 03 00 00 je 406cff - 40691a: 83 f8 03 cmp $0x3,%eax - 40691d: 0f 84 ad 03 00 00 je 406cd0 - 406923: 83 f8 01 cmp $0x1,%eax - 406926: 0f 84 02 04 00 00 je 406d2e - 40692c: 4c 89 ef mov %r13,%rdi - 40692f: e8 7c 74 01 00 callq 41ddb0 <__cfree> - 406934: e9 53 fd ff ff jmpq 40668c - 406939: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 406940: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 406944: 48 89 44 24 08 mov %rax,0x8(%rsp) - 406949: 48 89 14 24 mov %rdx,(%rsp) - 40694d: e8 be f2 ff ff callq 405c10 <__gettext_free_exp> - 406952: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 406957: 48 8b 14 24 mov (%rsp),%rdx - 40695b: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 40695f: 48 89 44 24 08 mov %rax,0x8(%rsp) - 406964: 48 89 14 24 mov %rdx,(%rsp) - 406968: e8 a3 f2 ff ff callq 405c10 <__gettext_free_exp> - 40696d: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 406972: 48 8b 14 24 mov (%rsp),%rdx - 406976: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 40697a: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40697f: 48 89 14 24 mov %rdx,(%rsp) - 406983: e8 88 f2 ff ff callq 405c10 <__gettext_free_exp> - 406988: 48 8b 14 24 mov (%rsp),%rdx - 40698c: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 406991: 48 89 d7 mov %rdx,%rdi - 406994: 48 89 04 24 mov %rax,(%rsp) - 406998: e8 13 74 01 00 callq 41ddb0 <__cfree> - 40699d: 48 8b 04 24 mov (%rsp),%rax - 4069a1: 48 8b 78 08 mov 0x8(%rax),%rdi - 4069a5: 48 89 04 24 mov %rax,(%rsp) - 4069a9: e8 62 f2 ff ff callq 405c10 <__gettext_free_exp> - 4069ae: 48 8b 04 24 mov (%rsp),%rax - 4069b2: e9 79 fd ff ff jmpq 406730 - 4069b7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 4069be: 00 00 - 4069c0: 48 8b 04 24 mov (%rsp),%rax - 4069c4: 48 8b 78 18 mov 0x18(%rax),%rdi - 4069c8: e8 43 f2 ff ff callq 405c10 <__gettext_free_exp> - 4069cd: 48 8b 04 24 mov (%rsp),%rax - 4069d1: 48 8b 40 10 mov 0x10(%rax),%rax - 4069d5: 48 85 c0 test %rax,%rax - 4069d8: 74 25 je 4069ff - 4069da: 8b 10 mov (%rax),%edx - 4069dc: 83 fa 02 cmp $0x2,%edx - 4069df: 0f 84 fc 1c 00 00 je 4086e1 - 4069e5: 83 fa 03 cmp $0x3,%edx - 4069e8: 0f 84 e0 1c 00 00 je 4086ce - 4069ee: 83 fa 01 cmp $0x1,%edx - 4069f1: 0f 84 fd 1c 00 00 je 4086f4 - 4069f7: 48 89 c7 mov %rax,%rdi - 4069fa: e8 b1 73 01 00 callq 41ddb0 <__cfree> - 4069ff: 48 8b 04 24 mov (%rsp),%rax - 406a03: 48 8b 40 08 mov 0x8(%rax),%rax - 406a07: 48 85 c0 test %rax,%rax - 406a0a: 74 25 je 406a31 - 406a0c: 8b 10 mov (%rax),%edx - 406a0e: 83 fa 02 cmp $0x2,%edx - 406a11: 0f 84 8c 14 00 00 je 407ea3 - 406a17: 83 fa 03 cmp $0x3,%edx - 406a1a: 0f 84 70 14 00 00 je 407e90 - 406a20: 83 fa 01 cmp $0x1,%edx - 406a23: 0f 84 8d 14 00 00 je 407eb6 - 406a29: 48 89 c7 mov %rax,%rdi - 406a2c: e8 7f 73 01 00 callq 41ddb0 <__cfree> - 406a31: 48 8b 3c 24 mov (%rsp),%rdi - 406a35: e8 76 73 01 00 callq 41ddb0 <__cfree> - 406a3a: 49 8b 47 08 mov 0x8(%r15),%rax - 406a3e: 48 85 c0 test %rax,%rax - 406a41: 48 89 04 24 mov %rax,(%rsp) - 406a45: 0f 84 dd fa ff ff je 406528 - 406a4b: 8b 00 mov (%rax),%eax - 406a4d: 83 f8 02 cmp $0x2,%eax - 406a50: 0f 84 dc 08 00 00 je 407332 - 406a56: 83 f8 03 cmp $0x3,%eax - 406a59: 0f 84 a1 08 00 00 je 407300 - 406a5f: 83 f8 01 cmp $0x1,%eax - 406a62: 0f 84 fc 08 00 00 je 407364 - 406a68: 48 8b 3c 24 mov (%rsp),%rdi - 406a6c: e8 3f 73 01 00 callq 41ddb0 <__cfree> - 406a71: e9 b2 fa ff ff jmpq 406528 - 406a76: 48 8b 78 18 mov 0x18(%rax),%rdi - 406a7a: 48 89 44 24 08 mov %rax,0x8(%rsp) - 406a7f: e8 8c f1 ff ff callq 405c10 <__gettext_free_exp> - 406a84: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 406a89: 48 8b 78 10 mov 0x10(%rax),%rdi - 406a8d: 48 89 44 24 08 mov %rax,0x8(%rsp) - 406a92: e8 79 f1 ff ff callq 405c10 <__gettext_free_exp> - 406a97: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 406a9c: 48 8b 78 08 mov 0x8(%rax),%rdi - 406aa0: 48 89 44 24 08 mov %rax,0x8(%rsp) - 406aa5: e8 66 f1 ff ff callq 405c10 <__gettext_free_exp> - 406aaa: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 406aaf: 48 89 c7 mov %rax,%rdi - 406ab2: e8 f9 72 01 00 callq 41ddb0 <__cfree> - 406ab7: 48 8b 04 24 mov (%rsp),%rax - 406abb: 48 8b 40 10 mov 0x10(%rax),%rax - 406abf: 48 85 c0 test %rax,%rax - 406ac2: 74 25 je 406ae9 - 406ac4: 8b 10 mov (%rax),%edx - 406ac6: 83 fa 02 cmp $0x2,%edx - 406ac9: 0f 84 d4 1b 00 00 je 4086a3 - 406acf: 83 fa 03 cmp $0x3,%edx - 406ad2: 0f 84 b8 1b 00 00 je 408690 - 406ad8: 83 fa 01 cmp $0x1,%edx - 406adb: 0f 84 d5 1b 00 00 je 4086b6 - 406ae1: 48 89 c7 mov %rax,%rdi - 406ae4: e8 c7 72 01 00 callq 41ddb0 <__cfree> - 406ae9: 48 8b 04 24 mov (%rsp),%rax - 406aed: 48 8b 40 08 mov 0x8(%rax),%rax - 406af1: 48 85 c0 test %rax,%rax - 406af4: 74 25 je 406b1b - 406af6: 8b 10 mov (%rax),%edx - 406af8: 83 fa 02 cmp $0x2,%edx - 406afb: 0f 84 22 14 00 00 je 407f23 - 406b01: 83 fa 03 cmp $0x3,%edx - 406b04: 0f 84 06 14 00 00 je 407f10 - 406b0a: 83 fa 01 cmp $0x1,%edx - 406b0d: 0f 84 23 14 00 00 je 407f36 - 406b13: 48 89 c7 mov %rax,%rdi - 406b16: e8 95 72 01 00 callq 41ddb0 <__cfree> - 406b1b: 48 8b 3c 24 mov (%rsp),%rdi - 406b1f: e8 8c 72 01 00 callq 41ddb0 <__cfree> - 406b24: 49 8b 47 08 mov 0x8(%r15),%rax - 406b28: 48 85 c0 test %rax,%rax - 406b2b: 48 89 04 24 mov %rax,(%rsp) - 406b2f: 0f 84 34 fd ff ff je 406869 - 406b35: 8b 00 mov (%rax),%eax - 406b37: 83 f8 02 cmp $0x2,%eax - 406b3a: 0f 84 12 07 00 00 je 407252 - 406b40: 83 f8 03 cmp $0x3,%eax - 406b43: 0f 84 d7 06 00 00 je 407220 - 406b49: 83 f8 01 cmp $0x1,%eax - 406b4c: 0f 84 32 07 00 00 je 407284 - 406b52: 48 8b 3c 24 mov (%rsp),%rdi - 406b56: e8 55 72 01 00 callq 41ddb0 <__cfree> - 406b5b: e9 09 fd ff ff jmpq 406869 - 406b60: 48 8b 04 24 mov (%rsp),%rax - 406b64: 48 8b 78 18 mov 0x18(%rax),%rdi - 406b68: e8 a3 f0 ff ff callq 405c10 <__gettext_free_exp> - 406b6d: 48 8b 04 24 mov (%rsp),%rax - 406b71: 48 8b 40 10 mov 0x10(%rax),%rax - 406b75: 48 85 c0 test %rax,%rax - 406b78: 74 25 je 406b9f - 406b7a: 8b 10 mov (%rax),%edx - 406b7c: 83 fa 02 cmp $0x2,%edx - 406b7f: 0f 84 16 1c 00 00 je 40879b - 406b85: 83 fa 03 cmp $0x3,%edx - 406b88: 0f 84 fa 1b 00 00 je 408788 - 406b8e: 83 fa 01 cmp $0x1,%edx - 406b91: 0f 84 17 1c 00 00 je 4087ae - 406b97: 48 89 c7 mov %rax,%rdi - 406b9a: e8 11 72 01 00 callq 41ddb0 <__cfree> - 406b9f: 48 8b 04 24 mov (%rsp),%rax - 406ba3: 48 8b 40 08 mov 0x8(%rax),%rax - 406ba7: 48 85 c0 test %rax,%rax - 406baa: 74 25 je 406bd1 - 406bac: 8b 10 mov (%rax),%edx - 406bae: 83 fa 02 cmp $0x2,%edx - 406bb1: 0f 84 6c 12 00 00 je 407e23 - 406bb7: 83 fa 03 cmp $0x3,%edx - 406bba: 0f 84 50 12 00 00 je 407e10 - 406bc0: 83 fa 01 cmp $0x1,%edx - 406bc3: 0f 84 6d 12 00 00 je 407e36 - 406bc9: 48 89 c7 mov %rax,%rdi - 406bcc: e8 df 71 01 00 callq 41ddb0 <__cfree> - 406bd1: 48 8b 3c 24 mov (%rsp),%rdi - 406bd5: e8 d6 71 01 00 callq 41ddb0 <__cfree> - 406bda: 49 8b 47 08 mov 0x8(%r15),%rax - 406bde: 48 85 c0 test %rax,%rax - 406be1: 48 89 04 24 mov %rax,(%rsp) - 406be5: 0f 84 de fb ff ff je 4067c9 - 406beb: 8b 00 mov (%rax),%eax - 406bed: 83 f8 02 cmp $0x2,%eax - 406bf0: 0f 84 94 04 00 00 je 40708a - 406bf6: 83 f8 03 cmp $0x3,%eax - 406bf9: 0f 84 59 04 00 00 je 407058 - 406bff: 83 f8 01 cmp $0x1,%eax - 406c02: 0f 84 b4 04 00 00 je 4070bc - 406c08: 48 8b 3c 24 mov (%rsp),%rdi - 406c0c: e8 9f 71 01 00 callq 41ddb0 <__cfree> - 406c11: e9 b3 fb ff ff jmpq 4067c9 - 406c16: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 406c1d: 00 00 00 - 406c20: 49 8b 7f 18 mov 0x18(%r15),%rdi - 406c24: e8 e7 ef ff ff callq 405c10 <__gettext_free_exp> - 406c29: 49 8b 47 10 mov 0x10(%r15),%rax - 406c2d: 48 85 c0 test %rax,%rax - 406c30: 74 25 je 406c57 - 406c32: 8b 10 mov (%rax),%edx - 406c34: 83 fa 02 cmp $0x2,%edx - 406c37: 0f 84 d8 1b 00 00 je 408815 - 406c3d: 83 fa 03 cmp $0x3,%edx - 406c40: 0f 84 be 1b 00 00 je 408804 - 406c46: 83 fa 01 cmp $0x1,%edx - 406c49: 0f 84 d7 1b 00 00 je 408826 - 406c4f: 48 89 c7 mov %rax,%rdi - 406c52: e8 59 71 01 00 callq 41ddb0 <__cfree> - 406c57: 49 8b 47 08 mov 0x8(%r15),%rax - 406c5b: 48 85 c0 test %rax,%rax - 406c5e: 48 89 04 24 mov %rax,(%rsp) - 406c62: 74 26 je 406c8a - 406c64: 8b 00 mov (%rax),%eax - 406c66: 83 f8 02 cmp $0x2,%eax - 406c69: 0f 84 2e 14 00 00 je 40809d - 406c6f: 83 f8 03 cmp $0x3,%eax - 406c72: 0f 84 18 14 00 00 je 408090 - 406c78: 83 f8 01 cmp $0x1,%eax - 406c7b: 0f 84 4e 14 00 00 je 4080cf - 406c81: 48 8b 3c 24 mov (%rsp),%rdi - 406c85: e8 26 71 01 00 callq 41ddb0 <__cfree> - 406c8a: 4c 89 ff mov %r15,%rdi - 406c8d: e8 1e 71 01 00 callq 41ddb0 <__cfree> - 406c92: 4d 8b 7d 08 mov 0x8(%r13),%r15 - 406c96: 4d 85 ff test %r15,%r15 - 406c99: 0f 84 7b f9 ff ff je 40661a - 406c9f: 41 8b 07 mov (%r15),%eax - 406ca2: 83 f8 02 cmp $0x2,%eax - 406ca5: 0f 84 f3 0a 00 00 je 40779e - 406cab: 83 f8 03 cmp $0x3,%eax - 406cae: 0f 84 bc 0a 00 00 je 407770 - 406cb4: 83 f8 01 cmp $0x1,%eax - 406cb7: 0f 84 14 0b 00 00 je 4077d1 - 406cbd: 4c 89 ff mov %r15,%rdi - 406cc0: e8 eb 70 01 00 callq 41ddb0 <__cfree> - 406cc5: e9 50 f9 ff ff jmpq 40661a - 406cca: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 406cd0: 4d 8b 7d 18 mov 0x18(%r13),%r15 - 406cd4: 4d 85 ff test %r15,%r15 - 406cd7: 74 26 je 406cff - 406cd9: 41 8b 07 mov (%r15),%eax - 406cdc: 83 f8 02 cmp $0x2,%eax - 406cdf: 0f 84 5b 22 00 00 je 408f40 - 406ce5: 83 f8 03 cmp $0x3,%eax - 406ce8: 0f 84 49 22 00 00 je 408f37 - 406cee: 83 f8 01 cmp $0x1,%eax - 406cf1: 0f 84 52 22 00 00 je 408f49 - 406cf7: 4c 89 ff mov %r15,%rdi - 406cfa: e8 b1 70 01 00 callq 41ddb0 <__cfree> - 406cff: 4d 8b 7d 10 mov 0x10(%r13),%r15 - 406d03: 4d 85 ff test %r15,%r15 - 406d06: 74 26 je 406d2e - 406d08: 41 8b 07 mov (%r15),%eax - 406d0b: 83 f8 02 cmp $0x2,%eax - 406d0e: 0f 84 b5 0f 00 00 je 407cc9 - 406d14: 83 f8 03 cmp $0x3,%eax - 406d17: 0f 84 a3 0f 00 00 je 407cc0 - 406d1d: 83 f8 01 cmp $0x1,%eax - 406d20: 0f 84 d1 0f 00 00 je 407cf7 - 406d26: 4c 89 ff mov %r15,%rdi - 406d29: e8 82 70 01 00 callq 41ddb0 <__cfree> - 406d2e: 4d 8b 7d 08 mov 0x8(%r13),%r15 - 406d32: 4d 85 ff test %r15,%r15 - 406d35: 0f 84 f1 fb ff ff je 40692c - 406d3b: 41 8b 07 mov (%r15),%eax - 406d3e: 83 f8 02 cmp $0x2,%eax - 406d41: 74 56 je 406d99 - 406d43: 83 f8 03 cmp $0x3,%eax - 406d46: 0f 84 14 21 00 00 je 408e60 - 406d4c: 83 f8 01 cmp $0x1,%eax - 406d4f: 74 76 je 406dc7 - 406d51: 4c 89 ff mov %r15,%rdi - 406d54: e8 57 70 01 00 callq 41ddb0 <__cfree> - 406d59: e9 ce fb ff ff jmpq 40692c - 406d5e: 48 8b 78 18 mov 0x18(%rax),%rdi - 406d62: 48 89 04 24 mov %rax,(%rsp) - 406d66: e8 a5 ee ff ff callq 405c10 <__gettext_free_exp> - 406d6b: 48 8b 04 24 mov (%rsp),%rax - 406d6f: 48 8b 78 10 mov 0x10(%rax),%rdi - 406d73: 48 89 04 24 mov %rax,(%rsp) - 406d77: e8 94 ee ff ff callq 405c10 <__gettext_free_exp> - 406d7c: 48 8b 04 24 mov (%rsp),%rax - 406d80: 48 8b 78 08 mov 0x8(%rax),%rdi - 406d84: 48 89 04 24 mov %rax,(%rsp) - 406d88: e8 83 ee ff ff callq 405c10 <__gettext_free_exp> - 406d8d: 48 8b 04 24 mov (%rsp),%rax - 406d91: 48 89 c7 mov %rax,%rdi - 406d94: e8 17 70 01 00 callq 41ddb0 <__cfree> - 406d99: 49 8b 47 10 mov 0x10(%r15),%rax - 406d9d: 48 85 c0 test %rax,%rax - 406da0: 74 25 je 406dc7 - 406da2: 8b 10 mov (%rax),%edx - 406da4: 83 fa 02 cmp $0x2,%edx - 406da7: 0f 84 1b 16 00 00 je 4083c8 - 406dad: 83 fa 03 cmp $0x3,%edx - 406db0: 0f 84 01 16 00 00 je 4083b7 - 406db6: 83 fa 01 cmp $0x1,%edx - 406db9: 0f 84 1a 16 00 00 je 4083d9 - 406dbf: 48 89 c7 mov %rax,%rdi - 406dc2: e8 e9 6f 01 00 callq 41ddb0 <__cfree> - 406dc7: 49 8b 47 08 mov 0x8(%r15),%rax - 406dcb: 48 85 c0 test %rax,%rax - 406dce: 48 89 04 24 mov %rax,(%rsp) - 406dd2: 0f 84 79 ff ff ff je 406d51 - 406dd8: 8b 00 mov (%rax),%eax - 406dda: 83 f8 02 cmp $0x2,%eax - 406ddd: 0f 84 9a 0c 00 00 je 407a7d - 406de3: 83 f8 03 cmp $0x3,%eax - 406de6: 0f 84 84 0c 00 00 je 407a70 - 406dec: 83 f8 01 cmp $0x1,%eax - 406def: 0f 84 ba 0c 00 00 je 407aaf - 406df5: 48 8b 3c 24 mov (%rsp),%rdi - 406df9: e8 b2 6f 01 00 callq 41ddb0 <__cfree> - 406dfe: 4c 89 ff mov %r15,%rdi - 406e01: e8 aa 6f 01 00 callq 41ddb0 <__cfree> - 406e06: e9 21 fb ff ff jmpq 40692c - 406e0b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 406e10: 4d 8b 7d 18 mov 0x18(%r13),%r15 - 406e14: 4d 85 ff test %r15,%r15 - 406e17: 74 26 je 406e3f - 406e19: 41 8b 07 mov (%r15),%eax - 406e1c: 83 f8 02 cmp $0x2,%eax - 406e1f: 0f 84 73 20 00 00 je 408e98 - 406e25: 83 f8 03 cmp $0x3,%eax - 406e28: 0f 84 61 20 00 00 je 408e8f - 406e2e: 83 f8 01 cmp $0x1,%eax - 406e31: 0f 84 6a 20 00 00 je 408ea1 - 406e37: 4c 89 ff mov %r15,%rdi - 406e3a: e8 71 6f 01 00 callq 41ddb0 <__cfree> - 406e3f: 4d 8b 7d 10 mov 0x10(%r13),%r15 - 406e43: 4d 85 ff test %r15,%r15 - 406e46: 74 26 je 406e6e - 406e48: 41 8b 07 mov (%r15),%eax - 406e4b: 83 f8 02 cmp $0x2,%eax - 406e4e: 0f 84 e5 0e 00 00 je 407d39 - 406e54: 83 f8 03 cmp $0x3,%eax - 406e57: 0f 84 d3 0e 00 00 je 407d30 - 406e5d: 83 f8 01 cmp $0x1,%eax - 406e60: 0f 84 01 0f 00 00 je 407d67 - 406e66: 4c 89 ff mov %r15,%rdi - 406e69: e8 42 6f 01 00 callq 41ddb0 <__cfree> - 406e6e: 4d 8b 7d 08 mov 0x8(%r13),%r15 - 406e72: 4d 85 ff test %r15,%r15 - 406e75: 0f 84 6e f5 ff ff je 4063e9 - 406e7b: 41 8b 07 mov (%r15),%eax - 406e7e: 83 f8 02 cmp $0x2,%eax - 406e81: 74 56 je 406ed9 - 406e83: 83 f8 03 cmp $0x3,%eax - 406e86: 0f 84 7c 20 00 00 je 408f08 - 406e8c: 83 f8 01 cmp $0x1,%eax - 406e8f: 74 76 je 406f07 - 406e91: 4c 89 ff mov %r15,%rdi - 406e94: e8 17 6f 01 00 callq 41ddb0 <__cfree> - 406e99: e9 4b f5 ff ff jmpq 4063e9 - 406e9e: 48 8b 78 18 mov 0x18(%rax),%rdi - 406ea2: 48 89 04 24 mov %rax,(%rsp) - 406ea6: e8 65 ed ff ff callq 405c10 <__gettext_free_exp> - 406eab: 48 8b 04 24 mov (%rsp),%rax - 406eaf: 48 8b 78 10 mov 0x10(%rax),%rdi - 406eb3: 48 89 04 24 mov %rax,(%rsp) - 406eb7: e8 54 ed ff ff callq 405c10 <__gettext_free_exp> - 406ebc: 48 8b 04 24 mov (%rsp),%rax - 406ec0: 48 8b 78 08 mov 0x8(%rax),%rdi - 406ec4: 48 89 04 24 mov %rax,(%rsp) - 406ec8: e8 43 ed ff ff callq 405c10 <__gettext_free_exp> - 406ecd: 48 8b 04 24 mov (%rsp),%rax - 406ed1: 48 89 c7 mov %rax,%rdi - 406ed4: e8 d7 6e 01 00 callq 41ddb0 <__cfree> - 406ed9: 49 8b 47 10 mov 0x10(%r15),%rax - 406edd: 48 85 c0 test %rax,%rax - 406ee0: 74 25 je 406f07 - 406ee2: 8b 10 mov (%rax),%edx - 406ee4: 83 fa 02 cmp $0x2,%edx - 406ee7: 0f 84 9d 15 00 00 je 40848a - 406eed: 83 fa 03 cmp $0x3,%edx - 406ef0: 0f 84 83 15 00 00 je 408479 - 406ef6: 83 fa 01 cmp $0x1,%edx - 406ef9: 0f 84 9c 15 00 00 je 40849b - 406eff: 48 89 c7 mov %rax,%rdi - 406f02: e8 a9 6e 01 00 callq 41ddb0 <__cfree> - 406f07: 49 8b 47 08 mov 0x8(%r15),%rax - 406f0b: 48 85 c0 test %rax,%rax - 406f0e: 48 89 04 24 mov %rax,(%rsp) - 406f12: 0f 84 79 ff ff ff je 406e91 - 406f18: 8b 00 mov (%rax),%eax - 406f1a: 83 f8 02 cmp $0x2,%eax - 406f1d: 0f 84 da 0b 00 00 je 407afd - 406f23: 83 f8 03 cmp $0x3,%eax - 406f26: 0f 84 c4 0b 00 00 je 407af0 - 406f2c: 83 f8 01 cmp $0x1,%eax - 406f2f: 0f 84 fa 0b 00 00 je 407b2f - 406f35: 48 8b 3c 24 mov (%rsp),%rdi - 406f39: e8 72 6e 01 00 callq 41ddb0 <__cfree> - 406f3e: 4c 89 ff mov %r15,%rdi - 406f41: e8 6a 6e 01 00 callq 41ddb0 <__cfree> - 406f46: e9 9e f4 ff ff jmpq 4063e9 - 406f4b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 406f50: 4d 8b 7d 18 mov 0x18(%r13),%r15 - 406f54: 4d 85 ff test %r15,%r15 - 406f57: 0f 84 a4 f5 ff ff je 406501 - 406f5d: 41 8b 07 mov (%r15),%eax - 406f60: 83 f8 02 cmp $0x2,%eax - 406f63: 0f 84 2a f5 ff ff je 406493 - 406f69: 83 f8 03 cmp $0x3,%eax - 406f6c: 0f 84 3e 20 00 00 je 408fb0 - 406f72: 83 f8 01 cmp $0x1,%eax - 406f75: 0f 84 4b f5 ff ff je 4064c6 - 406f7b: 4c 89 ff mov %r15,%rdi - 406f7e: e8 2d 6e 01 00 callq 41ddb0 <__cfree> - 406f83: e9 79 f5 ff ff jmpq 406501 - 406f88: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 406f8f: 00 - 406f90: 4d 8b 6c 24 18 mov 0x18(%r12),%r13 - 406f95: 4d 85 ed test %r13,%r13 - 406f98: 74 27 je 406fc1 - 406f9a: 41 8b 45 00 mov 0x0(%r13),%eax - 406f9e: 83 f8 02 cmp $0x2,%eax - 406fa1: 0f 84 f2 12 00 00 je 408299 - 406fa7: 83 f8 03 cmp $0x3,%eax - 406faa: 0f 84 e0 12 00 00 je 408290 - 406fb0: 83 f8 01 cmp $0x1,%eax - 406fb3: 0f 84 0f 13 00 00 je 4082c8 - 406fb9: 4c 89 ef mov %r13,%rdi - 406fbc: e8 ef 6d 01 00 callq 41ddb0 <__cfree> - 406fc1: 4d 8b 6c 24 10 mov 0x10(%r12),%r13 - 406fc6: 4d 85 ed test %r13,%r13 - 406fc9: 0f 84 30 f9 ff ff je 4068ff - 406fcf: 41 8b 45 00 mov 0x0(%r13),%eax - 406fd3: 83 f8 02 cmp $0x2,%eax - 406fd6: 0f 84 bd f8 ff ff je 406899 - 406fdc: 83 f8 03 cmp $0x3,%eax - 406fdf: 0f 84 ab 20 00 00 je 409090 - 406fe5: 83 f8 01 cmp $0x1,%eax - 406fe8: 0f 84 da f8 ff ff je 4068c8 - 406fee: 4c 89 ef mov %r13,%rdi - 406ff1: e8 ba 6d 01 00 callq 41ddb0 <__cfree> - 406ff6: e9 04 f9 ff ff jmpq 4068ff - 406ffb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 407000: 4d 8b 6c 24 18 mov 0x18(%r12),%r13 - 407005: 4d 85 ed test %r13,%r13 - 407008: 0f 84 e3 f5 ff ff je 4065f1 - 40700e: 41 8b 45 00 mov 0x0(%r13),%eax - 407012: 83 f8 02 cmp $0x2,%eax - 407015: 0f 84 70 f5 ff ff je 40658b - 40701b: 83 f8 03 cmp $0x3,%eax - 40701e: 0f 84 34 20 00 00 je 409058 - 407024: 83 f8 01 cmp $0x1,%eax - 407027: 0f 84 8d f5 ff ff je 4065ba - 40702d: 4c 89 ef mov %r13,%rdi - 407030: e8 7b 6d 01 00 callq 41ddb0 <__cfree> - 407035: e9 b7 f5 ff ff jmpq 4065f1 - 40703a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 407040: 48 83 c4 18 add $0x18,%rsp - 407044: 31 c0 xor %eax,%eax - 407046: 5b pop %rbx - 407047: 5d pop %rbp - 407048: 41 5c pop %r12 - 40704a: 41 5d pop %r13 - 40704c: 41 5e pop %r14 - 40704e: 41 5f pop %r15 - 407050: c3 retq - 407051: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 407058: 48 8b 04 24 mov (%rsp),%rax - 40705c: 48 8b 40 18 mov 0x18(%rax),%rax - 407060: 48 85 c0 test %rax,%rax - 407063: 74 25 je 40708a - 407065: 8b 10 mov (%rax),%edx - 407067: 83 fa 02 cmp $0x2,%edx - 40706a: 0f 84 63 20 00 00 je 4090d3 - 407070: 83 fa 03 cmp $0x3,%edx - 407073: 0f 84 47 20 00 00 je 4090c0 - 407079: 83 fa 01 cmp $0x1,%edx - 40707c: 0f 84 64 20 00 00 je 4090e6 - 407082: 48 89 c7 mov %rax,%rdi - 407085: e8 26 6d 01 00 callq 41ddb0 <__cfree> - 40708a: 48 8b 04 24 mov (%rsp),%rax - 40708e: 48 8b 40 10 mov 0x10(%rax),%rax - 407092: 48 85 c0 test %rax,%rax - 407095: 74 25 je 4070bc - 407097: 8b 10 mov (%rax),%edx - 407099: 83 fa 02 cmp $0x2,%edx - 40709c: 0f 84 01 0f 00 00 je 407fa3 - 4070a2: 83 fa 03 cmp $0x3,%edx - 4070a5: 0f 84 e5 0e 00 00 je 407f90 - 4070ab: 83 fa 01 cmp $0x1,%edx - 4070ae: 0f 84 02 0f 00 00 je 407fb6 - 4070b4: 48 89 c7 mov %rax,%rdi - 4070b7: e8 f4 6c 01 00 callq 41ddb0 <__cfree> - 4070bc: 48 8b 04 24 mov (%rsp),%rax - 4070c0: 48 8b 40 08 mov 0x8(%rax),%rax - 4070c4: 48 85 c0 test %rax,%rax - 4070c7: 0f 84 3b fb ff ff je 406c08 - 4070cd: 8b 10 mov (%rax),%edx - 4070cf: 83 fa 02 cmp $0x2,%edx - 4070d2: 74 2f je 407103 - 4070d4: 83 fa 03 cmp $0x3,%edx - 4070d7: 74 17 je 4070f0 - 4070d9: 83 fa 01 cmp $0x1,%edx - 4070dc: 74 38 je 407116 - 4070de: 48 89 c7 mov %rax,%rdi - 4070e1: e8 ca 6c 01 00 callq 41ddb0 <__cfree> - 4070e6: e9 1d fb ff ff jmpq 406c08 - 4070eb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4070f0: 48 8b 78 18 mov 0x18(%rax),%rdi - 4070f4: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4070f9: e8 12 eb ff ff callq 405c10 <__gettext_free_exp> - 4070fe: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 407103: 48 8b 78 10 mov 0x10(%rax),%rdi - 407107: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40710c: e8 ff ea ff ff callq 405c10 <__gettext_free_exp> - 407111: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 407116: 48 8b 78 08 mov 0x8(%rax),%rdi - 40711a: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40711f: e8 ec ea ff ff callq 405c10 <__gettext_free_exp> - 407124: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 407129: 48 89 c7 mov %rax,%rdi - 40712c: e8 7f 6c 01 00 callq 41ddb0 <__cfree> - 407131: e9 d2 fa ff ff jmpq 406c08 - 407136: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 40713d: 00 00 00 - 407140: 48 8b 04 24 mov (%rsp),%rax - 407144: 48 8b 40 18 mov 0x18(%rax),%rax - 407148: 48 85 c0 test %rax,%rax - 40714b: 74 25 je 407172 - 40714d: 8b 10 mov (%rax),%edx - 40714f: 83 fa 02 cmp $0x2,%edx - 407152: 0f 84 cb 21 00 00 je 409323 - 407158: 83 fa 03 cmp $0x3,%edx - 40715b: 0f 84 af 21 00 00 je 409310 - 407161: 83 fa 01 cmp $0x1,%edx - 407164: 0f 84 cc 21 00 00 je 409336 - 40716a: 48 89 c7 mov %rax,%rdi - 40716d: e8 3e 6c 01 00 callq 41ddb0 <__cfree> - 407172: 48 8b 04 24 mov (%rsp),%rax - 407176: 48 8b 40 10 mov 0x10(%rax),%rax - 40717a: 48 85 c0 test %rax,%rax - 40717d: 74 25 je 4071a4 - 40717f: 8b 10 mov (%rax),%edx - 407181: 83 fa 02 cmp $0x2,%edx - 407184: 0f 84 59 0d 00 00 je 407ee3 - 40718a: 83 fa 03 cmp $0x3,%edx - 40718d: 0f 84 3d 0d 00 00 je 407ed0 - 407193: 83 fa 01 cmp $0x1,%edx - 407196: 0f 84 5a 0d 00 00 je 407ef6 - 40719c: 48 89 c7 mov %rax,%rdi - 40719f: e8 0c 6c 01 00 callq 41ddb0 <__cfree> - 4071a4: 48 8b 04 24 mov (%rsp),%rax - 4071a8: 48 8b 40 08 mov 0x8(%rax),%rax - 4071ac: 48 85 c0 test %rax,%rax - 4071af: 0f 84 48 f5 ff ff je 4066fd - 4071b5: 8b 10 mov (%rax),%edx - 4071b7: 83 fa 02 cmp $0x2,%edx - 4071ba: 74 2f je 4071eb - 4071bc: 83 fa 03 cmp $0x3,%edx - 4071bf: 74 17 je 4071d8 - 4071c1: 83 fa 01 cmp $0x1,%edx - 4071c4: 74 38 je 4071fe - 4071c6: 48 89 c7 mov %rax,%rdi - 4071c9: e8 e2 6b 01 00 callq 41ddb0 <__cfree> - 4071ce: e9 2a f5 ff ff jmpq 4066fd - 4071d3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4071d8: 48 8b 78 18 mov 0x18(%rax),%rdi - 4071dc: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4071e1: e8 2a ea ff ff callq 405c10 <__gettext_free_exp> - 4071e6: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4071eb: 48 8b 78 10 mov 0x10(%rax),%rdi - 4071ef: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4071f4: e8 17 ea ff ff callq 405c10 <__gettext_free_exp> - 4071f9: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4071fe: 48 8b 78 08 mov 0x8(%rax),%rdi - 407202: 48 89 44 24 08 mov %rax,0x8(%rsp) - 407207: e8 04 ea ff ff callq 405c10 <__gettext_free_exp> - 40720c: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 407211: 48 89 c7 mov %rax,%rdi - 407214: e8 97 6b 01 00 callq 41ddb0 <__cfree> - 407219: e9 df f4 ff ff jmpq 4066fd - 40721e: 66 90 xchg %ax,%ax - 407220: 48 8b 04 24 mov (%rsp),%rax - 407224: 48 8b 40 18 mov 0x18(%rax),%rax - 407228: 48 85 c0 test %rax,%rax - 40722b: 74 25 je 407252 - 40722d: 8b 10 mov (%rax),%edx - 40722f: 83 fa 02 cmp $0x2,%edx - 407232: 0f 84 ad 20 00 00 je 4092e5 - 407238: 83 fa 03 cmp $0x3,%edx - 40723b: 0f 84 91 20 00 00 je 4092d2 - 407241: 83 fa 01 cmp $0x1,%edx - 407244: 0f 84 ae 20 00 00 je 4092f8 - 40724a: 48 89 c7 mov %rax,%rdi - 40724d: e8 5e 6b 01 00 callq 41ddb0 <__cfree> - 407252: 48 8b 04 24 mov (%rsp),%rax - 407256: 48 8b 40 10 mov 0x10(%rax),%rax - 40725a: 48 85 c0 test %rax,%rax - 40725d: 74 25 je 407284 - 40725f: 8b 10 mov (%rax),%edx - 407261: 83 fa 02 cmp $0x2,%edx - 407264: 0f 84 f9 0c 00 00 je 407f63 - 40726a: 83 fa 03 cmp $0x3,%edx - 40726d: 0f 84 dd 0c 00 00 je 407f50 - 407273: 83 fa 01 cmp $0x1,%edx - 407276: 0f 84 fa 0c 00 00 je 407f76 - 40727c: 48 89 c7 mov %rax,%rdi - 40727f: e8 2c 6b 01 00 callq 41ddb0 <__cfree> - 407284: 48 8b 04 24 mov (%rsp),%rax - 407288: 48 8b 40 08 mov 0x8(%rax),%rax - 40728c: 48 85 c0 test %rax,%rax - 40728f: 0f 84 bd f8 ff ff je 406b52 - 407295: 8b 10 mov (%rax),%edx - 407297: 83 fa 02 cmp $0x2,%edx - 40729a: 74 2f je 4072cb - 40729c: 83 fa 03 cmp $0x3,%edx - 40729f: 74 17 je 4072b8 - 4072a1: 83 fa 01 cmp $0x1,%edx - 4072a4: 74 38 je 4072de - 4072a6: 48 89 c7 mov %rax,%rdi - 4072a9: e8 02 6b 01 00 callq 41ddb0 <__cfree> - 4072ae: e9 9f f8 ff ff jmpq 406b52 - 4072b3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4072b8: 48 8b 78 18 mov 0x18(%rax),%rdi - 4072bc: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4072c1: e8 4a e9 ff ff callq 405c10 <__gettext_free_exp> - 4072c6: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4072cb: 48 8b 78 10 mov 0x10(%rax),%rdi - 4072cf: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4072d4: e8 37 e9 ff ff callq 405c10 <__gettext_free_exp> - 4072d9: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4072de: 48 8b 78 08 mov 0x8(%rax),%rdi - 4072e2: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4072e7: e8 24 e9 ff ff callq 405c10 <__gettext_free_exp> - 4072ec: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4072f1: 48 89 c7 mov %rax,%rdi - 4072f4: e8 b7 6a 01 00 callq 41ddb0 <__cfree> - 4072f9: e9 54 f8 ff ff jmpq 406b52 - 4072fe: 66 90 xchg %ax,%ax - 407300: 48 8b 04 24 mov (%rsp),%rax - 407304: 48 8b 40 18 mov 0x18(%rax),%rax - 407308: 48 85 c0 test %rax,%rax - 40730b: 74 25 je 407332 - 40730d: 8b 10 mov (%rax),%edx - 40730f: 83 fa 02 cmp $0x2,%edx - 407312: 0f 84 c9 22 00 00 je 4095e1 - 407318: 83 fa 03 cmp $0x3,%edx - 40731b: 0f 84 ad 22 00 00 je 4095ce - 407321: 83 fa 01 cmp $0x1,%edx - 407324: 0f 84 ca 22 00 00 je 4095f4 - 40732a: 48 89 c7 mov %rax,%rdi - 40732d: e8 7e 6a 01 00 callq 41ddb0 <__cfree> - 407332: 48 8b 04 24 mov (%rsp),%rax - 407336: 48 8b 40 10 mov 0x10(%rax),%rax - 40733a: 48 85 c0 test %rax,%rax - 40733d: 74 25 je 407364 - 40733f: 8b 10 mov (%rax),%edx - 407341: 83 fa 02 cmp $0x2,%edx - 407344: 0f 84 99 0c 00 00 je 407fe3 - 40734a: 83 fa 03 cmp $0x3,%edx - 40734d: 0f 84 7d 0c 00 00 je 407fd0 - 407353: 83 fa 01 cmp $0x1,%edx - 407356: 0f 84 9a 0c 00 00 je 407ff6 - 40735c: 48 89 c7 mov %rax,%rdi - 40735f: e8 4c 6a 01 00 callq 41ddb0 <__cfree> - 407364: 48 8b 04 24 mov (%rsp),%rax - 407368: 48 8b 40 08 mov 0x8(%rax),%rax - 40736c: 48 85 c0 test %rax,%rax - 40736f: 0f 84 f3 f6 ff ff je 406a68 - 407375: 8b 10 mov (%rax),%edx - 407377: 83 fa 02 cmp $0x2,%edx - 40737a: 74 2f je 4073ab - 40737c: 83 fa 03 cmp $0x3,%edx - 40737f: 74 17 je 407398 - 407381: 83 fa 01 cmp $0x1,%edx - 407384: 74 38 je 4073be - 407386: 48 89 c7 mov %rax,%rdi - 407389: e8 22 6a 01 00 callq 41ddb0 <__cfree> - 40738e: e9 d5 f6 ff ff jmpq 406a68 - 407393: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 407398: 48 8b 78 18 mov 0x18(%rax),%rdi - 40739c: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4073a1: e8 6a e8 ff ff callq 405c10 <__gettext_free_exp> - 4073a6: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4073ab: 48 8b 78 10 mov 0x10(%rax),%rdi - 4073af: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4073b4: e8 57 e8 ff ff callq 405c10 <__gettext_free_exp> - 4073b9: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4073be: 48 8b 78 08 mov 0x8(%rax),%rdi - 4073c2: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4073c7: e8 44 e8 ff ff callq 405c10 <__gettext_free_exp> - 4073cc: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4073d1: 48 89 c7 mov %rax,%rdi - 4073d4: e8 d7 69 01 00 callq 41ddb0 <__cfree> - 4073d9: e9 8a f6 ff ff jmpq 406a68 - 4073de: 66 90 xchg %ax,%ax - 4073e0: 48 8b 50 18 mov 0x18(%rax),%rdx - 4073e4: 48 85 d2 test %rdx,%rdx - 4073e7: 74 2d je 407416 - 4073e9: 8b 0a mov (%rdx),%ecx - 4073eb: 83 f9 02 cmp $0x2,%ecx - 4073ee: 0f 84 27 0f 00 00 je 40831b - 4073f4: 83 f9 03 cmp $0x3,%ecx - 4073f7: 0f 84 03 0f 00 00 je 408300 - 4073fd: 83 f9 01 cmp $0x1,%ecx - 407400: 0f 84 30 0f 00 00 je 408336 - 407406: 48 89 d7 mov %rdx,%rdi - 407409: 48 89 04 24 mov %rax,(%rsp) - 40740d: e8 9e 69 01 00 callq 41ddb0 <__cfree> - 407412: 48 8b 04 24 mov (%rsp),%rax - 407416: 48 8b 50 10 mov 0x10(%rax),%rdx - 40741a: 48 85 d2 test %rdx,%rdx - 40741d: 0f 84 7e f5 ff ff je 4069a1 - 407423: 8b 0a mov (%rdx),%ecx - 407425: 83 f9 02 cmp $0x2,%ecx - 407428: 0f 84 2d f5 ff ff je 40695b - 40742e: 83 f9 03 cmp $0x3,%ecx - 407431: 0f 84 09 f5 ff ff je 406940 - 407437: 83 f9 01 cmp $0x1,%ecx - 40743a: 0f 84 36 f5 ff ff je 406976 - 407440: 48 89 d7 mov %rdx,%rdi - 407443: 48 89 04 24 mov %rax,(%rsp) - 407447: e8 64 69 01 00 callq 41ddb0 <__cfree> - 40744c: 48 8b 04 24 mov (%rsp),%rax - 407450: e9 4c f5 ff ff jmpq 4069a1 - 407455: 0f 1f 00 nopl (%rax) - 407458: 49 8b 47 18 mov 0x18(%r15),%rax - 40745c: 48 85 c0 test %rax,%rax - 40745f: 74 25 je 407486 - 407461: 8b 10 mov (%rax),%edx - 407463: 83 fa 02 cmp $0x2,%edx - 407466: 0f 84 58 23 00 00 je 4097c4 - 40746c: 83 fa 03 cmp $0x3,%edx - 40746f: 0f 84 3e 23 00 00 je 4097b3 - 407475: 83 fa 01 cmp $0x1,%edx - 407478: 0f 84 57 23 00 00 je 4097d5 - 40747e: 48 89 c7 mov %rax,%rdi - 407481: e8 2a 69 01 00 callq 41ddb0 <__cfree> - 407486: 49 8b 47 10 mov 0x10(%r15),%rax - 40748a: 48 85 c0 test %rax,%rax - 40748d: 48 89 04 24 mov %rax,(%rsp) - 407491: 74 26 je 4074b9 - 407493: 8b 00 mov (%rax),%eax - 407495: 83 f8 02 cmp $0x2,%eax - 407498: 0f 84 7f 0c 00 00 je 40811d - 40749e: 83 f8 03 cmp $0x3,%eax - 4074a1: 0f 84 69 0c 00 00 je 408110 - 4074a7: 83 f8 01 cmp $0x1,%eax - 4074aa: 0f 84 9f 0c 00 00 je 40814f - 4074b0: 48 8b 3c 24 mov (%rsp),%rdi - 4074b4: e8 f7 68 01 00 callq 41ddb0 <__cfree> - 4074b9: 49 8b 47 08 mov 0x8(%r15),%rax - 4074bd: 48 85 c0 test %rax,%rax - 4074c0: 48 89 04 24 mov %rax,(%rsp) - 4074c4: 0f 84 6c f3 ff ff je 406836 - 4074ca: 8b 00 mov (%rax),%eax - 4074cc: 83 f8 02 cmp $0x2,%eax - 4074cf: 74 2c je 4074fd - 4074d1: 83 f8 03 cmp $0x3,%eax - 4074d4: 74 1a je 4074f0 - 4074d6: 83 f8 01 cmp $0x1,%eax - 4074d9: 74 54 je 40752f - 4074db: 48 8b 3c 24 mov (%rsp),%rdi - 4074df: e8 cc 68 01 00 callq 41ddb0 <__cfree> - 4074e4: e9 4d f3 ff ff jmpq 406836 - 4074e9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4074f0: 48 8b 04 24 mov (%rsp),%rax - 4074f4: 48 8b 78 18 mov 0x18(%rax),%rdi - 4074f8: e8 13 e7 ff ff callq 405c10 <__gettext_free_exp> - 4074fd: 48 8b 04 24 mov (%rsp),%rax - 407501: 48 8b 40 10 mov 0x10(%rax),%rax - 407505: 48 85 c0 test %rax,%rax - 407508: 74 25 je 40752f - 40750a: 8b 10 mov (%rax),%edx - 40750c: 83 fa 02 cmp $0x2,%edx - 40750f: 0f 84 48 12 00 00 je 40875d - 407515: 83 fa 03 cmp $0x3,%edx - 407518: 0f 84 2c 12 00 00 je 40874a - 40751e: 83 fa 01 cmp $0x1,%edx - 407521: 0f 84 49 12 00 00 je 408770 - 407527: 48 89 c7 mov %rax,%rdi - 40752a: e8 81 68 01 00 callq 41ddb0 <__cfree> - 40752f: 48 8b 04 24 mov (%rsp),%rax - 407533: 48 8b 40 08 mov 0x8(%rax),%rax - 407537: 48 85 c0 test %rax,%rax - 40753a: 74 9f je 4074db - 40753c: 8b 10 mov (%rax),%edx - 40753e: 83 fa 02 cmp $0x2,%edx - 407541: 0f 84 1c 09 00 00 je 407e63 - 407547: 83 fa 03 cmp $0x3,%edx - 40754a: 0f 84 00 09 00 00 je 407e50 - 407550: 83 fa 01 cmp $0x1,%edx - 407553: 0f 84 1d 09 00 00 je 407e76 - 407559: 48 89 c7 mov %rax,%rdi - 40755c: e8 4f 68 01 00 callq 41ddb0 <__cfree> - 407561: 48 8b 3c 24 mov (%rsp),%rdi - 407565: e8 46 68 01 00 callq 41ddb0 <__cfree> - 40756a: e9 c7 f2 ff ff jmpq 406836 - 40756f: 90 nop - 407570: 49 8b 47 18 mov 0x18(%r15),%rax - 407574: 48 85 c0 test %rax,%rax - 407577: 74 25 je 40759e - 407579: 8b 10 mov (%rax),%edx - 40757b: 83 fa 02 cmp $0x2,%edx - 40757e: 0f 84 e3 0d 00 00 je 408367 - 407584: 83 fa 03 cmp $0x3,%edx - 407587: 0f 84 c9 0d 00 00 je 408356 - 40758d: 83 fa 01 cmp $0x1,%edx - 407590: 0f 84 e2 0d 00 00 je 408378 - 407596: 48 89 c7 mov %rax,%rdi - 407599: e8 12 68 01 00 callq 41ddb0 <__cfree> - 40759e: 49 8b 47 10 mov 0x10(%r15),%rax - 4075a2: 48 85 c0 test %rax,%rax - 4075a5: 48 89 04 24 mov %rax,(%rsp) - 4075a9: 0f 84 75 f5 ff ff je 406b24 - 4075af: 8b 00 mov (%rax),%eax - 4075b1: 83 f8 02 cmp $0x2,%eax - 4075b4: 0f 84 fd f4 ff ff je 406ab7 - 4075ba: 83 f8 03 cmp $0x3,%eax - 4075bd: 0f 84 dd 20 00 00 je 4096a0 - 4075c3: 83 f8 01 cmp $0x1,%eax - 4075c6: 0f 84 1d f5 ff ff je 406ae9 - 4075cc: 48 8b 3c 24 mov (%rsp),%rdi - 4075d0: e8 db 67 01 00 callq 41ddb0 <__cfree> - 4075d5: e9 4a f5 ff ff jmpq 406b24 - 4075da: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4075e0: 49 8b 47 18 mov 0x18(%r15),%rax - 4075e4: 48 85 c0 test %rax,%rax - 4075e7: 74 25 je 40760e - 4075e9: 8b 10 mov (%rax),%edx - 4075eb: 83 fa 02 cmp $0x2,%edx - 4075ee: 0f 84 f7 0e 00 00 je 4084eb - 4075f4: 83 fa 03 cmp $0x3,%edx - 4075f7: 0f 84 dd 0e 00 00 je 4084da - 4075fd: 83 fa 01 cmp $0x1,%edx - 407600: 0f 84 f6 0e 00 00 je 4084fc - 407606: 48 89 c7 mov %rax,%rdi - 407609: e8 a2 67 01 00 callq 41ddb0 <__cfree> - 40760e: 49 8b 47 10 mov 0x10(%r15),%rax - 407612: 48 85 c0 test %rax,%rax - 407615: 48 89 04 24 mov %rax,(%rsp) - 407619: 0f 84 1b f4 ff ff je 406a3a - 40761f: 8b 00 mov (%rax),%eax - 407621: 83 f8 02 cmp $0x2,%eax - 407624: 0f 84 a3 f3 ff ff je 4069cd - 40762a: 83 f8 03 cmp $0x3,%eax - 40762d: 0f 84 8d f3 ff ff je 4069c0 - 407633: 83 f8 01 cmp $0x1,%eax - 407636: 0f 84 c3 f3 ff ff je 4069ff - 40763c: 48 8b 3c 24 mov (%rsp),%rdi - 407640: e8 6b 67 01 00 callq 41ddb0 <__cfree> - 407645: e9 f0 f3 ff ff jmpq 406a3a - 40764a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 407650: 49 8b 47 18 mov 0x18(%r15),%rax - 407654: 48 85 c0 test %rax,%rax - 407657: 74 25 je 40767e - 407659: 8b 10 mov (%rax),%edx - 40765b: 83 fa 02 cmp $0x2,%edx - 40765e: 0f 84 08 22 00 00 je 40986c - 407664: 83 fa 03 cmp $0x3,%edx - 407667: 0f 84 ee 21 00 00 je 40985b - 40766d: 83 fa 01 cmp $0x1,%edx - 407670: 0f 84 07 22 00 00 je 40987d - 407676: 48 89 c7 mov %rax,%rdi - 407679: e8 32 67 01 00 callq 41ddb0 <__cfree> - 40767e: 49 8b 47 10 mov 0x10(%r15),%rax - 407682: 48 85 c0 test %rax,%rax - 407685: 48 89 04 24 mov %rax,(%rsp) - 407689: 74 26 je 4076b1 - 40768b: 8b 00 mov (%rax),%eax - 40768d: 83 f8 02 cmp $0x2,%eax - 407690: 0f 84 87 0b 00 00 je 40821d - 407696: 83 f8 03 cmp $0x3,%eax - 407699: 0f 84 71 0b 00 00 je 408210 - 40769f: 83 f8 01 cmp $0x1,%eax - 4076a2: 0f 84 a7 0b 00 00 je 40824f - 4076a8: 48 8b 3c 24 mov (%rsp),%rdi - 4076ac: e8 ff 66 01 00 callq 41ddb0 <__cfree> - 4076b1: 49 8b 47 08 mov 0x8(%r15),%rax - 4076b5: 48 85 c0 test %rax,%rax - 4076b8: 48 89 04 24 mov %rax,(%rsp) - 4076bc: 0f 84 d4 f0 ff ff je 406796 - 4076c2: 8b 00 mov (%rax),%eax - 4076c4: 83 f8 02 cmp $0x2,%eax - 4076c7: 74 2c je 4076f5 - 4076c9: 83 f8 03 cmp $0x3,%eax - 4076cc: 74 1a je 4076e8 - 4076ce: 83 f8 01 cmp $0x1,%eax - 4076d1: 74 54 je 407727 - 4076d3: 48 8b 3c 24 mov (%rsp),%rdi - 4076d7: e8 d4 66 01 00 callq 41ddb0 <__cfree> - 4076dc: e9 b5 f0 ff ff jmpq 406796 - 4076e1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4076e8: 48 8b 04 24 mov (%rsp),%rax - 4076ec: 48 8b 78 18 mov 0x18(%rax),%rdi - 4076f0: e8 1b e5 ff ff callq 405c10 <__gettext_free_exp> - 4076f5: 48 8b 04 24 mov (%rsp),%rax - 4076f9: 48 8b 40 10 mov 0x10(%rax),%rax - 4076fd: 48 85 c0 test %rax,%rax - 407700: 74 25 je 407727 - 407702: 8b 10 mov (%rax),%edx - 407704: 83 fa 02 cmp $0x2,%edx - 407707: 0f 84 cc 10 00 00 je 4087d9 - 40770d: 83 fa 03 cmp $0x3,%edx - 407710: 0f 84 b0 10 00 00 je 4087c6 - 407716: 83 fa 01 cmp $0x1,%edx - 407719: 0f 84 cd 10 00 00 je 4087ec - 40771f: 48 89 c7 mov %rax,%rdi - 407722: e8 89 66 01 00 callq 41ddb0 <__cfree> - 407727: 48 8b 04 24 mov (%rsp),%rax - 40772b: 48 8b 40 08 mov 0x8(%rax),%rax - 40772f: 48 85 c0 test %rax,%rax - 407732: 74 9f je 4076d3 - 407734: 8b 10 mov (%rax),%edx - 407736: 83 fa 02 cmp $0x2,%edx - 407739: 0f 84 24 09 00 00 je 408063 - 40773f: 83 fa 03 cmp $0x3,%edx - 407742: 0f 84 08 09 00 00 je 408050 - 407748: 83 fa 01 cmp $0x1,%edx - 40774b: 0f 84 25 09 00 00 je 408076 - 407751: 48 89 c7 mov %rax,%rdi - 407754: e8 57 66 01 00 callq 41ddb0 <__cfree> - 407759: 48 8b 3c 24 mov (%rsp),%rdi - 40775d: e8 4e 66 01 00 callq 41ddb0 <__cfree> - 407762: e9 2f f0 ff ff jmpq 406796 - 407767: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 40776e: 00 00 - 407770: 49 8b 47 18 mov 0x18(%r15),%rax - 407774: 48 85 c0 test %rax,%rax - 407777: 74 25 je 40779e - 407779: 8b 10 mov (%rax),%edx - 40777b: 83 fa 02 cmp $0x2,%edx - 40777e: 0f 84 a8 22 00 00 je 409a2c - 407784: 83 fa 03 cmp $0x3,%edx - 407787: 0f 84 8e 22 00 00 je 409a1b - 40778d: 83 fa 01 cmp $0x1,%edx - 407790: 0f 84 a7 22 00 00 je 409a3d - 407796: 48 89 c7 mov %rax,%rdi - 407799: e8 12 66 01 00 callq 41ddb0 <__cfree> - 40779e: 49 8b 47 10 mov 0x10(%r15),%rax - 4077a2: 48 85 c0 test %rax,%rax - 4077a5: 48 89 04 24 mov %rax,(%rsp) - 4077a9: 74 26 je 4077d1 - 4077ab: 8b 00 mov (%rax),%eax - 4077ad: 83 f8 02 cmp $0x2,%eax - 4077b0: 0f 84 e7 09 00 00 je 40819d - 4077b6: 83 f8 03 cmp $0x3,%eax - 4077b9: 0f 84 d1 09 00 00 je 408190 - 4077bf: 83 f8 01 cmp $0x1,%eax - 4077c2: 0f 84 07 0a 00 00 je 4081cf - 4077c8: 48 8b 3c 24 mov (%rsp),%rdi - 4077cc: e8 df 65 01 00 callq 41ddb0 <__cfree> - 4077d1: 49 8b 47 08 mov 0x8(%r15),%rax - 4077d5: 48 85 c0 test %rax,%rax - 4077d8: 48 89 04 24 mov %rax,(%rsp) - 4077dc: 0f 84 db f4 ff ff je 406cbd - 4077e2: 8b 00 mov (%rax),%eax - 4077e4: 83 f8 02 cmp $0x2,%eax - 4077e7: 74 2c je 407815 - 4077e9: 83 f8 03 cmp $0x3,%eax - 4077ec: 74 1a je 407808 - 4077ee: 83 f8 01 cmp $0x1,%eax - 4077f1: 74 54 je 407847 - 4077f3: 48 8b 3c 24 mov (%rsp),%rdi - 4077f7: e8 b4 65 01 00 callq 41ddb0 <__cfree> - 4077fc: e9 bc f4 ff ff jmpq 406cbd - 407801: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 407808: 48 8b 04 24 mov (%rsp),%rax - 40780c: 48 8b 78 18 mov 0x18(%rax),%rdi - 407810: e8 fb e3 ff ff callq 405c10 <__gettext_free_exp> - 407815: 48 8b 04 24 mov (%rsp),%rax - 407819: 48 8b 40 10 mov 0x10(%rax),%rax - 40781d: 48 85 c0 test %rax,%rax - 407820: 74 25 je 407847 - 407822: 8b 10 mov (%rax),%edx - 407824: 83 fa 02 cmp $0x2,%edx - 407827: 0f 84 f2 0e 00 00 je 40871f - 40782d: 83 fa 03 cmp $0x3,%edx - 407830: 0f 84 d6 0e 00 00 je 40870c - 407836: 83 fa 01 cmp $0x1,%edx - 407839: 0f 84 f3 0e 00 00 je 408732 - 40783f: 48 89 c7 mov %rax,%rdi - 407842: e8 69 65 01 00 callq 41ddb0 <__cfree> - 407847: 48 8b 04 24 mov (%rsp),%rax - 40784b: 48 8b 40 08 mov 0x8(%rax),%rax - 40784f: 48 85 c0 test %rax,%rax - 407852: 74 9f je 4077f3 - 407854: 8b 10 mov (%rax),%edx - 407856: 83 fa 02 cmp $0x2,%edx - 407859: 0f 84 c4 07 00 00 je 408023 - 40785f: 83 fa 03 cmp $0x3,%edx - 407862: 0f 84 a8 07 00 00 je 408010 - 407868: 83 fa 01 cmp $0x1,%edx - 40786b: 0f 84 c5 07 00 00 je 408036 - 407871: 48 89 c7 mov %rax,%rdi - 407874: e8 37 65 01 00 callq 41ddb0 <__cfree> - 407879: 48 8b 3c 24 mov (%rsp),%rdi - 40787d: e8 2e 65 01 00 callq 41ddb0 <__cfree> - 407882: e9 36 f4 ff ff jmpq 406cbd - 407887: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 40788e: 00 00 - 407890: 49 8b 47 18 mov 0x18(%r15),%rax - 407894: 48 85 c0 test %rax,%rax - 407897: 74 25 je 4078be - 407899: 8b 10 mov (%rax),%edx - 40789b: 83 fa 02 cmp $0x2,%edx - 40789e: 0f 84 85 0b 00 00 je 408429 - 4078a4: 83 fa 03 cmp $0x3,%edx - 4078a7: 0f 84 6b 0b 00 00 je 408418 - 4078ad: 83 fa 01 cmp $0x1,%edx - 4078b0: 0f 84 84 0b 00 00 je 40843a - 4078b6: 48 89 c7 mov %rax,%rdi - 4078b9: e8 f2 64 01 00 callq 41ddb0 <__cfree> - 4078be: 49 8b 47 10 mov 0x10(%r15),%rax - 4078c2: 48 85 c0 test %rax,%rax - 4078c5: 48 89 04 24 mov %rax,(%rsp) - 4078c9: 0f 84 0b f3 ff ff je 406bda - 4078cf: 8b 00 mov (%rax),%eax - 4078d1: 83 f8 02 cmp $0x2,%eax - 4078d4: 0f 84 93 f2 ff ff je 406b6d - 4078da: 83 f8 03 cmp $0x3,%eax - 4078dd: 0f 84 7d f2 ff ff je 406b60 - 4078e3: 83 f8 01 cmp $0x1,%eax - 4078e6: 0f 84 b3 f2 ff ff je 406b9f - 4078ec: 48 8b 3c 24 mov (%rsp),%rdi - 4078f0: e8 bb 64 01 00 callq 41ddb0 <__cfree> - 4078f5: e9 e0 f2 ff ff jmpq 406bda - 4078fa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 407900: 4d 8b 7d 18 mov 0x18(%r13),%r15 - 407904: 4d 85 ff test %r15,%r15 - 407907: 74 26 je 40792f - 407909: 41 8b 07 mov (%r15),%eax - 40790c: 83 f8 02 cmp $0x2,%eax - 40790f: 0f 84 3b 0d 00 00 je 408650 - 407915: 83 f8 03 cmp $0x3,%eax - 407918: 0f 84 29 0d 00 00 je 408647 - 40791e: 83 f8 01 cmp $0x1,%eax - 407921: 0f 84 32 0d 00 00 je 408659 - 407927: 4c 89 ff mov %r15,%rdi - 40792a: e8 81 64 01 00 callq 41ddb0 <__cfree> - 40792f: 4d 8b 7d 10 mov 0x10(%r13),%r15 - 407933: 4d 85 ff test %r15,%r15 - 407936: 0f 84 56 f3 ff ff je 406c92 - 40793c: 41 8b 07 mov (%r15),%eax - 40793f: 83 f8 02 cmp $0x2,%eax - 407942: 0f 84 e1 f2 ff ff je 406c29 - 407948: 83 f8 03 cmp $0x3,%eax - 40794b: 0f 84 cf f2 ff ff je 406c20 - 407951: 83 f8 01 cmp $0x1,%eax - 407954: 0f 84 fd f2 ff ff je 406c57 - 40795a: 4c 89 ff mov %r15,%rdi - 40795d: e8 4e 64 01 00 callq 41ddb0 <__cfree> - 407962: e9 2b f3 ff ff jmpq 406c92 - 407967: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 40796e: 00 00 - 407970: 48 8b 04 24 mov (%rsp),%rax - 407974: 48 8b 78 18 mov 0x18(%rax),%rdi - 407978: e8 93 e2 ff ff callq 405c10 <__gettext_free_exp> - 40797d: 48 8b 04 24 mov (%rsp),%rax - 407981: 48 8b 40 10 mov 0x10(%rax),%rax - 407985: 48 85 c0 test %rax,%rax - 407988: 74 25 je 4079af - 40798a: 8b 10 mov (%rax),%edx - 40798c: 83 fa 02 cmp $0x2,%edx - 40798f: 0f 84 0c 1b 00 00 je 4094a1 - 407995: 83 fa 03 cmp $0x3,%edx - 407998: 0f 84 f0 1a 00 00 je 40948e - 40799e: 83 fa 01 cmp $0x1,%edx - 4079a1: 0f 84 0d 1b 00 00 je 4094b4 - 4079a7: 48 89 c7 mov %rax,%rdi - 4079aa: e8 01 64 01 00 callq 41ddb0 <__cfree> - 4079af: 48 8b 04 24 mov (%rsp),%rax - 4079b3: 48 8b 40 08 mov 0x8(%rax),%rax - 4079b7: 48 85 c0 test %rax,%rax - 4079ba: 0f 84 30 eb ff ff je 4064f0 - 4079c0: 8b 10 mov (%rax),%edx - 4079c2: 83 fa 02 cmp $0x2,%edx - 4079c5: 0f 84 69 10 00 00 je 408a34 - 4079cb: 83 fa 03 cmp $0x3,%edx - 4079ce: 0f 84 4d 10 00 00 je 408a21 - 4079d4: 83 fa 01 cmp $0x1,%edx - 4079d7: 0f 84 6a 10 00 00 je 408a47 - 4079dd: 48 89 c7 mov %rax,%rdi - 4079e0: e8 cb 63 01 00 callq 41ddb0 <__cfree> - 4079e5: e9 06 eb ff ff jmpq 4064f0 - 4079ea: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4079f0: 48 8b 04 24 mov (%rsp),%rax - 4079f4: 48 8b 78 18 mov 0x18(%rax),%rdi - 4079f8: e8 13 e2 ff ff callq 405c10 <__gettext_free_exp> - 4079fd: 48 8b 04 24 mov (%rsp),%rax - 407a01: 48 8b 40 10 mov 0x10(%rax),%rax - 407a05: 48 85 c0 test %rax,%rax - 407a08: 74 25 je 407a2f - 407a0a: 8b 10 mov (%rax),%edx - 407a0c: 83 fa 02 cmp $0x2,%edx - 407a0f: 0f 84 0a 1c 00 00 je 40961f - 407a15: 83 fa 03 cmp $0x3,%edx - 407a18: 0f 84 ee 1b 00 00 je 40960c - 407a1e: 83 fa 01 cmp $0x1,%edx - 407a21: 0f 84 0b 1c 00 00 je 409632 - 407a27: 48 89 c7 mov %rax,%rdi - 407a2a: e8 81 63 01 00 callq 41ddb0 <__cfree> - 407a2f: 48 8b 04 24 mov (%rsp),%rax - 407a33: 48 8b 40 08 mov 0x8(%rax),%rax - 407a37: 48 85 c0 test %rax,%rax - 407a3a: 0f 84 8a ec ff ff je 4066ca - 407a40: 8b 10 mov (%rax),%edx - 407a42: 83 fa 02 cmp $0x2,%edx - 407a45: 0f 84 a3 10 00 00 je 408aee - 407a4b: 83 fa 03 cmp $0x3,%edx - 407a4e: 0f 84 87 10 00 00 je 408adb - 407a54: 83 fa 01 cmp $0x1,%edx - 407a57: 0f 84 a4 10 00 00 je 408b01 - 407a5d: 48 89 c7 mov %rax,%rdi - 407a60: e8 4b 63 01 00 callq 41ddb0 <__cfree> - 407a65: e9 60 ec ff ff jmpq 4066ca - 407a6a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 407a70: 48 8b 04 24 mov (%rsp),%rax - 407a74: 48 8b 78 18 mov 0x18(%rax),%rdi - 407a78: e8 93 e1 ff ff callq 405c10 <__gettext_free_exp> - 407a7d: 48 8b 04 24 mov (%rsp),%rax - 407a81: 48 8b 40 10 mov 0x10(%rax),%rax - 407a85: 48 85 c0 test %rax,%rax - 407a88: 74 25 je 407aaf - 407a8a: 8b 10 mov (%rax),%edx - 407a8c: 83 fa 02 cmp $0x2,%edx - 407a8f: 0f 84 66 17 00 00 je 4091fb - 407a95: 83 fa 03 cmp $0x3,%edx - 407a98: 0f 84 4a 17 00 00 je 4091e8 - 407a9e: 83 fa 01 cmp $0x1,%edx - 407aa1: 0f 84 67 17 00 00 je 40920e - 407aa7: 48 89 c7 mov %rax,%rdi - 407aaa: e8 01 63 01 00 callq 41ddb0 <__cfree> - 407aaf: 48 8b 04 24 mov (%rsp),%rax - 407ab3: 48 8b 40 08 mov 0x8(%rax),%rax - 407ab7: 48 85 c0 test %rax,%rax - 407aba: 0f 84 35 f3 ff ff je 406df5 - 407ac0: 8b 10 mov (%rax),%edx - 407ac2: 83 fa 02 cmp $0x2,%edx - 407ac5: 0f 84 e5 0f 00 00 je 408ab0 - 407acb: 83 fa 03 cmp $0x3,%edx - 407ace: 0f 84 c9 0f 00 00 je 408a9d - 407ad4: 83 fa 01 cmp $0x1,%edx - 407ad7: 0f 84 e6 0f 00 00 je 408ac3 - 407add: 48 89 c7 mov %rax,%rdi - 407ae0: e8 cb 62 01 00 callq 41ddb0 <__cfree> - 407ae5: e9 0b f3 ff ff jmpq 406df5 - 407aea: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 407af0: 48 8b 04 24 mov (%rsp),%rax - 407af4: 48 8b 78 18 mov 0x18(%rax),%rdi - 407af8: e8 13 e1 ff ff callq 405c10 <__gettext_free_exp> - 407afd: 48 8b 04 24 mov (%rsp),%rax - 407b01: 48 8b 40 10 mov 0x10(%rax),%rax - 407b05: 48 85 c0 test %rax,%rax - 407b08: 74 25 je 407b2f - 407b0a: 8b 10 mov (%rax),%edx - 407b0c: 83 fa 02 cmp $0x2,%edx - 407b0f: 0f 84 a8 16 00 00 je 4091bd - 407b15: 83 fa 03 cmp $0x3,%edx - 407b18: 0f 84 8c 16 00 00 je 4091aa - 407b1e: 83 fa 01 cmp $0x1,%edx - 407b21: 0f 84 a9 16 00 00 je 4091d0 - 407b27: 48 89 c7 mov %rax,%rdi - 407b2a: e8 81 62 01 00 callq 41ddb0 <__cfree> - 407b2f: 48 8b 04 24 mov (%rsp),%rax - 407b33: 48 8b 40 08 mov 0x8(%rax),%rax - 407b37: 48 85 c0 test %rax,%rax - 407b3a: 0f 84 f5 f3 ff ff je 406f35 - 407b40: 8b 10 mov (%rax),%edx - 407b42: 83 fa 02 cmp $0x2,%edx - 407b45: 0f 84 27 0f 00 00 je 408a72 - 407b4b: 83 fa 03 cmp $0x3,%edx - 407b4e: 0f 84 0b 0f 00 00 je 408a5f - 407b54: 83 fa 01 cmp $0x1,%edx - 407b57: 0f 84 28 0f 00 00 je 408a85 - 407b5d: 48 89 c7 mov %rax,%rdi - 407b60: e8 4b 62 01 00 callq 41ddb0 <__cfree> - 407b65: e9 cb f3 ff ff jmpq 406f35 - 407b6a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 407b70: 49 8b 7f 18 mov 0x18(%r15),%rdi - 407b74: e8 97 e0 ff ff callq 405c10 <__gettext_free_exp> - 407b79: 49 8b 47 10 mov 0x10(%r15),%rax - 407b7d: 48 85 c0 test %rax,%rax - 407b80: 74 25 je 407ba7 - 407b82: 8b 10 mov (%rax),%edx - 407b84: 83 fa 02 cmp $0x2,%edx - 407b87: 0f 84 bf 1d 00 00 je 40994c - 407b8d: 83 fa 03 cmp $0x3,%edx - 407b90: 0f 84 a5 1d 00 00 je 40993b - 407b96: 83 fa 01 cmp $0x1,%edx - 407b99: 0f 84 be 1d 00 00 je 40995d - 407b9f: 48 89 c7 mov %rax,%rdi - 407ba2: e8 09 62 01 00 callq 41ddb0 <__cfree> - 407ba7: 49 8b 47 08 mov 0x8(%r15),%rax - 407bab: 48 85 c0 test %rax,%rax - 407bae: 0f 84 2d ea ff ff je 4065e1 - 407bb4: 8b 10 mov (%rax),%edx - 407bb6: 83 fa 02 cmp $0x2,%edx - 407bb9: 0f 84 50 11 00 00 je 408d0f - 407bbf: 83 fa 03 cmp $0x3,%edx - 407bc2: 0f 84 36 11 00 00 je 408cfe - 407bc8: 83 fa 01 cmp $0x1,%edx - 407bcb: 0f 84 4f 11 00 00 je 408d20 - 407bd1: 48 89 c7 mov %rax,%rdi - 407bd4: e8 d7 61 01 00 callq 41ddb0 <__cfree> - 407bd9: e9 03 ea ff ff jmpq 4065e1 - 407bde: 66 90 xchg %ax,%ax - 407be0: 49 8b 7f 18 mov 0x18(%r15),%rdi - 407be4: e8 27 e0 ff ff callq 405c10 <__gettext_free_exp> - 407be9: 49 8b 47 10 mov 0x10(%r15),%rax - 407bed: 48 85 c0 test %rax,%rax - 407bf0: 74 25 je 407c17 - 407bf2: 8b 10 mov (%rax),%edx - 407bf4: 83 fa 02 cmp $0x2,%edx - 407bf7: 0f 84 e7 1a 00 00 je 4096e4 - 407bfd: 83 fa 03 cmp $0x3,%edx - 407c00: 0f 84 cd 1a 00 00 je 4096d3 - 407c06: 83 fa 01 cmp $0x1,%edx - 407c09: 0f 84 e6 1a 00 00 je 4096f5 - 407c0f: 48 89 c7 mov %rax,%rdi - 407c12: e8 99 61 01 00 callq 41ddb0 <__cfree> - 407c17: 49 8b 47 08 mov 0x8(%r15),%rax - 407c1b: 48 85 c0 test %rax,%rax - 407c1e: 0f 84 e3 eb ff ff je 406807 - 407c24: 8b 10 mov (%rax),%edx - 407c26: 83 fa 02 cmp $0x2,%edx - 407c29: 0f 84 5c 0f 00 00 je 408b8b - 407c2f: 83 fa 03 cmp $0x3,%edx - 407c32: 0f 84 42 0f 00 00 je 408b7a - 407c38: 83 fa 01 cmp $0x1,%edx - 407c3b: 0f 84 5b 0f 00 00 je 408b9c - 407c41: 48 89 c7 mov %rax,%rdi - 407c44: e8 67 61 01 00 callq 41ddb0 <__cfree> - 407c49: e9 b9 eb ff ff jmpq 406807 - 407c4e: 66 90 xchg %ax,%ax - 407c50: 49 8b 7f 18 mov 0x18(%r15),%rdi - 407c54: e8 b7 df ff ff callq 405c10 <__gettext_free_exp> - 407c59: 49 8b 47 10 mov 0x10(%r15),%rax - 407c5d: 48 85 c0 test %rax,%rax - 407c60: 74 25 je 407c87 - 407c62: 8b 10 mov (%rax),%edx - 407c64: 83 fa 02 cmp $0x2,%edx - 407c67: 0f 84 4f 1d 00 00 je 4099bc - 407c6d: 83 fa 03 cmp $0x3,%edx - 407c70: 0f 84 35 1d 00 00 je 4099ab - 407c76: 83 fa 01 cmp $0x1,%edx - 407c79: 0f 84 4e 1d 00 00 je 4099cd - 407c7f: 48 89 c7 mov %rax,%rdi - 407c82: e8 29 61 01 00 callq 41ddb0 <__cfree> - 407c87: 49 8b 47 08 mov 0x8(%r15),%rax - 407c8b: 48 85 c0 test %rax,%rax - 407c8e: 0f 84 5b ec ff ff je 4068ef - 407c94: 8b 10 mov (%rax),%edx - 407c96: 83 fa 02 cmp $0x2,%edx - 407c99: 0f 84 4d 0f 00 00 je 408bec - 407c9f: 83 fa 03 cmp $0x3,%edx - 407ca2: 0f 84 33 0f 00 00 je 408bdb - 407ca8: 83 fa 01 cmp $0x1,%edx - 407cab: 0f 84 4c 0f 00 00 je 408bfd - 407cb1: 48 89 c7 mov %rax,%rdi - 407cb4: e8 f7 60 01 00 callq 41ddb0 <__cfree> - 407cb9: e9 31 ec ff ff jmpq 4068ef - 407cbe: 66 90 xchg %ax,%ax - 407cc0: 49 8b 7f 18 mov 0x18(%r15),%rdi - 407cc4: e8 47 df ff ff callq 405c10 <__gettext_free_exp> - 407cc9: 49 8b 47 10 mov 0x10(%r15),%rax - 407ccd: 48 85 c0 test %rax,%rax - 407cd0: 74 25 je 407cf7 - 407cd2: 8b 10 mov (%rax),%edx - 407cd4: 83 fa 02 cmp $0x2,%edx - 407cd7: 0f 84 17 1d 00 00 je 4099f4 - 407cdd: 83 fa 03 cmp $0x3,%edx - 407ce0: 0f 84 fd 1c 00 00 je 4099e3 - 407ce6: 83 fa 01 cmp $0x1,%edx - 407ce9: 0f 84 16 1d 00 00 je 409a05 - 407cef: 48 89 c7 mov %rax,%rdi - 407cf2: e8 b9 60 01 00 callq 41ddb0 <__cfree> - 407cf7: 49 8b 47 08 mov 0x8(%r15),%rax - 407cfb: 48 85 c0 test %rax,%rax - 407cfe: 0f 84 22 f0 ff ff je 406d26 - 407d04: 8b 10 mov (%rax),%edx - 407d06: 83 fa 02 cmp $0x2,%edx - 407d09: 0f 84 1b 0e 00 00 je 408b2a - 407d0f: 83 fa 03 cmp $0x3,%edx - 407d12: 0f 84 01 0e 00 00 je 408b19 - 407d18: 83 fa 01 cmp $0x1,%edx - 407d1b: 0f 84 1a 0e 00 00 je 408b3b - 407d21: 48 89 c7 mov %rax,%rdi - 407d24: e8 87 60 01 00 callq 41ddb0 <__cfree> - 407d29: e9 f8 ef ff ff jmpq 406d26 - 407d2e: 66 90 xchg %ax,%ax - 407d30: 49 8b 7f 18 mov 0x18(%r15),%rdi - 407d34: e8 d7 de ff ff callq 405c10 <__gettext_free_exp> - 407d39: 49 8b 47 10 mov 0x10(%r15),%rax - 407d3d: 48 85 c0 test %rax,%rax - 407d40: 74 25 je 407d67 - 407d42: 8b 10 mov (%rax),%edx - 407d44: 83 fa 02 cmp $0x2,%edx - 407d47: 0f 84 3f 1a 00 00 je 40978c - 407d4d: 83 fa 03 cmp $0x3,%edx - 407d50: 0f 84 25 1a 00 00 je 40977b - 407d56: 83 fa 01 cmp $0x1,%edx - 407d59: 0f 84 3e 1a 00 00 je 40979d - 407d5f: 48 89 c7 mov %rax,%rdi - 407d62: e8 49 60 01 00 callq 41ddb0 <__cfree> - 407d67: 49 8b 47 08 mov 0x8(%r15),%rax - 407d6b: 48 85 c0 test %rax,%rax - 407d6e: 0f 84 f2 f0 ff ff je 406e66 - 407d74: 8b 10 mov (%rax),%edx - 407d76: 83 fa 02 cmp $0x2,%edx - 407d79: 0f 84 ce 0e 00 00 je 408c4d - 407d7f: 83 fa 03 cmp $0x3,%edx - 407d82: 0f 84 b4 0e 00 00 je 408c3c - 407d88: 83 fa 01 cmp $0x1,%edx - 407d8b: 0f 84 cd 0e 00 00 je 408c5e - 407d91: 48 89 c7 mov %rax,%rdi - 407d94: e8 17 60 01 00 callq 41ddb0 <__cfree> - 407d99: e9 c8 f0 ff ff jmpq 406e66 - 407d9e: 66 90 xchg %ax,%ax - 407da0: 49 8b 7f 18 mov 0x18(%r15),%rdi - 407da4: e8 67 de ff ff callq 405c10 <__gettext_free_exp> - 407da9: 49 8b 47 10 mov 0x10(%r15),%rax - 407dad: 48 85 c0 test %rax,%rax - 407db0: 74 25 je 407dd7 - 407db2: 8b 10 mov (%rax),%edx - 407db4: 83 fa 02 cmp $0x2,%edx - 407db7: 0f 84 97 19 00 00 je 409754 - 407dbd: 83 fa 03 cmp $0x3,%edx - 407dc0: 0f 84 7d 19 00 00 je 409743 - 407dc6: 83 fa 01 cmp $0x1,%edx - 407dc9: 0f 84 96 19 00 00 je 409765 - 407dcf: 48 89 c7 mov %rax,%rdi - 407dd2: e8 d9 5f 01 00 callq 41ddb0 <__cfree> - 407dd7: 49 8b 47 08 mov 0x8(%r15),%rax - 407ddb: 48 85 c0 test %rax,%rax - 407dde: 0f 84 83 e9 ff ff je 406767 - 407de4: 8b 10 mov (%rax),%edx - 407de6: 83 fa 02 cmp $0x2,%edx - 407de9: 0f 84 bf 0e 00 00 je 408cae - 407def: 83 fa 03 cmp $0x3,%edx - 407df2: 0f 84 a5 0e 00 00 je 408c9d - 407df8: 83 fa 01 cmp $0x1,%edx - 407dfb: 0f 84 be 0e 00 00 je 408cbf - 407e01: 48 89 c7 mov %rax,%rdi - 407e04: e8 a7 5f 01 00 callq 41ddb0 <__cfree> - 407e09: e9 59 e9 ff ff jmpq 406767 - 407e0e: 66 90 xchg %ax,%ax - 407e10: 48 8b 78 18 mov 0x18(%rax),%rdi - 407e14: 48 89 44 24 08 mov %rax,0x8(%rsp) - 407e19: e8 f2 dd ff ff callq 405c10 <__gettext_free_exp> - 407e1e: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 407e23: 48 8b 78 10 mov 0x10(%rax),%rdi - 407e27: 48 89 44 24 08 mov %rax,0x8(%rsp) - 407e2c: e8 df dd ff ff callq 405c10 <__gettext_free_exp> - 407e31: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 407e36: 48 8b 78 08 mov 0x8(%rax),%rdi - 407e3a: 48 89 44 24 08 mov %rax,0x8(%rsp) - 407e3f: e8 cc dd ff ff callq 405c10 <__gettext_free_exp> - 407e44: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 407e49: e9 7b ed ff ff jmpq 406bc9 - 407e4e: 66 90 xchg %ax,%ax - 407e50: 48 8b 78 18 mov 0x18(%rax),%rdi - 407e54: 48 89 44 24 08 mov %rax,0x8(%rsp) - 407e59: e8 b2 dd ff ff callq 405c10 <__gettext_free_exp> - 407e5e: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 407e63: 48 8b 78 10 mov 0x10(%rax),%rdi - 407e67: 48 89 44 24 08 mov %rax,0x8(%rsp) - 407e6c: e8 9f dd ff ff callq 405c10 <__gettext_free_exp> - 407e71: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 407e76: 48 8b 78 08 mov 0x8(%rax),%rdi - 407e7a: 48 89 44 24 08 mov %rax,0x8(%rsp) - 407e7f: e8 8c dd ff ff callq 405c10 <__gettext_free_exp> - 407e84: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 407e89: e9 cb f6 ff ff jmpq 407559 - 407e8e: 66 90 xchg %ax,%ax - 407e90: 48 8b 78 18 mov 0x18(%rax),%rdi - 407e94: 48 89 44 24 08 mov %rax,0x8(%rsp) - 407e99: e8 72 dd ff ff callq 405c10 <__gettext_free_exp> - 407e9e: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 407ea3: 48 8b 78 10 mov 0x10(%rax),%rdi - 407ea7: 48 89 44 24 08 mov %rax,0x8(%rsp) - 407eac: e8 5f dd ff ff callq 405c10 <__gettext_free_exp> - 407eb1: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 407eb6: 48 8b 78 08 mov 0x8(%rax),%rdi - 407eba: 48 89 44 24 08 mov %rax,0x8(%rsp) - 407ebf: e8 4c dd ff ff callq 405c10 <__gettext_free_exp> - 407ec4: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 407ec9: e9 5b eb ff ff jmpq 406a29 - 407ece: 66 90 xchg %ax,%ax - 407ed0: 48 8b 78 18 mov 0x18(%rax),%rdi - 407ed4: 48 89 44 24 08 mov %rax,0x8(%rsp) - 407ed9: e8 32 dd ff ff callq 405c10 <__gettext_free_exp> - 407ede: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 407ee3: 48 8b 78 10 mov 0x10(%rax),%rdi - 407ee7: 48 89 44 24 08 mov %rax,0x8(%rsp) - 407eec: e8 1f dd ff ff callq 405c10 <__gettext_free_exp> - 407ef1: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 407ef6: 48 8b 78 08 mov 0x8(%rax),%rdi - 407efa: 48 89 44 24 08 mov %rax,0x8(%rsp) - 407eff: e8 0c dd ff ff callq 405c10 <__gettext_free_exp> - 407f04: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 407f09: e9 8e f2 ff ff jmpq 40719c - 407f0e: 66 90 xchg %ax,%ax - 407f10: 48 8b 78 18 mov 0x18(%rax),%rdi - 407f14: 48 89 44 24 08 mov %rax,0x8(%rsp) - 407f19: e8 f2 dc ff ff callq 405c10 <__gettext_free_exp> - 407f1e: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 407f23: 48 8b 78 10 mov 0x10(%rax),%rdi - 407f27: 48 89 44 24 08 mov %rax,0x8(%rsp) - 407f2c: e8 df dc ff ff callq 405c10 <__gettext_free_exp> - 407f31: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 407f36: 48 8b 78 08 mov 0x8(%rax),%rdi - 407f3a: 48 89 44 24 08 mov %rax,0x8(%rsp) - 407f3f: e8 cc dc ff ff callq 405c10 <__gettext_free_exp> - 407f44: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 407f49: e9 c5 eb ff ff jmpq 406b13 - 407f4e: 66 90 xchg %ax,%ax - 407f50: 48 8b 78 18 mov 0x18(%rax),%rdi - 407f54: 48 89 44 24 08 mov %rax,0x8(%rsp) - 407f59: e8 b2 dc ff ff callq 405c10 <__gettext_free_exp> - 407f5e: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 407f63: 48 8b 78 10 mov 0x10(%rax),%rdi - 407f67: 48 89 44 24 08 mov %rax,0x8(%rsp) - 407f6c: e8 9f dc ff ff callq 405c10 <__gettext_free_exp> - 407f71: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 407f76: 48 8b 78 08 mov 0x8(%rax),%rdi - 407f7a: 48 89 44 24 08 mov %rax,0x8(%rsp) - 407f7f: e8 8c dc ff ff callq 405c10 <__gettext_free_exp> - 407f84: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 407f89: e9 ee f2 ff ff jmpq 40727c - 407f8e: 66 90 xchg %ax,%ax - 407f90: 48 8b 78 18 mov 0x18(%rax),%rdi - 407f94: 48 89 44 24 08 mov %rax,0x8(%rsp) - 407f99: e8 72 dc ff ff callq 405c10 <__gettext_free_exp> - 407f9e: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 407fa3: 48 8b 78 10 mov 0x10(%rax),%rdi - 407fa7: 48 89 44 24 08 mov %rax,0x8(%rsp) - 407fac: e8 5f dc ff ff callq 405c10 <__gettext_free_exp> - 407fb1: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 407fb6: 48 8b 78 08 mov 0x8(%rax),%rdi - 407fba: 48 89 44 24 08 mov %rax,0x8(%rsp) - 407fbf: e8 4c dc ff ff callq 405c10 <__gettext_free_exp> - 407fc4: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 407fc9: e9 e6 f0 ff ff jmpq 4070b4 - 407fce: 66 90 xchg %ax,%ax - 407fd0: 48 8b 78 18 mov 0x18(%rax),%rdi - 407fd4: 48 89 44 24 08 mov %rax,0x8(%rsp) - 407fd9: e8 32 dc ff ff callq 405c10 <__gettext_free_exp> - 407fde: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 407fe3: 48 8b 78 10 mov 0x10(%rax),%rdi - 407fe7: 48 89 44 24 08 mov %rax,0x8(%rsp) - 407fec: e8 1f dc ff ff callq 405c10 <__gettext_free_exp> - 407ff1: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 407ff6: 48 8b 78 08 mov 0x8(%rax),%rdi - 407ffa: 48 89 44 24 08 mov %rax,0x8(%rsp) - 407fff: e8 0c dc ff ff callq 405c10 <__gettext_free_exp> - 408004: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408009: e9 4e f3 ff ff jmpq 40735c - 40800e: 66 90 xchg %ax,%ax - 408010: 48 8b 78 18 mov 0x18(%rax),%rdi - 408014: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408019: e8 f2 db ff ff callq 405c10 <__gettext_free_exp> - 40801e: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408023: 48 8b 78 10 mov 0x10(%rax),%rdi - 408027: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40802c: e8 df db ff ff callq 405c10 <__gettext_free_exp> - 408031: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408036: 48 8b 78 08 mov 0x8(%rax),%rdi - 40803a: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40803f: e8 cc db ff ff callq 405c10 <__gettext_free_exp> - 408044: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408049: e9 23 f8 ff ff jmpq 407871 - 40804e: 66 90 xchg %ax,%ax - 408050: 48 8b 78 18 mov 0x18(%rax),%rdi - 408054: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408059: e8 b2 db ff ff callq 405c10 <__gettext_free_exp> - 40805e: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408063: 48 8b 78 10 mov 0x10(%rax),%rdi - 408067: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40806c: e8 9f db ff ff callq 405c10 <__gettext_free_exp> - 408071: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408076: 48 8b 78 08 mov 0x8(%rax),%rdi - 40807a: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40807f: e8 8c db ff ff callq 405c10 <__gettext_free_exp> - 408084: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408089: e9 c3 f6 ff ff jmpq 407751 - 40808e: 66 90 xchg %ax,%ax - 408090: 48 8b 04 24 mov (%rsp),%rax - 408094: 48 8b 78 18 mov 0x18(%rax),%rdi - 408098: e8 73 db ff ff callq 405c10 <__gettext_free_exp> - 40809d: 48 8b 04 24 mov (%rsp),%rax - 4080a1: 48 8b 40 10 mov 0x10(%rax),%rax - 4080a5: 48 85 c0 test %rax,%rax - 4080a8: 74 25 je 4080cf - 4080aa: 8b 10 mov (%rax),%edx - 4080ac: 83 fa 02 cmp $0x2,%edx - 4080af: 0f 84 3f 08 00 00 je 4088f4 - 4080b5: 83 fa 03 cmp $0x3,%edx - 4080b8: 0f 84 23 08 00 00 je 4088e1 - 4080be: 83 fa 01 cmp $0x1,%edx - 4080c1: 0f 84 40 08 00 00 je 408907 - 4080c7: 48 89 c7 mov %rax,%rdi - 4080ca: e8 e1 5c 01 00 callq 41ddb0 <__cfree> - 4080cf: 48 8b 04 24 mov (%rsp),%rax - 4080d3: 48 8b 40 08 mov 0x8(%rax),%rax - 4080d7: 48 85 c0 test %rax,%rax - 4080da: 0f 84 a1 eb ff ff je 406c81 - 4080e0: 8b 10 mov (%rax),%edx - 4080e2: 83 fa 02 cmp $0x2,%edx - 4080e5: 0f 84 41 0d 00 00 je 408e2c - 4080eb: 83 fa 03 cmp $0x3,%edx - 4080ee: 0f 84 25 0d 00 00 je 408e19 - 4080f4: 83 fa 01 cmp $0x1,%edx - 4080f7: 0f 84 42 0d 00 00 je 408e3f - 4080fd: 48 89 c7 mov %rax,%rdi - 408100: e8 ab 5c 01 00 callq 41ddb0 <__cfree> - 408105: e9 77 eb ff ff jmpq 406c81 - 40810a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 408110: 48 8b 04 24 mov (%rsp),%rax - 408114: 48 8b 78 18 mov 0x18(%rax),%rdi - 408118: e8 f3 da ff ff callq 405c10 <__gettext_free_exp> - 40811d: 48 8b 04 24 mov (%rsp),%rax - 408121: 48 8b 40 10 mov 0x10(%rax),%rax - 408125: 48 85 c0 test %rax,%rax - 408128: 74 25 je 40814f - 40812a: 8b 10 mov (%rax),%edx - 40812c: 83 fa 02 cmp $0x2,%edx - 40812f: 0f 84 43 07 00 00 je 408878 - 408135: 83 fa 03 cmp $0x3,%edx - 408138: 0f 84 27 07 00 00 je 408865 - 40813e: 83 fa 01 cmp $0x1,%edx - 408141: 0f 84 44 07 00 00 je 40888b - 408147: 48 89 c7 mov %rax,%rdi - 40814a: e8 61 5c 01 00 callq 41ddb0 <__cfree> - 40814f: 48 8b 04 24 mov (%rsp),%rax - 408153: 48 8b 40 08 mov 0x8(%rax),%rax - 408157: 48 85 c0 test %rax,%rax - 40815a: 0f 84 50 f3 ff ff je 4074b0 - 408160: 8b 10 mov (%rax),%edx - 408162: 83 fa 02 cmp $0x2,%edx - 408165: 0f 84 45 0c 00 00 je 408db0 - 40816b: 83 fa 03 cmp $0x3,%edx - 40816e: 0f 84 29 0c 00 00 je 408d9d - 408174: 83 fa 01 cmp $0x1,%edx - 408177: 0f 84 46 0c 00 00 je 408dc3 - 40817d: 48 89 c7 mov %rax,%rdi - 408180: e8 2b 5c 01 00 callq 41ddb0 <__cfree> - 408185: e9 26 f3 ff ff jmpq 4074b0 - 40818a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 408190: 48 8b 04 24 mov (%rsp),%rax - 408194: 48 8b 78 18 mov 0x18(%rax),%rdi - 408198: e8 73 da ff ff callq 405c10 <__gettext_free_exp> - 40819d: 48 8b 04 24 mov (%rsp),%rax - 4081a1: 48 8b 40 10 mov 0x10(%rax),%rax - 4081a5: 48 85 c0 test %rax,%rax - 4081a8: 74 25 je 4081cf - 4081aa: 8b 10 mov (%rax),%edx - 4081ac: 83 fa 02 cmp $0x2,%edx - 4081af: 0f 84 7d 07 00 00 je 408932 - 4081b5: 83 fa 03 cmp $0x3,%edx - 4081b8: 0f 84 61 07 00 00 je 40891f - 4081be: 83 fa 01 cmp $0x1,%edx - 4081c1: 0f 84 7e 07 00 00 je 408945 - 4081c7: 48 89 c7 mov %rax,%rdi - 4081ca: e8 e1 5b 01 00 callq 41ddb0 <__cfree> - 4081cf: 48 8b 04 24 mov (%rsp),%rax - 4081d3: 48 8b 40 08 mov 0x8(%rax),%rax - 4081d7: 48 85 c0 test %rax,%rax - 4081da: 0f 84 e8 f5 ff ff je 4077c8 - 4081e0: 8b 10 mov (%rax),%edx - 4081e2: 83 fa 02 cmp $0x2,%edx - 4081e5: 0f 84 87 0b 00 00 je 408d72 - 4081eb: 83 fa 03 cmp $0x3,%edx - 4081ee: 0f 84 6b 0b 00 00 je 408d5f - 4081f4: 83 fa 01 cmp $0x1,%edx - 4081f7: 0f 84 88 0b 00 00 je 408d85 - 4081fd: 48 89 c7 mov %rax,%rdi - 408200: e8 ab 5b 01 00 callq 41ddb0 <__cfree> - 408205: e9 be f5 ff ff jmpq 4077c8 - 40820a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 408210: 48 8b 04 24 mov (%rsp),%rax - 408214: 48 8b 78 18 mov 0x18(%rax),%rdi - 408218: e8 f3 d9 ff ff callq 405c10 <__gettext_free_exp> - 40821d: 48 8b 04 24 mov (%rsp),%rax - 408221: 48 8b 40 10 mov 0x10(%rax),%rax - 408225: 48 85 c0 test %rax,%rax - 408228: 74 25 je 40824f - 40822a: 8b 10 mov (%rax),%edx - 40822c: 83 fa 02 cmp $0x2,%edx - 40822f: 0f 84 81 06 00 00 je 4088b6 - 408235: 83 fa 03 cmp $0x3,%edx - 408238: 0f 84 65 06 00 00 je 4088a3 - 40823e: 83 fa 01 cmp $0x1,%edx - 408241: 0f 84 82 06 00 00 je 4088c9 - 408247: 48 89 c7 mov %rax,%rdi - 40824a: e8 61 5b 01 00 callq 41ddb0 <__cfree> - 40824f: 48 8b 04 24 mov (%rsp),%rax - 408253: 48 8b 40 08 mov 0x8(%rax),%rax - 408257: 48 85 c0 test %rax,%rax - 40825a: 0f 84 48 f4 ff ff je 4076a8 - 408260: 8b 10 mov (%rax),%edx - 408262: 83 fa 02 cmp $0x2,%edx - 408265: 0f 84 83 0b 00 00 je 408dee - 40826b: 83 fa 03 cmp $0x3,%edx - 40826e: 0f 84 67 0b 00 00 je 408ddb - 408274: 83 fa 01 cmp $0x1,%edx - 408277: 0f 84 84 0b 00 00 je 408e01 - 40827d: 48 89 c7 mov %rax,%rdi - 408280: e8 2b 5b 01 00 callq 41ddb0 <__cfree> - 408285: e9 1e f4 ff ff jmpq 4076a8 - 40828a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 408290: 49 8b 7d 18 mov 0x18(%r13),%rdi - 408294: e8 77 d9 ff ff callq 405c10 <__gettext_free_exp> - 408299: 4d 8b 7d 10 mov 0x10(%r13),%r15 - 40829d: 4d 85 ff test %r15,%r15 - 4082a0: 74 26 je 4082c8 - 4082a2: 41 8b 07 mov (%r15),%eax - 4082a5: 83 f8 02 cmp $0x2,%eax - 4082a8: 0f 84 1e 07 00 00 je 4089cc - 4082ae: 83 f8 03 cmp $0x3,%eax - 4082b1: 0f 84 0c 07 00 00 je 4089c3 - 4082b7: 83 f8 01 cmp $0x1,%eax - 4082ba: 0f 84 15 07 00 00 je 4089d5 - 4082c0: 4c 89 ff mov %r15,%rdi - 4082c3: e8 e8 5a 01 00 callq 41ddb0 <__cfree> - 4082c8: 4d 8b 7d 08 mov 0x8(%r13),%r15 - 4082cc: 4d 85 ff test %r15,%r15 - 4082cf: 0f 84 e4 ec ff ff je 406fb9 - 4082d5: 41 8b 07 mov (%r15),%eax - 4082d8: 83 f8 02 cmp $0x2,%eax - 4082db: 0f 84 07 0d 00 00 je 408fe8 - 4082e1: 83 f8 03 cmp $0x3,%eax - 4082e4: 0f 84 f5 0c 00 00 je 408fdf - 4082ea: 83 f8 01 cmp $0x1,%eax - 4082ed: 0f 84 fe 0c 00 00 je 408ff1 - 4082f3: 4c 89 ff mov %r15,%rdi - 4082f6: e8 b5 5a 01 00 callq 41ddb0 <__cfree> - 4082fb: e9 b9 ec ff ff jmpq 406fb9 - 408300: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 408304: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408309: 48 89 14 24 mov %rdx,(%rsp) - 40830d: e8 fe d8 ff ff callq 405c10 <__gettext_free_exp> - 408312: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408317: 48 8b 14 24 mov (%rsp),%rdx - 40831b: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 40831f: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408324: 48 89 14 24 mov %rdx,(%rsp) - 408328: e8 e3 d8 ff ff callq 405c10 <__gettext_free_exp> - 40832d: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408332: 48 8b 14 24 mov (%rsp),%rdx - 408336: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 40833a: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40833f: 48 89 14 24 mov %rdx,(%rsp) - 408343: e8 c8 d8 ff ff callq 405c10 <__gettext_free_exp> - 408348: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40834d: 48 8b 14 24 mov (%rsp),%rdx - 408351: e9 b0 f0 ff ff jmpq 407406 - 408356: 48 8b 78 18 mov 0x18(%rax),%rdi - 40835a: 48 89 04 24 mov %rax,(%rsp) - 40835e: e8 ad d8 ff ff callq 405c10 <__gettext_free_exp> - 408363: 48 8b 04 24 mov (%rsp),%rax - 408367: 48 8b 78 10 mov 0x10(%rax),%rdi - 40836b: 48 89 04 24 mov %rax,(%rsp) - 40836f: e8 9c d8 ff ff callq 405c10 <__gettext_free_exp> - 408374: 48 8b 04 24 mov (%rsp),%rax - 408378: 48 8b 50 08 mov 0x8(%rax),%rdx - 40837c: 48 85 d2 test %rdx,%rdx - 40837f: 0f 84 11 f2 ff ff je 407596 - 408385: 8b 0a mov (%rdx),%ecx - 408387: 83 f9 02 cmp $0x2,%ecx - 40838a: 0f 84 c3 10 00 00 je 409453 - 408390: 83 f9 03 cmp $0x3,%ecx - 408393: 0f 84 9f 10 00 00 je 409438 - 408399: 83 f9 01 cmp $0x1,%ecx - 40839c: 0f 84 cc 10 00 00 je 40946e - 4083a2: 48 89 d7 mov %rdx,%rdi - 4083a5: 48 89 04 24 mov %rax,(%rsp) - 4083a9: e8 02 5a 01 00 callq 41ddb0 <__cfree> - 4083ae: 48 8b 04 24 mov (%rsp),%rax - 4083b2: e9 df f1 ff ff jmpq 407596 - 4083b7: 48 8b 78 18 mov 0x18(%rax),%rdi - 4083bb: 48 89 04 24 mov %rax,(%rsp) - 4083bf: e8 4c d8 ff ff callq 405c10 <__gettext_free_exp> - 4083c4: 48 8b 04 24 mov (%rsp),%rax - 4083c8: 48 8b 78 10 mov 0x10(%rax),%rdi - 4083cc: 48 89 04 24 mov %rax,(%rsp) - 4083d0: e8 3b d8 ff ff callq 405c10 <__gettext_free_exp> - 4083d5: 48 8b 04 24 mov (%rsp),%rax - 4083d9: 48 8b 50 08 mov 0x8(%rax),%rdx - 4083dd: 48 85 d2 test %rdx,%rdx - 4083e0: 0f 84 d9 e9 ff ff je 406dbf - 4083e6: 8b 0a mov (%rdx),%ecx - 4083e8: 83 f9 02 cmp $0x2,%ecx - 4083eb: 0f 84 4c 11 00 00 je 40953d - 4083f1: 83 f9 03 cmp $0x3,%ecx - 4083f4: 0f 84 28 11 00 00 je 409522 - 4083fa: 83 f9 01 cmp $0x1,%ecx - 4083fd: 0f 84 55 11 00 00 je 409558 - 408403: 48 89 d7 mov %rdx,%rdi - 408406: 48 89 04 24 mov %rax,(%rsp) - 40840a: e8 a1 59 01 00 callq 41ddb0 <__cfree> - 40840f: 48 8b 04 24 mov (%rsp),%rax - 408413: e9 a7 e9 ff ff jmpq 406dbf - 408418: 48 8b 78 18 mov 0x18(%rax),%rdi - 40841c: 48 89 04 24 mov %rax,(%rsp) - 408420: e8 eb d7 ff ff callq 405c10 <__gettext_free_exp> - 408425: 48 8b 04 24 mov (%rsp),%rax - 408429: 48 8b 78 10 mov 0x10(%rax),%rdi - 40842d: 48 89 04 24 mov %rax,(%rsp) - 408431: e8 da d7 ff ff callq 405c10 <__gettext_free_exp> - 408436: 48 8b 04 24 mov (%rsp),%rax - 40843a: 48 8b 50 08 mov 0x8(%rax),%rdx - 40843e: 48 85 d2 test %rdx,%rdx - 408441: 0f 84 6f f4 ff ff je 4078b6 - 408447: 8b 0a mov (%rdx),%ecx - 408449: 83 f9 02 cmp $0x2,%ecx - 40844c: 0f 84 95 10 00 00 je 4094e7 - 408452: 83 f9 03 cmp $0x3,%ecx - 408455: 0f 84 71 10 00 00 je 4094cc - 40845b: 83 f9 01 cmp $0x1,%ecx - 40845e: 0f 84 9e 10 00 00 je 409502 - 408464: 48 89 d7 mov %rdx,%rdi - 408467: 48 89 04 24 mov %rax,(%rsp) - 40846b: e8 40 59 01 00 callq 41ddb0 <__cfree> - 408470: 48 8b 04 24 mov (%rsp),%rax - 408474: e9 3d f4 ff ff jmpq 4078b6 - 408479: 48 8b 78 18 mov 0x18(%rax),%rdi - 40847d: 48 89 04 24 mov %rax,(%rsp) - 408481: e8 8a d7 ff ff callq 405c10 <__gettext_free_exp> - 408486: 48 8b 04 24 mov (%rsp),%rax - 40848a: 48 8b 78 10 mov 0x10(%rax),%rdi - 40848e: 48 89 04 24 mov %rax,(%rsp) - 408492: e8 79 d7 ff ff callq 405c10 <__gettext_free_exp> - 408497: 48 8b 04 24 mov (%rsp),%rax - 40849b: 48 8b 50 08 mov 0x8(%rax),%rdx - 40849f: 48 85 d2 test %rdx,%rdx - 4084a2: 0f 84 57 ea ff ff je 406eff - 4084a8: 8b 0a mov (%rdx),%ecx - 4084aa: 83 f9 02 cmp $0x2,%ecx - 4084ad: 0f 84 bc 0c 00 00 je 40916f - 4084b3: 83 f9 03 cmp $0x3,%ecx - 4084b6: 0f 84 98 0c 00 00 je 409154 - 4084bc: 83 f9 01 cmp $0x1,%ecx - 4084bf: 0f 84 c5 0c 00 00 je 40918a - 4084c5: 48 89 d7 mov %rdx,%rdi - 4084c8: 48 89 04 24 mov %rax,(%rsp) - 4084cc: e8 df 58 01 00 callq 41ddb0 <__cfree> - 4084d1: 48 8b 04 24 mov (%rsp),%rax - 4084d5: e9 25 ea ff ff jmpq 406eff - 4084da: 48 8b 78 18 mov 0x18(%rax),%rdi - 4084de: 48 89 04 24 mov %rax,(%rsp) - 4084e2: e8 29 d7 ff ff callq 405c10 <__gettext_free_exp> - 4084e7: 48 8b 04 24 mov (%rsp),%rax - 4084eb: 48 8b 78 10 mov 0x10(%rax),%rdi - 4084ef: 48 89 04 24 mov %rax,(%rsp) - 4084f3: e8 18 d7 ff ff callq 405c10 <__gettext_free_exp> - 4084f8: 48 8b 04 24 mov (%rsp),%rax - 4084fc: 48 8b 50 08 mov 0x8(%rax),%rdx - 408500: 48 85 d2 test %rdx,%rdx - 408503: 0f 84 fd f0 ff ff je 407606 - 408509: 8b 0a mov (%rdx),%ecx - 40850b: 83 f9 02 cmp $0x2,%ecx - 40850e: 0f 84 e9 0e 00 00 je 4093fd - 408514: 83 f9 03 cmp $0x3,%ecx - 408517: 0f 84 c5 0e 00 00 je 4093e2 - 40851d: 83 f9 01 cmp $0x1,%ecx - 408520: 0f 84 f2 0e 00 00 je 409418 - 408526: 48 89 d7 mov %rdx,%rdi - 408529: 48 89 04 24 mov %rax,(%rsp) - 40852d: e8 7e 58 01 00 callq 41ddb0 <__cfree> - 408532: 48 8b 04 24 mov (%rsp),%rax - 408536: e9 cb f0 ff ff jmpq 407606 - 40853b: 48 8b 04 24 mov (%rsp),%rax - 40853f: 48 8b 78 18 mov 0x18(%rax),%rdi - 408543: e8 c8 d6 ff ff callq 405c10 <__gettext_free_exp> - 408548: 48 8b 04 24 mov (%rsp),%rax - 40854c: 48 8b 40 10 mov 0x10(%rax),%rax - 408550: 48 85 c0 test %rax,%rax - 408553: 74 25 je 40857a - 408555: 8b 10 mov (%rax),%edx - 408557: 83 fa 02 cmp $0x2,%edx - 40855a: 0f 84 96 04 00 00 je 4089f6 - 408560: 83 fa 03 cmp $0x3,%edx - 408563: 0f 84 7a 04 00 00 je 4089e3 - 408569: 83 fa 01 cmp $0x1,%edx - 40856c: 0f 84 97 04 00 00 je 408a09 - 408572: 48 89 c7 mov %rax,%rdi - 408575: e8 36 58 01 00 callq 41ddb0 <__cfree> - 40857a: 48 8b 04 24 mov (%rsp),%rax - 40857e: 48 8b 40 08 mov 0x8(%rax),%rax - 408582: 48 85 c0 test %rax,%rax - 408585: 0f 84 32 df ff ff je 4064bd - 40858b: 8b 10 mov (%rax),%edx - 40858d: 83 fa 02 cmp $0x2,%edx - 408590: 0f 84 21 0e 00 00 je 4093b7 - 408596: 83 fa 03 cmp $0x3,%edx - 408599: 0f 84 05 0e 00 00 je 4093a4 - 40859f: 83 fa 01 cmp $0x1,%edx - 4085a2: 0f 84 22 0e 00 00 je 4093ca - 4085a8: 48 89 c7 mov %rax,%rdi - 4085ab: e8 00 58 01 00 callq 41ddb0 <__cfree> - 4085b0: e9 08 df ff ff jmpq 4064bd - 4085b5: 49 8b 7f 18 mov 0x18(%r15),%rdi - 4085b9: e8 52 d6 ff ff callq 405c10 <__gettext_free_exp> - 4085be: 49 8b 7f 10 mov 0x10(%r15),%rdi - 4085c2: e8 49 d6 ff ff callq 405c10 <__gettext_free_exp> - 4085c7: 49 8b 47 08 mov 0x8(%r15),%rax - 4085cb: 48 85 c0 test %rax,%rax - 4085ce: 0f 84 ec e2 ff ff je 4068c0 - 4085d4: 8b 10 mov (%rax),%edx - 4085d6: 83 fa 02 cmp $0x2,%edx - 4085d9: 0f 84 35 13 00 00 je 409914 - 4085df: 83 fa 03 cmp $0x3,%edx - 4085e2: 0f 84 1b 13 00 00 je 409903 - 4085e8: 83 fa 01 cmp $0x1,%edx - 4085eb: 0f 84 34 13 00 00 je 409925 - 4085f1: 48 89 c7 mov %rax,%rdi - 4085f4: e8 b7 57 01 00 callq 41ddb0 <__cfree> - 4085f9: e9 c2 e2 ff ff jmpq 4068c0 - 4085fe: 49 8b 7f 18 mov 0x18(%r15),%rdi - 408602: e8 09 d6 ff ff callq 405c10 <__gettext_free_exp> - 408607: 49 8b 7f 10 mov 0x10(%r15),%rdi - 40860b: e8 00 d6 ff ff callq 405c10 <__gettext_free_exp> - 408610: 49 8b 47 08 mov 0x8(%r15),%rax - 408614: 48 85 c0 test %rax,%rax - 408617: 0f 84 95 df ff ff je 4065b2 - 40861d: 8b 10 mov (%rax),%edx - 40861f: 83 fa 02 cmp $0x2,%edx - 408622: 0f 84 5c 13 00 00 je 409984 - 408628: 83 fa 03 cmp $0x3,%edx - 40862b: 0f 84 42 13 00 00 je 409973 - 408631: 83 fa 01 cmp $0x1,%edx - 408634: 0f 84 5b 13 00 00 je 409995 - 40863a: 48 89 c7 mov %rax,%rdi - 40863d: e8 6e 57 01 00 callq 41ddb0 <__cfree> - 408642: e9 6b df ff ff jmpq 4065b2 - 408647: 49 8b 7f 18 mov 0x18(%r15),%rdi - 40864b: e8 c0 d5 ff ff callq 405c10 <__gettext_free_exp> - 408650: 49 8b 7f 10 mov 0x10(%r15),%rdi - 408654: e8 b7 d5 ff ff callq 405c10 <__gettext_free_exp> - 408659: 49 8b 47 08 mov 0x8(%r15),%rax - 40865d: 48 85 c0 test %rax,%rax - 408660: 0f 84 c1 f2 ff ff je 407927 - 408666: 8b 10 mov (%rax),%edx - 408668: 83 fa 02 cmp $0x2,%edx - 40866b: 0f 84 ab 10 00 00 je 40971c - 408671: 83 fa 03 cmp $0x3,%edx - 408674: 0f 84 91 10 00 00 je 40970b - 40867a: 83 fa 01 cmp $0x1,%edx - 40867d: 0f 84 aa 10 00 00 je 40972d - 408683: 48 89 c7 mov %rax,%rdi - 408686: e8 25 57 01 00 callq 41ddb0 <__cfree> - 40868b: e9 97 f2 ff ff jmpq 407927 - 408690: 48 8b 78 18 mov 0x18(%rax),%rdi - 408694: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408699: e8 72 d5 ff ff callq 405c10 <__gettext_free_exp> - 40869e: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4086a3: 48 8b 78 10 mov 0x10(%rax),%rdi - 4086a7: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4086ac: e8 5f d5 ff ff callq 405c10 <__gettext_free_exp> - 4086b1: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4086b6: 48 8b 78 08 mov 0x8(%rax),%rdi - 4086ba: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4086bf: e8 4c d5 ff ff callq 405c10 <__gettext_free_exp> - 4086c4: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4086c9: e9 13 e4 ff ff jmpq 406ae1 - 4086ce: 48 8b 78 18 mov 0x18(%rax),%rdi - 4086d2: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4086d7: e8 34 d5 ff ff callq 405c10 <__gettext_free_exp> - 4086dc: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4086e1: 48 8b 78 10 mov 0x10(%rax),%rdi - 4086e5: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4086ea: e8 21 d5 ff ff callq 405c10 <__gettext_free_exp> - 4086ef: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4086f4: 48 8b 78 08 mov 0x8(%rax),%rdi - 4086f8: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4086fd: e8 0e d5 ff ff callq 405c10 <__gettext_free_exp> - 408702: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408707: e9 eb e2 ff ff jmpq 4069f7 - 40870c: 48 8b 78 18 mov 0x18(%rax),%rdi - 408710: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408715: e8 f6 d4 ff ff callq 405c10 <__gettext_free_exp> - 40871a: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40871f: 48 8b 78 10 mov 0x10(%rax),%rdi - 408723: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408728: e8 e3 d4 ff ff callq 405c10 <__gettext_free_exp> - 40872d: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408732: 48 8b 78 08 mov 0x8(%rax),%rdi - 408736: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40873b: e8 d0 d4 ff ff callq 405c10 <__gettext_free_exp> - 408740: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408745: e9 f5 f0 ff ff jmpq 40783f - 40874a: 48 8b 78 18 mov 0x18(%rax),%rdi - 40874e: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408753: e8 b8 d4 ff ff callq 405c10 <__gettext_free_exp> - 408758: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40875d: 48 8b 78 10 mov 0x10(%rax),%rdi - 408761: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408766: e8 a5 d4 ff ff callq 405c10 <__gettext_free_exp> - 40876b: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408770: 48 8b 78 08 mov 0x8(%rax),%rdi - 408774: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408779: e8 92 d4 ff ff callq 405c10 <__gettext_free_exp> - 40877e: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408783: e9 9f ed ff ff jmpq 407527 - 408788: 48 8b 78 18 mov 0x18(%rax),%rdi - 40878c: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408791: e8 7a d4 ff ff callq 405c10 <__gettext_free_exp> - 408796: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40879b: 48 8b 78 10 mov 0x10(%rax),%rdi - 40879f: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4087a4: e8 67 d4 ff ff callq 405c10 <__gettext_free_exp> - 4087a9: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4087ae: 48 8b 78 08 mov 0x8(%rax),%rdi - 4087b2: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4087b7: e8 54 d4 ff ff callq 405c10 <__gettext_free_exp> - 4087bc: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4087c1: e9 d1 e3 ff ff jmpq 406b97 - 4087c6: 48 8b 78 18 mov 0x18(%rax),%rdi - 4087ca: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4087cf: e8 3c d4 ff ff callq 405c10 <__gettext_free_exp> - 4087d4: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4087d9: 48 8b 78 10 mov 0x10(%rax),%rdi - 4087dd: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4087e2: e8 29 d4 ff ff callq 405c10 <__gettext_free_exp> - 4087e7: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4087ec: 48 8b 78 08 mov 0x8(%rax),%rdi - 4087f0: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4087f5: e8 16 d4 ff ff callq 405c10 <__gettext_free_exp> - 4087fa: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4087ff: e9 1b ef ff ff jmpq 40771f - 408804: 48 8b 78 18 mov 0x18(%rax),%rdi - 408808: 48 89 04 24 mov %rax,(%rsp) - 40880c: e8 ff d3 ff ff callq 405c10 <__gettext_free_exp> - 408811: 48 8b 04 24 mov (%rsp),%rax - 408815: 48 8b 78 10 mov 0x10(%rax),%rdi - 408819: 48 89 04 24 mov %rax,(%rsp) - 40881d: e8 ee d3 ff ff callq 405c10 <__gettext_free_exp> - 408822: 48 8b 04 24 mov (%rsp),%rax - 408826: 48 8b 50 08 mov 0x8(%rax),%rdx - 40882a: 48 85 d2 test %rdx,%rdx - 40882d: 0f 84 1c e4 ff ff je 406c4f - 408833: 8b 0a mov (%rdx),%ecx - 408835: 83 f9 02 cmp $0x2,%ecx - 408838: 0f 84 3a 01 00 00 je 408978 - 40883e: 83 f9 03 cmp $0x3,%ecx - 408841: 0f 84 16 01 00 00 je 40895d - 408847: 83 f9 01 cmp $0x1,%ecx - 40884a: 0f 84 43 01 00 00 je 408993 - 408850: 48 89 d7 mov %rdx,%rdi - 408853: 48 89 04 24 mov %rax,(%rsp) - 408857: e8 54 55 01 00 callq 41ddb0 <__cfree> - 40885c: 48 8b 04 24 mov (%rsp),%rax - 408860: e9 ea e3 ff ff jmpq 406c4f - 408865: 48 8b 78 18 mov 0x18(%rax),%rdi - 408869: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40886e: e8 9d d3 ff ff callq 405c10 <__gettext_free_exp> - 408873: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408878: 48 8b 78 10 mov 0x10(%rax),%rdi - 40887c: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408881: e8 8a d3 ff ff callq 405c10 <__gettext_free_exp> - 408886: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40888b: 48 8b 78 08 mov 0x8(%rax),%rdi - 40888f: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408894: e8 77 d3 ff ff callq 405c10 <__gettext_free_exp> - 408899: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40889e: e9 a4 f8 ff ff jmpq 408147 - 4088a3: 48 8b 78 18 mov 0x18(%rax),%rdi - 4088a7: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4088ac: e8 5f d3 ff ff callq 405c10 <__gettext_free_exp> - 4088b1: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4088b6: 48 8b 78 10 mov 0x10(%rax),%rdi - 4088ba: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4088bf: e8 4c d3 ff ff callq 405c10 <__gettext_free_exp> - 4088c4: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4088c9: 48 8b 78 08 mov 0x8(%rax),%rdi - 4088cd: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4088d2: e8 39 d3 ff ff callq 405c10 <__gettext_free_exp> - 4088d7: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4088dc: e9 66 f9 ff ff jmpq 408247 - 4088e1: 48 8b 78 18 mov 0x18(%rax),%rdi - 4088e5: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4088ea: e8 21 d3 ff ff callq 405c10 <__gettext_free_exp> - 4088ef: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4088f4: 48 8b 78 10 mov 0x10(%rax),%rdi - 4088f8: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4088fd: e8 0e d3 ff ff callq 405c10 <__gettext_free_exp> - 408902: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408907: 48 8b 78 08 mov 0x8(%rax),%rdi - 40890b: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408910: e8 fb d2 ff ff callq 405c10 <__gettext_free_exp> - 408915: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40891a: e9 a8 f7 ff ff jmpq 4080c7 - 40891f: 48 8b 78 18 mov 0x18(%rax),%rdi - 408923: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408928: e8 e3 d2 ff ff callq 405c10 <__gettext_free_exp> - 40892d: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408932: 48 8b 78 10 mov 0x10(%rax),%rdi - 408936: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40893b: e8 d0 d2 ff ff callq 405c10 <__gettext_free_exp> - 408940: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408945: 48 8b 78 08 mov 0x8(%rax),%rdi - 408949: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40894e: e8 bd d2 ff ff callq 405c10 <__gettext_free_exp> - 408953: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408958: e9 6a f8 ff ff jmpq 4081c7 - 40895d: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 408961: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408966: 48 89 14 24 mov %rdx,(%rsp) - 40896a: e8 a1 d2 ff ff callq 405c10 <__gettext_free_exp> - 40896f: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408974: 48 8b 14 24 mov (%rsp),%rdx - 408978: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 40897c: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408981: 48 89 14 24 mov %rdx,(%rsp) - 408985: e8 86 d2 ff ff callq 405c10 <__gettext_free_exp> - 40898a: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40898f: 48 8b 14 24 mov (%rsp),%rdx - 408993: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 408997: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40899c: 48 89 14 24 mov %rdx,(%rsp) - 4089a0: e8 6b d2 ff ff callq 405c10 <__gettext_free_exp> - 4089a5: 48 8b 14 24 mov (%rsp),%rdx - 4089a9: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4089ae: 48 89 d7 mov %rdx,%rdi - 4089b1: 48 89 04 24 mov %rax,(%rsp) - 4089b5: e8 f6 53 01 00 callq 41ddb0 <__cfree> - 4089ba: 48 8b 04 24 mov (%rsp),%rax - 4089be: e9 8c e2 ff ff jmpq 406c4f - 4089c3: 49 8b 7f 18 mov 0x18(%r15),%rdi - 4089c7: e8 44 d2 ff ff callq 405c10 <__gettext_free_exp> - 4089cc: 49 8b 7f 10 mov 0x10(%r15),%rdi - 4089d0: e8 3b d2 ff ff callq 405c10 <__gettext_free_exp> - 4089d5: 49 8b 7f 08 mov 0x8(%r15),%rdi - 4089d9: e8 32 d2 ff ff callq 405c10 <__gettext_free_exp> - 4089de: e9 dd f8 ff ff jmpq 4082c0 - 4089e3: 48 8b 78 18 mov 0x18(%rax),%rdi - 4089e7: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4089ec: e8 1f d2 ff ff callq 405c10 <__gettext_free_exp> - 4089f1: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4089f6: 48 8b 78 10 mov 0x10(%rax),%rdi - 4089fa: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4089ff: e8 0c d2 ff ff callq 405c10 <__gettext_free_exp> - 408a04: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408a09: 48 8b 78 08 mov 0x8(%rax),%rdi - 408a0d: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408a12: e8 f9 d1 ff ff callq 405c10 <__gettext_free_exp> - 408a17: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408a1c: e9 51 fb ff ff jmpq 408572 - 408a21: 48 8b 78 18 mov 0x18(%rax),%rdi - 408a25: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408a2a: e8 e1 d1 ff ff callq 405c10 <__gettext_free_exp> - 408a2f: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408a34: 48 8b 78 10 mov 0x10(%rax),%rdi - 408a38: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408a3d: e8 ce d1 ff ff callq 405c10 <__gettext_free_exp> - 408a42: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408a47: 48 8b 78 08 mov 0x8(%rax),%rdi - 408a4b: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408a50: e8 bb d1 ff ff callq 405c10 <__gettext_free_exp> - 408a55: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408a5a: e9 7e ef ff ff jmpq 4079dd - 408a5f: 48 8b 78 18 mov 0x18(%rax),%rdi - 408a63: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408a68: e8 a3 d1 ff ff callq 405c10 <__gettext_free_exp> - 408a6d: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408a72: 48 8b 78 10 mov 0x10(%rax),%rdi - 408a76: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408a7b: e8 90 d1 ff ff callq 405c10 <__gettext_free_exp> - 408a80: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408a85: 48 8b 78 08 mov 0x8(%rax),%rdi - 408a89: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408a8e: e8 7d d1 ff ff callq 405c10 <__gettext_free_exp> - 408a93: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408a98: e9 c0 f0 ff ff jmpq 407b5d - 408a9d: 48 8b 78 18 mov 0x18(%rax),%rdi - 408aa1: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408aa6: e8 65 d1 ff ff callq 405c10 <__gettext_free_exp> - 408aab: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408ab0: 48 8b 78 10 mov 0x10(%rax),%rdi - 408ab4: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408ab9: e8 52 d1 ff ff callq 405c10 <__gettext_free_exp> - 408abe: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408ac3: 48 8b 78 08 mov 0x8(%rax),%rdi - 408ac7: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408acc: e8 3f d1 ff ff callq 405c10 <__gettext_free_exp> - 408ad1: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408ad6: e9 02 f0 ff ff jmpq 407add - 408adb: 48 8b 78 18 mov 0x18(%rax),%rdi - 408adf: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408ae4: e8 27 d1 ff ff callq 405c10 <__gettext_free_exp> - 408ae9: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408aee: 48 8b 78 10 mov 0x10(%rax),%rdi - 408af2: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408af7: e8 14 d1 ff ff callq 405c10 <__gettext_free_exp> - 408afc: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408b01: 48 8b 78 08 mov 0x8(%rax),%rdi - 408b05: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408b0a: e8 01 d1 ff ff callq 405c10 <__gettext_free_exp> - 408b0f: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408b14: e9 44 ef ff ff jmpq 407a5d - 408b19: 48 8b 78 18 mov 0x18(%rax),%rdi - 408b1d: 48 89 04 24 mov %rax,(%rsp) - 408b21: e8 ea d0 ff ff callq 405c10 <__gettext_free_exp> - 408b26: 48 8b 04 24 mov (%rsp),%rax - 408b2a: 48 8b 78 10 mov 0x10(%rax),%rdi - 408b2e: 48 89 04 24 mov %rax,(%rsp) - 408b32: e8 d9 d0 ff ff callq 405c10 <__gettext_free_exp> - 408b37: 48 8b 04 24 mov (%rsp),%rax - 408b3b: 48 8b 50 08 mov 0x8(%rax),%rdx - 408b3f: 48 85 d2 test %rdx,%rdx - 408b42: 0f 84 d9 f1 ff ff je 407d21 - 408b48: 8b 0a mov (%rdx),%ecx - 408b4a: 83 f9 02 cmp $0x2,%ecx - 408b4d: 0f 84 40 0a 00 00 je 409593 - 408b53: 83 f9 03 cmp $0x3,%ecx - 408b56: 0f 84 1c 0a 00 00 je 409578 - 408b5c: 83 f9 01 cmp $0x1,%ecx - 408b5f: 0f 84 49 0a 00 00 je 4095ae - 408b65: 48 89 d7 mov %rdx,%rdi - 408b68: 48 89 04 24 mov %rax,(%rsp) - 408b6c: e8 3f 52 01 00 callq 41ddb0 <__cfree> - 408b71: 48 8b 04 24 mov (%rsp),%rax - 408b75: e9 a7 f1 ff ff jmpq 407d21 - 408b7a: 48 8b 78 18 mov 0x18(%rax),%rdi - 408b7e: 48 89 04 24 mov %rax,(%rsp) - 408b82: e8 89 d0 ff ff callq 405c10 <__gettext_free_exp> - 408b87: 48 8b 04 24 mov (%rsp),%rax - 408b8b: 48 8b 78 10 mov 0x10(%rax),%rdi - 408b8f: 48 89 04 24 mov %rax,(%rsp) - 408b93: e8 78 d0 ff ff callq 405c10 <__gettext_free_exp> - 408b98: 48 8b 04 24 mov (%rsp),%rax - 408b9c: 48 8b 50 08 mov 0x8(%rax),%rdx - 408ba0: 48 85 d2 test %rdx,%rdx - 408ba3: 0f 84 98 f0 ff ff je 407c41 - 408ba9: 8b 0a mov (%rdx),%ecx - 408bab: 83 f9 02 cmp $0x2,%ecx - 408bae: 0f 84 b1 0a 00 00 je 409665 - 408bb4: 83 f9 03 cmp $0x3,%ecx - 408bb7: 0f 84 8d 0a 00 00 je 40964a - 408bbd: 83 f9 01 cmp $0x1,%ecx - 408bc0: 0f 84 ba 0a 00 00 je 409680 - 408bc6: 48 89 d7 mov %rdx,%rdi - 408bc9: 48 89 04 24 mov %rax,(%rsp) - 408bcd: e8 de 51 01 00 callq 41ddb0 <__cfree> - 408bd2: 48 8b 04 24 mov (%rsp),%rax - 408bd6: e9 66 f0 ff ff jmpq 407c41 - 408bdb: 48 8b 78 18 mov 0x18(%rax),%rdi - 408bdf: 48 89 04 24 mov %rax,(%rsp) - 408be3: e8 28 d0 ff ff callq 405c10 <__gettext_free_exp> - 408be8: 48 8b 04 24 mov (%rsp),%rax - 408bec: 48 8b 78 10 mov 0x10(%rax),%rdi - 408bf0: 48 89 04 24 mov %rax,(%rsp) - 408bf4: e8 17 d0 ff ff callq 405c10 <__gettext_free_exp> - 408bf9: 48 8b 04 24 mov (%rsp),%rax - 408bfd: 48 8b 50 08 mov 0x8(%rax),%rdx - 408c01: 48 85 d2 test %rdx,%rdx - 408c04: 0f 84 a7 f0 ff ff je 407cb1 - 408c0a: 8b 0a mov (%rdx),%ecx - 408c0c: 83 f9 02 cmp $0x2,%ecx - 408c0f: 0f 84 04 05 00 00 je 409119 - 408c15: 83 f9 03 cmp $0x3,%ecx - 408c18: 0f 84 e0 04 00 00 je 4090fe - 408c1e: 83 f9 01 cmp $0x1,%ecx - 408c21: 0f 84 0d 05 00 00 je 409134 - 408c27: 48 89 d7 mov %rdx,%rdi - 408c2a: 48 89 04 24 mov %rax,(%rsp) - 408c2e: e8 7d 51 01 00 callq 41ddb0 <__cfree> - 408c33: 48 8b 04 24 mov (%rsp),%rax - 408c37: e9 75 f0 ff ff jmpq 407cb1 - 408c3c: 48 8b 78 18 mov 0x18(%rax),%rdi - 408c40: 48 89 04 24 mov %rax,(%rsp) - 408c44: e8 c7 cf ff ff callq 405c10 <__gettext_free_exp> - 408c49: 48 8b 04 24 mov (%rsp),%rax - 408c4d: 48 8b 78 10 mov 0x10(%rax),%rdi - 408c51: 48 89 04 24 mov %rax,(%rsp) - 408c55: e8 b6 cf ff ff callq 405c10 <__gettext_free_exp> - 408c5a: 48 8b 04 24 mov (%rsp),%rax - 408c5e: 48 8b 50 08 mov 0x8(%rax),%rdx - 408c62: 48 85 d2 test %rdx,%rdx - 408c65: 0f 84 26 f1 ff ff je 407d91 - 408c6b: 8b 0a mov (%rdx),%ecx - 408c6d: 83 f9 02 cmp $0x2,%ecx - 408c70: 0f 84 cb 05 00 00 je 409241 - 408c76: 83 f9 03 cmp $0x3,%ecx - 408c79: 0f 84 a7 05 00 00 je 409226 - 408c7f: 83 f9 01 cmp $0x1,%ecx - 408c82: 0f 84 d4 05 00 00 je 40925c - 408c88: 48 89 d7 mov %rdx,%rdi - 408c8b: 48 89 04 24 mov %rax,(%rsp) - 408c8f: e8 1c 51 01 00 callq 41ddb0 <__cfree> - 408c94: 48 8b 04 24 mov (%rsp),%rax - 408c98: e9 f4 f0 ff ff jmpq 407d91 - 408c9d: 48 8b 78 18 mov 0x18(%rax),%rdi - 408ca1: 48 89 04 24 mov %rax,(%rsp) - 408ca5: e8 66 cf ff ff callq 405c10 <__gettext_free_exp> - 408caa: 48 8b 04 24 mov (%rsp),%rax - 408cae: 48 8b 78 10 mov 0x10(%rax),%rdi - 408cb2: 48 89 04 24 mov %rax,(%rsp) - 408cb6: e8 55 cf ff ff callq 405c10 <__gettext_free_exp> - 408cbb: 48 8b 04 24 mov (%rsp),%rax - 408cbf: 48 8b 50 08 mov 0x8(%rax),%rdx - 408cc3: 48 85 d2 test %rdx,%rdx - 408cc6: 0f 84 35 f1 ff ff je 407e01 - 408ccc: 8b 0a mov (%rdx),%ecx - 408cce: 83 f9 02 cmp $0x2,%ecx - 408cd1: 0f 84 92 06 00 00 je 409369 - 408cd7: 83 f9 03 cmp $0x3,%ecx - 408cda: 0f 84 6e 06 00 00 je 40934e - 408ce0: 83 f9 01 cmp $0x1,%ecx - 408ce3: 0f 84 9b 06 00 00 je 409384 - 408ce9: 48 89 d7 mov %rdx,%rdi - 408cec: 48 89 04 24 mov %rax,(%rsp) - 408cf0: e8 bb 50 01 00 callq 41ddb0 <__cfree> - 408cf5: 48 8b 04 24 mov (%rsp),%rax - 408cf9: e9 03 f1 ff ff jmpq 407e01 - 408cfe: 48 8b 78 18 mov 0x18(%rax),%rdi - 408d02: 48 89 04 24 mov %rax,(%rsp) - 408d06: e8 05 cf ff ff callq 405c10 <__gettext_free_exp> - 408d0b: 48 8b 04 24 mov (%rsp),%rax - 408d0f: 48 8b 78 10 mov 0x10(%rax),%rdi - 408d13: 48 89 04 24 mov %rax,(%rsp) - 408d17: e8 f4 ce ff ff callq 405c10 <__gettext_free_exp> - 408d1c: 48 8b 04 24 mov (%rsp),%rax - 408d20: 48 8b 50 08 mov 0x8(%rax),%rdx - 408d24: 48 85 d2 test %rdx,%rdx - 408d27: 0f 84 a4 ee ff ff je 407bd1 - 408d2d: 8b 0a mov (%rdx),%ecx - 408d2f: 83 f9 02 cmp $0x2,%ecx - 408d32: 0f 84 5f 05 00 00 je 409297 - 408d38: 83 f9 03 cmp $0x3,%ecx - 408d3b: 0f 84 3b 05 00 00 je 40927c - 408d41: 83 f9 01 cmp $0x1,%ecx - 408d44: 0f 84 68 05 00 00 je 4092b2 - 408d4a: 48 89 d7 mov %rdx,%rdi - 408d4d: 48 89 04 24 mov %rax,(%rsp) - 408d51: e8 5a 50 01 00 callq 41ddb0 <__cfree> - 408d56: 48 8b 04 24 mov (%rsp),%rax - 408d5a: e9 72 ee ff ff jmpq 407bd1 - 408d5f: 48 8b 78 18 mov 0x18(%rax),%rdi - 408d63: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408d68: e8 a3 ce ff ff callq 405c10 <__gettext_free_exp> - 408d6d: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408d72: 48 8b 78 10 mov 0x10(%rax),%rdi - 408d76: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408d7b: e8 90 ce ff ff callq 405c10 <__gettext_free_exp> - 408d80: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408d85: 48 8b 78 08 mov 0x8(%rax),%rdi - 408d89: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408d8e: e8 7d ce ff ff callq 405c10 <__gettext_free_exp> - 408d93: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408d98: e9 60 f4 ff ff jmpq 4081fd - 408d9d: 48 8b 78 18 mov 0x18(%rax),%rdi - 408da1: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408da6: e8 65 ce ff ff callq 405c10 <__gettext_free_exp> - 408dab: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408db0: 48 8b 78 10 mov 0x10(%rax),%rdi - 408db4: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408db9: e8 52 ce ff ff callq 405c10 <__gettext_free_exp> - 408dbe: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408dc3: 48 8b 78 08 mov 0x8(%rax),%rdi - 408dc7: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408dcc: e8 3f ce ff ff callq 405c10 <__gettext_free_exp> - 408dd1: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408dd6: e9 a2 f3 ff ff jmpq 40817d - 408ddb: 48 8b 78 18 mov 0x18(%rax),%rdi - 408ddf: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408de4: e8 27 ce ff ff callq 405c10 <__gettext_free_exp> - 408de9: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408dee: 48 8b 78 10 mov 0x10(%rax),%rdi - 408df2: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408df7: e8 14 ce ff ff callq 405c10 <__gettext_free_exp> - 408dfc: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408e01: 48 8b 78 08 mov 0x8(%rax),%rdi - 408e05: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408e0a: e8 01 ce ff ff callq 405c10 <__gettext_free_exp> - 408e0f: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408e14: e9 64 f4 ff ff jmpq 40827d - 408e19: 48 8b 78 18 mov 0x18(%rax),%rdi - 408e1d: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408e22: e8 e9 cd ff ff callq 405c10 <__gettext_free_exp> - 408e27: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408e2c: 48 8b 78 10 mov 0x10(%rax),%rdi - 408e30: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408e35: e8 d6 cd ff ff callq 405c10 <__gettext_free_exp> - 408e3a: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408e3f: 48 8b 78 08 mov 0x8(%rax),%rdi - 408e43: 48 89 44 24 08 mov %rax,0x8(%rsp) - 408e48: e8 c3 cd ff ff callq 405c10 <__gettext_free_exp> - 408e4d: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 408e52: e9 a6 f2 ff ff jmpq 4080fd - 408e57: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 408e5e: 00 00 - 408e60: 49 8b 47 18 mov 0x18(%r15),%rax - 408e64: 48 85 c0 test %rax,%rax - 408e67: 0f 84 2c df ff ff je 406d99 - 408e6d: 8b 10 mov (%rax),%edx - 408e6f: 83 fa 02 cmp $0x2,%edx - 408e72: 0f 84 f7 de ff ff je 406d6f - 408e78: 83 fa 03 cmp $0x3,%edx - 408e7b: 0f 84 dd de ff ff je 406d5e - 408e81: 83 fa 01 cmp $0x1,%edx - 408e84: 0f 85 07 df ff ff jne 406d91 - 408e8a: e9 f1 de ff ff jmpq 406d80 - 408e8f: 49 8b 7f 18 mov 0x18(%r15),%rdi - 408e93: e8 78 cd ff ff callq 405c10 <__gettext_free_exp> - 408e98: 49 8b 7f 10 mov 0x10(%r15),%rdi - 408e9c: e8 6f cd ff ff callq 405c10 <__gettext_free_exp> - 408ea1: 49 8b 47 08 mov 0x8(%r15),%rax - 408ea5: 48 85 c0 test %rax,%rax - 408ea8: 0f 84 89 df ff ff je 406e37 - 408eae: 8b 10 mov (%rax),%edx - 408eb0: 83 fa 02 cmp $0x2,%edx - 408eb3: 74 28 je 408edd - 408eb5: 83 fa 03 cmp $0x3,%edx - 408eb8: 74 12 je 408ecc - 408eba: 83 fa 01 cmp $0x1,%edx - 408ebd: 74 2f je 408eee - 408ebf: 48 89 c7 mov %rax,%rdi - 408ec2: e8 e9 4e 01 00 callq 41ddb0 <__cfree> - 408ec7: e9 6b df ff ff jmpq 406e37 - 408ecc: 48 8b 78 18 mov 0x18(%rax),%rdi - 408ed0: 48 89 04 24 mov %rax,(%rsp) - 408ed4: e8 37 cd ff ff callq 405c10 <__gettext_free_exp> - 408ed9: 48 8b 04 24 mov (%rsp),%rax - 408edd: 48 8b 78 10 mov 0x10(%rax),%rdi - 408ee1: 48 89 04 24 mov %rax,(%rsp) - 408ee5: e8 26 cd ff ff callq 405c10 <__gettext_free_exp> - 408eea: 48 8b 04 24 mov (%rsp),%rax - 408eee: 48 8b 78 08 mov 0x8(%rax),%rdi - 408ef2: 48 89 04 24 mov %rax,(%rsp) - 408ef6: e8 15 cd ff ff callq 405c10 <__gettext_free_exp> - 408efb: 48 8b 04 24 mov (%rsp),%rax - 408eff: eb be jmp 408ebf - 408f01: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 408f08: 49 8b 47 18 mov 0x18(%r15),%rax - 408f0c: 48 85 c0 test %rax,%rax - 408f0f: 0f 84 c4 df ff ff je 406ed9 - 408f15: 8b 10 mov (%rax),%edx - 408f17: 83 fa 02 cmp $0x2,%edx - 408f1a: 0f 84 8f df ff ff je 406eaf - 408f20: 83 fa 03 cmp $0x3,%edx - 408f23: 0f 84 75 df ff ff je 406e9e - 408f29: 83 fa 01 cmp $0x1,%edx - 408f2c: 0f 85 9f df ff ff jne 406ed1 - 408f32: e9 89 df ff ff jmpq 406ec0 - 408f37: 49 8b 7f 18 mov 0x18(%r15),%rdi - 408f3b: e8 d0 cc ff ff callq 405c10 <__gettext_free_exp> - 408f40: 49 8b 7f 10 mov 0x10(%r15),%rdi - 408f44: e8 c7 cc ff ff callq 405c10 <__gettext_free_exp> - 408f49: 49 8b 47 08 mov 0x8(%r15),%rax - 408f4d: 48 85 c0 test %rax,%rax - 408f50: 0f 84 a1 dd ff ff je 406cf7 - 408f56: 8b 10 mov (%rax),%edx - 408f58: 83 fa 02 cmp $0x2,%edx - 408f5b: 74 28 je 408f85 - 408f5d: 83 fa 03 cmp $0x3,%edx - 408f60: 74 12 je 408f74 - 408f62: 83 fa 01 cmp $0x1,%edx - 408f65: 74 2f je 408f96 - 408f67: 48 89 c7 mov %rax,%rdi - 408f6a: e8 41 4e 01 00 callq 41ddb0 <__cfree> - 408f6f: e9 83 dd ff ff jmpq 406cf7 - 408f74: 48 8b 78 18 mov 0x18(%rax),%rdi - 408f78: 48 89 04 24 mov %rax,(%rsp) - 408f7c: e8 8f cc ff ff callq 405c10 <__gettext_free_exp> - 408f81: 48 8b 04 24 mov (%rsp),%rax - 408f85: 48 8b 78 10 mov 0x10(%rax),%rdi - 408f89: 48 89 04 24 mov %rax,(%rsp) - 408f8d: e8 7e cc ff ff callq 405c10 <__gettext_free_exp> - 408f92: 48 8b 04 24 mov (%rsp),%rax - 408f96: 48 8b 78 08 mov 0x8(%rax),%rdi - 408f9a: 48 89 04 24 mov %rax,(%rsp) - 408f9e: e8 6d cc ff ff callq 405c10 <__gettext_free_exp> - 408fa3: 48 8b 04 24 mov (%rsp),%rax - 408fa7: eb be jmp 408f67 - 408fa9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 408fb0: 49 8b 47 18 mov 0x18(%r15),%rax - 408fb4: 48 85 c0 test %rax,%rax - 408fb7: 0f 84 d6 d4 ff ff je 406493 - 408fbd: 8b 10 mov (%rax),%edx - 408fbf: 83 fa 02 cmp $0x2,%edx - 408fc2: 0f 84 a1 d4 ff ff je 406469 - 408fc8: 83 fa 03 cmp $0x3,%edx - 408fcb: 0f 84 87 d4 ff ff je 406458 - 408fd1: 83 fa 01 cmp $0x1,%edx - 408fd4: 0f 85 b1 d4 ff ff jne 40648b - 408fda: e9 9b d4 ff ff jmpq 40647a - 408fdf: 49 8b 7f 18 mov 0x18(%r15),%rdi - 408fe3: e8 28 cc ff ff callq 405c10 <__gettext_free_exp> - 408fe8: 49 8b 7f 10 mov 0x10(%r15),%rdi - 408fec: e8 1f cc ff ff callq 405c10 <__gettext_free_exp> - 408ff1: 49 8b 47 08 mov 0x8(%r15),%rax - 408ff5: 48 85 c0 test %rax,%rax - 408ff8: 0f 84 f5 f2 ff ff je 4082f3 - 408ffe: 8b 10 mov (%rax),%edx - 409000: 83 fa 02 cmp $0x2,%edx - 409003: 74 28 je 40902d - 409005: 83 fa 03 cmp $0x3,%edx - 409008: 74 12 je 40901c - 40900a: 83 fa 01 cmp $0x1,%edx - 40900d: 74 2f je 40903e - 40900f: 48 89 c7 mov %rax,%rdi - 409012: e8 99 4d 01 00 callq 41ddb0 <__cfree> - 409017: e9 d7 f2 ff ff jmpq 4082f3 - 40901c: 48 8b 78 18 mov 0x18(%rax),%rdi - 409020: 48 89 04 24 mov %rax,(%rsp) - 409024: e8 e7 cb ff ff callq 405c10 <__gettext_free_exp> - 409029: 48 8b 04 24 mov (%rsp),%rax - 40902d: 48 8b 78 10 mov 0x10(%rax),%rdi - 409031: 48 89 04 24 mov %rax,(%rsp) - 409035: e8 d6 cb ff ff callq 405c10 <__gettext_free_exp> - 40903a: 48 8b 04 24 mov (%rsp),%rax - 40903e: 48 8b 78 08 mov 0x8(%rax),%rdi - 409042: 48 89 04 24 mov %rax,(%rsp) - 409046: e8 c5 cb ff ff callq 405c10 <__gettext_free_exp> - 40904b: 48 8b 04 24 mov (%rsp),%rax - 40904f: eb be jmp 40900f - 409051: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 409058: 4d 8b 7d 18 mov 0x18(%r13),%r15 - 40905c: 4d 85 ff test %r15,%r15 - 40905f: 0f 84 26 d5 ff ff je 40658b - 409065: 41 8b 07 mov (%r15),%eax - 409068: 83 f8 02 cmp $0x2,%eax - 40906b: 0f 84 00 d5 ff ff je 406571 - 409071: 83 f8 03 cmp $0x3,%eax - 409074: 0f 84 ee d4 ff ff je 406568 - 40907a: 83 f8 01 cmp $0x1,%eax - 40907d: 0f 85 00 d5 ff ff jne 406583 - 409083: e9 f2 d4 ff ff jmpq 40657a - 409088: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 40908f: 00 - 409090: 4d 8b 7d 18 mov 0x18(%r13),%r15 - 409094: 4d 85 ff test %r15,%r15 - 409097: 0f 84 fc d7 ff ff je 406899 - 40909d: 41 8b 07 mov (%r15),%eax - 4090a0: 83 f8 02 cmp $0x2,%eax - 4090a3: 0f 84 d6 d7 ff ff je 40687f - 4090a9: 83 f8 03 cmp $0x3,%eax - 4090ac: 0f 84 c4 d7 ff ff je 406876 - 4090b2: 83 f8 01 cmp $0x1,%eax - 4090b5: 0f 85 d6 d7 ff ff jne 406891 - 4090bb: e9 c8 d7 ff ff jmpq 406888 - 4090c0: 48 8b 78 18 mov 0x18(%rax),%rdi - 4090c4: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4090c9: e8 42 cb ff ff callq 405c10 <__gettext_free_exp> - 4090ce: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4090d3: 48 8b 78 10 mov 0x10(%rax),%rdi - 4090d7: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4090dc: e8 2f cb ff ff callq 405c10 <__gettext_free_exp> - 4090e1: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4090e6: 48 8b 78 08 mov 0x8(%rax),%rdi - 4090ea: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4090ef: e8 1c cb ff ff callq 405c10 <__gettext_free_exp> - 4090f4: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4090f9: e9 84 df ff ff jmpq 407082 - 4090fe: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 409102: 48 89 44 24 08 mov %rax,0x8(%rsp) - 409107: 48 89 14 24 mov %rdx,(%rsp) - 40910b: e8 00 cb ff ff callq 405c10 <__gettext_free_exp> - 409110: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 409115: 48 8b 14 24 mov (%rsp),%rdx - 409119: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 40911d: 48 89 44 24 08 mov %rax,0x8(%rsp) - 409122: 48 89 14 24 mov %rdx,(%rsp) - 409126: e8 e5 ca ff ff callq 405c10 <__gettext_free_exp> - 40912b: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 409130: 48 8b 14 24 mov (%rsp),%rdx - 409134: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 409138: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40913d: 48 89 14 24 mov %rdx,(%rsp) - 409141: e8 ca ca ff ff callq 405c10 <__gettext_free_exp> - 409146: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40914b: 48 8b 14 24 mov (%rsp),%rdx - 40914f: e9 d3 fa ff ff jmpq 408c27 - 409154: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 409158: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40915d: 48 89 14 24 mov %rdx,(%rsp) - 409161: e8 aa ca ff ff callq 405c10 <__gettext_free_exp> - 409166: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40916b: 48 8b 14 24 mov (%rsp),%rdx - 40916f: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 409173: 48 89 44 24 08 mov %rax,0x8(%rsp) - 409178: 48 89 14 24 mov %rdx,(%rsp) - 40917c: e8 8f ca ff ff callq 405c10 <__gettext_free_exp> - 409181: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 409186: 48 8b 14 24 mov (%rsp),%rdx - 40918a: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 40918e: 48 89 44 24 08 mov %rax,0x8(%rsp) - 409193: 48 89 14 24 mov %rdx,(%rsp) - 409197: e8 74 ca ff ff callq 405c10 <__gettext_free_exp> - 40919c: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4091a1: 48 8b 14 24 mov (%rsp),%rdx - 4091a5: e9 1b f3 ff ff jmpq 4084c5 - 4091aa: 48 8b 78 18 mov 0x18(%rax),%rdi - 4091ae: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4091b3: e8 58 ca ff ff callq 405c10 <__gettext_free_exp> - 4091b8: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4091bd: 48 8b 78 10 mov 0x10(%rax),%rdi - 4091c1: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4091c6: e8 45 ca ff ff callq 405c10 <__gettext_free_exp> - 4091cb: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4091d0: 48 8b 78 08 mov 0x8(%rax),%rdi - 4091d4: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4091d9: e8 32 ca ff ff callq 405c10 <__gettext_free_exp> - 4091de: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4091e3: e9 3f e9 ff ff jmpq 407b27 - 4091e8: 48 8b 78 18 mov 0x18(%rax),%rdi - 4091ec: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4091f1: e8 1a ca ff ff callq 405c10 <__gettext_free_exp> - 4091f6: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4091fb: 48 8b 78 10 mov 0x10(%rax),%rdi - 4091ff: 48 89 44 24 08 mov %rax,0x8(%rsp) - 409204: e8 07 ca ff ff callq 405c10 <__gettext_free_exp> - 409209: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40920e: 48 8b 78 08 mov 0x8(%rax),%rdi - 409212: 48 89 44 24 08 mov %rax,0x8(%rsp) - 409217: e8 f4 c9 ff ff callq 405c10 <__gettext_free_exp> - 40921c: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 409221: e9 81 e8 ff ff jmpq 407aa7 - 409226: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 40922a: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40922f: 48 89 14 24 mov %rdx,(%rsp) - 409233: e8 d8 c9 ff ff callq 405c10 <__gettext_free_exp> - 409238: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40923d: 48 8b 14 24 mov (%rsp),%rdx - 409241: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 409245: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40924a: 48 89 14 24 mov %rdx,(%rsp) - 40924e: e8 bd c9 ff ff callq 405c10 <__gettext_free_exp> - 409253: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 409258: 48 8b 14 24 mov (%rsp),%rdx - 40925c: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 409260: 48 89 44 24 08 mov %rax,0x8(%rsp) - 409265: 48 89 14 24 mov %rdx,(%rsp) - 409269: e8 a2 c9 ff ff callq 405c10 <__gettext_free_exp> - 40926e: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 409273: 48 8b 14 24 mov (%rsp),%rdx - 409277: e9 0c fa ff ff jmpq 408c88 - 40927c: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 409280: 48 89 44 24 08 mov %rax,0x8(%rsp) - 409285: 48 89 14 24 mov %rdx,(%rsp) - 409289: e8 82 c9 ff ff callq 405c10 <__gettext_free_exp> - 40928e: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 409293: 48 8b 14 24 mov (%rsp),%rdx - 409297: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 40929b: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4092a0: 48 89 14 24 mov %rdx,(%rsp) - 4092a4: e8 67 c9 ff ff callq 405c10 <__gettext_free_exp> - 4092a9: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4092ae: 48 8b 14 24 mov (%rsp),%rdx - 4092b2: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 4092b6: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4092bb: 48 89 14 24 mov %rdx,(%rsp) - 4092bf: e8 4c c9 ff ff callq 405c10 <__gettext_free_exp> - 4092c4: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4092c9: 48 8b 14 24 mov (%rsp),%rdx - 4092cd: e9 78 fa ff ff jmpq 408d4a - 4092d2: 48 8b 78 18 mov 0x18(%rax),%rdi - 4092d6: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4092db: e8 30 c9 ff ff callq 405c10 <__gettext_free_exp> - 4092e0: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4092e5: 48 8b 78 10 mov 0x10(%rax),%rdi - 4092e9: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4092ee: e8 1d c9 ff ff callq 405c10 <__gettext_free_exp> - 4092f3: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4092f8: 48 8b 78 08 mov 0x8(%rax),%rdi - 4092fc: 48 89 44 24 08 mov %rax,0x8(%rsp) - 409301: e8 0a c9 ff ff callq 405c10 <__gettext_free_exp> - 409306: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40930b: e9 3a df ff ff jmpq 40724a - 409310: 48 8b 78 18 mov 0x18(%rax),%rdi - 409314: 48 89 44 24 08 mov %rax,0x8(%rsp) - 409319: e8 f2 c8 ff ff callq 405c10 <__gettext_free_exp> - 40931e: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 409323: 48 8b 78 10 mov 0x10(%rax),%rdi - 409327: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40932c: e8 df c8 ff ff callq 405c10 <__gettext_free_exp> - 409331: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 409336: 48 8b 78 08 mov 0x8(%rax),%rdi - 40933a: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40933f: e8 cc c8 ff ff callq 405c10 <__gettext_free_exp> - 409344: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 409349: e9 1c de ff ff jmpq 40716a - 40934e: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 409352: 48 89 44 24 08 mov %rax,0x8(%rsp) - 409357: 48 89 14 24 mov %rdx,(%rsp) - 40935b: e8 b0 c8 ff ff callq 405c10 <__gettext_free_exp> - 409360: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 409365: 48 8b 14 24 mov (%rsp),%rdx - 409369: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 40936d: 48 89 44 24 08 mov %rax,0x8(%rsp) - 409372: 48 89 14 24 mov %rdx,(%rsp) - 409376: e8 95 c8 ff ff callq 405c10 <__gettext_free_exp> - 40937b: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 409380: 48 8b 14 24 mov (%rsp),%rdx - 409384: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 409388: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40938d: 48 89 14 24 mov %rdx,(%rsp) - 409391: e8 7a c8 ff ff callq 405c10 <__gettext_free_exp> - 409396: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40939b: 48 8b 14 24 mov (%rsp),%rdx - 40939f: e9 45 f9 ff ff jmpq 408ce9 - 4093a4: 48 8b 78 18 mov 0x18(%rax),%rdi - 4093a8: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4093ad: e8 5e c8 ff ff callq 405c10 <__gettext_free_exp> - 4093b2: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4093b7: 48 8b 78 10 mov 0x10(%rax),%rdi - 4093bb: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4093c0: e8 4b c8 ff ff callq 405c10 <__gettext_free_exp> - 4093c5: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4093ca: 48 8b 78 08 mov 0x8(%rax),%rdi - 4093ce: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4093d3: e8 38 c8 ff ff callq 405c10 <__gettext_free_exp> - 4093d8: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4093dd: e9 c6 f1 ff ff jmpq 4085a8 - 4093e2: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 4093e6: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4093eb: 48 89 14 24 mov %rdx,(%rsp) - 4093ef: e8 1c c8 ff ff callq 405c10 <__gettext_free_exp> - 4093f4: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4093f9: 48 8b 14 24 mov (%rsp),%rdx - 4093fd: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 409401: 48 89 44 24 08 mov %rax,0x8(%rsp) - 409406: 48 89 14 24 mov %rdx,(%rsp) - 40940a: e8 01 c8 ff ff callq 405c10 <__gettext_free_exp> - 40940f: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 409414: 48 8b 14 24 mov (%rsp),%rdx - 409418: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 40941c: 48 89 44 24 08 mov %rax,0x8(%rsp) - 409421: 48 89 14 24 mov %rdx,(%rsp) - 409425: e8 e6 c7 ff ff callq 405c10 <__gettext_free_exp> - 40942a: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40942f: 48 8b 14 24 mov (%rsp),%rdx - 409433: e9 ee f0 ff ff jmpq 408526 - 409438: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 40943c: 48 89 44 24 08 mov %rax,0x8(%rsp) - 409441: 48 89 14 24 mov %rdx,(%rsp) - 409445: e8 c6 c7 ff ff callq 405c10 <__gettext_free_exp> - 40944a: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40944f: 48 8b 14 24 mov (%rsp),%rdx - 409453: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 409457: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40945c: 48 89 14 24 mov %rdx,(%rsp) - 409460: e8 ab c7 ff ff callq 405c10 <__gettext_free_exp> - 409465: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40946a: 48 8b 14 24 mov (%rsp),%rdx - 40946e: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 409472: 48 89 44 24 08 mov %rax,0x8(%rsp) - 409477: 48 89 14 24 mov %rdx,(%rsp) - 40947b: e8 90 c7 ff ff callq 405c10 <__gettext_free_exp> - 409480: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 409485: 48 8b 14 24 mov (%rsp),%rdx - 409489: e9 14 ef ff ff jmpq 4083a2 - 40948e: 48 8b 78 18 mov 0x18(%rax),%rdi - 409492: 48 89 44 24 08 mov %rax,0x8(%rsp) - 409497: e8 74 c7 ff ff callq 405c10 <__gettext_free_exp> - 40949c: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4094a1: 48 8b 78 10 mov 0x10(%rax),%rdi - 4094a5: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4094aa: e8 61 c7 ff ff callq 405c10 <__gettext_free_exp> - 4094af: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4094b4: 48 8b 78 08 mov 0x8(%rax),%rdi - 4094b8: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4094bd: e8 4e c7 ff ff callq 405c10 <__gettext_free_exp> - 4094c2: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4094c7: e9 db e4 ff ff jmpq 4079a7 - 4094cc: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 4094d0: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4094d5: 48 89 14 24 mov %rdx,(%rsp) - 4094d9: e8 32 c7 ff ff callq 405c10 <__gettext_free_exp> - 4094de: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4094e3: 48 8b 14 24 mov (%rsp),%rdx - 4094e7: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 4094eb: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4094f0: 48 89 14 24 mov %rdx,(%rsp) - 4094f4: e8 17 c7 ff ff callq 405c10 <__gettext_free_exp> - 4094f9: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4094fe: 48 8b 14 24 mov (%rsp),%rdx - 409502: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 409506: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40950b: 48 89 14 24 mov %rdx,(%rsp) - 40950f: e8 fc c6 ff ff callq 405c10 <__gettext_free_exp> - 409514: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 409519: 48 8b 14 24 mov (%rsp),%rdx - 40951d: e9 42 ef ff ff jmpq 408464 - 409522: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 409526: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40952b: 48 89 14 24 mov %rdx,(%rsp) - 40952f: e8 dc c6 ff ff callq 405c10 <__gettext_free_exp> - 409534: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 409539: 48 8b 14 24 mov (%rsp),%rdx - 40953d: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 409541: 48 89 44 24 08 mov %rax,0x8(%rsp) - 409546: 48 89 14 24 mov %rdx,(%rsp) - 40954a: e8 c1 c6 ff ff callq 405c10 <__gettext_free_exp> - 40954f: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 409554: 48 8b 14 24 mov (%rsp),%rdx - 409558: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 40955c: 48 89 44 24 08 mov %rax,0x8(%rsp) - 409561: 48 89 14 24 mov %rdx,(%rsp) - 409565: e8 a6 c6 ff ff callq 405c10 <__gettext_free_exp> - 40956a: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40956f: 48 8b 14 24 mov (%rsp),%rdx - 409573: e9 8b ee ff ff jmpq 408403 - 409578: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 40957c: 48 89 44 24 08 mov %rax,0x8(%rsp) - 409581: 48 89 14 24 mov %rdx,(%rsp) - 409585: e8 86 c6 ff ff callq 405c10 <__gettext_free_exp> - 40958a: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40958f: 48 8b 14 24 mov (%rsp),%rdx - 409593: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 409597: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40959c: 48 89 14 24 mov %rdx,(%rsp) - 4095a0: e8 6b c6 ff ff callq 405c10 <__gettext_free_exp> - 4095a5: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4095aa: 48 8b 14 24 mov (%rsp),%rdx - 4095ae: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 4095b2: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4095b7: 48 89 14 24 mov %rdx,(%rsp) - 4095bb: e8 50 c6 ff ff callq 405c10 <__gettext_free_exp> - 4095c0: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4095c5: 48 8b 14 24 mov (%rsp),%rdx - 4095c9: e9 97 f5 ff ff jmpq 408b65 - 4095ce: 48 8b 78 18 mov 0x18(%rax),%rdi - 4095d2: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4095d7: e8 34 c6 ff ff callq 405c10 <__gettext_free_exp> - 4095dc: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4095e1: 48 8b 78 10 mov 0x10(%rax),%rdi - 4095e5: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4095ea: e8 21 c6 ff ff callq 405c10 <__gettext_free_exp> - 4095ef: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4095f4: 48 8b 78 08 mov 0x8(%rax),%rdi - 4095f8: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4095fd: e8 0e c6 ff ff callq 405c10 <__gettext_free_exp> - 409602: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 409607: e9 1e dd ff ff jmpq 40732a - 40960c: 48 8b 78 18 mov 0x18(%rax),%rdi - 409610: 48 89 44 24 08 mov %rax,0x8(%rsp) - 409615: e8 f6 c5 ff ff callq 405c10 <__gettext_free_exp> - 40961a: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40961f: 48 8b 78 10 mov 0x10(%rax),%rdi - 409623: 48 89 44 24 08 mov %rax,0x8(%rsp) - 409628: e8 e3 c5 ff ff callq 405c10 <__gettext_free_exp> - 40962d: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 409632: 48 8b 78 08 mov 0x8(%rax),%rdi - 409636: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40963b: e8 d0 c5 ff ff callq 405c10 <__gettext_free_exp> - 409640: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 409645: e9 dd e3 ff ff jmpq 407a27 - 40964a: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 40964e: 48 89 44 24 08 mov %rax,0x8(%rsp) - 409653: 48 89 14 24 mov %rdx,(%rsp) - 409657: e8 b4 c5 ff ff callq 405c10 <__gettext_free_exp> - 40965c: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 409661: 48 8b 14 24 mov (%rsp),%rdx - 409665: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 409669: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40966e: 48 89 14 24 mov %rdx,(%rsp) - 409672: e8 99 c5 ff ff callq 405c10 <__gettext_free_exp> - 409677: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40967c: 48 8b 14 24 mov (%rsp),%rdx - 409680: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 409684: 48 89 44 24 08 mov %rax,0x8(%rsp) - 409689: 48 89 14 24 mov %rdx,(%rsp) - 40968d: e8 7e c5 ff ff callq 405c10 <__gettext_free_exp> - 409692: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 409697: 48 8b 14 24 mov (%rsp),%rdx - 40969b: e9 26 f5 ff ff jmpq 408bc6 - 4096a0: 48 8b 04 24 mov (%rsp),%rax - 4096a4: 48 8b 40 18 mov 0x18(%rax),%rax - 4096a8: 48 85 c0 test %rax,%rax - 4096ab: 0f 84 06 d4 ff ff je 406ab7 - 4096b1: 8b 10 mov (%rax),%edx - 4096b3: 83 fa 02 cmp $0x2,%edx - 4096b6: 0f 84 cd d3 ff ff je 406a89 - 4096bc: 83 fa 03 cmp $0x3,%edx - 4096bf: 0f 84 b1 d3 ff ff je 406a76 - 4096c5: 83 fa 01 cmp $0x1,%edx - 4096c8: 0f 85 e1 d3 ff ff jne 406aaf - 4096ce: e9 c9 d3 ff ff jmpq 406a9c - 4096d3: 48 8b 78 18 mov 0x18(%rax),%rdi - 4096d7: 48 89 04 24 mov %rax,(%rsp) - 4096db: e8 30 c5 ff ff callq 405c10 <__gettext_free_exp> - 4096e0: 48 8b 04 24 mov (%rsp),%rax - 4096e4: 48 8b 78 10 mov 0x10(%rax),%rdi - 4096e8: 48 89 04 24 mov %rax,(%rsp) - 4096ec: e8 1f c5 ff ff callq 405c10 <__gettext_free_exp> - 4096f1: 48 8b 04 24 mov (%rsp),%rax - 4096f5: 48 8b 78 08 mov 0x8(%rax),%rdi - 4096f9: 48 89 04 24 mov %rax,(%rsp) - 4096fd: e8 0e c5 ff ff callq 405c10 <__gettext_free_exp> - 409702: 48 8b 04 24 mov (%rsp),%rax - 409706: e9 04 e5 ff ff jmpq 407c0f - 40970b: 48 8b 78 18 mov 0x18(%rax),%rdi - 40970f: 48 89 04 24 mov %rax,(%rsp) - 409713: e8 f8 c4 ff ff callq 405c10 <__gettext_free_exp> - 409718: 48 8b 04 24 mov (%rsp),%rax - 40971c: 48 8b 78 10 mov 0x10(%rax),%rdi - 409720: 48 89 04 24 mov %rax,(%rsp) - 409724: e8 e7 c4 ff ff callq 405c10 <__gettext_free_exp> - 409729: 48 8b 04 24 mov (%rsp),%rax - 40972d: 48 8b 78 08 mov 0x8(%rax),%rdi - 409731: 48 89 04 24 mov %rax,(%rsp) - 409735: e8 d6 c4 ff ff callq 405c10 <__gettext_free_exp> - 40973a: 48 8b 04 24 mov (%rsp),%rax - 40973e: e9 40 ef ff ff jmpq 408683 - 409743: 48 8b 78 18 mov 0x18(%rax),%rdi - 409747: 48 89 04 24 mov %rax,(%rsp) - 40974b: e8 c0 c4 ff ff callq 405c10 <__gettext_free_exp> - 409750: 48 8b 04 24 mov (%rsp),%rax - 409754: 48 8b 78 10 mov 0x10(%rax),%rdi - 409758: 48 89 04 24 mov %rax,(%rsp) - 40975c: e8 af c4 ff ff callq 405c10 <__gettext_free_exp> - 409761: 48 8b 04 24 mov (%rsp),%rax - 409765: 48 8b 78 08 mov 0x8(%rax),%rdi - 409769: 48 89 04 24 mov %rax,(%rsp) - 40976d: e8 9e c4 ff ff callq 405c10 <__gettext_free_exp> - 409772: 48 8b 04 24 mov (%rsp),%rax - 409776: e9 54 e6 ff ff jmpq 407dcf - 40977b: 48 8b 78 18 mov 0x18(%rax),%rdi - 40977f: 48 89 04 24 mov %rax,(%rsp) - 409783: e8 88 c4 ff ff callq 405c10 <__gettext_free_exp> - 409788: 48 8b 04 24 mov (%rsp),%rax - 40978c: 48 8b 78 10 mov 0x10(%rax),%rdi - 409790: 48 89 04 24 mov %rax,(%rsp) - 409794: e8 77 c4 ff ff callq 405c10 <__gettext_free_exp> - 409799: 48 8b 04 24 mov (%rsp),%rax - 40979d: 48 8b 78 08 mov 0x8(%rax),%rdi - 4097a1: 48 89 04 24 mov %rax,(%rsp) - 4097a5: e8 66 c4 ff ff callq 405c10 <__gettext_free_exp> - 4097aa: 48 8b 04 24 mov (%rsp),%rax - 4097ae: e9 ac e5 ff ff jmpq 407d5f - 4097b3: 48 8b 78 18 mov 0x18(%rax),%rdi - 4097b7: 48 89 04 24 mov %rax,(%rsp) - 4097bb: e8 50 c4 ff ff callq 405c10 <__gettext_free_exp> - 4097c0: 48 8b 04 24 mov (%rsp),%rax - 4097c4: 48 8b 78 10 mov 0x10(%rax),%rdi - 4097c8: 48 89 04 24 mov %rax,(%rsp) - 4097cc: e8 3f c4 ff ff callq 405c10 <__gettext_free_exp> - 4097d1: 48 8b 04 24 mov (%rsp),%rax - 4097d5: 48 8b 50 08 mov 0x8(%rax),%rdx - 4097d9: 48 85 d2 test %rdx,%rdx - 4097dc: 0f 84 9c dc ff ff je 40747e - 4097e2: 8b 0a mov (%rdx),%ecx - 4097e4: 83 f9 02 cmp $0x2,%ecx - 4097e7: 74 3a je 409823 - 4097e9: 83 f9 03 cmp $0x3,%ecx - 4097ec: 74 1a je 409808 - 4097ee: 83 f9 01 cmp $0x1,%ecx - 4097f1: 74 4b je 40983e - 4097f3: 48 89 d7 mov %rdx,%rdi - 4097f6: 48 89 04 24 mov %rax,(%rsp) - 4097fa: e8 b1 45 01 00 callq 41ddb0 <__cfree> - 4097ff: 48 8b 04 24 mov (%rsp),%rax - 409803: e9 76 dc ff ff jmpq 40747e - 409808: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 40980c: 48 89 44 24 08 mov %rax,0x8(%rsp) - 409811: 48 89 14 24 mov %rdx,(%rsp) - 409815: e8 f6 c3 ff ff callq 405c10 <__gettext_free_exp> - 40981a: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40981f: 48 8b 14 24 mov (%rsp),%rdx - 409823: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 409827: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40982c: 48 89 14 24 mov %rdx,(%rsp) - 409830: e8 db c3 ff ff callq 405c10 <__gettext_free_exp> - 409835: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40983a: 48 8b 14 24 mov (%rsp),%rdx - 40983e: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 409842: 48 89 44 24 08 mov %rax,0x8(%rsp) - 409847: 48 89 14 24 mov %rdx,(%rsp) - 40984b: e8 c0 c3 ff ff callq 405c10 <__gettext_free_exp> - 409850: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 409855: 48 8b 14 24 mov (%rsp),%rdx - 409859: eb 98 jmp 4097f3 - 40985b: 48 8b 78 18 mov 0x18(%rax),%rdi - 40985f: 48 89 04 24 mov %rax,(%rsp) - 409863: e8 a8 c3 ff ff callq 405c10 <__gettext_free_exp> - 409868: 48 8b 04 24 mov (%rsp),%rax - 40986c: 48 8b 78 10 mov 0x10(%rax),%rdi - 409870: 48 89 04 24 mov %rax,(%rsp) - 409874: e8 97 c3 ff ff callq 405c10 <__gettext_free_exp> - 409879: 48 8b 04 24 mov (%rsp),%rax - 40987d: 48 8b 50 08 mov 0x8(%rax),%rdx - 409881: 48 85 d2 test %rdx,%rdx - 409884: 0f 84 ec dd ff ff je 407676 - 40988a: 8b 0a mov (%rdx),%ecx - 40988c: 83 f9 02 cmp $0x2,%ecx - 40988f: 74 3a je 4098cb - 409891: 83 f9 03 cmp $0x3,%ecx - 409894: 74 1a je 4098b0 - 409896: 83 f9 01 cmp $0x1,%ecx - 409899: 74 4b je 4098e6 - 40989b: 48 89 d7 mov %rdx,%rdi - 40989e: 48 89 04 24 mov %rax,(%rsp) - 4098a2: e8 09 45 01 00 callq 41ddb0 <__cfree> - 4098a7: 48 8b 04 24 mov (%rsp),%rax - 4098ab: e9 c6 dd ff ff jmpq 407676 - 4098b0: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 4098b4: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4098b9: 48 89 14 24 mov %rdx,(%rsp) - 4098bd: e8 4e c3 ff ff callq 405c10 <__gettext_free_exp> - 4098c2: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4098c7: 48 8b 14 24 mov (%rsp),%rdx - 4098cb: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 4098cf: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4098d4: 48 89 14 24 mov %rdx,(%rsp) - 4098d8: e8 33 c3 ff ff callq 405c10 <__gettext_free_exp> - 4098dd: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4098e2: 48 8b 14 24 mov (%rsp),%rdx - 4098e6: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 4098ea: 48 89 44 24 08 mov %rax,0x8(%rsp) - 4098ef: 48 89 14 24 mov %rdx,(%rsp) - 4098f3: e8 18 c3 ff ff callq 405c10 <__gettext_free_exp> - 4098f8: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4098fd: 48 8b 14 24 mov (%rsp),%rdx - 409901: eb 98 jmp 40989b - 409903: 48 8b 78 18 mov 0x18(%rax),%rdi - 409907: 48 89 04 24 mov %rax,(%rsp) - 40990b: e8 00 c3 ff ff callq 405c10 <__gettext_free_exp> - 409910: 48 8b 04 24 mov (%rsp),%rax - 409914: 48 8b 78 10 mov 0x10(%rax),%rdi - 409918: 48 89 04 24 mov %rax,(%rsp) - 40991c: e8 ef c2 ff ff callq 405c10 <__gettext_free_exp> - 409921: 48 8b 04 24 mov (%rsp),%rax - 409925: 48 8b 78 08 mov 0x8(%rax),%rdi - 409929: 48 89 04 24 mov %rax,(%rsp) - 40992d: e8 de c2 ff ff callq 405c10 <__gettext_free_exp> - 409932: 48 8b 04 24 mov (%rsp),%rax - 409936: e9 b6 ec ff ff jmpq 4085f1 - 40993b: 48 8b 78 18 mov 0x18(%rax),%rdi - 40993f: 48 89 04 24 mov %rax,(%rsp) - 409943: e8 c8 c2 ff ff callq 405c10 <__gettext_free_exp> - 409948: 48 8b 04 24 mov (%rsp),%rax - 40994c: 48 8b 78 10 mov 0x10(%rax),%rdi - 409950: 48 89 04 24 mov %rax,(%rsp) - 409954: e8 b7 c2 ff ff callq 405c10 <__gettext_free_exp> - 409959: 48 8b 04 24 mov (%rsp),%rax - 40995d: 48 8b 78 08 mov 0x8(%rax),%rdi - 409961: 48 89 04 24 mov %rax,(%rsp) - 409965: e8 a6 c2 ff ff callq 405c10 <__gettext_free_exp> - 40996a: 48 8b 04 24 mov (%rsp),%rax - 40996e: e9 2c e2 ff ff jmpq 407b9f - 409973: 48 8b 78 18 mov 0x18(%rax),%rdi - 409977: 48 89 04 24 mov %rax,(%rsp) - 40997b: e8 90 c2 ff ff callq 405c10 <__gettext_free_exp> - 409980: 48 8b 04 24 mov (%rsp),%rax - 409984: 48 8b 78 10 mov 0x10(%rax),%rdi - 409988: 48 89 04 24 mov %rax,(%rsp) - 40998c: e8 7f c2 ff ff callq 405c10 <__gettext_free_exp> - 409991: 48 8b 04 24 mov (%rsp),%rax - 409995: 48 8b 78 08 mov 0x8(%rax),%rdi - 409999: 48 89 04 24 mov %rax,(%rsp) - 40999d: e8 6e c2 ff ff callq 405c10 <__gettext_free_exp> - 4099a2: 48 8b 04 24 mov (%rsp),%rax - 4099a6: e9 8f ec ff ff jmpq 40863a - 4099ab: 48 8b 78 18 mov 0x18(%rax),%rdi - 4099af: 48 89 04 24 mov %rax,(%rsp) - 4099b3: e8 58 c2 ff ff callq 405c10 <__gettext_free_exp> - 4099b8: 48 8b 04 24 mov (%rsp),%rax - 4099bc: 48 8b 78 10 mov 0x10(%rax),%rdi - 4099c0: 48 89 04 24 mov %rax,(%rsp) - 4099c4: e8 47 c2 ff ff callq 405c10 <__gettext_free_exp> - 4099c9: 48 8b 04 24 mov (%rsp),%rax - 4099cd: 48 8b 78 08 mov 0x8(%rax),%rdi - 4099d1: 48 89 04 24 mov %rax,(%rsp) - 4099d5: e8 36 c2 ff ff callq 405c10 <__gettext_free_exp> - 4099da: 48 8b 04 24 mov (%rsp),%rax - 4099de: e9 9c e2 ff ff jmpq 407c7f - 4099e3: 48 8b 78 18 mov 0x18(%rax),%rdi - 4099e7: 48 89 04 24 mov %rax,(%rsp) - 4099eb: e8 20 c2 ff ff callq 405c10 <__gettext_free_exp> - 4099f0: 48 8b 04 24 mov (%rsp),%rax - 4099f4: 48 8b 78 10 mov 0x10(%rax),%rdi - 4099f8: 48 89 04 24 mov %rax,(%rsp) - 4099fc: e8 0f c2 ff ff callq 405c10 <__gettext_free_exp> - 409a01: 48 8b 04 24 mov (%rsp),%rax - 409a05: 48 8b 78 08 mov 0x8(%rax),%rdi - 409a09: 48 89 04 24 mov %rax,(%rsp) - 409a0d: e8 fe c1 ff ff callq 405c10 <__gettext_free_exp> - 409a12: 48 8b 04 24 mov (%rsp),%rax - 409a16: e9 d4 e2 ff ff jmpq 407cef - 409a1b: 48 8b 78 18 mov 0x18(%rax),%rdi - 409a1f: 48 89 04 24 mov %rax,(%rsp) - 409a23: e8 e8 c1 ff ff callq 405c10 <__gettext_free_exp> - 409a28: 48 8b 04 24 mov (%rsp),%rax - 409a2c: 48 8b 78 10 mov 0x10(%rax),%rdi - 409a30: 48 89 04 24 mov %rax,(%rsp) - 409a34: e8 d7 c1 ff ff callq 405c10 <__gettext_free_exp> - 409a39: 48 8b 04 24 mov (%rsp),%rax - 409a3d: 48 8b 78 08 mov 0x8(%rax),%rdi - 409a41: 48 89 04 24 mov %rax,(%rsp) - 409a45: e8 c6 c1 ff ff callq 405c10 <__gettext_free_exp> - 409a4a: 48 8b 04 24 mov (%rsp),%rax - 409a4e: e9 43 dd ff ff jmpq 407796 - 409a53: 0f 1f 00 nopl (%rax) - 409a56: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 409a5d: 00 00 00 - -0000000000409a60 : - 409a60: 41 57 push %r15 - 409a62: 41 56 push %r14 - 409a64: 41 55 push %r13 - 409a66: 41 54 push %r12 - 409a68: 4c 63 e7 movslq %edi,%r12 - 409a6b: 55 push %rbp - 409a6c: 53 push %rbx - 409a6d: 41 8d 5c 24 ff lea -0x1(%r12),%ebx - 409a72: 48 83 ec 18 sub $0x18,%rsp - 409a76: 85 db test %ebx,%ebx - 409a78: 0f 88 85 37 00 00 js 40d203 - 409a7e: 4c 63 eb movslq %ebx,%r13 - 409a81: 49 89 d7 mov %rdx,%r15 - 409a84: 89 dd mov %ebx,%ebp - 409a86: 4a 83 3c ea 00 cmpq $0x0,(%rdx,%r13,8) - 409a8b: 4a 8d 04 ed 00 00 00 lea 0x0(,%r13,8),%rax - 409a92: 00 - 409a93: 48 8d 4c 02 f8 lea -0x8(%rdx,%rax,1),%rcx - 409a98: 89 d8 mov %ebx,%eax - 409a9a: 75 0f jne 409aab - 409a9c: eb 72 jmp 409b10 - 409a9e: 66 90 xchg %ax,%ax - 409aa0: 48 83 e9 08 sub $0x8,%rcx - 409aa4: 48 83 79 08 00 cmpq $0x0,0x8(%rcx) - 409aa9: 74 65 je 409b10 - 409aab: 83 e8 01 sub $0x1,%eax - 409aae: 83 f8 ff cmp $0xffffffff,%eax - 409ab1: 75 ed jne 409aa0 - 409ab3: bf 20 00 00 00 mov $0x20,%edi - 409ab8: 89 34 24 mov %esi,(%rsp) - 409abb: e8 50 3f 01 00 callq 41da10 <__libc_malloc> - 409ac0: 48 85 c0 test %rax,%rax - 409ac3: 49 89 c6 mov %rax,%r14 - 409ac6: 8b 34 24 mov (%rsp),%esi - 409ac9: 74 45 je 409b10 - 409acb: 41 89 76 04 mov %esi,0x4(%r14) - 409acf: 4a 8d 34 e5 00 00 00 lea 0x0(,%r12,8),%rsi - 409ad6: 00 - 409ad7: 89 db mov %ebx,%ebx - 409ad9: 48 8d 14 dd 08 00 00 lea 0x8(,%rbx,8),%rdx - 409ae0: 00 - 409ae1: 45 89 26 mov %r12d,(%r14) - 409ae4: 48 8d 7e 08 lea 0x8(%rsi),%rdi - 409ae8: 48 29 d6 sub %rdx,%rsi - 409aeb: 48 29 d7 sub %rdx,%rdi - 409aee: 4c 01 fe add %r15,%rsi - 409af1: 4c 01 f7 add %r14,%rdi - 409af4: e8 27 25 02 00 callq 42c020 - 409af9: 48 83 c4 18 add $0x18,%rsp - 409afd: 4c 89 f0 mov %r14,%rax - 409b00: 5b pop %rbx - 409b01: 5d pop %rbp - 409b02: 41 5c pop %r12 - 409b04: 41 5d pop %r13 - 409b06: 41 5e pop %r14 - 409b08: 41 5f pop %r15 - 409b0a: c3 retq - 409b0b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 409b10: 4f 8d 24 ef lea (%r15,%r13,8),%r12 - 409b14: eb 30 jmp 409b46 - 409b16: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 409b1d: 00 00 00 - 409b20: 83 f8 03 cmp $0x3,%eax - 409b23: 0f 84 f7 02 00 00 je 409e20 - 409b29: 83 f8 01 cmp $0x1,%eax - 409b2c: 74 58 je 409b86 - 409b2e: 48 89 df mov %rbx,%rdi - 409b31: e8 7a 42 01 00 callq 41ddb0 <__cfree> - 409b36: 83 ed 01 sub $0x1,%ebp - 409b39: 49 83 ec 08 sub $0x8,%r12 - 409b3d: 83 fd ff cmp $0xffffffff,%ebp - 409b40: 0f 84 8a 0a 00 00 je 40a5d0 - 409b46: 49 8b 1c 24 mov (%r12),%rbx - 409b4a: 48 85 db test %rbx,%rbx - 409b4d: 74 e7 je 409b36 - 409b4f: 8b 03 mov (%rbx),%eax - 409b51: 83 f8 02 cmp $0x2,%eax - 409b54: 75 ca jne 409b20 - 409b56: 4c 8b 6b 10 mov 0x10(%rbx),%r13 - 409b5a: 4d 85 ed test %r13,%r13 - 409b5d: 74 27 je 409b86 - 409b5f: 41 8b 45 00 mov 0x0(%r13),%eax - 409b63: 83 f8 02 cmp $0x2,%eax - 409b66: 0f 84 35 09 00 00 je 40a4a1 - 409b6c: 83 f8 03 cmp $0x3,%eax - 409b6f: 0f 84 1b 0a 00 00 je 40a590 - 409b75: 83 f8 01 cmp $0x1,%eax - 409b78: 0f 84 63 02 00 00 je 409de1 - 409b7e: 4c 89 ef mov %r13,%rdi - 409b81: e8 2a 42 01 00 callq 41ddb0 <__cfree> - 409b86: 4c 8b 6b 08 mov 0x8(%rbx),%r13 - 409b8a: 4d 85 ed test %r13,%r13 - 409b8d: 74 9f je 409b2e - 409b8f: 41 8b 45 00 mov 0x0(%r13),%eax - 409b93: 83 f8 02 cmp $0x2,%eax - 409b96: 74 47 je 409bdf - 409b98: 83 f8 03 cmp $0x3,%eax - 409b9b: 74 13 je 409bb0 - 409b9d: 83 f8 01 cmp $0x1,%eax - 409ba0: 74 6c je 409c0e - 409ba2: 4c 89 ef mov %r13,%rdi - 409ba5: e8 06 42 01 00 callq 41ddb0 <__cfree> - 409baa: eb 82 jmp 409b2e - 409bac: 0f 1f 40 00 nopl 0x0(%rax) - 409bb0: 4d 8b 75 18 mov 0x18(%r13),%r14 - 409bb4: 4d 85 f6 test %r14,%r14 - 409bb7: 74 26 je 409bdf - 409bb9: 41 8b 06 mov (%r14),%eax - 409bbc: 83 f8 02 cmp $0x2,%eax - 409bbf: 0f 84 ca 0d 00 00 je 40a98f - 409bc5: 83 f8 03 cmp $0x3,%eax - 409bc8: 0f 84 92 0d 00 00 je 40a960 - 409bce: 83 f8 01 cmp $0x1,%eax - 409bd1: 0f 84 e7 0d 00 00 je 40a9be - 409bd7: 4c 89 f7 mov %r14,%rdi - 409bda: e8 d1 41 01 00 callq 41ddb0 <__cfree> - 409bdf: 4d 8b 75 10 mov 0x10(%r13),%r14 - 409be3: 4d 85 f6 test %r14,%r14 - 409be6: 74 26 je 409c0e - 409be8: 41 8b 06 mov (%r14),%eax - 409beb: 83 f8 02 cmp $0x2,%eax - 409bee: 0f 84 8b 04 00 00 je 40a07f - 409bf4: 83 f8 03 cmp $0x3,%eax - 409bf7: 0f 84 53 04 00 00 je 40a050 - 409bfd: 83 f8 01 cmp $0x1,%eax - 409c00: 0f 84 a8 04 00 00 je 40a0ae - 409c06: 4c 89 f7 mov %r14,%rdi - 409c09: e8 a2 41 01 00 callq 41ddb0 <__cfree> - 409c0e: 4d 8b 75 08 mov 0x8(%r13),%r14 - 409c12: 4d 85 f6 test %r14,%r14 - 409c15: 74 8b je 409ba2 - 409c17: 41 8b 06 mov (%r14),%eax - 409c1a: 83 f8 02 cmp $0x2,%eax - 409c1d: 0f 84 2f 06 00 00 je 40a252 - 409c23: 83 f8 03 cmp $0x3,%eax - 409c26: 0f 84 b4 08 00 00 je 40a4e0 - 409c2c: 83 f8 01 cmp $0x1,%eax - 409c2f: 0f 84 c8 00 00 00 je 409cfd - 409c35: 4c 89 f7 mov %r14,%rdi - 409c38: e8 73 41 01 00 callq 41ddb0 <__cfree> - 409c3d: e9 60 ff ff ff jmpq 409ba2 - 409c42: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 409c48: 48 8b 04 24 mov (%rsp),%rax - 409c4c: 48 8b 78 18 mov 0x18(%rax),%rdi - 409c50: e8 bb bf ff ff callq 405c10 <__gettext_free_exp> - 409c55: 48 8b 04 24 mov (%rsp),%rax - 409c59: 48 8b 40 10 mov 0x10(%rax),%rax - 409c5d: 48 85 c0 test %rax,%rax - 409c60: 74 25 je 409c87 - 409c62: 8b 10 mov (%rax),%edx - 409c64: 83 fa 02 cmp $0x2,%edx - 409c67: 0f 84 93 22 00 00 je 40bf00 - 409c6d: 83 fa 03 cmp $0x3,%edx - 409c70: 0f 84 77 22 00 00 je 40beed - 409c76: 83 fa 01 cmp $0x1,%edx - 409c79: 0f 84 94 22 00 00 je 40bf13 - 409c7f: 48 89 c7 mov %rax,%rdi - 409c82: e8 29 41 01 00 callq 41ddb0 <__cfree> - 409c87: 48 8b 04 24 mov (%rsp),%rax - 409c8b: 48 8b 40 08 mov 0x8(%rax),%rax - 409c8f: 48 85 c0 test %rax,%rax - 409c92: 74 25 je 409cb9 - 409c94: 8b 10 mov (%rax),%edx - 409c96: 83 fa 02 cmp $0x2,%edx - 409c99: 0f 84 6c 19 00 00 je 40b60b - 409c9f: 83 fa 03 cmp $0x3,%edx - 409ca2: 0f 84 50 19 00 00 je 40b5f8 - 409ca8: 83 fa 01 cmp $0x1,%edx - 409cab: 0f 84 6d 19 00 00 je 40b61e - 409cb1: 48 89 c7 mov %rax,%rdi - 409cb4: e8 f7 40 01 00 callq 41ddb0 <__cfree> - 409cb9: 48 8b 3c 24 mov (%rsp),%rdi - 409cbd: e8 ee 40 01 00 callq 41ddb0 <__cfree> - 409cc2: 49 8b 47 08 mov 0x8(%r15),%rax - 409cc6: 48 85 c0 test %rax,%rax - 409cc9: 48 89 04 24 mov %rax,(%rsp) - 409ccd: 74 26 je 409cf5 - 409ccf: 8b 00 mov (%rax),%eax - 409cd1: 83 f8 02 cmp $0x2,%eax - 409cd4: 0f 84 98 10 00 00 je 40ad72 - 409cda: 83 f8 03 cmp $0x3,%eax - 409cdd: 0f 84 5d 10 00 00 je 40ad40 - 409ce3: 83 f8 01 cmp $0x1,%eax - 409ce6: 0f 84 b8 10 00 00 je 40ada4 - 409cec: 48 8b 3c 24 mov (%rsp),%rdi - 409cf0: e8 bb 40 01 00 callq 41ddb0 <__cfree> - 409cf5: 4c 89 ff mov %r15,%rdi - 409cf8: e8 b3 40 01 00 callq 41ddb0 <__cfree> - 409cfd: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 409d01: 4d 85 ff test %r15,%r15 - 409d04: 0f 84 2b ff ff ff je 409c35 - 409d0a: 41 8b 07 mov (%r15),%eax - 409d0d: 83 f8 02 cmp $0x2,%eax - 409d10: 0f 84 45 02 00 00 je 409f5b - 409d16: 83 f8 03 cmp $0x3,%eax - 409d19: 0f 84 09 02 00 00 je 409f28 - 409d1f: 83 f8 01 cmp $0x1,%eax - 409d22: 0f 84 66 02 00 00 je 409f8e - 409d28: 4c 89 ff mov %r15,%rdi - 409d2b: e8 80 40 01 00 callq 41ddb0 <__cfree> - 409d30: e9 00 ff ff ff jmpq 409c35 - 409d35: 0f 1f 00 nopl (%rax) - 409d38: 49 8b 7f 18 mov 0x18(%r15),%rdi - 409d3c: e8 cf be ff ff callq 405c10 <__gettext_free_exp> - 409d41: 49 8b 47 10 mov 0x10(%r15),%rax - 409d45: 48 85 c0 test %rax,%rax - 409d48: 74 25 je 409d6f - 409d4a: 8b 10 mov (%rax),%edx - 409d4c: 83 fa 02 cmp $0x2,%edx - 409d4f: 0f 84 63 22 00 00 je 40bfb8 - 409d55: 83 fa 03 cmp $0x3,%edx - 409d58: 0f 84 49 22 00 00 je 40bfa7 - 409d5e: 83 fa 01 cmp $0x1,%edx - 409d61: 0f 84 62 22 00 00 je 40bfc9 - 409d67: 48 89 c7 mov %rax,%rdi - 409d6a: e8 41 40 01 00 callq 41ddb0 <__cfree> - 409d6f: 49 8b 47 08 mov 0x8(%r15),%rax - 409d73: 48 85 c0 test %rax,%rax - 409d76: 48 89 04 24 mov %rax,(%rsp) - 409d7a: 74 26 je 409da2 - 409d7c: 8b 00 mov (%rax),%eax - 409d7e: 83 f8 02 cmp $0x2,%eax - 409d81: 0f 84 64 1b 00 00 je 40b8eb - 409d87: 83 f8 03 cmp $0x3,%eax - 409d8a: 0f 84 4e 1b 00 00 je 40b8de - 409d90: 83 f8 01 cmp $0x1,%eax - 409d93: 0f 84 84 1b 00 00 je 40b91d - 409d99: 48 8b 3c 24 mov (%rsp),%rdi - 409d9d: e8 0e 40 01 00 callq 41ddb0 <__cfree> - 409da2: 4c 89 ff mov %r15,%rdi - 409da5: e8 06 40 01 00 callq 41ddb0 <__cfree> - 409daa: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 409dae: 4d 85 ff test %r15,%r15 - 409db1: 74 26 je 409dd9 - 409db3: 41 8b 07 mov (%r15),%eax - 409db6: 83 f8 02 cmp $0x2,%eax - 409db9: 0f 84 cf 12 00 00 je 40b08e - 409dbf: 83 f8 03 cmp $0x3,%eax - 409dc2: 0f 84 98 12 00 00 je 40b060 - 409dc8: 83 f8 01 cmp $0x1,%eax - 409dcb: 0f 84 f0 12 00 00 je 40b0c1 - 409dd1: 4c 89 ff mov %r15,%rdi - 409dd4: e8 d7 3f 01 00 callq 41ddb0 <__cfree> - 409dd9: 4c 89 f7 mov %r14,%rdi - 409ddc: e8 cf 3f 01 00 callq 41ddb0 <__cfree> - 409de1: 4d 8b 75 08 mov 0x8(%r13),%r14 - 409de5: 4d 85 f6 test %r14,%r14 - 409de8: 0f 84 90 fd ff ff je 409b7e - 409dee: 41 8b 06 mov (%r14),%eax - 409df1: 83 f8 02 cmp $0x2,%eax - 409df4: 0f 84 c5 04 00 00 je 40a2bf - 409dfa: 83 f8 03 cmp $0x3,%eax - 409dfd: 0f 84 8d 04 00 00 je 40a290 - 409e03: 83 f8 01 cmp $0x1,%eax - 409e06: 0f 84 e2 04 00 00 je 40a2ee - 409e0c: 4c 89 f7 mov %r14,%rdi - 409e0f: e8 9c 3f 01 00 callq 41ddb0 <__cfree> - 409e14: e9 65 fd ff ff jmpq 409b7e - 409e19: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 409e20: 4c 8b 6b 18 mov 0x18(%rbx),%r13 - 409e24: 4d 85 ed test %r13,%r13 - 409e27: 0f 84 29 fd ff ff je 409b56 - 409e2d: 41 8b 45 00 mov 0x0(%r13),%eax - 409e31: 83 f8 02 cmp $0x2,%eax - 409e34: 0f 84 15 07 00 00 je 40a54f - 409e3a: 83 f8 03 cmp $0x3,%eax - 409e3d: 0f 84 dd 06 00 00 je 40a520 - 409e43: 83 f8 01 cmp $0x1,%eax - 409e46: 0f 84 96 00 00 00 je 409ee2 - 409e4c: 4c 89 ef mov %r13,%rdi - 409e4f: e8 5c 3f 01 00 callq 41ddb0 <__cfree> - 409e54: e9 fd fc ff ff jmpq 409b56 - 409e59: 49 8b 7f 18 mov 0x18(%r15),%rdi - 409e5d: e8 ae bd ff ff callq 405c10 <__gettext_free_exp> - 409e62: 49 8b 7f 10 mov 0x10(%r15),%rdi - 409e66: e8 a5 bd ff ff callq 405c10 <__gettext_free_exp> - 409e6b: 49 8b 7f 08 mov 0x8(%r15),%rdi - 409e6f: e8 9c bd ff ff callq 405c10 <__gettext_free_exp> - 409e74: 4c 89 ff mov %r15,%rdi - 409e77: e8 34 3f 01 00 callq 41ddb0 <__cfree> - 409e7c: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 409e80: 4d 85 ff test %r15,%r15 - 409e83: 74 26 je 409eab - 409e85: 41 8b 07 mov (%r15),%eax - 409e88: 83 f8 02 cmp $0x2,%eax - 409e8b: 0f 84 19 1f 00 00 je 40bdaa - 409e91: 83 f8 03 cmp $0x3,%eax - 409e94: 0f 84 07 1f 00 00 je 40bda1 - 409e9a: 83 f8 01 cmp $0x1,%eax - 409e9d: 0f 84 10 1f 00 00 je 40bdb3 - 409ea3: 4c 89 ff mov %r15,%rdi - 409ea6: e8 05 3f 01 00 callq 41ddb0 <__cfree> - 409eab: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 409eaf: 4d 85 ff test %r15,%r15 - 409eb2: 74 26 je 409eda - 409eb4: 41 8b 07 mov (%r15),%eax - 409eb7: 83 f8 02 cmp $0x2,%eax - 409eba: 0f 84 16 15 00 00 je 40b3d6 - 409ec0: 83 f8 03 cmp $0x3,%eax - 409ec3: 0f 84 04 15 00 00 je 40b3cd - 409ec9: 83 f8 01 cmp $0x1,%eax - 409ecc: 0f 84 32 15 00 00 je 40b404 - 409ed2: 4c 89 ff mov %r15,%rdi - 409ed5: e8 d6 3e 01 00 callq 41ddb0 <__cfree> - 409eda: 4c 89 f7 mov %r14,%rdi - 409edd: e8 ce 3e 01 00 callq 41ddb0 <__cfree> - 409ee2: 4d 8b 75 08 mov 0x8(%r13),%r14 - 409ee6: 4d 85 f6 test %r14,%r14 - 409ee9: 0f 84 5d ff ff ff je 409e4c - 409eef: 41 8b 06 mov (%r14),%eax - 409ef2: 83 f8 02 cmp $0x2,%eax - 409ef5: 0f 84 54 09 00 00 je 40a84f - 409efb: 83 f8 03 cmp $0x3,%eax - 409efe: 0f 84 1c 09 00 00 je 40a820 - 409f04: 83 f8 01 cmp $0x1,%eax - 409f07: 0f 84 71 09 00 00 je 40a87e - 409f0d: 4c 89 f7 mov %r14,%rdi - 409f10: e8 9b 3e 01 00 callq 41ddb0 <__cfree> - 409f15: 4c 89 ef mov %r13,%rdi - 409f18: e8 93 3e 01 00 callq 41ddb0 <__cfree> - 409f1d: e9 34 fc ff ff jmpq 409b56 - 409f22: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 409f28: 49 8b 47 18 mov 0x18(%r15),%rax - 409f2c: 48 85 c0 test %rax,%rax - 409f2f: 48 89 04 24 mov %rax,(%rsp) - 409f33: 74 26 je 409f5b - 409f35: 8b 00 mov (%rax),%eax - 409f37: 83 f8 02 cmp $0x2,%eax - 409f3a: 0f 84 44 12 00 00 je 40b184 - 409f40: 83 f8 03 cmp $0x3,%eax - 409f43: 0f 84 2e 12 00 00 je 40b177 - 409f49: 83 f8 01 cmp $0x1,%eax - 409f4c: 0f 84 64 12 00 00 je 40b1b6 - 409f52: 48 8b 3c 24 mov (%rsp),%rdi - 409f56: e8 55 3e 01 00 callq 41ddb0 <__cfree> - 409f5b: 49 8b 47 10 mov 0x10(%r15),%rax - 409f5f: 48 85 c0 test %rax,%rax - 409f62: 48 89 04 24 mov %rax,(%rsp) - 409f66: 74 26 je 409f8e - 409f68: 8b 00 mov (%rax),%eax - 409f6a: 83 f8 02 cmp $0x2,%eax - 409f6d: 0f 84 3f 0c 00 00 je 40abb2 - 409f73: 83 f8 03 cmp $0x3,%eax - 409f76: 0f 84 04 0c 00 00 je 40ab80 - 409f7c: 83 f8 01 cmp $0x1,%eax - 409f7f: 0f 84 5f 0c 00 00 je 40abe4 - 409f85: 48 8b 3c 24 mov (%rsp),%rdi - 409f89: e8 22 3e 01 00 callq 41ddb0 <__cfree> - 409f8e: 49 8b 47 08 mov 0x8(%r15),%rax - 409f92: 48 85 c0 test %rax,%rax - 409f95: 0f 84 8d fd ff ff je 409d28 - 409f9b: 8b 10 mov (%rax),%edx - 409f9d: 83 fa 02 cmp $0x2,%edx - 409fa0: 0f 84 78 06 00 00 je 40a61e - 409fa6: 83 fa 03 cmp $0x3,%edx - 409fa9: 0f 84 39 06 00 00 je 40a5e8 - 409faf: 83 fa 01 cmp $0x1,%edx - 409fb2: 74 75 je 40a029 - 409fb4: 48 89 c7 mov %rax,%rdi - 409fb7: e8 f4 3d 01 00 callq 41ddb0 <__cfree> - 409fbc: e9 67 fd ff ff jmpq 409d28 - 409fc1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 409fc8: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 409fcc: 48 89 44 24 08 mov %rax,0x8(%rsp) - 409fd1: 48 89 14 24 mov %rdx,(%rsp) - 409fd5: e8 36 bc ff ff callq 405c10 <__gettext_free_exp> - 409fda: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 409fdf: 48 8b 14 24 mov (%rsp),%rdx - 409fe3: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 409fe7: 48 89 44 24 08 mov %rax,0x8(%rsp) - 409fec: 48 89 14 24 mov %rdx,(%rsp) - 409ff0: e8 1b bc ff ff callq 405c10 <__gettext_free_exp> - 409ff5: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 409ffa: 48 8b 14 24 mov (%rsp),%rdx - 409ffe: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 40a002: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40a007: 48 89 14 24 mov %rdx,(%rsp) - 40a00b: e8 00 bc ff ff callq 405c10 <__gettext_free_exp> - 40a010: 48 8b 14 24 mov (%rsp),%rdx - 40a014: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40a019: 48 89 d7 mov %rdx,%rdi - 40a01c: 48 89 04 24 mov %rax,(%rsp) - 40a020: e8 8b 3d 01 00 callq 41ddb0 <__cfree> - 40a025: 48 8b 04 24 mov (%rsp),%rax - 40a029: 48 8b 78 08 mov 0x8(%rax),%rdi - 40a02d: 48 89 04 24 mov %rax,(%rsp) - 40a031: e8 da bb ff ff callq 405c10 <__gettext_free_exp> - 40a036: 48 8b 04 24 mov (%rsp),%rax - 40a03a: 48 89 c7 mov %rax,%rdi - 40a03d: e8 6e 3d 01 00 callq 41ddb0 <__cfree> - 40a042: e9 e1 fc ff ff jmpq 409d28 - 40a047: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 40a04e: 00 00 - 40a050: 4d 8b 7e 18 mov 0x18(%r14),%r15 - 40a054: 4d 85 ff test %r15,%r15 - 40a057: 74 26 je 40a07f - 40a059: 41 8b 07 mov (%r15),%eax - 40a05c: 83 f8 02 cmp $0x2,%eax - 40a05f: 0f 84 29 15 00 00 je 40b58e - 40a065: 83 f8 03 cmp $0x3,%eax - 40a068: 0f 84 17 15 00 00 je 40b585 - 40a06e: 83 f8 01 cmp $0x1,%eax - 40a071: 0f 84 45 15 00 00 je 40b5bc - 40a077: 4c 89 ff mov %r15,%rdi - 40a07a: e8 31 3d 01 00 callq 41ddb0 <__cfree> - 40a07f: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 40a083: 4d 85 ff test %r15,%r15 - 40a086: 74 26 je 40a0ae - 40a088: 41 8b 07 mov (%r15),%eax - 40a08b: 83 f8 02 cmp $0x2,%eax - 40a08e: 0f 84 ba 0d 00 00 je 40ae4e - 40a094: 83 f8 03 cmp $0x3,%eax - 40a097: 0f 84 83 0d 00 00 je 40ae20 - 40a09d: 83 f8 01 cmp $0x1,%eax - 40a0a0: 0f 84 db 0d 00 00 je 40ae81 - 40a0a6: 4c 89 ff mov %r15,%rdi - 40a0a9: e8 02 3d 01 00 callq 41ddb0 <__cfree> - 40a0ae: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 40a0b2: 4d 85 ff test %r15,%r15 - 40a0b5: 0f 84 4b fb ff ff je 409c06 - 40a0bb: 41 8b 07 mov (%r15),%eax - 40a0be: 83 f8 02 cmp $0x2,%eax - 40a0c1: 0f 84 a7 06 00 00 je 40a76e - 40a0c7: 83 f8 03 cmp $0x3,%eax - 40a0ca: 0f 84 70 06 00 00 je 40a740 - 40a0d0: 83 f8 01 cmp $0x1,%eax - 40a0d3: 0f 84 91 00 00 00 je 40a16a - 40a0d9: 4c 89 ff mov %r15,%rdi - 40a0dc: e8 cf 3c 01 00 callq 41ddb0 <__cfree> - 40a0e1: e9 20 fb ff ff jmpq 409c06 - 40a0e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 40a0ed: 00 00 00 - 40a0f0: 48 8b 04 24 mov (%rsp),%rax - 40a0f4: 48 8b 78 18 mov 0x18(%rax),%rdi - 40a0f8: e8 13 bb ff ff callq 405c10 <__gettext_free_exp> - 40a0fd: 48 8b 04 24 mov (%rsp),%rax - 40a101: 48 8b 40 10 mov 0x10(%rax),%rax - 40a105: 48 85 c0 test %rax,%rax - 40a108: 74 25 je 40a12f - 40a10a: 8b 10 mov (%rax),%edx - 40a10c: 83 fa 02 cmp $0x2,%edx - 40a10f: 0f 84 6f 1d 00 00 je 40be84 - 40a115: 83 fa 03 cmp $0x3,%edx - 40a118: 0f 84 53 1d 00 00 je 40be71 - 40a11e: 83 fa 01 cmp $0x1,%edx - 40a121: 0f 84 70 1d 00 00 je 40be97 - 40a127: 48 89 c7 mov %rax,%rdi - 40a12a: e8 81 3c 01 00 callq 41ddb0 <__cfree> - 40a12f: 48 8b 04 24 mov (%rsp),%rax - 40a133: 48 8b 40 08 mov 0x8(%rax),%rax - 40a137: 48 85 c0 test %rax,%rax - 40a13a: 74 25 je 40a161 - 40a13c: 8b 10 mov (%rax),%edx - 40a13e: 83 fa 02 cmp $0x2,%edx - 40a141: 0f 84 76 16 00 00 je 40b7bd - 40a147: 83 fa 03 cmp $0x3,%edx - 40a14a: 0f 84 5a 16 00 00 je 40b7aa - 40a150: 83 fa 01 cmp $0x1,%edx - 40a153: 0f 84 77 16 00 00 je 40b7d0 - 40a159: 48 89 c7 mov %rax,%rdi - 40a15c: e8 4f 3c 01 00 callq 41ddb0 <__cfree> - 40a161: 48 8b 3c 24 mov (%rsp),%rdi - 40a165: e8 46 3c 01 00 callq 41ddb0 <__cfree> - 40a16a: 49 8b 47 08 mov 0x8(%r15),%rax - 40a16e: 48 85 c0 test %rax,%rax - 40a171: 48 89 04 24 mov %rax,(%rsp) - 40a175: 0f 84 5e ff ff ff je 40a0d9 - 40a17b: 8b 00 mov (%rax),%eax - 40a17d: 83 f8 02 cmp $0x2,%eax - 40a180: 0f 84 4c 09 00 00 je 40aad2 - 40a186: 83 f8 03 cmp $0x3,%eax - 40a189: 0f 84 11 09 00 00 je 40aaa0 - 40a18f: 83 f8 01 cmp $0x1,%eax - 40a192: 0f 84 6c 09 00 00 je 40ab04 - 40a198: 48 8b 3c 24 mov (%rsp),%rdi - 40a19c: e8 0f 3c 01 00 callq 41ddb0 <__cfree> - 40a1a1: 4c 89 ff mov %r15,%rdi - 40a1a4: e8 07 3c 01 00 callq 41ddb0 <__cfree> - 40a1a9: e9 58 fa ff ff jmpq 409c06 - 40a1ae: 48 8b 78 18 mov 0x18(%rax),%rdi - 40a1b2: 48 89 04 24 mov %rax,(%rsp) - 40a1b6: e8 55 ba ff ff callq 405c10 <__gettext_free_exp> - 40a1bb: 48 8b 04 24 mov (%rsp),%rax - 40a1bf: 48 8b 78 10 mov 0x10(%rax),%rdi - 40a1c3: 48 89 04 24 mov %rax,(%rsp) - 40a1c7: e8 44 ba ff ff callq 405c10 <__gettext_free_exp> - 40a1cc: 48 8b 04 24 mov (%rsp),%rax - 40a1d0: 48 8b 78 08 mov 0x8(%rax),%rdi - 40a1d4: 48 89 04 24 mov %rax,(%rsp) - 40a1d8: e8 33 ba ff ff callq 405c10 <__gettext_free_exp> - 40a1dd: 48 8b 04 24 mov (%rsp),%rax - 40a1e1: 48 89 c7 mov %rax,%rdi - 40a1e4: e8 c7 3b 01 00 callq 41ddb0 <__cfree> - 40a1e9: 49 8b 47 10 mov 0x10(%r15),%rax - 40a1ed: 48 85 c0 test %rax,%rax - 40a1f0: 74 25 je 40a217 - 40a1f2: 8b 10 mov (%rax),%edx - 40a1f4: 83 fa 02 cmp $0x2,%edx - 40a1f7: 0f 84 26 19 00 00 je 40bb23 - 40a1fd: 83 fa 03 cmp $0x3,%edx - 40a200: 0f 84 0c 19 00 00 je 40bb12 - 40a206: 83 fa 01 cmp $0x1,%edx - 40a209: 0f 84 25 19 00 00 je 40bb34 - 40a20f: 48 89 c7 mov %rax,%rdi - 40a212: e8 99 3b 01 00 callq 41ddb0 <__cfree> - 40a217: 49 8b 47 08 mov 0x8(%r15),%rax - 40a21b: 48 85 c0 test %rax,%rax - 40a21e: 48 89 04 24 mov %rax,(%rsp) - 40a222: 74 26 je 40a24a - 40a224: 8b 00 mov (%rax),%eax - 40a226: 83 f8 02 cmp $0x2,%eax - 40a229: 0f 84 cf 0f 00 00 je 40b1fe - 40a22f: 83 f8 03 cmp $0x3,%eax - 40a232: 0f 84 b9 0f 00 00 je 40b1f1 - 40a238: 83 f8 01 cmp $0x1,%eax - 40a23b: 0f 84 ef 0f 00 00 je 40b230 - 40a241: 48 8b 3c 24 mov (%rsp),%rdi - 40a245: e8 66 3b 01 00 callq 41ddb0 <__cfree> - 40a24a: 4c 89 ff mov %r15,%rdi - 40a24d: e8 5e 3b 01 00 callq 41ddb0 <__cfree> - 40a252: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 40a256: 4d 85 ff test %r15,%r15 - 40a259: 0f 84 9e fa ff ff je 409cfd - 40a25f: 41 8b 07 mov (%r15),%eax - 40a262: 83 f8 02 cmp $0x2,%eax - 40a265: 0f 84 23 04 00 00 je 40a68e - 40a26b: 83 f8 03 cmp $0x3,%eax - 40a26e: 0f 84 ec 03 00 00 je 40a660 - 40a274: 83 f8 01 cmp $0x1,%eax - 40a277: 0f 84 45 fa ff ff je 409cc2 - 40a27d: 4c 89 ff mov %r15,%rdi - 40a280: e8 2b 3b 01 00 callq 41ddb0 <__cfree> - 40a285: e9 73 fa ff ff jmpq 409cfd - 40a28a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 40a290: 4d 8b 7e 18 mov 0x18(%r14),%r15 - 40a294: 4d 85 ff test %r15,%r15 - 40a297: 74 26 je 40a2bf - 40a299: 41 8b 07 mov (%r15),%eax - 40a29c: 83 f8 02 cmp $0x2,%eax - 40a29f: 0f 84 0d 12 00 00 je 40b4b2 - 40a2a5: 83 f8 03 cmp $0x3,%eax - 40a2a8: 0f 84 fb 11 00 00 je 40b4a9 - 40a2ae: 83 f8 01 cmp $0x1,%eax - 40a2b1: 0f 84 29 12 00 00 je 40b4e0 - 40a2b7: 4c 89 ff mov %r15,%rdi - 40a2ba: e8 f1 3a 01 00 callq 41ddb0 <__cfree> - 40a2bf: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 40a2c3: 4d 85 ff test %r15,%r15 - 40a2c6: 74 26 je 40a2ee - 40a2c8: 41 8b 07 mov (%r15),%eax - 40a2cb: 83 f8 02 cmp $0x2,%eax - 40a2ce: 0f 84 9a 0c 00 00 je 40af6e - 40a2d4: 83 f8 03 cmp $0x3,%eax - 40a2d7: 0f 84 63 0c 00 00 je 40af40 - 40a2dd: 83 f8 01 cmp $0x1,%eax - 40a2e0: 0f 84 bb 0c 00 00 je 40afa1 - 40a2e6: 4c 89 ff mov %r15,%rdi - 40a2e9: e8 c2 3a 01 00 callq 41ddb0 <__cfree> - 40a2ee: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 40a2f2: 4d 85 ff test %r15,%r15 - 40a2f5: 0f 84 11 fb ff ff je 409e0c - 40a2fb: 41 8b 07 mov (%r15),%eax - 40a2fe: 83 f8 02 cmp $0x2,%eax - 40a301: 0f 84 f7 03 00 00 je 40a6fe - 40a307: 83 f8 03 cmp $0x3,%eax - 40a30a: 0f 84 c0 03 00 00 je 40a6d0 - 40a310: 83 f8 01 cmp $0x1,%eax - 40a313: 0f 84 bb 00 00 00 je 40a3d4 - 40a319: 4c 89 ff mov %r15,%rdi - 40a31c: e8 8f 3a 01 00 callq 41ddb0 <__cfree> - 40a321: e9 e6 fa ff ff jmpq 409e0c - 40a326: 48 8b 78 18 mov 0x18(%rax),%rdi - 40a32a: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40a32f: e8 dc b8 ff ff callq 405c10 <__gettext_free_exp> - 40a334: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40a339: 48 8b 78 10 mov 0x10(%rax),%rdi - 40a33d: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40a342: e8 c9 b8 ff ff callq 405c10 <__gettext_free_exp> - 40a347: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40a34c: 48 8b 78 08 mov 0x8(%rax),%rdi - 40a350: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40a355: e8 b6 b8 ff ff callq 405c10 <__gettext_free_exp> - 40a35a: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40a35f: 48 89 c7 mov %rax,%rdi - 40a362: e8 49 3a 01 00 callq 41ddb0 <__cfree> - 40a367: 48 8b 04 24 mov (%rsp),%rax - 40a36b: 48 8b 40 10 mov 0x10(%rax),%rax - 40a36f: 48 85 c0 test %rax,%rax - 40a372: 74 25 je 40a399 - 40a374: 8b 10 mov (%rax),%edx - 40a376: 83 fa 02 cmp $0x2,%edx - 40a379: 0f 84 c7 1a 00 00 je 40be46 - 40a37f: 83 fa 03 cmp $0x3,%edx - 40a382: 0f 84 ab 1a 00 00 je 40be33 - 40a388: 83 fa 01 cmp $0x1,%edx - 40a38b: 0f 84 c8 1a 00 00 je 40be59 - 40a391: 48 89 c7 mov %rax,%rdi - 40a394: e8 17 3a 01 00 callq 41ddb0 <__cfree> - 40a399: 48 8b 04 24 mov (%rsp),%rax - 40a39d: 48 8b 40 08 mov 0x8(%rax),%rax - 40a3a1: 48 85 c0 test %rax,%rax - 40a3a4: 74 25 je 40a3cb - 40a3a6: 8b 10 mov (%rax),%edx - 40a3a8: 83 fa 02 cmp $0x2,%edx - 40a3ab: 0f 84 4a 14 00 00 je 40b7fb - 40a3b1: 83 fa 03 cmp $0x3,%edx - 40a3b4: 0f 84 2e 14 00 00 je 40b7e8 - 40a3ba: 83 fa 01 cmp $0x1,%edx - 40a3bd: 0f 84 4b 14 00 00 je 40b80e - 40a3c3: 48 89 c7 mov %rax,%rdi - 40a3c6: e8 e5 39 01 00 callq 41ddb0 <__cfree> - 40a3cb: 48 8b 3c 24 mov (%rsp),%rdi - 40a3cf: e8 dc 39 01 00 callq 41ddb0 <__cfree> - 40a3d4: 49 8b 47 08 mov 0x8(%r15),%rax - 40a3d8: 48 85 c0 test %rax,%rax - 40a3db: 48 89 04 24 mov %rax,(%rsp) - 40a3df: 0f 84 34 ff ff ff je 40a319 - 40a3e5: 8b 00 mov (%rax),%eax - 40a3e7: 83 f8 02 cmp $0x2,%eax - 40a3ea: 0f 84 a2 08 00 00 je 40ac92 - 40a3f0: 83 f8 03 cmp $0x3,%eax - 40a3f3: 0f 84 67 08 00 00 je 40ac60 - 40a3f9: 83 f8 01 cmp $0x1,%eax - 40a3fc: 0f 84 c2 08 00 00 je 40acc4 - 40a402: 48 8b 3c 24 mov (%rsp),%rdi - 40a406: e8 a5 39 01 00 callq 41ddb0 <__cfree> - 40a40b: 4c 89 ff mov %r15,%rdi - 40a40e: e8 9d 39 01 00 callq 41ddb0 <__cfree> - 40a413: e9 f4 f9 ff ff jmpq 409e0c - 40a418: 49 8b 7f 18 mov 0x18(%r15),%rdi - 40a41c: e8 ef b7 ff ff callq 405c10 <__gettext_free_exp> - 40a421: 49 8b 7f 10 mov 0x10(%r15),%rdi - 40a425: e8 e6 b7 ff ff callq 405c10 <__gettext_free_exp> - 40a42a: 49 8b 7f 08 mov 0x8(%r15),%rdi - 40a42e: e8 dd b7 ff ff callq 405c10 <__gettext_free_exp> - 40a433: 4c 89 ff mov %r15,%rdi - 40a436: e8 75 39 01 00 callq 41ddb0 <__cfree> - 40a43b: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 40a43f: 4d 85 ff test %r15,%r15 - 40a442: 74 26 je 40a46a - 40a444: 41 8b 07 mov (%r15),%eax - 40a447: 83 f8 02 cmp $0x2,%eax - 40a44a: 0f 84 11 19 00 00 je 40bd61 - 40a450: 83 f8 03 cmp $0x3,%eax - 40a453: 0f 84 ff 18 00 00 je 40bd58 - 40a459: 83 f8 01 cmp $0x1,%eax - 40a45c: 0f 84 08 19 00 00 je 40bd6a - 40a462: 4c 89 ff mov %r15,%rdi - 40a465: e8 46 39 01 00 callq 41ddb0 <__cfree> - 40a46a: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 40a46e: 4d 85 ff test %r15,%r15 - 40a471: 74 26 je 40a499 - 40a473: 41 8b 07 mov (%r15),%eax - 40a476: 83 f8 02 cmp $0x2,%eax - 40a479: 0f 84 c5 0f 00 00 je 40b444 - 40a47f: 83 f8 03 cmp $0x3,%eax - 40a482: 0f 84 b3 0f 00 00 je 40b43b - 40a488: 83 f8 01 cmp $0x1,%eax - 40a48b: 0f 84 e1 0f 00 00 je 40b472 - 40a491: 4c 89 ff mov %r15,%rdi - 40a494: e8 17 39 01 00 callq 41ddb0 <__cfree> - 40a499: 4c 89 f7 mov %r14,%rdi - 40a49c: e8 0f 39 01 00 callq 41ddb0 <__cfree> - 40a4a1: 4d 8b 75 10 mov 0x10(%r13),%r14 - 40a4a5: 4d 85 f6 test %r14,%r14 - 40a4a8: 0f 84 33 f9 ff ff je 409de1 - 40a4ae: 41 8b 06 mov (%r14),%eax - 40a4b1: 83 f8 02 cmp $0x2,%eax - 40a4b4: 0f 84 25 03 00 00 je 40a7df - 40a4ba: 83 f8 03 cmp $0x3,%eax - 40a4bd: 0f 84 ed 02 00 00 je 40a7b0 - 40a4c3: 83 f8 01 cmp $0x1,%eax - 40a4c6: 0f 84 de f8 ff ff je 409daa - 40a4cc: 4c 89 f7 mov %r14,%rdi - 40a4cf: e8 dc 38 01 00 callq 41ddb0 <__cfree> - 40a4d4: e9 08 f9 ff ff jmpq 409de1 - 40a4d9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 40a4e0: 4d 8b 7e 18 mov 0x18(%r14),%r15 - 40a4e4: 4d 85 ff test %r15,%r15 - 40a4e7: 0f 84 65 fd ff ff je 40a252 - 40a4ed: 41 8b 07 mov (%r15),%eax - 40a4f0: 83 f8 02 cmp $0x2,%eax - 40a4f3: 0f 84 f0 fc ff ff je 40a1e9 - 40a4f9: 83 f8 03 cmp $0x3,%eax - 40a4fc: 0f 84 7e 21 00 00 je 40c680 - 40a502: 83 f8 01 cmp $0x1,%eax - 40a505: 0f 84 0c fd ff ff je 40a217 - 40a50b: 4c 89 ff mov %r15,%rdi - 40a50e: e8 9d 38 01 00 callq 41ddb0 <__cfree> - 40a513: e9 3a fd ff ff jmpq 40a252 - 40a518: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 40a51f: 00 - 40a520: 4d 8b 75 18 mov 0x18(%r13),%r14 - 40a524: 4d 85 f6 test %r14,%r14 - 40a527: 74 26 je 40a54f - 40a529: 41 8b 06 mov (%r14),%eax - 40a52c: 83 f8 02 cmp $0x2,%eax - 40a52f: 0f 84 20 15 00 00 je 40ba55 - 40a535: 83 f8 03 cmp $0x3,%eax - 40a538: 0f 84 0e 15 00 00 je 40ba4c - 40a53e: 83 f8 01 cmp $0x1,%eax - 40a541: 0f 84 3d 15 00 00 je 40ba84 - 40a547: 4c 89 f7 mov %r14,%rdi - 40a54a: e8 61 38 01 00 callq 41ddb0 <__cfree> - 40a54f: 4d 8b 75 10 mov 0x10(%r13),%r14 - 40a553: 4d 85 f6 test %r14,%r14 - 40a556: 0f 84 86 f9 ff ff je 409ee2 - 40a55c: 41 8b 06 mov (%r14),%eax - 40a55f: 83 f8 02 cmp $0x2,%eax - 40a562: 0f 84 14 f9 ff ff je 409e7c - 40a568: 83 f8 03 cmp $0x3,%eax - 40a56b: 0f 84 8f 22 00 00 je 40c800 - 40a571: 83 f8 01 cmp $0x1,%eax - 40a574: 0f 84 31 f9 ff ff je 409eab - 40a57a: 4c 89 f7 mov %r14,%rdi - 40a57d: e8 2e 38 01 00 callq 41ddb0 <__cfree> - 40a582: e9 5b f9 ff ff jmpq 409ee2 - 40a587: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 40a58e: 00 00 - 40a590: 4d 8b 75 18 mov 0x18(%r13),%r14 - 40a594: 4d 85 f6 test %r14,%r14 - 40a597: 0f 84 04 ff ff ff je 40a4a1 - 40a59d: 41 8b 06 mov (%r14),%eax - 40a5a0: 83 f8 02 cmp $0x2,%eax - 40a5a3: 0f 84 92 fe ff ff je 40a43b - 40a5a9: 83 f8 03 cmp $0x3,%eax - 40a5ac: 0f 84 16 22 00 00 je 40c7c8 - 40a5b2: 83 f8 01 cmp $0x1,%eax - 40a5b5: 0f 84 af fe ff ff je 40a46a - 40a5bb: 4c 89 f7 mov %r14,%rdi - 40a5be: e8 ed 37 01 00 callq 41ddb0 <__cfree> - 40a5c3: e9 d9 fe ff ff jmpq 40a4a1 - 40a5c8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 40a5cf: 00 - 40a5d0: 31 c0 xor %eax,%eax - 40a5d2: 48 83 c4 18 add $0x18,%rsp - 40a5d6: 5b pop %rbx - 40a5d7: 5d pop %rbp - 40a5d8: 41 5c pop %r12 - 40a5da: 41 5d pop %r13 - 40a5dc: 41 5e pop %r14 - 40a5de: 41 5f pop %r15 - 40a5e0: c3 retq - 40a5e1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 40a5e8: 48 8b 50 18 mov 0x18(%rax),%rdx - 40a5ec: 48 85 d2 test %rdx,%rdx - 40a5ef: 74 2d je 40a61e - 40a5f1: 8b 0a mov (%rdx),%ecx - 40a5f3: 83 f9 02 cmp $0x2,%ecx - 40a5f6: 0f 84 db 14 00 00 je 40bad7 - 40a5fc: 83 f9 03 cmp $0x3,%ecx - 40a5ff: 0f 84 b7 14 00 00 je 40babc - 40a605: 83 f9 01 cmp $0x1,%ecx - 40a608: 0f 84 e4 14 00 00 je 40baf2 - 40a60e: 48 89 d7 mov %rdx,%rdi - 40a611: 48 89 04 24 mov %rax,(%rsp) - 40a615: e8 96 37 01 00 callq 41ddb0 <__cfree> - 40a61a: 48 8b 04 24 mov (%rsp),%rax - 40a61e: 48 8b 50 10 mov 0x10(%rax),%rdx - 40a622: 48 85 d2 test %rdx,%rdx - 40a625: 0f 84 fe f9 ff ff je 40a029 - 40a62b: 8b 0a mov (%rdx),%ecx - 40a62d: 83 f9 02 cmp $0x2,%ecx - 40a630: 0f 84 ad f9 ff ff je 409fe3 - 40a636: 83 f9 03 cmp $0x3,%ecx - 40a639: 0f 84 89 f9 ff ff je 409fc8 - 40a63f: 83 f9 01 cmp $0x1,%ecx - 40a642: 0f 84 b6 f9 ff ff je 409ffe - 40a648: 48 89 d7 mov %rdx,%rdi - 40a64b: 48 89 04 24 mov %rax,(%rsp) - 40a64f: e8 5c 37 01 00 callq 41ddb0 <__cfree> - 40a654: 48 8b 04 24 mov (%rsp),%rax - 40a658: e9 cc f9 ff ff jmpq 40a029 - 40a65d: 0f 1f 00 nopl (%rax) - 40a660: 49 8b 47 18 mov 0x18(%r15),%rax - 40a664: 48 85 c0 test %rax,%rax - 40a667: 74 25 je 40a68e - 40a669: 8b 10 mov (%rax),%edx - 40a66b: 83 fa 02 cmp $0x2,%edx - 40a66e: 0f 84 10 15 00 00 je 40bb84 - 40a674: 83 fa 03 cmp $0x3,%edx - 40a677: 0f 84 f6 14 00 00 je 40bb73 - 40a67d: 83 fa 01 cmp $0x1,%edx - 40a680: 0f 84 0f 15 00 00 je 40bb95 - 40a686: 48 89 c7 mov %rax,%rdi - 40a689: e8 22 37 01 00 callq 41ddb0 <__cfree> - 40a68e: 49 8b 47 10 mov 0x10(%r15),%rax - 40a692: 48 85 c0 test %rax,%rax - 40a695: 48 89 04 24 mov %rax,(%rsp) - 40a699: 0f 84 23 f6 ff ff je 409cc2 - 40a69f: 8b 00 mov (%rax),%eax - 40a6a1: 83 f8 02 cmp $0x2,%eax - 40a6a4: 0f 84 ab f5 ff ff je 409c55 - 40a6aa: 83 f8 03 cmp $0x3,%eax - 40a6ad: 0f 84 95 f5 ff ff je 409c48 - 40a6b3: 83 f8 01 cmp $0x1,%eax - 40a6b6: 0f 84 cb f5 ff ff je 409c87 - 40a6bc: 48 8b 3c 24 mov (%rsp),%rdi - 40a6c0: e8 eb 36 01 00 callq 41ddb0 <__cfree> - 40a6c5: e9 f8 f5 ff ff jmpq 409cc2 - 40a6ca: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 40a6d0: 49 8b 47 18 mov 0x18(%r15),%rax - 40a6d4: 48 85 c0 test %rax,%rax - 40a6d7: 74 25 je 40a6fe - 40a6d9: 8b 10 mov (%rax),%edx - 40a6db: 83 fa 02 cmp $0x2,%edx - 40a6de: 0f 84 24 16 00 00 je 40bd08 - 40a6e4: 83 fa 03 cmp $0x3,%edx - 40a6e7: 0f 84 0a 16 00 00 je 40bcf7 - 40a6ed: 83 fa 01 cmp $0x1,%edx - 40a6f0: 0f 84 23 16 00 00 je 40bd19 - 40a6f6: 48 89 c7 mov %rax,%rdi - 40a6f9: e8 b2 36 01 00 callq 41ddb0 <__cfree> - 40a6fe: 49 8b 47 10 mov 0x10(%r15),%rax - 40a702: 48 85 c0 test %rax,%rax - 40a705: 48 89 04 24 mov %rax,(%rsp) - 40a709: 0f 84 c5 fc ff ff je 40a3d4 - 40a70f: 8b 00 mov (%rax),%eax - 40a711: 83 f8 02 cmp $0x2,%eax - 40a714: 0f 84 4d fc ff ff je 40a367 - 40a71a: 83 f8 03 cmp $0x3,%eax - 40a71d: 0f 84 ed 28 00 00 je 40d010 - 40a723: 83 f8 01 cmp $0x1,%eax - 40a726: 0f 84 6d fc ff ff je 40a399 - 40a72c: 48 8b 3c 24 mov (%rsp),%rdi - 40a730: e8 7b 36 01 00 callq 41ddb0 <__cfree> - 40a735: e9 9a fc ff ff jmpq 40a3d4 - 40a73a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 40a740: 49 8b 47 18 mov 0x18(%r15),%rax - 40a744: 48 85 c0 test %rax,%rax - 40a747: 74 25 je 40a76e - 40a749: 8b 10 mov (%rax),%edx - 40a74b: 83 fa 02 cmp $0x2,%edx - 40a74e: 0f 84 53 15 00 00 je 40bca7 - 40a754: 83 fa 03 cmp $0x3,%edx - 40a757: 0f 84 39 15 00 00 je 40bc96 - 40a75d: 83 fa 01 cmp $0x1,%edx - 40a760: 0f 84 52 15 00 00 je 40bcb8 - 40a766: 48 89 c7 mov %rax,%rdi - 40a769: e8 42 36 01 00 callq 41ddb0 <__cfree> - 40a76e: 49 8b 47 10 mov 0x10(%r15),%rax - 40a772: 48 85 c0 test %rax,%rax - 40a775: 48 89 04 24 mov %rax,(%rsp) - 40a779: 0f 84 eb f9 ff ff je 40a16a - 40a77f: 8b 00 mov (%rax),%eax - 40a781: 83 f8 02 cmp $0x2,%eax - 40a784: 0f 84 73 f9 ff ff je 40a0fd - 40a78a: 83 f8 03 cmp $0x3,%eax - 40a78d: 0f 84 5d f9 ff ff je 40a0f0 - 40a793: 83 f8 01 cmp $0x1,%eax - 40a796: 0f 84 93 f9 ff ff je 40a12f - 40a79c: 48 8b 3c 24 mov (%rsp),%rdi - 40a7a0: e8 0b 36 01 00 callq 41ddb0 <__cfree> - 40a7a5: e9 c0 f9 ff ff jmpq 40a16a - 40a7aa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 40a7b0: 4d 8b 7e 18 mov 0x18(%r14),%r15 - 40a7b4: 4d 85 ff test %r15,%r15 - 40a7b7: 74 26 je 40a7df - 40a7b9: 41 8b 07 mov (%r15),%eax - 40a7bc: 83 f8 02 cmp $0x2,%eax - 40a7bf: 0f 84 2e 16 00 00 je 40bdf3 - 40a7c5: 83 f8 03 cmp $0x3,%eax - 40a7c8: 0f 84 1c 16 00 00 je 40bdea - 40a7ce: 83 f8 01 cmp $0x1,%eax - 40a7d1: 0f 84 25 16 00 00 je 40bdfc - 40a7d7: 4c 89 ff mov %r15,%rdi - 40a7da: e8 d1 35 01 00 callq 41ddb0 <__cfree> - 40a7df: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 40a7e3: 4d 85 ff test %r15,%r15 - 40a7e6: 0f 84 be f5 ff ff je 409daa - 40a7ec: 41 8b 07 mov (%r15),%eax - 40a7ef: 83 f8 02 cmp $0x2,%eax - 40a7f2: 0f 84 49 f5 ff ff je 409d41 - 40a7f8: 83 f8 03 cmp $0x3,%eax - 40a7fb: 0f 84 37 f5 ff ff je 409d38 - 40a801: 83 f8 01 cmp $0x1,%eax - 40a804: 0f 84 65 f5 ff ff je 409d6f - 40a80a: 4c 89 ff mov %r15,%rdi - 40a80d: e8 9e 35 01 00 callq 41ddb0 <__cfree> - 40a812: e9 93 f5 ff ff jmpq 409daa - 40a817: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 40a81e: 00 00 - 40a820: 4d 8b 7e 18 mov 0x18(%r14),%r15 - 40a824: 4d 85 ff test %r15,%r15 - 40a827: 74 26 je 40a84f - 40a829: 41 8b 07 mov (%r15),%eax - 40a82c: 83 f8 02 cmp $0x2,%eax - 40a82f: 0f 84 ab 1d 00 00 je 40c5e0 - 40a835: 83 f8 03 cmp $0x3,%eax - 40a838: 0f 84 99 1d 00 00 je 40c5d7 - 40a83e: 83 f8 01 cmp $0x1,%eax - 40a841: 0f 84 a2 1d 00 00 je 40c5e9 - 40a847: 4c 89 ff mov %r15,%rdi - 40a84a: e8 61 35 01 00 callq 41ddb0 <__cfree> - 40a84f: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 40a853: 4d 85 ff test %r15,%r15 - 40a856: 74 26 je 40a87e - 40a858: 41 8b 07 mov (%r15),%eax - 40a85b: 83 f8 02 cmp $0x2,%eax - 40a85e: 0f 84 bc 0c 00 00 je 40b520 - 40a864: 83 f8 03 cmp $0x3,%eax - 40a867: 0f 84 aa 0c 00 00 je 40b517 - 40a86d: 83 f8 01 cmp $0x1,%eax - 40a870: 0f 84 d8 0c 00 00 je 40b54e - 40a876: 4c 89 ff mov %r15,%rdi - 40a879: e8 32 35 01 00 callq 41ddb0 <__cfree> - 40a87e: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 40a882: 4d 85 ff test %r15,%r15 - 40a885: 0f 84 82 f6 ff ff je 409f0d - 40a88b: 41 8b 07 mov (%r15),%eax - 40a88e: 83 f8 02 cmp $0x2,%eax - 40a891: 74 56 je 40a8e9 - 40a893: 83 f8 03 cmp $0x3,%eax - 40a896: 0f 84 b4 1d 00 00 je 40c650 - 40a89c: 83 f8 01 cmp $0x1,%eax - 40a89f: 74 76 je 40a917 - 40a8a1: 4c 89 ff mov %r15,%rdi - 40a8a4: e8 07 35 01 00 callq 41ddb0 <__cfree> - 40a8a9: e9 5f f6 ff ff jmpq 409f0d - 40a8ae: 48 8b 78 18 mov 0x18(%rax),%rdi - 40a8b2: 48 89 04 24 mov %rax,(%rsp) - 40a8b6: e8 55 b3 ff ff callq 405c10 <__gettext_free_exp> - 40a8bb: 48 8b 04 24 mov (%rsp),%rax - 40a8bf: 48 8b 78 10 mov 0x10(%rax),%rdi - 40a8c3: 48 89 04 24 mov %rax,(%rsp) - 40a8c7: e8 44 b3 ff ff callq 405c10 <__gettext_free_exp> - 40a8cc: 48 8b 04 24 mov (%rsp),%rax - 40a8d0: 48 8b 78 08 mov 0x8(%rax),%rdi - 40a8d4: 48 89 04 24 mov %rax,(%rsp) - 40a8d8: e8 33 b3 ff ff callq 405c10 <__gettext_free_exp> - 40a8dd: 48 8b 04 24 mov (%rsp),%rax - 40a8e1: 48 89 c7 mov %rax,%rdi - 40a8e4: e8 c7 34 01 00 callq 41ddb0 <__cfree> - 40a8e9: 49 8b 47 10 mov 0x10(%r15),%rax - 40a8ed: 48 85 c0 test %rax,%rax - 40a8f0: 74 25 je 40a917 - 40a8f2: 8b 10 mov (%rax),%edx - 40a8f4: 83 fa 02 cmp $0x2,%edx - 40a8f7: 0f 84 e8 12 00 00 je 40bbe5 - 40a8fd: 83 fa 03 cmp $0x3,%edx - 40a900: 0f 84 ce 12 00 00 je 40bbd4 - 40a906: 83 fa 01 cmp $0x1,%edx - 40a909: 0f 84 e7 12 00 00 je 40bbf6 - 40a90f: 48 89 c7 mov %rax,%rdi - 40a912: e8 99 34 01 00 callq 41ddb0 <__cfree> - 40a917: 49 8b 47 08 mov 0x8(%r15),%rax - 40a91b: 48 85 c0 test %rax,%rax - 40a91e: 48 89 04 24 mov %rax,(%rsp) - 40a922: 0f 84 79 ff ff ff je 40a8a1 - 40a928: 8b 00 mov (%rax),%eax - 40a92a: 83 f8 02 cmp $0x2,%eax - 40a92d: 0f 84 bf 09 00 00 je 40b2f2 - 40a933: 83 f8 03 cmp $0x3,%eax - 40a936: 0f 84 a9 09 00 00 je 40b2e5 - 40a93c: 83 f8 01 cmp $0x1,%eax - 40a93f: 0f 84 df 09 00 00 je 40b324 - 40a945: 48 8b 3c 24 mov (%rsp),%rdi - 40a949: e8 62 34 01 00 callq 41ddb0 <__cfree> - 40a94e: 4c 89 ff mov %r15,%rdi - 40a951: e8 5a 34 01 00 callq 41ddb0 <__cfree> - 40a956: e9 b2 f5 ff ff jmpq 409f0d - 40a95b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 40a960: 4d 8b 7e 18 mov 0x18(%r14),%r15 - 40a964: 4d 85 ff test %r15,%r15 - 40a967: 74 26 je 40a98f - 40a969: 41 8b 07 mov (%r15),%eax - 40a96c: 83 f8 02 cmp $0x2,%eax - 40a96f: 0f 84 73 1d 00 00 je 40c6e8 - 40a975: 83 f8 03 cmp $0x3,%eax - 40a978: 0f 84 61 1d 00 00 je 40c6df - 40a97e: 83 f8 01 cmp $0x1,%eax - 40a981: 0f 84 6a 1d 00 00 je 40c6f1 - 40a987: 4c 89 ff mov %r15,%rdi - 40a98a: e8 21 34 01 00 callq 41ddb0 <__cfree> - 40a98f: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 40a993: 4d 85 ff test %r15,%r15 - 40a996: 74 26 je 40a9be - 40a998: 41 8b 07 mov (%r15),%eax - 40a99b: 83 f8 02 cmp $0x2,%eax - 40a99e: 0f 84 c4 09 00 00 je 40b368 - 40a9a4: 83 f8 03 cmp $0x3,%eax - 40a9a7: 0f 84 b2 09 00 00 je 40b35f - 40a9ad: 83 f8 01 cmp $0x1,%eax - 40a9b0: 0f 84 e0 09 00 00 je 40b396 - 40a9b6: 4c 89 ff mov %r15,%rdi - 40a9b9: e8 f2 33 01 00 callq 41ddb0 <__cfree> - 40a9be: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 40a9c2: 4d 85 ff test %r15,%r15 - 40a9c5: 0f 84 0c f2 ff ff je 409bd7 - 40a9cb: 41 8b 07 mov (%r15),%eax - 40a9ce: 83 f8 02 cmp $0x2,%eax - 40a9d1: 74 56 je 40aa29 - 40a9d3: 83 f8 03 cmp $0x3,%eax - 40a9d6: 0f 84 d4 1c 00 00 je 40c6b0 - 40a9dc: 83 f8 01 cmp $0x1,%eax - 40a9df: 74 76 je 40aa57 - 40a9e1: 4c 89 ff mov %r15,%rdi - 40a9e4: e8 c7 33 01 00 callq 41ddb0 <__cfree> - 40a9e9: e9 e9 f1 ff ff jmpq 409bd7 - 40a9ee: 48 8b 78 18 mov 0x18(%rax),%rdi - 40a9f2: 48 89 04 24 mov %rax,(%rsp) - 40a9f6: e8 15 b2 ff ff callq 405c10 <__gettext_free_exp> - 40a9fb: 48 8b 04 24 mov (%rsp),%rax - 40a9ff: 48 8b 78 10 mov 0x10(%rax),%rdi - 40aa03: 48 89 04 24 mov %rax,(%rsp) - 40aa07: e8 04 b2 ff ff callq 405c10 <__gettext_free_exp> - 40aa0c: 48 8b 04 24 mov (%rsp),%rax - 40aa10: 48 8b 78 08 mov 0x8(%rax),%rdi - 40aa14: 48 89 04 24 mov %rax,(%rsp) - 40aa18: e8 f3 b1 ff ff callq 405c10 <__gettext_free_exp> - 40aa1d: 48 8b 04 24 mov (%rsp),%rax - 40aa21: 48 89 c7 mov %rax,%rdi - 40aa24: e8 87 33 01 00 callq 41ddb0 <__cfree> - 40aa29: 49 8b 47 10 mov 0x10(%r15),%rax - 40aa2d: 48 85 c0 test %rax,%rax - 40aa30: 74 25 je 40aa57 - 40aa32: 8b 10 mov (%rax),%edx - 40aa34: 83 fa 02 cmp $0x2,%edx - 40aa37: 0f 84 09 12 00 00 je 40bc46 - 40aa3d: 83 fa 03 cmp $0x3,%edx - 40aa40: 0f 84 ef 11 00 00 je 40bc35 - 40aa46: 83 fa 01 cmp $0x1,%edx - 40aa49: 0f 84 08 12 00 00 je 40bc57 - 40aa4f: 48 89 c7 mov %rax,%rdi - 40aa52: e8 59 33 01 00 callq 41ddb0 <__cfree> - 40aa57: 49 8b 47 08 mov 0x8(%r15),%rax - 40aa5b: 48 85 c0 test %rax,%rax - 40aa5e: 48 89 04 24 mov %rax,(%rsp) - 40aa62: 0f 84 79 ff ff ff je 40a9e1 - 40aa68: 8b 00 mov (%rax),%eax - 40aa6a: 83 f8 02 cmp $0x2,%eax - 40aa6d: 0f 84 05 08 00 00 je 40b278 - 40aa73: 83 f8 03 cmp $0x3,%eax - 40aa76: 0f 84 ef 07 00 00 je 40b26b - 40aa7c: 83 f8 01 cmp $0x1,%eax - 40aa7f: 0f 84 25 08 00 00 je 40b2aa - 40aa85: 48 8b 3c 24 mov (%rsp),%rdi - 40aa89: e8 22 33 01 00 callq 41ddb0 <__cfree> - 40aa8e: 4c 89 ff mov %r15,%rdi - 40aa91: e8 1a 33 01 00 callq 41ddb0 <__cfree> - 40aa96: e9 3c f1 ff ff jmpq 409bd7 - 40aa9b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 40aaa0: 48 8b 04 24 mov (%rsp),%rax - 40aaa4: 48 8b 40 18 mov 0x18(%rax),%rax - 40aaa8: 48 85 c0 test %rax,%rax - 40aaab: 74 25 je 40aad2 - 40aaad: 8b 10 mov (%rax),%edx - 40aaaf: 83 fa 02 cmp $0x2,%edx - 40aab2: 0f 84 81 22 00 00 je 40cd39 - 40aab8: 83 fa 03 cmp $0x3,%edx - 40aabb: 0f 84 65 22 00 00 je 40cd26 - 40aac1: 83 fa 01 cmp $0x1,%edx - 40aac4: 0f 84 82 22 00 00 je 40cd4c - 40aaca: 48 89 c7 mov %rax,%rdi - 40aacd: e8 de 32 01 00 callq 41ddb0 <__cfree> - 40aad2: 48 8b 04 24 mov (%rsp),%rax - 40aad6: 48 8b 40 10 mov 0x10(%rax),%rax - 40aada: 48 85 c0 test %rax,%rax - 40aadd: 74 25 je 40ab04 - 40aadf: 8b 10 mov (%rax),%edx - 40aae1: 83 fa 02 cmp $0x2,%edx - 40aae4: 0f 84 4f 0d 00 00 je 40b839 - 40aaea: 83 fa 03 cmp $0x3,%edx - 40aaed: 0f 84 33 0d 00 00 je 40b826 - 40aaf3: 83 fa 01 cmp $0x1,%edx - 40aaf6: 0f 84 50 0d 00 00 je 40b84c - 40aafc: 48 89 c7 mov %rax,%rdi - 40aaff: e8 ac 32 01 00 callq 41ddb0 <__cfree> - 40ab04: 48 8b 04 24 mov (%rsp),%rax - 40ab08: 48 8b 40 08 mov 0x8(%rax),%rax - 40ab0c: 48 85 c0 test %rax,%rax - 40ab0f: 0f 84 83 f6 ff ff je 40a198 - 40ab15: 8b 10 mov (%rax),%edx - 40ab17: 83 fa 02 cmp $0x2,%edx - 40ab1a: 74 2f je 40ab4b - 40ab1c: 83 fa 03 cmp $0x3,%edx - 40ab1f: 74 17 je 40ab38 - 40ab21: 83 fa 01 cmp $0x1,%edx - 40ab24: 74 38 je 40ab5e - 40ab26: 48 89 c7 mov %rax,%rdi - 40ab29: e8 82 32 01 00 callq 41ddb0 <__cfree> - 40ab2e: e9 65 f6 ff ff jmpq 40a198 - 40ab33: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 40ab38: 48 8b 78 18 mov 0x18(%rax),%rdi - 40ab3c: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40ab41: e8 ca b0 ff ff callq 405c10 <__gettext_free_exp> - 40ab46: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40ab4b: 48 8b 78 10 mov 0x10(%rax),%rdi - 40ab4f: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40ab54: e8 b7 b0 ff ff callq 405c10 <__gettext_free_exp> - 40ab59: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40ab5e: 48 8b 78 08 mov 0x8(%rax),%rdi - 40ab62: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40ab67: e8 a4 b0 ff ff callq 405c10 <__gettext_free_exp> - 40ab6c: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40ab71: 48 89 c7 mov %rax,%rdi - 40ab74: e8 37 32 01 00 callq 41ddb0 <__cfree> - 40ab79: e9 1a f6 ff ff jmpq 40a198 - 40ab7e: 66 90 xchg %ax,%ax - 40ab80: 48 8b 04 24 mov (%rsp),%rax - 40ab84: 48 8b 40 18 mov 0x18(%rax),%rax - 40ab88: 48 85 c0 test %rax,%rax - 40ab8b: 74 25 je 40abb2 - 40ab8d: 8b 10 mov (%rax),%edx - 40ab8f: 83 fa 02 cmp $0x2,%edx - 40ab92: 0f 84 39 1f 00 00 je 40cad1 - 40ab98: 83 fa 03 cmp $0x3,%edx - 40ab9b: 0f 84 1d 1f 00 00 je 40cabe - 40aba1: 83 fa 01 cmp $0x1,%edx - 40aba4: 0f 84 3a 1f 00 00 je 40cae4 - 40abaa: 48 89 c7 mov %rax,%rdi - 40abad: e8 fe 31 01 00 callq 41ddb0 <__cfree> - 40abb2: 48 8b 04 24 mov (%rsp),%rax - 40abb6: 48 8b 40 10 mov 0x10(%rax),%rax - 40abba: 48 85 c0 test %rax,%rax - 40abbd: 74 25 je 40abe4 - 40abbf: 8b 10 mov (%rax),%edx - 40abc1: 83 fa 02 cmp $0x2,%edx - 40abc4: 0f 84 b5 0b 00 00 je 40b77f - 40abca: 83 fa 03 cmp $0x3,%edx - 40abcd: 0f 84 99 0b 00 00 je 40b76c - 40abd3: 83 fa 01 cmp $0x1,%edx - 40abd6: 0f 84 b6 0b 00 00 je 40b792 - 40abdc: 48 89 c7 mov %rax,%rdi - 40abdf: e8 cc 31 01 00 callq 41ddb0 <__cfree> - 40abe4: 48 8b 04 24 mov (%rsp),%rax - 40abe8: 48 8b 40 08 mov 0x8(%rax),%rax - 40abec: 48 85 c0 test %rax,%rax - 40abef: 0f 84 90 f3 ff ff je 409f85 - 40abf5: 8b 10 mov (%rax),%edx - 40abf7: 83 fa 02 cmp $0x2,%edx - 40abfa: 74 2f je 40ac2b - 40abfc: 83 fa 03 cmp $0x3,%edx - 40abff: 74 17 je 40ac18 - 40ac01: 83 fa 01 cmp $0x1,%edx - 40ac04: 74 38 je 40ac3e - 40ac06: 48 89 c7 mov %rax,%rdi - 40ac09: e8 a2 31 01 00 callq 41ddb0 <__cfree> - 40ac0e: e9 72 f3 ff ff jmpq 409f85 - 40ac13: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 40ac18: 48 8b 78 18 mov 0x18(%rax),%rdi - 40ac1c: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40ac21: e8 ea af ff ff callq 405c10 <__gettext_free_exp> - 40ac26: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40ac2b: 48 8b 78 10 mov 0x10(%rax),%rdi - 40ac2f: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40ac34: e8 d7 af ff ff callq 405c10 <__gettext_free_exp> - 40ac39: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40ac3e: 48 8b 78 08 mov 0x8(%rax),%rdi - 40ac42: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40ac47: e8 c4 af ff ff callq 405c10 <__gettext_free_exp> - 40ac4c: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40ac51: 48 89 c7 mov %rax,%rdi - 40ac54: e8 57 31 01 00 callq 41ddb0 <__cfree> - 40ac59: e9 27 f3 ff ff jmpq 409f85 - 40ac5e: 66 90 xchg %ax,%ax - 40ac60: 48 8b 04 24 mov (%rsp),%rax - 40ac64: 48 8b 40 18 mov 0x18(%rax),%rax - 40ac68: 48 85 c0 test %rax,%rax - 40ac6b: 74 25 je 40ac92 - 40ac6d: 8b 10 mov (%rax),%edx - 40ac6f: 83 fa 02 cmp $0x2,%edx - 40ac72: 0f 84 1b 1e 00 00 je 40ca93 - 40ac78: 83 fa 03 cmp $0x3,%edx - 40ac7b: 0f 84 ff 1d 00 00 je 40ca80 - 40ac81: 83 fa 01 cmp $0x1,%edx - 40ac84: 0f 84 1c 1e 00 00 je 40caa6 - 40ac8a: 48 89 c7 mov %rax,%rdi - 40ac8d: e8 1e 31 01 00 callq 41ddb0 <__cfree> - 40ac92: 48 8b 04 24 mov (%rsp),%rax - 40ac96: 48 8b 40 10 mov 0x10(%rax),%rax - 40ac9a: 48 85 c0 test %rax,%rax - 40ac9d: 74 25 je 40acc4 - 40ac9f: 8b 10 mov (%rax),%edx - 40aca1: 83 fa 02 cmp $0x2,%edx - 40aca4: 0f 84 97 0a 00 00 je 40b741 - 40acaa: 83 fa 03 cmp $0x3,%edx - 40acad: 0f 84 7b 0a 00 00 je 40b72e - 40acb3: 83 fa 01 cmp $0x1,%edx - 40acb6: 0f 84 98 0a 00 00 je 40b754 - 40acbc: 48 89 c7 mov %rax,%rdi - 40acbf: e8 ec 30 01 00 callq 41ddb0 <__cfree> - 40acc4: 48 8b 04 24 mov (%rsp),%rax - 40acc8: 48 8b 40 08 mov 0x8(%rax),%rax - 40accc: 48 85 c0 test %rax,%rax - 40accf: 0f 84 2d f7 ff ff je 40a402 - 40acd5: 8b 10 mov (%rax),%edx - 40acd7: 83 fa 02 cmp $0x2,%edx - 40acda: 74 2f je 40ad0b - 40acdc: 83 fa 03 cmp $0x3,%edx - 40acdf: 74 17 je 40acf8 - 40ace1: 83 fa 01 cmp $0x1,%edx - 40ace4: 74 38 je 40ad1e - 40ace6: 48 89 c7 mov %rax,%rdi - 40ace9: e8 c2 30 01 00 callq 41ddb0 <__cfree> - 40acee: e9 0f f7 ff ff jmpq 40a402 - 40acf3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 40acf8: 48 8b 78 18 mov 0x18(%rax),%rdi - 40acfc: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40ad01: e8 0a af ff ff callq 405c10 <__gettext_free_exp> - 40ad06: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40ad0b: 48 8b 78 10 mov 0x10(%rax),%rdi - 40ad0f: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40ad14: e8 f7 ae ff ff callq 405c10 <__gettext_free_exp> - 40ad19: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40ad1e: 48 8b 78 08 mov 0x8(%rax),%rdi - 40ad22: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40ad27: e8 e4 ae ff ff callq 405c10 <__gettext_free_exp> - 40ad2c: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40ad31: 48 89 c7 mov %rax,%rdi - 40ad34: e8 77 30 01 00 callq 41ddb0 <__cfree> - 40ad39: e9 c4 f6 ff ff jmpq 40a402 - 40ad3e: 66 90 xchg %ax,%ax - 40ad40: 48 8b 04 24 mov (%rsp),%rax - 40ad44: 48 8b 40 18 mov 0x18(%rax),%rax - 40ad48: 48 85 c0 test %rax,%rax - 40ad4b: 74 25 je 40ad72 - 40ad4d: 8b 10 mov (%rax),%edx - 40ad4f: 83 fa 02 cmp $0x2,%edx - 40ad52: 0f 84 2b 1c 00 00 je 40c983 - 40ad58: 83 fa 03 cmp $0x3,%edx - 40ad5b: 0f 84 0f 1c 00 00 je 40c970 - 40ad61: 83 fa 01 cmp $0x1,%edx - 40ad64: 0f 84 2c 1c 00 00 je 40c996 - 40ad6a: 48 89 c7 mov %rax,%rdi - 40ad6d: e8 3e 30 01 00 callq 41ddb0 <__cfree> - 40ad72: 48 8b 04 24 mov (%rsp),%rax - 40ad76: 48 8b 40 10 mov 0x10(%rax),%rax - 40ad7a: 48 85 c0 test %rax,%rax - 40ad7d: 74 25 je 40ada4 - 40ad7f: 8b 10 mov (%rax),%edx - 40ad81: 83 fa 02 cmp $0x2,%edx - 40ad84: 0f 84 79 09 00 00 je 40b703 - 40ad8a: 83 fa 03 cmp $0x3,%edx - 40ad8d: 0f 84 5d 09 00 00 je 40b6f0 - 40ad93: 83 fa 01 cmp $0x1,%edx - 40ad96: 0f 84 7a 09 00 00 je 40b716 - 40ad9c: 48 89 c7 mov %rax,%rdi - 40ad9f: e8 0c 30 01 00 callq 41ddb0 <__cfree> - 40ada4: 48 8b 04 24 mov (%rsp),%rax - 40ada8: 48 8b 40 08 mov 0x8(%rax),%rax - 40adac: 48 85 c0 test %rax,%rax - 40adaf: 0f 84 37 ef ff ff je 409cec - 40adb5: 8b 10 mov (%rax),%edx - 40adb7: 83 fa 02 cmp $0x2,%edx - 40adba: 74 2f je 40adeb - 40adbc: 83 fa 03 cmp $0x3,%edx - 40adbf: 74 17 je 40add8 - 40adc1: 83 fa 01 cmp $0x1,%edx - 40adc4: 74 38 je 40adfe - 40adc6: 48 89 c7 mov %rax,%rdi - 40adc9: e8 e2 2f 01 00 callq 41ddb0 <__cfree> - 40adce: e9 19 ef ff ff jmpq 409cec - 40add3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 40add8: 48 8b 78 18 mov 0x18(%rax),%rdi - 40addc: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40ade1: e8 2a ae ff ff callq 405c10 <__gettext_free_exp> - 40ade6: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40adeb: 48 8b 78 10 mov 0x10(%rax),%rdi - 40adef: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40adf4: e8 17 ae ff ff callq 405c10 <__gettext_free_exp> - 40adf9: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40adfe: 48 8b 78 08 mov 0x8(%rax),%rdi - 40ae02: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40ae07: e8 04 ae ff ff callq 405c10 <__gettext_free_exp> - 40ae0c: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40ae11: 48 89 c7 mov %rax,%rdi - 40ae14: e8 97 2f 01 00 callq 41ddb0 <__cfree> - 40ae19: e9 ce ee ff ff jmpq 409cec - 40ae1e: 66 90 xchg %ax,%ax - 40ae20: 49 8b 47 18 mov 0x18(%r15),%rax - 40ae24: 48 85 c0 test %rax,%rax - 40ae27: 74 25 je 40ae4e - 40ae29: 8b 10 mov (%rax),%edx - 40ae2b: 83 fa 02 cmp $0x2,%edx - 40ae2e: 0f 84 20 22 00 00 je 40d054 - 40ae34: 83 fa 03 cmp $0x3,%edx - 40ae37: 0f 84 06 22 00 00 je 40d043 - 40ae3d: 83 fa 01 cmp $0x1,%edx - 40ae40: 0f 84 1f 22 00 00 je 40d065 - 40ae46: 48 89 c7 mov %rax,%rdi - 40ae49: e8 62 2f 01 00 callq 41ddb0 <__cfree> - 40ae4e: 49 8b 47 10 mov 0x10(%r15),%rax - 40ae52: 48 85 c0 test %rax,%rax - 40ae55: 48 89 04 24 mov %rax,(%rsp) - 40ae59: 74 26 je 40ae81 - 40ae5b: 8b 00 mov (%rax),%eax - 40ae5d: 83 f8 02 cmp $0x2,%eax - 40ae60: 0f 84 ff 0a 00 00 je 40b965 - 40ae66: 83 f8 03 cmp $0x3,%eax - 40ae69: 0f 84 e9 0a 00 00 je 40b958 - 40ae6f: 83 f8 01 cmp $0x1,%eax - 40ae72: 0f 84 1f 0b 00 00 je 40b997 - 40ae78: 48 8b 3c 24 mov (%rsp),%rdi - 40ae7c: e8 2f 2f 01 00 callq 41ddb0 <__cfree> - 40ae81: 49 8b 47 08 mov 0x8(%r15),%rax - 40ae85: 48 85 c0 test %rax,%rax - 40ae88: 48 89 04 24 mov %rax,(%rsp) - 40ae8c: 0f 84 14 f2 ff ff je 40a0a6 - 40ae92: 8b 00 mov (%rax),%eax - 40ae94: 83 f8 02 cmp $0x2,%eax - 40ae97: 74 2c je 40aec5 - 40ae99: 83 f8 03 cmp $0x3,%eax - 40ae9c: 74 1a je 40aeb8 - 40ae9e: 83 f8 01 cmp $0x1,%eax - 40aea1: 74 54 je 40aef7 - 40aea3: 48 8b 3c 24 mov (%rsp),%rdi - 40aea7: e8 04 2f 01 00 callq 41ddb0 <__cfree> - 40aeac: e9 f5 f1 ff ff jmpq 40a0a6 - 40aeb1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 40aeb8: 48 8b 04 24 mov (%rsp),%rax - 40aebc: 48 8b 78 18 mov 0x18(%rax),%rdi - 40aec0: e8 4b ad ff ff callq 405c10 <__gettext_free_exp> - 40aec5: 48 8b 04 24 mov (%rsp),%rax - 40aec9: 48 8b 40 10 mov 0x10(%rax),%rax - 40aecd: 48 85 c0 test %rax,%rax - 40aed0: 74 25 je 40aef7 - 40aed2: 8b 10 mov (%rax),%edx - 40aed4: 83 fa 02 cmp $0x2,%edx - 40aed7: 0f 84 e5 0f 00 00 je 40bec2 - 40aedd: 83 fa 03 cmp $0x3,%edx - 40aee0: 0f 84 c9 0f 00 00 je 40beaf - 40aee6: 83 fa 01 cmp $0x1,%edx - 40aee9: 0f 84 e6 0f 00 00 je 40bed5 - 40aeef: 48 89 c7 mov %rax,%rdi - 40aef2: e8 b9 2e 01 00 callq 41ddb0 <__cfree> - 40aef7: 48 8b 04 24 mov (%rsp),%rax - 40aefb: 48 8b 40 08 mov 0x8(%rax),%rax - 40aeff: 48 85 c0 test %rax,%rax - 40af02: 74 9f je 40aea3 - 40af04: 8b 10 mov (%rax),%edx - 40af06: 83 fa 02 cmp $0x2,%edx - 40af09: 0f 84 3a 07 00 00 je 40b649 - 40af0f: 83 fa 03 cmp $0x3,%edx - 40af12: 0f 84 1e 07 00 00 je 40b636 - 40af18: 83 fa 01 cmp $0x1,%edx - 40af1b: 0f 84 3b 07 00 00 je 40b65c - 40af21: 48 89 c7 mov %rax,%rdi - 40af24: e8 87 2e 01 00 callq 41ddb0 <__cfree> - 40af29: 48 8b 3c 24 mov (%rsp),%rdi - 40af2d: e8 7e 2e 01 00 callq 41ddb0 <__cfree> - 40af32: e9 6f f1 ff ff jmpq 40a0a6 - 40af37: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 40af3e: 00 00 - 40af40: 49 8b 47 18 mov 0x18(%r15),%rax - 40af44: 48 85 c0 test %rax,%rax - 40af47: 74 25 je 40af6e - 40af49: 8b 10 mov (%rax),%edx - 40af4b: 83 fa 02 cmp $0x2,%edx - 40af4e: 0f 84 a8 21 00 00 je 40d0fc - 40af54: 83 fa 03 cmp $0x3,%edx - 40af57: 0f 84 8e 21 00 00 je 40d0eb - 40af5d: 83 fa 01 cmp $0x1,%edx - 40af60: 0f 84 a7 21 00 00 je 40d10d - 40af66: 48 89 c7 mov %rax,%rdi - 40af69: e8 42 2e 01 00 callq 41ddb0 <__cfree> - 40af6e: 49 8b 47 10 mov 0x10(%r15),%rax - 40af72: 48 85 c0 test %rax,%rax - 40af75: 48 89 04 24 mov %rax,(%rsp) - 40af79: 74 26 je 40afa1 - 40af7b: 8b 00 mov (%rax),%eax - 40af7d: 83 f8 02 cmp $0x2,%eax - 40af80: 0f 84 eb 08 00 00 je 40b871 - 40af86: 83 f8 03 cmp $0x3,%eax - 40af89: 0f 84 d5 08 00 00 je 40b864 - 40af8f: 83 f8 01 cmp $0x1,%eax - 40af92: 0f 84 0b 09 00 00 je 40b8a3 - 40af98: 48 8b 3c 24 mov (%rsp),%rdi - 40af9c: e8 0f 2e 01 00 callq 41ddb0 <__cfree> - 40afa1: 49 8b 47 08 mov 0x8(%r15),%rax - 40afa5: 48 85 c0 test %rax,%rax - 40afa8: 48 89 04 24 mov %rax,(%rsp) - 40afac: 0f 84 34 f3 ff ff je 40a2e6 - 40afb2: 8b 00 mov (%rax),%eax - 40afb4: 83 f8 02 cmp $0x2,%eax - 40afb7: 74 2c je 40afe5 - 40afb9: 83 f8 03 cmp $0x3,%eax - 40afbc: 74 1a je 40afd8 - 40afbe: 83 f8 01 cmp $0x1,%eax - 40afc1: 74 54 je 40b017 - 40afc3: 48 8b 3c 24 mov (%rsp),%rdi - 40afc7: e8 e4 2d 01 00 callq 41ddb0 <__cfree> - 40afcc: e9 15 f3 ff ff jmpq 40a2e6 - 40afd1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 40afd8: 48 8b 04 24 mov (%rsp),%rax - 40afdc: 48 8b 78 18 mov 0x18(%rax),%rdi - 40afe0: e8 2b ac ff ff callq 405c10 <__gettext_free_exp> - 40afe5: 48 8b 04 24 mov (%rsp),%rax - 40afe9: 48 8b 40 10 mov 0x10(%rax),%rax - 40afed: 48 85 c0 test %rax,%rax - 40aff0: 74 25 je 40b017 - 40aff2: 8b 10 mov (%rax),%edx - 40aff4: 83 fa 02 cmp $0x2,%edx - 40aff7: 0f 84 7f 0f 00 00 je 40bf7c - 40affd: 83 fa 03 cmp $0x3,%edx - 40b000: 0f 84 63 0f 00 00 je 40bf69 - 40b006: 83 fa 01 cmp $0x1,%edx - 40b009: 0f 84 80 0f 00 00 je 40bf8f - 40b00f: 48 89 c7 mov %rax,%rdi - 40b012: e8 99 2d 01 00 callq 41ddb0 <__cfree> - 40b017: 48 8b 04 24 mov (%rsp),%rax - 40b01b: 48 8b 40 08 mov 0x8(%rax),%rax - 40b01f: 48 85 c0 test %rax,%rax - 40b022: 74 9f je 40afc3 - 40b024: 8b 10 mov (%rax),%edx - 40b026: 83 fa 02 cmp $0x2,%edx - 40b029: 0f 84 96 06 00 00 je 40b6c5 - 40b02f: 83 fa 03 cmp $0x3,%edx - 40b032: 0f 84 7a 06 00 00 je 40b6b2 - 40b038: 83 fa 01 cmp $0x1,%edx - 40b03b: 0f 84 97 06 00 00 je 40b6d8 - 40b041: 48 89 c7 mov %rax,%rdi - 40b044: e8 67 2d 01 00 callq 41ddb0 <__cfree> - 40b049: 48 8b 3c 24 mov (%rsp),%rdi - 40b04d: e8 5e 2d 01 00 callq 41ddb0 <__cfree> - 40b052: e9 8f f2 ff ff jmpq 40a2e6 - 40b057: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 40b05e: 00 00 - 40b060: 49 8b 47 18 mov 0x18(%r15),%rax - 40b064: 48 85 c0 test %rax,%rax - 40b067: 74 25 je 40b08e - 40b069: 8b 10 mov (%rax),%edx - 40b06b: 83 fa 02 cmp $0x2,%edx - 40b06e: 0f 84 c5 1e 00 00 je 40cf39 - 40b074: 83 fa 03 cmp $0x3,%edx - 40b077: 0f 84 ab 1e 00 00 je 40cf28 - 40b07d: 83 fa 01 cmp $0x1,%edx - 40b080: 0f 84 c4 1e 00 00 je 40cf4a - 40b086: 48 89 c7 mov %rax,%rdi - 40b089: e8 22 2d 01 00 callq 41ddb0 <__cfree> - 40b08e: 49 8b 47 10 mov 0x10(%r15),%rax - 40b092: 48 85 c0 test %rax,%rax - 40b095: 48 89 04 24 mov %rax,(%rsp) - 40b099: 74 26 je 40b0c1 - 40b09b: 8b 00 mov (%rax),%eax - 40b09d: 83 f8 02 cmp $0x2,%eax - 40b0a0: 0f 84 39 09 00 00 je 40b9df - 40b0a6: 83 f8 03 cmp $0x3,%eax - 40b0a9: 0f 84 23 09 00 00 je 40b9d2 - 40b0af: 83 f8 01 cmp $0x1,%eax - 40b0b2: 0f 84 59 09 00 00 je 40ba11 - 40b0b8: 48 8b 3c 24 mov (%rsp),%rdi - 40b0bc: e8 ef 2c 01 00 callq 41ddb0 <__cfree> - 40b0c1: 49 8b 47 08 mov 0x8(%r15),%rax - 40b0c5: 48 85 c0 test %rax,%rax - 40b0c8: 48 89 04 24 mov %rax,(%rsp) - 40b0cc: 0f 84 ff ec ff ff je 409dd1 - 40b0d2: 8b 00 mov (%rax),%eax - 40b0d4: 83 f8 02 cmp $0x2,%eax - 40b0d7: 74 2c je 40b105 - 40b0d9: 83 f8 03 cmp $0x3,%eax - 40b0dc: 74 1a je 40b0f8 - 40b0de: 83 f8 01 cmp $0x1,%eax - 40b0e1: 74 54 je 40b137 - 40b0e3: 48 8b 3c 24 mov (%rsp),%rdi - 40b0e7: e8 c4 2c 01 00 callq 41ddb0 <__cfree> - 40b0ec: e9 e0 ec ff ff jmpq 409dd1 - 40b0f1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 40b0f8: 48 8b 04 24 mov (%rsp),%rax - 40b0fc: 48 8b 78 18 mov 0x18(%rax),%rdi - 40b100: e8 0b ab ff ff callq 405c10 <__gettext_free_exp> - 40b105: 48 8b 04 24 mov (%rsp),%rax - 40b109: 48 8b 40 10 mov 0x10(%rax),%rax - 40b10d: 48 85 c0 test %rax,%rax - 40b110: 74 25 je 40b137 - 40b112: 8b 10 mov (%rax),%edx - 40b114: 83 fa 02 cmp $0x2,%edx - 40b117: 0f 84 21 0e 00 00 je 40bf3e - 40b11d: 83 fa 03 cmp $0x3,%edx - 40b120: 0f 84 05 0e 00 00 je 40bf2b - 40b126: 83 fa 01 cmp $0x1,%edx - 40b129: 0f 84 22 0e 00 00 je 40bf51 - 40b12f: 48 89 c7 mov %rax,%rdi - 40b132: e8 79 2c 01 00 callq 41ddb0 <__cfree> - 40b137: 48 8b 04 24 mov (%rsp),%rax - 40b13b: 48 8b 40 08 mov 0x8(%rax),%rax - 40b13f: 48 85 c0 test %rax,%rax - 40b142: 74 9f je 40b0e3 - 40b144: 8b 10 mov (%rax),%edx - 40b146: 83 fa 02 cmp $0x2,%edx - 40b149: 0f 84 38 05 00 00 je 40b687 - 40b14f: 83 fa 03 cmp $0x3,%edx - 40b152: 0f 84 1c 05 00 00 je 40b674 - 40b158: 83 fa 01 cmp $0x1,%edx - 40b15b: 0f 84 39 05 00 00 je 40b69a - 40b161: 48 89 c7 mov %rax,%rdi - 40b164: e8 47 2c 01 00 callq 41ddb0 <__cfree> - 40b169: 48 8b 3c 24 mov (%rsp),%rdi - 40b16d: e8 3e 2c 01 00 callq 41ddb0 <__cfree> - 40b172: e9 5a ec ff ff jmpq 409dd1 - 40b177: 48 8b 04 24 mov (%rsp),%rax - 40b17b: 48 8b 78 18 mov 0x18(%rax),%rdi - 40b17f: e8 8c aa ff ff callq 405c10 <__gettext_free_exp> - 40b184: 48 8b 04 24 mov (%rsp),%rax - 40b188: 48 8b 40 10 mov 0x10(%rax),%rax - 40b18c: 48 85 c0 test %rax,%rax - 40b18f: 74 25 je 40b1b6 - 40b191: 8b 10 mov (%rax),%edx - 40b193: 83 fa 02 cmp $0x2,%edx - 40b196: 0f 84 b9 18 00 00 je 40ca55 - 40b19c: 83 fa 03 cmp $0x3,%edx - 40b19f: 0f 84 9d 18 00 00 je 40ca42 - 40b1a5: 83 fa 01 cmp $0x1,%edx - 40b1a8: 0f 84 ba 18 00 00 je 40ca68 - 40b1ae: 48 89 c7 mov %rax,%rdi - 40b1b1: e8 fa 2b 01 00 callq 41ddb0 <__cfree> - 40b1b6: 48 8b 04 24 mov (%rsp),%rax - 40b1ba: 48 8b 40 08 mov 0x8(%rax),%rax - 40b1be: 48 85 c0 test %rax,%rax - 40b1c1: 0f 84 8b ed ff ff je 409f52 - 40b1c7: 8b 10 mov (%rax),%edx - 40b1c9: 83 fa 02 cmp $0x2,%edx - 40b1cc: 0f 84 c7 0f 00 00 je 40c199 - 40b1d2: 83 fa 03 cmp $0x3,%edx - 40b1d5: 0f 84 ab 0f 00 00 je 40c186 - 40b1db: 83 fa 01 cmp $0x1,%edx - 40b1de: 0f 84 c8 0f 00 00 je 40c1ac - 40b1e4: 48 89 c7 mov %rax,%rdi - 40b1e7: e8 c4 2b 01 00 callq 41ddb0 <__cfree> - 40b1ec: e9 61 ed ff ff jmpq 409f52 - 40b1f1: 48 8b 04 24 mov (%rsp),%rax - 40b1f5: 48 8b 78 18 mov 0x18(%rax),%rdi - 40b1f9: e8 12 aa ff ff callq 405c10 <__gettext_free_exp> - 40b1fe: 48 8b 04 24 mov (%rsp),%rax - 40b202: 48 8b 40 10 mov 0x10(%rax),%rax - 40b206: 48 85 c0 test %rax,%rax - 40b209: 74 25 je 40b230 - 40b20b: 8b 10 mov (%rax),%edx - 40b20d: 83 fa 02 cmp $0x2,%edx - 40b210: 0f 84 2f 17 00 00 je 40c945 - 40b216: 83 fa 03 cmp $0x3,%edx - 40b219: 0f 84 13 17 00 00 je 40c932 - 40b21f: 83 fa 01 cmp $0x1,%edx - 40b222: 0f 84 30 17 00 00 je 40c958 - 40b228: 48 89 c7 mov %rax,%rdi - 40b22b: e8 80 2b 01 00 callq 41ddb0 <__cfree> - 40b230: 48 8b 04 24 mov (%rsp),%rax - 40b234: 48 8b 40 08 mov 0x8(%rax),%rax - 40b238: 48 85 c0 test %rax,%rax - 40b23b: 0f 84 00 f0 ff ff je 40a241 - 40b241: 8b 10 mov (%rax),%edx - 40b243: 83 fa 02 cmp $0x2,%edx - 40b246: 0f 84 c9 0f 00 00 je 40c215 - 40b24c: 83 fa 03 cmp $0x3,%edx - 40b24f: 0f 84 ad 0f 00 00 je 40c202 - 40b255: 83 fa 01 cmp $0x1,%edx - 40b258: 0f 84 ca 0f 00 00 je 40c228 - 40b25e: 48 89 c7 mov %rax,%rdi - 40b261: e8 4a 2b 01 00 callq 41ddb0 <__cfree> - 40b266: e9 d6 ef ff ff jmpq 40a241 - 40b26b: 48 8b 04 24 mov (%rsp),%rax - 40b26f: 48 8b 78 18 mov 0x18(%rax),%rdi - 40b273: e8 98 a9 ff ff callq 405c10 <__gettext_free_exp> - 40b278: 48 8b 04 24 mov (%rsp),%rax - 40b27c: 48 8b 40 10 mov 0x10(%rax),%rax - 40b280: 48 85 c0 test %rax,%rax - 40b283: 74 25 je 40b2aa - 40b285: 8b 10 mov (%rax),%edx - 40b287: 83 fa 02 cmp $0x2,%edx - 40b28a: 0f 84 d5 18 00 00 je 40cb65 - 40b290: 83 fa 03 cmp $0x3,%edx - 40b293: 0f 84 b9 18 00 00 je 40cb52 - 40b299: 83 fa 01 cmp $0x1,%edx - 40b29c: 0f 84 d6 18 00 00 je 40cb78 - 40b2a2: 48 89 c7 mov %rax,%rdi - 40b2a5: e8 06 2b 01 00 callq 41ddb0 <__cfree> - 40b2aa: 48 8b 04 24 mov (%rsp),%rax - 40b2ae: 48 8b 40 08 mov 0x8(%rax),%rax - 40b2b2: 48 85 c0 test %rax,%rax - 40b2b5: 0f 84 ca f7 ff ff je 40aa85 - 40b2bb: 8b 10 mov (%rax),%edx - 40b2bd: 83 fa 02 cmp $0x2,%edx - 40b2c0: 0f 84 8d 0f 00 00 je 40c253 - 40b2c6: 83 fa 03 cmp $0x3,%edx - 40b2c9: 0f 84 71 0f 00 00 je 40c240 - 40b2cf: 83 fa 01 cmp $0x1,%edx - 40b2d2: 0f 84 8e 0f 00 00 je 40c266 - 40b2d8: 48 89 c7 mov %rax,%rdi - 40b2db: e8 d0 2a 01 00 callq 41ddb0 <__cfree> - 40b2e0: e9 a0 f7 ff ff jmpq 40aa85 - 40b2e5: 48 8b 04 24 mov (%rsp),%rax - 40b2e9: 48 8b 78 18 mov 0x18(%rax),%rdi - 40b2ed: e8 1e a9 ff ff callq 405c10 <__gettext_free_exp> - 40b2f2: 48 8b 04 24 mov (%rsp),%rax - 40b2f6: 48 8b 40 10 mov 0x10(%rax),%rax - 40b2fa: 48 85 c0 test %rax,%rax - 40b2fd: 74 25 je 40b324 - 40b2ff: 8b 10 mov (%rax),%edx - 40b301: 83 fa 02 cmp $0x2,%edx - 40b304: 0f 84 99 18 00 00 je 40cba3 - 40b30a: 83 fa 03 cmp $0x3,%edx - 40b30d: 0f 84 7d 18 00 00 je 40cb90 - 40b313: 83 fa 01 cmp $0x1,%edx - 40b316: 0f 84 9a 18 00 00 je 40cbb6 - 40b31c: 48 89 c7 mov %rax,%rdi - 40b31f: e8 8c 2a 01 00 callq 41ddb0 <__cfree> - 40b324: 48 8b 04 24 mov (%rsp),%rax - 40b328: 48 8b 40 08 mov 0x8(%rax),%rax - 40b32c: 48 85 c0 test %rax,%rax - 40b32f: 0f 84 10 f6 ff ff je 40a945 - 40b335: 8b 10 mov (%rax),%edx - 40b337: 83 fa 02 cmp $0x2,%edx - 40b33a: 0f 84 97 0e 00 00 je 40c1d7 - 40b340: 83 fa 03 cmp $0x3,%edx - 40b343: 0f 84 7b 0e 00 00 je 40c1c4 - 40b349: 83 fa 01 cmp $0x1,%edx - 40b34c: 0f 84 98 0e 00 00 je 40c1ea - 40b352: 48 89 c7 mov %rax,%rdi - 40b355: e8 56 2a 01 00 callq 41ddb0 <__cfree> - 40b35a: e9 e6 f5 ff ff jmpq 40a945 - 40b35f: 49 8b 7f 18 mov 0x18(%r15),%rdi - 40b363: e8 a8 a8 ff ff callq 405c10 <__gettext_free_exp> - 40b368: 49 8b 47 10 mov 0x10(%r15),%rax - 40b36c: 48 85 c0 test %rax,%rax - 40b36f: 74 25 je 40b396 - 40b371: 8b 10 mov (%rax),%edx - 40b373: 83 fa 02 cmp $0x2,%edx - 40b376: 0f 84 85 1b 00 00 je 40cf01 - 40b37c: 83 fa 03 cmp $0x3,%edx - 40b37f: 0f 84 6b 1b 00 00 je 40cef0 - 40b385: 83 fa 01 cmp $0x1,%edx - 40b388: 0f 84 84 1b 00 00 je 40cf12 - 40b38e: 48 89 c7 mov %rax,%rdi - 40b391: e8 1a 2a 01 00 callq 41ddb0 <__cfree> - 40b396: 49 8b 47 08 mov 0x8(%r15),%rax - 40b39a: 48 85 c0 test %rax,%rax - 40b39d: 0f 84 13 f6 ff ff je 40a9b6 - 40b3a3: 8b 10 mov (%rax),%edx - 40b3a5: 83 fa 02 cmp $0x2,%edx - 40b3a8: 0f 84 04 10 00 00 je 40c3b2 - 40b3ae: 83 fa 03 cmp $0x3,%edx - 40b3b1: 0f 84 ea 0f 00 00 je 40c3a1 - 40b3b7: 83 fa 01 cmp $0x1,%edx - 40b3ba: 0f 84 03 10 00 00 je 40c3c3 - 40b3c0: 48 89 c7 mov %rax,%rdi - 40b3c3: e8 e8 29 01 00 callq 41ddb0 <__cfree> - 40b3c8: e9 e9 f5 ff ff jmpq 40a9b6 - 40b3cd: 49 8b 7f 18 mov 0x18(%r15),%rdi - 40b3d1: e8 3a a8 ff ff callq 405c10 <__gettext_free_exp> - 40b3d6: 49 8b 47 10 mov 0x10(%r15),%rax - 40b3da: 48 85 c0 test %rax,%rax - 40b3dd: 74 25 je 40b404 - 40b3df: 8b 10 mov (%rax),%edx - 40b3e1: 83 fa 02 cmp $0x2,%edx - 40b3e4: 0f 84 a7 1a 00 00 je 40ce91 - 40b3ea: 83 fa 03 cmp $0x3,%edx - 40b3ed: 0f 84 8d 1a 00 00 je 40ce80 - 40b3f3: 83 fa 01 cmp $0x1,%edx - 40b3f6: 0f 84 a6 1a 00 00 je 40cea2 - 40b3fc: 48 89 c7 mov %rax,%rdi - 40b3ff: e8 ac 29 01 00 callq 41ddb0 <__cfree> - 40b404: 49 8b 47 08 mov 0x8(%r15),%rax - 40b408: 48 85 c0 test %rax,%rax - 40b40b: 0f 84 c1 ea ff ff je 409ed2 - 40b411: 8b 10 mov (%rax),%edx - 40b413: 83 fa 02 cmp $0x2,%edx - 40b416: 0f 84 35 0f 00 00 je 40c351 - 40b41c: 83 fa 03 cmp $0x3,%edx - 40b41f: 0f 84 1b 0f 00 00 je 40c340 - 40b425: 83 fa 01 cmp $0x1,%edx - 40b428: 0f 84 34 0f 00 00 je 40c362 - 40b42e: 48 89 c7 mov %rax,%rdi - 40b431: e8 7a 29 01 00 callq 41ddb0 <__cfree> - 40b436: e9 97 ea ff ff jmpq 409ed2 - 40b43b: 49 8b 7f 18 mov 0x18(%r15),%rdi - 40b43f: e8 cc a7 ff ff callq 405c10 <__gettext_free_exp> - 40b444: 49 8b 47 10 mov 0x10(%r15),%rax - 40b448: 48 85 c0 test %rax,%rax - 40b44b: 74 25 je 40b472 - 40b44d: 8b 10 mov (%rax),%edx - 40b44f: 83 fa 02 cmp $0x2,%edx - 40b452: 0f 84 14 1d 00 00 je 40d16c - 40b458: 83 fa 03 cmp $0x3,%edx - 40b45b: 0f 84 fa 1c 00 00 je 40d15b - 40b461: 83 fa 01 cmp $0x1,%edx - 40b464: 0f 84 13 1d 00 00 je 40d17d - 40b46a: 48 89 c7 mov %rax,%rdi - 40b46d: e8 3e 29 01 00 callq 41ddb0 <__cfree> - 40b472: 49 8b 47 08 mov 0x8(%r15),%rax - 40b476: 48 85 c0 test %rax,%rax - 40b479: 0f 84 12 f0 ff ff je 40a491 - 40b47f: 8b 10 mov (%rax),%edx - 40b481: 83 fa 02 cmp $0x2,%edx - 40b484: 0f 84 05 0e 00 00 je 40c28f - 40b48a: 83 fa 03 cmp $0x3,%edx - 40b48d: 0f 84 eb 0d 00 00 je 40c27e - 40b493: 83 fa 01 cmp $0x1,%edx - 40b496: 0f 84 04 0e 00 00 je 40c2a0 - 40b49c: 48 89 c7 mov %rax,%rdi - 40b49f: e8 0c 29 01 00 callq 41ddb0 <__cfree> - 40b4a4: e9 e8 ef ff ff jmpq 40a491 - 40b4a9: 49 8b 7f 18 mov 0x18(%r15),%rdi - 40b4ad: e8 5e a7 ff ff callq 405c10 <__gettext_free_exp> - 40b4b2: 49 8b 47 10 mov 0x10(%r15),%rax - 40b4b6: 48 85 c0 test %rax,%rax - 40b4b9: 74 25 je 40b4e0 - 40b4bb: 8b 10 mov (%rax),%edx - 40b4bd: 83 fa 02 cmp $0x2,%edx - 40b4c0: 0f 84 6e 1c 00 00 je 40d134 - 40b4c6: 83 fa 03 cmp $0x3,%edx - 40b4c9: 0f 84 54 1c 00 00 je 40d123 - 40b4cf: 83 fa 01 cmp $0x1,%edx - 40b4d2: 0f 84 6d 1c 00 00 je 40d145 - 40b4d8: 48 89 c7 mov %rax,%rdi - 40b4db: e8 d0 28 01 00 callq 41ddb0 <__cfree> - 40b4e0: 49 8b 47 08 mov 0x8(%r15),%rax - 40b4e4: 48 85 c0 test %rax,%rax - 40b4e7: 0f 84 ca ed ff ff je 40a2b7 - 40b4ed: 8b 10 mov (%rax),%edx - 40b4ef: 83 fa 02 cmp $0x2,%edx - 40b4f2: 0f 84 1b 0f 00 00 je 40c413 - 40b4f8: 83 fa 03 cmp $0x3,%edx - 40b4fb: 0f 84 01 0f 00 00 je 40c402 - 40b501: 83 fa 01 cmp $0x1,%edx - 40b504: 0f 84 1a 0f 00 00 je 40c424 - 40b50a: 48 89 c7 mov %rax,%rdi - 40b50d: e8 9e 28 01 00 callq 41ddb0 <__cfree> - 40b512: e9 a0 ed ff ff jmpq 40a2b7 - 40b517: 49 8b 7f 18 mov 0x18(%r15),%rdi - 40b51b: e8 f0 a6 ff ff callq 405c10 <__gettext_free_exp> - 40b520: 49 8b 47 10 mov 0x10(%r15),%rax - 40b524: 48 85 c0 test %rax,%rax - 40b527: 74 25 je 40b54e - 40b529: 8b 10 mov (%rax),%edx - 40b52b: 83 fa 02 cmp $0x2,%edx - 40b52e: 0f 84 25 19 00 00 je 40ce59 - 40b534: 83 fa 03 cmp $0x3,%edx - 40b537: 0f 84 0b 19 00 00 je 40ce48 - 40b53d: 83 fa 01 cmp $0x1,%edx - 40b540: 0f 84 24 19 00 00 je 40ce6a - 40b546: 48 89 c7 mov %rax,%rdi - 40b549: e8 62 28 01 00 callq 41ddb0 <__cfree> - 40b54e: 49 8b 47 08 mov 0x8(%r15),%rax - 40b552: 48 85 c0 test %rax,%rax - 40b555: 0f 84 1b f3 ff ff je 40a876 - 40b55b: 8b 10 mov (%rax),%edx - 40b55d: 83 fa 02 cmp $0x2,%edx - 40b560: 0f 84 8a 0d 00 00 je 40c2f0 - 40b566: 83 fa 03 cmp $0x3,%edx - 40b569: 0f 84 70 0d 00 00 je 40c2df - 40b56f: 83 fa 01 cmp $0x1,%edx - 40b572: 0f 84 89 0d 00 00 je 40c301 - 40b578: 48 89 c7 mov %rax,%rdi - 40b57b: e8 30 28 01 00 callq 41ddb0 <__cfree> - 40b580: e9 f1 f2 ff ff jmpq 40a876 - 40b585: 49 8b 7f 18 mov 0x18(%r15),%rdi - 40b589: e8 82 a6 ff ff callq 405c10 <__gettext_free_exp> - 40b58e: 49 8b 47 10 mov 0x10(%r15),%rax - 40b592: 48 85 c0 test %rax,%rax - 40b595: 74 25 je 40b5bc - 40b597: 8b 10 mov (%rax),%edx - 40b599: 83 fa 02 cmp $0x2,%edx - 40b59c: 0f 84 27 19 00 00 je 40cec9 - 40b5a2: 83 fa 03 cmp $0x3,%edx - 40b5a5: 0f 84 0d 19 00 00 je 40ceb8 - 40b5ab: 83 fa 01 cmp $0x1,%edx - 40b5ae: 0f 84 26 19 00 00 je 40ceda - 40b5b4: 48 89 c7 mov %rax,%rdi - 40b5b7: e8 f4 27 01 00 callq 41ddb0 <__cfree> - 40b5bc: 49 8b 47 08 mov 0x8(%r15),%rax - 40b5c0: 48 85 c0 test %rax,%rax - 40b5c3: 48 89 04 24 mov %rax,(%rsp) - 40b5c7: 0f 84 aa ea ff ff je 40a077 - 40b5cd: 8b 00 mov (%rax),%eax - 40b5cf: 83 f8 02 cmp $0x2,%eax - 40b5d2: 0f 84 cd 19 00 00 je 40cfa5 - 40b5d8: 83 f8 03 cmp $0x3,%eax - 40b5db: 0f 84 b7 19 00 00 je 40cf98 - 40b5e1: 83 f8 01 cmp $0x1,%eax - 40b5e4: 0f 84 ba 0e 00 00 je 40c4a4 - 40b5ea: 48 8b 3c 24 mov (%rsp),%rdi - 40b5ee: e8 bd 27 01 00 callq 41ddb0 <__cfree> - 40b5f3: e9 7f ea ff ff jmpq 40a077 - 40b5f8: 48 8b 78 18 mov 0x18(%rax),%rdi - 40b5fc: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40b601: e8 0a a6 ff ff callq 405c10 <__gettext_free_exp> - 40b606: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40b60b: 48 8b 78 10 mov 0x10(%rax),%rdi - 40b60f: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40b614: e8 f7 a5 ff ff callq 405c10 <__gettext_free_exp> - 40b619: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40b61e: 48 8b 78 08 mov 0x8(%rax),%rdi - 40b622: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40b627: e8 e4 a5 ff ff callq 405c10 <__gettext_free_exp> - 40b62c: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40b631: e9 7b e6 ff ff jmpq 409cb1 - 40b636: 48 8b 78 18 mov 0x18(%rax),%rdi - 40b63a: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40b63f: e8 cc a5 ff ff callq 405c10 <__gettext_free_exp> - 40b644: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40b649: 48 8b 78 10 mov 0x10(%rax),%rdi - 40b64d: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40b652: e8 b9 a5 ff ff callq 405c10 <__gettext_free_exp> - 40b657: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40b65c: 48 8b 78 08 mov 0x8(%rax),%rdi - 40b660: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40b665: e8 a6 a5 ff ff callq 405c10 <__gettext_free_exp> - 40b66a: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40b66f: e9 ad f8 ff ff jmpq 40af21 - 40b674: 48 8b 78 18 mov 0x18(%rax),%rdi - 40b678: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40b67d: e8 8e a5 ff ff callq 405c10 <__gettext_free_exp> - 40b682: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40b687: 48 8b 78 10 mov 0x10(%rax),%rdi - 40b68b: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40b690: e8 7b a5 ff ff callq 405c10 <__gettext_free_exp> - 40b695: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40b69a: 48 8b 78 08 mov 0x8(%rax),%rdi - 40b69e: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40b6a3: e8 68 a5 ff ff callq 405c10 <__gettext_free_exp> - 40b6a8: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40b6ad: e9 af fa ff ff jmpq 40b161 - 40b6b2: 48 8b 78 18 mov 0x18(%rax),%rdi - 40b6b6: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40b6bb: e8 50 a5 ff ff callq 405c10 <__gettext_free_exp> - 40b6c0: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40b6c5: 48 8b 78 10 mov 0x10(%rax),%rdi - 40b6c9: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40b6ce: e8 3d a5 ff ff callq 405c10 <__gettext_free_exp> - 40b6d3: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40b6d8: 48 8b 78 08 mov 0x8(%rax),%rdi - 40b6dc: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40b6e1: e8 2a a5 ff ff callq 405c10 <__gettext_free_exp> - 40b6e6: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40b6eb: e9 51 f9 ff ff jmpq 40b041 - 40b6f0: 48 8b 78 18 mov 0x18(%rax),%rdi - 40b6f4: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40b6f9: e8 12 a5 ff ff callq 405c10 <__gettext_free_exp> - 40b6fe: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40b703: 48 8b 78 10 mov 0x10(%rax),%rdi - 40b707: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40b70c: e8 ff a4 ff ff callq 405c10 <__gettext_free_exp> - 40b711: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40b716: 48 8b 78 08 mov 0x8(%rax),%rdi - 40b71a: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40b71f: e8 ec a4 ff ff callq 405c10 <__gettext_free_exp> - 40b724: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40b729: e9 6e f6 ff ff jmpq 40ad9c - 40b72e: 48 8b 78 18 mov 0x18(%rax),%rdi - 40b732: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40b737: e8 d4 a4 ff ff callq 405c10 <__gettext_free_exp> - 40b73c: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40b741: 48 8b 78 10 mov 0x10(%rax),%rdi - 40b745: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40b74a: e8 c1 a4 ff ff callq 405c10 <__gettext_free_exp> - 40b74f: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40b754: 48 8b 78 08 mov 0x8(%rax),%rdi - 40b758: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40b75d: e8 ae a4 ff ff callq 405c10 <__gettext_free_exp> - 40b762: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40b767: e9 50 f5 ff ff jmpq 40acbc - 40b76c: 48 8b 78 18 mov 0x18(%rax),%rdi - 40b770: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40b775: e8 96 a4 ff ff callq 405c10 <__gettext_free_exp> - 40b77a: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40b77f: 48 8b 78 10 mov 0x10(%rax),%rdi - 40b783: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40b788: e8 83 a4 ff ff callq 405c10 <__gettext_free_exp> - 40b78d: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40b792: 48 8b 78 08 mov 0x8(%rax),%rdi - 40b796: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40b79b: e8 70 a4 ff ff callq 405c10 <__gettext_free_exp> - 40b7a0: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40b7a5: e9 32 f4 ff ff jmpq 40abdc - 40b7aa: 48 8b 78 18 mov 0x18(%rax),%rdi - 40b7ae: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40b7b3: e8 58 a4 ff ff callq 405c10 <__gettext_free_exp> - 40b7b8: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40b7bd: 48 8b 78 10 mov 0x10(%rax),%rdi - 40b7c1: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40b7c6: e8 45 a4 ff ff callq 405c10 <__gettext_free_exp> - 40b7cb: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40b7d0: 48 8b 78 08 mov 0x8(%rax),%rdi - 40b7d4: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40b7d9: e8 32 a4 ff ff callq 405c10 <__gettext_free_exp> - 40b7de: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40b7e3: e9 71 e9 ff ff jmpq 40a159 - 40b7e8: 48 8b 78 18 mov 0x18(%rax),%rdi - 40b7ec: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40b7f1: e8 1a a4 ff ff callq 405c10 <__gettext_free_exp> - 40b7f6: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40b7fb: 48 8b 78 10 mov 0x10(%rax),%rdi - 40b7ff: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40b804: e8 07 a4 ff ff callq 405c10 <__gettext_free_exp> - 40b809: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40b80e: 48 8b 78 08 mov 0x8(%rax),%rdi - 40b812: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40b817: e8 f4 a3 ff ff callq 405c10 <__gettext_free_exp> - 40b81c: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40b821: e9 9d eb ff ff jmpq 40a3c3 - 40b826: 48 8b 78 18 mov 0x18(%rax),%rdi - 40b82a: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40b82f: e8 dc a3 ff ff callq 405c10 <__gettext_free_exp> - 40b834: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40b839: 48 8b 78 10 mov 0x10(%rax),%rdi - 40b83d: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40b842: e8 c9 a3 ff ff callq 405c10 <__gettext_free_exp> - 40b847: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40b84c: 48 8b 78 08 mov 0x8(%rax),%rdi - 40b850: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40b855: e8 b6 a3 ff ff callq 405c10 <__gettext_free_exp> - 40b85a: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40b85f: e9 98 f2 ff ff jmpq 40aafc - 40b864: 48 8b 04 24 mov (%rsp),%rax - 40b868: 48 8b 78 18 mov 0x18(%rax),%rdi - 40b86c: e8 9f a3 ff ff callq 405c10 <__gettext_free_exp> - 40b871: 48 8b 04 24 mov (%rsp),%rax - 40b875: 48 8b 40 10 mov 0x10(%rax),%rax - 40b879: 48 85 c0 test %rax,%rax - 40b87c: 74 25 je 40b8a3 - 40b87e: 8b 10 mov (%rax),%edx - 40b880: 83 fa 02 cmp $0x2,%edx - 40b883: 0f 84 d0 07 00 00 je 40c059 - 40b889: 83 fa 03 cmp $0x3,%edx - 40b88c: 0f 84 b4 07 00 00 je 40c046 - 40b892: 83 fa 01 cmp $0x1,%edx - 40b895: 0f 84 d1 07 00 00 je 40c06c - 40b89b: 48 89 c7 mov %rax,%rdi - 40b89e: e8 0d 25 01 00 callq 41ddb0 <__cfree> - 40b8a3: 48 8b 04 24 mov (%rsp),%rax - 40b8a7: 48 8b 40 08 mov 0x8(%rax),%rax - 40b8ab: 48 85 c0 test %rax,%rax - 40b8ae: 0f 84 e4 f6 ff ff je 40af98 - 40b8b4: 8b 10 mov (%rax),%edx - 40b8b6: 83 fa 02 cmp $0x2,%edx - 40b8b9: 0f 84 ed 0c 00 00 je 40c5ac - 40b8bf: 83 fa 03 cmp $0x3,%edx - 40b8c2: 0f 84 d1 0c 00 00 je 40c599 - 40b8c8: 83 fa 01 cmp $0x1,%edx - 40b8cb: 0f 84 ee 0c 00 00 je 40c5bf - 40b8d1: 48 89 c7 mov %rax,%rdi - 40b8d4: e8 d7 24 01 00 callq 41ddb0 <__cfree> - 40b8d9: e9 ba f6 ff ff jmpq 40af98 - 40b8de: 48 8b 04 24 mov (%rsp),%rax - 40b8e2: 48 8b 78 18 mov 0x18(%rax),%rdi - 40b8e6: e8 25 a3 ff ff callq 405c10 <__gettext_free_exp> - 40b8eb: 48 8b 04 24 mov (%rsp),%rax - 40b8ef: 48 8b 40 10 mov 0x10(%rax),%rax - 40b8f3: 48 85 c0 test %rax,%rax - 40b8f6: 74 25 je 40b91d - 40b8f8: 8b 10 mov (%rax),%edx - 40b8fa: 83 fa 02 cmp $0x2,%edx - 40b8fd: 0f 84 fa 07 00 00 je 40c0fd - 40b903: 83 fa 03 cmp $0x3,%edx - 40b906: 0f 84 de 07 00 00 je 40c0ea - 40b90c: 83 fa 01 cmp $0x1,%edx - 40b90f: 0f 84 fb 07 00 00 je 40c110 - 40b915: 48 89 c7 mov %rax,%rdi - 40b918: e8 93 24 01 00 callq 41ddb0 <__cfree> - 40b91d: 48 8b 04 24 mov (%rsp),%rax - 40b921: 48 8b 40 08 mov 0x8(%rax),%rax - 40b925: 48 85 c0 test %rax,%rax - 40b928: 0f 84 6b e4 ff ff je 409d99 - 40b92e: 8b 10 mov (%rax),%edx - 40b930: 83 fa 02 cmp $0x2,%edx - 40b933: 0f 84 b9 0b 00 00 je 40c4f2 - 40b939: 83 fa 03 cmp $0x3,%edx - 40b93c: 0f 84 9d 0b 00 00 je 40c4df - 40b942: 83 fa 01 cmp $0x1,%edx - 40b945: 0f 84 ba 0b 00 00 je 40c505 - 40b94b: 48 89 c7 mov %rax,%rdi - 40b94e: e8 5d 24 01 00 callq 41ddb0 <__cfree> - 40b953: e9 41 e4 ff ff jmpq 409d99 - 40b958: 48 8b 04 24 mov (%rsp),%rax - 40b95c: 48 8b 78 18 mov 0x18(%rax),%rdi - 40b960: e8 ab a2 ff ff callq 405c10 <__gettext_free_exp> - 40b965: 48 8b 04 24 mov (%rsp),%rax - 40b969: 48 8b 40 10 mov 0x10(%rax),%rax - 40b96d: 48 85 c0 test %rax,%rax - 40b970: 74 25 je 40b997 - 40b972: 8b 10 mov (%rax),%edx - 40b974: 83 fa 02 cmp $0x2,%edx - 40b977: 0f 84 9e 06 00 00 je 40c01b - 40b97d: 83 fa 03 cmp $0x3,%edx - 40b980: 0f 84 82 06 00 00 je 40c008 - 40b986: 83 fa 01 cmp $0x1,%edx - 40b989: 0f 84 9f 06 00 00 je 40c02e - 40b98f: 48 89 c7 mov %rax,%rdi - 40b992: e8 19 24 01 00 callq 41ddb0 <__cfree> - 40b997: 48 8b 04 24 mov (%rsp),%rax - 40b99b: 48 8b 40 08 mov 0x8(%rax),%rax - 40b99f: 48 85 c0 test %rax,%rax - 40b9a2: 0f 84 d0 f4 ff ff je 40ae78 - 40b9a8: 8b 10 mov (%rax),%edx - 40b9aa: 83 fa 02 cmp $0x2,%edx - 40b9ad: 0f 84 7d 0b 00 00 je 40c530 - 40b9b3: 83 fa 03 cmp $0x3,%edx - 40b9b6: 0f 84 61 0b 00 00 je 40c51d - 40b9bc: 83 fa 01 cmp $0x1,%edx - 40b9bf: 0f 84 7e 0b 00 00 je 40c543 - 40b9c5: 48 89 c7 mov %rax,%rdi - 40b9c8: e8 e3 23 01 00 callq 41ddb0 <__cfree> - 40b9cd: e9 a6 f4 ff ff jmpq 40ae78 - 40b9d2: 48 8b 04 24 mov (%rsp),%rax - 40b9d6: 48 8b 78 18 mov 0x18(%rax),%rdi - 40b9da: e8 31 a2 ff ff callq 405c10 <__gettext_free_exp> - 40b9df: 48 8b 04 24 mov (%rsp),%rax - 40b9e3: 48 8b 40 10 mov 0x10(%rax),%rax - 40b9e7: 48 85 c0 test %rax,%rax - 40b9ea: 74 25 je 40ba11 - 40b9ec: 8b 10 mov (%rax),%edx - 40b9ee: 83 fa 02 cmp $0x2,%edx - 40b9f1: 0f 84 44 07 00 00 je 40c13b - 40b9f7: 83 fa 03 cmp $0x3,%edx - 40b9fa: 0f 84 28 07 00 00 je 40c128 - 40ba00: 83 fa 01 cmp $0x1,%edx - 40ba03: 0f 84 45 07 00 00 je 40c14e - 40ba09: 48 89 c7 mov %rax,%rdi - 40ba0c: e8 9f 23 01 00 callq 41ddb0 <__cfree> - 40ba11: 48 8b 04 24 mov (%rsp),%rax - 40ba15: 48 8b 40 08 mov 0x8(%rax),%rax - 40ba19: 48 85 c0 test %rax,%rax - 40ba1c: 0f 84 96 f6 ff ff je 40b0b8 - 40ba22: 8b 10 mov (%rax),%edx - 40ba24: 83 fa 02 cmp $0x2,%edx - 40ba27: 0f 84 41 0b 00 00 je 40c56e - 40ba2d: 83 fa 03 cmp $0x3,%edx - 40ba30: 0f 84 25 0b 00 00 je 40c55b - 40ba36: 83 fa 01 cmp $0x1,%edx - 40ba39: 0f 84 42 0b 00 00 je 40c581 - 40ba3f: 48 89 c7 mov %rax,%rdi - 40ba42: e8 69 23 01 00 callq 41ddb0 <__cfree> - 40ba47: e9 6c f6 ff ff jmpq 40b0b8 - 40ba4c: 49 8b 7e 18 mov 0x18(%r14),%rdi - 40ba50: e8 bb a1 ff ff callq 405c10 <__gettext_free_exp> - 40ba55: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 40ba59: 4d 85 ff test %r15,%r15 - 40ba5c: 74 26 je 40ba84 - 40ba5e: 41 8b 07 mov (%r15),%eax - 40ba61: 83 f8 02 cmp $0x2,%eax - 40ba64: 0f 84 05 07 00 00 je 40c16f - 40ba6a: 83 f8 03 cmp $0x3,%eax - 40ba6d: 0f 84 f3 06 00 00 je 40c166 - 40ba73: 83 f8 01 cmp $0x1,%eax - 40ba76: 0f 84 fc 06 00 00 je 40c178 - 40ba7c: 4c 89 ff mov %r15,%rdi - 40ba7f: e8 2c 23 01 00 callq 41ddb0 <__cfree> - 40ba84: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 40ba88: 4d 85 ff test %r15,%r15 - 40ba8b: 0f 84 b6 ea ff ff je 40a547 - 40ba91: 41 8b 07 mov (%r15),%eax - 40ba94: 83 f8 02 cmp $0x2,%eax - 40ba97: 0f 84 bd 0c 00 00 je 40c75a - 40ba9d: 83 f8 03 cmp $0x3,%eax - 40baa0: 0f 84 ab 0c 00 00 je 40c751 - 40baa6: 83 f8 01 cmp $0x1,%eax - 40baa9: 0f 84 b4 0c 00 00 je 40c763 - 40baaf: 4c 89 ff mov %r15,%rdi - 40bab2: e8 f9 22 01 00 callq 41ddb0 <__cfree> - 40bab7: e9 8b ea ff ff jmpq 40a547 - 40babc: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 40bac0: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40bac5: 48 89 14 24 mov %rdx,(%rsp) - 40bac9: e8 42 a1 ff ff callq 405c10 <__gettext_free_exp> - 40bace: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40bad3: 48 8b 14 24 mov (%rsp),%rdx - 40bad7: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 40badb: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40bae0: 48 89 14 24 mov %rdx,(%rsp) - 40bae4: e8 27 a1 ff ff callq 405c10 <__gettext_free_exp> - 40bae9: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40baee: 48 8b 14 24 mov (%rsp),%rdx - 40baf2: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 40baf6: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40bafb: 48 89 14 24 mov %rdx,(%rsp) - 40baff: e8 0c a1 ff ff callq 405c10 <__gettext_free_exp> - 40bb04: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40bb09: 48 8b 14 24 mov (%rsp),%rdx - 40bb0d: e9 fc ea ff ff jmpq 40a60e - 40bb12: 48 8b 78 18 mov 0x18(%rax),%rdi - 40bb16: 48 89 04 24 mov %rax,(%rsp) - 40bb1a: e8 f1 a0 ff ff callq 405c10 <__gettext_free_exp> - 40bb1f: 48 8b 04 24 mov (%rsp),%rax - 40bb23: 48 8b 78 10 mov 0x10(%rax),%rdi - 40bb27: 48 89 04 24 mov %rax,(%rsp) - 40bb2b: e8 e0 a0 ff ff callq 405c10 <__gettext_free_exp> - 40bb30: 48 8b 04 24 mov (%rsp),%rax - 40bb34: 48 8b 50 08 mov 0x8(%rax),%rdx - 40bb38: 48 85 d2 test %rdx,%rdx - 40bb3b: 0f 84 ce e6 ff ff je 40a20f - 40bb41: 8b 0a mov (%rdx),%ecx - 40bb43: 83 f9 02 cmp $0x2,%ecx - 40bb46: 0f 84 33 12 00 00 je 40cd7f - 40bb4c: 83 f9 03 cmp $0x3,%ecx - 40bb4f: 0f 84 0f 12 00 00 je 40cd64 - 40bb55: 83 f9 01 cmp $0x1,%ecx - 40bb58: 0f 84 3c 12 00 00 je 40cd9a - 40bb5e: 48 89 d7 mov %rdx,%rdi - 40bb61: 48 89 04 24 mov %rax,(%rsp) - 40bb65: e8 46 22 01 00 callq 41ddb0 <__cfree> - 40bb6a: 48 8b 04 24 mov (%rsp),%rax - 40bb6e: e9 9c e6 ff ff jmpq 40a20f - 40bb73: 48 8b 78 18 mov 0x18(%rax),%rdi - 40bb77: 48 89 04 24 mov %rax,(%rsp) - 40bb7b: e8 90 a0 ff ff callq 405c10 <__gettext_free_exp> - 40bb80: 48 8b 04 24 mov (%rsp),%rax - 40bb84: 48 8b 78 10 mov 0x10(%rax),%rdi - 40bb88: 48 89 04 24 mov %rax,(%rsp) - 40bb8c: e8 7f a0 ff ff callq 405c10 <__gettext_free_exp> - 40bb91: 48 8b 04 24 mov (%rsp),%rax - 40bb95: 48 8b 50 08 mov 0x8(%rax),%rdx - 40bb99: 48 85 d2 test %rdx,%rdx - 40bb9c: 0f 84 e4 ea ff ff je 40a686 - 40bba2: 8b 0a mov (%rdx),%ecx - 40bba4: 83 f9 02 cmp $0x2,%ecx - 40bba7: 0f 84 e8 10 00 00 je 40cc95 - 40bbad: 83 f9 03 cmp $0x3,%ecx - 40bbb0: 0f 84 c4 10 00 00 je 40cc7a - 40bbb6: 83 f9 01 cmp $0x1,%ecx - 40bbb9: 0f 84 f1 10 00 00 je 40ccb0 - 40bbbf: 48 89 d7 mov %rdx,%rdi - 40bbc2: 48 89 04 24 mov %rax,(%rsp) - 40bbc6: e8 e5 21 01 00 callq 41ddb0 <__cfree> - 40bbcb: 48 8b 04 24 mov (%rsp),%rax - 40bbcf: e9 b2 ea ff ff jmpq 40a686 - 40bbd4: 48 8b 78 18 mov 0x18(%rax),%rdi - 40bbd8: 48 89 04 24 mov %rax,(%rsp) - 40bbdc: e8 2f a0 ff ff callq 405c10 <__gettext_free_exp> - 40bbe1: 48 8b 04 24 mov (%rsp),%rax - 40bbe5: 48 8b 78 10 mov 0x10(%rax),%rdi - 40bbe9: 48 89 04 24 mov %rax,(%rsp) - 40bbed: e8 1e a0 ff ff callq 405c10 <__gettext_free_exp> - 40bbf2: 48 8b 04 24 mov (%rsp),%rax - 40bbf6: 48 8b 50 08 mov 0x8(%rax),%rdx - 40bbfa: 48 85 d2 test %rdx,%rdx - 40bbfd: 0f 84 0c ed ff ff je 40a90f - 40bc03: 8b 0a mov (%rdx),%ecx - 40bc05: 83 f9 02 cmp $0x2,%ecx - 40bc08: 0f 84 93 0c 00 00 je 40c8a1 - 40bc0e: 83 f9 03 cmp $0x3,%ecx - 40bc11: 0f 84 6f 0c 00 00 je 40c886 - 40bc17: 83 f9 01 cmp $0x1,%ecx - 40bc1a: 0f 84 9c 0c 00 00 je 40c8bc - 40bc20: 48 89 d7 mov %rdx,%rdi - 40bc23: 48 89 04 24 mov %rax,(%rsp) - 40bc27: e8 84 21 01 00 callq 41ddb0 <__cfree> - 40bc2c: 48 8b 04 24 mov (%rsp),%rax - 40bc30: e9 da ec ff ff jmpq 40a90f - 40bc35: 48 8b 78 18 mov 0x18(%rax),%rdi - 40bc39: 48 89 04 24 mov %rax,(%rsp) - 40bc3d: e8 ce 9f ff ff callq 405c10 <__gettext_free_exp> - 40bc42: 48 8b 04 24 mov (%rsp),%rax - 40bc46: 48 8b 78 10 mov 0x10(%rax),%rdi - 40bc4a: 48 89 04 24 mov %rax,(%rsp) - 40bc4e: e8 bd 9f ff ff callq 405c10 <__gettext_free_exp> - 40bc53: 48 8b 04 24 mov (%rsp),%rax - 40bc57: 48 8b 50 08 mov 0x8(%rax),%rdx - 40bc5b: 48 85 d2 test %rdx,%rdx - 40bc5e: 0f 84 eb ed ff ff je 40aa4f - 40bc64: 8b 0a mov (%rdx),%ecx - 40bc66: 83 f9 02 cmp $0x2,%ecx - 40bc69: 0f 84 7c 10 00 00 je 40cceb - 40bc6f: 83 f9 03 cmp $0x3,%ecx - 40bc72: 0f 84 58 10 00 00 je 40ccd0 - 40bc78: 83 f9 01 cmp $0x1,%ecx - 40bc7b: 0f 84 85 10 00 00 je 40cd06 - 40bc81: 48 89 d7 mov %rdx,%rdi - 40bc84: 48 89 04 24 mov %rax,(%rsp) - 40bc88: e8 23 21 01 00 callq 41ddb0 <__cfree> - 40bc8d: 48 8b 04 24 mov (%rsp),%rax - 40bc91: e9 b9 ed ff ff jmpq 40aa4f - 40bc96: 48 8b 78 18 mov 0x18(%rax),%rdi - 40bc9a: 48 89 04 24 mov %rax,(%rsp) - 40bc9e: e8 6d 9f ff ff callq 405c10 <__gettext_free_exp> - 40bca3: 48 8b 04 24 mov (%rsp),%rax - 40bca7: 48 8b 78 10 mov 0x10(%rax),%rdi - 40bcab: 48 89 04 24 mov %rax,(%rsp) - 40bcaf: e8 5c 9f ff ff callq 405c10 <__gettext_free_exp> - 40bcb4: 48 8b 04 24 mov (%rsp),%rax - 40bcb8: 48 8b 50 08 mov 0x8(%rax),%rdx - 40bcbc: 48 85 d2 test %rdx,%rdx - 40bcbf: 0f 84 a1 ea ff ff je 40a766 - 40bcc5: 8b 0a mov (%rdx),%ecx - 40bcc7: 83 f9 02 cmp $0x2,%ecx - 40bcca: 0f 84 f9 0c 00 00 je 40c9c9 - 40bcd0: 83 f9 03 cmp $0x3,%ecx - 40bcd3: 0f 84 d5 0c 00 00 je 40c9ae - 40bcd9: 83 f9 01 cmp $0x1,%ecx - 40bcdc: 0f 84 02 0d 00 00 je 40c9e4 - 40bce2: 48 89 d7 mov %rdx,%rdi - 40bce5: 48 89 04 24 mov %rax,(%rsp) - 40bce9: e8 c2 20 01 00 callq 41ddb0 <__cfree> - 40bcee: 48 8b 04 24 mov (%rsp),%rax - 40bcf2: e9 6f ea ff ff jmpq 40a766 - 40bcf7: 48 8b 78 18 mov 0x18(%rax),%rdi - 40bcfb: 48 89 04 24 mov %rax,(%rsp) - 40bcff: e8 0c 9f ff ff callq 405c10 <__gettext_free_exp> - 40bd04: 48 8b 04 24 mov (%rsp),%rax - 40bd08: 48 8b 78 10 mov 0x10(%rax),%rdi - 40bd0c: 48 89 04 24 mov %rax,(%rsp) - 40bd10: e8 fb 9e ff ff callq 405c10 <__gettext_free_exp> - 40bd15: 48 8b 04 24 mov (%rsp),%rax - 40bd19: 48 8b 50 08 mov 0x8(%rax),%rdx - 40bd1d: 48 85 d2 test %rdx,%rdx - 40bd20: 0f 84 d0 e9 ff ff je 40a6f6 - 40bd26: 8b 0a mov (%rdx),%ecx - 40bd28: 83 f9 02 cmp $0x2,%ecx - 40bd2b: 0f 84 0e 0f 00 00 je 40cc3f - 40bd31: 83 f9 03 cmp $0x3,%ecx - 40bd34: 0f 84 ea 0e 00 00 je 40cc24 - 40bd3a: 83 f9 01 cmp $0x1,%ecx - 40bd3d: 0f 84 17 0f 00 00 je 40cc5a - 40bd43: 48 89 d7 mov %rdx,%rdi - 40bd46: 48 89 04 24 mov %rax,(%rsp) - 40bd4a: e8 61 20 01 00 callq 41ddb0 <__cfree> - 40bd4f: 48 8b 04 24 mov (%rsp),%rax - 40bd53: e9 9e e9 ff ff jmpq 40a6f6 - 40bd58: 49 8b 7f 18 mov 0x18(%r15),%rdi - 40bd5c: e8 af 9e ff ff callq 405c10 <__gettext_free_exp> - 40bd61: 49 8b 7f 10 mov 0x10(%r15),%rdi - 40bd65: e8 a6 9e ff ff callq 405c10 <__gettext_free_exp> - 40bd6a: 49 8b 47 08 mov 0x8(%r15),%rax - 40bd6e: 48 85 c0 test %rax,%rax - 40bd71: 0f 84 eb e6 ff ff je 40a462 - 40bd77: 8b 10 mov (%rax),%edx - 40bd79: 83 fa 02 cmp $0x2,%edx - 40bd7c: 0f 84 ef 11 00 00 je 40cf71 - 40bd82: 83 fa 03 cmp $0x3,%edx - 40bd85: 0f 84 d5 11 00 00 je 40cf60 - 40bd8b: 83 fa 01 cmp $0x1,%edx - 40bd8e: 0f 84 ee 11 00 00 je 40cf82 - 40bd94: 48 89 c7 mov %rax,%rdi - 40bd97: e8 14 20 01 00 callq 41ddb0 <__cfree> - 40bd9c: e9 c1 e6 ff ff jmpq 40a462 - 40bda1: 49 8b 7f 18 mov 0x18(%r15),%rdi - 40bda5: e8 66 9e ff ff callq 405c10 <__gettext_free_exp> - 40bdaa: 49 8b 7f 10 mov 0x10(%r15),%rdi - 40bdae: e8 5d 9e ff ff callq 405c10 <__gettext_free_exp> - 40bdb3: 49 8b 47 08 mov 0x8(%r15),%rax - 40bdb7: 48 85 c0 test %rax,%rax - 40bdba: 0f 84 e3 e0 ff ff je 409ea3 - 40bdc0: 8b 10 mov (%rax),%edx - 40bdc2: 83 fa 02 cmp $0x2,%edx - 40bdc5: 0f 84 56 10 00 00 je 40ce21 - 40bdcb: 83 fa 03 cmp $0x3,%edx - 40bdce: 0f 84 3c 10 00 00 je 40ce10 - 40bdd4: 83 fa 01 cmp $0x1,%edx - 40bdd7: 0f 84 55 10 00 00 je 40ce32 - 40bddd: 48 89 c7 mov %rax,%rdi - 40bde0: e8 cb 1f 01 00 callq 41ddb0 <__cfree> - 40bde5: e9 b9 e0 ff ff jmpq 409ea3 - 40bdea: 49 8b 7f 18 mov 0x18(%r15),%rdi - 40bdee: e8 1d 9e ff ff callq 405c10 <__gettext_free_exp> - 40bdf3: 49 8b 7f 10 mov 0x10(%r15),%rdi - 40bdf7: e8 14 9e ff ff callq 405c10 <__gettext_free_exp> - 40bdfc: 49 8b 47 08 mov 0x8(%r15),%rax - 40be00: 48 85 c0 test %rax,%rax - 40be03: 0f 84 ce e9 ff ff je 40a7d7 - 40be09: 8b 10 mov (%rax),%edx - 40be0b: 83 fa 02 cmp $0x2,%edx - 40be0e: 0f 84 d5 11 00 00 je 40cfe9 - 40be14: 83 fa 03 cmp $0x3,%edx - 40be17: 0f 84 bb 11 00 00 je 40cfd8 - 40be1d: 83 fa 01 cmp $0x1,%edx - 40be20: 0f 84 d4 11 00 00 je 40cffa - 40be26: 48 89 c7 mov %rax,%rdi - 40be29: e8 82 1f 01 00 callq 41ddb0 <__cfree> - 40be2e: e9 a4 e9 ff ff jmpq 40a7d7 - 40be33: 48 8b 78 18 mov 0x18(%rax),%rdi - 40be37: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40be3c: e8 cf 9d ff ff callq 405c10 <__gettext_free_exp> - 40be41: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40be46: 48 8b 78 10 mov 0x10(%rax),%rdi - 40be4a: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40be4f: e8 bc 9d ff ff callq 405c10 <__gettext_free_exp> - 40be54: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40be59: 48 8b 78 08 mov 0x8(%rax),%rdi - 40be5d: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40be62: e8 a9 9d ff ff callq 405c10 <__gettext_free_exp> - 40be67: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40be6c: e9 20 e5 ff ff jmpq 40a391 - 40be71: 48 8b 78 18 mov 0x18(%rax),%rdi - 40be75: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40be7a: e8 91 9d ff ff callq 405c10 <__gettext_free_exp> - 40be7f: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40be84: 48 8b 78 10 mov 0x10(%rax),%rdi - 40be88: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40be8d: e8 7e 9d ff ff callq 405c10 <__gettext_free_exp> - 40be92: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40be97: 48 8b 78 08 mov 0x8(%rax),%rdi - 40be9b: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40bea0: e8 6b 9d ff ff callq 405c10 <__gettext_free_exp> - 40bea5: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40beaa: e9 78 e2 ff ff jmpq 40a127 - 40beaf: 48 8b 78 18 mov 0x18(%rax),%rdi - 40beb3: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40beb8: e8 53 9d ff ff callq 405c10 <__gettext_free_exp> - 40bebd: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40bec2: 48 8b 78 10 mov 0x10(%rax),%rdi - 40bec6: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40becb: e8 40 9d ff ff callq 405c10 <__gettext_free_exp> - 40bed0: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40bed5: 48 8b 78 08 mov 0x8(%rax),%rdi - 40bed9: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40bede: e8 2d 9d ff ff callq 405c10 <__gettext_free_exp> - 40bee3: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40bee8: e9 02 f0 ff ff jmpq 40aeef - 40beed: 48 8b 78 18 mov 0x18(%rax),%rdi - 40bef1: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40bef6: e8 15 9d ff ff callq 405c10 <__gettext_free_exp> - 40befb: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40bf00: 48 8b 78 10 mov 0x10(%rax),%rdi - 40bf04: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40bf09: e8 02 9d ff ff callq 405c10 <__gettext_free_exp> - 40bf0e: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40bf13: 48 8b 78 08 mov 0x8(%rax),%rdi - 40bf17: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40bf1c: e8 ef 9c ff ff callq 405c10 <__gettext_free_exp> - 40bf21: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40bf26: e9 54 dd ff ff jmpq 409c7f - 40bf2b: 48 8b 78 18 mov 0x18(%rax),%rdi - 40bf2f: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40bf34: e8 d7 9c ff ff callq 405c10 <__gettext_free_exp> - 40bf39: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40bf3e: 48 8b 78 10 mov 0x10(%rax),%rdi - 40bf42: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40bf47: e8 c4 9c ff ff callq 405c10 <__gettext_free_exp> - 40bf4c: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40bf51: 48 8b 78 08 mov 0x8(%rax),%rdi - 40bf55: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40bf5a: e8 b1 9c ff ff callq 405c10 <__gettext_free_exp> - 40bf5f: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40bf64: e9 c6 f1 ff ff jmpq 40b12f - 40bf69: 48 8b 78 18 mov 0x18(%rax),%rdi - 40bf6d: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40bf72: e8 99 9c ff ff callq 405c10 <__gettext_free_exp> - 40bf77: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40bf7c: 48 8b 78 10 mov 0x10(%rax),%rdi - 40bf80: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40bf85: e8 86 9c ff ff callq 405c10 <__gettext_free_exp> - 40bf8a: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40bf8f: 48 8b 78 08 mov 0x8(%rax),%rdi - 40bf93: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40bf98: e8 73 9c ff ff callq 405c10 <__gettext_free_exp> - 40bf9d: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40bfa2: e9 68 f0 ff ff jmpq 40b00f - 40bfa7: 48 8b 78 18 mov 0x18(%rax),%rdi - 40bfab: 48 89 04 24 mov %rax,(%rsp) - 40bfaf: e8 5c 9c ff ff callq 405c10 <__gettext_free_exp> - 40bfb4: 48 8b 04 24 mov (%rsp),%rax - 40bfb8: 48 8b 78 10 mov 0x10(%rax),%rdi - 40bfbc: 48 89 04 24 mov %rax,(%rsp) - 40bfc0: e8 4b 9c ff ff callq 405c10 <__gettext_free_exp> - 40bfc5: 48 8b 04 24 mov (%rsp),%rax - 40bfc9: 48 8b 50 08 mov 0x8(%rax),%rdx - 40bfcd: 48 85 d2 test %rdx,%rdx - 40bfd0: 0f 84 91 dd ff ff je 409d67 - 40bfd6: 8b 0a mov (%rdx),%ecx - 40bfd8: 83 f9 02 cmp $0x2,%ecx - 40bfdb: 0f 84 be 00 00 00 je 40c09f - 40bfe1: 83 f9 03 cmp $0x3,%ecx - 40bfe4: 0f 84 9a 00 00 00 je 40c084 - 40bfea: 83 f9 01 cmp $0x1,%ecx - 40bfed: 0f 84 c7 00 00 00 je 40c0ba - 40bff3: 48 89 d7 mov %rdx,%rdi - 40bff6: 48 89 04 24 mov %rax,(%rsp) - 40bffa: e8 b1 1d 01 00 callq 41ddb0 <__cfree> - 40bfff: 48 8b 04 24 mov (%rsp),%rax - 40c003: e9 5f dd ff ff jmpq 409d67 - 40c008: 48 8b 78 18 mov 0x18(%rax),%rdi - 40c00c: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c011: e8 fa 9b ff ff callq 405c10 <__gettext_free_exp> - 40c016: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c01b: 48 8b 78 10 mov 0x10(%rax),%rdi - 40c01f: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c024: e8 e7 9b ff ff callq 405c10 <__gettext_free_exp> - 40c029: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c02e: 48 8b 78 08 mov 0x8(%rax),%rdi - 40c032: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c037: e8 d4 9b ff ff callq 405c10 <__gettext_free_exp> - 40c03c: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c041: e9 49 f9 ff ff jmpq 40b98f - 40c046: 48 8b 78 18 mov 0x18(%rax),%rdi - 40c04a: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c04f: e8 bc 9b ff ff callq 405c10 <__gettext_free_exp> - 40c054: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c059: 48 8b 78 10 mov 0x10(%rax),%rdi - 40c05d: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c062: e8 a9 9b ff ff callq 405c10 <__gettext_free_exp> - 40c067: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c06c: 48 8b 78 08 mov 0x8(%rax),%rdi - 40c070: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c075: e8 96 9b ff ff callq 405c10 <__gettext_free_exp> - 40c07a: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c07f: e9 17 f8 ff ff jmpq 40b89b - 40c084: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 40c088: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c08d: 48 89 14 24 mov %rdx,(%rsp) - 40c091: e8 7a 9b ff ff callq 405c10 <__gettext_free_exp> - 40c096: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c09b: 48 8b 14 24 mov (%rsp),%rdx - 40c09f: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 40c0a3: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c0a8: 48 89 14 24 mov %rdx,(%rsp) - 40c0ac: e8 5f 9b ff ff callq 405c10 <__gettext_free_exp> - 40c0b1: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c0b6: 48 8b 14 24 mov (%rsp),%rdx - 40c0ba: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 40c0be: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c0c3: 48 89 14 24 mov %rdx,(%rsp) - 40c0c7: e8 44 9b ff ff callq 405c10 <__gettext_free_exp> - 40c0cc: 48 8b 14 24 mov (%rsp),%rdx - 40c0d0: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c0d5: 48 89 d7 mov %rdx,%rdi - 40c0d8: 48 89 04 24 mov %rax,(%rsp) - 40c0dc: e8 cf 1c 01 00 callq 41ddb0 <__cfree> - 40c0e1: 48 8b 04 24 mov (%rsp),%rax - 40c0e5: e9 7d dc ff ff jmpq 409d67 - 40c0ea: 48 8b 78 18 mov 0x18(%rax),%rdi - 40c0ee: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c0f3: e8 18 9b ff ff callq 405c10 <__gettext_free_exp> - 40c0f8: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c0fd: 48 8b 78 10 mov 0x10(%rax),%rdi - 40c101: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c106: e8 05 9b ff ff callq 405c10 <__gettext_free_exp> - 40c10b: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c110: 48 8b 78 08 mov 0x8(%rax),%rdi - 40c114: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c119: e8 f2 9a ff ff callq 405c10 <__gettext_free_exp> - 40c11e: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c123: e9 ed f7 ff ff jmpq 40b915 - 40c128: 48 8b 78 18 mov 0x18(%rax),%rdi - 40c12c: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c131: e8 da 9a ff ff callq 405c10 <__gettext_free_exp> - 40c136: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c13b: 48 8b 78 10 mov 0x10(%rax),%rdi - 40c13f: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c144: e8 c7 9a ff ff callq 405c10 <__gettext_free_exp> - 40c149: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c14e: 48 8b 78 08 mov 0x8(%rax),%rdi - 40c152: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c157: e8 b4 9a ff ff callq 405c10 <__gettext_free_exp> - 40c15c: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c161: e9 a3 f8 ff ff jmpq 40ba09 - 40c166: 49 8b 7f 18 mov 0x18(%r15),%rdi - 40c16a: e8 a1 9a ff ff callq 405c10 <__gettext_free_exp> - 40c16f: 49 8b 7f 10 mov 0x10(%r15),%rdi - 40c173: e8 98 9a ff ff callq 405c10 <__gettext_free_exp> - 40c178: 49 8b 7f 08 mov 0x8(%r15),%rdi - 40c17c: e8 8f 9a ff ff callq 405c10 <__gettext_free_exp> - 40c181: e9 f6 f8 ff ff jmpq 40ba7c - 40c186: 48 8b 78 18 mov 0x18(%rax),%rdi - 40c18a: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c18f: e8 7c 9a ff ff callq 405c10 <__gettext_free_exp> - 40c194: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c199: 48 8b 78 10 mov 0x10(%rax),%rdi - 40c19d: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c1a2: e8 69 9a ff ff callq 405c10 <__gettext_free_exp> - 40c1a7: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c1ac: 48 8b 78 08 mov 0x8(%rax),%rdi - 40c1b0: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c1b5: e8 56 9a ff ff callq 405c10 <__gettext_free_exp> - 40c1ba: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c1bf: e9 20 f0 ff ff jmpq 40b1e4 - 40c1c4: 48 8b 78 18 mov 0x18(%rax),%rdi - 40c1c8: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c1cd: e8 3e 9a ff ff callq 405c10 <__gettext_free_exp> - 40c1d2: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c1d7: 48 8b 78 10 mov 0x10(%rax),%rdi - 40c1db: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c1e0: e8 2b 9a ff ff callq 405c10 <__gettext_free_exp> - 40c1e5: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c1ea: 48 8b 78 08 mov 0x8(%rax),%rdi - 40c1ee: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c1f3: e8 18 9a ff ff callq 405c10 <__gettext_free_exp> - 40c1f8: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c1fd: e9 50 f1 ff ff jmpq 40b352 - 40c202: 48 8b 78 18 mov 0x18(%rax),%rdi - 40c206: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c20b: e8 00 9a ff ff callq 405c10 <__gettext_free_exp> - 40c210: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c215: 48 8b 78 10 mov 0x10(%rax),%rdi - 40c219: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c21e: e8 ed 99 ff ff callq 405c10 <__gettext_free_exp> - 40c223: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c228: 48 8b 78 08 mov 0x8(%rax),%rdi - 40c22c: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c231: e8 da 99 ff ff callq 405c10 <__gettext_free_exp> - 40c236: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c23b: e9 1e f0 ff ff jmpq 40b25e - 40c240: 48 8b 78 18 mov 0x18(%rax),%rdi - 40c244: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c249: e8 c2 99 ff ff callq 405c10 <__gettext_free_exp> - 40c24e: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c253: 48 8b 78 10 mov 0x10(%rax),%rdi - 40c257: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c25c: e8 af 99 ff ff callq 405c10 <__gettext_free_exp> - 40c261: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c266: 48 8b 78 08 mov 0x8(%rax),%rdi - 40c26a: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c26f: e8 9c 99 ff ff callq 405c10 <__gettext_free_exp> - 40c274: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c279: e9 5a f0 ff ff jmpq 40b2d8 - 40c27e: 48 8b 78 18 mov 0x18(%rax),%rdi - 40c282: 48 89 04 24 mov %rax,(%rsp) - 40c286: e8 85 99 ff ff callq 405c10 <__gettext_free_exp> - 40c28b: 48 8b 04 24 mov (%rsp),%rax - 40c28f: 48 8b 78 10 mov 0x10(%rax),%rdi - 40c293: 48 89 04 24 mov %rax,(%rsp) - 40c297: e8 74 99 ff ff callq 405c10 <__gettext_free_exp> - 40c29c: 48 8b 04 24 mov (%rsp),%rax - 40c2a0: 48 8b 50 08 mov 0x8(%rax),%rdx - 40c2a4: 48 85 d2 test %rdx,%rdx - 40c2a7: 0f 84 ef f1 ff ff je 40b49c - 40c2ad: 8b 0a mov (%rdx),%ecx - 40c2af: 83 f9 02 cmp $0x2,%ecx - 40c2b2: 0f 84 1d 0b 00 00 je 40cdd5 - 40c2b8: 83 f9 03 cmp $0x3,%ecx - 40c2bb: 0f 84 f9 0a 00 00 je 40cdba - 40c2c1: 83 f9 01 cmp $0x1,%ecx - 40c2c4: 0f 84 26 0b 00 00 je 40cdf0 - 40c2ca: 48 89 d7 mov %rdx,%rdi - 40c2cd: 48 89 04 24 mov %rax,(%rsp) - 40c2d1: e8 da 1a 01 00 callq 41ddb0 <__cfree> - 40c2d6: 48 8b 04 24 mov (%rsp),%rax - 40c2da: e9 bd f1 ff ff jmpq 40b49c - 40c2df: 48 8b 78 18 mov 0x18(%rax),%rdi - 40c2e3: 48 89 04 24 mov %rax,(%rsp) - 40c2e7: e8 24 99 ff ff callq 405c10 <__gettext_free_exp> - 40c2ec: 48 8b 04 24 mov (%rsp),%rax - 40c2f0: 48 8b 78 10 mov 0x10(%rax),%rdi - 40c2f4: 48 89 04 24 mov %rax,(%rsp) - 40c2f8: e8 13 99 ff ff callq 405c10 <__gettext_free_exp> - 40c2fd: 48 8b 04 24 mov (%rsp),%rax - 40c301: 48 8b 50 08 mov 0x8(%rax),%rdx - 40c305: 48 85 d2 test %rdx,%rdx - 40c308: 0f 84 6a f2 ff ff je 40b578 - 40c30e: 8b 0a mov (%rdx),%ecx - 40c310: 83 f9 02 cmp $0x2,%ecx - 40c313: 0f 84 de 05 00 00 je 40c8f7 - 40c319: 83 f9 03 cmp $0x3,%ecx - 40c31c: 0f 84 ba 05 00 00 je 40c8dc - 40c322: 83 f9 01 cmp $0x1,%ecx - 40c325: 0f 84 e7 05 00 00 je 40c912 - 40c32b: 48 89 d7 mov %rdx,%rdi - 40c32e: 48 89 04 24 mov %rax,(%rsp) - 40c332: e8 79 1a 01 00 callq 41ddb0 <__cfree> - 40c337: 48 8b 04 24 mov (%rsp),%rax - 40c33b: e9 38 f2 ff ff jmpq 40b578 - 40c340: 48 8b 78 18 mov 0x18(%rax),%rdi - 40c344: 48 89 04 24 mov %rax,(%rsp) - 40c348: e8 c3 98 ff ff callq 405c10 <__gettext_free_exp> - 40c34d: 48 8b 04 24 mov (%rsp),%rax - 40c351: 48 8b 78 10 mov 0x10(%rax),%rdi - 40c355: 48 89 04 24 mov %rax,(%rsp) - 40c359: e8 b2 98 ff ff callq 405c10 <__gettext_free_exp> - 40c35e: 48 8b 04 24 mov (%rsp),%rax - 40c362: 48 8b 50 08 mov 0x8(%rax),%rdx - 40c366: 48 85 d2 test %rdx,%rdx - 40c369: 0f 84 bf f0 ff ff je 40b42e - 40c36f: 8b 0a mov (%rdx),%ecx - 40c371: 83 f9 02 cmp $0x2,%ecx - 40c374: 0f 84 d1 04 00 00 je 40c84b - 40c37a: 83 f9 03 cmp $0x3,%ecx - 40c37d: 0f 84 ad 04 00 00 je 40c830 - 40c383: 83 f9 01 cmp $0x1,%ecx - 40c386: 0f 84 da 04 00 00 je 40c866 - 40c38c: 48 89 d7 mov %rdx,%rdi - 40c38f: 48 89 04 24 mov %rax,(%rsp) - 40c393: e8 18 1a 01 00 callq 41ddb0 <__cfree> - 40c398: 48 8b 04 24 mov (%rsp),%rax - 40c39c: e9 8d f0 ff ff jmpq 40b42e - 40c3a1: 48 8b 78 18 mov 0x18(%rax),%rdi - 40c3a5: 48 89 04 24 mov %rax,(%rsp) - 40c3a9: e8 62 98 ff ff callq 405c10 <__gettext_free_exp> - 40c3ae: 48 8b 04 24 mov (%rsp),%rax - 40c3b2: 48 8b 78 10 mov 0x10(%rax),%rdi - 40c3b6: 48 89 04 24 mov %rax,(%rsp) - 40c3ba: e8 51 98 ff ff callq 405c10 <__gettext_free_exp> - 40c3bf: 48 8b 04 24 mov (%rsp),%rax - 40c3c3: 48 8b 50 08 mov 0x8(%rax),%rdx - 40c3c7: 48 85 d2 test %rdx,%rdx - 40c3ca: 0f 84 f0 ef ff ff je 40b3c0 - 40c3d0: 8b 0a mov (%rdx),%ecx - 40c3d2: 83 f9 02 cmp $0x2,%ecx - 40c3d5: 0f 84 3c 07 00 00 je 40cb17 - 40c3db: 83 f9 03 cmp $0x3,%ecx - 40c3de: 0f 84 18 07 00 00 je 40cafc - 40c3e4: 83 f9 01 cmp $0x1,%ecx - 40c3e7: 0f 84 45 07 00 00 je 40cb32 - 40c3ed: 48 89 d7 mov %rdx,%rdi - 40c3f0: 48 89 04 24 mov %rax,(%rsp) - 40c3f4: e8 b7 19 01 00 callq 41ddb0 <__cfree> - 40c3f9: 48 8b 04 24 mov (%rsp),%rax - 40c3fd: e9 be ef ff ff jmpq 40b3c0 - 40c402: 48 8b 78 18 mov 0x18(%rax),%rdi - 40c406: 48 89 04 24 mov %rax,(%rsp) - 40c40a: e8 01 98 ff ff callq 405c10 <__gettext_free_exp> - 40c40f: 48 8b 04 24 mov (%rsp),%rax - 40c413: 48 8b 78 10 mov 0x10(%rax),%rdi - 40c417: 48 89 04 24 mov %rax,(%rsp) - 40c41b: e8 f0 97 ff ff callq 405c10 <__gettext_free_exp> - 40c420: 48 8b 04 24 mov (%rsp),%rax - 40c424: 48 8b 50 08 mov 0x8(%rax),%rdx - 40c428: 48 85 d2 test %rdx,%rdx - 40c42b: 0f 84 d9 f0 ff ff je 40b50a - 40c431: 8b 0a mov (%rdx),%ecx - 40c433: 83 f9 02 cmp $0x2,%ecx - 40c436: 0f 84 ad 07 00 00 je 40cbe9 - 40c43c: 83 f9 03 cmp $0x3,%ecx - 40c43f: 0f 84 89 07 00 00 je 40cbce - 40c445: 83 f9 01 cmp $0x1,%ecx - 40c448: 0f 84 b6 07 00 00 je 40cc04 - 40c44e: 48 89 d7 mov %rdx,%rdi - 40c451: 48 89 04 24 mov %rax,(%rsp) - 40c455: e8 56 19 01 00 callq 41ddb0 <__cfree> - 40c45a: 48 8b 04 24 mov (%rsp),%rax - 40c45e: e9 a7 f0 ff ff jmpq 40b50a - 40c463: 48 8b 78 18 mov 0x18(%rax),%rdi - 40c467: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c46c: e8 9f 97 ff ff callq 405c10 <__gettext_free_exp> - 40c471: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c476: 48 8b 78 10 mov 0x10(%rax),%rdi - 40c47a: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c47f: e8 8c 97 ff ff callq 405c10 <__gettext_free_exp> - 40c484: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c489: 48 8b 78 08 mov 0x8(%rax),%rdi - 40c48d: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c492: e8 79 97 ff ff callq 405c10 <__gettext_free_exp> - 40c497: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c49c: 48 89 c7 mov %rax,%rdi - 40c49f: e8 0c 19 01 00 callq 41ddb0 <__cfree> - 40c4a4: 48 8b 04 24 mov (%rsp),%rax - 40c4a8: 48 8b 40 08 mov 0x8(%rax),%rax - 40c4ac: 48 85 c0 test %rax,%rax - 40c4af: 0f 84 35 f1 ff ff je 40b5ea - 40c4b5: 8b 10 mov (%rax),%edx - 40c4b7: 83 fa 02 cmp $0x2,%edx - 40c4ba: 0f 84 57 05 00 00 je 40ca17 - 40c4c0: 83 fa 03 cmp $0x3,%edx - 40c4c3: 0f 84 3b 05 00 00 je 40ca04 - 40c4c9: 83 fa 01 cmp $0x1,%edx - 40c4cc: 0f 84 58 05 00 00 je 40ca2a - 40c4d2: 48 89 c7 mov %rax,%rdi - 40c4d5: e8 d6 18 01 00 callq 41ddb0 <__cfree> - 40c4da: e9 0b f1 ff ff jmpq 40b5ea - 40c4df: 48 8b 78 18 mov 0x18(%rax),%rdi - 40c4e3: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c4e8: e8 23 97 ff ff callq 405c10 <__gettext_free_exp> - 40c4ed: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c4f2: 48 8b 78 10 mov 0x10(%rax),%rdi - 40c4f6: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c4fb: e8 10 97 ff ff callq 405c10 <__gettext_free_exp> - 40c500: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c505: 48 8b 78 08 mov 0x8(%rax),%rdi - 40c509: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c50e: e8 fd 96 ff ff callq 405c10 <__gettext_free_exp> - 40c513: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c518: e9 2e f4 ff ff jmpq 40b94b - 40c51d: 48 8b 78 18 mov 0x18(%rax),%rdi - 40c521: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c526: e8 e5 96 ff ff callq 405c10 <__gettext_free_exp> - 40c52b: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c530: 48 8b 78 10 mov 0x10(%rax),%rdi - 40c534: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c539: e8 d2 96 ff ff callq 405c10 <__gettext_free_exp> - 40c53e: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c543: 48 8b 78 08 mov 0x8(%rax),%rdi - 40c547: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c54c: e8 bf 96 ff ff callq 405c10 <__gettext_free_exp> - 40c551: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c556: e9 6a f4 ff ff jmpq 40b9c5 - 40c55b: 48 8b 78 18 mov 0x18(%rax),%rdi - 40c55f: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c564: e8 a7 96 ff ff callq 405c10 <__gettext_free_exp> - 40c569: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c56e: 48 8b 78 10 mov 0x10(%rax),%rdi - 40c572: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c577: e8 94 96 ff ff callq 405c10 <__gettext_free_exp> - 40c57c: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c581: 48 8b 78 08 mov 0x8(%rax),%rdi - 40c585: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c58a: e8 81 96 ff ff callq 405c10 <__gettext_free_exp> - 40c58f: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c594: e9 a6 f4 ff ff jmpq 40ba3f - 40c599: 48 8b 78 18 mov 0x18(%rax),%rdi - 40c59d: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c5a2: e8 69 96 ff ff callq 405c10 <__gettext_free_exp> - 40c5a7: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c5ac: 48 8b 78 10 mov 0x10(%rax),%rdi - 40c5b0: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c5b5: e8 56 96 ff ff callq 405c10 <__gettext_free_exp> - 40c5ba: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c5bf: 48 8b 78 08 mov 0x8(%rax),%rdi - 40c5c3: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c5c8: e8 43 96 ff ff callq 405c10 <__gettext_free_exp> - 40c5cd: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c5d2: e9 fa f2 ff ff jmpq 40b8d1 - 40c5d7: 49 8b 7f 18 mov 0x18(%r15),%rdi - 40c5db: e8 30 96 ff ff callq 405c10 <__gettext_free_exp> - 40c5e0: 49 8b 7f 10 mov 0x10(%r15),%rdi - 40c5e4: e8 27 96 ff ff callq 405c10 <__gettext_free_exp> - 40c5e9: 49 8b 47 08 mov 0x8(%r15),%rax - 40c5ed: 48 85 c0 test %rax,%rax - 40c5f0: 0f 84 51 e2 ff ff je 40a847 - 40c5f6: 8b 10 mov (%rax),%edx - 40c5f8: 83 fa 02 cmp $0x2,%edx - 40c5fb: 74 28 je 40c625 - 40c5fd: 83 fa 03 cmp $0x3,%edx - 40c600: 74 12 je 40c614 - 40c602: 83 fa 01 cmp $0x1,%edx - 40c605: 74 2f je 40c636 - 40c607: 48 89 c7 mov %rax,%rdi - 40c60a: e8 a1 17 01 00 callq 41ddb0 <__cfree> - 40c60f: e9 33 e2 ff ff jmpq 40a847 - 40c614: 48 8b 78 18 mov 0x18(%rax),%rdi - 40c618: 48 89 04 24 mov %rax,(%rsp) - 40c61c: e8 ef 95 ff ff callq 405c10 <__gettext_free_exp> - 40c621: 48 8b 04 24 mov (%rsp),%rax - 40c625: 48 8b 78 10 mov 0x10(%rax),%rdi - 40c629: 48 89 04 24 mov %rax,(%rsp) - 40c62d: e8 de 95 ff ff callq 405c10 <__gettext_free_exp> - 40c632: 48 8b 04 24 mov (%rsp),%rax - 40c636: 48 8b 78 08 mov 0x8(%rax),%rdi - 40c63a: 48 89 04 24 mov %rax,(%rsp) - 40c63e: e8 cd 95 ff ff callq 405c10 <__gettext_free_exp> - 40c643: 48 8b 04 24 mov (%rsp),%rax - 40c647: eb be jmp 40c607 - 40c649: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 40c650: 49 8b 47 18 mov 0x18(%r15),%rax - 40c654: 48 85 c0 test %rax,%rax - 40c657: 0f 84 8c e2 ff ff je 40a8e9 - 40c65d: 8b 10 mov (%rax),%edx - 40c65f: 83 fa 02 cmp $0x2,%edx - 40c662: 0f 84 57 e2 ff ff je 40a8bf - 40c668: 83 fa 03 cmp $0x3,%edx - 40c66b: 0f 84 3d e2 ff ff je 40a8ae - 40c671: 83 fa 01 cmp $0x1,%edx - 40c674: 0f 85 67 e2 ff ff jne 40a8e1 - 40c67a: e9 51 e2 ff ff jmpq 40a8d0 - 40c67f: 90 nop - 40c680: 49 8b 47 18 mov 0x18(%r15),%rax - 40c684: 48 85 c0 test %rax,%rax - 40c687: 0f 84 5c db ff ff je 40a1e9 - 40c68d: 8b 10 mov (%rax),%edx - 40c68f: 83 fa 02 cmp $0x2,%edx - 40c692: 0f 84 27 db ff ff je 40a1bf - 40c698: 83 fa 03 cmp $0x3,%edx - 40c69b: 0f 84 0d db ff ff je 40a1ae - 40c6a1: 83 fa 01 cmp $0x1,%edx - 40c6a4: 0f 85 37 db ff ff jne 40a1e1 - 40c6aa: e9 21 db ff ff jmpq 40a1d0 - 40c6af: 90 nop - 40c6b0: 49 8b 47 18 mov 0x18(%r15),%rax - 40c6b4: 48 85 c0 test %rax,%rax - 40c6b7: 0f 84 6c e3 ff ff je 40aa29 - 40c6bd: 8b 10 mov (%rax),%edx - 40c6bf: 83 fa 02 cmp $0x2,%edx - 40c6c2: 0f 84 37 e3 ff ff je 40a9ff - 40c6c8: 83 fa 03 cmp $0x3,%edx - 40c6cb: 0f 84 1d e3 ff ff je 40a9ee - 40c6d1: 83 fa 01 cmp $0x1,%edx - 40c6d4: 0f 85 47 e3 ff ff jne 40aa21 - 40c6da: e9 31 e3 ff ff jmpq 40aa10 - 40c6df: 49 8b 7f 18 mov 0x18(%r15),%rdi - 40c6e3: e8 28 95 ff ff callq 405c10 <__gettext_free_exp> - 40c6e8: 49 8b 7f 10 mov 0x10(%r15),%rdi - 40c6ec: e8 1f 95 ff ff callq 405c10 <__gettext_free_exp> - 40c6f1: 49 8b 47 08 mov 0x8(%r15),%rax - 40c6f5: 48 85 c0 test %rax,%rax - 40c6f8: 0f 84 89 e2 ff ff je 40a987 - 40c6fe: 8b 10 mov (%rax),%edx - 40c700: 83 fa 02 cmp $0x2,%edx - 40c703: 74 28 je 40c72d - 40c705: 83 fa 03 cmp $0x3,%edx - 40c708: 74 12 je 40c71c - 40c70a: 83 fa 01 cmp $0x1,%edx - 40c70d: 74 2f je 40c73e - 40c70f: 48 89 c7 mov %rax,%rdi - 40c712: e8 99 16 01 00 callq 41ddb0 <__cfree> - 40c717: e9 6b e2 ff ff jmpq 40a987 - 40c71c: 48 8b 78 18 mov 0x18(%rax),%rdi - 40c720: 48 89 04 24 mov %rax,(%rsp) - 40c724: e8 e7 94 ff ff callq 405c10 <__gettext_free_exp> - 40c729: 48 8b 04 24 mov (%rsp),%rax - 40c72d: 48 8b 78 10 mov 0x10(%rax),%rdi - 40c731: 48 89 04 24 mov %rax,(%rsp) - 40c735: e8 d6 94 ff ff callq 405c10 <__gettext_free_exp> - 40c73a: 48 8b 04 24 mov (%rsp),%rax - 40c73e: 48 8b 78 08 mov 0x8(%rax),%rdi - 40c742: 48 89 04 24 mov %rax,(%rsp) - 40c746: e8 c5 94 ff ff callq 405c10 <__gettext_free_exp> - 40c74b: 48 8b 04 24 mov (%rsp),%rax - 40c74f: eb be jmp 40c70f - 40c751: 49 8b 7f 18 mov 0x18(%r15),%rdi - 40c755: e8 b6 94 ff ff callq 405c10 <__gettext_free_exp> - 40c75a: 49 8b 7f 10 mov 0x10(%r15),%rdi - 40c75e: e8 ad 94 ff ff callq 405c10 <__gettext_free_exp> - 40c763: 49 8b 47 08 mov 0x8(%r15),%rax - 40c767: 48 85 c0 test %rax,%rax - 40c76a: 0f 84 3f f3 ff ff je 40baaf - 40c770: 8b 10 mov (%rax),%edx - 40c772: 83 fa 02 cmp $0x2,%edx - 40c775: 74 28 je 40c79f - 40c777: 83 fa 03 cmp $0x3,%edx - 40c77a: 74 12 je 40c78e - 40c77c: 83 fa 01 cmp $0x1,%edx - 40c77f: 74 2f je 40c7b0 - 40c781: 48 89 c7 mov %rax,%rdi - 40c784: e8 27 16 01 00 callq 41ddb0 <__cfree> - 40c789: e9 21 f3 ff ff jmpq 40baaf - 40c78e: 48 8b 78 18 mov 0x18(%rax),%rdi - 40c792: 48 89 04 24 mov %rax,(%rsp) - 40c796: e8 75 94 ff ff callq 405c10 <__gettext_free_exp> - 40c79b: 48 8b 04 24 mov (%rsp),%rax - 40c79f: 48 8b 78 10 mov 0x10(%rax),%rdi - 40c7a3: 48 89 04 24 mov %rax,(%rsp) - 40c7a7: e8 64 94 ff ff callq 405c10 <__gettext_free_exp> - 40c7ac: 48 8b 04 24 mov (%rsp),%rax - 40c7b0: 48 8b 78 08 mov 0x8(%rax),%rdi - 40c7b4: 48 89 04 24 mov %rax,(%rsp) - 40c7b8: e8 53 94 ff ff callq 405c10 <__gettext_free_exp> - 40c7bd: 48 8b 04 24 mov (%rsp),%rax - 40c7c1: eb be jmp 40c781 - 40c7c3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 40c7c8: 4d 8b 7e 18 mov 0x18(%r14),%r15 - 40c7cc: 4d 85 ff test %r15,%r15 - 40c7cf: 0f 84 66 dc ff ff je 40a43b - 40c7d5: 41 8b 07 mov (%r15),%eax - 40c7d8: 83 f8 02 cmp $0x2,%eax - 40c7db: 0f 84 40 dc ff ff je 40a421 - 40c7e1: 83 f8 03 cmp $0x3,%eax - 40c7e4: 0f 84 2e dc ff ff je 40a418 - 40c7ea: 83 f8 01 cmp $0x1,%eax - 40c7ed: 0f 85 40 dc ff ff jne 40a433 - 40c7f3: e9 32 dc ff ff jmpq 40a42a - 40c7f8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 40c7ff: 00 - 40c800: 4d 8b 7e 18 mov 0x18(%r14),%r15 - 40c804: 4d 85 ff test %r15,%r15 - 40c807: 0f 84 6f d6 ff ff je 409e7c - 40c80d: 41 8b 07 mov (%r15),%eax - 40c810: 83 f8 02 cmp $0x2,%eax - 40c813: 0f 84 49 d6 ff ff je 409e62 - 40c819: 83 f8 03 cmp $0x3,%eax - 40c81c: 0f 84 37 d6 ff ff je 409e59 - 40c822: 83 f8 01 cmp $0x1,%eax - 40c825: 0f 85 49 d6 ff ff jne 409e74 - 40c82b: e9 3b d6 ff ff jmpq 409e6b - 40c830: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 40c834: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c839: 48 89 14 24 mov %rdx,(%rsp) - 40c83d: e8 ce 93 ff ff callq 405c10 <__gettext_free_exp> - 40c842: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c847: 48 8b 14 24 mov (%rsp),%rdx - 40c84b: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 40c84f: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c854: 48 89 14 24 mov %rdx,(%rsp) - 40c858: e8 b3 93 ff ff callq 405c10 <__gettext_free_exp> - 40c85d: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c862: 48 8b 14 24 mov (%rsp),%rdx - 40c866: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 40c86a: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c86f: 48 89 14 24 mov %rdx,(%rsp) - 40c873: e8 98 93 ff ff callq 405c10 <__gettext_free_exp> - 40c878: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c87d: 48 8b 14 24 mov (%rsp),%rdx - 40c881: e9 06 fb ff ff jmpq 40c38c - 40c886: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 40c88a: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c88f: 48 89 14 24 mov %rdx,(%rsp) - 40c893: e8 78 93 ff ff callq 405c10 <__gettext_free_exp> - 40c898: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c89d: 48 8b 14 24 mov (%rsp),%rdx - 40c8a1: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 40c8a5: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c8aa: 48 89 14 24 mov %rdx,(%rsp) - 40c8ae: e8 5d 93 ff ff callq 405c10 <__gettext_free_exp> - 40c8b3: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c8b8: 48 8b 14 24 mov (%rsp),%rdx - 40c8bc: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 40c8c0: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c8c5: 48 89 14 24 mov %rdx,(%rsp) - 40c8c9: e8 42 93 ff ff callq 405c10 <__gettext_free_exp> - 40c8ce: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c8d3: 48 8b 14 24 mov (%rsp),%rdx - 40c8d7: e9 44 f3 ff ff jmpq 40bc20 - 40c8dc: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 40c8e0: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c8e5: 48 89 14 24 mov %rdx,(%rsp) - 40c8e9: e8 22 93 ff ff callq 405c10 <__gettext_free_exp> - 40c8ee: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c8f3: 48 8b 14 24 mov (%rsp),%rdx - 40c8f7: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 40c8fb: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c900: 48 89 14 24 mov %rdx,(%rsp) - 40c904: e8 07 93 ff ff callq 405c10 <__gettext_free_exp> - 40c909: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c90e: 48 8b 14 24 mov (%rsp),%rdx - 40c912: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 40c916: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c91b: 48 89 14 24 mov %rdx,(%rsp) - 40c91f: e8 ec 92 ff ff callq 405c10 <__gettext_free_exp> - 40c924: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c929: 48 8b 14 24 mov (%rsp),%rdx - 40c92d: e9 f9 f9 ff ff jmpq 40c32b - 40c932: 48 8b 78 18 mov 0x18(%rax),%rdi - 40c936: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c93b: e8 d0 92 ff ff callq 405c10 <__gettext_free_exp> - 40c940: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c945: 48 8b 78 10 mov 0x10(%rax),%rdi - 40c949: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c94e: e8 bd 92 ff ff callq 405c10 <__gettext_free_exp> - 40c953: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c958: 48 8b 78 08 mov 0x8(%rax),%rdi - 40c95c: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c961: e8 aa 92 ff ff callq 405c10 <__gettext_free_exp> - 40c966: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c96b: e9 b8 e8 ff ff jmpq 40b228 - 40c970: 48 8b 78 18 mov 0x18(%rax),%rdi - 40c974: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c979: e8 92 92 ff ff callq 405c10 <__gettext_free_exp> - 40c97e: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c983: 48 8b 78 10 mov 0x10(%rax),%rdi - 40c987: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c98c: e8 7f 92 ff ff callq 405c10 <__gettext_free_exp> - 40c991: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c996: 48 8b 78 08 mov 0x8(%rax),%rdi - 40c99a: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c99f: e8 6c 92 ff ff callq 405c10 <__gettext_free_exp> - 40c9a4: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c9a9: e9 bc e3 ff ff jmpq 40ad6a - 40c9ae: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 40c9b2: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c9b7: 48 89 14 24 mov %rdx,(%rsp) - 40c9bb: e8 50 92 ff ff callq 405c10 <__gettext_free_exp> - 40c9c0: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c9c5: 48 8b 14 24 mov (%rsp),%rdx - 40c9c9: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 40c9cd: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c9d2: 48 89 14 24 mov %rdx,(%rsp) - 40c9d6: e8 35 92 ff ff callq 405c10 <__gettext_free_exp> - 40c9db: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c9e0: 48 8b 14 24 mov (%rsp),%rdx - 40c9e4: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 40c9e8: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40c9ed: 48 89 14 24 mov %rdx,(%rsp) - 40c9f1: e8 1a 92 ff ff callq 405c10 <__gettext_free_exp> - 40c9f6: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40c9fb: 48 8b 14 24 mov (%rsp),%rdx - 40c9ff: e9 de f2 ff ff jmpq 40bce2 - 40ca04: 48 8b 78 18 mov 0x18(%rax),%rdi - 40ca08: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40ca0d: e8 fe 91 ff ff callq 405c10 <__gettext_free_exp> - 40ca12: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40ca17: 48 8b 78 10 mov 0x10(%rax),%rdi - 40ca1b: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40ca20: e8 eb 91 ff ff callq 405c10 <__gettext_free_exp> - 40ca25: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40ca2a: 48 8b 78 08 mov 0x8(%rax),%rdi - 40ca2e: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40ca33: e8 d8 91 ff ff callq 405c10 <__gettext_free_exp> - 40ca38: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40ca3d: e9 90 fa ff ff jmpq 40c4d2 - 40ca42: 48 8b 78 18 mov 0x18(%rax),%rdi - 40ca46: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40ca4b: e8 c0 91 ff ff callq 405c10 <__gettext_free_exp> - 40ca50: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40ca55: 48 8b 78 10 mov 0x10(%rax),%rdi - 40ca59: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40ca5e: e8 ad 91 ff ff callq 405c10 <__gettext_free_exp> - 40ca63: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40ca68: 48 8b 78 08 mov 0x8(%rax),%rdi - 40ca6c: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40ca71: e8 9a 91 ff ff callq 405c10 <__gettext_free_exp> - 40ca76: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40ca7b: e9 2e e7 ff ff jmpq 40b1ae - 40ca80: 48 8b 78 18 mov 0x18(%rax),%rdi - 40ca84: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40ca89: e8 82 91 ff ff callq 405c10 <__gettext_free_exp> - 40ca8e: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40ca93: 48 8b 78 10 mov 0x10(%rax),%rdi - 40ca97: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40ca9c: e8 6f 91 ff ff callq 405c10 <__gettext_free_exp> - 40caa1: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40caa6: 48 8b 78 08 mov 0x8(%rax),%rdi - 40caaa: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40caaf: e8 5c 91 ff ff callq 405c10 <__gettext_free_exp> - 40cab4: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40cab9: e9 cc e1 ff ff jmpq 40ac8a - 40cabe: 48 8b 78 18 mov 0x18(%rax),%rdi - 40cac2: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40cac7: e8 44 91 ff ff callq 405c10 <__gettext_free_exp> - 40cacc: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40cad1: 48 8b 78 10 mov 0x10(%rax),%rdi - 40cad5: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40cada: e8 31 91 ff ff callq 405c10 <__gettext_free_exp> - 40cadf: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40cae4: 48 8b 78 08 mov 0x8(%rax),%rdi - 40cae8: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40caed: e8 1e 91 ff ff callq 405c10 <__gettext_free_exp> - 40caf2: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40caf7: e9 ae e0 ff ff jmpq 40abaa - 40cafc: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 40cb00: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40cb05: 48 89 14 24 mov %rdx,(%rsp) - 40cb09: e8 02 91 ff ff callq 405c10 <__gettext_free_exp> - 40cb0e: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40cb13: 48 8b 14 24 mov (%rsp),%rdx - 40cb17: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 40cb1b: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40cb20: 48 89 14 24 mov %rdx,(%rsp) - 40cb24: e8 e7 90 ff ff callq 405c10 <__gettext_free_exp> - 40cb29: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40cb2e: 48 8b 14 24 mov (%rsp),%rdx - 40cb32: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 40cb36: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40cb3b: 48 89 14 24 mov %rdx,(%rsp) - 40cb3f: e8 cc 90 ff ff callq 405c10 <__gettext_free_exp> - 40cb44: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40cb49: 48 8b 14 24 mov (%rsp),%rdx - 40cb4d: e9 9b f8 ff ff jmpq 40c3ed - 40cb52: 48 8b 78 18 mov 0x18(%rax),%rdi - 40cb56: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40cb5b: e8 b0 90 ff ff callq 405c10 <__gettext_free_exp> - 40cb60: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40cb65: 48 8b 78 10 mov 0x10(%rax),%rdi - 40cb69: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40cb6e: e8 9d 90 ff ff callq 405c10 <__gettext_free_exp> - 40cb73: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40cb78: 48 8b 78 08 mov 0x8(%rax),%rdi - 40cb7c: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40cb81: e8 8a 90 ff ff callq 405c10 <__gettext_free_exp> - 40cb86: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40cb8b: e9 12 e7 ff ff jmpq 40b2a2 - 40cb90: 48 8b 78 18 mov 0x18(%rax),%rdi - 40cb94: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40cb99: e8 72 90 ff ff callq 405c10 <__gettext_free_exp> - 40cb9e: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40cba3: 48 8b 78 10 mov 0x10(%rax),%rdi - 40cba7: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40cbac: e8 5f 90 ff ff callq 405c10 <__gettext_free_exp> - 40cbb1: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40cbb6: 48 8b 78 08 mov 0x8(%rax),%rdi - 40cbba: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40cbbf: e8 4c 90 ff ff callq 405c10 <__gettext_free_exp> - 40cbc4: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40cbc9: e9 4e e7 ff ff jmpq 40b31c - 40cbce: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 40cbd2: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40cbd7: 48 89 14 24 mov %rdx,(%rsp) - 40cbdb: e8 30 90 ff ff callq 405c10 <__gettext_free_exp> - 40cbe0: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40cbe5: 48 8b 14 24 mov (%rsp),%rdx - 40cbe9: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 40cbed: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40cbf2: 48 89 14 24 mov %rdx,(%rsp) - 40cbf6: e8 15 90 ff ff callq 405c10 <__gettext_free_exp> - 40cbfb: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40cc00: 48 8b 14 24 mov (%rsp),%rdx - 40cc04: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 40cc08: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40cc0d: 48 89 14 24 mov %rdx,(%rsp) - 40cc11: e8 fa 8f ff ff callq 405c10 <__gettext_free_exp> - 40cc16: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40cc1b: 48 8b 14 24 mov (%rsp),%rdx - 40cc1f: e9 2a f8 ff ff jmpq 40c44e - 40cc24: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 40cc28: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40cc2d: 48 89 14 24 mov %rdx,(%rsp) - 40cc31: e8 da 8f ff ff callq 405c10 <__gettext_free_exp> - 40cc36: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40cc3b: 48 8b 14 24 mov (%rsp),%rdx - 40cc3f: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 40cc43: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40cc48: 48 89 14 24 mov %rdx,(%rsp) - 40cc4c: e8 bf 8f ff ff callq 405c10 <__gettext_free_exp> - 40cc51: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40cc56: 48 8b 14 24 mov (%rsp),%rdx - 40cc5a: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 40cc5e: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40cc63: 48 89 14 24 mov %rdx,(%rsp) - 40cc67: e8 a4 8f ff ff callq 405c10 <__gettext_free_exp> - 40cc6c: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40cc71: 48 8b 14 24 mov (%rsp),%rdx - 40cc75: e9 c9 f0 ff ff jmpq 40bd43 - 40cc7a: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 40cc7e: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40cc83: 48 89 14 24 mov %rdx,(%rsp) - 40cc87: e8 84 8f ff ff callq 405c10 <__gettext_free_exp> - 40cc8c: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40cc91: 48 8b 14 24 mov (%rsp),%rdx - 40cc95: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 40cc99: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40cc9e: 48 89 14 24 mov %rdx,(%rsp) - 40cca2: e8 69 8f ff ff callq 405c10 <__gettext_free_exp> - 40cca7: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40ccac: 48 8b 14 24 mov (%rsp),%rdx - 40ccb0: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 40ccb4: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40ccb9: 48 89 14 24 mov %rdx,(%rsp) - 40ccbd: e8 4e 8f ff ff callq 405c10 <__gettext_free_exp> - 40ccc2: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40ccc7: 48 8b 14 24 mov (%rsp),%rdx - 40cccb: e9 ef ee ff ff jmpq 40bbbf - 40ccd0: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 40ccd4: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40ccd9: 48 89 14 24 mov %rdx,(%rsp) - 40ccdd: e8 2e 8f ff ff callq 405c10 <__gettext_free_exp> - 40cce2: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40cce7: 48 8b 14 24 mov (%rsp),%rdx - 40cceb: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 40ccef: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40ccf4: 48 89 14 24 mov %rdx,(%rsp) - 40ccf8: e8 13 8f ff ff callq 405c10 <__gettext_free_exp> - 40ccfd: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40cd02: 48 8b 14 24 mov (%rsp),%rdx - 40cd06: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 40cd0a: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40cd0f: 48 89 14 24 mov %rdx,(%rsp) - 40cd13: e8 f8 8e ff ff callq 405c10 <__gettext_free_exp> - 40cd18: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40cd1d: 48 8b 14 24 mov (%rsp),%rdx - 40cd21: e9 5b ef ff ff jmpq 40bc81 - 40cd26: 48 8b 78 18 mov 0x18(%rax),%rdi - 40cd2a: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40cd2f: e8 dc 8e ff ff callq 405c10 <__gettext_free_exp> - 40cd34: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40cd39: 48 8b 78 10 mov 0x10(%rax),%rdi - 40cd3d: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40cd42: e8 c9 8e ff ff callq 405c10 <__gettext_free_exp> - 40cd47: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40cd4c: 48 8b 78 08 mov 0x8(%rax),%rdi - 40cd50: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40cd55: e8 b6 8e ff ff callq 405c10 <__gettext_free_exp> - 40cd5a: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40cd5f: e9 66 dd ff ff jmpq 40aaca - 40cd64: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 40cd68: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40cd6d: 48 89 14 24 mov %rdx,(%rsp) - 40cd71: e8 9a 8e ff ff callq 405c10 <__gettext_free_exp> - 40cd76: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40cd7b: 48 8b 14 24 mov (%rsp),%rdx - 40cd7f: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 40cd83: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40cd88: 48 89 14 24 mov %rdx,(%rsp) - 40cd8c: e8 7f 8e ff ff callq 405c10 <__gettext_free_exp> - 40cd91: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40cd96: 48 8b 14 24 mov (%rsp),%rdx - 40cd9a: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 40cd9e: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40cda3: 48 89 14 24 mov %rdx,(%rsp) - 40cda7: e8 64 8e ff ff callq 405c10 <__gettext_free_exp> - 40cdac: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40cdb1: 48 8b 14 24 mov (%rsp),%rdx - 40cdb5: e9 a4 ed ff ff jmpq 40bb5e - 40cdba: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 40cdbe: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40cdc3: 48 89 14 24 mov %rdx,(%rsp) - 40cdc7: e8 44 8e ff ff callq 405c10 <__gettext_free_exp> - 40cdcc: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40cdd1: 48 8b 14 24 mov (%rsp),%rdx - 40cdd5: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 40cdd9: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40cdde: 48 89 14 24 mov %rdx,(%rsp) - 40cde2: e8 29 8e ff ff callq 405c10 <__gettext_free_exp> - 40cde7: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40cdec: 48 8b 14 24 mov (%rsp),%rdx - 40cdf0: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 40cdf4: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40cdf9: 48 89 14 24 mov %rdx,(%rsp) - 40cdfd: e8 0e 8e ff ff callq 405c10 <__gettext_free_exp> - 40ce02: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40ce07: 48 8b 14 24 mov (%rsp),%rdx - 40ce0b: e9 ba f4 ff ff jmpq 40c2ca - 40ce10: 48 8b 78 18 mov 0x18(%rax),%rdi - 40ce14: 48 89 04 24 mov %rax,(%rsp) - 40ce18: e8 f3 8d ff ff callq 405c10 <__gettext_free_exp> - 40ce1d: 48 8b 04 24 mov (%rsp),%rax - 40ce21: 48 8b 78 10 mov 0x10(%rax),%rdi - 40ce25: 48 89 04 24 mov %rax,(%rsp) - 40ce29: e8 e2 8d ff ff callq 405c10 <__gettext_free_exp> - 40ce2e: 48 8b 04 24 mov (%rsp),%rax - 40ce32: 48 8b 78 08 mov 0x8(%rax),%rdi - 40ce36: 48 89 04 24 mov %rax,(%rsp) - 40ce3a: e8 d1 8d ff ff callq 405c10 <__gettext_free_exp> - 40ce3f: 48 8b 04 24 mov (%rsp),%rax - 40ce43: e9 95 ef ff ff jmpq 40bddd - 40ce48: 48 8b 78 18 mov 0x18(%rax),%rdi - 40ce4c: 48 89 04 24 mov %rax,(%rsp) - 40ce50: e8 bb 8d ff ff callq 405c10 <__gettext_free_exp> - 40ce55: 48 8b 04 24 mov (%rsp),%rax - 40ce59: 48 8b 78 10 mov 0x10(%rax),%rdi - 40ce5d: 48 89 04 24 mov %rax,(%rsp) - 40ce61: e8 aa 8d ff ff callq 405c10 <__gettext_free_exp> - 40ce66: 48 8b 04 24 mov (%rsp),%rax - 40ce6a: 48 8b 78 08 mov 0x8(%rax),%rdi - 40ce6e: 48 89 04 24 mov %rax,(%rsp) - 40ce72: e8 99 8d ff ff callq 405c10 <__gettext_free_exp> - 40ce77: 48 8b 04 24 mov (%rsp),%rax - 40ce7b: e9 c6 e6 ff ff jmpq 40b546 - 40ce80: 48 8b 78 18 mov 0x18(%rax),%rdi - 40ce84: 48 89 04 24 mov %rax,(%rsp) - 40ce88: e8 83 8d ff ff callq 405c10 <__gettext_free_exp> - 40ce8d: 48 8b 04 24 mov (%rsp),%rax - 40ce91: 48 8b 78 10 mov 0x10(%rax),%rdi - 40ce95: 48 89 04 24 mov %rax,(%rsp) - 40ce99: e8 72 8d ff ff callq 405c10 <__gettext_free_exp> - 40ce9e: 48 8b 04 24 mov (%rsp),%rax - 40cea2: 48 8b 78 08 mov 0x8(%rax),%rdi - 40cea6: 48 89 04 24 mov %rax,(%rsp) - 40ceaa: e8 61 8d ff ff callq 405c10 <__gettext_free_exp> - 40ceaf: 48 8b 04 24 mov (%rsp),%rax - 40ceb3: e9 44 e5 ff ff jmpq 40b3fc - 40ceb8: 48 8b 78 18 mov 0x18(%rax),%rdi - 40cebc: 48 89 04 24 mov %rax,(%rsp) - 40cec0: e8 4b 8d ff ff callq 405c10 <__gettext_free_exp> - 40cec5: 48 8b 04 24 mov (%rsp),%rax - 40cec9: 48 8b 78 10 mov 0x10(%rax),%rdi - 40cecd: 48 89 04 24 mov %rax,(%rsp) - 40ced1: e8 3a 8d ff ff callq 405c10 <__gettext_free_exp> - 40ced6: 48 8b 04 24 mov (%rsp),%rax - 40ceda: 48 8b 78 08 mov 0x8(%rax),%rdi - 40cede: 48 89 04 24 mov %rax,(%rsp) - 40cee2: e8 29 8d ff ff callq 405c10 <__gettext_free_exp> - 40cee7: 48 8b 04 24 mov (%rsp),%rax - 40ceeb: e9 c4 e6 ff ff jmpq 40b5b4 - 40cef0: 48 8b 78 18 mov 0x18(%rax),%rdi - 40cef4: 48 89 04 24 mov %rax,(%rsp) - 40cef8: e8 13 8d ff ff callq 405c10 <__gettext_free_exp> - 40cefd: 48 8b 04 24 mov (%rsp),%rax - 40cf01: 48 8b 78 10 mov 0x10(%rax),%rdi - 40cf05: 48 89 04 24 mov %rax,(%rsp) - 40cf09: e8 02 8d ff ff callq 405c10 <__gettext_free_exp> - 40cf0e: 48 8b 04 24 mov (%rsp),%rax - 40cf12: 48 8b 78 08 mov 0x8(%rax),%rdi - 40cf16: 48 89 04 24 mov %rax,(%rsp) - 40cf1a: e8 f1 8c ff ff callq 405c10 <__gettext_free_exp> - 40cf1f: 48 8b 04 24 mov (%rsp),%rax - 40cf23: e9 66 e4 ff ff jmpq 40b38e - 40cf28: 48 8b 78 18 mov 0x18(%rax),%rdi - 40cf2c: 48 89 04 24 mov %rax,(%rsp) - 40cf30: e8 db 8c ff ff callq 405c10 <__gettext_free_exp> - 40cf35: 48 8b 04 24 mov (%rsp),%rax - 40cf39: 48 8b 78 10 mov 0x10(%rax),%rdi - 40cf3d: 48 89 04 24 mov %rax,(%rsp) - 40cf41: e8 ca 8c ff ff callq 405c10 <__gettext_free_exp> - 40cf46: 48 8b 04 24 mov (%rsp),%rax - 40cf4a: 48 8b 78 08 mov 0x8(%rax),%rdi - 40cf4e: 48 89 04 24 mov %rax,(%rsp) - 40cf52: e8 b9 8c ff ff callq 405c10 <__gettext_free_exp> - 40cf57: 48 8b 04 24 mov (%rsp),%rax - 40cf5b: e9 26 e1 ff ff jmpq 40b086 - 40cf60: 48 8b 78 18 mov 0x18(%rax),%rdi - 40cf64: 48 89 04 24 mov %rax,(%rsp) - 40cf68: e8 a3 8c ff ff callq 405c10 <__gettext_free_exp> - 40cf6d: 48 8b 04 24 mov (%rsp),%rax - 40cf71: 48 8b 78 10 mov 0x10(%rax),%rdi - 40cf75: 48 89 04 24 mov %rax,(%rsp) - 40cf79: e8 92 8c ff ff callq 405c10 <__gettext_free_exp> - 40cf7e: 48 8b 04 24 mov (%rsp),%rax - 40cf82: 48 8b 78 08 mov 0x8(%rax),%rdi - 40cf86: 48 89 04 24 mov %rax,(%rsp) - 40cf8a: e8 81 8c ff ff callq 405c10 <__gettext_free_exp> - 40cf8f: 48 8b 04 24 mov (%rsp),%rax - 40cf93: e9 fc ed ff ff jmpq 40bd94 - 40cf98: 48 8b 04 24 mov (%rsp),%rax - 40cf9c: 48 8b 78 18 mov 0x18(%rax),%rdi - 40cfa0: e8 6b 8c ff ff callq 405c10 <__gettext_free_exp> - 40cfa5: 48 8b 04 24 mov (%rsp),%rax - 40cfa9: 48 8b 40 10 mov 0x10(%rax),%rax - 40cfad: 48 85 c0 test %rax,%rax - 40cfb0: 0f 84 ee f4 ff ff je 40c4a4 - 40cfb6: 8b 10 mov (%rax),%edx - 40cfb8: 83 fa 02 cmp $0x2,%edx - 40cfbb: 0f 84 b5 f4 ff ff je 40c476 - 40cfc1: 83 fa 03 cmp $0x3,%edx - 40cfc4: 0f 84 99 f4 ff ff je 40c463 - 40cfca: 83 fa 01 cmp $0x1,%edx - 40cfcd: 0f 85 c9 f4 ff ff jne 40c49c - 40cfd3: e9 b1 f4 ff ff jmpq 40c489 - 40cfd8: 48 8b 78 18 mov 0x18(%rax),%rdi - 40cfdc: 48 89 04 24 mov %rax,(%rsp) - 40cfe0: e8 2b 8c ff ff callq 405c10 <__gettext_free_exp> - 40cfe5: 48 8b 04 24 mov (%rsp),%rax - 40cfe9: 48 8b 78 10 mov 0x10(%rax),%rdi - 40cfed: 48 89 04 24 mov %rax,(%rsp) - 40cff1: e8 1a 8c ff ff callq 405c10 <__gettext_free_exp> - 40cff6: 48 8b 04 24 mov (%rsp),%rax - 40cffa: 48 8b 78 08 mov 0x8(%rax),%rdi - 40cffe: 48 89 04 24 mov %rax,(%rsp) - 40d002: e8 09 8c ff ff callq 405c10 <__gettext_free_exp> - 40d007: 48 8b 04 24 mov (%rsp),%rax - 40d00b: e9 16 ee ff ff jmpq 40be26 - 40d010: 48 8b 04 24 mov (%rsp),%rax - 40d014: 48 8b 40 18 mov 0x18(%rax),%rax - 40d018: 48 85 c0 test %rax,%rax - 40d01b: 0f 84 46 d3 ff ff je 40a367 - 40d021: 8b 10 mov (%rax),%edx - 40d023: 83 fa 02 cmp $0x2,%edx - 40d026: 0f 84 0d d3 ff ff je 40a339 - 40d02c: 83 fa 03 cmp $0x3,%edx - 40d02f: 0f 84 f1 d2 ff ff je 40a326 - 40d035: 83 fa 01 cmp $0x1,%edx - 40d038: 0f 85 21 d3 ff ff jne 40a35f - 40d03e: e9 09 d3 ff ff jmpq 40a34c - 40d043: 48 8b 78 18 mov 0x18(%rax),%rdi - 40d047: 48 89 04 24 mov %rax,(%rsp) - 40d04b: e8 c0 8b ff ff callq 405c10 <__gettext_free_exp> - 40d050: 48 8b 04 24 mov (%rsp),%rax - 40d054: 48 8b 78 10 mov 0x10(%rax),%rdi - 40d058: 48 89 04 24 mov %rax,(%rsp) - 40d05c: e8 af 8b ff ff callq 405c10 <__gettext_free_exp> - 40d061: 48 8b 04 24 mov (%rsp),%rax - 40d065: 48 8b 50 08 mov 0x8(%rax),%rdx - 40d069: 48 85 d2 test %rdx,%rdx - 40d06c: 0f 84 d4 dd ff ff je 40ae46 - 40d072: 8b 0a mov (%rdx),%ecx - 40d074: 83 f9 02 cmp $0x2,%ecx - 40d077: 74 3a je 40d0b3 - 40d079: 83 f9 03 cmp $0x3,%ecx - 40d07c: 74 1a je 40d098 - 40d07e: 83 f9 01 cmp $0x1,%ecx - 40d081: 74 4b je 40d0ce - 40d083: 48 89 d7 mov %rdx,%rdi - 40d086: 48 89 04 24 mov %rax,(%rsp) - 40d08a: e8 21 0d 01 00 callq 41ddb0 <__cfree> - 40d08f: 48 8b 04 24 mov (%rsp),%rax - 40d093: e9 ae dd ff ff jmpq 40ae46 - 40d098: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 40d09c: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40d0a1: 48 89 14 24 mov %rdx,(%rsp) - 40d0a5: e8 66 8b ff ff callq 405c10 <__gettext_free_exp> - 40d0aa: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40d0af: 48 8b 14 24 mov (%rsp),%rdx - 40d0b3: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 40d0b7: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40d0bc: 48 89 14 24 mov %rdx,(%rsp) - 40d0c0: e8 4b 8b ff ff callq 405c10 <__gettext_free_exp> - 40d0c5: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40d0ca: 48 8b 14 24 mov (%rsp),%rdx - 40d0ce: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 40d0d2: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40d0d7: 48 89 14 24 mov %rdx,(%rsp) - 40d0db: e8 30 8b ff ff callq 405c10 <__gettext_free_exp> - 40d0e0: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40d0e5: 48 8b 14 24 mov (%rsp),%rdx - 40d0e9: eb 98 jmp 40d083 - 40d0eb: 48 8b 78 18 mov 0x18(%rax),%rdi - 40d0ef: 48 89 04 24 mov %rax,(%rsp) - 40d0f3: e8 18 8b ff ff callq 405c10 <__gettext_free_exp> - 40d0f8: 48 8b 04 24 mov (%rsp),%rax - 40d0fc: 48 8b 78 10 mov 0x10(%rax),%rdi - 40d100: 48 89 04 24 mov %rax,(%rsp) - 40d104: e8 07 8b ff ff callq 405c10 <__gettext_free_exp> - 40d109: 48 8b 04 24 mov (%rsp),%rax - 40d10d: 48 8b 78 08 mov 0x8(%rax),%rdi - 40d111: 48 89 04 24 mov %rax,(%rsp) - 40d115: e8 f6 8a ff ff callq 405c10 <__gettext_free_exp> - 40d11a: 48 8b 04 24 mov (%rsp),%rax - 40d11e: e9 43 de ff ff jmpq 40af66 - 40d123: 48 8b 78 18 mov 0x18(%rax),%rdi - 40d127: 48 89 04 24 mov %rax,(%rsp) - 40d12b: e8 e0 8a ff ff callq 405c10 <__gettext_free_exp> - 40d130: 48 8b 04 24 mov (%rsp),%rax - 40d134: 48 8b 78 10 mov 0x10(%rax),%rdi - 40d138: 48 89 04 24 mov %rax,(%rsp) - 40d13c: e8 cf 8a ff ff callq 405c10 <__gettext_free_exp> - 40d141: 48 8b 04 24 mov (%rsp),%rax - 40d145: 48 8b 78 08 mov 0x8(%rax),%rdi - 40d149: 48 89 04 24 mov %rax,(%rsp) - 40d14d: e8 be 8a ff ff callq 405c10 <__gettext_free_exp> - 40d152: 48 8b 04 24 mov (%rsp),%rax - 40d156: e9 7d e3 ff ff jmpq 40b4d8 - 40d15b: 48 8b 78 18 mov 0x18(%rax),%rdi - 40d15f: 48 89 04 24 mov %rax,(%rsp) - 40d163: e8 a8 8a ff ff callq 405c10 <__gettext_free_exp> - 40d168: 48 8b 04 24 mov (%rsp),%rax - 40d16c: 48 8b 78 10 mov 0x10(%rax),%rdi - 40d170: 48 89 04 24 mov %rax,(%rsp) - 40d174: e8 97 8a ff ff callq 405c10 <__gettext_free_exp> - 40d179: 48 8b 04 24 mov (%rsp),%rax - 40d17d: 48 8b 50 08 mov 0x8(%rax),%rdx - 40d181: 48 85 d2 test %rdx,%rdx - 40d184: 0f 84 e0 e2 ff ff je 40b46a - 40d18a: 8b 0a mov (%rdx),%ecx - 40d18c: 83 f9 02 cmp $0x2,%ecx - 40d18f: 74 3a je 40d1cb - 40d191: 83 f9 03 cmp $0x3,%ecx - 40d194: 74 1a je 40d1b0 - 40d196: 83 f9 01 cmp $0x1,%ecx - 40d199: 74 4b je 40d1e6 - 40d19b: 48 89 d7 mov %rdx,%rdi - 40d19e: 48 89 04 24 mov %rax,(%rsp) - 40d1a2: e8 09 0c 01 00 callq 41ddb0 <__cfree> - 40d1a7: 48 8b 04 24 mov (%rsp),%rax - 40d1ab: e9 ba e2 ff ff jmpq 40b46a - 40d1b0: 48 8b 7a 18 mov 0x18(%rdx),%rdi - 40d1b4: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40d1b9: 48 89 14 24 mov %rdx,(%rsp) - 40d1bd: e8 4e 8a ff ff callq 405c10 <__gettext_free_exp> - 40d1c2: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40d1c7: 48 8b 14 24 mov (%rsp),%rdx - 40d1cb: 48 8b 7a 10 mov 0x10(%rdx),%rdi - 40d1cf: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40d1d4: 48 89 14 24 mov %rdx,(%rsp) - 40d1d8: e8 33 8a ff ff callq 405c10 <__gettext_free_exp> - 40d1dd: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40d1e2: 48 8b 14 24 mov (%rsp),%rdx - 40d1e6: 48 8b 7a 08 mov 0x8(%rdx),%rdi - 40d1ea: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40d1ef: 48 89 14 24 mov %rdx,(%rsp) - 40d1f3: e8 18 8a ff ff callq 405c10 <__gettext_free_exp> - 40d1f8: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40d1fd: 48 8b 14 24 mov (%rsp),%rdx - 40d201: eb 98 jmp 40d19b - 40d203: bf 20 00 00 00 mov $0x20,%edi - 40d208: 89 34 24 mov %esi,(%rsp) - 40d20b: e8 00 08 01 00 callq 41da10 <__libc_malloc> - 40d210: 48 85 c0 test %rax,%rax - 40d213: 8b 34 24 mov (%rsp),%esi - 40d216: 0f 84 b4 d3 ff ff je 40a5d0 - 40d21c: 44 89 20 mov %r12d,(%rax) - 40d21f: 89 70 04 mov %esi,0x4(%rax) - 40d222: e9 ab d3 ff ff jmpq 40a5d2 - 40d227: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 40d22e: 00 00 - -000000000040d230 <__gettextparse>: - 40d230: 41 57 push %r15 - 40d232: 41 56 push %r14 - 40d234: 45 31 c0 xor %r8d,%r8d - 40d237: 41 55 push %r13 - 40d239: 41 54 push %r12 - 40d23b: 45 89 c5 mov %r8d,%r13d - 40d23e: 55 push %rbp - 40d23f: 53 push %rbx - 40d240: bd c8 00 00 00 mov $0xc8,%ebp - 40d245: 41 bc fe ff ff ff mov $0xfffffffe,%r12d - 40d24b: 48 81 ec 28 08 00 00 sub $0x828,%rsp - 40d252: 48 8d 9c 24 e0 01 00 lea 0x1e0(%rsp),%rbx - 40d259: 00 - 40d25a: 4c 8d 74 24 50 lea 0x50(%rsp),%r14 - 40d25f: 48 89 7c 24 18 mov %rdi,0x18(%rsp) - 40d264: c7 44 24 0c 00 00 00 movl $0x0,0xc(%rsp) - 40d26b: 00 - 40d26c: 48 89 1c 24 mov %rbx,(%rsp) - 40d270: 4c 89 f1 mov %r14,%rcx - 40d273: 48 8d 44 2d 00 lea 0x0(%rbp,%rbp,1),%rax - 40d278: 66 45 89 2e mov %r13w,(%r14) - 40d27c: 48 8d 54 01 fe lea -0x2(%rcx,%rax,1),%rdx - 40d281: 49 39 d6 cmp %rdx,%r14 - 40d284: 0f 82 c4 00 00 00 jb 40d34e <__gettextparse+0x11e> - 40d28a: 49 29 ce sub %rcx,%r14 - 40d28d: 49 d1 fe sar %r14 - 40d290: 48 81 fd 0f 27 00 00 cmp $0x270f,%rbp - 40d297: 49 8d 5e 01 lea 0x1(%r14),%rbx - 40d29b: 0f 87 0e 07 00 00 ja 40d9af <__gettextparse+0x77f> - 40d2a1: 48 3d 10 27 00 00 cmp $0x2710,%rax - 40d2a7: bd 10 27 00 00 mov $0x2710,%ebp - 40d2ac: 48 89 4c 24 10 mov %rcx,0x10(%rsp) - 40d2b1: 48 0f 46 e8 cmovbe %rax,%rbp - 40d2b5: 48 8d 44 ad 00 lea 0x0(%rbp,%rbp,4),%rax - 40d2ba: 48 8d 7c 00 07 lea 0x7(%rax,%rax,1),%rdi - 40d2bf: e8 4c 07 01 00 callq 41da10 <__libc_malloc> - 40d2c4: 48 85 c0 test %rax,%rax - 40d2c7: 49 89 c7 mov %rax,%r15 - 40d2ca: 48 8b 4c 24 10 mov 0x10(%rsp),%rcx - 40d2cf: 0f 84 da 06 00 00 je 40d9af <__gettextparse+0x77f> - 40d2d5: 4c 8d 34 1b lea (%rbx,%rbx,1),%r14 - 40d2d9: 48 89 ce mov %rcx,%rsi - 40d2dc: 48 89 c7 mov %rax,%rdi - 40d2df: 48 c1 e3 03 shl $0x3,%rbx - 40d2e3: 4c 89 f2 mov %r14,%rdx - 40d2e6: e8 35 ed 01 00 callq 42c020 - 40d2eb: 4d 8d 14 6f lea (%r15,%rbp,2),%r10 - 40d2ef: 48 8b 34 24 mov (%rsp),%rsi - 40d2f3: 48 8d 44 2d 00 lea 0x0(%rbp,%rbp,1),%rax - 40d2f8: 48 89 da mov %rbx,%rdx - 40d2fb: 4c 89 d7 mov %r10,%rdi - 40d2fe: 48 89 44 24 20 mov %rax,0x20(%rsp) - 40d303: e8 18 ed 01 00 callq 42c020 - 40d308: 48 8b 4c 24 10 mov 0x10(%rsp),%rcx - 40d30d: 49 89 c2 mov %rax,%r10 - 40d310: 48 8d 44 24 50 lea 0x50(%rsp),%rax - 40d315: 48 39 c1 cmp %rax,%rcx - 40d318: 74 10 je 40d32a <__gettextparse+0xfa> - 40d31a: 48 89 cf mov %rcx,%rdi - 40d31d: 4c 89 14 24 mov %r10,(%rsp) - 40d321: e8 8a 0a 01 00 callq 41ddb0 <__cfree> - 40d326: 4c 8b 14 24 mov (%rsp),%r10 - 40d32a: 48 8d 44 2d 00 lea 0x0(%rbp,%rbp,1),%rax - 40d32f: 4f 8d 74 37 fe lea -0x2(%r15,%r14,1),%r14 - 40d334: 49 8d 5c 1a f8 lea -0x8(%r10,%rbx,1),%rbx - 40d339: 49 8d 44 07 fe lea -0x2(%r15,%rax,1),%rax - 40d33e: 49 39 c6 cmp %rax,%r14 - 40d341: 0f 83 7f 06 00 00 jae 40d9c6 <__gettextparse+0x796> - 40d347: 4c 89 14 24 mov %r10,(%rsp) - 40d34b: 4c 89 f9 mov %r15,%rcx - 40d34e: 41 83 fd 09 cmp $0x9,%r13d - 40d352: 0f 84 64 06 00 00 je 40d9bc <__gettextparse+0x78c> - 40d358: 4d 63 c5 movslq %r13d,%r8 - 40d35b: 41 0f be 80 20 17 4a movsbl 0x4a1720(%r8),%eax - 40d362: 00 - 40d363: 83 f8 f6 cmp $0xfffffff6,%eax - 40d366: 74 3f je 40d3a7 <__gettextparse+0x177> - 40d368: 41 83 fc fe cmp $0xfffffffe,%r12d - 40d36c: 0f 84 2e 02 00 00 je 40d5a0 <__gettextparse+0x370> - 40d372: 45 85 e4 test %r12d,%r12d - 40d375: 0f 8e bc 01 00 00 jle 40d537 <__gettextparse+0x307> - 40d37b: 41 81 fc 06 01 00 00 cmp $0x106,%r12d - 40d382: be 02 00 00 00 mov $0x2,%esi - 40d387: 0f 8e 93 01 00 00 jle 40d520 <__gettextparse+0x2f0> - 40d38d: 8d 14 06 lea (%rsi,%rax,1),%edx - 40d390: 83 fa 36 cmp $0x36,%edx - 40d393: 77 12 ja 40d3a7 <__gettextparse+0x177> - 40d395: 48 63 d2 movslq %edx,%rdx - 40d398: 0f be ba a0 16 4a 00 movsbl 0x4a16a0(%rdx),%edi - 40d39f: 39 fe cmp %edi,%esi - 40d3a1: 0f 84 b9 01 00 00 je 40d560 <__gettextparse+0x330> - 40d3a7: 41 0f b6 b0 40 17 4a movzbl 0x4a1740(%r8),%esi - 40d3ae: 00 - 40d3af: 85 f6 test %esi,%esi - 40d3b1: 48 89 f2 mov %rsi,%rdx - 40d3b4: 74 32 je 40d3e8 <__gettextparse+0x1b8> - 40d3b6: 48 63 f6 movslq %esi,%rsi - 40d3b9: bf 01 00 00 00 mov $0x1,%edi - 40d3be: 0f b6 86 60 17 4a 00 movzbl 0x4a1760(%rsi),%eax - 40d3c5: 29 c7 sub %eax,%edi - 40d3c7: 49 89 c7 mov %rax,%r15 - 40d3ca: 80 fa 0d cmp $0xd,%dl - 40d3cd: 48 63 c7 movslq %edi,%rax - 40d3d0: 48 8b 04 c3 mov (%rbx,%rax,8),%rax - 40d3d4: 0f 87 94 03 00 00 ja 40d76e <__gettextparse+0x53e> - 40d3da: ff 24 d5 40 12 4a 00 jmpq *0x4a1240(,%rdx,8) - 40d3e1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 40d3e8: 83 7c 24 0c 03 cmpl $0x3,0xc(%rsp) - 40d3ed: 75 21 jne 40d410 <__gettextparse+0x1e0> - 40d3ef: e9 54 01 00 00 jmpq 40d548 <__gettextparse+0x318> - 40d3f4: 0f 1f 40 00 nopl 0x0(%rax) - 40d3f8: 4c 39 f1 cmp %r14,%rcx - 40d3fb: 74 53 je 40d450 <__gettextparse+0x220> - 40d3fd: 49 83 ee 02 sub $0x2,%r14 - 40d401: 49 0f bf 06 movswq (%r14),%rax - 40d405: 48 83 eb 08 sub $0x8,%rbx - 40d409: 0f be 80 20 17 4a 00 movsbl 0x4a1720(%rax),%eax - 40d410: 83 f8 f6 cmp $0xfffffff6,%eax - 40d413: 74 e3 je 40d3f8 <__gettextparse+0x1c8> - 40d415: 83 c0 01 add $0x1,%eax - 40d418: 83 f8 36 cmp $0x36,%eax - 40d41b: 77 db ja 40d3f8 <__gettextparse+0x1c8> - 40d41d: 48 98 cltq - 40d41f: 80 b8 a0 16 4a 00 01 cmpb $0x1,0x4a16a0(%rax) - 40d426: 75 d0 jne 40d3f8 <__gettextparse+0x1c8> - 40d428: 44 0f b6 a8 e0 16 4a movzbl 0x4a16e0(%rax),%r13d - 40d42f: 00 - 40d430: 45 85 ed test %r13d,%r13d - 40d433: 74 c3 je 40d3f8 <__gettextparse+0x1c8> - 40d435: 48 8b 44 24 28 mov 0x28(%rsp),%rax - 40d43a: 48 83 c3 08 add $0x8,%rbx - 40d43e: c7 44 24 0c 03 00 00 movl $0x3,0xc(%rsp) - 40d445: 00 - 40d446: 48 89 03 mov %rax,(%rbx) - 40d449: e9 b0 00 00 00 jmpq 40d4fe <__gettextparse+0x2ce> - 40d44e: 66 90 xchg %ax,%ax - 40d450: bb 01 00 00 00 mov $0x1,%ebx - 40d455: 48 8d 44 24 50 lea 0x50(%rsp),%rax - 40d45a: 49 39 c6 cmp %rax,%r14 - 40d45d: 74 08 je 40d467 <__gettextparse+0x237> - 40d45f: 4c 89 f7 mov %r14,%rdi - 40d462: e8 49 09 01 00 callq 41ddb0 <__cfree> - 40d467: 48 81 c4 28 08 00 00 add $0x828,%rsp - 40d46e: 89 d8 mov %ebx,%eax - 40d470: 5b pop %rbx - 40d471: 5d pop %rbp - 40d472: 41 5c pop %r12 - 40d474: 41 5d pop %r13 - 40d476: 41 5e pop %r14 - 40d478: 41 5f pop %r15 - 40d47a: c3 retq - 40d47b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 40d480: 48 8b 03 mov (%rbx),%rax - 40d483: 48 8b 53 f0 mov -0x10(%rbx),%rdx - 40d487: 48 8d 74 24 30 lea 0x30(%rsp),%rsi - 40d48c: 8b 7b f8 mov -0x8(%rbx),%edi - 40d48f: 48 89 4c 24 10 mov %rcx,0x10(%rsp) - 40d494: 48 89 54 24 30 mov %rdx,0x30(%rsp) - 40d499: 48 89 44 24 38 mov %rax,0x38(%rsp) - 40d49e: e8 2d 8e ff ff callq 4062d0 - 40d4a3: 4a 8d 3c fd 00 00 00 lea 0x0(,%r15,8),%rdi - 40d4aa: 00 - 40d4ab: 4b 8d 14 3f lea (%r15,%r15,1),%rdx - 40d4af: 48 8b 4c 24 10 mov 0x10(%rsp),%rcx - 40d4b4: be ff ff ff ff mov $0xffffffff,%esi - 40d4b9: 41 b8 02 00 00 00 mov $0x2,%r8d - 40d4bf: 48 f7 df neg %rdi - 40d4c2: 48 f7 da neg %rdx - 40d4c5: 48 01 df add %rbx,%rdi - 40d4c8: 49 01 d6 add %rdx,%r14 - 40d4cb: 48 89 47 08 mov %rax,0x8(%rdi) - 40d4cf: 41 0f bf 06 movswl (%r14),%eax - 40d4d3: 48 8d 5f 08 lea 0x8(%rdi),%rbx - 40d4d7: 89 c2 mov %eax,%edx - 40d4d9: 01 f0 add %esi,%eax - 40d4db: 83 f8 36 cmp $0x36,%eax - 40d4de: 77 13 ja 40d4f3 <__gettextparse+0x2c3> - 40d4e0: 48 98 cltq - 40d4e2: 66 0f be b0 a0 16 4a movsbw 0x4a16a0(%rax),%si - 40d4e9: 00 - 40d4ea: 66 39 f2 cmp %si,%dx - 40d4ed: 0f 84 5b 02 00 00 je 40d74e <__gettextparse+0x51e> - 40d4f3: 4d 63 c0 movslq %r8d,%r8 - 40d4f6: 45 0f be a8 3b 17 4a movsbl 0x4a173b(%r8),%r13d - 40d4fd: 00 - 40d4fe: 49 83 c6 02 add $0x2,%r14 - 40d502: e9 6c fd ff ff jmpq 40d273 <__gettextparse+0x43> - 40d507: 49 8d 79 02 lea 0x2(%r9),%rdi - 40d50b: 48 8b 74 24 18 mov 0x18(%rsp),%rsi - 40d510: 45 85 e4 test %r12d,%r12d - 40d513: 48 89 3e mov %rdi,(%rsi) - 40d516: 7e 1f jle 40d537 <__gettextparse+0x307> - 40d518: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 40d51f: 00 - 40d520: 49 63 d4 movslq %r12d,%rdx - 40d523: 0f b6 b2 80 17 4a 00 movzbl 0x4a1780(%rdx),%esi - 40d52a: e9 5e fe ff ff jmpq 40d38d <__gettextparse+0x15d> - 40d52f: 48 8b 74 24 18 mov 0x18(%rsp),%rsi - 40d534: 4c 89 0e mov %r9,(%rsi) - 40d537: 31 f6 xor %esi,%esi - 40d539: 45 31 e4 xor %r12d,%r12d - 40d53c: e9 4c fe ff ff jmpq 40d38d <__gettextparse+0x15d> - 40d541: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 40d548: 41 83 fc 00 cmp $0x0,%r12d - 40d54c: 0f 8e 09 02 00 00 jle 40d75b <__gettextparse+0x52b> - 40d552: 41 bc fe ff ff ff mov $0xfffffffe,%r12d - 40d558: e9 b3 fe ff ff jmpq 40d410 <__gettextparse+0x1e0> - 40d55d: 0f 1f 00 nopl (%rax) - 40d560: 44 0f b6 aa e0 16 4a movzbl 0x4a16e0(%rdx),%r13d - 40d567: 00 - 40d568: 45 85 ed test %r13d,%r13d - 40d56b: 0f 84 c8 01 00 00 je 40d739 <__gettextparse+0x509> - 40d571: 8b 44 24 0c mov 0xc(%rsp),%eax - 40d575: 41 bc fe ff ff ff mov $0xfffffffe,%r12d - 40d57b: 83 f8 01 cmp $0x1,%eax - 40d57e: 83 d0 ff adc $0xffffffff,%eax - 40d581: 48 83 c3 08 add $0x8,%rbx - 40d585: 89 44 24 0c mov %eax,0xc(%rsp) - 40d589: 48 8b 44 24 28 mov 0x28(%rsp),%rax - 40d58e: 48 89 03 mov %rax,(%rbx) - 40d591: e9 68 ff ff ff jmpq 40d4fe <__gettextparse+0x2ce> - 40d596: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 40d59d: 00 00 00 - 40d5a0: 48 8b 74 24 18 mov 0x18(%rsp),%rsi - 40d5a5: 4c 8b 0e mov (%rsi),%r9 - 40d5a8: 41 0f b6 11 movzbl (%r9),%edx - 40d5ac: 84 d2 test %dl,%dl - 40d5ae: 74 84 je 40d534 <__gettextparse+0x304> - 40d5b0: 80 fa 09 cmp $0x9,%dl - 40d5b3: 74 0b je 40d5c0 <__gettextparse+0x390> - 40d5b5: 80 fa 20 cmp $0x20,%dl - 40d5b8: 75 20 jne 40d5da <__gettextparse+0x3aa> - 40d5ba: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 40d5c0: 49 83 c1 01 add $0x1,%r9 - 40d5c4: 41 0f b6 11 movzbl (%r9),%edx - 40d5c8: 84 d2 test %dl,%dl - 40d5ca: 0f 84 5f ff ff ff je 40d52f <__gettextparse+0x2ff> - 40d5d0: 80 fa 20 cmp $0x20,%dl - 40d5d3: 74 eb je 40d5c0 <__gettextparse+0x390> - 40d5d5: 80 fa 09 cmp $0x9,%dl - 40d5d8: 74 e6 je 40d5c0 <__gettextparse+0x390> - 40d5da: 80 fa 7c cmp $0x7c,%dl - 40d5dd: 49 8d 79 01 lea 0x1(%r9),%rdi - 40d5e1: 44 0f be e2 movsbl %dl,%r12d - 40d5e5: 0f 87 c0 01 00 00 ja 40d7ab <__gettextparse+0x57b> - 40d5eb: 0f b6 d2 movzbl %dl,%edx - 40d5ee: ff 24 d5 b0 12 4a 00 jmpq *0x4a12b0(,%rdx,8) - 40d5f5: 48 8b 13 mov (%rbx),%rdx - 40d5f8: 48 85 d2 test %rdx,%rdx - 40d5fb: 0f 84 60 01 00 00 je 40d761 <__gettextparse+0x531> - 40d601: 48 8b 74 24 18 mov 0x18(%rsp),%rsi - 40d606: 4a 8d 3c fd 00 00 00 lea 0x0(,%r15,8),%rdi - 40d60d: 00 - 40d60e: 41 b8 01 00 00 00 mov $0x1,%r8d - 40d614: 48 f7 df neg %rdi - 40d617: 48 89 56 08 mov %rdx,0x8(%rsi) - 40d61b: 4b 8d 14 3f lea (%r15,%r15,1),%rdx - 40d61f: be f6 ff ff ff mov $0xfffffff6,%esi - 40d624: 48 f7 da neg %rdx - 40d627: e9 99 fe ff ff jmpq 40d4c5 <__gettextparse+0x295> - 40d62c: 48 8b 53 f0 mov -0x10(%rbx),%rdx - 40d630: 48 8b 73 e0 mov -0x20(%rbx),%rsi - 40d634: bf 03 00 00 00 mov $0x3,%edi - 40d639: 48 8b 03 mov (%rbx),%rax - 40d63c: 48 89 4c 24 10 mov %rcx,0x10(%rsp) - 40d641: 48 89 54 24 38 mov %rdx,0x38(%rsp) - 40d646: 48 8d 54 24 30 lea 0x30(%rsp),%rdx - 40d64b: 48 89 74 24 30 mov %rsi,0x30(%rsp) - 40d650: be 10 00 00 00 mov $0x10,%esi - 40d655: 48 89 44 24 40 mov %rax,0x40(%rsp) - 40d65a: e8 01 c4 ff ff callq 409a60 - 40d65f: e9 3f fe ff ff jmpq 40d4a3 <__gettextparse+0x273> - 40d664: 48 8b 03 mov (%rbx),%rax - 40d667: 48 8b 53 f0 mov -0x10(%rbx),%rdx - 40d66b: 48 8d 74 24 30 lea 0x30(%rsp),%rsi - 40d670: 48 89 4c 24 10 mov %rcx,0x10(%rsp) - 40d675: bf 0f 00 00 00 mov $0xf,%edi - 40d67a: 48 89 54 24 30 mov %rdx,0x30(%rsp) - 40d67f: 48 89 44 24 38 mov %rax,0x38(%rsp) - 40d684: e9 15 fe ff ff jmpq 40d49e <__gettextparse+0x26e> - 40d689: 48 8b 03 mov (%rbx),%rax - 40d68c: 48 8b 53 f0 mov -0x10(%rbx),%rdx - 40d690: 48 8d 74 24 30 lea 0x30(%rsp),%rsi - 40d695: 48 89 4c 24 10 mov %rcx,0x10(%rsp) - 40d69a: bf 0e 00 00 00 mov $0xe,%edi - 40d69f: 48 89 54 24 30 mov %rdx,0x30(%rsp) - 40d6a4: 48 89 44 24 38 mov %rax,0x38(%rsp) - 40d6a9: e9 f0 fd ff ff jmpq 40d49e <__gettextparse+0x26e> - 40d6ae: 48 8b 43 f8 mov -0x8(%rbx),%rax - 40d6b2: 4a 8d 3c fd 00 00 00 lea 0x0(,%r15,8),%rdi - 40d6b9: 00 - 40d6ba: 4b 8d 14 3f lea (%r15,%r15,1),%rdx - 40d6be: be ff ff ff ff mov $0xffffffff,%esi - 40d6c3: 41 b8 02 00 00 00 mov $0x2,%r8d - 40d6c9: 48 f7 df neg %rdi - 40d6cc: 48 f7 da neg %rdx - 40d6cf: e9 f1 fd ff ff jmpq 40d4c5 <__gettextparse+0x295> - 40d6d4: 48 8b 03 mov (%rbx),%rax - 40d6d7: 48 8d 54 24 30 lea 0x30(%rsp),%rdx - 40d6dc: be 02 00 00 00 mov $0x2,%esi - 40d6e1: bf 01 00 00 00 mov $0x1,%edi - 40d6e6: 48 89 4c 24 10 mov %rcx,0x10(%rsp) - 40d6eb: 48 89 44 24 30 mov %rax,0x30(%rsp) - 40d6f0: e8 6b c3 ff ff callq 409a60 - 40d6f5: e9 a9 fd ff ff jmpq 40d4a3 <__gettextparse+0x273> - 40d6fa: 31 d2 xor %edx,%edx - 40d6fc: 31 ff xor %edi,%edi - 40d6fe: be 01 00 00 00 mov $0x1,%esi - 40d703: 48 89 4c 24 10 mov %rcx,0x10(%rsp) - 40d708: e8 53 c3 ff ff callq 409a60 - 40d70d: 48 85 c0 test %rax,%rax - 40d710: 48 8b 4c 24 10 mov 0x10(%rsp),%rcx - 40d715: 0f 84 b8 02 00 00 je 40d9d3 <__gettextparse+0x7a3> - 40d71b: 48 8b 13 mov (%rbx),%rdx - 40d71e: 48 89 50 08 mov %rdx,0x8(%rax) - 40d722: eb 8e jmp 40d6b2 <__gettextparse+0x482> - 40d724: 31 d2 xor %edx,%edx - 40d726: 31 f6 xor %esi,%esi - 40d728: 31 ff xor %edi,%edi - 40d72a: 48 89 4c 24 10 mov %rcx,0x10(%rsp) - 40d72f: e8 2c c3 ff ff callq 409a60 - 40d734: e9 6a fd ff ff jmpq 40d4a3 <__gettextparse+0x273> - 40d739: 48 8b 43 08 mov 0x8(%rbx),%rax - 40d73d: 31 f6 xor %esi,%esi - 40d73f: 41 b8 f0 ff ff ff mov $0xfffffff0,%r8d - 40d745: 31 d2 xor %edx,%edx - 40d747: 31 ff xor %edi,%edi - 40d749: e9 77 fd ff ff jmpq 40d4c5 <__gettextparse+0x295> - 40d74e: 44 0f b6 a8 e0 16 4a movzbl 0x4a16e0(%rax),%r13d - 40d755: 00 - 40d756: e9 a3 fd ff ff jmpq 40d4fe <__gettextparse+0x2ce> - 40d75b: 0f 85 af fc ff ff jne 40d410 <__gettextparse+0x1e0> - 40d761: 49 89 ce mov %rcx,%r14 - 40d764: bb 01 00 00 00 mov $0x1,%ebx - 40d769: e9 e7 fc ff ff jmpq 40d455 <__gettextparse+0x225> - 40d76e: 44 0f b6 86 70 17 4a movzbl 0x4a1770(%rsi),%r8d - 40d775: 00 - 40d776: 4a 8d 3c fd 00 00 00 lea 0x0(,%r15,8),%rdi - 40d77d: 00 - 40d77e: 4d 01 ff add %r15,%r15 - 40d781: 4c 89 fa mov %r15,%rdx - 40d784: 48 f7 df neg %rdi - 40d787: 48 f7 da neg %rdx - 40d78a: 41 83 e8 10 sub $0x10,%r8d - 40d78e: 49 63 f0 movslq %r8d,%rsi - 40d791: 0f be b6 17 17 4a 00 movsbl 0x4a1717(%rsi),%esi - 40d798: e9 28 fd ff ff jmpq 40d4c5 <__gettextparse+0x295> - 40d79d: 41 0f be 51 01 movsbl 0x1(%r9),%edx - 40d7a2: 41 39 d4 cmp %edx,%r12d - 40d7a5: 0f 84 5c fd ff ff je 40d507 <__gettextparse+0x2d7> - 40d7ab: be 01 00 00 00 mov $0x1,%esi - 40d7b0: 41 bc 00 01 00 00 mov $0x100,%r12d - 40d7b6: 48 8b 54 24 18 mov 0x18(%rsp),%rdx - 40d7bb: 48 89 3a mov %rdi,(%rdx) - 40d7be: e9 ca fb ff ff jmpq 40d38d <__gettextparse+0x15d> - 40d7c3: 48 ba 00 00 00 00 ff movabs $0xffffffff00000000,%rdx - 40d7ca: ff ff ff - 40d7cd: 48 23 54 24 28 and 0x28(%rsp),%rdx - 40d7d2: be 09 00 00 00 mov $0x9,%esi - 40d7d7: 41 bc 05 01 00 00 mov $0x105,%r12d - 40d7dd: 48 83 ca 05 or $0x5,%rdx - 40d7e1: 48 89 54 24 28 mov %rdx,0x28(%rsp) - 40d7e6: eb ce jmp 40d7b6 <__gettextparse+0x586> - 40d7e8: 41 80 79 01 3d cmpb $0x3d,0x1(%r9) - 40d7ed: 0f 85 18 fd ff ff jne 40d50b <__gettextparse+0x2db> - 40d7f3: 48 ba 00 00 00 00 ff movabs $0xffffffff00000000,%rdx - 40d7fa: ff ff ff - 40d7fd: 48 23 54 24 28 and 0x28(%rsp),%rdx - 40d802: 49 8d 79 02 lea 0x2(%r9),%rdi - 40d806: be 06 00 00 00 mov $0x6,%esi - 40d80b: 41 bc 02 01 00 00 mov $0x102,%r12d - 40d811: 48 83 ca 0d or $0xd,%rdx - 40d815: 48 89 54 24 28 mov %rdx,0x28(%rsp) - 40d81a: eb 9a jmp 40d7b6 <__gettextparse+0x586> - 40d81c: 41 80 79 01 3d cmpb $0x3d,0x1(%r9) - 40d821: 0f 84 d0 01 00 00 je 40d9f7 <__gettextparse+0x7c7> - 40d827: 48 ba 00 00 00 00 ff movabs $0xffffffff00000000,%rdx - 40d82e: ff ff ff - 40d831: 48 23 54 24 28 and 0x28(%rsp),%rdx - 40d836: be 07 00 00 00 mov $0x7,%esi - 40d83b: 41 bc 03 01 00 00 mov $0x103,%r12d - 40d841: 48 83 ca 09 or $0x9,%rdx - 40d845: 48 89 54 24 28 mov %rdx,0x28(%rsp) - 40d84a: e9 67 ff ff ff jmpq 40d7b6 <__gettextparse+0x586> - 40d84f: 41 80 79 01 3d cmpb $0x3d,0x1(%r9) - 40d854: be 01 00 00 00 mov $0x1,%esi - 40d859: 41 bc 00 01 00 00 mov $0x100,%r12d - 40d85f: 0f 85 51 ff ff ff jne 40d7b6 <__gettextparse+0x586> - 40d865: 48 ba 00 00 00 00 ff movabs $0xffffffff00000000,%rdx - 40d86c: ff ff ff - 40d86f: 48 23 54 24 28 and 0x28(%rsp),%rdx - 40d874: 49 8d 79 02 lea 0x2(%r9),%rdi - 40d878: be 06 00 00 00 mov $0x6,%esi - 40d87d: 41 bc 02 01 00 00 mov $0x102,%r12d - 40d883: 48 83 ca 0c or $0xc,%rdx - 40d887: 48 89 54 24 28 mov %rdx,0x28(%rsp) - 40d88c: e9 25 ff ff ff jmpq 40d7b6 <__gettextparse+0x586> - 40d891: 41 80 79 01 3d cmpb $0x3d,0x1(%r9) - 40d896: 0f 84 87 01 00 00 je 40da23 <__gettextparse+0x7f3> - 40d89c: 48 ba 00 00 00 00 ff movabs $0xffffffff00000000,%rdx - 40d8a3: ff ff ff - 40d8a6: 48 23 54 24 28 and 0x28(%rsp),%rdx - 40d8ab: be 07 00 00 00 mov $0x7,%esi - 40d8b0: 41 bc 03 01 00 00 mov $0x103,%r12d - 40d8b6: 48 83 ca 08 or $0x8,%rdx - 40d8ba: 48 89 54 24 28 mov %rdx,0x28(%rsp) - 40d8bf: e9 f2 fe ff ff jmpq 40d7b6 <__gettextparse+0x586> - 40d8c4: 41 0f be 51 01 movsbl 0x1(%r9),%edx - 40d8c9: 41 8d 74 24 d0 lea -0x30(%r12),%esi - 40d8ce: 48 63 f6 movslq %esi,%rsi - 40d8d1: 44 8d 4a d0 lea -0x30(%rdx),%r9d - 40d8d5: 41 80 f9 09 cmp $0x9,%r9b - 40d8d9: 77 1f ja 40d8fa <__gettextparse+0x6ca> - 40d8db: 83 ea 30 sub $0x30,%edx - 40d8de: 48 8d 34 b6 lea (%rsi,%rsi,4),%rsi - 40d8e2: 48 83 c7 01 add $0x1,%rdi - 40d8e6: 48 63 d2 movslq %edx,%rdx - 40d8e9: 48 8d 34 72 lea (%rdx,%rsi,2),%rsi - 40d8ed: 0f be 17 movsbl (%rdi),%edx - 40d8f0: 44 8d 4a d0 lea -0x30(%rdx),%r9d - 40d8f4: 41 80 f9 09 cmp $0x9,%r9b - 40d8f8: 76 e1 jbe 40d8db <__gettextparse+0x6ab> - 40d8fa: 48 89 74 24 28 mov %rsi,0x28(%rsp) - 40d8ff: 41 bc 06 01 00 00 mov $0x106,%r12d - 40d905: be 0b 00 00 00 mov $0xb,%esi - 40d90a: e9 a7 fe ff ff jmpq 40d7b6 <__gettextparse+0x586> - 40d90f: 48 ba 00 00 00 00 ff movabs $0xffffffff00000000,%rdx - 40d916: ff ff ff - 40d919: 48 23 54 24 28 and 0x28(%rsp),%rdx - 40d91e: be 09 00 00 00 mov $0x9,%esi - 40d923: 41 bc 05 01 00 00 mov $0x105,%r12d - 40d929: 48 83 ca 04 or $0x4,%rdx - 40d92d: 48 89 54 24 28 mov %rdx,0x28(%rsp) - 40d932: e9 7f fe ff ff jmpq 40d7b6 <__gettextparse+0x586> - 40d937: 48 ba 00 00 00 00 ff movabs $0xffffffff00000000,%rdx - 40d93e: ff ff ff - 40d941: 48 23 54 24 28 and 0x28(%rsp),%rdx - 40d946: be 08 00 00 00 mov $0x8,%esi - 40d94b: 41 bc 04 01 00 00 mov $0x104,%r12d - 40d951: 48 83 ca 06 or $0x6,%rdx - 40d955: 48 89 54 24 28 mov %rdx,0x28(%rsp) - 40d95a: e9 57 fe ff ff jmpq 40d7b6 <__gettextparse+0x586> - 40d95f: 48 ba 00 00 00 00 ff movabs $0xffffffff00000000,%rdx - 40d966: ff ff ff - 40d969: 48 23 54 24 28 and 0x28(%rsp),%rdx - 40d96e: be 09 00 00 00 mov $0x9,%esi - 40d973: 41 bc 05 01 00 00 mov $0x105,%r12d - 40d979: 48 83 ca 03 or $0x3,%rdx - 40d97d: 48 89 54 24 28 mov %rdx,0x28(%rsp) - 40d982: e9 2f fe ff ff jmpq 40d7b6 <__gettextparse+0x586> - 40d987: 48 ba 00 00 00 00 ff movabs $0xffffffff00000000,%rdx - 40d98e: ff ff ff - 40d991: 48 23 54 24 28 and 0x28(%rsp),%rdx - 40d996: be 08 00 00 00 mov $0x8,%esi - 40d99b: 41 bc 04 01 00 00 mov $0x104,%r12d - 40d9a1: 48 83 ca 07 or $0x7,%rdx - 40d9a5: 48 89 54 24 28 mov %rdx,0x28(%rsp) - 40d9aa: e9 07 fe ff ff jmpq 40d7b6 <__gettextparse+0x586> - 40d9af: 49 89 ce mov %rcx,%r14 - 40d9b2: bb 02 00 00 00 mov $0x2,%ebx - 40d9b7: e9 99 fa ff ff jmpq 40d455 <__gettextparse+0x225> - 40d9bc: 49 89 ce mov %rcx,%r14 - 40d9bf: 31 db xor %ebx,%ebx - 40d9c1: e9 8f fa ff ff jmpq 40d455 <__gettextparse+0x225> - 40d9c6: 4d 89 fe mov %r15,%r14 - 40d9c9: bb 01 00 00 00 mov $0x1,%ebx - 40d9ce: e9 82 fa ff ff jmpq 40d455 <__gettextparse+0x225> - 40d9d3: 4a 8d 3c fd 00 00 00 lea 0x0(,%r15,8),%rdi - 40d9da: 00 - 40d9db: 4d 01 ff add %r15,%r15 - 40d9de: be ff ff ff ff mov $0xffffffff,%esi - 40d9e3: 4c 89 fa mov %r15,%rdx - 40d9e6: 41 b8 02 00 00 00 mov $0x2,%r8d - 40d9ec: 48 f7 df neg %rdi - 40d9ef: 48 f7 da neg %rdx - 40d9f2: e9 ce fa ff ff jmpq 40d4c5 <__gettextparse+0x295> - 40d9f7: 48 ba 00 00 00 00 ff movabs $0xffffffff00000000,%rdx - 40d9fe: ff ff ff - 40da01: 48 23 54 24 28 and 0x28(%rsp),%rdx - 40da06: 49 8d 79 02 lea 0x2(%r9),%rdi - 40da0a: be 07 00 00 00 mov $0x7,%esi - 40da0f: 41 bc 03 01 00 00 mov $0x103,%r12d - 40da15: 48 83 ca 0b or $0xb,%rdx - 40da19: 48 89 54 24 28 mov %rdx,0x28(%rsp) - 40da1e: e9 93 fd ff ff jmpq 40d7b6 <__gettextparse+0x586> - 40da23: 48 ba 00 00 00 00 ff movabs $0xffffffff00000000,%rdx - 40da2a: ff ff ff - 40da2d: 48 23 54 24 28 and 0x28(%rsp),%rdx - 40da32: 49 8d 79 02 lea 0x2(%r9),%rdi - 40da36: be 07 00 00 00 mov $0x7,%esi - 40da3b: 41 bc 03 01 00 00 mov $0x103,%r12d - 40da41: 48 83 ca 0a or $0xa,%rdx - 40da45: 48 89 54 24 28 mov %rdx,0x28(%rsp) - 40da4a: e9 67 fd ff ff jmpq 40d7b6 <__gettextparse+0x586> - 40da4f: 90 nop - -000000000040da50 <__gettext_extract_plural>: - 40da50: 41 55 push %r13 - 40da52: 41 54 push %r12 - 40da54: 55 push %rbp - 40da55: 53 push %rbx - 40da56: 48 89 f5 mov %rsi,%rbp - 40da59: 48 89 d3 mov %rdx,%rbx - 40da5c: 48 83 ec 28 sub $0x28,%rsp - 40da60: 48 85 ff test %rdi,%rdi - 40da63: 0f 84 9f 00 00 00 je 40db08 <__gettext_extract_plural+0xb8> - 40da69: 49 89 fd mov %rdi,%r13 - 40da6c: be 87 18 4a 00 mov $0x4a1887,%esi - 40da71: e8 aa 28 ff ff callq 400320 <__rela_iplt_end+0x58> - 40da76: be 8f 18 4a 00 mov $0x4a188f,%esi - 40da7b: 49 89 c4 mov %rax,%r12 - 40da7e: 4c 89 ef mov %r13,%rdi - 40da81: e8 9a 28 ff ff callq 400320 <__rela_iplt_end+0x58> - 40da86: 4d 85 e4 test %r12,%r12 - 40da89: 74 7d je 40db08 <__gettext_extract_plural+0xb8> - 40da8b: 48 85 c0 test %rax,%rax - 40da8e: 74 78 je 40db08 <__gettext_extract_plural+0xb8> - 40da90: 4c 8d 68 09 lea 0x9(%rax),%r13 - 40da94: 0f b6 40 09 movzbl 0x9(%rax),%eax - 40da98: 84 c0 test %al,%al - 40da9a: 74 6c je 40db08 <__gettext_extract_plural+0xb8> - 40da9c: 48 c7 c2 f0 ff ff ff mov $0xfffffffffffffff0,%rdx - 40daa3: 64 48 8b 0a mov %fs:(%rdx),%rcx - 40daa7: eb 14 jmp 40dabd <__gettext_extract_plural+0x6d> - 40daa9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 40dab0: 49 83 c5 01 add $0x1,%r13 - 40dab4: 41 0f b6 45 00 movzbl 0x0(%r13),%eax - 40dab9: 84 c0 test %al,%al - 40dabb: 74 4b je 40db08 <__gettext_extract_plural+0xb8> - 40dabd: 0f b6 d0 movzbl %al,%edx - 40dac0: f6 44 51 01 20 testb $0x20,0x1(%rcx,%rdx,2) - 40dac5: 75 e9 jne 40dab0 <__gettext_extract_plural+0x60> - 40dac7: 83 e8 30 sub $0x30,%eax - 40daca: 3c 09 cmp $0x9,%al - 40dacc: 77 3a ja 40db08 <__gettext_extract_plural+0xb8> - 40dace: 48 8d 74 24 08 lea 0x8(%rsp),%rsi - 40dad3: ba 0a 00 00 00 mov $0xa,%edx - 40dad8: 4c 89 ef mov %r13,%rdi - 40dadb: e8 70 11 00 00 callq 40ec50 <__strtoul> - 40dae0: 4c 39 6c 24 08 cmp %r13,0x8(%rsp) - 40dae5: 74 21 je 40db08 <__gettext_extract_plural+0xb8> - 40dae7: 48 8d 7c 24 10 lea 0x10(%rsp),%rdi - 40daec: 49 83 c4 07 add $0x7,%r12 - 40daf0: 48 89 03 mov %rax,(%rbx) - 40daf3: 4c 89 64 24 10 mov %r12,0x10(%rsp) - 40daf8: e8 33 f7 ff ff callq 40d230 <__gettextparse> - 40dafd: 85 c0 test %eax,%eax - 40daff: 74 21 je 40db22 <__gettext_extract_plural+0xd2> - 40db01: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 40db08: 48 c7 45 00 a0 18 4a movq $0x4a18a0,0x0(%rbp) - 40db0f: 00 - 40db10: 48 c7 03 02 00 00 00 movq $0x2,(%rbx) - 40db17: 48 83 c4 28 add $0x28,%rsp - 40db1b: 5b pop %rbx - 40db1c: 5d pop %rbp - 40db1d: 41 5c pop %r12 - 40db1f: 41 5d pop %r13 - 40db21: c3 retq - 40db22: 48 8b 44 24 18 mov 0x18(%rsp),%rax - 40db27: 48 89 45 00 mov %rax,0x0(%rbp) - 40db2b: eb ea jmp 40db17 <__gettext_extract_plural+0xc7> - 40db2d: 0f 1f 00 nopl (%rax) - -000000000040db30 <__hash_string>: - 40db30: 31 c0 xor %eax,%eax - 40db32: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 40db38: 0f b6 17 movzbl (%rdi),%edx - 40db3b: 84 d2 test %dl,%dl - 40db3d: 74 27 je 40db66 <__hash_string+0x36> - 40db3f: 48 c1 e0 04 shl $0x4,%rax - 40db43: 48 83 c7 01 add $0x1,%rdi - 40db47: 48 01 d0 add %rdx,%rax - 40db4a: 48 89 c2 mov %rax,%rdx - 40db4d: 81 e2 00 00 00 f0 and $0xf0000000,%edx - 40db53: 74 e3 je 40db38 <__hash_string+0x8> - 40db55: 48 31 d0 xor %rdx,%rax - 40db58: 48 c1 ea 18 shr $0x18,%rdx - 40db5c: 48 31 d0 xor %rdx,%rax - 40db5f: 0f b6 17 movzbl (%rdi),%edx - 40db62: 84 d2 test %dl,%dl - 40db64: 75 d9 jne 40db3f <__hash_string+0xf> - 40db66: f3 c3 repz retq - 40db68: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 40db6f: 00 - -000000000040db70 <_setjmp>: - 40db70: 31 f6 xor %esi,%esi - 40db72: e9 b9 18 04 00 jmpq 44f430 <__sigsetjmp> - 40db77: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 40db7e: 00 00 - -000000000040db80 : - 40db80: 64 8b 0c 25 d4 02 00 mov %fs:0x2d4,%ecx - 40db87: 00 - 40db88: 64 8b 04 25 d0 02 00 mov %fs:0x2d0,%eax - 40db8f: 00 - 40db90: 48 63 f0 movslq %eax,%rsi - 40db93: 85 f6 test %esi,%esi - 40db95: 75 31 jne 40dbc8 - 40db97: b8 ba 00 00 00 mov $0xba,%eax - 40db9c: 0f 05 syscall - 40db9e: 89 c1 mov %eax,%ecx - 40dba0: 64 89 04 25 d0 02 00 mov %eax,%fs:0x2d0 - 40dba7: 00 - 40dba8: 48 63 f0 movslq %eax,%rsi - 40dbab: 48 63 d7 movslq %edi,%rdx - 40dbae: b8 ea 00 00 00 mov $0xea,%eax - 40dbb3: 48 63 f9 movslq %ecx,%rdi - 40dbb6: 0f 05 syscall - 40dbb8: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 40dbbe: 77 20 ja 40dbe0 - 40dbc0: f3 c3 repz retq - 40dbc2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 40dbc8: 85 c9 test %ecx,%ecx - 40dbca: 7f df jg 40dbab - 40dbcc: 89 ca mov %ecx,%edx - 40dbce: f7 da neg %edx - 40dbd0: 81 e1 ff ff ff 7f and $0x7fffffff,%ecx - 40dbd6: 0f 44 d6 cmove %esi,%edx - 40dbd9: 89 d1 mov %edx,%ecx - 40dbdb: eb ce jmp 40dbab - 40dbdd: 0f 1f 00 nopl (%rax) - 40dbe0: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx - 40dbe7: f7 d8 neg %eax - 40dbe9: 64 89 02 mov %eax,%fs:(%rdx) - 40dbec: b8 ff ff ff ff mov $0xffffffff,%eax - 40dbf1: c3 retq - 40dbf2: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 40dbf9: 00 00 00 - 40dbfc: 0f 1f 40 00 nopl 0x0(%rax) - -000000000040dc00 : - 40dc00: 48 81 ec 28 01 00 00 sub $0x128,%rsp - 40dc07: 64 48 8b 14 25 10 00 mov %fs:0x10,%rdx - 40dc0e: 00 00 - 40dc10: 48 3b 15 21 e5 2b 00 cmp 0x2be521(%rip),%rdx # 6cc138 - 40dc17: 74 46 je 40dc5f - 40dc19: be 01 00 00 00 mov $0x1,%esi - 40dc1e: 31 c0 xor %eax,%eax - 40dc20: 83 3d 95 f5 2b 00 00 cmpl $0x0,0x2bf595(%rip) # 6cd1bc <__libc_multiple_threads> - 40dc27: 74 0c je 40dc35 - 40dc29: f0 0f b1 35 ff e4 2b lock cmpxchg %esi,0x2be4ff(%rip) # 6cc130 - 40dc30: 00 - 40dc31: 75 0b jne 40dc3e - 40dc33: eb 23 jmp 40dc58 - 40dc35: 0f b1 35 f4 e4 2b 00 cmpxchg %esi,0x2be4f4(%rip) # 6cc130 - 40dc3c: 74 1a je 40dc58 - 40dc3e: 48 8d 3d eb e4 2b 00 lea 0x2be4eb(%rip),%rdi # 6cc130 - 40dc45: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 40dc4c: e8 7f 49 03 00 callq 4425d0 <__lll_lock_wait_private> - 40dc51: 48 81 c4 80 00 00 00 add $0x80,%rsp - 40dc58: 48 89 15 d9 e4 2b 00 mov %rdx,0x2be4d9(%rip) # 6cc138 - 40dc5f: 8b 05 db e4 2b 00 mov 0x2be4db(%rip),%eax # 6cc140 - 40dc65: 83 05 c8 e4 2b 00 01 addl $0x1,0x2be4c8(%rip) # 6cc134 - 40dc6c: 85 c0 test %eax,%eax - 40dc6e: 74 43 je 40dcb3 - 40dc70: 83 f8 01 cmp $0x1,%eax - 40dc73: 74 77 je 40dcec - 40dc75: 83 f8 02 cmp $0x2,%eax - 40dc78: 0f 84 8e 00 00 00 je 40dd0c - 40dc7e: 83 f8 03 cmp $0x3,%eax - 40dc81: 0f 84 42 01 00 00 je 40ddc9 - 40dc87: 83 f8 04 cmp $0x4,%eax - 40dc8a: 0f 84 05 02 00 00 je 40de95 - 40dc90: 83 f8 05 cmp $0x5,%eax - 40dc93: 0f 84 1a 02 00 00 je 40deb3 - 40dc99: 83 f8 06 cmp $0x6,%eax - 40dc9c: 0f 84 34 02 00 00 je 40ded6 - 40dca2: 83 f8 07 cmp $0x7,%eax - 40dca5: 0f 84 2c 02 00 00 je 40ded7 - 40dcab: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 40dcb0: f4 hlt - 40dcb1: eb fd jmp 40dcb0 - 40dcb3: 31 c0 xor %eax,%eax - 40dcb5: b9 10 00 00 00 mov $0x10,%ecx - 40dcba: 48 89 e7 mov %rsp,%rdi - 40dcbd: f3 48 ab rep stos %rax,%es:(%rdi) - 40dcc0: 31 d2 xor %edx,%edx - 40dcc2: 48 89 e6 mov %rsp,%rsi - 40dcc5: bf 01 00 00 00 mov $0x1,%edi - 40dcca: c7 05 6c e4 2b 00 01 movl $0x1,0x2be46c(%rip) # 6cc140 - 40dcd1: 00 00 00 - 40dcd4: 48 c7 04 24 20 00 00 movq $0x20,(%rsp) - 40dcdb: 00 - 40dcdc: e8 5f 1a 04 00 callq 44f740 <__sigprocmask> - 40dce1: 8b 05 59 e4 2b 00 mov 0x2be459(%rip),%eax # 6cc140 - 40dce7: 83 f8 01 cmp $0x1,%eax - 40dcea: 75 89 jne 40dc75 - 40dcec: 31 ff xor %edi,%edi - 40dcee: c7 05 48 e4 2b 00 02 movl $0x2,0x2be448(%rip) # 6cc140 - 40dcf5: 00 00 00 - 40dcf8: e8 03 7d 00 00 callq 415a00 <_IO_flush_all_lockp> - 40dcfd: 8b 05 3d e4 2b 00 mov 0x2be43d(%rip),%eax # 6cc140 - 40dd03: 83 f8 02 cmp $0x2,%eax - 40dd06: 0f 85 72 ff ff ff jne 40dc7e - 40dd0c: 83 2d 21 e4 2b 00 01 subl $0x1,0x2be421(%rip) # 6cc134 - 40dd13: c7 05 23 e4 2b 00 00 movl $0x0,0x2be423(%rip) # 6cc140 - 40dd1a: 00 00 00 - 40dd1d: 75 41 jne 40dd60 - 40dd1f: 48 c7 05 0e e4 2b 00 movq $0x0,0x2be40e(%rip) # 6cc138 - 40dd26: 00 00 00 00 - 40dd2a: 83 3d 8b f4 2b 00 00 cmpl $0x0,0x2bf48b(%rip) # 6cd1bc <__libc_multiple_threads> - 40dd31: 74 0b je 40dd3e - 40dd33: f0 ff 0d f6 e3 2b 00 lock decl 0x2be3f6(%rip) # 6cc130 - 40dd3a: 75 0a jne 40dd46 - 40dd3c: eb 22 jmp 40dd60 - 40dd3e: ff 0d ec e3 2b 00 decl 0x2be3ec(%rip) # 6cc130 - 40dd44: 74 1a je 40dd60 - 40dd46: 48 8d 3d e3 e3 2b 00 lea 0x2be3e3(%rip),%rdi # 6cc130 - 40dd4d: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 40dd54: e8 a7 48 03 00 callq 442600 <__lll_unlock_wake_private> - 40dd59: 48 81 c4 80 00 00 00 add $0x80,%rsp - 40dd60: bf 06 00 00 00 mov $0x6,%edi - 40dd65: e8 16 fe ff ff callq 40db80 - 40dd6a: 64 48 8b 14 25 10 00 mov %fs:0x10,%rdx - 40dd71: 00 00 - 40dd73: 48 3b 15 be e3 2b 00 cmp 0x2be3be(%rip),%rdx # 6cc138 - 40dd7a: 74 46 je 40ddc2 - 40dd7c: be 01 00 00 00 mov $0x1,%esi - 40dd81: 31 c0 xor %eax,%eax - 40dd83: 83 3d 32 f4 2b 00 00 cmpl $0x0,0x2bf432(%rip) # 6cd1bc <__libc_multiple_threads> - 40dd8a: 74 0c je 40dd98 - 40dd8c: f0 0f b1 35 9c e3 2b lock cmpxchg %esi,0x2be39c(%rip) # 6cc130 - 40dd93: 00 - 40dd94: 75 0b jne 40dda1 - 40dd96: eb 23 jmp 40ddbb - 40dd98: 0f b1 35 91 e3 2b 00 cmpxchg %esi,0x2be391(%rip) # 6cc130 - 40dd9f: 74 1a je 40ddbb - 40dda1: 48 8d 3d 88 e3 2b 00 lea 0x2be388(%rip),%rdi # 6cc130 - 40dda8: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 40ddaf: e8 1c 48 03 00 callq 4425d0 <__lll_lock_wait_private> - 40ddb4: 48 81 c4 80 00 00 00 add $0x80,%rsp - 40ddbb: 48 89 15 76 e3 2b 00 mov %rdx,0x2be376(%rip) # 6cc138 - 40ddc2: 83 05 6b e3 2b 00 01 addl $0x1,0x2be36b(%rip) # 6cc134 - 40ddc9: 48 8d b4 24 80 00 00 lea 0x80(%rsp),%rsi - 40ddd0: 00 - 40ddd1: 31 c0 xor %eax,%eax - 40ddd3: b9 13 00 00 00 mov $0x13,%ecx - 40ddd8: 31 d2 xor %edx,%edx - 40ddda: c7 05 5c e3 2b 00 04 movl $0x4,0x2be35c(%rip) # 6cc140 - 40dde1: 00 00 00 - 40dde4: 48 89 f7 mov %rsi,%rdi - 40dde7: f3 48 ab rep stos %rax,%es:(%rdi) - 40ddea: 48 c7 84 24 88 00 00 movq $0xffffffffffffffff,0x88(%rsp) - 40ddf1: 00 ff ff ff ff - 40ddf6: bf 06 00 00 00 mov $0x6,%edi - 40ddfb: 48 c7 46 10 ff ff ff movq $0xffffffffffffffff,0x10(%rsi) - 40de02: ff - 40de03: 48 c7 46 18 ff ff ff movq $0xffffffffffffffff,0x18(%rsi) - 40de0a: ff - 40de0b: 48 c7 46 20 ff ff ff movq $0xffffffffffffffff,0x20(%rsi) - 40de12: ff - 40de13: 48 c7 46 28 ff ff ff movq $0xffffffffffffffff,0x28(%rsi) - 40de1a: ff - 40de1b: 48 c7 46 30 ff ff ff movq $0xffffffffffffffff,0x30(%rsi) - 40de22: ff - 40de23: 48 c7 46 38 ff ff ff movq $0xffffffffffffffff,0x38(%rsi) - 40de2a: ff - 40de2b: 48 c7 46 40 ff ff ff movq $0xffffffffffffffff,0x40(%rsi) - 40de32: ff - 40de33: 48 c7 46 48 ff ff ff movq $0xffffffffffffffff,0x48(%rsi) - 40de3a: ff - 40de3b: 48 c7 46 50 ff ff ff movq $0xffffffffffffffff,0x50(%rsi) - 40de42: ff - 40de43: 48 c7 46 58 ff ff ff movq $0xffffffffffffffff,0x58(%rsi) - 40de4a: ff - 40de4b: 48 c7 46 60 ff ff ff movq $0xffffffffffffffff,0x60(%rsi) - 40de52: ff - 40de53: 48 c7 46 68 ff ff ff movq $0xffffffffffffffff,0x68(%rsi) - 40de5a: ff - 40de5b: 48 c7 46 70 ff ff ff movq $0xffffffffffffffff,0x70(%rsi) - 40de62: ff - 40de63: 48 c7 46 78 ff ff ff movq $0xffffffffffffffff,0x78(%rsi) - 40de6a: ff - 40de6b: 48 c7 86 80 00 00 00 movq $0xffffffffffffffff,0x80(%rsi) - 40de72: ff ff ff ff - 40de76: c7 84 24 08 01 00 00 movl $0x0,0x108(%rsp) - 40de7d: 00 00 00 00 - 40de81: e8 8a 18 04 00 callq 44f710 <__sigaction> - 40de86: 8b 05 b4 e2 2b 00 mov 0x2be2b4(%rip),%eax # 6cc140 - 40de8c: 83 f8 04 cmp $0x4,%eax - 40de8f: 0f 85 fb fd ff ff jne 40dc90 - 40de95: c7 05 a1 e2 2b 00 05 movl $0x5,0x2be2a1(%rip) # 6cc140 - 40de9c: 00 00 00 - 40de9f: e8 4c 35 00 00 callq 4113f0 <__fcloseall> - 40dea4: 8b 05 96 e2 2b 00 mov 0x2be296(%rip),%eax # 6cc140 - 40deaa: 83 f8 05 cmp $0x5,%eax - 40dead: 0f 85 e6 fd ff ff jne 40dc99 - 40deb3: bf 06 00 00 00 mov $0x6,%edi - 40deb8: c7 05 7e e2 2b 00 06 movl $0x6,0x2be27e(%rip) # 6cc140 - 40debf: 00 00 00 - 40dec2: e8 b9 fc ff ff callq 40db80 - 40dec7: 8b 05 73 e2 2b 00 mov 0x2be273(%rip),%eax # 6cc140 - 40decd: 83 f8 06 cmp $0x6,%eax - 40ded0: 0f 85 cc fd ff ff jne 40dca2 - 40ded6: f4 hlt - 40ded7: bf 7f 00 00 00 mov $0x7f,%edi - 40dedc: c7 05 5a e2 2b 00 08 movl $0x8,0x2be25a(%rip) # 6cc140 - 40dee3: 00 00 00 - 40dee6: e8 e5 08 03 00 callq 43e7d0 <_exit> - 40deeb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - -000000000040def0 : - 40def0: 41 57 push %r15 - 40def2: 41 56 push %r14 - 40def4: 48 89 f8 mov %rdi,%rax - 40def7: 41 55 push %r13 - 40def9: 41 54 push %r12 - 40defb: 49 89 d4 mov %rdx,%r12 - 40defe: 55 push %rbp - 40deff: 53 push %rbx - 40df00: 49 d1 ec shr %r12 - 40df03: 4d 89 e7 mov %r12,%r15 - 40df06: 48 89 d5 mov %rdx,%rbp - 40df09: 48 83 ec 58 sub $0x58,%rsp - 40df0d: 4c 29 e5 sub %r12,%rbp - 40df10: 4c 0f af 3f imul (%rdi),%r15 - 40df14: 48 89 7c 24 18 mov %rdi,0x18(%rsp) - 40df19: 48 89 74 24 28 mov %rsi,0x28(%rsp) - 40df1e: 48 89 54 24 48 mov %rdx,0x48(%rsp) - 40df23: 49 01 f7 add %rsi,%r15 - 40df26: 49 83 fc 01 cmp $0x1,%r12 - 40df2a: 76 0b jbe 40df37 - 40df2c: 4c 89 e2 mov %r12,%rdx - 40df2f: 48 89 c7 mov %rax,%rdi - 40df32: e8 b9 ff ff ff callq 40def0 - 40df37: 48 83 fd 01 cmp $0x1,%rbp - 40df3b: 76 10 jbe 40df4d - 40df3d: 48 8b 7c 24 18 mov 0x18(%rsp),%rdi - 40df42: 48 89 ea mov %rbp,%rdx - 40df45: 4c 89 fe mov %r15,%rsi - 40df48: e8 a3 ff ff ff callq 40def0 - 40df4d: 48 8b 44 24 18 mov 0x18(%rsp),%rax - 40df52: 48 8b 38 mov (%rax),%rdi - 40df55: 48 8b 58 20 mov 0x20(%rax),%rbx - 40df59: 4c 8b 70 10 mov 0x10(%rax),%r14 - 40df5d: 48 89 7c 24 10 mov %rdi,0x10(%rsp) - 40df62: 48 8b 78 18 mov 0x18(%rax),%rdi - 40df66: 48 8b 40 08 mov 0x8(%rax),%rax - 40df6a: 48 89 7c 24 08 mov %rdi,0x8(%rsp) - 40df6f: 48 83 f8 01 cmp $0x1,%rax - 40df73: 0f 84 df 02 00 00 je 40e258 - 40df79: 0f 82 61 02 00 00 jb 40e1e0 - 40df7f: 48 83 f8 02 cmp $0x2,%rax - 40df83: 74 73 je 40dff8 - 40df85: 48 83 f8 03 cmp $0x3,%rax - 40df89: 0f 85 29 03 00 00 jne 40e2b8 - 40df8f: 48 85 ed test %rbp,%rbp - 40df92: 0f 84 91 03 00 00 je 40e329 - 40df98: 4d 85 e4 test %r12,%r12 - 40df9b: 4c 8b 6c 24 28 mov 0x28(%rsp),%r13 - 40dfa0: 75 32 jne 40dfd4 - 40dfa2: e9 82 03 00 00 jmpq 40e329 - 40dfa7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 40dfae: 00 00 - 40dfb0: 49 8b 07 mov (%r15),%rax - 40dfb3: 48 83 ed 01 sub $0x1,%rbp - 40dfb7: 49 83 c7 08 add $0x8,%r15 - 40dfbb: 48 89 03 mov %rax,(%rbx) - 40dfbe: 48 83 c3 08 add $0x8,%rbx - 40dfc2: 4d 85 e4 test %r12,%r12 - 40dfc5: 0f 84 85 01 00 00 je 40e150 - 40dfcb: 48 85 ed test %rbp,%rbp - 40dfce: 0f 84 7c 01 00 00 je 40e150 - 40dfd4: 48 8b 54 24 08 mov 0x8(%rsp),%rdx - 40dfd9: 49 8b 37 mov (%r15),%rsi - 40dfdc: 49 8b 7d 00 mov 0x0(%r13),%rdi - 40dfe0: 41 ff d6 callq *%r14 - 40dfe3: 85 c0 test %eax,%eax - 40dfe5: 7f c9 jg 40dfb0 - 40dfe7: 49 8b 45 00 mov 0x0(%r13),%rax - 40dfeb: 49 83 ec 01 sub $0x1,%r12 - 40dfef: 49 83 c5 08 add $0x8,%r13 - 40dff3: eb c6 jmp 40dfbb - 40dff5: 0f 1f 00 nopl (%rax) - 40dff8: 48 8b 74 24 10 mov 0x10(%rsp),%rsi - 40dffd: b8 08 00 00 00 mov $0x8,%eax - 40e002: 4c 8b 6c 24 28 mov 0x28(%rsp),%r13 - 40e007: 4c 89 74 24 30 mov %r14,0x30(%rsp) - 40e00c: 48 29 f0 sub %rsi,%rax - 40e00f: 4c 89 6c 24 20 mov %r13,0x20(%rsp) - 40e014: 49 89 f6 mov %rsi,%r14 - 40e017: 48 89 44 24 38 mov %rax,0x38(%rsp) - 40e01c: b8 10 00 00 00 mov $0x10,%eax - 40e021: 49 89 ed mov %rbp,%r13 - 40e024: 48 29 f0 sub %rsi,%rax - 40e027: 4d 85 e4 test %r12,%r12 - 40e02a: 4c 89 fd mov %r15,%rbp - 40e02d: 48 89 44 24 40 mov %rax,0x40(%rsp) - 40e032: 0f 84 09 01 00 00 je 40e141 - 40e038: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 40e03f: 00 - 40e040: 4d 85 ed test %r13,%r13 - 40e043: 0f 84 f8 00 00 00 je 40e141 - 40e049: 48 8b 54 24 08 mov 0x8(%rsp),%rdx - 40e04e: 48 89 ee mov %rbp,%rsi - 40e051: 48 8b 7c 24 20 mov 0x20(%rsp),%rdi - 40e056: 48 8b 44 24 30 mov 0x30(%rsp),%rax - 40e05b: 4e 8d 3c 33 lea (%rbx,%r14,1),%r15 - 40e05f: ff d0 callq *%rax - 40e061: 85 c0 test %eax,%eax - 40e063: 0f 8e 47 01 00 00 jle 40e1b0 - 40e069: 48 89 e8 mov %rbp,%rax - 40e06c: 49 83 ed 01 sub $0x1,%r13 - 40e070: 4c 01 f5 add %r14,%rbp - 40e073: 4c 39 fb cmp %r15,%rbx - 40e076: 0f 83 b9 00 00 00 jae 40e135 - 40e07c: 48 8b 7c 24 38 mov 0x38(%rsp),%rdi - 40e081: 48 8b 74 24 40 mov 0x40(%rsp),%rsi - 40e086: 49 8d 57 07 lea 0x7(%r15),%rdx - 40e08a: 4c 01 ff add %r15,%rdi - 40e08d: 49 8d 0c 37 lea (%r15,%rsi,1),%rcx - 40e091: 48 29 fa sub %rdi,%rdx - 40e094: 48 c1 ea 03 shr $0x3,%rdx - 40e098: 48 83 c2 01 add $0x1,%rdx - 40e09c: 48 39 c8 cmp %rcx,%rax - 40e09f: 48 8d 48 10 lea 0x10(%rax),%rcx - 40e0a3: 40 0f 93 c6 setae %sil - 40e0a7: 48 39 cb cmp %rcx,%rbx - 40e0aa: 0f 93 c1 setae %cl - 40e0ad: 40 08 ce or %cl,%sil - 40e0b0: 0f 84 da 00 00 00 je 40e190 - 40e0b6: 48 83 fa 18 cmp $0x18,%rdx - 40e0ba: 0f 86 d0 00 00 00 jbe 40e190 - 40e0c0: 48 89 c1 mov %rax,%rcx - 40e0c3: 48 c1 e1 3c shl $0x3c,%rcx - 40e0c7: 48 c1 e9 3f shr $0x3f,%rcx - 40e0cb: 48 39 d1 cmp %rdx,%rcx - 40e0ce: 48 0f 47 ca cmova %rdx,%rcx - 40e0d2: 48 85 c9 test %rcx,%rcx - 40e0d5: 0f 84 f5 00 00 00 je 40e1d0 - 40e0db: 48 8b 30 mov (%rax),%rsi - 40e0de: 4c 8d 48 08 lea 0x8(%rax),%r9 - 40e0e2: 48 89 33 mov %rsi,(%rbx) - 40e0e5: 48 29 ca sub %rcx,%rdx - 40e0e8: 48 c1 e1 03 shl $0x3,%rcx - 40e0ec: 45 31 db xor %r11d,%r11d - 40e0ef: 48 8d 72 fe lea -0x2(%rdx),%rsi - 40e0f3: 48 01 c8 add %rcx,%rax - 40e0f6: 48 01 cb add %rcx,%rbx - 40e0f9: 31 c9 xor %ecx,%ecx - 40e0fb: 48 d1 ee shr %rsi - 40e0fe: 48 83 c6 01 add $0x1,%rsi - 40e102: 4c 8d 14 36 lea (%rsi,%rsi,1),%r10 - 40e106: 66 0f 6f 04 08 movdqa (%rax,%rcx,1),%xmm0 - 40e10b: 49 83 c3 01 add $0x1,%r11 - 40e10f: 0f 11 04 0b movups %xmm0,(%rbx,%rcx,1) - 40e113: 48 83 c1 10 add $0x10,%rcx - 40e117: 49 39 f3 cmp %rsi,%r11 - 40e11a: 72 ea jb 40e106 - 40e11c: 4a 8d 04 d5 00 00 00 lea 0x0(,%r10,8),%rax - 40e123: 00 - 40e124: 48 01 c7 add %rax,%rdi - 40e127: 49 01 c1 add %rax,%r9 - 40e12a: 49 39 d2 cmp %rdx,%r10 - 40e12d: 74 06 je 40e135 - 40e12f: 49 8b 01 mov (%r9),%rax - 40e132: 48 89 07 mov %rax,(%rdi) - 40e135: 4d 85 e4 test %r12,%r12 - 40e138: 4c 89 fb mov %r15,%rbx - 40e13b: 0f 85 ff fe ff ff jne 40e040 - 40e141: 4c 89 ed mov %r13,%rbp - 40e144: 4c 8b 6c 24 20 mov 0x20(%rsp),%r13 - 40e149: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 40e150: 4d 85 e4 test %r12,%r12 - 40e153: 0f 85 df 00 00 00 jne 40e238 - 40e159: 48 8b 54 24 48 mov 0x48(%rsp),%rdx - 40e15e: 48 8b 44 24 18 mov 0x18(%rsp),%rax - 40e163: 48 8b 7c 24 28 mov 0x28(%rsp),%rdi - 40e168: 48 29 ea sub %rbp,%rdx - 40e16b: 48 8b 70 20 mov 0x20(%rax),%rsi - 40e16f: 48 0f af 54 24 10 imul 0x10(%rsp),%rdx - 40e175: 48 83 c4 58 add $0x58,%rsp - 40e179: 5b pop %rbx - 40e17a: 5d pop %rbp - 40e17b: 41 5c pop %r12 - 40e17d: 41 5d pop %r13 - 40e17f: 41 5e pop %r14 - 40e181: 41 5f pop %r15 - 40e183: e9 98 de 01 00 jmpq 42c020 - 40e188: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 40e18f: 00 - 40e190: 48 83 c0 08 add $0x8,%rax - 40e194: 48 8b 50 f8 mov -0x8(%rax),%rdx - 40e198: 48 83 c3 08 add $0x8,%rbx - 40e19c: 49 39 df cmp %rbx,%r15 - 40e19f: 48 89 53 f8 mov %rdx,-0x8(%rbx) - 40e1a3: 77 eb ja 40e190 - 40e1a5: eb 8e jmp 40e135 - 40e1a7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 40e1ae: 00 00 - 40e1b0: 48 8b 7c 24 20 mov 0x20(%rsp),%rdi - 40e1b5: 49 83 ec 01 sub $0x1,%r12 - 40e1b9: 48 89 f8 mov %rdi,%rax - 40e1bc: 4c 01 f7 add %r14,%rdi - 40e1bf: 48 89 7c 24 20 mov %rdi,0x20(%rsp) - 40e1c4: e9 aa fe ff ff jmpq 40e073 - 40e1c9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 40e1d0: 49 89 c1 mov %rax,%r9 - 40e1d3: 48 89 df mov %rbx,%rdi - 40e1d6: e9 0a ff ff ff jmpq 40e0e5 - 40e1db: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 40e1e0: 4d 85 e4 test %r12,%r12 - 40e1e3: 4c 8b 6c 24 28 mov 0x28(%rsp),%r13 - 40e1e8: 75 20 jne 40e20a - 40e1ea: e9 61 ff ff ff jmpq 40e150 - 40e1ef: 90 nop - 40e1f0: 41 8b 07 mov (%r15),%eax - 40e1f3: 48 83 ed 01 sub $0x1,%rbp - 40e1f7: 49 83 c7 04 add $0x4,%r15 - 40e1fb: 89 03 mov %eax,(%rbx) - 40e1fd: 48 83 c3 04 add $0x4,%rbx - 40e201: 4d 85 e4 test %r12,%r12 - 40e204: 0f 84 46 ff ff ff je 40e150 - 40e20a: 48 85 ed test %rbp,%rbp - 40e20d: 0f 84 3d ff ff ff je 40e150 - 40e213: 48 8b 54 24 08 mov 0x8(%rsp),%rdx - 40e218: 4c 89 fe mov %r15,%rsi - 40e21b: 4c 89 ef mov %r13,%rdi - 40e21e: 41 ff d6 callq *%r14 - 40e221: 85 c0 test %eax,%eax - 40e223: 7f cb jg 40e1f0 - 40e225: 41 8b 45 00 mov 0x0(%r13),%eax - 40e229: 49 83 ec 01 sub $0x1,%r12 - 40e22d: 49 83 c5 04 add $0x4,%r13 - 40e231: eb c8 jmp 40e1fb - 40e233: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 40e238: 4c 89 e2 mov %r12,%rdx - 40e23b: 4c 89 ee mov %r13,%rsi - 40e23e: 48 89 df mov %rbx,%rdi - 40e241: 48 0f af 54 24 10 imul 0x10(%rsp),%rdx - 40e247: e8 d4 dd 01 00 callq 42c020 - 40e24c: e9 08 ff ff ff jmpq 40e159 - 40e251: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 40e258: 48 85 ed test %rbp,%rbp - 40e25b: 0f 84 c8 00 00 00 je 40e329 - 40e261: 4d 85 e4 test %r12,%r12 - 40e264: 4c 8b 6c 24 28 mov 0x28(%rsp),%r13 - 40e269: 75 29 jne 40e294 - 40e26b: e9 b9 00 00 00 jmpq 40e329 - 40e270: 49 8b 07 mov (%r15),%rax - 40e273: 48 83 ed 01 sub $0x1,%rbp - 40e277: 49 83 c7 08 add $0x8,%r15 - 40e27b: 48 89 03 mov %rax,(%rbx) - 40e27e: 48 83 c3 08 add $0x8,%rbx - 40e282: 4d 85 e4 test %r12,%r12 - 40e285: 0f 84 c5 fe ff ff je 40e150 - 40e28b: 48 85 ed test %rbp,%rbp - 40e28e: 0f 84 bc fe ff ff je 40e150 - 40e294: 48 8b 54 24 08 mov 0x8(%rsp),%rdx - 40e299: 4c 89 fe mov %r15,%rsi - 40e29c: 4c 89 ef mov %r13,%rdi - 40e29f: 41 ff d6 callq *%r14 - 40e2a2: 85 c0 test %eax,%eax - 40e2a4: 7f ca jg 40e270 - 40e2a6: 49 8b 45 00 mov 0x0(%r13),%rax - 40e2aa: 49 83 ec 01 sub $0x1,%r12 - 40e2ae: 49 83 c5 08 add $0x8,%r13 - 40e2b2: eb c7 jmp 40e27b - 40e2b4: 0f 1f 40 00 nopl 0x0(%rax) - 40e2b8: 4c 8b 6c 24 28 mov 0x28(%rsp),%r13 - 40e2bd: 4d 85 e4 test %r12,%r12 - 40e2c0: 0f 84 8a fe ff ff je 40e150 - 40e2c6: 48 85 ed test %rbp,%rbp - 40e2c9: 0f 84 81 fe ff ff je 40e150 - 40e2cf: 48 8b 54 24 08 mov 0x8(%rsp),%rdx - 40e2d4: 4c 89 fe mov %r15,%rsi - 40e2d7: 4c 89 ef mov %r13,%rdi - 40e2da: 41 ff d6 callq *%r14 - 40e2dd: 85 c0 test %eax,%eax - 40e2df: 48 8b 54 24 10 mov 0x10(%rsp),%rdx - 40e2e4: 7e 2a jle 40e310 - 40e2e6: 4c 89 fe mov %r15,%rsi - 40e2e9: 48 89 df mov %rbx,%rdi - 40e2ec: 48 83 ed 01 sub $0x1,%rbp - 40e2f0: e8 cb 82 01 00 callq 4265c0 <__mempcpy> - 40e2f5: 4c 03 7c 24 10 add 0x10(%rsp),%r15 - 40e2fa: 4d 85 e4 test %r12,%r12 - 40e2fd: 48 89 c3 mov %rax,%rbx - 40e300: 75 c4 jne 40e2c6 - 40e302: e9 49 fe ff ff jmpq 40e150 - 40e307: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 40e30e: 00 00 - 40e310: 4c 89 ee mov %r13,%rsi - 40e313: 48 89 df mov %rbx,%rdi - 40e316: 49 83 ec 01 sub $0x1,%r12 - 40e31a: e8 a1 82 01 00 callq 4265c0 <__mempcpy> - 40e31f: 4c 03 6c 24 10 add 0x10(%rsp),%r13 - 40e324: 48 89 c3 mov %rax,%rbx - 40e327: eb 94 jmp 40e2bd - 40e329: 4c 8b 6c 24 28 mov 0x28(%rsp),%r13 - 40e32e: e9 1d fe ff ff jmpq 40e150 - 40e333: 0f 1f 00 nopl (%rax) - 40e336: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 40e33d: 00 00 00 - -000000000040e340 <__qsort_r>: - 40e340: 55 push %rbp - 40e341: 48 89 e5 mov %rsp,%rbp - 40e344: 41 57 push %r15 - 40e346: 41 56 push %r14 - 40e348: 41 55 push %r13 - 40e34a: 41 54 push %r12 - 40e34c: 49 89 fe mov %rdi,%r14 - 40e34f: 53 push %rbx - 40e350: 49 89 cf mov %rcx,%r15 - 40e353: 48 89 d3 mov %rdx,%rbx - 40e356: 49 89 f5 mov %rsi,%r13 - 40e359: 48 83 ec 68 sub $0x68,%rsp - 40e35d: 48 83 fa 20 cmp $0x20,%rdx - 40e361: 48 89 75 88 mov %rsi,-0x78(%rbp) - 40e365: 0f 87 f5 02 00 00 ja 40e660 <__qsort_r+0x320> - 40e36b: 4c 0f af ea imul %rdx,%r13 - 40e36f: 49 81 fd ff 03 00 00 cmp $0x3ff,%r13 - 40e376: 0f 86 f8 02 00 00 jbe 40e674 <__qsort_r+0x334> - 40e37c: 8b 15 ce dd 2b 00 mov 0x2bddce(%rip),%edx # 6cc150 - 40e382: 85 d2 test %edx,%edx - 40e384: 0f 84 96 03 00 00 je 40e720 <__qsort_r+0x3e0> - 40e38a: 48 63 f2 movslq %edx,%rsi - 40e38d: 4c 89 e8 mov %r13,%rax - 40e390: 31 d2 xor %edx,%edx - 40e392: 48 f7 f6 div %rsi - 40e395: 48 3b 05 ac dd 2b 00 cmp 0x2bddac(%rip),%rax # 6cc148 - 40e39c: 0f 87 fe 02 00 00 ja 40e6a0 <__qsort_r+0x360> - 40e3a2: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 40e3a9: 4c 89 ef mov %r13,%rdi - 40e3ac: 4c 89 45 98 mov %r8,-0x68(%rbp) - 40e3b0: 64 44 8b 20 mov %fs:(%rax),%r12d - 40e3b4: e8 57 f6 00 00 callq 41da10 <__libc_malloc> - 40e3b9: 48 c7 c1 d0 ff ff ff mov $0xffffffffffffffd0,%rcx - 40e3c0: 48 85 c0 test %rax,%rax - 40e3c3: 48 89 85 78 ff ff ff mov %rax,-0x88(%rbp) - 40e3ca: 4c 8b 45 98 mov -0x68(%rbp),%r8 - 40e3ce: 64 44 89 21 mov %r12d,%fs:(%rcx) - 40e3d2: 0f 84 c8 02 00 00 je 40e6a0 <__qsort_r+0x360> - 40e3d8: 48 89 45 c0 mov %rax,-0x40(%rbp) - 40e3dc: 48 89 c6 mov %rax,%rsi - 40e3df: 48 83 fb 20 cmp $0x20,%rbx - 40e3e3: 48 89 5d a0 mov %rbx,-0x60(%rbp) - 40e3e7: 48 c7 45 a8 04 00 00 movq $0x4,-0x58(%rbp) - 40e3ee: 00 - 40e3ef: 4c 89 7d b0 mov %r15,-0x50(%rbp) - 40e3f3: 4c 89 45 b8 mov %r8,-0x48(%rbp) - 40e3f7: 0f 86 cb 02 00 00 jbe 40e6c8 <__qsort_r+0x388> - 40e3fd: 48 8b 45 88 mov -0x78(%rbp),%rax - 40e401: 4c 8d 0c c5 00 00 00 lea 0x0(,%rax,8),%r9 - 40e408: 00 - 40e409: 4e 8d 24 0e lea (%rsi,%r9,1),%r12 - 40e40d: 4b 8d 04 0c lea (%r12,%r9,1),%rax - 40e411: 49 39 c4 cmp %rax,%r12 - 40e414: 48 89 45 80 mov %rax,-0x80(%rbp) - 40e418: 0f 83 94 03 00 00 jae 40e7b2 <__qsort_r+0x472> - 40e41e: 49 8d 4c 24 08 lea 0x8(%r12),%rcx - 40e423: 4c 8d 58 07 lea 0x7(%rax),%r11 - 40e427: 4c 89 e2 mov %r12,%rdx - 40e42a: 48 c1 e2 3c shl $0x3c,%rdx - 40e42e: 49 29 cb sub %rcx,%r11 - 40e431: 48 c1 ea 3f shr $0x3f,%rdx - 40e435: 49 c1 eb 03 shr $0x3,%r11 - 40e439: 49 8d 7b 01 lea 0x1(%r11),%rdi - 40e43d: 48 39 fa cmp %rdi,%rdx - 40e440: 48 0f 47 d7 cmova %rdi,%rdx - 40e444: 48 83 ff 0a cmp $0xa,%rdi - 40e448: 0f 87 29 03 00 00 ja 40e777 <__qsort_r+0x437> - 40e44e: 48 89 fa mov %rdi,%rdx - 40e451: 48 83 fa 01 cmp $0x1,%rdx - 40e455: 4d 89 34 24 mov %r14,(%r12) - 40e459: 49 8d 04 1e lea (%r14,%rbx,1),%rax - 40e45d: 0f 84 a9 00 00 00 je 40e50c <__qsort_r+0x1cc> - 40e463: 49 89 44 24 08 mov %rax,0x8(%r12) - 40e468: 48 01 d8 add %rbx,%rax - 40e46b: 48 83 fa 02 cmp $0x2,%rdx - 40e46f: 49 8d 4c 24 10 lea 0x10(%r12),%rcx - 40e474: 0f 84 92 00 00 00 je 40e50c <__qsort_r+0x1cc> - 40e47a: 49 89 44 24 10 mov %rax,0x10(%r12) - 40e47f: 48 01 d8 add %rbx,%rax - 40e482: 48 83 fa 03 cmp $0x3,%rdx - 40e486: 49 8d 4c 24 18 lea 0x18(%r12),%rcx - 40e48b: 74 7f je 40e50c <__qsort_r+0x1cc> - 40e48d: 49 89 44 24 18 mov %rax,0x18(%r12) - 40e492: 48 01 d8 add %rbx,%rax - 40e495: 48 83 fa 04 cmp $0x4,%rdx - 40e499: 49 8d 4c 24 20 lea 0x20(%r12),%rcx - 40e49e: 74 6c je 40e50c <__qsort_r+0x1cc> - 40e4a0: 49 89 44 24 20 mov %rax,0x20(%r12) - 40e4a5: 48 01 d8 add %rbx,%rax - 40e4a8: 48 83 fa 05 cmp $0x5,%rdx - 40e4ac: 49 8d 4c 24 28 lea 0x28(%r12),%rcx - 40e4b1: 74 59 je 40e50c <__qsort_r+0x1cc> - 40e4b3: 49 89 44 24 28 mov %rax,0x28(%r12) - 40e4b8: 48 01 d8 add %rbx,%rax - 40e4bb: 48 83 fa 06 cmp $0x6,%rdx - 40e4bf: 49 8d 4c 24 30 lea 0x30(%r12),%rcx - 40e4c4: 74 46 je 40e50c <__qsort_r+0x1cc> - 40e4c6: 49 89 44 24 30 mov %rax,0x30(%r12) - 40e4cb: 48 01 d8 add %rbx,%rax - 40e4ce: 48 83 fa 07 cmp $0x7,%rdx - 40e4d2: 49 8d 4c 24 38 lea 0x38(%r12),%rcx - 40e4d7: 74 33 je 40e50c <__qsort_r+0x1cc> - 40e4d9: 49 89 44 24 38 mov %rax,0x38(%r12) - 40e4de: 48 01 d8 add %rbx,%rax - 40e4e1: 48 83 fa 08 cmp $0x8,%rdx - 40e4e5: 49 8d 4c 24 40 lea 0x40(%r12),%rcx - 40e4ea: 74 20 je 40e50c <__qsort_r+0x1cc> - 40e4ec: 49 89 44 24 40 mov %rax,0x40(%r12) - 40e4f1: 48 01 d8 add %rbx,%rax - 40e4f4: 48 83 fa 0a cmp $0xa,%rdx - 40e4f8: 49 8d 4c 24 48 lea 0x48(%r12),%rcx - 40e4fd: 75 0d jne 40e50c <__qsort_r+0x1cc> - 40e4ff: 49 8d 4c 24 50 lea 0x50(%r12),%rcx - 40e504: 49 89 44 24 48 mov %rax,0x48(%r12) - 40e509: 48 01 d8 add %rbx,%rax - 40e50c: 48 39 d7 cmp %rdx,%rdi - 40e50f: 74 72 je 40e583 <__qsort_r+0x243> - 40e511: 48 29 d7 sub %rdx,%rdi - 40e514: 4c 8d 47 fe lea -0x2(%rdi),%r8 - 40e518: 49 d1 e8 shr %r8 - 40e51b: 49 83 c0 01 add $0x1,%r8 - 40e51f: 49 39 d3 cmp %rdx,%r11 - 40e522: 4f 8d 14 00 lea (%r8,%r8,1),%r10 - 40e526: 74 58 je 40e580 <__qsort_r+0x240> - 40e528: 4c 8d 1c 03 lea (%rbx,%rax,1),%r11 - 40e52c: 48 89 45 98 mov %rax,-0x68(%rbp) - 40e530: 48 03 55 88 add -0x78(%rbp),%rdx - 40e534: f3 0f 7e 45 98 movq -0x68(%rbp),%xmm0 - 40e539: 4c 89 5d 98 mov %r11,-0x68(%rbp) - 40e53d: 4c 8d 1c 1b lea (%rbx,%rbx,1),%r11 - 40e541: 0f 16 45 98 movhps -0x68(%rbp),%xmm0 - 40e545: 4c 89 5d 98 mov %r11,-0x68(%rbp) - 40e549: 48 8d 34 d6 lea (%rsi,%rdx,8),%rsi - 40e54d: 31 d2 xor %edx,%edx - 40e54f: f3 0f 7e 4d 98 movq -0x68(%rbp),%xmm1 - 40e554: 66 0f 6c c9 punpcklqdq %xmm1,%xmm1 - 40e558: 48 83 c2 01 add $0x1,%rdx - 40e55c: 48 83 c6 10 add $0x10,%rsi - 40e560: 0f 29 46 f0 movaps %xmm0,-0x10(%rsi) - 40e564: 66 0f d4 c1 paddq %xmm1,%xmm0 - 40e568: 4c 39 c2 cmp %r8,%rdx - 40e56b: 72 eb jb 40e558 <__qsort_r+0x218> - 40e56d: 48 89 da mov %rbx,%rdx - 40e570: 4a 8d 0c d1 lea (%rcx,%r10,8),%rcx - 40e574: 49 0f af d2 imul %r10,%rdx - 40e578: 48 01 d0 add %rdx,%rax - 40e57b: 4c 39 d7 cmp %r10,%rdi - 40e57e: 74 03 je 40e583 <__qsort_r+0x243> - 40e580: 48 89 01 mov %rax,(%rcx) - 40e583: 4c 89 ce mov %r9,%rsi - 40e586: 48 03 75 c0 add -0x40(%rbp),%rsi - 40e58a: 48 8b 45 88 mov -0x78(%rbp),%rax - 40e58e: 48 c7 45 a0 08 00 00 movq $0x8,-0x60(%rbp) - 40e595: 00 - 40e596: 48 c7 45 a8 03 00 00 movq $0x3,-0x58(%rbp) - 40e59d: 00 - 40e59e: 48 83 f8 01 cmp $0x1,%rax - 40e5a2: 0f 86 e3 01 00 00 jbe 40e78b <__qsort_r+0x44b> - 40e5a8: 48 8d 7d a0 lea -0x60(%rbp),%rdi - 40e5ac: 48 89 c2 mov %rax,%rdx - 40e5af: e8 3c f9 ff ff callq 40def0 - 40e5b4: 48 c7 45 90 00 00 00 movq $0x0,-0x70(%rbp) - 40e5bb: 00 - 40e5bc: 48 8b 45 90 mov -0x70(%rbp),%rax - 40e5c0: 4c 89 75 98 mov %r14,-0x68(%rbp) - 40e5c4: 0f 1f 40 00 nopl 0x0(%rax) - 40e5c8: 4d 8b 3c c4 mov (%r12,%rax,8),%r15 - 40e5cc: 4c 8b 6d 98 mov -0x68(%rbp),%r13 - 40e5d0: 4d 39 ef cmp %r13,%r15 - 40e5d3: 74 5d je 40e632 <__qsort_r+0x2f2> - 40e5d5: 48 8b 7d 80 mov -0x80(%rbp),%rdi - 40e5d9: 4c 89 ee mov %r13,%rsi - 40e5dc: 48 89 da mov %rbx,%rdx - 40e5df: e8 3c da 01 00 callq 42c020 - 40e5e4: 4c 89 ef mov %r13,%rdi - 40e5e7: 48 8b 75 90 mov -0x70(%rbp),%rsi - 40e5eb: eb 06 jmp 40e5f3 <__qsort_r+0x2b3> - 40e5ed: 0f 1f 00 nopl (%rax) - 40e5f0: 49 89 c7 mov %rax,%r15 - 40e5f3: 4c 89 f8 mov %r15,%rax - 40e5f6: 31 d2 xor %edx,%edx - 40e5f8: 49 89 3c f4 mov %rdi,(%r12,%rsi,8) - 40e5fc: 4c 29 f0 sub %r14,%rax - 40e5ff: 4c 89 fe mov %r15,%rsi - 40e602: 48 f7 f3 div %rbx - 40e605: 48 89 da mov %rbx,%rdx - 40e608: 49 89 c5 mov %rax,%r13 - 40e60b: e8 10 da 01 00 callq 42c020 - 40e610: 4b 8d 14 ec lea (%r12,%r13,8),%rdx - 40e614: 4c 89 ee mov %r13,%rsi - 40e617: 4c 89 ff mov %r15,%rdi - 40e61a: 48 8b 02 mov (%rdx),%rax - 40e61d: 48 3b 45 98 cmp -0x68(%rbp),%rax - 40e621: 75 cd jne 40e5f0 <__qsort_r+0x2b0> - 40e623: 48 8b 75 80 mov -0x80(%rbp),%rsi - 40e627: 4c 89 3a mov %r15,(%rdx) - 40e62a: 48 89 da mov %rbx,%rdx - 40e62d: e8 ee d9 01 00 callq 42c020 - 40e632: 48 83 45 90 01 addq $0x1,-0x70(%rbp) - 40e637: 48 01 5d 98 add %rbx,-0x68(%rbp) - 40e63b: 48 8b 45 90 mov -0x70(%rbp),%rax - 40e63f: 48 39 45 88 cmp %rax,-0x78(%rbp) - 40e643: 75 83 jne 40e5c8 <__qsort_r+0x288> - 40e645: 48 8b bd 78 ff ff ff mov -0x88(%rbp),%rdi - 40e64c: e8 5f f7 00 00 callq 41ddb0 <__cfree> - 40e651: 48 8d 65 d8 lea -0x28(%rbp),%rsp - 40e655: 5b pop %rbx - 40e656: 41 5c pop %r12 - 40e658: 41 5d pop %r13 - 40e65a: 41 5e pop %r14 - 40e65c: 41 5f pop %r15 - 40e65e: 5d pop %rbp - 40e65f: c3 retq - 40e660: 49 c1 e5 04 shl $0x4,%r13 - 40e664: 49 01 d5 add %rdx,%r13 - 40e667: 49 81 fd ff 03 00 00 cmp $0x3ff,%r13 - 40e66e: 0f 87 08 fd ff ff ja 40e37c <__qsort_r+0x3c> - 40e674: 49 83 c5 1e add $0x1e,%r13 - 40e678: 48 c7 85 78 ff ff ff movq $0x0,-0x88(%rbp) - 40e67f: 00 00 00 00 - 40e683: 49 83 e5 f0 and $0xfffffffffffffff0,%r13 - 40e687: 4c 29 ec sub %r13,%rsp - 40e68a: 48 8d 74 24 0f lea 0xf(%rsp),%rsi - 40e68f: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi - 40e693: 48 89 75 c0 mov %rsi,-0x40(%rbp) - 40e697: e9 43 fd ff ff jmpq 40e3df <__qsort_r+0x9f> - 40e69c: 0f 1f 40 00 nopl 0x0(%rax) - 40e6a0: 48 8b 75 88 mov -0x78(%rbp),%rsi - 40e6a4: 4c 89 f9 mov %r15,%rcx - 40e6a7: 48 89 da mov %rbx,%rdx - 40e6aa: 4c 89 f7 mov %r14,%rdi - 40e6ad: e8 ce 10 04 00 callq 44f780 <_quicksort> - 40e6b2: 48 8d 65 d8 lea -0x28(%rbp),%rsp - 40e6b6: 5b pop %rbx - 40e6b7: 41 5c pop %r12 - 40e6b9: 41 5d pop %r13 - 40e6bb: 41 5e pop %r14 - 40e6bd: 41 5f pop %r15 - 40e6bf: 5d pop %rbp - 40e6c0: c3 retq - 40e6c1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 40e6c8: 48 89 d8 mov %rbx,%rax - 40e6cb: 4c 09 f0 or %r14,%rax - 40e6ce: a8 03 test $0x3,%al - 40e6d0: 75 20 jne 40e6f2 <__qsort_r+0x3b2> - 40e6d2: 48 83 fb 04 cmp $0x4,%rbx - 40e6d6: 0f 84 de 00 00 00 je 40e7ba <__qsort_r+0x47a> - 40e6dc: 48 83 fb 08 cmp $0x8,%rbx - 40e6e0: 0f 84 b5 00 00 00 je 40e79b <__qsort_r+0x45b> - 40e6e6: a8 07 test $0x7,%al - 40e6e8: 75 08 jne 40e6f2 <__qsort_r+0x3b2> - 40e6ea: 48 c7 45 a8 02 00 00 movq $0x2,-0x58(%rbp) - 40e6f1: 00 - 40e6f2: 48 8b 45 88 mov -0x78(%rbp),%rax - 40e6f6: 48 83 f8 01 cmp $0x1,%rax - 40e6fa: 0f 86 45 ff ff ff jbe 40e645 <__qsort_r+0x305> - 40e700: 48 8d 7d a0 lea -0x60(%rbp),%rdi - 40e704: 48 89 c2 mov %rax,%rdx - 40e707: 4c 89 f6 mov %r14,%rsi - 40e70a: e8 e1 f7 ff ff callq 40def0 - 40e70f: 48 8b bd 78 ff ff ff mov -0x88(%rbp),%rdi - 40e716: e8 95 f6 00 00 callq 41ddb0 <__cfree> - 40e71b: e9 31 ff ff ff jmpq 40e651 <__qsort_r+0x311> - 40e720: bf 55 00 00 00 mov $0x55,%edi - 40e725: 4c 89 45 98 mov %r8,-0x68(%rbp) - 40e729: e8 e2 01 03 00 callq 43e910 <__sysconf> - 40e72e: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 40e732: 48 ba ff ff ff ff ff movabs $0x1fffffffffffffff,%rdx - 40e739: ff ff 1f - 40e73c: 4c 8b 45 98 mov -0x68(%rbp),%r8 - 40e740: 74 0f je 40e751 <__qsort_r+0x411> - 40e742: 48 8d 50 03 lea 0x3(%rax),%rdx - 40e746: 48 85 c0 test %rax,%rax - 40e749: 48 0f 49 d0 cmovns %rax,%rdx - 40e74d: 48 c1 fa 02 sar $0x2,%rdx - 40e751: 4c 89 45 98 mov %r8,-0x68(%rbp) - 40e755: 48 89 15 ec d9 2b 00 mov %rdx,0x2bd9ec(%rip) # 6cc148 - 40e75c: bf 1e 00 00 00 mov $0x1e,%edi - 40e761: e8 aa 01 03 00 callq 43e910 <__sysconf> - 40e766: 4c 8b 45 98 mov -0x68(%rbp),%r8 - 40e76a: 89 c2 mov %eax,%edx - 40e76c: 89 05 de d9 2b 00 mov %eax,0x2bd9de(%rip) # 6cc150 - 40e772: e9 13 fc ff ff jmpq 40e38a <__qsort_r+0x4a> - 40e777: 48 85 d2 test %rdx,%rdx - 40e77a: 0f 85 d1 fc ff ff jne 40e451 <__qsort_r+0x111> - 40e780: 4c 89 e1 mov %r12,%rcx - 40e783: 4c 89 f0 mov %r14,%rax - 40e786: e9 86 fd ff ff jmpq 40e511 <__qsort_r+0x1d1> - 40e78b: 48 83 7d 88 00 cmpq $0x0,-0x78(%rbp) - 40e790: 0f 85 1e fe ff ff jne 40e5b4 <__qsort_r+0x274> - 40e796: e9 aa fe ff ff jmpq 40e645 <__qsort_r+0x305> - 40e79b: 41 f6 c6 07 test $0x7,%r14b - 40e79f: 0f 85 41 ff ff ff jne 40e6e6 <__qsort_r+0x3a6> - 40e7a5: 48 c7 45 a8 01 00 00 movq $0x1,-0x58(%rbp) - 40e7ac: 00 - 40e7ad: e9 40 ff ff ff jmpq 40e6f2 <__qsort_r+0x3b2> - 40e7b2: 4c 89 e6 mov %r12,%rsi - 40e7b5: e9 d0 fd ff ff jmpq 40e58a <__qsort_r+0x24a> - 40e7ba: 48 c7 45 a8 00 00 00 movq $0x0,-0x58(%rbp) - 40e7c1: 00 - 40e7c2: e9 2b ff ff ff jmpq 40e6f2 <__qsort_r+0x3b2> - 40e7c7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 40e7ce: 00 00 - -000000000040e7d0 : - 40e7d0: 45 31 c0 xor %r8d,%r8d - 40e7d3: e9 68 fb ff ff jmpq 40e340 <__qsort_r> - 40e7d8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 40e7df: 00 - -000000000040e7e0 : - 40e7e0: 41 57 push %r15 - 40e7e2: 41 56 push %r14 - 40e7e4: 41 55 push %r13 - 40e7e6: 41 54 push %r12 - 40e7e8: 55 push %rbp - 40e7e9: 53 push %rbx - 40e7ea: 48 89 fb mov %rdi,%rbx - 40e7ed: 48 83 ec 08 sub $0x8,%rsp - 40e7f1: e8 5a 4e 01 00 callq 423650 - 40e7f6: 48 8b 2d 43 de 2b 00 mov 0x2bde43(%rip),%rbp # 6cc640 <__environ> - 40e7fd: 48 85 ed test %rbp,%rbp - 40e800: 0f 84 b2 00 00 00 je 40e8b8 - 40e806: 49 89 c5 mov %rax,%r13 - 40e809: 0f b6 03 movzbl (%rbx),%eax - 40e80c: 84 c0 test %al,%al - 40e80e: 0f 84 a4 00 00 00 je 40e8b8 - 40e814: 80 7b 01 00 cmpb $0x0,0x1(%rbx) - 40e818: 75 46 jne 40e860 - 40e81a: 48 8b 5d 00 mov 0x0(%rbp),%rbx - 40e81e: 80 cc 3d or $0x3d,%ah - 40e821: 48 85 db test %rbx,%rbx - 40e824: 75 17 jne 40e83d - 40e826: eb 1e jmp 40e846 - 40e828: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 40e82f: 00 - 40e830: 48 83 c5 08 add $0x8,%rbp - 40e834: 48 8b 5d 00 mov 0x0(%rbp),%rbx - 40e838: 48 85 db test %rbx,%rbx - 40e83b: 74 09 je 40e846 - 40e83d: 66 3b 03 cmp (%rbx),%ax - 40e840: 75 ee jne 40e830 - 40e842: 48 83 c3 02 add $0x2,%rbx - 40e846: 48 83 c4 08 add $0x8,%rsp - 40e84a: 48 89 d8 mov %rbx,%rax - 40e84d: 5b pop %rbx - 40e84e: 5d pop %rbp - 40e84f: 41 5c pop %r12 - 40e851: 41 5d pop %r13 - 40e853: 41 5e pop %r14 - 40e855: 41 5f pop %r15 - 40e857: c3 retq - 40e858: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 40e85f: 00 - 40e860: 44 0f b7 23 movzwl (%rbx),%r12d - 40e864: 4c 8d 7b 02 lea 0x2(%rbx),%r15 - 40e868: 48 8b 5d 00 mov 0x0(%rbp),%rbx - 40e86c: 4d 8d 75 fe lea -0x2(%r13),%r14 - 40e870: 48 85 db test %rbx,%rbx - 40e873: 75 18 jne 40e88d - 40e875: eb cf jmp 40e846 - 40e877: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 40e87e: 00 00 - 40e880: 48 83 c5 08 add $0x8,%rbp - 40e884: 48 8b 5d 00 mov 0x0(%rbp),%rbx - 40e888: 48 85 db test %rbx,%rbx - 40e88b: 74 b9 je 40e846 - 40e88d: 66 44 3b 23 cmp (%rbx),%r12w - 40e891: 75 ed jne 40e880 - 40e893: 48 8d 7b 02 lea 0x2(%rbx),%rdi - 40e897: 4c 89 f2 mov %r14,%rdx - 40e89a: 4c 89 fe mov %r15,%rsi - 40e89d: e8 4e 4f 01 00 callq 4237f0 - 40e8a2: 85 c0 test %eax,%eax - 40e8a4: 75 da jne 40e880 - 40e8a6: 42 80 3c 2b 3d cmpb $0x3d,(%rbx,%r13,1) - 40e8ab: 75 d3 jne 40e880 - 40e8ad: 4a 8d 5c 2b 01 lea 0x1(%rbx,%r13,1),%rbx - 40e8b2: eb 92 jmp 40e846 - 40e8b4: 0f 1f 40 00 nopl 0x0(%rax) - 40e8b8: 31 db xor %ebx,%ebx - 40e8ba: eb 8a jmp 40e846 - 40e8bc: 0f 1f 40 00 nopl 0x0(%rax) - -000000000040e8c0 <__run_exit_handlers>: - 40e8c0: 41 55 push %r13 - 40e8c2: 41 54 push %r12 - 40e8c4: b8 00 00 00 00 mov $0x0,%eax - 40e8c9: 55 push %rbp - 40e8ca: 53 push %rbx - 40e8cb: 48 89 f5 mov %rsi,%rbp - 40e8ce: 89 fb mov %edi,%ebx - 40e8d0: 41 89 d4 mov %edx,%r12d - 40e8d3: 48 83 ec 08 sub $0x8,%rsp - 40e8d7: 48 85 c0 test %rax,%rax - 40e8da: 74 05 je 40e8e1 <__run_exit_handlers+0x21> - 40e8dc: e8 1f 17 bf ff callq 0 <_nl_current_LC_CTYPE> - 40e8e1: 4c 8b 6d 00 mov 0x0(%rbp),%r13 - 40e8e5: 4d 85 ed test %r13,%r13 - 40e8e8: 74 56 je 40e940 <__run_exit_handlers+0x80> - 40e8ea: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 40e8f0: 49 8b 45 08 mov 0x8(%r13),%rax - 40e8f4: 48 89 c2 mov %rax,%rdx - 40e8f7: 48 c1 e2 05 shl $0x5,%rdx - 40e8fb: 48 85 c0 test %rax,%rax - 40e8fe: 49 8d 4c 15 f0 lea -0x10(%r13,%rdx,1),%rcx - 40e903: 74 2a je 40e92f <__run_exit_handlers+0x6f> - 40e905: 48 83 e8 01 sub $0x1,%rax - 40e909: 49 89 45 08 mov %rax,0x8(%r13) - 40e90d: 48 8b 11 mov (%rcx),%rdx - 40e910: 48 83 fa 03 cmp $0x3,%rdx - 40e914: 0f 84 a6 00 00 00 je 40e9c0 <__run_exit_handlers+0x100> - 40e91a: 48 83 fa 04 cmp $0x4,%rdx - 40e91e: 74 78 je 40e998 <__run_exit_handlers+0xd8> - 40e920: 48 83 fa 02 cmp $0x2,%rdx - 40e924: 74 4a je 40e970 <__run_exit_handlers+0xb0> - 40e926: 48 83 e9 20 sub $0x20,%rcx - 40e92a: 48 85 c0 test %rax,%rax - 40e92d: 75 d6 jne 40e905 <__run_exit_handlers+0x45> - 40e92f: 49 8b 45 00 mov 0x0(%r13),%rax - 40e933: 48 85 c0 test %rax,%rax - 40e936: 48 89 45 00 mov %rax,0x0(%rbp) - 40e93a: 0f 85 9d 00 00 00 jne 40e9dd <__run_exit_handlers+0x11d> - 40e940: 45 84 e4 test %r12b,%r12b - 40e943: 74 20 je 40e965 <__run_exit_handlers+0xa5> - 40e945: b8 58 e1 4b 00 mov $0x4be158,%eax - 40e94a: 48 3d 60 e1 4b 00 cmp $0x4be160,%rax - 40e950: 73 13 jae 40e965 <__run_exit_handlers+0xa5> - 40e952: 48 89 c5 mov %rax,%rbp - 40e955: ff 55 00 callq *0x0(%rbp) - 40e958: 48 83 c5 08 add $0x8,%rbp - 40e95c: 48 81 fd 60 e1 4b 00 cmp $0x4be160,%rbp - 40e963: 72 f0 jb 40e955 <__run_exit_handlers+0x95> - 40e965: 89 df mov %ebx,%edi - 40e967: e8 64 fe 02 00 callq 43e7d0 <_exit> - 40e96c: 0f 1f 40 00 nopl 0x0(%rax) - 40e970: 48 c1 e0 05 shl $0x5,%rax - 40e974: 89 df mov %ebx,%edi - 40e976: 4c 01 e8 add %r13,%rax - 40e979: 48 8b 50 18 mov 0x18(%rax),%rdx - 40e97d: 48 8b 70 20 mov 0x20(%rax),%rsi - 40e981: 48 c1 ca 11 ror $0x11,%rdx - 40e985: 64 48 33 14 25 30 00 xor %fs:0x30,%rdx - 40e98c: 00 00 - 40e98e: ff d2 callq *%rdx - 40e990: e9 5b ff ff ff jmpq 40e8f0 <__run_exit_handlers+0x30> - 40e995: 0f 1f 00 nopl (%rax) - 40e998: 48 c1 e0 05 shl $0x5,%rax - 40e99c: 89 de mov %ebx,%esi - 40e99e: 4c 01 e8 add %r13,%rax - 40e9a1: 48 8b 50 18 mov 0x18(%rax),%rdx - 40e9a5: 48 8b 78 20 mov 0x20(%rax),%rdi - 40e9a9: 48 c1 ca 11 ror $0x11,%rdx - 40e9ad: 64 48 33 14 25 30 00 xor %fs:0x30,%rdx - 40e9b4: 00 00 - 40e9b6: ff d2 callq *%rdx - 40e9b8: e9 33 ff ff ff jmpq 40e8f0 <__run_exit_handlers+0x30> - 40e9bd: 0f 1f 00 nopl (%rax) - 40e9c0: 48 c1 e0 05 shl $0x5,%rax - 40e9c4: 49 8b 44 05 18 mov 0x18(%r13,%rax,1),%rax - 40e9c9: 48 c1 c8 11 ror $0x11,%rax - 40e9cd: 64 48 33 04 25 30 00 xor %fs:0x30,%rax - 40e9d4: 00 00 - 40e9d6: ff d0 callq *%rax - 40e9d8: e9 13 ff ff ff jmpq 40e8f0 <__run_exit_handlers+0x30> - 40e9dd: 4c 89 ef mov %r13,%rdi - 40e9e0: e8 cb f3 00 00 callq 41ddb0 <__cfree> - 40e9e5: e9 f7 fe ff ff jmpq 40e8e1 <__run_exit_handlers+0x21> - 40e9ea: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - -000000000040e9f0 : - 40e9f0: 48 83 ec 08 sub $0x8,%rsp - 40e9f4: ba 01 00 00 00 mov $0x1,%edx - 40e9f9: be a0 a0 6c 00 mov $0x6ca0a0,%esi - 40e9fe: e8 bd fe ff ff callq 40e8c0 <__run_exit_handlers> - 40ea03: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 40ea0a: 00 00 00 - 40ea0d: 0f 1f 00 nopl (%rax) - -000000000040ea10 <__new_exitfn>: - 40ea10: 55 push %rbp - 40ea11: 53 push %rbx - 40ea12: be 01 00 00 00 mov $0x1,%esi - 40ea17: 48 89 fb mov %rdi,%rbx - 40ea1a: 31 c0 xor %eax,%eax - 40ea1c: 48 83 ec 08 sub $0x8,%rsp - 40ea20: 83 3d 95 e7 2b 00 00 cmpl $0x0,0x2be795(%rip) # 6cd1bc <__libc_multiple_threads> - 40ea27: 74 0c je 40ea35 <__new_exitfn+0x25> - 40ea29: f0 0f b1 35 3f db 2b lock cmpxchg %esi,0x2bdb3f(%rip) # 6cc570 - 40ea30: 00 - 40ea31: 75 0b jne 40ea3e <__new_exitfn+0x2e> - 40ea33: eb 23 jmp 40ea58 <__new_exitfn+0x48> - 40ea35: 0f b1 35 34 db 2b 00 cmpxchg %esi,0x2bdb34(%rip) # 6cc570 - 40ea3c: 74 1a je 40ea58 <__new_exitfn+0x48> - 40ea3e: 48 8d 3d 2b db 2b 00 lea 0x2bdb2b(%rip),%rdi # 6cc570 - 40ea45: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 40ea4c: e8 7f 3b 03 00 callq 4425d0 <__lll_lock_wait_private> - 40ea51: 48 81 c4 80 00 00 00 add $0x80,%rsp - 40ea58: 48 8b 2b mov (%rbx),%rbp - 40ea5b: 31 ff xor %edi,%edi - 40ea5d: 48 85 ed test %rbp,%rbp - 40ea60: 48 89 e8 mov %rbp,%rax - 40ea63: 0f 84 10 01 00 00 je 40eb79 <__new_exitfn+0x169> - 40ea69: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 40ea70: 48 8b 48 08 mov 0x8(%rax),%rcx - 40ea74: 48 85 c9 test %rcx,%rcx - 40ea77: 74 3e je 40eab7 <__new_exitfn+0xa7> - 40ea79: 48 8d 51 ff lea -0x1(%rcx),%rdx - 40ea7d: 48 89 d6 mov %rdx,%rsi - 40ea80: 48 c1 e6 05 shl $0x5,%rsi - 40ea84: 48 83 7c 30 10 00 cmpq $0x0,0x10(%rax,%rsi,1) - 40ea8a: 75 47 jne 40ead3 <__new_exitfn+0xc3> - 40ea8c: 48 c1 e1 05 shl $0x5,%rcx - 40ea90: 48 8d 4c 08 d0 lea -0x30(%rax,%rcx,1),%rcx - 40ea95: eb 1b jmp 40eab2 <__new_exitfn+0xa2> - 40ea97: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 40ea9e: 00 00 - 40eaa0: 48 83 e9 20 sub $0x20,%rcx - 40eaa4: 48 8d 72 ff lea -0x1(%rdx),%rsi - 40eaa8: 48 83 79 20 00 cmpq $0x0,0x20(%rcx) - 40eaad: 75 31 jne 40eae0 <__new_exitfn+0xd0> - 40eaaf: 48 89 f2 mov %rsi,%rdx - 40eab2: 48 85 d2 test %rdx,%rdx - 40eab5: 75 e9 jne 40eaa0 <__new_exitfn+0x90> - 40eab7: 48 8b 10 mov (%rax),%rdx - 40eaba: 48 c7 40 08 00 00 00 movq $0x0,0x8(%rax) - 40eac1: 00 - 40eac2: 48 89 c7 mov %rax,%rdi - 40eac5: 48 85 d2 test %rdx,%rdx - 40eac8: 0f 84 9d 00 00 00 je 40eb6b <__new_exitfn+0x15b> - 40eace: 48 89 d0 mov %rdx,%rax - 40ead1: eb 9d jmp 40ea70 <__new_exitfn+0x60> - 40ead3: 48 89 ca mov %rcx,%rdx - 40ead6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 40eadd: 00 00 00 - 40eae0: 48 83 fa 20 cmp $0x20,%rdx - 40eae4: 74 63 je 40eb49 <__new_exitfn+0x139> - 40eae6: 48 89 d1 mov %rdx,%rcx - 40eae9: 48 83 c2 01 add $0x1,%rdx - 40eaed: 48 c1 e1 05 shl $0x5,%rcx - 40eaf1: 48 89 50 08 mov %rdx,0x8(%rax) - 40eaf5: 48 8d 74 08 10 lea 0x10(%rax,%rcx,1),%rsi - 40eafa: 48 c7 06 01 00 00 00 movq $0x1,(%rsi) - 40eb01: 48 83 05 a7 e6 2b 00 addq $0x1,0x2be6a7(%rip) # 6cd1b0 <__new_exitfn_called> - 40eb08: 01 - 40eb09: 83 3d ac e6 2b 00 00 cmpl $0x0,0x2be6ac(%rip) # 6cd1bc <__libc_multiple_threads> - 40eb10: 74 0b je 40eb1d <__new_exitfn+0x10d> - 40eb12: f0 ff 0d 57 da 2b 00 lock decl 0x2bda57(%rip) # 6cc570 - 40eb19: 75 0a jne 40eb25 <__new_exitfn+0x115> - 40eb1b: eb 22 jmp 40eb3f <__new_exitfn+0x12f> - 40eb1d: ff 0d 4d da 2b 00 decl 0x2bda4d(%rip) # 6cc570 - 40eb23: 74 1a je 40eb3f <__new_exitfn+0x12f> - 40eb25: 48 8d 3d 44 da 2b 00 lea 0x2bda44(%rip),%rdi # 6cc570 - 40eb2c: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 40eb33: e8 c8 3a 03 00 callq 442600 <__lll_unlock_wake_private> - 40eb38: 48 81 c4 80 00 00 00 add $0x80,%rsp - 40eb3f: 48 83 c4 08 add $0x8,%rsp - 40eb43: 48 89 f0 mov %rsi,%rax - 40eb46: 5b pop %rbx - 40eb47: 5d pop %rbp - 40eb48: c3 retq - 40eb49: 48 85 ff test %rdi,%rdi - 40eb4c: 48 89 f8 mov %rdi,%rax - 40eb4f: 75 1a jne 40eb6b <__new_exitfn+0x15b> - 40eb51: be 10 04 00 00 mov $0x410,%esi - 40eb56: bf 01 00 00 00 mov $0x1,%edi - 40eb5b: e8 60 fa 00 00 callq 41e5c0 <__calloc> - 40eb60: 48 85 c0 test %rax,%rax - 40eb63: 74 2d je 40eb92 <__new_exitfn+0x182> - 40eb65: 48 89 28 mov %rbp,(%rax) - 40eb68: 48 89 03 mov %rax,(%rbx) - 40eb6b: 48 8d 70 10 lea 0x10(%rax),%rsi - 40eb6f: 48 c7 40 08 01 00 00 movq $0x1,0x8(%rax) - 40eb76: 00 - 40eb77: eb 81 jmp 40eafa <__new_exitfn+0xea> - 40eb79: b9 18 19 4a 00 mov $0x4a1918,%ecx - 40eb7e: ba 64 00 00 00 mov $0x64,%edx - 40eb83: be 00 19 4a 00 mov $0x4a1900,%esi - 40eb88: bf 0d 19 4a 00 mov $0x4a190d,%edi - 40eb8d: e8 ae 2b ff ff callq 401740 <__assert_fail> - 40eb92: 31 f6 xor %esi,%esi - 40eb94: e9 70 ff ff ff jmpq 40eb09 <__new_exitfn+0xf9> - 40eb99: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - -000000000040eba0 <__internal_atexit>: - 40eba0: 41 54 push %r12 - 40eba2: 55 push %rbp - 40eba3: 49 89 f4 mov %rsi,%r12 - 40eba6: 53 push %rbx - 40eba7: 48 89 fb mov %rdi,%rbx - 40ebaa: 48 89 cf mov %rcx,%rdi - 40ebad: 48 89 d5 mov %rdx,%rbp - 40ebb0: e8 5b fe ff ff callq 40ea10 <__new_exitfn> - 40ebb5: 48 85 c0 test %rax,%rax - 40ebb8: 74 2a je 40ebe4 <__internal_atexit+0x44> - 40ebba: 48 89 df mov %rbx,%rdi - 40ebbd: 4c 89 60 10 mov %r12,0x10(%rax) - 40ebc1: 48 89 68 18 mov %rbp,0x18(%rax) - 40ebc5: 64 48 33 3c 25 30 00 xor %fs:0x30,%rdi - 40ebcc: 00 00 - 40ebce: 48 c1 c7 11 rol $0x11,%rdi - 40ebd2: 48 89 78 08 mov %rdi,0x8(%rax) - 40ebd6: 48 c7 00 04 00 00 00 movq $0x4,(%rax) - 40ebdd: 31 c0 xor %eax,%eax - 40ebdf: 5b pop %rbx - 40ebe0: 5d pop %rbp - 40ebe1: 41 5c pop %r12 - 40ebe3: c3 retq - 40ebe4: b8 ff ff ff ff mov $0xffffffff,%eax - 40ebe9: eb f4 jmp 40ebdf <__internal_atexit+0x3f> - 40ebeb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - -000000000040ebf0 <__cxa_atexit>: - 40ebf0: 41 54 push %r12 - 40ebf2: 55 push %rbp - 40ebf3: 49 89 f4 mov %rsi,%r12 - 40ebf6: 53 push %rbx - 40ebf7: 48 89 fb mov %rdi,%rbx - 40ebfa: bf a0 a0 6c 00 mov $0x6ca0a0,%edi - 40ebff: 48 89 d5 mov %rdx,%rbp - 40ec02: e8 09 fe ff ff callq 40ea10 <__new_exitfn> - 40ec07: 48 85 c0 test %rax,%rax - 40ec0a: 74 2a je 40ec36 <__cxa_atexit+0x46> - 40ec0c: 48 89 df mov %rbx,%rdi - 40ec0f: 4c 89 60 10 mov %r12,0x10(%rax) - 40ec13: 48 89 68 18 mov %rbp,0x18(%rax) - 40ec17: 64 48 33 3c 25 30 00 xor %fs:0x30,%rdi - 40ec1e: 00 00 - 40ec20: 48 c1 c7 11 rol $0x11,%rdi - 40ec24: 48 89 78 08 mov %rdi,0x8(%rax) - 40ec28: 48 c7 00 04 00 00 00 movq $0x4,(%rax) - 40ec2f: 31 c0 xor %eax,%eax - 40ec31: 5b pop %rbx - 40ec32: 5d pop %rbp - 40ec33: 41 5c pop %r12 - 40ec35: c3 retq - 40ec36: b8 ff ff ff ff mov $0xffffffff,%eax - 40ec3b: eb f4 jmp 40ec31 <__cxa_atexit+0x41> - 40ec3d: 0f 1f 00 nopl (%rax) - -000000000040ec40 <__strtoul_internal>: - 40ec40: 48 c7 c0 b8 ff ff ff mov $0xffffffffffffffb8,%rax - 40ec47: 64 4c 8b 00 mov %fs:(%rax),%r8 - 40ec4b: e9 20 00 00 00 jmpq 40ec70 <____strtoul_l_internal> - -000000000040ec50 <__strtoul>: - 40ec50: 48 c7 c0 b8 ff ff ff mov $0xffffffffffffffb8,%rax - 40ec57: 31 c9 xor %ecx,%ecx - 40ec59: 64 4c 8b 00 mov %fs:(%rax),%r8 - 40ec5d: e9 0e 00 00 00 jmpq 40ec70 <____strtoul_l_internal> - 40ec62: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 40ec69: 00 00 00 - 40ec6c: 0f 1f 40 00 nopl 0x0(%rax) - -000000000040ec70 <____strtoul_l_internal>: - 40ec70: 41 57 push %r15 - 40ec72: 41 56 push %r14 - 40ec74: 49 89 f7 mov %rsi,%r15 - 40ec77: 41 55 push %r13 - 40ec79: 41 54 push %r12 - 40ec7b: 49 89 fe mov %rdi,%r14 - 40ec7e: 55 push %rbp - 40ec7f: 53 push %rbx - 40ec80: 48 83 ec 28 sub $0x28,%rsp - 40ec84: 85 c9 test %ecx,%ecx - 40ec86: 74 16 je 40ec9e <____strtoul_l_internal+0x2e> - 40ec88: 49 8b 70 08 mov 0x8(%r8),%rsi - 40ec8c: 48 8b 4e 50 mov 0x50(%rsi),%rcx - 40ec90: 0f b6 01 movzbl (%rcx),%eax - 40ec93: 83 e8 01 sub $0x1,%eax - 40ec96: 3c 7d cmp $0x7d,%al - 40ec98: 0f 86 f2 00 00 00 jbe 40ed90 <____strtoul_l_internal+0x120> - 40ec9e: 31 c9 xor %ecx,%ecx - 40eca0: 31 ed xor %ebp,%ebp - 40eca2: 83 fa 01 cmp $0x1,%edx - 40eca5: 0f 84 c5 00 00 00 je 40ed70 <____strtoul_l_internal+0x100> - 40ecab: 83 fa 24 cmp $0x24,%edx - 40ecae: 0f 87 bc 00 00 00 ja 40ed70 <____strtoul_l_internal+0x100> - 40ecb4: 49 0f be 06 movsbq (%r14),%rax - 40ecb8: 49 8b 70 68 mov 0x68(%r8),%rsi - 40ecbc: 4d 89 f4 mov %r14,%r12 - 40ecbf: f6 44 46 01 20 testb $0x20,0x1(%rsi,%rax,2) - 40ecc4: 48 89 c3 mov %rax,%rbx - 40ecc7: 74 1a je 40ece3 <____strtoul_l_internal+0x73> - 40ecc9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 40ecd0: 49 83 c4 01 add $0x1,%r12 - 40ecd4: 49 0f be 04 24 movsbq (%r12),%rax - 40ecd9: f6 44 46 01 20 testb $0x20,0x1(%rsi,%rax,2) - 40ecde: 48 89 c3 mov %rax,%rbx - 40ece1: 75 ed jne 40ecd0 <____strtoul_l_internal+0x60> - 40ece3: 84 db test %bl,%bl - 40ece5: 0f 84 bd 00 00 00 je 40eda8 <____strtoul_l_internal+0x138> - 40eceb: 80 fb 2d cmp $0x2d,%bl - 40ecee: 0f 84 10 03 00 00 je 40f004 <____strtoul_l_internal+0x394> - 40ecf4: 80 fb 2b cmp $0x2b,%bl - 40ecf7: c7 44 24 14 00 00 00 movl $0x0,0x14(%rsp) - 40ecfe: 00 - 40ecff: 0f 84 5a 03 00 00 je 40f05f <____strtoul_l_internal+0x3ef> - 40ed05: 80 fb 30 cmp $0x30,%bl - 40ed08: 0f 84 dd 00 00 00 je 40edeb <____strtoul_l_internal+0x17b> - 40ed0e: 85 d2 test %edx,%edx - 40ed10: 0f 85 e1 00 00 00 jne 40edf7 <____strtoul_l_internal+0x187> - 40ed16: 48 85 c9 test %rcx,%rcx - 40ed19: 48 89 0c 24 mov %rcx,(%rsp) - 40ed1d: 0f 84 73 03 00 00 je 40f096 <____strtoul_l_internal+0x426> - 40ed23: 48 89 ef mov %rbp,%rdi - 40ed26: e8 25 49 01 00 callq 423650 - 40ed2b: 48 85 c0 test %rax,%rax - 40ed2e: 49 89 c5 mov %rax,%r13 - 40ed31: 74 78 je 40edab <____strtoul_l_internal+0x13b> - 40ed33: 0f b6 7d 00 movzbl 0x0(%rbp),%edi - 40ed37: 48 8b 0c 24 mov (%rsp),%rcx - 40ed3b: 40 38 df cmp %bl,%dil - 40ed3e: 0f 85 0e 02 00 00 jne 40ef52 <____strtoul_l_internal+0x2e2> - 40ed44: 31 d2 xor %edx,%edx - 40ed46: eb 18 jmp 40ed60 <____strtoul_l_internal+0xf0> - 40ed48: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 40ed4f: 00 - 40ed50: 41 0f b6 34 14 movzbl (%r12,%rdx,1),%esi - 40ed55: 40 38 74 15 00 cmp %sil,0x0(%rbp,%rdx,1) - 40ed5a: 0f 85 f2 01 00 00 jne 40ef52 <____strtoul_l_internal+0x2e2> - 40ed60: 48 83 c2 01 add $0x1,%rdx - 40ed64: 48 39 d0 cmp %rdx,%rax - 40ed67: 75 e7 jne 40ed50 <____strtoul_l_internal+0xe0> - 40ed69: eb 40 jmp 40edab <____strtoul_l_internal+0x13b> - 40ed6b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 40ed70: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 40ed77: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) - 40ed7e: 31 c0 xor %eax,%eax - 40ed80: 48 83 c4 28 add $0x28,%rsp - 40ed84: 5b pop %rbx - 40ed85: 5d pop %rbp - 40ed86: 41 5c pop %r12 - 40ed88: 41 5d pop %r13 - 40ed8a: 41 5e pop %r14 - 40ed8c: 41 5f pop %r15 - 40ed8e: c3 retq - 40ed8f: 90 nop - 40ed90: 48 8b 6e 48 mov 0x48(%rsi),%rbp - 40ed94: 80 7d 00 00 cmpb $0x0,0x0(%rbp) - 40ed98: 0f 85 04 ff ff ff jne 40eca2 <____strtoul_l_internal+0x32> - 40ed9e: e9 fb fe ff ff jmpq 40ec9e <____strtoul_l_internal+0x2e> - 40eda3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 40eda8: 4d 89 f4 mov %r14,%r12 - 40edab: 4d 85 ff test %r15,%r15 - 40edae: 0f 84 ba 02 00 00 je 40f06e <____strtoul_l_internal+0x3fe> - 40edb4: 4c 89 e0 mov %r12,%rax - 40edb7: 4c 29 f0 sub %r14,%rax - 40edba: 48 83 f8 01 cmp $0x1,%rax - 40edbe: 7e 17 jle 40edd7 <____strtoul_l_internal+0x167> - 40edc0: 49 0f be 54 24 ff movsbq -0x1(%r12),%rdx - 40edc6: 48 8b 05 2b 39 0a 00 mov 0xa392b(%rip),%rax # 4b26f8 <_nl_C_locobj+0x78> - 40edcd: 83 3c 90 58 cmpl $0x58,(%rax,%rdx,4) - 40edd1: 0f 84 6e 02 00 00 je 40f045 <____strtoul_l_internal+0x3d5> - 40edd7: 4d 89 37 mov %r14,(%r15) - 40edda: 48 83 c4 28 add $0x28,%rsp - 40edde: 31 c0 xor %eax,%eax - 40ede0: 5b pop %rbx - 40ede1: 5d pop %rbp - 40ede2: 41 5c pop %r12 - 40ede4: 41 5d pop %r13 - 40ede6: 41 5e pop %r14 - 40ede8: 41 5f pop %r15 - 40edea: c3 retq - 40edeb: f7 c2 ef ff ff ff test $0xffffffef,%edx - 40edf1: 0f 84 24 02 00 00 je 40f01b <____strtoul_l_internal+0x3ab> - 40edf7: 83 fa 0a cmp $0xa,%edx - 40edfa: 0f 84 16 ff ff ff je 40ed16 <____strtoul_l_internal+0xa6> - 40ee00: 8d 4a fe lea -0x2(%rdx),%ecx - 40ee03: 45 31 ed xor %r13d,%r13d - 40ee06: 31 c0 xor %eax,%eax - 40ee08: 48 63 c9 movslq %ecx,%rcx - 40ee0b: 4c 39 e0 cmp %r12,%rax - 40ee0e: 48 8b 3c cd c0 27 4b mov 0x4b27c0(,%rcx,8),%rdi - 40ee15: 00 - 40ee16: 48 89 3c 24 mov %rdi,(%rsp) - 40ee1a: 0f b6 b9 80 27 4b 00 movzbl 0x4b2780(%rcx),%edi - 40ee21: 40 88 7c 24 13 mov %dil,0x13(%rsp) - 40ee26: 74 83 je 40edab <____strtoul_l_internal+0x13b> - 40ee28: 84 db test %bl,%bl - 40ee2a: 0f 84 7b ff ff ff je 40edab <____strtoul_l_internal+0x13b> - 40ee30: 4d 8d 45 ff lea -0x1(%r13),%r8 - 40ee34: 4c 8b 15 ad 38 0a 00 mov 0xa38ad(%rip),%r10 # 4b26e8 <_nl_C_locobj+0x68> - 40ee3b: 4c 8b 1d b6 38 0a 00 mov 0xa38b6(%rip),%r11 # 4b26f8 <_nl_C_locobj+0x78> - 40ee42: 48 63 ca movslq %edx,%rcx - 40ee45: 4c 89 e7 mov %r12,%rdi - 40ee48: 4c 89 64 24 18 mov %r12,0x18(%rsp) - 40ee4d: 4c 89 44 24 08 mov %r8,0x8(%rsp) - 40ee52: 4c 8b 04 24 mov (%rsp),%r8 - 40ee56: 45 31 c9 xor %r9d,%r9d - 40ee59: 31 f6 xor %esi,%esi - 40ee5b: 49 89 cc mov %rcx,%r12 - 40ee5e: 66 90 xchg %ax,%ax - 40ee60: 8d 4b d0 lea -0x30(%rbx),%ecx - 40ee63: 80 f9 09 cmp $0x9,%cl - 40ee66: 0f 86 aa 00 00 00 jbe 40ef16 <____strtoul_l_internal+0x2a6> - 40ee6c: 4d 85 ed test %r13,%r13 - 40ee6f: 0f 84 8f 00 00 00 je 40ef04 <____strtoul_l_internal+0x294> - 40ee75: 38 5d 00 cmp %bl,0x0(%rbp) - 40ee78: 0f 85 86 00 00 00 jne 40ef04 <____strtoul_l_internal+0x294> - 40ee7e: 31 c9 xor %ecx,%ecx - 40ee80: 88 1c 24 mov %bl,(%rsp) - 40ee83: eb 0d jmp 40ee92 <____strtoul_l_internal+0x222> - 40ee85: 0f 1f 00 nopl (%rax) - 40ee88: 0f b6 1c 0f movzbl (%rdi,%rcx,1),%ebx - 40ee8c: 38 5c 0d 00 cmp %bl,0x0(%rbp,%rcx,1) - 40ee90: 75 6e jne 40ef00 <____strtoul_l_internal+0x290> - 40ee92: 48 83 c1 01 add $0x1,%rcx - 40ee96: 49 39 cd cmp %rcx,%r13 - 40ee99: 75 ed jne 40ee88 <____strtoul_l_internal+0x218> - 40ee9b: 48 8b 5c 24 08 mov 0x8(%rsp),%rbx - 40eea0: 48 8d 0c 1f lea (%rdi,%rbx,1),%rcx - 40eea4: 0f 1f 40 00 nopl 0x0(%rax) - 40eea8: 48 8d 79 01 lea 0x1(%rcx),%rdi - 40eeac: 0f b6 59 01 movzbl 0x1(%rcx),%ebx - 40eeb0: 48 39 f8 cmp %rdi,%rax - 40eeb3: 74 04 je 40eeb9 <____strtoul_l_internal+0x249> - 40eeb5: 84 db test %bl,%bl - 40eeb7: 75 a7 jne 40ee60 <____strtoul_l_internal+0x1f0> - 40eeb9: 4c 8b 64 24 18 mov 0x18(%rsp),%r12 - 40eebe: 49 39 fc cmp %rdi,%r12 - 40eec1: 0f 84 e4 fe ff ff je 40edab <____strtoul_l_internal+0x13b> - 40eec7: 4d 85 ff test %r15,%r15 - 40eeca: 74 03 je 40eecf <____strtoul_l_internal+0x25f> - 40eecc: 49 89 3f mov %rdi,(%r15) - 40eecf: 45 85 c9 test %r9d,%r9d - 40eed2: 0f 84 17 01 00 00 je 40efef <____strtoul_l_internal+0x37f> - 40eed8: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 40eedf: 64 c7 00 22 00 00 00 movl $0x22,%fs:(%rax) - 40eee6: 48 83 c4 28 add $0x28,%rsp - 40eeea: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax - 40eef1: 5b pop %rbx - 40eef2: 5d pop %rbp - 40eef3: 41 5c pop %r12 - 40eef5: 41 5d pop %r13 - 40eef7: 41 5e pop %r14 - 40eef9: 41 5f pop %r15 - 40eefb: c3 retq - 40eefc: 0f 1f 40 00 nopl 0x0(%rax) - 40ef00: 0f b6 1c 24 movzbl (%rsp),%ebx - 40ef04: 0f b6 db movzbl %bl,%ebx - 40ef07: 41 f6 44 5a 01 04 testb $0x4,0x1(%r10,%rbx,2) - 40ef0d: 74 aa je 40eeb9 <____strtoul_l_internal+0x249> - 40ef0f: 41 8b 0c 9b mov (%r11,%rbx,4),%ecx - 40ef13: 83 e9 37 sub $0x37,%ecx - 40ef16: 0f b6 d9 movzbl %cl,%ebx - 40ef19: 39 d3 cmp %edx,%ebx - 40ef1b: 7d 9c jge 40eeb9 <____strtoul_l_internal+0x249> - 40ef1d: 49 39 f0 cmp %rsi,%r8 - 40ef20: 72 0e jb 40ef30 <____strtoul_l_internal+0x2c0> - 40ef22: 3a 4c 24 13 cmp 0x13(%rsp),%cl - 40ef26: 76 18 jbe 40ef40 <____strtoul_l_internal+0x2d0> - 40ef28: 49 39 f0 cmp %rsi,%r8 - 40ef2b: 75 13 jne 40ef40 <____strtoul_l_internal+0x2d0> - 40ef2d: 0f 1f 00 nopl (%rax) - 40ef30: 48 89 f9 mov %rdi,%rcx - 40ef33: 41 b9 01 00 00 00 mov $0x1,%r9d - 40ef39: e9 6a ff ff ff jmpq 40eea8 <____strtoul_l_internal+0x238> - 40ef3e: 66 90 xchg %ax,%ax - 40ef40: 49 0f af f4 imul %r12,%rsi - 40ef44: 0f b6 c9 movzbl %cl,%ecx - 40ef47: 48 01 ce add %rcx,%rsi - 40ef4a: 48 89 f9 mov %rdi,%rcx - 40ef4d: e9 56 ff ff ff jmpq 40eea8 <____strtoul_l_internal+0x238> - 40ef52: 84 db test %bl,%bl - 40ef54: 0f 84 34 01 00 00 je 40f08e <____strtoul_l_internal+0x41e> - 40ef5a: 4c 8b 05 87 37 0a 00 mov 0xa3787(%rip),%r8 # 4b26e8 <_nl_C_locobj+0x68> - 40ef61: 4c 8b 0d 90 37 0a 00 mov 0xa3790(%rip),%r9 # 4b26f8 <_nl_C_locobj+0x78> - 40ef68: 4c 89 e6 mov %r12,%rsi - 40ef6b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 40ef70: 8d 53 d0 lea -0x30(%rbx),%edx - 40ef73: 80 fa 09 cmp $0x9,%dl - 40ef76: 76 25 jbe 40ef9d <____strtoul_l_internal+0x32d> - 40ef78: 40 3a 3e cmp (%rsi),%dil - 40ef7b: 75 53 jne 40efd0 <____strtoul_l_internal+0x360> - 40ef7d: 31 d2 xor %edx,%edx - 40ef7f: eb 13 jmp 40ef94 <____strtoul_l_internal+0x324> - 40ef81: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 40ef88: 44 0f b6 1c 16 movzbl (%rsi,%rdx,1),%r11d - 40ef8d: 44 38 5c 15 00 cmp %r11b,0x0(%rbp,%rdx,1) - 40ef92: 75 3c jne 40efd0 <____strtoul_l_internal+0x360> - 40ef94: 48 83 c2 01 add $0x1,%rdx - 40ef98: 48 39 d0 cmp %rdx,%rax - 40ef9b: 75 eb jne 40ef88 <____strtoul_l_internal+0x318> - 40ef9d: 48 83 c6 01 add $0x1,%rsi - 40efa1: 0f b6 1e movzbl (%rsi),%ebx - 40efa4: 84 db test %bl,%bl - 40efa6: 75 c8 jne 40ef70 <____strtoul_l_internal+0x300> - 40efa8: 48 89 ea mov %rbp,%rdx - 40efab: 4c 89 e7 mov %r12,%rdi - 40efae: e8 0d 01 00 00 callq 40f0c0 <__correctly_grouped_prefixmb> - 40efb3: 41 0f b6 1c 24 movzbl (%r12),%ebx - 40efb8: b9 08 00 00 00 mov $0x8,%ecx - 40efbd: ba 0a 00 00 00 mov $0xa,%edx - 40efc2: e9 41 fe ff ff jmpq 40ee08 <____strtoul_l_internal+0x198> - 40efc7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 40efce: 00 00 - 40efd0: 0f b6 db movzbl %bl,%ebx - 40efd3: 41 f6 44 58 01 04 testb $0x4,0x1(%r8,%rbx,2) - 40efd9: 74 cd je 40efa8 <____strtoul_l_internal+0x338> - 40efdb: 41 83 3c 99 40 cmpl $0x40,(%r9,%rbx,4) - 40efe0: 7f c6 jg 40efa8 <____strtoul_l_internal+0x338> - 40efe2: 48 83 c6 01 add $0x1,%rsi - 40efe6: 0f b6 1e movzbl (%rsi),%ebx - 40efe9: 84 db test %bl,%bl - 40efeb: 75 83 jne 40ef70 <____strtoul_l_internal+0x300> - 40efed: eb b9 jmp 40efa8 <____strtoul_l_internal+0x338> - 40efef: 8b 54 24 14 mov 0x14(%rsp),%edx - 40eff3: 48 89 f0 mov %rsi,%rax - 40eff6: 48 f7 d8 neg %rax - 40eff9: 85 d2 test %edx,%edx - 40effb: 48 0f 44 c6 cmove %rsi,%rax - 40efff: e9 7c fd ff ff jmpq 40ed80 <____strtoul_l_internal+0x110> - 40f004: 41 0f b6 5c 24 01 movzbl 0x1(%r12),%ebx - 40f00a: c7 44 24 14 01 00 00 movl $0x1,0x14(%rsp) - 40f011: 00 - 40f012: 49 83 c4 01 add $0x1,%r12 - 40f016: e9 ea fc ff ff jmpq 40ed05 <____strtoul_l_internal+0x95> - 40f01b: 49 0f be 74 24 01 movsbq 0x1(%r12),%rsi - 40f021: 48 8b 05 d0 36 0a 00 mov 0xa36d0(%rip),%rax # 4b26f8 <_nl_C_locobj+0x78> - 40f028: 83 3c b0 58 cmpl $0x58,(%rax,%rsi,4) - 40f02c: 74 47 je 40f075 <____strtoul_l_internal+0x405> - 40f02e: 85 d2 test %edx,%edx - 40f030: 0f 85 c1 fd ff ff jne 40edf7 <____strtoul_l_internal+0x187> - 40f036: b9 06 00 00 00 mov $0x6,%ecx - 40f03b: ba 08 00 00 00 mov $0x8,%edx - 40f040: e9 be fd ff ff jmpq 40ee03 <____strtoul_l_internal+0x193> - 40f045: 41 80 7c 24 fe 30 cmpb $0x30,-0x2(%r12) - 40f04b: 0f 85 86 fd ff ff jne 40edd7 <____strtoul_l_internal+0x167> - 40f051: 49 83 ec 01 sub $0x1,%r12 - 40f055: 31 c0 xor %eax,%eax - 40f057: 4d 89 27 mov %r12,(%r15) - 40f05a: e9 21 fd ff ff jmpq 40ed80 <____strtoul_l_internal+0x110> - 40f05f: 41 0f b6 5c 24 01 movzbl 0x1(%r12),%ebx - 40f065: 49 83 c4 01 add $0x1,%r12 - 40f069: e9 97 fc ff ff jmpq 40ed05 <____strtoul_l_internal+0x95> - 40f06e: 31 c0 xor %eax,%eax - 40f070: e9 0b fd ff ff jmpq 40ed80 <____strtoul_l_internal+0x110> - 40f075: 41 0f b6 5c 24 02 movzbl 0x2(%r12),%ebx - 40f07b: b9 0e 00 00 00 mov $0xe,%ecx - 40f080: 49 83 c4 02 add $0x2,%r12 - 40f084: ba 10 00 00 00 mov $0x10,%edx - 40f089: e9 75 fd ff ff jmpq 40ee03 <____strtoul_l_internal+0x193> - 40f08e: 4c 89 e6 mov %r12,%rsi - 40f091: e9 12 ff ff ff jmpq 40efa8 <____strtoul_l_internal+0x338> - 40f096: b9 08 00 00 00 mov $0x8,%ecx - 40f09b: ba 0a 00 00 00 mov $0xa,%edx - 40f0a0: e9 5e fd ff ff jmpq 40ee03 <____strtoul_l_internal+0x193> - 40f0a5: 90 nop - 40f0a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 40f0ad: 00 00 00 - -000000000040f0b0 <__strtoul_l>: - 40f0b0: 49 89 c8 mov %rcx,%r8 - 40f0b3: 31 c9 xor %ecx,%ecx - 40f0b5: e9 b6 fb ff ff jmpq 40ec70 <____strtoul_l_internal> - 40f0ba: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - -000000000040f0c0 <__correctly_grouped_prefixmb>: - 40f0c0: 41 57 push %r15 - 40f0c2: 41 56 push %r14 - 40f0c4: 41 55 push %r13 - 40f0c6: 41 54 push %r12 - 40f0c8: 55 push %rbp - 40f0c9: 53 push %rbx - 40f0ca: 48 83 ec 18 sub $0x18,%rsp - 40f0ce: 48 85 c9 test %rcx,%rcx - 40f0d1: 48 89 4c 24 08 mov %rcx,0x8(%rsp) - 40f0d6: 0f 84 fd 00 00 00 je 40f1d9 <__correctly_grouped_prefixmb+0x119> - 40f0dc: 48 89 fd mov %rdi,%rbp - 40f0df: 48 89 d7 mov %rdx,%rdi - 40f0e2: 48 89 34 24 mov %rsi,(%rsp) - 40f0e6: 48 89 d3 mov %rdx,%rbx - 40f0e9: e8 62 45 01 00 callq 423650 - 40f0ee: 48 8b 34 24 mov (%rsp),%rsi - 40f0f2: 48 39 ee cmp %rbp,%rsi - 40f0f5: 0f 86 ad 00 00 00 jbe 40f1a8 <__correctly_grouped_prefixmb+0xe8> - 40f0fb: 4c 8d 78 ff lea -0x1(%rax),%r15 - 40f0ff: 48 8d 55 ff lea -0x1(%rbp),%rdx - 40f103: 4c 8d 4e ff lea -0x1(%rsi),%r9 - 40f107: 4c 39 cd cmp %r9,%rbp - 40f10a: 0f 87 c9 00 00 00 ja 40f1d9 <__correctly_grouped_prefixmb+0x119> - 40f110: 44 0f b6 13 movzbl (%rbx),%r10d - 40f114: 4e 8d 1c 3e lea (%rsi,%r15,1),%r11 - 40f118: eb 17 jmp 40f131 <__correctly_grouped_prefixmb+0x71> - 40f11a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 40f120: 49 83 e9 01 sub $0x1,%r9 - 40f124: 49 83 eb 01 sub $0x1,%r11 - 40f128: 49 39 d1 cmp %rdx,%r9 - 40f12b: 0f 84 a8 00 00 00 je 40f1d9 <__correctly_grouped_prefixmb+0x119> - 40f131: 45 38 53 ff cmp %r10b,-0x1(%r11) - 40f135: 75 e9 jne 40f120 <__correctly_grouped_prefixmb+0x60> - 40f137: 0f b6 43 01 movzbl 0x1(%rbx),%eax - 40f13b: 84 c0 test %al,%al - 40f13d: 74 2b je 40f16a <__correctly_grouped_prefixmb+0xaa> - 40f13f: 41 38 43 fe cmp %al,-0x2(%r11) - 40f143: 75 db jne 40f120 <__correctly_grouped_prefixmb+0x60> - 40f145: 48 8d 43 02 lea 0x2(%rbx),%rax - 40f149: 4c 89 d9 mov %r11,%rcx - 40f14c: eb 14 jmp 40f162 <__correctly_grouped_prefixmb+0xa2> - 40f14e: 66 90 xchg %ax,%ax - 40f150: 44 0f b6 41 fd movzbl -0x3(%rcx),%r8d - 40f155: 48 83 c0 01 add $0x1,%rax - 40f159: 48 83 e9 01 sub $0x1,%rcx - 40f15d: 44 38 c7 cmp %r8b,%dil - 40f160: 75 be jne 40f120 <__correctly_grouped_prefixmb+0x60> - 40f162: 0f b6 38 movzbl (%rax),%edi - 40f165: 40 84 ff test %dil,%dil - 40f168: 75 e6 jne 40f150 <__correctly_grouped_prefixmb+0x90> - 40f16a: 4c 39 cd cmp %r9,%rbp - 40f16d: 77 6a ja 40f1d9 <__correctly_grouped_prefixmb+0x119> - 40f16f: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 40f174: 48 89 f1 mov %rsi,%rcx - 40f177: 4c 29 c9 sub %r9,%rcx - 40f17a: 48 0f be 00 movsbq (%rax),%rax - 40f17e: 49 89 c5 mov %rax,%r13 - 40f181: 83 c0 01 add $0x1,%eax - 40f184: 48 98 cltq - 40f186: 48 39 c1 cmp %rax,%rcx - 40f189: 74 60 je 40f1eb <__correctly_grouped_prefixmb+0x12b> - 40f18b: 4c 89 0c 24 mov %r9,(%rsp) - 40f18f: 7e 09 jle 40f19a <__correctly_grouped_prefixmb+0xda> - 40f191: 4b 8d 44 29 01 lea 0x1(%r9,%r13,1),%rax - 40f196: 48 89 04 24 mov %rax,(%rsp) - 40f19a: 48 3b 2c 24 cmp (%rsp),%rbp - 40f19e: 48 8b 34 24 mov (%rsp),%rsi - 40f1a2: 0f 82 5b ff ff ff jb 40f103 <__correctly_grouped_prefixmb+0x43> - 40f1a8: 48 39 f5 cmp %rsi,%rbp - 40f1ab: 48 89 f0 mov %rsi,%rax - 40f1ae: 48 0f 43 c5 cmovae %rbp,%rax - 40f1b2: 48 83 c4 18 add $0x18,%rsp - 40f1b6: 5b pop %rbx - 40f1b7: 5d pop %rbp - 40f1b8: 41 5c pop %r12 - 40f1ba: 41 5d pop %r13 - 40f1bc: 41 5e pop %r14 - 40f1be: 41 5f pop %r15 - 40f1c0: c3 retq - 40f1c1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 40f1c8: 49 83 e9 01 sub $0x1,%r9 - 40f1cc: 49 83 eb 01 sub $0x1,%r11 - 40f1d0: 4c 39 ca cmp %r9,%rdx - 40f1d3: 0f 85 d7 00 00 00 jne 40f2b0 <__correctly_grouped_prefixmb+0x1f0> - 40f1d9: 48 83 c4 18 add $0x18,%rsp - 40f1dd: 48 89 f0 mov %rsi,%rax - 40f1e0: 5b pop %rbx - 40f1e1: 5d pop %rbp - 40f1e2: 41 5c pop %r12 - 40f1e4: 41 5d pop %r13 - 40f1e6: 41 5e pop %r14 - 40f1e8: 41 5f pop %r15 - 40f1ea: c3 retq - 40f1eb: 4d 8d 61 ff lea -0x1(%r9),%r12 - 40f1ef: 4c 8b 74 24 08 mov 0x8(%rsp),%r14 - 40f1f4: 4c 89 24 24 mov %r12,(%rsp) - 40f1f8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 40f1ff: 00 - 40f200: 41 0f b6 46 01 movzbl 0x1(%r14),%eax - 40f205: 84 c0 test %al,%al - 40f207: 74 08 je 40f211 <__correctly_grouped_prefixmb+0x151> - 40f209: 49 83 c6 01 add $0x1,%r14 - 40f20d: 4c 0f be e8 movsbq %al,%r13 - 40f211: 41 80 fd 7f cmp $0x7f,%r13b - 40f215: 0f 84 85 00 00 00 je 40f2a0 <__correctly_grouped_prefixmb+0x1e0> - 40f21b: 45 84 ed test %r13b,%r13b - 40f21e: 0f 88 7c 00 00 00 js 40f2a0 <__correctly_grouped_prefixmb+0x1e0> - 40f224: 4c 39 e5 cmp %r12,%rbp - 40f227: 77 b0 ja 40f1d9 <__correctly_grouped_prefixmb+0x119> - 40f229: 4f 8d 1c 39 lea (%r9,%r15,1),%r11 - 40f22d: 4d 89 e1 mov %r12,%r9 - 40f230: 45 84 d2 test %r10b,%r10b - 40f233: 74 2c je 40f261 <__correctly_grouped_prefixmb+0x1a1> - 40f235: 45 3a 53 ff cmp -0x1(%r11),%r10b - 40f239: 48 8d 43 01 lea 0x1(%rbx),%rax - 40f23d: 4c 89 df mov %r11,%rdi - 40f240: 74 18 je 40f25a <__correctly_grouped_prefixmb+0x19a> - 40f242: eb 3c jmp 40f280 <__correctly_grouped_prefixmb+0x1c0> - 40f244: 0f 1f 40 00 nopl 0x0(%rax) - 40f248: 44 0f b6 47 fe movzbl -0x2(%rdi),%r8d - 40f24d: 48 83 c0 01 add $0x1,%rax - 40f251: 48 83 ef 01 sub $0x1,%rdi - 40f255: 44 38 c1 cmp %r8b,%cl - 40f258: 75 26 jne 40f280 <__correctly_grouped_prefixmb+0x1c0> - 40f25a: 0f b6 08 movzbl (%rax),%ecx - 40f25d: 84 c9 test %cl,%cl - 40f25f: 75 e7 jne 40f248 <__correctly_grouped_prefixmb+0x188> - 40f261: 4d 29 cc sub %r9,%r12 - 40f264: 4c 39 cd cmp %r9,%rbp - 40f267: 77 27 ja 40f290 <__correctly_grouped_prefixmb+0x1d0> - 40f269: 49 0f be c5 movsbq %r13b,%rax - 40f26d: 49 39 c4 cmp %rax,%r12 - 40f270: 0f 85 24 ff ff ff jne 40f19a <__correctly_grouped_prefixmb+0xda> - 40f276: 4d 8d 61 ff lea -0x1(%r9),%r12 - 40f27a: eb 84 jmp 40f200 <__correctly_grouped_prefixmb+0x140> - 40f27c: 0f 1f 40 00 nopl 0x0(%rax) - 40f280: 49 83 e9 01 sub $0x1,%r9 - 40f284: 49 83 eb 01 sub $0x1,%r11 - 40f288: 4c 39 ca cmp %r9,%rdx - 40f28b: 75 a3 jne 40f230 <__correctly_grouped_prefixmb+0x170> - 40f28d: 49 29 d4 sub %rdx,%r12 - 40f290: 4d 39 e5 cmp %r12,%r13 - 40f293: 0f 8c 01 ff ff ff jl 40f19a <__correctly_grouped_prefixmb+0xda> - 40f299: e9 3b ff ff ff jmpq 40f1d9 <__correctly_grouped_prefixmb+0x119> - 40f29e: 66 90 xchg %ax,%ax - 40f2a0: 4c 39 e5 cmp %r12,%rbp - 40f2a3: 0f 87 30 ff ff ff ja 40f1d9 <__correctly_grouped_prefixmb+0x119> - 40f2a9: 4f 8d 1c 39 lea (%r9,%r15,1),%r11 - 40f2ad: 4d 89 e1 mov %r12,%r9 - 40f2b0: 45 84 d2 test %r10b,%r10b - 40f2b3: 74 38 je 40f2ed <__correctly_grouped_prefixmb+0x22d> - 40f2b5: 45 38 53 ff cmp %r10b,-0x1(%r11) - 40f2b9: 48 8d 43 01 lea 0x1(%rbx),%rax - 40f2bd: 4c 89 df mov %r11,%rdi - 40f2c0: 74 24 je 40f2e6 <__correctly_grouped_prefixmb+0x226> - 40f2c2: e9 01 ff ff ff jmpq 40f1c8 <__correctly_grouped_prefixmb+0x108> - 40f2c7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 40f2ce: 00 00 - 40f2d0: 44 0f b6 47 fe movzbl -0x2(%rdi),%r8d - 40f2d5: 48 83 c0 01 add $0x1,%rax - 40f2d9: 48 83 ef 01 sub $0x1,%rdi - 40f2dd: 44 38 c1 cmp %r8b,%cl - 40f2e0: 0f 85 e2 fe ff ff jne 40f1c8 <__correctly_grouped_prefixmb+0x108> - 40f2e6: 0f b6 08 movzbl (%rax),%ecx - 40f2e9: 84 c9 test %cl,%cl - 40f2eb: 75 e3 jne 40f2d0 <__correctly_grouped_prefixmb+0x210> - 40f2ed: 4c 39 cd cmp %r9,%rbp - 40f2f0: 76 84 jbe 40f276 <__correctly_grouped_prefixmb+0x1b6> - 40f2f2: e9 e2 fe ff ff jmpq 40f1d9 <__correctly_grouped_prefixmb+0x119> - 40f2f7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 40f2fe: 00 00 - -000000000040f300 <___asprintf>: - 40f300: 48 81 ec d8 00 00 00 sub $0xd8,%rsp - 40f307: 84 c0 test %al,%al - 40f309: 48 89 54 24 30 mov %rdx,0x30(%rsp) - 40f30e: 48 89 4c 24 38 mov %rcx,0x38(%rsp) - 40f313: 4c 89 44 24 40 mov %r8,0x40(%rsp) - 40f318: 4c 89 4c 24 48 mov %r9,0x48(%rsp) - 40f31d: 74 37 je 40f356 <___asprintf+0x56> - 40f31f: 0f 29 44 24 50 movaps %xmm0,0x50(%rsp) - 40f324: 0f 29 4c 24 60 movaps %xmm1,0x60(%rsp) - 40f329: 0f 29 54 24 70 movaps %xmm2,0x70(%rsp) - 40f32e: 0f 29 9c 24 80 00 00 movaps %xmm3,0x80(%rsp) - 40f335: 00 - 40f336: 0f 29 a4 24 90 00 00 movaps %xmm4,0x90(%rsp) - 40f33d: 00 - 40f33e: 0f 29 ac 24 a0 00 00 movaps %xmm5,0xa0(%rsp) - 40f345: 00 - 40f346: 0f 29 b4 24 b0 00 00 movaps %xmm6,0xb0(%rsp) - 40f34d: 00 - 40f34e: 0f 29 bc 24 c0 00 00 movaps %xmm7,0xc0(%rsp) - 40f355: 00 - 40f356: 48 8d 84 24 e0 00 00 lea 0xe0(%rsp),%rax - 40f35d: 00 - 40f35e: 48 8d 54 24 08 lea 0x8(%rsp),%rdx - 40f363: 48 89 44 24 10 mov %rax,0x10(%rsp) - 40f368: 48 8d 44 24 20 lea 0x20(%rsp),%rax - 40f36d: c7 44 24 08 10 00 00 movl $0x10,0x8(%rsp) - 40f374: 00 - 40f375: c7 44 24 0c 30 00 00 movl $0x30,0xc(%rsp) - 40f37c: 00 - 40f37d: 48 89 44 24 18 mov %rax,0x18(%rsp) - 40f382: e8 19 1f 00 00 callq 4112a0 <_IO_vasprintf> - 40f387: 48 81 c4 d8 00 00 00 add $0xd8,%rsp - 40f38e: c3 retq - 40f38f: 90 nop - -000000000040f390 <__fxprintf>: - 40f390: 55 push %rbp - 40f391: 48 89 e5 mov %rsp,%rbp - 40f394: 41 55 push %r13 - 40f396: 41 54 push %r12 - 40f398: 53 push %rbx - 40f399: 49 89 fc mov %rdi,%r12 - 40f39c: 49 89 f5 mov %rsi,%r13 - 40f39f: 48 81 ec d8 00 00 00 sub $0xd8,%rsp - 40f3a6: 84 c0 test %al,%al - 40f3a8: 48 89 95 40 ff ff ff mov %rdx,-0xc0(%rbp) - 40f3af: 48 89 8d 48 ff ff ff mov %rcx,-0xb8(%rbp) - 40f3b6: 4c 89 85 50 ff ff ff mov %r8,-0xb0(%rbp) - 40f3bd: 4c 89 8d 58 ff ff ff mov %r9,-0xa8(%rbp) - 40f3c4: 74 26 je 40f3ec <__fxprintf+0x5c> - 40f3c6: 0f 29 85 60 ff ff ff movaps %xmm0,-0xa0(%rbp) - 40f3cd: 0f 29 8d 70 ff ff ff movaps %xmm1,-0x90(%rbp) - 40f3d4: 0f 29 55 80 movaps %xmm2,-0x80(%rbp) - 40f3d8: 0f 29 5d 90 movaps %xmm3,-0x70(%rbp) - 40f3dc: 0f 29 65 a0 movaps %xmm4,-0x60(%rbp) - 40f3e0: 0f 29 6d b0 movaps %xmm5,-0x50(%rbp) - 40f3e4: 0f 29 75 c0 movaps %xmm6,-0x40(%rbp) - 40f3e8: 0f 29 7d d0 movaps %xmm7,-0x30(%rbp) - 40f3ec: 4d 85 e4 test %r12,%r12 - 40f3ef: 48 8d 45 10 lea 0x10(%rbp),%rax - 40f3f3: 4c 0f 44 25 3d b3 2b cmove 0x2bb33d(%rip),%r12 # 6ca738 <_IO_stderr> - 40f3fa: 00 - 40f3fb: 48 89 85 20 ff ff ff mov %rax,-0xe0(%rbp) - 40f402: 48 8d 85 30 ff ff ff lea -0xd0(%rbp),%rax - 40f409: c7 85 18 ff ff ff 10 movl $0x10,-0xe8(%rbp) - 40f410: 00 00 00 - 40f413: c7 85 1c ff ff ff 30 movl $0x30,-0xe4(%rbp) - 40f41a: 00 00 00 - 40f41d: 48 89 85 28 ff ff ff mov %rax,-0xd8(%rbp) - 40f424: 41 8b 84 24 c0 00 00 mov 0xc0(%r12),%eax - 40f42b: 00 - 40f42c: 85 c0 test %eax,%eax - 40f42e: 7e 70 jle 40f4a0 <__fxprintf+0x110> - 40f430: 4c 89 ef mov %r13,%rdi - 40f433: 48 89 e3 mov %rsp,%rbx - 40f436: e8 15 42 01 00 callq 423650 - 40f43b: 48 83 c0 01 add $0x1,%rax - 40f43f: 48 8d 14 85 12 00 00 lea 0x12(,%rax,4),%rdx - 40f446: 00 - 40f447: 48 83 e2 f0 and $0xfffffffffffffff0,%rdx - 40f44b: 48 29 d4 sub %rdx,%rsp - 40f44e: 48 85 c0 test %rax,%rax - 40f451: 48 89 e6 mov %rsp,%rsi - 40f454: 74 28 je 40f47e <__fxprintf+0xee> - 40f456: 41 0f be 4d 00 movsbl 0x0(%r13),%ecx - 40f45b: 84 c9 test %cl,%cl - 40f45d: 78 5e js 40f4bd <__fxprintf+0x12d> - 40f45f: 31 d2 xor %edx,%edx - 40f461: eb 0f jmp 40f472 <__fxprintf+0xe2> - 40f463: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 40f468: 41 0f be 4c 15 00 movsbl 0x0(%r13,%rdx,1),%ecx - 40f46e: 84 c9 test %cl,%cl - 40f470: 78 4b js 40f4bd <__fxprintf+0x12d> - 40f472: 89 0c 96 mov %ecx,(%rsi,%rdx,4) - 40f475: 48 83 c2 01 add $0x1,%rdx - 40f479: 48 39 d0 cmp %rdx,%rax - 40f47c: 75 ea jne 40f468 <__fxprintf+0xd8> - 40f47e: 48 8d 95 18 ff ff ff lea -0xe8(%rbp),%rdx - 40f485: 4c 89 e7 mov %r12,%rdi - 40f488: e8 03 fd 04 00 callq 45f190 <_IO_vfwprintf> - 40f48d: 48 89 dc mov %rbx,%rsp - 40f490: 48 8d 65 e8 lea -0x18(%rbp),%rsp - 40f494: 5b pop %rbx - 40f495: 41 5c pop %r12 - 40f497: 41 5d pop %r13 - 40f499: 5d pop %rbp - 40f49a: c3 retq - 40f49b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 40f4a0: 48 8d 95 18 ff ff ff lea -0xe8(%rbp),%rdx - 40f4a7: 4c 89 ee mov %r13,%rsi - 40f4aa: 4c 89 e7 mov %r12,%rdi - 40f4ad: e8 1e 54 04 00 callq 4548d0 <_IO_vfprintf> - 40f4b2: 48 8d 65 e8 lea -0x18(%rbp),%rsp - 40f4b6: 5b pop %rbx - 40f4b7: 41 5c pop %r12 - 40f4b9: 41 5d pop %r13 - 40f4bb: 5d pop %rbp - 40f4bc: c3 retq - 40f4bd: b9 48 19 4a 00 mov $0x4a1948,%ecx - 40f4c2: ba 2c 00 00 00 mov $0x2c,%edx - 40f4c7: be 25 19 4a 00 mov $0x4a1925,%esi - 40f4cc: bf 30 19 4a 00 mov $0x4a1930,%edi - 40f4d1: e8 6a 22 ff ff callq 401740 <__assert_fail> - 40f4d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 40f4dd: 00 00 00 - -000000000040f4e0 <_IO_new_fclose>: - 40f4e0: 41 54 push %r12 - 40f4e2: 55 push %rbp - 40f4e3: 53 push %rbx - 40f4e4: 8b 07 mov (%rdi),%eax - 40f4e6: 48 89 fb mov %rdi,%rbx - 40f4e9: f6 c4 20 test $0x20,%ah - 40f4ec: 0f 85 fe 00 00 00 jne 40f5f0 <_IO_new_fclose+0x110> - 40f4f2: 89 c2 mov %eax,%edx - 40f4f4: 81 e2 00 80 00 00 and $0x8000,%edx - 40f4fa: 0f 84 fc 00 00 00 je 40f5fc <_IO_new_fclose+0x11c> - 40f500: c1 e0 1a shl $0x1a,%eax - 40f503: c1 f8 1f sar $0x1f,%eax - 40f506: 85 d2 test %edx,%edx - 40f508: 89 c5 mov %eax,%ebp - 40f50a: 0f 84 71 01 00 00 je 40f681 <_IO_new_fclose+0x1a1> - 40f510: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 40f517: 31 f6 xor %esi,%esi - 40f519: 48 89 df mov %rbx,%rdi - 40f51c: ff 50 10 callq *0x10(%rax) - 40f51f: 8b 83 c0 00 00 00 mov 0xc0(%rbx),%eax - 40f525: 85 c0 test %eax,%eax - 40f527: 0f 8e a3 01 00 00 jle 40f6d0 <_IO_new_fclose+0x1f0> - 40f52d: 4c 8b a3 98 00 00 00 mov 0x98(%rbx),%r12 - 40f534: be 01 00 00 00 mov $0x1,%esi - 40f539: 31 c0 xor %eax,%eax - 40f53b: 83 3d 7a dc 2b 00 00 cmpl $0x0,0x2bdc7a(%rip) # 6cd1bc <__libc_multiple_threads> - 40f542: 74 0c je 40f550 <_IO_new_fclose+0x70> - 40f544: f0 0f b1 35 84 dd 2b lock cmpxchg %esi,0x2bdd84(%rip) # 6cd2d0 <__gconv_lock> - 40f54b: 00 - 40f54c: 75 0b jne 40f559 <_IO_new_fclose+0x79> - 40f54e: eb 23 jmp 40f573 <_IO_new_fclose+0x93> - 40f550: 0f b1 35 79 dd 2b 00 cmpxchg %esi,0x2bdd79(%rip) # 6cd2d0 <__gconv_lock> - 40f557: 74 1a je 40f573 <_IO_new_fclose+0x93> - 40f559: 48 8d 3d 70 dd 2b 00 lea 0x2bdd70(%rip),%rdi # 6cd2d0 <__gconv_lock> - 40f560: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 40f567: e8 64 30 03 00 callq 4425d0 <__lll_lock_wait_private> - 40f56c: 48 81 c4 80 00 00 00 add $0x80,%rsp - 40f573: 49 8b 7c 24 48 mov 0x48(%r12),%rdi - 40f578: e8 43 5f 03 00 callq 4454c0 <__gconv_release_step> - 40f57d: 49 8b bc 24 88 00 00 mov 0x88(%r12),%rdi - 40f584: 00 - 40f585: e8 36 5f 03 00 callq 4454c0 <__gconv_release_step> - 40f58a: 83 3d 2b dc 2b 00 00 cmpl $0x0,0x2bdc2b(%rip) # 6cd1bc <__libc_multiple_threads> - 40f591: 74 0b je 40f59e <_IO_new_fclose+0xbe> - 40f593: f0 ff 0d 36 dd 2b 00 lock decl 0x2bdd36(%rip) # 6cd2d0 <__gconv_lock> - 40f59a: 75 0a jne 40f5a6 <_IO_new_fclose+0xc6> - 40f59c: eb 22 jmp 40f5c0 <_IO_new_fclose+0xe0> - 40f59e: ff 0d 2c dd 2b 00 decl 0x2bdd2c(%rip) # 6cd2d0 <__gconv_lock> - 40f5a4: 74 1a je 40f5c0 <_IO_new_fclose+0xe0> - 40f5a6: 48 8d 3d 23 dd 2b 00 lea 0x2bdd23(%rip),%rdi # 6cd2d0 <__gconv_lock> - 40f5ad: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 40f5b4: e8 47 30 03 00 callq 442600 <__lll_unlock_wake_private> - 40f5b9: 48 81 c4 80 00 00 00 add $0x80,%rsp - 40f5c0: 48 3b 1d 81 b1 2b 00 cmp 0x2bb181(%rip),%rbx # 6ca748 <_IO_stdin> - 40f5c7: 74 1a je 40f5e3 <_IO_new_fclose+0x103> - 40f5c9: 48 3b 1d 70 b1 2b 00 cmp 0x2bb170(%rip),%rbx # 6ca740 <_IO_stdout> - 40f5d0: 74 11 je 40f5e3 <_IO_new_fclose+0x103> - 40f5d2: 48 3b 1d 5f b1 2b 00 cmp 0x2bb15f(%rip),%rbx # 6ca738 <_IO_stderr> - 40f5d9: 74 08 je 40f5e3 <_IO_new_fclose+0x103> - 40f5db: 48 89 df mov %rbx,%rdi - 40f5de: e8 cd e7 00 00 callq 41ddb0 <__cfree> - 40f5e3: 89 e8 mov %ebp,%eax - 40f5e5: 5b pop %rbx - 40f5e6: 5d pop %rbp - 40f5e7: 41 5c pop %r12 - 40f5e9: c3 retq - 40f5ea: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 40f5f0: e8 5b 4e 00 00 callq 414450 <_IO_un_link> - 40f5f5: 8b 03 mov (%rbx),%eax - 40f5f7: f6 c4 80 test $0x80,%ah - 40f5fa: 75 5a jne 40f656 <_IO_new_fclose+0x176> - 40f5fc: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx - 40f603: 64 4c 8b 04 25 10 00 mov %fs:0x10,%r8 - 40f60a: 00 00 - 40f60c: 4c 3b 42 08 cmp 0x8(%rdx),%r8 - 40f610: 74 40 je 40f652 <_IO_new_fclose+0x172> - 40f612: be 01 00 00 00 mov $0x1,%esi - 40f617: 31 c0 xor %eax,%eax - 40f619: 83 3d 9c db 2b 00 00 cmpl $0x0,0x2bdb9c(%rip) # 6cd1bc <__libc_multiple_threads> - 40f620: 74 08 je 40f62a <_IO_new_fclose+0x14a> - 40f622: f0 0f b1 32 lock cmpxchg %esi,(%rdx) - 40f626: 75 07 jne 40f62f <_IO_new_fclose+0x14f> - 40f628: eb 1b jmp 40f645 <_IO_new_fclose+0x165> - 40f62a: 0f b1 32 cmpxchg %esi,(%rdx) - 40f62d: 74 16 je 40f645 <_IO_new_fclose+0x165> - 40f62f: 48 8d 3a lea (%rdx),%rdi - 40f632: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 40f639: e8 92 2f 03 00 callq 4425d0 <__lll_lock_wait_private> - 40f63e: 48 81 c4 80 00 00 00 add $0x80,%rsp - 40f645: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx - 40f64c: 8b 03 mov (%rbx),%eax - 40f64e: 4c 89 42 08 mov %r8,0x8(%rdx) - 40f652: 83 42 04 01 addl $0x1,0x4(%rdx) - 40f656: 89 c2 mov %eax,%edx - 40f658: 81 e2 00 80 00 00 and $0x8000,%edx - 40f65e: f6 c4 20 test $0x20,%ah - 40f661: 0f 84 99 fe ff ff je 40f500 <_IO_new_fclose+0x20> - 40f667: 48 89 df mov %rbx,%rdi - 40f66a: e8 71 3c 00 00 callq 4132e0 <_IO_new_file_close_it> - 40f66f: 8b 13 mov (%rbx),%edx - 40f671: 89 c5 mov %eax,%ebp - 40f673: 81 e2 00 80 00 00 and $0x8000,%edx - 40f679: 85 d2 test %edx,%edx - 40f67b: 0f 85 8f fe ff ff jne 40f510 <_IO_new_fclose+0x30> - 40f681: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx - 40f688: 83 6a 04 01 subl $0x1,0x4(%rdx) - 40f68c: 0f 85 7e fe ff ff jne 40f510 <_IO_new_fclose+0x30> - 40f692: 48 c7 42 08 00 00 00 movq $0x0,0x8(%rdx) - 40f699: 00 - 40f69a: 83 3d 1b db 2b 00 00 cmpl $0x0,0x2bdb1b(%rip) # 6cd1bc <__libc_multiple_threads> - 40f6a1: 74 07 je 40f6aa <_IO_new_fclose+0x1ca> - 40f6a3: f0 ff 0a lock decl (%rdx) - 40f6a6: 75 06 jne 40f6ae <_IO_new_fclose+0x1ce> - 40f6a8: eb 1a jmp 40f6c4 <_IO_new_fclose+0x1e4> - 40f6aa: ff 0a decl (%rdx) - 40f6ac: 74 16 je 40f6c4 <_IO_new_fclose+0x1e4> - 40f6ae: 48 8d 3a lea (%rdx),%rdi - 40f6b1: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 40f6b8: e8 43 2f 03 00 callq 442600 <__lll_unlock_wake_private> - 40f6bd: 48 81 c4 80 00 00 00 add $0x80,%rsp - 40f6c4: e9 47 fe ff ff jmpq 40f510 <_IO_new_fclose+0x30> - 40f6c9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 40f6d0: 48 83 7b 48 00 cmpq $0x0,0x48(%rbx) - 40f6d5: 0f 84 e5 fe ff ff je 40f5c0 <_IO_new_fclose+0xe0> - 40f6db: 48 89 df mov %rbx,%rdi - 40f6de: e8 4d 53 00 00 callq 414a30 <_IO_free_backup_area> - 40f6e3: e9 d8 fe ff ff jmpq 40f5c0 <_IO_new_fclose+0xe0> - 40f6e8: 48 89 c6 mov %rax,%rsi - 40f6eb: f7 03 00 80 00 00 testl $0x8000,(%rbx) - 40f6f1: 75 3f jne 40f732 <_IO_new_fclose+0x252> - 40f6f3: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx - 40f6fa: 83 6a 04 01 subl $0x1,0x4(%rdx) - 40f6fe: 75 32 jne 40f732 <_IO_new_fclose+0x252> - 40f700: 48 c7 42 08 00 00 00 movq $0x0,0x8(%rdx) - 40f707: 00 - 40f708: 83 3d ad da 2b 00 00 cmpl $0x0,0x2bdaad(%rip) # 6cd1bc <__libc_multiple_threads> - 40f70f: 74 07 je 40f718 <_IO_new_fclose+0x238> - 40f711: f0 ff 0a lock decl (%rdx) - 40f714: 75 06 jne 40f71c <_IO_new_fclose+0x23c> - 40f716: eb 1a jmp 40f732 <_IO_new_fclose+0x252> - 40f718: ff 0a decl (%rdx) - 40f71a: 74 16 je 40f732 <_IO_new_fclose+0x252> - 40f71c: 48 8d 3a lea (%rdx),%rdi - 40f71f: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 40f726: e8 d5 2e 03 00 callq 442600 <__lll_unlock_wake_private> - 40f72b: 48 81 c4 80 00 00 00 add $0x80,%rsp - 40f732: 48 89 f7 mov %rsi,%rdi - 40f735: e8 36 ce 08 00 callq 49c570 <_Unwind_Resume> - 40f73a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - -000000000040f740 <_IO_fflush>: - 40f740: 48 85 ff test %rdi,%rdi - 40f743: 0f 84 d7 00 00 00 je 40f820 <_IO_fflush+0xe0> - 40f749: 53 push %rbx - 40f74a: 8b 07 mov (%rdi),%eax - 40f74c: 48 89 fa mov %rdi,%rdx - 40f74f: 25 00 80 00 00 and $0x8000,%eax - 40f754: 75 59 jne 40f7af <_IO_fflush+0x6f> - 40f756: 4c 8b 87 88 00 00 00 mov 0x88(%rdi),%r8 - 40f75d: 64 4c 8b 0c 25 10 00 mov %fs:0x10,%r9 - 40f764: 00 00 - 40f766: 4d 3b 48 08 cmp 0x8(%r8),%r9 - 40f76a: 74 3e je 40f7aa <_IO_fflush+0x6a> - 40f76c: be 01 00 00 00 mov $0x1,%esi - 40f771: 83 3d 44 da 2b 00 00 cmpl $0x0,0x2bda44(%rip) # 6cd1bc <__libc_multiple_threads> - 40f778: 74 09 je 40f783 <_IO_fflush+0x43> - 40f77a: f0 41 0f b1 30 lock cmpxchg %esi,(%r8) - 40f77f: 75 08 jne 40f789 <_IO_fflush+0x49> - 40f781: eb 1c jmp 40f79f <_IO_fflush+0x5f> - 40f783: 41 0f b1 30 cmpxchg %esi,(%r8) - 40f787: 74 16 je 40f79f <_IO_fflush+0x5f> - 40f789: 49 8d 38 lea (%r8),%rdi - 40f78c: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 40f793: e8 38 2e 03 00 callq 4425d0 <__lll_lock_wait_private> - 40f798: 48 81 c4 80 00 00 00 add $0x80,%rsp - 40f79f: 4c 8b 82 88 00 00 00 mov 0x88(%rdx),%r8 - 40f7a6: 4d 89 48 08 mov %r9,0x8(%r8) - 40f7aa: 41 83 40 04 01 addl $0x1,0x4(%r8) - 40f7af: 48 8b 82 d8 00 00 00 mov 0xd8(%rdx),%rax - 40f7b6: 48 89 d3 mov %rdx,%rbx - 40f7b9: 48 89 d7 mov %rdx,%rdi - 40f7bc: ff 50 60 callq *0x60(%rax) - 40f7bf: 31 d2 xor %edx,%edx - 40f7c1: 85 c0 test %eax,%eax - 40f7c3: 0f 95 c2 setne %dl - 40f7c6: f7 da neg %edx - 40f7c8: f7 03 00 80 00 00 testl $0x8000,(%rbx) - 40f7ce: 74 08 je 40f7d8 <_IO_fflush+0x98> - 40f7d0: 89 d0 mov %edx,%eax - 40f7d2: 5b pop %rbx - 40f7d3: c3 retq - 40f7d4: 0f 1f 40 00 nopl 0x0(%rax) - 40f7d8: 48 8b b3 88 00 00 00 mov 0x88(%rbx),%rsi - 40f7df: 83 6e 04 01 subl $0x1,0x4(%rsi) - 40f7e3: 75 eb jne 40f7d0 <_IO_fflush+0x90> - 40f7e5: 48 c7 46 08 00 00 00 movq $0x0,0x8(%rsi) - 40f7ec: 00 - 40f7ed: 83 3d c8 d9 2b 00 00 cmpl $0x0,0x2bd9c8(%rip) # 6cd1bc <__libc_multiple_threads> - 40f7f4: 74 07 je 40f7fd <_IO_fflush+0xbd> - 40f7f6: f0 ff 0e lock decl (%rsi) - 40f7f9: 75 06 jne 40f801 <_IO_fflush+0xc1> - 40f7fb: eb 1a jmp 40f817 <_IO_fflush+0xd7> - 40f7fd: ff 0e decl (%rsi) - 40f7ff: 74 16 je 40f817 <_IO_fflush+0xd7> - 40f801: 48 8d 3e lea (%rsi),%rdi - 40f804: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 40f80b: e8 f0 2d 03 00 callq 442600 <__lll_unlock_wake_private> - 40f810: 48 81 c4 80 00 00 00 add $0x80,%rsp - 40f817: 89 d0 mov %edx,%eax - 40f819: 5b pop %rbx - 40f81a: c3 retq - 40f81b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 40f820: e9 ab 64 00 00 jmpq 415cd0 <_IO_flush_all> - 40f825: 48 89 c6 mov %rax,%rsi - 40f828: f7 03 00 80 00 00 testl $0x8000,(%rbx) - 40f82e: 75 3f jne 40f86f <_IO_fflush+0x12f> - 40f830: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx - 40f837: 83 6a 04 01 subl $0x1,0x4(%rdx) - 40f83b: 75 32 jne 40f86f <_IO_fflush+0x12f> - 40f83d: 48 c7 42 08 00 00 00 movq $0x0,0x8(%rdx) - 40f844: 00 - 40f845: 83 3d 70 d9 2b 00 00 cmpl $0x0,0x2bd970(%rip) # 6cd1bc <__libc_multiple_threads> - 40f84c: 74 07 je 40f855 <_IO_fflush+0x115> - 40f84e: f0 ff 0a lock decl (%rdx) - 40f851: 75 06 jne 40f859 <_IO_fflush+0x119> - 40f853: eb 1a jmp 40f86f <_IO_fflush+0x12f> - 40f855: ff 0a decl (%rdx) - 40f857: 74 16 je 40f86f <_IO_fflush+0x12f> - 40f859: 48 8d 3a lea (%rdx),%rdi - 40f85c: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 40f863: e8 98 2d 03 00 callq 442600 <__lll_unlock_wake_private> - 40f868: 48 81 c4 80 00 00 00 add $0x80,%rsp - 40f86f: 48 89 f7 mov %rsi,%rdi - 40f872: e8 f9 cc 08 00 callq 49c570 <_Unwind_Resume> - 40f877: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 40f87e: 00 00 - -000000000040f880 <__fopen_maybe_mmap>: - 40f880: f6 47 74 01 testb $0x1,0x74(%rdi) - 40f884: 48 89 f8 mov %rdi,%rax - 40f887: 74 30 je 40f8b9 <__fopen_maybe_mmap+0x39> - 40f889: f6 07 08 testb $0x8,(%rdi) - 40f88c: 74 2b je 40f8b9 <__fopen_maybe_mmap+0x39> - 40f88e: 8b 97 c0 00 00 00 mov 0xc0(%rdi),%edx - 40f894: b9 a0 19 4a 00 mov $0x4a19a0,%ecx - 40f899: 85 d2 test %edx,%edx - 40f89b: ba a0 1c 4a 00 mov $0x4a1ca0,%edx - 40f8a0: 48 0f 4f d1 cmovg %rcx,%rdx - 40f8a4: 48 89 97 d8 00 00 00 mov %rdx,0xd8(%rdi) - 40f8ab: 48 8b 97 a0 00 00 00 mov 0xa0(%rdi),%rdx - 40f8b2: 48 89 8a 30 01 00 00 mov %rcx,0x130(%rdx) - 40f8b9: f3 c3 repz retq - 40f8bb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - -000000000040f8c0 <__fopen_internal>: - 40f8c0: 41 55 push %r13 - 40f8c2: 41 54 push %r12 - 40f8c4: 41 89 d5 mov %edx,%r13d - 40f8c7: 55 push %rbp - 40f8c8: 53 push %rbx - 40f8c9: 48 89 fd mov %rdi,%rbp - 40f8cc: bf 28 02 00 00 mov $0x228,%edi - 40f8d1: 49 89 f4 mov %rsi,%r12 - 40f8d4: 48 83 ec 08 sub $0x8,%rsp - 40f8d8: e8 33 e1 00 00 callq 41da10 <__libc_malloc> - 40f8dd: 48 85 c0 test %rax,%rax - 40f8e0: 0f 84 b2 00 00 00 je 40f998 <__fopen_internal+0xd8> - 40f8e6: 48 8d 90 e0 00 00 00 lea 0xe0(%rax),%rdx - 40f8ed: 48 8d 88 f0 00 00 00 lea 0xf0(%rax),%rcx - 40f8f4: 48 89 c3 mov %rax,%rbx - 40f8f7: 31 f6 xor %esi,%esi - 40f8f9: 48 89 c7 mov %rax,%rdi - 40f8fc: 41 b8 20 1b 4a 00 mov $0x4a1b20,%r8d - 40f902: 48 89 90 88 00 00 00 mov %rdx,0x88(%rax) - 40f909: 31 d2 xor %edx,%edx - 40f90b: e8 b0 5b 00 00 callq 4154c0 <_IO_no_init> - 40f910: 48 89 df mov %rbx,%rdi - 40f913: 48 c7 83 d8 00 00 00 movq $0x4a1e20,0xd8(%rbx) - 40f91a: 20 1e 4a 00 - 40f91e: e8 0d 37 00 00 callq 413030 <_IO_new_file_init> - 40f923: 44 89 e9 mov %r13d,%ecx - 40f926: 4c 89 e2 mov %r12,%rdx - 40f929: 48 89 ee mov %rbp,%rsi - 40f92c: 48 89 df mov %rbx,%rdi - 40f92f: e8 2c 3b 00 00 callq 413460 <_IO_new_file_fopen> - 40f934: 48 85 c0 test %rax,%rax - 40f937: 74 63 je 40f99c <__fopen_internal+0xdc> - 40f939: f6 43 74 01 testb $0x1,0x74(%rbx) - 40f93d: 74 05 je 40f944 <__fopen_internal+0x84> - 40f93f: f6 03 08 testb $0x8,(%rbx) - 40f942: 75 14 jne 40f958 <__fopen_internal+0x98> - 40f944: 48 83 c4 08 add $0x8,%rsp - 40f948: 48 89 d8 mov %rbx,%rax - 40f94b: 5b pop %rbx - 40f94c: 5d pop %rbp - 40f94d: 41 5c pop %r12 - 40f94f: 41 5d pop %r13 - 40f951: c3 retq - 40f952: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 40f958: 8b 83 c0 00 00 00 mov 0xc0(%rbx),%eax - 40f95e: ba a0 19 4a 00 mov $0x4a19a0,%edx - 40f963: 85 c0 test %eax,%eax - 40f965: b8 a0 1c 4a 00 mov $0x4a1ca0,%eax - 40f96a: 48 0f 4f c2 cmovg %rdx,%rax - 40f96e: 48 89 83 d8 00 00 00 mov %rax,0xd8(%rbx) - 40f975: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 40f97c: 48 89 90 30 01 00 00 mov %rdx,0x130(%rax) - 40f983: 48 83 c4 08 add $0x8,%rsp - 40f987: 48 89 d8 mov %rbx,%rax - 40f98a: 5b pop %rbx - 40f98b: 5d pop %rbp - 40f98c: 41 5c pop %r12 - 40f98e: 41 5d pop %r13 - 40f990: c3 retq - 40f991: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 40f998: 31 db xor %ebx,%ebx - 40f99a: eb a8 jmp 40f944 <__fopen_internal+0x84> - 40f99c: 48 89 df mov %rbx,%rdi - 40f99f: e8 ac 4a 00 00 callq 414450 <_IO_un_link> - 40f9a4: 48 89 df mov %rbx,%rdi - 40f9a7: 31 db xor %ebx,%ebx - 40f9a9: e8 02 e4 00 00 callq 41ddb0 <__cfree> - 40f9ae: eb 94 jmp 40f944 <__fopen_internal+0x84> - -000000000040f9b0 <_IO_new_fopen>: - 40f9b0: 41 54 push %r12 - 40f9b2: 55 push %rbp - 40f9b3: 48 89 fd mov %rdi,%rbp - 40f9b6: 53 push %rbx - 40f9b7: bf 28 02 00 00 mov $0x228,%edi - 40f9bc: 49 89 f4 mov %rsi,%r12 - 40f9bf: e8 4c e0 00 00 callq 41da10 <__libc_malloc> - 40f9c4: 48 85 c0 test %rax,%rax - 40f9c7: 0f 84 a3 00 00 00 je 40fa70 <_IO_new_fopen+0xc0> - 40f9cd: 48 8d 90 e0 00 00 00 lea 0xe0(%rax),%rdx - 40f9d4: 48 8d 88 f0 00 00 00 lea 0xf0(%rax),%rcx - 40f9db: 48 89 c3 mov %rax,%rbx - 40f9de: 31 f6 xor %esi,%esi - 40f9e0: 48 89 c7 mov %rax,%rdi - 40f9e3: 41 b8 20 1b 4a 00 mov $0x4a1b20,%r8d - 40f9e9: 48 89 90 88 00 00 00 mov %rdx,0x88(%rax) - 40f9f0: 31 d2 xor %edx,%edx - 40f9f2: e8 c9 5a 00 00 callq 4154c0 <_IO_no_init> - 40f9f7: 48 89 df mov %rbx,%rdi - 40f9fa: 48 c7 83 d8 00 00 00 movq $0x4a1e20,0xd8(%rbx) - 40fa01: 20 1e 4a 00 - 40fa05: e8 26 36 00 00 callq 413030 <_IO_new_file_init> - 40fa0a: b9 01 00 00 00 mov $0x1,%ecx - 40fa0f: 4c 89 e2 mov %r12,%rdx - 40fa12: 48 89 ee mov %rbp,%rsi - 40fa15: 48 89 df mov %rbx,%rdi - 40fa18: e8 43 3a 00 00 callq 413460 <_IO_new_file_fopen> - 40fa1d: 48 85 c0 test %rax,%rax - 40fa20: 74 52 je 40fa74 <_IO_new_fopen+0xc4> - 40fa22: f6 43 74 01 testb $0x1,0x74(%rbx) - 40fa26: 74 05 je 40fa2d <_IO_new_fopen+0x7d> - 40fa28: f6 03 08 testb $0x8,(%rbx) - 40fa2b: 75 0b jne 40fa38 <_IO_new_fopen+0x88> - 40fa2d: 48 89 d8 mov %rbx,%rax - 40fa30: 5b pop %rbx - 40fa31: 5d pop %rbp - 40fa32: 41 5c pop %r12 - 40fa34: c3 retq - 40fa35: 0f 1f 00 nopl (%rax) - 40fa38: 8b 83 c0 00 00 00 mov 0xc0(%rbx),%eax - 40fa3e: ba a0 19 4a 00 mov $0x4a19a0,%edx - 40fa43: 85 c0 test %eax,%eax - 40fa45: b8 a0 1c 4a 00 mov $0x4a1ca0,%eax - 40fa4a: 48 0f 4f c2 cmovg %rdx,%rax - 40fa4e: 48 89 83 d8 00 00 00 mov %rax,0xd8(%rbx) - 40fa55: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 40fa5c: 48 89 90 30 01 00 00 mov %rdx,0x130(%rax) - 40fa63: 48 89 d8 mov %rbx,%rax - 40fa66: 5b pop %rbx - 40fa67: 5d pop %rbp - 40fa68: 41 5c pop %r12 - 40fa6a: c3 retq - 40fa6b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 40fa70: 31 db xor %ebx,%ebx - 40fa72: eb b9 jmp 40fa2d <_IO_new_fopen+0x7d> - 40fa74: 48 89 df mov %rbx,%rdi - 40fa77: e8 d4 49 00 00 callq 414450 <_IO_un_link> - 40fa7c: 48 89 df mov %rbx,%rdi - 40fa7f: 31 db xor %ebx,%ebx - 40fa81: e8 2a e3 00 00 callq 41ddb0 <__cfree> - 40fa86: eb a5 jmp 40fa2d <_IO_new_fopen+0x7d> - 40fa88: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 40fa8f: 00 - -000000000040fa90 : - 40fa90: 41 54 push %r12 - 40fa92: 55 push %rbp - 40fa93: 41 89 f4 mov %esi,%r12d - 40fa96: 53 push %rbx - 40fa97: 48 89 fb mov %rdi,%rbx - 40fa9a: 48 83 ec 10 sub $0x10,%rsp - 40fa9e: 48 8b af 98 00 00 00 mov 0x98(%rdi),%rbp - 40faa5: 48 89 ef mov %rbp,%rdi - 40faa8: ff 55 20 callq *0x20(%rbp) - 40faab: 85 c0 test %eax,%eax - 40faad: 0f 9f c2 setg %dl - 40fab0: 41 38 d4 cmp %dl,%r12b - 40fab3: 73 3b jae 40faf0 - 40fab5: 48 8b 53 08 mov 0x8(%rbx),%rdx - 40fab9: 48 2b 53 18 sub 0x18(%rbx),%rdx - 40fabd: 48 63 c8 movslq %eax,%rcx - 40fac0: 48 8b b3 a0 00 00 00 mov 0xa0(%rbx),%rsi - 40fac7: 48 89 d0 mov %rdx,%rax - 40faca: 48 99 cqto - 40facc: 48 f7 f9 idiv %rcx - 40facf: 48 c1 e0 02 shl $0x2,%rax - 40fad3: 48 01 46 08 add %rax,0x8(%rsi) - 40fad7: 48 8b 46 08 mov 0x8(%rsi),%rax - 40fadb: 48 89 06 mov %rax,(%rsi) - 40fade: 31 c0 xor %eax,%eax - 40fae0: 48 83 c4 10 add $0x10,%rsp - 40fae4: 5b pop %rbx - 40fae5: 5d pop %rbp - 40fae6: 41 5c pop %r12 - 40fae8: c3 retq - 40fae9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 40faf0: 48 8b 43 18 mov 0x18(%rbx),%rax - 40faf4: 48 89 44 24 08 mov %rax,0x8(%rsp) - 40faf9: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 40fb00: 48 8b 50 58 mov 0x58(%rax),%rdx - 40fb04: 48 89 50 60 mov %rdx,0x60(%rax) - 40fb08: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 40fb0f: 48 8b 4b 08 mov 0x8(%rbx),%rcx - 40fb13: 48 8b 53 18 mov 0x18(%rbx),%rdx - 40fb17: 48 8d 78 08 lea 0x8(%rax),%rdi - 40fb1b: 48 8d 70 58 lea 0x58(%rax),%rsi - 40fb1f: 57 push %rdi - 40fb20: ff 70 38 pushq 0x38(%rax) - 40fb23: 48 89 ef mov %rbp,%rdi - 40fb26: 4c 8b 48 10 mov 0x10(%rax),%r9 - 40fb2a: 4c 8d 44 24 18 lea 0x18(%rsp),%r8 - 40fb2f: ff 55 18 callq *0x18(%rbp) - 40fb32: 83 f8 02 cmp $0x2,%eax - 40fb35: 5a pop %rdx - 40fb36: 59 pop %rcx - 40fb37: 74 17 je 40fb50 - 40fb39: 83 f8 01 cmp $0x1,%eax - 40fb3c: 74 bb je 40faf9 - 40fb3e: 48 8b b3 a0 00 00 00 mov 0xa0(%rbx),%rsi - 40fb45: eb 90 jmp 40fad7 - 40fb47: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 40fb4e: 00 00 - 40fb50: 83 0b 20 orl $0x20,(%rbx) - 40fb53: b8 ff ff ff ff mov $0xffffffff,%eax - 40fb58: eb 86 jmp 40fae0 - 40fb5a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - -000000000040fb60 <_IO_wfile_underflow>: - 40fb60: 8b 07 mov (%rdi),%eax - 40fb62: a8 04 test $0x4,%al - 40fb64: 0f 85 96 04 00 00 jne 410000 <_IO_wfile_underflow+0x4a0> - 40fb6a: 48 8b 87 a0 00 00 00 mov 0xa0(%rdi),%rax - 40fb71: 48 8b 10 mov (%rax),%rdx - 40fb74: 48 3b 50 08 cmp 0x8(%rax),%rdx - 40fb78: 0f 82 62 03 00 00 jb 40fee0 <_IO_wfile_underflow+0x380> - 40fb7e: 41 57 push %r15 - 40fb80: 41 56 push %r14 - 40fb82: 41 55 push %r13 - 40fb84: 41 54 push %r12 - 40fb86: 55 push %rbp - 40fb87: 53 push %rbx - 40fb88: 48 89 fb mov %rdi,%rbx - 40fb8b: 48 83 ec 28 sub $0x28,%rsp - 40fb8f: 48 8b 57 08 mov 0x8(%rdi),%rdx - 40fb93: 48 3b 57 10 cmp 0x10(%rdi),%rdx - 40fb97: 4c 8b a7 98 00 00 00 mov 0x98(%rdi),%r12 - 40fb9e: 0f 82 7c 03 00 00 jb 40ff20 <_IO_wfile_underflow+0x3c0> - 40fba4: 48 8b 47 38 mov 0x38(%rdi),%rax - 40fba8: 48 89 47 10 mov %rax,0x10(%rdi) - 40fbac: 48 89 47 08 mov %rax,0x8(%rdi) - 40fbb0: 48 89 47 18 mov %rax,0x18(%rdi) - 40fbb4: 48 85 c0 test %rax,%rax - 40fbb7: 0f 84 8b 04 00 00 je 410048 <_IO_wfile_underflow+0x4e8> - 40fbbd: 48 89 43 30 mov %rax,0x30(%rbx) - 40fbc1: 48 89 43 28 mov %rax,0x28(%rbx) - 40fbc5: 48 89 43 20 mov %rax,0x20(%rbx) - 40fbc9: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 40fbd0: 48 83 78 30 00 cmpq $0x0,0x30(%rax) - 40fbd5: 0f 84 45 04 00 00 je 410020 <_IO_wfile_underflow+0x4c0> - 40fbdb: f7 03 02 02 00 00 testl $0x202,(%rbx) - 40fbe1: 0f 84 a9 00 00 00 je 40fc90 <_IO_wfile_underflow+0x130> - 40fbe7: 48 8b 2d 52 ab 2b 00 mov 0x2bab52(%rip),%rbp # 6ca740 <_IO_stdout> - 40fbee: 8b 55 00 mov 0x0(%rbp),%edx - 40fbf1: 89 d0 mov %edx,%eax - 40fbf3: 25 00 80 00 00 and $0x8000,%eax - 40fbf8: 0f 85 92 03 00 00 jne 40ff90 <_IO_wfile_underflow+0x430> - 40fbfe: 4c 8b 85 88 00 00 00 mov 0x88(%rbp),%r8 - 40fc05: 64 4c 8b 0c 25 10 00 mov %fs:0x10,%r9 - 40fc0c: 00 00 - 40fc0e: 4d 3b 48 08 cmp 0x8(%r8),%r9 - 40fc12: 0f 84 c4 04 00 00 je 4100dc <_IO_wfile_underflow+0x57c> - 40fc18: be 01 00 00 00 mov $0x1,%esi - 40fc1d: 83 3d 98 d5 2b 00 00 cmpl $0x0,0x2bd598(%rip) # 6cd1bc <__libc_multiple_threads> - 40fc24: 74 09 je 40fc2f <_IO_wfile_underflow+0xcf> - 40fc26: f0 41 0f b1 30 lock cmpxchg %esi,(%r8) - 40fc2b: 75 08 jne 40fc35 <_IO_wfile_underflow+0xd5> - 40fc2d: eb 1c jmp 40fc4b <_IO_wfile_underflow+0xeb> - 40fc2f: 41 0f b1 30 cmpxchg %esi,(%r8) - 40fc33: 74 16 je 40fc4b <_IO_wfile_underflow+0xeb> - 40fc35: 49 8d 38 lea (%r8),%rdi - 40fc38: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 40fc3f: e8 8c 29 03 00 callq 4425d0 <__lll_lock_wait_private> - 40fc44: 48 81 c4 80 00 00 00 add $0x80,%rsp - 40fc4b: 48 8b 3d ee aa 2b 00 mov 0x2baaee(%rip),%rdi # 6ca740 <_IO_stdout> - 40fc52: 4c 8b 85 88 00 00 00 mov 0x88(%rbp),%r8 - 40fc59: 8b 17 mov (%rdi),%edx - 40fc5b: 4d 89 48 08 mov %r9,0x8(%r8) - 40fc5f: 81 e2 88 02 00 00 and $0x288,%edx - 40fc65: 41 83 40 04 01 addl $0x1,0x4(%r8) - 40fc6a: 81 fa 80 02 00 00 cmp $0x280,%edx - 40fc70: 0f 84 2f 03 00 00 je 40ffa5 <_IO_wfile_underflow+0x445> - 40fc76: f7 45 00 00 80 00 00 testl $0x8000,0x0(%rbp) - 40fc7d: 75 11 jne 40fc90 <_IO_wfile_underflow+0x130> - 40fc7f: 48 8b 95 88 00 00 00 mov 0x88(%rbp),%rdx - 40fc86: 83 6a 04 01 subl $0x1,0x4(%rdx) - 40fc8a: 0f 84 15 04 00 00 je 4100a5 <_IO_wfile_underflow+0x545> - 40fc90: 48 89 df mov %rbx,%rdi - 40fc93: 4c 8d 6c 24 10 lea 0x10(%rsp),%r13 - 40fc98: 31 ed xor %ebp,%ebp - 40fc9a: e8 21 4d 00 00 callq 4149c0 <_IO_switch_to_get_mode> - 40fc9f: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 40fca6: 4c 8b 73 10 mov 0x10(%rbx),%r14 - 40fcaa: 48 8b 50 30 mov 0x30(%rax),%rdx - 40fcae: 48 89 10 mov %rdx,(%rax) - 40fcb1: 48 89 50 10 mov %rdx,0x10(%rax) - 40fcb5: 48 89 50 08 mov %rdx,0x8(%rax) - 40fcb9: 48 89 50 28 mov %rdx,0x28(%rax) - 40fcbd: 48 89 50 20 mov %rdx,0x20(%rax) - 40fcc1: 48 89 50 18 mov %rdx,0x18(%rax) - 40fcc5: 0f 1f 00 nopl (%rax) - 40fcc8: 48 8b 53 40 mov 0x40(%rbx),%rdx - 40fccc: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 40fcd3: 4c 89 f6 mov %r14,%rsi - 40fcd6: 48 89 df mov %rbx,%rdi - 40fcd9: 4c 29 f2 sub %r14,%rdx - 40fcdc: ff 50 70 callq *0x70(%rax) - 40fcdf: 48 83 f8 00 cmp $0x0,%rax - 40fce3: 0f 8e f7 00 00 00 jle 40fde0 <_IO_wfile_underflow+0x280> - 40fce9: 48 8b 8b 90 00 00 00 mov 0x90(%rbx),%rcx - 40fcf0: 48 01 43 10 add %rax,0x10(%rbx) - 40fcf4: 48 83 f9 ff cmp $0xffffffffffffffff,%rcx - 40fcf8: 74 0a je 40fd04 <_IO_wfile_underflow+0x1a4> - 40fcfa: 48 01 c1 add %rax,%rcx - 40fcfd: 48 89 8b 90 00 00 00 mov %rcx,0x90(%rbx) - 40fd04: 48 8b 93 a0 00 00 00 mov 0xa0(%rbx),%rdx - 40fd0b: 48 85 ed test %rbp,%rbp - 40fd0e: 48 8b 4a 58 mov 0x58(%rdx),%rcx - 40fd12: 48 89 4a 60 mov %rcx,0x60(%rdx) - 40fd16: 48 8b 7b 08 mov 0x8(%rbx),%rdi - 40fd1a: 48 8b 4b 10 mov 0x10(%rbx),%rcx - 40fd1e: 48 89 7b 18 mov %rdi,0x18(%rbx) - 40fd22: 0f 85 38 01 00 00 jne 40fe60 <_IO_wfile_underflow+0x300> - 40fd28: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 40fd2f: 48 8d 50 08 lea 0x8(%rax),%rdx - 40fd33: 48 8d 70 58 lea 0x58(%rax),%rsi - 40fd37: 52 push %rdx - 40fd38: ff 70 38 pushq 0x38(%rax) - 40fd3b: 48 89 fa mov %rdi,%rdx - 40fd3e: 4c 8b 48 08 mov 0x8(%rax),%r9 - 40fd42: 4c 89 e7 mov %r12,%rdi - 40fd45: 4c 8d 44 24 18 lea 0x18(%rsp),%r8 - 40fd4a: 41 ff 54 24 18 callq *0x18(%r12) - 40fd4f: 5a pop %rdx - 40fd50: 59 pop %rcx - 40fd51: 48 8b 4c 24 08 mov 0x8(%rsp),%rcx - 40fd56: 31 ed xor %ebp,%ebp - 40fd58: 48 89 ce mov %rcx,%rsi - 40fd5b: 48 8b 93 a0 00 00 00 mov 0xa0(%rbx),%rdx - 40fd62: 48 89 73 08 mov %rsi,0x8(%rbx) - 40fd66: 48 8b 7a 30 mov 0x30(%rdx),%rdi - 40fd6a: 48 39 7a 08 cmp %rdi,0x8(%rdx) - 40fd6e: 0f 85 74 02 00 00 jne 40ffe8 <_IO_wfile_underflow+0x488> - 40fd74: 83 f8 02 cmp $0x2,%eax - 40fd77: 0f 84 74 01 00 00 je 40fef1 <_IO_wfile_underflow+0x391> - 40fd7d: 83 f8 01 cmp $0x1,%eax - 40fd80: 0f 85 5e 03 00 00 jne 4100e4 <_IO_wfile_underflow+0x584> - 40fd86: 48 85 ed test %rbp,%rbp - 40fd89: 75 3d jne 40fdc8 <_IO_wfile_underflow+0x268> - 40fd8b: 4c 8b 73 18 mov 0x18(%rbx),%r14 - 40fd8f: 4c 39 f6 cmp %r14,%rsi - 40fd92: 0f 87 80 00 00 00 ja 40fe18 <_IO_wfile_underflow+0x2b8> - 40fd98: 48 8b 6b 10 mov 0x10(%rbx),%rbp - 40fd9c: 48 29 f5 sub %rsi,%rbp - 40fd9f: 48 83 fd 0f cmp $0xf,%rbp - 40fda3: 0f 87 48 01 00 00 ja 40fef1 <_IO_wfile_underflow+0x391> - 40fda9: 48 89 ea mov %rbp,%rdx - 40fdac: 4c 89 ef mov %r13,%rdi - 40fdaf: e8 6c c2 01 00 callq 42c020 - 40fdb4: 4c 89 73 10 mov %r14,0x10(%rbx) - 40fdb8: 4c 89 73 08 mov %r14,0x8(%rbx) - 40fdbc: e9 07 ff ff ff jmpq 40fcc8 <_IO_wfile_underflow+0x168> - 40fdc1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 40fdc8: 48 89 c8 mov %rcx,%rax - 40fdcb: 4c 29 e8 sub %r13,%rax - 40fdce: 75 78 jne 40fe48 <_IO_wfile_underflow+0x2e8> - 40fdd0: 48 83 fd 10 cmp $0x10,%rbp - 40fdd4: 0f 84 17 01 00 00 je 40fef1 <_IO_wfile_underflow+0x391> - 40fdda: 4c 8b 73 18 mov 0x18(%rbx),%r14 - 40fdde: eb d4 jmp 40fdb4 <_IO_wfile_underflow+0x254> - 40fde0: 0f 85 da 01 00 00 jne 40ffc0 <_IO_wfile_underflow+0x460> - 40fde6: 48 85 ed test %rbp,%rbp - 40fde9: 0f 85 d1 01 00 00 jne 40ffc0 <_IO_wfile_underflow+0x460> - 40fdef: 8b 03 mov (%rbx),%eax - 40fdf1: 48 c7 83 90 00 00 00 movq $0xffffffffffffffff,0x90(%rbx) - 40fdf8: ff ff ff ff - 40fdfc: 83 c8 10 or $0x10,%eax - 40fdff: 89 03 mov %eax,(%rbx) - 40fe01: b8 ff ff ff ff mov $0xffffffff,%eax - 40fe06: 48 83 c4 28 add $0x28,%rsp - 40fe0a: 5b pop %rbx - 40fe0b: 5d pop %rbp - 40fe0c: 41 5c pop %r12 - 40fe0e: 41 5d pop %r13 - 40fe10: 41 5e pop %r14 - 40fe12: 41 5f pop %r15 - 40fe14: c3 retq - 40fe15: 0f 1f 00 nopl (%rax) - 40fe18: 4c 8b 7b 10 mov 0x10(%rbx),%r15 - 40fe1c: 4c 89 f7 mov %r14,%rdi - 40fe1f: 49 29 f7 sub %rsi,%r15 - 40fe22: 4c 89 fa mov %r15,%rdx - 40fe25: e8 d6 04 ff ff callq 400300 <__rela_iplt_end+0x38> - 40fe2a: 4c 8b 73 10 mov 0x10(%rbx),%r14 - 40fe2e: 48 8b 43 18 mov 0x18(%rbx),%rax - 40fe32: 4d 29 fe sub %r15,%r14 - 40fe35: 48 89 43 08 mov %rax,0x8(%rbx) - 40fe39: 4c 89 73 10 mov %r14,0x10(%rbx) - 40fe3d: e9 86 fe ff ff jmpq 40fcc8 <_IO_wfile_underflow+0x168> - 40fe42: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 40fe48: 48 29 c5 sub %rax,%rbp - 40fe4b: 48 89 ce mov %rcx,%rsi - 40fe4e: 4c 89 ef mov %r13,%rdi - 40fe51: 48 89 ea mov %rbp,%rdx - 40fe54: e8 a7 04 ff ff callq 400300 <__rela_iplt_end+0x38> - 40fe59: e9 72 ff ff ff jmpq 40fdd0 <_IO_wfile_underflow+0x270> - 40fe5e: 66 90 xchg %ax,%ax - 40fe60: 41 b8 10 00 00 00 mov $0x10,%r8d - 40fe66: 4d 8d 74 2d 00 lea 0x0(%r13,%rbp,1),%r14 - 40fe6b: 48 89 fe mov %rdi,%rsi - 40fe6e: 49 29 e8 sub %rbp,%r8 - 40fe71: 49 39 c0 cmp %rax,%r8 - 40fe74: 4c 89 f7 mov %r14,%rdi - 40fe77: 49 0f 46 c0 cmovbe %r8,%rax - 40fe7b: 48 89 c2 mov %rax,%rdx - 40fe7e: 49 89 c7 mov %rax,%r15 - 40fe81: e8 3a 67 01 00 callq 4265c0 <__mempcpy> - 40fe86: 48 8b 93 a0 00 00 00 mov 0xa0(%rbx),%rdx - 40fe8d: 4c 01 fd add %r15,%rbp - 40fe90: 4c 89 e7 mov %r12,%rdi - 40fe93: 48 8d 4a 08 lea 0x8(%rdx),%rcx - 40fe97: 48 8d 72 58 lea 0x58(%rdx),%rsi - 40fe9b: 51 push %rcx - 40fe9c: ff 72 38 pushq 0x38(%rdx) - 40fe9f: 48 89 c1 mov %rax,%rcx - 40fea2: 4c 8b 4a 08 mov 0x8(%rdx),%r9 - 40fea6: 4c 89 ea mov %r13,%rdx - 40fea9: 4c 8d 44 24 18 lea 0x18(%rsp),%r8 - 40feae: 41 ff 54 24 18 callq *0x18(%r12) - 40feb3: 48 85 ed test %rbp,%rbp - 40feb6: 5e pop %rsi - 40feb7: 5f pop %rdi - 40feb8: 0f 84 93 fe ff ff je 40fd51 <_IO_wfile_underflow+0x1f1> - 40febe: 48 8b 4c 24 08 mov 0x8(%rsp),%rcx - 40fec3: be 00 00 00 00 mov $0x0,%esi - 40fec8: 48 89 ca mov %rcx,%rdx - 40fecb: 4c 29 f2 sub %r14,%rdx - 40fece: 48 0f 48 d6 cmovs %rsi,%rdx - 40fed2: 48 89 d6 mov %rdx,%rsi - 40fed5: 48 03 73 08 add 0x8(%rbx),%rsi - 40fed9: e9 7d fe ff ff jmpq 40fd5b <_IO_wfile_underflow+0x1fb> - 40fede: 66 90 xchg %ax,%ax - 40fee0: 8b 02 mov (%rdx),%eax - 40fee2: c3 retq - 40fee3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 40fee8: 83 f8 02 cmp $0x2,%eax - 40feeb: 0f 85 88 01 00 00 jne 410079 <_IO_wfile_underflow+0x519> - 40fef1: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 40fef8: 64 c7 00 54 00 00 00 movl $0x54,%fs:(%rax) - 40feff: 83 0b 20 orl $0x20,(%rbx) - 40ff02: 48 83 c4 28 add $0x28,%rsp - 40ff06: 5b pop %rbx - 40ff07: b8 ff ff ff ff mov $0xffffffff,%eax - 40ff0c: 5d pop %rbp - 40ff0d: 41 5c pop %r12 - 40ff0f: 41 5d pop %r13 - 40ff11: 41 5e pop %r14 - 40ff13: 41 5f pop %r15 - 40ff15: c3 retq - 40ff16: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 40ff1d: 00 00 00 - 40ff20: 48 89 54 24 10 mov %rdx,0x10(%rsp) - 40ff25: 48 8b 50 58 mov 0x58(%rax),%rdx - 40ff29: 48 89 50 60 mov %rdx,0x60(%rax) - 40ff2d: 48 8b 87 a0 00 00 00 mov 0xa0(%rdi),%rax - 40ff34: 48 8b 4f 10 mov 0x10(%rdi),%rcx - 40ff38: 48 8b 57 08 mov 0x8(%rdi),%rdx - 40ff3c: 4c 8b 48 30 mov 0x30(%rax),%r9 - 40ff40: 48 8d 78 08 lea 0x8(%rax),%rdi - 40ff44: 48 8d 70 58 lea 0x58(%rax),%rsi - 40ff48: 4c 89 08 mov %r9,(%rax) - 40ff4b: 4c 89 48 10 mov %r9,0x10(%rax) - 40ff4f: 57 push %rdi - 40ff50: ff 70 38 pushq 0x38(%rax) - 40ff53: 4c 89 e7 mov %r12,%rdi - 40ff56: 4c 8d 44 24 20 lea 0x20(%rsp),%r8 - 40ff5b: 41 ff 54 24 18 callq *0x18(%r12) - 40ff60: 48 8b 53 08 mov 0x8(%rbx),%rdx - 40ff64: 48 8b 74 24 20 mov 0x20(%rsp),%rsi - 40ff69: 48 89 53 18 mov %rdx,0x18(%rbx) - 40ff6d: 48 8b 93 a0 00 00 00 mov 0xa0(%rbx),%rdx - 40ff74: 48 89 73 08 mov %rsi,0x8(%rbx) - 40ff78: 41 58 pop %r8 - 40ff7a: 48 8b 0a mov (%rdx),%rcx - 40ff7d: 48 3b 4a 08 cmp 0x8(%rdx),%rcx - 40ff81: 41 59 pop %r9 - 40ff83: 0f 83 5f ff ff ff jae 40fee8 <_IO_wfile_underflow+0x388> - 40ff89: 8b 01 mov (%rcx),%eax - 40ff8b: e9 76 fe ff ff jmpq 40fe06 <_IO_wfile_underflow+0x2a6> - 40ff90: 81 e2 88 02 00 00 and $0x288,%edx - 40ff96: 81 fa 80 02 00 00 cmp $0x280,%edx - 40ff9c: 0f 85 ee fc ff ff jne 40fc90 <_IO_wfile_underflow+0x130> - 40ffa2: 48 89 ef mov %rbp,%rdi - 40ffa5: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax - 40ffac: be ff ff ff ff mov $0xffffffff,%esi - 40ffb1: ff 50 18 callq *0x18(%rax) - 40ffb4: e9 bd fc ff ff jmpq 40fc76 <_IO_wfile_underflow+0x116> - 40ffb9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 40ffc0: 83 0b 20 orl $0x20,(%rbx) - 40ffc3: 48 85 ed test %rbp,%rbp - 40ffc6: 0f 84 84 01 00 00 je 410150 <_IO_wfile_underflow+0x5f0> - 40ffcc: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 40ffd3: 64 c7 00 54 00 00 00 movl $0x54,%fs:(%rax) - 40ffda: b8 ff ff ff ff mov $0xffffffff,%eax - 40ffdf: e9 22 fe ff ff jmpq 40fe06 <_IO_wfile_underflow+0x2a6> - 40ffe4: 0f 1f 40 00 nopl 0x0(%rax) - 40ffe8: 48 8b 02 mov (%rdx),%rax - 40ffeb: 8b 00 mov (%rax),%eax - 40ffed: 48 83 c4 28 add $0x28,%rsp - 40fff1: 5b pop %rbx - 40fff2: 5d pop %rbp - 40fff3: 41 5c pop %r12 - 40fff5: 41 5d pop %r13 - 40fff7: 41 5e pop %r14 - 40fff9: 41 5f pop %r15 - 40fffb: c3 retq - 40fffc: 0f 1f 40 00 nopl 0x0(%rax) - 410000: 83 c8 20 or $0x20,%eax - 410003: 89 07 mov %eax,(%rdi) - 410005: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 41000c: 64 c7 00 09 00 00 00 movl $0x9,%fs:(%rax) - 410013: b8 ff ff ff ff mov $0xffffffff,%eax - 410018: c3 retq - 410019: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 410020: 48 8b 78 40 mov 0x40(%rax),%rdi - 410024: 48 85 ff test %rdi,%rdi - 410027: 74 0b je 410034 <_IO_wfile_underflow+0x4d4> - 410029: e8 82 dd 00 00 callq 41ddb0 <__cfree> - 41002e: 81 23 ff fe ff ff andl $0xfffffeff,(%rbx) - 410034: 48 89 df mov %rbx,%rdi - 410037: e8 64 46 05 00 callq 4646a0 <_IO_wdoallocbuf> - 41003c: e9 9a fb ff ff jmpq 40fbdb <_IO_wfile_underflow+0x7b> - 410041: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 410048: 48 8b 7b 48 mov 0x48(%rbx),%rdi - 41004c: 48 85 ff test %rdi,%rdi - 41004f: 74 0b je 41005c <_IO_wfile_underflow+0x4fc> - 410051: e8 5a dd 00 00 callq 41ddb0 <__cfree> - 410056: 81 23 ff fe ff ff andl $0xfffffeff,(%rbx) - 41005c: 48 89 df mov %rbx,%rdi - 41005f: e8 9c 4d 00 00 callq 414e00 <_IO_doallocbuf> - 410064: 48 8b 43 38 mov 0x38(%rbx),%rax - 410068: 48 89 43 10 mov %rax,0x10(%rbx) - 41006c: 48 89 43 08 mov %rax,0x8(%rbx) - 410070: 48 89 43 18 mov %rax,0x18(%rbx) - 410074: e9 44 fb ff ff jmpq 40fbbd <_IO_wfile_underflow+0x5d> - 410079: 48 8b 53 10 mov 0x10(%rbx),%rdx - 41007d: 48 8b 7b 38 mov 0x38(%rbx),%rdi - 410081: 48 29 f2 sub %rsi,%rdx - 410084: e8 77 02 ff ff callq 400300 <__rela_iplt_end+0x38> - 410089: 48 8b 43 38 mov 0x38(%rbx),%rax - 41008d: 48 89 c2 mov %rax,%rdx - 410090: 48 2b 53 08 sub 0x8(%rbx),%rdx - 410094: 48 89 43 18 mov %rax,0x18(%rbx) - 410098: 48 01 53 10 add %rdx,0x10(%rbx) - 41009c: 48 89 43 08 mov %rax,0x8(%rbx) - 4100a0: e9 0f fb ff ff jmpq 40fbb4 <_IO_wfile_underflow+0x54> - 4100a5: 48 c7 42 08 00 00 00 movq $0x0,0x8(%rdx) - 4100ac: 00 - 4100ad: 83 3d 08 d1 2b 00 00 cmpl $0x0,0x2bd108(%rip) # 6cd1bc <__libc_multiple_threads> - 4100b4: 74 07 je 4100bd <_IO_wfile_underflow+0x55d> - 4100b6: f0 ff 0a lock decl (%rdx) - 4100b9: 75 06 jne 4100c1 <_IO_wfile_underflow+0x561> - 4100bb: eb 1a jmp 4100d7 <_IO_wfile_underflow+0x577> - 4100bd: ff 0a decl (%rdx) - 4100bf: 74 16 je 4100d7 <_IO_wfile_underflow+0x577> - 4100c1: 48 8d 3a lea (%rdx),%rdi - 4100c4: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 4100cb: e8 30 25 03 00 callq 442600 <__lll_unlock_wake_private> - 4100d0: 48 81 c4 80 00 00 00 add $0x80,%rsp - 4100d7: e9 b4 fb ff ff jmpq 40fc90 <_IO_wfile_underflow+0x130> - 4100dc: 48 89 ef mov %rbp,%rdi - 4100df: e9 7b fb ff ff jmpq 40fc5f <_IO_wfile_underflow+0xff> - 4100e4: b9 80 19 4a 00 mov $0x4a1980,%ecx - 4100e9: ba 35 01 00 00 mov $0x135,%edx - 4100ee: be 53 19 4a 00 mov $0x4a1953,%esi - 4100f3: bf 5e 19 4a 00 mov $0x4a195e,%edi - 4100f8: e8 43 16 ff ff callq 401740 <__assert_fail> - 4100fd: f7 45 00 00 80 00 00 testl $0x8000,0x0(%rbp) - 410104: 48 89 c6 mov %rax,%rsi - 410107: 75 3f jne 410148 <_IO_wfile_underflow+0x5e8> - 410109: 48 8b 95 88 00 00 00 mov 0x88(%rbp),%rdx - 410110: 83 6a 04 01 subl $0x1,0x4(%rdx) - 410114: 75 32 jne 410148 <_IO_wfile_underflow+0x5e8> - 410116: 48 c7 42 08 00 00 00 movq $0x0,0x8(%rdx) - 41011d: 00 - 41011e: 83 3d 97 d0 2b 00 00 cmpl $0x0,0x2bd097(%rip) # 6cd1bc <__libc_multiple_threads> - 410125: 74 07 je 41012e <_IO_wfile_underflow+0x5ce> - 410127: f0 ff 0a lock decl (%rdx) - 41012a: 75 06 jne 410132 <_IO_wfile_underflow+0x5d2> - 41012c: eb 1a jmp 410148 <_IO_wfile_underflow+0x5e8> - 41012e: ff 0a decl (%rdx) - 410130: 74 16 je 410148 <_IO_wfile_underflow+0x5e8> - 410132: 48 8d 3a lea (%rdx),%rdi - 410135: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41013c: e8 bf 24 03 00 callq 442600 <__lll_unlock_wake_private> - 410141: 48 81 c4 80 00 00 00 add $0x80,%rsp - 410148: 48 89 f7 mov %rsi,%rdi - 41014b: e8 20 c4 08 00 callq 49c570 <_Unwind_Resume> - 410150: 83 c8 ff or $0xffffffff,%eax - 410153: e9 ae fc ff ff jmpq 40fe06 <_IO_wfile_underflow+0x2a6> - 410158: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 41015f: 00 - -0000000000410160 <_IO_wfile_seekoff>: - 410160: 41 57 push %r15 - 410162: 41 56 push %r14 - 410164: 49 89 ff mov %rdi,%r15 - 410167: 41 55 push %r13 - 410169: 41 54 push %r12 - 41016b: 55 push %rbp - 41016c: 53 push %rbx - 41016d: 48 81 ec b8 00 00 00 sub $0xb8,%rsp - 410174: 85 c9 test %ecx,%ecx - 410176: 0f 84 a4 02 00 00 je 410420 <_IO_wfile_seekoff+0x2c0> - 41017c: 48 8b 87 a0 00 00 00 mov 0xa0(%rdi),%rax - 410183: 48 89 f3 mov %rsi,%rbx - 410186: 89 d5 mov %edx,%ebp - 410188: 48 8b 70 08 mov 0x8(%rax),%rsi - 41018c: 48 39 70 10 cmp %rsi,0x10(%rax) - 410190: 74 3e je 4101d0 <_IO_wfile_seekoff+0x70> - 410192: 48 8b 48 20 mov 0x20(%rax),%rcx - 410196: 48 8b 50 18 mov 0x18(%rax),%rdx - 41019a: 45 31 e4 xor %r12d,%r12d - 41019d: 48 39 d1 cmp %rdx,%rcx - 4101a0: 76 46 jbe 4101e8 <_IO_wfile_seekoff+0x88> - 4101a2: 4c 89 ff mov %r15,%rdi - 4101a5: e8 f6 45 05 00 callq 4647a0 <_IO_switch_to_wget_mode> - 4101aa: 85 c0 test %eax,%eax - 4101ac: ba ff ff ff ff mov $0xffffffff,%edx - 4101b1: 0f 84 41 03 00 00 je 4104f8 <_IO_wfile_seekoff+0x398> - 4101b7: 48 81 c4 b8 00 00 00 add $0xb8,%rsp - 4101be: 48 89 d0 mov %rdx,%rax - 4101c1: 5b pop %rbx - 4101c2: 5d pop %rbp - 4101c3: 41 5c pop %r12 - 4101c5: 41 5d pop %r13 - 4101c7: 41 5e pop %r14 - 4101c9: 41 5f pop %r15 - 4101cb: c3 retq - 4101cc: 0f 1f 40 00 nopl 0x0(%rax) - 4101d0: 48 8b 50 18 mov 0x18(%rax),%rdx - 4101d4: 48 8b 48 20 mov 0x20(%rax),%rcx - 4101d8: 48 39 ca cmp %rcx,%rdx - 4101db: 75 bd jne 41019a <_IO_wfile_seekoff+0x3a> - 4101dd: 41 bc 01 00 00 00 mov $0x1,%r12d - 4101e3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4101e8: 41 f7 07 00 08 00 00 testl $0x800,(%r15) - 4101ef: 75 b1 jne 4101a2 <_IO_wfile_seekoff+0x42> - 4101f1: 48 83 78 30 00 cmpq $0x0,0x30(%rax) - 4101f6: 0f 84 b4 03 00 00 je 4105b0 <_IO_wfile_seekoff+0x450> - 4101fc: 83 fd 01 cmp $0x1,%ebp - 4101ff: 0f 84 bb 01 00 00 je 4103c0 <_IO_wfile_seekoff+0x260> - 410205: 83 fd 02 cmp $0x2,%ebp - 410208: 0f 85 c2 00 00 00 jne 4102d0 <_IO_wfile_seekoff+0x170> - 41020e: 49 8b 87 d8 00 00 00 mov 0xd8(%r15),%rax - 410215: 48 8d 74 24 20 lea 0x20(%rsp),%rsi - 41021a: 4c 89 ff mov %r15,%rdi - 41021d: ff 90 90 00 00 00 callq *0x90(%rax) - 410223: 85 c0 test %eax,%eax - 410225: 0f 84 85 00 00 00 je 4102b0 <_IO_wfile_seekoff+0x150> - 41022b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 410230: 4c 89 ff mov %r15,%rdi - 410233: e8 68 61 00 00 callq 4163a0 <_IO_unsave_markers> - 410238: 49 8b 87 d8 00 00 00 mov 0xd8(%r15),%rax - 41023f: 89 ea mov %ebp,%edx - 410241: 48 89 de mov %rbx,%rsi - 410244: 4c 89 ff mov %r15,%rdi - 410247: ff 90 80 00 00 00 callq *0x80(%rax) - 41024d: 48 c7 c2 ff ff ff ff mov $0xffffffffffffffff,%rdx - 410254: 48 39 d0 cmp %rdx,%rax - 410257: 0f 84 5a ff ff ff je 4101b7 <_IO_wfile_seekoff+0x57> - 41025d: 49 8b 57 38 mov 0x38(%r15),%rdx - 410261: 41 83 27 ef andl $0xffffffef,(%r15) - 410265: 49 89 87 90 00 00 00 mov %rax,0x90(%r15) - 41026c: 49 89 57 18 mov %rdx,0x18(%r15) - 410270: 49 89 57 08 mov %rdx,0x8(%r15) - 410274: 49 89 57 10 mov %rdx,0x10(%r15) - 410278: 49 89 57 28 mov %rdx,0x28(%r15) - 41027c: 49 89 57 20 mov %rdx,0x20(%r15) - 410280: 49 89 57 30 mov %rdx,0x30(%r15) - 410284: 49 8b 97 a0 00 00 00 mov 0xa0(%r15),%rdx - 41028b: 48 8b 4a 30 mov 0x30(%rdx),%rcx - 41028f: 48 89 4a 10 mov %rcx,0x10(%rdx) - 410293: 48 89 0a mov %rcx,(%rdx) - 410296: 48 89 4a 08 mov %rcx,0x8(%rdx) - 41029a: 48 89 4a 20 mov %rcx,0x20(%rdx) - 41029e: 48 89 4a 18 mov %rcx,0x18(%rdx) - 4102a2: 48 89 4a 28 mov %rcx,0x28(%rdx) - 4102a6: 48 89 c2 mov %rax,%rdx - 4102a9: e9 09 ff ff ff jmpq 4101b7 <_IO_wfile_seekoff+0x57> - 4102ae: 66 90 xchg %ax,%ax - 4102b0: 8b 44 24 38 mov 0x38(%rsp),%eax - 4102b4: 25 00 f0 00 00 and $0xf000,%eax - 4102b9: 3d 00 80 00 00 cmp $0x8000,%eax - 4102be: 0f 85 6c ff ff ff jne 410230 <_IO_wfile_seekoff+0xd0> - 4102c4: 48 03 5c 24 50 add 0x50(%rsp),%rbx - 4102c9: 31 ed xor %ebp,%ebp - 4102cb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4102d0: 49 8b 87 90 00 00 00 mov 0x90(%r15),%rax - 4102d7: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 4102db: 0f 84 27 02 00 00 je 410508 <_IO_wfile_seekoff+0x3a8> - 4102e1: 49 83 7f 18 00 cmpq $0x0,0x18(%r15) - 4102e6: 41 8b 17 mov (%r15),%edx - 4102e9: 74 25 je 410310 <_IO_wfile_seekoff+0x1b0> - 4102eb: f6 c6 01 test $0x1,%dh - 4102ee: 75 20 jne 410310 <_IO_wfile_seekoff+0x1b0> - 4102f0: 49 8b 4f 38 mov 0x38(%r15),%rcx - 4102f4: 48 89 ce mov %rcx,%rsi - 4102f7: 49 2b 77 10 sub 0x10(%r15),%rsi - 4102fb: 48 01 c6 add %rax,%rsi - 4102fe: 48 39 de cmp %rbx,%rsi - 410301: 7f 0d jg 410310 <_IO_wfile_seekoff+0x1b0> - 410303: 48 39 c3 cmp %rax,%rbx - 410306: 0f 8c ac 03 00 00 jl 4106b8 <_IO_wfile_seekoff+0x558> - 41030c: 0f 1f 40 00 nopl 0x0(%rax) - 410310: 83 e2 04 and $0x4,%edx - 410313: 0f 85 17 ff ff ff jne 410230 <_IO_wfile_seekoff+0xd0> - 410319: 49 8b 57 38 mov 0x38(%r15),%rdx - 41031d: 49 8b 47 40 mov 0x40(%r15),%rax - 410321: 49 89 dd mov %rbx,%r13 - 410324: 48 89 d6 mov %rdx,%rsi - 410327: 48 29 c6 sub %rax,%rsi - 41032a: 48 29 d0 sub %rdx,%rax - 41032d: ba 00 00 00 00 mov $0x0,%edx - 410332: 48 21 de and %rbx,%rsi - 410335: 49 29 f5 sub %rsi,%r13 - 410338: 49 39 c5 cmp %rax,%r13 - 41033b: 49 8b 87 d8 00 00 00 mov 0xd8(%r15),%rax - 410342: 0f 8f d8 01 00 00 jg 410520 <_IO_wfile_seekoff+0x3c0> - 410348: 4c 89 ff mov %r15,%rdi - 41034b: ff 90 80 00 00 00 callq *0x80(%rax) - 410351: 48 85 c0 test %rax,%rax - 410354: 49 89 c6 mov %rax,%r14 - 410357: 0f 88 8b 01 00 00 js 4104e8 <_IO_wfile_seekoff+0x388> - 41035d: 4d 85 ed test %r13,%r13 - 410360: 0f 84 ce 01 00 00 je 410534 <_IO_wfile_seekoff+0x3d4> - 410366: 49 8b 87 d8 00 00 00 mov 0xd8(%r15),%rax - 41036d: 45 85 e4 test %r12d,%r12d - 410370: 49 8b 77 38 mov 0x38(%r15),%rsi - 410374: 4c 89 ea mov %r13,%rdx - 410377: 48 8b 40 70 mov 0x70(%rax),%rax - 41037b: 75 07 jne 410384 <_IO_wfile_seekoff+0x224> - 41037d: 49 8b 57 40 mov 0x40(%r15),%rdx - 410381: 48 29 f2 sub %rsi,%rdx - 410384: 4c 89 ff mov %r15,%rdi - 410387: ff d0 callq *%rax - 410389: 49 39 c5 cmp %rax,%r13 - 41038c: 49 89 c4 mov %rax,%r12 - 41038f: 48 89 c2 mov %rax,%rdx - 410392: 0f 8e a4 01 00 00 jle 41053c <_IO_wfile_seekoff+0x3dc> - 410398: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 41039c: 4c 89 eb mov %r13,%rbx - 41039f: bd 01 00 00 00 mov $0x1,%ebp - 4103a4: 0f 84 86 fe ff ff je 410230 <_IO_wfile_seekoff+0xd0> - 4103aa: 48 29 c3 sub %rax,%rbx - 4103ad: bd 01 00 00 00 mov $0x1,%ebp - 4103b2: e9 79 fe ff ff jmpq 410230 <_IO_wfile_seekoff+0xd0> - 4103b7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 4103be: 00 00 - 4103c0: 4d 8b af 98 00 00 00 mov 0x98(%r15),%r13 - 4103c7: 4c 89 ef mov %r13,%rdi - 4103ca: 41 ff 55 20 callq *0x20(%r13) - 4103ce: 85 c0 test %eax,%eax - 4103d0: 0f 8e 6a 03 00 00 jle 410740 <_IO_wfile_seekoff+0x5e0> - 4103d6: 49 8b 8f a0 00 00 00 mov 0xa0(%r15),%rcx - 4103dd: 48 98 cltq - 4103df: 48 8b 51 08 mov 0x8(%rcx),%rdx - 4103e3: 48 2b 11 sub (%rcx),%rdx - 4103e6: 48 c1 fa 02 sar $0x2,%rdx - 4103ea: 48 0f af c2 imul %rdx,%rax - 4103ee: 48 29 c3 sub %rax,%rbx - 4103f1: 49 8b 47 10 mov 0x10(%r15),%rax - 4103f5: 49 2b 47 08 sub 0x8(%r15),%rax - 4103f9: 48 29 c3 sub %rax,%rbx - 4103fc: 49 8b 87 90 00 00 00 mov 0x90(%r15),%rax - 410403: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 410407: 0f 84 23 fe ff ff je 410230 <_IO_wfile_seekoff+0xd0> - 41040d: 48 01 c3 add %rax,%rbx - 410410: 31 ed xor %ebp,%ebp - 410412: e9 ca fe ff ff jmpq 4102e1 <_IO_wfile_seekoff+0x181> - 410417: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 41041e: 00 00 - 410420: 48 8b 87 a0 00 00 00 mov 0xa0(%rdi),%rax - 410427: 48 83 78 30 00 cmpq $0x0,0x30(%rax) - 41042c: 0f 84 06 03 00 00 je 410738 <_IO_wfile_seekoff+0x5d8> - 410432: 8b 17 mov (%rdi),%edx - 410434: 4c 8b 60 20 mov 0x20(%rax),%r12 - 410438: 48 8b 68 18 mov 0x18(%rax),%rbp - 41043c: 41 89 d5 mov %edx,%r13d - 41043f: 41 81 e5 00 10 00 00 and $0x1000,%r13d - 410446: 49 39 ec cmp %rbp,%r12 - 410449: 76 09 jbe 410454 <_IO_wfile_seekoff+0x2f4> - 41044b: 45 85 ed test %r13d,%r13d - 41044e: 0f 85 1c 02 00 00 jne 410670 <_IO_wfile_seekoff+0x510> - 410454: 80 e6 01 and $0x1,%dh - 410457: 0f 84 b3 01 00 00 je 410610 <_IO_wfile_seekoff+0x4b0> - 41045d: 48 8b 78 08 mov 0x8(%rax),%rdi - 410461: 48 39 38 cmp %rdi,(%rax) - 410464: 72 6e jb 4104d4 <_IO_wfile_seekoff+0x374> - 410466: 4c 8b 70 40 mov 0x40(%rax),%r14 - 41046a: 48 8b 40 50 mov 0x50(%rax),%rax - 41046e: 4c 89 74 24 08 mov %r14,0x8(%rsp) - 410473: 48 89 04 24 mov %rax,(%rsp) - 410477: 49 8b 9f 98 00 00 00 mov 0x98(%r15),%rbx - 41047e: 48 89 df mov %rbx,%rdi - 410481: ff 53 20 callq *0x20(%rbx) - 410484: 49 39 ec cmp %rbp,%r12 - 410487: 0f 87 a3 01 00 00 ja 410630 <_IO_wfile_seekoff+0x4d0> - 41048d: 85 c0 test %eax,%eax - 41048f: 0f 8e 3b 03 00 00 jle 4107d0 <_IO_wfile_seekoff+0x670> - 410495: 48 8b 14 24 mov (%rsp),%rdx - 410499: 48 98 cltq - 41049b: 4c 29 f2 sub %r14,%rdx - 41049e: 48 c1 fa 02 sar $0x2,%rdx - 4104a2: 48 0f af d0 imul %rax,%rdx - 4104a6: 49 8b 47 10 mov 0x10(%r15),%rax - 4104aa: 49 2b 47 08 sub 0x8(%r15),%rax - 4104ae: 48 f7 da neg %rdx - 4104b1: 48 89 d3 mov %rdx,%rbx - 4104b4: 48 29 c3 sub %rax,%rbx - 4104b7: 49 8b 87 90 00 00 00 mov 0x90(%r15),%rax - 4104be: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 4104c2: 0f 84 e0 02 00 00 je 4107a8 <_IO_wfile_seekoff+0x648> - 4104c8: 48 01 c3 add %rax,%rbx - 4104cb: 48 89 da mov %rbx,%rdx - 4104ce: 0f 89 e3 fc ff ff jns 4101b7 <_IO_wfile_seekoff+0x57> - 4104d4: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 4104db: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) - 4104e2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4104e8: 48 c7 c2 ff ff ff ff mov $0xffffffffffffffff,%rdx - 4104ef: e9 c3 fc ff ff jmpq 4101b7 <_IO_wfile_seekoff+0x57> - 4104f4: 0f 1f 40 00 nopl 0x0(%rax) - 4104f8: 49 8b 87 a0 00 00 00 mov 0xa0(%r15),%rax - 4104ff: e9 ed fc ff ff jmpq 4101f1 <_IO_wfile_seekoff+0x91> - 410504: 0f 1f 40 00 nopl 0x0(%rax) - 410508: 41 8b 17 mov (%r15),%edx - 41050b: 83 e2 04 and $0x4,%edx - 41050e: 0f 85 1c fd ff ff jne 410230 <_IO_wfile_seekoff+0xd0> - 410514: e9 00 fe ff ff jmpq 410319 <_IO_wfile_seekoff+0x1b9> - 410519: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 410520: 48 89 de mov %rbx,%rsi - 410523: 4c 89 ff mov %r15,%rdi - 410526: ff 90 80 00 00 00 callq *0x80(%rax) - 41052c: 48 85 c0 test %rax,%rax - 41052f: 49 89 c6 mov %rax,%r14 - 410532: 78 b4 js 4104e8 <_IO_wfile_seekoff+0x388> - 410534: 31 d2 xor %edx,%edx - 410536: 45 31 ed xor %r13d,%r13d - 410539: 45 31 e4 xor %r12d,%r12d - 41053c: 49 8b 47 38 mov 0x38(%r15),%rax - 410540: be 01 00 00 00 mov $0x1,%esi - 410545: 4c 89 ff mov %r15,%rdi - 410548: 49 89 47 18 mov %rax,0x18(%r15) - 41054c: 49 89 47 28 mov %rax,0x28(%r15) - 410550: 48 01 c2 add %rax,%rdx - 410553: 49 89 47 20 mov %rax,0x20(%r15) - 410557: 49 89 47 30 mov %rax,0x30(%r15) - 41055b: 49 01 c5 add %rax,%r13 - 41055e: 49 8b 87 a0 00 00 00 mov 0xa0(%r15),%rax - 410565: 49 89 57 10 mov %rdx,0x10(%r15) - 410569: 4d 89 6f 08 mov %r13,0x8(%r15) - 41056d: 48 8b 50 30 mov 0x30(%rax),%rdx - 410571: 48 89 50 10 mov %rdx,0x10(%rax) - 410575: 48 89 10 mov %rdx,(%rax) - 410578: 48 89 50 08 mov %rdx,0x8(%rax) - 41057c: 48 89 50 20 mov %rdx,0x20(%rax) - 410580: 48 89 50 18 mov %rdx,0x18(%rax) - 410584: 48 89 50 28 mov %rdx,0x28(%rax) - 410588: e8 03 f5 ff ff callq 40fa90 - 41058d: 85 c0 test %eax,%eax - 41058f: 0f 85 9b fc ff ff jne 410230 <_IO_wfile_seekoff+0xd0> - 410595: 4d 01 e6 add %r12,%r14 - 410598: 41 83 27 ef andl $0xffffffef,(%r15) - 41059c: 48 89 da mov %rbx,%rdx - 41059f: 4d 89 b7 90 00 00 00 mov %r14,0x90(%r15) - 4105a6: e9 0c fc ff ff jmpq 4101b7 <_IO_wfile_seekoff+0x57> - 4105ab: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4105b0: 48 8b 78 10 mov 0x10(%rax),%rdi - 4105b4: 48 85 ff test %rdi,%rdi - 4105b7: 74 0c je 4105c5 <_IO_wfile_seekoff+0x465> - 4105b9: e8 f2 d7 00 00 callq 41ddb0 <__cfree> - 4105be: 41 81 27 ff fe ff ff andl $0xfffffeff,(%r15) - 4105c5: 4c 89 ff mov %r15,%rdi - 4105c8: e8 33 48 00 00 callq 414e00 <_IO_doallocbuf> - 4105cd: 49 8b 47 38 mov 0x38(%r15),%rax - 4105d1: 49 89 47 28 mov %rax,0x28(%r15) - 4105d5: 49 89 47 20 mov %rax,0x20(%r15) - 4105d9: 49 89 47 30 mov %rax,0x30(%r15) - 4105dd: 49 89 47 18 mov %rax,0x18(%r15) - 4105e1: 49 89 47 08 mov %rax,0x8(%r15) - 4105e5: 49 89 47 10 mov %rax,0x10(%r15) - 4105e9: 49 8b 87 a0 00 00 00 mov 0xa0(%r15),%rax - 4105f0: 48 8b 50 30 mov 0x30(%rax),%rdx - 4105f4: 48 89 50 20 mov %rdx,0x20(%rax) - 4105f8: 48 89 50 18 mov %rdx,0x18(%rax) - 4105fc: 48 89 50 28 mov %rdx,0x28(%rax) - 410600: 48 89 50 10 mov %rdx,0x10(%rax) - 410604: 48 89 10 mov %rdx,(%rax) - 410607: 48 89 50 08 mov %rdx,0x8(%rax) - 41060b: e9 ec fb ff ff jmpq 4101fc <_IO_wfile_seekoff+0x9c> - 410610: 48 8b 78 10 mov 0x10(%rax),%rdi - 410614: 4c 8b 30 mov (%rax),%r14 - 410617: 48 8b 40 08 mov 0x8(%rax),%rax - 41061b: 48 89 7c 24 08 mov %rdi,0x8(%rsp) - 410620: 48 89 04 24 mov %rax,(%rsp) - 410624: e9 4e fe ff ff jmpq 410477 <_IO_wfile_seekoff+0x317> - 410629: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 410630: 85 c0 test %eax,%eax - 410632: 0f 8e e0 01 00 00 jle 410818 <_IO_wfile_seekoff+0x6b8> - 410638: 49 8b 97 a0 00 00 00 mov 0xa0(%r15),%rdx - 41063f: 48 98 cltq - 410641: 48 8b 5a 20 mov 0x20(%rdx),%rbx - 410645: 48 2b 5a 18 sub 0x18(%rdx),%rbx - 410649: 48 c1 fb 02 sar $0x2,%rbx - 41064d: 48 0f af d8 imul %rax,%rbx - 410651: 48 89 dd mov %rbx,%rbp - 410654: 45 85 ed test %r13d,%r13d - 410657: 49 8b 57 28 mov 0x28(%r15),%rdx - 41065b: 74 4b je 4106a8 <_IO_wfile_seekoff+0x548> - 41065d: 49 2b 57 20 sub 0x20(%r15),%rdx - 410661: 48 8d 1c 2a lea (%rdx,%rbp,1),%rbx - 410665: e9 4d fe ff ff jmpq 4104b7 <_IO_wfile_seekoff+0x357> - 41066a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 410670: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax - 410677: 31 f6 xor %esi,%esi - 410679: ba 02 00 00 00 mov $0x2,%edx - 41067e: ff 90 80 00 00 00 callq *0x80(%rax) - 410684: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 410688: 0f 84 5a fe ff ff je 4104e8 <_IO_wfile_seekoff+0x388> - 41068e: 49 89 87 90 00 00 00 mov %rax,0x90(%r15) - 410695: 41 8b 17 mov (%r15),%edx - 410698: 49 8b 87 a0 00 00 00 mov 0xa0(%r15),%rax - 41069f: e9 b0 fd ff ff jmpq 410454 <_IO_wfile_seekoff+0x2f4> - 4106a4: 0f 1f 40 00 nopl 0x0(%rax) - 4106a8: 49 2b 57 10 sub 0x10(%r15),%rdx - 4106ac: 48 8d 1c 2a lea (%rdx,%rbp,1),%rbx - 4106b0: e9 02 fe ff ff jmpq 4104b7 <_IO_wfile_seekoff+0x357> - 4106b5: 0f 1f 00 nopl (%rax) - 4106b8: 48 89 d8 mov %rbx,%rax - 4106bb: 49 89 4f 18 mov %rcx,0x18(%r15) - 4106bf: 49 89 4f 28 mov %rcx,0x28(%r15) - 4106c3: 48 29 f0 sub %rsi,%rax - 4106c6: 49 89 4f 20 mov %rcx,0x20(%r15) - 4106ca: 49 89 4f 30 mov %rcx,0x30(%r15) - 4106ce: 48 01 c8 add %rcx,%rax - 4106d1: 31 f6 xor %esi,%esi - 4106d3: 4c 89 ff mov %r15,%rdi - 4106d6: 49 89 47 08 mov %rax,0x8(%r15) - 4106da: 49 8b 87 a0 00 00 00 mov 0xa0(%r15),%rax - 4106e1: 48 8b 50 30 mov 0x30(%rax),%rdx - 4106e5: 48 89 50 10 mov %rdx,0x10(%rax) - 4106e9: 48 89 10 mov %rdx,(%rax) - 4106ec: 48 89 50 08 mov %rdx,0x8(%rax) - 4106f0: 48 89 50 20 mov %rdx,0x20(%rax) - 4106f4: 48 89 50 18 mov %rdx,0x18(%rax) - 4106f8: 48 89 50 28 mov %rdx,0x28(%rax) - 4106fc: e8 8f f3 ff ff callq 40fa90 - 410701: 85 c0 test %eax,%eax - 410703: 0f 85 27 fb ff ff jne 410230 <_IO_wfile_seekoff+0xd0> - 410709: 49 8b b7 90 00 00 00 mov 0x90(%r15),%rsi - 410710: 41 83 27 ef andl $0xffffffef,(%r15) - 410714: 48 85 f6 test %rsi,%rsi - 410717: 78 12 js 41072b <_IO_wfile_seekoff+0x5cb> - 410719: 49 8b 87 d8 00 00 00 mov 0xd8(%r15),%rax - 410720: 31 d2 xor %edx,%edx - 410722: 4c 89 ff mov %r15,%rdi - 410725: ff 90 80 00 00 00 callq *0x80(%rax) - 41072b: 48 89 da mov %rbx,%rdx - 41072e: e9 84 fa ff ff jmpq 4101b7 <_IO_wfile_seekoff+0x57> - 410733: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 410738: 31 db xor %ebx,%ebx - 41073a: e9 78 fd ff ff jmpq 4104b7 <_IO_wfile_seekoff+0x357> - 41073f: 90 nop - 410740: 49 8b 87 a0 00 00 00 mov 0xa0(%r15),%rax - 410747: 4c 89 ef mov %r13,%rdi - 41074a: 48 8b 50 60 mov 0x60(%rax),%rdx - 41074e: 4c 8b 00 mov (%rax),%r8 - 410751: 4c 2b 40 10 sub 0x10(%rax),%r8 - 410755: 48 89 50 58 mov %rdx,0x58(%rax) - 410759: 49 8b 87 a0 00 00 00 mov 0xa0(%r15),%rax - 410760: 49 8b 4f 10 mov 0x10(%r15),%rcx - 410764: 49 8b 57 18 mov 0x18(%r15),%rdx - 410768: 49 c1 f8 02 sar $0x2,%r8 - 41076c: 48 8d 70 58 lea 0x58(%rax),%rsi - 410770: 41 ff 55 30 callq *0x30(%r13) - 410774: 49 8b 4f 18 mov 0x18(%r15),%rcx - 410778: 48 63 d0 movslq %eax,%rdx - 41077b: 48 8d 04 11 lea (%rcx,%rdx,1),%rax - 41077f: 49 89 47 08 mov %rax,0x8(%r15) - 410783: 49 8b 87 a0 00 00 00 mov 0xa0(%r15),%rax - 41078a: 48 8b 30 mov (%rax),%rsi - 41078d: 48 89 70 08 mov %rsi,0x8(%rax) - 410791: 49 8b 47 10 mov 0x10(%r15),%rax - 410795: 48 29 c8 sub %rcx,%rax - 410798: 48 29 d0 sub %rdx,%rax - 41079b: 48 29 c3 sub %rax,%rbx - 41079e: e9 59 fc ff ff jmpq 4103fc <_IO_wfile_seekoff+0x29c> - 4107a3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4107a8: 49 8b 87 d8 00 00 00 mov 0xd8(%r15),%rax - 4107af: 31 f6 xor %esi,%esi - 4107b1: ba 01 00 00 00 mov $0x1,%edx - 4107b6: 4c 89 ff mov %r15,%rdi - 4107b9: ff 90 80 00 00 00 callq *0x80(%rax) - 4107bf: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 4107c3: 0f 84 1f fd ff ff je 4104e8 <_IO_wfile_seekoff+0x388> - 4107c9: e9 fa fc ff ff jmpq 4104c8 <_IO_wfile_seekoff+0x368> - 4107ce: 66 90 xchg %ax,%ax - 4107d0: 49 8b 87 a0 00 00 00 mov 0xa0(%r15),%rax - 4107d7: 4d 89 f0 mov %r14,%r8 - 4107da: 4c 2b 44 24 08 sub 0x8(%rsp),%r8 - 4107df: 49 8b 4f 10 mov 0x10(%r15),%rcx - 4107e3: 49 8b 57 18 mov 0x18(%r15),%rdx - 4107e7: 48 89 df mov %rbx,%rdi - 4107ea: 48 8d 74 24 20 lea 0x20(%rsp),%rsi - 4107ef: 48 8b 40 60 mov 0x60(%rax),%rax - 4107f3: 49 c1 f8 02 sar $0x2,%r8 - 4107f7: 48 89 44 24 20 mov %rax,0x20(%rsp) - 4107fc: ff 53 30 callq *0x30(%rbx) - 4107ff: 49 8b 4f 10 mov 0x10(%r15),%rcx - 410803: 49 2b 4f 18 sub 0x18(%r15),%rcx - 410807: 48 63 d0 movslq %eax,%rdx - 41080a: 48 89 d3 mov %rdx,%rbx - 41080d: 48 29 cb sub %rcx,%rbx - 410810: e9 a2 fc ff ff jmpq 4104b7 <_IO_wfile_seekoff+0x357> - 410815: 0f 1f 00 nopl (%rax) - 410818: 4d 8b b7 a0 00 00 00 mov 0xa0(%r15),%r14 - 41081f: 49 8b 4e 20 mov 0x20(%r14),%rcx - 410823: 4d 8b 66 18 mov 0x18(%r14),%r12 - 410827: 48 89 cd mov %rcx,%rbp - 41082a: 48 89 4c 24 08 mov %rcx,0x8(%rsp) - 41082f: 4c 29 e5 sub %r12,%rbp - 410832: 48 89 ef mov %rbp,%rdi - 410835: e8 d6 d1 00 00 callq 41da10 <__libc_malloc> - 41083a: 4c 89 64 24 20 mov %r12,0x20(%rsp) - 41083f: 48 89 44 24 18 mov %rax,0x18(%rsp) - 410844: 49 89 c2 mov %rax,%r10 - 410847: 49 8b 46 60 mov 0x60(%r14),%rax - 41084b: 4c 01 d5 add %r10,%rbp - 41084e: 4d 89 d1 mov %r10,%r9 - 410851: 4c 89 e2 mov %r12,%rdx - 410854: 48 89 df mov %rbx,%rdi - 410857: 48 89 44 24 10 mov %rax,0x10(%rsp) - 41085c: 48 8d 44 24 18 lea 0x18(%rsp),%rax - 410861: 50 push %rax - 410862: 55 push %rbp - 410863: 48 8b 4c 24 18 mov 0x18(%rsp),%rcx - 410868: 4c 89 54 24 10 mov %r10,0x10(%rsp) - 41086d: 4c 8d 44 24 30 lea 0x30(%rsp),%r8 - 410872: 48 8d 74 24 20 lea 0x20(%rsp),%rsi - 410877: ff 53 08 callq *0x8(%rbx) - 41087a: 5a pop %rdx - 41087b: 85 c0 test %eax,%eax - 41087d: 59 pop %rcx - 41087e: 4c 8b 14 24 mov (%rsp),%r10 - 410882: 75 15 jne 410899 <_IO_wfile_seekoff+0x739> - 410884: 48 8b 6c 24 18 mov 0x18(%rsp),%rbp - 410889: 4c 89 d7 mov %r10,%rdi - 41088c: 4c 29 d5 sub %r10,%rbp - 41088f: e8 1c d5 00 00 callq 41ddb0 <__cfree> - 410894: e9 bb fd ff ff jmpq 410654 <_IO_wfile_seekoff+0x4f4> - 410899: 4c 89 d7 mov %r10,%rdi - 41089c: e8 0f d5 00 00 callq 41ddb0 <__cfree> - 4108a1: ba ff ff ff ff mov $0xffffffff,%edx - 4108a6: e9 0c f9 ff ff jmpq 4101b7 <_IO_wfile_seekoff+0x57> - 4108ab: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - -00000000004108b0 <_IO_wfile_underflow_mmap>: - 4108b0: 8b 07 mov (%rdi),%eax - 4108b2: a8 04 test $0x4,%al - 4108b4: 0f 85 f6 00 00 00 jne 4109b0 <_IO_wfile_underflow_mmap+0x100> - 4108ba: 48 8b 87 a0 00 00 00 mov 0xa0(%rdi),%rax - 4108c1: 48 8b 10 mov (%rax),%rdx - 4108c4: 48 3b 50 08 cmp 0x8(%rax),%rdx - 4108c8: 0f 82 a2 00 00 00 jb 410970 <_IO_wfile_underflow_mmap+0xc0> - 4108ce: 55 push %rbp - 4108cf: 53 push %rbx - 4108d0: 48 89 fb mov %rdi,%rbx - 4108d3: 48 83 ec 18 sub $0x18,%rsp - 4108d7: 48 8b 57 08 mov 0x8(%rdi),%rdx - 4108db: 48 3b 57 10 cmp 0x10(%rdi),%rdx - 4108df: 48 8b af 98 00 00 00 mov 0x98(%rdi),%rbp - 4108e6: 0f 83 8c 00 00 00 jae 410978 <_IO_wfile_underflow_mmap+0xc8> - 4108ec: 48 83 78 30 00 cmpq $0x0,0x30(%rax) - 4108f1: 48 89 54 24 08 mov %rdx,0x8(%rsp) - 4108f6: 0f 84 d4 00 00 00 je 4109d0 <_IO_wfile_underflow_mmap+0x120> - 4108fc: 48 8b 50 58 mov 0x58(%rax),%rdx - 410900: 48 89 50 60 mov %rdx,0x60(%rax) - 410904: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 41090b: 48 8b 4b 10 mov 0x10(%rbx),%rcx - 41090f: 48 8b 53 08 mov 0x8(%rbx),%rdx - 410913: 4c 8b 48 30 mov 0x30(%rax),%r9 - 410917: 48 8d 78 08 lea 0x8(%rax),%rdi - 41091b: 48 8d 70 58 lea 0x58(%rax),%rsi - 41091f: 4c 89 08 mov %r9,(%rax) - 410922: 4c 89 48 10 mov %r9,0x10(%rax) - 410926: 57 push %rdi - 410927: ff 70 38 pushq 0x38(%rax) - 41092a: 48 89 ef mov %rbp,%rdi - 41092d: 4c 8d 44 24 18 lea 0x18(%rsp),%r8 - 410932: ff 55 18 callq *0x18(%rbp) - 410935: 48 8b 44 24 18 mov 0x18(%rsp),%rax - 41093a: 48 89 43 08 mov %rax,0x8(%rbx) - 41093e: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 410945: 59 pop %rcx - 410946: 5e pop %rsi - 410947: 48 8b 10 mov (%rax),%rdx - 41094a: 48 3b 50 08 cmp 0x8(%rax),%rdx - 41094e: 72 50 jb 4109a0 <_IO_wfile_underflow_mmap+0xf0> - 410950: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 410957: 64 c7 00 54 00 00 00 movl $0x54,%fs:(%rax) - 41095e: 83 0b 20 orl $0x20,(%rbx) - 410961: b8 ff ff ff ff mov $0xffffffff,%eax - 410966: 48 83 c4 18 add $0x18,%rsp - 41096a: 5b pop %rbx - 41096b: 5d pop %rbp - 41096c: c3 retq - 41096d: 0f 1f 00 nopl (%rax) - 410970: 8b 02 mov (%rdx),%eax - 410972: c3 retq - 410973: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 410978: e8 b3 24 00 00 callq 412e30 <_IO_file_underflow_mmap> - 41097d: 89 c2 mov %eax,%edx - 41097f: b8 ff ff ff ff mov $0xffffffff,%eax - 410984: 39 c2 cmp %eax,%edx - 410986: 74 de je 410966 <_IO_wfile_underflow_mmap+0xb6> - 410988: 48 8b 53 08 mov 0x8(%rbx),%rdx - 41098c: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 410993: e9 54 ff ff ff jmpq 4108ec <_IO_wfile_underflow_mmap+0x3c> - 410998: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 41099f: 00 - 4109a0: 8b 02 mov (%rdx),%eax - 4109a2: 48 83 c4 18 add $0x18,%rsp - 4109a6: 5b pop %rbx - 4109a7: 5d pop %rbp - 4109a8: c3 retq - 4109a9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4109b0: 83 c8 20 or $0x20,%eax - 4109b3: 89 07 mov %eax,(%rdi) - 4109b5: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 4109bc: 64 c7 00 09 00 00 00 movl $0x9,%fs:(%rax) - 4109c3: b8 ff ff ff ff mov $0xffffffff,%eax - 4109c8: c3 retq - 4109c9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4109d0: 48 8b 78 40 mov 0x40(%rax),%rdi - 4109d4: 48 85 ff test %rdi,%rdi - 4109d7: 74 0b je 4109e4 <_IO_wfile_underflow_mmap+0x134> - 4109d9: e8 d2 d3 00 00 callq 41ddb0 <__cfree> - 4109de: 81 23 ff fe ff ff andl $0xfffffeff,(%rbx) - 4109e4: 48 89 df mov %rbx,%rdi - 4109e7: e8 b4 3c 05 00 callq 4646a0 <_IO_wdoallocbuf> - 4109ec: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 4109f3: e9 04 ff ff ff jmpq 4108fc <_IO_wfile_underflow_mmap+0x4c> - 4109f8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 4109ff: 00 - -0000000000410a00 <_IO_wfile_underflow_maybe_mmap>: - 410a00: 53 push %rbx - 410a01: 48 89 fb mov %rdi,%rbx - 410a04: e8 b7 22 00 00 callq 412cc0 <_IO_file_underflow_maybe_mmap> - 410a09: 83 f8 ff cmp $0xffffffff,%eax - 410a0c: 75 02 jne 410a10 <_IO_wfile_underflow_maybe_mmap+0x10> - 410a0e: 5b pop %rbx - 410a0f: c3 retq - 410a10: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 410a17: 48 89 df mov %rbx,%rdi - 410a1a: 5b pop %rbx - 410a1b: 48 8b 80 30 01 00 00 mov 0x130(%rax),%rax - 410a22: 48 8b 40 20 mov 0x20(%rax),%rax - 410a26: ff e0 jmpq *%rax - 410a28: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 410a2f: 00 - -0000000000410a30 <_IO_wdo_write>: - 410a30: 41 57 push %r15 - 410a32: 41 56 push %r14 - 410a34: 41 55 push %r13 - 410a36: 41 54 push %r12 - 410a38: 55 push %rbp - 410a39: 53 push %rbx - 410a3a: 48 89 fb mov %rdi,%rbx - 410a3d: 48 83 ec 38 sub $0x38,%rsp - 410a41: 48 85 d2 test %rdx,%rdx - 410a44: 0f 84 46 01 00 00 je 410b90 <_IO_wdo_write+0x160> - 410a4a: 4c 8b 4f 28 mov 0x28(%rdi),%r9 - 410a4e: 4c 39 4f 30 cmp %r9,0x30(%rdi) - 410a52: 49 89 f7 mov %rsi,%r15 - 410a55: 48 8b 87 98 00 00 00 mov 0x98(%rdi),%rax - 410a5c: 49 89 d4 mov %rdx,%r12 - 410a5f: 48 8b 77 20 mov 0x20(%rdi),%rsi - 410a63: 48 89 44 24 08 mov %rax,0x8(%rsp) - 410a68: 0f 84 5e 01 00 00 je 410bcc <_IO_wdo_write+0x19c> - 410a6e: 48 89 f5 mov %rsi,%rbp - 410a71: e9 a7 00 00 00 jmpq 410b1d <_IO_wdo_write+0xed> - 410a76: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 410a7d: 00 00 00 - 410a80: 4c 8d 6c 24 20 lea 0x20(%rsp),%r13 - 410a85: 48 8d 44 24 30 lea 0x30(%rsp),%rax - 410a8a: 4d 89 e9 mov %r13,%r9 - 410a8d: 4c 89 ed mov %r13,%rbp - 410a90: 48 8b bb a0 00 00 00 mov 0xa0(%rbx),%rdi - 410a97: 4c 89 4c 24 18 mov %r9,0x18(%rsp) - 410a9c: 4b 8d 0c a7 lea (%r15,%r12,4),%rcx - 410aa0: 4c 89 fa mov %r15,%rdx - 410aa3: 48 8d 77 58 lea 0x58(%rdi),%rsi - 410aa7: 48 8d 7c 24 18 lea 0x18(%rsp),%rdi - 410aac: 57 push %rdi - 410aad: 50 push %rax - 410aae: 48 8b 44 24 18 mov 0x18(%rsp),%rax - 410ab3: 4c 8d 44 24 20 lea 0x20(%rsp),%r8 - 410ab8: 48 89 c7 mov %rax,%rdi - 410abb: ff 50 08 callq *0x8(%rax) - 410abe: 41 89 c6 mov %eax,%r14d - 410ac1: 48 89 ee mov %rbp,%rsi - 410ac4: 48 89 df mov %rbx,%rdi - 410ac7: 58 pop %rax - 410ac8: 5a pop %rdx - 410ac9: 48 8b 54 24 18 mov 0x18(%rsp),%rdx - 410ace: 4c 29 ea sub %r13,%rdx - 410ad1: e8 fa 26 00 00 callq 4131d0 <_IO_new_do_write> - 410ad6: 83 f8 ff cmp $0xffffffff,%eax - 410ad9: 0f 84 99 00 00 00 je 410b78 <_IO_wdo_write+0x148> - 410adf: 48 8b 54 24 10 mov 0x10(%rsp),%rdx - 410ae4: 48 89 d0 mov %rdx,%rax - 410ae7: 4c 29 f8 sub %r15,%rax - 410aea: 48 89 c6 mov %rax,%rsi - 410aed: 48 c1 fe 02 sar $0x2,%rsi - 410af1: 49 29 f4 sub %rsi,%r12 - 410af4: 45 85 f6 test %r14d,%r14d - 410af7: 74 10 je 410b09 <_IO_wdo_write+0xd9> - 410af9: 41 83 fe 01 cmp $0x1,%r14d - 410afd: 75 41 jne 410b40 <_IO_wdo_write+0x110> - 410aff: 48 83 c0 03 add $0x3,%rax - 410b03: 48 83 f8 06 cmp $0x6,%rax - 410b07: 76 37 jbe 410b40 <_IO_wdo_write+0x110> - 410b09: 4d 85 e4 test %r12,%r12 - 410b0c: 0f 84 7e 00 00 00 je 410b90 <_IO_wdo_write+0x160> - 410b12: 4c 8b 4b 28 mov 0x28(%rbx),%r9 - 410b16: 48 8b 6b 20 mov 0x20(%rbx),%rbp - 410b1a: 49 89 d7 mov %rdx,%r15 - 410b1d: 4c 89 c8 mov %r9,%rax - 410b20: 49 89 ed mov %rbp,%r13 - 410b23: 48 29 e8 sub %rbp,%rax - 410b26: 48 83 f8 0f cmp $0xf,%rax - 410b2a: 0f 86 50 ff ff ff jbe 410a80 <_IO_wdo_write+0x50> - 410b30: 48 8b 43 40 mov 0x40(%rbx),%rax - 410b34: e9 57 ff ff ff jmpq 410a90 <_IO_wdo_write+0x60> - 410b39: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 410b40: 48 8b 93 a0 00 00 00 mov 0xa0(%rbx),%rdx - 410b47: 31 c0 xor %eax,%eax - 410b49: 4d 85 e4 test %r12,%r12 - 410b4c: 0f 95 c0 setne %al - 410b4f: f7 d8 neg %eax - 410b51: f7 03 02 02 00 00 testl $0x202,(%rbx) - 410b57: 48 8b 4a 30 mov 0x30(%rdx),%rcx - 410b5b: 48 89 4a 10 mov %rcx,0x10(%rdx) - 410b5f: 48 89 0a mov %rcx,(%rdx) - 410b62: 48 89 4a 08 mov %rcx,0x8(%rdx) - 410b66: 48 89 4a 20 mov %rcx,0x20(%rdx) - 410b6a: 48 89 4a 18 mov %rcx,0x18(%rdx) - 410b6e: 75 04 jne 410b74 <_IO_wdo_write+0x144> - 410b70: 48 8b 4a 38 mov 0x38(%rdx),%rcx - 410b74: 48 89 4a 28 mov %rcx,0x28(%rdx) - 410b78: 48 83 c4 38 add $0x38,%rsp - 410b7c: 5b pop %rbx - 410b7d: 5d pop %rbp - 410b7e: 41 5c pop %r12 - 410b80: 41 5d pop %r13 - 410b82: 41 5e pop %r14 - 410b84: 41 5f pop %r15 - 410b86: c3 retq - 410b87: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 410b8e: 00 00 - 410b90: 48 8b 93 a0 00 00 00 mov 0xa0(%rbx),%rdx - 410b97: 8b 03 mov (%rbx),%eax - 410b99: 48 8b 4a 30 mov 0x30(%rdx),%rcx - 410b9d: 25 02 02 00 00 and $0x202,%eax - 410ba2: 48 89 4a 10 mov %rcx,0x10(%rdx) - 410ba6: 48 89 0a mov %rcx,(%rdx) - 410ba9: 48 89 4a 08 mov %rcx,0x8(%rdx) - 410bad: 48 89 4a 20 mov %rcx,0x20(%rdx) - 410bb1: 48 89 4a 18 mov %rcx,0x18(%rdx) - 410bb5: 74 b9 je 410b70 <_IO_wdo_write+0x140> - 410bb7: 48 89 4a 28 mov %rcx,0x28(%rdx) - 410bbb: 48 83 c4 38 add $0x38,%rsp - 410bbf: 31 c0 xor %eax,%eax - 410bc1: 5b pop %rbx - 410bc2: 5d pop %rbp - 410bc3: 41 5c pop %r12 - 410bc5: 41 5d pop %r13 - 410bc7: 41 5e pop %r14 - 410bc9: 41 5f pop %r15 - 410bcb: c3 retq - 410bcc: 49 39 f1 cmp %rsi,%r9 - 410bcf: 0f 84 99 fe ff ff je 410a6e <_IO_wdo_write+0x3e> - 410bd5: 4c 89 ca mov %r9,%rdx - 410bd8: 48 29 f2 sub %rsi,%rdx - 410bdb: e8 f0 25 00 00 callq 4131d0 <_IO_new_do_write> - 410be0: 83 f8 ff cmp $0xffffffff,%eax - 410be3: 74 93 je 410b78 <_IO_wdo_write+0x148> - 410be5: 4c 8b 4b 28 mov 0x28(%rbx),%r9 - 410be9: 48 8b 73 20 mov 0x20(%rbx),%rsi - 410bed: e9 7c fe ff ff jmpq 410a6e <_IO_wdo_write+0x3e> - 410bf2: 0f 1f 40 00 nopl 0x0(%rax) - 410bf6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 410bfd: 00 00 00 - -0000000000410c00 <_IO_wfile_overflow>: - 410c00: 8b 17 mov (%rdi),%edx - 410c02: f6 c2 08 test $0x8,%dl - 410c05: 74 19 je 410c20 <_IO_wfile_overflow+0x20> - 410c07: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 410c0e: 83 ca 20 or $0x20,%edx - 410c11: 89 17 mov %edx,(%rdi) - 410c13: 64 c7 00 09 00 00 00 movl $0x9,%fs:(%rax) - 410c1a: b8 ff ff ff ff mov $0xffffffff,%eax - 410c1f: c3 retq - 410c20: 55 push %rbp - 410c21: 53 push %rbx - 410c22: 89 f5 mov %esi,%ebp - 410c24: 48 89 fb mov %rdi,%rbx - 410c27: 48 83 ec 08 sub $0x8,%rsp - 410c2b: f6 c6 08 test $0x8,%dh - 410c2e: 75 6f jne 410c9f <_IO_wfile_overflow+0x9f> - 410c30: 48 8b 8f a0 00 00 00 mov 0xa0(%rdi),%rcx - 410c37: 48 83 79 18 00 cmpq $0x0,0x18(%rcx) - 410c3c: 0f 84 be 01 00 00 je 410e00 <_IO_wfile_overflow+0x200> - 410c42: 48 8b 01 mov (%rcx),%rax - 410c45: 48 8b 71 38 mov 0x38(%rcx),%rsi - 410c49: 48 39 f0 cmp %rsi,%rax - 410c4c: 0f 84 8e 01 00 00 je 410de0 <_IO_wfile_overflow+0x1e0> - 410c52: 48 89 71 28 mov %rsi,0x28(%rcx) - 410c56: 48 8b 71 08 mov 0x8(%rcx),%rsi - 410c5a: 48 89 41 20 mov %rax,0x20(%rcx) - 410c5e: 48 89 41 18 mov %rax,0x18(%rcx) - 410c62: 48 89 31 mov %rsi,(%rcx) - 410c65: 48 89 71 10 mov %rsi,0x10(%rcx) - 410c69: 48 8b 73 08 mov 0x8(%rbx),%rsi - 410c6d: 48 89 73 28 mov %rsi,0x28(%rbx) - 410c71: 48 89 73 20 mov %rsi,0x20(%rbx) - 410c75: 48 8b 73 40 mov 0x40(%rbx),%rsi - 410c79: 48 89 73 30 mov %rsi,0x30(%rbx) - 410c7d: 48 8b 73 10 mov 0x10(%rbx),%rsi - 410c81: 48 89 73 08 mov %rsi,0x8(%rbx) - 410c85: 48 89 73 18 mov %rsi,0x18(%rbx) - 410c89: 89 d6 mov %edx,%esi - 410c8b: 81 ce 00 08 00 00 or $0x800,%esi - 410c91: 81 e2 02 02 00 00 and $0x202,%edx - 410c97: 89 33 mov %esi,(%rbx) - 410c99: 74 04 je 410c9f <_IO_wfile_overflow+0x9f> - 410c9b: 48 89 41 28 mov %rax,0x28(%rcx) - 410c9f: 83 fd ff cmp $0xffffffff,%ebp - 410ca2: 74 7c je 410d20 <_IO_wfile_overflow+0x120> - 410ca4: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 410cab: 48 8b 48 20 mov 0x20(%rax),%rcx - 410caf: 48 3b 48 38 cmp 0x38(%rax),%rcx - 410cb3: 0f 84 9f 00 00 00 je 410d58 <_IO_wfile_overflow+0x158> - 410cb9: 48 8d 51 04 lea 0x4(%rcx),%rdx - 410cbd: 48 89 50 20 mov %rdx,0x20(%rax) - 410cc1: 89 29 mov %ebp,(%rcx) - 410cc3: 8b 0b mov (%rbx),%ecx - 410cc5: f6 c1 02 test $0x2,%cl - 410cc8: 74 3e je 410d08 <_IO_wfile_overflow+0x108> - 410cca: 8b 8b c0 00 00 00 mov 0xc0(%rbx),%ecx - 410cd0: 85 c9 test %ecx,%ecx - 410cd2: 0f 8e c8 00 00 00 jle 410da0 <_IO_wfile_overflow+0x1a0> - 410cd8: 48 8b 70 18 mov 0x18(%rax),%rsi - 410cdc: 48 89 df mov %rbx,%rdi - 410cdf: 48 29 f2 sub %rsi,%rdx - 410ce2: 48 c1 fa 02 sar $0x2,%rdx - 410ce6: e8 45 fd ff ff callq 410a30 <_IO_wdo_write> - 410ceb: 83 f8 ff cmp $0xffffffff,%eax - 410cee: 0f 94 c0 sete %al - 410cf1: 84 c0 test %al,%al - 410cf3: 74 1d je 410d12 <_IO_wfile_overflow+0x112> - 410cf5: 48 83 c4 08 add $0x8,%rsp - 410cf9: b8 ff ff ff ff mov $0xffffffff,%eax - 410cfe: 5b pop %rbx - 410cff: 5d pop %rbp - 410d00: c3 retq - 410d01: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 410d08: 80 e5 02 and $0x2,%ch - 410d0b: 74 05 je 410d12 <_IO_wfile_overflow+0x112> - 410d0d: 83 fd 0a cmp $0xa,%ebp - 410d10: 74 b8 je 410cca <_IO_wfile_overflow+0xca> - 410d12: 48 83 c4 08 add $0x8,%rsp - 410d16: 89 e8 mov %ebp,%eax - 410d18: 5b pop %rbx - 410d19: 5d pop %rbp - 410d1a: c3 retq - 410d1b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 410d20: 8b bb c0 00 00 00 mov 0xc0(%rbx),%edi - 410d26: 85 ff test %edi,%edi - 410d28: 0f 8e 92 00 00 00 jle 410dc0 <_IO_wfile_overflow+0x1c0> - 410d2e: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 410d35: 48 89 df mov %rbx,%rdi - 410d38: 48 8b 70 18 mov 0x18(%rax),%rsi - 410d3c: 48 8b 50 20 mov 0x20(%rax),%rdx - 410d40: 48 83 c4 08 add $0x8,%rsp - 410d44: 5b pop %rbx - 410d45: 5d pop %rbp - 410d46: 48 29 f2 sub %rsi,%rdx - 410d49: 48 c1 fa 02 sar $0x2,%rdx - 410d4d: e9 de fc ff ff jmpq 410a30 <_IO_wdo_write> - 410d52: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 410d58: 8b b3 c0 00 00 00 mov 0xc0(%rbx),%esi - 410d5e: 85 f6 test %esi,%esi - 410d60: 0f 8e c7 00 00 00 jle 410e2d <_IO_wfile_overflow+0x22d> - 410d66: 48 8b 70 18 mov 0x18(%rax),%rsi - 410d6a: 48 89 df mov %rbx,%rdi - 410d6d: 48 29 f1 sub %rsi,%rcx - 410d70: 48 89 ca mov %rcx,%rdx - 410d73: 48 c1 fa 02 sar $0x2,%rdx - 410d77: e8 b4 fc ff ff callq 410a30 <_IO_wdo_write> - 410d7c: 83 f8 ff cmp $0xffffffff,%eax - 410d7f: 0f 94 c0 sete %al - 410d82: 84 c0 test %al,%al - 410d84: 0f 85 6b ff ff ff jne 410cf5 <_IO_wfile_overflow+0xf5> - 410d8a: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 410d91: 48 8b 48 20 mov 0x20(%rax),%rcx - 410d95: e9 1f ff ff ff jmpq 410cb9 <_IO_wfile_overflow+0xb9> - 410d9a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 410da0: 48 8b 73 20 mov 0x20(%rbx),%rsi - 410da4: 48 8b 53 28 mov 0x28(%rbx),%rdx - 410da8: 48 89 df mov %rbx,%rdi - 410dab: 48 29 f2 sub %rsi,%rdx - 410dae: e8 1d 24 00 00 callq 4131d0 <_IO_new_do_write> - 410db3: 83 f8 ff cmp $0xffffffff,%eax - 410db6: 0f 94 c0 sete %al - 410db9: e9 33 ff ff ff jmpq 410cf1 <_IO_wfile_overflow+0xf1> - 410dbe: 66 90 xchg %ax,%ax - 410dc0: 48 8b 73 20 mov 0x20(%rbx),%rsi - 410dc4: 48 8b 53 28 mov 0x28(%rbx),%rdx - 410dc8: 48 83 c4 08 add $0x8,%rsp - 410dcc: 48 89 df mov %rbx,%rdi - 410dcf: 5b pop %rbx - 410dd0: 5d pop %rbp - 410dd1: 48 29 f2 sub %rsi,%rdx - 410dd4: e9 f7 23 00 00 jmpq 4131d0 <_IO_new_do_write> - 410dd9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 410de0: 48 8b 47 38 mov 0x38(%rdi),%rax - 410de4: 48 89 47 08 mov %rax,0x8(%rdi) - 410de8: 48 89 47 10 mov %rax,0x10(%rdi) - 410dec: 48 8b 41 30 mov 0x30(%rcx),%rax - 410df0: 48 89 01 mov %rax,(%rcx) - 410df3: 48 89 41 08 mov %rax,0x8(%rcx) - 410df7: e9 56 fe ff ff jmpq 410c52 <_IO_wfile_overflow+0x52> - 410dfc: 0f 1f 40 00 nopl 0x0(%rax) - 410e00: e8 9b 38 05 00 callq 4646a0 <_IO_wdoallocbuf> - 410e05: 48 8b 8b a0 00 00 00 mov 0xa0(%rbx),%rcx - 410e0c: 48 83 7b 20 00 cmpq $0x0,0x20(%rbx) - 410e11: 48 8b 41 30 mov 0x30(%rcx),%rax - 410e15: 48 89 41 10 mov %rax,0x10(%rcx) - 410e19: 48 89 01 mov %rax,(%rcx) - 410e1c: 48 89 41 08 mov %rax,0x8(%rcx) - 410e20: 74 29 je 410e4b <_IO_wfile_overflow+0x24b> - 410e22: 48 8b 71 38 mov 0x38(%rcx),%rsi - 410e26: 8b 13 mov (%rbx),%edx - 410e28: e9 25 fe ff ff jmpq 410c52 <_IO_wfile_overflow+0x52> - 410e2d: 48 8b 73 20 mov 0x20(%rbx),%rsi - 410e31: 48 8b 53 28 mov 0x28(%rbx),%rdx - 410e35: 48 89 df mov %rbx,%rdi - 410e38: 48 29 f2 sub %rsi,%rdx - 410e3b: e8 90 23 00 00 callq 4131d0 <_IO_new_do_write> - 410e40: 83 f8 ff cmp $0xffffffff,%eax - 410e43: 0f 94 c0 sete %al - 410e46: e9 37 ff ff ff jmpq 410d82 <_IO_wfile_overflow+0x182> - 410e4b: 48 89 df mov %rbx,%rdi - 410e4e: e8 ad 3f 00 00 callq 414e00 <_IO_doallocbuf> - 410e53: 48 8b 43 38 mov 0x38(%rbx),%rax - 410e57: 48 8b 8b a0 00 00 00 mov 0xa0(%rbx),%rcx - 410e5e: 48 89 43 08 mov %rax,0x8(%rbx) - 410e62: 48 89 43 10 mov %rax,0x10(%rbx) - 410e66: 48 8b 01 mov (%rcx),%rax - 410e69: eb b7 jmp 410e22 <_IO_wfile_overflow+0x222> - 410e6b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - -0000000000410e70 <_IO_wfile_sync>: - 410e70: 41 54 push %r12 - 410e72: 55 push %rbp - 410e73: 53 push %rbx - 410e74: 48 8b 87 a0 00 00 00 mov 0xa0(%rdi),%rax - 410e7b: 48 89 fb mov %rdi,%rbx - 410e7e: 48 8b 50 20 mov 0x20(%rax),%rdx - 410e82: 48 8b 70 18 mov 0x18(%rax),%rsi - 410e86: 48 39 f2 cmp %rsi,%rdx - 410e89: 76 3c jbe 410ec7 <_IO_wfile_sync+0x57> - 410e8b: 8b 87 c0 00 00 00 mov 0xc0(%rdi),%eax - 410e91: 85 c0 test %eax,%eax - 410e93: 0f 8e a7 00 00 00 jle 410f40 <_IO_wfile_sync+0xd0> - 410e99: 48 29 f2 sub %rsi,%rdx - 410e9c: 48 c1 fa 02 sar $0x2,%rdx - 410ea0: e8 8b fb ff ff callq 410a30 <_IO_wdo_write> - 410ea5: 85 c0 test %eax,%eax - 410ea7: 0f 95 c0 setne %al - 410eaa: 84 c0 test %al,%al - 410eac: 74 12 je 410ec0 <_IO_wfile_sync+0x50> - 410eae: 5b pop %rbx - 410eaf: b8 ff ff ff ff mov $0xffffffff,%eax - 410eb4: 5d pop %rbp - 410eb5: 41 5c pop %r12 - 410eb7: c3 retq - 410eb8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 410ebf: 00 - 410ec0: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 410ec7: 48 8b 28 mov (%rax),%rbp - 410eca: 48 2b 68 08 sub 0x8(%rax),%rbp - 410ece: 48 c1 fd 02 sar $0x2,%rbp - 410ed2: 48 85 ed test %rbp,%rbp - 410ed5: 75 19 jne 410ef0 <_IO_wfile_sync+0x80> - 410ed7: 48 c7 83 90 00 00 00 movq $0xffffffffffffffff,0x90(%rbx) - 410ede: ff ff ff ff - 410ee2: 31 c0 xor %eax,%eax - 410ee4: 5b pop %rbx - 410ee5: 5d pop %rbp - 410ee6: 41 5c pop %r12 - 410ee8: c3 retq - 410ee9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 410ef0: 4c 8b a3 98 00 00 00 mov 0x98(%rbx),%r12 - 410ef7: 4c 89 e7 mov %r12,%rdi - 410efa: 41 ff 54 24 20 callq *0x20(%r12) - 410eff: 85 c0 test %eax,%eax - 410f01: 7e 7d jle 410f80 <_IO_wfile_sync+0x110> - 410f03: 48 63 f0 movslq %eax,%rsi - 410f06: 48 0f af f5 imul %rbp,%rsi - 410f0a: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 410f11: ba 01 00 00 00 mov $0x1,%edx - 410f16: 48 89 df mov %rbx,%rdi - 410f19: ff 90 80 00 00 00 callq *0x80(%rax) - 410f1f: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 410f23: 74 3b je 410f60 <_IO_wfile_sync+0xf0> - 410f25: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 410f2c: 48 8b 10 mov (%rax),%rdx - 410f2f: 48 89 50 08 mov %rdx,0x8(%rax) - 410f33: 48 8b 43 08 mov 0x8(%rbx),%rax - 410f37: 48 89 43 10 mov %rax,0x10(%rbx) - 410f3b: eb 9a jmp 410ed7 <_IO_wfile_sync+0x67> - 410f3d: 0f 1f 00 nopl (%rax) - 410f40: 48 8b 77 20 mov 0x20(%rdi),%rsi - 410f44: 48 8b 57 28 mov 0x28(%rdi),%rdx - 410f48: 48 29 f2 sub %rsi,%rdx - 410f4b: e8 80 22 00 00 callq 4131d0 <_IO_new_do_write> - 410f50: 85 c0 test %eax,%eax - 410f52: 0f 95 c0 setne %al - 410f55: e9 50 ff ff ff jmpq 410eaa <_IO_wfile_sync+0x3a> - 410f5a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 410f60: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 410f67: 64 83 38 1d cmpl $0x1d,%fs:(%rax) - 410f6b: 0f 85 3d ff ff ff jne 410eae <_IO_wfile_sync+0x3e> - 410f71: e9 61 ff ff ff jmpq 410ed7 <_IO_wfile_sync+0x67> - 410f76: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 410f7d: 00 00 00 - 410f80: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 410f87: 49 89 e8 mov %rbp,%r8 - 410f8a: 4c 89 e7 mov %r12,%rdi - 410f8d: 48 8b 50 60 mov 0x60(%rax),%rdx - 410f91: 48 89 50 58 mov %rdx,0x58(%rax) - 410f95: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 410f9c: 48 8b 4b 10 mov 0x10(%rbx),%rcx - 410fa0: 48 8b 53 18 mov 0x18(%rbx),%rdx - 410fa4: 48 8d 70 58 lea 0x58(%rax),%rsi - 410fa8: 41 ff 54 24 30 callq *0x30(%r12) - 410fad: 48 8b 53 18 mov 0x18(%rbx),%rdx - 410fb1: 48 98 cltq - 410fb3: 48 8d 0c 02 lea (%rdx,%rax,1),%rcx - 410fb7: 48 2b 53 10 sub 0x10(%rbx),%rdx - 410fbb: 48 89 4b 08 mov %rcx,0x8(%rbx) - 410fbf: 48 8d 34 02 lea (%rdx,%rax,1),%rsi - 410fc3: e9 42 ff ff ff jmpq 410f0a <_IO_wfile_sync+0x9a> - 410fc8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 410fcf: 00 - -0000000000410fd0 <_IO_wfile_xsputn>: - 410fd0: 48 85 d2 test %rdx,%rdx - 410fd3: 0f 84 df 01 00 00 je 4111b8 <_IO_wfile_xsputn+0x1e8> - 410fd9: 41 57 push %r15 - 410fdb: 41 56 push %r14 - 410fdd: 41 55 push %r13 - 410fdf: 41 54 push %r12 - 410fe1: 49 89 fd mov %rdi,%r13 - 410fe4: 55 push %rbp - 410fe5: 53 push %rbx - 410fe6: 48 89 f5 mov %rsi,%rbp - 410fe9: 49 89 d4 mov %rdx,%r12 - 410fec: 48 83 ec 28 sub $0x28,%rsp - 410ff0: 41 8b 45 00 mov 0x0(%r13),%eax - 410ff4: 4c 8b b7 a0 00 00 00 mov 0xa0(%rdi),%r14 - 410ffb: 25 00 0a 00 00 and $0xa00,%eax - 411000: 49 8b 5e 28 mov 0x28(%r14),%rbx - 411004: 49 8b 7e 20 mov 0x20(%r14),%rdi - 411008: 3d 00 0a 00 00 cmp $0xa00,%eax - 41100d: 0f 84 cd 01 00 00 je 4111e0 <_IO_wfile_xsputn+0x210> - 411013: 48 29 fb sub %rdi,%rbx - 411016: 45 31 ff xor %r15d,%r15d - 411019: 48 c1 fb 02 sar $0x2,%rbx - 41101d: 48 85 db test %rbx,%rbx - 411020: 0f 84 9a 01 00 00 je 4111c0 <_IO_wfile_xsputn+0x1f0> - 411026: 49 39 dc cmp %rbx,%r12 - 411029: 49 0f 46 dc cmovbe %r12,%rbx - 41102d: 48 83 fb 14 cmp $0x14,%rbx - 411031: 0f 87 f9 01 00 00 ja 411230 <_IO_wfile_xsputn+0x260> - 411037: 48 8d 55 10 lea 0x10(%rbp),%rdx - 41103b: 8d 43 ff lea -0x1(%rbx),%eax - 41103e: 48 39 d7 cmp %rdx,%rdi - 411041: 48 8d 57 10 lea 0x10(%rdi),%rdx - 411045: 89 c1 mov %eax,%ecx - 411047: 40 0f 93 c6 setae %sil - 41104b: 48 39 d5 cmp %rdx,%rbp - 41104e: 0f 93 c2 setae %dl - 411051: 40 08 d6 or %dl,%sil - 411054: 0f 84 06 02 00 00 je 411260 <_IO_wfile_xsputn+0x290> - 41105a: 83 fb 0c cmp $0xc,%ebx - 41105d: 0f 86 fd 01 00 00 jbe 411260 <_IO_wfile_xsputn+0x290> - 411063: 49 89 e8 mov %rbp,%r8 - 411066: 41 83 e0 0f and $0xf,%r8d - 41106a: 49 c1 e8 02 shr $0x2,%r8 - 41106e: 49 f7 d8 neg %r8 - 411071: 41 83 e0 03 and $0x3,%r8d - 411075: 41 39 d8 cmp %ebx,%r8d - 411078: 44 0f 47 c3 cmova %ebx,%r8d - 41107c: 45 85 c0 test %r8d,%r8d - 41107f: 0f 84 cb 01 00 00 je 411250 <_IO_wfile_xsputn+0x280> - 411085: 8b 55 00 mov 0x0(%rbp),%edx - 411088: 41 83 f8 01 cmp $0x1,%r8d - 41108c: 48 8d 77 04 lea 0x4(%rdi),%rsi - 411090: 4c 8d 55 04 lea 0x4(%rbp),%r10 - 411094: 8d 4b fe lea -0x2(%rbx),%ecx - 411097: 89 17 mov %edx,(%rdi) - 411099: 74 28 je 4110c3 <_IO_wfile_xsputn+0xf3> - 41109b: 8b 55 04 mov 0x4(%rbp),%edx - 41109e: 41 83 f8 03 cmp $0x3,%r8d - 4110a2: 48 8d 77 08 lea 0x8(%rdi),%rsi - 4110a6: 4c 8d 55 08 lea 0x8(%rbp),%r10 - 4110aa: 8d 4b fd lea -0x3(%rbx),%ecx - 4110ad: 89 57 04 mov %edx,0x4(%rdi) - 4110b0: 75 11 jne 4110c3 <_IO_wfile_xsputn+0xf3> - 4110b2: 8b 55 08 mov 0x8(%rbp),%edx - 4110b5: 48 8d 77 0c lea 0xc(%rdi),%rsi - 4110b9: 4c 8d 55 0c lea 0xc(%rbp),%r10 - 4110bd: 8d 4b fc lea -0x4(%rbx),%ecx - 4110c0: 89 57 08 mov %edx,0x8(%rdi) - 4110c3: 89 da mov %ebx,%edx - 4110c5: 89 44 24 1c mov %eax,0x1c(%rsp) - 4110c9: 44 29 c2 sub %r8d,%edx - 4110cc: 45 89 c0 mov %r8d,%r8d - 4110cf: 89 54 24 14 mov %edx,0x14(%rsp) - 4110d3: 83 ea 04 sub $0x4,%edx - 4110d6: 49 c1 e0 02 shl $0x2,%r8 - 4110da: c1 ea 02 shr $0x2,%edx - 4110dd: 4e 8d 5c 05 00 lea 0x0(%rbp,%r8,1),%r11 - 4110e2: 83 c2 01 add $0x1,%edx - 4110e5: 44 8d 0c 95 00 00 00 lea 0x0(,%rdx,4),%r9d - 4110ec: 00 - 4110ed: 44 89 4c 24 18 mov %r9d,0x18(%rsp) - 4110f2: 4e 8d 0c 07 lea (%rdi,%r8,1),%r9 - 4110f6: 45 31 c0 xor %r8d,%r8d - 4110f9: 4c 89 4c 24 08 mov %r9,0x8(%rsp) - 4110fe: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 411103: 45 31 c9 xor %r9d,%r9d - 411106: 66 43 0f 6f 04 03 movdqa (%r11,%r8,1),%xmm0 - 41110c: 41 83 c1 01 add $0x1,%r9d - 411110: 42 0f 11 04 00 movups %xmm0,(%rax,%r8,1) - 411115: 49 83 c0 10 add $0x10,%r8 - 411119: 41 39 d1 cmp %edx,%r9d - 41111c: 72 e8 jb 411106 <_IO_wfile_xsputn+0x136> - 41111e: 44 8b 5c 24 18 mov 0x18(%rsp),%r11d - 411123: 8b 44 24 1c mov 0x1c(%rsp),%eax - 411127: 44 89 da mov %r11d,%edx - 41112a: 44 29 d9 sub %r11d,%ecx - 41112d: 48 c1 e2 02 shl $0x2,%rdx - 411131: 48 01 d6 add %rdx,%rsi - 411134: 49 01 d2 add %rdx,%r10 - 411137: 44 39 5c 24 14 cmp %r11d,0x14(%rsp) - 41113c: 74 1c je 41115a <_IO_wfile_xsputn+0x18a> - 41113e: 41 8b 12 mov (%r10),%edx - 411141: 85 c9 test %ecx,%ecx - 411143: 89 16 mov %edx,(%rsi) - 411145: 74 13 je 41115a <_IO_wfile_xsputn+0x18a> - 411147: 41 8b 52 04 mov 0x4(%r10),%edx - 41114b: 83 f9 01 cmp $0x1,%ecx - 41114e: 89 56 04 mov %edx,0x4(%rsi) - 411151: 74 07 je 41115a <_IO_wfile_xsputn+0x18a> - 411153: 41 8b 52 08 mov 0x8(%r10),%edx - 411157: 89 56 08 mov %edx,0x8(%rsi) - 41115a: 48 8d 04 85 04 00 00 lea 0x4(,%rax,4),%rax - 411161: 00 - 411162: 48 01 c7 add %rax,%rdi - 411165: 48 01 c5 add %rax,%rbp - 411168: 49 89 7e 20 mov %rdi,0x20(%r14) - 41116c: 4c 89 e0 mov %r12,%rax - 41116f: 48 29 d8 sub %rbx,%rax - 411172: 48 89 c3 mov %rax,%rbx - 411175: 75 4c jne 4111c3 <_IO_wfile_xsputn+0x1f3> - 411177: 45 85 ff test %r15d,%r15d - 41117a: 74 23 je 41119f <_IO_wfile_xsputn+0x1cf> - 41117c: 49 8b 85 a0 00 00 00 mov 0xa0(%r13),%rax - 411183: 48 8b 50 20 mov 0x20(%rax),%rdx - 411187: 48 8b 70 18 mov 0x18(%rax),%rsi - 41118b: 48 39 f2 cmp %rsi,%rdx - 41118e: 74 0f je 41119f <_IO_wfile_xsputn+0x1cf> - 411190: 48 29 f2 sub %rsi,%rdx - 411193: 4c 89 ef mov %r13,%rdi - 411196: 48 c1 fa 02 sar $0x2,%rdx - 41119a: e8 91 f8 ff ff callq 410a30 <_IO_wdo_write> - 41119f: 48 83 c4 28 add $0x28,%rsp - 4111a3: 4c 89 e0 mov %r12,%rax - 4111a6: 48 29 d8 sub %rbx,%rax - 4111a9: 5b pop %rbx - 4111aa: 5d pop %rbp - 4111ab: 41 5c pop %r12 - 4111ad: 41 5d pop %r13 - 4111af: 41 5e pop %r14 - 4111b1: 41 5f pop %r15 - 4111b3: c3 retq - 4111b4: 0f 1f 40 00 nopl 0x0(%rax) - 4111b8: 31 c0 xor %eax,%eax - 4111ba: c3 retq - 4111bb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4111c0: 4c 89 e3 mov %r12,%rbx - 4111c3: 48 89 da mov %rbx,%rdx - 4111c6: 48 89 ee mov %rbp,%rsi - 4111c9: 4c 89 ef mov %r13,%rdi - 4111cc: e8 df 2d 05 00 callq 463fb0 <_IO_wdefault_xsputn> - 4111d1: 48 29 c3 sub %rax,%rbx - 4111d4: eb a1 jmp 411177 <_IO_wfile_xsputn+0x1a7> - 4111d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4111dd: 00 00 00 - 4111e0: 49 8b 5e 38 mov 0x38(%r14),%rbx - 4111e4: 45 31 ff xor %r15d,%r15d - 4111e7: 48 29 fb sub %rdi,%rbx - 4111ea: 48 c1 fb 02 sar $0x2,%rbx - 4111ee: 48 39 da cmp %rbx,%rdx - 4111f1: 0f 87 26 fe ff ff ja 41101d <_IO_wfile_xsputn+0x4d> - 4111f7: 48 8d 14 96 lea (%rsi,%rdx,4),%rdx - 4111fb: 48 39 d6 cmp %rdx,%rsi - 4111fe: 0f 83 19 fe ff ff jae 41101d <_IO_wfile_xsputn+0x4d> - 411204: 83 7a fc 0a cmpl $0xa,-0x4(%rdx) - 411208: 48 8d 42 fc lea -0x4(%rdx),%rax - 41120c: 75 0b jne 411219 <_IO_wfile_xsputn+0x249> - 41120e: eb 78 jmp 411288 <_IO_wfile_xsputn+0x2b8> - 411210: 48 83 e8 04 sub $0x4,%rax - 411214: 83 38 0a cmpl $0xa,(%rax) - 411217: 74 6f je 411288 <_IO_wfile_xsputn+0x2b8> - 411219: 48 39 c5 cmp %rax,%rbp - 41121c: 72 f2 jb 411210 <_IO_wfile_xsputn+0x240> - 41121e: 45 31 ff xor %r15d,%r15d - 411221: e9 f7 fd ff ff jmpq 41101d <_IO_wfile_xsputn+0x4d> - 411226: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41122d: 00 00 00 - 411230: 48 89 ee mov %rbp,%rsi - 411233: 48 89 da mov %rbx,%rdx - 411236: 48 8d 6c 9d 00 lea 0x0(%rbp,%rbx,4),%rbp - 41123b: e8 00 d1 02 00 callq 43e340 <__wmempcpy> - 411240: 49 89 46 20 mov %rax,0x20(%r14) - 411244: e9 23 ff ff ff jmpq 41116c <_IO_wfile_xsputn+0x19c> - 411249: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 411250: 49 89 ea mov %rbp,%r10 - 411253: 48 89 fe mov %rdi,%rsi - 411256: e9 68 fe ff ff jmpq 4110c3 <_IO_wfile_xsputn+0xf3> - 41125b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 411260: 89 c6 mov %eax,%esi - 411262: 31 d2 xor %edx,%edx - 411264: 48 83 c6 01 add $0x1,%rsi - 411268: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 41126f: 00 - 411270: 8b 4c 95 00 mov 0x0(%rbp,%rdx,4),%ecx - 411274: 89 0c 97 mov %ecx,(%rdi,%rdx,4) - 411277: 48 83 c2 01 add $0x1,%rdx - 41127b: 48 39 f2 cmp %rsi,%rdx - 41127e: 75 f0 jne 411270 <_IO_wfile_xsputn+0x2a0> - 411280: e9 d5 fe ff ff jmpq 41115a <_IO_wfile_xsputn+0x18a> - 411285: 0f 1f 00 nopl (%rax) - 411288: 48 29 e8 sub %rbp,%rax - 41128b: 41 bf 01 00 00 00 mov $0x1,%r15d - 411291: 48 c1 f8 02 sar $0x2,%rax - 411295: 48 8d 58 01 lea 0x1(%rax),%rbx - 411299: e9 7f fd ff ff jmpq 41101d <_IO_wfile_xsputn+0x4d> - 41129e: 66 90 xchg %ax,%ax - -00000000004112a0 <_IO_vasprintf>: - 4112a0: 41 55 push %r13 - 4112a2: 41 54 push %r12 - 4112a4: 49 89 fc mov %rdi,%r12 - 4112a7: 55 push %rbp - 4112a8: 53 push %rbx - 4112a9: bf 64 00 00 00 mov $0x64,%edi - 4112ae: 48 89 f5 mov %rsi,%rbp - 4112b1: 49 89 d5 mov %rdx,%r13 - 4112b4: 48 81 ec f8 00 00 00 sub $0xf8,%rsp - 4112bb: e8 50 c7 00 00 callq 41da10 <__libc_malloc> - 4112c0: 48 85 c0 test %rax,%rax - 4112c3: 0f 84 17 01 00 00 je 4113e0 <_IO_vasprintf+0x140> - 4112c9: 48 89 c3 mov %rax,%rbx - 4112cc: 45 31 c0 xor %r8d,%r8d - 4112cf: 31 c9 xor %ecx,%ecx - 4112d1: ba ff ff ff ff mov $0xffffffff,%edx - 4112d6: be 00 80 00 00 mov $0x8000,%esi - 4112db: 48 89 e7 mov %rsp,%rdi - 4112de: 48 c7 84 24 88 00 00 movq $0x0,0x88(%rsp) - 4112e5: 00 00 00 00 00 - 4112ea: e8 d1 41 00 00 callq 4154c0 <_IO_no_init> - 4112ef: 48 89 d9 mov %rbx,%rcx - 4112f2: 48 89 de mov %rbx,%rsi - 4112f5: ba 64 00 00 00 mov $0x64,%edx - 4112fa: 48 89 e7 mov %rsp,%rdi - 4112fd: 48 c7 84 24 d8 00 00 movq $0x4a1f00,0xd8(%rsp) - 411304: 00 00 1f 4a 00 - 411309: e8 32 59 00 00 callq 416c40 <_IO_str_init_static_internal> - 41130e: 4c 89 ea mov %r13,%rdx - 411311: 48 89 ee mov %rbp,%rsi - 411314: 48 89 e7 mov %rsp,%rdi - 411317: 83 24 24 fe andl $0xfffffffe,(%rsp) - 41131b: 48 c7 84 24 e0 00 00 movq $0x41da10,0xe0(%rsp) - 411322: 00 10 da 41 00 - 411327: 48 c7 84 24 e8 00 00 movq $0x41ddb0,0xe8(%rsp) - 41132e: 00 b0 dd 41 00 - 411333: e8 98 35 04 00 callq 4548d0 <_IO_vfprintf> - 411338: 85 c0 test %eax,%eax - 41133a: 89 c3 mov %eax,%ebx - 41133c: 0f 88 8e 00 00 00 js 4113d0 <_IO_vasprintf+0x130> - 411342: 48 8b 44 24 20 mov 0x20(%rsp),%rax - 411347: 48 8b 6c 24 28 mov 0x28(%rsp),%rbp - 41134c: 48 8b 54 24 30 mov 0x30(%rsp),%rdx - 411351: 48 29 c5 sub %rax,%rbp - 411354: 48 29 c2 sub %rax,%rdx - 411357: 4c 8d 6d 01 lea 0x1(%rbp),%r13 - 41135b: 48 d1 ea shr %rdx - 41135e: 49 39 d5 cmp %rdx,%r13 - 411361: 72 2d jb 411390 <_IO_vasprintf+0xf0> - 411363: 48 8b 7c 24 38 mov 0x38(%rsp),%rdi - 411368: 4c 89 ee mov %r13,%rsi - 41136b: e8 00 cc 00 00 callq 41df70 <__libc_realloc> - 411370: 48 85 c0 test %rax,%rax - 411373: 49 89 04 24 mov %rax,(%r12) - 411377: 74 4c je 4113c5 <_IO_vasprintf+0x125> - 411379: c6 04 28 00 movb $0x0,(%rax,%rbp,1) - 41137d: 89 d8 mov %ebx,%eax - 41137f: 48 81 c4 f8 00 00 00 add $0xf8,%rsp - 411386: 5b pop %rbx - 411387: 5d pop %rbp - 411388: 41 5c pop %r12 - 41138a: 41 5d pop %r13 - 41138c: c3 retq - 41138d: 0f 1f 00 nopl (%rax) - 411390: 4c 89 ef mov %r13,%rdi - 411393: e8 78 c6 00 00 callq 41da10 <__libc_malloc> - 411398: 48 85 c0 test %rax,%rax - 41139b: 49 89 04 24 mov %rax,(%r12) - 41139f: 74 c2 je 411363 <_IO_vasprintf+0xc3> - 4113a1: 4c 8b 6c 24 38 mov 0x38(%rsp),%r13 - 4113a6: 48 89 ea mov %rbp,%rdx - 4113a9: 48 89 c7 mov %rax,%rdi - 4113ac: 4c 89 ee mov %r13,%rsi - 4113af: e8 6c ac 01 00 callq 42c020 - 4113b4: 4c 89 ef mov %r13,%rdi - 4113b7: e8 f4 c9 00 00 callq 41ddb0 <__cfree> - 4113bc: 49 8b 04 24 mov (%r12),%rax - 4113c0: 48 85 c0 test %rax,%rax - 4113c3: 75 b4 jne 411379 <_IO_vasprintf+0xd9> - 4113c5: 48 8b 44 24 38 mov 0x38(%rsp),%rax - 4113ca: 49 89 04 24 mov %rax,(%r12) - 4113ce: eb a9 jmp 411379 <_IO_vasprintf+0xd9> - 4113d0: 48 8b 7c 24 38 mov 0x38(%rsp),%rdi - 4113d5: e8 d6 c9 00 00 callq 41ddb0 <__cfree> - 4113da: 89 d8 mov %ebx,%eax - 4113dc: eb a1 jmp 41137f <_IO_vasprintf+0xdf> - 4113de: 66 90 xchg %ax,%ax - 4113e0: b8 ff ff ff ff mov $0xffffffff,%eax - 4113e5: eb 98 jmp 41137f <_IO_vasprintf+0xdf> - 4113e7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 4113ee: 00 00 - -00000000004113f0 <__fcloseall>: - 4113f0: e9 fb 2d 00 00 jmpq 4141f0 <_IO_cleanup> - 4113f5: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4113fc: 00 00 00 - 4113ff: 90 nop - -0000000000411400 <__libc_message.constprop.0>: - 411400: 55 push %rbp - 411401: bf 14 1c 4a 00 mov $0x4a1c14,%edi - 411406: 48 89 e5 mov %rsp,%rbp - 411409: 41 57 push %r15 - 41140b: 41 56 push %r14 - 41140d: 48 8d 45 10 lea 0x10(%rbp),%rax - 411411: 41 55 push %r13 - 411413: 41 54 push %r12 - 411415: 53 push %rbx - 411416: 48 83 ec 58 sub $0x58,%rsp - 41141a: 48 89 45 90 mov %rax,-0x70(%rbp) - 41141e: 48 8d 45 a0 lea -0x60(%rbp),%rax - 411422: 48 89 55 b0 mov %rdx,-0x50(%rbp) - 411426: 48 89 4d b8 mov %rcx,-0x48(%rbp) - 41142a: 4c 89 45 c0 mov %r8,-0x40(%rbp) - 41142e: 4c 89 4d c8 mov %r9,-0x38(%rbp) - 411432: c7 45 88 10 00 00 00 movl $0x10,-0x78(%rbp) - 411439: 48 89 45 98 mov %rax,-0x68(%rbp) - 41143d: e8 5e 05 04 00 callq 4519a0 <__libc_secure_getenv> - 411442: 48 85 c0 test %rax,%rax - 411445: 74 09 je 411450 <__libc_message.constprop.0+0x50> - 411447: 80 38 00 cmpb $0x0,(%rax) - 41144a: 0f 85 26 01 00 00 jne 411576 <__libc_message.constprop.0+0x176> - 411450: be 02 09 00 00 mov $0x902,%esi - 411455: bf 27 1c 4a 00 mov $0x4a1c27,%edi - 41145a: b8 02 00 00 00 mov $0x2,%eax - 41145f: 0f 05 syscall - 411461: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 411467: 0f 87 2b 01 00 00 ja 411598 <__libc_message.constprop.0+0x198> - 41146d: 83 f8 ff cmp $0xffffffff,%eax - 411470: 41 89 c5 mov %eax,%r13d - 411473: 0f 84 fd 00 00 00 je 411576 <__libc_message.constprop.0+0x176> - 411479: 4c 63 e0 movslq %eax,%r12 - 41147c: 8b 45 88 mov -0x78(%rbp),%eax - 41147f: 83 f8 2f cmp $0x2f,%eax - 411482: 0f 87 ff 00 00 00 ja 411587 <__libc_message.constprop.0+0x187> - 411488: 89 c2 mov %eax,%edx - 41148a: 48 03 55 98 add -0x68(%rbp),%rdx - 41148e: 83 c0 08 add $0x8,%eax - 411491: 89 45 88 mov %eax,-0x78(%rbp) - 411494: 4c 8b 32 mov (%rdx),%r14 - 411497: 4c 89 f7 mov %r14,%rdi - 41149a: e8 b1 21 01 00 callq 423650 - 41149f: 48 83 ec 30 sub $0x30,%rsp - 4114a3: 49 89 c0 mov %rax,%r8 - 4114a6: 41 b9 14 00 00 00 mov $0x14,%r9d - 4114ac: 48 8d 44 24 0f lea 0xf(%rsp),%rax - 4114b1: 48 83 ec 20 sub $0x20,%rsp - 4114b5: 48 8d 5c 24 0f lea 0xf(%rsp),%rbx - 4114ba: 48 83 e0 f0 and $0xfffffffffffffff0,%rax - 4114be: 48 83 e3 f0 and $0xfffffffffffffff0,%rbx - 4114c2: 4c 89 30 mov %r14,(%rax) - 4114c5: 4c 89 40 08 mov %r8,0x8(%rax) - 4114c9: 48 c7 40 10 00 00 00 movq $0x0,0x10(%rax) - 4114d0: 00 - 4114d1: 4c 89 33 mov %r14,(%rbx) - 4114d4: 4c 89 43 08 mov %r8,0x8(%rbx) - 4114d8: ba 01 00 00 00 mov $0x1,%edx - 4114dd: 48 89 de mov %rbx,%rsi - 4114e0: 4c 89 e7 mov %r12,%rdi - 4114e3: 44 89 c8 mov %r9d,%eax - 4114e6: 0f 05 syscall - 4114e8: 48 83 f8 fc cmp $0xfffffffffffffffc,%rax - 4114ec: 74 ea je 4114d8 <__libc_message.constprop.0+0xd8> - 4114ee: 4c 8b 3d 8b 9c 2b 00 mov 0x2b9c8b(%rip),%r15 # 6cb180 <_dl_pagesize> - 4114f5: 49 39 c0 cmp %rax,%r8 - 4114f8: b9 22 00 00 00 mov $0x22,%ecx - 4114fd: 41 0f 94 c4 sete %r12b - 411501: ba 03 00 00 00 mov $0x3,%edx - 411506: 45 31 c9 xor %r9d,%r9d - 411509: 31 ff xor %edi,%edi - 41150b: 4b 8d 04 38 lea (%r8,%r15,1),%rax - 41150f: 49 f7 df neg %r15 - 411512: 41 83 c8 ff or $0xffffffff,%r8d - 411516: 49 21 c7 and %rax,%r15 - 411519: 4c 89 fe mov %r15,%rsi - 41151c: e8 cf e6 02 00 callq 43fbf0 <__mmap> - 411521: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 411525: 49 89 c6 mov %rax,%r14 - 411528: 74 36 je 411560 <__libc_message.constprop.0+0x160> - 41152a: 48 8b 53 08 mov 0x8(%rbx),%rdx - 41152e: 48 8b 33 mov (%rbx),%rsi - 411531: 48 8d 78 04 lea 0x4(%rax),%rdi - 411535: 44 89 38 mov %r15d,(%rax) - 411538: e8 83 50 01 00 callq 4265c0 <__mempcpy> - 41153d: 4c 89 f7 mov %r14,%rdi - 411540: c6 00 00 movb $0x0,(%rax) - 411543: 48 87 3d d6 ab 2b 00 xchg %rdi,0x2babd6(%rip) # 6cc120 <__abort_msg> - 41154a: 48 85 ff test %rdi,%rdi - 41154d: 74 11 je 411560 <__libc_message.constprop.0+0x160> - 41154f: 8b 37 mov (%rdi),%esi - 411551: e8 5a e7 02 00 callq 43fcb0 <__munmap> - 411556: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41155d: 00 00 00 - 411560: 41 0f b6 f4 movzbl %r12b,%esi - 411564: 44 89 ea mov %r13d,%edx - 411567: bf 01 00 00 00 mov $0x1,%edi - 41156c: e8 1f ee fe ff callq 400390 - 411571: e8 8a c6 ff ff callq 40dc00 - 411576: 41 bc 02 00 00 00 mov $0x2,%r12d - 41157c: 41 bd 02 00 00 00 mov $0x2,%r13d - 411582: e9 f5 fe ff ff jmpq 41147c <__libc_message.constprop.0+0x7c> - 411587: 48 8b 55 90 mov -0x70(%rbp),%rdx - 41158b: 48 8d 42 08 lea 0x8(%rdx),%rax - 41158f: 48 89 45 90 mov %rax,-0x70(%rbp) - 411593: e9 fc fe ff ff jmpq 411494 <__libc_message.constprop.0+0x94> - 411598: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx - 41159f: f7 d8 neg %eax - 4115a1: 41 bc 02 00 00 00 mov $0x2,%r12d - 4115a7: 41 bd 02 00 00 00 mov $0x2,%r13d - 4115ad: 64 89 02 mov %eax,%fs:(%rdx) - 4115b0: e9 c7 fe ff ff jmpq 41147c <__libc_message.constprop.0+0x7c> - 4115b5: 90 nop - 4115b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4115bd: 00 00 00 - -00000000004115c0 <__libc_message>: - 4115c0: 55 push %rbp - 4115c1: 48 89 e5 mov %rsp,%rbp - 4115c4: 41 57 push %r15 - 4115c6: 41 56 push %r14 - 4115c8: 48 8d 45 10 lea 0x10(%rbp),%rax - 4115cc: 41 55 push %r13 - 4115ce: 41 54 push %r12 - 4115d0: 53 push %rbx - 4115d1: 41 89 ff mov %edi,%r15d - 4115d4: bf 14 1c 4a 00 mov $0x4a1c14,%edi - 4115d9: 48 89 f3 mov %rsi,%rbx - 4115dc: 48 83 ec 68 sub $0x68,%rsp - 4115e0: 48 89 45 90 mov %rax,-0x70(%rbp) - 4115e4: 48 8d 45 a0 lea -0x60(%rbp),%rax - 4115e8: 48 89 55 b0 mov %rdx,-0x50(%rbp) - 4115ec: 48 89 4d b8 mov %rcx,-0x48(%rbp) - 4115f0: 4c 89 45 c0 mov %r8,-0x40(%rbp) - 4115f4: 4c 89 4d c8 mov %r9,-0x38(%rbp) - 4115f8: c7 45 88 10 00 00 00 movl $0x10,-0x78(%rbp) - 4115ff: 48 89 45 98 mov %rax,-0x68(%rbp) - 411603: e8 98 03 04 00 callq 4519a0 <__libc_secure_getenv> - 411608: 48 85 c0 test %rax,%rax - 41160b: 74 09 je 411616 <__libc_message+0x56> - 41160d: 80 38 00 cmpb $0x0,(%rax) - 411610: 0f 85 81 01 00 00 jne 411797 <__libc_message+0x1d7> - 411616: be 02 09 00 00 mov $0x902,%esi - 41161b: bf 27 1c 4a 00 mov $0x4a1c27,%edi - 411620: b8 02 00 00 00 mov $0x2,%eax - 411625: 0f 05 syscall - 411627: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 41162d: 0f 87 58 01 00 00 ja 41178b <__libc_message+0x1cb> - 411633: 83 f8 ff cmp $0xffffffff,%eax - 411636: 89 85 7c ff ff ff mov %eax,-0x84(%rbp) - 41163c: 0f 84 55 01 00 00 je 411797 <__libc_message+0x1d7> - 411642: 44 0f b6 2b movzbl (%rbx),%r13d - 411646: 45 31 e4 xor %r12d,%r12d - 411649: 45 31 f6 xor %r14d,%r14d - 41164c: 45 84 ed test %r13b,%r13b - 41164f: 0f 84 5f 01 00 00 je 4117b4 <__libc_message+0x1f4> - 411655: 0f 1f 00 nopl (%rax) - 411658: 44 89 ea mov %r13d,%edx - 41165b: 48 89 d8 mov %rbx,%rax - 41165e: eb 15 jmp 411675 <__libc_message+0xb5> - 411660: 48 8d 78 01 lea 0x1(%rax),%rdi - 411664: be 25 00 00 00 mov $0x25,%esi - 411669: e8 72 b5 01 00 callq 42cbe0 <__strchrnul> - 41166e: 0f b6 10 movzbl (%rax),%edx - 411671: 84 d2 test %dl,%dl - 411673: 74 0b je 411680 <__libc_message+0xc0> - 411675: 80 fa 25 cmp $0x25,%dl - 411678: 75 e6 jne 411660 <__libc_message+0xa0> - 41167a: 80 78 01 73 cmpb $0x73,0x1(%rax) - 41167e: 75 e0 jne 411660 <__libc_message+0xa0> - 411680: 41 80 fd 25 cmp $0x25,%r13b - 411684: 74 3a je 4116c0 <__libc_message+0x100> - 411686: 48 89 c6 mov %rax,%rsi - 411689: 48 89 d9 mov %rbx,%rcx - 41168c: 48 29 de sub %rbx,%rsi - 41168f: 48 89 c3 mov %rax,%rbx - 411692: 48 83 ec 30 sub $0x30,%rsp - 411696: 45 8d 54 24 01 lea 0x1(%r12),%r10d - 41169b: 48 8d 54 24 0f lea 0xf(%rsp),%rdx - 4116a0: 48 83 e2 f0 and $0xfffffffffffffff0,%rdx - 4116a4: 48 89 0a mov %rcx,(%rdx) - 4116a7: 48 89 72 08 mov %rsi,0x8(%rdx) - 4116ab: 4c 89 72 10 mov %r14,0x10(%rdx) - 4116af: 44 0f b6 2b movzbl (%rbx),%r13d - 4116b3: 45 84 ed test %r13b,%r13b - 4116b6: 74 48 je 411700 <__libc_message+0x140> - 4116b8: 45 89 d4 mov %r10d,%r12d - 4116bb: 49 89 d6 mov %rdx,%r14 - 4116be: eb 98 jmp 411658 <__libc_message+0x98> - 4116c0: 80 7b 01 73 cmpb $0x73,0x1(%rbx) - 4116c4: 75 c0 jne 411686 <__libc_message+0xc6> - 4116c6: 8b 45 88 mov -0x78(%rbp),%eax - 4116c9: 83 f8 2f cmp $0x2f,%eax - 4116cc: 0f 87 ee 00 00 00 ja 4117c0 <__libc_message+0x200> - 4116d2: 89 c2 mov %eax,%edx - 4116d4: 48 03 55 98 add -0x68(%rbp),%rdx - 4116d8: 83 c0 08 add $0x8,%eax - 4116db: 89 45 88 mov %eax,-0x78(%rbp) - 4116de: 48 8b 0a mov (%rdx),%rcx - 4116e1: 48 83 c3 02 add $0x2,%rbx - 4116e5: 48 89 cf mov %rcx,%rdi - 4116e8: 48 89 8d 70 ff ff ff mov %rcx,-0x90(%rbp) - 4116ef: e8 5c 1f 01 00 callq 423650 - 4116f4: 48 8b 8d 70 ff ff ff mov -0x90(%rbp),%rcx - 4116fb: 48 89 c6 mov %rax,%rsi - 4116fe: eb 92 jmp 411692 <__libc_message+0xd2> - 411700: 4d 63 c2 movslq %r10d,%r8 - 411703: 49 63 d4 movslq %r12d,%rdx - 411706: 4c 89 c0 mov %r8,%rax - 411709: 48 c1 e2 04 shl $0x4,%rdx - 41170d: 48 c1 e0 04 shl $0x4,%rax - 411711: 48 83 c0 10 add $0x10,%rax - 411715: 48 29 c4 sub %rax,%rsp - 411718: 31 c0 xor %eax,%eax - 41171a: 4c 8d 6c 24 0f lea 0xf(%rsp),%r13 - 41171f: 49 83 e5 f0 and $0xfffffffffffffff0,%r13 - 411723: 4c 01 ea add %r13,%rdx - 411726: eb 17 jmp 41173f <__libc_message+0x17f> - 411728: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 41172f: 00 - 411730: 49 8b 0e mov (%r14),%rcx - 411733: 49 8b 76 08 mov 0x8(%r14),%rsi - 411737: 48 83 ea 10 sub $0x10,%rdx - 41173b: 4d 8b 76 10 mov 0x10(%r14),%r14 - 41173f: 48 8d 1c 30 lea (%rax,%rsi,1),%rbx - 411743: 49 39 d5 cmp %rdx,%r13 - 411746: 48 89 0a mov %rcx,(%rdx) - 411749: 48 89 72 08 mov %rsi,0x8(%rdx) - 41174d: 48 89 d8 mov %rbx,%rax - 411750: 75 de jne 411730 <__libc_message+0x170> - 411752: 4c 63 b5 7c ff ff ff movslq -0x84(%rbp),%r14 - 411759: 41 b9 14 00 00 00 mov $0x14,%r9d - 41175f: 90 nop - 411760: 4c 89 c2 mov %r8,%rdx - 411763: 4c 89 ee mov %r13,%rsi - 411766: 4c 89 f7 mov %r14,%rdi - 411769: 44 89 c8 mov %r9d,%eax - 41176c: 0f 05 syscall - 41176e: 48 83 f8 fc cmp $0xfffffffffffffffc,%rax - 411772: 49 89 c4 mov %rax,%r12 - 411775: 74 e9 je 411760 <__libc_message+0x1a0> - 411777: 45 85 ff test %r15d,%r15d - 41177a: 75 55 jne 4117d1 <__libc_message+0x211> - 41177c: 48 8d 65 d8 lea -0x28(%rbp),%rsp - 411780: 5b pop %rbx - 411781: 41 5c pop %r12 - 411783: 41 5d pop %r13 - 411785: 41 5e pop %r14 - 411787: 41 5f pop %r15 - 411789: 5d pop %rbp - 41178a: c3 retq - 41178b: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx - 411792: f7 d8 neg %eax - 411794: 64 89 02 mov %eax,%fs:(%rdx) - 411797: 44 0f b6 2b movzbl (%rbx),%r13d - 41179b: 45 31 e4 xor %r12d,%r12d - 41179e: 45 31 f6 xor %r14d,%r14d - 4117a1: c7 85 7c ff ff ff 02 movl $0x2,-0x84(%rbp) - 4117a8: 00 00 00 - 4117ab: 45 84 ed test %r13b,%r13b - 4117ae: 0f 85 a4 fe ff ff jne 411658 <__libc_message+0x98> - 4117b4: 45 85 ff test %r15d,%r15d - 4117b7: 74 c3 je 41177c <__libc_message+0x1bc> - 4117b9: 31 f6 xor %esi,%esi - 4117bb: e9 b3 00 00 00 jmpq 411873 <__libc_message+0x2b3> - 4117c0: 48 8b 55 90 mov -0x70(%rbp),%rdx - 4117c4: 48 8d 42 08 lea 0x8(%rdx),%rax - 4117c8: 48 89 45 90 mov %rax,-0x70(%rbp) - 4117cc: e9 0d ff ff ff jmpq 4116de <__libc_message+0x11e> - 4117d1: 48 8b 05 a8 99 2b 00 mov 0x2b99a8(%rip),%rax # 6cb180 <_dl_pagesize> - 4117d8: 45 31 c9 xor %r9d,%r9d - 4117db: 31 ff xor %edi,%edi - 4117dd: 41 b8 ff ff ff ff mov $0xffffffff,%r8d - 4117e3: b9 22 00 00 00 mov $0x22,%ecx - 4117e8: ba 03 00 00 00 mov $0x3,%edx - 4117ed: 44 89 95 78 ff ff ff mov %r10d,-0x88(%rbp) - 4117f4: 4c 8d 1c 03 lea (%rbx,%rax,1),%r11 - 4117f8: 48 f7 d8 neg %rax - 4117fb: 49 21 c3 and %rax,%r11 - 4117fe: 4c 89 de mov %r11,%rsi - 411801: 4d 89 de mov %r11,%r14 - 411804: e8 e7 e3 02 00 callq 43fbf0 <__mmap> - 411809: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 41180d: 48 89 85 70 ff ff ff mov %rax,-0x90(%rbp) - 411814: 74 54 je 41186a <__libc_message+0x2aa> - 411816: 44 8b 95 78 ff ff ff mov -0x88(%rbp),%r10d - 41181d: 44 89 30 mov %r14d,(%rax) - 411820: 4d 8d 75 08 lea 0x8(%r13),%r14 - 411824: 48 83 c0 04 add $0x4,%rax - 411828: 41 8d 52 ff lea -0x1(%r10),%edx - 41182c: 48 c1 e2 04 shl $0x4,%rdx - 411830: 4d 8d 6c 15 18 lea 0x18(%r13,%rdx,1),%r13 - 411835: 49 8b 76 f8 mov -0x8(%r14),%rsi - 411839: 49 8b 16 mov (%r14),%rdx - 41183c: 48 89 c7 mov %rax,%rdi - 41183f: 49 83 c6 10 add $0x10,%r14 - 411843: e8 78 4d 01 00 callq 4265c0 <__mempcpy> - 411848: 4d 39 ee cmp %r13,%r14 - 41184b: 75 e8 jne 411835 <__libc_message+0x275> - 41184d: c6 00 00 movb $0x0,(%rax) - 411850: 48 8b bd 70 ff ff ff mov -0x90(%rbp),%rdi - 411857: 48 87 3d c2 a8 2b 00 xchg %rdi,0x2ba8c2(%rip) # 6cc120 <__abort_msg> - 41185e: 48 85 ff test %rdi,%rdi - 411861: 74 07 je 41186a <__libc_message+0x2aa> - 411863: 8b 37 mov (%rdi),%esi - 411865: e8 46 e4 02 00 callq 43fcb0 <__munmap> - 41186a: 31 f6 xor %esi,%esi - 41186c: 4c 39 e3 cmp %r12,%rbx - 41186f: 40 0f 94 c6 sete %sil - 411873: 8b 95 7c ff ff ff mov -0x84(%rbp),%edx - 411879: 44 89 ff mov %r15d,%edi - 41187c: e8 0f eb fe ff callq 400390 - 411881: e8 7a c3 ff ff callq 40dc00 - 411886: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41188d: 00 00 00 - -0000000000411890 <__libc_fatal>: - 411890: 48 89 fa mov %rdi,%rdx - 411893: 48 83 ec 08 sub $0x8,%rsp - 411897: be 99 c4 4b 00 mov $0x4bc499,%esi - 41189c: bf 01 00 00 00 mov $0x1,%edi - 4118a1: 31 c0 xor %eax,%eax - 4118a3: e8 58 fb ff ff callq 411400 <__libc_message.constprop.0> - 4118a8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 4118af: 00 - -00000000004118b0 <__fgets_unlocked>: - 4118b0: 85 f6 test %esi,%esi - 4118b2: 0f 8e 88 00 00 00 jle 411940 <__fgets_unlocked+0x90> - 4118b8: 83 fe 01 cmp $0x1,%esi - 4118bb: 41 54 push %r12 - 4118bd: 55 push %rbp - 4118be: 53 push %rbx - 4118bf: 48 89 fb mov %rdi,%rbx - 4118c2: 74 6c je 411930 <__fgets_unlocked+0x80> - 4118c4: 8b 02 mov (%rdx),%eax - 4118c6: 48 89 d5 mov %rdx,%rbp - 4118c9: 83 ee 01 sub $0x1,%esi - 4118cc: 41 b8 01 00 00 00 mov $0x1,%r8d - 4118d2: b9 0a 00 00 00 mov $0xa,%ecx - 4118d7: 41 89 c4 mov %eax,%r12d - 4118da: 83 e0 df and $0xffffffdf,%eax - 4118dd: 89 02 mov %eax,(%rdx) - 4118df: 48 63 d6 movslq %esi,%rdx - 4118e2: 48 89 fe mov %rdi,%rsi - 4118e5: 48 89 ef mov %rbp,%rdi - 4118e8: 41 83 e4 20 and $0x20,%r12d - 4118ec: e8 1f 1b 05 00 callq 463410 <_IO_getline> - 4118f1: 48 85 c0 test %rax,%rax - 4118f4: 8b 55 00 mov 0x0(%rbp),%edx - 4118f7: 75 17 jne 411910 <__fgets_unlocked+0x60> - 4118f9: 31 db xor %ebx,%ebx - 4118fb: 41 09 d4 or %edx,%r12d - 4118fe: 48 89 d8 mov %rbx,%rax - 411901: 44 89 65 00 mov %r12d,0x0(%rbp) - 411905: 5b pop %rbx - 411906: 5d pop %rbp - 411907: 41 5c pop %r12 - 411909: c3 retq - 41190a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 411910: f6 c2 20 test $0x20,%dl - 411913: 74 0d je 411922 <__fgets_unlocked+0x72> - 411915: 48 c7 c1 d0 ff ff ff mov $0xffffffffffffffd0,%rcx - 41191c: 64 83 39 0b cmpl $0xb,%fs:(%rcx) - 411920: 75 d7 jne 4118f9 <__fgets_unlocked+0x49> - 411922: c6 04 03 00 movb $0x0,(%rbx,%rax,1) - 411926: 8b 55 00 mov 0x0(%rbp),%edx - 411929: eb d0 jmp 4118fb <__fgets_unlocked+0x4b> - 41192b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 411930: c6 07 00 movb $0x0,(%rdi) - 411933: 48 89 f8 mov %rdi,%rax - 411936: eb cd jmp 411905 <__fgets_unlocked+0x55> - 411938: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 41193f: 00 - 411940: 31 c0 xor %eax,%eax - 411942: c3 retq - 411943: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41194a: 00 00 00 - 41194d: 0f 1f 00 nopl (%rax) - -0000000000411950 <_IO_file_seekoff_maybe_mmap>: - 411950: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax - 411957: 53 push %rbx - 411958: 48 89 fb mov %rdi,%rbx - 41195b: ff 90 80 00 00 00 callq *0x80(%rax) - 411961: 48 85 c0 test %rax,%rax - 411964: 78 0a js 411970 <_IO_file_seekoff_maybe_mmap+0x20> - 411966: 48 89 83 90 00 00 00 mov %rax,0x90(%rbx) - 41196d: 5b pop %rbx - 41196e: c3 retq - 41196f: 90 nop - 411970: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax - 411977: 5b pop %rbx - 411978: c3 retq - 411979: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - -0000000000411980 <_IO_file_close>: - 411980: 48 63 7f 70 movslq 0x70(%rdi),%rdi - 411984: b8 03 00 00 00 mov $0x3,%eax - 411989: 0f 05 syscall - 41198b: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 411991: 76 11 jbe 4119a4 <_IO_file_close+0x24> - 411993: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx - 41199a: f7 d8 neg %eax - 41199c: 64 89 02 mov %eax,%fs:(%rdx) - 41199f: b8 ff ff ff ff mov $0xffffffff,%eax - 4119a4: f3 c3 repz retq - 4119a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4119ad: 00 00 00 - -00000000004119b0 <_IO_new_file_setbuf>: - 4119b0: 53 push %rbx - 4119b1: 48 89 fb mov %rdi,%rbx - 4119b4: e8 37 38 00 00 callq 4151f0 <_IO_default_setbuf> - 4119b9: 48 85 c0 test %rax,%rax - 4119bc: 74 1f je 4119dd <_IO_new_file_setbuf+0x2d> - 4119be: 48 8b 43 38 mov 0x38(%rbx),%rax - 4119c2: 48 89 43 30 mov %rax,0x30(%rbx) - 4119c6: 48 89 43 28 mov %rax,0x28(%rbx) - 4119ca: 48 89 43 20 mov %rax,0x20(%rbx) - 4119ce: 48 89 43 18 mov %rax,0x18(%rbx) - 4119d2: 48 89 43 08 mov %rax,0x8(%rbx) - 4119d6: 48 89 43 10 mov %rax,0x10(%rbx) - 4119da: 48 89 d8 mov %rbx,%rax - 4119dd: 5b pop %rbx - 4119de: c3 retq - 4119df: 90 nop - -00000000004119e0 <_IO_file_setbuf_mmap>: - 4119e0: 48 8b 87 a0 00 00 00 mov 0xa0(%rdi),%rax - 4119e7: 53 push %rbx - 4119e8: 48 89 fb mov %rdi,%rbx - 4119eb: 48 c7 87 d8 00 00 00 movq $0x4a1e20,0xd8(%rdi) - 4119f2: 20 1e 4a 00 - 4119f6: 48 c7 80 30 01 00 00 movq $0x4a1b20,0x130(%rax) - 4119fd: 20 1b 4a 00 - 411a01: e8 ea 37 00 00 callq 4151f0 <_IO_default_setbuf> - 411a06: 48 85 c0 test %rax,%rax - 411a09: 74 25 je 411a30 <_IO_file_setbuf_mmap+0x50> - 411a0b: 48 8b 43 38 mov 0x38(%rbx),%rax - 411a0f: 48 89 43 30 mov %rax,0x30(%rbx) - 411a13: 48 89 43 28 mov %rax,0x28(%rbx) - 411a17: 48 89 43 20 mov %rax,0x20(%rbx) - 411a1b: 48 89 43 18 mov %rax,0x18(%rbx) - 411a1f: 48 89 43 08 mov %rax,0x8(%rbx) - 411a23: 48 89 43 10 mov %rax,0x10(%rbx) - 411a27: 48 89 d8 mov %rbx,%rax - 411a2a: 5b pop %rbx - 411a2b: c3 retq - 411a2c: 0f 1f 40 00 nopl 0x0(%rax) - 411a30: 48 8b 93 a0 00 00 00 mov 0xa0(%rbx),%rdx - 411a37: 48 c7 83 d8 00 00 00 movq $0x4a1d60,0xd8(%rbx) - 411a3e: 60 1d 4a 00 - 411a42: 48 c7 82 30 01 00 00 movq $0x4a1a60,0x130(%rdx) - 411a49: 60 1a 4a 00 - 411a4d: 5b pop %rbx - 411a4e: c3 retq - 411a4f: 90 nop - -0000000000411a50 <_IO_new_file_underflow>: - 411a50: 8b 07 mov (%rdi),%eax - 411a52: a8 04 test $0x4,%al - 411a54: 0f 85 16 02 00 00 jne 411c70 <_IO_new_file_underflow+0x220> - 411a5a: 48 8b 57 08 mov 0x8(%rdi),%rdx - 411a5e: 48 3b 57 10 cmp 0x10(%rdi),%rdx - 411a62: 0f 82 68 01 00 00 jb 411bd0 <_IO_new_file_underflow+0x180> - 411a68: 55 push %rbp - 411a69: 53 push %rbx - 411a6a: 48 89 fb mov %rdi,%rbx - 411a6d: 48 83 ec 08 sub $0x8,%rsp - 411a71: 48 83 7f 38 00 cmpq $0x0,0x38(%rdi) - 411a76: 0f 84 b4 01 00 00 je 411c30 <_IO_new_file_underflow+0x1e0> - 411a7c: a9 02 02 00 00 test $0x202,%eax - 411a81: 0f 84 d9 00 00 00 je 411b60 <_IO_new_file_underflow+0x110> - 411a87: 48 8b 2d b2 8c 2b 00 mov 0x2b8cb2(%rip),%rbp # 6ca740 <_IO_stdout> - 411a8e: 8b 55 00 mov 0x0(%rbp),%edx - 411a91: 89 d0 mov %edx,%eax - 411a93: 25 00 80 00 00 and $0x8000,%eax - 411a98: 0f 85 3a 01 00 00 jne 411bd8 <_IO_new_file_underflow+0x188> - 411a9e: 4c 8b 85 88 00 00 00 mov 0x88(%rbp),%r8 - 411aa5: 64 4c 8b 0c 25 10 00 mov %fs:0x10,%r9 - 411aac: 00 00 - 411aae: 4d 3b 48 08 cmp 0x8(%r8),%r9 - 411ab2: 0f 84 a8 01 00 00 je 411c60 <_IO_new_file_underflow+0x210> - 411ab8: be 01 00 00 00 mov $0x1,%esi - 411abd: 83 3d f8 b6 2b 00 00 cmpl $0x0,0x2bb6f8(%rip) # 6cd1bc <__libc_multiple_threads> - 411ac4: 74 09 je 411acf <_IO_new_file_underflow+0x7f> - 411ac6: f0 41 0f b1 30 lock cmpxchg %esi,(%r8) - 411acb: 75 08 jne 411ad5 <_IO_new_file_underflow+0x85> - 411acd: eb 1c jmp 411aeb <_IO_new_file_underflow+0x9b> - 411acf: 41 0f b1 30 cmpxchg %esi,(%r8) - 411ad3: 74 16 je 411aeb <_IO_new_file_underflow+0x9b> - 411ad5: 49 8d 38 lea (%r8),%rdi - 411ad8: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 411adf: e8 ec 0a 03 00 callq 4425d0 <__lll_lock_wait_private> - 411ae4: 48 81 c4 80 00 00 00 add $0x80,%rsp - 411aeb: 48 8b 3d 4e 8c 2b 00 mov 0x2b8c4e(%rip),%rdi # 6ca740 <_IO_stdout> - 411af2: 4c 8b 85 88 00 00 00 mov 0x88(%rbp),%r8 - 411af9: 8b 17 mov (%rdi),%edx - 411afb: 4d 89 48 08 mov %r9,0x8(%r8) - 411aff: 81 e2 88 02 00 00 and $0x288,%edx - 411b05: 41 83 40 04 01 addl $0x1,0x4(%r8) - 411b0a: 81 fa 80 02 00 00 cmp $0x280,%edx - 411b10: 0f 84 d7 00 00 00 je 411bed <_IO_new_file_underflow+0x19d> - 411b16: f7 45 00 00 80 00 00 testl $0x8000,0x0(%rbp) - 411b1d: 75 41 jne 411b60 <_IO_new_file_underflow+0x110> - 411b1f: 48 8b 95 88 00 00 00 mov 0x88(%rbp),%rdx - 411b26: 83 6a 04 01 subl $0x1,0x4(%rdx) - 411b2a: 75 34 jne 411b60 <_IO_new_file_underflow+0x110> - 411b2c: 48 c7 42 08 00 00 00 movq $0x0,0x8(%rdx) - 411b33: 00 - 411b34: 83 3d 81 b6 2b 00 00 cmpl $0x0,0x2bb681(%rip) # 6cd1bc <__libc_multiple_threads> - 411b3b: 74 07 je 411b44 <_IO_new_file_underflow+0xf4> - 411b3d: f0 ff 0a lock decl (%rdx) - 411b40: 75 06 jne 411b48 <_IO_new_file_underflow+0xf8> - 411b42: eb 1a jmp 411b5e <_IO_new_file_underflow+0x10e> - 411b44: ff 0a decl (%rdx) - 411b46: 74 16 je 411b5e <_IO_new_file_underflow+0x10e> - 411b48: 48 8d 3a lea (%rdx),%rdi - 411b4b: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 411b52: e8 a9 0a 03 00 callq 442600 <__lll_unlock_wake_private> - 411b57: 48 81 c4 80 00 00 00 add $0x80,%rsp - 411b5e: 66 90 xchg %ax,%ax - 411b60: 48 89 df mov %rbx,%rdi - 411b63: e8 58 2e 00 00 callq 4149c0 <_IO_switch_to_get_mode> - 411b68: 48 8b 73 38 mov 0x38(%rbx),%rsi - 411b6c: 48 8b 53 40 mov 0x40(%rbx),%rdx - 411b70: 48 89 df mov %rbx,%rdi - 411b73: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 411b7a: 48 29 f2 sub %rsi,%rdx - 411b7d: 48 89 73 08 mov %rsi,0x8(%rbx) - 411b81: 48 89 73 18 mov %rsi,0x18(%rbx) - 411b85: 48 89 73 10 mov %rsi,0x10(%rbx) - 411b89: 48 89 73 30 mov %rsi,0x30(%rbx) - 411b8d: 48 89 73 28 mov %rsi,0x28(%rbx) - 411b91: 48 89 73 20 mov %rsi,0x20(%rbx) - 411b95: ff 50 70 callq *0x70(%rax) - 411b98: 48 83 f8 00 cmp $0x0,%rax - 411b9c: 7e 6a jle 411c08 <_IO_new_file_underflow+0x1b8> - 411b9e: 48 8b 93 90 00 00 00 mov 0x90(%rbx),%rdx - 411ba5: 48 01 43 10 add %rax,0x10(%rbx) - 411ba9: 48 83 fa ff cmp $0xffffffffffffffff,%rdx - 411bad: 74 0a je 411bb9 <_IO_new_file_underflow+0x169> - 411baf: 48 01 c2 add %rax,%rdx - 411bb2: 48 89 93 90 00 00 00 mov %rdx,0x90(%rbx) - 411bb9: 48 8b 43 08 mov 0x8(%rbx),%rax - 411bbd: 0f b6 00 movzbl (%rax),%eax - 411bc0: 48 83 c4 08 add $0x8,%rsp - 411bc4: 5b pop %rbx - 411bc5: 5d pop %rbp - 411bc6: c3 retq - 411bc7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 411bce: 00 00 - 411bd0: 0f b6 02 movzbl (%rdx),%eax - 411bd3: c3 retq - 411bd4: 0f 1f 40 00 nopl 0x0(%rax) - 411bd8: 81 e2 88 02 00 00 and $0x288,%edx - 411bde: 81 fa 80 02 00 00 cmp $0x280,%edx - 411be4: 0f 85 76 ff ff ff jne 411b60 <_IO_new_file_underflow+0x110> - 411bea: 48 89 ef mov %rbp,%rdi - 411bed: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax - 411bf4: be ff ff ff ff mov $0xffffffff,%esi - 411bf9: ff 50 18 callq *0x18(%rax) - 411bfc: e9 15 ff ff ff jmpq 411b16 <_IO_new_file_underflow+0xc6> - 411c01: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 411c08: 8b 03 mov (%rbx),%eax - 411c0a: 75 4c jne 411c58 <_IO_new_file_underflow+0x208> - 411c0c: 83 c8 10 or $0x10,%eax - 411c0f: 89 03 mov %eax,(%rbx) - 411c11: 48 c7 83 90 00 00 00 movq $0xffffffffffffffff,0x90(%rbx) - 411c18: ff ff ff ff - 411c1c: 48 83 c4 08 add $0x8,%rsp - 411c20: b8 ff ff ff ff mov $0xffffffff,%eax - 411c25: 5b pop %rbx - 411c26: 5d pop %rbp - 411c27: c3 retq - 411c28: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 411c2f: 00 - 411c30: 48 8b 7f 48 mov 0x48(%rdi),%rdi - 411c34: 48 85 ff test %rdi,%rdi - 411c37: 74 0b je 411c44 <_IO_new_file_underflow+0x1f4> - 411c39: e8 72 c1 00 00 callq 41ddb0 <__cfree> - 411c3e: 81 23 ff fe ff ff andl $0xfffffeff,(%rbx) - 411c44: 48 89 df mov %rbx,%rdi - 411c47: e8 b4 31 00 00 callq 414e00 <_IO_doallocbuf> - 411c4c: 8b 03 mov (%rbx),%eax - 411c4e: e9 29 fe ff ff jmpq 411a7c <_IO_new_file_underflow+0x2c> - 411c53: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 411c58: 83 c8 20 or $0x20,%eax - 411c5b: eb b2 jmp 411c0f <_IO_new_file_underflow+0x1bf> - 411c5d: 0f 1f 00 nopl (%rax) - 411c60: 48 89 ef mov %rbp,%rdi - 411c63: e9 97 fe ff ff jmpq 411aff <_IO_new_file_underflow+0xaf> - 411c68: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 411c6f: 00 - 411c70: 83 c8 20 or $0x20,%eax - 411c73: 89 07 mov %eax,(%rdi) - 411c75: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 411c7c: 64 c7 00 09 00 00 00 movl $0x9,%fs:(%rax) - 411c83: b8 ff ff ff ff mov $0xffffffff,%eax - 411c88: c3 retq - 411c89: f7 45 00 00 80 00 00 testl $0x8000,0x0(%rbp) - 411c90: 48 89 c6 mov %rax,%rsi - 411c93: 75 3f jne 411cd4 <_IO_new_file_underflow+0x284> - 411c95: 48 8b 95 88 00 00 00 mov 0x88(%rbp),%rdx - 411c9c: 83 6a 04 01 subl $0x1,0x4(%rdx) - 411ca0: 75 32 jne 411cd4 <_IO_new_file_underflow+0x284> - 411ca2: 48 c7 42 08 00 00 00 movq $0x0,0x8(%rdx) - 411ca9: 00 - 411caa: 83 3d 0b b5 2b 00 00 cmpl $0x0,0x2bb50b(%rip) # 6cd1bc <__libc_multiple_threads> - 411cb1: 74 07 je 411cba <_IO_new_file_underflow+0x26a> - 411cb3: f0 ff 0a lock decl (%rdx) - 411cb6: 75 06 jne 411cbe <_IO_new_file_underflow+0x26e> - 411cb8: eb 1a jmp 411cd4 <_IO_new_file_underflow+0x284> - 411cba: ff 0a decl (%rdx) - 411cbc: 74 16 je 411cd4 <_IO_new_file_underflow+0x284> - 411cbe: 48 8d 3a lea (%rdx),%rdi - 411cc1: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 411cc8: e8 33 09 03 00 callq 442600 <__lll_unlock_wake_private> - 411ccd: 48 81 c4 80 00 00 00 add $0x80,%rsp - 411cd4: 48 89 f7 mov %rsi,%rdi - 411cd7: e8 94 a8 08 00 callq 49c570 <_Unwind_Resume> - 411cdc: 0f 1f 40 00 nopl 0x0(%rax) - -0000000000411ce0 <_IO_new_file_seekoff>: - 411ce0: 41 56 push %r14 - 411ce2: 41 55 push %r13 - 411ce4: 41 54 push %r12 - 411ce6: 55 push %rbp - 411ce7: 53 push %rbx - 411ce8: 48 89 fb mov %rdi,%rbx - 411ceb: 48 81 ec 90 00 00 00 sub $0x90,%rsp - 411cf2: 85 c9 test %ecx,%ecx - 411cf4: 0f 84 d6 02 00 00 je 411fd0 <_IO_new_file_seekoff+0x2f0> - 411cfa: 48 8b 47 10 mov 0x10(%rdi),%rax - 411cfe: 48 39 47 18 cmp %rax,0x18(%rdi) - 411d02: 48 89 f5 mov %rsi,%rbp - 411d05: 41 89 d4 mov %edx,%r12d - 411d08: 0f 84 ca 00 00 00 je 411dd8 <_IO_new_file_seekoff+0xf8> - 411d0e: 48 8b 57 28 mov 0x28(%rdi),%rdx - 411d12: 48 8b 47 20 mov 0x20(%rdi),%rax - 411d16: 45 31 ed xor %r13d,%r13d - 411d19: 48 39 c2 cmp %rax,%rdx - 411d1c: 0f 86 ce 00 00 00 jbe 411df0 <_IO_new_file_seekoff+0x110> - 411d22: 48 89 df mov %rbx,%rdi - 411d25: e8 96 2c 00 00 callq 4149c0 <_IO_switch_to_get_mode> - 411d2a: 85 c0 test %eax,%eax - 411d2c: 0f 85 06 03 00 00 jne 412038 <_IO_new_file_seekoff+0x358> - 411d32: 48 83 7b 38 00 cmpq $0x0,0x38(%rbx) - 411d37: 0f 84 ca 00 00 00 je 411e07 <_IO_new_file_seekoff+0x127> - 411d3d: 41 83 fc 01 cmp $0x1,%r12d - 411d41: 0f 84 09 01 00 00 je 411e50 <_IO_new_file_seekoff+0x170> - 411d47: 41 83 fc 02 cmp $0x2,%r12d - 411d4b: 0f 85 bf 01 00 00 jne 411f10 <_IO_new_file_seekoff+0x230> - 411d51: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 411d58: 48 89 e6 mov %rsp,%rsi - 411d5b: 48 89 df mov %rbx,%rdi - 411d5e: ff 90 90 00 00 00 callq *0x90(%rax) - 411d64: 85 c0 test %eax,%eax - 411d66: 0f 84 84 01 00 00 je 411ef0 <_IO_new_file_seekoff+0x210> - 411d6c: 48 89 df mov %rbx,%rdi - 411d6f: e8 2c 46 00 00 callq 4163a0 <_IO_unsave_markers> - 411d74: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 411d7b: 48 89 ee mov %rbp,%rsi - 411d7e: 48 c7 c5 ff ff ff ff mov $0xffffffffffffffff,%rbp - 411d85: 44 89 e2 mov %r12d,%edx - 411d88: 48 89 df mov %rbx,%rdi - 411d8b: ff 90 80 00 00 00 callq *0x80(%rax) - 411d91: 48 39 e8 cmp %rbp,%rax - 411d94: 74 29 je 411dbf <_IO_new_file_seekoff+0xdf> - 411d96: 48 8b 53 38 mov 0x38(%rbx),%rdx - 411d9a: 83 23 ef andl $0xffffffef,(%rbx) - 411d9d: 48 89 c5 mov %rax,%rbp - 411da0: 48 89 83 90 00 00 00 mov %rax,0x90(%rbx) - 411da7: 48 89 53 18 mov %rdx,0x18(%rbx) - 411dab: 48 89 53 08 mov %rdx,0x8(%rbx) - 411daf: 48 89 53 10 mov %rdx,0x10(%rbx) - 411db3: 48 89 53 28 mov %rdx,0x28(%rbx) - 411db7: 48 89 53 20 mov %rdx,0x20(%rbx) - 411dbb: 48 89 53 30 mov %rdx,0x30(%rbx) - 411dbf: 48 81 c4 90 00 00 00 add $0x90,%rsp - 411dc6: 48 89 e8 mov %rbp,%rax - 411dc9: 5b pop %rbx - 411dca: 5d pop %rbp - 411dcb: 41 5c pop %r12 - 411dcd: 41 5d pop %r13 - 411dcf: 41 5e pop %r14 - 411dd1: c3 retq - 411dd2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 411dd8: 48 8b 47 20 mov 0x20(%rdi),%rax - 411ddc: 48 8b 57 28 mov 0x28(%rdi),%rdx - 411de0: 48 39 d0 cmp %rdx,%rax - 411de3: 0f 85 2d ff ff ff jne 411d16 <_IO_new_file_seekoff+0x36> - 411de9: 41 bd 01 00 00 00 mov $0x1,%r13d - 411def: 90 nop - 411df0: f7 03 00 08 00 00 testl $0x800,(%rbx) - 411df6: 0f 85 26 ff ff ff jne 411d22 <_IO_new_file_seekoff+0x42> - 411dfc: 48 83 7b 38 00 cmpq $0x0,0x38(%rbx) - 411e01: 0f 85 36 ff ff ff jne 411d3d <_IO_new_file_seekoff+0x5d> - 411e07: 48 8b 7b 18 mov 0x18(%rbx),%rdi - 411e0b: 48 85 ff test %rdi,%rdi - 411e0e: 74 0b je 411e1b <_IO_new_file_seekoff+0x13b> - 411e10: e8 9b bf 00 00 callq 41ddb0 <__cfree> - 411e15: 81 23 ff fe ff ff andl $0xfffffeff,(%rbx) - 411e1b: 48 89 df mov %rbx,%rdi - 411e1e: e8 dd 2f 00 00 callq 414e00 <_IO_doallocbuf> - 411e23: 48 8b 43 38 mov 0x38(%rbx),%rax - 411e27: 41 83 fc 01 cmp $0x1,%r12d - 411e2b: 48 89 43 28 mov %rax,0x28(%rbx) - 411e2f: 48 89 43 20 mov %rax,0x20(%rbx) - 411e33: 48 89 43 30 mov %rax,0x30(%rbx) - 411e37: 48 89 43 18 mov %rax,0x18(%rbx) - 411e3b: 48 89 43 08 mov %rax,0x8(%rbx) - 411e3f: 48 89 43 10 mov %rax,0x10(%rbx) - 411e43: 0f 85 fe fe ff ff jne 411d47 <_IO_new_file_seekoff+0x67> - 411e49: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 411e50: 48 8b 43 10 mov 0x10(%rbx),%rax - 411e54: 48 2b 43 08 sub 0x8(%rbx),%rax - 411e58: 48 8b b3 90 00 00 00 mov 0x90(%rbx),%rsi - 411e5f: 48 29 c5 sub %rax,%rbp - 411e62: 48 83 fe ff cmp $0xffffffffffffffff,%rsi - 411e66: 0f 84 00 ff ff ff je 411d6c <_IO_new_file_seekoff+0x8c> - 411e6c: 48 01 f5 add %rsi,%rbp - 411e6f: 0f 88 ae 01 00 00 js 412023 <_IO_new_file_seekoff+0x343> - 411e75: 45 31 e4 xor %r12d,%r12d - 411e78: 48 83 7b 18 00 cmpq $0x0,0x18(%rbx) - 411e7d: 8b 03 mov (%rbx),%eax - 411e7f: 0f 84 9e 00 00 00 je 411f23 <_IO_new_file_seekoff+0x243> - 411e85: f6 c4 01 test $0x1,%ah - 411e88: 0f 85 95 00 00 00 jne 411f23 <_IO_new_file_seekoff+0x243> - 411e8e: 48 8b 53 38 mov 0x38(%rbx),%rdx - 411e92: 48 89 d1 mov %rdx,%rcx - 411e95: 48 2b 4b 10 sub 0x10(%rbx),%rcx - 411e99: 48 01 f1 add %rsi,%rcx - 411e9c: 48 39 e9 cmp %rbp,%rcx - 411e9f: 0f 8f 7e 00 00 00 jg 411f23 <_IO_new_file_seekoff+0x243> - 411ea5: 48 39 f5 cmp %rsi,%rbp - 411ea8: 7d 79 jge 411f23 <_IO_new_file_seekoff+0x243> - 411eaa: 48 89 ef mov %rbp,%rdi - 411ead: 83 e0 ef and $0xffffffef,%eax - 411eb0: 48 89 53 18 mov %rdx,0x18(%rbx) - 411eb4: 48 29 cf sub %rcx,%rdi - 411eb7: 48 89 53 28 mov %rdx,0x28(%rbx) - 411ebb: 48 89 53 20 mov %rdx,0x20(%rbx) - 411ebf: 48 89 f9 mov %rdi,%rcx - 411ec2: 48 89 53 30 mov %rdx,0x30(%rbx) - 411ec6: 89 03 mov %eax,(%rbx) - 411ec8: 48 01 d1 add %rdx,%rcx - 411ecb: 48 85 f6 test %rsi,%rsi - 411ece: 48 89 4b 08 mov %rcx,0x8(%rbx) - 411ed2: 0f 88 e7 fe ff ff js 411dbf <_IO_new_file_seekoff+0xdf> - 411ed8: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 411edf: 31 d2 xor %edx,%edx - 411ee1: 48 89 df mov %rbx,%rdi - 411ee4: ff 90 80 00 00 00 callq *0x80(%rax) - 411eea: e9 d0 fe ff ff jmpq 411dbf <_IO_new_file_seekoff+0xdf> - 411eef: 90 nop - 411ef0: 8b 44 24 18 mov 0x18(%rsp),%eax - 411ef4: 25 00 f0 00 00 and $0xf000,%eax - 411ef9: 3d 00 80 00 00 cmp $0x8000,%eax - 411efe: 0f 85 68 fe ff ff jne 411d6c <_IO_new_file_seekoff+0x8c> - 411f04: 48 03 6c 24 30 add 0x30(%rsp),%rbp - 411f09: 45 31 e4 xor %r12d,%r12d - 411f0c: 0f 1f 40 00 nopl 0x0(%rax) - 411f10: 48 8b b3 90 00 00 00 mov 0x90(%rbx),%rsi - 411f17: 48 83 fe ff cmp $0xffffffffffffffff,%rsi - 411f1b: 0f 85 57 ff ff ff jne 411e78 <_IO_new_file_seekoff+0x198> - 411f21: 8b 03 mov (%rbx),%eax - 411f23: a8 04 test $0x4,%al - 411f25: 0f 85 41 fe ff ff jne 411d6c <_IO_new_file_seekoff+0x8c> - 411f2b: 48 8b 53 38 mov 0x38(%rbx),%rdx - 411f2f: 48 8b 43 40 mov 0x40(%rbx),%rax - 411f33: 49 89 ec mov %rbp,%r12 - 411f36: 48 89 d6 mov %rdx,%rsi - 411f39: 48 29 c6 sub %rax,%rsi - 411f3c: 48 29 d0 sub %rdx,%rax - 411f3f: ba 00 00 00 00 mov $0x0,%edx - 411f44: 48 21 ee and %rbp,%rsi - 411f47: 49 29 f4 sub %rsi,%r12 - 411f4a: 49 39 c4 cmp %rax,%r12 - 411f4d: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 411f54: 0f 8f ee 00 00 00 jg 412048 <_IO_new_file_seekoff+0x368> - 411f5a: 48 89 df mov %rbx,%rdi - 411f5d: ff 90 80 00 00 00 callq *0x80(%rax) - 411f63: 48 85 c0 test %rax,%rax - 411f66: 49 89 c6 mov %rax,%r14 - 411f69: 0f 88 c9 00 00 00 js 412038 <_IO_new_file_seekoff+0x358> - 411f6f: 4d 85 e4 test %r12,%r12 - 411f72: 0f 84 e4 00 00 00 je 41205c <_IO_new_file_seekoff+0x37c> - 411f78: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 411f7f: 45 85 ed test %r13d,%r13d - 411f82: 48 8b 73 38 mov 0x38(%rbx),%rsi - 411f86: 4c 89 e2 mov %r12,%rdx - 411f89: 48 8b 40 70 mov 0x70(%rax),%rax - 411f8d: 75 07 jne 411f96 <_IO_new_file_seekoff+0x2b6> - 411f8f: 48 8b 53 40 mov 0x40(%rbx),%rdx - 411f93: 48 29 f2 sub %rsi,%rdx - 411f96: 48 89 df mov %rbx,%rdi - 411f99: ff d0 callq *%rax - 411f9b: 49 39 c4 cmp %rax,%r12 - 411f9e: 48 89 c1 mov %rax,%rcx - 411fa1: 0f 8e bc 00 00 00 jle 412063 <_IO_new_file_seekoff+0x383> - 411fa7: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 411fab: 4c 89 e5 mov %r12,%rbp - 411fae: 41 bc 01 00 00 00 mov $0x1,%r12d - 411fb4: 0f 84 b2 fd ff ff je 411d6c <_IO_new_file_seekoff+0x8c> - 411fba: 48 29 c5 sub %rax,%rbp - 411fbd: 41 bc 01 00 00 00 mov $0x1,%r12d - 411fc3: e9 a4 fd ff ff jmpq 411d6c <_IO_new_file_seekoff+0x8c> - 411fc8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 411fcf: 00 - 411fd0: 48 83 7f 38 00 cmpq $0x0,0x38(%rdi) - 411fd5: 0f 84 1d 01 00 00 je 4120f8 <_IO_new_file_seekoff+0x418> - 411fdb: 4c 8b 6f 28 mov 0x28(%rdi),%r13 - 411fdf: 4c 8b 67 20 mov 0x20(%rdi),%r12 - 411fe3: 8b 2f mov (%rdi),%ebp - 411fe5: 81 e5 00 10 00 00 and $0x1000,%ebp - 411feb: 4d 39 e5 cmp %r12,%r13 - 411fee: 76 08 jbe 411ff8 <_IO_new_file_seekoff+0x318> - 411ff0: 85 ed test %ebp,%ebp - 411ff2: 0f 85 c0 00 00 00 jne 4120b8 <_IO_new_file_seekoff+0x3d8> - 411ff8: 48 8b 83 90 00 00 00 mov 0x90(%rbx),%rax - 411fff: 4d 39 e5 cmp %r12,%r13 - 412002: 0f 87 98 00 00 00 ja 4120a0 <_IO_new_file_seekoff+0x3c0> - 412008: 48 8b 6b 08 mov 0x8(%rbx),%rbp - 41200c: 48 2b 6b 10 sub 0x10(%rbx),%rbp - 412010: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 412014: 0f 84 f6 00 00 00 je 412110 <_IO_new_file_seekoff+0x430> - 41201a: 48 01 c5 add %rax,%rbp - 41201d: 0f 89 9c fd ff ff jns 411dbf <_IO_new_file_seekoff+0xdf> - 412023: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 41202a: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) - 412031: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 412038: 48 c7 c5 ff ff ff ff mov $0xffffffffffffffff,%rbp - 41203f: e9 7b fd ff ff jmpq 411dbf <_IO_new_file_seekoff+0xdf> - 412044: 0f 1f 40 00 nopl 0x0(%rax) - 412048: 48 89 ee mov %rbp,%rsi - 41204b: 48 89 df mov %rbx,%rdi - 41204e: ff 90 80 00 00 00 callq *0x80(%rax) - 412054: 48 85 c0 test %rax,%rax - 412057: 49 89 c6 mov %rax,%r14 - 41205a: 78 dc js 412038 <_IO_new_file_seekoff+0x358> - 41205c: 31 c9 xor %ecx,%ecx - 41205e: 45 31 e4 xor %r12d,%r12d - 412061: 31 c0 xor %eax,%eax - 412063: 48 8b 53 38 mov 0x38(%rbx),%rdx - 412067: 4c 01 f0 add %r14,%rax - 41206a: 83 23 ef andl $0xffffffef,(%rbx) - 41206d: 48 89 83 90 00 00 00 mov %rax,0x90(%rbx) - 412074: 49 01 d4 add %rdx,%r12 - 412077: 48 01 d1 add %rdx,%rcx - 41207a: 48 89 53 18 mov %rdx,0x18(%rbx) - 41207e: 4c 89 63 08 mov %r12,0x8(%rbx) - 412082: 48 89 4b 10 mov %rcx,0x10(%rbx) - 412086: 48 89 53 28 mov %rdx,0x28(%rbx) - 41208a: 48 89 53 20 mov %rdx,0x20(%rbx) - 41208e: 48 89 53 30 mov %rdx,0x30(%rbx) - 412092: e9 28 fd ff ff jmpq 411dbf <_IO_new_file_seekoff+0xdf> - 412097: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 41209e: 00 00 - 4120a0: 85 ed test %ebp,%ebp - 4120a2: 48 8b 6b 28 mov 0x28(%rbx),%rbp - 4120a6: 74 40 je 4120e8 <_IO_new_file_seekoff+0x408> - 4120a8: 48 2b 6b 20 sub 0x20(%rbx),%rbp - 4120ac: e9 5f ff ff ff jmpq 412010 <_IO_new_file_seekoff+0x330> - 4120b1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4120b8: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax - 4120bf: 31 f6 xor %esi,%esi - 4120c1: ba 02 00 00 00 mov $0x2,%edx - 4120c6: ff 90 80 00 00 00 callq *0x80(%rax) - 4120cc: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 4120d0: 0f 84 62 ff ff ff je 412038 <_IO_new_file_seekoff+0x358> - 4120d6: 48 89 83 90 00 00 00 mov %rax,0x90(%rbx) - 4120dd: e9 1d ff ff ff jmpq 411fff <_IO_new_file_seekoff+0x31f> - 4120e2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4120e8: 48 2b 6b 10 sub 0x10(%rbx),%rbp - 4120ec: e9 1f ff ff ff jmpq 412010 <_IO_new_file_seekoff+0x330> - 4120f1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4120f8: 48 8b 87 90 00 00 00 mov 0x90(%rdi),%rax - 4120ff: 31 ed xor %ebp,%ebp - 412101: e9 0a ff ff ff jmpq 412010 <_IO_new_file_seekoff+0x330> - 412106: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41210d: 00 00 00 - 412110: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 412117: 31 f6 xor %esi,%esi - 412119: ba 01 00 00 00 mov $0x1,%edx - 41211e: 48 89 df mov %rbx,%rdi - 412121: ff 90 80 00 00 00 callq *0x80(%rax) - 412127: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 41212b: 0f 84 07 ff ff ff je 412038 <_IO_new_file_seekoff+0x358> - 412131: e9 e4 fe ff ff jmpq 41201a <_IO_new_file_seekoff+0x33a> - 412136: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41213d: 00 00 00 - -0000000000412140 <_IO_file_close_mmap>: - 412140: 53 push %rbx - 412141: 48 89 fb mov %rdi,%rbx - 412144: 48 8b 7f 38 mov 0x38(%rdi),%rdi - 412148: 48 8b 73 40 mov 0x40(%rbx),%rsi - 41214c: 48 29 fe sub %rdi,%rsi - 41214f: e8 5c db 02 00 callq 43fcb0 <__munmap> - 412154: 48 c7 43 40 00 00 00 movq $0x0,0x40(%rbx) - 41215b: 00 - 41215c: 48 c7 43 38 00 00 00 movq $0x0,0x38(%rbx) - 412163: 00 - 412164: b8 03 00 00 00 mov $0x3,%eax - 412169: 48 63 7b 70 movslq 0x70(%rbx),%rdi - 41216d: 0f 05 syscall - 41216f: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 412175: 76 11 jbe 412188 <_IO_file_close_mmap+0x48> - 412177: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx - 41217e: f7 d8 neg %eax - 412180: 64 89 02 mov %eax,%fs:(%rdx) - 412183: b8 ff ff ff ff mov $0xffffffff,%eax - 412188: 5b pop %rbx - 412189: c3 retq - 41218a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - -0000000000412190 <_IO_file_seek>: - 412190: 8b 7f 70 mov 0x70(%rdi),%edi - 412193: e9 98 03 03 00 jmpq 442530 <__libc_lseek> - 412198: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 41219f: 00 - -00000000004121a0 <_IO_file_sync_mmap>: - 4121a0: 53 push %rbx - 4121a1: 48 8b 77 08 mov 0x8(%rdi),%rsi - 4121a5: 48 89 fb mov %rdi,%rbx - 4121a8: 48 3b 77 10 cmp 0x10(%rdi),%rsi - 4121ac: 74 32 je 4121e0 <_IO_file_sync_mmap+0x40> - 4121ae: 48 2b 77 38 sub 0x38(%rdi),%rsi - 4121b2: 8b 7f 70 mov 0x70(%rdi),%edi - 4121b5: 31 d2 xor %edx,%edx - 4121b7: e8 74 03 03 00 callq 442530 <__libc_lseek> - 4121bc: 48 8b 73 08 mov 0x8(%rbx),%rsi - 4121c0: 48 2b 73 38 sub 0x38(%rbx),%rsi - 4121c4: 48 39 f0 cmp %rsi,%rax - 4121c7: 75 27 jne 4121f0 <_IO_file_sync_mmap+0x50> - 4121c9: 48 8b 43 18 mov 0x18(%rbx),%rax - 4121cd: 48 89 b3 90 00 00 00 mov %rsi,0x90(%rbx) - 4121d4: 48 89 43 08 mov %rax,0x8(%rbx) - 4121d8: 48 89 43 10 mov %rax,0x10(%rbx) - 4121dc: 31 c0 xor %eax,%eax - 4121de: 5b pop %rbx - 4121df: c3 retq - 4121e0: 48 2b 77 38 sub 0x38(%rdi),%rsi - 4121e4: eb e3 jmp 4121c9 <_IO_file_sync_mmap+0x29> - 4121e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4121ed: 00 00 00 - 4121f0: 83 0b 20 orl $0x20,(%rbx) - 4121f3: b8 ff ff ff ff mov $0xffffffff,%eax - 4121f8: 5b pop %rbx - 4121f9: c3 retq - 4121fa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - -0000000000412200 <_IO_file_xsgetn_maybe_mmap>: - 412200: 41 55 push %r13 - 412202: 41 54 push %r12 - 412204: 49 89 d4 mov %rdx,%r12 - 412207: 55 push %rbp - 412208: 53 push %rbx - 412209: 48 89 f5 mov %rsi,%rbp - 41220c: 48 89 fb mov %rdi,%rbx - 41220f: 48 81 ec 98 00 00 00 sub $0x98,%rsp - 412216: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax - 41221d: 48 89 e6 mov %rsp,%rsi - 412220: ff 90 90 00 00 00 callq *0x90(%rax) - 412226: 85 c0 test %eax,%eax - 412228: 75 10 jne 41223a <_IO_file_xsgetn_maybe_mmap+0x3a> - 41222a: 8b 44 24 18 mov 0x18(%rsp),%eax - 41222e: 25 00 f0 00 00 and $0xf000,%eax - 412233: 3d 00 80 00 00 cmp $0x8000,%eax - 412238: 74 56 je 412290 <_IO_file_xsgetn_maybe_mmap+0x90> - 41223a: 8b 83 c0 00 00 00 mov 0xc0(%rbx),%eax - 412240: ba 20 1e 4a 00 mov $0x4a1e20,%edx - 412245: 85 c0 test %eax,%eax - 412247: b8 20 1b 4a 00 mov $0x4a1b20,%eax - 41224c: 48 0f 4e c2 cmovle %rdx,%rax - 412250: 48 89 83 d8 00 00 00 mov %rax,0xd8(%rbx) - 412257: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 41225e: 48 c7 80 30 01 00 00 movq $0x4a1b20,0x130(%rax) - 412265: 20 1b 4a 00 - 412269: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 412270: 4c 89 e2 mov %r12,%rdx - 412273: 48 89 ee mov %rbp,%rsi - 412276: 48 89 df mov %rbx,%rdi - 412279: ff 50 40 callq *0x40(%rax) - 41227c: 48 81 c4 98 00 00 00 add $0x98,%rsp - 412283: 5b pop %rbx - 412284: 5d pop %rbp - 412285: 41 5c pop %r12 - 412287: 41 5d pop %r13 - 412289: c3 retq - 41228a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 412290: 48 8b 74 24 30 mov 0x30(%rsp),%rsi - 412295: 48 85 f6 test %rsi,%rsi - 412298: 74 a0 je 41223a <_IO_file_xsgetn_maybe_mmap+0x3a> - 41229a: 48 8b 83 90 00 00 00 mov 0x90(%rbx),%rax - 4122a1: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 4122a5: 74 05 je 4122ac <_IO_file_xsgetn_maybe_mmap+0xac> - 4122a7: 48 39 c6 cmp %rax,%rsi - 4122aa: 7c 8e jl 41223a <_IO_file_xsgetn_maybe_mmap+0x3a> - 4122ac: 44 8b 43 70 mov 0x70(%rbx),%r8d - 4122b0: 45 31 c9 xor %r9d,%r9d - 4122b3: 31 ff xor %edi,%edi - 4122b5: b9 01 00 00 00 mov $0x1,%ecx - 4122ba: ba 01 00 00 00 mov $0x1,%edx - 4122bf: e8 2c d9 02 00 callq 43fbf0 <__mmap> - 4122c4: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 4122c8: 49 89 c5 mov %rax,%r13 - 4122cb: 0f 84 69 ff ff ff je 41223a <_IO_file_xsgetn_maybe_mmap+0x3a> - 4122d1: 48 8b 74 24 30 mov 0x30(%rsp),%rsi - 4122d6: 8b 7b 70 mov 0x70(%rbx),%edi - 4122d9: 31 d2 xor %edx,%edx - 4122db: e8 50 02 03 00 callq 442530 <__libc_lseek> - 4122e0: 48 8b 74 24 30 mov 0x30(%rsp),%rsi - 4122e5: 48 39 f0 cmp %rsi,%rax - 4122e8: 74 18 je 412302 <_IO_file_xsgetn_maybe_mmap+0x102> - 4122ea: 4c 89 ef mov %r13,%rdi - 4122ed: e8 be d9 02 00 callq 43fcb0 <__munmap> - 4122f2: 48 c7 83 90 00 00 00 movq $0xffffffffffffffff,0x90(%rbx) - 4122f9: ff ff ff ff - 4122fd: e9 38 ff ff ff jmpq 41223a <_IO_file_xsgetn_maybe_mmap+0x3a> - 412302: 49 8d 54 05 00 lea 0x0(%r13,%rax,1),%rdx - 412307: 31 c9 xor %ecx,%ecx - 412309: 4c 89 ee mov %r13,%rsi - 41230c: 48 89 df mov %rbx,%rdi - 41230f: e8 8c 2a 00 00 callq 414da0 <_IO_setb> - 412314: 48 8b 83 90 00 00 00 mov 0x90(%rbx),%rax - 41231b: ba 00 00 00 00 mov $0x0,%edx - 412320: 4c 89 6b 18 mov %r13,0x18(%rbx) - 412324: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 412328: 48 0f 44 c2 cmove %rdx,%rax - 41232c: 8b 93 c0 00 00 00 mov 0xc0(%rbx),%edx - 412332: 4c 01 e8 add %r13,%rax - 412335: 48 89 43 08 mov %rax,0x8(%rbx) - 412339: 48 8b 44 24 30 mov 0x30(%rsp),%rax - 41233e: 49 01 c5 add %rax,%r13 - 412341: 48 89 83 90 00 00 00 mov %rax,0x90(%rbx) - 412348: 85 d2 test %edx,%edx - 41234a: b8 60 1a 4a 00 mov $0x4a1a60,%eax - 41234f: ba 60 1d 4a 00 mov $0x4a1d60,%edx - 412354: 4c 89 6b 10 mov %r13,0x10(%rbx) - 412358: 48 0f 4e c2 cmovle %rdx,%rax - 41235c: 48 89 83 d8 00 00 00 mov %rax,0xd8(%rbx) - 412363: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 41236a: 48 c7 80 30 01 00 00 movq $0x4a1a60,0x130(%rax) - 412371: 60 1a 4a 00 - 412375: e9 ef fe ff ff jmpq 412269 <_IO_file_xsgetn_maybe_mmap+0x69> - 41237a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - -0000000000412380 <_IO_file_stat>: - 412380: 48 89 f2 mov %rsi,%rdx - 412383: 8b 77 70 mov 0x70(%rdi),%esi - 412386: bf 01 00 00 00 mov $0x1,%edi - 41238b: e9 40 cd 02 00 jmpq 43f0d0 <__fxstat> - -0000000000412390 <_IO_new_file_write>: - 412390: 48 85 d2 test %rdx,%rdx - 412393: 41 56 push %r14 - 412395: 49 89 fe mov %rdi,%r14 - 412398: 41 55 push %r13 - 41239a: 41 54 push %r12 - 41239c: 55 push %rbp - 41239d: 53 push %rbx - 41239e: 0f 8e 93 00 00 00 jle 412437 <_IO_new_file_write+0xa7> - 4123a4: 48 89 f5 mov %rsi,%rbp - 4123a7: 49 89 d4 mov %rdx,%r12 - 4123aa: 48 89 d3 mov %rdx,%rbx - 4123ad: 41 bd 01 00 00 00 mov $0x1,%r13d - 4123b3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4123b8: 41 f6 46 74 02 testb $0x2,0x74(%r14) - 4123bd: 74 51 je 412410 <_IO_new_file_write+0x80> - 4123bf: 49 63 7e 70 movslq 0x70(%r14),%rdi - 4123c3: 48 89 da mov %rbx,%rdx - 4123c6: 48 89 ee mov %rbp,%rsi - 4123c9: 44 89 e8 mov %r13d,%eax - 4123cc: 0f 05 syscall - 4123ce: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 4123d4: 76 49 jbe 41241f <_IO_new_file_write+0x8f> - 4123d6: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx - 4123dd: f7 d8 neg %eax - 4123df: 64 89 02 mov %eax,%fs:(%rdx) - 4123e2: 41 83 0e 20 orl $0x20,(%r14) - 4123e6: 4c 89 e0 mov %r12,%rax - 4123e9: 48 29 d8 sub %rbx,%rax - 4123ec: 49 8b 96 90 00 00 00 mov 0x90(%r14),%rdx - 4123f3: 48 85 d2 test %rdx,%rdx - 4123f6: 78 0a js 412402 <_IO_new_file_write+0x72> - 4123f8: 48 01 c2 add %rax,%rdx - 4123fb: 49 89 96 90 00 00 00 mov %rdx,0x90(%r14) - 412402: 5b pop %rbx - 412403: 5d pop %rbp - 412404: 41 5c pop %r12 - 412406: 41 5d pop %r13 - 412408: 41 5e pop %r14 - 41240a: c3 retq - 41240b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 412410: 41 8b 7e 70 mov 0x70(%r14),%edi - 412414: 48 89 da mov %rbx,%rdx - 412417: 48 89 ee mov %rbp,%rsi - 41241a: e8 c1 cd 02 00 callq 43f1e0 <__libc_write> - 41241f: 48 85 c0 test %rax,%rax - 412422: 78 be js 4123e2 <_IO_new_file_write+0x52> - 412424: 48 29 c3 sub %rax,%rbx - 412427: 48 01 c5 add %rax,%rbp - 41242a: 48 85 db test %rbx,%rbx - 41242d: 7f 89 jg 4123b8 <_IO_new_file_write+0x28> - 41242f: 4c 89 e0 mov %r12,%rax - 412432: 48 29 d8 sub %rbx,%rax - 412435: eb b5 jmp 4123ec <_IO_new_file_write+0x5c> - 412437: 31 c0 xor %eax,%eax - 412439: eb b1 jmp 4123ec <_IO_new_file_write+0x5c> - 41243b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - -0000000000412440 <_IO_file_xsgetn_mmap>: - 412440: 41 57 push %r15 - 412442: 41 56 push %r14 - 412444: 49 89 d7 mov %rdx,%r15 - 412447: 41 55 push %r13 - 412449: 41 54 push %r12 - 41244b: 49 89 f6 mov %rsi,%r14 - 41244e: 55 push %rbp - 41244f: 53 push %rbx - 412450: 48 89 fd mov %rdi,%rbp - 412453: 49 89 f4 mov %rsi,%r12 - 412456: 48 81 ec 98 00 00 00 sub $0x98,%rsp - 41245d: 4c 8b 6f 08 mov 0x8(%rdi),%r13 - 412461: 48 8b 5f 10 mov 0x10(%rdi),%rbx - 412465: 4c 29 eb sub %r13,%rbx - 412468: 48 39 d3 cmp %rdx,%rbx - 41246b: 0f 83 80 01 00 00 jae 4125f1 <_IO_file_xsgetn_mmap+0x1b1> - 412471: f7 07 00 01 00 00 testl $0x100,(%rdi) - 412477: 0f 85 93 01 00 00 jne 412610 <_IO_file_xsgetn_mmap+0x1d0> - 41247d: 48 8b 85 d8 00 00 00 mov 0xd8(%rbp),%rax - 412484: 48 89 e6 mov %rsp,%rsi - 412487: 48 89 ef mov %rbp,%rdi - 41248a: ff 90 90 00 00 00 callq *0x90(%rax) - 412490: 85 c0 test %eax,%eax - 412492: 75 14 jne 4124a8 <_IO_file_xsgetn_mmap+0x68> - 412494: 8b 44 24 18 mov 0x18(%rsp),%eax - 412498: 25 00 f0 00 00 and $0xf000,%eax - 41249d: 3d 00 80 00 00 cmp $0x8000,%eax - 4124a2: 0f 84 88 00 00 00 je 412530 <_IO_file_xsgetn_mmap+0xf0> - 4124a8: 48 8b 7d 38 mov 0x38(%rbp),%rdi - 4124ac: 48 8b 75 40 mov 0x40(%rbp),%rsi - 4124b0: 48 29 fe sub %rdi,%rsi - 4124b3: e8 f8 d7 02 00 callq 43fcb0 <__munmap> - 4124b8: 8b 85 c0 00 00 00 mov 0xc0(%rbp),%eax - 4124be: ba 20 1e 4a 00 mov $0x4a1e20,%edx - 4124c3: 48 c7 45 40 00 00 00 movq $0x0,0x40(%rbp) - 4124ca: 00 - 4124cb: 48 c7 45 38 00 00 00 movq $0x0,0x38(%rbp) - 4124d2: 00 - 4124d3: 48 c7 45 18 00 00 00 movq $0x0,0x18(%rbp) - 4124da: 00 - 4124db: 4c 89 f6 mov %r14,%rsi - 4124de: 48 c7 45 08 00 00 00 movq $0x0,0x8(%rbp) - 4124e5: 00 - 4124e6: 48 c7 45 10 00 00 00 movq $0x0,0x10(%rbp) - 4124ed: 00 - 4124ee: 48 89 ef mov %rbp,%rdi - 4124f1: 85 c0 test %eax,%eax - 4124f3: b8 20 1b 4a 00 mov $0x4a1b20,%eax - 4124f8: 48 0f 4e c2 cmovle %rdx,%rax - 4124fc: 4d 29 f4 sub %r14,%r12 - 4124ff: 4c 89 fa mov %r15,%rdx - 412502: 48 89 85 d8 00 00 00 mov %rax,0xd8(%rbp) - 412509: 48 8b 85 a0 00 00 00 mov 0xa0(%rbp),%rax - 412510: 48 c7 80 30 01 00 00 movq $0x4a1b20,0x130(%rax) - 412517: 20 1b 4a 00 - 41251b: 48 8b 85 d8 00 00 00 mov 0xd8(%rbp),%rax - 412522: ff 50 40 callq *0x40(%rax) - 412525: 4c 01 e0 add %r12,%rax - 412528: e9 cf 00 00 00 jmpq 4125fc <_IO_file_xsgetn_mmap+0x1bc> - 41252d: 0f 1f 00 nopl (%rax) - 412530: 48 8b 5c 24 30 mov 0x30(%rsp),%rbx - 412535: 48 85 db test %rbx,%rbx - 412538: 0f 84 6a ff ff ff je 4124a8 <_IO_file_xsgetn_mmap+0x68> - 41253e: e8 4d d6 02 00 callq 43fb90 <__getpagesize> - 412543: 48 8b 7d 38 mov 0x38(%rbp),%rdi - 412547: 48 63 c8 movslq %eax,%rcx - 41254a: 48 89 ce mov %rcx,%rsi - 41254d: 48 8d 54 0b ff lea -0x1(%rbx,%rcx,1),%rdx - 412552: 48 f7 de neg %rsi - 412555: 49 89 f8 mov %rdi,%r8 - 412558: 48 21 f2 and %rsi,%rdx - 41255b: 48 89 f8 mov %rdi,%rax - 41255e: 49 f7 d0 not %r8 - 412561: 4c 03 45 40 add 0x40(%rbp),%r8 - 412565: 4c 01 c1 add %r8,%rcx - 412568: 48 21 ce and %rcx,%rsi - 41256b: 48 39 f2 cmp %rsi,%rdx - 41256e: 0f 82 01 01 00 00 jb 412675 <_IO_file_xsgetn_mmap+0x235> - 412574: 0f 87 21 01 00 00 ja 41269b <_IO_file_xsgetn_mmap+0x25b> - 41257a: 48 01 fb add %rdi,%rbx - 41257d: 48 89 5d 40 mov %rbx,0x40(%rbp) - 412581: 49 89 dd mov %rbx,%r13 - 412584: 48 8b 55 10 mov 0x10(%rbp),%rdx - 412588: 48 2b 55 08 sub 0x8(%rbp),%rdx - 41258c: 4c 89 ee mov %r13,%rsi - 41258f: 48 8b 8d 90 00 00 00 mov 0x90(%rbp),%rcx - 412596: 48 29 c6 sub %rax,%rsi - 412599: 48 89 7d 18 mov %rdi,0x18(%rbp) - 41259d: 48 29 d1 sub %rdx,%rcx - 4125a0: 48 39 f1 cmp %rsi,%rcx - 4125a3: 48 89 ca mov %rcx,%rdx - 4125a6: 48 89 8d 90 00 00 00 mov %rcx,0x90(%rbp) - 4125ad: 0f 8d ae 00 00 00 jge 412661 <_IO_file_xsgetn_mmap+0x221> - 4125b3: 48 01 fa add %rdi,%rdx - 4125b6: 8b 7d 70 mov 0x70(%rbp),%edi - 4125b9: 4c 89 6d 10 mov %r13,0x10(%rbp) - 4125bd: 48 89 55 08 mov %rdx,0x8(%rbp) - 4125c1: 31 d2 xor %edx,%edx - 4125c3: e8 68 ff 02 00 callq 442530 <__libc_lseek> - 4125c8: 48 8b 55 40 mov 0x40(%rbp),%rdx - 4125cc: 48 2b 55 38 sub 0x38(%rbp),%rdx - 4125d0: 48 39 d0 cmp %rdx,%rax - 4125d3: 0f 84 f3 00 00 00 je 4126cc <_IO_file_xsgetn_mmap+0x28c> - 4125d9: 83 4d 00 20 orl $0x20,0x0(%rbp) - 4125dd: 4c 8b 6d 08 mov 0x8(%rbp),%r13 - 4125e1: 48 8b 5d 10 mov 0x10(%rbp),%rbx - 4125e5: 4c 29 eb sub %r13,%rbx - 4125e8: 4c 39 fb cmp %r15,%rbx - 4125eb: 73 04 jae 4125f1 <_IO_file_xsgetn_mmap+0x1b1> - 4125ed: 83 4d 00 10 orl $0x10,0x0(%rbp) - 4125f1: 48 85 db test %rbx,%rbx - 4125f4: 75 4a jne 412640 <_IO_file_xsgetn_mmap+0x200> - 4125f6: 4c 89 e0 mov %r12,%rax - 4125f9: 4c 29 f0 sub %r14,%rax - 4125fc: 48 81 c4 98 00 00 00 add $0x98,%rsp - 412603: 5b pop %rbx - 412604: 5d pop %rbp - 412605: 41 5c pop %r12 - 412607: 41 5d pop %r13 - 412609: 41 5e pop %r14 - 41260b: 41 5f pop %r15 - 41260d: c3 retq - 41260e: 66 90 xchg %ax,%ax - 412610: 48 89 da mov %rbx,%rdx - 412613: 4c 89 ee mov %r13,%rsi - 412616: 4c 89 f7 mov %r14,%rdi - 412619: e8 a2 3f 01 00 callq 4265c0 <__mempcpy> - 41261e: 48 89 ef mov %rbp,%rdi - 412621: 49 29 df sub %rbx,%r15 - 412624: 49 89 c4 mov %rax,%r12 - 412627: e8 34 23 00 00 callq 414960 <_IO_switch_to_main_get_area> - 41262c: 4c 8b 6d 08 mov 0x8(%rbp),%r13 - 412630: 48 8b 5d 10 mov 0x10(%rbp),%rbx - 412634: 4c 29 eb sub %r13,%rbx - 412637: 49 39 df cmp %rbx,%r15 - 41263a: 0f 87 3d fe ff ff ja 41247d <_IO_file_xsgetn_mmap+0x3d> - 412640: 4c 39 fb cmp %r15,%rbx - 412643: 4c 89 e7 mov %r12,%rdi - 412646: 4c 89 ee mov %r13,%rsi - 412649: 49 0f 47 df cmova %r15,%rbx - 41264d: 48 89 da mov %rbx,%rdx - 412650: 4c 01 eb add %r13,%rbx - 412653: e8 68 3f 01 00 callq 4265c0 <__mempcpy> - 412658: 48 89 5d 08 mov %rbx,0x8(%rbp) - 41265c: 49 89 c4 mov %rax,%r12 - 41265f: eb 95 jmp 4125f6 <_IO_file_xsgetn_mmap+0x1b6> - 412661: 4d 85 ff test %r15,%r15 - 412664: 4c 89 6d 08 mov %r13,0x8(%rbp) - 412668: 4c 89 6d 10 mov %r13,0x10(%rbp) - 41266c: 74 88 je 4125f6 <_IO_file_xsgetn_mmap+0x1b6> - 41266e: 31 db xor %ebx,%ebx - 412670: e9 78 ff ff ff jmpq 4125ed <_IO_file_xsgetn_mmap+0x1ad> - 412675: 48 01 d7 add %rdx,%rdi - 412678: 48 29 d6 sub %rdx,%rsi - 41267b: e8 30 d6 02 00 callq 43fcb0 <__munmap> - 412680: 48 8b 7d 38 mov 0x38(%rbp),%rdi - 412684: 48 89 fb mov %rdi,%rbx - 412687: 48 03 5c 24 30 add 0x30(%rsp),%rbx - 41268c: 48 89 f8 mov %rdi,%rax - 41268f: 48 89 5d 40 mov %rbx,0x40(%rbp) - 412693: 49 89 dd mov %rbx,%r13 - 412696: e9 e9 fe ff ff jmpq 412584 <_IO_file_xsgetn_mmap+0x144> - 41269b: 31 c0 xor %eax,%eax - 41269d: b9 01 00 00 00 mov $0x1,%ecx - 4126a2: e8 a9 fe 02 00 callq 442550 <__mremap> - 4126a7: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 4126ab: 0f 84 f7 fd ff ff je 4124a8 <_IO_file_xsgetn_mmap+0x68> - 4126b1: 48 89 c3 mov %rax,%rbx - 4126b4: 48 03 5c 24 30 add 0x30(%rsp),%rbx - 4126b9: 48 89 45 38 mov %rax,0x38(%rbp) - 4126bd: 48 89 c7 mov %rax,%rdi - 4126c0: 48 89 5d 40 mov %rbx,0x40(%rbp) - 4126c4: 49 89 dd mov %rbx,%r13 - 4126c7: e9 b8 fe ff ff jmpq 412584 <_IO_file_xsgetn_mmap+0x144> - 4126cc: 48 89 85 90 00 00 00 mov %rax,0x90(%rbp) - 4126d3: e9 05 ff ff ff jmpq 4125dd <_IO_file_xsgetn_mmap+0x19d> - 4126d8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 4126df: 00 - -00000000004126e0 <_IO_file_xsgetn>: - 4126e0: 41 56 push %r14 - 4126e2: 41 55 push %r13 - 4126e4: 49 89 f6 mov %rsi,%r14 - 4126e7: 41 54 push %r12 - 4126e9: 55 push %rbp - 4126ea: 49 89 d5 mov %rdx,%r13 - 4126ed: 53 push %rbx - 4126ee: 48 83 7f 38 00 cmpq $0x0,0x38(%rdi) - 4126f3: 48 89 fb mov %rdi,%rbx - 4126f6: 0f 84 a4 01 00 00 je 4128a0 <_IO_file_xsgetn+0x1c0> - 4126fc: 4d 85 ed test %r13,%r13 - 4126ff: 4d 89 ec mov %r13,%r12 - 412702: 0f 84 c8 00 00 00 je 4127d0 <_IO_file_xsgetn+0xf0> - 412708: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 41270f: 00 - 412710: 48 8b 73 08 mov 0x8(%rbx),%rsi - 412714: 48 8b 6b 10 mov 0x10(%rbx),%rbp - 412718: 48 29 f5 sub %rsi,%rbp - 41271b: 4c 39 e5 cmp %r12,%rbp - 41271e: 0f 83 c4 00 00 00 jae 4127e8 <_IO_file_xsgetn+0x108> - 412724: 48 85 ed test %rbp,%rbp - 412727: 0f 85 23 01 00 00 jne 412850 <_IO_file_xsgetn+0x170> - 41272d: f7 03 00 01 00 00 testl $0x100,(%rbx) - 412733: 0f 85 07 01 00 00 jne 412840 <_IO_file_xsgetn+0x160> - 412739: 48 8b 53 38 mov 0x38(%rbx),%rdx - 41273d: 48 85 d2 test %rdx,%rdx - 412740: 0f 84 ba 00 00 00 je 412800 <_IO_file_xsgetn+0x120> - 412746: 48 8b 4b 40 mov 0x40(%rbx),%rcx - 41274a: 48 29 d1 sub %rdx,%rcx - 41274d: 49 39 cc cmp %rcx,%r12 - 412750: 0f 82 1a 01 00 00 jb 412870 <_IO_file_xsgetn+0x190> - 412756: 48 83 f9 7f cmp $0x7f,%rcx - 41275a: 48 89 53 18 mov %rdx,0x18(%rbx) - 41275e: 48 89 53 08 mov %rdx,0x8(%rbx) - 412762: 48 89 53 10 mov %rdx,0x10(%rbx) - 412766: 48 89 53 28 mov %rdx,0x28(%rbx) - 41276a: 48 89 53 20 mov %rdx,0x20(%rbx) - 41276e: 48 89 53 30 mov %rdx,0x30(%rbx) - 412772: 0f 86 b8 00 00 00 jbe 412830 <_IO_file_xsgetn+0x150> - 412778: 4c 89 e0 mov %r12,%rax - 41277b: 31 d2 xor %edx,%edx - 41277d: 48 f7 f1 div %rcx - 412780: 4c 89 e0 mov %r12,%rax - 412783: 48 29 d0 sub %rdx,%rax - 412786: 48 89 c2 mov %rax,%rdx - 412789: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 412790: 4c 89 f6 mov %r14,%rsi - 412793: 48 89 df mov %rbx,%rdi - 412796: ff 50 70 callq *0x70(%rax) - 412799: 48 83 f8 00 cmp $0x0,%rax - 41279d: 0f 8e ed 00 00 00 jle 412890 <_IO_file_xsgetn+0x1b0> - 4127a3: 48 8b 93 90 00 00 00 mov 0x90(%rbx),%rdx - 4127aa: 49 01 c6 add %rax,%r14 - 4127ad: 49 29 c4 sub %rax,%r12 - 4127b0: 48 83 fa ff cmp $0xffffffffffffffff,%rdx - 4127b4: 74 0a je 4127c0 <_IO_file_xsgetn+0xe0> - 4127b6: 48 01 d0 add %rdx,%rax - 4127b9: 48 89 83 90 00 00 00 mov %rax,0x90(%rbx) - 4127c0: 4d 85 e4 test %r12,%r12 - 4127c3: 0f 85 47 ff ff ff jne 412710 <_IO_file_xsgetn+0x30> - 4127c9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4127d0: 45 31 e4 xor %r12d,%r12d - 4127d3: 4c 89 e8 mov %r13,%rax - 4127d6: 5b pop %rbx - 4127d7: 4c 29 e0 sub %r12,%rax - 4127da: 5d pop %rbp - 4127db: 41 5c pop %r12 - 4127dd: 41 5d pop %r13 - 4127df: 41 5e pop %r14 - 4127e1: c3 retq - 4127e2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4127e8: 4c 89 e2 mov %r12,%rdx - 4127eb: 4c 89 f7 mov %r14,%rdi - 4127ee: e8 2d 98 01 00 callq 42c020 - 4127f3: 4c 01 63 08 add %r12,0x8(%rbx) - 4127f7: eb d7 jmp 4127d0 <_IO_file_xsgetn+0xf0> - 4127f9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 412800: 48 c7 43 18 00 00 00 movq $0x0,0x18(%rbx) - 412807: 00 - 412808: 48 c7 43 08 00 00 00 movq $0x0,0x8(%rbx) - 41280f: 00 - 412810: 48 c7 43 10 00 00 00 movq $0x0,0x10(%rbx) - 412817: 00 - 412818: 48 c7 43 28 00 00 00 movq $0x0,0x28(%rbx) - 41281f: 00 - 412820: 48 c7 43 20 00 00 00 movq $0x0,0x20(%rbx) - 412827: 00 - 412828: 48 c7 43 30 00 00 00 movq $0x0,0x30(%rbx) - 41282f: 00 - 412830: 4c 89 e2 mov %r12,%rdx - 412833: e9 51 ff ff ff jmpq 412789 <_IO_file_xsgetn+0xa9> - 412838: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 41283f: 00 - 412840: 48 89 df mov %rbx,%rdi - 412843: e8 18 21 00 00 callq 414960 <_IO_switch_to_main_get_area> - 412848: e9 73 ff ff ff jmpq 4127c0 <_IO_file_xsgetn+0xe0> - 41284d: 0f 1f 00 nopl (%rax) - 412850: 4c 89 f7 mov %r14,%rdi - 412853: 48 89 ea mov %rbp,%rdx - 412856: 49 29 ec sub %rbp,%r12 - 412859: e8 62 3d 01 00 callq 4265c0 <__mempcpy> - 41285e: 48 01 6b 08 add %rbp,0x8(%rbx) - 412862: 49 89 c6 mov %rax,%r14 - 412865: e9 c3 fe ff ff jmpq 41272d <_IO_file_xsgetn+0x4d> - 41286a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 412870: 48 89 df mov %rbx,%rdi - 412873: e8 48 22 00 00 callq 414ac0 <__underflow> - 412878: 83 f8 ff cmp $0xffffffff,%eax - 41287b: 0f 85 3f ff ff ff jne 4127c0 <_IO_file_xsgetn+0xe0> - 412881: 4c 89 e8 mov %r13,%rax - 412884: 5b pop %rbx - 412885: 4c 29 e0 sub %r12,%rax - 412888: 5d pop %rbp - 412889: 41 5c pop %r12 - 41288b: 41 5d pop %r13 - 41288d: 41 5e pop %r14 - 41288f: c3 retq - 412890: 75 2f jne 4128c1 <_IO_file_xsgetn+0x1e1> - 412892: 83 0b 10 orl $0x10,(%rbx) - 412895: e9 39 ff ff ff jmpq 4127d3 <_IO_file_xsgetn+0xf3> - 41289a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4128a0: 48 8b 7f 48 mov 0x48(%rdi),%rdi - 4128a4: 48 85 ff test %rdi,%rdi - 4128a7: 74 0b je 4128b4 <_IO_file_xsgetn+0x1d4> - 4128a9: e8 02 b5 00 00 callq 41ddb0 <__cfree> - 4128ae: 81 23 ff fe ff ff andl $0xfffffeff,(%rbx) - 4128b4: 48 89 df mov %rbx,%rdi - 4128b7: e8 44 25 00 00 callq 414e00 <_IO_doallocbuf> - 4128bc: e9 3b fe ff ff jmpq 4126fc <_IO_file_xsgetn+0x1c> - 4128c1: 83 0b 20 orl $0x20,(%rbx) - 4128c4: e9 0a ff ff ff jmpq 4127d3 <_IO_file_xsgetn+0xf3> - 4128c9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - -00000000004128d0 <_IO_file_seekoff_mmap>: - 4128d0: 55 push %rbp - 4128d1: 53 push %rbx - 4128d2: 48 89 fb mov %rdi,%rbx - 4128d5: 48 83 ec 08 sub $0x8,%rsp - 4128d9: 85 c9 test %ecx,%ecx - 4128db: 0f 84 87 00 00 00 je 412968 <_IO_file_seekoff_mmap+0x98> - 4128e1: 83 fa 01 cmp $0x1,%edx - 4128e4: 48 89 f5 mov %rsi,%rbp - 4128e7: 74 6f je 412958 <_IO_file_seekoff_mmap+0x88> - 4128e9: 83 fa 02 cmp $0x2,%edx - 4128ec: 75 0b jne 4128f9 <_IO_file_seekoff_mmap+0x29> - 4128ee: 48 8b 47 40 mov 0x40(%rdi),%rax - 4128f2: 48 2b 47 38 sub 0x38(%rdi),%rax - 4128f6: 48 01 c5 add %rax,%rbp - 4128f9: 48 85 ed test %rbp,%rbp - 4128fc: 0f 88 96 00 00 00 js 412998 <_IO_file_seekoff_mmap+0xc8> - 412902: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 412909: 31 d2 xor %edx,%edx - 41290b: 48 89 ee mov %rbp,%rsi - 41290e: 48 89 df mov %rbx,%rdi - 412911: ff 90 80 00 00 00 callq *0x80(%rax) - 412917: 48 85 c0 test %rax,%rax - 41291a: 0f 88 8f 00 00 00 js 4129af <_IO_file_seekoff_mmap+0xdf> - 412920: 48 8b 4b 40 mov 0x40(%rbx),%rcx - 412924: 48 8b 53 38 mov 0x38(%rbx),%rdx - 412928: 48 89 ce mov %rcx,%rsi - 41292b: 48 89 53 18 mov %rdx,0x18(%rbx) - 41292f: 48 29 d6 sub %rdx,%rsi - 412932: 48 39 f5 cmp %rsi,%rbp - 412935: 7e 51 jle 412988 <_IO_file_seekoff_mmap+0xb8> - 412937: 48 89 4b 08 mov %rcx,0x8(%rbx) - 41293b: 48 89 4b 10 mov %rcx,0x10(%rbx) - 41293f: 83 23 ef andl $0xffffffef,(%rbx) - 412942: 48 89 83 90 00 00 00 mov %rax,0x90(%rbx) - 412949: 48 89 e8 mov %rbp,%rax - 41294c: 48 83 c4 08 add $0x8,%rsp - 412950: 5b pop %rbx - 412951: 5d pop %rbp - 412952: c3 retq - 412953: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 412958: 48 8b 47 08 mov 0x8(%rdi),%rax - 41295c: 48 2b 47 18 sub 0x18(%rdi),%rax - 412960: 48 01 c5 add %rax,%rbp - 412963: eb 94 jmp 4128f9 <_IO_file_seekoff_mmap+0x29> - 412965: 0f 1f 00 nopl (%rax) - 412968: 48 8b 57 10 mov 0x10(%rdi),%rdx - 41296c: 48 2b 57 08 sub 0x8(%rdi),%rdx - 412970: 48 8b 87 90 00 00 00 mov 0x90(%rdi),%rax - 412977: 48 83 c4 08 add $0x8,%rsp - 41297b: 5b pop %rbx - 41297c: 5d pop %rbp - 41297d: 48 29 d0 sub %rdx,%rax - 412980: c3 retq - 412981: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 412988: 48 01 ea add %rbp,%rdx - 41298b: 48 89 53 08 mov %rdx,0x8(%rbx) - 41298f: 48 89 53 10 mov %rdx,0x10(%rbx) - 412993: eb aa jmp 41293f <_IO_file_seekoff_mmap+0x6f> - 412995: 0f 1f 00 nopl (%rax) - 412998: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 41299f: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) - 4129a6: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax - 4129ad: eb 9d jmp 41294c <_IO_file_seekoff_mmap+0x7c> - 4129af: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax - 4129b6: eb 94 jmp 41294c <_IO_file_seekoff_mmap+0x7c> - 4129b8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 4129bf: 00 - -00000000004129c0 <_IO_file_read>: - 4129c0: f6 47 74 02 testb $0x2,0x74(%rdi) - 4129c4: 74 32 je 4129f8 <_IO_file_read+0x38> - 4129c6: 48 63 7f 70 movslq 0x70(%rdi),%rdi - 4129ca: 31 c0 xor %eax,%eax - 4129cc: 0f 05 syscall - 4129ce: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 4129d4: 76 1a jbe 4129f0 <_IO_file_read+0x30> - 4129d6: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx - 4129dd: f7 d8 neg %eax - 4129df: 64 89 02 mov %eax,%fs:(%rdx) - 4129e2: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax - 4129e9: c3 retq - 4129ea: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4129f0: f3 c3 repz retq - 4129f2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4129f8: 8b 7f 70 mov 0x70(%rdi),%edi - 4129fb: e9 80 c7 02 00 jmpq 43f180 <__libc_read> - -0000000000412a00 <_IO_new_file_xsputn>: - 412a00: 31 c0 xor %eax,%eax - 412a02: 48 85 d2 test %rdx,%rdx - 412a05: 0f 84 84 00 00 00 je 412a8f <_IO_new_file_xsputn+0x8f> - 412a0b: 41 57 push %r15 - 412a0d: 41 56 push %r14 - 412a0f: 41 55 push %r13 - 412a11: 41 54 push %r12 - 412a13: 49 89 f5 mov %rsi,%r13 - 412a16: 55 push %rbp - 412a17: 53 push %rbx - 412a18: 49 89 d4 mov %rdx,%r12 - 412a1b: 48 89 fb mov %rdi,%rbx - 412a1e: 48 83 ec 08 sub $0x8,%rsp - 412a22: 8b 07 mov (%rdi),%eax - 412a24: 25 00 0a 00 00 and $0xa00,%eax - 412a29: 3d 00 0a 00 00 cmp $0xa00,%eax - 412a2e: 0f 84 bc 00 00 00 je 412af0 <_IO_new_file_xsputn+0xf0> - 412a34: 48 8b 57 30 mov 0x30(%rdi),%rdx - 412a38: 48 8b 7f 28 mov 0x28(%rdi),%rdi - 412a3c: 48 39 fa cmp %rdi,%rdx - 412a3f: 76 57 jbe 412a98 <_IO_new_file_xsputn+0x98> - 412a41: 48 29 fa sub %rdi,%rdx - 412a44: 45 31 f6 xor %r14d,%r14d - 412a47: 48 85 d2 test %rdx,%rdx - 412a4a: 0f 84 f0 00 00 00 je 412b40 <_IO_new_file_xsputn+0x140> - 412a50: 49 39 d4 cmp %rdx,%r12 - 412a53: 4c 89 ee mov %r13,%rsi - 412a56: 49 0f 46 d4 cmovbe %r12,%rdx - 412a5a: 48 89 d5 mov %rdx,%rbp - 412a5d: e8 5e 3b 01 00 callq 4265c0 <__mempcpy> - 412a62: 48 89 43 28 mov %rax,0x28(%rbx) - 412a66: 4c 89 e0 mov %r12,%rax - 412a69: 49 01 ed add %rbp,%r13 - 412a6c: 48 29 e8 sub %rbp,%rax - 412a6f: 48 89 c5 mov %rax,%rbp - 412a72: 49 01 ee add %rbp,%r14 - 412a75: 0f 85 12 02 00 00 jne 412c8d <_IO_new_file_xsputn+0x28d> - 412a7b: 4c 89 e0 mov %r12,%rax - 412a7e: 48 29 e8 sub %rbp,%rax - 412a81: 48 83 c4 08 add $0x8,%rsp - 412a85: 5b pop %rbx - 412a86: 5d pop %rbp - 412a87: 41 5c pop %r12 - 412a89: 41 5d pop %r13 - 412a8b: 41 5e pop %r14 - 412a8d: 41 5f pop %r15 - 412a8f: f3 c3 repz retq - 412a91: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 412a98: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 412a9f: be ff ff ff ff mov $0xffffffff,%esi - 412aa4: 48 89 df mov %rbx,%rdi - 412aa7: 4c 89 e5 mov %r12,%rbp - 412aaa: ff 50 18 callq *0x18(%rax) - 412aad: 83 f8 ff cmp $0xffffffff,%eax - 412ab0: 74 c9 je 412a7b <_IO_new_file_xsputn+0x7b> - 412ab2: 48 8b 4b 40 mov 0x40(%rbx),%rcx - 412ab6: 48 2b 4b 38 sub 0x38(%rbx),%rcx - 412aba: 31 d2 xor %edx,%edx - 412abc: 48 83 f9 7f cmp $0x7f,%rcx - 412ac0: 0f 87 ad 00 00 00 ja 412b73 <_IO_new_file_xsputn+0x173> - 412ac6: 49 89 ee mov %rbp,%r14 - 412ac9: 49 29 d6 sub %rdx,%r14 - 412acc: 0f 85 ae 00 00 00 jne 412b80 <_IO_new_file_xsputn+0x180> - 412ad2: 48 85 ed test %rbp,%rbp - 412ad5: 74 a4 je 412a7b <_IO_new_file_xsputn+0x7b> - 412ad7: 4b 8d 74 35 00 lea 0x0(%r13,%r14,1),%rsi - 412adc: 48 89 ea mov %rbp,%rdx - 412adf: 48 89 df mov %rbx,%rdi - 412ae2: e8 e9 23 00 00 callq 414ed0 <_IO_default_xsputn> - 412ae7: 48 29 c5 sub %rax,%rbp - 412aea: eb 8f jmp 412a7b <_IO_new_file_xsputn+0x7b> - 412aec: 0f 1f 40 00 nopl 0x0(%rax) - 412af0: 48 8b 7f 28 mov 0x28(%rdi),%rdi - 412af4: 48 8b 53 40 mov 0x40(%rbx),%rdx - 412af8: 48 29 fa sub %rdi,%rdx - 412afb: 49 39 d4 cmp %rdx,%r12 - 412afe: 0f 87 40 ff ff ff ja 412a44 <_IO_new_file_xsputn+0x44> - 412b04: 4a 8d 0c 26 lea (%rsi,%r12,1),%rcx - 412b08: 48 39 ce cmp %rcx,%rsi - 412b0b: 73 25 jae 412b32 <_IO_new_file_xsputn+0x132> - 412b0d: 80 79 ff 0a cmpb $0xa,-0x1(%rcx) - 412b11: 48 8d 41 ff lea -0x1(%rcx),%rax - 412b15: 75 16 jne 412b2d <_IO_new_file_xsputn+0x12d> - 412b17: e9 e4 00 00 00 jmpq 412c00 <_IO_new_file_xsputn+0x200> - 412b1c: 0f 1f 40 00 nopl 0x0(%rax) - 412b20: 48 83 e8 01 sub $0x1,%rax - 412b24: 80 38 0a cmpb $0xa,(%rax) - 412b27: 0f 84 d3 00 00 00 je 412c00 <_IO_new_file_xsputn+0x200> - 412b2d: 49 39 c5 cmp %rax,%r13 - 412b30: 75 ee jne 412b20 <_IO_new_file_xsputn+0x120> - 412b32: 45 31 f6 xor %r14d,%r14d - 412b35: e9 16 ff ff ff jmpq 412a50 <_IO_new_file_xsputn+0x50> - 412b3a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 412b40: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 412b47: be ff ff ff ff mov $0xffffffff,%esi - 412b4c: 48 89 df mov %rbx,%rdi - 412b4f: ff 50 18 callq *0x18(%rax) - 412b52: 89 c2 mov %eax,%edx - 412b54: 31 c0 xor %eax,%eax - 412b56: 83 fa ff cmp $0xffffffff,%edx - 412b59: 0f 84 22 ff ff ff je 412a81 <_IO_new_file_xsputn+0x81> - 412b5f: 48 8b 4b 40 mov 0x40(%rbx),%rcx - 412b63: 48 2b 4b 38 sub 0x38(%rbx),%rcx - 412b67: 4c 89 e5 mov %r12,%rbp - 412b6a: 4d 89 e6 mov %r12,%r14 - 412b6d: 48 83 f9 7f cmp $0x7f,%rcx - 412b71: 76 0d jbe 412b80 <_IO_new_file_xsputn+0x180> - 412b73: 48 89 e8 mov %rbp,%rax - 412b76: 31 d2 xor %edx,%edx - 412b78: 48 f7 f1 div %rcx - 412b7b: e9 46 ff ff ff jmpq 412ac6 <_IO_new_file_xsputn+0xc6> - 412b80: f7 03 00 10 00 00 testl $0x1000,(%rbx) - 412b86: 0f 84 94 00 00 00 je 412c20 <_IO_new_file_xsputn+0x220> - 412b8c: 48 c7 83 90 00 00 00 movq $0xffffffffffffffff,0x90(%rbx) - 412b93: ff ff ff ff - 412b97: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 412b9e: 4c 89 f2 mov %r14,%rdx - 412ba1: 4c 89 ee mov %r13,%rsi - 412ba4: 48 89 df mov %rbx,%rdi - 412ba7: ff 50 78 callq *0x78(%rax) - 412baa: 49 89 c7 mov %rax,%r15 - 412bad: 0f b7 83 80 00 00 00 movzwl 0x80(%rbx),%eax - 412bb4: 4d 85 ff test %r15,%r15 - 412bb7: 74 09 je 412bc2 <_IO_new_file_xsputn+0x1c2> - 412bb9: 66 85 c0 test %ax,%ax - 412bbc: 0f 85 ae 00 00 00 jne 412c70 <_IO_new_file_xsputn+0x270> - 412bc2: 8b 93 c0 00 00 00 mov 0xc0(%rbx),%edx - 412bc8: 48 8b 43 38 mov 0x38(%rbx),%rax - 412bcc: 85 d2 test %edx,%edx - 412bce: 48 89 43 18 mov %rax,0x18(%rbx) - 412bd2: 48 89 43 08 mov %rax,0x8(%rbx) - 412bd6: 48 89 43 10 mov %rax,0x10(%rbx) - 412bda: 48 89 43 28 mov %rax,0x28(%rbx) - 412bde: 48 89 43 20 mov %rax,0x20(%rbx) - 412be2: 7e 7b jle 412c5f <_IO_new_file_xsputn+0x25f> - 412be4: 48 8b 43 40 mov 0x40(%rbx),%rax - 412be8: 4c 29 fd sub %r15,%rbp - 412beb: 4d 39 f7 cmp %r14,%r15 - 412bee: 48 89 43 30 mov %rax,0x30(%rbx) - 412bf2: 0f 83 da fe ff ff jae 412ad2 <_IO_new_file_xsputn+0xd2> - 412bf8: e9 7e fe ff ff jmpq 412a7b <_IO_new_file_xsputn+0x7b> - 412bfd: 0f 1f 00 nopl (%rax) - 412c00: 4c 29 e8 sub %r13,%rax - 412c03: 41 be 01 00 00 00 mov $0x1,%r14d - 412c09: 4c 89 e5 mov %r12,%rbp - 412c0c: 48 83 c0 01 add $0x1,%rax - 412c10: 48 89 c2 mov %rax,%rdx - 412c13: 0f 85 37 fe ff ff jne 412a50 <_IO_new_file_xsputn+0x50> - 412c19: e9 54 fe ff ff jmpq 412a72 <_IO_new_file_xsputn+0x72> - 412c1e: 66 90 xchg %ax,%ax - 412c20: 48 8b 43 10 mov 0x10(%rbx),%rax - 412c24: 48 8b 73 20 mov 0x20(%rbx),%rsi - 412c28: 48 39 f0 cmp %rsi,%rax - 412c2b: 0f 84 66 ff ff ff je 412b97 <_IO_new_file_xsputn+0x197> - 412c31: 48 29 c6 sub %rax,%rsi - 412c34: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 412c3b: ba 01 00 00 00 mov $0x1,%edx - 412c40: 48 89 df mov %rbx,%rdi - 412c43: ff 90 80 00 00 00 callq *0x80(%rax) - 412c49: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 412c4d: 0f 84 28 fe ff ff je 412a7b <_IO_new_file_xsputn+0x7b> - 412c53: 48 89 83 90 00 00 00 mov %rax,0x90(%rbx) - 412c5a: e9 38 ff ff ff jmpq 412b97 <_IO_new_file_xsputn+0x197> - 412c5f: f7 03 02 02 00 00 testl $0x202,(%rbx) - 412c65: 0f 85 7d ff ff ff jne 412be8 <_IO_new_file_xsputn+0x1e8> - 412c6b: e9 74 ff ff ff jmpq 412be4 <_IO_new_file_xsputn+0x1e4> - 412c70: 8d 78 ff lea -0x1(%rax),%edi - 412c73: 44 89 fa mov %r15d,%edx - 412c76: 4c 89 ee mov %r13,%rsi - 412c79: e8 42 2d 00 00 callq 4159c0 <_IO_adjust_column> - 412c7e: 83 c0 01 add $0x1,%eax - 412c81: 66 89 83 80 00 00 00 mov %ax,0x80(%rbx) - 412c88: e9 35 ff ff ff jmpq 412bc2 <_IO_new_file_xsputn+0x1c2> - 412c8d: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 412c94: 83 ce ff or $0xffffffff,%esi - 412c97: 48 89 df mov %rbx,%rdi - 412c9a: ff 50 18 callq *0x18(%rax) - 412c9d: 83 c0 01 add $0x1,%eax - 412ca0: 0f 85 0c fe ff ff jne 412ab2 <_IO_new_file_xsputn+0xb2> - 412ca6: 48 85 ed test %rbp,%rbp - 412ca9: 0f 85 cc fd ff ff jne 412a7b <_IO_new_file_xsputn+0x7b> - 412caf: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax - 412cb6: e9 c6 fd ff ff jmpq 412a81 <_IO_new_file_xsputn+0x81> - 412cbb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - -0000000000412cc0 <_IO_file_underflow_maybe_mmap>: - 412cc0: 55 push %rbp - 412cc1: 53 push %rbx - 412cc2: 48 89 fb mov %rdi,%rbx - 412cc5: 48 81 ec 98 00 00 00 sub $0x98,%rsp - 412ccc: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax - 412cd3: 48 89 e6 mov %rsp,%rsi - 412cd6: ff 90 90 00 00 00 callq *0x90(%rax) - 412cdc: 85 c0 test %eax,%eax - 412cde: 75 10 jne 412cf0 <_IO_file_underflow_maybe_mmap+0x30> - 412ce0: 8b 44 24 18 mov 0x18(%rsp),%eax - 412ce4: 25 00 f0 00 00 and $0xf000,%eax - 412ce9: 3d 00 80 00 00 cmp $0x8000,%eax - 412cee: 74 50 je 412d40 <_IO_file_underflow_maybe_mmap+0x80> - 412cf0: 8b 83 c0 00 00 00 mov 0xc0(%rbx),%eax - 412cf6: ba 20 1e 4a 00 mov $0x4a1e20,%edx - 412cfb: 85 c0 test %eax,%eax - 412cfd: b8 20 1b 4a 00 mov $0x4a1b20,%eax - 412d02: 48 0f 4e c2 cmovle %rdx,%rax - 412d06: 48 89 83 d8 00 00 00 mov %rax,0xd8(%rbx) - 412d0d: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 412d14: 48 c7 80 30 01 00 00 movq $0x4a1b20,0x130(%rax) - 412d1b: 20 1b 4a 00 - 412d1f: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 412d26: 48 89 df mov %rbx,%rdi - 412d29: ff 50 20 callq *0x20(%rax) - 412d2c: 48 81 c4 98 00 00 00 add $0x98,%rsp - 412d33: 5b pop %rbx - 412d34: 5d pop %rbp - 412d35: c3 retq - 412d36: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 412d3d: 00 00 00 - 412d40: 48 8b 74 24 30 mov 0x30(%rsp),%rsi - 412d45: 48 85 f6 test %rsi,%rsi - 412d48: 74 a6 je 412cf0 <_IO_file_underflow_maybe_mmap+0x30> - 412d4a: 48 8b 83 90 00 00 00 mov 0x90(%rbx),%rax - 412d51: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 412d55: 74 05 je 412d5c <_IO_file_underflow_maybe_mmap+0x9c> - 412d57: 48 39 c6 cmp %rax,%rsi - 412d5a: 7c 94 jl 412cf0 <_IO_file_underflow_maybe_mmap+0x30> - 412d5c: 44 8b 43 70 mov 0x70(%rbx),%r8d - 412d60: 45 31 c9 xor %r9d,%r9d - 412d63: 31 ff xor %edi,%edi - 412d65: b9 01 00 00 00 mov $0x1,%ecx - 412d6a: ba 01 00 00 00 mov $0x1,%edx - 412d6f: e8 7c ce 02 00 callq 43fbf0 <__mmap> - 412d74: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 412d78: 48 89 c5 mov %rax,%rbp - 412d7b: 0f 84 6f ff ff ff je 412cf0 <_IO_file_underflow_maybe_mmap+0x30> - 412d81: 48 8b 74 24 30 mov 0x30(%rsp),%rsi - 412d86: 8b 7b 70 mov 0x70(%rbx),%edi - 412d89: 31 d2 xor %edx,%edx - 412d8b: e8 a0 f7 02 00 callq 442530 <__libc_lseek> - 412d90: 48 8b 74 24 30 mov 0x30(%rsp),%rsi - 412d95: 48 39 f0 cmp %rsi,%rax - 412d98: 74 18 je 412db2 <_IO_file_underflow_maybe_mmap+0xf2> - 412d9a: 48 89 ef mov %rbp,%rdi - 412d9d: e8 0e cf 02 00 callq 43fcb0 <__munmap> - 412da2: 48 c7 83 90 00 00 00 movq $0xffffffffffffffff,0x90(%rbx) - 412da9: ff ff ff ff - 412dad: e9 3e ff ff ff jmpq 412cf0 <_IO_file_underflow_maybe_mmap+0x30> - 412db2: 48 8d 54 05 00 lea 0x0(%rbp,%rax,1),%rdx - 412db7: 31 c9 xor %ecx,%ecx - 412db9: 48 89 ee mov %rbp,%rsi - 412dbc: 48 89 df mov %rbx,%rdi - 412dbf: e8 dc 1f 00 00 callq 414da0 <_IO_setb> - 412dc4: 48 8b 83 90 00 00 00 mov 0x90(%rbx),%rax - 412dcb: ba 00 00 00 00 mov $0x0,%edx - 412dd0: 48 89 6b 18 mov %rbp,0x18(%rbx) - 412dd4: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 412dd8: 48 0f 44 c2 cmove %rdx,%rax - 412ddc: 8b 93 c0 00 00 00 mov 0xc0(%rbx),%edx - 412de2: 48 01 e8 add %rbp,%rax - 412de5: 48 89 43 08 mov %rax,0x8(%rbx) - 412de9: 48 8b 44 24 30 mov 0x30(%rsp),%rax - 412dee: 48 01 c5 add %rax,%rbp - 412df1: 48 89 83 90 00 00 00 mov %rax,0x90(%rbx) - 412df8: 85 d2 test %edx,%edx - 412dfa: b8 60 1a 4a 00 mov $0x4a1a60,%eax - 412dff: ba 60 1d 4a 00 mov $0x4a1d60,%edx - 412e04: 48 89 6b 10 mov %rbp,0x10(%rbx) - 412e08: 48 0f 4e c2 cmovle %rdx,%rax - 412e0c: 48 89 83 d8 00 00 00 mov %rax,0xd8(%rbx) - 412e13: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 412e1a: 48 c7 80 30 01 00 00 movq $0x4a1a60,0x130(%rax) - 412e21: 60 1a 4a 00 - 412e25: e9 f5 fe ff ff jmpq 412d1f <_IO_file_underflow_maybe_mmap+0x5f> - 412e2a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - -0000000000412e30 <_IO_file_underflow_mmap>: - 412e30: 48 8b 47 08 mov 0x8(%rdi),%rax - 412e34: 48 3b 47 10 cmp 0x10(%rdi),%rax - 412e38: 73 06 jae 412e40 <_IO_file_underflow_mmap+0x10> - 412e3a: 0f b6 00 movzbl (%rax),%eax - 412e3d: c3 retq - 412e3e: 66 90 xchg %ax,%ax - 412e40: 55 push %rbp - 412e41: 53 push %rbx - 412e42: 48 89 fb mov %rdi,%rbx - 412e45: 48 81 ec 98 00 00 00 sub $0x98,%rsp - 412e4c: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax - 412e53: 48 89 e6 mov %rsp,%rsi - 412e56: ff 90 90 00 00 00 callq *0x90(%rax) - 412e5c: 85 c0 test %eax,%eax - 412e5e: 75 14 jne 412e74 <_IO_file_underflow_mmap+0x44> - 412e60: 8b 44 24 18 mov 0x18(%rsp),%eax - 412e64: 25 00 f0 00 00 and $0xf000,%eax - 412e69: 3d 00 80 00 00 cmp $0x8000,%eax - 412e6e: 0f 84 84 00 00 00 je 412ef8 <_IO_file_underflow_mmap+0xc8> - 412e74: 48 8b 7b 38 mov 0x38(%rbx),%rdi - 412e78: 48 8b 73 40 mov 0x40(%rbx),%rsi - 412e7c: 48 29 fe sub %rdi,%rsi - 412e7f: e8 2c ce 02 00 callq 43fcb0 <__munmap> - 412e84: 8b 83 c0 00 00 00 mov 0xc0(%rbx),%eax - 412e8a: ba 20 1e 4a 00 mov $0x4a1e20,%edx - 412e8f: 48 c7 43 40 00 00 00 movq $0x0,0x40(%rbx) - 412e96: 00 - 412e97: 48 c7 43 38 00 00 00 movq $0x0,0x38(%rbx) - 412e9e: 00 - 412e9f: 48 c7 43 18 00 00 00 movq $0x0,0x18(%rbx) - 412ea6: 00 - 412ea7: 48 89 df mov %rbx,%rdi - 412eaa: 48 c7 43 08 00 00 00 movq $0x0,0x8(%rbx) - 412eb1: 00 - 412eb2: 48 c7 43 10 00 00 00 movq $0x0,0x10(%rbx) - 412eb9: 00 - 412eba: 85 c0 test %eax,%eax - 412ebc: b8 20 1b 4a 00 mov $0x4a1b20,%eax - 412ec1: 48 0f 4e c2 cmovle %rdx,%rax - 412ec5: 48 89 83 d8 00 00 00 mov %rax,0xd8(%rbx) - 412ecc: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 412ed3: 48 c7 80 30 01 00 00 movq $0x4a1b20,0x130(%rax) - 412eda: 20 1b 4a 00 - 412ede: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 412ee5: ff 50 20 callq *0x20(%rax) - 412ee8: 48 81 c4 98 00 00 00 add $0x98,%rsp - 412eef: 5b pop %rbx - 412ef0: 5d pop %rbp - 412ef1: c3 retq - 412ef2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 412ef8: 48 8b 6c 24 30 mov 0x30(%rsp),%rbp - 412efd: 48 85 ed test %rbp,%rbp - 412f00: 0f 84 6e ff ff ff je 412e74 <_IO_file_underflow_mmap+0x44> - 412f06: e8 85 cc 02 00 callq 43fb90 <__getpagesize> - 412f0b: 48 8b 7b 38 mov 0x38(%rbx),%rdi - 412f0f: 48 98 cltq - 412f11: 48 89 c6 mov %rax,%rsi - 412f14: 48 8d 54 05 ff lea -0x1(%rbp,%rax,1),%rdx - 412f19: 48 f7 de neg %rsi - 412f1c: 48 89 f9 mov %rdi,%rcx - 412f1f: 48 21 f2 and %rsi,%rdx - 412f22: 49 89 f8 mov %rdi,%r8 - 412f25: 48 f7 d1 not %rcx - 412f28: 48 03 4b 40 add 0x40(%rbx),%rcx - 412f2c: 48 01 c8 add %rcx,%rax - 412f2f: 48 21 c6 and %rax,%rsi - 412f32: 48 39 f2 cmp %rsi,%rdx - 412f35: 0f 82 8d 00 00 00 jb 412fc8 <_IO_file_underflow_mmap+0x198> - 412f3b: 0f 87 aa 00 00 00 ja 412feb <_IO_file_underflow_mmap+0x1bb> - 412f41: 48 01 fd add %rdi,%rbp - 412f44: 48 89 6b 40 mov %rbp,0x40(%rbx) - 412f48: 48 8b 53 10 mov 0x10(%rbx),%rdx - 412f4c: 48 2b 53 08 sub 0x8(%rbx),%rdx - 412f50: 48 89 ee mov %rbp,%rsi - 412f53: 48 8b 83 90 00 00 00 mov 0x90(%rbx),%rax - 412f5a: 4c 29 c6 sub %r8,%rsi - 412f5d: 48 89 7b 18 mov %rdi,0x18(%rbx) - 412f61: 48 29 d0 sub %rdx,%rax - 412f64: 48 39 f0 cmp %rsi,%rax - 412f67: 48 89 83 90 00 00 00 mov %rax,0x90(%rbx) - 412f6e: 7d 40 jge 412fb0 <_IO_file_underflow_mmap+0x180> - 412f70: 48 01 c7 add %rax,%rdi - 412f73: 31 d2 xor %edx,%edx - 412f75: 48 89 6b 10 mov %rbp,0x10(%rbx) - 412f79: 48 89 7b 08 mov %rdi,0x8(%rbx) - 412f7d: 8b 7b 70 mov 0x70(%rbx),%edi - 412f80: e8 ab f5 02 00 callq 442530 <__libc_lseek> - 412f85: 48 8b 53 40 mov 0x40(%rbx),%rdx - 412f89: 48 2b 53 38 sub 0x38(%rbx),%rdx - 412f8d: 48 39 d0 cmp %rdx,%rax - 412f90: 0f 84 86 00 00 00 je 41301c <_IO_file_underflow_mmap+0x1ec> - 412f96: 83 0b 20 orl $0x20,(%rbx) - 412f99: 48 8b 43 08 mov 0x8(%rbx),%rax - 412f9d: 48 3b 43 10 cmp 0x10(%rbx),%rax - 412fa1: 73 15 jae 412fb8 <_IO_file_underflow_mmap+0x188> - 412fa3: 0f b6 00 movzbl (%rax),%eax - 412fa6: 48 81 c4 98 00 00 00 add $0x98,%rsp - 412fad: 5b pop %rbx - 412fae: 5d pop %rbp - 412faf: c3 retq - 412fb0: 48 89 6b 08 mov %rbp,0x8(%rbx) - 412fb4: 48 89 6b 10 mov %rbp,0x10(%rbx) - 412fb8: 83 0b 10 orl $0x10,(%rbx) - 412fbb: b8 ff ff ff ff mov $0xffffffff,%eax - 412fc0: e9 23 ff ff ff jmpq 412ee8 <_IO_file_underflow_mmap+0xb8> - 412fc5: 0f 1f 00 nopl (%rax) - 412fc8: 48 01 d7 add %rdx,%rdi - 412fcb: 48 29 d6 sub %rdx,%rsi - 412fce: e8 dd cc 02 00 callq 43fcb0 <__munmap> - 412fd3: 48 8b 7b 38 mov 0x38(%rbx),%rdi - 412fd7: 48 89 fd mov %rdi,%rbp - 412fda: 48 03 6c 24 30 add 0x30(%rsp),%rbp - 412fdf: 49 89 f8 mov %rdi,%r8 - 412fe2: 48 89 6b 40 mov %rbp,0x40(%rbx) - 412fe6: e9 5d ff ff ff jmpq 412f48 <_IO_file_underflow_mmap+0x118> - 412feb: 31 c0 xor %eax,%eax - 412fed: b9 01 00 00 00 mov $0x1,%ecx - 412ff2: e8 59 f5 02 00 callq 442550 <__mremap> - 412ff7: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 412ffb: 0f 84 73 fe ff ff je 412e74 <_IO_file_underflow_mmap+0x44> - 413001: 48 89 c5 mov %rax,%rbp - 413004: 48 03 6c 24 30 add 0x30(%rsp),%rbp - 413009: 48 89 43 38 mov %rax,0x38(%rbx) - 41300d: 49 89 c0 mov %rax,%r8 - 413010: 48 89 c7 mov %rax,%rdi - 413013: 48 89 6b 40 mov %rbp,0x40(%rbx) - 413017: e9 2c ff ff ff jmpq 412f48 <_IO_file_underflow_mmap+0x118> - 41301c: 48 89 83 90 00 00 00 mov %rax,0x90(%rbx) - 413023: e9 71 ff ff ff jmpq 412f99 <_IO_file_underflow_mmap+0x169> - 413028: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 41302f: 00 - -0000000000413030 <_IO_new_file_init>: - 413030: 55 push %rbp - 413031: 53 push %rbx - 413032: 48 c7 c5 ff ff ff ff mov $0xffffffffffffffff,%rbp - 413039: 48 89 fb mov %rdi,%rbx - 41303c: 48 83 ec 08 sub $0x8,%rsp - 413040: 81 0f 0c 24 00 00 orl $0x240c,(%rdi) - 413046: 48 89 af 90 00 00 00 mov %rbp,0x90(%rdi) - 41304d: e8 9e 16 00 00 callq 4146f0 <_IO_link_in> - 413052: 89 6b 70 mov %ebp,0x70(%rbx) - 413055: 48 83 c4 08 add $0x8,%rsp - 413059: 5b pop %rbx - 41305a: 5d pop %rbp - 41305b: c3 retq - 41305c: 0f 1f 40 00 nopl 0x0(%rax) - -0000000000413060 <_IO_file_open>: - 413060: 55 push %rbp - 413061: 53 push %rbx - 413062: 48 89 fb mov %rdi,%rbx - 413065: 48 89 f7 mov %rsi,%rdi - 413068: 48 63 f2 movslq %edx,%rsi - 41306b: 48 83 ec 18 sub $0x18,%rsp - 41306f: f6 43 74 02 testb $0x2,0x74(%rbx) - 413073: 74 6b je 4130e0 <_IO_file_open+0x80> - 413075: 48 63 d1 movslq %ecx,%rdx - 413078: b8 02 00 00 00 mov $0x2,%eax - 41307d: 0f 05 syscall - 41307f: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 413085: 89 c5 mov %eax,%ebp - 413087: 77 47 ja 4130d0 <_IO_file_open+0x70> - 413089: 85 ed test %ebp,%ebp - 41308b: 78 4f js 4130dc <_IO_file_open+0x7c> - 41308d: 8b 13 mov (%rbx),%edx - 41308f: 44 89 c0 mov %r8d,%eax - 413092: 41 81 e0 04 10 00 00 and $0x1004,%r8d - 413099: 25 0c 10 00 00 and $0x100c,%eax - 41309e: 89 6b 70 mov %ebp,0x70(%rbx) - 4130a1: 81 e2 f3 ef ff ff and $0xffffeff3,%edx - 4130a7: 09 d0 or %edx,%eax - 4130a9: 41 81 f8 04 10 00 00 cmp $0x1004,%r8d - 4130b0: 89 03 mov %eax,(%rbx) - 4130b2: 74 4c je 413100 <_IO_file_open+0xa0> - 4130b4: 48 89 df mov %rbx,%rdi - 4130b7: e8 34 16 00 00 callq 4146f0 <_IO_link_in> - 4130bc: 48 89 d8 mov %rbx,%rax - 4130bf: 48 83 c4 18 add $0x18,%rsp - 4130c3: 5b pop %rbx - 4130c4: 5d pop %rbp - 4130c5: c3 retq - 4130c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4130cd: 00 00 00 - 4130d0: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx - 4130d7: f7 d8 neg %eax - 4130d9: 64 89 02 mov %eax,%fs:(%rdx) - 4130dc: 31 c0 xor %eax,%eax - 4130de: eb df jmp 4130bf <_IO_file_open+0x5f> - 4130e0: 89 ca mov %ecx,%edx - 4130e2: 31 c0 xor %eax,%eax - 4130e4: 44 89 44 24 0c mov %r8d,0xc(%rsp) - 4130e9: e8 32 c0 02 00 callq 43f120 <__libc_open> - 4130ee: 44 8b 44 24 0c mov 0xc(%rsp),%r8d - 4130f3: 89 c5 mov %eax,%ebp - 4130f5: eb 92 jmp 413089 <_IO_file_open+0x29> - 4130f7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 4130fe: 00 00 - 413100: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 413107: 31 f6 xor %esi,%esi - 413109: ba 02 00 00 00 mov $0x2,%edx - 41310e: 48 89 df mov %rbx,%rdi - 413111: ff 90 80 00 00 00 callq *0x80(%rax) - 413117: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 41311b: 75 97 jne 4130b4 <_IO_file_open+0x54> - 41311d: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx - 413124: 64 83 3a 1d cmpl $0x1d,%fs:(%rdx) - 413128: 74 8a je 4130b4 <_IO_file_open+0x54> - 41312a: 48 63 fd movslq %ebp,%rdi - 41312d: b8 03 00 00 00 mov $0x3,%eax - 413132: 0f 05 syscall - 413134: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 41313a: 76 a0 jbe 4130dc <_IO_file_open+0x7c> - 41313c: f7 d8 neg %eax - 41313e: 64 89 02 mov %eax,%fs:(%rdx) - 413141: 31 c0 xor %eax,%eax - 413143: e9 77 ff ff ff jmpq 4130bf <_IO_file_open+0x5f> - 413148: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 41314f: 00 - -0000000000413150 <_IO_new_file_attach>: - 413150: 83 7f 70 ff cmpl $0xffffffff,0x70(%rdi) - 413154: 75 5a jne 4131b0 <_IO_new_file_attach+0x60> - 413156: 8b 07 mov (%rdi),%eax - 413158: 41 54 push %r12 - 41315a: b9 03 00 00 00 mov $0x3,%ecx - 41315f: 55 push %rbp - 413160: 48 c7 c5 d0 ff ff ff mov $0xffffffffffffffd0,%rbp - 413167: ba 01 00 00 00 mov $0x1,%edx - 41316c: 53 push %rbx - 41316d: 89 77 70 mov %esi,0x70(%rdi) - 413170: 48 89 fb mov %rdi,%rbx - 413173: 83 e0 f3 and $0xfffffff3,%eax - 413176: 31 f6 xor %esi,%esi - 413178: 48 c7 87 90 00 00 00 movq $0xffffffffffffffff,0x90(%rdi) - 41317f: ff ff ff ff - 413183: 83 c8 40 or $0x40,%eax - 413186: 64 44 8b 65 00 mov %fs:0x0(%rbp),%r12d - 41318b: 89 07 mov %eax,(%rdi) - 41318d: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax - 413194: ff 50 48 callq *0x48(%rax) - 413197: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 41319b: 74 1b je 4131b8 <_IO_new_file_attach+0x68> - 41319d: 64 44 89 65 00 mov %r12d,%fs:0x0(%rbp) - 4131a2: 48 89 d8 mov %rbx,%rax - 4131a5: 5b pop %rbx - 4131a6: 5d pop %rbp - 4131a7: 41 5c pop %r12 - 4131a9: c3 retq - 4131aa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4131b0: 31 c0 xor %eax,%eax - 4131b2: c3 retq - 4131b3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4131b8: 31 c0 xor %eax,%eax - 4131ba: 64 83 7d 00 1d cmpl $0x1d,%fs:0x0(%rbp) - 4131bf: 74 dc je 41319d <_IO_new_file_attach+0x4d> - 4131c1: eb e2 jmp 4131a5 <_IO_new_file_attach+0x55> - 4131c3: 0f 1f 00 nopl (%rax) - 4131c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4131cd: 00 00 00 - -00000000004131d0 <_IO_new_do_write>: - 4131d0: 31 c0 xor %eax,%eax - 4131d2: 48 85 d2 test %rdx,%rdx - 4131d5: 75 09 jne 4131e0 <_IO_new_do_write+0x10> - 4131d7: c3 retq - 4131d8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 4131df: 00 - 4131e0: 41 55 push %r13 - 4131e2: 41 54 push %r12 - 4131e4: 49 89 f4 mov %rsi,%r12 - 4131e7: 55 push %rbp - 4131e8: 53 push %rbx - 4131e9: 48 89 d5 mov %rdx,%rbp - 4131ec: 48 89 fb mov %rdi,%rbx - 4131ef: 48 83 ec 08 sub $0x8,%rsp - 4131f3: f7 07 00 10 00 00 testl $0x1000,(%rdi) - 4131f9: 0f 85 a1 00 00 00 jne 4132a0 <_IO_new_do_write+0xd0> - 4131ff: 48 8b 47 10 mov 0x10(%rdi),%rax - 413203: 48 8b 77 20 mov 0x20(%rdi),%rsi - 413207: 48 39 f0 cmp %rsi,%rax - 41320a: 74 2a je 413236 <_IO_new_do_write+0x66> - 41320c: 48 29 c6 sub %rax,%rsi - 41320f: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax - 413216: ba 01 00 00 00 mov $0x1,%edx - 41321b: ff 90 80 00 00 00 callq *0x80(%rax) - 413221: 48 89 c2 mov %rax,%rdx - 413224: b8 ff ff ff ff mov $0xffffffff,%eax - 413229: 48 83 fa ff cmp $0xffffffffffffffff,%rdx - 41322d: 74 62 je 413291 <_IO_new_do_write+0xc1> - 41322f: 48 89 93 90 00 00 00 mov %rdx,0x90(%rbx) - 413236: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 41323d: 48 89 ea mov %rbp,%rdx - 413240: 4c 89 e6 mov %r12,%rsi - 413243: 48 89 df mov %rbx,%rdi - 413246: ff 50 78 callq *0x78(%rax) - 413249: 49 89 c5 mov %rax,%r13 - 41324c: 0f b7 83 80 00 00 00 movzwl 0x80(%rbx),%eax - 413253: 4d 85 ed test %r13,%r13 - 413256: 74 05 je 41325d <_IO_new_do_write+0x8d> - 413258: 66 85 c0 test %ax,%ax - 41325b: 75 63 jne 4132c0 <_IO_new_do_write+0xf0> - 41325d: 8b 93 c0 00 00 00 mov 0xc0(%rbx),%edx - 413263: 48 8b 43 38 mov 0x38(%rbx),%rax - 413267: 85 d2 test %edx,%edx - 413269: 48 89 43 18 mov %rax,0x18(%rbx) - 41326d: 48 89 43 08 mov %rax,0x8(%rbx) - 413271: 48 89 43 10 mov %rax,0x10(%rbx) - 413275: 48 89 43 28 mov %rax,0x28(%rbx) - 413279: 48 89 43 20 mov %rax,0x20(%rbx) - 41327d: 7e 31 jle 4132b0 <_IO_new_do_write+0xe0> - 41327f: 48 8b 43 40 mov 0x40(%rbx),%rax - 413283: 48 89 43 30 mov %rax,0x30(%rbx) - 413287: 31 c0 xor %eax,%eax - 413289: 4c 39 ed cmp %r13,%rbp - 41328c: 0f 95 c0 setne %al - 41328f: f7 d8 neg %eax - 413291: 48 83 c4 08 add $0x8,%rsp - 413295: 5b pop %rbx - 413296: 5d pop %rbp - 413297: 41 5c pop %r12 - 413299: 41 5d pop %r13 - 41329b: c3 retq - 41329c: 0f 1f 40 00 nopl 0x0(%rax) - 4132a0: 48 c7 87 90 00 00 00 movq $0xffffffffffffffff,0x90(%rdi) - 4132a7: ff ff ff ff - 4132ab: eb 89 jmp 413236 <_IO_new_do_write+0x66> - 4132ad: 0f 1f 00 nopl (%rax) - 4132b0: f7 03 02 02 00 00 testl $0x202,(%rbx) - 4132b6: 75 cb jne 413283 <_IO_new_do_write+0xb3> - 4132b8: eb c5 jmp 41327f <_IO_new_do_write+0xaf> - 4132ba: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4132c0: 8d 78 ff lea -0x1(%rax),%edi - 4132c3: 44 89 ea mov %r13d,%edx - 4132c6: 4c 89 e6 mov %r12,%rsi - 4132c9: e8 f2 26 00 00 callq 4159c0 <_IO_adjust_column> - 4132ce: 83 c0 01 add $0x1,%eax - 4132d1: 66 89 83 80 00 00 00 mov %ax,0x80(%rbx) - 4132d8: e9 80 ff ff ff jmpq 41325d <_IO_new_do_write+0x8d> - 4132dd: 0f 1f 00 nopl (%rax) - -00000000004132e0 <_IO_new_file_close_it>: - 4132e0: 8b 47 70 mov 0x70(%rdi),%eax - 4132e3: 83 f8 ff cmp $0xffffffff,%eax - 4132e6: 0f 84 fe 00 00 00 je 4133ea <_IO_new_file_close_it+0x10a> - 4132ec: 41 54 push %r12 - 4132ee: 55 push %rbp - 4132ef: 45 31 e4 xor %r12d,%r12d - 4132f2: 53 push %rbx - 4132f3: 8b 07 mov (%rdi),%eax - 4132f5: 48 89 fb mov %rdi,%rbx - 4132f8: 25 08 08 00 00 and $0x808,%eax - 4132fd: 3d 00 08 00 00 cmp $0x800,%eax - 413302: 0f 84 08 01 00 00 je 413410 <_IO_new_file_close_it+0x130> - 413308: 48 89 df mov %rbx,%rdi - 41330b: 31 ed xor %ebp,%ebp - 41330d: e8 8e 30 00 00 callq 4163a0 <_IO_unsave_markers> - 413312: f6 43 74 20 testb $0x20,0x74(%rbx) - 413316: 0f 84 d4 00 00 00 je 4133f0 <_IO_new_file_close_it+0x110> - 41331c: 8b 83 c0 00 00 00 mov 0xc0(%rbx),%eax - 413322: 85 c0 test %eax,%eax - 413324: 7e 5a jle 413380 <_IO_new_file_close_it+0xa0> - 413326: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 41332d: 48 83 78 40 00 cmpq $0x0,0x40(%rax) - 413332: 74 08 je 41333c <_IO_new_file_close_it+0x5c> - 413334: 48 89 df mov %rbx,%rdi - 413337: e8 e4 14 05 00 callq 464820 <_IO_free_wbackup_area> - 41333c: 31 c9 xor %ecx,%ecx - 41333e: 31 d2 xor %edx,%edx - 413340: 31 f6 xor %esi,%esi - 413342: 48 89 df mov %rbx,%rdi - 413345: e8 46 05 05 00 callq 463890 <_IO_wsetb> - 41334a: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 413351: 48 c7 40 10 00 00 00 movq $0x0,0x10(%rax) - 413358: 00 - 413359: 48 c7 00 00 00 00 00 movq $0x0,(%rax) - 413360: 48 c7 40 08 00 00 00 movq $0x0,0x8(%rax) - 413367: 00 - 413368: 48 c7 40 20 00 00 00 movq $0x0,0x20(%rax) - 41336f: 00 - 413370: 48 c7 40 18 00 00 00 movq $0x0,0x18(%rax) - 413377: 00 - 413378: 48 c7 40 28 00 00 00 movq $0x0,0x28(%rax) - 41337f: 00 - 413380: 31 c9 xor %ecx,%ecx - 413382: 31 d2 xor %edx,%edx - 413384: 31 f6 xor %esi,%esi - 413386: 48 89 df mov %rbx,%rdi - 413389: e8 12 1a 00 00 callq 414da0 <_IO_setb> - 41338e: 48 c7 43 18 00 00 00 movq $0x0,0x18(%rbx) - 413395: 00 - 413396: 48 c7 43 08 00 00 00 movq $0x0,0x8(%rbx) - 41339d: 00 - 41339e: 48 89 df mov %rbx,%rdi - 4133a1: 48 c7 43 10 00 00 00 movq $0x0,0x10(%rbx) - 4133a8: 00 - 4133a9: 48 c7 43 28 00 00 00 movq $0x0,0x28(%rbx) - 4133b0: 00 - 4133b1: 48 c7 43 20 00 00 00 movq $0x0,0x20(%rbx) - 4133b8: 00 - 4133b9: 48 c7 43 30 00 00 00 movq $0x0,0x30(%rbx) - 4133c0: 00 - 4133c1: e8 8a 10 00 00 callq 414450 <_IO_un_link> - 4133c6: 85 ed test %ebp,%ebp - 4133c8: 44 89 e0 mov %r12d,%eax - 4133cb: c7 03 0c 24 ad fb movl $0xfbad240c,(%rbx) - 4133d1: c7 43 70 ff ff ff ff movl $0xffffffff,0x70(%rbx) - 4133d8: 48 c7 83 90 00 00 00 movq $0xffffffffffffffff,0x90(%rbx) - 4133df: ff ff ff ff - 4133e3: 0f 45 c5 cmovne %ebp,%eax - 4133e6: 5b pop %rbx - 4133e7: 5d pop %rbp - 4133e8: 41 5c pop %r12 - 4133ea: f3 c3 repz retq - 4133ec: 0f 1f 40 00 nopl 0x0(%rax) - 4133f0: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 4133f7: 48 89 df mov %rbx,%rdi - 4133fa: ff 90 88 00 00 00 callq *0x88(%rax) - 413400: 89 c5 mov %eax,%ebp - 413402: e9 15 ff ff ff jmpq 41331c <_IO_new_file_close_it+0x3c> - 413407: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 41340e: 00 00 - 413410: 8b 97 c0 00 00 00 mov 0xc0(%rdi),%edx - 413416: 85 d2 test %edx,%edx - 413418: 7e 26 jle 413440 <_IO_new_file_close_it+0x160> - 41341a: 48 8b 87 a0 00 00 00 mov 0xa0(%rdi),%rax - 413421: 48 8b 70 18 mov 0x18(%rax),%rsi - 413425: 48 8b 50 20 mov 0x20(%rax),%rdx - 413429: 48 29 f2 sub %rsi,%rdx - 41342c: 48 c1 fa 02 sar $0x2,%rdx - 413430: e8 fb d5 ff ff callq 410a30 <_IO_wdo_write> - 413435: 41 89 c4 mov %eax,%r12d - 413438: e9 cb fe ff ff jmpq 413308 <_IO_new_file_close_it+0x28> - 41343d: 0f 1f 00 nopl (%rax) - 413440: 48 8b 77 20 mov 0x20(%rdi),%rsi - 413444: 48 8b 57 28 mov 0x28(%rdi),%rdx - 413448: 48 29 f2 sub %rsi,%rdx - 41344b: e8 80 fd ff ff callq 4131d0 <_IO_new_do_write> - 413450: 41 89 c4 mov %eax,%r12d - 413453: e9 b0 fe ff ff jmpq 413308 <_IO_new_file_close_it+0x28> - 413458: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 41345f: 00 - -0000000000413460 <_IO_new_file_fopen>: - 413460: 41 57 push %r15 - 413462: 41 56 push %r14 - 413464: 41 55 push %r13 - 413466: 41 54 push %r12 - 413468: 55 push %rbp - 413469: 53 push %rbx - 41346a: 48 83 ec 28 sub $0x28,%rsp - 41346e: 83 7f 70 ff cmpl $0xffffffff,0x70(%rdi) - 413472: 75 54 jne 4134c8 <_IO_new_file_fopen+0x68> - 413474: 0f b6 02 movzbl (%rdx),%eax - 413477: 3c 72 cmp $0x72,%al - 413479: 0f 84 51 05 00 00 je 4139d0 <_IO_new_file_fopen+0x570> - 41347f: 3c 77 cmp $0x77,%al - 413481: 74 5d je 4134e0 <_IO_new_file_fopen+0x80> - 413483: 3c 61 cmp $0x61,%al - 413485: 0f 84 25 05 00 00 je 4139b0 <_IO_new_file_fopen+0x550> - 41348b: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 413492: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) - 413499: 48 83 c4 28 add $0x28,%rsp - 41349d: 31 c0 xor %eax,%eax - 41349f: 5b pop %rbx - 4134a0: 5d pop %rbp - 4134a1: 41 5c pop %r12 - 4134a3: 41 5d pop %r13 - 4134a5: 41 5e pop %r14 - 4134a7: 41 5f pop %r15 - 4134a9: c3 retq - 4134aa: 48 c7 c5 d0 ff ff ff mov $0xffffffffffffffd0,%rbp - 4134b1: 48 89 df mov %rbx,%rdi - 4134b4: 64 44 8b 65 00 mov %fs:0x0(%rbp),%r12d - 4134b9: e8 22 fe ff ff callq 4132e0 <_IO_new_file_close_it> - 4134be: 64 44 89 65 00 mov %r12d,%fs:0x0(%rbp) - 4134c3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4134c8: 31 c0 xor %eax,%eax - 4134ca: 48 83 c4 28 add $0x28,%rsp - 4134ce: 5b pop %rbx - 4134cf: 5d pop %rbp - 4134d0: 41 5c pop %r12 - 4134d2: 41 5d pop %r13 - 4134d4: 41 5e pop %r14 - 4134d6: 41 5f pop %r15 - 4134d8: c3 retq - 4134d9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4134e0: 41 b8 04 00 00 00 mov $0x4,%r8d - 4134e6: b8 01 00 00 00 mov $0x1,%eax - 4134eb: 41 ba 40 02 00 00 mov $0x240,%r10d - 4134f1: 44 0f b6 4a 01 movzbl 0x1(%rdx),%r9d - 4134f6: 4c 8d 62 01 lea 0x1(%rdx),%r12 - 4134fa: 41 80 f9 63 cmp $0x63,%r9b - 4134fe: 0f 84 bb 05 00 00 je 413abf <_IO_new_file_fopen+0x65f> - 413504: 0f 8f ee 03 00 00 jg 4138f8 <_IO_new_file_fopen+0x498> - 41350a: 41 80 f9 2b cmp $0x2b,%r9b - 41350e: 0f 84 c3 05 00 00 je 413ad7 <_IO_new_file_fopen+0x677> - 413514: 41 80 f9 62 cmp $0x62,%r9b - 413518: 74 16 je 413530 <_IO_new_file_fopen+0xd0> - 41351a: 45 84 c9 test %r9b,%r9b - 41351d: 49 89 d4 mov %rdx,%r12 - 413520: 0f 84 2a 01 00 00 je 413650 <_IO_new_file_fopen+0x1f0> - 413526: 49 89 d4 mov %rdx,%r12 - 413529: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 413530: 44 0f b6 4a 02 movzbl 0x2(%rdx),%r9d - 413535: 4c 8d 5a 02 lea 0x2(%rdx),%r11 - 413539: 41 80 f9 63 cmp $0x63,%r9b - 41353d: 0f 84 ae 05 00 00 je 413af1 <_IO_new_file_fopen+0x691> - 413543: 0f 8f 07 04 00 00 jg 413950 <_IO_new_file_fopen+0x4f0> - 413549: 41 80 f9 2b cmp $0x2b,%r9b - 41354d: 0f 84 a7 05 00 00 je 413afa <_IO_new_file_fopen+0x69a> - 413553: 41 80 f9 62 cmp $0x62,%r9b - 413557: 0f 84 12 05 00 00 je 413a6f <_IO_new_file_fopen+0x60f> - 41355d: 45 84 c9 test %r9b,%r9b - 413560: 0f 84 ea 00 00 00 je 413650 <_IO_new_file_fopen+0x1f0> - 413566: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41356d: 00 00 00 - 413570: 44 0f b6 4a 03 movzbl 0x3(%rdx),%r9d - 413575: 4c 8d 5a 03 lea 0x3(%rdx),%r11 - 413579: 41 80 f9 63 cmp $0x63,%r9b - 41357d: 0f 84 9f 05 00 00 je 413b22 <_IO_new_file_fopen+0x6c2> - 413583: 0f 8f f7 03 00 00 jg 413980 <_IO_new_file_fopen+0x520> - 413589: 41 80 f9 2b cmp $0x2b,%r9b - 41358d: 0f 84 7b 05 00 00 je 413b0e <_IO_new_file_fopen+0x6ae> - 413593: 41 80 f9 62 cmp $0x62,%r9b - 413597: 0f 84 f9 04 00 00 je 413a96 <_IO_new_file_fopen+0x636> - 41359d: 45 84 c9 test %r9b,%r9b - 4135a0: 0f 84 aa 00 00 00 je 413650 <_IO_new_file_fopen+0x1f0> - 4135a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4135ad: 00 00 00 - 4135b0: 44 0f b6 4a 04 movzbl 0x4(%rdx),%r9d - 4135b5: 4c 8d 5a 04 lea 0x4(%rdx),%r11 - 4135b9: 41 80 f9 63 cmp $0x63,%r9b - 4135bd: 0f 84 85 05 00 00 je 413b48 <_IO_new_file_fopen+0x6e8> - 4135c3: 0f 8f 17 04 00 00 jg 4139e0 <_IO_new_file_fopen+0x580> - 4135c9: 41 80 f9 2b cmp $0x2b,%r9b - 4135cd: 0f 84 61 05 00 00 je 413b34 <_IO_new_file_fopen+0x6d4> - 4135d3: 41 80 f9 62 cmp $0x62,%r9b - 4135d7: 0f 84 c5 04 00 00 je 413aa2 <_IO_new_file_fopen+0x642> - 4135dd: 45 84 c9 test %r9b,%r9b - 4135e0: 74 6e je 413650 <_IO_new_file_fopen+0x1f0> - 4135e2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4135e8: 44 0f b6 4a 05 movzbl 0x5(%rdx),%r9d - 4135ed: 4c 8d 5a 05 lea 0x5(%rdx),%r11 - 4135f1: 41 80 f9 63 cmp $0x63,%r9b - 4135f5: 0f 84 7c 05 00 00 je 413b77 <_IO_new_file_fopen+0x717> - 4135fb: 0f 8f 0f 04 00 00 jg 413a10 <_IO_new_file_fopen+0x5b0> - 413601: 41 80 f9 2b cmp $0x2b,%r9b - 413605: 0f 84 58 05 00 00 je 413b63 <_IO_new_file_fopen+0x703> - 41360b: 41 80 f9 62 cmp $0x62,%r9b - 41360f: 0f 84 99 04 00 00 je 413aae <_IO_new_file_fopen+0x64e> - 413615: 45 84 c9 test %r9b,%r9b - 413618: 74 36 je 413650 <_IO_new_file_fopen+0x1f0> - 41361a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 413620: 4c 8d 4a 06 lea 0x6(%rdx),%r9 - 413624: 0f b6 52 06 movzbl 0x6(%rdx),%edx - 413628: 80 fa 63 cmp $0x63,%dl - 41362b: 0f 84 88 05 00 00 je 413bb9 <_IO_new_file_fopen+0x759> - 413631: 0f 8f 09 04 00 00 jg 413a40 <_IO_new_file_fopen+0x5e0> - 413637: 80 fa 2b cmp $0x2b,%dl - 41363a: 0f 84 65 05 00 00 je 413ba5 <_IO_new_file_fopen+0x745> - 413640: 80 fa 62 cmp $0x62,%dl - 413643: 4d 0f 44 e1 cmove %r9,%r12 - 413647: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 41364e: 00 00 - 413650: 44 89 d2 mov %r10d,%edx - 413653: 41 89 c9 mov %ecx,%r9d - 413656: b9 b6 01 00 00 mov $0x1b6,%ecx - 41365b: 09 c2 or %eax,%edx - 41365d: 48 89 fb mov %rdi,%rbx - 413660: e8 fb f9 ff ff callq 413060 <_IO_file_open> - 413665: 48 85 c0 test %rax,%rax - 413668: 48 89 c5 mov %rax,%rbp - 41366b: 0f 84 57 fe ff ff je 4134c8 <_IO_new_file_fopen+0x68> - 413671: 49 8d 7c 24 01 lea 0x1(%r12),%rdi - 413676: be 30 1c 4a 00 mov $0x4a1c30,%esi - 41367b: e8 a0 cc fe ff callq 400320 <__rela_iplt_end+0x58> - 413680: 48 85 c0 test %rax,%rax - 413683: 49 89 c5 mov %rax,%r13 - 413686: 0f 84 f4 03 00 00 je 413a80 <_IO_new_file_fopen+0x620> - 41368c: 4c 8d 78 05 lea 0x5(%rax),%r15 - 413690: be 2c 00 00 00 mov $0x2c,%esi - 413695: 4c 89 ff mov %r15,%rdi - 413698: e8 43 95 01 00 callq 42cbe0 <__strchrnul> - 41369d: 4c 29 f8 sub %r15,%rax - 4136a0: 48 8d 78 03 lea 0x3(%rax),%rdi - 4136a4: 49 89 c6 mov %rax,%r14 - 4136a7: e8 64 a3 00 00 callq 41da10 <__libc_malloc> - 4136ac: 48 85 c0 test %rax,%rax - 4136af: 49 89 c4 mov %rax,%r12 - 4136b2: 0f 84 f2 fd ff ff je 4134aa <_IO_new_file_fopen+0x4a> - 4136b8: 4c 89 f2 mov %r14,%rdx - 4136bb: 4c 89 fe mov %r15,%rsi - 4136be: 48 89 c7 mov %rax,%rdi - 4136c1: e8 fa 2e 01 00 callq 4265c0 <__mempcpy> - 4136c6: c6 00 00 movb $0x0,(%rax) - 4136c9: 45 0f b6 04 24 movzbl (%r12),%r8d - 4136ce: 45 84 c0 test %r8b,%r8b - 4136d1: 0f 84 08 05 00 00 je 413bdf <_IO_new_file_fopen+0x77f> - 4136d7: 4c 8b 1d 0a f0 09 00 mov 0x9f00a(%rip),%r11 # 4b26e8 <_nl_C_locobj+0x68> - 4136de: 4c 8b 35 13 f0 09 00 mov 0x9f013(%rip),%r14 # 4b26f8 <_nl_C_locobj+0x78> - 4136e5: 4d 89 e1 mov %r12,%r9 - 4136e8: 4c 89 e0 mov %r12,%rax - 4136eb: 45 31 ff xor %r15d,%r15d - 4136ee: 49 ba 07 40 00 00 00 movabs $0x8000000004007,%r10 - 4136f5: 00 08 00 - 4136f8: eb 26 jmp 413720 <_IO_new_file_fopen+0x2c0> - 4136fa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 413700: 41 80 f8 2f cmp $0x2f,%r8b - 413704: 0f 84 26 02 00 00 je 413930 <_IO_new_file_fopen+0x4d0> - 41370a: 49 83 c1 01 add $0x1,%r9 - 41370e: 45 0f b6 01 movzbl (%r9),%r8d - 413712: 45 84 c0 test %r8b,%r8b - 413715: 74 54 je 41376b <_IO_new_file_fopen+0x30b> - 413717: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 41371e: 00 00 - 413720: 49 0f be f8 movsbq %r8b,%rdi - 413724: 41 8d 48 d4 lea -0x2c(%r8),%ecx - 413728: ba 01 00 00 00 mov $0x1,%edx - 41372d: 41 0f b7 34 7b movzwl (%r11,%rdi,2),%esi - 413732: 66 c1 ee 03 shr $0x3,%si - 413736: 83 e6 01 and $0x1,%esi - 413739: 80 f9 33 cmp $0x33,%cl - 41373c: 77 10 ja 41374e <_IO_new_file_fopen+0x2ee> - 41373e: 4c 89 d2 mov %r10,%rdx - 413741: 48 d3 ea shr %cl,%rdx - 413744: 83 e2 01 and $0x1,%edx - 413747: 48 83 f2 01 xor $0x1,%rdx - 41374b: 83 e2 01 and $0x1,%edx - 41374e: 40 38 f2 cmp %sil,%dl - 413751: 77 ad ja 413700 <_IO_new_file_fopen+0x2a0> - 413753: 41 8b 14 be mov (%r14,%rdi,4),%edx - 413757: 49 83 c1 01 add $0x1,%r9 - 41375b: 48 83 c0 01 add $0x1,%rax - 41375f: 88 50 ff mov %dl,-0x1(%rax) - 413762: 45 0f b6 01 movzbl (%r9),%r8d - 413766: 45 84 c0 test %r8b,%r8b - 413769: 75 b5 jne 413720 <_IO_new_file_fopen+0x2c0> - 41376b: 41 83 ff 01 cmp $0x1,%r15d - 41376f: 7f 17 jg 413788 <_IO_new_file_fopen+0x328> - 413771: 45 85 ff test %r15d,%r15d - 413774: 48 8d 50 01 lea 0x1(%rax),%rdx - 413778: c6 00 2f movb $0x2f,(%rax) - 41377b: 0f 85 56 04 00 00 jne 413bd7 <_IO_new_file_fopen+0x777> - 413781: 48 8d 42 01 lea 0x1(%rdx),%rax - 413785: c6 02 2f movb $0x2f,(%rdx) - 413788: c6 00 00 movb $0x0,(%rax) - 41378b: 41 80 7c 24 02 00 cmpb $0x0,0x2(%r12) - 413791: 75 22 jne 4137b5 <_IO_new_file_fopen+0x355> - 413793: 48 8b 0d 5e ef 09 00 mov 0x9ef5e(%rip),%rcx # 4b26f8 <_nl_C_locobj+0x78> - 41379a: 31 c0 xor %eax,%eax - 41379c: 0f 1f 40 00 nopl 0x0(%rax) - 4137a0: 49 0f be 54 05 05 movsbq 0x5(%r13,%rax,1),%rdx - 4137a6: 8b 14 91 mov (%rcx,%rdx,4),%edx - 4137a9: 41 88 14 04 mov %dl,(%r12,%rax,1) - 4137ad: 48 83 c0 01 add $0x1,%rax - 4137b1: 84 d2 test %dl,%dl - 4137b3: 75 eb jne 4137a0 <_IO_new_file_fopen+0x340> - 4137b5: 4c 89 e6 mov %r12,%rsi - 4137b8: 48 89 e7 mov %rsp,%rdi - 4137bb: e8 10 af 02 00 callq 43e6d0 <__wcsmbs_named_conv> - 4137c0: 85 c0 test %eax,%eax - 4137c2: 0f 85 b8 03 00 00 jne 413b80 <_IO_new_file_fopen+0x720> - 4137c8: 4c 89 e7 mov %r12,%rdi - 4137cb: e8 e0 a5 00 00 callq 41ddb0 <__cfree> - 4137d0: 48 83 7c 24 08 01 cmpq $0x1,0x8(%rsp) - 4137d6: 0f 85 2b 04 00 00 jne 413c07 <_IO_new_file_fopen+0x7a7> - 4137dc: 48 83 7c 24 18 01 cmpq $0x1,0x18(%rsp) - 4137e2: 0f 85 06 04 00 00 jne 413bee <_IO_new_file_fopen+0x78e> - 4137e8: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 4137ef: be e0 45 4b 00 mov $0x4b45e0,%esi - 4137f4: b9 18 00 00 00 mov $0x18,%ecx - 4137f9: 48 8b 50 08 mov 0x8(%rax),%rdx - 4137fd: 48 c7 40 58 00 00 00 movq $0x0,0x58(%rax) - 413804: 00 - 413805: 48 89 10 mov %rdx,(%rax) - 413808: 48 8b 50 18 mov 0x18(%rax),%rdx - 41380c: 48 89 50 20 mov %rdx,0x20(%rax) - 413810: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 413817: 48 c7 40 60 00 00 00 movq $0x0,0x60(%rax) - 41381e: 00 - 41381f: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 413826: 48 8d 50 68 lea 0x68(%rax),%rdx - 41382a: 48 89 93 98 00 00 00 mov %rdx,0x98(%rbx) - 413831: 48 89 d7 mov %rdx,%rdi - 413834: 48 8b 14 24 mov (%rsp),%rdx - 413838: f3 48 a5 rep movsq %ds:(%rsi),%es:(%rdi) - 41383b: 48 c7 80 a8 00 00 00 movq $0x1,0xa8(%rax) - 413842: 01 00 00 00 - 413846: c7 80 cc 00 00 00 00 movl $0x0,0xcc(%rax) - 41384d: 00 00 00 - 413850: 48 89 90 b0 00 00 00 mov %rdx,0xb0(%rax) - 413857: c7 80 d0 00 00 00 01 movl $0x1,0xd0(%rax) - 41385e: 00 00 00 - 413861: c7 80 c8 00 00 00 01 movl $0x1,0xc8(%rax) - 413868: 00 00 00 - 41386b: 48 8b 8d a0 00 00 00 mov 0xa0(%rbp),%rcx - 413872: 48 c7 80 e8 00 00 00 movq $0x1,0xe8(%rax) - 413879: 01 00 00 00 - 41387d: c7 80 0c 01 00 00 00 movl $0x0,0x10c(%rax) - 413884: 00 00 00 - 413887: c7 80 10 01 00 00 01 movl $0x1,0x110(%rax) - 41388e: 00 00 00 - 413891: c7 80 08 01 00 00 09 movl $0x9,0x108(%rax) - 413898: 00 00 00 - 41389b: 48 8d 51 58 lea 0x58(%rcx),%rdx - 41389f: 48 89 90 d8 00 00 00 mov %rdx,0xd8(%rax) - 4138a6: 48 8b 54 24 10 mov 0x10(%rsp),%rdx - 4138ab: 48 89 90 f0 00 00 00 mov %rdx,0xf0(%rax) - 4138b2: 48 8b 8d a0 00 00 00 mov 0xa0(%rbp),%rcx - 4138b9: 48 8d 51 58 lea 0x58(%rcx),%rdx - 4138bd: 48 89 90 18 01 00 00 mov %rdx,0x118(%rax) - 4138c4: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 4138cb: 48 8b 80 30 01 00 00 mov 0x130(%rax),%rax - 4138d2: 48 89 83 d8 00 00 00 mov %rax,0xd8(%rbx) - 4138d9: c7 85 c0 00 00 00 01 movl $0x1,0xc0(%rbp) - 4138e0: 00 00 00 - 4138e3: 48 83 c4 28 add $0x28,%rsp - 4138e7: 5b pop %rbx - 4138e8: 48 89 e8 mov %rbp,%rax - 4138eb: 5d pop %rbp - 4138ec: 41 5c pop %r12 - 4138ee: 41 5d pop %r13 - 4138f0: 41 5e pop %r14 - 4138f2: 41 5f pop %r15 - 4138f4: c3 retq - 4138f5: 0f 1f 00 nopl (%rax) - 4138f8: 41 80 f9 6d cmp $0x6d,%r9b - 4138fc: 0f 84 c9 01 00 00 je 413acb <_IO_new_file_fopen+0x66b> - 413902: 41 80 f9 78 cmp $0x78,%r9b - 413906: 0f 84 aa 01 00 00 je 413ab6 <_IO_new_file_fopen+0x656> - 41390c: 41 80 f9 65 cmp $0x65,%r9b - 413910: 0f 85 10 fc ff ff jne 413526 <_IO_new_file_fopen+0xc6> - 413916: 41 81 ca 00 00 08 00 or $0x80000,%r10d - 41391d: 83 4f 74 40 orl $0x40,0x74(%rdi) - 413921: 49 89 d4 mov %rdx,%r12 - 413924: e9 07 fc ff ff jmpq 413530 <_IO_new_file_fopen+0xd0> - 413929: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 413930: 41 83 c7 01 add $0x1,%r15d - 413934: 41 83 ff 03 cmp $0x3,%r15d - 413938: 0f 84 4a fe ff ff je 413788 <_IO_new_file_fopen+0x328> - 41393e: c6 00 2f movb $0x2f,(%rax) - 413941: 48 83 c0 01 add $0x1,%rax - 413945: e9 c0 fd ff ff jmpq 41370a <_IO_new_file_fopen+0x2aa> - 41394a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 413950: 41 80 f9 6d cmp $0x6d,%r9b - 413954: 0f 84 8e 01 00 00 je 413ae8 <_IO_new_file_fopen+0x688> - 41395a: 41 80 f9 78 cmp $0x78,%r9b - 41395e: 0f 84 07 01 00 00 je 413a6b <_IO_new_file_fopen+0x60b> - 413964: 41 80 f9 65 cmp $0x65,%r9b - 413968: 0f 85 02 fc ff ff jne 413570 <_IO_new_file_fopen+0x110> - 41396e: 41 81 ca 00 00 08 00 or $0x80000,%r10d - 413975: 83 4f 74 40 orl $0x40,0x74(%rdi) - 413979: e9 f2 fb ff ff jmpq 413570 <_IO_new_file_fopen+0x110> - 41397e: 66 90 xchg %ax,%ax - 413980: 41 80 f9 6d cmp $0x6d,%r9b - 413984: 0f 84 a1 01 00 00 je 413b2b <_IO_new_file_fopen+0x6cb> - 41398a: 41 80 f9 78 cmp $0x78,%r9b - 41398e: 0f 84 fe 00 00 00 je 413a92 <_IO_new_file_fopen+0x632> - 413994: 41 80 f9 65 cmp $0x65,%r9b - 413998: 0f 85 12 fc ff ff jne 4135b0 <_IO_new_file_fopen+0x150> - 41399e: 41 81 ca 00 00 08 00 or $0x80000,%r10d - 4139a5: 83 4f 74 40 orl $0x40,0x74(%rdi) - 4139a9: e9 02 fc ff ff jmpq 4135b0 <_IO_new_file_fopen+0x150> - 4139ae: 66 90 xchg %ax,%ax - 4139b0: 41 b8 04 10 00 00 mov $0x1004,%r8d - 4139b6: b8 01 00 00 00 mov $0x1,%eax - 4139bb: 41 ba 40 04 00 00 mov $0x440,%r10d - 4139c1: e9 2b fb ff ff jmpq 4134f1 <_IO_new_file_fopen+0x91> - 4139c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4139cd: 00 00 00 - 4139d0: 41 b8 08 00 00 00 mov $0x8,%r8d - 4139d6: 31 c0 xor %eax,%eax - 4139d8: 45 31 d2 xor %r10d,%r10d - 4139db: e9 11 fb ff ff jmpq 4134f1 <_IO_new_file_fopen+0x91> - 4139e0: 41 80 f9 6d cmp $0x6d,%r9b - 4139e4: 0f 84 67 01 00 00 je 413b51 <_IO_new_file_fopen+0x6f1> - 4139ea: 41 80 f9 78 cmp $0x78,%r9b - 4139ee: 0f 84 aa 00 00 00 je 413a9e <_IO_new_file_fopen+0x63e> - 4139f4: 41 80 f9 65 cmp $0x65,%r9b - 4139f8: 0f 85 ea fb ff ff jne 4135e8 <_IO_new_file_fopen+0x188> - 4139fe: 41 81 ca 00 00 08 00 or $0x80000,%r10d - 413a05: 83 4f 74 40 orl $0x40,0x74(%rdi) - 413a09: e9 da fb ff ff jmpq 4135e8 <_IO_new_file_fopen+0x188> - 413a0e: 66 90 xchg %ax,%ax - 413a10: 41 80 f9 6d cmp $0x6d,%r9b - 413a14: 0f 84 40 01 00 00 je 413b5a <_IO_new_file_fopen+0x6fa> - 413a1a: 41 80 f9 78 cmp $0x78,%r9b - 413a1e: 0f 84 86 00 00 00 je 413aaa <_IO_new_file_fopen+0x64a> - 413a24: 41 80 f9 65 cmp $0x65,%r9b - 413a28: 0f 85 f2 fb ff ff jne 413620 <_IO_new_file_fopen+0x1c0> - 413a2e: 41 81 ca 00 00 08 00 or $0x80000,%r10d - 413a35: 83 4f 74 40 orl $0x40,0x74(%rdi) - 413a39: e9 e2 fb ff ff jmpq 413620 <_IO_new_file_fopen+0x1c0> - 413a3e: 66 90 xchg %ax,%ax - 413a40: 80 fa 6d cmp $0x6d,%dl - 413a43: 0f 84 79 01 00 00 je 413bc2 <_IO_new_file_fopen+0x762> - 413a49: 80 fa 78 cmp $0x78,%dl - 413a4c: 0f 84 79 01 00 00 je 413bcb <_IO_new_file_fopen+0x76b> - 413a52: 80 fa 65 cmp $0x65,%dl - 413a55: 0f 85 f5 fb ff ff jne 413650 <_IO_new_file_fopen+0x1f0> - 413a5b: 41 81 ca 00 00 08 00 or $0x80000,%r10d - 413a62: 83 4f 74 40 orl $0x40,0x74(%rdi) - 413a66: e9 e5 fb ff ff jmpq 413650 <_IO_new_file_fopen+0x1f0> - 413a6b: 41 80 ca 80 or $0x80,%r10b - 413a6f: 4d 89 dc mov %r11,%r12 - 413a72: e9 f9 fa ff ff jmpq 413570 <_IO_new_file_fopen+0x110> - 413a77: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 413a7e: 00 00 - 413a80: 48 83 c4 28 add $0x28,%rsp - 413a84: 48 89 e8 mov %rbp,%rax - 413a87: 5b pop %rbx - 413a88: 5d pop %rbp - 413a89: 41 5c pop %r12 - 413a8b: 41 5d pop %r13 - 413a8d: 41 5e pop %r14 - 413a8f: 41 5f pop %r15 - 413a91: c3 retq - 413a92: 41 80 ca 80 or $0x80,%r10b - 413a96: 4d 89 dc mov %r11,%r12 - 413a99: e9 12 fb ff ff jmpq 4135b0 <_IO_new_file_fopen+0x150> - 413a9e: 41 80 ca 80 or $0x80,%r10b - 413aa2: 4d 89 dc mov %r11,%r12 - 413aa5: e9 3e fb ff ff jmpq 4135e8 <_IO_new_file_fopen+0x188> - 413aaa: 41 80 ca 80 or $0x80,%r10b - 413aae: 4d 89 dc mov %r11,%r12 - 413ab1: e9 6a fb ff ff jmpq 413620 <_IO_new_file_fopen+0x1c0> - 413ab6: 41 80 ca 80 or $0x80,%r10b - 413aba: e9 71 fa ff ff jmpq 413530 <_IO_new_file_fopen+0xd0> - 413abf: 83 4f 74 02 orl $0x2,0x74(%rdi) - 413ac3: 49 89 d4 mov %rdx,%r12 - 413ac6: e9 65 fa ff ff jmpq 413530 <_IO_new_file_fopen+0xd0> - 413acb: 83 4f 74 01 orl $0x1,0x74(%rdi) - 413acf: 49 89 d4 mov %rdx,%r12 - 413ad2: e9 59 fa ff ff jmpq 413530 <_IO_new_file_fopen+0xd0> - 413ad7: 41 81 e0 00 10 00 00 and $0x1000,%r8d - 413ade: b8 02 00 00 00 mov $0x2,%eax - 413ae3: e9 48 fa ff ff jmpq 413530 <_IO_new_file_fopen+0xd0> - 413ae8: 83 4f 74 01 orl $0x1,0x74(%rdi) - 413aec: e9 7f fa ff ff jmpq 413570 <_IO_new_file_fopen+0x110> - 413af1: 83 4f 74 02 orl $0x2,0x74(%rdi) - 413af5: e9 76 fa ff ff jmpq 413570 <_IO_new_file_fopen+0x110> - 413afa: 41 81 e0 00 10 00 00 and $0x1000,%r8d - 413b01: 4d 89 dc mov %r11,%r12 - 413b04: b8 02 00 00 00 mov $0x2,%eax - 413b09: e9 62 fa ff ff jmpq 413570 <_IO_new_file_fopen+0x110> - 413b0e: 41 81 e0 00 10 00 00 and $0x1000,%r8d - 413b15: 4d 89 dc mov %r11,%r12 - 413b18: b8 02 00 00 00 mov $0x2,%eax - 413b1d: e9 8e fa ff ff jmpq 4135b0 <_IO_new_file_fopen+0x150> - 413b22: 83 4f 74 02 orl $0x2,0x74(%rdi) - 413b26: e9 85 fa ff ff jmpq 4135b0 <_IO_new_file_fopen+0x150> - 413b2b: 83 4f 74 01 orl $0x1,0x74(%rdi) - 413b2f: e9 7c fa ff ff jmpq 4135b0 <_IO_new_file_fopen+0x150> - 413b34: 41 81 e0 00 10 00 00 and $0x1000,%r8d - 413b3b: 4d 89 dc mov %r11,%r12 - 413b3e: b8 02 00 00 00 mov $0x2,%eax - 413b43: e9 a0 fa ff ff jmpq 4135e8 <_IO_new_file_fopen+0x188> - 413b48: 83 4f 74 02 orl $0x2,0x74(%rdi) - 413b4c: e9 97 fa ff ff jmpq 4135e8 <_IO_new_file_fopen+0x188> - 413b51: 83 4f 74 01 orl $0x1,0x74(%rdi) - 413b55: e9 8e fa ff ff jmpq 4135e8 <_IO_new_file_fopen+0x188> - 413b5a: 83 4f 74 01 orl $0x1,0x74(%rdi) - 413b5e: e9 bd fa ff ff jmpq 413620 <_IO_new_file_fopen+0x1c0> - 413b63: 41 81 e0 00 10 00 00 and $0x1000,%r8d - 413b6a: 4d 89 dc mov %r11,%r12 - 413b6d: b8 02 00 00 00 mov $0x2,%eax - 413b72: e9 a9 fa ff ff jmpq 413620 <_IO_new_file_fopen+0x1c0> - 413b77: 83 4f 74 02 orl $0x2,0x74(%rdi) - 413b7b: e9 a0 fa ff ff jmpq 413620 <_IO_new_file_fopen+0x1c0> - 413b80: 48 89 df mov %rbx,%rdi - 413b83: e8 58 f7 ff ff callq 4132e0 <_IO_new_file_close_it> - 413b88: 4c 89 e7 mov %r12,%rdi - 413b8b: e8 20 a2 00 00 callq 41ddb0 <__cfree> - 413b90: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 413b97: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) - 413b9e: 31 c0 xor %eax,%eax - 413ba0: e9 25 f9 ff ff jmpq 4134ca <_IO_new_file_fopen+0x6a> - 413ba5: 41 81 e0 00 10 00 00 and $0x1000,%r8d - 413bac: 4d 89 cc mov %r9,%r12 - 413baf: b8 02 00 00 00 mov $0x2,%eax - 413bb4: e9 97 fa ff ff jmpq 413650 <_IO_new_file_fopen+0x1f0> - 413bb9: 83 4f 74 02 orl $0x2,0x74(%rdi) - 413bbd: e9 8e fa ff ff jmpq 413650 <_IO_new_file_fopen+0x1f0> - 413bc2: 83 4f 74 01 orl $0x1,0x74(%rdi) - 413bc6: e9 85 fa ff ff jmpq 413650 <_IO_new_file_fopen+0x1f0> - 413bcb: 41 80 ca 80 or $0x80,%r10b - 413bcf: 4d 89 cc mov %r9,%r12 - 413bd2: e9 79 fa ff ff jmpq 413650 <_IO_new_file_fopen+0x1f0> - 413bd7: 48 89 d0 mov %rdx,%rax - 413bda: e9 a9 fb ff ff jmpq 413788 <_IO_new_file_fopen+0x328> - 413bdf: 49 8d 54 24 01 lea 0x1(%r12),%rdx - 413be4: 41 c6 04 24 2f movb $0x2f,(%r12) - 413be9: e9 93 fb ff ff jmpq 413781 <_IO_new_file_fopen+0x321> - 413bee: b9 70 1c 4a 00 mov $0x4a1c70,%ecx - 413bf3: ba 80 01 00 00 mov $0x180,%edx - 413bf8: be 54 19 4a 00 mov $0x4a1954,%esi - 413bfd: bf 4c 1c 4a 00 mov $0x4a1c4c,%edi - 413c02: e8 39 db fe ff callq 401740 <__assert_fail> - 413c07: b9 70 1c 4a 00 mov $0x4a1c70,%ecx - 413c0c: ba 7f 01 00 00 mov $0x17f,%edx - 413c11: be 54 19 4a 00 mov $0x4a1954,%esi - 413c16: bf 36 1c 4a 00 mov $0x4a1c36,%edi - 413c1b: e8 20 db fe ff callq 401740 <__assert_fail> - -0000000000413c20 <_IO_new_file_finish>: - 413c20: 53 push %rbx - 413c21: 83 7f 70 ff cmpl $0xffffffff,0x70(%rdi) - 413c25: 48 89 fb mov %rdi,%rbx - 413c28: 74 2a je 413c54 <_IO_new_file_finish+0x34> - 413c2a: 8b 87 c0 00 00 00 mov 0xc0(%rdi),%eax - 413c30: 85 c0 test %eax,%eax - 413c32: 7e 4c jle 413c80 <_IO_new_file_finish+0x60> - 413c34: 48 8b 87 a0 00 00 00 mov 0xa0(%rdi),%rax - 413c3b: 48 8b 70 18 mov 0x18(%rax),%rsi - 413c3f: 48 8b 50 20 mov 0x20(%rax),%rdx - 413c43: 48 29 f2 sub %rsi,%rdx - 413c46: 48 c1 fa 02 sar $0x2,%rdx - 413c4a: e8 e1 cd ff ff callq 410a30 <_IO_wdo_write> - 413c4f: f6 03 40 testb $0x40,(%rbx) - 413c52: 74 0c je 413c60 <_IO_new_file_finish+0x40> - 413c54: 48 89 df mov %rbx,%rdi - 413c57: 31 f6 xor %esi,%esi - 413c59: 5b pop %rbx - 413c5a: e9 b1 19 00 00 jmpq 415610 <_IO_default_finish> - 413c5f: 90 nop - 413c60: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 413c67: 48 89 df mov %rbx,%rdi - 413c6a: ff 90 88 00 00 00 callq *0x88(%rax) - 413c70: 48 89 df mov %rbx,%rdi - 413c73: 31 f6 xor %esi,%esi - 413c75: 5b pop %rbx - 413c76: e9 95 19 00 00 jmpq 415610 <_IO_default_finish> - 413c7b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 413c80: 48 8b 77 20 mov 0x20(%rdi),%rsi - 413c84: 48 8b 57 28 mov 0x28(%rdi),%rdx - 413c88: 48 29 f2 sub %rsi,%rdx - 413c8b: e8 40 f5 ff ff callq 4131d0 <_IO_new_do_write> - 413c90: eb bd jmp 413c4f <_IO_new_file_finish+0x2f> - 413c92: 0f 1f 40 00 nopl 0x0(%rax) - 413c96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 413c9d: 00 00 00 - -0000000000413ca0 <_IO_new_file_overflow>: - 413ca0: 8b 0f mov (%rdi),%ecx - 413ca2: f6 c1 08 test $0x8,%cl - 413ca5: 0f 85 95 01 00 00 jne 413e40 <_IO_new_file_overflow+0x1a0> - 413cab: f6 c5 08 test $0x8,%ch - 413cae: 41 54 push %r12 - 413cb0: 55 push %rbp - 413cb1: 89 f5 mov %esi,%ebp - 413cb3: 53 push %rbx - 413cb4: 48 89 fb mov %rdi,%rbx - 413cb7: 74 4f je 413d08 <_IO_new_file_overflow+0x68> - 413cb9: 48 8b 77 20 mov 0x20(%rdi),%rsi - 413cbd: 48 85 f6 test %rsi,%rsi - 413cc0: 0f 84 9a 01 00 00 je 413e60 <_IO_new_file_overflow+0x1c0> - 413cc6: 48 8b 57 28 mov 0x28(%rdi),%rdx - 413cca: 83 fd ff cmp $0xffffffff,%ebp - 413ccd: 0f 84 4d 01 00 00 je 413e20 <_IO_new_file_overflow+0x180> - 413cd3: 48 39 53 40 cmp %rdx,0x40(%rbx) - 413cd7: 0f 84 fb 00 00 00 je 413dd8 <_IO_new_file_overflow+0x138> - 413cdd: 48 8d 42 01 lea 0x1(%rdx),%rax - 413ce1: 48 89 43 28 mov %rax,0x28(%rbx) - 413ce5: 40 88 2a mov %bpl,(%rdx) - 413ce8: 8b 03 mov (%rbx),%eax - 413cea: a8 02 test $0x2,%al - 413cec: 0f 85 86 00 00 00 jne 413d78 <_IO_new_file_overflow+0xd8> - 413cf2: f6 c4 02 test $0x2,%ah - 413cf5: 74 05 je 413cfc <_IO_new_file_overflow+0x5c> - 413cf7: 83 fd 0a cmp $0xa,%ebp - 413cfa: 74 7c je 413d78 <_IO_new_file_overflow+0xd8> - 413cfc: 40 0f b6 c5 movzbl %bpl,%eax - 413d00: 5b pop %rbx - 413d01: 5d pop %rbp - 413d02: 41 5c pop %r12 - 413d04: c3 retq - 413d05: 0f 1f 00 nopl (%rax) - 413d08: 48 83 7f 20 00 cmpq $0x0,0x20(%rdi) - 413d0d: 0f 84 4d 01 00 00 je 413e60 <_IO_new_file_overflow+0x1c0> - 413d13: 48 8b 57 08 mov 0x8(%rdi),%rdx - 413d17: f6 c5 01 test $0x1,%ch - 413d1a: 0f 85 80 00 00 00 jne 413da0 <_IO_new_file_overflow+0x100> - 413d20: 48 8b 43 40 mov 0x40(%rbx),%rax - 413d24: 48 39 d0 cmp %rdx,%rax - 413d27: 0f 84 03 01 00 00 je 413e30 <_IO_new_file_overflow+0x190> - 413d2d: 48 8b 73 10 mov 0x10(%rbx),%rsi - 413d31: 8b bb c0 00 00 00 mov 0xc0(%rbx),%edi - 413d37: 48 89 43 30 mov %rax,0x30(%rbx) - 413d3b: 89 c8 mov %ecx,%eax - 413d3d: 80 cc 08 or $0x8,%ah - 413d40: 48 89 73 08 mov %rsi,0x8(%rbx) - 413d44: 48 89 73 18 mov %rsi,0x18(%rbx) - 413d48: 48 89 53 28 mov %rdx,0x28(%rbx) - 413d4c: 48 89 53 20 mov %rdx,0x20(%rbx) - 413d50: 48 89 d6 mov %rdx,%rsi - 413d53: 85 ff test %edi,%edi - 413d55: 89 03 mov %eax,(%rbx) - 413d57: 0f 8f 6d ff ff ff jg 413cca <_IO_new_file_overflow+0x2a> - 413d5d: 81 e1 02 02 00 00 and $0x202,%ecx - 413d63: 0f 84 61 ff ff ff je 413cca <_IO_new_file_overflow+0x2a> - 413d69: 48 89 53 30 mov %rdx,0x30(%rbx) - 413d6d: e9 58 ff ff ff jmpq 413cca <_IO_new_file_overflow+0x2a> - 413d72: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 413d78: 48 8b 73 20 mov 0x20(%rbx),%rsi - 413d7c: 48 8b 53 28 mov 0x28(%rbx),%rdx - 413d80: 48 89 df mov %rbx,%rdi - 413d83: 48 29 f2 sub %rsi,%rdx - 413d86: e8 45 f4 ff ff callq 4131d0 <_IO_new_do_write> - 413d8b: 83 f8 ff cmp $0xffffffff,%eax - 413d8e: 0f 85 68 ff ff ff jne 413cfc <_IO_new_file_overflow+0x5c> - 413d94: b8 ff ff ff ff mov $0xffffffff,%eax - 413d99: e9 62 ff ff ff jmpq 413d00 <_IO_new_file_overflow+0x60> - 413d9e: 66 90 xchg %ax,%ax - 413da0: 4c 8b 63 10 mov 0x10(%rbx),%r12 - 413da4: 48 89 df mov %rbx,%rdi - 413da7: 49 29 d4 sub %rdx,%r12 - 413daa: e8 81 0c 00 00 callq 414a30 <_IO_free_backup_area> - 413daf: 48 8b 53 18 mov 0x18(%rbx),%rdx - 413db3: 8b 0b mov (%rbx),%ecx - 413db5: 48 89 d0 mov %rdx,%rax - 413db8: 48 2b 43 38 sub 0x38(%rbx),%rax - 413dbc: 4c 39 e0 cmp %r12,%rax - 413dbf: 49 0f 47 c4 cmova %r12,%rax - 413dc3: 48 29 c2 sub %rax,%rdx - 413dc6: 48 89 53 18 mov %rdx,0x18(%rbx) - 413dca: 48 89 53 08 mov %rdx,0x8(%rbx) - 413dce: e9 4d ff ff ff jmpq 413d20 <_IO_new_file_overflow+0x80> - 413dd3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 413dd8: 8b 83 c0 00 00 00 mov 0xc0(%rbx),%eax - 413dde: 85 c0 test %eax,%eax - 413de0: 0f 8e 9a 00 00 00 jle 413e80 <_IO_new_file_overflow+0x1e0> - 413de6: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 413ded: 48 89 df mov %rbx,%rdi - 413df0: 48 8b 70 18 mov 0x18(%rax),%rsi - 413df4: 48 8b 50 20 mov 0x20(%rax),%rdx - 413df8: 48 29 f2 sub %rsi,%rdx - 413dfb: 48 c1 fa 02 sar $0x2,%rdx - 413dff: e8 2c cc ff ff callq 410a30 <_IO_wdo_write> - 413e04: 83 f8 ff cmp $0xffffffff,%eax - 413e07: 0f 94 c0 sete %al - 413e0a: 84 c0 test %al,%al - 413e0c: 0f 85 82 ff ff ff jne 413d94 <_IO_new_file_overflow+0xf4> - 413e12: 48 8b 53 28 mov 0x28(%rbx),%rdx - 413e16: e9 c2 fe ff ff jmpq 413cdd <_IO_new_file_overflow+0x3d> - 413e1b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 413e20: 48 89 df mov %rbx,%rdi - 413e23: 48 29 f2 sub %rsi,%rdx - 413e26: 5b pop %rbx - 413e27: 5d pop %rbp - 413e28: 41 5c pop %r12 - 413e2a: e9 a1 f3 ff ff jmpq 4131d0 <_IO_new_do_write> - 413e2f: 90 nop - 413e30: 48 8b 53 38 mov 0x38(%rbx),%rdx - 413e34: 48 89 53 10 mov %rdx,0x10(%rbx) - 413e38: 48 89 d6 mov %rdx,%rsi - 413e3b: e9 f1 fe ff ff jmpq 413d31 <_IO_new_file_overflow+0x91> - 413e40: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 413e47: 83 c9 20 or $0x20,%ecx - 413e4a: 89 0f mov %ecx,(%rdi) - 413e4c: 64 c7 00 09 00 00 00 movl $0x9,%fs:(%rax) - 413e53: b8 ff ff ff ff mov $0xffffffff,%eax - 413e58: c3 retq - 413e59: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 413e60: 48 89 df mov %rbx,%rdi - 413e63: e8 98 0f 00 00 callq 414e00 <_IO_doallocbuf> - 413e68: 48 8b 53 38 mov 0x38(%rbx),%rdx - 413e6c: 8b 0b mov (%rbx),%ecx - 413e6e: 48 89 53 18 mov %rdx,0x18(%rbx) - 413e72: 48 89 53 08 mov %rdx,0x8(%rbx) - 413e76: 48 89 53 10 mov %rdx,0x10(%rbx) - 413e7a: e9 98 fe ff ff jmpq 413d17 <_IO_new_file_overflow+0x77> - 413e7f: 90 nop - 413e80: 48 29 f2 sub %rsi,%rdx - 413e83: 48 89 df mov %rbx,%rdi - 413e86: e8 45 f3 ff ff callq 4131d0 <_IO_new_do_write> - 413e8b: 83 f8 ff cmp $0xffffffff,%eax - 413e8e: 0f 94 c0 sete %al - 413e91: e9 74 ff ff ff jmpq 413e0a <_IO_new_file_overflow+0x16a> - 413e96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 413e9d: 00 00 00 - -0000000000413ea0 <_IO_new_file_sync>: - 413ea0: 53 push %rbx - 413ea1: 48 8b 57 28 mov 0x28(%rdi),%rdx - 413ea5: 48 89 fb mov %rdi,%rbx - 413ea8: 48 8b 77 20 mov 0x20(%rdi),%rsi - 413eac: 48 39 f2 cmp %rsi,%rdx - 413eaf: 76 2e jbe 413edf <_IO_new_file_sync+0x3f> - 413eb1: 8b 87 c0 00 00 00 mov 0xc0(%rdi),%eax - 413eb7: 85 c0 test %eax,%eax - 413eb9: 7e 6d jle 413f28 <_IO_new_file_sync+0x88> - 413ebb: 48 8b 87 a0 00 00 00 mov 0xa0(%rdi),%rax - 413ec2: 48 8b 70 18 mov 0x18(%rax),%rsi - 413ec6: 48 8b 50 20 mov 0x20(%rax),%rdx - 413eca: 48 29 f2 sub %rsi,%rdx - 413ecd: 48 c1 fa 02 sar $0x2,%rdx - 413ed1: e8 5a cb ff ff callq 410a30 <_IO_wdo_write> - 413ed6: 85 c0 test %eax,%eax - 413ed8: 0f 95 c0 setne %al - 413edb: 84 c0 test %al,%al - 413edd: 75 6e jne 413f4d <_IO_new_file_sync+0xad> - 413edf: 48 8b 73 08 mov 0x8(%rbx),%rsi - 413ee3: 48 2b 73 10 sub 0x10(%rbx),%rsi - 413ee7: 75 17 jne 413f00 <_IO_new_file_sync+0x60> - 413ee9: 48 c7 83 90 00 00 00 movq $0xffffffffffffffff,0x90(%rbx) - 413ef0: ff ff ff ff - 413ef4: 31 c0 xor %eax,%eax - 413ef6: 5b pop %rbx - 413ef7: c3 retq - 413ef8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 413eff: 00 - 413f00: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 413f07: ba 01 00 00 00 mov $0x1,%edx - 413f0c: 48 89 df mov %rbx,%rdi - 413f0f: ff 90 80 00 00 00 callq *0x80(%rax) - 413f15: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 413f19: 74 25 je 413f40 <_IO_new_file_sync+0xa0> - 413f1b: 48 8b 43 08 mov 0x8(%rbx),%rax - 413f1f: 48 89 43 10 mov %rax,0x10(%rbx) - 413f23: eb c4 jmp 413ee9 <_IO_new_file_sync+0x49> - 413f25: 0f 1f 00 nopl (%rax) - 413f28: 48 29 f2 sub %rsi,%rdx - 413f2b: e8 a0 f2 ff ff callq 4131d0 <_IO_new_do_write> - 413f30: 85 c0 test %eax,%eax - 413f32: 0f 95 c0 setne %al - 413f35: eb a4 jmp 413edb <_IO_new_file_sync+0x3b> - 413f37: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 413f3e: 00 00 - 413f40: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 413f47: 64 83 38 1d cmpl $0x1d,%fs:(%rax) - 413f4b: 74 9c je 413ee9 <_IO_new_file_sync+0x49> - 413f4d: b8 ff ff ff ff mov $0xffffffff,%eax - 413f52: 5b pop %rbx - 413f53: c3 retq - 413f54: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 413f5b: 00 00 00 - 413f5e: 66 90 xchg %ax,%ax - -0000000000413f60 : - 413f60: 41 57 push %r15 - 413f62: 41 56 push %r14 - 413f64: 41 55 push %r13 - 413f66: 41 54 push %r12 - 413f68: 49 89 f4 mov %rsi,%r12 - 413f6b: 55 push %rbp - 413f6c: 53 push %rbx - 413f6d: 49 89 fd mov %rdi,%r13 - 413f70: 48 89 f5 mov %rsi,%rbp - 413f73: 48 83 ec 28 sub $0x28,%rsp - 413f77: 4c 8b 47 18 mov 0x18(%rdi),%r8 - 413f7b: 48 8b 47 60 mov 0x60(%rdi),%rax - 413f7f: 4d 29 c4 sub %r8,%r12 - 413f82: 48 85 c0 test %rax,%rax - 413f85: 0f 84 36 01 00 00 je 4140c1 - 413f8b: 4c 89 e3 mov %r12,%rbx - 413f8e: 48 89 c1 mov %rax,%rcx - 413f91: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 413f98: 48 63 79 10 movslq 0x10(%rcx),%rdi - 413f9c: 48 8b 09 mov (%rcx),%rcx - 413f9f: 48 39 fb cmp %rdi,%rbx - 413fa2: 48 0f 4f df cmovg %rdi,%rbx - 413fa6: 48 85 c9 test %rcx,%rcx - 413fa9: 75 ed jne 413f98 - 413fab: 49 8b 75 58 mov 0x58(%r13),%rsi - 413faf: 4d 8b 7d 48 mov 0x48(%r13),%r15 - 413fb3: 4c 89 e2 mov %r12,%rdx - 413fb6: 48 29 da sub %rbx,%rdx - 413fb9: 49 89 f6 mov %rsi,%r14 - 413fbc: 4d 29 fe sub %r15,%r14 - 413fbf: 4c 39 f2 cmp %r14,%rdx - 413fc2: 77 4c ja 414010 - 413fc4: 49 29 d6 sub %rdx,%r14 - 413fc7: 48 85 db test %rbx,%rbx - 413fca: 0f 88 0b 01 00 00 js 4140db - 413fd0: 48 85 d2 test %rdx,%rdx - 413fd3: 0f 85 c7 00 00 00 jne 4140a0 - 413fd9: 4d 01 fe add %r15,%r14 - 413fdc: 4c 89 e6 mov %r12,%rsi - 413fdf: 48 85 c0 test %rax,%rax - 413fe2: 4d 89 75 50 mov %r14,0x50(%r13) - 413fe6: 74 13 je 413ffb - 413fe8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 413fef: 00 - 413ff0: 29 70 10 sub %esi,0x10(%rax) - 413ff3: 48 8b 00 mov (%rax),%rax - 413ff6: 48 85 c0 test %rax,%rax - 413ff9: 75 f5 jne 413ff0 - 413ffb: 31 c0 xor %eax,%eax - 413ffd: 48 83 c4 28 add $0x28,%rsp - 414001: 5b pop %rbx - 414002: 5d pop %rbp - 414003: 41 5c pop %r12 - 414005: 41 5d pop %r13 - 414007: 41 5e pop %r14 - 414009: 41 5f pop %r15 - 41400b: c3 retq - 41400c: 0f 1f 40 00 nopl 0x0(%rax) - 414010: 48 8d 42 64 lea 0x64(%rdx),%rax - 414014: 4c 89 44 24 18 mov %r8,0x18(%rsp) - 414019: 48 89 74 24 10 mov %rsi,0x10(%rsp) - 41401e: 48 89 54 24 08 mov %rdx,0x8(%rsp) - 414023: 48 89 c7 mov %rax,%rdi - 414026: 48 89 04 24 mov %rax,(%rsp) - 41402a: e8 e1 99 00 00 callq 41da10 <__libc_malloc> - 41402f: 48 85 c0 test %rax,%rax - 414032: 0f 84 0b 01 00 00 je 414143 - 414038: 48 85 db test %rbx,%rbx - 41403b: 48 8b 54 24 08 mov 0x8(%rsp),%rdx - 414040: 48 8b 74 24 10 mov 0x10(%rsp),%rsi - 414045: 4c 8b 44 24 18 mov 0x18(%rsp),%r8 - 41404a: 0f 88 b3 00 00 00 js 414103 - 414050: 4c 8d 70 64 lea 0x64(%rax),%r14 - 414054: 49 8d 34 18 lea (%r8,%rbx,1),%rsi - 414058: 48 89 44 24 08 mov %rax,0x8(%rsp) - 41405d: 4c 89 f7 mov %r14,%rdi - 414060: e8 bb 7f 01 00 callq 42c020 - 414065: 4c 8b 4c 24 08 mov 0x8(%rsp),%r9 - 41406a: 4c 89 ff mov %r15,%rdi - 41406d: 4c 89 4c 24 08 mov %r9,0x8(%rsp) - 414072: e8 39 9d 00 00 callq 41ddb0 <__cfree> - 414077: 4c 8b 4c 24 08 mov 0x8(%rsp),%r9 - 41407c: 4c 8b 3c 24 mov (%rsp),%r15 - 414080: 48 89 ee mov %rbp,%rsi - 414083: 49 8b 45 60 mov 0x60(%r13),%rax - 414087: 49 2b 75 18 sub 0x18(%r13),%rsi - 41408b: 4d 01 cf add %r9,%r15 - 41408e: 4d 89 4d 48 mov %r9,0x48(%r13) - 414092: 4d 89 7d 58 mov %r15,0x58(%r13) - 414096: e9 44 ff ff ff jmpq 413fdf - 41409b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4140a0: 4b 8d 3c 37 lea (%r15,%r14,1),%rdi - 4140a4: 49 8d 34 18 lea (%r8,%rbx,1),%rsi - 4140a8: e8 73 7f 01 00 callq 42c020 - 4140ad: 48 89 ee mov %rbp,%rsi - 4140b0: 4d 03 75 48 add 0x48(%r13),%r14 - 4140b4: 49 2b 75 18 sub 0x18(%r13),%rsi - 4140b8: 49 8b 45 60 mov 0x60(%r13),%rax - 4140bc: e9 1e ff ff ff jmpq 413fdf - 4140c1: 48 8b 77 58 mov 0x58(%rdi),%rsi - 4140c5: 4c 8b 7f 48 mov 0x48(%rdi),%r15 - 4140c9: 49 89 f6 mov %rsi,%r14 - 4140cc: 4d 29 fe sub %r15,%r14 - 4140cf: 4d 85 e4 test %r12,%r12 - 4140d2: 0f 89 01 ff ff ff jns 413fd9 - 4140d8: 4c 89 e3 mov %r12,%rbx - 4140db: 4b 8d 3c 37 lea (%r15,%r14,1),%rdi - 4140df: 48 89 da mov %rbx,%rdx - 4140e2: 48 01 de add %rbx,%rsi - 4140e5: 48 f7 da neg %rdx - 4140e8: e8 13 c2 fe ff callq 400300 <__rela_iplt_end+0x38> - 4140ed: 49 8b 75 18 mov 0x18(%r13),%rsi - 4140f1: 4c 89 f7 mov %r14,%rdi - 4140f4: 48 89 ea mov %rbp,%rdx - 4140f7: 48 29 df sub %rbx,%rdi - 4140fa: 49 03 7d 48 add 0x48(%r13),%rdi - 4140fe: 48 29 f2 sub %rsi,%rdx - 414101: eb a5 jmp 4140a8 - 414103: 4c 8d 70 64 lea 0x64(%rax),%r14 - 414107: 48 89 da mov %rbx,%rdx - 41410a: 48 01 de add %rbx,%rsi - 41410d: 48 f7 da neg %rdx - 414110: 4c 89 44 24 10 mov %r8,0x10(%rsp) - 414115: 48 89 44 24 08 mov %rax,0x8(%rsp) - 41411a: 4c 89 f7 mov %r14,%rdi - 41411d: e8 9e 24 01 00 callq 4265c0 <__mempcpy> - 414122: 4c 8b 44 24 10 mov 0x10(%rsp),%r8 - 414127: 4c 89 e2 mov %r12,%rdx - 41412a: 48 89 c7 mov %rax,%rdi - 41412d: 4c 89 c6 mov %r8,%rsi - 414130: e8 8b 24 01 00 callq 4265c0 <__mempcpy> - 414135: 4d 8b 7d 48 mov 0x48(%r13),%r15 - 414139: 4c 8b 4c 24 08 mov 0x8(%rsp),%r9 - 41413e: e9 27 ff ff ff jmpq 41406a - 414143: b8 ff ff ff ff mov $0xffffffff,%eax - 414148: e9 b0 fe ff ff jmpq 413ffd - 41414d: 0f 1f 00 nopl (%rax) - -0000000000414150 : - 414150: 48 8b 05 39 84 2b 00 mov 0x2b8439(%rip),%rax # 6cc590 - 414157: 48 85 c0 test %rax,%rax - 41415a: 74 47 je 4141a3 - 41415c: f7 00 00 80 00 00 testl $0x8000,(%rax) - 414162: 75 3f jne 4141a3 - 414164: 48 8b 90 88 00 00 00 mov 0x88(%rax),%rdx - 41416b: 83 6a 04 01 subl $0x1,0x4(%rdx) - 41416f: 75 32 jne 4141a3 - 414171: 48 c7 42 08 00 00 00 movq $0x0,0x8(%rdx) - 414178: 00 - 414179: 83 3d 3c 90 2b 00 00 cmpl $0x0,0x2b903c(%rip) # 6cd1bc <__libc_multiple_threads> - 414180: 74 07 je 414189 - 414182: f0 ff 0a lock decl (%rdx) - 414185: 75 06 jne 41418d - 414187: eb 1a jmp 4141a3 - 414189: ff 0a decl (%rdx) - 41418b: 74 16 je 4141a3 - 41418d: 48 8d 3a lea (%rdx),%rdi - 414190: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 414197: e8 64 e4 02 00 callq 442600 <__lll_unlock_wake_private> - 41419c: 48 81 c4 80 00 00 00 add $0x80,%rsp - 4141a3: 83 2d fa 83 2b 00 01 subl $0x1,0x2b83fa(%rip) # 6cc5a4 - 4141aa: 75 41 jne 4141ed - 4141ac: 48 c7 05 f1 83 2b 00 movq $0x0,0x2b83f1(%rip) # 6cc5a8 - 4141b3: 00 00 00 00 - 4141b7: 83 3d fe 8f 2b 00 00 cmpl $0x0,0x2b8ffe(%rip) # 6cd1bc <__libc_multiple_threads> - 4141be: 74 0b je 4141cb - 4141c0: f0 ff 0d d9 83 2b 00 lock decl 0x2b83d9(%rip) # 6cc5a0 - 4141c7: 75 0a jne 4141d3 - 4141c9: eb 22 jmp 4141ed - 4141cb: ff 0d cf 83 2b 00 decl 0x2b83cf(%rip) # 6cc5a0 - 4141d1: 74 1a je 4141ed - 4141d3: 48 8d 3d c6 83 2b 00 lea 0x2b83c6(%rip),%rdi # 6cc5a0 - 4141da: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 4141e1: e8 1a e4 02 00 callq 442600 <__lll_unlock_wake_private> - 4141e6: 48 81 c4 80 00 00 00 add $0x80,%rsp - 4141ed: f3 c3 repz retq - 4141ef: 90 nop - -00000000004141f0 <_IO_cleanup>: - 4141f0: 41 55 push %r13 - 4141f2: 41 54 push %r12 - 4141f4: 45 31 e4 xor %r12d,%r12d - 4141f7: 55 push %rbp - 4141f8: 53 push %rbx - 4141f9: 48 83 ec 08 sub $0x8,%rsp - 4141fd: 48 8b 1d bc 5e 2b 00 mov 0x2b5ebc(%rip),%rbx # 6ca0c0 <_IO_list_all> - 414204: 8b 2d 8e 83 2b 00 mov 0x2b838e(%rip),%ebp # 6cc598 <_IO_list_all_stamp> - 41420a: 48 85 db test %rbx,%rbx - 41420d: 75 47 jne 414256 <_IO_cleanup+0x66> - 41420f: e9 bc 01 00 00 jmpq 4143d0 <_IO_cleanup+0x1e0> - 414214: 0f 1f 40 00 nopl 0x0(%rax) - 414218: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 41421f: be ff ff ff ff mov $0xffffffff,%esi - 414224: 48 89 df mov %rbx,%rdi - 414227: ff 50 18 callq *0x18(%rax) - 41422a: 83 f8 ff cmp $0xffffffff,%eax - 41422d: 8b 15 65 83 2b 00 mov 0x2b8365(%rip),%edx # 6cc598 <_IO_list_all_stamp> - 414233: 0f 84 8f 01 00 00 je 4143c8 <_IO_cleanup+0x1d8> - 414239: 39 d5 cmp %edx,%ebp - 41423b: 48 c7 05 4a 83 2b 00 movq $0x0,0x2b834a(%rip) # 6cc590 - 414242: 00 00 00 00 - 414246: 74 41 je 414289 <_IO_cleanup+0x99> - 414248: 48 8b 1d 71 5e 2b 00 mov 0x2b5e71(%rip),%rbx # 6ca0c0 <_IO_list_all> - 41424f: 89 d5 mov %edx,%ebp - 414251: 48 85 db test %rbx,%rbx - 414254: 74 3e je 414294 <_IO_cleanup+0xa4> - 414256: 8b 8b c0 00 00 00 mov 0xc0(%rbx),%ecx - 41425c: 48 89 1d 2d 83 2b 00 mov %rbx,0x2b832d(%rip) # 6cc590 - 414263: 85 c9 test %ecx,%ecx - 414265: 0f 8e 45 01 00 00 jle 4143b0 <_IO_cleanup+0x1c0> - 41426b: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 414272: 48 8b 70 18 mov 0x18(%rax),%rsi - 414276: 48 39 70 20 cmp %rsi,0x20(%rax) - 41427a: 77 9c ja 414218 <_IO_cleanup+0x28> - 41427c: 48 c7 05 09 83 2b 00 movq $0x0,0x2b8309(%rip) # 6cc590 - 414283: 00 00 00 00 - 414287: 89 ea mov %ebp,%edx - 414289: 48 8b 5b 68 mov 0x68(%rbx),%rbx - 41428d: 89 d5 mov %edx,%ebp - 41428f: 48 85 db test %rbx,%rbx - 414292: 75 c2 jne 414256 <_IO_cleanup+0x66> - 414294: 48 8b 1d 25 5e 2b 00 mov 0x2b5e25(%rip),%rbx # 6ca0c0 <_IO_list_all> - 41429b: 48 85 db test %rbx,%rbx - 41429e: 0f 84 2c 01 00 00 je 4143d0 <_IO_cleanup+0x1e0> - 4142a4: 64 4c 8b 2c 25 10 00 mov %fs:0x10,%r13 - 4142ab: 00 00 - 4142ad: e9 95 00 00 00 jmpq 414347 <_IO_cleanup+0x157> - 4142b2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4142b8: 48 8b 83 88 00 00 00 mov 0x88(%rbx),%rax - 4142bf: 4c 89 68 08 mov %r13,0x8(%rax) - 4142c3: c7 40 04 01 00 00 00 movl $0x1,0x4(%rax) - 4142ca: 80 3d b7 82 2b 00 00 cmpb $0x0,0x2b82b7(%rip) # 6cc588 - 4142d1: 75 2b jne 4142fe <_IO_cleanup+0x10e> - 4142d3: 8b 03 mov (%rbx),%eax - 4142d5: a8 01 test $0x1,%al - 4142d7: 75 25 jne 4142fe <_IO_cleanup+0x10e> - 4142d9: 83 c8 01 or $0x1,%eax - 4142dc: 89 03 mov %eax,(%rbx) - 4142de: 48 8b 05 9b 82 2b 00 mov 0x2b829b(%rip),%rax # 6cc580 - 4142e5: 48 89 1d 94 82 2b 00 mov %rbx,0x2b8294(%rip) # 6cc580 - 4142ec: 48 89 83 a8 00 00 00 mov %rax,0xa8(%rbx) - 4142f3: 48 8b 43 38 mov 0x38(%rbx),%rax - 4142f7: 48 89 83 b0 00 00 00 mov %rax,0xb0(%rbx) - 4142fe: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 414305: 31 d2 xor %edx,%edx - 414307: 31 f6 xor %esi,%esi - 414309: 48 89 df mov %rbx,%rdi - 41430c: ff 50 58 callq *0x58(%rax) - 41430f: 8b 83 c0 00 00 00 mov 0xc0(%rbx),%eax - 414315: 85 c0 test %eax,%eax - 414317: 7e 0e jle 414327 <_IO_cleanup+0x137> - 414319: 31 c9 xor %ecx,%ecx - 41431b: 31 d2 xor %edx,%edx - 41431d: 31 f6 xor %esi,%esi - 41431f: 48 89 df mov %rbx,%rdi - 414322: e8 69 f5 04 00 callq 463890 <_IO_wsetb> - 414327: 83 fd 02 cmp $0x2,%ebp - 41432a: 0f 85 b0 00 00 00 jne 4143e0 <_IO_cleanup+0x1f0> - 414330: c7 83 c0 00 00 00 ff movl $0xffffffff,0xc0(%rbx) - 414337: ff ff ff - 41433a: 48 8b 5b 68 mov 0x68(%rbx),%rbx - 41433e: 48 85 db test %rbx,%rbx - 414341: 0f 84 89 00 00 00 je 4143d0 <_IO_cleanup+0x1e0> - 414347: f6 03 02 testb $0x2,(%rbx) - 41434a: 75 e4 jne 414330 <_IO_cleanup+0x140> - 41434c: 8b 93 c0 00 00 00 mov 0xc0(%rbx),%edx - 414352: 85 d2 test %edx,%edx - 414354: 74 da je 414330 <_IO_cleanup+0x140> - 414356: 31 ed xor %ebp,%ebp - 414358: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx - 41435f: 48 85 d2 test %rdx,%rdx - 414362: 0f 84 62 ff ff ff je 4142ca <_IO_cleanup+0xda> - 414368: 4c 3b 6a 08 cmp 0x8(%rdx),%r13 - 41436c: 0f 84 c6 00 00 00 je 414438 <_IO_cleanup+0x248> - 414372: 31 c0 xor %eax,%eax - 414374: b9 01 00 00 00 mov $0x1,%ecx - 414379: 83 3d 3c 8e 2b 00 00 cmpl $0x0,0x2b8e3c(%rip) # 6cd1bc <__libc_multiple_threads> - 414380: 74 06 je 414388 <_IO_cleanup+0x198> - 414382: f0 0f b1 0a lock cmpxchg %ecx,(%rdx) - 414386: eb 03 jmp 41438b <_IO_cleanup+0x19b> - 414388: 0f b1 0a cmpxchg %ecx,(%rdx) - 41438b: 85 c0 test %eax,%eax - 41438d: 0f 84 25 ff ff ff je 4142b8 <_IO_cleanup+0xc8> - 414393: 83 c5 01 add $0x1,%ebp - 414396: e8 95 ac 02 00 callq 43f030 <__sched_yield> - 41439b: 83 fd 02 cmp $0x2,%ebp - 41439e: 0f 84 26 ff ff ff je 4142ca <_IO_cleanup+0xda> - 4143a4: eb b2 jmp 414358 <_IO_cleanup+0x168> - 4143a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4143ad: 00 00 00 - 4143b0: 48 8b 43 20 mov 0x20(%rbx),%rax - 4143b4: 48 39 43 28 cmp %rax,0x28(%rbx) - 4143b8: 0f 87 5a fe ff ff ja 414218 <_IO_cleanup+0x28> - 4143be: e9 b9 fe ff ff jmpq 41427c <_IO_cleanup+0x8c> - 4143c3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4143c8: 41 89 c4 mov %eax,%r12d - 4143cb: e9 69 fe ff ff jmpq 414239 <_IO_cleanup+0x49> - 4143d0: 48 83 c4 08 add $0x8,%rsp - 4143d4: 44 89 e0 mov %r12d,%eax - 4143d7: 5b pop %rbx - 4143d8: 5d pop %rbp - 4143d9: 41 5c pop %r12 - 4143db: 41 5d pop %r13 - 4143dd: c3 retq - 4143de: 66 90 xchg %ax,%ax - 4143e0: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx - 4143e7: 48 85 d2 test %rdx,%rdx - 4143ea: 0f 84 40 ff ff ff je 414330 <_IO_cleanup+0x140> - 4143f0: 83 6a 04 01 subl $0x1,0x4(%rdx) - 4143f4: 0f 85 36 ff ff ff jne 414330 <_IO_cleanup+0x140> - 4143fa: 48 c7 42 08 00 00 00 movq $0x0,0x8(%rdx) - 414401: 00 - 414402: 83 3d b3 8d 2b 00 00 cmpl $0x0,0x2b8db3(%rip) # 6cd1bc <__libc_multiple_threads> - 414409: 74 07 je 414412 <_IO_cleanup+0x222> - 41440b: f0 ff 0a lock decl (%rdx) - 41440e: 75 06 jne 414416 <_IO_cleanup+0x226> - 414410: eb 1a jmp 41442c <_IO_cleanup+0x23c> - 414412: ff 0a decl (%rdx) - 414414: 74 16 je 41442c <_IO_cleanup+0x23c> - 414416: 48 8d 3a lea (%rdx),%rdi - 414419: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 414420: e8 db e1 02 00 callq 442600 <__lll_unlock_wake_private> - 414425: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41442c: e9 ff fe ff ff jmpq 414330 <_IO_cleanup+0x140> - 414431: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 414438: 83 42 04 01 addl $0x1,0x4(%rdx) - 41443c: e9 89 fe ff ff jmpq 4142ca <_IO_cleanup+0xda> - 414441: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 414446: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41444d: 00 00 00 - -0000000000414450 <_IO_un_link>: - 414450: f6 07 80 testb $0x80,(%rdi) - 414453: 0f 84 da 01 00 00 je 414633 <_IO_un_link+0x1e3> - 414459: 55 push %rbp - 41445a: 53 push %rbx - 41445b: bd 00 00 00 00 mov $0x0,%ebp - 414460: 48 89 fb mov %rdi,%rbx - 414463: 48 83 ec 28 sub $0x28,%rsp - 414467: 48 85 ed test %rbp,%rbp - 41446a: 0f 84 28 02 00 00 je 414698 <_IO_un_link+0x248> - 414470: 31 d2 xor %edx,%edx - 414472: be 50 41 41 00 mov $0x414150,%esi - 414477: 48 89 e7 mov %rsp,%rdi - 41447a: e8 81 bb be ff callq 0 <_nl_current_LC_CTYPE> - 41447f: 64 48 8b 14 25 10 00 mov %fs:0x10,%rdx - 414486: 00 00 - 414488: 48 3b 15 19 81 2b 00 cmp 0x2b8119(%rip),%rdx # 6cc5a8 - 41448f: 74 46 je 4144d7 <_IO_un_link+0x87> - 414491: be 01 00 00 00 mov $0x1,%esi - 414496: 31 c0 xor %eax,%eax - 414498: 83 3d 1d 8d 2b 00 00 cmpl $0x0,0x2b8d1d(%rip) # 6cd1bc <__libc_multiple_threads> - 41449f: 74 0c je 4144ad <_IO_un_link+0x5d> - 4144a1: f0 0f b1 35 f7 80 2b lock cmpxchg %esi,0x2b80f7(%rip) # 6cc5a0 - 4144a8: 00 - 4144a9: 75 0b jne 4144b6 <_IO_un_link+0x66> - 4144ab: eb 23 jmp 4144d0 <_IO_un_link+0x80> - 4144ad: 0f b1 35 ec 80 2b 00 cmpxchg %esi,0x2b80ec(%rip) # 6cc5a0 - 4144b4: 74 1a je 4144d0 <_IO_un_link+0x80> - 4144b6: 48 8d 3d e3 80 2b 00 lea 0x2b80e3(%rip),%rdi # 6cc5a0 - 4144bd: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 4144c4: e8 07 e1 02 00 callq 4425d0 <__lll_lock_wait_private> - 4144c9: 48 81 c4 80 00 00 00 add $0x80,%rsp - 4144d0: 48 89 15 d1 80 2b 00 mov %rdx,0x2b80d1(%rip) # 6cc5a8 - 4144d7: 8b 33 mov (%rbx),%esi - 4144d9: 8b 15 c5 80 2b 00 mov 0x2b80c5(%rip),%edx # 6cc5a4 - 4144df: 48 89 1d aa 80 2b 00 mov %rbx,0x2b80aa(%rip) # 6cc590 - 4144e6: 89 f0 mov %esi,%eax - 4144e8: 83 c2 01 add $0x1,%edx - 4144eb: 25 00 80 00 00 and $0x8000,%eax - 4144f0: 89 15 ae 80 2b 00 mov %edx,0x2b80ae(%rip) # 6cc5a4 - 4144f6: 0f 85 7c 01 00 00 jne 414678 <_IO_un_link+0x228> - 4144fc: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx - 414503: 64 4c 8b 04 25 10 00 mov %fs:0x10,%r8 - 41450a: 00 00 - 41450c: 4c 3b 42 08 cmp 0x8(%rdx),%r8 - 414510: 74 3c je 41454e <_IO_un_link+0xfe> - 414512: be 01 00 00 00 mov $0x1,%esi - 414517: 83 3d 9e 8c 2b 00 00 cmpl $0x0,0x2b8c9e(%rip) # 6cd1bc <__libc_multiple_threads> - 41451e: 74 08 je 414528 <_IO_un_link+0xd8> - 414520: f0 0f b1 32 lock cmpxchg %esi,(%rdx) - 414524: 75 07 jne 41452d <_IO_un_link+0xdd> - 414526: eb 1b jmp 414543 <_IO_un_link+0xf3> - 414528: 0f b1 32 cmpxchg %esi,(%rdx) - 41452b: 74 16 je 414543 <_IO_un_link+0xf3> - 41452d: 48 8d 3a lea (%rdx),%rdi - 414530: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 414537: e8 94 e0 02 00 callq 4425d0 <__lll_lock_wait_private> - 41453c: 48 81 c4 80 00 00 00 add $0x80,%rsp - 414543: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx - 41454a: 4c 89 42 08 mov %r8,0x8(%rdx) - 41454e: 8b 33 mov (%rbx),%esi - 414550: 48 8b 3d 69 5b 2b 00 mov 0x2b5b69(%rip),%rdi # 6ca0c0 <_IO_list_all> - 414557: 83 42 04 01 addl $0x1,0x4(%rdx) - 41455b: 89 f0 mov %esi,%eax - 41455d: 25 00 80 00 00 and $0x8000,%eax - 414562: 48 85 ff test %rdi,%rdi - 414565: 74 36 je 41459d <_IO_un_link+0x14d> - 414567: 48 39 fb cmp %rdi,%rbx - 41456a: 0f 84 60 01 00 00 je 4146d0 <_IO_un_link+0x280> - 414570: 48 8b 4f 68 mov 0x68(%rdi),%rcx - 414574: 48 85 c9 test %rcx,%rcx - 414577: 74 24 je 41459d <_IO_un_link+0x14d> - 414579: 48 39 cb cmp %rcx,%rbx - 41457c: 75 16 jne 414594 <_IO_un_link+0x144> - 41457e: e9 64 01 00 00 jmpq 4146e7 <_IO_un_link+0x297> - 414583: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 414588: 48 39 d3 cmp %rdx,%rbx - 41458b: 0f 84 1f 01 00 00 je 4146b0 <_IO_un_link+0x260> - 414591: 48 89 d1 mov %rdx,%rcx - 414594: 48 8b 51 68 mov 0x68(%rcx),%rdx - 414598: 48 85 d2 test %rdx,%rdx - 41459b: 75 eb jne 414588 <_IO_un_link+0x138> - 41459d: 40 80 e6 7f and $0x7f,%sil - 4145a1: 85 c0 test %eax,%eax - 4145a3: 89 33 mov %esi,(%rbx) - 4145a5: 0f 85 bf 00 00 00 jne 41466a <_IO_un_link+0x21a> - 4145ab: 48 8b b3 88 00 00 00 mov 0x88(%rbx),%rsi - 4145b2: 8b 46 04 mov 0x4(%rsi),%eax - 4145b5: 83 e8 01 sub $0x1,%eax - 4145b8: 85 c0 test %eax,%eax - 4145ba: 89 46 04 mov %eax,0x4(%rsi) - 4145bd: 8b 15 e1 7f 2b 00 mov 0x2b7fe1(%rip),%edx # 6cc5a4 - 4145c3: 74 73 je 414638 <_IO_un_link+0x1e8> - 4145c5: 83 ea 01 sub $0x1,%edx - 4145c8: 48 c7 05 bd 7f 2b 00 movq $0x0,0x2b7fbd(%rip) # 6cc590 - 4145cf: 00 00 00 00 - 4145d3: 85 d2 test %edx,%edx - 4145d5: 89 15 c9 7f 2b 00 mov %edx,0x2b7fc9(%rip) # 6cc5a4 - 4145db: 75 41 jne 41461e <_IO_un_link+0x1ce> - 4145dd: 48 c7 05 c0 7f 2b 00 movq $0x0,0x2b7fc0(%rip) # 6cc5a8 - 4145e4: 00 00 00 00 - 4145e8: 83 3d cd 8b 2b 00 00 cmpl $0x0,0x2b8bcd(%rip) # 6cd1bc <__libc_multiple_threads> - 4145ef: 74 0b je 4145fc <_IO_un_link+0x1ac> - 4145f1: f0 ff 0d a8 7f 2b 00 lock decl 0x2b7fa8(%rip) # 6cc5a0 - 4145f8: 75 0a jne 414604 <_IO_un_link+0x1b4> - 4145fa: eb 22 jmp 41461e <_IO_un_link+0x1ce> - 4145fc: ff 0d 9e 7f 2b 00 decl 0x2b7f9e(%rip) # 6cc5a0 - 414602: 74 1a je 41461e <_IO_un_link+0x1ce> - 414604: 48 8d 3d 95 7f 2b 00 lea 0x2b7f95(%rip),%rdi # 6cc5a0 - 41460b: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 414612: e8 e9 df 02 00 callq 442600 <__lll_unlock_wake_private> - 414617: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41461e: 48 85 ed test %rbp,%rbp - 414621: 74 0a je 41462d <_IO_un_link+0x1dd> - 414623: 31 f6 xor %esi,%esi - 414625: 48 89 e7 mov %rsp,%rdi - 414628: e8 d3 b9 be ff callq 0 <_nl_current_LC_CTYPE> - 41462d: 48 83 c4 28 add $0x28,%rsp - 414631: 5b pop %rbx - 414632: 5d pop %rbp - 414633: f3 c3 repz retq - 414635: 0f 1f 00 nopl (%rax) - 414638: 48 c7 46 08 00 00 00 movq $0x0,0x8(%rsi) - 41463f: 00 - 414640: 83 3d 75 8b 2b 00 00 cmpl $0x0,0x2b8b75(%rip) # 6cd1bc <__libc_multiple_threads> - 414647: 74 07 je 414650 <_IO_un_link+0x200> - 414649: f0 ff 0e lock decl (%rsi) - 41464c: 75 06 jne 414654 <_IO_un_link+0x204> - 41464e: eb 1a jmp 41466a <_IO_un_link+0x21a> - 414650: ff 0e decl (%rsi) - 414652: 74 16 je 41466a <_IO_un_link+0x21a> - 414654: 48 8d 3e lea (%rsi),%rdi - 414657: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41465e: e8 9d df 02 00 callq 442600 <__lll_unlock_wake_private> - 414663: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41466a: 8b 15 34 7f 2b 00 mov 0x2b7f34(%rip),%edx # 6cc5a4 - 414670: e9 50 ff ff ff jmpq 4145c5 <_IO_un_link+0x175> - 414675: 0f 1f 00 nopl (%rax) - 414678: 48 8b 3d 41 5a 2b 00 mov 0x2b5a41(%rip),%rdi # 6ca0c0 <_IO_list_all> - 41467f: 48 85 ff test %rdi,%rdi - 414682: 0f 85 df fe ff ff jne 414567 <_IO_un_link+0x117> - 414688: 40 80 e6 7f and $0x7f,%sil - 41468c: 89 33 mov %esi,(%rbx) - 41468e: e9 32 ff ff ff jmpq 4145c5 <_IO_un_link+0x175> - 414693: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 414698: 48 c7 04 24 50 41 41 movq $0x414150,(%rsp) - 41469f: 00 - 4146a0: 48 c7 44 24 08 00 00 movq $0x0,0x8(%rsp) - 4146a7: 00 00 - 4146a9: e9 d1 fd ff ff jmpq 41447f <_IO_un_link+0x2f> - 4146ae: 66 90 xchg %ax,%ax - 4146b0: 48 83 c1 68 add $0x68,%rcx - 4146b4: 48 8b 53 68 mov 0x68(%rbx),%rdx - 4146b8: 83 05 d9 7e 2b 00 01 addl $0x1,0x2b7ed9(%rip) # 6cc598 <_IO_list_all_stamp> - 4146bf: 48 89 11 mov %rdx,(%rcx) - 4146c2: e9 d6 fe ff ff jmpq 41459d <_IO_un_link+0x14d> - 4146c7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 4146ce: 00 00 - 4146d0: 48 8b 53 68 mov 0x68(%rbx),%rdx - 4146d4: 83 05 bd 7e 2b 00 01 addl $0x1,0x2b7ebd(%rip) # 6cc598 <_IO_list_all_stamp> - 4146db: 48 89 15 de 59 2b 00 mov %rdx,0x2b59de(%rip) # 6ca0c0 <_IO_list_all> - 4146e2: e9 b6 fe ff ff jmpq 41459d <_IO_un_link+0x14d> - 4146e7: 48 8d 4f 68 lea 0x68(%rdi),%rcx - 4146eb: eb c7 jmp 4146b4 <_IO_un_link+0x264> - 4146ed: 0f 1f 00 nopl (%rax) - -00000000004146f0 <_IO_link_in>: - 4146f0: 8b 07 mov (%rdi),%eax - 4146f2: a8 80 test $0x80,%al - 4146f4: 0f 85 ab 01 00 00 jne 4148a5 <_IO_link_in+0x1b5> - 4146fa: 55 push %rbp - 4146fb: 53 push %rbx - 4146fc: bd 00 00 00 00 mov $0x0,%ebp - 414701: 0c 80 or $0x80,%al - 414703: 48 89 fb mov %rdi,%rbx - 414706: 48 83 ec 28 sub $0x28,%rsp - 41470a: 48 85 ed test %rbp,%rbp - 41470d: 89 07 mov %eax,(%rdi) - 41470f: 0f 84 bb 01 00 00 je 4148d0 <_IO_link_in+0x1e0> - 414715: 31 d2 xor %edx,%edx - 414717: be 50 41 41 00 mov $0x414150,%esi - 41471c: 48 89 e7 mov %rsp,%rdi - 41471f: e8 dc b8 be ff callq 0 <_nl_current_LC_CTYPE> - 414724: 64 48 8b 14 25 10 00 mov %fs:0x10,%rdx - 41472b: 00 00 - 41472d: 48 3b 15 74 7e 2b 00 cmp 0x2b7e74(%rip),%rdx # 6cc5a8 - 414734: 74 46 je 41477c <_IO_link_in+0x8c> - 414736: be 01 00 00 00 mov $0x1,%esi - 41473b: 31 c0 xor %eax,%eax - 41473d: 83 3d 78 8a 2b 00 00 cmpl $0x0,0x2b8a78(%rip) # 6cd1bc <__libc_multiple_threads> - 414744: 74 0c je 414752 <_IO_link_in+0x62> - 414746: f0 0f b1 35 52 7e 2b lock cmpxchg %esi,0x2b7e52(%rip) # 6cc5a0 - 41474d: 00 - 41474e: 75 0b jne 41475b <_IO_link_in+0x6b> - 414750: eb 23 jmp 414775 <_IO_link_in+0x85> - 414752: 0f b1 35 47 7e 2b 00 cmpxchg %esi,0x2b7e47(%rip) # 6cc5a0 - 414759: 74 1a je 414775 <_IO_link_in+0x85> - 41475b: 48 8d 3d 3e 7e 2b 00 lea 0x2b7e3e(%rip),%rdi # 6cc5a0 - 414762: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 414769: e8 62 de 02 00 callq 4425d0 <__lll_lock_wait_private> - 41476e: 48 81 c4 80 00 00 00 add $0x80,%rsp - 414775: 48 89 15 2c 7e 2b 00 mov %rdx,0x2b7e2c(%rip) # 6cc5a8 - 41477c: 8b 0b mov (%rbx),%ecx - 41477e: 8b 15 20 7e 2b 00 mov 0x2b7e20(%rip),%edx # 6cc5a4 - 414784: 48 89 1d 05 7e 2b 00 mov %rbx,0x2b7e05(%rip) # 6cc590 - 41478b: 89 c8 mov %ecx,%eax - 41478d: 83 c2 01 add $0x1,%edx - 414790: 25 00 80 00 00 and $0x8000,%eax - 414795: 89 15 09 7e 2b 00 mov %edx,0x2b7e09(%rip) # 6cc5a4 - 41479b: 0f 85 0f 01 00 00 jne 4148b0 <_IO_link_in+0x1c0> - 4147a1: 4c 8b 83 88 00 00 00 mov 0x88(%rbx),%r8 - 4147a8: 64 48 8b 14 25 10 00 mov %fs:0x10,%rdx - 4147af: 00 00 - 4147b1: 49 3b 50 08 cmp 0x8(%r8),%rdx - 4147b5: 74 40 je 4147f7 <_IO_link_in+0x107> - 4147b7: be 01 00 00 00 mov $0x1,%esi - 4147bc: 83 3d f9 89 2b 00 00 cmpl $0x0,0x2b89f9(%rip) # 6cd1bc <__libc_multiple_threads> - 4147c3: 74 09 je 4147ce <_IO_link_in+0xde> - 4147c5: f0 41 0f b1 30 lock cmpxchg %esi,(%r8) - 4147ca: 75 08 jne 4147d4 <_IO_link_in+0xe4> - 4147cc: eb 1c jmp 4147ea <_IO_link_in+0xfa> - 4147ce: 41 0f b1 30 cmpxchg %esi,(%r8) - 4147d2: 74 16 je 4147ea <_IO_link_in+0xfa> - 4147d4: 49 8d 38 lea (%r8),%rdi - 4147d7: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 4147de: e8 ed dd 02 00 callq 4425d0 <__lll_lock_wait_private> - 4147e3: 48 81 c4 80 00 00 00 add $0x80,%rsp - 4147ea: 4c 8b 83 88 00 00 00 mov 0x88(%rbx),%r8 - 4147f1: 8b 0b mov (%rbx),%ecx - 4147f3: 49 89 50 08 mov %rdx,0x8(%r8) - 4147f7: 48 8b 05 c2 58 2b 00 mov 0x2b58c2(%rip),%rax # 6ca0c0 <_IO_list_all> - 4147fe: 41 83 40 04 01 addl $0x1,0x4(%r8) - 414803: 83 05 8e 7d 2b 00 01 addl $0x1,0x2b7d8e(%rip) # 6cc598 <_IO_list_all_stamp> - 41480a: 80 e5 80 and $0x80,%ch - 41480d: 48 89 1d ac 58 2b 00 mov %rbx,0x2b58ac(%rip) # 6ca0c0 <_IO_list_all> - 414814: 48 89 43 68 mov %rax,0x68(%rbx) - 414818: 0f 85 06 01 00 00 jne 414924 <_IO_link_in+0x234> - 41481e: 41 8b 40 04 mov 0x4(%r8),%eax - 414822: 83 e8 01 sub $0x1,%eax - 414825: 85 c0 test %eax,%eax - 414827: 41 89 40 04 mov %eax,0x4(%r8) - 41482b: 8b 15 73 7d 2b 00 mov 0x2b7d73(%rip),%edx # 6cc5a4 - 414831: 0f 84 b9 00 00 00 je 4148f0 <_IO_link_in+0x200> - 414837: 83 ea 01 sub $0x1,%edx - 41483a: 48 c7 05 4b 7d 2b 00 movq $0x0,0x2b7d4b(%rip) # 6cc590 - 414841: 00 00 00 00 - 414845: 85 d2 test %edx,%edx - 414847: 89 15 57 7d 2b 00 mov %edx,0x2b7d57(%rip) # 6cc5a4 - 41484d: 75 41 jne 414890 <_IO_link_in+0x1a0> - 41484f: 48 c7 05 4e 7d 2b 00 movq $0x0,0x2b7d4e(%rip) # 6cc5a8 - 414856: 00 00 00 00 - 41485a: 83 3d 5b 89 2b 00 00 cmpl $0x0,0x2b895b(%rip) # 6cd1bc <__libc_multiple_threads> - 414861: 74 0b je 41486e <_IO_link_in+0x17e> - 414863: f0 ff 0d 36 7d 2b 00 lock decl 0x2b7d36(%rip) # 6cc5a0 - 41486a: 75 0a jne 414876 <_IO_link_in+0x186> - 41486c: eb 22 jmp 414890 <_IO_link_in+0x1a0> - 41486e: ff 0d 2c 7d 2b 00 decl 0x2b7d2c(%rip) # 6cc5a0 - 414874: 74 1a je 414890 <_IO_link_in+0x1a0> - 414876: 48 8d 3d 23 7d 2b 00 lea 0x2b7d23(%rip),%rdi # 6cc5a0 - 41487d: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 414884: e8 77 dd 02 00 callq 442600 <__lll_unlock_wake_private> - 414889: 48 81 c4 80 00 00 00 add $0x80,%rsp - 414890: 48 85 ed test %rbp,%rbp - 414893: 74 0a je 41489f <_IO_link_in+0x1af> - 414895: 31 f6 xor %esi,%esi - 414897: 48 89 e7 mov %rsp,%rdi - 41489a: e8 61 b7 be ff callq 0 <_nl_current_LC_CTYPE> - 41489f: 48 83 c4 28 add $0x28,%rsp - 4148a3: 5b pop %rbx - 4148a4: 5d pop %rbp - 4148a5: f3 c3 repz retq - 4148a7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 4148ae: 00 00 - 4148b0: 48 8b 05 09 58 2b 00 mov 0x2b5809(%rip),%rax # 6ca0c0 <_IO_list_all> - 4148b7: 83 05 da 7c 2b 00 01 addl $0x1,0x2b7cda(%rip) # 6cc598 <_IO_list_all_stamp> - 4148be: 48 89 1d fb 57 2b 00 mov %rbx,0x2b57fb(%rip) # 6ca0c0 <_IO_list_all> - 4148c5: 48 89 43 68 mov %rax,0x68(%rbx) - 4148c9: e9 69 ff ff ff jmpq 414837 <_IO_link_in+0x147> - 4148ce: 66 90 xchg %ax,%ax - 4148d0: 48 c7 04 24 50 41 41 movq $0x414150,(%rsp) - 4148d7: 00 - 4148d8: 48 c7 44 24 08 00 00 movq $0x0,0x8(%rsp) - 4148df: 00 00 - 4148e1: e9 3e fe ff ff jmpq 414724 <_IO_link_in+0x34> - 4148e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4148ed: 00 00 00 - 4148f0: 49 c7 40 08 00 00 00 movq $0x0,0x8(%r8) - 4148f7: 00 - 4148f8: 83 3d bd 88 2b 00 00 cmpl $0x0,0x2b88bd(%rip) # 6cd1bc <__libc_multiple_threads> - 4148ff: 74 08 je 414909 <_IO_link_in+0x219> - 414901: f0 41 ff 08 lock decl (%r8) - 414905: 75 07 jne 41490e <_IO_link_in+0x21e> - 414907: eb 1b jmp 414924 <_IO_link_in+0x234> - 414909: 41 ff 08 decl (%r8) - 41490c: 74 16 je 414924 <_IO_link_in+0x234> - 41490e: 49 8d 38 lea (%r8),%rdi - 414911: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 414918: e8 e3 dc 02 00 callq 442600 <__lll_unlock_wake_private> - 41491d: 48 81 c4 80 00 00 00 add $0x80,%rsp - 414924: 8b 15 7a 7c 2b 00 mov 0x2b7c7a(%rip),%edx # 6cc5a4 - 41492a: e9 08 ff ff ff jmpq 414837 <_IO_link_in+0x147> - 41492f: 90 nop - -0000000000414930 <_IO_least_marker>: - 414930: 48 8b 57 60 mov 0x60(%rdi),%rdx - 414934: 48 89 f0 mov %rsi,%rax - 414937: 48 2b 47 18 sub 0x18(%rdi),%rax - 41493b: 48 85 d2 test %rdx,%rdx - 41493e: 74 13 je 414953 <_IO_least_marker+0x23> - 414940: 48 63 4a 10 movslq 0x10(%rdx),%rcx - 414944: 48 8b 12 mov (%rdx),%rdx - 414947: 48 39 c8 cmp %rcx,%rax - 41494a: 48 0f 4f c1 cmovg %rcx,%rax - 41494e: 48 85 d2 test %rdx,%rdx - 414951: 75 ed jne 414940 <_IO_least_marker+0x10> - 414953: f3 c3 repz retq - 414955: 90 nop - 414956: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41495d: 00 00 00 - -0000000000414960 <_IO_switch_to_main_get_area>: - 414960: 48 8b 47 10 mov 0x10(%rdi),%rax - 414964: 48 8b 57 58 mov 0x58(%rdi),%rdx - 414968: 81 27 ff fe ff ff andl $0xfffffeff,(%rdi) - 41496e: 48 89 57 10 mov %rdx,0x10(%rdi) - 414972: 48 89 47 58 mov %rax,0x58(%rdi) - 414976: 48 8b 57 18 mov 0x18(%rdi),%rdx - 41497a: 48 8b 47 48 mov 0x48(%rdi),%rax - 41497e: 48 89 57 48 mov %rdx,0x48(%rdi) - 414982: 48 89 47 18 mov %rax,0x18(%rdi) - 414986: 48 89 47 08 mov %rax,0x8(%rdi) - 41498a: c3 retq - 41498b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - -0000000000414990 <_IO_switch_to_backup_area>: - 414990: 48 8b 57 10 mov 0x10(%rdi),%rdx - 414994: 48 8b 47 58 mov 0x58(%rdi),%rax - 414998: 48 8b 4f 48 mov 0x48(%rdi),%rcx - 41499c: 81 0f 00 01 00 00 orl $0x100,(%rdi) - 4149a2: 48 89 57 58 mov %rdx,0x58(%rdi) - 4149a6: 48 8b 57 18 mov 0x18(%rdi),%rdx - 4149aa: 48 89 47 10 mov %rax,0x10(%rdi) - 4149ae: 48 89 4f 18 mov %rcx,0x18(%rdi) - 4149b2: 48 89 57 48 mov %rdx,0x48(%rdi) - 4149b6: 48 89 47 08 mov %rax,0x8(%rdi) - 4149ba: c3 retq - 4149bb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - -00000000004149c0 <_IO_switch_to_get_mode>: - 4149c0: 48 8b 47 28 mov 0x28(%rdi),%rax - 4149c4: 48 3b 47 20 cmp 0x20(%rdi),%rax - 4149c8: 53 push %rbx - 4149c9: 48 89 fb mov %rdi,%rbx - 4149cc: 77 42 ja 414a10 <_IO_switch_to_get_mode+0x50> - 4149ce: 8b 13 mov (%rbx),%edx - 4149d0: f6 c6 01 test $0x1,%dh - 4149d3: 75 2b jne 414a00 <_IO_switch_to_get_mode+0x40> - 4149d5: 48 39 43 10 cmp %rax,0x10(%rbx) - 4149d9: 48 8b 4b 38 mov 0x38(%rbx),%rcx - 4149dd: 48 89 4b 18 mov %rcx,0x18(%rbx) - 4149e1: 73 04 jae 4149e7 <_IO_switch_to_get_mode+0x27> - 4149e3: 48 89 43 10 mov %rax,0x10(%rbx) - 4149e7: 80 e6 f7 and $0xf7,%dh - 4149ea: 48 89 43 08 mov %rax,0x8(%rbx) - 4149ee: 48 89 43 30 mov %rax,0x30(%rbx) - 4149f2: 48 89 43 20 mov %rax,0x20(%rbx) - 4149f6: 89 13 mov %edx,(%rbx) - 4149f8: 31 c0 xor %eax,%eax - 4149fa: 5b pop %rbx - 4149fb: c3 retq - 4149fc: 0f 1f 40 00 nopl 0x0(%rax) - 414a00: 48 8b 4b 50 mov 0x50(%rbx),%rcx - 414a04: 48 89 4b 18 mov %rcx,0x18(%rbx) - 414a08: eb dd jmp 4149e7 <_IO_switch_to_get_mode+0x27> - 414a0a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 414a10: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax - 414a17: be ff ff ff ff mov $0xffffffff,%esi - 414a1c: ff 50 18 callq *0x18(%rax) - 414a1f: 83 f8 ff cmp $0xffffffff,%eax - 414a22: 74 d6 je 4149fa <_IO_switch_to_get_mode+0x3a> - 414a24: 48 8b 43 28 mov 0x28(%rbx),%rax - 414a28: eb a4 jmp 4149ce <_IO_switch_to_get_mode+0xe> - 414a2a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - -0000000000414a30 <_IO_free_backup_area>: - 414a30: 53 push %rbx - 414a31: 8b 07 mov (%rdi),%eax - 414a33: 48 89 fb mov %rdi,%rbx - 414a36: f6 c4 01 test $0x1,%ah - 414a39: 74 45 je 414a80 <_IO_free_backup_area+0x50> - 414a3b: 80 e4 fe and $0xfe,%ah - 414a3e: 89 07 mov %eax,(%rdi) - 414a40: 48 8b 47 58 mov 0x58(%rdi),%rax - 414a44: 48 89 47 10 mov %rax,0x10(%rdi) - 414a48: 48 8b 43 48 mov 0x48(%rbx),%rax - 414a4c: 48 8b 7f 18 mov 0x18(%rdi),%rdi - 414a50: 48 89 43 18 mov %rax,0x18(%rbx) - 414a54: 48 89 43 08 mov %rax,0x8(%rbx) - 414a58: e8 53 93 00 00 callq 41ddb0 <__cfree> - 414a5d: 48 c7 43 48 00 00 00 movq $0x0,0x48(%rbx) - 414a64: 00 - 414a65: 48 c7 43 58 00 00 00 movq $0x0,0x58(%rbx) - 414a6c: 00 - 414a6d: 48 c7 43 50 00 00 00 movq $0x0,0x50(%rbx) - 414a74: 00 - 414a75: 5b pop %rbx - 414a76: c3 retq - 414a77: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 414a7e: 00 00 - 414a80: 48 8b 7f 48 mov 0x48(%rdi),%rdi - 414a84: eb d2 jmp 414a58 <_IO_free_backup_area+0x28> - 414a86: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 414a8d: 00 00 00 - -0000000000414a90 <__overflow>: - 414a90: 8b 87 c0 00 00 00 mov 0xc0(%rdi),%eax - 414a96: 85 c0 test %eax,%eax - 414a98: 75 0a jne 414aa4 <__overflow+0x14> - 414a9a: c7 87 c0 00 00 00 ff movl $0xffffffff,0xc0(%rdi) - 414aa1: ff ff ff - 414aa4: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax - 414aab: 48 8b 40 18 mov 0x18(%rax),%rax - 414aaf: ff e0 jmpq *%rax - 414ab1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 414ab6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 414abd: 00 00 00 - -0000000000414ac0 <__underflow>: - 414ac0: 53 push %rbx - 414ac1: 8b 87 c0 00 00 00 mov 0xc0(%rdi),%eax - 414ac7: 85 c0 test %eax,%eax - 414ac9: 75 55 jne 414b20 <__underflow+0x60> - 414acb: c7 87 c0 00 00 00 ff movl $0xffffffff,0xc0(%rdi) - 414ad2: ff ff ff - 414ad5: 8b 07 mov (%rdi),%eax - 414ad7: 48 89 fb mov %rdi,%rbx - 414ada: f6 c4 08 test $0x8,%ah - 414add: 0f 85 85 00 00 00 jne 414b68 <__underflow+0xa8> - 414ae3: 48 8b 57 08 mov 0x8(%rdi),%rdx - 414ae7: 48 8b 77 10 mov 0x10(%rdi),%rsi - 414aeb: 48 39 f2 cmp %rsi,%rdx - 414aee: 72 6d jb 414b5d <__underflow+0x9d> - 414af0: f6 c4 01 test $0x1,%ah - 414af3: 75 3b jne 414b30 <__underflow+0x70> - 414af5: 48 83 7b 60 00 cmpq $0x0,0x60(%rbx) - 414afa: 0f 84 e0 00 00 00 je 414be0 <__underflow+0x120> - 414b00: 48 89 df mov %rbx,%rdi - 414b03: e8 58 f4 ff ff callq 413f60 - 414b08: 85 c0 test %eax,%eax - 414b0a: 75 19 jne 414b25 <__underflow+0x65> - 414b0c: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 414b13: 48 89 df mov %rbx,%rdi - 414b16: 5b pop %rbx - 414b17: 48 8b 40 20 mov 0x20(%rax),%rax - 414b1b: ff e0 jmpq *%rax - 414b1d: 0f 1f 00 nopl (%rax) - 414b20: 83 f8 ff cmp $0xffffffff,%eax - 414b23: 74 b0 je 414ad5 <__underflow+0x15> - 414b25: b8 ff ff ff ff mov $0xffffffff,%eax - 414b2a: 5b pop %rbx - 414b2b: c3 retq - 414b2c: 0f 1f 40 00 nopl 0x0(%rax) - 414b30: 48 8b 4b 58 mov 0x58(%rbx),%rcx - 414b34: 48 8b 53 48 mov 0x48(%rbx),%rdx - 414b38: 80 e4 fe and $0xfe,%ah - 414b3b: 48 89 73 58 mov %rsi,0x58(%rbx) - 414b3f: 48 8b 73 18 mov 0x18(%rbx),%rsi - 414b43: 89 03 mov %eax,(%rbx) - 414b45: 48 39 d1 cmp %rdx,%rcx - 414b48: 48 89 4b 10 mov %rcx,0x10(%rbx) - 414b4c: 48 89 53 18 mov %rdx,0x18(%rbx) - 414b50: 48 89 73 48 mov %rsi,0x48(%rbx) - 414b54: 48 89 53 08 mov %rdx,0x8(%rbx) - 414b58: 48 89 ce mov %rcx,%rsi - 414b5b: 76 98 jbe 414af5 <__underflow+0x35> - 414b5d: 0f b6 02 movzbl (%rdx),%eax - 414b60: 5b pop %rbx - 414b61: c3 retq - 414b62: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 414b68: 48 8b 57 28 mov 0x28(%rdi),%rdx - 414b6c: 48 3b 57 20 cmp 0x20(%rdi),%rdx - 414b70: 77 4e ja 414bc0 <__underflow+0x100> - 414b72: f6 c4 01 test $0x1,%ah - 414b75: 75 31 jne 414ba8 <__underflow+0xe8> - 414b77: 48 8b 73 10 mov 0x10(%rbx),%rsi - 414b7b: 48 8b 4b 38 mov 0x38(%rbx),%rcx - 414b7f: 48 39 d6 cmp %rdx,%rsi - 414b82: 48 89 4b 18 mov %rcx,0x18(%rbx) - 414b86: 73 07 jae 414b8f <__underflow+0xcf> - 414b88: 48 89 53 10 mov %rdx,0x10(%rbx) - 414b8c: 48 89 d6 mov %rdx,%rsi - 414b8f: 80 e4 f7 and $0xf7,%ah - 414b92: 48 89 53 08 mov %rdx,0x8(%rbx) - 414b96: 48 89 53 30 mov %rdx,0x30(%rbx) - 414b9a: 48 89 53 20 mov %rdx,0x20(%rbx) - 414b9e: 89 03 mov %eax,(%rbx) - 414ba0: e9 46 ff ff ff jmpq 414aeb <__underflow+0x2b> - 414ba5: 0f 1f 00 nopl (%rax) - 414ba8: 48 8b 4b 50 mov 0x50(%rbx),%rcx - 414bac: 48 8b 73 10 mov 0x10(%rbx),%rsi - 414bb0: 48 89 4b 18 mov %rcx,0x18(%rbx) - 414bb4: eb d9 jmp 414b8f <__underflow+0xcf> - 414bb6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 414bbd: 00 00 00 - 414bc0: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax - 414bc7: be ff ff ff ff mov $0xffffffff,%esi - 414bcc: ff 50 18 callq *0x18(%rax) - 414bcf: 83 f8 ff cmp $0xffffffff,%eax - 414bd2: 0f 84 4d ff ff ff je 414b25 <__underflow+0x65> - 414bd8: 8b 03 mov (%rbx),%eax - 414bda: 48 8b 53 28 mov 0x28(%rbx),%rdx - 414bde: eb 92 jmp 414b72 <__underflow+0xb2> - 414be0: 48 8b 7b 48 mov 0x48(%rbx),%rdi - 414be4: 48 85 ff test %rdi,%rdi - 414be7: 0f 84 1f ff ff ff je 414b0c <__underflow+0x4c> - 414bed: f6 c4 01 test $0x1,%ah - 414bf0: 74 1c je 414c0e <__underflow+0x14e> - 414bf2: 80 e4 fe and $0xfe,%ah - 414bf5: 48 89 7b 08 mov %rdi,0x8(%rbx) - 414bf9: 89 03 mov %eax,(%rbx) - 414bfb: 48 8b 43 58 mov 0x58(%rbx),%rax - 414bff: 48 89 43 10 mov %rax,0x10(%rbx) - 414c03: 48 8b 43 18 mov 0x18(%rbx),%rax - 414c07: 48 89 7b 18 mov %rdi,0x18(%rbx) - 414c0b: 48 89 c7 mov %rax,%rdi - 414c0e: e8 9d 91 00 00 callq 41ddb0 <__cfree> - 414c13: 48 c7 43 48 00 00 00 movq $0x0,0x48(%rbx) - 414c1a: 00 - 414c1b: 48 c7 43 58 00 00 00 movq $0x0,0x58(%rbx) - 414c22: 00 - 414c23: 48 c7 43 50 00 00 00 movq $0x0,0x50(%rbx) - 414c2a: 00 - 414c2b: e9 dc fe ff ff jmpq 414b0c <__underflow+0x4c> - -0000000000414c30 <__uflow>: - 414c30: 53 push %rbx - 414c31: 8b 87 c0 00 00 00 mov 0xc0(%rdi),%eax - 414c37: 85 c0 test %eax,%eax - 414c39: 75 55 jne 414c90 <__uflow+0x60> - 414c3b: c7 87 c0 00 00 00 ff movl $0xffffffff,0xc0(%rdi) - 414c42: ff ff ff - 414c45: 8b 07 mov (%rdi),%eax - 414c47: 48 89 fb mov %rdi,%rbx - 414c4a: f6 c4 08 test $0x8,%ah - 414c4d: 0f 85 dd 00 00 00 jne 414d30 <__uflow+0x100> - 414c53: 48 8b 57 08 mov 0x8(%rdi),%rdx - 414c57: 48 8b 77 10 mov 0x10(%rdi),%rsi - 414c5b: 48 39 f2 cmp %rsi,%rdx - 414c5e: 0f 82 bc 00 00 00 jb 414d20 <__uflow+0xf0> - 414c64: f6 c4 01 test $0x1,%ah - 414c67: 75 37 jne 414ca0 <__uflow+0x70> - 414c69: 48 83 7b 60 00 cmpq $0x0,0x60(%rbx) - 414c6e: 74 64 je 414cd4 <__uflow+0xa4> - 414c70: 48 89 df mov %rbx,%rdi - 414c73: e8 e8 f2 ff ff callq 413f60 - 414c78: 85 c0 test %eax,%eax - 414c7a: 75 19 jne 414c95 <__uflow+0x65> - 414c7c: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 414c83: 48 89 df mov %rbx,%rdi - 414c86: 5b pop %rbx - 414c87: 48 8b 40 28 mov 0x28(%rax),%rax - 414c8b: ff e0 jmpq *%rax - 414c8d: 0f 1f 00 nopl (%rax) - 414c90: 83 f8 ff cmp $0xffffffff,%eax - 414c93: 74 b0 je 414c45 <__uflow+0x15> - 414c95: b8 ff ff ff ff mov $0xffffffff,%eax - 414c9a: 5b pop %rbx - 414c9b: c3 retq - 414c9c: 0f 1f 40 00 nopl 0x0(%rax) - 414ca0: 48 8b 4b 58 mov 0x58(%rbx),%rcx - 414ca4: 48 8b 53 48 mov 0x48(%rbx),%rdx - 414ca8: 80 e4 fe and $0xfe,%ah - 414cab: 48 89 73 58 mov %rsi,0x58(%rbx) - 414caf: 48 8b 73 18 mov 0x18(%rbx),%rsi - 414cb3: 89 03 mov %eax,(%rbx) - 414cb5: 48 39 d1 cmp %rdx,%rcx - 414cb8: 48 89 4b 10 mov %rcx,0x10(%rbx) - 414cbc: 48 89 53 18 mov %rdx,0x18(%rbx) - 414cc0: 48 89 73 48 mov %rsi,0x48(%rbx) - 414cc4: 77 5a ja 414d20 <__uflow+0xf0> - 414cc6: 48 83 7b 60 00 cmpq $0x0,0x60(%rbx) - 414ccb: 48 89 53 08 mov %rdx,0x8(%rbx) - 414ccf: 48 89 ce mov %rcx,%rsi - 414cd2: 75 9c jne 414c70 <__uflow+0x40> - 414cd4: 48 8b 7b 48 mov 0x48(%rbx),%rdi - 414cd8: 48 85 ff test %rdi,%rdi - 414cdb: 74 9f je 414c7c <__uflow+0x4c> - 414cdd: f6 c4 01 test $0x1,%ah - 414ce0: 74 1c je 414cfe <__uflow+0xce> - 414ce2: 80 e4 fe and $0xfe,%ah - 414ce5: 48 89 7b 08 mov %rdi,0x8(%rbx) - 414ce9: 89 03 mov %eax,(%rbx) - 414ceb: 48 8b 43 58 mov 0x58(%rbx),%rax - 414cef: 48 89 43 10 mov %rax,0x10(%rbx) - 414cf3: 48 8b 43 18 mov 0x18(%rbx),%rax - 414cf7: 48 89 7b 18 mov %rdi,0x18(%rbx) - 414cfb: 48 89 c7 mov %rax,%rdi - 414cfe: e8 ad 90 00 00 callq 41ddb0 <__cfree> - 414d03: 48 c7 43 48 00 00 00 movq $0x0,0x48(%rbx) - 414d0a: 00 - 414d0b: 48 c7 43 58 00 00 00 movq $0x0,0x58(%rbx) - 414d12: 00 - 414d13: 48 c7 43 50 00 00 00 movq $0x0,0x50(%rbx) - 414d1a: 00 - 414d1b: e9 5c ff ff ff jmpq 414c7c <__uflow+0x4c> - 414d20: 48 8d 42 01 lea 0x1(%rdx),%rax - 414d24: 48 89 43 08 mov %rax,0x8(%rbx) - 414d28: 0f b6 02 movzbl (%rdx),%eax - 414d2b: 5b pop %rbx - 414d2c: c3 retq - 414d2d: 0f 1f 00 nopl (%rax) - 414d30: 48 8b 57 28 mov 0x28(%rdi),%rdx - 414d34: 48 3b 57 20 cmp 0x20(%rdi),%rdx - 414d38: 77 46 ja 414d80 <__uflow+0x150> - 414d3a: f6 c4 01 test $0x1,%ah - 414d3d: 75 31 jne 414d70 <__uflow+0x140> - 414d3f: 48 8b 73 10 mov 0x10(%rbx),%rsi - 414d43: 48 8b 4b 38 mov 0x38(%rbx),%rcx - 414d47: 48 39 d6 cmp %rdx,%rsi - 414d4a: 48 89 4b 18 mov %rcx,0x18(%rbx) - 414d4e: 73 07 jae 414d57 <__uflow+0x127> - 414d50: 48 89 53 10 mov %rdx,0x10(%rbx) - 414d54: 48 89 d6 mov %rdx,%rsi - 414d57: 80 e4 f7 and $0xf7,%ah - 414d5a: 48 89 53 08 mov %rdx,0x8(%rbx) - 414d5e: 48 89 53 30 mov %rdx,0x30(%rbx) - 414d62: 48 89 53 20 mov %rdx,0x20(%rbx) - 414d66: 89 03 mov %eax,(%rbx) - 414d68: e9 ee fe ff ff jmpq 414c5b <__uflow+0x2b> - 414d6d: 0f 1f 00 nopl (%rax) - 414d70: 48 8b 4b 50 mov 0x50(%rbx),%rcx - 414d74: 48 8b 73 10 mov 0x10(%rbx),%rsi - 414d78: 48 89 4b 18 mov %rcx,0x18(%rbx) - 414d7c: eb d9 jmp 414d57 <__uflow+0x127> - 414d7e: 66 90 xchg %ax,%ax - 414d80: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax - 414d87: be ff ff ff ff mov $0xffffffff,%esi - 414d8c: ff 50 18 callq *0x18(%rax) - 414d8f: 83 f8 ff cmp $0xffffffff,%eax - 414d92: 0f 84 fd fe ff ff je 414c95 <__uflow+0x65> - 414d98: 8b 03 mov (%rbx),%eax - 414d9a: 48 8b 53 28 mov 0x28(%rbx),%rdx - 414d9e: eb 9a jmp 414d3a <__uflow+0x10a> - -0000000000414da0 <_IO_setb>: - 414da0: 53 push %rbx - 414da1: 48 89 fb mov %rdi,%rbx - 414da4: 48 83 ec 20 sub $0x20,%rsp - 414da8: 48 8b 7f 38 mov 0x38(%rdi),%rdi - 414dac: 8b 03 mov (%rbx),%eax - 414dae: 48 85 ff test %rdi,%rdi - 414db1: 74 04 je 414db7 <_IO_setb+0x17> - 414db3: a8 01 test $0x1,%al - 414db5: 74 21 je 414dd8 <_IO_setb+0x38> - 414db7: 48 89 53 40 mov %rdx,0x40(%rbx) - 414dbb: 89 c2 mov %eax,%edx - 414dbd: 83 c8 01 or $0x1,%eax - 414dc0: 83 e2 fe and $0xfffffffe,%edx - 414dc3: 85 c9 test %ecx,%ecx - 414dc5: 48 89 73 38 mov %rsi,0x38(%rbx) - 414dc9: 0f 45 c2 cmovne %edx,%eax - 414dcc: 89 03 mov %eax,(%rbx) - 414dce: 48 83 c4 20 add $0x20,%rsp - 414dd2: 5b pop %rbx - 414dd3: c3 retq - 414dd4: 0f 1f 40 00 nopl 0x0(%rax) - 414dd8: 89 4c 24 1c mov %ecx,0x1c(%rsp) - 414ddc: 48 89 54 24 10 mov %rdx,0x10(%rsp) - 414de1: 48 89 74 24 08 mov %rsi,0x8(%rsp) - 414de6: e8 c5 8f 00 00 callq 41ddb0 <__cfree> - 414deb: 8b 03 mov (%rbx),%eax - 414ded: 8b 4c 24 1c mov 0x1c(%rsp),%ecx - 414df1: 48 8b 54 24 10 mov 0x10(%rsp),%rdx - 414df6: 48 8b 74 24 08 mov 0x8(%rsp),%rsi - 414dfb: eb ba jmp 414db7 <_IO_setb+0x17> - 414dfd: 0f 1f 00 nopl (%rax) - -0000000000414e00 <_IO_doallocbuf>: - 414e00: 48 83 7f 38 00 cmpq $0x0,0x38(%rdi) - 414e05: 74 09 je 414e10 <_IO_doallocbuf+0x10> - 414e07: c3 retq - 414e08: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 414e0f: 00 - 414e10: 41 54 push %r12 - 414e12: 55 push %rbp - 414e13: 53 push %rbx - 414e14: 8b 07 mov (%rdi),%eax - 414e16: 48 89 fb mov %rdi,%rbx - 414e19: a8 02 test $0x2,%al - 414e1b: 74 0a je 414e27 <_IO_doallocbuf+0x27> - 414e1d: 8b 97 c0 00 00 00 mov 0xc0(%rdi),%edx - 414e23: 85 d2 test %edx,%edx - 414e25: 7e 49 jle 414e70 <_IO_doallocbuf+0x70> - 414e27: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 414e2e: 48 89 df mov %rbx,%rdi - 414e31: ff 50 68 callq *0x68(%rax) - 414e34: 83 f8 ff cmp $0xffffffff,%eax - 414e37: 74 07 je 414e40 <_IO_doallocbuf+0x40> - 414e39: 5b pop %rbx - 414e3a: 5d pop %rbp - 414e3b: 41 5c pop %r12 - 414e3d: c3 retq - 414e3e: 66 90 xchg %ax,%ax - 414e40: 48 8b 7b 38 mov 0x38(%rbx),%rdi - 414e44: 4c 8d a3 84 00 00 00 lea 0x84(%rbx),%r12 - 414e4b: 48 8d ab 83 00 00 00 lea 0x83(%rbx),%rbp - 414e52: 8b 03 mov (%rbx),%eax - 414e54: 48 85 ff test %rdi,%rdi - 414e57: 74 04 je 414e5d <_IO_doallocbuf+0x5d> - 414e59: a8 01 test $0x1,%al - 414e5b: 74 23 je 414e80 <_IO_doallocbuf+0x80> - 414e5d: 83 c8 01 or $0x1,%eax - 414e60: 48 89 6b 38 mov %rbp,0x38(%rbx) - 414e64: 4c 89 63 40 mov %r12,0x40(%rbx) - 414e68: 89 03 mov %eax,(%rbx) - 414e6a: eb cd jmp 414e39 <_IO_doallocbuf+0x39> - 414e6c: 0f 1f 40 00 nopl 0x0(%rax) - 414e70: 4c 8d a7 84 00 00 00 lea 0x84(%rdi),%r12 - 414e77: 48 8d af 83 00 00 00 lea 0x83(%rdi),%rbp - 414e7e: eb dd jmp 414e5d <_IO_doallocbuf+0x5d> - 414e80: e8 2b 8f 00 00 callq 41ddb0 <__cfree> - 414e85: 8b 03 mov (%rbx),%eax - 414e87: eb d4 jmp 414e5d <_IO_doallocbuf+0x5d> - 414e89: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - -0000000000414e90 <_IO_default_underflow>: - 414e90: b8 ff ff ff ff mov $0xffffffff,%eax - 414e95: c3 retq - 414e96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 414e9d: 00 00 00 - -0000000000414ea0 <_IO_default_uflow>: - 414ea0: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax - 414ea7: 53 push %rbx - 414ea8: 48 89 fb mov %rdi,%rbx - 414eab: ff 50 20 callq *0x20(%rax) - 414eae: 83 f8 ff cmp $0xffffffff,%eax - 414eb1: 74 0f je 414ec2 <_IO_default_uflow+0x22> - 414eb3: 48 8b 43 08 mov 0x8(%rbx),%rax - 414eb7: 48 8d 50 01 lea 0x1(%rax),%rdx - 414ebb: 48 89 53 08 mov %rdx,0x8(%rbx) - 414ebf: 0f b6 00 movzbl (%rax),%eax - 414ec2: 5b pop %rbx - 414ec3: c3 retq - 414ec4: 66 90 xchg %ax,%ax - 414ec6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 414ecd: 00 00 00 - -0000000000414ed0 <_IO_default_xsputn>: - 414ed0: 48 85 d2 test %rdx,%rdx - 414ed3: 0f 84 b7 00 00 00 je 414f90 <_IO_default_xsputn+0xc0> - 414ed9: 41 56 push %r14 - 414edb: 41 55 push %r13 - 414edd: 49 89 f6 mov %rsi,%r14 - 414ee0: 41 54 push %r12 - 414ee2: 55 push %rbp - 414ee3: 49 89 fc mov %rdi,%r12 - 414ee6: 53 push %rbx - 414ee7: 49 89 d5 mov %rdx,%r13 - 414eea: 48 89 d5 mov %rdx,%rbp - 414eed: 0f 1f 00 nopl (%rax) - 414ef0: 49 8b 7c 24 28 mov 0x28(%r12),%rdi - 414ef5: 49 8b 5c 24 30 mov 0x30(%r12),%rbx - 414efa: 48 39 df cmp %rbx,%rdi - 414efd: 73 36 jae 414f35 <_IO_default_xsputn+0x65> - 414eff: 48 29 fb sub %rdi,%rbx - 414f02: 48 39 dd cmp %rbx,%rbp - 414f05: 48 0f 46 dd cmovbe %rbp,%rbx - 414f09: 48 83 fb 14 cmp $0x14,%rbx - 414f0d: 77 51 ja 414f60 <_IO_default_xsputn+0x90> - 414f0f: 48 85 db test %rbx,%rbx - 414f12: 74 1e je 414f32 <_IO_default_xsputn+0x62> - 414f14: 31 c0 xor %eax,%eax - 414f16: 41 0f b6 14 06 movzbl (%r14,%rax,1),%edx - 414f1b: 88 14 07 mov %dl,(%rdi,%rax,1) - 414f1e: 48 83 c0 01 add $0x1,%rax - 414f22: 48 39 c3 cmp %rax,%rbx - 414f25: 75 ef jne 414f16 <_IO_default_xsputn+0x46> - 414f27: 48 01 df add %rbx,%rdi - 414f2a: 49 01 de add %rbx,%r14 - 414f2d: 49 89 7c 24 28 mov %rdi,0x28(%r12) - 414f32: 48 29 dd sub %rbx,%rbp - 414f35: 48 85 ed test %rbp,%rbp - 414f38: 74 3e je 414f78 <_IO_default_xsputn+0xa8> - 414f3a: 49 8b 84 24 d8 00 00 mov 0xd8(%r12),%rax - 414f41: 00 - 414f42: 41 0f b6 36 movzbl (%r14),%esi - 414f46: 4c 89 e7 mov %r12,%rdi - 414f49: 49 8d 5e 01 lea 0x1(%r14),%rbx - 414f4d: ff 50 18 callq *0x18(%rax) - 414f50: 83 f8 ff cmp $0xffffffff,%eax - 414f53: 74 23 je 414f78 <_IO_default_xsputn+0xa8> - 414f55: 48 83 ed 01 sub $0x1,%rbp - 414f59: 49 89 de mov %rbx,%r14 - 414f5c: eb 92 jmp 414ef0 <_IO_default_xsputn+0x20> - 414f5e: 66 90 xchg %ax,%ax - 414f60: 4c 89 f6 mov %r14,%rsi - 414f63: 48 89 da mov %rbx,%rdx - 414f66: 49 01 de add %rbx,%r14 - 414f69: e8 52 16 01 00 callq 4265c0 <__mempcpy> - 414f6e: 49 89 44 24 28 mov %rax,0x28(%r12) - 414f73: eb bd jmp 414f32 <_IO_default_xsputn+0x62> - 414f75: 0f 1f 00 nopl (%rax) - 414f78: 4c 89 e8 mov %r13,%rax - 414f7b: 5b pop %rbx - 414f7c: 48 29 e8 sub %rbp,%rax - 414f7f: 5d pop %rbp - 414f80: 41 5c pop %r12 - 414f82: 41 5d pop %r13 - 414f84: 41 5e pop %r14 - 414f86: c3 retq - 414f87: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 414f8e: 00 00 - 414f90: 31 c0 xor %eax,%eax - 414f92: c3 retq - 414f93: 0f 1f 00 nopl (%rax) - 414f96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 414f9d: 00 00 00 - -0000000000414fa0 <_IO_sgetn>: - 414fa0: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax - 414fa7: 48 8b 40 40 mov 0x40(%rax),%rax - 414fab: ff e0 jmpq *%rax - 414fad: 0f 1f 00 nopl (%rax) - -0000000000414fb0 <_IO_default_xsgetn>: - 414fb0: 41 56 push %r14 - 414fb2: 41 55 push %r13 - 414fb4: 49 89 d6 mov %rdx,%r14 - 414fb7: 41 54 push %r12 - 414fb9: 49 89 f4 mov %rsi,%r12 - 414fbc: 55 push %rbp - 414fbd: 53 push %rbx - 414fbe: 48 8b 4f 08 mov 0x8(%rdi),%rcx - 414fc2: 48 89 fb mov %rdi,%rbx - 414fc5: 48 8b 77 10 mov 0x10(%rdi),%rsi - 414fc9: 49 89 d5 mov %rdx,%r13 - 414fcc: 0f 1f 40 00 nopl 0x0(%rax) - 414fd0: 48 39 ce cmp %rcx,%rsi - 414fd3: 76 4a jbe 41501f <_IO_default_xsgetn+0x6f> - 414fd5: 48 29 ce sub %rcx,%rsi - 414fd8: 49 39 f6 cmp %rsi,%r14 - 414fdb: 49 0f 46 f6 cmovbe %r14,%rsi - 414fdf: 48 83 fe 14 cmp $0x14,%rsi - 414fe3: 48 89 f5 mov %rsi,%rbp - 414fe6: 0f 87 44 01 00 00 ja 415130 <_IO_default_xsgetn+0x180> - 414fec: 48 85 f6 test %rsi,%rsi - 414fef: 74 2b je 41501c <_IO_default_xsgetn+0x6c> - 414ff1: 8d 76 ff lea -0x1(%rsi),%esi - 414ff4: 31 c0 xor %eax,%eax - 414ff6: 48 89 f2 mov %rsi,%rdx - 414ff9: 48 83 c6 01 add $0x1,%rsi - 414ffd: 0f b6 3c 01 movzbl (%rcx,%rax,1),%edi - 415001: 41 88 3c 04 mov %dil,(%r12,%rax,1) - 415005: 48 83 c0 01 add $0x1,%rax - 415009: 48 39 f0 cmp %rsi,%rax - 41500c: 75 ef jne 414ffd <_IO_default_xsgetn+0x4d> - 41500e: 48 83 c2 01 add $0x1,%rdx - 415012: 49 01 d4 add %rdx,%r12 - 415015: 48 01 ca add %rcx,%rdx - 415018: 48 89 53 08 mov %rdx,0x8(%rbx) - 41501c: 49 29 ee sub %rbp,%r14 - 41501f: 4d 85 f6 test %r14,%r14 - 415022: 0f 84 b1 00 00 00 je 4150d9 <_IO_default_xsgetn+0x129> - 415028: 8b 83 c0 00 00 00 mov 0xc0(%rbx),%eax - 41502e: 85 c0 test %eax,%eax - 415030: 0f 85 9a 00 00 00 jne 4150d0 <_IO_default_xsgetn+0x120> - 415036: c7 83 c0 00 00 00 ff movl $0xffffffff,0xc0(%rbx) - 41503d: ff ff ff - 415040: 8b 03 mov (%rbx),%eax - 415042: f6 c4 08 test $0x8,%ah - 415045: 0f 85 a5 00 00 00 jne 4150f0 <_IO_default_xsgetn+0x140> - 41504b: 48 8b 4b 08 mov 0x8(%rbx),%rcx - 41504f: 48 8b 73 10 mov 0x10(%rbx),%rsi - 415053: 48 39 ce cmp %rcx,%rsi - 415056: 0f 87 74 ff ff ff ja 414fd0 <_IO_default_xsgetn+0x20> - 41505c: f6 c4 01 test $0x1,%ah - 41505f: 74 31 je 415092 <_IO_default_xsgetn+0xe2> - 415061: 48 8b 53 58 mov 0x58(%rbx),%rdx - 415065: 48 8b 4b 48 mov 0x48(%rbx),%rcx - 415069: 80 e4 fe and $0xfe,%ah - 41506c: 48 89 73 58 mov %rsi,0x58(%rbx) - 415070: 48 8b 73 18 mov 0x18(%rbx),%rsi - 415074: 89 03 mov %eax,(%rbx) - 415076: 48 39 ca cmp %rcx,%rdx - 415079: 48 89 53 10 mov %rdx,0x10(%rbx) - 41507d: 48 89 4b 18 mov %rcx,0x18(%rbx) - 415081: 48 89 73 48 mov %rsi,0x48(%rbx) - 415085: 48 89 4b 08 mov %rcx,0x8(%rbx) - 415089: 48 89 d6 mov %rdx,%rsi - 41508c: 0f 87 3e ff ff ff ja 414fd0 <_IO_default_xsgetn+0x20> - 415092: 48 83 7b 60 00 cmpq $0x0,0x60(%rbx) - 415097: 0f 84 b3 00 00 00 je 415150 <_IO_default_xsgetn+0x1a0> - 41509d: 48 89 df mov %rbx,%rdi - 4150a0: e8 bb ee ff ff callq 413f60 - 4150a5: 85 c0 test %eax,%eax - 4150a7: 75 30 jne 4150d9 <_IO_default_xsgetn+0x129> - 4150a9: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 4150b0: 48 89 df mov %rbx,%rdi - 4150b3: ff 50 20 callq *0x20(%rax) - 4150b6: 83 f8 ff cmp $0xffffffff,%eax - 4150b9: 74 1e je 4150d9 <_IO_default_xsgetn+0x129> - 4150bb: 48 8b 4b 08 mov 0x8(%rbx),%rcx - 4150bf: 48 8b 73 10 mov 0x10(%rbx),%rsi - 4150c3: e9 08 ff ff ff jmpq 414fd0 <_IO_default_xsgetn+0x20> - 4150c8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 4150cf: 00 - 4150d0: 83 f8 ff cmp $0xffffffff,%eax - 4150d3: 0f 84 67 ff ff ff je 415040 <_IO_default_xsgetn+0x90> - 4150d9: 4c 89 e8 mov %r13,%rax - 4150dc: 5b pop %rbx - 4150dd: 4c 29 f0 sub %r14,%rax - 4150e0: 5d pop %rbp - 4150e1: 41 5c pop %r12 - 4150e3: 41 5d pop %r13 - 4150e5: 41 5e pop %r14 - 4150e7: c3 retq - 4150e8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 4150ef: 00 - 4150f0: 48 8b 4b 28 mov 0x28(%rbx),%rcx - 4150f4: 48 3b 4b 20 cmp 0x20(%rbx),%rcx - 4150f8: 0f 87 ca 00 00 00 ja 4151c8 <_IO_default_xsgetn+0x218> - 4150fe: f6 c4 01 test $0x1,%ah - 415101: 0f 84 99 00 00 00 je 4151a0 <_IO_default_xsgetn+0x1f0> - 415107: 48 8b 53 50 mov 0x50(%rbx),%rdx - 41510b: 48 8b 73 10 mov 0x10(%rbx),%rsi - 41510f: 48 89 53 18 mov %rdx,0x18(%rbx) - 415113: 80 e4 f7 and $0xf7,%ah - 415116: 48 89 4b 08 mov %rcx,0x8(%rbx) - 41511a: 48 89 4b 30 mov %rcx,0x30(%rbx) - 41511e: 48 89 4b 20 mov %rcx,0x20(%rbx) - 415122: 89 03 mov %eax,(%rbx) - 415124: e9 2a ff ff ff jmpq 415053 <_IO_default_xsgetn+0xa3> - 415129: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 415130: 48 89 f2 mov %rsi,%rdx - 415133: 4c 89 e7 mov %r12,%rdi - 415136: 48 89 ce mov %rcx,%rsi - 415139: e8 82 14 01 00 callq 4265c0 <__mempcpy> - 41513e: 48 01 6b 08 add %rbp,0x8(%rbx) - 415142: 49 89 c4 mov %rax,%r12 - 415145: e9 d2 fe ff ff jmpq 41501c <_IO_default_xsgetn+0x6c> - 41514a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 415150: 48 8b 7b 48 mov 0x48(%rbx),%rdi - 415154: 48 85 ff test %rdi,%rdi - 415157: 0f 84 4c ff ff ff je 4150a9 <_IO_default_xsgetn+0xf9> - 41515d: f6 c4 01 test $0x1,%ah - 415160: 74 1c je 41517e <_IO_default_xsgetn+0x1ce> - 415162: 80 e4 fe and $0xfe,%ah - 415165: 48 89 7b 08 mov %rdi,0x8(%rbx) - 415169: 89 03 mov %eax,(%rbx) - 41516b: 48 8b 43 58 mov 0x58(%rbx),%rax - 41516f: 48 89 43 10 mov %rax,0x10(%rbx) - 415173: 48 8b 43 18 mov 0x18(%rbx),%rax - 415177: 48 89 7b 18 mov %rdi,0x18(%rbx) - 41517b: 48 89 c7 mov %rax,%rdi - 41517e: e8 2d 8c 00 00 callq 41ddb0 <__cfree> - 415183: 48 c7 43 48 00 00 00 movq $0x0,0x48(%rbx) - 41518a: 00 - 41518b: 48 c7 43 58 00 00 00 movq $0x0,0x58(%rbx) - 415192: 00 - 415193: 48 c7 43 50 00 00 00 movq $0x0,0x50(%rbx) - 41519a: 00 - 41519b: e9 09 ff ff ff jmpq 4150a9 <_IO_default_xsgetn+0xf9> - 4151a0: 48 8b 73 10 mov 0x10(%rbx),%rsi - 4151a4: 48 8b 53 38 mov 0x38(%rbx),%rdx - 4151a8: 48 39 ce cmp %rcx,%rsi - 4151ab: 48 89 53 18 mov %rdx,0x18(%rbx) - 4151af: 0f 83 5e ff ff ff jae 415113 <_IO_default_xsgetn+0x163> - 4151b5: 48 89 4b 10 mov %rcx,0x10(%rbx) - 4151b9: 48 89 ce mov %rcx,%rsi - 4151bc: e9 52 ff ff ff jmpq 415113 <_IO_default_xsgetn+0x163> - 4151c1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4151c8: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 4151cf: be ff ff ff ff mov $0xffffffff,%esi - 4151d4: 48 89 df mov %rbx,%rdi - 4151d7: ff 50 18 callq *0x18(%rax) - 4151da: 83 f8 ff cmp $0xffffffff,%eax - 4151dd: 0f 84 f6 fe ff ff je 4150d9 <_IO_default_xsgetn+0x129> - 4151e3: 8b 03 mov (%rbx),%eax - 4151e5: 48 8b 4b 28 mov 0x28(%rbx),%rcx - 4151e9: e9 10 ff ff ff jmpq 4150fe <_IO_default_xsgetn+0x14e> - 4151ee: 66 90 xchg %ax,%ax - -00000000004151f0 <_IO_default_setbuf>: - 4151f0: 41 54 push %r12 - 4151f2: 55 push %rbp - 4151f3: 49 89 f4 mov %rsi,%r12 - 4151f6: 53 push %rbx - 4151f7: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax - 4151fe: 48 89 fb mov %rdi,%rbx - 415201: 48 89 d5 mov %rdx,%rbp - 415204: ff 50 60 callq *0x60(%rax) - 415207: 83 f8 ff cmp $0xffffffff,%eax - 41520a: 0f 84 a0 00 00 00 je 4152b0 <_IO_default_setbuf+0xc0> - 415210: 8b 13 mov (%rbx),%edx - 415212: 4d 85 e4 test %r12,%r12 - 415215: 89 d0 mov %edx,%eax - 415217: 74 67 je 415280 <_IO_default_setbuf+0x90> - 415219: 48 85 ed test %rbp,%rbp - 41521c: 74 62 je 415280 <_IO_default_setbuf+0x90> - 41521e: 48 8b 7b 38 mov 0x38(%rbx),%rdi - 415222: 83 e0 fd and $0xfffffffd,%eax - 415225: 4c 01 e5 add %r12,%rbp - 415228: 89 03 mov %eax,(%rbx) - 41522a: 48 85 ff test %rdi,%rdi - 41522d: 74 05 je 415234 <_IO_default_setbuf+0x44> - 41522f: 83 e2 01 and $0x1,%edx - 415232: 74 6d je 4152a1 <_IO_default_setbuf+0xb1> - 415234: 83 c8 01 or $0x1,%eax - 415237: 4c 89 63 38 mov %r12,0x38(%rbx) - 41523b: 48 89 6b 40 mov %rbp,0x40(%rbx) - 41523f: 89 03 mov %eax,(%rbx) - 415241: 48 c7 43 30 00 00 00 movq $0x0,0x30(%rbx) - 415248: 00 - 415249: 48 89 d8 mov %rbx,%rax - 41524c: 48 c7 43 28 00 00 00 movq $0x0,0x28(%rbx) - 415253: 00 - 415254: 48 c7 43 20 00 00 00 movq $0x0,0x20(%rbx) - 41525b: 00 - 41525c: 48 c7 43 10 00 00 00 movq $0x0,0x10(%rbx) - 415263: 00 - 415264: 48 c7 43 08 00 00 00 movq $0x0,0x8(%rbx) - 41526b: 00 - 41526c: 48 c7 43 18 00 00 00 movq $0x0,0x18(%rbx) - 415273: 00 - 415274: 5b pop %rbx - 415275: 5d pop %rbp - 415276: 41 5c pop %r12 - 415278: c3 retq - 415279: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 415280: 48 8b 7b 38 mov 0x38(%rbx),%rdi - 415284: 83 c8 02 or $0x2,%eax - 415287: 48 8d ab 84 00 00 00 lea 0x84(%rbx),%rbp - 41528e: 89 03 mov %eax,(%rbx) - 415290: 4c 8d a3 83 00 00 00 lea 0x83(%rbx),%r12 - 415297: 48 85 ff test %rdi,%rdi - 41529a: 74 98 je 415234 <_IO_default_setbuf+0x44> - 41529c: 83 e2 01 and $0x1,%edx - 41529f: 75 93 jne 415234 <_IO_default_setbuf+0x44> - 4152a1: e8 0a 8b 00 00 callq 41ddb0 <__cfree> - 4152a6: 8b 03 mov (%rbx),%eax - 4152a8: eb 8a jmp 415234 <_IO_default_setbuf+0x44> - 4152aa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4152b0: 31 c0 xor %eax,%eax - 4152b2: eb c0 jmp 415274 <_IO_default_setbuf+0x84> - 4152b4: 66 90 xchg %ax,%ax - 4152b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4152bd: 00 00 00 - -00000000004152c0 <_IO_default_seekpos>: - 4152c0: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax - 4152c7: 89 d1 mov %edx,%ecx - 4152c9: 31 d2 xor %edx,%edx - 4152cb: 48 8b 40 48 mov 0x48(%rax),%rax - 4152cf: ff e0 jmpq *%rax - 4152d1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4152d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4152dd: 00 00 00 - -00000000004152e0 <_IO_default_doallocate>: - 4152e0: 41 54 push %r12 - 4152e2: 55 push %rbp - 4152e3: 53 push %rbx - 4152e4: 48 89 fb mov %rdi,%rbx - 4152e7: bf 00 20 00 00 mov $0x2000,%edi - 4152ec: e8 1f 87 00 00 callq 41da10 <__libc_malloc> - 4152f1: 48 89 c5 mov %rax,%rbp - 4152f4: b8 ff ff ff ff mov $0xffffffff,%eax - 4152f9: 48 85 ed test %rbp,%rbp - 4152fc: 74 29 je 415327 <_IO_default_doallocate+0x47> - 4152fe: 48 8b 7b 38 mov 0x38(%rbx),%rdi - 415302: 4c 8d a5 00 20 00 00 lea 0x2000(%rbp),%r12 - 415309: 8b 13 mov (%rbx),%edx - 41530b: 48 85 ff test %rdi,%rdi - 41530e: 74 05 je 415315 <_IO_default_doallocate+0x35> - 415310: f6 c2 01 test $0x1,%dl - 415313: 74 1b je 415330 <_IO_default_doallocate+0x50> - 415315: 83 e2 fe and $0xfffffffe,%edx - 415318: 48 89 6b 38 mov %rbp,0x38(%rbx) - 41531c: 4c 89 63 40 mov %r12,0x40(%rbx) - 415320: 89 13 mov %edx,(%rbx) - 415322: b8 01 00 00 00 mov $0x1,%eax - 415327: 5b pop %rbx - 415328: 5d pop %rbp - 415329: 41 5c pop %r12 - 41532b: c3 retq - 41532c: 0f 1f 40 00 nopl 0x0(%rax) - 415330: e8 7b 8a 00 00 callq 41ddb0 <__cfree> - 415335: 8b 13 mov (%rbx),%edx - 415337: eb dc jmp 415315 <_IO_default_doallocate+0x35> - 415339: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - -0000000000415340 <_IO_init>: - 415340: 31 c0 xor %eax,%eax - 415342: 81 ce 00 00 ad fb or $0xfbad0000,%esi - 415348: c7 47 74 00 00 00 00 movl $0x0,0x74(%rdi) - 41534f: 66 89 87 80 00 00 00 mov %ax,0x80(%rdi) - 415356: 48 8b 87 88 00 00 00 mov 0x88(%rdi),%rax - 41535d: 89 37 mov %esi,(%rdi) - 41535f: 48 c7 47 38 00 00 00 movq $0x0,0x38(%rdi) - 415366: 00 - 415367: 48 c7 47 40 00 00 00 movq $0x0,0x40(%rdi) - 41536e: 00 - 41536f: 48 c7 47 18 00 00 00 movq $0x0,0x18(%rdi) - 415376: 00 - 415377: 48 85 c0 test %rax,%rax - 41537a: 48 c7 47 08 00 00 00 movq $0x0,0x8(%rdi) - 415381: 00 - 415382: 48 c7 47 10 00 00 00 movq $0x0,0x10(%rdi) - 415389: 00 - 41538a: 48 c7 47 20 00 00 00 movq $0x0,0x20(%rdi) - 415391: 00 - 415392: 48 c7 47 28 00 00 00 movq $0x0,0x28(%rdi) - 415399: 00 - 41539a: 48 c7 47 30 00 00 00 movq $0x0,0x30(%rdi) - 4153a1: 00 - 4153a2: 48 c7 47 68 00 00 00 movq $0x0,0x68(%rdi) - 4153a9: 00 - 4153aa: 48 c7 47 48 00 00 00 movq $0x0,0x48(%rdi) - 4153b1: 00 - 4153b2: 48 c7 47 50 00 00 00 movq $0x0,0x50(%rdi) - 4153b9: 00 - 4153ba: 48 c7 47 58 00 00 00 movq $0x0,0x58(%rdi) - 4153c1: 00 - 4153c2: 48 c7 47 60 00 00 00 movq $0x0,0x60(%rdi) - 4153c9: 00 - 4153ca: 74 15 je 4153e1 <_IO_init+0xa1> - 4153cc: c7 00 00 00 00 00 movl $0x0,(%rax) - 4153d2: c7 40 04 00 00 00 00 movl $0x0,0x4(%rax) - 4153d9: 48 c7 40 08 00 00 00 movq $0x0,0x8(%rax) - 4153e0: 00 - 4153e1: c7 87 c0 00 00 00 ff movl $0xffffffff,0xc0(%rdi) - 4153e8: ff ff ff - 4153eb: 48 c7 87 a0 00 00 00 movq $0xffffffffffffffff,0xa0(%rdi) - 4153f2: ff ff ff ff - 4153f6: 48 c7 87 a8 00 00 00 movq $0x0,0xa8(%rdi) - 4153fd: 00 00 00 00 - 415401: c3 retq - 415402: 0f 1f 40 00 nopl 0x0(%rax) - 415406: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41540d: 00 00 00 - -0000000000415410 <_IO_old_init>: - 415410: 31 c0 xor %eax,%eax - 415412: 81 ce 00 00 ad fb or $0xfbad0000,%esi - 415418: c7 47 74 00 00 00 00 movl $0x0,0x74(%rdi) - 41541f: 66 89 87 80 00 00 00 mov %ax,0x80(%rdi) - 415426: 48 8b 87 88 00 00 00 mov 0x88(%rdi),%rax - 41542d: 89 37 mov %esi,(%rdi) - 41542f: 48 c7 47 38 00 00 00 movq $0x0,0x38(%rdi) - 415436: 00 - 415437: 48 c7 47 40 00 00 00 movq $0x0,0x40(%rdi) - 41543e: 00 - 41543f: 48 c7 47 18 00 00 00 movq $0x0,0x18(%rdi) - 415446: 00 - 415447: 48 85 c0 test %rax,%rax - 41544a: 48 c7 47 08 00 00 00 movq $0x0,0x8(%rdi) - 415451: 00 - 415452: 48 c7 47 10 00 00 00 movq $0x0,0x10(%rdi) - 415459: 00 - 41545a: 48 c7 47 20 00 00 00 movq $0x0,0x20(%rdi) - 415461: 00 - 415462: 48 c7 47 28 00 00 00 movq $0x0,0x28(%rdi) - 415469: 00 - 41546a: 48 c7 47 30 00 00 00 movq $0x0,0x30(%rdi) - 415471: 00 - 415472: 48 c7 47 68 00 00 00 movq $0x0,0x68(%rdi) - 415479: 00 - 41547a: 48 c7 47 48 00 00 00 movq $0x0,0x48(%rdi) - 415481: 00 - 415482: 48 c7 47 50 00 00 00 movq $0x0,0x50(%rdi) - 415489: 00 - 41548a: 48 c7 47 58 00 00 00 movq $0x0,0x58(%rdi) - 415491: 00 - 415492: 48 c7 47 60 00 00 00 movq $0x0,0x60(%rdi) - 415499: 00 - 41549a: 74 15 je 4154b1 <_IO_old_init+0xa1> - 41549c: c7 00 00 00 00 00 movl $0x0,(%rax) - 4154a2: c7 40 04 00 00 00 00 movl $0x0,0x4(%rax) - 4154a9: 48 c7 40 08 00 00 00 movq $0x0,0x8(%rax) - 4154b0: 00 - 4154b1: f3 c3 repz retq - 4154b3: 0f 1f 00 nopl (%rax) - 4154b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4154bd: 00 00 00 - -00000000004154c0 <_IO_no_init>: - 4154c0: 31 c0 xor %eax,%eax - 4154c2: 81 ce 00 00 ad fb or $0xfbad0000,%esi - 4154c8: c7 47 74 00 00 00 00 movl $0x0,0x74(%rdi) - 4154cf: 66 89 87 80 00 00 00 mov %ax,0x80(%rdi) - 4154d6: 48 8b 87 88 00 00 00 mov 0x88(%rdi),%rax - 4154dd: 89 37 mov %esi,(%rdi) - 4154df: 48 c7 47 38 00 00 00 movq $0x0,0x38(%rdi) - 4154e6: 00 - 4154e7: 48 c7 47 40 00 00 00 movq $0x0,0x40(%rdi) - 4154ee: 00 - 4154ef: 48 c7 47 18 00 00 00 movq $0x0,0x18(%rdi) - 4154f6: 00 - 4154f7: 48 85 c0 test %rax,%rax - 4154fa: 48 c7 47 08 00 00 00 movq $0x0,0x8(%rdi) - 415501: 00 - 415502: 48 c7 47 10 00 00 00 movq $0x0,0x10(%rdi) - 415509: 00 - 41550a: 48 c7 47 20 00 00 00 movq $0x0,0x20(%rdi) - 415511: 00 - 415512: 48 c7 47 28 00 00 00 movq $0x0,0x28(%rdi) - 415519: 00 - 41551a: 48 c7 47 30 00 00 00 movq $0x0,0x30(%rdi) - 415521: 00 - 415522: 48 c7 47 68 00 00 00 movq $0x0,0x68(%rdi) - 415529: 00 - 41552a: 48 c7 47 48 00 00 00 movq $0x0,0x48(%rdi) - 415531: 00 - 415532: 48 c7 47 50 00 00 00 movq $0x0,0x50(%rdi) - 415539: 00 - 41553a: 48 c7 47 58 00 00 00 movq $0x0,0x58(%rdi) - 415541: 00 - 415542: 48 c7 47 60 00 00 00 movq $0x0,0x60(%rdi) - 415549: 00 - 41554a: 74 15 je 415561 <_IO_no_init+0xa1> - 41554c: c7 00 00 00 00 00 movl $0x0,(%rax) - 415552: c7 40 04 00 00 00 00 movl $0x0,0x4(%rax) - 415559: 48 c7 40 08 00 00 00 movq $0x0,0x8(%rax) - 415560: 00 - 415561: 85 d2 test %edx,%edx - 415563: 89 97 c0 00 00 00 mov %edx,0xc0(%rdi) - 415569: 78 75 js 4155e0 <_IO_no_init+0x120> - 41556b: 48 89 8f a0 00 00 00 mov %rcx,0xa0(%rdi) - 415572: 48 c7 41 30 00 00 00 movq $0x0,0x30(%rcx) - 415579: 00 - 41557a: 48 c7 41 38 00 00 00 movq $0x0,0x38(%rcx) - 415581: 00 - 415582: 48 c7 41 10 00 00 00 movq $0x0,0x10(%rcx) - 415589: 00 - 41558a: 48 c7 01 00 00 00 00 movq $0x0,(%rcx) - 415591: 48 c7 41 08 00 00 00 movq $0x0,0x8(%rcx) - 415598: 00 - 415599: 48 c7 41 18 00 00 00 movq $0x0,0x18(%rcx) - 4155a0: 00 - 4155a1: 48 c7 41 20 00 00 00 movq $0x0,0x20(%rcx) - 4155a8: 00 - 4155a9: 48 c7 41 28 00 00 00 movq $0x0,0x28(%rcx) - 4155b0: 00 - 4155b1: 48 c7 41 40 00 00 00 movq $0x0,0x40(%rcx) - 4155b8: 00 - 4155b9: 48 c7 41 48 00 00 00 movq $0x0,0x48(%rcx) - 4155c0: 00 - 4155c1: 48 c7 41 50 00 00 00 movq $0x0,0x50(%rcx) - 4155c8: 00 - 4155c9: 4c 89 81 30 01 00 00 mov %r8,0x130(%rcx) - 4155d0: 48 c7 87 a8 00 00 00 movq $0x0,0xa8(%rdi) - 4155d7: 00 00 00 00 - 4155db: c3 retq - 4155dc: 0f 1f 40 00 nopl 0x0(%rax) - 4155e0: 48 c7 87 a0 00 00 00 movq $0xffffffffffffffff,0xa0(%rdi) - 4155e7: ff ff ff ff - 4155eb: 48 c7 87 a8 00 00 00 movq $0x0,0xa8(%rdi) - 4155f2: 00 00 00 00 - 4155f6: c3 retq - 4155f7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 4155fe: 00 00 - -0000000000415600 <_IO_default_sync>: - 415600: 31 c0 xor %eax,%eax - 415602: c3 retq - 415603: 0f 1f 00 nopl (%rax) - 415606: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41560d: 00 00 00 - -0000000000415610 <_IO_default_finish>: - 415610: 55 push %rbp - 415611: 53 push %rbx - 415612: 48 89 fb mov %rdi,%rbx - 415615: 48 83 ec 28 sub $0x28,%rsp - 415619: 48 8b 7f 38 mov 0x38(%rdi),%rdi - 41561d: 48 85 ff test %rdi,%rdi - 415620: 74 09 je 41562b <_IO_default_finish+0x1b> - 415622: f6 03 01 testb $0x1,(%rbx) - 415625: 0f 84 fd 01 00 00 je 415828 <_IO_default_finish+0x218> - 41562b: 48 8b 43 60 mov 0x60(%rbx),%rax - 41562f: 48 85 c0 test %rax,%rax - 415632: 74 14 je 415648 <_IO_default_finish+0x38> - 415634: 0f 1f 40 00 nopl 0x0(%rax) - 415638: 48 c7 40 08 00 00 00 movq $0x0,0x8(%rax) - 41563f: 00 - 415640: 48 8b 00 mov (%rax),%rax - 415643: 48 85 c0 test %rax,%rax - 415646: 75 f0 jne 415638 <_IO_default_finish+0x28> - 415648: 48 8b 7b 48 mov 0x48(%rbx),%rdi - 41564c: 48 85 ff test %rdi,%rdi - 41564f: 74 0d je 41565e <_IO_default_finish+0x4e> - 415651: e8 5a 87 00 00 callq 41ddb0 <__cfree> - 415656: 48 c7 43 48 00 00 00 movq $0x0,0x48(%rbx) - 41565d: 00 - 41565e: f6 03 80 testb $0x80,(%rbx) - 415661: 75 0d jne 415670 <_IO_default_finish+0x60> - 415663: 48 83 c4 28 add $0x28,%rsp - 415667: 5b pop %rbx - 415668: 5d pop %rbp - 415669: c3 retq - 41566a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 415670: bd 00 00 00 00 mov $0x0,%ebp - 415675: 48 85 ed test %rbp,%rbp - 415678: 0f 84 62 02 00 00 je 4158e0 <_IO_default_finish+0x2d0> - 41567e: 31 d2 xor %edx,%edx - 415680: be 50 41 41 00 mov $0x414150,%esi - 415685: 48 89 e7 mov %rsp,%rdi - 415688: e8 73 a9 be ff callq 0 <_nl_current_LC_CTYPE> - 41568d: 64 48 8b 14 25 10 00 mov %fs:0x10,%rdx - 415694: 00 00 - 415696: 48 3b 15 0b 6f 2b 00 cmp 0x2b6f0b(%rip),%rdx # 6cc5a8 - 41569d: 74 46 je 4156e5 <_IO_default_finish+0xd5> - 41569f: be 01 00 00 00 mov $0x1,%esi - 4156a4: 31 c0 xor %eax,%eax - 4156a6: 83 3d 0f 7b 2b 00 00 cmpl $0x0,0x2b7b0f(%rip) # 6cd1bc <__libc_multiple_threads> - 4156ad: 74 0c je 4156bb <_IO_default_finish+0xab> - 4156af: f0 0f b1 35 e9 6e 2b lock cmpxchg %esi,0x2b6ee9(%rip) # 6cc5a0 - 4156b6: 00 - 4156b7: 75 0b jne 4156c4 <_IO_default_finish+0xb4> - 4156b9: eb 23 jmp 4156de <_IO_default_finish+0xce> - 4156bb: 0f b1 35 de 6e 2b 00 cmpxchg %esi,0x2b6ede(%rip) # 6cc5a0 - 4156c2: 74 1a je 4156de <_IO_default_finish+0xce> - 4156c4: 48 8d 3d d5 6e 2b 00 lea 0x2b6ed5(%rip),%rdi # 6cc5a0 - 4156cb: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 4156d2: e8 f9 ce 02 00 callq 4425d0 <__lll_lock_wait_private> - 4156d7: 48 81 c4 80 00 00 00 add $0x80,%rsp - 4156de: 48 89 15 c3 6e 2b 00 mov %rdx,0x2b6ec3(%rip) # 6cc5a8 - 4156e5: 8b 33 mov (%rbx),%esi - 4156e7: 8b 15 b7 6e 2b 00 mov 0x2b6eb7(%rip),%edx # 6cc5a4 - 4156ed: 48 89 1d 9c 6e 2b 00 mov %rbx,0x2b6e9c(%rip) # 6cc590 - 4156f4: 89 f0 mov %esi,%eax - 4156f6: 83 c2 01 add $0x1,%edx - 4156f9: 25 00 80 00 00 and $0x8000,%eax - 4156fe: 89 15 a0 6e 2b 00 mov %edx,0x2b6ea0(%rip) # 6cc5a4 - 415704: 0f 84 3e 01 00 00 je 415848 <_IO_default_finish+0x238> - 41570a: 48 8b 3d af 49 2b 00 mov 0x2b49af(%rip),%rdi # 6ca0c0 <_IO_list_all> - 415711: 48 85 ff test %rdi,%rdi - 415714: 0f 84 f3 01 00 00 je 41590d <_IO_default_finish+0x2fd> - 41571a: 48 39 fb cmp %rdi,%rbx - 41571d: 0f 84 d3 01 00 00 je 4158f6 <_IO_default_finish+0x2e6> - 415723: 48 8b 4f 68 mov 0x68(%rdi),%rcx - 415727: 48 85 c9 test %rcx,%rcx - 41572a: 74 29 je 415755 <_IO_default_finish+0x145> - 41572c: 48 39 cb cmp %rcx,%rbx - 41572f: 75 1b jne 41574c <_IO_default_finish+0x13c> - 415731: e9 e2 01 00 00 jmpq 415918 <_IO_default_finish+0x308> - 415736: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41573d: 00 00 00 - 415740: 48 39 d3 cmp %rdx,%rbx - 415743: 0f 84 77 01 00 00 je 4158c0 <_IO_default_finish+0x2b0> - 415749: 48 89 d1 mov %rdx,%rcx - 41574c: 48 8b 51 68 mov 0x68(%rcx),%rdx - 415750: 48 85 d2 test %rdx,%rdx - 415753: 75 eb jne 415740 <_IO_default_finish+0x130> - 415755: 40 80 e6 7f and $0x7f,%sil - 415759: 85 c0 test %eax,%eax - 41575b: 89 33 mov %esi,(%rbx) - 41575d: 75 4c jne 4157ab <_IO_default_finish+0x19b> - 41575f: 48 8b b3 88 00 00 00 mov 0x88(%rbx),%rsi - 415766: 8b 46 04 mov 0x4(%rsi),%eax - 415769: 83 e8 01 sub $0x1,%eax - 41576c: 85 c0 test %eax,%eax - 41576e: 89 46 04 mov %eax,0x4(%rsi) - 415771: 8b 15 2d 6e 2b 00 mov 0x2b6e2d(%rip),%edx # 6cc5a4 - 415777: 75 38 jne 4157b1 <_IO_default_finish+0x1a1> - 415779: 48 c7 46 08 00 00 00 movq $0x0,0x8(%rsi) - 415780: 00 - 415781: 83 3d 34 7a 2b 00 00 cmpl $0x0,0x2b7a34(%rip) # 6cd1bc <__libc_multiple_threads> - 415788: 74 07 je 415791 <_IO_default_finish+0x181> - 41578a: f0 ff 0e lock decl (%rsi) - 41578d: 75 06 jne 415795 <_IO_default_finish+0x185> - 41578f: eb 1a jmp 4157ab <_IO_default_finish+0x19b> - 415791: ff 0e decl (%rsi) - 415793: 74 16 je 4157ab <_IO_default_finish+0x19b> - 415795: 48 8d 3e lea (%rsi),%rdi - 415798: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41579f: e8 5c ce 02 00 callq 442600 <__lll_unlock_wake_private> - 4157a4: 48 81 c4 80 00 00 00 add $0x80,%rsp - 4157ab: 8b 15 f3 6d 2b 00 mov 0x2b6df3(%rip),%edx # 6cc5a4 - 4157b1: 83 ea 01 sub $0x1,%edx - 4157b4: 48 c7 05 d1 6d 2b 00 movq $0x0,0x2b6dd1(%rip) # 6cc590 - 4157bb: 00 00 00 00 - 4157bf: 85 d2 test %edx,%edx - 4157c1: 89 15 dd 6d 2b 00 mov %edx,0x2b6ddd(%rip) # 6cc5a4 - 4157c7: 75 41 jne 41580a <_IO_default_finish+0x1fa> - 4157c9: 48 c7 05 d4 6d 2b 00 movq $0x0,0x2b6dd4(%rip) # 6cc5a8 - 4157d0: 00 00 00 00 - 4157d4: 83 3d e1 79 2b 00 00 cmpl $0x0,0x2b79e1(%rip) # 6cd1bc <__libc_multiple_threads> - 4157db: 74 0b je 4157e8 <_IO_default_finish+0x1d8> - 4157dd: f0 ff 0d bc 6d 2b 00 lock decl 0x2b6dbc(%rip) # 6cc5a0 - 4157e4: 75 0a jne 4157f0 <_IO_default_finish+0x1e0> - 4157e6: eb 22 jmp 41580a <_IO_default_finish+0x1fa> - 4157e8: ff 0d b2 6d 2b 00 decl 0x2b6db2(%rip) # 6cc5a0 - 4157ee: 74 1a je 41580a <_IO_default_finish+0x1fa> - 4157f0: 48 8d 3d a9 6d 2b 00 lea 0x2b6da9(%rip),%rdi # 6cc5a0 - 4157f7: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 4157fe: e8 fd cd 02 00 callq 442600 <__lll_unlock_wake_private> - 415803: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41580a: 48 85 ed test %rbp,%rbp - 41580d: 0f 84 50 fe ff ff je 415663 <_IO_default_finish+0x53> - 415813: 48 89 e7 mov %rsp,%rdi - 415816: 31 f6 xor %esi,%esi - 415818: e8 e3 a7 be ff callq 0 <_nl_current_LC_CTYPE> - 41581d: 48 83 c4 28 add $0x28,%rsp - 415821: 5b pop %rbx - 415822: 5d pop %rbp - 415823: c3 retq - 415824: 0f 1f 40 00 nopl 0x0(%rax) - 415828: e8 83 85 00 00 callq 41ddb0 <__cfree> - 41582d: 48 c7 43 40 00 00 00 movq $0x0,0x40(%rbx) - 415834: 00 - 415835: 48 c7 43 38 00 00 00 movq $0x0,0x38(%rbx) - 41583c: 00 - 41583d: e9 e9 fd ff ff jmpq 41562b <_IO_default_finish+0x1b> - 415842: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 415848: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx - 41584f: 64 4c 8b 04 25 10 00 mov %fs:0x10,%r8 - 415856: 00 00 - 415858: 4c 3b 42 08 cmp 0x8(%rdx),%r8 - 41585c: 74 3c je 41589a <_IO_default_finish+0x28a> - 41585e: be 01 00 00 00 mov $0x1,%esi - 415863: 83 3d 52 79 2b 00 00 cmpl $0x0,0x2b7952(%rip) # 6cd1bc <__libc_multiple_threads> - 41586a: 74 08 je 415874 <_IO_default_finish+0x264> - 41586c: f0 0f b1 32 lock cmpxchg %esi,(%rdx) - 415870: 75 07 jne 415879 <_IO_default_finish+0x269> - 415872: eb 1b jmp 41588f <_IO_default_finish+0x27f> - 415874: 0f b1 32 cmpxchg %esi,(%rdx) - 415877: 74 16 je 41588f <_IO_default_finish+0x27f> - 415879: 48 8d 3a lea (%rdx),%rdi - 41587c: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 415883: e8 48 cd 02 00 callq 4425d0 <__lll_lock_wait_private> - 415888: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41588f: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx - 415896: 4c 89 42 08 mov %r8,0x8(%rdx) - 41589a: 8b 33 mov (%rbx),%esi - 41589c: 48 8b 3d 1d 48 2b 00 mov 0x2b481d(%rip),%rdi # 6ca0c0 <_IO_list_all> - 4158a3: 83 42 04 01 addl $0x1,0x4(%rdx) - 4158a7: 89 f0 mov %esi,%eax - 4158a9: 25 00 80 00 00 and $0x8000,%eax - 4158ae: 48 85 ff test %rdi,%rdi - 4158b1: 0f 85 63 fe ff ff jne 41571a <_IO_default_finish+0x10a> - 4158b7: e9 99 fe ff ff jmpq 415755 <_IO_default_finish+0x145> - 4158bc: 0f 1f 40 00 nopl 0x0(%rax) - 4158c0: 48 83 c1 68 add $0x68,%rcx - 4158c4: 48 8b 53 68 mov 0x68(%rbx),%rdx - 4158c8: 83 05 c9 6c 2b 00 01 addl $0x1,0x2b6cc9(%rip) # 6cc598 <_IO_list_all_stamp> - 4158cf: 48 89 11 mov %rdx,(%rcx) - 4158d2: e9 7e fe ff ff jmpq 415755 <_IO_default_finish+0x145> - 4158d7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 4158de: 00 00 - 4158e0: 48 c7 04 24 50 41 41 movq $0x414150,(%rsp) - 4158e7: 00 - 4158e8: 48 c7 44 24 08 00 00 movq $0x0,0x8(%rsp) - 4158ef: 00 00 - 4158f1: e9 97 fd ff ff jmpq 41568d <_IO_default_finish+0x7d> - 4158f6: 48 8b 53 68 mov 0x68(%rbx),%rdx - 4158fa: 83 05 97 6c 2b 00 01 addl $0x1,0x2b6c97(%rip) # 6cc598 <_IO_list_all_stamp> - 415901: 48 89 15 b8 47 2b 00 mov %rdx,0x2b47b8(%rip) # 6ca0c0 <_IO_list_all> - 415908: e9 48 fe ff ff jmpq 415755 <_IO_default_finish+0x145> - 41590d: 40 80 e6 7f and $0x7f,%sil - 415911: 89 33 mov %esi,(%rbx) - 415913: e9 99 fe ff ff jmpq 4157b1 <_IO_default_finish+0x1a1> - 415918: 48 8d 4f 68 lea 0x68(%rdi),%rcx - 41591c: eb a6 jmp 4158c4 <_IO_default_finish+0x2b4> - 41591e: 66 90 xchg %ax,%ax - -0000000000415920 <_IO_default_seekoff>: - 415920: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax - 415927: c3 retq - 415928: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 41592f: 00 - -0000000000415930 <_IO_sputbackc>: - 415930: 53 push %rbx - 415931: 48 8b 57 08 mov 0x8(%rdi),%rdx - 415935: 48 89 fb mov %rdi,%rbx - 415938: 48 3b 57 18 cmp 0x18(%rdi),%rdx - 41593c: 76 0c jbe 41594a <_IO_sputbackc+0x1a> - 41593e: 0f b6 42 ff movzbl -0x1(%rdx),%eax - 415942: 40 0f b6 ce movzbl %sil,%ecx - 415946: 39 c8 cmp %ecx,%eax - 415948: 74 1e je 415968 <_IO_sputbackc+0x38> - 41594a: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 415951: 48 89 df mov %rbx,%rdi - 415954: ff 50 30 callq *0x30(%rax) - 415957: 83 f8 ff cmp $0xffffffff,%eax - 41595a: 74 03 je 41595f <_IO_sputbackc+0x2f> - 41595c: 83 23 ef andl $0xffffffef,(%rbx) - 41595f: 5b pop %rbx - 415960: c3 retq - 415961: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 415968: 48 83 ea 01 sub $0x1,%rdx - 41596c: 48 89 57 08 mov %rdx,0x8(%rdi) - 415970: eb ea jmp 41595c <_IO_sputbackc+0x2c> - 415972: 0f 1f 40 00 nopl 0x0(%rax) - 415976: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41597d: 00 00 00 - -0000000000415980 <_IO_sungetc>: - 415980: 48 8b 47 08 mov 0x8(%rdi),%rax - 415984: 48 3b 47 18 cmp 0x18(%rdi),%rax - 415988: 53 push %rbx - 415989: 48 89 fb mov %rdi,%rbx - 41598c: 76 12 jbe 4159a0 <_IO_sungetc+0x20> - 41598e: 48 8d 50 ff lea -0x1(%rax),%rdx - 415992: 48 89 57 08 mov %rdx,0x8(%rdi) - 415996: 0f b6 40 ff movzbl -0x1(%rax),%eax - 41599a: 83 23 ef andl $0xffffffef,(%rbx) - 41599d: 5b pop %rbx - 41599e: c3 retq - 41599f: 90 nop - 4159a0: 48 8b 87 d8 00 00 00 mov 0xd8(%rdi),%rax - 4159a7: be ff ff ff ff mov $0xffffffff,%esi - 4159ac: ff 50 30 callq *0x30(%rax) - 4159af: 83 f8 ff cmp $0xffffffff,%eax - 4159b2: 75 e6 jne 41599a <_IO_sungetc+0x1a> - 4159b4: 5b pop %rbx - 4159b5: c3 retq - 4159b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4159bd: 00 00 00 - -00000000004159c0 <_IO_adjust_column>: - 4159c0: 4c 63 c2 movslq %edx,%r8 - 4159c3: 49 01 f0 add %rsi,%r8 - 4159c6: 4c 39 c6 cmp %r8,%rsi - 4159c9: 73 23 jae 4159ee <_IO_adjust_column+0x2e> - 4159cb: 41 80 78 ff 0a cmpb $0xa,-0x1(%r8) - 4159d0: 49 8d 48 ff lea -0x1(%r8),%rcx - 4159d4: 75 13 jne 4159e9 <_IO_adjust_column+0x29> - 4159d6: eb 20 jmp 4159f8 <_IO_adjust_column+0x38> - 4159d8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 4159df: 00 - 4159e0: 48 83 e9 01 sub $0x1,%rcx - 4159e4: 80 39 0a cmpb $0xa,(%rcx) - 4159e7: 74 0f je 4159f8 <_IO_adjust_column+0x38> - 4159e9: 48 39 ce cmp %rcx,%rsi - 4159ec: 75 f2 jne 4159e0 <_IO_adjust_column+0x20> - 4159ee: 8d 04 3a lea (%rdx,%rdi,1),%eax - 4159f1: c3 retq - 4159f2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4159f8: 49 29 c8 sub %rcx,%r8 - 4159fb: 41 8d 40 ff lea -0x1(%r8),%eax - 4159ff: c3 retq - -0000000000415a00 <_IO_flush_all_lockp>: - 415a00: 41 57 push %r15 - 415a02: 41 56 push %r14 - 415a04: 41 89 fe mov %edi,%r14d - 415a07: 41 55 push %r13 - 415a09: 41 54 push %r12 - 415a0b: 55 push %rbp - 415a0c: 53 push %rbx - 415a0d: 48 83 ec 28 sub $0x28,%rsp - 415a11: 85 ff test %edi,%edi - 415a13: 0f 84 17 02 00 00 je 415c30 <_IO_flush_all_lockp+0x230> - 415a19: b8 00 00 00 00 mov $0x0,%eax - 415a1e: 45 31 ed xor %r13d,%r13d - 415a21: 48 85 c0 test %rax,%rax - 415a24: 41 0f 95 c5 setne %r13b - 415a28: 0f 84 82 02 00 00 je 415cb0 <_IO_flush_all_lockp+0x2b0> - 415a2e: 31 d2 xor %edx,%edx - 415a30: be 50 41 41 00 mov $0x414150,%esi - 415a35: 48 89 e7 mov %rsp,%rdi - 415a38: e8 c3 a5 be ff callq 0 <_nl_current_LC_CTYPE> - 415a3d: 64 48 8b 14 25 10 00 mov %fs:0x10,%rdx - 415a44: 00 00 - 415a46: 48 3b 15 5b 6b 2b 00 cmp 0x2b6b5b(%rip),%rdx # 6cc5a8 - 415a4d: 74 46 je 415a95 <_IO_flush_all_lockp+0x95> - 415a4f: be 01 00 00 00 mov $0x1,%esi - 415a54: 31 c0 xor %eax,%eax - 415a56: 83 3d 5f 77 2b 00 00 cmpl $0x0,0x2b775f(%rip) # 6cd1bc <__libc_multiple_threads> - 415a5d: 74 0c je 415a6b <_IO_flush_all_lockp+0x6b> - 415a5f: f0 0f b1 35 39 6b 2b lock cmpxchg %esi,0x2b6b39(%rip) # 6cc5a0 - 415a66: 00 - 415a67: 75 0b jne 415a74 <_IO_flush_all_lockp+0x74> - 415a69: eb 23 jmp 415a8e <_IO_flush_all_lockp+0x8e> - 415a6b: 0f b1 35 2e 6b 2b 00 cmpxchg %esi,0x2b6b2e(%rip) # 6cc5a0 - 415a72: 74 1a je 415a8e <_IO_flush_all_lockp+0x8e> - 415a74: 48 8d 3d 25 6b 2b 00 lea 0x2b6b25(%rip),%rdi # 6cc5a0 - 415a7b: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 415a82: e8 49 cb 02 00 callq 4425d0 <__lll_lock_wait_private> - 415a87: 48 81 c4 80 00 00 00 add $0x80,%rsp - 415a8e: 48 89 15 13 6b 2b 00 mov %rdx,0x2b6b13(%rip) # 6cc5a8 - 415a95: 8b 05 09 6b 2b 00 mov 0x2b6b09(%rip),%eax # 6cc5a4 - 415a9b: 48 8b 1d 1e 46 2b 00 mov 0x2b461e(%rip),%rbx # 6ca0c0 <_IO_list_all> - 415aa2: 44 8b 3d ef 6a 2b 00 mov 0x2b6aef(%rip),%r15d # 6cc598 <_IO_list_all_stamp> - 415aa9: 83 c0 01 add $0x1,%eax - 415aac: 48 85 db test %rbx,%rbx - 415aaf: 89 05 ef 6a 2b 00 mov %eax,0x2b6aef(%rip) # 6cc5a4 - 415ab5: 0f 84 0b 02 00 00 je 415cc6 <_IO_flush_all_lockp+0x2c6> - 415abb: 31 ed xor %ebp,%ebp - 415abd: 64 4c 8b 24 25 10 00 mov %fs:0x10,%r12 - 415ac4: 00 00 - 415ac6: eb 1b jmp 415ae3 <_IO_flush_all_lockp+0xe3> - 415ac8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 415acf: 00 - 415ad0: 48 8b 1d e9 45 2b 00 mov 0x2b45e9(%rip),%rbx # 6ca0c0 <_IO_list_all> - 415ad7: 41 89 c7 mov %eax,%r15d - 415ada: 48 85 db test %rbx,%rbx - 415add: 0f 84 14 01 00 00 je 415bf7 <_IO_flush_all_lockp+0x1f7> - 415ae3: 45 85 f6 test %r14d,%r14d - 415ae6: 48 89 1d a3 6a 2b 00 mov %rbx,0x2b6aa3(%rip) # 6cc590 - 415aed: 74 56 je 415b45 <_IO_flush_all_lockp+0x145> - 415aef: 8b 03 mov (%rbx),%eax - 415af1: 25 00 80 00 00 and $0x8000,%eax - 415af6: 75 4d jne 415b45 <_IO_flush_all_lockp+0x145> - 415af8: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx - 415aff: 4c 3b 62 08 cmp 0x8(%rdx),%r12 - 415b03: 74 3c je 415b41 <_IO_flush_all_lockp+0x141> - 415b05: be 01 00 00 00 mov $0x1,%esi - 415b0a: 83 3d ab 76 2b 00 00 cmpl $0x0,0x2b76ab(%rip) # 6cd1bc <__libc_multiple_threads> - 415b11: 74 08 je 415b1b <_IO_flush_all_lockp+0x11b> - 415b13: f0 0f b1 32 lock cmpxchg %esi,(%rdx) - 415b17: 75 07 jne 415b20 <_IO_flush_all_lockp+0x120> - 415b19: eb 1b jmp 415b36 <_IO_flush_all_lockp+0x136> - 415b1b: 0f b1 32 cmpxchg %esi,(%rdx) - 415b1e: 74 16 je 415b36 <_IO_flush_all_lockp+0x136> - 415b20: 48 8d 3a lea (%rdx),%rdi - 415b23: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 415b2a: e8 a1 ca 02 00 callq 4425d0 <__lll_lock_wait_private> - 415b2f: 48 81 c4 80 00 00 00 add $0x80,%rsp - 415b36: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx - 415b3d: 4c 89 62 08 mov %r12,0x8(%rdx) - 415b41: 83 42 04 01 addl $0x1,0x4(%rdx) - 415b45: 8b 83 c0 00 00 00 mov 0xc0(%rbx),%eax - 415b4b: 85 c0 test %eax,%eax - 415b4d: 0f 8e fd 00 00 00 jle 415c50 <_IO_flush_all_lockp+0x250> - 415b53: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 415b5a: 48 8b 48 18 mov 0x18(%rax),%rcx - 415b5e: 48 39 48 20 cmp %rcx,0x20(%rax) - 415b62: 76 1d jbe 415b81 <_IO_flush_all_lockp+0x181> - 415b64: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 415b6b: be ff ff ff ff mov $0xffffffff,%esi - 415b70: 48 89 df mov %rbx,%rdi - 415b73: ff 50 18 callq *0x18(%rax) - 415b76: 83 f8 ff cmp $0xffffffff,%eax - 415b79: b8 ff ff ff ff mov $0xffffffff,%eax - 415b7e: 0f 44 e8 cmove %eax,%ebp - 415b81: 45 85 f6 test %r14d,%r14d - 415b84: 74 4a je 415bd0 <_IO_flush_all_lockp+0x1d0> - 415b86: f7 03 00 80 00 00 testl $0x8000,(%rbx) - 415b8c: 75 42 jne 415bd0 <_IO_flush_all_lockp+0x1d0> - 415b8e: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx - 415b95: 83 6a 04 01 subl $0x1,0x4(%rdx) - 415b99: 75 35 jne 415bd0 <_IO_flush_all_lockp+0x1d0> - 415b9b: 48 c7 42 08 00 00 00 movq $0x0,0x8(%rdx) - 415ba2: 00 - 415ba3: 83 3d 12 76 2b 00 00 cmpl $0x0,0x2b7612(%rip) # 6cd1bc <__libc_multiple_threads> - 415baa: 74 07 je 415bb3 <_IO_flush_all_lockp+0x1b3> - 415bac: f0 ff 0a lock decl (%rdx) - 415baf: 75 06 jne 415bb7 <_IO_flush_all_lockp+0x1b7> - 415bb1: eb 1a jmp 415bcd <_IO_flush_all_lockp+0x1cd> - 415bb3: ff 0a decl (%rdx) - 415bb5: 74 16 je 415bcd <_IO_flush_all_lockp+0x1cd> - 415bb7: 48 8d 3a lea (%rdx),%rdi - 415bba: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 415bc1: e8 3a ca 02 00 callq 442600 <__lll_unlock_wake_private> - 415bc6: 48 81 c4 80 00 00 00 add $0x80,%rsp - 415bcd: 0f 1f 00 nopl (%rax) - 415bd0: 8b 05 c2 69 2b 00 mov 0x2b69c2(%rip),%eax # 6cc598 <_IO_list_all_stamp> - 415bd6: 48 c7 05 af 69 2b 00 movq $0x0,0x2b69af(%rip) # 6cc590 - 415bdd: 00 00 00 00 - 415be1: 41 39 c7 cmp %eax,%r15d - 415be4: 0f 85 e6 fe ff ff jne 415ad0 <_IO_flush_all_lockp+0xd0> - 415bea: 48 8b 5b 68 mov 0x68(%rbx),%rbx - 415bee: 48 85 db test %rbx,%rbx - 415bf1: 0f 85 ec fe ff ff jne 415ae3 <_IO_flush_all_lockp+0xe3> - 415bf7: 45 85 f6 test %r14d,%r14d - 415bfa: 8b 05 a4 69 2b 00 mov 0x2b69a4(%rip),%eax # 6cc5a4 - 415c00: 74 0d je 415c0f <_IO_flush_all_lockp+0x20f> - 415c02: 83 e8 01 sub $0x1,%eax - 415c05: 85 c0 test %eax,%eax - 415c07: 89 05 97 69 2b 00 mov %eax,0x2b6997(%rip) # 6cc5a4 - 415c0d: 74 59 je 415c68 <_IO_flush_all_lockp+0x268> - 415c0f: 45 85 ed test %r13d,%r13d - 415c12: 74 0a je 415c1e <_IO_flush_all_lockp+0x21e> - 415c14: 31 f6 xor %esi,%esi - 415c16: 48 89 e7 mov %rsp,%rdi - 415c19: e8 e2 a3 be ff callq 0 <_nl_current_LC_CTYPE> - 415c1e: 48 83 c4 28 add $0x28,%rsp - 415c22: 89 e8 mov %ebp,%eax - 415c24: 5b pop %rbx - 415c25: 5d pop %rbp - 415c26: 41 5c pop %r12 - 415c28: 41 5d pop %r13 - 415c2a: 41 5e pop %r14 - 415c2c: 41 5f pop %r15 - 415c2e: c3 retq - 415c2f: 90 nop - 415c30: 48 8b 1d 89 44 2b 00 mov 0x2b4489(%rip),%rbx # 6ca0c0 <_IO_list_all> - 415c37: 45 31 ed xor %r13d,%r13d - 415c3a: 44 8b 3d 57 69 2b 00 mov 0x2b6957(%rip),%r15d # 6cc598 <_IO_list_all_stamp> - 415c41: 48 85 db test %rbx,%rbx - 415c44: 0f 85 71 fe ff ff jne 415abb <_IO_flush_all_lockp+0xbb> - 415c4a: 31 ed xor %ebp,%ebp - 415c4c: eb d0 jmp 415c1e <_IO_flush_all_lockp+0x21e> - 415c4e: 66 90 xchg %ax,%ax - 415c50: 48 8b 43 20 mov 0x20(%rbx),%rax - 415c54: 48 39 43 28 cmp %rax,0x28(%rbx) - 415c58: 0f 87 06 ff ff ff ja 415b64 <_IO_flush_all_lockp+0x164> - 415c5e: e9 1e ff ff ff jmpq 415b81 <_IO_flush_all_lockp+0x181> - 415c63: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 415c68: 48 c7 05 35 69 2b 00 movq $0x0,0x2b6935(%rip) # 6cc5a8 - 415c6f: 00 00 00 00 - 415c73: 83 3d 42 75 2b 00 00 cmpl $0x0,0x2b7542(%rip) # 6cd1bc <__libc_multiple_threads> - 415c7a: 74 0b je 415c87 <_IO_flush_all_lockp+0x287> - 415c7c: f0 ff 0d 1d 69 2b 00 lock decl 0x2b691d(%rip) # 6cc5a0 - 415c83: 75 0a jne 415c8f <_IO_flush_all_lockp+0x28f> - 415c85: eb 22 jmp 415ca9 <_IO_flush_all_lockp+0x2a9> - 415c87: ff 0d 13 69 2b 00 decl 0x2b6913(%rip) # 6cc5a0 - 415c8d: 74 1a je 415ca9 <_IO_flush_all_lockp+0x2a9> - 415c8f: 48 8d 3d 0a 69 2b 00 lea 0x2b690a(%rip),%rdi # 6cc5a0 - 415c96: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 415c9d: e8 5e c9 02 00 callq 442600 <__lll_unlock_wake_private> - 415ca2: 48 81 c4 80 00 00 00 add $0x80,%rsp - 415ca9: e9 61 ff ff ff jmpq 415c0f <_IO_flush_all_lockp+0x20f> - 415cae: 66 90 xchg %ax,%ax - 415cb0: 48 c7 04 24 50 41 41 movq $0x414150,(%rsp) - 415cb7: 00 - 415cb8: 48 c7 44 24 08 00 00 movq $0x0,0x8(%rsp) - 415cbf: 00 00 - 415cc1: e9 77 fd ff ff jmpq 415a3d <_IO_flush_all_lockp+0x3d> - 415cc6: 31 ed xor %ebp,%ebp - 415cc8: e9 35 ff ff ff jmpq 415c02 <_IO_flush_all_lockp+0x202> - 415ccd: 0f 1f 00 nopl (%rax) - -0000000000415cd0 <_IO_flush_all>: - 415cd0: 41 56 push %r14 - 415cd2: 41 55 push %r13 - 415cd4: 41 54 push %r12 - 415cd6: 55 push %rbp - 415cd7: 41 bc 00 00 00 00 mov $0x0,%r12d - 415cdd: 53 push %rbx - 415cde: 48 83 ec 20 sub $0x20,%rsp - 415ce2: 4d 85 e4 test %r12,%r12 - 415ce5: 0f 84 45 02 00 00 je 415f30 <_IO_flush_all+0x260> - 415ceb: 31 d2 xor %edx,%edx - 415ced: be 50 41 41 00 mov $0x414150,%esi - 415cf2: 48 89 e7 mov %rsp,%rdi - 415cf5: e8 06 a3 be ff callq 0 <_nl_current_LC_CTYPE> - 415cfa: 64 48 8b 14 25 10 00 mov %fs:0x10,%rdx - 415d01: 00 00 - 415d03: 48 3b 15 9e 68 2b 00 cmp 0x2b689e(%rip),%rdx # 6cc5a8 - 415d0a: 74 46 je 415d52 <_IO_flush_all+0x82> - 415d0c: be 01 00 00 00 mov $0x1,%esi - 415d11: 31 c0 xor %eax,%eax - 415d13: 83 3d a2 74 2b 00 00 cmpl $0x0,0x2b74a2(%rip) # 6cd1bc <__libc_multiple_threads> - 415d1a: 74 0c je 415d28 <_IO_flush_all+0x58> - 415d1c: f0 0f b1 35 7c 68 2b lock cmpxchg %esi,0x2b687c(%rip) # 6cc5a0 - 415d23: 00 - 415d24: 75 0b jne 415d31 <_IO_flush_all+0x61> - 415d26: eb 23 jmp 415d4b <_IO_flush_all+0x7b> - 415d28: 0f b1 35 71 68 2b 00 cmpxchg %esi,0x2b6871(%rip) # 6cc5a0 - 415d2f: 74 1a je 415d4b <_IO_flush_all+0x7b> - 415d31: 48 8d 3d 68 68 2b 00 lea 0x2b6868(%rip),%rdi # 6cc5a0 - 415d38: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 415d3f: e8 8c c8 02 00 callq 4425d0 <__lll_lock_wait_private> - 415d44: 48 81 c4 80 00 00 00 add $0x80,%rsp - 415d4b: 48 89 15 56 68 2b 00 mov %rdx,0x2b6856(%rip) # 6cc5a8 - 415d52: 8b 05 4c 68 2b 00 mov 0x2b684c(%rip),%eax # 6cc5a4 - 415d58: 48 8b 1d 61 43 2b 00 mov 0x2b4361(%rip),%rbx # 6ca0c0 <_IO_list_all> - 415d5f: 31 ed xor %ebp,%ebp - 415d61: 44 8b 2d 30 68 2b 00 mov 0x2b6830(%rip),%r13d # 6cc598 <_IO_list_all_stamp> - 415d68: 83 c0 01 add $0x1,%eax - 415d6b: 48 85 db test %rbx,%rbx - 415d6e: 89 05 30 68 2b 00 mov %eax,0x2b6830(%rip) # 6cc5a4 - 415d74: 0f 84 2e 01 00 00 je 415ea8 <_IO_flush_all+0x1d8> - 415d7a: 64 4c 8b 34 25 10 00 mov %fs:0x10,%r14 - 415d81: 00 00 - 415d83: eb 16 jmp 415d9b <_IO_flush_all+0xcb> - 415d85: 0f 1f 00 nopl (%rax) - 415d88: 48 8b 1d 31 43 2b 00 mov 0x2b4331(%rip),%rbx # 6ca0c0 <_IO_list_all> - 415d8f: 48 85 db test %rbx,%rbx - 415d92: 0f 84 0a 01 00 00 je 415ea2 <_IO_flush_all+0x1d2> - 415d98: 41 89 c5 mov %eax,%r13d - 415d9b: 8b 03 mov (%rbx),%eax - 415d9d: 48 89 1d ec 67 2b 00 mov %rbx,0x2b67ec(%rip) # 6cc590 - 415da4: 25 00 80 00 00 and $0x8000,%eax - 415da9: 75 4d jne 415df8 <_IO_flush_all+0x128> - 415dab: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx - 415db2: 4c 3b 72 08 cmp 0x8(%rdx),%r14 - 415db6: 74 3c je 415df4 <_IO_flush_all+0x124> - 415db8: be 01 00 00 00 mov $0x1,%esi - 415dbd: 83 3d f8 73 2b 00 00 cmpl $0x0,0x2b73f8(%rip) # 6cd1bc <__libc_multiple_threads> - 415dc4: 74 08 je 415dce <_IO_flush_all+0xfe> - 415dc6: f0 0f b1 32 lock cmpxchg %esi,(%rdx) - 415dca: 75 07 jne 415dd3 <_IO_flush_all+0x103> - 415dcc: eb 1b jmp 415de9 <_IO_flush_all+0x119> - 415dce: 0f b1 32 cmpxchg %esi,(%rdx) - 415dd1: 74 16 je 415de9 <_IO_flush_all+0x119> - 415dd3: 48 8d 3a lea (%rdx),%rdi - 415dd6: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 415ddd: e8 ee c7 02 00 callq 4425d0 <__lll_lock_wait_private> - 415de2: 48 81 c4 80 00 00 00 add $0x80,%rsp - 415de9: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx - 415df0: 4c 89 72 08 mov %r14,0x8(%rdx) - 415df4: 83 42 04 01 addl $0x1,0x4(%rdx) - 415df8: 8b 83 c0 00 00 00 mov 0xc0(%rbx),%eax - 415dfe: 85 c0 test %eax,%eax - 415e00: 0f 8e 12 01 00 00 jle 415f18 <_IO_flush_all+0x248> - 415e06: 48 8b 83 a0 00 00 00 mov 0xa0(%rbx),%rax - 415e0d: 48 8b 48 18 mov 0x18(%rax),%rcx - 415e11: 48 39 48 20 cmp %rcx,0x20(%rax) - 415e15: 76 1d jbe 415e34 <_IO_flush_all+0x164> - 415e17: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 415e1e: be ff ff ff ff mov $0xffffffff,%esi - 415e23: 48 89 df mov %rbx,%rdi - 415e26: ff 50 18 callq *0x18(%rax) - 415e29: 83 f8 ff cmp $0xffffffff,%eax - 415e2c: b8 ff ff ff ff mov $0xffffffff,%eax - 415e31: 0f 44 e8 cmove %eax,%ebp - 415e34: f7 03 00 80 00 00 testl $0x8000,(%rbx) - 415e3a: 75 3f jne 415e7b <_IO_flush_all+0x1ab> - 415e3c: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx - 415e43: 83 6a 04 01 subl $0x1,0x4(%rdx) - 415e47: 75 32 jne 415e7b <_IO_flush_all+0x1ab> - 415e49: 48 c7 42 08 00 00 00 movq $0x0,0x8(%rdx) - 415e50: 00 - 415e51: 83 3d 64 73 2b 00 00 cmpl $0x0,0x2b7364(%rip) # 6cd1bc <__libc_multiple_threads> - 415e58: 74 07 je 415e61 <_IO_flush_all+0x191> - 415e5a: f0 ff 0a lock decl (%rdx) - 415e5d: 75 06 jne 415e65 <_IO_flush_all+0x195> - 415e5f: eb 1a jmp 415e7b <_IO_flush_all+0x1ab> - 415e61: ff 0a decl (%rdx) - 415e63: 74 16 je 415e7b <_IO_flush_all+0x1ab> - 415e65: 48 8d 3a lea (%rdx),%rdi - 415e68: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 415e6f: e8 8c c7 02 00 callq 442600 <__lll_unlock_wake_private> - 415e74: 48 81 c4 80 00 00 00 add $0x80,%rsp - 415e7b: 8b 05 17 67 2b 00 mov 0x2b6717(%rip),%eax # 6cc598 <_IO_list_all_stamp> - 415e81: 48 c7 05 04 67 2b 00 movq $0x0,0x2b6704(%rip) # 6cc590 - 415e88: 00 00 00 00 - 415e8c: 44 39 e8 cmp %r13d,%eax - 415e8f: 0f 85 f3 fe ff ff jne 415d88 <_IO_flush_all+0xb8> - 415e95: 48 8b 5b 68 mov 0x68(%rbx),%rbx - 415e99: 48 85 db test %rbx,%rbx - 415e9c: 0f 85 f6 fe ff ff jne 415d98 <_IO_flush_all+0xc8> - 415ea2: 8b 05 fc 66 2b 00 mov 0x2b66fc(%rip),%eax # 6cc5a4 - 415ea8: 83 e8 01 sub $0x1,%eax - 415eab: 85 c0 test %eax,%eax - 415ead: 89 05 f1 66 2b 00 mov %eax,0x2b66f1(%rip) # 6cc5a4 - 415eb3: 75 41 jne 415ef6 <_IO_flush_all+0x226> - 415eb5: 48 c7 05 e8 66 2b 00 movq $0x0,0x2b66e8(%rip) # 6cc5a8 - 415ebc: 00 00 00 00 - 415ec0: 83 3d f5 72 2b 00 00 cmpl $0x0,0x2b72f5(%rip) # 6cd1bc <__libc_multiple_threads> - 415ec7: 74 0b je 415ed4 <_IO_flush_all+0x204> - 415ec9: f0 ff 0d d0 66 2b 00 lock decl 0x2b66d0(%rip) # 6cc5a0 - 415ed0: 75 0a jne 415edc <_IO_flush_all+0x20c> - 415ed2: eb 22 jmp 415ef6 <_IO_flush_all+0x226> - 415ed4: ff 0d c6 66 2b 00 decl 0x2b66c6(%rip) # 6cc5a0 - 415eda: 74 1a je 415ef6 <_IO_flush_all+0x226> - 415edc: 48 8d 3d bd 66 2b 00 lea 0x2b66bd(%rip),%rdi # 6cc5a0 - 415ee3: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 415eea: e8 11 c7 02 00 callq 442600 <__lll_unlock_wake_private> - 415eef: 48 81 c4 80 00 00 00 add $0x80,%rsp - 415ef6: 4d 85 e4 test %r12,%r12 - 415ef9: 74 0a je 415f05 <_IO_flush_all+0x235> - 415efb: 31 f6 xor %esi,%esi - 415efd: 48 89 e7 mov %rsp,%rdi - 415f00: e8 fb a0 be ff callq 0 <_nl_current_LC_CTYPE> - 415f05: 48 83 c4 20 add $0x20,%rsp - 415f09: 89 e8 mov %ebp,%eax - 415f0b: 5b pop %rbx - 415f0c: 5d pop %rbp - 415f0d: 41 5c pop %r12 - 415f0f: 41 5d pop %r13 - 415f11: 41 5e pop %r14 - 415f13: c3 retq - 415f14: 0f 1f 40 00 nopl 0x0(%rax) - 415f18: 48 8b 43 20 mov 0x20(%rbx),%rax - 415f1c: 48 39 43 28 cmp %rax,0x28(%rbx) - 415f20: 0f 87 f1 fe ff ff ja 415e17 <_IO_flush_all+0x147> - 415f26: e9 09 ff ff ff jmpq 415e34 <_IO_flush_all+0x164> - 415f2b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 415f30: 48 c7 04 24 50 41 41 movq $0x414150,(%rsp) - 415f37: 00 - 415f38: 48 c7 44 24 08 00 00 movq $0x0,0x8(%rsp) - 415f3f: 00 00 - 415f41: e9 b4 fd ff ff jmpq 415cfa <_IO_flush_all+0x2a> - 415f46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 415f4d: 00 00 00 - -0000000000415f50 <_IO_flush_all_linebuffered>: - 415f50: 41 55 push %r13 - 415f52: 41 54 push %r12 - 415f54: 55 push %rbp - 415f55: 53 push %rbx - 415f56: bd 00 00 00 00 mov $0x0,%ebp - 415f5b: 48 83 ec 28 sub $0x28,%rsp - 415f5f: 48 85 ed test %rbp,%rbp - 415f62: 0f 84 38 02 00 00 je 4161a0 <_IO_flush_all_linebuffered+0x250> - 415f68: 31 d2 xor %edx,%edx - 415f6a: be 50 41 41 00 mov $0x414150,%esi - 415f6f: 48 89 e7 mov %rsp,%rdi - 415f72: e8 89 a0 be ff callq 0 <_nl_current_LC_CTYPE> - 415f77: 64 48 8b 14 25 10 00 mov %fs:0x10,%rdx - 415f7e: 00 00 - 415f80: 48 3b 15 21 66 2b 00 cmp 0x2b6621(%rip),%rdx # 6cc5a8 - 415f87: 74 46 je 415fcf <_IO_flush_all_linebuffered+0x7f> - 415f89: be 01 00 00 00 mov $0x1,%esi - 415f8e: 31 c0 xor %eax,%eax - 415f90: 83 3d 25 72 2b 00 00 cmpl $0x0,0x2b7225(%rip) # 6cd1bc <__libc_multiple_threads> - 415f97: 74 0c je 415fa5 <_IO_flush_all_linebuffered+0x55> - 415f99: f0 0f b1 35 ff 65 2b lock cmpxchg %esi,0x2b65ff(%rip) # 6cc5a0 - 415fa0: 00 - 415fa1: 75 0b jne 415fae <_IO_flush_all_linebuffered+0x5e> - 415fa3: eb 23 jmp 415fc8 <_IO_flush_all_linebuffered+0x78> - 415fa5: 0f b1 35 f4 65 2b 00 cmpxchg %esi,0x2b65f4(%rip) # 6cc5a0 - 415fac: 74 1a je 415fc8 <_IO_flush_all_linebuffered+0x78> - 415fae: 48 8d 3d eb 65 2b 00 lea 0x2b65eb(%rip),%rdi # 6cc5a0 - 415fb5: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 415fbc: e8 0f c6 02 00 callq 4425d0 <__lll_lock_wait_private> - 415fc1: 48 81 c4 80 00 00 00 add $0x80,%rsp - 415fc8: 48 89 15 d9 65 2b 00 mov %rdx,0x2b65d9(%rip) # 6cc5a8 - 415fcf: 8b 05 cf 65 2b 00 mov 0x2b65cf(%rip),%eax # 6cc5a4 - 415fd5: 48 8b 1d e4 40 2b 00 mov 0x2b40e4(%rip),%rbx # 6ca0c0 <_IO_list_all> - 415fdc: 44 8b 25 b5 65 2b 00 mov 0x2b65b5(%rip),%r12d # 6cc598 <_IO_list_all_stamp> - 415fe3: 83 c0 01 add $0x1,%eax - 415fe6: 48 85 db test %rbx,%rbx - 415fe9: 89 05 b5 65 2b 00 mov %eax,0x2b65b5(%rip) # 6cc5a4 - 415fef: 0f 84 3a 01 00 00 je 41612f <_IO_flush_all_linebuffered+0x1df> - 415ff5: 44 89 e0 mov %r12d,%eax - 415ff8: 64 4c 8b 2c 25 10 00 mov %fs:0x10,%r13 - 415fff: 00 00 - 416001: e9 d7 00 00 00 jmpq 4160dd <_IO_flush_all_linebuffered+0x18d> - 416006: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41600d: 00 00 00 - 416010: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx - 416017: 4c 3b 6a 08 cmp 0x8(%rdx),%r13 - 41601b: 74 3e je 41605b <_IO_flush_all_linebuffered+0x10b> - 41601d: be 01 00 00 00 mov $0x1,%esi - 416022: 89 c8 mov %ecx,%eax - 416024: 83 3d 91 71 2b 00 00 cmpl $0x0,0x2b7191(%rip) # 6cd1bc <__libc_multiple_threads> - 41602b: 74 08 je 416035 <_IO_flush_all_linebuffered+0xe5> - 41602d: f0 0f b1 32 lock cmpxchg %esi,(%rdx) - 416031: 75 07 jne 41603a <_IO_flush_all_linebuffered+0xea> - 416033: eb 1b jmp 416050 <_IO_flush_all_linebuffered+0x100> - 416035: 0f b1 32 cmpxchg %esi,(%rdx) - 416038: 74 16 je 416050 <_IO_flush_all_linebuffered+0x100> - 41603a: 48 8d 3a lea (%rdx),%rdi - 41603d: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 416044: e8 87 c5 02 00 callq 4425d0 <__lll_lock_wait_private> - 416049: 48 81 c4 80 00 00 00 add $0x80,%rsp - 416050: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx - 416057: 4c 89 6a 08 mov %r13,0x8(%rdx) - 41605b: 83 42 04 01 addl $0x1,0x4(%rdx) - 41605f: 8b 03 mov (%rbx),%eax - 416061: 25 08 02 00 00 and $0x208,%eax - 416066: 3d 00 02 00 00 cmp $0x200,%eax - 41606b: 0f 84 91 00 00 00 je 416102 <_IO_flush_all_linebuffered+0x1b2> - 416071: f7 03 00 80 00 00 testl $0x8000,(%rbx) - 416077: 75 3f jne 4160b8 <_IO_flush_all_linebuffered+0x168> - 416079: 48 8b 93 88 00 00 00 mov 0x88(%rbx),%rdx - 416080: 83 6a 04 01 subl $0x1,0x4(%rdx) - 416084: 75 32 jne 4160b8 <_IO_flush_all_linebuffered+0x168> - 416086: 48 c7 42 08 00 00 00 movq $0x0,0x8(%rdx) - 41608d: 00 - 41608e: 83 3d 27 71 2b 00 00 cmpl $0x0,0x2b7127(%rip) # 6cd1bc <__libc_multiple_threads> - 416095: 74 07 je 41609e <_IO_flush_all_linebuffered+0x14e> - 416097: f0 ff 0a lock decl (%rdx) - 41609a: 75 06 jne 4160a2 <_IO_flush_all_linebuffered+0x152> - 41609c: eb 1a jmp 4160b8 <_IO_flush_all_linebuffered+0x168> - 41609e: ff 0a decl (%rdx) - 4160a0: 74 16 je 4160b8 <_IO_flush_all_linebuffered+0x168> - 4160a2: 48 8d 3a lea (%rdx),%rdi - 4160a5: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 4160ac: e8 4f c5 02 00 callq 442600 <__lll_unlock_wake_private> - 4160b1: 48 81 c4 80 00 00 00 add $0x80,%rsp - 4160b8: 8b 05 da 64 2b 00 mov 0x2b64da(%rip),%eax # 6cc598 <_IO_list_all_stamp> - 4160be: 41 39 c4 cmp %eax,%r12d - 4160c1: 48 c7 05 c4 64 2b 00 movq $0x0,0x2b64c4(%rip) # 6cc590 - 4160c8: 00 00 00 00 - 4160cc: 74 52 je 416120 <_IO_flush_all_linebuffered+0x1d0> - 4160ce: 48 8b 1d eb 3f 2b 00 mov 0x2b3feb(%rip),%rbx # 6ca0c0 <_IO_list_all> - 4160d5: 41 89 c4 mov %eax,%r12d - 4160d8: 48 85 db test %rbx,%rbx - 4160db: 74 4c je 416129 <_IO_flush_all_linebuffered+0x1d9> - 4160dd: 8b 13 mov (%rbx),%edx - 4160df: 48 89 1d aa 64 2b 00 mov %rbx,0x2b64aa(%rip) # 6cc590 - 4160e6: 89 d1 mov %edx,%ecx - 4160e8: 81 e1 00 80 00 00 and $0x8000,%ecx - 4160ee: 0f 84 1c ff ff ff je 416010 <_IO_flush_all_linebuffered+0xc0> - 4160f4: 81 e2 08 02 00 00 and $0x208,%edx - 4160fa: 81 fa 00 02 00 00 cmp $0x200,%edx - 416100: 75 bc jne 4160be <_IO_flush_all_linebuffered+0x16e> - 416102: 48 8b 83 d8 00 00 00 mov 0xd8(%rbx),%rax - 416109: be ff ff ff ff mov $0xffffffff,%esi - 41610e: 48 89 df mov %rbx,%rdi - 416111: ff 50 18 callq *0x18(%rax) - 416114: e9 58 ff ff ff jmpq 416071 <_IO_flush_all_linebuffered+0x121> - 416119: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 416120: 48 8b 5b 68 mov 0x68(%rbx),%rbx - 416124: 48 85 db test %rbx,%rbx - 416127: 75 b4 jne 4160dd <_IO_flush_all_linebuffered+0x18d> - 416129: 8b 05 75 64 2b 00 mov 0x2b6475(%rip),%eax # 6cc5a4 - 41612f: 83 e8 01 sub $0x1,%eax - 416132: 85 c0 test %eax,%eax - 416134: 89 05 6a 64 2b 00 mov %eax,0x2b646a(%rip) # 6cc5a4 - 41613a: 75 41 jne 41617d <_IO_flush_all_linebuffered+0x22d> - 41613c: 48 c7 05 61 64 2b 00 movq $0x0,0x2b6461(%rip) # 6cc5a8 - 416143: 00 00 00 00 - 416147: 83 3d 6e 70 2b 00 00 cmpl $0x0,0x2b706e(%rip) # 6cd1bc <__libc_multiple_threads> - 41614e: 74 0b je 41615b <_IO_flush_all_linebuffered+0x20b> - 416150: f0 ff 0d 49 64 2b 00 lock decl 0x2b6449(%rip) # 6cc5a0 - 416157: 75 0a jne 416163 <_IO_flush_all_linebuffered+0x213> - 416159: eb 22 jmp 41617d <_IO_flush_all_linebuffered+0x22d> - 41615b: ff 0d 3f 64 2b 00 decl 0x2b643f(%rip) # 6cc5a0 - 416161: 74 1a je 41617d <_IO_flush_all_linebuffered+0x22d> - 416163: 48 8d 3d 36 64 2b 00 lea 0x2b6436(%rip),%rdi # 6cc5a0 - 41616a: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 416171: e8 8a c4 02 00 callq 442600 <__lll_unlock_wake_private> - 416176: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41617d: 48 85 ed test %rbp,%rbp - 416180: 74 0a je 41618c <_IO_flush_all_linebuffered+0x23c> - 416182: 31 f6 xor %esi,%esi - 416184: 48 89 e7 mov %rsp,%rdi - 416187: e8 74 9e be ff callq 0 <_nl_current_LC_CTYPE> - 41618c: 48 83 c4 28 add $0x28,%rsp - 416190: 5b pop %rbx - 416191: 5d pop %rbp - 416192: 41 5c pop %r12 - 416194: 41 5d pop %r13 - 416196: c3 retq - 416197: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 41619e: 00 00 - 4161a0: 48 c7 04 24 50 41 41 movq $0x414150,(%rsp) - 4161a7: 00 - 4161a8: 48 c7 44 24 08 00 00 movq $0x0,0x8(%rsp) - 4161af: 00 00 - 4161b1: e9 c1 fd ff ff jmpq 415f77 <_IO_flush_all_linebuffered+0x27> - 4161b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4161bd: 00 00 00 - -00000000004161c0 <_IO_init_marker>: - 4161c0: 55 push %rbp - 4161c1: 53 push %rbx - 4161c2: 48 89 fd mov %rdi,%rbp - 4161c5: 48 89 f3 mov %rsi,%rbx - 4161c8: 48 83 ec 08 sub $0x8,%rsp - 4161cc: 8b 06 mov (%rsi),%eax - 4161ce: 48 89 77 08 mov %rsi,0x8(%rdi) - 4161d2: f6 c4 08 test $0x8,%ah - 4161d5: 75 31 jne 416208 <_IO_init_marker+0x48> - 4161d7: 48 8b 53 08 mov 0x8(%rbx),%rdx - 4161db: f6 c4 01 test $0x1,%ah - 4161de: 89 d0 mov %edx,%eax - 4161e0: 75 1e jne 416200 <_IO_init_marker+0x40> - 4161e2: 2b 43 18 sub 0x18(%rbx),%eax - 4161e5: 89 45 10 mov %eax,0x10(%rbp) - 4161e8: 48 8b 43 60 mov 0x60(%rbx),%rax - 4161ec: 48 89 45 00 mov %rax,0x0(%rbp) - 4161f0: 48 89 6b 60 mov %rbp,0x60(%rbx) - 4161f4: 48 83 c4 08 add $0x8,%rsp - 4161f8: 5b pop %rbx - 4161f9: 5d pop %rbp - 4161fa: c3 retq - 4161fb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 416200: 2b 43 10 sub 0x10(%rbx),%eax - 416203: eb e0 jmp 4161e5 <_IO_init_marker+0x25> - 416205: 0f 1f 00 nopl (%rax) - 416208: 48 8b 4e 28 mov 0x28(%rsi),%rcx - 41620c: 48 3b 4e 20 cmp 0x20(%rsi),%rcx - 416210: 77 3e ja 416250 <_IO_init_marker+0x90> - 416212: f6 c4 01 test $0x1,%ah - 416215: 75 29 jne 416240 <_IO_init_marker+0x80> - 416217: 48 3b 4b 10 cmp 0x10(%rbx),%rcx - 41621b: 48 8b 53 38 mov 0x38(%rbx),%rdx - 41621f: 48 89 53 18 mov %rdx,0x18(%rbx) - 416223: 48 89 ca mov %rcx,%rdx - 416226: 76 04 jbe 41622c <_IO_init_marker+0x6c> - 416228: 48 89 4b 10 mov %rcx,0x10(%rbx) - 41622c: 80 e4 f7 and $0xf7,%ah - 41622f: 48 89 4b 08 mov %rcx,0x8(%rbx) - 416233: 48 89 4b 30 mov %rcx,0x30(%rbx) - 416237: 48 89 4b 20 mov %rcx,0x20(%rbx) - 41623b: 89 03 mov %eax,(%rbx) - 41623d: eb 9c jmp 4161db <_IO_init_marker+0x1b> - 41623f: 90 nop - 416240: 48 8b 53 50 mov 0x50(%rbx),%rdx - 416244: 48 89 53 18 mov %rdx,0x18(%rbx) - 416248: 48 89 ca mov %rcx,%rdx - 41624b: eb df jmp 41622c <_IO_init_marker+0x6c> - 41624d: 0f 1f 00 nopl (%rax) - 416250: 48 8b 86 d8 00 00 00 mov 0xd8(%rsi),%rax - 416257: 48 89 df mov %rbx,%rdi - 41625a: be ff ff ff ff mov $0xffffffff,%esi - 41625f: ff 50 18 callq *0x18(%rax) - 416262: 83 f8 ff cmp $0xffffffff,%eax - 416265: 8b 03 mov (%rbx),%eax - 416267: 0f 84 6a ff ff ff je 4161d7 <_IO_init_marker+0x17> - 41626d: 48 8b 4b 28 mov 0x28(%rbx),%rcx - 416271: eb 9f jmp 416212 <_IO_init_marker+0x52> - 416273: 0f 1f 00 nopl (%rax) - 416276: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41627d: 00 00 00 - -0000000000416280 <_IO_remove_marker>: - 416280: 48 8b 47 08 mov 0x8(%rdi),%rax - 416284: 48 8b 50 60 mov 0x60(%rax),%rdx - 416288: 48 85 d2 test %rdx,%rdx - 41628b: 74 1b je 4162a8 <_IO_remove_marker+0x28> - 41628d: 48 39 d7 cmp %rdx,%rdi - 416290: 75 0e jne 4162a0 <_IO_remove_marker+0x20> - 416292: eb 16 jmp 4162aa <_IO_remove_marker+0x2a> - 416294: 0f 1f 40 00 nopl 0x0(%rax) - 416298: 48 39 c7 cmp %rax,%rdi - 41629b: 74 11 je 4162ae <_IO_remove_marker+0x2e> - 41629d: 48 89 c2 mov %rax,%rdx - 4162a0: 48 8b 02 mov (%rdx),%rax - 4162a3: 48 85 c0 test %rax,%rax - 4162a6: 75 f0 jne 416298 <_IO_remove_marker+0x18> - 4162a8: f3 c3 repz retq - 4162aa: 48 8d 50 60 lea 0x60(%rax),%rdx - 4162ae: 48 8b 07 mov (%rdi),%rax - 4162b1: 48 89 02 mov %rax,(%rdx) - 4162b4: c3 retq - 4162b5: 90 nop - 4162b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4162bd: 00 00 00 - -00000000004162c0 <_IO_marker_difference>: - 4162c0: 8b 47 10 mov 0x10(%rdi),%eax - 4162c3: 2b 46 10 sub 0x10(%rsi),%eax - 4162c6: c3 retq - 4162c7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 4162ce: 00 00 - -00000000004162d0 <_IO_marker_delta>: - 4162d0: 48 8b 47 08 mov 0x8(%rdi),%rax - 4162d4: 48 85 c0 test %rax,%rax - 4162d7: 74 20 je 4162f9 <_IO_marker_delta+0x29> - 4162d9: f7 00 00 01 00 00 testl $0x100,(%rax) - 4162df: 48 8b 50 08 mov 0x8(%rax),%rdx - 4162e3: 75 0b jne 4162f0 <_IO_marker_delta+0x20> - 4162e5: 2b 50 18 sub 0x18(%rax),%edx - 4162e8: 8b 47 10 mov 0x10(%rdi),%eax - 4162eb: 29 d0 sub %edx,%eax - 4162ed: c3 retq - 4162ee: 66 90 xchg %ax,%ax - 4162f0: 2b 50 10 sub 0x10(%rax),%edx - 4162f3: 8b 47 10 mov 0x10(%rdi),%eax - 4162f6: 29 d0 sub %edx,%eax - 4162f8: c3 retq - 4162f9: b8 ff ff ff ff mov $0xffffffff,%eax - 4162fe: c3 retq - 4162ff: 90 nop - -0000000000416300 <_IO_seekmark>: - 416300: 48 8b 56 08 mov 0x8(%rsi),%rdx - 416304: b8 ff ff ff ff mov $0xffffffff,%eax - 416309: 48 39 fa cmp %rdi,%rdx - 41630c: 75 3d jne 41634b <_IO_seekmark+0x4b> - 41630e: 48 63 46 10 movslq 0x10(%rsi),%rax - 416312: 8b 0a mov (%rdx),%ecx - 416314: 85 c0 test %eax,%eax - 416316: 78 48 js 416360 <_IO_seekmark+0x60> - 416318: f6 c5 01 test $0x1,%ch - 41631b: 74 33 je 416350 <_IO_seekmark+0x50> - 41631d: 80 e5 fe and $0xfe,%ch - 416320: 48 8b 72 58 mov 0x58(%rdx),%rsi - 416324: 89 0a mov %ecx,(%rdx) - 416326: 48 8b 4a 10 mov 0x10(%rdx),%rcx - 41632a: 48 89 72 10 mov %rsi,0x10(%rdx) - 41632e: 48 8b 72 18 mov 0x18(%rdx),%rsi - 416332: 48 89 4a 58 mov %rcx,0x58(%rdx) - 416336: 48 8b 4a 48 mov 0x48(%rdx),%rcx - 41633a: 48 89 72 48 mov %rsi,0x48(%rdx) - 41633e: 48 89 4a 18 mov %rcx,0x18(%rdx) - 416342: 48 01 c8 add %rcx,%rax - 416345: 48 89 42 08 mov %rax,0x8(%rdx) - 416349: 31 c0 xor %eax,%eax - 41634b: f3 c3 repz retq - 41634d: 0f 1f 00 nopl (%rax) - 416350: 48 8b 4a 18 mov 0x18(%rdx),%rcx - 416354: eb ec jmp 416342 <_IO_seekmark+0x42> - 416356: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41635d: 00 00 00 - 416360: f6 c5 01 test $0x1,%ch - 416363: 75 2b jne 416390 <_IO_seekmark+0x90> - 416365: 48 8b 72 10 mov 0x10(%rdx),%rsi - 416369: 80 cd 01 or $0x1,%ch - 41636c: 48 8b 7a 48 mov 0x48(%rdx),%rdi - 416370: 89 0a mov %ecx,(%rdx) - 416372: 48 8b 4a 58 mov 0x58(%rdx),%rcx - 416376: 48 89 72 58 mov %rsi,0x58(%rdx) - 41637a: 48 8b 72 18 mov 0x18(%rdx),%rsi - 41637e: 48 89 4a 10 mov %rcx,0x10(%rdx) - 416382: 48 89 7a 18 mov %rdi,0x18(%rdx) - 416386: 48 89 72 48 mov %rsi,0x48(%rdx) - 41638a: eb b6 jmp 416342 <_IO_seekmark+0x42> - 41638c: 0f 1f 40 00 nopl 0x0(%rax) - 416390: 48 8b 4a 10 mov 0x10(%rdx),%rcx - 416394: eb ac jmp 416342 <_IO_seekmark+0x42> - 416396: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41639d: 00 00 00 - -00000000004163a0 <_IO_unsave_markers>: - 4163a0: 48 83 7f 60 00 cmpq $0x0,0x60(%rdi) - 4163a5: 48 89 f8 mov %rdi,%rax - 4163a8: 74 08 je 4163b2 <_IO_unsave_markers+0x12> - 4163aa: 48 c7 47 60 00 00 00 movq $0x0,0x60(%rdi) - 4163b1: 00 - 4163b2: 48 8b 78 48 mov 0x48(%rax),%rdi - 4163b6: 48 85 ff test %rdi,%rdi - 4163b9: 74 45 je 416400 <_IO_unsave_markers+0x60> - 4163bb: 8b 10 mov (%rax),%edx - 4163bd: 53 push %rbx - 4163be: f6 c6 01 test $0x1,%dh - 4163c1: 74 1c je 4163df <_IO_unsave_markers+0x3f> - 4163c3: 80 e6 fe and $0xfe,%dh - 4163c6: 48 89 78 08 mov %rdi,0x8(%rax) - 4163ca: 89 10 mov %edx,(%rax) - 4163cc: 48 8b 50 58 mov 0x58(%rax),%rdx - 4163d0: 48 89 50 10 mov %rdx,0x10(%rax) - 4163d4: 48 8b 50 18 mov 0x18(%rax),%rdx - 4163d8: 48 89 78 18 mov %rdi,0x18(%rax) - 4163dc: 48 89 d7 mov %rdx,%rdi - 4163df: 48 89 c3 mov %rax,%rbx - 4163e2: e8 c9 79 00 00 callq 41ddb0 <__cfree> - 4163e7: 48 c7 43 48 00 00 00 movq $0x0,0x48(%rbx) - 4163ee: 00 - 4163ef: 48 c7 43 58 00 00 00 movq $0x0,0x58(%rbx) - 4163f6: 00 - 4163f7: 48 c7 43 50 00 00 00 movq $0x0,0x50(%rbx) - 4163fe: 00 - 4163ff: 5b pop %rbx - 416400: f3 c3 repz retq - 416402: 0f 1f 40 00 nopl 0x0(%rax) - 416406: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41640d: 00 00 00 - -0000000000416410 <_IO_default_pbackfail>: - 416410: 41 57 push %r15 - 416412: 41 56 push %r14 - 416414: 41 55 push %r13 - 416416: 41 54 push %r12 - 416418: 41 89 f4 mov %esi,%r12d - 41641b: 55 push %rbp - 41641c: 53 push %rbx - 41641d: 48 89 fb mov %rdi,%rbx - 416420: 48 83 ec 08 sub $0x8,%rsp - 416424: 48 8b 6f 08 mov 0x8(%rdi),%rbp - 416428: 4c 8b 77 18 mov 0x18(%rdi),%r14 - 41642c: 44 8b 2f mov (%rdi),%r13d - 41642f: 4c 39 f5 cmp %r14,%rbp - 416432: 76 2c jbe 416460 <_IO_default_pbackfail+0x50> - 416434: 41 f7 c5 00 01 00 00 test $0x100,%r13d - 41643b: 74 7b je 4164b8 <_IO_default_pbackfail+0xa8> - 41643d: 48 8d 45 ff lea -0x1(%rbp),%rax - 416441: 48 89 43 08 mov %rax,0x8(%rbx) - 416445: 44 88 65 ff mov %r12b,-0x1(%rbp) - 416449: 41 0f b6 c4 movzbl %r12b,%eax - 41644d: 48 83 c4 08 add $0x8,%rsp - 416451: 5b pop %rbx - 416452: 5d pop %rbp - 416453: 41 5c pop %r12 - 416455: 41 5d pop %r13 - 416457: 41 5e pop %r14 - 416459: 41 5f pop %r15 - 41645b: c3 retq - 41645c: 0f 1f 40 00 nopl 0x0(%rax) - 416460: 41 f7 c5 00 01 00 00 test $0x100,%r13d - 416467: 0f 84 83 00 00 00 je 4164f0 <_IO_default_pbackfail+0xe0> - 41646d: 4c 8b 6b 10 mov 0x10(%rbx),%r13 - 416471: 4d 29 f5 sub %r14,%r13 - 416474: 4b 8d 7c 2d 00 lea 0x0(%r13,%r13,1),%rdi - 416479: e8 92 75 00 00 callq 41da10 <__libc_malloc> - 41647e: 48 85 c0 test %rax,%rax - 416481: 49 89 c7 mov %rax,%r15 - 416484: 0f 84 d0 00 00 00 je 41655a <_IO_default_pbackfail+0x14a> - 41648a: 4a 8d 2c 28 lea (%rax,%r13,1),%rbp - 41648e: 4c 89 ea mov %r13,%rdx - 416491: 4c 89 f6 mov %r14,%rsi - 416494: 48 89 ef mov %rbp,%rdi - 416497: 49 01 ed add %rbp,%r13 - 41649a: e8 81 5b 01 00 callq 42c020 - 41649f: 4c 89 f7 mov %r14,%rdi - 4164a2: e8 09 79 00 00 callq 41ddb0 <__cfree> - 4164a7: 4c 89 7b 18 mov %r15,0x18(%rbx) - 4164ab: 4c 89 6b 10 mov %r13,0x10(%rbx) - 4164af: 48 89 6b 50 mov %rbp,0x50(%rbx) - 4164b3: eb 88 jmp 41643d <_IO_default_pbackfail+0x2d> - 4164b5: 0f 1f 00 nopl (%rax) - 4164b8: 0f b6 45 ff movzbl -0x1(%rbp),%eax - 4164bc: 39 f0 cmp %esi,%eax - 4164be: 74 68 je 416528 <_IO_default_pbackfail+0x118> - 4164c0: 48 83 7f 48 00 cmpq $0x0,0x48(%rdi) - 4164c5: 74 71 je 416538 <_IO_default_pbackfail+0x128> - 4164c7: 48 89 ee mov %rbp,%rsi - 4164ca: 48 89 df mov %rbx,%rdi - 4164cd: e8 8e da ff ff callq 413f60 - 4164d2: 85 c0 test %eax,%eax - 4164d4: 0f 85 80 00 00 00 jne 41655a <_IO_default_pbackfail+0x14a> - 4164da: 48 8b 4b 08 mov 0x8(%rbx),%rcx - 4164de: 44 8b 2b mov (%rbx),%r13d - 4164e1: 48 8b 6b 58 mov 0x58(%rbx),%rbp - 4164e5: 48 8b 43 48 mov 0x48(%rbx),%rax - 4164e9: eb 15 jmp 416500 <_IO_default_pbackfail+0xf0> - 4164eb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4164f0: 48 8b 43 48 mov 0x48(%rbx),%rax - 4164f4: 48 85 c0 test %rax,%rax - 4164f7: 74 3f je 416538 <_IO_default_pbackfail+0x128> - 4164f9: 48 89 e9 mov %rbp,%rcx - 4164fc: 48 8b 6b 58 mov 0x58(%rbx),%rbp - 416500: 48 8b 53 10 mov 0x10(%rbx),%rdx - 416504: 41 81 cd 00 01 00 00 or $0x100,%r13d - 41650b: 48 89 6b 10 mov %rbp,0x10(%rbx) - 41650f: 44 89 2b mov %r13d,(%rbx) - 416512: 48 89 43 18 mov %rax,0x18(%rbx) - 416516: 48 89 4b 48 mov %rcx,0x48(%rbx) - 41651a: 48 89 53 58 mov %rdx,0x58(%rbx) - 41651e: e9 1a ff ff ff jmpq 41643d <_IO_default_pbackfail+0x2d> - 416523: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 416528: 48 83 ed 01 sub $0x1,%rbp - 41652c: 48 89 6f 08 mov %rbp,0x8(%rdi) - 416530: e9 14 ff ff ff jmpq 416449 <_IO_default_pbackfail+0x39> - 416535: 0f 1f 00 nopl (%rax) - 416538: bf 80 00 00 00 mov $0x80,%edi - 41653d: e8 ce 74 00 00 callq 41da10 <__libc_malloc> - 416542: 48 85 c0 test %rax,%rax - 416545: 74 13 je 41655a <_IO_default_pbackfail+0x14a> - 416547: 48 8d 90 80 00 00 00 lea 0x80(%rax),%rdx - 41654e: 48 89 e9 mov %rbp,%rcx - 416551: 48 89 53 50 mov %rdx,0x50(%rbx) - 416555: 48 89 d5 mov %rdx,%rbp - 416558: eb a6 jmp 416500 <_IO_default_pbackfail+0xf0> - 41655a: b8 ff ff ff ff mov $0xffffffff,%eax - 41655f: e9 e9 fe ff ff jmpq 41644d <_IO_default_pbackfail+0x3d> - 416564: 66 90 xchg %ax,%ax - 416566: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41656d: 00 00 00 - -0000000000416570 <_IO_default_seek>: - 416570: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax - 416577: c3 retq - 416578: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 41657f: 00 - -0000000000416580 <_IO_default_stat>: - 416580: b8 ff ff ff ff mov $0xffffffff,%eax - 416585: c3 retq - 416586: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41658d: 00 00 00 - -0000000000416590 <_IO_default_read>: - 416590: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax - 416597: c3 retq - 416598: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 41659f: 00 - -00000000004165a0 <_IO_default_write>: - 4165a0: 31 c0 xor %eax,%eax - 4165a2: c3 retq - 4165a3: 0f 1f 00 nopl (%rax) - 4165a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4165ad: 00 00 00 - -00000000004165b0 <_IO_default_showmanyc>: - 4165b0: b8 ff ff ff ff mov $0xffffffff,%eax - 4165b5: c3 retq - 4165b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4165bd: 00 00 00 - -00000000004165c0 <_IO_default_imbue>: - 4165c0: f3 c3 repz retq - 4165c2: 0f 1f 40 00 nopl 0x0(%rax) - 4165c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4165cd: 00 00 00 - -00000000004165d0 <_IO_iter_begin>: - 4165d0: 48 8b 05 e9 3a 2b 00 mov 0x2b3ae9(%rip),%rax # 6ca0c0 <_IO_list_all> - 4165d7: c3 retq - 4165d8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 4165df: 00 - -00000000004165e0 <_IO_iter_end>: - 4165e0: 31 c0 xor %eax,%eax - 4165e2: c3 retq - 4165e3: 0f 1f 00 nopl (%rax) - 4165e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4165ed: 00 00 00 - -00000000004165f0 <_IO_iter_next>: - 4165f0: 48 8b 47 68 mov 0x68(%rdi),%rax - 4165f4: c3 retq - 4165f5: 90 nop - 4165f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4165fd: 00 00 00 - -0000000000416600 <_IO_iter_file>: - 416600: 48 89 f8 mov %rdi,%rax - 416603: c3 retq - 416604: 66 90 xchg %ax,%ax - 416606: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41660d: 00 00 00 - -0000000000416610 <_IO_list_lock>: - 416610: 64 48 8b 14 25 10 00 mov %fs:0x10,%rdx - 416617: 00 00 - 416619: 48 3b 15 88 5f 2b 00 cmp 0x2b5f88(%rip),%rdx # 6cc5a8 - 416620: 74 46 je 416668 <_IO_list_lock+0x58> - 416622: be 01 00 00 00 mov $0x1,%esi - 416627: 31 c0 xor %eax,%eax - 416629: 83 3d 8c 6b 2b 00 00 cmpl $0x0,0x2b6b8c(%rip) # 6cd1bc <__libc_multiple_threads> - 416630: 74 0c je 41663e <_IO_list_lock+0x2e> - 416632: f0 0f b1 35 66 5f 2b lock cmpxchg %esi,0x2b5f66(%rip) # 6cc5a0 - 416639: 00 - 41663a: 75 0b jne 416647 <_IO_list_lock+0x37> - 41663c: eb 23 jmp 416661 <_IO_list_lock+0x51> - 41663e: 0f b1 35 5b 5f 2b 00 cmpxchg %esi,0x2b5f5b(%rip) # 6cc5a0 - 416645: 74 1a je 416661 <_IO_list_lock+0x51> - 416647: 48 8d 3d 52 5f 2b 00 lea 0x2b5f52(%rip),%rdi # 6cc5a0 - 41664e: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 416655: e8 76 bf 02 00 callq 4425d0 <__lll_lock_wait_private> - 41665a: 48 81 c4 80 00 00 00 add $0x80,%rsp - 416661: 48 89 15 40 5f 2b 00 mov %rdx,0x2b5f40(%rip) # 6cc5a8 - 416668: 83 05 35 5f 2b 00 01 addl $0x1,0x2b5f35(%rip) # 6cc5a4 - 41666f: c3 retq - -0000000000416670 <_IO_list_unlock>: - 416670: 83 2d 2d 5f 2b 00 01 subl $0x1,0x2b5f2d(%rip) # 6cc5a4 - 416677: 75 41 jne 4166ba <_IO_list_unlock+0x4a> - 416679: 48 c7 05 24 5f 2b 00 movq $0x0,0x2b5f24(%rip) # 6cc5a8 - 416680: 00 00 00 00 - 416684: 83 3d 31 6b 2b 00 00 cmpl $0x0,0x2b6b31(%rip) # 6cd1bc <__libc_multiple_threads> - 41668b: 74 0b je 416698 <_IO_list_unlock+0x28> - 41668d: f0 ff 0d 0c 5f 2b 00 lock decl 0x2b5f0c(%rip) # 6cc5a0 - 416694: 75 0a jne 4166a0 <_IO_list_unlock+0x30> - 416696: eb 22 jmp 4166ba <_IO_list_unlock+0x4a> - 416698: ff 0d 02 5f 2b 00 decl 0x2b5f02(%rip) # 6cc5a0 - 41669e: 74 1a je 4166ba <_IO_list_unlock+0x4a> - 4166a0: 48 8d 3d f9 5e 2b 00 lea 0x2b5ef9(%rip),%rdi # 6cc5a0 - 4166a7: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 4166ae: e8 4d bf 02 00 callq 442600 <__lll_unlock_wake_private> - 4166b3: 48 81 c4 80 00 00 00 add $0x80,%rsp - 4166ba: f3 c3 repz retq - 4166bc: 0f 1f 40 00 nopl 0x0(%rax) - -00000000004166c0 <_IO_list_resetlock>: - 4166c0: c7 05 d6 5e 2b 00 00 movl $0x0,0x2b5ed6(%rip) # 6cc5a0 - 4166c7: 00 00 00 - 4166ca: c7 05 d0 5e 2b 00 00 movl $0x0,0x2b5ed0(%rip) # 6cc5a4 - 4166d1: 00 00 00 - 4166d4: 48 c7 05 c9 5e 2b 00 movq $0x0,0x2b5ec9(%rip) # 6cc5a8 - 4166db: 00 00 00 00 - 4166df: c3 retq - -00000000004166e0 <_IO_str_underflow>: - 4166e0: 48 8b 47 28 mov 0x28(%rdi),%rax - 4166e4: 48 8b 4f 10 mov 0x10(%rdi),%rcx - 4166e8: 48 39 c8 cmp %rcx,%rax - 4166eb: 76 07 jbe 4166f4 <_IO_str_underflow+0x14> - 4166ed: 48 89 47 10 mov %rax,0x10(%rdi) - 4166f1: 48 89 c1 mov %rax,%rcx - 4166f4: 8b 17 mov (%rdi),%edx - 4166f6: 81 e2 00 0c 00 00 and $0xc00,%edx - 4166fc: 81 fa 00 0c 00 00 cmp $0xc00,%edx - 416702: 74 14 je 416718 <_IO_str_underflow+0x38> - 416704: 48 8b 47 08 mov 0x8(%rdi),%rax - 416708: 48 39 c8 cmp %rcx,%rax - 41670b: 73 23 jae 416730 <_IO_str_underflow+0x50> - 41670d: 0f b6 00 movzbl (%rax),%eax - 416710: c3 retq - 416711: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 416718: 48 8b 57 30 mov 0x30(%rdi),%rdx - 41671c: 81 27 ff f7 ff ff andl $0xfffff7ff,(%rdi) - 416722: 48 89 47 08 mov %rax,0x8(%rdi) - 416726: 48 89 57 28 mov %rdx,0x28(%rdi) - 41672a: eb dc jmp 416708 <_IO_str_underflow+0x28> - 41672c: 0f 1f 40 00 nopl 0x0(%rax) - 416730: b8 ff ff ff ff mov $0xffffffff,%eax - 416735: c3 retq - 416736: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41673d: 00 00 00 - -0000000000416740 <_IO_str_overflow>: - 416740: 8b 0f mov (%rdi),%ecx - 416742: f6 c1 08 test $0x8,%cl - 416745: 74 11 je 416758 <_IO_str_overflow+0x18> - 416747: 31 c0 xor %eax,%eax - 416749: 83 fe ff cmp $0xffffffff,%esi - 41674c: 0f 95 c0 setne %al - 41674f: f7 d8 neg %eax - 416751: c3 retq - 416752: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 416758: 41 57 push %r15 - 41675a: 89 c8 mov %ecx,%eax - 41675c: 41 56 push %r14 - 41675e: 41 55 push %r13 - 416760: 41 54 push %r12 - 416762: 25 00 0c 00 00 and $0xc00,%eax - 416767: 55 push %rbp - 416768: 53 push %rbx - 416769: 48 83 ec 08 sub $0x8,%rsp - 41676d: 3d 00 04 00 00 cmp $0x400,%eax - 416772: 0f 84 08 01 00 00 je 416880 <_IO_str_overflow+0x140> - 416778: 48 8b 57 28 mov 0x28(%rdi),%rdx - 41677c: 4c 8b 67 38 mov 0x38(%rdi),%r12 - 416780: 4c 8b 6f 40 mov 0x40(%rdi),%r13 - 416784: 89 f5 mov %esi,%ebp - 416786: 48 89 d6 mov %rdx,%rsi - 416789: 48 2b 77 20 sub 0x20(%rdi),%rsi - 41678d: 31 c0 xor %eax,%eax - 41678f: 48 89 fb mov %rdi,%rbx - 416792: 4d 29 e5 sub %r12,%r13 - 416795: 83 fd ff cmp $0xffffffff,%ebp - 416798: 0f 94 c0 sete %al - 41679b: 4c 01 e8 add %r13,%rax - 41679e: 48 39 c6 cmp %rax,%rsi - 4167a1: 0f 82 aa 00 00 00 jb 416851 <_IO_str_overflow+0x111> - 4167a7: 83 e1 01 and $0x1,%ecx - 4167aa: 0f 85 f0 00 00 00 jne 4168a0 <_IO_str_overflow+0x160> - 4167b0: 4f 8d 74 2d 64 lea 0x64(%r13,%r13,1),%r14 - 4167b5: 4d 39 f5 cmp %r14,%r13 - 4167b8: 0f 87 e2 00 00 00 ja 4168a0 <_IO_str_overflow+0x160> - 4167be: 4c 89 f7 mov %r14,%rdi - 4167c1: ff 93 e0 00 00 00 callq *0xe0(%rbx) - 4167c7: 48 85 c0 test %rax,%rax - 4167ca: 49 89 c7 mov %rax,%r15 - 4167cd: 0f 84 cd 00 00 00 je 4168a0 <_IO_str_overflow+0x160> - 4167d3: 4d 85 e4 test %r12,%r12 - 4167d6: 74 1f je 4167f7 <_IO_str_overflow+0xb7> - 4167d8: 4c 89 ea mov %r13,%rdx - 4167db: 4c 89 e6 mov %r12,%rsi - 4167de: 48 89 c7 mov %rax,%rdi - 4167e1: e8 3a 58 01 00 callq 42c020 - 4167e6: 4c 89 e7 mov %r12,%rdi - 4167e9: ff 93 e8 00 00 00 callq *0xe8(%rbx) - 4167ef: 48 c7 43 38 00 00 00 movq $0x0,0x38(%rbx) - 4167f6: 00 - 4167f7: 4b 8d 3c 2f lea (%r15,%r13,1),%rdi - 4167fb: 4c 89 f2 mov %r14,%rdx - 4167fe: 31 f6 xor %esi,%esi - 416800: 4c 29 ea sub %r13,%rdx - 416803: e8 48 9b fe ff callq 400350 <__rela_iplt_end+0x88> - 416808: 4b 8d 14 37 lea (%r15,%r14,1),%rdx - 41680c: b9 01 00 00 00 mov $0x1,%ecx - 416811: 4c 89 fe mov %r15,%rsi - 416814: 48 89 df mov %rbx,%rdi - 416817: e8 84 e5 ff ff callq 414da0 <_IO_setb> - 41681c: 4c 89 f8 mov %r15,%rax - 41681f: 4c 89 7b 20 mov %r15,0x20(%rbx) - 416823: 4c 29 e0 sub %r12,%rax - 416826: 48 01 43 18 add %rax,0x18(%rbx) - 41682a: 4c 89 f8 mov %r15,%rax - 41682d: 4c 29 e0 sub %r12,%rax - 416830: 48 01 43 08 add %rax,0x8(%rbx) - 416834: 4c 89 f8 mov %r15,%rax - 416837: 4c 29 e0 sub %r12,%rax - 41683a: 48 01 43 10 add %rax,0x10(%rbx) - 41683e: 48 89 c2 mov %rax,%rdx - 416841: 48 03 53 28 add 0x28(%rbx),%rdx - 416845: 48 8b 43 40 mov 0x40(%rbx),%rax - 416849: 48 89 53 28 mov %rdx,0x28(%rbx) - 41684d: 48 89 43 30 mov %rax,0x30(%rbx) - 416851: 83 fd ff cmp $0xffffffff,%ebp - 416854: 74 0f je 416865 <_IO_str_overflow+0x125> - 416856: 48 8d 42 01 lea 0x1(%rdx),%rax - 41685a: 48 89 43 28 mov %rax,0x28(%rbx) - 41685e: 40 88 2a mov %bpl,(%rdx) - 416861: 48 8b 53 28 mov 0x28(%rbx),%rdx - 416865: 48 39 53 10 cmp %rdx,0x10(%rbx) - 416869: 89 e8 mov %ebp,%eax - 41686b: 73 04 jae 416871 <_IO_str_overflow+0x131> - 41686d: 48 89 53 10 mov %rdx,0x10(%rbx) - 416871: 48 83 c4 08 add $0x8,%rsp - 416875: 5b pop %rbx - 416876: 5d pop %rbp - 416877: 41 5c pop %r12 - 416879: 41 5d pop %r13 - 41687b: 41 5e pop %r14 - 41687d: 41 5f pop %r15 - 41687f: c3 retq - 416880: 48 8b 57 08 mov 0x8(%rdi),%rdx - 416884: 48 8b 47 10 mov 0x10(%rdi),%rax - 416888: 80 cd 08 or $0x8,%ch - 41688b: 89 0f mov %ecx,(%rdi) - 41688d: 48 89 57 28 mov %rdx,0x28(%rdi) - 416891: 48 89 47 08 mov %rax,0x8(%rdi) - 416895: e9 e2 fe ff ff jmpq 41677c <_IO_str_overflow+0x3c> - 41689a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4168a0: b8 ff ff ff ff mov $0xffffffff,%eax - 4168a5: eb ca jmp 416871 <_IO_str_overflow+0x131> - 4168a7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 4168ae: 00 00 - -00000000004168b0 : - 4168b0: 41 57 push %r15 - 4168b2: 41 56 push %r14 - 4168b4: 41 55 push %r13 - 4168b6: 41 54 push %r12 - 4168b8: 55 push %rbp - 4168b9: 53 push %rbx - 4168ba: 48 83 ec 28 sub $0x28,%rsp - 4168be: 4c 8b 77 38 mov 0x38(%rdi),%r14 - 4168c2: 48 8b 47 40 mov 0x40(%rdi),%rax - 4168c6: 4c 29 f0 sub %r14,%rax - 4168c9: 48 39 f0 cmp %rsi,%rax - 4168cc: 0f 8d fe 00 00 00 jge 4169d0 - 4168d2: 44 8b 3f mov (%rdi),%r15d - 4168d5: 41 83 e7 01 and $0x1,%r15d - 4168d9: 74 1d je 4168f8 - 4168db: 41 bf 01 00 00 00 mov $0x1,%r15d - 4168e1: 48 83 c4 28 add $0x28,%rsp - 4168e5: 44 89 f8 mov %r15d,%eax - 4168e8: 5b pop %rbx - 4168e9: 5d pop %rbp - 4168ea: 41 5c pop %r12 - 4168ec: 41 5d pop %r13 - 4168ee: 41 5e pop %r14 - 4168f0: 41 5f pop %r15 - 4168f2: c3 retq - 4168f3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4168f8: 48 8b 47 20 mov 0x20(%rdi),%rax - 4168fc: 48 89 fb mov %rdi,%rbx - 4168ff: 4c 8b 67 30 mov 0x30(%rdi),%r12 - 416903: 89 54 24 1c mov %edx,0x1c(%rsp) - 416907: 48 89 f5 mov %rsi,%rbp - 41690a: 48 89 44 24 08 mov %rax,0x8(%rsp) - 41690f: 48 8d 46 64 lea 0x64(%rsi),%rax - 416913: 48 89 44 24 10 mov %rax,0x10(%rsp) - 416918: 48 89 c7 mov %rax,%rdi - 41691b: ff 93 e0 00 00 00 callq *0xe0(%rbx) - 416921: 48 85 c0 test %rax,%rax - 416924: 49 89 c5 mov %rax,%r13 - 416927: 74 b2 je 4168db - 416929: 4d 85 f6 test %r14,%r14 - 41692c: 74 24 je 416952 - 41692e: 48 8b 53 40 mov 0x40(%rbx),%rdx - 416932: 48 2b 53 38 sub 0x38(%rbx),%rdx - 416936: 4c 89 f6 mov %r14,%rsi - 416939: 48 89 c7 mov %rax,%rdi - 41693c: e8 df 56 01 00 callq 42c020 - 416941: 4c 89 f7 mov %r14,%rdi - 416944: ff 93 e8 00 00 00 callq *0xe8(%rbx) - 41694a: 48 c7 43 38 00 00 00 movq $0x0,0x38(%rbx) - 416951: 00 - 416952: 48 8b 54 24 10 mov 0x10(%rsp),%rdx - 416957: b9 01 00 00 00 mov $0x1,%ecx - 41695c: 4c 89 ee mov %r13,%rsi - 41695f: 48 89 df mov %rbx,%rdi - 416962: 4c 2b 64 24 08 sub 0x8(%rsp),%r12 - 416967: 4c 01 ea add %r13,%rdx - 41696a: e8 31 e4 ff ff callq 414da0 <_IO_setb> - 41696f: 8b 54 24 1c mov 0x1c(%rsp),%edx - 416973: 4c 89 e8 mov %r13,%rax - 416976: 4c 29 f0 sub %r14,%rax - 416979: 85 d2 test %edx,%edx - 41697b: 75 63 jne 4169e0 - 41697d: 48 01 43 18 add %rax,0x18(%rbx) - 416981: 4c 89 e8 mov %r13,%rax - 416984: 4c 89 6b 20 mov %r13,0x20(%rbx) - 416988: 4c 29 f0 sub %r14,%rax - 41698b: 48 01 43 08 add %rax,0x8(%rbx) - 41698f: 4c 89 e8 mov %r13,%rax - 416992: 4c 29 f0 sub %r14,%rax - 416995: 48 01 43 10 add %rax,0x10(%rbx) - 416999: 4c 89 e8 mov %r13,%rax - 41699c: 4c 29 f0 sub %r14,%rax - 41699f: 48 01 43 28 add %rax,0x28(%rbx) - 4169a3: 4c 39 e5 cmp %r12,%rbp - 4169a6: 48 8b 43 40 mov 0x40(%rbx),%rax - 4169aa: 48 89 43 30 mov %rax,0x30(%rbx) - 4169ae: 7c 63 jl 416a13 - 4169b0: 48 89 ea mov %rbp,%rdx - 4169b3: 4b 8d 7c 25 00 lea 0x0(%r13,%r12,1),%rdi - 4169b8: 31 f6 xor %esi,%esi - 4169ba: 4c 29 e2 sub %r12,%rdx - 4169bd: e8 8e 99 fe ff callq 400350 <__rela_iplt_end+0x88> - 4169c2: e9 1a ff ff ff jmpq 4168e1 - 4169c7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 4169ce: 00 00 - 4169d0: 45 31 ff xor %r15d,%r15d - 4169d3: e9 09 ff ff ff jmpq 4168e1 - 4169d8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 4169df: 00 - 4169e0: 48 01 43 20 add %rax,0x20(%rbx) - 4169e4: 4c 89 e8 mov %r13,%rax - 4169e7: 4c 89 6b 18 mov %r13,0x18(%rbx) - 4169eb: 4c 29 f0 sub %r14,%rax - 4169ee: 48 01 43 28 add %rax,0x28(%rbx) - 4169f2: 4c 89 e8 mov %r13,%rax - 4169f5: 4c 29 f0 sub %r14,%rax - 4169f8: 48 01 43 30 add %rax,0x30(%rbx) - 4169fc: 4c 89 e8 mov %r13,%rax - 4169ff: 4c 29 f0 sub %r14,%rax - 416a02: 48 01 43 08 add %rax,0x8(%rbx) - 416a06: 4c 39 e5 cmp %r12,%rbp - 416a09: 48 8b 43 40 mov 0x40(%rbx),%rax - 416a0d: 48 89 43 10 mov %rax,0x10(%rbx) - 416a11: 7d 9d jge 4169b0 - 416a13: b9 f0 1e 4a 00 mov $0x4a1ef0,%ecx - 416a18: ba e0 00 00 00 mov $0xe0,%edx - 416a1d: be c8 1e 4a 00 mov $0x4a1ec8,%esi - 416a22: bf d1 1e 4a 00 mov $0x4a1ed1,%edi - 416a27: e8 14 ad fe ff callq 401740 <__assert_fail> - 416a2c: 0f 1f 40 00 nopl 0x0(%rax) - -0000000000416a30 <_IO_str_seekoff>: - 416a30: 41 55 push %r13 - 416a32: 41 54 push %r12 - 416a34: 41 89 d5 mov %edx,%r13d - 416a37: 55 push %rbp - 416a38: 53 push %rbx - 416a39: 49 89 f4 mov %rsi,%r12 - 416a3c: 48 89 fb mov %rdi,%rbx - 416a3f: 48 83 ec 18 sub $0x18,%rsp - 416a43: 85 c9 test %ecx,%ecx - 416a45: 0f 85 85 00 00 00 jne 416ad0 <_IO_str_seekoff+0xa0> - 416a4b: 8b 07 mov (%rdi),%eax - 416a4d: f6 c4 04 test $0x4,%ah - 416a50: 74 5e je 416ab0 <_IO_str_seekoff+0x80> - 416a52: f6 c4 08 test $0x8,%ah - 416a55: 0f 84 b5 00 00 00 je 416b10 <_IO_str_seekoff+0xe0> - 416a5b: 48 8b 6f 28 mov 0x28(%rdi),%rbp - 416a5f: 48 39 6f 10 cmp %rbp,0x10(%rdi) - 416a63: 48 0f 43 6f 10 cmovae 0x10(%rdi),%rbp - 416a68: 48 2b 6f 18 sub 0x18(%rdi),%rbp - 416a6c: 41 83 fd 01 cmp $0x1,%r13d - 416a70: 0f 84 12 01 00 00 je 416b88 <_IO_str_seekoff+0x158> - 416a76: 49 8d 04 2c lea (%r12,%rbp,1),%rax - 416a7a: 41 83 fd 02 cmp $0x2,%r13d - 416a7e: 4c 0f 44 e0 cmove %rax,%r12 - 416a82: 4d 85 e4 test %r12,%r12 - 416a85: 0f 88 2a 01 00 00 js 416bb5 <_IO_str_seekoff+0x185> - 416a8b: 49 39 ec cmp %rbp,%r12 - 416a8e: 0f 8f 0c 01 00 00 jg 416ba0 <_IO_str_seekoff+0x170> - 416a94: 4c 89 e0 mov %r12,%rax - 416a97: 48 03 43 20 add 0x20(%rbx),%rax - 416a9b: 48 89 43 28 mov %rax,0x28(%rbx) - 416a9f: 48 83 c4 18 add $0x18,%rsp - 416aa3: 4c 89 e0 mov %r12,%rax - 416aa6: 5b pop %rbx - 416aa7: 5d pop %rbp - 416aa8: 41 5c pop %r12 - 416aaa: 41 5d pop %r13 - 416aac: c3 retq - 416aad: 0f 1f 00 nopl (%rax) - 416ab0: a8 08 test $0x8,%al - 416ab2: 0f 85 a8 00 00 00 jne 416b60 <_IO_str_seekoff+0x130> - 416ab8: 48 8b 43 28 mov 0x28(%rbx),%rax - 416abc: 48 2b 43 20 sub 0x20(%rbx),%rax - 416ac0: 48 83 c4 18 add $0x18,%rsp - 416ac4: 5b pop %rbx - 416ac5: 5d pop %rbp - 416ac6: 41 5c pop %r12 - 416ac8: 41 5d pop %r13 - 416aca: c3 retq - 416acb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 416ad0: 48 8b 6f 28 mov 0x28(%rdi),%rbp - 416ad4: 48 39 6f 10 cmp %rbp,0x10(%rdi) - 416ad8: 48 0f 43 6f 10 cmovae 0x10(%rdi),%rbp - 416add: 48 8b 47 18 mov 0x18(%rdi),%rax - 416ae1: 48 29 c5 sub %rax,%rbp - 416ae4: f6 c1 01 test $0x1,%cl - 416ae7: 75 40 jne 416b29 <_IO_str_seekoff+0xf9> - 416ae9: 83 e1 02 and $0x2,%ecx - 416aec: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax - 416af3: 85 c9 test %ecx,%ecx - 416af5: 0f 85 71 ff ff ff jne 416a6c <_IO_str_seekoff+0x3c> - 416afb: 48 83 c4 18 add $0x18,%rsp - 416aff: 5b pop %rbx - 416b00: 5d pop %rbp - 416b01: 41 5c pop %r12 - 416b03: 41 5d pop %r13 - 416b05: c3 retq - 416b06: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 416b0d: 00 00 00 - 416b10: 48 8b 6f 28 mov 0x28(%rdi),%rbp - 416b14: 48 39 6f 10 cmp %rbp,0x10(%rdi) - 416b18: b9 01 00 00 00 mov $0x1,%ecx - 416b1d: 48 0f 43 6f 10 cmovae 0x10(%rdi),%rbp - 416b22: 48 8b 47 18 mov 0x18(%rdi),%rax - 416b26: 48 29 c5 sub %rax,%rbp - 416b29: 41 83 fd 01 cmp $0x1,%r13d - 416b2d: 74 49 je 416b78 <_IO_str_seekoff+0x148> - 416b2f: 49 8d 14 2c lea (%r12,%rbp,1),%rdx - 416b33: 41 83 fd 02 cmp $0x2,%r13d - 416b37: 4c 0f 44 e2 cmove %rdx,%r12 - 416b3b: 4d 85 e4 test %r12,%r12 - 416b3e: 78 75 js 416bb5 <_IO_str_seekoff+0x185> - 416b40: 49 39 ec cmp %rbp,%r12 - 416b43: 0f 8f 7f 00 00 00 jg 416bc8 <_IO_str_seekoff+0x198> - 416b49: 4a 8d 14 20 lea (%rax,%r12,1),%rdx - 416b4d: 48 01 e8 add %rbp,%rax - 416b50: 83 e1 02 and $0x2,%ecx - 416b53: 48 89 43 10 mov %rax,0x10(%rbx) - 416b57: 4c 89 e0 mov %r12,%rax - 416b5a: 48 89 53 08 mov %rdx,0x8(%rbx) - 416b5e: eb 93 jmp 416af3 <_IO_str_seekoff+0xc3> - 416b60: 48 8b 43 08 mov 0x8(%rbx),%rax - 416b64: 48 2b 43 18 sub 0x18(%rbx),%rax - 416b68: 48 83 c4 18 add $0x18,%rsp - 416b6c: 5b pop %rbx - 416b6d: 5d pop %rbp - 416b6e: 41 5c pop %r12 - 416b70: 41 5d pop %r13 - 416b72: c3 retq - 416b73: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 416b78: 48 8b 53 08 mov 0x8(%rbx),%rdx - 416b7c: 48 29 c2 sub %rax,%rdx - 416b7f: 49 01 d4 add %rdx,%r12 - 416b82: eb b7 jmp 416b3b <_IO_str_seekoff+0x10b> - 416b84: 0f 1f 40 00 nopl 0x0(%rax) - 416b88: 48 8b 43 28 mov 0x28(%rbx),%rax - 416b8c: 48 2b 43 20 sub 0x20(%rbx),%rax - 416b90: 49 01 c4 add %rax,%r12 - 416b93: e9 ea fe ff ff jmpq 416a82 <_IO_str_seekoff+0x52> - 416b98: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 416b9f: 00 - 416ba0: 31 d2 xor %edx,%edx - 416ba2: 4c 89 e6 mov %r12,%rsi - 416ba5: 48 89 df mov %rbx,%rdi - 416ba8: e8 03 fd ff ff callq 4168b0 - 416bad: 85 c0 test %eax,%eax - 416baf: 0f 84 df fe ff ff je 416a94 <_IO_str_seekoff+0x64> - 416bb5: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax - 416bbc: e9 ff fe ff ff jmpq 416ac0 <_IO_str_seekoff+0x90> - 416bc1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 416bc8: ba 01 00 00 00 mov $0x1,%edx - 416bcd: 4c 89 e6 mov %r12,%rsi - 416bd0: 48 89 df mov %rbx,%rdi - 416bd3: 89 4c 24 0c mov %ecx,0xc(%rsp) - 416bd7: e8 d4 fc ff ff callq 4168b0 - 416bdc: 85 c0 test %eax,%eax - 416bde: 75 d5 jne 416bb5 <_IO_str_seekoff+0x185> - 416be0: 48 8b 43 18 mov 0x18(%rbx),%rax - 416be4: 8b 4c 24 0c mov 0xc(%rsp),%ecx - 416be8: e9 5c ff ff ff jmpq 416b49 <_IO_str_seekoff+0x119> - 416bed: 0f 1f 00 nopl (%rax) - -0000000000416bf0 <_IO_str_pbackfail>: - 416bf0: f6 07 08 testb $0x8,(%rdi) - 416bf3: 74 05 je 416bfa <_IO_str_pbackfail+0xa> - 416bf5: 83 fe ff cmp $0xffffffff,%esi - 416bf8: 75 06 jne 416c00 <_IO_str_pbackfail+0x10> - 416bfa: e9 11 f8 ff ff jmpq 416410 <_IO_default_pbackfail> - 416bff: 90 nop - 416c00: b8 ff ff ff ff mov $0xffffffff,%eax - 416c05: c3 retq - 416c06: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 416c0d: 00 00 00 - -0000000000416c10 <_IO_str_finish>: - 416c10: 53 push %rbx - 416c11: 48 89 fb mov %rdi,%rbx - 416c14: 48 8b 7f 38 mov 0x38(%rdi),%rdi - 416c18: 48 85 ff test %rdi,%rdi - 416c1b: 74 0b je 416c28 <_IO_str_finish+0x18> - 416c1d: f6 03 01 testb $0x1,(%rbx) - 416c20: 75 06 jne 416c28 <_IO_str_finish+0x18> - 416c22: ff 93 e8 00 00 00 callq *0xe8(%rbx) - 416c28: 48 c7 43 38 00 00 00 movq $0x0,0x38(%rbx) - 416c2f: 00 - 416c30: 48 89 df mov %rbx,%rdi - 416c33: 31 f6 xor %esi,%esi - 416c35: 5b pop %rbx - 416c36: e9 d5 e9 ff ff jmpq 415610 <_IO_default_finish> - 416c3b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - -0000000000416c40 <_IO_str_init_static_internal>: - 416c40: 41 55 push %r13 - 416c42: 41 54 push %r12 - 416c44: 49 89 cd mov %rcx,%r13 - 416c47: 55 push %rbp - 416c48: 53 push %rbx - 416c49: 49 89 f4 mov %rsi,%r12 - 416c4c: 48 89 fb mov %rdi,%rbx - 416c4f: 48 83 ec 08 sub $0x8,%rsp - 416c53: 48 85 d2 test %rdx,%rdx - 416c56: 75 58 jne 416cb0 <_IO_str_init_static_internal+0x70> - 416c58: 31 f6 xor %esi,%esi - 416c5a: 4c 89 e7 mov %r12,%rdi - 416c5d: e8 6e 5d 01 00 callq 42c9d0 <__rawmemchr> - 416c62: 48 89 c5 mov %rax,%rbp - 416c65: 31 c9 xor %ecx,%ecx - 416c67: 48 89 ea mov %rbp,%rdx - 416c6a: 4c 89 e6 mov %r12,%rsi - 416c6d: 48 89 df mov %rbx,%rdi - 416c70: e8 2b e1 ff ff callq 414da0 <_IO_setb> - 416c75: 4d 85 ed test %r13,%r13 - 416c78: 4c 89 63 20 mov %r12,0x20(%rbx) - 416c7c: 4c 89 63 18 mov %r12,0x18(%rbx) - 416c80: 4c 89 63 08 mov %r12,0x8(%rbx) - 416c84: 74 42 je 416cc8 <_IO_str_init_static_internal+0x88> - 416c86: 4c 89 6b 28 mov %r13,0x28(%rbx) - 416c8a: 48 89 6b 30 mov %rbp,0x30(%rbx) - 416c8e: 4c 89 6b 10 mov %r13,0x10(%rbx) - 416c92: 48 c7 83 e0 00 00 00 movq $0x0,0xe0(%rbx) - 416c99: 00 00 00 00 - 416c9d: 48 83 c4 08 add $0x8,%rsp - 416ca1: 5b pop %rbx - 416ca2: 5d pop %rbp - 416ca3: 41 5c pop %r12 - 416ca5: 41 5d pop %r13 - 416ca7: c3 retq - 416ca8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 416caf: 00 - 416cb0: 48 01 f2 add %rsi,%rdx - 416cb3: 48 c7 c5 ff ff ff ff mov $0xffffffffffffffff,%rbp - 416cba: 48 39 d6 cmp %rdx,%rsi - 416cbd: 48 0f 42 ea cmovb %rdx,%rbp - 416cc1: eb a2 jmp 416c65 <_IO_str_init_static_internal+0x25> - 416cc3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 416cc8: 4c 89 63 28 mov %r12,0x28(%rbx) - 416ccc: 4c 89 63 30 mov %r12,0x30(%rbx) - 416cd0: 48 89 6b 10 mov %rbp,0x10(%rbx) - 416cd4: eb bc jmp 416c92 <_IO_str_init_static_internal+0x52> - 416cd6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 416cdd: 00 00 00 - -0000000000416ce0 <_IO_str_init_static>: - 416ce0: 41 55 push %r13 - 416ce2: 41 54 push %r12 - 416ce4: 49 89 cd mov %rcx,%r13 - 416ce7: 55 push %rbp - 416ce8: 53 push %rbx - 416ce9: bb ff ff ff ff mov $0xffffffff,%ebx - 416cee: 48 89 fd mov %rdi,%rbp - 416cf1: 49 89 f4 mov %rsi,%r12 - 416cf4: 48 83 ec 08 sub $0x8,%rsp - 416cf8: 85 d2 test %edx,%edx - 416cfa: 0f 48 d3 cmovs %ebx,%edx - 416cfd: 48 63 d2 movslq %edx,%rdx - 416d00: 48 85 d2 test %rdx,%rdx - 416d03: 75 53 jne 416d58 <_IO_str_init_static+0x78> - 416d05: 31 f6 xor %esi,%esi - 416d07: 4c 89 e7 mov %r12,%rdi - 416d0a: e8 c1 5c 01 00 callq 42c9d0 <__rawmemchr> - 416d0f: 48 89 c3 mov %rax,%rbx - 416d12: 31 c9 xor %ecx,%ecx - 416d14: 48 89 da mov %rbx,%rdx - 416d17: 4c 89 e6 mov %r12,%rsi - 416d1a: 48 89 ef mov %rbp,%rdi - 416d1d: e8 7e e0 ff ff callq 414da0 <_IO_setb> - 416d22: 4d 85 ed test %r13,%r13 - 416d25: 4c 89 65 20 mov %r12,0x20(%rbp) - 416d29: 4c 89 65 18 mov %r12,0x18(%rbp) - 416d2d: 4c 89 65 08 mov %r12,0x8(%rbp) - 416d31: 74 3d je 416d70 <_IO_str_init_static+0x90> - 416d33: 4c 89 6d 28 mov %r13,0x28(%rbp) - 416d37: 48 89 5d 30 mov %rbx,0x30(%rbp) - 416d3b: 4c 89 6d 10 mov %r13,0x10(%rbp) - 416d3f: 48 c7 85 e0 00 00 00 movq $0x0,0xe0(%rbp) - 416d46: 00 00 00 00 - 416d4a: 48 83 c4 08 add $0x8,%rsp - 416d4e: 5b pop %rbx - 416d4f: 5d pop %rbp - 416d50: 41 5c pop %r12 - 416d52: 41 5d pop %r13 - 416d54: c3 retq - 416d55: 0f 1f 00 nopl (%rax) - 416d58: 48 01 f2 add %rsi,%rdx - 416d5b: 48 c7 c3 ff ff ff ff mov $0xffffffffffffffff,%rbx - 416d62: 48 39 d6 cmp %rdx,%rsi - 416d65: 48 0f 42 da cmovb %rdx,%rbx - 416d69: eb a7 jmp 416d12 <_IO_str_init_static+0x32> - 416d6b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 416d70: 4c 89 65 28 mov %r12,0x28(%rbp) - 416d74: 4c 89 65 30 mov %r12,0x30(%rbp) - 416d78: 48 89 5d 10 mov %rbx,0x10(%rbp) - 416d7c: eb c1 jmp 416d3f <_IO_str_init_static+0x5f> - 416d7e: 66 90 xchg %ax,%ax - -0000000000416d80 <_IO_str_init_readonly>: - 416d80: 41 54 push %r12 - 416d82: 85 d2 test %edx,%edx - 416d84: 55 push %rbp - 416d85: 53 push %rbx - 416d86: bb ff ff ff ff mov $0xffffffff,%ebx - 416d8b: 48 89 fd mov %rdi,%rbp - 416d8e: 0f 48 d3 cmovs %ebx,%edx - 416d91: 49 89 f4 mov %rsi,%r12 - 416d94: 48 63 d2 movslq %edx,%rdx - 416d97: 48 85 d2 test %rdx,%rdx - 416d9a: 75 4c jne 416de8 <_IO_str_init_readonly+0x68> - 416d9c: 31 f6 xor %esi,%esi - 416d9e: 4c 89 e7 mov %r12,%rdi - 416da1: e8 2a 5c 01 00 callq 42c9d0 <__rawmemchr> - 416da6: 48 89 c3 mov %rax,%rbx - 416da9: 48 89 da mov %rbx,%rdx - 416dac: 4c 89 e6 mov %r12,%rsi - 416daf: 48 89 ef mov %rbp,%rdi - 416db2: 31 c9 xor %ecx,%ecx - 416db4: e8 e7 df ff ff callq 414da0 <_IO_setb> - 416db9: 83 4d 00 08 orl $0x8,0x0(%rbp) - 416dbd: 4c 89 65 20 mov %r12,0x20(%rbp) - 416dc1: 4c 89 65 18 mov %r12,0x18(%rbp) - 416dc5: 4c 89 65 08 mov %r12,0x8(%rbp) - 416dc9: 4c 89 65 28 mov %r12,0x28(%rbp) - 416dcd: 4c 89 65 30 mov %r12,0x30(%rbp) - 416dd1: 48 89 5d 10 mov %rbx,0x10(%rbp) - 416dd5: 48 c7 85 e0 00 00 00 movq $0x0,0xe0(%rbp) - 416ddc: 00 00 00 00 - 416de0: 5b pop %rbx - 416de1: 5d pop %rbp - 416de2: 41 5c pop %r12 - 416de4: c3 retq - 416de5: 0f 1f 00 nopl (%rax) - 416de8: 48 01 f2 add %rsi,%rdx - 416deb: 48 c7 c3 ff ff ff ff mov $0xffffffffffffffff,%rbx - 416df2: 48 39 d6 cmp %rdx,%rsi - 416df5: 48 0f 42 da cmovb %rdx,%rbx - 416df9: eb ae jmp 416da9 <_IO_str_init_readonly+0x29> - 416dfb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - -0000000000416e00 <_IO_str_count>: - 416e00: 48 8b 47 28 mov 0x28(%rdi),%rax - 416e04: 48 39 47 10 cmp %rax,0x10(%rdi) - 416e08: 48 0f 43 47 10 cmovae 0x10(%rdi),%rax - 416e0d: 48 2b 47 18 sub 0x18(%rdi),%rax - 416e11: c3 retq - 416e12: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 416e19: 00 00 00 - 416e1c: 0f 1f 40 00 nopl 0x0(%rax) - -0000000000416e20 <__malloc_assert>: - 416e20: 48 83 ec 10 sub $0x10,%rsp - 416e24: 41 89 d1 mov %edx,%r9d - 416e27: 48 8b 15 b2 42 2b 00 mov 0x2b42b2(%rip),%rdx # 6cb0e0 <__progname> - 416e2e: 41 bb 25 67 4b 00 mov $0x4b6725,%r11d - 416e34: 41 ba 6f 52 4b 00 mov $0x4b526f,%r10d - 416e3a: 48 85 c9 test %rcx,%rcx - 416e3d: 49 89 f0 mov %rsi,%r8 - 416e40: 48 89 c8 mov %rcx,%rax - 416e43: 4c 89 de mov %r11,%rsi - 416e46: 49 0f 45 f2 cmovne %r10,%rsi - 416e4a: 49 0f 44 c3 cmove %r11,%rax - 416e4e: 80 3a 00 cmpb $0x0,(%rdx) - 416e51: 4c 89 d9 mov %r11,%rcx - 416e54: 57 push %rdi - 416e55: 56 push %rsi - 416e56: 50 push %rax - 416e57: be 20 23 4a 00 mov $0x4a2320,%esi - 416e5c: 49 0f 45 ca cmovne %r10,%rcx - 416e60: 31 ff xor %edi,%edi - 416e62: 31 c0 xor %eax,%eax - 416e64: e8 27 85 ff ff callq 40f390 <__fxprintf> - 416e69: 48 8b 3d c8 38 2b 00 mov 0x2b38c8(%rip),%rdi # 6ca738 <_IO_stderr> - 416e70: 48 83 c4 20 add $0x20,%rsp - 416e74: e8 c7 88 ff ff callq 40f740 <_IO_fflush> - 416e79: e8 82 6d ff ff callq 40dc00 - 416e7e: 66 90 xchg %ax,%ax - -0000000000416e80 : - 416e80: 48 01 fe add %rdi,%rsi - 416e83: 41 54 push %r12 - 416e85: 48 8b 05 f4 42 2b 00 mov 0x2b42f4(%rip),%rax # 6cb180 <_dl_pagesize> - 416e8c: 48 81 fe ff 7f 00 00 cmp $0x7fff,%rsi - 416e93: 55 push %rbp - 416e94: 53 push %rbx - 416e95: 0f 86 f5 00 00 00 jbe 416f90 - 416e9b: 48 81 fe 00 00 00 04 cmp $0x4000000,%rsi - 416ea2: 0f 87 f8 00 00 00 ja 416fa0 - 416ea8: 48 8b 3d 61 57 2b 00 mov 0x2b5761(%rip),%rdi # 6cc610 - 416eaf: 48 8d 6c 06 ff lea -0x1(%rsi,%rax,1),%rbp - 416eb4: 48 f7 d8 neg %rax - 416eb7: 48 21 c5 and %rax,%rbp - 416eba: 48 85 ff test %rdi,%rdi - 416ebd: 74 6e je 416f2d - 416ebf: 45 31 c9 xor %r9d,%r9d - 416ec2: 31 d2 xor %edx,%edx - 416ec4: 41 b8 ff ff ff ff mov $0xffffffff,%r8d - 416eca: b9 22 40 00 00 mov $0x4022,%ecx - 416ecf: be 00 00 00 04 mov $0x4000000,%esi - 416ed4: e8 17 8d 02 00 callq 43fbf0 <__mmap> - 416ed9: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 416edd: 48 89 c3 mov %rax,%rbx - 416ee0: 48 c7 05 25 57 2b 00 movq $0x0,0x2b5725(%rip) # 6cc610 - 416ee7: 00 00 00 00 - 416eeb: 74 40 je 416f2d - 416eed: a9 ff ff ff 03 test $0x3ffffff,%eax - 416ef2: 75 2c jne 416f20 - 416ef4: ba 03 00 00 00 mov $0x3,%edx - 416ef9: 48 89 ee mov %rbp,%rsi - 416efc: 48 89 df mov %rbx,%rdi - 416eff: e8 cc 8d 02 00 callq 43fcd0 <__mprotect> - 416f04: 85 c0 test %eax,%eax - 416f06: 0f 85 fc 00 00 00 jne 417008 - 416f0c: 48 89 6b 10 mov %rbp,0x10(%rbx) - 416f10: 48 89 6b 18 mov %rbp,0x18(%rbx) - 416f14: 90 nop - 416f15: 48 89 d8 mov %rbx,%rax - 416f18: 5b pop %rbx - 416f19: 5d pop %rbp - 416f1a: 41 5c pop %r12 - 416f1c: c3 retq - 416f1d: 0f 1f 00 nopl (%rax) - 416f20: be 00 00 00 04 mov $0x4000000,%esi - 416f25: 48 89 c7 mov %rax,%rdi - 416f28: e8 83 8d 02 00 callq 43fcb0 <__munmap> - 416f2d: 45 31 c9 xor %r9d,%r9d - 416f30: 31 d2 xor %edx,%edx - 416f32: 31 ff xor %edi,%edi - 416f34: 41 b8 ff ff ff ff mov $0xffffffff,%r8d - 416f3a: b9 22 40 00 00 mov $0x4022,%ecx - 416f3f: be 00 00 00 08 mov $0x8000000,%esi - 416f44: e8 a7 8c 02 00 callq 43fbf0 <__mmap> - 416f49: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 416f4d: 0f 84 85 00 00 00 je 416fd8 - 416f53: 48 8d 98 ff ff ff 03 lea 0x3ffffff(%rax),%rbx - 416f5a: 48 81 e3 00 00 00 fc and $0xfffffffffc000000,%rbx - 416f61: 49 89 dc mov %rbx,%r12 - 416f64: 49 29 c4 sub %rax,%r12 - 416f67: 75 57 jne 416fc0 - 416f69: 48 8d bb 00 00 00 04 lea 0x4000000(%rbx),%rdi - 416f70: 48 89 3d 99 56 2b 00 mov %rdi,0x2b5699(%rip) # 6cc610 - 416f77: be 00 00 00 04 mov $0x4000000,%esi - 416f7c: 4c 29 e6 sub %r12,%rsi - 416f7f: e8 2c 8d 02 00 callq 43fcb0 <__munmap> - 416f84: e9 6b ff ff ff jmpq 416ef4 - 416f89: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 416f90: be 00 80 00 00 mov $0x8000,%esi - 416f95: e9 0e ff ff ff jmpq 416ea8 - 416f9a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 416fa0: 48 81 ff 00 00 00 04 cmp $0x4000000,%rdi - 416fa7: be 00 00 00 04 mov $0x4000000,%esi - 416fac: 0f 86 f6 fe ff ff jbe 416ea8 - 416fb2: 31 c0 xor %eax,%eax - 416fb4: e9 5f ff ff ff jmpq 416f18 - 416fb9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 416fc0: 48 89 c7 mov %rax,%rdi - 416fc3: 4c 89 e6 mov %r12,%rsi - 416fc6: e8 e5 8c 02 00 callq 43fcb0 <__munmap> - 416fcb: 48 8d bb 00 00 00 04 lea 0x4000000(%rbx),%rdi - 416fd2: eb a3 jmp 416f77 - 416fd4: 0f 1f 40 00 nopl 0x0(%rax) - 416fd8: 45 31 c9 xor %r9d,%r9d - 416fdb: 31 d2 xor %edx,%edx - 416fdd: 31 ff xor %edi,%edi - 416fdf: 41 89 c0 mov %eax,%r8d - 416fe2: b9 22 40 00 00 mov $0x4022,%ecx - 416fe7: be 00 00 00 04 mov $0x4000000,%esi - 416fec: e8 ff 8b 02 00 callq 43fbf0 <__mmap> - 416ff1: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 416ff5: 48 89 c3 mov %rax,%rbx - 416ff8: 74 b8 je 416fb2 - 416ffa: a9 ff ff ff 03 test $0x3ffffff,%eax - 416fff: 0f 84 ef fe ff ff je 416ef4 - 417005: 0f 1f 00 nopl (%rax) - 417008: be 00 00 00 04 mov $0x4000000,%esi - 41700d: 48 89 df mov %rbx,%rdi - 417010: e8 9b 8c 02 00 callq 43fcb0 <__munmap> - 417015: 31 c0 xor %eax,%eax - 417017: e9 fc fe ff ff jmpq 416f18 - 41701c: 0f 1f 40 00 nopl 0x0(%rax) - -0000000000417020 : - 417020: 41 55 push %r13 - 417022: 41 54 push %r12 - 417024: 55 push %rbp - 417025: 53 push %rbx - 417026: 48 83 ec 08 sub $0x8,%rsp - 41702a: 48 8b 57 08 mov 0x8(%rdi),%rdx - 41702e: 48 8b 05 4b 41 2b 00 mov 0x2b414b(%rip),%rax # 6cb180 <_dl_pagesize> - 417035: 48 8b 2f mov (%rdi),%rbp - 417038: 49 89 d5 mov %rdx,%r13 - 41703b: 49 83 e5 f8 and $0xfffffffffffffff8,%r13 - 41703f: 83 e2 02 and $0x2,%edx - 417042: 0f 84 c5 00 00 00 je 41710d - 417048: 4e 8d 64 2d 00 lea 0x0(%rbp,%r13,1),%r12 - 41704d: 48 8d 50 ff lea -0x1(%rax),%rdx - 417051: 4c 85 e2 test %r12,%rdx - 417054: 0f 85 9a 00 00 00 jne 4170f4 - 41705a: 48 8d 5c 28 07 lea 0x7(%rax,%rbp,1),%rbx - 41705f: 48 f7 d8 neg %rax - 417062: 48 01 f3 add %rsi,%rbx - 417065: 48 21 c3 and %rax,%rbx - 417068: 49 39 dc cmp %rbx,%r12 - 41706b: 74 6f je 4170dc - 41706d: 48 29 ef sub %rbp,%rdi - 417070: 31 c0 xor %eax,%eax - 417072: b9 01 00 00 00 mov $0x1,%ecx - 417077: 48 89 da mov %rbx,%rdx - 41707a: 4c 89 e6 mov %r12,%rsi - 41707d: e8 ce b4 02 00 callq 442550 <__mremap> - 417082: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 417086: 74 68 je 4170f0 - 417088: 48 8d 3c 28 lea (%rax,%rbp,1),%rdi - 41708c: 40 f6 c7 0f test $0xf,%dil - 417090: 0f 85 a9 00 00 00 jne 41713f - 417096: 48 3b 2f cmp (%rdi),%rbp - 417099: 0f 85 87 00 00 00 jne 417126 - 41709f: 48 89 d8 mov %rbx,%rax - 4170a2: 48 29 e8 sub %rbp,%rax - 4170a5: 48 83 c8 02 or $0x2,%rax - 4170a9: 48 89 47 08 mov %rax,0x8(%rdi) - 4170ad: 48 89 d8 mov %rbx,%rax - 4170b0: 4c 29 e8 sub %r13,%rax - 4170b3: 48 29 e8 sub %rbp,%rax - 4170b6: f0 48 0f c1 05 19 37 lock xadd %rax,0x2b3719(%rip) # 6ca7d8 - 4170bd: 2b 00 - 4170bf: 4c 29 e3 sub %r12,%rbx - 4170c2: 48 01 c3 add %rax,%rbx - 4170c5: 48 8b 05 14 37 2b 00 mov 0x2b3714(%rip),%rax # 6ca7e0 - 4170cc: 48 39 c3 cmp %rax,%rbx - 4170cf: 76 0b jbe 4170dc - 4170d1: f0 48 0f b1 1d 06 37 lock cmpxchg %rbx,0x2b3706(%rip) # 6ca7e0 - 4170d8: 2b 00 - 4170da: 75 e9 jne 4170c5 - 4170dc: 48 89 f8 mov %rdi,%rax - 4170df: 48 83 c4 08 add $0x8,%rsp - 4170e3: 5b pop %rbx - 4170e4: 5d pop %rbp - 4170e5: 41 5c pop %r12 - 4170e7: 41 5d pop %r13 - 4170e9: c3 retq - 4170ea: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4170f0: 31 c0 xor %eax,%eax - 4170f2: eb eb jmp 4170df - 4170f4: b9 68 2e 4a 00 mov $0x4a2e68,%ecx - 4170f9: ba 34 0b 00 00 mov $0xb34,%edx - 4170fe: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 417103: bf 48 23 4a 00 mov $0x4a2348,%edi - 417108: e8 13 fd ff ff callq 416e20 <__malloc_assert> - 41710d: b9 68 2e 4a 00 mov $0x4a2e68,%ecx - 417112: ba 33 0b 00 00 mov $0xb33,%edx - 417117: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 41711c: bf d1 1f 4a 00 mov $0x4a1fd1,%edi - 417121: e8 fa fc ff ff callq 416e20 <__malloc_assert> - 417126: b9 68 2e 4a 00 mov $0x4a2e68,%ecx - 41712b: ba 47 0b 00 00 mov $0xb47,%edx - 417130: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 417135: bf 01 20 4a 00 mov $0x4a2001,%edi - 41713a: e8 e1 fc ff ff callq 416e20 <__malloc_assert> - 41713f: b9 68 2e 4a 00 mov $0x4a2e68,%ecx - 417144: ba 45 0b 00 00 mov $0xb45,%edx - 417149: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 41714e: bf e6 1f 4a 00 mov $0x4a1fe6,%edi - 417153: e8 c8 fc ff ff callq 416e20 <__malloc_assert> - 417158: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 41715f: 00 - -0000000000417160 : - 417160: 48 83 ec 08 sub $0x8,%rsp - 417164: 48 8b 15 bd 54 2b 00 mov 0x2b54bd(%rip),%rdx # 6cc628 - 41716b: 49 c7 c1 d8 ff ff ff mov $0xffffffffffffffd8,%r9 - 417172: 48 85 d2 test %rdx,%rdx - 417175: 64 4d 8b 01 mov %fs:(%r9),%r8 - 417179: 0f 84 05 01 00 00 je 417284 - 41717f: be 01 00 00 00 mov $0x1,%esi - 417184: 31 c0 xor %eax,%eax - 417186: 83 3d 2f 60 2b 00 00 cmpl $0x0,0x2b602f(%rip) # 6cd1bc <__libc_multiple_threads> - 41718d: 74 0c je 41719b - 41718f: f0 0f b1 35 99 54 2b lock cmpxchg %esi,0x2b5499(%rip) # 6cc630 - 417196: 00 - 417197: 75 0b jne 4171a4 - 417199: eb 23 jmp 4171be - 41719b: 0f b1 35 8e 54 2b 00 cmpxchg %esi,0x2b548e(%rip) # 6cc630 - 4171a2: 74 1a je 4171be - 4171a4: 48 8d 3d 85 54 2b 00 lea 0x2b5485(%rip),%rdi # 6cc630 - 4171ab: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 4171b2: e8 19 b4 02 00 callq 4425d0 <__lll_lock_wait_private> - 4171b7: 48 81 c4 80 00 00 00 add $0x80,%rsp - 4171be: 48 8b 15 63 54 2b 00 mov 0x2b5463(%rip),%rdx # 6cc628 - 4171c5: 48 85 d2 test %rdx,%rdx - 4171c8: 74 47 je 417211 - 4171ca: 48 83 ba 78 08 00 00 cmpq $0x0,0x878(%rdx) - 4171d1: 00 - 4171d2: 48 8b 82 70 08 00 00 mov 0x870(%rdx),%rax - 4171d9: 48 89 05 48 54 2b 00 mov %rax,0x2b5448(%rip) # 6cc628 - 4171e0: 0f 85 a6 00 00 00 jne 41728c - 4171e6: 4d 85 c0 test %r8,%r8 - 4171e9: 48 c7 82 78 08 00 00 movq $0x1,0x878(%rdx) - 4171f0: 01 00 00 00 - 4171f4: 74 1b je 417211 - 4171f6: 49 8b 80 78 08 00 00 mov 0x878(%r8),%rax - 4171fd: 48 85 c0 test %rax,%rax - 417200: 0f 84 9f 00 00 00 je 4172a5 - 417206: 48 83 e8 01 sub $0x1,%rax - 41720a: 49 89 80 78 08 00 00 mov %rax,0x878(%r8) - 417211: 83 3d a4 5f 2b 00 00 cmpl $0x0,0x2b5fa4(%rip) # 6cd1bc <__libc_multiple_threads> - 417218: 74 0b je 417225 - 41721a: f0 ff 0d 0f 54 2b 00 lock decl 0x2b540f(%rip) # 6cc630 - 417221: 75 0a jne 41722d - 417223: eb 22 jmp 417247 - 417225: ff 0d 05 54 2b 00 decl 0x2b5405(%rip) # 6cc630 - 41722b: 74 1a je 417247 - 41722d: 48 8d 3d fc 53 2b 00 lea 0x2b53fc(%rip),%rdi # 6cc630 - 417234: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41723b: e8 c0 b3 02 00 callq 442600 <__lll_unlock_wake_private> - 417240: 48 81 c4 80 00 00 00 add $0x80,%rsp - 417247: 48 85 d2 test %rdx,%rdx - 41724a: 74 38 je 417284 - 41724c: 90 nop - 41724d: be 01 00 00 00 mov $0x1,%esi - 417252: 31 c0 xor %eax,%eax - 417254: 83 3d 61 5f 2b 00 00 cmpl $0x0,0x2b5f61(%rip) # 6cd1bc <__libc_multiple_threads> - 41725b: 74 08 je 417265 - 41725d: f0 0f b1 32 lock cmpxchg %esi,(%rdx) - 417261: 75 07 jne 41726a - 417263: eb 1b jmp 417280 - 417265: 0f b1 32 cmpxchg %esi,(%rdx) - 417268: 74 16 je 417280 - 41726a: 48 8d 3a lea (%rdx),%rdi - 41726d: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 417274: e8 57 b3 02 00 callq 4425d0 <__lll_lock_wait_private> - 417279: 48 81 c4 80 00 00 00 add $0x80,%rsp - 417280: 64 49 89 11 mov %rdx,%fs:(%r9) - 417284: 48 89 d0 mov %rdx,%rax - 417287: 48 83 c4 08 add $0x8,%rsp - 41728b: c3 retq - 41728c: b9 38 2e 4a 00 mov $0x4a2e38,%ecx - 417291: ba d4 02 00 00 mov $0x2d4,%edx - 417296: be a8 1f 4a 00 mov $0x4a1fa8,%esi - 41729b: bf 1a 20 4a 00 mov $0x4a201a,%edi - 4172a0: e8 7b fb ff ff callq 416e20 <__malloc_assert> - 4172a5: e8 29 92 fe ff callq 4004d3 - 4172aa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - -00000000004172b0 : - 4172b0: 41 56 push %r14 - 4172b2: 41 55 push %r13 - 4172b4: 41 54 push %r12 - 4172b6: 55 push %rbp - 4172b7: 49 89 f4 mov %rsi,%r12 - 4172ba: 53 push %rbx - 4172bb: 89 fb mov %edi,%ebx - 4172bd: 48 89 d7 mov %rdx,%rdi - 4172c0: 48 83 ec 20 sub $0x20,%rsp - 4172c4: 48 85 c9 test %rcx,%rcx - 4172c7: 74 04 je 4172cd - 4172c9: 83 49 04 04 orl $0x4,0x4(%rcx) - 4172cd: 89 d8 mov %ebx,%eax - 4172cf: 83 e0 05 and $0x5,%eax - 4172d2: 83 f8 05 cmp $0x5,%eax - 4172d5: 0f 84 a5 00 00 00 je 417380 - 4172db: f6 c3 01 test $0x1,%bl - 4172de: 75 20 jne 417300 - 4172e0: 83 e3 02 and $0x2,%ebx - 4172e3: 0f 85 b0 00 00 00 jne 417399 - 4172e9: 48 83 c4 20 add $0x20,%rsp - 4172ed: 5b pop %rbx - 4172ee: 5d pop %rbp - 4172ef: 41 5c pop %r12 - 4172f1: 41 5d pop %r13 - 4172f3: 41 5e pop %r14 - 4172f5: c3 retq - 4172f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4172fd: 00 00 00 - 417300: 48 8d 74 24 10 lea 0x10(%rsp),%rsi - 417305: 31 c9 xor %ecx,%ecx - 417307: ba 10 00 00 00 mov $0x10,%edx - 41730c: c6 44 24 10 00 movb $0x0,0x10(%rsp) - 417311: e8 9a ab 03 00 callq 451eb0 <_itoa_word> - 417316: 48 39 e0 cmp %rsp,%rax - 417319: 48 89 c5 mov %rax,%rbp - 41731c: 76 25 jbe 417343 - 41731e: 48 89 c2 mov %rax,%rdx - 417321: 48 89 c7 mov %rax,%rdi - 417324: be 30 00 00 00 mov $0x30,%esi - 417329: 48 29 e2 sub %rsp,%rdx - 41732c: 4c 8d 70 ff lea -0x1(%rax),%r14 - 417330: 48 29 d7 sub %rdx,%rdi - 417333: e8 18 90 fe ff callq 400350 <__rela_iplt_end+0x88> - 417338: 48 8d 44 24 ff lea -0x1(%rsp),%rax - 41733d: 4c 29 f0 sub %r14,%rax - 417340: 48 01 c5 add %rax,%rbp - 417343: 48 8b 05 76 5f 2b 00 mov 0x2b5f76(%rip),%rax # 6cd2c0 <__libc_argv> - 41734a: ba 38 20 4a 00 mov $0x4a2038,%edx - 41734f: 49 89 e8 mov %rbp,%r8 - 417352: 4c 89 e1 mov %r12,%rcx - 417355: be a8 23 4a 00 mov $0x4a23a8,%esi - 41735a: 48 8b 00 mov (%rax),%rax - 41735d: 48 85 c0 test %rax,%rax - 417360: 48 0f 45 d0 cmovne %rax,%rdx - 417364: 83 e3 02 and $0x2,%ebx - 417367: 31 c0 xor %eax,%eax - 417369: 89 df mov %ebx,%edi - 41736b: e8 50 a2 ff ff callq 4115c0 <__libc_message> - 417370: 48 83 c4 20 add $0x20,%rsp - 417374: 5b pop %rbx - 417375: 5d pop %rbp - 417376: 41 5c pop %r12 - 417378: 41 5d pop %r13 - 41737a: 41 5e pop %r14 - 41737c: c3 retq - 41737d: 0f 1f 00 nopl (%rax) - 417380: 83 e3 02 and $0x2,%ebx - 417383: 4c 89 e2 mov %r12,%rdx - 417386: be 3c ca 4b 00 mov $0x4bca3c,%esi - 41738b: 89 df mov %ebx,%edi - 41738d: 31 c0 xor %eax,%eax - 41738f: e8 2c a2 ff ff callq 4115c0 <__libc_message> - 417394: e9 50 ff ff ff jmpq 4172e9 - 417399: e8 62 68 ff ff callq 40dc00 - 41739e: 66 90 xchg %ax,%ax - -00000000004173a0 : - 4173a0: 48 8b 06 mov (%rsi),%rax - 4173a3: 41 56 push %r14 - 4173a5: 41 55 push %r13 - 4173a7: 41 54 push %r12 - 4173a9: 55 push %rbp - 4173aa: 53 push %rbx - 4173ab: 48 8b 68 08 mov 0x8(%rax),%rbp - 4173af: 48 83 e5 f8 and $0xfffffffffffffff8,%rbp - 4173b3: 48 8d 45 df lea -0x21(%rbp),%rax - 4173b7: 48 39 f8 cmp %rdi,%rax - 4173ba: 76 12 jbe 4173ce - 4173bc: 48 8b 1d bd 3d 2b 00 mov 0x2b3dbd(%rip),%rbx # 6cb180 <_dl_pagesize> - 4173c3: 48 29 f8 sub %rdi,%rax - 4173c6: 48 f7 db neg %rbx - 4173c9: 48 21 c3 and %rax,%rbx - 4173cc: 75 12 jne 4173e0 - 4173ce: 31 c0 xor %eax,%eax - 4173d0: 5b pop %rbx - 4173d1: 5d pop %rbp - 4173d2: 41 5c pop %r12 - 4173d4: 41 5d pop %r13 - 4173d6: 41 5e pop %r14 - 4173d8: c3 retq - 4173d9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4173e0: 49 89 f4 mov %rsi,%r12 - 4173e3: 31 ff xor %edi,%edi - 4173e5: 49 89 d5 mov %rdx,%r13 - 4173e8: ff 15 a2 3c 2b 00 callq *0x2b3ca2(%rip) # 6cb090 <__morecore> - 4173ee: 49 89 c6 mov %rax,%r14 - 4173f1: 48 89 e8 mov %rbp,%rax - 4173f4: 49 03 04 24 add (%r12),%rax - 4173f8: 49 39 c6 cmp %rax,%r14 - 4173fb: 75 d1 jne 4173ce - 4173fd: 48 89 df mov %rbx,%rdi - 417400: 48 f7 df neg %rdi - 417403: ff 15 87 3c 2b 00 callq *0x2b3c87(%rip) # 6cb090 <__morecore> - 417409: 48 8b 05 d0 51 2b 00 mov 0x2b51d0(%rip),%rax # 6cc5e0 <__after_morecore_hook> - 417410: 48 85 c0 test %rax,%rax - 417413: 75 2d jne 417442 - 417415: 31 ff xor %edi,%edi - 417417: ff 15 73 3c 2b 00 callq *0x2b3c73(%rip) # 6cb090 <__morecore> - 41741d: 90 nop - 41741e: 48 85 c0 test %rax,%rax - 417421: 74 ab je 4173ce - 417423: 49 29 c6 sub %rax,%r14 - 417426: 74 a6 je 4173ce - 417428: 49 8b 04 24 mov (%r12),%rax - 41742c: 4c 29 f5 sub %r14,%rbp - 41742f: 4d 29 75 00 sub %r14,0x0(%r13) - 417433: 48 83 cd 01 or $0x1,%rbp - 417437: 48 89 68 08 mov %rbp,0x8(%rax) - 41743b: b8 01 00 00 00 mov $0x1,%eax - 417440: eb 8e jmp 4173d0 - 417442: ff d0 callq *%rax - 417444: eb cf jmp 417415 - 417446: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41744d: 00 00 00 - -0000000000417450 : - 417450: 55 push %rbp - 417451: 53 push %rbx - 417452: 48 89 fd mov %rdi,%rbp - 417455: 48 89 f3 mov %rsi,%rbx - 417458: 48 83 ec 08 sub $0x8,%rsp - 41745c: 48 8b 05 9d 51 2b 00 mov 0x2b519d(%rip),%rax # 6cc600 - 417463: 48 85 c0 test %rax,%rax - 417466: 75 17 jne 41747f - 417468: 48 8b 05 51 33 2b 00 mov 0x2b3351(%rip),%rax # 6ca7c0 - 41746f: 48 85 c0 test %rax,%rax - 417472: 0f 84 00 02 00 00 je 417678 - 417478: 48 89 05 81 51 2b 00 mov %rax,0x2b5181(%rip) # 6cc600 - 41747f: 48 8b 15 e2 32 2b 00 mov 0x2b32e2(%rip),%rdx # 6ca768 - 417486: 48 83 e8 01 sub $0x1,%rax - 41748a: 48 39 d0 cmp %rdx,%rax - 41748d: 0f 83 50 02 00 00 jae 4176e3 - 417493: 48 8b 15 5e 51 2b 00 mov 0x2b515e(%rip),%rdx # 6cc5f8 - 41749a: 48 85 d2 test %rdx,%rdx - 41749d: 0f 84 2b 02 00 00 je 4176ce - 4174a3: 48 89 d1 mov %rdx,%rcx - 4174a6: be 01 00 00 00 mov $0x1,%esi - 4174ab: eb 33 jmp 4174e0 - 4174ad: 0f 1f 00 nopl (%rax) - 4174b0: 83 3d 05 5d 2b 00 00 cmpl $0x0,0x2b5d05(%rip) # 6cd1bc <__libc_multiple_threads> - 4174b7: 74 06 je 4174bf - 4174b9: f0 0f b1 32 lock cmpxchg %esi,(%rdx) - 4174bd: eb 03 jmp 4174c2 - 4174bf: 0f b1 32 cmpxchg %esi,(%rdx) - 4174c2: 85 c0 test %eax,%eax - 4174c4: 0f 84 95 00 00 00 je 41755f - 4174ca: 48 8b 05 27 51 2b 00 mov 0x2b5127(%rip),%rax # 6cc5f8 - 4174d1: 48 8b 92 68 08 00 00 mov 0x868(%rdx),%rdx - 4174d8: 48 39 c2 cmp %rax,%rdx - 4174db: 48 89 c1 mov %rax,%rcx - 4174de: 74 1a je 4174fa - 4174e0: 8b 42 04 mov 0x4(%rdx),%eax - 4174e3: 83 e0 04 and $0x4,%eax - 4174e6: 74 c8 je 4174b0 - 4174e8: 48 8b 92 68 08 00 00 mov 0x868(%rdx),%rdx - 4174ef: 48 89 c8 mov %rcx,%rax - 4174f2: 48 89 c1 mov %rax,%rcx - 4174f5: 48 39 c2 cmp %rax,%rdx - 4174f8: 75 e6 jne 4174e0 - 4174fa: 48 39 c3 cmp %rax,%rbx - 4174fd: 0f 84 13 02 00 00 je 417716 - 417503: 48 89 c2 mov %rax,%rdx - 417506: eb 18 jmp 417520 - 417508: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 41750f: 00 - 417510: 48 8b 92 68 08 00 00 mov 0x868(%rdx),%rdx - 417517: 48 39 c2 cmp %rax,%rdx - 41751a: 0f 84 88 01 00 00 je 4176a8 - 417520: f6 42 04 04 testb $0x4,0x4(%rdx) - 417524: 75 ea jne 417510 - 417526: 48 39 d3 cmp %rdx,%rbx - 417529: 74 e5 je 417510 - 41752b: 90 nop - 41752c: be 01 00 00 00 mov $0x1,%esi - 417531: 31 c0 xor %eax,%eax - 417533: 83 3d 82 5c 2b 00 00 cmpl $0x0,0x2b5c82(%rip) # 6cd1bc <__libc_multiple_threads> - 41753a: 74 08 je 417544 - 41753c: f0 0f b1 32 lock cmpxchg %esi,(%rdx) - 417540: 75 07 jne 417549 - 417542: eb 1b jmp 41755f - 417544: 0f b1 32 cmpxchg %esi,(%rdx) - 417547: 74 16 je 41755f - 417549: 48 8d 3a lea (%rdx),%rdi - 41754c: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 417553: e8 78 b0 02 00 callq 4425d0 <__lll_lock_wait_private> - 417558: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41755f: 49 c7 c0 d8 ff ff ff mov $0xffffffffffffffd8,%r8 - 417566: be 01 00 00 00 mov $0x1,%esi - 41756b: 31 c0 xor %eax,%eax - 41756d: 64 4d 8b 08 mov %fs:(%r8),%r9 - 417571: 83 3d 44 5c 2b 00 00 cmpl $0x0,0x2b5c44(%rip) # 6cd1bc <__libc_multiple_threads> - 417578: 74 0c je 417586 - 41757a: f0 0f b1 35 ae 50 2b lock cmpxchg %esi,0x2b50ae(%rip) # 6cc630 - 417581: 00 - 417582: 75 0b jne 41758f - 417584: eb 23 jmp 4175a9 - 417586: 0f b1 35 a3 50 2b 00 cmpxchg %esi,0x2b50a3(%rip) # 6cc630 - 41758d: 74 1a je 4175a9 - 41758f: 48 8d 3d 9a 50 2b 00 lea 0x2b509a(%rip),%rdi # 6cc630 - 417596: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41759d: e8 2e b0 02 00 callq 4425d0 <__lll_lock_wait_private> - 4175a2: 48 81 c4 80 00 00 00 add $0x80,%rsp - 4175a9: 4d 85 c9 test %r9,%r9 - 4175ac: 74 1b je 4175c9 - 4175ae: 49 8b 81 78 08 00 00 mov 0x878(%r9),%rax - 4175b5: 48 85 c0 test %rax,%rax - 4175b8: 0f 84 ff 03 00 00 je 4179bd - 4175be: 48 83 e8 01 sub $0x1,%rax - 4175c2: 49 89 81 78 08 00 00 mov %rax,0x878(%r9) - 4175c9: 48 8b 0d 58 50 2b 00 mov 0x2b5058(%rip),%rcx # 6cc628 - 4175d0: 48 85 c9 test %rcx,%rcx - 4175d3: 74 41 je 417616 - 4175d5: 48 83 b9 78 08 00 00 cmpq $0x0,0x878(%rcx) - 4175dc: 00 - 4175dd: 0f 85 ad 03 00 00 jne 417990 - 4175e3: 48 39 d1 cmp %rdx,%rcx - 4175e6: 75 22 jne 41760a - 4175e8: e9 51 01 00 00 jmpq 41773e - 4175ed: 0f 1f 00 nopl (%rax) - 4175f0: 48 83 b8 78 08 00 00 cmpq $0x0,0x878(%rax) - 4175f7: 00 - 4175f8: 0f 85 92 03 00 00 jne 417990 - 4175fe: 48 39 c2 cmp %rax,%rdx - 417601: 0f 84 b1 00 00 00 je 4176b8 - 417607: 48 89 c1 mov %rax,%rcx - 41760a: 48 8b 81 70 08 00 00 mov 0x870(%rcx),%rax - 417611: 48 85 c0 test %rax,%rax - 417614: 75 da jne 4175f0 - 417616: 48 83 82 78 08 00 00 addq $0x1,0x878(%rdx) - 41761d: 01 - 41761e: 83 3d 97 5b 2b 00 00 cmpl $0x0,0x2b5b97(%rip) # 6cd1bc <__libc_multiple_threads> - 417625: 74 0b je 417632 - 417627: f0 ff 0d 02 50 2b 00 lock decl 0x2b5002(%rip) # 6cc630 - 41762e: 75 0a jne 41763a - 417630: eb 22 jmp 417654 - 417632: ff 0d f8 4f 2b 00 decl 0x2b4ff8(%rip) # 6cc630 - 417638: 74 1a je 417654 - 41763a: 48 8d 3d ef 4f 2b 00 lea 0x2b4fef(%rip),%rdi # 6cc630 - 417641: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 417648: e8 b3 af 02 00 callq 442600 <__lll_unlock_wake_private> - 41764d: 48 81 c4 80 00 00 00 add $0x80,%rsp - 417654: 90 nop - 417655: 48 8b 82 68 08 00 00 mov 0x868(%rdx),%rax - 41765c: 64 49 89 10 mov %rdx,%fs:(%r8) - 417660: 48 89 05 91 4f 2b 00 mov %rax,0x2b4f91(%rip) # 6cc5f8 - 417667: 48 83 c4 08 add $0x8,%rsp - 41766b: 48 89 d0 mov %rdx,%rax - 41766e: 5b pop %rbx - 41766f: 5d pop %rbp - 417670: c3 retq - 417671: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 417678: 48 8b 15 e9 30 2b 00 mov 0x2b30e9(%rip),%rdx # 6ca768 - 41767f: 48 39 15 32 31 2b 00 cmp %rdx,0x2b3132(%rip) # 6ca7b8 - 417686: 0f 83 fa fd ff ff jae 417486 - 41768c: e8 af a9 02 00 callq 442040 <__get_nprocs> - 417691: 85 c0 test %eax,%eax - 417693: 0f 8e 89 00 00 00 jle 417722 - 417699: c1 e0 03 shl $0x3,%eax - 41769c: 48 98 cltq - 41769e: e9 d5 fd ff ff jmpq 417478 - 4176a3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4176a8: 48 83 c4 08 add $0x8,%rsp - 4176ac: 31 d2 xor %edx,%edx - 4176ae: 48 89 d0 mov %rdx,%rax - 4176b1: 5b pop %rbx - 4176b2: 5d pop %rbp - 4176b3: c3 retq - 4176b4: 0f 1f 40 00 nopl 0x0(%rax) - 4176b8: 48 81 c1 70 08 00 00 add $0x870,%rcx - 4176bf: 48 8b 80 70 08 00 00 mov 0x870(%rax),%rax - 4176c6: 48 89 01 mov %rax,(%rcx) - 4176c9: e9 48 ff ff ff jmpq 417616 - 4176ce: 48 c7 05 1f 4f 2b 00 movq $0x6ca800,0x2b4f1f(%rip) # 6cc5f8 - 4176d5: 00 a8 6c 00 - 4176d9: ba 00 a8 6c 00 mov $0x6ca800,%edx - 4176de: e9 c0 fd ff ff jmpq 4174a3 - 4176e3: 48 8d 4a 01 lea 0x1(%rdx),%rcx - 4176e7: 48 89 d0 mov %rdx,%rax - 4176ea: 64 83 3c 25 18 00 00 cmpl $0x0,%fs:0x18 - 4176f1: 00 00 - 4176f3: 74 01 je 4176f6 - 4176f5: f0 48 0f b1 0d 6a 30 lock cmpxchg %rcx,0x2b306a(%rip) # 6ca768 - 4176fc: 2b 00 - 4176fe: 48 39 d0 cmp %rdx,%rax - 417701: 74 48 je 41774b - 417703: 48 8b 15 5e 30 2b 00 mov 0x2b305e(%rip),%rdx # 6ca768 - 41770a: 48 8b 05 ef 4e 2b 00 mov 0x2b4eef(%rip),%rax # 6cc600 - 417711: e9 70 fd ff ff jmpq 417486 - 417716: 48 8b 83 68 08 00 00 mov 0x868(%rbx),%rax - 41771d: e9 e1 fd ff ff jmpq 417503 - 417722: 48 c7 05 d3 4e 2b 00 movq $0x10,0x2b4ed3(%rip) # 6cc600 - 417729: 10 00 00 00 - 41772d: 48 8b 15 34 30 2b 00 mov 0x2b3034(%rip),%rdx # 6ca768 - 417734: b8 10 00 00 00 mov $0x10,%eax - 417739: e9 48 fd ff ff jmpq 417486 - 41773e: 48 89 d0 mov %rdx,%rax - 417741: b9 28 c6 6c 00 mov $0x6cc628,%ecx - 417746: e9 74 ff ff ff jmpq 4176bf - 41774b: 48 8b 35 56 30 2b 00 mov 0x2b3056(%rip),%rsi # 6ca7a8 - 417752: 48 8d bd c0 08 00 00 lea 0x8c0(%rbp),%rdi - 417759: e8 22 f7 ff ff callq 416e80 - 41775e: 48 85 c0 test %rax,%rax - 417761: 49 89 c0 mov %rax,%r8 - 417764: 0f 84 58 02 00 00 je 4179c2 - 41776a: 49 8d 50 20 lea 0x20(%r8),%rdx - 41776e: 49 8d 40 78 lea 0x78(%r8),%rax - 417772: 49 8d 88 68 08 00 00 lea 0x868(%r8),%rcx - 417779: 49 89 10 mov %rdx,(%r8) - 41777c: 0f 1f 40 00 nopl 0x0(%rax) - 417780: 48 89 40 18 mov %rax,0x18(%rax) - 417784: 48 89 40 10 mov %rax,0x10(%rax) - 417788: 48 83 c0 10 add $0x10,%rax - 41778c: 48 39 c8 cmp %rcx,%rax - 41778f: 75 ef jne 417780 - 417791: 48 81 fa 00 a8 6c 00 cmp $0x6ca800,%rdx - 417798: 0f 84 0b 02 00 00 je 4179a9 - 41779e: 41 8b 40 24 mov 0x24(%r8),%eax - 4177a2: 83 c8 02 or $0x2,%eax - 4177a5: 83 c8 01 or $0x1,%eax - 4177a8: 4c 89 c6 mov %r8,%rsi - 4177ab: 49 c7 80 98 08 00 00 movq $0x1,0x898(%r8) - 4177b2: 01 00 00 00 - 4177b6: 41 89 40 24 mov %eax,0x24(%r8) - 4177ba: 49 8b 40 10 mov 0x10(%r8),%rax - 4177be: 49 8d 88 b0 08 00 00 lea 0x8b0(%r8),%rcx - 4177c5: 48 01 05 4c 4e 2b 00 add %rax,0x2b4e4c(%rip) # 6cc618 - 4177cc: 83 e6 0f and $0xf,%esi - 4177cf: 49 89 80 a8 08 00 00 mov %rax,0x8a8(%r8) - 4177d6: 49 89 80 a0 08 00 00 mov %rax,0x8a0(%r8) - 4177dd: 74 07 je 4177e6 - 4177df: 48 29 f1 sub %rsi,%rcx - 4177e2: 48 83 c1 10 add $0x10,%rcx - 4177e6: 4c 01 c0 add %r8,%rax - 4177e9: 49 89 48 78 mov %rcx,0x78(%r8) - 4177ed: 48 29 c8 sub %rcx,%rax - 4177f0: 48 83 c8 01 or $0x1,%rax - 4177f4: 48 89 41 08 mov %rax,0x8(%rcx) - 4177f8: 90 nop - 4177f9: 48 c7 c0 d8 ff ff ff mov $0xffffffffffffffd8,%rax - 417800: 41 b9 01 00 00 00 mov $0x1,%r9d - 417806: 45 31 d2 xor %r10d,%r10d - 417809: 41 c7 40 20 00 00 00 movl $0x0,0x20(%r8) - 417810: 00 - 417811: 44 89 ce mov %r9d,%esi - 417814: 64 48 8b 18 mov %fs:(%rax),%rbx - 417818: 64 48 89 10 mov %rdx,%fs:(%rax) - 41781c: 44 89 d0 mov %r10d,%eax - 41781f: 83 3d 96 59 2b 00 00 cmpl $0x0,0x2b5996(%rip) # 6cd1bc <__libc_multiple_threads> - 417826: 74 0c je 417834 - 417828: f0 0f b1 35 f0 4d 2b lock cmpxchg %esi,0x2b4df0(%rip) # 6cc620 - 41782f: 00 - 417830: 75 0b jne 41783d - 417832: eb 23 jmp 417857 - 417834: 0f b1 35 e5 4d 2b 00 cmpxchg %esi,0x2b4de5(%rip) # 6cc620 - 41783b: 74 1a je 417857 - 41783d: 48 8d 3d dc 4d 2b 00 lea 0x2b4ddc(%rip),%rdi # 6cc620 - 417844: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41784b: e8 80 ad 02 00 callq 4425d0 <__lll_lock_wait_private> - 417850: 48 81 c4 80 00 00 00 add $0x80,%rsp - 417857: 48 8b 05 0a 38 2b 00 mov 0x2b380a(%rip),%rax # 6cb068 - 41785e: 49 89 80 88 08 00 00 mov %rax,0x888(%r8) - 417865: 48 89 15 fc 37 2b 00 mov %rdx,0x2b37fc(%rip) # 6cb068 - 41786c: 83 3d 49 59 2b 00 00 cmpl $0x0,0x2b5949(%rip) # 6cd1bc <__libc_multiple_threads> - 417873: 74 0b je 417880 - 417875: f0 ff 0d a4 4d 2b 00 lock decl 0x2b4da4(%rip) # 6cc620 - 41787c: 75 0a jne 417888 - 41787e: eb 22 jmp 4178a2 - 417880: ff 0d 9a 4d 2b 00 decl 0x2b4d9a(%rip) # 6cc620 - 417886: 74 1a je 4178a2 - 417888: 48 8d 3d 91 4d 2b 00 lea 0x2b4d91(%rip),%rdi # 6cc620 - 41788f: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 417896: e8 65 ad 02 00 callq 442600 <__lll_unlock_wake_private> - 41789b: 48 81 c4 80 00 00 00 add $0x80,%rsp - 4178a2: 44 89 ce mov %r9d,%esi - 4178a5: 44 89 d0 mov %r10d,%eax - 4178a8: 83 3d 0d 59 2b 00 00 cmpl $0x0,0x2b590d(%rip) # 6cd1bc <__libc_multiple_threads> - 4178af: 74 0c je 4178bd - 4178b1: f0 0f b1 35 77 4d 2b lock cmpxchg %esi,0x2b4d77(%rip) # 6cc630 - 4178b8: 00 - 4178b9: 75 0b jne 4178c6 - 4178bb: eb 23 jmp 4178e0 - 4178bd: 0f b1 35 6c 4d 2b 00 cmpxchg %esi,0x2b4d6c(%rip) # 6cc630 - 4178c4: 74 1a je 4178e0 - 4178c6: 48 8d 3d 63 4d 2b 00 lea 0x2b4d63(%rip),%rdi # 6cc630 - 4178cd: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 4178d4: e8 f7 ac 02 00 callq 4425d0 <__lll_lock_wait_private> - 4178d9: 48 81 c4 80 00 00 00 add $0x80,%rsp - 4178e0: 48 85 db test %rbx,%rbx - 4178e3: 74 1b je 417900 - 4178e5: 48 8b 83 78 08 00 00 mov 0x878(%rbx),%rax - 4178ec: 48 85 c0 test %rax,%rax - 4178ef: 0f 84 c8 00 00 00 je 4179bd - 4178f5: 48 83 e8 01 sub $0x1,%rax - 4178f9: 48 89 83 78 08 00 00 mov %rax,0x878(%rbx) - 417900: 83 3d b5 58 2b 00 00 cmpl $0x0,0x2b58b5(%rip) # 6cd1bc <__libc_multiple_threads> - 417907: 74 0b je 417914 - 417909: f0 ff 0d 20 4d 2b 00 lock decl 0x2b4d20(%rip) # 6cc630 - 417910: 75 0a jne 41791c - 417912: eb 22 jmp 417936 - 417914: ff 0d 16 4d 2b 00 decl 0x2b4d16(%rip) # 6cc630 - 41791a: 74 1a je 417936 - 41791c: 48 8d 3d 0d 4d 2b 00 lea 0x2b4d0d(%rip),%rdi # 6cc630 - 417923: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41792a: e8 d1 ac 02 00 callq 442600 <__lll_unlock_wake_private> - 41792f: 48 81 c4 80 00 00 00 add $0x80,%rsp - 417936: be 01 00 00 00 mov $0x1,%esi - 41793b: 31 c0 xor %eax,%eax - 41793d: 83 3d 78 58 2b 00 00 cmpl $0x0,0x2b5878(%rip) # 6cd1bc <__libc_multiple_threads> - 417944: 74 08 je 41794e - 417946: f0 0f b1 32 lock cmpxchg %esi,(%rdx) - 41794a: 75 07 jne 417953 - 41794c: eb 1b jmp 417969 - 41794e: 0f b1 32 cmpxchg %esi,(%rdx) - 417951: 74 16 je 417969 - 417953: 48 8d 3a lea (%rdx),%rdi - 417956: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41795d: e8 6e ac 02 00 callq 4425d0 <__lll_lock_wait_private> - 417962: 48 81 c4 80 00 00 00 add $0x80,%rsp - 417969: 48 85 d2 test %rdx,%rdx - 41796c: 0f 85 f5 fc ff ff jne 417667 - 417972: 64 83 3c 25 18 00 00 cmpl $0x0,%fs:0x18 - 417979: 00 00 - 41797b: 74 01 je 41797e - 41797d: f0 48 ff 0d e3 2d 2b lock decq 0x2b2de3(%rip) # 6ca768 - 417984: 00 - 417985: 31 d2 xor %edx,%edx - 417987: e9 db fc ff ff jmpq 417667 - 41798c: 0f 1f 40 00 nopl 0x0(%rax) - 417990: b9 80 2f 4a 00 mov $0x4a2f80,%ecx - 417995: ba ee 02 00 00 mov $0x2ee,%edx - 41799a: be a8 1f 4a 00 mov $0x4a1fa8,%esi - 41799f: bf 42 20 4a 00 mov $0x4a2042,%edi - 4179a4: e8 77 f4 ff ff callq 416e20 <__malloc_assert> - 4179a9: 48 c7 05 84 4c 2b 00 movq $0x80,0x2b4c84(%rip) # 6cc638 - 4179b0: 80 00 00 00 - 4179b4: 41 8b 40 24 mov 0x24(%r8),%eax - 4179b8: e9 e8 fd ff ff jmpq 4177a5 - 4179bd: e8 11 8b fe ff callq 4004d3 - 4179c2: 48 8b 35 df 2d 2b 00 mov 0x2b2ddf(%rip),%rsi # 6ca7a8 - 4179c9: bf c0 08 00 00 mov $0x8c0,%edi - 4179ce: e8 ad f4 ff ff callq 416e80 - 4179d3: 48 85 c0 test %rax,%rax - 4179d6: 49 89 c0 mov %rax,%r8 - 4179d9: 0f 85 8b fd ff ff jne 41776a - 4179df: eb 91 jmp 417972 - 4179e1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4179e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4179ed: 00 00 00 - -00000000004179f0 : - 4179f0: 90 nop - 4179f1: 48 81 ff 00 a8 6c 00 cmp $0x6ca800,%rdi - 4179f8: 0f 84 8a 00 00 00 je 417a88 - 4179fe: 48 89 fa mov %rdi,%rdx - 417a01: 83 3d b4 57 2b 00 00 cmpl $0x0,0x2b57b4(%rip) # 6cd1bc <__libc_multiple_threads> - 417a08: 74 07 je 417a11 - 417a0a: f0 ff 0a lock decl (%rdx) - 417a0d: 75 06 jne 417a15 - 417a0f: eb 1a jmp 417a2b - 417a11: ff 0a decl (%rdx) - 417a13: 74 16 je 417a2b - 417a15: 48 8d 3a lea (%rdx),%rdi - 417a18: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 417a1f: e8 dc ab 02 00 callq 442600 <__lll_unlock_wake_private> - 417a24: 48 81 c4 80 00 00 00 add $0x80,%rsp - 417a2b: 8b 05 d3 2d 2b 00 mov 0x2b2dd3(%rip),%eax # 6ca804 - 417a31: 83 e0 04 and $0x4,%eax - 417a34: 75 4a jne 417a80 - 417a36: be 01 00 00 00 mov $0x1,%esi - 417a3b: 83 3d 7a 57 2b 00 00 cmpl $0x0,0x2b577a(%rip) # 6cd1bc <__libc_multiple_threads> - 417a42: 74 0c je 417a50 - 417a44: f0 0f b1 35 b4 2d 2b lock cmpxchg %esi,0x2b2db4(%rip) # 6ca800 - 417a4b: 00 - 417a4c: 75 0b jne 417a59 - 417a4e: eb 23 jmp 417a73 - 417a50: 0f b1 35 a9 2d 2b 00 cmpxchg %esi,0x2b2da9(%rip) # 6ca800 - 417a57: 74 1a je 417a73 - 417a59: 48 8d 3d a0 2d 2b 00 lea 0x2b2da0(%rip),%rdi # 6ca800 - 417a60: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 417a67: e8 64 ab 02 00 callq 4425d0 <__lll_lock_wait_private> - 417a6c: 48 81 c4 80 00 00 00 add $0x80,%rsp - 417a73: b8 00 a8 6c 00 mov $0x6ca800,%eax - 417a78: c3 retq - 417a79: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 417a80: 31 c0 xor %eax,%eax - 417a82: c3 retq - 417a83: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 417a88: 53 push %rbx - 417a89: 48 89 f3 mov %rsi,%rbx - 417a8c: 83 3d 29 57 2b 00 00 cmpl $0x0,0x2b5729(%rip) # 6cd1bc <__libc_multiple_threads> - 417a93: 74 0b je 417aa0 - 417a95: f0 ff 0d 64 2d 2b 00 lock decl 0x2b2d64(%rip) # 6ca800 - 417a9c: 75 0a jne 417aa8 - 417a9e: eb 22 jmp 417ac2 - 417aa0: ff 0d 5a 2d 2b 00 decl 0x2b2d5a(%rip) # 6ca800 - 417aa6: 74 1a je 417ac2 - 417aa8: 48 8d 3d 51 2d 2b 00 lea 0x2b2d51(%rip),%rdi # 6ca800 - 417aaf: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 417ab6: e8 45 ab 02 00 callq 442600 <__lll_unlock_wake_private> - 417abb: 48 81 c4 80 00 00 00 add $0x80,%rsp - 417ac2: e8 99 f6 ff ff callq 417160 - 417ac7: 48 85 c0 test %rax,%rax - 417aca: 74 02 je 417ace - 417acc: 5b pop %rbx - 417acd: c3 retq - 417ace: 48 89 df mov %rbx,%rdi - 417ad1: be 00 a8 6c 00 mov $0x6ca800,%esi - 417ad6: 5b pop %rbx - 417ad7: e9 74 f9 ff ff jmpq 417450 - 417adc: 0f 1f 40 00 nopl 0x0(%rax) - -0000000000417ae0 : - 417ae0: 41 56 push %r14 - 417ae2: 41 55 push %r13 - 417ae4: 41 54 push %r12 - 417ae6: 55 push %rbp - 417ae7: 53 push %rbx - 417ae8: 48 83 ec 20 sub $0x20,%rsp - 417aec: 48 8b 3d 65 2d 2b 00 mov 0x2b2d65(%rip),%rdi # 6ca858 - 417af3: 48 8b 1d 86 36 2b 00 mov 0x2b3686(%rip),%rbx # 6cb180 <_dl_pagesize> - 417afa: 48 81 ff 58 a8 6c 00 cmp $0x6ca858,%rdi - 417b01: 0f 84 15 01 00 00 je 417c1c - 417b07: 48 8b 47 08 mov 0x8(%rdi),%rax - 417b0b: a8 02 test $0x2,%al - 417b0d: 75 11 jne 417b20 - 417b0f: 48 89 c2 mov %rax,%rdx - 417b12: 48 83 e2 f8 and $0xfffffffffffffff8,%rdx - 417b16: 48 83 fa 1f cmp $0x1f,%rdx - 417b1a: 0f 87 d0 00 00 00 ja 417bf0 - 417b20: 8b 05 de 2c 2b 00 mov 0x2b2cde(%rip),%eax # 6ca804 - 417b26: 8b 2d 44 2c 2b 00 mov 0x2b2c44(%rip),%ebp # 6ca770 - 417b2c: 83 c8 04 or $0x4,%eax - 417b2f: 89 05 cf 2c 2b 00 mov %eax,0x2b2ccf(%rip) # 6ca804 - 417b35: 89 e8 mov %ebp,%eax - 417b37: 83 e0 05 and $0x5,%eax - 417b3a: 83 f8 05 cmp $0x5,%eax - 417b3d: 0f 84 6d 01 00 00 je 417cb0 - 417b43: 40 f6 c5 01 test $0x1,%bpl - 417b47: 0f 85 e3 00 00 00 jne 417c30 - 417b4d: 83 e5 02 and $0x2,%ebp - 417b50: 0f 85 8d 01 00 00 jne 417ce3 - 417b56: 31 ff xor %edi,%edi - 417b58: ff 15 32 35 2b 00 callq *0x2b3532(%rip) # 6cb090 <__morecore> - 417b5e: 49 89 c5 mov %rax,%r13 - 417b61: 48 89 c5 mov %rax,%rbp - 417b64: 41 83 e5 0f and $0xf,%r13d - 417b68: 75 76 jne 417be0 - 417b6a: 48 8b 05 37 2c 2b 00 mov 0x2b2c37(%rip),%rax # 6ca7a8 - 417b71: 48 8d 53 ff lea -0x1(%rbx),%rdx - 417b75: 49 8d 44 05 20 lea 0x20(%r13,%rax,1),%rax - 417b7a: 48 8d 4c 05 00 lea 0x0(%rbp,%rax,1),%rcx - 417b7f: 48 01 c3 add %rax,%rbx - 417b82: 48 21 ca and %rcx,%rdx - 417b85: 48 29 d3 sub %rdx,%rbx - 417b88: 48 89 df mov %rbx,%rdi - 417b8b: ff 15 ff 34 2b 00 callq *0x2b34ff(%rip) # 6cb090 <__morecore> - 417b91: 48 85 c0 test %rax,%rax - 417b94: 49 89 c4 mov %rax,%r12 - 417b97: 0f 84 2e 01 00 00 je 417ccb - 417b9d: 48 8b 05 3c 4a 2b 00 mov 0x2b4a3c(%rip),%rax # 6cc5e0 <__after_morecore_hook> - 417ba4: 48 85 c0 test %rax,%rax - 417ba7: 74 02 je 417bab - 417ba9: ff d0 callq *%rax - 417bab: 4c 2b 25 3e 2c 2b 00 sub 0x2b2c3e(%rip),%r12 # 6ca7f0 - 417bb2: 4c 01 ed add %r13,%rbp - 417bb5: 31 c0 xor %eax,%eax - 417bb7: 48 89 2d 9a 2c 2b 00 mov %rbp,0x2b2c9a(%rip) # 6ca858 - 417bbe: 49 01 dc add %rbx,%r12 - 417bc1: 4c 29 eb sub %r13,%rbx - 417bc4: 48 83 cb 01 or $0x1,%rbx - 417bc8: 4c 89 25 b1 34 2b 00 mov %r12,0x2b34b1(%rip) # 6cb080 - 417bcf: 48 89 5d 08 mov %rbx,0x8(%rbp) - 417bd3: 48 83 c4 20 add $0x20,%rsp - 417bd7: 5b pop %rbx - 417bd8: 5d pop %rbp - 417bd9: 41 5c pop %r12 - 417bdb: 41 5d pop %r13 - 417bdd: 41 5e pop %r14 - 417bdf: c3 retq - 417be0: b8 10 00 00 00 mov $0x10,%eax - 417be5: 4c 29 e8 sub %r13,%rax - 417be8: 49 89 c5 mov %rax,%r13 - 417beb: e9 7a ff ff ff jmpq 417b6a - 417bf0: a8 01 test $0x1,%al - 417bf2: 0f 84 28 ff ff ff je 417b20 - 417bf8: 8b 05 06 2c 2b 00 mov 0x2b2c06(%rip),%eax # 6ca804 - 417bfe: a8 02 test $0x2,%al - 417c00: 75 1a jne 417c1c - 417c02: 48 8b 0d 77 34 2b 00 mov 0x2b3477(%rip),%rcx # 6cb080 - 417c09: 48 03 0d e0 2b 2b 00 add 0x2b2be0(%rip),%rcx # 6ca7f0 - 417c10: 48 01 fa add %rdi,%rdx - 417c13: 48 39 ca cmp %rcx,%rdx - 417c16: 0f 85 0a ff ff ff jne 417b26 - 417c1c: 48 83 c4 20 add $0x20,%rsp - 417c20: 31 c0 xor %eax,%eax - 417c22: 5b pop %rbx - 417c23: 5d pop %rbp - 417c24: 41 5c pop %r12 - 417c26: 41 5d pop %r13 - 417c28: 41 5e pop %r14 - 417c2a: c3 retq - 417c2b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 417c30: 48 8d 74 24 10 lea 0x10(%rsp),%rsi - 417c35: 31 c9 xor %ecx,%ecx - 417c37: ba 10 00 00 00 mov $0x10,%edx - 417c3c: c6 44 24 10 00 movb $0x0,0x10(%rsp) - 417c41: e8 6a a2 03 00 callq 451eb0 <_itoa_word> - 417c46: 48 39 e0 cmp %rsp,%rax - 417c49: 49 89 c4 mov %rax,%r12 - 417c4c: 76 25 jbe 417c73 - 417c4e: 48 89 c2 mov %rax,%rdx - 417c51: 48 89 c7 mov %rax,%rdi - 417c54: be 30 00 00 00 mov $0x30,%esi - 417c59: 48 29 e2 sub %rsp,%rdx - 417c5c: 4c 8d 70 ff lea -0x1(%rax),%r14 - 417c60: 48 29 d7 sub %rdx,%rdi - 417c63: e8 e8 86 fe ff callq 400350 <__rela_iplt_end+0x88> - 417c68: 48 8d 44 24 ff lea -0x1(%rsp),%rax - 417c6d: 4c 29 f0 sub %r14,%rax - 417c70: 49 01 c4 add %rax,%r12 - 417c73: 48 8b 05 46 56 2b 00 mov 0x2b5646(%rip),%rax # 6cd2c0 <__libc_argv> - 417c7a: 89 ef mov %ebp,%edi - 417c7c: ba 38 20 4a 00 mov $0x4a2038,%edx - 417c81: 4d 89 e0 mov %r12,%r8 - 417c84: b9 5b 20 4a 00 mov $0x4a205b,%ecx - 417c89: be a8 23 4a 00 mov $0x4a23a8,%esi - 417c8e: 48 8b 00 mov (%rax),%rax - 417c91: 48 85 c0 test %rax,%rax - 417c94: 48 0f 45 d0 cmovne %rax,%rdx - 417c98: 83 e7 02 and $0x2,%edi - 417c9b: 31 c0 xor %eax,%eax - 417c9d: e8 1e 99 ff ff callq 4115c0 <__libc_message> - 417ca2: e9 af fe ff ff jmpq 417b56 - 417ca7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 417cae: 00 00 - 417cb0: 89 ef mov %ebp,%edi - 417cb2: ba 5b 20 4a 00 mov $0x4a205b,%edx - 417cb7: be 3c ca 4b 00 mov $0x4bca3c,%esi - 417cbc: 83 e7 02 and $0x2,%edi - 417cbf: 31 c0 xor %eax,%eax - 417cc1: e8 fa 98 ff ff callq 4115c0 <__libc_message> - 417cc6: e9 8b fe ff ff jmpq 417b56 - 417ccb: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 417cd2: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) - 417cd9: b8 ff ff ff ff mov $0xffffffff,%eax - 417cde: e9 f0 fe ff ff jmpq 417bd3 - 417ce3: e8 18 5f ff ff callq 40dc00 - 417ce8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 417cef: 00 - -0000000000417cf0 : - 417cf0: 41 55 push %r13 - 417cf2: 41 54 push %r12 - 417cf4: 55 push %rbp - 417cf5: 53 push %rbx - 417cf6: 48 83 ec 28 sub $0x28,%rsp - 417cfa: 48 8b 47 08 mov 0x8(%rdi),%rax - 417cfe: 48 89 c6 mov %rax,%rsi - 417d01: 48 83 e6 f8 and $0xfffffffffffffff8,%rsi - 417d05: a8 02 test $0x2,%al - 417d07: 0f 84 09 01 00 00 je 417e16 - 417d0d: 48 8b 07 mov (%rdi),%rax - 417d10: 48 89 fa mov %rdi,%rdx - 417d13: 48 01 c6 add %rax,%rsi - 417d16: 48 29 c7 sub %rax,%rdi - 417d19: 48 8b 05 60 34 2b 00 mov 0x2b3460(%rip),%rax # 6cb180 <_dl_pagesize> - 417d20: 48 89 f9 mov %rdi,%rcx - 417d23: 48 09 f1 or %rsi,%rcx - 417d26: 48 83 e8 01 sub $0x1,%rax - 417d2a: 48 85 c8 test %rcx,%rax - 417d2d: 75 29 jne 417d58 - 417d2f: f0 ff 0d 92 2a 2b 00 lock decl 0x2b2a92(%rip) # 6ca7c8 - 417d36: 48 89 f0 mov %rsi,%rax - 417d39: 48 f7 d8 neg %rax - 417d3c: f0 48 01 05 94 2a 2b lock add %rax,0x2b2a94(%rip) # 6ca7d8 - 417d43: 00 - 417d44: e8 67 7f 02 00 callq 43fcb0 <__munmap> - 417d49: 48 83 c4 28 add $0x28,%rsp - 417d4d: 5b pop %rbx - 417d4e: 5d pop %rbp - 417d4f: 41 5c pop %r12 - 417d51: 41 5d pop %r13 - 417d53: c3 retq - 417d54: 0f 1f 40 00 nopl 0x0(%rax) - 417d58: 8b 1d 12 2a 2b 00 mov 0x2b2a12(%rip),%ebx # 6ca770 - 417d5e: 89 d8 mov %ebx,%eax - 417d60: 83 e0 05 and $0x5,%eax - 417d63: 83 f8 05 cmp $0x5,%eax - 417d66: 0f 84 8f 00 00 00 je 417dfb - 417d6c: f6 c3 01 test $0x1,%bl - 417d6f: 75 0f jne 417d80 - 417d71: 83 e3 02 and $0x2,%ebx - 417d74: 74 d3 je 417d49 - 417d76: e8 85 5e ff ff callq 40dc00 - 417d7b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 417d80: 48 8d 7a 10 lea 0x10(%rdx),%rdi - 417d84: 48 8d 74 24 10 lea 0x10(%rsp),%rsi - 417d89: 31 c9 xor %ecx,%ecx - 417d8b: ba 10 00 00 00 mov $0x10,%edx - 417d90: c6 44 24 10 00 movb $0x0,0x10(%rsp) - 417d95: e8 16 a1 03 00 callq 451eb0 <_itoa_word> - 417d9a: 48 39 e0 cmp %rsp,%rax - 417d9d: 48 89 c5 mov %rax,%rbp - 417da0: 76 25 jbe 417dc7 - 417da2: 48 89 c2 mov %rax,%rdx - 417da5: 48 89 c7 mov %rax,%rdi - 417da8: be 30 00 00 00 mov $0x30,%esi - 417dad: 48 29 e2 sub %rsp,%rdx - 417db0: 4c 8d 68 ff lea -0x1(%rax),%r13 - 417db4: 48 29 d7 sub %rdx,%rdi - 417db7: e8 94 85 fe ff callq 400350 <__rela_iplt_end+0x88> - 417dbc: 48 8d 44 24 ff lea -0x1(%rsp),%rax - 417dc1: 4c 29 e8 sub %r13,%rax - 417dc4: 48 01 c5 add %rax,%rbp - 417dc7: 48 8b 05 f2 54 2b 00 mov 0x2b54f2(%rip),%rax # 6cd2c0 <__libc_argv> - 417dce: ba 38 20 4a 00 mov $0x4a2038,%edx - 417dd3: 49 89 e8 mov %rbp,%r8 - 417dd6: b9 d0 23 4a 00 mov $0x4a23d0,%ecx - 417ddb: be a8 23 4a 00 mov $0x4a23a8,%esi - 417de0: 48 8b 00 mov (%rax),%rax - 417de3: 48 85 c0 test %rax,%rax - 417de6: 48 0f 45 d0 cmovne %rax,%rdx - 417dea: 83 e3 02 and $0x2,%ebx - 417ded: 31 c0 xor %eax,%eax - 417def: 89 df mov %ebx,%edi - 417df1: e8 ca 97 ff ff callq 4115c0 <__libc_message> - 417df6: e9 4e ff ff ff jmpq 417d49 - 417dfb: 83 e3 02 and $0x2,%ebx - 417dfe: ba d0 23 4a 00 mov $0x4a23d0,%edx - 417e03: be 3c ca 4b 00 mov $0x4bca3c,%esi - 417e08: 89 df mov %ebx,%edi - 417e0a: 31 c0 xor %eax,%eax - 417e0c: e8 af 97 ff ff callq 4115c0 <__libc_message> - 417e11: e9 33 ff ff ff jmpq 417d49 - 417e16: b9 78 2e 4a 00 mov $0x4a2e78,%ecx - 417e1b: ba 0f 0b 00 00 mov $0xb0f,%edx - 417e20: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 417e25: bf d1 1f 4a 00 mov $0x4a1fd1,%edi - 417e2a: e8 f1 ef ff ff callq 416e20 <__malloc_assert> - 417e2f: 90 nop - -0000000000417e30 : - 417e30: 48 83 3d 00 48 2b 00 cmpq $0x0,0x2b4800(%rip) # 6cc638 - 417e37: 00 - 417e38: 0f 84 26 07 00 00 je 418564 - 417e3e: 41 57 push %r15 - 417e40: 41 56 push %r14 - 417e42: 49 89 fe mov %rdi,%r14 - 417e45: 41 55 push %r13 - 417e47: 41 54 push %r12 - 417e49: 55 push %rbp - 417e4a: 53 push %rbx - 417e4b: 48 83 ec 68 sub $0x68,%rsp - 417e4f: 64 83 3c 25 18 00 00 cmpl $0x0,%fs:0x18 - 417e56: 00 00 - 417e58: 74 01 je 417e5b - 417e5a: f0 83 4f 04 01 lock orl $0x1,0x4(%rdi) - 417e5f: 48 8d 47 50 lea 0x50(%rdi),%rax - 417e63: 48 8d 74 24 40 lea 0x40(%rsp),%rsi - 417e68: 4c 8d 57 58 lea 0x58(%rdi),%r10 - 417e6c: 4c 8d 5f 08 lea 0x8(%rdi),%r11 - 417e70: 48 89 44 24 08 mov %rax,0x8(%rsp) - 417e75: b8 01 00 00 00 mov $0x1,%eax - 417e7a: 48 29 f0 sub %rsi,%rax - 417e7d: 48 89 44 24 10 mov %rax,0x10(%rsp) - 417e82: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 417e88: 31 db xor %ebx,%ebx - 417e8a: 49 87 1b xchg %rbx,(%r11) - 417e8d: 48 85 db test %rbx,%rbx - 417e90: 0f 84 71 01 00 00 je 418007 - 417e96: 4c 89 1c 24 mov %r11,(%rsp) - 417e9a: 4d 89 d7 mov %r10,%r15 - 417e9d: e9 a6 00 00 00 jmpq 417f48 - 417ea2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 417ea8: 48 8b 45 08 mov 0x8(%rbp),%rax - 417eac: 4d 01 ec add %r13,%r12 - 417eaf: 48 83 e0 f8 and $0xfffffffffffffff8,%rax - 417eb3: 48 3b 44 05 00 cmp 0x0(%rbp,%rax,1),%rax - 417eb8: 0f 85 22 02 00 00 jne 4180e0 - 417ebe: 4c 8b 6d 10 mov 0x10(%rbp),%r13 - 417ec2: 48 8b 45 18 mov 0x18(%rbp),%rax - 417ec6: 49 3b 6d 18 cmp 0x18(%r13),%rbp - 417eca: 0f 85 a0 01 00 00 jne 418070 - 417ed0: 48 3b 68 10 cmp 0x10(%rax),%rbp - 417ed4: 0f 85 96 01 00 00 jne 418070 - 417eda: 48 81 7d 08 ff 03 00 cmpq $0x3ff,0x8(%rbp) - 417ee1: 00 - 417ee2: 49 89 45 18 mov %rax,0x18(%r13) - 417ee6: 4c 89 68 10 mov %r13,0x10(%rax) - 417eea: 76 14 jbe 417f00 - 417eec: 48 8b 45 20 mov 0x20(%rbp),%rax - 417ef0: 48 85 c0 test %rax,%rax - 417ef3: 0f 85 07 04 00 00 jne 418300 - 417ef9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 417f00: 49 8b 46 68 mov 0x68(%r14),%rax - 417f04: 49 81 fc ff 03 00 00 cmp $0x3ff,%r12 - 417f0b: 49 89 5e 68 mov %rbx,0x68(%r14) - 417f0f: 48 89 58 18 mov %rbx,0x18(%rax) - 417f13: 76 10 jbe 417f25 - 417f15: 48 c7 43 20 00 00 00 movq $0x0,0x20(%rbx) - 417f1c: 00 - 417f1d: 48 c7 43 28 00 00 00 movq $0x0,0x28(%rbx) - 417f24: 00 - 417f25: 4c 89 e2 mov %r12,%rdx - 417f28: 4c 89 7b 18 mov %r15,0x18(%rbx) - 417f2c: 48 89 43 10 mov %rax,0x10(%rbx) - 417f30: 48 83 ca 01 or $0x1,%rdx - 417f34: 4d 85 c9 test %r9,%r9 - 417f37: 48 89 53 08 mov %rdx,0x8(%rbx) - 417f3b: 4e 89 24 23 mov %r12,(%rbx,%r12,1) - 417f3f: 4c 89 cb mov %r9,%rbx - 417f42: 0f 84 b8 00 00 00 je 418000 - 417f48: 48 8b 43 08 mov 0x8(%rbx),%rax - 417f4c: 4c 8b 4b 10 mov 0x10(%rbx),%r9 - 417f50: 49 89 c4 mov %rax,%r12 - 417f53: 49 83 e4 fa and $0xfffffffffffffffa,%r12 - 417f57: 4a 8d 2c 23 lea (%rbx,%r12,1),%rbp - 417f5b: 4c 8b 6d 08 mov 0x8(%rbp),%r13 - 417f5f: 49 83 e5 f8 and $0xfffffffffffffff8,%r13 - 417f63: a8 01 test $0x1,%al - 417f65: 75 59 jne 417fc0 - 417f67: 48 8b 03 mov (%rbx),%rax - 417f6a: 48 29 c3 sub %rax,%rbx - 417f6d: 49 01 c4 add %rax,%r12 - 417f70: 48 8b 43 08 mov 0x8(%rbx),%rax - 417f74: 48 83 e0 f8 and $0xfffffffffffffff8,%rax - 417f78: 48 3b 04 03 cmp (%rbx,%rax,1),%rax - 417f7c: 0f 85 26 01 00 00 jne 4180a8 - 417f82: 4c 8b 5b 10 mov 0x10(%rbx),%r11 - 417f86: 48 8b 43 18 mov 0x18(%rbx),%rax - 417f8a: 49 3b 5b 18 cmp 0x18(%r11),%rbx - 417f8e: 0f 85 9c 00 00 00 jne 418030 - 417f94: 48 3b 58 10 cmp 0x10(%rax),%rbx - 417f98: 0f 85 92 00 00 00 jne 418030 - 417f9e: 48 81 7b 08 ff 03 00 cmpq $0x3ff,0x8(%rbx) - 417fa5: 00 - 417fa6: 49 89 43 18 mov %rax,0x18(%r11) - 417faa: 4c 89 58 10 mov %r11,0x10(%rax) - 417fae: 76 10 jbe 417fc0 - 417fb0: 48 8b 43 20 mov 0x20(%rbx),%rax - 417fb4: 48 85 c0 test %rax,%rax - 417fb7: 0f 85 03 03 00 00 jne 4182c0 - 417fbd: 0f 1f 00 nopl (%rax) - 417fc0: 49 3b 6e 58 cmp 0x58(%r14),%rbp - 417fc4: 74 1a je 417fe0 - 417fc6: 42 f6 44 2d 08 01 testb $0x1,0x8(%rbp,%r13,1) - 417fcc: 0f 84 d6 fe ff ff je 417ea8 - 417fd2: 48 83 65 08 fe andq $0xfffffffffffffffe,0x8(%rbp) - 417fd7: e9 24 ff ff ff jmpq 417f00 - 417fdc: 0f 1f 40 00 nopl 0x0(%rax) - 417fe0: 4d 01 ec add %r13,%r12 - 417fe3: 49 83 cc 01 or $0x1,%r12 - 417fe7: 4d 85 c9 test %r9,%r9 - 417fea: 4c 89 63 08 mov %r12,0x8(%rbx) - 417fee: 49 89 5e 58 mov %rbx,0x58(%r14) - 417ff2: 4c 89 cb mov %r9,%rbx - 417ff5: 0f 85 4d ff ff ff jne 417f48 - 417ffb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 418000: 4c 8b 1c 24 mov (%rsp),%r11 - 418004: 4d 89 fa mov %r15,%r10 - 418007: 49 83 c3 08 add $0x8,%r11 - 41800b: 49 8d 43 f8 lea -0x8(%r11),%rax - 41800f: 48 39 44 24 08 cmp %rax,0x8(%rsp) - 418014: 0f 85 6e fe ff ff jne 417e88 - 41801a: 48 83 c4 68 add $0x68,%rsp - 41801e: 5b pop %rbx - 41801f: 5d pop %rbp - 418020: 41 5c pop %r12 - 418022: 41 5d pop %r13 - 418024: 41 5e pop %r14 - 418026: 41 5f pop %r15 - 418028: c3 retq - 418029: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 418030: 4d 85 f6 test %r14,%r14 - 418033: 44 8b 1d 36 27 2b 00 mov 0x2b2736(%rip),%r11d # 6ca770 - 41803a: 74 05 je 418041 - 41803c: 41 83 4e 04 04 orl $0x4,0x4(%r14) - 418041: 44 89 d8 mov %r11d,%eax - 418044: 83 e0 05 and $0x5,%eax - 418047: 83 f8 05 cmp $0x5,%eax - 41804a: 0f 84 7f 04 00 00 je 4184cf - 418050: 41 f6 c3 01 test $0x1,%r11b - 418054: 0f 85 96 01 00 00 jne 4181f0 - 41805a: 41 83 e3 02 and $0x2,%r11d - 41805e: 0f 84 5c ff ff ff je 417fc0 - 418064: e8 97 5b ff ff callq 40dc00 - 418069: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 418070: 8b 3d fa 26 2b 00 mov 0x2b26fa(%rip),%edi # 6ca770 - 418076: 41 83 4e 04 04 orl $0x4,0x4(%r14) - 41807b: 89 f8 mov %edi,%eax - 41807d: 83 e0 05 and $0x5,%eax - 418080: 83 f8 05 cmp $0x5,%eax - 418083: 0f 84 6c 04 00 00 je 4184f5 - 418089: 41 89 fd mov %edi,%r13d - 41808c: 41 83 e5 02 and $0x2,%r13d - 418090: 83 e7 01 and $0x1,%edi - 418093: 0f 85 af 00 00 00 jne 418148 - 418099: 45 85 ed test %r13d,%r13d - 41809c: 0f 84 5e fe ff ff je 417f00 - 4180a2: eb c0 jmp 418064 - 4180a4: 0f 1f 40 00 nopl 0x0(%rax) - 4180a8: 4d 85 f6 test %r14,%r14 - 4180ab: 44 8b 1d be 26 2b 00 mov 0x2b26be(%rip),%r11d # 6ca770 - 4180b2: 74 05 je 4180b9 - 4180b4: 41 83 4e 04 04 orl $0x4,0x4(%r14) - 4180b9: 44 89 d8 mov %r11d,%eax - 4180bc: 83 e0 05 and $0x5,%eax - 4180bf: 83 f8 05 cmp $0x5,%eax - 4180c2: 0f 84 50 04 00 00 je 418518 - 4180c8: 41 f6 c3 01 test $0x1,%r11b - 4180cc: 0f 85 6e 02 00 00 jne 418340 - 4180d2: 41 83 e3 02 and $0x2,%r11d - 4180d6: 0f 84 a6 fe ff ff je 417f82 - 4180dc: eb 86 jmp 418064 - 4180de: 66 90 xchg %ax,%ax - 4180e0: 44 8b 1d 89 26 2b 00 mov 0x2b2689(%rip),%r11d # 6ca770 - 4180e7: 41 83 4e 04 04 orl $0x4,0x4(%r14) - 4180ec: 44 89 d8 mov %r11d,%eax - 4180ef: 83 e0 05 and $0x5,%eax - 4180f2: 83 f8 05 cmp $0x5,%eax - 4180f5: 0f 84 43 04 00 00 je 41853e - 4180fb: 41 f6 c3 01 test $0x1,%r11b - 4180ff: 0f 85 0b 03 00 00 jne 418410 - 418105: 41 f6 c3 02 test $0x2,%r11b - 418109: 0f 85 55 ff ff ff jne 418064 - 41810f: 4c 8b 6d 10 mov 0x10(%rbp),%r13 - 418113: 48 8b 45 18 mov 0x18(%rbp),%rax - 418117: 49 39 6d 18 cmp %rbp,0x18(%r13) - 41811b: 0f 85 df fd ff ff jne 417f00 - 418121: 48 3b 68 10 cmp 0x10(%rax),%rbp - 418125: 0f 84 af fd ff ff je 417eda - 41812b: 44 89 df mov %r11d,%edi - 41812e: 41 83 4e 04 04 orl $0x4,0x4(%r14) - 418133: 41 89 fd mov %edi,%r13d - 418136: 41 83 e5 02 and $0x2,%r13d - 41813a: 83 e7 01 and $0x1,%edi - 41813d: 0f 84 56 ff ff ff je 418099 - 418143: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 418148: 48 8d 74 24 50 lea 0x50(%rsp),%rsi - 41814d: 31 c9 xor %ecx,%ecx - 41814f: 48 89 ef mov %rbp,%rdi - 418152: ba 10 00 00 00 mov $0x10,%edx - 418157: 4c 89 4c 24 18 mov %r9,0x18(%rsp) - 41815c: c6 44 24 50 00 movb $0x0,0x50(%rsp) - 418161: e8 4a 9d 03 00 callq 451eb0 <_itoa_word> - 418166: 48 89 c5 mov %rax,%rbp - 418169: 48 8d 44 24 40 lea 0x40(%rsp),%rax - 41816e: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 - 418173: 48 39 c5 cmp %rax,%rbp - 418176: 76 3c jbe 4181b4 - 418178: 48 8b 44 24 10 mov 0x10(%rsp),%rax - 41817d: 48 8d 4d ff lea -0x1(%rbp),%rcx - 418181: 48 89 ef mov %rbp,%rdi - 418184: be 30 00 00 00 mov $0x30,%esi - 418189: 4c 89 4c 24 20 mov %r9,0x20(%rsp) - 41818e: 48 89 4c 24 18 mov %rcx,0x18(%rsp) - 418193: 48 8d 14 08 lea (%rax,%rcx,1),%rdx - 418197: 48 29 d7 sub %rdx,%rdi - 41819a: e8 b1 81 fe ff callq 400350 <__rela_iplt_end+0x88> - 41819f: 48 8b 4c 24 18 mov 0x18(%rsp),%rcx - 4181a4: 48 8d 44 24 3f lea 0x3f(%rsp),%rax - 4181a9: 4c 8b 4c 24 20 mov 0x20(%rsp),%r9 - 4181ae: 48 29 c8 sub %rcx,%rax - 4181b1: 48 01 c5 add %rax,%rbp - 4181b4: 48 8b 05 05 51 2b 00 mov 0x2b5105(%rip),%rax # 6cd2c0 <__libc_argv> - 4181bb: ba 38 20 4a 00 mov $0x4a2038,%edx - 4181c0: 49 89 e8 mov %rbp,%r8 - 4181c3: b9 95 20 4a 00 mov $0x4a2095,%ecx - 4181c8: be a8 23 4a 00 mov $0x4a23a8,%esi - 4181cd: 44 89 ef mov %r13d,%edi - 4181d0: 4c 89 4c 24 18 mov %r9,0x18(%rsp) - 4181d5: 48 8b 00 mov (%rax),%rax - 4181d8: 48 85 c0 test %rax,%rax - 4181db: 48 0f 45 d0 cmovne %rax,%rdx - 4181df: 31 c0 xor %eax,%eax - 4181e1: e8 da 93 ff ff callq 4115c0 <__libc_message> - 4181e6: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 - 4181eb: e9 10 fd ff ff jmpq 417f00 - 4181f0: 48 8d 74 24 50 lea 0x50(%rsp),%rsi - 4181f5: 31 c9 xor %ecx,%ecx - 4181f7: ba 10 00 00 00 mov $0x10,%edx - 4181fc: 48 89 df mov %rbx,%rdi - 4181ff: 44 89 5c 24 20 mov %r11d,0x20(%rsp) - 418204: 4c 89 4c 24 18 mov %r9,0x18(%rsp) - 418209: c6 44 24 50 00 movb $0x0,0x50(%rsp) - 41820e: e8 9d 9c 03 00 callq 451eb0 <_itoa_word> - 418213: 49 89 c0 mov %rax,%r8 - 418216: 48 8d 44 24 40 lea 0x40(%rsp),%rax - 41821b: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 - 418220: 44 8b 5c 24 20 mov 0x20(%rsp),%r11d - 418225: 49 39 c0 cmp %rax,%r8 - 418228: 76 50 jbe 41827a - 41822a: 48 8b 44 24 10 mov 0x10(%rsp),%rax - 41822f: 49 8d 48 ff lea -0x1(%r8),%rcx - 418233: 4c 89 c7 mov %r8,%rdi - 418236: be 30 00 00 00 mov $0x30,%esi - 41823b: 44 89 5c 24 30 mov %r11d,0x30(%rsp) - 418240: 4c 89 4c 24 28 mov %r9,0x28(%rsp) - 418245: 48 89 4c 24 20 mov %rcx,0x20(%rsp) - 41824a: 4c 89 44 24 18 mov %r8,0x18(%rsp) - 41824f: 48 8d 14 08 lea (%rax,%rcx,1),%rdx - 418253: 48 29 d7 sub %rdx,%rdi - 418256: e8 f5 80 fe ff callq 400350 <__rela_iplt_end+0x88> - 41825b: 48 8b 4c 24 20 mov 0x20(%rsp),%rcx - 418260: 48 8d 44 24 3f lea 0x3f(%rsp),%rax - 418265: 4c 8b 44 24 18 mov 0x18(%rsp),%r8 - 41826a: 44 8b 5c 24 30 mov 0x30(%rsp),%r11d - 41826f: 4c 8b 4c 24 28 mov 0x28(%rsp),%r9 - 418274: 48 29 c8 sub %rcx,%rax - 418277: 49 01 c0 add %rax,%r8 - 41827a: 48 8b 05 3f 50 2b 00 mov 0x2b503f(%rip),%rax # 6cd2c0 <__libc_argv> - 418281: 44 89 df mov %r11d,%edi - 418284: ba 38 20 4a 00 mov $0x4a2038,%edx - 418289: b9 95 20 4a 00 mov $0x4a2095,%ecx - 41828e: be a8 23 4a 00 mov $0x4a23a8,%esi - 418293: 4c 89 4c 24 18 mov %r9,0x18(%rsp) - 418298: 48 8b 00 mov (%rax),%rax - 41829b: 48 85 c0 test %rax,%rax - 41829e: 48 0f 45 d0 cmovne %rax,%rdx - 4182a2: 83 e7 02 and $0x2,%edi - 4182a5: 31 c0 xor %eax,%eax - 4182a7: e8 14 93 ff ff callq 4115c0 <__libc_message> - 4182ac: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 - 4182b1: e9 0a fd ff ff jmpq 417fc0 - 4182b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4182bd: 00 00 00 - 4182c0: 48 3b 58 28 cmp 0x28(%rax),%rbx - 4182c4: 0f 85 dd 02 00 00 jne 4185a7 - 4182ca: 48 8b 53 28 mov 0x28(%rbx),%rdx - 4182ce: 48 3b 5a 20 cmp 0x20(%rdx),%rbx - 4182d2: 0f 85 cf 02 00 00 jne 4185a7 - 4182d8: 49 83 7b 20 00 cmpq $0x0,0x20(%r11) - 4182dd: 0f 84 03 03 00 00 je 4185e6 - 4182e3: 48 8b 53 28 mov 0x28(%rbx),%rdx - 4182e7: 48 89 50 28 mov %rdx,0x28(%rax) - 4182eb: 48 8b 53 28 mov 0x28(%rbx),%rdx - 4182ef: 48 89 42 20 mov %rax,0x20(%rdx) - 4182f3: e9 c8 fc ff ff jmpq 417fc0 - 4182f8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 4182ff: 00 - 418300: 48 3b 68 28 cmp 0x28(%rax),%rbp - 418304: 0f 85 06 03 00 00 jne 418610 - 41830a: 48 8b 55 28 mov 0x28(%rbp),%rdx - 41830e: 48 3b 6a 20 cmp 0x20(%rdx),%rbp - 418312: 0f 85 f8 02 00 00 jne 418610 - 418318: 49 83 7d 20 00 cmpq $0x0,0x20(%r13) - 41831d: 0f 84 27 03 00 00 je 41864a - 418323: 48 8b 55 28 mov 0x28(%rbp),%rdx - 418327: 48 89 50 28 mov %rdx,0x28(%rax) - 41832b: 48 8b 55 28 mov 0x28(%rbp),%rdx - 41832f: 48 89 42 20 mov %rax,0x20(%rdx) - 418333: e9 c8 fb ff ff jmpq 417f00 - 418338: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 41833f: 00 - 418340: 48 8d 74 24 50 lea 0x50(%rsp),%rsi - 418345: 31 c9 xor %ecx,%ecx - 418347: ba 10 00 00 00 mov $0x10,%edx - 41834c: 48 89 df mov %rbx,%rdi - 41834f: 44 89 5c 24 20 mov %r11d,0x20(%rsp) - 418354: 4c 89 4c 24 18 mov %r9,0x18(%rsp) - 418359: c6 44 24 50 00 movb $0x0,0x50(%rsp) - 41835e: e8 4d 9b 03 00 callq 451eb0 <_itoa_word> - 418363: 49 89 c0 mov %rax,%r8 - 418366: 48 8d 44 24 40 lea 0x40(%rsp),%rax - 41836b: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 - 418370: 44 8b 5c 24 20 mov 0x20(%rsp),%r11d - 418375: 49 39 c0 cmp %rax,%r8 - 418378: 76 50 jbe 4183ca - 41837a: 48 8b 44 24 10 mov 0x10(%rsp),%rax - 41837f: 49 8d 48 ff lea -0x1(%r8),%rcx - 418383: 4c 89 c7 mov %r8,%rdi - 418386: be 30 00 00 00 mov $0x30,%esi - 41838b: 44 89 5c 24 30 mov %r11d,0x30(%rsp) - 418390: 4c 89 4c 24 28 mov %r9,0x28(%rsp) - 418395: 48 89 4c 24 20 mov %rcx,0x20(%rsp) - 41839a: 4c 89 44 24 18 mov %r8,0x18(%rsp) - 41839f: 48 8d 14 08 lea (%rax,%rcx,1),%rdx - 4183a3: 48 29 d7 sub %rdx,%rdi - 4183a6: e8 a5 7f fe ff callq 400350 <__rela_iplt_end+0x88> - 4183ab: 48 8b 4c 24 20 mov 0x20(%rsp),%rcx - 4183b0: 48 8d 44 24 3f lea 0x3f(%rsp),%rax - 4183b5: 4c 8b 44 24 18 mov 0x18(%rsp),%r8 - 4183ba: 44 8b 5c 24 30 mov 0x30(%rsp),%r11d - 4183bf: 4c 8b 4c 24 28 mov 0x28(%rsp),%r9 - 4183c4: 48 29 c8 sub %rcx,%rax - 4183c7: 49 01 c0 add %rax,%r8 - 4183ca: 48 8b 05 ef 4e 2b 00 mov 0x2b4eef(%rip),%rax # 6cd2c0 <__libc_argv> - 4183d1: 44 89 df mov %r11d,%edi - 4183d4: ba 38 20 4a 00 mov $0x4a2038,%edx - 4183d9: b9 78 20 4a 00 mov $0x4a2078,%ecx - 4183de: be a8 23 4a 00 mov $0x4a23a8,%esi - 4183e3: 4c 89 4c 24 18 mov %r9,0x18(%rsp) - 4183e8: 48 8b 00 mov (%rax),%rax - 4183eb: 48 85 c0 test %rax,%rax - 4183ee: 48 0f 45 d0 cmovne %rax,%rdx - 4183f2: 83 e7 02 and $0x2,%edi - 4183f5: 31 c0 xor %eax,%eax - 4183f7: e8 c4 91 ff ff callq 4115c0 <__libc_message> - 4183fc: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 - 418401: e9 7c fb ff ff jmpq 417f82 - 418406: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41840d: 00 00 00 - 418410: 48 8d 74 24 50 lea 0x50(%rsp),%rsi - 418415: 31 c9 xor %ecx,%ecx - 418417: ba 10 00 00 00 mov $0x10,%edx - 41841c: 48 89 ef mov %rbp,%rdi - 41841f: 44 89 5c 24 20 mov %r11d,0x20(%rsp) - 418424: 4c 89 4c 24 18 mov %r9,0x18(%rsp) - 418429: c6 44 24 50 00 movb $0x0,0x50(%rsp) - 41842e: e8 7d 9a 03 00 callq 451eb0 <_itoa_word> - 418433: 49 89 c5 mov %rax,%r13 - 418436: 48 8d 44 24 40 lea 0x40(%rsp),%rax - 41843b: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 - 418440: 44 8b 5c 24 20 mov 0x20(%rsp),%r11d - 418445: 49 39 c5 cmp %rax,%r13 - 418448: 76 46 jbe 418490 - 41844a: 48 8b 44 24 10 mov 0x10(%rsp),%rax - 41844f: 49 8d 4d ff lea -0x1(%r13),%rcx - 418453: 4c 89 ef mov %r13,%rdi - 418456: be 30 00 00 00 mov $0x30,%esi - 41845b: 44 89 5c 24 28 mov %r11d,0x28(%rsp) - 418460: 4c 89 4c 24 20 mov %r9,0x20(%rsp) - 418465: 48 89 4c 24 18 mov %rcx,0x18(%rsp) - 41846a: 48 8d 14 08 lea (%rax,%rcx,1),%rdx - 41846e: 48 29 d7 sub %rdx,%rdi - 418471: e8 da 7e fe ff callq 400350 <__rela_iplt_end+0x88> - 418476: 48 8b 4c 24 18 mov 0x18(%rsp),%rcx - 41847b: 48 8d 44 24 3f lea 0x3f(%rsp),%rax - 418480: 44 8b 5c 24 28 mov 0x28(%rsp),%r11d - 418485: 4c 8b 4c 24 20 mov 0x20(%rsp),%r9 - 41848a: 48 29 c8 sub %rcx,%rax - 41848d: 49 01 c5 add %rax,%r13 - 418490: 48 8b 05 29 4e 2b 00 mov 0x2b4e29(%rip),%rax # 6cd2c0 <__libc_argv> - 418497: 44 89 df mov %r11d,%edi - 41849a: ba 38 20 4a 00 mov $0x4a2038,%edx - 41849f: 4d 89 e8 mov %r13,%r8 - 4184a2: b9 78 20 4a 00 mov $0x4a2078,%ecx - 4184a7: be a8 23 4a 00 mov $0x4a23a8,%esi - 4184ac: 4c 89 4c 24 18 mov %r9,0x18(%rsp) - 4184b1: 48 8b 00 mov (%rax),%rax - 4184b4: 48 85 c0 test %rax,%rax - 4184b7: 48 0f 45 d0 cmovne %rax,%rdx - 4184bb: 83 e7 02 and $0x2,%edi - 4184be: 31 c0 xor %eax,%eax - 4184c0: e8 fb 90 ff ff callq 4115c0 <__libc_message> - 4184c5: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 - 4184ca: e9 ef f9 ff ff jmpq 417ebe - 4184cf: 44 89 df mov %r11d,%edi - 4184d2: ba 95 20 4a 00 mov $0x4a2095,%edx - 4184d7: be 3c ca 4b 00 mov $0x4bca3c,%esi - 4184dc: 83 e7 02 and $0x2,%edi - 4184df: 31 c0 xor %eax,%eax - 4184e1: 4c 89 4c 24 18 mov %r9,0x18(%rsp) - 4184e6: e8 d5 90 ff ff callq 4115c0 <__libc_message> - 4184eb: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 - 4184f0: e9 cb fa ff ff jmpq 417fc0 - 4184f5: 83 e7 02 and $0x2,%edi - 4184f8: ba 95 20 4a 00 mov $0x4a2095,%edx - 4184fd: be 3c ca 4b 00 mov $0x4bca3c,%esi - 418502: 31 c0 xor %eax,%eax - 418504: 4c 89 4c 24 18 mov %r9,0x18(%rsp) - 418509: e8 b2 90 ff ff callq 4115c0 <__libc_message> - 41850e: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 - 418513: e9 e8 f9 ff ff jmpq 417f00 - 418518: 44 89 df mov %r11d,%edi - 41851b: ba 78 20 4a 00 mov $0x4a2078,%edx - 418520: be 3c ca 4b 00 mov $0x4bca3c,%esi - 418525: 83 e7 02 and $0x2,%edi - 418528: 31 c0 xor %eax,%eax - 41852a: 4c 89 4c 24 18 mov %r9,0x18(%rsp) - 41852f: e8 8c 90 ff ff callq 4115c0 <__libc_message> - 418534: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 - 418539: e9 44 fa ff ff jmpq 417f82 - 41853e: 44 89 df mov %r11d,%edi - 418541: ba 78 20 4a 00 mov $0x4a2078,%edx - 418546: be 3c ca 4b 00 mov $0x4bca3c,%esi - 41854b: 83 e7 02 and $0x2,%edi - 41854e: 31 c0 xor %eax,%eax - 418550: 4c 89 4c 24 18 mov %r9,0x18(%rsp) - 418555: e8 66 90 ff ff callq 4115c0 <__libc_message> - 41855a: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 - 41855f: e9 5a f9 ff ff jmpq 417ebe - 418564: 48 8d 4f 58 lea 0x58(%rdi),%rcx - 418568: 48 8d 97 48 08 00 00 lea 0x848(%rdi),%rdx - 41856f: 48 89 c8 mov %rcx,%rax - 418572: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 418578: 48 89 40 18 mov %rax,0x18(%rax) - 41857c: 48 89 40 10 mov %rax,0x10(%rax) - 418580: 48 83 c0 10 add $0x10,%rax - 418584: 48 39 c2 cmp %rax,%rdx - 418587: 75 ef jne 418578 - 418589: 48 81 ff 00 a8 6c 00 cmp $0x6ca800,%rdi - 418590: 0f 84 93 02 00 00 je 418829 - 418596: 8b 47 04 mov 0x4(%rdi),%eax - 418599: 83 c8 02 or $0x2,%eax - 41859c: 83 c8 01 or $0x1,%eax - 41859f: 48 89 4f 58 mov %rcx,0x58(%rdi) - 4185a3: 89 47 04 mov %eax,0x4(%rdi) - 4185a6: c3 retq - 4185a7: 4d 85 f6 test %r14,%r14 - 4185aa: 44 8b 05 bf 21 2b 00 mov 0x2b21bf(%rip),%r8d # 6ca770 - 4185b1: 74 05 je 4185b8 - 4185b3: 41 83 4e 04 04 orl $0x4,0x4(%r14) - 4185b8: 44 89 c2 mov %r8d,%edx - 4185bb: 83 e2 05 and $0x5,%edx - 4185be: 83 fa 05 cmp $0x5,%edx - 4185c1: 0f 84 85 02 00 00 je 41884c - 4185c7: 41 f6 c0 01 test $0x1,%r8b - 4185cb: 0f 85 a3 00 00 00 jne 418674 - 4185d1: 41 83 e0 02 and $0x2,%r8d - 4185d5: 0f 85 89 fa ff ff jne 418064 - 4185db: 49 83 7b 20 00 cmpq $0x0,0x20(%r11) - 4185e0: 0f 85 fd fc ff ff jne 4182e3 - 4185e6: 48 39 c3 cmp %rax,%rbx - 4185e9: 0f 84 50 02 00 00 je 41883f - 4185ef: 49 89 43 20 mov %rax,0x20(%r11) - 4185f3: 48 8b 43 28 mov 0x28(%rbx),%rax - 4185f7: 49 89 43 28 mov %rax,0x28(%r11) - 4185fb: 48 8b 43 20 mov 0x20(%rbx),%rax - 4185ff: 4c 89 58 28 mov %r11,0x28(%rax) - 418603: 48 8b 43 28 mov 0x28(%rbx),%rax - 418607: 4c 89 58 20 mov %r11,0x20(%rax) - 41860b: e9 b0 f9 ff ff jmpq 417fc0 - 418610: 44 8b 1d 59 21 2b 00 mov 0x2b2159(%rip),%r11d # 6ca770 - 418617: 41 83 4e 04 04 orl $0x4,0x4(%r14) - 41861c: 44 89 da mov %r11d,%edx - 41861f: 83 e2 05 and $0x5,%edx - 418622: 83 fa 05 cmp $0x5,%edx - 418625: 0f 84 62 02 00 00 je 41888d - 41862b: 41 f6 c3 01 test $0x1,%r11b - 41862f: 0f 85 2a 01 00 00 jne 41875f - 418635: 41 83 e3 02 and $0x2,%r11d - 418639: 0f 85 25 fa ff ff jne 418064 - 41863f: 49 83 7d 20 00 cmpq $0x0,0x20(%r13) - 418644: 0f 85 d9 fc ff ff jne 418323 - 41864a: 48 39 c5 cmp %rax,%rbp - 41864d: 0f 84 2d 02 00 00 je 418880 - 418653: 49 89 45 20 mov %rax,0x20(%r13) - 418657: 48 8b 45 28 mov 0x28(%rbp),%rax - 41865b: 49 89 45 28 mov %rax,0x28(%r13) - 41865f: 48 8b 45 20 mov 0x20(%rbp),%rax - 418663: 4c 89 68 28 mov %r13,0x28(%rax) - 418667: 48 8b 45 28 mov 0x28(%rbp),%rax - 41866b: 4c 89 68 20 mov %r13,0x20(%rax) - 41866f: e9 8c f8 ff ff jmpq 417f00 - 418674: 48 8d 74 24 50 lea 0x50(%rsp),%rsi - 418679: 31 c9 xor %ecx,%ecx - 41867b: ba 10 00 00 00 mov $0x10,%edx - 418680: 48 89 df mov %rbx,%rdi - 418683: 44 89 44 24 28 mov %r8d,0x28(%rsp) - 418688: 4c 89 5c 24 20 mov %r11,0x20(%rsp) - 41868d: 4c 89 4c 24 18 mov %r9,0x18(%rsp) - 418692: c6 44 24 50 00 movb $0x0,0x50(%rsp) - 418697: e8 14 98 03 00 callq 451eb0 <_itoa_word> - 41869c: 48 89 c1 mov %rax,%rcx - 41869f: 48 8d 44 24 40 lea 0x40(%rsp),%rax - 4186a4: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 - 4186a9: 4c 8b 5c 24 20 mov 0x20(%rsp),%r11 - 4186ae: 44 8b 44 24 28 mov 0x28(%rsp),%r8d - 4186b3: 48 39 c1 cmp %rax,%rcx - 4186b6: 76 5a jbe 418712 - 4186b8: 48 8b 44 24 10 mov 0x10(%rsp),%rax - 4186bd: 4c 8d 51 ff lea -0x1(%rcx),%r10 - 4186c1: 48 89 cf mov %rcx,%rdi - 4186c4: be 30 00 00 00 mov $0x30,%esi - 4186c9: 44 89 44 24 3c mov %r8d,0x3c(%rsp) - 4186ce: 4c 89 5c 24 30 mov %r11,0x30(%rsp) - 4186d3: 4c 89 4c 24 28 mov %r9,0x28(%rsp) - 4186d8: 4c 89 54 24 20 mov %r10,0x20(%rsp) - 4186dd: 4a 8d 14 10 lea (%rax,%r10,1),%rdx - 4186e1: 48 89 4c 24 18 mov %rcx,0x18(%rsp) - 4186e6: 48 29 d7 sub %rdx,%rdi - 4186e9: e8 62 7c fe ff callq 400350 <__rela_iplt_end+0x88> - 4186ee: 4c 8b 54 24 20 mov 0x20(%rsp),%r10 - 4186f3: 48 8d 44 24 3f lea 0x3f(%rsp),%rax - 4186f8: 48 8b 4c 24 18 mov 0x18(%rsp),%rcx - 4186fd: 44 8b 44 24 3c mov 0x3c(%rsp),%r8d - 418702: 4c 8b 5c 24 30 mov 0x30(%rsp),%r11 - 418707: 4c 8b 4c 24 28 mov 0x28(%rsp),%r9 - 41870c: 4c 29 d0 sub %r10,%rax - 41870f: 48 01 c1 add %rax,%rcx - 418712: 48 8b 05 a7 4b 2b 00 mov 0x2b4ba7(%rip),%rax # 6cd2c0 <__libc_argv> - 418719: 44 89 c7 mov %r8d,%edi - 41871c: ba 38 20 4a 00 mov $0x4a2038,%edx - 418721: 49 89 c8 mov %rcx,%r8 - 418724: be a8 23 4a 00 mov $0x4a23a8,%esi - 418729: b9 f0 23 4a 00 mov $0x4a23f0,%ecx - 41872e: 4c 89 5c 24 20 mov %r11,0x20(%rsp) - 418733: 4c 89 4c 24 18 mov %r9,0x18(%rsp) - 418738: 48 8b 00 mov (%rax),%rax - 41873b: 48 85 c0 test %rax,%rax - 41873e: 48 0f 45 d0 cmovne %rax,%rdx - 418742: 31 c0 xor %eax,%eax - 418744: 83 e7 02 and $0x2,%edi - 418747: e8 74 8e ff ff callq 4115c0 <__libc_message> - 41874c: 48 8b 43 20 mov 0x20(%rbx),%rax - 418750: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 - 418755: 4c 8b 5c 24 20 mov 0x20(%rsp),%r11 - 41875a: e9 79 fb ff ff jmpq 4182d8 - 41875f: 48 8d 74 24 50 lea 0x50(%rsp),%rsi - 418764: 31 c9 xor %ecx,%ecx - 418766: ba 10 00 00 00 mov $0x10,%edx - 41876b: 48 89 ef mov %rbp,%rdi - 41876e: 44 89 5c 24 20 mov %r11d,0x20(%rsp) - 418773: 4c 89 4c 24 18 mov %r9,0x18(%rsp) - 418778: c6 44 24 50 00 movb $0x0,0x50(%rsp) - 41877d: e8 2e 97 03 00 callq 451eb0 <_itoa_word> - 418782: 49 89 c0 mov %rax,%r8 - 418785: 48 8d 44 24 40 lea 0x40(%rsp),%rax - 41878a: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 - 41878f: 44 8b 5c 24 20 mov 0x20(%rsp),%r11d - 418794: 49 39 c0 cmp %rax,%r8 - 418797: 76 50 jbe 4187e9 - 418799: 48 8b 44 24 10 mov 0x10(%rsp),%rax - 41879e: 49 8d 48 ff lea -0x1(%r8),%rcx - 4187a2: 4c 89 c7 mov %r8,%rdi - 4187a5: be 30 00 00 00 mov $0x30,%esi - 4187aa: 44 89 5c 24 30 mov %r11d,0x30(%rsp) - 4187af: 4c 89 4c 24 28 mov %r9,0x28(%rsp) - 4187b4: 48 89 4c 24 20 mov %rcx,0x20(%rsp) - 4187b9: 4c 89 44 24 18 mov %r8,0x18(%rsp) - 4187be: 48 8d 14 08 lea (%rax,%rcx,1),%rdx - 4187c2: 48 29 d7 sub %rdx,%rdi - 4187c5: e8 86 7b fe ff callq 400350 <__rela_iplt_end+0x88> - 4187ca: 48 8b 4c 24 20 mov 0x20(%rsp),%rcx - 4187cf: 48 8d 44 24 3f lea 0x3f(%rsp),%rax - 4187d4: 4c 8b 44 24 18 mov 0x18(%rsp),%r8 - 4187d9: 44 8b 5c 24 30 mov 0x30(%rsp),%r11d - 4187de: 4c 8b 4c 24 28 mov 0x28(%rsp),%r9 - 4187e3: 48 29 c8 sub %rcx,%rax - 4187e6: 49 01 c0 add %rax,%r8 - 4187e9: 48 8b 05 d0 4a 2b 00 mov 0x2b4ad0(%rip),%rax # 6cd2c0 <__libc_argv> - 4187f0: 44 89 df mov %r11d,%edi - 4187f3: ba 38 20 4a 00 mov $0x4a2038,%edx - 4187f8: b9 f0 23 4a 00 mov $0x4a23f0,%ecx - 4187fd: be a8 23 4a 00 mov $0x4a23a8,%esi - 418802: 4c 89 4c 24 18 mov %r9,0x18(%rsp) - 418807: 48 8b 00 mov (%rax),%rax - 41880a: 48 85 c0 test %rax,%rax - 41880d: 48 0f 45 d0 cmovne %rax,%rdx - 418811: 31 c0 xor %eax,%eax - 418813: 83 e7 02 and $0x2,%edi - 418816: e8 a5 8d ff ff callq 4115c0 <__libc_message> - 41881b: 48 8b 45 20 mov 0x20(%rbp),%rax - 41881f: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 - 418824: e9 ef fa ff ff jmpq 418318 - 418829: 48 c7 05 04 3e 2b 00 movq $0x80,0x2b3e04(%rip) # 6cc638 - 418830: 80 00 00 00 - 418834: 8b 05 ca 1f 2b 00 mov 0x2b1fca(%rip),%eax # 6ca804 - 41883a: e9 5d fd ff ff jmpq 41859c - 41883f: 4d 89 5b 28 mov %r11,0x28(%r11) - 418843: 4d 89 5b 20 mov %r11,0x20(%r11) - 418847: e9 74 f7 ff ff jmpq 417fc0 - 41884c: 44 89 c7 mov %r8d,%edi - 41884f: 31 c0 xor %eax,%eax - 418851: ba f0 23 4a 00 mov $0x4a23f0,%edx - 418856: 83 e7 02 and $0x2,%edi - 418859: be 3c ca 4b 00 mov $0x4bca3c,%esi - 41885e: 4c 89 5c 24 20 mov %r11,0x20(%rsp) - 418863: 4c 89 4c 24 18 mov %r9,0x18(%rsp) - 418868: e8 53 8d ff ff callq 4115c0 <__libc_message> - 41886d: 48 8b 43 20 mov 0x20(%rbx),%rax - 418871: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 - 418876: 4c 8b 5c 24 20 mov 0x20(%rsp),%r11 - 41887b: e9 58 fa ff ff jmpq 4182d8 - 418880: 4d 89 6d 28 mov %r13,0x28(%r13) - 418884: 4d 89 6d 20 mov %r13,0x20(%r13) - 418888: e9 73 f6 ff ff jmpq 417f00 - 41888d: 44 89 df mov %r11d,%edi - 418890: 31 c0 xor %eax,%eax - 418892: ba f0 23 4a 00 mov $0x4a23f0,%edx - 418897: 83 e7 02 and $0x2,%edi - 41889a: be 3c ca 4b 00 mov $0x4bca3c,%esi - 41889f: 4c 89 4c 24 18 mov %r9,0x18(%rsp) - 4188a4: e8 17 8d ff ff callq 4115c0 <__libc_message> - 4188a9: 48 8b 45 20 mov 0x20(%rbp),%rax - 4188ad: 4c 8b 4c 24 18 mov 0x18(%rsp),%r9 - 4188b2: e9 61 fa ff ff jmpq 418318 - 4188b7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 4188be: 00 00 - -00000000004188c0 : - 4188c0: 41 54 push %r12 - 4188c2: 55 push %rbp - 4188c3: 49 89 f4 mov %rsi,%r12 - 4188c6: 53 push %rbx - 4188c7: 48 8b 47 58 mov 0x58(%rdi),%rax - 4188cb: 48 89 fb mov %rdi,%rbx - 4188ce: 48 85 c0 test %rax,%rax - 4188d1: 0f 84 f4 00 00 00 je 4189cb - 4188d7: 48 8b 68 08 mov 0x8(%rax),%rbp - 4188db: 48 8d 7b 08 lea 0x8(%rbx),%rdi - 4188df: 4c 8d 43 58 lea 0x58(%rbx),%r8 - 4188e3: 45 31 d2 xor %r10d,%r10d - 4188e6: 45 31 c9 xor %r9d,%r9d - 4188e9: 48 89 e9 mov %rbp,%rcx - 4188ec: 48 83 e1 f8 and $0xfffffffffffffff8,%rcx - 4188f0: 48 8b 07 mov (%rdi),%rax - 4188f3: 48 85 c0 test %rax,%rax - 4188f6: 74 20 je 418918 - 4188f8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 4188ff: 00 - 418900: 48 8b 50 08 mov 0x8(%rax),%rdx - 418904: 48 8b 40 10 mov 0x10(%rax),%rax - 418908: 41 83 c2 01 add $0x1,%r10d - 41890c: 48 83 e2 f8 and $0xfffffffffffffff8,%rdx - 418910: 49 01 d1 add %rdx,%r9 - 418913: 48 85 c0 test %rax,%rax - 418916: 75 e8 jne 418900 - 418918: 48 83 c7 08 add $0x8,%rdi - 41891c: 4c 39 c7 cmp %r8,%rdi - 41891f: 75 cf jne 4188f0 - 418921: 4c 8d 9b 48 08 00 00 lea 0x848(%rbx),%r11 - 418928: 4c 01 c9 add %r9,%rcx - 41892b: bf 01 00 00 00 mov $0x1,%edi - 418930: 49 8b 40 18 mov 0x18(%r8),%rax - 418934: 49 39 c0 cmp %rax,%r8 - 418937: 74 1e je 418957 - 418939: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 418940: 48 8b 50 08 mov 0x8(%rax),%rdx - 418944: 48 8b 40 18 mov 0x18(%rax),%rax - 418948: 83 c7 01 add $0x1,%edi - 41894b: 48 83 e2 f8 and $0xfffffffffffffff8,%rdx - 41894f: 48 01 d1 add %rdx,%rcx - 418952: 49 39 c0 cmp %rax,%r8 - 418955: 75 e9 jne 418940 - 418957: 49 83 c0 10 add $0x10,%r8 - 41895b: 4d 39 c3 cmp %r8,%r11 - 41895e: 75 d0 jne 418930 - 418960: 48 8b 93 80 08 00 00 mov 0x880(%rbx),%rdx - 418967: 41 8b 44 24 1c mov 0x1c(%r12),%eax - 41896c: 45 01 54 24 08 add %r10d,0x8(%r12) - 418971: 41 01 7c 24 04 add %edi,0x4(%r12) - 418976: 01 d0 add %edx,%eax - 418978: 41 01 4c 24 20 add %ecx,0x20(%r12) - 41897d: 41 01 14 24 add %edx,(%r12) - 418981: 29 c8 sub %ecx,%eax - 418983: 45 01 4c 24 18 add %r9d,0x18(%r12) - 418988: 48 81 fb 00 a8 6c 00 cmp $0x6ca800,%rbx - 41898f: 41 89 44 24 1c mov %eax,0x1c(%r12) - 418994: 74 05 je 41899b - 418996: 5b pop %rbx - 418997: 5d pop %rbp - 418998: 41 5c pop %r12 - 41899a: c3 retq - 41899b: 8b 05 27 1e 2b 00 mov 0x2b1e27(%rip),%eax # 6ca7c8 - 4189a1: 83 e5 f8 and $0xfffffff8,%ebp - 4189a4: 5b pop %rbx - 4189a5: 41 89 44 24 0c mov %eax,0xc(%r12) - 4189aa: 48 8b 05 27 1e 2b 00 mov 0x2b1e27(%rip),%rax # 6ca7d8 - 4189b1: 41 89 44 24 10 mov %eax,0x10(%r12) - 4189b6: 48 8b 05 2b 1e 2b 00 mov 0x2b1e2b(%rip),%rax # 6ca7e8 - 4189bd: 41 89 6c 24 24 mov %ebp,0x24(%r12) - 4189c2: 5d pop %rbp - 4189c3: 41 89 44 24 14 mov %eax,0x14(%r12) - 4189c8: 41 5c pop %r12 - 4189ca: c3 retq - 4189cb: e8 60 f4 ff ff callq 417e30 - 4189d0: 48 8b 43 58 mov 0x58(%rbx),%rax - 4189d4: e9 fe fe ff ff jmpq 4188d7 - 4189d9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - -00000000004189e0 : - 4189e0: 48 85 ff test %rdi,%rdi - 4189e3: 0f 84 1b 04 00 00 je 418e04 - 4189e9: 41 57 push %r15 - 4189eb: 41 56 push %r14 - 4189ed: 49 89 f8 mov %rdi,%r8 - 4189f0: 41 55 push %r13 - 4189f2: 41 54 push %r12 - 4189f4: be 01 00 00 00 mov $0x1,%esi - 4189f9: 55 push %rbp - 4189fa: 53 push %rbx - 4189fb: 31 c0 xor %eax,%eax - 4189fd: 48 83 ec 38 sub $0x38,%rsp - 418a01: 83 3d b4 47 2b 00 00 cmpl $0x0,0x2b47b4(%rip) # 6cd1bc <__libc_multiple_threads> - 418a08: 74 0c je 418a16 - 418a0a: f0 0f b1 35 ee 1d 2b lock cmpxchg %esi,0x2b1dee(%rip) # 6ca800 - 418a11: 00 - 418a12: 75 0b jne 418a1f - 418a14: eb 23 jmp 418a39 - 418a16: 0f b1 35 e3 1d 2b 00 cmpxchg %esi,0x2b1de3(%rip) # 6ca800 - 418a1d: 74 1a je 418a39 - 418a1f: 48 8d 3d da 1d 2b 00 lea 0x2b1dda(%rip),%rdi # 6ca800 - 418a26: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 418a2d: e8 9e 9b 02 00 callq 4425d0 <__lll_lock_wait_private> - 418a32: 48 81 c4 80 00 00 00 add $0x80,%rsp - 418a39: 41 f6 c0 0f test $0xf,%r8b - 418a3d: 0f 85 35 04 00 00 jne 418e78 - 418a43: 49 8d 58 f0 lea -0x10(%r8),%rbx - 418a47: 49 8b 40 f8 mov -0x8(%r8),%rax - 418a4b: 48 89 df mov %rbx,%rdi - 418a4e: 48 89 d9 mov %rbx,%rcx - 418a51: 48 c1 e9 0b shr $0xb,%rcx - 418a55: 48 c1 ef 03 shr $0x3,%rdi - 418a59: 48 89 c2 mov %rax,%rdx - 418a5c: 31 cf xor %ecx,%edi - 418a5e: 48 83 e2 f8 and $0xfffffffffffffff8,%rdx - 418a62: b9 02 00 00 00 mov $0x2,%ecx - 418a67: 40 80 ff 01 cmp $0x1,%dil - 418a6b: 0f 44 f9 cmove %ecx,%edi - 418a6e: a8 02 test $0x2,%al - 418a70: 0f 84 9a 03 00 00 je 418e10 - 418a76: 48 8b 05 03 27 2b 00 mov 0x2b2703(%rip),%rax # 6cb180 <_dl_pagesize> - 418a7d: 48 8d 48 ff lea -0x1(%rax),%rcx - 418a81: 4c 89 c0 mov %r8,%rax - 418a84: 48 21 c8 and %rcx,%rax - 418a87: 48 8d 70 f0 lea -0x10(%rax),%rsi - 418a8b: 48 f7 c6 ef ff ff ff test $0xffffffffffffffef,%rsi - 418a92: 74 34 je 418ac8 - 418a94: 48 8d 70 ff lea -0x1(%rax),%rsi - 418a98: 48 81 fe fe 1f 00 00 cmp $0x1ffe,%rsi - 418a9f: 77 27 ja 418ac8 - 418aa1: 48 8d 70 c0 lea -0x40(%rax),%rsi - 418aa5: 48 f7 c6 bf ff ff ff test $0xffffffffffffffbf,%rsi - 418aac: 74 1a je 418ac8 - 418aae: 48 8d b0 00 ff ff ff lea -0x100(%rax),%rsi - 418ab5: 48 f7 c6 ff fe ff ff test $0xfffffffffffffeff,%rsi - 418abc: 0f 85 5e 06 00 00 jne 419120 - 418ac2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 418ac8: 49 8b 40 f8 mov -0x8(%r8),%rax - 418acc: 83 e0 03 and $0x3,%eax - 418acf: 48 83 f8 02 cmp $0x2,%rax - 418ad3: 0f 85 9f 03 00 00 jne 418e78 - 418ad9: 49 8b 40 f0 mov -0x10(%r8),%rax - 418add: 48 89 de mov %rbx,%rsi - 418ae0: 48 29 c6 sub %rax,%rsi - 418ae3: 48 01 d0 add %rdx,%rax - 418ae6: 48 09 f0 or %rsi,%rax - 418ae9: 48 85 c8 test %rcx,%rax - 418aec: 0f 85 86 03 00 00 jne 418e78 - 418af2: 48 83 ea 01 sub $0x1,%rdx - 418af6: 40 0f b6 ff movzbl %dil,%edi - 418afa: 48 8d 34 13 lea (%rbx,%rdx,1),%rsi - 418afe: 0f b6 06 movzbl (%rsi),%eax - 418b01: 48 39 f8 cmp %rdi,%rax - 418b04: 48 89 c1 mov %rax,%rcx - 418b07: 74 3f je 418b48 - 418b09: 48 85 c0 test %rax,%rax - 418b0c: 0f 84 66 03 00 00 je 418e78 - 418b12: 48 8d 48 10 lea 0x10(%rax),%rcx - 418b16: 48 39 ca cmp %rcx,%rdx - 418b19: 73 1b jae 418b36 - 418b1b: e9 58 03 00 00 jmpq 418e78 - 418b20: 48 85 c0 test %rax,%rax - 418b23: 0f 84 4f 03 00 00 je 418e78 - 418b29: 48 8d 48 10 lea 0x10(%rax),%rcx - 418b2d: 48 39 d1 cmp %rdx,%rcx - 418b30: 0f 87 42 03 00 00 ja 418e78 - 418b36: 48 29 c2 sub %rax,%rdx - 418b39: 48 8d 34 13 lea (%rbx,%rdx,1),%rsi - 418b3d: 0f b6 06 movzbl (%rsi),%eax - 418b40: 48 39 f8 cmp %rdi,%rax - 418b43: 48 89 c1 mov %rax,%rcx - 418b46: 75 d8 jne 418b20 - 418b48: f7 d1 not %ecx - 418b4a: 48 85 db test %rbx,%rbx - 418b4d: 88 0e mov %cl,(%rsi) - 418b4f: 0f 84 23 03 00 00 je 418e78 - 418b55: 4d 8b 60 f8 mov -0x8(%r8),%r12 - 418b59: 41 f6 c4 02 test $0x2,%r12b - 418b5d: 0f 85 55 02 00 00 jne 418db8 - 418b63: 4c 89 e5 mov %r12,%rbp - 418b66: 48 83 e5 f8 and $0xfffffffffffffff8,%rbp - 418b6a: 48 89 e8 mov %rbp,%rax - 418b6d: 48 f7 d8 neg %rax - 418b70: 48 39 c3 cmp %rax,%rbx - 418b73: 0f 87 e7 04 00 00 ja 419060 - 418b79: f6 c3 0f test $0xf,%bl - 418b7c: 0f 85 de 04 00 00 jne 419060 - 418b82: 48 83 fd 1f cmp $0x1f,%rbp - 418b86: 0f 86 64 05 00 00 jbe 4190f0 - 418b8c: 41 f6 c4 08 test $0x8,%r12b - 418b90: 0f 85 5a 05 00 00 jne 4190f0 - 418b96: 48 3b 2d 9b 3a 2b 00 cmp 0x2b3a9b(%rip),%rbp # 6cc638 - 418b9d: 0f 86 a5 03 00 00 jbe 418f48 - 418ba3: 48 8b 05 ae 1c 2b 00 mov 0x2b1cae(%rip),%rax # 6ca858 - 418baa: 4c 8d 34 2b lea (%rbx,%rbp,1),%r14 - 418bae: 44 8b 2d 4f 1c 2b 00 mov 0x2b1c4f(%rip),%r13d # 6ca804 - 418bb5: 48 39 c3 cmp %rax,%rbx - 418bb8: 0f 84 94 06 00 00 je 419252 - 418bbe: 41 f6 c5 02 test $0x2,%r13b - 418bc2: 0f 84 af 06 00 00 je 419277 - 418bc8: 49 8b 46 08 mov 0x8(%r14),%rax - 418bcc: a8 01 test $0x1,%al - 418bce: 0f 84 c2 06 00 00 je 419296 - 418bd4: 49 89 c7 mov %rax,%r15 - 418bd7: 49 83 e7 f8 and $0xfffffffffffffff8,%r15 - 418bdb: 48 83 f8 10 cmp $0x10,%rax - 418bdf: 0f 86 4e 06 00 00 jbe 419233 - 418be5: 4c 3b 3d 94 24 2b 00 cmp 0x2b2494(%rip),%r15 # 6cb080 - 418bec: 0f 83 41 06 00 00 jae 419233 - 418bf2: 8b 35 3c 3a 2b 00 mov 0x2b3a3c(%rip),%esi # 6cc634 - 418bf8: 85 f6 test %esi,%esi - 418bfa: 0f 85 b0 06 00 00 jne 4192b0 - 418c00: 41 83 e4 01 and $0x1,%r12d - 418c04: 0f 85 8e 00 00 00 jne 418c98 - 418c0a: 49 8b 40 f0 mov -0x10(%r8),%rax - 418c0e: 48 29 c3 sub %rax,%rbx - 418c11: 48 01 c5 add %rax,%rbp - 418c14: 48 8b 43 08 mov 0x8(%rbx),%rax - 418c18: 48 83 e0 f8 and $0xfffffffffffffff8,%rax - 418c1c: 48 3b 04 03 cmp (%rbx,%rax,1),%rax - 418c20: 0f 85 1a 07 00 00 jne 419340 - 418c26: 4c 8b 63 10 mov 0x10(%rbx),%r12 - 418c2a: 48 8b 43 18 mov 0x18(%rbx),%rax - 418c2e: 49 3b 5c 24 18 cmp 0x18(%r12),%rbx - 418c33: 0f 85 8b 06 00 00 jne 4192c4 - 418c39: 48 3b 58 10 cmp 0x10(%rax),%rbx - 418c3d: 0f 85 81 06 00 00 jne 4192c4 - 418c43: 48 81 7b 08 ff 03 00 cmpq $0x3ff,0x8(%rbx) - 418c4a: 00 - 418c4b: 49 89 44 24 18 mov %rax,0x18(%r12) - 418c50: 4c 89 60 10 mov %r12,0x10(%rax) - 418c54: 76 42 jbe 418c98 - 418c56: 48 8b 43 20 mov 0x20(%rbx),%rax - 418c5a: 48 85 c0 test %rax,%rax - 418c5d: 74 39 je 418c98 - 418c5f: 48 3b 58 28 cmp 0x28(%rax),%rbx - 418c63: 0f 85 92 0a 00 00 jne 4196fb - 418c69: 48 8b 53 28 mov 0x28(%rbx),%rdx - 418c6d: 48 3b 5a 20 cmp 0x20(%rdx),%rbx - 418c71: 0f 85 84 0a 00 00 jne 4196fb - 418c77: 49 83 7c 24 20 00 cmpq $0x0,0x20(%r12) - 418c7d: 0f 84 4c 0a 00 00 je 4196cf - 418c83: 48 8b 53 28 mov 0x28(%rbx),%rdx - 418c87: 48 89 50 28 mov %rdx,0x28(%rax) - 418c8b: 48 8b 53 28 mov 0x28(%rbx),%rdx - 418c8f: 48 89 42 20 mov %rax,0x20(%rdx) - 418c93: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 418c98: 4c 3b 35 b9 1b 2b 00 cmp 0x2b1bb9(%rip),%r14 # 6ca858 - 418c9f: 0f 84 b8 05 00 00 je 41925d - 418ca5: 43 f6 44 3e 08 01 testb $0x1,0x8(%r14,%r15,1) - 418cab: 0f 85 97 04 00 00 jne 419148 - 418cb1: 49 8b 46 08 mov 0x8(%r14),%rax - 418cb5: 48 83 e0 f8 and $0xfffffffffffffff8,%rax - 418cb9: 49 3b 04 06 cmp (%r14,%rax,1),%rax - 418cbd: 0f 85 f8 06 00 00 jne 4193bb - 418cc3: 4d 8b 66 10 mov 0x10(%r14),%r12 - 418cc7: 49 8b 46 18 mov 0x18(%r14),%rax - 418ccb: 4d 3b 74 24 18 cmp 0x18(%r12),%r14 - 418cd0: 0f 85 2a 06 00 00 jne 419300 - 418cd6: 4c 3b 70 10 cmp 0x10(%rax),%r14 - 418cda: 0f 85 20 06 00 00 jne 419300 - 418ce0: 49 81 7e 08 ff 03 00 cmpq $0x3ff,0x8(%r14) - 418ce7: 00 - 418ce8: 49 89 44 24 18 mov %rax,0x18(%r12) - 418ced: 4c 89 60 10 mov %r12,0x10(%rax) - 418cf1: 76 0d jbe 418d00 - 418cf3: 49 8b 46 20 mov 0x20(%r14),%rax - 418cf7: 48 85 c0 test %rax,%rax - 418cfa: 0f 85 3b 08 00 00 jne 41953b - 418d00: 4c 01 fd add %r15,%rbp - 418d03: 48 8b 05 5e 1b 2b 00 mov 0x2b1b5e(%rip),%rax # 6ca868 - 418d0a: 44 8b 2d f3 1a 2b 00 mov 0x2b1af3(%rip),%r13d # 6ca804 - 418d11: 41 bc 48 24 4a 00 mov $0x4a2448,%r12d - 418d17: 48 81 78 18 58 a8 6c cmpq $0x6ca858,0x18(%rax) - 418d1e: 00 - 418d1f: 0f 85 cd 02 00 00 jne 418ff2 - 418d25: 48 81 fd ff 03 00 00 cmp $0x3ff,%rbp - 418d2c: 48 89 43 10 mov %rax,0x10(%rbx) - 418d30: 48 c7 43 18 58 a8 6c movq $0x6ca858,0x18(%rbx) - 418d37: 00 - 418d38: 76 10 jbe 418d4a - 418d3a: 48 c7 43 20 00 00 00 movq $0x0,0x20(%rbx) - 418d41: 00 - 418d42: 48 c7 43 28 00 00 00 movq $0x0,0x28(%rbx) - 418d49: 00 - 418d4a: 48 89 1d 17 1b 2b 00 mov %rbx,0x2b1b17(%rip) # 6ca868 - 418d51: 48 89 58 18 mov %rbx,0x18(%rax) - 418d55: 48 89 e8 mov %rbp,%rax - 418d58: 48 83 c8 01 or $0x1,%rax - 418d5c: 48 89 43 08 mov %rax,0x8(%rbx) - 418d60: 48 89 2c 2b mov %rbp,(%rbx,%rbp,1) - 418d64: 48 81 fd ff ff 00 00 cmp $0xffff,%rbp - 418d6b: 0f 86 af 02 00 00 jbe 419020 - 418d71: f6 05 8c 1a 2b 00 01 testb $0x1,0x2b1a8c(%rip) # 6ca804 - 418d78: 0f 84 23 05 00 00 je 4192a1 - 418d7e: 48 8b 05 d3 1a 2b 00 mov 0x2b1ad3(%rip),%rax # 6ca858 - 418d85: 48 8b 40 08 mov 0x8(%rax),%rax - 418d89: 48 83 e0 f8 and $0xfffffffffffffff8,%rax - 418d8d: 48 3b 05 0c 1a 2b 00 cmp 0x2b1a0c(%rip),%rax # 6ca7a0 - 418d94: 0f 82 86 02 00 00 jb 419020 - 418d9a: 48 8b 3d 07 1a 2b 00 mov 0x2b1a07(%rip),%rdi # 6ca7a8 - 418da1: ba 80 b0 6c 00 mov $0x6cb080,%edx - 418da6: be 58 a8 6c 00 mov $0x6ca858,%esi - 418dab: e8 f0 e5 ff ff callq 4173a0 - 418db0: e9 6b 02 00 00 jmpq 419020 - 418db5: 0f 1f 00 nopl (%rax) - 418db8: 83 3d fd 43 2b 00 00 cmpl $0x0,0x2b43fd(%rip) # 6cd1bc <__libc_multiple_threads> - 418dbf: 74 0b je 418dcc - 418dc1: f0 ff 0d 38 1a 2b 00 lock decl 0x2b1a38(%rip) # 6ca800 - 418dc8: 75 0a jne 418dd4 - 418dca: eb 22 jmp 418dee - 418dcc: ff 0d 2e 1a 2b 00 decl 0x2b1a2e(%rip) # 6ca800 - 418dd2: 74 1a je 418dee - 418dd4: 48 8d 3d 25 1a 2b 00 lea 0x2b1a25(%rip),%rdi # 6ca800 - 418ddb: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 418de2: e8 19 98 02 00 callq 442600 <__lll_unlock_wake_private> - 418de7: 48 81 c4 80 00 00 00 add $0x80,%rsp - 418dee: 48 89 df mov %rbx,%rdi - 418df1: e8 fa ee ff ff callq 417cf0 - 418df6: 48 83 c4 38 add $0x38,%rsp - 418dfa: 5b pop %rbx - 418dfb: 5d pop %rbp - 418dfc: 41 5c pop %r12 - 418dfe: 41 5d pop %r13 - 418e00: 41 5e pop %r14 - 418e02: 41 5f pop %r15 - 418e04: f3 c3 repz retq - 418e06: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 418e0d: 00 00 00 - 418e10: 8b 0d ee 19 2b 00 mov 0x2b19ee(%rip),%ecx # 6ca804 - 418e16: 83 e1 02 and $0x2,%ecx - 418e19: 75 1c jne 418e37 - 418e1b: 48 8b 35 ce 19 2b 00 mov 0x2b19ce(%rip),%rsi # 6ca7f0 - 418e22: 48 39 f3 cmp %rsi,%rbx - 418e25: 72 51 jb 418e78 - 418e27: 48 03 35 52 22 2b 00 add 0x2b2252(%rip),%rsi # 6cb080 - 418e2e: 4c 8d 0c 13 lea (%rbx,%rdx,1),%r9 - 418e32: 49 39 f1 cmp %rsi,%r9 - 418e35: 73 41 jae 418e78 - 418e37: 48 83 fa 1f cmp $0x1f,%rdx - 418e3b: 76 3b jbe 418e78 - 418e3d: a8 08 test $0x8,%al - 418e3f: 75 37 jne 418e78 - 418e41: 41 f6 44 10 f8 01 testb $0x1,-0x8(%r8,%rdx,1) - 418e47: 74 2f je 418e78 - 418e49: a8 01 test $0x1,%al - 418e4b: 0f 85 8f 00 00 00 jne 418ee0 - 418e51: 49 8b 40 f0 mov -0x10(%r8),%rax - 418e55: a8 0f test $0xf,%al - 418e57: 75 1f jne 418e78 - 418e59: 85 c9 test %ecx,%ecx - 418e5b: 48 89 d9 mov %rbx,%rcx - 418e5e: 0f 84 a4 02 00 00 je 419108 - 418e64: 48 29 c1 sub %rax,%rcx - 418e67: 48 8b 49 08 mov 0x8(%rcx),%rcx - 418e6b: 48 83 e1 f8 and $0xfffffffffffffff8,%rcx - 418e6f: 48 39 c8 cmp %rcx,%rax - 418e72: 74 6c je 418ee0 - 418e74: 0f 1f 40 00 nopl 0x0(%rax) - 418e78: 83 3d 3d 43 2b 00 00 cmpl $0x0,0x2b433d(%rip) # 6cd1bc <__libc_multiple_threads> - 418e7f: 74 0b je 418e8c - 418e81: f0 ff 0d 78 19 2b 00 lock decl 0x2b1978(%rip) # 6ca800 - 418e88: 75 0a jne 418e94 - 418e8a: eb 22 jmp 418eae - 418e8c: ff 0d 6e 19 2b 00 decl 0x2b196e(%rip) # 6ca800 - 418e92: 74 1a je 418eae - 418e94: 48 8d 3d 65 19 2b 00 lea 0x2b1965(%rip),%rdi # 6ca800 - 418e9b: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 418ea2: e8 59 97 02 00 callq 442600 <__lll_unlock_wake_private> - 418ea7: 48 81 c4 80 00 00 00 add $0x80,%rsp - 418eae: 8b 1d bc 18 2b 00 mov 0x2b18bc(%rip),%ebx # 6ca770 - 418eb4: 83 0d 49 19 2b 00 04 orl $0x4,0x2b1949(%rip) # 6ca804 - 418ebb: 89 d8 mov %ebx,%eax - 418ebd: 83 e0 05 and $0x5,%eax - 418ec0: 83 f8 05 cmp $0x5,%eax - 418ec3: 0f 84 d7 04 00 00 je 4193a0 - 418ec9: f6 c3 01 test $0x1,%bl - 418ecc: 0f 85 80 02 00 00 jne 419152 - 418ed2: 83 e3 02 and $0x2,%ebx - 418ed5: 0f 84 1b ff ff ff je 418df6 - 418edb: e8 20 4d ff ff callq 40dc00 - 418ee0: 48 83 c2 07 add $0x7,%rdx - 418ee4: 40 0f b6 ff movzbl %dil,%edi - 418ee8: 48 8d 34 13 lea (%rbx,%rdx,1),%rsi - 418eec: 0f b6 06 movzbl (%rsi),%eax - 418eef: 48 39 f8 cmp %rdi,%rax - 418ef2: 48 89 c1 mov %rax,%rcx - 418ef5: 0f 84 4d fc ff ff je 418b48 - 418efb: 48 85 c0 test %rax,%rax - 418efe: 0f 84 74 ff ff ff je 418e78 - 418f04: 48 8d 48 10 lea 0x10(%rax),%rcx - 418f08: 48 39 ca cmp %rcx,%rdx - 418f0b: 73 21 jae 418f2e - 418f0d: e9 66 ff ff ff jmpq 418e78 - 418f12: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 418f18: 48 85 c0 test %rax,%rax - 418f1b: 0f 84 57 ff ff ff je 418e78 - 418f21: 48 8d 48 10 lea 0x10(%rax),%rcx - 418f25: 48 39 d1 cmp %rdx,%rcx - 418f28: 0f 87 4a ff ff ff ja 418e78 - 418f2e: 48 29 c2 sub %rax,%rdx - 418f31: 48 8d 34 13 lea (%rbx,%rdx,1),%rsi - 418f35: 0f b6 06 movzbl (%rsi),%eax - 418f38: 48 39 f8 cmp %rdi,%rax - 418f3b: 48 89 c1 mov %rax,%rcx - 418f3e: 75 d8 jne 418f18 - 418f40: e9 03 fc ff ff jmpq 418b48 - 418f45: 0f 1f 00 nopl (%rax) - 418f48: 49 8b 44 28 f8 mov -0x8(%r8,%rbp,1),%rax - 418f4d: 48 83 f8 10 cmp $0x10,%rax - 418f51: 0f 86 a1 02 00 00 jbe 4191f8 - 418f57: 48 83 e0 f8 and $0xfffffffffffffff8,%rax - 418f5b: 48 3b 05 1e 21 2b 00 cmp 0x2b211e(%rip),%rax # 6cb080 - 418f62: 0f 83 90 02 00 00 jae 4191f8 - 418f68: 8b 35 c6 36 2b 00 mov 0x2b36c6(%rip),%esi # 6cc634 - 418f6e: 85 f6 test %esi,%esi - 418f70: 0f 85 c8 02 00 00 jne 41923e - 418f76: 64 83 3c 25 18 00 00 cmpl $0x0,%fs:0x18 - 418f7d: 00 00 - 418f7f: 74 01 je 418f82 - 418f81: f0 83 25 7b 18 2b 00 lock andl $0xfffffffe,0x2b187b(%rip) # 6ca804 - 418f88: fe - 418f89: c1 ed 04 shr $0x4,%ebp - 418f8c: be ff ff ff ff mov $0xffffffff,%esi - 418f91: 8d 45 fe lea -0x2(%rbp),%eax - 418f94: 48 8b 14 c5 08 a8 6c mov 0x6ca808(,%rax,8),%rdx - 418f9b: 00 - 418f9c: 48 89 c5 mov %rax,%rbp - 418f9f: 48 8d 0c c5 08 a8 6c lea 0x6ca808(,%rax,8),%rcx - 418fa6: 00 - 418fa7: 48 39 d3 cmp %rdx,%rbx - 418faa: 75 07 jne 418fb3 - 418fac: eb 37 jmp 418fe5 - 418fae: 66 90 xchg %ax,%ax - 418fb0: 48 89 c2 mov %rax,%rdx - 418fb3: 48 85 d2 test %rdx,%rdx - 418fb6: 74 09 je 418fc1 - 418fb8: 8b 42 08 mov 0x8(%rdx),%eax - 418fbb: c1 e8 04 shr $0x4,%eax - 418fbe: 8d 70 fe lea -0x2(%rax),%esi - 418fc1: 49 89 10 mov %rdx,(%r8) - 418fc4: 48 89 d0 mov %rdx,%rax - 418fc7: 64 83 3c 25 18 00 00 cmpl $0x0,%fs:0x18 - 418fce: 00 00 - 418fd0: 74 01 je 418fd3 - 418fd2: f0 48 0f b1 19 lock cmpxchg %rbx,(%rcx) - 418fd7: 48 39 d0 cmp %rdx,%rax - 418fda: 0f 84 30 02 00 00 je 419210 - 418fe0: 48 39 c3 cmp %rax,%rbx - 418fe3: 75 cb jne 418fb0 - 418fe5: 44 8b 2d 18 18 2b 00 mov 0x2b1818(%rip),%r13d # 6ca804 - 418fec: 41 bc 70 24 4a 00 mov $0x4a2470,%r12d - 418ff2: 8b 2d 78 17 2b 00 mov 0x2b1778(%rip),%ebp # 6ca770 - 418ff8: 41 83 cd 04 or $0x4,%r13d - 418ffc: 44 89 2d 01 18 2b 00 mov %r13d,0x2b1801(%rip) # 6ca804 - 419003: 89 e8 mov %ebp,%eax - 419005: 83 e0 05 and $0x5,%eax - 419008: 83 f8 05 cmp $0x5,%eax - 41900b: 0f 84 c7 01 00 00 je 4191d8 - 419011: 40 f6 c5 01 test $0x1,%bpl - 419015: 75 59 jne 419070 - 419017: 83 e5 02 and $0x2,%ebp - 41901a: 0f 85 bb fe ff ff jne 418edb - 419020: 83 3d 95 41 2b 00 00 cmpl $0x0,0x2b4195(%rip) # 6cd1bc <__libc_multiple_threads> - 419027: 74 0b je 419034 - 419029: f0 ff 0d d0 17 2b 00 lock decl 0x2b17d0(%rip) # 6ca800 - 419030: 75 0a jne 41903c - 419032: eb 22 jmp 419056 - 419034: ff 0d c6 17 2b 00 decl 0x2b17c6(%rip) # 6ca800 - 41903a: 74 1a je 419056 - 41903c: 48 8d 3d bd 17 2b 00 lea 0x2b17bd(%rip),%rdi # 6ca800 - 419043: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41904a: e8 b1 95 02 00 callq 442600 <__lll_unlock_wake_private> - 41904f: 48 81 c4 80 00 00 00 add $0x80,%rsp - 419056: e9 9b fd ff ff jmpq 418df6 - 41905b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 419060: 44 8b 2d 9d 17 2b 00 mov 0x2b179d(%rip),%r13d # 6ca804 - 419067: 41 bc b2 20 4a 00 mov $0x4a20b2,%r12d - 41906d: eb 83 jmp 418ff2 - 41906f: 90 nop - 419070: 48 8d 7b 10 lea 0x10(%rbx),%rdi - 419074: 4c 8d 6c 24 10 lea 0x10(%rsp),%r13 - 419079: 48 8d 74 24 20 lea 0x20(%rsp),%rsi - 41907e: 31 c9 xor %ecx,%ecx - 419080: ba 10 00 00 00 mov $0x10,%edx - 419085: c6 44 24 20 00 movb $0x0,0x20(%rsp) - 41908a: e8 21 8e 03 00 callq 451eb0 <_itoa_word> - 41908f: 4c 39 e8 cmp %r13,%rax - 419092: 48 89 c3 mov %rax,%rbx - 419095: 76 25 jbe 4190bc - 419097: 48 89 c2 mov %rax,%rdx - 41909a: 48 89 c7 mov %rax,%rdi - 41909d: be 30 00 00 00 mov $0x30,%esi - 4190a2: 4c 29 ea sub %r13,%rdx - 4190a5: 4c 8d 70 ff lea -0x1(%rax),%r14 - 4190a9: 48 29 d7 sub %rdx,%rdi - 4190ac: e8 9f 72 fe ff callq 400350 <__rela_iplt_end+0x88> - 4190b1: 48 8d 44 24 0f lea 0xf(%rsp),%rax - 4190b6: 4c 29 f0 sub %r14,%rax - 4190b9: 48 01 c3 add %rax,%rbx - 4190bc: 48 8b 05 fd 41 2b 00 mov 0x2b41fd(%rip),%rax # 6cd2c0 <__libc_argv> - 4190c3: 89 ef mov %ebp,%edi - 4190c5: ba 38 20 4a 00 mov $0x4a2038,%edx - 4190ca: 49 89 d8 mov %rbx,%r8 - 4190cd: 4c 89 e1 mov %r12,%rcx - 4190d0: be a8 23 4a 00 mov $0x4a23a8,%esi - 4190d5: 48 8b 00 mov (%rax),%rax - 4190d8: 48 85 c0 test %rax,%rax - 4190db: 48 0f 45 d0 cmovne %rax,%rdx - 4190df: 83 e7 02 and $0x2,%edi - 4190e2: 31 c0 xor %eax,%eax - 4190e4: e8 d7 84 ff ff callq 4115c0 <__libc_message> - 4190e9: e9 32 ff ff ff jmpq 419020 - 4190ee: 66 90 xchg %ax,%ax - 4190f0: 44 8b 2d 0d 17 2b 00 mov 0x2b170d(%rip),%r13d # 6ca804 - 4190f7: 41 bc ca 20 4a 00 mov $0x4a20ca,%r12d - 4190fd: e9 f0 fe ff ff jmpq 418ff2 - 419102: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 419108: 48 29 c1 sub %rax,%rcx - 41910b: 48 3b 0d de 16 2b 00 cmp 0x2b16de(%rip),%rcx # 6ca7f0 - 419112: 0f 83 4f fd ff ff jae 418e67 - 419118: e9 5b fd ff ff jmpq 418e78 - 41911d: 0f 1f 00 nopl (%rax) - 419120: 48 8d b0 00 fc ff ff lea -0x400(%rax),%rsi - 419127: 48 f7 c6 ff fb ff ff test $0xfffffffffffffbff,%rsi - 41912e: 0f 84 94 f9 ff ff je 418ac8 - 419134: 48 3d 00 10 00 00 cmp $0x1000,%rax - 41913a: 0f 84 88 f9 ff ff je 418ac8 - 419140: e9 33 fd ff ff jmpq 418e78 - 419145: 0f 1f 00 nopl (%rax) - 419148: 49 83 66 08 fe andq $0xfffffffffffffffe,0x8(%r14) - 41914d: e9 b1 fb ff ff jmpq 418d03 - 419152: 4c 8d 64 24 10 lea 0x10(%rsp),%r12 - 419157: 48 8d 74 24 20 lea 0x20(%rsp),%rsi - 41915c: 31 c9 xor %ecx,%ecx - 41915e: ba 10 00 00 00 mov $0x10,%edx - 419163: 4c 89 c7 mov %r8,%rdi - 419166: c6 44 24 20 00 movb $0x0,0x20(%rsp) - 41916b: e8 40 8d 03 00 callq 451eb0 <_itoa_word> - 419170: 4c 39 e0 cmp %r12,%rax - 419173: 48 89 c5 mov %rax,%rbp - 419176: 76 25 jbe 41919d - 419178: 48 89 c2 mov %rax,%rdx - 41917b: 48 89 c7 mov %rax,%rdi - 41917e: be 30 00 00 00 mov $0x30,%esi - 419183: 4c 29 e2 sub %r12,%rdx - 419186: 4c 8d 68 ff lea -0x1(%rax),%r13 - 41918a: 48 29 d7 sub %rdx,%rdi - 41918d: e8 be 71 fe ff callq 400350 <__rela_iplt_end+0x88> - 419192: 48 8d 44 24 0f lea 0xf(%rsp),%rax - 419197: 4c 29 e8 sub %r13,%rax - 41919a: 48 01 c5 add %rax,%rbp - 41919d: 48 8b 05 1c 41 2b 00 mov 0x2b411c(%rip),%rax # 6cd2c0 <__libc_argv> - 4191a4: ba 38 20 4a 00 mov $0x4a2038,%edx - 4191a9: 49 89 e8 mov %rbp,%r8 - 4191ac: b9 b2 20 4a 00 mov $0x4a20b2,%ecx - 4191b1: be a8 23 4a 00 mov $0x4a23a8,%esi - 4191b6: 48 8b 00 mov (%rax),%rax - 4191b9: 48 85 c0 test %rax,%rax - 4191bc: 48 0f 45 d0 cmovne %rax,%rdx - 4191c0: 83 e3 02 and $0x2,%ebx - 4191c3: 31 c0 xor %eax,%eax - 4191c5: 89 df mov %ebx,%edi - 4191c7: e8 f4 83 ff ff callq 4115c0 <__libc_message> - 4191cc: e9 25 fc ff ff jmpq 418df6 - 4191d1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4191d8: 89 ef mov %ebp,%edi - 4191da: 4c 89 e2 mov %r12,%rdx - 4191dd: be 3c ca 4b 00 mov $0x4bca3c,%esi - 4191e2: 83 e7 02 and $0x2,%edi - 4191e5: 31 c0 xor %eax,%eax - 4191e7: e8 d4 83 ff ff callq 4115c0 <__libc_message> - 4191ec: e9 2f fe ff ff jmpq 419020 - 4191f1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4191f8: 44 8b 2d 05 16 2b 00 mov 0x2b1605(%rip),%r13d # 6ca804 - 4191ff: 41 bc 20 24 4a 00 mov $0x4a2420,%r12d - 419205: e9 e8 fd ff ff jmpq 418ff2 - 41920a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 419210: 39 f5 cmp %esi,%ebp - 419212: 0f 84 08 fe ff ff je 419020 - 419218: 48 85 d2 test %rdx,%rdx - 41921b: 44 8b 2d e2 15 2b 00 mov 0x2b15e2(%rip),%r13d # 6ca804 - 419222: 41 bc df 20 4a 00 mov $0x4a20df,%r12d - 419228: 0f 84 f2 fd ff ff je 419020 - 41922e: e9 bf fd ff ff jmpq 418ff2 - 419233: 41 bc 00 25 4a 00 mov $0x4a2500,%r12d - 419239: e9 b4 fd ff ff jmpq 418ff2 - 41923e: 48 8d 55 f0 lea -0x10(%rbp),%rdx - 419242: 4c 89 c7 mov %r8,%rdi - 419245: e8 06 71 fe ff callq 400350 <__rela_iplt_end+0x88> - 41924a: 49 89 c0 mov %rax,%r8 - 41924d: e9 24 fd ff ff jmpq 418f76 - 419252: 41 bc 98 24 4a 00 mov $0x4a2498,%r12d - 419258: e9 95 fd ff ff jmpq 418ff2 - 41925d: 4c 01 fd add %r15,%rbp - 419260: 48 89 e8 mov %rbp,%rax - 419263: 48 83 c8 01 or $0x1,%rax - 419267: 48 89 43 08 mov %rax,0x8(%rbx) - 41926b: 48 89 1d e6 15 2b 00 mov %rbx,0x2b15e6(%rip) # 6ca858 - 419272: e9 ed fa ff ff jmpq 418d64 - 419277: 48 8b 50 08 mov 0x8(%rax),%rdx - 41927b: 48 83 e2 f8 and $0xfffffffffffffff8,%rdx - 41927f: 48 01 d0 add %rdx,%rax - 419282: 49 39 c6 cmp %rax,%r14 - 419285: 0f 82 3d f9 ff ff jb 418bc8 - 41928b: 41 bc b8 24 4a 00 mov $0x4a24b8,%r12d - 419291: e9 5c fd ff ff jmpq 418ff2 - 419296: 41 bc d8 24 4a 00 mov $0x4a24d8,%r12d - 41929c: e9 51 fd ff ff jmpq 418ff2 - 4192a1: bf 00 a8 6c 00 mov $0x6ca800,%edi - 4192a6: e8 85 eb ff ff callq 417e30 - 4192ab: e9 ce fa ff ff jmpq 418d7e - 4192b0: 48 8d 55 f0 lea -0x10(%rbp),%rdx - 4192b4: 4c 89 c7 mov %r8,%rdi - 4192b7: e8 94 70 fe ff callq 400350 <__rela_iplt_end+0x88> - 4192bc: 49 89 c0 mov %rax,%r8 - 4192bf: e9 3c f9 ff ff jmpq 418c00 - 4192c4: 44 8b 0d a5 14 2b 00 mov 0x2b14a5(%rip),%r9d # 6ca770 - 4192cb: 83 0d 32 15 2b 00 04 orl $0x4,0x2b1532(%rip) # 6ca804 - 4192d2: 44 89 c8 mov %r9d,%eax - 4192d5: 83 e0 05 and $0x5,%eax - 4192d8: 83 f8 05 cmp $0x5,%eax - 4192db: 0f 84 d2 03 00 00 je 4196b3 - 4192e1: 41 f6 c1 01 test $0x1,%r9b - 4192e5: 0f 85 31 01 00 00 jne 41941c - 4192eb: 41 83 e1 02 and $0x2,%r9d - 4192ef: 0f 84 a3 f9 ff ff je 418c98 - 4192f5: e9 e1 fb ff ff jmpq 418edb - 4192fa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 419300: 44 8b 2d 69 14 2b 00 mov 0x2b1469(%rip),%r13d # 6ca770 - 419307: 83 0d f6 14 2b 00 04 orl $0x4,0x2b14f6(%rip) # 6ca804 - 41930e: 44 89 e8 mov %r13d,%eax - 419311: 83 e0 05 and $0x5,%eax - 419314: 83 f8 05 cmp $0x5,%eax - 419317: 0f 84 7a 03 00 00 je 419697 - 41931d: 41 f6 c5 01 test $0x1,%r13b - 419321: 0f 85 8c 01 00 00 jne 4194b3 - 419327: 41 83 e5 02 and $0x2,%r13d - 41932b: 0f 84 cf f9 ff ff je 418d00 - 419331: e9 a5 fb ff ff jmpq 418edb - 419336: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41933d: 00 00 00 - 419340: 44 8b 0d 29 14 2b 00 mov 0x2b1429(%rip),%r9d # 6ca770 - 419347: 41 83 cd 04 or $0x4,%r13d - 41934b: 44 89 2d b2 14 2b 00 mov %r13d,0x2b14b2(%rip) # 6ca804 - 419352: 44 89 c8 mov %r9d,%eax - 419355: 83 e0 05 and $0x5,%eax - 419358: 83 f8 05 cmp $0x5,%eax - 41935b: 0f 84 bb 03 00 00 je 41971c - 419361: 41 f6 c1 01 test $0x1,%r9b - 419365: 0f 85 09 02 00 00 jne 419574 - 41936b: 41 f6 c1 02 test $0x2,%r9b - 41936f: 0f 85 66 fb ff ff jne 418edb - 419375: 4c 8b 63 10 mov 0x10(%rbx),%r12 - 419379: 48 8b 43 18 mov 0x18(%rbx),%rax - 41937d: 49 39 5c 24 18 cmp %rbx,0x18(%r12) - 419382: 0f 85 63 ff ff ff jne 4192eb - 419388: 48 3b 58 10 cmp 0x10(%rax),%rbx - 41938c: 0f 84 b1 f8 ff ff je 418c43 - 419392: 44 89 2d 6b 14 2b 00 mov %r13d,0x2b146b(%rip) # 6ca804 - 419399: e9 43 ff ff ff jmpq 4192e1 - 41939e: 66 90 xchg %ax,%ax - 4193a0: 83 e3 02 and $0x2,%ebx - 4193a3: ba b2 20 4a 00 mov $0x4a20b2,%edx - 4193a8: be 3c ca 4b 00 mov $0x4bca3c,%esi - 4193ad: 89 df mov %ebx,%edi - 4193af: 31 c0 xor %eax,%eax - 4193b1: e8 0a 82 ff ff callq 4115c0 <__libc_message> - 4193b6: e9 3b fa ff ff jmpq 418df6 - 4193bb: 44 8b 2d ae 13 2b 00 mov 0x2b13ae(%rip),%r13d # 6ca770 - 4193c2: 8b 15 3c 14 2b 00 mov 0x2b143c(%rip),%edx # 6ca804 - 4193c8: 44 89 e8 mov %r13d,%eax - 4193cb: 83 ca 04 or $0x4,%edx - 4193ce: 83 e0 05 and $0x5,%eax - 4193d1: 89 15 2d 14 2b 00 mov %edx,0x2b142d(%rip) # 6ca804 - 4193d7: 83 f8 05 cmp $0x5,%eax - 4193da: 0f 84 58 03 00 00 je 419738 - 4193e0: 41 f6 c5 01 test $0x1,%r13b - 4193e4: 0f 85 21 02 00 00 jne 41960b - 4193ea: 41 f6 c5 02 test $0x2,%r13b - 4193ee: 0f 85 e7 fa ff ff jne 418edb - 4193f4: 4d 8b 66 10 mov 0x10(%r14),%r12 - 4193f8: 49 8b 46 18 mov 0x18(%r14),%rax - 4193fc: 4d 3b 74 24 18 cmp 0x18(%r12),%r14 - 419401: 0f 85 20 ff ff ff jne 419327 - 419407: 4c 3b 70 10 cmp 0x10(%rax),%r14 - 41940b: 0f 84 cf f8 ff ff je 418ce0 - 419411: 89 15 ed 13 2b 00 mov %edx,0x2b13ed(%rip) # 6ca804 - 419417: e9 01 ff ff ff jmpq 41931d - 41941c: 4c 8d 64 24 10 lea 0x10(%rsp),%r12 - 419421: 48 8d 74 24 20 lea 0x20(%rsp),%rsi - 419426: 31 c9 xor %ecx,%ecx - 419428: ba 10 00 00 00 mov $0x10,%edx - 41942d: 48 89 df mov %rbx,%rdi - 419430: 44 89 0c 24 mov %r9d,(%rsp) - 419434: c6 44 24 20 00 movb $0x0,0x20(%rsp) - 419439: e8 72 8a 03 00 callq 451eb0 <_itoa_word> - 41943e: 4c 39 e0 cmp %r12,%rax - 419441: 49 89 c5 mov %rax,%r13 - 419444: 44 8b 0c 24 mov (%rsp),%r9d - 419448: 76 34 jbe 41947e - 41944a: 4c 89 ea mov %r13,%rdx - 41944d: 48 8d 40 ff lea -0x1(%rax),%rax - 419451: 4c 89 ef mov %r13,%rdi - 419454: 4c 29 e2 sub %r12,%rdx - 419457: be 30 00 00 00 mov $0x30,%esi - 41945c: 44 89 4c 24 08 mov %r9d,0x8(%rsp) - 419461: 48 29 d7 sub %rdx,%rdi - 419464: 48 89 04 24 mov %rax,(%rsp) - 419468: e8 e3 6e fe ff callq 400350 <__rela_iplt_end+0x88> - 41946d: 48 8d 44 24 0f lea 0xf(%rsp),%rax - 419472: 48 2b 04 24 sub (%rsp),%rax - 419476: 44 8b 4c 24 08 mov 0x8(%rsp),%r9d - 41947b: 49 01 c5 add %rax,%r13 - 41947e: 48 8b 05 3b 3e 2b 00 mov 0x2b3e3b(%rip),%rax # 6cd2c0 <__libc_argv> - 419485: 44 89 cf mov %r9d,%edi - 419488: ba 38 20 4a 00 mov $0x4a2038,%edx - 41948d: 4d 89 e8 mov %r13,%r8 - 419490: b9 95 20 4a 00 mov $0x4a2095,%ecx - 419495: be a8 23 4a 00 mov $0x4a23a8,%esi - 41949a: 48 8b 00 mov (%rax),%rax - 41949d: 48 85 c0 test %rax,%rax - 4194a0: 48 0f 45 d0 cmovne %rax,%rdx - 4194a4: 83 e7 02 and $0x2,%edi - 4194a7: 31 c0 xor %eax,%eax - 4194a9: e8 12 81 ff ff callq 4115c0 <__libc_message> - 4194ae: e9 e5 f7 ff ff jmpq 418c98 - 4194b3: 4c 8d 44 24 10 lea 0x10(%rsp),%r8 - 4194b8: 48 8d 74 24 20 lea 0x20(%rsp),%rsi - 4194bd: 31 c9 xor %ecx,%ecx - 4194bf: ba 10 00 00 00 mov $0x10,%edx - 4194c4: 4c 89 f7 mov %r14,%rdi - 4194c7: c6 44 24 20 00 movb $0x0,0x20(%rsp) - 4194cc: 4c 89 04 24 mov %r8,(%rsp) - 4194d0: e8 db 89 03 00 callq 451eb0 <_itoa_word> - 4194d5: 4c 8b 04 24 mov (%rsp),%r8 - 4194d9: 49 89 c4 mov %rax,%r12 - 4194dc: 4c 39 c0 cmp %r8,%rax - 4194df: 76 25 jbe 419506 - 4194e1: 48 89 c2 mov %rax,%rdx - 4194e4: 48 89 c7 mov %rax,%rdi - 4194e7: be 30 00 00 00 mov $0x30,%esi - 4194ec: 4c 29 c2 sub %r8,%rdx - 4194ef: 4c 8d 70 ff lea -0x1(%rax),%r14 - 4194f3: 48 29 d7 sub %rdx,%rdi - 4194f6: e8 55 6e fe ff callq 400350 <__rela_iplt_end+0x88> - 4194fb: 48 8d 44 24 0f lea 0xf(%rsp),%rax - 419500: 4c 29 f0 sub %r14,%rax - 419503: 49 01 c4 add %rax,%r12 - 419506: 48 8b 05 b3 3d 2b 00 mov 0x2b3db3(%rip),%rax # 6cd2c0 <__libc_argv> - 41950d: 44 89 ef mov %r13d,%edi - 419510: ba 38 20 4a 00 mov $0x4a2038,%edx - 419515: 4d 89 e0 mov %r12,%r8 - 419518: b9 95 20 4a 00 mov $0x4a2095,%ecx - 41951d: be a8 23 4a 00 mov $0x4a23a8,%esi - 419522: 48 8b 00 mov (%rax),%rax - 419525: 48 85 c0 test %rax,%rax - 419528: 48 0f 45 d0 cmovne %rax,%rdx - 41952c: 83 e7 02 and $0x2,%edi - 41952f: 31 c0 xor %eax,%eax - 419531: e8 8a 80 ff ff callq 4115c0 <__libc_message> - 419536: e9 c5 f7 ff ff jmpq 418d00 - 41953b: 4c 3b 70 28 cmp 0x28(%rax),%r14 - 41953f: 0f 85 37 02 00 00 jne 41977c - 419545: 49 8b 56 28 mov 0x28(%r14),%rdx - 419549: 4c 3b 72 20 cmp 0x20(%rdx),%r14 - 41954d: 0f 85 29 02 00 00 jne 41977c - 419553: 49 83 7c 24 20 00 cmpq $0x0,0x20(%r12) - 419559: 0f 84 f5 01 00 00 je 419754 - 41955f: 49 8b 56 28 mov 0x28(%r14),%rdx - 419563: 48 89 50 28 mov %rdx,0x28(%rax) - 419567: 49 8b 56 28 mov 0x28(%r14),%rdx - 41956b: 48 89 42 20 mov %rax,0x20(%rdx) - 41956f: e9 8c f7 ff ff jmpq 418d00 - 419574: 4c 8d 64 24 10 lea 0x10(%rsp),%r12 - 419579: 48 8d 74 24 20 lea 0x20(%rsp),%rsi - 41957e: 31 c9 xor %ecx,%ecx - 419580: ba 10 00 00 00 mov $0x10,%edx - 419585: 48 89 df mov %rbx,%rdi - 419588: 44 89 0c 24 mov %r9d,(%rsp) - 41958c: c6 44 24 20 00 movb $0x0,0x20(%rsp) - 419591: e8 1a 89 03 00 callq 451eb0 <_itoa_word> - 419596: 4c 39 e0 cmp %r12,%rax - 419599: 49 89 c5 mov %rax,%r13 - 41959c: 44 8b 0c 24 mov (%rsp),%r9d - 4195a0: 76 34 jbe 4195d6 - 4195a2: 4c 89 ea mov %r13,%rdx - 4195a5: 48 8d 40 ff lea -0x1(%rax),%rax - 4195a9: 4c 89 ef mov %r13,%rdi - 4195ac: 4c 29 e2 sub %r12,%rdx - 4195af: be 30 00 00 00 mov $0x30,%esi - 4195b4: 44 89 4c 24 08 mov %r9d,0x8(%rsp) - 4195b9: 48 29 d7 sub %rdx,%rdi - 4195bc: 48 89 04 24 mov %rax,(%rsp) - 4195c0: e8 8b 6d fe ff callq 400350 <__rela_iplt_end+0x88> - 4195c5: 48 8d 44 24 0f lea 0xf(%rsp),%rax - 4195ca: 48 2b 04 24 sub (%rsp),%rax - 4195ce: 44 8b 4c 24 08 mov 0x8(%rsp),%r9d - 4195d3: 49 01 c5 add %rax,%r13 - 4195d6: 48 8b 05 e3 3c 2b 00 mov 0x2b3ce3(%rip),%rax # 6cd2c0 <__libc_argv> - 4195dd: 44 89 cf mov %r9d,%edi - 4195e0: ba 38 20 4a 00 mov $0x4a2038,%edx - 4195e5: 4d 89 e8 mov %r13,%r8 - 4195e8: b9 78 20 4a 00 mov $0x4a2078,%ecx - 4195ed: be a8 23 4a 00 mov $0x4a23a8,%esi - 4195f2: 48 8b 00 mov (%rax),%rax - 4195f5: 48 85 c0 test %rax,%rax - 4195f8: 48 0f 45 d0 cmovne %rax,%rdx - 4195fc: 83 e7 02 and $0x2,%edi - 4195ff: 31 c0 xor %eax,%eax - 419601: e8 ba 7f ff ff callq 4115c0 <__libc_message> - 419606: e9 1b f6 ff ff jmpq 418c26 - 41960b: 4c 8d 64 24 10 lea 0x10(%rsp),%r12 - 419610: 48 8d 74 24 20 lea 0x20(%rsp),%rsi - 419615: 31 c9 xor %ecx,%ecx - 419617: ba 10 00 00 00 mov $0x10,%edx - 41961c: 4c 89 f7 mov %r14,%rdi - 41961f: c6 44 24 20 00 movb $0x0,0x20(%rsp) - 419624: e8 87 88 03 00 callq 451eb0 <_itoa_word> - 419629: 4c 39 e0 cmp %r12,%rax - 41962c: 49 89 c0 mov %rax,%r8 - 41962f: 76 34 jbe 419665 - 419631: 4c 89 c2 mov %r8,%rdx - 419634: 4c 89 c7 mov %r8,%rdi - 419637: 48 8d 40 ff lea -0x1(%rax),%rax - 41963b: 4c 29 e2 sub %r12,%rdx - 41963e: be 30 00 00 00 mov $0x30,%esi - 419643: 4c 89 44 24 08 mov %r8,0x8(%rsp) - 419648: 48 29 d7 sub %rdx,%rdi - 41964b: 48 89 04 24 mov %rax,(%rsp) - 41964f: e8 fc 6c fe ff callq 400350 <__rela_iplt_end+0x88> - 419654: 48 8d 44 24 0f lea 0xf(%rsp),%rax - 419659: 48 2b 04 24 sub (%rsp),%rax - 41965d: 4c 8b 44 24 08 mov 0x8(%rsp),%r8 - 419662: 49 01 c0 add %rax,%r8 - 419665: 48 8b 05 54 3c 2b 00 mov 0x2b3c54(%rip),%rax # 6cd2c0 <__libc_argv> - 41966c: 44 89 ef mov %r13d,%edi - 41966f: ba 38 20 4a 00 mov $0x4a2038,%edx - 419674: b9 78 20 4a 00 mov $0x4a2078,%ecx - 419679: be a8 23 4a 00 mov $0x4a23a8,%esi - 41967e: 48 8b 00 mov (%rax),%rax - 419681: 48 85 c0 test %rax,%rax - 419684: 48 0f 45 d0 cmovne %rax,%rdx - 419688: 83 e7 02 and $0x2,%edi - 41968b: 31 c0 xor %eax,%eax - 41968d: e8 2e 7f ff ff callq 4115c0 <__libc_message> - 419692: e9 2c f6 ff ff jmpq 418cc3 - 419697: 44 89 ef mov %r13d,%edi - 41969a: ba 95 20 4a 00 mov $0x4a2095,%edx - 41969f: be 3c ca 4b 00 mov $0x4bca3c,%esi - 4196a4: 83 e7 02 and $0x2,%edi - 4196a7: 31 c0 xor %eax,%eax - 4196a9: e8 12 7f ff ff callq 4115c0 <__libc_message> - 4196ae: e9 4d f6 ff ff jmpq 418d00 - 4196b3: 44 89 cf mov %r9d,%edi - 4196b6: ba 95 20 4a 00 mov $0x4a2095,%edx - 4196bb: be 3c ca 4b 00 mov $0x4bca3c,%esi - 4196c0: 83 e7 02 and $0x2,%edi - 4196c3: 31 c0 xor %eax,%eax - 4196c5: e8 f6 7e ff ff callq 4115c0 <__libc_message> - 4196ca: e9 c9 f5 ff ff jmpq 418c98 - 4196cf: 48 39 c3 cmp %rax,%rbx - 4196d2: 0f 84 c5 00 00 00 je 41979d - 4196d8: 49 89 44 24 20 mov %rax,0x20(%r12) - 4196dd: 48 8b 43 28 mov 0x28(%rbx),%rax - 4196e1: 49 89 44 24 28 mov %rax,0x28(%r12) - 4196e6: 48 8b 43 20 mov 0x20(%rbx),%rax - 4196ea: 4c 89 60 28 mov %r12,0x28(%rax) - 4196ee: 48 8b 43 28 mov 0x28(%rbx),%rax - 4196f2: 4c 89 60 20 mov %r12,0x20(%rax) - 4196f6: e9 9d f5 ff ff jmpq 418c98 - 4196fb: 8b 3d 6f 10 2b 00 mov 0x2b106f(%rip),%edi # 6ca770 - 419701: b9 00 a8 6c 00 mov $0x6ca800,%ecx - 419706: 48 89 da mov %rbx,%rdx - 419709: be f0 23 4a 00 mov $0x4a23f0,%esi - 41970e: e8 9d db ff ff callq 4172b0 - 419713: 48 8b 43 20 mov 0x20(%rbx),%rax - 419717: e9 5b f5 ff ff jmpq 418c77 - 41971c: 44 89 cf mov %r9d,%edi - 41971f: ba 78 20 4a 00 mov $0x4a2078,%edx - 419724: be 3c ca 4b 00 mov $0x4bca3c,%esi - 419729: 83 e7 02 and $0x2,%edi - 41972c: 31 c0 xor %eax,%eax - 41972e: e8 8d 7e ff ff callq 4115c0 <__libc_message> - 419733: e9 ee f4 ff ff jmpq 418c26 - 419738: 44 89 ef mov %r13d,%edi - 41973b: ba 78 20 4a 00 mov $0x4a2078,%edx - 419740: be 3c ca 4b 00 mov $0x4bca3c,%esi - 419745: 83 e7 02 and $0x2,%edi - 419748: 31 c0 xor %eax,%eax - 41974a: e8 71 7e ff ff callq 4115c0 <__libc_message> - 41974f: e9 6f f5 ff ff jmpq 418cc3 - 419754: 49 39 c6 cmp %rax,%r14 - 419757: 74 53 je 4197ac - 419759: 49 89 44 24 20 mov %rax,0x20(%r12) - 41975e: 49 8b 46 28 mov 0x28(%r14),%rax - 419762: 49 89 44 24 28 mov %rax,0x28(%r12) - 419767: 49 8b 46 20 mov 0x20(%r14),%rax - 41976b: 4c 89 60 28 mov %r12,0x28(%rax) - 41976f: 49 8b 46 28 mov 0x28(%r14),%rax - 419773: 4c 89 60 20 mov %r12,0x20(%rax) - 419777: e9 84 f5 ff ff jmpq 418d00 - 41977c: 8b 3d ee 0f 2b 00 mov 0x2b0fee(%rip),%edi # 6ca770 - 419782: b9 00 a8 6c 00 mov $0x6ca800,%ecx - 419787: 4c 89 f2 mov %r14,%rdx - 41978a: be f0 23 4a 00 mov $0x4a23f0,%esi - 41978f: e8 1c db ff ff callq 4172b0 - 419794: 49 8b 46 20 mov 0x20(%r14),%rax - 419798: e9 b6 fd ff ff jmpq 419553 - 41979d: 4d 89 64 24 28 mov %r12,0x28(%r12) - 4197a2: 4d 89 64 24 20 mov %r12,0x20(%r12) - 4197a7: e9 ec f4 ff ff jmpq 418c98 - 4197ac: 4d 89 64 24 28 mov %r12,0x28(%r12) - 4197b1: 4d 89 64 24 20 mov %r12,0x20(%r12) - 4197b6: e9 45 f5 ff ff jmpq 418d00 - 4197bb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - -00000000004197c0 <_int_free>: - 4197c0: 41 57 push %r15 - 4197c2: 41 56 push %r14 - 4197c4: 41 55 push %r13 - 4197c6: 41 54 push %r12 - 4197c8: 55 push %rbp - 4197c9: 53 push %rbx - 4197ca: 48 89 fd mov %rdi,%rbp - 4197cd: 48 89 f3 mov %rsi,%rbx - 4197d0: 48 83 ec 58 sub $0x58,%rsp - 4197d4: 48 8b 46 08 mov 0x8(%rsi),%rax - 4197d8: 89 54 24 04 mov %edx,0x4(%rsp) - 4197dc: 49 89 c4 mov %rax,%r12 - 4197df: 49 83 e4 f8 and $0xfffffffffffffff8,%r12 - 4197e3: 4c 89 e2 mov %r12,%rdx - 4197e6: 48 f7 da neg %rdx - 4197e9: 48 39 d6 cmp %rdx,%rsi - 4197ec: 0f 87 4e 05 00 00 ja 419d40 <_int_free+0x580> - 4197f2: 40 f6 c6 0f test $0xf,%sil - 4197f6: 0f 85 44 05 00 00 jne 419d40 <_int_free+0x580> - 4197fc: 49 83 fc 1f cmp $0x1f,%r12 - 419800: 0f 86 d2 05 00 00 jbe 419dd8 <_int_free+0x618> - 419806: a8 08 test $0x8,%al - 419808: 0f 85 ca 05 00 00 jne 419dd8 <_int_free+0x618> - 41980e: 4c 3b 25 23 2e 2b 00 cmp 0x2b2e23(%rip),%r12 # 6cc638 - 419815: 0f 87 05 01 00 00 ja 419920 <_int_free+0x160> - 41981b: 4a 8d 14 26 lea (%rsi,%r12,1),%rdx - 41981f: 48 8b 42 08 mov 0x8(%rdx),%rax - 419823: 48 83 f8 10 cmp $0x10,%rax - 419827: 0f 86 a3 07 00 00 jbe 419fd0 <_int_free+0x810> - 41982d: 48 83 e0 f8 and $0xfffffffffffffff8,%rax - 419831: 48 3b 87 80 08 00 00 cmp 0x880(%rdi),%rax - 419838: 0f 83 92 07 00 00 jae 419fd0 <_int_free+0x810> - 41983e: 8b 35 f0 2d 2b 00 mov 0x2b2df0(%rip),%esi # 6cc634 - 419844: 4c 8d 43 10 lea 0x10(%rbx),%r8 - 419848: 85 f6 test %esi,%esi - 41984a: 0f 85 50 0a 00 00 jne 41a2a0 <_int_free+0xae0> - 419850: 64 83 3c 25 18 00 00 cmpl $0x0,%fs:0x18 - 419857: 00 00 - 419859: 74 01 je 41985c <_int_free+0x9c> - 41985b: f0 83 65 04 fe lock andl $0xfffffffe,0x4(%rbp) - 419860: 41 c1 ec 04 shr $0x4,%r12d - 419864: 41 8d 44 24 fe lea -0x2(%r12),%eax - 419869: 48 8b 54 c5 08 mov 0x8(%rbp,%rax,8),%rdx - 41986e: 49 89 c4 mov %rax,%r12 - 419871: 48 8d 74 c5 08 lea 0x8(%rbp,%rax,8),%rsi - 419876: 48 39 d3 cmp %rdx,%rbx - 419879: 74 51 je 4198cc <_int_free+0x10c> - 41987b: 8b 7c 24 04 mov 0x4(%rsp),%edi - 41987f: 85 ff test %edi,%edi - 419881: bf ff ff ff ff mov $0xffffffff,%edi - 419886: 41 0f 95 c1 setne %r9b - 41988a: eb 07 jmp 419893 <_int_free+0xd3> - 41988c: 0f 1f 40 00 nopl 0x0(%rax) - 419890: 48 89 c2 mov %rax,%rdx - 419893: 48 85 d2 test %rdx,%rdx - 419896: 0f 95 c1 setne %cl - 419899: 44 20 c9 and %r9b,%cl - 41989c: 74 09 je 4198a7 <_int_free+0xe7> - 41989e: 8b 7a 08 mov 0x8(%rdx),%edi - 4198a1: c1 ef 04 shr $0x4,%edi - 4198a4: 83 ef 02 sub $0x2,%edi - 4198a7: 48 89 53 10 mov %rdx,0x10(%rbx) - 4198ab: 48 89 d0 mov %rdx,%rax - 4198ae: 64 83 3c 25 18 00 00 cmpl $0x0,%fs:0x18 - 4198b5: 00 00 - 4198b7: 74 01 je 4198ba <_int_free+0xfa> - 4198b9: f0 48 0f b1 1e lock cmpxchg %rbx,(%rsi) - 4198be: 48 39 d0 cmp %rdx,%rax - 4198c1: 0f 84 59 06 00 00 je 419f20 <_int_free+0x760> - 4198c7: 48 39 c3 cmp %rax,%rbx - 4198ca: 75 c4 jne 419890 <_int_free+0xd0> - 4198cc: 4c 89 c7 mov %r8,%rdi - 4198cf: 41 bd 70 24 4a 00 mov $0x4a2470,%r13d - 4198d5: 0f 1f 00 nopl (%rax) - 4198d8: 48 85 ed test %rbp,%rbp - 4198db: 44 8b 25 8e 0e 2b 00 mov 0x2b0e8e(%rip),%r12d # 6ca770 - 4198e2: 74 04 je 4198e8 <_int_free+0x128> - 4198e4: 83 4d 04 04 orl $0x4,0x4(%rbp) - 4198e8: 44 89 e0 mov %r12d,%eax - 4198eb: 83 e0 05 and $0x5,%eax - 4198ee: 83 f8 05 cmp $0x5,%eax - 4198f1: 0f 84 b9 06 00 00 je 419fb0 <_int_free+0x7f0> - 4198f7: 41 f6 c4 01 test $0x1,%r12b - 4198fb: 0f 85 4f 04 00 00 jne 419d50 <_int_free+0x590> - 419901: 41 83 e4 02 and $0x2,%r12d - 419905: 0f 85 99 08 00 00 jne 41a1a4 <_int_free+0x9e4> - 41990b: 48 83 c4 58 add $0x58,%rsp - 41990f: 5b pop %rbx - 419910: 5d pop %rbp - 419911: 41 5c pop %r12 - 419913: 41 5d pop %r13 - 419915: 41 5e pop %r14 - 419917: 41 5f pop %r15 - 419919: c3 retq - 41991a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 419920: a8 02 test $0x2,%al - 419922: 0f 85 e8 05 00 00 jne 419f10 <_int_free+0x750> - 419928: 8b 44 24 04 mov 0x4(%rsp),%eax - 41992c: 85 c0 test %eax,%eax - 41992e: 0f 84 ac 03 00 00 je 419ce0 <_int_free+0x520> - 419934: 48 8b 47 58 mov 0x58(%rdi),%rax - 419938: 4e 8d 2c 26 lea (%rsi,%r12,1),%r13 - 41993c: 48 39 c6 cmp %rax,%rsi - 41993f: 0f 84 b1 12 00 00 je 41abf6 <_int_free+0x1436> - 419945: 45 31 c9 xor %r9d,%r9d - 419948: c7 44 24 28 00 00 00 movl $0x0,0x28(%rsp) - 41994f: 00 - 419950: f6 45 04 02 testb $0x2,0x4(%rbp) - 419954: 0f 84 d6 09 00 00 je 41a330 <_int_free+0xb70> - 41995a: 49 8b 45 08 mov 0x8(%r13),%rax - 41995e: a8 01 test $0x1,%al - 419960: 0f 84 ea 09 00 00 je 41a350 <_int_free+0xb90> - 419966: 49 89 c7 mov %rax,%r15 - 419969: 49 83 e7 f8 and $0xfffffffffffffff8,%r15 - 41996d: 48 83 f8 10 cmp $0x10,%rax - 419971: 0f 86 39 08 00 00 jbe 41a1b0 <_int_free+0x9f0> - 419977: 4c 3b bd 80 08 00 00 cmp 0x880(%rbp),%r15 - 41997e: 0f 83 2c 08 00 00 jae 41a1b0 <_int_free+0x9f0> - 419984: 8b 35 aa 2c 2b 00 mov 0x2b2caa(%rip),%esi # 6cc634 - 41998a: 85 f6 test %esi,%esi - 41998c: 0f 85 c9 09 00 00 jne 41a35b <_int_free+0xb9b> - 419992: f6 43 08 01 testb $0x1,0x8(%rbx) - 419996: 0f 85 8c 00 00 00 jne 419a28 <_int_free+0x268> - 41999c: 48 8b 03 mov (%rbx),%rax - 41999f: 48 29 c3 sub %rax,%rbx - 4199a2: 49 01 c4 add %rax,%r12 - 4199a5: 48 8b 43 08 mov 0x8(%rbx),%rax - 4199a9: 48 83 e0 f8 and $0xfffffffffffffff8,%rax - 4199ad: 48 3b 04 03 cmp (%rbx,%rax,1),%rax - 4199b1: 0f 85 54 0a 00 00 jne 41a40b <_int_free+0xc4b> - 4199b7: 48 8b 43 10 mov 0x10(%rbx),%rax - 4199bb: 48 8b 53 18 mov 0x18(%rbx),%rdx - 4199bf: 48 3b 58 18 cmp 0x18(%rax),%rbx - 4199c3: 0f 85 b0 09 00 00 jne 41a379 <_int_free+0xbb9> - 4199c9: 48 3b 5a 10 cmp 0x10(%rdx),%rbx - 4199cd: 0f 85 a6 09 00 00 jne 41a379 <_int_free+0xbb9> - 4199d3: 48 81 7b 08 ff 03 00 cmpq $0x3ff,0x8(%rbx) - 4199da: 00 - 4199db: 48 89 50 18 mov %rdx,0x18(%rax) - 4199df: 48 89 42 10 mov %rax,0x10(%rdx) - 4199e3: 76 43 jbe 419a28 <_int_free+0x268> - 4199e5: 48 8b 53 20 mov 0x20(%rbx),%rdx - 4199e9: 48 85 d2 test %rdx,%rdx - 4199ec: 74 3a je 419a28 <_int_free+0x268> - 4199ee: 48 3b 5a 28 cmp 0x28(%rdx),%rbx - 4199f2: 0f 85 c3 10 00 00 jne 41aabb <_int_free+0x12fb> - 4199f8: 48 8b 4b 28 mov 0x28(%rbx),%rcx - 4199fc: 48 3b 59 20 cmp 0x20(%rcx),%rbx - 419a00: 0f 85 b5 10 00 00 jne 41aabb <_int_free+0x12fb> - 419a06: 48 83 78 20 00 cmpq $0x0,0x20(%rax) - 419a0b: 0f 84 ff 10 00 00 je 41ab10 <_int_free+0x1350> - 419a11: 48 8b 43 28 mov 0x28(%rbx),%rax - 419a15: 48 89 42 28 mov %rax,0x28(%rdx) - 419a19: 48 8b 43 28 mov 0x28(%rbx),%rax - 419a1d: 48 89 50 20 mov %rdx,0x20(%rax) - 419a21: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 419a28: 4c 39 6d 58 cmp %r13,0x58(%rbp) - 419a2c: 0f 84 e6 08 00 00 je 41a318 <_int_free+0xb58> - 419a32: 43 f6 44 3d 08 01 testb $0x1,0x8(%r13,%r15,1) - 419a38: 0f 85 62 05 00 00 jne 419fa0 <_int_free+0x7e0> - 419a3e: 49 8b 45 08 mov 0x8(%r13),%rax - 419a42: 48 83 e0 f8 and $0xfffffffffffffff8,%rax - 419a46: 49 3b 44 05 00 cmp 0x0(%r13,%rax,1),%rax - 419a4b: 0f 85 0f 0a 00 00 jne 41a460 <_int_free+0xca0> - 419a51: 49 8b 45 10 mov 0x10(%r13),%rax - 419a55: 49 8b 55 18 mov 0x18(%r13),%rdx - 419a59: 4c 39 68 18 cmp %r13,0x18(%rax) - 419a5d: 0f 85 13 07 00 00 jne 41a176 <_int_free+0x9b6> - 419a63: 4c 8b 42 10 mov 0x10(%rdx),%r8 - 419a67: 4d 39 e8 cmp %r13,%r8 - 419a6a: 0f 85 06 07 00 00 jne 41a176 <_int_free+0x9b6> - 419a70: 49 81 78 08 ff 03 00 cmpq $0x3ff,0x8(%r8) - 419a77: 00 - 419a78: 48 89 50 18 mov %rdx,0x18(%rax) - 419a7c: 48 89 42 10 mov %rax,0x10(%rdx) - 419a80: 0f 87 fa 05 00 00 ja 41a080 <_int_free+0x8c0> - 419a86: 4d 01 fc add %r15,%r12 - 419a89: 48 8b 45 68 mov 0x68(%rbp),%rax - 419a8d: 48 8d 55 58 lea 0x58(%rbp),%rdx - 419a91: 48 3b 50 18 cmp 0x18(%rax),%rdx - 419a95: 0f 85 15 09 00 00 jne 41a3b0 <_int_free+0xbf0> - 419a9b: 49 81 fc ff 03 00 00 cmp $0x3ff,%r12 - 419aa2: 48 89 43 10 mov %rax,0x10(%rbx) - 419aa6: 48 89 53 18 mov %rdx,0x18(%rbx) - 419aaa: 76 10 jbe 419abc <_int_free+0x2fc> - 419aac: 48 c7 43 20 00 00 00 movq $0x0,0x20(%rbx) - 419ab3: 00 - 419ab4: 48 c7 43 28 00 00 00 movq $0x0,0x28(%rbx) - 419abb: 00 - 419abc: 48 89 5d 68 mov %rbx,0x68(%rbp) - 419ac0: 48 89 58 18 mov %rbx,0x18(%rax) - 419ac4: 4c 89 e0 mov %r12,%rax - 419ac7: 48 83 c8 01 or $0x1,%rax - 419acb: 48 89 43 08 mov %rax,0x8(%rbx) - 419acf: 4e 89 24 23 mov %r12,(%rbx,%r12,1) - 419ad3: 49 81 fc ff ff 00 00 cmp $0xffff,%r12 - 419ada: 0f 86 a0 03 00 00 jbe 419e80 <_int_free+0x6c0> - 419ae0: f6 45 04 01 testb $0x1,0x4(%rbp) - 419ae4: 0f 84 de 05 00 00 je 41a0c8 <_int_free+0x908> - 419aea: 48 81 fd 00 a8 6c 00 cmp $0x6ca800,%rbp - 419af1: 0f 84 dd 08 00 00 je 41a3d4 <_int_free+0xc14> - 419af7: 4c 8b 65 58 mov 0x58(%rbp),%r12 - 419afb: 4c 89 e7 mov %r12,%rdi - 419afe: 48 81 e7 00 00 00 fc and $0xfffffffffc000000,%rdi - 419b05: 48 3b 2f cmp (%rdi),%rbp - 419b08: 0f 85 cf 10 00 00 jne 41abdd <_int_free+0x141d> - 419b0e: 48 8b 05 93 0c 2b 00 mov 0x2b0c93(%rip),%rax # 6ca7a8 - 419b15: 4c 8b 2d 64 16 2b 00 mov 0x2b1664(%rip),%r13 # 6cb180 <_dl_pagesize> - 419b1c: 48 89 44 24 08 mov %rax,0x8(%rsp) - 419b21: 48 8d 47 20 lea 0x20(%rdi),%rax - 419b25: 49 39 c4 cmp %rax,%r12 - 419b28: 0f 85 c2 02 00 00 jne 419df0 <_int_free+0x630> - 419b2e: 4c 8b 7f 08 mov 0x8(%rdi),%r15 - 419b32: 49 8b 4f 10 mov 0x10(%r15),%rcx - 419b36: 48 8d 51 f0 lea -0x10(%rcx),%rdx - 419b3a: 49 8d 04 17 lea (%r15,%rdx,1),%rax - 419b3e: 83 e0 0f and $0xf,%eax - 419b41: 48 29 c2 sub %rax,%rdx - 419b44: 4c 01 fa add %r15,%rdx - 419b47: 48 83 7a 08 01 cmpq $0x1,0x8(%rdx) - 419b4c: 0f 85 aa 0e 00 00 jne 41a9fc <_int_free+0x123c> - 419b52: 48 8d 5c 24 30 lea 0x30(%rsp),%rbx - 419b57: be 01 00 00 00 mov $0x1,%esi - 419b5c: 49 89 d6 mov %rdx,%r14 - 419b5f: 48 29 de sub %rbx,%rsi - 419b62: 48 89 74 24 10 mov %rsi,0x10(%rsp) - 419b67: e9 d9 00 00 00 jmpq 419c45 <_int_free+0x485> - 419b6c: 0f 1f 40 00 nopl 0x0(%rax) - 419b70: be 00 00 00 04 mov $0x4000000,%esi - 419b75: 4d 89 f4 mov %r14,%r12 - 419b78: e8 33 61 02 00 callq 43fcb0 <__munmap> - 419b7d: 41 f6 46 08 01 testb $0x1,0x8(%r14) - 419b82: 75 5c jne 419be0 <_int_free+0x420> - 419b84: 4d 2b 26 sub (%r14),%r12 - 419b87: 49 8b 44 24 08 mov 0x8(%r12),%rax - 419b8c: 48 83 e0 f8 and $0xfffffffffffffff8,%rax - 419b90: 49 3b 04 04 cmp (%r12,%rax,1),%rax - 419b94: 0f 85 a6 03 00 00 jne 419f40 <_int_free+0x780> - 419b9a: 4d 8b 74 24 10 mov 0x10(%r12),%r14 - 419b9f: 49 8b 44 24 18 mov 0x18(%r12),%rax - 419ba4: 4d 3b 66 18 cmp 0x18(%r14),%r12 - 419ba8: 0f 85 22 03 00 00 jne 419ed0 <_int_free+0x710> - 419bae: 4c 3b 60 10 cmp 0x10(%rax),%r12 - 419bb2: 0f 85 18 03 00 00 jne 419ed0 <_int_free+0x710> - 419bb8: 49 81 7c 24 08 ff 03 cmpq $0x3ff,0x8(%r12) - 419bbf: 00 00 - 419bc1: 49 89 46 18 mov %rax,0x18(%r14) - 419bc5: 4c 89 70 10 mov %r14,0x10(%rax) - 419bc9: 76 15 jbe 419be0 <_int_free+0x420> - 419bcb: 49 8b 44 24 20 mov 0x20(%r12),%rax - 419bd0: 48 85 c0 test %rax,%rax - 419bd3: 0f 85 df 06 00 00 jne 41a2b8 <_int_free+0xaf8> - 419bd9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 419be0: 49 8d 04 1c lea (%r12,%rbx,1),%rax - 419be4: 49 8d 55 ff lea -0x1(%r13),%rdx - 419be8: 48 85 d0 test %rdx,%rax - 419beb: 0f 85 a4 0e 00 00 jne 41aa95 <_int_free+0x12d5> - 419bf1: 4c 89 fa mov %r15,%rdx - 419bf4: 49 03 57 10 add 0x10(%r15),%rdx - 419bf8: 48 39 d0 cmp %rdx,%rax - 419bfb: 0f 85 7b 0e 00 00 jne 41aa7c <_int_free+0x12bc> - 419c01: 49 8d 47 20 lea 0x20(%r15),%rax - 419c05: 48 83 cb 01 or $0x1,%rbx - 419c09: 4c 89 65 58 mov %r12,0x58(%rbp) - 419c0d: 49 89 5c 24 08 mov %rbx,0x8(%r12) - 419c12: 49 39 c4 cmp %rax,%r12 - 419c15: 0f 85 dd 01 00 00 jne 419df8 <_int_free+0x638> - 419c1b: 49 8b 57 08 mov 0x8(%r15),%rdx - 419c1f: 4c 89 ff mov %r15,%rdi - 419c22: 48 8b 4a 10 mov 0x10(%rdx),%rcx - 419c26: 4c 8d 71 f0 lea -0x10(%rcx),%r14 - 419c2a: 4a 8d 04 32 lea (%rdx,%r14,1),%rax - 419c2e: 83 e0 0f and $0xf,%eax - 419c31: 49 29 c6 sub %rax,%r14 - 419c34: 49 01 d6 add %rdx,%r14 - 419c37: 49 83 7e 08 01 cmpq $0x1,0x8(%r14) - 419c3c: 0f 85 ba 0d 00 00 jne 41a9fc <_int_free+0x123c> - 419c42: 49 89 d7 mov %rdx,%r15 - 419c45: 4d 2b 36 sub (%r14),%r14 - 419c48: 49 8b 56 08 mov 0x8(%r14),%rdx - 419c4c: 48 89 d6 mov %rdx,%rsi - 419c4f: 48 83 e6 f8 and $0xfffffffffffffff8,%rsi - 419c53: 48 01 f0 add %rsi,%rax - 419c56: 4c 8d 48 10 lea 0x10(%rax),%r9 - 419c5a: 48 83 c0 0f add $0xf,%rax - 419c5e: 48 83 f8 3e cmp $0x3e,%rax - 419c62: 0f 87 7b 0d 00 00 ja 41a9e3 <_int_free+0x1223> - 419c68: 83 e2 01 and $0x1,%edx - 419c6b: 4c 89 cb mov %r9,%rbx - 419c6e: 75 03 jne 419c73 <_int_free+0x4b3> - 419c70: 49 03 1e add (%r14),%rbx - 419c73: 48 8d 43 ff lea -0x1(%rbx),%rax - 419c77: 48 3d fe ff ff 03 cmp $0x3fffffe,%rax - 419c7d: 0f 87 e0 0d 00 00 ja 41aa63 <_int_free+0x12a3> - 419c83: 48 89 d8 mov %rbx,%rax - 419c86: 48 29 c8 sub %rcx,%rax - 419c89: 48 8d 90 00 00 00 04 lea 0x4000000(%rax),%rdx - 419c90: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 419c95: 4a 8d 44 28 20 lea 0x20(%rax,%r13,1),%rax - 419c9a: 48 39 c2 cmp %rax,%rdx - 419c9d: 0f 82 4d 01 00 00 jb 419df0 <_int_free+0x630> - 419ca3: 48 8b 47 10 mov 0x10(%rdi),%rax - 419ca7: 48 29 85 80 08 00 00 sub %rax,0x880(%rbp) - 419cae: 48 29 05 63 29 2b 00 sub %rax,0x2b2963(%rip) # 6cc618 - 419cb5: 90 nop - 419cb6: 48 8d 87 00 00 00 04 lea 0x4000000(%rdi),%rax - 419cbd: 48 39 05 4c 29 2b 00 cmp %rax,0x2b294c(%rip) # 6cc610 - 419cc4: 0f 85 a6 fe ff ff jne 419b70 <_int_free+0x3b0> - 419cca: 48 c7 05 3b 29 2b 00 movq $0x0,0x2b293b(%rip) # 6cc610 - 419cd1: 00 00 00 00 - 419cd5: e9 96 fe ff ff jmpq 419b70 <_int_free+0x3b0> - 419cda: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 419ce0: be 01 00 00 00 mov $0x1,%esi - 419ce5: 83 3d d0 34 2b 00 00 cmpl $0x0,0x2b34d0(%rip) # 6cd1bc <__libc_multiple_threads> - 419cec: 74 09 je 419cf7 <_int_free+0x537> - 419cee: f0 0f b1 75 00 lock cmpxchg %esi,0x0(%rbp) - 419cf3: 75 08 jne 419cfd <_int_free+0x53d> - 419cf5: eb 1d jmp 419d14 <_int_free+0x554> - 419cf7: 0f b1 75 00 cmpxchg %esi,0x0(%rbp) - 419cfb: 74 17 je 419d14 <_int_free+0x554> - 419cfd: 48 8d 7d 00 lea 0x0(%rbp),%rdi - 419d01: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 419d08: e8 c3 88 02 00 callq 4425d0 <__lll_lock_wait_private> - 419d0d: 48 81 c4 80 00 00 00 add $0x80,%rsp - 419d14: 48 8b 45 58 mov 0x58(%rbp),%rax - 419d18: 4e 8d 2c 23 lea (%rbx,%r12,1),%r13 - 419d1c: 48 39 c3 cmp %rax,%rbx - 419d1f: 0f 84 e3 05 00 00 je 41a308 <_int_free+0xb48> - 419d25: 41 b9 01 00 00 00 mov $0x1,%r9d - 419d2b: c7 44 24 28 01 00 00 movl $0x1,0x28(%rsp) - 419d32: 00 - 419d33: e9 18 fc ff ff jmpq 419950 <_int_free+0x190> - 419d38: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 419d3f: 00 - 419d40: 48 8d 7b 10 lea 0x10(%rbx),%rdi - 419d44: 41 bd b2 20 4a 00 mov $0x4a20b2,%r13d - 419d4a: e9 89 fb ff ff jmpq 4198d8 <_int_free+0x118> - 419d4f: 90 nop - 419d50: 48 8d 6c 24 30 lea 0x30(%rsp),%rbp - 419d55: 48 8d 74 24 40 lea 0x40(%rsp),%rsi - 419d5a: 31 c9 xor %ecx,%ecx - 419d5c: ba 10 00 00 00 mov $0x10,%edx - 419d61: c6 44 24 40 00 movb $0x0,0x40(%rsp) - 419d66: e8 45 81 03 00 callq 451eb0 <_itoa_word> - 419d6b: 48 39 e8 cmp %rbp,%rax - 419d6e: 48 89 c3 mov %rax,%rbx - 419d71: 76 25 jbe 419d98 <_int_free+0x5d8> - 419d73: 48 89 c2 mov %rax,%rdx - 419d76: 48 89 c7 mov %rax,%rdi - 419d79: be 30 00 00 00 mov $0x30,%esi - 419d7e: 48 29 ea sub %rbp,%rdx - 419d81: 4c 8d 70 ff lea -0x1(%rax),%r14 - 419d85: 48 29 d7 sub %rdx,%rdi - 419d88: e8 c3 65 fe ff callq 400350 <__rela_iplt_end+0x88> - 419d8d: 48 8d 44 24 2f lea 0x2f(%rsp),%rax - 419d92: 4c 29 f0 sub %r14,%rax - 419d95: 48 01 c3 add %rax,%rbx - 419d98: 48 8b 05 21 35 2b 00 mov 0x2b3521(%rip),%rax # 6cd2c0 <__libc_argv> - 419d9f: 44 89 e7 mov %r12d,%edi - 419da2: ba 38 20 4a 00 mov $0x4a2038,%edx - 419da7: 49 89 d8 mov %rbx,%r8 - 419daa: 4c 89 e9 mov %r13,%rcx - 419dad: be a8 23 4a 00 mov $0x4a23a8,%esi - 419db2: 48 8b 00 mov (%rax),%rax - 419db5: 48 85 c0 test %rax,%rax - 419db8: 48 0f 45 d0 cmovne %rax,%rdx - 419dbc: 83 e7 02 and $0x2,%edi - 419dbf: 31 c0 xor %eax,%eax - 419dc1: e8 fa 77 ff ff callq 4115c0 <__libc_message> - 419dc6: 48 83 c4 58 add $0x58,%rsp - 419dca: 5b pop %rbx - 419dcb: 5d pop %rbp - 419dcc: 41 5c pop %r12 - 419dce: 41 5d pop %r13 - 419dd0: 41 5e pop %r14 - 419dd2: 41 5f pop %r15 - 419dd4: c3 retq - 419dd5: 0f 1f 00 nopl (%rax) - 419dd8: 48 8d 7b 10 lea 0x10(%rbx),%rdi - 419ddc: 41 bd ca 20 4a 00 mov $0x4a20ca,%r13d - 419de2: e9 f1 fa ff ff jmpq 4198d8 <_int_free+0x118> - 419de7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 419dee: 00 00 - 419df0: 49 8b 5c 24 08 mov 0x8(%r12),%rbx - 419df5: 49 89 ff mov %rdi,%r15 - 419df8: 48 83 e3 f8 and $0xfffffffffffffff8,%rbx - 419dfc: 48 39 1d 9d 09 2b 00 cmp %rbx,0x2b099d(%rip) # 6ca7a0 - 419e03: 77 7b ja 419e80 <_int_free+0x6c0> - 419e05: 48 89 d8 mov %rbx,%rax - 419e08: 48 83 e8 21 sub $0x21,%rax - 419e0c: 78 72 js 419e80 <_int_free+0x6c0> - 419e0e: 48 8b 4c 24 08 mov 0x8(%rsp),%rcx - 419e13: 48 39 c1 cmp %rax,%rcx - 419e16: 73 68 jae 419e80 <_int_free+0x6c0> - 419e18: 48 29 c8 sub %rcx,%rax - 419e1b: 49 f7 dd neg %r13 - 419e1e: 49 21 c5 and %rax,%r13 - 419e21: 74 5d je 419e80 <_int_free+0x6c0> - 419e23: 4d 8b 77 10 mov 0x10(%r15),%r14 - 419e27: 4d 29 ee sub %r13,%r14 - 419e2a: 49 83 fe 1f cmp $0x1f,%r14 - 419e2e: 7e 50 jle 419e80 <_int_free+0x6c0> - 419e30: 8b 35 2a 09 2b 00 mov 0x2b092a(%rip),%esi # 6ca760 - 419e36: 85 f6 test %esi,%esi - 419e38: 0f 88 1e 0b 00 00 js 41a95c <_int_free+0x119c> - 419e3e: 0f 95 c0 setne %al - 419e41: 84 c0 test %al,%al - 419e43: 4b 8d 3c 37 lea (%r15,%r14,1),%rdi - 419e47: 0f 85 e4 0a 00 00 jne 41a931 <_int_free+0x1171> - 419e4d: ba 04 00 00 00 mov $0x4,%edx - 419e52: 4c 89 ee mov %r13,%rsi - 419e55: e8 96 5e 02 00 callq 43fcf0 <__madvise> - 419e5a: 4d 89 77 10 mov %r14,0x10(%r15) - 419e5e: 90 nop - 419e5f: 4c 29 2d b2 27 2b 00 sub %r13,0x2b27b2(%rip) # 6cc618 - 419e66: 4c 29 eb sub %r13,%rbx - 419e69: 4c 29 ad 80 08 00 00 sub %r13,0x880(%rbp) - 419e70: 48 83 cb 01 or $0x1,%rbx - 419e74: 49 89 5c 24 08 mov %rbx,0x8(%r12) - 419e79: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 419e80: 8b 54 24 04 mov 0x4(%rsp),%edx - 419e84: 85 d2 test %edx,%edx - 419e86: 0f 85 7f fa ff ff jne 41990b <_int_free+0x14b> - 419e8c: 8b 44 24 28 mov 0x28(%rsp),%eax - 419e90: 85 c0 test %eax,%eax - 419e92: 0f 84 2c 0d 00 00 je 41abc4 <_int_free+0x1404> - 419e98: 83 3d 1d 33 2b 00 00 cmpl $0x0,0x2b331d(%rip) # 6cd1bc <__libc_multiple_threads> - 419e9f: 74 08 je 419ea9 <_int_free+0x6e9> - 419ea1: f0 ff 4d 00 lock decl 0x0(%rbp) - 419ea5: 75 07 jne 419eae <_int_free+0x6ee> - 419ea7: eb 1c jmp 419ec5 <_int_free+0x705> - 419ea9: ff 4d 00 decl 0x0(%rbp) - 419eac: 74 17 je 419ec5 <_int_free+0x705> - 419eae: 48 8d 7d 00 lea 0x0(%rbp),%rdi - 419eb2: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 419eb9: e8 42 87 02 00 callq 442600 <__lll_unlock_wake_private> - 419ebe: 48 81 c4 80 00 00 00 add $0x80,%rsp - 419ec5: e9 41 fa ff ff jmpq 41990b <_int_free+0x14b> - 419eca: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 419ed0: 8b 3d 9a 08 2b 00 mov 0x2b089a(%rip),%edi # 6ca770 - 419ed6: 83 4d 04 04 orl $0x4,0x4(%rbp) - 419eda: 89 f8 mov %edi,%eax - 419edc: 83 e0 05 and $0x5,%eax - 419edf: 83 f8 05 cmp $0x5,%eax - 419ee2: 0f 84 d3 04 00 00 je 41a3bb <_int_free+0xbfb> - 419ee8: 41 89 fe mov %edi,%r14d - 419eeb: 41 83 e6 02 and $0x2,%r14d - 419eef: 83 e7 01 and $0x1,%edi - 419ef2: 0f 85 10 03 00 00 jne 41a208 <_int_free+0xa48> - 419ef8: 45 85 f6 test %r14d,%r14d - 419efb: 0f 84 df fc ff ff je 419be0 <_int_free+0x420> - 419f01: e9 9e 02 00 00 jmpq 41a1a4 <_int_free+0x9e4> - 419f06: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 419f0d: 00 00 00 - 419f10: 48 89 f7 mov %rsi,%rdi - 419f13: e8 d8 dd ff ff callq 417cf0 - 419f18: e9 ee f9 ff ff jmpq 41990b <_int_free+0x14b> - 419f1d: 0f 1f 00 nopl (%rax) - 419f20: 44 39 e7 cmp %r12d,%edi - 419f23: 0f 84 e2 f9 ff ff je 41990b <_int_free+0x14b> - 419f29: 84 c9 test %cl,%cl - 419f2b: 0f 84 da f9 ff ff je 41990b <_int_free+0x14b> - 419f31: 4c 89 c7 mov %r8,%rdi - 419f34: 41 bd df 20 4a 00 mov $0x4a20df,%r13d - 419f3a: e9 99 f9 ff ff jmpq 4198d8 <_int_free+0x118> - 419f3f: 90 nop - 419f40: 44 8b 15 29 08 2b 00 mov 0x2b0829(%rip),%r10d # 6ca770 - 419f47: 83 4d 04 04 orl $0x4,0x4(%rbp) - 419f4b: 44 89 d0 mov %r10d,%eax - 419f4e: 83 e0 05 and $0x5,%eax - 419f51: 83 f8 05 cmp $0x5,%eax - 419f54: 0f 84 66 05 00 00 je 41a4c0 <_int_free+0xd00> - 419f5a: 41 f6 c2 01 test $0x1,%r10b - 419f5e: 0f 85 71 01 00 00 jne 41a0d5 <_int_free+0x915> - 419f64: 41 f6 c2 02 test $0x2,%r10b - 419f68: 0f 85 36 02 00 00 jne 41a1a4 <_int_free+0x9e4> - 419f6e: 4d 8b 74 24 10 mov 0x10(%r12),%r14 - 419f73: 49 8b 44 24 18 mov 0x18(%r12),%rax - 419f78: 4d 3b 66 18 cmp 0x18(%r14),%r12 - 419f7c: 0f 85 5e fc ff ff jne 419be0 <_int_free+0x420> - 419f82: 4c 3b 60 10 cmp 0x10(%rax),%r12 - 419f86: 0f 84 2c fc ff ff je 419bb8 <_int_free+0x3f8> - 419f8c: 44 89 d7 mov %r10d,%edi - 419f8f: 83 4d 04 04 orl $0x4,0x4(%rbp) - 419f93: e9 50 ff ff ff jmpq 419ee8 <_int_free+0x728> - 419f98: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 419f9f: 00 - 419fa0: 49 83 65 08 fe andq $0xfffffffffffffffe,0x8(%r13) - 419fa5: e9 df fa ff ff jmpq 419a89 <_int_free+0x2c9> - 419faa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 419fb0: 44 89 e7 mov %r12d,%edi - 419fb3: 4c 89 ea mov %r13,%rdx - 419fb6: be 3c ca 4b 00 mov $0x4bca3c,%esi - 419fbb: 83 e7 02 and $0x2,%edi - 419fbe: 31 c0 xor %eax,%eax - 419fc0: e8 fb 75 ff ff callq 4115c0 <__libc_message> - 419fc5: e9 41 f9 ff ff jmpq 41990b <_int_free+0x14b> - 419fca: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 419fd0: 44 8b 44 24 04 mov 0x4(%rsp),%r8d - 419fd5: 45 85 c0 test %r8d,%r8d - 419fd8: 0f 85 92 00 00 00 jne 41a070 <_int_free+0x8b0> - 419fde: be 01 00 00 00 mov $0x1,%esi - 419fe3: 8b 44 24 04 mov 0x4(%rsp),%eax - 419fe7: 83 3d ce 31 2b 00 00 cmpl $0x0,0x2b31ce(%rip) # 6cd1bc <__libc_multiple_threads> - 419fee: 74 09 je 419ff9 <_int_free+0x839> - 419ff0: f0 0f b1 75 00 lock cmpxchg %esi,0x0(%rbp) - 419ff5: 75 08 jne 419fff <_int_free+0x83f> - 419ff7: eb 1d jmp 41a016 <_int_free+0x856> - 419ff9: 0f b1 75 00 cmpxchg %esi,0x0(%rbp) - 419ffd: 74 17 je 41a016 <_int_free+0x856> - 419fff: 48 8d 7d 00 lea 0x0(%rbp),%rdi - 41a003: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41a00a: e8 c1 85 02 00 callq 4425d0 <__lll_lock_wait_private> - 41a00f: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41a016: 48 8b 42 08 mov 0x8(%rdx),%rax - 41a01a: 48 83 f8 10 cmp $0x10,%rax - 41a01e: 0f 86 d4 02 00 00 jbe 41a2f8 <_int_free+0xb38> - 41a024: 48 83 e0 f8 and $0xfffffffffffffff8,%rax - 41a028: 48 3b 85 80 08 00 00 cmp 0x880(%rbp),%rax - 41a02f: 0f 83 c3 02 00 00 jae 41a2f8 <_int_free+0xb38> - 41a035: 83 3d 80 31 2b 00 00 cmpl $0x0,0x2b3180(%rip) # 6cd1bc <__libc_multiple_threads> - 41a03c: 74 08 je 41a046 <_int_free+0x886> - 41a03e: f0 ff 4d 00 lock decl 0x0(%rbp) - 41a042: 75 07 jne 41a04b <_int_free+0x88b> - 41a044: eb 1c jmp 41a062 <_int_free+0x8a2> - 41a046: ff 4d 00 decl 0x0(%rbp) - 41a049: 74 17 je 41a062 <_int_free+0x8a2> - 41a04b: 48 8d 7d 00 lea 0x0(%rbp),%rdi - 41a04f: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41a056: e8 a5 85 02 00 callq 442600 <__lll_unlock_wake_private> - 41a05b: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41a062: e9 d7 f7 ff ff jmpq 41983e <_int_free+0x7e> - 41a067: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 41a06e: 00 00 - 41a070: 48 8d 7b 10 lea 0x10(%rbx),%rdi - 41a074: 41 bd 20 24 4a 00 mov $0x4a2420,%r13d - 41a07a: e9 59 f8 ff ff jmpq 4198d8 <_int_free+0x118> - 41a07f: 90 nop - 41a080: 49 8b 50 20 mov 0x20(%r8),%rdx - 41a084: 48 85 d2 test %rdx,%rdx - 41a087: 0f 84 f9 f9 ff ff je 419a86 <_int_free+0x2c6> - 41a08d: 4c 39 42 28 cmp %r8,0x28(%rdx) - 41a091: 0f 85 cd 0a 00 00 jne 41ab64 <_int_free+0x13a4> - 41a097: 49 8b 48 28 mov 0x28(%r8),%rcx - 41a09b: 4c 39 41 20 cmp %r8,0x20(%rcx) - 41a09f: 0f 85 bf 0a 00 00 jne 41ab64 <_int_free+0x13a4> - 41a0a5: 48 83 78 20 00 cmpq $0x0,0x20(%rax) - 41a0aa: 0f 84 8a 0a 00 00 je 41ab3a <_int_free+0x137a> - 41a0b0: 49 8b 40 28 mov 0x28(%r8),%rax - 41a0b4: 48 89 42 28 mov %rax,0x28(%rdx) - 41a0b8: 49 8b 40 28 mov 0x28(%r8),%rax - 41a0bc: 48 89 50 20 mov %rdx,0x20(%rax) - 41a0c0: e9 c1 f9 ff ff jmpq 419a86 <_int_free+0x2c6> - 41a0c5: 0f 1f 00 nopl (%rax) - 41a0c8: 48 89 ef mov %rbp,%rdi - 41a0cb: e8 60 dd ff ff callq 417e30 - 41a0d0: e9 15 fa ff ff jmpq 419aea <_int_free+0x32a> - 41a0d5: 48 8d 74 24 40 lea 0x40(%rsp),%rsi - 41a0da: 31 c9 xor %ecx,%ecx - 41a0dc: ba 10 00 00 00 mov $0x10,%edx - 41a0e1: 4c 89 e7 mov %r12,%rdi - 41a0e4: 44 89 54 24 18 mov %r10d,0x18(%rsp) - 41a0e9: c6 44 24 40 00 movb $0x0,0x40(%rsp) - 41a0ee: e8 bd 7d 03 00 callq 451eb0 <_itoa_word> - 41a0f3: 49 89 c6 mov %rax,%r14 - 41a0f6: 48 8d 44 24 30 lea 0x30(%rsp),%rax - 41a0fb: 44 8b 54 24 18 mov 0x18(%rsp),%r10d - 41a100: 49 39 c6 cmp %rax,%r14 - 41a103: 76 3c jbe 41a141 <_int_free+0x981> - 41a105: 48 8b 44 24 10 mov 0x10(%rsp),%rax - 41a10a: 49 8d 4e ff lea -0x1(%r14),%rcx - 41a10e: 4c 89 f7 mov %r14,%rdi - 41a111: be 30 00 00 00 mov $0x30,%esi - 41a116: 44 89 54 24 20 mov %r10d,0x20(%rsp) - 41a11b: 48 89 4c 24 18 mov %rcx,0x18(%rsp) - 41a120: 48 8d 14 08 lea (%rax,%rcx,1),%rdx - 41a124: 48 29 d7 sub %rdx,%rdi - 41a127: e8 24 62 fe ff callq 400350 <__rela_iplt_end+0x88> - 41a12c: 48 8b 4c 24 18 mov 0x18(%rsp),%rcx - 41a131: 48 8d 44 24 2f lea 0x2f(%rsp),%rax - 41a136: 44 8b 54 24 20 mov 0x20(%rsp),%r10d - 41a13b: 48 29 c8 sub %rcx,%rax - 41a13e: 49 01 c6 add %rax,%r14 - 41a141: 48 8b 05 78 31 2b 00 mov 0x2b3178(%rip),%rax # 6cd2c0 <__libc_argv> - 41a148: 44 89 d7 mov %r10d,%edi - 41a14b: ba 38 20 4a 00 mov $0x4a2038,%edx - 41a150: 4d 89 f0 mov %r14,%r8 - 41a153: b9 78 20 4a 00 mov $0x4a2078,%ecx - 41a158: be a8 23 4a 00 mov $0x4a23a8,%esi - 41a15d: 48 8b 00 mov (%rax),%rax - 41a160: 48 85 c0 test %rax,%rax - 41a163: 48 0f 45 d0 cmovne %rax,%rdx - 41a167: 83 e7 02 and $0x2,%edi - 41a16a: 31 c0 xor %eax,%eax - 41a16c: e8 4f 74 ff ff callq 4115c0 <__libc_message> - 41a171: e9 24 fa ff ff jmpq 419b9a <_int_free+0x3da> - 41a176: 44 8b 15 f3 05 2b 00 mov 0x2b05f3(%rip),%r10d # 6ca770 - 41a17d: 83 4d 04 04 orl $0x4,0x4(%rbp) - 41a181: 44 89 d0 mov %r10d,%eax - 41a184: 83 e0 05 and $0x5,%eax - 41a187: 83 f8 05 cmp $0x5,%eax - 41a18a: 0f 84 7a 07 00 00 je 41a90a <_int_free+0x114a> - 41a190: 41 f6 c2 01 test $0x1,%r10b - 41a194: 0f 85 62 04 00 00 jne 41a5fc <_int_free+0xe3c> - 41a19a: 41 83 e2 02 and $0x2,%r10d - 41a19e: 0f 84 e2 f8 ff ff je 419a86 <_int_free+0x2c6> - 41a1a4: e8 57 3a ff ff callq 40dc00 - 41a1a9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 41a1b0: 41 bd 00 25 4a 00 mov $0x4a2500,%r13d - 41a1b6: 44 8b 54 24 04 mov 0x4(%rsp),%r10d - 41a1bb: 45 85 d2 test %r10d,%r10d - 41a1be: 0f 85 48 0a 00 00 jne 41ac0c <_int_free+0x144c> - 41a1c4: 45 84 c9 test %r9b,%r9b - 41a1c7: 0f 84 3f 0a 00 00 je 41ac0c <_int_free+0x144c> - 41a1cd: 83 3d e8 2f 2b 00 00 cmpl $0x0,0x2b2fe8(%rip) # 6cd1bc <__libc_multiple_threads> - 41a1d4: 74 08 je 41a1de <_int_free+0xa1e> - 41a1d6: f0 ff 4d 00 lock decl 0x0(%rbp) - 41a1da: 75 07 jne 41a1e3 <_int_free+0xa23> - 41a1dc: eb 1c jmp 41a1fa <_int_free+0xa3a> - 41a1de: ff 4d 00 decl 0x0(%rbp) - 41a1e1: 74 17 je 41a1fa <_int_free+0xa3a> - 41a1e3: 48 8d 7d 00 lea 0x0(%rbp),%rdi - 41a1e7: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41a1ee: e8 0d 84 02 00 callq 442600 <__lll_unlock_wake_private> - 41a1f3: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41a1fa: 48 8d 7b 10 lea 0x10(%rbx),%rdi - 41a1fe: e9 d5 f6 ff ff jmpq 4198d8 <_int_free+0x118> - 41a203: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41a208: 48 8d 74 24 40 lea 0x40(%rsp),%rsi - 41a20d: 31 c9 xor %ecx,%ecx - 41a20f: ba 10 00 00 00 mov $0x10,%edx - 41a214: 4c 89 e7 mov %r12,%rdi - 41a217: c6 44 24 40 00 movb $0x0,0x40(%rsp) - 41a21c: e8 8f 7c 03 00 callq 451eb0 <_itoa_word> - 41a221: 49 89 c0 mov %rax,%r8 - 41a224: 48 8d 44 24 30 lea 0x30(%rsp),%rax - 41a229: 49 39 c0 cmp %rax,%r8 - 41a22c: 76 3c jbe 41a26a <_int_free+0xaaa> - 41a22e: 48 8b 44 24 10 mov 0x10(%rsp),%rax - 41a233: 49 8d 48 ff lea -0x1(%r8),%rcx - 41a237: 4c 89 c7 mov %r8,%rdi - 41a23a: be 30 00 00 00 mov $0x30,%esi - 41a23f: 4c 89 44 24 18 mov %r8,0x18(%rsp) - 41a244: 48 89 4c 24 20 mov %rcx,0x20(%rsp) - 41a249: 48 8d 14 08 lea (%rax,%rcx,1),%rdx - 41a24d: 48 29 d7 sub %rdx,%rdi - 41a250: e8 fb 60 fe ff callq 400350 <__rela_iplt_end+0x88> - 41a255: 48 8b 4c 24 20 mov 0x20(%rsp),%rcx - 41a25a: 48 8d 44 24 2f lea 0x2f(%rsp),%rax - 41a25f: 4c 8b 44 24 18 mov 0x18(%rsp),%r8 - 41a264: 48 29 c8 sub %rcx,%rax - 41a267: 49 01 c0 add %rax,%r8 - 41a26a: 48 8b 05 4f 30 2b 00 mov 0x2b304f(%rip),%rax # 6cd2c0 <__libc_argv> - 41a271: ba 38 20 4a 00 mov $0x4a2038,%edx - 41a276: b9 95 20 4a 00 mov $0x4a2095,%ecx - 41a27b: be a8 23 4a 00 mov $0x4a23a8,%esi - 41a280: 44 89 f7 mov %r14d,%edi - 41a283: 48 8b 00 mov (%rax),%rax - 41a286: 48 85 c0 test %rax,%rax - 41a289: 48 0f 45 d0 cmovne %rax,%rdx - 41a28d: 31 c0 xor %eax,%eax - 41a28f: e8 2c 73 ff ff callq 4115c0 <__libc_message> - 41a294: e9 47 f9 ff ff jmpq 419be0 <_int_free+0x420> - 41a299: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 41a2a0: 49 8d 54 24 f0 lea -0x10(%r12),%rdx - 41a2a5: 4c 89 c7 mov %r8,%rdi - 41a2a8: e8 a3 60 fe ff callq 400350 <__rela_iplt_end+0x88> - 41a2ad: 49 89 c0 mov %rax,%r8 - 41a2b0: e9 9b f5 ff ff jmpq 419850 <_int_free+0x90> - 41a2b5: 0f 1f 00 nopl (%rax) - 41a2b8: 4c 3b 60 28 cmp 0x28(%rax),%r12 - 41a2bc: 0f 85 1a 02 00 00 jne 41a4dc <_int_free+0xd1c> - 41a2c2: 49 8b 54 24 28 mov 0x28(%r12),%rdx - 41a2c7: 4c 3b 62 20 cmp 0x20(%rdx),%r12 - 41a2cb: 0f 85 0b 02 00 00 jne 41a4dc <_int_free+0xd1c> - 41a2d1: 49 83 7e 20 00 cmpq $0x0,0x20(%r14) - 41a2d6: 0f 84 34 02 00 00 je 41a510 <_int_free+0xd50> - 41a2dc: 49 8b 54 24 28 mov 0x28(%r12),%rdx - 41a2e1: 48 89 50 28 mov %rdx,0x28(%rax) - 41a2e5: 49 8b 54 24 28 mov 0x28(%r12),%rdx - 41a2ea: 48 89 42 20 mov %rax,0x20(%rdx) - 41a2ee: e9 ed f8 ff ff jmpq 419be0 <_int_free+0x420> - 41a2f3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41a2f8: 41 bd 20 24 4a 00 mov $0x4a2420,%r13d - 41a2fe: e9 ca fe ff ff jmpq 41a1cd <_int_free+0xa0d> - 41a303: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41a308: 41 bd 98 24 4a 00 mov $0x4a2498,%r13d - 41a30e: e9 ba fe ff ff jmpq 41a1cd <_int_free+0xa0d> - 41a313: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41a318: 4d 01 fc add %r15,%r12 - 41a31b: 4c 89 e0 mov %r12,%rax - 41a31e: 48 83 c8 01 or $0x1,%rax - 41a322: 48 89 43 08 mov %rax,0x8(%rbx) - 41a326: 48 89 5d 58 mov %rbx,0x58(%rbp) - 41a32a: e9 a4 f7 ff ff jmpq 419ad3 <_int_free+0x313> - 41a32f: 90 nop - 41a330: 48 8b 50 08 mov 0x8(%rax),%rdx - 41a334: 48 83 e2 f8 and $0xfffffffffffffff8,%rdx - 41a338: 48 01 d0 add %rdx,%rax - 41a33b: 49 39 c5 cmp %rax,%r13 - 41a33e: 0f 82 16 f6 ff ff jb 41995a <_int_free+0x19a> - 41a344: 41 bd b8 24 4a 00 mov $0x4a24b8,%r13d - 41a34a: e9 67 fe ff ff jmpq 41a1b6 <_int_free+0x9f6> - 41a34f: 90 nop - 41a350: 41 bd d8 24 4a 00 mov $0x4a24d8,%r13d - 41a356: e9 5b fe ff ff jmpq 41a1b6 <_int_free+0x9f6> - 41a35b: 49 8d 54 24 f0 lea -0x10(%r12),%rdx - 41a360: 48 8d 7b 10 lea 0x10(%rbx),%rdi - 41a364: 44 88 4c 24 08 mov %r9b,0x8(%rsp) - 41a369: e8 e2 5f fe ff callq 400350 <__rela_iplt_end+0x88> - 41a36e: 44 0f b6 4c 24 08 movzbl 0x8(%rsp),%r9d - 41a374: e9 19 f6 ff ff jmpq 419992 <_int_free+0x1d2> - 41a379: 44 8b 15 f0 03 2b 00 mov 0x2b03f0(%rip),%r10d # 6ca770 - 41a380: 83 4d 04 04 orl $0x4,0x4(%rbp) - 41a384: 44 89 d0 mov %r10d,%eax - 41a387: 83 e0 05 and $0x5,%eax - 41a38a: 83 f8 05 cmp $0x5,%eax - 41a38d: 0f 84 50 05 00 00 je 41a8e3 <_int_free+0x1123> - 41a393: 41 f6 c2 01 test $0x1,%r10b - 41a397: 0f 85 a0 01 00 00 jne 41a53d <_int_free+0xd7d> - 41a39d: 41 83 e2 02 and $0x2,%r10d - 41a3a1: 0f 84 81 f6 ff ff je 419a28 <_int_free+0x268> - 41a3a7: e9 f8 fd ff ff jmpq 41a1a4 <_int_free+0x9e4> - 41a3ac: 0f 1f 40 00 nopl 0x0(%rax) - 41a3b0: 41 bd 48 24 4a 00 mov $0x4a2448,%r13d - 41a3b6: e9 fb fd ff ff jmpq 41a1b6 <_int_free+0x9f6> - 41a3bb: 83 e7 02 and $0x2,%edi - 41a3be: ba 95 20 4a 00 mov $0x4a2095,%edx - 41a3c3: be 3c ca 4b 00 mov $0x4bca3c,%esi - 41a3c8: 31 c0 xor %eax,%eax - 41a3ca: e8 f1 71 ff ff callq 4115c0 <__libc_message> - 41a3cf: e9 0c f8 ff ff jmpq 419be0 <_int_free+0x420> - 41a3d4: 48 8b 05 7d 04 2b 00 mov 0x2b047d(%rip),%rax # 6ca858 - 41a3db: 48 8b 40 08 mov 0x8(%rax),%rax - 41a3df: 48 83 e0 f8 and $0xfffffffffffffff8,%rax - 41a3e3: 48 3b 05 b6 03 2b 00 cmp 0x2b03b6(%rip),%rax # 6ca7a0 - 41a3ea: 0f 82 90 fa ff ff jb 419e80 <_int_free+0x6c0> - 41a3f0: 48 8b 3d b1 03 2b 00 mov 0x2b03b1(%rip),%rdi # 6ca7a8 - 41a3f7: ba 80 b0 6c 00 mov $0x6cb080,%edx - 41a3fc: be 58 a8 6c 00 mov $0x6ca858,%esi - 41a401: e8 9a cf ff ff callq 4173a0 - 41a406: e9 75 fa ff ff jmpq 419e80 <_int_free+0x6c0> - 41a40b: 44 8b 15 5e 03 2b 00 mov 0x2b035e(%rip),%r10d # 6ca770 - 41a412: 83 4d 04 04 orl $0x4,0x4(%rbp) - 41a416: 44 89 d0 mov %r10d,%eax - 41a419: 83 e0 05 and $0x5,%eax - 41a41c: 83 f8 05 cmp $0x5,%eax - 41a41f: 0f 84 f0 05 00 00 je 41aa15 <_int_free+0x1255> - 41a425: 41 f6 c2 01 test $0x1,%r10b - 41a429: 0f 85 89 02 00 00 jne 41a6b8 <_int_free+0xef8> - 41a42f: 41 f6 c2 02 test $0x2,%r10b - 41a433: 0f 85 6b fd ff ff jne 41a1a4 <_int_free+0x9e4> - 41a439: 48 8b 43 10 mov 0x10(%rbx),%rax - 41a43d: 48 8b 53 18 mov 0x18(%rbx),%rdx - 41a441: 48 3b 58 18 cmp 0x18(%rax),%rbx - 41a445: 0f 85 52 ff ff ff jne 41a39d <_int_free+0xbdd> - 41a44b: 48 3b 5a 10 cmp 0x10(%rdx),%rbx - 41a44f: 0f 84 7e f5 ff ff je 4199d3 <_int_free+0x213> - 41a455: 83 4d 04 04 orl $0x4,0x4(%rbp) - 41a459: e9 35 ff ff ff jmpq 41a393 <_int_free+0xbd3> - 41a45e: 66 90 xchg %ax,%ax - 41a460: 44 8b 15 09 03 2b 00 mov 0x2b0309(%rip),%r10d # 6ca770 - 41a467: 83 4d 04 04 orl $0x4,0x4(%rbp) - 41a46b: 44 89 d0 mov %r10d,%eax - 41a46e: 83 e0 05 and $0x5,%eax - 41a471: 83 f8 05 cmp $0x5,%eax - 41a474: 0f 84 c2 05 00 00 je 41aa3c <_int_free+0x127c> - 41a47a: 41 f6 c2 01 test $0x1,%r10b - 41a47e: 0f 85 f3 02 00 00 jne 41a777 <_int_free+0xfb7> - 41a484: 41 f6 c2 02 test $0x2,%r10b - 41a488: 0f 85 16 fd ff ff jne 41a1a4 <_int_free+0x9e4> - 41a48e: 49 8b 45 10 mov 0x10(%r13),%rax - 41a492: 49 8b 55 18 mov 0x18(%r13),%rdx - 41a496: 4c 39 68 18 cmp %r13,0x18(%rax) - 41a49a: 0f 85 fa fc ff ff jne 41a19a <_int_free+0x9da> - 41a4a0: 4c 8b 42 10 mov 0x10(%rdx),%r8 - 41a4a4: 4d 39 c5 cmp %r8,%r13 - 41a4a7: 0f 84 c3 f5 ff ff je 419a70 <_int_free+0x2b0> - 41a4ad: 83 4d 04 04 orl $0x4,0x4(%rbp) - 41a4b1: e9 da fc ff ff jmpq 41a190 <_int_free+0x9d0> - 41a4b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41a4bd: 00 00 00 - 41a4c0: 44 89 d7 mov %r10d,%edi - 41a4c3: ba 78 20 4a 00 mov $0x4a2078,%edx - 41a4c8: be 3c ca 4b 00 mov $0x4bca3c,%esi - 41a4cd: 83 e7 02 and $0x2,%edi - 41a4d0: 31 c0 xor %eax,%eax - 41a4d2: e8 e9 70 ff ff callq 4115c0 <__libc_message> - 41a4d7: e9 be f6 ff ff jmpq 419b9a <_int_free+0x3da> - 41a4dc: 44 8b 15 8d 02 2b 00 mov 0x2b028d(%rip),%r10d # 6ca770 - 41a4e3: 83 4d 04 04 orl $0x4,0x4(%rbp) - 41a4e7: 44 89 d2 mov %r10d,%edx - 41a4ea: 83 e2 05 and $0x5,%edx - 41a4ed: 83 fa 05 cmp $0x5,%edx - 41a4f0: 0f 84 f9 05 00 00 je 41aaef <_int_free+0x132f> - 41a4f6: 41 f6 c2 01 test $0x1,%r10b - 41a4fa: 0f 85 36 03 00 00 jne 41a836 <_int_free+0x1076> - 41a500: 41 83 e2 02 and $0x2,%r10d - 41a504: 0f 84 c7 fd ff ff je 41a2d1 <_int_free+0xb11> - 41a50a: e9 95 fc ff ff jmpq 41a1a4 <_int_free+0x9e4> - 41a50f: 90 nop - 41a510: 49 39 c4 cmp %rax,%r12 - 41a513: 0f 84 95 05 00 00 je 41aaae <_int_free+0x12ee> - 41a519: 49 89 46 20 mov %rax,0x20(%r14) - 41a51d: 49 8b 44 24 28 mov 0x28(%r12),%rax - 41a522: 49 89 46 28 mov %rax,0x28(%r14) - 41a526: 49 8b 44 24 20 mov 0x20(%r12),%rax - 41a52b: 4c 89 70 28 mov %r14,0x28(%rax) - 41a52f: 49 8b 44 24 28 mov 0x28(%r12),%rax - 41a534: 4c 89 70 20 mov %r14,0x20(%rax) - 41a538: e9 a3 f6 ff ff jmpq 419be0 <_int_free+0x420> - 41a53d: 4c 8d 5c 24 30 lea 0x30(%rsp),%r11 - 41a542: 48 8d 74 24 40 lea 0x40(%rsp),%rsi - 41a547: 31 c9 xor %ecx,%ecx - 41a549: ba 10 00 00 00 mov $0x10,%edx - 41a54e: 48 89 df mov %rbx,%rdi - 41a551: 44 88 4c 24 18 mov %r9b,0x18(%rsp) - 41a556: 44 89 54 24 10 mov %r10d,0x10(%rsp) - 41a55b: 4c 89 5c 24 08 mov %r11,0x8(%rsp) - 41a560: c6 44 24 40 00 movb $0x0,0x40(%rsp) - 41a565: e8 46 79 03 00 callq 451eb0 <_itoa_word> - 41a56a: 4c 8b 5c 24 08 mov 0x8(%rsp),%r11 - 41a56f: 49 89 c0 mov %rax,%r8 - 41a572: 44 8b 54 24 10 mov 0x10(%rsp),%r10d - 41a577: 44 0f b6 4c 24 18 movzbl 0x18(%rsp),%r9d - 41a57d: 4c 39 d8 cmp %r11,%rax - 41a580: 76 3d jbe 41a5bf <_int_free+0xdff> - 41a582: 4c 89 c2 mov %r8,%rdx - 41a585: 4c 89 c7 mov %r8,%rdi - 41a588: 48 8d 40 ff lea -0x1(%rax),%rax - 41a58c: 4c 29 da sub %r11,%rdx - 41a58f: be 30 00 00 00 mov $0x30,%esi - 41a594: 4c 89 44 24 08 mov %r8,0x8(%rsp) - 41a599: 48 29 d7 sub %rdx,%rdi - 41a59c: 49 89 c6 mov %rax,%r14 - 41a59f: e8 ac 5d fe ff callq 400350 <__rela_iplt_end+0x88> - 41a5a4: 48 8d 44 24 2f lea 0x2f(%rsp),%rax - 41a5a9: 4c 8b 44 24 08 mov 0x8(%rsp),%r8 - 41a5ae: 44 0f b6 4c 24 18 movzbl 0x18(%rsp),%r9d - 41a5b4: 44 8b 54 24 10 mov 0x10(%rsp),%r10d - 41a5b9: 4c 29 f0 sub %r14,%rax - 41a5bc: 49 01 c0 add %rax,%r8 - 41a5bf: 48 8b 05 fa 2c 2b 00 mov 0x2b2cfa(%rip),%rax # 6cd2c0 <__libc_argv> - 41a5c6: 44 89 d7 mov %r10d,%edi - 41a5c9: ba 38 20 4a 00 mov $0x4a2038,%edx - 41a5ce: b9 95 20 4a 00 mov $0x4a2095,%ecx - 41a5d3: be a8 23 4a 00 mov $0x4a23a8,%esi - 41a5d8: 44 88 4c 24 08 mov %r9b,0x8(%rsp) - 41a5dd: 48 8b 00 mov (%rax),%rax - 41a5e0: 48 85 c0 test %rax,%rax - 41a5e3: 48 0f 45 d0 cmovne %rax,%rdx - 41a5e7: 83 e7 02 and $0x2,%edi - 41a5ea: 31 c0 xor %eax,%eax - 41a5ec: e8 cf 6f ff ff callq 4115c0 <__libc_message> - 41a5f1: 44 0f b6 4c 24 08 movzbl 0x8(%rsp),%r9d - 41a5f7: e9 2c f4 ff ff jmpq 419a28 <_int_free+0x268> - 41a5fc: 4c 8d 5c 24 30 lea 0x30(%rsp),%r11 - 41a601: 48 8d 74 24 40 lea 0x40(%rsp),%rsi - 41a606: 31 c9 xor %ecx,%ecx - 41a608: ba 10 00 00 00 mov $0x10,%edx - 41a60d: 4c 89 ef mov %r13,%rdi - 41a610: 44 88 4c 24 18 mov %r9b,0x18(%rsp) - 41a615: 44 89 54 24 10 mov %r10d,0x10(%rsp) - 41a61a: 4c 89 5c 24 08 mov %r11,0x8(%rsp) - 41a61f: c6 44 24 40 00 movb $0x0,0x40(%rsp) - 41a624: e8 87 78 03 00 callq 451eb0 <_itoa_word> - 41a629: 4c 8b 5c 24 08 mov 0x8(%rsp),%r11 - 41a62e: 49 89 c0 mov %rax,%r8 - 41a631: 44 8b 54 24 10 mov 0x10(%rsp),%r10d - 41a636: 44 0f b6 4c 24 18 movzbl 0x18(%rsp),%r9d - 41a63c: 4c 39 d8 cmp %r11,%rax - 41a63f: 76 3a jbe 41a67b <_int_free+0xebb> - 41a641: 48 89 c2 mov %rax,%rdx - 41a644: 48 89 c7 mov %rax,%rdi - 41a647: be 30 00 00 00 mov $0x30,%esi - 41a64c: 4c 29 da sub %r11,%rdx - 41a64f: 4c 8d 68 ff lea -0x1(%rax),%r13 - 41a653: 48 89 44 24 08 mov %rax,0x8(%rsp) - 41a658: 48 29 d7 sub %rdx,%rdi - 41a65b: e8 f0 5c fe ff callq 400350 <__rela_iplt_end+0x88> - 41a660: 48 8d 44 24 2f lea 0x2f(%rsp),%rax - 41a665: 4c 8b 44 24 08 mov 0x8(%rsp),%r8 - 41a66a: 44 0f b6 4c 24 18 movzbl 0x18(%rsp),%r9d - 41a670: 44 8b 54 24 10 mov 0x10(%rsp),%r10d - 41a675: 4c 29 e8 sub %r13,%rax - 41a678: 49 01 c0 add %rax,%r8 - 41a67b: 48 8b 05 3e 2c 2b 00 mov 0x2b2c3e(%rip),%rax # 6cd2c0 <__libc_argv> - 41a682: 44 89 d7 mov %r10d,%edi - 41a685: ba 38 20 4a 00 mov $0x4a2038,%edx - 41a68a: b9 95 20 4a 00 mov $0x4a2095,%ecx - 41a68f: be a8 23 4a 00 mov $0x4a23a8,%esi - 41a694: 44 88 4c 24 08 mov %r9b,0x8(%rsp) - 41a699: 48 8b 00 mov (%rax),%rax - 41a69c: 48 85 c0 test %rax,%rax - 41a69f: 48 0f 45 d0 cmovne %rax,%rdx - 41a6a3: 83 e7 02 and $0x2,%edi - 41a6a6: 31 c0 xor %eax,%eax - 41a6a8: e8 13 6f ff ff callq 4115c0 <__libc_message> - 41a6ad: 44 0f b6 4c 24 08 movzbl 0x8(%rsp),%r9d - 41a6b3: e9 ce f3 ff ff jmpq 419a86 <_int_free+0x2c6> - 41a6b8: 4c 8d 5c 24 30 lea 0x30(%rsp),%r11 - 41a6bd: 48 8d 74 24 40 lea 0x40(%rsp),%rsi - 41a6c2: 31 c9 xor %ecx,%ecx - 41a6c4: ba 10 00 00 00 mov $0x10,%edx - 41a6c9: 48 89 df mov %rbx,%rdi - 41a6cc: 44 88 4c 24 18 mov %r9b,0x18(%rsp) - 41a6d1: 44 89 54 24 10 mov %r10d,0x10(%rsp) - 41a6d6: 4c 89 5c 24 08 mov %r11,0x8(%rsp) - 41a6db: c6 44 24 40 00 movb $0x0,0x40(%rsp) - 41a6e0: e8 cb 77 03 00 callq 451eb0 <_itoa_word> - 41a6e5: 4c 8b 5c 24 08 mov 0x8(%rsp),%r11 - 41a6ea: 49 89 c0 mov %rax,%r8 - 41a6ed: 44 8b 54 24 10 mov 0x10(%rsp),%r10d - 41a6f2: 44 0f b6 4c 24 18 movzbl 0x18(%rsp),%r9d - 41a6f8: 4c 39 d8 cmp %r11,%rax - 41a6fb: 76 3d jbe 41a73a <_int_free+0xf7a> - 41a6fd: 4c 89 c2 mov %r8,%rdx - 41a700: 4c 89 c7 mov %r8,%rdi - 41a703: 48 8d 40 ff lea -0x1(%rax),%rax - 41a707: 4c 29 da sub %r11,%rdx - 41a70a: be 30 00 00 00 mov $0x30,%esi - 41a70f: 4c 89 44 24 08 mov %r8,0x8(%rsp) - 41a714: 48 29 d7 sub %rdx,%rdi - 41a717: 49 89 c6 mov %rax,%r14 - 41a71a: e8 31 5c fe ff callq 400350 <__rela_iplt_end+0x88> - 41a71f: 48 8d 44 24 2f lea 0x2f(%rsp),%rax - 41a724: 4c 8b 44 24 08 mov 0x8(%rsp),%r8 - 41a729: 44 0f b6 4c 24 18 movzbl 0x18(%rsp),%r9d - 41a72f: 44 8b 54 24 10 mov 0x10(%rsp),%r10d - 41a734: 4c 29 f0 sub %r14,%rax - 41a737: 49 01 c0 add %rax,%r8 - 41a73a: 48 8b 05 7f 2b 2b 00 mov 0x2b2b7f(%rip),%rax # 6cd2c0 <__libc_argv> - 41a741: 44 89 d7 mov %r10d,%edi - 41a744: ba 38 20 4a 00 mov $0x4a2038,%edx - 41a749: b9 78 20 4a 00 mov $0x4a2078,%ecx - 41a74e: be a8 23 4a 00 mov $0x4a23a8,%esi - 41a753: 44 88 4c 24 08 mov %r9b,0x8(%rsp) - 41a758: 48 8b 00 mov (%rax),%rax - 41a75b: 48 85 c0 test %rax,%rax - 41a75e: 48 0f 45 d0 cmovne %rax,%rdx - 41a762: 83 e7 02 and $0x2,%edi - 41a765: 31 c0 xor %eax,%eax - 41a767: e8 54 6e ff ff callq 4115c0 <__libc_message> - 41a76c: 44 0f b6 4c 24 08 movzbl 0x8(%rsp),%r9d - 41a772: e9 40 f2 ff ff jmpq 4199b7 <_int_free+0x1f7> - 41a777: 4c 8d 5c 24 30 lea 0x30(%rsp),%r11 - 41a77c: 48 8d 74 24 40 lea 0x40(%rsp),%rsi - 41a781: 31 c9 xor %ecx,%ecx - 41a783: ba 10 00 00 00 mov $0x10,%edx - 41a788: 4c 89 ef mov %r13,%rdi - 41a78b: 44 88 4c 24 18 mov %r9b,0x18(%rsp) - 41a790: 44 89 54 24 10 mov %r10d,0x10(%rsp) - 41a795: 4c 89 5c 24 08 mov %r11,0x8(%rsp) - 41a79a: c6 44 24 40 00 movb $0x0,0x40(%rsp) - 41a79f: e8 0c 77 03 00 callq 451eb0 <_itoa_word> - 41a7a4: 4c 8b 5c 24 08 mov 0x8(%rsp),%r11 - 41a7a9: 49 89 c0 mov %rax,%r8 - 41a7ac: 44 8b 54 24 10 mov 0x10(%rsp),%r10d - 41a7b1: 44 0f b6 4c 24 18 movzbl 0x18(%rsp),%r9d - 41a7b7: 4c 39 d8 cmp %r11,%rax - 41a7ba: 76 3d jbe 41a7f9 <_int_free+0x1039> - 41a7bc: 4c 89 c2 mov %r8,%rdx - 41a7bf: 4c 89 c7 mov %r8,%rdi - 41a7c2: 48 8d 40 ff lea -0x1(%rax),%rax - 41a7c6: 4c 29 da sub %r11,%rdx - 41a7c9: be 30 00 00 00 mov $0x30,%esi - 41a7ce: 4c 89 44 24 08 mov %r8,0x8(%rsp) - 41a7d3: 48 29 d7 sub %rdx,%rdi - 41a7d6: 49 89 c6 mov %rax,%r14 - 41a7d9: e8 72 5b fe ff callq 400350 <__rela_iplt_end+0x88> - 41a7de: 48 8d 44 24 2f lea 0x2f(%rsp),%rax - 41a7e3: 4c 8b 44 24 08 mov 0x8(%rsp),%r8 - 41a7e8: 44 0f b6 4c 24 18 movzbl 0x18(%rsp),%r9d - 41a7ee: 44 8b 54 24 10 mov 0x10(%rsp),%r10d - 41a7f3: 4c 29 f0 sub %r14,%rax - 41a7f6: 49 01 c0 add %rax,%r8 - 41a7f9: 48 8b 05 c0 2a 2b 00 mov 0x2b2ac0(%rip),%rax # 6cd2c0 <__libc_argv> - 41a800: 44 89 d7 mov %r10d,%edi - 41a803: ba 38 20 4a 00 mov $0x4a2038,%edx - 41a808: b9 78 20 4a 00 mov $0x4a2078,%ecx - 41a80d: be a8 23 4a 00 mov $0x4a23a8,%esi - 41a812: 44 88 4c 24 08 mov %r9b,0x8(%rsp) - 41a817: 48 8b 00 mov (%rax),%rax - 41a81a: 48 85 c0 test %rax,%rax - 41a81d: 48 0f 45 d0 cmovne %rax,%rdx - 41a821: 83 e7 02 and $0x2,%edi - 41a824: 31 c0 xor %eax,%eax - 41a826: e8 95 6d ff ff callq 4115c0 <__libc_message> - 41a82b: 44 0f b6 4c 24 08 movzbl 0x8(%rsp),%r9d - 41a831: e9 1b f2 ff ff jmpq 419a51 <_int_free+0x291> - 41a836: 48 8d 74 24 40 lea 0x40(%rsp),%rsi - 41a83b: 31 c9 xor %ecx,%ecx - 41a83d: ba 10 00 00 00 mov $0x10,%edx - 41a842: 4c 89 e7 mov %r12,%rdi - 41a845: 44 89 54 24 18 mov %r10d,0x18(%rsp) - 41a84a: c6 44 24 40 00 movb $0x0,0x40(%rsp) - 41a84f: e8 5c 76 03 00 callq 451eb0 <_itoa_word> - 41a854: 49 89 c0 mov %rax,%r8 - 41a857: 48 8d 44 24 30 lea 0x30(%rsp),%rax - 41a85c: 44 8b 54 24 18 mov 0x18(%rsp),%r10d - 41a861: 49 39 c0 cmp %rax,%r8 - 41a864: 76 46 jbe 41a8ac <_int_free+0x10ec> - 41a866: 48 8b 44 24 10 mov 0x10(%rsp),%rax - 41a86b: 49 8d 48 ff lea -0x1(%r8),%rcx - 41a86f: 4c 89 c7 mov %r8,%rdi - 41a872: be 30 00 00 00 mov $0x30,%esi - 41a877: 44 89 54 24 2c mov %r10d,0x2c(%rsp) - 41a87c: 4c 89 44 24 18 mov %r8,0x18(%rsp) - 41a881: 48 89 4c 24 20 mov %rcx,0x20(%rsp) - 41a886: 48 8d 14 08 lea (%rax,%rcx,1),%rdx - 41a88a: 48 29 d7 sub %rdx,%rdi - 41a88d: e8 be 5a fe ff callq 400350 <__rela_iplt_end+0x88> - 41a892: 48 8b 4c 24 20 mov 0x20(%rsp),%rcx - 41a897: 48 8d 44 24 2f lea 0x2f(%rsp),%rax - 41a89c: 4c 8b 44 24 18 mov 0x18(%rsp),%r8 - 41a8a1: 44 8b 54 24 2c mov 0x2c(%rsp),%r10d - 41a8a6: 48 29 c8 sub %rcx,%rax - 41a8a9: 49 01 c0 add %rax,%r8 - 41a8ac: 48 8b 05 0d 2a 2b 00 mov 0x2b2a0d(%rip),%rax # 6cd2c0 <__libc_argv> - 41a8b3: 44 89 d7 mov %r10d,%edi - 41a8b6: ba 38 20 4a 00 mov $0x4a2038,%edx - 41a8bb: b9 f0 23 4a 00 mov $0x4a23f0,%ecx - 41a8c0: be a8 23 4a 00 mov $0x4a23a8,%esi - 41a8c5: 48 8b 00 mov (%rax),%rax - 41a8c8: 48 85 c0 test %rax,%rax - 41a8cb: 48 0f 45 d0 cmovne %rax,%rdx - 41a8cf: 31 c0 xor %eax,%eax - 41a8d1: 83 e7 02 and $0x2,%edi - 41a8d4: e8 e7 6c ff ff callq 4115c0 <__libc_message> - 41a8d9: 49 8b 44 24 20 mov 0x20(%r12),%rax - 41a8de: e9 ee f9 ff ff jmpq 41a2d1 <_int_free+0xb11> - 41a8e3: 44 89 d7 mov %r10d,%edi - 41a8e6: ba 95 20 4a 00 mov $0x4a2095,%edx - 41a8eb: be 3c ca 4b 00 mov $0x4bca3c,%esi - 41a8f0: 83 e7 02 and $0x2,%edi - 41a8f3: 31 c0 xor %eax,%eax - 41a8f5: 44 88 4c 24 08 mov %r9b,0x8(%rsp) - 41a8fa: e8 c1 6c ff ff callq 4115c0 <__libc_message> - 41a8ff: 44 0f b6 4c 24 08 movzbl 0x8(%rsp),%r9d - 41a905: e9 1e f1 ff ff jmpq 419a28 <_int_free+0x268> - 41a90a: 44 89 d7 mov %r10d,%edi - 41a90d: ba 95 20 4a 00 mov $0x4a2095,%edx - 41a912: be 3c ca 4b 00 mov $0x4bca3c,%esi - 41a917: 83 e7 02 and $0x2,%edi - 41a91a: 31 c0 xor %eax,%eax - 41a91c: 44 88 4c 24 08 mov %r9b,0x8(%rsp) - 41a921: e8 9a 6c ff ff callq 4115c0 <__libc_message> - 41a926: 44 0f b6 4c 24 08 movzbl 0x8(%rsp),%r9d - 41a92c: e9 55 f1 ff ff jmpq 419a86 <_int_free+0x2c6> - 41a931: 45 31 c9 xor %r9d,%r9d - 41a934: 31 d2 xor %edx,%edx - 41a936: 41 b8 ff ff ff ff mov $0xffffffff,%r8d - 41a93c: b9 32 00 00 00 mov $0x32,%ecx - 41a941: 4c 89 ee mov %r13,%rsi - 41a944: e8 a7 52 02 00 callq 43fbf0 <__mmap> - 41a949: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 41a94d: 0f 84 2d f5 ff ff je 419e80 <_int_free+0x6c0> - 41a953: 4d 89 77 18 mov %r14,0x18(%r15) - 41a957: e9 fe f4 ff ff jmpq 419e5a <_int_free+0x69a> - 41a95c: 44 8b 05 35 f6 2a 00 mov 0x2af635(%rip),%r8d # 6c9f98 <__libc_enable_secure> - 41a963: 45 85 c0 test %r8d,%r8d - 41a966: 44 89 05 f3 fd 2a 00 mov %r8d,0x2afdf3(%rip) # 6ca760 - 41a96d: 75 64 jne 41a9d3 <_int_free+0x1213> - 41a96f: be 00 00 08 00 mov $0x80000,%esi - 41a974: bf 00 26 4a 00 mov $0x4a2600,%edi - 41a979: b8 02 00 00 00 mov $0x2,%eax - 41a97e: 0f 05 syscall - 41a980: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 41a986: 0f 87 27 02 00 00 ja 41abb3 <_int_free+0x13f3> - 41a98c: 85 c0 test %eax,%eax - 41a98e: 78 43 js 41a9d3 <_int_free+0x1213> - 41a990: 4c 63 c8 movslq %eax,%r9 - 41a993: ba 01 00 00 00 mov $0x1,%edx - 41a998: 48 8d 74 24 30 lea 0x30(%rsp),%rsi - 41a99d: 4c 89 cf mov %r9,%rdi - 41a9a0: 44 89 c0 mov %r8d,%eax - 41a9a3: 0f 05 syscall - 41a9a5: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 41a9ab: 0f 87 f1 01 00 00 ja 41aba2 <_int_free+0x13e2> - 41a9b1: 48 85 c0 test %rax,%rax - 41a9b4: 7e 0c jle 41a9c2 <_int_free+0x1202> - 41a9b6: 45 31 c0 xor %r8d,%r8d - 41a9b9: 80 7c 24 30 32 cmpb $0x32,0x30(%rsp) - 41a9be: 41 0f 94 c0 sete %r8b - 41a9c2: 44 89 05 97 fd 2a 00 mov %r8d,0x2afd97(%rip) # 6ca760 - 41a9c9: 4c 89 cf mov %r9,%rdi - 41a9cc: b8 03 00 00 00 mov $0x3,%eax - 41a9d1: 0f 05 syscall - 41a9d3: 8b 0d 87 fd 2a 00 mov 0x2afd87(%rip),%ecx # 6ca760 - 41a9d9: 85 c9 test %ecx,%ecx - 41a9db: 0f 95 c0 setne %al - 41a9de: e9 5e f4 ff ff jmpq 419e41 <_int_free+0x681> - 41a9e3: b9 88 2e 4a 00 mov $0x4a2e88,%ecx - 41a9e8: ba 37 02 00 00 mov $0x237,%edx - 41a9ed: be a8 1f 4a 00 mov $0x4a1fa8,%esi - 41a9f2: bf 28 25 4a 00 mov $0x4a2528,%edi - 41a9f7: e8 24 c4 ff ff callq 416e20 <__malloc_assert> - 41a9fc: b9 88 2e 4a 00 mov $0x4a2e88,%ecx - 41aa01: ba 34 02 00 00 mov $0x234,%edx - 41aa06: be a8 1f 4a 00 mov $0x4a1fa8,%esi - 41aa0b: bf 0f 21 4a 00 mov $0x4a210f,%edi - 41aa10: e8 0b c4 ff ff callq 416e20 <__malloc_assert> - 41aa15: 44 89 d7 mov %r10d,%edi - 41aa18: ba 78 20 4a 00 mov $0x4a2078,%edx - 41aa1d: be 3c ca 4b 00 mov $0x4bca3c,%esi - 41aa22: 83 e7 02 and $0x2,%edi - 41aa25: 31 c0 xor %eax,%eax - 41aa27: 44 88 4c 24 08 mov %r9b,0x8(%rsp) - 41aa2c: e8 8f 6b ff ff callq 4115c0 <__libc_message> - 41aa31: 44 0f b6 4c 24 08 movzbl 0x8(%rsp),%r9d - 41aa37: e9 7b ef ff ff jmpq 4199b7 <_int_free+0x1f7> - 41aa3c: 44 89 d7 mov %r10d,%edi - 41aa3f: ba 78 20 4a 00 mov $0x4a2078,%edx - 41aa44: be 3c ca 4b 00 mov $0x4bca3c,%esi - 41aa49: 83 e7 02 and $0x2,%edi - 41aa4c: 31 c0 xor %eax,%eax - 41aa4e: 44 88 4c 24 08 mov %r9b,0x8(%rsp) - 41aa53: e8 68 6b ff ff callq 4115c0 <__libc_message> - 41aa58: 44 0f b6 4c 24 08 movzbl 0x8(%rsp),%r9d - 41aa5e: e9 ee ef ff ff jmpq 419a51 <_int_free+0x291> - 41aa63: b9 88 2e 4a 00 mov $0x4a2e88,%ecx - 41aa68: ba 3a 02 00 00 mov $0x23a,%edx - 41aa6d: be a8 1f 4a 00 mov $0x4a1fa8,%esi - 41aa72: bf 58 25 4a 00 mov $0x4a2558,%edi - 41aa77: e8 a4 c3 ff ff callq 416e20 <__malloc_assert> - 41aa7c: b9 88 2e 4a 00 mov $0x4a2e88,%ecx - 41aa81: ba 48 02 00 00 mov $0x248,%edx - 41aa86: be a8 1f 4a 00 mov $0x4a1fa8,%esi - 41aa8b: bf c8 25 4a 00 mov $0x4a25c8,%edi - 41aa90: e8 8b c3 ff ff callq 416e20 <__malloc_assert> - 41aa95: b9 88 2e 4a 00 mov $0x4a2e88,%ecx - 41aa9a: ba 47 02 00 00 mov $0x247,%edx - 41aa9f: be a8 1f 4a 00 mov $0x4a1fa8,%esi - 41aaa4: bf 88 25 4a 00 mov $0x4a2588,%edi - 41aaa9: e8 72 c3 ff ff callq 416e20 <__malloc_assert> - 41aaae: 4d 89 76 28 mov %r14,0x28(%r14) - 41aab2: 4d 89 76 20 mov %r14,0x20(%r14) - 41aab6: e9 25 f1 ff ff jmpq 419be0 <_int_free+0x420> - 41aabb: 8b 3d af fc 2a 00 mov 0x2afcaf(%rip),%edi # 6ca770 - 41aac1: 48 89 da mov %rbx,%rdx - 41aac4: 48 89 e9 mov %rbp,%rcx - 41aac7: be f0 23 4a 00 mov $0x4a23f0,%esi - 41aacc: 44 88 4c 24 10 mov %r9b,0x10(%rsp) - 41aad1: 48 89 44 24 08 mov %rax,0x8(%rsp) - 41aad6: e8 d5 c7 ff ff callq 4172b0 - 41aadb: 48 8b 53 20 mov 0x20(%rbx),%rdx - 41aadf: 44 0f b6 4c 24 10 movzbl 0x10(%rsp),%r9d - 41aae5: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 41aaea: e9 17 ef ff ff jmpq 419a06 <_int_free+0x246> - 41aaef: 44 89 d7 mov %r10d,%edi - 41aaf2: 31 c0 xor %eax,%eax - 41aaf4: ba f0 23 4a 00 mov $0x4a23f0,%edx - 41aaf9: 83 e7 02 and $0x2,%edi - 41aafc: be 3c ca 4b 00 mov $0x4bca3c,%esi - 41ab01: e8 ba 6a ff ff callq 4115c0 <__libc_message> - 41ab06: 49 8b 44 24 20 mov 0x20(%r12),%rax - 41ab0b: e9 c1 f7 ff ff jmpq 41a2d1 <_int_free+0xb11> - 41ab10: 48 39 d3 cmp %rdx,%rbx - 41ab13: 0f 84 f9 00 00 00 je 41ac12 <_int_free+0x1452> - 41ab19: 48 89 50 20 mov %rdx,0x20(%rax) - 41ab1d: 48 8b 53 28 mov 0x28(%rbx),%rdx - 41ab21: 48 89 50 28 mov %rdx,0x28(%rax) - 41ab25: 48 8b 53 20 mov 0x20(%rbx),%rdx - 41ab29: 48 89 42 28 mov %rax,0x28(%rdx) - 41ab2d: 48 8b 53 28 mov 0x28(%rbx),%rdx - 41ab31: 48 89 42 20 mov %rax,0x20(%rdx) - 41ab35: e9 ee ee ff ff jmpq 419a28 <_int_free+0x268> - 41ab3a: 49 39 d0 cmp %rdx,%r8 - 41ab3d: 0f 84 dc 00 00 00 je 41ac1f <_int_free+0x145f> - 41ab43: 48 89 50 20 mov %rdx,0x20(%rax) - 41ab47: 49 8b 50 28 mov 0x28(%r8),%rdx - 41ab4b: 48 89 50 28 mov %rdx,0x28(%rax) - 41ab4f: 49 8b 50 20 mov 0x20(%r8),%rdx - 41ab53: 48 89 42 28 mov %rax,0x28(%rdx) - 41ab57: 49 8b 50 28 mov 0x28(%r8),%rdx - 41ab5b: 48 89 42 20 mov %rax,0x20(%rdx) - 41ab5f: e9 22 ef ff ff jmpq 419a86 <_int_free+0x2c6> - 41ab64: 8b 3d 06 fc 2a 00 mov 0x2afc06(%rip),%edi # 6ca770 - 41ab6a: 4c 89 c2 mov %r8,%rdx - 41ab6d: 48 89 e9 mov %rbp,%rcx - 41ab70: be f0 23 4a 00 mov $0x4a23f0,%esi - 41ab75: 44 88 4c 24 18 mov %r9b,0x18(%rsp) - 41ab7a: 48 89 44 24 10 mov %rax,0x10(%rsp) - 41ab7f: 4c 89 44 24 08 mov %r8,0x8(%rsp) - 41ab84: e8 27 c7 ff ff callq 4172b0 - 41ab89: 4c 8b 44 24 08 mov 0x8(%rsp),%r8 - 41ab8e: 44 0f b6 4c 24 18 movzbl 0x18(%rsp),%r9d - 41ab94: 48 8b 44 24 10 mov 0x10(%rsp),%rax - 41ab99: 49 8b 50 20 mov 0x20(%r8),%rdx - 41ab9d: e9 03 f5 ff ff jmpq 41a0a5 <_int_free+0x8e5> - 41aba2: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx - 41aba9: f7 d8 neg %eax - 41abab: 64 89 02 mov %eax,%fs:(%rdx) - 41abae: e9 0f fe ff ff jmpq 41a9c2 <_int_free+0x1202> - 41abb3: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx - 41abba: f7 d8 neg %eax - 41abbc: 64 89 02 mov %eax,%fs:(%rdx) - 41abbf: e9 0f fe ff ff jmpq 41a9d3 <_int_free+0x1213> - 41abc4: b9 98 2e 4a 00 mov $0x4a2e98,%ecx - 41abc9: ba fe 0f 00 00 mov $0xffe,%edx - 41abce: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 41abd3: bf 2b 21 4a 00 mov $0x4a212b,%edi - 41abd8: e8 43 c2 ff ff callq 416e20 <__malloc_assert> - 41abdd: b9 98 2e 4a 00 mov $0x4a2e98,%ecx - 41abe2: ba f8 0f 00 00 mov $0xff8,%edx - 41abe7: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 41abec: bf fc 20 4a 00 mov $0x4a20fc,%edi - 41abf1: e8 2a c2 ff ff callq 416e20 <__malloc_assert> - 41abf6: 48 8d 7e 10 lea 0x10(%rsi),%rdi - 41abfa: 41 bd 98 24 4a 00 mov $0x4a2498,%r13d - 41ac00: 44 8b 25 69 fb 2a 00 mov 0x2afb69(%rip),%r12d # 6ca770 - 41ac07: e9 d8 ec ff ff jmpq 4198e4 <_int_free+0x124> - 41ac0c: 48 8d 7b 10 lea 0x10(%rbx),%rdi - 41ac10: eb ee jmp 41ac00 <_int_free+0x1440> - 41ac12: 48 89 40 28 mov %rax,0x28(%rax) - 41ac16: 48 89 40 20 mov %rax,0x20(%rax) - 41ac1a: e9 09 ee ff ff jmpq 419a28 <_int_free+0x268> - 41ac1f: 48 89 40 28 mov %rax,0x28(%rax) - 41ac23: 48 89 40 20 mov %rax,0x20(%rax) - 41ac27: e9 5a ee ff ff jmpq 419a86 <_int_free+0x2c6> - 41ac2c: 0f 1f 40 00 nopl 0x0(%rax) - -000000000041ac30 : - 41ac30: 41 57 push %r15 - 41ac32: 41 56 push %r14 - 41ac34: 41 55 push %r13 - 41ac36: 41 54 push %r12 - 41ac38: 55 push %rbp - 41ac39: 53 push %rbx - 41ac3a: 48 89 fd mov %rdi,%rbp - 41ac3d: 48 83 ec 58 sub $0x58,%rsp - 41ac41: 48 85 f6 test %rsi,%rsi - 41ac44: 4c 8b 3d 35 05 2b 00 mov 0x2b0535(%rip),%r15 # 6cb180 <_dl_pagesize> - 41ac4b: 0f 84 bf 02 00 00 je 41af10 - 41ac51: 48 39 3d 58 fb 2a 00 cmp %rdi,0x2afb58(%rip) # 6ca7b0 - 41ac58: 48 89 f3 mov %rsi,%rbx - 41ac5b: 0f 86 8f 01 00 00 jbe 41adf0 - 41ac61: c6 44 24 08 00 movb $0x0,0x8(%rsp) - 41ac66: 48 8d 43 58 lea 0x58(%rbx),%rax - 41ac6a: 4d 8d 74 2f 07 lea 0x7(%r15,%rbp,1),%r14 - 41ac6f: 48 89 04 24 mov %rax,(%rsp) - 41ac73: 4c 89 f8 mov %r15,%rax - 41ac76: 48 f7 d8 neg %rax - 41ac79: 49 21 c6 and %rax,%r14 - 41ac7c: 4c 89 74 24 18 mov %r14,0x18(%rsp) - 41ac81: 4c 8b 6b 58 mov 0x58(%rbx),%r13 - 41ac85: 49 8b 45 08 mov 0x8(%r13),%rax - 41ac89: 49 89 c4 mov %rax,%r12 - 41ac8c: 49 83 e4 f8 and $0xfffffffffffffff8,%r12 - 41ac90: 4d 85 e4 test %r12,%r12 - 41ac93: 4f 8d 54 25 00 lea 0x0(%r13,%r12,1),%r10 - 41ac98: 41 0f 95 c3 setne %r11b - 41ac9c: 4c 3b 2c 24 cmp (%rsp),%r13 - 41aca0: 0f 85 1a 01 00 00 jne 41adc0 - 41aca6: 45 84 db test %r11b,%r11b - 41aca9: 0f 85 11 01 00 00 jne 41adc0 - 41acaf: 4c 8d 45 20 lea 0x20(%rbp),%r8 - 41acb3: 4d 39 c4 cmp %r8,%r12 - 41acb6: 0f 83 b7 07 00 00 jae 41b473 - 41acbc: 48 81 fb 00 a8 6c 00 cmp $0x6ca800,%rbx - 41acc3: 0f 84 f7 02 00 00 je 41afc0 - 41acc9: 48 89 ea mov %rbp,%rdx - 41accc: 4d 89 ee mov %r13,%r14 - 41accf: 4c 29 e2 sub %r12,%rdx - 41acd2: 49 81 e6 00 00 00 fc and $0xfffffffffc000000,%r14 - 41acd9: 48 83 c2 20 add $0x20,%rdx - 41acdd: 48 85 d2 test %rdx,%rdx - 41ace0: 0f 8e 42 01 00 00 jle 41ae28 - 41ace6: 48 8b 05 93 04 2b 00 mov 0x2b0493(%rip),%rax # 6cb180 <_dl_pagesize> - 41aced: 4d 8b 4e 10 mov 0x10(%r14),%r9 - 41acf1: 48 8d 4c 02 ff lea -0x1(%rdx,%rax,1),%rcx - 41acf6: 48 f7 d8 neg %rax - 41acf9: 48 21 c8 and %rcx,%rax - 41acfc: 4a 8d 0c 08 lea (%rax,%r9,1),%rcx - 41ad00: 48 81 f9 00 00 00 04 cmp $0x4000000,%rcx - 41ad07: 0f 87 1b 01 00 00 ja 41ae28 - 41ad0d: 49 8b 7e 18 mov 0x18(%r14),%rdi - 41ad11: 48 39 f9 cmp %rdi,%rcx - 41ad14: 0f 87 a6 01 00 00 ja 41aec0 - 41ad1a: 4c 89 f0 mov %r14,%rax - 41ad1d: 4c 89 ea mov %r13,%rdx - 41ad20: 4d 89 c6 mov %r8,%r14 - 41ad23: 49 89 c0 mov %rax,%r8 - 41ad26: 49 89 48 10 mov %rcx,0x10(%r8) - 41ad2a: 90 nop - 41ad2b: 48 89 c8 mov %rcx,%rax - 41ad2e: 4c 01 c1 add %r8,%rcx - 41ad31: 4c 29 c8 sub %r9,%rax - 41ad34: 48 01 05 dd 18 2b 00 add %rax,0x2b18dd(%rip) # 6cc618 - 41ad3b: 4c 29 e9 sub %r13,%rcx - 41ad3e: 48 89 c6 mov %rax,%rsi - 41ad41: 48 03 b3 80 08 00 00 add 0x880(%rbx),%rsi - 41ad48: 48 83 c9 01 or $0x1,%rcx - 41ad4c: 48 89 b3 80 08 00 00 mov %rsi,0x880(%rbx) - 41ad53: 49 89 4d 08 mov %rcx,0x8(%r13) - 41ad57: 48 39 b3 88 08 00 00 cmp %rsi,0x888(%rbx) - 41ad5e: 73 07 jae 41ad67 - 41ad60: 48 89 b3 88 08 00 00 mov %rsi,0x888(%rbx) - 41ad67: 48 8b 42 08 mov 0x8(%rdx),%rax - 41ad6b: 48 83 e0 f8 and $0xfffffffffffffff8,%rax - 41ad6f: 49 39 c6 cmp %rax,%r14 - 41ad72: 0f 87 58 03 00 00 ja 41b0d0 - 41ad78: 48 29 e8 sub %rbp,%rax - 41ad7b: 31 c9 xor %ecx,%ecx - 41ad7d: 48 81 fb 00 a8 6c 00 cmp $0x6ca800,%rbx - 41ad84: 0f 95 c1 setne %cl - 41ad87: 48 8d 34 2a lea (%rdx,%rbp,1),%rsi - 41ad8b: 48 83 cd 01 or $0x1,%rbp - 41ad8f: 48 c1 e1 02 shl $0x2,%rcx - 41ad93: 48 83 c8 01 or $0x1,%rax - 41ad97: 48 83 c2 10 add $0x10,%rdx - 41ad9b: 48 09 e9 or %rbp,%rcx - 41ad9e: 48 89 73 58 mov %rsi,0x58(%rbx) - 41ada2: 48 89 4a f8 mov %rcx,-0x8(%rdx) - 41ada6: 48 89 46 08 mov %rax,0x8(%rsi) - 41adaa: 48 83 c4 58 add $0x58,%rsp - 41adae: 48 89 d0 mov %rdx,%rax - 41adb1: 5b pop %rbx - 41adb2: 5d pop %rbp - 41adb3: 41 5c pop %r12 - 41adb5: 41 5d pop %r13 - 41adb7: 41 5e pop %r14 - 41adb9: 41 5f pop %r15 - 41adbb: c3 retq - 41adbc: 0f 1f 40 00 nopl 0x0(%rax) - 41adc0: 49 83 fc 1f cmp $0x1f,%r12 - 41adc4: 76 11 jbe 41add7 - 41adc6: a8 01 test $0x1,%al - 41adc8: 74 0d je 41add7 - 41adca: 49 8d 47 ff lea -0x1(%r15),%rax - 41adce: 49 85 c2 test %rax,%r10 - 41add1: 0f 84 d8 fe ff ff je 41acaf - 41add7: b9 a8 2e 4a 00 mov $0x4a2ea8,%ecx - 41addc: ba 5a 09 00 00 mov $0x95a,%edx - 41ade1: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 41ade6: bf 60 26 4a 00 mov $0x4a2660,%edi - 41adeb: e8 30 c0 ff ff callq 416e20 <__malloc_assert> - 41adf0: 8b 05 d6 f9 2a 00 mov 0x2af9d6(%rip),%eax # 6ca7cc - 41adf6: 39 05 cc f9 2a 00 cmp %eax,0x2af9cc(%rip) # 6ca7c8 - 41adfc: 0f 8d 5f fe ff ff jge 41ac61 - 41ae02: 4d 8d 64 3f 07 lea 0x7(%r15,%rdi,1),%r12 - 41ae07: 4c 89 f8 mov %r15,%rax - 41ae0a: 48 f7 d8 neg %rax - 41ae0d: 49 21 c4 and %rax,%r12 - 41ae10: 4c 39 e7 cmp %r12,%rdi - 41ae13: 0f 82 9e 06 00 00 jb 41b4b7 - 41ae19: c6 44 24 08 01 movb $0x1,0x8(%rsp) - 41ae1e: e9 43 fe ff ff jmpq 41ac66 - 41ae23: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41ae28: 48 8b 35 79 f9 2a 00 mov 0x2af979(%rip),%rsi # 6ca7a8 - 41ae2f: 48 8d 7d 40 lea 0x40(%rbp),%rdi - 41ae33: 4c 89 44 24 10 mov %r8,0x10(%rsp) - 41ae38: e8 43 c0 ff ff callq 416e80 - 41ae3d: 48 85 c0 test %rax,%rax - 41ae40: 4c 8b 44 24 10 mov 0x10(%rsp),%r8 - 41ae45: 0f 84 9d 02 00 00 je 41b0e8 - 41ae4b: 48 8b 48 10 mov 0x10(%rax),%rcx - 41ae4f: 48 8d 50 20 lea 0x20(%rax),%rdx - 41ae53: 48 01 0d be 17 2b 00 add %rcx,0x2b17be(%rip) # 6cc618 - 41ae5a: 49 83 ec 20 sub $0x20,%r12 - 41ae5e: 4c 89 f7 mov %r14,%rdi - 41ae61: 48 89 18 mov %rbx,(%rax) - 41ae64: 49 83 e4 f0 and $0xfffffffffffffff0,%r12 - 41ae68: 48 89 78 08 mov %rdi,0x8(%rax) - 41ae6c: 48 89 53 58 mov %rdx,0x58(%rbx) - 41ae70: 48 89 ce mov %rcx,%rsi - 41ae73: 48 03 b3 80 08 00 00 add 0x880(%rbx),%rsi - 41ae7a: 48 83 e9 20 sub $0x20,%rcx - 41ae7e: 48 83 c9 01 or $0x1,%rcx - 41ae82: 49 83 fc 1f cmp $0x1f,%r12 - 41ae86: 4d 89 c6 mov %r8,%r14 - 41ae89: 48 89 b3 80 08 00 00 mov %rsi,0x880(%rbx) - 41ae90: 48 89 48 28 mov %rcx,0x28(%rax) - 41ae94: 49 8d 44 24 10 lea 0x10(%r12),%rax - 41ae99: 49 8d 4c 05 00 lea 0x0(%r13,%rax,1),%rcx - 41ae9e: 48 c7 41 08 01 00 00 movq $0x1,0x8(%rcx) - 41aea5: 00 - 41aea6: 0f 87 ec 01 00 00 ja 41b098 - 41aeac: 48 89 c7 mov %rax,%rdi - 41aeaf: 48 83 cf 01 or $0x1,%rdi - 41aeb3: 49 89 7d 08 mov %rdi,0x8(%r13) - 41aeb7: 48 89 01 mov %rax,(%rcx) - 41aeba: e9 98 fe ff ff jmpq 41ad57 - 41aebf: 90 nop - 41aec0: 48 89 ce mov %rcx,%rsi - 41aec3: ba 03 00 00 00 mov $0x3,%edx - 41aec8: 4c 89 44 24 10 mov %r8,0x10(%rsp) - 41aecd: 48 29 fe sub %rdi,%rsi - 41aed0: 4c 01 f7 add %r14,%rdi - 41aed3: 4c 89 4c 24 28 mov %r9,0x28(%rsp) - 41aed8: 48 89 4c 24 20 mov %rcx,0x20(%rsp) - 41aedd: e8 ee 4d 02 00 callq 43fcd0 <__mprotect> - 41aee2: 85 c0 test %eax,%eax - 41aee4: 4c 8b 44 24 10 mov 0x10(%rsp),%r8 - 41aee9: 0f 85 39 ff ff ff jne 41ae28 - 41aeef: 48 8b 4c 24 20 mov 0x20(%rsp),%rcx - 41aef4: 4c 89 f0 mov %r14,%rax - 41aef7: 4c 8b 4c 24 28 mov 0x28(%rsp),%r9 - 41aefc: 4d 89 c6 mov %r8,%r14 - 41aeff: 48 8b 53 58 mov 0x58(%rbx),%rdx - 41af03: 49 89 c0 mov %rax,%r8 - 41af06: 48 89 48 18 mov %rcx,0x18(%rax) - 41af0a: e9 17 fe ff ff jmpq 41ad26 - 41af0f: 90 nop - 41af10: 4d 8d 64 3f 07 lea 0x7(%r15,%rdi,1),%r12 - 41af15: 4d 89 fa mov %r15,%r10 - 41af18: 49 f7 da neg %r10 - 41af1b: 4d 21 d4 and %r10,%r12 - 41af1e: 4c 39 e7 cmp %r12,%rdi - 41af21: 0f 83 b7 01 00 00 jae 41b0de - 41af27: 45 31 c9 xor %r9d,%r9d - 41af2a: 31 ff xor %edi,%edi - 41af2c: 41 b8 ff ff ff ff mov $0xffffffff,%r8d - 41af32: b9 22 00 00 00 mov $0x22,%ecx - 41af37: ba 03 00 00 00 mov $0x3,%edx - 41af3c: 4c 89 e6 mov %r12,%rsi - 41af3f: e8 ac 4c 02 00 callq 43fbf0 <__mmap> - 41af44: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 41af48: 0f 84 90 01 00 00 je 41b0de - 41af4e: 48 8d 50 10 lea 0x10(%rax),%rdx - 41af52: f6 c2 0f test $0xf,%dl - 41af55: 0f 85 86 05 00 00 jne 41b4e1 - 41af5b: 4c 89 e1 mov %r12,%rcx - 41af5e: 48 83 c9 02 or $0x2,%rcx - 41af62: 48 89 48 08 mov %rcx,0x8(%rax) - 41af66: b9 01 00 00 00 mov $0x1,%ecx - 41af6b: f0 0f c1 0d 55 f8 2a lock xadd %ecx,0x2af855(%rip) # 6ca7c8 - 41af72: 00 - 41af73: 83 c1 01 add $0x1,%ecx - 41af76: 8b 05 54 f8 2a 00 mov 0x2af854(%rip),%eax # 6ca7d0 - 41af7c: 39 c1 cmp %eax,%ecx - 41af7e: 7e 0a jle 41af8a - 41af80: f0 0f b1 0d 48 f8 2a lock cmpxchg %ecx,0x2af848(%rip) # 6ca7d0 - 41af87: 00 - 41af88: 75 ec jne 41af76 - 41af8a: 4d 89 e2 mov %r12,%r10 - 41af8d: f0 4c 0f c1 15 42 f8 lock xadd %r10,0x2af842(%rip) # 6ca7d8 - 41af94: 2a 00 - 41af96: 4d 01 e2 add %r12,%r10 - 41af99: 48 8b 05 40 f8 2a 00 mov 0x2af840(%rip),%rax # 6ca7e0 - 41afa0: 49 39 c2 cmp %rax,%r10 - 41afa3: 0f 86 01 fe ff ff jbe 41adaa - 41afa9: f0 4c 0f b1 15 2e f8 lock cmpxchg %r10,0x2af82e(%rip) # 6ca7e0 - 41afb0: 2a 00 - 41afb2: 0f 84 f2 fd ff ff je 41adaa - 41afb8: eb df jmp 41af99 - 41afba: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 41afc0: f6 05 3d f8 2a 00 02 testb $0x2,0x2af83d(%rip) # 6ca804 - 41afc7: 48 8b 05 da f7 2a 00 mov 0x2af7da(%rip),%rax # 6ca7a8 - 41afce: 4d 89 c6 mov %r8,%r14 - 41afd1: 48 8d 54 05 20 lea 0x20(%rbp,%rax,1),%rdx - 41afd6: 0f 84 34 01 00 00 je 41b110 - 41afdc: 49 8d 47 ff lea -0x1(%r15),%rax - 41afe0: 49 f7 df neg %r15 - 41afe3: 4c 89 7c 24 08 mov %r15,0x8(%rsp) - 41afe8: 48 01 c2 add %rax,%rdx - 41afeb: 48 89 04 24 mov %rax,(%rsp) - 41afef: 4c 21 fa and %r15,%rdx - 41aff2: 48 85 d2 test %rdx,%rdx - 41aff5: 49 89 d7 mov %rdx,%r15 - 41aff8: 0f 8e 49 01 00 00 jle 41b147 - 41affe: 48 89 d7 mov %rdx,%rdi - 41b001: 48 89 54 24 10 mov %rdx,0x10(%rsp) - 41b006: 44 88 5c 24 20 mov %r11b,0x20(%rsp) - 41b00b: 4c 89 54 24 18 mov %r10,0x18(%rsp) - 41b010: ff 15 7a 00 2b 00 callq *0x2b007a(%rip) # 6cb090 <__morecore> - 41b016: 48 8b 54 24 10 mov 0x10(%rsp),%rdx - 41b01b: 49 89 c0 mov %rax,%r8 - 41b01e: 90 nop - 41b01f: 48 85 c0 test %rax,%rax - 41b022: 4c 8b 54 24 18 mov 0x18(%rsp),%r10 - 41b027: 44 0f b6 5c 24 20 movzbl 0x20(%rsp),%r11d - 41b02d: 0f 84 72 04 00 00 je 41b4a5 - 41b033: 48 8b 05 a6 15 2b 00 mov 0x2b15a6(%rip),%rax # 6cc5e0 <__after_morecore_hook> - 41b03a: 48 85 c0 test %rax,%rax - 41b03d: 0f 85 3d 03 00 00 jne 41b380 - 41b043: ba 01 00 00 00 mov $0x1,%edx - 41b048: 31 c0 xor %eax,%eax - 41b04a: 48 83 3d 9e f7 2a 00 cmpq $0x0,0x2af79e(%rip) # 6ca7f0 - 41b051: 00 - 41b052: 0f 84 08 03 00 00 je 41b360 - 41b058: 4c 89 fe mov %r15,%rsi - 41b05b: 48 03 35 1e 00 2b 00 add 0x2b001e(%rip),%rsi # 6cb080 - 41b062: 4d 39 c2 cmp %r8,%r10 - 41b065: 48 89 35 14 00 2b 00 mov %rsi,0x2b0014(%rip) # 6cb080 - 41b06c: 0f 85 5e 01 00 00 jne 41b1d0 - 41b072: 84 d2 test %dl,%dl - 41b074: 0f 84 56 01 00 00 je 41b1d0 - 41b07a: 4d 01 fc add %r15,%r12 - 41b07d: 48 8b 15 d4 f7 2a 00 mov 0x2af7d4(%rip),%rdx # 6ca858 - 41b084: 49 83 cc 01 or $0x1,%r12 - 41b088: 4d 89 65 08 mov %r12,0x8(%r13) - 41b08c: e9 c6 fc ff ff jmpq 41ad57 - 41b091: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 41b098: 4b c7 44 25 08 11 00 movq $0x11,0x8(%r13,%r12,1) - 41b09f: 00 00 - 41b0a1: 49 83 cc 05 or $0x5,%r12 - 41b0a5: 48 c7 01 10 00 00 00 movq $0x10,(%rcx) - 41b0ac: ba 01 00 00 00 mov $0x1,%edx - 41b0b1: 4c 89 ee mov %r13,%rsi - 41b0b4: 4d 89 65 08 mov %r12,0x8(%r13) - 41b0b8: 48 89 df mov %rbx,%rdi - 41b0bb: e8 00 e7 ff ff callq 4197c0 <_int_free> - 41b0c0: 48 8b b3 80 08 00 00 mov 0x880(%rbx),%rsi - 41b0c7: 48 8b 53 58 mov 0x58(%rbx),%rdx - 41b0cb: e9 87 fc ff ff jmpq 41ad57 - 41b0d0: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 41b0d7: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) - 41b0de: 31 d2 xor %edx,%edx - 41b0e0: e9 c5 fc ff ff jmpq 41adaa - 41b0e5: 0f 1f 00 nopl (%rax) - 41b0e8: 80 7c 24 08 00 cmpb $0x0,0x8(%rsp) - 41b0ed: 0f 85 0d 02 00 00 jne 41b300 - 41b0f3: 48 8b 44 24 18 mov 0x18(%rsp),%rax - 41b0f8: 48 39 c5 cmp %rax,%rbp - 41b0fb: 49 89 c4 mov %rax,%r12 - 41b0fe: 0f 82 f6 03 00 00 jb 41b4fa - 41b104: c6 44 24 08 01 movb $0x1,0x8(%rsp) - 41b109: e9 73 fb ff ff jmpq 41ac81 - 41b10e: 66 90 xchg %ax,%ax - 41b110: 49 8d 47 ff lea -0x1(%r15),%rax - 41b114: 4c 29 e2 sub %r12,%rdx - 41b117: 49 f7 df neg %r15 - 41b11a: 4c 89 7c 24 08 mov %r15,0x8(%rsp) - 41b11f: 48 01 c2 add %rax,%rdx - 41b122: 48 89 04 24 mov %rax,(%rsp) - 41b126: 4c 21 fa and %r15,%rdx - 41b129: 48 85 d2 test %rdx,%rdx - 41b12c: 49 89 d7 mov %rdx,%r15 - 41b12f: 0f 8f c9 fe ff ff jg 41affe - 41b135: 48 8b 04 24 mov (%rsp),%rax - 41b139: 4c 01 e0 add %r12,%rax - 41b13c: 48 01 d0 add %rdx,%rax - 41b13f: 48 23 44 24 08 and 0x8(%rsp),%rax - 41b144: 49 89 c7 mov %rax,%r15 - 41b147: 49 81 ff ff ff 0f 00 cmp $0xfffff,%r15 - 41b14e: 4c 89 7c 24 10 mov %r15,0x10(%rsp) - 41b153: 77 0f ja 41b164 - 41b155: 48 c7 44 24 10 00 00 movq $0x100000,0x10(%rsp) - 41b15c: 10 00 - 41b15e: 41 bf 00 00 10 00 mov $0x100000,%r15d - 41b164: 48 3b 6c 24 10 cmp 0x10(%rsp),%rbp - 41b169: 0f 83 7e 01 00 00 jae 41b2ed - 41b16f: 48 8b 74 24 10 mov 0x10(%rsp),%rsi - 41b174: 45 31 c9 xor %r9d,%r9d - 41b177: 41 b8 ff ff ff ff mov $0xffffffff,%r8d - 41b17d: 31 ff xor %edi,%edi - 41b17f: b9 22 00 00 00 mov $0x22,%ecx - 41b184: ba 03 00 00 00 mov $0x3,%edx - 41b189: 44 88 5c 24 20 mov %r11b,0x20(%rsp) - 41b18e: 4c 89 54 24 18 mov %r10,0x18(%rsp) - 41b193: e8 58 4a 02 00 callq 43fbf0 <__mmap> - 41b198: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 41b19c: 49 89 c0 mov %rax,%r8 - 41b19f: 0f 84 48 01 00 00 je 41b2ed - 41b1a5: 83 0d 58 f6 2a 00 02 orl $0x2,0x2af658(%rip) # 6ca804 - 41b1ac: 48 85 c0 test %rax,%rax - 41b1af: 4c 8b 54 24 18 mov 0x18(%rsp),%r10 - 41b1b4: 44 0f b6 5c 24 20 movzbl 0x20(%rsp),%r11d - 41b1ba: 0f 84 2d 01 00 00 je 41b2ed - 41b1c0: 48 8b 44 24 10 mov 0x10(%rsp),%rax - 41b1c5: 4c 01 c0 add %r8,%rax - 41b1c8: 0f 94 c2 sete %dl - 41b1cb: e9 7a fe ff ff jmpq 41b04a - 41b1d0: 8b 15 2e f6 2a 00 mov 0x2af62e(%rip),%edx # 6ca804 - 41b1d6: f6 c2 02 test $0x2,%dl - 41b1d9: 0f 85 39 01 00 00 jne 41b318 - 41b1df: 4d 39 c2 cmp %r8,%r10 - 41b1e2: 76 09 jbe 41b1ed - 41b1e4: 45 84 db test %r11b,%r11b - 41b1e7: 0f 85 b9 01 00 00 jne 41b3a6 - 41b1ed: 4d 85 e4 test %r12,%r12 - 41b1f0: 74 10 je 41b202 - 41b1f2: 4c 89 c0 mov %r8,%rax - 41b1f5: 4c 29 d0 sub %r10,%rax - 41b1f8: 48 01 c6 add %rax,%rsi - 41b1fb: 48 89 35 7e fe 2a 00 mov %rsi,0x2afe7e(%rip) # 6cb080 - 41b202: 4c 89 c2 mov %r8,%rdx - 41b205: 83 e2 0f and $0xf,%edx - 41b208: 0f 84 62 01 00 00 je 41b370 - 41b20e: b8 10 00 00 00 mov $0x10,%eax - 41b213: 48 29 d0 sub %rdx,%rax - 41b216: 49 8d 3c 00 lea (%r8,%rax,1),%rdi - 41b21a: 48 89 7c 24 10 mov %rdi,0x10(%rsp) - 41b21f: 4c 01 e0 add %r12,%rax - 41b222: 48 8b 0c 24 mov (%rsp),%rcx - 41b226: 4c 8b 54 24 08 mov 0x8(%rsp),%r10 - 41b22b: 49 8d 14 07 lea (%r15,%rax,1),%rdx - 41b22f: 4c 01 c2 add %r8,%rdx - 41b232: 48 01 d1 add %rdx,%rcx - 41b235: 48 29 d0 sub %rdx,%rax - 41b238: 49 21 ca and %rcx,%r10 - 41b23b: 49 8d 0c 02 lea (%r10,%rax,1),%rcx - 41b23f: 48 85 c9 test %rcx,%rcx - 41b242: 49 89 cf mov %rcx,%r15 - 41b245: 0f 88 41 02 00 00 js 41b48c - 41b24b: 48 89 cf mov %rcx,%rdi - 41b24e: 48 89 0c 24 mov %rcx,(%rsp) - 41b252: ff 15 38 fe 2a 00 callq *0x2afe38(%rip) # 6cb090 <__morecore> - 41b258: 48 85 c0 test %rax,%rax - 41b25b: 48 8b 0c 24 mov (%rsp),%rcx - 41b25f: 0f 84 01 02 00 00 je 41b466 - 41b265: 48 8b 15 74 13 2b 00 mov 0x2b1374(%rip),%rdx # 6cc5e0 <__after_morecore_hook> - 41b26c: 48 8b 35 0d fe 2a 00 mov 0x2afe0d(%rip),%rsi # 6cb080 - 41b273: 48 85 d2 test %rdx,%rdx - 41b276: 4c 8b 44 24 10 mov 0x10(%rsp),%r8 - 41b27b: 0f 85 bb 01 00 00 jne 41b43c - 41b281: 4c 29 c0 sub %r8,%rax - 41b284: 48 01 ce add %rcx,%rsi - 41b287: 4c 89 05 ca f5 2a 00 mov %r8,0x2af5ca(%rip) # 6ca858 - 41b28e: 49 01 c7 add %rax,%r15 - 41b291: 4c 89 c2 mov %r8,%rdx - 41b294: 49 83 cf 01 or $0x1,%r15 - 41b298: 4d 85 e4 test %r12,%r12 - 41b29b: 4d 89 78 08 mov %r15,0x8(%r8) - 41b29f: 48 89 35 da fd 2a 00 mov %rsi,0x2afdda(%rip) # 6cb080 - 41b2a6: 0f 84 ab fa ff ff je 41ad57 - 41b2ac: 49 83 ec 20 sub $0x20,%r12 - 41b2b0: 49 83 e4 f0 and $0xfffffffffffffff0,%r12 - 41b2b4: 4c 89 e0 mov %r12,%rax - 41b2b7: 48 83 c8 01 or $0x1,%rax - 41b2bb: 49 83 fc 1f cmp $0x1f,%r12 - 41b2bf: 49 89 45 08 mov %rax,0x8(%r13) - 41b2c3: 4b c7 44 25 08 11 00 movq $0x11,0x8(%r13,%r12,1) - 41b2ca: 00 00 - 41b2cc: 4b c7 44 25 18 11 00 movq $0x11,0x18(%r13,%r12,1) - 41b2d3: 00 00 - 41b2d5: 0f 86 7c fa ff ff jbe 41ad57 - 41b2db: ba 01 00 00 00 mov $0x1,%edx - 41b2e0: 4c 89 ee mov %r13,%rsi - 41b2e3: bf 00 a8 6c 00 mov $0x6ca800,%edi - 41b2e8: e8 d3 e4 ff ff callq 4197c0 <_int_free> - 41b2ed: 48 8b 35 8c fd 2a 00 mov 0x2afd8c(%rip),%rsi # 6cb080 - 41b2f4: 48 8b 15 5d f5 2a 00 mov 0x2af55d(%rip),%rdx # 6ca858 - 41b2fb: e9 57 fa ff ff jmpq 41ad57 - 41b300: 4d 89 c6 mov %r8,%r14 - 41b303: 48 8b b3 80 08 00 00 mov 0x880(%rbx),%rsi - 41b30a: 48 8b 53 58 mov 0x58(%rbx),%rdx - 41b30e: e9 44 fa ff ff jmpq 41ad57 - 41b313: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41b318: 4c 89 c1 mov %r8,%rcx - 41b31b: 83 e1 0f and $0xf,%ecx - 41b31e: 0f 85 00 02 00 00 jne 41b524 - 41b324: 45 31 ff xor %r15d,%r15d - 41b327: 48 85 c0 test %rax,%rax - 41b32a: 0f 85 51 ff ff ff jne 41b281 - 41b330: 4c 89 04 24 mov %r8,(%rsp) - 41b334: 31 ff xor %edi,%edi - 41b336: ff 15 54 fd 2a 00 callq *0x2afd54(%rip) # 6cb090 <__morecore> - 41b33c: 4c 8b 04 24 mov (%rsp),%r8 - 41b340: 4c 89 44 24 10 mov %r8,0x10(%rsp) - 41b345: 48 85 c0 test %rax,%rax - 41b348: 48 8b 35 31 fd 2a 00 mov 0x2afd31(%rip),%rsi # 6cb080 - 41b34f: 74 a3 je 41b2f4 - 41b351: 4c 8b 44 24 10 mov 0x10(%rsp),%r8 - 41b356: 31 c9 xor %ecx,%ecx - 41b358: 45 31 ff xor %r15d,%r15d - 41b35b: e9 21 ff ff ff jmpq 41b281 - 41b360: 4c 89 05 89 f4 2a 00 mov %r8,0x2af489(%rip) # 6ca7f0 - 41b367: e9 ec fc ff ff jmpq 41b058 - 41b36c: 0f 1f 40 00 nopl 0x0(%rax) - 41b370: 4c 89 44 24 10 mov %r8,0x10(%rsp) - 41b375: 31 c0 xor %eax,%eax - 41b377: e9 a3 fe ff ff jmpq 41b21f - 41b37c: 0f 1f 40 00 nopl 0x0(%rax) - 41b380: 44 88 5c 24 20 mov %r11b,0x20(%rsp) - 41b385: 4c 89 44 24 18 mov %r8,0x18(%rsp) - 41b38a: 4c 89 54 24 10 mov %r10,0x10(%rsp) - 41b38f: ff d0 callq *%rax - 41b391: 4c 8b 54 24 10 mov 0x10(%rsp),%r10 - 41b396: 4c 8b 44 24 18 mov 0x18(%rsp),%r8 - 41b39b: 44 0f b6 5c 24 20 movzbl 0x20(%rsp),%r11d - 41b3a1: e9 9d fc ff ff jmpq 41b043 - 41b3a6: 83 ca 04 or $0x4,%edx - 41b3a9: 4c 8d 6c 24 30 lea 0x30(%rsp),%r13 - 41b3ae: 48 8d 74 24 40 lea 0x40(%rsp),%rsi - 41b3b3: 89 15 4b f4 2a 00 mov %edx,0x2af44b(%rip) # 6ca804 - 41b3b9: 31 c9 xor %ecx,%ecx - 41b3bb: ba 10 00 00 00 mov $0x10,%edx - 41b3c0: 4c 89 c7 mov %r8,%rdi - 41b3c3: c6 44 24 40 00 movb $0x0,0x40(%rsp) - 41b3c8: e8 e3 6a 03 00 callq 451eb0 <_itoa_word> - 41b3cd: 4c 39 e8 cmp %r13,%rax - 41b3d0: 49 89 c4 mov %rax,%r12 - 41b3d3: 76 25 jbe 41b3fa - 41b3d5: 48 89 c2 mov %rax,%rdx - 41b3d8: 48 89 c7 mov %rax,%rdi - 41b3db: be 30 00 00 00 mov $0x30,%esi - 41b3e0: 4c 29 ea sub %r13,%rdx - 41b3e3: 4c 8d 78 ff lea -0x1(%rax),%r15 - 41b3e7: 48 29 d7 sub %rdx,%rdi - 41b3ea: e8 61 4f fe ff callq 400350 <__rela_iplt_end+0x88> - 41b3ef: 48 8d 44 24 2f lea 0x2f(%rsp),%rax - 41b3f4: 4c 29 f8 sub %r15,%rax - 41b3f7: 49 01 c4 add %rax,%r12 - 41b3fa: 48 8b 05 bf 1e 2b 00 mov 0x2b1ebf(%rip),%rax # 6cd2c0 <__libc_argv> - 41b401: ba 38 20 4a 00 mov $0x4a2038,%edx - 41b406: be a8 23 4a 00 mov $0x4a23a8,%esi - 41b40b: 4d 89 e0 mov %r12,%r8 - 41b40e: b9 48 27 4a 00 mov $0x4a2748,%ecx - 41b413: bf 02 00 00 00 mov $0x2,%edi - 41b418: 48 8b 00 mov (%rax),%rax - 41b41b: 48 85 c0 test %rax,%rax - 41b41e: 48 0f 45 d0 cmovne %rax,%rdx - 41b422: 31 c0 xor %eax,%eax - 41b424: e8 97 61 ff ff callq 4115c0 <__libc_message> - 41b429: 48 8b 35 50 fc 2a 00 mov 0x2afc50(%rip),%rsi # 6cb080 - 41b430: 48 8b 15 21 f4 2a 00 mov 0x2af421(%rip),%rdx # 6ca858 - 41b437: e9 1b f9 ff ff jmpq 41ad57 - 41b43c: 48 89 44 24 10 mov %rax,0x10(%rsp) - 41b441: 4c 89 44 24 08 mov %r8,0x8(%rsp) - 41b446: 48 89 0c 24 mov %rcx,(%rsp) - 41b44a: ff d2 callq *%rdx - 41b44c: 48 8b 35 2d fc 2a 00 mov 0x2afc2d(%rip),%rsi # 6cb080 - 41b453: 48 8b 0c 24 mov (%rsp),%rcx - 41b457: 4c 8b 44 24 08 mov 0x8(%rsp),%r8 - 41b45c: 48 8b 44 24 10 mov 0x10(%rsp),%rax - 41b461: e9 1b fe ff ff jmpq 41b281 - 41b466: 31 ff xor %edi,%edi - 41b468: ff 15 22 fc 2a 00 callq *0x2afc22(%rip) # 6cb090 <__morecore> - 41b46e: e9 d2 fe ff ff jmpq 41b345 - 41b473: b9 a8 2e 4a 00 mov $0x4a2ea8,%ecx - 41b478: ba 5d 09 00 00 mov $0x95d,%edx - 41b47d: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 41b482: bf 08 27 4a 00 mov $0x4a2708,%edi - 41b487: e8 94 b9 ff ff callq 416e20 <__malloc_assert> - 41b48c: b9 a8 2e 4a 00 mov $0x4a2ea8,%ecx - 41b491: ba 39 0a 00 00 mov $0xa39,%edx - 41b496: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 41b49b: bf 32 21 4a 00 mov $0x4a2132,%edi - 41b4a0: e8 7b b9 ff ff callq 416e20 <__malloc_assert> - 41b4a5: f6 05 58 f3 2a 00 02 testb $0x2,0x2af358(%rip) # 6ca804 - 41b4ac: 0f 84 83 fc ff ff je 41b135 - 41b4b2: e9 90 fc ff ff jmpq 41b147 - 41b4b7: 45 31 c9 xor %r9d,%r9d - 41b4ba: 41 83 c8 ff or $0xffffffff,%r8d - 41b4be: 31 ff xor %edi,%edi - 41b4c0: b9 22 00 00 00 mov $0x22,%ecx - 41b4c5: ba 03 00 00 00 mov $0x3,%edx - 41b4ca: 4c 89 e6 mov %r12,%rsi - 41b4cd: e8 1e 47 02 00 callq 43fbf0 <__mmap> - 41b4d2: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 41b4d6: 0f 85 72 fa ff ff jne 41af4e - 41b4dc: e9 38 f9 ff ff jmpq 41ae19 - 41b4e1: b9 a8 2e 4a 00 mov $0x4a2ea8,%ecx - 41b4e6: ba 24 09 00 00 mov $0x924,%edx - 41b4eb: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 41b4f0: bf 20 26 4a 00 mov $0x4a2620,%edi - 41b4f5: e8 26 b9 ff ff callq 416e20 <__malloc_assert> - 41b4fa: 45 31 c9 xor %r9d,%r9d - 41b4fd: 41 83 c8 ff or $0xffffffff,%r8d - 41b501: 31 ff xor %edi,%edi - 41b503: b9 22 00 00 00 mov $0x22,%ecx - 41b508: ba 03 00 00 00 mov $0x3,%edx - 41b50d: 48 89 c6 mov %rax,%rsi - 41b510: e8 db 46 02 00 callq 43fbf0 <__mmap> - 41b515: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 41b519: 0f 85 2f fa ff ff jne 41af4e - 41b51f: e9 e0 fb ff ff jmpq 41b104 - 41b524: b9 a8 2e 4a 00 mov $0x4a2ea8,%ecx - 41b529: ba 59 0a 00 00 mov $0xa59,%edx - 41b52e: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 41b533: bf 70 27 4a 00 mov $0x4a2770,%edi - 41b538: e8 e3 b8 ff ff callq 416e20 <__malloc_assert> - 41b53d: 0f 1f 00 nopl (%rax) - -000000000041b540 <_int_malloc>: - 41b540: 48 83 fe bf cmp $0xffffffffffffffbf,%rsi - 41b544: 0f 87 63 08 00 00 ja 41bdad <_int_malloc+0x86d> - 41b54a: 48 89 f0 mov %rsi,%rax - 41b54d: 41 57 push %r15 - 41b54f: 41 56 push %r14 - 41b551: 48 83 c0 17 add $0x17,%rax - 41b555: 41 55 push %r13 - 41b557: 41 54 push %r12 - 41b559: 55 push %rbp - 41b55a: 53 push %rbx - 41b55b: 48 89 c5 mov %rax,%rbp - 41b55e: 48 83 e5 f0 and $0xfffffffffffffff0,%rbp - 41b562: 48 89 fb mov %rdi,%rbx - 41b565: 48 81 ec 98 00 00 00 sub $0x98,%rsp - 41b56c: 48 83 f8 20 cmp $0x20,%rax - 41b570: b8 20 00 00 00 mov $0x20,%eax - 41b575: 48 0f 42 e8 cmovb %rax,%rbp - 41b579: 48 85 ff test %rdi,%rdi - 41b57c: 48 89 74 24 08 mov %rsi,0x8(%rsp) - 41b581: 0f 84 3a 08 00 00 je 41bdc1 <_int_malloc+0x881> - 41b587: 48 3b 2d aa 10 2b 00 cmp 0x2b10aa(%rip),%rbp # 6cc638 - 41b58e: 77 70 ja 41b600 <_int_malloc+0xc0> - 41b590: 89 ef mov %ebp,%edi - 41b592: c1 ef 04 shr $0x4,%edi - 41b595: 8d 47 fe lea -0x2(%rdi),%eax - 41b598: 48 8b 4c c3 08 mov 0x8(%rbx,%rax,8),%rcx - 41b59d: 48 8d 34 c3 lea (%rbx,%rax,8),%rsi - 41b5a1: 48 89 c7 mov %rax,%rdi - 41b5a4: 48 8d 56 08 lea 0x8(%rsi),%rdx - 41b5a8: 48 85 c9 test %rcx,%rcx - 41b5ab: 74 53 je 41b600 <_int_malloc+0xc0> - 41b5ad: 4c 8b 41 10 mov 0x10(%rcx),%r8 - 41b5b1: 48 89 c8 mov %rcx,%rax - 41b5b4: 64 83 3c 25 18 00 00 cmpl $0x0,%fs:0x18 - 41b5bb: 00 00 - 41b5bd: 74 01 je 41b5c0 <_int_malloc+0x80> - 41b5bf: f0 4c 0f b1 46 08 lock cmpxchg %r8,0x8(%rsi) - 41b5c5: 48 39 c8 cmp %rcx,%rax - 41b5c8: 49 89 c7 mov %rax,%r15 - 41b5cb: 75 2e jne 41b5fb <_int_malloc+0xbb> - 41b5cd: e9 64 02 00 00 jmpq 41b836 <_int_malloc+0x2f6> - 41b5d2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 41b5d8: 49 8b 4f 10 mov 0x10(%r15),%rcx - 41b5dc: 4c 89 f8 mov %r15,%rax - 41b5df: 64 83 3c 25 18 00 00 cmpl $0x0,%fs:0x18 - 41b5e6: 00 00 - 41b5e8: 74 01 je 41b5eb <_int_malloc+0xab> - 41b5ea: f0 48 0f b1 0a lock cmpxchg %rcx,(%rdx) - 41b5ef: 4c 39 f8 cmp %r15,%rax - 41b5f2: 0f 84 3e 02 00 00 je 41b836 <_int_malloc+0x2f6> - 41b5f8: 49 89 c7 mov %rax,%r15 - 41b5fb: 4d 85 ff test %r15,%r15 - 41b5fe: 75 d8 jne 41b5d8 <_int_malloc+0x98> - 41b600: 48 81 fd ff 03 00 00 cmp $0x3ff,%rbp - 41b607: 77 5a ja 41b663 <_int_malloc+0x123> - 41b609: 89 e8 mov %ebp,%eax - 41b60b: c1 e8 04 shr $0x4,%eax - 41b60e: 89 04 24 mov %eax,(%rsp) - 41b611: 8d 44 00 fe lea -0x2(%rax,%rax,1),%eax - 41b615: 48 8d 44 c3 60 lea 0x60(%rbx,%rax,8),%rax - 41b61a: 48 8d 48 08 lea 0x8(%rax),%rcx - 41b61e: 4c 8b 79 08 mov 0x8(%rcx),%r15 - 41b622: 48 83 e8 08 sub $0x8,%rax - 41b626: 4c 39 f8 cmp %r15,%rax - 41b629: 74 70 je 41b69b <_int_malloc+0x15b> - 41b62b: 4d 85 ff test %r15,%r15 - 41b62e: 74 63 je 41b693 <_int_malloc+0x153> - 41b630: 49 8b 57 18 mov 0x18(%r15),%rdx - 41b634: 4c 3b 7a 10 cmp 0x10(%rdx),%r15 - 41b638: 0f 85 13 09 00 00 jne 41bf51 <_int_malloc+0xa11> - 41b63e: 49 83 4c 2f 08 01 orq $0x1,0x8(%r15,%rbp,1) - 41b644: 48 81 fb 00 a8 6c 00 cmp $0x6ca800,%rbx - 41b64b: 48 89 51 08 mov %rdx,0x8(%rcx) - 41b64f: 48 89 42 10 mov %rax,0x10(%rdx) - 41b653: 0f 84 ef 01 00 00 je 41b848 <_int_malloc+0x308> - 41b659: 49 83 4f 08 04 orq $0x4,0x8(%r15) - 41b65e: e9 e5 01 00 00 jmpq 41b848 <_int_malloc+0x308> - 41b663: 49 89 ec mov %rbp,%r12 - 41b666: 49 c1 ec 06 shr $0x6,%r12 - 41b66a: 49 83 fc 30 cmp $0x30,%r12 - 41b66e: 0f 86 0c 07 00 00 jbe 41bd80 <_int_malloc+0x840> - 41b674: 49 89 ec mov %rbp,%r12 - 41b677: 49 c1 ec 09 shr $0x9,%r12 - 41b67b: 49 83 fc 14 cmp $0x14,%r12 - 41b67f: 0f 87 7b 07 00 00 ja 41be00 <_int_malloc+0x8c0> - 41b685: 41 8d 44 24 5b lea 0x5b(%r12),%eax - 41b68a: 89 04 24 mov %eax,(%rsp) - 41b68d: f6 43 04 01 testb $0x1,0x4(%rbx) - 41b691: 75 08 jne 41b69b <_int_malloc+0x15b> - 41b693: 48 89 df mov %rbx,%rdi - 41b696: e8 95 c7 ff ff callq 417e30 - 41b69b: 48 89 e9 mov %rbp,%rcx - 41b69e: 48 89 e8 mov %rbp,%rax - 41b6a1: 48 89 ef mov %rbp,%rdi - 41b6a4: 48 c1 e9 0c shr $0xc,%rcx - 41b6a8: 48 c1 e8 06 shr $0x6,%rax - 41b6ac: 48 c1 ef 09 shr $0x9,%rdi - 41b6b0: 48 89 4c 24 48 mov %rcx,0x48(%rsp) - 41b6b5: 83 c1 6e add $0x6e,%ecx - 41b6b8: 48 89 44 24 30 mov %rax,0x30(%rsp) - 41b6bd: 89 4c 24 54 mov %ecx,0x54(%rsp) - 41b6c1: 48 89 e9 mov %rbp,%rcx - 41b6c4: 83 c0 30 add $0x30,%eax - 41b6c7: 48 c1 e9 0f shr $0xf,%rcx - 41b6cb: 48 89 7c 24 40 mov %rdi,0x40(%rsp) - 41b6d0: 89 44 24 3c mov %eax,0x3c(%rsp) - 41b6d4: 83 c7 5b add $0x5b,%edi - 41b6d7: 48 89 4c 24 58 mov %rcx,0x58(%rsp) - 41b6dc: 89 e8 mov %ebp,%eax - 41b6de: 83 c1 77 add $0x77,%ecx - 41b6e1: c1 e8 04 shr $0x4,%eax - 41b6e4: 89 7c 24 50 mov %edi,0x50(%rsp) - 41b6e8: 89 4c 24 68 mov %ecx,0x68(%rsp) - 41b6ec: 48 8d 7c 24 70 lea 0x70(%rsp),%rdi - 41b6f1: 48 89 e9 mov %rbp,%rcx - 41b6f4: 48 c1 e9 12 shr $0x12,%rcx - 41b6f8: 89 44 24 38 mov %eax,0x38(%rsp) - 41b6fc: b8 01 00 00 00 mov $0x1,%eax - 41b701: 48 89 4c 24 60 mov %rcx,0x60(%rsp) - 41b706: 48 29 f8 sub %rdi,%rax - 41b709: 83 c1 7c add $0x7c,%ecx - 41b70c: 4c 8d 63 58 lea 0x58(%rbx),%r12 - 41b710: 89 4c 24 6c mov %ecx,0x6c(%rsp) - 41b714: 48 89 44 24 28 mov %rax,0x28(%rsp) - 41b719: 41 bf 10 27 00 00 mov $0x2710,%r15d - 41b71f: eb 4e jmp 41b76f <_int_malloc+0x22f> - 41b721: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 41b728: 89 f1 mov %esi,%ecx - 41b72a: c1 e9 04 shr $0x4,%ecx - 41b72d: 8d 44 09 fe lea -0x2(%rcx,%rcx,1),%eax - 41b731: 48 98 cltq - 41b733: 48 8d 44 c3 60 lea 0x60(%rbx,%rax,8),%rax - 41b738: 48 8b 78 08 mov 0x8(%rax),%rdi - 41b73c: 4c 8d 40 f8 lea -0x8(%rax),%r8 - 41b740: 89 c8 mov %ecx,%eax - 41b742: ba 01 00 00 00 mov $0x1,%edx - 41b747: c1 f8 05 sar $0x5,%eax - 41b74a: d3 e2 shl %cl,%edx - 41b74c: 48 98 cltq - 41b74e: 09 94 83 58 08 00 00 or %edx,0x858(%rbx,%rax,4) - 41b755: 41 83 ef 01 sub $0x1,%r15d - 41b759: 4d 89 45 18 mov %r8,0x18(%r13) - 41b75d: 49 89 7d 10 mov %rdi,0x10(%r13) - 41b761: 4c 89 6f 18 mov %r13,0x18(%rdi) - 41b765: 4d 89 68 10 mov %r13,0x10(%r8) - 41b769: 0f 84 94 03 00 00 je 41bb03 <_int_malloc+0x5c3> - 41b76f: 4c 8b 6b 70 mov 0x70(%rbx),%r13 - 41b773: 4d 39 e5 cmp %r12,%r13 - 41b776: 0f 84 87 03 00 00 je 41bb03 <_int_malloc+0x5c3> - 41b77c: 49 8b 75 08 mov 0x8(%r13),%rsi - 41b780: 4d 8b 75 18 mov 0x18(%r13),%r14 - 41b784: 48 83 fe 10 cmp $0x10,%rsi - 41b788: 0f 86 52 01 00 00 jbe 41b8e0 <_int_malloc+0x3a0> - 41b78e: 48 3b b3 80 08 00 00 cmp 0x880(%rbx),%rsi - 41b795: 0f 87 45 01 00 00 ja 41b8e0 <_int_malloc+0x3a0> - 41b79b: 48 83 e6 f8 and $0xfffffffffffffff8,%rsi - 41b79f: 48 81 fd ff 03 00 00 cmp $0x3ff,%rbp - 41b7a6: 77 09 ja 41b7b1 <_int_malloc+0x271> - 41b7a8: 4d 39 e6 cmp %r12,%r14 - 41b7ab: 0f 84 8f 01 00 00 je 41b940 <_int_malloc+0x400> - 41b7b1: 48 39 f5 cmp %rsi,%rbp - 41b7b4: 4c 89 73 70 mov %r14,0x70(%rbx) - 41b7b8: 4d 89 66 10 mov %r12,0x10(%r14) - 41b7bc: 0f 84 a6 04 00 00 je 41bc68 <_int_malloc+0x728> - 41b7c2: 48 81 fe ff 03 00 00 cmp $0x3ff,%rsi - 41b7c9: 0f 86 59 ff ff ff jbe 41b728 <_int_malloc+0x1e8> - 41b7cf: 48 89 f0 mov %rsi,%rax - 41b7d2: 48 c1 e8 06 shr $0x6,%rax - 41b7d6: 48 83 f8 30 cmp $0x30,%rax - 41b7da: 0f 87 90 00 00 00 ja 41b870 <_int_malloc+0x330> - 41b7e0: 8d 48 30 lea 0x30(%rax),%ecx - 41b7e3: 8d 44 00 5e lea 0x5e(%rax,%rax,1),%eax - 41b7e7: 48 98 cltq - 41b7e9: 48 8d 44 c3 60 lea 0x60(%rbx,%rax,8),%rax - 41b7ee: 48 8d 78 f8 lea -0x8(%rax),%rdi - 41b7f2: 48 8d 50 08 lea 0x8(%rax),%rdx - 41b7f6: 48 8b 40 08 mov 0x8(%rax),%rax - 41b7fa: 48 39 c7 cmp %rax,%rdi - 41b7fd: 0f 84 e5 01 00 00 je 41b9e8 <_int_malloc+0x4a8> - 41b803: 4c 8b 42 08 mov 0x8(%rdx),%r8 - 41b807: 48 83 ce 01 or $0x1,%rsi - 41b80b: 49 8b 50 08 mov 0x8(%r8),%rdx - 41b80f: f6 c2 04 test $0x4,%dl - 41b812: 0f 85 f1 09 00 00 jne 41c209 <_int_malloc+0xcc9> - 41b818: 48 39 d6 cmp %rdx,%rsi - 41b81b: 73 73 jae 41b890 <_int_malloc+0x350> - 41b81d: 48 8b 50 28 mov 0x28(%rax),%rdx - 41b821: 49 89 45 20 mov %rax,0x20(%r13) - 41b825: 49 89 55 28 mov %rdx,0x28(%r13) - 41b829: 4c 89 6a 20 mov %r13,0x20(%rdx) - 41b82d: 4c 89 68 28 mov %r13,0x28(%rax) - 41b831: e9 0a ff ff ff jmpq 41b740 <_int_malloc+0x200> - 41b836: 41 8b 47 08 mov 0x8(%r15),%eax - 41b83a: c1 e8 04 shr $0x4,%eax - 41b83d: 83 e8 02 sub $0x2,%eax - 41b840: 39 c7 cmp %eax,%edi - 41b842: 0f 85 26 06 00 00 jne 41be6e <_int_malloc+0x92e> - 41b848: 8b 05 e6 0d 2b 00 mov 0x2b0de6(%rip),%eax # 6cc634 - 41b84e: 49 8d 4f 10 lea 0x10(%r15),%rcx - 41b852: 85 c0 test %eax,%eax - 41b854: 0f 85 71 01 00 00 jne 41b9cb <_int_malloc+0x48b> - 41b85a: 48 81 c4 98 00 00 00 add $0x98,%rsp - 41b861: 48 89 c8 mov %rcx,%rax - 41b864: 5b pop %rbx - 41b865: 5d pop %rbp - 41b866: 41 5c pop %r12 - 41b868: 41 5d pop %r13 - 41b86a: 41 5e pop %r14 - 41b86c: 41 5f pop %r15 - 41b86e: c3 retq - 41b86f: 90 nop - 41b870: 48 89 f0 mov %rsi,%rax - 41b873: 48 c1 e8 09 shr $0x9,%rax - 41b877: 48 83 f8 14 cmp $0x14,%rax - 41b87b: 0f 87 97 00 00 00 ja 41b918 <_int_malloc+0x3d8> - 41b881: 8d 48 5b lea 0x5b(%rax),%ecx - 41b884: 8d 84 00 b4 00 00 00 lea 0xb4(%rax,%rax,1),%eax - 41b88b: e9 57 ff ff ff jmpq 41b7e7 <_int_malloc+0x2a7> - 41b890: 48 8b 50 08 mov 0x8(%rax),%rdx - 41b894: f6 c2 04 test $0x4,%dl - 41b897: 74 18 je 41b8b1 <_int_malloc+0x371> - 41b899: e9 84 09 00 00 jmpq 41c222 <_int_malloc+0xce2> - 41b89e: 66 90 xchg %ax,%ax - 41b8a0: 48 8b 40 20 mov 0x20(%rax),%rax - 41b8a4: 48 8b 50 08 mov 0x8(%rax),%rdx - 41b8a8: f6 c2 04 test $0x4,%dl - 41b8ab: 0f 85 87 06 00 00 jne 41bf38 <_int_malloc+0x9f8> - 41b8b1: 48 39 d6 cmp %rdx,%rsi - 41b8b4: 72 ea jb 41b8a0 <_int_malloc+0x360> - 41b8b6: 0f 84 64 01 00 00 je 41ba20 <_int_malloc+0x4e0> - 41b8bc: 48 8b 50 28 mov 0x28(%rax),%rdx - 41b8c0: 49 89 45 20 mov %rax,0x20(%r13) - 41b8c4: 48 89 c7 mov %rax,%rdi - 41b8c7: 49 89 55 28 mov %rdx,0x28(%r13) - 41b8cb: 4c 89 68 28 mov %r13,0x28(%rax) - 41b8cf: 49 8b 55 28 mov 0x28(%r13),%rdx - 41b8d3: 4c 89 6a 20 mov %r13,0x20(%rdx) - 41b8d7: 4c 8b 47 18 mov 0x18(%rdi),%r8 - 41b8db: e9 60 fe ff ff jmpq 41b740 <_int_malloc+0x200> - 41b8e0: 44 8b 0d 89 ee 2a 00 mov 0x2aee89(%rip),%r9d # 6ca770 - 41b8e7: 83 4b 04 04 orl $0x4,0x4(%rbx) - 41b8eb: 44 89 c8 mov %r9d,%eax - 41b8ee: 83 e0 05 and $0x5,%eax - 41b8f1: 83 f8 05 cmp $0x5,%eax - 41b8f4: 0f 84 93 04 00 00 je 41bd8d <_int_malloc+0x84d> - 41b8fa: 41 f6 c1 01 test $0x1,%r9b - 41b8fe: 0f 85 2c 01 00 00 jne 41ba30 <_int_malloc+0x4f0> - 41b904: 41 83 e1 02 and $0x2,%r9d - 41b908: 0f 84 8d fe ff ff je 41b79b <_int_malloc+0x25b> - 41b90e: e9 84 05 00 00 jmpq 41be97 <_int_malloc+0x957> - 41b913: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41b918: 48 89 f0 mov %rsi,%rax - 41b91b: 48 c1 e8 0c shr $0xc,%rax - 41b91f: 48 83 f8 0a cmp $0xa,%rax - 41b923: 0f 87 d7 00 00 00 ja 41ba00 <_int_malloc+0x4c0> - 41b929: 8d 48 6e lea 0x6e(%rax),%ecx - 41b92c: 8d 84 00 da 00 00 00 lea 0xda(%rax,%rax,1),%eax - 41b933: e9 af fe ff ff jmpq 41b7e7 <_int_malloc+0x2a7> - 41b938: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 41b93f: 00 - 41b940: 4c 3b 6b 60 cmp 0x60(%rbx),%r13 - 41b944: 0f 85 67 fe ff ff jne 41b7b1 <_int_malloc+0x271> - 41b94a: 48 8d 45 20 lea 0x20(%rbp),%rax - 41b94e: 48 39 c6 cmp %rax,%rsi - 41b951: 0f 86 5a fe ff ff jbe 41b7b1 <_int_malloc+0x271> - 41b957: 48 89 f2 mov %rsi,%rdx - 41b95a: 49 8d 44 2d 00 lea 0x0(%r13,%rbp,1),%rax - 41b95f: 48 29 ea sub %rbp,%rdx - 41b962: 48 81 fa ff 03 00 00 cmp $0x3ff,%rdx - 41b969: 48 89 43 68 mov %rax,0x68(%rbx) - 41b96d: 48 89 43 70 mov %rax,0x70(%rbx) - 41b971: 48 89 43 60 mov %rax,0x60(%rbx) - 41b975: 4c 89 60 10 mov %r12,0x10(%rax) - 41b979: 4c 89 60 18 mov %r12,0x18(%rax) - 41b97d: 76 10 jbe 41b98f <_int_malloc+0x44f> - 41b97f: 48 c7 40 20 00 00 00 movq $0x0,0x20(%rax) - 41b986: 00 - 41b987: 48 c7 40 28 00 00 00 movq $0x0,0x28(%rax) - 41b98e: 00 - 41b98f: 31 c9 xor %ecx,%ecx - 41b991: 48 81 fb 00 a8 6c 00 cmp $0x6ca800,%rbx - 41b998: 0f 95 c1 setne %cl - 41b99b: 48 83 cd 01 or $0x1,%rbp - 41b99f: 48 c1 e1 02 shl $0x2,%rcx - 41b9a3: 48 09 e9 or %rbp,%rcx - 41b9a6: 49 89 4d 08 mov %rcx,0x8(%r13) - 41b9aa: 48 89 d1 mov %rdx,%rcx - 41b9ad: 48 83 c9 01 or $0x1,%rcx - 41b9b1: 48 89 48 08 mov %rcx,0x8(%rax) - 41b9b5: 48 89 14 10 mov %rdx,(%rax,%rdx,1) - 41b9b9: 49 8d 4d 10 lea 0x10(%r13),%rcx - 41b9bd: 8b 05 71 0c 2b 00 mov 0x2b0c71(%rip),%eax # 6cc634 - 41b9c3: 85 c0 test %eax,%eax - 41b9c5: 0f 84 8f fe ff ff je 41b85a <_int_malloc+0x31a> - 41b9cb: 48 8b 54 24 08 mov 0x8(%rsp),%rdx - 41b9d0: 34 ff xor $0xff,%al - 41b9d2: 48 89 cf mov %rcx,%rdi - 41b9d5: 89 c6 mov %eax,%esi - 41b9d7: e8 74 49 fe ff callq 400350 <__rela_iplt_end+0x88> - 41b9dc: 48 89 c1 mov %rax,%rcx - 41b9df: e9 76 fe ff ff jmpq 41b85a <_int_malloc+0x31a> - 41b9e4: 0f 1f 40 00 nopl 0x0(%rax) - 41b9e8: 4d 89 6d 28 mov %r13,0x28(%r13) - 41b9ec: 4d 89 6d 20 mov %r13,0x20(%r13) - 41b9f0: 49 89 f8 mov %rdi,%r8 - 41b9f3: e9 48 fd ff ff jmpq 41b740 <_int_malloc+0x200> - 41b9f8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 41b9ff: 00 - 41ba00: 48 89 f0 mov %rsi,%rax - 41ba03: 48 c1 e8 0f shr $0xf,%rax - 41ba07: 48 83 f8 04 cmp $0x4,%rax - 41ba0b: 0f 87 d2 00 00 00 ja 41bae3 <_int_malloc+0x5a3> - 41ba11: 8d 48 77 lea 0x77(%rax),%ecx - 41ba14: 8d 84 00 ec 00 00 00 lea 0xec(%rax,%rax,1),%eax - 41ba1b: e9 c7 fd ff ff jmpq 41b7e7 <_int_malloc+0x2a7> - 41ba20: 48 8b 78 10 mov 0x10(%rax),%rdi - 41ba24: e9 ae fe ff ff jmpq 41b8d7 <_int_malloc+0x397> - 41ba29: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 41ba30: 48 8d b4 24 80 00 00 lea 0x80(%rsp),%rsi - 41ba37: 00 - 41ba38: 49 8d 7d 10 lea 0x10(%r13),%rdi - 41ba3c: 31 c9 xor %ecx,%ecx - 41ba3e: ba 10 00 00 00 mov $0x10,%edx - 41ba43: 44 89 4c 24 10 mov %r9d,0x10(%rsp) - 41ba48: c6 84 24 80 00 00 00 movb $0x0,0x80(%rsp) - 41ba4f: 00 - 41ba50: e8 5b 64 03 00 callq 451eb0 <_itoa_word> - 41ba55: 49 89 c0 mov %rax,%r8 - 41ba58: 48 8d 44 24 70 lea 0x70(%rsp),%rax - 41ba5d: 44 8b 4c 24 10 mov 0x10(%rsp),%r9d - 41ba62: 49 39 c0 cmp %rax,%r8 - 41ba65: 76 46 jbe 41baad <_int_malloc+0x56d> - 41ba67: 48 8b 44 24 28 mov 0x28(%rsp),%rax - 41ba6c: 49 8d 48 ff lea -0x1(%r8),%rcx - 41ba70: 4c 89 c7 mov %r8,%rdi - 41ba73: be 30 00 00 00 mov $0x30,%esi - 41ba78: 44 89 4c 24 24 mov %r9d,0x24(%rsp) - 41ba7d: 4c 89 44 24 10 mov %r8,0x10(%rsp) - 41ba82: 48 89 4c 24 18 mov %rcx,0x18(%rsp) - 41ba87: 48 8d 14 08 lea (%rax,%rcx,1),%rdx - 41ba8b: 48 29 d7 sub %rdx,%rdi - 41ba8e: e8 bd 48 fe ff callq 400350 <__rela_iplt_end+0x88> - 41ba93: 48 8b 4c 24 18 mov 0x18(%rsp),%rcx - 41ba98: 48 8d 44 24 6f lea 0x6f(%rsp),%rax - 41ba9d: 4c 8b 44 24 10 mov 0x10(%rsp),%r8 - 41baa2: 44 8b 4c 24 24 mov 0x24(%rsp),%r9d - 41baa7: 48 29 c8 sub %rcx,%rax - 41baaa: 49 01 c0 add %rax,%r8 - 41baad: 48 8b 05 0c 18 2b 00 mov 0x2b180c(%rip),%rax # 6cd2c0 <__libc_argv> - 41bab4: 44 89 cf mov %r9d,%edi - 41bab7: ba 38 20 4a 00 mov $0x4a2038,%edx - 41babc: be a8 23 4a 00 mov $0x4a23a8,%esi - 41bac1: b9 42 21 4a 00 mov $0x4a2142,%ecx - 41bac6: 48 8b 00 mov (%rax),%rax - 41bac9: 48 85 c0 test %rax,%rax - 41bacc: 48 0f 45 d0 cmovne %rax,%rdx - 41bad0: 83 e7 02 and $0x2,%edi - 41bad3: 31 c0 xor %eax,%eax - 41bad5: e8 e6 5a ff ff callq 4115c0 <__libc_message> - 41bada: 49 8b 75 08 mov 0x8(%r13),%rsi - 41bade: e9 b8 fc ff ff jmpq 41b79b <_int_malloc+0x25b> - 41bae3: 48 89 f0 mov %rsi,%rax - 41bae6: 48 c1 e8 12 shr $0x12,%rax - 41baea: 48 83 f8 02 cmp $0x2,%rax - 41baee: 0f 87 9f 01 00 00 ja 41bc93 <_int_malloc+0x753> - 41baf4: 8d 48 7c lea 0x7c(%rax),%ecx - 41baf7: 8d 84 00 f6 00 00 00 lea 0xf6(%rax,%rax,1),%eax - 41bafe: e9 e4 fc ff ff jmpq 41b7e7 <_int_malloc+0x2a7> - 41bb03: 48 81 fd ff 03 00 00 cmp $0x3ff,%rbp - 41bb0a: 0f 87 92 01 00 00 ja 41bca2 <_int_malloc+0x762> - 41bb10: 8b 04 24 mov (%rsp),%eax - 41bb13: 8d 48 01 lea 0x1(%rax),%ecx - 41bb16: 01 c0 add %eax,%eax - 41bb18: 48 8d 54 c3 58 lea 0x58(%rbx,%rax,8),%rdx - 41bb1d: 89 cf mov %ecx,%edi - 41bb1f: c1 ef 05 shr $0x5,%edi - 41bb22: 89 f8 mov %edi,%eax - 41bb24: 8b b4 83 58 08 00 00 mov 0x858(%rbx,%rax,4),%esi - 41bb2b: b8 01 00 00 00 mov $0x1,%eax - 41bb30: d3 e0 shl %cl,%eax - 41bb32: 39 f0 cmp %esi,%eax - 41bb34: 77 40 ja 41bb76 <_int_malloc+0x636> - 41bb36: 85 c0 test %eax,%eax - 41bb38: 75 12 jne 41bb4c <_int_malloc+0x60c> - 41bb3a: eb 3a jmp 41bb76 <_int_malloc+0x636> - 41bb3c: 0f 1f 40 00 nopl 0x0(%rax) - 41bb40: 48 83 c2 10 add $0x10,%rdx - 41bb44: 01 c0 add %eax,%eax - 41bb46: 0f 84 dc 05 00 00 je 41c128 <_int_malloc+0xbe8> - 41bb4c: 85 f0 test %esi,%eax - 41bb4e: 74 f0 je 41bb40 <_int_malloc+0x600> - 41bb50: 4c 8b 7a 18 mov 0x18(%rdx),%r15 - 41bb54: 4c 39 fa cmp %r15,%rdx - 41bb57: 0f 85 4f 03 00 00 jne 41beac <_int_malloc+0x96c> - 41bb5d: 89 c1 mov %eax,%ecx - 41bb5f: 01 c0 add %eax,%eax - 41bb61: 48 83 c2 10 add $0x10,%rdx - 41bb65: f7 d1 not %ecx - 41bb67: 21 ce and %ecx,%esi - 41bb69: 89 f9 mov %edi,%ecx - 41bb6b: 39 f0 cmp %esi,%eax - 41bb6d: 89 b4 8b 58 08 00 00 mov %esi,0x858(%rbx,%rcx,4) - 41bb74: 76 c0 jbe 41bb36 <_int_malloc+0x5f6> - 41bb76: 8d 47 01 lea 0x1(%rdi),%eax - 41bb79: 83 f8 03 cmp $0x3,%eax - 41bb7c: 77 3d ja 41bbbb <_int_malloc+0x67b> - 41bb7e: 89 c2 mov %eax,%edx - 41bb80: 8b b4 93 58 08 00 00 mov 0x858(%rbx,%rdx,4),%esi - 41bb87: 85 f6 test %esi,%esi - 41bb89: 0f 85 9c 02 00 00 jne 41be2b <_int_malloc+0x8eb> - 41bb8f: 8d 47 02 lea 0x2(%rdi),%eax - 41bb92: 83 f8 04 cmp $0x4,%eax - 41bb95: 74 24 je 41bbbb <_int_malloc+0x67b> - 41bb97: 89 c2 mov %eax,%edx - 41bb99: 8b b4 93 58 08 00 00 mov 0x858(%rbx,%rdx,4),%esi - 41bba0: 85 f6 test %esi,%esi - 41bba2: 0f 85 83 02 00 00 jne 41be2b <_int_malloc+0x8eb> - 41bba8: 83 ff 01 cmp $0x1,%edi - 41bbab: 74 0e je 41bbbb <_int_malloc+0x67b> - 41bbad: 8b b3 64 08 00 00 mov 0x864(%rbx),%esi - 41bbb3: 85 f6 test %esi,%esi - 41bbb5: 0f 85 e5 02 00 00 jne 41bea0 <_int_malloc+0x960> - 41bbbb: 48 8b 53 58 mov 0x58(%rbx),%rdx - 41bbbf: 48 8d 4d 20 lea 0x20(%rbp),%rcx - 41bbc3: 48 8b 42 08 mov 0x8(%rdx),%rax - 41bbc7: 48 83 e0 f8 and $0xfffffffffffffff8,%rax - 41bbcb: 48 39 c8 cmp %rcx,%rax - 41bbce: 0f 83 0c 05 00 00 jae 41c0e0 <_int_malloc+0xba0> - 41bbd4: f6 43 04 01 testb $0x1,0x4(%rbx) - 41bbd8: 0f 85 e2 04 00 00 jne 41c0c0 <_int_malloc+0xb80> - 41bbde: 48 89 df mov %rbx,%rdi - 41bbe1: e8 4a c2 ff ff callq 417e30 - 41bbe6: 8b 44 24 38 mov 0x38(%rsp),%eax - 41bbea: 48 81 fd ff 03 00 00 cmp $0x3ff,%rbp - 41bbf1: 89 04 24 mov %eax,(%rsp) - 41bbf4: 0f 86 1f fb ff ff jbe 41b719 <_int_malloc+0x1d9> - 41bbfa: 48 83 7c 24 30 30 cmpq $0x30,0x30(%rsp) - 41bc00: 8b 44 24 3c mov 0x3c(%rsp),%eax - 41bc04: 89 04 24 mov %eax,(%rsp) - 41bc07: 0f 86 0c fb ff ff jbe 41b719 <_int_malloc+0x1d9> - 41bc0d: 48 83 7c 24 40 14 cmpq $0x14,0x40(%rsp) - 41bc13: 8b 44 24 50 mov 0x50(%rsp),%eax - 41bc17: 89 04 24 mov %eax,(%rsp) - 41bc1a: 0f 86 f9 fa ff ff jbe 41b719 <_int_malloc+0x1d9> - 41bc20: 48 83 7c 24 48 0a cmpq $0xa,0x48(%rsp) - 41bc26: 8b 44 24 54 mov 0x54(%rsp),%eax - 41bc2a: 89 04 24 mov %eax,(%rsp) - 41bc2d: 0f 86 e6 fa ff ff jbe 41b719 <_int_malloc+0x1d9> - 41bc33: 48 83 7c 24 58 04 cmpq $0x4,0x58(%rsp) - 41bc39: 8b 44 24 68 mov 0x68(%rsp),%eax - 41bc3d: 89 04 24 mov %eax,(%rsp) - 41bc40: 0f 86 d3 fa ff ff jbe 41b719 <_int_malloc+0x1d9> - 41bc46: 48 83 7c 24 60 02 cmpq $0x2,0x60(%rsp) - 41bc4c: 41 be 7e 00 00 00 mov $0x7e,%r14d - 41bc52: 44 0f 46 74 24 6c cmovbe 0x6c(%rsp),%r14d - 41bc58: 44 89 34 24 mov %r14d,(%rsp) - 41bc5c: e9 b8 fa ff ff jmpq 41b719 <_int_malloc+0x1d9> - 41bc61: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 41bc68: 49 83 4c 2d 08 01 orq $0x1,0x8(%r13,%rbp,1) - 41bc6e: 48 81 fb 00 a8 6c 00 cmp $0x6ca800,%rbx - 41bc75: 74 05 je 41bc7c <_int_malloc+0x73c> - 41bc77: 49 83 4d 08 04 orq $0x4,0x8(%r13) - 41bc7c: 8b 05 b2 09 2b 00 mov 0x2b09b2(%rip),%eax # 6cc634 - 41bc82: 49 8d 4d 10 lea 0x10(%r13),%rcx - 41bc86: 85 c0 test %eax,%eax - 41bc88: 0f 84 cc fb ff ff je 41b85a <_int_malloc+0x31a> - 41bc8e: e9 38 fd ff ff jmpq 41b9cb <_int_malloc+0x48b> - 41bc93: b8 fa 00 00 00 mov $0xfa,%eax - 41bc98: b9 7e 00 00 00 mov $0x7e,%ecx - 41bc9d: e9 45 fb ff ff jmpq 41b7e7 <_int_malloc+0x2a7> - 41bca2: 8b 04 24 mov (%rsp),%eax - 41bca5: 8d 44 00 fe lea -0x2(%rax,%rax,1),%eax - 41bca9: 48 8d 44 c3 60 lea 0x60(%rbx,%rax,8),%rax - 41bcae: 48 8b 50 08 mov 0x8(%rax),%rdx - 41bcb2: 48 8d 48 08 lea 0x8(%rax),%rcx - 41bcb6: 48 83 e8 08 sub $0x8,%rax - 41bcba: 48 39 c2 cmp %rax,%rdx - 41bcbd: 0f 84 4d fe ff ff je 41bb10 <_int_malloc+0x5d0> - 41bcc3: 48 3b 6a 08 cmp 0x8(%rdx),%rbp - 41bcc7: 0f 87 43 fe ff ff ja 41bb10 <_int_malloc+0x5d0> - 41bccd: 4c 8b 7a 28 mov 0x28(%rdx),%r15 - 41bcd1: eb 04 jmp 41bcd7 <_int_malloc+0x797> - 41bcd3: 4d 8b 7f 28 mov 0x28(%r15),%r15 - 41bcd7: 49 8b 57 08 mov 0x8(%r15),%rdx - 41bcdb: 49 89 d6 mov %rdx,%r14 - 41bcde: 49 83 e6 f8 and $0xfffffffffffffff8,%r14 - 41bce2: 4c 39 f5 cmp %r14,%rbp - 41bce5: 77 ec ja 41bcd3 <_int_malloc+0x793> - 41bce7: 4c 3b 79 08 cmp 0x8(%rcx),%r15 - 41bceb: 0f 84 da 04 00 00 je 41c1cb <_int_malloc+0xc8b> - 41bcf1: 49 8b 4f 10 mov 0x10(%r15),%rcx - 41bcf5: 4c 89 f0 mov %r14,%rax - 41bcf8: 48 3b 51 08 cmp 0x8(%rcx),%rdx - 41bcfc: 75 0a jne 41bd08 <_int_malloc+0x7c8> - 41bcfe: 48 89 d0 mov %rdx,%rax - 41bd01: 49 89 cf mov %rcx,%r15 - 41bd04: 48 83 e0 f8 and $0xfffffffffffffff8,%rax - 41bd08: 4c 89 f7 mov %r14,%rdi - 41bd0b: 48 29 ef sub %rbp,%rdi - 41bd0e: 49 39 04 07 cmp %rax,(%r15,%rax,1) - 41bd12: 48 89 3c 24 mov %rdi,(%rsp) - 41bd16: 0f 85 26 06 00 00 jne 41c342 <_int_malloc+0xe02> - 41bd1c: 4d 8b 6f 10 mov 0x10(%r15),%r13 - 41bd20: 49 8b 47 18 mov 0x18(%r15),%rax - 41bd24: 4d 3b 7d 18 cmp 0x18(%r13),%r15 - 41bd28: 0f 85 c0 04 00 00 jne 41c1ee <_int_malloc+0xcae> - 41bd2e: 4c 3b 78 10 cmp 0x10(%rax),%r15 - 41bd32: 0f 85 b6 04 00 00 jne 41c1ee <_int_malloc+0xcae> - 41bd38: 49 81 7f 08 ff 03 00 cmpq $0x3ff,0x8(%r15) - 41bd3f: 00 - 41bd40: 49 89 45 18 mov %rax,0x18(%r13) - 41bd44: 4c 89 68 10 mov %r13,0x10(%rax) - 41bd48: 76 0d jbe 41bd57 <_int_malloc+0x817> - 41bd4a: 49 8b 47 20 mov 0x20(%r15),%rax - 41bd4e: 48 85 c0 test %rax,%rax - 41bd51: 0f 85 06 06 00 00 jne 41c35d <_int_malloc+0xe1d> - 41bd57: 48 83 3c 24 1f cmpq $0x1f,(%rsp) - 41bd5c: 0f 87 38 04 00 00 ja 41c19a <_int_malloc+0xc5a> - 41bd62: 4b 83 4c 37 08 01 orq $0x1,0x8(%r15,%r14,1) - 41bd68: 48 81 fb 00 a8 6c 00 cmp $0x6ca800,%rbx - 41bd6f: 0f 85 e4 f8 ff ff jne 41b659 <_int_malloc+0x119> - 41bd75: e9 ce fa ff ff jmpq 41b848 <_int_malloc+0x308> - 41bd7a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 41bd80: 41 8d 44 24 30 lea 0x30(%r12),%eax - 41bd85: 89 04 24 mov %eax,(%rsp) - 41bd88: e9 00 f9 ff ff jmpq 41b68d <_int_malloc+0x14d> - 41bd8d: 44 89 cf mov %r9d,%edi - 41bd90: be 3c ca 4b 00 mov $0x4bca3c,%esi - 41bd95: ba 42 21 4a 00 mov $0x4a2142,%edx - 41bd9a: 83 e7 02 and $0x2,%edi - 41bd9d: 31 c0 xor %eax,%eax - 41bd9f: e8 1c 58 ff ff callq 4115c0 <__libc_message> - 41bda4: 49 8b 75 08 mov 0x8(%r13),%rsi - 41bda8: e9 ee f9 ff ff jmpq 41b79b <_int_malloc+0x25b> - 41bdad: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 41bdb4: 31 c9 xor %ecx,%ecx - 41bdb6: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) - 41bdbd: 48 89 c8 mov %rcx,%rax - 41bdc0: c3 retq - 41bdc1: 31 f6 xor %esi,%esi - 41bdc3: 48 89 ef mov %rbp,%rdi - 41bdc6: e8 65 ee ff ff callq 41ac30 - 41bdcb: 48 85 c0 test %rax,%rax - 41bdce: 0f 84 86 00 00 00 je 41be5a <_int_malloc+0x91a> - 41bdd4: 8b 15 5a 08 2b 00 mov 0x2b085a(%rip),%edx # 6cc634 - 41bdda: 48 89 c1 mov %rax,%rcx - 41bddd: 85 d2 test %edx,%edx - 41bddf: 0f 84 75 fa ff ff je 41b85a <_int_malloc+0x31a> - 41bde5: 89 d6 mov %edx,%esi - 41bde7: 48 8b 54 24 08 mov 0x8(%rsp),%rdx - 41bdec: 48 89 c7 mov %rax,%rdi - 41bdef: 40 80 f6 ff xor $0xff,%sil - 41bdf3: e8 58 45 fe ff callq 400350 <__rela_iplt_end+0x88> - 41bdf8: 48 89 c1 mov %rax,%rcx - 41bdfb: e9 5a fa ff ff jmpq 41b85a <_int_malloc+0x31a> - 41be00: 49 89 ec mov %rbp,%r12 - 41be03: 49 c1 ec 0c shr $0xc,%r12 - 41be07: 49 83 fc 0a cmp $0xa,%r12 - 41be0b: 76 54 jbe 41be61 <_int_malloc+0x921> - 41be0d: 49 89 ec mov %rbp,%r12 - 41be10: 49 c1 ec 0f shr $0xf,%r12 - 41be14: 49 83 fc 04 cmp $0x4,%r12 - 41be18: 0f 87 43 02 00 00 ja 41c061 <_int_malloc+0xb21> - 41be1e: 41 8d 44 24 77 lea 0x77(%r12),%eax - 41be23: 89 04 24 mov %eax,(%rsp) - 41be26: e9 62 f8 ff ff jmpq 41b68d <_int_malloc+0x14d> - 41be2b: 89 c2 mov %eax,%edx - 41be2d: 89 c7 mov %eax,%edi - 41be2f: c1 e2 06 shl $0x6,%edx - 41be32: 83 ea 02 sub $0x2,%edx - 41be35: 89 d0 mov %edx,%eax - 41be37: 48 8d 54 c3 58 lea 0x58(%rbx,%rax,8),%rdx - 41be3c: b8 01 00 00 00 mov $0x1,%eax - 41be41: e9 06 fd ff ff jmpq 41bb4c <_int_malloc+0x60c> - 41be46: 89 ef mov %ebp,%edi - 41be48: 4c 89 e2 mov %r12,%rdx - 41be4b: be 3c ca 4b 00 mov $0x4bca3c,%esi - 41be50: 83 e7 02 and $0x2,%edi - 41be53: 31 c0 xor %eax,%eax - 41be55: e8 66 57 ff ff callq 4115c0 <__libc_message> - 41be5a: 31 c9 xor %ecx,%ecx - 41be5c: e9 f9 f9 ff ff jmpq 41b85a <_int_malloc+0x31a> - 41be61: 41 8d 44 24 6e lea 0x6e(%r12),%eax - 41be66: 89 04 24 mov %eax,(%rsp) - 41be69: e9 1f f8 ff ff jmpq 41b68d <_int_malloc+0x14d> - 41be6e: 41 bc b0 27 4a 00 mov $0x4a27b0,%r12d - 41be74: 8b 2d f6 e8 2a 00 mov 0x2ae8f6(%rip),%ebp # 6ca770 - 41be7a: 83 4b 04 04 orl $0x4,0x4(%rbx) - 41be7e: 89 e8 mov %ebp,%eax - 41be80: 83 e0 05 and $0x5,%eax - 41be83: 83 f8 05 cmp $0x5,%eax - 41be86: 74 be je 41be46 <_int_malloc+0x906> - 41be88: 40 f6 c5 01 test $0x1,%bpl - 41be8c: 0f 85 ca 00 00 00 jne 41bf5c <_int_malloc+0xa1c> - 41be92: 83 e5 02 and $0x2,%ebp - 41be95: 74 c3 je 41be5a <_int_malloc+0x91a> - 41be97: e8 64 1d ff ff callq 40dc00 - 41be9c: 0f 1f 40 00 nopl 0x0(%rax) - 41bea0: ba be 00 00 00 mov $0xbe,%edx - 41bea5: bf 03 00 00 00 mov $0x3,%edi - 41beaa: eb 89 jmp 41be35 <_int_malloc+0x8f5> - 41beac: 49 8b 47 08 mov 0x8(%r15),%rax - 41beb0: 48 83 e0 f8 and $0xfffffffffffffff8,%rax - 41beb4: 48 39 c5 cmp %rax,%rbp - 41beb7: 0f 87 34 04 00 00 ja 41c2f1 <_int_malloc+0xdb1> - 41bebd: 4d 8d 2c 07 lea (%r15,%rax,1),%r13 - 41bec1: 48 89 c7 mov %rax,%rdi - 41bec4: 48 29 ef sub %rbp,%rdi - 41bec7: 49 3b 45 00 cmp 0x0(%r13),%rax - 41becb: 48 89 3c 24 mov %rdi,(%rsp) - 41becf: 0f 85 6c 02 00 00 jne 41c141 <_int_malloc+0xc01> - 41bed5: 49 8b 47 10 mov 0x10(%r15),%rax - 41bed9: 49 8b 57 18 mov 0x18(%r15),%rdx - 41bedd: 4c 3b 78 18 cmp 0x18(%rax),%r15 - 41bee1: 0f 85 9a 01 00 00 jne 41c081 <_int_malloc+0xb41> - 41bee7: 4c 8b 72 10 mov 0x10(%rdx),%r14 - 41beeb: 4d 39 f7 cmp %r14,%r15 - 41beee: 0f 85 8d 01 00 00 jne 41c081 <_int_malloc+0xb41> - 41bef4: 49 81 7e 08 ff 03 00 cmpq $0x3ff,0x8(%r14) - 41befb: 00 - 41befc: 48 89 50 18 mov %rdx,0x18(%rax) - 41bf00: 48 89 42 10 mov %rax,0x10(%rdx) - 41bf04: 76 0d jbe 41bf13 <_int_malloc+0x9d3> - 41bf06: 49 8b 56 20 mov 0x20(%r14),%rdx - 41bf0a: 48 85 d2 test %rdx,%rdx - 41bf0d: 0f 85 f7 03 00 00 jne 41c30a <_int_malloc+0xdca> - 41bf13: 48 83 3c 24 1f cmpq $0x1f,(%rsp) - 41bf18: 0f 87 c4 00 00 00 ja 41bfe2 <_int_malloc+0xaa2> - 41bf1e: 49 83 4d 08 01 orq $0x1,0x8(%r13) - 41bf23: 48 81 fb 00 a8 6c 00 cmp $0x6ca800,%rbx - 41bf2a: 0f 85 29 f7 ff ff jne 41b659 <_int_malloc+0x119> - 41bf30: e9 13 f9 ff ff jmpq 41b848 <_int_malloc+0x308> - 41bf35: 0f 1f 00 nopl (%rax) - 41bf38: b9 b8 2e 4a 00 mov $0x4a2eb8,%ecx - 41bf3d: ba ef 0d 00 00 mov $0xdef,%edx - 41bf42: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 41bf47: bf 80 28 4a 00 mov $0x4a2880,%edi - 41bf4c: e8 cf ae ff ff callq 416e20 <__malloc_assert> - 41bf51: 41 bc d8 27 4a 00 mov $0x4a27d8,%r12d - 41bf57: e9 18 ff ff ff jmpq 41be74 <_int_malloc+0x934> - 41bf5c: 4c 8d 6c 24 70 lea 0x70(%rsp),%r13 - 41bf61: 48 8d b4 24 80 00 00 lea 0x80(%rsp),%rsi - 41bf68: 00 - 41bf69: 49 8d 7f 10 lea 0x10(%r15),%rdi - 41bf6d: 31 c9 xor %ecx,%ecx - 41bf6f: ba 10 00 00 00 mov $0x10,%edx - 41bf74: c6 84 24 80 00 00 00 movb $0x0,0x80(%rsp) - 41bf7b: 00 - 41bf7c: e8 2f 5f 03 00 callq 451eb0 <_itoa_word> - 41bf81: 4c 39 e8 cmp %r13,%rax - 41bf84: 48 89 c3 mov %rax,%rbx - 41bf87: 76 25 jbe 41bfae <_int_malloc+0xa6e> - 41bf89: 48 89 c2 mov %rax,%rdx - 41bf8c: 48 89 c7 mov %rax,%rdi - 41bf8f: be 30 00 00 00 mov $0x30,%esi - 41bf94: 4c 29 ea sub %r13,%rdx - 41bf97: 4c 8d 70 ff lea -0x1(%rax),%r14 - 41bf9b: 48 29 d7 sub %rdx,%rdi - 41bf9e: e8 ad 43 fe ff callq 400350 <__rela_iplt_end+0x88> - 41bfa3: 48 8d 44 24 6f lea 0x6f(%rsp),%rax - 41bfa8: 4c 29 f0 sub %r14,%rax - 41bfab: 48 01 c3 add %rax,%rbx - 41bfae: 48 8b 05 0b 13 2b 00 mov 0x2b130b(%rip),%rax # 6cd2c0 <__libc_argv> - 41bfb5: ba 38 20 4a 00 mov $0x4a2038,%edx - 41bfba: 89 ef mov %ebp,%edi - 41bfbc: 4c 89 e1 mov %r12,%rcx - 41bfbf: 49 89 d8 mov %rbx,%r8 - 41bfc2: be a8 23 4a 00 mov $0x4a23a8,%esi - 41bfc7: 48 8b 00 mov (%rax),%rax - 41bfca: 48 85 c0 test %rax,%rax - 41bfcd: 48 0f 45 d0 cmovne %rax,%rdx - 41bfd1: 83 e7 02 and $0x2,%edi - 41bfd4: 31 c0 xor %eax,%eax - 41bfd6: e8 e5 55 ff ff callq 4115c0 <__libc_message> - 41bfdb: 31 c9 xor %ecx,%ecx - 41bfdd: e9 78 f8 ff ff jmpq 41b85a <_int_malloc+0x31a> - 41bfe2: 48 8b 53 68 mov 0x68(%rbx),%rdx - 41bfe6: 4c 39 62 18 cmp %r12,0x18(%rdx) - 41bfea: 0f 85 f3 01 00 00 jne 41c1e3 <_int_malloc+0xca3> - 41bff0: 49 8d 04 2f lea (%r15,%rbp,1),%rax - 41bff4: 48 81 fd ff 03 00 00 cmp $0x3ff,%rbp - 41bffb: 4c 89 60 18 mov %r12,0x18(%rax) - 41bfff: 48 89 50 10 mov %rdx,0x10(%rax) - 41c003: 48 89 43 68 mov %rax,0x68(%rbx) - 41c007: 48 89 42 18 mov %rax,0x18(%rdx) - 41c00b: 77 04 ja 41c011 <_int_malloc+0xad1> - 41c00d: 48 89 43 60 mov %rax,0x60(%rbx) - 41c011: 48 81 3c 24 ff 03 00 cmpq $0x3ff,(%rsp) - 41c018: 00 - 41c019: 76 10 jbe 41c02b <_int_malloc+0xaeb> - 41c01b: 48 c7 40 20 00 00 00 movq $0x0,0x20(%rax) - 41c022: 00 - 41c023: 48 c7 40 28 00 00 00 movq $0x0,0x28(%rax) - 41c02a: 00 - 41c02b: 31 d2 xor %edx,%edx - 41c02d: 48 81 fb 00 a8 6c 00 cmp $0x6ca800,%rbx - 41c034: 48 8b 3c 24 mov (%rsp),%rdi - 41c038: 0f 95 c2 setne %dl - 41c03b: 48 83 cd 01 or $0x1,%rbp - 41c03f: 48 c1 e2 02 shl $0x2,%rdx - 41c043: 48 09 ea or %rbp,%rdx - 41c046: 49 89 57 08 mov %rdx,0x8(%r15) - 41c04a: 48 89 fa mov %rdi,%rdx - 41c04d: 48 83 ca 01 or $0x1,%rdx - 41c051: 48 89 50 08 mov %rdx,0x8(%rax) - 41c055: 48 89 fa mov %rdi,%rdx - 41c058: 48 89 3c 10 mov %rdi,(%rax,%rdx,1) - 41c05c: e9 e7 f7 ff ff jmpq 41b848 <_int_malloc+0x308> - 41c061: 48 89 e8 mov %rbp,%rax - 41c064: 48 c1 e8 12 shr $0x12,%rax - 41c068: 44 8d 60 7c lea 0x7c(%rax),%r12d - 41c06c: 48 83 f8 02 cmp $0x2,%rax - 41c070: b8 7e 00 00 00 mov $0x7e,%eax - 41c075: 41 0f 46 c4 cmovbe %r12d,%eax - 41c079: 89 04 24 mov %eax,(%rsp) - 41c07c: e9 0c f6 ff ff jmpq 41b68d <_int_malloc+0x14d> - 41c081: 8b 15 e9 e6 2a 00 mov 0x2ae6e9(%rip),%edx # 6ca770 - 41c087: 83 4b 04 04 orl $0x4,0x4(%rbx) - 41c08b: 89 d0 mov %edx,%eax - 41c08d: 83 e0 05 and $0x5,%eax - 41c090: 83 f8 05 cmp $0x5,%eax - 41c093: 0f 84 3d 02 00 00 je 41c2d6 <_int_malloc+0xd96> - 41c099: 41 89 d6 mov %edx,%r14d - 41c09c: 41 83 e6 02 and $0x2,%r14d - 41c0a0: 83 e2 01 and $0x1,%edx - 41c0a3: 0f 85 92 01 00 00 jne 41c23b <_int_malloc+0xcfb> - 41c0a9: 45 85 f6 test %r14d,%r14d - 41c0ac: 0f 84 61 fe ff ff je 41bf13 <_int_malloc+0x9d3> - 41c0b2: e9 e0 fd ff ff jmpq 41be97 <_int_malloc+0x957> - 41c0b7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 41c0be: 00 00 - 41c0c0: 48 89 de mov %rbx,%rsi - 41c0c3: 48 89 ef mov %rbp,%rdi - 41c0c6: e8 65 eb ff ff callq 41ac30 - 41c0cb: 48 85 c0 test %rax,%rax - 41c0ce: 0f 85 00 fd ff ff jne 41bdd4 <_int_malloc+0x894> - 41c0d4: 31 c9 xor %ecx,%ecx - 41c0d6: e9 7f f7 ff ff jmpq 41b85a <_int_malloc+0x31a> - 41c0db: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41c0e0: 48 29 e8 sub %rbp,%rax - 41c0e3: 31 c9 xor %ecx,%ecx - 41c0e5: 48 81 fb 00 a8 6c 00 cmp $0x6ca800,%rbx - 41c0ec: 0f 95 c1 setne %cl - 41c0ef: 48 8d 34 2a lea (%rdx,%rbp,1),%rsi - 41c0f3: 48 83 cd 01 or $0x1,%rbp - 41c0f7: 48 c1 e1 02 shl $0x2,%rcx - 41c0fb: 48 83 c8 01 or $0x1,%rax - 41c0ff: 48 09 e9 or %rbp,%rcx - 41c102: 48 89 73 58 mov %rsi,0x58(%rbx) - 41c106: 48 89 4a 08 mov %rcx,0x8(%rdx) - 41c10a: 48 89 46 08 mov %rax,0x8(%rsi) - 41c10e: 48 8d 4a 10 lea 0x10(%rdx),%rcx - 41c112: 8b 05 1c 05 2b 00 mov 0x2b051c(%rip),%eax # 6cc634 - 41c118: 85 c0 test %eax,%eax - 41c11a: 0f 84 3a f7 ff ff je 41b85a <_int_malloc+0x31a> - 41c120: e9 a6 f8 ff ff jmpq 41b9cb <_int_malloc+0x48b> - 41c125: 0f 1f 00 nopl (%rax) - 41c128: b9 b8 2e 4a 00 mov $0x4a2eb8,%ecx - 41c12d: ba 77 0e 00 00 mov $0xe77,%edx - 41c132: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 41c137: bf 5e 21 4a 00 mov $0x4a215e,%edi - 41c13c: e8 df ac ff ff callq 416e20 <__malloc_assert> - 41c141: 44 8b 0d 28 e6 2a 00 mov 0x2ae628(%rip),%r9d # 6ca770 - 41c148: 83 4b 04 04 orl $0x4,0x4(%rbx) - 41c14c: 44 89 c8 mov %r9d,%eax - 41c14f: 83 e0 05 and $0x5,%eax - 41c152: 83 f8 05 cmp $0x5,%eax - 41c155: 0f 84 e2 02 00 00 je 41c43d <_int_malloc+0xefd> - 41c15b: 41 f6 c1 01 test $0x1,%r9b - 41c15f: 0f 85 30 02 00 00 jne 41c395 <_int_malloc+0xe55> - 41c165: 41 f6 c1 02 test $0x2,%r9b - 41c169: 0f 85 28 fd ff ff jne 41be97 <_int_malloc+0x957> - 41c16f: 49 8b 47 10 mov 0x10(%r15),%rax - 41c173: 49 8b 57 18 mov 0x18(%r15),%rdx - 41c177: 4c 3b 78 18 cmp 0x18(%rax),%r15 - 41c17b: 0f 85 92 fd ff ff jne 41bf13 <_int_malloc+0x9d3> - 41c181: 4c 8b 72 10 mov 0x10(%rdx),%r14 - 41c185: 4d 39 f7 cmp %r14,%r15 - 41c188: 0f 84 66 fd ff ff je 41bef4 <_int_malloc+0x9b4> - 41c18e: 44 89 ca mov %r9d,%edx - 41c191: 83 4b 04 04 orl $0x4,0x4(%rbx) - 41c195: e9 ff fe ff ff jmpq 41c099 <_int_malloc+0xb59> - 41c19a: 48 8b 53 68 mov 0x68(%rbx),%rdx - 41c19e: 49 8d 04 2f lea (%r15,%rbp,1),%rax - 41c1a2: 4c 39 62 18 cmp %r12,0x18(%rdx) - 41c1a6: 75 30 jne 41c1d8 <_int_malloc+0xc98> - 41c1a8: 48 81 3c 24 ff 03 00 cmpq $0x3ff,(%rsp) - 41c1af: 00 - 41c1b0: 4c 89 60 18 mov %r12,0x18(%rax) - 41c1b4: 48 89 50 10 mov %rdx,0x10(%rax) - 41c1b8: 48 89 43 68 mov %rax,0x68(%rbx) - 41c1bc: 48 89 42 18 mov %rax,0x18(%rdx) - 41c1c0: 0f 86 65 fe ff ff jbe 41c02b <_int_malloc+0xaeb> - 41c1c6: e9 50 fe ff ff jmpq 41c01b <_int_malloc+0xadb> - 41c1cb: 49 8b 47 08 mov 0x8(%r15),%rax - 41c1cf: 48 83 e0 f8 and $0xfffffffffffffff8,%rax - 41c1d3: e9 30 fb ff ff jmpq 41bd08 <_int_malloc+0x7c8> - 41c1d8: 41 bc 08 28 4a 00 mov $0x4a2808,%r12d - 41c1de: e9 91 fc ff ff jmpq 41be74 <_int_malloc+0x934> - 41c1e3: 41 bc 30 28 4a 00 mov $0x4a2830,%r12d - 41c1e9: e9 86 fc ff ff jmpq 41be74 <_int_malloc+0x934> - 41c1ee: 8b 3d 7c e5 2a 00 mov 0x2ae57c(%rip),%edi # 6ca770 - 41c1f4: 48 89 d9 mov %rbx,%rcx - 41c1f7: 4c 89 fa mov %r15,%rdx - 41c1fa: be 95 20 4a 00 mov $0x4a2095,%esi - 41c1ff: e8 ac b0 ff ff callq 4172b0 - 41c204: e9 4e fb ff ff jmpq 41bd57 <_int_malloc+0x817> - 41c209: b9 b8 2e 4a 00 mov $0x4a2eb8,%ecx - 41c20e: ba df 0d 00 00 mov $0xddf,%edx - 41c213: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 41c218: bf 58 28 4a 00 mov $0x4a2858,%edi - 41c21d: e8 fe ab ff ff callq 416e20 <__malloc_assert> - 41c222: b9 b8 2e 4a 00 mov $0x4a2eb8,%ecx - 41c227: ba eb 0d 00 00 mov $0xdeb,%edx - 41c22c: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 41c231: bf 80 28 4a 00 mov $0x4a2880,%edi - 41c236: e8 e5 ab ff ff callq 416e20 <__malloc_assert> - 41c23b: 4c 8d 5c 24 70 lea 0x70(%rsp),%r11 - 41c240: 48 8d b4 24 80 00 00 lea 0x80(%rsp),%rsi - 41c247: 00 - 41c248: 31 c9 xor %ecx,%ecx - 41c24a: ba 10 00 00 00 mov $0x10,%edx - 41c24f: 4c 89 ff mov %r15,%rdi - 41c252: c6 84 24 80 00 00 00 movb $0x0,0x80(%rsp) - 41c259: 00 - 41c25a: 4c 89 5c 24 10 mov %r11,0x10(%rsp) - 41c25f: e8 4c 5c 03 00 callq 451eb0 <_itoa_word> - 41c264: 4c 8b 5c 24 10 mov 0x10(%rsp),%r11 - 41c269: 49 89 c0 mov %rax,%r8 - 41c26c: 4c 39 d8 cmp %r11,%rax - 41c26f: 76 36 jbe 41c2a7 <_int_malloc+0xd67> - 41c271: 4c 89 c2 mov %r8,%rdx - 41c274: 4c 89 c7 mov %r8,%rdi - 41c277: 48 8d 40 ff lea -0x1(%rax),%rax - 41c27b: 4c 29 da sub %r11,%rdx - 41c27e: be 30 00 00 00 mov $0x30,%esi - 41c283: 4c 89 44 24 18 mov %r8,0x18(%rsp) - 41c288: 48 29 d7 sub %rdx,%rdi - 41c28b: 48 89 44 24 10 mov %rax,0x10(%rsp) - 41c290: e8 bb 40 fe ff callq 400350 <__rela_iplt_end+0x88> - 41c295: 48 8d 44 24 6f lea 0x6f(%rsp),%rax - 41c29a: 48 2b 44 24 10 sub 0x10(%rsp),%rax - 41c29f: 4c 8b 44 24 18 mov 0x18(%rsp),%r8 - 41c2a4: 49 01 c0 add %rax,%r8 - 41c2a7: 48 8b 05 12 10 2b 00 mov 0x2b1012(%rip),%rax # 6cd2c0 <__libc_argv> - 41c2ae: ba 38 20 4a 00 mov $0x4a2038,%edx - 41c2b3: b9 95 20 4a 00 mov $0x4a2095,%ecx - 41c2b8: be a8 23 4a 00 mov $0x4a23a8,%esi - 41c2bd: 44 89 f7 mov %r14d,%edi - 41c2c0: 48 8b 00 mov (%rax),%rax - 41c2c3: 48 85 c0 test %rax,%rax - 41c2c6: 48 0f 45 d0 cmovne %rax,%rdx - 41c2ca: 31 c0 xor %eax,%eax - 41c2cc: e8 ef 52 ff ff callq 4115c0 <__libc_message> - 41c2d1: e9 3d fc ff ff jmpq 41bf13 <_int_malloc+0x9d3> - 41c2d6: 89 d7 mov %edx,%edi - 41c2d8: be 3c ca 4b 00 mov $0x4bca3c,%esi - 41c2dd: ba 95 20 4a 00 mov $0x4a2095,%edx - 41c2e2: 83 e7 02 and $0x2,%edi - 41c2e5: 31 c0 xor %eax,%eax - 41c2e7: e8 d4 52 ff ff callq 4115c0 <__libc_message> - 41c2ec: e9 22 fc ff ff jmpq 41bf13 <_int_malloc+0x9d3> - 41c2f1: b9 b8 2e 4a 00 mov $0x4a2eb8,%ecx - 41c2f6: ba 8a 0e 00 00 mov $0xe8a,%edx - 41c2fb: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 41c300: bf a8 28 4a 00 mov $0x4a28a8,%edi - 41c305: e8 16 ab ff ff callq 416e20 <__malloc_assert> - 41c30a: 4c 39 72 28 cmp %r14,0x28(%rdx) - 41c30e: 0f 85 6b 01 00 00 jne 41c47f <_int_malloc+0xf3f> - 41c314: 49 8b 4e 28 mov 0x28(%r14),%rcx - 41c318: 4c 39 71 20 cmp %r14,0x20(%rcx) - 41c31c: 0f 85 5d 01 00 00 jne 41c47f <_int_malloc+0xf3f> - 41c322: 48 83 78 20 00 cmpq $0x0,0x20(%rax) - 41c327: 0f 84 2c 01 00 00 je 41c459 <_int_malloc+0xf19> - 41c32d: 49 8b 46 28 mov 0x28(%r14),%rax - 41c331: 48 89 42 28 mov %rax,0x28(%rdx) - 41c335: 49 8b 46 28 mov 0x28(%r14),%rax - 41c339: 48 89 50 20 mov %rdx,0x20(%rax) - 41c33d: e9 d1 fb ff ff jmpq 41bf13 <_int_malloc+0x9d3> - 41c342: 8b 3d 28 e4 2a 00 mov 0x2ae428(%rip),%edi # 6ca770 - 41c348: 48 89 d9 mov %rbx,%rcx - 41c34b: 4c 89 fa mov %r15,%rdx - 41c34e: be 78 20 4a 00 mov $0x4a2078,%esi - 41c353: e8 58 af ff ff callq 4172b0 - 41c358: e9 bf f9 ff ff jmpq 41bd1c <_int_malloc+0x7dc> - 41c35d: 4c 3b 78 28 cmp 0x28(%rax),%r15 - 41c361: 0f 85 74 01 00 00 jne 41c4db <_int_malloc+0xf9b> - 41c367: 49 8b 57 28 mov 0x28(%r15),%rdx - 41c36b: 4c 3b 7a 20 cmp 0x20(%rdx),%r15 - 41c36f: 0f 85 66 01 00 00 jne 41c4db <_int_malloc+0xf9b> - 41c375: 49 83 7d 20 00 cmpq $0x0,0x20(%r13) - 41c37a: 0f 84 35 01 00 00 je 41c4b5 <_int_malloc+0xf75> - 41c380: 49 8b 57 28 mov 0x28(%r15),%rdx - 41c384: 48 89 50 28 mov %rdx,0x28(%rax) - 41c388: 49 8b 57 28 mov 0x28(%r15),%rdx - 41c38c: 48 89 42 20 mov %rax,0x20(%rdx) - 41c390: e9 c2 f9 ff ff jmpq 41bd57 <_int_malloc+0x817> - 41c395: 4c 8d 74 24 70 lea 0x70(%rsp),%r14 - 41c39a: 48 8d b4 24 80 00 00 lea 0x80(%rsp),%rsi - 41c3a1: 00 - 41c3a2: 31 c9 xor %ecx,%ecx - 41c3a4: ba 10 00 00 00 mov $0x10,%edx - 41c3a9: 4c 89 ff mov %r15,%rdi - 41c3ac: 44 89 4c 24 10 mov %r9d,0x10(%rsp) - 41c3b1: c6 84 24 80 00 00 00 movb $0x0,0x80(%rsp) - 41c3b8: 00 - 41c3b9: e8 f2 5a 03 00 callq 451eb0 <_itoa_word> - 41c3be: 4c 39 f0 cmp %r14,%rax - 41c3c1: 49 89 c0 mov %rax,%r8 - 41c3c4: 44 8b 4c 24 10 mov 0x10(%rsp),%r9d - 41c3c9: 76 40 jbe 41c40b <_int_malloc+0xecb> - 41c3cb: 4c 89 c2 mov %r8,%rdx - 41c3ce: 4c 89 c7 mov %r8,%rdi - 41c3d1: 48 8d 40 ff lea -0x1(%rax),%rax - 41c3d5: 4c 29 f2 sub %r14,%rdx - 41c3d8: be 30 00 00 00 mov $0x30,%esi - 41c3dd: 44 89 4c 24 24 mov %r9d,0x24(%rsp) - 41c3e2: 48 29 d7 sub %rdx,%rdi - 41c3e5: 4c 89 44 24 18 mov %r8,0x18(%rsp) - 41c3ea: 48 89 44 24 10 mov %rax,0x10(%rsp) - 41c3ef: e8 5c 3f fe ff callq 400350 <__rela_iplt_end+0x88> - 41c3f4: 48 8d 44 24 6f lea 0x6f(%rsp),%rax - 41c3f9: 48 2b 44 24 10 sub 0x10(%rsp),%rax - 41c3fe: 4c 8b 44 24 18 mov 0x18(%rsp),%r8 - 41c403: 44 8b 4c 24 24 mov 0x24(%rsp),%r9d - 41c408: 49 01 c0 add %rax,%r8 - 41c40b: 48 8b 05 ae 0e 2b 00 mov 0x2b0eae(%rip),%rax # 6cd2c0 <__libc_argv> - 41c412: 44 89 cf mov %r9d,%edi - 41c415: ba 38 20 4a 00 mov $0x4a2038,%edx - 41c41a: b9 78 20 4a 00 mov $0x4a2078,%ecx - 41c41f: be a8 23 4a 00 mov $0x4a23a8,%esi - 41c424: 48 8b 00 mov (%rax),%rax - 41c427: 48 85 c0 test %rax,%rax - 41c42a: 48 0f 45 d0 cmovne %rax,%rdx - 41c42e: 83 e7 02 and $0x2,%edi - 41c431: 31 c0 xor %eax,%eax - 41c433: e8 88 51 ff ff callq 4115c0 <__libc_message> - 41c438: e9 98 fa ff ff jmpq 41bed5 <_int_malloc+0x995> - 41c43d: 44 89 cf mov %r9d,%edi - 41c440: ba 78 20 4a 00 mov $0x4a2078,%edx - 41c445: be 3c ca 4b 00 mov $0x4bca3c,%esi - 41c44a: 83 e7 02 and $0x2,%edi - 41c44d: 31 c0 xor %eax,%eax - 41c44f: e8 6c 51 ff ff callq 4115c0 <__libc_message> - 41c454: e9 7c fa ff ff jmpq 41bed5 <_int_malloc+0x995> - 41c459: 4c 39 f2 cmp %r14,%rdx - 41c45c: 74 4a je 41c4a8 <_int_malloc+0xf68> - 41c45e: 48 89 50 20 mov %rdx,0x20(%rax) - 41c462: 49 8b 56 28 mov 0x28(%r14),%rdx - 41c466: 48 89 50 28 mov %rdx,0x28(%rax) - 41c46a: 49 8b 56 20 mov 0x20(%r14),%rdx - 41c46e: 48 89 42 28 mov %rax,0x28(%rdx) - 41c472: 49 8b 56 28 mov 0x28(%r14),%rdx - 41c476: 48 89 42 20 mov %rax,0x20(%rdx) - 41c47a: e9 94 fa ff ff jmpq 41bf13 <_int_malloc+0x9d3> - 41c47f: 8b 3d eb e2 2a 00 mov 0x2ae2eb(%rip),%edi # 6ca770 - 41c485: 4c 89 f2 mov %r14,%rdx - 41c488: 48 89 d9 mov %rbx,%rcx - 41c48b: be f0 23 4a 00 mov $0x4a23f0,%esi - 41c490: 48 89 44 24 10 mov %rax,0x10(%rsp) - 41c495: e8 16 ae ff ff callq 4172b0 - 41c49a: 49 8b 56 20 mov 0x20(%r14),%rdx - 41c49e: 48 8b 44 24 10 mov 0x10(%rsp),%rax - 41c4a3: e9 7a fe ff ff jmpq 41c322 <_int_malloc+0xde2> - 41c4a8: 48 89 40 28 mov %rax,0x28(%rax) - 41c4ac: 48 89 40 20 mov %rax,0x20(%rax) - 41c4b0: e9 5e fa ff ff jmpq 41bf13 <_int_malloc+0x9d3> - 41c4b5: 49 39 c7 cmp %rax,%r15 - 41c4b8: 74 40 je 41c4fa <_int_malloc+0xfba> - 41c4ba: 49 89 45 20 mov %rax,0x20(%r13) - 41c4be: 49 8b 47 28 mov 0x28(%r15),%rax - 41c4c2: 49 89 45 28 mov %rax,0x28(%r13) - 41c4c6: 49 8b 47 20 mov 0x20(%r15),%rax - 41c4ca: 4c 89 68 28 mov %r13,0x28(%rax) - 41c4ce: 49 8b 47 28 mov 0x28(%r15),%rax - 41c4d2: 4c 89 68 20 mov %r13,0x20(%rax) - 41c4d6: e9 7c f8 ff ff jmpq 41bd57 <_int_malloc+0x817> - 41c4db: 8b 3d 8f e2 2a 00 mov 0x2ae28f(%rip),%edi # 6ca770 - 41c4e1: 48 89 d9 mov %rbx,%rcx - 41c4e4: 4c 89 fa mov %r15,%rdx - 41c4e7: be f0 23 4a 00 mov $0x4a23f0,%esi - 41c4ec: e8 bf ad ff ff callq 4172b0 - 41c4f1: 49 8b 47 20 mov 0x20(%r15),%rax - 41c4f5: e9 7b fe ff ff jmpq 41c375 <_int_malloc+0xe35> - 41c4fa: 4d 89 6d 28 mov %r13,0x28(%r13) - 41c4fe: 4d 89 6d 20 mov %r13,0x20(%r13) - 41c502: e9 50 f8 ff ff jmpq 41bd57 <_int_malloc+0x817> - 41c507: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 41c50e: 00 00 - -000000000041c510 <_int_memalign>: - 41c510: 48 83 fa bf cmp $0xffffffffffffffbf,%rdx - 41c514: 0f 87 a6 01 00 00 ja 41c6c0 <_int_memalign+0x1b0> - 41c51a: 48 83 c2 17 add $0x17,%rdx - 41c51e: 41 56 push %r14 - 41c520: 41 55 push %r13 - 41c522: 41 54 push %r12 - 41c524: 55 push %rbp - 41c525: 48 89 d5 mov %rdx,%rbp - 41c528: 48 83 e5 f0 and $0xfffffffffffffff0,%rbp - 41c52c: b8 20 00 00 00 mov $0x20,%eax - 41c531: 48 83 fa 20 cmp $0x20,%rdx - 41c535: 48 0f 42 e8 cmovb %rax,%rbp - 41c539: 53 push %rbx - 41c53a: 49 89 f5 mov %rsi,%r13 - 41c53d: 48 8d 74 35 20 lea 0x20(%rbp,%rsi,1),%rsi - 41c542: 48 89 fb mov %rdi,%rbx - 41c545: e8 f6 ef ff ff callq 41b540 <_int_malloc> - 41c54a: 48 85 c0 test %rax,%rax - 41c54d: 48 89 c1 mov %rax,%rcx - 41c550: 0f 84 aa 01 00 00 je 41c700 <_int_memalign+0x1f0> - 41c556: 31 d2 xor %edx,%edx - 41c558: 48 8d 70 f0 lea -0x10(%rax),%rsi - 41c55c: 49 f7 f5 div %r13 - 41c55f: 48 85 d2 test %rdx,%rdx - 41c562: 0f 84 c8 00 00 00 je 41c630 <_int_memalign+0x120> - 41c568: 4a 8d 44 29 ff lea -0x1(%rcx,%r13,1),%rax - 41c56d: 4c 89 ea mov %r13,%rdx - 41c570: 48 f7 da neg %rdx - 41c573: 48 21 d0 and %rdx,%rax - 41c576: 48 83 e8 10 sub $0x10,%rax - 41c57a: 48 89 c2 mov %rax,%rdx - 41c57d: 4e 8d 24 28 lea (%rax,%r13,1),%r12 - 41c581: 48 29 f2 sub %rsi,%rdx - 41c584: 48 83 fa 1f cmp $0x1f,%rdx - 41c588: 4c 0f 47 e0 cmova %rax,%r12 - 41c58c: 48 8b 41 f8 mov -0x8(%rcx),%rax - 41c590: 4c 89 e2 mov %r12,%rdx - 41c593: 48 29 f2 sub %rsi,%rdx - 41c596: 49 89 c6 mov %rax,%r14 - 41c599: 49 83 e6 f8 and $0xfffffffffffffff8,%r14 - 41c59d: 49 29 d6 sub %rdx,%r14 - 41c5a0: 83 e0 02 and $0x2,%eax - 41c5a3: 0f 85 ef 00 00 00 jne 41c698 <_int_memalign+0x188> - 41c5a9: 48 81 fb 00 a8 6c 00 cmp $0x6ca800,%rbx - 41c5b0: 0f 84 22 01 00 00 je 41c6d8 <_int_memalign+0x1c8> - 41c5b6: 4c 89 f0 mov %r14,%rax - 41c5b9: 48 83 c8 05 or $0x5,%rax - 41c5bd: 49 89 44 24 08 mov %rax,0x8(%r12) - 41c5c2: 4b 83 4c 34 08 01 orq $0x1,0x8(%r12,%r14,1) - 41c5c8: b8 04 00 00 00 mov $0x4,%eax - 41c5cd: 48 8b 79 f8 mov -0x8(%rcx),%rdi - 41c5d1: 83 e7 07 and $0x7,%edi - 41c5d4: 48 09 f8 or %rdi,%rax - 41c5d7: 48 89 df mov %rbx,%rdi - 41c5da: 48 09 c2 or %rax,%rdx - 41c5dd: 48 89 51 f8 mov %rdx,-0x8(%rcx) - 41c5e1: ba 01 00 00 00 mov $0x1,%edx - 41c5e6: e8 d5 d1 ff ff callq 4197c0 <_int_free> - 41c5eb: 4c 39 f5 cmp %r14,%rbp - 41c5ee: 0f 87 13 01 00 00 ja 41c707 <_int_memalign+0x1f7> - 41c5f4: 49 8d 4c 24 10 lea 0x10(%r12),%rcx - 41c5f9: 31 d2 xor %edx,%edx - 41c5fb: 48 89 c8 mov %rcx,%rax - 41c5fe: 49 f7 f5 div %r13 - 41c601: 48 85 d2 test %rdx,%rdx - 41c604: 0f 85 fd 00 00 00 jne 41c707 <_int_memalign+0x1f7> - 41c60a: 49 8b 54 24 08 mov 0x8(%r12),%rdx - 41c60f: 49 89 cd mov %rcx,%r13 - 41c612: 48 89 d1 mov %rdx,%rcx - 41c615: 83 e1 02 and $0x2,%ecx - 41c618: 74 29 je 41c643 <_int_memalign+0x133> - 41c61a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 41c620: 4c 89 e8 mov %r13,%rax - 41c623: 5b pop %rbx - 41c624: 5d pop %rbp - 41c625: 41 5c pop %r12 - 41c627: 41 5d pop %r13 - 41c629: 41 5e pop %r14 - 41c62b: c3 retq - 41c62c: 0f 1f 40 00 nopl 0x0(%rax) - 41c630: 49 89 f4 mov %rsi,%r12 - 41c633: 49 89 cd mov %rcx,%r13 - 41c636: 49 8b 54 24 08 mov 0x8(%r12),%rdx - 41c63b: 48 89 d1 mov %rdx,%rcx - 41c63e: 83 e1 02 and $0x2,%ecx - 41c641: 75 dd jne 41c620 <_int_memalign+0x110> - 41c643: 48 8d 75 20 lea 0x20(%rbp),%rsi - 41c647: 48 83 e2 f8 and $0xfffffffffffffff8,%rdx - 41c64b: 48 39 f2 cmp %rsi,%rdx - 41c64e: 76 d0 jbe 41c620 <_int_memalign+0x110> - 41c650: 48 29 ea sub %rbp,%rdx - 41c653: bf 04 00 00 00 mov $0x4,%edi - 41c658: 48 81 fb 00 a8 6c 00 cmp $0x6ca800,%rbx - 41c65f: 48 0f 45 cf cmovne %rdi,%rcx - 41c663: 49 8d 34 2c lea (%r12,%rbp,1),%rsi - 41c667: 48 83 ca 01 or $0x1,%rdx - 41c66b: 48 09 ca or %rcx,%rdx - 41c66e: 48 89 df mov %rbx,%rdi - 41c671: 48 89 56 08 mov %rdx,0x8(%rsi) - 41c675: 49 8b 54 24 08 mov 0x8(%r12),%rdx - 41c67a: 83 e2 07 and $0x7,%edx - 41c67d: 48 09 d5 or %rdx,%rbp - 41c680: ba 01 00 00 00 mov $0x1,%edx - 41c685: 49 89 6c 24 08 mov %rbp,0x8(%r12) - 41c68a: e8 31 d1 ff ff callq 4197c0 <_int_free> - 41c68f: eb 8f jmp 41c620 <_int_memalign+0x110> - 41c691: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 41c698: 48 03 51 f0 add -0x10(%rcx),%rdx - 41c69c: 49 83 ce 02 or $0x2,%r14 - 41c6a0: 49 8d 44 24 10 lea 0x10(%r12),%rax - 41c6a5: 4d 89 74 24 08 mov %r14,0x8(%r12) - 41c6aa: 49 89 14 24 mov %rdx,(%r12) - 41c6ae: 5b pop %rbx - 41c6af: 5d pop %rbp - 41c6b0: 41 5c pop %r12 - 41c6b2: 41 5d pop %r13 - 41c6b4: 41 5e pop %r14 - 41c6b6: c3 retq - 41c6b7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 41c6be: 00 00 - 41c6c0: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 41c6c7: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) - 41c6ce: 31 c0 xor %eax,%eax - 41c6d0: c3 retq - 41c6d1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 41c6d8: 4c 89 f7 mov %r14,%rdi - 41c6db: 48 83 cf 01 or $0x1,%rdi - 41c6df: 49 89 7c 24 08 mov %rdi,0x8(%r12) - 41c6e4: 4b 83 4c 34 08 01 orq $0x1,0x8(%r12,%r14,1) - 41c6ea: 48 8b 79 f8 mov -0x8(%rcx),%rdi - 41c6ee: 83 e7 07 and $0x7,%edi - 41c6f1: e9 de fe ff ff jmpq 41c5d4 <_int_memalign+0xc4> - 41c6f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41c6fd: 00 00 00 - 41c700: 31 c0 xor %eax,%eax - 41c702: e9 1c ff ff ff jmpq 41c623 <_int_memalign+0x113> - 41c707: b9 c8 2e 4a 00 mov $0x4a2ec8,%ecx - 41c70c: ba 6f 11 00 00 mov $0x116f,%edx - 41c711: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 41c716: bf d8 28 4a 00 mov $0x4a28d8,%edi - 41c71b: e8 00 a7 ff ff callq 416e20 <__malloc_assert> - -000000000041c720 : - 41c720: 48 83 ff ff cmp $0xffffffffffffffff,%rdi - 41c724: 0f 84 26 01 00 00 je 41c850 - 41c72a: 53 push %rbx - 41c72b: be 01 00 00 00 mov $0x1,%esi - 41c730: 48 89 fb mov %rdi,%rbx - 41c733: 31 c0 xor %eax,%eax - 41c735: 83 3d 80 0a 2b 00 00 cmpl $0x0,0x2b0a80(%rip) # 6cd1bc <__libc_multiple_threads> - 41c73c: 74 0c je 41c74a - 41c73e: f0 0f b1 35 ba e0 2a lock cmpxchg %esi,0x2ae0ba(%rip) # 6ca800 - 41c745: 00 - 41c746: 75 0b jne 41c753 - 41c748: eb 23 jmp 41c76d - 41c74a: 0f b1 35 af e0 2a 00 cmpxchg %esi,0x2ae0af(%rip) # 6ca800 - 41c751: 74 1a je 41c76d - 41c753: 48 8d 3d a6 e0 2a 00 lea 0x2ae0a6(%rip),%rdi # 6ca800 - 41c75a: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41c761: e8 6a 5e 02 00 callq 4425d0 <__lll_lock_wait_private> - 41c766: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41c76d: e8 6e b3 ff ff callq 417ae0 - 41c772: 45 31 c0 xor %r8d,%r8d - 41c775: 85 c0 test %eax,%eax - 41c777: 78 11 js 41c78a - 41c779: 48 8d 73 01 lea 0x1(%rbx),%rsi - 41c77d: bf 00 a8 6c 00 mov $0x6ca800,%edi - 41c782: e8 b9 ed ff ff callq 41b540 <_int_malloc> - 41c787: 49 89 c0 mov %rax,%r8 - 41c78a: 83 3d 2b 0a 2b 00 00 cmpl $0x0,0x2b0a2b(%rip) # 6cd1bc <__libc_multiple_threads> - 41c791: 74 0b je 41c79e - 41c793: f0 ff 0d 66 e0 2a 00 lock decl 0x2ae066(%rip) # 6ca800 - 41c79a: 75 0a jne 41c7a6 - 41c79c: eb 22 jmp 41c7c0 - 41c79e: ff 0d 5c e0 2a 00 decl 0x2ae05c(%rip) # 6ca800 - 41c7a4: 74 1a je 41c7c0 - 41c7a6: 48 8d 3d 53 e0 2a 00 lea 0x2ae053(%rip),%rdi # 6ca800 - 41c7ad: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41c7b4: e8 47 5e 02 00 callq 442600 <__lll_unlock_wake_private> - 41c7b9: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41c7c0: 4d 85 c0 test %r8,%r8 - 41c7c3: 0f 84 9f 00 00 00 je 41c868 - 41c7c9: 49 8d 40 f0 lea -0x10(%r8),%rax - 41c7cd: 49 89 c1 mov %rax,%r9 - 41c7d0: 48 c1 e8 0b shr $0xb,%rax - 41c7d4: 49 c1 e9 03 shr $0x3,%r9 - 41c7d8: 41 31 c1 xor %eax,%r9d - 41c7db: b8 02 00 00 00 mov $0x2,%eax - 41c7e0: 41 80 f9 01 cmp $0x1,%r9b - 41c7e4: 44 0f 44 c8 cmove %eax,%r9d - 41c7e8: 49 8b 40 f8 mov -0x8(%r8),%rax - 41c7ec: 41 0f b6 f9 movzbl %r9b,%edi - 41c7f0: 48 89 c2 mov %rax,%rdx - 41c7f3: 48 83 e2 f8 and $0xfffffffffffffff8,%rdx - 41c7f7: 48 8d 4a f0 lea -0x10(%rdx),%rcx - 41c7fb: 48 83 ea 08 sub $0x8,%rdx - 41c7ff: a8 02 test $0x2,%al - 41c801: b8 ff 00 00 00 mov $0xff,%eax - 41c806: 48 0f 44 ca cmove %rdx,%rcx - 41c80a: 48 83 e9 01 sub $0x1,%rcx - 41c80e: 48 39 cb cmp %rcx,%rbx - 41c811: 73 2d jae 41c840 - 41c813: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41c818: 48 89 ca mov %rcx,%rdx - 41c81b: 48 29 da sub %rbx,%rdx - 41c81e: 48 81 fa ff 00 00 00 cmp $0xff,%rdx - 41c825: 48 0f 47 d0 cmova %rax,%rdx - 41c829: 48 8d 72 ff lea -0x1(%rdx),%rsi - 41c82d: 48 39 fa cmp %rdi,%rdx - 41c830: 48 0f 44 d6 cmove %rsi,%rdx - 41c834: 41 88 14 08 mov %dl,(%r8,%rcx,1) - 41c838: 48 29 d1 sub %rdx,%rcx - 41c83b: 48 39 cb cmp %rcx,%rbx - 41c83e: 72 d8 jb 41c818 - 41c840: 45 88 0c 18 mov %r9b,(%r8,%rbx,1) - 41c844: 4c 89 c0 mov %r8,%rax - 41c847: 5b pop %rbx - 41c848: c3 retq - 41c849: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 41c850: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 41c857: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) - 41c85e: 31 c0 xor %eax,%eax - 41c860: c3 retq - 41c861: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 41c868: 31 c0 xor %eax,%eax - 41c86a: 5b pop %rbx - 41c86b: c3 retq - 41c86c: 0f 1f 40 00 nopl 0x0(%rax) - -000000000041c870 : - 41c870: 55 push %rbp - 41c871: 53 push %rbx - 41c872: 48 89 f3 mov %rsi,%rbx - 41c875: 48 83 ec 08 sub $0x8,%rsp - 41c879: 48 83 ff 10 cmp $0x10,%rdi - 41c87d: 0f 86 8d 01 00 00 jbe 41ca10 - 41c883: 48 83 ff 1f cmp $0x1f,%rdi - 41c887: 0f 87 33 01 00 00 ja 41c9c0 - 41c88d: 48 83 fe bf cmp $0xffffffffffffffbf,%rsi - 41c891: 0f 87 a1 01 00 00 ja 41ca38 - 41c897: bd 20 00 00 00 mov $0x20,%ebp - 41c89c: be 01 00 00 00 mov $0x1,%esi - 41c8a1: 31 c0 xor %eax,%eax - 41c8a3: 83 3d 12 09 2b 00 00 cmpl $0x0,0x2b0912(%rip) # 6cd1bc <__libc_multiple_threads> - 41c8aa: 74 0c je 41c8b8 - 41c8ac: f0 0f b1 35 4c df 2a lock cmpxchg %esi,0x2adf4c(%rip) # 6ca800 - 41c8b3: 00 - 41c8b4: 75 0b jne 41c8c1 - 41c8b6: eb 23 jmp 41c8db - 41c8b8: 0f b1 35 41 df 2a 00 cmpxchg %esi,0x2adf41(%rip) # 6ca800 - 41c8bf: 74 1a je 41c8db - 41c8c1: 48 8d 3d 38 df 2a 00 lea 0x2adf38(%rip),%rdi # 6ca800 - 41c8c8: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41c8cf: e8 fc 5c 02 00 callq 4425d0 <__lll_lock_wait_private> - 41c8d4: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41c8db: e8 00 b2 ff ff callq 417ae0 - 41c8e0: 45 31 c0 xor %r8d,%r8d - 41c8e3: 85 c0 test %eax,%eax - 41c8e5: 78 14 js 41c8fb - 41c8e7: 48 8d 53 01 lea 0x1(%rbx),%rdx - 41c8eb: 48 89 ee mov %rbp,%rsi - 41c8ee: bf 00 a8 6c 00 mov $0x6ca800,%edi - 41c8f3: e8 18 fc ff ff callq 41c510 <_int_memalign> - 41c8f8: 49 89 c0 mov %rax,%r8 - 41c8fb: 83 3d ba 08 2b 00 00 cmpl $0x0,0x2b08ba(%rip) # 6cd1bc <__libc_multiple_threads> - 41c902: 74 0b je 41c90f - 41c904: f0 ff 0d f5 de 2a 00 lock decl 0x2adef5(%rip) # 6ca800 - 41c90b: 75 0a jne 41c917 - 41c90d: eb 22 jmp 41c931 - 41c90f: ff 0d eb de 2a 00 decl 0x2adeeb(%rip) # 6ca800 - 41c915: 74 1a je 41c931 - 41c917: 48 8d 3d e2 de 2a 00 lea 0x2adee2(%rip),%rdi # 6ca800 - 41c91e: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41c925: e8 d6 5c 02 00 callq 442600 <__lll_unlock_wake_private> - 41c92a: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41c931: 4d 85 c0 test %r8,%r8 - 41c934: 0f 84 16 01 00 00 je 41ca50 - 41c93a: 49 8d 40 f0 lea -0x10(%r8),%rax - 41c93e: 49 89 c1 mov %rax,%r9 - 41c941: 48 c1 e8 0b shr $0xb,%rax - 41c945: 49 c1 e9 03 shr $0x3,%r9 - 41c949: 41 31 c1 xor %eax,%r9d - 41c94c: b8 02 00 00 00 mov $0x2,%eax - 41c951: 41 80 f9 01 cmp $0x1,%r9b - 41c955: 44 0f 44 c8 cmove %eax,%r9d - 41c959: 49 8b 40 f8 mov -0x8(%r8),%rax - 41c95d: 41 0f b6 f9 movzbl %r9b,%edi - 41c961: 48 89 c2 mov %rax,%rdx - 41c964: 48 83 e2 f8 and $0xfffffffffffffff8,%rdx - 41c968: 48 8d 4a f0 lea -0x10(%rdx),%rcx - 41c96c: 48 83 ea 08 sub $0x8,%rdx - 41c970: a8 02 test $0x2,%al - 41c972: b8 ff 00 00 00 mov $0xff,%eax - 41c977: 48 0f 44 ca cmove %rdx,%rcx - 41c97b: 48 83 e9 01 sub $0x1,%rcx - 41c97f: 48 39 cb cmp %rcx,%rbx - 41c982: 73 2c jae 41c9b0 - 41c984: 0f 1f 40 00 nopl 0x0(%rax) - 41c988: 48 89 ca mov %rcx,%rdx - 41c98b: 48 29 da sub %rbx,%rdx - 41c98e: 48 81 fa ff 00 00 00 cmp $0xff,%rdx - 41c995: 48 0f 47 d0 cmova %rax,%rdx - 41c999: 48 8d 72 ff lea -0x1(%rdx),%rsi - 41c99d: 48 39 fa cmp %rdi,%rdx - 41c9a0: 48 0f 44 d6 cmove %rsi,%rdx - 41c9a4: 41 88 14 08 mov %dl,(%r8,%rcx,1) - 41c9a8: 48 29 d1 sub %rdx,%rcx - 41c9ab: 48 39 cb cmp %rcx,%rbx - 41c9ae: 72 d8 jb 41c988 - 41c9b0: 45 88 0c 18 mov %r9b,(%r8,%rbx,1) - 41c9b4: 4c 89 c0 mov %r8,%rax - 41c9b7: 48 83 c4 08 add $0x8,%rsp - 41c9bb: 5b pop %rbx - 41c9bc: 5d pop %rbp - 41c9bd: c3 retq - 41c9be: 66 90 xchg %ax,%ax - 41c9c0: 48 b8 00 00 00 00 00 movabs $0x8000000000000000,%rax - 41c9c7: 00 00 80 - 41c9ca: 48 39 c7 cmp %rax,%rdi - 41c9cd: 77 51 ja 41ca20 - 41c9cf: 48 c7 c0 df ff ff ff mov $0xffffffffffffffdf,%rax - 41c9d6: 48 29 f8 sub %rdi,%rax - 41c9d9: 48 39 c6 cmp %rax,%rsi - 41c9dc: 77 5a ja 41ca38 - 41c9de: 48 8d 47 ff lea -0x1(%rdi),%rax - 41c9e2: 48 85 f8 test %rdi,%rax - 41c9e5: 74 70 je 41ca57 - 41c9e7: 48 83 ff 20 cmp $0x20,%rdi - 41c9eb: bd 20 00 00 00 mov $0x20,%ebp - 41c9f0: 0f 84 a6 fe ff ff je 41c89c - 41c9f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41c9fd: 00 00 00 - 41ca00: 48 01 ed add %rbp,%rbp - 41ca03: 48 39 ef cmp %rbp,%rdi - 41ca06: 77 f8 ja 41ca00 - 41ca08: e9 8f fe ff ff jmpq 41c89c - 41ca0d: 0f 1f 00 nopl (%rax) - 41ca10: 48 83 c4 08 add $0x8,%rsp - 41ca14: 48 89 df mov %rbx,%rdi - 41ca17: 31 f6 xor %esi,%esi - 41ca19: 5b pop %rbx - 41ca1a: 5d pop %rbp - 41ca1b: e9 00 fd ff ff jmpq 41c720 - 41ca20: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 41ca27: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) - 41ca2e: 31 c0 xor %eax,%eax - 41ca30: e9 82 ff ff ff jmpq 41c9b7 - 41ca35: 0f 1f 00 nopl (%rax) - 41ca38: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 41ca3f: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) - 41ca46: 31 c0 xor %eax,%eax - 41ca48: e9 6a ff ff ff jmpq 41c9b7 - 41ca4d: 0f 1f 00 nopl (%rax) - 41ca50: 31 c0 xor %eax,%eax - 41ca52: e9 60 ff ff ff jmpq 41c9b7 - 41ca57: 48 89 fd mov %rdi,%rbp - 41ca5a: e9 3d fe ff ff jmpq 41c89c - 41ca5f: 90 nop - -000000000041ca60 <_int_realloc>: - 41ca60: 41 57 push %r15 - 41ca62: 41 56 push %r14 - 41ca64: 41 55 push %r13 - 41ca66: 41 54 push %r12 - 41ca68: 49 89 cd mov %rcx,%r13 - 41ca6b: 55 push %rbp - 41ca6c: 53 push %rbx - 41ca6d: 48 89 fd mov %rdi,%rbp - 41ca70: 48 89 f3 mov %rsi,%rbx - 41ca73: 48 83 ec 48 sub $0x48,%rsp - 41ca77: 48 8b 4e 08 mov 0x8(%rsi),%rcx - 41ca7b: 48 83 f9 10 cmp $0x10,%rcx - 41ca7f: 0f 86 03 02 00 00 jbe 41cc88 <_int_realloc+0x228> - 41ca85: 48 8b 87 80 08 00 00 mov 0x880(%rdi),%rax - 41ca8c: 48 39 d0 cmp %rdx,%rax - 41ca8f: 0f 86 9b 02 00 00 jbe 41cd30 <_int_realloc+0x2d0> - 41ca95: 49 89 cc mov %rcx,%r12 - 41ca98: 41 83 e4 02 and $0x2,%r12d - 41ca9c: 0f 85 77 06 00 00 jne 41d119 <_int_realloc+0x6b9> - 41caa2: 4c 8d 3c 16 lea (%rsi,%rdx,1),%r15 - 41caa6: 49 8b 77 08 mov 0x8(%r15),%rsi - 41caaa: 48 89 f7 mov %rsi,%rdi - 41caad: 48 83 e7 f8 and $0xfffffffffffffff8,%rdi - 41cab1: 48 39 f8 cmp %rdi,%rax - 41cab4: 0f 86 16 03 00 00 jbe 41cdd0 <_int_realloc+0x370> - 41caba: 48 83 fe 10 cmp $0x10,%rsi - 41cabe: 0f 86 0c 03 00 00 jbe 41cdd0 <_int_realloc+0x370> - 41cac4: 4c 39 ea cmp %r13,%rdx - 41cac7: 72 47 jb 41cb10 <_int_realloc+0xb0> - 41cac9: 48 89 d0 mov %rdx,%rax - 41cacc: 4c 29 e8 sub %r13,%rax - 41cacf: 48 83 f8 1f cmp $0x1f,%rax - 41cad3: 0f 87 07 02 00 00 ja 41cce0 <_int_realloc+0x280> - 41cad9: 83 e1 07 and $0x7,%ecx - 41cadc: b8 04 00 00 00 mov $0x4,%eax - 41cae1: 48 81 fd 00 a8 6c 00 cmp $0x6ca800,%rbp - 41cae8: 4c 0f 45 e0 cmovne %rax,%r12 - 41caec: 48 09 d1 or %rdx,%rcx - 41caef: 4c 09 e1 or %r12,%rcx - 41caf2: 48 89 4b 08 mov %rcx,0x8(%rbx) - 41caf6: 48 83 4c 13 08 01 orq $0x1,0x8(%rbx,%rdx,1) - 41cafc: 48 8d 43 10 lea 0x10(%rbx),%rax - 41cb00: 48 83 c4 48 add $0x48,%rsp - 41cb04: 5b pop %rbx - 41cb05: 5d pop %rbp - 41cb06: 41 5c pop %r12 - 41cb08: 41 5d pop %r13 - 41cb0a: 41 5e pop %r14 - 41cb0c: 41 5f pop %r15 - 41cb0e: c3 retq - 41cb0f: 90 nop - 41cb10: 4c 3b 7d 58 cmp 0x58(%rbp),%r15 - 41cb14: 0f 84 3e 03 00 00 je 41ce58 <_int_realloc+0x3f8> - 41cb1a: 49 8d 04 3f lea (%r15,%rdi,1),%rax - 41cb1e: f6 40 08 01 testb $0x1,0x8(%rax) - 41cb22: 0f 85 98 00 00 00 jne 41cbc0 <_int_realloc+0x160> - 41cb28: 4c 8d 0c 3a lea (%rdx,%rdi,1),%r9 - 41cb2c: 4d 39 cd cmp %r9,%r13 - 41cb2f: 0f 87 8b 00 00 00 ja 41cbc0 <_int_realloc+0x160> - 41cb35: 48 3b 38 cmp (%rax),%rdi - 41cb38: 0f 85 86 03 00 00 jne 41cec4 <_int_realloc+0x464> - 41cb3e: 4d 8b 77 10 mov 0x10(%r15),%r14 - 41cb42: 49 8b 47 18 mov 0x18(%r15),%rax - 41cb46: 4d 3b 7e 18 cmp 0x18(%r14),%r15 - 41cb4a: 0f 85 d0 02 00 00 jne 41ce20 <_int_realloc+0x3c0> - 41cb50: 4c 3b 78 10 cmp 0x10(%rax),%r15 - 41cb54: 0f 85 c6 02 00 00 jne 41ce20 <_int_realloc+0x3c0> - 41cb5a: 49 81 7f 08 ff 03 00 cmpq $0x3ff,0x8(%r15) - 41cb61: 00 - 41cb62: 49 89 46 18 mov %rax,0x18(%r14) - 41cb66: 4c 89 70 10 mov %r14,0x10(%rax) - 41cb6a: 76 44 jbe 41cbb0 <_int_realloc+0x150> - 41cb6c: 49 8b 47 20 mov 0x20(%r15),%rax - 41cb70: 48 85 c0 test %rax,%rax - 41cb73: 74 3b je 41cbb0 <_int_realloc+0x150> - 41cb75: 4c 3b 78 28 cmp 0x28(%rax),%r15 - 41cb79: 0f 85 4d 05 00 00 jne 41d0cc <_int_realloc+0x66c> - 41cb7f: 49 8b 57 28 mov 0x28(%r15),%rdx - 41cb83: 4c 3b 7a 20 cmp 0x20(%rdx),%r15 - 41cb87: 0f 85 3f 05 00 00 jne 41d0cc <_int_realloc+0x66c> - 41cb8d: 49 83 7e 20 00 cmpq $0x0,0x20(%r14) - 41cb92: 0f 84 5b 05 00 00 je 41d0f3 <_int_realloc+0x693> - 41cb98: 49 8b 57 28 mov 0x28(%r15),%rdx - 41cb9c: 48 89 50 28 mov %rdx,0x28(%rax) - 41cba0: 49 8b 57 28 mov 0x28(%r15),%rdx - 41cba4: 48 89 42 20 mov %rax,0x20(%rdx) - 41cba8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 41cbaf: 00 - 41cbb0: 48 8b 4b 08 mov 0x8(%rbx),%rcx - 41cbb4: 4c 89 ca mov %r9,%rdx - 41cbb7: e9 0d ff ff ff jmpq 41cac9 <_int_realloc+0x69> - 41cbbc: 0f 1f 40 00 nopl 0x0(%rax) - 41cbc0: 49 8d 75 f1 lea -0xf(%r13),%rsi - 41cbc4: 48 89 ef mov %rbp,%rdi - 41cbc7: 48 89 14 24 mov %rdx,(%rsp) - 41cbcb: e8 70 e9 ff ff callq 41b540 <_int_malloc> - 41cbd0: 48 85 c0 test %rax,%rax - 41cbd3: 49 89 c6 mov %rax,%r14 - 41cbd6: 0f 84 ef 00 00 00 je 41cccb <_int_realloc+0x26b> - 41cbdc: 48 8d 40 f0 lea -0x10(%rax),%rax - 41cbe0: 48 8b 14 24 mov (%rsp),%rdx - 41cbe4: 49 39 c7 cmp %rax,%r15 - 41cbe7: 0f 84 0b 02 00 00 je 41cdf8 <_int_realloc+0x398> - 41cbed: 48 83 ea 08 sub $0x8,%rdx - 41cbf1: 48 89 d0 mov %rdx,%rax - 41cbf4: 48 c1 e8 03 shr $0x3,%rax - 41cbf8: 83 f8 02 cmp $0x2,%eax - 41cbfb: 0f 86 4a 05 00 00 jbe 41d14b <_int_realloc+0x6eb> - 41cc01: 83 f8 09 cmp $0x9,%eax - 41cc04: 0f 87 d6 01 00 00 ja 41cde0 <_int_realloc+0x380> - 41cc0a: 48 8b 53 10 mov 0x10(%rbx),%rdx - 41cc0e: 83 f8 04 cmp $0x4,%eax - 41cc11: 49 89 16 mov %rdx,(%r14) - 41cc14: 48 8b 53 18 mov 0x18(%rbx),%rdx - 41cc18: 49 89 56 08 mov %rdx,0x8(%r14) - 41cc1c: 48 8b 53 20 mov 0x20(%rbx),%rdx - 41cc20: 49 89 56 10 mov %rdx,0x10(%r14) - 41cc24: 76 3a jbe 41cc60 <_int_realloc+0x200> - 41cc26: 48 8b 53 28 mov 0x28(%rbx),%rdx - 41cc2a: 83 f8 06 cmp $0x6,%eax - 41cc2d: 49 89 56 18 mov %rdx,0x18(%r14) - 41cc31: 48 8b 53 30 mov 0x30(%rbx),%rdx - 41cc35: 49 89 56 20 mov %rdx,0x20(%r14) - 41cc39: 76 25 jbe 41cc60 <_int_realloc+0x200> - 41cc3b: 48 8b 53 38 mov 0x38(%rbx),%rdx - 41cc3f: 83 f8 09 cmp $0x9,%eax - 41cc42: 49 89 56 28 mov %rdx,0x28(%r14) - 41cc46: 48 8b 53 40 mov 0x40(%rbx),%rdx - 41cc4a: 49 89 56 30 mov %rdx,0x30(%r14) - 41cc4e: 75 10 jne 41cc60 <_int_realloc+0x200> - 41cc50: 48 8b 43 48 mov 0x48(%rbx),%rax - 41cc54: 49 89 46 38 mov %rax,0x38(%r14) - 41cc58: 48 8b 43 50 mov 0x50(%rbx),%rax - 41cc5c: 49 89 46 40 mov %rax,0x40(%r14) - 41cc60: 48 89 de mov %rbx,%rsi - 41cc63: 48 89 ef mov %rbp,%rdi - 41cc66: ba 01 00 00 00 mov $0x1,%edx - 41cc6b: e8 50 cb ff ff callq 4197c0 <_int_free> - 41cc70: 48 83 c4 48 add $0x48,%rsp - 41cc74: 4c 89 f0 mov %r14,%rax - 41cc77: 5b pop %rbx - 41cc78: 5d pop %rbp - 41cc79: 41 5c pop %r12 - 41cc7b: 41 5d pop %r13 - 41cc7d: 41 5e pop %r14 - 41cc7f: 41 5f pop %r15 - 41cc81: c3 retq - 41cc82: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 41cc88: 48 85 ed test %rbp,%rbp - 41cc8b: 48 8d 7e 10 lea 0x10(%rsi),%rdi - 41cc8f: 44 8b 25 da da 2a 00 mov 0x2adada(%rip),%r12d # 6ca770 - 41cc96: 41 bd 67 21 4a 00 mov $0x4a2167,%r13d - 41cc9c: 0f 85 9f 00 00 00 jne 41cd41 <_int_realloc+0x2e1> - 41cca2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 41cca8: 44 89 e2 mov %r12d,%edx - 41ccab: 83 e2 05 and $0x5,%edx - 41ccae: 83 fa 05 cmp $0x5,%edx - 41ccb1: 0f 84 f1 01 00 00 je 41cea8 <_int_realloc+0x448> - 41ccb7: 41 f6 c4 01 test $0x1,%r12b - 41ccbb: 0f 85 8f 00 00 00 jne 41cd50 <_int_realloc+0x2f0> - 41ccc1: 41 83 e4 02 and $0x2,%r12d - 41ccc5: 0f 85 83 01 00 00 jne 41ce4e <_int_realloc+0x3ee> - 41cccb: 48 83 c4 48 add $0x48,%rsp - 41cccf: 31 c0 xor %eax,%eax - 41ccd1: 5b pop %rbx - 41ccd2: 5d pop %rbp - 41ccd3: 41 5c pop %r12 - 41ccd5: 41 5d pop %r13 - 41ccd7: 41 5e pop %r14 - 41ccd9: 41 5f pop %r15 - 41ccdb: c3 retq - 41ccdc: 0f 1f 40 00 nopl 0x0(%rax) - 41cce0: 83 e1 07 and $0x7,%ecx - 41cce3: 48 81 fd 00 a8 6c 00 cmp $0x6ca800,%rbp - 41ccea: 4a 8d 34 2b lea (%rbx,%r13,1),%rsi - 41ccee: 0f 84 24 01 00 00 je 41ce18 <_int_realloc+0x3b8> - 41ccf4: 49 83 cd 04 or $0x4,%r13 - 41ccf8: 41 bc 04 00 00 00 mov $0x4,%r12d - 41ccfe: 4c 09 e9 or %r13,%rcx - 41cd01: 48 89 4b 08 mov %rcx,0x8(%rbx) - 41cd05: 48 89 c1 mov %rax,%rcx - 41cd08: ba 01 00 00 00 mov $0x1,%edx - 41cd0d: 48 83 c9 01 or $0x1,%rcx - 41cd11: 48 89 ef mov %rbp,%rdi - 41cd14: 4c 09 e1 or %r12,%rcx - 41cd17: 48 89 4e 08 mov %rcx,0x8(%rsi) - 41cd1b: 48 83 4c 06 08 01 orq $0x1,0x8(%rsi,%rax,1) - 41cd21: e8 9a ca ff ff callq 4197c0 <_int_free> - 41cd26: e9 d1 fd ff ff jmpq 41cafc <_int_realloc+0x9c> - 41cd2b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41cd30: 41 bd 67 21 4a 00 mov $0x4a2167,%r13d - 41cd36: 44 8b 25 33 da 2a 00 mov 0x2ada33(%rip),%r12d # 6ca770 - 41cd3d: 48 8d 7b 10 lea 0x10(%rbx),%rdi - 41cd41: 83 4d 04 04 orl $0x4,0x4(%rbp) - 41cd45: e9 5e ff ff ff jmpq 41cca8 <_int_realloc+0x248> - 41cd4a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 41cd50: 48 8d 6c 24 20 lea 0x20(%rsp),%rbp - 41cd55: 48 8d 74 24 30 lea 0x30(%rsp),%rsi - 41cd5a: 31 c9 xor %ecx,%ecx - 41cd5c: ba 10 00 00 00 mov $0x10,%edx - 41cd61: c6 44 24 30 00 movb $0x0,0x30(%rsp) - 41cd66: e8 45 51 03 00 callq 451eb0 <_itoa_word> - 41cd6b: 48 39 e8 cmp %rbp,%rax - 41cd6e: 48 89 c3 mov %rax,%rbx - 41cd71: 76 25 jbe 41cd98 <_int_realloc+0x338> - 41cd73: 48 89 c2 mov %rax,%rdx - 41cd76: 48 89 c7 mov %rax,%rdi - 41cd79: be 30 00 00 00 mov $0x30,%esi - 41cd7e: 48 29 ea sub %rbp,%rdx - 41cd81: 4c 8d 70 ff lea -0x1(%rax),%r14 - 41cd85: 48 29 d7 sub %rdx,%rdi - 41cd88: e8 c3 35 fe ff callq 400350 <__rela_iplt_end+0x88> - 41cd8d: 48 8d 44 24 1f lea 0x1f(%rsp),%rax - 41cd92: 4c 29 f0 sub %r14,%rax - 41cd95: 48 01 c3 add %rax,%rbx - 41cd98: 48 8b 05 21 05 2b 00 mov 0x2b0521(%rip),%rax # 6cd2c0 <__libc_argv> - 41cd9f: ba 38 20 4a 00 mov $0x4a2038,%edx - 41cda4: 44 89 e7 mov %r12d,%edi - 41cda7: 49 89 d8 mov %rbx,%r8 - 41cdaa: 4c 89 e9 mov %r13,%rcx - 41cdad: be a8 23 4a 00 mov $0x4a23a8,%esi - 41cdb2: 48 8b 00 mov (%rax),%rax - 41cdb5: 48 85 c0 test %rax,%rax - 41cdb8: 48 0f 45 d0 cmovne %rax,%rdx - 41cdbc: 31 c0 xor %eax,%eax - 41cdbe: 83 e7 02 and $0x2,%edi - 41cdc1: e8 fa 47 ff ff callq 4115c0 <__libc_message> - 41cdc6: 31 c0 xor %eax,%eax - 41cdc8: e9 33 fd ff ff jmpq 41cb00 <_int_realloc+0xa0> - 41cdcd: 0f 1f 00 nopl (%rax) - 41cdd0: 41 bd 83 21 4a 00 mov $0x4a2183,%r13d - 41cdd6: e9 5b ff ff ff jmpq 41cd36 <_int_realloc+0x2d6> - 41cddb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41cde0: 48 8d 73 10 lea 0x10(%rbx),%rsi - 41cde4: 4c 89 f7 mov %r14,%rdi - 41cde7: e8 34 f2 00 00 callq 42c020 - 41cdec: e9 6f fe ff ff jmpq 41cc60 <_int_realloc+0x200> - 41cdf1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 41cdf8: 49 8b 46 f8 mov -0x8(%r14),%rax - 41cdfc: 48 83 e0 f8 and $0xfffffffffffffff8,%rax - 41ce00: 48 01 c2 add %rax,%rdx - 41ce03: 49 39 d5 cmp %rdx,%r13 - 41ce06: 0f 87 26 03 00 00 ja 41d132 <_int_realloc+0x6d2> - 41ce0c: 48 8b 4b 08 mov 0x8(%rbx),%rcx - 41ce10: e9 b4 fc ff ff jmpq 41cac9 <_int_realloc+0x69> - 41ce15: 0f 1f 00 nopl (%rax) - 41ce18: 4c 09 e9 or %r13,%rcx - 41ce1b: e9 e1 fe ff ff jmpq 41cd01 <_int_realloc+0x2a1> - 41ce20: 44 8b 15 49 d9 2a 00 mov 0x2ad949(%rip),%r10d # 6ca770 - 41ce27: 83 4d 04 04 orl $0x4,0x4(%rbp) - 41ce2b: 44 89 d0 mov %r10d,%eax - 41ce2e: 83 e0 05 and $0x5,%eax - 41ce31: 83 f8 05 cmp $0x5,%eax - 41ce34: 0f 84 4a 02 00 00 je 41d084 <_int_realloc+0x624> - 41ce3a: 41 f6 c2 01 test $0x1,%r10b - 41ce3e: 0f 85 d3 00 00 00 jne 41cf17 <_int_realloc+0x4b7> - 41ce44: 41 83 e2 02 and $0x2,%r10d - 41ce48: 0f 84 62 fd ff ff je 41cbb0 <_int_realloc+0x150> - 41ce4e: e8 ad 0d ff ff callq 40dc00 - 41ce53: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41ce58: 49 8d 45 20 lea 0x20(%r13),%rax - 41ce5c: 48 01 d7 add %rdx,%rdi - 41ce5f: 48 39 c7 cmp %rax,%rdi - 41ce62: 0f 82 58 fd ff ff jb 41cbc0 <_int_realloc+0x160> - 41ce68: 83 e1 07 and $0x7,%ecx - 41ce6b: b8 04 00 00 00 mov $0x4,%eax - 41ce70: 48 81 fd 00 a8 6c 00 cmp $0x6ca800,%rbp - 41ce77: 48 89 ca mov %rcx,%rdx - 41ce7a: 4c 0f 45 e0 cmovne %rax,%r12 - 41ce7e: 4a 8d 04 2b lea (%rbx,%r13,1),%rax - 41ce82: 4c 09 ea or %r13,%rdx - 41ce85: 4c 29 ef sub %r13,%rdi - 41ce88: 4c 09 e2 or %r12,%rdx - 41ce8b: 48 83 cf 01 or $0x1,%rdi - 41ce8f: 48 89 53 08 mov %rdx,0x8(%rbx) - 41ce93: 48 89 45 58 mov %rax,0x58(%rbp) - 41ce97: 48 89 78 08 mov %rdi,0x8(%rax) - 41ce9b: 48 8d 43 10 lea 0x10(%rbx),%rax - 41ce9f: e9 5c fc ff ff jmpq 41cb00 <_int_realloc+0xa0> - 41cea4: 0f 1f 40 00 nopl 0x0(%rax) - 41cea8: 44 89 e7 mov %r12d,%edi - 41ceab: 31 c0 xor %eax,%eax - 41cead: 4c 89 ea mov %r13,%rdx - 41ceb0: 83 e7 02 and $0x2,%edi - 41ceb3: be 3c ca 4b 00 mov $0x4bca3c,%esi - 41ceb8: e8 03 47 ff ff callq 4115c0 <__libc_message> - 41cebd: 31 c0 xor %eax,%eax - 41cebf: e9 3c fc ff ff jmpq 41cb00 <_int_realloc+0xa0> - 41cec4: 44 8b 15 a5 d8 2a 00 mov 0x2ad8a5(%rip),%r10d # 6ca770 - 41cecb: 83 4d 04 04 orl $0x4,0x4(%rbp) - 41cecf: 44 89 d0 mov %r10d,%eax - 41ced2: 83 e0 05 and $0x5,%eax - 41ced5: 83 f8 05 cmp $0x5,%eax - 41ced8: 0f 84 ca 01 00 00 je 41d0a8 <_int_realloc+0x648> - 41cede: 41 f6 c2 01 test $0x1,%r10b - 41cee2: 0f 85 e2 00 00 00 jne 41cfca <_int_realloc+0x56a> - 41cee8: 41 f6 c2 02 test $0x2,%r10b - 41ceec: 0f 85 5c ff ff ff jne 41ce4e <_int_realloc+0x3ee> - 41cef2: 4d 8b 77 10 mov 0x10(%r15),%r14 - 41cef6: 49 8b 47 18 mov 0x18(%r15),%rax - 41cefa: 4d 3b 7e 18 cmp 0x18(%r14),%r15 - 41cefe: 0f 85 40 ff ff ff jne 41ce44 <_int_realloc+0x3e4> - 41cf04: 4c 3b 78 10 cmp 0x10(%rax),%r15 - 41cf08: 0f 84 4c fc ff ff je 41cb5a <_int_realloc+0xfa> - 41cf0e: 83 4d 04 04 orl $0x4,0x4(%rbp) - 41cf12: e9 23 ff ff ff jmpq 41ce3a <_int_realloc+0x3da> - 41cf17: 4c 8d 74 24 20 lea 0x20(%rsp),%r14 - 41cf1c: 48 8d 74 24 30 lea 0x30(%rsp),%rsi - 41cf21: 31 c9 xor %ecx,%ecx - 41cf23: 4c 89 ff mov %r15,%rdi - 41cf26: ba 10 00 00 00 mov $0x10,%edx - 41cf2b: 44 89 54 24 08 mov %r10d,0x8(%rsp) - 41cf30: 4c 89 0c 24 mov %r9,(%rsp) - 41cf34: c6 44 24 30 00 movb $0x0,0x30(%rsp) - 41cf39: e8 72 4f 03 00 callq 451eb0 <_itoa_word> - 41cf3e: 4c 39 f0 cmp %r14,%rax - 41cf41: 49 89 c7 mov %rax,%r15 - 41cf44: 4c 8b 0c 24 mov (%rsp),%r9 - 41cf48: 44 8b 54 24 08 mov 0x8(%rsp),%r10d - 41cf4d: 76 3e jbe 41cf8d <_int_realloc+0x52d> - 41cf4f: 4c 89 fa mov %r15,%rdx - 41cf52: 48 8d 40 ff lea -0x1(%rax),%rax - 41cf56: 4c 89 ff mov %r15,%rdi - 41cf59: 4c 29 f2 sub %r14,%rdx - 41cf5c: be 30 00 00 00 mov $0x30,%esi - 41cf61: 44 89 54 24 10 mov %r10d,0x10(%rsp) - 41cf66: 48 29 d7 sub %rdx,%rdi - 41cf69: 4c 89 4c 24 08 mov %r9,0x8(%rsp) - 41cf6e: 48 89 04 24 mov %rax,(%rsp) - 41cf72: e8 d9 33 fe ff callq 400350 <__rela_iplt_end+0x88> - 41cf77: 48 8d 44 24 1f lea 0x1f(%rsp),%rax - 41cf7c: 48 2b 04 24 sub (%rsp),%rax - 41cf80: 44 8b 54 24 10 mov 0x10(%rsp),%r10d - 41cf85: 4c 8b 4c 24 08 mov 0x8(%rsp),%r9 - 41cf8a: 49 01 c7 add %rax,%r15 - 41cf8d: 48 8b 05 2c 03 2b 00 mov 0x2b032c(%rip),%rax # 6cd2c0 <__libc_argv> - 41cf94: 44 89 d7 mov %r10d,%edi - 41cf97: ba 38 20 4a 00 mov $0x4a2038,%edx - 41cf9c: 4d 89 f8 mov %r15,%r8 - 41cf9f: b9 95 20 4a 00 mov $0x4a2095,%ecx - 41cfa4: be a8 23 4a 00 mov $0x4a23a8,%esi - 41cfa9: 4c 89 0c 24 mov %r9,(%rsp) - 41cfad: 48 8b 00 mov (%rax),%rax - 41cfb0: 48 85 c0 test %rax,%rax - 41cfb3: 48 0f 45 d0 cmovne %rax,%rdx - 41cfb7: 83 e7 02 and $0x2,%edi - 41cfba: 31 c0 xor %eax,%eax - 41cfbc: e8 ff 45 ff ff callq 4115c0 <__libc_message> - 41cfc1: 4c 8b 0c 24 mov (%rsp),%r9 - 41cfc5: e9 e6 fb ff ff jmpq 41cbb0 <_int_realloc+0x150> - 41cfca: 4c 8d 74 24 20 lea 0x20(%rsp),%r14 - 41cfcf: 48 8d 74 24 30 lea 0x30(%rsp),%rsi - 41cfd4: 31 c9 xor %ecx,%ecx - 41cfd6: ba 10 00 00 00 mov $0x10,%edx - 41cfdb: 4c 89 ff mov %r15,%rdi - 41cfde: 44 89 54 24 08 mov %r10d,0x8(%rsp) - 41cfe3: 4c 89 0c 24 mov %r9,(%rsp) - 41cfe7: c6 44 24 30 00 movb $0x0,0x30(%rsp) - 41cfec: e8 bf 4e 03 00 callq 451eb0 <_itoa_word> - 41cff1: 4c 39 f0 cmp %r14,%rax - 41cff4: 49 89 c0 mov %rax,%r8 - 41cff7: 4c 8b 0c 24 mov (%rsp),%r9 - 41cffb: 44 8b 54 24 08 mov 0x8(%rsp),%r10d - 41d000: 76 48 jbe 41d04a <_int_realloc+0x5ea> - 41d002: 4c 89 c2 mov %r8,%rdx - 41d005: 4c 89 c7 mov %r8,%rdi - 41d008: 48 8d 40 ff lea -0x1(%rax),%rax - 41d00c: 4c 29 f2 sub %r14,%rdx - 41d00f: be 30 00 00 00 mov $0x30,%esi - 41d014: 44 89 54 24 1c mov %r10d,0x1c(%rsp) - 41d019: 48 29 d7 sub %rdx,%rdi - 41d01c: 4c 89 4c 24 10 mov %r9,0x10(%rsp) - 41d021: 4c 89 44 24 08 mov %r8,0x8(%rsp) - 41d026: 48 89 04 24 mov %rax,(%rsp) - 41d02a: e8 21 33 fe ff callq 400350 <__rela_iplt_end+0x88> - 41d02f: 48 8d 44 24 1f lea 0x1f(%rsp),%rax - 41d034: 48 2b 04 24 sub (%rsp),%rax - 41d038: 4c 8b 44 24 08 mov 0x8(%rsp),%r8 - 41d03d: 44 8b 54 24 1c mov 0x1c(%rsp),%r10d - 41d042: 4c 8b 4c 24 10 mov 0x10(%rsp),%r9 - 41d047: 49 01 c0 add %rax,%r8 - 41d04a: 48 8b 05 6f 02 2b 00 mov 0x2b026f(%rip),%rax # 6cd2c0 <__libc_argv> - 41d051: 44 89 d7 mov %r10d,%edi - 41d054: ba 38 20 4a 00 mov $0x4a2038,%edx - 41d059: b9 78 20 4a 00 mov $0x4a2078,%ecx - 41d05e: be a8 23 4a 00 mov $0x4a23a8,%esi - 41d063: 4c 89 0c 24 mov %r9,(%rsp) - 41d067: 48 8b 00 mov (%rax),%rax - 41d06a: 48 85 c0 test %rax,%rax - 41d06d: 48 0f 45 d0 cmovne %rax,%rdx - 41d071: 83 e7 02 and $0x2,%edi - 41d074: 31 c0 xor %eax,%eax - 41d076: e8 45 45 ff ff callq 4115c0 <__libc_message> - 41d07b: 4c 8b 0c 24 mov (%rsp),%r9 - 41d07f: e9 ba fa ff ff jmpq 41cb3e <_int_realloc+0xde> - 41d084: 44 89 d7 mov %r10d,%edi - 41d087: ba 95 20 4a 00 mov $0x4a2095,%edx - 41d08c: be 3c ca 4b 00 mov $0x4bca3c,%esi - 41d091: 83 e7 02 and $0x2,%edi - 41d094: 31 c0 xor %eax,%eax - 41d096: 4c 89 0c 24 mov %r9,(%rsp) - 41d09a: e8 21 45 ff ff callq 4115c0 <__libc_message> - 41d09f: 4c 8b 0c 24 mov (%rsp),%r9 - 41d0a3: e9 08 fb ff ff jmpq 41cbb0 <_int_realloc+0x150> - 41d0a8: 44 89 d7 mov %r10d,%edi - 41d0ab: ba 78 20 4a 00 mov $0x4a2078,%edx - 41d0b0: be 3c ca 4b 00 mov $0x4bca3c,%esi - 41d0b5: 83 e7 02 and $0x2,%edi - 41d0b8: 31 c0 xor %eax,%eax - 41d0ba: 4c 89 0c 24 mov %r9,(%rsp) - 41d0be: e8 fd 44 ff ff callq 4115c0 <__libc_message> - 41d0c3: 4c 8b 0c 24 mov (%rsp),%r9 - 41d0c7: e9 72 fa ff ff jmpq 41cb3e <_int_realloc+0xde> - 41d0cc: 8b 3d 9e d6 2a 00 mov 0x2ad69e(%rip),%edi # 6ca770 - 41d0d2: 48 89 e9 mov %rbp,%rcx - 41d0d5: 4c 89 fa mov %r15,%rdx - 41d0d8: be f0 23 4a 00 mov $0x4a23f0,%esi - 41d0dd: 4c 89 0c 24 mov %r9,(%rsp) - 41d0e1: e8 ca a1 ff ff callq 4172b0 - 41d0e6: 49 8b 47 20 mov 0x20(%r15),%rax - 41d0ea: 4c 8b 0c 24 mov (%rsp),%r9 - 41d0ee: e9 9a fa ff ff jmpq 41cb8d <_int_realloc+0x12d> - 41d0f3: 49 39 c7 cmp %rax,%r15 - 41d0f6: 74 6c je 41d164 <_int_realloc+0x704> - 41d0f8: 49 89 46 20 mov %rax,0x20(%r14) - 41d0fc: 49 8b 47 28 mov 0x28(%r15),%rax - 41d100: 49 89 46 28 mov %rax,0x28(%r14) - 41d104: 49 8b 47 20 mov 0x20(%r15),%rax - 41d108: 4c 89 70 28 mov %r14,0x28(%rax) - 41d10c: 49 8b 47 28 mov 0x28(%r15),%rax - 41d110: 4c 89 70 20 mov %r14,0x20(%rax) - 41d114: e9 97 fa ff ff jmpq 41cbb0 <_int_realloc+0x150> - 41d119: b9 58 2e 4a 00 mov $0x4a2e58,%ecx - 41d11e: ba a3 10 00 00 mov $0x10a3,%edx - 41d123: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 41d128: bf a0 21 4a 00 mov $0x4a21a0,%edi - 41d12d: e8 ee 9c ff ff callq 416e20 <__malloc_assert> - 41d132: b9 58 2e 4a 00 mov $0x4a2e58,%ecx - 41d137: ba 0f 11 00 00 mov $0x110f,%edx - 41d13c: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 41d141: bf 20 29 4a 00 mov $0x4a2920,%edi - 41d146: e8 d5 9c ff ff callq 416e20 <__malloc_assert> - 41d14b: b9 58 2e 4a 00 mov $0x4a2e58,%ecx - 41d150: ba eb 10 00 00 mov $0x10eb,%edx - 41d155: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 41d15a: bf b9 21 4a 00 mov $0x4a21b9,%edi - 41d15f: e8 bc 9c ff ff callq 416e20 <__malloc_assert> - 41d164: 4d 89 76 28 mov %r14,0x28(%r14) - 41d168: 4d 89 76 20 mov %r14,0x20(%r14) - 41d16c: e9 3f fa ff ff jmpq 41cbb0 <_int_realloc+0x150> - 41d171: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41d176: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41d17d: 00 00 00 - -000000000041d180 : - 41d180: 41 57 push %r15 - 41d182: 41 56 push %r14 - 41d184: 41 55 push %r13 - 41d186: 41 54 push %r12 - 41d188: 55 push %rbp - 41d189: 53 push %rbx - 41d18a: 48 83 ec 48 sub $0x48,%rsp - 41d18e: 48 83 fe ff cmp $0xffffffffffffffff,%rsi - 41d192: 0f 84 98 04 00 00 je 41d630 - 41d198: 48 85 ff test %rdi,%rdi - 41d19b: 48 89 fd mov %rdi,%rbp - 41d19e: 48 89 f3 mov %rsi,%rbx - 41d1a1: 0f 84 49 05 00 00 je 41d6f0 - 41d1a7: 48 85 f6 test %rsi,%rsi - 41d1aa: 0f 84 b0 04 00 00 je 41d660 - 41d1b0: be 01 00 00 00 mov $0x1,%esi - 41d1b5: 31 c0 xor %eax,%eax - 41d1b7: 83 3d fe ff 2a 00 00 cmpl $0x0,0x2afffe(%rip) # 6cd1bc <__libc_multiple_threads> - 41d1be: 74 0c je 41d1cc - 41d1c0: f0 0f b1 35 38 d6 2a lock cmpxchg %esi,0x2ad638(%rip) # 6ca800 - 41d1c7: 00 - 41d1c8: 75 0b jne 41d1d5 - 41d1ca: eb 23 jmp 41d1ef - 41d1cc: 0f b1 35 2d d6 2a 00 cmpxchg %esi,0x2ad62d(%rip) # 6ca800 - 41d1d3: 74 1a je 41d1ef - 41d1d5: 48 8d 3d 24 d6 2a 00 lea 0x2ad624(%rip),%rdi # 6ca800 - 41d1dc: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41d1e3: e8 e8 53 02 00 callq 4425d0 <__lll_lock_wait_private> - 41d1e8: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41d1ef: 40 f6 c5 0f test $0xf,%bpl - 41d1f3: 0f 85 37 01 00 00 jne 41d330 - 41d1f9: 48 8d 7d f0 lea -0x10(%rbp),%rdi - 41d1fd: 48 8b 45 f8 mov -0x8(%rbp),%rax - 41d201: 48 89 fe mov %rdi,%rsi - 41d204: 48 89 f9 mov %rdi,%rcx - 41d207: 48 c1 e9 0b shr $0xb,%rcx - 41d20b: 48 c1 ee 03 shr $0x3,%rsi - 41d20f: 48 89 c2 mov %rax,%rdx - 41d212: 31 ce xor %ecx,%esi - 41d214: 48 83 e2 f8 and $0xfffffffffffffff8,%rdx - 41d218: b9 02 00 00 00 mov $0x2,%ecx - 41d21d: 40 80 fe 01 cmp $0x1,%sil - 41d221: 0f 44 f1 cmove %ecx,%esi - 41d224: a8 02 test $0x2,%al - 41d226: 0f 84 d4 02 00 00 je 41d500 - 41d22c: 48 8b 05 4d df 2a 00 mov 0x2adf4d(%rip),%rax # 6cb180 <_dl_pagesize> - 41d233: 48 8d 48 ff lea -0x1(%rax),%rcx - 41d237: 48 89 e8 mov %rbp,%rax - 41d23a: 48 21 c8 and %rcx,%rax - 41d23d: 4c 8d 40 f0 lea -0x10(%rax),%r8 - 41d241: 49 f7 c0 ef ff ff ff test $0xffffffffffffffef,%r8 - 41d248: 74 36 je 41d280 - 41d24a: 4c 8d 40 ff lea -0x1(%rax),%r8 - 41d24e: 49 81 f8 fe 1f 00 00 cmp $0x1ffe,%r8 - 41d255: 77 29 ja 41d280 - 41d257: 4c 8d 40 c0 lea -0x40(%rax),%r8 - 41d25b: 49 f7 c0 bf ff ff ff test $0xffffffffffffffbf,%r8 - 41d262: 74 1c je 41d280 - 41d264: 4c 8d 80 00 ff ff ff lea -0x100(%rax),%r8 - 41d26b: 49 f7 c0 ff fe ff ff test $0xfffffffffffffeff,%r8 - 41d272: 0f 85 90 00 00 00 jne 41d308 - 41d278: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 41d27f: 00 - 41d280: 48 8b 45 f8 mov -0x8(%rbp),%rax - 41d284: 45 31 ed xor %r13d,%r13d - 41d287: 83 e0 03 and $0x3,%eax - 41d28a: 48 83 f8 02 cmp $0x2,%rax - 41d28e: 0f 85 9f 00 00 00 jne 41d333 - 41d294: 48 8b 45 f0 mov -0x10(%rbp),%rax - 41d298: 49 89 f8 mov %rdi,%r8 - 41d29b: 49 29 c0 sub %rax,%r8 - 41d29e: 48 01 d0 add %rdx,%rax - 41d2a1: 4c 09 c0 or %r8,%rax - 41d2a4: 48 85 c8 test %rcx,%rax - 41d2a7: 0f 85 86 00 00 00 jne 41d333 - 41d2ad: 48 83 ea 01 sub $0x1,%rdx - 41d2b1: 40 0f b6 f6 movzbl %sil,%esi - 41d2b5: 4c 8d 04 17 lea (%rdi,%rdx,1),%r8 - 41d2b9: 41 0f b6 00 movzbl (%r8),%eax - 41d2bd: 48 39 f0 cmp %rsi,%rax - 41d2c0: 48 89 c1 mov %rax,%rcx - 41d2c3: 74 34 je 41d2f9 - 41d2c5: 48 85 c0 test %rax,%rax - 41d2c8: 74 69 je 41d333 - 41d2ca: 48 8d 48 10 lea 0x10(%rax),%rcx - 41d2ce: 48 39 ca cmp %rcx,%rdx - 41d2d1: 73 13 jae 41d2e6 - 41d2d3: eb 5e jmp 41d333 - 41d2d5: 0f 1f 00 nopl (%rax) - 41d2d8: 48 85 c0 test %rax,%rax - 41d2db: 74 53 je 41d330 - 41d2dd: 48 8d 48 10 lea 0x10(%rax),%rcx - 41d2e1: 48 39 d1 cmp %rdx,%rcx - 41d2e4: 77 4a ja 41d330 - 41d2e6: 48 29 c2 sub %rax,%rdx - 41d2e9: 4c 8d 04 17 lea (%rdi,%rdx,1),%r8 - 41d2ed: 41 0f b6 00 movzbl (%r8),%eax - 41d2f1: 48 39 f0 cmp %rsi,%rax - 41d2f4: 48 89 c1 mov %rax,%rcx - 41d2f7: 75 df jne 41d2d8 - 41d2f9: f7 d1 not %ecx - 41d2fb: 4c 89 44 24 18 mov %r8,0x18(%rsp) - 41d300: 49 89 fd mov %rdi,%r13 - 41d303: 41 88 08 mov %cl,(%r8) - 41d306: eb 2b jmp 41d333 - 41d308: 4c 8d 80 00 fc ff ff lea -0x400(%rax),%r8 - 41d30f: 49 f7 c0 ff fb ff ff test $0xfffffffffffffbff,%r8 - 41d316: 0f 84 64 ff ff ff je 41d280 - 41d31c: 48 3d 00 10 00 00 cmp $0x1000,%rax - 41d322: 0f 84 58 ff ff ff je 41d280 - 41d328: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 41d32f: 00 - 41d330: 45 31 ed xor %r13d,%r13d - 41d333: 83 3d 82 fe 2a 00 00 cmpl $0x0,0x2afe82(%rip) # 6cd1bc <__libc_multiple_threads> - 41d33a: 74 0b je 41d347 - 41d33c: f0 ff 0d bd d4 2a 00 lock decl 0x2ad4bd(%rip) # 6ca800 - 41d343: 75 0a jne 41d34f - 41d345: eb 22 jmp 41d369 - 41d347: ff 0d b3 d4 2a 00 decl 0x2ad4b3(%rip) # 6ca800 - 41d34d: 74 1a je 41d369 - 41d34f: 48 8d 3d aa d4 2a 00 lea 0x2ad4aa(%rip),%rdi # 6ca800 - 41d356: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41d35d: e8 9e 52 02 00 callq 442600 <__lll_unlock_wake_private> - 41d362: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41d369: 4d 85 ed test %r13,%r13 - 41d36c: 0f 84 06 04 00 00 je 41d778 - 41d372: 4d 8b 75 08 mov 0x8(%r13),%r14 - 41d376: 4c 8d 4b 01 lea 0x1(%rbx),%r9 - 41d37a: 4c 89 4c 24 08 mov %r9,0x8(%rsp) - 41d37f: 49 83 e6 f8 and $0xfffffffffffffff8,%r14 - 41d383: 49 83 f9 bf cmp $0xffffffffffffffbf,%r9 - 41d387: 0f 87 a3 02 00 00 ja 41d630 - 41d38d: 4c 8d 7b 18 lea 0x18(%rbx),%r15 - 41d391: 41 bc 20 00 00 00 mov $0x20,%r12d - 41d397: be 01 00 00 00 mov $0x1,%esi - 41d39c: 4d 89 e2 mov %r12,%r10 - 41d39f: 4c 89 fa mov %r15,%rdx - 41d3a2: 48 83 e2 f0 and $0xfffffffffffffff0,%rdx - 41d3a6: 49 83 ff 20 cmp $0x20,%r15 - 41d3aa: 4c 0f 43 d2 cmovae %rdx,%r10 - 41d3ae: 31 c0 xor %eax,%eax - 41d3b0: 83 3d 05 fe 2a 00 00 cmpl $0x0,0x2afe05(%rip) # 6cd1bc <__libc_multiple_threads> - 41d3b7: 74 0c je 41d3c5 - 41d3b9: f0 0f b1 35 3f d4 2a lock cmpxchg %esi,0x2ad43f(%rip) # 6ca800 - 41d3c0: 00 - 41d3c1: 75 0b jne 41d3ce - 41d3c3: eb 23 jmp 41d3e8 - 41d3c5: 0f b1 35 34 d4 2a 00 cmpxchg %esi,0x2ad434(%rip) # 6ca800 - 41d3cc: 74 1a je 41d3e8 - 41d3ce: 48 8d 3d 2b d4 2a 00 lea 0x2ad42b(%rip),%rdi # 6ca800 - 41d3d5: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41d3dc: e8 ef 51 02 00 callq 4425d0 <__lll_lock_wait_private> - 41d3e1: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41d3e8: 41 f6 45 08 02 testb $0x2,0x8(%r13) - 41d3ed: 0f 85 dd 01 00 00 jne 41d5d0 - 41d3f3: 48 89 54 24 08 mov %rdx,0x8(%rsp) - 41d3f8: e8 e3 a6 ff ff callq 417ae0 - 41d3fd: 85 c0 test %eax,%eax - 41d3ff: 0f 88 4b 02 00 00 js 41d650 - 41d405: 48 8b 54 24 08 mov 0x8(%rsp),%rdx - 41d40a: 49 83 ff 20 cmp $0x20,%r15 - 41d40e: 4c 89 e1 mov %r12,%rcx - 41d411: 4c 89 ee mov %r13,%rsi - 41d414: bf 00 a8 6c 00 mov $0x6ca800,%edi - 41d419: 48 0f 43 ca cmovae %rdx,%rcx - 41d41d: 4c 89 f2 mov %r14,%rdx - 41d420: e8 3b f6 ff ff callq 41ca60 <_int_realloc> - 41d425: 48 89 c5 mov %rax,%rbp - 41d428: 48 85 ed test %rbp,%rbp - 41d42b: 0f 84 1f 02 00 00 je 41d650 - 41d431: 83 3d 84 fd 2a 00 00 cmpl $0x0,0x2afd84(%rip) # 6cd1bc <__libc_multiple_threads> - 41d438: 74 0b je 41d445 - 41d43a: f0 ff 0d bf d3 2a 00 lock decl 0x2ad3bf(%rip) # 6ca800 - 41d441: 75 0a jne 41d44d - 41d443: eb 22 jmp 41d467 - 41d445: ff 0d b5 d3 2a 00 decl 0x2ad3b5(%rip) # 6ca800 - 41d44b: 74 1a je 41d467 - 41d44d: 48 8d 3d ac d3 2a 00 lea 0x2ad3ac(%rip),%rdi # 6ca800 - 41d454: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41d45b: e8 a0 51 02 00 callq 442600 <__lll_unlock_wake_private> - 41d460: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41d467: 48 85 ed test %rbp,%rbp - 41d46a: 0f 84 90 02 00 00 je 41d700 - 41d470: 48 8d 45 f0 lea -0x10(%rbp),%rax - 41d474: be ff 00 00 00 mov $0xff,%esi - 41d479: 49 89 c0 mov %rax,%r8 - 41d47c: 48 c1 e8 0b shr $0xb,%rax - 41d480: 49 c1 e8 03 shr $0x3,%r8 - 41d484: 41 31 c0 xor %eax,%r8d - 41d487: b8 02 00 00 00 mov $0x2,%eax - 41d48c: 41 80 f8 01 cmp $0x1,%r8b - 41d490: 44 0f 44 c0 cmove %eax,%r8d - 41d494: 48 8b 45 f8 mov -0x8(%rbp),%rax - 41d498: 41 0f b6 f8 movzbl %r8b,%edi - 41d49c: 48 89 c2 mov %rax,%rdx - 41d49f: 48 83 e2 f8 and $0xfffffffffffffff8,%rdx - 41d4a3: 48 8d 4a f0 lea -0x10(%rdx),%rcx - 41d4a7: 48 83 ea 08 sub $0x8,%rdx - 41d4ab: a8 02 test $0x2,%al - 41d4ad: 48 0f 44 ca cmove %rdx,%rcx - 41d4b1: 48 83 e9 01 sub $0x1,%rcx - 41d4b5: 48 39 cb cmp %rcx,%rbx - 41d4b8: 73 2e jae 41d4e8 - 41d4ba: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 41d4c0: 48 89 ca mov %rcx,%rdx - 41d4c3: 48 29 da sub %rbx,%rdx - 41d4c6: 48 81 fa ff 00 00 00 cmp $0xff,%rdx - 41d4cd: 48 0f 47 d6 cmova %rsi,%rdx - 41d4d1: 48 8d 42 ff lea -0x1(%rdx),%rax - 41d4d5: 48 39 fa cmp %rdi,%rdx - 41d4d8: 48 0f 44 d0 cmove %rax,%rdx - 41d4dc: 88 54 0d 00 mov %dl,0x0(%rbp,%rcx,1) - 41d4e0: 48 29 d1 sub %rdx,%rcx - 41d4e3: 48 39 cb cmp %rcx,%rbx - 41d4e6: 72 d8 jb 41d4c0 - 41d4e8: 44 88 44 1d 00 mov %r8b,0x0(%rbp,%rbx,1) - 41d4ed: 48 89 e8 mov %rbp,%rax - 41d4f0: 48 83 c4 48 add $0x48,%rsp - 41d4f4: 5b pop %rbx - 41d4f5: 5d pop %rbp - 41d4f6: 41 5c pop %r12 - 41d4f8: 41 5d pop %r13 - 41d4fa: 41 5e pop %r14 - 41d4fc: 41 5f pop %r15 - 41d4fe: c3 retq - 41d4ff: 90 nop - 41d500: 8b 0d fe d2 2a 00 mov 0x2ad2fe(%rip),%ecx # 6ca804 - 41d506: 83 e1 02 and $0x2,%ecx - 41d509: 0f 84 f1 00 00 00 je 41d600 - 41d50f: 48 83 fa 1f cmp $0x1f,%rdx - 41d513: 0f 86 17 fe ff ff jbe 41d330 - 41d519: a8 08 test $0x8,%al - 41d51b: 0f 85 0f fe ff ff jne 41d330 - 41d521: f6 44 17 08 01 testb $0x1,0x8(%rdi,%rdx,1) - 41d526: 0f 84 04 fe ff ff je 41d330 - 41d52c: a8 01 test $0x1,%al - 41d52e: 75 2e jne 41d55e - 41d530: 48 8b 45 f0 mov -0x10(%rbp),%rax - 41d534: a8 0f test $0xf,%al - 41d536: 0f 85 f4 fd ff ff jne 41d330 - 41d53c: 85 c9 test %ecx,%ecx - 41d53e: 48 89 f9 mov %rdi,%rcx - 41d541: 0f 84 c0 01 00 00 je 41d707 - 41d547: 48 29 c1 sub %rax,%rcx - 41d54a: 48 8b 49 08 mov 0x8(%rcx),%rcx - 41d54e: 45 31 ed xor %r13d,%r13d - 41d551: 48 83 e1 f8 and $0xfffffffffffffff8,%rcx - 41d555: 48 39 c8 cmp %rcx,%rax - 41d558: 0f 85 d5 fd ff ff jne 41d333 - 41d55e: 48 83 c2 07 add $0x7,%rdx - 41d562: 40 0f b6 f6 movzbl %sil,%esi - 41d566: 4c 8d 04 17 lea (%rdi,%rdx,1),%r8 - 41d56a: 41 0f b6 00 movzbl (%r8),%eax - 41d56e: 48 39 c6 cmp %rax,%rsi - 41d571: 48 89 c1 mov %rax,%rcx - 41d574: 0f 84 7f fd ff ff je 41d2f9 - 41d57a: 48 85 c0 test %rax,%rax - 41d57d: 0f 84 ad fd ff ff je 41d330 - 41d583: 48 8d 48 10 lea 0x10(%rax),%rcx - 41d587: 48 39 ca cmp %rcx,%rdx - 41d58a: 73 22 jae 41d5ae - 41d58c: e9 9f fd ff ff jmpq 41d330 - 41d591: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 41d598: 48 85 c0 test %rax,%rax - 41d59b: 0f 84 8f fd ff ff je 41d330 - 41d5a1: 48 8d 48 10 lea 0x10(%rax),%rcx - 41d5a5: 48 39 d1 cmp %rdx,%rcx - 41d5a8: 0f 87 82 fd ff ff ja 41d330 - 41d5ae: 48 29 c2 sub %rax,%rdx - 41d5b1: 4c 8d 04 17 lea (%rdi,%rdx,1),%r8 - 41d5b5: 41 0f b6 00 movzbl (%r8),%eax - 41d5b9: 48 39 c6 cmp %rax,%rsi - 41d5bc: 48 89 c1 mov %rax,%rcx - 41d5bf: 75 d7 jne 41d598 - 41d5c1: e9 33 fd ff ff jmpq 41d2f9 - 41d5c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41d5cd: 00 00 00 - 41d5d0: 4c 89 d6 mov %r10,%rsi - 41d5d3: 4c 89 ef mov %r13,%rdi - 41d5d6: 4c 89 54 24 10 mov %r10,0x10(%rsp) - 41d5db: e8 40 9a ff ff callq 417020 - 41d5e0: 48 85 c0 test %rax,%rax - 41d5e3: 4c 8b 54 24 10 mov 0x10(%rsp),%r10 - 41d5e8: 4c 8b 4c 24 08 mov 0x8(%rsp),%r9 - 41d5ed: 0f 84 29 01 00 00 je 41d71c - 41d5f3: 48 8d 68 10 lea 0x10(%rax),%rbp - 41d5f7: e9 2c fe ff ff jmpq 41d428 - 41d5fc: 0f 1f 40 00 nopl 0x0(%rax) - 41d600: 4c 8b 05 e9 d1 2a 00 mov 0x2ad1e9(%rip),%r8 # 6ca7f0 - 41d607: 4c 39 c7 cmp %r8,%rdi - 41d60a: 0f 82 20 fd ff ff jb 41d330 - 41d610: 4c 03 05 69 da 2a 00 add 0x2ada69(%rip),%r8 # 6cb080 - 41d617: 4c 8d 0c 17 lea (%rdi,%rdx,1),%r9 - 41d61b: 4d 39 c1 cmp %r8,%r9 - 41d61e: 0f 82 eb fe ff ff jb 41d50f - 41d624: e9 07 fd ff ff jmpq 41d330 - 41d629: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 41d630: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 41d637: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) - 41d63e: 48 83 c4 48 add $0x48,%rsp - 41d642: 31 c0 xor %eax,%eax - 41d644: 5b pop %rbx - 41d645: 5d pop %rbp - 41d646: 41 5c pop %r12 - 41d648: 41 5d pop %r13 - 41d64a: 41 5e pop %r14 - 41d64c: 41 5f pop %r15 - 41d64e: c3 retq - 41d64f: 90 nop - 41d650: 48 8b 44 24 18 mov 0x18(%rsp),%rax - 41d655: 31 ed xor %ebp,%ebp - 41d657: f6 10 notb (%rax) - 41d659: e9 d3 fd ff ff jmpq 41d431 - 41d65e: 66 90 xchg %ax,%ax - 41d660: 31 f6 xor %esi,%esi - 41d662: e8 79 b3 ff ff callq 4189e0 - 41d667: 31 c0 xor %eax,%eax - 41d669: e9 82 fe ff ff jmpq 41d4f0 - 41d66e: 4c 8d 6c 24 20 lea 0x20(%rsp),%r13 - 41d673: 48 8d 74 24 30 lea 0x30(%rsp),%rsi - 41d678: 31 c9 xor %ecx,%ecx - 41d67a: 48 89 ef mov %rbp,%rdi - 41d67d: ba 10 00 00 00 mov $0x10,%edx - 41d682: c6 44 24 30 00 movb $0x0,0x30(%rsp) - 41d687: e8 24 48 03 00 callq 451eb0 <_itoa_word> - 41d68c: 4c 39 e8 cmp %r13,%rax - 41d68f: 48 89 c5 mov %rax,%rbp - 41d692: 76 25 jbe 41d6b9 - 41d694: 48 89 c2 mov %rax,%rdx - 41d697: 48 89 c7 mov %rax,%rdi - 41d69a: be 30 00 00 00 mov $0x30,%esi - 41d69f: 4c 29 ea sub %r13,%rdx - 41d6a2: 4c 8d 70 ff lea -0x1(%rax),%r14 - 41d6a6: 48 29 d7 sub %rdx,%rdi - 41d6a9: e8 a2 2c fe ff callq 400350 <__rela_iplt_end+0x88> - 41d6ae: 48 8d 44 24 1f lea 0x1f(%rsp),%rax - 41d6b3: 4c 29 f0 sub %r14,%rax - 41d6b6: 48 01 c5 add %rax,%rbp - 41d6b9: 48 8b 05 00 fc 2a 00 mov 0x2afc00(%rip),%rax # 6cd2c0 <__libc_argv> - 41d6c0: ba 38 20 4a 00 mov $0x4a2038,%edx - 41d6c5: 44 89 e7 mov %r12d,%edi - 41d6c8: 49 89 e8 mov %rbp,%r8 - 41d6cb: b9 c6 21 4a 00 mov $0x4a21c6,%ecx - 41d6d0: be a8 23 4a 00 mov $0x4a23a8,%esi - 41d6d5: 48 8b 00 mov (%rax),%rax - 41d6d8: 48 85 c0 test %rax,%rax - 41d6db: 48 0f 45 d0 cmovne %rax,%rdx - 41d6df: 83 e7 02 and $0x2,%edi - 41d6e2: 31 c0 xor %eax,%eax - 41d6e4: e8 d7 3e ff ff callq 4115c0 <__libc_message> - 41d6e9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 41d6f0: 31 f6 xor %esi,%esi - 41d6f2: 48 89 df mov %rbx,%rdi - 41d6f5: e8 26 f0 ff ff callq 41c720 - 41d6fa: e9 f1 fd ff ff jmpq 41d4f0 - 41d6ff: 90 nop - 41d700: 31 c0 xor %eax,%eax - 41d702: e9 e9 fd ff ff jmpq 41d4f0 - 41d707: 48 29 c1 sub %rax,%rcx - 41d70a: 48 3b 0d df d0 2a 00 cmp 0x2ad0df(%rip),%rcx # 6ca7f0 - 41d711: 0f 83 33 fe ff ff jae 41d54a - 41d717: e9 14 fc ff ff jmpq 41d330 - 41d71c: 49 8d 46 f8 lea -0x8(%r14),%rax - 41d720: 49 39 c2 cmp %rax,%r10 - 41d723: 0f 86 08 fd ff ff jbe 41d431 - 41d729: 4c 89 4c 24 08 mov %r9,0x8(%rsp) - 41d72e: e8 ad a3 ff ff callq 417ae0 - 41d733: 85 c0 test %eax,%eax - 41d735: 0f 88 15 ff ff ff js 41d650 - 41d73b: 4c 8b 4c 24 08 mov 0x8(%rsp),%r9 - 41d740: bf 00 a8 6c 00 mov $0x6ca800,%edi - 41d745: 4c 89 ce mov %r9,%rsi - 41d748: e8 f3 dd ff ff callq 41b540 <_int_malloc> - 41d74d: 48 85 c0 test %rax,%rax - 41d750: 49 89 c7 mov %rax,%r15 - 41d753: 0f 84 f7 fe ff ff je 41d650 - 41d759: 49 8d 56 f0 lea -0x10(%r14),%rdx - 41d75d: 48 89 ee mov %rbp,%rsi - 41d760: 48 89 c7 mov %rax,%rdi - 41d763: 4c 89 fd mov %r15,%rbp - 41d766: e8 b5 e8 00 00 callq 42c020 - 41d76b: 4c 89 ef mov %r13,%rdi - 41d76e: e8 7d a5 ff ff callq 417cf0 - 41d773: e9 b9 fc ff ff jmpq 41d431 - 41d778: 44 8b 25 f1 cf 2a 00 mov 0x2acff1(%rip),%r12d # 6ca770 - 41d77f: 83 0d 7e d0 2a 00 04 orl $0x4,0x2ad07e(%rip) # 6ca804 - 41d786: 44 89 e0 mov %r12d,%eax - 41d789: 83 e0 05 and $0x5,%eax - 41d78c: 83 f8 05 cmp $0x5,%eax - 41d78f: 74 1f je 41d7b0 - 41d791: 41 f6 c4 01 test $0x1,%r12b - 41d795: 0f 85 d3 fe ff ff jne 41d66e - 41d79b: 41 83 e4 02 and $0x2,%r12d - 41d79f: 0f 84 4b ff ff ff je 41d6f0 - 41d7a5: e8 56 04 ff ff callq 40dc00 - 41d7aa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 41d7b0: 44 89 e7 mov %r12d,%edi - 41d7b3: ba c6 21 4a 00 mov $0x4a21c6,%edx - 41d7b8: be 3c ca 4b 00 mov $0x4bca3c,%esi - 41d7bd: 83 e7 02 and $0x2,%edi - 41d7c0: 31 c0 xor %eax,%eax - 41d7c2: e8 f9 3d ff ff callq 4115c0 <__libc_message> - 41d7c7: e9 24 ff ff ff jmpq 41d6f0 - 41d7cc: 0f 1f 40 00 nopl 0x0(%rax) - -000000000041d7d0 <__malloc_fork_lock_parent>: - 41d7d0: 8b 05 8e cf 2a 00 mov 0x2acf8e(%rip),%eax # 6ca764 <__libc_malloc_initialized> - 41d7d6: 85 c0 test %eax,%eax - 41d7d8: 0f 8e 94 00 00 00 jle 41d872 <__malloc_fork_lock_parent+0xa2> - 41d7de: be 01 00 00 00 mov $0x1,%esi - 41d7e3: 31 c0 xor %eax,%eax - 41d7e5: 83 3d d0 f9 2a 00 00 cmpl $0x0,0x2af9d0(%rip) # 6cd1bc <__libc_multiple_threads> - 41d7ec: 74 0c je 41d7fa <__malloc_fork_lock_parent+0x2a> - 41d7ee: f0 0f b1 35 2a ee 2a lock cmpxchg %esi,0x2aee2a(%rip) # 6cc620 - 41d7f5: 00 - 41d7f6: 75 0b jne 41d803 <__malloc_fork_lock_parent+0x33> - 41d7f8: eb 23 jmp 41d81d <__malloc_fork_lock_parent+0x4d> - 41d7fa: 0f b1 35 1f ee 2a 00 cmpxchg %esi,0x2aee1f(%rip) # 6cc620 - 41d801: 74 1a je 41d81d <__malloc_fork_lock_parent+0x4d> - 41d803: 48 8d 3d 16 ee 2a 00 lea 0x2aee16(%rip),%rdi # 6cc620 - 41d80a: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41d811: e8 ba 4d 02 00 callq 4425d0 <__lll_lock_wait_private> - 41d816: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41d81d: ba 00 a8 6c 00 mov $0x6ca800,%edx - 41d822: 41 b9 01 00 00 00 mov $0x1,%r9d - 41d828: 45 31 c0 xor %r8d,%r8d - 41d82b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41d830: 44 89 ce mov %r9d,%esi - 41d833: 44 89 c0 mov %r8d,%eax - 41d836: 83 3d 7f f9 2a 00 00 cmpl $0x0,0x2af97f(%rip) # 6cd1bc <__libc_multiple_threads> - 41d83d: 74 08 je 41d847 <__malloc_fork_lock_parent+0x77> - 41d83f: f0 0f b1 32 lock cmpxchg %esi,(%rdx) - 41d843: 75 07 jne 41d84c <__malloc_fork_lock_parent+0x7c> - 41d845: eb 1b jmp 41d862 <__malloc_fork_lock_parent+0x92> - 41d847: 0f b1 32 cmpxchg %esi,(%rdx) - 41d84a: 74 16 je 41d862 <__malloc_fork_lock_parent+0x92> - 41d84c: 48 8d 3a lea (%rdx),%rdi - 41d84f: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41d856: e8 75 4d 02 00 callq 4425d0 <__lll_lock_wait_private> - 41d85b: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41d862: 48 8b 92 68 08 00 00 mov 0x868(%rdx),%rdx - 41d869: 48 81 fa 00 a8 6c 00 cmp $0x6ca800,%rdx - 41d870: 75 be jne 41d830 <__malloc_fork_lock_parent+0x60> - 41d872: f3 c3 repz retq - 41d874: 66 90 xchg %ax,%ax - 41d876: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41d87d: 00 00 00 - -000000000041d880 <__malloc_fork_unlock_parent>: - 41d880: 8b 05 de ce 2a 00 mov 0x2acede(%rip),%eax # 6ca764 <__libc_malloc_initialized> - 41d886: 85 c0 test %eax,%eax - 41d888: 7e 76 jle 41d900 <__malloc_fork_unlock_parent+0x80> - 41d88a: ba 00 a8 6c 00 mov $0x6ca800,%edx - 41d88f: 90 nop - 41d890: 83 3d 25 f9 2a 00 00 cmpl $0x0,0x2af925(%rip) # 6cd1bc <__libc_multiple_threads> - 41d897: 74 07 je 41d8a0 <__malloc_fork_unlock_parent+0x20> - 41d899: f0 ff 0a lock decl (%rdx) - 41d89c: 75 06 jne 41d8a4 <__malloc_fork_unlock_parent+0x24> - 41d89e: eb 1a jmp 41d8ba <__malloc_fork_unlock_parent+0x3a> - 41d8a0: ff 0a decl (%rdx) - 41d8a2: 74 16 je 41d8ba <__malloc_fork_unlock_parent+0x3a> - 41d8a4: 48 8d 3a lea (%rdx),%rdi - 41d8a7: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41d8ae: e8 4d 4d 02 00 callq 442600 <__lll_unlock_wake_private> - 41d8b3: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41d8ba: 48 8b 92 68 08 00 00 mov 0x868(%rdx),%rdx - 41d8c1: 48 81 fa 00 a8 6c 00 cmp $0x6ca800,%rdx - 41d8c8: 75 c6 jne 41d890 <__malloc_fork_unlock_parent+0x10> - 41d8ca: 83 3d eb f8 2a 00 00 cmpl $0x0,0x2af8eb(%rip) # 6cd1bc <__libc_multiple_threads> - 41d8d1: 74 0b je 41d8de <__malloc_fork_unlock_parent+0x5e> - 41d8d3: f0 ff 0d 46 ed 2a 00 lock decl 0x2aed46(%rip) # 6cc620 - 41d8da: 75 0a jne 41d8e6 <__malloc_fork_unlock_parent+0x66> - 41d8dc: eb 22 jmp 41d900 <__malloc_fork_unlock_parent+0x80> - 41d8de: ff 0d 3c ed 2a 00 decl 0x2aed3c(%rip) # 6cc620 - 41d8e4: 74 1a je 41d900 <__malloc_fork_unlock_parent+0x80> - 41d8e6: 48 8d 3d 33 ed 2a 00 lea 0x2aed33(%rip),%rdi # 6cc620 - 41d8ed: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41d8f4: e8 07 4d 02 00 callq 442600 <__lll_unlock_wake_private> - 41d8f9: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41d900: f3 c3 repz retq - 41d902: 0f 1f 40 00 nopl 0x0(%rax) - 41d906: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41d90d: 00 00 00 - -000000000041d910 <__malloc_fork_unlock_child>: - 41d910: 8b 05 4e ce 2a 00 mov 0x2ace4e(%rip),%eax # 6ca764 <__libc_malloc_initialized> - 41d916: 85 c0 test %eax,%eax - 41d918: 0f 8e 85 00 00 00 jle 41d9a3 <__malloc_fork_unlock_child+0x93> - 41d91e: 48 c7 c0 d8 ff ff ff mov $0xffffffffffffffd8,%rax - 41d925: c7 05 01 ed 2a 00 00 movl $0x0,0x2aed01(%rip) # 6cc630 - 41d92c: 00 00 00 - 41d92f: 64 48 8b 08 mov %fs:(%rax),%rcx - 41d933: 48 85 c9 test %rcx,%rcx - 41d936: 74 0b je 41d943 <__malloc_fork_unlock_child+0x33> - 41d938: 48 c7 81 78 08 00 00 movq $0x1,0x878(%rcx) - 41d93f: 01 00 00 00 - 41d943: 48 c7 05 da ec 2a 00 movq $0x0,0x2aecda(%rip) # 6cc628 - 41d94a: 00 00 00 00 - 41d94e: 31 f6 xor %esi,%esi - 41d950: 31 d2 xor %edx,%edx - 41d952: b8 00 a8 6c 00 mov $0x6ca800,%eax - 41d957: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 41d95e: 00 00 - 41d960: 48 39 c8 cmp %rcx,%rax - 41d963: c7 00 00 00 00 00 movl $0x0,(%rax) - 41d969: 74 1a je 41d985 <__malloc_fork_unlock_child+0x75> - 41d96b: 48 89 90 70 08 00 00 mov %rdx,0x870(%rax) - 41d972: 48 c7 80 78 08 00 00 movq $0x0,0x878(%rax) - 41d979: 00 00 00 00 - 41d97d: 48 89 c2 mov %rax,%rdx - 41d980: be 01 00 00 00 mov $0x1,%esi - 41d985: 48 8b 80 68 08 00 00 mov 0x868(%rax),%rax - 41d98c: 48 3d 00 a8 6c 00 cmp $0x6ca800,%rax - 41d992: 75 cc jne 41d960 <__malloc_fork_unlock_child+0x50> - 41d994: 40 84 f6 test %sil,%sil - 41d997: 75 0c jne 41d9a5 <__malloc_fork_unlock_child+0x95> - 41d999: c7 05 7d ec 2a 00 00 movl $0x0,0x2aec7d(%rip) # 6cc620 - 41d9a0: 00 00 00 - 41d9a3: f3 c3 repz retq - 41d9a5: 48 89 15 7c ec 2a 00 mov %rdx,0x2aec7c(%rip) # 6cc628 - 41d9ac: eb eb jmp 41d999 <__malloc_fork_unlock_child+0x89> - 41d9ae: 66 90 xchg %ax,%ax - -000000000041d9b0 <__malloc_check_init>: - 41d9b0: 8b 05 52 ec 2a 00 mov 0x2aec52(%rip),%eax # 6cc608 - 41d9b6: 85 c0 test %eax,%eax - 41d9b8: 75 3e jne 41d9f8 <__malloc_check_init+0x48> - 41d9ba: c7 05 48 ec 2a 00 01 movl $0x1,0x2aec48(%rip) # 6cc60c - 41d9c1: 00 00 00 - 41d9c4: 48 c7 05 b9 cd 2a 00 movq $0x41c720,0x2acdb9(%rip) # 6ca788 <__malloc_hook> - 41d9cb: 20 c7 41 00 - 41d9cf: 48 c7 05 0e ec 2a 00 movq $0x4189e0,0x2aec0e(%rip) # 6cc5e8 <__free_hook> - 41d9d6: e0 89 41 00 - 41d9da: 48 c7 05 9b cd 2a 00 movq $0x41d180,0x2acd9b(%rip) # 6ca780 <__realloc_hook> - 41d9e1: 80 d1 41 00 - 41d9e5: 48 c7 05 88 cd 2a 00 movq $0x41c870,0x2acd88(%rip) # 6ca778 <__memalign_hook> - 41d9ec: 70 c8 41 00 - 41d9f0: c3 retq - 41d9f1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 41d9f8: c7 05 06 ec 2a 00 00 movl $0x0,0x2aec06(%rip) # 6cc608 - 41d9ff: 00 00 00 - 41da02: c3 retq - 41da03: 0f 1f 00 nopl (%rax) - 41da06: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41da0d: 00 00 00 - -000000000041da10 <__libc_malloc>: - 41da10: 55 push %rbp - 41da11: 53 push %rbx - 41da12: 48 83 ec 08 sub $0x8,%rsp - 41da16: 48 8b 05 6b cd 2a 00 mov 0x2acd6b(%rip),%rax # 6ca788 <__malloc_hook> - 41da1d: 48 85 c0 test %rax,%rax - 41da20: 0f 85 42 01 00 00 jne 41db68 <__libc_malloc+0x158> - 41da26: 48 c7 c0 d8 ff ff ff mov $0xffffffffffffffd8,%rax - 41da2d: 48 89 fd mov %rdi,%rbp - 41da30: 64 48 8b 18 mov %fs:(%rax),%rbx - 41da34: 48 85 db test %rbx,%rbx - 41da37: 74 0c je 41da45 <__libc_malloc+0x35> - 41da39: 8b 43 04 mov 0x4(%rbx),%eax - 41da3c: 83 e0 04 and $0x4,%eax - 41da3f: 0f 84 93 00 00 00 je 41dad8 <__libc_malloc+0xc8> - 41da45: e8 16 97 ff ff callq 417160 - 41da4a: 48 85 c0 test %rax,%rax - 41da4d: 48 89 c3 mov %rax,%rbx - 41da50: 0f 84 ba 00 00 00 je 41db10 <__libc_malloc+0x100> - 41da56: 48 89 ee mov %rbp,%rsi - 41da59: 48 89 df mov %rbx,%rdi - 41da5c: e8 df da ff ff callq 41b540 <_int_malloc> - 41da61: 48 85 c0 test %rax,%rax - 41da64: 48 89 c2 mov %rax,%rdx - 41da67: 0f 84 cb 00 00 00 je 41db38 <__libc_malloc+0x128> - 41da6d: 83 3d 48 f7 2a 00 00 cmpl $0x0,0x2af748(%rip) # 6cd1bc <__libc_multiple_threads> - 41da74: 74 07 je 41da7d <__libc_malloc+0x6d> - 41da76: f0 ff 0b lock decl (%rbx) - 41da79: 75 06 jne 41da81 <__libc_malloc+0x71> - 41da7b: eb 1a jmp 41da97 <__libc_malloc+0x87> - 41da7d: ff 0b decl (%rbx) - 41da7f: 74 16 je 41da97 <__libc_malloc+0x87> - 41da81: 48 8d 3b lea (%rbx),%rdi - 41da84: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41da8b: e8 70 4b 02 00 callq 442600 <__lll_unlock_wake_private> - 41da90: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41da97: 48 85 d2 test %rdx,%rdx - 41da9a: 0f 84 d8 00 00 00 je 41db78 <__libc_malloc+0x168> - 41daa0: 48 8b 42 f8 mov -0x8(%rdx),%rax - 41daa4: a8 02 test $0x2,%al - 41daa6: 75 1f jne 41dac7 <__libc_malloc+0xb7> - 41daa8: a8 04 test $0x4,%al - 41daaa: b9 00 a8 6c 00 mov $0x6ca800,%ecx - 41daaf: 74 0d je 41dabe <__libc_malloc+0xae> - 41dab1: 48 8d 42 f0 lea -0x10(%rdx),%rax - 41dab5: 48 25 00 00 00 fc and $0xfffffffffc000000,%rax - 41dabb: 48 8b 08 mov (%rax),%rcx - 41dabe: 48 39 d9 cmp %rbx,%rcx - 41dac1: 0f 85 b8 00 00 00 jne 41db7f <__libc_malloc+0x16f> - 41dac7: 48 89 d0 mov %rdx,%rax - 41daca: 48 83 c4 08 add $0x8,%rsp - 41dace: 5b pop %rbx - 41dacf: 5d pop %rbp - 41dad0: c3 retq - 41dad1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 41dad8: be 01 00 00 00 mov $0x1,%esi - 41dadd: 83 3d d8 f6 2a 00 00 cmpl $0x0,0x2af6d8(%rip) # 6cd1bc <__libc_multiple_threads> - 41dae4: 74 08 je 41daee <__libc_malloc+0xde> - 41dae6: f0 0f b1 33 lock cmpxchg %esi,(%rbx) - 41daea: 75 07 jne 41daf3 <__libc_malloc+0xe3> - 41daec: eb 1b jmp 41db09 <__libc_malloc+0xf9> - 41daee: 0f b1 33 cmpxchg %esi,(%rbx) - 41daf1: 74 16 je 41db09 <__libc_malloc+0xf9> - 41daf3: 48 8d 3b lea (%rbx),%rdi - 41daf6: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41dafd: e8 ce 4a 02 00 callq 4425d0 <__lll_lock_wait_private> - 41db02: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41db09: e9 48 ff ff ff jmpq 41da56 <__libc_malloc+0x46> - 41db0e: 66 90 xchg %ax,%ax - 41db10: 31 f6 xor %esi,%esi - 41db12: 48 89 ef mov %rbp,%rdi - 41db15: e8 36 99 ff ff callq 417450 - 41db1a: 48 89 ee mov %rbp,%rsi - 41db1d: 48 89 c7 mov %rax,%rdi - 41db20: 48 89 c3 mov %rax,%rbx - 41db23: e8 18 da ff ff callq 41b540 <_int_malloc> - 41db28: 48 85 c0 test %rax,%rax - 41db2b: 48 89 c2 mov %rax,%rdx - 41db2e: 75 25 jne 41db55 <__libc_malloc+0x145> - 41db30: 48 85 db test %rbx,%rbx - 41db33: 74 20 je 41db55 <__libc_malloc+0x145> - 41db35: 0f 1f 00 nopl (%rax) - 41db38: 90 nop - 41db39: 48 89 df mov %rbx,%rdi - 41db3c: 48 89 ee mov %rbp,%rsi - 41db3f: e8 ac 9e ff ff callq 4179f0 - 41db44: 48 89 ee mov %rbp,%rsi - 41db47: 48 89 c7 mov %rax,%rdi - 41db4a: 48 89 c3 mov %rax,%rbx - 41db4d: e8 ee d9 ff ff callq 41b540 <_int_malloc> - 41db52: 48 89 c2 mov %rax,%rdx - 41db55: 48 85 db test %rbx,%rbx - 41db58: 0f 85 0f ff ff ff jne 41da6d <__libc_malloc+0x5d> - 41db5e: e9 34 ff ff ff jmpq 41da97 <__libc_malloc+0x87> - 41db63: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41db68: 48 8b 74 24 18 mov 0x18(%rsp),%rsi - 41db6d: 48 83 c4 08 add $0x8,%rsp - 41db71: 5b pop %rbx - 41db72: 5d pop %rbp - 41db73: ff e0 jmpq *%rax - 41db75: 0f 1f 00 nopl (%rax) - 41db78: 31 c0 xor %eax,%eax - 41db7a: e9 4b ff ff ff jmpq 41daca <__libc_malloc+0xba> - 41db7f: b9 48 2e 4a 00 mov $0x4a2e48,%ecx - 41db84: ba 6f 0b 00 00 mov $0xb6f,%edx - 41db89: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 41db8e: bf 58 29 4a 00 mov $0x4a2958,%edi - 41db93: e8 88 92 ff ff callq 416e20 <__malloc_assert> - 41db98: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 41db9f: 00 - -000000000041dba0 <__malloc_get_state>: - 41dba0: 53 push %rbx - 41dba1: bf a8 08 00 00 mov $0x8a8,%edi - 41dba6: e8 65 fe ff ff callq 41da10 <__libc_malloc> - 41dbab: 48 85 c0 test %rax,%rax - 41dbae: 0f 84 f5 01 00 00 je 41dda9 <__malloc_get_state+0x209> - 41dbb4: 48 89 c3 mov %rax,%rbx - 41dbb7: be 01 00 00 00 mov $0x1,%esi - 41dbbc: 31 c0 xor %eax,%eax - 41dbbe: 83 3d f7 f5 2a 00 00 cmpl $0x0,0x2af5f7(%rip) # 6cd1bc <__libc_multiple_threads> - 41dbc5: 74 0c je 41dbd3 <__malloc_get_state+0x33> - 41dbc7: f0 0f b1 35 31 cc 2a lock cmpxchg %esi,0x2acc31(%rip) # 6ca800 - 41dbce: 00 - 41dbcf: 75 0b jne 41dbdc <__malloc_get_state+0x3c> - 41dbd1: eb 23 jmp 41dbf6 <__malloc_get_state+0x56> - 41dbd3: 0f b1 35 26 cc 2a 00 cmpxchg %esi,0x2acc26(%rip) # 6ca800 - 41dbda: 74 1a je 41dbf6 <__malloc_get_state+0x56> - 41dbdc: 48 8d 3d 1d cc 2a 00 lea 0x2acc1d(%rip),%rdi # 6ca800 - 41dbe3: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41dbea: e8 e1 49 02 00 callq 4425d0 <__lll_lock_wait_private> - 41dbef: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41dbf6: bf 00 a8 6c 00 mov $0x6ca800,%edi - 41dbfb: e8 30 a2 ff ff callq 417e30 - 41dc00: 48 8b 05 51 cc 2a 00 mov 0x2acc51(%rip),%rax # 6ca858 - 41dc07: 48 c7 03 41 45 4c 44 movq $0x444c4541,(%rbx) - 41dc0e: ba 58 a8 6c 00 mov $0x6ca858,%edx - 41dc13: 48 c7 43 08 04 00 00 movq $0x4,0x8(%rbx) - 41dc1a: 00 - 41dc1b: 48 c7 43 10 00 00 00 movq $0x0,0x10(%rbx) - 41dc22: 00 - 41dc23: 48 8d 4b 38 lea 0x38(%rbx),%rcx - 41dc27: 48 c7 43 18 00 00 00 movq $0x0,0x18(%rbx) - 41dc2e: 00 - 41dc2f: 48 c7 43 28 00 00 00 movq $0x0,0x28(%rbx) - 41dc36: 00 - 41dc37: 48 89 43 20 mov %rax,0x20(%rbx) - 41dc3b: eb 1f jmp 41dc5c <__malloc_get_state+0xbc> - 41dc3d: 0f 1f 00 nopl (%rax) - 41dc40: 48 89 71 f8 mov %rsi,-0x8(%rcx) - 41dc44: 48 8b 72 18 mov 0x18(%rdx),%rsi - 41dc48: 48 89 31 mov %rsi,(%rcx) - 41dc4b: 48 83 c2 10 add $0x10,%rdx - 41dc4f: 48 83 c1 10 add $0x10,%rcx - 41dc53: 48 81 fa 48 b0 6c 00 cmp $0x6cb048,%rdx - 41dc5a: 74 24 je 41dc80 <__malloc_get_state+0xe0> - 41dc5c: 48 8b 72 10 mov 0x10(%rdx),%rsi - 41dc60: 48 39 f2 cmp %rsi,%rdx - 41dc63: 75 db jne 41dc40 <__malloc_get_state+0xa0> - 41dc65: 48 c7 01 00 00 00 00 movq $0x0,(%rcx) - 41dc6c: 48 c7 41 f8 00 00 00 movq $0x0,-0x8(%rcx) - 41dc73: 00 - 41dc74: eb d5 jmp 41dc4b <__malloc_get_state+0xab> - 41dc76: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41dc7d: 00 00 00 - 41dc80: 48 8b 05 69 cb 2a 00 mov 0x2acb69(%rip),%rax # 6ca7f0 - 41dc87: 48 89 83 20 08 00 00 mov %rax,0x820(%rbx) - 41dc8e: 48 8b 05 eb d3 2a 00 mov 0x2ad3eb(%rip),%rax # 6cb080 - 41dc95: 89 83 28 08 00 00 mov %eax,0x828(%rbx) - 41dc9b: 48 8b 05 fe ca 2a 00 mov 0x2acafe(%rip),%rax # 6ca7a0 - 41dca2: 48 89 83 30 08 00 00 mov %rax,0x830(%rbx) - 41dca9: 48 8b 05 f8 ca 2a 00 mov 0x2acaf8(%rip),%rax # 6ca7a8 - 41dcb0: 48 89 83 38 08 00 00 mov %rax,0x838(%rbx) - 41dcb7: 8b 05 0f cb 2a 00 mov 0x2acb0f(%rip),%eax # 6ca7cc - 41dcbd: 89 83 40 08 00 00 mov %eax,0x840(%rbx) - 41dcc3: 48 8b 05 e6 ca 2a 00 mov 0x2acae6(%rip),%rax # 6ca7b0 - 41dcca: 48 89 83 48 08 00 00 mov %rax,0x848(%rbx) - 41dcd1: 8b 05 99 ca 2a 00 mov 0x2aca99(%rip),%eax # 6ca770 - 41dcd7: 89 83 50 08 00 00 mov %eax,0x850(%rbx) - 41dcdd: 48 8b 05 a4 d3 2a 00 mov 0x2ad3a4(%rip),%rax # 6cb088 - 41dce4: 48 c7 83 60 08 00 00 movq $0x0,0x860(%rbx) - 41dceb: 00 00 00 00 - 41dcef: 48 89 83 58 08 00 00 mov %rax,0x858(%rbx) - 41dcf6: 8b 05 cc ca 2a 00 mov 0x2acacc(%rip),%eax # 6ca7c8 - 41dcfc: 89 83 68 08 00 00 mov %eax,0x868(%rbx) - 41dd02: 8b 05 c8 ca 2a 00 mov 0x2acac8(%rip),%eax # 6ca7d0 - 41dd08: 89 83 6c 08 00 00 mov %eax,0x86c(%rbx) - 41dd0e: 48 8b 05 c3 ca 2a 00 mov 0x2acac3(%rip),%rax # 6ca7d8 - 41dd15: 48 89 83 70 08 00 00 mov %rax,0x870(%rbx) - 41dd1c: 48 8b 05 bd ca 2a 00 mov 0x2acabd(%rip),%rax # 6ca7e0 - 41dd23: 48 89 83 78 08 00 00 mov %rax,0x878(%rbx) - 41dd2a: 8b 05 dc e8 2a 00 mov 0x2ae8dc(%rip),%eax # 6cc60c - 41dd30: 89 83 80 08 00 00 mov %eax,0x880(%rbx) - 41dd36: 48 8b 05 fb e8 2a 00 mov 0x2ae8fb(%rip),%rax # 6cc638 - 41dd3d: 48 89 83 88 08 00 00 mov %rax,0x888(%rbx) - 41dd44: 48 8b 05 6d ca 2a 00 mov 0x2aca6d(%rip),%rax # 6ca7b8 - 41dd4b: 48 89 83 90 08 00 00 mov %rax,0x890(%rbx) - 41dd52: 48 8b 05 67 ca 2a 00 mov 0x2aca67(%rip),%rax # 6ca7c0 - 41dd59: 48 89 83 98 08 00 00 mov %rax,0x898(%rbx) - 41dd60: 48 8b 05 01 ca 2a 00 mov 0x2aca01(%rip),%rax # 6ca768 - 41dd67: 48 89 83 a0 08 00 00 mov %rax,0x8a0(%rbx) - 41dd6e: 83 3d 47 f4 2a 00 00 cmpl $0x0,0x2af447(%rip) # 6cd1bc <__libc_multiple_threads> - 41dd75: 74 0b je 41dd82 <__malloc_get_state+0x1e2> - 41dd77: f0 ff 0d 82 ca 2a 00 lock decl 0x2aca82(%rip) # 6ca800 - 41dd7e: 75 0a jne 41dd8a <__malloc_get_state+0x1ea> - 41dd80: eb 22 jmp 41dda4 <__malloc_get_state+0x204> - 41dd82: ff 0d 78 ca 2a 00 decl 0x2aca78(%rip) # 6ca800 - 41dd88: 74 1a je 41dda4 <__malloc_get_state+0x204> - 41dd8a: 48 8d 3d 6f ca 2a 00 lea 0x2aca6f(%rip),%rdi # 6ca800 - 41dd91: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41dd98: e8 63 48 02 00 callq 442600 <__lll_unlock_wake_private> - 41dd9d: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41dda4: 48 89 d8 mov %rbx,%rax - 41dda7: 5b pop %rbx - 41dda8: c3 retq - 41dda9: 31 c0 xor %eax,%eax - 41ddab: 5b pop %rbx - 41ddac: c3 retq - 41ddad: 0f 1f 00 nopl (%rax) - -000000000041ddb0 <__cfree>: - 41ddb0: 41 55 push %r13 - 41ddb2: 41 54 push %r12 - 41ddb4: 55 push %rbp - 41ddb5: 53 push %rbx - 41ddb6: 48 83 ec 28 sub $0x28,%rsp - 41ddba: 48 8b 05 27 e8 2a 00 mov 0x2ae827(%rip),%rax # 6cc5e8 <__free_hook> - 41ddc1: 48 85 c0 test %rax,%rax - 41ddc4: 0f 85 c6 00 00 00 jne 41de90 <__cfree+0xe0> - 41ddca: 48 85 ff test %rdi,%rdi - 41ddcd: 74 28 je 41ddf7 <__cfree+0x47> - 41ddcf: 48 8b 47 f8 mov -0x8(%rdi),%rax - 41ddd3: 48 8d 77 f0 lea -0x10(%rdi),%rsi - 41ddd7: a8 02 test $0x2,%al - 41ddd9: 75 2d jne 41de08 <__cfree+0x58> - 41dddb: a8 04 test $0x4,%al - 41dddd: bf 00 a8 6c 00 mov $0x6ca800,%edi - 41dde2: 74 0c je 41ddf0 <__cfree+0x40> - 41dde4: 48 89 f0 mov %rsi,%rax - 41dde7: 48 25 00 00 00 fc and $0xfffffffffc000000,%rax - 41dded: 48 8b 38 mov (%rax),%rdi - 41ddf0: 31 d2 xor %edx,%edx - 41ddf2: e8 c9 b9 ff ff callq 4197c0 <_int_free> - 41ddf7: 48 83 c4 28 add $0x28,%rsp - 41ddfb: 5b pop %rbx - 41ddfc: 5d pop %rbp - 41ddfd: 41 5c pop %r12 - 41ddff: 41 5d pop %r13 - 41de01: c3 retq - 41de02: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 41de08: 8b 15 c6 c9 2a 00 mov 0x2ac9c6(%rip),%edx # 6ca7d4 - 41de0e: 85 d2 test %edx,%edx - 41de10: 75 2e jne 41de40 <__cfree+0x90> - 41de12: 48 3b 05 97 c9 2a 00 cmp 0x2ac997(%rip),%rax # 6ca7b0 - 41de19: 76 25 jbe 41de40 <__cfree+0x90> - 41de1b: 48 3d 00 00 00 02 cmp $0x2000000,%rax - 41de21: 77 1d ja 41de40 <__cfree+0x90> - 41de23: 48 83 e0 f8 and $0xfffffffffffffff8,%rax - 41de27: 48 8d 14 00 lea (%rax,%rax,1),%rdx - 41de2b: 48 89 05 7e c9 2a 00 mov %rax,0x2ac97e(%rip) # 6ca7b0 - 41de32: 48 89 15 67 c9 2a 00 mov %rdx,0x2ac967(%rip) # 6ca7a0 - 41de39: 90 nop - 41de3a: eb 08 jmp 41de44 <__cfree+0x94> - 41de3c: 0f 1f 40 00 nopl 0x0(%rax) - 41de40: 48 83 e0 f8 and $0xfffffffffffffff8,%rax - 41de44: 48 8b 4f f0 mov -0x10(%rdi),%rcx - 41de48: 48 89 f2 mov %rsi,%rdx - 41de4b: 48 8d 34 01 lea (%rcx,%rax,1),%rsi - 41de4f: 48 8b 05 2a d3 2a 00 mov 0x2ad32a(%rip),%rax # 6cb180 <_dl_pagesize> - 41de56: 48 29 ca sub %rcx,%rdx - 41de59: 48 89 d1 mov %rdx,%rcx - 41de5c: 48 09 f1 or %rsi,%rcx - 41de5f: 48 83 e8 01 sub $0x1,%rax - 41de63: 48 85 c8 test %rcx,%rax - 41de66: 75 40 jne 41dea8 <__cfree+0xf8> - 41de68: f0 ff 0d 59 c9 2a 00 lock decl 0x2ac959(%rip) # 6ca7c8 - 41de6f: 48 89 f0 mov %rsi,%rax - 41de72: 48 f7 d8 neg %rax - 41de75: f0 48 01 05 5b c9 2a lock add %rax,0x2ac95b(%rip) # 6ca7d8 - 41de7c: 00 - 41de7d: 48 89 d7 mov %rdx,%rdi - 41de80: e8 2b 1e 02 00 callq 43fcb0 <__munmap> - 41de85: 48 83 c4 28 add $0x28,%rsp - 41de89: 5b pop %rbx - 41de8a: 5d pop %rbp - 41de8b: 41 5c pop %r12 - 41de8d: 41 5d pop %r13 - 41de8f: c3 retq - 41de90: 48 8b 74 24 48 mov 0x48(%rsp),%rsi - 41de95: ff d0 callq *%rax - 41de97: 48 83 c4 28 add $0x28,%rsp - 41de9b: 5b pop %rbx - 41de9c: 5d pop %rbp - 41de9d: 41 5c pop %r12 - 41de9f: 41 5d pop %r13 - 41dea1: c3 retq - 41dea2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 41dea8: 8b 1d c2 c8 2a 00 mov 0x2ac8c2(%rip),%ebx # 6ca770 - 41deae: 89 d8 mov %ebx,%eax - 41deb0: 83 e0 05 and $0x5,%eax - 41deb3: 83 f8 05 cmp $0x5,%eax - 41deb6: 0f 84 8b 00 00 00 je 41df47 <__cfree+0x197> - 41debc: f6 c3 01 test $0x1,%bl - 41debf: 75 0f jne 41ded0 <__cfree+0x120> - 41dec1: 83 e3 02 and $0x2,%ebx - 41dec4: 0f 84 2d ff ff ff je 41ddf7 <__cfree+0x47> - 41deca: e8 31 fd fe ff callq 40dc00 - 41decf: 90 nop - 41ded0: 48 8d 74 24 10 lea 0x10(%rsp),%rsi - 41ded5: 31 c9 xor %ecx,%ecx - 41ded7: ba 10 00 00 00 mov $0x10,%edx - 41dedc: c6 44 24 10 00 movb $0x0,0x10(%rsp) - 41dee1: e8 ca 3f 03 00 callq 451eb0 <_itoa_word> - 41dee6: 48 39 e0 cmp %rsp,%rax - 41dee9: 48 89 c5 mov %rax,%rbp - 41deec: 76 25 jbe 41df13 <__cfree+0x163> - 41deee: 48 89 c2 mov %rax,%rdx - 41def1: 48 89 c7 mov %rax,%rdi - 41def4: be 30 00 00 00 mov $0x30,%esi - 41def9: 48 29 e2 sub %rsp,%rdx - 41defc: 4c 8d 68 ff lea -0x1(%rax),%r13 - 41df00: 48 29 d7 sub %rdx,%rdi - 41df03: e8 48 24 fe ff callq 400350 <__rela_iplt_end+0x88> - 41df08: 48 8d 44 24 ff lea -0x1(%rsp),%rax - 41df0d: 4c 29 e8 sub %r13,%rax - 41df10: 48 01 c5 add %rax,%rbp - 41df13: 48 8b 05 a6 f3 2a 00 mov 0x2af3a6(%rip),%rax # 6cd2c0 <__libc_argv> - 41df1a: ba 38 20 4a 00 mov $0x4a2038,%edx - 41df1f: 49 89 e8 mov %rbp,%r8 - 41df22: b9 d0 23 4a 00 mov $0x4a23d0,%ecx - 41df27: be a8 23 4a 00 mov $0x4a23a8,%esi - 41df2c: 48 8b 00 mov (%rax),%rax - 41df2f: 48 85 c0 test %rax,%rax - 41df32: 48 0f 45 d0 cmovne %rax,%rdx - 41df36: 83 e3 02 and $0x2,%ebx - 41df39: 31 c0 xor %eax,%eax - 41df3b: 89 df mov %ebx,%edi - 41df3d: e8 7e 36 ff ff callq 4115c0 <__libc_message> - 41df42: e9 b0 fe ff ff jmpq 41ddf7 <__cfree+0x47> - 41df47: 83 e3 02 and $0x2,%ebx - 41df4a: ba d0 23 4a 00 mov $0x4a23d0,%edx - 41df4f: be 3c ca 4b 00 mov $0x4bca3c,%esi - 41df54: 89 df mov %ebx,%edi - 41df56: 31 c0 xor %eax,%eax - 41df58: e8 63 36 ff ff callq 4115c0 <__libc_message> - 41df5d: e9 95 fe ff ff jmpq 41ddf7 <__cfree+0x47> - 41df62: 0f 1f 40 00 nopl 0x0(%rax) - 41df66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41df6d: 00 00 00 - -000000000041df70 <__libc_realloc>: - 41df70: 41 57 push %r15 - 41df72: 41 56 push %r14 - 41df74: 41 55 push %r13 - 41df76: 41 54 push %r12 - 41df78: 49 89 f5 mov %rsi,%r13 - 41df7b: 55 push %rbp - 41df7c: 53 push %rbx - 41df7d: 48 89 fb mov %rdi,%rbx - 41df80: 48 83 ec 38 sub $0x38,%rsp - 41df84: 48 8b 05 f5 c7 2a 00 mov 0x2ac7f5(%rip),%rax # 6ca780 <__realloc_hook> - 41df8b: 48 85 c0 test %rax,%rax - 41df8e: 0f 85 04 02 00 00 jne 41e198 <__libc_realloc+0x228> - 41df94: 48 85 f6 test %rsi,%rsi - 41df97: 75 09 jne 41dfa2 <__libc_realloc+0x32> - 41df99: 48 85 ff test %rdi,%rdi - 41df9c: 0f 85 6e 02 00 00 jne 41e210 <__libc_realloc+0x2a0> - 41dfa2: 48 85 db test %rbx,%rbx - 41dfa5: 0f 84 15 03 00 00 je 41e2c0 <__libc_realloc+0x350> - 41dfab: 48 8b 43 f8 mov -0x8(%rbx),%rax - 41dfaf: 4c 8d 73 f0 lea -0x10(%rbx),%r14 - 41dfb3: 49 89 c7 mov %rax,%r15 - 41dfb6: 48 89 c1 mov %rax,%rcx - 41dfb9: 49 83 e7 f8 and $0xfffffffffffffff8,%r15 - 41dfbd: 83 e1 02 and $0x2,%ecx - 41dfc0: 74 7e je 41e040 <__libc_realloc+0xd0> - 41dfc2: 4c 89 f8 mov %r15,%rax - 41dfc5: 48 f7 d8 neg %rax - 41dfc8: 49 39 c6 cmp %rax,%r14 - 41dfcb: 0f 87 3f 03 00 00 ja 41e310 <__libc_realloc+0x3a0> - 41dfd1: 41 f6 c6 0f test $0xf,%r14b - 41dfd5: 0f 85 35 03 00 00 jne 41e310 <__libc_realloc+0x3a0> - 41dfdb: 45 31 e4 xor %r12d,%r12d - 41dfde: 49 83 fd bf cmp $0xffffffffffffffbf,%r13 - 41dfe2: 0f 87 c8 01 00 00 ja 41e1b0 <__libc_realloc+0x240> - 41dfe8: 49 8d 45 17 lea 0x17(%r13),%rax - 41dfec: 48 89 c2 mov %rax,%rdx - 41dfef: 48 83 e2 f0 and $0xfffffffffffffff0,%rdx - 41dff3: 48 83 f8 20 cmp $0x20,%rax - 41dff7: b8 20 00 00 00 mov $0x20,%eax - 41dffc: 48 0f 42 d0 cmovb %rax,%rdx - 41e000: 48 85 c9 test %rcx,%rcx - 41e003: 0f 84 97 00 00 00 je 41e0a0 <__libc_realloc+0x130> - 41e009: 48 89 d6 mov %rdx,%rsi - 41e00c: 4c 89 f7 mov %r14,%rdi - 41e00f: 48 89 54 24 08 mov %rdx,0x8(%rsp) - 41e014: e8 07 90 ff ff callq 417020 - 41e019: 48 85 c0 test %rax,%rax - 41e01c: 48 8d 68 10 lea 0x10(%rax),%rbp - 41e020: 48 8b 54 24 08 mov 0x8(%rsp),%rdx - 41e025: 0f 84 9d 01 00 00 je 41e1c8 <__libc_realloc+0x258> - 41e02b: 48 83 c4 38 add $0x38,%rsp - 41e02f: 48 89 e8 mov %rbp,%rax - 41e032: 5b pop %rbx - 41e033: 5d pop %rbp - 41e034: 41 5c pop %r12 - 41e036: 41 5d pop %r13 - 41e038: 41 5e pop %r14 - 41e03a: 41 5f pop %r15 - 41e03c: c3 retq - 41e03d: 0f 1f 00 nopl (%rax) - 41e040: a8 04 test $0x4,%al - 41e042: 0f 84 28 01 00 00 je 41e170 <__libc_realloc+0x200> - 41e048: 4c 89 f0 mov %r14,%rax - 41e04b: 48 25 00 00 00 fc and $0xfffffffffc000000,%rax - 41e051: 4c 8b 20 mov (%rax),%r12 - 41e054: 4c 89 f8 mov %r15,%rax - 41e057: 48 f7 d8 neg %rax - 41e05a: 49 39 c6 cmp %rax,%r14 - 41e05d: 77 0a ja 41e069 <__libc_realloc+0xf9> - 41e05f: 41 f6 c6 0f test $0xf,%r14b - 41e063: 0f 84 75 ff ff ff je 41dfde <__libc_realloc+0x6e> - 41e069: 4d 85 e4 test %r12,%r12 - 41e06c: 8b 2d fe c6 2a 00 mov 0x2ac6fe(%rip),%ebp # 6ca770 - 41e072: 74 06 je 41e07a <__libc_realloc+0x10a> - 41e074: 41 83 4c 24 04 04 orl $0x4,0x4(%r12) - 41e07a: 89 e8 mov %ebp,%eax - 41e07c: 83 e0 05 and $0x5,%eax - 41e07f: 83 f8 05 cmp $0x5,%eax - 41e082: 0f 84 98 02 00 00 je 41e320 <__libc_realloc+0x3b0> - 41e088: 40 f6 c5 01 test $0x1,%bpl - 41e08c: 0f 85 a6 01 00 00 jne 41e238 <__libc_realloc+0x2c8> - 41e092: 83 e5 02 and $0x2,%ebp - 41e095: 0f 85 a2 02 00 00 jne 41e33d <__libc_realloc+0x3cd> - 41e09b: 31 ed xor %ebp,%ebp - 41e09d: eb 8c jmp 41e02b <__libc_realloc+0xbb> - 41e09f: 90 nop - 41e0a0: be 01 00 00 00 mov $0x1,%esi - 41e0a5: 31 c0 xor %eax,%eax - 41e0a7: 83 3d 0e f1 2a 00 00 cmpl $0x0,0x2af10e(%rip) # 6cd1bc <__libc_multiple_threads> - 41e0ae: 74 0a je 41e0ba <__libc_realloc+0x14a> - 41e0b0: f0 41 0f b1 34 24 lock cmpxchg %esi,(%r12) - 41e0b6: 75 09 jne 41e0c1 <__libc_realloc+0x151> - 41e0b8: eb 1e jmp 41e0d8 <__libc_realloc+0x168> - 41e0ba: 41 0f b1 34 24 cmpxchg %esi,(%r12) - 41e0bf: 74 17 je 41e0d8 <__libc_realloc+0x168> - 41e0c1: 49 8d 3c 24 lea (%r12),%rdi - 41e0c5: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41e0cc: e8 ff 44 02 00 callq 4425d0 <__lll_lock_wait_private> - 41e0d1: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41e0d8: 48 89 d1 mov %rdx,%rcx - 41e0db: 4c 89 f6 mov %r14,%rsi - 41e0de: 4c 89 fa mov %r15,%rdx - 41e0e1: 4c 89 e7 mov %r12,%rdi - 41e0e4: e8 77 e9 ff ff callq 41ca60 <_int_realloc> - 41e0e9: 48 89 c5 mov %rax,%rbp - 41e0ec: 83 3d c9 f0 2a 00 00 cmpl $0x0,0x2af0c9(%rip) # 6cd1bc <__libc_multiple_threads> - 41e0f3: 74 09 je 41e0fe <__libc_realloc+0x18e> - 41e0f5: f0 41 ff 0c 24 lock decl (%r12) - 41e0fa: 75 08 jne 41e104 <__libc_realloc+0x194> - 41e0fc: eb 1d jmp 41e11b <__libc_realloc+0x1ab> - 41e0fe: 41 ff 0c 24 decl (%r12) - 41e102: 74 17 je 41e11b <__libc_realloc+0x1ab> - 41e104: 49 8d 3c 24 lea (%r12),%rdi - 41e108: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41e10f: e8 ec 44 02 00 callq 442600 <__lll_unlock_wake_private> - 41e114: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41e11b: 48 85 ed test %rbp,%rbp - 41e11e: 0f 84 ac 01 00 00 je 41e2d0 <__libc_realloc+0x360> - 41e124: 48 8b 45 f8 mov -0x8(%rbp),%rax - 41e128: a8 02 test $0x2,%al - 41e12a: 0f 85 fb fe ff ff jne 41e02b <__libc_realloc+0xbb> - 41e130: a8 04 test $0x4,%al - 41e132: ba 00 a8 6c 00 mov $0x6ca800,%edx - 41e137: 74 0d je 41e146 <__libc_realloc+0x1d6> - 41e139: 48 8d 45 f0 lea -0x10(%rbp),%rax - 41e13d: 48 25 00 00 00 fc and $0xfffffffffc000000,%rax - 41e143: 48 8b 10 mov (%rax),%rdx - 41e146: 4c 39 e2 cmp %r12,%rdx - 41e149: 0f 84 dc fe ff ff je 41e02b <__libc_realloc+0xbb> - 41e14f: b9 18 2e 4a 00 mov $0x4a2e18,%ecx - 41e154: ba e9 0b 00 00 mov $0xbe9,%edx - 41e159: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 41e15e: bf c0 29 4a 00 mov $0x4a29c0,%edi - 41e163: e8 b8 8c ff ff callq 416e20 <__malloc_assert> - 41e168: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 41e16f: 00 - 41e170: 4c 89 f8 mov %r15,%rax - 41e173: 48 f7 d8 neg %rax - 41e176: 49 39 c6 cmp %rax,%r14 - 41e179: 0f 87 a1 00 00 00 ja 41e220 <__libc_realloc+0x2b0> - 41e17f: 41 f6 c6 0f test $0xf,%r14b - 41e183: 0f 85 97 00 00 00 jne 41e220 <__libc_realloc+0x2b0> - 41e189: 41 bc 00 a8 6c 00 mov $0x6ca800,%r12d - 41e18f: e9 4a fe ff ff jmpq 41dfde <__libc_realloc+0x6e> - 41e194: 0f 1f 40 00 nopl 0x0(%rax) - 41e198: 48 8b 54 24 68 mov 0x68(%rsp),%rdx - 41e19d: ff d0 callq *%rax - 41e19f: 48 89 c5 mov %rax,%rbp - 41e1a2: e9 84 fe ff ff jmpq 41e02b <__libc_realloc+0xbb> - 41e1a7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 41e1ae: 00 00 - 41e1b0: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 41e1b7: 31 ed xor %ebp,%ebp - 41e1b9: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) - 41e1c0: e9 66 fe ff ff jmpq 41e02b <__libc_realloc+0xbb> - 41e1c5: 0f 1f 00 nopl (%rax) - 41e1c8: 49 8d 47 f8 lea -0x8(%r15),%rax - 41e1cc: 48 89 dd mov %rbx,%rbp - 41e1cf: 48 39 c2 cmp %rax,%rdx - 41e1d2: 0f 86 53 fe ff ff jbe 41e02b <__libc_realloc+0xbb> - 41e1d8: 4c 89 ef mov %r13,%rdi - 41e1db: e8 30 f8 ff ff callq 41da10 <__libc_malloc> - 41e1e0: 48 85 c0 test %rax,%rax - 41e1e3: 48 89 c3 mov %rax,%rbx - 41e1e6: 0f 84 af fe ff ff je 41e09b <__libc_realloc+0x12b> - 41e1ec: 49 8d 57 f0 lea -0x10(%r15),%rdx - 41e1f0: 48 89 ee mov %rbp,%rsi - 41e1f3: 48 89 c7 mov %rax,%rdi - 41e1f6: 48 89 dd mov %rbx,%rbp - 41e1f9: e8 22 de 00 00 callq 42c020 - 41e1fe: 4c 89 f7 mov %r14,%rdi - 41e201: e8 ea 9a ff ff callq 417cf0 - 41e206: e9 20 fe ff ff jmpq 41e02b <__libc_realloc+0xbb> - 41e20b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41e210: e8 9b fb ff ff callq 41ddb0 <__cfree> - 41e215: 31 ed xor %ebp,%ebp - 41e217: e9 0f fe ff ff jmpq 41e02b <__libc_realloc+0xbb> - 41e21c: 0f 1f 40 00 nopl 0x0(%rax) - 41e220: 8b 2d 4a c5 2a 00 mov 0x2ac54a(%rip),%ebp # 6ca770 - 41e226: 41 bc 00 a8 6c 00 mov $0x6ca800,%r12d - 41e22c: e9 43 fe ff ff jmpq 41e074 <__libc_realloc+0x104> - 41e231: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 41e238: 4c 8d 64 24 10 lea 0x10(%rsp),%r12 - 41e23d: 48 8d 74 24 20 lea 0x20(%rsp),%rsi - 41e242: 31 c9 xor %ecx,%ecx - 41e244: 48 89 df mov %rbx,%rdi - 41e247: ba 10 00 00 00 mov $0x10,%edx - 41e24c: c6 44 24 20 00 movb $0x0,0x20(%rsp) - 41e251: e8 5a 3c 03 00 callq 451eb0 <_itoa_word> - 41e256: 4c 39 e0 cmp %r12,%rax - 41e259: 48 89 c3 mov %rax,%rbx - 41e25c: 76 25 jbe 41e283 <__libc_realloc+0x313> - 41e25e: 48 89 c2 mov %rax,%rdx - 41e261: 48 89 c7 mov %rax,%rdi - 41e264: be 30 00 00 00 mov $0x30,%esi - 41e269: 4c 29 e2 sub %r12,%rdx - 41e26c: 4c 8d 68 ff lea -0x1(%rax),%r13 - 41e270: 48 29 d7 sub %rdx,%rdi - 41e273: e8 d8 20 fe ff callq 400350 <__rela_iplt_end+0x88> - 41e278: 48 8d 44 24 0f lea 0xf(%rsp),%rax - 41e27d: 4c 29 e8 sub %r13,%rax - 41e280: 48 01 c3 add %rax,%rbx - 41e283: 48 8b 05 36 f0 2a 00 mov 0x2af036(%rip),%rax # 6cd2c0 <__libc_argv> - 41e28a: 89 ef mov %ebp,%edi - 41e28c: ba 38 20 4a 00 mov $0x4a2038,%edx - 41e291: 49 89 d8 mov %rbx,%r8 - 41e294: b9 c6 21 4a 00 mov $0x4a21c6,%ecx - 41e299: be a8 23 4a 00 mov $0x4a23a8,%esi - 41e29e: 48 8b 00 mov (%rax),%rax - 41e2a1: 48 85 c0 test %rax,%rax - 41e2a4: 48 0f 45 d0 cmovne %rax,%rdx - 41e2a8: 83 e7 02 and $0x2,%edi - 41e2ab: 31 c0 xor %eax,%eax - 41e2ad: e8 0e 33 ff ff callq 4115c0 <__libc_message> - 41e2b2: 31 ed xor %ebp,%ebp - 41e2b4: e9 72 fd ff ff jmpq 41e02b <__libc_realloc+0xbb> - 41e2b9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 41e2c0: 4c 89 ef mov %r13,%rdi - 41e2c3: e8 48 f7 ff ff callq 41da10 <__libc_malloc> - 41e2c8: 48 89 c5 mov %rax,%rbp - 41e2cb: e9 5b fd ff ff jmpq 41e02b <__libc_realloc+0xbb> - 41e2d0: 90 nop - 41e2d1: 4c 89 ef mov %r13,%rdi - 41e2d4: 31 ed xor %ebp,%ebp - 41e2d6: e8 35 f7 ff ff callq 41da10 <__libc_malloc> - 41e2db: 48 85 c0 test %rax,%rax - 41e2de: 49 89 c5 mov %rax,%r13 - 41e2e1: 0f 84 44 fd ff ff je 41e02b <__libc_realloc+0xbb> - 41e2e7: 49 8d 57 f8 lea -0x8(%r15),%rdx - 41e2eb: 48 89 de mov %rbx,%rsi - 41e2ee: 48 89 c7 mov %rax,%rdi - 41e2f1: 4c 89 ed mov %r13,%rbp - 41e2f4: e8 27 dd 00 00 callq 42c020 - 41e2f9: 31 d2 xor %edx,%edx - 41e2fb: 4c 89 f6 mov %r14,%rsi - 41e2fe: 4c 89 e7 mov %r12,%rdi - 41e301: e8 ba b4 ff ff callq 4197c0 <_int_free> - 41e306: e9 20 fd ff ff jmpq 41e02b <__libc_realloc+0xbb> - 41e30b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41e310: 8b 2d 5a c4 2a 00 mov 0x2ac45a(%rip),%ebp # 6ca770 - 41e316: e9 5f fd ff ff jmpq 41e07a <__libc_realloc+0x10a> - 41e31b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41e320: 89 ef mov %ebp,%edi - 41e322: ba c6 21 4a 00 mov $0x4a21c6,%edx - 41e327: be 3c ca 4b 00 mov $0x4bca3c,%esi - 41e32c: 83 e7 02 and $0x2,%edi - 41e32f: 31 c0 xor %eax,%eax - 41e331: 31 ed xor %ebp,%ebp - 41e333: e8 88 32 ff ff callq 4115c0 <__libc_message> - 41e338: e9 ee fc ff ff jmpq 41e02b <__libc_realloc+0xbb> - 41e33d: e8 be f8 fe ff callq 40dc00 - 41e342: 0f 1f 40 00 nopl 0x0(%rax) - 41e346: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41e34d: 00 00 00 - -000000000041e350 <__libc_memalign>: - 41e350: 48 8b 05 21 c4 2a 00 mov 0x2ac421(%rip),%rax # 6ca778 <__memalign_hook> - 41e357: 41 54 push %r12 - 41e359: 48 85 c0 test %rax,%rax - 41e35c: 55 push %rbp - 41e35d: 53 push %rbx - 41e35e: 48 8b 54 24 18 mov 0x18(%rsp),%rdx - 41e363: 0f 85 ef 01 00 00 jne 41e558 <__libc_memalign+0x208> - 41e369: 48 83 ff 10 cmp $0x10,%rdi - 41e36d: 0f 86 d5 01 00 00 jbe 41e548 <__libc_memalign+0x1f8> - 41e373: 48 83 ff 1f cmp $0x1f,%rdi - 41e377: 0f 87 e3 00 00 00 ja 41e460 <__libc_memalign+0x110> - 41e37d: 48 83 fe bf cmp $0xffffffffffffffbf,%rsi - 41e381: 0f 87 f1 01 00 00 ja 41e578 <__libc_memalign+0x228> - 41e387: bb 20 00 00 00 mov $0x20,%ebx - 41e38c: 48 c7 c0 d8 ff ff ff mov $0xffffffffffffffd8,%rax - 41e393: 49 89 f4 mov %rsi,%r12 - 41e396: 64 48 8b 28 mov %fs:(%rax),%rbp - 41e39a: 48 85 ed test %rbp,%rbp - 41e39d: 0f 84 15 01 00 00 je 41e4b8 <__libc_memalign+0x168> - 41e3a3: 8b 45 04 mov 0x4(%rbp),%eax - 41e3a6: 83 e0 04 and $0x4,%eax - 41e3a9: 0f 85 09 01 00 00 jne 41e4b8 <__libc_memalign+0x168> - 41e3af: be 01 00 00 00 mov $0x1,%esi - 41e3b4: 83 3d 01 ee 2a 00 00 cmpl $0x0,0x2aee01(%rip) # 6cd1bc <__libc_multiple_threads> - 41e3bb: 74 09 je 41e3c6 <__libc_memalign+0x76> - 41e3bd: f0 0f b1 75 00 lock cmpxchg %esi,0x0(%rbp) - 41e3c2: 75 08 jne 41e3cc <__libc_memalign+0x7c> - 41e3c4: eb 1d jmp 41e3e3 <__libc_memalign+0x93> - 41e3c6: 0f b1 75 00 cmpxchg %esi,0x0(%rbp) - 41e3ca: 74 17 je 41e3e3 <__libc_memalign+0x93> - 41e3cc: 48 8d 7d 00 lea 0x0(%rbp),%rdi - 41e3d0: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41e3d7: e8 f4 41 02 00 callq 4425d0 <__lll_lock_wait_private> - 41e3dc: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41e3e3: 4c 89 e2 mov %r12,%rdx - 41e3e6: 48 89 de mov %rbx,%rsi - 41e3e9: 48 89 ef mov %rbp,%rdi - 41e3ec: e8 1f e1 ff ff callq 41c510 <_int_memalign> - 41e3f1: 48 85 c0 test %rax,%rax - 41e3f4: 48 89 c2 mov %rax,%rdx - 41e3f7: 0f 84 fb 00 00 00 je 41e4f8 <__libc_memalign+0x1a8> - 41e3fd: 83 3d b8 ed 2a 00 00 cmpl $0x0,0x2aedb8(%rip) # 6cd1bc <__libc_multiple_threads> - 41e404: 74 08 je 41e40e <__libc_memalign+0xbe> - 41e406: f0 ff 4d 00 lock decl 0x0(%rbp) - 41e40a: 75 07 jne 41e413 <__libc_memalign+0xc3> - 41e40c: eb 1c jmp 41e42a <__libc_memalign+0xda> - 41e40e: ff 4d 00 decl 0x0(%rbp) - 41e411: 74 17 je 41e42a <__libc_memalign+0xda> - 41e413: 48 8d 7d 00 lea 0x0(%rbp),%rdi - 41e417: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41e41e: e8 dd 41 02 00 callq 442600 <__lll_unlock_wake_private> - 41e423: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41e42a: 48 85 d2 test %rdx,%rdx - 41e42d: 0f 84 5d 01 00 00 je 41e590 <__libc_memalign+0x240> - 41e433: 48 8b 42 f8 mov -0x8(%rdx),%rax - 41e437: a8 02 test $0x2,%al - 41e439: 75 16 jne 41e451 <__libc_memalign+0x101> - 41e43b: a8 04 test $0x4,%al - 41e43d: b9 00 a8 6c 00 mov $0x6ca800,%ecx - 41e442: 0f 85 e8 00 00 00 jne 41e530 <__libc_memalign+0x1e0> - 41e448: 48 39 e9 cmp %rbp,%rcx - 41e44b: 0f 85 46 01 00 00 jne 41e597 <__libc_memalign+0x247> - 41e451: 48 89 d0 mov %rdx,%rax - 41e454: 5b pop %rbx - 41e455: 5d pop %rbp - 41e456: 41 5c pop %r12 - 41e458: c3 retq - 41e459: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 41e460: 48 b8 00 00 00 00 00 movabs $0x8000000000000000,%rax - 41e467: 00 00 80 - 41e46a: 48 39 c7 cmp %rax,%rdi - 41e46d: 0f 87 ed 00 00 00 ja 41e560 <__libc_memalign+0x210> - 41e473: 48 c7 c0 df ff ff ff mov $0xffffffffffffffdf,%rax - 41e47a: 48 29 f8 sub %rdi,%rax - 41e47d: 48 39 c6 cmp %rax,%rsi - 41e480: 0f 87 f2 00 00 00 ja 41e578 <__libc_memalign+0x228> - 41e486: 48 8d 47 ff lea -0x1(%rdi),%rax - 41e48a: 48 85 f8 test %rdi,%rax - 41e48d: 0f 84 1d 01 00 00 je 41e5b0 <__libc_memalign+0x260> - 41e493: 48 83 ff 20 cmp $0x20,%rdi - 41e497: bb 20 00 00 00 mov $0x20,%ebx - 41e49c: 0f 84 ea fe ff ff je 41e38c <__libc_memalign+0x3c> - 41e4a2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 41e4a8: 48 01 db add %rbx,%rbx - 41e4ab: 48 39 df cmp %rbx,%rdi - 41e4ae: 77 f8 ja 41e4a8 <__libc_memalign+0x158> - 41e4b0: e9 d7 fe ff ff jmpq 41e38c <__libc_memalign+0x3c> - 41e4b5: 0f 1f 00 nopl (%rax) - 41e4b8: e8 a3 8c ff ff callq 417160 - 41e4bd: 48 85 c0 test %rax,%rax - 41e4c0: 48 89 c5 mov %rax,%rbp - 41e4c3: 0f 85 1a ff ff ff jne 41e3e3 <__libc_memalign+0x93> - 41e4c9: 4a 8d 7c 23 20 lea 0x20(%rbx,%r12,1),%rdi - 41e4ce: 31 f6 xor %esi,%esi - 41e4d0: e8 7b 8f ff ff callq 417450 - 41e4d5: 4c 89 e2 mov %r12,%rdx - 41e4d8: 48 89 de mov %rbx,%rsi - 41e4db: 48 89 c7 mov %rax,%rdi - 41e4de: 48 89 c5 mov %rax,%rbp - 41e4e1: e8 2a e0 ff ff callq 41c510 <_int_memalign> - 41e4e6: 48 85 c0 test %rax,%rax - 41e4e9: 48 89 c2 mov %rax,%rdx - 41e4ec: 75 2a jne 41e518 <__libc_memalign+0x1c8> - 41e4ee: 48 85 ed test %rbp,%rbp - 41e4f1: 74 25 je 41e518 <__libc_memalign+0x1c8> - 41e4f3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41e4f8: 90 nop - 41e4f9: 48 89 ef mov %rbp,%rdi - 41e4fc: 4c 89 e6 mov %r12,%rsi - 41e4ff: e8 ec 94 ff ff callq 4179f0 - 41e504: 4c 89 e2 mov %r12,%rdx - 41e507: 48 89 de mov %rbx,%rsi - 41e50a: 48 89 c7 mov %rax,%rdi - 41e50d: 48 89 c5 mov %rax,%rbp - 41e510: e8 fb df ff ff callq 41c510 <_int_memalign> - 41e515: 48 89 c2 mov %rax,%rdx - 41e518: 48 85 ed test %rbp,%rbp - 41e51b: 0f 85 dc fe ff ff jne 41e3fd <__libc_memalign+0xad> - 41e521: e9 04 ff ff ff jmpq 41e42a <__libc_memalign+0xda> - 41e526: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41e52d: 00 00 00 - 41e530: 48 8d 42 f0 lea -0x10(%rdx),%rax - 41e534: 48 25 00 00 00 fc and $0xfffffffffc000000,%rax - 41e53a: 48 8b 08 mov (%rax),%rcx - 41e53d: e9 06 ff ff ff jmpq 41e448 <__libc_memalign+0xf8> - 41e542: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 41e548: 5b pop %rbx - 41e549: 5d pop %rbp - 41e54a: 41 5c pop %r12 - 41e54c: 48 89 f7 mov %rsi,%rdi - 41e54f: e9 bc f4 ff ff jmpq 41da10 <__libc_malloc> - 41e554: 0f 1f 40 00 nopl 0x0(%rax) - 41e558: 5b pop %rbx - 41e559: 5d pop %rbp - 41e55a: 41 5c pop %r12 - 41e55c: ff e0 jmpq *%rax - 41e55e: 66 90 xchg %ax,%ax - 41e560: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 41e567: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) - 41e56e: 31 c0 xor %eax,%eax - 41e570: e9 df fe ff ff jmpq 41e454 <__libc_memalign+0x104> - 41e575: 0f 1f 00 nopl (%rax) - 41e578: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 41e57f: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) - 41e586: 31 c0 xor %eax,%eax - 41e588: e9 c7 fe ff ff jmpq 41e454 <__libc_memalign+0x104> - 41e58d: 0f 1f 00 nopl (%rax) - 41e590: 31 c0 xor %eax,%eax - 41e592: e9 bd fe ff ff jmpq 41e454 <__libc_memalign+0x104> - 41e597: b9 08 2e 4a 00 mov $0x4a2e08,%ecx - 41e59c: ba 3c 0c 00 00 mov $0xc3c,%edx - 41e5a1: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 41e5a6: bf 20 2a 4a 00 mov $0x4a2a20,%edi - 41e5ab: e8 70 88 ff ff callq 416e20 <__malloc_assert> - 41e5b0: 48 89 fb mov %rdi,%rbx - 41e5b3: e9 d4 fd ff ff jmpq 41e38c <__libc_memalign+0x3c> - 41e5b8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 41e5bf: 00 - -000000000041e5c0 <__calloc>: - 41e5c0: 41 55 push %r13 - 41e5c2: 48 89 fa mov %rdi,%rdx - 41e5c5: 41 54 push %r12 - 41e5c7: 55 push %rbp - 41e5c8: 53 push %rbx - 41e5c9: 48 89 fd mov %rdi,%rbp - 41e5cc: 48 09 f2 or %rsi,%rdx - 41e5cf: b8 ff ff ff ff mov $0xffffffff,%eax - 41e5d4: 48 83 ec 08 sub $0x8,%rsp - 41e5d8: 48 0f af ee imul %rsi,%rbp - 41e5dc: 48 39 c2 cmp %rax,%rdx - 41e5df: 76 1f jbe 41e600 <__calloc+0x40> - 41e5e1: 48 85 f6 test %rsi,%rsi - 41e5e4: 74 1a je 41e600 <__calloc+0x40> - 41e5e6: 31 d2 xor %edx,%edx - 41e5e8: 48 89 e8 mov %rbp,%rax - 41e5eb: 48 f7 f6 div %rsi - 41e5ee: 48 39 c7 cmp %rax,%rdi - 41e5f1: 0f 85 a9 02 00 00 jne 41e8a0 <__calloc+0x2e0> - 41e5f7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 41e5fe: 00 00 - 41e600: 48 8b 05 81 c1 2a 00 mov 0x2ac181(%rip),%rax # 6ca788 <__malloc_hook> - 41e607: 48 85 c0 test %rax,%rax - 41e60a: 0f 85 70 02 00 00 jne 41e880 <__calloc+0x2c0> - 41e610: 48 c7 c0 d8 ff ff ff mov $0xffffffffffffffd8,%rax - 41e617: 64 48 8b 18 mov %fs:(%rax),%rbx - 41e61b: 48 85 db test %rbx,%rbx - 41e61e: 74 0c je 41e62c <__calloc+0x6c> - 41e620: 8b 43 04 mov 0x4(%rbx),%eax - 41e623: 83 e0 04 and $0x4,%eax - 41e626: 0f 84 d4 00 00 00 je 41e700 <__calloc+0x140> - 41e62c: e8 2f 8b ff ff callq 417160 - 41e631: 48 85 c0 test %rax,%rax - 41e634: 48 89 c3 mov %rax,%rbx - 41e637: 0f 84 7b 02 00 00 je 41e8b8 <__calloc+0x2f8> - 41e63d: 4c 8b 6b 58 mov 0x58(%rbx),%r13 - 41e641: 4d 8b 65 08 mov 0x8(%r13),%r12 - 41e645: 49 83 e4 f8 and $0xfffffffffffffff8,%r12 - 41e649: 48 81 fb 00 a8 6c 00 cmp $0x6ca800,%rbx - 41e650: 0f 84 9a 01 00 00 je 41e7f0 <__calloc+0x230> - 41e656: 4c 89 e8 mov %r13,%rax - 41e659: 48 89 ee mov %rbp,%rsi - 41e65c: 48 89 df mov %rbx,%rdi - 41e65f: 48 25 00 00 00 fc and $0xfffffffffc000000,%rax - 41e665: 48 03 40 18 add 0x18(%rax),%rax - 41e669: 4c 29 e8 sub %r13,%rax - 41e66c: 49 39 c4 cmp %rax,%r12 - 41e66f: 4c 0f 42 e0 cmovb %rax,%r12 - 41e673: e8 c8 ce ff ff callq 41b540 <_int_malloc> - 41e678: 48 85 c0 test %rax,%rax - 41e67b: 49 89 c0 mov %rax,%r8 - 41e67e: 0f 84 8c 01 00 00 je 41e810 <__calloc+0x250> - 41e684: 49 8b 40 f8 mov -0x8(%r8),%rax - 41e688: a8 02 test $0x2,%al - 41e68a: 75 16 jne 41e6a2 <__calloc+0xe2> - 41e68c: a8 04 test $0x4,%al - 41e68e: ba 00 a8 6c 00 mov $0x6ca800,%edx - 41e693: 0f 85 b7 01 00 00 jne 41e850 <__calloc+0x290> - 41e699: 48 39 da cmp %rbx,%rdx - 41e69c: 0f 85 55 02 00 00 jne 41e8f7 <__calloc+0x337> - 41e6a2: 48 85 db test %rbx,%rbx - 41e6a5: 74 33 je 41e6da <__calloc+0x11a> - 41e6a7: 83 3d 0e eb 2a 00 00 cmpl $0x0,0x2aeb0e(%rip) # 6cd1bc <__libc_multiple_threads> - 41e6ae: 74 07 je 41e6b7 <__calloc+0xf7> - 41e6b0: f0 ff 0b lock decl (%rbx) - 41e6b3: 75 06 jne 41e6bb <__calloc+0xfb> - 41e6b5: eb 1a jmp 41e6d1 <__calloc+0x111> - 41e6b7: ff 0b decl (%rbx) - 41e6b9: 74 16 je 41e6d1 <__calloc+0x111> - 41e6bb: 48 8d 3b lea (%rbx),%rdi - 41e6be: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41e6c5: e8 36 3f 02 00 callq 442600 <__lll_unlock_wake_private> - 41e6ca: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41e6d1: 4d 85 c0 test %r8,%r8 - 41e6d4: 0f 84 bd 01 00 00 je 41e897 <__calloc+0x2d7> - 41e6da: 49 8b 50 f8 mov -0x8(%r8),%rdx - 41e6de: f6 c2 02 test $0x2,%dl - 41e6e1: 74 5d je 41e740 <__calloc+0x180> - 41e6e3: 8b 15 4b df 2a 00 mov 0x2adf4b(%rip),%edx # 6cc634 - 41e6e9: 4c 89 c0 mov %r8,%rax - 41e6ec: 85 d2 test %edx,%edx - 41e6ee: 0f 85 74 01 00 00 jne 41e868 <__calloc+0x2a8> - 41e6f4: 48 83 c4 08 add $0x8,%rsp - 41e6f8: 5b pop %rbx - 41e6f9: 5d pop %rbp - 41e6fa: 41 5c pop %r12 - 41e6fc: 41 5d pop %r13 - 41e6fe: c3 retq - 41e6ff: 90 nop - 41e700: be 01 00 00 00 mov $0x1,%esi - 41e705: 83 3d b0 ea 2a 00 00 cmpl $0x0,0x2aeab0(%rip) # 6cd1bc <__libc_multiple_threads> - 41e70c: 74 08 je 41e716 <__calloc+0x156> - 41e70e: f0 0f b1 33 lock cmpxchg %esi,(%rbx) - 41e712: 75 07 jne 41e71b <__calloc+0x15b> - 41e714: eb 1b jmp 41e731 <__calloc+0x171> - 41e716: 0f b1 33 cmpxchg %esi,(%rbx) - 41e719: 74 16 je 41e731 <__calloc+0x171> - 41e71b: 48 8d 3b lea (%rbx),%rdi - 41e71e: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41e725: e8 a6 3e 02 00 callq 4425d0 <__lll_lock_wait_private> - 41e72a: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41e731: e9 07 ff ff ff jmpq 41e63d <__calloc+0x7d> - 41e736: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41e73d: 00 00 00 - 41e740: 8b 05 ee de 2a 00 mov 0x2adeee(%rip),%eax # 6cc634 - 41e746: 48 83 e2 f8 and $0xfffffffffffffff8,%rdx - 41e74a: 85 c0 test %eax,%eax - 41e74c: 75 10 jne 41e75e <__calloc+0x19e> - 41e74e: 49 8d 40 f0 lea -0x10(%r8),%rax - 41e752: 49 39 c5 cmp %rax,%r13 - 41e755: 75 07 jne 41e75e <__calloc+0x19e> - 41e757: 4c 39 e2 cmp %r12,%rdx - 41e75a: 49 0f 47 d4 cmova %r12,%rdx - 41e75e: 48 83 ea 08 sub $0x8,%rdx - 41e762: 48 89 d1 mov %rdx,%rcx - 41e765: 48 c1 e9 03 shr $0x3,%rcx - 41e769: 48 83 f9 02 cmp $0x2,%rcx - 41e76d: 0f 86 9d 01 00 00 jbe 41e910 <__calloc+0x350> - 41e773: 48 83 f9 09 cmp $0x9,%rcx - 41e777: 0f 87 ee 00 00 00 ja 41e86b <__calloc+0x2ab> - 41e77d: 48 83 f9 04 cmp $0x4,%rcx - 41e781: 49 c7 00 00 00 00 00 movq $0x0,(%r8) - 41e788: 49 c7 40 08 00 00 00 movq $0x0,0x8(%r8) - 41e78f: 00 - 41e790: 49 c7 40 10 00 00 00 movq $0x0,0x10(%r8) - 41e797: 00 - 41e798: 4c 89 c0 mov %r8,%rax - 41e79b: 0f 86 53 ff ff ff jbe 41e6f4 <__calloc+0x134> - 41e7a1: 48 83 f9 06 cmp $0x6,%rcx - 41e7a5: 49 c7 40 18 00 00 00 movq $0x0,0x18(%r8) - 41e7ac: 00 - 41e7ad: 49 c7 40 20 00 00 00 movq $0x0,0x20(%r8) - 41e7b4: 00 - 41e7b5: 0f 86 39 ff ff ff jbe 41e6f4 <__calloc+0x134> - 41e7bb: 48 83 f9 09 cmp $0x9,%rcx - 41e7bf: 49 c7 40 28 00 00 00 movq $0x0,0x28(%r8) - 41e7c6: 00 - 41e7c7: 49 c7 40 30 00 00 00 movq $0x0,0x30(%r8) - 41e7ce: 00 - 41e7cf: 0f 85 1f ff ff ff jne 41e6f4 <__calloc+0x134> - 41e7d5: 49 c7 40 38 00 00 00 movq $0x0,0x38(%r8) - 41e7dc: 00 - 41e7dd: 49 c7 40 40 00 00 00 movq $0x0,0x40(%r8) - 41e7e4: 00 - 41e7e5: e9 0a ff ff ff jmpq 41e6f4 <__calloc+0x134> - 41e7ea: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 41e7f0: 48 89 ee mov %rbp,%rsi - 41e7f3: bf 00 a8 6c 00 mov $0x6ca800,%edi - 41e7f8: e8 43 cd ff ff callq 41b540 <_int_malloc> - 41e7fd: 48 85 c0 test %rax,%rax - 41e800: 49 89 c0 mov %rax,%r8 - 41e803: 0f 85 7b fe ff ff jne 41e684 <__calloc+0xc4> - 41e809: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 41e810: 90 nop - 41e811: 48 89 df mov %rbx,%rdi - 41e814: 48 89 ee mov %rbp,%rsi - 41e817: e8 d4 91 ff ff callq 4179f0 - 41e81c: 48 89 ee mov %rbp,%rsi - 41e81f: 48 89 c3 mov %rax,%rbx - 41e822: 48 89 c7 mov %rax,%rdi - 41e825: e8 16 cd ff ff callq 41b540 <_int_malloc> - 41e82a: 48 85 db test %rbx,%rbx - 41e82d: 49 89 c0 mov %rax,%r8 - 41e830: 0f 85 71 fe ff ff jne 41e6a7 <__calloc+0xe7> - 41e836: e9 96 fe ff ff jmpq 41e6d1 <__calloc+0x111> - 41e83b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41e840: a8 04 test $0x4,%al - 41e842: 0f 84 af 00 00 00 je 41e8f7 <__calloc+0x337> - 41e848: 45 31 e4 xor %r12d,%r12d - 41e84b: 45 31 ed xor %r13d,%r13d - 41e84e: 66 90 xchg %ax,%ax - 41e850: 49 8d 40 f0 lea -0x10(%r8),%rax - 41e854: 48 25 00 00 00 fc and $0xfffffffffc000000,%rax - 41e85a: 48 8b 10 mov (%rax),%rdx - 41e85d: e9 37 fe ff ff jmpq 41e699 <__calloc+0xd9> - 41e862: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 41e868: 48 89 ea mov %rbp,%rdx - 41e86b: 31 f6 xor %esi,%esi - 41e86d: 4c 89 c7 mov %r8,%rdi - 41e870: 48 83 c4 08 add $0x8,%rsp - 41e874: 5b pop %rbx - 41e875: 5d pop %rbp - 41e876: 41 5c pop %r12 - 41e878: 41 5d pop %r13 - 41e87a: e9 d1 1a fe ff jmpq 400350 <__rela_iplt_end+0x88> - 41e87f: 90 nop - 41e880: 48 8b 74 24 28 mov 0x28(%rsp),%rsi - 41e885: 48 89 ef mov %rbp,%rdi - 41e888: ff d0 callq *%rax - 41e88a: 31 f6 xor %esi,%esi - 41e88c: 48 85 c0 test %rax,%rax - 41e88f: 48 89 ea mov %rbp,%rdx - 41e892: 48 89 c7 mov %rax,%rdi - 41e895: 75 d9 jne 41e870 <__calloc+0x2b0> - 41e897: 31 c0 xor %eax,%eax - 41e899: e9 56 fe ff ff jmpq 41e6f4 <__calloc+0x134> - 41e89e: 66 90 xchg %ax,%ax - 41e8a0: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 41e8a7: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) - 41e8ae: 31 c0 xor %eax,%eax - 41e8b0: e9 3f fe ff ff jmpq 41e6f4 <__calloc+0x134> - 41e8b5: 0f 1f 00 nopl (%rax) - 41e8b8: 31 f6 xor %esi,%esi - 41e8ba: 48 89 ef mov %rbp,%rdi - 41e8bd: e8 8e 8b ff ff callq 417450 - 41e8c2: 48 85 c0 test %rax,%rax - 41e8c5: 48 89 c3 mov %rax,%rbx - 41e8c8: 0f 85 6f fd ff ff jne 41e63d <__calloc+0x7d> - 41e8ce: 31 ff xor %edi,%edi - 41e8d0: 48 89 ee mov %rbp,%rsi - 41e8d3: e8 68 cc ff ff callq 41b540 <_int_malloc> - 41e8d8: 48 85 c0 test %rax,%rax - 41e8db: 49 89 c0 mov %rax,%r8 - 41e8de: 74 b7 je 41e897 <__calloc+0x2d7> - 41e8e0: 48 8b 40 f8 mov -0x8(%rax),%rax - 41e8e4: a8 02 test $0x2,%al - 41e8e6: 0f 84 54 ff ff ff je 41e840 <__calloc+0x280> - 41e8ec: 45 31 e4 xor %r12d,%r12d - 41e8ef: 45 31 ed xor %r13d,%r13d - 41e8f2: e9 e3 fd ff ff jmpq 41e6da <__calloc+0x11a> - 41e8f7: b9 f8 2d 4a 00 mov $0x4a2df8,%ecx - 41e8fc: ba a8 0c 00 00 mov $0xca8,%edx - 41e901: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 41e906: bf 78 2a 4a 00 mov $0x4a2a78,%edi - 41e90b: e8 10 85 ff ff callq 416e20 <__malloc_assert> - 41e910: b9 f8 2d 4a 00 mov $0x4a2df8,%ecx - 41e915: ba d3 0c 00 00 mov $0xcd3,%edx - 41e91a: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 41e91f: bf e1 21 4a 00 mov $0x4a21e1,%edi - 41e924: e8 f7 84 ff ff callq 416e20 <__malloc_assert> - 41e929: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - -000000000041e930 <__malloc_usable_size>: - 41e930: 41 55 push %r13 - 41e932: 41 54 push %r12 - 41e934: 55 push %rbp - 41e935: 53 push %rbx - 41e936: 48 83 ec 28 sub $0x28,%rsp - 41e93a: 48 85 ff test %rdi,%rdi - 41e93d: 74 5a je 41e999 <__malloc_usable_size+0x69> - 41e93f: 83 3d c6 dc 2a 00 01 cmpl $0x1,0x2adcc6(%rip) # 6cc60c - 41e946: 48 8d 4f f0 lea -0x10(%rdi),%rcx - 41e94a: 74 64 je 41e9b0 <__malloc_usable_size+0x80> - 41e94c: 48 8b 47 f8 mov -0x8(%rdi),%rax - 41e950: a8 02 test $0x2,%al - 41e952: 75 1c jne 41e970 <__malloc_usable_size+0x40> - 41e954: 48 83 e0 f8 and $0xfffffffffffffff8,%rax - 41e958: f6 44 07 f8 01 testb $0x1,-0x8(%rdi,%rax,1) - 41e95d: 74 3a je 41e999 <__malloc_usable_size+0x69> - 41e95f: 48 83 e8 08 sub $0x8,%rax - 41e963: 48 83 c4 28 add $0x28,%rsp - 41e967: 5b pop %rbx - 41e968: 5d pop %rbp - 41e969: 41 5c pop %r12 - 41e96b: 41 5d pop %r13 - 41e96d: c3 retq - 41e96e: 66 90 xchg %ax,%ax - 41e970: 48 83 e0 f8 and $0xfffffffffffffff8,%rax - 41e974: 48 83 c4 28 add $0x28,%rsp - 41e978: 48 83 e8 10 sub $0x10,%rax - 41e97c: 5b pop %rbx - 41e97d: 5d pop %rbp - 41e97e: 41 5c pop %r12 - 41e980: 41 5d pop %r13 - 41e982: c3 retq - 41e983: 83 e3 02 and $0x2,%ebx - 41e986: ba d0 2a 4a 00 mov $0x4a2ad0,%edx - 41e98b: be 3c ca 4b 00 mov $0x4bca3c,%esi - 41e990: 89 df mov %ebx,%edi - 41e992: 31 c0 xor %eax,%eax - 41e994: e8 27 2c ff ff callq 4115c0 <__libc_message> - 41e999: 48 83 c4 28 add $0x28,%rsp - 41e99d: 31 c0 xor %eax,%eax - 41e99f: 5b pop %rbx - 41e9a0: 5d pop %rbp - 41e9a1: 41 5c pop %r12 - 41e9a3: 41 5d pop %r13 - 41e9a5: c3 retq - 41e9a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41e9ad: 00 00 00 - 41e9b0: 4c 8b 4f f8 mov -0x8(%rdi),%r9 - 41e9b4: 49 89 c8 mov %rcx,%r8 - 41e9b7: 48 89 c8 mov %rcx,%rax - 41e9ba: 48 c1 e8 0b shr $0xb,%rax - 41e9be: 49 c1 e8 03 shr $0x3,%r8 - 41e9c2: 41 31 c0 xor %eax,%r8d - 41e9c5: b8 02 00 00 00 mov $0x2,%eax - 41e9ca: 41 80 f8 01 cmp $0x1,%r8b - 41e9ce: 4d 89 ca mov %r9,%r10 - 41e9d1: 4c 89 ca mov %r9,%rdx - 41e9d4: 44 0f 44 c0 cmove %eax,%r8d - 41e9d8: 41 83 e2 02 and $0x2,%r10d - 41e9dc: 48 83 e2 f8 and $0xfffffffffffffff8,%rdx - 41e9e0: 49 83 fa 01 cmp $0x1,%r10 - 41e9e4: 48 19 c0 sbb %rax,%rax - 41e9e7: 83 e0 08 and $0x8,%eax - 41e9ea: 48 8d 44 02 ff lea -0x1(%rdx,%rax,1),%rax - 41e9ef: 0f b6 54 07 f0 movzbl -0x10(%rdi,%rax,1),%edx - 41e9f4: 44 38 c2 cmp %r8b,%dl - 41e9f7: 0f 84 77 ff ff ff je 41e974 <__malloc_usable_size+0x44> - 41e9fd: 84 d2 test %dl,%dl - 41e9ff: 74 2c je 41ea2d <__malloc_usable_size+0xfd> - 41ea01: 48 8d 72 10 lea 0x10(%rdx),%rsi - 41ea05: 48 39 f0 cmp %rsi,%rax - 41ea08: 73 0f jae 41ea19 <__malloc_usable_size+0xe9> - 41ea0a: eb 21 jmp 41ea2d <__malloc_usable_size+0xfd> - 41ea0c: 0f 1f 40 00 nopl 0x0(%rax) - 41ea10: 48 8d 72 10 lea 0x10(%rdx),%rsi - 41ea14: 48 39 c6 cmp %rax,%rsi - 41ea17: 77 14 ja 41ea2d <__malloc_usable_size+0xfd> - 41ea19: 48 29 d0 sub %rdx,%rax - 41ea1c: 0f b6 14 01 movzbl (%rcx,%rax,1),%edx - 41ea20: 44 38 c2 cmp %r8b,%dl - 41ea23: 0f 84 4b ff ff ff je 41e974 <__malloc_usable_size+0x44> - 41ea29: 84 d2 test %dl,%dl - 41ea2b: 75 e3 jne 41ea10 <__malloc_usable_size+0xe0> - 41ea2d: 4d 85 d2 test %r10,%r10 - 41ea30: 8b 1d 3a bd 2a 00 mov 0x2abd3a(%rip),%ebx # 6ca770 - 41ea36: 75 1d jne 41ea55 <__malloc_usable_size+0x125> - 41ea38: 41 83 e1 04 and $0x4,%r9d - 41ea3c: 0f 84 be 00 00 00 je 41eb00 <__malloc_usable_size+0x1d0> - 41ea42: 48 81 e1 00 00 00 fc and $0xfffffffffc000000,%rcx - 41ea49: 48 8b 01 mov (%rcx),%rax - 41ea4c: 48 85 c0 test %rax,%rax - 41ea4f: 74 04 je 41ea55 <__malloc_usable_size+0x125> - 41ea51: 83 48 04 04 orl $0x4,0x4(%rax) - 41ea55: 89 d8 mov %ebx,%eax - 41ea57: 83 e0 05 and $0x5,%eax - 41ea5a: 83 f8 05 cmp $0x5,%eax - 41ea5d: 0f 84 20 ff ff ff je 41e983 <__malloc_usable_size+0x53> - 41ea63: f6 c3 01 test $0x1,%bl - 41ea66: 75 18 jne 41ea80 <__malloc_usable_size+0x150> - 41ea68: 83 e3 02 and $0x2,%ebx - 41ea6b: 0f 84 28 ff ff ff je 41e999 <__malloc_usable_size+0x69> - 41ea71: e8 8a f1 fe ff callq 40dc00 - 41ea76: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41ea7d: 00 00 00 - 41ea80: 48 8d 74 24 10 lea 0x10(%rsp),%rsi - 41ea85: 31 c9 xor %ecx,%ecx - 41ea87: ba 10 00 00 00 mov $0x10,%edx - 41ea8c: c6 44 24 10 00 movb $0x0,0x10(%rsp) - 41ea91: e8 1a 34 03 00 callq 451eb0 <_itoa_word> - 41ea96: 48 39 e0 cmp %rsp,%rax - 41ea99: 48 89 c5 mov %rax,%rbp - 41ea9c: 76 25 jbe 41eac3 <__malloc_usable_size+0x193> - 41ea9e: 48 89 c2 mov %rax,%rdx - 41eaa1: 48 89 c7 mov %rax,%rdi - 41eaa4: be 30 00 00 00 mov $0x30,%esi - 41eaa9: 48 29 e2 sub %rsp,%rdx - 41eaac: 4c 8d 68 ff lea -0x1(%rax),%r13 - 41eab0: 48 29 d7 sub %rdx,%rdi - 41eab3: e8 98 18 fe ff callq 400350 <__rela_iplt_end+0x88> - 41eab8: 48 8d 44 24 ff lea -0x1(%rsp),%rax - 41eabd: 4c 29 e8 sub %r13,%rax - 41eac0: 48 01 c5 add %rax,%rbp - 41eac3: 48 8b 05 f6 e7 2a 00 mov 0x2ae7f6(%rip),%rax # 6cd2c0 <__libc_argv> - 41eaca: ba 38 20 4a 00 mov $0x4a2038,%edx - 41eacf: 49 89 e8 mov %rbp,%r8 - 41ead2: b9 d0 2a 4a 00 mov $0x4a2ad0,%ecx - 41ead7: be a8 23 4a 00 mov $0x4a23a8,%esi - 41eadc: 48 8b 00 mov (%rax),%rax - 41eadf: 48 85 c0 test %rax,%rax - 41eae2: 48 0f 45 d0 cmovne %rax,%rdx - 41eae6: 83 e3 02 and $0x2,%ebx - 41eae9: 31 c0 xor %eax,%eax - 41eaeb: 89 df mov %ebx,%edi - 41eaed: e8 ce 2a ff ff callq 4115c0 <__libc_message> - 41eaf2: 31 c0 xor %eax,%eax - 41eaf4: e9 6a fe ff ff jmpq 41e963 <__malloc_usable_size+0x33> - 41eaf9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 41eb00: b8 00 a8 6c 00 mov $0x6ca800,%eax - 41eb05: e9 47 ff ff ff jmpq 41ea51 <__malloc_usable_size+0x121> - 41eb0a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - -000000000041eb10 <__libc_mallopt>: - 41eb10: 55 push %rbp - 41eb11: 53 push %rbx - 41eb12: 48 63 ee movslq %esi,%rbp - 41eb15: 89 fb mov %edi,%ebx - 41eb17: 48 83 ec 08 sub $0x8,%rsp - 41eb1b: 8b 05 43 bc 2a 00 mov 0x2abc43(%rip),%eax # 6ca764 <__libc_malloc_initialized> - 41eb21: 85 c0 test %eax,%eax - 41eb23: 0f 88 b7 01 00 00 js 41ece0 <__libc_mallopt+0x1d0> - 41eb29: be 01 00 00 00 mov $0x1,%esi - 41eb2e: 31 c0 xor %eax,%eax - 41eb30: 83 3d 85 e6 2a 00 00 cmpl $0x0,0x2ae685(%rip) # 6cd1bc <__libc_multiple_threads> - 41eb37: 74 0c je 41eb45 <__libc_mallopt+0x35> - 41eb39: f0 0f b1 35 bf bc 2a lock cmpxchg %esi,0x2abcbf(%rip) # 6ca800 - 41eb40: 00 - 41eb41: 75 0b jne 41eb4e <__libc_mallopt+0x3e> - 41eb43: eb 23 jmp 41eb68 <__libc_mallopt+0x58> - 41eb45: 0f b1 35 b4 bc 2a 00 cmpxchg %esi,0x2abcb4(%rip) # 6ca800 - 41eb4c: 74 1a je 41eb68 <__libc_mallopt+0x58> - 41eb4e: 48 8d 3d ab bc 2a 00 lea 0x2abcab(%rip),%rdi # 6ca800 - 41eb55: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41eb5c: e8 6f 3a 02 00 callq 4425d0 <__lll_lock_wait_private> - 41eb61: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41eb68: bf 00 a8 6c 00 mov $0x6ca800,%edi - 41eb6d: e8 be 92 ff ff callq 417e30 - 41eb72: 90 nop - 41eb73: 83 c3 08 add $0x8,%ebx - 41eb76: 83 fb 09 cmp $0x9,%ebx - 41eb79: 0f 87 ba 00 00 00 ja 41ec39 <__libc_mallopt+0x129> - 41eb7f: ff 24 dd d8 2e 4a 00 jmpq *0x4a2ed8(,%rbx,8) - 41eb86: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41eb8d: 00 00 00 - 41eb90: 31 d2 xor %edx,%edx - 41eb92: 81 fd a0 00 00 00 cmp $0xa0,%ebp - 41eb98: 77 37 ja 41ebd1 <__libc_mallopt+0xc1> - 41eb9a: 90 nop - 41eb9b: 85 ed test %ebp,%ebp - 41eb9d: b8 10 00 00 00 mov $0x10,%eax - 41eba2: 74 08 je 41ebac <__libc_mallopt+0x9c> - 41eba4: 48 8d 45 08 lea 0x8(%rbp),%rax - 41eba8: 48 83 e0 f0 and $0xfffffffffffffff0,%rax - 41ebac: 48 89 05 85 da 2a 00 mov %rax,0x2ada85(%rip) # 6cc638 - 41ebb3: ba 01 00 00 00 mov $0x1,%edx - 41ebb8: eb 17 jmp 41ebd1 <__libc_mallopt+0xc1> - 41ebba: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 41ebc0: 85 ed test %ebp,%ebp - 41ebc2: 7e 75 jle 41ec39 <__libc_mallopt+0x129> - 41ebc4: 90 nop - 41ebc5: ba 01 00 00 00 mov $0x1,%edx - 41ebca: 48 89 2d ef bb 2a 00 mov %rbp,0x2abbef(%rip) # 6ca7c0 - 41ebd1: 83 3d e4 e5 2a 00 00 cmpl $0x0,0x2ae5e4(%rip) # 6cd1bc <__libc_multiple_threads> - 41ebd8: 74 0b je 41ebe5 <__libc_mallopt+0xd5> - 41ebda: f0 ff 0d 1f bc 2a 00 lock decl 0x2abc1f(%rip) # 6ca800 - 41ebe1: 75 0a jne 41ebed <__libc_mallopt+0xdd> - 41ebe3: eb 22 jmp 41ec07 <__libc_mallopt+0xf7> - 41ebe5: ff 0d 15 bc 2a 00 decl 0x2abc15(%rip) # 6ca800 - 41ebeb: 74 1a je 41ec07 <__libc_mallopt+0xf7> - 41ebed: 48 8d 3d 0c bc 2a 00 lea 0x2abc0c(%rip),%rdi # 6ca800 - 41ebf4: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41ebfb: e8 00 3a 02 00 callq 442600 <__lll_unlock_wake_private> - 41ec00: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41ec07: 48 83 c4 08 add $0x8,%rsp - 41ec0b: 89 d0 mov %edx,%eax - 41ec0d: 5b pop %rbx - 41ec0e: 5d pop %rbp - 41ec0f: c3 retq - 41ec10: 85 ed test %ebp,%ebp - 41ec12: 7e 25 jle 41ec39 <__libc_mallopt+0x129> - 41ec14: 90 nop - 41ec15: ba 01 00 00 00 mov $0x1,%edx - 41ec1a: 48 89 2d 97 bb 2a 00 mov %rbp,0x2abb97(%rip) # 6ca7b8 - 41ec21: eb ae jmp 41ebd1 <__libc_mallopt+0xc1> - 41ec23: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41ec28: 90 nop - 41ec29: c7 05 a1 bb 2a 00 01 movl $0x1,0x2abba1(%rip) # 6ca7d4 - 41ec30: 00 00 00 - 41ec33: 89 2d 93 bb 2a 00 mov %ebp,0x2abb93(%rip) # 6ca7cc - 41ec39: ba 01 00 00 00 mov $0x1,%edx - 41ec3e: eb 91 jmp 41ebd1 <__libc_mallopt+0xc1> - 41ec40: 31 d2 xor %edx,%edx - 41ec42: 81 fd 00 00 00 02 cmp $0x2000000,%ebp - 41ec48: 0f 87 83 ff ff ff ja 41ebd1 <__libc_mallopt+0xc1> - 41ec4e: 90 nop - 41ec4f: c7 05 7b bb 2a 00 01 movl $0x1,0x2abb7b(%rip) # 6ca7d4 - 41ec56: 00 00 00 - 41ec59: 48 89 2d 50 bb 2a 00 mov %rbp,0x2abb50(%rip) # 6ca7b0 - 41ec60: ba 01 00 00 00 mov $0x1,%edx - 41ec65: e9 67 ff ff ff jmpq 41ebd1 <__libc_mallopt+0xc1> - 41ec6a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 41ec70: 90 nop - 41ec71: c7 05 59 bb 2a 00 01 movl $0x1,0x2abb59(%rip) # 6ca7d4 - 41ec78: 00 00 00 - 41ec7b: 48 89 2d 26 bb 2a 00 mov %rbp,0x2abb26(%rip) # 6ca7a8 - 41ec82: ba 01 00 00 00 mov $0x1,%edx - 41ec87: e9 45 ff ff ff jmpq 41ebd1 <__libc_mallopt+0xc1> - 41ec8c: 0f 1f 40 00 nopl 0x0(%rax) - 41ec90: 90 nop - 41ec91: c7 05 39 bb 2a 00 01 movl $0x1,0x2abb39(%rip) # 6ca7d4 - 41ec98: 00 00 00 - 41ec9b: 48 89 2d fe ba 2a 00 mov %rbp,0x2abafe(%rip) # 6ca7a0 - 41eca2: ba 01 00 00 00 mov $0x1,%edx - 41eca7: e9 25 ff ff ff jmpq 41ebd1 <__libc_mallopt+0xc1> - 41ecac: 0f 1f 40 00 nopl 0x0(%rax) - 41ecb0: 90 nop - 41ecb1: ba 01 00 00 00 mov $0x1,%edx - 41ecb6: 89 2d 78 d9 2a 00 mov %ebp,0x2ad978(%rip) # 6cc634 - 41ecbc: e9 10 ff ff ff jmpq 41ebd1 <__libc_mallopt+0xc1> - 41ecc1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 41ecc8: 90 nop - 41ecc9: ba 01 00 00 00 mov $0x1,%edx - 41ecce: 89 2d 9c ba 2a 00 mov %ebp,0x2aba9c(%rip) # 6ca770 - 41ecd4: e9 f8 fe ff ff jmpq 41ebd1 <__libc_mallopt+0xc1> - 41ecd9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 41ece0: e8 0b 00 00 00 callq 41ecf0 - 41ece5: e9 3f fe ff ff jmpq 41eb29 <__libc_mallopt+0x19> - 41ecea: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - -000000000041ecf0 : - 41ecf0: 41 55 push %r13 - 41ecf2: 41 54 push %r12 - 41ecf4: 55 push %rbp - 41ecf5: 53 push %rbx - 41ecf6: 48 83 ec 08 sub $0x8,%rsp - 41ecfa: 4c 8b 25 3f d9 2a 00 mov 0x2ad93f(%rip),%r12 # 6cc640 <__environ> - 41ed01: 48 c7 c0 d8 ff ff ff mov $0xffffffffffffffd8,%rax - 41ed08: c7 05 52 ba 2a 00 00 movl $0x0,0x2aba52(%rip) # 6ca764 <__libc_malloc_initialized> - 41ed0f: 00 00 00 - 41ed12: 4d 85 e4 test %r12,%r12 - 41ed15: 64 48 c7 00 00 a8 6c movq $0x6ca800,%fs:(%rax) - 41ed1c: 00 - 41ed1d: 0f 84 9b 00 00 00 je 41edbe - 41ed23: 45 31 ed xor %r13d,%r13d - 41ed26: eb 0c jmp 41ed34 - 41ed28: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 41ed2f: 00 - 41ed30: 49 83 c4 08 add $0x8,%r12 - 41ed34: 49 8b 1c 24 mov (%r12),%rbx - 41ed38: 48 85 db test %rbx,%rbx - 41ed3b: 74 73 je 41edb0 - 41ed3d: 80 3b 4d cmpb $0x4d,(%rbx) - 41ed40: 75 ee jne 41ed30 - 41ed42: 80 7b 01 41 cmpb $0x41,0x1(%rbx) - 41ed46: 75 e8 jne 41ed30 - 41ed48: 80 7b 02 4c cmpb $0x4c,0x2(%rbx) - 41ed4c: 75 e2 jne 41ed30 - 41ed4e: 80 7b 03 4c cmpb $0x4c,0x3(%rbx) - 41ed52: 75 dc jne 41ed30 - 41ed54: 80 7b 04 4f cmpb $0x4f,0x4(%rbx) - 41ed58: 75 d6 jne 41ed30 - 41ed5a: 80 7b 05 43 cmpb $0x43,0x5(%rbx) - 41ed5e: 75 d0 jne 41ed30 - 41ed60: 80 7b 06 5f cmpb $0x5f,0x6(%rbx) - 41ed64: 75 ca jne 41ed30 - 41ed66: 48 89 dd mov %rbx,%rbp - 41ed69: 49 83 c4 08 add $0x8,%r12 - 41ed6d: 48 83 c5 07 add $0x7,%rbp - 41ed71: 74 3d je 41edb0 - 41ed73: 0f b6 53 07 movzbl 0x7(%rbx),%edx - 41ed77: 84 d2 test %dl,%dl - 41ed79: 74 b9 je 41ed34 - 41ed7b: 31 c0 xor %eax,%eax - 41ed7d: 80 fa 3d cmp $0x3d,%dl - 41ed80: 74 b2 je 41ed34 - 41ed82: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 41ed88: 48 83 c0 01 add $0x1,%rax - 41ed8c: 0f b6 54 03 07 movzbl 0x7(%rbx,%rax,1),%edx - 41ed91: 84 d2 test %dl,%dl - 41ed93: 74 9f je 41ed34 - 41ed95: 80 fa 3d cmp $0x3d,%dl - 41ed98: 75 ee jne 41ed88 - 41ed9a: 48 83 e8 06 sub $0x6,%rax - 41ed9e: 48 83 f8 09 cmp $0x9,%rax - 41eda2: 77 90 ja 41ed34 - 41eda4: ff 24 c5 28 2f 4a 00 jmpq *0x4a2f28(,%rax,8) - 41edab: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41edb0: 4d 85 ed test %r13,%r13 - 41edb3: 74 09 je 41edbe - 41edb5: 41 0f be 45 00 movsbl 0x0(%r13),%eax - 41edba: 84 c0 test %al,%al - 41edbc: 75 2a jne 41ede8 - 41edbe: 48 8b 05 2b d8 2a 00 mov 0x2ad82b(%rip),%rax # 6cc5f0 <__malloc_initialize_hook> - 41edc5: 48 85 c0 test %rax,%rax - 41edc8: 74 02 je 41edcc - 41edca: ff d0 callq *%rax - 41edcc: c7 05 8e b9 2a 00 01 movl $0x1,0x2ab98e(%rip) # 6ca764 <__libc_malloc_initialized> - 41edd3: 00 00 00 - 41edd6: 48 83 c4 08 add $0x8,%rsp - 41edda: 5b pop %rbx - 41eddb: 5d pop %rbp - 41eddc: 41 5c pop %r12 - 41edde: 41 5d pop %r13 - 41ede0: c3 retq - 41ede1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 41ede8: 8d 70 d0 lea -0x30(%rax),%esi - 41edeb: bf fb ff ff ff mov $0xfffffffb,%edi - 41edf0: e8 1b fd ff ff callq 41eb10 <__libc_mallopt> - 41edf5: 8b 15 75 b9 2a 00 mov 0x2ab975(%rip),%edx # 6ca770 - 41edfb: 85 d2 test %edx,%edx - 41edfd: 74 bf je 41edbe - 41edff: 8b 05 03 d8 2a 00 mov 0x2ad803(%rip),%eax # 6cc608 - 41ee05: 85 c0 test %eax,%eax - 41ee07: 0f 84 ac 01 00 00 je 41efb9 - 41ee0d: c7 05 f1 d7 2a 00 00 movl $0x0,0x2ad7f1(%rip) # 6cc608 - 41ee14: 00 00 00 - 41ee17: eb a5 jmp 41edbe - 41ee19: 8b 0d 79 b1 2a 00 mov 0x2ab179(%rip),%ecx # 6c9f98 <__libc_enable_secure> - 41ee1f: 85 c9 test %ecx,%ecx - 41ee21: 0f 85 0d ff ff ff jne 41ed34 - 41ee27: ba 0f 00 00 00 mov $0xf,%edx - 41ee2c: be 1f 22 4a 00 mov $0x4a221f,%esi - 41ee31: 48 89 ef mov %rbp,%rdi - 41ee34: e8 f7 14 fe ff callq 400330 <__rela_iplt_end+0x68> - 41ee39: 85 c0 test %eax,%eax - 41ee3b: 0f 84 d4 01 00 00 je 41f015 - 41ee41: ba 0f 00 00 00 mov $0xf,%edx - 41ee46: be 2f 22 4a 00 mov $0x4a222f,%esi - 41ee4b: 48 89 ef mov %rbp,%rdi - 41ee4e: e8 dd 14 fe ff callq 400330 <__rela_iplt_end+0x68> - 41ee53: 85 c0 test %eax,%eax - 41ee55: 0f 85 d9 fe ff ff jne 41ed34 - 41ee5b: 48 8d 7b 17 lea 0x17(%rbx),%rdi - 41ee5f: 31 f6 xor %esi,%esi - 41ee61: ba 0a 00 00 00 mov $0xa,%edx - 41ee66: e8 65 2b 03 00 callq 4519d0 <__strtol> - 41ee6b: bf fd ff ff ff mov $0xfffffffd,%edi - 41ee70: 89 c6 mov %eax,%esi - 41ee72: e8 99 fc ff ff callq 41eb10 <__libc_mallopt> - 41ee77: e9 b8 fe ff ff jmpq 41ed34 - 41ee7c: 0f 1f 40 00 nopl 0x0(%rax) - 41ee80: 8b 35 12 b1 2a 00 mov 0x2ab112(%rip),%esi # 6c9f98 <__libc_enable_secure> - 41ee86: 85 f6 test %esi,%esi - 41ee88: 0f 85 a6 fe ff ff jne 41ed34 - 41ee8e: ba 0a 00 00 00 mov $0xa,%edx - 41ee93: be 14 22 4a 00 mov $0x4a2214,%esi - 41ee98: 48 89 ef mov %rbp,%rdi - 41ee9b: e8 90 14 fe ff callq 400330 <__rela_iplt_end+0x68> - 41eea0: 85 c0 test %eax,%eax - 41eea2: 0f 85 8c fe ff ff jne 41ed34 - 41eea8: 48 8d 7b 12 lea 0x12(%rbx),%rdi - 41eeac: 31 f6 xor %esi,%esi - 41eeae: ba 0a 00 00 00 mov $0xa,%edx - 41eeb3: e8 18 2b 03 00 callq 4519d0 <__strtol> - 41eeb8: bf f9 ff ff ff mov $0xfffffff9,%edi - 41eebd: 89 c6 mov %eax,%esi - 41eebf: e8 4c fc ff ff callq 41eb10 <__libc_mallopt> - 41eec4: e9 6b fe ff ff jmpq 41ed34 - 41eec9: 8b 3d c9 b0 2a 00 mov 0x2ab0c9(%rip),%edi # 6c9f98 <__libc_enable_secure> - 41eecf: 85 ff test %edi,%edi - 41eed1: 0f 85 5d fe ff ff jne 41ed34 - 41eed7: ba 09 00 00 00 mov $0x9,%edx - 41eedc: be 00 22 4a 00 mov $0x4a2200,%esi - 41eee1: 48 89 ef mov %rbp,%rdi - 41eee4: e8 47 14 fe ff callq 400330 <__rela_iplt_end+0x68> - 41eee9: 85 c0 test %eax,%eax - 41eeeb: 0f 84 45 01 00 00 je 41f036 - 41eef1: ba 09 00 00 00 mov $0x9,%edx - 41eef6: be 0a 22 4a 00 mov $0x4a220a,%esi - 41eefb: 48 89 ef mov %rbp,%rdi - 41eefe: e8 2d 14 fe ff callq 400330 <__rela_iplt_end+0x68> - 41ef03: 85 c0 test %eax,%eax - 41ef05: 0f 85 29 fe ff ff jne 41ed34 - 41ef0b: 48 8d 7b 11 lea 0x11(%rbx),%rdi - 41ef0f: 31 f6 xor %esi,%esi - 41ef11: ba 0a 00 00 00 mov $0xa,%edx - 41ef16: e8 b5 2a 03 00 callq 4519d0 <__strtol> - 41ef1b: bf f8 ff ff ff mov $0xfffffff8,%edi - 41ef20: 89 c6 mov %eax,%esi - 41ef22: e8 e9 fb ff ff callq 41eb10 <__libc_mallopt> - 41ef27: e9 08 fe ff ff jmpq 41ed34 - 41ef2c: 0f 1f 40 00 nopl 0x0(%rax) - 41ef30: 44 8b 05 61 b0 2a 00 mov 0x2ab061(%rip),%r8d # 6c9f98 <__libc_enable_secure> - 41ef37: 45 85 c0 test %r8d,%r8d - 41ef3a: 0f 85 f4 fd ff ff jne 41ed34 - 41ef40: ba 08 00 00 00 mov $0x8,%edx - 41ef45: be ee 21 4a 00 mov $0x4a21ee,%esi - 41ef4a: 48 89 ef mov %rbp,%rdi - 41ef4d: e8 de 13 fe ff callq 400330 <__rela_iplt_end+0x68> - 41ef52: 85 c0 test %eax,%eax - 41ef54: 0f 84 9a 00 00 00 je 41eff4 - 41ef5a: ba 08 00 00 00 mov $0x8,%edx - 41ef5f: be f7 21 4a 00 mov $0x4a21f7,%esi - 41ef64: 48 89 ef mov %rbp,%rdi - 41ef67: e8 c4 13 fe ff callq 400330 <__rela_iplt_end+0x68> - 41ef6c: 85 c0 test %eax,%eax - 41ef6e: 0f 85 c0 fd ff ff jne 41ed34 - 41ef74: 48 8d 7b 10 lea 0x10(%rbx),%rdi - 41ef78: 31 f6 xor %esi,%esi - 41ef7a: ba 0a 00 00 00 mov $0xa,%edx - 41ef7f: e8 4c 2a 03 00 callq 4519d0 <__strtol> - 41ef84: bf fa ff ff ff mov $0xfffffffa,%edi - 41ef89: 89 c6 mov %eax,%esi - 41ef8b: e8 80 fb ff ff callq 41eb10 <__libc_mallopt> - 41ef90: e9 9f fd ff ff jmpq 41ed34 - 41ef95: 0f 1f 00 nopl (%rax) - 41ef98: ba 06 00 00 00 mov $0x6,%edx - 41ef9d: be b9 4f 4a 00 mov $0x4a4fb9,%esi - 41efa2: 48 89 ef mov %rbp,%rdi - 41efa5: 48 83 c3 0e add $0xe,%rbx - 41efa9: e8 82 13 fe ff callq 400330 <__rela_iplt_end+0x68> - 41efae: 85 c0 test %eax,%eax - 41efb0: 4c 0f 44 eb cmove %rbx,%r13 - 41efb4: e9 7b fd ff ff jmpq 41ed34 - 41efb9: c7 05 49 d6 2a 00 01 movl $0x1,0x2ad649(%rip) # 6cc60c - 41efc0: 00 00 00 - 41efc3: 48 c7 05 ba b7 2a 00 movq $0x41c720,0x2ab7ba(%rip) # 6ca788 <__malloc_hook> - 41efca: 20 c7 41 00 - 41efce: 48 c7 05 0f d6 2a 00 movq $0x4189e0,0x2ad60f(%rip) # 6cc5e8 <__free_hook> - 41efd5: e0 89 41 00 - 41efd9: 48 c7 05 9c b7 2a 00 movq $0x41d180,0x2ab79c(%rip) # 6ca780 <__realloc_hook> - 41efe0: 80 d1 41 00 - 41efe4: 48 c7 05 89 b7 2a 00 movq $0x41c870,0x2ab789(%rip) # 6ca778 <__memalign_hook> - 41efeb: 70 c8 41 00 - 41efef: e9 ca fd ff ff jmpq 41edbe - 41eff4: 48 8d 7b 10 lea 0x10(%rbx),%rdi - 41eff8: 31 f6 xor %esi,%esi - 41effa: ba 0a 00 00 00 mov $0xa,%edx - 41efff: e8 cc 29 03 00 callq 4519d0 <__strtol> - 41f004: bf fe ff ff ff mov $0xfffffffe,%edi - 41f009: 89 c6 mov %eax,%esi - 41f00b: e8 00 fb ff ff callq 41eb10 <__libc_mallopt> - 41f010: e9 1f fd ff ff jmpq 41ed34 - 41f015: 48 8d 7b 17 lea 0x17(%rbx),%rdi - 41f019: 31 f6 xor %esi,%esi - 41f01b: ba 0a 00 00 00 mov $0xa,%edx - 41f020: e8 ab 29 03 00 callq 4519d0 <__strtol> - 41f025: bf ff ff ff ff mov $0xffffffff,%edi - 41f02a: 89 c6 mov %eax,%esi - 41f02c: e8 df fa ff ff callq 41eb10 <__libc_mallopt> - 41f031: e9 fe fc ff ff jmpq 41ed34 - 41f036: 48 8d 7b 11 lea 0x11(%rbx),%rdi - 41f03a: 31 f6 xor %esi,%esi - 41f03c: ba 0a 00 00 00 mov $0xa,%edx - 41f041: e8 8a 29 03 00 callq 4519d0 <__strtol> - 41f046: bf fc ff ff ff mov $0xfffffffc,%edi - 41f04b: 89 c6 mov %eax,%esi - 41f04d: e8 be fa ff ff callq 41eb10 <__libc_mallopt> - 41f052: e9 dd fc ff ff jmpq 41ed34 - 41f057: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 41f05e: 00 00 - -000000000041f060 : - 41f060: 55 push %rbp - 41f061: 53 push %rbx - 41f062: 48 89 fd mov %rdi,%rbp - 41f065: 48 83 ec 08 sub $0x8,%rsp - 41f069: 8b 05 f5 b6 2a 00 mov 0x2ab6f5(%rip),%eax # 6ca764 <__libc_malloc_initialized> - 41f06f: 48 c7 05 0e b7 2a 00 movq $0x0,0x2ab70e(%rip) # 6ca788 <__malloc_hook> - 41f076: 00 00 00 00 - 41f07a: 85 c0 test %eax,%eax - 41f07c: 0f 88 46 01 00 00 js 41f1c8 - 41f082: 31 c0 xor %eax,%eax - 41f084: 48 85 c0 test %rax,%rax - 41f087: 0f 85 50 01 00 00 jne 41f1dd - 41f08d: 48 c7 c0 d8 ff ff ff mov $0xffffffffffffffd8,%rax - 41f094: 64 48 8b 18 mov %fs:(%rax),%rbx - 41f098: 48 85 db test %rbx,%rbx - 41f09b: 74 0c je 41f0a9 - 41f09d: 8b 43 04 mov 0x4(%rbx),%eax - 41f0a0: 83 e0 04 and $0x4,%eax - 41f0a3: 0f 84 8f 00 00 00 je 41f138 - 41f0a9: e8 b2 80 ff ff callq 417160 - 41f0ae: 48 85 c0 test %rax,%rax - 41f0b1: 48 89 c3 mov %rax,%rbx - 41f0b4: 0f 84 b6 00 00 00 je 41f170 - 41f0ba: 48 89 ee mov %rbp,%rsi - 41f0bd: 48 89 df mov %rbx,%rdi - 41f0c0: e8 7b c4 ff ff callq 41b540 <_int_malloc> - 41f0c5: 48 85 c0 test %rax,%rax - 41f0c8: 48 89 c2 mov %rax,%rdx - 41f0cb: 0f 84 c7 00 00 00 je 41f198 - 41f0d1: 83 3d e4 e0 2a 00 00 cmpl $0x0,0x2ae0e4(%rip) # 6cd1bc <__libc_multiple_threads> - 41f0d8: 74 07 je 41f0e1 - 41f0da: f0 ff 0b lock decl (%rbx) - 41f0dd: 75 06 jne 41f0e5 - 41f0df: eb 1a jmp 41f0fb - 41f0e1: ff 0b decl (%rbx) - 41f0e3: 74 16 je 41f0fb - 41f0e5: 48 8d 3b lea (%rbx),%rdi - 41f0e8: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41f0ef: e8 0c 35 02 00 callq 442600 <__lll_unlock_wake_private> - 41f0f4: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41f0fb: 48 85 d2 test %rdx,%rdx - 41f0fe: 0f 84 ec 00 00 00 je 41f1f0 - 41f104: 48 8b 42 f8 mov -0x8(%rdx),%rax - 41f108: a8 02 test $0x2,%al - 41f10a: 75 1f jne 41f12b - 41f10c: a8 04 test $0x4,%al - 41f10e: b9 00 a8 6c 00 mov $0x6ca800,%ecx - 41f113: 74 0d je 41f122 - 41f115: 48 8d 42 f0 lea -0x10(%rdx),%rax - 41f119: 48 25 00 00 00 fc and $0xfffffffffc000000,%rax - 41f11f: 48 8b 08 mov (%rax),%rcx - 41f122: 48 39 d9 cmp %rbx,%rcx - 41f125: 0f 85 cc 00 00 00 jne 41f1f7 - 41f12b: 48 89 d0 mov %rdx,%rax - 41f12e: 48 83 c4 08 add $0x8,%rsp - 41f132: 5b pop %rbx - 41f133: 5d pop %rbp - 41f134: c3 retq - 41f135: 0f 1f 00 nopl (%rax) - 41f138: be 01 00 00 00 mov $0x1,%esi - 41f13d: 83 3d 78 e0 2a 00 00 cmpl $0x0,0x2ae078(%rip) # 6cd1bc <__libc_multiple_threads> - 41f144: 74 08 je 41f14e - 41f146: f0 0f b1 33 lock cmpxchg %esi,(%rbx) - 41f14a: 75 07 jne 41f153 - 41f14c: eb 1b jmp 41f169 - 41f14e: 0f b1 33 cmpxchg %esi,(%rbx) - 41f151: 74 16 je 41f169 - 41f153: 48 8d 3b lea (%rbx),%rdi - 41f156: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41f15d: e8 6e 34 02 00 callq 4425d0 <__lll_lock_wait_private> - 41f162: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41f169: e9 4c ff ff ff jmpq 41f0ba - 41f16e: 66 90 xchg %ax,%ax - 41f170: 31 f6 xor %esi,%esi - 41f172: 48 89 ef mov %rbp,%rdi - 41f175: e8 d6 82 ff ff callq 417450 - 41f17a: 48 89 ee mov %rbp,%rsi - 41f17d: 48 89 c7 mov %rax,%rdi - 41f180: 48 89 c3 mov %rax,%rbx - 41f183: e8 b8 c3 ff ff callq 41b540 <_int_malloc> - 41f188: 48 85 c0 test %rax,%rax - 41f18b: 48 89 c2 mov %rax,%rdx - 41f18e: 75 25 jne 41f1b5 - 41f190: 48 85 db test %rbx,%rbx - 41f193: 74 20 je 41f1b5 - 41f195: 0f 1f 00 nopl (%rax) - 41f198: 90 nop - 41f199: 48 89 df mov %rbx,%rdi - 41f19c: 48 89 ee mov %rbp,%rsi - 41f19f: e8 4c 88 ff ff callq 4179f0 - 41f1a4: 48 89 ee mov %rbp,%rsi - 41f1a7: 48 89 c7 mov %rax,%rdi - 41f1aa: 48 89 c3 mov %rax,%rbx - 41f1ad: e8 8e c3 ff ff callq 41b540 <_int_malloc> - 41f1b2: 48 89 c2 mov %rax,%rdx - 41f1b5: 48 85 db test %rbx,%rbx - 41f1b8: 0f 85 13 ff ff ff jne 41f0d1 - 41f1be: e9 38 ff ff ff jmpq 41f0fb - 41f1c3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41f1c8: e8 23 fb ff ff callq 41ecf0 - 41f1cd: 48 8b 05 b4 b5 2a 00 mov 0x2ab5b4(%rip),%rax # 6ca788 <__malloc_hook> - 41f1d4: 48 85 c0 test %rax,%rax - 41f1d7: 0f 84 b0 fe ff ff je 41f08d - 41f1dd: 48 8b 74 24 18 mov 0x18(%rsp),%rsi - 41f1e2: 48 83 c4 08 add $0x8,%rsp - 41f1e6: 48 89 ef mov %rbp,%rdi - 41f1e9: 5b pop %rbx - 41f1ea: 5d pop %rbp - 41f1eb: ff e0 jmpq *%rax - 41f1ed: 0f 1f 00 nopl (%rax) - 41f1f0: 31 c0 xor %eax,%eax - 41f1f2: e9 37 ff ff ff jmpq 41f12e - 41f1f7: b9 48 2e 4a 00 mov $0x4a2e48,%ecx - 41f1fc: ba 6f 0b 00 00 mov $0xb6f,%edx - 41f201: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 41f206: bf 58 29 4a 00 mov $0x4a2958,%edi - 41f20b: e8 10 7c ff ff callq 416e20 <__malloc_assert> - -000000000041f210 : - 41f210: 41 57 push %r15 - 41f212: 41 56 push %r14 - 41f214: 41 55 push %r13 - 41f216: 41 54 push %r12 - 41f218: 49 89 f5 mov %rsi,%r13 - 41f21b: 55 push %rbp - 41f21c: 53 push %rbx - 41f21d: 48 89 fb mov %rdi,%rbx - 41f220: 48 83 ec 38 sub $0x38,%rsp - 41f224: 8b 05 3a b5 2a 00 mov 0x2ab53a(%rip),%eax # 6ca764 <__libc_malloc_initialized> - 41f22a: 48 c7 05 53 b5 2a 00 movq $0x0,0x2ab553(%rip) # 6ca788 <__malloc_hook> - 41f231: 00 00 00 00 - 41f235: 48 c7 05 40 b5 2a 00 movq $0x0,0x2ab540(%rip) # 6ca780 <__realloc_hook> - 41f23c: 00 00 00 00 - 41f240: 85 c0 test %eax,%eax - 41f242: 0f 88 18 02 00 00 js 41f460 - 41f248: 31 c0 xor %eax,%eax - 41f24a: 48 85 c0 test %rax,%rax - 41f24d: 0f 85 25 02 00 00 jne 41f478 - 41f253: 4d 85 ed test %r13,%r13 - 41f256: 75 09 jne 41f261 - 41f258: 48 85 db test %rbx,%rbx - 41f25b: 0f 85 8f 02 00 00 jne 41f4f0 - 41f261: 48 85 db test %rbx,%rbx - 41f264: 0f 84 1e 03 00 00 je 41f588 - 41f26a: 48 8b 43 f8 mov -0x8(%rbx),%rax - 41f26e: 4c 8d 73 f0 lea -0x10(%rbx),%r14 - 41f272: 49 89 c7 mov %rax,%r15 - 41f275: 48 89 c1 mov %rax,%rcx - 41f278: 49 83 e7 f8 and $0xfffffffffffffff8,%r15 - 41f27c: 83 e1 02 and $0x2,%ecx - 41f27f: 74 7f je 41f300 - 41f281: 4c 89 f8 mov %r15,%rax - 41f284: 48 f7 d8 neg %rax - 41f287: 49 39 c6 cmp %rax,%r14 - 41f28a: 0f 87 50 03 00 00 ja 41f5e0 - 41f290: 41 f6 c6 0f test $0xf,%r14b - 41f294: 0f 85 46 03 00 00 jne 41f5e0 - 41f29a: 45 31 e4 xor %r12d,%r12d - 41f29d: 49 83 fd bf cmp $0xffffffffffffffbf,%r13 - 41f2a1: 0f 87 e9 01 00 00 ja 41f490 - 41f2a7: 49 8d 45 17 lea 0x17(%r13),%rax - 41f2ab: 48 89 c2 mov %rax,%rdx - 41f2ae: 48 83 e2 f0 and $0xfffffffffffffff0,%rdx - 41f2b2: 48 83 f8 20 cmp $0x20,%rax - 41f2b6: b8 20 00 00 00 mov $0x20,%eax - 41f2bb: 48 0f 42 d0 cmovb %rax,%rdx - 41f2bf: 48 85 c9 test %rcx,%rcx - 41f2c2: 0f 84 98 00 00 00 je 41f360 - 41f2c8: 48 89 d6 mov %rdx,%rsi - 41f2cb: 4c 89 f7 mov %r14,%rdi - 41f2ce: 48 89 54 24 08 mov %rdx,0x8(%rsp) - 41f2d3: e8 48 7d ff ff callq 417020 - 41f2d8: 48 85 c0 test %rax,%rax - 41f2db: 48 8d 68 10 lea 0x10(%rax),%rbp - 41f2df: 48 8b 54 24 08 mov 0x8(%rsp),%rdx - 41f2e4: 0f 84 be 01 00 00 je 41f4a8 - 41f2ea: 48 83 c4 38 add $0x38,%rsp - 41f2ee: 48 89 e8 mov %rbp,%rax - 41f2f1: 5b pop %rbx - 41f2f2: 5d pop %rbp - 41f2f3: 41 5c pop %r12 - 41f2f5: 41 5d pop %r13 - 41f2f7: 41 5e pop %r14 - 41f2f9: 41 5f pop %r15 - 41f2fb: c3 retq - 41f2fc: 0f 1f 40 00 nopl 0x0(%rax) - 41f300: a8 04 test $0x4,%al - 41f302: 0f 84 28 01 00 00 je 41f430 - 41f308: 4c 89 f0 mov %r14,%rax - 41f30b: 48 25 00 00 00 fc and $0xfffffffffc000000,%rax - 41f311: 4c 8b 20 mov (%rax),%r12 - 41f314: 4c 89 f8 mov %r15,%rax - 41f317: 48 f7 d8 neg %rax - 41f31a: 49 39 c6 cmp %rax,%r14 - 41f31d: 77 0a ja 41f329 - 41f31f: 41 f6 c6 0f test $0xf,%r14b - 41f323: 0f 84 74 ff ff ff je 41f29d - 41f329: 4d 85 e4 test %r12,%r12 - 41f32c: 8b 2d 3e b4 2a 00 mov 0x2ab43e(%rip),%ebp # 6ca770 - 41f332: 74 06 je 41f33a - 41f334: 41 83 4c 24 04 04 orl $0x4,0x4(%r12) - 41f33a: 89 e8 mov %ebp,%eax - 41f33c: 83 e0 05 and $0x5,%eax - 41f33f: 83 f8 05 cmp $0x5,%eax - 41f342: 0f 84 a8 02 00 00 je 41f5f0 - 41f348: 40 f6 c5 01 test $0x1,%bpl - 41f34c: 0f 85 ae 01 00 00 jne 41f500 - 41f352: 83 e5 02 and $0x2,%ebp - 41f355: 0f 85 b2 02 00 00 jne 41f60d - 41f35b: 31 ed xor %ebp,%ebp - 41f35d: eb 8b jmp 41f2ea - 41f35f: 90 nop - 41f360: be 01 00 00 00 mov $0x1,%esi - 41f365: 31 c0 xor %eax,%eax - 41f367: 83 3d 4e de 2a 00 00 cmpl $0x0,0x2ade4e(%rip) # 6cd1bc <__libc_multiple_threads> - 41f36e: 74 0a je 41f37a - 41f370: f0 41 0f b1 34 24 lock cmpxchg %esi,(%r12) - 41f376: 75 09 jne 41f381 - 41f378: eb 1e jmp 41f398 - 41f37a: 41 0f b1 34 24 cmpxchg %esi,(%r12) - 41f37f: 74 17 je 41f398 - 41f381: 49 8d 3c 24 lea (%r12),%rdi - 41f385: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41f38c: e8 3f 32 02 00 callq 4425d0 <__lll_lock_wait_private> - 41f391: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41f398: 48 89 d1 mov %rdx,%rcx - 41f39b: 4c 89 f6 mov %r14,%rsi - 41f39e: 4c 89 fa mov %r15,%rdx - 41f3a1: 4c 89 e7 mov %r12,%rdi - 41f3a4: e8 b7 d6 ff ff callq 41ca60 <_int_realloc> - 41f3a9: 48 89 c5 mov %rax,%rbp - 41f3ac: 83 3d 09 de 2a 00 00 cmpl $0x0,0x2ade09(%rip) # 6cd1bc <__libc_multiple_threads> - 41f3b3: 74 09 je 41f3be - 41f3b5: f0 41 ff 0c 24 lock decl (%r12) - 41f3ba: 75 08 jne 41f3c4 - 41f3bc: eb 1d jmp 41f3db - 41f3be: 41 ff 0c 24 decl (%r12) - 41f3c2: 74 17 je 41f3db - 41f3c4: 49 8d 3c 24 lea (%r12),%rdi - 41f3c8: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41f3cf: e8 2c 32 02 00 callq 442600 <__lll_unlock_wake_private> - 41f3d4: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41f3db: 48 85 ed test %rbp,%rbp - 41f3de: 0f 84 bc 01 00 00 je 41f5a0 - 41f3e4: 48 8b 45 f8 mov -0x8(%rbp),%rax - 41f3e8: a8 02 test $0x2,%al - 41f3ea: 0f 85 fa fe ff ff jne 41f2ea - 41f3f0: a8 04 test $0x4,%al - 41f3f2: ba 00 a8 6c 00 mov $0x6ca800,%edx - 41f3f7: 74 0d je 41f406 - 41f3f9: 48 8d 45 f0 lea -0x10(%rbp),%rax - 41f3fd: 48 25 00 00 00 fc and $0xfffffffffc000000,%rax - 41f403: 48 8b 10 mov (%rax),%rdx - 41f406: 4c 39 e2 cmp %r12,%rdx - 41f409: 0f 84 db fe ff ff je 41f2ea - 41f40f: b9 18 2e 4a 00 mov $0x4a2e18,%ecx - 41f414: ba e9 0b 00 00 mov $0xbe9,%edx - 41f419: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 41f41e: bf c0 29 4a 00 mov $0x4a29c0,%edi - 41f423: e8 f8 79 ff ff callq 416e20 <__malloc_assert> - 41f428: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 41f42f: 00 - 41f430: 4c 89 f8 mov %r15,%rax - 41f433: 48 f7 d8 neg %rax - 41f436: 49 39 c6 cmp %rax,%r14 - 41f439: 77 10 ja 41f44b - 41f43b: 41 f6 c6 0f test $0xf,%r14b - 41f43f: 41 bc 00 a8 6c 00 mov $0x6ca800,%r12d - 41f445: 0f 84 52 fe ff ff je 41f29d - 41f44b: 8b 2d 1f b3 2a 00 mov 0x2ab31f(%rip),%ebp # 6ca770 - 41f451: 41 bc 00 a8 6c 00 mov $0x6ca800,%r12d - 41f457: e9 d8 fe ff ff jmpq 41f334 - 41f45c: 0f 1f 40 00 nopl 0x0(%rax) - 41f460: e8 8b f8 ff ff callq 41ecf0 - 41f465: 48 8b 05 14 b3 2a 00 mov 0x2ab314(%rip),%rax # 6ca780 <__realloc_hook> - 41f46c: 48 85 c0 test %rax,%rax - 41f46f: 0f 84 de fd ff ff je 41f253 - 41f475: 0f 1f 00 nopl (%rax) - 41f478: 48 8b 54 24 68 mov 0x68(%rsp),%rdx - 41f47d: 4c 89 ee mov %r13,%rsi - 41f480: 48 89 df mov %rbx,%rdi - 41f483: ff d0 callq *%rax - 41f485: 48 89 c5 mov %rax,%rbp - 41f488: e9 5d fe ff ff jmpq 41f2ea - 41f48d: 0f 1f 00 nopl (%rax) - 41f490: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 41f497: 31 ed xor %ebp,%ebp - 41f499: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) - 41f4a0: e9 45 fe ff ff jmpq 41f2ea - 41f4a5: 0f 1f 00 nopl (%rax) - 41f4a8: 49 8d 47 f8 lea -0x8(%r15),%rax - 41f4ac: 48 89 dd mov %rbx,%rbp - 41f4af: 48 39 c2 cmp %rax,%rdx - 41f4b2: 0f 86 32 fe ff ff jbe 41f2ea - 41f4b8: 4c 89 ef mov %r13,%rdi - 41f4bb: e8 50 e5 ff ff callq 41da10 <__libc_malloc> - 41f4c0: 48 85 c0 test %rax,%rax - 41f4c3: 48 89 c3 mov %rax,%rbx - 41f4c6: 0f 84 8f fe ff ff je 41f35b - 41f4cc: 49 8d 57 f0 lea -0x10(%r15),%rdx - 41f4d0: 48 89 ee mov %rbp,%rsi - 41f4d3: 48 89 c7 mov %rax,%rdi - 41f4d6: 48 89 dd mov %rbx,%rbp - 41f4d9: e8 42 cb 00 00 callq 42c020 - 41f4de: 4c 89 f7 mov %r14,%rdi - 41f4e1: e8 0a 88 ff ff callq 417cf0 - 41f4e6: e9 ff fd ff ff jmpq 41f2ea - 41f4eb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41f4f0: 48 89 df mov %rbx,%rdi - 41f4f3: 31 ed xor %ebp,%ebp - 41f4f5: e8 b6 e8 ff ff callq 41ddb0 <__cfree> - 41f4fa: e9 eb fd ff ff jmpq 41f2ea - 41f4ff: 90 nop - 41f500: 4c 8d 64 24 10 lea 0x10(%rsp),%r12 - 41f505: 48 8d 74 24 20 lea 0x20(%rsp),%rsi - 41f50a: 31 c9 xor %ecx,%ecx - 41f50c: 48 89 df mov %rbx,%rdi - 41f50f: ba 10 00 00 00 mov $0x10,%edx - 41f514: c6 44 24 20 00 movb $0x0,0x20(%rsp) - 41f519: e8 92 29 03 00 callq 451eb0 <_itoa_word> - 41f51e: 4c 39 e0 cmp %r12,%rax - 41f521: 48 89 c3 mov %rax,%rbx - 41f524: 76 25 jbe 41f54b - 41f526: 48 89 c2 mov %rax,%rdx - 41f529: 48 89 c7 mov %rax,%rdi - 41f52c: be 30 00 00 00 mov $0x30,%esi - 41f531: 4c 29 e2 sub %r12,%rdx - 41f534: 4c 8d 68 ff lea -0x1(%rax),%r13 - 41f538: 48 29 d7 sub %rdx,%rdi - 41f53b: e8 10 0e fe ff callq 400350 <__rela_iplt_end+0x88> - 41f540: 48 8d 44 24 0f lea 0xf(%rsp),%rax - 41f545: 4c 29 e8 sub %r13,%rax - 41f548: 48 01 c3 add %rax,%rbx - 41f54b: 48 8b 05 6e dd 2a 00 mov 0x2add6e(%rip),%rax # 6cd2c0 <__libc_argv> - 41f552: 89 ef mov %ebp,%edi - 41f554: ba 38 20 4a 00 mov $0x4a2038,%edx - 41f559: 49 89 d8 mov %rbx,%r8 - 41f55c: b9 c6 21 4a 00 mov $0x4a21c6,%ecx - 41f561: be a8 23 4a 00 mov $0x4a23a8,%esi - 41f566: 48 8b 00 mov (%rax),%rax - 41f569: 48 85 c0 test %rax,%rax - 41f56c: 48 0f 45 d0 cmovne %rax,%rdx - 41f570: 83 e7 02 and $0x2,%edi - 41f573: 31 c0 xor %eax,%eax - 41f575: e8 46 20 ff ff callq 4115c0 <__libc_message> - 41f57a: 31 ed xor %ebp,%ebp - 41f57c: e9 69 fd ff ff jmpq 41f2ea - 41f581: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 41f588: 4c 89 ef mov %r13,%rdi - 41f58b: e8 80 e4 ff ff callq 41da10 <__libc_malloc> - 41f590: 48 89 c5 mov %rax,%rbp - 41f593: e9 52 fd ff ff jmpq 41f2ea - 41f598: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 41f59f: 00 - 41f5a0: 90 nop - 41f5a1: 4c 89 ef mov %r13,%rdi - 41f5a4: 31 ed xor %ebp,%ebp - 41f5a6: e8 65 e4 ff ff callq 41da10 <__libc_malloc> - 41f5ab: 48 85 c0 test %rax,%rax - 41f5ae: 49 89 c5 mov %rax,%r13 - 41f5b1: 0f 84 33 fd ff ff je 41f2ea - 41f5b7: 49 8d 57 f8 lea -0x8(%r15),%rdx - 41f5bb: 48 89 de mov %rbx,%rsi - 41f5be: 48 89 c7 mov %rax,%rdi - 41f5c1: 4c 89 ed mov %r13,%rbp - 41f5c4: e8 57 ca 00 00 callq 42c020 - 41f5c9: 31 d2 xor %edx,%edx - 41f5cb: 4c 89 f6 mov %r14,%rsi - 41f5ce: 4c 89 e7 mov %r12,%rdi - 41f5d1: e8 ea a1 ff ff callq 4197c0 <_int_free> - 41f5d6: e9 0f fd ff ff jmpq 41f2ea - 41f5db: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41f5e0: 8b 2d 8a b1 2a 00 mov 0x2ab18a(%rip),%ebp # 6ca770 - 41f5e6: e9 4f fd ff ff jmpq 41f33a - 41f5eb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41f5f0: 89 ef mov %ebp,%edi - 41f5f2: ba c6 21 4a 00 mov $0x4a21c6,%edx - 41f5f7: be 3c ca 4b 00 mov $0x4bca3c,%esi - 41f5fc: 83 e7 02 and $0x2,%edi - 41f5ff: 31 c0 xor %eax,%eax - 41f601: 31 ed xor %ebp,%ebp - 41f603: e8 b8 1f ff ff callq 4115c0 <__libc_message> - 41f608: e9 dd fc ff ff jmpq 41f2ea - 41f60d: e8 ee e5 fe ff callq 40dc00 - 41f612: 0f 1f 40 00 nopl 0x0(%rax) - 41f616: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41f61d: 00 00 00 - -000000000041f620 : - 41f620: 41 54 push %r12 - 41f622: 55 push %rbp - 41f623: 49 89 f4 mov %rsi,%r12 - 41f626: 53 push %rbx - 41f627: 48 83 ec 10 sub $0x10,%rsp - 41f62b: 8b 05 33 b1 2a 00 mov 0x2ab133(%rip),%eax # 6ca764 <__libc_malloc_initialized> - 41f631: 48 c7 05 3c b1 2a 00 movq $0x0,0x2ab13c(%rip) # 6ca778 <__memalign_hook> - 41f638: 00 00 00 00 - 41f63c: 85 c0 test %eax,%eax - 41f63e: 0f 88 f4 01 00 00 js 41f838 - 41f644: 48 8b 05 2d b1 2a 00 mov 0x2ab12d(%rip),%rax # 6ca778 <__memalign_hook> - 41f64b: 48 8b 54 24 28 mov 0x28(%rsp),%rdx - 41f650: 48 85 c0 test %rax,%rax - 41f653: 0f 85 07 02 00 00 jne 41f860 - 41f659: 48 83 ff 10 cmp $0x10,%rdi - 41f65d: 0f 86 ed 01 00 00 jbe 41f850 - 41f663: 48 83 ff 1f cmp $0x1f,%rdi - 41f667: 0f 87 e3 00 00 00 ja 41f750 - 41f66d: 49 83 fc bf cmp $0xffffffffffffffbf,%r12 - 41f671: 0f 87 11 02 00 00 ja 41f888 - 41f677: bb 20 00 00 00 mov $0x20,%ebx - 41f67c: 48 c7 c0 d8 ff ff ff mov $0xffffffffffffffd8,%rax - 41f683: 64 48 8b 28 mov %fs:(%rax),%rbp - 41f687: 48 85 ed test %rbp,%rbp - 41f68a: 0f 84 18 01 00 00 je 41f7a8 - 41f690: 8b 45 04 mov 0x4(%rbp),%eax - 41f693: 83 e0 04 and $0x4,%eax - 41f696: 0f 85 0c 01 00 00 jne 41f7a8 - 41f69c: be 01 00 00 00 mov $0x1,%esi - 41f6a1: 83 3d 14 db 2a 00 00 cmpl $0x0,0x2adb14(%rip) # 6cd1bc <__libc_multiple_threads> - 41f6a8: 74 09 je 41f6b3 - 41f6aa: f0 0f b1 75 00 lock cmpxchg %esi,0x0(%rbp) - 41f6af: 75 08 jne 41f6b9 - 41f6b1: eb 1d jmp 41f6d0 - 41f6b3: 0f b1 75 00 cmpxchg %esi,0x0(%rbp) - 41f6b7: 74 17 je 41f6d0 - 41f6b9: 48 8d 7d 00 lea 0x0(%rbp),%rdi - 41f6bd: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41f6c4: e8 07 2f 02 00 callq 4425d0 <__lll_lock_wait_private> - 41f6c9: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41f6d0: 4c 89 e2 mov %r12,%rdx - 41f6d3: 48 89 de mov %rbx,%rsi - 41f6d6: 48 89 ef mov %rbp,%rdi - 41f6d9: e8 32 ce ff ff callq 41c510 <_int_memalign> - 41f6de: 48 85 c0 test %rax,%rax - 41f6e1: 48 89 c2 mov %rax,%rdx - 41f6e4: 0f 84 fe 00 00 00 je 41f7e8 - 41f6ea: 83 3d cb da 2a 00 00 cmpl $0x0,0x2adacb(%rip) # 6cd1bc <__libc_multiple_threads> - 41f6f1: 74 08 je 41f6fb - 41f6f3: f0 ff 4d 00 lock decl 0x0(%rbp) - 41f6f7: 75 07 jne 41f700 - 41f6f9: eb 1c jmp 41f717 - 41f6fb: ff 4d 00 decl 0x0(%rbp) - 41f6fe: 74 17 je 41f717 - 41f700: 48 8d 7d 00 lea 0x0(%rbp),%rdi - 41f704: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41f70b: e8 f0 2e 02 00 callq 442600 <__lll_unlock_wake_private> - 41f710: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41f717: 48 85 d2 test %rdx,%rdx - 41f71a: 0f 84 80 01 00 00 je 41f8a0 - 41f720: 48 8b 42 f8 mov -0x8(%rdx),%rax - 41f724: a8 02 test $0x2,%al - 41f726: 75 16 jne 41f73e - 41f728: a8 04 test $0x4,%al - 41f72a: b9 00 a8 6c 00 mov $0x6ca800,%ecx - 41f72f: 0f 85 eb 00 00 00 jne 41f820 - 41f735: 48 39 e9 cmp %rbp,%rcx - 41f738: 0f 85 69 01 00 00 jne 41f8a7 - 41f73e: 48 89 d0 mov %rdx,%rax - 41f741: 48 83 c4 10 add $0x10,%rsp - 41f745: 5b pop %rbx - 41f746: 5d pop %rbp - 41f747: 41 5c pop %r12 - 41f749: c3 retq - 41f74a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 41f750: 48 b8 00 00 00 00 00 movabs $0x8000000000000000,%rax - 41f757: 00 00 80 - 41f75a: 48 39 c7 cmp %rax,%rdi - 41f75d: 0f 87 0d 01 00 00 ja 41f870 - 41f763: 48 c7 c0 df ff ff ff mov $0xffffffffffffffdf,%rax - 41f76a: 48 29 f8 sub %rdi,%rax - 41f76d: 49 39 c4 cmp %rax,%r12 - 41f770: 0f 87 12 01 00 00 ja 41f888 - 41f776: 48 8d 47 ff lea -0x1(%rdi),%rax - 41f77a: 48 85 f8 test %rdi,%rax - 41f77d: 0f 84 3d 01 00 00 je 41f8c0 - 41f783: 48 83 ff 20 cmp $0x20,%rdi - 41f787: bb 20 00 00 00 mov $0x20,%ebx - 41f78c: 0f 84 ea fe ff ff je 41f67c - 41f792: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 41f798: 48 01 db add %rbx,%rbx - 41f79b: 48 39 df cmp %rbx,%rdi - 41f79e: 77 f8 ja 41f798 - 41f7a0: e9 d7 fe ff ff jmpq 41f67c - 41f7a5: 0f 1f 00 nopl (%rax) - 41f7a8: e8 b3 79 ff ff callq 417160 - 41f7ad: 48 85 c0 test %rax,%rax - 41f7b0: 48 89 c5 mov %rax,%rbp - 41f7b3: 0f 85 17 ff ff ff jne 41f6d0 - 41f7b9: 4a 8d 7c 23 20 lea 0x20(%rbx,%r12,1),%rdi - 41f7be: 31 f6 xor %esi,%esi - 41f7c0: e8 8b 7c ff ff callq 417450 - 41f7c5: 4c 89 e2 mov %r12,%rdx - 41f7c8: 48 89 de mov %rbx,%rsi - 41f7cb: 48 89 c7 mov %rax,%rdi - 41f7ce: 48 89 c5 mov %rax,%rbp - 41f7d1: e8 3a cd ff ff callq 41c510 <_int_memalign> - 41f7d6: 48 85 c0 test %rax,%rax - 41f7d9: 48 89 c2 mov %rax,%rdx - 41f7dc: 75 2a jne 41f808 - 41f7de: 48 85 ed test %rbp,%rbp - 41f7e1: 74 25 je 41f808 - 41f7e3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41f7e8: 90 nop - 41f7e9: 48 89 ef mov %rbp,%rdi - 41f7ec: 4c 89 e6 mov %r12,%rsi - 41f7ef: e8 fc 81 ff ff callq 4179f0 - 41f7f4: 4c 89 e2 mov %r12,%rdx - 41f7f7: 48 89 de mov %rbx,%rsi - 41f7fa: 48 89 c7 mov %rax,%rdi - 41f7fd: 48 89 c5 mov %rax,%rbp - 41f800: e8 0b cd ff ff callq 41c510 <_int_memalign> - 41f805: 48 89 c2 mov %rax,%rdx - 41f808: 48 85 ed test %rbp,%rbp - 41f80b: 0f 85 d9 fe ff ff jne 41f6ea - 41f811: e9 01 ff ff ff jmpq 41f717 - 41f816: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41f81d: 00 00 00 - 41f820: 48 8d 42 f0 lea -0x10(%rdx),%rax - 41f824: 48 25 00 00 00 fc and $0xfffffffffc000000,%rax - 41f82a: 48 8b 08 mov (%rax),%rcx - 41f82d: e9 03 ff ff ff jmpq 41f735 - 41f832: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 41f838: 48 89 7c 24 08 mov %rdi,0x8(%rsp) - 41f83d: e8 ae f4 ff ff callq 41ecf0 - 41f842: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi - 41f847: e9 f8 fd ff ff jmpq 41f644 - 41f84c: 0f 1f 40 00 nopl 0x0(%rax) - 41f850: 48 83 c4 10 add $0x10,%rsp - 41f854: 4c 89 e7 mov %r12,%rdi - 41f857: 5b pop %rbx - 41f858: 5d pop %rbp - 41f859: 41 5c pop %r12 - 41f85b: e9 b0 e1 ff ff jmpq 41da10 <__libc_malloc> - 41f860: 48 83 c4 10 add $0x10,%rsp - 41f864: 4c 89 e6 mov %r12,%rsi - 41f867: 5b pop %rbx - 41f868: 5d pop %rbp - 41f869: 41 5c pop %r12 - 41f86b: ff e0 jmpq *%rax - 41f86d: 0f 1f 00 nopl (%rax) - 41f870: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 41f877: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) - 41f87e: 31 c0 xor %eax,%eax - 41f880: e9 bc fe ff ff jmpq 41f741 - 41f885: 0f 1f 00 nopl (%rax) - 41f888: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 41f88f: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) - 41f896: 31 c0 xor %eax,%eax - 41f898: e9 a4 fe ff ff jmpq 41f741 - 41f89d: 0f 1f 00 nopl (%rax) - 41f8a0: 31 c0 xor %eax,%eax - 41f8a2: e9 9a fe ff ff jmpq 41f741 - 41f8a7: b9 08 2e 4a 00 mov $0x4a2e08,%ecx - 41f8ac: ba 3c 0c 00 00 mov $0xc3c,%edx - 41f8b1: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 41f8b6: bf 20 2a 4a 00 mov $0x4a2a20,%edi - 41f8bb: e8 60 75 ff ff callq 416e20 <__malloc_assert> - 41f8c0: 48 89 fb mov %rdi,%rbx - 41f8c3: e9 b4 fd ff ff jmpq 41f67c - 41f8c8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 41f8cf: 00 - -000000000041f8d0 <__malloc_set_state>: - 41f8d0: 44 8b 05 8d ae 2a 00 mov 0x2aae8d(%rip),%r8d # 6ca764 <__libc_malloc_initialized> - 41f8d7: 53 push %rbx - 41f8d8: 48 89 fb mov %rdi,%rbx - 41f8db: c7 05 23 cd 2a 00 01 movl $0x1,0x2acd23(%rip) # 6cc608 - 41f8e2: 00 00 00 - 41f8e5: 45 85 c0 test %r8d,%r8d - 41f8e8: 0f 88 df 04 00 00 js 41fdcd <__malloc_set_state+0x4fd> - 41f8ee: 48 81 3b 41 45 4c 44 cmpq $0x444c4541,(%rbx) - 41f8f5: 0f 85 e4 04 00 00 jne 41fddf <__malloc_set_state+0x50f> - 41f8fb: 48 f7 43 08 00 ff ff testq $0xffffffffffffff00,0x8(%rbx) - 41f902: ff - 41f903: 0f 8f dd 04 00 00 jg 41fde6 <__malloc_set_state+0x516> - 41f909: be 01 00 00 00 mov $0x1,%esi - 41f90e: 31 c0 xor %eax,%eax - 41f910: 83 3d a5 d8 2a 00 00 cmpl $0x0,0x2ad8a5(%rip) # 6cd1bc <__libc_multiple_threads> - 41f917: 74 0c je 41f925 <__malloc_set_state+0x55> - 41f919: f0 0f b1 35 df ae 2a lock cmpxchg %esi,0x2aaedf(%rip) # 6ca800 - 41f920: 00 - 41f921: 75 0b jne 41f92e <__malloc_set_state+0x5e> - 41f923: eb 23 jmp 41f948 <__malloc_set_state+0x78> - 41f925: 0f b1 35 d4 ae 2a 00 cmpxchg %esi,0x2aaed4(%rip) # 6ca800 - 41f92c: 74 1a je 41f948 <__malloc_set_state+0x78> - 41f92e: 48 8d 3d cb ae 2a 00 lea 0x2aaecb(%rip),%rdi # 6ca800 - 41f935: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41f93c: e8 8f 2c 02 00 callq 4425d0 <__lll_lock_wait_private> - 41f941: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41f948: 64 83 3c 25 18 00 00 cmpl $0x0,%fs:0x18 - 41f94f: 00 00 - 41f951: 74 01 je 41f954 <__malloc_set_state+0x84> - 41f953: f0 83 0d a9 ae 2a 00 lock orl $0x1,0x2aaea9(%rip) # 6ca804 - 41f95a: 01 - 41f95b: 48 83 7b 08 03 cmpq $0x3,0x8(%rbx) - 41f960: 0f 8f 0d 01 00 00 jg 41fa73 <__malloc_set_state+0x1a3> - 41f966: 48 c7 05 c7 cc 2a 00 movq $0x40,0x2accc7(%rip) # 6cc638 - 41f96d: 40 00 00 00 - 41f971: ba 08 a8 6c 00 mov $0x6ca808,%edx - 41f976: 31 c0 xor %eax,%eax - 41f978: b9 0a 00 00 00 mov $0xa,%ecx - 41f97d: 48 89 d7 mov %rdx,%rdi - 41f980: c7 05 ce b6 2a 00 00 movl $0x0,0x2ab6ce(%rip) # 6cb058 - 41f987: 00 00 00 - 41f98a: c7 05 c8 b6 2a 00 00 movl $0x0,0x2ab6c8(%rip) # 6cb05c - 41f991: 00 00 00 - 41f994: f3 48 ab rep stos %rax,%es:(%rdi) - 41f997: c7 05 bf b6 2a 00 00 movl $0x0,0x2ab6bf(%rip) # 6cb060 - 41f99e: 00 00 00 - 41f9a1: c7 05 b9 b6 2a 00 00 movl $0x0,0x2ab6b9(%rip) # 6cb064 - 41f9a8: 00 00 00 - 41f9ab: 48 8d 53 38 lea 0x38(%rbx),%rdx - 41f9af: b9 01 00 00 00 mov $0x1,%ecx - 41f9b4: 41 b8 01 00 00 00 mov $0x1,%r8d - 41f9ba: 41 b9 7e 00 00 00 mov $0x7e,%r9d - 41f9c0: 48 8b 43 20 mov 0x20(%rbx),%rax - 41f9c4: 48 c7 05 91 ae 2a 00 movq $0x0,0x2aae91(%rip) # 6ca860 - 41f9cb: 00 00 00 00 - 41f9cf: 48 89 05 82 ae 2a 00 mov %rax,0x2aae82(%rip) # 6ca858 - 41f9d6: b8 58 a8 6c 00 mov $0x6ca858,%eax - 41f9db: eb 50 jmp 41fa2d <__malloc_set_state+0x15d> - 41f9dd: 0f 1f 00 nopl (%rax) - 41f9e0: 48 83 f9 3f cmp $0x3f,%rcx - 41f9e4: 0f 87 b6 00 00 00 ja 41faa0 <__malloc_set_state+0x1d0> - 41f9ea: 48 8b 3a mov (%rdx),%rdi - 41f9ed: 48 89 78 18 mov %rdi,0x18(%rax) - 41f9f1: 48 89 70 10 mov %rsi,0x10(%rax) - 41f9f5: 44 89 c7 mov %r8d,%edi - 41f9f8: 48 89 46 18 mov %rax,0x18(%rsi) - 41f9fc: 48 8b 70 18 mov 0x18(%rax),%rsi - 41fa00: d3 e7 shl %cl,%edi - 41fa02: 48 89 46 10 mov %rax,0x10(%rsi) - 41fa06: 48 89 ce mov %rcx,%rsi - 41fa09: 48 c1 ee 05 shr $0x5,%rsi - 41fa0d: 09 3c b5 58 b0 6c 00 or %edi,0x6cb058(,%rsi,4) - 41fa14: 48 83 c1 01 add $0x1,%rcx - 41fa18: 48 83 c0 10 add $0x10,%rax - 41fa1c: 48 83 c2 10 add $0x10,%rdx - 41fa20: 48 81 f9 80 00 00 00 cmp $0x80,%rcx - 41fa27: 0f 84 6b 01 00 00 je 41fb98 <__malloc_set_state+0x2c8> - 41fa2d: 48 8b 72 f8 mov -0x8(%rdx),%rsi - 41fa31: 48 85 f6 test %rsi,%rsi - 41fa34: 0f 84 a6 00 00 00 je 41fae0 <__malloc_set_state+0x210> - 41fa3a: 48 83 7b 08 02 cmpq $0x2,0x8(%rbx) - 41fa3f: 7f 9f jg 41f9e0 <__malloc_set_state+0x110> - 41fa41: 48 8b 3a mov (%rdx),%rdi - 41fa44: 48 89 40 18 mov %rax,0x18(%rax) - 41fa48: 48 89 40 10 mov %rax,0x10(%rax) - 41fa4c: 48 c7 46 18 58 a8 6c movq $0x6ca858,0x18(%rsi) - 41fa53: 00 - 41fa54: 4c 8b 15 0d ae 2a 00 mov 0x2aae0d(%rip),%r10 # 6ca868 - 41fa5b: 4c 89 57 10 mov %r10,0x10(%rdi) - 41fa5f: 4c 8b 15 02 ae 2a 00 mov 0x2aae02(%rip),%r10 # 6ca868 - 41fa66: 49 89 7a 18 mov %rdi,0x18(%r10) - 41fa6a: 48 89 35 f7 ad 2a 00 mov %rsi,0x2aadf7(%rip) # 6ca868 - 41fa71: eb a1 jmp 41fa14 <__malloc_set_state+0x144> - 41fa73: 48 8b 93 88 08 00 00 mov 0x888(%rbx),%rdx - 41fa7a: b8 10 00 00 00 mov $0x10,%eax - 41fa7f: 48 85 d2 test %rdx,%rdx - 41fa82: 74 08 je 41fa8c <__malloc_set_state+0x1bc> - 41fa84: 48 8d 42 08 lea 0x8(%rdx),%rax - 41fa88: 48 83 e0 f0 and $0xfffffffffffffff0,%rax - 41fa8c: 48 89 05 a5 cb 2a 00 mov %rax,0x2acba5(%rip) # 6cc638 - 41fa93: e9 d9 fe ff ff jmpq 41f971 <__malloc_set_state+0xa1> - 41fa98: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 41fa9f: 00 - 41faa0: 4c 8b 56 08 mov 0x8(%rsi),%r10 - 41faa4: 4c 89 d7 mov %r10,%rdi - 41faa7: 48 c1 ef 06 shr $0x6,%rdi - 41faab: 48 83 ff 30 cmp $0x30,%rdi - 41faaf: 77 4f ja 41fb00 <__malloc_set_state+0x230> - 41fab1: 48 83 c7 30 add $0x30,%rdi - 41fab5: 48 39 cf cmp %rcx,%rdi - 41fab8: 48 8b 3a mov (%rdx),%rdi - 41fabb: 75 87 jne 41fa44 <__malloc_set_state+0x174> - 41fabd: 4c 8b 5f 08 mov 0x8(%rdi),%r11 - 41fac1: 4d 89 da mov %r11,%r10 - 41fac4: 49 c1 ea 06 shr $0x6,%r10 - 41fac8: 49 83 fa 30 cmp $0x30,%r10 - 41facc: 77 62 ja 41fb30 <__malloc_set_state+0x260> - 41face: 49 83 c2 30 add $0x30,%r10 - 41fad2: 49 39 ca cmp %rcx,%r10 - 41fad5: 0f 85 69 ff ff ff jne 41fa44 <__malloc_set_state+0x174> - 41fadb: e9 0d ff ff ff jmpq 41f9ed <__malloc_set_state+0x11d> - 41fae0: 48 83 3a 00 cmpq $0x0,(%rdx) - 41fae4: 0f 85 03 03 00 00 jne 41fded <__malloc_set_state+0x51d> - 41faea: 48 89 40 18 mov %rax,0x18(%rax) - 41faee: 48 89 40 10 mov %rax,0x10(%rax) - 41faf2: e9 1d ff ff ff jmpq 41fa14 <__malloc_set_state+0x144> - 41faf7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 41fafe: 00 00 - 41fb00: 4c 89 d7 mov %r10,%rdi - 41fb03: 48 c1 ef 09 shr $0x9,%rdi - 41fb07: 48 83 ff 14 cmp $0x14,%rdi - 41fb0b: 77 0b ja 41fb18 <__malloc_set_state+0x248> - 41fb0d: 48 83 c7 5b add $0x5b,%rdi - 41fb11: eb a2 jmp 41fab5 <__malloc_set_state+0x1e5> - 41fb13: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41fb18: 4c 89 d7 mov %r10,%rdi - 41fb1b: 48 c1 ef 0c shr $0xc,%rdi - 41fb1f: 48 83 ff 0a cmp $0xa,%rdi - 41fb23: 77 23 ja 41fb48 <__malloc_set_state+0x278> - 41fb25: 48 83 c7 6e add $0x6e,%rdi - 41fb29: eb 8a jmp 41fab5 <__malloc_set_state+0x1e5> - 41fb2b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41fb30: 4d 89 da mov %r11,%r10 - 41fb33: 49 c1 ea 09 shr $0x9,%r10 - 41fb37: 49 83 fa 14 cmp $0x14,%r10 - 41fb3b: 77 23 ja 41fb60 <__malloc_set_state+0x290> - 41fb3d: 49 83 c2 5b add $0x5b,%r10 - 41fb41: eb 8f jmp 41fad2 <__malloc_set_state+0x202> - 41fb43: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41fb48: 4c 89 d7 mov %r10,%rdi - 41fb4b: 48 c1 ef 0f shr $0xf,%rdi - 41fb4f: 48 83 ff 04 cmp $0x4,%rdi - 41fb53: 77 2b ja 41fb80 <__malloc_set_state+0x2b0> - 41fb55: 48 83 c7 77 add $0x77,%rdi - 41fb59: e9 57 ff ff ff jmpq 41fab5 <__malloc_set_state+0x1e5> - 41fb5e: 66 90 xchg %ax,%ax - 41fb60: 4d 89 da mov %r11,%r10 - 41fb63: 49 c1 ea 0c shr $0xc,%r10 - 41fb67: 49 83 fa 0a cmp $0xa,%r10 - 41fb6b: 0f 87 9f 01 00 00 ja 41fd10 <__malloc_set_state+0x440> - 41fb71: 49 83 c2 6e add $0x6e,%r10 - 41fb75: e9 58 ff ff ff jmpq 41fad2 <__malloc_set_state+0x202> - 41fb7a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 41fb80: 49 c1 ea 12 shr $0x12,%r10 - 41fb84: 49 8d 7a 7c lea 0x7c(%r10),%rdi - 41fb88: 49 83 fa 02 cmp $0x2,%r10 - 41fb8c: 49 0f 47 f9 cmova %r9,%rdi - 41fb90: e9 20 ff ff ff jmpq 41fab5 <__malloc_set_state+0x1e5> - 41fb95: 0f 1f 00 nopl (%rax) - 41fb98: 48 8b 4b 08 mov 0x8(%rbx),%rcx - 41fb9c: 48 83 f9 02 cmp $0x2,%rcx - 41fba0: 7f 43 jg 41fbe5 <__malloc_set_state+0x315> - 41fba2: 48 8b 05 bf ac 2a 00 mov 0x2aacbf(%rip),%rax # 6ca868 - 41fba9: 48 3d 58 a8 6c 00 cmp $0x6ca858,%rax - 41fbaf: 74 34 je 41fbe5 <__malloc_set_state+0x315> - 41fbb1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 41fbb8: 48 8b 50 08 mov 0x8(%rax),%rdx - 41fbbc: 48 83 e2 f8 and $0xfffffffffffffff8,%rdx - 41fbc0: 48 81 fa ff 03 00 00 cmp $0x3ff,%rdx - 41fbc7: 76 10 jbe 41fbd9 <__malloc_set_state+0x309> - 41fbc9: 48 c7 40 20 00 00 00 movq $0x0,0x20(%rax) - 41fbd0: 00 - 41fbd1: 48 c7 40 28 00 00 00 movq $0x0,0x28(%rax) - 41fbd8: 00 - 41fbd9: 48 8b 40 10 mov 0x10(%rax),%rax - 41fbdd: 48 3d 58 a8 6c 00 cmp $0x6ca858,%rax - 41fbe3: 75 d3 jne 41fbb8 <__malloc_set_state+0x2e8> - 41fbe5: 48 8b 83 20 08 00 00 mov 0x820(%rbx),%rax - 41fbec: 48 85 c9 test %rcx,%rcx - 41fbef: 48 89 05 fa ab 2a 00 mov %rax,0x2aabfa(%rip) # 6ca7f0 - 41fbf6: 48 63 83 28 08 00 00 movslq 0x828(%rbx),%rax - 41fbfd: 48 89 05 7c b4 2a 00 mov %rax,0x2ab47c(%rip) # 6cb080 - 41fc04: 48 8b 83 30 08 00 00 mov 0x830(%rbx),%rax - 41fc0b: 48 89 05 8e ab 2a 00 mov %rax,0x2aab8e(%rip) # 6ca7a0 - 41fc12: 48 8b 83 38 08 00 00 mov 0x838(%rbx),%rax - 41fc19: 48 89 05 88 ab 2a 00 mov %rax,0x2aab88(%rip) # 6ca7a8 - 41fc20: 8b 83 40 08 00 00 mov 0x840(%rbx),%eax - 41fc26: 89 05 a0 ab 2a 00 mov %eax,0x2aaba0(%rip) # 6ca7cc - 41fc2c: 48 8b 83 48 08 00 00 mov 0x848(%rbx),%rax - 41fc33: 48 89 05 76 ab 2a 00 mov %rax,0x2aab76(%rip) # 6ca7b0 - 41fc3a: 8b 83 50 08 00 00 mov 0x850(%rbx),%eax - 41fc40: 89 05 2a ab 2a 00 mov %eax,0x2aab2a(%rip) # 6ca770 - 41fc46: 48 8b 83 58 08 00 00 mov 0x858(%rbx),%rax - 41fc4d: 48 89 05 34 b4 2a 00 mov %rax,0x2ab434(%rip) # 6cb088 - 41fc54: 8b 83 68 08 00 00 mov 0x868(%rbx),%eax - 41fc5a: 89 05 68 ab 2a 00 mov %eax,0x2aab68(%rip) # 6ca7c8 - 41fc60: 8b 83 6c 08 00 00 mov 0x86c(%rbx),%eax - 41fc66: 89 05 64 ab 2a 00 mov %eax,0x2aab64(%rip) # 6ca7d0 - 41fc6c: 48 8b 83 70 08 00 00 mov 0x870(%rbx),%rax - 41fc73: 48 89 05 5e ab 2a 00 mov %rax,0x2aab5e(%rip) # 6ca7d8 - 41fc7a: 48 8b 83 78 08 00 00 mov 0x878(%rbx),%rax - 41fc81: 48 89 05 58 ab 2a 00 mov %rax,0x2aab58(%rip) # 6ca7e0 - 41fc88: 7e 4c jle 41fcd6 <__malloc_set_state+0x406> - 41fc8a: 8b bb 80 08 00 00 mov 0x880(%rbx),%edi - 41fc90: 85 ff test %edi,%edi - 41fc92: 0f 85 a3 00 00 00 jne 41fd3b <__malloc_set_state+0x46b> - 41fc98: 8b 05 6e c9 2a 00 mov 0x2ac96e(%rip),%eax # 6cc60c - 41fc9e: 85 c0 test %eax,%eax - 41fca0: 0f 85 ec 00 00 00 jne 41fd92 <__malloc_set_state+0x4c2> - 41fca6: 48 83 f9 03 cmp $0x3,%rcx - 41fcaa: 7e 2a jle 41fcd6 <__malloc_set_state+0x406> - 41fcac: 48 8b 83 90 08 00 00 mov 0x890(%rbx),%rax - 41fcb3: 48 89 05 fe aa 2a 00 mov %rax,0x2aaafe(%rip) # 6ca7b8 - 41fcba: 48 8b 83 98 08 00 00 mov 0x898(%rbx),%rax - 41fcc1: 48 89 05 f8 aa 2a 00 mov %rax,0x2aaaf8(%rip) # 6ca7c0 - 41fcc8: 48 8b 83 a0 08 00 00 mov 0x8a0(%rbx),%rax - 41fccf: 48 89 05 92 aa 2a 00 mov %rax,0x2aaa92(%rip) # 6ca768 - 41fcd6: 83 3d df d4 2a 00 00 cmpl $0x0,0x2ad4df(%rip) # 6cd1bc <__libc_multiple_threads> - 41fcdd: 74 0b je 41fcea <__malloc_set_state+0x41a> - 41fcdf: f0 ff 0d 1a ab 2a 00 lock decl 0x2aab1a(%rip) # 6ca800 - 41fce6: 75 0a jne 41fcf2 <__malloc_set_state+0x422> - 41fce8: eb 22 jmp 41fd0c <__malloc_set_state+0x43c> - 41fcea: ff 0d 10 ab 2a 00 decl 0x2aab10(%rip) # 6ca800 - 41fcf0: 74 1a je 41fd0c <__malloc_set_state+0x43c> - 41fcf2: 48 8d 3d 07 ab 2a 00 lea 0x2aab07(%rip),%rdi # 6ca800 - 41fcf9: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41fd00: e8 fb 28 02 00 callq 442600 <__lll_unlock_wake_private> - 41fd05: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41fd0c: 31 c0 xor %eax,%eax - 41fd0e: 5b pop %rbx - 41fd0f: c3 retq - 41fd10: 4d 89 da mov %r11,%r10 - 41fd13: 49 c1 ea 0f shr $0xf,%r10 - 41fd17: 49 83 fa 04 cmp $0x4,%r10 - 41fd1b: 77 09 ja 41fd26 <__malloc_set_state+0x456> - 41fd1d: 49 83 c2 77 add $0x77,%r10 - 41fd21: e9 ac fd ff ff jmpq 41fad2 <__malloc_set_state+0x202> - 41fd26: 49 c1 eb 12 shr $0x12,%r11 - 41fd2a: 4d 8d 53 7c lea 0x7c(%r11),%r10 - 41fd2e: 49 83 fb 02 cmp $0x2,%r11 - 41fd32: 4d 0f 47 d1 cmova %r9,%r10 - 41fd36: e9 97 fd ff ff jmpq 41fad2 <__malloc_set_state+0x202> - 41fd3b: 8b 35 cb c8 2a 00 mov 0x2ac8cb(%rip),%esi # 6cc60c - 41fd41: 85 f6 test %esi,%esi - 41fd43: 0f 85 5d ff ff ff jne 41fca6 <__malloc_set_state+0x3d6> - 41fd49: 8b 15 b9 c8 2a 00 mov 0x2ac8b9(%rip),%edx # 6cc608 - 41fd4f: 85 d2 test %edx,%edx - 41fd51: 0f 85 4f ff ff ff jne 41fca6 <__malloc_set_state+0x3d6> - 41fd57: c7 05 ab c8 2a 00 01 movl $0x1,0x2ac8ab(%rip) # 6cc60c - 41fd5e: 00 00 00 - 41fd61: 48 c7 05 1c aa 2a 00 movq $0x41c720,0x2aaa1c(%rip) # 6ca788 <__malloc_hook> - 41fd68: 20 c7 41 00 - 41fd6c: 48 c7 05 71 c8 2a 00 movq $0x4189e0,0x2ac871(%rip) # 6cc5e8 <__free_hook> - 41fd73: e0 89 41 00 - 41fd77: 48 c7 05 fe a9 2a 00 movq $0x41d180,0x2aa9fe(%rip) # 6ca780 <__realloc_hook> - 41fd7e: 80 d1 41 00 - 41fd82: 48 c7 05 eb a9 2a 00 movq $0x41c870,0x2aa9eb(%rip) # 6ca778 <__memalign_hook> - 41fd89: 70 c8 41 00 - 41fd8d: e9 14 ff ff ff jmpq 41fca6 <__malloc_set_state+0x3d6> - 41fd92: 48 c7 05 eb a9 2a 00 movq $0x0,0x2aa9eb(%rip) # 6ca788 <__malloc_hook> - 41fd99: 00 00 00 00 - 41fd9d: 48 c7 05 40 c8 2a 00 movq $0x0,0x2ac840(%rip) # 6cc5e8 <__free_hook> - 41fda4: 00 00 00 00 - 41fda8: 48 c7 05 cd a9 2a 00 movq $0x0,0x2aa9cd(%rip) # 6ca780 <__realloc_hook> - 41fdaf: 00 00 00 00 - 41fdb3: 48 c7 05 ba a9 2a 00 movq $0x0,0x2aa9ba(%rip) # 6ca778 <__memalign_hook> - 41fdba: 00 00 00 00 - 41fdbe: c7 05 44 c8 2a 00 00 movl $0x0,0x2ac844(%rip) # 6cc60c - 41fdc5: 00 00 00 - 41fdc8: e9 d9 fe ff ff jmpq 41fca6 <__malloc_set_state+0x3d6> - 41fdcd: e8 1e ef ff ff callq 41ecf0 - 41fdd2: 48 81 3b 41 45 4c 44 cmpq $0x444c4541,(%rbx) - 41fdd9: 0f 84 1c fb ff ff je 41f8fb <__malloc_set_state+0x2b> - 41fddf: b8 ff ff ff ff mov $0xffffffff,%eax - 41fde4: 5b pop %rbx - 41fde5: c3 retq - 41fde6: b8 fe ff ff ff mov $0xfffffffe,%eax - 41fdeb: 5b pop %rbx - 41fdec: c3 retq - 41fded: b9 a0 2f 4a 00 mov $0x4a2fa0,%ecx - 41fdf2: ba 45 02 00 00 mov $0x245,%edx - 41fdf7: be 3f 22 4a 00 mov $0x4a223f,%esi - 41fdfc: bf 47 22 4a 00 mov $0x4a2247,%edi - 41fe01: e8 1a 70 ff ff callq 416e20 <__malloc_assert> - 41fe06: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41fe0d: 00 00 00 - -000000000041fe10 <__libc_valloc>: - 41fe10: 8b 05 4e a9 2a 00 mov 0x2aa94e(%rip),%eax # 6ca764 <__libc_malloc_initialized> - 41fe16: 41 54 push %r12 - 41fe18: 49 89 fc mov %rdi,%r12 - 41fe1b: 55 push %rbp - 41fe1c: 53 push %rbx - 41fe1d: 85 c0 test %eax,%eax - 41fe1f: 0f 88 2b 02 00 00 js 420050 <__libc_valloc+0x240> - 41fe25: 48 8b 05 4c a9 2a 00 mov 0x2aa94c(%rip),%rax # 6ca778 <__memalign_hook> - 41fe2c: 48 8b 54 24 18 mov 0x18(%rsp),%rdx - 41fe31: 48 85 c0 test %rax,%rax - 41fe34: 48 8b 3d 45 b3 2a 00 mov 0x2ab345(%rip),%rdi # 6cb180 <_dl_pagesize> - 41fe3b: 0f 85 e7 01 00 00 jne 420028 <__libc_valloc+0x218> - 41fe41: 48 83 ff 10 cmp $0x10,%rdi - 41fe45: 0f 86 cd 01 00 00 jbe 420018 <__libc_valloc+0x208> - 41fe4b: 48 83 ff 1f cmp $0x1f,%rdi - 41fe4f: 0f 87 db 00 00 00 ja 41ff30 <__libc_valloc+0x120> - 41fe55: 49 83 fc bf cmp $0xffffffffffffffbf,%r12 - 41fe59: 0f 87 01 02 00 00 ja 420060 <__libc_valloc+0x250> - 41fe5f: bb 20 00 00 00 mov $0x20,%ebx - 41fe64: 48 c7 c0 d8 ff ff ff mov $0xffffffffffffffd8,%rax - 41fe6b: 64 48 8b 28 mov %fs:(%rax),%rbp - 41fe6f: 48 85 ed test %rbp,%rbp - 41fe72: 0f 84 10 01 00 00 je 41ff88 <__libc_valloc+0x178> - 41fe78: 8b 45 04 mov 0x4(%rbp),%eax - 41fe7b: 83 e0 04 and $0x4,%eax - 41fe7e: 0f 85 04 01 00 00 jne 41ff88 <__libc_valloc+0x178> - 41fe84: be 01 00 00 00 mov $0x1,%esi - 41fe89: 83 3d 2c d3 2a 00 00 cmpl $0x0,0x2ad32c(%rip) # 6cd1bc <__libc_multiple_threads> - 41fe90: 74 09 je 41fe9b <__libc_valloc+0x8b> - 41fe92: f0 0f b1 75 00 lock cmpxchg %esi,0x0(%rbp) - 41fe97: 75 08 jne 41fea1 <__libc_valloc+0x91> - 41fe99: eb 1d jmp 41feb8 <__libc_valloc+0xa8> - 41fe9b: 0f b1 75 00 cmpxchg %esi,0x0(%rbp) - 41fe9f: 74 17 je 41feb8 <__libc_valloc+0xa8> - 41fea1: 48 8d 7d 00 lea 0x0(%rbp),%rdi - 41fea5: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41feac: e8 1f 27 02 00 callq 4425d0 <__lll_lock_wait_private> - 41feb1: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41feb8: 4c 89 e2 mov %r12,%rdx - 41febb: 48 89 de mov %rbx,%rsi - 41febe: 48 89 ef mov %rbp,%rdi - 41fec1: e8 4a c6 ff ff callq 41c510 <_int_memalign> - 41fec6: 48 85 c0 test %rax,%rax - 41fec9: 48 89 c2 mov %rax,%rdx - 41fecc: 0f 84 f6 00 00 00 je 41ffc8 <__libc_valloc+0x1b8> - 41fed2: 83 3d e3 d2 2a 00 00 cmpl $0x0,0x2ad2e3(%rip) # 6cd1bc <__libc_multiple_threads> - 41fed9: 74 08 je 41fee3 <__libc_valloc+0xd3> - 41fedb: f0 ff 4d 00 lock decl 0x0(%rbp) - 41fedf: 75 07 jne 41fee8 <__libc_valloc+0xd8> - 41fee1: eb 1c jmp 41feff <__libc_valloc+0xef> - 41fee3: ff 4d 00 decl 0x0(%rbp) - 41fee6: 74 17 je 41feff <__libc_valloc+0xef> - 41fee8: 48 8d 7d 00 lea 0x0(%rbp),%rdi - 41feec: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 41fef3: e8 08 27 02 00 callq 442600 <__lll_unlock_wake_private> - 41fef8: 48 81 c4 80 00 00 00 add $0x80,%rsp - 41feff: 48 85 d2 test %rdx,%rdx - 41ff02: 0f 84 70 01 00 00 je 420078 <__libc_valloc+0x268> - 41ff08: 48 8b 42 f8 mov -0x8(%rdx),%rax - 41ff0c: a8 02 test $0x2,%al - 41ff0e: 75 16 jne 41ff26 <__libc_valloc+0x116> - 41ff10: a8 04 test $0x4,%al - 41ff12: b9 00 a8 6c 00 mov $0x6ca800,%ecx - 41ff17: 0f 85 e3 00 00 00 jne 420000 <__libc_valloc+0x1f0> - 41ff1d: 48 39 e9 cmp %rbp,%rcx - 41ff20: 0f 85 59 01 00 00 jne 42007f <__libc_valloc+0x26f> - 41ff26: 48 89 d0 mov %rdx,%rax - 41ff29: 5b pop %rbx - 41ff2a: 5d pop %rbp - 41ff2b: 41 5c pop %r12 - 41ff2d: c3 retq - 41ff2e: 66 90 xchg %ax,%ax - 41ff30: 48 b8 00 00 00 00 00 movabs $0x8000000000000000,%rax - 41ff37: 00 00 80 - 41ff3a: 48 39 c7 cmp %rax,%rdi - 41ff3d: 0f 87 f5 00 00 00 ja 420038 <__libc_valloc+0x228> - 41ff43: 48 c7 c0 df ff ff ff mov $0xffffffffffffffdf,%rax - 41ff4a: 48 29 f8 sub %rdi,%rax - 41ff4d: 49 39 c4 cmp %rax,%r12 - 41ff50: 0f 87 0a 01 00 00 ja 420060 <__libc_valloc+0x250> - 41ff56: 48 8d 47 ff lea -0x1(%rdi),%rax - 41ff5a: 48 85 f8 test %rdi,%rax - 41ff5d: 0f 84 35 01 00 00 je 420098 <__libc_valloc+0x288> - 41ff63: 48 83 ff 20 cmp $0x20,%rdi - 41ff67: bb 20 00 00 00 mov $0x20,%ebx - 41ff6c: 0f 84 f2 fe ff ff je 41fe64 <__libc_valloc+0x54> - 41ff72: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 41ff78: 48 01 db add %rbx,%rbx - 41ff7b: 48 39 df cmp %rbx,%rdi - 41ff7e: 77 f8 ja 41ff78 <__libc_valloc+0x168> - 41ff80: e9 df fe ff ff jmpq 41fe64 <__libc_valloc+0x54> - 41ff85: 0f 1f 00 nopl (%rax) - 41ff88: e8 d3 71 ff ff callq 417160 - 41ff8d: 48 85 c0 test %rax,%rax - 41ff90: 48 89 c5 mov %rax,%rbp - 41ff93: 0f 85 1f ff ff ff jne 41feb8 <__libc_valloc+0xa8> - 41ff99: 4a 8d 7c 23 20 lea 0x20(%rbx,%r12,1),%rdi - 41ff9e: 31 f6 xor %esi,%esi - 41ffa0: e8 ab 74 ff ff callq 417450 - 41ffa5: 4c 89 e2 mov %r12,%rdx - 41ffa8: 48 89 de mov %rbx,%rsi - 41ffab: 48 89 c7 mov %rax,%rdi - 41ffae: 48 89 c5 mov %rax,%rbp - 41ffb1: e8 5a c5 ff ff callq 41c510 <_int_memalign> - 41ffb6: 48 85 c0 test %rax,%rax - 41ffb9: 48 89 c2 mov %rax,%rdx - 41ffbc: 75 2a jne 41ffe8 <__libc_valloc+0x1d8> - 41ffbe: 48 85 ed test %rbp,%rbp - 41ffc1: 74 25 je 41ffe8 <__libc_valloc+0x1d8> - 41ffc3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 41ffc8: 90 nop - 41ffc9: 48 89 ef mov %rbp,%rdi - 41ffcc: 4c 89 e6 mov %r12,%rsi - 41ffcf: e8 1c 7a ff ff callq 4179f0 - 41ffd4: 4c 89 e2 mov %r12,%rdx - 41ffd7: 48 89 de mov %rbx,%rsi - 41ffda: 48 89 c7 mov %rax,%rdi - 41ffdd: 48 89 c5 mov %rax,%rbp - 41ffe0: e8 2b c5 ff ff callq 41c510 <_int_memalign> - 41ffe5: 48 89 c2 mov %rax,%rdx - 41ffe8: 48 85 ed test %rbp,%rbp - 41ffeb: 0f 85 e1 fe ff ff jne 41fed2 <__libc_valloc+0xc2> - 41fff1: e9 09 ff ff ff jmpq 41feff <__libc_valloc+0xef> - 41fff6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 41fffd: 00 00 00 - 420000: 48 8d 42 f0 lea -0x10(%rdx),%rax - 420004: 48 25 00 00 00 fc and $0xfffffffffc000000,%rax - 42000a: 48 8b 08 mov (%rax),%rcx - 42000d: e9 0b ff ff ff jmpq 41ff1d <__libc_valloc+0x10d> - 420012: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 420018: 5b pop %rbx - 420019: 4c 89 e7 mov %r12,%rdi - 42001c: 5d pop %rbp - 42001d: 41 5c pop %r12 - 42001f: e9 ec d9 ff ff jmpq 41da10 <__libc_malloc> - 420024: 0f 1f 40 00 nopl 0x0(%rax) - 420028: 5b pop %rbx - 420029: 4c 89 e6 mov %r12,%rsi - 42002c: 5d pop %rbp - 42002d: 41 5c pop %r12 - 42002f: ff e0 jmpq *%rax - 420031: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 420038: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 42003f: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) - 420046: 31 c0 xor %eax,%eax - 420048: e9 dc fe ff ff jmpq 41ff29 <__libc_valloc+0x119> - 42004d: 0f 1f 00 nopl (%rax) - 420050: e8 9b ec ff ff callq 41ecf0 - 420055: e9 cb fd ff ff jmpq 41fe25 <__libc_valloc+0x15> - 42005a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 420060: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 420067: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) - 42006e: 31 c0 xor %eax,%eax - 420070: e9 b4 fe ff ff jmpq 41ff29 <__libc_valloc+0x119> - 420075: 0f 1f 00 nopl (%rax) - 420078: 31 c0 xor %eax,%eax - 42007a: e9 aa fe ff ff jmpq 41ff29 <__libc_valloc+0x119> - 42007f: b9 08 2e 4a 00 mov $0x4a2e08,%ecx - 420084: ba 3c 0c 00 00 mov $0xc3c,%edx - 420089: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 42008e: bf 20 2a 4a 00 mov $0x4a2a20,%edi - 420093: e8 88 6d ff ff callq 416e20 <__malloc_assert> - 420098: 48 89 fb mov %rdi,%rbx - 42009b: e9 c4 fd ff ff jmpq 41fe64 <__libc_valloc+0x54> - -00000000004200a0 <__libc_pvalloc>: - 4200a0: 41 54 push %r12 - 4200a2: 55 push %rbp - 4200a3: 53 push %rbx - 4200a4: 48 83 ec 10 sub $0x10,%rsp - 4200a8: 8b 05 b6 a6 2a 00 mov 0x2aa6b6(%rip),%eax # 6ca764 <__libc_malloc_initialized> - 4200ae: 85 c0 test %eax,%eax - 4200b0: 0f 88 7a 02 00 00 js 420330 <__libc_pvalloc+0x290> - 4200b6: 48 8b 05 c3 b0 2a 00 mov 0x2ab0c3(%rip),%rax # 6cb180 <_dl_pagesize> - 4200bd: 48 c7 c6 df ff ff ff mov $0xffffffffffffffdf,%rsi - 4200c4: 48 8b 54 24 28 mov 0x28(%rsp),%rdx - 4200c9: 48 89 f3 mov %rsi,%rbx - 4200cc: 4c 8d 40 ff lea -0x1(%rax),%r8 - 4200d0: 48 89 c1 mov %rax,%rcx - 4200d3: 48 f7 d9 neg %rcx - 4200d6: 4e 8d 24 07 lea (%rdi,%r8,1),%r12 - 4200da: 49 21 cc and %rcx,%r12 - 4200dd: 48 8d 0c 00 lea (%rax,%rax,1),%rcx - 4200e1: 48 29 cb sub %rcx,%rbx - 4200e4: 48 39 df cmp %rbx,%rdi - 4200e7: 0f 87 4b 01 00 00 ja 420238 <__libc_pvalloc+0x198> - 4200ed: 48 8b 0d 84 a6 2a 00 mov 0x2aa684(%rip),%rcx # 6ca778 <__memalign_hook> - 4200f4: 48 85 c9 test %rcx,%rcx - 4200f7: 0f 85 03 02 00 00 jne 420300 <__libc_pvalloc+0x260> - 4200fd: 48 83 f8 10 cmp $0x10,%rax - 420101: 0f 86 e1 01 00 00 jbe 4202e8 <__libc_pvalloc+0x248> - 420107: 48 83 f8 1f cmp $0x1f,%rax - 42010b: 0f 87 df 00 00 00 ja 4201f0 <__libc_pvalloc+0x150> - 420111: 49 83 fc bf cmp $0xffffffffffffffbf,%r12 - 420115: 0f 87 1d 01 00 00 ja 420238 <__libc_pvalloc+0x198> - 42011b: bb 20 00 00 00 mov $0x20,%ebx - 420120: 48 c7 c0 d8 ff ff ff mov $0xffffffffffffffd8,%rax - 420127: 64 48 8b 28 mov %fs:(%rax),%rbp - 42012b: 48 85 ed test %rbp,%rbp - 42012e: 0f 84 24 01 00 00 je 420258 <__libc_pvalloc+0x1b8> - 420134: 8b 45 04 mov 0x4(%rbp),%eax - 420137: 83 e0 04 and $0x4,%eax - 42013a: 0f 85 18 01 00 00 jne 420258 <__libc_pvalloc+0x1b8> - 420140: be 01 00 00 00 mov $0x1,%esi - 420145: 83 3d 70 d0 2a 00 00 cmpl $0x0,0x2ad070(%rip) # 6cd1bc <__libc_multiple_threads> - 42014c: 74 09 je 420157 <__libc_pvalloc+0xb7> - 42014e: f0 0f b1 75 00 lock cmpxchg %esi,0x0(%rbp) - 420153: 75 08 jne 42015d <__libc_pvalloc+0xbd> - 420155: eb 1d jmp 420174 <__libc_pvalloc+0xd4> - 420157: 0f b1 75 00 cmpxchg %esi,0x0(%rbp) - 42015b: 74 17 je 420174 <__libc_pvalloc+0xd4> - 42015d: 48 8d 7d 00 lea 0x0(%rbp),%rdi - 420161: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 420168: e8 63 24 02 00 callq 4425d0 <__lll_lock_wait_private> - 42016d: 48 81 c4 80 00 00 00 add $0x80,%rsp - 420174: 4c 89 e2 mov %r12,%rdx - 420177: 48 89 de mov %rbx,%rsi - 42017a: 48 89 ef mov %rbp,%rdi - 42017d: e8 8e c3 ff ff callq 41c510 <_int_memalign> - 420182: 48 85 c0 test %rax,%rax - 420185: 48 89 c2 mov %rax,%rdx - 420188: 0f 84 0a 01 00 00 je 420298 <__libc_pvalloc+0x1f8> - 42018e: 83 3d 27 d0 2a 00 00 cmpl $0x0,0x2ad027(%rip) # 6cd1bc <__libc_multiple_threads> - 420195: 74 08 je 42019f <__libc_pvalloc+0xff> - 420197: f0 ff 4d 00 lock decl 0x0(%rbp) - 42019b: 75 07 jne 4201a4 <__libc_pvalloc+0x104> - 42019d: eb 1c jmp 4201bb <__libc_pvalloc+0x11b> - 42019f: ff 4d 00 decl 0x0(%rbp) - 4201a2: 74 17 je 4201bb <__libc_pvalloc+0x11b> - 4201a4: 48 8d 7d 00 lea 0x0(%rbp),%rdi - 4201a8: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 4201af: e8 4c 24 02 00 callq 442600 <__lll_unlock_wake_private> - 4201b4: 48 81 c4 80 00 00 00 add $0x80,%rsp - 4201bb: 48 85 d2 test %rdx,%rdx - 4201be: 0f 84 64 01 00 00 je 420328 <__libc_pvalloc+0x288> - 4201c4: 48 8b 42 f8 mov -0x8(%rdx),%rax - 4201c8: a8 02 test $0x2,%al - 4201ca: 75 16 jne 4201e2 <__libc_pvalloc+0x142> - 4201cc: a8 04 test $0x4,%al - 4201ce: b9 00 a8 6c 00 mov $0x6ca800,%ecx - 4201d3: 0f 85 f7 00 00 00 jne 4202d0 <__libc_pvalloc+0x230> - 4201d9: 48 39 cd cmp %rcx,%rbp - 4201dc: 0f 85 6a 01 00 00 jne 42034c <__libc_pvalloc+0x2ac> - 4201e2: 48 89 d0 mov %rdx,%rax - 4201e5: 48 83 c4 10 add $0x10,%rsp - 4201e9: 5b pop %rbx - 4201ea: 5d pop %rbp - 4201eb: 41 5c pop %r12 - 4201ed: c3 retq - 4201ee: 66 90 xchg %ax,%ax - 4201f0: 48 ba 00 00 00 00 00 movabs $0x8000000000000000,%rdx - 4201f7: 00 00 80 - 4201fa: 48 39 d0 cmp %rdx,%rax - 4201fd: 0f 87 0d 01 00 00 ja 420310 <__libc_pvalloc+0x270> - 420203: 48 29 c6 sub %rax,%rsi - 420206: 49 39 f4 cmp %rsi,%r12 - 420209: 77 2d ja 420238 <__libc_pvalloc+0x198> - 42020b: 4c 85 c0 test %r8,%rax - 42020e: 0f 84 30 01 00 00 je 420344 <__libc_pvalloc+0x2a4> - 420214: 48 83 f8 20 cmp $0x20,%rax - 420218: bb 20 00 00 00 mov $0x20,%ebx - 42021d: 0f 84 fd fe ff ff je 420120 <__libc_pvalloc+0x80> - 420223: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 420228: 48 01 db add %rbx,%rbx - 42022b: 48 39 d8 cmp %rbx,%rax - 42022e: 77 f8 ja 420228 <__libc_pvalloc+0x188> - 420230: e9 eb fe ff ff jmpq 420120 <__libc_pvalloc+0x80> - 420235: 0f 1f 00 nopl (%rax) - 420238: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 42023f: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) - 420246: 48 83 c4 10 add $0x10,%rsp - 42024a: 31 c0 xor %eax,%eax - 42024c: 5b pop %rbx - 42024d: 5d pop %rbp - 42024e: 41 5c pop %r12 - 420250: c3 retq - 420251: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 420258: e8 03 6f ff ff callq 417160 - 42025d: 48 85 c0 test %rax,%rax - 420260: 48 89 c5 mov %rax,%rbp - 420263: 0f 85 0b ff ff ff jne 420174 <__libc_pvalloc+0xd4> - 420269: 49 8d 7c 1c 20 lea 0x20(%r12,%rbx,1),%rdi - 42026e: 31 f6 xor %esi,%esi - 420270: e8 db 71 ff ff callq 417450 - 420275: 4c 89 e2 mov %r12,%rdx - 420278: 48 89 de mov %rbx,%rsi - 42027b: 48 89 c7 mov %rax,%rdi - 42027e: 48 89 c5 mov %rax,%rbp - 420281: e8 8a c2 ff ff callq 41c510 <_int_memalign> - 420286: 48 85 c0 test %rax,%rax - 420289: 48 89 c2 mov %rax,%rdx - 42028c: 75 2a jne 4202b8 <__libc_pvalloc+0x218> - 42028e: 48 85 ed test %rbp,%rbp - 420291: 74 25 je 4202b8 <__libc_pvalloc+0x218> - 420293: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 420298: 90 nop - 420299: 48 89 ef mov %rbp,%rdi - 42029c: 4c 89 e6 mov %r12,%rsi - 42029f: e8 4c 77 ff ff callq 4179f0 - 4202a4: 4c 89 e2 mov %r12,%rdx - 4202a7: 48 89 de mov %rbx,%rsi - 4202aa: 48 89 c7 mov %rax,%rdi - 4202ad: 48 89 c5 mov %rax,%rbp - 4202b0: e8 5b c2 ff ff callq 41c510 <_int_memalign> - 4202b5: 48 89 c2 mov %rax,%rdx - 4202b8: 48 85 ed test %rbp,%rbp - 4202bb: 0f 85 cd fe ff ff jne 42018e <__libc_pvalloc+0xee> - 4202c1: e9 f5 fe ff ff jmpq 4201bb <__libc_pvalloc+0x11b> - 4202c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4202cd: 00 00 00 - 4202d0: 48 8d 42 f0 lea -0x10(%rdx),%rax - 4202d4: 48 25 00 00 00 fc and $0xfffffffffc000000,%rax - 4202da: 48 8b 08 mov (%rax),%rcx - 4202dd: e9 f7 fe ff ff jmpq 4201d9 <__libc_pvalloc+0x139> - 4202e2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4202e8: 48 83 c4 10 add $0x10,%rsp - 4202ec: 4c 89 e7 mov %r12,%rdi - 4202ef: 5b pop %rbx - 4202f0: 5d pop %rbp - 4202f1: 41 5c pop %r12 - 4202f3: e9 18 d7 ff ff jmpq 41da10 <__libc_malloc> - 4202f8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 4202ff: 00 - 420300: 48 83 c4 10 add $0x10,%rsp - 420304: 4c 89 e6 mov %r12,%rsi - 420307: 48 89 c7 mov %rax,%rdi - 42030a: 5b pop %rbx - 42030b: 5d pop %rbp - 42030c: 41 5c pop %r12 - 42030e: ff e1 jmpq *%rcx - 420310: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 420317: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) - 42031e: 31 c0 xor %eax,%eax - 420320: e9 c0 fe ff ff jmpq 4201e5 <__libc_pvalloc+0x145> - 420325: 0f 1f 00 nopl (%rax) - 420328: 31 c0 xor %eax,%eax - 42032a: e9 b6 fe ff ff jmpq 4201e5 <__libc_pvalloc+0x145> - 42032f: 90 nop - 420330: 48 89 7c 24 08 mov %rdi,0x8(%rsp) - 420335: e8 b6 e9 ff ff callq 41ecf0 - 42033a: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi - 42033f: e9 72 fd ff ff jmpq 4200b6 <__libc_pvalloc+0x16> - 420344: 48 89 c3 mov %rax,%rbx - 420347: e9 d4 fd ff ff jmpq 420120 <__libc_pvalloc+0x80> - 42034c: b9 08 2e 4a 00 mov $0x4a2e08,%ecx - 420351: ba 3c 0c 00 00 mov $0xc3c,%edx - 420356: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 42035b: bf 20 2a 4a 00 mov $0x4a2a20,%edi - 420360: e8 bb 6a ff ff callq 416e20 <__malloc_assert> - 420365: 90 nop - 420366: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42036d: 00 00 00 - -0000000000420370 <__malloc_trim>: - 420370: 41 57 push %r15 - 420372: 41 56 push %r14 - 420374: 41 55 push %r13 - 420376: 41 54 push %r12 - 420378: 55 push %rbp - 420379: 53 push %rbx - 42037a: 48 83 ec 28 sub $0x28,%rsp - 42037e: 8b 05 e0 a3 2a 00 mov 0x2aa3e0(%rip),%eax # 6ca764 <__libc_malloc_initialized> - 420384: 48 89 7c 24 18 mov %rdi,0x18(%rsp) - 420389: 85 c0 test %eax,%eax - 42038b: 0f 88 40 02 00 00 js 4205d1 <__malloc_trim+0x261> - 420391: 48 c7 44 24 08 00 a8 movq $0x6ca800,0x8(%rsp) - 420398: 6c 00 - 42039a: c7 44 24 14 00 00 00 movl $0x0,0x14(%rsp) - 4203a1: 00 - 4203a2: be 01 00 00 00 mov $0x1,%esi - 4203a7: 31 c0 xor %eax,%eax - 4203a9: 48 8b 54 24 08 mov 0x8(%rsp),%rdx - 4203ae: 83 3d 07 ce 2a 00 00 cmpl $0x0,0x2ace07(%rip) # 6cd1bc <__libc_multiple_threads> - 4203b5: 74 08 je 4203bf <__malloc_trim+0x4f> - 4203b7: f0 0f b1 32 lock cmpxchg %esi,(%rdx) - 4203bb: 75 07 jne 4203c4 <__malloc_trim+0x54> - 4203bd: eb 1b jmp 4203da <__malloc_trim+0x6a> - 4203bf: 0f b1 32 cmpxchg %esi,(%rdx) - 4203c2: 74 16 je 4203da <__malloc_trim+0x6a> - 4203c4: 48 8d 3a lea (%rdx),%rdi - 4203c7: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 4203ce: e8 fd 21 02 00 callq 4425d0 <__lll_lock_wait_private> - 4203d3: 48 81 c4 80 00 00 00 add $0x80,%rsp - 4203da: 45 31 db xor %r11d,%r11d - 4203dd: f6 42 04 04 testb $0x4,0x4(%rdx) - 4203e1: 74 5f je 420442 <__malloc_trim+0xd2> - 4203e3: 44 09 5c 24 14 or %r11d,0x14(%rsp) - 4203e8: 48 8b 54 24 08 mov 0x8(%rsp),%rdx - 4203ed: 83 3d c8 cd 2a 00 00 cmpl $0x0,0x2acdc8(%rip) # 6cd1bc <__libc_multiple_threads> - 4203f4: 74 07 je 4203fd <__malloc_trim+0x8d> - 4203f6: f0 ff 0a lock decl (%rdx) - 4203f9: 75 06 jne 420401 <__malloc_trim+0x91> - 4203fb: eb 1a jmp 420417 <__malloc_trim+0xa7> - 4203fd: ff 0a decl (%rdx) - 4203ff: 74 16 je 420417 <__malloc_trim+0xa7> - 420401: 48 8d 3a lea (%rdx),%rdi - 420404: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 42040b: e8 f0 21 02 00 callq 442600 <__lll_unlock_wake_private> - 420410: 48 81 c4 80 00 00 00 add $0x80,%rsp - 420417: 48 8b 82 68 08 00 00 mov 0x868(%rdx),%rax - 42041e: 48 3d 00 a8 6c 00 cmp $0x6ca800,%rax - 420424: 48 89 44 24 08 mov %rax,0x8(%rsp) - 420429: 0f 85 73 ff ff ff jne 4203a2 <__malloc_trim+0x32> - 42042f: 8b 44 24 14 mov 0x14(%rsp),%eax - 420433: 48 83 c4 28 add $0x28,%rsp - 420437: 5b pop %rbx - 420438: 5d pop %rbp - 420439: 41 5c pop %r12 - 42043b: 41 5d pop %r13 - 42043d: 41 5e pop %r14 - 42043f: 41 5f pop %r15 - 420441: c3 retq - 420442: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi - 420447: e8 e4 79 ff ff callq 417e30 - 42044c: 48 8b 0d 2d ad 2a 00 mov 0x2aad2d(%rip),%rcx # 6cb180 <_dl_pagesize> - 420453: 48 81 f9 ff 03 00 00 cmp $0x3ff,%rcx - 42045a: 0f 87 d3 00 00 00 ja 420533 <__malloc_trim+0x1c3> - 420460: 89 c8 mov %ecx,%eax - 420462: c1 e8 04 shr $0x4,%eax - 420465: 89 44 24 10 mov %eax,0x10(%rsp) - 420469: 4c 8d 71 ff lea -0x1(%rcx),%r14 - 42046d: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 420472: 45 31 db xor %r11d,%r11d - 420475: bd 01 00 00 00 mov $0x1,%ebp - 42047a: 4c 8d 69 2f lea 0x2f(%rcx),%r13 - 42047e: 4d 89 f7 mov %r14,%r15 - 420481: 4c 8d 60 58 lea 0x58(%rax),%r12 - 420485: 49 f7 d7 not %r15 - 420488: eb 1b jmp 4204a5 <__malloc_trim+0x135> - 42048a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 420490: 39 6c 24 10 cmp %ebp,0x10(%rsp) - 420494: 7e 14 jle 4204aa <__malloc_trim+0x13a> - 420496: 83 c5 01 add $0x1,%ebp - 420499: 49 83 c4 10 add $0x10,%r12 - 42049d: 81 fd 80 00 00 00 cmp $0x80,%ebp - 4204a3: 74 75 je 42051a <__malloc_trim+0x1aa> - 4204a5: 83 fd 01 cmp $0x1,%ebp - 4204a8: 75 e6 jne 420490 <__malloc_trim+0x120> - 4204aa: 49 8b 5c 24 18 mov 0x18(%r12),%rbx - 4204af: 49 39 dc cmp %rbx,%r12 - 4204b2: 75 15 jne 4204c9 <__malloc_trim+0x159> - 4204b4: eb e0 jmp 420496 <__malloc_trim+0x126> - 4204b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4204bd: 00 00 00 - 4204c0: 48 8b 5b 18 mov 0x18(%rbx),%rbx - 4204c4: 49 39 dc cmp %rbx,%r12 - 4204c7: 74 cd je 420496 <__malloc_trim+0x126> - 4204c9: 48 8b 73 08 mov 0x8(%rbx),%rsi - 4204cd: 48 83 e6 f8 and $0xfffffffffffffff8,%rsi - 4204d1: 4c 39 ee cmp %r13,%rsi - 4204d4: 76 ea jbe 4204c0 <__malloc_trim+0x150> - 4204d6: 4a 8d 3c 2b lea (%rbx,%r13,1),%rdi - 4204da: 48 8d 43 30 lea 0x30(%rbx),%rax - 4204de: 4c 21 ff and %r15,%rdi - 4204e1: 48 39 c7 cmp %rax,%rdi - 4204e4: 0f 82 b3 00 00 00 jb 42059d <__malloc_trim+0x22d> - 4204ea: 48 8d 04 33 lea (%rbx,%rsi,1),%rax - 4204ee: 48 39 c7 cmp %rax,%rdi - 4204f1: 0f 83 8d 00 00 00 jae 420584 <__malloc_trim+0x214> - 4204f7: 48 89 f8 mov %rdi,%rax - 4204fa: 48 29 d8 sub %rbx,%rax - 4204fd: 48 29 c6 sub %rax,%rsi - 420500: 49 39 f6 cmp %rsi,%r14 - 420503: 73 bb jae 4204c0 <__malloc_trim+0x150> - 420505: 4c 21 fe and %r15,%rsi - 420508: ba 04 00 00 00 mov $0x4,%edx - 42050d: e8 de f7 01 00 callq 43fcf0 <__madvise> - 420512: 41 bb 01 00 00 00 mov $0x1,%r11d - 420518: eb a6 jmp 4204c0 <__malloc_trim+0x150> - 42051a: 31 c0 xor %eax,%eax - 42051c: 48 81 7c 24 08 00 a8 cmpq $0x6ca800,0x8(%rsp) - 420523: 6c 00 - 420525: 0f 84 d1 00 00 00 je 4205fc <__malloc_trim+0x28c> - 42052b: 41 09 c3 or %eax,%r11d - 42052e: e9 b0 fe ff ff jmpq 4203e3 <__malloc_trim+0x73> - 420533: 49 89 cc mov %rcx,%r12 - 420536: 49 c1 ec 06 shr $0x6,%r12 - 42053a: 49 83 fc 30 cmp $0x30,%r12 - 42053e: 77 0e ja 42054e <__malloc_trim+0x1de> - 420540: 41 8d 44 24 30 lea 0x30(%r12),%eax - 420545: 89 44 24 10 mov %eax,0x10(%rsp) - 420549: e9 1b ff ff ff jmpq 420469 <__malloc_trim+0xf9> - 42054e: 49 89 cc mov %rcx,%r12 - 420551: 49 c1 ec 09 shr $0x9,%r12 - 420555: 49 83 fc 14 cmp $0x14,%r12 - 420559: 76 1b jbe 420576 <__malloc_trim+0x206> - 42055b: 49 89 cc mov %rcx,%r12 - 42055e: 49 c1 ec 0c shr $0xc,%r12 - 420562: 49 83 fc 0a cmp $0xa,%r12 - 420566: 77 4e ja 4205b6 <__malloc_trim+0x246> - 420568: 41 8d 44 24 6e lea 0x6e(%r12),%eax - 42056d: 89 44 24 10 mov %eax,0x10(%rsp) - 420571: e9 f3 fe ff ff jmpq 420469 <__malloc_trim+0xf9> - 420576: 41 8d 44 24 5b lea 0x5b(%r12),%eax - 42057b: 89 44 24 10 mov %eax,0x10(%rsp) - 42057f: e9 e5 fe ff ff jmpq 420469 <__malloc_trim+0xf9> - 420584: b9 1a 23 4a 00 mov $0x4a231a,%ecx - 420589: ba aa 11 00 00 mov $0x11aa,%edx - 42058e: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 420593: bf 38 2b 4a 00 mov $0x4a2b38,%edi - 420598: e8 83 68 ff ff callq 416e20 <__malloc_assert> - 42059d: b9 1a 23 4a 00 mov $0x4a231a,%ecx - 4205a2: ba a9 11 00 00 mov $0x11a9,%edx - 4205a7: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 4205ac: bf 00 2b 4a 00 mov $0x4a2b00,%edi - 4205b1: e8 6a 68 ff ff callq 416e20 <__malloc_assert> - 4205b6: 49 89 cc mov %rcx,%r12 - 4205b9: 49 c1 ec 0f shr $0xf,%r12 - 4205bd: 49 83 fc 04 cmp $0x4,%r12 - 4205c1: 77 18 ja 4205db <__malloc_trim+0x26b> - 4205c3: 41 8d 44 24 77 lea 0x77(%r12),%eax - 4205c8: 89 44 24 10 mov %eax,0x10(%rsp) - 4205cc: e9 98 fe ff ff jmpq 420469 <__malloc_trim+0xf9> - 4205d1: e8 1a e7 ff ff callq 41ecf0 - 4205d6: e9 b6 fd ff ff jmpq 420391 <__malloc_trim+0x21> - 4205db: 48 89 c8 mov %rcx,%rax - 4205de: 48 c1 e8 12 shr $0x12,%rax - 4205e2: 44 8d 60 7c lea 0x7c(%rax),%r12d - 4205e6: 48 83 f8 02 cmp $0x2,%rax - 4205ea: b8 7e 00 00 00 mov $0x7e,%eax - 4205ef: 41 0f 46 c4 cmovbe %r12d,%eax - 4205f3: 89 44 24 10 mov %eax,0x10(%rsp) - 4205f7: e9 6d fe ff ff jmpq 420469 <__malloc_trim+0xf9> - 4205fc: 48 8b 7c 24 18 mov 0x18(%rsp),%rdi - 420601: ba 80 b0 6c 00 mov $0x6cb080,%edx - 420606: be 58 a8 6c 00 mov $0x6ca858,%esi - 42060b: 44 89 5c 24 10 mov %r11d,0x10(%rsp) - 420610: e8 8b 6d ff ff callq 4173a0 - 420615: 44 8b 5c 24 10 mov 0x10(%rsp),%r11d - 42061a: e9 0c ff ff ff jmpq 42052b <__malloc_trim+0x1bb> - 42061f: 90 nop - -0000000000420620 <__libc_mallinfo>: - 420620: 41 54 push %r12 - 420622: 55 push %rbp - 420623: 49 89 fc mov %rdi,%r12 - 420626: 53 push %rbx - 420627: 48 83 ec 30 sub $0x30,%rsp - 42062b: 8b 05 33 a1 2a 00 mov 0x2aa133(%rip),%eax # 6ca764 <__libc_malloc_initialized> - 420631: 85 c0 test %eax,%eax - 420633: 0f 88 ef 00 00 00 js 420728 <__libc_mallinfo+0x108> - 420639: 48 c7 04 24 00 00 00 movq $0x0,(%rsp) - 420640: 00 - 420641: 48 c7 44 24 08 00 00 movq $0x0,0x8(%rsp) - 420648: 00 00 - 42064a: bb 00 a8 6c 00 mov $0x6ca800,%ebx - 42064f: 48 c7 44 24 10 00 00 movq $0x0,0x10(%rsp) - 420656: 00 00 - 420658: 48 c7 44 24 18 00 00 movq $0x0,0x18(%rsp) - 42065f: 00 00 - 420661: bd 01 00 00 00 mov $0x1,%ebp - 420666: 48 c7 44 24 20 00 00 movq $0x0,0x20(%rsp) - 42066d: 00 00 - 42066f: 90 nop - 420670: 89 ee mov %ebp,%esi - 420672: 31 c0 xor %eax,%eax - 420674: 83 3d 41 cb 2a 00 00 cmpl $0x0,0x2acb41(%rip) # 6cd1bc <__libc_multiple_threads> - 42067b: 74 08 je 420685 <__libc_mallinfo+0x65> - 42067d: f0 0f b1 33 lock cmpxchg %esi,(%rbx) - 420681: 75 07 jne 42068a <__libc_mallinfo+0x6a> - 420683: eb 1b jmp 4206a0 <__libc_mallinfo+0x80> - 420685: 0f b1 33 cmpxchg %esi,(%rbx) - 420688: 74 16 je 4206a0 <__libc_mallinfo+0x80> - 42068a: 48 8d 3b lea (%rbx),%rdi - 42068d: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 420694: e8 37 1f 02 00 callq 4425d0 <__lll_lock_wait_private> - 420699: 48 81 c4 80 00 00 00 add $0x80,%rsp - 4206a0: 48 89 e6 mov %rsp,%rsi - 4206a3: 48 89 df mov %rbx,%rdi - 4206a6: e8 15 82 ff ff callq 4188c0 - 4206ab: 83 3d 0a cb 2a 00 00 cmpl $0x0,0x2acb0a(%rip) # 6cd1bc <__libc_multiple_threads> - 4206b2: 74 07 je 4206bb <__libc_mallinfo+0x9b> - 4206b4: f0 ff 0b lock decl (%rbx) - 4206b7: 75 06 jne 4206bf <__libc_mallinfo+0x9f> - 4206b9: eb 1a jmp 4206d5 <__libc_mallinfo+0xb5> - 4206bb: ff 0b decl (%rbx) - 4206bd: 74 16 je 4206d5 <__libc_mallinfo+0xb5> - 4206bf: 48 8d 3b lea (%rbx),%rdi - 4206c2: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 4206c9: e8 32 1f 02 00 callq 442600 <__lll_unlock_wake_private> - 4206ce: 48 81 c4 80 00 00 00 add $0x80,%rsp - 4206d5: 48 8b 9b 68 08 00 00 mov 0x868(%rbx),%rbx - 4206dc: 48 81 fb 00 a8 6c 00 cmp $0x6ca800,%rbx - 4206e3: 75 8b jne 420670 <__libc_mallinfo+0x50> - 4206e5: 48 8b 04 24 mov (%rsp),%rax - 4206e9: 49 89 04 24 mov %rax,(%r12) - 4206ed: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4206f2: 49 89 44 24 08 mov %rax,0x8(%r12) - 4206f7: 48 8b 44 24 10 mov 0x10(%rsp),%rax - 4206fc: 49 89 44 24 10 mov %rax,0x10(%r12) - 420701: 48 8b 44 24 18 mov 0x18(%rsp),%rax - 420706: 49 89 44 24 18 mov %rax,0x18(%r12) - 42070b: 48 8b 44 24 20 mov 0x20(%rsp),%rax - 420710: 49 89 44 24 20 mov %rax,0x20(%r12) - 420715: 48 83 c4 30 add $0x30,%rsp - 420719: 4c 89 e0 mov %r12,%rax - 42071c: 5b pop %rbx - 42071d: 5d pop %rbp - 42071e: 41 5c pop %r12 - 420720: c3 retq - 420721: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 420728: e8 c3 e5 ff ff callq 41ecf0 - 42072d: e9 07 ff ff ff jmpq 420639 <__libc_mallinfo+0x19> - 420732: 0f 1f 40 00 nopl 0x0(%rax) - 420736: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42073d: 00 00 00 - -0000000000420740 <__malloc_stats>: - 420740: 41 57 push %r15 - 420742: 41 56 push %r14 - 420744: 41 55 push %r13 - 420746: 41 54 push %r12 - 420748: 55 push %rbp - 420749: 53 push %rbx - 42074a: 48 83 ec 38 sub $0x38,%rsp - 42074e: 8b 05 10 a0 2a 00 mov 0x2aa010(%rip),%eax # 6ca764 <__libc_malloc_initialized> - 420754: 4c 8b 25 7d a0 2a 00 mov 0x2aa07d(%rip),%r12 # 6ca7d8 - 42075b: 85 c0 test %eax,%eax - 42075d: 45 89 e5 mov %r12d,%r13d - 420760: 0f 88 ba 01 00 00 js 420920 <__malloc_stats+0x1e0> - 420766: 48 8b 05 cb 9f 2a 00 mov 0x2a9fcb(%rip),%rax # 6ca738 <_IO_stderr> - 42076d: bb 00 a8 6c 00 mov $0x6ca800,%ebx - 420772: 31 ed xor %ebp,%ebp - 420774: 41 be 01 00 00 00 mov $0x1,%r14d - 42077a: 44 8b 78 74 mov 0x74(%rax),%r15d - 42077e: 44 89 fa mov %r15d,%edx - 420781: 83 ca 02 or $0x2,%edx - 420784: 89 50 74 mov %edx,0x74(%rax) - 420787: eb 0a jmp 420793 <__malloc_stats+0x53> - 420789: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 420790: 83 c5 01 add $0x1,%ebp - 420793: 48 c7 04 24 00 00 00 movq $0x0,(%rsp) - 42079a: 00 - 42079b: 48 c7 44 24 08 00 00 movq $0x0,0x8(%rsp) - 4207a2: 00 00 - 4207a4: 44 89 f6 mov %r14d,%esi - 4207a7: 48 c7 44 24 10 00 00 movq $0x0,0x10(%rsp) - 4207ae: 00 00 - 4207b0: 48 c7 44 24 18 00 00 movq $0x0,0x18(%rsp) - 4207b7: 00 00 - 4207b9: 31 c0 xor %eax,%eax - 4207bb: 48 c7 44 24 20 00 00 movq $0x0,0x20(%rsp) - 4207c2: 00 00 - 4207c4: 83 3d f1 c9 2a 00 00 cmpl $0x0,0x2ac9f1(%rip) # 6cd1bc <__libc_multiple_threads> - 4207cb: 74 08 je 4207d5 <__malloc_stats+0x95> - 4207cd: f0 0f b1 33 lock cmpxchg %esi,(%rbx) - 4207d1: 75 07 jne 4207da <__malloc_stats+0x9a> - 4207d3: eb 1b jmp 4207f0 <__malloc_stats+0xb0> - 4207d5: 0f b1 33 cmpxchg %esi,(%rbx) - 4207d8: 74 16 je 4207f0 <__malloc_stats+0xb0> - 4207da: 48 8d 3b lea (%rbx),%rdi - 4207dd: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 4207e4: e8 e7 1d 02 00 callq 4425d0 <__lll_lock_wait_private> - 4207e9: 48 81 c4 80 00 00 00 add $0x80,%rsp - 4207f0: 48 89 e6 mov %rsp,%rsi - 4207f3: 48 89 df mov %rbx,%rdi - 4207f6: e8 c5 80 ff ff callq 4188c0 - 4207fb: 48 8b 3d 36 9f 2a 00 mov 0x2a9f36(%rip),%rdi # 6ca738 <_IO_stderr> - 420802: 89 ea mov %ebp,%edx - 420804: be 5e 22 4a 00 mov $0x4a225e,%esi - 420809: 31 c0 xor %eax,%eax - 42080b: e8 90 bb 03 00 callq 45c3a0 <__fprintf> - 420810: 8b 14 24 mov (%rsp),%edx - 420813: 48 8b 3d 1e 9f 2a 00 mov 0x2a9f1e(%rip),%rdi # 6ca738 <_IO_stderr> - 42081a: be 69 22 4a 00 mov $0x4a2269,%esi - 42081f: 31 c0 xor %eax,%eax - 420821: e8 7a bb 03 00 callq 45c3a0 <__fprintf> - 420826: 8b 54 24 1c mov 0x1c(%rsp),%edx - 42082a: 48 8b 3d 07 9f 2a 00 mov 0x2a9f07(%rip),%rdi # 6ca738 <_IO_stderr> - 420831: be 82 22 4a 00 mov $0x4a2282,%esi - 420836: 31 c0 xor %eax,%eax - 420838: e8 63 bb 03 00 callq 45c3a0 <__fprintf> - 42083d: 44 03 24 24 add (%rsp),%r12d - 420841: 44 03 6c 24 1c add 0x1c(%rsp),%r13d - 420846: 83 3d 6f c9 2a 00 00 cmpl $0x0,0x2ac96f(%rip) # 6cd1bc <__libc_multiple_threads> - 42084d: 74 07 je 420856 <__malloc_stats+0x116> - 42084f: f0 ff 0b lock decl (%rbx) - 420852: 75 06 jne 42085a <__malloc_stats+0x11a> - 420854: eb 1a jmp 420870 <__malloc_stats+0x130> - 420856: ff 0b decl (%rbx) - 420858: 74 16 je 420870 <__malloc_stats+0x130> - 42085a: 48 8d 3b lea (%rbx),%rdi - 42085d: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 420864: e8 97 1d 02 00 callq 442600 <__lll_unlock_wake_private> - 420869: 48 81 c4 80 00 00 00 add $0x80,%rsp - 420870: 48 8b 9b 68 08 00 00 mov 0x868(%rbx),%rbx - 420877: 48 81 fb 00 a8 6c 00 cmp $0x6ca800,%rbx - 42087e: 0f 85 0c ff ff ff jne 420790 <__malloc_stats+0x50> - 420884: 48 8b 0d ad 9e 2a 00 mov 0x2a9ead(%rip),%rcx # 6ca738 <_IO_stderr> - 42088b: ba 14 00 00 00 mov $0x14,%edx - 420890: be 01 00 00 00 mov $0x1,%esi - 420895: bf 9b 22 4a 00 mov $0x4a229b,%edi - 42089a: e8 e1 24 04 00 callq 462d80 <_IO_fwrite> - 42089f: 48 8b 3d 92 9e 2a 00 mov 0x2a9e92(%rip),%rdi # 6ca738 <_IO_stderr> - 4208a6: 44 89 e2 mov %r12d,%edx - 4208a9: be 69 22 4a 00 mov $0x4a2269,%esi - 4208ae: 31 c0 xor %eax,%eax - 4208b0: e8 eb ba 03 00 callq 45c3a0 <__fprintf> - 4208b5: 48 8b 3d 7c 9e 2a 00 mov 0x2a9e7c(%rip),%rdi # 6ca738 <_IO_stderr> - 4208bc: 44 89 ea mov %r13d,%edx - 4208bf: be 82 22 4a 00 mov $0x4a2282,%esi - 4208c4: 31 c0 xor %eax,%eax - 4208c6: e8 d5 ba 03 00 callq 45c3a0 <__fprintf> - 4208cb: 8b 15 ff 9e 2a 00 mov 0x2a9eff(%rip),%edx # 6ca7d0 - 4208d1: 48 8b 3d 60 9e 2a 00 mov 0x2a9e60(%rip),%rdi # 6ca738 <_IO_stderr> - 4208d8: be b0 22 4a 00 mov $0x4a22b0,%esi - 4208dd: 31 c0 xor %eax,%eax - 4208df: e8 bc ba 03 00 callq 45c3a0 <__fprintf> - 4208e4: 48 8b 15 f5 9e 2a 00 mov 0x2a9ef5(%rip),%rdx # 6ca7e0 - 4208eb: 48 8b 3d 46 9e 2a 00 mov 0x2a9e46(%rip),%rdi # 6ca738 <_IO_stderr> - 4208f2: be c9 22 4a 00 mov $0x4a22c9,%esi - 4208f7: 31 c0 xor %eax,%eax - 4208f9: e8 a2 ba 03 00 callq 45c3a0 <__fprintf> - 4208fe: 48 8b 05 33 9e 2a 00 mov 0x2a9e33(%rip),%rax # 6ca738 <_IO_stderr> - 420905: 44 09 78 74 or %r15d,0x74(%rax) - 420909: 48 83 c4 38 add $0x38,%rsp - 42090d: 5b pop %rbx - 42090e: 5d pop %rbp - 42090f: 41 5c pop %r12 - 420911: 41 5d pop %r13 - 420913: 41 5e pop %r14 - 420915: 41 5f pop %r15 - 420917: c3 retq - 420918: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 42091f: 00 - 420920: e8 cb e3 ff ff callq 41ecf0 - 420925: e9 3c fe ff ff jmpq 420766 <__malloc_stats+0x26> - 42092a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - -0000000000420930 <__malloc_info.part.7>: - 420930: 41 57 push %r15 - 420932: 41 56 push %r14 - 420934: 41 55 push %r13 - 420936: 41 54 push %r12 - 420938: 55 push %rbp - 420939: 53 push %rbx - 42093a: 48 89 fb mov %rdi,%rbx - 42093d: 48 81 ec 98 11 00 00 sub $0x1198,%rsp - 420944: 8b 0d 1a 9e 2a 00 mov 0x2a9e1a(%rip),%ecx # 6ca764 <__libc_malloc_initialized> - 42094a: 85 c9 test %ecx,%ecx - 42094c: 0f 88 55 04 00 00 js 420da7 <__malloc_info.part.7+0x477> - 420952: 48 89 de mov %rbx,%rsi - 420955: bf e3 22 4a 00 mov $0x4a22e3,%edi - 42095a: e8 31 22 04 00 callq 462b90 <_IO_fputs> - 42095f: 48 8d 84 24 b8 01 00 lea 0x1b8(%rsp),%rax - 420966: 00 - 420967: 48 c7 44 24 10 00 a8 movq $0x6ca800,0x10(%rsp) - 42096e: 6c 00 - 420970: 48 c7 44 24 20 00 00 movq $0x0,0x20(%rsp) - 420977: 00 00 - 420979: 48 c7 44 24 18 00 00 movq $0x0,0x18(%rsp) - 420980: 00 00 - 420982: 48 c7 44 24 50 00 00 movq $0x0,0x50(%rsp) - 420989: 00 00 - 42098b: 31 d2 xor %edx,%edx - 42098d: 48 c7 44 24 48 00 00 movq $0x0,0x48(%rsp) - 420994: 00 00 - 420996: 48 c7 44 24 30 00 00 movq $0x0,0x30(%rsp) - 42099d: 00 00 - 42099f: 48 c7 44 24 40 00 00 movq $0x0,0x40(%rsp) - 4209a6: 00 00 - 4209a8: 48 c7 44 24 28 00 00 movq $0x0,0x28(%rsp) - 4209af: 00 00 - 4209b1: 48 c7 44 24 38 00 00 movq $0x0,0x38(%rsp) - 4209b8: 00 00 - 4209ba: 48 89 44 24 68 mov %rax,0x68(%rsp) - 4209bf: 8d 42 01 lea 0x1(%rdx),%eax - 4209c2: be f9 22 4a 00 mov $0x4a22f9,%esi - 4209c7: 48 89 df mov %rbx,%rdi - 4209ca: 89 44 24 64 mov %eax,0x64(%rsp) - 4209ce: 31 c0 xor %eax,%eax - 4209d0: e8 cb b9 03 00 callq 45c3a0 <__fprintf> - 4209d5: be 01 00 00 00 mov $0x1,%esi - 4209da: 31 c0 xor %eax,%eax - 4209dc: 48 8b 54 24 10 mov 0x10(%rsp),%rdx - 4209e1: 83 3d d4 c7 2a 00 00 cmpl $0x0,0x2ac7d4(%rip) # 6cd1bc <__libc_multiple_threads> - 4209e8: 74 08 je 4209f2 <__malloc_info.part.7+0xc2> - 4209ea: f0 0f b1 32 lock cmpxchg %esi,(%rdx) - 4209ee: 75 07 jne 4209f7 <__malloc_info.part.7+0xc7> - 4209f0: eb 1b jmp 420a0d <__malloc_info.part.7+0xdd> - 4209f2: 0f b1 32 cmpxchg %esi,(%rdx) - 4209f5: 74 16 je 420a0d <__malloc_info.part.7+0xdd> - 4209f7: 48 8d 3a lea (%rdx),%rdi - 4209fa: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 420a01: e8 ca 1b 02 00 callq 4425d0 <__lll_lock_wait_private> - 420a06: 48 81 c4 80 00 00 00 add $0x80,%rsp - 420a0d: 4c 8b 4c 24 68 mov 0x68(%rsp),%r9 - 420a12: 48 8d 7a 08 lea 0x8(%rdx),%rdi - 420a16: 48 8d 4c 24 78 lea 0x78(%rsp),%rcx - 420a1b: 45 31 c0 xor %r8d,%r8d - 420a1e: 45 31 e4 xor %r12d,%r12d - 420a21: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 420a28: 48 8b 07 mov (%rdi),%rax - 420a2b: 48 85 c0 test %rax,%rax - 420a2e: 0f 84 fa 02 00 00 je 420d2e <__malloc_info.part.7+0x3fe> - 420a34: 48 8b 70 08 mov 0x8(%rax),%rsi - 420a38: 31 d2 xor %edx,%edx - 420a3a: 48 83 e6 f8 and $0xfffffffffffffff8,%rsi - 420a3e: 66 90 xchg %ax,%ax - 420a40: 48 8b 40 10 mov 0x10(%rax),%rax - 420a44: 48 83 c2 01 add $0x1,%rdx - 420a48: 48 85 c0 test %rax,%rax - 420a4b: 75 f3 jne 420a40 <__malloc_info.part.7+0x110> - 420a4d: 48 89 f0 mov %rsi,%rax - 420a50: 49 01 d0 add %rdx,%r8 - 420a53: 48 89 31 mov %rsi,(%rcx) - 420a56: 48 0f af c2 imul %rdx,%rax - 420a5a: 48 89 51 10 mov %rdx,0x10(%rcx) - 420a5e: 49 01 c4 add %rax,%r12 - 420a61: 48 8d 46 f1 lea -0xf(%rsi),%rax - 420a65: 48 89 41 f8 mov %rax,-0x8(%rcx) - 420a69: 48 0f af 11 imul (%rcx),%rdx - 420a6d: 48 83 c1 20 add $0x20,%rcx - 420a71: 48 83 c7 08 add $0x8,%rdi - 420a75: 48 89 51 e8 mov %rdx,-0x18(%rcx) - 420a79: 49 39 c9 cmp %rcx,%r9 - 420a7c: 75 aa jne 420a28 <__malloc_info.part.7+0xf8> - 420a7e: 48 8b 44 24 10 mov 0x10(%rsp),%rax - 420a83: 4c 8d 94 24 b0 01 00 lea 0x1b0(%rsp),%r10 - 420a8a: 00 - 420a8b: 4c 8d 9c 24 90 11 00 lea 0x1190(%rsp),%r11 - 420a92: 00 - 420a93: 4c 89 44 24 58 mov %r8,0x58(%rsp) - 420a98: 45 31 f6 xor %r14d,%r14d - 420a9b: 45 31 c0 xor %r8d,%r8d - 420a9e: 4c 8d 48 58 lea 0x58(%rax),%r9 - 420aa2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 420aa8: 49 8b 51 10 mov 0x10(%r9),%rdx - 420aac: 66 0f ef d2 pxor %xmm2,%xmm2 - 420ab0: 66 0f 6f 0d 28 25 08 movdqa 0x82528(%rip),%xmm1 # 4a2fe0 <__func__.10972+0x20> - 420ab7: 00 - 420ab8: 48 85 d2 test %rdx,%rdx - 420abb: 41 0f 29 0a movaps %xmm1,(%r10) - 420abf: 41 0f 29 52 10 movaps %xmm2,0x10(%r10) - 420ac4: 0f 84 56 02 00 00 je 420d20 <__malloc_info.part.7+0x3f0> - 420aca: 49 39 d1 cmp %rdx,%r9 - 420acd: 0f 84 4d 02 00 00 je 420d20 <__malloc_info.part.7+0x3f0> - 420ad3: 49 8b 42 18 mov 0x18(%r10),%rax - 420ad7: 49 8b 6a 10 mov 0x10(%r10),%rbp - 420adb: 31 c9 xor %ecx,%ecx - 420add: 49 8b 32 mov (%r10),%rsi - 420ae0: 48 8d 78 01 lea 0x1(%rax),%rdi - 420ae4: eb 0d jmp 420af3 <__malloc_info.part.7+0x1c3> - 420ae6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 420aed: 00 00 00 - 420af0: 48 89 c7 mov %rax,%rdi - 420af3: 48 8b 42 08 mov 0x8(%rdx),%rax - 420af7: 48 8b 52 10 mov 0x10(%rdx),%rdx - 420afb: 48 01 c5 add %rax,%rbp - 420afe: 48 39 c6 cmp %rax,%rsi - 420b01: 48 0f 47 f0 cmova %rax,%rsi - 420b05: 48 39 c1 cmp %rax,%rcx - 420b08: 48 0f 42 c8 cmovb %rax,%rcx - 420b0c: 49 39 d1 cmp %rdx,%r9 - 420b0f: 48 8d 47 01 lea 0x1(%rdi),%rax - 420b13: 75 db jne 420af0 <__malloc_info.part.7+0x1c0> - 420b15: 48 89 74 24 08 mov %rsi,0x8(%rsp) - 420b1a: 48 85 ff test %rdi,%rdi - 420b1d: f3 0f 7e 44 24 08 movq 0x8(%rsp),%xmm0 - 420b23: 48 89 4c 24 08 mov %rcx,0x8(%rsp) - 420b28: 0f 16 44 24 08 movhps 0x8(%rsp),%xmm0 - 420b2d: 48 89 6c 24 08 mov %rbp,0x8(%rsp) - 420b32: 41 0f 29 02 movaps %xmm0,(%r10) - 420b36: f3 0f 7e 44 24 08 movq 0x8(%rsp),%xmm0 - 420b3c: 48 89 7c 24 08 mov %rdi,0x8(%rsp) - 420b41: 0f 16 44 24 08 movhps 0x8(%rsp),%xmm0 - 420b46: 41 0f 29 42 10 movaps %xmm0,0x10(%r10) - 420b4b: 0f 84 cf 01 00 00 je 420d20 <__malloc_info.part.7+0x3f0> - 420b51: 4d 89 c7 mov %r8,%r15 - 420b54: 49 83 c2 20 add $0x20,%r10 - 420b58: 49 01 fe add %rdi,%r14 - 420b5b: 49 83 c1 10 add $0x10,%r9 - 420b5f: 4d 03 7a f0 add -0x10(%r10),%r15 - 420b63: 4d 39 d3 cmp %r10,%r11 - 420b66: 4d 89 f8 mov %r15,%r8 - 420b69: 0f 85 39 ff ff ff jne 420aa8 <__malloc_info.part.7+0x178> - 420b6f: 48 8b 74 24 10 mov 0x10(%rsp),%rsi - 420b74: 83 3d 41 c6 2a 00 00 cmpl $0x0,0x2ac641(%rip) # 6cd1bc <__libc_multiple_threads> - 420b7b: 74 07 je 420b84 <__malloc_info.part.7+0x254> - 420b7d: f0 ff 0e lock decl (%rsi) - 420b80: 75 06 jne 420b88 <__malloc_info.part.7+0x258> - 420b82: eb 1a jmp 420b9e <__malloc_info.part.7+0x26e> - 420b84: ff 0e decl (%rsi) - 420b86: 74 16 je 420b9e <__malloc_info.part.7+0x26e> - 420b88: 48 8d 3e lea (%rsi),%rdi - 420b8b: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 420b92: e8 69 1a 02 00 callq 442600 <__lll_unlock_wake_private> - 420b97: 48 81 c4 80 00 00 00 add $0x80,%rsp - 420b9e: 48 8b 74 24 58 mov 0x58(%rsp),%rsi - 420ba3: 4c 01 64 24 30 add %r12,0x30(%rsp) - 420ba8: 48 8d ac 24 88 00 00 lea 0x88(%rsp),%rbp - 420baf: 00 - 420bb0: 48 01 74 24 28 add %rsi,0x28(%rsp) - 420bb5: 45 31 ed xor %r13d,%r13d - 420bb8: 4c 01 74 24 38 add %r14,0x38(%rsp) - 420bbd: 4c 01 7c 24 40 add %r15,0x40(%rsp) - 420bc2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 420bc8: 49 83 fd 0a cmp $0xa,%r13 - 420bcc: 4c 8b 4d 00 mov 0x0(%rbp),%r9 - 420bd0: 74 20 je 420bf2 <__malloc_info.part.7+0x2c2> - 420bd2: 4d 85 c9 test %r9,%r9 - 420bd5: 74 1b je 420bf2 <__malloc_info.part.7+0x2c2> - 420bd7: 48 8b 4d f0 mov -0x10(%rbp),%rcx - 420bdb: 48 8b 55 e8 mov -0x18(%rbp),%rdx - 420bdf: be 60 2b 4a 00 mov $0x4a2b60,%esi - 420be4: 4c 8b 45 f8 mov -0x8(%rbp),%r8 - 420be8: 48 89 df mov %rbx,%rdi - 420beb: 31 c0 xor %eax,%eax - 420bed: e8 ae b7 03 00 callq 45c3a0 <__fprintf> - 420bf2: 49 83 c5 01 add $0x1,%r13 - 420bf6: 48 83 c5 20 add $0x20,%rbp - 420bfa: 49 81 fd 89 00 00 00 cmp $0x89,%r13 - 420c01: 75 c5 jne 420bc8 <__malloc_info.part.7+0x298> - 420c03: 4c 8b 8c 24 c8 01 00 mov 0x1c8(%rsp),%r9 - 420c0a: 00 - 420c0b: 4d 85 c9 test %r9,%r9 - 420c0e: 0f 85 38 01 00 00 jne 420d4c <__malloc_info.part.7+0x41c> - 420c14: 48 8b 6c 24 10 mov 0x10(%rsp),%rbp - 420c19: 4d 89 f9 mov %r15,%r9 - 420c1c: 4d 89 f0 mov %r14,%r8 - 420c1f: 4c 89 e1 mov %r12,%rcx - 420c22: be e8 2b 4a 00 mov $0x4a2be8,%esi - 420c27: 48 89 df mov %rbx,%rdi - 420c2a: 48 8b 85 80 08 00 00 mov 0x880(%rbp),%rax - 420c31: 48 8b 95 88 08 00 00 mov 0x888(%rbp),%rdx - 420c38: 48 01 44 24 48 add %rax,0x48(%rsp) - 420c3d: 48 01 54 24 50 add %rdx,0x50(%rsp) - 420c42: 52 push %rdx - 420c43: 50 push %rax - 420c44: 31 c0 xor %eax,%eax - 420c46: 48 8b 54 24 68 mov 0x68(%rsp),%rdx - 420c4b: e8 50 b7 03 00 callq 45c3a0 <__fprintf> - 420c50: 48 81 fd 00 a8 6c 00 cmp $0x6ca800,%rbp - 420c57: 58 pop %rax - 420c58: 5a pop %rdx - 420c59: 0f 84 19 01 00 00 je 420d78 <__malloc_info.part.7+0x448> - 420c5f: 48 8b 45 58 mov 0x58(%rbp),%rax - 420c63: be 90 2c 4a 00 mov $0x4a2c90,%esi - 420c68: 48 89 df mov %rbx,%rdi - 420c6b: 48 89 c5 mov %rax,%rbp - 420c6e: 48 89 44 24 08 mov %rax,0x8(%rsp) - 420c73: 31 c0 xor %eax,%eax - 420c75: 48 81 e5 00 00 00 fc and $0xfffffffffc000000,%rbp - 420c7c: 48 8b 4d 18 mov 0x18(%rbp),%rcx - 420c80: 48 8b 55 10 mov 0x10(%rbp),%rdx - 420c84: e8 17 b7 03 00 callq 45c3a0 <__fprintf> - 420c89: 48 8b 75 10 mov 0x10(%rbp),%rsi - 420c8d: 48 01 74 24 18 add %rsi,0x18(%rsp) - 420c92: 48 8b 75 18 mov 0x18(%rbp),%rsi - 420c96: 48 01 74 24 20 add %rsi,0x20(%rsp) - 420c9b: 48 89 de mov %rbx,%rsi - 420c9e: bf 11 23 4a 00 mov $0x4a2311,%edi - 420ca3: e8 e8 1e 04 00 callq 462b90 <_IO_fputs> - 420ca8: 48 8b 44 24 10 mov 0x10(%rsp),%rax - 420cad: 8b 54 24 64 mov 0x64(%rsp),%edx - 420cb1: 48 8b 80 68 08 00 00 mov 0x868(%rax),%rax - 420cb8: 48 3d 00 a8 6c 00 cmp $0x6ca800,%rax - 420cbe: 48 89 44 24 10 mov %rax,0x10(%rsp) - 420cc3: 0f 85 f6 fc ff ff jne 4209bf <__malloc_info.part.7+0x8f> - 420cc9: 8b 05 f9 9a 2a 00 mov 0x2a9af9(%rip),%eax # 6ca7c8 - 420ccf: ff 74 24 20 pushq 0x20(%rsp) - 420cd3: 48 89 df mov %rbx,%rdi - 420cd6: ff 74 24 20 pushq 0x20(%rsp) - 420cda: ff 74 24 60 pushq 0x60(%rsp) - 420cde: be d8 2c 4a 00 mov $0x4a2cd8,%esi - 420ce3: ff 74 24 60 pushq 0x60(%rsp) - 420ce7: ff 35 eb 9a 2a 00 pushq 0x2a9aeb(%rip) # 6ca7d8 - 420ced: 50 push %rax - 420cee: 4c 8b 4c 24 70 mov 0x70(%rsp),%r9 - 420cf3: 31 c0 xor %eax,%eax - 420cf5: 4c 8b 44 24 68 mov 0x68(%rsp),%r8 - 420cfa: 48 8b 4c 24 60 mov 0x60(%rsp),%rcx - 420cff: 48 8b 54 24 58 mov 0x58(%rsp),%rdx - 420d04: e8 97 b6 03 00 callq 45c3a0 <__fprintf> - 420d09: 48 81 c4 c8 11 00 00 add $0x11c8,%rsp - 420d10: 31 c0 xor %eax,%eax - 420d12: 5b pop %rbx - 420d13: 5d pop %rbp - 420d14: 41 5c pop %r12 - 420d16: 41 5d pop %r13 - 420d18: 41 5e pop %r14 - 420d1a: 41 5f pop %r15 - 420d1c: c3 retq - 420d1d: 0f 1f 00 nopl (%rax) - 420d20: 49 c7 02 00 00 00 00 movq $0x0,(%r10) - 420d27: 31 ff xor %edi,%edi - 420d29: e9 23 fe ff ff jmpq 420b51 <__malloc_info.part.7+0x221> - 420d2e: 48 c7 41 10 00 00 00 movq $0x0,0x10(%rcx) - 420d35: 00 - 420d36: 48 c7 01 00 00 00 00 movq $0x0,(%rcx) - 420d3d: 31 d2 xor %edx,%edx - 420d3f: 48 c7 41 f8 00 00 00 movq $0x0,-0x8(%rcx) - 420d46: 00 - 420d47: e9 1d fd ff ff jmpq 420a69 <__malloc_info.part.7+0x139> - 420d4c: 4c 8b 84 24 c0 01 00 mov 0x1c0(%rsp),%r8 - 420d53: 00 - 420d54: 48 8b 8c 24 b8 01 00 mov 0x1b8(%rsp),%rcx - 420d5b: 00 - 420d5c: be a8 2b 4a 00 mov $0x4a2ba8,%esi - 420d61: 48 8b 94 24 b0 01 00 mov 0x1b0(%rsp),%rdx - 420d68: 00 - 420d69: 48 89 df mov %rbx,%rdi - 420d6c: 31 c0 xor %eax,%eax - 420d6e: e8 2d b6 03 00 callq 45c3a0 <__fprintf> - 420d73: e9 9c fe ff ff jmpq 420c14 <__malloc_info.part.7+0x2e4> - 420d78: 48 8b 15 01 a3 2a 00 mov 0x2aa301(%rip),%rdx # 6cb080 - 420d7f: be 90 2c 4a 00 mov $0x4a2c90,%esi - 420d84: 48 89 df mov %rbx,%rdi - 420d87: 31 c0 xor %eax,%eax - 420d89: 48 89 d1 mov %rdx,%rcx - 420d8c: e8 0f b6 03 00 callq 45c3a0 <__fprintf> - 420d91: 48 8b 05 e8 a2 2a 00 mov 0x2aa2e8(%rip),%rax # 6cb080 - 420d98: 48 01 44 24 18 add %rax,0x18(%rsp) - 420d9d: 48 01 44 24 20 add %rax,0x20(%rsp) - 420da2: e9 f4 fe ff ff jmpq 420c9b <__malloc_info.part.7+0x36b> - 420da7: e8 44 df ff ff callq 41ecf0 - 420dac: e9 a1 fb ff ff jmpq 420952 <__malloc_info.part.7+0x22> - 420db1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 420db6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 420dbd: 00 00 00 - -0000000000420dc0 <__posix_memalign>: - 420dc0: 40 f6 c6 07 test $0x7,%sil - 420dc4: b8 16 00 00 00 mov $0x16,%eax - 420dc9: 74 05 je 420dd0 <__posix_memalign+0x10> - 420dcb: c3 retq - 420dcc: 0f 1f 40 00 nopl 0x0(%rax) - 420dd0: 48 89 f0 mov %rsi,%rax - 420dd3: 48 c1 e8 03 shr $0x3,%rax - 420dd7: 48 8d 48 ff lea -0x1(%rax),%rcx - 420ddb: 48 85 c1 test %rax,%rcx - 420dde: 0f 85 7c 01 00 00 jne 420f60 <__posix_memalign+0x1a0> - 420de4: 48 85 f6 test %rsi,%rsi - 420de7: 0f 84 73 01 00 00 je 420f60 <__posix_memalign+0x1a0> - 420ded: 41 55 push %r13 - 420def: 41 54 push %r12 - 420df1: 48 89 f0 mov %rsi,%rax - 420df4: 55 push %rbp - 420df5: 53 push %rbx - 420df6: 48 89 fd mov %rdi,%rbp - 420df9: 48 89 d3 mov %rdx,%rbx - 420dfc: 48 83 ec 08 sub $0x8,%rsp - 420e00: 48 8b 0d 71 99 2a 00 mov 0x2a9971(%rip),%rcx # 6ca778 <__memalign_hook> - 420e07: 48 85 c9 test %rcx,%rcx - 420e0a: 48 8b 54 24 28 mov 0x28(%rsp),%rdx - 420e0f: 0f 85 51 01 00 00 jne 420f66 <__posix_memalign+0x1a6> - 420e15: 48 83 fe 10 cmp $0x10,%rsi - 420e19: 0f 86 b9 01 00 00 jbe 420fd8 <__posix_memalign+0x218> - 420e1f: 48 83 fe 1f cmp $0x1f,%rsi - 420e23: 0f 86 51 01 00 00 jbe 420f7a <__posix_memalign+0x1ba> - 420e29: 48 ba 00 00 00 00 00 movabs $0x8000000000000000,%rdx - 420e30: 00 00 80 - 420e33: 48 39 d6 cmp %rdx,%rsi - 420e36: 0f 87 c8 01 00 00 ja 421004 <__posix_memalign+0x244> - 420e3c: 48 c7 c2 df ff ff ff mov $0xffffffffffffffdf,%rdx - 420e43: 48 29 f2 sub %rsi,%rdx - 420e46: 48 39 d3 cmp %rdx,%rbx - 420e49: 0f 87 c8 01 00 00 ja 421017 <__posix_memalign+0x257> - 420e4f: 48 8d 56 ff lea -0x1(%rsi),%rdx - 420e53: 48 85 f2 test %rsi,%rdx - 420e56: 0f 84 e7 01 00 00 je 421043 <__posix_memalign+0x283> - 420e5c: 48 83 fe 20 cmp $0x20,%rsi - 420e60: 41 bc 20 00 00 00 mov $0x20,%r12d - 420e66: 74 10 je 420e78 <__posix_memalign+0xb8> - 420e68: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 420e6f: 00 - 420e70: 4d 01 e4 add %r12,%r12 - 420e73: 4c 39 e0 cmp %r12,%rax - 420e76: 77 f8 ja 420e70 <__posix_memalign+0xb0> - 420e78: 48 c7 c0 d8 ff ff ff mov $0xffffffffffffffd8,%rax - 420e7f: 64 4c 8b 28 mov %fs:(%rax),%r13 - 420e83: 4d 85 ed test %r13,%r13 - 420e86: 0f 84 03 01 00 00 je 420f8f <__posix_memalign+0x1cf> - 420e8c: 41 8b 45 04 mov 0x4(%r13),%eax - 420e90: 83 e0 04 and $0x4,%eax - 420e93: 0f 85 f6 00 00 00 jne 420f8f <__posix_memalign+0x1cf> - 420e99: be 01 00 00 00 mov $0x1,%esi - 420e9e: 83 3d 17 c3 2a 00 00 cmpl $0x0,0x2ac317(%rip) # 6cd1bc <__libc_multiple_threads> - 420ea5: 74 0a je 420eb1 <__posix_memalign+0xf1> - 420ea7: f0 41 0f b1 75 00 lock cmpxchg %esi,0x0(%r13) - 420ead: 75 09 jne 420eb8 <__posix_memalign+0xf8> - 420eaf: eb 1e jmp 420ecf <__posix_memalign+0x10f> - 420eb1: 41 0f b1 75 00 cmpxchg %esi,0x0(%r13) - 420eb6: 74 17 je 420ecf <__posix_memalign+0x10f> - 420eb8: 49 8d 7d 00 lea 0x0(%r13),%rdi - 420ebc: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 420ec3: e8 08 17 02 00 callq 4425d0 <__lll_lock_wait_private> - 420ec8: 48 81 c4 80 00 00 00 add $0x80,%rsp - 420ecf: 48 89 da mov %rbx,%rdx - 420ed2: 4c 89 e6 mov %r12,%rsi - 420ed5: 4c 89 ef mov %r13,%rdi - 420ed8: e8 33 b6 ff ff callq 41c510 <_int_memalign> - 420edd: 48 85 c0 test %rax,%rax - 420ee0: 48 89 c2 mov %rax,%rdx - 420ee3: 0f 84 f9 00 00 00 je 420fe2 <__posix_memalign+0x222> - 420ee9: 83 3d cc c2 2a 00 00 cmpl $0x0,0x2ac2cc(%rip) # 6cd1bc <__libc_multiple_threads> - 420ef0: 74 09 je 420efb <__posix_memalign+0x13b> - 420ef2: f0 41 ff 4d 00 lock decl 0x0(%r13) - 420ef7: 75 08 jne 420f01 <__posix_memalign+0x141> - 420ef9: eb 1d jmp 420f18 <__posix_memalign+0x158> - 420efb: 41 ff 4d 00 decl 0x0(%r13) - 420eff: 74 17 je 420f18 <__posix_memalign+0x158> - 420f01: 49 8d 7d 00 lea 0x0(%r13),%rdi - 420f05: 48 81 ec 80 00 00 00 sub $0x80,%rsp - 420f0c: e8 ef 16 02 00 callq 442600 <__lll_unlock_wake_private> - 420f11: 48 81 c4 80 00 00 00 add $0x80,%rsp - 420f18: 48 85 d2 test %rdx,%rdx - 420f1b: 74 56 je 420f73 <__posix_memalign+0x1b3> - 420f1d: 48 8b 42 f8 mov -0x8(%rdx),%rax - 420f21: a8 02 test $0x2,%al - 420f23: 75 1f jne 420f44 <__posix_memalign+0x184> - 420f25: a8 04 test $0x4,%al - 420f27: b9 00 a8 6c 00 mov $0x6ca800,%ecx - 420f2c: 74 0d je 420f3b <__posix_memalign+0x17b> - 420f2e: 48 8d 42 f0 lea -0x10(%rdx),%rax - 420f32: 48 25 00 00 00 fc and $0xfffffffffc000000,%rax - 420f38: 48 8b 08 mov (%rax),%rcx - 420f3b: 4c 39 e9 cmp %r13,%rcx - 420f3e: 0f 85 e6 00 00 00 jne 42102a <__posix_memalign+0x26a> - 420f44: 48 89 d0 mov %rdx,%rax - 420f47: 48 89 45 00 mov %rax,0x0(%rbp) - 420f4b: 31 c0 xor %eax,%eax - 420f4d: 48 83 c4 08 add $0x8,%rsp - 420f51: 5b pop %rbx - 420f52: 5d pop %rbp - 420f53: 41 5c pop %r12 - 420f55: 41 5d pop %r13 - 420f57: c3 retq - 420f58: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 420f5f: 00 - 420f60: b8 16 00 00 00 mov $0x16,%eax - 420f65: c3 retq - 420f66: 48 89 de mov %rbx,%rsi - 420f69: 48 89 c7 mov %rax,%rdi - 420f6c: ff d1 callq *%rcx - 420f6e: 48 85 c0 test %rax,%rax - 420f71: 75 d4 jne 420f47 <__posix_memalign+0x187> - 420f73: b8 0c 00 00 00 mov $0xc,%eax - 420f78: eb d3 jmp 420f4d <__posix_memalign+0x18d> - 420f7a: 48 83 fb bf cmp $0xffffffffffffffbf,%rbx - 420f7e: 0f 87 93 00 00 00 ja 421017 <__posix_memalign+0x257> - 420f84: 41 bc 20 00 00 00 mov $0x20,%r12d - 420f8a: e9 e9 fe ff ff jmpq 420e78 <__posix_memalign+0xb8> - 420f8f: e8 cc 61 ff ff callq 417160 - 420f94: 48 85 c0 test %rax,%rax - 420f97: 49 89 c5 mov %rax,%r13 - 420f9a: 0f 85 2f ff ff ff jne 420ecf <__posix_memalign+0x10f> - 420fa0: 49 8d 7c 1c 20 lea 0x20(%r12,%rbx,1),%rdi - 420fa5: 31 f6 xor %esi,%esi - 420fa7: e8 a4 64 ff ff callq 417450 - 420fac: 48 89 da mov %rbx,%rdx - 420faf: 4c 89 e6 mov %r12,%rsi - 420fb2: 48 89 c7 mov %rax,%rdi - 420fb5: 49 89 c5 mov %rax,%r13 - 420fb8: e8 53 b5 ff ff callq 41c510 <_int_memalign> - 420fbd: 48 85 c0 test %rax,%rax - 420fc0: 48 89 c2 mov %rax,%rdx - 420fc3: 75 05 jne 420fca <__posix_memalign+0x20a> - 420fc5: 4d 85 ed test %r13,%r13 - 420fc8: 75 18 jne 420fe2 <__posix_memalign+0x222> - 420fca: 4d 85 ed test %r13,%r13 - 420fcd: 0f 85 16 ff ff ff jne 420ee9 <__posix_memalign+0x129> - 420fd3: e9 40 ff ff ff jmpq 420f18 <__posix_memalign+0x158> - 420fd8: 48 89 df mov %rbx,%rdi - 420fdb: e8 30 ca ff ff callq 41da10 <__libc_malloc> - 420fe0: eb 8c jmp 420f6e <__posix_memalign+0x1ae> - 420fe2: 90 nop - 420fe3: 4c 89 ef mov %r13,%rdi - 420fe6: 48 89 de mov %rbx,%rsi - 420fe9: e8 02 6a ff ff callq 4179f0 - 420fee: 48 89 da mov %rbx,%rdx - 420ff1: 4c 89 e6 mov %r12,%rsi - 420ff4: 48 89 c7 mov %rax,%rdi - 420ff7: 49 89 c5 mov %rax,%r13 - 420ffa: e8 11 b5 ff ff callq 41c510 <_int_memalign> - 420fff: 48 89 c2 mov %rax,%rdx - 421002: eb c6 jmp 420fca <__posix_memalign+0x20a> - 421004: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 42100b: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) - 421012: e9 5c ff ff ff jmpq 420f73 <__posix_memalign+0x1b3> - 421017: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 42101e: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) - 421025: e9 49 ff ff ff jmpq 420f73 <__posix_memalign+0x1b3> - 42102a: b9 08 2e 4a 00 mov $0x4a2e08,%ecx - 42102f: ba 3c 0c 00 00 mov $0xc3c,%edx - 421034: be c8 1f 4a 00 mov $0x4a1fc8,%esi - 421039: bf 20 2a 4a 00 mov $0x4a2a20,%edi - 42103e: e8 dd 5d ff ff callq 416e20 <__malloc_assert> - 421043: 49 89 f4 mov %rsi,%r12 - 421046: e9 2d fe ff ff jmpq 420e78 <__posix_memalign+0xb8> - 42104b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - -0000000000421050 <__malloc_info>: - 421050: 85 ff test %edi,%edi - 421052: 74 0c je 421060 <__malloc_info+0x10> - 421054: b8 16 00 00 00 mov $0x16,%eax - 421059: c3 retq - 42105a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 421060: 48 89 f7 mov %rsi,%rdi - 421063: e9 c8 f8 ff ff jmpq 420930 <__malloc_info.part.7> - 421068: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 42106f: 00 - -0000000000421070 <__default_morecore>: - 421070: 48 83 ec 08 sub $0x8,%rsp - 421074: e8 77 ea 01 00 callq 43faf0 <__sbrk> - 421079: ba 00 00 00 00 mov $0x0,%edx - 42107e: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 421082: 48 0f 44 c2 cmove %rdx,%rax - 421086: 48 83 c4 08 add $0x8,%rsp - 42108a: c3 retq - 42108b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - -0000000000421090 : - 421090: 48 8d 05 19 00 00 00 lea 0x19(%rip),%rax # 4210b0 <__GI_strchr> - 421097: f7 05 1f b6 2a 00 04 testl $0x4,0x2ab61f(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> - 42109e: 00 00 00 - 4210a1: 74 07 je 4210aa - 4210a3: 48 8d 05 66 a9 01 00 lea 0x1a966(%rip),%rax # 43ba10 <__strchr_sse2_no_bsf> - 4210aa: c3 retq - 4210ab: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - -00000000004210b0 <__GI_strchr>: - 4210b0: 66 0f 6e ce movd %esi,%xmm1 - 4210b4: 89 f8 mov %edi,%eax - 4210b6: 25 ff 0f 00 00 and $0xfff,%eax - 4210bb: 66 0f 60 c9 punpcklbw %xmm1,%xmm1 - 4210bf: 3d c0 0f 00 00 cmp $0xfc0,%eax - 4210c4: 66 0f 61 c9 punpcklwd %xmm1,%xmm1 - 4210c8: 66 0f 70 c9 00 pshufd $0x0,%xmm1,%xmm1 - 4210cd: 0f 8f 5d 01 00 00 jg 421230 <__GI_strchr+0x180> - 4210d3: f3 0f 6f 07 movdqu (%rdi),%xmm0 - 4210d7: 66 0f ef db pxor %xmm3,%xmm3 - 4210db: 66 0f 6f e0 movdqa %xmm0,%xmm4 - 4210df: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4210e3: 66 0f 74 e3 pcmpeqb %xmm3,%xmm4 - 4210e7: 66 0f eb c4 por %xmm4,%xmm0 - 4210eb: 66 0f d7 c0 pmovmskb %xmm0,%eax - 4210ef: 85 c0 test %eax,%eax - 4210f1: 74 15 je 421108 <__GI_strchr+0x58> - 4210f3: 0f bc c0 bsf %eax,%eax - 4210f6: ba 00 00 00 00 mov $0x0,%edx - 4210fb: 48 8d 04 07 lea (%rdi,%rax,1),%rax - 4210ff: 40 38 30 cmp %sil,(%rax) - 421102: 48 0f 45 c2 cmovne %rdx,%rax - 421106: c3 retq - 421107: 90 nop - 421108: f3 0f 6f 47 10 movdqu 0x10(%rdi),%xmm0 - 42110d: 66 0f 6f e0 movdqa %xmm0,%xmm4 - 421111: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 421115: 66 0f 74 e3 pcmpeqb %xmm3,%xmm4 - 421119: 66 0f eb c4 por %xmm4,%xmm0 - 42111d: 66 0f d7 c8 pmovmskb %xmm0,%ecx - 421121: f3 0f 6f 47 20 movdqu 0x20(%rdi),%xmm0 - 421126: 66 0f 6f e0 movdqa %xmm0,%xmm4 - 42112a: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42112e: 48 c1 e1 10 shl $0x10,%rcx - 421132: 66 0f 74 e3 pcmpeqb %xmm3,%xmm4 - 421136: 66 0f eb c4 por %xmm4,%xmm0 - 42113a: 66 0f d7 c0 pmovmskb %xmm0,%eax - 42113e: f3 0f 6f 47 30 movdqu 0x30(%rdi),%xmm0 - 421143: 66 0f 74 d8 pcmpeqb %xmm0,%xmm3 - 421147: 48 c1 e0 20 shl $0x20,%rax - 42114b: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42114f: 48 09 c8 or %rcx,%rax - 421152: 66 0f eb c3 por %xmm3,%xmm0 - 421156: 66 0f d7 c8 pmovmskb %xmm0,%ecx - 42115a: 48 c1 e1 30 shl $0x30,%rcx - 42115e: 48 09 c8 or %rcx,%rax - 421161: 48 85 c0 test %rax,%rax - 421164: 0f 85 a6 00 00 00 jne 421210 <__GI_strchr+0x160> - 42116a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 421170: 66 0f ef f6 pxor %xmm6,%xmm6 - 421174: 48 83 e7 c0 and $0xffffffffffffffc0,%rdi - 421178: 48 83 c7 40 add $0x40,%rdi - 42117c: 66 0f 6f 2f movdqa (%rdi),%xmm5 - 421180: 66 0f 6f 57 10 movdqa 0x10(%rdi),%xmm2 - 421185: 66 0f 6f 5f 20 movdqa 0x20(%rdi),%xmm3 - 42118a: 66 0f ef e9 pxor %xmm1,%xmm5 - 42118e: 66 0f 6f 67 30 movdqa 0x30(%rdi),%xmm4 - 421193: 66 0f ef d1 pxor %xmm1,%xmm2 - 421197: 66 0f ef d9 pxor %xmm1,%xmm3 - 42119b: 66 0f da 2f pminub (%rdi),%xmm5 - 42119f: 66 0f ef e1 pxor %xmm1,%xmm4 - 4211a3: 66 0f da 57 10 pminub 0x10(%rdi),%xmm2 - 4211a8: 66 0f da 5f 20 pminub 0x20(%rdi),%xmm3 - 4211ad: 66 0f da ea pminub %xmm2,%xmm5 - 4211b1: 66 0f da 67 30 pminub 0x30(%rdi),%xmm4 - 4211b6: 66 0f da eb pminub %xmm3,%xmm5 - 4211ba: 66 0f da ec pminub %xmm4,%xmm5 - 4211be: 66 0f 74 ee pcmpeqb %xmm6,%xmm5 - 4211c2: 66 0f d7 c5 pmovmskb %xmm5,%eax - 4211c6: 85 c0 test %eax,%eax - 4211c8: 74 ae je 421178 <__GI_strchr+0xc8> - 4211ca: 66 0f 6f 2f movdqa (%rdi),%xmm5 - 4211ce: 66 0f 6f c5 movdqa %xmm5,%xmm0 - 4211d2: 66 0f 74 e9 pcmpeqb %xmm1,%xmm5 - 4211d6: 66 0f 74 c6 pcmpeqb %xmm6,%xmm0 - 4211da: 66 0f eb e8 por %xmm0,%xmm5 - 4211de: 66 0f 74 d6 pcmpeqb %xmm6,%xmm2 - 4211e2: 66 0f 74 de pcmpeqb %xmm6,%xmm3 - 4211e6: 66 0f 74 e6 pcmpeqb %xmm6,%xmm4 - 4211ea: 66 0f d7 cd pmovmskb %xmm5,%ecx - 4211ee: 66 0f d7 c2 pmovmskb %xmm2,%eax - 4211f2: 48 c1 e0 10 shl $0x10,%rax - 4211f6: 66 44 0f d7 c3 pmovmskb %xmm3,%r8d - 4211fb: 66 0f d7 d4 pmovmskb %xmm4,%edx - 4211ff: 49 c1 e0 20 shl $0x20,%r8 - 421203: 4c 09 c0 or %r8,%rax - 421206: 48 09 c8 or %rcx,%rax - 421209: 48 c1 e2 30 shl $0x30,%rdx - 42120d: 48 09 d0 or %rdx,%rax - 421210: 48 0f bc c0 bsf %rax,%rax - 421214: ba 00 00 00 00 mov $0x0,%edx - 421219: 48 8d 04 07 lea (%rdi,%rax,1),%rax - 42121d: 40 38 30 cmp %sil,(%rax) - 421220: 48 0f 45 c2 cmovne %rdx,%rax - 421224: c3 retq - 421225: 90 nop - 421226: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42122d: 00 00 00 - 421230: 48 89 fa mov %rdi,%rdx - 421233: 66 0f ef d2 pxor %xmm2,%xmm2 - 421237: 48 83 e2 c0 and $0xffffffffffffffc0,%rdx - 42123b: 66 0f 6f c1 movdqa %xmm1,%xmm0 - 42123f: 66 0f 6f 1a movdqa (%rdx),%xmm3 - 421243: 66 0f 6f e3 movdqa %xmm3,%xmm4 - 421247: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 - 42124b: 66 0f 74 e2 pcmpeqb %xmm2,%xmm4 - 42124f: 66 0f eb dc por %xmm4,%xmm3 - 421253: 66 44 0f d7 c3 pmovmskb %xmm3,%r8d - 421258: 66 0f 6f 5a 10 movdqa 0x10(%rdx),%xmm3 - 42125d: 66 0f 6f e3 movdqa %xmm3,%xmm4 - 421261: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 - 421265: 66 0f 74 e2 pcmpeqb %xmm2,%xmm4 - 421269: 66 0f eb dc por %xmm4,%xmm3 - 42126d: 66 0f d7 c3 pmovmskb %xmm3,%eax - 421271: 66 0f 6f 5a 20 movdqa 0x20(%rdx),%xmm3 - 421276: 66 0f 6f e3 movdqa %xmm3,%xmm4 - 42127a: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 - 42127e: 48 c1 e0 10 shl $0x10,%rax - 421282: 66 0f 74 e2 pcmpeqb %xmm2,%xmm4 - 421286: 66 0f eb dc por %xmm4,%xmm3 - 42128a: 66 44 0f d7 cb pmovmskb %xmm3,%r9d - 42128f: 66 0f 6f 5a 30 movdqa 0x30(%rdx),%xmm3 - 421294: 66 0f 74 d3 pcmpeqb %xmm3,%xmm2 - 421298: 49 c1 e1 20 shl $0x20,%r9 - 42129c: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 4212a0: 4c 09 c8 or %r9,%rax - 4212a3: 4c 09 c0 or %r8,%rax - 4212a6: 66 0f eb c2 por %xmm2,%xmm0 - 4212aa: 66 0f d7 c8 pmovmskb %xmm0,%ecx - 4212ae: 48 c1 e1 30 shl $0x30,%rcx - 4212b2: 48 09 c8 or %rcx,%rax - 4212b5: 89 f9 mov %edi,%ecx - 4212b7: 28 d1 sub %dl,%cl - 4212b9: 48 d3 e8 shr %cl,%rax - 4212bc: 48 85 c0 test %rax,%rax - 4212bf: 0f 85 4b ff ff ff jne 421210 <__GI_strchr+0x160> - 4212c5: e9 a0 fe ff ff jmpq 42116a <__GI_strchr+0xba> - 4212ca: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - -00000000004212d0 : - 4212d0: 48 8d 05 79 cd 00 00 lea 0xcd79(%rip),%rax # 42e050 <__strcmp_sse2_unaligned> - 4212d7: f7 05 df b3 2a 00 10 testl $0x10,0x2ab3df(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> - 4212de: 00 00 00 - 4212e1: 75 1a jne 4212fd - 4212e3: 48 8d 05 06 bb 00 00 lea 0xbb06(%rip),%rax # 42cdf0 <__strcmp_ssse3> - 4212ea: f7 05 9c b3 2a 00 00 testl $0x200,0x2ab39c(%rip) # 6cc690 <_dl_x86_cpu_features+0x10> - 4212f1: 02 00 00 - 4212f4: 75 07 jne 4212fd - 4212f6: 48 8d 05 03 00 00 00 lea 0x3(%rip),%rax # 421300 <__GI_strcmp> - 4212fd: c3 retq - 4212fe: 66 90 xchg %ax,%ax - -0000000000421300 <__GI_strcmp>: - 421300: 89 f1 mov %esi,%ecx - 421302: 89 f8 mov %edi,%eax - 421304: 48 83 e1 3f and $0x3f,%rcx - 421308: 48 83 e0 3f and $0x3f,%rax - 42130c: 83 f9 30 cmp $0x30,%ecx - 42130f: 77 3f ja 421350 <__GI_strcmp+0x50> - 421311: 83 f8 30 cmp $0x30,%eax - 421314: 77 3a ja 421350 <__GI_strcmp+0x50> - 421316: 66 0f 12 0f movlpd (%rdi),%xmm1 - 42131a: 66 0f 12 16 movlpd (%rsi),%xmm2 - 42131e: 66 0f 16 4f 08 movhpd 0x8(%rdi),%xmm1 - 421323: 66 0f 16 56 08 movhpd 0x8(%rsi),%xmm2 - 421328: 66 0f ef c0 pxor %xmm0,%xmm0 - 42132c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 421330: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 421334: 66 0f f8 c8 psubb %xmm0,%xmm1 - 421338: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42133c: 81 ea ff ff 00 00 sub $0xffff,%edx - 421342: 0f 85 c8 13 00 00 jne 422710 <__GI_strcmp+0x1410> - 421348: 48 83 c6 10 add $0x10,%rsi - 42134c: 48 83 c7 10 add $0x10,%rdi - 421350: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi - 421354: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi - 421358: ba ff ff 00 00 mov $0xffff,%edx - 42135d: 45 31 c0 xor %r8d,%r8d - 421360: 83 e1 0f and $0xf,%ecx - 421363: 83 e0 0f and $0xf,%eax - 421366: 39 c1 cmp %eax,%ecx - 421368: 74 26 je 421390 <__GI_strcmp+0x90> - 42136a: 77 07 ja 421373 <__GI_strcmp+0x73> - 42136c: 41 89 d0 mov %edx,%r8d - 42136f: 91 xchg %eax,%ecx - 421370: 48 87 f7 xchg %rsi,%rdi - 421373: 4c 8d 48 0f lea 0xf(%rax),%r9 - 421377: 49 29 c9 sub %rcx,%r9 - 42137a: 4c 8d 15 af 1c 08 00 lea 0x81caf(%rip),%r10 # 4a3030 <__func__.10972+0x70> - 421381: 4f 63 0c 8a movslq (%r10,%r9,4),%r9 - 421385: 4f 8d 14 0a lea (%r10,%r9,1),%r10 - 421389: 41 ff e2 jmpq *%r10 - 42138c: 0f 1f 40 00 nopl 0x0(%rax) - 421390: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 421394: 66 0f ef c0 pxor %xmm0,%xmm0 - 421398: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42139c: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 - 4213a0: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4213a4: 66 44 0f d7 c9 pmovmskb %xmm1,%r9d - 4213a9: d3 ea shr %cl,%edx - 4213ab: 41 d3 e9 shr %cl,%r9d - 4213ae: 44 29 ca sub %r9d,%edx - 4213b1: 0f 85 3e 13 00 00 jne 4226f5 <__GI_strcmp+0x13f5> - 4213b7: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 4213be: 49 c7 c1 10 00 00 00 mov $0x10,%r9 - 4213c5: 66 0f ef c0 pxor %xmm0,%xmm0 - 4213c9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4213d0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4213d5: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4213da: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4213de: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 4213e2: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4213e6: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4213ea: 81 ea ff ff 00 00 sub $0xffff,%edx - 4213f0: 0f 85 fa 12 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 4213f6: 48 83 c1 10 add $0x10,%rcx - 4213fa: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4213ff: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 421404: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 421408: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42140c: 66 0f f8 c8 psubb %xmm0,%xmm1 - 421410: 66 0f d7 d1 pmovmskb %xmm1,%edx - 421414: 81 ea ff ff 00 00 sub $0xffff,%edx - 42141a: 0f 85 d0 12 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 421420: 48 83 c1 10 add $0x10,%rcx - 421424: eb aa jmp 4213d0 <__GI_strcmp+0xd0> - 421426: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42142d: 00 00 00 - 421430: 66 0f ef c0 pxor %xmm0,%xmm0 - 421434: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 421438: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42143c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 421440: 66 0f 73 fa 0f pslldq $0xf,%xmm2 - 421445: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 421449: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42144d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 421452: d3 ea shr %cl,%edx - 421454: 41 d3 e9 shr %cl,%r9d - 421457: 44 29 ca sub %r9d,%edx - 42145a: 0f 85 95 12 00 00 jne 4226f5 <__GI_strcmp+0x13f5> - 421460: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 421464: 66 0f ef c0 pxor %xmm0,%xmm0 - 421468: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42146f: 41 b9 01 00 00 00 mov $0x1,%r9d - 421475: 4c 8d 57 01 lea 0x1(%rdi),%r10 - 421479: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 421480: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 421487: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 42148e: 00 00 - 421490: 49 83 c2 10 add $0x10,%r10 - 421494: 0f 8f 96 00 00 00 jg 421530 <__GI_strcmp+0x230> - 42149a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42149f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4214a4: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 4214a8: 66 0f 73 db 01 psrldq $0x1,%xmm3 - 4214ad: 66 0f 73 fa 0f pslldq $0xf,%xmm2 - 4214b2: 66 0f eb d3 por %xmm3,%xmm2 - 4214b6: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4214ba: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 4214be: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4214c2: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4214c6: 81 ea ff ff 00 00 sub $0xffff,%edx - 4214cc: 0f 85 1e 12 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 4214d2: 48 83 c1 10 add $0x10,%rcx - 4214d6: 66 0f 6f dc movdqa %xmm4,%xmm3 - 4214da: 49 83 c2 10 add $0x10,%r10 - 4214de: 7f 50 jg 421530 <__GI_strcmp+0x230> - 4214e0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4214e5: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4214ea: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 4214ee: 66 0f 73 db 01 psrldq $0x1,%xmm3 - 4214f3: 66 0f 73 fa 0f pslldq $0xf,%xmm2 - 4214f8: 66 0f eb d3 por %xmm3,%xmm2 - 4214fc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 421500: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 421504: 66 0f f8 c8 psubb %xmm0,%xmm1 - 421508: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42150c: 81 ea ff ff 00 00 sub $0xffff,%edx - 421512: 0f 85 d8 11 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 421518: 48 83 c1 10 add $0x10,%rcx - 42151c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 421520: e9 6b ff ff ff jmpq 421490 <__GI_strcmp+0x190> - 421525: 90 nop - 421526: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42152d: 00 00 00 - 421530: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 421534: 66 0f d7 d0 pmovmskb %xmm0,%edx - 421538: f7 c2 fe ff 00 00 test $0xfffe,%edx - 42153e: 75 10 jne 421550 <__GI_strcmp+0x250> - 421540: 66 0f ef c0 pxor %xmm0,%xmm0 - 421544: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42154b: e9 4a ff ff ff jmpq 42149a <__GI_strcmp+0x19a> - 421550: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 421555: 66 0f 73 d8 01 psrldq $0x1,%xmm0 - 42155a: 66 0f 73 db 01 psrldq $0x1,%xmm3 - 42155f: e9 7c 11 00 00 jmpq 4226e0 <__GI_strcmp+0x13e0> - 421564: 66 90 xchg %ax,%ax - 421566: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42156d: 00 00 00 - 421570: 66 0f ef c0 pxor %xmm0,%xmm0 - 421574: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 421578: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42157c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 421580: 66 0f 73 fa 0e pslldq $0xe,%xmm2 - 421585: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 421589: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42158d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 421592: d3 ea shr %cl,%edx - 421594: 41 d3 e9 shr %cl,%r9d - 421597: 44 29 ca sub %r9d,%edx - 42159a: 0f 85 55 11 00 00 jne 4226f5 <__GI_strcmp+0x13f5> - 4215a0: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 4215a4: 66 0f ef c0 pxor %xmm0,%xmm0 - 4215a8: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 4215af: 41 b9 02 00 00 00 mov $0x2,%r9d - 4215b5: 4c 8d 57 02 lea 0x2(%rdi),%r10 - 4215b9: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 4215c0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 4215c7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 4215ce: 00 00 - 4215d0: 49 83 c2 10 add $0x10,%r10 - 4215d4: 0f 8f 96 00 00 00 jg 421670 <__GI_strcmp+0x370> - 4215da: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4215df: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4215e4: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 4215e8: 66 0f 73 db 02 psrldq $0x2,%xmm3 - 4215ed: 66 0f 73 fa 0e pslldq $0xe,%xmm2 - 4215f2: 66 0f eb d3 por %xmm3,%xmm2 - 4215f6: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4215fa: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 4215fe: 66 0f f8 c8 psubb %xmm0,%xmm1 - 421602: 66 0f d7 d1 pmovmskb %xmm1,%edx - 421606: 81 ea ff ff 00 00 sub $0xffff,%edx - 42160c: 0f 85 de 10 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 421612: 48 83 c1 10 add $0x10,%rcx - 421616: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42161a: 49 83 c2 10 add $0x10,%r10 - 42161e: 7f 50 jg 421670 <__GI_strcmp+0x370> - 421620: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 421625: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42162a: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42162e: 66 0f 73 db 02 psrldq $0x2,%xmm3 - 421633: 66 0f 73 fa 0e pslldq $0xe,%xmm2 - 421638: 66 0f eb d3 por %xmm3,%xmm2 - 42163c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 421640: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 421644: 66 0f f8 c8 psubb %xmm0,%xmm1 - 421648: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42164c: 81 ea ff ff 00 00 sub $0xffff,%edx - 421652: 0f 85 98 10 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 421658: 48 83 c1 10 add $0x10,%rcx - 42165c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 421660: e9 6b ff ff ff jmpq 4215d0 <__GI_strcmp+0x2d0> - 421665: 90 nop - 421666: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42166d: 00 00 00 - 421670: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 421674: 66 0f d7 d0 pmovmskb %xmm0,%edx - 421678: f7 c2 fc ff 00 00 test $0xfffc,%edx - 42167e: 75 10 jne 421690 <__GI_strcmp+0x390> - 421680: 66 0f ef c0 pxor %xmm0,%xmm0 - 421684: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42168b: e9 4a ff ff ff jmpq 4215da <__GI_strcmp+0x2da> - 421690: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 421695: 66 0f 73 d8 02 psrldq $0x2,%xmm0 - 42169a: 66 0f 73 db 02 psrldq $0x2,%xmm3 - 42169f: e9 3c 10 00 00 jmpq 4226e0 <__GI_strcmp+0x13e0> - 4216a4: 66 90 xchg %ax,%ax - 4216a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4216ad: 00 00 00 - 4216b0: 66 0f ef c0 pxor %xmm0,%xmm0 - 4216b4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 4216b8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 4216bc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4216c0: 66 0f 73 fa 0d pslldq $0xd,%xmm2 - 4216c5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 4216c9: 66 0f f8 d0 psubb %xmm0,%xmm2 - 4216cd: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 4216d2: d3 ea shr %cl,%edx - 4216d4: 41 d3 e9 shr %cl,%r9d - 4216d7: 44 29 ca sub %r9d,%edx - 4216da: 0f 85 15 10 00 00 jne 4226f5 <__GI_strcmp+0x13f5> - 4216e0: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 4216e4: 66 0f ef c0 pxor %xmm0,%xmm0 - 4216e8: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 4216ef: 41 b9 03 00 00 00 mov $0x3,%r9d - 4216f5: 4c 8d 57 03 lea 0x3(%rdi),%r10 - 4216f9: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 421700: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 421707: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 42170e: 00 00 - 421710: 49 83 c2 10 add $0x10,%r10 - 421714: 0f 8f 96 00 00 00 jg 4217b0 <__GI_strcmp+0x4b0> - 42171a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42171f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 421724: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 421728: 66 0f 73 db 03 psrldq $0x3,%xmm3 - 42172d: 66 0f 73 fa 0d pslldq $0xd,%xmm2 - 421732: 66 0f eb d3 por %xmm3,%xmm2 - 421736: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42173a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42173e: 66 0f f8 c8 psubb %xmm0,%xmm1 - 421742: 66 0f d7 d1 pmovmskb %xmm1,%edx - 421746: 81 ea ff ff 00 00 sub $0xffff,%edx - 42174c: 0f 85 9e 0f 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 421752: 48 83 c1 10 add $0x10,%rcx - 421756: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42175a: 49 83 c2 10 add $0x10,%r10 - 42175e: 7f 50 jg 4217b0 <__GI_strcmp+0x4b0> - 421760: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 421765: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42176a: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42176e: 66 0f 73 db 03 psrldq $0x3,%xmm3 - 421773: 66 0f 73 fa 0d pslldq $0xd,%xmm2 - 421778: 66 0f eb d3 por %xmm3,%xmm2 - 42177c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 421780: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 421784: 66 0f f8 c8 psubb %xmm0,%xmm1 - 421788: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42178c: 81 ea ff ff 00 00 sub $0xffff,%edx - 421792: 0f 85 58 0f 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 421798: 48 83 c1 10 add $0x10,%rcx - 42179c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 4217a0: e9 6b ff ff ff jmpq 421710 <__GI_strcmp+0x410> - 4217a5: 90 nop - 4217a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4217ad: 00 00 00 - 4217b0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 4217b4: 66 0f d7 d0 pmovmskb %xmm0,%edx - 4217b8: f7 c2 f8 ff 00 00 test $0xfff8,%edx - 4217be: 75 10 jne 4217d0 <__GI_strcmp+0x4d0> - 4217c0: 66 0f ef c0 pxor %xmm0,%xmm0 - 4217c4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 4217cb: e9 4a ff ff ff jmpq 42171a <__GI_strcmp+0x41a> - 4217d0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4217d5: 66 0f 73 d8 03 psrldq $0x3,%xmm0 - 4217da: 66 0f 73 db 03 psrldq $0x3,%xmm3 - 4217df: e9 fc 0e 00 00 jmpq 4226e0 <__GI_strcmp+0x13e0> - 4217e4: 66 90 xchg %ax,%ax - 4217e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4217ed: 00 00 00 - 4217f0: 66 0f ef c0 pxor %xmm0,%xmm0 - 4217f4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 4217f8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 4217fc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 421800: 66 0f 73 fa 0c pslldq $0xc,%xmm2 - 421805: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 421809: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42180d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 421812: d3 ea shr %cl,%edx - 421814: 41 d3 e9 shr %cl,%r9d - 421817: 44 29 ca sub %r9d,%edx - 42181a: 0f 85 d5 0e 00 00 jne 4226f5 <__GI_strcmp+0x13f5> - 421820: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 421824: 66 0f ef c0 pxor %xmm0,%xmm0 - 421828: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42182f: 41 b9 04 00 00 00 mov $0x4,%r9d - 421835: 4c 8d 57 04 lea 0x4(%rdi),%r10 - 421839: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 421840: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 421847: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 42184e: 00 00 - 421850: 49 83 c2 10 add $0x10,%r10 - 421854: 0f 8f 96 00 00 00 jg 4218f0 <__GI_strcmp+0x5f0> - 42185a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42185f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 421864: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 421868: 66 0f 73 db 04 psrldq $0x4,%xmm3 - 42186d: 66 0f 73 fa 0c pslldq $0xc,%xmm2 - 421872: 66 0f eb d3 por %xmm3,%xmm2 - 421876: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42187a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42187e: 66 0f f8 c8 psubb %xmm0,%xmm1 - 421882: 66 0f d7 d1 pmovmskb %xmm1,%edx - 421886: 81 ea ff ff 00 00 sub $0xffff,%edx - 42188c: 0f 85 5e 0e 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 421892: 48 83 c1 10 add $0x10,%rcx - 421896: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42189a: 49 83 c2 10 add $0x10,%r10 - 42189e: 7f 50 jg 4218f0 <__GI_strcmp+0x5f0> - 4218a0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4218a5: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4218aa: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 4218ae: 66 0f 73 db 04 psrldq $0x4,%xmm3 - 4218b3: 66 0f 73 fa 0c pslldq $0xc,%xmm2 - 4218b8: 66 0f eb d3 por %xmm3,%xmm2 - 4218bc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4218c0: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 4218c4: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4218c8: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4218cc: 81 ea ff ff 00 00 sub $0xffff,%edx - 4218d2: 0f 85 18 0e 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 4218d8: 48 83 c1 10 add $0x10,%rcx - 4218dc: 66 0f 6f dc movdqa %xmm4,%xmm3 - 4218e0: e9 6b ff ff ff jmpq 421850 <__GI_strcmp+0x550> - 4218e5: 90 nop - 4218e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4218ed: 00 00 00 - 4218f0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 4218f4: 66 0f d7 d0 pmovmskb %xmm0,%edx - 4218f8: f7 c2 f0 ff 00 00 test $0xfff0,%edx - 4218fe: 75 10 jne 421910 <__GI_strcmp+0x610> - 421900: 66 0f ef c0 pxor %xmm0,%xmm0 - 421904: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42190b: e9 4a ff ff ff jmpq 42185a <__GI_strcmp+0x55a> - 421910: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 421915: 66 0f 73 d8 04 psrldq $0x4,%xmm0 - 42191a: 66 0f 73 db 04 psrldq $0x4,%xmm3 - 42191f: e9 bc 0d 00 00 jmpq 4226e0 <__GI_strcmp+0x13e0> - 421924: 66 90 xchg %ax,%ax - 421926: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42192d: 00 00 00 - 421930: 66 0f ef c0 pxor %xmm0,%xmm0 - 421934: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 421938: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42193c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 421940: 66 0f 73 fa 0b pslldq $0xb,%xmm2 - 421945: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 421949: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42194d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 421952: d3 ea shr %cl,%edx - 421954: 41 d3 e9 shr %cl,%r9d - 421957: 44 29 ca sub %r9d,%edx - 42195a: 0f 85 95 0d 00 00 jne 4226f5 <__GI_strcmp+0x13f5> - 421960: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 421964: 66 0f ef c0 pxor %xmm0,%xmm0 - 421968: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42196f: 41 b9 05 00 00 00 mov $0x5,%r9d - 421975: 4c 8d 57 05 lea 0x5(%rdi),%r10 - 421979: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 421980: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 421987: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 42198e: 00 00 - 421990: 49 83 c2 10 add $0x10,%r10 - 421994: 0f 8f 96 00 00 00 jg 421a30 <__GI_strcmp+0x730> - 42199a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42199f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4219a4: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 4219a8: 66 0f 73 db 05 psrldq $0x5,%xmm3 - 4219ad: 66 0f 73 fa 0b pslldq $0xb,%xmm2 - 4219b2: 66 0f eb d3 por %xmm3,%xmm2 - 4219b6: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4219ba: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 4219be: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4219c2: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4219c6: 81 ea ff ff 00 00 sub $0xffff,%edx - 4219cc: 0f 85 1e 0d 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 4219d2: 48 83 c1 10 add $0x10,%rcx - 4219d6: 66 0f 6f dc movdqa %xmm4,%xmm3 - 4219da: 49 83 c2 10 add $0x10,%r10 - 4219de: 7f 50 jg 421a30 <__GI_strcmp+0x730> - 4219e0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4219e5: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4219ea: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 4219ee: 66 0f 73 db 05 psrldq $0x5,%xmm3 - 4219f3: 66 0f 73 fa 0b pslldq $0xb,%xmm2 - 4219f8: 66 0f eb d3 por %xmm3,%xmm2 - 4219fc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 421a00: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 421a04: 66 0f f8 c8 psubb %xmm0,%xmm1 - 421a08: 66 0f d7 d1 pmovmskb %xmm1,%edx - 421a0c: 81 ea ff ff 00 00 sub $0xffff,%edx - 421a12: 0f 85 d8 0c 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 421a18: 48 83 c1 10 add $0x10,%rcx - 421a1c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 421a20: e9 6b ff ff ff jmpq 421990 <__GI_strcmp+0x690> - 421a25: 90 nop - 421a26: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 421a2d: 00 00 00 - 421a30: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 421a34: 66 0f d7 d0 pmovmskb %xmm0,%edx - 421a38: f7 c2 e0 ff 00 00 test $0xffe0,%edx - 421a3e: 75 10 jne 421a50 <__GI_strcmp+0x750> - 421a40: 66 0f ef c0 pxor %xmm0,%xmm0 - 421a44: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 421a4b: e9 4a ff ff ff jmpq 42199a <__GI_strcmp+0x69a> - 421a50: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 421a55: 66 0f 73 d8 05 psrldq $0x5,%xmm0 - 421a5a: 66 0f 73 db 05 psrldq $0x5,%xmm3 - 421a5f: e9 7c 0c 00 00 jmpq 4226e0 <__GI_strcmp+0x13e0> - 421a64: 66 90 xchg %ax,%ax - 421a66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 421a6d: 00 00 00 - 421a70: 66 0f ef c0 pxor %xmm0,%xmm0 - 421a74: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 421a78: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 421a7c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 421a80: 66 0f 73 fa 0a pslldq $0xa,%xmm2 - 421a85: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 421a89: 66 0f f8 d0 psubb %xmm0,%xmm2 - 421a8d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 421a92: d3 ea shr %cl,%edx - 421a94: 41 d3 e9 shr %cl,%r9d - 421a97: 44 29 ca sub %r9d,%edx - 421a9a: 0f 85 55 0c 00 00 jne 4226f5 <__GI_strcmp+0x13f5> - 421aa0: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 421aa4: 66 0f ef c0 pxor %xmm0,%xmm0 - 421aa8: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 421aaf: 41 b9 06 00 00 00 mov $0x6,%r9d - 421ab5: 4c 8d 57 06 lea 0x6(%rdi),%r10 - 421ab9: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 421ac0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 421ac7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 421ace: 00 00 - 421ad0: 49 83 c2 10 add $0x10,%r10 - 421ad4: 0f 8f 96 00 00 00 jg 421b70 <__GI_strcmp+0x870> - 421ada: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 421adf: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 421ae4: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 421ae8: 66 0f 73 db 06 psrldq $0x6,%xmm3 - 421aed: 66 0f 73 fa 0a pslldq $0xa,%xmm2 - 421af2: 66 0f eb d3 por %xmm3,%xmm2 - 421af6: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 421afa: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 421afe: 66 0f f8 c8 psubb %xmm0,%xmm1 - 421b02: 66 0f d7 d1 pmovmskb %xmm1,%edx - 421b06: 81 ea ff ff 00 00 sub $0xffff,%edx - 421b0c: 0f 85 de 0b 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 421b12: 48 83 c1 10 add $0x10,%rcx - 421b16: 66 0f 6f dc movdqa %xmm4,%xmm3 - 421b1a: 49 83 c2 10 add $0x10,%r10 - 421b1e: 7f 50 jg 421b70 <__GI_strcmp+0x870> - 421b20: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 421b25: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 421b2a: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 421b2e: 66 0f 73 db 06 psrldq $0x6,%xmm3 - 421b33: 66 0f 73 fa 0a pslldq $0xa,%xmm2 - 421b38: 66 0f eb d3 por %xmm3,%xmm2 - 421b3c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 421b40: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 421b44: 66 0f f8 c8 psubb %xmm0,%xmm1 - 421b48: 66 0f d7 d1 pmovmskb %xmm1,%edx - 421b4c: 81 ea ff ff 00 00 sub $0xffff,%edx - 421b52: 0f 85 98 0b 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 421b58: 48 83 c1 10 add $0x10,%rcx - 421b5c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 421b60: e9 6b ff ff ff jmpq 421ad0 <__GI_strcmp+0x7d0> - 421b65: 90 nop - 421b66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 421b6d: 00 00 00 - 421b70: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 421b74: 66 0f d7 d0 pmovmskb %xmm0,%edx - 421b78: f7 c2 c0 ff 00 00 test $0xffc0,%edx - 421b7e: 75 10 jne 421b90 <__GI_strcmp+0x890> - 421b80: 66 0f ef c0 pxor %xmm0,%xmm0 - 421b84: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 421b8b: e9 4a ff ff ff jmpq 421ada <__GI_strcmp+0x7da> - 421b90: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 421b95: 66 0f 73 d8 06 psrldq $0x6,%xmm0 - 421b9a: 66 0f 73 db 06 psrldq $0x6,%xmm3 - 421b9f: e9 3c 0b 00 00 jmpq 4226e0 <__GI_strcmp+0x13e0> - 421ba4: 66 90 xchg %ax,%ax - 421ba6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 421bad: 00 00 00 - 421bb0: 66 0f ef c0 pxor %xmm0,%xmm0 - 421bb4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 421bb8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 421bbc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 421bc0: 66 0f 73 fa 09 pslldq $0x9,%xmm2 - 421bc5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 421bc9: 66 0f f8 d0 psubb %xmm0,%xmm2 - 421bcd: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 421bd2: d3 ea shr %cl,%edx - 421bd4: 41 d3 e9 shr %cl,%r9d - 421bd7: 44 29 ca sub %r9d,%edx - 421bda: 0f 85 15 0b 00 00 jne 4226f5 <__GI_strcmp+0x13f5> - 421be0: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 421be4: 66 0f ef c0 pxor %xmm0,%xmm0 - 421be8: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 421bef: 41 b9 07 00 00 00 mov $0x7,%r9d - 421bf5: 4c 8d 57 07 lea 0x7(%rdi),%r10 - 421bf9: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 421c00: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 421c07: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 421c0e: 00 00 - 421c10: 49 83 c2 10 add $0x10,%r10 - 421c14: 0f 8f 96 00 00 00 jg 421cb0 <__GI_strcmp+0x9b0> - 421c1a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 421c1f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 421c24: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 421c28: 66 0f 73 db 07 psrldq $0x7,%xmm3 - 421c2d: 66 0f 73 fa 09 pslldq $0x9,%xmm2 - 421c32: 66 0f eb d3 por %xmm3,%xmm2 - 421c36: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 421c3a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 421c3e: 66 0f f8 c8 psubb %xmm0,%xmm1 - 421c42: 66 0f d7 d1 pmovmskb %xmm1,%edx - 421c46: 81 ea ff ff 00 00 sub $0xffff,%edx - 421c4c: 0f 85 9e 0a 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 421c52: 48 83 c1 10 add $0x10,%rcx - 421c56: 66 0f 6f dc movdqa %xmm4,%xmm3 - 421c5a: 49 83 c2 10 add $0x10,%r10 - 421c5e: 7f 50 jg 421cb0 <__GI_strcmp+0x9b0> - 421c60: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 421c65: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 421c6a: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 421c6e: 66 0f 73 db 07 psrldq $0x7,%xmm3 - 421c73: 66 0f 73 fa 09 pslldq $0x9,%xmm2 - 421c78: 66 0f eb d3 por %xmm3,%xmm2 - 421c7c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 421c80: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 421c84: 66 0f f8 c8 psubb %xmm0,%xmm1 - 421c88: 66 0f d7 d1 pmovmskb %xmm1,%edx - 421c8c: 81 ea ff ff 00 00 sub $0xffff,%edx - 421c92: 0f 85 58 0a 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 421c98: 48 83 c1 10 add $0x10,%rcx - 421c9c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 421ca0: e9 6b ff ff ff jmpq 421c10 <__GI_strcmp+0x910> - 421ca5: 90 nop - 421ca6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 421cad: 00 00 00 - 421cb0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 421cb4: 66 0f d7 d0 pmovmskb %xmm0,%edx - 421cb8: f7 c2 80 ff 00 00 test $0xff80,%edx - 421cbe: 75 10 jne 421cd0 <__GI_strcmp+0x9d0> - 421cc0: 66 0f ef c0 pxor %xmm0,%xmm0 - 421cc4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 421ccb: e9 4a ff ff ff jmpq 421c1a <__GI_strcmp+0x91a> - 421cd0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 421cd5: 66 0f 73 d8 07 psrldq $0x7,%xmm0 - 421cda: 66 0f 73 db 07 psrldq $0x7,%xmm3 - 421cdf: e9 fc 09 00 00 jmpq 4226e0 <__GI_strcmp+0x13e0> - 421ce4: 66 90 xchg %ax,%ax - 421ce6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 421ced: 00 00 00 - 421cf0: 66 0f ef c0 pxor %xmm0,%xmm0 - 421cf4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 421cf8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 421cfc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 421d00: 66 0f 73 fa 08 pslldq $0x8,%xmm2 - 421d05: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 421d09: 66 0f f8 d0 psubb %xmm0,%xmm2 - 421d0d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 421d12: d3 ea shr %cl,%edx - 421d14: 41 d3 e9 shr %cl,%r9d - 421d17: 44 29 ca sub %r9d,%edx - 421d1a: 0f 85 d5 09 00 00 jne 4226f5 <__GI_strcmp+0x13f5> - 421d20: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 421d24: 66 0f ef c0 pxor %xmm0,%xmm0 - 421d28: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 421d2f: 41 b9 08 00 00 00 mov $0x8,%r9d - 421d35: 4c 8d 57 08 lea 0x8(%rdi),%r10 - 421d39: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 421d40: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 421d47: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 421d4e: 00 00 - 421d50: 49 83 c2 10 add $0x10,%r10 - 421d54: 0f 8f 96 00 00 00 jg 421df0 <__GI_strcmp+0xaf0> - 421d5a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 421d5f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 421d64: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 421d68: 66 0f 73 db 08 psrldq $0x8,%xmm3 - 421d6d: 66 0f 73 fa 08 pslldq $0x8,%xmm2 - 421d72: 66 0f eb d3 por %xmm3,%xmm2 - 421d76: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 421d7a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 421d7e: 66 0f f8 c8 psubb %xmm0,%xmm1 - 421d82: 66 0f d7 d1 pmovmskb %xmm1,%edx - 421d86: 81 ea ff ff 00 00 sub $0xffff,%edx - 421d8c: 0f 85 5e 09 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 421d92: 48 83 c1 10 add $0x10,%rcx - 421d96: 66 0f 6f dc movdqa %xmm4,%xmm3 - 421d9a: 49 83 c2 10 add $0x10,%r10 - 421d9e: 7f 50 jg 421df0 <__GI_strcmp+0xaf0> - 421da0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 421da5: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 421daa: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 421dae: 66 0f 73 db 08 psrldq $0x8,%xmm3 - 421db3: 66 0f 73 fa 08 pslldq $0x8,%xmm2 - 421db8: 66 0f eb d3 por %xmm3,%xmm2 - 421dbc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 421dc0: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 421dc4: 66 0f f8 c8 psubb %xmm0,%xmm1 - 421dc8: 66 0f d7 d1 pmovmskb %xmm1,%edx - 421dcc: 81 ea ff ff 00 00 sub $0xffff,%edx - 421dd2: 0f 85 18 09 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 421dd8: 48 83 c1 10 add $0x10,%rcx - 421ddc: 66 0f 6f dc movdqa %xmm4,%xmm3 - 421de0: e9 6b ff ff ff jmpq 421d50 <__GI_strcmp+0xa50> - 421de5: 90 nop - 421de6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 421ded: 00 00 00 - 421df0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 421df4: 66 0f d7 d0 pmovmskb %xmm0,%edx - 421df8: f7 c2 00 ff 00 00 test $0xff00,%edx - 421dfe: 75 10 jne 421e10 <__GI_strcmp+0xb10> - 421e00: 66 0f ef c0 pxor %xmm0,%xmm0 - 421e04: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 421e0b: e9 4a ff ff ff jmpq 421d5a <__GI_strcmp+0xa5a> - 421e10: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 421e15: 66 0f 73 d8 08 psrldq $0x8,%xmm0 - 421e1a: 66 0f 73 db 08 psrldq $0x8,%xmm3 - 421e1f: e9 bc 08 00 00 jmpq 4226e0 <__GI_strcmp+0x13e0> - 421e24: 66 90 xchg %ax,%ax - 421e26: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 421e2d: 00 00 00 - 421e30: 66 0f ef c0 pxor %xmm0,%xmm0 - 421e34: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 421e38: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 421e3c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 421e40: 66 0f 73 fa 07 pslldq $0x7,%xmm2 - 421e45: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 421e49: 66 0f f8 d0 psubb %xmm0,%xmm2 - 421e4d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 421e52: d3 ea shr %cl,%edx - 421e54: 41 d3 e9 shr %cl,%r9d - 421e57: 44 29 ca sub %r9d,%edx - 421e5a: 0f 85 95 08 00 00 jne 4226f5 <__GI_strcmp+0x13f5> - 421e60: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 421e64: 66 0f ef c0 pxor %xmm0,%xmm0 - 421e68: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 421e6f: 41 b9 09 00 00 00 mov $0x9,%r9d - 421e75: 4c 8d 57 09 lea 0x9(%rdi),%r10 - 421e79: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 421e80: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 421e87: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 421e8e: 00 00 - 421e90: 49 83 c2 10 add $0x10,%r10 - 421e94: 0f 8f 96 00 00 00 jg 421f30 <__GI_strcmp+0xc30> - 421e9a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 421e9f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 421ea4: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 421ea8: 66 0f 73 db 09 psrldq $0x9,%xmm3 - 421ead: 66 0f 73 fa 07 pslldq $0x7,%xmm2 - 421eb2: 66 0f eb d3 por %xmm3,%xmm2 - 421eb6: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 421eba: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 421ebe: 66 0f f8 c8 psubb %xmm0,%xmm1 - 421ec2: 66 0f d7 d1 pmovmskb %xmm1,%edx - 421ec6: 81 ea ff ff 00 00 sub $0xffff,%edx - 421ecc: 0f 85 1e 08 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 421ed2: 48 83 c1 10 add $0x10,%rcx - 421ed6: 66 0f 6f dc movdqa %xmm4,%xmm3 - 421eda: 49 83 c2 10 add $0x10,%r10 - 421ede: 7f 50 jg 421f30 <__GI_strcmp+0xc30> - 421ee0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 421ee5: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 421eea: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 421eee: 66 0f 73 db 09 psrldq $0x9,%xmm3 - 421ef3: 66 0f 73 fa 07 pslldq $0x7,%xmm2 - 421ef8: 66 0f eb d3 por %xmm3,%xmm2 - 421efc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 421f00: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 421f04: 66 0f f8 c8 psubb %xmm0,%xmm1 - 421f08: 66 0f d7 d1 pmovmskb %xmm1,%edx - 421f0c: 81 ea ff ff 00 00 sub $0xffff,%edx - 421f12: 0f 85 d8 07 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 421f18: 48 83 c1 10 add $0x10,%rcx - 421f1c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 421f20: e9 6b ff ff ff jmpq 421e90 <__GI_strcmp+0xb90> - 421f25: 90 nop - 421f26: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 421f2d: 00 00 00 - 421f30: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 421f34: 66 0f d7 d0 pmovmskb %xmm0,%edx - 421f38: f7 c2 00 fe 00 00 test $0xfe00,%edx - 421f3e: 75 10 jne 421f50 <__GI_strcmp+0xc50> - 421f40: 66 0f ef c0 pxor %xmm0,%xmm0 - 421f44: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 421f4b: e9 4a ff ff ff jmpq 421e9a <__GI_strcmp+0xb9a> - 421f50: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 421f55: 66 0f 73 d8 09 psrldq $0x9,%xmm0 - 421f5a: 66 0f 73 db 09 psrldq $0x9,%xmm3 - 421f5f: e9 7c 07 00 00 jmpq 4226e0 <__GI_strcmp+0x13e0> - 421f64: 66 90 xchg %ax,%ax - 421f66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 421f6d: 00 00 00 - 421f70: 66 0f ef c0 pxor %xmm0,%xmm0 - 421f74: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 421f78: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 421f7c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 421f80: 66 0f 73 fa 06 pslldq $0x6,%xmm2 - 421f85: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 421f89: 66 0f f8 d0 psubb %xmm0,%xmm2 - 421f8d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 421f92: d3 ea shr %cl,%edx - 421f94: 41 d3 e9 shr %cl,%r9d - 421f97: 44 29 ca sub %r9d,%edx - 421f9a: 0f 85 55 07 00 00 jne 4226f5 <__GI_strcmp+0x13f5> - 421fa0: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 421fa4: 66 0f ef c0 pxor %xmm0,%xmm0 - 421fa8: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 421faf: 41 b9 0a 00 00 00 mov $0xa,%r9d - 421fb5: 4c 8d 57 0a lea 0xa(%rdi),%r10 - 421fb9: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 421fc0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 421fc7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 421fce: 00 00 - 421fd0: 49 83 c2 10 add $0x10,%r10 - 421fd4: 0f 8f 96 00 00 00 jg 422070 <__GI_strcmp+0xd70> - 421fda: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 421fdf: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 421fe4: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 421fe8: 66 0f 73 db 0a psrldq $0xa,%xmm3 - 421fed: 66 0f 73 fa 06 pslldq $0x6,%xmm2 - 421ff2: 66 0f eb d3 por %xmm3,%xmm2 - 421ff6: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 421ffa: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 421ffe: 66 0f f8 c8 psubb %xmm0,%xmm1 - 422002: 66 0f d7 d1 pmovmskb %xmm1,%edx - 422006: 81 ea ff ff 00 00 sub $0xffff,%edx - 42200c: 0f 85 de 06 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 422012: 48 83 c1 10 add $0x10,%rcx - 422016: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42201a: 49 83 c2 10 add $0x10,%r10 - 42201e: 7f 50 jg 422070 <__GI_strcmp+0xd70> - 422020: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 422025: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42202a: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42202e: 66 0f 73 db 0a psrldq $0xa,%xmm3 - 422033: 66 0f 73 fa 06 pslldq $0x6,%xmm2 - 422038: 66 0f eb d3 por %xmm3,%xmm2 - 42203c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 422040: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 422044: 66 0f f8 c8 psubb %xmm0,%xmm1 - 422048: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42204c: 81 ea ff ff 00 00 sub $0xffff,%edx - 422052: 0f 85 98 06 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 422058: 48 83 c1 10 add $0x10,%rcx - 42205c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 422060: e9 6b ff ff ff jmpq 421fd0 <__GI_strcmp+0xcd0> - 422065: 90 nop - 422066: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42206d: 00 00 00 - 422070: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 422074: 66 0f d7 d0 pmovmskb %xmm0,%edx - 422078: f7 c2 00 fc 00 00 test $0xfc00,%edx - 42207e: 75 10 jne 422090 <__GI_strcmp+0xd90> - 422080: 66 0f ef c0 pxor %xmm0,%xmm0 - 422084: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42208b: e9 4a ff ff ff jmpq 421fda <__GI_strcmp+0xcda> - 422090: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 422095: 66 0f 73 d8 0a psrldq $0xa,%xmm0 - 42209a: 66 0f 73 db 0a psrldq $0xa,%xmm3 - 42209f: e9 3c 06 00 00 jmpq 4226e0 <__GI_strcmp+0x13e0> - 4220a4: 66 90 xchg %ax,%ax - 4220a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4220ad: 00 00 00 - 4220b0: 66 0f ef c0 pxor %xmm0,%xmm0 - 4220b4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 4220b8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 4220bc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4220c0: 66 0f 73 fa 05 pslldq $0x5,%xmm2 - 4220c5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 4220c9: 66 0f f8 d0 psubb %xmm0,%xmm2 - 4220cd: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 4220d2: d3 ea shr %cl,%edx - 4220d4: 41 d3 e9 shr %cl,%r9d - 4220d7: 44 29 ca sub %r9d,%edx - 4220da: 0f 85 15 06 00 00 jne 4226f5 <__GI_strcmp+0x13f5> - 4220e0: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 4220e4: 66 0f ef c0 pxor %xmm0,%xmm0 - 4220e8: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 4220ef: 41 b9 0b 00 00 00 mov $0xb,%r9d - 4220f5: 4c 8d 57 0b lea 0xb(%rdi),%r10 - 4220f9: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 422100: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 422107: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 42210e: 00 00 - 422110: 49 83 c2 10 add $0x10,%r10 - 422114: 0f 8f 96 00 00 00 jg 4221b0 <__GI_strcmp+0xeb0> - 42211a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42211f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 422124: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 422128: 66 0f 73 db 0b psrldq $0xb,%xmm3 - 42212d: 66 0f 73 fa 05 pslldq $0x5,%xmm2 - 422132: 66 0f eb d3 por %xmm3,%xmm2 - 422136: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42213a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42213e: 66 0f f8 c8 psubb %xmm0,%xmm1 - 422142: 66 0f d7 d1 pmovmskb %xmm1,%edx - 422146: 81 ea ff ff 00 00 sub $0xffff,%edx - 42214c: 0f 85 9e 05 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 422152: 48 83 c1 10 add $0x10,%rcx - 422156: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42215a: 49 83 c2 10 add $0x10,%r10 - 42215e: 7f 50 jg 4221b0 <__GI_strcmp+0xeb0> - 422160: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 422165: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42216a: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42216e: 66 0f 73 db 0b psrldq $0xb,%xmm3 - 422173: 66 0f 73 fa 05 pslldq $0x5,%xmm2 - 422178: 66 0f eb d3 por %xmm3,%xmm2 - 42217c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 422180: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 422184: 66 0f f8 c8 psubb %xmm0,%xmm1 - 422188: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42218c: 81 ea ff ff 00 00 sub $0xffff,%edx - 422192: 0f 85 58 05 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 422198: 48 83 c1 10 add $0x10,%rcx - 42219c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 4221a0: e9 6b ff ff ff jmpq 422110 <__GI_strcmp+0xe10> - 4221a5: 90 nop - 4221a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4221ad: 00 00 00 - 4221b0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 4221b4: 66 0f d7 d0 pmovmskb %xmm0,%edx - 4221b8: f7 c2 00 f8 00 00 test $0xf800,%edx - 4221be: 75 10 jne 4221d0 <__GI_strcmp+0xed0> - 4221c0: 66 0f ef c0 pxor %xmm0,%xmm0 - 4221c4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 4221cb: e9 4a ff ff ff jmpq 42211a <__GI_strcmp+0xe1a> - 4221d0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4221d5: 66 0f 73 d8 0b psrldq $0xb,%xmm0 - 4221da: 66 0f 73 db 0b psrldq $0xb,%xmm3 - 4221df: e9 fc 04 00 00 jmpq 4226e0 <__GI_strcmp+0x13e0> - 4221e4: 66 90 xchg %ax,%ax - 4221e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4221ed: 00 00 00 - 4221f0: 66 0f ef c0 pxor %xmm0,%xmm0 - 4221f4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 4221f8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 4221fc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 422200: 66 0f 73 fa 04 pslldq $0x4,%xmm2 - 422205: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 422209: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42220d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 422212: d3 ea shr %cl,%edx - 422214: 41 d3 e9 shr %cl,%r9d - 422217: 44 29 ca sub %r9d,%edx - 42221a: 0f 85 d5 04 00 00 jne 4226f5 <__GI_strcmp+0x13f5> - 422220: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 422224: 66 0f ef c0 pxor %xmm0,%xmm0 - 422228: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42222f: 41 b9 0c 00 00 00 mov $0xc,%r9d - 422235: 4c 8d 57 0c lea 0xc(%rdi),%r10 - 422239: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 422240: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 422247: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 42224e: 00 00 - 422250: 49 83 c2 10 add $0x10,%r10 - 422254: 0f 8f 96 00 00 00 jg 4222f0 <__GI_strcmp+0xff0> - 42225a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42225f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 422264: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 422268: 66 0f 73 db 0c psrldq $0xc,%xmm3 - 42226d: 66 0f 73 fa 04 pslldq $0x4,%xmm2 - 422272: 66 0f eb d3 por %xmm3,%xmm2 - 422276: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42227a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42227e: 66 0f f8 c8 psubb %xmm0,%xmm1 - 422282: 66 0f d7 d1 pmovmskb %xmm1,%edx - 422286: 81 ea ff ff 00 00 sub $0xffff,%edx - 42228c: 0f 85 5e 04 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 422292: 48 83 c1 10 add $0x10,%rcx - 422296: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42229a: 49 83 c2 10 add $0x10,%r10 - 42229e: 7f 50 jg 4222f0 <__GI_strcmp+0xff0> - 4222a0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4222a5: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4222aa: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 4222ae: 66 0f 73 db 0c psrldq $0xc,%xmm3 - 4222b3: 66 0f 73 fa 04 pslldq $0x4,%xmm2 - 4222b8: 66 0f eb d3 por %xmm3,%xmm2 - 4222bc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4222c0: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 4222c4: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4222c8: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4222cc: 81 ea ff ff 00 00 sub $0xffff,%edx - 4222d2: 0f 85 18 04 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 4222d8: 48 83 c1 10 add $0x10,%rcx - 4222dc: 66 0f 6f dc movdqa %xmm4,%xmm3 - 4222e0: e9 6b ff ff ff jmpq 422250 <__GI_strcmp+0xf50> - 4222e5: 90 nop - 4222e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4222ed: 00 00 00 - 4222f0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 4222f4: 66 0f d7 d0 pmovmskb %xmm0,%edx - 4222f8: f7 c2 00 f0 00 00 test $0xf000,%edx - 4222fe: 75 10 jne 422310 <__GI_strcmp+0x1010> - 422300: 66 0f ef c0 pxor %xmm0,%xmm0 - 422304: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42230b: e9 4a ff ff ff jmpq 42225a <__GI_strcmp+0xf5a> - 422310: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 422315: 66 0f 73 d8 0c psrldq $0xc,%xmm0 - 42231a: 66 0f 73 db 0c psrldq $0xc,%xmm3 - 42231f: e9 bc 03 00 00 jmpq 4226e0 <__GI_strcmp+0x13e0> - 422324: 66 90 xchg %ax,%ax - 422326: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42232d: 00 00 00 - 422330: 66 0f ef c0 pxor %xmm0,%xmm0 - 422334: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 422338: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42233c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 422340: 66 0f 73 fa 03 pslldq $0x3,%xmm2 - 422345: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 422349: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42234d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 422352: d3 ea shr %cl,%edx - 422354: 41 d3 e9 shr %cl,%r9d - 422357: 44 29 ca sub %r9d,%edx - 42235a: 0f 85 95 03 00 00 jne 4226f5 <__GI_strcmp+0x13f5> - 422360: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 422364: 66 0f ef c0 pxor %xmm0,%xmm0 - 422368: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42236f: 41 b9 0d 00 00 00 mov $0xd,%r9d - 422375: 4c 8d 57 0d lea 0xd(%rdi),%r10 - 422379: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 422380: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 422387: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 42238e: 00 00 - 422390: 49 83 c2 10 add $0x10,%r10 - 422394: 0f 8f 96 00 00 00 jg 422430 <__GI_strcmp+0x1130> - 42239a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42239f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4223a4: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 4223a8: 66 0f 73 db 0d psrldq $0xd,%xmm3 - 4223ad: 66 0f 73 fa 03 pslldq $0x3,%xmm2 - 4223b2: 66 0f eb d3 por %xmm3,%xmm2 - 4223b6: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4223ba: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 4223be: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4223c2: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4223c6: 81 ea ff ff 00 00 sub $0xffff,%edx - 4223cc: 0f 85 1e 03 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 4223d2: 48 83 c1 10 add $0x10,%rcx - 4223d6: 66 0f 6f dc movdqa %xmm4,%xmm3 - 4223da: 49 83 c2 10 add $0x10,%r10 - 4223de: 7f 50 jg 422430 <__GI_strcmp+0x1130> - 4223e0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4223e5: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4223ea: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 4223ee: 66 0f 73 db 0d psrldq $0xd,%xmm3 - 4223f3: 66 0f 73 fa 03 pslldq $0x3,%xmm2 - 4223f8: 66 0f eb d3 por %xmm3,%xmm2 - 4223fc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 422400: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 422404: 66 0f f8 c8 psubb %xmm0,%xmm1 - 422408: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42240c: 81 ea ff ff 00 00 sub $0xffff,%edx - 422412: 0f 85 d8 02 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 422418: 48 83 c1 10 add $0x10,%rcx - 42241c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 422420: e9 6b ff ff ff jmpq 422390 <__GI_strcmp+0x1090> - 422425: 90 nop - 422426: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42242d: 00 00 00 - 422430: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 422434: 66 0f d7 d0 pmovmskb %xmm0,%edx - 422438: f7 c2 00 e0 00 00 test $0xe000,%edx - 42243e: 75 10 jne 422450 <__GI_strcmp+0x1150> - 422440: 66 0f ef c0 pxor %xmm0,%xmm0 - 422444: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42244b: e9 4a ff ff ff jmpq 42239a <__GI_strcmp+0x109a> - 422450: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 422455: 66 0f 73 d8 0d psrldq $0xd,%xmm0 - 42245a: 66 0f 73 db 0d psrldq $0xd,%xmm3 - 42245f: e9 7c 02 00 00 jmpq 4226e0 <__GI_strcmp+0x13e0> - 422464: 66 90 xchg %ax,%ax - 422466: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42246d: 00 00 00 - 422470: 66 0f ef c0 pxor %xmm0,%xmm0 - 422474: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 422478: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42247c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 422480: 66 0f 73 fa 02 pslldq $0x2,%xmm2 - 422485: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 422489: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42248d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 422492: d3 ea shr %cl,%edx - 422494: 41 d3 e9 shr %cl,%r9d - 422497: 44 29 ca sub %r9d,%edx - 42249a: 0f 85 55 02 00 00 jne 4226f5 <__GI_strcmp+0x13f5> - 4224a0: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 4224a4: 66 0f ef c0 pxor %xmm0,%xmm0 - 4224a8: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 4224af: 41 b9 0e 00 00 00 mov $0xe,%r9d - 4224b5: 4c 8d 57 0e lea 0xe(%rdi),%r10 - 4224b9: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 4224c0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 4224c7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 4224ce: 00 00 - 4224d0: 49 83 c2 10 add $0x10,%r10 - 4224d4: 0f 8f 96 00 00 00 jg 422570 <__GI_strcmp+0x1270> - 4224da: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4224df: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4224e4: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 4224e8: 66 0f 73 db 0e psrldq $0xe,%xmm3 - 4224ed: 66 0f 73 fa 02 pslldq $0x2,%xmm2 - 4224f2: 66 0f eb d3 por %xmm3,%xmm2 - 4224f6: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4224fa: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 4224fe: 66 0f f8 c8 psubb %xmm0,%xmm1 - 422502: 66 0f d7 d1 pmovmskb %xmm1,%edx - 422506: 81 ea ff ff 00 00 sub $0xffff,%edx - 42250c: 0f 85 de 01 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 422512: 48 83 c1 10 add $0x10,%rcx - 422516: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42251a: 49 83 c2 10 add $0x10,%r10 - 42251e: 7f 50 jg 422570 <__GI_strcmp+0x1270> - 422520: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 422525: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42252a: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42252e: 66 0f 73 db 0e psrldq $0xe,%xmm3 - 422533: 66 0f 73 fa 02 pslldq $0x2,%xmm2 - 422538: 66 0f eb d3 por %xmm3,%xmm2 - 42253c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 422540: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 422544: 66 0f f8 c8 psubb %xmm0,%xmm1 - 422548: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42254c: 81 ea ff ff 00 00 sub $0xffff,%edx - 422552: 0f 85 98 01 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 422558: 48 83 c1 10 add $0x10,%rcx - 42255c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 422560: e9 6b ff ff ff jmpq 4224d0 <__GI_strcmp+0x11d0> - 422565: 90 nop - 422566: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42256d: 00 00 00 - 422570: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 422574: 66 0f d7 d0 pmovmskb %xmm0,%edx - 422578: f7 c2 00 c0 00 00 test $0xc000,%edx - 42257e: 75 10 jne 422590 <__GI_strcmp+0x1290> - 422580: 66 0f ef c0 pxor %xmm0,%xmm0 - 422584: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42258b: e9 4a ff ff ff jmpq 4224da <__GI_strcmp+0x11da> - 422590: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 422595: 66 0f 73 d8 0e psrldq $0xe,%xmm0 - 42259a: 66 0f 73 db 0e psrldq $0xe,%xmm3 - 42259f: e9 3c 01 00 00 jmpq 4226e0 <__GI_strcmp+0x13e0> - 4225a4: 66 90 xchg %ax,%ax - 4225a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4225ad: 00 00 00 - 4225b0: 66 0f ef c0 pxor %xmm0,%xmm0 - 4225b4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 4225b8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 4225bc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4225c0: 66 0f 73 fa 01 pslldq $0x1,%xmm2 - 4225c5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 4225c9: 66 0f f8 d0 psubb %xmm0,%xmm2 - 4225cd: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 4225d2: d3 ea shr %cl,%edx - 4225d4: 41 d3 e9 shr %cl,%r9d - 4225d7: 44 29 ca sub %r9d,%edx - 4225da: 0f 85 15 01 00 00 jne 4226f5 <__GI_strcmp+0x13f5> - 4225e0: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 4225e4: 66 0f ef c0 pxor %xmm0,%xmm0 - 4225e8: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 4225ef: 41 b9 0f 00 00 00 mov $0xf,%r9d - 4225f5: 4c 8d 57 0f lea 0xf(%rdi),%r10 - 4225f9: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 422600: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 422607: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 42260e: 00 00 - 422610: 49 83 c2 10 add $0x10,%r10 - 422614: 0f 8f 96 00 00 00 jg 4226b0 <__GI_strcmp+0x13b0> - 42261a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42261f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 422624: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 422628: 66 0f 73 db 0f psrldq $0xf,%xmm3 - 42262d: 66 0f 73 fa 01 pslldq $0x1,%xmm2 - 422632: 66 0f eb d3 por %xmm3,%xmm2 - 422636: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42263a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42263e: 66 0f f8 c8 psubb %xmm0,%xmm1 - 422642: 66 0f d7 d1 pmovmskb %xmm1,%edx - 422646: 81 ea ff ff 00 00 sub $0xffff,%edx - 42264c: 0f 85 9e 00 00 00 jne 4226f0 <__GI_strcmp+0x13f0> - 422652: 48 83 c1 10 add $0x10,%rcx - 422656: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42265a: 49 83 c2 10 add $0x10,%r10 - 42265e: 7f 50 jg 4226b0 <__GI_strcmp+0x13b0> - 422660: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 422665: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42266a: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42266e: 66 0f 73 db 0f psrldq $0xf,%xmm3 - 422673: 66 0f 73 fa 01 pslldq $0x1,%xmm2 - 422678: 66 0f eb d3 por %xmm3,%xmm2 - 42267c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 422680: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 422684: 66 0f f8 c8 psubb %xmm0,%xmm1 - 422688: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42268c: 81 ea ff ff 00 00 sub $0xffff,%edx - 422692: 75 5c jne 4226f0 <__GI_strcmp+0x13f0> - 422694: 48 83 c1 10 add $0x10,%rcx - 422698: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42269c: e9 6f ff ff ff jmpq 422610 <__GI_strcmp+0x1310> - 4226a1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4226a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4226ad: 00 00 00 - 4226b0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 4226b4: 66 0f d7 d0 pmovmskb %xmm0,%edx - 4226b8: f7 c2 00 80 00 00 test $0x8000,%edx - 4226be: 75 10 jne 4226d0 <__GI_strcmp+0x13d0> - 4226c0: 66 0f ef c0 pxor %xmm0,%xmm0 - 4226c4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 4226cb: e9 4a ff ff ff jmpq 42261a <__GI_strcmp+0x131a> - 4226d0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4226d5: 66 0f 73 db 0f psrldq $0xf,%xmm3 - 4226da: 66 0f 73 d8 0f psrldq $0xf,%xmm0 - 4226df: 90 nop - 4226e0: 66 0f 74 cb pcmpeqb %xmm3,%xmm1 - 4226e4: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4226e8: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4226ec: f7 d2 not %edx - 4226ee: 66 90 xchg %ax,%ax - 4226f0: 49 8d 44 09 f0 lea -0x10(%r9,%rcx,1),%rax - 4226f5: 48 8d 3c 07 lea (%rdi,%rax,1),%rdi - 4226f9: 48 8d 34 0e lea (%rsi,%rcx,1),%rsi - 4226fd: 45 85 c0 test %r8d,%r8d - 422700: 74 0e je 422710 <__GI_strcmp+0x1410> - 422702: 48 87 f7 xchg %rsi,%rdi - 422705: 90 nop - 422706: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42270d: 00 00 00 - 422710: 48 0f bc d2 bsf %rdx,%rdx - 422714: 0f b6 0c 16 movzbl (%rsi,%rdx,1),%ecx - 422718: 0f b6 04 17 movzbl (%rdi,%rdx,1),%eax - 42271c: 29 c8 sub %ecx,%eax - 42271e: c3 retq - 42271f: 31 c0 xor %eax,%eax - 422721: c3 retq - 422722: 0f 1f 40 00 nopl 0x0(%rax) - 422726: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42272d: 00 00 00 - 422730: 0f b6 0e movzbl (%rsi),%ecx - 422733: 0f b6 07 movzbl (%rdi),%eax - 422736: 29 c8 sub %ecx,%eax - 422738: c3 retq - 422739: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - -0000000000422740 <__strcmp_sse42>: - 422740: 89 f1 mov %esi,%ecx - 422742: 89 f8 mov %edi,%eax - 422744: 48 83 e1 3f and $0x3f,%rcx - 422748: 48 83 e0 3f and $0x3f,%rax - 42274c: 83 f9 30 cmp $0x30,%ecx - 42274f: 77 3f ja 422790 <__strcmp_sse42+0x50> - 422751: 83 f8 30 cmp $0x30,%eax - 422754: 77 3a ja 422790 <__strcmp_sse42+0x50> - 422756: f3 0f 6f 0f movdqu (%rdi),%xmm1 - 42275a: f3 0f 6f 16 movdqu (%rsi),%xmm2 - 42275e: 66 0f ef c0 pxor %xmm0,%xmm0 - 422762: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 422766: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42276a: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42276e: 66 0f d7 d1 pmovmskb %xmm1,%edx - 422772: 81 ea ff ff 00 00 sub $0xffff,%edx - 422778: 0f 85 42 0d 00 00 jne 4234c0 <__strcmp_sse42+0xd80> - 42277e: 48 83 c6 10 add $0x10,%rsi - 422782: 48 83 c7 10 add $0x10,%rdi - 422786: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42278d: 00 00 00 - 422790: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi - 422794: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi - 422798: ba ff ff 00 00 mov $0xffff,%edx - 42279d: 45 31 c0 xor %r8d,%r8d - 4227a0: 83 e1 0f and $0xf,%ecx - 4227a3: 83 e0 0f and $0xf,%eax - 4227a6: 66 0f ef c0 pxor %xmm0,%xmm0 - 4227aa: 39 c1 cmp %eax,%ecx - 4227ac: 74 32 je 4227e0 <__strcmp_sse42+0xa0> - 4227ae: 77 07 ja 4227b7 <__strcmp_sse42+0x77> - 4227b0: 41 89 d0 mov %edx,%r8d - 4227b3: 91 xchg %eax,%ecx - 4227b4: 48 87 f7 xchg %rsi,%rdi - 4227b7: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 4227bb: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 4227bf: 4c 8d 48 0f lea 0xf(%rax),%r9 - 4227c3: 49 29 c9 sub %rcx,%r9 - 4227c6: 4c 8d 15 23 08 08 00 lea 0x80823(%rip),%r10 # 4a2ff0 <__func__.10972+0x30> - 4227cd: 4f 63 0c 8a movslq (%r10,%r9,4),%r9 - 4227d1: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4227d5: 4f 8d 14 0a lea (%r10,%r9,1),%r10 - 4227d9: 41 ff e2 jmpq *%r10 - 4227dc: 0f 1f 40 00 nopl 0x0(%rax) - 4227e0: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 4227e4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4227e8: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 - 4227ec: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4227f0: 66 44 0f d7 c9 pmovmskb %xmm1,%r9d - 4227f5: d3 ea shr %cl,%edx - 4227f7: 41 d3 e9 shr %cl,%r9d - 4227fa: 44 29 ca sub %r9d,%edx - 4227fd: 0f 85 a8 0c 00 00 jne 4234ab <__strcmp_sse42+0xd6b> - 422803: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42280a: 49 c7 c1 10 00 00 00 mov $0x10,%r9 - 422811: 48 89 ca mov %rcx,%rdx - 422814: 66 90 xchg %ax,%ax - 422816: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42281d: 00 00 00 - 422820: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 422825: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 42282c: 48 8d 52 10 lea 0x10(%rdx),%rdx - 422830: 76 1e jbe 422850 <__strcmp_sse42+0x110> - 422832: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 422837: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 42283e: 48 8d 52 10 lea 0x10(%rdx),%rdx - 422842: 76 0c jbe 422850 <__strcmp_sse42+0x110> - 422844: eb da jmp 422820 <__strcmp_sse42+0xe0> - 422846: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42284d: 00 00 00 - 422850: 0f 83 79 0c 00 00 jae 4234cf <__strcmp_sse42+0xd8f> - 422856: 48 8d 4c 0a f0 lea -0x10(%rdx,%rcx,1),%rcx - 42285b: 0f b6 04 0f movzbl (%rdi,%rcx,1),%eax - 42285f: 0f b6 14 0e movzbl (%rsi,%rcx,1),%edx - 422863: 29 d0 sub %edx,%eax - 422865: c3 retq - 422866: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42286d: 00 00 00 - 422870: 66 0f 73 fa 0f pslldq $0xf,%xmm2 - 422875: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 422879: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42287d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 422882: d3 ea shr %cl,%edx - 422884: 41 d3 e9 shr %cl,%r9d - 422887: 44 29 ca sub %r9d,%edx - 42288a: 0f 85 1b 0c 00 00 jne 4234ab <__strcmp_sse42+0xd6b> - 422890: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 422894: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42289b: 41 b9 01 00 00 00 mov $0x1,%r9d - 4228a1: 4c 8d 57 01 lea 0x1(%rdi),%r10 - 4228a5: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 4228ac: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 4228b3: 48 89 ca mov %rcx,%rdx - 4228b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4228bd: 00 00 00 - 4228c0: 49 83 c2 10 add $0x10,%r10 - 4228c4: 7f 4a jg 422910 <__strcmp_sse42+0x1d0> - 4228c6: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 4228cb: 66 0f 3a 0f 44 17 f0 palignr $0x1,-0x10(%rdi,%rdx,1),%xmm0 - 4228d2: 01 - 4228d3: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 4228da: 0f 86 b0 0b 00 00 jbe 423490 <__strcmp_sse42+0xd50> - 4228e0: 48 83 c2 10 add $0x10,%rdx - 4228e4: 49 83 c2 10 add $0x10,%r10 - 4228e8: 7f 26 jg 422910 <__strcmp_sse42+0x1d0> - 4228ea: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 4228ef: 66 0f 3a 0f 44 17 f0 palignr $0x1,-0x10(%rdi,%rdx,1),%xmm0 - 4228f6: 01 - 4228f7: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 4228fe: 0f 86 8c 0b 00 00 jbe 423490 <__strcmp_sse42+0xd50> - 422904: 48 83 c2 10 add $0x10,%rdx - 422908: eb b6 jmp 4228c0 <__strcmp_sse42+0x180> - 42290a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 422910: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 422917: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 - 42291d: 66 0f 73 d8 01 psrldq $0x1,%xmm0 - 422922: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 - 422928: 83 f9 0e cmp $0xe,%ecx - 42292b: 77 99 ja 4228c6 <__strcmp_sse42+0x186> - 42292d: e9 4b 0b 00 00 jmpq 42347d <__strcmp_sse42+0xd3d> - 422932: 0f 1f 40 00 nopl 0x0(%rax) - 422936: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42293d: 00 00 00 - 422940: 66 0f 73 fa 0e pslldq $0xe,%xmm2 - 422945: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 422949: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42294d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 422952: d3 ea shr %cl,%edx - 422954: 41 d3 e9 shr %cl,%r9d - 422957: 44 29 ca sub %r9d,%edx - 42295a: 0f 85 4b 0b 00 00 jne 4234ab <__strcmp_sse42+0xd6b> - 422960: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 422964: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42296b: 41 b9 02 00 00 00 mov $0x2,%r9d - 422971: 4c 8d 57 02 lea 0x2(%rdi),%r10 - 422975: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42297c: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 422983: 48 89 ca mov %rcx,%rdx - 422986: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42298d: 00 00 00 - 422990: 49 83 c2 10 add $0x10,%r10 - 422994: 7f 4a jg 4229e0 <__strcmp_sse42+0x2a0> - 422996: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 42299b: 66 0f 3a 0f 44 17 f0 palignr $0x2,-0x10(%rdi,%rdx,1),%xmm0 - 4229a2: 02 - 4229a3: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 4229aa: 0f 86 e0 0a 00 00 jbe 423490 <__strcmp_sse42+0xd50> - 4229b0: 48 83 c2 10 add $0x10,%rdx - 4229b4: 49 83 c2 10 add $0x10,%r10 - 4229b8: 7f 26 jg 4229e0 <__strcmp_sse42+0x2a0> - 4229ba: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 4229bf: 66 0f 3a 0f 44 17 f0 palignr $0x2,-0x10(%rdi,%rdx,1),%xmm0 - 4229c6: 02 - 4229c7: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 4229ce: 0f 86 bc 0a 00 00 jbe 423490 <__strcmp_sse42+0xd50> - 4229d4: 48 83 c2 10 add $0x10,%rdx - 4229d8: eb b6 jmp 422990 <__strcmp_sse42+0x250> - 4229da: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4229e0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 4229e7: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 - 4229ed: 66 0f 73 d8 02 psrldq $0x2,%xmm0 - 4229f2: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 - 4229f8: 83 f9 0d cmp $0xd,%ecx - 4229fb: 77 99 ja 422996 <__strcmp_sse42+0x256> - 4229fd: e9 7b 0a 00 00 jmpq 42347d <__strcmp_sse42+0xd3d> - 422a02: 0f 1f 40 00 nopl 0x0(%rax) - 422a06: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 422a0d: 00 00 00 - 422a10: 66 0f 73 fa 0d pslldq $0xd,%xmm2 - 422a15: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 422a19: 66 0f f8 d0 psubb %xmm0,%xmm2 - 422a1d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 422a22: d3 ea shr %cl,%edx - 422a24: 41 d3 e9 shr %cl,%r9d - 422a27: 44 29 ca sub %r9d,%edx - 422a2a: 0f 85 7b 0a 00 00 jne 4234ab <__strcmp_sse42+0xd6b> - 422a30: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 422a34: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 422a3b: 41 b9 03 00 00 00 mov $0x3,%r9d - 422a41: 4c 8d 57 03 lea 0x3(%rdi),%r10 - 422a45: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 422a4c: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 422a53: 48 89 ca mov %rcx,%rdx - 422a56: 49 83 c2 10 add $0x10,%r10 - 422a5a: 7f 44 jg 422aa0 <__strcmp_sse42+0x360> - 422a5c: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 422a61: 66 0f 3a 0f 44 17 f0 palignr $0x3,-0x10(%rdi,%rdx,1),%xmm0 - 422a68: 03 - 422a69: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 422a70: 0f 86 1a 0a 00 00 jbe 423490 <__strcmp_sse42+0xd50> - 422a76: 48 83 c2 10 add $0x10,%rdx - 422a7a: 49 83 c2 10 add $0x10,%r10 - 422a7e: 7f 20 jg 422aa0 <__strcmp_sse42+0x360> - 422a80: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 422a85: 66 0f 3a 0f 44 17 f0 palignr $0x3,-0x10(%rdi,%rdx,1),%xmm0 - 422a8c: 03 - 422a8d: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 422a94: 0f 86 f6 09 00 00 jbe 423490 <__strcmp_sse42+0xd50> - 422a9a: 48 83 c2 10 add $0x10,%rdx - 422a9e: eb b6 jmp 422a56 <__strcmp_sse42+0x316> - 422aa0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 422aa7: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 - 422aad: 66 0f 73 d8 03 psrldq $0x3,%xmm0 - 422ab2: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 - 422ab8: 83 f9 0c cmp $0xc,%ecx - 422abb: 77 9f ja 422a5c <__strcmp_sse42+0x31c> - 422abd: e9 bb 09 00 00 jmpq 42347d <__strcmp_sse42+0xd3d> - 422ac2: 0f 1f 40 00 nopl 0x0(%rax) - 422ac6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 422acd: 00 00 00 - 422ad0: 66 0f 73 fa 0c pslldq $0xc,%xmm2 - 422ad5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 422ad9: 66 0f f8 d0 psubb %xmm0,%xmm2 - 422add: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 422ae2: d3 ea shr %cl,%edx - 422ae4: 41 d3 e9 shr %cl,%r9d - 422ae7: 44 29 ca sub %r9d,%edx - 422aea: 0f 85 bb 09 00 00 jne 4234ab <__strcmp_sse42+0xd6b> - 422af0: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 422af4: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 422afb: 41 b9 04 00 00 00 mov $0x4,%r9d - 422b01: 4c 8d 57 04 lea 0x4(%rdi),%r10 - 422b05: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 422b0c: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 422b13: 48 89 ca mov %rcx,%rdx - 422b16: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 422b1d: 00 00 00 - 422b20: 49 83 c2 10 add $0x10,%r10 - 422b24: 7f 4a jg 422b70 <__strcmp_sse42+0x430> - 422b26: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 422b2b: 66 0f 3a 0f 44 17 f0 palignr $0x4,-0x10(%rdi,%rdx,1),%xmm0 - 422b32: 04 - 422b33: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 422b3a: 0f 86 50 09 00 00 jbe 423490 <__strcmp_sse42+0xd50> - 422b40: 48 83 c2 10 add $0x10,%rdx - 422b44: 49 83 c2 10 add $0x10,%r10 - 422b48: 7f 26 jg 422b70 <__strcmp_sse42+0x430> - 422b4a: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 422b4f: 66 0f 3a 0f 44 17 f0 palignr $0x4,-0x10(%rdi,%rdx,1),%xmm0 - 422b56: 04 - 422b57: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 422b5e: 0f 86 2c 09 00 00 jbe 423490 <__strcmp_sse42+0xd50> - 422b64: 48 83 c2 10 add $0x10,%rdx - 422b68: eb b6 jmp 422b20 <__strcmp_sse42+0x3e0> - 422b6a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 422b70: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 422b77: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 - 422b7d: 66 0f 73 d8 04 psrldq $0x4,%xmm0 - 422b82: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 - 422b88: 83 f9 0b cmp $0xb,%ecx - 422b8b: 77 99 ja 422b26 <__strcmp_sse42+0x3e6> - 422b8d: e9 eb 08 00 00 jmpq 42347d <__strcmp_sse42+0xd3d> - 422b92: 0f 1f 40 00 nopl 0x0(%rax) - 422b96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 422b9d: 00 00 00 - 422ba0: 66 0f 73 fa 0b pslldq $0xb,%xmm2 - 422ba5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 422ba9: 66 0f f8 d0 psubb %xmm0,%xmm2 - 422bad: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 422bb2: d3 ea shr %cl,%edx - 422bb4: 41 d3 e9 shr %cl,%r9d - 422bb7: 44 29 ca sub %r9d,%edx - 422bba: 0f 85 eb 08 00 00 jne 4234ab <__strcmp_sse42+0xd6b> - 422bc0: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 422bc4: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 422bcb: 41 b9 05 00 00 00 mov $0x5,%r9d - 422bd1: 4c 8d 57 05 lea 0x5(%rdi),%r10 - 422bd5: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 422bdc: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 422be3: 48 89 ca mov %rcx,%rdx - 422be6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 422bed: 00 00 00 - 422bf0: 49 83 c2 10 add $0x10,%r10 - 422bf4: 7f 4a jg 422c40 <__strcmp_sse42+0x500> - 422bf6: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 422bfb: 66 0f 3a 0f 44 17 f0 palignr $0x5,-0x10(%rdi,%rdx,1),%xmm0 - 422c02: 05 - 422c03: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 422c0a: 0f 86 80 08 00 00 jbe 423490 <__strcmp_sse42+0xd50> - 422c10: 48 83 c2 10 add $0x10,%rdx - 422c14: 49 83 c2 10 add $0x10,%r10 - 422c18: 7f 26 jg 422c40 <__strcmp_sse42+0x500> - 422c1a: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 422c1f: 66 0f 3a 0f 44 17 f0 palignr $0x5,-0x10(%rdi,%rdx,1),%xmm0 - 422c26: 05 - 422c27: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 422c2e: 0f 86 5c 08 00 00 jbe 423490 <__strcmp_sse42+0xd50> - 422c34: 48 83 c2 10 add $0x10,%rdx - 422c38: eb b6 jmp 422bf0 <__strcmp_sse42+0x4b0> - 422c3a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 422c40: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 422c47: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 - 422c4d: 66 0f 73 d8 05 psrldq $0x5,%xmm0 - 422c52: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 - 422c58: 83 f9 0a cmp $0xa,%ecx - 422c5b: 77 99 ja 422bf6 <__strcmp_sse42+0x4b6> - 422c5d: e9 1b 08 00 00 jmpq 42347d <__strcmp_sse42+0xd3d> - 422c62: 0f 1f 40 00 nopl 0x0(%rax) - 422c66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 422c6d: 00 00 00 - 422c70: 66 0f 73 fa 0a pslldq $0xa,%xmm2 - 422c75: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 422c79: 66 0f f8 d0 psubb %xmm0,%xmm2 - 422c7d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 422c82: d3 ea shr %cl,%edx - 422c84: 41 d3 e9 shr %cl,%r9d - 422c87: 44 29 ca sub %r9d,%edx - 422c8a: 0f 85 1b 08 00 00 jne 4234ab <__strcmp_sse42+0xd6b> - 422c90: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 422c94: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 422c9b: 41 b9 06 00 00 00 mov $0x6,%r9d - 422ca1: 4c 8d 57 06 lea 0x6(%rdi),%r10 - 422ca5: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 422cac: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 422cb3: 48 89 ca mov %rcx,%rdx - 422cb6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 422cbd: 00 00 00 - 422cc0: 49 83 c2 10 add $0x10,%r10 - 422cc4: 7f 4a jg 422d10 <__strcmp_sse42+0x5d0> - 422cc6: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 422ccb: 66 0f 3a 0f 44 17 f0 palignr $0x6,-0x10(%rdi,%rdx,1),%xmm0 - 422cd2: 06 - 422cd3: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 422cda: 0f 86 b0 07 00 00 jbe 423490 <__strcmp_sse42+0xd50> - 422ce0: 48 83 c2 10 add $0x10,%rdx - 422ce4: 49 83 c2 10 add $0x10,%r10 - 422ce8: 7f 26 jg 422d10 <__strcmp_sse42+0x5d0> - 422cea: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 422cef: 66 0f 3a 0f 44 17 f0 palignr $0x6,-0x10(%rdi,%rdx,1),%xmm0 - 422cf6: 06 - 422cf7: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 422cfe: 0f 86 8c 07 00 00 jbe 423490 <__strcmp_sse42+0xd50> - 422d04: 48 83 c2 10 add $0x10,%rdx - 422d08: eb b6 jmp 422cc0 <__strcmp_sse42+0x580> - 422d0a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 422d10: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 422d17: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 - 422d1d: 66 0f 73 d8 06 psrldq $0x6,%xmm0 - 422d22: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 - 422d28: 83 f9 09 cmp $0x9,%ecx - 422d2b: 77 99 ja 422cc6 <__strcmp_sse42+0x586> - 422d2d: e9 4b 07 00 00 jmpq 42347d <__strcmp_sse42+0xd3d> - 422d32: 0f 1f 40 00 nopl 0x0(%rax) - 422d36: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 422d3d: 00 00 00 - 422d40: 66 0f 73 fa 09 pslldq $0x9,%xmm2 - 422d45: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 422d49: 66 0f f8 d0 psubb %xmm0,%xmm2 - 422d4d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 422d52: d3 ea shr %cl,%edx - 422d54: 41 d3 e9 shr %cl,%r9d - 422d57: 44 29 ca sub %r9d,%edx - 422d5a: 0f 85 4b 07 00 00 jne 4234ab <__strcmp_sse42+0xd6b> - 422d60: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 422d64: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 422d6b: 41 b9 07 00 00 00 mov $0x7,%r9d - 422d71: 4c 8d 57 07 lea 0x7(%rdi),%r10 - 422d75: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 422d7c: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 422d83: 48 89 ca mov %rcx,%rdx - 422d86: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 422d8d: 00 00 00 - 422d90: 49 83 c2 10 add $0x10,%r10 - 422d94: 7f 4a jg 422de0 <__strcmp_sse42+0x6a0> - 422d96: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 422d9b: 66 0f 3a 0f 44 17 f0 palignr $0x7,-0x10(%rdi,%rdx,1),%xmm0 - 422da2: 07 - 422da3: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 422daa: 0f 86 e0 06 00 00 jbe 423490 <__strcmp_sse42+0xd50> - 422db0: 48 83 c2 10 add $0x10,%rdx - 422db4: 49 83 c2 10 add $0x10,%r10 - 422db8: 7f 26 jg 422de0 <__strcmp_sse42+0x6a0> - 422dba: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 422dbf: 66 0f 3a 0f 44 17 f0 palignr $0x7,-0x10(%rdi,%rdx,1),%xmm0 - 422dc6: 07 - 422dc7: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 422dce: 0f 86 bc 06 00 00 jbe 423490 <__strcmp_sse42+0xd50> - 422dd4: 48 83 c2 10 add $0x10,%rdx - 422dd8: eb b6 jmp 422d90 <__strcmp_sse42+0x650> - 422dda: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 422de0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 422de7: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 - 422ded: 66 0f 73 d8 07 psrldq $0x7,%xmm0 - 422df2: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 - 422df8: 83 f9 08 cmp $0x8,%ecx - 422dfb: 77 99 ja 422d96 <__strcmp_sse42+0x656> - 422dfd: e9 7b 06 00 00 jmpq 42347d <__strcmp_sse42+0xd3d> - 422e02: 0f 1f 40 00 nopl 0x0(%rax) - 422e06: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 422e0d: 00 00 00 - 422e10: 66 0f 73 fa 08 pslldq $0x8,%xmm2 - 422e15: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 422e19: 66 0f f8 d0 psubb %xmm0,%xmm2 - 422e1d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 422e22: d3 ea shr %cl,%edx - 422e24: 41 d3 e9 shr %cl,%r9d - 422e27: 44 29 ca sub %r9d,%edx - 422e2a: 0f 85 7b 06 00 00 jne 4234ab <__strcmp_sse42+0xd6b> - 422e30: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 422e34: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 422e3b: 41 b9 08 00 00 00 mov $0x8,%r9d - 422e41: 4c 8d 57 08 lea 0x8(%rdi),%r10 - 422e45: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 422e4c: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 422e53: 48 89 ca mov %rcx,%rdx - 422e56: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 422e5d: 00 00 00 - 422e60: 49 83 c2 10 add $0x10,%r10 - 422e64: 7f 4a jg 422eb0 <__strcmp_sse42+0x770> - 422e66: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 422e6b: 66 0f 3a 0f 44 17 f0 palignr $0x8,-0x10(%rdi,%rdx,1),%xmm0 - 422e72: 08 - 422e73: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 422e7a: 0f 86 10 06 00 00 jbe 423490 <__strcmp_sse42+0xd50> - 422e80: 48 83 c2 10 add $0x10,%rdx - 422e84: 49 83 c2 10 add $0x10,%r10 - 422e88: 7f 26 jg 422eb0 <__strcmp_sse42+0x770> - 422e8a: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 422e8f: 66 0f 3a 0f 44 17 f0 palignr $0x8,-0x10(%rdi,%rdx,1),%xmm0 - 422e96: 08 - 422e97: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 422e9e: 0f 86 ec 05 00 00 jbe 423490 <__strcmp_sse42+0xd50> - 422ea4: 48 83 c2 10 add $0x10,%rdx - 422ea8: eb b6 jmp 422e60 <__strcmp_sse42+0x720> - 422eaa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 422eb0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 422eb7: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 - 422ebd: 66 0f 73 d8 08 psrldq $0x8,%xmm0 - 422ec2: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 - 422ec8: 83 f9 07 cmp $0x7,%ecx - 422ecb: 77 99 ja 422e66 <__strcmp_sse42+0x726> - 422ecd: e9 ab 05 00 00 jmpq 42347d <__strcmp_sse42+0xd3d> - 422ed2: 0f 1f 40 00 nopl 0x0(%rax) - 422ed6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 422edd: 00 00 00 - 422ee0: 66 0f 73 fa 07 pslldq $0x7,%xmm2 - 422ee5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 422ee9: 66 0f f8 d0 psubb %xmm0,%xmm2 - 422eed: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 422ef2: d3 ea shr %cl,%edx - 422ef4: 41 d3 e9 shr %cl,%r9d - 422ef7: 44 29 ca sub %r9d,%edx - 422efa: 0f 85 ab 05 00 00 jne 4234ab <__strcmp_sse42+0xd6b> - 422f00: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 422f04: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 422f0b: 41 b9 09 00 00 00 mov $0x9,%r9d - 422f11: 4c 8d 57 09 lea 0x9(%rdi),%r10 - 422f15: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 422f1c: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 422f23: 48 89 ca mov %rcx,%rdx - 422f26: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 422f2d: 00 00 00 - 422f30: 49 83 c2 10 add $0x10,%r10 - 422f34: 7f 4a jg 422f80 <__strcmp_sse42+0x840> - 422f36: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 422f3b: 66 0f 3a 0f 44 17 f0 palignr $0x9,-0x10(%rdi,%rdx,1),%xmm0 - 422f42: 09 - 422f43: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 422f4a: 0f 86 40 05 00 00 jbe 423490 <__strcmp_sse42+0xd50> - 422f50: 48 83 c2 10 add $0x10,%rdx - 422f54: 49 83 c2 10 add $0x10,%r10 - 422f58: 7f 26 jg 422f80 <__strcmp_sse42+0x840> - 422f5a: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 422f5f: 66 0f 3a 0f 44 17 f0 palignr $0x9,-0x10(%rdi,%rdx,1),%xmm0 - 422f66: 09 - 422f67: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 422f6e: 0f 86 1c 05 00 00 jbe 423490 <__strcmp_sse42+0xd50> - 422f74: 48 83 c2 10 add $0x10,%rdx - 422f78: eb b6 jmp 422f30 <__strcmp_sse42+0x7f0> - 422f7a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 422f80: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 422f87: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 - 422f8d: 66 0f 73 d8 09 psrldq $0x9,%xmm0 - 422f92: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 - 422f98: 83 f9 06 cmp $0x6,%ecx - 422f9b: 77 99 ja 422f36 <__strcmp_sse42+0x7f6> - 422f9d: e9 db 04 00 00 jmpq 42347d <__strcmp_sse42+0xd3d> - 422fa2: 0f 1f 40 00 nopl 0x0(%rax) - 422fa6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 422fad: 00 00 00 - 422fb0: 66 0f 73 fa 06 pslldq $0x6,%xmm2 - 422fb5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 422fb9: 66 0f f8 d0 psubb %xmm0,%xmm2 - 422fbd: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 422fc2: d3 ea shr %cl,%edx - 422fc4: 41 d3 e9 shr %cl,%r9d - 422fc7: 44 29 ca sub %r9d,%edx - 422fca: 0f 85 db 04 00 00 jne 4234ab <__strcmp_sse42+0xd6b> - 422fd0: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 422fd4: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 422fdb: 41 b9 0a 00 00 00 mov $0xa,%r9d - 422fe1: 4c 8d 57 0a lea 0xa(%rdi),%r10 - 422fe5: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 422fec: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 422ff3: 48 89 ca mov %rcx,%rdx - 422ff6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 422ffd: 00 00 00 - 423000: 49 83 c2 10 add $0x10,%r10 - 423004: 7f 4a jg 423050 <__strcmp_sse42+0x910> - 423006: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 42300b: 66 0f 3a 0f 44 17 f0 palignr $0xa,-0x10(%rdi,%rdx,1),%xmm0 - 423012: 0a - 423013: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 42301a: 0f 86 70 04 00 00 jbe 423490 <__strcmp_sse42+0xd50> - 423020: 48 83 c2 10 add $0x10,%rdx - 423024: 49 83 c2 10 add $0x10,%r10 - 423028: 7f 26 jg 423050 <__strcmp_sse42+0x910> - 42302a: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 42302f: 66 0f 3a 0f 44 17 f0 palignr $0xa,-0x10(%rdi,%rdx,1),%xmm0 - 423036: 0a - 423037: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 42303e: 0f 86 4c 04 00 00 jbe 423490 <__strcmp_sse42+0xd50> - 423044: 48 83 c2 10 add $0x10,%rdx - 423048: eb b6 jmp 423000 <__strcmp_sse42+0x8c0> - 42304a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 423050: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 423057: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 - 42305d: 66 0f 73 d8 0a psrldq $0xa,%xmm0 - 423062: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 - 423068: 83 f9 05 cmp $0x5,%ecx - 42306b: 77 99 ja 423006 <__strcmp_sse42+0x8c6> - 42306d: e9 0b 04 00 00 jmpq 42347d <__strcmp_sse42+0xd3d> - 423072: 0f 1f 40 00 nopl 0x0(%rax) - 423076: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42307d: 00 00 00 - 423080: 66 0f 73 fa 05 pslldq $0x5,%xmm2 - 423085: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 423089: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42308d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 423092: d3 ea shr %cl,%edx - 423094: 41 d3 e9 shr %cl,%r9d - 423097: 44 29 ca sub %r9d,%edx - 42309a: 0f 85 0b 04 00 00 jne 4234ab <__strcmp_sse42+0xd6b> - 4230a0: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 4230a4: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 4230ab: 41 b9 0b 00 00 00 mov $0xb,%r9d - 4230b1: 4c 8d 57 0b lea 0xb(%rdi),%r10 - 4230b5: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 4230bc: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 4230c3: 48 89 ca mov %rcx,%rdx - 4230c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4230cd: 00 00 00 - 4230d0: 49 83 c2 10 add $0x10,%r10 - 4230d4: 7f 4a jg 423120 <__strcmp_sse42+0x9e0> - 4230d6: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 4230db: 66 0f 3a 0f 44 17 f0 palignr $0xb,-0x10(%rdi,%rdx,1),%xmm0 - 4230e2: 0b - 4230e3: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 4230ea: 0f 86 a0 03 00 00 jbe 423490 <__strcmp_sse42+0xd50> - 4230f0: 48 83 c2 10 add $0x10,%rdx - 4230f4: 49 83 c2 10 add $0x10,%r10 - 4230f8: 7f 26 jg 423120 <__strcmp_sse42+0x9e0> - 4230fa: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 4230ff: 66 0f 3a 0f 44 17 f0 palignr $0xb,-0x10(%rdi,%rdx,1),%xmm0 - 423106: 0b - 423107: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 42310e: 0f 86 7c 03 00 00 jbe 423490 <__strcmp_sse42+0xd50> - 423114: 48 83 c2 10 add $0x10,%rdx - 423118: eb b6 jmp 4230d0 <__strcmp_sse42+0x990> - 42311a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 423120: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 423127: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 - 42312d: 66 0f 73 d8 0b psrldq $0xb,%xmm0 - 423132: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 - 423138: 83 f9 04 cmp $0x4,%ecx - 42313b: 77 99 ja 4230d6 <__strcmp_sse42+0x996> - 42313d: e9 3b 03 00 00 jmpq 42347d <__strcmp_sse42+0xd3d> - 423142: 0f 1f 40 00 nopl 0x0(%rax) - 423146: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42314d: 00 00 00 - 423150: 66 0f 73 fa 04 pslldq $0x4,%xmm2 - 423155: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 423159: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42315d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 423162: d3 ea shr %cl,%edx - 423164: 41 d3 e9 shr %cl,%r9d - 423167: 44 29 ca sub %r9d,%edx - 42316a: 0f 85 3b 03 00 00 jne 4234ab <__strcmp_sse42+0xd6b> - 423170: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 423174: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42317b: 41 b9 0c 00 00 00 mov $0xc,%r9d - 423181: 4c 8d 57 0c lea 0xc(%rdi),%r10 - 423185: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42318c: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 423193: 48 89 ca mov %rcx,%rdx - 423196: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42319d: 00 00 00 - 4231a0: 49 83 c2 10 add $0x10,%r10 - 4231a4: 7f 4a jg 4231f0 <__strcmp_sse42+0xab0> - 4231a6: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 4231ab: 66 0f 3a 0f 44 17 f0 palignr $0xc,-0x10(%rdi,%rdx,1),%xmm0 - 4231b2: 0c - 4231b3: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 4231ba: 0f 86 d0 02 00 00 jbe 423490 <__strcmp_sse42+0xd50> - 4231c0: 48 83 c2 10 add $0x10,%rdx - 4231c4: 49 83 c2 10 add $0x10,%r10 - 4231c8: 7f 26 jg 4231f0 <__strcmp_sse42+0xab0> - 4231ca: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 4231cf: 66 0f 3a 0f 44 17 f0 palignr $0xc,-0x10(%rdi,%rdx,1),%xmm0 - 4231d6: 0c - 4231d7: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 4231de: 0f 86 ac 02 00 00 jbe 423490 <__strcmp_sse42+0xd50> - 4231e4: 48 83 c2 10 add $0x10,%rdx - 4231e8: eb b6 jmp 4231a0 <__strcmp_sse42+0xa60> - 4231ea: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4231f0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 4231f7: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 - 4231fd: 66 0f 73 d8 0c psrldq $0xc,%xmm0 - 423202: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 - 423208: 83 f9 03 cmp $0x3,%ecx - 42320b: 77 99 ja 4231a6 <__strcmp_sse42+0xa66> - 42320d: e9 6b 02 00 00 jmpq 42347d <__strcmp_sse42+0xd3d> - 423212: 0f 1f 40 00 nopl 0x0(%rax) - 423216: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42321d: 00 00 00 - 423220: 66 0f 73 fa 03 pslldq $0x3,%xmm2 - 423225: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 423229: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42322d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 423232: d3 ea shr %cl,%edx - 423234: 41 d3 e9 shr %cl,%r9d - 423237: 44 29 ca sub %r9d,%edx - 42323a: 0f 85 6b 02 00 00 jne 4234ab <__strcmp_sse42+0xd6b> - 423240: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 423244: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42324b: 41 b9 0d 00 00 00 mov $0xd,%r9d - 423251: 4c 8d 57 0d lea 0xd(%rdi),%r10 - 423255: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42325c: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 423263: 48 89 ca mov %rcx,%rdx - 423266: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42326d: 00 00 00 - 423270: 49 83 c2 10 add $0x10,%r10 - 423274: 7f 4a jg 4232c0 <__strcmp_sse42+0xb80> - 423276: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 42327b: 66 0f 3a 0f 44 17 f0 palignr $0xd,-0x10(%rdi,%rdx,1),%xmm0 - 423282: 0d - 423283: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 42328a: 0f 86 00 02 00 00 jbe 423490 <__strcmp_sse42+0xd50> - 423290: 48 83 c2 10 add $0x10,%rdx - 423294: 49 83 c2 10 add $0x10,%r10 - 423298: 7f 26 jg 4232c0 <__strcmp_sse42+0xb80> - 42329a: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 42329f: 66 0f 3a 0f 44 17 f0 palignr $0xd,-0x10(%rdi,%rdx,1),%xmm0 - 4232a6: 0d - 4232a7: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 4232ae: 0f 86 dc 01 00 00 jbe 423490 <__strcmp_sse42+0xd50> - 4232b4: 48 83 c2 10 add $0x10,%rdx - 4232b8: eb b6 jmp 423270 <__strcmp_sse42+0xb30> - 4232ba: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4232c0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 4232c7: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 - 4232cd: 66 0f 73 d8 0d psrldq $0xd,%xmm0 - 4232d2: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 - 4232d8: 83 f9 02 cmp $0x2,%ecx - 4232db: 77 99 ja 423276 <__strcmp_sse42+0xb36> - 4232dd: e9 9b 01 00 00 jmpq 42347d <__strcmp_sse42+0xd3d> - 4232e2: 0f 1f 40 00 nopl 0x0(%rax) - 4232e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4232ed: 00 00 00 - 4232f0: 66 0f 73 fa 02 pslldq $0x2,%xmm2 - 4232f5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 4232f9: 66 0f f8 d0 psubb %xmm0,%xmm2 - 4232fd: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 423302: d3 ea shr %cl,%edx - 423304: 41 d3 e9 shr %cl,%r9d - 423307: 44 29 ca sub %r9d,%edx - 42330a: 0f 85 9b 01 00 00 jne 4234ab <__strcmp_sse42+0xd6b> - 423310: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 423314: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42331b: 41 b9 0e 00 00 00 mov $0xe,%r9d - 423321: 4c 8d 57 0e lea 0xe(%rdi),%r10 - 423325: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42332c: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 423333: 48 89 ca mov %rcx,%rdx - 423336: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42333d: 00 00 00 - 423340: 49 83 c2 10 add $0x10,%r10 - 423344: 7f 4a jg 423390 <__strcmp_sse42+0xc50> - 423346: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 42334b: 66 0f 3a 0f 44 17 f0 palignr $0xe,-0x10(%rdi,%rdx,1),%xmm0 - 423352: 0e - 423353: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 42335a: 0f 86 30 01 00 00 jbe 423490 <__strcmp_sse42+0xd50> - 423360: 48 83 c2 10 add $0x10,%rdx - 423364: 49 83 c2 10 add $0x10,%r10 - 423368: 7f 26 jg 423390 <__strcmp_sse42+0xc50> - 42336a: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 42336f: 66 0f 3a 0f 44 17 f0 palignr $0xe,-0x10(%rdi,%rdx,1),%xmm0 - 423376: 0e - 423377: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 42337e: 0f 86 0c 01 00 00 jbe 423490 <__strcmp_sse42+0xd50> - 423384: 48 83 c2 10 add $0x10,%rdx - 423388: eb b6 jmp 423340 <__strcmp_sse42+0xc00> - 42338a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 423390: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 423397: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 - 42339d: 66 0f 73 d8 0e psrldq $0xe,%xmm0 - 4233a2: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 - 4233a8: 83 f9 01 cmp $0x1,%ecx - 4233ab: 77 99 ja 423346 <__strcmp_sse42+0xc06> - 4233ad: e9 cb 00 00 00 jmpq 42347d <__strcmp_sse42+0xd3d> - 4233b2: 0f 1f 40 00 nopl 0x0(%rax) - 4233b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4233bd: 00 00 00 - 4233c0: 66 0f 73 fa 01 pslldq $0x1,%xmm2 - 4233c5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 4233c9: 66 0f f8 d0 psubb %xmm0,%xmm2 - 4233cd: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 4233d2: d3 ea shr %cl,%edx - 4233d4: 41 d3 e9 shr %cl,%r9d - 4233d7: 44 29 ca sub %r9d,%edx - 4233da: 0f 85 cb 00 00 00 jne 4234ab <__strcmp_sse42+0xd6b> - 4233e0: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 4233e4: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 4233eb: 41 b9 0f 00 00 00 mov $0xf,%r9d - 4233f1: 4c 8d 57 0f lea 0xf(%rdi),%r10 - 4233f5: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 4233fc: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 423403: 48 89 ca mov %rcx,%rdx - 423406: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42340d: 00 00 00 - 423410: 49 83 c2 10 add $0x10,%r10 - 423414: 7f 4a jg 423460 <__strcmp_sse42+0xd20> - 423416: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 42341b: 66 0f 3a 0f 44 17 f0 palignr $0xf,-0x10(%rdi,%rdx,1),%xmm0 - 423422: 0f - 423423: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 42342a: 76 64 jbe 423490 <__strcmp_sse42+0xd50> - 42342c: 48 83 c2 10 add $0x10,%rdx - 423430: 49 83 c2 10 add $0x10,%r10 - 423434: 7f 2a jg 423460 <__strcmp_sse42+0xd20> - 423436: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 42343b: 66 0f 3a 0f 44 17 f0 palignr $0xf,-0x10(%rdi,%rdx,1),%xmm0 - 423442: 0f - 423443: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 42344a: 76 44 jbe 423490 <__strcmp_sse42+0xd50> - 42344c: 48 83 c2 10 add $0x10,%rdx - 423450: eb be jmp 423410 <__strcmp_sse42+0xcd0> - 423452: 0f 1f 40 00 nopl 0x0(%rax) - 423456: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42345d: 00 00 00 - 423460: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 423467: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 - 42346d: 66 0f 73 d8 0f psrldq $0xf,%xmm0 - 423472: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 - 423478: 83 f9 00 cmp $0x0,%ecx - 42347b: 77 99 ja 423416 <__strcmp_sse42+0xcd6> - 42347d: 66 0f 3a 63 04 16 1a pcmpistri $0x1a,(%rsi,%rdx,1),%xmm0 - 423484: 66 90 xchg %ax,%ax - 423486: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42348d: 00 00 00 - 423490: 73 3d jae 4234cf <__strcmp_sse42+0xd8f> - 423492: 48 01 ca add %rcx,%rdx - 423495: 4a 8d 7c 0f f0 lea -0x10(%rdi,%r9,1),%rdi - 42349a: 0f b6 04 17 movzbl (%rdi,%rdx,1),%eax - 42349e: 0f b6 14 16 movzbl (%rsi,%rdx,1),%edx - 4234a2: 45 85 c0 test %r8d,%r8d - 4234a5: 74 01 je 4234a8 <__strcmp_sse42+0xd68> - 4234a7: 92 xchg %eax,%edx - 4234a8: 29 d0 sub %edx,%eax - 4234aa: c3 retq - 4234ab: 48 8d 3c 07 lea (%rdi,%rax,1),%rdi - 4234af: 48 8d 34 0e lea (%rsi,%rcx,1),%rsi - 4234b3: 45 85 c0 test %r8d,%r8d - 4234b6: 74 08 je 4234c0 <__strcmp_sse42+0xd80> - 4234b8: 48 87 f7 xchg %rsi,%rdi - 4234bb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4234c0: 48 0f bc d2 bsf %rdx,%rdx - 4234c4: 0f b6 0c 16 movzbl (%rsi,%rdx,1),%ecx - 4234c8: 0f b6 04 17 movzbl (%rdi,%rdx,1),%eax - 4234cc: 29 c8 sub %ecx,%eax - 4234ce: c3 retq - 4234cf: 31 c0 xor %eax,%eax - 4234d1: c3 retq - 4234d2: 0f 1f 40 00 nopl 0x0(%rax) - 4234d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4234dd: 00 00 00 - 4234e0: 0f b6 0e movzbl (%rsi),%ecx - 4234e3: 0f b6 07 movzbl (%rdi),%eax - 4234e6: 29 c8 sub %ecx,%eax - 4234e8: c3 retq - 4234e9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - -00000000004234f0 : - 4234f0: 48 8d 05 39 78 01 00 lea 0x17839(%rip),%rax # 43ad30 <__strcpy_sse2_unaligned> - 4234f7: f7 05 bf 91 2a 00 10 testl $0x10,0x2a91bf(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> - 4234fe: 00 00 00 - 423501: 75 1a jne 42351d - 423503: 48 8d 05 16 00 00 00 lea 0x16(%rip),%rax # 423520 <__GI_strcpy> - 42350a: f7 05 7c 91 2a 00 00 testl $0x200,0x2a917c(%rip) # 6cc690 <_dl_x86_cpu_features+0x10> - 423511: 02 00 00 - 423514: 74 07 je 42351d - 423516: 48 8d 05 53 48 01 00 lea 0x14853(%rip),%rax # 437d70 <__strcpy_ssse3> - 42351d: c3 retq - 42351e: 66 90 xchg %ax,%ax - -0000000000423520 <__GI_strcpy>: - 423520: 48 89 f1 mov %rsi,%rcx - 423523: 83 e1 07 and $0x7,%ecx - 423526: 48 89 fa mov %rdi,%rdx - 423529: 74 1b je 423546 <__GI_strcpy+0x26> - 42352b: f7 d9 neg %ecx - 42352d: 83 c1 08 add $0x8,%ecx - 423530: 8a 06 mov (%rsi),%al - 423532: 84 c0 test %al,%al - 423534: 88 02 mov %al,(%rdx) - 423536: 0f 84 bc 00 00 00 je 4235f8 <__GI_strcpy+0xd8> - 42353c: 48 ff c6 inc %rsi - 42353f: 48 ff c2 inc %rdx - 423542: ff c9 dec %ecx - 423544: 75 ea jne 423530 <__GI_strcpy+0x10> - 423546: 49 b8 ff fe fe fe fe movabs $0xfefefefefefefeff,%r8 - 42354d: fe fe fe - 423550: 48 8b 06 mov (%rsi),%rax - 423553: 48 83 c6 08 add $0x8,%rsi - 423557: 49 89 c1 mov %rax,%r9 - 42355a: 4d 01 c1 add %r8,%r9 - 42355d: 0f 83 7d 00 00 00 jae 4235e0 <__GI_strcpy+0xc0> - 423563: 49 31 c1 xor %rax,%r9 - 423566: 4d 09 c1 or %r8,%r9 - 423569: 49 ff c1 inc %r9 - 42356c: 75 72 jne 4235e0 <__GI_strcpy+0xc0> - 42356e: 48 89 02 mov %rax,(%rdx) - 423571: 48 83 c2 08 add $0x8,%rdx - 423575: 48 8b 06 mov (%rsi),%rax - 423578: 48 83 c6 08 add $0x8,%rsi - 42357c: 49 89 c1 mov %rax,%r9 - 42357f: 4d 01 c1 add %r8,%r9 - 423582: 73 5c jae 4235e0 <__GI_strcpy+0xc0> - 423584: 49 31 c1 xor %rax,%r9 - 423587: 4d 09 c1 or %r8,%r9 - 42358a: 49 ff c1 inc %r9 - 42358d: 75 51 jne 4235e0 <__GI_strcpy+0xc0> - 42358f: 48 89 02 mov %rax,(%rdx) - 423592: 48 83 c2 08 add $0x8,%rdx - 423596: 48 8b 06 mov (%rsi),%rax - 423599: 48 83 c6 08 add $0x8,%rsi - 42359d: 49 89 c1 mov %rax,%r9 - 4235a0: 4d 01 c1 add %r8,%r9 - 4235a3: 73 3b jae 4235e0 <__GI_strcpy+0xc0> - 4235a5: 49 31 c1 xor %rax,%r9 - 4235a8: 4d 09 c1 or %r8,%r9 - 4235ab: 49 ff c1 inc %r9 - 4235ae: 75 30 jne 4235e0 <__GI_strcpy+0xc0> - 4235b0: 48 89 02 mov %rax,(%rdx) - 4235b3: 48 83 c2 08 add $0x8,%rdx - 4235b7: 48 8b 06 mov (%rsi),%rax - 4235ba: 48 83 c6 08 add $0x8,%rsi - 4235be: 49 89 c1 mov %rax,%r9 - 4235c1: 4d 01 c1 add %r8,%r9 - 4235c4: 73 1a jae 4235e0 <__GI_strcpy+0xc0> - 4235c6: 49 31 c1 xor %rax,%r9 - 4235c9: 4d 09 c1 or %r8,%r9 - 4235cc: 49 ff c1 inc %r9 - 4235cf: 75 0f jne 4235e0 <__GI_strcpy+0xc0> - 4235d1: 48 89 02 mov %rax,(%rdx) - 4235d4: 48 83 c2 08 add $0x8,%rdx - 4235d8: e9 73 ff ff ff jmpq 423550 <__GI_strcpy+0x30> - 4235dd: 0f 1f 00 nopl (%rax) - 4235e0: 88 02 mov %al,(%rdx) - 4235e2: 84 c0 test %al,%al - 4235e4: 74 12 je 4235f8 <__GI_strcpy+0xd8> - 4235e6: 48 ff c2 inc %rdx - 4235e9: 88 22 mov %ah,(%rdx) - 4235eb: 84 e4 test %ah,%ah - 4235ed: 74 09 je 4235f8 <__GI_strcpy+0xd8> - 4235ef: 48 ff c2 inc %rdx - 4235f2: 48 c1 e8 10 shr $0x10,%rax - 4235f6: eb e8 jmp 4235e0 <__GI_strcpy+0xc0> - 4235f8: 48 89 f8 mov %rdi,%rax - 4235fb: c3 retq - 4235fc: 0f 1f 40 00 nopl 0x0(%rax) - -0000000000423600 <__strdup>: - 423600: 55 push %rbp - 423601: 53 push %rbx - 423602: 48 89 fd mov %rdi,%rbp - 423605: 48 83 ec 08 sub $0x8,%rsp - 423609: e8 42 00 00 00 callq 423650 - 42360e: 48 8d 58 01 lea 0x1(%rax),%rbx - 423612: 48 89 df mov %rbx,%rdi - 423615: e8 f6 a3 ff ff callq 41da10 <__libc_malloc> - 42361a: 48 85 c0 test %rax,%rax - 42361d: 74 19 je 423638 <__strdup+0x38> - 42361f: 48 83 c4 08 add $0x8,%rsp - 423623: 48 89 da mov %rbx,%rdx - 423626: 48 89 ee mov %rbp,%rsi - 423629: 5b pop %rbx - 42362a: 5d pop %rbp - 42362b: 48 89 c7 mov %rax,%rdi - 42362e: e9 ed 89 00 00 jmpq 42c020 - 423633: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 423638: 48 83 c4 08 add $0x8,%rsp - 42363c: 31 c0 xor %eax,%eax - 42363e: 5b pop %rbx - 42363f: 5d pop %rbp - 423640: c3 retq - 423641: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 423648: 00 00 00 - 42364b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - -0000000000423650 : - 423650: 66 0f ef c0 pxor %xmm0,%xmm0 - 423654: 66 0f ef c9 pxor %xmm1,%xmm1 - 423658: 66 0f ef d2 pxor %xmm2,%xmm2 - 42365c: 66 0f ef db pxor %xmm3,%xmm3 - 423660: 48 89 f8 mov %rdi,%rax - 423663: 48 89 f9 mov %rdi,%rcx - 423666: 48 81 e1 ff 0f 00 00 and $0xfff,%rcx - 42366d: 48 81 f9 cf 0f 00 00 cmp $0xfcf,%rcx - 423674: 77 6a ja 4236e0 - 423676: f3 0f 6f 20 movdqu (%rax),%xmm4 - 42367a: 66 0f 74 e0 pcmpeqb %xmm0,%xmm4 - 42367e: 66 0f d7 d4 pmovmskb %xmm4,%edx - 423682: 85 d2 test %edx,%edx - 423684: 74 04 je 42368a - 423686: 0f bc c2 bsf %edx,%eax - 423689: c3 retq - 42368a: 48 83 e0 f0 and $0xfffffffffffffff0,%rax - 42368e: 66 0f 74 48 10 pcmpeqb 0x10(%rax),%xmm1 - 423693: 66 0f 74 50 20 pcmpeqb 0x20(%rax),%xmm2 - 423698: 66 0f 74 58 30 pcmpeqb 0x30(%rax),%xmm3 - 42369d: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4236a1: 66 44 0f d7 c2 pmovmskb %xmm2,%r8d - 4236a6: 66 0f d7 cb pmovmskb %xmm3,%ecx - 4236aa: 48 c1 e2 10 shl $0x10,%rdx - 4236ae: 48 c1 e1 10 shl $0x10,%rcx - 4236b2: 4c 09 c1 or %r8,%rcx - 4236b5: 48 c1 e1 20 shl $0x20,%rcx - 4236b9: 48 09 ca or %rcx,%rdx - 4236bc: 48 89 f9 mov %rdi,%rcx - 4236bf: 48 31 c1 xor %rax,%rcx - 4236c2: 48 83 e0 c0 and $0xffffffffffffffc0,%rax - 4236c6: 48 d3 fa sar %cl,%rdx - 4236c9: 48 85 d2 test %rdx,%rdx - 4236cc: 0f 84 7e 00 00 00 je 423750 - 4236d2: 48 0f bc c2 bsf %rdx,%rax - 4236d6: c3 retq - 4236d7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 4236de: 00 00 - 4236e0: 48 83 e0 c0 and $0xffffffffffffffc0,%rax - 4236e4: 66 0f 74 00 pcmpeqb (%rax),%xmm0 - 4236e8: 66 0f 74 48 10 pcmpeqb 0x10(%rax),%xmm1 - 4236ed: 66 0f 74 50 20 pcmpeqb 0x20(%rax),%xmm2 - 4236f2: 66 0f 74 58 30 pcmpeqb 0x30(%rax),%xmm3 - 4236f7: 66 0f d7 f0 pmovmskb %xmm0,%esi - 4236fb: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4236ff: 66 44 0f d7 c2 pmovmskb %xmm2,%r8d - 423704: 66 0f d7 cb pmovmskb %xmm3,%ecx - 423708: 48 c1 e2 10 shl $0x10,%rdx - 42370c: 48 c1 e1 10 shl $0x10,%rcx - 423710: 48 09 f2 or %rsi,%rdx - 423713: 4c 09 c1 or %r8,%rcx - 423716: 48 c1 e1 20 shl $0x20,%rcx - 42371a: 48 09 ca or %rcx,%rdx - 42371d: 48 89 f9 mov %rdi,%rcx - 423720: 48 31 c1 xor %rax,%rcx - 423723: 48 83 e0 c0 and $0xffffffffffffffc0,%rax - 423727: 48 d3 fa sar %cl,%rdx - 42372a: 48 85 d2 test %rdx,%rdx - 42372d: 74 11 je 423740 - 42372f: 48 0f bc c2 bsf %rdx,%rax - 423733: c3 retq - 423734: 66 90 xchg %ax,%ax - 423736: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42373d: 00 00 00 - 423740: 66 0f ef c9 pxor %xmm1,%xmm1 - 423744: 66 0f ef d2 pxor %xmm2,%xmm2 - 423748: 66 0f ef db pxor %xmm3,%xmm3 - 42374c: 0f 1f 40 00 nopl 0x0(%rax) - 423750: 66 0f 6f 40 40 movdqa 0x40(%rax),%xmm0 - 423755: 66 0f da 40 50 pminub 0x50(%rax),%xmm0 - 42375a: 66 0f da 40 60 pminub 0x60(%rax),%xmm0 - 42375f: 66 0f da 40 70 pminub 0x70(%rax),%xmm0 - 423764: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 423768: 66 0f d7 d0 pmovmskb %xmm0,%edx - 42376c: 85 d2 test %edx,%edx - 42376e: 75 30 jne 4237a0 - 423770: 48 83 e8 80 sub $0xffffffffffffff80,%rax - 423774: 66 0f 6f 00 movdqa (%rax),%xmm0 - 423778: 66 0f da 40 10 pminub 0x10(%rax),%xmm0 - 42377d: 66 0f da 40 20 pminub 0x20(%rax),%xmm0 - 423782: 66 0f da 40 30 pminub 0x30(%rax),%xmm0 - 423787: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 42378b: 66 0f d7 d0 pmovmskb %xmm0,%edx - 42378f: 85 d2 test %edx,%edx - 423791: 75 11 jne 4237a4 - 423793: eb bb jmp 423750 - 423795: 90 nop - 423796: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42379d: 00 00 00 - 4237a0: 48 83 c0 40 add $0x40,%rax - 4237a4: 66 0f ef c0 pxor %xmm0,%xmm0 - 4237a8: 66 0f 74 00 pcmpeqb (%rax),%xmm0 - 4237ac: 66 0f 74 48 10 pcmpeqb 0x10(%rax),%xmm1 - 4237b1: 66 0f 74 50 20 pcmpeqb 0x20(%rax),%xmm2 - 4237b6: 66 0f 74 58 30 pcmpeqb 0x30(%rax),%xmm3 - 4237bb: 66 0f d7 f0 pmovmskb %xmm0,%esi - 4237bf: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4237c3: 66 44 0f d7 c2 pmovmskb %xmm2,%r8d - 4237c8: 66 0f d7 cb pmovmskb %xmm3,%ecx - 4237cc: 48 c1 e2 10 shl $0x10,%rdx - 4237d0: 48 c1 e1 10 shl $0x10,%rcx - 4237d4: 48 09 f2 or %rsi,%rdx - 4237d7: 4c 09 c1 or %r8,%rcx - 4237da: 48 c1 e1 20 shl $0x20,%rcx - 4237de: 48 09 ca or %rcx,%rdx - 4237e1: 48 0f bc d2 bsf %rdx,%rdx - 4237e5: 48 01 d0 add %rdx,%rax - 4237e8: 48 29 f8 sub %rdi,%rax - 4237eb: c3 retq - 4237ec: 0f 1f 40 00 nopl 0x0(%rax) - -00000000004237f0 : - 4237f0: 48 85 d2 test %rdx,%rdx - 4237f3: 0f 84 2b 18 00 00 je 425024 - 4237f9: 48 83 fa 01 cmp $0x1,%rdx - 4237fd: 0f 84 2d 18 00 00 je 425030 - 423803: 49 89 d3 mov %rdx,%r11 - 423806: 89 f1 mov %esi,%ecx - 423808: 89 f8 mov %edi,%eax - 42380a: 48 83 e1 3f and $0x3f,%rcx - 42380e: 48 83 e0 3f and $0x3f,%rax - 423812: 83 f9 30 cmp $0x30,%ecx - 423815: 77 49 ja 423860 - 423817: 83 f8 30 cmp $0x30,%eax - 42381a: 77 44 ja 423860 - 42381c: 66 0f 12 0f movlpd (%rdi),%xmm1 - 423820: 66 0f 12 16 movlpd (%rsi),%xmm2 - 423824: 66 0f 16 4f 08 movhpd 0x8(%rdi),%xmm1 - 423829: 66 0f 16 56 08 movhpd 0x8(%rsi),%xmm2 - 42382e: 66 0f ef c0 pxor %xmm0,%xmm0 - 423832: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 423836: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42383a: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42383e: 66 0f d7 d1 pmovmskb %xmm1,%edx - 423842: 81 ea ff ff 00 00 sub $0xffff,%edx - 423848: 0f 85 c2 17 00 00 jne 425010 - 42384e: 49 83 eb 10 sub $0x10,%r11 - 423852: 0f 86 cc 17 00 00 jbe 425024 - 423858: 48 83 c6 10 add $0x10,%rsi - 42385c: 48 83 c7 10 add $0x10,%rdi - 423860: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi - 423864: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi - 423868: ba ff ff 00 00 mov $0xffff,%edx - 42386d: 45 31 c0 xor %r8d,%r8d - 423870: 83 e1 0f and $0xf,%ecx - 423873: 83 e0 0f and $0xf,%eax - 423876: 39 c1 cmp %eax,%ecx - 423878: 74 26 je 4238a0 - 42387a: 77 07 ja 423883 - 42387c: 41 89 d0 mov %edx,%r8d - 42387f: 91 xchg %eax,%ecx - 423880: 48 87 f7 xchg %rsi,%rdi - 423883: 4c 8d 48 0f lea 0xf(%rax),%r9 - 423887: 49 29 c9 sub %rcx,%r9 - 42388a: 4c 8d 15 df f7 07 00 lea 0x7f7df(%rip),%r10 # 4a3070 <__func__.10972+0xb0> - 423891: 4f 63 0c 8a movslq (%r10,%r9,4),%r9 - 423895: 4f 8d 14 0a lea (%r10,%r9,1),%r10 - 423899: 41 ff e2 jmpq *%r10 - 42389c: 0f 1f 40 00 nopl 0x0(%rax) - 4238a0: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 4238a4: 66 0f ef c0 pxor %xmm0,%xmm0 - 4238a8: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4238ac: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 - 4238b0: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4238b4: 66 44 0f d7 c9 pmovmskb %xmm1,%r9d - 4238b9: d3 ea shr %cl,%edx - 4238bb: 41 d3 e9 shr %cl,%r9d - 4238be: 44 29 ca sub %r9d,%edx - 4238c1: 0f 85 2e 17 00 00 jne 424ff5 - 4238c7: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 - 4238cc: 4d 39 cb cmp %r9,%r11 - 4238cf: 0f 82 4f 17 00 00 jb 425024 - 4238d5: 4d 85 c9 test %r9,%r9 - 4238d8: 0f 84 46 17 00 00 je 425024 - 4238de: 4d 89 cb mov %r9,%r11 - 4238e1: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 4238e8: 49 c7 c1 10 00 00 00 mov $0x10,%r9 - 4238ef: 66 0f ef c0 pxor %xmm0,%xmm0 - 4238f3: 0f 1f 00 nopl (%rax) - 4238f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4238fd: 00 00 00 - 423900: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 423905: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42390a: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42390e: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 423912: 66 0f f8 c8 psubb %xmm0,%xmm1 - 423916: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42391a: 81 ea ff ff 00 00 sub $0xffff,%edx - 423920: 0f 85 ca 16 00 00 jne 424ff0 - 423926: 49 83 eb 10 sub $0x10,%r11 - 42392a: 0f 86 f4 16 00 00 jbe 425024 - 423930: 48 83 c1 10 add $0x10,%rcx - 423934: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 423939: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42393e: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 423942: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 423946: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42394a: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42394e: 81 ea ff ff 00 00 sub $0xffff,%edx - 423954: 0f 85 96 16 00 00 jne 424ff0 - 42395a: 49 83 eb 10 sub $0x10,%r11 - 42395e: 0f 86 c0 16 00 00 jbe 425024 - 423964: 48 83 c1 10 add $0x10,%rcx - 423968: eb 96 jmp 423900 - 42396a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 423970: 66 0f ef c0 pxor %xmm0,%xmm0 - 423974: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 423978: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42397c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 423980: 66 0f 73 fa 0f pslldq $0xf,%xmm2 - 423985: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 423989: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42398d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 423992: d3 ea shr %cl,%edx - 423994: 41 d3 e9 shr %cl,%r9d - 423997: 44 29 ca sub %r9d,%edx - 42399a: 0f 85 55 16 00 00 jne 424ff5 - 4239a0: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 4239a4: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 - 4239a9: 4d 39 cb cmp %r9,%r11 - 4239ac: 0f 82 72 16 00 00 jb 425024 - 4239b2: 4d 85 c9 test %r9,%r9 - 4239b5: 0f 84 69 16 00 00 je 425024 - 4239bb: 4d 89 cb mov %r9,%r11 - 4239be: 66 0f ef c0 pxor %xmm0,%xmm0 - 4239c2: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 4239c9: 41 b9 01 00 00 00 mov $0x1,%r9d - 4239cf: 4c 8d 57 01 lea 0x1(%rdi),%r10 - 4239d3: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 4239da: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 4239e1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4239e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4239ed: 00 00 00 - 4239f0: 49 83 c2 10 add $0x10,%r10 - 4239f4: 0f 8f a6 00 00 00 jg 423aa0 - 4239fa: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4239ff: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 423a04: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 423a08: 66 0f 73 db 01 psrldq $0x1,%xmm3 - 423a0d: 66 0f 73 fa 0f pslldq $0xf,%xmm2 - 423a12: 66 0f eb d3 por %xmm3,%xmm2 - 423a16: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 423a1a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 423a1e: 66 0f f8 c8 psubb %xmm0,%xmm1 - 423a22: 66 0f d7 d1 pmovmskb %xmm1,%edx - 423a26: 81 ea ff ff 00 00 sub $0xffff,%edx - 423a2c: 0f 85 be 15 00 00 jne 424ff0 - 423a32: 49 83 eb 10 sub $0x10,%r11 - 423a36: 0f 86 e8 15 00 00 jbe 425024 - 423a3c: 48 83 c1 10 add $0x10,%rcx - 423a40: 66 0f 6f dc movdqa %xmm4,%xmm3 - 423a44: 49 83 c2 10 add $0x10,%r10 - 423a48: 7f 56 jg 423aa0 - 423a4a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 423a4f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 423a54: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 423a58: 66 0f 73 db 01 psrldq $0x1,%xmm3 - 423a5d: 66 0f 73 fa 0f pslldq $0xf,%xmm2 - 423a62: 66 0f eb d3 por %xmm3,%xmm2 - 423a66: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 423a6a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 423a6e: 66 0f f8 c8 psubb %xmm0,%xmm1 - 423a72: 66 0f d7 d1 pmovmskb %xmm1,%edx - 423a76: 81 ea ff ff 00 00 sub $0xffff,%edx - 423a7c: 0f 85 6e 15 00 00 jne 424ff0 - 423a82: 49 83 eb 10 sub $0x10,%r11 - 423a86: 0f 86 98 15 00 00 jbe 425024 - 423a8c: 48 83 c1 10 add $0x10,%rcx - 423a90: 66 0f 6f dc movdqa %xmm4,%xmm3 - 423a94: e9 57 ff ff ff jmpq 4239f0 - 423a99: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 423aa0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 423aa4: 66 0f d7 d0 pmovmskb %xmm0,%edx - 423aa8: f7 c2 fe ff 00 00 test $0xfffe,%edx - 423aae: 75 20 jne 423ad0 - 423ab0: 49 83 fb 0f cmp $0xf,%r11 - 423ab4: 76 1a jbe 423ad0 - 423ab6: 66 0f ef c0 pxor %xmm0,%xmm0 - 423aba: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 423ac1: e9 34 ff ff ff jmpq 4239fa - 423ac6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 423acd: 00 00 00 - 423ad0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 423ad5: 66 0f 73 d8 01 psrldq $0x1,%xmm0 - 423ada: 66 0f 73 db 01 psrldq $0x1,%xmm3 - 423adf: e9 fc 14 00 00 jmpq 424fe0 - 423ae4: 66 90 xchg %ax,%ax - 423ae6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 423aed: 00 00 00 - 423af0: 66 0f ef c0 pxor %xmm0,%xmm0 - 423af4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 423af8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 423afc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 423b00: 66 0f 73 fa 0e pslldq $0xe,%xmm2 - 423b05: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 423b09: 66 0f f8 d0 psubb %xmm0,%xmm2 - 423b0d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 423b12: d3 ea shr %cl,%edx - 423b14: 41 d3 e9 shr %cl,%r9d - 423b17: 44 29 ca sub %r9d,%edx - 423b1a: 0f 85 d5 14 00 00 jne 424ff5 - 423b20: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 423b24: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 - 423b29: 4d 39 cb cmp %r9,%r11 - 423b2c: 0f 82 f2 14 00 00 jb 425024 - 423b32: 4d 85 c9 test %r9,%r9 - 423b35: 0f 84 e9 14 00 00 je 425024 - 423b3b: 4d 89 cb mov %r9,%r11 - 423b3e: 66 0f ef c0 pxor %xmm0,%xmm0 - 423b42: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 423b49: 41 b9 02 00 00 00 mov $0x2,%r9d - 423b4f: 4c 8d 57 02 lea 0x2(%rdi),%r10 - 423b53: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 423b5a: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 423b61: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 423b66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 423b6d: 00 00 00 - 423b70: 49 83 c2 10 add $0x10,%r10 - 423b74: 0f 8f a6 00 00 00 jg 423c20 - 423b7a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 423b7f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 423b84: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 423b88: 66 0f 73 db 02 psrldq $0x2,%xmm3 - 423b8d: 66 0f 73 fa 0e pslldq $0xe,%xmm2 - 423b92: 66 0f eb d3 por %xmm3,%xmm2 - 423b96: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 423b9a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 423b9e: 66 0f f8 c8 psubb %xmm0,%xmm1 - 423ba2: 66 0f d7 d1 pmovmskb %xmm1,%edx - 423ba6: 81 ea ff ff 00 00 sub $0xffff,%edx - 423bac: 0f 85 3e 14 00 00 jne 424ff0 - 423bb2: 49 83 eb 10 sub $0x10,%r11 - 423bb6: 0f 86 68 14 00 00 jbe 425024 - 423bbc: 48 83 c1 10 add $0x10,%rcx - 423bc0: 66 0f 6f dc movdqa %xmm4,%xmm3 - 423bc4: 49 83 c2 10 add $0x10,%r10 - 423bc8: 7f 56 jg 423c20 - 423bca: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 423bcf: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 423bd4: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 423bd8: 66 0f 73 db 02 psrldq $0x2,%xmm3 - 423bdd: 66 0f 73 fa 0e pslldq $0xe,%xmm2 - 423be2: 66 0f eb d3 por %xmm3,%xmm2 - 423be6: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 423bea: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 423bee: 66 0f f8 c8 psubb %xmm0,%xmm1 - 423bf2: 66 0f d7 d1 pmovmskb %xmm1,%edx - 423bf6: 81 ea ff ff 00 00 sub $0xffff,%edx - 423bfc: 0f 85 ee 13 00 00 jne 424ff0 - 423c02: 49 83 eb 10 sub $0x10,%r11 - 423c06: 0f 86 18 14 00 00 jbe 425024 - 423c0c: 48 83 c1 10 add $0x10,%rcx - 423c10: 66 0f 6f dc movdqa %xmm4,%xmm3 - 423c14: e9 57 ff ff ff jmpq 423b70 - 423c19: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 423c20: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 423c24: 66 0f d7 d0 pmovmskb %xmm0,%edx - 423c28: f7 c2 fc ff 00 00 test $0xfffc,%edx - 423c2e: 75 20 jne 423c50 - 423c30: 49 83 fb 0e cmp $0xe,%r11 - 423c34: 76 1a jbe 423c50 - 423c36: 66 0f ef c0 pxor %xmm0,%xmm0 - 423c3a: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 423c41: e9 34 ff ff ff jmpq 423b7a - 423c46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 423c4d: 00 00 00 - 423c50: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 423c55: 66 0f 73 d8 02 psrldq $0x2,%xmm0 - 423c5a: 66 0f 73 db 02 psrldq $0x2,%xmm3 - 423c5f: e9 7c 13 00 00 jmpq 424fe0 - 423c64: 66 90 xchg %ax,%ax - 423c66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 423c6d: 00 00 00 - 423c70: 66 0f ef c0 pxor %xmm0,%xmm0 - 423c74: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 423c78: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 423c7c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 423c80: 66 0f 73 fa 0d pslldq $0xd,%xmm2 - 423c85: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 423c89: 66 0f f8 d0 psubb %xmm0,%xmm2 - 423c8d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 423c92: d3 ea shr %cl,%edx - 423c94: 41 d3 e9 shr %cl,%r9d - 423c97: 44 29 ca sub %r9d,%edx - 423c9a: 0f 85 55 13 00 00 jne 424ff5 - 423ca0: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 423ca4: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 - 423ca9: 4d 39 cb cmp %r9,%r11 - 423cac: 0f 82 72 13 00 00 jb 425024 - 423cb2: 4d 85 c9 test %r9,%r9 - 423cb5: 0f 84 69 13 00 00 je 425024 - 423cbb: 4d 89 cb mov %r9,%r11 - 423cbe: 66 0f ef c0 pxor %xmm0,%xmm0 - 423cc2: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 423cc9: 41 b9 03 00 00 00 mov $0x3,%r9d - 423ccf: 4c 8d 57 03 lea 0x3(%rdi),%r10 - 423cd3: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 423cda: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 423ce1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 423ce6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 423ced: 00 00 00 - 423cf0: 49 83 c2 10 add $0x10,%r10 - 423cf4: 0f 8f a6 00 00 00 jg 423da0 - 423cfa: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 423cff: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 423d04: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 423d08: 66 0f 73 db 03 psrldq $0x3,%xmm3 - 423d0d: 66 0f 73 fa 0d pslldq $0xd,%xmm2 - 423d12: 66 0f eb d3 por %xmm3,%xmm2 - 423d16: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 423d1a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 423d1e: 66 0f f8 c8 psubb %xmm0,%xmm1 - 423d22: 66 0f d7 d1 pmovmskb %xmm1,%edx - 423d26: 81 ea ff ff 00 00 sub $0xffff,%edx - 423d2c: 0f 85 be 12 00 00 jne 424ff0 - 423d32: 49 83 eb 10 sub $0x10,%r11 - 423d36: 0f 86 e8 12 00 00 jbe 425024 - 423d3c: 48 83 c1 10 add $0x10,%rcx - 423d40: 66 0f 6f dc movdqa %xmm4,%xmm3 - 423d44: 49 83 c2 10 add $0x10,%r10 - 423d48: 7f 56 jg 423da0 - 423d4a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 423d4f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 423d54: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 423d58: 66 0f 73 db 03 psrldq $0x3,%xmm3 - 423d5d: 66 0f 73 fa 0d pslldq $0xd,%xmm2 - 423d62: 66 0f eb d3 por %xmm3,%xmm2 - 423d66: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 423d6a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 423d6e: 66 0f f8 c8 psubb %xmm0,%xmm1 - 423d72: 66 0f d7 d1 pmovmskb %xmm1,%edx - 423d76: 81 ea ff ff 00 00 sub $0xffff,%edx - 423d7c: 0f 85 6e 12 00 00 jne 424ff0 - 423d82: 49 83 eb 10 sub $0x10,%r11 - 423d86: 0f 86 98 12 00 00 jbe 425024 - 423d8c: 48 83 c1 10 add $0x10,%rcx - 423d90: 66 0f 6f dc movdqa %xmm4,%xmm3 - 423d94: e9 57 ff ff ff jmpq 423cf0 - 423d99: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 423da0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 423da4: 66 0f d7 d0 pmovmskb %xmm0,%edx - 423da8: f7 c2 f8 ff 00 00 test $0xfff8,%edx - 423dae: 75 20 jne 423dd0 - 423db0: 49 83 fb 0d cmp $0xd,%r11 - 423db4: 76 1a jbe 423dd0 - 423db6: 66 0f ef c0 pxor %xmm0,%xmm0 - 423dba: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 423dc1: e9 34 ff ff ff jmpq 423cfa - 423dc6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 423dcd: 00 00 00 - 423dd0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 423dd5: 66 0f 73 d8 03 psrldq $0x3,%xmm0 - 423dda: 66 0f 73 db 03 psrldq $0x3,%xmm3 - 423ddf: e9 fc 11 00 00 jmpq 424fe0 - 423de4: 66 90 xchg %ax,%ax - 423de6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 423ded: 00 00 00 - 423df0: 66 0f ef c0 pxor %xmm0,%xmm0 - 423df4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 423df8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 423dfc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 423e00: 66 0f 73 fa 0c pslldq $0xc,%xmm2 - 423e05: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 423e09: 66 0f f8 d0 psubb %xmm0,%xmm2 - 423e0d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 423e12: d3 ea shr %cl,%edx - 423e14: 41 d3 e9 shr %cl,%r9d - 423e17: 44 29 ca sub %r9d,%edx - 423e1a: 0f 85 d5 11 00 00 jne 424ff5 - 423e20: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 423e24: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 - 423e29: 4d 39 cb cmp %r9,%r11 - 423e2c: 0f 82 f2 11 00 00 jb 425024 - 423e32: 4d 85 c9 test %r9,%r9 - 423e35: 0f 84 e9 11 00 00 je 425024 - 423e3b: 4d 89 cb mov %r9,%r11 - 423e3e: 66 0f ef c0 pxor %xmm0,%xmm0 - 423e42: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 423e49: 41 b9 04 00 00 00 mov $0x4,%r9d - 423e4f: 4c 8d 57 04 lea 0x4(%rdi),%r10 - 423e53: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 423e5a: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 423e61: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 423e66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 423e6d: 00 00 00 - 423e70: 49 83 c2 10 add $0x10,%r10 - 423e74: 0f 8f a6 00 00 00 jg 423f20 - 423e7a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 423e7f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 423e84: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 423e88: 66 0f 73 db 04 psrldq $0x4,%xmm3 - 423e8d: 66 0f 73 fa 0c pslldq $0xc,%xmm2 - 423e92: 66 0f eb d3 por %xmm3,%xmm2 - 423e96: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 423e9a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 423e9e: 66 0f f8 c8 psubb %xmm0,%xmm1 - 423ea2: 66 0f d7 d1 pmovmskb %xmm1,%edx - 423ea6: 81 ea ff ff 00 00 sub $0xffff,%edx - 423eac: 0f 85 3e 11 00 00 jne 424ff0 - 423eb2: 49 83 eb 10 sub $0x10,%r11 - 423eb6: 0f 86 68 11 00 00 jbe 425024 - 423ebc: 48 83 c1 10 add $0x10,%rcx - 423ec0: 66 0f 6f dc movdqa %xmm4,%xmm3 - 423ec4: 49 83 c2 10 add $0x10,%r10 - 423ec8: 7f 56 jg 423f20 - 423eca: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 423ecf: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 423ed4: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 423ed8: 66 0f 73 db 04 psrldq $0x4,%xmm3 - 423edd: 66 0f 73 fa 0c pslldq $0xc,%xmm2 - 423ee2: 66 0f eb d3 por %xmm3,%xmm2 - 423ee6: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 423eea: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 423eee: 66 0f f8 c8 psubb %xmm0,%xmm1 - 423ef2: 66 0f d7 d1 pmovmskb %xmm1,%edx - 423ef6: 81 ea ff ff 00 00 sub $0xffff,%edx - 423efc: 0f 85 ee 10 00 00 jne 424ff0 - 423f02: 49 83 eb 10 sub $0x10,%r11 - 423f06: 0f 86 18 11 00 00 jbe 425024 - 423f0c: 48 83 c1 10 add $0x10,%rcx - 423f10: 66 0f 6f dc movdqa %xmm4,%xmm3 - 423f14: e9 57 ff ff ff jmpq 423e70 - 423f19: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 423f20: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 423f24: 66 0f d7 d0 pmovmskb %xmm0,%edx - 423f28: f7 c2 f0 ff 00 00 test $0xfff0,%edx - 423f2e: 75 20 jne 423f50 - 423f30: 49 83 fb 0c cmp $0xc,%r11 - 423f34: 76 1a jbe 423f50 - 423f36: 66 0f ef c0 pxor %xmm0,%xmm0 - 423f3a: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 423f41: e9 34 ff ff ff jmpq 423e7a - 423f46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 423f4d: 00 00 00 - 423f50: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 423f55: 66 0f 73 d8 04 psrldq $0x4,%xmm0 - 423f5a: 66 0f 73 db 04 psrldq $0x4,%xmm3 - 423f5f: e9 7c 10 00 00 jmpq 424fe0 - 423f64: 66 90 xchg %ax,%ax - 423f66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 423f6d: 00 00 00 - 423f70: 66 0f ef c0 pxor %xmm0,%xmm0 - 423f74: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 423f78: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 423f7c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 423f80: 66 0f 73 fa 0b pslldq $0xb,%xmm2 - 423f85: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 423f89: 66 0f f8 d0 psubb %xmm0,%xmm2 - 423f8d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 423f92: d3 ea shr %cl,%edx - 423f94: 41 d3 e9 shr %cl,%r9d - 423f97: 44 29 ca sub %r9d,%edx - 423f9a: 0f 85 55 10 00 00 jne 424ff5 - 423fa0: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 423fa4: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 - 423fa9: 4d 39 cb cmp %r9,%r11 - 423fac: 0f 82 72 10 00 00 jb 425024 - 423fb2: 4d 85 c9 test %r9,%r9 - 423fb5: 0f 84 69 10 00 00 je 425024 - 423fbb: 4d 89 cb mov %r9,%r11 - 423fbe: 66 0f ef c0 pxor %xmm0,%xmm0 - 423fc2: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 423fc9: 41 b9 05 00 00 00 mov $0x5,%r9d - 423fcf: 4c 8d 57 05 lea 0x5(%rdi),%r10 - 423fd3: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 423fda: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 423fe1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 423fe6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 423fed: 00 00 00 - 423ff0: 49 83 c2 10 add $0x10,%r10 - 423ff4: 0f 8f a6 00 00 00 jg 4240a0 - 423ffa: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 423fff: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 424004: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 424008: 66 0f 73 db 05 psrldq $0x5,%xmm3 - 42400d: 66 0f 73 fa 0b pslldq $0xb,%xmm2 - 424012: 66 0f eb d3 por %xmm3,%xmm2 - 424016: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42401a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42401e: 66 0f f8 c8 psubb %xmm0,%xmm1 - 424022: 66 0f d7 d1 pmovmskb %xmm1,%edx - 424026: 81 ea ff ff 00 00 sub $0xffff,%edx - 42402c: 0f 85 be 0f 00 00 jne 424ff0 - 424032: 49 83 eb 10 sub $0x10,%r11 - 424036: 0f 86 e8 0f 00 00 jbe 425024 - 42403c: 48 83 c1 10 add $0x10,%rcx - 424040: 66 0f 6f dc movdqa %xmm4,%xmm3 - 424044: 49 83 c2 10 add $0x10,%r10 - 424048: 7f 56 jg 4240a0 - 42404a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42404f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 424054: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 424058: 66 0f 73 db 05 psrldq $0x5,%xmm3 - 42405d: 66 0f 73 fa 0b pslldq $0xb,%xmm2 - 424062: 66 0f eb d3 por %xmm3,%xmm2 - 424066: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42406a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42406e: 66 0f f8 c8 psubb %xmm0,%xmm1 - 424072: 66 0f d7 d1 pmovmskb %xmm1,%edx - 424076: 81 ea ff ff 00 00 sub $0xffff,%edx - 42407c: 0f 85 6e 0f 00 00 jne 424ff0 - 424082: 49 83 eb 10 sub $0x10,%r11 - 424086: 0f 86 98 0f 00 00 jbe 425024 - 42408c: 48 83 c1 10 add $0x10,%rcx - 424090: 66 0f 6f dc movdqa %xmm4,%xmm3 - 424094: e9 57 ff ff ff jmpq 423ff0 - 424099: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4240a0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 4240a4: 66 0f d7 d0 pmovmskb %xmm0,%edx - 4240a8: f7 c2 e0 ff 00 00 test $0xffe0,%edx - 4240ae: 75 20 jne 4240d0 - 4240b0: 49 83 fb 0b cmp $0xb,%r11 - 4240b4: 76 1a jbe 4240d0 - 4240b6: 66 0f ef c0 pxor %xmm0,%xmm0 - 4240ba: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 4240c1: e9 34 ff ff ff jmpq 423ffa - 4240c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4240cd: 00 00 00 - 4240d0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4240d5: 66 0f 73 d8 05 psrldq $0x5,%xmm0 - 4240da: 66 0f 73 db 05 psrldq $0x5,%xmm3 - 4240df: e9 fc 0e 00 00 jmpq 424fe0 - 4240e4: 66 90 xchg %ax,%ax - 4240e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4240ed: 00 00 00 - 4240f0: 66 0f ef c0 pxor %xmm0,%xmm0 - 4240f4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 4240f8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 4240fc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 424100: 66 0f 73 fa 0a pslldq $0xa,%xmm2 - 424105: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 424109: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42410d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 424112: d3 ea shr %cl,%edx - 424114: 41 d3 e9 shr %cl,%r9d - 424117: 44 29 ca sub %r9d,%edx - 42411a: 0f 85 d5 0e 00 00 jne 424ff5 - 424120: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 424124: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 - 424129: 4d 39 cb cmp %r9,%r11 - 42412c: 0f 82 f2 0e 00 00 jb 425024 - 424132: 4d 85 c9 test %r9,%r9 - 424135: 0f 84 e9 0e 00 00 je 425024 - 42413b: 4d 89 cb mov %r9,%r11 - 42413e: 66 0f ef c0 pxor %xmm0,%xmm0 - 424142: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 424149: 41 b9 06 00 00 00 mov $0x6,%r9d - 42414f: 4c 8d 57 06 lea 0x6(%rdi),%r10 - 424153: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42415a: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 424161: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 424166: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42416d: 00 00 00 - 424170: 49 83 c2 10 add $0x10,%r10 - 424174: 0f 8f a6 00 00 00 jg 424220 - 42417a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42417f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 424184: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 424188: 66 0f 73 db 06 psrldq $0x6,%xmm3 - 42418d: 66 0f 73 fa 0a pslldq $0xa,%xmm2 - 424192: 66 0f eb d3 por %xmm3,%xmm2 - 424196: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42419a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42419e: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4241a2: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4241a6: 81 ea ff ff 00 00 sub $0xffff,%edx - 4241ac: 0f 85 3e 0e 00 00 jne 424ff0 - 4241b2: 49 83 eb 10 sub $0x10,%r11 - 4241b6: 0f 86 68 0e 00 00 jbe 425024 - 4241bc: 48 83 c1 10 add $0x10,%rcx - 4241c0: 66 0f 6f dc movdqa %xmm4,%xmm3 - 4241c4: 49 83 c2 10 add $0x10,%r10 - 4241c8: 7f 56 jg 424220 - 4241ca: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4241cf: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4241d4: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 4241d8: 66 0f 73 db 06 psrldq $0x6,%xmm3 - 4241dd: 66 0f 73 fa 0a pslldq $0xa,%xmm2 - 4241e2: 66 0f eb d3 por %xmm3,%xmm2 - 4241e6: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4241ea: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 4241ee: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4241f2: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4241f6: 81 ea ff ff 00 00 sub $0xffff,%edx - 4241fc: 0f 85 ee 0d 00 00 jne 424ff0 - 424202: 49 83 eb 10 sub $0x10,%r11 - 424206: 0f 86 18 0e 00 00 jbe 425024 - 42420c: 48 83 c1 10 add $0x10,%rcx - 424210: 66 0f 6f dc movdqa %xmm4,%xmm3 - 424214: e9 57 ff ff ff jmpq 424170 - 424219: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 424220: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 424224: 66 0f d7 d0 pmovmskb %xmm0,%edx - 424228: f7 c2 c0 ff 00 00 test $0xffc0,%edx - 42422e: 75 20 jne 424250 - 424230: 49 83 fb 0a cmp $0xa,%r11 - 424234: 76 1a jbe 424250 - 424236: 66 0f ef c0 pxor %xmm0,%xmm0 - 42423a: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 424241: e9 34 ff ff ff jmpq 42417a - 424246: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42424d: 00 00 00 - 424250: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 424255: 66 0f 73 d8 06 psrldq $0x6,%xmm0 - 42425a: 66 0f 73 db 06 psrldq $0x6,%xmm3 - 42425f: e9 7c 0d 00 00 jmpq 424fe0 - 424264: 66 90 xchg %ax,%ax - 424266: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42426d: 00 00 00 - 424270: 66 0f ef c0 pxor %xmm0,%xmm0 - 424274: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 424278: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42427c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 424280: 66 0f 73 fa 09 pslldq $0x9,%xmm2 - 424285: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 424289: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42428d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 424292: d3 ea shr %cl,%edx - 424294: 41 d3 e9 shr %cl,%r9d - 424297: 44 29 ca sub %r9d,%edx - 42429a: 0f 85 55 0d 00 00 jne 424ff5 - 4242a0: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 4242a4: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 - 4242a9: 4d 39 cb cmp %r9,%r11 - 4242ac: 0f 82 72 0d 00 00 jb 425024 - 4242b2: 4d 85 c9 test %r9,%r9 - 4242b5: 0f 84 69 0d 00 00 je 425024 - 4242bb: 4d 89 cb mov %r9,%r11 - 4242be: 66 0f ef c0 pxor %xmm0,%xmm0 - 4242c2: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 4242c9: 41 b9 07 00 00 00 mov $0x7,%r9d - 4242cf: 4c 8d 57 07 lea 0x7(%rdi),%r10 - 4242d3: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 4242da: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 4242e1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4242e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4242ed: 00 00 00 - 4242f0: 49 83 c2 10 add $0x10,%r10 - 4242f4: 0f 8f a6 00 00 00 jg 4243a0 - 4242fa: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4242ff: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 424304: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 424308: 66 0f 73 db 07 psrldq $0x7,%xmm3 - 42430d: 66 0f 73 fa 09 pslldq $0x9,%xmm2 - 424312: 66 0f eb d3 por %xmm3,%xmm2 - 424316: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42431a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42431e: 66 0f f8 c8 psubb %xmm0,%xmm1 - 424322: 66 0f d7 d1 pmovmskb %xmm1,%edx - 424326: 81 ea ff ff 00 00 sub $0xffff,%edx - 42432c: 0f 85 be 0c 00 00 jne 424ff0 - 424332: 49 83 eb 10 sub $0x10,%r11 - 424336: 0f 86 e8 0c 00 00 jbe 425024 - 42433c: 48 83 c1 10 add $0x10,%rcx - 424340: 66 0f 6f dc movdqa %xmm4,%xmm3 - 424344: 49 83 c2 10 add $0x10,%r10 - 424348: 7f 56 jg 4243a0 - 42434a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42434f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 424354: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 424358: 66 0f 73 db 07 psrldq $0x7,%xmm3 - 42435d: 66 0f 73 fa 09 pslldq $0x9,%xmm2 - 424362: 66 0f eb d3 por %xmm3,%xmm2 - 424366: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42436a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42436e: 66 0f f8 c8 psubb %xmm0,%xmm1 - 424372: 66 0f d7 d1 pmovmskb %xmm1,%edx - 424376: 81 ea ff ff 00 00 sub $0xffff,%edx - 42437c: 0f 85 6e 0c 00 00 jne 424ff0 - 424382: 49 83 eb 10 sub $0x10,%r11 - 424386: 0f 86 98 0c 00 00 jbe 425024 - 42438c: 48 83 c1 10 add $0x10,%rcx - 424390: 66 0f 6f dc movdqa %xmm4,%xmm3 - 424394: e9 57 ff ff ff jmpq 4242f0 - 424399: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4243a0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 4243a4: 66 0f d7 d0 pmovmskb %xmm0,%edx - 4243a8: f7 c2 80 ff 00 00 test $0xff80,%edx - 4243ae: 75 20 jne 4243d0 - 4243b0: 49 83 fb 09 cmp $0x9,%r11 - 4243b4: 76 1a jbe 4243d0 - 4243b6: 66 0f ef c0 pxor %xmm0,%xmm0 - 4243ba: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 4243c1: e9 34 ff ff ff jmpq 4242fa - 4243c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4243cd: 00 00 00 - 4243d0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4243d5: 66 0f 73 d8 07 psrldq $0x7,%xmm0 - 4243da: 66 0f 73 db 07 psrldq $0x7,%xmm3 - 4243df: e9 fc 0b 00 00 jmpq 424fe0 - 4243e4: 66 90 xchg %ax,%ax - 4243e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4243ed: 00 00 00 - 4243f0: 66 0f ef c0 pxor %xmm0,%xmm0 - 4243f4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 4243f8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 4243fc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 424400: 66 0f 73 fa 08 pslldq $0x8,%xmm2 - 424405: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 424409: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42440d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 424412: d3 ea shr %cl,%edx - 424414: 41 d3 e9 shr %cl,%r9d - 424417: 44 29 ca sub %r9d,%edx - 42441a: 0f 85 d5 0b 00 00 jne 424ff5 - 424420: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 424424: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 - 424429: 4d 39 cb cmp %r9,%r11 - 42442c: 0f 82 f2 0b 00 00 jb 425024 - 424432: 4d 85 c9 test %r9,%r9 - 424435: 0f 84 e9 0b 00 00 je 425024 - 42443b: 4d 89 cb mov %r9,%r11 - 42443e: 66 0f ef c0 pxor %xmm0,%xmm0 - 424442: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 424449: 41 b9 08 00 00 00 mov $0x8,%r9d - 42444f: 4c 8d 57 08 lea 0x8(%rdi),%r10 - 424453: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42445a: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 424461: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 424466: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42446d: 00 00 00 - 424470: 49 83 c2 10 add $0x10,%r10 - 424474: 0f 8f a6 00 00 00 jg 424520 - 42447a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42447f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 424484: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 424488: 66 0f 73 db 08 psrldq $0x8,%xmm3 - 42448d: 66 0f 73 fa 08 pslldq $0x8,%xmm2 - 424492: 66 0f eb d3 por %xmm3,%xmm2 - 424496: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42449a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42449e: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4244a2: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4244a6: 81 ea ff ff 00 00 sub $0xffff,%edx - 4244ac: 0f 85 3e 0b 00 00 jne 424ff0 - 4244b2: 49 83 eb 10 sub $0x10,%r11 - 4244b6: 0f 86 68 0b 00 00 jbe 425024 - 4244bc: 48 83 c1 10 add $0x10,%rcx - 4244c0: 66 0f 6f dc movdqa %xmm4,%xmm3 - 4244c4: 49 83 c2 10 add $0x10,%r10 - 4244c8: 7f 56 jg 424520 - 4244ca: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4244cf: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4244d4: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 4244d8: 66 0f 73 db 08 psrldq $0x8,%xmm3 - 4244dd: 66 0f 73 fa 08 pslldq $0x8,%xmm2 - 4244e2: 66 0f eb d3 por %xmm3,%xmm2 - 4244e6: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4244ea: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 4244ee: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4244f2: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4244f6: 81 ea ff ff 00 00 sub $0xffff,%edx - 4244fc: 0f 85 ee 0a 00 00 jne 424ff0 - 424502: 49 83 eb 10 sub $0x10,%r11 - 424506: 0f 86 18 0b 00 00 jbe 425024 - 42450c: 48 83 c1 10 add $0x10,%rcx - 424510: 66 0f 6f dc movdqa %xmm4,%xmm3 - 424514: e9 57 ff ff ff jmpq 424470 - 424519: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 424520: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 424524: 66 0f d7 d0 pmovmskb %xmm0,%edx - 424528: f7 c2 00 ff 00 00 test $0xff00,%edx - 42452e: 75 20 jne 424550 - 424530: 49 83 fb 08 cmp $0x8,%r11 - 424534: 76 1a jbe 424550 - 424536: 66 0f ef c0 pxor %xmm0,%xmm0 - 42453a: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 424541: e9 34 ff ff ff jmpq 42447a - 424546: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42454d: 00 00 00 - 424550: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 424555: 66 0f 73 d8 08 psrldq $0x8,%xmm0 - 42455a: 66 0f 73 db 08 psrldq $0x8,%xmm3 - 42455f: e9 7c 0a 00 00 jmpq 424fe0 - 424564: 66 90 xchg %ax,%ax - 424566: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42456d: 00 00 00 - 424570: 66 0f ef c0 pxor %xmm0,%xmm0 - 424574: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 424578: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42457c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 424580: 66 0f 73 fa 07 pslldq $0x7,%xmm2 - 424585: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 424589: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42458d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 424592: d3 ea shr %cl,%edx - 424594: 41 d3 e9 shr %cl,%r9d - 424597: 44 29 ca sub %r9d,%edx - 42459a: 0f 85 55 0a 00 00 jne 424ff5 - 4245a0: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 4245a4: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 - 4245a9: 4d 39 cb cmp %r9,%r11 - 4245ac: 0f 82 72 0a 00 00 jb 425024 - 4245b2: 4d 85 c9 test %r9,%r9 - 4245b5: 0f 84 69 0a 00 00 je 425024 - 4245bb: 4d 89 cb mov %r9,%r11 - 4245be: 66 0f ef c0 pxor %xmm0,%xmm0 - 4245c2: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 4245c9: 41 b9 09 00 00 00 mov $0x9,%r9d - 4245cf: 4c 8d 57 09 lea 0x9(%rdi),%r10 - 4245d3: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 4245da: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 4245e1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4245e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4245ed: 00 00 00 - 4245f0: 49 83 c2 10 add $0x10,%r10 - 4245f4: 0f 8f a6 00 00 00 jg 4246a0 - 4245fa: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4245ff: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 424604: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 424608: 66 0f 73 db 09 psrldq $0x9,%xmm3 - 42460d: 66 0f 73 fa 07 pslldq $0x7,%xmm2 - 424612: 66 0f eb d3 por %xmm3,%xmm2 - 424616: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42461a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42461e: 66 0f f8 c8 psubb %xmm0,%xmm1 - 424622: 66 0f d7 d1 pmovmskb %xmm1,%edx - 424626: 81 ea ff ff 00 00 sub $0xffff,%edx - 42462c: 0f 85 be 09 00 00 jne 424ff0 - 424632: 49 83 eb 10 sub $0x10,%r11 - 424636: 0f 86 e8 09 00 00 jbe 425024 - 42463c: 48 83 c1 10 add $0x10,%rcx - 424640: 66 0f 6f dc movdqa %xmm4,%xmm3 - 424644: 49 83 c2 10 add $0x10,%r10 - 424648: 7f 56 jg 4246a0 - 42464a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42464f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 424654: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 424658: 66 0f 73 db 09 psrldq $0x9,%xmm3 - 42465d: 66 0f 73 fa 07 pslldq $0x7,%xmm2 - 424662: 66 0f eb d3 por %xmm3,%xmm2 - 424666: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42466a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42466e: 66 0f f8 c8 psubb %xmm0,%xmm1 - 424672: 66 0f d7 d1 pmovmskb %xmm1,%edx - 424676: 81 ea ff ff 00 00 sub $0xffff,%edx - 42467c: 0f 85 6e 09 00 00 jne 424ff0 - 424682: 49 83 eb 10 sub $0x10,%r11 - 424686: 0f 86 98 09 00 00 jbe 425024 - 42468c: 48 83 c1 10 add $0x10,%rcx - 424690: 66 0f 6f dc movdqa %xmm4,%xmm3 - 424694: e9 57 ff ff ff jmpq 4245f0 - 424699: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4246a0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 4246a4: 66 0f d7 d0 pmovmskb %xmm0,%edx - 4246a8: f7 c2 00 fe 00 00 test $0xfe00,%edx - 4246ae: 75 20 jne 4246d0 - 4246b0: 49 83 fb 07 cmp $0x7,%r11 - 4246b4: 76 1a jbe 4246d0 - 4246b6: 66 0f ef c0 pxor %xmm0,%xmm0 - 4246ba: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 4246c1: e9 34 ff ff ff jmpq 4245fa - 4246c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4246cd: 00 00 00 - 4246d0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4246d5: 66 0f 73 d8 09 psrldq $0x9,%xmm0 - 4246da: 66 0f 73 db 09 psrldq $0x9,%xmm3 - 4246df: e9 fc 08 00 00 jmpq 424fe0 - 4246e4: 66 90 xchg %ax,%ax - 4246e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4246ed: 00 00 00 - 4246f0: 66 0f ef c0 pxor %xmm0,%xmm0 - 4246f4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 4246f8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 4246fc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 424700: 66 0f 73 fa 06 pslldq $0x6,%xmm2 - 424705: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 424709: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42470d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 424712: d3 ea shr %cl,%edx - 424714: 41 d3 e9 shr %cl,%r9d - 424717: 44 29 ca sub %r9d,%edx - 42471a: 0f 85 d5 08 00 00 jne 424ff5 - 424720: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 424724: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 - 424729: 4d 39 cb cmp %r9,%r11 - 42472c: 0f 82 f2 08 00 00 jb 425024 - 424732: 4d 85 c9 test %r9,%r9 - 424735: 0f 84 e9 08 00 00 je 425024 - 42473b: 4d 89 cb mov %r9,%r11 - 42473e: 66 0f ef c0 pxor %xmm0,%xmm0 - 424742: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 424749: 41 b9 0a 00 00 00 mov $0xa,%r9d - 42474f: 4c 8d 57 0a lea 0xa(%rdi),%r10 - 424753: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42475a: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 424761: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 424766: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42476d: 00 00 00 - 424770: 49 83 c2 10 add $0x10,%r10 - 424774: 0f 8f a6 00 00 00 jg 424820 - 42477a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42477f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 424784: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 424788: 66 0f 73 db 0a psrldq $0xa,%xmm3 - 42478d: 66 0f 73 fa 06 pslldq $0x6,%xmm2 - 424792: 66 0f eb d3 por %xmm3,%xmm2 - 424796: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42479a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42479e: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4247a2: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4247a6: 81 ea ff ff 00 00 sub $0xffff,%edx - 4247ac: 0f 85 3e 08 00 00 jne 424ff0 - 4247b2: 49 83 eb 10 sub $0x10,%r11 - 4247b6: 0f 86 68 08 00 00 jbe 425024 - 4247bc: 48 83 c1 10 add $0x10,%rcx - 4247c0: 66 0f 6f dc movdqa %xmm4,%xmm3 - 4247c4: 49 83 c2 10 add $0x10,%r10 - 4247c8: 7f 56 jg 424820 - 4247ca: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4247cf: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4247d4: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 4247d8: 66 0f 73 db 0a psrldq $0xa,%xmm3 - 4247dd: 66 0f 73 fa 06 pslldq $0x6,%xmm2 - 4247e2: 66 0f eb d3 por %xmm3,%xmm2 - 4247e6: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4247ea: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 4247ee: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4247f2: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4247f6: 81 ea ff ff 00 00 sub $0xffff,%edx - 4247fc: 0f 85 ee 07 00 00 jne 424ff0 - 424802: 49 83 eb 10 sub $0x10,%r11 - 424806: 0f 86 18 08 00 00 jbe 425024 - 42480c: 48 83 c1 10 add $0x10,%rcx - 424810: 66 0f 6f dc movdqa %xmm4,%xmm3 - 424814: e9 57 ff ff ff jmpq 424770 - 424819: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 424820: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 424824: 66 0f d7 d0 pmovmskb %xmm0,%edx - 424828: f7 c2 00 fc 00 00 test $0xfc00,%edx - 42482e: 75 20 jne 424850 - 424830: 49 83 fb 06 cmp $0x6,%r11 - 424834: 76 1a jbe 424850 - 424836: 66 0f ef c0 pxor %xmm0,%xmm0 - 42483a: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 424841: e9 34 ff ff ff jmpq 42477a - 424846: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42484d: 00 00 00 - 424850: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 424855: 66 0f 73 d8 0a psrldq $0xa,%xmm0 - 42485a: 66 0f 73 db 0a psrldq $0xa,%xmm3 - 42485f: e9 7c 07 00 00 jmpq 424fe0 - 424864: 66 90 xchg %ax,%ax - 424866: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42486d: 00 00 00 - 424870: 66 0f ef c0 pxor %xmm0,%xmm0 - 424874: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 424878: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42487c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 424880: 66 0f 73 fa 05 pslldq $0x5,%xmm2 - 424885: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 424889: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42488d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 424892: d3 ea shr %cl,%edx - 424894: 41 d3 e9 shr %cl,%r9d - 424897: 44 29 ca sub %r9d,%edx - 42489a: 0f 85 55 07 00 00 jne 424ff5 - 4248a0: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 4248a4: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 - 4248a9: 4d 39 cb cmp %r9,%r11 - 4248ac: 0f 82 72 07 00 00 jb 425024 - 4248b2: 4d 85 c9 test %r9,%r9 - 4248b5: 0f 84 69 07 00 00 je 425024 - 4248bb: 4d 89 cb mov %r9,%r11 - 4248be: 66 0f ef c0 pxor %xmm0,%xmm0 - 4248c2: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 4248c9: 41 b9 0b 00 00 00 mov $0xb,%r9d - 4248cf: 4c 8d 57 0b lea 0xb(%rdi),%r10 - 4248d3: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 4248da: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 4248e1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4248e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4248ed: 00 00 00 - 4248f0: 49 83 c2 10 add $0x10,%r10 - 4248f4: 0f 8f a6 00 00 00 jg 4249a0 - 4248fa: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4248ff: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 424904: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 424908: 66 0f 73 db 0b psrldq $0xb,%xmm3 - 42490d: 66 0f 73 fa 05 pslldq $0x5,%xmm2 - 424912: 66 0f eb d3 por %xmm3,%xmm2 - 424916: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42491a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42491e: 66 0f f8 c8 psubb %xmm0,%xmm1 - 424922: 66 0f d7 d1 pmovmskb %xmm1,%edx - 424926: 81 ea ff ff 00 00 sub $0xffff,%edx - 42492c: 0f 85 be 06 00 00 jne 424ff0 - 424932: 49 83 eb 10 sub $0x10,%r11 - 424936: 0f 86 e8 06 00 00 jbe 425024 - 42493c: 48 83 c1 10 add $0x10,%rcx - 424940: 66 0f 6f dc movdqa %xmm4,%xmm3 - 424944: 49 83 c2 10 add $0x10,%r10 - 424948: 7f 56 jg 4249a0 - 42494a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42494f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 424954: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 424958: 66 0f 73 db 0b psrldq $0xb,%xmm3 - 42495d: 66 0f 73 fa 05 pslldq $0x5,%xmm2 - 424962: 66 0f eb d3 por %xmm3,%xmm2 - 424966: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42496a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42496e: 66 0f f8 c8 psubb %xmm0,%xmm1 - 424972: 66 0f d7 d1 pmovmskb %xmm1,%edx - 424976: 81 ea ff ff 00 00 sub $0xffff,%edx - 42497c: 0f 85 6e 06 00 00 jne 424ff0 - 424982: 49 83 eb 10 sub $0x10,%r11 - 424986: 0f 86 98 06 00 00 jbe 425024 - 42498c: 48 83 c1 10 add $0x10,%rcx - 424990: 66 0f 6f dc movdqa %xmm4,%xmm3 - 424994: e9 57 ff ff ff jmpq 4248f0 - 424999: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4249a0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 4249a4: 66 0f d7 d0 pmovmskb %xmm0,%edx - 4249a8: f7 c2 00 f8 00 00 test $0xf800,%edx - 4249ae: 75 20 jne 4249d0 - 4249b0: 49 83 fb 05 cmp $0x5,%r11 - 4249b4: 76 1a jbe 4249d0 - 4249b6: 66 0f ef c0 pxor %xmm0,%xmm0 - 4249ba: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 4249c1: e9 34 ff ff ff jmpq 4248fa - 4249c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4249cd: 00 00 00 - 4249d0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4249d5: 66 0f 73 d8 0b psrldq $0xb,%xmm0 - 4249da: 66 0f 73 db 0b psrldq $0xb,%xmm3 - 4249df: e9 fc 05 00 00 jmpq 424fe0 - 4249e4: 66 90 xchg %ax,%ax - 4249e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4249ed: 00 00 00 - 4249f0: 66 0f ef c0 pxor %xmm0,%xmm0 - 4249f4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 4249f8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 4249fc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 424a00: 66 0f 73 fa 04 pslldq $0x4,%xmm2 - 424a05: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 424a09: 66 0f f8 d0 psubb %xmm0,%xmm2 - 424a0d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 424a12: d3 ea shr %cl,%edx - 424a14: 41 d3 e9 shr %cl,%r9d - 424a17: 44 29 ca sub %r9d,%edx - 424a1a: 0f 85 d5 05 00 00 jne 424ff5 - 424a20: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 424a24: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 - 424a29: 4d 39 cb cmp %r9,%r11 - 424a2c: 0f 82 f2 05 00 00 jb 425024 - 424a32: 4d 85 c9 test %r9,%r9 - 424a35: 0f 84 e9 05 00 00 je 425024 - 424a3b: 4d 89 cb mov %r9,%r11 - 424a3e: 66 0f ef c0 pxor %xmm0,%xmm0 - 424a42: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 424a49: 41 b9 0c 00 00 00 mov $0xc,%r9d - 424a4f: 4c 8d 57 0c lea 0xc(%rdi),%r10 - 424a53: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 424a5a: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 424a61: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 424a66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 424a6d: 00 00 00 - 424a70: 49 83 c2 10 add $0x10,%r10 - 424a74: 0f 8f a6 00 00 00 jg 424b20 - 424a7a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 424a7f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 424a84: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 424a88: 66 0f 73 db 0c psrldq $0xc,%xmm3 - 424a8d: 66 0f 73 fa 04 pslldq $0x4,%xmm2 - 424a92: 66 0f eb d3 por %xmm3,%xmm2 - 424a96: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 424a9a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 424a9e: 66 0f f8 c8 psubb %xmm0,%xmm1 - 424aa2: 66 0f d7 d1 pmovmskb %xmm1,%edx - 424aa6: 81 ea ff ff 00 00 sub $0xffff,%edx - 424aac: 0f 85 3e 05 00 00 jne 424ff0 - 424ab2: 49 83 eb 10 sub $0x10,%r11 - 424ab6: 0f 86 68 05 00 00 jbe 425024 - 424abc: 48 83 c1 10 add $0x10,%rcx - 424ac0: 66 0f 6f dc movdqa %xmm4,%xmm3 - 424ac4: 49 83 c2 10 add $0x10,%r10 - 424ac8: 7f 56 jg 424b20 - 424aca: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 424acf: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 424ad4: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 424ad8: 66 0f 73 db 0c psrldq $0xc,%xmm3 - 424add: 66 0f 73 fa 04 pslldq $0x4,%xmm2 - 424ae2: 66 0f eb d3 por %xmm3,%xmm2 - 424ae6: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 424aea: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 424aee: 66 0f f8 c8 psubb %xmm0,%xmm1 - 424af2: 66 0f d7 d1 pmovmskb %xmm1,%edx - 424af6: 81 ea ff ff 00 00 sub $0xffff,%edx - 424afc: 0f 85 ee 04 00 00 jne 424ff0 - 424b02: 49 83 eb 10 sub $0x10,%r11 - 424b06: 0f 86 18 05 00 00 jbe 425024 - 424b0c: 48 83 c1 10 add $0x10,%rcx - 424b10: 66 0f 6f dc movdqa %xmm4,%xmm3 - 424b14: e9 57 ff ff ff jmpq 424a70 - 424b19: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 424b20: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 424b24: 66 0f d7 d0 pmovmskb %xmm0,%edx - 424b28: f7 c2 00 f0 00 00 test $0xf000,%edx - 424b2e: 75 20 jne 424b50 - 424b30: 49 83 fb 04 cmp $0x4,%r11 - 424b34: 76 1a jbe 424b50 - 424b36: 66 0f ef c0 pxor %xmm0,%xmm0 - 424b3a: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 424b41: e9 34 ff ff ff jmpq 424a7a - 424b46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 424b4d: 00 00 00 - 424b50: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 424b55: 66 0f 73 d8 0c psrldq $0xc,%xmm0 - 424b5a: 66 0f 73 db 0c psrldq $0xc,%xmm3 - 424b5f: e9 7c 04 00 00 jmpq 424fe0 - 424b64: 66 90 xchg %ax,%ax - 424b66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 424b6d: 00 00 00 - 424b70: 66 0f ef c0 pxor %xmm0,%xmm0 - 424b74: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 424b78: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 424b7c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 424b80: 66 0f 73 fa 03 pslldq $0x3,%xmm2 - 424b85: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 424b89: 66 0f f8 d0 psubb %xmm0,%xmm2 - 424b8d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 424b92: d3 ea shr %cl,%edx - 424b94: 41 d3 e9 shr %cl,%r9d - 424b97: 44 29 ca sub %r9d,%edx - 424b9a: 0f 85 55 04 00 00 jne 424ff5 - 424ba0: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 424ba4: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 - 424ba9: 4d 39 cb cmp %r9,%r11 - 424bac: 0f 82 72 04 00 00 jb 425024 - 424bb2: 4d 85 c9 test %r9,%r9 - 424bb5: 0f 84 69 04 00 00 je 425024 - 424bbb: 4d 89 cb mov %r9,%r11 - 424bbe: 66 0f ef c0 pxor %xmm0,%xmm0 - 424bc2: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 424bc9: 41 b9 0d 00 00 00 mov $0xd,%r9d - 424bcf: 4c 8d 57 0d lea 0xd(%rdi),%r10 - 424bd3: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 424bda: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 424be1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 424be6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 424bed: 00 00 00 - 424bf0: 49 83 c2 10 add $0x10,%r10 - 424bf4: 0f 8f a6 00 00 00 jg 424ca0 - 424bfa: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 424bff: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 424c04: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 424c08: 66 0f 73 db 0d psrldq $0xd,%xmm3 - 424c0d: 66 0f 73 fa 03 pslldq $0x3,%xmm2 - 424c12: 66 0f eb d3 por %xmm3,%xmm2 - 424c16: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 424c1a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 424c1e: 66 0f f8 c8 psubb %xmm0,%xmm1 - 424c22: 66 0f d7 d1 pmovmskb %xmm1,%edx - 424c26: 81 ea ff ff 00 00 sub $0xffff,%edx - 424c2c: 0f 85 be 03 00 00 jne 424ff0 - 424c32: 49 83 eb 10 sub $0x10,%r11 - 424c36: 0f 86 e8 03 00 00 jbe 425024 - 424c3c: 48 83 c1 10 add $0x10,%rcx - 424c40: 66 0f 6f dc movdqa %xmm4,%xmm3 - 424c44: 49 83 c2 10 add $0x10,%r10 - 424c48: 7f 56 jg 424ca0 - 424c4a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 424c4f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 424c54: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 424c58: 66 0f 73 db 0d psrldq $0xd,%xmm3 - 424c5d: 66 0f 73 fa 03 pslldq $0x3,%xmm2 - 424c62: 66 0f eb d3 por %xmm3,%xmm2 - 424c66: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 424c6a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 424c6e: 66 0f f8 c8 psubb %xmm0,%xmm1 - 424c72: 66 0f d7 d1 pmovmskb %xmm1,%edx - 424c76: 81 ea ff ff 00 00 sub $0xffff,%edx - 424c7c: 0f 85 6e 03 00 00 jne 424ff0 - 424c82: 49 83 eb 10 sub $0x10,%r11 - 424c86: 0f 86 98 03 00 00 jbe 425024 - 424c8c: 48 83 c1 10 add $0x10,%rcx - 424c90: 66 0f 6f dc movdqa %xmm4,%xmm3 - 424c94: e9 57 ff ff ff jmpq 424bf0 - 424c99: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 424ca0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 424ca4: 66 0f d7 d0 pmovmskb %xmm0,%edx - 424ca8: f7 c2 00 e0 00 00 test $0xe000,%edx - 424cae: 75 20 jne 424cd0 - 424cb0: 49 83 fb 03 cmp $0x3,%r11 - 424cb4: 76 1a jbe 424cd0 - 424cb6: 66 0f ef c0 pxor %xmm0,%xmm0 - 424cba: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 424cc1: e9 34 ff ff ff jmpq 424bfa - 424cc6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 424ccd: 00 00 00 - 424cd0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 424cd5: 66 0f 73 d8 0d psrldq $0xd,%xmm0 - 424cda: 66 0f 73 db 0d psrldq $0xd,%xmm3 - 424cdf: e9 fc 02 00 00 jmpq 424fe0 - 424ce4: 66 90 xchg %ax,%ax - 424ce6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 424ced: 00 00 00 - 424cf0: 66 0f ef c0 pxor %xmm0,%xmm0 - 424cf4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 424cf8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 424cfc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 424d00: 66 0f 73 fa 02 pslldq $0x2,%xmm2 - 424d05: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 424d09: 66 0f f8 d0 psubb %xmm0,%xmm2 - 424d0d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 424d12: d3 ea shr %cl,%edx - 424d14: 41 d3 e9 shr %cl,%r9d - 424d17: 44 29 ca sub %r9d,%edx - 424d1a: 0f 85 d5 02 00 00 jne 424ff5 - 424d20: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 424d24: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 - 424d29: 4d 39 cb cmp %r9,%r11 - 424d2c: 0f 82 f2 02 00 00 jb 425024 - 424d32: 4d 85 c9 test %r9,%r9 - 424d35: 0f 84 e9 02 00 00 je 425024 - 424d3b: 4d 89 cb mov %r9,%r11 - 424d3e: 66 0f ef c0 pxor %xmm0,%xmm0 - 424d42: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 424d49: 41 b9 0e 00 00 00 mov $0xe,%r9d - 424d4f: 4c 8d 57 0e lea 0xe(%rdi),%r10 - 424d53: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 424d5a: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 424d61: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 424d66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 424d6d: 00 00 00 - 424d70: 49 83 c2 10 add $0x10,%r10 - 424d74: 0f 8f a6 00 00 00 jg 424e20 - 424d7a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 424d7f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 424d84: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 424d88: 66 0f 73 db 0e psrldq $0xe,%xmm3 - 424d8d: 66 0f 73 fa 02 pslldq $0x2,%xmm2 - 424d92: 66 0f eb d3 por %xmm3,%xmm2 - 424d96: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 424d9a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 424d9e: 66 0f f8 c8 psubb %xmm0,%xmm1 - 424da2: 66 0f d7 d1 pmovmskb %xmm1,%edx - 424da6: 81 ea ff ff 00 00 sub $0xffff,%edx - 424dac: 0f 85 3e 02 00 00 jne 424ff0 - 424db2: 49 83 eb 10 sub $0x10,%r11 - 424db6: 0f 86 68 02 00 00 jbe 425024 - 424dbc: 48 83 c1 10 add $0x10,%rcx - 424dc0: 66 0f 6f dc movdqa %xmm4,%xmm3 - 424dc4: 49 83 c2 10 add $0x10,%r10 - 424dc8: 7f 56 jg 424e20 - 424dca: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 424dcf: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 424dd4: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 424dd8: 66 0f 73 db 0e psrldq $0xe,%xmm3 - 424ddd: 66 0f 73 fa 02 pslldq $0x2,%xmm2 - 424de2: 66 0f eb d3 por %xmm3,%xmm2 - 424de6: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 424dea: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 424dee: 66 0f f8 c8 psubb %xmm0,%xmm1 - 424df2: 66 0f d7 d1 pmovmskb %xmm1,%edx - 424df6: 81 ea ff ff 00 00 sub $0xffff,%edx - 424dfc: 0f 85 ee 01 00 00 jne 424ff0 - 424e02: 49 83 eb 10 sub $0x10,%r11 - 424e06: 0f 86 18 02 00 00 jbe 425024 - 424e0c: 48 83 c1 10 add $0x10,%rcx - 424e10: 66 0f 6f dc movdqa %xmm4,%xmm3 - 424e14: e9 57 ff ff ff jmpq 424d70 - 424e19: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 424e20: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 424e24: 66 0f d7 d0 pmovmskb %xmm0,%edx - 424e28: f7 c2 00 c0 00 00 test $0xc000,%edx - 424e2e: 75 20 jne 424e50 - 424e30: 49 83 fb 02 cmp $0x2,%r11 - 424e34: 76 1a jbe 424e50 - 424e36: 66 0f ef c0 pxor %xmm0,%xmm0 - 424e3a: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 424e41: e9 34 ff ff ff jmpq 424d7a - 424e46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 424e4d: 00 00 00 - 424e50: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 424e55: 66 0f 73 d8 0e psrldq $0xe,%xmm0 - 424e5a: 66 0f 73 db 0e psrldq $0xe,%xmm3 - 424e5f: e9 7c 01 00 00 jmpq 424fe0 - 424e64: 66 90 xchg %ax,%ax - 424e66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 424e6d: 00 00 00 - 424e70: 66 0f ef c0 pxor %xmm0,%xmm0 - 424e74: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 424e78: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 424e7c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 424e80: 66 0f 73 fa 01 pslldq $0x1,%xmm2 - 424e85: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 424e89: 66 0f f8 d0 psubb %xmm0,%xmm2 - 424e8d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 424e92: d3 ea shr %cl,%edx - 424e94: 41 d3 e9 shr %cl,%r9d - 424e97: 44 29 ca sub %r9d,%edx - 424e9a: 0f 85 55 01 00 00 jne 424ff5 - 424ea0: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 424ea4: 4e 8d 4c 19 f0 lea -0x10(%rcx,%r11,1),%r9 - 424ea9: 4d 39 cb cmp %r9,%r11 - 424eac: 0f 82 72 01 00 00 jb 425024 - 424eb2: 4d 85 c9 test %r9,%r9 - 424eb5: 0f 84 69 01 00 00 je 425024 - 424ebb: 4d 89 cb mov %r9,%r11 - 424ebe: 66 0f ef c0 pxor %xmm0,%xmm0 - 424ec2: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 424ec9: 41 b9 0f 00 00 00 mov $0xf,%r9d - 424ecf: 4c 8d 57 0f lea 0xf(%rdi),%r10 - 424ed3: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 424eda: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 424ee1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 424ee6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 424eed: 00 00 00 - 424ef0: 49 83 c2 10 add $0x10,%r10 - 424ef4: 0f 8f a6 00 00 00 jg 424fa0 - 424efa: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 424eff: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 424f04: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 424f08: 66 0f 73 db 0f psrldq $0xf,%xmm3 - 424f0d: 66 0f 73 fa 01 pslldq $0x1,%xmm2 - 424f12: 66 0f eb d3 por %xmm3,%xmm2 - 424f16: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 424f1a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 424f1e: 66 0f f8 c8 psubb %xmm0,%xmm1 - 424f22: 66 0f d7 d1 pmovmskb %xmm1,%edx - 424f26: 81 ea ff ff 00 00 sub $0xffff,%edx - 424f2c: 0f 85 be 00 00 00 jne 424ff0 - 424f32: 49 83 eb 10 sub $0x10,%r11 - 424f36: 0f 86 e8 00 00 00 jbe 425024 - 424f3c: 48 83 c1 10 add $0x10,%rcx - 424f40: 66 0f 6f dc movdqa %xmm4,%xmm3 - 424f44: 49 83 c2 10 add $0x10,%r10 - 424f48: 7f 56 jg 424fa0 - 424f4a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 424f4f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 424f54: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 424f58: 66 0f 73 db 0f psrldq $0xf,%xmm3 - 424f5d: 66 0f 73 fa 01 pslldq $0x1,%xmm2 - 424f62: 66 0f eb d3 por %xmm3,%xmm2 - 424f66: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 424f6a: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 424f6e: 66 0f f8 c8 psubb %xmm0,%xmm1 - 424f72: 66 0f d7 d1 pmovmskb %xmm1,%edx - 424f76: 81 ea ff ff 00 00 sub $0xffff,%edx - 424f7c: 75 72 jne 424ff0 - 424f7e: 49 83 eb 10 sub $0x10,%r11 - 424f82: 0f 86 9c 00 00 00 jbe 425024 - 424f88: 48 83 c1 10 add $0x10,%rcx - 424f8c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 424f90: e9 5b ff ff ff jmpq 424ef0 - 424f95: 90 nop - 424f96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 424f9d: 00 00 00 - 424fa0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 424fa4: 66 0f d7 d0 pmovmskb %xmm0,%edx - 424fa8: f7 c2 00 80 00 00 test $0x8000,%edx - 424fae: 75 20 jne 424fd0 - 424fb0: 49 83 fb 01 cmp $0x1,%r11 - 424fb4: 76 1a jbe 424fd0 - 424fb6: 66 0f ef c0 pxor %xmm0,%xmm0 - 424fba: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 424fc1: e9 34 ff ff ff jmpq 424efa - 424fc6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 424fcd: 00 00 00 - 424fd0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 424fd5: 66 0f 73 db 0f psrldq $0xf,%xmm3 - 424fda: 66 0f 73 d8 0f psrldq $0xf,%xmm0 - 424fdf: 90 nop - 424fe0: 66 0f 74 cb pcmpeqb %xmm3,%xmm1 - 424fe4: 66 0f f8 c8 psubb %xmm0,%xmm1 - 424fe8: 66 0f d7 d1 pmovmskb %xmm1,%edx - 424fec: f7 d2 not %edx - 424fee: 66 90 xchg %ax,%ax - 424ff0: 49 8d 44 09 f0 lea -0x10(%r9,%rcx,1),%rax - 424ff5: 48 8d 3c 07 lea (%rdi,%rax,1),%rdi - 424ff9: 48 8d 34 0e lea (%rsi,%rcx,1),%rsi - 424ffd: 45 85 c0 test %r8d,%r8d - 425000: 74 0e je 425010 - 425002: 48 87 f7 xchg %rsi,%rdi - 425005: 90 nop - 425006: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42500d: 00 00 00 - 425010: 48 0f bc d2 bsf %rdx,%rdx - 425014: 49 29 d3 sub %rdx,%r11 - 425017: 76 0b jbe 425024 - 425019: 0f b6 0c 16 movzbl (%rsi,%rdx,1),%ecx - 42501d: 0f b6 04 17 movzbl (%rdi,%rdx,1),%eax - 425021: 29 c8 sub %ecx,%eax - 425023: c3 retq - 425024: 31 c0 xor %eax,%eax - 425026: c3 retq - 425027: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 42502e: 00 00 - 425030: 0f b6 0e movzbl (%rsi),%ecx - 425033: 0f b6 07 movzbl (%rdi),%eax - 425036: 29 c8 sub %ecx,%eax - 425038: c3 retq - 425039: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - -0000000000425040 : - 425040: 41 57 push %r15 - 425042: 41 56 push %r14 - 425044: 41 55 push %r13 - 425046: 41 54 push %r12 - 425048: 49 89 fd mov %rdi,%r13 - 42504b: 55 push %rbp - 42504c: 53 push %rbx - 42504d: 48 89 d5 mov %rdx,%rbp - 425050: 48 89 f3 mov %rsi,%rbx - 425053: 49 89 cc mov %rcx,%r12 - 425056: bf 01 00 00 00 mov $0x1,%edi - 42505b: 48 81 ec 58 08 00 00 sub $0x858,%rsp - 425062: ba 01 00 00 00 mov $0x1,%edx - 425067: 31 c9 xor %ecx,%ecx - 425069: 48 c7 c6 ff ff ff ff mov $0xffffffffffffffff,%rsi - 425070: 48 8d 04 0a lea (%rdx,%rcx,1),%rax - 425074: 49 39 c4 cmp %rax,%r12 - 425077: 76 2c jbe 4250a5 - 425079: 4c 8d 44 35 00 lea 0x0(%rbp,%rsi,1),%r8 - 42507e: 45 0f b6 14 10 movzbl (%r8,%rdx,1),%r10d - 425083: 44 38 54 05 00 cmp %r10b,0x0(%rbp,%rax,1) - 425088: 0f 83 8a 02 00 00 jae 425318 - 42508e: 48 89 c1 mov %rax,%rcx - 425091: ba 01 00 00 00 mov $0x1,%edx - 425096: 48 89 c7 mov %rax,%rdi - 425099: 48 8d 04 0a lea (%rdx,%rcx,1),%rax - 42509d: 48 29 f7 sub %rsi,%rdi - 4250a0: 49 39 c4 cmp %rax,%r12 - 4250a3: 77 d4 ja 425079 - 4250a5: 48 c7 44 24 08 01 00 movq $0x1,0x8(%rsp) - 4250ac: 00 00 - 4250ae: ba 01 00 00 00 mov $0x1,%edx - 4250b3: 31 c9 xor %ecx,%ecx - 4250b5: 49 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%r8 - 4250bc: 0f 1f 40 00 nopl 0x0(%rax) - 4250c0: 48 8d 04 0a lea (%rdx,%rcx,1),%rax - 4250c4: 49 39 c4 cmp %rax,%r12 - 4250c7: 76 31 jbe 4250fa - 4250c9: 4e 8d 4c 05 00 lea 0x0(%rbp,%r8,1),%r9 - 4250ce: 45 0f b6 1c 11 movzbl (%r9,%rdx,1),%r11d - 4250d3: 44 38 5c 05 00 cmp %r11b,0x0(%rbp,%rax,1) - 4250d8: 0f 86 52 02 00 00 jbe 425330 - 4250de: 48 89 c1 mov %rax,%rcx - 4250e1: ba 01 00 00 00 mov $0x1,%edx - 4250e6: 4c 29 c1 sub %r8,%rcx - 4250e9: 48 89 4c 24 08 mov %rcx,0x8(%rsp) - 4250ee: 48 89 c1 mov %rax,%rcx - 4250f1: 48 8d 04 0a lea (%rdx,%rcx,1),%rax - 4250f5: 49 39 c4 cmp %rax,%r12 - 4250f8: 77 cf ja 4250c9 - 4250fa: 49 8d 40 01 lea 0x1(%r8),%rax - 4250fe: 48 83 c6 01 add $0x1,%rsi - 425102: 48 39 f0 cmp %rsi,%rax - 425105: 48 89 44 24 10 mov %rax,0x10(%rsp) - 42510a: 73 0a jae 425116 - 42510c: 48 89 7c 24 08 mov %rdi,0x8(%rsp) - 425111: 48 89 74 24 10 mov %rsi,0x10(%rsp) - 425116: 4c 89 64 24 18 mov %r12,0x18(%rsp) - 42511b: 48 8d 44 24 50 lea 0x50(%rsp),%rax - 425120: 48 8d 94 24 50 08 00 lea 0x850(%rsp),%rdx - 425127: 00 - 425128: f3 0f 7e 44 24 18 movq 0x18(%rsp),%xmm0 - 42512e: 66 0f 6c c0 punpcklqdq %xmm0,%xmm0 - 425132: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 425138: 0f 29 00 movaps %xmm0,(%rax) - 42513b: 48 83 c0 10 add $0x10,%rax - 42513f: 48 39 d0 cmp %rdx,%rax - 425142: 75 f4 jne 425138 - 425144: 4d 85 e4 test %r12,%r12 - 425147: 49 8d 44 24 ff lea -0x1(%r12),%rax - 42514c: 48 89 ea mov %rbp,%rdx - 42514f: 74 1d je 42516e - 425151: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 425158: 0f b6 0a movzbl (%rdx),%ecx - 42515b: 48 83 c2 01 add $0x1,%rdx - 42515f: 48 89 44 cc 50 mov %rax,0x50(%rsp,%rcx,8) - 425164: 48 83 e8 01 sub $0x1,%rax - 425168: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 42516c: 75 ea jne 425158 - 42516e: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 425173: 48 8b 54 24 10 mov 0x10(%rsp),%rdx - 425178: 48 89 ef mov %rbp,%rdi - 42517b: 48 8d 74 05 00 lea 0x0(%rbp,%rax,1),%rsi - 425180: e8 ab b1 fd ff callq 400330 <__rela_iplt_end+0x68> - 425185: 85 c0 test %eax,%eax - 425187: 0f 85 0b 02 00 00 jne 425398 - 42518d: 48 8b 4c 24 10 mov 0x10(%rsp),%rcx - 425192: 4d 8d 7c 24 ff lea -0x1(%r12),%r15 - 425197: b8 01 00 00 00 mov $0x1,%eax - 42519c: 45 31 c0 xor %r8d,%r8d - 42519f: 48 89 6c 24 20 mov %rbp,0x20(%rsp) - 4251a4: 45 31 f6 xor %r14d,%r14d - 4251a7: 4c 89 64 24 18 mov %r12,0x18(%rsp) - 4251ac: 48 8d 71 ff lea -0x1(%rcx),%rsi - 4251b0: 48 89 cf mov %rcx,%rdi - 4251b3: 48 29 c8 sub %rcx,%rax - 4251b6: 48 f7 df neg %rdi - 4251b9: 48 89 44 24 40 mov %rax,0x40(%rsp) - 4251be: 4c 89 e0 mov %r12,%rax - 4251c1: 48 89 74 24 28 mov %rsi,0x28(%rsp) - 4251c6: 48 01 ee add %rbp,%rsi - 4251c9: 48 89 7c 24 48 mov %rdi,0x48(%rsp) - 4251ce: 49 89 f1 mov %rsi,%r9 - 4251d1: 48 89 74 24 38 mov %rsi,0x38(%rsp) - 4251d6: 4c 89 e6 mov %r12,%rsi - 4251d9: 48 2b 74 24 08 sub 0x8(%rsp),%rsi - 4251de: 49 01 f9 add %rdi,%r9 - 4251e1: 4c 89 fd mov %r15,%rbp - 4251e4: 48 89 df mov %rbx,%rdi - 4251e7: 4d 89 c7 mov %r8,%r15 - 4251ea: 4c 89 cb mov %r9,%rbx - 4251ed: 48 89 74 24 30 mov %rsi,0x30(%rsp) - 4251f2: eb 22 jmp 425216 - 4251f4: 0f 1f 40 00 nopl 0x0(%rax) - 4251f8: 4d 85 f6 test %r14,%r14 - 4251fb: 74 0b je 425208 - 4251fd: 48 3b 44 24 08 cmp 0x8(%rsp),%rax - 425202: 48 0f 42 44 24 30 cmovb 0x30(%rsp),%rax - 425208: 49 01 c7 add %rax,%r15 - 42520b: 45 31 f6 xor %r14d,%r14d - 42520e: 48 8b 44 24 18 mov 0x18(%rsp),%rax - 425213: 4c 89 e7 mov %r12,%rdi - 425216: 4d 8d 24 07 lea (%r15,%rax,1),%r12 - 42521a: 31 f6 xor %esi,%esi - 42521c: 4c 89 e2 mov %r12,%rdx - 42521f: 48 29 fa sub %rdi,%rdx - 425222: 4c 01 ef add %r13,%rdi - 425225: e8 16 09 00 00 callq 425b40 <__memchr> - 42522a: 4d 85 e4 test %r12,%r12 - 42522d: 0f 84 d7 02 00 00 je 42550a - 425233: 48 85 c0 test %rax,%rax - 425236: 0f 85 ce 02 00 00 jne 42550a - 42523c: 43 0f b6 44 25 ff movzbl -0x1(%r13,%r12,1),%eax - 425242: 48 8b 44 c4 50 mov 0x50(%rsp,%rax,8),%rax - 425247: 48 85 c0 test %rax,%rax - 42524a: 75 ac jne 4251f8 - 42524c: 48 8b 44 24 10 mov 0x10(%rsp),%rax - 425251: 48 8b 74 24 20 mov 0x20(%rsp),%rsi - 425256: 49 39 c6 cmp %rax,%r14 - 425259: 49 0f 43 c6 cmovae %r14,%rax - 42525d: 48 8d 14 06 lea (%rsi,%rax,1),%rdx - 425261: 49 8d 34 07 lea (%r15,%rax,1),%rsi - 425265: 48 39 e8 cmp %rbp,%rax - 425268: 49 8d 7c 35 00 lea 0x0(%r13,%rsi,1),%rdi - 42526d: 73 37 jae 4252a6 - 42526f: 0f b6 32 movzbl (%rdx),%esi - 425272: 40 38 37 cmp %sil,(%rdi) - 425275: 0f 85 d5 00 00 00 jne 425350 - 42527b: 48 89 c6 mov %rax,%rsi - 42527e: 48 f7 de neg %rsi - 425281: 48 01 f2 add %rsi,%rdx - 425284: 48 01 fe add %rdi,%rsi - 425287: eb 14 jmp 42529d - 425289: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 425290: 0f b6 0c 06 movzbl (%rsi,%rax,1),%ecx - 425294: 38 0c 02 cmp %cl,(%rdx,%rax,1) - 425297: 0f 85 b3 00 00 00 jne 425350 - 42529d: 48 83 c0 01 add $0x1,%rax - 4252a1: 48 39 e8 cmp %rbp,%rax - 4252a4: 72 ea jb 425290 - 4252a6: 48 8b 44 24 28 mov 0x28(%rsp),%rax - 4252ab: 49 8d 34 07 lea (%r15,%rax,1),%rsi - 4252af: 4c 01 ee add %r13,%rsi - 4252b2: 4c 3b 74 24 10 cmp 0x10(%rsp),%r14 - 4252b7: 0f 83 73 02 00 00 jae 425530 - 4252bd: 48 8b 44 24 38 mov 0x38(%rsp),%rax - 4252c2: 0f b6 00 movzbl (%rax),%eax - 4252c5: 38 06 cmp %al,(%rsi) - 4252c7: 0f 85 63 02 00 00 jne 425530 - 4252cd: 48 8b 44 24 28 mov 0x28(%rsp),%rax - 4252d2: 48 03 74 24 48 add 0x48(%rsp),%rsi - 4252d7: eb 18 jmp 4252f1 - 4252d9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4252e0: 48 8d 50 ff lea -0x1(%rax),%rdx - 4252e4: 0f b6 4c 32 01 movzbl 0x1(%rdx,%rsi,1),%ecx - 4252e9: 38 0c 03 cmp %cl,(%rbx,%rax,1) - 4252ec: 75 08 jne 4252f6 - 4252ee: 48 89 d0 mov %rdx,%rax - 4252f1: 49 39 c6 cmp %rax,%r14 - 4252f4: 75 ea jne 4252e0 - 4252f6: 49 83 c6 01 add $0x1,%r14 - 4252fa: 49 39 c6 cmp %rax,%r14 - 4252fd: 0f 87 37 02 00 00 ja 42553a - 425303: 4c 03 7c 24 08 add 0x8(%rsp),%r15 - 425308: 4c 8b 74 24 30 mov 0x30(%rsp),%r14 - 42530d: e9 fc fe ff ff jmpq 42520e - 425312: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 425318: 74 4e je 425368 - 42531a: 48 89 ce mov %rcx,%rsi - 42531d: bf 01 00 00 00 mov $0x1,%edi - 425322: 48 83 c1 01 add $0x1,%rcx - 425326: ba 01 00 00 00 mov $0x1,%edx - 42532b: e9 40 fd ff ff jmpq 425070 - 425330: 74 4e je 425380 - 425332: 49 89 c8 mov %rcx,%r8 - 425335: 48 c7 44 24 08 01 00 movq $0x1,0x8(%rsp) - 42533c: 00 00 - 42533e: 48 83 c1 01 add $0x1,%rcx - 425342: ba 01 00 00 00 mov $0x1,%edx - 425347: e9 74 fd ff ff jmpq 4250c0 - 42534c: 0f 1f 40 00 nopl 0x0(%rax) - 425350: 48 8b 7c 24 40 mov 0x40(%rsp),%rdi - 425355: 45 31 f6 xor %r14d,%r14d - 425358: 4e 8d 04 3f lea (%rdi,%r15,1),%r8 - 42535c: 4e 8d 3c 00 lea (%rax,%r8,1),%r15 - 425360: e9 a9 fe ff ff jmpq 42520e - 425365: 0f 1f 00 nopl (%rax) - 425368: 48 39 fa cmp %rdi,%rdx - 42536b: 0f 84 af 01 00 00 je 425520 - 425371: 48 83 c2 01 add $0x1,%rdx - 425375: e9 f6 fc ff ff jmpq 425070 - 42537a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 425380: 48 3b 54 24 08 cmp 0x8(%rsp),%rdx - 425385: 0f 84 83 01 00 00 je 42550e - 42538b: 48 83 c2 01 add $0x1,%rdx - 42538f: e9 2c fd ff ff jmpq 4250c0 - 425394: 0f 1f 40 00 nopl 0x0(%rax) - 425398: 48 8b 74 24 10 mov 0x10(%rsp),%rsi - 42539d: 4c 89 e0 mov %r12,%rax - 4253a0: 41 bb 01 00 00 00 mov $0x1,%r11d - 4253a6: 49 8d 4c 24 ff lea -0x1(%r12),%rcx - 4253ab: 4c 89 64 24 08 mov %r12,0x8(%rsp) - 4253b0: 48 29 f0 sub %rsi,%rax - 4253b3: 48 39 f0 cmp %rsi,%rax - 4253b6: 48 0f 42 c6 cmovb %rsi,%rax - 4253ba: 49 29 f3 sub %rsi,%r11 - 4253bd: 45 31 ff xor %r15d,%r15d - 4253c0: 48 83 c0 01 add $0x1,%rax - 4253c4: 48 89 44 24 38 mov %rax,0x38(%rsp) - 4253c9: 48 8d 46 ff lea -0x1(%rsi),%rax - 4253cd: 48 89 c7 mov %rax,%rdi - 4253d0: 48 89 44 24 30 mov %rax,0x30(%rsp) - 4253d5: 48 8d 44 35 00 lea 0x0(%rbp,%rsi,1),%rax - 4253da: 48 f7 de neg %rsi - 4253dd: 48 01 fd add %rdi,%rbp - 4253e0: 48 89 df mov %rbx,%rdi - 4253e3: 49 89 c6 mov %rax,%r14 - 4253e6: 48 89 44 24 18 mov %rax,0x18(%rsp) - 4253eb: 4c 89 e8 mov %r13,%rax - 4253ee: 49 01 f6 add %rsi,%r14 - 4253f1: 4d 89 fd mov %r15,%r13 - 4253f4: 48 89 74 24 20 mov %rsi,0x20(%rsp) - 4253f9: 4c 89 74 24 28 mov %r14,0x28(%rsp) - 4253fe: 48 89 cb mov %rcx,%rbx - 425401: 49 89 ec mov %rbp,%r12 - 425404: 4d 89 de mov %r11,%r14 - 425407: 49 89 c7 mov %rax,%r15 - 42540a: eb 0a jmp 425416 - 42540c: 0f 1f 40 00 nopl 0x0(%rax) - 425410: 49 01 c5 add %rax,%r13 - 425413: 48 89 ef mov %rbp,%rdi - 425416: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 42541b: 31 f6 xor %esi,%esi - 42541d: 49 8d 6c 05 00 lea 0x0(%r13,%rax,1),%rbp - 425422: 48 89 ea mov %rbp,%rdx - 425425: 48 29 fa sub %rdi,%rdx - 425428: 4c 01 ff add %r15,%rdi - 42542b: e8 10 07 00 00 callq 425b40 <__memchr> - 425430: 48 85 c0 test %rax,%rax - 425433: 0f 85 d1 00 00 00 jne 42550a - 425439: 48 85 ed test %rbp,%rbp - 42543c: 0f 84 c8 00 00 00 je 42550a - 425442: 41 0f b6 44 2f ff movzbl -0x1(%r15,%rbp,1),%eax - 425448: 48 8b 44 c4 50 mov 0x50(%rsp,%rax,8),%rax - 42544d: 48 85 c0 test %rax,%rax - 425450: 75 be jne 425410 - 425452: 48 8b 44 24 10 mov 0x10(%rsp),%rax - 425457: 49 8d 54 05 00 lea 0x0(%r13,%rax,1),%rdx - 42545c: 4c 01 fa add %r15,%rdx - 42545f: 48 39 d8 cmp %rbx,%rax - 425462: 73 2f jae 425493 - 425464: 48 8b 74 24 18 mov 0x18(%rsp),%rsi - 425469: 0f b6 36 movzbl (%rsi),%esi - 42546c: 40 38 32 cmp %sil,(%rdx) - 42546f: 75 7f jne 4254f0 - 425471: 48 03 54 24 20 add 0x20(%rsp),%rdx - 425476: 48 8b 4c 24 28 mov 0x28(%rsp),%rcx - 42547b: eb 0d jmp 42548a - 42547d: 0f 1f 00 nopl (%rax) - 425480: 0f b6 3c 02 movzbl (%rdx,%rax,1),%edi - 425484: 40 38 3c 01 cmp %dil,(%rcx,%rax,1) - 425488: 75 66 jne 4254f0 - 42548a: 48 83 c0 01 add $0x1,%rax - 42548e: 48 39 d8 cmp %rbx,%rax - 425491: 72 ed jb 425480 - 425493: 48 8b 44 24 30 mov 0x30(%rsp),%rax - 425498: 49 8d 74 05 00 lea 0x0(%r13,%rax,1),%rsi - 42549d: 4c 01 fe add %r15,%rsi - 4254a0: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 4254a4: 74 26 je 4254cc - 4254a6: 41 0f b6 04 24 movzbl (%r12),%eax - 4254ab: 38 06 cmp %al,(%rsi) - 4254ad: 75 51 jne 425500 - 4254af: 31 c0 xor %eax,%eax - 4254b1: eb 14 jmp 4254c7 - 4254b3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4254b8: 41 0f b6 54 04 ff movzbl -0x1(%r12,%rax,1),%edx - 4254be: 48 83 e8 01 sub $0x1,%rax - 4254c2: 3a 14 06 cmp (%rsi,%rax,1),%dl - 4254c5: 75 39 jne 425500 - 4254c7: 49 39 c6 cmp %rax,%r14 - 4254ca: 75 ec jne 4254b8 - 4254cc: 4c 89 f8 mov %r15,%rax - 4254cf: 4d 89 ef mov %r13,%r15 - 4254d2: 4a 8d 04 38 lea (%rax,%r15,1),%rax - 4254d6: 48 81 c4 58 08 00 00 add $0x858,%rsp - 4254dd: 5b pop %rbx - 4254de: 5d pop %rbp - 4254df: 41 5c pop %r12 - 4254e1: 41 5d pop %r13 - 4254e3: 41 5e pop %r14 - 4254e5: 41 5f pop %r15 - 4254e7: c3 retq - 4254e8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 4254ef: 00 - 4254f0: 4f 8d 04 2e lea (%r14,%r13,1),%r8 - 4254f4: 4e 8d 2c 00 lea (%rax,%r8,1),%r13 - 4254f8: e9 16 ff ff ff jmpq 425413 - 4254fd: 0f 1f 00 nopl (%rax) - 425500: 4c 03 6c 24 38 add 0x38(%rsp),%r13 - 425505: e9 09 ff ff ff jmpq 425413 - 42550a: 31 c0 xor %eax,%eax - 42550c: eb c8 jmp 4254d6 - 42550e: 48 89 54 24 08 mov %rdx,0x8(%rsp) - 425513: 48 89 c1 mov %rax,%rcx - 425516: ba 01 00 00 00 mov $0x1,%edx - 42551b: e9 a0 fb ff ff jmpq 4250c0 - 425520: 48 89 d7 mov %rdx,%rdi - 425523: 48 89 c1 mov %rax,%rcx - 425526: ba 01 00 00 00 mov $0x1,%edx - 42552b: e9 40 fb ff ff jmpq 425070 - 425530: 48 8b 44 24 10 mov 0x10(%rsp),%rax - 425535: e9 bc fd ff ff jmpq 4252f6 - 42553a: 4b 8d 44 3d 00 lea 0x0(%r13,%r15,1),%rax - 42553f: eb 95 jmp 4254d6 - 425541: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 425546: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42554d: 00 00 00 - -0000000000425550 <__strstr_sse2>: - 425550: 41 57 push %r15 - 425552: 41 56 push %r14 - 425554: 41 55 push %r13 - 425556: 41 54 push %r12 - 425558: 55 push %rbp - 425559: 53 push %rbx - 42555a: 48 83 ec 58 sub $0x58,%rsp - 42555e: 0f b6 17 movzbl (%rdi),%edx - 425561: 84 d2 test %dl,%dl - 425563: 0f 84 93 05 00 00 je 425afc <__strstr_sse2+0x5ac> - 425569: 0f b6 0e movzbl (%rsi),%ecx - 42556c: 84 c9 test %cl,%cl - 42556e: 0f 84 bc 00 00 00 je 425630 <__strstr_sse2+0xe0> - 425574: 48 89 f3 mov %rsi,%rbx - 425577: 49 89 f8 mov %rdi,%r8 - 42557a: 41 b9 01 00 00 00 mov $0x1,%r9d - 425580: eb 0d jmp 42558f <__strstr_sse2+0x3f> - 425582: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 425588: 0f b6 0b movzbl (%rbx),%ecx - 42558b: 84 c9 test %cl,%cl - 42558d: 74 1d je 4255ac <__strstr_sse2+0x5c> - 42558f: 49 83 c0 01 add $0x1,%r8 - 425593: 48 83 c3 01 add $0x1,%rbx - 425597: 38 ca cmp %cl,%dl - 425599: 41 0f b6 10 movzbl (%r8),%edx - 42559d: 0f 94 c0 sete %al - 4255a0: 41 21 c1 and %eax,%r9d - 4255a3: 84 d2 test %dl,%dl - 4255a5: 75 e1 jne 425588 <__strstr_sse2+0x38> - 4255a7: 80 3b 00 cmpb $0x0,(%rbx) - 4255aa: 75 6c jne 425618 <__strstr_sse2+0xc8> - 4255ac: 45 84 c9 test %r9b,%r9b - 4255af: 75 7f jne 425630 <__strstr_sse2+0xe0> - 4255b1: 49 89 dc mov %rbx,%r12 - 4255b4: 48 89 fd mov %rdi,%rbp - 4255b7: 48 8d 7f 01 lea 0x1(%rdi),%rdi - 4255bb: 49 29 f4 sub %rsi,%r12 - 4255be: 0f be 36 movsbl (%rsi),%esi - 4255c1: e8 ba ad fd ff callq 400380 <__rela_iplt_end+0xb8> - 4255c6: 48 85 c0 test %rax,%rax - 4255c9: 49 89 c7 mov %rax,%r15 - 4255cc: 74 4a je 425618 <__strstr_sse2+0xc8> - 4255ce: 49 83 fc 01 cmp $0x1,%r12 - 4255d2: 74 46 je 42561a <__strstr_sse2+0xca> - 4255d4: 4a 8d 7c 25 00 lea 0x0(%rbp,%r12,1),%rdi - 4255d9: 4c 29 e3 sub %r12,%rbx - 4255dc: 49 89 f8 mov %rdi,%r8 - 4255df: 49 29 c0 sub %rax,%r8 - 4255e2: 48 39 f8 cmp %rdi,%rax - 4255e5: b8 01 00 00 00 mov $0x1,%eax - 4255ea: 4c 0f 47 c0 cmova %rax,%r8 - 4255ee: 49 83 fc 1f cmp $0x1f,%r12 - 4255f2: 76 54 jbe 425648 <__strstr_sse2+0xf8> - 4255f4: 48 83 c4 58 add $0x58,%rsp - 4255f8: 4c 89 e1 mov %r12,%rcx - 4255fb: 48 89 da mov %rbx,%rdx - 4255fe: 4c 89 ff mov %r15,%rdi - 425601: 4c 89 c6 mov %r8,%rsi - 425604: 5b pop %rbx - 425605: 5d pop %rbp - 425606: 41 5c pop %r12 - 425608: 41 5d pop %r13 - 42560a: 41 5e pop %r14 - 42560c: 41 5f pop %r15 - 42560e: e9 2d fa ff ff jmpq 425040 - 425613: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 425618: 31 c0 xor %eax,%eax - 42561a: 48 83 c4 58 add $0x58,%rsp - 42561e: 5b pop %rbx - 42561f: 5d pop %rbp - 425620: 41 5c pop %r12 - 425622: 41 5d pop %r13 - 425624: 41 5e pop %r14 - 425626: 41 5f pop %r15 - 425628: c3 retq - 425629: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 425630: 48 83 c4 58 add $0x58,%rsp - 425634: 48 89 f8 mov %rdi,%rax - 425637: 5b pop %rbx - 425638: 5d pop %rbp - 425639: 41 5c pop %r12 - 42563b: 41 5d pop %r13 - 42563d: 41 5e pop %r14 - 42563f: 41 5f pop %r15 - 425641: c3 retq - 425642: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 425648: 41 be 01 00 00 00 mov $0x1,%r14d - 42564e: ba 01 00 00 00 mov $0x1,%edx - 425653: 31 f6 xor %esi,%esi - 425655: 48 c7 c1 ff ff ff ff mov $0xffffffffffffffff,%rcx - 42565c: 0f 1f 40 00 nopl 0x0(%rax) - 425660: 48 8d 04 32 lea (%rdx,%rsi,1),%rax - 425664: 49 39 c4 cmp %rax,%r12 - 425667: 76 29 jbe 425692 <__strstr_sse2+0x142> - 425669: 48 8d 3c 0b lea (%rbx,%rcx,1),%rdi - 42566d: 0f b6 3c 17 movzbl (%rdi,%rdx,1),%edi - 425671: 40 38 3c 03 cmp %dil,(%rbx,%rax,1) - 425675: 0f 83 f5 01 00 00 jae 425870 <__strstr_sse2+0x320> - 42567b: 48 89 c6 mov %rax,%rsi - 42567e: ba 01 00 00 00 mov $0x1,%edx - 425683: 49 89 c6 mov %rax,%r14 - 425686: 48 8d 04 32 lea (%rdx,%rsi,1),%rax - 42568a: 49 29 ce sub %rcx,%r14 - 42568d: 49 39 c4 cmp %rax,%r12 - 425690: 77 d7 ja 425669 <__strstr_sse2+0x119> - 425692: 41 bb 01 00 00 00 mov $0x1,%r11d - 425698: ba 01 00 00 00 mov $0x1,%edx - 42569d: 31 f6 xor %esi,%esi - 42569f: 48 c7 c7 ff ff ff ff mov $0xffffffffffffffff,%rdi - 4256a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4256ad: 00 00 00 - 4256b0: 48 8d 04 32 lea (%rdx,%rsi,1),%rax - 4256b4: 49 39 c4 cmp %rax,%r12 - 4256b7: 76 2a jbe 4256e3 <__strstr_sse2+0x193> - 4256b9: 4c 8d 0c 3b lea (%rbx,%rdi,1),%r9 - 4256bd: 45 0f b6 14 11 movzbl (%r9,%rdx,1),%r10d - 4256c2: 44 38 14 03 cmp %r10b,(%rbx,%rax,1) - 4256c6: 0f 86 c4 01 00 00 jbe 425890 <__strstr_sse2+0x340> - 4256cc: 48 89 c6 mov %rax,%rsi - 4256cf: ba 01 00 00 00 mov $0x1,%edx - 4256d4: 49 89 c3 mov %rax,%r11 - 4256d7: 48 8d 04 32 lea (%rdx,%rsi,1),%rax - 4256db: 49 29 fb sub %rdi,%r11 - 4256de: 49 39 c4 cmp %rax,%r12 - 4256e1: 77 d6 ja 4256b9 <__strstr_sse2+0x169> - 4256e3: 48 83 c7 01 add $0x1,%rdi - 4256e7: 48 83 c1 01 add $0x1,%rcx - 4256eb: 48 39 cf cmp %rcx,%rdi - 4256ee: 72 06 jb 4256f6 <__strstr_sse2+0x1a6> - 4256f0: 4d 89 de mov %r11,%r14 - 4256f3: 48 89 f9 mov %rdi,%rcx - 4256f6: 4a 8d 34 33 lea (%rbx,%r14,1),%rsi - 4256fa: 48 89 ca mov %rcx,%rdx - 4256fd: 48 89 df mov %rbx,%rdi - 425700: 4c 89 44 24 10 mov %r8,0x10(%rsp) - 425705: 48 89 4c 24 08 mov %rcx,0x8(%rsp) - 42570a: e8 21 ac fd ff callq 400330 <__rela_iplt_end+0x68> - 42570f: 85 c0 test %eax,%eax - 425711: 48 8b 4c 24 08 mov 0x8(%rsp),%rcx - 425716: 4c 8b 44 24 10 mov 0x10(%rsp),%r8 - 42571b: 0f 85 d1 01 00 00 jne 4258f2 <__strstr_sse2+0x3a2> - 425721: 48 8d 41 ff lea -0x1(%rcx),%rax - 425725: 4c 89 e7 mov %r12,%rdi - 425728: 45 31 ed xor %r13d,%r13d - 42572b: 4c 29 f7 sub %r14,%rdi - 42572e: 31 ed xor %ebp,%ebp - 425730: 4c 89 74 24 38 mov %r14,0x38(%rsp) - 425735: 48 89 44 24 18 mov %rax,0x18(%rsp) - 42573a: 48 89 7c 24 30 mov %rdi,0x30(%rsp) - 42573f: 48 01 d8 add %rbx,%rax - 425742: 48 89 cf mov %rcx,%rdi - 425745: 49 89 c2 mov %rax,%r10 - 425748: 48 89 44 24 28 mov %rax,0x28(%rsp) - 42574d: 48 f7 df neg %rdi - 425750: b8 01 00 00 00 mov $0x1,%eax - 425755: 4d 89 ee mov %r13,%r14 - 425758: 49 01 fa add %rdi,%r10 - 42575b: 48 29 c8 sub %rcx,%rax - 42575e: 48 89 7c 24 40 mov %rdi,0x40(%rsp) - 425763: 4d 89 e5 mov %r12,%r13 - 425766: 48 89 44 24 20 mov %rax,0x20(%rsp) - 42576b: 49 89 ec mov %rbp,%r12 - 42576e: 4c 89 c7 mov %r8,%rdi - 425771: 48 89 5c 24 10 mov %rbx,0x10(%rsp) - 425776: 4c 89 d5 mov %r10,%rbp - 425779: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 425780: 4b 8d 5c 25 00 lea 0x0(%r13,%r12,1),%rbx - 425785: 31 f6 xor %esi,%esi - 425787: 48 89 da mov %rbx,%rdx - 42578a: 48 29 fa sub %rdi,%rdx - 42578d: 4c 01 ff add %r15,%rdi - 425790: e8 ab 03 00 00 callq 425b40 <__memchr> - 425795: 48 85 c0 test %rax,%rax - 425798: 0f 85 7a fe ff ff jne 425618 <__strstr_sse2+0xc8> - 42579e: 48 85 db test %rbx,%rbx - 4257a1: 0f 84 71 fe ff ff je 425618 <__strstr_sse2+0xc8> - 4257a7: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 4257ac: 48 8b 4c 24 10 mov 0x10(%rsp),%rcx - 4257b1: 49 39 c6 cmp %rax,%r14 - 4257b4: 49 0f 43 c6 cmovae %r14,%rax - 4257b8: 4a 8d 34 20 lea (%rax,%r12,1),%rsi - 4257bc: 49 39 c5 cmp %rax,%r13 - 4257bf: 48 8d 14 01 lea (%rcx,%rax,1),%rdx - 4257c3: 49 8d 3c 37 lea (%r15,%rsi,1),%rdi - 4257c7: 76 36 jbe 4257ff <__strstr_sse2+0x2af> - 4257c9: 0f b6 0f movzbl (%rdi),%ecx - 4257cc: 38 0a cmp %cl,(%rdx) - 4257ce: 0f 85 dc 00 00 00 jne 4258b0 <__strstr_sse2+0x360> - 4257d4: 48 89 c6 mov %rax,%rsi - 4257d7: 48 f7 de neg %rsi - 4257da: 48 01 f2 add %rsi,%rdx - 4257dd: 48 01 fe add %rdi,%rsi - 4257e0: eb 14 jmp 4257f6 <__strstr_sse2+0x2a6> - 4257e2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4257e8: 0f b6 3c 06 movzbl (%rsi,%rax,1),%edi - 4257ec: 40 38 3c 02 cmp %dil,(%rdx,%rax,1) - 4257f0: 0f 85 ba 00 00 00 jne 4258b0 <__strstr_sse2+0x360> - 4257f6: 48 83 c0 01 add $0x1,%rax - 4257fa: 49 39 c5 cmp %rax,%r13 - 4257fd: 77 e9 ja 4257e8 <__strstr_sse2+0x298> - 4257ff: 48 8b 44 24 18 mov 0x18(%rsp),%rax - 425804: 49 8d 34 04 lea (%r12,%rax,1),%rsi - 425808: 4c 01 fe add %r15,%rsi - 42580b: 4c 3b 74 24 08 cmp 0x8(%rsp),%r14 - 425810: 0f 83 9d 02 00 00 jae 425ab3 <__strstr_sse2+0x563> - 425816: 48 8b 7c 24 28 mov 0x28(%rsp),%rdi - 42581b: 0f b6 0e movzbl (%rsi),%ecx - 42581e: 38 0f cmp %cl,(%rdi) - 425820: 0f 85 8d 02 00 00 jne 425ab3 <__strstr_sse2+0x563> - 425826: 48 03 74 24 40 add 0x40(%rsp),%rsi - 42582b: eb 15 jmp 425842 <__strstr_sse2+0x2f2> - 42582d: 0f 1f 00 nopl (%rax) - 425830: 48 8d 50 ff lea -0x1(%rax),%rdx - 425834: 0f b6 4c 32 01 movzbl 0x1(%rdx,%rsi,1),%ecx - 425839: 38 4c 05 00 cmp %cl,0x0(%rbp,%rax,1) - 42583d: 75 08 jne 425847 <__strstr_sse2+0x2f7> - 42583f: 48 89 d0 mov %rdx,%rax - 425842: 49 39 c6 cmp %rax,%r14 - 425845: 75 e9 jne 425830 <__strstr_sse2+0x2e0> - 425847: 4d 8d 4e 01 lea 0x1(%r14),%r9 - 42584b: 49 39 c1 cmp %rax,%r9 - 42584e: 0f 87 b6 02 00 00 ja 425b0a <__strstr_sse2+0x5ba> - 425854: 4c 03 64 24 38 add 0x38(%rsp),%r12 - 425859: 4c 8b 74 24 30 mov 0x30(%rsp),%r14 - 42585e: 48 89 df mov %rbx,%rdi - 425861: e9 1a ff ff ff jmpq 425780 <__strstr_sse2+0x230> - 425866: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42586d: 00 00 00 - 425870: 74 56 je 4258c8 <__strstr_sse2+0x378> - 425872: 48 89 f1 mov %rsi,%rcx - 425875: 41 be 01 00 00 00 mov $0x1,%r14d - 42587b: 48 83 c6 01 add $0x1,%rsi - 42587f: ba 01 00 00 00 mov $0x1,%edx - 425884: e9 d7 fd ff ff jmpq 425660 <__strstr_sse2+0x110> - 425889: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 425890: 74 4e je 4258e0 <__strstr_sse2+0x390> - 425892: 48 89 f7 mov %rsi,%rdi - 425895: 41 bb 01 00 00 00 mov $0x1,%r11d - 42589b: 48 83 c6 01 add $0x1,%rsi - 42589f: ba 01 00 00 00 mov $0x1,%edx - 4258a4: e9 07 fe ff ff jmpq 4256b0 <__strstr_sse2+0x160> - 4258a9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4258b0: 48 8b 4c 24 20 mov 0x20(%rsp),%rcx - 4258b5: 45 31 f6 xor %r14d,%r14d - 4258b8: 4e 8d 1c 21 lea (%rcx,%r12,1),%r11 - 4258bc: 4e 8d 24 18 lea (%rax,%r11,1),%r12 - 4258c0: eb 9c jmp 42585e <__strstr_sse2+0x30e> - 4258c2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4258c8: 4c 39 f2 cmp %r14,%rdx - 4258cb: 0f 84 ae 01 00 00 je 425a7f <__strstr_sse2+0x52f> - 4258d1: 48 83 c2 01 add $0x1,%rdx - 4258d5: e9 86 fd ff ff jmpq 425660 <__strstr_sse2+0x110> - 4258da: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4258e0: 4c 39 da cmp %r11,%rdx - 4258e3: 0f 84 a6 01 00 00 je 425a8f <__strstr_sse2+0x53f> - 4258e9: 48 83 c2 01 add $0x1,%rdx - 4258ed: e9 be fd ff ff jmpq 4256b0 <__strstr_sse2+0x160> - 4258f2: 4c 8d 51 01 lea 0x1(%rcx),%r10 - 4258f6: 49 8d 04 0f lea (%r15,%rcx,1),%rax - 4258fa: 48 8d 2c 0b lea (%rbx,%rcx,1),%rbp - 4258fe: 4d 39 d0 cmp %r10,%r8 - 425901: 48 89 44 24 18 mov %rax,0x18(%rsp) - 425906: 0f 82 b1 01 00 00 jb 425abd <__strstr_sse2+0x56d> - 42590c: 4c 89 e0 mov %r12,%rax - 42590f: 44 0f b6 4d 00 movzbl 0x0(%rbp),%r9d - 425914: 41 be 01 00 00 00 mov $0x1,%r14d - 42591a: 48 29 c8 sub %rcx,%rax - 42591d: 48 89 4c 24 38 mov %rcx,0x38(%rsp) - 425922: 48 8b 54 24 18 mov 0x18(%rsp),%rdx - 425927: 48 39 c8 cmp %rcx,%rax - 42592a: 4c 89 54 24 20 mov %r10,0x20(%rsp) - 42592f: 48 0f 42 c1 cmovb %rcx,%rax - 425933: 49 29 ce sub %rcx,%r14 - 425936: 48 83 c0 01 add $0x1,%rax - 42593a: 48 89 44 24 40 mov %rax,0x40(%rsp) - 42593f: 48 8d 41 ff lea -0x1(%rcx),%rax - 425943: 48 89 c7 mov %rax,%rdi - 425946: 48 89 44 24 48 mov %rax,0x48(%rsp) - 42594b: 4a 8d 04 13 lea (%rbx,%r10,1),%rax - 42594f: 48 01 fb add %rdi,%rbx - 425952: 48 89 cf mov %rcx,%rdi - 425955: 4c 89 f1 mov %r14,%rcx - 425958: 48 f7 df neg %rdi - 42595b: 49 89 c5 mov %rax,%r13 - 42595e: 4d 89 fe mov %r15,%r14 - 425961: 48 89 7c 24 30 mov %rdi,0x30(%rsp) - 425966: 49 01 fd add %rdi,%r13 - 425969: 49 89 df mov %rbx,%r15 - 42596c: 48 89 44 24 28 mov %rax,0x28(%rsp) - 425971: 4c 89 c7 mov %r8,%rdi - 425974: 44 89 cb mov %r9d,%ebx - 425977: eb 12 jmp 42598b <__strstr_sse2+0x43b> - 425979: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 425980: 84 c0 test %al,%al - 425982: 0f 84 90 fc ff ff je 425618 <__strstr_sse2+0xc8> - 425988: 48 89 ea mov %rbp,%rdx - 42598b: 0f b6 02 movzbl (%rdx),%eax - 42598e: 48 8d 6a 01 lea 0x1(%rdx),%rbp - 425992: 38 c3 cmp %al,%bl - 425994: 75 ea jne 425980 <__strstr_sse2+0x430> - 425996: 48 2b 6c 24 18 sub 0x18(%rsp),%rbp - 42599b: 4c 8b 54 24 20 mov 0x20(%rsp),%r10 - 4259a0: 4d 39 d4 cmp %r10,%r12 - 4259a3: 48 8d 45 ff lea -0x1(%rbp),%rax - 4259a7: 76 35 jbe 4259de <__strstr_sse2+0x48e> - 4259a9: 0f b6 72 01 movzbl 0x1(%rdx),%esi - 4259ad: 4c 8d 42 02 lea 0x2(%rdx),%r8 - 4259b1: 48 8b 54 24 28 mov 0x28(%rsp),%rdx - 4259b6: 40 38 32 cmp %sil,(%rdx) - 4259b9: 4c 89 d2 mov %r10,%rdx - 4259bc: 75 67 jne 425a25 <__strstr_sse2+0x4d5> - 4259be: 4c 03 44 24 30 add 0x30(%rsp),%r8 - 4259c3: eb 10 jmp 4259d5 <__strstr_sse2+0x485> - 4259c5: 0f 1f 00 nopl (%rax) - 4259c8: 41 0f b6 74 10 fe movzbl -0x2(%r8,%rdx,1),%esi - 4259ce: 41 38 74 15 ff cmp %sil,-0x1(%r13,%rdx,1) - 4259d3: 75 50 jne 425a25 <__strstr_sse2+0x4d5> - 4259d5: 48 83 c2 01 add $0x1,%rdx - 4259d9: 49 39 d4 cmp %rdx,%r12 - 4259dc: 77 ea ja 4259c8 <__strstr_sse2+0x478> - 4259de: 48 8b 74 24 48 mov 0x48(%rsp),%rsi - 4259e3: 48 8d 2c 30 lea (%rax,%rsi,1),%rbp - 4259e7: 4c 01 f5 add %r14,%rbp - 4259ea: 48 83 fe ff cmp $0xffffffffffffffff,%rsi - 4259ee: 74 2d je 425a1d <__strstr_sse2+0x4cd> - 4259f0: 0f b6 75 00 movzbl 0x0(%rbp),%esi - 4259f4: 31 d2 xor %edx,%edx - 4259f6: 41 3a 37 cmp (%r15),%sil - 4259f9: 74 1d je 425a18 <__strstr_sse2+0x4c8> - 4259fb: e9 9f 00 00 00 jmpq 425a9f <__strstr_sse2+0x54f> - 425a00: 45 0f b6 44 17 ff movzbl -0x1(%r15,%rdx,1),%r8d - 425a06: 48 83 ea 01 sub $0x1,%rdx - 425a0a: 0f b6 74 15 00 movzbl 0x0(%rbp,%rdx,1),%esi - 425a0f: 41 38 f0 cmp %sil,%r8b - 425a12: 0f 85 87 00 00 00 jne 425a9f <__strstr_sse2+0x54f> - 425a18: 48 39 d1 cmp %rdx,%rcx - 425a1b: 75 e3 jne 425a00 <__strstr_sse2+0x4b0> - 425a1d: 4c 01 f0 add %r14,%rax - 425a20: e9 f5 fb ff ff jmpq 42561a <__strstr_sse2+0xca> - 425a25: 40 84 f6 test %sil,%sil - 425a28: 0f 84 ea fb ff ff je 425618 <__strstr_sse2+0xc8> - 425a2e: 48 8d 2c 01 lea (%rcx,%rax,1),%rbp - 425a32: 48 01 d5 add %rdx,%rbp - 425a35: 4d 8d 04 2c lea (%r12,%rbp,1),%r8 - 425a39: 31 f6 xor %esi,%esi - 425a3b: 48 89 4c 24 10 mov %rcx,0x10(%rsp) - 425a40: 4c 89 c2 mov %r8,%rdx - 425a43: 4c 89 44 24 08 mov %r8,0x8(%rsp) - 425a48: 48 29 fa sub %rdi,%rdx - 425a4b: 4c 01 f7 add %r14,%rdi - 425a4e: e8 ed 00 00 00 callq 425b40 <__memchr> - 425a53: 4c 8b 44 24 08 mov 0x8(%rsp),%r8 - 425a58: 4d 85 c0 test %r8,%r8 - 425a5b: 0f 84 b7 fb ff ff je 425618 <__strstr_sse2+0xc8> - 425a61: 48 85 c0 test %rax,%rax - 425a64: 0f 85 ae fb ff ff jne 425618 <__strstr_sse2+0xc8> - 425a6a: 48 03 6c 24 38 add 0x38(%rsp),%rbp - 425a6f: 4c 89 c7 mov %r8,%rdi - 425a72: 48 8b 4c 24 10 mov 0x10(%rsp),%rcx - 425a77: 4c 01 f5 add %r14,%rbp - 425a7a: e9 09 ff ff ff jmpq 425988 <__strstr_sse2+0x438> - 425a7f: 49 89 d6 mov %rdx,%r14 - 425a82: 48 89 c6 mov %rax,%rsi - 425a85: ba 01 00 00 00 mov $0x1,%edx - 425a8a: e9 d1 fb ff ff jmpq 425660 <__strstr_sse2+0x110> - 425a8f: 49 89 d3 mov %rdx,%r11 - 425a92: 48 89 c6 mov %rax,%rsi - 425a95: ba 01 00 00 00 mov $0x1,%edx - 425a9a: e9 11 fc ff ff jmpq 4256b0 <__strstr_sse2+0x160> - 425a9f: 40 84 f6 test %sil,%sil - 425aa2: 0f 84 70 fb ff ff je 425618 <__strstr_sse2+0xc8> - 425aa8: 48 8b 74 24 40 mov 0x40(%rsp),%rsi - 425aad: 48 8d 2c 06 lea (%rsi,%rax,1),%rbp - 425ab1: eb 82 jmp 425a35 <__strstr_sse2+0x4e5> - 425ab3: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 425ab8: e9 8a fd ff ff jmpq 425847 <__strstr_sse2+0x2f7> - 425abd: 48 89 c8 mov %rcx,%rax - 425ac0: 4b 8d 3c 07 lea (%r15,%r8,1),%rdi - 425ac4: 31 f6 xor %esi,%esi - 425ac6: 4c 29 c0 sub %r8,%rax - 425ac9: 4c 89 54 24 10 mov %r10,0x10(%rsp) - 425ace: 48 89 4c 24 08 mov %rcx,0x8(%rsp) - 425ad3: 48 8d 50 01 lea 0x1(%rax),%rdx - 425ad7: e8 64 00 00 00 callq 425b40 <__memchr> - 425adc: 48 89 c2 mov %rax,%rdx - 425adf: 31 c0 xor %eax,%eax - 425ae1: 48 85 d2 test %rdx,%rdx - 425ae4: 0f 85 30 fb ff ff jne 42561a <__strstr_sse2+0xca> - 425aea: 4c 8b 54 24 10 mov 0x10(%rsp),%r10 - 425aef: 48 8b 4c 24 08 mov 0x8(%rsp),%rcx - 425af4: 4d 89 d0 mov %r10,%r8 - 425af7: e9 10 fe ff ff jmpq 42590c <__strstr_sse2+0x3bc> - 425afc: 48 89 f3 mov %rsi,%rbx - 425aff: 41 b9 01 00 00 00 mov $0x1,%r9d - 425b05: e9 9d fa ff ff jmpq 4255a7 <__strstr_sse2+0x57> - 425b0a: 4b 8d 04 27 lea (%r15,%r12,1),%rax - 425b0e: e9 07 fb ff ff jmpq 42561a <__strstr_sse2+0xca> - 425b13: 0f 1f 00 nopl (%rax) - 425b16: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 425b1d: 00 00 00 - -0000000000425b20 <__libc_strstr>: - 425b20: f6 05 99 6b 2a 00 10 testb $0x10,0x2a6b99(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> - 425b27: ba 50 55 42 00 mov $0x425550,%edx - 425b2c: b8 a0 d4 43 00 mov $0x43d4a0,%eax - 425b31: 48 0f 44 c2 cmove %rdx,%rax - 425b35: c3 retq - 425b36: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 425b3d: 00 00 00 - -0000000000425b40 <__memchr>: - 425b40: 66 48 0f 6e ce movq %rsi,%xmm1 - 425b45: 48 89 f9 mov %rdi,%rcx - 425b48: 66 0f 60 c9 punpcklbw %xmm1,%xmm1 - 425b4c: 48 85 d2 test %rdx,%rdx - 425b4f: 0f 84 2b 03 00 00 je 425e80 <__memchr+0x340> - 425b55: 66 0f 60 c9 punpcklbw %xmm1,%xmm1 - 425b59: 48 83 e1 3f and $0x3f,%rcx - 425b5d: 66 0f 70 c9 00 pshufd $0x0,%xmm1,%xmm1 - 425b62: 48 83 f9 30 cmp $0x30,%rcx - 425b66: 77 48 ja 425bb0 <__memchr+0x70> - 425b68: f3 0f 6f 07 movdqu (%rdi),%xmm0 - 425b6c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 425b70: 66 0f d7 c0 pmovmskb %xmm0,%eax - 425b74: 85 c0 test %eax,%eax - 425b76: 0f 85 c4 02 00 00 jne 425e40 <__memchr+0x300> - 425b7c: 48 83 ea 10 sub $0x10,%rdx - 425b80: 0f 86 fa 02 00 00 jbe 425e80 <__memchr+0x340> - 425b86: 48 83 c7 10 add $0x10,%rdi - 425b8a: 48 83 e1 0f and $0xf,%rcx - 425b8e: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi - 425b92: 48 01 ca add %rcx,%rdx - 425b95: 48 83 ea 40 sub $0x40,%rdx - 425b99: 0f 86 c1 01 00 00 jbe 425d60 <__memchr+0x220> - 425b9f: eb 5f jmp 425c00 <__memchr+0xc0> - 425ba1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 425ba6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 425bad: 00 00 00 - 425bb0: 48 83 e1 0f and $0xf,%rcx - 425bb4: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi - 425bb8: 66 0f 6f 07 movdqa (%rdi),%xmm0 - 425bbc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 425bc0: 66 0f d7 c0 pmovmskb %xmm0,%eax - 425bc4: d3 f8 sar %cl,%eax - 425bc6: 85 c0 test %eax,%eax - 425bc8: 74 16 je 425be0 <__memchr+0xa0> - 425bca: 0f bc c0 bsf %eax,%eax - 425bcd: 48 29 c2 sub %rax,%rdx - 425bd0: 0f 86 aa 02 00 00 jbe 425e80 <__memchr+0x340> - 425bd6: 48 01 f8 add %rdi,%rax - 425bd9: 48 01 c8 add %rcx,%rax - 425bdc: c3 retq - 425bdd: 0f 1f 00 nopl (%rax) - 425be0: 48 01 ca add %rcx,%rdx - 425be3: 48 83 ea 10 sub $0x10,%rdx - 425be7: 0f 86 93 02 00 00 jbe 425e80 <__memchr+0x340> - 425bed: 48 83 c7 10 add $0x10,%rdi - 425bf1: 48 83 ea 40 sub $0x40,%rdx - 425bf5: 0f 86 65 01 00 00 jbe 425d60 <__memchr+0x220> - 425bfb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 425c00: 66 0f 6f 07 movdqa (%rdi),%xmm0 - 425c04: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 425c08: 66 0f d7 c0 pmovmskb %xmm0,%eax - 425c0c: 85 c0 test %eax,%eax - 425c0e: 0f 85 fc 01 00 00 jne 425e10 <__memchr+0x2d0> - 425c14: 66 0f 6f 57 10 movdqa 0x10(%rdi),%xmm2 - 425c19: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 425c1d: 66 0f d7 c2 pmovmskb %xmm2,%eax - 425c21: 85 c0 test %eax,%eax - 425c23: 0f 85 f7 01 00 00 jne 425e20 <__memchr+0x2e0> - 425c29: 66 0f 6f 5f 20 movdqa 0x20(%rdi),%xmm3 - 425c2e: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 - 425c32: 66 0f d7 c3 pmovmskb %xmm3,%eax - 425c36: 85 c0 test %eax,%eax - 425c38: 0f 85 f2 01 00 00 jne 425e30 <__memchr+0x2f0> - 425c3e: 66 0f 6f 67 30 movdqa 0x30(%rdi),%xmm4 - 425c43: 66 0f 74 e1 pcmpeqb %xmm1,%xmm4 - 425c47: 48 83 c7 40 add $0x40,%rdi - 425c4b: 66 0f d7 c4 pmovmskb %xmm4,%eax - 425c4f: 85 c0 test %eax,%eax - 425c51: 0f 85 a9 01 00 00 jne 425e00 <__memchr+0x2c0> - 425c57: 48 f7 c7 3f 00 00 00 test $0x3f,%rdi - 425c5e: 74 70 je 425cd0 <__memchr+0x190> - 425c60: 48 83 ea 40 sub $0x40,%rdx - 425c64: 0f 86 f6 00 00 00 jbe 425d60 <__memchr+0x220> - 425c6a: 66 0f 6f 07 movdqa (%rdi),%xmm0 - 425c6e: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 425c72: 66 0f d7 c0 pmovmskb %xmm0,%eax - 425c76: 85 c0 test %eax,%eax - 425c78: 0f 85 92 01 00 00 jne 425e10 <__memchr+0x2d0> - 425c7e: 66 0f 6f 57 10 movdqa 0x10(%rdi),%xmm2 - 425c83: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 425c87: 66 0f d7 c2 pmovmskb %xmm2,%eax - 425c8b: 85 c0 test %eax,%eax - 425c8d: 0f 85 8d 01 00 00 jne 425e20 <__memchr+0x2e0> - 425c93: 66 0f 6f 5f 20 movdqa 0x20(%rdi),%xmm3 - 425c98: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 - 425c9c: 66 0f d7 c3 pmovmskb %xmm3,%eax - 425ca0: 85 c0 test %eax,%eax - 425ca2: 0f 85 88 01 00 00 jne 425e30 <__memchr+0x2f0> - 425ca8: 66 0f 6f 5f 30 movdqa 0x30(%rdi),%xmm3 - 425cad: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 - 425cb1: 66 0f d7 c3 pmovmskb %xmm3,%eax - 425cb5: 48 83 c7 40 add $0x40,%rdi - 425cb9: 85 c0 test %eax,%eax - 425cbb: 0f 85 3f 01 00 00 jne 425e00 <__memchr+0x2c0> - 425cc1: 48 89 f9 mov %rdi,%rcx - 425cc4: 48 83 e7 c0 and $0xffffffffffffffc0,%rdi - 425cc8: 48 83 e1 3f and $0x3f,%rcx - 425ccc: 48 01 ca add %rcx,%rdx - 425ccf: 90 nop - 425cd0: 48 83 ea 40 sub $0x40,%rdx - 425cd4: 0f 86 86 00 00 00 jbe 425d60 <__memchr+0x220> - 425cda: 66 0f 6f 07 movdqa (%rdi),%xmm0 - 425cde: 66 0f 6f 57 10 movdqa 0x10(%rdi),%xmm2 - 425ce3: 66 0f 6f 5f 20 movdqa 0x20(%rdi),%xmm3 - 425ce8: 66 0f 6f 67 30 movdqa 0x30(%rdi),%xmm4 - 425ced: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 425cf1: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 425cf5: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 - 425cf9: 66 0f 74 e1 pcmpeqb %xmm1,%xmm4 - 425cfd: 66 0f de d8 pmaxub %xmm0,%xmm3 - 425d01: 66 0f de e2 pmaxub %xmm2,%xmm4 - 425d05: 66 0f de e3 pmaxub %xmm3,%xmm4 - 425d09: 66 0f d7 c4 pmovmskb %xmm4,%eax - 425d0d: 48 83 c7 40 add $0x40,%rdi - 425d11: 85 c0 test %eax,%eax - 425d13: 74 bb je 425cd0 <__memchr+0x190> - 425d15: 48 83 ef 40 sub $0x40,%rdi - 425d19: 66 0f d7 c0 pmovmskb %xmm0,%eax - 425d1d: 85 c0 test %eax,%eax - 425d1f: 0f 85 eb 00 00 00 jne 425e10 <__memchr+0x2d0> - 425d25: 66 0f d7 c2 pmovmskb %xmm2,%eax - 425d29: 85 c0 test %eax,%eax - 425d2b: 0f 85 ef 00 00 00 jne 425e20 <__memchr+0x2e0> - 425d31: 66 0f 6f 5f 20 movdqa 0x20(%rdi),%xmm3 - 425d36: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 - 425d3a: 66 0f 74 4f 30 pcmpeqb 0x30(%rdi),%xmm1 - 425d3f: 66 0f d7 c3 pmovmskb %xmm3,%eax - 425d43: 85 c0 test %eax,%eax - 425d45: 0f 85 e5 00 00 00 jne 425e30 <__memchr+0x2f0> - 425d4b: 66 0f d7 c1 pmovmskb %xmm1,%eax - 425d4f: 0f bc c0 bsf %eax,%eax - 425d52: 48 8d 44 07 30 lea 0x30(%rdi,%rax,1),%rax - 425d57: c3 retq - 425d58: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 425d5f: 00 - 425d60: 48 83 c2 20 add $0x20,%rdx - 425d64: 7e 6a jle 425dd0 <__memchr+0x290> - 425d66: 66 0f 6f 07 movdqa (%rdi),%xmm0 - 425d6a: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 425d6e: 66 0f d7 c0 pmovmskb %xmm0,%eax - 425d72: 85 c0 test %eax,%eax - 425d74: 0f 85 96 00 00 00 jne 425e10 <__memchr+0x2d0> - 425d7a: 66 0f 6f 57 10 movdqa 0x10(%rdi),%xmm2 - 425d7f: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 425d83: 66 0f d7 c2 pmovmskb %xmm2,%eax - 425d87: 85 c0 test %eax,%eax - 425d89: 0f 85 91 00 00 00 jne 425e20 <__memchr+0x2e0> - 425d8f: 66 0f 6f 5f 20 movdqa 0x20(%rdi),%xmm3 - 425d94: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 - 425d98: 66 0f d7 c3 pmovmskb %xmm3,%eax - 425d9c: 85 c0 test %eax,%eax - 425d9e: 0f 85 bc 00 00 00 jne 425e60 <__memchr+0x320> - 425da4: 48 83 ea 10 sub $0x10,%rdx - 425da8: 0f 8e d2 00 00 00 jle 425e80 <__memchr+0x340> - 425dae: 66 0f 74 4f 30 pcmpeqb 0x30(%rdi),%xmm1 - 425db3: 66 0f d7 c1 pmovmskb %xmm1,%eax - 425db7: 85 c0 test %eax,%eax - 425db9: 0f 85 b1 00 00 00 jne 425e70 <__memchr+0x330> - 425dbf: 48 31 c0 xor %rax,%rax - 425dc2: c3 retq - 425dc3: 0f 1f 00 nopl (%rax) - 425dc6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 425dcd: 00 00 00 - 425dd0: 48 83 c2 20 add $0x20,%rdx - 425dd4: 66 0f 6f 07 movdqa (%rdi),%xmm0 - 425dd8: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 425ddc: 66 0f d7 c0 pmovmskb %xmm0,%eax - 425de0: 85 c0 test %eax,%eax - 425de2: 75 5c jne 425e40 <__memchr+0x300> - 425de4: 48 83 ea 10 sub $0x10,%rdx - 425de8: 0f 86 92 00 00 00 jbe 425e80 <__memchr+0x340> - 425dee: 66 0f 74 4f 10 pcmpeqb 0x10(%rdi),%xmm1 - 425df3: 66 0f d7 c1 pmovmskb %xmm1,%eax - 425df7: 85 c0 test %eax,%eax - 425df9: 75 55 jne 425e50 <__memchr+0x310> - 425dfb: 48 31 c0 xor %rax,%rax - 425dfe: c3 retq - 425dff: 90 nop - 425e00: 0f bc c0 bsf %eax,%eax - 425e03: 48 8d 44 38 f0 lea -0x10(%rax,%rdi,1),%rax - 425e08: c3 retq - 425e09: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 425e10: 0f bc c0 bsf %eax,%eax - 425e13: 48 01 f8 add %rdi,%rax - 425e16: c3 retq - 425e17: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 425e1e: 00 00 - 425e20: 0f bc c0 bsf %eax,%eax - 425e23: 48 8d 44 38 10 lea 0x10(%rax,%rdi,1),%rax - 425e28: c3 retq - 425e29: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 425e30: 0f bc c0 bsf %eax,%eax - 425e33: 48 8d 44 38 20 lea 0x20(%rax,%rdi,1),%rax - 425e38: c3 retq - 425e39: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 425e40: 0f bc c0 bsf %eax,%eax - 425e43: 48 29 c2 sub %rax,%rdx - 425e46: 76 38 jbe 425e80 <__memchr+0x340> - 425e48: 48 01 f8 add %rdi,%rax - 425e4b: c3 retq - 425e4c: 0f 1f 40 00 nopl 0x0(%rax) - 425e50: 0f bc c0 bsf %eax,%eax - 425e53: 48 29 c2 sub %rax,%rdx - 425e56: 76 28 jbe 425e80 <__memchr+0x340> - 425e58: 48 8d 44 07 10 lea 0x10(%rdi,%rax,1),%rax - 425e5d: c3 retq - 425e5e: 66 90 xchg %ax,%ax - 425e60: 0f bc c0 bsf %eax,%eax - 425e63: 48 29 c2 sub %rax,%rdx - 425e66: 76 18 jbe 425e80 <__memchr+0x340> - 425e68: 48 8d 44 07 20 lea 0x20(%rdi,%rax,1),%rax - 425e6d: c3 retq - 425e6e: 66 90 xchg %ax,%ax - 425e70: 0f bc c0 bsf %eax,%eax - 425e73: 48 29 c2 sub %rax,%rdx - 425e76: 76 08 jbe 425e80 <__memchr+0x340> - 425e78: 48 8d 44 07 30 lea 0x30(%rdi,%rax,1),%rax - 425e7d: c3 retq - 425e7e: 66 90 xchg %ax,%ax - 425e80: 48 31 c0 xor %rax,%rax - 425e83: c3 retq - 425e84: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 425e8b: 00 00 00 - 425e8e: 66 90 xchg %ax,%ax - -0000000000425e90 : - 425e90: f7 05 f6 67 2a 00 00 testl $0x200,0x2a67f6(%rip) # 6cc690 <_dl_x86_cpu_features+0x10> - 425e97: 02 00 00 - 425e9a: 75 08 jne 425ea4 - 425e9c: 48 8d 05 1d 00 00 00 lea 0x1d(%rip),%rax # 425ec0 <__memcmp_sse2> - 425ea3: c3 retq - 425ea4: f7 05 e2 67 2a 00 00 testl $0x80000,0x2a67e2(%rip) # 6cc690 <_dl_x86_cpu_features+0x10> - 425eab: 00 08 00 - 425eae: 74 08 je 425eb8 - 425eb0: 48 8d 05 49 84 00 00 lea 0x8449(%rip),%rax # 42e300 <__memcmp_sse4_1> - 425eb7: c3 retq - 425eb8: 48 8d 05 71 5e 01 00 lea 0x15e71(%rip),%rax # 43bd30 <__memcmp_ssse3> - 425ebf: c3 retq - -0000000000425ec0 <__memcmp_sse2>: - 425ec0: 48 85 d2 test %rdx,%rdx - 425ec3: 0f 84 f7 00 00 00 je 425fc0 <__memcmp_sse2+0x100> - 425ec9: 48 83 fa 01 cmp $0x1,%rdx - 425ecd: 0f 8e bd 00 00 00 jle 425f90 <__memcmp_sse2+0xd0> - 425ed3: 48 29 fe sub %rdi,%rsi - 425ed6: 49 89 d2 mov %rdx,%r10 - 425ed9: 49 83 fa 20 cmp $0x20,%r10 - 425edd: 0f 8d e0 00 00 00 jge 425fc3 <__memcmp_sse2+0x103> - 425ee3: 49 f7 c2 01 00 00 00 test $0x1,%r10 - 425eea: 74 1d je 425f09 <__memcmp_sse2+0x49> - 425eec: 0f b6 07 movzbl (%rdi),%eax - 425eef: 0f b6 14 37 movzbl (%rdi,%rsi,1),%edx - 425ef3: 49 83 ea 01 sub $0x1,%r10 - 425ef7: 0f 84 99 00 00 00 je 425f96 <__memcmp_sse2+0xd6> - 425efd: 48 83 c7 01 add $0x1,%rdi - 425f01: 29 d0 sub %edx,%eax - 425f03: 0f 85 8f 00 00 00 jne 425f98 <__memcmp_sse2+0xd8> - 425f09: 49 f7 c2 02 00 00 00 test $0x2,%r10 - 425f10: 74 15 je 425f27 <__memcmp_sse2+0x67> - 425f12: 0f b7 07 movzwl (%rdi),%eax - 425f15: 0f b7 14 37 movzwl (%rdi,%rsi,1),%edx - 425f19: 49 83 ea 02 sub $0x2,%r10 - 425f1d: 74 7a je 425f99 <__memcmp_sse2+0xd9> - 425f1f: 48 83 c7 02 add $0x2,%rdi - 425f23: 39 d0 cmp %edx,%eax - 425f25: 75 72 jne 425f99 <__memcmp_sse2+0xd9> - 425f27: 49 f7 c2 04 00 00 00 test $0x4,%r10 - 425f2e: 74 13 je 425f43 <__memcmp_sse2+0x83> - 425f30: 8b 07 mov (%rdi),%eax - 425f32: 8b 14 37 mov (%rdi,%rsi,1),%edx - 425f35: 49 83 ea 04 sub $0x4,%r10 - 425f39: 74 5e je 425f99 <__memcmp_sse2+0xd9> - 425f3b: 48 83 c7 04 add $0x4,%rdi - 425f3f: 39 d0 cmp %edx,%eax - 425f41: 75 56 jne 425f99 <__memcmp_sse2+0xd9> - 425f43: 49 f7 c2 08 00 00 00 test $0x8,%r10 - 425f4a: 74 16 je 425f62 <__memcmp_sse2+0xa2> - 425f4c: 48 8b 07 mov (%rdi),%rax - 425f4f: 48 8b 14 37 mov (%rdi,%rsi,1),%rdx - 425f53: 49 83 ea 08 sub $0x8,%r10 - 425f57: 74 40 je 425f99 <__memcmp_sse2+0xd9> - 425f59: 48 83 c7 08 add $0x8,%rdi - 425f5d: 48 39 d0 cmp %rdx,%rax - 425f60: 75 37 jne 425f99 <__memcmp_sse2+0xd9> - 425f62: f3 0f 6f 0f movdqu (%rdi),%xmm1 - 425f66: f3 0f 6f 04 37 movdqu (%rdi,%rsi,1),%xmm0 - 425f6b: 66 0f 74 c8 pcmpeqb %xmm0,%xmm1 - 425f6f: 66 0f d7 d1 pmovmskb %xmm1,%edx - 425f73: 31 c0 xor %eax,%eax - 425f75: 81 ea ff ff 00 00 sub $0xffff,%edx - 425f7b: 74 43 je 425fc0 <__memcmp_sse2+0x100> - 425f7d: 0f bc ca bsf %edx,%ecx - 425f80: 48 8d 0c 0f lea (%rdi,%rcx,1),%rcx - 425f84: 0f b6 01 movzbl (%rcx),%eax - 425f87: 0f b6 14 0e movzbl (%rsi,%rcx,1),%edx - 425f8b: eb 09 jmp 425f96 <__memcmp_sse2+0xd6> - 425f8d: 0f 1f 00 nopl (%rax) - 425f90: 0f b6 07 movzbl (%rdi),%eax - 425f93: 0f b6 16 movzbl (%rsi),%edx - 425f96: 29 d0 sub %edx,%eax - 425f98: c3 retq - 425f99: 48 39 d0 cmp %rdx,%rax - 425f9c: 74 22 je 425fc0 <__memcmp_sse2+0x100> - 425f9e: 49 89 c3 mov %rax,%r11 - 425fa1: 49 29 d3 sub %rdx,%r11 - 425fa4: 49 0f bc cb bsf %r11,%rcx - 425fa8: 48 c1 f9 03 sar $0x3,%rcx - 425fac: 48 c1 e1 03 shl $0x3,%rcx - 425fb0: 48 d3 f8 sar %cl,%rax - 425fb3: 0f b6 c0 movzbl %al,%eax - 425fb6: 48 d3 fa sar %cl,%rdx - 425fb9: 0f b6 d2 movzbl %dl,%edx - 425fbc: 29 d0 sub %edx,%eax - 425fbe: c3 retq - 425fbf: 90 nop - 425fc0: 31 c0 xor %eax,%eax - 425fc2: c3 retq - 425fc3: 49 89 d3 mov %rdx,%r11 - 425fc6: 49 01 fb add %rdi,%r11 - 425fc9: 49 89 f8 mov %rdi,%r8 - 425fcc: 49 83 e0 0f and $0xf,%r8 - 425fd0: 74 25 je 425ff7 <__memcmp_sse2+0x137> - 425fd2: f3 0f 6f 0f movdqu (%rdi),%xmm1 - 425fd6: f3 0f 6f 04 37 movdqu (%rdi,%rsi,1),%xmm0 - 425fdb: 66 0f 74 c8 pcmpeqb %xmm0,%xmm1 - 425fdf: 66 0f d7 d1 pmovmskb %xmm1,%edx - 425fe3: 81 ea ff ff 00 00 sub $0xffff,%edx - 425fe9: 0f 85 61 01 00 00 jne 426150 <__memcmp_sse2+0x290> - 425fef: 49 f7 d8 neg %r8 - 425ff2: 4a 8d 7c 07 10 lea 0x10(%rdi,%r8,1),%rdi - 425ff7: 48 f7 c6 0f 00 00 00 test $0xf,%rsi - 425ffe: 0f 84 5f 01 00 00 je 426163 <__memcmp_sse2+0x2a3> - 426004: 48 f7 c7 10 00 00 00 test $0x10,%rdi - 42600b: 74 1d je 42602a <__memcmp_sse2+0x16a> - 42600d: f3 0f 6f 04 37 movdqu (%rdi,%rsi,1),%xmm0 - 426012: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 426016: 66 0f d7 d0 pmovmskb %xmm0,%edx - 42601a: 81 ea ff ff 00 00 sub $0xffff,%edx - 426020: 0f 85 2a 01 00 00 jne 426150 <__memcmp_sse2+0x290> - 426026: 48 83 c7 10 add $0x10,%rdi - 42602a: 4d 89 da mov %r11,%r10 - 42602d: 49 83 e2 e0 and $0xffffffffffffffe0,%r10 - 426031: 4c 39 d7 cmp %r10,%rdi - 426034: 0f 8d 03 01 00 00 jge 42613d <__memcmp_sse2+0x27d> - 42603a: 48 f7 c7 20 00 00 00 test $0x20,%rdi - 426041: 74 3a je 42607d <__memcmp_sse2+0x1bd> - 426043: f3 0f 6f 04 37 movdqu (%rdi,%rsi,1),%xmm0 - 426048: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 42604c: 66 0f d7 d0 pmovmskb %xmm0,%edx - 426050: 81 ea ff ff 00 00 sub $0xffff,%edx - 426056: 0f 85 f4 00 00 00 jne 426150 <__memcmp_sse2+0x290> - 42605c: 48 83 c7 10 add $0x10,%rdi - 426060: f3 0f 6f 04 37 movdqu (%rdi,%rsi,1),%xmm0 - 426065: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 426069: 66 0f d7 d0 pmovmskb %xmm0,%edx - 42606d: 81 ea ff ff 00 00 sub $0xffff,%edx - 426073: 0f 85 d7 00 00 00 jne 426150 <__memcmp_sse2+0x290> - 426079: 48 83 c7 10 add $0x10,%rdi - 42607d: 4d 89 da mov %r11,%r10 - 426080: 49 83 e2 c0 and $0xffffffffffffffc0,%r10 - 426084: 4c 39 d7 cmp %r10,%rdi - 426087: 7d 71 jge 4260fa <__memcmp_sse2+0x23a> - 426089: f3 0f 6f 04 37 movdqu (%rdi,%rsi,1),%xmm0 - 42608e: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 426092: 66 0f d7 d0 pmovmskb %xmm0,%edx - 426096: 81 ea ff ff 00 00 sub $0xffff,%edx - 42609c: 0f 85 ae 00 00 00 jne 426150 <__memcmp_sse2+0x290> - 4260a2: 48 83 c7 10 add $0x10,%rdi - 4260a6: f3 0f 6f 04 37 movdqu (%rdi,%rsi,1),%xmm0 - 4260ab: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 4260af: 66 0f d7 d0 pmovmskb %xmm0,%edx - 4260b3: 81 ea ff ff 00 00 sub $0xffff,%edx - 4260b9: 0f 85 91 00 00 00 jne 426150 <__memcmp_sse2+0x290> - 4260bf: 48 83 c7 10 add $0x10,%rdi - 4260c3: f3 0f 6f 04 37 movdqu (%rdi,%rsi,1),%xmm0 - 4260c8: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 4260cc: 66 0f d7 d0 pmovmskb %xmm0,%edx - 4260d0: 81 ea ff ff 00 00 sub $0xffff,%edx - 4260d6: 75 78 jne 426150 <__memcmp_sse2+0x290> - 4260d8: 48 83 c7 10 add $0x10,%rdi - 4260dc: f3 0f 6f 04 37 movdqu (%rdi,%rsi,1),%xmm0 - 4260e1: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 4260e5: 66 0f d7 d0 pmovmskb %xmm0,%edx - 4260e9: 81 ea ff ff 00 00 sub $0xffff,%edx - 4260ef: 75 5f jne 426150 <__memcmp_sse2+0x290> - 4260f1: 48 83 c7 10 add $0x10,%rdi - 4260f5: 49 39 fa cmp %rdi,%r10 - 4260f8: 75 8f jne 426089 <__memcmp_sse2+0x1c9> - 4260fa: 4d 89 da mov %r11,%r10 - 4260fd: 49 83 e2 e0 and $0xffffffffffffffe0,%r10 - 426101: 4c 39 d7 cmp %r10,%rdi - 426104: 7d 37 jge 42613d <__memcmp_sse2+0x27d> - 426106: f3 0f 6f 04 37 movdqu (%rdi,%rsi,1),%xmm0 - 42610b: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 42610f: 66 0f d7 d0 pmovmskb %xmm0,%edx - 426113: 81 ea ff ff 00 00 sub $0xffff,%edx - 426119: 75 35 jne 426150 <__memcmp_sse2+0x290> - 42611b: 48 83 c7 10 add $0x10,%rdi - 42611f: f3 0f 6f 04 37 movdqu (%rdi,%rsi,1),%xmm0 - 426124: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 426128: 66 0f d7 d0 pmovmskb %xmm0,%edx - 42612c: 81 ea ff ff 00 00 sub $0xffff,%edx - 426132: 75 1c jne 426150 <__memcmp_sse2+0x290> - 426134: 48 83 c7 10 add $0x10,%rdi - 426138: 49 39 fa cmp %rdi,%r10 - 42613b: 75 c9 jne 426106 <__memcmp_sse2+0x246> - 42613d: 49 29 fb sub %rdi,%r11 - 426140: 0f 84 7a fe ff ff je 425fc0 <__memcmp_sse2+0x100> - 426146: 4d 89 da mov %r11,%r10 - 426149: e9 95 fd ff ff jmpq 425ee3 <__memcmp_sse2+0x23> - 42614e: 66 90 xchg %ax,%ax - 426150: 0f bc ca bsf %edx,%ecx - 426153: 0f b6 04 0f movzbl (%rdi,%rcx,1),%eax - 426157: 48 01 fe add %rdi,%rsi - 42615a: 0f b6 14 0e movzbl (%rsi,%rcx,1),%edx - 42615e: e9 33 fe ff ff jmpq 425f96 <__memcmp_sse2+0xd6> - 426163: 4d 89 da mov %r11,%r10 - 426166: 49 83 e2 e0 and $0xffffffffffffffe0,%r10 - 42616a: 4c 39 d7 cmp %r10,%rdi - 42616d: 7d ce jge 42613d <__memcmp_sse2+0x27d> - 42616f: 48 f7 c7 10 00 00 00 test $0x10,%rdi - 426176: 74 1e je 426196 <__memcmp_sse2+0x2d6> - 426178: 66 0f 6f 04 37 movdqa (%rdi,%rsi,1),%xmm0 - 42617d: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 426181: 66 0f d7 d0 pmovmskb %xmm0,%edx - 426185: 81 ea ff ff 00 00 sub $0xffff,%edx - 42618b: 75 c3 jne 426150 <__memcmp_sse2+0x290> - 42618d: 48 83 c7 10 add $0x10,%rdi - 426191: 49 39 fa cmp %rdi,%r10 - 426194: 74 a7 je 42613d <__memcmp_sse2+0x27d> - 426196: 4d 89 da mov %r11,%r10 - 426199: 49 83 e2 c0 and $0xffffffffffffffc0,%r10 - 42619d: 48 f7 c7 20 00 00 00 test $0x20,%rdi - 4261a4: 74 36 je 4261dc <__memcmp_sse2+0x31c> - 4261a6: 66 0f 6f 04 37 movdqa (%rdi,%rsi,1),%xmm0 - 4261ab: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 4261af: 66 0f d7 d0 pmovmskb %xmm0,%edx - 4261b3: 81 ea ff ff 00 00 sub $0xffff,%edx - 4261b9: 75 95 jne 426150 <__memcmp_sse2+0x290> - 4261bb: 48 83 c7 10 add $0x10,%rdi - 4261bf: 66 0f 6f 04 37 movdqa (%rdi,%rsi,1),%xmm0 - 4261c4: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 4261c8: 66 0f d7 d0 pmovmskb %xmm0,%edx - 4261cc: 81 ea ff ff 00 00 sub $0xffff,%edx - 4261d2: 0f 85 78 ff ff ff jne 426150 <__memcmp_sse2+0x290> - 4261d8: 48 83 c7 10 add $0x10,%rdi - 4261dc: 49 39 fa cmp %rdi,%r10 - 4261df: 0f 84 15 ff ff ff je 4260fa <__memcmp_sse2+0x23a> - 4261e5: 66 0f 6f 04 37 movdqa (%rdi,%rsi,1),%xmm0 - 4261ea: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 4261ee: 66 0f d7 d0 pmovmskb %xmm0,%edx - 4261f2: 81 ea ff ff 00 00 sub $0xffff,%edx - 4261f8: 0f 85 52 ff ff ff jne 426150 <__memcmp_sse2+0x290> - 4261fe: 48 83 c7 10 add $0x10,%rdi - 426202: 66 0f 6f 04 37 movdqa (%rdi,%rsi,1),%xmm0 - 426207: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 42620b: 66 0f d7 d0 pmovmskb %xmm0,%edx - 42620f: 81 ea ff ff 00 00 sub $0xffff,%edx - 426215: 0f 85 35 ff ff ff jne 426150 <__memcmp_sse2+0x290> - 42621b: 48 83 c7 10 add $0x10,%rdi - 42621f: 66 0f 6f 04 37 movdqa (%rdi,%rsi,1),%xmm0 - 426224: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 426228: 66 0f d7 d0 pmovmskb %xmm0,%edx - 42622c: 81 ea ff ff 00 00 sub $0xffff,%edx - 426232: 0f 85 18 ff ff ff jne 426150 <__memcmp_sse2+0x290> - 426238: 48 83 c7 10 add $0x10,%rdi - 42623c: 66 0f 6f 04 37 movdqa (%rdi,%rsi,1),%xmm0 - 426241: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 426245: 66 0f d7 d0 pmovmskb %xmm0,%edx - 426249: 81 ea ff ff 00 00 sub $0xffff,%edx - 42624f: 0f 85 fb fe ff ff jne 426150 <__memcmp_sse2+0x290> - 426255: 48 83 c7 10 add $0x10,%rdi - 426259: 49 39 fa cmp %rdi,%r10 - 42625c: 75 87 jne 4261e5 <__memcmp_sse2+0x325> - 42625e: 4d 89 da mov %r11,%r10 - 426261: 49 83 e2 e0 and $0xffffffffffffffe0,%r10 - 426265: 4c 39 d7 cmp %r10,%rdi - 426268: 0f 8d cf fe ff ff jge 42613d <__memcmp_sse2+0x27d> - 42626e: 66 0f 6f 04 37 movdqa (%rdi,%rsi,1),%xmm0 - 426273: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 426277: 66 0f d7 d0 pmovmskb %xmm0,%edx - 42627b: 81 ea ff ff 00 00 sub $0xffff,%edx - 426281: 0f 85 c9 fe ff ff jne 426150 <__memcmp_sse2+0x290> - 426287: 48 83 c7 10 add $0x10,%rdi - 42628b: 66 0f 6f 04 37 movdqa (%rdi,%rsi,1),%xmm0 - 426290: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 426294: 66 0f d7 d0 pmovmskb %xmm0,%edx - 426298: 81 ea ff ff 00 00 sub $0xffff,%edx - 42629e: 0f 85 ac fe ff ff jne 426150 <__memcmp_sse2+0x290> - 4262a4: 48 83 c7 10 add $0x10,%rdi - 4262a8: 4c 39 d7 cmp %r10,%rdi - 4262ab: 75 c1 jne 42626e <__memcmp_sse2+0x3ae> - 4262ad: 49 29 fb sub %rdi,%r11 - 4262b0: 0f 84 0a fd ff ff je 425fc0 <__memcmp_sse2+0x100> - 4262b6: 4d 89 da mov %r11,%r10 - 4262b9: e9 25 fc ff ff jmpq 425ee3 <__memcmp_sse2+0x23> - 4262be: 66 90 xchg %ax,%ax - -00000000004262c0 <__memmove_sse2>: - 4262c0: 41 55 push %r13 - 4262c2: 48 89 f8 mov %rdi,%rax - 4262c5: 41 54 push %r12 - 4262c7: 55 push %rbp - 4262c8: 53 push %rbx - 4262c9: 48 29 f0 sub %rsi,%rax - 4262cc: 49 89 fc mov %rdi,%r12 - 4262cf: 48 83 ec 08 sub $0x8,%rsp - 4262d3: 48 39 d0 cmp %rdx,%rax - 4262d6: 0f 82 99 00 00 00 jb 426375 <__memmove_sse2+0xb5> - 4262dc: 48 83 fa 0f cmp $0xf,%rdx - 4262e0: 48 89 fb mov %rdi,%rbx - 4262e3: 49 89 f5 mov %rsi,%r13 - 4262e6: 76 5e jbe 426346 <__memmove_sse2+0x86> - 4262e8: 48 89 f9 mov %rdi,%rcx - 4262eb: 48 f7 d9 neg %rcx - 4262ee: 83 e1 07 and $0x7,%ecx - 4262f1: 48 29 ca sub %rcx,%rdx - 4262f4: 48 85 c9 test %rcx,%rcx - 4262f7: 48 89 d5 mov %rdx,%rbp - 4262fa: 74 1b je 426317 <__memmove_sse2+0x57> - 4262fc: 31 c0 xor %eax,%eax - 4262fe: 0f b6 14 06 movzbl (%rsi,%rax,1),%edx - 426302: 41 88 14 04 mov %dl,(%r12,%rax,1) - 426306: 48 83 c0 01 add $0x1,%rax - 42630a: 48 39 c1 cmp %rax,%rcx - 42630d: 75 ef jne 4262fe <__memmove_sse2+0x3e> - 42630f: 4c 8d 2c 0e lea (%rsi,%rcx,1),%r13 - 426313: 49 8d 1c 0c lea (%r12,%rcx,1),%rbx - 426317: 48 89 ea mov %rbp,%rdx - 42631a: 4c 89 ee mov %r13,%rsi - 42631d: 48 89 df mov %rbx,%rdi - 426320: 48 c1 ea 03 shr $0x3,%rdx - 426324: 41 f6 c5 07 test $0x7,%r13b - 426328: 0f 84 dc 00 00 00 je 42640a <__memmove_sse2+0x14a> - 42632e: e8 8d 62 00 00 callq 42c5c0 <_wordcopy_fwd_dest_aligned> - 426333: 48 89 e8 mov %rbp,%rax - 426336: 48 89 ea mov %rbp,%rdx - 426339: 48 83 e0 f8 and $0xfffffffffffffff8,%rax - 42633d: 83 e2 07 and $0x7,%edx - 426340: 49 01 c5 add %rax,%r13 - 426343: 48 01 c3 add %rax,%rbx - 426346: 49 29 dd sub %rbx,%r13 - 426349: 48 85 d2 test %rdx,%rdx - 42634c: 48 8d 0c 13 lea (%rbx,%rdx,1),%rcx - 426350: 48 89 df mov %rbx,%rdi - 426353: 74 12 je 426367 <__memmove_sse2+0xa7> - 426355: 41 0f b6 44 3d 00 movzbl 0x0(%r13,%rdi,1),%eax - 42635b: 48 83 c7 01 add $0x1,%rdi - 42635f: 88 47 ff mov %al,-0x1(%rdi) - 426362: 48 39 cf cmp %rcx,%rdi - 426365: 75 ee jne 426355 <__memmove_sse2+0x95> - 426367: 48 83 c4 08 add $0x8,%rsp - 42636b: 4c 89 e0 mov %r12,%rax - 42636e: 5b pop %rbx - 42636f: 5d pop %rbp - 426370: 41 5c pop %r12 - 426372: 41 5d pop %r13 - 426374: c3 retq - 426375: 48 01 d6 add %rdx,%rsi - 426378: 48 83 fa 0f cmp $0xf,%rdx - 42637c: 48 8d 2c 17 lea (%rdi,%rdx,1),%rbp - 426380: 76 5f jbe 4263e1 <__memmove_sse2+0x121> - 426382: 48 89 e9 mov %rbp,%rcx - 426385: 48 89 d3 mov %rdx,%rbx - 426388: 49 89 f5 mov %rsi,%r13 - 42638b: 83 e1 07 and $0x7,%ecx - 42638e: 48 29 cb sub %rcx,%rbx - 426391: 48 85 c9 test %rcx,%rcx - 426394: 74 1b je 4263b1 <__memmove_sse2+0xf1> - 426396: 48 89 ea mov %rbp,%rdx - 426399: 49 29 cd sub %rcx,%r13 - 42639c: 48 29 f2 sub %rsi,%rdx - 42639f: 48 83 ee 01 sub $0x1,%rsi - 4263a3: 0f b6 06 movzbl (%rsi),%eax - 4263a6: 4c 39 ee cmp %r13,%rsi - 4263a9: 88 04 32 mov %al,(%rdx,%rsi,1) - 4263ac: 75 f1 jne 42639f <__memmove_sse2+0xdf> - 4263ae: 48 29 cd sub %rcx,%rbp - 4263b1: 48 89 da mov %rbx,%rdx - 4263b4: 4c 89 ee mov %r13,%rsi - 4263b7: 48 89 ef mov %rbp,%rdi - 4263ba: 48 c1 ea 03 shr $0x3,%rdx - 4263be: 41 f6 c5 07 test $0x7,%r13b - 4263c2: 74 50 je 426414 <__memmove_sse2+0x154> - 4263c4: e8 a7 64 00 00 callq 42c870 <_wordcopy_bwd_dest_aligned> - 4263c9: 48 89 d8 mov %rbx,%rax - 4263cc: 4c 89 ee mov %r13,%rsi - 4263cf: 48 83 e0 f8 and $0xfffffffffffffff8,%rax - 4263d3: 48 29 c6 sub %rax,%rsi - 4263d6: 48 29 c5 sub %rax,%rbp - 4263d9: 83 e3 07 and $0x7,%ebx - 4263dc: 48 89 da mov %rbx,%rdx - 4263df: 74 86 je 426367 <__memmove_sse2+0xa7> - 4263e1: 48 89 f0 mov %rsi,%rax - 4263e4: 48 89 ef mov %rbp,%rdi - 4263e7: 48 29 d0 sub %rdx,%rax - 4263ea: 48 29 f7 sub %rsi,%rdi - 4263ed: 48 83 ee 01 sub $0x1,%rsi - 4263f1: 0f b6 16 movzbl (%rsi),%edx - 4263f4: 48 39 c6 cmp %rax,%rsi - 4263f7: 88 14 37 mov %dl,(%rdi,%rsi,1) - 4263fa: 75 f1 jne 4263ed <__memmove_sse2+0x12d> - 4263fc: 48 83 c4 08 add $0x8,%rsp - 426400: 4c 89 e0 mov %r12,%rax - 426403: 5b pop %rbx - 426404: 5d pop %rbp - 426405: 41 5c pop %r12 - 426407: 41 5d pop %r13 - 426409: c3 retq - 42640a: e8 81 60 00 00 callq 42c490 <_wordcopy_fwd_aligned> - 42640f: e9 1f ff ff ff jmpq 426333 <__memmove_sse2+0x73> - 426414: e8 d7 62 00 00 callq 42c6f0 <_wordcopy_bwd_aligned> - 426419: eb ae jmp 4263c9 <__memmove_sse2+0x109> - -000000000042641b <__libc_memmove>: - 42641b: 8b 15 9f 62 2a 00 mov 0x2a629f(%rip),%edx # 6cc6c0 <_dl_x86_cpu_features+0x40> - 426421: 89 d0 mov %edx,%eax - 426423: 25 00 10 02 00 and $0x21000,%eax - 426428: 3d 00 10 02 00 cmp $0x21000,%eax - 42642d: 74 2a je 426459 <__libc_memmove+0x3e> - 42642f: f6 c6 08 test $0x8,%dh - 426432: b8 d0 24 43 00 mov $0x4324d0,%eax - 426437: 75 25 jne 42645e <__libc_memmove+0x43> - 426439: f6 05 51 62 2a 00 02 testb $0x2,0x2a6251(%rip) # 6cc691 <_dl_x86_cpu_features+0x11> - 426440: b8 c0 62 42 00 mov $0x4262c0,%eax - 426445: 74 17 je 42645e <__libc_memmove+0x43> - 426447: 83 e2 02 and $0x2,%edx - 42644a: b8 c0 29 43 00 mov $0x4329c0,%eax - 42644f: ba 50 f9 42 00 mov $0x42f950,%edx - 426454: 48 0f 44 c2 cmove %rdx,%rax - 426458: c3 retq - 426459: b8 e0 54 43 00 mov $0x4354e0,%eax - 42645e: f3 c3 repz retq - -0000000000426460 : - 426460: 48 8d 05 69 00 00 00 lea 0x69(%rip),%rax # 4264d0 <__memset_sse2> - 426467: f7 05 4f 62 2a 00 00 testl $0x400,0x2a624f(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> - 42646e: 04 00 00 - 426471: 74 26 je 426499 - 426473: 48 8d 05 c6 74 01 00 lea 0x174c6(%rip),%rax # 43d940 <__memset_avx2> - 42647a: f7 05 3c 62 2a 00 00 testl $0x1000,0x2a623c(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> - 426481: 10 00 00 - 426484: 74 13 je 426499 - 426486: f7 05 30 62 2a 00 00 testl $0x20000,0x2a6230(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> - 42648d: 00 02 00 - 426490: 74 07 je 426499 - 426492: 48 8d 05 47 76 01 00 lea 0x17647(%rip),%rax # 43dae0 <__memset_avx512_no_vzeroupper> - 426499: c3 retq - 42649a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - -00000000004264a0 <__bzero>: - 4264a0: 48 89 f8 mov %rdi,%rax - 4264a3: 48 89 f2 mov %rsi,%rdx - 4264a6: 66 0f ef c0 pxor %xmm0,%xmm0 - 4264aa: eb 38 jmp 4264e4 <__memset_sse2+0x14> - 4264ac: 0f 1f 40 00 nopl 0x0(%rax) - -00000000004264b0 <__memset_tail>: - 4264b0: 48 89 c8 mov %rcx,%rax - 4264b3: 66 0f 6e c6 movd %esi,%xmm0 - 4264b7: 66 0f 60 c0 punpcklbw %xmm0,%xmm0 - 4264bb: 66 0f 61 c0 punpcklwd %xmm0,%xmm0 - 4264bf: 66 0f 70 c0 00 pshufd $0x0,%xmm0,%xmm0 - 4264c4: eb 1e jmp 4264e4 <__memset_sse2+0x14> - 4264c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4264cd: 00 00 00 - -00000000004264d0 <__memset_sse2>: - 4264d0: 66 0f 6e c6 movd %esi,%xmm0 - 4264d4: 48 89 f8 mov %rdi,%rax - 4264d7: 66 0f 60 c0 punpcklbw %xmm0,%xmm0 - 4264db: 66 0f 61 c0 punpcklwd %xmm0,%xmm0 - 4264df: 66 0f 70 c0 00 pshufd $0x0,%xmm0,%xmm0 - 4264e4: 48 83 fa 40 cmp $0x40,%rdx - 4264e8: 77 36 ja 426520 <__memset_sse2+0x50> - 4264ea: 48 83 fa 10 cmp $0x10,%rdx - 4264ee: 0f 86 8a 00 00 00 jbe 42657e <__memset_sse2+0xae> - 4264f4: 48 83 fa 20 cmp $0x20,%rdx - 4264f8: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 4264fc: f3 0f 7f 44 17 f0 movdqu %xmm0,-0x10(%rdi,%rdx,1) - 426502: 77 0c ja 426510 <__memset_sse2+0x40> - 426504: f3 c3 repz retq - 426506: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42650d: 00 00 00 - 426510: f3 0f 7f 47 10 movdqu %xmm0,0x10(%rdi) - 426515: f3 0f 7f 44 17 e0 movdqu %xmm0,-0x20(%rdi,%rdx,1) - 42651b: c3 retq - 42651c: 0f 1f 40 00 nopl 0x0(%rax) - 426520: 48 8d 4f 40 lea 0x40(%rdi),%rcx - 426524: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 426528: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 42652c: f3 0f 7f 44 17 f0 movdqu %xmm0,-0x10(%rdi,%rdx,1) - 426532: f3 0f 7f 47 10 movdqu %xmm0,0x10(%rdi) - 426537: f3 0f 7f 44 17 e0 movdqu %xmm0,-0x20(%rdi,%rdx,1) - 42653d: f3 0f 7f 47 20 movdqu %xmm0,0x20(%rdi) - 426542: f3 0f 7f 44 17 d0 movdqu %xmm0,-0x30(%rdi,%rdx,1) - 426548: f3 0f 7f 47 30 movdqu %xmm0,0x30(%rdi) - 42654d: f3 0f 7f 44 17 c0 movdqu %xmm0,-0x40(%rdi,%rdx,1) - 426553: 48 01 fa add %rdi,%rdx - 426556: 48 83 e2 c0 and $0xffffffffffffffc0,%rdx - 42655a: 48 39 d1 cmp %rdx,%rcx - 42655d: 74 a5 je 426504 <__memset_sse2+0x34> - 42655f: 90 nop - 426560: 66 0f 7f 01 movdqa %xmm0,(%rcx) - 426564: 66 0f 7f 41 10 movdqa %xmm0,0x10(%rcx) - 426569: 66 0f 7f 41 20 movdqa %xmm0,0x20(%rcx) - 42656e: 66 0f 7f 41 30 movdqa %xmm0,0x30(%rcx) - 426573: 48 83 c1 40 add $0x40,%rcx - 426577: 48 39 ca cmp %rcx,%rdx - 42657a: 75 e4 jne 426560 <__memset_sse2+0x90> - 42657c: f3 c3 repz retq - 42657e: 66 48 0f 7e c1 movq %xmm0,%rcx - 426583: f6 c2 18 test $0x18,%dl - 426586: 75 22 jne 4265aa <__memset_sse2+0xda> - 426588: f6 c2 04 test $0x4,%dl - 42658b: 75 16 jne 4265a3 <__memset_sse2+0xd3> - 42658d: f6 c2 01 test $0x1,%dl - 426590: 74 02 je 426594 <__memset_sse2+0xc4> - 426592: 88 0f mov %cl,(%rdi) - 426594: f6 c2 02 test $0x2,%dl - 426597: 0f 84 67 ff ff ff je 426504 <__memset_sse2+0x34> - 42659d: 66 89 4c 10 fe mov %cx,-0x2(%rax,%rdx,1) - 4265a2: c3 retq - 4265a3: 89 0f mov %ecx,(%rdi) - 4265a5: 89 4c 17 fc mov %ecx,-0x4(%rdi,%rdx,1) - 4265a9: c3 retq - 4265aa: 48 89 0f mov %rcx,(%rdi) - 4265ad: 48 89 4c 17 f8 mov %rcx,-0x8(%rdi,%rdx,1) - 4265b2: c3 retq - 4265b3: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4265ba: 00 00 00 - 4265bd: 0f 1f 00 nopl (%rax) - -00000000004265c0 <__mempcpy>: - 4265c0: 48 83 fa 20 cmp $0x20,%rdx - 4265c4: 73 7a jae 426640 <__mempcpy+0x80> - 4265c6: f6 c2 01 test $0x1,%dl - 4265c9: 74 0b je 4265d6 <__mempcpy+0x16> - 4265cb: 0f b6 0e movzbl (%rsi),%ecx - 4265ce: 88 0f mov %cl,(%rdi) - 4265d0: 48 ff c6 inc %rsi - 4265d3: 48 ff c7 inc %rdi - 4265d6: f6 c2 02 test $0x2,%dl - 4265d9: 74 0e je 4265e9 <__mempcpy+0x29> - 4265db: 0f b7 0e movzwl (%rsi),%ecx - 4265de: 66 89 0f mov %cx,(%rdi) - 4265e1: 48 83 c6 02 add $0x2,%rsi - 4265e5: 48 83 c7 02 add $0x2,%rdi - 4265e9: f6 c2 04 test $0x4,%dl - 4265ec: 74 0c je 4265fa <__mempcpy+0x3a> - 4265ee: 8b 0e mov (%rsi),%ecx - 4265f0: 89 0f mov %ecx,(%rdi) - 4265f2: 48 83 c6 04 add $0x4,%rsi - 4265f6: 48 83 c7 04 add $0x4,%rdi - 4265fa: f6 c2 08 test $0x8,%dl - 4265fd: 74 11 je 426610 <__mempcpy+0x50> - 4265ff: 48 8b 0e mov (%rsi),%rcx - 426602: 48 89 0f mov %rcx,(%rdi) - 426605: 48 83 c6 08 add $0x8,%rsi - 426609: 48 83 c7 08 add $0x8,%rdi - 42660d: 0f 1f 00 nopl (%rax) - 426610: 81 e2 f0 00 00 00 and $0xf0,%edx - 426616: 74 23 je 42663b <__mempcpy+0x7b> - 426618: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 42661f: 00 - 426620: 48 8b 0e mov (%rsi),%rcx - 426623: 4c 8b 46 08 mov 0x8(%rsi),%r8 - 426627: 48 89 0f mov %rcx,(%rdi) - 42662a: 4c 89 47 08 mov %r8,0x8(%rdi) - 42662e: 83 ea 10 sub $0x10,%edx - 426631: 48 8d 76 10 lea 0x10(%rsi),%rsi - 426635: 48 8d 7f 10 lea 0x10(%rdi),%rdi - 426639: 75 e5 jne 426620 <__mempcpy+0x60> - 42663b: 48 89 f8 mov %rdi,%rax - 42663e: c3 retq - 42663f: 90 nop - 426640: 89 f1 mov %esi,%ecx - 426642: 83 e1 07 and $0x7,%ecx - 426645: 74 29 je 426670 <__mempcpy+0xb0> - 426647: 48 8d 54 11 f8 lea -0x8(%rcx,%rdx,1),%rdx - 42664c: 83 e9 08 sub $0x8,%ecx - 42664f: 90 nop - 426650: 0f b6 06 movzbl (%rsi),%eax - 426653: 88 07 mov %al,(%rdi) - 426655: ff c1 inc %ecx - 426657: 48 8d 76 01 lea 0x1(%rsi),%rsi - 42665b: 48 8d 7f 01 lea 0x1(%rdi),%rdi - 42665f: 75 ef jne 426650 <__mempcpy+0x90> - 426661: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 426666: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42666d: 00 00 00 - 426670: 48 81 fa 00 04 00 00 cmp $0x400,%rdx - 426677: 77 77 ja 4266f0 <__mempcpy+0x130> - 426679: 89 d1 mov %edx,%ecx - 42667b: c1 e9 05 shr $0x5,%ecx - 42667e: 74 60 je 4266e0 <__mempcpy+0x120> - 426680: ff c9 dec %ecx - 426682: 48 8b 06 mov (%rsi),%rax - 426685: 4c 8b 46 08 mov 0x8(%rsi),%r8 - 426689: 4c 8b 4e 10 mov 0x10(%rsi),%r9 - 42668d: 4c 8b 56 18 mov 0x18(%rsi),%r10 - 426691: 48 89 07 mov %rax,(%rdi) - 426694: 4c 89 47 08 mov %r8,0x8(%rdi) - 426698: 4c 89 4f 10 mov %r9,0x10(%rdi) - 42669c: 4c 89 57 18 mov %r10,0x18(%rdi) - 4266a0: 48 8d 76 20 lea 0x20(%rsi),%rsi - 4266a4: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 4266a8: 74 36 je 4266e0 <__mempcpy+0x120> - 4266aa: ff c9 dec %ecx - 4266ac: 48 8b 06 mov (%rsi),%rax - 4266af: 4c 8b 46 08 mov 0x8(%rsi),%r8 - 4266b3: 4c 8b 4e 10 mov 0x10(%rsi),%r9 - 4266b7: 4c 8b 56 18 mov 0x18(%rsi),%r10 - 4266bb: 48 89 07 mov %rax,(%rdi) - 4266be: 4c 89 47 08 mov %r8,0x8(%rdi) - 4266c2: 4c 89 4f 10 mov %r9,0x10(%rdi) - 4266c6: 4c 89 57 18 mov %r10,0x18(%rdi) - 4266ca: 48 8d 76 20 lea 0x20(%rsi),%rsi - 4266ce: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 4266d2: 75 ac jne 426680 <__mempcpy+0xc0> - 4266d4: 66 90 xchg %ax,%ax - 4266d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4266dd: 00 00 00 - 4266e0: 83 e2 1f and $0x1f,%edx - 4266e3: 0f 85 dd fe ff ff jne 4265c6 <__mempcpy+0x6> - 4266e9: 48 89 f8 mov %rdi,%rax - 4266ec: c3 retq - 4266ed: 0f 1f 00 nopl (%rax) - 4266f0: 4c 8b 1d d9 49 2a 00 mov 0x2a49d9(%rip),%r11 # 6cb0d0 <__x86_data_cache_size_half> - 4266f7: 49 39 d3 cmp %rdx,%r11 - 4266fa: 4c 0f 47 da cmova %rdx,%r11 - 4266fe: 4c 89 d9 mov %r11,%rcx - 426701: 49 83 e3 f8 and $0xfffffffffffffff8,%r11 - 426705: 48 c1 e9 03 shr $0x3,%rcx - 426709: 74 05 je 426710 <__mempcpy+0x150> - 42670b: f3 48 a5 rep movsq %ds:(%rsi),%es:(%rdi) - 42670e: 66 90 xchg %ax,%ax - 426710: 4c 29 da sub %r11,%rdx - 426713: 48 f7 c2 f8 ff ff ff test $0xfffffffffffffff8,%rdx - 42671a: 75 14 jne 426730 <__mempcpy+0x170> - 42671c: 83 e2 07 and $0x7,%edx - 42671f: 0f 85 a1 fe ff ff jne 4265c6 <__mempcpy+0x6> - 426725: 48 89 f8 mov %rdi,%rax - 426728: c3 retq - 426729: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 426730: 4c 8b 05 79 49 2a 00 mov 0x2a4979(%rip),%r8 # 6cb0b0 <__x86_shared_cache_size_half> - 426737: 49 39 d0 cmp %rdx,%r8 - 42673a: 4c 0f 47 c2 cmova %rdx,%r8 - 42673e: 4c 89 c1 mov %r8,%rcx - 426741: 49 83 e0 c0 and $0xffffffffffffffc0,%r8 - 426745: 48 c1 e9 06 shr $0x6,%rcx - 426749: 0f 84 ab 01 00 00 je 4268fa <__mempcpy+0x33a> - 42674f: 4c 89 74 24 f8 mov %r14,-0x8(%rsp) - 426754: 4c 89 6c 24 f0 mov %r13,-0x10(%rsp) - 426759: 4c 89 64 24 e8 mov %r12,-0x18(%rsp) - 42675e: 48 89 5c 24 e0 mov %rbx,-0x20(%rsp) - 426763: 83 3d 4e 6a 2a 00 00 cmpl $0x0,0x2a6a4e(%rip) # 6cd1b8 <__x86_prefetchw> - 42676a: 0f 84 c0 00 00 00 je 426830 <__mempcpy+0x270> - 426770: 48 ff c9 dec %rcx - 426773: 48 8b 06 mov (%rsi),%rax - 426776: 48 8b 5e 08 mov 0x8(%rsi),%rbx - 42677a: 4c 8b 4e 10 mov 0x10(%rsi),%r9 - 42677e: 4c 8b 56 18 mov 0x18(%rsi),%r10 - 426782: 4c 8b 5e 20 mov 0x20(%rsi),%r11 - 426786: 4c 8b 66 28 mov 0x28(%rsi),%r12 - 42678a: 4c 8b 6e 30 mov 0x30(%rsi),%r13 - 42678e: 4c 8b 76 38 mov 0x38(%rsi),%r14 - 426792: 0f 18 8e 80 03 00 00 prefetcht0 0x380(%rsi) - 426799: 0f 18 8e c0 03 00 00 prefetcht0 0x3c0(%rsi) - 4267a0: 48 89 07 mov %rax,(%rdi) - 4267a3: 48 89 5f 08 mov %rbx,0x8(%rdi) - 4267a7: 4c 89 4f 10 mov %r9,0x10(%rdi) - 4267ab: 4c 89 57 18 mov %r10,0x18(%rdi) - 4267af: 4c 89 5f 20 mov %r11,0x20(%rdi) - 4267b3: 4c 89 67 28 mov %r12,0x28(%rdi) - 4267b7: 4c 89 6f 30 mov %r13,0x30(%rdi) - 4267bb: 4c 89 77 38 mov %r14,0x38(%rdi) - 4267bf: 48 8d 76 40 lea 0x40(%rsi),%rsi - 4267c3: 48 8d 7f 40 lea 0x40(%rdi),%rdi - 4267c7: 0f 84 19 01 00 00 je 4268e6 <__mempcpy+0x326> - 4267cd: 48 ff c9 dec %rcx - 4267d0: 48 8b 06 mov (%rsi),%rax - 4267d3: 48 8b 5e 08 mov 0x8(%rsi),%rbx - 4267d7: 4c 8b 4e 10 mov 0x10(%rsi),%r9 - 4267db: 4c 8b 56 18 mov 0x18(%rsi),%r10 - 4267df: 4c 8b 5e 20 mov 0x20(%rsi),%r11 - 4267e3: 4c 8b 66 28 mov 0x28(%rsi),%r12 - 4267e7: 4c 8b 6e 30 mov 0x30(%rsi),%r13 - 4267eb: 4c 8b 76 38 mov 0x38(%rsi),%r14 - 4267ef: 48 89 07 mov %rax,(%rdi) - 4267f2: 48 89 5f 08 mov %rbx,0x8(%rdi) - 4267f6: 4c 89 4f 10 mov %r9,0x10(%rdi) - 4267fa: 4c 89 57 18 mov %r10,0x18(%rdi) - 4267fe: 4c 89 5f 20 mov %r11,0x20(%rdi) - 426802: 4c 89 67 28 mov %r12,0x28(%rdi) - 426806: 4c 89 6f 30 mov %r13,0x30(%rdi) - 42680a: 4c 89 77 38 mov %r14,0x38(%rdi) - 42680e: 0f 0d 8f 40 03 00 00 prefetchw 0x340(%rdi) - 426815: 0f 0d 8f 80 03 00 00 prefetchw 0x380(%rdi) - 42681c: 48 8d 76 40 lea 0x40(%rsi),%rsi - 426820: 48 8d 7f 40 lea 0x40(%rdi),%rdi - 426824: 0f 85 46 ff ff ff jne 426770 <__mempcpy+0x1b0> - 42682a: e9 b7 00 00 00 jmpq 4268e6 <__mempcpy+0x326> - 42682f: 90 nop - 426830: 48 ff c9 dec %rcx - 426833: 48 8b 06 mov (%rsi),%rax - 426836: 48 8b 5e 08 mov 0x8(%rsi),%rbx - 42683a: 4c 8b 4e 10 mov 0x10(%rsi),%r9 - 42683e: 4c 8b 56 18 mov 0x18(%rsi),%r10 - 426842: 4c 8b 5e 20 mov 0x20(%rsi),%r11 - 426846: 4c 8b 66 28 mov 0x28(%rsi),%r12 - 42684a: 4c 8b 6e 30 mov 0x30(%rsi),%r13 - 42684e: 4c 8b 76 38 mov 0x38(%rsi),%r14 - 426852: 0f 18 8e 80 03 00 00 prefetcht0 0x380(%rsi) - 426859: 0f 18 8e c0 03 00 00 prefetcht0 0x3c0(%rsi) - 426860: 48 89 07 mov %rax,(%rdi) - 426863: 48 89 5f 08 mov %rbx,0x8(%rdi) - 426867: 4c 89 4f 10 mov %r9,0x10(%rdi) - 42686b: 4c 89 57 18 mov %r10,0x18(%rdi) - 42686f: 4c 89 5f 20 mov %r11,0x20(%rdi) - 426873: 4c 89 67 28 mov %r12,0x28(%rdi) - 426877: 4c 89 6f 30 mov %r13,0x30(%rdi) - 42687b: 4c 89 77 38 mov %r14,0x38(%rdi) - 42687f: 48 8d 76 40 lea 0x40(%rsi),%rsi - 426883: 48 8d 7f 40 lea 0x40(%rdi),%rdi - 426887: 74 5d je 4268e6 <__mempcpy+0x326> - 426889: 48 ff c9 dec %rcx - 42688c: 48 8b 06 mov (%rsi),%rax - 42688f: 48 8b 5e 08 mov 0x8(%rsi),%rbx - 426893: 4c 8b 4e 10 mov 0x10(%rsi),%r9 - 426897: 4c 8b 56 18 mov 0x18(%rsi),%r10 - 42689b: 4c 8b 5e 20 mov 0x20(%rsi),%r11 - 42689f: 4c 8b 66 28 mov 0x28(%rsi),%r12 - 4268a3: 4c 8b 6e 30 mov 0x30(%rsi),%r13 - 4268a7: 4c 8b 76 38 mov 0x38(%rsi),%r14 - 4268ab: 0f 18 8f 40 03 00 00 prefetcht0 0x340(%rdi) - 4268b2: 0f 18 8f 80 03 00 00 prefetcht0 0x380(%rdi) - 4268b9: 48 89 07 mov %rax,(%rdi) - 4268bc: 48 89 5f 08 mov %rbx,0x8(%rdi) - 4268c0: 4c 89 4f 10 mov %r9,0x10(%rdi) - 4268c4: 4c 89 57 18 mov %r10,0x18(%rdi) - 4268c8: 4c 89 5f 20 mov %r11,0x20(%rdi) - 4268cc: 4c 89 67 28 mov %r12,0x28(%rdi) - 4268d0: 4c 89 6f 30 mov %r13,0x30(%rdi) - 4268d4: 4c 89 77 38 mov %r14,0x38(%rdi) - 4268d8: 48 8d 76 40 lea 0x40(%rsi),%rsi - 4268dc: 48 8d 7f 40 lea 0x40(%rdi),%rdi - 4268e0: 0f 85 4a ff ff ff jne 426830 <__mempcpy+0x270> - 4268e6: 48 8b 5c 24 e0 mov -0x20(%rsp),%rbx - 4268eb: 4c 8b 64 24 e8 mov -0x18(%rsp),%r12 - 4268f0: 4c 8b 6c 24 f0 mov -0x10(%rsp),%r13 - 4268f5: 4c 8b 74 24 f8 mov -0x8(%rsp),%r14 - 4268fa: 4c 29 c2 sub %r8,%rdx - 4268fd: 48 f7 c2 c0 ff ff ff test $0xffffffffffffffc0,%rdx - 426904: 75 1a jne 426920 <__mempcpy+0x360> - 426906: 83 e2 3f and $0x3f,%edx - 426909: 0f 85 b7 fc ff ff jne 4265c6 <__mempcpy+0x6> - 42690f: 48 89 f8 mov %rdi,%rax - 426912: c3 retq - 426913: 0f 1f 00 nopl (%rax) - 426916: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42691d: 00 00 00 - 426920: 48 89 d1 mov %rdx,%rcx - 426923: 48 c1 e9 07 shr $0x7,%rcx - 426927: 0f 84 d8 00 00 00 je 426a05 <__mempcpy+0x445> - 42692d: 4c 89 74 24 f8 mov %r14,-0x8(%rsp) - 426932: 4c 89 6c 24 f0 mov %r13,-0x10(%rsp) - 426937: 4c 89 64 24 e8 mov %r12,-0x18(%rsp) - 42693c: 0f 1f 40 00 nopl 0x0(%rax) - 426940: 0f 18 86 00 03 00 00 prefetchnta 0x300(%rsi) - 426947: 0f 18 86 40 03 00 00 prefetchnta 0x340(%rsi) - 42694e: 48 ff c9 dec %rcx - 426951: 48 8b 06 mov (%rsi),%rax - 426954: 4c 8b 46 08 mov 0x8(%rsi),%r8 - 426958: 4c 8b 4e 10 mov 0x10(%rsi),%r9 - 42695c: 4c 8b 56 18 mov 0x18(%rsi),%r10 - 426960: 4c 8b 5e 20 mov 0x20(%rsi),%r11 - 426964: 4c 8b 66 28 mov 0x28(%rsi),%r12 - 426968: 4c 8b 6e 30 mov 0x30(%rsi),%r13 - 42696c: 4c 8b 76 38 mov 0x38(%rsi),%r14 - 426970: 48 0f c3 07 movnti %rax,(%rdi) - 426974: 4c 0f c3 47 08 movnti %r8,0x8(%rdi) - 426979: 4c 0f c3 4f 10 movnti %r9,0x10(%rdi) - 42697e: 4c 0f c3 57 18 movnti %r10,0x18(%rdi) - 426983: 4c 0f c3 5f 20 movnti %r11,0x20(%rdi) - 426988: 4c 0f c3 67 28 movnti %r12,0x28(%rdi) - 42698d: 4c 0f c3 6f 30 movnti %r13,0x30(%rdi) - 426992: 4c 0f c3 77 38 movnti %r14,0x38(%rdi) - 426997: 48 8b 46 40 mov 0x40(%rsi),%rax - 42699b: 4c 8b 46 48 mov 0x48(%rsi),%r8 - 42699f: 4c 8b 4e 50 mov 0x50(%rsi),%r9 - 4269a3: 4c 8b 56 58 mov 0x58(%rsi),%r10 - 4269a7: 4c 8b 5e 60 mov 0x60(%rsi),%r11 - 4269ab: 4c 8b 66 68 mov 0x68(%rsi),%r12 - 4269af: 4c 8b 6e 70 mov 0x70(%rsi),%r13 - 4269b3: 4c 8b 76 78 mov 0x78(%rsi),%r14 - 4269b7: 48 0f c3 47 40 movnti %rax,0x40(%rdi) - 4269bc: 4c 0f c3 47 48 movnti %r8,0x48(%rdi) - 4269c1: 4c 0f c3 4f 50 movnti %r9,0x50(%rdi) - 4269c6: 4c 0f c3 57 58 movnti %r10,0x58(%rdi) - 4269cb: 4c 0f c3 5f 60 movnti %r11,0x60(%rdi) - 4269d0: 4c 0f c3 67 68 movnti %r12,0x68(%rdi) - 4269d5: 4c 0f c3 6f 70 movnti %r13,0x70(%rdi) - 4269da: 4c 0f c3 77 78 movnti %r14,0x78(%rdi) - 4269df: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi - 4269e6: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi - 4269ed: 0f 85 4d ff ff ff jne 426940 <__mempcpy+0x380> - 4269f3: 0f ae f8 sfence - 4269f6: 4c 8b 64 24 e8 mov -0x18(%rsp),%r12 - 4269fb: 4c 8b 6c 24 f0 mov -0x10(%rsp),%r13 - 426a00: 4c 8b 74 24 f8 mov -0x8(%rsp),%r14 - 426a05: 83 e2 7f and $0x7f,%edx - 426a08: 0f 85 b8 fb ff ff jne 4265c6 <__mempcpy+0x6> - 426a0e: 48 89 f8 mov %rdi,%rax - 426a11: c3 retq - 426a12: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 426a19: 00 00 00 - 426a1c: 0f 1f 40 00 nopl 0x0(%rax) - -0000000000426a20 <__stpcpy>: - 426a20: 48 8d 05 39 49 01 00 lea 0x14939(%rip),%rax # 43b360 <__stpcpy_sse2_unaligned> - 426a27: f7 05 8f 5c 2a 00 10 testl $0x10,0x2a5c8f(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> - 426a2e: 00 00 00 - 426a31: 75 1a jne 426a4d <__stpcpy+0x2d> - 426a33: 48 8d 05 16 00 00 00 lea 0x16(%rip),%rax # 426a50 <__GI___stpcpy> - 426a3a: f7 05 4c 5c 2a 00 00 testl $0x200,0x2a5c4c(%rip) # 6cc690 <_dl_x86_cpu_features+0x10> - 426a41: 02 00 00 - 426a44: 74 07 je 426a4d <__stpcpy+0x2d> - 426a46: 48 8d 05 d3 2a 01 00 lea 0x12ad3(%rip),%rax # 439520 <__stpcpy_ssse3> - 426a4d: c3 retq - 426a4e: 66 90 xchg %ax,%ax - -0000000000426a50 <__GI___stpcpy>: - 426a50: 48 89 f1 mov %rsi,%rcx - 426a53: 83 e1 07 and $0x7,%ecx - 426a56: 48 89 fa mov %rdi,%rdx - 426a59: 74 1b je 426a76 <__GI___stpcpy+0x26> - 426a5b: f7 d9 neg %ecx - 426a5d: 83 c1 08 add $0x8,%ecx - 426a60: 8a 06 mov (%rsi),%al - 426a62: 84 c0 test %al,%al - 426a64: 88 02 mov %al,(%rdx) - 426a66: 0f 84 bc 00 00 00 je 426b28 <__GI___stpcpy+0xd8> - 426a6c: 48 ff c6 inc %rsi - 426a6f: 48 ff c2 inc %rdx - 426a72: ff c9 dec %ecx - 426a74: 75 ea jne 426a60 <__GI___stpcpy+0x10> - 426a76: 49 b8 ff fe fe fe fe movabs $0xfefefefefefefeff,%r8 - 426a7d: fe fe fe - 426a80: 48 8b 06 mov (%rsi),%rax - 426a83: 48 83 c6 08 add $0x8,%rsi - 426a87: 49 89 c1 mov %rax,%r9 - 426a8a: 4d 01 c1 add %r8,%r9 - 426a8d: 0f 83 7d 00 00 00 jae 426b10 <__GI___stpcpy+0xc0> - 426a93: 49 31 c1 xor %rax,%r9 - 426a96: 4d 09 c1 or %r8,%r9 - 426a99: 49 ff c1 inc %r9 - 426a9c: 75 72 jne 426b10 <__GI___stpcpy+0xc0> - 426a9e: 48 89 02 mov %rax,(%rdx) - 426aa1: 48 83 c2 08 add $0x8,%rdx - 426aa5: 48 8b 06 mov (%rsi),%rax - 426aa8: 48 83 c6 08 add $0x8,%rsi - 426aac: 49 89 c1 mov %rax,%r9 - 426aaf: 4d 01 c1 add %r8,%r9 - 426ab2: 73 5c jae 426b10 <__GI___stpcpy+0xc0> - 426ab4: 49 31 c1 xor %rax,%r9 - 426ab7: 4d 09 c1 or %r8,%r9 - 426aba: 49 ff c1 inc %r9 - 426abd: 75 51 jne 426b10 <__GI___stpcpy+0xc0> - 426abf: 48 89 02 mov %rax,(%rdx) - 426ac2: 48 83 c2 08 add $0x8,%rdx - 426ac6: 48 8b 06 mov (%rsi),%rax - 426ac9: 48 83 c6 08 add $0x8,%rsi - 426acd: 49 89 c1 mov %rax,%r9 - 426ad0: 4d 01 c1 add %r8,%r9 - 426ad3: 73 3b jae 426b10 <__GI___stpcpy+0xc0> - 426ad5: 49 31 c1 xor %rax,%r9 - 426ad8: 4d 09 c1 or %r8,%r9 - 426adb: 49 ff c1 inc %r9 - 426ade: 75 30 jne 426b10 <__GI___stpcpy+0xc0> - 426ae0: 48 89 02 mov %rax,(%rdx) - 426ae3: 48 83 c2 08 add $0x8,%rdx - 426ae7: 48 8b 06 mov (%rsi),%rax - 426aea: 48 83 c6 08 add $0x8,%rsi - 426aee: 49 89 c1 mov %rax,%r9 - 426af1: 4d 01 c1 add %r8,%r9 - 426af4: 73 1a jae 426b10 <__GI___stpcpy+0xc0> - 426af6: 49 31 c1 xor %rax,%r9 - 426af9: 4d 09 c1 or %r8,%r9 - 426afc: 49 ff c1 inc %r9 - 426aff: 75 0f jne 426b10 <__GI___stpcpy+0xc0> - 426b01: 48 89 02 mov %rax,(%rdx) - 426b04: 48 83 c2 08 add $0x8,%rdx - 426b08: e9 73 ff ff ff jmpq 426a80 <__GI___stpcpy+0x30> - 426b0d: 0f 1f 00 nopl (%rax) - 426b10: 88 02 mov %al,(%rdx) - 426b12: 84 c0 test %al,%al - 426b14: 74 12 je 426b28 <__GI___stpcpy+0xd8> - 426b16: 48 ff c2 inc %rdx - 426b19: 88 22 mov %ah,(%rdx) - 426b1b: 84 e4 test %ah,%ah - 426b1d: 74 09 je 426b28 <__GI___stpcpy+0xd8> - 426b1f: 48 ff c2 inc %rdx - 426b22: 48 c1 e8 10 shr $0x10,%rax - 426b26: eb e8 jmp 426b10 <__GI___stpcpy+0xc0> - 426b28: 48 89 d0 mov %rdx,%rax - 426b2b: c3 retq - 426b2c: 0f 1f 40 00 nopl 0x0(%rax) - -0000000000426b30 <__strcasecmp_l>: - 426b30: f7 05 86 5b 2a 00 00 testl $0x200,0x2a5b86(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> - 426b37: 02 00 00 - 426b3a: 75 13 jne 426b4f <__strcasecmp_l+0x1f> - 426b3c: 48 8d 05 cd 22 00 00 lea 0x22cd(%rip),%rax # 428e10 <__strcasecmp_l_sse42> - 426b43: f7 05 43 5b 2a 00 00 testl $0x100000,0x2a5b43(%rip) # 6cc690 <_dl_x86_cpu_features+0x10> - 426b4a: 00 10 00 - 426b4d: 75 1a jne 426b69 <__strcasecmp_l+0x39> - 426b4f: 48 8d 05 da f0 00 00 lea 0xf0da(%rip),%rax # 435c30 <__strcasecmp_l_ssse3> - 426b56: f7 05 30 5b 2a 00 00 testl $0x200,0x2a5b30(%rip) # 6cc690 <_dl_x86_cpu_features+0x10> - 426b5d: 02 00 00 - 426b60: 75 07 jne 426b69 <__strcasecmp_l+0x39> - 426b62: 48 8d 05 67 00 00 00 lea 0x67(%rip),%rax # 426bd0 <__GI___strcasecmp_l> - 426b69: c3 retq - 426b6a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - -0000000000426b70 <__strcasecmp>: - 426b70: 48 8d 05 39 3e 00 00 lea 0x3e39(%rip),%rax # 42a9b0 <__strcasecmp_avx> - 426b77: f7 05 3f 5b 2a 00 40 testl $0x40,0x2a5b3f(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> - 426b7e: 00 00 00 - 426b81: 75 39 jne 426bbc <__strcasecmp+0x4c> - 426b83: f7 05 33 5b 2a 00 00 testl $0x200,0x2a5b33(%rip) # 6cc6c0 <_dl_x86_cpu_features+0x40> - 426b8a: 02 00 00 - 426b8d: 75 13 jne 426ba2 <__strcasecmp+0x32> - 426b8f: 48 8d 05 6a 22 00 00 lea 0x226a(%rip),%rax # 428e00 <__strcasecmp_sse42> - 426b96: f7 05 f0 5a 2a 00 00 testl $0x100000,0x2a5af0(%rip) # 6cc690 <_dl_x86_cpu_features+0x10> - 426b9d: 00 10 00 - 426ba0: 75 1a jne 426bbc <__strcasecmp+0x4c> - 426ba2: 48 8d 05 77 f0 00 00 lea 0xf077(%rip),%rax # 435c20 <__strcasecmp_ssse3> - 426ba9: f7 05 dd 5a 2a 00 00 testl $0x200,0x2a5add(%rip) # 6cc690 <_dl_x86_cpu_features+0x10> - 426bb0: 02 00 00 - 426bb3: 75 07 jne 426bbc <__strcasecmp+0x4c> - 426bb5: 48 8d 05 04 00 00 00 lea 0x4(%rip),%rax # 426bc0 <__strcasecmp_sse2> - 426bbc: c3 retq - 426bbd: 0f 1f 00 nopl (%rax) - -0000000000426bc0 <__strcasecmp_sse2>: - 426bc0: 48 c7 c0 b8 ff ff ff mov $0xffffffffffffffb8,%rax - 426bc7: 64 48 8b 10 mov %fs:(%rax),%rdx - 426bcb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - -0000000000426bd0 <__GI___strcasecmp_l>: - 426bd0: 48 8b 02 mov (%rdx),%rax - 426bd3: f7 80 78 02 00 00 01 testl $0x1,0x278(%rax) - 426bda: 00 00 00 - 426bdd: 0f 85 1d 77 01 00 jne 43e300 <__strcasecmp_l_nonascii> - 426be3: 89 f1 mov %esi,%ecx - 426be5: 89 f8 mov %edi,%eax - 426be7: 48 83 e1 3f and $0x3f,%rcx - 426beb: 48 83 e0 3f and $0x3f,%rax - 426bef: 66 0f 6f 2d b9 c4 07 movdqa 0x7c4b9(%rip),%xmm5 # 4a30b0 <__func__.10972+0xf0> - 426bf6: 00 - 426bf7: 66 0f 6f 35 c1 c4 07 movdqa 0x7c4c1(%rip),%xmm6 # 4a30c0 <__func__.10972+0x100> - 426bfe: 00 - 426bff: 66 0f 6f 3d c9 c4 07 movdqa 0x7c4c9(%rip),%xmm7 # 4a30d0 - 426c06: 00 - 426c07: 83 f9 30 cmp $0x30,%ecx - 426c0a: 0f 87 90 00 00 00 ja 426ca0 <__GI___strcasecmp_l+0xd0> - 426c10: 83 f8 30 cmp $0x30,%eax - 426c13: 0f 87 87 00 00 00 ja 426ca0 <__GI___strcasecmp_l+0xd0> - 426c19: 66 0f 12 0f movlpd (%rdi),%xmm1 - 426c1d: 66 0f 12 16 movlpd (%rsi),%xmm2 - 426c21: 66 0f 16 4f 08 movhpd 0x8(%rdi),%xmm1 - 426c26: 66 0f 16 56 08 movhpd 0x8(%rsi),%xmm2 - 426c2b: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 426c30: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 426c35: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 426c3a: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 426c3f: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 426c44: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 426c49: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 426c4e: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 426c53: 66 45 0f db c1 pand %xmm9,%xmm8 - 426c58: 66 45 0f db d3 pand %xmm11,%xmm10 - 426c5d: 66 44 0f db c7 pand %xmm7,%xmm8 - 426c62: 66 44 0f db d7 pand %xmm7,%xmm10 - 426c67: 66 41 0f eb c8 por %xmm8,%xmm1 - 426c6c: 66 41 0f eb d2 por %xmm10,%xmm2 - 426c71: 66 0f ef c0 pxor %xmm0,%xmm0 - 426c75: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 426c79: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 426c7d: 66 0f f8 c8 psubb %xmm0,%xmm1 - 426c81: 66 0f d7 d1 pmovmskb %xmm1,%edx - 426c85: 81 ea ff ff 00 00 sub $0xffff,%edx - 426c8b: 0f 85 2f 21 00 00 jne 428dc0 <__GI___strcasecmp_l+0x21f0> - 426c91: 48 83 c6 10 add $0x10,%rsi - 426c95: 48 83 c7 10 add $0x10,%rdi - 426c99: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 426ca0: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi - 426ca4: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi - 426ca8: ba ff ff 00 00 mov $0xffff,%edx - 426cad: 45 31 c0 xor %r8d,%r8d - 426cb0: 83 e1 0f and $0xf,%ecx - 426cb3: 83 e0 0f and $0xf,%eax - 426cb6: 39 c1 cmp %eax,%ecx - 426cb8: 74 26 je 426ce0 <__GI___strcasecmp_l+0x110> - 426cba: 77 07 ja 426cc3 <__GI___strcasecmp_l+0xf3> - 426cbc: 41 89 d0 mov %edx,%r8d - 426cbf: 91 xchg %eax,%ecx - 426cc0: 48 87 f7 xchg %rsi,%rdi - 426cc3: 4c 8d 48 0f lea 0xf(%rax),%r9 - 426cc7: 49 29 c9 sub %rcx,%r9 - 426cca: 4c 8d 15 9f c4 07 00 lea 0x7c49f(%rip),%r10 # 4a3170 - 426cd1: 4f 63 0c 8a movslq (%r10,%r9,4),%r9 - 426cd5: 4f 8d 14 0a lea (%r10,%r9,1),%r10 - 426cd9: 41 ff e2 jmpq *%r10 - 426cdc: 0f 1f 40 00 nopl 0x0(%rax) - 426ce0: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 426ce4: 66 0f ef c0 pxor %xmm0,%xmm0 - 426ce8: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 426cec: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 426cf0: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 426cf5: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 426cfa: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 426cff: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 426d04: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 426d09: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 426d0e: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 426d13: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 426d18: 66 45 0f db c1 pand %xmm9,%xmm8 - 426d1d: 66 45 0f db d3 pand %xmm11,%xmm10 - 426d22: 66 44 0f db c7 pand %xmm7,%xmm8 - 426d27: 66 44 0f db d7 pand %xmm7,%xmm10 - 426d2c: 66 41 0f eb c8 por %xmm8,%xmm1 - 426d31: 66 41 0f eb d2 por %xmm10,%xmm2 - 426d36: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 426d3a: 66 0f f8 c8 psubb %xmm0,%xmm1 - 426d3e: 66 44 0f d7 c9 pmovmskb %xmm1,%r9d - 426d43: d3 ea shr %cl,%edx - 426d45: 41 d3 e9 shr %cl,%r9d - 426d48: 44 29 ca sub %r9d,%edx - 426d4b: 0f 85 54 20 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> - 426d51: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 426d58: 49 c7 c1 10 00 00 00 mov $0x10,%r9 - 426d5f: 66 0f ef c0 pxor %xmm0,%xmm0 - 426d63: 0f 1f 00 nopl (%rax) - 426d66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 426d6d: 00 00 00 - 426d70: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 426d75: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 426d7a: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 426d7f: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 426d84: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 426d89: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 426d8e: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 426d93: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 426d98: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 426d9d: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 426da2: 66 45 0f db c1 pand %xmm9,%xmm8 - 426da7: 66 45 0f db d3 pand %xmm11,%xmm10 - 426dac: 66 44 0f db c7 pand %xmm7,%xmm8 - 426db1: 66 44 0f db d7 pand %xmm7,%xmm10 - 426db6: 66 41 0f eb c8 por %xmm8,%xmm1 - 426dbb: 66 41 0f eb d2 por %xmm10,%xmm2 - 426dc0: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 426dc4: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 426dc8: 66 0f f8 c8 psubb %xmm0,%xmm1 - 426dcc: 66 0f d7 d1 pmovmskb %xmm1,%edx - 426dd0: 81 ea ff ff 00 00 sub $0xffff,%edx - 426dd6: 0f 85 c4 1f 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 426ddc: 48 83 c1 10 add $0x10,%rcx - 426de0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 426de5: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 426dea: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 426def: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 426df4: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 426df9: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 426dfe: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 426e03: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 426e08: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 426e0d: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 426e12: 66 45 0f db c1 pand %xmm9,%xmm8 - 426e17: 66 45 0f db d3 pand %xmm11,%xmm10 - 426e1c: 66 44 0f db c7 pand %xmm7,%xmm8 - 426e21: 66 44 0f db d7 pand %xmm7,%xmm10 - 426e26: 66 41 0f eb c8 por %xmm8,%xmm1 - 426e2b: 66 41 0f eb d2 por %xmm10,%xmm2 - 426e30: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 426e34: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 426e38: 66 0f f8 c8 psubb %xmm0,%xmm1 - 426e3c: 66 0f d7 d1 pmovmskb %xmm1,%edx - 426e40: 81 ea ff ff 00 00 sub $0xffff,%edx - 426e46: 0f 85 54 1f 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 426e4c: 48 83 c1 10 add $0x10,%rcx - 426e50: e9 1b ff ff ff jmpq 426d70 <__GI___strcasecmp_l+0x1a0> - 426e55: 90 nop - 426e56: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 426e5d: 00 00 00 - 426e60: 66 0f ef c0 pxor %xmm0,%xmm0 - 426e64: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 426e68: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 426e6c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 426e70: 66 0f 73 fa 0f pslldq $0xf,%xmm2 - 426e75: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 426e7a: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 426e7f: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 426e84: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 426e89: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 426e8e: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 426e93: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 426e98: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 426e9d: 66 45 0f db c1 pand %xmm9,%xmm8 - 426ea2: 66 45 0f db d3 pand %xmm11,%xmm10 - 426ea7: 66 44 0f db c7 pand %xmm7,%xmm8 - 426eac: 66 44 0f db d7 pand %xmm7,%xmm10 - 426eb1: 66 41 0f eb c8 por %xmm8,%xmm1 - 426eb6: 66 41 0f eb d2 por %xmm10,%xmm2 - 426ebb: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 426ebf: 66 0f f8 d0 psubb %xmm0,%xmm2 - 426ec3: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 426ec8: d3 ea shr %cl,%edx - 426eca: 41 d3 e9 shr %cl,%r9d - 426ecd: 44 29 ca sub %r9d,%edx - 426ed0: 0f 85 cf 1e 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> - 426ed6: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 426eda: 66 0f ef c0 pxor %xmm0,%xmm0 - 426ede: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 426ee5: 41 b9 01 00 00 00 mov $0x1,%r9d - 426eeb: 4c 8d 57 01 lea 0x1(%rdi),%r10 - 426eef: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 426ef6: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 426efd: 0f 1f 00 nopl (%rax) - 426f00: 49 83 c2 10 add $0x10,%r10 - 426f04: 0f 8f 26 01 00 00 jg 427030 <__GI___strcasecmp_l+0x460> - 426f0a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 426f0f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 426f14: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 426f18: 66 0f 73 db 01 psrldq $0x1,%xmm3 - 426f1d: 66 0f 73 fa 0f pslldq $0xf,%xmm2 - 426f22: 66 0f eb d3 por %xmm3,%xmm2 - 426f26: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 426f2b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 426f30: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 426f35: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 426f3a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 426f3f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 426f44: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 426f49: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 426f4e: 66 45 0f db c1 pand %xmm9,%xmm8 - 426f53: 66 45 0f db d3 pand %xmm11,%xmm10 - 426f58: 66 44 0f db c7 pand %xmm7,%xmm8 - 426f5d: 66 44 0f db d7 pand %xmm7,%xmm10 - 426f62: 66 41 0f eb c8 por %xmm8,%xmm1 - 426f67: 66 41 0f eb d2 por %xmm10,%xmm2 - 426f6c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 426f70: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 426f74: 66 0f f8 c8 psubb %xmm0,%xmm1 - 426f78: 66 0f d7 d1 pmovmskb %xmm1,%edx - 426f7c: 81 ea ff ff 00 00 sub $0xffff,%edx - 426f82: 0f 85 18 1e 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 426f88: 48 83 c1 10 add $0x10,%rcx - 426f8c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 426f90: 49 83 c2 10 add $0x10,%r10 - 426f94: 0f 8f 96 00 00 00 jg 427030 <__GI___strcasecmp_l+0x460> - 426f9a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 426f9f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 426fa4: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 426fa8: 66 0f 73 db 01 psrldq $0x1,%xmm3 - 426fad: 66 0f 73 fa 0f pslldq $0xf,%xmm2 - 426fb2: 66 0f eb d3 por %xmm3,%xmm2 - 426fb6: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 426fbb: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 426fc0: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 426fc5: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 426fca: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 426fcf: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 426fd4: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 426fd9: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 426fde: 66 45 0f db c1 pand %xmm9,%xmm8 - 426fe3: 66 45 0f db d3 pand %xmm11,%xmm10 - 426fe8: 66 44 0f db c7 pand %xmm7,%xmm8 - 426fed: 66 44 0f db d7 pand %xmm7,%xmm10 - 426ff2: 66 41 0f eb c8 por %xmm8,%xmm1 - 426ff7: 66 41 0f eb d2 por %xmm10,%xmm2 - 426ffc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 427000: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 427004: 66 0f f8 c8 psubb %xmm0,%xmm1 - 427008: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42700c: 81 ea ff ff 00 00 sub $0xffff,%edx - 427012: 0f 85 88 1d 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 427018: 48 83 c1 10 add $0x10,%rcx - 42701c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 427020: e9 db fe ff ff jmpq 426f00 <__GI___strcasecmp_l+0x330> - 427025: 90 nop - 427026: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42702d: 00 00 00 - 427030: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 427034: 66 0f d7 d0 pmovmskb %xmm0,%edx - 427038: f7 c2 fe ff 00 00 test $0xfffe,%edx - 42703e: 75 10 jne 427050 <__GI___strcasecmp_l+0x480> - 427040: 66 0f ef c0 pxor %xmm0,%xmm0 - 427044: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42704b: e9 ba fe ff ff jmpq 426f0a <__GI___strcasecmp_l+0x33a> - 427050: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 427055: 66 0f 73 d8 01 psrldq $0x1,%xmm0 - 42705a: 66 0f 73 db 01 psrldq $0x1,%xmm3 - 42705f: e9 dc 1c 00 00 jmpq 428d40 <__GI___strcasecmp_l+0x2170> - 427064: 66 90 xchg %ax,%ax - 427066: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42706d: 00 00 00 - 427070: 66 0f ef c0 pxor %xmm0,%xmm0 - 427074: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 427078: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42707c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 427080: 66 0f 73 fa 0e pslldq $0xe,%xmm2 - 427085: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 42708a: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 42708f: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 427094: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 427099: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 42709e: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 4270a3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 4270a8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 4270ad: 66 45 0f db c1 pand %xmm9,%xmm8 - 4270b2: 66 45 0f db d3 pand %xmm11,%xmm10 - 4270b7: 66 44 0f db c7 pand %xmm7,%xmm8 - 4270bc: 66 44 0f db d7 pand %xmm7,%xmm10 - 4270c1: 66 41 0f eb c8 por %xmm8,%xmm1 - 4270c6: 66 41 0f eb d2 por %xmm10,%xmm2 - 4270cb: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 4270cf: 66 0f f8 d0 psubb %xmm0,%xmm2 - 4270d3: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 4270d8: d3 ea shr %cl,%edx - 4270da: 41 d3 e9 shr %cl,%r9d - 4270dd: 44 29 ca sub %r9d,%edx - 4270e0: 0f 85 bf 1c 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> - 4270e6: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 4270ea: 66 0f ef c0 pxor %xmm0,%xmm0 - 4270ee: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 4270f5: 41 b9 02 00 00 00 mov $0x2,%r9d - 4270fb: 4c 8d 57 02 lea 0x2(%rdi),%r10 - 4270ff: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 427106: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42710d: 0f 1f 00 nopl (%rax) - 427110: 49 83 c2 10 add $0x10,%r10 - 427114: 0f 8f 26 01 00 00 jg 427240 <__GI___strcasecmp_l+0x670> - 42711a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42711f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 427124: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 427128: 66 0f 73 db 02 psrldq $0x2,%xmm3 - 42712d: 66 0f 73 fa 0e pslldq $0xe,%xmm2 - 427132: 66 0f eb d3 por %xmm3,%xmm2 - 427136: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 42713b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 427140: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 427145: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 42714a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 42714f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 427154: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 427159: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 42715e: 66 45 0f db c1 pand %xmm9,%xmm8 - 427163: 66 45 0f db d3 pand %xmm11,%xmm10 - 427168: 66 44 0f db c7 pand %xmm7,%xmm8 - 42716d: 66 44 0f db d7 pand %xmm7,%xmm10 - 427172: 66 41 0f eb c8 por %xmm8,%xmm1 - 427177: 66 41 0f eb d2 por %xmm10,%xmm2 - 42717c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 427180: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 427184: 66 0f f8 c8 psubb %xmm0,%xmm1 - 427188: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42718c: 81 ea ff ff 00 00 sub $0xffff,%edx - 427192: 0f 85 08 1c 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 427198: 48 83 c1 10 add $0x10,%rcx - 42719c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 4271a0: 49 83 c2 10 add $0x10,%r10 - 4271a4: 0f 8f 96 00 00 00 jg 427240 <__GI___strcasecmp_l+0x670> - 4271aa: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4271af: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4271b4: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 4271b8: 66 0f 73 db 02 psrldq $0x2,%xmm3 - 4271bd: 66 0f 73 fa 0e pslldq $0xe,%xmm2 - 4271c2: 66 0f eb d3 por %xmm3,%xmm2 - 4271c6: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 4271cb: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 4271d0: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 4271d5: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 4271da: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 4271df: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 4271e4: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 4271e9: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 4271ee: 66 45 0f db c1 pand %xmm9,%xmm8 - 4271f3: 66 45 0f db d3 pand %xmm11,%xmm10 - 4271f8: 66 44 0f db c7 pand %xmm7,%xmm8 - 4271fd: 66 44 0f db d7 pand %xmm7,%xmm10 - 427202: 66 41 0f eb c8 por %xmm8,%xmm1 - 427207: 66 41 0f eb d2 por %xmm10,%xmm2 - 42720c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 427210: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 427214: 66 0f f8 c8 psubb %xmm0,%xmm1 - 427218: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42721c: 81 ea ff ff 00 00 sub $0xffff,%edx - 427222: 0f 85 78 1b 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 427228: 48 83 c1 10 add $0x10,%rcx - 42722c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 427230: e9 db fe ff ff jmpq 427110 <__GI___strcasecmp_l+0x540> - 427235: 90 nop - 427236: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42723d: 00 00 00 - 427240: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 427244: 66 0f d7 d0 pmovmskb %xmm0,%edx - 427248: f7 c2 fc ff 00 00 test $0xfffc,%edx - 42724e: 75 10 jne 427260 <__GI___strcasecmp_l+0x690> - 427250: 66 0f ef c0 pxor %xmm0,%xmm0 - 427254: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42725b: e9 ba fe ff ff jmpq 42711a <__GI___strcasecmp_l+0x54a> - 427260: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 427265: 66 0f 73 d8 02 psrldq $0x2,%xmm0 - 42726a: 66 0f 73 db 02 psrldq $0x2,%xmm3 - 42726f: e9 cc 1a 00 00 jmpq 428d40 <__GI___strcasecmp_l+0x2170> - 427274: 66 90 xchg %ax,%ax - 427276: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42727d: 00 00 00 - 427280: 66 0f ef c0 pxor %xmm0,%xmm0 - 427284: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 427288: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42728c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 427290: 66 0f 73 fa 0d pslldq $0xd,%xmm2 - 427295: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 42729a: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 42729f: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 4272a4: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 4272a9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 4272ae: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 4272b3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 4272b8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 4272bd: 66 45 0f db c1 pand %xmm9,%xmm8 - 4272c2: 66 45 0f db d3 pand %xmm11,%xmm10 - 4272c7: 66 44 0f db c7 pand %xmm7,%xmm8 - 4272cc: 66 44 0f db d7 pand %xmm7,%xmm10 - 4272d1: 66 41 0f eb c8 por %xmm8,%xmm1 - 4272d6: 66 41 0f eb d2 por %xmm10,%xmm2 - 4272db: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 4272df: 66 0f f8 d0 psubb %xmm0,%xmm2 - 4272e3: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 4272e8: d3 ea shr %cl,%edx - 4272ea: 41 d3 e9 shr %cl,%r9d - 4272ed: 44 29 ca sub %r9d,%edx - 4272f0: 0f 85 af 1a 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> - 4272f6: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 4272fa: 66 0f ef c0 pxor %xmm0,%xmm0 - 4272fe: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 427305: 41 b9 03 00 00 00 mov $0x3,%r9d - 42730b: 4c 8d 57 03 lea 0x3(%rdi),%r10 - 42730f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 427316: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42731d: 0f 1f 00 nopl (%rax) - 427320: 49 83 c2 10 add $0x10,%r10 - 427324: 0f 8f 26 01 00 00 jg 427450 <__GI___strcasecmp_l+0x880> - 42732a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42732f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 427334: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 427338: 66 0f 73 db 03 psrldq $0x3,%xmm3 - 42733d: 66 0f 73 fa 0d pslldq $0xd,%xmm2 - 427342: 66 0f eb d3 por %xmm3,%xmm2 - 427346: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 42734b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 427350: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 427355: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 42735a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 42735f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 427364: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 427369: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 42736e: 66 45 0f db c1 pand %xmm9,%xmm8 - 427373: 66 45 0f db d3 pand %xmm11,%xmm10 - 427378: 66 44 0f db c7 pand %xmm7,%xmm8 - 42737d: 66 44 0f db d7 pand %xmm7,%xmm10 - 427382: 66 41 0f eb c8 por %xmm8,%xmm1 - 427387: 66 41 0f eb d2 por %xmm10,%xmm2 - 42738c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 427390: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 427394: 66 0f f8 c8 psubb %xmm0,%xmm1 - 427398: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42739c: 81 ea ff ff 00 00 sub $0xffff,%edx - 4273a2: 0f 85 f8 19 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 4273a8: 48 83 c1 10 add $0x10,%rcx - 4273ac: 66 0f 6f dc movdqa %xmm4,%xmm3 - 4273b0: 49 83 c2 10 add $0x10,%r10 - 4273b4: 0f 8f 96 00 00 00 jg 427450 <__GI___strcasecmp_l+0x880> - 4273ba: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4273bf: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4273c4: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 4273c8: 66 0f 73 db 03 psrldq $0x3,%xmm3 - 4273cd: 66 0f 73 fa 0d pslldq $0xd,%xmm2 - 4273d2: 66 0f eb d3 por %xmm3,%xmm2 - 4273d6: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 4273db: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 4273e0: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 4273e5: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 4273ea: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 4273ef: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 4273f4: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 4273f9: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 4273fe: 66 45 0f db c1 pand %xmm9,%xmm8 - 427403: 66 45 0f db d3 pand %xmm11,%xmm10 - 427408: 66 44 0f db c7 pand %xmm7,%xmm8 - 42740d: 66 44 0f db d7 pand %xmm7,%xmm10 - 427412: 66 41 0f eb c8 por %xmm8,%xmm1 - 427417: 66 41 0f eb d2 por %xmm10,%xmm2 - 42741c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 427420: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 427424: 66 0f f8 c8 psubb %xmm0,%xmm1 - 427428: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42742c: 81 ea ff ff 00 00 sub $0xffff,%edx - 427432: 0f 85 68 19 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 427438: 48 83 c1 10 add $0x10,%rcx - 42743c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 427440: e9 db fe ff ff jmpq 427320 <__GI___strcasecmp_l+0x750> - 427445: 90 nop - 427446: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42744d: 00 00 00 - 427450: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 427454: 66 0f d7 d0 pmovmskb %xmm0,%edx - 427458: f7 c2 f8 ff 00 00 test $0xfff8,%edx - 42745e: 75 10 jne 427470 <__GI___strcasecmp_l+0x8a0> - 427460: 66 0f ef c0 pxor %xmm0,%xmm0 - 427464: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42746b: e9 ba fe ff ff jmpq 42732a <__GI___strcasecmp_l+0x75a> - 427470: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 427475: 66 0f 73 d8 03 psrldq $0x3,%xmm0 - 42747a: 66 0f 73 db 03 psrldq $0x3,%xmm3 - 42747f: e9 bc 18 00 00 jmpq 428d40 <__GI___strcasecmp_l+0x2170> - 427484: 66 90 xchg %ax,%ax - 427486: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42748d: 00 00 00 - 427490: 66 0f ef c0 pxor %xmm0,%xmm0 - 427494: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 427498: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42749c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4274a0: 66 0f 73 fa 0c pslldq $0xc,%xmm2 - 4274a5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 4274aa: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 4274af: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 4274b4: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 4274b9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 4274be: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 4274c3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 4274c8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 4274cd: 66 45 0f db c1 pand %xmm9,%xmm8 - 4274d2: 66 45 0f db d3 pand %xmm11,%xmm10 - 4274d7: 66 44 0f db c7 pand %xmm7,%xmm8 - 4274dc: 66 44 0f db d7 pand %xmm7,%xmm10 - 4274e1: 66 41 0f eb c8 por %xmm8,%xmm1 - 4274e6: 66 41 0f eb d2 por %xmm10,%xmm2 - 4274eb: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 4274ef: 66 0f f8 d0 psubb %xmm0,%xmm2 - 4274f3: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 4274f8: d3 ea shr %cl,%edx - 4274fa: 41 d3 e9 shr %cl,%r9d - 4274fd: 44 29 ca sub %r9d,%edx - 427500: 0f 85 9f 18 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> - 427506: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 42750a: 66 0f ef c0 pxor %xmm0,%xmm0 - 42750e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 427515: 41 b9 04 00 00 00 mov $0x4,%r9d - 42751b: 4c 8d 57 04 lea 0x4(%rdi),%r10 - 42751f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 427526: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42752d: 0f 1f 00 nopl (%rax) - 427530: 49 83 c2 10 add $0x10,%r10 - 427534: 0f 8f 26 01 00 00 jg 427660 <__GI___strcasecmp_l+0xa90> - 42753a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42753f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 427544: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 427548: 66 0f 73 db 04 psrldq $0x4,%xmm3 - 42754d: 66 0f 73 fa 0c pslldq $0xc,%xmm2 - 427552: 66 0f eb d3 por %xmm3,%xmm2 - 427556: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 42755b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 427560: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 427565: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 42756a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 42756f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 427574: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 427579: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 42757e: 66 45 0f db c1 pand %xmm9,%xmm8 - 427583: 66 45 0f db d3 pand %xmm11,%xmm10 - 427588: 66 44 0f db c7 pand %xmm7,%xmm8 - 42758d: 66 44 0f db d7 pand %xmm7,%xmm10 - 427592: 66 41 0f eb c8 por %xmm8,%xmm1 - 427597: 66 41 0f eb d2 por %xmm10,%xmm2 - 42759c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4275a0: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 4275a4: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4275a8: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4275ac: 81 ea ff ff 00 00 sub $0xffff,%edx - 4275b2: 0f 85 e8 17 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 4275b8: 48 83 c1 10 add $0x10,%rcx - 4275bc: 66 0f 6f dc movdqa %xmm4,%xmm3 - 4275c0: 49 83 c2 10 add $0x10,%r10 - 4275c4: 0f 8f 96 00 00 00 jg 427660 <__GI___strcasecmp_l+0xa90> - 4275ca: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4275cf: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4275d4: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 4275d8: 66 0f 73 db 04 psrldq $0x4,%xmm3 - 4275dd: 66 0f 73 fa 0c pslldq $0xc,%xmm2 - 4275e2: 66 0f eb d3 por %xmm3,%xmm2 - 4275e6: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 4275eb: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 4275f0: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 4275f5: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 4275fa: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 4275ff: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 427604: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 427609: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 42760e: 66 45 0f db c1 pand %xmm9,%xmm8 - 427613: 66 45 0f db d3 pand %xmm11,%xmm10 - 427618: 66 44 0f db c7 pand %xmm7,%xmm8 - 42761d: 66 44 0f db d7 pand %xmm7,%xmm10 - 427622: 66 41 0f eb c8 por %xmm8,%xmm1 - 427627: 66 41 0f eb d2 por %xmm10,%xmm2 - 42762c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 427630: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 427634: 66 0f f8 c8 psubb %xmm0,%xmm1 - 427638: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42763c: 81 ea ff ff 00 00 sub $0xffff,%edx - 427642: 0f 85 58 17 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 427648: 48 83 c1 10 add $0x10,%rcx - 42764c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 427650: e9 db fe ff ff jmpq 427530 <__GI___strcasecmp_l+0x960> - 427655: 90 nop - 427656: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42765d: 00 00 00 - 427660: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 427664: 66 0f d7 d0 pmovmskb %xmm0,%edx - 427668: f7 c2 f0 ff 00 00 test $0xfff0,%edx - 42766e: 75 10 jne 427680 <__GI___strcasecmp_l+0xab0> - 427670: 66 0f ef c0 pxor %xmm0,%xmm0 - 427674: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42767b: e9 ba fe ff ff jmpq 42753a <__GI___strcasecmp_l+0x96a> - 427680: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 427685: 66 0f 73 d8 04 psrldq $0x4,%xmm0 - 42768a: 66 0f 73 db 04 psrldq $0x4,%xmm3 - 42768f: e9 ac 16 00 00 jmpq 428d40 <__GI___strcasecmp_l+0x2170> - 427694: 66 90 xchg %ax,%ax - 427696: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42769d: 00 00 00 - 4276a0: 66 0f ef c0 pxor %xmm0,%xmm0 - 4276a4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 4276a8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 4276ac: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4276b0: 66 0f 73 fa 0b pslldq $0xb,%xmm2 - 4276b5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 4276ba: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 4276bf: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 4276c4: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 4276c9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 4276ce: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 4276d3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 4276d8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 4276dd: 66 45 0f db c1 pand %xmm9,%xmm8 - 4276e2: 66 45 0f db d3 pand %xmm11,%xmm10 - 4276e7: 66 44 0f db c7 pand %xmm7,%xmm8 - 4276ec: 66 44 0f db d7 pand %xmm7,%xmm10 - 4276f1: 66 41 0f eb c8 por %xmm8,%xmm1 - 4276f6: 66 41 0f eb d2 por %xmm10,%xmm2 - 4276fb: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 4276ff: 66 0f f8 d0 psubb %xmm0,%xmm2 - 427703: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 427708: d3 ea shr %cl,%edx - 42770a: 41 d3 e9 shr %cl,%r9d - 42770d: 44 29 ca sub %r9d,%edx - 427710: 0f 85 8f 16 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> - 427716: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 42771a: 66 0f ef c0 pxor %xmm0,%xmm0 - 42771e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 427725: 41 b9 05 00 00 00 mov $0x5,%r9d - 42772b: 4c 8d 57 05 lea 0x5(%rdi),%r10 - 42772f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 427736: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42773d: 0f 1f 00 nopl (%rax) - 427740: 49 83 c2 10 add $0x10,%r10 - 427744: 0f 8f 26 01 00 00 jg 427870 <__GI___strcasecmp_l+0xca0> - 42774a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42774f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 427754: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 427758: 66 0f 73 db 05 psrldq $0x5,%xmm3 - 42775d: 66 0f 73 fa 0b pslldq $0xb,%xmm2 - 427762: 66 0f eb d3 por %xmm3,%xmm2 - 427766: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 42776b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 427770: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 427775: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 42777a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 42777f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 427784: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 427789: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 42778e: 66 45 0f db c1 pand %xmm9,%xmm8 - 427793: 66 45 0f db d3 pand %xmm11,%xmm10 - 427798: 66 44 0f db c7 pand %xmm7,%xmm8 - 42779d: 66 44 0f db d7 pand %xmm7,%xmm10 - 4277a2: 66 41 0f eb c8 por %xmm8,%xmm1 - 4277a7: 66 41 0f eb d2 por %xmm10,%xmm2 - 4277ac: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4277b0: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 4277b4: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4277b8: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4277bc: 81 ea ff ff 00 00 sub $0xffff,%edx - 4277c2: 0f 85 d8 15 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 4277c8: 48 83 c1 10 add $0x10,%rcx - 4277cc: 66 0f 6f dc movdqa %xmm4,%xmm3 - 4277d0: 49 83 c2 10 add $0x10,%r10 - 4277d4: 0f 8f 96 00 00 00 jg 427870 <__GI___strcasecmp_l+0xca0> - 4277da: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4277df: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4277e4: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 4277e8: 66 0f 73 db 05 psrldq $0x5,%xmm3 - 4277ed: 66 0f 73 fa 0b pslldq $0xb,%xmm2 - 4277f2: 66 0f eb d3 por %xmm3,%xmm2 - 4277f6: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 4277fb: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 427800: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 427805: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 42780a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 42780f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 427814: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 427819: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 42781e: 66 45 0f db c1 pand %xmm9,%xmm8 - 427823: 66 45 0f db d3 pand %xmm11,%xmm10 - 427828: 66 44 0f db c7 pand %xmm7,%xmm8 - 42782d: 66 44 0f db d7 pand %xmm7,%xmm10 - 427832: 66 41 0f eb c8 por %xmm8,%xmm1 - 427837: 66 41 0f eb d2 por %xmm10,%xmm2 - 42783c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 427840: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 427844: 66 0f f8 c8 psubb %xmm0,%xmm1 - 427848: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42784c: 81 ea ff ff 00 00 sub $0xffff,%edx - 427852: 0f 85 48 15 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 427858: 48 83 c1 10 add $0x10,%rcx - 42785c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 427860: e9 db fe ff ff jmpq 427740 <__GI___strcasecmp_l+0xb70> - 427865: 90 nop - 427866: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42786d: 00 00 00 - 427870: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 427874: 66 0f d7 d0 pmovmskb %xmm0,%edx - 427878: f7 c2 e0 ff 00 00 test $0xffe0,%edx - 42787e: 75 10 jne 427890 <__GI___strcasecmp_l+0xcc0> - 427880: 66 0f ef c0 pxor %xmm0,%xmm0 - 427884: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42788b: e9 ba fe ff ff jmpq 42774a <__GI___strcasecmp_l+0xb7a> - 427890: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 427895: 66 0f 73 d8 05 psrldq $0x5,%xmm0 - 42789a: 66 0f 73 db 05 psrldq $0x5,%xmm3 - 42789f: e9 9c 14 00 00 jmpq 428d40 <__GI___strcasecmp_l+0x2170> - 4278a4: 66 90 xchg %ax,%ax - 4278a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4278ad: 00 00 00 - 4278b0: 66 0f ef c0 pxor %xmm0,%xmm0 - 4278b4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 4278b8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 4278bc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4278c0: 66 0f 73 fa 0a pslldq $0xa,%xmm2 - 4278c5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 4278ca: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 4278cf: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 4278d4: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 4278d9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 4278de: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 4278e3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 4278e8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 4278ed: 66 45 0f db c1 pand %xmm9,%xmm8 - 4278f2: 66 45 0f db d3 pand %xmm11,%xmm10 - 4278f7: 66 44 0f db c7 pand %xmm7,%xmm8 - 4278fc: 66 44 0f db d7 pand %xmm7,%xmm10 - 427901: 66 41 0f eb c8 por %xmm8,%xmm1 - 427906: 66 41 0f eb d2 por %xmm10,%xmm2 - 42790b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42790f: 66 0f f8 d0 psubb %xmm0,%xmm2 - 427913: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 427918: d3 ea shr %cl,%edx - 42791a: 41 d3 e9 shr %cl,%r9d - 42791d: 44 29 ca sub %r9d,%edx - 427920: 0f 85 7f 14 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> - 427926: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 42792a: 66 0f ef c0 pxor %xmm0,%xmm0 - 42792e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 427935: 41 b9 06 00 00 00 mov $0x6,%r9d - 42793b: 4c 8d 57 06 lea 0x6(%rdi),%r10 - 42793f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 427946: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42794d: 0f 1f 00 nopl (%rax) - 427950: 49 83 c2 10 add $0x10,%r10 - 427954: 0f 8f 26 01 00 00 jg 427a80 <__GI___strcasecmp_l+0xeb0> - 42795a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42795f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 427964: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 427968: 66 0f 73 db 06 psrldq $0x6,%xmm3 - 42796d: 66 0f 73 fa 0a pslldq $0xa,%xmm2 - 427972: 66 0f eb d3 por %xmm3,%xmm2 - 427976: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 42797b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 427980: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 427985: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 42798a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 42798f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 427994: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 427999: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 42799e: 66 45 0f db c1 pand %xmm9,%xmm8 - 4279a3: 66 45 0f db d3 pand %xmm11,%xmm10 - 4279a8: 66 44 0f db c7 pand %xmm7,%xmm8 - 4279ad: 66 44 0f db d7 pand %xmm7,%xmm10 - 4279b2: 66 41 0f eb c8 por %xmm8,%xmm1 - 4279b7: 66 41 0f eb d2 por %xmm10,%xmm2 - 4279bc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4279c0: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 4279c4: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4279c8: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4279cc: 81 ea ff ff 00 00 sub $0xffff,%edx - 4279d2: 0f 85 c8 13 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 4279d8: 48 83 c1 10 add $0x10,%rcx - 4279dc: 66 0f 6f dc movdqa %xmm4,%xmm3 - 4279e0: 49 83 c2 10 add $0x10,%r10 - 4279e4: 0f 8f 96 00 00 00 jg 427a80 <__GI___strcasecmp_l+0xeb0> - 4279ea: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4279ef: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4279f4: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 4279f8: 66 0f 73 db 06 psrldq $0x6,%xmm3 - 4279fd: 66 0f 73 fa 0a pslldq $0xa,%xmm2 - 427a02: 66 0f eb d3 por %xmm3,%xmm2 - 427a06: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 427a0b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 427a10: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 427a15: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 427a1a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 427a1f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 427a24: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 427a29: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 427a2e: 66 45 0f db c1 pand %xmm9,%xmm8 - 427a33: 66 45 0f db d3 pand %xmm11,%xmm10 - 427a38: 66 44 0f db c7 pand %xmm7,%xmm8 - 427a3d: 66 44 0f db d7 pand %xmm7,%xmm10 - 427a42: 66 41 0f eb c8 por %xmm8,%xmm1 - 427a47: 66 41 0f eb d2 por %xmm10,%xmm2 - 427a4c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 427a50: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 427a54: 66 0f f8 c8 psubb %xmm0,%xmm1 - 427a58: 66 0f d7 d1 pmovmskb %xmm1,%edx - 427a5c: 81 ea ff ff 00 00 sub $0xffff,%edx - 427a62: 0f 85 38 13 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 427a68: 48 83 c1 10 add $0x10,%rcx - 427a6c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 427a70: e9 db fe ff ff jmpq 427950 <__GI___strcasecmp_l+0xd80> - 427a75: 90 nop - 427a76: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 427a7d: 00 00 00 - 427a80: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 427a84: 66 0f d7 d0 pmovmskb %xmm0,%edx - 427a88: f7 c2 c0 ff 00 00 test $0xffc0,%edx - 427a8e: 75 10 jne 427aa0 <__GI___strcasecmp_l+0xed0> - 427a90: 66 0f ef c0 pxor %xmm0,%xmm0 - 427a94: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 427a9b: e9 ba fe ff ff jmpq 42795a <__GI___strcasecmp_l+0xd8a> - 427aa0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 427aa5: 66 0f 73 d8 06 psrldq $0x6,%xmm0 - 427aaa: 66 0f 73 db 06 psrldq $0x6,%xmm3 - 427aaf: e9 8c 12 00 00 jmpq 428d40 <__GI___strcasecmp_l+0x2170> - 427ab4: 66 90 xchg %ax,%ax - 427ab6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 427abd: 00 00 00 - 427ac0: 66 0f ef c0 pxor %xmm0,%xmm0 - 427ac4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 427ac8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 427acc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 427ad0: 66 0f 73 fa 09 pslldq $0x9,%xmm2 - 427ad5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 427ada: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 427adf: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 427ae4: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 427ae9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 427aee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 427af3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 427af8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 427afd: 66 45 0f db c1 pand %xmm9,%xmm8 - 427b02: 66 45 0f db d3 pand %xmm11,%xmm10 - 427b07: 66 44 0f db c7 pand %xmm7,%xmm8 - 427b0c: 66 44 0f db d7 pand %xmm7,%xmm10 - 427b11: 66 41 0f eb c8 por %xmm8,%xmm1 - 427b16: 66 41 0f eb d2 por %xmm10,%xmm2 - 427b1b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 427b1f: 66 0f f8 d0 psubb %xmm0,%xmm2 - 427b23: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 427b28: d3 ea shr %cl,%edx - 427b2a: 41 d3 e9 shr %cl,%r9d - 427b2d: 44 29 ca sub %r9d,%edx - 427b30: 0f 85 6f 12 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> - 427b36: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 427b3a: 66 0f ef c0 pxor %xmm0,%xmm0 - 427b3e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 427b45: 41 b9 07 00 00 00 mov $0x7,%r9d - 427b4b: 4c 8d 57 07 lea 0x7(%rdi),%r10 - 427b4f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 427b56: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 427b5d: 0f 1f 00 nopl (%rax) - 427b60: 49 83 c2 10 add $0x10,%r10 - 427b64: 0f 8f 26 01 00 00 jg 427c90 <__GI___strcasecmp_l+0x10c0> - 427b6a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 427b6f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 427b74: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 427b78: 66 0f 73 db 07 psrldq $0x7,%xmm3 - 427b7d: 66 0f 73 fa 09 pslldq $0x9,%xmm2 - 427b82: 66 0f eb d3 por %xmm3,%xmm2 - 427b86: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 427b8b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 427b90: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 427b95: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 427b9a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 427b9f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 427ba4: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 427ba9: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 427bae: 66 45 0f db c1 pand %xmm9,%xmm8 - 427bb3: 66 45 0f db d3 pand %xmm11,%xmm10 - 427bb8: 66 44 0f db c7 pand %xmm7,%xmm8 - 427bbd: 66 44 0f db d7 pand %xmm7,%xmm10 - 427bc2: 66 41 0f eb c8 por %xmm8,%xmm1 - 427bc7: 66 41 0f eb d2 por %xmm10,%xmm2 - 427bcc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 427bd0: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 427bd4: 66 0f f8 c8 psubb %xmm0,%xmm1 - 427bd8: 66 0f d7 d1 pmovmskb %xmm1,%edx - 427bdc: 81 ea ff ff 00 00 sub $0xffff,%edx - 427be2: 0f 85 b8 11 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 427be8: 48 83 c1 10 add $0x10,%rcx - 427bec: 66 0f 6f dc movdqa %xmm4,%xmm3 - 427bf0: 49 83 c2 10 add $0x10,%r10 - 427bf4: 0f 8f 96 00 00 00 jg 427c90 <__GI___strcasecmp_l+0x10c0> - 427bfa: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 427bff: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 427c04: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 427c08: 66 0f 73 db 07 psrldq $0x7,%xmm3 - 427c0d: 66 0f 73 fa 09 pslldq $0x9,%xmm2 - 427c12: 66 0f eb d3 por %xmm3,%xmm2 - 427c16: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 427c1b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 427c20: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 427c25: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 427c2a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 427c2f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 427c34: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 427c39: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 427c3e: 66 45 0f db c1 pand %xmm9,%xmm8 - 427c43: 66 45 0f db d3 pand %xmm11,%xmm10 - 427c48: 66 44 0f db c7 pand %xmm7,%xmm8 - 427c4d: 66 44 0f db d7 pand %xmm7,%xmm10 - 427c52: 66 41 0f eb c8 por %xmm8,%xmm1 - 427c57: 66 41 0f eb d2 por %xmm10,%xmm2 - 427c5c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 427c60: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 427c64: 66 0f f8 c8 psubb %xmm0,%xmm1 - 427c68: 66 0f d7 d1 pmovmskb %xmm1,%edx - 427c6c: 81 ea ff ff 00 00 sub $0xffff,%edx - 427c72: 0f 85 28 11 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 427c78: 48 83 c1 10 add $0x10,%rcx - 427c7c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 427c80: e9 db fe ff ff jmpq 427b60 <__GI___strcasecmp_l+0xf90> - 427c85: 90 nop - 427c86: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 427c8d: 00 00 00 - 427c90: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 427c94: 66 0f d7 d0 pmovmskb %xmm0,%edx - 427c98: f7 c2 80 ff 00 00 test $0xff80,%edx - 427c9e: 75 10 jne 427cb0 <__GI___strcasecmp_l+0x10e0> - 427ca0: 66 0f ef c0 pxor %xmm0,%xmm0 - 427ca4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 427cab: e9 ba fe ff ff jmpq 427b6a <__GI___strcasecmp_l+0xf9a> - 427cb0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 427cb5: 66 0f 73 d8 07 psrldq $0x7,%xmm0 - 427cba: 66 0f 73 db 07 psrldq $0x7,%xmm3 - 427cbf: e9 7c 10 00 00 jmpq 428d40 <__GI___strcasecmp_l+0x2170> - 427cc4: 66 90 xchg %ax,%ax - 427cc6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 427ccd: 00 00 00 - 427cd0: 66 0f ef c0 pxor %xmm0,%xmm0 - 427cd4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 427cd8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 427cdc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 427ce0: 66 0f 73 fa 08 pslldq $0x8,%xmm2 - 427ce5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 427cea: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 427cef: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 427cf4: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 427cf9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 427cfe: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 427d03: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 427d08: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 427d0d: 66 45 0f db c1 pand %xmm9,%xmm8 - 427d12: 66 45 0f db d3 pand %xmm11,%xmm10 - 427d17: 66 44 0f db c7 pand %xmm7,%xmm8 - 427d1c: 66 44 0f db d7 pand %xmm7,%xmm10 - 427d21: 66 41 0f eb c8 por %xmm8,%xmm1 - 427d26: 66 41 0f eb d2 por %xmm10,%xmm2 - 427d2b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 427d2f: 66 0f f8 d0 psubb %xmm0,%xmm2 - 427d33: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 427d38: d3 ea shr %cl,%edx - 427d3a: 41 d3 e9 shr %cl,%r9d - 427d3d: 44 29 ca sub %r9d,%edx - 427d40: 0f 85 5f 10 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> - 427d46: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 427d4a: 66 0f ef c0 pxor %xmm0,%xmm0 - 427d4e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 427d55: 41 b9 08 00 00 00 mov $0x8,%r9d - 427d5b: 4c 8d 57 08 lea 0x8(%rdi),%r10 - 427d5f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 427d66: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 427d6d: 0f 1f 00 nopl (%rax) - 427d70: 49 83 c2 10 add $0x10,%r10 - 427d74: 0f 8f 26 01 00 00 jg 427ea0 <__GI___strcasecmp_l+0x12d0> - 427d7a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 427d7f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 427d84: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 427d88: 66 0f 73 db 08 psrldq $0x8,%xmm3 - 427d8d: 66 0f 73 fa 08 pslldq $0x8,%xmm2 - 427d92: 66 0f eb d3 por %xmm3,%xmm2 - 427d96: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 427d9b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 427da0: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 427da5: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 427daa: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 427daf: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 427db4: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 427db9: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 427dbe: 66 45 0f db c1 pand %xmm9,%xmm8 - 427dc3: 66 45 0f db d3 pand %xmm11,%xmm10 - 427dc8: 66 44 0f db c7 pand %xmm7,%xmm8 - 427dcd: 66 44 0f db d7 pand %xmm7,%xmm10 - 427dd2: 66 41 0f eb c8 por %xmm8,%xmm1 - 427dd7: 66 41 0f eb d2 por %xmm10,%xmm2 - 427ddc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 427de0: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 427de4: 66 0f f8 c8 psubb %xmm0,%xmm1 - 427de8: 66 0f d7 d1 pmovmskb %xmm1,%edx - 427dec: 81 ea ff ff 00 00 sub $0xffff,%edx - 427df2: 0f 85 a8 0f 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 427df8: 48 83 c1 10 add $0x10,%rcx - 427dfc: 66 0f 6f dc movdqa %xmm4,%xmm3 - 427e00: 49 83 c2 10 add $0x10,%r10 - 427e04: 0f 8f 96 00 00 00 jg 427ea0 <__GI___strcasecmp_l+0x12d0> - 427e0a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 427e0f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 427e14: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 427e18: 66 0f 73 db 08 psrldq $0x8,%xmm3 - 427e1d: 66 0f 73 fa 08 pslldq $0x8,%xmm2 - 427e22: 66 0f eb d3 por %xmm3,%xmm2 - 427e26: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 427e2b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 427e30: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 427e35: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 427e3a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 427e3f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 427e44: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 427e49: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 427e4e: 66 45 0f db c1 pand %xmm9,%xmm8 - 427e53: 66 45 0f db d3 pand %xmm11,%xmm10 - 427e58: 66 44 0f db c7 pand %xmm7,%xmm8 - 427e5d: 66 44 0f db d7 pand %xmm7,%xmm10 - 427e62: 66 41 0f eb c8 por %xmm8,%xmm1 - 427e67: 66 41 0f eb d2 por %xmm10,%xmm2 - 427e6c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 427e70: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 427e74: 66 0f f8 c8 psubb %xmm0,%xmm1 - 427e78: 66 0f d7 d1 pmovmskb %xmm1,%edx - 427e7c: 81 ea ff ff 00 00 sub $0xffff,%edx - 427e82: 0f 85 18 0f 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 427e88: 48 83 c1 10 add $0x10,%rcx - 427e8c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 427e90: e9 db fe ff ff jmpq 427d70 <__GI___strcasecmp_l+0x11a0> - 427e95: 90 nop - 427e96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 427e9d: 00 00 00 - 427ea0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 427ea4: 66 0f d7 d0 pmovmskb %xmm0,%edx - 427ea8: f7 c2 00 ff 00 00 test $0xff00,%edx - 427eae: 75 10 jne 427ec0 <__GI___strcasecmp_l+0x12f0> - 427eb0: 66 0f ef c0 pxor %xmm0,%xmm0 - 427eb4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 427ebb: e9 ba fe ff ff jmpq 427d7a <__GI___strcasecmp_l+0x11aa> - 427ec0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 427ec5: 66 0f 73 d8 08 psrldq $0x8,%xmm0 - 427eca: 66 0f 73 db 08 psrldq $0x8,%xmm3 - 427ecf: e9 6c 0e 00 00 jmpq 428d40 <__GI___strcasecmp_l+0x2170> - 427ed4: 66 90 xchg %ax,%ax - 427ed6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 427edd: 00 00 00 - 427ee0: 66 0f ef c0 pxor %xmm0,%xmm0 - 427ee4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 427ee8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 427eec: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 427ef0: 66 0f 73 fa 07 pslldq $0x7,%xmm2 - 427ef5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 427efa: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 427eff: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 427f04: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 427f09: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 427f0e: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 427f13: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 427f18: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 427f1d: 66 45 0f db c1 pand %xmm9,%xmm8 - 427f22: 66 45 0f db d3 pand %xmm11,%xmm10 - 427f27: 66 44 0f db c7 pand %xmm7,%xmm8 - 427f2c: 66 44 0f db d7 pand %xmm7,%xmm10 - 427f31: 66 41 0f eb c8 por %xmm8,%xmm1 - 427f36: 66 41 0f eb d2 por %xmm10,%xmm2 - 427f3b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 427f3f: 66 0f f8 d0 psubb %xmm0,%xmm2 - 427f43: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 427f48: d3 ea shr %cl,%edx - 427f4a: 41 d3 e9 shr %cl,%r9d - 427f4d: 44 29 ca sub %r9d,%edx - 427f50: 0f 85 4f 0e 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> - 427f56: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 427f5a: 66 0f ef c0 pxor %xmm0,%xmm0 - 427f5e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 427f65: 41 b9 09 00 00 00 mov $0x9,%r9d - 427f6b: 4c 8d 57 09 lea 0x9(%rdi),%r10 - 427f6f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 427f76: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 427f7d: 0f 1f 00 nopl (%rax) - 427f80: 49 83 c2 10 add $0x10,%r10 - 427f84: 0f 8f 26 01 00 00 jg 4280b0 <__GI___strcasecmp_l+0x14e0> - 427f8a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 427f8f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 427f94: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 427f98: 66 0f 73 db 09 psrldq $0x9,%xmm3 - 427f9d: 66 0f 73 fa 07 pslldq $0x7,%xmm2 - 427fa2: 66 0f eb d3 por %xmm3,%xmm2 - 427fa6: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 427fab: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 427fb0: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 427fb5: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 427fba: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 427fbf: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 427fc4: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 427fc9: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 427fce: 66 45 0f db c1 pand %xmm9,%xmm8 - 427fd3: 66 45 0f db d3 pand %xmm11,%xmm10 - 427fd8: 66 44 0f db c7 pand %xmm7,%xmm8 - 427fdd: 66 44 0f db d7 pand %xmm7,%xmm10 - 427fe2: 66 41 0f eb c8 por %xmm8,%xmm1 - 427fe7: 66 41 0f eb d2 por %xmm10,%xmm2 - 427fec: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 427ff0: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 427ff4: 66 0f f8 c8 psubb %xmm0,%xmm1 - 427ff8: 66 0f d7 d1 pmovmskb %xmm1,%edx - 427ffc: 81 ea ff ff 00 00 sub $0xffff,%edx - 428002: 0f 85 98 0d 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 428008: 48 83 c1 10 add $0x10,%rcx - 42800c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 428010: 49 83 c2 10 add $0x10,%r10 - 428014: 0f 8f 96 00 00 00 jg 4280b0 <__GI___strcasecmp_l+0x14e0> - 42801a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42801f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 428024: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 428028: 66 0f 73 db 09 psrldq $0x9,%xmm3 - 42802d: 66 0f 73 fa 07 pslldq $0x7,%xmm2 - 428032: 66 0f eb d3 por %xmm3,%xmm2 - 428036: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 42803b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 428040: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 428045: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 42804a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 42804f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 428054: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 428059: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 42805e: 66 45 0f db c1 pand %xmm9,%xmm8 - 428063: 66 45 0f db d3 pand %xmm11,%xmm10 - 428068: 66 44 0f db c7 pand %xmm7,%xmm8 - 42806d: 66 44 0f db d7 pand %xmm7,%xmm10 - 428072: 66 41 0f eb c8 por %xmm8,%xmm1 - 428077: 66 41 0f eb d2 por %xmm10,%xmm2 - 42807c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 428080: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 428084: 66 0f f8 c8 psubb %xmm0,%xmm1 - 428088: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42808c: 81 ea ff ff 00 00 sub $0xffff,%edx - 428092: 0f 85 08 0d 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 428098: 48 83 c1 10 add $0x10,%rcx - 42809c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 4280a0: e9 db fe ff ff jmpq 427f80 <__GI___strcasecmp_l+0x13b0> - 4280a5: 90 nop - 4280a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4280ad: 00 00 00 - 4280b0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 4280b4: 66 0f d7 d0 pmovmskb %xmm0,%edx - 4280b8: f7 c2 00 fe 00 00 test $0xfe00,%edx - 4280be: 75 10 jne 4280d0 <__GI___strcasecmp_l+0x1500> - 4280c0: 66 0f ef c0 pxor %xmm0,%xmm0 - 4280c4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 4280cb: e9 ba fe ff ff jmpq 427f8a <__GI___strcasecmp_l+0x13ba> - 4280d0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4280d5: 66 0f 73 d8 09 psrldq $0x9,%xmm0 - 4280da: 66 0f 73 db 09 psrldq $0x9,%xmm3 - 4280df: e9 5c 0c 00 00 jmpq 428d40 <__GI___strcasecmp_l+0x2170> - 4280e4: 66 90 xchg %ax,%ax - 4280e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4280ed: 00 00 00 - 4280f0: 66 0f ef c0 pxor %xmm0,%xmm0 - 4280f4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 4280f8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 4280fc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 428100: 66 0f 73 fa 06 pslldq $0x6,%xmm2 - 428105: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 42810a: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 42810f: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 428114: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 428119: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 42811e: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 428123: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 428128: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 42812d: 66 45 0f db c1 pand %xmm9,%xmm8 - 428132: 66 45 0f db d3 pand %xmm11,%xmm10 - 428137: 66 44 0f db c7 pand %xmm7,%xmm8 - 42813c: 66 44 0f db d7 pand %xmm7,%xmm10 - 428141: 66 41 0f eb c8 por %xmm8,%xmm1 - 428146: 66 41 0f eb d2 por %xmm10,%xmm2 - 42814b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42814f: 66 0f f8 d0 psubb %xmm0,%xmm2 - 428153: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 428158: d3 ea shr %cl,%edx - 42815a: 41 d3 e9 shr %cl,%r9d - 42815d: 44 29 ca sub %r9d,%edx - 428160: 0f 85 3f 0c 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> - 428166: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 42816a: 66 0f ef c0 pxor %xmm0,%xmm0 - 42816e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 428175: 41 b9 0a 00 00 00 mov $0xa,%r9d - 42817b: 4c 8d 57 0a lea 0xa(%rdi),%r10 - 42817f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 428186: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42818d: 0f 1f 00 nopl (%rax) - 428190: 49 83 c2 10 add $0x10,%r10 - 428194: 0f 8f 26 01 00 00 jg 4282c0 <__GI___strcasecmp_l+0x16f0> - 42819a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42819f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4281a4: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 4281a8: 66 0f 73 db 0a psrldq $0xa,%xmm3 - 4281ad: 66 0f 73 fa 06 pslldq $0x6,%xmm2 - 4281b2: 66 0f eb d3 por %xmm3,%xmm2 - 4281b6: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 4281bb: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 4281c0: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 4281c5: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 4281ca: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 4281cf: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 4281d4: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 4281d9: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 4281de: 66 45 0f db c1 pand %xmm9,%xmm8 - 4281e3: 66 45 0f db d3 pand %xmm11,%xmm10 - 4281e8: 66 44 0f db c7 pand %xmm7,%xmm8 - 4281ed: 66 44 0f db d7 pand %xmm7,%xmm10 - 4281f2: 66 41 0f eb c8 por %xmm8,%xmm1 - 4281f7: 66 41 0f eb d2 por %xmm10,%xmm2 - 4281fc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 428200: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 428204: 66 0f f8 c8 psubb %xmm0,%xmm1 - 428208: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42820c: 81 ea ff ff 00 00 sub $0xffff,%edx - 428212: 0f 85 88 0b 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 428218: 48 83 c1 10 add $0x10,%rcx - 42821c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 428220: 49 83 c2 10 add $0x10,%r10 - 428224: 0f 8f 96 00 00 00 jg 4282c0 <__GI___strcasecmp_l+0x16f0> - 42822a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42822f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 428234: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 428238: 66 0f 73 db 0a psrldq $0xa,%xmm3 - 42823d: 66 0f 73 fa 06 pslldq $0x6,%xmm2 - 428242: 66 0f eb d3 por %xmm3,%xmm2 - 428246: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 42824b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 428250: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 428255: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 42825a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 42825f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 428264: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 428269: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 42826e: 66 45 0f db c1 pand %xmm9,%xmm8 - 428273: 66 45 0f db d3 pand %xmm11,%xmm10 - 428278: 66 44 0f db c7 pand %xmm7,%xmm8 - 42827d: 66 44 0f db d7 pand %xmm7,%xmm10 - 428282: 66 41 0f eb c8 por %xmm8,%xmm1 - 428287: 66 41 0f eb d2 por %xmm10,%xmm2 - 42828c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 428290: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 428294: 66 0f f8 c8 psubb %xmm0,%xmm1 - 428298: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42829c: 81 ea ff ff 00 00 sub $0xffff,%edx - 4282a2: 0f 85 f8 0a 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 4282a8: 48 83 c1 10 add $0x10,%rcx - 4282ac: 66 0f 6f dc movdqa %xmm4,%xmm3 - 4282b0: e9 db fe ff ff jmpq 428190 <__GI___strcasecmp_l+0x15c0> - 4282b5: 90 nop - 4282b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4282bd: 00 00 00 - 4282c0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 4282c4: 66 0f d7 d0 pmovmskb %xmm0,%edx - 4282c8: f7 c2 00 fc 00 00 test $0xfc00,%edx - 4282ce: 75 10 jne 4282e0 <__GI___strcasecmp_l+0x1710> - 4282d0: 66 0f ef c0 pxor %xmm0,%xmm0 - 4282d4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 4282db: e9 ba fe ff ff jmpq 42819a <__GI___strcasecmp_l+0x15ca> - 4282e0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4282e5: 66 0f 73 d8 0a psrldq $0xa,%xmm0 - 4282ea: 66 0f 73 db 0a psrldq $0xa,%xmm3 - 4282ef: e9 4c 0a 00 00 jmpq 428d40 <__GI___strcasecmp_l+0x2170> - 4282f4: 66 90 xchg %ax,%ax - 4282f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4282fd: 00 00 00 - 428300: 66 0f ef c0 pxor %xmm0,%xmm0 - 428304: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 428308: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42830c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 428310: 66 0f 73 fa 05 pslldq $0x5,%xmm2 - 428315: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 42831a: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 42831f: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 428324: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 428329: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 42832e: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 428333: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 428338: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 42833d: 66 45 0f db c1 pand %xmm9,%xmm8 - 428342: 66 45 0f db d3 pand %xmm11,%xmm10 - 428347: 66 44 0f db c7 pand %xmm7,%xmm8 - 42834c: 66 44 0f db d7 pand %xmm7,%xmm10 - 428351: 66 41 0f eb c8 por %xmm8,%xmm1 - 428356: 66 41 0f eb d2 por %xmm10,%xmm2 - 42835b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42835f: 66 0f f8 d0 psubb %xmm0,%xmm2 - 428363: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 428368: d3 ea shr %cl,%edx - 42836a: 41 d3 e9 shr %cl,%r9d - 42836d: 44 29 ca sub %r9d,%edx - 428370: 0f 85 2f 0a 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> - 428376: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 42837a: 66 0f ef c0 pxor %xmm0,%xmm0 - 42837e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 428385: 41 b9 0b 00 00 00 mov $0xb,%r9d - 42838b: 4c 8d 57 0b lea 0xb(%rdi),%r10 - 42838f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 428396: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42839d: 0f 1f 00 nopl (%rax) - 4283a0: 49 83 c2 10 add $0x10,%r10 - 4283a4: 0f 8f 26 01 00 00 jg 4284d0 <__GI___strcasecmp_l+0x1900> - 4283aa: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4283af: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4283b4: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 4283b8: 66 0f 73 db 0b psrldq $0xb,%xmm3 - 4283bd: 66 0f 73 fa 05 pslldq $0x5,%xmm2 - 4283c2: 66 0f eb d3 por %xmm3,%xmm2 - 4283c6: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 4283cb: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 4283d0: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 4283d5: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 4283da: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 4283df: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 4283e4: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 4283e9: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 4283ee: 66 45 0f db c1 pand %xmm9,%xmm8 - 4283f3: 66 45 0f db d3 pand %xmm11,%xmm10 - 4283f8: 66 44 0f db c7 pand %xmm7,%xmm8 - 4283fd: 66 44 0f db d7 pand %xmm7,%xmm10 - 428402: 66 41 0f eb c8 por %xmm8,%xmm1 - 428407: 66 41 0f eb d2 por %xmm10,%xmm2 - 42840c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 428410: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 428414: 66 0f f8 c8 psubb %xmm0,%xmm1 - 428418: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42841c: 81 ea ff ff 00 00 sub $0xffff,%edx - 428422: 0f 85 78 09 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 428428: 48 83 c1 10 add $0x10,%rcx - 42842c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 428430: 49 83 c2 10 add $0x10,%r10 - 428434: 0f 8f 96 00 00 00 jg 4284d0 <__GI___strcasecmp_l+0x1900> - 42843a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42843f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 428444: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 428448: 66 0f 73 db 0b psrldq $0xb,%xmm3 - 42844d: 66 0f 73 fa 05 pslldq $0x5,%xmm2 - 428452: 66 0f eb d3 por %xmm3,%xmm2 - 428456: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 42845b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 428460: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 428465: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 42846a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 42846f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 428474: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 428479: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 42847e: 66 45 0f db c1 pand %xmm9,%xmm8 - 428483: 66 45 0f db d3 pand %xmm11,%xmm10 - 428488: 66 44 0f db c7 pand %xmm7,%xmm8 - 42848d: 66 44 0f db d7 pand %xmm7,%xmm10 - 428492: 66 41 0f eb c8 por %xmm8,%xmm1 - 428497: 66 41 0f eb d2 por %xmm10,%xmm2 - 42849c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4284a0: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 4284a4: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4284a8: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4284ac: 81 ea ff ff 00 00 sub $0xffff,%edx - 4284b2: 0f 85 e8 08 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 4284b8: 48 83 c1 10 add $0x10,%rcx - 4284bc: 66 0f 6f dc movdqa %xmm4,%xmm3 - 4284c0: e9 db fe ff ff jmpq 4283a0 <__GI___strcasecmp_l+0x17d0> - 4284c5: 90 nop - 4284c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4284cd: 00 00 00 - 4284d0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 4284d4: 66 0f d7 d0 pmovmskb %xmm0,%edx - 4284d8: f7 c2 00 f8 00 00 test $0xf800,%edx - 4284de: 75 10 jne 4284f0 <__GI___strcasecmp_l+0x1920> - 4284e0: 66 0f ef c0 pxor %xmm0,%xmm0 - 4284e4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 4284eb: e9 ba fe ff ff jmpq 4283aa <__GI___strcasecmp_l+0x17da> - 4284f0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4284f5: 66 0f 73 d8 0b psrldq $0xb,%xmm0 - 4284fa: 66 0f 73 db 0b psrldq $0xb,%xmm3 - 4284ff: e9 3c 08 00 00 jmpq 428d40 <__GI___strcasecmp_l+0x2170> - 428504: 66 90 xchg %ax,%ax - 428506: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42850d: 00 00 00 - 428510: 66 0f ef c0 pxor %xmm0,%xmm0 - 428514: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 428518: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42851c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 428520: 66 0f 73 fa 04 pslldq $0x4,%xmm2 - 428525: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 42852a: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 42852f: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 428534: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 428539: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 42853e: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 428543: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 428548: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 42854d: 66 45 0f db c1 pand %xmm9,%xmm8 - 428552: 66 45 0f db d3 pand %xmm11,%xmm10 - 428557: 66 44 0f db c7 pand %xmm7,%xmm8 - 42855c: 66 44 0f db d7 pand %xmm7,%xmm10 - 428561: 66 41 0f eb c8 por %xmm8,%xmm1 - 428566: 66 41 0f eb d2 por %xmm10,%xmm2 - 42856b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42856f: 66 0f f8 d0 psubb %xmm0,%xmm2 - 428573: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 428578: d3 ea shr %cl,%edx - 42857a: 41 d3 e9 shr %cl,%r9d - 42857d: 44 29 ca sub %r9d,%edx - 428580: 0f 85 1f 08 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> - 428586: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 42858a: 66 0f ef c0 pxor %xmm0,%xmm0 - 42858e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 428595: 41 b9 0c 00 00 00 mov $0xc,%r9d - 42859b: 4c 8d 57 0c lea 0xc(%rdi),%r10 - 42859f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 4285a6: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 4285ad: 0f 1f 00 nopl (%rax) - 4285b0: 49 83 c2 10 add $0x10,%r10 - 4285b4: 0f 8f 26 01 00 00 jg 4286e0 <__GI___strcasecmp_l+0x1b10> - 4285ba: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4285bf: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4285c4: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 4285c8: 66 0f 73 db 0c psrldq $0xc,%xmm3 - 4285cd: 66 0f 73 fa 04 pslldq $0x4,%xmm2 - 4285d2: 66 0f eb d3 por %xmm3,%xmm2 - 4285d6: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 4285db: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 4285e0: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 4285e5: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 4285ea: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 4285ef: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 4285f4: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 4285f9: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 4285fe: 66 45 0f db c1 pand %xmm9,%xmm8 - 428603: 66 45 0f db d3 pand %xmm11,%xmm10 - 428608: 66 44 0f db c7 pand %xmm7,%xmm8 - 42860d: 66 44 0f db d7 pand %xmm7,%xmm10 - 428612: 66 41 0f eb c8 por %xmm8,%xmm1 - 428617: 66 41 0f eb d2 por %xmm10,%xmm2 - 42861c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 428620: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 428624: 66 0f f8 c8 psubb %xmm0,%xmm1 - 428628: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42862c: 81 ea ff ff 00 00 sub $0xffff,%edx - 428632: 0f 85 68 07 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 428638: 48 83 c1 10 add $0x10,%rcx - 42863c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 428640: 49 83 c2 10 add $0x10,%r10 - 428644: 0f 8f 96 00 00 00 jg 4286e0 <__GI___strcasecmp_l+0x1b10> - 42864a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42864f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 428654: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 428658: 66 0f 73 db 0c psrldq $0xc,%xmm3 - 42865d: 66 0f 73 fa 04 pslldq $0x4,%xmm2 - 428662: 66 0f eb d3 por %xmm3,%xmm2 - 428666: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 42866b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 428670: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 428675: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 42867a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 42867f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 428684: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 428689: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 42868e: 66 45 0f db c1 pand %xmm9,%xmm8 - 428693: 66 45 0f db d3 pand %xmm11,%xmm10 - 428698: 66 44 0f db c7 pand %xmm7,%xmm8 - 42869d: 66 44 0f db d7 pand %xmm7,%xmm10 - 4286a2: 66 41 0f eb c8 por %xmm8,%xmm1 - 4286a7: 66 41 0f eb d2 por %xmm10,%xmm2 - 4286ac: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4286b0: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 4286b4: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4286b8: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4286bc: 81 ea ff ff 00 00 sub $0xffff,%edx - 4286c2: 0f 85 d8 06 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 4286c8: 48 83 c1 10 add $0x10,%rcx - 4286cc: 66 0f 6f dc movdqa %xmm4,%xmm3 - 4286d0: e9 db fe ff ff jmpq 4285b0 <__GI___strcasecmp_l+0x19e0> - 4286d5: 90 nop - 4286d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4286dd: 00 00 00 - 4286e0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 4286e4: 66 0f d7 d0 pmovmskb %xmm0,%edx - 4286e8: f7 c2 00 f0 00 00 test $0xf000,%edx - 4286ee: 75 10 jne 428700 <__GI___strcasecmp_l+0x1b30> - 4286f0: 66 0f ef c0 pxor %xmm0,%xmm0 - 4286f4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 4286fb: e9 ba fe ff ff jmpq 4285ba <__GI___strcasecmp_l+0x19ea> - 428700: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 428705: 66 0f 73 d8 0c psrldq $0xc,%xmm0 - 42870a: 66 0f 73 db 0c psrldq $0xc,%xmm3 - 42870f: e9 2c 06 00 00 jmpq 428d40 <__GI___strcasecmp_l+0x2170> - 428714: 66 90 xchg %ax,%ax - 428716: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42871d: 00 00 00 - 428720: 66 0f ef c0 pxor %xmm0,%xmm0 - 428724: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 428728: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42872c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 428730: 66 0f 73 fa 03 pslldq $0x3,%xmm2 - 428735: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 42873a: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 42873f: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 428744: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 428749: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 42874e: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 428753: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 428758: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 42875d: 66 45 0f db c1 pand %xmm9,%xmm8 - 428762: 66 45 0f db d3 pand %xmm11,%xmm10 - 428767: 66 44 0f db c7 pand %xmm7,%xmm8 - 42876c: 66 44 0f db d7 pand %xmm7,%xmm10 - 428771: 66 41 0f eb c8 por %xmm8,%xmm1 - 428776: 66 41 0f eb d2 por %xmm10,%xmm2 - 42877b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42877f: 66 0f f8 d0 psubb %xmm0,%xmm2 - 428783: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 428788: d3 ea shr %cl,%edx - 42878a: 41 d3 e9 shr %cl,%r9d - 42878d: 44 29 ca sub %r9d,%edx - 428790: 0f 85 0f 06 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> - 428796: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 42879a: 66 0f ef c0 pxor %xmm0,%xmm0 - 42879e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 4287a5: 41 b9 0d 00 00 00 mov $0xd,%r9d - 4287ab: 4c 8d 57 0d lea 0xd(%rdi),%r10 - 4287af: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 4287b6: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 4287bd: 0f 1f 00 nopl (%rax) - 4287c0: 49 83 c2 10 add $0x10,%r10 - 4287c4: 0f 8f 26 01 00 00 jg 4288f0 <__GI___strcasecmp_l+0x1d20> - 4287ca: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4287cf: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4287d4: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 4287d8: 66 0f 73 db 0d psrldq $0xd,%xmm3 - 4287dd: 66 0f 73 fa 03 pslldq $0x3,%xmm2 - 4287e2: 66 0f eb d3 por %xmm3,%xmm2 - 4287e6: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 4287eb: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 4287f0: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 4287f5: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 4287fa: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 4287ff: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 428804: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 428809: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 42880e: 66 45 0f db c1 pand %xmm9,%xmm8 - 428813: 66 45 0f db d3 pand %xmm11,%xmm10 - 428818: 66 44 0f db c7 pand %xmm7,%xmm8 - 42881d: 66 44 0f db d7 pand %xmm7,%xmm10 - 428822: 66 41 0f eb c8 por %xmm8,%xmm1 - 428827: 66 41 0f eb d2 por %xmm10,%xmm2 - 42882c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 428830: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 428834: 66 0f f8 c8 psubb %xmm0,%xmm1 - 428838: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42883c: 81 ea ff ff 00 00 sub $0xffff,%edx - 428842: 0f 85 58 05 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 428848: 48 83 c1 10 add $0x10,%rcx - 42884c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 428850: 49 83 c2 10 add $0x10,%r10 - 428854: 0f 8f 96 00 00 00 jg 4288f0 <__GI___strcasecmp_l+0x1d20> - 42885a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42885f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 428864: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 428868: 66 0f 73 db 0d psrldq $0xd,%xmm3 - 42886d: 66 0f 73 fa 03 pslldq $0x3,%xmm2 - 428872: 66 0f eb d3 por %xmm3,%xmm2 - 428876: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 42887b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 428880: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 428885: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 42888a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 42888f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 428894: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 428899: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 42889e: 66 45 0f db c1 pand %xmm9,%xmm8 - 4288a3: 66 45 0f db d3 pand %xmm11,%xmm10 - 4288a8: 66 44 0f db c7 pand %xmm7,%xmm8 - 4288ad: 66 44 0f db d7 pand %xmm7,%xmm10 - 4288b2: 66 41 0f eb c8 por %xmm8,%xmm1 - 4288b7: 66 41 0f eb d2 por %xmm10,%xmm2 - 4288bc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4288c0: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 4288c4: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4288c8: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4288cc: 81 ea ff ff 00 00 sub $0xffff,%edx - 4288d2: 0f 85 c8 04 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 4288d8: 48 83 c1 10 add $0x10,%rcx - 4288dc: 66 0f 6f dc movdqa %xmm4,%xmm3 - 4288e0: e9 db fe ff ff jmpq 4287c0 <__GI___strcasecmp_l+0x1bf0> - 4288e5: 90 nop - 4288e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4288ed: 00 00 00 - 4288f0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 4288f4: 66 0f d7 d0 pmovmskb %xmm0,%edx - 4288f8: f7 c2 00 e0 00 00 test $0xe000,%edx - 4288fe: 75 10 jne 428910 <__GI___strcasecmp_l+0x1d40> - 428900: 66 0f ef c0 pxor %xmm0,%xmm0 - 428904: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42890b: e9 ba fe ff ff jmpq 4287ca <__GI___strcasecmp_l+0x1bfa> - 428910: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 428915: 66 0f 73 d8 0d psrldq $0xd,%xmm0 - 42891a: 66 0f 73 db 0d psrldq $0xd,%xmm3 - 42891f: e9 1c 04 00 00 jmpq 428d40 <__GI___strcasecmp_l+0x2170> - 428924: 66 90 xchg %ax,%ax - 428926: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42892d: 00 00 00 - 428930: 66 0f ef c0 pxor %xmm0,%xmm0 - 428934: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 428938: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42893c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 428940: 66 0f 73 fa 02 pslldq $0x2,%xmm2 - 428945: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 42894a: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 42894f: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 428954: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 428959: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 42895e: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 428963: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 428968: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 42896d: 66 45 0f db c1 pand %xmm9,%xmm8 - 428972: 66 45 0f db d3 pand %xmm11,%xmm10 - 428977: 66 44 0f db c7 pand %xmm7,%xmm8 - 42897c: 66 44 0f db d7 pand %xmm7,%xmm10 - 428981: 66 41 0f eb c8 por %xmm8,%xmm1 - 428986: 66 41 0f eb d2 por %xmm10,%xmm2 - 42898b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42898f: 66 0f f8 d0 psubb %xmm0,%xmm2 - 428993: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 428998: d3 ea shr %cl,%edx - 42899a: 41 d3 e9 shr %cl,%r9d - 42899d: 44 29 ca sub %r9d,%edx - 4289a0: 0f 85 ff 03 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> - 4289a6: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 4289aa: 66 0f ef c0 pxor %xmm0,%xmm0 - 4289ae: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 4289b5: 41 b9 0e 00 00 00 mov $0xe,%r9d - 4289bb: 4c 8d 57 0e lea 0xe(%rdi),%r10 - 4289bf: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 4289c6: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 4289cd: 0f 1f 00 nopl (%rax) - 4289d0: 49 83 c2 10 add $0x10,%r10 - 4289d4: 0f 8f 26 01 00 00 jg 428b00 <__GI___strcasecmp_l+0x1f30> - 4289da: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4289df: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4289e4: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 4289e8: 66 0f 73 db 0e psrldq $0xe,%xmm3 - 4289ed: 66 0f 73 fa 02 pslldq $0x2,%xmm2 - 4289f2: 66 0f eb d3 por %xmm3,%xmm2 - 4289f6: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 4289fb: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 428a00: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 428a05: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 428a0a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 428a0f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 428a14: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 428a19: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 428a1e: 66 45 0f db c1 pand %xmm9,%xmm8 - 428a23: 66 45 0f db d3 pand %xmm11,%xmm10 - 428a28: 66 44 0f db c7 pand %xmm7,%xmm8 - 428a2d: 66 44 0f db d7 pand %xmm7,%xmm10 - 428a32: 66 41 0f eb c8 por %xmm8,%xmm1 - 428a37: 66 41 0f eb d2 por %xmm10,%xmm2 - 428a3c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 428a40: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 428a44: 66 0f f8 c8 psubb %xmm0,%xmm1 - 428a48: 66 0f d7 d1 pmovmskb %xmm1,%edx - 428a4c: 81 ea ff ff 00 00 sub $0xffff,%edx - 428a52: 0f 85 48 03 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 428a58: 48 83 c1 10 add $0x10,%rcx - 428a5c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 428a60: 49 83 c2 10 add $0x10,%r10 - 428a64: 0f 8f 96 00 00 00 jg 428b00 <__GI___strcasecmp_l+0x1f30> - 428a6a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 428a6f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 428a74: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 428a78: 66 0f 73 db 0e psrldq $0xe,%xmm3 - 428a7d: 66 0f 73 fa 02 pslldq $0x2,%xmm2 - 428a82: 66 0f eb d3 por %xmm3,%xmm2 - 428a86: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 428a8b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 428a90: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 428a95: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 428a9a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 428a9f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 428aa4: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 428aa9: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 428aae: 66 45 0f db c1 pand %xmm9,%xmm8 - 428ab3: 66 45 0f db d3 pand %xmm11,%xmm10 - 428ab8: 66 44 0f db c7 pand %xmm7,%xmm8 - 428abd: 66 44 0f db d7 pand %xmm7,%xmm10 - 428ac2: 66 41 0f eb c8 por %xmm8,%xmm1 - 428ac7: 66 41 0f eb d2 por %xmm10,%xmm2 - 428acc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 428ad0: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 428ad4: 66 0f f8 c8 psubb %xmm0,%xmm1 - 428ad8: 66 0f d7 d1 pmovmskb %xmm1,%edx - 428adc: 81 ea ff ff 00 00 sub $0xffff,%edx - 428ae2: 0f 85 b8 02 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 428ae8: 48 83 c1 10 add $0x10,%rcx - 428aec: 66 0f 6f dc movdqa %xmm4,%xmm3 - 428af0: e9 db fe ff ff jmpq 4289d0 <__GI___strcasecmp_l+0x1e00> - 428af5: 90 nop - 428af6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 428afd: 00 00 00 - 428b00: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 428b04: 66 0f d7 d0 pmovmskb %xmm0,%edx - 428b08: f7 c2 00 c0 00 00 test $0xc000,%edx - 428b0e: 75 10 jne 428b20 <__GI___strcasecmp_l+0x1f50> - 428b10: 66 0f ef c0 pxor %xmm0,%xmm0 - 428b14: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 428b1b: e9 ba fe ff ff jmpq 4289da <__GI___strcasecmp_l+0x1e0a> - 428b20: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 428b25: 66 0f 73 d8 0e psrldq $0xe,%xmm0 - 428b2a: 66 0f 73 db 0e psrldq $0xe,%xmm3 - 428b2f: e9 0c 02 00 00 jmpq 428d40 <__GI___strcasecmp_l+0x2170> - 428b34: 66 90 xchg %ax,%ax - 428b36: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 428b3d: 00 00 00 - 428b40: 66 0f ef c0 pxor %xmm0,%xmm0 - 428b44: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 428b48: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 428b4c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 428b50: 66 0f 73 fa 01 pslldq $0x1,%xmm2 - 428b55: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 428b5a: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 428b5f: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 428b64: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 428b69: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 428b6e: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 428b73: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 428b78: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 428b7d: 66 45 0f db c1 pand %xmm9,%xmm8 - 428b82: 66 45 0f db d3 pand %xmm11,%xmm10 - 428b87: 66 44 0f db c7 pand %xmm7,%xmm8 - 428b8c: 66 44 0f db d7 pand %xmm7,%xmm10 - 428b91: 66 41 0f eb c8 por %xmm8,%xmm1 - 428b96: 66 41 0f eb d2 por %xmm10,%xmm2 - 428b9b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 428b9f: 66 0f f8 d0 psubb %xmm0,%xmm2 - 428ba3: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 428ba8: d3 ea shr %cl,%edx - 428baa: 41 d3 e9 shr %cl,%r9d - 428bad: 44 29 ca sub %r9d,%edx - 428bb0: 0f 85 ef 01 00 00 jne 428da5 <__GI___strcasecmp_l+0x21d5> - 428bb6: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 428bba: 66 0f ef c0 pxor %xmm0,%xmm0 - 428bbe: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 428bc5: 41 b9 0f 00 00 00 mov $0xf,%r9d - 428bcb: 4c 8d 57 0f lea 0xf(%rdi),%r10 - 428bcf: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 428bd6: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 428bdd: 0f 1f 00 nopl (%rax) - 428be0: 49 83 c2 10 add $0x10,%r10 - 428be4: 0f 8f 26 01 00 00 jg 428d10 <__GI___strcasecmp_l+0x2140> - 428bea: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 428bef: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 428bf4: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 428bf8: 66 0f 73 db 0f psrldq $0xf,%xmm3 - 428bfd: 66 0f 73 fa 01 pslldq $0x1,%xmm2 - 428c02: 66 0f eb d3 por %xmm3,%xmm2 - 428c06: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 428c0b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 428c10: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 428c15: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 428c1a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 428c1f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 428c24: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 428c29: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 428c2e: 66 45 0f db c1 pand %xmm9,%xmm8 - 428c33: 66 45 0f db d3 pand %xmm11,%xmm10 - 428c38: 66 44 0f db c7 pand %xmm7,%xmm8 - 428c3d: 66 44 0f db d7 pand %xmm7,%xmm10 - 428c42: 66 41 0f eb c8 por %xmm8,%xmm1 - 428c47: 66 41 0f eb d2 por %xmm10,%xmm2 - 428c4c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 428c50: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 428c54: 66 0f f8 c8 psubb %xmm0,%xmm1 - 428c58: 66 0f d7 d1 pmovmskb %xmm1,%edx - 428c5c: 81 ea ff ff 00 00 sub $0xffff,%edx - 428c62: 0f 85 38 01 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 428c68: 48 83 c1 10 add $0x10,%rcx - 428c6c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 428c70: 49 83 c2 10 add $0x10,%r10 - 428c74: 0f 8f 96 00 00 00 jg 428d10 <__GI___strcasecmp_l+0x2140> - 428c7a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 428c7f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 428c84: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 428c88: 66 0f 73 db 0f psrldq $0xf,%xmm3 - 428c8d: 66 0f 73 fa 01 pslldq $0x1,%xmm2 - 428c92: 66 0f eb d3 por %xmm3,%xmm2 - 428c96: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 428c9b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 428ca0: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 428ca5: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 428caa: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 428caf: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 428cb4: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 428cb9: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 428cbe: 66 45 0f db c1 pand %xmm9,%xmm8 - 428cc3: 66 45 0f db d3 pand %xmm11,%xmm10 - 428cc8: 66 44 0f db c7 pand %xmm7,%xmm8 - 428ccd: 66 44 0f db d7 pand %xmm7,%xmm10 - 428cd2: 66 41 0f eb c8 por %xmm8,%xmm1 - 428cd7: 66 41 0f eb d2 por %xmm10,%xmm2 - 428cdc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 428ce0: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 428ce4: 66 0f f8 c8 psubb %xmm0,%xmm1 - 428ce8: 66 0f d7 d1 pmovmskb %xmm1,%edx - 428cec: 81 ea ff ff 00 00 sub $0xffff,%edx - 428cf2: 0f 85 a8 00 00 00 jne 428da0 <__GI___strcasecmp_l+0x21d0> - 428cf8: 48 83 c1 10 add $0x10,%rcx - 428cfc: 66 0f 6f dc movdqa %xmm4,%xmm3 - 428d00: e9 db fe ff ff jmpq 428be0 <__GI___strcasecmp_l+0x2010> - 428d05: 90 nop - 428d06: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 428d0d: 00 00 00 - 428d10: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 428d14: 66 0f d7 d0 pmovmskb %xmm0,%edx - 428d18: f7 c2 00 80 00 00 test $0x8000,%edx - 428d1e: 75 10 jne 428d30 <__GI___strcasecmp_l+0x2160> - 428d20: 66 0f ef c0 pxor %xmm0,%xmm0 - 428d24: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 428d2b: e9 ba fe ff ff jmpq 428bea <__GI___strcasecmp_l+0x201a> - 428d30: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 428d35: 66 0f 73 db 0f psrldq $0xf,%xmm3 - 428d3a: 66 0f 73 d8 0f psrldq $0xf,%xmm0 - 428d3f: 90 nop - 428d40: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 428d45: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 428d4a: 66 44 0f 6f d3 movdqa %xmm3,%xmm10 - 428d4f: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 428d54: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 428d59: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 428d5e: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 428d63: 66 44 0f 64 db pcmpgtb %xmm3,%xmm11 - 428d68: 66 45 0f db c1 pand %xmm9,%xmm8 - 428d6d: 66 45 0f db d3 pand %xmm11,%xmm10 - 428d72: 66 44 0f db c7 pand %xmm7,%xmm8 - 428d77: 66 44 0f db d7 pand %xmm7,%xmm10 - 428d7c: 66 41 0f eb c8 por %xmm8,%xmm1 - 428d81: 66 41 0f eb da por %xmm10,%xmm3 - 428d86: 66 0f 74 cb pcmpeqb %xmm3,%xmm1 - 428d8a: 66 0f f8 c8 psubb %xmm0,%xmm1 - 428d8e: 66 0f d7 d1 pmovmskb %xmm1,%edx - 428d92: f7 d2 not %edx - 428d94: 66 90 xchg %ax,%ax - 428d96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 428d9d: 00 00 00 - 428da0: 49 8d 44 09 f0 lea -0x10(%r9,%rcx,1),%rax - 428da5: 48 8d 3c 07 lea (%rdi,%rax,1),%rdi - 428da9: 48 8d 34 0e lea (%rsi,%rcx,1),%rsi - 428dad: 45 85 c0 test %r8d,%r8d - 428db0: 74 0e je 428dc0 <__GI___strcasecmp_l+0x21f0> - 428db2: 48 87 f7 xchg %rsi,%rdi - 428db5: 90 nop - 428db6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 428dbd: 00 00 00 - 428dc0: 48 0f bc d2 bsf %rdx,%rdx - 428dc4: 0f b6 0c 16 movzbl (%rsi,%rdx,1),%ecx - 428dc8: 0f b6 04 17 movzbl (%rdi,%rdx,1),%eax - 428dcc: 48 8d 15 6d e7 07 00 lea 0x7e76d(%rip),%rdx # 4a7540 <_nl_C_LC_CTYPE_tolower+0x200> - 428dd3: 8b 0c 8a mov (%rdx,%rcx,4),%ecx - 428dd6: 8b 04 82 mov (%rdx,%rax,4),%eax - 428dd9: 29 c8 sub %ecx,%eax - 428ddb: c3 retq - 428ddc: 31 c0 xor %eax,%eax - 428dde: c3 retq - 428ddf: 90 nop - 428de0: 0f b6 0e movzbl (%rsi),%ecx - 428de3: 0f b6 07 movzbl (%rdi),%eax - 428de6: 48 8d 15 53 e7 07 00 lea 0x7e753(%rip),%rdx # 4a7540 <_nl_C_LC_CTYPE_tolower+0x200> - 428ded: 8b 0c 8a mov (%rdx,%rcx,4),%ecx - 428df0: 8b 04 82 mov (%rdx,%rax,4),%eax - 428df3: 29 c8 sub %ecx,%eax - 428df5: c3 retq - 428df6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 428dfd: 00 00 00 - -0000000000428e00 <__strcasecmp_sse42>: - 428e00: 48 c7 c0 b8 ff ff ff mov $0xffffffffffffffb8,%rax - 428e07: 64 48 8b 10 mov %fs:(%rax),%rdx - 428e0b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - -0000000000428e10 <__strcasecmp_l_sse42>: - 428e10: 48 8b 02 mov (%rdx),%rax - 428e13: f7 80 78 02 00 00 01 testl $0x1,0x278(%rax) - 428e1a: 00 00 00 - 428e1d: 0f 85 dd 54 01 00 jne 43e300 <__strcasecmp_l_nonascii> - 428e23: 89 f1 mov %esi,%ecx - 428e25: 89 f8 mov %edi,%eax - 428e27: 48 83 e1 3f and $0x3f,%rcx - 428e2b: 48 83 e0 3f and $0x3f,%rax - 428e2f: 66 0f 6f 25 79 a2 07 movdqa 0x7a279(%rip),%xmm4 # 4a30b0 <__func__.10972+0xf0> - 428e36: 00 - 428e37: 66 0f 6f 2d 81 a2 07 movdqa 0x7a281(%rip),%xmm5 # 4a30c0 <__func__.10972+0x100> - 428e3e: 00 - 428e3f: 66 0f 6f 35 89 a2 07 movdqa 0x7a289(%rip),%xmm6 # 4a30d0 - 428e46: 00 - 428e47: 83 f9 30 cmp $0x30,%ecx - 428e4a: 0f 87 80 00 00 00 ja 428ed0 <__strcasecmp_l_sse42+0xc0> - 428e50: 83 f8 30 cmp $0x30,%eax - 428e53: 77 7b ja 428ed0 <__strcasecmp_l_sse42+0xc0> - 428e55: f3 0f 6f 0f movdqu (%rdi),%xmm1 - 428e59: f3 0f 6f 16 movdqu (%rsi),%xmm2 - 428e5d: 66 0f 6f f9 movdqa %xmm1,%xmm7 - 428e61: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 428e66: 66 44 0f 6f ca movdqa %xmm2,%xmm9 - 428e6b: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 428e70: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 428e74: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 - 428e79: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 428e7e: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 - 428e83: 66 41 0f db f8 pand %xmm8,%xmm7 - 428e88: 66 45 0f db ca pand %xmm10,%xmm9 - 428e8d: 66 0f db fe pand %xmm6,%xmm7 - 428e91: 66 44 0f db ce pand %xmm6,%xmm9 - 428e96: 66 0f eb cf por %xmm7,%xmm1 - 428e9a: 66 41 0f eb d1 por %xmm9,%xmm2 - 428e9f: 66 0f ef c0 pxor %xmm0,%xmm0 - 428ea3: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 428ea7: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 428eab: 66 0f f8 c8 psubb %xmm0,%xmm1 - 428eaf: 66 0f d7 d1 pmovmskb %xmm1,%edx - 428eb3: 81 ea ff ff 00 00 sub $0xffff,%edx - 428eb9: 0f 85 b1 1a 00 00 jne 42a970 <__strcasecmp_l_sse42+0x1b60> - 428ebf: 48 83 c6 10 add $0x10,%rsi - 428ec3: 48 83 c7 10 add $0x10,%rdi - 428ec7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 428ece: 00 00 - 428ed0: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi - 428ed4: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi - 428ed8: ba ff ff 00 00 mov $0xffff,%edx - 428edd: 45 31 c0 xor %r8d,%r8d - 428ee0: 83 e1 0f and $0xf,%ecx - 428ee3: 83 e0 0f and $0xf,%eax - 428ee6: 66 0f ef c0 pxor %xmm0,%xmm0 - 428eea: 39 c1 cmp %eax,%ecx - 428eec: 74 32 je 428f20 <__strcasecmp_l_sse42+0x110> - 428eee: 77 07 ja 428ef7 <__strcasecmp_l_sse42+0xe7> - 428ef0: 41 89 d0 mov %edx,%r8d - 428ef3: 91 xchg %eax,%ecx - 428ef4: 48 87 f7 xchg %rsi,%rdi - 428ef7: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 428efb: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 428eff: 4c 8d 48 0f lea 0xf(%rax),%r9 - 428f03: 49 29 c9 sub %rcx,%r9 - 428f06: 4c 8d 15 e3 a1 07 00 lea 0x7a1e3(%rip),%r10 # 4a30f0 - 428f0d: 4f 63 0c 8a movslq (%r10,%r9,4),%r9 - 428f11: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 428f15: 4f 8d 14 0a lea (%r10,%r9,1),%r10 - 428f19: 41 ff e2 jmpq *%r10 - 428f1c: 0f 1f 40 00 nopl 0x0(%rax) - 428f20: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 428f24: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 428f28: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 428f2c: 66 0f 6f f9 movdqa %xmm1,%xmm7 - 428f30: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 428f35: 66 44 0f 6f ca movdqa %xmm2,%xmm9 - 428f3a: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 428f3f: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 428f43: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 - 428f48: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 428f4d: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 - 428f52: 66 41 0f db f8 pand %xmm8,%xmm7 - 428f57: 66 45 0f db ca pand %xmm10,%xmm9 - 428f5c: 66 0f db fe pand %xmm6,%xmm7 - 428f60: 66 44 0f db ce pand %xmm6,%xmm9 - 428f65: 66 0f eb cf por %xmm7,%xmm1 - 428f69: 66 41 0f eb d1 por %xmm9,%xmm2 - 428f6e: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 428f72: 66 0f f8 c8 psubb %xmm0,%xmm1 - 428f76: 66 44 0f d7 c9 pmovmskb %xmm1,%r9d - 428f7b: d3 ea shr %cl,%edx - 428f7d: 41 d3 e9 shr %cl,%r9d - 428f80: 44 29 ca sub %r9d,%edx - 428f83: 0f 85 cf 19 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> - 428f89: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 428f90: 49 c7 c1 10 00 00 00 mov $0x10,%r9 - 428f97: 48 89 ca mov %rcx,%rdx - 428f9a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 428fa0: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 428fa5: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 428faa: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 428fae: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 428fb3: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 428fb8: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 428fbd: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 428fc1: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 428fc6: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 428fcb: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 428fd0: 66 41 0f db f8 pand %xmm8,%xmm7 - 428fd5: 66 45 0f db ca pand %xmm10,%xmm9 - 428fda: 66 0f db fe pand %xmm6,%xmm7 - 428fde: 66 44 0f db ce pand %xmm6,%xmm9 - 428fe3: 66 0f eb c7 por %xmm7,%xmm0 - 428fe7: 66 41 0f eb c9 por %xmm9,%xmm1 - 428fec: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 428ff2: 48 8d 52 10 lea 0x10(%rdx),%rdx - 428ff6: 76 68 jbe 429060 <__strcasecmp_l_sse42+0x250> - 428ff8: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 428ffd: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 429002: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 429006: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 42900b: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 429010: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 429015: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 429019: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 42901e: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 429023: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 429028: 66 41 0f db f8 pand %xmm8,%xmm7 - 42902d: 66 45 0f db ca pand %xmm10,%xmm9 - 429032: 66 0f db fe pand %xmm6,%xmm7 - 429036: 66 44 0f db ce pand %xmm6,%xmm9 - 42903b: 66 0f eb c7 por %xmm7,%xmm0 - 42903f: 66 41 0f eb c9 por %xmm9,%xmm1 - 429044: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 42904a: 48 8d 52 10 lea 0x10(%rdx),%rdx - 42904e: 76 10 jbe 429060 <__strcasecmp_l_sse42+0x250> - 429050: e9 4b ff ff ff jmpq 428fa0 <__strcasecmp_l_sse42+0x190> - 429055: 90 nop - 429056: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42905d: 00 00 00 - 429060: 0f 83 26 19 00 00 jae 42a98c <__strcasecmp_l_sse42+0x1b7c> - 429066: 48 8d 4c 0a f0 lea -0x10(%rdx,%rcx,1),%rcx - 42906b: 0f b6 04 0f movzbl (%rdi,%rcx,1),%eax - 42906f: 0f b6 14 0e movzbl (%rsi,%rcx,1),%edx - 429073: 48 8d 0d c6 e4 07 00 lea 0x7e4c6(%rip),%rcx # 4a7540 <_nl_C_LC_CTYPE_tolower+0x200> - 42907a: 8b 04 81 mov (%rcx,%rax,4),%eax - 42907d: 8b 14 91 mov (%rcx,%rdx,4),%edx - 429080: 29 d0 sub %edx,%eax - 429082: c3 retq - 429083: 0f 1f 00 nopl (%rax) - 429086: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42908d: 00 00 00 - 429090: 66 0f 73 fa 0f pslldq $0xf,%xmm2 - 429095: 66 0f 6f f9 movdqa %xmm1,%xmm7 - 429099: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 42909e: 66 44 0f 6f ca movdqa %xmm2,%xmm9 - 4290a3: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 4290a8: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 4290ac: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 - 4290b1: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 4290b6: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 - 4290bb: 66 41 0f db f8 pand %xmm8,%xmm7 - 4290c0: 66 45 0f db ca pand %xmm10,%xmm9 - 4290c5: 66 0f db fe pand %xmm6,%xmm7 - 4290c9: 66 44 0f db ce pand %xmm6,%xmm9 - 4290ce: 66 0f eb cf por %xmm7,%xmm1 - 4290d2: 66 41 0f eb d1 por %xmm9,%xmm2 - 4290d7: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 4290db: 66 0f f8 d0 psubb %xmm0,%xmm2 - 4290df: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 4290e4: d3 ea shr %cl,%edx - 4290e6: 41 d3 e9 shr %cl,%r9d - 4290e9: 44 29 ca sub %r9d,%edx - 4290ec: 0f 85 66 18 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> - 4290f2: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 4290f6: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 4290fd: 41 b9 01 00 00 00 mov $0x1,%r9d - 429103: 4c 8d 57 01 lea 0x1(%rdi),%r10 - 429107: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42910e: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 429115: 48 89 ca mov %rcx,%rdx - 429118: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 42911f: 00 - 429120: 49 83 c2 10 add $0x10,%r10 - 429124: 0f 8f d6 00 00 00 jg 429200 <__strcasecmp_l_sse42+0x3f0> - 42912a: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 42912f: 66 0f 3a 0f 44 17 f0 palignr $0x1,-0x10(%rdi,%rdx,1),%xmm0 - 429136: 01 - 429137: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 42913c: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 429140: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 429145: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 42914a: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 42914f: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 429153: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 429158: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 42915d: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 429162: 66 41 0f db f8 pand %xmm8,%xmm7 - 429167: 66 45 0f db ca pand %xmm10,%xmm9 - 42916c: 66 0f db fe pand %xmm6,%xmm7 - 429170: 66 44 0f db ce pand %xmm6,%xmm9 - 429175: 66 0f eb c7 por %xmm7,%xmm0 - 429179: 66 41 0f eb c9 por %xmm9,%xmm1 - 42917e: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 429184: 0f 86 a6 17 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> - 42918a: 48 83 c2 10 add $0x10,%rdx - 42918e: 49 83 c2 10 add $0x10,%r10 - 429192: 7f 6c jg 429200 <__strcasecmp_l_sse42+0x3f0> - 429194: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 429199: 66 0f 3a 0f 44 17 f0 palignr $0x1,-0x10(%rdi,%rdx,1),%xmm0 - 4291a0: 01 - 4291a1: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 4291a6: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 4291aa: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 4291af: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 4291b4: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 4291b9: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 4291bd: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 4291c2: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 4291c7: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 4291cc: 66 41 0f db f8 pand %xmm8,%xmm7 - 4291d1: 66 45 0f db ca pand %xmm10,%xmm9 - 4291d6: 66 0f db fe pand %xmm6,%xmm7 - 4291da: 66 44 0f db ce pand %xmm6,%xmm9 - 4291df: 66 0f eb c7 por %xmm7,%xmm0 - 4291e3: 66 41 0f eb c9 por %xmm9,%xmm1 - 4291e8: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 4291ee: 0f 86 3c 17 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> - 4291f4: 48 83 c2 10 add $0x10,%rdx - 4291f8: e9 23 ff ff ff jmpq 429120 <__strcasecmp_l_sse42+0x310> - 4291fd: 0f 1f 00 nopl (%rax) - 429200: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 429207: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 - 42920d: 66 0f 73 d8 01 psrldq $0x1,%xmm0 - 429212: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 - 429218: 83 f9 0e cmp $0xe,%ecx - 42921b: 0f 87 09 ff ff ff ja 42912a <__strcasecmp_l_sse42+0x31a> - 429221: e9 bb 16 00 00 jmpq 42a8e1 <__strcasecmp_l_sse42+0x1ad1> - 429226: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42922d: 00 00 00 - 429230: 66 0f 73 fa 0e pslldq $0xe,%xmm2 - 429235: 66 0f 6f f9 movdqa %xmm1,%xmm7 - 429239: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 42923e: 66 44 0f 6f ca movdqa %xmm2,%xmm9 - 429243: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 429248: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 42924c: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 - 429251: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 429256: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 - 42925b: 66 41 0f db f8 pand %xmm8,%xmm7 - 429260: 66 45 0f db ca pand %xmm10,%xmm9 - 429265: 66 0f db fe pand %xmm6,%xmm7 - 429269: 66 44 0f db ce pand %xmm6,%xmm9 - 42926e: 66 0f eb cf por %xmm7,%xmm1 - 429272: 66 41 0f eb d1 por %xmm9,%xmm2 - 429277: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42927b: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42927f: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 429284: d3 ea shr %cl,%edx - 429286: 41 d3 e9 shr %cl,%r9d - 429289: 44 29 ca sub %r9d,%edx - 42928c: 0f 85 c6 16 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> - 429292: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 429296: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42929d: 41 b9 02 00 00 00 mov $0x2,%r9d - 4292a3: 4c 8d 57 02 lea 0x2(%rdi),%r10 - 4292a7: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 4292ae: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 4292b5: 48 89 ca mov %rcx,%rdx - 4292b8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 4292bf: 00 - 4292c0: 49 83 c2 10 add $0x10,%r10 - 4292c4: 0f 8f d6 00 00 00 jg 4293a0 <__strcasecmp_l_sse42+0x590> - 4292ca: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 4292cf: 66 0f 3a 0f 44 17 f0 palignr $0x2,-0x10(%rdi,%rdx,1),%xmm0 - 4292d6: 02 - 4292d7: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 4292dc: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 4292e0: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 4292e5: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 4292ea: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 4292ef: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 4292f3: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 4292f8: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 4292fd: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 429302: 66 41 0f db f8 pand %xmm8,%xmm7 - 429307: 66 45 0f db ca pand %xmm10,%xmm9 - 42930c: 66 0f db fe pand %xmm6,%xmm7 - 429310: 66 44 0f db ce pand %xmm6,%xmm9 - 429315: 66 0f eb c7 por %xmm7,%xmm0 - 429319: 66 41 0f eb c9 por %xmm9,%xmm1 - 42931e: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 429324: 0f 86 06 16 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> - 42932a: 48 83 c2 10 add $0x10,%rdx - 42932e: 49 83 c2 10 add $0x10,%r10 - 429332: 7f 6c jg 4293a0 <__strcasecmp_l_sse42+0x590> - 429334: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 429339: 66 0f 3a 0f 44 17 f0 palignr $0x2,-0x10(%rdi,%rdx,1),%xmm0 - 429340: 02 - 429341: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 429346: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 42934a: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 42934f: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 429354: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 429359: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 42935d: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 429362: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 429367: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 42936c: 66 41 0f db f8 pand %xmm8,%xmm7 - 429371: 66 45 0f db ca pand %xmm10,%xmm9 - 429376: 66 0f db fe pand %xmm6,%xmm7 - 42937a: 66 44 0f db ce pand %xmm6,%xmm9 - 42937f: 66 0f eb c7 por %xmm7,%xmm0 - 429383: 66 41 0f eb c9 por %xmm9,%xmm1 - 429388: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 42938e: 0f 86 9c 15 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> - 429394: 48 83 c2 10 add $0x10,%rdx - 429398: e9 23 ff ff ff jmpq 4292c0 <__strcasecmp_l_sse42+0x4b0> - 42939d: 0f 1f 00 nopl (%rax) - 4293a0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 4293a7: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 - 4293ad: 66 0f 73 d8 02 psrldq $0x2,%xmm0 - 4293b2: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 - 4293b8: 83 f9 0d cmp $0xd,%ecx - 4293bb: 0f 87 09 ff ff ff ja 4292ca <__strcasecmp_l_sse42+0x4ba> - 4293c1: e9 1b 15 00 00 jmpq 42a8e1 <__strcasecmp_l_sse42+0x1ad1> - 4293c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4293cd: 00 00 00 - 4293d0: 66 0f 73 fa 0d pslldq $0xd,%xmm2 - 4293d5: 66 0f 6f f9 movdqa %xmm1,%xmm7 - 4293d9: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 4293de: 66 44 0f 6f ca movdqa %xmm2,%xmm9 - 4293e3: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 4293e8: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 4293ec: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 - 4293f1: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 4293f6: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 - 4293fb: 66 41 0f db f8 pand %xmm8,%xmm7 - 429400: 66 45 0f db ca pand %xmm10,%xmm9 - 429405: 66 0f db fe pand %xmm6,%xmm7 - 429409: 66 44 0f db ce pand %xmm6,%xmm9 - 42940e: 66 0f eb cf por %xmm7,%xmm1 - 429412: 66 41 0f eb d1 por %xmm9,%xmm2 - 429417: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42941b: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42941f: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 429424: d3 ea shr %cl,%edx - 429426: 41 d3 e9 shr %cl,%r9d - 429429: 44 29 ca sub %r9d,%edx - 42942c: 0f 85 26 15 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> - 429432: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 429436: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42943d: 41 b9 03 00 00 00 mov $0x3,%r9d - 429443: 4c 8d 57 03 lea 0x3(%rdi),%r10 - 429447: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42944e: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 429455: 48 89 ca mov %rcx,%rdx - 429458: 49 83 c2 10 add $0x10,%r10 - 42945c: 0f 8f de 00 00 00 jg 429540 <__strcasecmp_l_sse42+0x730> - 429462: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 429467: 66 0f 3a 0f 44 17 f0 palignr $0x3,-0x10(%rdi,%rdx,1),%xmm0 - 42946e: 03 - 42946f: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 429474: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 429478: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 42947d: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 429482: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 429487: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 42948b: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 429490: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 429495: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 42949a: 66 41 0f db f8 pand %xmm8,%xmm7 - 42949f: 66 45 0f db ca pand %xmm10,%xmm9 - 4294a4: 66 0f db fe pand %xmm6,%xmm7 - 4294a8: 66 44 0f db ce pand %xmm6,%xmm9 - 4294ad: 66 0f eb c7 por %xmm7,%xmm0 - 4294b1: 66 41 0f eb c9 por %xmm9,%xmm1 - 4294b6: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 4294bc: 0f 86 6e 14 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> - 4294c2: 48 83 c2 10 add $0x10,%rdx - 4294c6: 49 83 c2 10 add $0x10,%r10 - 4294ca: 7f 74 jg 429540 <__strcasecmp_l_sse42+0x730> - 4294cc: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 4294d1: 66 0f 3a 0f 44 17 f0 palignr $0x3,-0x10(%rdi,%rdx,1),%xmm0 - 4294d8: 03 - 4294d9: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 4294de: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 4294e2: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 4294e7: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 4294ec: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 4294f1: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 4294f5: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 4294fa: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 4294ff: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 429504: 66 41 0f db f8 pand %xmm8,%xmm7 - 429509: 66 45 0f db ca pand %xmm10,%xmm9 - 42950e: 66 0f db fe pand %xmm6,%xmm7 - 429512: 66 44 0f db ce pand %xmm6,%xmm9 - 429517: 66 0f eb c7 por %xmm7,%xmm0 - 42951b: 66 41 0f eb c9 por %xmm9,%xmm1 - 429520: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 429526: 0f 86 04 14 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> - 42952c: 48 83 c2 10 add $0x10,%rdx - 429530: e9 23 ff ff ff jmpq 429458 <__strcasecmp_l_sse42+0x648> - 429535: 90 nop - 429536: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42953d: 00 00 00 - 429540: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 429547: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 - 42954d: 66 0f 73 d8 03 psrldq $0x3,%xmm0 - 429552: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 - 429558: 83 f9 0c cmp $0xc,%ecx - 42955b: 0f 87 01 ff ff ff ja 429462 <__strcasecmp_l_sse42+0x652> - 429561: e9 7b 13 00 00 jmpq 42a8e1 <__strcasecmp_l_sse42+0x1ad1> - 429566: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42956d: 00 00 00 - 429570: 66 0f 73 fa 0c pslldq $0xc,%xmm2 - 429575: 66 0f 6f f9 movdqa %xmm1,%xmm7 - 429579: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 42957e: 66 44 0f 6f ca movdqa %xmm2,%xmm9 - 429583: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 429588: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 42958c: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 - 429591: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 429596: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 - 42959b: 66 41 0f db f8 pand %xmm8,%xmm7 - 4295a0: 66 45 0f db ca pand %xmm10,%xmm9 - 4295a5: 66 0f db fe pand %xmm6,%xmm7 - 4295a9: 66 44 0f db ce pand %xmm6,%xmm9 - 4295ae: 66 0f eb cf por %xmm7,%xmm1 - 4295b2: 66 41 0f eb d1 por %xmm9,%xmm2 - 4295b7: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 4295bb: 66 0f f8 d0 psubb %xmm0,%xmm2 - 4295bf: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 4295c4: d3 ea shr %cl,%edx - 4295c6: 41 d3 e9 shr %cl,%r9d - 4295c9: 44 29 ca sub %r9d,%edx - 4295cc: 0f 85 86 13 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> - 4295d2: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 4295d6: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 4295dd: 41 b9 04 00 00 00 mov $0x4,%r9d - 4295e3: 4c 8d 57 04 lea 0x4(%rdi),%r10 - 4295e7: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 4295ee: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 4295f5: 48 89 ca mov %rcx,%rdx - 4295f8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 4295ff: 00 - 429600: 49 83 c2 10 add $0x10,%r10 - 429604: 0f 8f d6 00 00 00 jg 4296e0 <__strcasecmp_l_sse42+0x8d0> - 42960a: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 42960f: 66 0f 3a 0f 44 17 f0 palignr $0x4,-0x10(%rdi,%rdx,1),%xmm0 - 429616: 04 - 429617: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 42961c: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 429620: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 429625: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 42962a: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 42962f: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 429633: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 429638: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 42963d: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 429642: 66 41 0f db f8 pand %xmm8,%xmm7 - 429647: 66 45 0f db ca pand %xmm10,%xmm9 - 42964c: 66 0f db fe pand %xmm6,%xmm7 - 429650: 66 44 0f db ce pand %xmm6,%xmm9 - 429655: 66 0f eb c7 por %xmm7,%xmm0 - 429659: 66 41 0f eb c9 por %xmm9,%xmm1 - 42965e: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 429664: 0f 86 c6 12 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> - 42966a: 48 83 c2 10 add $0x10,%rdx - 42966e: 49 83 c2 10 add $0x10,%r10 - 429672: 7f 6c jg 4296e0 <__strcasecmp_l_sse42+0x8d0> - 429674: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 429679: 66 0f 3a 0f 44 17 f0 palignr $0x4,-0x10(%rdi,%rdx,1),%xmm0 - 429680: 04 - 429681: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 429686: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 42968a: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 42968f: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 429694: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 429699: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 42969d: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 4296a2: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 4296a7: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 4296ac: 66 41 0f db f8 pand %xmm8,%xmm7 - 4296b1: 66 45 0f db ca pand %xmm10,%xmm9 - 4296b6: 66 0f db fe pand %xmm6,%xmm7 - 4296ba: 66 44 0f db ce pand %xmm6,%xmm9 - 4296bf: 66 0f eb c7 por %xmm7,%xmm0 - 4296c3: 66 41 0f eb c9 por %xmm9,%xmm1 - 4296c8: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 4296ce: 0f 86 5c 12 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> - 4296d4: 48 83 c2 10 add $0x10,%rdx - 4296d8: e9 23 ff ff ff jmpq 429600 <__strcasecmp_l_sse42+0x7f0> - 4296dd: 0f 1f 00 nopl (%rax) - 4296e0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 4296e7: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 - 4296ed: 66 0f 73 d8 04 psrldq $0x4,%xmm0 - 4296f2: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 - 4296f8: 83 f9 0b cmp $0xb,%ecx - 4296fb: 0f 87 09 ff ff ff ja 42960a <__strcasecmp_l_sse42+0x7fa> - 429701: e9 db 11 00 00 jmpq 42a8e1 <__strcasecmp_l_sse42+0x1ad1> - 429706: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42970d: 00 00 00 - 429710: 66 0f 73 fa 0b pslldq $0xb,%xmm2 - 429715: 66 0f 6f f9 movdqa %xmm1,%xmm7 - 429719: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 42971e: 66 44 0f 6f ca movdqa %xmm2,%xmm9 - 429723: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 429728: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 42972c: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 - 429731: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 429736: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 - 42973b: 66 41 0f db f8 pand %xmm8,%xmm7 - 429740: 66 45 0f db ca pand %xmm10,%xmm9 - 429745: 66 0f db fe pand %xmm6,%xmm7 - 429749: 66 44 0f db ce pand %xmm6,%xmm9 - 42974e: 66 0f eb cf por %xmm7,%xmm1 - 429752: 66 41 0f eb d1 por %xmm9,%xmm2 - 429757: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42975b: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42975f: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 429764: d3 ea shr %cl,%edx - 429766: 41 d3 e9 shr %cl,%r9d - 429769: 44 29 ca sub %r9d,%edx - 42976c: 0f 85 e6 11 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> - 429772: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 429776: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42977d: 41 b9 05 00 00 00 mov $0x5,%r9d - 429783: 4c 8d 57 05 lea 0x5(%rdi),%r10 - 429787: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42978e: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 429795: 48 89 ca mov %rcx,%rdx - 429798: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 42979f: 00 - 4297a0: 49 83 c2 10 add $0x10,%r10 - 4297a4: 0f 8f d6 00 00 00 jg 429880 <__strcasecmp_l_sse42+0xa70> - 4297aa: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 4297af: 66 0f 3a 0f 44 17 f0 palignr $0x5,-0x10(%rdi,%rdx,1),%xmm0 - 4297b6: 05 - 4297b7: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 4297bc: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 4297c0: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 4297c5: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 4297ca: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 4297cf: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 4297d3: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 4297d8: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 4297dd: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 4297e2: 66 41 0f db f8 pand %xmm8,%xmm7 - 4297e7: 66 45 0f db ca pand %xmm10,%xmm9 - 4297ec: 66 0f db fe pand %xmm6,%xmm7 - 4297f0: 66 44 0f db ce pand %xmm6,%xmm9 - 4297f5: 66 0f eb c7 por %xmm7,%xmm0 - 4297f9: 66 41 0f eb c9 por %xmm9,%xmm1 - 4297fe: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 429804: 0f 86 26 11 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> - 42980a: 48 83 c2 10 add $0x10,%rdx - 42980e: 49 83 c2 10 add $0x10,%r10 - 429812: 7f 6c jg 429880 <__strcasecmp_l_sse42+0xa70> - 429814: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 429819: 66 0f 3a 0f 44 17 f0 palignr $0x5,-0x10(%rdi,%rdx,1),%xmm0 - 429820: 05 - 429821: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 429826: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 42982a: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 42982f: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 429834: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 429839: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 42983d: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 429842: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 429847: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 42984c: 66 41 0f db f8 pand %xmm8,%xmm7 - 429851: 66 45 0f db ca pand %xmm10,%xmm9 - 429856: 66 0f db fe pand %xmm6,%xmm7 - 42985a: 66 44 0f db ce pand %xmm6,%xmm9 - 42985f: 66 0f eb c7 por %xmm7,%xmm0 - 429863: 66 41 0f eb c9 por %xmm9,%xmm1 - 429868: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 42986e: 0f 86 bc 10 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> - 429874: 48 83 c2 10 add $0x10,%rdx - 429878: e9 23 ff ff ff jmpq 4297a0 <__strcasecmp_l_sse42+0x990> - 42987d: 0f 1f 00 nopl (%rax) - 429880: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 429887: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 - 42988d: 66 0f 73 d8 05 psrldq $0x5,%xmm0 - 429892: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 - 429898: 83 f9 0a cmp $0xa,%ecx - 42989b: 0f 87 09 ff ff ff ja 4297aa <__strcasecmp_l_sse42+0x99a> - 4298a1: e9 3b 10 00 00 jmpq 42a8e1 <__strcasecmp_l_sse42+0x1ad1> - 4298a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4298ad: 00 00 00 - 4298b0: 66 0f 73 fa 0a pslldq $0xa,%xmm2 - 4298b5: 66 0f 6f f9 movdqa %xmm1,%xmm7 - 4298b9: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 4298be: 66 44 0f 6f ca movdqa %xmm2,%xmm9 - 4298c3: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 4298c8: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 4298cc: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 - 4298d1: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 4298d6: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 - 4298db: 66 41 0f db f8 pand %xmm8,%xmm7 - 4298e0: 66 45 0f db ca pand %xmm10,%xmm9 - 4298e5: 66 0f db fe pand %xmm6,%xmm7 - 4298e9: 66 44 0f db ce pand %xmm6,%xmm9 - 4298ee: 66 0f eb cf por %xmm7,%xmm1 - 4298f2: 66 41 0f eb d1 por %xmm9,%xmm2 - 4298f7: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 4298fb: 66 0f f8 d0 psubb %xmm0,%xmm2 - 4298ff: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 429904: d3 ea shr %cl,%edx - 429906: 41 d3 e9 shr %cl,%r9d - 429909: 44 29 ca sub %r9d,%edx - 42990c: 0f 85 46 10 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> - 429912: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 429916: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42991d: 41 b9 06 00 00 00 mov $0x6,%r9d - 429923: 4c 8d 57 06 lea 0x6(%rdi),%r10 - 429927: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42992e: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 429935: 48 89 ca mov %rcx,%rdx - 429938: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 42993f: 00 - 429940: 49 83 c2 10 add $0x10,%r10 - 429944: 0f 8f d6 00 00 00 jg 429a20 <__strcasecmp_l_sse42+0xc10> - 42994a: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 42994f: 66 0f 3a 0f 44 17 f0 palignr $0x6,-0x10(%rdi,%rdx,1),%xmm0 - 429956: 06 - 429957: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 42995c: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 429960: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 429965: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 42996a: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 42996f: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 429973: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 429978: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 42997d: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 429982: 66 41 0f db f8 pand %xmm8,%xmm7 - 429987: 66 45 0f db ca pand %xmm10,%xmm9 - 42998c: 66 0f db fe pand %xmm6,%xmm7 - 429990: 66 44 0f db ce pand %xmm6,%xmm9 - 429995: 66 0f eb c7 por %xmm7,%xmm0 - 429999: 66 41 0f eb c9 por %xmm9,%xmm1 - 42999e: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 4299a4: 0f 86 86 0f 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> - 4299aa: 48 83 c2 10 add $0x10,%rdx - 4299ae: 49 83 c2 10 add $0x10,%r10 - 4299b2: 7f 6c jg 429a20 <__strcasecmp_l_sse42+0xc10> - 4299b4: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 4299b9: 66 0f 3a 0f 44 17 f0 palignr $0x6,-0x10(%rdi,%rdx,1),%xmm0 - 4299c0: 06 - 4299c1: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 4299c6: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 4299ca: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 4299cf: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 4299d4: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 4299d9: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 4299dd: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 4299e2: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 4299e7: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 4299ec: 66 41 0f db f8 pand %xmm8,%xmm7 - 4299f1: 66 45 0f db ca pand %xmm10,%xmm9 - 4299f6: 66 0f db fe pand %xmm6,%xmm7 - 4299fa: 66 44 0f db ce pand %xmm6,%xmm9 - 4299ff: 66 0f eb c7 por %xmm7,%xmm0 - 429a03: 66 41 0f eb c9 por %xmm9,%xmm1 - 429a08: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 429a0e: 0f 86 1c 0f 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> - 429a14: 48 83 c2 10 add $0x10,%rdx - 429a18: e9 23 ff ff ff jmpq 429940 <__strcasecmp_l_sse42+0xb30> - 429a1d: 0f 1f 00 nopl (%rax) - 429a20: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 429a27: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 - 429a2d: 66 0f 73 d8 06 psrldq $0x6,%xmm0 - 429a32: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 - 429a38: 83 f9 09 cmp $0x9,%ecx - 429a3b: 0f 87 09 ff ff ff ja 42994a <__strcasecmp_l_sse42+0xb3a> - 429a41: e9 9b 0e 00 00 jmpq 42a8e1 <__strcasecmp_l_sse42+0x1ad1> - 429a46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 429a4d: 00 00 00 - 429a50: 66 0f 73 fa 09 pslldq $0x9,%xmm2 - 429a55: 66 0f 6f f9 movdqa %xmm1,%xmm7 - 429a59: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 429a5e: 66 44 0f 6f ca movdqa %xmm2,%xmm9 - 429a63: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 429a68: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 429a6c: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 - 429a71: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 429a76: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 - 429a7b: 66 41 0f db f8 pand %xmm8,%xmm7 - 429a80: 66 45 0f db ca pand %xmm10,%xmm9 - 429a85: 66 0f db fe pand %xmm6,%xmm7 - 429a89: 66 44 0f db ce pand %xmm6,%xmm9 - 429a8e: 66 0f eb cf por %xmm7,%xmm1 - 429a92: 66 41 0f eb d1 por %xmm9,%xmm2 - 429a97: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 429a9b: 66 0f f8 d0 psubb %xmm0,%xmm2 - 429a9f: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 429aa4: d3 ea shr %cl,%edx - 429aa6: 41 d3 e9 shr %cl,%r9d - 429aa9: 44 29 ca sub %r9d,%edx - 429aac: 0f 85 a6 0e 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> - 429ab2: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 429ab6: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 429abd: 41 b9 07 00 00 00 mov $0x7,%r9d - 429ac3: 4c 8d 57 07 lea 0x7(%rdi),%r10 - 429ac7: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 429ace: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 429ad5: 48 89 ca mov %rcx,%rdx - 429ad8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 429adf: 00 - 429ae0: 49 83 c2 10 add $0x10,%r10 - 429ae4: 0f 8f d6 00 00 00 jg 429bc0 <__strcasecmp_l_sse42+0xdb0> - 429aea: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 429aef: 66 0f 3a 0f 44 17 f0 palignr $0x7,-0x10(%rdi,%rdx,1),%xmm0 - 429af6: 07 - 429af7: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 429afc: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 429b00: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 429b05: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 429b0a: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 429b0f: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 429b13: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 429b18: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 429b1d: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 429b22: 66 41 0f db f8 pand %xmm8,%xmm7 - 429b27: 66 45 0f db ca pand %xmm10,%xmm9 - 429b2c: 66 0f db fe pand %xmm6,%xmm7 - 429b30: 66 44 0f db ce pand %xmm6,%xmm9 - 429b35: 66 0f eb c7 por %xmm7,%xmm0 - 429b39: 66 41 0f eb c9 por %xmm9,%xmm1 - 429b3e: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 429b44: 0f 86 e6 0d 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> - 429b4a: 48 83 c2 10 add $0x10,%rdx - 429b4e: 49 83 c2 10 add $0x10,%r10 - 429b52: 7f 6c jg 429bc0 <__strcasecmp_l_sse42+0xdb0> - 429b54: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 429b59: 66 0f 3a 0f 44 17 f0 palignr $0x7,-0x10(%rdi,%rdx,1),%xmm0 - 429b60: 07 - 429b61: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 429b66: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 429b6a: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 429b6f: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 429b74: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 429b79: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 429b7d: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 429b82: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 429b87: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 429b8c: 66 41 0f db f8 pand %xmm8,%xmm7 - 429b91: 66 45 0f db ca pand %xmm10,%xmm9 - 429b96: 66 0f db fe pand %xmm6,%xmm7 - 429b9a: 66 44 0f db ce pand %xmm6,%xmm9 - 429b9f: 66 0f eb c7 por %xmm7,%xmm0 - 429ba3: 66 41 0f eb c9 por %xmm9,%xmm1 - 429ba8: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 429bae: 0f 86 7c 0d 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> - 429bb4: 48 83 c2 10 add $0x10,%rdx - 429bb8: e9 23 ff ff ff jmpq 429ae0 <__strcasecmp_l_sse42+0xcd0> - 429bbd: 0f 1f 00 nopl (%rax) - 429bc0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 429bc7: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 - 429bcd: 66 0f 73 d8 07 psrldq $0x7,%xmm0 - 429bd2: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 - 429bd8: 83 f9 08 cmp $0x8,%ecx - 429bdb: 0f 87 09 ff ff ff ja 429aea <__strcasecmp_l_sse42+0xcda> - 429be1: e9 fb 0c 00 00 jmpq 42a8e1 <__strcasecmp_l_sse42+0x1ad1> - 429be6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 429bed: 00 00 00 - 429bf0: 66 0f 73 fa 08 pslldq $0x8,%xmm2 - 429bf5: 66 0f 6f f9 movdqa %xmm1,%xmm7 - 429bf9: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 429bfe: 66 44 0f 6f ca movdqa %xmm2,%xmm9 - 429c03: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 429c08: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 429c0c: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 - 429c11: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 429c16: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 - 429c1b: 66 41 0f db f8 pand %xmm8,%xmm7 - 429c20: 66 45 0f db ca pand %xmm10,%xmm9 - 429c25: 66 0f db fe pand %xmm6,%xmm7 - 429c29: 66 44 0f db ce pand %xmm6,%xmm9 - 429c2e: 66 0f eb cf por %xmm7,%xmm1 - 429c32: 66 41 0f eb d1 por %xmm9,%xmm2 - 429c37: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 429c3b: 66 0f f8 d0 psubb %xmm0,%xmm2 - 429c3f: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 429c44: d3 ea shr %cl,%edx - 429c46: 41 d3 e9 shr %cl,%r9d - 429c49: 44 29 ca sub %r9d,%edx - 429c4c: 0f 85 06 0d 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> - 429c52: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 429c56: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 429c5d: 41 b9 08 00 00 00 mov $0x8,%r9d - 429c63: 4c 8d 57 08 lea 0x8(%rdi),%r10 - 429c67: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 429c6e: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 429c75: 48 89 ca mov %rcx,%rdx - 429c78: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 429c7f: 00 - 429c80: 49 83 c2 10 add $0x10,%r10 - 429c84: 0f 8f d6 00 00 00 jg 429d60 <__strcasecmp_l_sse42+0xf50> - 429c8a: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 429c8f: 66 0f 3a 0f 44 17 f0 palignr $0x8,-0x10(%rdi,%rdx,1),%xmm0 - 429c96: 08 - 429c97: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 429c9c: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 429ca0: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 429ca5: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 429caa: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 429caf: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 429cb3: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 429cb8: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 429cbd: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 429cc2: 66 41 0f db f8 pand %xmm8,%xmm7 - 429cc7: 66 45 0f db ca pand %xmm10,%xmm9 - 429ccc: 66 0f db fe pand %xmm6,%xmm7 - 429cd0: 66 44 0f db ce pand %xmm6,%xmm9 - 429cd5: 66 0f eb c7 por %xmm7,%xmm0 - 429cd9: 66 41 0f eb c9 por %xmm9,%xmm1 - 429cde: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 429ce4: 0f 86 46 0c 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> - 429cea: 48 83 c2 10 add $0x10,%rdx - 429cee: 49 83 c2 10 add $0x10,%r10 - 429cf2: 7f 6c jg 429d60 <__strcasecmp_l_sse42+0xf50> - 429cf4: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 429cf9: 66 0f 3a 0f 44 17 f0 palignr $0x8,-0x10(%rdi,%rdx,1),%xmm0 - 429d00: 08 - 429d01: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 429d06: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 429d0a: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 429d0f: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 429d14: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 429d19: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 429d1d: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 429d22: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 429d27: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 429d2c: 66 41 0f db f8 pand %xmm8,%xmm7 - 429d31: 66 45 0f db ca pand %xmm10,%xmm9 - 429d36: 66 0f db fe pand %xmm6,%xmm7 - 429d3a: 66 44 0f db ce pand %xmm6,%xmm9 - 429d3f: 66 0f eb c7 por %xmm7,%xmm0 - 429d43: 66 41 0f eb c9 por %xmm9,%xmm1 - 429d48: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 429d4e: 0f 86 dc 0b 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> - 429d54: 48 83 c2 10 add $0x10,%rdx - 429d58: e9 23 ff ff ff jmpq 429c80 <__strcasecmp_l_sse42+0xe70> - 429d5d: 0f 1f 00 nopl (%rax) - 429d60: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 429d67: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 - 429d6d: 66 0f 73 d8 08 psrldq $0x8,%xmm0 - 429d72: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 - 429d78: 83 f9 07 cmp $0x7,%ecx - 429d7b: 0f 87 09 ff ff ff ja 429c8a <__strcasecmp_l_sse42+0xe7a> - 429d81: e9 5b 0b 00 00 jmpq 42a8e1 <__strcasecmp_l_sse42+0x1ad1> - 429d86: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 429d8d: 00 00 00 - 429d90: 66 0f 73 fa 07 pslldq $0x7,%xmm2 - 429d95: 66 0f 6f f9 movdqa %xmm1,%xmm7 - 429d99: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 429d9e: 66 44 0f 6f ca movdqa %xmm2,%xmm9 - 429da3: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 429da8: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 429dac: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 - 429db1: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 429db6: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 - 429dbb: 66 41 0f db f8 pand %xmm8,%xmm7 - 429dc0: 66 45 0f db ca pand %xmm10,%xmm9 - 429dc5: 66 0f db fe pand %xmm6,%xmm7 - 429dc9: 66 44 0f db ce pand %xmm6,%xmm9 - 429dce: 66 0f eb cf por %xmm7,%xmm1 - 429dd2: 66 41 0f eb d1 por %xmm9,%xmm2 - 429dd7: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 429ddb: 66 0f f8 d0 psubb %xmm0,%xmm2 - 429ddf: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 429de4: d3 ea shr %cl,%edx - 429de6: 41 d3 e9 shr %cl,%r9d - 429de9: 44 29 ca sub %r9d,%edx - 429dec: 0f 85 66 0b 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> - 429df2: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 429df6: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 429dfd: 41 b9 09 00 00 00 mov $0x9,%r9d - 429e03: 4c 8d 57 09 lea 0x9(%rdi),%r10 - 429e07: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 429e0e: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 429e15: 48 89 ca mov %rcx,%rdx - 429e18: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 429e1f: 00 - 429e20: 49 83 c2 10 add $0x10,%r10 - 429e24: 0f 8f d6 00 00 00 jg 429f00 <__strcasecmp_l_sse42+0x10f0> - 429e2a: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 429e2f: 66 0f 3a 0f 44 17 f0 palignr $0x9,-0x10(%rdi,%rdx,1),%xmm0 - 429e36: 09 - 429e37: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 429e3c: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 429e40: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 429e45: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 429e4a: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 429e4f: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 429e53: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 429e58: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 429e5d: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 429e62: 66 41 0f db f8 pand %xmm8,%xmm7 - 429e67: 66 45 0f db ca pand %xmm10,%xmm9 - 429e6c: 66 0f db fe pand %xmm6,%xmm7 - 429e70: 66 44 0f db ce pand %xmm6,%xmm9 - 429e75: 66 0f eb c7 por %xmm7,%xmm0 - 429e79: 66 41 0f eb c9 por %xmm9,%xmm1 - 429e7e: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 429e84: 0f 86 a6 0a 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> - 429e8a: 48 83 c2 10 add $0x10,%rdx - 429e8e: 49 83 c2 10 add $0x10,%r10 - 429e92: 7f 6c jg 429f00 <__strcasecmp_l_sse42+0x10f0> - 429e94: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 429e99: 66 0f 3a 0f 44 17 f0 palignr $0x9,-0x10(%rdi,%rdx,1),%xmm0 - 429ea0: 09 - 429ea1: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 429ea6: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 429eaa: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 429eaf: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 429eb4: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 429eb9: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 429ebd: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 429ec2: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 429ec7: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 429ecc: 66 41 0f db f8 pand %xmm8,%xmm7 - 429ed1: 66 45 0f db ca pand %xmm10,%xmm9 - 429ed6: 66 0f db fe pand %xmm6,%xmm7 - 429eda: 66 44 0f db ce pand %xmm6,%xmm9 - 429edf: 66 0f eb c7 por %xmm7,%xmm0 - 429ee3: 66 41 0f eb c9 por %xmm9,%xmm1 - 429ee8: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 429eee: 0f 86 3c 0a 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> - 429ef4: 48 83 c2 10 add $0x10,%rdx - 429ef8: e9 23 ff ff ff jmpq 429e20 <__strcasecmp_l_sse42+0x1010> - 429efd: 0f 1f 00 nopl (%rax) - 429f00: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 429f07: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 - 429f0d: 66 0f 73 d8 09 psrldq $0x9,%xmm0 - 429f12: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 - 429f18: 83 f9 06 cmp $0x6,%ecx - 429f1b: 0f 87 09 ff ff ff ja 429e2a <__strcasecmp_l_sse42+0x101a> - 429f21: e9 bb 09 00 00 jmpq 42a8e1 <__strcasecmp_l_sse42+0x1ad1> - 429f26: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 429f2d: 00 00 00 - 429f30: 66 0f 73 fa 06 pslldq $0x6,%xmm2 - 429f35: 66 0f 6f f9 movdqa %xmm1,%xmm7 - 429f39: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 429f3e: 66 44 0f 6f ca movdqa %xmm2,%xmm9 - 429f43: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 429f48: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 429f4c: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 - 429f51: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 429f56: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 - 429f5b: 66 41 0f db f8 pand %xmm8,%xmm7 - 429f60: 66 45 0f db ca pand %xmm10,%xmm9 - 429f65: 66 0f db fe pand %xmm6,%xmm7 - 429f69: 66 44 0f db ce pand %xmm6,%xmm9 - 429f6e: 66 0f eb cf por %xmm7,%xmm1 - 429f72: 66 41 0f eb d1 por %xmm9,%xmm2 - 429f77: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 429f7b: 66 0f f8 d0 psubb %xmm0,%xmm2 - 429f7f: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 429f84: d3 ea shr %cl,%edx - 429f86: 41 d3 e9 shr %cl,%r9d - 429f89: 44 29 ca sub %r9d,%edx - 429f8c: 0f 85 c6 09 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> - 429f92: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 429f96: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 429f9d: 41 b9 0a 00 00 00 mov $0xa,%r9d - 429fa3: 4c 8d 57 0a lea 0xa(%rdi),%r10 - 429fa7: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 429fae: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 429fb5: 48 89 ca mov %rcx,%rdx - 429fb8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 429fbf: 00 - 429fc0: 49 83 c2 10 add $0x10,%r10 - 429fc4: 0f 8f d6 00 00 00 jg 42a0a0 <__strcasecmp_l_sse42+0x1290> - 429fca: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 429fcf: 66 0f 3a 0f 44 17 f0 palignr $0xa,-0x10(%rdi,%rdx,1),%xmm0 - 429fd6: 0a - 429fd7: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 429fdc: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 429fe0: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 429fe5: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 429fea: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 429fef: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 429ff3: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 429ff8: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 429ffd: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 42a002: 66 41 0f db f8 pand %xmm8,%xmm7 - 42a007: 66 45 0f db ca pand %xmm10,%xmm9 - 42a00c: 66 0f db fe pand %xmm6,%xmm7 - 42a010: 66 44 0f db ce pand %xmm6,%xmm9 - 42a015: 66 0f eb c7 por %xmm7,%xmm0 - 42a019: 66 41 0f eb c9 por %xmm9,%xmm1 - 42a01e: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 42a024: 0f 86 06 09 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> - 42a02a: 48 83 c2 10 add $0x10,%rdx - 42a02e: 49 83 c2 10 add $0x10,%r10 - 42a032: 7f 6c jg 42a0a0 <__strcasecmp_l_sse42+0x1290> - 42a034: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 42a039: 66 0f 3a 0f 44 17 f0 palignr $0xa,-0x10(%rdi,%rdx,1),%xmm0 - 42a040: 0a - 42a041: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 42a046: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 42a04a: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 42a04f: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 42a054: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 42a059: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 42a05d: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 42a062: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 42a067: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 42a06c: 66 41 0f db f8 pand %xmm8,%xmm7 - 42a071: 66 45 0f db ca pand %xmm10,%xmm9 - 42a076: 66 0f db fe pand %xmm6,%xmm7 - 42a07a: 66 44 0f db ce pand %xmm6,%xmm9 - 42a07f: 66 0f eb c7 por %xmm7,%xmm0 - 42a083: 66 41 0f eb c9 por %xmm9,%xmm1 - 42a088: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 42a08e: 0f 86 9c 08 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> - 42a094: 48 83 c2 10 add $0x10,%rdx - 42a098: e9 23 ff ff ff jmpq 429fc0 <__strcasecmp_l_sse42+0x11b0> - 42a09d: 0f 1f 00 nopl (%rax) - 42a0a0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42a0a7: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 - 42a0ad: 66 0f 73 d8 0a psrldq $0xa,%xmm0 - 42a0b2: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 - 42a0b8: 83 f9 05 cmp $0x5,%ecx - 42a0bb: 0f 87 09 ff ff ff ja 429fca <__strcasecmp_l_sse42+0x11ba> - 42a0c1: e9 1b 08 00 00 jmpq 42a8e1 <__strcasecmp_l_sse42+0x1ad1> - 42a0c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42a0cd: 00 00 00 - 42a0d0: 66 0f 73 fa 05 pslldq $0x5,%xmm2 - 42a0d5: 66 0f 6f f9 movdqa %xmm1,%xmm7 - 42a0d9: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 42a0de: 66 44 0f 6f ca movdqa %xmm2,%xmm9 - 42a0e3: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 42a0e8: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 42a0ec: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 - 42a0f1: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 42a0f6: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 - 42a0fb: 66 41 0f db f8 pand %xmm8,%xmm7 - 42a100: 66 45 0f db ca pand %xmm10,%xmm9 - 42a105: 66 0f db fe pand %xmm6,%xmm7 - 42a109: 66 44 0f db ce pand %xmm6,%xmm9 - 42a10e: 66 0f eb cf por %xmm7,%xmm1 - 42a112: 66 41 0f eb d1 por %xmm9,%xmm2 - 42a117: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42a11b: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42a11f: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 42a124: d3 ea shr %cl,%edx - 42a126: 41 d3 e9 shr %cl,%r9d - 42a129: 44 29 ca sub %r9d,%edx - 42a12c: 0f 85 26 08 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> - 42a132: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 42a136: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42a13d: 41 b9 0b 00 00 00 mov $0xb,%r9d - 42a143: 4c 8d 57 0b lea 0xb(%rdi),%r10 - 42a147: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42a14e: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42a155: 48 89 ca mov %rcx,%rdx - 42a158: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 42a15f: 00 - 42a160: 49 83 c2 10 add $0x10,%r10 - 42a164: 0f 8f d6 00 00 00 jg 42a240 <__strcasecmp_l_sse42+0x1430> - 42a16a: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 42a16f: 66 0f 3a 0f 44 17 f0 palignr $0xb,-0x10(%rdi,%rdx,1),%xmm0 - 42a176: 0b - 42a177: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 42a17c: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 42a180: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 42a185: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 42a18a: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 42a18f: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 42a193: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 42a198: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 42a19d: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 42a1a2: 66 41 0f db f8 pand %xmm8,%xmm7 - 42a1a7: 66 45 0f db ca pand %xmm10,%xmm9 - 42a1ac: 66 0f db fe pand %xmm6,%xmm7 - 42a1b0: 66 44 0f db ce pand %xmm6,%xmm9 - 42a1b5: 66 0f eb c7 por %xmm7,%xmm0 - 42a1b9: 66 41 0f eb c9 por %xmm9,%xmm1 - 42a1be: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 42a1c4: 0f 86 66 07 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> - 42a1ca: 48 83 c2 10 add $0x10,%rdx - 42a1ce: 49 83 c2 10 add $0x10,%r10 - 42a1d2: 7f 6c jg 42a240 <__strcasecmp_l_sse42+0x1430> - 42a1d4: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 42a1d9: 66 0f 3a 0f 44 17 f0 palignr $0xb,-0x10(%rdi,%rdx,1),%xmm0 - 42a1e0: 0b - 42a1e1: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 42a1e6: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 42a1ea: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 42a1ef: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 42a1f4: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 42a1f9: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 42a1fd: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 42a202: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 42a207: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 42a20c: 66 41 0f db f8 pand %xmm8,%xmm7 - 42a211: 66 45 0f db ca pand %xmm10,%xmm9 - 42a216: 66 0f db fe pand %xmm6,%xmm7 - 42a21a: 66 44 0f db ce pand %xmm6,%xmm9 - 42a21f: 66 0f eb c7 por %xmm7,%xmm0 - 42a223: 66 41 0f eb c9 por %xmm9,%xmm1 - 42a228: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 42a22e: 0f 86 fc 06 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> - 42a234: 48 83 c2 10 add $0x10,%rdx - 42a238: e9 23 ff ff ff jmpq 42a160 <__strcasecmp_l_sse42+0x1350> - 42a23d: 0f 1f 00 nopl (%rax) - 42a240: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42a247: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 - 42a24d: 66 0f 73 d8 0b psrldq $0xb,%xmm0 - 42a252: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 - 42a258: 83 f9 04 cmp $0x4,%ecx - 42a25b: 0f 87 09 ff ff ff ja 42a16a <__strcasecmp_l_sse42+0x135a> - 42a261: e9 7b 06 00 00 jmpq 42a8e1 <__strcasecmp_l_sse42+0x1ad1> - 42a266: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42a26d: 00 00 00 - 42a270: 66 0f 73 fa 04 pslldq $0x4,%xmm2 - 42a275: 66 0f 6f f9 movdqa %xmm1,%xmm7 - 42a279: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 42a27e: 66 44 0f 6f ca movdqa %xmm2,%xmm9 - 42a283: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 42a288: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 42a28c: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 - 42a291: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 42a296: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 - 42a29b: 66 41 0f db f8 pand %xmm8,%xmm7 - 42a2a0: 66 45 0f db ca pand %xmm10,%xmm9 - 42a2a5: 66 0f db fe pand %xmm6,%xmm7 - 42a2a9: 66 44 0f db ce pand %xmm6,%xmm9 - 42a2ae: 66 0f eb cf por %xmm7,%xmm1 - 42a2b2: 66 41 0f eb d1 por %xmm9,%xmm2 - 42a2b7: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42a2bb: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42a2bf: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 42a2c4: d3 ea shr %cl,%edx - 42a2c6: 41 d3 e9 shr %cl,%r9d - 42a2c9: 44 29 ca sub %r9d,%edx - 42a2cc: 0f 85 86 06 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> - 42a2d2: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 42a2d6: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42a2dd: 41 b9 0c 00 00 00 mov $0xc,%r9d - 42a2e3: 4c 8d 57 0c lea 0xc(%rdi),%r10 - 42a2e7: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42a2ee: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42a2f5: 48 89 ca mov %rcx,%rdx - 42a2f8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 42a2ff: 00 - 42a300: 49 83 c2 10 add $0x10,%r10 - 42a304: 0f 8f d6 00 00 00 jg 42a3e0 <__strcasecmp_l_sse42+0x15d0> - 42a30a: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 42a30f: 66 0f 3a 0f 44 17 f0 palignr $0xc,-0x10(%rdi,%rdx,1),%xmm0 - 42a316: 0c - 42a317: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 42a31c: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 42a320: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 42a325: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 42a32a: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 42a32f: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 42a333: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 42a338: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 42a33d: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 42a342: 66 41 0f db f8 pand %xmm8,%xmm7 - 42a347: 66 45 0f db ca pand %xmm10,%xmm9 - 42a34c: 66 0f db fe pand %xmm6,%xmm7 - 42a350: 66 44 0f db ce pand %xmm6,%xmm9 - 42a355: 66 0f eb c7 por %xmm7,%xmm0 - 42a359: 66 41 0f eb c9 por %xmm9,%xmm1 - 42a35e: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 42a364: 0f 86 c6 05 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> - 42a36a: 48 83 c2 10 add $0x10,%rdx - 42a36e: 49 83 c2 10 add $0x10,%r10 - 42a372: 7f 6c jg 42a3e0 <__strcasecmp_l_sse42+0x15d0> - 42a374: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 42a379: 66 0f 3a 0f 44 17 f0 palignr $0xc,-0x10(%rdi,%rdx,1),%xmm0 - 42a380: 0c - 42a381: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 42a386: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 42a38a: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 42a38f: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 42a394: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 42a399: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 42a39d: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 42a3a2: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 42a3a7: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 42a3ac: 66 41 0f db f8 pand %xmm8,%xmm7 - 42a3b1: 66 45 0f db ca pand %xmm10,%xmm9 - 42a3b6: 66 0f db fe pand %xmm6,%xmm7 - 42a3ba: 66 44 0f db ce pand %xmm6,%xmm9 - 42a3bf: 66 0f eb c7 por %xmm7,%xmm0 - 42a3c3: 66 41 0f eb c9 por %xmm9,%xmm1 - 42a3c8: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 42a3ce: 0f 86 5c 05 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> - 42a3d4: 48 83 c2 10 add $0x10,%rdx - 42a3d8: e9 23 ff ff ff jmpq 42a300 <__strcasecmp_l_sse42+0x14f0> - 42a3dd: 0f 1f 00 nopl (%rax) - 42a3e0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42a3e7: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 - 42a3ed: 66 0f 73 d8 0c psrldq $0xc,%xmm0 - 42a3f2: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 - 42a3f8: 83 f9 03 cmp $0x3,%ecx - 42a3fb: 0f 87 09 ff ff ff ja 42a30a <__strcasecmp_l_sse42+0x14fa> - 42a401: e9 db 04 00 00 jmpq 42a8e1 <__strcasecmp_l_sse42+0x1ad1> - 42a406: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42a40d: 00 00 00 - 42a410: 66 0f 73 fa 03 pslldq $0x3,%xmm2 - 42a415: 66 0f 6f f9 movdqa %xmm1,%xmm7 - 42a419: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 42a41e: 66 44 0f 6f ca movdqa %xmm2,%xmm9 - 42a423: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 42a428: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 42a42c: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 - 42a431: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 42a436: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 - 42a43b: 66 41 0f db f8 pand %xmm8,%xmm7 - 42a440: 66 45 0f db ca pand %xmm10,%xmm9 - 42a445: 66 0f db fe pand %xmm6,%xmm7 - 42a449: 66 44 0f db ce pand %xmm6,%xmm9 - 42a44e: 66 0f eb cf por %xmm7,%xmm1 - 42a452: 66 41 0f eb d1 por %xmm9,%xmm2 - 42a457: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42a45b: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42a45f: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 42a464: d3 ea shr %cl,%edx - 42a466: 41 d3 e9 shr %cl,%r9d - 42a469: 44 29 ca sub %r9d,%edx - 42a46c: 0f 85 e6 04 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> - 42a472: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 42a476: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42a47d: 41 b9 0d 00 00 00 mov $0xd,%r9d - 42a483: 4c 8d 57 0d lea 0xd(%rdi),%r10 - 42a487: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42a48e: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42a495: 48 89 ca mov %rcx,%rdx - 42a498: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 42a49f: 00 - 42a4a0: 49 83 c2 10 add $0x10,%r10 - 42a4a4: 0f 8f d6 00 00 00 jg 42a580 <__strcasecmp_l_sse42+0x1770> - 42a4aa: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 42a4af: 66 0f 3a 0f 44 17 f0 palignr $0xd,-0x10(%rdi,%rdx,1),%xmm0 - 42a4b6: 0d - 42a4b7: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 42a4bc: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 42a4c0: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 42a4c5: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 42a4ca: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 42a4cf: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 42a4d3: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 42a4d8: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 42a4dd: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 42a4e2: 66 41 0f db f8 pand %xmm8,%xmm7 - 42a4e7: 66 45 0f db ca pand %xmm10,%xmm9 - 42a4ec: 66 0f db fe pand %xmm6,%xmm7 - 42a4f0: 66 44 0f db ce pand %xmm6,%xmm9 - 42a4f5: 66 0f eb c7 por %xmm7,%xmm0 - 42a4f9: 66 41 0f eb c9 por %xmm9,%xmm1 - 42a4fe: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 42a504: 0f 86 26 04 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> - 42a50a: 48 83 c2 10 add $0x10,%rdx - 42a50e: 49 83 c2 10 add $0x10,%r10 - 42a512: 7f 6c jg 42a580 <__strcasecmp_l_sse42+0x1770> - 42a514: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 42a519: 66 0f 3a 0f 44 17 f0 palignr $0xd,-0x10(%rdi,%rdx,1),%xmm0 - 42a520: 0d - 42a521: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 42a526: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 42a52a: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 42a52f: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 42a534: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 42a539: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 42a53d: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 42a542: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 42a547: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 42a54c: 66 41 0f db f8 pand %xmm8,%xmm7 - 42a551: 66 45 0f db ca pand %xmm10,%xmm9 - 42a556: 66 0f db fe pand %xmm6,%xmm7 - 42a55a: 66 44 0f db ce pand %xmm6,%xmm9 - 42a55f: 66 0f eb c7 por %xmm7,%xmm0 - 42a563: 66 41 0f eb c9 por %xmm9,%xmm1 - 42a568: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 42a56e: 0f 86 bc 03 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> - 42a574: 48 83 c2 10 add $0x10,%rdx - 42a578: e9 23 ff ff ff jmpq 42a4a0 <__strcasecmp_l_sse42+0x1690> - 42a57d: 0f 1f 00 nopl (%rax) - 42a580: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42a587: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 - 42a58d: 66 0f 73 d8 0d psrldq $0xd,%xmm0 - 42a592: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 - 42a598: 83 f9 02 cmp $0x2,%ecx - 42a59b: 0f 87 09 ff ff ff ja 42a4aa <__strcasecmp_l_sse42+0x169a> - 42a5a1: e9 3b 03 00 00 jmpq 42a8e1 <__strcasecmp_l_sse42+0x1ad1> - 42a5a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42a5ad: 00 00 00 - 42a5b0: 66 0f 73 fa 02 pslldq $0x2,%xmm2 - 42a5b5: 66 0f 6f f9 movdqa %xmm1,%xmm7 - 42a5b9: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 42a5be: 66 44 0f 6f ca movdqa %xmm2,%xmm9 - 42a5c3: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 42a5c8: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 42a5cc: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 - 42a5d1: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 42a5d6: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 - 42a5db: 66 41 0f db f8 pand %xmm8,%xmm7 - 42a5e0: 66 45 0f db ca pand %xmm10,%xmm9 - 42a5e5: 66 0f db fe pand %xmm6,%xmm7 - 42a5e9: 66 44 0f db ce pand %xmm6,%xmm9 - 42a5ee: 66 0f eb cf por %xmm7,%xmm1 - 42a5f2: 66 41 0f eb d1 por %xmm9,%xmm2 - 42a5f7: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42a5fb: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42a5ff: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 42a604: d3 ea shr %cl,%edx - 42a606: 41 d3 e9 shr %cl,%r9d - 42a609: 44 29 ca sub %r9d,%edx - 42a60c: 0f 85 46 03 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> - 42a612: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 42a616: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42a61d: 41 b9 0e 00 00 00 mov $0xe,%r9d - 42a623: 4c 8d 57 0e lea 0xe(%rdi),%r10 - 42a627: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42a62e: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42a635: 48 89 ca mov %rcx,%rdx - 42a638: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 42a63f: 00 - 42a640: 49 83 c2 10 add $0x10,%r10 - 42a644: 0f 8f d6 00 00 00 jg 42a720 <__strcasecmp_l_sse42+0x1910> - 42a64a: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 42a64f: 66 0f 3a 0f 44 17 f0 palignr $0xe,-0x10(%rdi,%rdx,1),%xmm0 - 42a656: 0e - 42a657: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 42a65c: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 42a660: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 42a665: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 42a66a: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 42a66f: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 42a673: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 42a678: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 42a67d: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 42a682: 66 41 0f db f8 pand %xmm8,%xmm7 - 42a687: 66 45 0f db ca pand %xmm10,%xmm9 - 42a68c: 66 0f db fe pand %xmm6,%xmm7 - 42a690: 66 44 0f db ce pand %xmm6,%xmm9 - 42a695: 66 0f eb c7 por %xmm7,%xmm0 - 42a699: 66 41 0f eb c9 por %xmm9,%xmm1 - 42a69e: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 42a6a4: 0f 86 86 02 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> - 42a6aa: 48 83 c2 10 add $0x10,%rdx - 42a6ae: 49 83 c2 10 add $0x10,%r10 - 42a6b2: 7f 6c jg 42a720 <__strcasecmp_l_sse42+0x1910> - 42a6b4: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 42a6b9: 66 0f 3a 0f 44 17 f0 palignr $0xe,-0x10(%rdi,%rdx,1),%xmm0 - 42a6c0: 0e - 42a6c1: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 42a6c6: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 42a6ca: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 42a6cf: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 42a6d4: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 42a6d9: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 42a6dd: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 42a6e2: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 42a6e7: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 42a6ec: 66 41 0f db f8 pand %xmm8,%xmm7 - 42a6f1: 66 45 0f db ca pand %xmm10,%xmm9 - 42a6f6: 66 0f db fe pand %xmm6,%xmm7 - 42a6fa: 66 44 0f db ce pand %xmm6,%xmm9 - 42a6ff: 66 0f eb c7 por %xmm7,%xmm0 - 42a703: 66 41 0f eb c9 por %xmm9,%xmm1 - 42a708: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 42a70e: 0f 86 1c 02 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> - 42a714: 48 83 c2 10 add $0x10,%rdx - 42a718: e9 23 ff ff ff jmpq 42a640 <__strcasecmp_l_sse42+0x1830> - 42a71d: 0f 1f 00 nopl (%rax) - 42a720: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42a727: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 - 42a72d: 66 0f 73 d8 0e psrldq $0xe,%xmm0 - 42a732: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 - 42a738: 83 f9 01 cmp $0x1,%ecx - 42a73b: 0f 87 09 ff ff ff ja 42a64a <__strcasecmp_l_sse42+0x183a> - 42a741: e9 9b 01 00 00 jmpq 42a8e1 <__strcasecmp_l_sse42+0x1ad1> - 42a746: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42a74d: 00 00 00 - 42a750: 66 0f 73 fa 01 pslldq $0x1,%xmm2 - 42a755: 66 0f 6f f9 movdqa %xmm1,%xmm7 - 42a759: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 42a75e: 66 44 0f 6f ca movdqa %xmm2,%xmm9 - 42a763: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 42a768: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 42a76c: 66 44 0f 64 c1 pcmpgtb %xmm1,%xmm8 - 42a771: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 42a776: 66 44 0f 64 d2 pcmpgtb %xmm2,%xmm10 - 42a77b: 66 41 0f db f8 pand %xmm8,%xmm7 - 42a780: 66 45 0f db ca pand %xmm10,%xmm9 - 42a785: 66 0f db fe pand %xmm6,%xmm7 - 42a789: 66 44 0f db ce pand %xmm6,%xmm9 - 42a78e: 66 0f eb cf por %xmm7,%xmm1 - 42a792: 66 41 0f eb d1 por %xmm9,%xmm2 - 42a797: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42a79b: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42a79f: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 42a7a4: d3 ea shr %cl,%edx - 42a7a6: 41 d3 e9 shr %cl,%r9d - 42a7a9: 44 29 ca sub %r9d,%edx - 42a7ac: 0f 85 a6 01 00 00 jne 42a958 <__strcasecmp_l_sse42+0x1b48> - 42a7b2: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 42a7b6: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42a7bd: 41 b9 0f 00 00 00 mov $0xf,%r9d - 42a7c3: 4c 8d 57 0f lea 0xf(%rdi),%r10 - 42a7c7: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42a7ce: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42a7d5: 48 89 ca mov %rcx,%rdx - 42a7d8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 42a7df: 00 - 42a7e0: 49 83 c2 10 add $0x10,%r10 - 42a7e4: 0f 8f d6 00 00 00 jg 42a8c0 <__strcasecmp_l_sse42+0x1ab0> - 42a7ea: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 42a7ef: 66 0f 3a 0f 44 17 f0 palignr $0xf,-0x10(%rdi,%rdx,1),%xmm0 - 42a7f6: 0f - 42a7f7: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 42a7fc: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 42a800: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 42a805: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 42a80a: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 42a80f: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 42a813: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 42a818: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 42a81d: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 42a822: 66 41 0f db f8 pand %xmm8,%xmm7 - 42a827: 66 45 0f db ca pand %xmm10,%xmm9 - 42a82c: 66 0f db fe pand %xmm6,%xmm7 - 42a830: 66 44 0f db ce pand %xmm6,%xmm9 - 42a835: 66 0f eb c7 por %xmm7,%xmm0 - 42a839: 66 41 0f eb c9 por %xmm9,%xmm1 - 42a83e: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 42a844: 0f 86 e6 00 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> - 42a84a: 48 83 c2 10 add $0x10,%rdx - 42a84e: 49 83 c2 10 add $0x10,%r10 - 42a852: 7f 6c jg 42a8c0 <__strcasecmp_l_sse42+0x1ab0> - 42a854: 66 0f 6f 04 17 movdqa (%rdi,%rdx,1),%xmm0 - 42a859: 66 0f 3a 0f 44 17 f0 palignr $0xf,-0x10(%rdi,%rdx,1),%xmm0 - 42a860: 0f - 42a861: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 42a866: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 42a86a: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 42a86f: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 42a874: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 42a879: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 42a87d: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 42a882: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 42a887: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 42a88c: 66 41 0f db f8 pand %xmm8,%xmm7 - 42a891: 66 45 0f db ca pand %xmm10,%xmm9 - 42a896: 66 0f db fe pand %xmm6,%xmm7 - 42a89a: 66 44 0f db ce pand %xmm6,%xmm9 - 42a89f: 66 0f eb c7 por %xmm7,%xmm0 - 42a8a3: 66 41 0f eb c9 por %xmm9,%xmm1 - 42a8a8: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 42a8ae: 0f 86 7c 00 00 00 jbe 42a930 <__strcasecmp_l_sse42+0x1b20> - 42a8b4: 48 83 c2 10 add $0x10,%rdx - 42a8b8: e9 23 ff ff ff jmpq 42a7e0 <__strcasecmp_l_sse42+0x19d0> - 42a8bd: 0f 1f 00 nopl (%rax) - 42a8c0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42a8c7: 66 0f 6f 44 17 f0 movdqa -0x10(%rdi,%rdx,1),%xmm0 - 42a8cd: 66 0f 73 d8 0f psrldq $0xf,%xmm0 - 42a8d2: 66 0f 3a 63 c0 3a pcmpistri $0x3a,%xmm0,%xmm0 - 42a8d8: 83 f9 00 cmp $0x0,%ecx - 42a8db: 0f 87 09 ff ff ff ja 42a7ea <__strcasecmp_l_sse42+0x19da> - 42a8e1: 66 0f 6f 0c 16 movdqa (%rsi,%rdx,1),%xmm1 - 42a8e6: 66 0f 6f f8 movdqa %xmm0,%xmm7 - 42a8ea: 66 44 0f 6f c5 movdqa %xmm5,%xmm8 - 42a8ef: 66 44 0f 6f c9 movdqa %xmm1,%xmm9 - 42a8f4: 66 44 0f 6f d5 movdqa %xmm5,%xmm10 - 42a8f9: 66 0f 64 fc pcmpgtb %xmm4,%xmm7 - 42a8fd: 66 44 0f 64 c0 pcmpgtb %xmm0,%xmm8 - 42a902: 66 44 0f 64 cc pcmpgtb %xmm4,%xmm9 - 42a907: 66 44 0f 64 d1 pcmpgtb %xmm1,%xmm10 - 42a90c: 66 41 0f db f8 pand %xmm8,%xmm7 - 42a911: 66 45 0f db ca pand %xmm10,%xmm9 - 42a916: 66 0f db fe pand %xmm6,%xmm7 - 42a91a: 66 44 0f db ce pand %xmm6,%xmm9 - 42a91f: 66 0f eb c7 por %xmm7,%xmm0 - 42a923: 66 41 0f eb c9 por %xmm9,%xmm1 - 42a928: 66 0f 3a 63 c1 1a pcmpistri $0x1a,%xmm1,%xmm0 - 42a92e: 66 90 xchg %ax,%ax - 42a930: 73 5a jae 42a98c <__strcasecmp_l_sse42+0x1b7c> - 42a932: 48 01 ca add %rcx,%rdx - 42a935: 4a 8d 7c 0f f0 lea -0x10(%rdi,%r9,1),%rdi - 42a93a: 0f b6 04 17 movzbl (%rdi,%rdx,1),%eax - 42a93e: 0f b6 14 16 movzbl (%rsi,%rdx,1),%edx - 42a942: 45 85 c0 test %r8d,%r8d - 42a945: 74 01 je 42a948 <__strcasecmp_l_sse42+0x1b38> - 42a947: 92 xchg %eax,%edx - 42a948: 48 8d 0d f1 cb 07 00 lea 0x7cbf1(%rip),%rcx # 4a7540 <_nl_C_LC_CTYPE_tolower+0x200> - 42a94f: 8b 14 91 mov (%rcx,%rdx,4),%edx - 42a952: 8b 04 81 mov (%rcx,%rax,4),%eax - 42a955: 29 d0 sub %edx,%eax - 42a957: c3 retq - 42a958: 48 8d 3c 07 lea (%rdi,%rax,1),%rdi - 42a95c: 48 8d 34 0e lea (%rsi,%rcx,1),%rsi - 42a960: 45 85 c0 test %r8d,%r8d - 42a963: 74 0b je 42a970 <__strcasecmp_l_sse42+0x1b60> - 42a965: 48 87 f7 xchg %rsi,%rdi - 42a968: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 42a96f: 00 - 42a970: 48 0f bc d2 bsf %rdx,%rdx - 42a974: 0f b6 0c 16 movzbl (%rsi,%rdx,1),%ecx - 42a978: 0f b6 04 17 movzbl (%rdi,%rdx,1),%eax - 42a97c: 48 8d 15 bd cb 07 00 lea 0x7cbbd(%rip),%rdx # 4a7540 <_nl_C_LC_CTYPE_tolower+0x200> - 42a983: 8b 0c 8a mov (%rdx,%rcx,4),%ecx - 42a986: 8b 04 82 mov (%rdx,%rax,4),%eax - 42a989: 29 c8 sub %ecx,%eax - 42a98b: c3 retq - 42a98c: 31 c0 xor %eax,%eax - 42a98e: c3 retq - 42a98f: 90 nop - 42a990: 0f b6 0e movzbl (%rsi),%ecx - 42a993: 0f b6 07 movzbl (%rdi),%eax - 42a996: 48 8d 15 a3 cb 07 00 lea 0x7cba3(%rip),%rdx # 4a7540 <_nl_C_LC_CTYPE_tolower+0x200> - 42a99d: 8b 0c 8a mov (%rdx,%rcx,4),%ecx - 42a9a0: 8b 04 82 mov (%rdx,%rax,4),%eax - 42a9a3: 29 c8 sub %ecx,%eax - 42a9a5: c3 retq - 42a9a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42a9ad: 00 00 00 - -000000000042a9b0 <__strcasecmp_avx>: - 42a9b0: 48 c7 c0 b8 ff ff ff mov $0xffffffffffffffb8,%rax - 42a9b7: 64 48 8b 10 mov %fs:(%rax),%rdx - 42a9bb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - -000000000042a9c0 <__strcasecmp_l_avx>: - 42a9c0: 48 8b 02 mov (%rdx),%rax - 42a9c3: f7 80 78 02 00 00 01 testl $0x1,0x278(%rax) - 42a9ca: 00 00 00 - 42a9cd: 0f 85 2d 39 01 00 jne 43e300 <__strcasecmp_l_nonascii> - 42a9d3: 89 f1 mov %esi,%ecx - 42a9d5: 89 f8 mov %edi,%eax - 42a9d7: 48 83 e1 3f and $0x3f,%rcx - 42a9db: 48 83 e0 3f and $0x3f,%rax - 42a9df: c5 f9 6f 25 c9 86 07 vmovdqa 0x786c9(%rip),%xmm4 # 4a30b0 <__func__.10972+0xf0> - 42a9e6: 00 - 42a9e7: c5 f9 6f 2d f1 86 07 vmovdqa 0x786f1(%rip),%xmm5 # 4a30e0 - 42a9ee: 00 - 42a9ef: c5 f9 6f 35 d9 86 07 vmovdqa 0x786d9(%rip),%xmm6 # 4a30d0 - 42a9f6: 00 - 42a9f7: 83 f9 30 cmp $0x30,%ecx - 42a9fa: 77 64 ja 42aa60 <__strcasecmp_l_avx+0xa0> - 42a9fc: 83 f8 30 cmp $0x30,%eax - 42a9ff: 77 5f ja 42aa60 <__strcasecmp_l_avx+0xa0> - 42aa01: c5 fa 6f 0f vmovdqu (%rdi),%xmm1 - 42aa05: c5 fa 6f 16 vmovdqu (%rsi),%xmm2 - 42aa09: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 - 42aa0d: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 - 42aa11: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 - 42aa15: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 - 42aa19: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42aa1d: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42aa22: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42aa26: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42aa2a: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 - 42aa2e: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 - 42aa32: c5 f9 ef c0 vpxor %xmm0,%xmm0,%xmm0 - 42aa36: c5 f9 74 c1 vpcmpeqb %xmm1,%xmm0,%xmm0 - 42aa3a: c5 f1 74 ca vpcmpeqb %xmm2,%xmm1,%xmm1 - 42aa3e: c5 f1 f8 c8 vpsubb %xmm0,%xmm1,%xmm1 - 42aa42: c5 f9 d7 d1 vpmovmskb %xmm1,%edx - 42aa46: 81 ea ff ff 00 00 sub $0xffff,%edx - 42aa4c: 0f 85 8e 15 00 00 jne 42bfe0 <__strcasecmp_l_avx+0x1620> - 42aa52: 48 83 c6 10 add $0x10,%rsi - 42aa56: 48 83 c7 10 add $0x10,%rdi - 42aa5a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 42aa60: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi - 42aa64: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi - 42aa68: ba ff ff 00 00 mov $0xffff,%edx - 42aa6d: 45 31 c0 xor %r8d,%r8d - 42aa70: 83 e1 0f and $0xf,%ecx - 42aa73: 83 e0 0f and $0xf,%eax - 42aa76: c5 f9 ef c0 vpxor %xmm0,%xmm0,%xmm0 - 42aa7a: 39 c1 cmp %eax,%ecx - 42aa7c: 74 32 je 42aab0 <__strcasecmp_l_avx+0xf0> - 42aa7e: 77 07 ja 42aa87 <__strcasecmp_l_avx+0xc7> - 42aa80: 41 89 d0 mov %edx,%r8d - 42aa83: 91 xchg %eax,%ecx - 42aa84: 48 87 f7 xchg %rsi,%rdi - 42aa87: c5 f9 6f 17 vmovdqa (%rdi),%xmm2 - 42aa8b: c5 f9 6f 0e vmovdqa (%rsi),%xmm1 - 42aa8f: 4c 8d 48 0f lea 0xf(%rax),%r9 - 42aa93: 49 29 c9 sub %rcx,%r9 - 42aa96: 4c 8d 15 93 86 07 00 lea 0x78693(%rip),%r10 # 4a3130 - 42aa9d: 4f 63 0c 8a movslq (%r10,%r9,4),%r9 - 42aaa1: c5 f9 74 c1 vpcmpeqb %xmm1,%xmm0,%xmm0 - 42aaa5: 4f 8d 14 0a lea (%r10,%r9,1),%r10 - 42aaa9: 41 ff e2 jmpq *%r10 - 42aaac: 0f 1f 40 00 nopl 0x0(%rax) - 42aab0: c5 f9 6f 0e vmovdqa (%rsi),%xmm1 - 42aab4: c5 f9 74 c1 vpcmpeqb %xmm1,%xmm0,%xmm0 - 42aab8: c5 f9 6f 17 vmovdqa (%rdi),%xmm2 - 42aabc: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 - 42aac0: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 - 42aac4: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 - 42aac8: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 - 42aacc: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42aad0: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42aad5: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42aad9: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42aadd: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 - 42aae1: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 - 42aae5: c5 f1 74 ca vpcmpeqb %xmm2,%xmm1,%xmm1 - 42aae9: c5 f1 f8 c8 vpsubb %xmm0,%xmm1,%xmm1 - 42aaed: c5 79 d7 c9 vpmovmskb %xmm1,%r9d - 42aaf1: d3 ea shr %cl,%edx - 42aaf3: 41 d3 e9 shr %cl,%r9d - 42aaf6: 44 29 ca sub %r9d,%edx - 42aaf9: 0f 85 c9 14 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> - 42aaff: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42ab06: 49 c7 c1 10 00 00 00 mov $0x10,%r9 - 42ab0d: 48 89 ca mov %rcx,%rdx - 42ab10: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42ab15: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42ab1a: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42ab1e: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42ab22: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42ab26: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42ab2a: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42ab2e: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42ab33: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42ab37: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42ab3b: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42ab3f: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42ab43: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42ab49: 48 8d 52 10 lea 0x10(%rdx),%rdx - 42ab4d: 76 41 jbe 42ab90 <__strcasecmp_l_avx+0x1d0> - 42ab4f: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42ab54: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42ab59: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42ab5d: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42ab61: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42ab65: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42ab69: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42ab6d: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42ab72: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42ab76: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42ab7a: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42ab7e: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42ab82: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42ab88: 48 8d 52 10 lea 0x10(%rdx),%rdx - 42ab8c: 76 02 jbe 42ab90 <__strcasecmp_l_avx+0x1d0> - 42ab8e: eb 80 jmp 42ab10 <__strcasecmp_l_avx+0x150> - 42ab90: 0f 83 66 14 00 00 jae 42bffc <__strcasecmp_l_avx+0x163c> - 42ab96: 48 8d 4c 0a f0 lea -0x10(%rdx,%rcx,1),%rcx - 42ab9b: 0f b6 04 0f movzbl (%rdi,%rcx,1),%eax - 42ab9f: 0f b6 14 0e movzbl (%rsi,%rcx,1),%edx - 42aba3: 48 8d 0d 96 c9 07 00 lea 0x7c996(%rip),%rcx # 4a7540 <_nl_C_LC_CTYPE_tolower+0x200> - 42abaa: 8b 04 81 mov (%rcx,%rax,4),%eax - 42abad: 8b 14 91 mov (%rcx,%rdx,4),%edx - 42abb0: 29 d0 sub %edx,%eax - 42abb2: c3 retq - 42abb3: 0f 1f 00 nopl (%rax) - 42abb6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42abbd: 00 00 00 - 42abc0: c5 e9 73 fa 0f vpslldq $0xf,%xmm2,%xmm2 - 42abc5: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 - 42abc9: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 - 42abcd: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 - 42abd1: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 - 42abd5: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42abd9: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42abde: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42abe2: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42abe6: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 - 42abea: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 - 42abee: c5 e9 74 d1 vpcmpeqb %xmm1,%xmm2,%xmm2 - 42abf2: c5 e9 f8 d0 vpsubb %xmm0,%xmm2,%xmm2 - 42abf6: c5 79 d7 ca vpmovmskb %xmm2,%r9d - 42abfa: d3 ea shr %cl,%edx - 42abfc: 41 d3 e9 shr %cl,%r9d - 42abff: 44 29 ca sub %r9d,%edx - 42ac02: 0f 85 c0 13 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> - 42ac08: c5 f9 6f 1f vmovdqa (%rdi),%xmm3 - 42ac0c: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42ac13: 41 b9 01 00 00 00 mov $0x1,%r9d - 42ac19: 4c 8d 57 01 lea 0x1(%rdi),%r10 - 42ac1d: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42ac24: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42ac2b: 48 89 ca mov %rcx,%rdx - 42ac2e: 66 90 xchg %ax,%ax - 42ac30: 49 83 c2 10 add $0x10,%r10 - 42ac34: 0f 8f a6 00 00 00 jg 42ace0 <__strcasecmp_l_avx+0x320> - 42ac3a: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42ac3f: c4 e3 79 0f 44 17 f0 vpalignr $0x1,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 - 42ac46: 01 - 42ac47: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42ac4c: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42ac50: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42ac54: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42ac58: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42ac5c: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42ac60: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42ac65: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42ac69: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42ac6d: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42ac71: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42ac75: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42ac7b: 0f 86 1f 13 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> - 42ac81: 48 83 c2 10 add $0x10,%rdx - 42ac85: 49 83 c2 10 add $0x10,%r10 - 42ac89: 7f 55 jg 42ace0 <__strcasecmp_l_avx+0x320> - 42ac8b: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42ac90: c4 e3 79 0f 44 17 f0 vpalignr $0x1,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 - 42ac97: 01 - 42ac98: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42ac9d: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42aca1: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42aca5: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42aca9: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42acad: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42acb1: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42acb6: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42acba: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42acbe: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42acc2: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42acc6: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42accc: 0f 86 ce 12 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> - 42acd2: 48 83 c2 10 add $0x10,%rdx - 42acd6: e9 55 ff ff ff jmpq 42ac30 <__strcasecmp_l_avx+0x270> - 42acdb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 42ace0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42ace7: c5 f9 6f 44 17 f0 vmovdqa -0x10(%rdi,%rdx,1),%xmm0 - 42aced: c5 f9 73 d8 01 vpsrldq $0x1,%xmm0,%xmm0 - 42acf2: c4 e3 79 63 c0 3a vpcmpistri $0x3a,%xmm0,%xmm0 - 42acf8: 83 f9 0e cmp $0xe,%ecx - 42acfb: 0f 87 39 ff ff ff ja 42ac3a <__strcasecmp_l_avx+0x27a> - 42ad01: e9 5b 12 00 00 jmpq 42bf61 <__strcasecmp_l_avx+0x15a1> - 42ad06: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42ad0d: 00 00 00 - 42ad10: c5 e9 73 fa 0e vpslldq $0xe,%xmm2,%xmm2 - 42ad15: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 - 42ad19: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 - 42ad1d: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 - 42ad21: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 - 42ad25: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42ad29: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42ad2e: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42ad32: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42ad36: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 - 42ad3a: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 - 42ad3e: c5 e9 74 d1 vpcmpeqb %xmm1,%xmm2,%xmm2 - 42ad42: c5 e9 f8 d0 vpsubb %xmm0,%xmm2,%xmm2 - 42ad46: c5 79 d7 ca vpmovmskb %xmm2,%r9d - 42ad4a: d3 ea shr %cl,%edx - 42ad4c: 41 d3 e9 shr %cl,%r9d - 42ad4f: 44 29 ca sub %r9d,%edx - 42ad52: 0f 85 70 12 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> - 42ad58: c5 f9 6f 1f vmovdqa (%rdi),%xmm3 - 42ad5c: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42ad63: 41 b9 02 00 00 00 mov $0x2,%r9d - 42ad69: 4c 8d 57 02 lea 0x2(%rdi),%r10 - 42ad6d: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42ad74: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42ad7b: 48 89 ca mov %rcx,%rdx - 42ad7e: 66 90 xchg %ax,%ax - 42ad80: 49 83 c2 10 add $0x10,%r10 - 42ad84: 0f 8f a6 00 00 00 jg 42ae30 <__strcasecmp_l_avx+0x470> - 42ad8a: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42ad8f: c4 e3 79 0f 44 17 f0 vpalignr $0x2,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 - 42ad96: 02 - 42ad97: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42ad9c: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42ada0: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42ada4: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42ada8: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42adac: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42adb0: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42adb5: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42adb9: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42adbd: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42adc1: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42adc5: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42adcb: 0f 86 cf 11 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> - 42add1: 48 83 c2 10 add $0x10,%rdx - 42add5: 49 83 c2 10 add $0x10,%r10 - 42add9: 7f 55 jg 42ae30 <__strcasecmp_l_avx+0x470> - 42addb: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42ade0: c4 e3 79 0f 44 17 f0 vpalignr $0x2,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 - 42ade7: 02 - 42ade8: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42aded: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42adf1: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42adf5: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42adf9: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42adfd: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42ae01: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42ae06: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42ae0a: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42ae0e: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42ae12: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42ae16: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42ae1c: 0f 86 7e 11 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> - 42ae22: 48 83 c2 10 add $0x10,%rdx - 42ae26: e9 55 ff ff ff jmpq 42ad80 <__strcasecmp_l_avx+0x3c0> - 42ae2b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 42ae30: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42ae37: c5 f9 6f 44 17 f0 vmovdqa -0x10(%rdi,%rdx,1),%xmm0 - 42ae3d: c5 f9 73 d8 02 vpsrldq $0x2,%xmm0,%xmm0 - 42ae42: c4 e3 79 63 c0 3a vpcmpistri $0x3a,%xmm0,%xmm0 - 42ae48: 83 f9 0d cmp $0xd,%ecx - 42ae4b: 0f 87 39 ff ff ff ja 42ad8a <__strcasecmp_l_avx+0x3ca> - 42ae51: e9 0b 11 00 00 jmpq 42bf61 <__strcasecmp_l_avx+0x15a1> - 42ae56: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42ae5d: 00 00 00 - 42ae60: c5 e9 73 fa 0d vpslldq $0xd,%xmm2,%xmm2 - 42ae65: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 - 42ae69: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 - 42ae6d: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 - 42ae71: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 - 42ae75: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42ae79: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42ae7e: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42ae82: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42ae86: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 - 42ae8a: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 - 42ae8e: c5 e9 74 d1 vpcmpeqb %xmm1,%xmm2,%xmm2 - 42ae92: c5 e9 f8 d0 vpsubb %xmm0,%xmm2,%xmm2 - 42ae96: c5 79 d7 ca vpmovmskb %xmm2,%r9d - 42ae9a: d3 ea shr %cl,%edx - 42ae9c: 41 d3 e9 shr %cl,%r9d - 42ae9f: 44 29 ca sub %r9d,%edx - 42aea2: 0f 85 20 11 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> - 42aea8: c5 f9 6f 1f vmovdqa (%rdi),%xmm3 - 42aeac: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42aeb3: 41 b9 03 00 00 00 mov $0x3,%r9d - 42aeb9: 4c 8d 57 03 lea 0x3(%rdi),%r10 - 42aebd: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42aec4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42aecb: 48 89 ca mov %rcx,%rdx - 42aece: 49 83 c2 10 add $0x10,%r10 - 42aed2: 0f 8f a8 00 00 00 jg 42af80 <__strcasecmp_l_avx+0x5c0> - 42aed8: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42aedd: c4 e3 79 0f 44 17 f0 vpalignr $0x3,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 - 42aee4: 03 - 42aee5: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42aeea: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42aeee: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42aef2: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42aef6: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42aefa: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42aefe: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42af03: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42af07: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42af0b: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42af0f: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42af13: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42af19: 0f 86 81 10 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> - 42af1f: 48 83 c2 10 add $0x10,%rdx - 42af23: 49 83 c2 10 add $0x10,%r10 - 42af27: 7f 57 jg 42af80 <__strcasecmp_l_avx+0x5c0> - 42af29: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42af2e: c4 e3 79 0f 44 17 f0 vpalignr $0x3,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 - 42af35: 03 - 42af36: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42af3b: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42af3f: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42af43: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42af47: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42af4b: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42af4f: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42af54: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42af58: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42af5c: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42af60: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42af64: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42af6a: 0f 86 30 10 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> - 42af70: 48 83 c2 10 add $0x10,%rdx - 42af74: e9 55 ff ff ff jmpq 42aece <__strcasecmp_l_avx+0x50e> - 42af79: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 42af80: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42af87: c5 f9 6f 44 17 f0 vmovdqa -0x10(%rdi,%rdx,1),%xmm0 - 42af8d: c5 f9 73 d8 03 vpsrldq $0x3,%xmm0,%xmm0 - 42af92: c4 e3 79 63 c0 3a vpcmpistri $0x3a,%xmm0,%xmm0 - 42af98: 83 f9 0c cmp $0xc,%ecx - 42af9b: 0f 87 37 ff ff ff ja 42aed8 <__strcasecmp_l_avx+0x518> - 42afa1: e9 bb 0f 00 00 jmpq 42bf61 <__strcasecmp_l_avx+0x15a1> - 42afa6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42afad: 00 00 00 - 42afb0: c5 e9 73 fa 0c vpslldq $0xc,%xmm2,%xmm2 - 42afb5: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 - 42afb9: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 - 42afbd: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 - 42afc1: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 - 42afc5: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42afc9: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42afce: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42afd2: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42afd6: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 - 42afda: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 - 42afde: c5 e9 74 d1 vpcmpeqb %xmm1,%xmm2,%xmm2 - 42afe2: c5 e9 f8 d0 vpsubb %xmm0,%xmm2,%xmm2 - 42afe6: c5 79 d7 ca vpmovmskb %xmm2,%r9d - 42afea: d3 ea shr %cl,%edx - 42afec: 41 d3 e9 shr %cl,%r9d - 42afef: 44 29 ca sub %r9d,%edx - 42aff2: 0f 85 d0 0f 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> - 42aff8: c5 f9 6f 1f vmovdqa (%rdi),%xmm3 - 42affc: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42b003: 41 b9 04 00 00 00 mov $0x4,%r9d - 42b009: 4c 8d 57 04 lea 0x4(%rdi),%r10 - 42b00d: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42b014: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42b01b: 48 89 ca mov %rcx,%rdx - 42b01e: 66 90 xchg %ax,%ax - 42b020: 49 83 c2 10 add $0x10,%r10 - 42b024: 0f 8f a6 00 00 00 jg 42b0d0 <__strcasecmp_l_avx+0x710> - 42b02a: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42b02f: c4 e3 79 0f 44 17 f0 vpalignr $0x4,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 - 42b036: 04 - 42b037: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42b03c: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42b040: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42b044: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42b048: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42b04c: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42b050: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42b055: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42b059: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42b05d: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42b061: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42b065: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42b06b: 0f 86 2f 0f 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> - 42b071: 48 83 c2 10 add $0x10,%rdx - 42b075: 49 83 c2 10 add $0x10,%r10 - 42b079: 7f 55 jg 42b0d0 <__strcasecmp_l_avx+0x710> - 42b07b: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42b080: c4 e3 79 0f 44 17 f0 vpalignr $0x4,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 - 42b087: 04 - 42b088: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42b08d: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42b091: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42b095: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42b099: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42b09d: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42b0a1: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42b0a6: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42b0aa: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42b0ae: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42b0b2: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42b0b6: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42b0bc: 0f 86 de 0e 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> - 42b0c2: 48 83 c2 10 add $0x10,%rdx - 42b0c6: e9 55 ff ff ff jmpq 42b020 <__strcasecmp_l_avx+0x660> - 42b0cb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 42b0d0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42b0d7: c5 f9 6f 44 17 f0 vmovdqa -0x10(%rdi,%rdx,1),%xmm0 - 42b0dd: c5 f9 73 d8 04 vpsrldq $0x4,%xmm0,%xmm0 - 42b0e2: c4 e3 79 63 c0 3a vpcmpistri $0x3a,%xmm0,%xmm0 - 42b0e8: 83 f9 0b cmp $0xb,%ecx - 42b0eb: 0f 87 39 ff ff ff ja 42b02a <__strcasecmp_l_avx+0x66a> - 42b0f1: e9 6b 0e 00 00 jmpq 42bf61 <__strcasecmp_l_avx+0x15a1> - 42b0f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42b0fd: 00 00 00 - 42b100: c5 e9 73 fa 0b vpslldq $0xb,%xmm2,%xmm2 - 42b105: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 - 42b109: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 - 42b10d: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 - 42b111: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 - 42b115: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42b119: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42b11e: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42b122: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42b126: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 - 42b12a: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 - 42b12e: c5 e9 74 d1 vpcmpeqb %xmm1,%xmm2,%xmm2 - 42b132: c5 e9 f8 d0 vpsubb %xmm0,%xmm2,%xmm2 - 42b136: c5 79 d7 ca vpmovmskb %xmm2,%r9d - 42b13a: d3 ea shr %cl,%edx - 42b13c: 41 d3 e9 shr %cl,%r9d - 42b13f: 44 29 ca sub %r9d,%edx - 42b142: 0f 85 80 0e 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> - 42b148: c5 f9 6f 1f vmovdqa (%rdi),%xmm3 - 42b14c: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42b153: 41 b9 05 00 00 00 mov $0x5,%r9d - 42b159: 4c 8d 57 05 lea 0x5(%rdi),%r10 - 42b15d: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42b164: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42b16b: 48 89 ca mov %rcx,%rdx - 42b16e: 66 90 xchg %ax,%ax - 42b170: 49 83 c2 10 add $0x10,%r10 - 42b174: 0f 8f a6 00 00 00 jg 42b220 <__strcasecmp_l_avx+0x860> - 42b17a: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42b17f: c4 e3 79 0f 44 17 f0 vpalignr $0x5,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 - 42b186: 05 - 42b187: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42b18c: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42b190: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42b194: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42b198: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42b19c: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42b1a0: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42b1a5: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42b1a9: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42b1ad: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42b1b1: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42b1b5: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42b1bb: 0f 86 df 0d 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> - 42b1c1: 48 83 c2 10 add $0x10,%rdx - 42b1c5: 49 83 c2 10 add $0x10,%r10 - 42b1c9: 7f 55 jg 42b220 <__strcasecmp_l_avx+0x860> - 42b1cb: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42b1d0: c4 e3 79 0f 44 17 f0 vpalignr $0x5,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 - 42b1d7: 05 - 42b1d8: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42b1dd: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42b1e1: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42b1e5: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42b1e9: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42b1ed: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42b1f1: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42b1f6: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42b1fa: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42b1fe: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42b202: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42b206: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42b20c: 0f 86 8e 0d 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> - 42b212: 48 83 c2 10 add $0x10,%rdx - 42b216: e9 55 ff ff ff jmpq 42b170 <__strcasecmp_l_avx+0x7b0> - 42b21b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 42b220: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42b227: c5 f9 6f 44 17 f0 vmovdqa -0x10(%rdi,%rdx,1),%xmm0 - 42b22d: c5 f9 73 d8 05 vpsrldq $0x5,%xmm0,%xmm0 - 42b232: c4 e3 79 63 c0 3a vpcmpistri $0x3a,%xmm0,%xmm0 - 42b238: 83 f9 0a cmp $0xa,%ecx - 42b23b: 0f 87 39 ff ff ff ja 42b17a <__strcasecmp_l_avx+0x7ba> - 42b241: e9 1b 0d 00 00 jmpq 42bf61 <__strcasecmp_l_avx+0x15a1> - 42b246: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42b24d: 00 00 00 - 42b250: c5 e9 73 fa 0a vpslldq $0xa,%xmm2,%xmm2 - 42b255: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 - 42b259: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 - 42b25d: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 - 42b261: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 - 42b265: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42b269: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42b26e: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42b272: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42b276: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 - 42b27a: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 - 42b27e: c5 e9 74 d1 vpcmpeqb %xmm1,%xmm2,%xmm2 - 42b282: c5 e9 f8 d0 vpsubb %xmm0,%xmm2,%xmm2 - 42b286: c5 79 d7 ca vpmovmskb %xmm2,%r9d - 42b28a: d3 ea shr %cl,%edx - 42b28c: 41 d3 e9 shr %cl,%r9d - 42b28f: 44 29 ca sub %r9d,%edx - 42b292: 0f 85 30 0d 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> - 42b298: c5 f9 6f 1f vmovdqa (%rdi),%xmm3 - 42b29c: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42b2a3: 41 b9 06 00 00 00 mov $0x6,%r9d - 42b2a9: 4c 8d 57 06 lea 0x6(%rdi),%r10 - 42b2ad: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42b2b4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42b2bb: 48 89 ca mov %rcx,%rdx - 42b2be: 66 90 xchg %ax,%ax - 42b2c0: 49 83 c2 10 add $0x10,%r10 - 42b2c4: 0f 8f a6 00 00 00 jg 42b370 <__strcasecmp_l_avx+0x9b0> - 42b2ca: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42b2cf: c4 e3 79 0f 44 17 f0 vpalignr $0x6,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 - 42b2d6: 06 - 42b2d7: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42b2dc: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42b2e0: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42b2e4: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42b2e8: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42b2ec: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42b2f0: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42b2f5: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42b2f9: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42b2fd: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42b301: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42b305: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42b30b: 0f 86 8f 0c 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> - 42b311: 48 83 c2 10 add $0x10,%rdx - 42b315: 49 83 c2 10 add $0x10,%r10 - 42b319: 7f 55 jg 42b370 <__strcasecmp_l_avx+0x9b0> - 42b31b: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42b320: c4 e3 79 0f 44 17 f0 vpalignr $0x6,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 - 42b327: 06 - 42b328: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42b32d: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42b331: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42b335: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42b339: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42b33d: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42b341: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42b346: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42b34a: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42b34e: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42b352: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42b356: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42b35c: 0f 86 3e 0c 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> - 42b362: 48 83 c2 10 add $0x10,%rdx - 42b366: e9 55 ff ff ff jmpq 42b2c0 <__strcasecmp_l_avx+0x900> - 42b36b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 42b370: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42b377: c5 f9 6f 44 17 f0 vmovdqa -0x10(%rdi,%rdx,1),%xmm0 - 42b37d: c5 f9 73 d8 06 vpsrldq $0x6,%xmm0,%xmm0 - 42b382: c4 e3 79 63 c0 3a vpcmpistri $0x3a,%xmm0,%xmm0 - 42b388: 83 f9 09 cmp $0x9,%ecx - 42b38b: 0f 87 39 ff ff ff ja 42b2ca <__strcasecmp_l_avx+0x90a> - 42b391: e9 cb 0b 00 00 jmpq 42bf61 <__strcasecmp_l_avx+0x15a1> - 42b396: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42b39d: 00 00 00 - 42b3a0: c5 e9 73 fa 09 vpslldq $0x9,%xmm2,%xmm2 - 42b3a5: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 - 42b3a9: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 - 42b3ad: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 - 42b3b1: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 - 42b3b5: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42b3b9: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42b3be: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42b3c2: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42b3c6: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 - 42b3ca: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 - 42b3ce: c5 e9 74 d1 vpcmpeqb %xmm1,%xmm2,%xmm2 - 42b3d2: c5 e9 f8 d0 vpsubb %xmm0,%xmm2,%xmm2 - 42b3d6: c5 79 d7 ca vpmovmskb %xmm2,%r9d - 42b3da: d3 ea shr %cl,%edx - 42b3dc: 41 d3 e9 shr %cl,%r9d - 42b3df: 44 29 ca sub %r9d,%edx - 42b3e2: 0f 85 e0 0b 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> - 42b3e8: c5 f9 6f 1f vmovdqa (%rdi),%xmm3 - 42b3ec: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42b3f3: 41 b9 07 00 00 00 mov $0x7,%r9d - 42b3f9: 4c 8d 57 07 lea 0x7(%rdi),%r10 - 42b3fd: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42b404: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42b40b: 48 89 ca mov %rcx,%rdx - 42b40e: 66 90 xchg %ax,%ax - 42b410: 49 83 c2 10 add $0x10,%r10 - 42b414: 0f 8f a6 00 00 00 jg 42b4c0 <__strcasecmp_l_avx+0xb00> - 42b41a: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42b41f: c4 e3 79 0f 44 17 f0 vpalignr $0x7,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 - 42b426: 07 - 42b427: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42b42c: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42b430: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42b434: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42b438: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42b43c: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42b440: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42b445: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42b449: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42b44d: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42b451: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42b455: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42b45b: 0f 86 3f 0b 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> - 42b461: 48 83 c2 10 add $0x10,%rdx - 42b465: 49 83 c2 10 add $0x10,%r10 - 42b469: 7f 55 jg 42b4c0 <__strcasecmp_l_avx+0xb00> - 42b46b: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42b470: c4 e3 79 0f 44 17 f0 vpalignr $0x7,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 - 42b477: 07 - 42b478: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42b47d: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42b481: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42b485: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42b489: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42b48d: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42b491: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42b496: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42b49a: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42b49e: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42b4a2: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42b4a6: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42b4ac: 0f 86 ee 0a 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> - 42b4b2: 48 83 c2 10 add $0x10,%rdx - 42b4b6: e9 55 ff ff ff jmpq 42b410 <__strcasecmp_l_avx+0xa50> - 42b4bb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 42b4c0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42b4c7: c5 f9 6f 44 17 f0 vmovdqa -0x10(%rdi,%rdx,1),%xmm0 - 42b4cd: c5 f9 73 d8 07 vpsrldq $0x7,%xmm0,%xmm0 - 42b4d2: c4 e3 79 63 c0 3a vpcmpistri $0x3a,%xmm0,%xmm0 - 42b4d8: 83 f9 08 cmp $0x8,%ecx - 42b4db: 0f 87 39 ff ff ff ja 42b41a <__strcasecmp_l_avx+0xa5a> - 42b4e1: e9 7b 0a 00 00 jmpq 42bf61 <__strcasecmp_l_avx+0x15a1> - 42b4e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42b4ed: 00 00 00 - 42b4f0: c5 e9 73 fa 08 vpslldq $0x8,%xmm2,%xmm2 - 42b4f5: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 - 42b4f9: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 - 42b4fd: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 - 42b501: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 - 42b505: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42b509: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42b50e: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42b512: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42b516: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 - 42b51a: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 - 42b51e: c5 e9 74 d1 vpcmpeqb %xmm1,%xmm2,%xmm2 - 42b522: c5 e9 f8 d0 vpsubb %xmm0,%xmm2,%xmm2 - 42b526: c5 79 d7 ca vpmovmskb %xmm2,%r9d - 42b52a: d3 ea shr %cl,%edx - 42b52c: 41 d3 e9 shr %cl,%r9d - 42b52f: 44 29 ca sub %r9d,%edx - 42b532: 0f 85 90 0a 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> - 42b538: c5 f9 6f 1f vmovdqa (%rdi),%xmm3 - 42b53c: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42b543: 41 b9 08 00 00 00 mov $0x8,%r9d - 42b549: 4c 8d 57 08 lea 0x8(%rdi),%r10 - 42b54d: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42b554: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42b55b: 48 89 ca mov %rcx,%rdx - 42b55e: 66 90 xchg %ax,%ax - 42b560: 49 83 c2 10 add $0x10,%r10 - 42b564: 0f 8f a6 00 00 00 jg 42b610 <__strcasecmp_l_avx+0xc50> - 42b56a: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42b56f: c4 e3 79 0f 44 17 f0 vpalignr $0x8,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 - 42b576: 08 - 42b577: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42b57c: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42b580: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42b584: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42b588: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42b58c: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42b590: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42b595: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42b599: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42b59d: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42b5a1: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42b5a5: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42b5ab: 0f 86 ef 09 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> - 42b5b1: 48 83 c2 10 add $0x10,%rdx - 42b5b5: 49 83 c2 10 add $0x10,%r10 - 42b5b9: 7f 55 jg 42b610 <__strcasecmp_l_avx+0xc50> - 42b5bb: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42b5c0: c4 e3 79 0f 44 17 f0 vpalignr $0x8,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 - 42b5c7: 08 - 42b5c8: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42b5cd: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42b5d1: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42b5d5: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42b5d9: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42b5dd: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42b5e1: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42b5e6: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42b5ea: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42b5ee: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42b5f2: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42b5f6: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42b5fc: 0f 86 9e 09 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> - 42b602: 48 83 c2 10 add $0x10,%rdx - 42b606: e9 55 ff ff ff jmpq 42b560 <__strcasecmp_l_avx+0xba0> - 42b60b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 42b610: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42b617: c5 f9 6f 44 17 f0 vmovdqa -0x10(%rdi,%rdx,1),%xmm0 - 42b61d: c5 f9 73 d8 08 vpsrldq $0x8,%xmm0,%xmm0 - 42b622: c4 e3 79 63 c0 3a vpcmpistri $0x3a,%xmm0,%xmm0 - 42b628: 83 f9 07 cmp $0x7,%ecx - 42b62b: 0f 87 39 ff ff ff ja 42b56a <__strcasecmp_l_avx+0xbaa> - 42b631: e9 2b 09 00 00 jmpq 42bf61 <__strcasecmp_l_avx+0x15a1> - 42b636: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42b63d: 00 00 00 - 42b640: c5 e9 73 fa 07 vpslldq $0x7,%xmm2,%xmm2 - 42b645: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 - 42b649: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 - 42b64d: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 - 42b651: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 - 42b655: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42b659: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42b65e: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42b662: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42b666: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 - 42b66a: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 - 42b66e: c5 e9 74 d1 vpcmpeqb %xmm1,%xmm2,%xmm2 - 42b672: c5 e9 f8 d0 vpsubb %xmm0,%xmm2,%xmm2 - 42b676: c5 79 d7 ca vpmovmskb %xmm2,%r9d - 42b67a: d3 ea shr %cl,%edx - 42b67c: 41 d3 e9 shr %cl,%r9d - 42b67f: 44 29 ca sub %r9d,%edx - 42b682: 0f 85 40 09 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> - 42b688: c5 f9 6f 1f vmovdqa (%rdi),%xmm3 - 42b68c: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42b693: 41 b9 09 00 00 00 mov $0x9,%r9d - 42b699: 4c 8d 57 09 lea 0x9(%rdi),%r10 - 42b69d: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42b6a4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42b6ab: 48 89 ca mov %rcx,%rdx - 42b6ae: 66 90 xchg %ax,%ax - 42b6b0: 49 83 c2 10 add $0x10,%r10 - 42b6b4: 0f 8f a6 00 00 00 jg 42b760 <__strcasecmp_l_avx+0xda0> - 42b6ba: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42b6bf: c4 e3 79 0f 44 17 f0 vpalignr $0x9,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 - 42b6c6: 09 - 42b6c7: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42b6cc: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42b6d0: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42b6d4: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42b6d8: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42b6dc: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42b6e0: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42b6e5: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42b6e9: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42b6ed: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42b6f1: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42b6f5: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42b6fb: 0f 86 9f 08 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> - 42b701: 48 83 c2 10 add $0x10,%rdx - 42b705: 49 83 c2 10 add $0x10,%r10 - 42b709: 7f 55 jg 42b760 <__strcasecmp_l_avx+0xda0> - 42b70b: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42b710: c4 e3 79 0f 44 17 f0 vpalignr $0x9,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 - 42b717: 09 - 42b718: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42b71d: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42b721: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42b725: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42b729: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42b72d: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42b731: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42b736: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42b73a: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42b73e: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42b742: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42b746: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42b74c: 0f 86 4e 08 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> - 42b752: 48 83 c2 10 add $0x10,%rdx - 42b756: e9 55 ff ff ff jmpq 42b6b0 <__strcasecmp_l_avx+0xcf0> - 42b75b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 42b760: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42b767: c5 f9 6f 44 17 f0 vmovdqa -0x10(%rdi,%rdx,1),%xmm0 - 42b76d: c5 f9 73 d8 09 vpsrldq $0x9,%xmm0,%xmm0 - 42b772: c4 e3 79 63 c0 3a vpcmpistri $0x3a,%xmm0,%xmm0 - 42b778: 83 f9 06 cmp $0x6,%ecx - 42b77b: 0f 87 39 ff ff ff ja 42b6ba <__strcasecmp_l_avx+0xcfa> - 42b781: e9 db 07 00 00 jmpq 42bf61 <__strcasecmp_l_avx+0x15a1> - 42b786: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42b78d: 00 00 00 - 42b790: c5 e9 73 fa 06 vpslldq $0x6,%xmm2,%xmm2 - 42b795: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 - 42b799: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 - 42b79d: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 - 42b7a1: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 - 42b7a5: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42b7a9: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42b7ae: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42b7b2: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42b7b6: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 - 42b7ba: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 - 42b7be: c5 e9 74 d1 vpcmpeqb %xmm1,%xmm2,%xmm2 - 42b7c2: c5 e9 f8 d0 vpsubb %xmm0,%xmm2,%xmm2 - 42b7c6: c5 79 d7 ca vpmovmskb %xmm2,%r9d - 42b7ca: d3 ea shr %cl,%edx - 42b7cc: 41 d3 e9 shr %cl,%r9d - 42b7cf: 44 29 ca sub %r9d,%edx - 42b7d2: 0f 85 f0 07 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> - 42b7d8: c5 f9 6f 1f vmovdqa (%rdi),%xmm3 - 42b7dc: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42b7e3: 41 b9 0a 00 00 00 mov $0xa,%r9d - 42b7e9: 4c 8d 57 0a lea 0xa(%rdi),%r10 - 42b7ed: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42b7f4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42b7fb: 48 89 ca mov %rcx,%rdx - 42b7fe: 66 90 xchg %ax,%ax - 42b800: 49 83 c2 10 add $0x10,%r10 - 42b804: 0f 8f a6 00 00 00 jg 42b8b0 <__strcasecmp_l_avx+0xef0> - 42b80a: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42b80f: c4 e3 79 0f 44 17 f0 vpalignr $0xa,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 - 42b816: 0a - 42b817: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42b81c: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42b820: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42b824: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42b828: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42b82c: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42b830: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42b835: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42b839: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42b83d: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42b841: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42b845: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42b84b: 0f 86 4f 07 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> - 42b851: 48 83 c2 10 add $0x10,%rdx - 42b855: 49 83 c2 10 add $0x10,%r10 - 42b859: 7f 55 jg 42b8b0 <__strcasecmp_l_avx+0xef0> - 42b85b: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42b860: c4 e3 79 0f 44 17 f0 vpalignr $0xa,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 - 42b867: 0a - 42b868: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42b86d: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42b871: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42b875: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42b879: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42b87d: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42b881: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42b886: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42b88a: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42b88e: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42b892: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42b896: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42b89c: 0f 86 fe 06 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> - 42b8a2: 48 83 c2 10 add $0x10,%rdx - 42b8a6: e9 55 ff ff ff jmpq 42b800 <__strcasecmp_l_avx+0xe40> - 42b8ab: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 42b8b0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42b8b7: c5 f9 6f 44 17 f0 vmovdqa -0x10(%rdi,%rdx,1),%xmm0 - 42b8bd: c5 f9 73 d8 0a vpsrldq $0xa,%xmm0,%xmm0 - 42b8c2: c4 e3 79 63 c0 3a vpcmpistri $0x3a,%xmm0,%xmm0 - 42b8c8: 83 f9 05 cmp $0x5,%ecx - 42b8cb: 0f 87 39 ff ff ff ja 42b80a <__strcasecmp_l_avx+0xe4a> - 42b8d1: e9 8b 06 00 00 jmpq 42bf61 <__strcasecmp_l_avx+0x15a1> - 42b8d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42b8dd: 00 00 00 - 42b8e0: c5 e9 73 fa 05 vpslldq $0x5,%xmm2,%xmm2 - 42b8e5: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 - 42b8e9: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 - 42b8ed: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 - 42b8f1: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 - 42b8f5: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42b8f9: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42b8fe: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42b902: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42b906: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 - 42b90a: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 - 42b90e: c5 e9 74 d1 vpcmpeqb %xmm1,%xmm2,%xmm2 - 42b912: c5 e9 f8 d0 vpsubb %xmm0,%xmm2,%xmm2 - 42b916: c5 79 d7 ca vpmovmskb %xmm2,%r9d - 42b91a: d3 ea shr %cl,%edx - 42b91c: 41 d3 e9 shr %cl,%r9d - 42b91f: 44 29 ca sub %r9d,%edx - 42b922: 0f 85 a0 06 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> - 42b928: c5 f9 6f 1f vmovdqa (%rdi),%xmm3 - 42b92c: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42b933: 41 b9 0b 00 00 00 mov $0xb,%r9d - 42b939: 4c 8d 57 0b lea 0xb(%rdi),%r10 - 42b93d: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42b944: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42b94b: 48 89 ca mov %rcx,%rdx - 42b94e: 66 90 xchg %ax,%ax - 42b950: 49 83 c2 10 add $0x10,%r10 - 42b954: 0f 8f a6 00 00 00 jg 42ba00 <__strcasecmp_l_avx+0x1040> - 42b95a: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42b95f: c4 e3 79 0f 44 17 f0 vpalignr $0xb,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 - 42b966: 0b - 42b967: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42b96c: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42b970: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42b974: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42b978: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42b97c: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42b980: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42b985: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42b989: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42b98d: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42b991: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42b995: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42b99b: 0f 86 ff 05 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> - 42b9a1: 48 83 c2 10 add $0x10,%rdx - 42b9a5: 49 83 c2 10 add $0x10,%r10 - 42b9a9: 7f 55 jg 42ba00 <__strcasecmp_l_avx+0x1040> - 42b9ab: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42b9b0: c4 e3 79 0f 44 17 f0 vpalignr $0xb,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 - 42b9b7: 0b - 42b9b8: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42b9bd: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42b9c1: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42b9c5: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42b9c9: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42b9cd: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42b9d1: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42b9d6: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42b9da: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42b9de: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42b9e2: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42b9e6: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42b9ec: 0f 86 ae 05 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> - 42b9f2: 48 83 c2 10 add $0x10,%rdx - 42b9f6: e9 55 ff ff ff jmpq 42b950 <__strcasecmp_l_avx+0xf90> - 42b9fb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 42ba00: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42ba07: c5 f9 6f 44 17 f0 vmovdqa -0x10(%rdi,%rdx,1),%xmm0 - 42ba0d: c5 f9 73 d8 0b vpsrldq $0xb,%xmm0,%xmm0 - 42ba12: c4 e3 79 63 c0 3a vpcmpistri $0x3a,%xmm0,%xmm0 - 42ba18: 83 f9 04 cmp $0x4,%ecx - 42ba1b: 0f 87 39 ff ff ff ja 42b95a <__strcasecmp_l_avx+0xf9a> - 42ba21: e9 3b 05 00 00 jmpq 42bf61 <__strcasecmp_l_avx+0x15a1> - 42ba26: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42ba2d: 00 00 00 - 42ba30: c5 e9 73 fa 04 vpslldq $0x4,%xmm2,%xmm2 - 42ba35: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 - 42ba39: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 - 42ba3d: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 - 42ba41: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 - 42ba45: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42ba49: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42ba4e: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42ba52: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42ba56: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 - 42ba5a: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 - 42ba5e: c5 e9 74 d1 vpcmpeqb %xmm1,%xmm2,%xmm2 - 42ba62: c5 e9 f8 d0 vpsubb %xmm0,%xmm2,%xmm2 - 42ba66: c5 79 d7 ca vpmovmskb %xmm2,%r9d - 42ba6a: d3 ea shr %cl,%edx - 42ba6c: 41 d3 e9 shr %cl,%r9d - 42ba6f: 44 29 ca sub %r9d,%edx - 42ba72: 0f 85 50 05 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> - 42ba78: c5 f9 6f 1f vmovdqa (%rdi),%xmm3 - 42ba7c: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42ba83: 41 b9 0c 00 00 00 mov $0xc,%r9d - 42ba89: 4c 8d 57 0c lea 0xc(%rdi),%r10 - 42ba8d: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42ba94: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42ba9b: 48 89 ca mov %rcx,%rdx - 42ba9e: 66 90 xchg %ax,%ax - 42baa0: 49 83 c2 10 add $0x10,%r10 - 42baa4: 0f 8f a6 00 00 00 jg 42bb50 <__strcasecmp_l_avx+0x1190> - 42baaa: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42baaf: c4 e3 79 0f 44 17 f0 vpalignr $0xc,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 - 42bab6: 0c - 42bab7: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42babc: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42bac0: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42bac4: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42bac8: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42bacc: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42bad0: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42bad5: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42bad9: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42badd: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42bae1: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42bae5: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42baeb: 0f 86 af 04 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> - 42baf1: 48 83 c2 10 add $0x10,%rdx - 42baf5: 49 83 c2 10 add $0x10,%r10 - 42baf9: 7f 55 jg 42bb50 <__strcasecmp_l_avx+0x1190> - 42bafb: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42bb00: c4 e3 79 0f 44 17 f0 vpalignr $0xc,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 - 42bb07: 0c - 42bb08: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42bb0d: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42bb11: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42bb15: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42bb19: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42bb1d: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42bb21: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42bb26: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42bb2a: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42bb2e: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42bb32: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42bb36: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42bb3c: 0f 86 5e 04 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> - 42bb42: 48 83 c2 10 add $0x10,%rdx - 42bb46: e9 55 ff ff ff jmpq 42baa0 <__strcasecmp_l_avx+0x10e0> - 42bb4b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 42bb50: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42bb57: c5 f9 6f 44 17 f0 vmovdqa -0x10(%rdi,%rdx,1),%xmm0 - 42bb5d: c5 f9 73 d8 0c vpsrldq $0xc,%xmm0,%xmm0 - 42bb62: c4 e3 79 63 c0 3a vpcmpistri $0x3a,%xmm0,%xmm0 - 42bb68: 83 f9 03 cmp $0x3,%ecx - 42bb6b: 0f 87 39 ff ff ff ja 42baaa <__strcasecmp_l_avx+0x10ea> - 42bb71: e9 eb 03 00 00 jmpq 42bf61 <__strcasecmp_l_avx+0x15a1> - 42bb76: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42bb7d: 00 00 00 - 42bb80: c5 e9 73 fa 03 vpslldq $0x3,%xmm2,%xmm2 - 42bb85: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 - 42bb89: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 - 42bb8d: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 - 42bb91: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 - 42bb95: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42bb99: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42bb9e: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42bba2: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42bba6: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 - 42bbaa: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 - 42bbae: c5 e9 74 d1 vpcmpeqb %xmm1,%xmm2,%xmm2 - 42bbb2: c5 e9 f8 d0 vpsubb %xmm0,%xmm2,%xmm2 - 42bbb6: c5 79 d7 ca vpmovmskb %xmm2,%r9d - 42bbba: d3 ea shr %cl,%edx - 42bbbc: 41 d3 e9 shr %cl,%r9d - 42bbbf: 44 29 ca sub %r9d,%edx - 42bbc2: 0f 85 00 04 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> - 42bbc8: c5 f9 6f 1f vmovdqa (%rdi),%xmm3 - 42bbcc: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42bbd3: 41 b9 0d 00 00 00 mov $0xd,%r9d - 42bbd9: 4c 8d 57 0d lea 0xd(%rdi),%r10 - 42bbdd: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42bbe4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42bbeb: 48 89 ca mov %rcx,%rdx - 42bbee: 66 90 xchg %ax,%ax - 42bbf0: 49 83 c2 10 add $0x10,%r10 - 42bbf4: 0f 8f a6 00 00 00 jg 42bca0 <__strcasecmp_l_avx+0x12e0> - 42bbfa: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42bbff: c4 e3 79 0f 44 17 f0 vpalignr $0xd,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 - 42bc06: 0d - 42bc07: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42bc0c: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42bc10: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42bc14: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42bc18: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42bc1c: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42bc20: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42bc25: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42bc29: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42bc2d: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42bc31: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42bc35: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42bc3b: 0f 86 5f 03 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> - 42bc41: 48 83 c2 10 add $0x10,%rdx - 42bc45: 49 83 c2 10 add $0x10,%r10 - 42bc49: 7f 55 jg 42bca0 <__strcasecmp_l_avx+0x12e0> - 42bc4b: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42bc50: c4 e3 79 0f 44 17 f0 vpalignr $0xd,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 - 42bc57: 0d - 42bc58: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42bc5d: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42bc61: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42bc65: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42bc69: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42bc6d: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42bc71: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42bc76: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42bc7a: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42bc7e: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42bc82: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42bc86: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42bc8c: 0f 86 0e 03 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> - 42bc92: 48 83 c2 10 add $0x10,%rdx - 42bc96: e9 55 ff ff ff jmpq 42bbf0 <__strcasecmp_l_avx+0x1230> - 42bc9b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 42bca0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42bca7: c5 f9 6f 44 17 f0 vmovdqa -0x10(%rdi,%rdx,1),%xmm0 - 42bcad: c5 f9 73 d8 0d vpsrldq $0xd,%xmm0,%xmm0 - 42bcb2: c4 e3 79 63 c0 3a vpcmpistri $0x3a,%xmm0,%xmm0 - 42bcb8: 83 f9 02 cmp $0x2,%ecx - 42bcbb: 0f 87 39 ff ff ff ja 42bbfa <__strcasecmp_l_avx+0x123a> - 42bcc1: e9 9b 02 00 00 jmpq 42bf61 <__strcasecmp_l_avx+0x15a1> - 42bcc6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42bccd: 00 00 00 - 42bcd0: c5 e9 73 fa 02 vpslldq $0x2,%xmm2,%xmm2 - 42bcd5: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 - 42bcd9: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 - 42bcdd: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 - 42bce1: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 - 42bce5: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42bce9: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42bcee: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42bcf2: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42bcf6: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 - 42bcfa: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 - 42bcfe: c5 e9 74 d1 vpcmpeqb %xmm1,%xmm2,%xmm2 - 42bd02: c5 e9 f8 d0 vpsubb %xmm0,%xmm2,%xmm2 - 42bd06: c5 79 d7 ca vpmovmskb %xmm2,%r9d - 42bd0a: d3 ea shr %cl,%edx - 42bd0c: 41 d3 e9 shr %cl,%r9d - 42bd0f: 44 29 ca sub %r9d,%edx - 42bd12: 0f 85 b0 02 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> - 42bd18: c5 f9 6f 1f vmovdqa (%rdi),%xmm3 - 42bd1c: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42bd23: 41 b9 0e 00 00 00 mov $0xe,%r9d - 42bd29: 4c 8d 57 0e lea 0xe(%rdi),%r10 - 42bd2d: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42bd34: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42bd3b: 48 89 ca mov %rcx,%rdx - 42bd3e: 66 90 xchg %ax,%ax - 42bd40: 49 83 c2 10 add $0x10,%r10 - 42bd44: 0f 8f a6 00 00 00 jg 42bdf0 <__strcasecmp_l_avx+0x1430> - 42bd4a: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42bd4f: c4 e3 79 0f 44 17 f0 vpalignr $0xe,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 - 42bd56: 0e - 42bd57: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42bd5c: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42bd60: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42bd64: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42bd68: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42bd6c: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42bd70: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42bd75: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42bd79: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42bd7d: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42bd81: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42bd85: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42bd8b: 0f 86 0f 02 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> - 42bd91: 48 83 c2 10 add $0x10,%rdx - 42bd95: 49 83 c2 10 add $0x10,%r10 - 42bd99: 7f 55 jg 42bdf0 <__strcasecmp_l_avx+0x1430> - 42bd9b: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42bda0: c4 e3 79 0f 44 17 f0 vpalignr $0xe,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 - 42bda7: 0e - 42bda8: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42bdad: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42bdb1: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42bdb5: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42bdb9: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42bdbd: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42bdc1: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42bdc6: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42bdca: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42bdce: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42bdd2: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42bdd6: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42bddc: 0f 86 be 01 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> - 42bde2: 48 83 c2 10 add $0x10,%rdx - 42bde6: e9 55 ff ff ff jmpq 42bd40 <__strcasecmp_l_avx+0x1380> - 42bdeb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 42bdf0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42bdf7: c5 f9 6f 44 17 f0 vmovdqa -0x10(%rdi,%rdx,1),%xmm0 - 42bdfd: c5 f9 73 d8 0e vpsrldq $0xe,%xmm0,%xmm0 - 42be02: c4 e3 79 63 c0 3a vpcmpistri $0x3a,%xmm0,%xmm0 - 42be08: 83 f9 01 cmp $0x1,%ecx - 42be0b: 0f 87 39 ff ff ff ja 42bd4a <__strcasecmp_l_avx+0x138a> - 42be11: e9 4b 01 00 00 jmpq 42bf61 <__strcasecmp_l_avx+0x15a1> - 42be16: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42be1d: 00 00 00 - 42be20: c5 e9 73 fa 01 vpslldq $0x1,%xmm2,%xmm2 - 42be25: c5 f1 64 fc vpcmpgtb %xmm4,%xmm1,%xmm7 - 42be29: c5 71 64 c5 vpcmpgtb %xmm5,%xmm1,%xmm8 - 42be2d: c5 69 64 cc vpcmpgtb %xmm4,%xmm2,%xmm9 - 42be31: c5 69 64 d5 vpcmpgtb %xmm5,%xmm2,%xmm10 - 42be35: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42be39: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42be3e: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42be42: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42be46: c5 b9 eb c9 vpor %xmm1,%xmm8,%xmm1 - 42be4a: c5 a9 eb d2 vpor %xmm2,%xmm10,%xmm2 - 42be4e: c5 e9 74 d1 vpcmpeqb %xmm1,%xmm2,%xmm2 - 42be52: c5 e9 f8 d0 vpsubb %xmm0,%xmm2,%xmm2 - 42be56: c5 79 d7 ca vpmovmskb %xmm2,%r9d - 42be5a: d3 ea shr %cl,%edx - 42be5c: 41 d3 e9 shr %cl,%r9d - 42be5f: 44 29 ca sub %r9d,%edx - 42be62: 0f 85 60 01 00 00 jne 42bfc8 <__strcasecmp_l_avx+0x1608> - 42be68: c5 f9 6f 1f vmovdqa (%rdi),%xmm3 - 42be6c: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42be73: 41 b9 0f 00 00 00 mov $0xf,%r9d - 42be79: 4c 8d 57 0f lea 0xf(%rdi),%r10 - 42be7d: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42be84: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42be8b: 48 89 ca mov %rcx,%rdx - 42be8e: 66 90 xchg %ax,%ax - 42be90: 49 83 c2 10 add $0x10,%r10 - 42be94: 0f 8f a6 00 00 00 jg 42bf40 <__strcasecmp_l_avx+0x1580> - 42be9a: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42be9f: c4 e3 79 0f 44 17 f0 vpalignr $0xf,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 - 42bea6: 0f - 42bea7: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42beac: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42beb0: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42beb4: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42beb8: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42bebc: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42bec0: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42bec5: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42bec9: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42becd: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42bed1: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42bed5: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42bedb: 0f 86 bf 00 00 00 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> - 42bee1: 48 83 c2 10 add $0x10,%rdx - 42bee5: 49 83 c2 10 add $0x10,%r10 - 42bee9: 7f 55 jg 42bf40 <__strcasecmp_l_avx+0x1580> - 42beeb: c5 f9 6f 04 17 vmovdqa (%rdi,%rdx,1),%xmm0 - 42bef0: c4 e3 79 0f 44 17 f0 vpalignr $0xf,-0x10(%rdi,%rdx,1),%xmm0,%xmm0 - 42bef7: 0f - 42bef8: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42befd: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42bf01: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42bf05: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42bf09: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42bf0d: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42bf11: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42bf16: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42bf1a: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42bf1e: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42bf22: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42bf26: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42bf2c: 76 72 jbe 42bfa0 <__strcasecmp_l_avx+0x15e0> - 42bf2e: 48 83 c2 10 add $0x10,%rdx - 42bf32: e9 59 ff ff ff jmpq 42be90 <__strcasecmp_l_avx+0x14d0> - 42bf37: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 42bf3e: 00 00 - 42bf40: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42bf47: c5 f9 6f 44 17 f0 vmovdqa -0x10(%rdi,%rdx,1),%xmm0 - 42bf4d: c5 f9 73 d8 0f vpsrldq $0xf,%xmm0,%xmm0 - 42bf52: c4 e3 79 63 c0 3a vpcmpistri $0x3a,%xmm0,%xmm0 - 42bf58: 83 f9 00 cmp $0x0,%ecx - 42bf5b: 0f 87 39 ff ff ff ja 42be9a <__strcasecmp_l_avx+0x14da> - 42bf61: c5 f9 6f 0c 16 vmovdqa (%rsi,%rdx,1),%xmm1 - 42bf66: c5 f9 64 fc vpcmpgtb %xmm4,%xmm0,%xmm7 - 42bf6a: c5 79 64 c5 vpcmpgtb %xmm5,%xmm0,%xmm8 - 42bf6e: c5 71 64 cc vpcmpgtb %xmm4,%xmm1,%xmm9 - 42bf72: c5 71 64 d5 vpcmpgtb %xmm5,%xmm1,%xmm10 - 42bf76: c5 39 df c7 vpandn %xmm7,%xmm8,%xmm8 - 42bf7a: c4 41 29 df d1 vpandn %xmm9,%xmm10,%xmm10 - 42bf7f: c5 39 db c6 vpand %xmm6,%xmm8,%xmm8 - 42bf83: c5 29 db d6 vpand %xmm6,%xmm10,%xmm10 - 42bf87: c5 b9 eb c0 vpor %xmm0,%xmm8,%xmm0 - 42bf8b: c5 a9 eb c9 vpor %xmm1,%xmm10,%xmm1 - 42bf8f: c4 e3 79 63 c1 1a vpcmpistri $0x1a,%xmm1,%xmm0 - 42bf95: 90 nop - 42bf96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42bf9d: 00 00 00 - 42bfa0: 73 5a jae 42bffc <__strcasecmp_l_avx+0x163c> - 42bfa2: 48 01 ca add %rcx,%rdx - 42bfa5: 4a 8d 7c 0f f0 lea -0x10(%rdi,%r9,1),%rdi - 42bfaa: 0f b6 04 17 movzbl (%rdi,%rdx,1),%eax - 42bfae: 0f b6 14 16 movzbl (%rsi,%rdx,1),%edx - 42bfb2: 45 85 c0 test %r8d,%r8d - 42bfb5: 74 01 je 42bfb8 <__strcasecmp_l_avx+0x15f8> - 42bfb7: 92 xchg %eax,%edx - 42bfb8: 48 8d 0d 81 b5 07 00 lea 0x7b581(%rip),%rcx # 4a7540 <_nl_C_LC_CTYPE_tolower+0x200> - 42bfbf: 8b 14 91 mov (%rcx,%rdx,4),%edx - 42bfc2: 8b 04 81 mov (%rcx,%rax,4),%eax - 42bfc5: 29 d0 sub %edx,%eax - 42bfc7: c3 retq - 42bfc8: 48 8d 3c 07 lea (%rdi,%rax,1),%rdi - 42bfcc: 48 8d 34 0e lea (%rsi,%rcx,1),%rsi - 42bfd0: 45 85 c0 test %r8d,%r8d - 42bfd3: 74 0b je 42bfe0 <__strcasecmp_l_avx+0x1620> - 42bfd5: 48 87 f7 xchg %rsi,%rdi - 42bfd8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 42bfdf: 00 - 42bfe0: 48 0f bc d2 bsf %rdx,%rdx - 42bfe4: 0f b6 0c 16 movzbl (%rsi,%rdx,1),%ecx - 42bfe8: 0f b6 04 17 movzbl (%rdi,%rdx,1),%eax - 42bfec: 48 8d 15 4d b5 07 00 lea 0x7b54d(%rip),%rdx # 4a7540 <_nl_C_LC_CTYPE_tolower+0x200> - 42bff3: 8b 0c 8a mov (%rdx,%rcx,4),%ecx - 42bff6: 8b 04 82 mov (%rdx,%rax,4),%eax - 42bff9: 29 c8 sub %ecx,%eax - 42bffb: c3 retq - 42bffc: 31 c0 xor %eax,%eax - 42bffe: c3 retq - 42bfff: 90 nop - 42c000: 0f b6 0e movzbl (%rsi),%ecx - 42c003: 0f b6 07 movzbl (%rdi),%eax - 42c006: 48 8d 15 33 b5 07 00 lea 0x7b533(%rip),%rdx # 4a7540 <_nl_C_LC_CTYPE_tolower+0x200> - 42c00d: 8b 0c 8a mov (%rdx,%rcx,4),%ecx - 42c010: 8b 04 82 mov (%rdx,%rax,4),%eax - 42c013: 29 c8 sub %ecx,%eax - 42c015: c3 retq - 42c016: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42c01d: 00 00 00 - -000000000042c020 : - 42c020: 48 83 fa 20 cmp $0x20,%rdx - 42c024: 48 89 f8 mov %rdi,%rax - 42c027: 73 77 jae 42c0a0 - 42c029: f6 c2 01 test $0x1,%dl - 42c02c: 74 0b je 42c039 - 42c02e: 0f b6 0e movzbl (%rsi),%ecx - 42c031: 88 0f mov %cl,(%rdi) - 42c033: 48 ff c6 inc %rsi - 42c036: 48 ff c7 inc %rdi - 42c039: f6 c2 02 test $0x2,%dl - 42c03c: 74 12 je 42c050 - 42c03e: 0f b7 0e movzwl (%rsi),%ecx - 42c041: 66 89 0f mov %cx,(%rdi) - 42c044: 48 83 c6 02 add $0x2,%rsi - 42c048: 48 83 c7 02 add $0x2,%rdi - 42c04c: 0f 1f 40 00 nopl 0x0(%rax) - 42c050: f6 c2 04 test $0x4,%dl - 42c053: 74 0c je 42c061 - 42c055: 8b 0e mov (%rsi),%ecx - 42c057: 89 0f mov %ecx,(%rdi) - 42c059: 48 83 c6 04 add $0x4,%rsi - 42c05d: 48 83 c7 04 add $0x4,%rdi - 42c061: f6 c2 08 test $0x8,%dl - 42c064: 74 0e je 42c074 - 42c066: 48 8b 0e mov (%rsi),%rcx - 42c069: 48 89 0f mov %rcx,(%rdi) - 42c06c: 48 83 c6 08 add $0x8,%rsi - 42c070: 48 83 c7 08 add $0x8,%rdi - 42c074: 81 e2 f0 00 00 00 and $0xf0,%edx - 42c07a: 74 1f je 42c09b - 42c07c: 0f 1f 40 00 nopl 0x0(%rax) - 42c080: 48 8b 0e mov (%rsi),%rcx - 42c083: 4c 8b 46 08 mov 0x8(%rsi),%r8 - 42c087: 48 89 0f mov %rcx,(%rdi) - 42c08a: 4c 89 47 08 mov %r8,0x8(%rdi) - 42c08e: 83 ea 10 sub $0x10,%edx - 42c091: 48 8d 76 10 lea 0x10(%rsi),%rsi - 42c095: 48 8d 7f 10 lea 0x10(%rdi),%rdi - 42c099: 75 e5 jne 42c080 - 42c09b: f3 c3 repz retq - 42c09d: 0f 1f 00 nopl (%rax) - 42c0a0: 48 89 44 24 f8 mov %rax,-0x8(%rsp) - 42c0a5: 89 f1 mov %esi,%ecx - 42c0a7: 83 e1 07 and $0x7,%ecx - 42c0aa: 74 34 je 42c0e0 - 42c0ac: 48 8d 54 11 f8 lea -0x8(%rcx,%rdx,1),%rdx - 42c0b1: 83 e9 08 sub $0x8,%ecx - 42c0b4: 66 90 xchg %ax,%ax - 42c0b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42c0bd: 00 00 00 - 42c0c0: 0f b6 06 movzbl (%rsi),%eax - 42c0c3: 88 07 mov %al,(%rdi) - 42c0c5: ff c1 inc %ecx - 42c0c7: 48 8d 76 01 lea 0x1(%rsi),%rsi - 42c0cb: 48 8d 7f 01 lea 0x1(%rdi),%rdi - 42c0cf: 75 ef jne 42c0c0 - 42c0d1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 42c0d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42c0dd: 00 00 00 - 42c0e0: 48 81 fa 00 04 00 00 cmp $0x400,%rdx - 42c0e7: 77 77 ja 42c160 - 42c0e9: 89 d1 mov %edx,%ecx - 42c0eb: c1 e9 05 shr $0x5,%ecx - 42c0ee: 74 60 je 42c150 - 42c0f0: ff c9 dec %ecx - 42c0f2: 48 8b 06 mov (%rsi),%rax - 42c0f5: 4c 8b 46 08 mov 0x8(%rsi),%r8 - 42c0f9: 4c 8b 4e 10 mov 0x10(%rsi),%r9 - 42c0fd: 4c 8b 56 18 mov 0x18(%rsi),%r10 - 42c101: 48 89 07 mov %rax,(%rdi) - 42c104: 4c 89 47 08 mov %r8,0x8(%rdi) - 42c108: 4c 89 4f 10 mov %r9,0x10(%rdi) - 42c10c: 4c 89 57 18 mov %r10,0x18(%rdi) - 42c110: 48 8d 76 20 lea 0x20(%rsi),%rsi - 42c114: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 42c118: 74 36 je 42c150 - 42c11a: ff c9 dec %ecx - 42c11c: 48 8b 06 mov (%rsi),%rax - 42c11f: 4c 8b 46 08 mov 0x8(%rsi),%r8 - 42c123: 4c 8b 4e 10 mov 0x10(%rsi),%r9 - 42c127: 4c 8b 56 18 mov 0x18(%rsi),%r10 - 42c12b: 48 89 07 mov %rax,(%rdi) - 42c12e: 4c 89 47 08 mov %r8,0x8(%rdi) - 42c132: 4c 89 4f 10 mov %r9,0x10(%rdi) - 42c136: 4c 89 57 18 mov %r10,0x18(%rdi) - 42c13a: 48 8d 76 20 lea 0x20(%rsi),%rsi - 42c13e: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 42c142: 75 ac jne 42c0f0 - 42c144: 66 90 xchg %ax,%ax - 42c146: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42c14d: 00 00 00 - 42c150: 83 e2 1f and $0x1f,%edx - 42c153: 48 8b 44 24 f8 mov -0x8(%rsp),%rax - 42c158: 0f 85 cb fe ff ff jne 42c029 - 42c15e: f3 c3 repz retq - 42c160: 4c 8b 1d 69 ef 29 00 mov 0x29ef69(%rip),%r11 # 6cb0d0 <__x86_data_cache_size_half> - 42c167: 49 39 d3 cmp %rdx,%r11 - 42c16a: 4c 0f 47 da cmova %rdx,%r11 - 42c16e: 4c 89 d9 mov %r11,%rcx - 42c171: 49 83 e3 f8 and $0xfffffffffffffff8,%r11 - 42c175: 48 c1 e9 03 shr $0x3,%rcx - 42c179: 74 05 je 42c180 - 42c17b: f3 48 a5 rep movsq %ds:(%rsi),%es:(%rdi) - 42c17e: 66 90 xchg %ax,%ax - 42c180: 4c 29 da sub %r11,%rdx - 42c183: 48 f7 c2 f8 ff ff ff test $0xfffffffffffffff8,%rdx - 42c18a: 75 14 jne 42c1a0 - 42c18c: 83 e2 07 and $0x7,%edx - 42c18f: 48 8b 44 24 f8 mov -0x8(%rsp),%rax - 42c194: 0f 85 8f fe ff ff jne 42c029 - 42c19a: f3 c3 repz retq - 42c19c: 0f 1f 40 00 nopl 0x0(%rax) - 42c1a0: 4c 8b 05 09 ef 29 00 mov 0x29ef09(%rip),%r8 # 6cb0b0 <__x86_shared_cache_size_half> - 42c1a7: 49 39 d0 cmp %rdx,%r8 - 42c1aa: 4c 0f 47 c2 cmova %rdx,%r8 - 42c1ae: 4c 89 c1 mov %r8,%rcx - 42c1b1: 49 83 e0 c0 and $0xffffffffffffffc0,%r8 - 42c1b5: 48 c1 e9 06 shr $0x6,%rcx - 42c1b9: 0f 84 ab 01 00 00 je 42c36a - 42c1bf: 4c 89 74 24 f0 mov %r14,-0x10(%rsp) - 42c1c4: 4c 89 6c 24 e8 mov %r13,-0x18(%rsp) - 42c1c9: 4c 89 64 24 e0 mov %r12,-0x20(%rsp) - 42c1ce: 48 89 5c 24 d8 mov %rbx,-0x28(%rsp) - 42c1d3: 83 3d de 0f 2a 00 00 cmpl $0x0,0x2a0fde(%rip) # 6cd1b8 <__x86_prefetchw> - 42c1da: 0f 84 c0 00 00 00 je 42c2a0 - 42c1e0: 48 ff c9 dec %rcx - 42c1e3: 48 8b 06 mov (%rsi),%rax - 42c1e6: 48 8b 5e 08 mov 0x8(%rsi),%rbx - 42c1ea: 4c 8b 4e 10 mov 0x10(%rsi),%r9 - 42c1ee: 4c 8b 56 18 mov 0x18(%rsi),%r10 - 42c1f2: 4c 8b 5e 20 mov 0x20(%rsi),%r11 - 42c1f6: 4c 8b 66 28 mov 0x28(%rsi),%r12 - 42c1fa: 4c 8b 6e 30 mov 0x30(%rsi),%r13 - 42c1fe: 4c 8b 76 38 mov 0x38(%rsi),%r14 - 42c202: 0f 18 8e 80 03 00 00 prefetcht0 0x380(%rsi) - 42c209: 0f 18 8e c0 03 00 00 prefetcht0 0x3c0(%rsi) - 42c210: 48 89 07 mov %rax,(%rdi) - 42c213: 48 89 5f 08 mov %rbx,0x8(%rdi) - 42c217: 4c 89 4f 10 mov %r9,0x10(%rdi) - 42c21b: 4c 89 57 18 mov %r10,0x18(%rdi) - 42c21f: 4c 89 5f 20 mov %r11,0x20(%rdi) - 42c223: 4c 89 67 28 mov %r12,0x28(%rdi) - 42c227: 4c 89 6f 30 mov %r13,0x30(%rdi) - 42c22b: 4c 89 77 38 mov %r14,0x38(%rdi) - 42c22f: 48 8d 76 40 lea 0x40(%rsi),%rsi - 42c233: 48 8d 7f 40 lea 0x40(%rdi),%rdi - 42c237: 0f 84 19 01 00 00 je 42c356 - 42c23d: 48 ff c9 dec %rcx - 42c240: 48 8b 06 mov (%rsi),%rax - 42c243: 48 8b 5e 08 mov 0x8(%rsi),%rbx - 42c247: 4c 8b 4e 10 mov 0x10(%rsi),%r9 - 42c24b: 4c 8b 56 18 mov 0x18(%rsi),%r10 - 42c24f: 4c 8b 5e 20 mov 0x20(%rsi),%r11 - 42c253: 4c 8b 66 28 mov 0x28(%rsi),%r12 - 42c257: 4c 8b 6e 30 mov 0x30(%rsi),%r13 - 42c25b: 4c 8b 76 38 mov 0x38(%rsi),%r14 - 42c25f: 48 89 07 mov %rax,(%rdi) - 42c262: 48 89 5f 08 mov %rbx,0x8(%rdi) - 42c266: 4c 89 4f 10 mov %r9,0x10(%rdi) - 42c26a: 4c 89 57 18 mov %r10,0x18(%rdi) - 42c26e: 4c 89 5f 20 mov %r11,0x20(%rdi) - 42c272: 4c 89 67 28 mov %r12,0x28(%rdi) - 42c276: 4c 89 6f 30 mov %r13,0x30(%rdi) - 42c27a: 4c 89 77 38 mov %r14,0x38(%rdi) - 42c27e: 0f 0d 8f 40 03 00 00 prefetchw 0x340(%rdi) - 42c285: 0f 0d 8f 80 03 00 00 prefetchw 0x380(%rdi) - 42c28c: 48 8d 76 40 lea 0x40(%rsi),%rsi - 42c290: 48 8d 7f 40 lea 0x40(%rdi),%rdi - 42c294: 0f 85 46 ff ff ff jne 42c1e0 - 42c29a: e9 b7 00 00 00 jmpq 42c356 - 42c29f: 90 nop - 42c2a0: 48 ff c9 dec %rcx - 42c2a3: 48 8b 06 mov (%rsi),%rax - 42c2a6: 48 8b 5e 08 mov 0x8(%rsi),%rbx - 42c2aa: 4c 8b 4e 10 mov 0x10(%rsi),%r9 - 42c2ae: 4c 8b 56 18 mov 0x18(%rsi),%r10 - 42c2b2: 4c 8b 5e 20 mov 0x20(%rsi),%r11 - 42c2b6: 4c 8b 66 28 mov 0x28(%rsi),%r12 - 42c2ba: 4c 8b 6e 30 mov 0x30(%rsi),%r13 - 42c2be: 4c 8b 76 38 mov 0x38(%rsi),%r14 - 42c2c2: 0f 18 8e 80 03 00 00 prefetcht0 0x380(%rsi) - 42c2c9: 0f 18 8e c0 03 00 00 prefetcht0 0x3c0(%rsi) - 42c2d0: 48 89 07 mov %rax,(%rdi) - 42c2d3: 48 89 5f 08 mov %rbx,0x8(%rdi) - 42c2d7: 4c 89 4f 10 mov %r9,0x10(%rdi) - 42c2db: 4c 89 57 18 mov %r10,0x18(%rdi) - 42c2df: 4c 89 5f 20 mov %r11,0x20(%rdi) - 42c2e3: 4c 89 67 28 mov %r12,0x28(%rdi) - 42c2e7: 4c 89 6f 30 mov %r13,0x30(%rdi) - 42c2eb: 4c 89 77 38 mov %r14,0x38(%rdi) - 42c2ef: 48 8d 76 40 lea 0x40(%rsi),%rsi - 42c2f3: 48 8d 7f 40 lea 0x40(%rdi),%rdi - 42c2f7: 74 5d je 42c356 - 42c2f9: 48 ff c9 dec %rcx - 42c2fc: 48 8b 06 mov (%rsi),%rax - 42c2ff: 48 8b 5e 08 mov 0x8(%rsi),%rbx - 42c303: 4c 8b 4e 10 mov 0x10(%rsi),%r9 - 42c307: 4c 8b 56 18 mov 0x18(%rsi),%r10 - 42c30b: 4c 8b 5e 20 mov 0x20(%rsi),%r11 - 42c30f: 4c 8b 66 28 mov 0x28(%rsi),%r12 - 42c313: 4c 8b 6e 30 mov 0x30(%rsi),%r13 - 42c317: 4c 8b 76 38 mov 0x38(%rsi),%r14 - 42c31b: 0f 18 8f 40 03 00 00 prefetcht0 0x340(%rdi) - 42c322: 0f 18 8f 80 03 00 00 prefetcht0 0x380(%rdi) - 42c329: 48 89 07 mov %rax,(%rdi) - 42c32c: 48 89 5f 08 mov %rbx,0x8(%rdi) - 42c330: 4c 89 4f 10 mov %r9,0x10(%rdi) - 42c334: 4c 89 57 18 mov %r10,0x18(%rdi) - 42c338: 4c 89 5f 20 mov %r11,0x20(%rdi) - 42c33c: 4c 89 67 28 mov %r12,0x28(%rdi) - 42c340: 4c 89 6f 30 mov %r13,0x30(%rdi) - 42c344: 4c 89 77 38 mov %r14,0x38(%rdi) - 42c348: 48 8d 76 40 lea 0x40(%rsi),%rsi - 42c34c: 48 8d 7f 40 lea 0x40(%rdi),%rdi - 42c350: 0f 85 4a ff ff ff jne 42c2a0 - 42c356: 48 8b 5c 24 d8 mov -0x28(%rsp),%rbx - 42c35b: 4c 8b 64 24 e0 mov -0x20(%rsp),%r12 - 42c360: 4c 8b 6c 24 e8 mov -0x18(%rsp),%r13 - 42c365: 4c 8b 74 24 f0 mov -0x10(%rsp),%r14 - 42c36a: 4c 29 c2 sub %r8,%rdx - 42c36d: 48 f7 c2 c0 ff ff ff test $0xffffffffffffffc0,%rdx - 42c374: 75 1a jne 42c390 - 42c376: 83 e2 3f and $0x3f,%edx - 42c379: 48 8b 44 24 f8 mov -0x8(%rsp),%rax - 42c37e: 0f 85 a5 fc ff ff jne 42c029 - 42c384: f3 c3 repz retq - 42c386: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42c38d: 00 00 00 - 42c390: 48 89 d1 mov %rdx,%rcx - 42c393: 48 c1 e9 07 shr $0x7,%rcx - 42c397: 0f 84 d8 00 00 00 je 42c475 - 42c39d: 4c 89 74 24 f0 mov %r14,-0x10(%rsp) - 42c3a2: 4c 89 6c 24 e8 mov %r13,-0x18(%rsp) - 42c3a7: 4c 89 64 24 e0 mov %r12,-0x20(%rsp) - 42c3ac: 0f 1f 40 00 nopl 0x0(%rax) - 42c3b0: 0f 18 86 00 03 00 00 prefetchnta 0x300(%rsi) - 42c3b7: 0f 18 86 40 03 00 00 prefetchnta 0x340(%rsi) - 42c3be: 48 ff c9 dec %rcx - 42c3c1: 48 8b 06 mov (%rsi),%rax - 42c3c4: 4c 8b 46 08 mov 0x8(%rsi),%r8 - 42c3c8: 4c 8b 4e 10 mov 0x10(%rsi),%r9 - 42c3cc: 4c 8b 56 18 mov 0x18(%rsi),%r10 - 42c3d0: 4c 8b 5e 20 mov 0x20(%rsi),%r11 - 42c3d4: 4c 8b 66 28 mov 0x28(%rsi),%r12 - 42c3d8: 4c 8b 6e 30 mov 0x30(%rsi),%r13 - 42c3dc: 4c 8b 76 38 mov 0x38(%rsi),%r14 - 42c3e0: 48 0f c3 07 movnti %rax,(%rdi) - 42c3e4: 4c 0f c3 47 08 movnti %r8,0x8(%rdi) - 42c3e9: 4c 0f c3 4f 10 movnti %r9,0x10(%rdi) - 42c3ee: 4c 0f c3 57 18 movnti %r10,0x18(%rdi) - 42c3f3: 4c 0f c3 5f 20 movnti %r11,0x20(%rdi) - 42c3f8: 4c 0f c3 67 28 movnti %r12,0x28(%rdi) - 42c3fd: 4c 0f c3 6f 30 movnti %r13,0x30(%rdi) - 42c402: 4c 0f c3 77 38 movnti %r14,0x38(%rdi) - 42c407: 48 8b 46 40 mov 0x40(%rsi),%rax - 42c40b: 4c 8b 46 48 mov 0x48(%rsi),%r8 - 42c40f: 4c 8b 4e 50 mov 0x50(%rsi),%r9 - 42c413: 4c 8b 56 58 mov 0x58(%rsi),%r10 - 42c417: 4c 8b 5e 60 mov 0x60(%rsi),%r11 - 42c41b: 4c 8b 66 68 mov 0x68(%rsi),%r12 - 42c41f: 4c 8b 6e 70 mov 0x70(%rsi),%r13 - 42c423: 4c 8b 76 78 mov 0x78(%rsi),%r14 - 42c427: 48 0f c3 47 40 movnti %rax,0x40(%rdi) - 42c42c: 4c 0f c3 47 48 movnti %r8,0x48(%rdi) - 42c431: 4c 0f c3 4f 50 movnti %r9,0x50(%rdi) - 42c436: 4c 0f c3 57 58 movnti %r10,0x58(%rdi) - 42c43b: 4c 0f c3 5f 60 movnti %r11,0x60(%rdi) - 42c440: 4c 0f c3 67 68 movnti %r12,0x68(%rdi) - 42c445: 4c 0f c3 6f 70 movnti %r13,0x70(%rdi) - 42c44a: 4c 0f c3 77 78 movnti %r14,0x78(%rdi) - 42c44f: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi - 42c456: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi - 42c45d: 0f 85 4d ff ff ff jne 42c3b0 - 42c463: 0f ae f8 sfence - 42c466: 4c 8b 64 24 e0 mov -0x20(%rsp),%r12 - 42c46b: 4c 8b 6c 24 e8 mov -0x18(%rsp),%r13 - 42c470: 4c 8b 74 24 f0 mov -0x10(%rsp),%r14 - 42c475: 83 e2 7f and $0x7f,%edx - 42c478: 48 8b 44 24 f8 mov -0x8(%rsp),%rax - 42c47d: 0f 85 a6 fb ff ff jne 42c029 - 42c483: f3 c3 repz retq - 42c485: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42c48c: 00 00 00 - 42c48f: 90 nop - -000000000042c490 <_wordcopy_fwd_aligned>: - 42c490: 48 89 d0 mov %rdx,%rax - 42c493: 83 e0 07 and $0x7,%eax - 42c496: ff 24 c5 b0 31 4a 00 jmpq *0x4a31b0(,%rax,8) - 42c49d: 0f 1f 00 nopl (%rax) - 42c4a0: 48 8b 06 mov (%rsi),%rax - 42c4a3: 48 83 ef 18 sub $0x18,%rdi - 42c4a7: 48 83 ee 10 sub $0x10,%rsi - 42c4ab: 48 8b 4e 18 mov 0x18(%rsi),%rcx - 42c4af: 48 83 c2 02 add $0x2,%rdx - 42c4b3: 48 89 47 18 mov %rax,0x18(%rdi) - 42c4b7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 42c4be: 00 00 - 42c4c0: 48 8b 46 20 mov 0x20(%rsi),%rax - 42c4c4: 48 89 4f 20 mov %rcx,0x20(%rdi) - 42c4c8: 48 8b 4e 28 mov 0x28(%rsi),%rcx - 42c4cc: 48 89 47 28 mov %rax,0x28(%rdi) - 42c4d0: 48 8b 46 30 mov 0x30(%rsi),%rax - 42c4d4: 48 89 4f 30 mov %rcx,0x30(%rdi) - 42c4d8: 48 8b 4e 38 mov 0x38(%rsi),%rcx - 42c4dc: 48 83 c7 40 add $0x40,%rdi - 42c4e0: 48 89 47 f8 mov %rax,-0x8(%rdi) - 42c4e4: 48 83 ea 08 sub $0x8,%rdx - 42c4e8: 0f 84 ca 00 00 00 je 42c5b8 <_wordcopy_fwd_aligned+0x128> - 42c4ee: 48 83 c6 40 add $0x40,%rsi - 42c4f2: 48 8b 06 mov (%rsi),%rax - 42c4f5: 48 89 0f mov %rcx,(%rdi) - 42c4f8: 48 8b 4e 08 mov 0x8(%rsi),%rcx - 42c4fc: 48 89 47 08 mov %rax,0x8(%rdi) - 42c500: 48 8b 46 10 mov 0x10(%rsi),%rax - 42c504: 48 89 4f 10 mov %rcx,0x10(%rdi) - 42c508: 48 8b 4e 18 mov 0x18(%rsi),%rcx - 42c50c: 48 89 47 18 mov %rax,0x18(%rdi) - 42c510: eb ae jmp 42c4c0 <_wordcopy_fwd_aligned+0x30> - 42c512: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 42c518: 48 85 d2 test %rdx,%rdx - 42c51b: 0f 84 9a 00 00 00 je 42c5bb <_wordcopy_fwd_aligned+0x12b> - 42c521: 48 8b 06 mov (%rsi),%rax - 42c524: 48 83 ef 08 sub $0x8,%rdi - 42c528: eb ce jmp 42c4f8 <_wordcopy_fwd_aligned+0x68> - 42c52a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 42c530: 48 83 ea 01 sub $0x1,%rdx - 42c534: 48 8b 0e mov (%rsi),%rcx - 42c537: 74 7f je 42c5b8 <_wordcopy_fwd_aligned+0x128> - 42c539: 48 83 c6 08 add $0x8,%rsi - 42c53d: eb b3 jmp 42c4f2 <_wordcopy_fwd_aligned+0x62> - 42c53f: 90 nop - 42c540: 48 8b 06 mov (%rsi),%rax - 42c543: 48 83 c2 06 add $0x6,%rdx - 42c547: 48 83 ee 30 sub $0x30,%rsi - 42c54b: 48 83 ef 38 sub $0x38,%rdi - 42c54f: eb 87 jmp 42c4d8 <_wordcopy_fwd_aligned+0x48> - 42c551: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 42c558: 48 8b 0e mov (%rsi),%rcx - 42c55b: 48 83 c2 05 add $0x5,%rdx - 42c55f: 48 83 ee 28 sub $0x28,%rsi - 42c563: 48 83 ef 30 sub $0x30,%rdi - 42c567: e9 64 ff ff ff jmpq 42c4d0 <_wordcopy_fwd_aligned+0x40> - 42c56c: 0f 1f 40 00 nopl 0x0(%rax) - 42c570: 48 8b 06 mov (%rsi),%rax - 42c573: 48 83 c2 04 add $0x4,%rdx - 42c577: 48 83 ee 20 sub $0x20,%rsi - 42c57b: 48 83 ef 28 sub $0x28,%rdi - 42c57f: e9 44 ff ff ff jmpq 42c4c8 <_wordcopy_fwd_aligned+0x38> - 42c584: 0f 1f 40 00 nopl 0x0(%rax) - 42c588: 48 8b 0e mov (%rsi),%rcx - 42c58b: 48 83 c2 03 add $0x3,%rdx - 42c58f: 48 83 ee 18 sub $0x18,%rsi - 42c593: 48 83 ef 20 sub $0x20,%rdi - 42c597: e9 24 ff ff ff jmpq 42c4c0 <_wordcopy_fwd_aligned+0x30> - 42c59c: 0f 1f 40 00 nopl 0x0(%rax) - 42c5a0: 48 8b 0e mov (%rsi),%rcx - 42c5a3: 48 83 c2 01 add $0x1,%rdx - 42c5a7: 48 83 ee 08 sub $0x8,%rsi - 42c5ab: 48 83 ef 10 sub $0x10,%rdi - 42c5af: e9 4c ff ff ff jmpq 42c500 <_wordcopy_fwd_aligned+0x70> - 42c5b4: 0f 1f 40 00 nopl 0x0(%rax) - 42c5b8: 48 89 0f mov %rcx,(%rdi) - 42c5bb: f3 c3 repz retq - 42c5bd: 0f 1f 00 nopl (%rax) - -000000000042c5c0 <_wordcopy_fwd_dest_aligned>: - 42c5c0: 89 f0 mov %esi,%eax - 42c5c2: 48 89 d1 mov %rdx,%rcx - 42c5c5: 41 b8 40 00 00 00 mov $0x40,%r8d - 42c5cb: 83 e0 07 and $0x7,%eax - 42c5ce: 83 e1 03 and $0x3,%ecx - 42c5d1: 48 83 e6 f8 and $0xfffffffffffffff8,%rsi - 42c5d5: c1 e0 03 shl $0x3,%eax - 42c5d8: 53 push %rbx - 42c5d9: 41 29 c0 sub %eax,%r8d - 42c5dc: 48 83 f9 02 cmp $0x2,%rcx - 42c5e0: 0f 84 e2 00 00 00 je 42c6c8 <_wordcopy_fwd_dest_aligned+0x108> - 42c5e6: 48 83 f9 03 cmp $0x3,%rcx - 42c5ea: 74 54 je 42c640 <_wordcopy_fwd_dest_aligned+0x80> - 42c5ec: 48 83 f9 01 cmp $0x1,%rcx - 42c5f0: 74 1e je 42c610 <_wordcopy_fwd_dest_aligned+0x50> - 42c5f2: 48 85 d2 test %rdx,%rdx - 42c5f5: 74 42 je 42c639 <_wordcopy_fwd_dest_aligned+0x79> - 42c5f7: 4c 8b 0e mov (%rsi),%r9 - 42c5fa: 48 8b 5e 08 mov 0x8(%rsi),%rbx - 42c5fe: 48 83 ef 08 sub $0x8,%rdi - 42c602: 48 83 c6 08 add $0x8,%rsi - 42c606: e9 9b 00 00 00 jmpq 42c6a6 <_wordcopy_fwd_dest_aligned+0xe6> - 42c60b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 42c610: 48 83 ea 01 sub $0x1,%rdx - 42c614: 4c 8b 16 mov (%rsi),%r10 - 42c617: 4c 8b 4e 08 mov 0x8(%rsi),%r9 - 42c61b: 0f 85 bf 00 00 00 jne 42c6e0 <_wordcopy_fwd_dest_aligned+0x120> - 42c621: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 42c628: 89 c1 mov %eax,%ecx - 42c62a: 49 d3 ea shr %cl,%r10 - 42c62d: 44 89 c1 mov %r8d,%ecx - 42c630: 49 d3 e1 shl %cl,%r9 - 42c633: 4d 09 d1 or %r10,%r9 - 42c636: 4c 89 0f mov %r9,(%rdi) - 42c639: 5b pop %rbx - 42c63a: c3 retq - 42c63b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 42c640: 48 8b 1e mov (%rsi),%rbx - 42c643: 4c 8b 5e 08 mov 0x8(%rsi),%r11 - 42c647: 48 83 c2 01 add $0x1,%rdx - 42c64b: 48 83 ef 10 sub $0x10,%rdi - 42c64f: 89 c1 mov %eax,%ecx - 42c651: 4d 89 d9 mov %r11,%r9 - 42c654: 4c 8b 56 10 mov 0x10(%rsi),%r10 - 42c658: 48 d3 eb shr %cl,%rbx - 42c65b: 44 89 c1 mov %r8d,%ecx - 42c65e: 49 d3 e1 shl %cl,%r9 - 42c661: 4c 09 cb or %r9,%rbx - 42c664: 48 89 5f 10 mov %rbx,0x10(%rdi) - 42c668: 89 c1 mov %eax,%ecx - 42c66a: 4c 89 d3 mov %r10,%rbx - 42c66d: 4c 8b 4e 18 mov 0x18(%rsi),%r9 - 42c671: 49 d3 eb shr %cl,%r11 - 42c674: 44 89 c1 mov %r8d,%ecx - 42c677: 48 83 c7 20 add $0x20,%rdi - 42c67b: 48 d3 e3 shl %cl,%rbx - 42c67e: 49 09 db or %rbx,%r11 - 42c681: 4c 89 5f f8 mov %r11,-0x8(%rdi) - 42c685: 48 83 ea 04 sub $0x4,%rdx - 42c689: 74 9d je 42c628 <_wordcopy_fwd_dest_aligned+0x68> - 42c68b: 48 83 c6 20 add $0x20,%rsi - 42c68f: 89 c1 mov %eax,%ecx - 42c691: 4d 89 cb mov %r9,%r11 - 42c694: 48 8b 1e mov (%rsi),%rbx - 42c697: 49 d3 ea shr %cl,%r10 - 42c69a: 44 89 c1 mov %r8d,%ecx - 42c69d: 49 d3 e3 shl %cl,%r11 - 42c6a0: 4d 09 da or %r11,%r10 - 42c6a3: 4c 89 17 mov %r10,(%rdi) - 42c6a6: 89 c1 mov %eax,%ecx - 42c6a8: 49 89 da mov %rbx,%r10 - 42c6ab: 4c 8b 5e 08 mov 0x8(%rsi),%r11 - 42c6af: 49 d3 e9 shr %cl,%r9 - 42c6b2: 44 89 c1 mov %r8d,%ecx - 42c6b5: 49 d3 e2 shl %cl,%r10 - 42c6b8: 4d 09 d1 or %r10,%r9 - 42c6bb: 4c 89 4f 08 mov %r9,0x8(%rdi) - 42c6bf: eb 8e jmp 42c64f <_wordcopy_fwd_dest_aligned+0x8f> - 42c6c1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 42c6c8: 4c 8b 1e mov (%rsi),%r11 - 42c6cb: 4c 8b 56 08 mov 0x8(%rsi),%r10 - 42c6cf: 48 83 c2 02 add $0x2,%rdx - 42c6d3: 48 83 ee 08 sub $0x8,%rsi - 42c6d7: 48 83 ef 18 sub $0x18,%rdi - 42c6db: eb 8b jmp 42c668 <_wordcopy_fwd_dest_aligned+0xa8> - 42c6dd: 0f 1f 00 nopl (%rax) - 42c6e0: 48 83 c6 10 add $0x10,%rsi - 42c6e4: eb a9 jmp 42c68f <_wordcopy_fwd_dest_aligned+0xcf> - 42c6e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42c6ed: 00 00 00 - -000000000042c6f0 <_wordcopy_bwd_aligned>: - 42c6f0: 48 89 d0 mov %rdx,%rax - 42c6f3: 83 e0 07 and $0x7,%eax - 42c6f6: ff 24 c5 f0 31 4a 00 jmpq *0x4a31f0(,%rax,8) - 42c6fd: 0f 1f 00 nopl (%rax) - 42c700: 4c 8d 46 d0 lea -0x30(%rsi),%r8 - 42c704: 48 8b 76 f8 mov -0x8(%rsi),%rsi - 42c708: 48 83 ef 28 sub $0x28,%rdi - 42c70c: 48 89 f8 mov %rdi,%rax - 42c70f: 48 83 c2 02 add $0x2,%rdx - 42c713: 4c 89 c1 mov %r8,%rcx - 42c716: 4c 8b 49 20 mov 0x20(%rcx),%r9 - 42c71a: 48 89 70 20 mov %rsi,0x20(%rax) - 42c71e: 66 90 xchg %ax,%ax - 42c720: 48 8b 71 18 mov 0x18(%rcx),%rsi - 42c724: 4c 89 48 18 mov %r9,0x18(%rax) - 42c728: 4c 8b 49 10 mov 0x10(%rcx),%r9 - 42c72c: 48 89 70 10 mov %rsi,0x10(%rax) - 42c730: 48 8b 71 08 mov 0x8(%rcx),%rsi - 42c734: 4c 89 48 08 mov %r9,0x8(%rax) - 42c738: 48 83 ea 08 sub $0x8,%rdx - 42c73c: 4d 8b 08 mov (%r8),%r9 - 42c73f: 48 89 37 mov %rsi,(%rdi) - 42c742: 4c 8d 41 c0 lea -0x40(%rcx),%r8 - 42c746: 48 8d 78 c0 lea -0x40(%rax),%rdi - 42c74a: 0f 84 10 01 00 00 je 42c860 <_wordcopy_bwd_aligned+0x170> - 42c750: 49 8b 70 38 mov 0x38(%r8),%rsi - 42c754: 4c 89 c1 mov %r8,%rcx - 42c757: 48 89 f8 mov %rdi,%rax - 42c75a: 4c 89 4f 38 mov %r9,0x38(%rdi) - 42c75e: 4c 8b 49 30 mov 0x30(%rcx),%r9 - 42c762: 48 89 70 30 mov %rsi,0x30(%rax) - 42c766: 48 8b 71 28 mov 0x28(%rcx),%rsi - 42c76a: 4c 89 48 28 mov %r9,0x28(%rax) - 42c76e: 4c 8b 49 20 mov 0x20(%rcx),%r9 - 42c772: 48 89 70 20 mov %rsi,0x20(%rax) - 42c776: eb a8 jmp 42c720 <_wordcopy_bwd_aligned+0x30> - 42c778: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 42c77f: 00 - 42c780: 48 85 d2 test %rdx,%rdx - 42c783: 0f 84 db 00 00 00 je 42c864 <_wordcopy_bwd_aligned+0x174> - 42c789: 4c 8d 46 c0 lea -0x40(%rsi),%r8 - 42c78d: 48 83 ef 38 sub $0x38,%rdi - 42c791: 48 8b 76 f8 mov -0x8(%rsi),%rsi - 42c795: 48 89 f8 mov %rdi,%rax - 42c798: 4c 89 c1 mov %r8,%rcx - 42c79b: eb c1 jmp 42c75e <_wordcopy_bwd_aligned+0x6e> - 42c79d: 0f 1f 00 nopl (%rax) - 42c7a0: 48 83 ef 40 sub $0x40,%rdi - 42c7a4: 48 83 ea 01 sub $0x1,%rdx - 42c7a8: 4c 8b 4e f8 mov -0x8(%rsi),%r9 - 42c7ac: 0f 84 ae 00 00 00 je 42c860 <_wordcopy_bwd_aligned+0x170> - 42c7b2: 4c 8d 46 b8 lea -0x48(%rsi),%r8 - 42c7b6: eb 98 jmp 42c750 <_wordcopy_bwd_aligned+0x60> - 42c7b8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 42c7bf: 00 - 42c7c0: 48 8d 4e f0 lea -0x10(%rsi),%rcx - 42c7c4: 48 8d 47 f8 lea -0x8(%rdi),%rax - 42c7c8: 48 8b 76 f8 mov -0x8(%rsi),%rsi - 42c7cc: 48 83 c2 06 add $0x6,%rdx - 42c7d0: 49 89 c8 mov %rcx,%r8 - 42c7d3: 48 89 c7 mov %rax,%rdi - 42c7d6: e9 5d ff ff ff jmpq 42c738 <_wordcopy_bwd_aligned+0x48> - 42c7db: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 42c7e0: 4c 8d 46 e8 lea -0x18(%rsi),%r8 - 42c7e4: 48 83 ef 10 sub $0x10,%rdi - 42c7e8: 4c 8b 4e f8 mov -0x8(%rsi),%r9 - 42c7ec: 48 83 c2 05 add $0x5,%rdx - 42c7f0: 48 89 f8 mov %rdi,%rax - 42c7f3: 4c 89 c1 mov %r8,%rcx - 42c7f6: e9 35 ff ff ff jmpq 42c730 <_wordcopy_bwd_aligned+0x40> - 42c7fb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 42c800: 4c 8d 46 e0 lea -0x20(%rsi),%r8 - 42c804: 48 83 ef 18 sub $0x18,%rdi - 42c808: 48 8b 76 f8 mov -0x8(%rsi),%rsi - 42c80c: 48 83 c2 04 add $0x4,%rdx - 42c810: 48 89 f8 mov %rdi,%rax - 42c813: 4c 89 c1 mov %r8,%rcx - 42c816: e9 0d ff ff ff jmpq 42c728 <_wordcopy_bwd_aligned+0x38> - 42c81b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 42c820: 4c 8d 46 d8 lea -0x28(%rsi),%r8 - 42c824: 48 83 ef 20 sub $0x20,%rdi - 42c828: 4c 8b 4e f8 mov -0x8(%rsi),%r9 - 42c82c: 48 83 c2 03 add $0x3,%rdx - 42c830: 48 89 f8 mov %rdi,%rax - 42c833: 4c 89 c1 mov %r8,%rcx - 42c836: e9 e5 fe ff ff jmpq 42c720 <_wordcopy_bwd_aligned+0x30> - 42c83b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 42c840: 4c 8d 46 c8 lea -0x38(%rsi),%r8 - 42c844: 48 83 ef 30 sub $0x30,%rdi - 42c848: 4c 8b 4e f8 mov -0x8(%rsi),%r9 - 42c84c: 48 83 c2 01 add $0x1,%rdx - 42c850: 48 89 f8 mov %rdi,%rax - 42c853: 4c 89 c1 mov %r8,%rcx - 42c856: e9 0b ff ff ff jmpq 42c766 <_wordcopy_bwd_aligned+0x76> - 42c85b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 42c860: 4c 89 4f 38 mov %r9,0x38(%rdi) - 42c864: f3 c3 repz retq - 42c866: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42c86d: 00 00 00 - -000000000042c870 <_wordcopy_bwd_dest_aligned>: - 42c870: 89 f0 mov %esi,%eax - 42c872: 48 89 d1 mov %rdx,%rcx - 42c875: 41 bb 40 00 00 00 mov $0x40,%r11d - 42c87b: 83 e0 07 and $0x7,%eax - 42c87e: 83 e1 03 and $0x3,%ecx - 42c881: 48 83 e6 f8 and $0xfffffffffffffff8,%rsi - 42c885: c1 e0 03 shl $0x3,%eax - 42c888: 41 54 push %r12 - 42c88a: 55 push %rbp - 42c88b: 41 29 c3 sub %eax,%r11d - 42c88e: 48 83 f9 02 cmp $0x2,%rcx - 42c892: 53 push %rbx - 42c893: 0f 84 07 01 00 00 je 42c9a0 <_wordcopy_bwd_dest_aligned+0x130> - 42c899: 48 83 f9 03 cmp $0x3,%rcx - 42c89d: 74 61 je 42c900 <_wordcopy_bwd_dest_aligned+0x90> - 42c89f: 48 83 f9 01 cmp $0x1,%rcx - 42c8a3: 74 23 je 42c8c8 <_wordcopy_bwd_dest_aligned+0x58> - 42c8a5: 48 85 d2 test %rdx,%rdx - 42c8a8: 74 48 je 42c8f2 <_wordcopy_bwd_dest_aligned+0x82> - 42c8aa: 48 8d 6e e0 lea -0x20(%rsi),%rbp - 42c8ae: 4c 8d 57 e8 lea -0x18(%rdi),%r10 - 42c8b2: 4c 8b 26 mov (%rsi),%r12 - 42c8b5: 4c 8b 4e f8 mov -0x8(%rsi),%r9 - 42c8b9: 4c 89 d7 mov %r10,%rdi - 42c8bc: 48 89 ee mov %rbp,%rsi - 42c8bf: e9 b9 00 00 00 jmpq 42c97d <_wordcopy_bwd_dest_aligned+0x10d> - 42c8c4: 0f 1f 40 00 nopl 0x0(%rax) - 42c8c8: 48 83 ea 01 sub $0x1,%rdx - 42c8cc: 4c 8d 57 e0 lea -0x20(%rdi),%r10 - 42c8d0: 4c 8b 06 mov (%rsi),%r8 - 42c8d3: 4c 8b 66 f8 mov -0x8(%rsi),%r12 - 42c8d7: 0f 85 e3 00 00 00 jne 42c9c0 <_wordcopy_bwd_dest_aligned+0x150> - 42c8dd: 0f 1f 00 nopl (%rax) - 42c8e0: 89 c1 mov %eax,%ecx - 42c8e2: 49 d3 ec shr %cl,%r12 - 42c8e5: 44 89 d9 mov %r11d,%ecx - 42c8e8: 49 d3 e0 shl %cl,%r8 - 42c8eb: 4d 09 e0 or %r12,%r8 - 42c8ee: 4d 89 42 18 mov %r8,0x18(%r10) - 42c8f2: 5b pop %rbx - 42c8f3: 5d pop %rbp - 42c8f4: 41 5c pop %r12 - 42c8f6: c3 retq - 42c8f7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 42c8fe: 00 00 - 42c900: 48 8d 6e e8 lea -0x18(%rsi),%rbp - 42c904: 4c 8d 57 f0 lea -0x10(%rdi),%r10 - 42c908: 4c 8b 0e mov (%rsi),%r9 - 42c90b: 48 8b 5e f8 mov -0x8(%rsi),%rbx - 42c90f: 48 83 c2 01 add $0x1,%rdx - 42c913: 48 89 ee mov %rbp,%rsi - 42c916: 4c 89 d7 mov %r10,%rdi - 42c919: 89 c1 mov %eax,%ecx - 42c91b: 49 89 dc mov %rbx,%r12 - 42c91e: 4c 8b 46 08 mov 0x8(%rsi),%r8 - 42c922: 49 d3 ec shr %cl,%r12 - 42c925: 44 89 d9 mov %r11d,%ecx - 42c928: 49 d3 e1 shl %cl,%r9 - 42c92b: 4d 09 e1 or %r12,%r9 - 42c92e: 4c 89 4f 08 mov %r9,0x8(%rdi) - 42c932: 49 89 f1 mov %rsi,%r9 - 42c935: 89 c1 mov %eax,%ecx - 42c937: 4c 89 c6 mov %r8,%rsi - 42c93a: 4c 8b 65 00 mov 0x0(%rbp),%r12 - 42c93e: 48 d3 ee shr %cl,%rsi - 42c941: 44 89 d9 mov %r11d,%ecx - 42c944: 49 8d 69 e0 lea -0x20(%r9),%rbp - 42c948: 48 d3 e3 shl %cl,%rbx - 42c94b: 48 89 d9 mov %rbx,%rcx - 42c94e: 48 09 f1 or %rsi,%rcx - 42c951: 48 83 ea 04 sub $0x4,%rdx - 42c955: 49 89 0a mov %rcx,(%r10) - 42c958: 4c 8d 57 e0 lea -0x20(%rdi),%r10 - 42c95c: 74 82 je 42c8e0 <_wordcopy_bwd_dest_aligned+0x70> - 42c95e: 89 c1 mov %eax,%ecx - 42c960: 4c 89 e3 mov %r12,%rbx - 42c963: 4c 8b 4d 18 mov 0x18(%rbp),%r9 - 42c967: 48 d3 eb shr %cl,%rbx - 42c96a: 44 89 d9 mov %r11d,%ecx - 42c96d: 48 89 ee mov %rbp,%rsi - 42c970: 49 d3 e0 shl %cl,%r8 - 42c973: 4c 89 d7 mov %r10,%rdi - 42c976: 49 09 d8 or %rbx,%r8 - 42c979: 4d 89 42 18 mov %r8,0x18(%r10) - 42c97d: 89 c1 mov %eax,%ecx - 42c97f: 4d 89 c8 mov %r9,%r8 - 42c982: 48 8b 5e 10 mov 0x10(%rsi),%rbx - 42c986: 49 d3 e8 shr %cl,%r8 - 42c989: 44 89 d9 mov %r11d,%ecx - 42c98c: 49 d3 e4 shl %cl,%r12 - 42c98f: 4d 09 c4 or %r8,%r12 - 42c992: 4c 89 67 10 mov %r12,0x10(%rdi) - 42c996: eb 81 jmp 42c919 <_wordcopy_bwd_dest_aligned+0xa9> - 42c998: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 42c99f: 00 - 42c9a0: 4c 8d 4e f0 lea -0x10(%rsi),%r9 - 42c9a4: 48 83 ef 08 sub $0x8,%rdi - 42c9a8: 48 8b 1e mov (%rsi),%rbx - 42c9ab: 49 89 fa mov %rdi,%r10 - 42c9ae: 4c 8b 46 f8 mov -0x8(%rsi),%r8 - 42c9b2: 48 83 c2 02 add $0x2,%rdx - 42c9b6: 4c 89 cd mov %r9,%rbp - 42c9b9: e9 77 ff ff ff jmpq 42c935 <_wordcopy_bwd_dest_aligned+0xc5> - 42c9be: 66 90 xchg %ax,%ax - 42c9c0: 48 8d 6e d8 lea -0x28(%rsi),%rbp - 42c9c4: eb 98 jmp 42c95e <_wordcopy_bwd_dest_aligned+0xee> - 42c9c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42c9cd: 00 00 00 - -000000000042c9d0 <__rawmemchr>: - 42c9d0: 66 48 0f 6e ce movq %rsi,%xmm1 - 42c9d5: 48 89 f9 mov %rdi,%rcx - 42c9d8: 66 0f 60 c9 punpcklbw %xmm1,%xmm1 - 42c9dc: 66 0f 60 c9 punpcklbw %xmm1,%xmm1 - 42c9e0: 48 83 e1 3f and $0x3f,%rcx - 42c9e4: 66 0f 70 c9 00 pshufd $0x0,%xmm1,%xmm1 - 42c9e9: 48 83 f9 30 cmp $0x30,%rcx - 42c9ed: 77 21 ja 42ca10 <__rawmemchr+0x40> - 42c9ef: f3 0f 6f 07 movdqu (%rdi),%xmm0 - 42c9f3: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42c9f7: 66 0f d7 c0 pmovmskb %xmm0,%eax - 42c9fb: 85 c0 test %eax,%eax - 42c9fd: 0f 85 9d 01 00 00 jne 42cba0 <__rawmemchr+0x1d0> - 42ca03: 48 83 c7 10 add $0x10,%rdi - 42ca07: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi - 42ca0b: eb 43 jmp 42ca50 <__rawmemchr+0x80> - 42ca0d: 0f 1f 00 nopl (%rax) - 42ca10: 48 83 e1 0f and $0xf,%rcx - 42ca14: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi - 42ca18: 66 0f 6f 07 movdqa (%rdi),%xmm0 - 42ca1c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42ca20: 66 0f d7 c0 pmovmskb %xmm0,%eax - 42ca24: d3 f8 sar %cl,%eax - 42ca26: 85 c0 test %eax,%eax - 42ca28: 74 16 je 42ca40 <__rawmemchr+0x70> - 42ca2a: 0f bc c0 bsf %eax,%eax - 42ca2d: 48 01 f8 add %rdi,%rax - 42ca30: 48 01 c8 add %rcx,%rax - 42ca33: c3 retq - 42ca34: 66 90 xchg %ax,%ax - 42ca36: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42ca3d: 00 00 00 - 42ca40: 48 83 c7 10 add $0x10,%rdi - 42ca44: 66 90 xchg %ax,%ax - 42ca46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42ca4d: 00 00 00 - 42ca50: 66 0f 6f 07 movdqa (%rdi),%xmm0 - 42ca54: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42ca58: 66 0f d7 c0 pmovmskb %xmm0,%eax - 42ca5c: 85 c0 test %eax,%eax - 42ca5e: 0f 85 3c 01 00 00 jne 42cba0 <__rawmemchr+0x1d0> - 42ca64: 66 0f 6f 57 10 movdqa 0x10(%rdi),%xmm2 - 42ca69: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42ca6d: 66 0f d7 c2 pmovmskb %xmm2,%eax - 42ca71: 85 c0 test %eax,%eax - 42ca73: 0f 85 37 01 00 00 jne 42cbb0 <__rawmemchr+0x1e0> - 42ca79: 66 0f 6f 5f 20 movdqa 0x20(%rdi),%xmm3 - 42ca7e: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 - 42ca82: 66 0f d7 c3 pmovmskb %xmm3,%eax - 42ca86: 85 c0 test %eax,%eax - 42ca88: 0f 85 32 01 00 00 jne 42cbc0 <__rawmemchr+0x1f0> - 42ca8e: 66 0f 6f 67 30 movdqa 0x30(%rdi),%xmm4 - 42ca93: 66 0f 74 e1 pcmpeqb %xmm1,%xmm4 - 42ca97: 48 83 c7 40 add $0x40,%rdi - 42ca9b: 66 0f d7 c4 pmovmskb %xmm4,%eax - 42ca9f: 85 c0 test %eax,%eax - 42caa1: 0f 85 e9 00 00 00 jne 42cb90 <__rawmemchr+0x1c0> - 42caa7: 48 f7 c7 3f 00 00 00 test $0x3f,%rdi - 42caae: 74 60 je 42cb10 <__rawmemchr+0x140> - 42cab0: 66 0f 6f 07 movdqa (%rdi),%xmm0 - 42cab4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42cab8: 66 0f d7 c0 pmovmskb %xmm0,%eax - 42cabc: 85 c0 test %eax,%eax - 42cabe: 0f 85 dc 00 00 00 jne 42cba0 <__rawmemchr+0x1d0> - 42cac4: 66 0f 6f 57 10 movdqa 0x10(%rdi),%xmm2 - 42cac9: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42cacd: 66 0f d7 c2 pmovmskb %xmm2,%eax - 42cad1: 85 c0 test %eax,%eax - 42cad3: 0f 85 d7 00 00 00 jne 42cbb0 <__rawmemchr+0x1e0> - 42cad9: 66 0f 6f 5f 20 movdqa 0x20(%rdi),%xmm3 - 42cade: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 - 42cae2: 66 0f d7 c3 pmovmskb %xmm3,%eax - 42cae6: 85 c0 test %eax,%eax - 42cae8: 0f 85 d2 00 00 00 jne 42cbc0 <__rawmemchr+0x1f0> - 42caee: 66 0f 6f 5f 30 movdqa 0x30(%rdi),%xmm3 - 42caf3: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 - 42caf7: 66 0f d7 c3 pmovmskb %xmm3,%eax - 42cafb: 48 83 c7 40 add $0x40,%rdi - 42caff: 85 c0 test %eax,%eax - 42cb01: 0f 85 89 00 00 00 jne 42cb90 <__rawmemchr+0x1c0> - 42cb07: 48 83 e7 c0 and $0xffffffffffffffc0,%rdi - 42cb0b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 42cb10: 66 0f 6f 07 movdqa (%rdi),%xmm0 - 42cb14: 66 0f 6f 57 10 movdqa 0x10(%rdi),%xmm2 - 42cb19: 66 0f 6f 5f 20 movdqa 0x20(%rdi),%xmm3 - 42cb1e: 66 0f 6f 67 30 movdqa 0x30(%rdi),%xmm4 - 42cb23: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42cb27: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42cb2b: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 - 42cb2f: 66 0f 74 e1 pcmpeqb %xmm1,%xmm4 - 42cb33: 66 0f de d8 pmaxub %xmm0,%xmm3 - 42cb37: 66 0f de e2 pmaxub %xmm2,%xmm4 - 42cb3b: 66 0f de e3 pmaxub %xmm3,%xmm4 - 42cb3f: 66 0f d7 c4 pmovmskb %xmm4,%eax - 42cb43: 48 83 c7 40 add $0x40,%rdi - 42cb47: 85 c0 test %eax,%eax - 42cb49: 74 c5 je 42cb10 <__rawmemchr+0x140> - 42cb4b: 48 83 ef 40 sub $0x40,%rdi - 42cb4f: 66 0f d7 c0 pmovmskb %xmm0,%eax - 42cb53: 85 c0 test %eax,%eax - 42cb55: 75 49 jne 42cba0 <__rawmemchr+0x1d0> - 42cb57: 66 0f d7 c2 pmovmskb %xmm2,%eax - 42cb5b: 85 c0 test %eax,%eax - 42cb5d: 75 51 jne 42cbb0 <__rawmemchr+0x1e0> - 42cb5f: 66 0f 6f 5f 20 movdqa 0x20(%rdi),%xmm3 - 42cb64: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 - 42cb68: 66 0f 74 4f 30 pcmpeqb 0x30(%rdi),%xmm1 - 42cb6d: 66 0f d7 c3 pmovmskb %xmm3,%eax - 42cb71: 85 c0 test %eax,%eax - 42cb73: 75 4b jne 42cbc0 <__rawmemchr+0x1f0> - 42cb75: 66 0f d7 c1 pmovmskb %xmm1,%eax - 42cb79: 0f bc c0 bsf %eax,%eax - 42cb7c: 48 8d 44 07 30 lea 0x30(%rdi,%rax,1),%rax - 42cb81: c3 retq - 42cb82: 0f 1f 40 00 nopl 0x0(%rax) - 42cb86: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42cb8d: 00 00 00 - 42cb90: 0f bc c0 bsf %eax,%eax - 42cb93: 48 8d 44 38 f0 lea -0x10(%rax,%rdi,1),%rax - 42cb98: c3 retq - 42cb99: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 42cba0: 0f bc c0 bsf %eax,%eax - 42cba3: 48 01 f8 add %rdi,%rax - 42cba6: c3 retq - 42cba7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 42cbae: 00 00 - 42cbb0: 0f bc c0 bsf %eax,%eax - 42cbb3: 48 8d 44 38 10 lea 0x10(%rax,%rdi,1),%rax - 42cbb8: c3 retq - 42cbb9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 42cbc0: 0f bc c0 bsf %eax,%eax - 42cbc3: 48 8d 44 38 20 lea 0x20(%rax,%rdi,1),%rax - 42cbc8: c3 retq - 42cbc9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 42cbd0: 48 31 c0 xor %rax,%rax - 42cbd3: c3 retq - 42cbd4: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42cbdb: 00 00 00 - 42cbde: 66 90 xchg %ax,%ax - -000000000042cbe0 <__strchrnul>: - 42cbe0: 66 0f 6e ce movd %esi,%xmm1 - 42cbe4: 89 f8 mov %edi,%eax - 42cbe6: 25 ff 0f 00 00 and $0xfff,%eax - 42cbeb: 66 0f 60 c9 punpcklbw %xmm1,%xmm1 - 42cbef: 3d c0 0f 00 00 cmp $0xfc0,%eax - 42cbf4: 66 0f 61 c9 punpcklwd %xmm1,%xmm1 - 42cbf8: 66 0f 70 c9 00 pshufd $0x0,%xmm1,%xmm1 - 42cbfd: 0f 8f 4d 01 00 00 jg 42cd50 <__strchrnul+0x170> - 42cc03: f3 0f 6f 07 movdqu (%rdi),%xmm0 - 42cc07: 66 0f ef db pxor %xmm3,%xmm3 - 42cc0b: 66 0f 6f e0 movdqa %xmm0,%xmm4 - 42cc0f: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42cc13: 66 0f 74 e3 pcmpeqb %xmm3,%xmm4 - 42cc17: 66 0f eb c4 por %xmm4,%xmm0 - 42cc1b: 66 0f d7 c0 pmovmskb %xmm0,%eax - 42cc1f: 85 c0 test %eax,%eax - 42cc21: 74 0d je 42cc30 <__strchrnul+0x50> - 42cc23: 0f bc c0 bsf %eax,%eax - 42cc26: 48 8d 04 07 lea (%rdi,%rax,1),%rax - 42cc2a: c3 retq - 42cc2b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 42cc30: f3 0f 6f 47 10 movdqu 0x10(%rdi),%xmm0 - 42cc35: 66 0f 6f e0 movdqa %xmm0,%xmm4 - 42cc39: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42cc3d: 66 0f 74 e3 pcmpeqb %xmm3,%xmm4 - 42cc41: 66 0f eb c4 por %xmm4,%xmm0 - 42cc45: 66 0f d7 c8 pmovmskb %xmm0,%ecx - 42cc49: f3 0f 6f 47 20 movdqu 0x20(%rdi),%xmm0 - 42cc4e: 66 0f 6f e0 movdqa %xmm0,%xmm4 - 42cc52: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42cc56: 48 c1 e1 10 shl $0x10,%rcx - 42cc5a: 66 0f 74 e3 pcmpeqb %xmm3,%xmm4 - 42cc5e: 66 0f eb c4 por %xmm4,%xmm0 - 42cc62: 66 0f d7 c0 pmovmskb %xmm0,%eax - 42cc66: f3 0f 6f 47 30 movdqu 0x30(%rdi),%xmm0 - 42cc6b: 66 0f 74 d8 pcmpeqb %xmm0,%xmm3 - 42cc6f: 48 c1 e0 20 shl $0x20,%rax - 42cc73: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42cc77: 48 09 c8 or %rcx,%rax - 42cc7a: 66 0f eb c3 por %xmm3,%xmm0 - 42cc7e: 66 0f d7 c8 pmovmskb %xmm0,%ecx - 42cc82: 48 c1 e1 30 shl $0x30,%rcx - 42cc86: 48 09 c8 or %rcx,%rax - 42cc89: 48 85 c0 test %rax,%rax - 42cc8c: 0f 85 ae 00 00 00 jne 42cd40 <__strchrnul+0x160> - 42cc92: 0f 1f 40 00 nopl 0x0(%rax) - 42cc96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42cc9d: 00 00 00 - 42cca0: 66 0f ef f6 pxor %xmm6,%xmm6 - 42cca4: 48 83 e7 c0 and $0xffffffffffffffc0,%rdi - 42cca8: 48 83 c7 40 add $0x40,%rdi - 42ccac: 66 0f 6f 2f movdqa (%rdi),%xmm5 - 42ccb0: 66 0f 6f 57 10 movdqa 0x10(%rdi),%xmm2 - 42ccb5: 66 0f 6f 5f 20 movdqa 0x20(%rdi),%xmm3 - 42ccba: 66 0f ef e9 pxor %xmm1,%xmm5 - 42ccbe: 66 0f 6f 67 30 movdqa 0x30(%rdi),%xmm4 - 42ccc3: 66 0f ef d1 pxor %xmm1,%xmm2 - 42ccc7: 66 0f ef d9 pxor %xmm1,%xmm3 - 42cccb: 66 0f da 2f pminub (%rdi),%xmm5 - 42cccf: 66 0f ef e1 pxor %xmm1,%xmm4 - 42ccd3: 66 0f da 57 10 pminub 0x10(%rdi),%xmm2 - 42ccd8: 66 0f da 5f 20 pminub 0x20(%rdi),%xmm3 - 42ccdd: 66 0f da ea pminub %xmm2,%xmm5 - 42cce1: 66 0f da 67 30 pminub 0x30(%rdi),%xmm4 - 42cce6: 66 0f da eb pminub %xmm3,%xmm5 - 42ccea: 66 0f da ec pminub %xmm4,%xmm5 - 42ccee: 66 0f 74 ee pcmpeqb %xmm6,%xmm5 - 42ccf2: 66 0f d7 c5 pmovmskb %xmm5,%eax - 42ccf6: 85 c0 test %eax,%eax - 42ccf8: 74 ae je 42cca8 <__strchrnul+0xc8> - 42ccfa: 66 0f 6f 2f movdqa (%rdi),%xmm5 - 42ccfe: 66 0f 6f c5 movdqa %xmm5,%xmm0 - 42cd02: 66 0f 74 e9 pcmpeqb %xmm1,%xmm5 - 42cd06: 66 0f 74 c6 pcmpeqb %xmm6,%xmm0 - 42cd0a: 66 0f eb e8 por %xmm0,%xmm5 - 42cd0e: 66 0f 74 d6 pcmpeqb %xmm6,%xmm2 - 42cd12: 66 0f 74 de pcmpeqb %xmm6,%xmm3 - 42cd16: 66 0f 74 e6 pcmpeqb %xmm6,%xmm4 - 42cd1a: 66 0f d7 cd pmovmskb %xmm5,%ecx - 42cd1e: 66 0f d7 c2 pmovmskb %xmm2,%eax - 42cd22: 48 c1 e0 10 shl $0x10,%rax - 42cd26: 66 44 0f d7 c3 pmovmskb %xmm3,%r8d - 42cd2b: 66 0f d7 d4 pmovmskb %xmm4,%edx - 42cd2f: 49 c1 e0 20 shl $0x20,%r8 - 42cd33: 4c 09 c0 or %r8,%rax - 42cd36: 48 09 c8 or %rcx,%rax - 42cd39: 48 c1 e2 30 shl $0x30,%rdx - 42cd3d: 48 09 d0 or %rdx,%rax - 42cd40: 48 0f bc c0 bsf %rax,%rax - 42cd44: 48 8d 04 07 lea (%rdi,%rax,1),%rax - 42cd48: c3 retq - 42cd49: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 42cd50: 48 89 fa mov %rdi,%rdx - 42cd53: 66 0f ef d2 pxor %xmm2,%xmm2 - 42cd57: 48 83 e2 c0 and $0xffffffffffffffc0,%rdx - 42cd5b: 66 0f 6f c1 movdqa %xmm1,%xmm0 - 42cd5f: 66 0f 6f 1a movdqa (%rdx),%xmm3 - 42cd63: 66 0f 6f e3 movdqa %xmm3,%xmm4 - 42cd67: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 - 42cd6b: 66 0f 74 e2 pcmpeqb %xmm2,%xmm4 - 42cd6f: 66 0f eb dc por %xmm4,%xmm3 - 42cd73: 66 44 0f d7 c3 pmovmskb %xmm3,%r8d - 42cd78: 66 0f 6f 5a 10 movdqa 0x10(%rdx),%xmm3 - 42cd7d: 66 0f 6f e3 movdqa %xmm3,%xmm4 - 42cd81: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 - 42cd85: 66 0f 74 e2 pcmpeqb %xmm2,%xmm4 - 42cd89: 66 0f eb dc por %xmm4,%xmm3 - 42cd8d: 66 0f d7 c3 pmovmskb %xmm3,%eax - 42cd91: 66 0f 6f 5a 20 movdqa 0x20(%rdx),%xmm3 - 42cd96: 66 0f 6f e3 movdqa %xmm3,%xmm4 - 42cd9a: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 - 42cd9e: 48 c1 e0 10 shl $0x10,%rax - 42cda2: 66 0f 74 e2 pcmpeqb %xmm2,%xmm4 - 42cda6: 66 0f eb dc por %xmm4,%xmm3 - 42cdaa: 66 44 0f d7 cb pmovmskb %xmm3,%r9d - 42cdaf: 66 0f 6f 5a 30 movdqa 0x30(%rdx),%xmm3 - 42cdb4: 66 0f 74 d3 pcmpeqb %xmm3,%xmm2 - 42cdb8: 49 c1 e1 20 shl $0x20,%r9 - 42cdbc: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 42cdc0: 4c 09 c8 or %r9,%rax - 42cdc3: 4c 09 c0 or %r8,%rax - 42cdc6: 66 0f eb c2 por %xmm2,%xmm0 - 42cdca: 66 0f d7 c8 pmovmskb %xmm0,%ecx - 42cdce: 48 c1 e1 30 shl $0x30,%rcx - 42cdd2: 48 09 c8 or %rcx,%rax - 42cdd5: 89 f9 mov %edi,%ecx - 42cdd7: 28 d1 sub %dl,%cl - 42cdd9: 48 d3 e8 shr %cl,%rax - 42cddc: 48 85 c0 test %rax,%rax - 42cddf: 0f 85 5b ff ff ff jne 42cd40 <__strchrnul+0x160> - 42cde5: e9 a8 fe ff ff jmpq 42cc92 <__strchrnul+0xb2> - 42cdea: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - -000000000042cdf0 <__strcmp_ssse3>: - 42cdf0: 89 f1 mov %esi,%ecx - 42cdf2: 89 f8 mov %edi,%eax - 42cdf4: 48 83 e1 3f and $0x3f,%rcx - 42cdf8: 48 83 e0 3f and $0x3f,%rax - 42cdfc: 83 f9 30 cmp $0x30,%ecx - 42cdff: 77 3f ja 42ce40 <__strcmp_ssse3+0x50> - 42ce01: 83 f8 30 cmp $0x30,%eax - 42ce04: 77 3a ja 42ce40 <__strcmp_ssse3+0x50> - 42ce06: 66 0f 12 0f movlpd (%rdi),%xmm1 - 42ce0a: 66 0f 12 16 movlpd (%rsi),%xmm2 - 42ce0e: 66 0f 16 4f 08 movhpd 0x8(%rdi),%xmm1 - 42ce13: 66 0f 16 56 08 movhpd 0x8(%rsi),%xmm2 - 42ce18: 66 0f ef c0 pxor %xmm0,%xmm0 - 42ce1c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42ce20: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42ce24: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42ce28: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42ce2c: 81 ea ff ff 00 00 sub $0xffff,%edx - 42ce32: 0f 85 e8 11 00 00 jne 42e020 <__strcmp_ssse3+0x1230> - 42ce38: 48 83 c6 10 add $0x10,%rsi - 42ce3c: 48 83 c7 10 add $0x10,%rdi - 42ce40: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi - 42ce44: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi - 42ce48: ba ff ff 00 00 mov $0xffff,%edx - 42ce4d: 45 31 c0 xor %r8d,%r8d - 42ce50: 83 e1 0f and $0xf,%ecx - 42ce53: 83 e0 0f and $0xf,%eax - 42ce56: 39 c1 cmp %eax,%ecx - 42ce58: 74 26 je 42ce80 <__strcmp_ssse3+0x90> - 42ce5a: 77 07 ja 42ce63 <__strcmp_ssse3+0x73> - 42ce5c: 41 89 d0 mov %edx,%r8d - 42ce5f: 91 xchg %eax,%ecx - 42ce60: 48 87 f7 xchg %rsi,%rdi - 42ce63: 4c 8d 48 0f lea 0xf(%rax),%r9 - 42ce67: 49 29 c9 sub %rcx,%r9 - 42ce6a: 4c 8d 15 bf 63 07 00 lea 0x763bf(%rip),%r10 # 4a3230 - 42ce71: 4f 63 0c 8a movslq (%r10,%r9,4),%r9 - 42ce75: 4f 8d 14 0a lea (%r10,%r9,1),%r10 - 42ce79: 41 ff e2 jmpq *%r10 - 42ce7c: 0f 1f 40 00 nopl 0x0(%rax) - 42ce80: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42ce84: 66 0f ef c0 pxor %xmm0,%xmm0 - 42ce88: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42ce8c: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 - 42ce90: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42ce94: 66 44 0f d7 c9 pmovmskb %xmm1,%r9d - 42ce99: d3 ea shr %cl,%edx - 42ce9b: 41 d3 e9 shr %cl,%r9d - 42ce9e: 44 29 ca sub %r9d,%edx - 42cea1: 0f 85 5e 11 00 00 jne 42e005 <__strcmp_ssse3+0x1215> - 42cea7: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42ceae: 49 c7 c1 10 00 00 00 mov $0x10,%r9 - 42ceb5: 66 0f ef c0 pxor %xmm0,%xmm0 - 42ceb9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 42cec0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42cec5: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42ceca: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42cece: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42ced2: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42ced6: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42ceda: 81 ea ff ff 00 00 sub $0xffff,%edx - 42cee0: 0f 85 1a 11 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42cee6: 48 83 c1 10 add $0x10,%rcx - 42ceea: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42ceef: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42cef4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42cef8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42cefc: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42cf00: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42cf04: 81 ea ff ff 00 00 sub $0xffff,%edx - 42cf0a: 0f 85 f0 10 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42cf10: 48 83 c1 10 add $0x10,%rcx - 42cf14: eb aa jmp 42cec0 <__strcmp_ssse3+0xd0> - 42cf16: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42cf1d: 00 00 00 - 42cf20: 66 0f ef c0 pxor %xmm0,%xmm0 - 42cf24: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 42cf28: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42cf2c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42cf30: 66 0f 73 fa 0f pslldq $0xf,%xmm2 - 42cf35: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42cf39: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42cf3d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 42cf42: d3 ea shr %cl,%edx - 42cf44: 41 d3 e9 shr %cl,%r9d - 42cf47: 44 29 ca sub %r9d,%edx - 42cf4a: 0f 85 b5 10 00 00 jne 42e005 <__strcmp_ssse3+0x1215> - 42cf50: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 42cf54: 66 0f ef c0 pxor %xmm0,%xmm0 - 42cf58: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42cf5f: 41 b9 01 00 00 00 mov $0x1,%r9d - 42cf65: 4c 8d 57 01 lea 0x1(%rdi),%r10 - 42cf69: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42cf70: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42cf77: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 42cf7e: 00 00 - 42cf80: 49 83 c2 10 add $0x10,%r10 - 42cf84: 7f 7a jg 42d000 <__strcmp_ssse3+0x210> - 42cf86: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42cf8b: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42cf90: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42cf94: 66 0f 3a 0f d3 01 palignr $0x1,%xmm3,%xmm2 - 42cf9a: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42cf9e: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42cfa2: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42cfa6: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42cfaa: 81 ea ff ff 00 00 sub $0xffff,%edx - 42cfb0: 0f 85 4a 10 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42cfb6: 48 83 c1 10 add $0x10,%rcx - 42cfba: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42cfbe: 49 83 c2 10 add $0x10,%r10 - 42cfc2: 7f 3c jg 42d000 <__strcmp_ssse3+0x210> - 42cfc4: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42cfc9: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42cfce: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42cfd2: 66 0f 3a 0f d3 01 palignr $0x1,%xmm3,%xmm2 - 42cfd8: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42cfdc: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42cfe0: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42cfe4: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42cfe8: 81 ea ff ff 00 00 sub $0xffff,%edx - 42cfee: 0f 85 0c 10 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42cff4: 48 83 c1 10 add $0x10,%rcx - 42cff8: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42cffc: eb 82 jmp 42cf80 <__strcmp_ssse3+0x190> - 42cffe: 66 90 xchg %ax,%ax - 42d000: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 42d004: 66 0f d7 d0 pmovmskb %xmm0,%edx - 42d008: f7 c2 fe ff 00 00 test $0xfffe,%edx - 42d00e: 75 10 jne 42d020 <__strcmp_ssse3+0x230> - 42d010: 66 0f ef c0 pxor %xmm0,%xmm0 - 42d014: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42d01b: e9 66 ff ff ff jmpq 42cf86 <__strcmp_ssse3+0x196> - 42d020: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42d025: 66 0f 73 d8 01 psrldq $0x1,%xmm0 - 42d02a: 66 0f 73 db 01 psrldq $0x1,%xmm3 - 42d02f: e9 bc 0f 00 00 jmpq 42dff0 <__strcmp_ssse3+0x1200> - 42d034: 66 90 xchg %ax,%ax - 42d036: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42d03d: 00 00 00 - 42d040: 66 0f ef c0 pxor %xmm0,%xmm0 - 42d044: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 42d048: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42d04c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42d050: 66 0f 73 fa 0e pslldq $0xe,%xmm2 - 42d055: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42d059: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42d05d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 42d062: d3 ea shr %cl,%edx - 42d064: 41 d3 e9 shr %cl,%r9d - 42d067: 44 29 ca sub %r9d,%edx - 42d06a: 0f 85 95 0f 00 00 jne 42e005 <__strcmp_ssse3+0x1215> - 42d070: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 42d074: 66 0f ef c0 pxor %xmm0,%xmm0 - 42d078: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42d07f: 41 b9 02 00 00 00 mov $0x2,%r9d - 42d085: 4c 8d 57 02 lea 0x2(%rdi),%r10 - 42d089: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42d090: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42d097: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 42d09e: 00 00 - 42d0a0: 49 83 c2 10 add $0x10,%r10 - 42d0a4: 7f 7a jg 42d120 <__strcmp_ssse3+0x330> - 42d0a6: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42d0ab: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42d0b0: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42d0b4: 66 0f 3a 0f d3 02 palignr $0x2,%xmm3,%xmm2 - 42d0ba: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42d0be: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42d0c2: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42d0c6: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42d0ca: 81 ea ff ff 00 00 sub $0xffff,%edx - 42d0d0: 0f 85 2a 0f 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42d0d6: 48 83 c1 10 add $0x10,%rcx - 42d0da: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42d0de: 49 83 c2 10 add $0x10,%r10 - 42d0e2: 7f 3c jg 42d120 <__strcmp_ssse3+0x330> - 42d0e4: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42d0e9: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42d0ee: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42d0f2: 66 0f 3a 0f d3 02 palignr $0x2,%xmm3,%xmm2 - 42d0f8: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42d0fc: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42d100: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42d104: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42d108: 81 ea ff ff 00 00 sub $0xffff,%edx - 42d10e: 0f 85 ec 0e 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42d114: 48 83 c1 10 add $0x10,%rcx - 42d118: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42d11c: eb 82 jmp 42d0a0 <__strcmp_ssse3+0x2b0> - 42d11e: 66 90 xchg %ax,%ax - 42d120: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 42d124: 66 0f d7 d0 pmovmskb %xmm0,%edx - 42d128: f7 c2 fc ff 00 00 test $0xfffc,%edx - 42d12e: 75 10 jne 42d140 <__strcmp_ssse3+0x350> - 42d130: 66 0f ef c0 pxor %xmm0,%xmm0 - 42d134: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42d13b: e9 66 ff ff ff jmpq 42d0a6 <__strcmp_ssse3+0x2b6> - 42d140: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42d145: 66 0f 73 d8 02 psrldq $0x2,%xmm0 - 42d14a: 66 0f 73 db 02 psrldq $0x2,%xmm3 - 42d14f: e9 9c 0e 00 00 jmpq 42dff0 <__strcmp_ssse3+0x1200> - 42d154: 66 90 xchg %ax,%ax - 42d156: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42d15d: 00 00 00 - 42d160: 66 0f ef c0 pxor %xmm0,%xmm0 - 42d164: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 42d168: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42d16c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42d170: 66 0f 73 fa 0d pslldq $0xd,%xmm2 - 42d175: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42d179: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42d17d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 42d182: d3 ea shr %cl,%edx - 42d184: 41 d3 e9 shr %cl,%r9d - 42d187: 44 29 ca sub %r9d,%edx - 42d18a: 0f 85 75 0e 00 00 jne 42e005 <__strcmp_ssse3+0x1215> - 42d190: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 42d194: 66 0f ef c0 pxor %xmm0,%xmm0 - 42d198: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42d19f: 41 b9 03 00 00 00 mov $0x3,%r9d - 42d1a5: 4c 8d 57 03 lea 0x3(%rdi),%r10 - 42d1a9: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42d1b0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42d1b7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 42d1be: 00 00 - 42d1c0: 49 83 c2 10 add $0x10,%r10 - 42d1c4: 7f 7a jg 42d240 <__strcmp_ssse3+0x450> - 42d1c6: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42d1cb: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42d1d0: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42d1d4: 66 0f 3a 0f d3 03 palignr $0x3,%xmm3,%xmm2 - 42d1da: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42d1de: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42d1e2: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42d1e6: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42d1ea: 81 ea ff ff 00 00 sub $0xffff,%edx - 42d1f0: 0f 85 0a 0e 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42d1f6: 48 83 c1 10 add $0x10,%rcx - 42d1fa: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42d1fe: 49 83 c2 10 add $0x10,%r10 - 42d202: 7f 3c jg 42d240 <__strcmp_ssse3+0x450> - 42d204: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42d209: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42d20e: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42d212: 66 0f 3a 0f d3 03 palignr $0x3,%xmm3,%xmm2 - 42d218: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42d21c: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42d220: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42d224: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42d228: 81 ea ff ff 00 00 sub $0xffff,%edx - 42d22e: 0f 85 cc 0d 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42d234: 48 83 c1 10 add $0x10,%rcx - 42d238: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42d23c: eb 82 jmp 42d1c0 <__strcmp_ssse3+0x3d0> - 42d23e: 66 90 xchg %ax,%ax - 42d240: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 42d244: 66 0f d7 d0 pmovmskb %xmm0,%edx - 42d248: f7 c2 f8 ff 00 00 test $0xfff8,%edx - 42d24e: 75 10 jne 42d260 <__strcmp_ssse3+0x470> - 42d250: 66 0f ef c0 pxor %xmm0,%xmm0 - 42d254: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42d25b: e9 66 ff ff ff jmpq 42d1c6 <__strcmp_ssse3+0x3d6> - 42d260: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42d265: 66 0f 73 d8 03 psrldq $0x3,%xmm0 - 42d26a: 66 0f 73 db 03 psrldq $0x3,%xmm3 - 42d26f: e9 7c 0d 00 00 jmpq 42dff0 <__strcmp_ssse3+0x1200> - 42d274: 66 90 xchg %ax,%ax - 42d276: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42d27d: 00 00 00 - 42d280: 66 0f ef c0 pxor %xmm0,%xmm0 - 42d284: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 42d288: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42d28c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42d290: 66 0f 73 fa 0c pslldq $0xc,%xmm2 - 42d295: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42d299: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42d29d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 42d2a2: d3 ea shr %cl,%edx - 42d2a4: 41 d3 e9 shr %cl,%r9d - 42d2a7: 44 29 ca sub %r9d,%edx - 42d2aa: 0f 85 55 0d 00 00 jne 42e005 <__strcmp_ssse3+0x1215> - 42d2b0: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 42d2b4: 66 0f ef c0 pxor %xmm0,%xmm0 - 42d2b8: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42d2bf: 41 b9 04 00 00 00 mov $0x4,%r9d - 42d2c5: 4c 8d 57 04 lea 0x4(%rdi),%r10 - 42d2c9: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42d2d0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42d2d7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 42d2de: 00 00 - 42d2e0: 49 83 c2 10 add $0x10,%r10 - 42d2e4: 7f 7a jg 42d360 <__strcmp_ssse3+0x570> - 42d2e6: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42d2eb: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42d2f0: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42d2f4: 66 0f 3a 0f d3 04 palignr $0x4,%xmm3,%xmm2 - 42d2fa: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42d2fe: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42d302: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42d306: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42d30a: 81 ea ff ff 00 00 sub $0xffff,%edx - 42d310: 0f 85 ea 0c 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42d316: 48 83 c1 10 add $0x10,%rcx - 42d31a: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42d31e: 49 83 c2 10 add $0x10,%r10 - 42d322: 7f 3c jg 42d360 <__strcmp_ssse3+0x570> - 42d324: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42d329: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42d32e: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42d332: 66 0f 3a 0f d3 04 palignr $0x4,%xmm3,%xmm2 - 42d338: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42d33c: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42d340: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42d344: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42d348: 81 ea ff ff 00 00 sub $0xffff,%edx - 42d34e: 0f 85 ac 0c 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42d354: 48 83 c1 10 add $0x10,%rcx - 42d358: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42d35c: eb 82 jmp 42d2e0 <__strcmp_ssse3+0x4f0> - 42d35e: 66 90 xchg %ax,%ax - 42d360: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 42d364: 66 0f d7 d0 pmovmskb %xmm0,%edx - 42d368: f7 c2 f0 ff 00 00 test $0xfff0,%edx - 42d36e: 75 10 jne 42d380 <__strcmp_ssse3+0x590> - 42d370: 66 0f ef c0 pxor %xmm0,%xmm0 - 42d374: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42d37b: e9 66 ff ff ff jmpq 42d2e6 <__strcmp_ssse3+0x4f6> - 42d380: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42d385: 66 0f 73 d8 04 psrldq $0x4,%xmm0 - 42d38a: 66 0f 73 db 04 psrldq $0x4,%xmm3 - 42d38f: e9 5c 0c 00 00 jmpq 42dff0 <__strcmp_ssse3+0x1200> - 42d394: 66 90 xchg %ax,%ax - 42d396: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42d39d: 00 00 00 - 42d3a0: 66 0f ef c0 pxor %xmm0,%xmm0 - 42d3a4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 42d3a8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42d3ac: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42d3b0: 66 0f 73 fa 0b pslldq $0xb,%xmm2 - 42d3b5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42d3b9: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42d3bd: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 42d3c2: d3 ea shr %cl,%edx - 42d3c4: 41 d3 e9 shr %cl,%r9d - 42d3c7: 44 29 ca sub %r9d,%edx - 42d3ca: 0f 85 35 0c 00 00 jne 42e005 <__strcmp_ssse3+0x1215> - 42d3d0: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 42d3d4: 66 0f ef c0 pxor %xmm0,%xmm0 - 42d3d8: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42d3df: 41 b9 05 00 00 00 mov $0x5,%r9d - 42d3e5: 4c 8d 57 05 lea 0x5(%rdi),%r10 - 42d3e9: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42d3f0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42d3f7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 42d3fe: 00 00 - 42d400: 49 83 c2 10 add $0x10,%r10 - 42d404: 7f 7a jg 42d480 <__strcmp_ssse3+0x690> - 42d406: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42d40b: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42d410: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42d414: 66 0f 3a 0f d3 05 palignr $0x5,%xmm3,%xmm2 - 42d41a: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42d41e: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42d422: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42d426: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42d42a: 81 ea ff ff 00 00 sub $0xffff,%edx - 42d430: 0f 85 ca 0b 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42d436: 48 83 c1 10 add $0x10,%rcx - 42d43a: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42d43e: 49 83 c2 10 add $0x10,%r10 - 42d442: 7f 3c jg 42d480 <__strcmp_ssse3+0x690> - 42d444: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42d449: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42d44e: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42d452: 66 0f 3a 0f d3 05 palignr $0x5,%xmm3,%xmm2 - 42d458: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42d45c: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42d460: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42d464: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42d468: 81 ea ff ff 00 00 sub $0xffff,%edx - 42d46e: 0f 85 8c 0b 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42d474: 48 83 c1 10 add $0x10,%rcx - 42d478: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42d47c: eb 82 jmp 42d400 <__strcmp_ssse3+0x610> - 42d47e: 66 90 xchg %ax,%ax - 42d480: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 42d484: 66 0f d7 d0 pmovmskb %xmm0,%edx - 42d488: f7 c2 e0 ff 00 00 test $0xffe0,%edx - 42d48e: 75 10 jne 42d4a0 <__strcmp_ssse3+0x6b0> - 42d490: 66 0f ef c0 pxor %xmm0,%xmm0 - 42d494: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42d49b: e9 66 ff ff ff jmpq 42d406 <__strcmp_ssse3+0x616> - 42d4a0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42d4a5: 66 0f 73 d8 05 psrldq $0x5,%xmm0 - 42d4aa: 66 0f 73 db 05 psrldq $0x5,%xmm3 - 42d4af: e9 3c 0b 00 00 jmpq 42dff0 <__strcmp_ssse3+0x1200> - 42d4b4: 66 90 xchg %ax,%ax - 42d4b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42d4bd: 00 00 00 - 42d4c0: 66 0f ef c0 pxor %xmm0,%xmm0 - 42d4c4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 42d4c8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42d4cc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42d4d0: 66 0f 73 fa 0a pslldq $0xa,%xmm2 - 42d4d5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42d4d9: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42d4dd: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 42d4e2: d3 ea shr %cl,%edx - 42d4e4: 41 d3 e9 shr %cl,%r9d - 42d4e7: 44 29 ca sub %r9d,%edx - 42d4ea: 0f 85 15 0b 00 00 jne 42e005 <__strcmp_ssse3+0x1215> - 42d4f0: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 42d4f4: 66 0f ef c0 pxor %xmm0,%xmm0 - 42d4f8: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42d4ff: 41 b9 06 00 00 00 mov $0x6,%r9d - 42d505: 4c 8d 57 06 lea 0x6(%rdi),%r10 - 42d509: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42d510: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42d517: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 42d51e: 00 00 - 42d520: 49 83 c2 10 add $0x10,%r10 - 42d524: 7f 7a jg 42d5a0 <__strcmp_ssse3+0x7b0> - 42d526: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42d52b: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42d530: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42d534: 66 0f 3a 0f d3 06 palignr $0x6,%xmm3,%xmm2 - 42d53a: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42d53e: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42d542: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42d546: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42d54a: 81 ea ff ff 00 00 sub $0xffff,%edx - 42d550: 0f 85 aa 0a 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42d556: 48 83 c1 10 add $0x10,%rcx - 42d55a: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42d55e: 49 83 c2 10 add $0x10,%r10 - 42d562: 7f 3c jg 42d5a0 <__strcmp_ssse3+0x7b0> - 42d564: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42d569: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42d56e: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42d572: 66 0f 3a 0f d3 06 palignr $0x6,%xmm3,%xmm2 - 42d578: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42d57c: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42d580: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42d584: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42d588: 81 ea ff ff 00 00 sub $0xffff,%edx - 42d58e: 0f 85 6c 0a 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42d594: 48 83 c1 10 add $0x10,%rcx - 42d598: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42d59c: eb 82 jmp 42d520 <__strcmp_ssse3+0x730> - 42d59e: 66 90 xchg %ax,%ax - 42d5a0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 42d5a4: 66 0f d7 d0 pmovmskb %xmm0,%edx - 42d5a8: f7 c2 c0 ff 00 00 test $0xffc0,%edx - 42d5ae: 75 10 jne 42d5c0 <__strcmp_ssse3+0x7d0> - 42d5b0: 66 0f ef c0 pxor %xmm0,%xmm0 - 42d5b4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42d5bb: e9 66 ff ff ff jmpq 42d526 <__strcmp_ssse3+0x736> - 42d5c0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42d5c5: 66 0f 73 d8 06 psrldq $0x6,%xmm0 - 42d5ca: 66 0f 73 db 06 psrldq $0x6,%xmm3 - 42d5cf: e9 1c 0a 00 00 jmpq 42dff0 <__strcmp_ssse3+0x1200> - 42d5d4: 66 90 xchg %ax,%ax - 42d5d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42d5dd: 00 00 00 - 42d5e0: 66 0f ef c0 pxor %xmm0,%xmm0 - 42d5e4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 42d5e8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42d5ec: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42d5f0: 66 0f 73 fa 09 pslldq $0x9,%xmm2 - 42d5f5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42d5f9: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42d5fd: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 42d602: d3 ea shr %cl,%edx - 42d604: 41 d3 e9 shr %cl,%r9d - 42d607: 44 29 ca sub %r9d,%edx - 42d60a: 0f 85 f5 09 00 00 jne 42e005 <__strcmp_ssse3+0x1215> - 42d610: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 42d614: 66 0f ef c0 pxor %xmm0,%xmm0 - 42d618: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42d61f: 41 b9 07 00 00 00 mov $0x7,%r9d - 42d625: 4c 8d 57 07 lea 0x7(%rdi),%r10 - 42d629: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42d630: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42d637: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 42d63e: 00 00 - 42d640: 49 83 c2 10 add $0x10,%r10 - 42d644: 7f 7a jg 42d6c0 <__strcmp_ssse3+0x8d0> - 42d646: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42d64b: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42d650: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42d654: 66 0f 3a 0f d3 07 palignr $0x7,%xmm3,%xmm2 - 42d65a: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42d65e: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42d662: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42d666: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42d66a: 81 ea ff ff 00 00 sub $0xffff,%edx - 42d670: 0f 85 8a 09 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42d676: 48 83 c1 10 add $0x10,%rcx - 42d67a: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42d67e: 49 83 c2 10 add $0x10,%r10 - 42d682: 7f 3c jg 42d6c0 <__strcmp_ssse3+0x8d0> - 42d684: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42d689: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42d68e: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42d692: 66 0f 3a 0f d3 07 palignr $0x7,%xmm3,%xmm2 - 42d698: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42d69c: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42d6a0: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42d6a4: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42d6a8: 81 ea ff ff 00 00 sub $0xffff,%edx - 42d6ae: 0f 85 4c 09 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42d6b4: 48 83 c1 10 add $0x10,%rcx - 42d6b8: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42d6bc: eb 82 jmp 42d640 <__strcmp_ssse3+0x850> - 42d6be: 66 90 xchg %ax,%ax - 42d6c0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 42d6c4: 66 0f d7 d0 pmovmskb %xmm0,%edx - 42d6c8: f7 c2 80 ff 00 00 test $0xff80,%edx - 42d6ce: 75 10 jne 42d6e0 <__strcmp_ssse3+0x8f0> - 42d6d0: 66 0f ef c0 pxor %xmm0,%xmm0 - 42d6d4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42d6db: e9 66 ff ff ff jmpq 42d646 <__strcmp_ssse3+0x856> - 42d6e0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42d6e5: 66 0f 73 d8 07 psrldq $0x7,%xmm0 - 42d6ea: 66 0f 73 db 07 psrldq $0x7,%xmm3 - 42d6ef: e9 fc 08 00 00 jmpq 42dff0 <__strcmp_ssse3+0x1200> - 42d6f4: 66 90 xchg %ax,%ax - 42d6f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42d6fd: 00 00 00 - 42d700: 66 0f ef c0 pxor %xmm0,%xmm0 - 42d704: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 42d708: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42d70c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42d710: 66 0f 73 fa 08 pslldq $0x8,%xmm2 - 42d715: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42d719: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42d71d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 42d722: d3 ea shr %cl,%edx - 42d724: 41 d3 e9 shr %cl,%r9d - 42d727: 44 29 ca sub %r9d,%edx - 42d72a: 0f 85 d5 08 00 00 jne 42e005 <__strcmp_ssse3+0x1215> - 42d730: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 42d734: 66 0f ef c0 pxor %xmm0,%xmm0 - 42d738: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42d73f: 41 b9 08 00 00 00 mov $0x8,%r9d - 42d745: 4c 8d 57 08 lea 0x8(%rdi),%r10 - 42d749: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42d750: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42d757: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 42d75e: 00 00 - 42d760: 49 83 c2 10 add $0x10,%r10 - 42d764: 7f 7a jg 42d7e0 <__strcmp_ssse3+0x9f0> - 42d766: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42d76b: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42d770: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42d774: 66 0f 3a 0f d3 08 palignr $0x8,%xmm3,%xmm2 - 42d77a: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42d77e: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42d782: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42d786: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42d78a: 81 ea ff ff 00 00 sub $0xffff,%edx - 42d790: 0f 85 6a 08 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42d796: 48 83 c1 10 add $0x10,%rcx - 42d79a: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42d79e: 49 83 c2 10 add $0x10,%r10 - 42d7a2: 7f 3c jg 42d7e0 <__strcmp_ssse3+0x9f0> - 42d7a4: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42d7a9: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42d7ae: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42d7b2: 66 0f 3a 0f d3 08 palignr $0x8,%xmm3,%xmm2 - 42d7b8: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42d7bc: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42d7c0: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42d7c4: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42d7c8: 81 ea ff ff 00 00 sub $0xffff,%edx - 42d7ce: 0f 85 2c 08 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42d7d4: 48 83 c1 10 add $0x10,%rcx - 42d7d8: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42d7dc: eb 82 jmp 42d760 <__strcmp_ssse3+0x970> - 42d7de: 66 90 xchg %ax,%ax - 42d7e0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 42d7e4: 66 0f d7 d0 pmovmskb %xmm0,%edx - 42d7e8: f7 c2 00 ff 00 00 test $0xff00,%edx - 42d7ee: 75 10 jne 42d800 <__strcmp_ssse3+0xa10> - 42d7f0: 66 0f ef c0 pxor %xmm0,%xmm0 - 42d7f4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42d7fb: e9 66 ff ff ff jmpq 42d766 <__strcmp_ssse3+0x976> - 42d800: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42d805: 66 0f 73 d8 08 psrldq $0x8,%xmm0 - 42d80a: 66 0f 73 db 08 psrldq $0x8,%xmm3 - 42d80f: e9 dc 07 00 00 jmpq 42dff0 <__strcmp_ssse3+0x1200> - 42d814: 66 90 xchg %ax,%ax - 42d816: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42d81d: 00 00 00 - 42d820: 66 0f ef c0 pxor %xmm0,%xmm0 - 42d824: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 42d828: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42d82c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42d830: 66 0f 73 fa 07 pslldq $0x7,%xmm2 - 42d835: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42d839: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42d83d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 42d842: d3 ea shr %cl,%edx - 42d844: 41 d3 e9 shr %cl,%r9d - 42d847: 44 29 ca sub %r9d,%edx - 42d84a: 0f 85 b5 07 00 00 jne 42e005 <__strcmp_ssse3+0x1215> - 42d850: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 42d854: 66 0f ef c0 pxor %xmm0,%xmm0 - 42d858: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42d85f: 41 b9 09 00 00 00 mov $0x9,%r9d - 42d865: 4c 8d 57 09 lea 0x9(%rdi),%r10 - 42d869: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42d870: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42d877: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 42d87e: 00 00 - 42d880: 49 83 c2 10 add $0x10,%r10 - 42d884: 7f 7a jg 42d900 <__strcmp_ssse3+0xb10> - 42d886: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42d88b: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42d890: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42d894: 66 0f 3a 0f d3 09 palignr $0x9,%xmm3,%xmm2 - 42d89a: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42d89e: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42d8a2: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42d8a6: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42d8aa: 81 ea ff ff 00 00 sub $0xffff,%edx - 42d8b0: 0f 85 4a 07 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42d8b6: 48 83 c1 10 add $0x10,%rcx - 42d8ba: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42d8be: 49 83 c2 10 add $0x10,%r10 - 42d8c2: 7f 3c jg 42d900 <__strcmp_ssse3+0xb10> - 42d8c4: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42d8c9: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42d8ce: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42d8d2: 66 0f 3a 0f d3 09 palignr $0x9,%xmm3,%xmm2 - 42d8d8: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42d8dc: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42d8e0: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42d8e4: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42d8e8: 81 ea ff ff 00 00 sub $0xffff,%edx - 42d8ee: 0f 85 0c 07 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42d8f4: 48 83 c1 10 add $0x10,%rcx - 42d8f8: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42d8fc: eb 82 jmp 42d880 <__strcmp_ssse3+0xa90> - 42d8fe: 66 90 xchg %ax,%ax - 42d900: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 42d904: 66 0f d7 d0 pmovmskb %xmm0,%edx - 42d908: f7 c2 00 fe 00 00 test $0xfe00,%edx - 42d90e: 75 10 jne 42d920 <__strcmp_ssse3+0xb30> - 42d910: 66 0f ef c0 pxor %xmm0,%xmm0 - 42d914: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42d91b: e9 66 ff ff ff jmpq 42d886 <__strcmp_ssse3+0xa96> - 42d920: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42d925: 66 0f 73 d8 09 psrldq $0x9,%xmm0 - 42d92a: 66 0f 73 db 09 psrldq $0x9,%xmm3 - 42d92f: e9 bc 06 00 00 jmpq 42dff0 <__strcmp_ssse3+0x1200> - 42d934: 66 90 xchg %ax,%ax - 42d936: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42d93d: 00 00 00 - 42d940: 66 0f ef c0 pxor %xmm0,%xmm0 - 42d944: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 42d948: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42d94c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42d950: 66 0f 73 fa 06 pslldq $0x6,%xmm2 - 42d955: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42d959: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42d95d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 42d962: d3 ea shr %cl,%edx - 42d964: 41 d3 e9 shr %cl,%r9d - 42d967: 44 29 ca sub %r9d,%edx - 42d96a: 0f 85 95 06 00 00 jne 42e005 <__strcmp_ssse3+0x1215> - 42d970: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 42d974: 66 0f ef c0 pxor %xmm0,%xmm0 - 42d978: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42d97f: 41 b9 0a 00 00 00 mov $0xa,%r9d - 42d985: 4c 8d 57 0a lea 0xa(%rdi),%r10 - 42d989: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42d990: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42d997: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 42d99e: 00 00 - 42d9a0: 49 83 c2 10 add $0x10,%r10 - 42d9a4: 7f 7a jg 42da20 <__strcmp_ssse3+0xc30> - 42d9a6: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42d9ab: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42d9b0: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42d9b4: 66 0f 3a 0f d3 0a palignr $0xa,%xmm3,%xmm2 - 42d9ba: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42d9be: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42d9c2: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42d9c6: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42d9ca: 81 ea ff ff 00 00 sub $0xffff,%edx - 42d9d0: 0f 85 2a 06 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42d9d6: 48 83 c1 10 add $0x10,%rcx - 42d9da: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42d9de: 49 83 c2 10 add $0x10,%r10 - 42d9e2: 7f 3c jg 42da20 <__strcmp_ssse3+0xc30> - 42d9e4: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42d9e9: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42d9ee: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42d9f2: 66 0f 3a 0f d3 0a palignr $0xa,%xmm3,%xmm2 - 42d9f8: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42d9fc: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42da00: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42da04: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42da08: 81 ea ff ff 00 00 sub $0xffff,%edx - 42da0e: 0f 85 ec 05 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42da14: 48 83 c1 10 add $0x10,%rcx - 42da18: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42da1c: eb 82 jmp 42d9a0 <__strcmp_ssse3+0xbb0> - 42da1e: 66 90 xchg %ax,%ax - 42da20: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 42da24: 66 0f d7 d0 pmovmskb %xmm0,%edx - 42da28: f7 c2 00 fc 00 00 test $0xfc00,%edx - 42da2e: 75 10 jne 42da40 <__strcmp_ssse3+0xc50> - 42da30: 66 0f ef c0 pxor %xmm0,%xmm0 - 42da34: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42da3b: e9 66 ff ff ff jmpq 42d9a6 <__strcmp_ssse3+0xbb6> - 42da40: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42da45: 66 0f 73 d8 0a psrldq $0xa,%xmm0 - 42da4a: 66 0f 73 db 0a psrldq $0xa,%xmm3 - 42da4f: e9 9c 05 00 00 jmpq 42dff0 <__strcmp_ssse3+0x1200> - 42da54: 66 90 xchg %ax,%ax - 42da56: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42da5d: 00 00 00 - 42da60: 66 0f ef c0 pxor %xmm0,%xmm0 - 42da64: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 42da68: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42da6c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42da70: 66 0f 73 fa 05 pslldq $0x5,%xmm2 - 42da75: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42da79: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42da7d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 42da82: d3 ea shr %cl,%edx - 42da84: 41 d3 e9 shr %cl,%r9d - 42da87: 44 29 ca sub %r9d,%edx - 42da8a: 0f 85 75 05 00 00 jne 42e005 <__strcmp_ssse3+0x1215> - 42da90: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 42da94: 66 0f ef c0 pxor %xmm0,%xmm0 - 42da98: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42da9f: 41 b9 0b 00 00 00 mov $0xb,%r9d - 42daa5: 4c 8d 57 0b lea 0xb(%rdi),%r10 - 42daa9: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42dab0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42dab7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 42dabe: 00 00 - 42dac0: 49 83 c2 10 add $0x10,%r10 - 42dac4: 7f 7a jg 42db40 <__strcmp_ssse3+0xd50> - 42dac6: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42dacb: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42dad0: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42dad4: 66 0f 3a 0f d3 0b palignr $0xb,%xmm3,%xmm2 - 42dada: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42dade: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42dae2: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42dae6: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42daea: 81 ea ff ff 00 00 sub $0xffff,%edx - 42daf0: 0f 85 0a 05 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42daf6: 48 83 c1 10 add $0x10,%rcx - 42dafa: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42dafe: 49 83 c2 10 add $0x10,%r10 - 42db02: 7f 3c jg 42db40 <__strcmp_ssse3+0xd50> - 42db04: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42db09: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42db0e: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42db12: 66 0f 3a 0f d3 0b palignr $0xb,%xmm3,%xmm2 - 42db18: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42db1c: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42db20: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42db24: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42db28: 81 ea ff ff 00 00 sub $0xffff,%edx - 42db2e: 0f 85 cc 04 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42db34: 48 83 c1 10 add $0x10,%rcx - 42db38: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42db3c: eb 82 jmp 42dac0 <__strcmp_ssse3+0xcd0> - 42db3e: 66 90 xchg %ax,%ax - 42db40: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 42db44: 66 0f d7 d0 pmovmskb %xmm0,%edx - 42db48: f7 c2 00 f8 00 00 test $0xf800,%edx - 42db4e: 75 10 jne 42db60 <__strcmp_ssse3+0xd70> - 42db50: 66 0f ef c0 pxor %xmm0,%xmm0 - 42db54: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42db5b: e9 66 ff ff ff jmpq 42dac6 <__strcmp_ssse3+0xcd6> - 42db60: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42db65: 66 0f 73 d8 0b psrldq $0xb,%xmm0 - 42db6a: 66 0f 73 db 0b psrldq $0xb,%xmm3 - 42db6f: e9 7c 04 00 00 jmpq 42dff0 <__strcmp_ssse3+0x1200> - 42db74: 66 90 xchg %ax,%ax - 42db76: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42db7d: 00 00 00 - 42db80: 66 0f ef c0 pxor %xmm0,%xmm0 - 42db84: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 42db88: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42db8c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42db90: 66 0f 73 fa 04 pslldq $0x4,%xmm2 - 42db95: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42db99: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42db9d: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 42dba2: d3 ea shr %cl,%edx - 42dba4: 41 d3 e9 shr %cl,%r9d - 42dba7: 44 29 ca sub %r9d,%edx - 42dbaa: 0f 85 55 04 00 00 jne 42e005 <__strcmp_ssse3+0x1215> - 42dbb0: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 42dbb4: 66 0f ef c0 pxor %xmm0,%xmm0 - 42dbb8: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42dbbf: 41 b9 0c 00 00 00 mov $0xc,%r9d - 42dbc5: 4c 8d 57 0c lea 0xc(%rdi),%r10 - 42dbc9: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42dbd0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42dbd7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 42dbde: 00 00 - 42dbe0: 49 83 c2 10 add $0x10,%r10 - 42dbe4: 7f 7a jg 42dc60 <__strcmp_ssse3+0xe70> - 42dbe6: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42dbeb: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42dbf0: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42dbf4: 66 0f 3a 0f d3 0c palignr $0xc,%xmm3,%xmm2 - 42dbfa: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42dbfe: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42dc02: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42dc06: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42dc0a: 81 ea ff ff 00 00 sub $0xffff,%edx - 42dc10: 0f 85 ea 03 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42dc16: 48 83 c1 10 add $0x10,%rcx - 42dc1a: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42dc1e: 49 83 c2 10 add $0x10,%r10 - 42dc22: 7f 3c jg 42dc60 <__strcmp_ssse3+0xe70> - 42dc24: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42dc29: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42dc2e: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42dc32: 66 0f 3a 0f d3 0c palignr $0xc,%xmm3,%xmm2 - 42dc38: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42dc3c: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42dc40: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42dc44: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42dc48: 81 ea ff ff 00 00 sub $0xffff,%edx - 42dc4e: 0f 85 ac 03 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42dc54: 48 83 c1 10 add $0x10,%rcx - 42dc58: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42dc5c: eb 82 jmp 42dbe0 <__strcmp_ssse3+0xdf0> - 42dc5e: 66 90 xchg %ax,%ax - 42dc60: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 42dc64: 66 0f d7 d0 pmovmskb %xmm0,%edx - 42dc68: f7 c2 00 f0 00 00 test $0xf000,%edx - 42dc6e: 75 10 jne 42dc80 <__strcmp_ssse3+0xe90> - 42dc70: 66 0f ef c0 pxor %xmm0,%xmm0 - 42dc74: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42dc7b: e9 66 ff ff ff jmpq 42dbe6 <__strcmp_ssse3+0xdf6> - 42dc80: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42dc85: 66 0f 73 d8 0c psrldq $0xc,%xmm0 - 42dc8a: 66 0f 73 db 0c psrldq $0xc,%xmm3 - 42dc8f: e9 5c 03 00 00 jmpq 42dff0 <__strcmp_ssse3+0x1200> - 42dc94: 66 90 xchg %ax,%ax - 42dc96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42dc9d: 00 00 00 - 42dca0: 66 0f ef c0 pxor %xmm0,%xmm0 - 42dca4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 42dca8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42dcac: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42dcb0: 66 0f 73 fa 03 pslldq $0x3,%xmm2 - 42dcb5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42dcb9: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42dcbd: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 42dcc2: d3 ea shr %cl,%edx - 42dcc4: 41 d3 e9 shr %cl,%r9d - 42dcc7: 44 29 ca sub %r9d,%edx - 42dcca: 0f 85 35 03 00 00 jne 42e005 <__strcmp_ssse3+0x1215> - 42dcd0: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 42dcd4: 66 0f ef c0 pxor %xmm0,%xmm0 - 42dcd8: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42dcdf: 41 b9 0d 00 00 00 mov $0xd,%r9d - 42dce5: 4c 8d 57 0d lea 0xd(%rdi),%r10 - 42dce9: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42dcf0: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42dcf7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 42dcfe: 00 00 - 42dd00: 49 83 c2 10 add $0x10,%r10 - 42dd04: 7f 7a jg 42dd80 <__strcmp_ssse3+0xf90> - 42dd06: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42dd0b: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42dd10: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42dd14: 66 0f 3a 0f d3 0d palignr $0xd,%xmm3,%xmm2 - 42dd1a: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42dd1e: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42dd22: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42dd26: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42dd2a: 81 ea ff ff 00 00 sub $0xffff,%edx - 42dd30: 0f 85 ca 02 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42dd36: 48 83 c1 10 add $0x10,%rcx - 42dd3a: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42dd3e: 49 83 c2 10 add $0x10,%r10 - 42dd42: 7f 3c jg 42dd80 <__strcmp_ssse3+0xf90> - 42dd44: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42dd49: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42dd4e: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42dd52: 66 0f 3a 0f d3 0d palignr $0xd,%xmm3,%xmm2 - 42dd58: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42dd5c: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42dd60: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42dd64: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42dd68: 81 ea ff ff 00 00 sub $0xffff,%edx - 42dd6e: 0f 85 8c 02 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42dd74: 48 83 c1 10 add $0x10,%rcx - 42dd78: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42dd7c: eb 82 jmp 42dd00 <__strcmp_ssse3+0xf10> - 42dd7e: 66 90 xchg %ax,%ax - 42dd80: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 42dd84: 66 0f d7 d0 pmovmskb %xmm0,%edx - 42dd88: f7 c2 00 e0 00 00 test $0xe000,%edx - 42dd8e: 75 10 jne 42dda0 <__strcmp_ssse3+0xfb0> - 42dd90: 66 0f ef c0 pxor %xmm0,%xmm0 - 42dd94: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42dd9b: e9 66 ff ff ff jmpq 42dd06 <__strcmp_ssse3+0xf16> - 42dda0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42dda5: 66 0f 73 d8 0d psrldq $0xd,%xmm0 - 42ddaa: 66 0f 73 db 0d psrldq $0xd,%xmm3 - 42ddaf: e9 3c 02 00 00 jmpq 42dff0 <__strcmp_ssse3+0x1200> - 42ddb4: 66 90 xchg %ax,%ax - 42ddb6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42ddbd: 00 00 00 - 42ddc0: 66 0f ef c0 pxor %xmm0,%xmm0 - 42ddc4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 42ddc8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42ddcc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42ddd0: 66 0f 73 fa 02 pslldq $0x2,%xmm2 - 42ddd5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42ddd9: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42dddd: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 42dde2: d3 ea shr %cl,%edx - 42dde4: 41 d3 e9 shr %cl,%r9d - 42dde7: 44 29 ca sub %r9d,%edx - 42ddea: 0f 85 15 02 00 00 jne 42e005 <__strcmp_ssse3+0x1215> - 42ddf0: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 42ddf4: 66 0f ef c0 pxor %xmm0,%xmm0 - 42ddf8: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42ddff: 41 b9 0e 00 00 00 mov $0xe,%r9d - 42de05: 4c 8d 57 0e lea 0xe(%rdi),%r10 - 42de09: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42de10: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42de17: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 42de1e: 00 00 - 42de20: 49 83 c2 10 add $0x10,%r10 - 42de24: 7f 7a jg 42dea0 <__strcmp_ssse3+0x10b0> - 42de26: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42de2b: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42de30: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42de34: 66 0f 3a 0f d3 0e palignr $0xe,%xmm3,%xmm2 - 42de3a: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42de3e: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42de42: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42de46: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42de4a: 81 ea ff ff 00 00 sub $0xffff,%edx - 42de50: 0f 85 aa 01 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42de56: 48 83 c1 10 add $0x10,%rcx - 42de5a: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42de5e: 49 83 c2 10 add $0x10,%r10 - 42de62: 7f 3c jg 42dea0 <__strcmp_ssse3+0x10b0> - 42de64: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42de69: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42de6e: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42de72: 66 0f 3a 0f d3 0e palignr $0xe,%xmm3,%xmm2 - 42de78: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42de7c: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42de80: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42de84: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42de88: 81 ea ff ff 00 00 sub $0xffff,%edx - 42de8e: 0f 85 6c 01 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42de94: 48 83 c1 10 add $0x10,%rcx - 42de98: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42de9c: eb 82 jmp 42de20 <__strcmp_ssse3+0x1030> - 42de9e: 66 90 xchg %ax,%ax - 42dea0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 42dea4: 66 0f d7 d0 pmovmskb %xmm0,%edx - 42dea8: f7 c2 00 c0 00 00 test $0xc000,%edx - 42deae: 75 10 jne 42dec0 <__strcmp_ssse3+0x10d0> - 42deb0: 66 0f ef c0 pxor %xmm0,%xmm0 - 42deb4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42debb: e9 66 ff ff ff jmpq 42de26 <__strcmp_ssse3+0x1036> - 42dec0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42dec5: 66 0f 73 d8 0e psrldq $0xe,%xmm0 - 42deca: 66 0f 73 db 0e psrldq $0xe,%xmm3 - 42decf: e9 1c 01 00 00 jmpq 42dff0 <__strcmp_ssse3+0x1200> - 42ded4: 66 90 xchg %ax,%ax - 42ded6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42dedd: 00 00 00 - 42dee0: 66 0f ef c0 pxor %xmm0,%xmm0 - 42dee4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 42dee8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42deec: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42def0: 66 0f 73 fa 01 pslldq $0x1,%xmm2 - 42def5: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42def9: 66 0f f8 d0 psubb %xmm0,%xmm2 - 42defd: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 42df02: d3 ea shr %cl,%edx - 42df04: 41 d3 e9 shr %cl,%r9d - 42df07: 44 29 ca sub %r9d,%edx - 42df0a: 0f 85 f5 00 00 00 jne 42e005 <__strcmp_ssse3+0x1215> - 42df10: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 42df14: 66 0f ef c0 pxor %xmm0,%xmm0 - 42df18: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 42df1f: 41 b9 0f 00 00 00 mov $0xf,%r9d - 42df25: 4c 8d 57 0f lea 0xf(%rdi),%r10 - 42df29: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 42df30: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42df37: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 42df3e: 00 00 - 42df40: 49 83 c2 10 add $0x10,%r10 - 42df44: 7f 7a jg 42dfc0 <__strcmp_ssse3+0x11d0> - 42df46: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42df4b: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42df50: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42df54: 66 0f 3a 0f d3 0f palignr $0xf,%xmm3,%xmm2 - 42df5a: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42df5e: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42df62: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42df66: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42df6a: 81 ea ff ff 00 00 sub $0xffff,%edx - 42df70: 0f 85 8a 00 00 00 jne 42e000 <__strcmp_ssse3+0x1210> - 42df76: 48 83 c1 10 add $0x10,%rcx - 42df7a: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42df7e: 49 83 c2 10 add $0x10,%r10 - 42df82: 7f 3c jg 42dfc0 <__strcmp_ssse3+0x11d0> - 42df84: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42df89: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 42df8e: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 42df92: 66 0f 3a 0f d3 0f palignr $0xf,%xmm3,%xmm2 - 42df98: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42df9c: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 42dfa0: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42dfa4: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42dfa8: 81 ea ff ff 00 00 sub $0xffff,%edx - 42dfae: 75 50 jne 42e000 <__strcmp_ssse3+0x1210> - 42dfb0: 48 83 c1 10 add $0x10,%rcx - 42dfb4: 66 0f 6f dc movdqa %xmm4,%xmm3 - 42dfb8: eb 86 jmp 42df40 <__strcmp_ssse3+0x1150> - 42dfba: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 42dfc0: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 42dfc4: 66 0f d7 d0 pmovmskb %xmm0,%edx - 42dfc8: f7 c2 00 80 00 00 test $0x8000,%edx - 42dfce: 75 10 jne 42dfe0 <__strcmp_ssse3+0x11f0> - 42dfd0: 66 0f ef c0 pxor %xmm0,%xmm0 - 42dfd4: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 42dfdb: e9 66 ff ff ff jmpq 42df46 <__strcmp_ssse3+0x1156> - 42dfe0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 42dfe5: 66 0f 73 db 0f psrldq $0xf,%xmm3 - 42dfea: 66 0f 73 d8 0f psrldq $0xf,%xmm0 - 42dfef: 90 nop - 42dff0: 66 0f 74 cb pcmpeqb %xmm3,%xmm1 - 42dff4: 66 0f f8 c8 psubb %xmm0,%xmm1 - 42dff8: 66 0f d7 d1 pmovmskb %xmm1,%edx - 42dffc: f7 d2 not %edx - 42dffe: 66 90 xchg %ax,%ax - 42e000: 49 8d 44 09 f0 lea -0x10(%r9,%rcx,1),%rax - 42e005: 48 8d 3c 07 lea (%rdi,%rax,1),%rdi - 42e009: 48 8d 34 0e lea (%rsi,%rcx,1),%rsi - 42e00d: 45 85 c0 test %r8d,%r8d - 42e010: 74 0e je 42e020 <__strcmp_ssse3+0x1230> - 42e012: 48 87 f7 xchg %rsi,%rdi - 42e015: 90 nop - 42e016: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42e01d: 00 00 00 - 42e020: 48 0f bc d2 bsf %rdx,%rdx - 42e024: 0f b6 0c 16 movzbl (%rsi,%rdx,1),%ecx - 42e028: 0f b6 04 17 movzbl (%rdi,%rdx,1),%eax - 42e02c: 29 c8 sub %ecx,%eax - 42e02e: c3 retq - 42e02f: 31 c0 xor %eax,%eax - 42e031: c3 retq - 42e032: 0f 1f 40 00 nopl 0x0(%rax) - 42e036: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42e03d: 00 00 00 - 42e040: 0f b6 0e movzbl (%rsi),%ecx - 42e043: 0f b6 07 movzbl (%rdi),%eax - 42e046: 29 c8 sub %ecx,%eax - 42e048: c3 retq - 42e049: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - -000000000042e050 <__strcmp_sse2_unaligned>: - 42e050: 89 f8 mov %edi,%eax - 42e052: 31 d2 xor %edx,%edx - 42e054: 66 0f ef ff pxor %xmm7,%xmm7 - 42e058: 09 f0 or %esi,%eax - 42e05a: 25 ff 0f 00 00 and $0xfff,%eax - 42e05f: 3d c0 0f 00 00 cmp $0xfc0,%eax - 42e064: 0f 8f 78 02 00 00 jg 42e2e2 <__strcmp_sse2_unaligned+0x292> - 42e06a: f3 0f 6f 0f movdqu (%rdi),%xmm1 - 42e06e: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 42e072: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42e076: 66 0f da c1 pminub %xmm1,%xmm0 - 42e07a: 66 0f ef c9 pxor %xmm1,%xmm1 - 42e07e: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42e082: 66 0f d7 c0 pmovmskb %xmm0,%eax - 42e086: 48 85 c0 test %rax,%rax - 42e089: 74 15 je 42e0a0 <__strcmp_sse2_unaligned+0x50> - 42e08b: 48 0f bc d0 bsf %rax,%rdx - 42e08f: 0f b6 04 17 movzbl (%rdi,%rdx,1),%eax - 42e093: 0f b6 14 16 movzbl (%rsi,%rdx,1),%edx - 42e097: 29 d0 sub %edx,%eax - 42e099: c3 retq - 42e09a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 42e0a0: f3 0f 6f 77 10 movdqu 0x10(%rdi),%xmm6 - 42e0a5: f3 0f 6f 5e 10 movdqu 0x10(%rsi),%xmm3 - 42e0aa: f3 0f 6f 6f 20 movdqu 0x20(%rdi),%xmm5 - 42e0af: 66 0f 74 de pcmpeqb %xmm6,%xmm3 - 42e0b3: f3 0f 6f 56 20 movdqu 0x20(%rsi),%xmm2 - 42e0b8: 66 0f da de pminub %xmm6,%xmm3 - 42e0bc: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 - 42e0c0: f3 0f 6f 67 30 movdqu 0x30(%rdi),%xmm4 - 42e0c5: 66 0f 74 d5 pcmpeqb %xmm5,%xmm2 - 42e0c9: 66 0f d7 d3 pmovmskb %xmm3,%edx - 42e0cd: f3 0f 6f 46 30 movdqu 0x30(%rsi),%xmm0 - 42e0d2: 66 0f da d5 pminub %xmm5,%xmm2 - 42e0d6: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 42e0da: 66 0f 74 c4 pcmpeqb %xmm4,%xmm0 - 42e0de: 66 0f d7 c2 pmovmskb %xmm2,%eax - 42e0e2: 48 c1 e2 10 shl $0x10,%rdx - 42e0e6: 66 0f da c4 pminub %xmm4,%xmm0 - 42e0ea: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 42e0ee: 48 c1 e0 20 shl $0x20,%rax - 42e0f2: 48 09 d0 or %rdx,%rax - 42e0f5: 66 0f d7 c8 pmovmskb %xmm0,%ecx - 42e0f9: 48 89 ca mov %rcx,%rdx - 42e0fc: 48 c1 e2 30 shl $0x30,%rdx - 42e100: 48 09 d0 or %rdx,%rax - 42e103: 75 86 jne 42e08b <__strcmp_sse2_unaligned+0x3b> - 42e105: 48 8d 57 40 lea 0x40(%rdi),%rdx - 42e109: b9 00 10 00 00 mov $0x1000,%ecx - 42e10e: 66 45 0f ef c9 pxor %xmm9,%xmm9 - 42e113: 48 83 e2 c0 and $0xffffffffffffffc0,%rdx - 42e117: 48 29 fa sub %rdi,%rdx - 42e11a: 48 8d 04 17 lea (%rdi,%rdx,1),%rax - 42e11e: 48 01 f2 add %rsi,%rdx - 42e121: 48 89 d6 mov %rdx,%rsi - 42e124: 81 e6 ff 0f 00 00 and $0xfff,%esi - 42e12a: 48 29 f1 sub %rsi,%rcx - 42e12d: 48 c1 e9 06 shr $0x6,%rcx - 42e131: 48 89 ce mov %rcx,%rsi - 42e134: eb 12 jmp 42e148 <__strcmp_sse2_unaligned+0xf8> - 42e136: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42e13d: 00 00 00 - 42e140: 48 83 c0 40 add $0x40,%rax - 42e144: 48 83 c2 40 add $0x40,%rdx - 42e148: 48 85 f6 test %rsi,%rsi - 42e14b: 48 8d 76 ff lea -0x1(%rsi),%rsi - 42e14f: 0f 84 bb 00 00 00 je 42e210 <__strcmp_sse2_unaligned+0x1c0> - 42e155: f3 0f 6f 02 movdqu (%rdx),%xmm0 - 42e159: f3 0f 6f 4a 10 movdqu 0x10(%rdx),%xmm1 - 42e15e: 66 0f 6f 10 movdqa (%rax),%xmm2 - 42e162: 66 0f 6f 58 10 movdqa 0x10(%rax),%xmm3 - 42e167: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 42e16b: f3 0f 6f 6a 20 movdqu 0x20(%rdx),%xmm5 - 42e170: 66 0f 74 cb pcmpeqb %xmm3,%xmm1 - 42e174: 66 0f da c2 pminub %xmm2,%xmm0 - 42e178: f3 0f 6f 72 30 movdqu 0x30(%rdx),%xmm6 - 42e17d: 66 0f da cb pminub %xmm3,%xmm1 - 42e181: 66 0f 6f 50 20 movdqa 0x20(%rax),%xmm2 - 42e186: 66 0f da c1 pminub %xmm1,%xmm0 - 42e18a: 66 0f 6f 58 30 movdqa 0x30(%rax),%xmm3 - 42e18f: 66 0f 74 ea pcmpeqb %xmm2,%xmm5 - 42e193: 66 0f 74 f3 pcmpeqb %xmm3,%xmm6 - 42e197: 66 0f da ea pminub %xmm2,%xmm5 - 42e19b: 66 0f da f3 pminub %xmm3,%xmm6 - 42e19f: 66 0f da c5 pminub %xmm5,%xmm0 - 42e1a3: 66 0f da c6 pminub %xmm6,%xmm0 - 42e1a7: 66 0f 74 c7 pcmpeqb %xmm7,%xmm0 - 42e1ab: 66 0f d7 c8 pmovmskb %xmm0,%ecx - 42e1af: 85 c9 test %ecx,%ecx - 42e1b1: 74 8d je 42e140 <__strcmp_sse2_unaligned+0xf0> - 42e1b3: 66 0f 74 ef pcmpeqb %xmm7,%xmm5 - 42e1b7: f3 0f 6f 02 movdqu (%rdx),%xmm0 - 42e1bb: 66 0f 74 cf pcmpeqb %xmm7,%xmm1 - 42e1bf: 66 0f 6f 10 movdqa (%rax),%xmm2 - 42e1c3: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 42e1c7: 66 0f da c2 pminub %xmm2,%xmm0 - 42e1cb: 66 0f 74 f7 pcmpeqb %xmm7,%xmm6 - 42e1cf: 66 0f 74 c7 pcmpeqb %xmm7,%xmm0 - 42e1d3: 66 0f d7 c9 pmovmskb %xmm1,%ecx - 42e1d7: 66 44 0f d7 c5 pmovmskb %xmm5,%r8d - 42e1dc: 66 0f d7 f8 pmovmskb %xmm0,%edi - 42e1e0: 48 c1 e1 10 shl $0x10,%rcx - 42e1e4: 49 c1 e0 20 shl $0x20,%r8 - 42e1e8: 66 0f d7 f6 pmovmskb %xmm6,%esi - 42e1ec: 4c 09 c1 or %r8,%rcx - 42e1ef: 48 09 f9 or %rdi,%rcx - 42e1f2: 48 c1 e6 30 shl $0x30,%rsi - 42e1f6: 48 09 f1 or %rsi,%rcx - 42e1f9: 48 0f bc c9 bsf %rcx,%rcx - 42e1fd: 0f b6 04 08 movzbl (%rax,%rcx,1),%eax - 42e201: 0f b6 14 0a movzbl (%rdx,%rcx,1),%edx - 42e205: 29 d0 sub %edx,%eax - 42e207: c3 retq - 42e208: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 42e20f: 00 - 42e210: 4d 31 d2 xor %r10,%r10 - 42e213: 49 89 d1 mov %rdx,%r9 - 42e216: 49 83 e1 3f and $0x3f,%r9 - 42e21a: 4d 29 ca sub %r9,%r10 - 42e21d: 66 42 0f 6f 04 12 movdqa (%rdx,%r10,1),%xmm0 - 42e223: 66 42 0f 6f 4c 12 10 movdqa 0x10(%rdx,%r10,1),%xmm1 - 42e22a: f3 42 0f 6f 14 10 movdqu (%rax,%r10,1),%xmm2 - 42e230: f3 42 0f 6f 5c 10 10 movdqu 0x10(%rax,%r10,1),%xmm3 - 42e237: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 42e23b: 66 42 0f 6f 6c 12 20 movdqa 0x20(%rdx,%r10,1),%xmm5 - 42e242: 66 0f 74 cb pcmpeqb %xmm3,%xmm1 - 42e246: 66 0f da c2 pminub %xmm2,%xmm0 - 42e24a: 66 42 0f 6f 74 12 30 movdqa 0x30(%rdx,%r10,1),%xmm6 - 42e251: 66 0f da cb pminub %xmm3,%xmm1 - 42e255: f3 42 0f 6f 54 10 20 movdqu 0x20(%rax,%r10,1),%xmm2 - 42e25c: f3 42 0f 6f 5c 10 30 movdqu 0x30(%rax,%r10,1),%xmm3 - 42e263: 66 0f 74 ea pcmpeqb %xmm2,%xmm5 - 42e267: 66 0f 74 f3 pcmpeqb %xmm3,%xmm6 - 42e26b: 66 0f da ea pminub %xmm2,%xmm5 - 42e26f: 66 0f da f3 pminub %xmm3,%xmm6 - 42e273: 66 0f 74 c7 pcmpeqb %xmm7,%xmm0 - 42e277: 66 0f 74 cf pcmpeqb %xmm7,%xmm1 - 42e27b: 66 0f 74 ef pcmpeqb %xmm7,%xmm5 - 42e27f: 66 0f 74 f7 pcmpeqb %xmm7,%xmm6 - 42e283: 66 0f d7 c9 pmovmskb %xmm1,%ecx - 42e287: 66 44 0f d7 c5 pmovmskb %xmm5,%r8d - 42e28c: 66 0f d7 f8 pmovmskb %xmm0,%edi - 42e290: 48 c1 e1 10 shl $0x10,%rcx - 42e294: 49 c1 e0 20 shl $0x20,%r8 - 42e298: 66 0f d7 f6 pmovmskb %xmm6,%esi - 42e29c: 4c 09 c7 or %r8,%rdi - 42e29f: 48 09 cf or %rcx,%rdi - 42e2a2: 48 c1 e6 30 shl $0x30,%rsi - 42e2a6: 48 09 f7 or %rsi,%rdi - 42e2a9: 4c 89 c9 mov %r9,%rcx - 42e2ac: 48 c7 c6 3f 00 00 00 mov $0x3f,%rsi - 42e2b3: 48 d3 ef shr %cl,%rdi - 42e2b6: 48 85 ff test %rdi,%rdi - 42e2b9: 0f 84 96 fe ff ff je 42e155 <__strcmp_sse2_unaligned+0x105> - 42e2bf: 48 0f bc cf bsf %rdi,%rcx - 42e2c3: 0f b6 04 08 movzbl (%rax,%rcx,1),%eax - 42e2c7: 0f b6 14 0a movzbl (%rdx,%rcx,1),%edx - 42e2cb: 29 d0 sub %edx,%eax - 42e2cd: c3 retq - 42e2ce: 66 90 xchg %ax,%ax - 42e2d0: 38 c8 cmp %cl,%al - 42e2d2: 75 1c jne 42e2f0 <__strcmp_sse2_unaligned+0x2a0> - 42e2d4: 48 83 c2 01 add $0x1,%rdx - 42e2d8: 48 83 fa 40 cmp $0x40,%rdx - 42e2dc: 0f 84 23 fe ff ff je 42e105 <__strcmp_sse2_unaligned+0xb5> - 42e2e2: 0f b6 04 17 movzbl (%rdi,%rdx,1),%eax - 42e2e6: 0f b6 0c 16 movzbl (%rsi,%rdx,1),%ecx - 42e2ea: 84 c0 test %al,%al - 42e2ec: 75 e2 jne 42e2d0 <__strcmp_sse2_unaligned+0x280> - 42e2ee: 31 c0 xor %eax,%eax - 42e2f0: 29 c8 sub %ecx,%eax - 42e2f2: c3 retq - 42e2f3: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42e2fa: 00 00 00 - 42e2fd: 0f 1f 00 nopl (%rax) - -000000000042e300 <__memcmp_sse4_1>: - 42e300: 66 0f ef c0 pxor %xmm0,%xmm0 - 42e304: 48 83 fa 4f cmp $0x4f,%rdx - 42e308: 77 36 ja 42e340 <__memcmp_sse4_1+0x40> - 42e30a: 48 83 fa 01 cmp $0x1,%rdx - 42e30e: 74 20 je 42e330 <__memcmp_sse4_1+0x30> - 42e310: 48 01 d6 add %rdx,%rsi - 42e313: 48 01 d7 add %rdx,%rdi - 42e316: 4c 8d 1d 53 4f 07 00 lea 0x74f53(%rip),%r11 # 4a3270 - 42e31d: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx - 42e321: 4c 01 d9 add %r11,%rcx - 42e324: ff e1 jmpq *%rcx - 42e326: 0f 0b ud2 - 42e328: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 42e32f: 00 - 42e330: 0f b6 07 movzbl (%rdi),%eax - 42e333: 0f b6 0e movzbl (%rsi),%ecx - 42e336: 29 c8 sub %ecx,%eax - 42e338: c3 retq - 42e339: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 42e340: f3 0f 6f 0e movdqu (%rsi),%xmm1 - 42e344: f3 0f 6f 17 movdqu (%rdi),%xmm2 - 42e348: 66 0f ef d1 pxor %xmm1,%xmm2 - 42e34c: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e351: 0f 83 56 0b 00 00 jae 42eead <__memcmp_sse4_1+0xbad> - 42e357: 48 89 f1 mov %rsi,%rcx - 42e35a: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi - 42e35e: 48 83 c6 10 add $0x10,%rsi - 42e362: 48 29 f1 sub %rsi,%rcx - 42e365: 48 29 cf sub %rcx,%rdi - 42e368: 48 01 ca add %rcx,%rdx - 42e36b: 48 f7 c7 0f 00 00 00 test $0xf,%rdi - 42e372: 0f 84 08 05 00 00 je 42e880 <__memcmp_sse4_1+0x580> - 42e378: 48 81 fa 80 00 00 00 cmp $0x80,%rdx - 42e37f: 0f 87 b2 00 00 00 ja 42e437 <__memcmp_sse4_1+0x137> - 42e385: 48 83 ea 40 sub $0x40,%rdx - 42e389: f3 0f 6f 17 movdqu (%rdi),%xmm2 - 42e38d: 66 0f ef 16 pxor (%rsi),%xmm2 - 42e391: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e396: 0f 83 11 0b 00 00 jae 42eead <__memcmp_sse4_1+0xbad> - 42e39c: f3 0f 6f 57 10 movdqu 0x10(%rdi),%xmm2 - 42e3a1: 66 0f ef 56 10 pxor 0x10(%rsi),%xmm2 - 42e3a6: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e3ab: 0f 83 f4 0a 00 00 jae 42eea5 <__memcmp_sse4_1+0xba5> - 42e3b1: f3 0f 6f 57 20 movdqu 0x20(%rdi),%xmm2 - 42e3b6: 66 0f ef 56 20 pxor 0x20(%rsi),%xmm2 - 42e3bb: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e3c0: 0f 83 d7 0a 00 00 jae 42ee9d <__memcmp_sse4_1+0xb9d> - 42e3c6: f3 0f 6f 57 30 movdqu 0x30(%rdi),%xmm2 - 42e3cb: 66 0f ef 56 30 pxor 0x30(%rsi),%xmm2 - 42e3d0: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e3d5: 0f 83 b8 0a 00 00 jae 42ee93 <__memcmp_sse4_1+0xb93> - 42e3db: 48 83 fa 20 cmp $0x20,%rdx - 42e3df: 72 36 jb 42e417 <__memcmp_sse4_1+0x117> - 42e3e1: f3 0f 6f 57 40 movdqu 0x40(%rdi),%xmm2 - 42e3e6: 66 0f ef 56 40 pxor 0x40(%rsi),%xmm2 - 42e3eb: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e3f0: 0f 83 93 0a 00 00 jae 42ee89 <__memcmp_sse4_1+0xb89> - 42e3f6: f3 0f 6f 57 50 movdqu 0x50(%rdi),%xmm2 - 42e3fb: 66 0f ef 56 50 pxor 0x50(%rsi),%xmm2 - 42e400: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e405: 0f 83 74 0a 00 00 jae 42ee7f <__memcmp_sse4_1+0xb7f> - 42e40b: 48 83 ea 20 sub $0x20,%rdx - 42e40f: 48 83 c7 20 add $0x20,%rdi - 42e413: 48 83 c6 20 add $0x20,%rsi - 42e417: 48 83 c7 40 add $0x40,%rdi - 42e41b: 48 83 c6 40 add $0x40,%rsi - 42e41f: 48 01 d6 add %rdx,%rsi - 42e422: 48 01 d7 add %rdx,%rdi - 42e425: 4c 8d 1d 44 4e 07 00 lea 0x74e44(%rip),%r11 # 4a3270 - 42e42c: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx - 42e430: 4c 01 d9 add %r11,%rcx - 42e433: ff e1 jmpq *%rcx - 42e435: 0f 0b ud2 - 42e437: 48 81 fa 00 02 00 00 cmp $0x200,%rdx - 42e43e: 0f 87 2c 03 00 00 ja 42e770 <__memcmp_sse4_1+0x470> - 42e444: 48 81 fa 00 01 00 00 cmp $0x100,%rdx - 42e44b: 0f 87 17 01 00 00 ja 42e568 <__memcmp_sse4_1+0x268> - 42e451: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 42e458: f3 0f 6f 17 movdqu (%rdi),%xmm2 - 42e45c: 66 0f ef 16 pxor (%rsi),%xmm2 - 42e460: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e465: 0f 83 42 0a 00 00 jae 42eead <__memcmp_sse4_1+0xbad> - 42e46b: f3 0f 6f 57 10 movdqu 0x10(%rdi),%xmm2 - 42e470: 66 0f ef 56 10 pxor 0x10(%rsi),%xmm2 - 42e475: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e47a: 0f 83 25 0a 00 00 jae 42eea5 <__memcmp_sse4_1+0xba5> - 42e480: f3 0f 6f 57 20 movdqu 0x20(%rdi),%xmm2 - 42e485: 66 0f ef 56 20 pxor 0x20(%rsi),%xmm2 - 42e48a: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e48f: 0f 83 08 0a 00 00 jae 42ee9d <__memcmp_sse4_1+0xb9d> - 42e495: f3 0f 6f 57 30 movdqu 0x30(%rdi),%xmm2 - 42e49a: 66 0f ef 56 30 pxor 0x30(%rsi),%xmm2 - 42e49f: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e4a4: 0f 83 e9 09 00 00 jae 42ee93 <__memcmp_sse4_1+0xb93> - 42e4aa: f3 0f 6f 57 40 movdqu 0x40(%rdi),%xmm2 - 42e4af: 66 0f ef 56 40 pxor 0x40(%rsi),%xmm2 - 42e4b4: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e4b9: 0f 83 ca 09 00 00 jae 42ee89 <__memcmp_sse4_1+0xb89> - 42e4bf: f3 0f 6f 57 50 movdqu 0x50(%rdi),%xmm2 - 42e4c4: 66 0f ef 56 50 pxor 0x50(%rsi),%xmm2 - 42e4c9: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e4ce: 0f 83 ab 09 00 00 jae 42ee7f <__memcmp_sse4_1+0xb7f> - 42e4d4: f3 0f 6f 57 60 movdqu 0x60(%rdi),%xmm2 - 42e4d9: 66 0f ef 56 60 pxor 0x60(%rsi),%xmm2 - 42e4de: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e4e3: 0f 83 8c 09 00 00 jae 42ee75 <__memcmp_sse4_1+0xb75> - 42e4e9: f3 0f 6f 57 70 movdqu 0x70(%rdi),%xmm2 - 42e4ee: 66 0f ef 56 70 pxor 0x70(%rsi),%xmm2 - 42e4f3: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e4f8: 0f 83 67 09 00 00 jae 42ee65 <__memcmp_sse4_1+0xb65> - 42e4fe: 48 81 c6 80 00 00 00 add $0x80,%rsi - 42e505: 48 81 c7 80 00 00 00 add $0x80,%rdi - 42e50c: 48 83 fa 40 cmp $0x40,%rdx - 42e510: 0f 83 6f fe ff ff jae 42e385 <__memcmp_sse4_1+0x85> - 42e516: 48 83 fa 20 cmp $0x20,%rdx - 42e51a: 72 34 jb 42e550 <__memcmp_sse4_1+0x250> - 42e51c: f3 0f 6f 17 movdqu (%rdi),%xmm2 - 42e520: 66 0f ef 16 pxor (%rsi),%xmm2 - 42e524: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e529: 0f 83 7e 09 00 00 jae 42eead <__memcmp_sse4_1+0xbad> - 42e52f: f3 0f 6f 57 10 movdqu 0x10(%rdi),%xmm2 - 42e534: 66 0f ef 56 10 pxor 0x10(%rsi),%xmm2 - 42e539: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e53e: 0f 83 61 09 00 00 jae 42eea5 <__memcmp_sse4_1+0xba5> - 42e544: 48 83 ea 20 sub $0x20,%rdx - 42e548: 48 83 c7 20 add $0x20,%rdi - 42e54c: 48 83 c6 20 add $0x20,%rsi - 42e550: 48 01 d6 add %rdx,%rsi - 42e553: 48 01 d7 add %rdx,%rdi - 42e556: 4c 8d 1d 13 4d 07 00 lea 0x74d13(%rip),%r11 # 4a3270 - 42e55d: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx - 42e561: 4c 01 d9 add %r11,%rcx - 42e564: ff e1 jmpq *%rcx - 42e566: 0f 0b ud2 - 42e568: 48 81 ea 00 01 00 00 sub $0x100,%rdx - 42e56f: f3 0f 6f 17 movdqu (%rdi),%xmm2 - 42e573: 66 0f ef 16 pxor (%rsi),%xmm2 - 42e577: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e57c: 0f 83 2b 09 00 00 jae 42eead <__memcmp_sse4_1+0xbad> - 42e582: f3 0f 6f 57 10 movdqu 0x10(%rdi),%xmm2 - 42e587: 66 0f ef 56 10 pxor 0x10(%rsi),%xmm2 - 42e58c: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e591: 0f 83 0e 09 00 00 jae 42eea5 <__memcmp_sse4_1+0xba5> - 42e597: f3 0f 6f 57 20 movdqu 0x20(%rdi),%xmm2 - 42e59c: 66 0f ef 56 20 pxor 0x20(%rsi),%xmm2 - 42e5a1: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e5a6: 0f 83 f1 08 00 00 jae 42ee9d <__memcmp_sse4_1+0xb9d> - 42e5ac: f3 0f 6f 57 30 movdqu 0x30(%rdi),%xmm2 - 42e5b1: 66 0f ef 56 30 pxor 0x30(%rsi),%xmm2 - 42e5b6: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e5bb: 0f 83 d2 08 00 00 jae 42ee93 <__memcmp_sse4_1+0xb93> - 42e5c1: f3 0f 6f 57 40 movdqu 0x40(%rdi),%xmm2 - 42e5c6: 66 0f ef 56 40 pxor 0x40(%rsi),%xmm2 - 42e5cb: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e5d0: 0f 83 b3 08 00 00 jae 42ee89 <__memcmp_sse4_1+0xb89> - 42e5d6: f3 0f 6f 57 50 movdqu 0x50(%rdi),%xmm2 - 42e5db: 66 0f ef 56 50 pxor 0x50(%rsi),%xmm2 - 42e5e0: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e5e5: 0f 83 94 08 00 00 jae 42ee7f <__memcmp_sse4_1+0xb7f> - 42e5eb: f3 0f 6f 57 60 movdqu 0x60(%rdi),%xmm2 - 42e5f0: 66 0f ef 56 60 pxor 0x60(%rsi),%xmm2 - 42e5f5: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e5fa: 0f 83 75 08 00 00 jae 42ee75 <__memcmp_sse4_1+0xb75> - 42e600: f3 0f 6f 57 70 movdqu 0x70(%rdi),%xmm2 - 42e605: 66 0f ef 56 70 pxor 0x70(%rsi),%xmm2 - 42e60a: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e60f: 0f 83 50 08 00 00 jae 42ee65 <__memcmp_sse4_1+0xb65> - 42e615: f3 0f 6f 97 80 00 00 movdqu 0x80(%rdi),%xmm2 - 42e61c: 00 - 42e61d: 66 0f ef 96 80 00 00 pxor 0x80(%rsi),%xmm2 - 42e624: 00 - 42e625: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e62a: 0f 83 25 08 00 00 jae 42ee55 <__memcmp_sse4_1+0xb55> - 42e630: f3 0f 6f 97 90 00 00 movdqu 0x90(%rdi),%xmm2 - 42e637: 00 - 42e638: 66 0f ef 96 90 00 00 pxor 0x90(%rsi),%xmm2 - 42e63f: 00 - 42e640: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e645: 0f 83 fa 07 00 00 jae 42ee45 <__memcmp_sse4_1+0xb45> - 42e64b: f3 0f 6f 97 a0 00 00 movdqu 0xa0(%rdi),%xmm2 - 42e652: 00 - 42e653: 66 0f ef 96 a0 00 00 pxor 0xa0(%rsi),%xmm2 - 42e65a: 00 - 42e65b: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e660: 0f 83 cf 07 00 00 jae 42ee35 <__memcmp_sse4_1+0xb35> - 42e666: f3 0f 6f 97 b0 00 00 movdqu 0xb0(%rdi),%xmm2 - 42e66d: 00 - 42e66e: 66 0f ef 96 b0 00 00 pxor 0xb0(%rsi),%xmm2 - 42e675: 00 - 42e676: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e67b: 0f 83 a1 07 00 00 jae 42ee22 <__memcmp_sse4_1+0xb22> - 42e681: f3 0f 6f 97 c0 00 00 movdqu 0xc0(%rdi),%xmm2 - 42e688: 00 - 42e689: 66 0f ef 96 c0 00 00 pxor 0xc0(%rsi),%xmm2 - 42e690: 00 - 42e691: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e696: 0f 83 73 07 00 00 jae 42ee0f <__memcmp_sse4_1+0xb0f> - 42e69c: f3 0f 6f 97 d0 00 00 movdqu 0xd0(%rdi),%xmm2 - 42e6a3: 00 - 42e6a4: 66 0f ef 96 d0 00 00 pxor 0xd0(%rsi),%xmm2 - 42e6ab: 00 - 42e6ac: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e6b1: 0f 83 45 07 00 00 jae 42edfc <__memcmp_sse4_1+0xafc> - 42e6b7: f3 0f 6f 97 e0 00 00 movdqu 0xe0(%rdi),%xmm2 - 42e6be: 00 - 42e6bf: 66 0f ef 96 e0 00 00 pxor 0xe0(%rsi),%xmm2 - 42e6c6: 00 - 42e6c7: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e6cc: 0f 83 17 07 00 00 jae 42ede9 <__memcmp_sse4_1+0xae9> - 42e6d2: f3 0f 6f 97 f0 00 00 movdqu 0xf0(%rdi),%xmm2 - 42e6d9: 00 - 42e6da: 66 0f ef 96 f0 00 00 pxor 0xf0(%rsi),%xmm2 - 42e6e1: 00 - 42e6e2: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e6e7: 0f 83 e9 06 00 00 jae 42edd6 <__memcmp_sse4_1+0xad6> - 42e6ed: 48 81 c6 00 01 00 00 add $0x100,%rsi - 42e6f4: 48 81 c7 00 01 00 00 add $0x100,%rdi - 42e6fb: 48 81 fa 80 00 00 00 cmp $0x80,%rdx - 42e702: 0f 83 49 fd ff ff jae 42e451 <__memcmp_sse4_1+0x151> - 42e708: 48 83 fa 40 cmp $0x40,%rdx - 42e70c: 0f 83 73 fc ff ff jae 42e385 <__memcmp_sse4_1+0x85> - 42e712: 48 83 fa 20 cmp $0x20,%rdx - 42e716: 72 34 jb 42e74c <__memcmp_sse4_1+0x44c> - 42e718: f3 0f 6f 17 movdqu (%rdi),%xmm2 - 42e71c: 66 0f ef 16 pxor (%rsi),%xmm2 - 42e720: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e725: 0f 83 82 07 00 00 jae 42eead <__memcmp_sse4_1+0xbad> - 42e72b: f3 0f 6f 57 10 movdqu 0x10(%rdi),%xmm2 - 42e730: 66 0f ef 56 10 pxor 0x10(%rsi),%xmm2 - 42e735: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e73a: 0f 83 65 07 00 00 jae 42eea5 <__memcmp_sse4_1+0xba5> - 42e740: 48 83 ea 20 sub $0x20,%rdx - 42e744: 48 83 c7 20 add $0x20,%rdi - 42e748: 48 83 c6 20 add $0x20,%rsi - 42e74c: 48 01 d6 add %rdx,%rsi - 42e74f: 48 01 d7 add %rdx,%rdi - 42e752: 4c 8d 1d 17 4b 07 00 lea 0x74b17(%rip),%r11 # 4a3270 - 42e759: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx - 42e75d: 4c 01 d9 add %r11,%rcx - 42e760: ff e1 jmpq *%rcx - 42e762: 0f 0b ud2 - 42e764: 66 90 xchg %ax,%ax - 42e766: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42e76d: 00 00 00 - 42e770: 4c 8b 05 59 c9 29 00 mov 0x29c959(%rip),%r8 # 6cb0d0 <__x86_data_cache_size_half> - 42e777: 4d 89 c1 mov %r8,%r9 - 42e77a: 49 d1 e8 shr %r8 - 42e77d: 4d 01 c8 add %r9,%r8 - 42e780: 4c 39 c2 cmp %r8,%rdx - 42e783: 77 76 ja 42e7fb <__memcmp_sse4_1+0x4fb> - 42e785: 48 83 ea 40 sub $0x40,%rdx - 42e789: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 42e790: f3 0f 6f 17 movdqu (%rdi),%xmm2 - 42e794: 66 0f ef 16 pxor (%rsi),%xmm2 - 42e798: 66 0f 6f ca movdqa %xmm2,%xmm1 - 42e79c: f3 0f 6f 5f 10 movdqu 0x10(%rdi),%xmm3 - 42e7a1: 66 0f ef 5e 10 pxor 0x10(%rsi),%xmm3 - 42e7a6: 66 0f eb cb por %xmm3,%xmm1 - 42e7aa: f3 0f 6f 67 20 movdqu 0x20(%rdi),%xmm4 - 42e7af: 66 0f ef 66 20 pxor 0x20(%rsi),%xmm4 - 42e7b4: 66 0f eb cc por %xmm4,%xmm1 - 42e7b8: f3 0f 6f 6f 30 movdqu 0x30(%rdi),%xmm5 - 42e7bd: 66 0f ef 6e 30 pxor 0x30(%rsi),%xmm5 - 42e7c2: 66 0f eb cd por %xmm5,%xmm1 - 42e7c6: 66 0f 38 17 c1 ptest %xmm1,%xmm0 - 42e7cb: 0f 83 bf 05 00 00 jae 42ed90 <__memcmp_sse4_1+0xa90> - 42e7d1: 48 83 c6 40 add $0x40,%rsi - 42e7d5: 48 83 c7 40 add $0x40,%rdi - 42e7d9: 48 83 ea 40 sub $0x40,%rdx - 42e7dd: 73 b1 jae 42e790 <__memcmp_sse4_1+0x490> - 42e7df: 48 83 c2 40 add $0x40,%rdx - 42e7e3: 48 01 d6 add %rdx,%rsi - 42e7e6: 48 01 d7 add %rdx,%rdi - 42e7e9: 4c 8d 1d 80 4a 07 00 lea 0x74a80(%rip),%r11 # 4a3270 - 42e7f0: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx - 42e7f4: 4c 01 d9 add %r11,%rcx - 42e7f7: ff e1 jmpq *%rcx - 42e7f9: 0f 0b ud2 - 42e7fb: 48 83 ea 40 sub $0x40,%rdx - 42e7ff: 90 nop - 42e800: 0f 18 87 c0 01 00 00 prefetchnta 0x1c0(%rdi) - 42e807: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) - 42e80e: f3 0f 6f 17 movdqu (%rdi),%xmm2 - 42e812: 66 0f ef 16 pxor (%rsi),%xmm2 - 42e816: 66 0f 6f ca movdqa %xmm2,%xmm1 - 42e81a: f3 0f 6f 5f 10 movdqu 0x10(%rdi),%xmm3 - 42e81f: 66 0f ef 5e 10 pxor 0x10(%rsi),%xmm3 - 42e824: 66 0f eb cb por %xmm3,%xmm1 - 42e828: f3 0f 6f 67 20 movdqu 0x20(%rdi),%xmm4 - 42e82d: 66 0f ef 66 20 pxor 0x20(%rsi),%xmm4 - 42e832: 66 0f eb cc por %xmm4,%xmm1 - 42e836: f3 0f 6f 6f 30 movdqu 0x30(%rdi),%xmm5 - 42e83b: 66 0f ef 6e 30 pxor 0x30(%rsi),%xmm5 - 42e840: 66 0f eb cd por %xmm5,%xmm1 - 42e844: 66 0f 38 17 c1 ptest %xmm1,%xmm0 - 42e849: 0f 83 41 05 00 00 jae 42ed90 <__memcmp_sse4_1+0xa90> - 42e84f: 48 83 c6 40 add $0x40,%rsi - 42e853: 48 83 c7 40 add $0x40,%rdi - 42e857: 48 83 ea 40 sub $0x40,%rdx - 42e85b: 73 a3 jae 42e800 <__memcmp_sse4_1+0x500> - 42e85d: 48 83 c2 40 add $0x40,%rdx - 42e861: 48 01 d6 add %rdx,%rsi - 42e864: 48 01 d7 add %rdx,%rdi - 42e867: 4c 8d 1d 02 4a 07 00 lea 0x74a02(%rip),%r11 # 4a3270 - 42e86e: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx - 42e872: 4c 01 d9 add %r11,%rcx - 42e875: ff e1 jmpq *%rcx - 42e877: 0f 0b ud2 - 42e879: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 42e880: 48 81 fa 80 00 00 00 cmp $0x80,%rdx - 42e887: 0f 87 b3 00 00 00 ja 42e940 <__memcmp_sse4_1+0x640> - 42e88d: 48 83 ea 40 sub $0x40,%rdx - 42e891: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 42e895: 66 0f ef 16 pxor (%rsi),%xmm2 - 42e899: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e89e: 0f 83 09 06 00 00 jae 42eead <__memcmp_sse4_1+0xbad> - 42e8a4: 66 0f 6f 57 10 movdqa 0x10(%rdi),%xmm2 - 42e8a9: 66 0f ef 56 10 pxor 0x10(%rsi),%xmm2 - 42e8ae: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e8b3: 0f 83 ec 05 00 00 jae 42eea5 <__memcmp_sse4_1+0xba5> - 42e8b9: 66 0f 6f 57 20 movdqa 0x20(%rdi),%xmm2 - 42e8be: 66 0f ef 56 20 pxor 0x20(%rsi),%xmm2 - 42e8c3: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e8c8: 0f 83 cf 05 00 00 jae 42ee9d <__memcmp_sse4_1+0xb9d> - 42e8ce: 66 0f 6f 57 30 movdqa 0x30(%rdi),%xmm2 - 42e8d3: 66 0f ef 56 30 pxor 0x30(%rsi),%xmm2 - 42e8d8: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e8dd: 0f 83 b0 05 00 00 jae 42ee93 <__memcmp_sse4_1+0xb93> - 42e8e3: 48 83 fa 20 cmp $0x20,%rdx - 42e8e7: 72 36 jb 42e91f <__memcmp_sse4_1+0x61f> - 42e8e9: 66 0f 6f 57 40 movdqa 0x40(%rdi),%xmm2 - 42e8ee: 66 0f ef 56 40 pxor 0x40(%rsi),%xmm2 - 42e8f3: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e8f8: 0f 83 8b 05 00 00 jae 42ee89 <__memcmp_sse4_1+0xb89> - 42e8fe: 66 0f 6f 57 50 movdqa 0x50(%rdi),%xmm2 - 42e903: 66 0f ef 56 50 pxor 0x50(%rsi),%xmm2 - 42e908: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e90d: 0f 83 6c 05 00 00 jae 42ee7f <__memcmp_sse4_1+0xb7f> - 42e913: 48 83 ea 20 sub $0x20,%rdx - 42e917: 48 83 c7 20 add $0x20,%rdi - 42e91b: 48 83 c6 20 add $0x20,%rsi - 42e91f: 48 83 c7 40 add $0x40,%rdi - 42e923: 48 83 c6 40 add $0x40,%rsi - 42e927: 48 01 d6 add %rdx,%rsi - 42e92a: 48 01 d7 add %rdx,%rdi - 42e92d: 4c 8d 1d 3c 49 07 00 lea 0x7493c(%rip),%r11 # 4a3270 - 42e934: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx - 42e938: 4c 01 d9 add %r11,%rcx - 42e93b: ff e1 jmpq *%rcx - 42e93d: 0f 0b ud2 - 42e93f: 90 nop - 42e940: 48 81 fa 00 02 00 00 cmp $0x200,%rdx - 42e947: 0f 87 33 03 00 00 ja 42ec80 <__memcmp_sse4_1+0x980> - 42e94d: 48 81 fa 00 01 00 00 cmp $0x100,%rdx - 42e954: 0f 87 26 01 00 00 ja 42ea80 <__memcmp_sse4_1+0x780> - 42e95a: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 42e961: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 42e965: 66 0f ef 16 pxor (%rsi),%xmm2 - 42e969: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e96e: 0f 83 39 05 00 00 jae 42eead <__memcmp_sse4_1+0xbad> - 42e974: 66 0f 6f 57 10 movdqa 0x10(%rdi),%xmm2 - 42e979: 66 0f ef 56 10 pxor 0x10(%rsi),%xmm2 - 42e97e: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e983: 0f 83 1c 05 00 00 jae 42eea5 <__memcmp_sse4_1+0xba5> - 42e989: 66 0f 6f 57 20 movdqa 0x20(%rdi),%xmm2 - 42e98e: 66 0f ef 56 20 pxor 0x20(%rsi),%xmm2 - 42e993: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e998: 0f 83 ff 04 00 00 jae 42ee9d <__memcmp_sse4_1+0xb9d> - 42e99e: 66 0f 6f 57 30 movdqa 0x30(%rdi),%xmm2 - 42e9a3: 66 0f ef 56 30 pxor 0x30(%rsi),%xmm2 - 42e9a8: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e9ad: 0f 83 e0 04 00 00 jae 42ee93 <__memcmp_sse4_1+0xb93> - 42e9b3: 66 0f 6f 57 40 movdqa 0x40(%rdi),%xmm2 - 42e9b8: 66 0f ef 56 40 pxor 0x40(%rsi),%xmm2 - 42e9bd: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e9c2: 0f 83 c1 04 00 00 jae 42ee89 <__memcmp_sse4_1+0xb89> - 42e9c8: 66 0f 6f 57 50 movdqa 0x50(%rdi),%xmm2 - 42e9cd: 66 0f ef 56 50 pxor 0x50(%rsi),%xmm2 - 42e9d2: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e9d7: 0f 83 a2 04 00 00 jae 42ee7f <__memcmp_sse4_1+0xb7f> - 42e9dd: 66 0f 6f 57 60 movdqa 0x60(%rdi),%xmm2 - 42e9e2: 66 0f ef 56 60 pxor 0x60(%rsi),%xmm2 - 42e9e7: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42e9ec: 0f 83 83 04 00 00 jae 42ee75 <__memcmp_sse4_1+0xb75> - 42e9f2: 66 0f 6f 57 70 movdqa 0x70(%rdi),%xmm2 - 42e9f7: 66 0f ef 56 70 pxor 0x70(%rsi),%xmm2 - 42e9fc: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42ea01: 0f 83 5e 04 00 00 jae 42ee65 <__memcmp_sse4_1+0xb65> - 42ea07: 48 81 c6 80 00 00 00 add $0x80,%rsi - 42ea0e: 48 81 c7 80 00 00 00 add $0x80,%rdi - 42ea15: 48 83 fa 40 cmp $0x40,%rdx - 42ea19: 0f 83 6e fe ff ff jae 42e88d <__memcmp_sse4_1+0x58d> - 42ea1f: 48 83 fa 20 cmp $0x20,%rdx - 42ea23: 72 34 jb 42ea59 <__memcmp_sse4_1+0x759> - 42ea25: f3 0f 6f 17 movdqu (%rdi),%xmm2 - 42ea29: 66 0f ef 16 pxor (%rsi),%xmm2 - 42ea2d: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42ea32: 0f 83 75 04 00 00 jae 42eead <__memcmp_sse4_1+0xbad> - 42ea38: f3 0f 6f 57 10 movdqu 0x10(%rdi),%xmm2 - 42ea3d: 66 0f ef 56 10 pxor 0x10(%rsi),%xmm2 - 42ea42: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42ea47: 0f 83 58 04 00 00 jae 42eea5 <__memcmp_sse4_1+0xba5> - 42ea4d: 48 83 ea 20 sub $0x20,%rdx - 42ea51: 48 83 c7 20 add $0x20,%rdi - 42ea55: 48 83 c6 20 add $0x20,%rsi - 42ea59: 48 01 d6 add %rdx,%rsi - 42ea5c: 48 01 d7 add %rdx,%rdi - 42ea5f: 4c 8d 1d 0a 48 07 00 lea 0x7480a(%rip),%r11 # 4a3270 - 42ea66: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx - 42ea6a: 4c 01 d9 add %r11,%rcx - 42ea6d: ff e1 jmpq *%rcx - 42ea6f: 0f 0b ud2 - 42ea71: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 42ea76: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42ea7d: 00 00 00 - 42ea80: 48 81 ea 00 01 00 00 sub $0x100,%rdx - 42ea87: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 42ea8b: 66 0f ef 16 pxor (%rsi),%xmm2 - 42ea8f: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42ea94: 0f 83 13 04 00 00 jae 42eead <__memcmp_sse4_1+0xbad> - 42ea9a: 66 0f 6f 57 10 movdqa 0x10(%rdi),%xmm2 - 42ea9f: 66 0f ef 56 10 pxor 0x10(%rsi),%xmm2 - 42eaa4: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42eaa9: 0f 83 f6 03 00 00 jae 42eea5 <__memcmp_sse4_1+0xba5> - 42eaaf: 66 0f 6f 57 20 movdqa 0x20(%rdi),%xmm2 - 42eab4: 66 0f ef 56 20 pxor 0x20(%rsi),%xmm2 - 42eab9: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42eabe: 0f 83 d9 03 00 00 jae 42ee9d <__memcmp_sse4_1+0xb9d> - 42eac4: 66 0f 6f 57 30 movdqa 0x30(%rdi),%xmm2 - 42eac9: 66 0f ef 56 30 pxor 0x30(%rsi),%xmm2 - 42eace: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42ead3: 0f 83 ba 03 00 00 jae 42ee93 <__memcmp_sse4_1+0xb93> - 42ead9: 66 0f 6f 57 40 movdqa 0x40(%rdi),%xmm2 - 42eade: 66 0f ef 56 40 pxor 0x40(%rsi),%xmm2 - 42eae3: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42eae8: 0f 83 9b 03 00 00 jae 42ee89 <__memcmp_sse4_1+0xb89> - 42eaee: 66 0f 6f 57 50 movdqa 0x50(%rdi),%xmm2 - 42eaf3: 66 0f ef 56 50 pxor 0x50(%rsi),%xmm2 - 42eaf8: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42eafd: 0f 83 7c 03 00 00 jae 42ee7f <__memcmp_sse4_1+0xb7f> - 42eb03: 66 0f 6f 57 60 movdqa 0x60(%rdi),%xmm2 - 42eb08: 66 0f ef 56 60 pxor 0x60(%rsi),%xmm2 - 42eb0d: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42eb12: 0f 83 5d 03 00 00 jae 42ee75 <__memcmp_sse4_1+0xb75> - 42eb18: 66 0f 6f 57 70 movdqa 0x70(%rdi),%xmm2 - 42eb1d: 66 0f ef 56 70 pxor 0x70(%rsi),%xmm2 - 42eb22: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42eb27: 0f 83 38 03 00 00 jae 42ee65 <__memcmp_sse4_1+0xb65> - 42eb2d: 66 0f 6f 97 80 00 00 movdqa 0x80(%rdi),%xmm2 - 42eb34: 00 - 42eb35: 66 0f ef 96 80 00 00 pxor 0x80(%rsi),%xmm2 - 42eb3c: 00 - 42eb3d: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42eb42: 0f 83 0d 03 00 00 jae 42ee55 <__memcmp_sse4_1+0xb55> - 42eb48: 66 0f 6f 97 90 00 00 movdqa 0x90(%rdi),%xmm2 - 42eb4f: 00 - 42eb50: 66 0f ef 96 90 00 00 pxor 0x90(%rsi),%xmm2 - 42eb57: 00 - 42eb58: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42eb5d: 0f 83 e2 02 00 00 jae 42ee45 <__memcmp_sse4_1+0xb45> - 42eb63: 66 0f 6f 97 a0 00 00 movdqa 0xa0(%rdi),%xmm2 - 42eb6a: 00 - 42eb6b: 66 0f ef 96 a0 00 00 pxor 0xa0(%rsi),%xmm2 - 42eb72: 00 - 42eb73: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42eb78: 0f 83 b7 02 00 00 jae 42ee35 <__memcmp_sse4_1+0xb35> - 42eb7e: 66 0f 6f 97 b0 00 00 movdqa 0xb0(%rdi),%xmm2 - 42eb85: 00 - 42eb86: 66 0f ef 96 b0 00 00 pxor 0xb0(%rsi),%xmm2 - 42eb8d: 00 - 42eb8e: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42eb93: 0f 83 89 02 00 00 jae 42ee22 <__memcmp_sse4_1+0xb22> - 42eb99: 66 0f 6f 97 c0 00 00 movdqa 0xc0(%rdi),%xmm2 - 42eba0: 00 - 42eba1: 66 0f ef 96 c0 00 00 pxor 0xc0(%rsi),%xmm2 - 42eba8: 00 - 42eba9: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42ebae: 0f 83 5b 02 00 00 jae 42ee0f <__memcmp_sse4_1+0xb0f> - 42ebb4: 66 0f 6f 97 d0 00 00 movdqa 0xd0(%rdi),%xmm2 - 42ebbb: 00 - 42ebbc: 66 0f ef 96 d0 00 00 pxor 0xd0(%rsi),%xmm2 - 42ebc3: 00 - 42ebc4: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42ebc9: 0f 83 2d 02 00 00 jae 42edfc <__memcmp_sse4_1+0xafc> - 42ebcf: 66 0f 6f 97 e0 00 00 movdqa 0xe0(%rdi),%xmm2 - 42ebd6: 00 - 42ebd7: 66 0f ef 96 e0 00 00 pxor 0xe0(%rsi),%xmm2 - 42ebde: 00 - 42ebdf: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42ebe4: 0f 83 ff 01 00 00 jae 42ede9 <__memcmp_sse4_1+0xae9> - 42ebea: 66 0f 6f 97 f0 00 00 movdqa 0xf0(%rdi),%xmm2 - 42ebf1: 00 - 42ebf2: 66 0f ef 96 f0 00 00 pxor 0xf0(%rsi),%xmm2 - 42ebf9: 00 - 42ebfa: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42ebff: 0f 83 d1 01 00 00 jae 42edd6 <__memcmp_sse4_1+0xad6> - 42ec05: 48 81 c6 00 01 00 00 add $0x100,%rsi - 42ec0c: 48 81 c7 00 01 00 00 add $0x100,%rdi - 42ec13: 48 81 fa 80 00 00 00 cmp $0x80,%rdx - 42ec1a: 0f 83 3a fd ff ff jae 42e95a <__memcmp_sse4_1+0x65a> - 42ec20: 48 83 fa 40 cmp $0x40,%rdx - 42ec24: 0f 83 63 fc ff ff jae 42e88d <__memcmp_sse4_1+0x58d> - 42ec2a: 48 83 fa 20 cmp $0x20,%rdx - 42ec2e: 72 34 jb 42ec64 <__memcmp_sse4_1+0x964> - 42ec30: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 42ec34: 66 0f ef 16 pxor (%rsi),%xmm2 - 42ec38: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42ec3d: 0f 83 6a 02 00 00 jae 42eead <__memcmp_sse4_1+0xbad> - 42ec43: 66 0f 6f 57 10 movdqa 0x10(%rdi),%xmm2 - 42ec48: 66 0f ef 56 10 pxor 0x10(%rsi),%xmm2 - 42ec4d: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42ec52: 0f 83 4d 02 00 00 jae 42eea5 <__memcmp_sse4_1+0xba5> - 42ec58: 48 83 ea 20 sub $0x20,%rdx - 42ec5c: 48 83 c7 20 add $0x20,%rdi - 42ec60: 48 83 c6 20 add $0x20,%rsi - 42ec64: 48 01 d6 add %rdx,%rsi - 42ec67: 48 01 d7 add %rdx,%rdi - 42ec6a: 4c 8d 1d ff 45 07 00 lea 0x745ff(%rip),%r11 # 4a3270 - 42ec71: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx - 42ec75: 4c 01 d9 add %r11,%rcx - 42ec78: ff e1 jmpq *%rcx - 42ec7a: 0f 0b ud2 - 42ec7c: 0f 1f 40 00 nopl 0x0(%rax) - 42ec80: 4c 8b 05 49 c4 29 00 mov 0x29c449(%rip),%r8 # 6cb0d0 <__x86_data_cache_size_half> - 42ec87: 4d 89 c1 mov %r8,%r9 - 42ec8a: 49 d1 e8 shr %r8 - 42ec8d: 4d 01 c8 add %r9,%r8 - 42ec90: 4c 39 c2 cmp %r8,%rdx - 42ec93: 77 76 ja 42ed0b <__memcmp_sse4_1+0xa0b> - 42ec95: 48 83 ea 40 sub $0x40,%rdx - 42ec99: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 42eca0: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 42eca4: 66 0f ef 16 pxor (%rsi),%xmm2 - 42eca8: 66 0f 6f ca movdqa %xmm2,%xmm1 - 42ecac: 66 0f 6f 5f 10 movdqa 0x10(%rdi),%xmm3 - 42ecb1: 66 0f ef 5e 10 pxor 0x10(%rsi),%xmm3 - 42ecb6: 66 0f eb cb por %xmm3,%xmm1 - 42ecba: 66 0f 6f 67 20 movdqa 0x20(%rdi),%xmm4 - 42ecbf: 66 0f ef 66 20 pxor 0x20(%rsi),%xmm4 - 42ecc4: 66 0f eb cc por %xmm4,%xmm1 - 42ecc8: 66 0f 6f 6f 30 movdqa 0x30(%rdi),%xmm5 - 42eccd: 66 0f ef 6e 30 pxor 0x30(%rsi),%xmm5 - 42ecd2: 66 0f eb cd por %xmm5,%xmm1 - 42ecd6: 66 0f 38 17 c1 ptest %xmm1,%xmm0 - 42ecdb: 0f 83 af 00 00 00 jae 42ed90 <__memcmp_sse4_1+0xa90> - 42ece1: 48 83 c6 40 add $0x40,%rsi - 42ece5: 48 83 c7 40 add $0x40,%rdi - 42ece9: 48 83 ea 40 sub $0x40,%rdx - 42eced: 73 b1 jae 42eca0 <__memcmp_sse4_1+0x9a0> - 42ecef: 48 83 c2 40 add $0x40,%rdx - 42ecf3: 48 01 d6 add %rdx,%rsi - 42ecf6: 48 01 d7 add %rdx,%rdi - 42ecf9: 4c 8d 1d 70 45 07 00 lea 0x74570(%rip),%r11 # 4a3270 - 42ed00: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx - 42ed04: 4c 01 d9 add %r11,%rcx - 42ed07: ff e1 jmpq *%rcx - 42ed09: 0f 0b ud2 - 42ed0b: 48 83 ea 40 sub $0x40,%rdx - 42ed0f: 90 nop - 42ed10: 0f 18 87 c0 01 00 00 prefetchnta 0x1c0(%rdi) - 42ed17: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) - 42ed1e: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 42ed22: 66 0f ef 16 pxor (%rsi),%xmm2 - 42ed26: 66 0f 6f ca movdqa %xmm2,%xmm1 - 42ed2a: 66 0f 6f 5f 10 movdqa 0x10(%rdi),%xmm3 - 42ed2f: 66 0f ef 5e 10 pxor 0x10(%rsi),%xmm3 - 42ed34: 66 0f eb cb por %xmm3,%xmm1 - 42ed38: 66 0f 6f 67 20 movdqa 0x20(%rdi),%xmm4 - 42ed3d: 66 0f ef 66 20 pxor 0x20(%rsi),%xmm4 - 42ed42: 66 0f eb cc por %xmm4,%xmm1 - 42ed46: 66 0f 6f 6f 30 movdqa 0x30(%rdi),%xmm5 - 42ed4b: 66 0f ef 6e 30 pxor 0x30(%rsi),%xmm5 - 42ed50: 66 0f eb cd por %xmm5,%xmm1 - 42ed54: 66 0f 38 17 c1 ptest %xmm1,%xmm0 - 42ed59: 73 35 jae 42ed90 <__memcmp_sse4_1+0xa90> - 42ed5b: 48 83 c6 40 add $0x40,%rsi - 42ed5f: 48 83 c7 40 add $0x40,%rdi - 42ed63: 48 83 ea 40 sub $0x40,%rdx - 42ed67: 73 a7 jae 42ed10 <__memcmp_sse4_1+0xa10> - 42ed69: 48 83 c2 40 add $0x40,%rdx - 42ed6d: 48 01 d6 add %rdx,%rsi - 42ed70: 48 01 d7 add %rdx,%rdi - 42ed73: 4c 8d 1d f6 44 07 00 lea 0x744f6(%rip),%r11 # 4a3270 - 42ed7a: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx - 42ed7e: 4c 01 d9 add %r11,%rcx - 42ed81: ff e1 jmpq *%rcx - 42ed83: 0f 0b ud2 - 42ed85: 90 nop - 42ed86: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42ed8d: 00 00 00 - 42ed90: 48 83 c7 10 add $0x10,%rdi - 42ed94: 48 83 c6 10 add $0x10,%rsi - 42ed98: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42ed9d: 0f 83 12 01 00 00 jae 42eeb5 <__memcmp_sse4_1+0xbb5> - 42eda3: 48 83 c7 10 add $0x10,%rdi - 42eda7: 48 83 c6 10 add $0x10,%rsi - 42edab: 66 0f 38 17 c3 ptest %xmm3,%xmm0 - 42edb0: 0f 83 ff 00 00 00 jae 42eeb5 <__memcmp_sse4_1+0xbb5> - 42edb6: 48 83 c7 10 add $0x10,%rdi - 42edba: 48 83 c6 10 add $0x10,%rsi - 42edbe: 66 0f 38 17 c4 ptest %xmm4,%xmm0 - 42edc3: 0f 83 ec 00 00 00 jae 42eeb5 <__memcmp_sse4_1+0xbb5> - 42edc9: 48 83 c7 10 add $0x10,%rdi - 42edcd: 48 83 c6 10 add $0x10,%rsi - 42edd1: e9 df 00 00 00 jmpq 42eeb5 <__memcmp_sse4_1+0xbb5> - 42edd6: 48 81 c7 00 01 00 00 add $0x100,%rdi - 42eddd: 48 81 c6 00 01 00 00 add $0x100,%rsi - 42ede4: e9 cc 00 00 00 jmpq 42eeb5 <__memcmp_sse4_1+0xbb5> - 42ede9: 48 81 c7 f0 00 00 00 add $0xf0,%rdi - 42edf0: 48 81 c6 f0 00 00 00 add $0xf0,%rsi - 42edf7: e9 b9 00 00 00 jmpq 42eeb5 <__memcmp_sse4_1+0xbb5> - 42edfc: 48 81 c7 e0 00 00 00 add $0xe0,%rdi - 42ee03: 48 81 c6 e0 00 00 00 add $0xe0,%rsi - 42ee0a: e9 a6 00 00 00 jmpq 42eeb5 <__memcmp_sse4_1+0xbb5> - 42ee0f: 48 81 c7 d0 00 00 00 add $0xd0,%rdi - 42ee16: 48 81 c6 d0 00 00 00 add $0xd0,%rsi - 42ee1d: e9 93 00 00 00 jmpq 42eeb5 <__memcmp_sse4_1+0xbb5> - 42ee22: 48 81 c7 c0 00 00 00 add $0xc0,%rdi - 42ee29: 48 81 c6 c0 00 00 00 add $0xc0,%rsi - 42ee30: e9 80 00 00 00 jmpq 42eeb5 <__memcmp_sse4_1+0xbb5> - 42ee35: 48 81 c7 b0 00 00 00 add $0xb0,%rdi - 42ee3c: 48 81 c6 b0 00 00 00 add $0xb0,%rsi - 42ee43: eb 70 jmp 42eeb5 <__memcmp_sse4_1+0xbb5> - 42ee45: 48 81 c7 a0 00 00 00 add $0xa0,%rdi - 42ee4c: 48 81 c6 a0 00 00 00 add $0xa0,%rsi - 42ee53: eb 60 jmp 42eeb5 <__memcmp_sse4_1+0xbb5> - 42ee55: 48 81 c7 90 00 00 00 add $0x90,%rdi - 42ee5c: 48 81 c6 90 00 00 00 add $0x90,%rsi - 42ee63: eb 50 jmp 42eeb5 <__memcmp_sse4_1+0xbb5> - 42ee65: 48 81 c7 80 00 00 00 add $0x80,%rdi - 42ee6c: 48 81 c6 80 00 00 00 add $0x80,%rsi - 42ee73: eb 40 jmp 42eeb5 <__memcmp_sse4_1+0xbb5> - 42ee75: 48 83 c7 70 add $0x70,%rdi - 42ee79: 48 83 c6 70 add $0x70,%rsi - 42ee7d: eb 36 jmp 42eeb5 <__memcmp_sse4_1+0xbb5> - 42ee7f: 48 83 c7 60 add $0x60,%rdi - 42ee83: 48 83 c6 60 add $0x60,%rsi - 42ee87: eb 2c jmp 42eeb5 <__memcmp_sse4_1+0xbb5> - 42ee89: 48 83 c7 50 add $0x50,%rdi - 42ee8d: 48 83 c6 50 add $0x50,%rsi - 42ee91: eb 22 jmp 42eeb5 <__memcmp_sse4_1+0xbb5> - 42ee93: 48 83 c7 40 add $0x40,%rdi - 42ee97: 48 83 c6 40 add $0x40,%rsi - 42ee9b: eb 18 jmp 42eeb5 <__memcmp_sse4_1+0xbb5> - 42ee9d: 48 83 c7 10 add $0x10,%rdi - 42eea1: 48 83 c6 10 add $0x10,%rsi - 42eea5: 48 83 c7 10 add $0x10,%rdi - 42eea9: 48 83 c6 10 add $0x10,%rsi - 42eead: 48 83 c7 10 add $0x10,%rdi - 42eeb1: 48 83 c6 10 add $0x10,%rsi - 42eeb5: 48 8b 47 f0 mov -0x10(%rdi),%rax - 42eeb9: 48 8b 4e f0 mov -0x10(%rsi),%rcx - 42eebd: 48 39 c1 cmp %rax,%rcx - 42eec0: 0f 85 3d 0a 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> - 42eec6: 48 8b 47 f8 mov -0x8(%rdi),%rax - 42eeca: 48 8b 4e f8 mov -0x8(%rsi),%rcx - 42eece: 48 39 c1 cmp %rax,%rcx - 42eed1: 0f 85 2c 0a 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> - 42eed7: 31 c0 xor %eax,%eax - 42eed9: c3 retq - 42eeda: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 42eee0: 48 8b 47 f4 mov -0xc(%rdi),%rax - 42eee4: 48 8b 4e f4 mov -0xc(%rsi),%rcx - 42eee8: 48 39 c1 cmp %rax,%rcx - 42eeeb: 0f 85 12 0a 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> - 42eef1: 8b 4e fc mov -0x4(%rsi),%ecx - 42eef4: 8b 47 fc mov -0x4(%rdi),%eax - 42eef7: 39 c1 cmp %eax,%ecx - 42eef9: 0f 85 10 0a 00 00 jne 42f90f <__memcmp_sse4_1+0x160f> - 42eeff: 31 c0 xor %eax,%eax - 42ef01: c3 retq - 42ef02: 0f 1f 40 00 nopl 0x0(%rax) - 42ef06: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42ef0d: 00 00 00 - 42ef10: f3 0f 6f 4f bf movdqu -0x41(%rdi),%xmm1 - 42ef15: f3 0f 6f 56 bf movdqu -0x41(%rsi),%xmm2 - 42ef1a: b2 bf mov $0xbf,%dl - 42ef1c: 66 0f ef d1 pxor %xmm1,%xmm2 - 42ef20: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42ef25: 0f 83 bd 09 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42ef2b: f3 0f 6f 4f cf movdqu -0x31(%rdi),%xmm1 - 42ef30: f3 0f 6f 56 cf movdqu -0x31(%rsi),%xmm2 - 42ef35: b2 cf mov $0xcf,%dl - 42ef37: 66 0f ef d1 pxor %xmm1,%xmm2 - 42ef3b: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42ef40: 0f 83 a2 09 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42ef46: f3 0f 6f 4f df movdqu -0x21(%rdi),%xmm1 - 42ef4b: f3 0f 6f 56 df movdqu -0x21(%rsi),%xmm2 - 42ef50: b2 df mov $0xdf,%dl - 42ef52: 66 0f ef d1 pxor %xmm1,%xmm2 - 42ef56: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42ef5b: 0f 83 87 09 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42ef61: 48 8b 47 ef mov -0x11(%rdi),%rax - 42ef65: 48 8b 4e ef mov -0x11(%rsi),%rcx - 42ef69: 48 39 c1 cmp %rax,%rcx - 42ef6c: 0f 85 91 09 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> - 42ef72: 48 8b 47 f7 mov -0x9(%rdi),%rax - 42ef76: 48 8b 4e f7 mov -0x9(%rsi),%rcx - 42ef7a: 48 39 c1 cmp %rax,%rcx - 42ef7d: 0f 85 80 09 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> - 42ef83: 0f b6 47 ff movzbl -0x1(%rdi),%eax - 42ef87: 0f b6 56 ff movzbl -0x1(%rsi),%edx - 42ef8b: 29 d0 sub %edx,%eax - 42ef8d: c3 retq - 42ef8e: 66 90 xchg %ax,%ax - 42ef90: 48 8b 47 f3 mov -0xd(%rdi),%rax - 42ef94: 48 8b 4e f3 mov -0xd(%rsi),%rcx - 42ef98: 48 39 c1 cmp %rax,%rcx - 42ef9b: 0f 85 62 09 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> - 42efa1: 48 8b 47 f8 mov -0x8(%rdi),%rax - 42efa5: 48 8b 4e f8 mov -0x8(%rsi),%rcx - 42efa9: 48 39 c1 cmp %rax,%rcx - 42efac: 0f 85 51 09 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> - 42efb2: 31 c0 xor %eax,%eax - 42efb4: c3 retq - 42efb5: 90 nop - 42efb6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42efbd: 00 00 00 - 42efc0: 8b 47 fb mov -0x5(%rdi),%eax - 42efc3: 8b 4e fb mov -0x5(%rsi),%ecx - 42efc6: 39 c1 cmp %eax,%ecx - 42efc8: 0f 85 41 09 00 00 jne 42f90f <__memcmp_sse4_1+0x160f> - 42efce: 0f b6 47 ff movzbl -0x1(%rdi),%eax - 42efd2: 0f b6 56 ff movzbl -0x1(%rsi),%edx - 42efd6: 29 d0 sub %edx,%eax - 42efd8: c3 retq - 42efd9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 42efe0: f3 0f 6f 4f be movdqu -0x42(%rdi),%xmm1 - 42efe5: f3 0f 6f 56 be movdqu -0x42(%rsi),%xmm2 - 42efea: b2 be mov $0xbe,%dl - 42efec: 66 0f ef d1 pxor %xmm1,%xmm2 - 42eff0: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42eff5: 0f 83 ed 08 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42effb: f3 0f 6f 4f ce movdqu -0x32(%rdi),%xmm1 - 42f000: f3 0f 6f 56 ce movdqu -0x32(%rsi),%xmm2 - 42f005: b2 ce mov $0xce,%dl - 42f007: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f00b: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f010: 0f 83 d2 08 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f016: f3 0f 6f 4f de movdqu -0x22(%rdi),%xmm1 - 42f01b: f3 0f 6f 56 de movdqu -0x22(%rsi),%xmm2 - 42f020: b2 de mov $0xde,%dl - 42f022: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f026: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f02b: 0f 83 b7 08 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f031: 48 8b 47 ee mov -0x12(%rdi),%rax - 42f035: 48 8b 4e ee mov -0x12(%rsi),%rcx - 42f039: 48 39 c1 cmp %rax,%rcx - 42f03c: 0f 85 c1 08 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> - 42f042: 48 8b 47 f6 mov -0xa(%rdi),%rax - 42f046: 48 8b 4e f6 mov -0xa(%rsi),%rcx - 42f04a: 48 39 c1 cmp %rax,%rcx - 42f04d: 0f 85 b0 08 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> - 42f053: 0f b7 47 fe movzwl -0x2(%rdi),%eax - 42f057: 0f b7 4e fe movzwl -0x2(%rsi),%ecx - 42f05b: 38 c8 cmp %cl,%al - 42f05d: 0f 85 cd 08 00 00 jne 42f930 <__memcmp_sse4_1+0x1630> - 42f063: 25 ff ff 00 00 and $0xffff,%eax - 42f068: 81 e1 ff ff 00 00 and $0xffff,%ecx - 42f06e: 29 c8 sub %ecx,%eax - 42f070: c3 retq - 42f071: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 42f076: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42f07d: 00 00 00 - 42f080: 48 8b 47 f2 mov -0xe(%rdi),%rax - 42f084: 48 8b 4e f2 mov -0xe(%rsi),%rcx - 42f088: 48 39 c1 cmp %rax,%rcx - 42f08b: 0f 85 72 08 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> - 42f091: 48 8b 47 f8 mov -0x8(%rdi),%rax - 42f095: 48 8b 4e f8 mov -0x8(%rsi),%rcx - 42f099: 48 39 c1 cmp %rax,%rcx - 42f09c: 0f 85 61 08 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> - 42f0a2: 31 c0 xor %eax,%eax - 42f0a4: c3 retq - 42f0a5: 90 nop - 42f0a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42f0ad: 00 00 00 - 42f0b0: 8b 47 fa mov -0x6(%rdi),%eax - 42f0b3: 8b 4e fa mov -0x6(%rsi),%ecx - 42f0b6: 39 c1 cmp %eax,%ecx - 42f0b8: 0f 85 51 08 00 00 jne 42f90f <__memcmp_sse4_1+0x160f> - 42f0be: 0f b7 4e fe movzwl -0x2(%rsi),%ecx - 42f0c2: 0f b7 47 fe movzwl -0x2(%rdi),%eax - 42f0c6: 38 c8 cmp %cl,%al - 42f0c8: 0f 85 62 08 00 00 jne 42f930 <__memcmp_sse4_1+0x1630> - 42f0ce: 25 ff ff 00 00 and $0xffff,%eax - 42f0d3: 81 e1 ff ff 00 00 and $0xffff,%ecx - 42f0d9: 29 c8 sub %ecx,%eax - 42f0db: c3 retq - 42f0dc: 0f 1f 40 00 nopl 0x0(%rax) - 42f0e0: f3 0f 6f 57 bd movdqu -0x43(%rdi),%xmm2 - 42f0e5: f3 0f 6f 4e bd movdqu -0x43(%rsi),%xmm1 - 42f0ea: b2 bd mov $0xbd,%dl - 42f0ec: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f0f0: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f0f5: 0f 83 ed 07 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f0fb: f3 0f 6f 57 cd movdqu -0x33(%rdi),%xmm2 - 42f100: f3 0f 6f 4e cd movdqu -0x33(%rsi),%xmm1 - 42f105: b2 cd mov $0xcd,%dl - 42f107: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f10b: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f110: 0f 83 d2 07 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f116: f3 0f 6f 4e dd movdqu -0x23(%rsi),%xmm1 - 42f11b: f3 0f 6f 57 dd movdqu -0x23(%rdi),%xmm2 - 42f120: b2 dd mov $0xdd,%dl - 42f122: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f126: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f12b: 0f 83 b7 07 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f131: 48 8b 47 ed mov -0x13(%rdi),%rax - 42f135: 48 8b 4e ed mov -0x13(%rsi),%rcx - 42f139: 48 39 c1 cmp %rax,%rcx - 42f13c: 0f 85 c1 07 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> - 42f142: 48 8b 47 f5 mov -0xb(%rdi),%rax - 42f146: 48 8b 4e f5 mov -0xb(%rsi),%rcx - 42f14a: 48 39 c1 cmp %rax,%rcx - 42f14d: 0f 85 b0 07 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> - 42f153: 8b 47 fc mov -0x4(%rdi),%eax - 42f156: 8b 4e fc mov -0x4(%rsi),%ecx - 42f159: 39 c1 cmp %eax,%ecx - 42f15b: 0f 85 ae 07 00 00 jne 42f90f <__memcmp_sse4_1+0x160f> - 42f161: 31 c0 xor %eax,%eax - 42f163: c3 retq - 42f164: 66 90 xchg %ax,%ax - 42f166: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42f16d: 00 00 00 - 42f170: 48 8b 47 f1 mov -0xf(%rdi),%rax - 42f174: 48 8b 4e f1 mov -0xf(%rsi),%rcx - 42f178: 48 39 c1 cmp %rax,%rcx - 42f17b: 0f 85 82 07 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> - 42f181: 48 8b 47 f8 mov -0x8(%rdi),%rax - 42f185: 48 8b 4e f8 mov -0x8(%rsi),%rcx - 42f189: 48 39 c1 cmp %rax,%rcx - 42f18c: 0f 85 71 07 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> - 42f192: 31 c0 xor %eax,%eax - 42f194: c3 retq - 42f195: 90 nop - 42f196: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42f19d: 00 00 00 - 42f1a0: 8b 47 f9 mov -0x7(%rdi),%eax - 42f1a3: 8b 4e f9 mov -0x7(%rsi),%ecx - 42f1a6: 39 c1 cmp %eax,%ecx - 42f1a8: 0f 85 61 07 00 00 jne 42f90f <__memcmp_sse4_1+0x160f> - 42f1ae: 8b 47 fc mov -0x4(%rdi),%eax - 42f1b1: 8b 4e fc mov -0x4(%rsi),%ecx - 42f1b4: 39 c1 cmp %eax,%ecx - 42f1b6: 0f 85 53 07 00 00 jne 42f90f <__memcmp_sse4_1+0x160f> - 42f1bc: 31 c0 xor %eax,%eax - 42f1be: c3 retq - 42f1bf: 90 nop - 42f1c0: 0f b7 47 fd movzwl -0x3(%rdi),%eax - 42f1c4: 0f b7 4e fd movzwl -0x3(%rsi),%ecx - 42f1c8: 39 c1 cmp %eax,%ecx - 42f1ca: 0f 85 4a 07 00 00 jne 42f91a <__memcmp_sse4_1+0x161a> - 42f1d0: 0f b6 47 ff movzbl -0x1(%rdi),%eax - 42f1d4: 0f b6 4e ff movzbl -0x1(%rsi),%ecx - 42f1d8: 29 c8 sub %ecx,%eax - 42f1da: c3 retq - 42f1db: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 42f1e0: f3 0f 6f 57 bc movdqu -0x44(%rdi),%xmm2 - 42f1e5: f3 0f 6f 4e bc movdqu -0x44(%rsi),%xmm1 - 42f1ea: b2 bc mov $0xbc,%dl - 42f1ec: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f1f0: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f1f5: 0f 83 ed 06 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f1fb: f3 0f 6f 57 cc movdqu -0x34(%rdi),%xmm2 - 42f200: f3 0f 6f 4e cc movdqu -0x34(%rsi),%xmm1 - 42f205: b2 cc mov $0xcc,%dl - 42f207: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f20b: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f210: 0f 83 d2 06 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f216: f3 0f 6f 57 dc movdqu -0x24(%rdi),%xmm2 - 42f21b: f3 0f 6f 4e dc movdqu -0x24(%rsi),%xmm1 - 42f220: b2 dc mov $0xdc,%dl - 42f222: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f226: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f22b: 0f 83 b7 06 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f231: f3 0f 6f 57 ec movdqu -0x14(%rdi),%xmm2 - 42f236: f3 0f 6f 4e ec movdqu -0x14(%rsi),%xmm1 - 42f23b: b2 ec mov $0xec,%dl - 42f23d: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f241: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f246: 0f 83 9c 06 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f24c: 8b 4e fc mov -0x4(%rsi),%ecx - 42f24f: 8b 47 fc mov -0x4(%rdi),%eax - 42f252: 39 c1 cmp %eax,%ecx - 42f254: 0f 85 b5 06 00 00 jne 42f90f <__memcmp_sse4_1+0x160f> - 42f25a: 31 c0 xor %eax,%eax - 42f25c: c3 retq - 42f25d: 0f 1f 00 nopl (%rax) - 42f260: f3 0f 6f 4e bb movdqu -0x45(%rsi),%xmm1 - 42f265: f3 0f 6f 57 bb movdqu -0x45(%rdi),%xmm2 - 42f26a: b2 bb mov $0xbb,%dl - 42f26c: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f270: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f275: 0f 83 6d 06 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f27b: f3 0f 6f 4e cb movdqu -0x35(%rsi),%xmm1 - 42f280: f3 0f 6f 57 cb movdqu -0x35(%rdi),%xmm2 - 42f285: b2 cb mov $0xcb,%dl - 42f287: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f28b: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f290: 0f 83 52 06 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f296: f3 0f 6f 4e db movdqu -0x25(%rsi),%xmm1 - 42f29b: f3 0f 6f 57 db movdqu -0x25(%rdi),%xmm2 - 42f2a0: b2 db mov $0xdb,%dl - 42f2a2: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f2a6: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f2ab: 0f 83 37 06 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f2b1: f3 0f 6f 4e eb movdqu -0x15(%rsi),%xmm1 - 42f2b6: f3 0f 6f 57 eb movdqu -0x15(%rdi),%xmm2 - 42f2bb: b2 eb mov $0xeb,%dl - 42f2bd: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f2c1: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f2c6: 0f 83 1c 06 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f2cc: 48 8b 47 f8 mov -0x8(%rdi),%rax - 42f2d0: 48 8b 4e f8 mov -0x8(%rsi),%rcx - 42f2d4: 48 39 c1 cmp %rax,%rcx - 42f2d7: 0f 85 26 06 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> - 42f2dd: 31 c0 xor %eax,%eax - 42f2df: c3 retq - 42f2e0: f3 0f 6f 4e ba movdqu -0x46(%rsi),%xmm1 - 42f2e5: f3 0f 6f 57 ba movdqu -0x46(%rdi),%xmm2 - 42f2ea: b2 ba mov $0xba,%dl - 42f2ec: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f2f0: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f2f5: 0f 83 ed 05 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f2fb: f3 0f 6f 4e ca movdqu -0x36(%rsi),%xmm1 - 42f300: f3 0f 6f 57 ca movdqu -0x36(%rdi),%xmm2 - 42f305: b2 ca mov $0xca,%dl - 42f307: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f30b: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f310: 0f 83 d2 05 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f316: f3 0f 6f 4e da movdqu -0x26(%rsi),%xmm1 - 42f31b: f3 0f 6f 57 da movdqu -0x26(%rdi),%xmm2 - 42f320: b2 da mov $0xda,%dl - 42f322: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f326: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f32b: 0f 83 b7 05 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f331: f3 0f 6f 4e ea movdqu -0x16(%rsi),%xmm1 - 42f336: f3 0f 6f 57 ea movdqu -0x16(%rdi),%xmm2 - 42f33b: b2 ea mov $0xea,%dl - 42f33d: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f341: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f346: 0f 83 9c 05 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f34c: 48 8b 47 f8 mov -0x8(%rdi),%rax - 42f350: 48 8b 4e f8 mov -0x8(%rsi),%rcx - 42f354: 48 39 c1 cmp %rax,%rcx - 42f357: 0f 85 a6 05 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> - 42f35d: 31 c0 xor %eax,%eax - 42f35f: c3 retq - 42f360: f3 0f 6f 4e b9 movdqu -0x47(%rsi),%xmm1 - 42f365: f3 0f 6f 57 b9 movdqu -0x47(%rdi),%xmm2 - 42f36a: b2 b9 mov $0xb9,%dl - 42f36c: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f370: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f375: 0f 83 6d 05 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f37b: f3 0f 6f 57 c9 movdqu -0x37(%rdi),%xmm2 - 42f380: f3 0f 6f 4e c9 movdqu -0x37(%rsi),%xmm1 - 42f385: b2 c9 mov $0xc9,%dl - 42f387: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f38b: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f390: 0f 83 52 05 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f396: f3 0f 6f 57 d9 movdqu -0x27(%rdi),%xmm2 - 42f39b: f3 0f 6f 4e d9 movdqu -0x27(%rsi),%xmm1 - 42f3a0: b2 d9 mov $0xd9,%dl - 42f3a2: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f3a6: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f3ab: 0f 83 37 05 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f3b1: f3 0f 6f 57 e9 movdqu -0x17(%rdi),%xmm2 - 42f3b6: f3 0f 6f 4e e9 movdqu -0x17(%rsi),%xmm1 - 42f3bb: b2 e9 mov $0xe9,%dl - 42f3bd: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f3c1: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f3c6: 0f 83 1c 05 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f3cc: 48 8b 47 f8 mov -0x8(%rdi),%rax - 42f3d0: 48 8b 4e f8 mov -0x8(%rsi),%rcx - 42f3d4: 48 39 c1 cmp %rax,%rcx - 42f3d7: 0f 85 26 05 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> - 42f3dd: 31 c0 xor %eax,%eax - 42f3df: c3 retq - 42f3e0: f3 0f 6f 4e b8 movdqu -0x48(%rsi),%xmm1 - 42f3e5: f3 0f 6f 57 b8 movdqu -0x48(%rdi),%xmm2 - 42f3ea: b2 b8 mov $0xb8,%dl - 42f3ec: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f3f0: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f3f5: 0f 83 ed 04 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f3fb: f3 0f 6f 57 c8 movdqu -0x38(%rdi),%xmm2 - 42f400: f3 0f 6f 4e c8 movdqu -0x38(%rsi),%xmm1 - 42f405: b2 c8 mov $0xc8,%dl - 42f407: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f40b: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f410: 0f 83 d2 04 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f416: f3 0f 6f 57 d8 movdqu -0x28(%rdi),%xmm2 - 42f41b: f3 0f 6f 4e d8 movdqu -0x28(%rsi),%xmm1 - 42f420: b2 d8 mov $0xd8,%dl - 42f422: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f426: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f42b: 0f 83 b7 04 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f431: f3 0f 6f 57 e8 movdqu -0x18(%rdi),%xmm2 - 42f436: f3 0f 6f 4e e8 movdqu -0x18(%rsi),%xmm1 - 42f43b: b2 e8 mov $0xe8,%dl - 42f43d: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f441: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f446: 0f 83 9c 04 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f44c: 48 8b 4e f8 mov -0x8(%rsi),%rcx - 42f450: 48 8b 47 f8 mov -0x8(%rdi),%rax - 42f454: 48 39 c1 cmp %rax,%rcx - 42f457: 0f 85 a6 04 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> - 42f45d: 31 c0 xor %eax,%eax - 42f45f: c3 retq - 42f460: f3 0f 6f 4e b7 movdqu -0x49(%rsi),%xmm1 - 42f465: f3 0f 6f 57 b7 movdqu -0x49(%rdi),%xmm2 - 42f46a: b2 b7 mov $0xb7,%dl - 42f46c: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f470: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f475: 0f 83 6d 04 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f47b: f3 0f 6f 57 c7 movdqu -0x39(%rdi),%xmm2 - 42f480: f3 0f 6f 4e c7 movdqu -0x39(%rsi),%xmm1 - 42f485: b2 c7 mov $0xc7,%dl - 42f487: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f48b: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f490: 0f 83 52 04 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f496: f3 0f 6f 57 d7 movdqu -0x29(%rdi),%xmm2 - 42f49b: f3 0f 6f 4e d7 movdqu -0x29(%rsi),%xmm1 - 42f4a0: b2 d7 mov $0xd7,%dl - 42f4a2: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f4a6: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f4ab: 0f 83 37 04 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f4b1: f3 0f 6f 57 e7 movdqu -0x19(%rdi),%xmm2 - 42f4b6: f3 0f 6f 4e e7 movdqu -0x19(%rsi),%xmm1 - 42f4bb: b2 e7 mov $0xe7,%dl - 42f4bd: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f4c1: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f4c6: 0f 83 1c 04 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f4cc: 48 8b 47 f7 mov -0x9(%rdi),%rax - 42f4d0: 48 8b 4e f7 mov -0x9(%rsi),%rcx - 42f4d4: 48 39 c1 cmp %rax,%rcx - 42f4d7: 0f 85 26 04 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> - 42f4dd: 0f b6 47 ff movzbl -0x1(%rdi),%eax - 42f4e1: 0f b6 4e ff movzbl -0x1(%rsi),%ecx - 42f4e5: 29 c8 sub %ecx,%eax - 42f4e7: c3 retq - 42f4e8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 42f4ef: 00 - 42f4f0: f3 0f 6f 4e b6 movdqu -0x4a(%rsi),%xmm1 - 42f4f5: f3 0f 6f 57 b6 movdqu -0x4a(%rdi),%xmm2 - 42f4fa: b2 b6 mov $0xb6,%dl - 42f4fc: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f500: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f505: 0f 83 dd 03 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f50b: f3 0f 6f 57 c6 movdqu -0x3a(%rdi),%xmm2 - 42f510: f3 0f 6f 4e c6 movdqu -0x3a(%rsi),%xmm1 - 42f515: b2 c6 mov $0xc6,%dl - 42f517: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f51b: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f520: 0f 83 c2 03 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f526: f3 0f 6f 57 d6 movdqu -0x2a(%rdi),%xmm2 - 42f52b: f3 0f 6f 4e d6 movdqu -0x2a(%rsi),%xmm1 - 42f530: b2 d6 mov $0xd6,%dl - 42f532: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f536: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f53b: 0f 83 a7 03 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f541: f3 0f 6f 57 e6 movdqu -0x1a(%rdi),%xmm2 - 42f546: f3 0f 6f 4e e6 movdqu -0x1a(%rsi),%xmm1 - 42f54b: b2 e6 mov $0xe6,%dl - 42f54d: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f551: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f556: 0f 83 8c 03 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f55c: 48 8b 47 f6 mov -0xa(%rdi),%rax - 42f560: 48 8b 4e f6 mov -0xa(%rsi),%rcx - 42f564: 48 39 c1 cmp %rax,%rcx - 42f567: 0f 85 96 03 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> - 42f56d: 0f b7 47 fe movzwl -0x2(%rdi),%eax - 42f571: 0f b7 4e fe movzwl -0x2(%rsi),%ecx - 42f575: e9 a0 03 00 00 jmpq 42f91a <__memcmp_sse4_1+0x161a> - 42f57a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 42f580: f3 0f 6f 4e b5 movdqu -0x4b(%rsi),%xmm1 - 42f585: f3 0f 6f 57 b5 movdqu -0x4b(%rdi),%xmm2 - 42f58a: b2 b5 mov $0xb5,%dl - 42f58c: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f590: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f595: 0f 83 4d 03 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f59b: f3 0f 6f 57 c5 movdqu -0x3b(%rdi),%xmm2 - 42f5a0: f3 0f 6f 4e c5 movdqu -0x3b(%rsi),%xmm1 - 42f5a5: b2 c5 mov $0xc5,%dl - 42f5a7: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f5ab: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f5b0: 0f 83 32 03 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f5b6: f3 0f 6f 57 d5 movdqu -0x2b(%rdi),%xmm2 - 42f5bb: f3 0f 6f 4e d5 movdqu -0x2b(%rsi),%xmm1 - 42f5c0: b2 d5 mov $0xd5,%dl - 42f5c2: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f5c6: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f5cb: 0f 83 17 03 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f5d1: f3 0f 6f 57 e5 movdqu -0x1b(%rdi),%xmm2 - 42f5d6: f3 0f 6f 4e e5 movdqu -0x1b(%rsi),%xmm1 - 42f5db: b2 e5 mov $0xe5,%dl - 42f5dd: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f5e1: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f5e6: 0f 83 fc 02 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f5ec: 48 8b 47 f5 mov -0xb(%rdi),%rax - 42f5f0: 48 8b 4e f5 mov -0xb(%rsi),%rcx - 42f5f4: 48 39 c1 cmp %rax,%rcx - 42f5f7: 0f 85 06 03 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> - 42f5fd: 8b 47 fc mov -0x4(%rdi),%eax - 42f600: 8b 4e fc mov -0x4(%rsi),%ecx - 42f603: 39 c1 cmp %eax,%ecx - 42f605: 0f 85 04 03 00 00 jne 42f90f <__memcmp_sse4_1+0x160f> - 42f60b: 31 c0 xor %eax,%eax - 42f60d: c3 retq - 42f60e: 66 90 xchg %ax,%ax - 42f610: f3 0f 6f 4e b4 movdqu -0x4c(%rsi),%xmm1 - 42f615: f3 0f 6f 57 b4 movdqu -0x4c(%rdi),%xmm2 - 42f61a: b2 b4 mov $0xb4,%dl - 42f61c: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f620: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f625: 0f 83 bd 02 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f62b: f3 0f 6f 57 c4 movdqu -0x3c(%rdi),%xmm2 - 42f630: f3 0f 6f 4e c4 movdqu -0x3c(%rsi),%xmm1 - 42f635: b2 c4 mov $0xc4,%dl - 42f637: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f63b: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f640: 0f 83 a2 02 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f646: f3 0f 6f 57 d4 movdqu -0x2c(%rdi),%xmm2 - 42f64b: f3 0f 6f 4e d4 movdqu -0x2c(%rsi),%xmm1 - 42f650: b2 d4 mov $0xd4,%dl - 42f652: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f656: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f65b: 0f 83 87 02 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f661: f3 0f 6f 57 e4 movdqu -0x1c(%rdi),%xmm2 - 42f666: f3 0f 6f 4e e4 movdqu -0x1c(%rsi),%xmm1 - 42f66b: b2 e4 mov $0xe4,%dl - 42f66d: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f671: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f676: 0f 83 6c 02 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f67c: 48 8b 47 f4 mov -0xc(%rdi),%rax - 42f680: 48 8b 4e f4 mov -0xc(%rsi),%rcx - 42f684: 48 39 c1 cmp %rax,%rcx - 42f687: 0f 85 76 02 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> - 42f68d: 8b 4e fc mov -0x4(%rsi),%ecx - 42f690: 8b 47 fc mov -0x4(%rdi),%eax - 42f693: 39 c1 cmp %eax,%ecx - 42f695: 0f 85 74 02 00 00 jne 42f90f <__memcmp_sse4_1+0x160f> - 42f69b: 31 c0 xor %eax,%eax - 42f69d: c3 retq - 42f69e: 66 90 xchg %ax,%ax - 42f6a0: f3 0f 6f 4e b3 movdqu -0x4d(%rsi),%xmm1 - 42f6a5: f3 0f 6f 57 b3 movdqu -0x4d(%rdi),%xmm2 - 42f6aa: b2 b3 mov $0xb3,%dl - 42f6ac: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f6b0: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f6b5: 0f 83 2d 02 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f6bb: f3 0f 6f 57 c3 movdqu -0x3d(%rdi),%xmm2 - 42f6c0: f3 0f 6f 4e c3 movdqu -0x3d(%rsi),%xmm1 - 42f6c5: b2 c3 mov $0xc3,%dl - 42f6c7: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f6cb: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f6d0: 0f 83 12 02 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f6d6: f3 0f 6f 57 d3 movdqu -0x2d(%rdi),%xmm2 - 42f6db: f3 0f 6f 4e d3 movdqu -0x2d(%rsi),%xmm1 - 42f6e0: b2 d3 mov $0xd3,%dl - 42f6e2: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f6e6: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f6eb: 0f 83 f7 01 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f6f1: f3 0f 6f 57 e3 movdqu -0x1d(%rdi),%xmm2 - 42f6f6: f3 0f 6f 4e e3 movdqu -0x1d(%rsi),%xmm1 - 42f6fb: b2 e3 mov $0xe3,%dl - 42f6fd: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f701: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f706: 0f 83 dc 01 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f70c: 48 8b 47 f3 mov -0xd(%rdi),%rax - 42f710: 48 8b 4e f3 mov -0xd(%rsi),%rcx - 42f714: 48 39 c1 cmp %rax,%rcx - 42f717: 0f 85 e6 01 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> - 42f71d: 48 8b 47 f8 mov -0x8(%rdi),%rax - 42f721: 48 8b 4e f8 mov -0x8(%rsi),%rcx - 42f725: 48 39 c1 cmp %rax,%rcx - 42f728: 0f 85 d5 01 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> - 42f72e: 31 c0 xor %eax,%eax - 42f730: c3 retq - 42f731: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 42f736: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42f73d: 00 00 00 - 42f740: f3 0f 6f 4e b2 movdqu -0x4e(%rsi),%xmm1 - 42f745: f3 0f 6f 57 b2 movdqu -0x4e(%rdi),%xmm2 - 42f74a: b2 b2 mov $0xb2,%dl - 42f74c: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f750: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f755: 0f 83 8d 01 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f75b: f3 0f 6f 57 c2 movdqu -0x3e(%rdi),%xmm2 - 42f760: f3 0f 6f 4e c2 movdqu -0x3e(%rsi),%xmm1 - 42f765: b2 c2 mov $0xc2,%dl - 42f767: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f76b: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f770: 0f 83 72 01 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f776: f3 0f 6f 57 d2 movdqu -0x2e(%rdi),%xmm2 - 42f77b: f3 0f 6f 4e d2 movdqu -0x2e(%rsi),%xmm1 - 42f780: b2 d2 mov $0xd2,%dl - 42f782: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f786: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f78b: 0f 83 57 01 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f791: f3 0f 6f 57 e2 movdqu -0x1e(%rdi),%xmm2 - 42f796: f3 0f 6f 4e e2 movdqu -0x1e(%rsi),%xmm1 - 42f79b: b2 e2 mov $0xe2,%dl - 42f79d: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f7a1: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f7a6: 0f 83 3c 01 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f7ac: 48 8b 47 f2 mov -0xe(%rdi),%rax - 42f7b0: 48 8b 4e f2 mov -0xe(%rsi),%rcx - 42f7b4: 48 39 c1 cmp %rax,%rcx - 42f7b7: 0f 85 46 01 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> - 42f7bd: 48 8b 47 f8 mov -0x8(%rdi),%rax - 42f7c1: 48 8b 4e f8 mov -0x8(%rsi),%rcx - 42f7c5: 48 39 c1 cmp %rax,%rcx - 42f7c8: 0f 85 35 01 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> - 42f7ce: 31 c0 xor %eax,%eax - 42f7d0: c3 retq - 42f7d1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 42f7d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42f7dd: 00 00 00 - 42f7e0: f3 0f 6f 4e b1 movdqu -0x4f(%rsi),%xmm1 - 42f7e5: f3 0f 6f 57 b1 movdqu -0x4f(%rdi),%xmm2 - 42f7ea: b2 b1 mov $0xb1,%dl - 42f7ec: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f7f0: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f7f5: 0f 83 ed 00 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f7fb: f3 0f 6f 57 c1 movdqu -0x3f(%rdi),%xmm2 - 42f800: f3 0f 6f 4e c1 movdqu -0x3f(%rsi),%xmm1 - 42f805: b2 c1 mov $0xc1,%dl - 42f807: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f80b: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f810: 0f 83 d2 00 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f816: f3 0f 6f 57 d1 movdqu -0x2f(%rdi),%xmm2 - 42f81b: f3 0f 6f 4e d1 movdqu -0x2f(%rsi),%xmm1 - 42f820: b2 d1 mov $0xd1,%dl - 42f822: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f826: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f82b: 0f 83 b7 00 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f831: f3 0f 6f 57 e1 movdqu -0x1f(%rdi),%xmm2 - 42f836: f3 0f 6f 4e e1 movdqu -0x1f(%rsi),%xmm1 - 42f83b: b2 e1 mov $0xe1,%dl - 42f83d: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f841: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f846: 0f 83 9c 00 00 00 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f84c: 48 8b 47 f1 mov -0xf(%rdi),%rax - 42f850: 48 8b 4e f1 mov -0xf(%rsi),%rcx - 42f854: 48 39 c1 cmp %rax,%rcx - 42f857: 0f 85 a6 00 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> - 42f85d: 48 8b 47 f8 mov -0x8(%rdi),%rax - 42f861: 48 8b 4e f8 mov -0x8(%rsi),%rcx - 42f865: 48 39 c1 cmp %rax,%rcx - 42f868: 0f 85 95 00 00 00 jne 42f903 <__memcmp_sse4_1+0x1603> - 42f86e: 31 c0 xor %eax,%eax - 42f870: c3 retq - 42f871: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 42f876: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42f87d: 00 00 00 - 42f880: f3 0f 6f 57 c0 movdqu -0x40(%rdi),%xmm2 - 42f885: f3 0f 6f 4e c0 movdqu -0x40(%rsi),%xmm1 - 42f88a: b2 c0 mov $0xc0,%dl - 42f88c: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f890: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f895: 73 51 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f897: f3 0f 6f 57 d0 movdqu -0x30(%rdi),%xmm2 - 42f89c: f3 0f 6f 4e d0 movdqu -0x30(%rsi),%xmm1 - 42f8a1: b2 d0 mov $0xd0,%dl - 42f8a3: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f8a7: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f8ac: 73 3a jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f8ae: f3 0f 6f 57 e0 movdqu -0x20(%rdi),%xmm2 - 42f8b3: f3 0f 6f 4e e0 movdqu -0x20(%rsi),%xmm1 - 42f8b8: b2 e0 mov $0xe0,%dl - 42f8ba: 66 0f ef d1 pxor %xmm1,%xmm2 - 42f8be: 66 0f 38 17 c2 ptest %xmm2,%xmm0 - 42f8c3: 73 23 jae 42f8e8 <__memcmp_sse4_1+0x15e8> - 42f8c5: 48 8b 47 f0 mov -0x10(%rdi),%rax - 42f8c9: 48 8b 4e f0 mov -0x10(%rsi),%rcx - 42f8cd: 48 39 c1 cmp %rax,%rcx - 42f8d0: 75 31 jne 42f903 <__memcmp_sse4_1+0x1603> - 42f8d2: 48 8b 47 f8 mov -0x8(%rdi),%rax - 42f8d6: 48 8b 4e f8 mov -0x8(%rsi),%rcx - 42f8da: 48 39 c1 cmp %rax,%rcx - 42f8dd: 75 24 jne 42f903 <__memcmp_sse4_1+0x1603> - 42f8df: 31 c0 xor %eax,%eax - 42f8e1: c3 retq - 42f8e2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 42f8e8: 48 0f be d2 movsbq %dl,%rdx - 42f8ec: 48 8b 0c 16 mov (%rsi,%rdx,1),%rcx - 42f8f0: 48 8b 04 17 mov (%rdi,%rdx,1),%rax - 42f8f4: 48 39 c1 cmp %rax,%rcx - 42f8f7: 75 0a jne 42f903 <__memcmp_sse4_1+0x1603> - 42f8f9: 48 8b 4c 16 08 mov 0x8(%rsi,%rdx,1),%rcx - 42f8fe: 48 8b 44 17 08 mov 0x8(%rdi,%rdx,1),%rax - 42f903: 39 c1 cmp %eax,%ecx - 42f905: 75 08 jne 42f90f <__memcmp_sse4_1+0x160f> - 42f907: 48 c1 e9 20 shr $0x20,%rcx - 42f90b: 48 c1 e8 20 shr $0x20,%rax - 42f90f: 66 39 c8 cmp %cx,%ax - 42f912: 75 06 jne 42f91a <__memcmp_sse4_1+0x161a> - 42f914: c1 e9 10 shr $0x10,%ecx - 42f917: c1 e8 10 shr $0x10,%eax - 42f91a: 38 c8 cmp %cl,%al - 42f91c: 75 12 jne 42f930 <__memcmp_sse4_1+0x1630> - 42f91e: 25 ff ff 00 00 and $0xffff,%eax - 42f923: 81 e1 ff ff 00 00 and $0xffff,%ecx - 42f929: 29 c8 sub %ecx,%eax - 42f92b: c3 retq - 42f92c: 0f 1f 40 00 nopl 0x0(%rax) - 42f930: 25 ff 00 00 00 and $0xff,%eax - 42f935: 81 e1 ff 00 00 00 and $0xff,%ecx - 42f93b: 29 c8 sub %ecx,%eax - 42f93d: c3 retq - 42f93e: 66 90 xchg %ax,%ax - -000000000042f940 <__memmove_chk_ssse3>: - 42f940: 48 39 d1 cmp %rdx,%rcx - 42f943: 0f 82 67 31 01 00 jb 442ab0 <__chk_fail> - 42f949: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - -000000000042f950 <__memmove_ssse3>: - 42f950: 48 89 f8 mov %rdi,%rax - 42f953: 48 39 f7 cmp %rsi,%rdi - 42f956: 72 0e jb 42f966 <__memmove_ssse3+0x16> - 42f958: 0f 84 7a 1a 00 00 je 4313d8 <__memmove_ssse3+0x1a88> - 42f95e: 48 83 fa 4f cmp $0x4f,%rdx - 42f962: 76 02 jbe 42f966 <__memmove_ssse3+0x16> - 42f964: eb 7a jmp 42f9e0 <__memmove_ssse3+0x90> - 42f966: 48 83 fa 4f cmp $0x4f,%rdx - 42f96a: 4c 8d 1d 3f 3a 07 00 lea 0x73a3f(%rip),%r11 # 4a33b0 - 42f971: 77 1d ja 42f990 <__memmove_ssse3+0x40> - 42f973: 4d 63 0c 93 movslq (%r11,%rdx,4),%r9 - 42f977: 48 01 d6 add %rdx,%rsi - 42f97a: 48 01 d7 add %rdx,%rdi - 42f97d: 4d 01 d9 add %r11,%r9 - 42f980: 41 ff e1 jmpq *%r9 - 42f983: 0f 0b ud2 - 42f985: 90 nop - 42f986: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42f98d: 00 00 00 - 42f990: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 42f994: 48 89 f9 mov %rdi,%rcx - 42f997: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi - 42f99b: 48 83 c7 10 add $0x10,%rdi - 42f99f: 49 89 c8 mov %rcx,%r8 - 42f9a2: 48 29 f9 sub %rdi,%rcx - 42f9a5: 48 01 ca add %rcx,%rdx - 42f9a8: 48 29 ce sub %rcx,%rsi - 42f9ab: 48 8b 0d fe b6 29 00 mov 0x29b6fe(%rip),%rcx # 6cb0b0 <__x86_shared_cache_size_half> - 42f9b2: 48 39 ca cmp %rcx,%rdx - 42f9b5: 49 89 f1 mov %rsi,%r9 - 42f9b8: 0f 87 92 27 00 00 ja 432150 <__memmove_ssse3+0x2800> - 42f9be: 49 83 e1 0f and $0xf,%r9 - 42f9c2: 74 7c je 42fa40 <__memmove_ssse3+0xf0> - 42f9c4: 48 8b 0d 05 b7 29 00 mov 0x29b705(%rip),%rcx # 6cb0d0 <__x86_data_cache_size_half> - 42f9cb: 4c 8d 1d 1e 3b 07 00 lea 0x73b1e(%rip),%r11 # 4a34f0 - 42f9d2: 4f 63 0c 8b movslq (%r11,%r9,4),%r9 - 42f9d6: 4f 8d 0c 0b lea (%r11,%r9,1),%r9 - 42f9da: 41 ff e1 jmpq *%r9 - 42f9dd: 0f 0b ud2 - 42f9df: 90 nop - 42f9e0: f3 0f 6f 44 16 f0 movdqu -0x10(%rsi,%rdx,1),%xmm0 - 42f9e6: 48 01 d6 add %rdx,%rsi - 42f9e9: 4c 8d 44 17 f0 lea -0x10(%rdi,%rdx,1),%r8 - 42f9ee: 48 01 d7 add %rdx,%rdi - 42f9f1: 48 89 f9 mov %rdi,%rcx - 42f9f4: 48 83 e1 0f and $0xf,%rcx - 42f9f8: 48 31 cf xor %rcx,%rdi - 42f9fb: 48 29 ca sub %rcx,%rdx - 42f9fe: 48 29 ce sub %rcx,%rsi - 42fa01: 48 8b 0d a8 b6 29 00 mov 0x29b6a8(%rip),%rcx # 6cb0b0 <__x86_shared_cache_size_half> - 42fa08: 48 39 ca cmp %rcx,%rdx - 42fa0b: 49 89 f1 mov %rsi,%r9 - 42fa0e: 0f 87 fc 28 00 00 ja 432310 <__memmove_ssse3+0x29c0> - 42fa14: 49 83 e1 0f and $0xf,%r9 - 42fa18: 0f 84 42 02 00 00 je 42fc60 <__memmove_ssse3+0x310> - 42fa1e: 48 8b 0d ab b6 29 00 mov 0x29b6ab(%rip),%rcx # 6cb0d0 <__x86_data_cache_size_half> - 42fa25: 4c 8d 1d 04 3b 07 00 lea 0x73b04(%rip),%r11 # 4a3530 - 42fa2c: 4f 63 0c 8b movslq (%r11,%r9,4),%r9 - 42fa30: 4f 8d 0c 0b lea (%r11,%r9,1),%r9 - 42fa34: 41 ff e1 jmpq *%r9 - 42fa37: 0f 0b ud2 - 42fa39: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 42fa40: 48 83 ea 10 sub $0x10,%rdx - 42fa44: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 42fa48: 48 83 c6 10 add $0x10,%rsi - 42fa4c: 66 0f 7f 0f movdqa %xmm1,(%rdi) - 42fa50: 48 83 c7 10 add $0x10,%rdi - 42fa54: 48 81 fa 80 00 00 00 cmp $0x80,%rdx - 42fa5b: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 42fa60: 77 4e ja 42fab0 <__memmove_ssse3+0x160> - 42fa62: 48 83 fa 40 cmp $0x40,%rdx - 42fa66: 72 2a jb 42fa92 <__memmove_ssse3+0x142> - 42fa68: 0f 28 26 movaps (%rsi),%xmm4 - 42fa6b: 0f 28 4e 10 movaps 0x10(%rsi),%xmm1 - 42fa6f: 0f 28 56 20 movaps 0x20(%rsi),%xmm2 - 42fa73: 0f 28 5e 30 movaps 0x30(%rsi),%xmm3 - 42fa77: 0f 29 27 movaps %xmm4,(%rdi) - 42fa7a: 0f 29 4f 10 movaps %xmm1,0x10(%rdi) - 42fa7e: 0f 29 57 20 movaps %xmm2,0x20(%rdi) - 42fa82: 0f 29 5f 30 movaps %xmm3,0x30(%rdi) - 42fa86: 48 83 ea 40 sub $0x40,%rdx - 42fa8a: 48 83 c6 40 add $0x40,%rsi - 42fa8e: 48 83 c7 40 add $0x40,%rdi - 42fa92: 48 01 d6 add %rdx,%rsi - 42fa95: 48 01 d7 add %rdx,%rdi - 42fa98: 4c 8d 1d 11 39 07 00 lea 0x73911(%rip),%r11 # 4a33b0 - 42fa9f: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 42faa3: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 42faa7: ff e2 jmpq *%rdx - 42faa9: 0f 0b ud2 - 42faab: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 42fab0: 48 3b 15 19 b6 29 00 cmp 0x29b619(%rip),%rdx # 6cb0d0 <__x86_data_cache_size_half> - 42fab7: 48 8d 52 80 lea -0x80(%rdx),%rdx - 42fabb: 0f 83 af 00 00 00 jae 42fb70 <__memmove_ssse3+0x220> - 42fac1: 66 0f 6f 26 movdqa (%rsi),%xmm4 - 42fac5: 0f 28 4e 10 movaps 0x10(%rsi),%xmm1 - 42fac9: 0f 28 56 20 movaps 0x20(%rsi),%xmm2 - 42facd: 0f 28 5e 30 movaps 0x30(%rsi),%xmm3 - 42fad1: 66 0f 7f 27 movdqa %xmm4,(%rdi) - 42fad5: 0f 29 4f 10 movaps %xmm1,0x10(%rdi) - 42fad9: 0f 29 57 20 movaps %xmm2,0x20(%rdi) - 42fadd: 0f 29 5f 30 movaps %xmm3,0x30(%rdi) - 42fae1: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 42fae8: 0f 28 66 40 movaps 0x40(%rsi),%xmm4 - 42faec: 0f 28 6e 50 movaps 0x50(%rsi),%xmm5 - 42faf0: 0f 28 76 60 movaps 0x60(%rsi),%xmm6 - 42faf4: 0f 28 7e 70 movaps 0x70(%rsi),%xmm7 - 42faf8: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi - 42faff: 0f 29 67 40 movaps %xmm4,0x40(%rdi) - 42fb03: 0f 29 6f 50 movaps %xmm5,0x50(%rdi) - 42fb07: 0f 29 77 60 movaps %xmm6,0x60(%rdi) - 42fb0b: 0f 29 7f 70 movaps %xmm7,0x70(%rdi) - 42fb0f: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi - 42fb16: 73 a9 jae 42fac1 <__memmove_ssse3+0x171> - 42fb18: 48 83 fa c0 cmp $0xffffffffffffffc0,%rdx - 42fb1c: 48 8d 92 80 00 00 00 lea 0x80(%rdx),%rdx - 42fb23: 7c 32 jl 42fb57 <__memmove_ssse3+0x207> - 42fb25: 66 0f 6f 26 movdqa (%rsi),%xmm4 - 42fb29: 48 83 ea 40 sub $0x40,%rdx - 42fb2d: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 - 42fb32: 66 0f 7f 27 movdqa %xmm4,(%rdi) - 42fb36: 66 0f 7f 4f 10 movdqa %xmm1,0x10(%rdi) - 42fb3b: 66 0f 6f 66 20 movdqa 0x20(%rsi),%xmm4 - 42fb40: 66 0f 6f 4e 30 movdqa 0x30(%rsi),%xmm1 - 42fb45: 48 83 c6 40 add $0x40,%rsi - 42fb49: 66 0f 7f 67 20 movdqa %xmm4,0x20(%rdi) - 42fb4e: 66 0f 7f 4f 30 movdqa %xmm1,0x30(%rdi) - 42fb53: 48 83 c7 40 add $0x40,%rdi - 42fb57: 48 01 d6 add %rdx,%rsi - 42fb5a: 48 01 d7 add %rdx,%rdi - 42fb5d: 4c 8d 1d 4c 38 07 00 lea 0x7384c(%rip),%r11 # 4a33b0 - 42fb64: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 42fb68: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 42fb6c: ff e2 jmpq *%rdx - 42fb6e: 0f 0b ud2 - 42fb70: 0f 18 8e c0 01 00 00 prefetcht0 0x1c0(%rsi) - 42fb77: 0f 18 8e 80 02 00 00 prefetcht0 0x280(%rsi) - 42fb7e: 66 0f 6f 06 movdqa (%rsi),%xmm0 - 42fb82: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 - 42fb87: 66 0f 6f 56 20 movdqa 0x20(%rsi),%xmm2 - 42fb8c: 66 0f 6f 5e 30 movdqa 0x30(%rsi),%xmm3 - 42fb91: 66 0f 6f 66 40 movdqa 0x40(%rsi),%xmm4 - 42fb96: 66 0f 6f 6e 50 movdqa 0x50(%rsi),%xmm5 - 42fb9b: 66 0f 6f 76 60 movdqa 0x60(%rsi),%xmm6 - 42fba0: 66 0f 6f 7e 70 movdqa 0x70(%rsi),%xmm7 - 42fba5: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi - 42fbac: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 42fbb3: 66 0f 7f 07 movdqa %xmm0,(%rdi) - 42fbb7: 66 0f 7f 4f 10 movdqa %xmm1,0x10(%rdi) - 42fbbc: 66 0f 7f 57 20 movdqa %xmm2,0x20(%rdi) - 42fbc1: 66 0f 7f 5f 30 movdqa %xmm3,0x30(%rdi) - 42fbc6: 66 0f 7f 67 40 movdqa %xmm4,0x40(%rdi) - 42fbcb: 66 0f 7f 6f 50 movdqa %xmm5,0x50(%rdi) - 42fbd0: 66 0f 7f 77 60 movdqa %xmm6,0x60(%rdi) - 42fbd5: 66 0f 7f 7f 70 movdqa %xmm7,0x70(%rdi) - 42fbda: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi - 42fbe1: 73 8d jae 42fb70 <__memmove_ssse3+0x220> - 42fbe3: 48 83 fa c0 cmp $0xffffffffffffffc0,%rdx - 42fbe7: 48 8d 92 80 00 00 00 lea 0x80(%rdx),%rdx - 42fbee: 7c 32 jl 42fc22 <__memmove_ssse3+0x2d2> - 42fbf0: 66 0f 6f 06 movdqa (%rsi),%xmm0 - 42fbf4: 48 83 ea 40 sub $0x40,%rdx - 42fbf8: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 - 42fbfd: 66 0f 7f 07 movdqa %xmm0,(%rdi) - 42fc01: 66 0f 7f 4f 10 movdqa %xmm1,0x10(%rdi) - 42fc06: 66 0f 6f 46 20 movdqa 0x20(%rsi),%xmm0 - 42fc0b: 66 0f 6f 4e 30 movdqa 0x30(%rsi),%xmm1 - 42fc10: 48 83 c6 40 add $0x40,%rsi - 42fc14: 66 0f 7f 47 20 movdqa %xmm0,0x20(%rdi) - 42fc19: 66 0f 7f 4f 30 movdqa %xmm1,0x30(%rdi) - 42fc1e: 48 83 c7 40 add $0x40,%rdi - 42fc22: 48 83 fa 20 cmp $0x20,%rdx - 42fc26: 72 1e jb 42fc46 <__memmove_ssse3+0x2f6> - 42fc28: 66 0f 6f 06 movdqa (%rsi),%xmm0 - 42fc2c: 48 83 ea 20 sub $0x20,%rdx - 42fc30: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 - 42fc35: 48 83 c6 20 add $0x20,%rsi - 42fc39: 66 0f 7f 07 movdqa %xmm0,(%rdi) - 42fc3d: 66 0f 7f 4f 10 movdqa %xmm1,0x10(%rdi) - 42fc42: 48 83 c7 20 add $0x20,%rdi - 42fc46: 48 01 d7 add %rdx,%rdi - 42fc49: 48 01 d6 add %rdx,%rsi - 42fc4c: 4c 8d 1d 5d 37 07 00 lea 0x7375d(%rip),%r11 # 4a33b0 - 42fc53: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 42fc57: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 42fc5b: ff e2 jmpq *%rdx - 42fc5d: 0f 0b ud2 - 42fc5f: 90 nop - 42fc60: 48 83 ea 10 sub $0x10,%rdx - 42fc64: 66 0f 6f 4e f0 movdqa -0x10(%rsi),%xmm1 - 42fc69: 48 83 ee 10 sub $0x10,%rsi - 42fc6d: 66 0f 7f 4f f0 movdqa %xmm1,-0x10(%rdi) - 42fc72: 48 83 ef 10 sub $0x10,%rdi - 42fc76: 48 81 fa 80 00 00 00 cmp $0x80,%rdx - 42fc7d: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 42fc82: 77 4c ja 42fcd0 <__memmove_ssse3+0x380> - 42fc84: 48 83 fa 40 cmp $0x40,%rdx - 42fc88: 72 2c jb 42fcb6 <__memmove_ssse3+0x366> - 42fc8a: 0f 28 46 f0 movaps -0x10(%rsi),%xmm0 - 42fc8e: 0f 28 4e e0 movaps -0x20(%rsi),%xmm1 - 42fc92: 0f 28 56 d0 movaps -0x30(%rsi),%xmm2 - 42fc96: 0f 28 5e c0 movaps -0x40(%rsi),%xmm3 - 42fc9a: 0f 29 47 f0 movaps %xmm0,-0x10(%rdi) - 42fc9e: 0f 29 4f e0 movaps %xmm1,-0x20(%rdi) - 42fca2: 0f 29 57 d0 movaps %xmm2,-0x30(%rdi) - 42fca6: 0f 29 5f c0 movaps %xmm3,-0x40(%rdi) - 42fcaa: 48 83 ea 40 sub $0x40,%rdx - 42fcae: 48 83 ee 40 sub $0x40,%rsi - 42fcb2: 48 83 ef 40 sub $0x40,%rdi - 42fcb6: 4c 8d 1d f3 36 07 00 lea 0x736f3(%rip),%r11 # 4a33b0 - 42fcbd: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 42fcc1: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 42fcc5: ff e2 jmpq *%rdx - 42fcc7: 0f 0b ud2 - 42fcc9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 42fcd0: 48 3b 15 f9 b3 29 00 cmp 0x29b3f9(%rip),%rdx # 6cb0d0 <__x86_data_cache_size_half> - 42fcd7: 48 8d 52 80 lea -0x80(%rdx),%rdx - 42fcdb: 0f 83 af 00 00 00 jae 42fd90 <__memmove_ssse3+0x440> - 42fce1: 66 0f 6f 46 f0 movdqa -0x10(%rsi),%xmm0 - 42fce6: 0f 28 4e e0 movaps -0x20(%rsi),%xmm1 - 42fcea: 0f 28 56 d0 movaps -0x30(%rsi),%xmm2 - 42fcee: 0f 28 5e c0 movaps -0x40(%rsi),%xmm3 - 42fcf2: 66 0f 7f 47 f0 movdqa %xmm0,-0x10(%rdi) - 42fcf7: 0f 29 4f e0 movaps %xmm1,-0x20(%rdi) - 42fcfb: 0f 29 57 d0 movaps %xmm2,-0x30(%rdi) - 42fcff: 0f 29 5f c0 movaps %xmm3,-0x40(%rdi) - 42fd03: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 42fd0a: 0f 28 66 b0 movaps -0x50(%rsi),%xmm4 - 42fd0e: 0f 28 6e a0 movaps -0x60(%rsi),%xmm5 - 42fd12: 0f 28 76 90 movaps -0x70(%rsi),%xmm6 - 42fd16: 0f 28 7e 80 movaps -0x80(%rsi),%xmm7 - 42fd1a: 48 8d 76 80 lea -0x80(%rsi),%rsi - 42fd1e: 0f 29 67 b0 movaps %xmm4,-0x50(%rdi) - 42fd22: 0f 29 6f a0 movaps %xmm5,-0x60(%rdi) - 42fd26: 0f 29 77 90 movaps %xmm6,-0x70(%rdi) - 42fd2a: 0f 29 7f 80 movaps %xmm7,-0x80(%rdi) - 42fd2e: 48 8d 7f 80 lea -0x80(%rdi),%rdi - 42fd32: 73 ad jae 42fce1 <__memmove_ssse3+0x391> - 42fd34: 48 83 fa c0 cmp $0xffffffffffffffc0,%rdx - 42fd38: 48 8d 92 80 00 00 00 lea 0x80(%rdx),%rdx - 42fd3f: 7c 34 jl 42fd75 <__memmove_ssse3+0x425> - 42fd41: 66 0f 6f 46 f0 movdqa -0x10(%rsi),%xmm0 - 42fd46: 48 83 ea 40 sub $0x40,%rdx - 42fd4a: 66 0f 6f 4e e0 movdqa -0x20(%rsi),%xmm1 - 42fd4f: 66 0f 7f 47 f0 movdqa %xmm0,-0x10(%rdi) - 42fd54: 66 0f 7f 4f e0 movdqa %xmm1,-0x20(%rdi) - 42fd59: 66 0f 6f 46 d0 movdqa -0x30(%rsi),%xmm0 - 42fd5e: 66 0f 6f 4e c0 movdqa -0x40(%rsi),%xmm1 - 42fd63: 48 83 ee 40 sub $0x40,%rsi - 42fd67: 66 0f 7f 47 d0 movdqa %xmm0,-0x30(%rdi) - 42fd6c: 66 0f 7f 4f c0 movdqa %xmm1,-0x40(%rdi) - 42fd71: 48 83 ef 40 sub $0x40,%rdi - 42fd75: 4c 8d 1d 34 36 07 00 lea 0x73634(%rip),%r11 # 4a33b0 - 42fd7c: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 42fd80: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 42fd84: ff e2 jmpq *%rdx - 42fd86: 0f 0b ud2 - 42fd88: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 42fd8f: 00 - 42fd90: 0f 18 8e 40 fe ff ff prefetcht0 -0x1c0(%rsi) - 42fd97: 0f 18 8e 80 fd ff ff prefetcht0 -0x280(%rsi) - 42fd9e: 66 0f 6f 46 f0 movdqa -0x10(%rsi),%xmm0 - 42fda3: 66 0f 6f 4e e0 movdqa -0x20(%rsi),%xmm1 - 42fda8: 66 0f 6f 56 d0 movdqa -0x30(%rsi),%xmm2 - 42fdad: 66 0f 6f 5e c0 movdqa -0x40(%rsi),%xmm3 - 42fdb2: 66 0f 6f 66 b0 movdqa -0x50(%rsi),%xmm4 - 42fdb7: 66 0f 6f 6e a0 movdqa -0x60(%rsi),%xmm5 - 42fdbc: 66 0f 6f 76 90 movdqa -0x70(%rsi),%xmm6 - 42fdc1: 66 0f 6f 7e 80 movdqa -0x80(%rsi),%xmm7 - 42fdc6: 48 8d 76 80 lea -0x80(%rsi),%rsi - 42fdca: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 42fdd1: 66 0f 7f 47 f0 movdqa %xmm0,-0x10(%rdi) - 42fdd6: 66 0f 7f 4f e0 movdqa %xmm1,-0x20(%rdi) - 42fddb: 66 0f 7f 57 d0 movdqa %xmm2,-0x30(%rdi) - 42fde0: 66 0f 7f 5f c0 movdqa %xmm3,-0x40(%rdi) - 42fde5: 66 0f 7f 67 b0 movdqa %xmm4,-0x50(%rdi) - 42fdea: 66 0f 7f 6f a0 movdqa %xmm5,-0x60(%rdi) - 42fdef: 66 0f 7f 77 90 movdqa %xmm6,-0x70(%rdi) - 42fdf4: 66 0f 7f 7f 80 movdqa %xmm7,-0x80(%rdi) - 42fdf9: 48 8d 7f 80 lea -0x80(%rdi),%rdi - 42fdfd: 73 91 jae 42fd90 <__memmove_ssse3+0x440> - 42fdff: 48 83 fa c0 cmp $0xffffffffffffffc0,%rdx - 42fe03: 48 8d 92 80 00 00 00 lea 0x80(%rdx),%rdx - 42fe0a: 7c 34 jl 42fe40 <__memmove_ssse3+0x4f0> - 42fe0c: 66 0f 6f 46 f0 movdqa -0x10(%rsi),%xmm0 - 42fe11: 48 83 ea 40 sub $0x40,%rdx - 42fe15: 66 0f 6f 4e e0 movdqa -0x20(%rsi),%xmm1 - 42fe1a: 66 0f 7f 47 f0 movdqa %xmm0,-0x10(%rdi) - 42fe1f: 66 0f 7f 4f e0 movdqa %xmm1,-0x20(%rdi) - 42fe24: 66 0f 6f 46 d0 movdqa -0x30(%rsi),%xmm0 - 42fe29: 66 0f 6f 4e c0 movdqa -0x40(%rsi),%xmm1 - 42fe2e: 48 83 ee 40 sub $0x40,%rsi - 42fe32: 66 0f 7f 47 d0 movdqa %xmm0,-0x30(%rdi) - 42fe37: 66 0f 7f 4f c0 movdqa %xmm1,-0x40(%rdi) - 42fe3c: 48 83 ef 40 sub $0x40,%rdi - 42fe40: 48 83 fa 20 cmp $0x20,%rdx - 42fe44: 72 20 jb 42fe66 <__memmove_ssse3+0x516> - 42fe46: 66 0f 6f 46 f0 movdqa -0x10(%rsi),%xmm0 - 42fe4b: 48 83 ea 20 sub $0x20,%rdx - 42fe4f: 66 0f 6f 4e e0 movdqa -0x20(%rsi),%xmm1 - 42fe54: 48 83 ee 20 sub $0x20,%rsi - 42fe58: 66 0f 7f 47 f0 movdqa %xmm0,-0x10(%rdi) - 42fe5d: 66 0f 7f 4f e0 movdqa %xmm1,-0x20(%rdi) - 42fe62: 48 83 ef 20 sub $0x20,%rdi - 42fe66: 4c 8d 1d 43 35 07 00 lea 0x73543(%rip),%r11 # 4a33b0 - 42fe6d: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 42fe71: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 42fe75: ff e2 jmpq *%rdx - 42fe77: 0f 0b ud2 - 42fe79: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 42fe80: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 - 42fe87: 48 39 ca cmp %rcx,%rdx - 42fe8a: 0f 28 4e ff movaps -0x1(%rsi),%xmm1 - 42fe8e: 72 07 jb 42fe97 <__memmove_ssse3+0x547> - 42fe90: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 - 42fe97: 48 8d 52 c0 lea -0x40(%rdx),%rdx - 42fe9b: 41 ff e1 jmpq *%r9 - 42fe9e: 0f 0b ud2 - 42fea0: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) - 42fea7: 48 83 ea 40 sub $0x40,%rdx - 42feab: 0f 28 56 0f movaps 0xf(%rsi),%xmm2 - 42feaf: 0f 28 5e 1f movaps 0x1f(%rsi),%xmm3 - 42feb3: 0f 28 66 2f movaps 0x2f(%rsi),%xmm4 - 42feb7: 0f 28 6e 3f movaps 0x3f(%rsi),%xmm5 - 42febb: 66 0f 6f f5 movdqa %xmm5,%xmm6 - 42febf: 66 0f 3a 0f ec 01 palignr $0x1,%xmm4,%xmm5 - 42fec5: 48 8d 76 40 lea 0x40(%rsi),%rsi - 42fec9: 66 0f 3a 0f e3 01 palignr $0x1,%xmm3,%xmm4 - 42fecf: 66 0f 3a 0f da 01 palignr $0x1,%xmm2,%xmm3 - 42fed5: 48 8d 7f 40 lea 0x40(%rdi),%rdi - 42fed9: 66 0f 3a 0f d1 01 palignr $0x1,%xmm1,%xmm2 - 42fedf: 66 0f 6f ce movdqa %xmm6,%xmm1 - 42fee3: 66 0f 7f 57 c0 movdqa %xmm2,-0x40(%rdi) - 42fee8: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 42feec: 72 0d jb 42fefb <__memmove_ssse3+0x5ab> - 42feee: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) - 42fef2: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) - 42fef6: 41 ff e1 jmpq *%r9 - 42fef9: 0f 0b ud2 - 42fefb: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) - 42feff: 48 8d 52 40 lea 0x40(%rdx),%rdx - 42ff03: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) - 42ff07: 48 01 d7 add %rdx,%rdi - 42ff0a: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 42ff0f: 48 01 d6 add %rdx,%rsi - 42ff12: 4c 8d 1d 97 34 07 00 lea 0x73497(%rip),%r11 # 4a33b0 - 42ff19: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 42ff1d: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 42ff21: ff e2 jmpq *%rdx - 42ff23: 0f 0b ud2 - 42ff25: 90 nop - 42ff26: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42ff2d: 00 00 00 - 42ff30: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 - 42ff37: 48 39 ca cmp %rcx,%rdx - 42ff3a: 0f 28 4e ff movaps -0x1(%rsi),%xmm1 - 42ff3e: 72 07 jb 42ff47 <__memmove_ssse3+0x5f7> - 42ff40: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 - 42ff47: 48 8d 52 c0 lea -0x40(%rdx),%rdx - 42ff4b: 41 ff e1 jmpq *%r9 - 42ff4e: 0f 0b ud2 - 42ff50: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) - 42ff57: 0f 28 56 ef movaps -0x11(%rsi),%xmm2 - 42ff5b: 48 83 ea 40 sub $0x40,%rdx - 42ff5f: 0f 28 5e df movaps -0x21(%rsi),%xmm3 - 42ff63: 0f 28 66 cf movaps -0x31(%rsi),%xmm4 - 42ff67: 0f 28 6e bf movaps -0x41(%rsi),%xmm5 - 42ff6b: 48 8d 76 c0 lea -0x40(%rsi),%rsi - 42ff6f: 66 0f 3a 0f ca 01 palignr $0x1,%xmm2,%xmm1 - 42ff75: 66 0f 3a 0f d3 01 palignr $0x1,%xmm3,%xmm2 - 42ff7b: 66 0f 3a 0f dc 01 palignr $0x1,%xmm4,%xmm3 - 42ff81: 66 0f 3a 0f e5 01 palignr $0x1,%xmm5,%xmm4 - 42ff87: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 42ff8b: 0f 28 cd movaps %xmm5,%xmm1 - 42ff8e: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 42ff92: 48 8d 7f c0 lea -0x40(%rdi),%rdi - 42ff96: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) - 42ff9a: 72 08 jb 42ffa4 <__memmove_ssse3+0x654> - 42ff9c: 0f 29 27 movaps %xmm4,(%rdi) - 42ff9f: 41 ff e1 jmpq *%r9 - 42ffa2: 0f 0b ud2 - 42ffa4: 0f 29 27 movaps %xmm4,(%rdi) - 42ffa7: 48 8d 52 40 lea 0x40(%rdx),%rdx - 42ffab: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 42ffb0: 4c 8d 1d f9 33 07 00 lea 0x733f9(%rip),%r11 # 4a33b0 - 42ffb7: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 42ffbb: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 42ffbf: ff e2 jmpq *%rdx - 42ffc1: 0f 0b ud2 - 42ffc3: 0f 1f 00 nopl (%rax) - 42ffc6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 42ffcd: 00 00 00 - 42ffd0: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 - 42ffd7: 48 39 ca cmp %rcx,%rdx - 42ffda: 0f 28 4e fe movaps -0x2(%rsi),%xmm1 - 42ffde: 72 07 jb 42ffe7 <__memmove_ssse3+0x697> - 42ffe0: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 - 42ffe7: 48 8d 52 c0 lea -0x40(%rdx),%rdx - 42ffeb: 41 ff e1 jmpq *%r9 - 42ffee: 0f 0b ud2 - 42fff0: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) - 42fff7: 48 83 ea 40 sub $0x40,%rdx - 42fffb: 0f 28 56 0e movaps 0xe(%rsi),%xmm2 - 42ffff: 0f 28 5e 1e movaps 0x1e(%rsi),%xmm3 - 430003: 0f 28 66 2e movaps 0x2e(%rsi),%xmm4 - 430007: 0f 28 6e 3e movaps 0x3e(%rsi),%xmm5 - 43000b: 66 0f 6f f5 movdqa %xmm5,%xmm6 - 43000f: 66 0f 3a 0f ec 02 palignr $0x2,%xmm4,%xmm5 - 430015: 48 8d 76 40 lea 0x40(%rsi),%rsi - 430019: 66 0f 3a 0f e3 02 palignr $0x2,%xmm3,%xmm4 - 43001f: 66 0f 3a 0f da 02 palignr $0x2,%xmm2,%xmm3 - 430025: 48 8d 7f 40 lea 0x40(%rdi),%rdi - 430029: 66 0f 3a 0f d1 02 palignr $0x2,%xmm1,%xmm2 - 43002f: 66 0f 6f ce movdqa %xmm6,%xmm1 - 430033: 66 0f 7f 57 c0 movdqa %xmm2,-0x40(%rdi) - 430038: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 43003c: 72 0d jb 43004b <__memmove_ssse3+0x6fb> - 43003e: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) - 430042: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) - 430046: 41 ff e1 jmpq *%r9 - 430049: 0f 0b ud2 - 43004b: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) - 43004f: 48 8d 52 40 lea 0x40(%rdx),%rdx - 430053: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) - 430057: 48 01 d7 add %rdx,%rdi - 43005a: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 43005f: 48 01 d6 add %rdx,%rsi - 430062: 4c 8d 1d 47 33 07 00 lea 0x73347(%rip),%r11 # 4a33b0 - 430069: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 43006d: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 430071: ff e2 jmpq *%rdx - 430073: 0f 0b ud2 - 430075: 90 nop - 430076: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43007d: 00 00 00 - 430080: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 - 430087: 48 39 ca cmp %rcx,%rdx - 43008a: 0f 28 4e fe movaps -0x2(%rsi),%xmm1 - 43008e: 72 07 jb 430097 <__memmove_ssse3+0x747> - 430090: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 - 430097: 48 8d 52 c0 lea -0x40(%rdx),%rdx - 43009b: 41 ff e1 jmpq *%r9 - 43009e: 0f 0b ud2 - 4300a0: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) - 4300a7: 0f 28 56 ee movaps -0x12(%rsi),%xmm2 - 4300ab: 48 83 ea 40 sub $0x40,%rdx - 4300af: 0f 28 5e de movaps -0x22(%rsi),%xmm3 - 4300b3: 0f 28 66 ce movaps -0x32(%rsi),%xmm4 - 4300b7: 0f 28 6e be movaps -0x42(%rsi),%xmm5 - 4300bb: 48 8d 76 c0 lea -0x40(%rsi),%rsi - 4300bf: 66 0f 3a 0f ca 02 palignr $0x2,%xmm2,%xmm1 - 4300c5: 66 0f 3a 0f d3 02 palignr $0x2,%xmm3,%xmm2 - 4300cb: 66 0f 3a 0f dc 02 palignr $0x2,%xmm4,%xmm3 - 4300d1: 66 0f 3a 0f e5 02 palignr $0x2,%xmm5,%xmm4 - 4300d7: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 4300db: 0f 28 cd movaps %xmm5,%xmm1 - 4300de: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 4300e2: 48 8d 7f c0 lea -0x40(%rdi),%rdi - 4300e6: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) - 4300ea: 72 08 jb 4300f4 <__memmove_ssse3+0x7a4> - 4300ec: 0f 29 27 movaps %xmm4,(%rdi) - 4300ef: 41 ff e1 jmpq *%r9 - 4300f2: 0f 0b ud2 - 4300f4: 0f 29 27 movaps %xmm4,(%rdi) - 4300f7: 48 8d 52 40 lea 0x40(%rdx),%rdx - 4300fb: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 430100: 4c 8d 1d a9 32 07 00 lea 0x732a9(%rip),%r11 # 4a33b0 - 430107: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 43010b: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 43010f: ff e2 jmpq *%rdx - 430111: 0f 0b ud2 - 430113: 0f 1f 00 nopl (%rax) - 430116: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43011d: 00 00 00 - 430120: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 - 430127: 48 39 ca cmp %rcx,%rdx - 43012a: 0f 28 4e fd movaps -0x3(%rsi),%xmm1 - 43012e: 72 07 jb 430137 <__memmove_ssse3+0x7e7> - 430130: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 - 430137: 48 8d 52 c0 lea -0x40(%rdx),%rdx - 43013b: 41 ff e1 jmpq *%r9 - 43013e: 0f 0b ud2 - 430140: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) - 430147: 48 83 ea 40 sub $0x40,%rdx - 43014b: 0f 28 56 0d movaps 0xd(%rsi),%xmm2 - 43014f: 0f 28 5e 1d movaps 0x1d(%rsi),%xmm3 - 430153: 0f 28 66 2d movaps 0x2d(%rsi),%xmm4 - 430157: 0f 28 6e 3d movaps 0x3d(%rsi),%xmm5 - 43015b: 66 0f 6f f5 movdqa %xmm5,%xmm6 - 43015f: 66 0f 3a 0f ec 03 palignr $0x3,%xmm4,%xmm5 - 430165: 48 8d 76 40 lea 0x40(%rsi),%rsi - 430169: 66 0f 3a 0f e3 03 palignr $0x3,%xmm3,%xmm4 - 43016f: 66 0f 3a 0f da 03 palignr $0x3,%xmm2,%xmm3 - 430175: 48 8d 7f 40 lea 0x40(%rdi),%rdi - 430179: 66 0f 3a 0f d1 03 palignr $0x3,%xmm1,%xmm2 - 43017f: 66 0f 6f ce movdqa %xmm6,%xmm1 - 430183: 66 0f 7f 57 c0 movdqa %xmm2,-0x40(%rdi) - 430188: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 43018c: 72 0d jb 43019b <__memmove_ssse3+0x84b> - 43018e: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) - 430192: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) - 430196: 41 ff e1 jmpq *%r9 - 430199: 0f 0b ud2 - 43019b: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) - 43019f: 48 8d 52 40 lea 0x40(%rdx),%rdx - 4301a3: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) - 4301a7: 48 01 d7 add %rdx,%rdi - 4301aa: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 4301af: 48 01 d6 add %rdx,%rsi - 4301b2: 4c 8d 1d f7 31 07 00 lea 0x731f7(%rip),%r11 # 4a33b0 - 4301b9: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 4301bd: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 4301c1: ff e2 jmpq *%rdx - 4301c3: 0f 0b ud2 - 4301c5: 90 nop - 4301c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4301cd: 00 00 00 - 4301d0: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 - 4301d7: 48 39 ca cmp %rcx,%rdx - 4301da: 0f 28 4e fd movaps -0x3(%rsi),%xmm1 - 4301de: 72 07 jb 4301e7 <__memmove_ssse3+0x897> - 4301e0: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 - 4301e7: 48 8d 52 c0 lea -0x40(%rdx),%rdx - 4301eb: 41 ff e1 jmpq *%r9 - 4301ee: 0f 0b ud2 - 4301f0: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) - 4301f7: 0f 28 56 ed movaps -0x13(%rsi),%xmm2 - 4301fb: 48 83 ea 40 sub $0x40,%rdx - 4301ff: 0f 28 5e dd movaps -0x23(%rsi),%xmm3 - 430203: 0f 28 66 cd movaps -0x33(%rsi),%xmm4 - 430207: 0f 28 6e bd movaps -0x43(%rsi),%xmm5 - 43020b: 48 8d 76 c0 lea -0x40(%rsi),%rsi - 43020f: 66 0f 3a 0f ca 03 palignr $0x3,%xmm2,%xmm1 - 430215: 66 0f 3a 0f d3 03 palignr $0x3,%xmm3,%xmm2 - 43021b: 66 0f 3a 0f dc 03 palignr $0x3,%xmm4,%xmm3 - 430221: 66 0f 3a 0f e5 03 palignr $0x3,%xmm5,%xmm4 - 430227: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 43022b: 0f 28 cd movaps %xmm5,%xmm1 - 43022e: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 430232: 48 8d 7f c0 lea -0x40(%rdi),%rdi - 430236: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) - 43023a: 72 08 jb 430244 <__memmove_ssse3+0x8f4> - 43023c: 0f 29 27 movaps %xmm4,(%rdi) - 43023f: 41 ff e1 jmpq *%r9 - 430242: 0f 0b ud2 - 430244: 0f 29 27 movaps %xmm4,(%rdi) - 430247: 48 8d 52 40 lea 0x40(%rdx),%rdx - 43024b: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 430250: 4c 8d 1d 59 31 07 00 lea 0x73159(%rip),%r11 # 4a33b0 - 430257: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 43025b: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 43025f: ff e2 jmpq *%rdx - 430261: 0f 0b ud2 - 430263: 0f 1f 00 nopl (%rax) - 430266: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43026d: 00 00 00 - 430270: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 - 430277: 48 39 ca cmp %rcx,%rdx - 43027a: 0f 28 4e fc movaps -0x4(%rsi),%xmm1 - 43027e: 72 07 jb 430287 <__memmove_ssse3+0x937> - 430280: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 - 430287: 48 8d 52 c0 lea -0x40(%rdx),%rdx - 43028b: 41 ff e1 jmpq *%r9 - 43028e: 0f 0b ud2 - 430290: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) - 430297: 48 83 ea 40 sub $0x40,%rdx - 43029b: 0f 28 56 0c movaps 0xc(%rsi),%xmm2 - 43029f: 0f 28 5e 1c movaps 0x1c(%rsi),%xmm3 - 4302a3: 0f 28 66 2c movaps 0x2c(%rsi),%xmm4 - 4302a7: 0f 28 6e 3c movaps 0x3c(%rsi),%xmm5 - 4302ab: 66 0f 6f f5 movdqa %xmm5,%xmm6 - 4302af: 66 0f 3a 0f ec 04 palignr $0x4,%xmm4,%xmm5 - 4302b5: 48 8d 76 40 lea 0x40(%rsi),%rsi - 4302b9: 66 0f 3a 0f e3 04 palignr $0x4,%xmm3,%xmm4 - 4302bf: 66 0f 3a 0f da 04 palignr $0x4,%xmm2,%xmm3 - 4302c5: 48 8d 7f 40 lea 0x40(%rdi),%rdi - 4302c9: 66 0f 3a 0f d1 04 palignr $0x4,%xmm1,%xmm2 - 4302cf: 66 0f 6f ce movdqa %xmm6,%xmm1 - 4302d3: 66 0f 7f 57 c0 movdqa %xmm2,-0x40(%rdi) - 4302d8: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 4302dc: 72 0d jb 4302eb <__memmove_ssse3+0x99b> - 4302de: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) - 4302e2: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) - 4302e6: 41 ff e1 jmpq *%r9 - 4302e9: 0f 0b ud2 - 4302eb: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) - 4302ef: 48 8d 52 40 lea 0x40(%rdx),%rdx - 4302f3: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) - 4302f7: 48 01 d7 add %rdx,%rdi - 4302fa: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 4302ff: 48 01 d6 add %rdx,%rsi - 430302: 4c 8d 1d a7 30 07 00 lea 0x730a7(%rip),%r11 # 4a33b0 - 430309: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 43030d: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 430311: ff e2 jmpq *%rdx - 430313: 0f 0b ud2 - 430315: 90 nop - 430316: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43031d: 00 00 00 - 430320: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 - 430327: 48 39 ca cmp %rcx,%rdx - 43032a: 0f 28 4e fc movaps -0x4(%rsi),%xmm1 - 43032e: 72 07 jb 430337 <__memmove_ssse3+0x9e7> - 430330: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 - 430337: 48 8d 52 c0 lea -0x40(%rdx),%rdx - 43033b: 41 ff e1 jmpq *%r9 - 43033e: 0f 0b ud2 - 430340: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) - 430347: 0f 28 56 ec movaps -0x14(%rsi),%xmm2 - 43034b: 48 83 ea 40 sub $0x40,%rdx - 43034f: 0f 28 5e dc movaps -0x24(%rsi),%xmm3 - 430353: 0f 28 66 cc movaps -0x34(%rsi),%xmm4 - 430357: 0f 28 6e bc movaps -0x44(%rsi),%xmm5 - 43035b: 48 8d 76 c0 lea -0x40(%rsi),%rsi - 43035f: 66 0f 3a 0f ca 04 palignr $0x4,%xmm2,%xmm1 - 430365: 66 0f 3a 0f d3 04 palignr $0x4,%xmm3,%xmm2 - 43036b: 66 0f 3a 0f dc 04 palignr $0x4,%xmm4,%xmm3 - 430371: 66 0f 3a 0f e5 04 palignr $0x4,%xmm5,%xmm4 - 430377: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 43037b: 0f 28 cd movaps %xmm5,%xmm1 - 43037e: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 430382: 48 8d 7f c0 lea -0x40(%rdi),%rdi - 430386: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) - 43038a: 72 08 jb 430394 <__memmove_ssse3+0xa44> - 43038c: 0f 29 27 movaps %xmm4,(%rdi) - 43038f: 41 ff e1 jmpq *%r9 - 430392: 0f 0b ud2 - 430394: 0f 29 27 movaps %xmm4,(%rdi) - 430397: 48 8d 52 40 lea 0x40(%rdx),%rdx - 43039b: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 4303a0: 4c 8d 1d 09 30 07 00 lea 0x73009(%rip),%r11 # 4a33b0 - 4303a7: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 4303ab: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 4303af: ff e2 jmpq *%rdx - 4303b1: 0f 0b ud2 - 4303b3: 0f 1f 00 nopl (%rax) - 4303b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4303bd: 00 00 00 - 4303c0: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 - 4303c7: 48 39 ca cmp %rcx,%rdx - 4303ca: 0f 28 4e fb movaps -0x5(%rsi),%xmm1 - 4303ce: 72 07 jb 4303d7 <__memmove_ssse3+0xa87> - 4303d0: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 - 4303d7: 48 8d 52 c0 lea -0x40(%rdx),%rdx - 4303db: 41 ff e1 jmpq *%r9 - 4303de: 0f 0b ud2 - 4303e0: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) - 4303e7: 48 83 ea 40 sub $0x40,%rdx - 4303eb: 0f 28 56 0b movaps 0xb(%rsi),%xmm2 - 4303ef: 0f 28 5e 1b movaps 0x1b(%rsi),%xmm3 - 4303f3: 0f 28 66 2b movaps 0x2b(%rsi),%xmm4 - 4303f7: 0f 28 6e 3b movaps 0x3b(%rsi),%xmm5 - 4303fb: 66 0f 6f f5 movdqa %xmm5,%xmm6 - 4303ff: 66 0f 3a 0f ec 05 palignr $0x5,%xmm4,%xmm5 - 430405: 48 8d 76 40 lea 0x40(%rsi),%rsi - 430409: 66 0f 3a 0f e3 05 palignr $0x5,%xmm3,%xmm4 - 43040f: 66 0f 3a 0f da 05 palignr $0x5,%xmm2,%xmm3 - 430415: 48 8d 7f 40 lea 0x40(%rdi),%rdi - 430419: 66 0f 3a 0f d1 05 palignr $0x5,%xmm1,%xmm2 - 43041f: 66 0f 6f ce movdqa %xmm6,%xmm1 - 430423: 66 0f 7f 57 c0 movdqa %xmm2,-0x40(%rdi) - 430428: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 43042c: 72 0d jb 43043b <__memmove_ssse3+0xaeb> - 43042e: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) - 430432: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) - 430436: 41 ff e1 jmpq *%r9 - 430439: 0f 0b ud2 - 43043b: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) - 43043f: 48 8d 52 40 lea 0x40(%rdx),%rdx - 430443: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) - 430447: 48 01 d7 add %rdx,%rdi - 43044a: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 43044f: 48 01 d6 add %rdx,%rsi - 430452: 4c 8d 1d 57 2f 07 00 lea 0x72f57(%rip),%r11 # 4a33b0 - 430459: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 43045d: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 430461: ff e2 jmpq *%rdx - 430463: 0f 0b ud2 - 430465: 90 nop - 430466: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43046d: 00 00 00 - 430470: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 - 430477: 48 39 ca cmp %rcx,%rdx - 43047a: 0f 28 4e fb movaps -0x5(%rsi),%xmm1 - 43047e: 72 07 jb 430487 <__memmove_ssse3+0xb37> - 430480: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 - 430487: 48 8d 52 c0 lea -0x40(%rdx),%rdx - 43048b: 41 ff e1 jmpq *%r9 - 43048e: 0f 0b ud2 - 430490: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) - 430497: 0f 28 56 eb movaps -0x15(%rsi),%xmm2 - 43049b: 48 83 ea 40 sub $0x40,%rdx - 43049f: 0f 28 5e db movaps -0x25(%rsi),%xmm3 - 4304a3: 0f 28 66 cb movaps -0x35(%rsi),%xmm4 - 4304a7: 0f 28 6e bb movaps -0x45(%rsi),%xmm5 - 4304ab: 48 8d 76 c0 lea -0x40(%rsi),%rsi - 4304af: 66 0f 3a 0f ca 05 palignr $0x5,%xmm2,%xmm1 - 4304b5: 66 0f 3a 0f d3 05 palignr $0x5,%xmm3,%xmm2 - 4304bb: 66 0f 3a 0f dc 05 palignr $0x5,%xmm4,%xmm3 - 4304c1: 66 0f 3a 0f e5 05 palignr $0x5,%xmm5,%xmm4 - 4304c7: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 4304cb: 0f 28 cd movaps %xmm5,%xmm1 - 4304ce: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 4304d2: 48 8d 7f c0 lea -0x40(%rdi),%rdi - 4304d6: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) - 4304da: 72 08 jb 4304e4 <__memmove_ssse3+0xb94> - 4304dc: 0f 29 27 movaps %xmm4,(%rdi) - 4304df: 41 ff e1 jmpq *%r9 - 4304e2: 0f 0b ud2 - 4304e4: 0f 29 27 movaps %xmm4,(%rdi) - 4304e7: 48 8d 52 40 lea 0x40(%rdx),%rdx - 4304eb: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 4304f0: 4c 8d 1d b9 2e 07 00 lea 0x72eb9(%rip),%r11 # 4a33b0 - 4304f7: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 4304fb: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 4304ff: ff e2 jmpq *%rdx - 430501: 0f 0b ud2 - 430503: 0f 1f 00 nopl (%rax) - 430506: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43050d: 00 00 00 - 430510: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 - 430517: 48 39 ca cmp %rcx,%rdx - 43051a: 0f 28 4e fa movaps -0x6(%rsi),%xmm1 - 43051e: 72 07 jb 430527 <__memmove_ssse3+0xbd7> - 430520: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 - 430527: 48 8d 52 c0 lea -0x40(%rdx),%rdx - 43052b: 41 ff e1 jmpq *%r9 - 43052e: 0f 0b ud2 - 430530: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) - 430537: 48 83 ea 40 sub $0x40,%rdx - 43053b: 0f 28 56 0a movaps 0xa(%rsi),%xmm2 - 43053f: 0f 28 5e 1a movaps 0x1a(%rsi),%xmm3 - 430543: 0f 28 66 2a movaps 0x2a(%rsi),%xmm4 - 430547: 0f 28 6e 3a movaps 0x3a(%rsi),%xmm5 - 43054b: 66 0f 6f f5 movdqa %xmm5,%xmm6 - 43054f: 66 0f 3a 0f ec 06 palignr $0x6,%xmm4,%xmm5 - 430555: 48 8d 76 40 lea 0x40(%rsi),%rsi - 430559: 66 0f 3a 0f e3 06 palignr $0x6,%xmm3,%xmm4 - 43055f: 66 0f 3a 0f da 06 palignr $0x6,%xmm2,%xmm3 - 430565: 48 8d 7f 40 lea 0x40(%rdi),%rdi - 430569: 66 0f 3a 0f d1 06 palignr $0x6,%xmm1,%xmm2 - 43056f: 66 0f 6f ce movdqa %xmm6,%xmm1 - 430573: 66 0f 7f 57 c0 movdqa %xmm2,-0x40(%rdi) - 430578: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 43057c: 72 0d jb 43058b <__memmove_ssse3+0xc3b> - 43057e: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) - 430582: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) - 430586: 41 ff e1 jmpq *%r9 - 430589: 0f 0b ud2 - 43058b: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) - 43058f: 48 8d 52 40 lea 0x40(%rdx),%rdx - 430593: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) - 430597: 48 01 d7 add %rdx,%rdi - 43059a: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 43059f: 48 01 d6 add %rdx,%rsi - 4305a2: 4c 8d 1d 07 2e 07 00 lea 0x72e07(%rip),%r11 # 4a33b0 - 4305a9: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 4305ad: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 4305b1: ff e2 jmpq *%rdx - 4305b3: 0f 0b ud2 - 4305b5: 90 nop - 4305b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4305bd: 00 00 00 - 4305c0: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 - 4305c7: 48 39 ca cmp %rcx,%rdx - 4305ca: 0f 28 4e fa movaps -0x6(%rsi),%xmm1 - 4305ce: 72 07 jb 4305d7 <__memmove_ssse3+0xc87> - 4305d0: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 - 4305d7: 48 8d 52 c0 lea -0x40(%rdx),%rdx - 4305db: 41 ff e1 jmpq *%r9 - 4305de: 0f 0b ud2 - 4305e0: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) - 4305e7: 0f 28 56 ea movaps -0x16(%rsi),%xmm2 - 4305eb: 48 83 ea 40 sub $0x40,%rdx - 4305ef: 0f 28 5e da movaps -0x26(%rsi),%xmm3 - 4305f3: 0f 28 66 ca movaps -0x36(%rsi),%xmm4 - 4305f7: 0f 28 6e ba movaps -0x46(%rsi),%xmm5 - 4305fb: 48 8d 76 c0 lea -0x40(%rsi),%rsi - 4305ff: 66 0f 3a 0f ca 06 palignr $0x6,%xmm2,%xmm1 - 430605: 66 0f 3a 0f d3 06 palignr $0x6,%xmm3,%xmm2 - 43060b: 66 0f 3a 0f dc 06 palignr $0x6,%xmm4,%xmm3 - 430611: 66 0f 3a 0f e5 06 palignr $0x6,%xmm5,%xmm4 - 430617: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 43061b: 0f 28 cd movaps %xmm5,%xmm1 - 43061e: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 430622: 48 8d 7f c0 lea -0x40(%rdi),%rdi - 430626: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) - 43062a: 72 08 jb 430634 <__memmove_ssse3+0xce4> - 43062c: 0f 29 27 movaps %xmm4,(%rdi) - 43062f: 41 ff e1 jmpq *%r9 - 430632: 0f 0b ud2 - 430634: 0f 29 27 movaps %xmm4,(%rdi) - 430637: 48 8d 52 40 lea 0x40(%rdx),%rdx - 43063b: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 430640: 4c 8d 1d 69 2d 07 00 lea 0x72d69(%rip),%r11 # 4a33b0 - 430647: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 43064b: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 43064f: ff e2 jmpq *%rdx - 430651: 0f 0b ud2 - 430653: 0f 1f 00 nopl (%rax) - 430656: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43065d: 00 00 00 - 430660: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 - 430667: 48 39 ca cmp %rcx,%rdx - 43066a: 0f 28 4e f9 movaps -0x7(%rsi),%xmm1 - 43066e: 72 07 jb 430677 <__memmove_ssse3+0xd27> - 430670: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 - 430677: 48 8d 52 c0 lea -0x40(%rdx),%rdx - 43067b: 41 ff e1 jmpq *%r9 - 43067e: 0f 0b ud2 - 430680: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) - 430687: 48 83 ea 40 sub $0x40,%rdx - 43068b: 0f 28 56 09 movaps 0x9(%rsi),%xmm2 - 43068f: 0f 28 5e 19 movaps 0x19(%rsi),%xmm3 - 430693: 0f 28 66 29 movaps 0x29(%rsi),%xmm4 - 430697: 0f 28 6e 39 movaps 0x39(%rsi),%xmm5 - 43069b: 66 0f 6f f5 movdqa %xmm5,%xmm6 - 43069f: 66 0f 3a 0f ec 07 palignr $0x7,%xmm4,%xmm5 - 4306a5: 48 8d 76 40 lea 0x40(%rsi),%rsi - 4306a9: 66 0f 3a 0f e3 07 palignr $0x7,%xmm3,%xmm4 - 4306af: 66 0f 3a 0f da 07 palignr $0x7,%xmm2,%xmm3 - 4306b5: 48 8d 7f 40 lea 0x40(%rdi),%rdi - 4306b9: 66 0f 3a 0f d1 07 palignr $0x7,%xmm1,%xmm2 - 4306bf: 66 0f 6f ce movdqa %xmm6,%xmm1 - 4306c3: 66 0f 7f 57 c0 movdqa %xmm2,-0x40(%rdi) - 4306c8: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 4306cc: 72 0d jb 4306db <__memmove_ssse3+0xd8b> - 4306ce: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) - 4306d2: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) - 4306d6: 41 ff e1 jmpq *%r9 - 4306d9: 0f 0b ud2 - 4306db: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) - 4306df: 48 8d 52 40 lea 0x40(%rdx),%rdx - 4306e3: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) - 4306e7: 48 01 d7 add %rdx,%rdi - 4306ea: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 4306ef: 48 01 d6 add %rdx,%rsi - 4306f2: 4c 8d 1d b7 2c 07 00 lea 0x72cb7(%rip),%r11 # 4a33b0 - 4306f9: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 4306fd: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 430701: ff e2 jmpq *%rdx - 430703: 0f 0b ud2 - 430705: 90 nop - 430706: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43070d: 00 00 00 - 430710: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 - 430717: 48 39 ca cmp %rcx,%rdx - 43071a: 0f 28 4e f9 movaps -0x7(%rsi),%xmm1 - 43071e: 72 07 jb 430727 <__memmove_ssse3+0xdd7> - 430720: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 - 430727: 48 8d 52 c0 lea -0x40(%rdx),%rdx - 43072b: 41 ff e1 jmpq *%r9 - 43072e: 0f 0b ud2 - 430730: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) - 430737: 0f 28 56 e9 movaps -0x17(%rsi),%xmm2 - 43073b: 48 83 ea 40 sub $0x40,%rdx - 43073f: 0f 28 5e d9 movaps -0x27(%rsi),%xmm3 - 430743: 0f 28 66 c9 movaps -0x37(%rsi),%xmm4 - 430747: 0f 28 6e b9 movaps -0x47(%rsi),%xmm5 - 43074b: 48 8d 76 c0 lea -0x40(%rsi),%rsi - 43074f: 66 0f 3a 0f ca 07 palignr $0x7,%xmm2,%xmm1 - 430755: 66 0f 3a 0f d3 07 palignr $0x7,%xmm3,%xmm2 - 43075b: 66 0f 3a 0f dc 07 palignr $0x7,%xmm4,%xmm3 - 430761: 66 0f 3a 0f e5 07 palignr $0x7,%xmm5,%xmm4 - 430767: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 43076b: 0f 28 cd movaps %xmm5,%xmm1 - 43076e: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 430772: 48 8d 7f c0 lea -0x40(%rdi),%rdi - 430776: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) - 43077a: 72 08 jb 430784 <__memmove_ssse3+0xe34> - 43077c: 0f 29 27 movaps %xmm4,(%rdi) - 43077f: 41 ff e1 jmpq *%r9 - 430782: 0f 0b ud2 - 430784: 0f 29 27 movaps %xmm4,(%rdi) - 430787: 48 8d 52 40 lea 0x40(%rdx),%rdx - 43078b: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 430790: 4c 8d 1d 19 2c 07 00 lea 0x72c19(%rip),%r11 # 4a33b0 - 430797: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 43079b: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 43079f: ff e2 jmpq *%rdx - 4307a1: 0f 0b ud2 - 4307a3: 0f 1f 00 nopl (%rax) - 4307a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4307ad: 00 00 00 - 4307b0: 4d 8d 89 25 00 00 00 lea 0x25(%r9),%r9 - 4307b7: 48 39 ca cmp %rcx,%rdx - 4307ba: 0f 28 4e f8 movaps -0x8(%rsi),%xmm1 - 4307be: 72 07 jb 4307c7 <__memmove_ssse3+0xe77> - 4307c0: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 - 4307c7: 48 8d 52 c0 lea -0x40(%rdx),%rdx - 4307cb: 41 ff e1 jmpq *%r9 - 4307ce: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) - 4307d5: 48 83 ea 40 sub $0x40,%rdx - 4307d9: 0f 28 56 08 movaps 0x8(%rsi),%xmm2 - 4307dd: 0f 28 5e 18 movaps 0x18(%rsi),%xmm3 - 4307e1: 0f 28 66 28 movaps 0x28(%rsi),%xmm4 - 4307e5: 0f 28 6e 38 movaps 0x38(%rsi),%xmm5 - 4307e9: 66 0f 6f f5 movdqa %xmm5,%xmm6 - 4307ed: 66 0f 3a 0f ec 08 palignr $0x8,%xmm4,%xmm5 - 4307f3: 48 8d 76 40 lea 0x40(%rsi),%rsi - 4307f7: 66 0f 3a 0f e3 08 palignr $0x8,%xmm3,%xmm4 - 4307fd: 66 0f 3a 0f da 08 palignr $0x8,%xmm2,%xmm3 - 430803: 48 8d 7f 40 lea 0x40(%rdi),%rdi - 430807: 66 0f 3a 0f d1 08 palignr $0x8,%xmm1,%xmm2 - 43080d: 66 0f 6f ce movdqa %xmm6,%xmm1 - 430811: 66 0f 7f 57 c0 movdqa %xmm2,-0x40(%rdi) - 430816: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 43081a: 72 14 jb 430830 <__memmove_ssse3+0xee0> - 43081c: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) - 430820: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) - 430824: 41 ff e1 jmpq *%r9 - 430827: 0f 0b ud2 - 430829: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 430830: 48 8d 52 40 lea 0x40(%rdx),%rdx - 430834: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) - 430838: 48 01 d6 add %rdx,%rsi - 43083b: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) - 43083f: 48 01 d7 add %rdx,%rdi - 430842: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 430847: 4c 8d 1d 62 2b 07 00 lea 0x72b62(%rip),%r11 # 4a33b0 - 43084e: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 430852: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 430856: ff e2 jmpq *%rdx - 430858: 0f 0b ud2 - 43085a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 430860: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 - 430867: 48 39 ca cmp %rcx,%rdx - 43086a: 0f 28 4e f8 movaps -0x8(%rsi),%xmm1 - 43086e: 72 07 jb 430877 <__memmove_ssse3+0xf27> - 430870: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 - 430877: 48 8d 52 c0 lea -0x40(%rdx),%rdx - 43087b: 41 ff e1 jmpq *%r9 - 43087e: 0f 0b ud2 - 430880: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) - 430887: 0f 28 56 e8 movaps -0x18(%rsi),%xmm2 - 43088b: 48 83 ea 40 sub $0x40,%rdx - 43088f: 0f 28 5e d8 movaps -0x28(%rsi),%xmm3 - 430893: 0f 28 66 c8 movaps -0x38(%rsi),%xmm4 - 430897: 0f 28 6e b8 movaps -0x48(%rsi),%xmm5 - 43089b: 48 8d 76 c0 lea -0x40(%rsi),%rsi - 43089f: 66 0f 3a 0f ca 08 palignr $0x8,%xmm2,%xmm1 - 4308a5: 66 0f 3a 0f d3 08 palignr $0x8,%xmm3,%xmm2 - 4308ab: 66 0f 3a 0f dc 08 palignr $0x8,%xmm4,%xmm3 - 4308b1: 66 0f 3a 0f e5 08 palignr $0x8,%xmm5,%xmm4 - 4308b7: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 4308bb: 0f 28 cd movaps %xmm5,%xmm1 - 4308be: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 4308c2: 48 8d 7f c0 lea -0x40(%rdi),%rdi - 4308c6: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) - 4308ca: 72 08 jb 4308d4 <__memmove_ssse3+0xf84> - 4308cc: 0f 29 27 movaps %xmm4,(%rdi) - 4308cf: 41 ff e1 jmpq *%r9 - 4308d2: 0f 0b ud2 - 4308d4: 0f 29 27 movaps %xmm4,(%rdi) - 4308d7: 48 8d 52 40 lea 0x40(%rdx),%rdx - 4308db: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 4308e0: 4c 8d 1d c9 2a 07 00 lea 0x72ac9(%rip),%r11 # 4a33b0 - 4308e7: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 4308eb: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 4308ef: ff e2 jmpq *%rdx - 4308f1: 0f 0b ud2 - 4308f3: 0f 1f 00 nopl (%rax) - 4308f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4308fd: 00 00 00 - 430900: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 - 430907: 48 39 ca cmp %rcx,%rdx - 43090a: 0f 28 4e f7 movaps -0x9(%rsi),%xmm1 - 43090e: 72 07 jb 430917 <__memmove_ssse3+0xfc7> - 430910: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 - 430917: 48 8d 52 c0 lea -0x40(%rdx),%rdx - 43091b: 41 ff e1 jmpq *%r9 - 43091e: 0f 0b ud2 - 430920: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) - 430927: 48 83 ea 40 sub $0x40,%rdx - 43092b: 0f 28 56 07 movaps 0x7(%rsi),%xmm2 - 43092f: 0f 28 5e 17 movaps 0x17(%rsi),%xmm3 - 430933: 0f 28 66 27 movaps 0x27(%rsi),%xmm4 - 430937: 0f 28 6e 37 movaps 0x37(%rsi),%xmm5 - 43093b: 66 0f 6f f5 movdqa %xmm5,%xmm6 - 43093f: 66 0f 3a 0f ec 09 palignr $0x9,%xmm4,%xmm5 - 430945: 48 8d 76 40 lea 0x40(%rsi),%rsi - 430949: 66 0f 3a 0f e3 09 palignr $0x9,%xmm3,%xmm4 - 43094f: 66 0f 3a 0f da 09 palignr $0x9,%xmm2,%xmm3 - 430955: 48 8d 7f 40 lea 0x40(%rdi),%rdi - 430959: 66 0f 3a 0f d1 09 palignr $0x9,%xmm1,%xmm2 - 43095f: 66 0f 6f ce movdqa %xmm6,%xmm1 - 430963: 66 0f 7f 57 c0 movdqa %xmm2,-0x40(%rdi) - 430968: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 43096c: 72 0d jb 43097b <__memmove_ssse3+0x102b> - 43096e: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) - 430972: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) - 430976: 41 ff e1 jmpq *%r9 - 430979: 0f 0b ud2 - 43097b: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) - 43097f: 48 8d 52 40 lea 0x40(%rdx),%rdx - 430983: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) - 430987: 48 01 d7 add %rdx,%rdi - 43098a: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 43098f: 48 01 d6 add %rdx,%rsi - 430992: 4c 8d 1d 17 2a 07 00 lea 0x72a17(%rip),%r11 # 4a33b0 - 430999: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 43099d: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 4309a1: ff e2 jmpq *%rdx - 4309a3: 0f 0b ud2 - 4309a5: 90 nop - 4309a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4309ad: 00 00 00 - 4309b0: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 - 4309b7: 48 39 ca cmp %rcx,%rdx - 4309ba: 0f 28 4e f7 movaps -0x9(%rsi),%xmm1 - 4309be: 72 07 jb 4309c7 <__memmove_ssse3+0x1077> - 4309c0: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 - 4309c7: 48 8d 52 c0 lea -0x40(%rdx),%rdx - 4309cb: 41 ff e1 jmpq *%r9 - 4309ce: 0f 0b ud2 - 4309d0: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) - 4309d7: 0f 28 56 e7 movaps -0x19(%rsi),%xmm2 - 4309db: 48 83 ea 40 sub $0x40,%rdx - 4309df: 0f 28 5e d7 movaps -0x29(%rsi),%xmm3 - 4309e3: 0f 28 66 c7 movaps -0x39(%rsi),%xmm4 - 4309e7: 0f 28 6e b7 movaps -0x49(%rsi),%xmm5 - 4309eb: 48 8d 76 c0 lea -0x40(%rsi),%rsi - 4309ef: 66 0f 3a 0f ca 09 palignr $0x9,%xmm2,%xmm1 - 4309f5: 66 0f 3a 0f d3 09 palignr $0x9,%xmm3,%xmm2 - 4309fb: 66 0f 3a 0f dc 09 palignr $0x9,%xmm4,%xmm3 - 430a01: 66 0f 3a 0f e5 09 palignr $0x9,%xmm5,%xmm4 - 430a07: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 430a0b: 0f 28 cd movaps %xmm5,%xmm1 - 430a0e: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 430a12: 48 8d 7f c0 lea -0x40(%rdi),%rdi - 430a16: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) - 430a1a: 72 08 jb 430a24 <__memmove_ssse3+0x10d4> - 430a1c: 0f 29 27 movaps %xmm4,(%rdi) - 430a1f: 41 ff e1 jmpq *%r9 - 430a22: 0f 0b ud2 - 430a24: 0f 29 27 movaps %xmm4,(%rdi) - 430a27: 48 8d 52 40 lea 0x40(%rdx),%rdx - 430a2b: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 430a30: 4c 8d 1d 79 29 07 00 lea 0x72979(%rip),%r11 # 4a33b0 - 430a37: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 430a3b: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 430a3f: ff e2 jmpq *%rdx - 430a41: 0f 0b ud2 - 430a43: 0f 1f 00 nopl (%rax) - 430a46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 430a4d: 00 00 00 - 430a50: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 - 430a57: 48 39 ca cmp %rcx,%rdx - 430a5a: 0f 28 4e f6 movaps -0xa(%rsi),%xmm1 - 430a5e: 72 07 jb 430a67 <__memmove_ssse3+0x1117> - 430a60: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 - 430a67: 48 8d 52 c0 lea -0x40(%rdx),%rdx - 430a6b: 41 ff e1 jmpq *%r9 - 430a6e: 0f 0b ud2 - 430a70: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) - 430a77: 48 83 ea 40 sub $0x40,%rdx - 430a7b: 0f 28 56 06 movaps 0x6(%rsi),%xmm2 - 430a7f: 0f 28 5e 16 movaps 0x16(%rsi),%xmm3 - 430a83: 0f 28 66 26 movaps 0x26(%rsi),%xmm4 - 430a87: 0f 28 6e 36 movaps 0x36(%rsi),%xmm5 - 430a8b: 66 0f 6f f5 movdqa %xmm5,%xmm6 - 430a8f: 66 0f 3a 0f ec 0a palignr $0xa,%xmm4,%xmm5 - 430a95: 48 8d 76 40 lea 0x40(%rsi),%rsi - 430a99: 66 0f 3a 0f e3 0a palignr $0xa,%xmm3,%xmm4 - 430a9f: 66 0f 3a 0f da 0a palignr $0xa,%xmm2,%xmm3 - 430aa5: 48 8d 7f 40 lea 0x40(%rdi),%rdi - 430aa9: 66 0f 3a 0f d1 0a palignr $0xa,%xmm1,%xmm2 - 430aaf: 66 0f 6f ce movdqa %xmm6,%xmm1 - 430ab3: 66 0f 7f 57 c0 movdqa %xmm2,-0x40(%rdi) - 430ab8: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 430abc: 72 0d jb 430acb <__memmove_ssse3+0x117b> - 430abe: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) - 430ac2: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) - 430ac6: 41 ff e1 jmpq *%r9 - 430ac9: 0f 0b ud2 - 430acb: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) - 430acf: 48 8d 52 40 lea 0x40(%rdx),%rdx - 430ad3: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) - 430ad7: 48 01 d7 add %rdx,%rdi - 430ada: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 430adf: 48 01 d6 add %rdx,%rsi - 430ae2: 4c 8d 1d c7 28 07 00 lea 0x728c7(%rip),%r11 # 4a33b0 - 430ae9: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 430aed: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 430af1: ff e2 jmpq *%rdx - 430af3: 0f 0b ud2 - 430af5: 90 nop - 430af6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 430afd: 00 00 00 - 430b00: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 - 430b07: 48 39 ca cmp %rcx,%rdx - 430b0a: 0f 28 4e f6 movaps -0xa(%rsi),%xmm1 - 430b0e: 72 07 jb 430b17 <__memmove_ssse3+0x11c7> - 430b10: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 - 430b17: 48 8d 52 c0 lea -0x40(%rdx),%rdx - 430b1b: 41 ff e1 jmpq *%r9 - 430b1e: 0f 0b ud2 - 430b20: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) - 430b27: 0f 28 56 e6 movaps -0x1a(%rsi),%xmm2 - 430b2b: 48 83 ea 40 sub $0x40,%rdx - 430b2f: 0f 28 5e d6 movaps -0x2a(%rsi),%xmm3 - 430b33: 0f 28 66 c6 movaps -0x3a(%rsi),%xmm4 - 430b37: 0f 28 6e b6 movaps -0x4a(%rsi),%xmm5 - 430b3b: 48 8d 76 c0 lea -0x40(%rsi),%rsi - 430b3f: 66 0f 3a 0f ca 0a palignr $0xa,%xmm2,%xmm1 - 430b45: 66 0f 3a 0f d3 0a palignr $0xa,%xmm3,%xmm2 - 430b4b: 66 0f 3a 0f dc 0a palignr $0xa,%xmm4,%xmm3 - 430b51: 66 0f 3a 0f e5 0a palignr $0xa,%xmm5,%xmm4 - 430b57: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 430b5b: 0f 28 cd movaps %xmm5,%xmm1 - 430b5e: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 430b62: 48 8d 7f c0 lea -0x40(%rdi),%rdi - 430b66: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) - 430b6a: 72 08 jb 430b74 <__memmove_ssse3+0x1224> - 430b6c: 0f 29 27 movaps %xmm4,(%rdi) - 430b6f: 41 ff e1 jmpq *%r9 - 430b72: 0f 0b ud2 - 430b74: 0f 29 27 movaps %xmm4,(%rdi) - 430b77: 48 8d 52 40 lea 0x40(%rdx),%rdx - 430b7b: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 430b80: 4c 8d 1d 29 28 07 00 lea 0x72829(%rip),%r11 # 4a33b0 - 430b87: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 430b8b: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 430b8f: ff e2 jmpq *%rdx - 430b91: 0f 0b ud2 - 430b93: 0f 1f 00 nopl (%rax) - 430b96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 430b9d: 00 00 00 - 430ba0: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 - 430ba7: 48 39 ca cmp %rcx,%rdx - 430baa: 0f 28 4e f5 movaps -0xb(%rsi),%xmm1 - 430bae: 72 07 jb 430bb7 <__memmove_ssse3+0x1267> - 430bb0: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 - 430bb7: 48 8d 52 c0 lea -0x40(%rdx),%rdx - 430bbb: 41 ff e1 jmpq *%r9 - 430bbe: 0f 0b ud2 - 430bc0: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) - 430bc7: 48 83 ea 40 sub $0x40,%rdx - 430bcb: 0f 28 56 05 movaps 0x5(%rsi),%xmm2 - 430bcf: 0f 28 5e 15 movaps 0x15(%rsi),%xmm3 - 430bd3: 0f 28 66 25 movaps 0x25(%rsi),%xmm4 - 430bd7: 0f 28 6e 35 movaps 0x35(%rsi),%xmm5 - 430bdb: 66 0f 6f f5 movdqa %xmm5,%xmm6 - 430bdf: 66 0f 3a 0f ec 0b palignr $0xb,%xmm4,%xmm5 - 430be5: 48 8d 76 40 lea 0x40(%rsi),%rsi - 430be9: 66 0f 3a 0f e3 0b palignr $0xb,%xmm3,%xmm4 - 430bef: 66 0f 3a 0f da 0b palignr $0xb,%xmm2,%xmm3 - 430bf5: 48 8d 7f 40 lea 0x40(%rdi),%rdi - 430bf9: 66 0f 3a 0f d1 0b palignr $0xb,%xmm1,%xmm2 - 430bff: 66 0f 6f ce movdqa %xmm6,%xmm1 - 430c03: 66 0f 7f 57 c0 movdqa %xmm2,-0x40(%rdi) - 430c08: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 430c0c: 72 0d jb 430c1b <__memmove_ssse3+0x12cb> - 430c0e: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) - 430c12: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) - 430c16: 41 ff e1 jmpq *%r9 - 430c19: 0f 0b ud2 - 430c1b: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) - 430c1f: 48 8d 52 40 lea 0x40(%rdx),%rdx - 430c23: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) - 430c27: 48 01 d7 add %rdx,%rdi - 430c2a: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 430c2f: 48 01 d6 add %rdx,%rsi - 430c32: 4c 8d 1d 77 27 07 00 lea 0x72777(%rip),%r11 # 4a33b0 - 430c39: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 430c3d: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 430c41: ff e2 jmpq *%rdx - 430c43: 0f 0b ud2 - 430c45: 90 nop - 430c46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 430c4d: 00 00 00 - 430c50: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 - 430c57: 48 39 ca cmp %rcx,%rdx - 430c5a: 0f 28 4e f5 movaps -0xb(%rsi),%xmm1 - 430c5e: 72 07 jb 430c67 <__memmove_ssse3+0x1317> - 430c60: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 - 430c67: 48 8d 52 c0 lea -0x40(%rdx),%rdx - 430c6b: 41 ff e1 jmpq *%r9 - 430c6e: 0f 0b ud2 - 430c70: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) - 430c77: 0f 28 56 e5 movaps -0x1b(%rsi),%xmm2 - 430c7b: 48 83 ea 40 sub $0x40,%rdx - 430c7f: 0f 28 5e d5 movaps -0x2b(%rsi),%xmm3 - 430c83: 0f 28 66 c5 movaps -0x3b(%rsi),%xmm4 - 430c87: 0f 28 6e b5 movaps -0x4b(%rsi),%xmm5 - 430c8b: 48 8d 76 c0 lea -0x40(%rsi),%rsi - 430c8f: 66 0f 3a 0f ca 0b palignr $0xb,%xmm2,%xmm1 - 430c95: 66 0f 3a 0f d3 0b palignr $0xb,%xmm3,%xmm2 - 430c9b: 66 0f 3a 0f dc 0b palignr $0xb,%xmm4,%xmm3 - 430ca1: 66 0f 3a 0f e5 0b palignr $0xb,%xmm5,%xmm4 - 430ca7: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 430cab: 0f 28 cd movaps %xmm5,%xmm1 - 430cae: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 430cb2: 48 8d 7f c0 lea -0x40(%rdi),%rdi - 430cb6: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) - 430cba: 72 08 jb 430cc4 <__memmove_ssse3+0x1374> - 430cbc: 0f 29 27 movaps %xmm4,(%rdi) - 430cbf: 41 ff e1 jmpq *%r9 - 430cc2: 0f 0b ud2 - 430cc4: 0f 29 27 movaps %xmm4,(%rdi) - 430cc7: 48 8d 52 40 lea 0x40(%rdx),%rdx - 430ccb: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 430cd0: 4c 8d 1d d9 26 07 00 lea 0x726d9(%rip),%r11 # 4a33b0 - 430cd7: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 430cdb: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 430cdf: ff e2 jmpq *%rdx - 430ce1: 0f 0b ud2 - 430ce3: 0f 1f 00 nopl (%rax) - 430ce6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 430ced: 00 00 00 - 430cf0: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 - 430cf7: 48 39 ca cmp %rcx,%rdx - 430cfa: 0f 28 4e f4 movaps -0xc(%rsi),%xmm1 - 430cfe: 72 07 jb 430d07 <__memmove_ssse3+0x13b7> - 430d00: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 - 430d07: 48 8d 52 c0 lea -0x40(%rdx),%rdx - 430d0b: 41 ff e1 jmpq *%r9 - 430d0e: 0f 0b ud2 - 430d10: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) - 430d17: 48 83 ea 40 sub $0x40,%rdx - 430d1b: 0f 28 56 04 movaps 0x4(%rsi),%xmm2 - 430d1f: 0f 28 5e 14 movaps 0x14(%rsi),%xmm3 - 430d23: 0f 28 66 24 movaps 0x24(%rsi),%xmm4 - 430d27: 0f 28 6e 34 movaps 0x34(%rsi),%xmm5 - 430d2b: 66 0f 6f f5 movdqa %xmm5,%xmm6 - 430d2f: 66 0f 3a 0f ec 0c palignr $0xc,%xmm4,%xmm5 - 430d35: 48 8d 76 40 lea 0x40(%rsi),%rsi - 430d39: 66 0f 3a 0f e3 0c palignr $0xc,%xmm3,%xmm4 - 430d3f: 66 0f 3a 0f da 0c palignr $0xc,%xmm2,%xmm3 - 430d45: 48 8d 7f 40 lea 0x40(%rdi),%rdi - 430d49: 66 0f 3a 0f d1 0c palignr $0xc,%xmm1,%xmm2 - 430d4f: 66 0f 6f ce movdqa %xmm6,%xmm1 - 430d53: 66 0f 7f 57 c0 movdqa %xmm2,-0x40(%rdi) - 430d58: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 430d5c: 72 0d jb 430d6b <__memmove_ssse3+0x141b> - 430d5e: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) - 430d62: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) - 430d66: 41 ff e1 jmpq *%r9 - 430d69: 0f 0b ud2 - 430d6b: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) - 430d6f: 48 8d 52 40 lea 0x40(%rdx),%rdx - 430d73: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) - 430d77: 48 01 d7 add %rdx,%rdi - 430d7a: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 430d7f: 48 01 d6 add %rdx,%rsi - 430d82: 4c 8d 1d 27 26 07 00 lea 0x72627(%rip),%r11 # 4a33b0 - 430d89: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 430d8d: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 430d91: ff e2 jmpq *%rdx - 430d93: 0f 0b ud2 - 430d95: 90 nop - 430d96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 430d9d: 00 00 00 - 430da0: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 - 430da7: 48 39 ca cmp %rcx,%rdx - 430daa: 0f 28 4e f4 movaps -0xc(%rsi),%xmm1 - 430dae: 72 07 jb 430db7 <__memmove_ssse3+0x1467> - 430db0: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 - 430db7: 48 8d 52 c0 lea -0x40(%rdx),%rdx - 430dbb: 41 ff e1 jmpq *%r9 - 430dbe: 0f 0b ud2 - 430dc0: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) - 430dc7: 0f 28 56 e4 movaps -0x1c(%rsi),%xmm2 - 430dcb: 48 83 ea 40 sub $0x40,%rdx - 430dcf: 0f 28 5e d4 movaps -0x2c(%rsi),%xmm3 - 430dd3: 0f 28 66 c4 movaps -0x3c(%rsi),%xmm4 - 430dd7: 0f 28 6e b4 movaps -0x4c(%rsi),%xmm5 - 430ddb: 48 8d 76 c0 lea -0x40(%rsi),%rsi - 430ddf: 66 0f 3a 0f ca 0c palignr $0xc,%xmm2,%xmm1 - 430de5: 66 0f 3a 0f d3 0c palignr $0xc,%xmm3,%xmm2 - 430deb: 66 0f 3a 0f dc 0c palignr $0xc,%xmm4,%xmm3 - 430df1: 66 0f 3a 0f e5 0c palignr $0xc,%xmm5,%xmm4 - 430df7: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 430dfb: 0f 28 cd movaps %xmm5,%xmm1 - 430dfe: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 430e02: 48 8d 7f c0 lea -0x40(%rdi),%rdi - 430e06: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) - 430e0a: 72 08 jb 430e14 <__memmove_ssse3+0x14c4> - 430e0c: 0f 29 27 movaps %xmm4,(%rdi) - 430e0f: 41 ff e1 jmpq *%r9 - 430e12: 0f 0b ud2 - 430e14: 0f 29 27 movaps %xmm4,(%rdi) - 430e17: 48 8d 52 40 lea 0x40(%rdx),%rdx - 430e1b: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 430e20: 4c 8d 1d 89 25 07 00 lea 0x72589(%rip),%r11 # 4a33b0 - 430e27: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 430e2b: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 430e2f: ff e2 jmpq *%rdx - 430e31: 0f 0b ud2 - 430e33: 0f 1f 00 nopl (%rax) - 430e36: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 430e3d: 00 00 00 - 430e40: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 - 430e47: 48 39 ca cmp %rcx,%rdx - 430e4a: 0f 28 4e f3 movaps -0xd(%rsi),%xmm1 - 430e4e: 72 07 jb 430e57 <__memmove_ssse3+0x1507> - 430e50: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 - 430e57: 48 8d 52 c0 lea -0x40(%rdx),%rdx - 430e5b: 41 ff e1 jmpq *%r9 - 430e5e: 0f 0b ud2 - 430e60: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) - 430e67: 48 83 ea 40 sub $0x40,%rdx - 430e6b: 0f 28 56 03 movaps 0x3(%rsi),%xmm2 - 430e6f: 0f 28 5e 13 movaps 0x13(%rsi),%xmm3 - 430e73: 0f 28 66 23 movaps 0x23(%rsi),%xmm4 - 430e77: 0f 28 6e 33 movaps 0x33(%rsi),%xmm5 - 430e7b: 66 0f 6f f5 movdqa %xmm5,%xmm6 - 430e7f: 66 0f 3a 0f ec 0d palignr $0xd,%xmm4,%xmm5 - 430e85: 48 8d 76 40 lea 0x40(%rsi),%rsi - 430e89: 66 0f 3a 0f e3 0d palignr $0xd,%xmm3,%xmm4 - 430e8f: 66 0f 3a 0f da 0d palignr $0xd,%xmm2,%xmm3 - 430e95: 48 8d 7f 40 lea 0x40(%rdi),%rdi - 430e99: 66 0f 3a 0f d1 0d palignr $0xd,%xmm1,%xmm2 - 430e9f: 66 0f 6f ce movdqa %xmm6,%xmm1 - 430ea3: 66 0f 7f 57 c0 movdqa %xmm2,-0x40(%rdi) - 430ea8: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 430eac: 72 0d jb 430ebb <__memmove_ssse3+0x156b> - 430eae: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) - 430eb2: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) - 430eb6: 41 ff e1 jmpq *%r9 - 430eb9: 0f 0b ud2 - 430ebb: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) - 430ebf: 48 8d 52 40 lea 0x40(%rdx),%rdx - 430ec3: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) - 430ec7: 48 01 d7 add %rdx,%rdi - 430eca: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 430ecf: 48 01 d6 add %rdx,%rsi - 430ed2: 4c 8d 1d d7 24 07 00 lea 0x724d7(%rip),%r11 # 4a33b0 - 430ed9: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 430edd: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 430ee1: ff e2 jmpq *%rdx - 430ee3: 0f 0b ud2 - 430ee5: 90 nop - 430ee6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 430eed: 00 00 00 - 430ef0: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 - 430ef7: 48 39 ca cmp %rcx,%rdx - 430efa: 0f 28 4e f3 movaps -0xd(%rsi),%xmm1 - 430efe: 72 07 jb 430f07 <__memmove_ssse3+0x15b7> - 430f00: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 - 430f07: 48 8d 52 c0 lea -0x40(%rdx),%rdx - 430f0b: 41 ff e1 jmpq *%r9 - 430f0e: 0f 0b ud2 - 430f10: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) - 430f17: 0f 28 56 e3 movaps -0x1d(%rsi),%xmm2 - 430f1b: 48 83 ea 40 sub $0x40,%rdx - 430f1f: 0f 28 5e d3 movaps -0x2d(%rsi),%xmm3 - 430f23: 0f 28 66 c3 movaps -0x3d(%rsi),%xmm4 - 430f27: 0f 28 6e b3 movaps -0x4d(%rsi),%xmm5 - 430f2b: 48 8d 76 c0 lea -0x40(%rsi),%rsi - 430f2f: 66 0f 3a 0f ca 0d palignr $0xd,%xmm2,%xmm1 - 430f35: 66 0f 3a 0f d3 0d palignr $0xd,%xmm3,%xmm2 - 430f3b: 66 0f 3a 0f dc 0d palignr $0xd,%xmm4,%xmm3 - 430f41: 66 0f 3a 0f e5 0d palignr $0xd,%xmm5,%xmm4 - 430f47: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 430f4b: 0f 28 cd movaps %xmm5,%xmm1 - 430f4e: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 430f52: 48 8d 7f c0 lea -0x40(%rdi),%rdi - 430f56: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) - 430f5a: 72 08 jb 430f64 <__memmove_ssse3+0x1614> - 430f5c: 0f 29 27 movaps %xmm4,(%rdi) - 430f5f: 41 ff e1 jmpq *%r9 - 430f62: 0f 0b ud2 - 430f64: 0f 29 27 movaps %xmm4,(%rdi) - 430f67: 48 8d 52 40 lea 0x40(%rdx),%rdx - 430f6b: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 430f70: 4c 8d 1d 39 24 07 00 lea 0x72439(%rip),%r11 # 4a33b0 - 430f77: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 430f7b: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 430f7f: ff e2 jmpq *%rdx - 430f81: 0f 0b ud2 - 430f83: 0f 1f 00 nopl (%rax) - 430f86: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 430f8d: 00 00 00 - 430f90: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 - 430f97: 48 39 ca cmp %rcx,%rdx - 430f9a: 0f 28 4e f2 movaps -0xe(%rsi),%xmm1 - 430f9e: 72 07 jb 430fa7 <__memmove_ssse3+0x1657> - 430fa0: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 - 430fa7: 48 8d 52 c0 lea -0x40(%rdx),%rdx - 430fab: 41 ff e1 jmpq *%r9 - 430fae: 0f 0b ud2 - 430fb0: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) - 430fb7: 48 83 ea 40 sub $0x40,%rdx - 430fbb: 0f 28 56 02 movaps 0x2(%rsi),%xmm2 - 430fbf: 0f 28 5e 12 movaps 0x12(%rsi),%xmm3 - 430fc3: 0f 28 66 22 movaps 0x22(%rsi),%xmm4 - 430fc7: 0f 28 6e 32 movaps 0x32(%rsi),%xmm5 - 430fcb: 66 0f 6f f5 movdqa %xmm5,%xmm6 - 430fcf: 66 0f 3a 0f ec 0e palignr $0xe,%xmm4,%xmm5 - 430fd5: 48 8d 76 40 lea 0x40(%rsi),%rsi - 430fd9: 66 0f 3a 0f e3 0e palignr $0xe,%xmm3,%xmm4 - 430fdf: 66 0f 3a 0f da 0e palignr $0xe,%xmm2,%xmm3 - 430fe5: 48 8d 7f 40 lea 0x40(%rdi),%rdi - 430fe9: 66 0f 3a 0f d1 0e palignr $0xe,%xmm1,%xmm2 - 430fef: 66 0f 6f ce movdqa %xmm6,%xmm1 - 430ff3: 66 0f 7f 57 c0 movdqa %xmm2,-0x40(%rdi) - 430ff8: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 430ffc: 72 0d jb 43100b <__memmove_ssse3+0x16bb> - 430ffe: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) - 431002: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) - 431006: 41 ff e1 jmpq *%r9 - 431009: 0f 0b ud2 - 43100b: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) - 43100f: 48 8d 52 40 lea 0x40(%rdx),%rdx - 431013: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) - 431017: 48 01 d7 add %rdx,%rdi - 43101a: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 43101f: 48 01 d6 add %rdx,%rsi - 431022: 4c 8d 1d 87 23 07 00 lea 0x72387(%rip),%r11 # 4a33b0 - 431029: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 43102d: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 431031: ff e2 jmpq *%rdx - 431033: 0f 0b ud2 - 431035: 90 nop - 431036: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43103d: 00 00 00 - 431040: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 - 431047: 48 39 ca cmp %rcx,%rdx - 43104a: 0f 28 4e f2 movaps -0xe(%rsi),%xmm1 - 43104e: 72 07 jb 431057 <__memmove_ssse3+0x1707> - 431050: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 - 431057: 48 8d 52 c0 lea -0x40(%rdx),%rdx - 43105b: 41 ff e1 jmpq *%r9 - 43105e: 0f 0b ud2 - 431060: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) - 431067: 0f 28 56 e2 movaps -0x1e(%rsi),%xmm2 - 43106b: 48 83 ea 40 sub $0x40,%rdx - 43106f: 0f 28 5e d2 movaps -0x2e(%rsi),%xmm3 - 431073: 0f 28 66 c2 movaps -0x3e(%rsi),%xmm4 - 431077: 0f 28 6e b2 movaps -0x4e(%rsi),%xmm5 - 43107b: 48 8d 76 c0 lea -0x40(%rsi),%rsi - 43107f: 66 0f 3a 0f ca 0e palignr $0xe,%xmm2,%xmm1 - 431085: 66 0f 3a 0f d3 0e palignr $0xe,%xmm3,%xmm2 - 43108b: 66 0f 3a 0f dc 0e palignr $0xe,%xmm4,%xmm3 - 431091: 66 0f 3a 0f e5 0e palignr $0xe,%xmm5,%xmm4 - 431097: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 43109b: 0f 28 cd movaps %xmm5,%xmm1 - 43109e: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 4310a2: 48 8d 7f c0 lea -0x40(%rdi),%rdi - 4310a6: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) - 4310aa: 72 08 jb 4310b4 <__memmove_ssse3+0x1764> - 4310ac: 0f 29 27 movaps %xmm4,(%rdi) - 4310af: 41 ff e1 jmpq *%r9 - 4310b2: 0f 0b ud2 - 4310b4: 0f 29 27 movaps %xmm4,(%rdi) - 4310b7: 48 8d 52 40 lea 0x40(%rdx),%rdx - 4310bb: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 4310c0: 4c 8d 1d e9 22 07 00 lea 0x722e9(%rip),%r11 # 4a33b0 - 4310c7: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 4310cb: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 4310cf: ff e2 jmpq *%rdx - 4310d1: 0f 0b ud2 - 4310d3: 0f 1f 00 nopl (%rax) - 4310d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4310dd: 00 00 00 - 4310e0: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 - 4310e7: 48 39 ca cmp %rcx,%rdx - 4310ea: 0f 28 4e f1 movaps -0xf(%rsi),%xmm1 - 4310ee: 72 07 jb 4310f7 <__memmove_ssse3+0x17a7> - 4310f0: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 - 4310f7: 48 8d 52 c0 lea -0x40(%rdx),%rdx - 4310fb: 41 ff e1 jmpq *%r9 - 4310fe: 0f 0b ud2 - 431100: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) - 431107: 48 83 ea 40 sub $0x40,%rdx - 43110b: 0f 28 56 01 movaps 0x1(%rsi),%xmm2 - 43110f: 0f 28 5e 11 movaps 0x11(%rsi),%xmm3 - 431113: 0f 28 66 21 movaps 0x21(%rsi),%xmm4 - 431117: 0f 28 6e 31 movaps 0x31(%rsi),%xmm5 - 43111b: 66 0f 6f f5 movdqa %xmm5,%xmm6 - 43111f: 66 0f 3a 0f ec 0f palignr $0xf,%xmm4,%xmm5 - 431125: 48 8d 76 40 lea 0x40(%rsi),%rsi - 431129: 66 0f 3a 0f e3 0f palignr $0xf,%xmm3,%xmm4 - 43112f: 66 0f 3a 0f da 0f palignr $0xf,%xmm2,%xmm3 - 431135: 48 8d 7f 40 lea 0x40(%rdi),%rdi - 431139: 66 0f 3a 0f d1 0f palignr $0xf,%xmm1,%xmm2 - 43113f: 66 0f 6f ce movdqa %xmm6,%xmm1 - 431143: 66 0f 7f 57 c0 movdqa %xmm2,-0x40(%rdi) - 431148: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 43114c: 72 0d jb 43115b <__memmove_ssse3+0x180b> - 43114e: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) - 431152: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) - 431156: 41 ff e1 jmpq *%r9 - 431159: 0f 0b ud2 - 43115b: 0f 29 67 e0 movaps %xmm4,-0x20(%rdi) - 43115f: 48 8d 52 40 lea 0x40(%rdx),%rdx - 431163: 0f 29 6f f0 movaps %xmm5,-0x10(%rdi) - 431167: 48 01 d7 add %rdx,%rdi - 43116a: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 43116f: 48 01 d6 add %rdx,%rsi - 431172: 4c 8d 1d 37 22 07 00 lea 0x72237(%rip),%r11 # 4a33b0 - 431179: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 43117d: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 431181: ff e2 jmpq *%rdx - 431183: 0f 0b ud2 - 431185: 90 nop - 431186: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43118d: 00 00 00 - 431190: 4d 8d 89 27 00 00 00 lea 0x27(%r9),%r9 - 431197: 48 39 ca cmp %rcx,%rdx - 43119a: 0f 28 4e f1 movaps -0xf(%rsi),%xmm1 - 43119e: 72 07 jb 4311a7 <__memmove_ssse3+0x1857> - 4311a0: 4d 8d 89 f9 ff ff ff lea -0x7(%r9),%r9 - 4311a7: 48 8d 52 c0 lea -0x40(%rdx),%rdx - 4311ab: 41 ff e1 jmpq *%r9 - 4311ae: 0f 0b ud2 - 4311b0: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) - 4311b7: 0f 28 56 e1 movaps -0x1f(%rsi),%xmm2 - 4311bb: 48 83 ea 40 sub $0x40,%rdx - 4311bf: 0f 28 5e d1 movaps -0x2f(%rsi),%xmm3 - 4311c3: 0f 28 66 c1 movaps -0x3f(%rsi),%xmm4 - 4311c7: 0f 28 6e b1 movaps -0x4f(%rsi),%xmm5 - 4311cb: 48 8d 76 c0 lea -0x40(%rsi),%rsi - 4311cf: 66 0f 3a 0f ca 0f palignr $0xf,%xmm2,%xmm1 - 4311d5: 66 0f 3a 0f d3 0f palignr $0xf,%xmm3,%xmm2 - 4311db: 66 0f 3a 0f dc 0f palignr $0xf,%xmm4,%xmm3 - 4311e1: 66 0f 3a 0f e5 0f palignr $0xf,%xmm5,%xmm4 - 4311e7: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 4311eb: 0f 28 cd movaps %xmm5,%xmm1 - 4311ee: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 4311f2: 48 8d 7f c0 lea -0x40(%rdi),%rdi - 4311f6: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) - 4311fa: 72 08 jb 431204 <__memmove_ssse3+0x18b4> - 4311fc: 0f 29 27 movaps %xmm4,(%rdi) - 4311ff: 41 ff e1 jmpq *%r9 - 431202: 0f 0b ud2 - 431204: 0f 29 27 movaps %xmm4,(%rdi) - 431207: 48 8d 52 40 lea 0x40(%rdx),%rdx - 43120b: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 431210: 4c 8d 1d 99 21 07 00 lea 0x72199(%rip),%r11 # 4a33b0 - 431217: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 43121b: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 43121f: ff e2 jmpq *%rdx - 431221: 0f 0b ud2 - 431223: 0f 1f 00 nopl (%rax) - 431226: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43122d: 00 00 00 - 431230: f3 0f 6f 46 b8 movdqu -0x48(%rsi),%xmm0 - 431235: f3 0f 6f 4e c8 movdqu -0x38(%rsi),%xmm1 - 43123a: 4c 8b 46 d8 mov -0x28(%rsi),%r8 - 43123e: 4c 8b 4e e0 mov -0x20(%rsi),%r9 - 431242: 4c 8b 56 e8 mov -0x18(%rsi),%r10 - 431246: 4c 8b 5e f0 mov -0x10(%rsi),%r11 - 43124a: 48 8b 4e f8 mov -0x8(%rsi),%rcx - 43124e: f3 0f 7f 47 b8 movdqu %xmm0,-0x48(%rdi) - 431253: f3 0f 7f 4f c8 movdqu %xmm1,-0x38(%rdi) - 431258: 4c 89 47 d8 mov %r8,-0x28(%rdi) - 43125c: 4c 89 4f e0 mov %r9,-0x20(%rdi) - 431260: 4c 89 57 e8 mov %r10,-0x18(%rdi) - 431264: 4c 89 5f f0 mov %r11,-0x10(%rdi) - 431268: 48 89 4f f8 mov %rcx,-0x8(%rdi) - 43126c: c3 retq - 43126d: 0f 1f 00 nopl (%rax) - 431270: f3 0f 6f 46 c0 movdqu -0x40(%rsi),%xmm0 - 431275: 48 8b 4e d0 mov -0x30(%rsi),%rcx - 431279: 4c 8b 46 d8 mov -0x28(%rsi),%r8 - 43127d: 4c 8b 4e e0 mov -0x20(%rsi),%r9 - 431281: 4c 8b 56 e8 mov -0x18(%rsi),%r10 - 431285: 4c 8b 5e f0 mov -0x10(%rsi),%r11 - 431289: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 43128d: f3 0f 7f 47 c0 movdqu %xmm0,-0x40(%rdi) - 431292: 48 89 4f d0 mov %rcx,-0x30(%rdi) - 431296: 4c 89 47 d8 mov %r8,-0x28(%rdi) - 43129a: 4c 89 4f e0 mov %r9,-0x20(%rdi) - 43129e: 4c 89 57 e8 mov %r10,-0x18(%rdi) - 4312a2: 4c 89 5f f0 mov %r11,-0x10(%rdi) - 4312a6: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 4312aa: c3 retq - 4312ab: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4312b0: f3 0f 6f 46 c8 movdqu -0x38(%rsi),%xmm0 - 4312b5: 4c 8b 46 d8 mov -0x28(%rsi),%r8 - 4312b9: 4c 8b 4e e0 mov -0x20(%rsi),%r9 - 4312bd: 4c 8b 56 e8 mov -0x18(%rsi),%r10 - 4312c1: 4c 8b 5e f0 mov -0x10(%rsi),%r11 - 4312c5: 48 8b 4e f8 mov -0x8(%rsi),%rcx - 4312c9: f3 0f 7f 47 c8 movdqu %xmm0,-0x38(%rdi) - 4312ce: 4c 89 47 d8 mov %r8,-0x28(%rdi) - 4312d2: 4c 89 4f e0 mov %r9,-0x20(%rdi) - 4312d6: 4c 89 57 e8 mov %r10,-0x18(%rdi) - 4312da: 4c 89 5f f0 mov %r11,-0x10(%rdi) - 4312de: 48 89 4f f8 mov %rcx,-0x8(%rdi) - 4312e2: c3 retq - 4312e3: 0f 1f 00 nopl (%rax) - 4312e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4312ed: 00 00 00 - 4312f0: 48 8b 4e d0 mov -0x30(%rsi),%rcx - 4312f4: 4c 8b 46 d8 mov -0x28(%rsi),%r8 - 4312f8: 4c 8b 4e e0 mov -0x20(%rsi),%r9 - 4312fc: 4c 8b 56 e8 mov -0x18(%rsi),%r10 - 431300: 4c 8b 5e f0 mov -0x10(%rsi),%r11 - 431304: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 431308: 48 89 4f d0 mov %rcx,-0x30(%rdi) - 43130c: 4c 89 47 d8 mov %r8,-0x28(%rdi) - 431310: 4c 89 4f e0 mov %r9,-0x20(%rdi) - 431314: 4c 89 57 e8 mov %r10,-0x18(%rdi) - 431318: 4c 89 5f f0 mov %r11,-0x10(%rdi) - 43131c: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 431320: c3 retq - 431321: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 431326: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43132d: 00 00 00 - 431330: 4c 8b 46 d8 mov -0x28(%rsi),%r8 - 431334: 4c 8b 4e e0 mov -0x20(%rsi),%r9 - 431338: 4c 8b 56 e8 mov -0x18(%rsi),%r10 - 43133c: 4c 8b 5e f0 mov -0x10(%rsi),%r11 - 431340: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 431344: 4c 89 47 d8 mov %r8,-0x28(%rdi) - 431348: 4c 89 4f e0 mov %r9,-0x20(%rdi) - 43134c: 4c 89 57 e8 mov %r10,-0x18(%rdi) - 431350: 4c 89 5f f0 mov %r11,-0x10(%rdi) - 431354: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 431358: c3 retq - 431359: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 431360: 4c 8b 4e e0 mov -0x20(%rsi),%r9 - 431364: 4c 8b 56 e8 mov -0x18(%rsi),%r10 - 431368: 4c 8b 5e f0 mov -0x10(%rsi),%r11 - 43136c: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 431370: 4c 89 4f e0 mov %r9,-0x20(%rdi) - 431374: 4c 89 57 e8 mov %r10,-0x18(%rdi) - 431378: 4c 89 5f f0 mov %r11,-0x10(%rdi) - 43137c: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 431380: c3 retq - 431381: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 431386: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43138d: 00 00 00 - 431390: 4c 8b 56 e8 mov -0x18(%rsi),%r10 - 431394: 4c 8b 5e f0 mov -0x10(%rsi),%r11 - 431398: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 43139c: 4c 89 57 e8 mov %r10,-0x18(%rdi) - 4313a0: 4c 89 5f f0 mov %r11,-0x10(%rdi) - 4313a4: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 4313a8: c3 retq - 4313a9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4313b0: 4c 8b 5e f0 mov -0x10(%rsi),%r11 - 4313b4: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 4313b8: 4c 89 5f f0 mov %r11,-0x10(%rdi) - 4313bc: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 4313c0: c3 retq - 4313c1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4313c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4313cd: 00 00 00 - 4313d0: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 4313d4: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 4313d8: c3 retq - 4313d9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4313e0: f3 0f 6f 46 b7 movdqu -0x49(%rsi),%xmm0 - 4313e5: f3 0f 6f 4e c7 movdqu -0x39(%rsi),%xmm1 - 4313ea: 48 8b 4e d7 mov -0x29(%rsi),%rcx - 4313ee: 4c 8b 4e df mov -0x21(%rsi),%r9 - 4313f2: 4c 8b 56 e7 mov -0x19(%rsi),%r10 - 4313f6: 4c 8b 5e ef mov -0x11(%rsi),%r11 - 4313fa: 4c 8b 46 f7 mov -0x9(%rsi),%r8 - 4313fe: 8b 56 fc mov -0x4(%rsi),%edx - 431401: f3 0f 7f 47 b7 movdqu %xmm0,-0x49(%rdi) - 431406: f3 0f 7f 4f c7 movdqu %xmm1,-0x39(%rdi) - 43140b: 48 89 4f d7 mov %rcx,-0x29(%rdi) - 43140f: 4c 89 4f df mov %r9,-0x21(%rdi) - 431413: 4c 89 57 e7 mov %r10,-0x19(%rdi) - 431417: 4c 89 5f ef mov %r11,-0x11(%rdi) - 43141b: 4c 89 47 f7 mov %r8,-0x9(%rdi) - 43141f: 89 57 fc mov %edx,-0x4(%rdi) - 431422: c3 retq - 431423: 0f 1f 00 nopl (%rax) - 431426: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43142d: 00 00 00 - 431430: f3 0f 6f 46 bf movdqu -0x41(%rsi),%xmm0 - 431435: f3 0f 6f 4e cf movdqu -0x31(%rsi),%xmm1 - 43143a: 4c 8b 4e df mov -0x21(%rsi),%r9 - 43143e: 4c 8b 56 e7 mov -0x19(%rsi),%r10 - 431442: 4c 8b 5e ef mov -0x11(%rsi),%r11 - 431446: 48 8b 4e f7 mov -0x9(%rsi),%rcx - 43144a: 8b 56 fc mov -0x4(%rsi),%edx - 43144d: f3 0f 7f 47 bf movdqu %xmm0,-0x41(%rdi) - 431452: f3 0f 7f 4f cf movdqu %xmm1,-0x31(%rdi) - 431457: 4c 89 4f df mov %r9,-0x21(%rdi) - 43145b: 4c 89 57 e7 mov %r10,-0x19(%rdi) - 43145f: 4c 89 5f ef mov %r11,-0x11(%rdi) - 431463: 48 89 4f f7 mov %rcx,-0x9(%rdi) - 431467: 89 57 fc mov %edx,-0x4(%rdi) - 43146a: c3 retq - 43146b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 431470: f3 0f 6f 46 c7 movdqu -0x39(%rsi),%xmm0 - 431475: 4c 8b 46 d7 mov -0x29(%rsi),%r8 - 431479: 4c 8b 4e df mov -0x21(%rsi),%r9 - 43147d: 4c 8b 56 e7 mov -0x19(%rsi),%r10 - 431481: 4c 8b 5e ef mov -0x11(%rsi),%r11 - 431485: 48 8b 4e f7 mov -0x9(%rsi),%rcx - 431489: 8b 56 fc mov -0x4(%rsi),%edx - 43148c: f3 0f 7f 47 c7 movdqu %xmm0,-0x39(%rdi) - 431491: 4c 89 47 d7 mov %r8,-0x29(%rdi) - 431495: 4c 89 4f df mov %r9,-0x21(%rdi) - 431499: 4c 89 57 e7 mov %r10,-0x19(%rdi) - 43149d: 4c 89 5f ef mov %r11,-0x11(%rdi) - 4314a1: 48 89 4f f7 mov %rcx,-0x9(%rdi) - 4314a5: 89 57 fc mov %edx,-0x4(%rdi) - 4314a8: c3 retq - 4314a9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4314b0: f3 0f 6f 46 cf movdqu -0x31(%rsi),%xmm0 - 4314b5: 4c 8b 4e df mov -0x21(%rsi),%r9 - 4314b9: 4c 8b 56 e7 mov -0x19(%rsi),%r10 - 4314bd: 4c 8b 5e ef mov -0x11(%rsi),%r11 - 4314c1: 48 8b 4e f7 mov -0x9(%rsi),%rcx - 4314c5: 8b 56 fc mov -0x4(%rsi),%edx - 4314c8: f3 0f 7f 47 cf movdqu %xmm0,-0x31(%rdi) - 4314cd: 4c 89 4f df mov %r9,-0x21(%rdi) - 4314d1: 4c 89 57 e7 mov %r10,-0x19(%rdi) - 4314d5: 4c 89 5f ef mov %r11,-0x11(%rdi) - 4314d9: 48 89 4f f7 mov %rcx,-0x9(%rdi) - 4314dd: 89 57 fc mov %edx,-0x4(%rdi) - 4314e0: c3 retq - 4314e1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4314e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4314ed: 00 00 00 - 4314f0: 4c 8b 46 d7 mov -0x29(%rsi),%r8 - 4314f4: 4c 8b 4e df mov -0x21(%rsi),%r9 - 4314f8: 4c 8b 56 e7 mov -0x19(%rsi),%r10 - 4314fc: 4c 8b 5e ef mov -0x11(%rsi),%r11 - 431500: 48 8b 4e f7 mov -0x9(%rsi),%rcx - 431504: 8a 56 ff mov -0x1(%rsi),%dl - 431507: 4c 89 47 d7 mov %r8,-0x29(%rdi) - 43150b: 4c 89 4f df mov %r9,-0x21(%rdi) - 43150f: 4c 89 57 e7 mov %r10,-0x19(%rdi) - 431513: 4c 89 5f ef mov %r11,-0x11(%rdi) - 431517: 48 89 4f f7 mov %rcx,-0x9(%rdi) - 43151b: 88 57 ff mov %dl,-0x1(%rdi) - 43151e: c3 retq - 43151f: 90 nop - 431520: 4c 8b 4e df mov -0x21(%rsi),%r9 - 431524: 4c 8b 56 e7 mov -0x19(%rsi),%r10 - 431528: 4c 8b 5e ef mov -0x11(%rsi),%r11 - 43152c: 48 8b 4e f7 mov -0x9(%rsi),%rcx - 431530: 8a 56 ff mov -0x1(%rsi),%dl - 431533: 4c 89 4f df mov %r9,-0x21(%rdi) - 431537: 4c 89 57 e7 mov %r10,-0x19(%rdi) - 43153b: 4c 89 5f ef mov %r11,-0x11(%rdi) - 43153f: 48 89 4f f7 mov %rcx,-0x9(%rdi) - 431543: 88 57 ff mov %dl,-0x1(%rdi) - 431546: c3 retq - 431547: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 43154e: 00 00 - 431550: 4c 8b 56 e7 mov -0x19(%rsi),%r10 - 431554: 4c 8b 5e ef mov -0x11(%rsi),%r11 - 431558: 48 8b 4e f7 mov -0x9(%rsi),%rcx - 43155c: 8a 56 ff mov -0x1(%rsi),%dl - 43155f: 4c 89 57 e7 mov %r10,-0x19(%rdi) - 431563: 4c 89 5f ef mov %r11,-0x11(%rdi) - 431567: 48 89 4f f7 mov %rcx,-0x9(%rdi) - 43156b: 88 57 ff mov %dl,-0x1(%rdi) - 43156e: c3 retq - 43156f: 90 nop - 431570: 4c 8b 5e ef mov -0x11(%rsi),%r11 - 431574: 48 8b 4e f7 mov -0x9(%rsi),%rcx - 431578: 8b 56 fc mov -0x4(%rsi),%edx - 43157b: 4c 89 5f ef mov %r11,-0x11(%rdi) - 43157f: 48 89 4f f7 mov %rcx,-0x9(%rdi) - 431583: 89 57 fc mov %edx,-0x4(%rdi) - 431586: c3 retq - 431587: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 43158e: 00 00 - 431590: 48 8b 4e f7 mov -0x9(%rsi),%rcx - 431594: 8b 56 fc mov -0x4(%rsi),%edx - 431597: 48 89 4f f7 mov %rcx,-0x9(%rdi) - 43159b: 89 57 fc mov %edx,-0x4(%rdi) - 43159e: c3 retq - 43159f: 90 nop - 4315a0: 8a 56 ff mov -0x1(%rsi),%dl - 4315a3: 88 57 ff mov %dl,-0x1(%rdi) - 4315a6: c3 retq - 4315a7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 4315ae: 00 00 - 4315b0: f3 0f 6f 46 b6 movdqu -0x4a(%rsi),%xmm0 - 4315b5: f3 0f 6f 4e c6 movdqu -0x3a(%rsi),%xmm1 - 4315ba: 4c 8b 46 d6 mov -0x2a(%rsi),%r8 - 4315be: 4c 8b 4e de mov -0x22(%rsi),%r9 - 4315c2: 4c 8b 56 e6 mov -0x1a(%rsi),%r10 - 4315c6: 4c 8b 5e ee mov -0x12(%rsi),%r11 - 4315ca: 48 8b 4e f6 mov -0xa(%rsi),%rcx - 4315ce: 8b 56 fc mov -0x4(%rsi),%edx - 4315d1: f3 0f 7f 47 b6 movdqu %xmm0,-0x4a(%rdi) - 4315d6: f3 0f 7f 4f c6 movdqu %xmm1,-0x3a(%rdi) - 4315db: 4c 89 47 d6 mov %r8,-0x2a(%rdi) - 4315df: 4c 89 4f de mov %r9,-0x22(%rdi) - 4315e3: 4c 89 57 e6 mov %r10,-0x1a(%rdi) - 4315e7: 4c 89 5f ee mov %r11,-0x12(%rdi) - 4315eb: 48 89 4f f6 mov %rcx,-0xa(%rdi) - 4315ef: 89 57 fc mov %edx,-0x4(%rdi) - 4315f2: c3 retq - 4315f3: 0f 1f 00 nopl (%rax) - 4315f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4315fd: 00 00 00 - 431600: f3 0f 6f 46 be movdqu -0x42(%rsi),%xmm0 - 431605: f3 0f 6f 4e ce movdqu -0x32(%rsi),%xmm1 - 43160a: 4c 8b 46 d6 mov -0x2a(%rsi),%r8 - 43160e: 4c 8b 4e de mov -0x22(%rsi),%r9 - 431612: 4c 8b 56 e6 mov -0x1a(%rsi),%r10 - 431616: 4c 8b 5e ee mov -0x12(%rsi),%r11 - 43161a: 48 8b 4e f6 mov -0xa(%rsi),%rcx - 43161e: 8b 56 fc mov -0x4(%rsi),%edx - 431621: f3 0f 7f 47 be movdqu %xmm0,-0x42(%rdi) - 431626: f3 0f 7f 4f ce movdqu %xmm1,-0x32(%rdi) - 43162b: 4c 89 47 d6 mov %r8,-0x2a(%rdi) - 43162f: 4c 89 4f de mov %r9,-0x22(%rdi) - 431633: 4c 89 57 e6 mov %r10,-0x1a(%rdi) - 431637: 4c 89 5f ee mov %r11,-0x12(%rdi) - 43163b: 48 89 4f f6 mov %rcx,-0xa(%rdi) - 43163f: 89 57 fc mov %edx,-0x4(%rdi) - 431642: c3 retq - 431643: 0f 1f 00 nopl (%rax) - 431646: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43164d: 00 00 00 - 431650: f3 0f 6f 4e c6 movdqu -0x3a(%rsi),%xmm1 - 431655: 4c 8b 46 d6 mov -0x2a(%rsi),%r8 - 431659: 4c 8b 4e de mov -0x22(%rsi),%r9 - 43165d: 4c 8b 56 e6 mov -0x1a(%rsi),%r10 - 431661: 4c 8b 5e ee mov -0x12(%rsi),%r11 - 431665: 48 8b 4e f6 mov -0xa(%rsi),%rcx - 431669: 8b 56 fc mov -0x4(%rsi),%edx - 43166c: f3 0f 7f 4f c6 movdqu %xmm1,-0x3a(%rdi) - 431671: 4c 89 47 d6 mov %r8,-0x2a(%rdi) - 431675: 4c 89 4f de mov %r9,-0x22(%rdi) - 431679: 4c 89 57 e6 mov %r10,-0x1a(%rdi) - 43167d: 4c 89 5f ee mov %r11,-0x12(%rdi) - 431681: 48 89 4f f6 mov %rcx,-0xa(%rdi) - 431685: 89 57 fc mov %edx,-0x4(%rdi) - 431688: c3 retq - 431689: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 431690: f3 0f 6f 46 ce movdqu -0x32(%rsi),%xmm0 - 431695: 4c 8b 4e de mov -0x22(%rsi),%r9 - 431699: 4c 8b 56 e6 mov -0x1a(%rsi),%r10 - 43169d: 4c 8b 5e ee mov -0x12(%rsi),%r11 - 4316a1: 48 8b 4e f6 mov -0xa(%rsi),%rcx - 4316a5: 8b 56 fc mov -0x4(%rsi),%edx - 4316a8: f3 0f 7f 47 ce movdqu %xmm0,-0x32(%rdi) - 4316ad: 4c 89 4f de mov %r9,-0x22(%rdi) - 4316b1: 4c 89 57 e6 mov %r10,-0x1a(%rdi) - 4316b5: 4c 89 5f ee mov %r11,-0x12(%rdi) - 4316b9: 48 89 4f f6 mov %rcx,-0xa(%rdi) - 4316bd: 89 57 fc mov %edx,-0x4(%rdi) - 4316c0: c3 retq - 4316c1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4316c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4316cd: 00 00 00 - 4316d0: 4c 8b 46 d6 mov -0x2a(%rsi),%r8 - 4316d4: 4c 8b 4e de mov -0x22(%rsi),%r9 - 4316d8: 4c 8b 56 e6 mov -0x1a(%rsi),%r10 - 4316dc: 4c 8b 5e ee mov -0x12(%rsi),%r11 - 4316e0: 48 8b 4e f6 mov -0xa(%rsi),%rcx - 4316e4: 8b 56 fc mov -0x4(%rsi),%edx - 4316e7: 4c 89 47 d6 mov %r8,-0x2a(%rdi) - 4316eb: 4c 89 4f de mov %r9,-0x22(%rdi) - 4316ef: 4c 89 57 e6 mov %r10,-0x1a(%rdi) - 4316f3: 4c 89 5f ee mov %r11,-0x12(%rdi) - 4316f7: 48 89 4f f6 mov %rcx,-0xa(%rdi) - 4316fb: 89 57 fc mov %edx,-0x4(%rdi) - 4316fe: c3 retq - 4316ff: 90 nop - 431700: 4c 8b 4e de mov -0x22(%rsi),%r9 - 431704: 4c 8b 56 e6 mov -0x1a(%rsi),%r10 - 431708: 4c 8b 5e ee mov -0x12(%rsi),%r11 - 43170c: 48 8b 4e f6 mov -0xa(%rsi),%rcx - 431710: 8b 56 fc mov -0x4(%rsi),%edx - 431713: 4c 89 4f de mov %r9,-0x22(%rdi) - 431717: 4c 89 57 e6 mov %r10,-0x1a(%rdi) - 43171b: 4c 89 5f ee mov %r11,-0x12(%rdi) - 43171f: 48 89 4f f6 mov %rcx,-0xa(%rdi) - 431723: 89 57 fc mov %edx,-0x4(%rdi) - 431726: c3 retq - 431727: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 43172e: 00 00 - 431730: 4c 8b 56 e6 mov -0x1a(%rsi),%r10 - 431734: 4c 8b 5e ee mov -0x12(%rsi),%r11 - 431738: 48 8b 4e f6 mov -0xa(%rsi),%rcx - 43173c: 8b 56 fc mov -0x4(%rsi),%edx - 43173f: 4c 89 57 e6 mov %r10,-0x1a(%rdi) - 431743: 4c 89 5f ee mov %r11,-0x12(%rdi) - 431747: 48 89 4f f6 mov %rcx,-0xa(%rdi) - 43174b: 89 57 fc mov %edx,-0x4(%rdi) - 43174e: c3 retq - 43174f: 90 nop - 431750: 4c 8b 5e ee mov -0x12(%rsi),%r11 - 431754: 48 8b 4e f6 mov -0xa(%rsi),%rcx - 431758: 8b 56 fc mov -0x4(%rsi),%edx - 43175b: 4c 89 5f ee mov %r11,-0x12(%rdi) - 43175f: 48 89 4f f6 mov %rcx,-0xa(%rdi) - 431763: 89 57 fc mov %edx,-0x4(%rdi) - 431766: c3 retq - 431767: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 43176e: 00 00 - 431770: 48 8b 4e f6 mov -0xa(%rsi),%rcx - 431774: 8b 56 fc mov -0x4(%rsi),%edx - 431777: 48 89 4f f6 mov %rcx,-0xa(%rdi) - 43177b: 89 57 fc mov %edx,-0x4(%rdi) - 43177e: c3 retq - 43177f: 90 nop - 431780: 66 8b 56 fe mov -0x2(%rsi),%dx - 431784: 66 89 57 fe mov %dx,-0x2(%rdi) - 431788: c3 retq - 431789: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 431790: f3 0f 6f 46 b5 movdqu -0x4b(%rsi),%xmm0 - 431795: f3 0f 6f 4e c5 movdqu -0x3b(%rsi),%xmm1 - 43179a: 4c 8b 46 d5 mov -0x2b(%rsi),%r8 - 43179e: 4c 8b 4e dd mov -0x23(%rsi),%r9 - 4317a2: 4c 8b 56 e5 mov -0x1b(%rsi),%r10 - 4317a6: 4c 8b 5e ed mov -0x13(%rsi),%r11 - 4317aa: 48 8b 4e f5 mov -0xb(%rsi),%rcx - 4317ae: 8b 56 fc mov -0x4(%rsi),%edx - 4317b1: f3 0f 7f 47 b5 movdqu %xmm0,-0x4b(%rdi) - 4317b6: f3 0f 7f 4f c5 movdqu %xmm1,-0x3b(%rdi) - 4317bb: 4c 89 47 d5 mov %r8,-0x2b(%rdi) - 4317bf: 4c 89 4f dd mov %r9,-0x23(%rdi) - 4317c3: 4c 89 57 e5 mov %r10,-0x1b(%rdi) - 4317c7: 4c 89 5f ed mov %r11,-0x13(%rdi) - 4317cb: 48 89 4f f5 mov %rcx,-0xb(%rdi) - 4317cf: 89 57 fc mov %edx,-0x4(%rdi) - 4317d2: c3 retq - 4317d3: 0f 1f 00 nopl (%rax) - 4317d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4317dd: 00 00 00 - 4317e0: f3 0f 6f 46 bd movdqu -0x43(%rsi),%xmm0 - 4317e5: f3 0f 6f 4e c5 movdqu -0x3b(%rsi),%xmm1 - 4317ea: 4c 8b 46 d5 mov -0x2b(%rsi),%r8 - 4317ee: 4c 8b 4e dd mov -0x23(%rsi),%r9 - 4317f2: 4c 8b 56 e5 mov -0x1b(%rsi),%r10 - 4317f6: 4c 8b 5e ed mov -0x13(%rsi),%r11 - 4317fa: 48 8b 4e f5 mov -0xb(%rsi),%rcx - 4317fe: 8b 56 fc mov -0x4(%rsi),%edx - 431801: f3 0f 7f 47 bd movdqu %xmm0,-0x43(%rdi) - 431806: f3 0f 7f 4f c5 movdqu %xmm1,-0x3b(%rdi) - 43180b: 4c 89 47 d5 mov %r8,-0x2b(%rdi) - 43180f: 4c 89 4f dd mov %r9,-0x23(%rdi) - 431813: 4c 89 57 e5 mov %r10,-0x1b(%rdi) - 431817: 4c 89 5f ed mov %r11,-0x13(%rdi) - 43181b: 48 89 4f f5 mov %rcx,-0xb(%rdi) - 43181f: 89 57 fc mov %edx,-0x4(%rdi) - 431822: c3 retq - 431823: 0f 1f 00 nopl (%rax) - 431826: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43182d: 00 00 00 - 431830: f3 0f 6f 46 c5 movdqu -0x3b(%rsi),%xmm0 - 431835: 4c 8b 46 d5 mov -0x2b(%rsi),%r8 - 431839: 4c 8b 4e dd mov -0x23(%rsi),%r9 - 43183d: 4c 8b 56 e5 mov -0x1b(%rsi),%r10 - 431841: 4c 8b 5e ed mov -0x13(%rsi),%r11 - 431845: 48 8b 4e f5 mov -0xb(%rsi),%rcx - 431849: 8b 56 fc mov -0x4(%rsi),%edx - 43184c: f3 0f 7f 47 c5 movdqu %xmm0,-0x3b(%rdi) - 431851: 4c 89 47 d5 mov %r8,-0x2b(%rdi) - 431855: 4c 89 4f dd mov %r9,-0x23(%rdi) - 431859: 4c 89 57 e5 mov %r10,-0x1b(%rdi) - 43185d: 4c 89 5f ed mov %r11,-0x13(%rdi) - 431861: 48 89 4f f5 mov %rcx,-0xb(%rdi) - 431865: 89 57 fc mov %edx,-0x4(%rdi) - 431868: c3 retq - 431869: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 431870: f3 0f 6f 46 cd movdqu -0x33(%rsi),%xmm0 - 431875: 4c 8b 4e dd mov -0x23(%rsi),%r9 - 431879: 4c 8b 56 e5 mov -0x1b(%rsi),%r10 - 43187d: 4c 8b 5e ed mov -0x13(%rsi),%r11 - 431881: 48 8b 4e f5 mov -0xb(%rsi),%rcx - 431885: 8b 56 fc mov -0x4(%rsi),%edx - 431888: f3 0f 7f 47 cd movdqu %xmm0,-0x33(%rdi) - 43188d: 4c 89 4f dd mov %r9,-0x23(%rdi) - 431891: 4c 89 57 e5 mov %r10,-0x1b(%rdi) - 431895: 4c 89 5f ed mov %r11,-0x13(%rdi) - 431899: 48 89 4f f5 mov %rcx,-0xb(%rdi) - 43189d: 89 57 fc mov %edx,-0x4(%rdi) - 4318a0: c3 retq - 4318a1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4318a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4318ad: 00 00 00 - 4318b0: 4c 8b 46 d5 mov -0x2b(%rsi),%r8 - 4318b4: 4c 8b 4e dd mov -0x23(%rsi),%r9 - 4318b8: 4c 8b 56 e5 mov -0x1b(%rsi),%r10 - 4318bc: 4c 8b 5e ed mov -0x13(%rsi),%r11 - 4318c0: 48 8b 4e f5 mov -0xb(%rsi),%rcx - 4318c4: 8b 56 fc mov -0x4(%rsi),%edx - 4318c7: 4c 89 47 d5 mov %r8,-0x2b(%rdi) - 4318cb: 4c 89 4f dd mov %r9,-0x23(%rdi) - 4318cf: 4c 89 57 e5 mov %r10,-0x1b(%rdi) - 4318d3: 4c 89 5f ed mov %r11,-0x13(%rdi) - 4318d7: 48 89 4f f5 mov %rcx,-0xb(%rdi) - 4318db: 89 57 fc mov %edx,-0x4(%rdi) - 4318de: c3 retq - 4318df: 90 nop - 4318e0: 4c 8b 4e dd mov -0x23(%rsi),%r9 - 4318e4: 4c 8b 56 e5 mov -0x1b(%rsi),%r10 - 4318e8: 4c 8b 5e ed mov -0x13(%rsi),%r11 - 4318ec: 48 8b 4e f5 mov -0xb(%rsi),%rcx - 4318f0: 8b 56 fc mov -0x4(%rsi),%edx - 4318f3: 4c 89 4f dd mov %r9,-0x23(%rdi) - 4318f7: 4c 89 57 e5 mov %r10,-0x1b(%rdi) - 4318fb: 4c 89 5f ed mov %r11,-0x13(%rdi) - 4318ff: 48 89 4f f5 mov %rcx,-0xb(%rdi) - 431903: 89 57 fc mov %edx,-0x4(%rdi) - 431906: c3 retq - 431907: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 43190e: 00 00 - 431910: 4c 8b 56 e5 mov -0x1b(%rsi),%r10 - 431914: 4c 8b 5e ed mov -0x13(%rsi),%r11 - 431918: 48 8b 4e f5 mov -0xb(%rsi),%rcx - 43191c: 8b 56 fc mov -0x4(%rsi),%edx - 43191f: 4c 89 57 e5 mov %r10,-0x1b(%rdi) - 431923: 4c 89 5f ed mov %r11,-0x13(%rdi) - 431927: 48 89 4f f5 mov %rcx,-0xb(%rdi) - 43192b: 89 57 fc mov %edx,-0x4(%rdi) - 43192e: c3 retq - 43192f: 90 nop - 431930: 4c 8b 5e ed mov -0x13(%rsi),%r11 - 431934: 48 8b 4e f5 mov -0xb(%rsi),%rcx - 431938: 8b 56 fc mov -0x4(%rsi),%edx - 43193b: 4c 89 5f ed mov %r11,-0x13(%rdi) - 43193f: 48 89 4f f5 mov %rcx,-0xb(%rdi) - 431943: 89 57 fc mov %edx,-0x4(%rdi) - 431946: c3 retq - 431947: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 43194e: 00 00 - 431950: 48 8b 4e f5 mov -0xb(%rsi),%rcx - 431954: 8b 56 fc mov -0x4(%rsi),%edx - 431957: 48 89 4f f5 mov %rcx,-0xb(%rdi) - 43195b: 89 57 fc mov %edx,-0x4(%rdi) - 43195e: c3 retq - 43195f: 90 nop - 431960: 66 8b 56 fd mov -0x3(%rsi),%dx - 431964: 66 8b 4e fe mov -0x2(%rsi),%cx - 431968: 66 89 57 fd mov %dx,-0x3(%rdi) - 43196c: 66 89 4f fe mov %cx,-0x2(%rdi) - 431970: c3 retq - 431971: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 431976: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43197d: 00 00 00 - 431980: f3 0f 6f 46 b4 movdqu -0x4c(%rsi),%xmm0 - 431985: f3 0f 6f 4e c4 movdqu -0x3c(%rsi),%xmm1 - 43198a: 4c 8b 46 d4 mov -0x2c(%rsi),%r8 - 43198e: 4c 8b 4e dc mov -0x24(%rsi),%r9 - 431992: 4c 8b 56 e4 mov -0x1c(%rsi),%r10 - 431996: 4c 8b 5e ec mov -0x14(%rsi),%r11 - 43199a: 48 8b 4e f4 mov -0xc(%rsi),%rcx - 43199e: 8b 56 fc mov -0x4(%rsi),%edx - 4319a1: f3 0f 7f 47 b4 movdqu %xmm0,-0x4c(%rdi) - 4319a6: f3 0f 7f 4f c4 movdqu %xmm1,-0x3c(%rdi) - 4319ab: 4c 89 47 d4 mov %r8,-0x2c(%rdi) - 4319af: 4c 89 4f dc mov %r9,-0x24(%rdi) - 4319b3: 4c 89 57 e4 mov %r10,-0x1c(%rdi) - 4319b7: 4c 89 5f ec mov %r11,-0x14(%rdi) - 4319bb: 48 89 4f f4 mov %rcx,-0xc(%rdi) - 4319bf: 89 57 fc mov %edx,-0x4(%rdi) - 4319c2: c3 retq - 4319c3: 0f 1f 00 nopl (%rax) - 4319c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4319cd: 00 00 00 - 4319d0: f3 0f 6f 46 bc movdqu -0x44(%rsi),%xmm0 - 4319d5: f3 0f 6f 4e cc movdqu -0x34(%rsi),%xmm1 - 4319da: 4c 8b 4e dc mov -0x24(%rsi),%r9 - 4319de: 4c 8b 56 e4 mov -0x1c(%rsi),%r10 - 4319e2: 4c 8b 5e ec mov -0x14(%rsi),%r11 - 4319e6: 48 8b 4e f4 mov -0xc(%rsi),%rcx - 4319ea: 8b 56 fc mov -0x4(%rsi),%edx - 4319ed: f3 0f 7f 47 bc movdqu %xmm0,-0x44(%rdi) - 4319f2: f3 0f 7f 4f cc movdqu %xmm1,-0x34(%rdi) - 4319f7: 4c 89 4f dc mov %r9,-0x24(%rdi) - 4319fb: 4c 89 57 e4 mov %r10,-0x1c(%rdi) - 4319ff: 4c 89 5f ec mov %r11,-0x14(%rdi) - 431a03: 48 89 4f f4 mov %rcx,-0xc(%rdi) - 431a07: 89 57 fc mov %edx,-0x4(%rdi) - 431a0a: c3 retq - 431a0b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 431a10: f3 0f 6f 46 c4 movdqu -0x3c(%rsi),%xmm0 - 431a15: 4c 8b 46 d4 mov -0x2c(%rsi),%r8 - 431a19: 4c 8b 4e dc mov -0x24(%rsi),%r9 - 431a1d: 4c 8b 56 e4 mov -0x1c(%rsi),%r10 - 431a21: 4c 8b 5e ec mov -0x14(%rsi),%r11 - 431a25: 48 8b 4e f4 mov -0xc(%rsi),%rcx - 431a29: 8b 56 fc mov -0x4(%rsi),%edx - 431a2c: f3 0f 7f 47 c4 movdqu %xmm0,-0x3c(%rdi) - 431a31: 4c 89 47 d4 mov %r8,-0x2c(%rdi) - 431a35: 4c 89 4f dc mov %r9,-0x24(%rdi) - 431a39: 4c 89 57 e4 mov %r10,-0x1c(%rdi) - 431a3d: 4c 89 5f ec mov %r11,-0x14(%rdi) - 431a41: 48 89 4f f4 mov %rcx,-0xc(%rdi) - 431a45: 89 57 fc mov %edx,-0x4(%rdi) - 431a48: c3 retq - 431a49: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 431a50: f3 0f 6f 46 cc movdqu -0x34(%rsi),%xmm0 - 431a55: 4c 8b 4e dc mov -0x24(%rsi),%r9 - 431a59: 4c 8b 56 e4 mov -0x1c(%rsi),%r10 - 431a5d: 4c 8b 5e ec mov -0x14(%rsi),%r11 - 431a61: 48 8b 4e f4 mov -0xc(%rsi),%rcx - 431a65: 8b 56 fc mov -0x4(%rsi),%edx - 431a68: f3 0f 7f 47 cc movdqu %xmm0,-0x34(%rdi) - 431a6d: 4c 89 4f dc mov %r9,-0x24(%rdi) - 431a71: 4c 89 57 e4 mov %r10,-0x1c(%rdi) - 431a75: 4c 89 5f ec mov %r11,-0x14(%rdi) - 431a79: 48 89 4f f4 mov %rcx,-0xc(%rdi) - 431a7d: 89 57 fc mov %edx,-0x4(%rdi) - 431a80: c3 retq - 431a81: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 431a86: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 431a8d: 00 00 00 - 431a90: 4c 8b 46 d4 mov -0x2c(%rsi),%r8 - 431a94: 4c 8b 4e dc mov -0x24(%rsi),%r9 - 431a98: 4c 8b 56 e4 mov -0x1c(%rsi),%r10 - 431a9c: 4c 8b 5e ec mov -0x14(%rsi),%r11 - 431aa0: 48 8b 4e f4 mov -0xc(%rsi),%rcx - 431aa4: 8b 56 fc mov -0x4(%rsi),%edx - 431aa7: 4c 89 47 d4 mov %r8,-0x2c(%rdi) - 431aab: 4c 89 4f dc mov %r9,-0x24(%rdi) - 431aaf: 4c 89 57 e4 mov %r10,-0x1c(%rdi) - 431ab3: 4c 89 5f ec mov %r11,-0x14(%rdi) - 431ab7: 48 89 4f f4 mov %rcx,-0xc(%rdi) - 431abb: 89 57 fc mov %edx,-0x4(%rdi) - 431abe: c3 retq - 431abf: 90 nop - 431ac0: 4c 8b 4e dc mov -0x24(%rsi),%r9 - 431ac4: 4c 8b 56 e4 mov -0x1c(%rsi),%r10 - 431ac8: 4c 8b 5e ec mov -0x14(%rsi),%r11 - 431acc: 48 8b 4e f4 mov -0xc(%rsi),%rcx - 431ad0: 8b 56 fc mov -0x4(%rsi),%edx - 431ad3: 4c 89 4f dc mov %r9,-0x24(%rdi) - 431ad7: 4c 89 57 e4 mov %r10,-0x1c(%rdi) - 431adb: 4c 89 5f ec mov %r11,-0x14(%rdi) - 431adf: 48 89 4f f4 mov %rcx,-0xc(%rdi) - 431ae3: 89 57 fc mov %edx,-0x4(%rdi) - 431ae6: c3 retq - 431ae7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 431aee: 00 00 - 431af0: 4c 8b 56 e4 mov -0x1c(%rsi),%r10 - 431af4: 4c 8b 5e ec mov -0x14(%rsi),%r11 - 431af8: 48 8b 4e f4 mov -0xc(%rsi),%rcx - 431afc: 8b 56 fc mov -0x4(%rsi),%edx - 431aff: 4c 89 57 e4 mov %r10,-0x1c(%rdi) - 431b03: 4c 89 5f ec mov %r11,-0x14(%rdi) - 431b07: 48 89 4f f4 mov %rcx,-0xc(%rdi) - 431b0b: 89 57 fc mov %edx,-0x4(%rdi) - 431b0e: c3 retq - 431b0f: 90 nop - 431b10: 4c 8b 5e ec mov -0x14(%rsi),%r11 - 431b14: 48 8b 4e f4 mov -0xc(%rsi),%rcx - 431b18: 8b 56 fc mov -0x4(%rsi),%edx - 431b1b: 4c 89 5f ec mov %r11,-0x14(%rdi) - 431b1f: 48 89 4f f4 mov %rcx,-0xc(%rdi) - 431b23: 89 57 fc mov %edx,-0x4(%rdi) - 431b26: c3 retq - 431b27: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 431b2e: 00 00 - 431b30: 48 8b 4e f4 mov -0xc(%rsi),%rcx - 431b34: 8b 56 fc mov -0x4(%rsi),%edx - 431b37: 48 89 4f f4 mov %rcx,-0xc(%rdi) - 431b3b: 89 57 fc mov %edx,-0x4(%rdi) - 431b3e: c3 retq - 431b3f: 90 nop - 431b40: 8b 56 fc mov -0x4(%rsi),%edx - 431b43: 89 57 fc mov %edx,-0x4(%rdi) - 431b46: c3 retq - 431b47: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 431b4e: 00 00 - 431b50: f3 0f 6f 46 b3 movdqu -0x4d(%rsi),%xmm0 - 431b55: f3 0f 6f 4e c3 movdqu -0x3d(%rsi),%xmm1 - 431b5a: 4c 8b 46 d3 mov -0x2d(%rsi),%r8 - 431b5e: 4c 8b 4e db mov -0x25(%rsi),%r9 - 431b62: 4c 8b 56 e3 mov -0x1d(%rsi),%r10 - 431b66: 4c 8b 5e eb mov -0x15(%rsi),%r11 - 431b6a: 48 8b 4e f3 mov -0xd(%rsi),%rcx - 431b6e: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 431b72: f3 0f 7f 47 b3 movdqu %xmm0,-0x4d(%rdi) - 431b77: f3 0f 7f 4f c3 movdqu %xmm1,-0x3d(%rdi) - 431b7c: 4c 89 47 d3 mov %r8,-0x2d(%rdi) - 431b80: 4c 89 4f db mov %r9,-0x25(%rdi) - 431b84: 4c 89 57 e3 mov %r10,-0x1d(%rdi) - 431b88: 4c 89 5f eb mov %r11,-0x15(%rdi) - 431b8c: 48 89 4f f3 mov %rcx,-0xd(%rdi) - 431b90: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 431b94: c3 retq - 431b95: 90 nop - 431b96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 431b9d: 00 00 00 - 431ba0: f3 0f 6f 46 bb movdqu -0x45(%rsi),%xmm0 - 431ba5: f3 0f 6f 4e cb movdqu -0x35(%rsi),%xmm1 - 431baa: 4c 8b 4e db mov -0x25(%rsi),%r9 - 431bae: 4c 8b 56 e3 mov -0x1d(%rsi),%r10 - 431bb2: 4c 8b 5e eb mov -0x15(%rsi),%r11 - 431bb6: 48 8b 4e f3 mov -0xd(%rsi),%rcx - 431bba: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 431bbe: f3 0f 7f 47 bb movdqu %xmm0,-0x45(%rdi) - 431bc3: f3 0f 7f 4f cb movdqu %xmm1,-0x35(%rdi) - 431bc8: 4c 89 4f db mov %r9,-0x25(%rdi) - 431bcc: 4c 89 57 e3 mov %r10,-0x1d(%rdi) - 431bd0: 4c 89 5f eb mov %r11,-0x15(%rdi) - 431bd4: 48 89 4f f3 mov %rcx,-0xd(%rdi) - 431bd8: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 431bdc: c3 retq - 431bdd: 0f 1f 00 nopl (%rax) - 431be0: f3 0f 6f 46 c3 movdqu -0x3d(%rsi),%xmm0 - 431be5: 4c 8b 46 d3 mov -0x2d(%rsi),%r8 - 431be9: 4c 8b 4e db mov -0x25(%rsi),%r9 - 431bed: 4c 8b 56 e3 mov -0x1d(%rsi),%r10 - 431bf1: 4c 8b 5e eb mov -0x15(%rsi),%r11 - 431bf5: 48 8b 4e f3 mov -0xd(%rsi),%rcx - 431bf9: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 431bfd: f3 0f 7f 47 c3 movdqu %xmm0,-0x3d(%rdi) - 431c02: 4c 89 47 d3 mov %r8,-0x2d(%rdi) - 431c06: 4c 89 4f db mov %r9,-0x25(%rdi) - 431c0a: 4c 89 57 e3 mov %r10,-0x1d(%rdi) - 431c0e: 4c 89 5f eb mov %r11,-0x15(%rdi) - 431c12: 48 89 4f f3 mov %rcx,-0xd(%rdi) - 431c16: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 431c1a: c3 retq - 431c1b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 431c20: f3 0f 6f 46 cb movdqu -0x35(%rsi),%xmm0 - 431c25: 4c 8b 46 d3 mov -0x2d(%rsi),%r8 - 431c29: 4c 8b 4e db mov -0x25(%rsi),%r9 - 431c2d: 4c 8b 56 e3 mov -0x1d(%rsi),%r10 - 431c31: 4c 8b 5e eb mov -0x15(%rsi),%r11 - 431c35: 48 8b 4e f3 mov -0xd(%rsi),%rcx - 431c39: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 431c3d: f3 0f 7f 47 cb movdqu %xmm0,-0x35(%rdi) - 431c42: 4c 89 4f db mov %r9,-0x25(%rdi) - 431c46: 4c 89 57 e3 mov %r10,-0x1d(%rdi) - 431c4a: 4c 89 5f eb mov %r11,-0x15(%rdi) - 431c4e: 48 89 4f f3 mov %rcx,-0xd(%rdi) - 431c52: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 431c56: c3 retq - 431c57: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 431c5e: 00 00 - 431c60: 4c 8b 46 d3 mov -0x2d(%rsi),%r8 - 431c64: 4c 8b 4e db mov -0x25(%rsi),%r9 - 431c68: 4c 8b 56 e3 mov -0x1d(%rsi),%r10 - 431c6c: 4c 8b 5e eb mov -0x15(%rsi),%r11 - 431c70: 48 8b 4e f3 mov -0xd(%rsi),%rcx - 431c74: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 431c78: 4c 89 47 d3 mov %r8,-0x2d(%rdi) - 431c7c: 4c 89 4f db mov %r9,-0x25(%rdi) - 431c80: 4c 89 57 e3 mov %r10,-0x1d(%rdi) - 431c84: 4c 89 5f eb mov %r11,-0x15(%rdi) - 431c88: 48 89 4f f3 mov %rcx,-0xd(%rdi) - 431c8c: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 431c90: c3 retq - 431c91: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 431c96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 431c9d: 00 00 00 - 431ca0: 4c 8b 4e db mov -0x25(%rsi),%r9 - 431ca4: 4c 8b 56 e3 mov -0x1d(%rsi),%r10 - 431ca8: 4c 8b 5e eb mov -0x15(%rsi),%r11 - 431cac: 48 8b 4e f3 mov -0xd(%rsi),%rcx - 431cb0: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 431cb4: 4c 89 4f db mov %r9,-0x25(%rdi) - 431cb8: 4c 89 57 e3 mov %r10,-0x1d(%rdi) - 431cbc: 4c 89 5f eb mov %r11,-0x15(%rdi) - 431cc0: 48 89 4f f3 mov %rcx,-0xd(%rdi) - 431cc4: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 431cc8: c3 retq - 431cc9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 431cd0: 4c 8b 56 e3 mov -0x1d(%rsi),%r10 - 431cd4: 4c 8b 5e eb mov -0x15(%rsi),%r11 - 431cd8: 48 8b 4e f3 mov -0xd(%rsi),%rcx - 431cdc: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 431ce0: 4c 89 57 e3 mov %r10,-0x1d(%rdi) - 431ce4: 4c 89 5f eb mov %r11,-0x15(%rdi) - 431ce8: 48 89 4f f3 mov %rcx,-0xd(%rdi) - 431cec: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 431cf0: c3 retq - 431cf1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 431cf6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 431cfd: 00 00 00 - 431d00: 4c 8b 5e eb mov -0x15(%rsi),%r11 - 431d04: 48 8b 4e f3 mov -0xd(%rsi),%rcx - 431d08: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 431d0c: 4c 89 5f eb mov %r11,-0x15(%rdi) - 431d10: 48 89 4f f3 mov %rcx,-0xd(%rdi) - 431d14: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 431d18: c3 retq - 431d19: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 431d20: 48 8b 4e f3 mov -0xd(%rsi),%rcx - 431d24: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 431d28: 48 89 4f f3 mov %rcx,-0xd(%rdi) - 431d2c: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 431d30: c3 retq - 431d31: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 431d36: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 431d3d: 00 00 00 - 431d40: 8b 56 fb mov -0x5(%rsi),%edx - 431d43: 8b 4e fc mov -0x4(%rsi),%ecx - 431d46: 89 57 fb mov %edx,-0x5(%rdi) - 431d49: 89 4f fc mov %ecx,-0x4(%rdi) - 431d4c: c3 retq - 431d4d: 0f 1f 00 nopl (%rax) - 431d50: f3 0f 6f 46 b2 movdqu -0x4e(%rsi),%xmm0 - 431d55: f3 0f 6f 4e c2 movdqu -0x3e(%rsi),%xmm1 - 431d5a: 4c 8b 46 d2 mov -0x2e(%rsi),%r8 - 431d5e: 4c 8b 4e da mov -0x26(%rsi),%r9 - 431d62: 4c 8b 56 e2 mov -0x1e(%rsi),%r10 - 431d66: 4c 8b 5e ea mov -0x16(%rsi),%r11 - 431d6a: 48 8b 4e f2 mov -0xe(%rsi),%rcx - 431d6e: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 431d72: f3 0f 7f 47 b2 movdqu %xmm0,-0x4e(%rdi) - 431d77: f3 0f 7f 4f c2 movdqu %xmm1,-0x3e(%rdi) - 431d7c: 4c 89 47 d2 mov %r8,-0x2e(%rdi) - 431d80: 4c 89 4f da mov %r9,-0x26(%rdi) - 431d84: 4c 89 57 e2 mov %r10,-0x1e(%rdi) - 431d88: 4c 89 5f ea mov %r11,-0x16(%rdi) - 431d8c: 48 89 4f f2 mov %rcx,-0xe(%rdi) - 431d90: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 431d94: c3 retq - 431d95: 90 nop - 431d96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 431d9d: 00 00 00 - 431da0: f3 0f 6f 46 ba movdqu -0x46(%rsi),%xmm0 - 431da5: f3 0f 6f 4e ca movdqu -0x36(%rsi),%xmm1 - 431daa: 4c 8b 4e da mov -0x26(%rsi),%r9 - 431dae: 4c 8b 56 e2 mov -0x1e(%rsi),%r10 - 431db2: 4c 8b 5e ea mov -0x16(%rsi),%r11 - 431db6: 48 8b 4e f2 mov -0xe(%rsi),%rcx - 431dba: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 431dbe: f3 0f 7f 47 ba movdqu %xmm0,-0x46(%rdi) - 431dc3: f3 0f 7f 4f ca movdqu %xmm1,-0x36(%rdi) - 431dc8: 4c 89 4f da mov %r9,-0x26(%rdi) - 431dcc: 4c 89 57 e2 mov %r10,-0x1e(%rdi) - 431dd0: 4c 89 5f ea mov %r11,-0x16(%rdi) - 431dd4: 48 89 4f f2 mov %rcx,-0xe(%rdi) - 431dd8: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 431ddc: c3 retq - 431ddd: 0f 1f 00 nopl (%rax) - 431de0: f3 0f 6f 46 c2 movdqu -0x3e(%rsi),%xmm0 - 431de5: 4c 8b 46 d2 mov -0x2e(%rsi),%r8 - 431de9: 4c 8b 4e da mov -0x26(%rsi),%r9 - 431ded: 4c 8b 56 e2 mov -0x1e(%rsi),%r10 - 431df1: 4c 8b 5e ea mov -0x16(%rsi),%r11 - 431df5: 48 8b 4e f2 mov -0xe(%rsi),%rcx - 431df9: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 431dfd: f3 0f 7f 47 c2 movdqu %xmm0,-0x3e(%rdi) - 431e02: 4c 89 47 d2 mov %r8,-0x2e(%rdi) - 431e06: 4c 89 4f da mov %r9,-0x26(%rdi) - 431e0a: 4c 89 57 e2 mov %r10,-0x1e(%rdi) - 431e0e: 4c 89 5f ea mov %r11,-0x16(%rdi) - 431e12: 48 89 4f f2 mov %rcx,-0xe(%rdi) - 431e16: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 431e1a: c3 retq - 431e1b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 431e20: f3 0f 6f 46 ca movdqu -0x36(%rsi),%xmm0 - 431e25: 4c 8b 4e da mov -0x26(%rsi),%r9 - 431e29: 4c 8b 56 e2 mov -0x1e(%rsi),%r10 - 431e2d: 4c 8b 5e ea mov -0x16(%rsi),%r11 - 431e31: 48 8b 4e f2 mov -0xe(%rsi),%rcx - 431e35: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 431e39: f3 0f 7f 47 ca movdqu %xmm0,-0x36(%rdi) - 431e3e: 4c 89 4f da mov %r9,-0x26(%rdi) - 431e42: 4c 89 57 e2 mov %r10,-0x1e(%rdi) - 431e46: 4c 89 5f ea mov %r11,-0x16(%rdi) - 431e4a: 48 89 4f f2 mov %rcx,-0xe(%rdi) - 431e4e: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 431e52: c3 retq - 431e53: 0f 1f 00 nopl (%rax) - 431e56: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 431e5d: 00 00 00 - 431e60: 4c 8b 46 d2 mov -0x2e(%rsi),%r8 - 431e64: 4c 8b 4e da mov -0x26(%rsi),%r9 - 431e68: 4c 8b 56 e2 mov -0x1e(%rsi),%r10 - 431e6c: 4c 8b 5e ea mov -0x16(%rsi),%r11 - 431e70: 48 8b 4e f2 mov -0xe(%rsi),%rcx - 431e74: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 431e78: 4c 89 47 d2 mov %r8,-0x2e(%rdi) - 431e7c: 4c 89 4f da mov %r9,-0x26(%rdi) - 431e80: 4c 89 57 e2 mov %r10,-0x1e(%rdi) - 431e84: 4c 89 5f ea mov %r11,-0x16(%rdi) - 431e88: 48 89 4f f2 mov %rcx,-0xe(%rdi) - 431e8c: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 431e90: c3 retq - 431e91: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 431e96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 431e9d: 00 00 00 - 431ea0: 4c 8b 4e da mov -0x26(%rsi),%r9 - 431ea4: 4c 8b 56 e2 mov -0x1e(%rsi),%r10 - 431ea8: 4c 8b 5e ea mov -0x16(%rsi),%r11 - 431eac: 48 8b 4e f2 mov -0xe(%rsi),%rcx - 431eb0: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 431eb4: 4c 89 4f da mov %r9,-0x26(%rdi) - 431eb8: 4c 89 57 e2 mov %r10,-0x1e(%rdi) - 431ebc: 4c 89 5f ea mov %r11,-0x16(%rdi) - 431ec0: 48 89 4f f2 mov %rcx,-0xe(%rdi) - 431ec4: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 431ec8: c3 retq - 431ec9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 431ed0: 4c 8b 56 e2 mov -0x1e(%rsi),%r10 - 431ed4: 4c 8b 5e ea mov -0x16(%rsi),%r11 - 431ed8: 48 8b 4e f2 mov -0xe(%rsi),%rcx - 431edc: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 431ee0: 4c 89 57 e2 mov %r10,-0x1e(%rdi) - 431ee4: 4c 89 5f ea mov %r11,-0x16(%rdi) - 431ee8: 48 89 4f f2 mov %rcx,-0xe(%rdi) - 431eec: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 431ef0: c3 retq - 431ef1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 431ef6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 431efd: 00 00 00 - 431f00: 4c 8b 5e ea mov -0x16(%rsi),%r11 - 431f04: 48 8b 4e f2 mov -0xe(%rsi),%rcx - 431f08: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 431f0c: 4c 89 5f ea mov %r11,-0x16(%rdi) - 431f10: 48 89 4f f2 mov %rcx,-0xe(%rdi) - 431f14: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 431f18: c3 retq - 431f19: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 431f20: 48 8b 4e f2 mov -0xe(%rsi),%rcx - 431f24: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 431f28: 48 89 4f f2 mov %rcx,-0xe(%rdi) - 431f2c: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 431f30: c3 retq - 431f31: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 431f36: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 431f3d: 00 00 00 - 431f40: 8b 56 fa mov -0x6(%rsi),%edx - 431f43: 8b 4e fc mov -0x4(%rsi),%ecx - 431f46: 89 57 fa mov %edx,-0x6(%rdi) - 431f49: 89 4f fc mov %ecx,-0x4(%rdi) - 431f4c: c3 retq - 431f4d: 0f 1f 00 nopl (%rax) - 431f50: f3 0f 6f 46 b1 movdqu -0x4f(%rsi),%xmm0 - 431f55: f3 0f 6f 4e c1 movdqu -0x3f(%rsi),%xmm1 - 431f5a: 4c 8b 46 d1 mov -0x2f(%rsi),%r8 - 431f5e: 4c 8b 4e d9 mov -0x27(%rsi),%r9 - 431f62: 4c 8b 56 e1 mov -0x1f(%rsi),%r10 - 431f66: 4c 8b 5e e9 mov -0x17(%rsi),%r11 - 431f6a: 48 8b 4e f1 mov -0xf(%rsi),%rcx - 431f6e: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 431f72: f3 0f 7f 47 b1 movdqu %xmm0,-0x4f(%rdi) - 431f77: f3 0f 7f 4f c1 movdqu %xmm1,-0x3f(%rdi) - 431f7c: 4c 89 47 d1 mov %r8,-0x2f(%rdi) - 431f80: 4c 89 4f d9 mov %r9,-0x27(%rdi) - 431f84: 4c 89 57 e1 mov %r10,-0x1f(%rdi) - 431f88: 4c 89 5f e9 mov %r11,-0x17(%rdi) - 431f8c: 48 89 4f f1 mov %rcx,-0xf(%rdi) - 431f90: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 431f94: c3 retq - 431f95: 90 nop - 431f96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 431f9d: 00 00 00 - 431fa0: f3 0f 6f 46 b9 movdqu -0x47(%rsi),%xmm0 - 431fa5: f3 0f 6f 4e c9 movdqu -0x37(%rsi),%xmm1 - 431faa: 4c 8b 4e d9 mov -0x27(%rsi),%r9 - 431fae: 4c 8b 56 e1 mov -0x1f(%rsi),%r10 - 431fb2: 4c 8b 5e e9 mov -0x17(%rsi),%r11 - 431fb6: 48 8b 4e f1 mov -0xf(%rsi),%rcx - 431fba: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 431fbe: f3 0f 7f 47 b9 movdqu %xmm0,-0x47(%rdi) - 431fc3: f3 0f 7f 4f c9 movdqu %xmm1,-0x37(%rdi) - 431fc8: 4c 89 4f d9 mov %r9,-0x27(%rdi) - 431fcc: 4c 89 57 e1 mov %r10,-0x1f(%rdi) - 431fd0: 4c 89 5f e9 mov %r11,-0x17(%rdi) - 431fd4: 48 89 4f f1 mov %rcx,-0xf(%rdi) - 431fd8: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 431fdc: c3 retq - 431fdd: 0f 1f 00 nopl (%rax) - 431fe0: f3 0f 6f 46 c1 movdqu -0x3f(%rsi),%xmm0 - 431fe5: 4c 8b 46 d1 mov -0x2f(%rsi),%r8 - 431fe9: 4c 8b 4e d9 mov -0x27(%rsi),%r9 - 431fed: 4c 8b 56 e1 mov -0x1f(%rsi),%r10 - 431ff1: 4c 8b 5e e9 mov -0x17(%rsi),%r11 - 431ff5: 48 8b 4e f1 mov -0xf(%rsi),%rcx - 431ff9: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 431ffd: f3 0f 7f 47 c1 movdqu %xmm0,-0x3f(%rdi) - 432002: 4c 89 47 d1 mov %r8,-0x2f(%rdi) - 432006: 4c 89 4f d9 mov %r9,-0x27(%rdi) - 43200a: 4c 89 57 e1 mov %r10,-0x1f(%rdi) - 43200e: 4c 89 5f e9 mov %r11,-0x17(%rdi) - 432012: 48 89 4f f1 mov %rcx,-0xf(%rdi) - 432016: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 43201a: c3 retq - 43201b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 432020: f3 0f 6f 46 c9 movdqu -0x37(%rsi),%xmm0 - 432025: 4c 8b 4e d9 mov -0x27(%rsi),%r9 - 432029: 4c 8b 56 e1 mov -0x1f(%rsi),%r10 - 43202d: 4c 8b 5e e9 mov -0x17(%rsi),%r11 - 432031: 48 8b 4e f1 mov -0xf(%rsi),%rcx - 432035: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 432039: f3 0f 7f 47 c9 movdqu %xmm0,-0x37(%rdi) - 43203e: 4c 89 4f d9 mov %r9,-0x27(%rdi) - 432042: 4c 89 57 e1 mov %r10,-0x1f(%rdi) - 432046: 4c 89 5f e9 mov %r11,-0x17(%rdi) - 43204a: 48 89 4f f1 mov %rcx,-0xf(%rdi) - 43204e: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 432052: c3 retq - 432053: 0f 1f 00 nopl (%rax) - 432056: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43205d: 00 00 00 - 432060: 4c 8b 46 d1 mov -0x2f(%rsi),%r8 - 432064: 4c 8b 4e d9 mov -0x27(%rsi),%r9 - 432068: 4c 8b 56 e1 mov -0x1f(%rsi),%r10 - 43206c: 4c 8b 5e e9 mov -0x17(%rsi),%r11 - 432070: 48 8b 4e f1 mov -0xf(%rsi),%rcx - 432074: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 432078: 4c 89 47 d1 mov %r8,-0x2f(%rdi) - 43207c: 4c 89 4f d9 mov %r9,-0x27(%rdi) - 432080: 4c 89 57 e1 mov %r10,-0x1f(%rdi) - 432084: 4c 89 5f e9 mov %r11,-0x17(%rdi) - 432088: 48 89 4f f1 mov %rcx,-0xf(%rdi) - 43208c: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 432090: c3 retq - 432091: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 432096: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43209d: 00 00 00 - 4320a0: 4c 8b 4e d9 mov -0x27(%rsi),%r9 - 4320a4: 4c 8b 56 e1 mov -0x1f(%rsi),%r10 - 4320a8: 4c 8b 5e e9 mov -0x17(%rsi),%r11 - 4320ac: 48 8b 4e f1 mov -0xf(%rsi),%rcx - 4320b0: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 4320b4: 4c 89 4f d9 mov %r9,-0x27(%rdi) - 4320b8: 4c 89 57 e1 mov %r10,-0x1f(%rdi) - 4320bc: 4c 89 5f e9 mov %r11,-0x17(%rdi) - 4320c0: 48 89 4f f1 mov %rcx,-0xf(%rdi) - 4320c4: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 4320c8: c3 retq - 4320c9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4320d0: 4c 8b 56 e1 mov -0x1f(%rsi),%r10 - 4320d4: 4c 8b 5e e9 mov -0x17(%rsi),%r11 - 4320d8: 48 8b 4e f1 mov -0xf(%rsi),%rcx - 4320dc: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 4320e0: 4c 89 57 e1 mov %r10,-0x1f(%rdi) - 4320e4: 4c 89 5f e9 mov %r11,-0x17(%rdi) - 4320e8: 48 89 4f f1 mov %rcx,-0xf(%rdi) - 4320ec: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 4320f0: c3 retq - 4320f1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4320f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4320fd: 00 00 00 - 432100: 4c 8b 5e e9 mov -0x17(%rsi),%r11 - 432104: 48 8b 4e f1 mov -0xf(%rsi),%rcx - 432108: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 43210c: 4c 89 5f e9 mov %r11,-0x17(%rdi) - 432110: 48 89 4f f1 mov %rcx,-0xf(%rdi) - 432114: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 432118: c3 retq - 432119: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 432120: 48 8b 4e f1 mov -0xf(%rsi),%rcx - 432124: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 432128: 48 89 4f f1 mov %rcx,-0xf(%rdi) - 43212c: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 432130: c3 retq - 432131: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 432136: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43213d: 00 00 00 - 432140: 8b 56 f9 mov -0x7(%rsi),%edx - 432143: 8b 4e fc mov -0x4(%rsi),%ecx - 432146: 89 57 f9 mov %edx,-0x7(%rdi) - 432149: 89 4f fc mov %ecx,-0x4(%rdi) - 43214c: c3 retq - 43214d: 0f 1f 00 nopl (%rax) - 432150: f3 0f 6f 0e movdqu (%rsi),%xmm1 - 432154: 48 8d 76 10 lea 0x10(%rsi),%rsi - 432158: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 43215d: 66 0f e7 0f movntdq %xmm1,(%rdi) - 432161: 48 8d 7f 10 lea 0x10(%rdi),%rdi - 432165: 48 8d 92 70 ff ff ff lea -0x90(%rdx),%rdx - 43216c: 49 89 f1 mov %rsi,%r9 - 43216f: 49 29 f9 sub %rdi,%r9 - 432172: 49 39 d1 cmp %rdx,%r9 - 432175: 73 0d jae 432184 <__memmove_ssse3+0x2834> - 432177: 48 c1 e1 02 shl $0x2,%rcx - 43217b: 48 39 ca cmp %rcx,%rdx - 43217e: 0f 82 cc 00 00 00 jb 432250 <__memmove_ssse3+0x2900> - 432184: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 432188: f3 0f 6f 4e 10 movdqu 0x10(%rsi),%xmm1 - 43218d: f3 0f 6f 56 20 movdqu 0x20(%rsi),%xmm2 - 432192: f3 0f 6f 5e 30 movdqu 0x30(%rsi),%xmm3 - 432197: f3 0f 6f 66 40 movdqu 0x40(%rsi),%xmm4 - 43219c: f3 0f 6f 6e 50 movdqu 0x50(%rsi),%xmm5 - 4321a1: f3 0f 6f 76 60 movdqu 0x60(%rsi),%xmm6 - 4321a6: f3 0f 6f 7e 70 movdqu 0x70(%rsi),%xmm7 - 4321ab: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi - 4321b2: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 4321b9: 66 0f e7 07 movntdq %xmm0,(%rdi) - 4321bd: 66 0f e7 4f 10 movntdq %xmm1,0x10(%rdi) - 4321c2: 66 0f e7 57 20 movntdq %xmm2,0x20(%rdi) - 4321c7: 66 0f e7 5f 30 movntdq %xmm3,0x30(%rdi) - 4321cc: 66 0f e7 67 40 movntdq %xmm4,0x40(%rdi) - 4321d1: 66 0f e7 6f 50 movntdq %xmm5,0x50(%rdi) - 4321d6: 66 0f e7 77 60 movntdq %xmm6,0x60(%rdi) - 4321db: 66 0f e7 7f 70 movntdq %xmm7,0x70(%rdi) - 4321e0: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi - 4321e7: 73 9b jae 432184 <__memmove_ssse3+0x2834> - 4321e9: 48 83 fa c0 cmp $0xffffffffffffffc0,%rdx - 4321ed: 48 8d 92 80 00 00 00 lea 0x80(%rdx),%rdx - 4321f4: 7c 32 jl 432228 <__memmove_ssse3+0x28d8> - 4321f6: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 4321fa: f3 0f 6f 4e 10 movdqu 0x10(%rsi),%xmm1 - 4321ff: f3 0f 6f 56 20 movdqu 0x20(%rsi),%xmm2 - 432204: f3 0f 6f 5e 30 movdqu 0x30(%rsi),%xmm3 - 432209: 48 8d 76 40 lea 0x40(%rsi),%rsi - 43220d: 66 0f e7 07 movntdq %xmm0,(%rdi) - 432211: 66 0f e7 4f 10 movntdq %xmm1,0x10(%rdi) - 432216: 66 0f e7 57 20 movntdq %xmm2,0x20(%rdi) - 43221b: 66 0f e7 5f 30 movntdq %xmm3,0x30(%rdi) - 432220: 48 8d 7f 40 lea 0x40(%rdi),%rdi - 432224: 48 83 ea 40 sub $0x40,%rdx - 432228: 48 01 d6 add %rdx,%rsi - 43222b: 48 01 d7 add %rdx,%rdi - 43222e: 0f ae f8 sfence - 432231: 4c 8d 1d 78 11 07 00 lea 0x71178(%rip),%r11 # 4a33b0 - 432238: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 43223c: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 432240: ff e2 jmpq *%rdx - 432242: 0f 0b ud2 - 432244: 66 90 xchg %ax,%ax - 432246: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43224d: 00 00 00 - 432250: 0f 18 8e c0 01 00 00 prefetcht0 0x1c0(%rsi) - 432257: 0f 18 8e 00 02 00 00 prefetcht0 0x200(%rsi) - 43225e: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 432262: f3 0f 6f 4e 10 movdqu 0x10(%rsi),%xmm1 - 432267: f3 0f 6f 56 20 movdqu 0x20(%rsi),%xmm2 - 43226c: f3 0f 6f 5e 30 movdqu 0x30(%rsi),%xmm3 - 432271: f3 0f 6f 66 40 movdqu 0x40(%rsi),%xmm4 - 432276: f3 0f 6f 6e 50 movdqu 0x50(%rsi),%xmm5 - 43227b: f3 0f 6f 76 60 movdqu 0x60(%rsi),%xmm6 - 432280: f3 0f 6f 7e 70 movdqu 0x70(%rsi),%xmm7 - 432285: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi - 43228c: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 432293: 0f 29 07 movaps %xmm0,(%rdi) - 432296: 0f 29 4f 10 movaps %xmm1,0x10(%rdi) - 43229a: 0f 29 57 20 movaps %xmm2,0x20(%rdi) - 43229e: 0f 29 5f 30 movaps %xmm3,0x30(%rdi) - 4322a2: 0f 29 67 40 movaps %xmm4,0x40(%rdi) - 4322a6: 0f 29 6f 50 movaps %xmm5,0x50(%rdi) - 4322aa: 0f 29 77 60 movaps %xmm6,0x60(%rdi) - 4322ae: 0f 29 7f 70 movaps %xmm7,0x70(%rdi) - 4322b2: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi - 4322b9: 73 95 jae 432250 <__memmove_ssse3+0x2900> - 4322bb: 48 83 fa c0 cmp $0xffffffffffffffc0,%rdx - 4322bf: 48 8d 92 80 00 00 00 lea 0x80(%rdx),%rdx - 4322c6: 7c 2e jl 4322f6 <__memmove_ssse3+0x29a6> - 4322c8: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 4322cc: f3 0f 6f 4e 10 movdqu 0x10(%rsi),%xmm1 - 4322d1: f3 0f 6f 56 20 movdqu 0x20(%rsi),%xmm2 - 4322d6: f3 0f 6f 5e 30 movdqu 0x30(%rsi),%xmm3 - 4322db: 48 8d 76 40 lea 0x40(%rsi),%rsi - 4322df: 0f 29 07 movaps %xmm0,(%rdi) - 4322e2: 0f 29 4f 10 movaps %xmm1,0x10(%rdi) - 4322e6: 0f 29 57 20 movaps %xmm2,0x20(%rdi) - 4322ea: 0f 29 5f 30 movaps %xmm3,0x30(%rdi) - 4322ee: 48 8d 7f 40 lea 0x40(%rdi),%rdi - 4322f2: 48 83 ea 40 sub $0x40,%rdx - 4322f6: 48 01 d6 add %rdx,%rsi - 4322f9: 48 01 d7 add %rdx,%rdi - 4322fc: 4c 8d 1d ad 10 07 00 lea 0x710ad(%rip),%r11 # 4a33b0 - 432303: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 432307: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 43230b: ff e2 jmpq *%rdx - 43230d: 0f 0b ud2 - 43230f: 90 nop - 432310: f3 0f 6f 4e f0 movdqu -0x10(%rsi),%xmm1 - 432315: 48 8d 76 f0 lea -0x10(%rsi),%rsi - 432319: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 43231e: 66 0f 7f 4f f0 movdqa %xmm1,-0x10(%rdi) - 432323: 48 8d 7f f0 lea -0x10(%rdi),%rdi - 432327: 48 8d 92 70 ff ff ff lea -0x90(%rdx),%rdx - 43232e: 49 89 f9 mov %rdi,%r9 - 432331: 49 29 f1 sub %rsi,%r9 - 432334: 49 39 d1 cmp %rdx,%r9 - 432337: 73 09 jae 432342 <__memmove_ssse3+0x29f2> - 432339: 49 39 c9 cmp %rcx,%r9 - 43233c: 0f 82 be 00 00 00 jb 432400 <__memmove_ssse3+0x2ab0> - 432342: f3 0f 6f 46 f0 movdqu -0x10(%rsi),%xmm0 - 432347: f3 0f 6f 4e e0 movdqu -0x20(%rsi),%xmm1 - 43234c: f3 0f 6f 56 d0 movdqu -0x30(%rsi),%xmm2 - 432351: f3 0f 6f 5e c0 movdqu -0x40(%rsi),%xmm3 - 432356: f3 0f 6f 66 b0 movdqu -0x50(%rsi),%xmm4 - 43235b: f3 0f 6f 6e a0 movdqu -0x60(%rsi),%xmm5 - 432360: f3 0f 6f 76 90 movdqu -0x70(%rsi),%xmm6 - 432365: f3 0f 6f 7e 80 movdqu -0x80(%rsi),%xmm7 - 43236a: 48 8d 76 80 lea -0x80(%rsi),%rsi - 43236e: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 432375: 66 0f e7 47 f0 movntdq %xmm0,-0x10(%rdi) - 43237a: 66 0f e7 4f e0 movntdq %xmm1,-0x20(%rdi) - 43237f: 66 0f e7 57 d0 movntdq %xmm2,-0x30(%rdi) - 432384: 66 0f e7 5f c0 movntdq %xmm3,-0x40(%rdi) - 432389: 66 0f e7 67 b0 movntdq %xmm4,-0x50(%rdi) - 43238e: 66 0f e7 6f a0 movntdq %xmm5,-0x60(%rdi) - 432393: 66 0f e7 77 90 movntdq %xmm6,-0x70(%rdi) - 432398: 66 0f e7 7f 80 movntdq %xmm7,-0x80(%rdi) - 43239d: 48 8d 7f 80 lea -0x80(%rdi),%rdi - 4323a1: 73 9f jae 432342 <__memmove_ssse3+0x29f2> - 4323a3: 48 83 fa c0 cmp $0xffffffffffffffc0,%rdx - 4323a7: 48 8d 92 80 00 00 00 lea 0x80(%rdx),%rdx - 4323ae: 7c 34 jl 4323e4 <__memmove_ssse3+0x2a94> - 4323b0: f3 0f 6f 46 f0 movdqu -0x10(%rsi),%xmm0 - 4323b5: f3 0f 6f 4e e0 movdqu -0x20(%rsi),%xmm1 - 4323ba: f3 0f 6f 56 d0 movdqu -0x30(%rsi),%xmm2 - 4323bf: f3 0f 6f 5e c0 movdqu -0x40(%rsi),%xmm3 - 4323c4: 48 8d 76 c0 lea -0x40(%rsi),%rsi - 4323c8: 66 0f e7 47 f0 movntdq %xmm0,-0x10(%rdi) - 4323cd: 66 0f e7 4f e0 movntdq %xmm1,-0x20(%rdi) - 4323d2: 66 0f e7 57 d0 movntdq %xmm2,-0x30(%rdi) - 4323d7: 66 0f e7 5f c0 movntdq %xmm3,-0x40(%rdi) - 4323dc: 48 8d 7f c0 lea -0x40(%rdi),%rdi - 4323e0: 48 83 ea 40 sub $0x40,%rdx - 4323e4: 0f ae f8 sfence - 4323e7: 4c 8d 1d c2 0f 07 00 lea 0x70fc2(%rip),%r11 # 4a33b0 - 4323ee: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 4323f2: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 4323f6: ff e2 jmpq *%rdx - 4323f8: 0f 0b ud2 - 4323fa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 432400: 0f 18 8e 40 fe ff ff prefetcht0 -0x1c0(%rsi) - 432407: 0f 18 8e 00 fe ff ff prefetcht0 -0x200(%rsi) - 43240e: f3 0f 6f 46 f0 movdqu -0x10(%rsi),%xmm0 - 432413: f3 0f 6f 4e e0 movdqu -0x20(%rsi),%xmm1 - 432418: f3 0f 6f 56 d0 movdqu -0x30(%rsi),%xmm2 - 43241d: f3 0f 6f 5e c0 movdqu -0x40(%rsi),%xmm3 - 432422: f3 0f 6f 66 b0 movdqu -0x50(%rsi),%xmm4 - 432427: f3 0f 6f 6e a0 movdqu -0x60(%rsi),%xmm5 - 43242c: f3 0f 6f 76 90 movdqu -0x70(%rsi),%xmm6 - 432431: f3 0f 6f 7e 80 movdqu -0x80(%rsi),%xmm7 - 432436: 48 8d 76 80 lea -0x80(%rsi),%rsi - 43243a: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 432441: 0f 29 47 f0 movaps %xmm0,-0x10(%rdi) - 432445: 0f 29 4f e0 movaps %xmm1,-0x20(%rdi) - 432449: 0f 29 57 d0 movaps %xmm2,-0x30(%rdi) - 43244d: 0f 29 5f c0 movaps %xmm3,-0x40(%rdi) - 432451: 0f 29 67 b0 movaps %xmm4,-0x50(%rdi) - 432455: 0f 29 6f a0 movaps %xmm5,-0x60(%rdi) - 432459: 0f 29 77 90 movaps %xmm6,-0x70(%rdi) - 43245d: 0f 29 7f 80 movaps %xmm7,-0x80(%rdi) - 432461: 48 8d 7f 80 lea -0x80(%rdi),%rdi - 432465: 73 99 jae 432400 <__memmove_ssse3+0x2ab0> - 432467: 48 83 fa c0 cmp $0xffffffffffffffc0,%rdx - 43246b: 48 8d 92 80 00 00 00 lea 0x80(%rdx),%rdx - 432472: 7c 30 jl 4324a4 <__memmove_ssse3+0x2b54> - 432474: f3 0f 6f 46 f0 movdqu -0x10(%rsi),%xmm0 - 432479: f3 0f 6f 4e e0 movdqu -0x20(%rsi),%xmm1 - 43247e: f3 0f 6f 56 d0 movdqu -0x30(%rsi),%xmm2 - 432483: f3 0f 6f 5e c0 movdqu -0x40(%rsi),%xmm3 - 432488: 48 8d 76 c0 lea -0x40(%rsi),%rsi - 43248c: 0f 29 47 f0 movaps %xmm0,-0x10(%rdi) - 432490: 0f 29 4f e0 movaps %xmm1,-0x20(%rdi) - 432494: 0f 29 57 d0 movaps %xmm2,-0x30(%rdi) - 432498: 0f 29 5f c0 movaps %xmm3,-0x40(%rdi) - 43249c: 48 8d 7f c0 lea -0x40(%rdi),%rdi - 4324a0: 48 83 ea 40 sub $0x40,%rdx - 4324a4: 4c 8d 1d 05 0f 07 00 lea 0x70f05(%rip),%r11 # 4a33b0 - 4324ab: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 4324af: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 4324b3: ff e2 jmpq *%rdx - 4324b5: 0f 0b ud2 - 4324b7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 4324be: 00 00 - -00000000004324c0 <__memmove_chk_avx_unaligned>: - 4324c0: 48 39 d1 cmp %rdx,%rcx - 4324c3: 0f 82 e7 05 01 00 jb 442ab0 <__chk_fail> - 4324c9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - -00000000004324d0 <__memmove_avx_unaligned>: - 4324d0: 48 89 f8 mov %rdi,%rax - 4324d3: 48 81 fa 00 01 00 00 cmp $0x100,%rdx - 4324da: 0f 83 c0 01 00 00 jae 4326a0 <__memmove_avx_unaligned+0x1d0> - 4324e0: 80 fa 10 cmp $0x10,%dl - 4324e3: 0f 82 67 01 00 00 jb 432650 <__memmove_avx_unaligned+0x180> - 4324e9: 80 fa 80 cmp $0x80,%dl - 4324ec: 0f 82 ae 00 00 00 jb 4325a0 <__memmove_avx_unaligned+0xd0> - 4324f2: c5 fa 6f 06 vmovdqu (%rsi),%xmm0 - 4324f6: 48 8d 0c 16 lea (%rsi,%rdx,1),%rcx - 4324fa: c5 fa 6f 4e 10 vmovdqu 0x10(%rsi),%xmm1 - 4324ff: c5 fa 6f 56 20 vmovdqu 0x20(%rsi),%xmm2 - 432504: c5 fa 6f 5e 30 vmovdqu 0x30(%rsi),%xmm3 - 432509: c5 fa 6f 66 40 vmovdqu 0x40(%rsi),%xmm4 - 43250e: c5 fa 6f 6e 50 vmovdqu 0x50(%rsi),%xmm5 - 432513: c5 fa 6f 76 60 vmovdqu 0x60(%rsi),%xmm6 - 432518: c5 fa 6f 7e 70 vmovdqu 0x70(%rsi),%xmm7 - 43251d: c5 7a 6f 41 80 vmovdqu -0x80(%rcx),%xmm8 - 432522: c5 7a 6f 49 90 vmovdqu -0x70(%rcx),%xmm9 - 432527: c5 7a 6f 51 a0 vmovdqu -0x60(%rcx),%xmm10 - 43252c: c5 7a 6f 59 b0 vmovdqu -0x50(%rcx),%xmm11 - 432531: c5 7a 6f 61 c0 vmovdqu -0x40(%rcx),%xmm12 - 432536: c5 7a 6f 69 d0 vmovdqu -0x30(%rcx),%xmm13 - 43253b: c5 7a 6f 71 e0 vmovdqu -0x20(%rcx),%xmm14 - 432540: c5 7a 6f 79 f0 vmovdqu -0x10(%rcx),%xmm15 - 432545: 48 8d 14 17 lea (%rdi,%rdx,1),%rdx - 432549: c5 fa 7f 07 vmovdqu %xmm0,(%rdi) - 43254d: c5 fa 7f 4f 10 vmovdqu %xmm1,0x10(%rdi) - 432552: c5 fa 7f 57 20 vmovdqu %xmm2,0x20(%rdi) - 432557: c5 fa 7f 5f 30 vmovdqu %xmm3,0x30(%rdi) - 43255c: c5 fa 7f 67 40 vmovdqu %xmm4,0x40(%rdi) - 432561: c5 fa 7f 6f 50 vmovdqu %xmm5,0x50(%rdi) - 432566: c5 fa 7f 77 60 vmovdqu %xmm6,0x60(%rdi) - 43256b: c5 fa 7f 7f 70 vmovdqu %xmm7,0x70(%rdi) - 432570: c5 7a 7f 42 80 vmovdqu %xmm8,-0x80(%rdx) - 432575: c5 7a 7f 4a 90 vmovdqu %xmm9,-0x70(%rdx) - 43257a: c5 7a 7f 52 a0 vmovdqu %xmm10,-0x60(%rdx) - 43257f: c5 7a 7f 5a b0 vmovdqu %xmm11,-0x50(%rdx) - 432584: c5 7a 7f 62 c0 vmovdqu %xmm12,-0x40(%rdx) - 432589: c5 7a 7f 6a d0 vmovdqu %xmm13,-0x30(%rdx) - 43258e: c5 7a 7f 72 e0 vmovdqu %xmm14,-0x20(%rdx) - 432593: c5 7a 7f 7a f0 vmovdqu %xmm15,-0x10(%rdx) - 432598: c3 retq - 432599: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4325a0: 80 fa 40 cmp $0x40,%dl - 4325a3: 72 5b jb 432600 <__memmove_avx_unaligned+0x130> - 4325a5: c5 fa 6f 06 vmovdqu (%rsi),%xmm0 - 4325a9: 48 8d 0c 16 lea (%rsi,%rdx,1),%rcx - 4325ad: c5 fa 6f 4e 10 vmovdqu 0x10(%rsi),%xmm1 - 4325b2: c5 fa 6f 56 20 vmovdqu 0x20(%rsi),%xmm2 - 4325b7: 48 8d 14 17 lea (%rdi,%rdx,1),%rdx - 4325bb: c5 fa 6f 5e 30 vmovdqu 0x30(%rsi),%xmm3 - 4325c0: c5 fa 6f 61 c0 vmovdqu -0x40(%rcx),%xmm4 - 4325c5: c5 fa 6f 69 d0 vmovdqu -0x30(%rcx),%xmm5 - 4325ca: c5 fa 6f 71 e0 vmovdqu -0x20(%rcx),%xmm6 - 4325cf: c5 fa 6f 79 f0 vmovdqu -0x10(%rcx),%xmm7 - 4325d4: c5 fa 7f 07 vmovdqu %xmm0,(%rdi) - 4325d8: c5 fa 7f 4f 10 vmovdqu %xmm1,0x10(%rdi) - 4325dd: c5 fa 7f 57 20 vmovdqu %xmm2,0x20(%rdi) - 4325e2: c5 fa 7f 5f 30 vmovdqu %xmm3,0x30(%rdi) - 4325e7: c5 fa 7f 62 c0 vmovdqu %xmm4,-0x40(%rdx) - 4325ec: c5 fa 7f 6a d0 vmovdqu %xmm5,-0x30(%rdx) - 4325f1: c5 fa 7f 72 e0 vmovdqu %xmm6,-0x20(%rdx) - 4325f6: c5 fa 7f 7a f0 vmovdqu %xmm7,-0x10(%rdx) - 4325fb: c3 retq - 4325fc: 0f 1f 40 00 nopl 0x0(%rax) - 432600: 80 fa 20 cmp $0x20,%dl - 432603: 72 2b jb 432630 <__memmove_avx_unaligned+0x160> - 432605: c5 fa 6f 06 vmovdqu (%rsi),%xmm0 - 432609: c5 fa 6f 4e 10 vmovdqu 0x10(%rsi),%xmm1 - 43260e: c5 fa 6f 74 16 e0 vmovdqu -0x20(%rsi,%rdx,1),%xmm6 - 432614: c5 fa 6f 7c 16 f0 vmovdqu -0x10(%rsi,%rdx,1),%xmm7 - 43261a: c5 fa 7f 07 vmovdqu %xmm0,(%rdi) - 43261e: c5 fa 7f 4f 10 vmovdqu %xmm1,0x10(%rdi) - 432623: c5 fa 7f 74 17 e0 vmovdqu %xmm6,-0x20(%rdi,%rdx,1) - 432629: c5 fa 7f 7c 17 f0 vmovdqu %xmm7,-0x10(%rdi,%rdx,1) - 43262f: c3 retq - 432630: c5 fa 6f 06 vmovdqu (%rsi),%xmm0 - 432634: c5 fa 6f 7c 16 f0 vmovdqu -0x10(%rsi,%rdx,1),%xmm7 - 43263a: c5 fa 7f 07 vmovdqu %xmm0,(%rdi) - 43263e: c5 fa 7f 7c 17 f0 vmovdqu %xmm7,-0x10(%rdi,%rdx,1) - 432644: c3 retq - 432645: 90 nop - 432646: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43264d: 00 00 00 - 432650: 80 fa 08 cmp $0x8,%dl - 432653: 72 1b jb 432670 <__memmove_avx_unaligned+0x1a0> - 432655: 48 8b 4c 16 f8 mov -0x8(%rsi,%rdx,1),%rcx - 43265a: 48 8b 36 mov (%rsi),%rsi - 43265d: 48 89 37 mov %rsi,(%rdi) - 432660: 48 89 4c 17 f8 mov %rcx,-0x8(%rdi,%rdx,1) - 432665: c3 retq - 432666: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43266d: 00 00 00 - 432670: 80 fa 04 cmp $0x4,%dl - 432673: 72 0d jb 432682 <__memmove_avx_unaligned+0x1b2> - 432675: 8b 4c 16 fc mov -0x4(%rsi,%rdx,1),%ecx - 432679: 8b 36 mov (%rsi),%esi - 43267b: 89 37 mov %esi,(%rdi) - 43267d: 89 4c 17 fc mov %ecx,-0x4(%rdi,%rdx,1) - 432681: c3 retq - 432682: 80 fa 01 cmp $0x1,%dl - 432685: 76 11 jbe 432698 <__memmove_avx_unaligned+0x1c8> - 432687: 66 8b 4c 16 fe mov -0x2(%rsi,%rdx,1),%cx - 43268c: 66 8b 36 mov (%rsi),%si - 43268f: 66 89 37 mov %si,(%rdi) - 432692: 66 89 4c 17 fe mov %cx,-0x2(%rdi,%rdx,1) - 432697: c3 retq - 432698: 72 04 jb 43269e <__memmove_avx_unaligned+0x1ce> - 43269a: 8a 0e mov (%rsi),%cl - 43269c: 88 0f mov %cl,(%rdi) - 43269e: c3 retq - 43269f: 90 nop - 4326a0: 48 89 f9 mov %rdi,%rcx - 4326a3: 48 29 f1 sub %rsi,%rcx - 4326a6: 48 39 d1 cmp %rdx,%rcx - 4326a9: 0f 82 c1 01 00 00 jb 432870 <__memmove_avx_unaligned+0x3a0> - 4326af: 48 81 fa 00 08 00 00 cmp $0x800,%rdx - 4326b6: 0f 83 c4 00 00 00 jae 432780 <__memmove_avx_unaligned+0x2b0> - 4326bc: 49 89 c0 mov %rax,%r8 - 4326bf: 48 8d 0c 16 lea (%rsi,%rdx,1),%rcx - 4326c3: 49 89 fa mov %rdi,%r10 - 4326c6: c5 fa 6f 69 80 vmovdqu -0x80(%rcx),%xmm5 - 4326cb: c5 fa 6f 71 90 vmovdqu -0x70(%rcx),%xmm6 - 4326d0: 48 c7 c0 80 00 00 00 mov $0x80,%rax - 4326d7: 48 83 e7 e0 and $0xffffffffffffffe0,%rdi - 4326db: 48 83 c7 20 add $0x20,%rdi - 4326df: c5 fa 6f 79 a0 vmovdqu -0x60(%rcx),%xmm7 - 4326e4: c5 7a 6f 41 b0 vmovdqu -0x50(%rcx),%xmm8 - 4326e9: 49 89 fb mov %rdi,%r11 - 4326ec: 4d 29 d3 sub %r10,%r11 - 4326ef: c5 7a 6f 49 c0 vmovdqu -0x40(%rcx),%xmm9 - 4326f4: c5 7a 6f 51 d0 vmovdqu -0x30(%rcx),%xmm10 - 4326f9: 4c 29 da sub %r11,%rdx - 4326fc: c5 7a 6f 59 e0 vmovdqu -0x20(%rcx),%xmm11 - 432701: c5 7a 6f 61 f0 vmovdqu -0x10(%rcx),%xmm12 - 432706: c5 fe 6f 26 vmovdqu (%rsi),%ymm4 - 43270a: 4c 01 de add %r11,%rsi - 43270d: 29 c2 sub %eax,%edx - 43270f: c5 fe 6f 06 vmovdqu (%rsi),%ymm0 - 432713: c5 fe 6f 4e 20 vmovdqu 0x20(%rsi),%ymm1 - 432718: c5 fe 6f 56 40 vmovdqu 0x40(%rsi),%ymm2 - 43271d: c5 fe 6f 5e 60 vmovdqu 0x60(%rsi),%ymm3 - 432722: 48 01 c6 add %rax,%rsi - 432725: c5 fd 7f 07 vmovdqa %ymm0,(%rdi) - 432729: c5 fd 7f 4f 20 vmovdqa %ymm1,0x20(%rdi) - 43272e: c5 fd 7f 57 40 vmovdqa %ymm2,0x40(%rdi) - 432733: c5 fd 7f 5f 60 vmovdqa %ymm3,0x60(%rdi) - 432738: 48 01 c7 add %rax,%rdi - 43273b: 29 c2 sub %eax,%edx - 43273d: 73 d0 jae 43270f <__memmove_avx_unaligned+0x23f> - 43273f: 01 c2 add %eax,%edx - 432741: 48 01 fa add %rdi,%rdx - 432744: c4 c1 7e 7f 22 vmovdqu %ymm4,(%r10) - 432749: c5 f8 77 vzeroupper - 43274c: c5 fa 7f 6a 80 vmovdqu %xmm5,-0x80(%rdx) - 432751: c5 fa 7f 72 90 vmovdqu %xmm6,-0x70(%rdx) - 432756: c5 fa 7f 7a a0 vmovdqu %xmm7,-0x60(%rdx) - 43275b: c5 7a 7f 42 b0 vmovdqu %xmm8,-0x50(%rdx) - 432760: c5 7a 7f 4a c0 vmovdqu %xmm9,-0x40(%rdx) - 432765: c5 7a 7f 52 d0 vmovdqu %xmm10,-0x30(%rdx) - 43276a: c5 7a 7f 5a e0 vmovdqu %xmm11,-0x20(%rdx) - 43276f: c5 7a 7f 62 f0 vmovdqu %xmm12,-0x10(%rdx) - 432774: 4c 89 c0 mov %r8,%rax - 432777: c3 retq - 432778: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 43277f: 00 - 432780: 48 8b 0d 29 89 29 00 mov 0x298929(%rip),%rcx # 6cb0b0 <__x86_shared_cache_size_half> - 432787: 48 c1 e1 03 shl $0x3,%rcx - 43278b: 48 39 ca cmp %rcx,%rdx - 43278e: 73 10 jae 4327a0 <__memmove_avx_unaligned+0x2d0> - 432790: 48 89 d1 mov %rdx,%rcx - 432793: 48 89 d1 mov %rdx,%rcx - 432796: f3 a4 rep movsb %ds:(%rsi),%es:(%rdi) - 432798: c3 retq - 432799: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4327a0: 48 8d 0c 16 lea (%rsi,%rdx,1),%rcx - 4327a4: c5 fe 6f 26 vmovdqu (%rsi),%ymm4 - 4327a8: c5 fa 6f 6c 16 80 vmovdqu -0x80(%rsi,%rdx,1),%xmm5 - 4327ae: c5 fa 6f 71 90 vmovdqu -0x70(%rcx),%xmm6 - 4327b3: c5 fa 6f 79 a0 vmovdqu -0x60(%rcx),%xmm7 - 4327b8: c5 7a 6f 41 b0 vmovdqu -0x50(%rcx),%xmm8 - 4327bd: c5 7a 6f 49 c0 vmovdqu -0x40(%rcx),%xmm9 - 4327c2: c5 7a 6f 51 d0 vmovdqu -0x30(%rcx),%xmm10 - 4327c7: c5 7a 6f 59 e0 vmovdqu -0x20(%rcx),%xmm11 - 4327cc: c5 7a 6f 61 f0 vmovdqu -0x10(%rcx),%xmm12 - 4327d1: 49 89 f8 mov %rdi,%r8 - 4327d4: 48 83 e7 e0 and $0xffffffffffffffe0,%rdi - 4327d8: 48 83 c7 20 add $0x20,%rdi - 4327dc: 49 89 fa mov %rdi,%r10 - 4327df: 4d 29 c2 sub %r8,%r10 - 4327e2: 4c 29 d2 sub %r10,%rdx - 4327e5: 4c 01 d6 add %r10,%rsi - 4327e8: 48 8d 0c 17 lea (%rdi,%rdx,1),%rcx - 4327ec: 48 83 c2 80 add $0xffffffffffffff80,%rdx - 4327f0: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) - 4327f7: 0f 18 86 80 02 00 00 prefetchnta 0x280(%rsi) - 4327fe: c5 fe 6f 06 vmovdqu (%rsi),%ymm0 - 432802: c5 fe 6f 4e 20 vmovdqu 0x20(%rsi),%ymm1 - 432807: c5 fe 6f 56 40 vmovdqu 0x40(%rsi),%ymm2 - 43280c: c5 fe 6f 5e 60 vmovdqu 0x60(%rsi),%ymm3 - 432811: 48 83 ee 80 sub $0xffffffffffffff80,%rsi - 432815: c5 fd e7 07 vmovntdq %ymm0,(%rdi) - 432819: c5 fd e7 4f 20 vmovntdq %ymm1,0x20(%rdi) - 43281e: c5 fd e7 57 40 vmovntdq %ymm2,0x40(%rdi) - 432823: c5 fd e7 5f 60 vmovntdq %ymm3,0x60(%rdi) - 432828: 48 83 ef 80 sub $0xffffffffffffff80,%rdi - 43282c: 48 83 c2 80 add $0xffffffffffffff80,%rdx - 432830: 72 be jb 4327f0 <__memmove_avx_unaligned+0x320> - 432832: 0f ae f8 sfence - 432835: c4 c1 7e 7f 20 vmovdqu %ymm4,(%r8) - 43283a: c5 f8 77 vzeroupper - 43283d: c5 fa 7f 69 80 vmovdqu %xmm5,-0x80(%rcx) - 432842: c5 fa 7f 71 90 vmovdqu %xmm6,-0x70(%rcx) - 432847: c5 fa 7f 79 a0 vmovdqu %xmm7,-0x60(%rcx) - 43284c: c5 7a 7f 41 b0 vmovdqu %xmm8,-0x50(%rcx) - 432851: c5 7a 7f 49 c0 vmovdqu %xmm9,-0x40(%rcx) - 432856: c5 7a 7f 51 d0 vmovdqu %xmm10,-0x30(%rcx) - 43285b: c5 7a 7f 59 e0 vmovdqu %xmm11,-0x20(%rcx) - 432860: c5 7a 7f 61 f0 vmovdqu %xmm12,-0x10(%rcx) - 432865: c3 retq - 432866: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43286d: 00 00 00 - 432870: 48 8b 0d 39 88 29 00 mov 0x298839(%rip),%rcx # 6cb0b0 <__x86_shared_cache_size_half> - 432877: 48 c1 e1 03 shl $0x3,%rcx - 43287b: c5 fa 6f 2e vmovdqu (%rsi),%xmm5 - 43287f: c5 fa 6f 76 10 vmovdqu 0x10(%rsi),%xmm6 - 432884: 48 01 d7 add %rdx,%rdi - 432887: c5 fa 6f 7e 20 vmovdqu 0x20(%rsi),%xmm7 - 43288c: c5 7a 6f 46 30 vmovdqu 0x30(%rsi),%xmm8 - 432891: 4c 8d 57 e0 lea -0x20(%rdi),%r10 - 432895: 49 89 fb mov %rdi,%r11 - 432898: c5 7a 6f 4e 40 vmovdqu 0x40(%rsi),%xmm9 - 43289d: c5 7a 6f 56 50 vmovdqu 0x50(%rsi),%xmm10 - 4328a2: 49 83 e3 1f and $0x1f,%r11 - 4328a6: c5 7a 6f 5e 60 vmovdqu 0x60(%rsi),%xmm11 - 4328ab: c5 7a 6f 66 70 vmovdqu 0x70(%rsi),%xmm12 - 4328b0: 4c 31 df xor %r11,%rdi - 4328b3: 48 01 d6 add %rdx,%rsi - 4328b6: c5 fe 6f 66 e0 vmovdqu -0x20(%rsi),%ymm4 - 4328bb: 4c 29 de sub %r11,%rsi - 4328be: 4c 29 da sub %r11,%rdx - 4328c1: 48 39 ca cmp %rcx,%rdx - 4328c4: 77 6a ja 432930 <__memmove_avx_unaligned+0x460> - 4328c6: 48 83 c2 80 add $0xffffffffffffff80,%rdx - 4328ca: c5 fe 6f 46 e0 vmovdqu -0x20(%rsi),%ymm0 - 4328cf: c5 fe 6f 4e c0 vmovdqu -0x40(%rsi),%ymm1 - 4328d4: c5 fe 6f 56 a0 vmovdqu -0x60(%rsi),%ymm2 - 4328d9: c5 fe 6f 5e 80 vmovdqu -0x80(%rsi),%ymm3 - 4328de: 48 8d 76 80 lea -0x80(%rsi),%rsi - 4328e2: c5 fd 7f 47 e0 vmovdqa %ymm0,-0x20(%rdi) - 4328e7: c5 fd 7f 4f c0 vmovdqa %ymm1,-0x40(%rdi) - 4328ec: c5 fd 7f 57 a0 vmovdqa %ymm2,-0x60(%rdi) - 4328f1: c5 fd 7f 5f 80 vmovdqa %ymm3,-0x80(%rdi) - 4328f6: 48 8d 7f 80 lea -0x80(%rdi),%rdi - 4328fa: 48 83 c2 80 add $0xffffffffffffff80,%rdx - 4328fe: 72 ca jb 4328ca <__memmove_avx_unaligned+0x3fa> - 432900: c4 c1 7e 7f 22 vmovdqu %ymm4,(%r10) - 432905: c5 f8 77 vzeroupper - 432908: c5 fa 7f 28 vmovdqu %xmm5,(%rax) - 43290c: c5 fa 7f 70 10 vmovdqu %xmm6,0x10(%rax) - 432911: c5 fa 7f 78 20 vmovdqu %xmm7,0x20(%rax) - 432916: c5 7a 7f 40 30 vmovdqu %xmm8,0x30(%rax) - 43291b: c5 7a 7f 48 40 vmovdqu %xmm9,0x40(%rax) - 432920: c5 7a 7f 50 50 vmovdqu %xmm10,0x50(%rax) - 432925: c5 7a 7f 58 60 vmovdqu %xmm11,0x60(%rax) - 43292a: c5 7a 7f 60 70 vmovdqu %xmm12,0x70(%rax) - 43292f: c3 retq - 432930: 48 83 c2 80 add $0xffffffffffffff80,%rdx - 432934: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) - 43293b: 0f 18 86 80 fd ff ff prefetchnta -0x280(%rsi) - 432942: c5 fe 6f 46 e0 vmovdqu -0x20(%rsi),%ymm0 - 432947: c5 fe 6f 4e c0 vmovdqu -0x40(%rsi),%ymm1 - 43294c: c5 fe 6f 56 a0 vmovdqu -0x60(%rsi),%ymm2 - 432951: c5 fe 6f 5e 80 vmovdqu -0x80(%rsi),%ymm3 - 432956: 48 8d 76 80 lea -0x80(%rsi),%rsi - 43295a: c5 fd e7 47 e0 vmovntdq %ymm0,-0x20(%rdi) - 43295f: c5 fd e7 4f c0 vmovntdq %ymm1,-0x40(%rdi) - 432964: c5 fd e7 57 a0 vmovntdq %ymm2,-0x60(%rdi) - 432969: c5 fd e7 5f 80 vmovntdq %ymm3,-0x80(%rdi) - 43296e: 48 8d 7f 80 lea -0x80(%rdi),%rdi - 432972: 48 83 c2 80 add $0xffffffffffffff80,%rdx - 432976: 72 bc jb 432934 <__memmove_avx_unaligned+0x464> - 432978: 0f ae f8 sfence - 43297b: c4 c1 7e 7f 22 vmovdqu %ymm4,(%r10) - 432980: c5 f8 77 vzeroupper - 432983: c5 fa 7f 28 vmovdqu %xmm5,(%rax) - 432987: c5 fa 7f 70 10 vmovdqu %xmm6,0x10(%rax) - 43298c: c5 fa 7f 78 20 vmovdqu %xmm7,0x20(%rax) - 432991: c5 7a 7f 40 30 vmovdqu %xmm8,0x30(%rax) - 432996: c5 7a 7f 48 40 vmovdqu %xmm9,0x40(%rax) - 43299b: c5 7a 7f 50 50 vmovdqu %xmm10,0x50(%rax) - 4329a0: c5 7a 7f 58 60 vmovdqu %xmm11,0x60(%rax) - 4329a5: c5 7a 7f 60 70 vmovdqu %xmm12,0x70(%rax) - 4329aa: c3 retq - 4329ab: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - -00000000004329b0 <__memmove_chk_ssse3_back>: - 4329b0: 48 39 d1 cmp %rdx,%rcx - 4329b3: 0f 82 f7 00 01 00 jb 442ab0 <__chk_fail> - 4329b9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - -00000000004329c0 <__memmove_ssse3_back>: - 4329c0: 48 89 f8 mov %rdi,%rax - 4329c3: 48 39 f7 cmp %rsi,%rdi - 4329c6: 72 26 jb 4329ee <__memmove_ssse3_back+0x2e> - 4329c8: 0f 84 70 24 00 00 je 434e3e <__memmove_ssse3_back+0x247e> - 4329ce: 48 81 fa 90 00 00 00 cmp $0x90,%rdx - 4329d5: 0f 83 95 00 00 00 jae 432a70 <__memmove_ssse3_back+0xb0> - 4329db: 4c 8d 1d 8e 0b 07 00 lea 0x70b8e(%rip),%r11 # 4a3570 - 4329e2: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 4329e6: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 4329ea: ff e2 jmpq *%rdx - 4329ec: 0f 0b ud2 - 4329ee: 48 81 fa 90 00 00 00 cmp $0x90,%rdx - 4329f5: 73 19 jae 432a10 <__memmove_ssse3_back+0x50> - 4329f7: 48 01 d6 add %rdx,%rsi - 4329fa: 48 01 d7 add %rdx,%rdi - 4329fd: 4c 8d 1d ac 0d 07 00 lea 0x70dac(%rip),%r11 # 4a37b0 - 432a04: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 432a08: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 432a0c: ff e2 jmpq *%rdx - 432a0e: 0f 0b ud2 - 432a10: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 432a14: 49 89 f8 mov %rdi,%r8 - 432a17: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi - 432a1b: 48 83 c7 10 add $0x10,%rdi - 432a1f: 49 89 f9 mov %rdi,%r9 - 432a22: 4d 29 c1 sub %r8,%r9 - 432a25: 4c 29 ca sub %r9,%rdx - 432a28: 4c 01 ce add %r9,%rsi - 432a2b: 49 89 f1 mov %rsi,%r9 - 432a2e: 49 83 e1 0f and $0xf,%r9 - 432a32: 0f 84 98 00 00 00 je 432ad0 <__memmove_ssse3_back+0x110> - 432a38: 48 8b 0d 89 86 29 00 mov 0x298689(%rip),%rcx # 6cb0c8 <__x86_data_cache_size> - 432a3f: 48 39 ca cmp %rcx,%rdx - 432a42: 0f 83 28 18 00 00 jae 434270 <__memmove_ssse3_back+0x18b0> - 432a48: 4c 8d 1d a1 0f 07 00 lea 0x70fa1(%rip),%r11 # 4a39f0 - 432a4f: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 432a56: 4f 63 0c 8b movslq (%r11,%r9,4),%r9 - 432a5a: 4d 01 d9 add %r11,%r9 - 432a5d: 41 ff e1 jmpq *%r9 - 432a60: 0f 0b ud2 - 432a62: 0f 1f 40 00 nopl 0x0(%rax) - 432a66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 432a6d: 00 00 00 - 432a70: 48 8b 0d 51 86 29 00 mov 0x298651(%rip),%rcx # 6cb0c8 <__x86_data_cache_size> - 432a77: 48 d1 e1 shl %rcx - 432a7a: 48 39 ca cmp %rcx,%rdx - 432a7d: 0f 87 9d 19 00 00 ja 434420 <__memmove_ssse3_back+0x1a60> - 432a83: 48 01 d7 add %rdx,%rdi - 432a86: 48 01 d6 add %rdx,%rsi - 432a89: f3 0f 6f 46 f0 movdqu -0x10(%rsi),%xmm0 - 432a8e: 4c 8d 47 f0 lea -0x10(%rdi),%r8 - 432a92: 49 89 f9 mov %rdi,%r9 - 432a95: 49 83 e1 0f and $0xf,%r9 - 432a99: 4c 31 cf xor %r9,%rdi - 432a9c: 4c 29 ce sub %r9,%rsi - 432a9f: 4c 29 ca sub %r9,%rdx - 432aa2: 49 89 f1 mov %rsi,%r9 - 432aa5: 49 83 e1 0f and $0xf,%r9 - 432aa9: 0f 84 c1 00 00 00 je 432b70 <__memmove_ssse3_back+0x1b0> - 432aaf: 4c 8d 1d 7a 0f 07 00 lea 0x70f7a(%rip),%r11 # 4a3a30 - 432ab6: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 432abd: 4f 63 0c 8b movslq (%r11,%r9,4),%r9 - 432ac1: 4d 01 d9 add %r11,%r9 - 432ac4: 41 ff e1 jmpq *%r9 - 432ac7: 0f 0b ud2 - 432ac9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 432ad0: 49 89 d1 mov %rdx,%r9 - 432ad3: 49 c1 e9 08 shr $0x8,%r9 - 432ad7: 49 01 d1 add %rdx,%r9 - 432ada: 4c 3b 0d ef 85 29 00 cmp 0x2985ef(%rip),%r9 # 6cb0d0 <__x86_data_cache_size_half> - 432ae1: 0f 83 89 17 00 00 jae 434270 <__memmove_ssse3_back+0x18b0> - 432ae7: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 432aee: 66 90 xchg %ax,%ax - 432af0: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 432af4: 66 0f 7f 0f movdqa %xmm1,(%rdi) - 432af8: 0f 28 56 10 movaps 0x10(%rsi),%xmm2 - 432afc: 0f 29 57 10 movaps %xmm2,0x10(%rdi) - 432b00: 0f 28 5e 20 movaps 0x20(%rsi),%xmm3 - 432b04: 0f 29 5f 20 movaps %xmm3,0x20(%rdi) - 432b08: 0f 28 66 30 movaps 0x30(%rsi),%xmm4 - 432b0c: 0f 29 67 30 movaps %xmm4,0x30(%rdi) - 432b10: 0f 28 4e 40 movaps 0x40(%rsi),%xmm1 - 432b14: 0f 29 4f 40 movaps %xmm1,0x40(%rdi) - 432b18: 0f 28 56 50 movaps 0x50(%rsi),%xmm2 - 432b1c: 0f 29 57 50 movaps %xmm2,0x50(%rdi) - 432b20: 0f 28 5e 60 movaps 0x60(%rsi),%xmm3 - 432b24: 0f 29 5f 60 movaps %xmm3,0x60(%rdi) - 432b28: 0f 28 66 70 movaps 0x70(%rsi),%xmm4 - 432b2c: 0f 29 67 70 movaps %xmm4,0x70(%rdi) - 432b30: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 432b37: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi - 432b3e: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi - 432b45: 73 a9 jae 432af0 <__memmove_ssse3_back+0x130> - 432b47: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 432b4c: 48 81 c2 80 00 00 00 add $0x80,%rdx - 432b53: 48 01 d6 add %rdx,%rsi - 432b56: 48 01 d7 add %rdx,%rdi - 432b59: 4c 8d 1d 50 0c 07 00 lea 0x70c50(%rip),%r11 # 4a37b0 - 432b60: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 432b64: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 432b68: ff e2 jmpq *%rdx - 432b6a: 0f 0b ud2 - 432b6c: 0f 1f 40 00 nopl 0x0(%rax) - 432b70: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 432b77: 0f 28 4e f0 movaps -0x10(%rsi),%xmm1 - 432b7b: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 432b7f: 0f 28 56 e0 movaps -0x20(%rsi),%xmm2 - 432b83: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 432b87: 0f 28 5e d0 movaps -0x30(%rsi),%xmm3 - 432b8b: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 432b8f: 0f 28 66 c0 movaps -0x40(%rsi),%xmm4 - 432b93: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) - 432b97: 0f 28 6e b0 movaps -0x50(%rsi),%xmm5 - 432b9b: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) - 432b9f: 0f 28 6e a0 movaps -0x60(%rsi),%xmm5 - 432ba3: 0f 29 6f a0 movaps %xmm5,-0x60(%rdi) - 432ba7: 0f 28 6e 90 movaps -0x70(%rsi),%xmm5 - 432bab: 0f 29 6f 90 movaps %xmm5,-0x70(%rdi) - 432baf: 0f 28 6e 80 movaps -0x80(%rsi),%xmm5 - 432bb3: 0f 29 6f 80 movaps %xmm5,-0x80(%rdi) - 432bb7: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 432bbe: 48 8d 7f 80 lea -0x80(%rdi),%rdi - 432bc2: 48 8d 76 80 lea -0x80(%rsi),%rsi - 432bc6: 73 af jae 432b77 <__memmove_ssse3_back+0x1b7> - 432bc8: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 432bcd: 48 81 c2 80 00 00 00 add $0x80,%rdx - 432bd4: 48 29 d7 sub %rdx,%rdi - 432bd7: 48 29 d6 sub %rdx,%rsi - 432bda: 4c 8d 1d 8f 09 07 00 lea 0x7098f(%rip),%r11 # 4a3570 - 432be1: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 432be5: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 432be9: ff e2 jmpq *%rdx - 432beb: 0f 0b ud2 - 432bed: 0f 1f 00 nopl (%rax) - 432bf0: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 432bf7: 0f 28 4e ff movaps -0x1(%rsi),%xmm1 - 432bfb: 0f 28 56 0f movaps 0xf(%rsi),%xmm2 - 432bff: 0f 28 5e 1f movaps 0x1f(%rsi),%xmm3 - 432c03: 0f 28 66 2f movaps 0x2f(%rsi),%xmm4 - 432c07: 0f 28 6e 3f movaps 0x3f(%rsi),%xmm5 - 432c0b: 0f 28 76 4f movaps 0x4f(%rsi),%xmm6 - 432c0f: 0f 28 7e 5f movaps 0x5f(%rsi),%xmm7 - 432c13: 44 0f 28 46 6f movaps 0x6f(%rsi),%xmm8 - 432c18: 44 0f 28 4e 7f movaps 0x7f(%rsi),%xmm9 - 432c1d: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi - 432c24: 66 45 0f 3a 0f c8 01 palignr $0x1,%xmm8,%xmm9 - 432c2b: 44 0f 29 4f 70 movaps %xmm9,0x70(%rdi) - 432c30: 66 44 0f 3a 0f c7 01 palignr $0x1,%xmm7,%xmm8 - 432c37: 44 0f 29 47 60 movaps %xmm8,0x60(%rdi) - 432c3c: 66 0f 3a 0f fe 01 palignr $0x1,%xmm6,%xmm7 - 432c42: 0f 29 7f 50 movaps %xmm7,0x50(%rdi) - 432c46: 66 0f 3a 0f f5 01 palignr $0x1,%xmm5,%xmm6 - 432c4c: 0f 29 77 40 movaps %xmm6,0x40(%rdi) - 432c50: 66 0f 3a 0f ec 01 palignr $0x1,%xmm4,%xmm5 - 432c56: 0f 29 6f 30 movaps %xmm5,0x30(%rdi) - 432c5a: 66 0f 3a 0f e3 01 palignr $0x1,%xmm3,%xmm4 - 432c60: 0f 29 67 20 movaps %xmm4,0x20(%rdi) - 432c64: 66 0f 3a 0f da 01 palignr $0x1,%xmm2,%xmm3 - 432c6a: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) - 432c6e: 66 0f 3a 0f d1 01 palignr $0x1,%xmm1,%xmm2 - 432c74: 0f 29 17 movaps %xmm2,(%rdi) - 432c77: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi - 432c7e: 0f 83 6c ff ff ff jae 432bf0 <__memmove_ssse3_back+0x230> - 432c84: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 432c89: 48 81 c2 80 00 00 00 add $0x80,%rdx - 432c90: 48 01 d7 add %rdx,%rdi - 432c93: 48 01 d6 add %rdx,%rsi - 432c96: 4c 8d 1d 13 0b 07 00 lea 0x70b13(%rip),%r11 # 4a37b0 - 432c9d: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 432ca1: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 432ca5: ff e2 jmpq *%rdx - 432ca7: 0f 0b ud2 - 432ca9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 432cb0: 0f 28 4e ff movaps -0x1(%rsi),%xmm1 - 432cb4: 0f 28 56 ef movaps -0x11(%rsi),%xmm2 - 432cb8: 66 0f 3a 0f ca 01 palignr $0x1,%xmm2,%xmm1 - 432cbe: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 432cc2: 0f 28 5e df movaps -0x21(%rsi),%xmm3 - 432cc6: 66 0f 3a 0f d3 01 palignr $0x1,%xmm3,%xmm2 - 432ccc: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 432cd0: 0f 28 66 cf movaps -0x31(%rsi),%xmm4 - 432cd4: 66 0f 3a 0f dc 01 palignr $0x1,%xmm4,%xmm3 - 432cda: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 432cde: 0f 28 6e bf movaps -0x41(%rsi),%xmm5 - 432ce2: 66 0f 3a 0f e5 01 palignr $0x1,%xmm5,%xmm4 - 432ce8: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) - 432cec: 0f 28 76 af movaps -0x51(%rsi),%xmm6 - 432cf0: 66 0f 3a 0f ee 01 palignr $0x1,%xmm6,%xmm5 - 432cf6: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) - 432cfa: 0f 28 7e 9f movaps -0x61(%rsi),%xmm7 - 432cfe: 66 0f 3a 0f f7 01 palignr $0x1,%xmm7,%xmm6 - 432d04: 0f 29 77 a0 movaps %xmm6,-0x60(%rdi) - 432d08: 44 0f 28 46 8f movaps -0x71(%rsi),%xmm8 - 432d0d: 66 41 0f 3a 0f f8 01 palignr $0x1,%xmm8,%xmm7 - 432d14: 0f 29 7f 90 movaps %xmm7,-0x70(%rdi) - 432d18: 44 0f 28 8e 7f ff ff movaps -0x81(%rsi),%xmm9 - 432d1f: ff - 432d20: 66 45 0f 3a 0f c1 01 palignr $0x1,%xmm9,%xmm8 - 432d27: 44 0f 29 47 80 movaps %xmm8,-0x80(%rdi) - 432d2c: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 432d33: 48 8d 7f 80 lea -0x80(%rdi),%rdi - 432d37: 48 8d 76 80 lea -0x80(%rsi),%rsi - 432d3b: 0f 83 6f ff ff ff jae 432cb0 <__memmove_ssse3_back+0x2f0> - 432d41: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 432d46: 48 81 c2 80 00 00 00 add $0x80,%rdx - 432d4d: 48 29 d7 sub %rdx,%rdi - 432d50: 48 29 d6 sub %rdx,%rsi - 432d53: 4c 8d 1d 16 08 07 00 lea 0x70816(%rip),%r11 # 4a3570 - 432d5a: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 432d5e: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 432d62: ff e2 jmpq *%rdx - 432d64: 0f 0b ud2 - 432d66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 432d6d: 00 00 00 - 432d70: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 432d77: 0f 28 4e fe movaps -0x2(%rsi),%xmm1 - 432d7b: 0f 28 56 0e movaps 0xe(%rsi),%xmm2 - 432d7f: 0f 28 5e 1e movaps 0x1e(%rsi),%xmm3 - 432d83: 0f 28 66 2e movaps 0x2e(%rsi),%xmm4 - 432d87: 0f 28 6e 3e movaps 0x3e(%rsi),%xmm5 - 432d8b: 0f 28 76 4e movaps 0x4e(%rsi),%xmm6 - 432d8f: 0f 28 7e 5e movaps 0x5e(%rsi),%xmm7 - 432d93: 44 0f 28 46 6e movaps 0x6e(%rsi),%xmm8 - 432d98: 44 0f 28 4e 7e movaps 0x7e(%rsi),%xmm9 - 432d9d: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi - 432da4: 66 45 0f 3a 0f c8 02 palignr $0x2,%xmm8,%xmm9 - 432dab: 44 0f 29 4f 70 movaps %xmm9,0x70(%rdi) - 432db0: 66 44 0f 3a 0f c7 02 palignr $0x2,%xmm7,%xmm8 - 432db7: 44 0f 29 47 60 movaps %xmm8,0x60(%rdi) - 432dbc: 66 0f 3a 0f fe 02 palignr $0x2,%xmm6,%xmm7 - 432dc2: 0f 29 7f 50 movaps %xmm7,0x50(%rdi) - 432dc6: 66 0f 3a 0f f5 02 palignr $0x2,%xmm5,%xmm6 - 432dcc: 0f 29 77 40 movaps %xmm6,0x40(%rdi) - 432dd0: 66 0f 3a 0f ec 02 palignr $0x2,%xmm4,%xmm5 - 432dd6: 0f 29 6f 30 movaps %xmm5,0x30(%rdi) - 432dda: 66 0f 3a 0f e3 02 palignr $0x2,%xmm3,%xmm4 - 432de0: 0f 29 67 20 movaps %xmm4,0x20(%rdi) - 432de4: 66 0f 3a 0f da 02 palignr $0x2,%xmm2,%xmm3 - 432dea: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) - 432dee: 66 0f 3a 0f d1 02 palignr $0x2,%xmm1,%xmm2 - 432df4: 0f 29 17 movaps %xmm2,(%rdi) - 432df7: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi - 432dfe: 0f 83 6c ff ff ff jae 432d70 <__memmove_ssse3_back+0x3b0> - 432e04: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 432e09: 48 81 c2 80 00 00 00 add $0x80,%rdx - 432e10: 48 01 d7 add %rdx,%rdi - 432e13: 48 01 d6 add %rdx,%rsi - 432e16: 4c 8d 1d 93 09 07 00 lea 0x70993(%rip),%r11 # 4a37b0 - 432e1d: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 432e21: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 432e25: ff e2 jmpq *%rdx - 432e27: 0f 0b ud2 - 432e29: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 432e30: 0f 28 4e fe movaps -0x2(%rsi),%xmm1 - 432e34: 0f 28 56 ee movaps -0x12(%rsi),%xmm2 - 432e38: 66 0f 3a 0f ca 02 palignr $0x2,%xmm2,%xmm1 - 432e3e: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 432e42: 0f 28 5e de movaps -0x22(%rsi),%xmm3 - 432e46: 66 0f 3a 0f d3 02 palignr $0x2,%xmm3,%xmm2 - 432e4c: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 432e50: 0f 28 66 ce movaps -0x32(%rsi),%xmm4 - 432e54: 66 0f 3a 0f dc 02 palignr $0x2,%xmm4,%xmm3 - 432e5a: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 432e5e: 0f 28 6e be movaps -0x42(%rsi),%xmm5 - 432e62: 66 0f 3a 0f e5 02 palignr $0x2,%xmm5,%xmm4 - 432e68: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) - 432e6c: 0f 28 76 ae movaps -0x52(%rsi),%xmm6 - 432e70: 66 0f 3a 0f ee 02 palignr $0x2,%xmm6,%xmm5 - 432e76: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) - 432e7a: 0f 28 7e 9e movaps -0x62(%rsi),%xmm7 - 432e7e: 66 0f 3a 0f f7 02 palignr $0x2,%xmm7,%xmm6 - 432e84: 0f 29 77 a0 movaps %xmm6,-0x60(%rdi) - 432e88: 44 0f 28 46 8e movaps -0x72(%rsi),%xmm8 - 432e8d: 66 41 0f 3a 0f f8 02 palignr $0x2,%xmm8,%xmm7 - 432e94: 0f 29 7f 90 movaps %xmm7,-0x70(%rdi) - 432e98: 44 0f 28 8e 7e ff ff movaps -0x82(%rsi),%xmm9 - 432e9f: ff - 432ea0: 66 45 0f 3a 0f c1 02 palignr $0x2,%xmm9,%xmm8 - 432ea7: 44 0f 29 47 80 movaps %xmm8,-0x80(%rdi) - 432eac: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 432eb3: 48 8d 7f 80 lea -0x80(%rdi),%rdi - 432eb7: 48 8d 76 80 lea -0x80(%rsi),%rsi - 432ebb: 0f 83 6f ff ff ff jae 432e30 <__memmove_ssse3_back+0x470> - 432ec1: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 432ec6: 48 81 c2 80 00 00 00 add $0x80,%rdx - 432ecd: 48 29 d7 sub %rdx,%rdi - 432ed0: 48 29 d6 sub %rdx,%rsi - 432ed3: 4c 8d 1d 96 06 07 00 lea 0x70696(%rip),%r11 # 4a3570 - 432eda: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 432ede: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 432ee2: ff e2 jmpq *%rdx - 432ee4: 0f 0b ud2 - 432ee6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 432eed: 00 00 00 - 432ef0: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 432ef7: 0f 28 4e fd movaps -0x3(%rsi),%xmm1 - 432efb: 0f 28 56 0d movaps 0xd(%rsi),%xmm2 - 432eff: 0f 28 5e 1d movaps 0x1d(%rsi),%xmm3 - 432f03: 0f 28 66 2d movaps 0x2d(%rsi),%xmm4 - 432f07: 0f 28 6e 3d movaps 0x3d(%rsi),%xmm5 - 432f0b: 0f 28 76 4d movaps 0x4d(%rsi),%xmm6 - 432f0f: 0f 28 7e 5d movaps 0x5d(%rsi),%xmm7 - 432f13: 44 0f 28 46 6d movaps 0x6d(%rsi),%xmm8 - 432f18: 44 0f 28 4e 7d movaps 0x7d(%rsi),%xmm9 - 432f1d: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi - 432f24: 66 45 0f 3a 0f c8 03 palignr $0x3,%xmm8,%xmm9 - 432f2b: 44 0f 29 4f 70 movaps %xmm9,0x70(%rdi) - 432f30: 66 44 0f 3a 0f c7 03 palignr $0x3,%xmm7,%xmm8 - 432f37: 44 0f 29 47 60 movaps %xmm8,0x60(%rdi) - 432f3c: 66 0f 3a 0f fe 03 palignr $0x3,%xmm6,%xmm7 - 432f42: 0f 29 7f 50 movaps %xmm7,0x50(%rdi) - 432f46: 66 0f 3a 0f f5 03 palignr $0x3,%xmm5,%xmm6 - 432f4c: 0f 29 77 40 movaps %xmm6,0x40(%rdi) - 432f50: 66 0f 3a 0f ec 03 palignr $0x3,%xmm4,%xmm5 - 432f56: 0f 29 6f 30 movaps %xmm5,0x30(%rdi) - 432f5a: 66 0f 3a 0f e3 03 palignr $0x3,%xmm3,%xmm4 - 432f60: 0f 29 67 20 movaps %xmm4,0x20(%rdi) - 432f64: 66 0f 3a 0f da 03 palignr $0x3,%xmm2,%xmm3 - 432f6a: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) - 432f6e: 66 0f 3a 0f d1 03 palignr $0x3,%xmm1,%xmm2 - 432f74: 0f 29 17 movaps %xmm2,(%rdi) - 432f77: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi - 432f7e: 0f 83 6c ff ff ff jae 432ef0 <__memmove_ssse3_back+0x530> - 432f84: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 432f89: 48 81 c2 80 00 00 00 add $0x80,%rdx - 432f90: 48 01 d7 add %rdx,%rdi - 432f93: 48 01 d6 add %rdx,%rsi - 432f96: 4c 8d 1d 13 08 07 00 lea 0x70813(%rip),%r11 # 4a37b0 - 432f9d: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 432fa1: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 432fa5: ff e2 jmpq *%rdx - 432fa7: 0f 0b ud2 - 432fa9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 432fb0: 0f 28 4e fd movaps -0x3(%rsi),%xmm1 - 432fb4: 0f 28 56 ed movaps -0x13(%rsi),%xmm2 - 432fb8: 66 0f 3a 0f ca 03 palignr $0x3,%xmm2,%xmm1 - 432fbe: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 432fc2: 0f 28 5e dd movaps -0x23(%rsi),%xmm3 - 432fc6: 66 0f 3a 0f d3 03 palignr $0x3,%xmm3,%xmm2 - 432fcc: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 432fd0: 0f 28 66 cd movaps -0x33(%rsi),%xmm4 - 432fd4: 66 0f 3a 0f dc 03 palignr $0x3,%xmm4,%xmm3 - 432fda: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 432fde: 0f 28 6e bd movaps -0x43(%rsi),%xmm5 - 432fe2: 66 0f 3a 0f e5 03 palignr $0x3,%xmm5,%xmm4 - 432fe8: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) - 432fec: 0f 28 76 ad movaps -0x53(%rsi),%xmm6 - 432ff0: 66 0f 3a 0f ee 03 palignr $0x3,%xmm6,%xmm5 - 432ff6: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) - 432ffa: 0f 28 7e 9d movaps -0x63(%rsi),%xmm7 - 432ffe: 66 0f 3a 0f f7 03 palignr $0x3,%xmm7,%xmm6 - 433004: 0f 29 77 a0 movaps %xmm6,-0x60(%rdi) - 433008: 44 0f 28 46 8d movaps -0x73(%rsi),%xmm8 - 43300d: 66 41 0f 3a 0f f8 03 palignr $0x3,%xmm8,%xmm7 - 433014: 0f 29 7f 90 movaps %xmm7,-0x70(%rdi) - 433018: 44 0f 28 8e 7d ff ff movaps -0x83(%rsi),%xmm9 - 43301f: ff - 433020: 66 45 0f 3a 0f c1 03 palignr $0x3,%xmm9,%xmm8 - 433027: 44 0f 29 47 80 movaps %xmm8,-0x80(%rdi) - 43302c: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 433033: 48 8d 7f 80 lea -0x80(%rdi),%rdi - 433037: 48 8d 76 80 lea -0x80(%rsi),%rsi - 43303b: 0f 83 6f ff ff ff jae 432fb0 <__memmove_ssse3_back+0x5f0> - 433041: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 433046: 48 81 c2 80 00 00 00 add $0x80,%rdx - 43304d: 48 29 d7 sub %rdx,%rdi - 433050: 48 29 d6 sub %rdx,%rsi - 433053: 4c 8d 1d 16 05 07 00 lea 0x70516(%rip),%r11 # 4a3570 - 43305a: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 43305e: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 433062: ff e2 jmpq *%rdx - 433064: 0f 0b ud2 - 433066: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43306d: 00 00 00 - 433070: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 433077: 0f 28 4e fc movaps -0x4(%rsi),%xmm1 - 43307b: 0f 28 56 0c movaps 0xc(%rsi),%xmm2 - 43307f: 0f 28 5e 1c movaps 0x1c(%rsi),%xmm3 - 433083: 0f 28 66 2c movaps 0x2c(%rsi),%xmm4 - 433087: 0f 28 6e 3c movaps 0x3c(%rsi),%xmm5 - 43308b: 0f 28 76 4c movaps 0x4c(%rsi),%xmm6 - 43308f: 0f 28 7e 5c movaps 0x5c(%rsi),%xmm7 - 433093: 44 0f 28 46 6c movaps 0x6c(%rsi),%xmm8 - 433098: 44 0f 28 4e 7c movaps 0x7c(%rsi),%xmm9 - 43309d: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi - 4330a4: 66 45 0f 3a 0f c8 04 palignr $0x4,%xmm8,%xmm9 - 4330ab: 44 0f 29 4f 70 movaps %xmm9,0x70(%rdi) - 4330b0: 66 44 0f 3a 0f c7 04 palignr $0x4,%xmm7,%xmm8 - 4330b7: 44 0f 29 47 60 movaps %xmm8,0x60(%rdi) - 4330bc: 66 0f 3a 0f fe 04 palignr $0x4,%xmm6,%xmm7 - 4330c2: 0f 29 7f 50 movaps %xmm7,0x50(%rdi) - 4330c6: 66 0f 3a 0f f5 04 palignr $0x4,%xmm5,%xmm6 - 4330cc: 0f 29 77 40 movaps %xmm6,0x40(%rdi) - 4330d0: 66 0f 3a 0f ec 04 palignr $0x4,%xmm4,%xmm5 - 4330d6: 0f 29 6f 30 movaps %xmm5,0x30(%rdi) - 4330da: 66 0f 3a 0f e3 04 palignr $0x4,%xmm3,%xmm4 - 4330e0: 0f 29 67 20 movaps %xmm4,0x20(%rdi) - 4330e4: 66 0f 3a 0f da 04 palignr $0x4,%xmm2,%xmm3 - 4330ea: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) - 4330ee: 66 0f 3a 0f d1 04 palignr $0x4,%xmm1,%xmm2 - 4330f4: 0f 29 17 movaps %xmm2,(%rdi) - 4330f7: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi - 4330fe: 0f 83 6c ff ff ff jae 433070 <__memmove_ssse3_back+0x6b0> - 433104: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 433109: 48 81 c2 80 00 00 00 add $0x80,%rdx - 433110: 48 01 d7 add %rdx,%rdi - 433113: 48 01 d6 add %rdx,%rsi - 433116: 4c 8d 1d 93 06 07 00 lea 0x70693(%rip),%r11 # 4a37b0 - 43311d: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 433121: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 433125: ff e2 jmpq *%rdx - 433127: 0f 0b ud2 - 433129: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 433130: 0f 28 4e fc movaps -0x4(%rsi),%xmm1 - 433134: 0f 28 56 ec movaps -0x14(%rsi),%xmm2 - 433138: 66 0f 3a 0f ca 04 palignr $0x4,%xmm2,%xmm1 - 43313e: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 433142: 0f 28 5e dc movaps -0x24(%rsi),%xmm3 - 433146: 66 0f 3a 0f d3 04 palignr $0x4,%xmm3,%xmm2 - 43314c: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 433150: 0f 28 66 cc movaps -0x34(%rsi),%xmm4 - 433154: 66 0f 3a 0f dc 04 palignr $0x4,%xmm4,%xmm3 - 43315a: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 43315e: 0f 28 6e bc movaps -0x44(%rsi),%xmm5 - 433162: 66 0f 3a 0f e5 04 palignr $0x4,%xmm5,%xmm4 - 433168: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) - 43316c: 0f 28 76 ac movaps -0x54(%rsi),%xmm6 - 433170: 66 0f 3a 0f ee 04 palignr $0x4,%xmm6,%xmm5 - 433176: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) - 43317a: 0f 28 7e 9c movaps -0x64(%rsi),%xmm7 - 43317e: 66 0f 3a 0f f7 04 palignr $0x4,%xmm7,%xmm6 - 433184: 0f 29 77 a0 movaps %xmm6,-0x60(%rdi) - 433188: 44 0f 28 46 8c movaps -0x74(%rsi),%xmm8 - 43318d: 66 41 0f 3a 0f f8 04 palignr $0x4,%xmm8,%xmm7 - 433194: 0f 29 7f 90 movaps %xmm7,-0x70(%rdi) - 433198: 44 0f 28 8e 7c ff ff movaps -0x84(%rsi),%xmm9 - 43319f: ff - 4331a0: 66 45 0f 3a 0f c1 04 palignr $0x4,%xmm9,%xmm8 - 4331a7: 44 0f 29 47 80 movaps %xmm8,-0x80(%rdi) - 4331ac: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 4331b3: 48 8d 7f 80 lea -0x80(%rdi),%rdi - 4331b7: 48 8d 76 80 lea -0x80(%rsi),%rsi - 4331bb: 0f 83 6f ff ff ff jae 433130 <__memmove_ssse3_back+0x770> - 4331c1: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 4331c6: 48 81 c2 80 00 00 00 add $0x80,%rdx - 4331cd: 48 29 d7 sub %rdx,%rdi - 4331d0: 48 29 d6 sub %rdx,%rsi - 4331d3: 4c 8d 1d 96 03 07 00 lea 0x70396(%rip),%r11 # 4a3570 - 4331da: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 4331de: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 4331e2: ff e2 jmpq *%rdx - 4331e4: 0f 0b ud2 - 4331e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4331ed: 00 00 00 - 4331f0: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 4331f7: 0f 28 4e fb movaps -0x5(%rsi),%xmm1 - 4331fb: 0f 28 56 0b movaps 0xb(%rsi),%xmm2 - 4331ff: 0f 28 5e 1b movaps 0x1b(%rsi),%xmm3 - 433203: 0f 28 66 2b movaps 0x2b(%rsi),%xmm4 - 433207: 0f 28 6e 3b movaps 0x3b(%rsi),%xmm5 - 43320b: 0f 28 76 4b movaps 0x4b(%rsi),%xmm6 - 43320f: 0f 28 7e 5b movaps 0x5b(%rsi),%xmm7 - 433213: 44 0f 28 46 6b movaps 0x6b(%rsi),%xmm8 - 433218: 44 0f 28 4e 7b movaps 0x7b(%rsi),%xmm9 - 43321d: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi - 433224: 66 45 0f 3a 0f c8 05 palignr $0x5,%xmm8,%xmm9 - 43322b: 44 0f 29 4f 70 movaps %xmm9,0x70(%rdi) - 433230: 66 44 0f 3a 0f c7 05 palignr $0x5,%xmm7,%xmm8 - 433237: 44 0f 29 47 60 movaps %xmm8,0x60(%rdi) - 43323c: 66 0f 3a 0f fe 05 palignr $0x5,%xmm6,%xmm7 - 433242: 0f 29 7f 50 movaps %xmm7,0x50(%rdi) - 433246: 66 0f 3a 0f f5 05 palignr $0x5,%xmm5,%xmm6 - 43324c: 0f 29 77 40 movaps %xmm6,0x40(%rdi) - 433250: 66 0f 3a 0f ec 05 palignr $0x5,%xmm4,%xmm5 - 433256: 0f 29 6f 30 movaps %xmm5,0x30(%rdi) - 43325a: 66 0f 3a 0f e3 05 palignr $0x5,%xmm3,%xmm4 - 433260: 0f 29 67 20 movaps %xmm4,0x20(%rdi) - 433264: 66 0f 3a 0f da 05 palignr $0x5,%xmm2,%xmm3 - 43326a: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) - 43326e: 66 0f 3a 0f d1 05 palignr $0x5,%xmm1,%xmm2 - 433274: 0f 29 17 movaps %xmm2,(%rdi) - 433277: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi - 43327e: 0f 83 6c ff ff ff jae 4331f0 <__memmove_ssse3_back+0x830> - 433284: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 433289: 48 81 c2 80 00 00 00 add $0x80,%rdx - 433290: 48 01 d7 add %rdx,%rdi - 433293: 48 01 d6 add %rdx,%rsi - 433296: 4c 8d 1d 13 05 07 00 lea 0x70513(%rip),%r11 # 4a37b0 - 43329d: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 4332a1: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 4332a5: ff e2 jmpq *%rdx - 4332a7: 0f 0b ud2 - 4332a9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4332b0: 0f 28 4e fb movaps -0x5(%rsi),%xmm1 - 4332b4: 0f 28 56 eb movaps -0x15(%rsi),%xmm2 - 4332b8: 66 0f 3a 0f ca 05 palignr $0x5,%xmm2,%xmm1 - 4332be: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 4332c2: 0f 28 5e db movaps -0x25(%rsi),%xmm3 - 4332c6: 66 0f 3a 0f d3 05 palignr $0x5,%xmm3,%xmm2 - 4332cc: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 4332d0: 0f 28 66 cb movaps -0x35(%rsi),%xmm4 - 4332d4: 66 0f 3a 0f dc 05 palignr $0x5,%xmm4,%xmm3 - 4332da: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 4332de: 0f 28 6e bb movaps -0x45(%rsi),%xmm5 - 4332e2: 66 0f 3a 0f e5 05 palignr $0x5,%xmm5,%xmm4 - 4332e8: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) - 4332ec: 0f 28 76 ab movaps -0x55(%rsi),%xmm6 - 4332f0: 66 0f 3a 0f ee 05 palignr $0x5,%xmm6,%xmm5 - 4332f6: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) - 4332fa: 0f 28 7e 9b movaps -0x65(%rsi),%xmm7 - 4332fe: 66 0f 3a 0f f7 05 palignr $0x5,%xmm7,%xmm6 - 433304: 0f 29 77 a0 movaps %xmm6,-0x60(%rdi) - 433308: 44 0f 28 46 8b movaps -0x75(%rsi),%xmm8 - 43330d: 66 41 0f 3a 0f f8 05 palignr $0x5,%xmm8,%xmm7 - 433314: 0f 29 7f 90 movaps %xmm7,-0x70(%rdi) - 433318: 44 0f 28 8e 7b ff ff movaps -0x85(%rsi),%xmm9 - 43331f: ff - 433320: 66 45 0f 3a 0f c1 05 palignr $0x5,%xmm9,%xmm8 - 433327: 44 0f 29 47 80 movaps %xmm8,-0x80(%rdi) - 43332c: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 433333: 48 8d 7f 80 lea -0x80(%rdi),%rdi - 433337: 48 8d 76 80 lea -0x80(%rsi),%rsi - 43333b: 0f 83 6f ff ff ff jae 4332b0 <__memmove_ssse3_back+0x8f0> - 433341: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 433346: 48 81 c2 80 00 00 00 add $0x80,%rdx - 43334d: 48 29 d7 sub %rdx,%rdi - 433350: 48 29 d6 sub %rdx,%rsi - 433353: 4c 8d 1d 16 02 07 00 lea 0x70216(%rip),%r11 # 4a3570 - 43335a: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 43335e: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 433362: ff e2 jmpq *%rdx - 433364: 0f 0b ud2 - 433366: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43336d: 00 00 00 - 433370: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 433377: 0f 28 4e fa movaps -0x6(%rsi),%xmm1 - 43337b: 0f 28 56 0a movaps 0xa(%rsi),%xmm2 - 43337f: 0f 28 5e 1a movaps 0x1a(%rsi),%xmm3 - 433383: 0f 28 66 2a movaps 0x2a(%rsi),%xmm4 - 433387: 0f 28 6e 3a movaps 0x3a(%rsi),%xmm5 - 43338b: 0f 28 76 4a movaps 0x4a(%rsi),%xmm6 - 43338f: 0f 28 7e 5a movaps 0x5a(%rsi),%xmm7 - 433393: 44 0f 28 46 6a movaps 0x6a(%rsi),%xmm8 - 433398: 44 0f 28 4e 7a movaps 0x7a(%rsi),%xmm9 - 43339d: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi - 4333a4: 66 45 0f 3a 0f c8 06 palignr $0x6,%xmm8,%xmm9 - 4333ab: 44 0f 29 4f 70 movaps %xmm9,0x70(%rdi) - 4333b0: 66 44 0f 3a 0f c7 06 palignr $0x6,%xmm7,%xmm8 - 4333b7: 44 0f 29 47 60 movaps %xmm8,0x60(%rdi) - 4333bc: 66 0f 3a 0f fe 06 palignr $0x6,%xmm6,%xmm7 - 4333c2: 0f 29 7f 50 movaps %xmm7,0x50(%rdi) - 4333c6: 66 0f 3a 0f f5 06 palignr $0x6,%xmm5,%xmm6 - 4333cc: 0f 29 77 40 movaps %xmm6,0x40(%rdi) - 4333d0: 66 0f 3a 0f ec 06 palignr $0x6,%xmm4,%xmm5 - 4333d6: 0f 29 6f 30 movaps %xmm5,0x30(%rdi) - 4333da: 66 0f 3a 0f e3 06 palignr $0x6,%xmm3,%xmm4 - 4333e0: 0f 29 67 20 movaps %xmm4,0x20(%rdi) - 4333e4: 66 0f 3a 0f da 06 palignr $0x6,%xmm2,%xmm3 - 4333ea: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) - 4333ee: 66 0f 3a 0f d1 06 palignr $0x6,%xmm1,%xmm2 - 4333f4: 0f 29 17 movaps %xmm2,(%rdi) - 4333f7: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi - 4333fe: 0f 83 6c ff ff ff jae 433370 <__memmove_ssse3_back+0x9b0> - 433404: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 433409: 48 81 c2 80 00 00 00 add $0x80,%rdx - 433410: 48 01 d7 add %rdx,%rdi - 433413: 48 01 d6 add %rdx,%rsi - 433416: 4c 8d 1d 93 03 07 00 lea 0x70393(%rip),%r11 # 4a37b0 - 43341d: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 433421: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 433425: ff e2 jmpq *%rdx - 433427: 0f 0b ud2 - 433429: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 433430: 0f 28 4e fa movaps -0x6(%rsi),%xmm1 - 433434: 0f 28 56 ea movaps -0x16(%rsi),%xmm2 - 433438: 66 0f 3a 0f ca 06 palignr $0x6,%xmm2,%xmm1 - 43343e: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 433442: 0f 28 5e da movaps -0x26(%rsi),%xmm3 - 433446: 66 0f 3a 0f d3 06 palignr $0x6,%xmm3,%xmm2 - 43344c: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 433450: 0f 28 66 ca movaps -0x36(%rsi),%xmm4 - 433454: 66 0f 3a 0f dc 06 palignr $0x6,%xmm4,%xmm3 - 43345a: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 43345e: 0f 28 6e ba movaps -0x46(%rsi),%xmm5 - 433462: 66 0f 3a 0f e5 06 palignr $0x6,%xmm5,%xmm4 - 433468: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) - 43346c: 0f 28 76 aa movaps -0x56(%rsi),%xmm6 - 433470: 66 0f 3a 0f ee 06 palignr $0x6,%xmm6,%xmm5 - 433476: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) - 43347a: 0f 28 7e 9a movaps -0x66(%rsi),%xmm7 - 43347e: 66 0f 3a 0f f7 06 palignr $0x6,%xmm7,%xmm6 - 433484: 0f 29 77 a0 movaps %xmm6,-0x60(%rdi) - 433488: 44 0f 28 46 8a movaps -0x76(%rsi),%xmm8 - 43348d: 66 41 0f 3a 0f f8 06 palignr $0x6,%xmm8,%xmm7 - 433494: 0f 29 7f 90 movaps %xmm7,-0x70(%rdi) - 433498: 44 0f 28 8e 7a ff ff movaps -0x86(%rsi),%xmm9 - 43349f: ff - 4334a0: 66 45 0f 3a 0f c1 06 palignr $0x6,%xmm9,%xmm8 - 4334a7: 44 0f 29 47 80 movaps %xmm8,-0x80(%rdi) - 4334ac: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 4334b3: 48 8d 7f 80 lea -0x80(%rdi),%rdi - 4334b7: 48 8d 76 80 lea -0x80(%rsi),%rsi - 4334bb: 0f 83 6f ff ff ff jae 433430 <__memmove_ssse3_back+0xa70> - 4334c1: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 4334c6: 48 81 c2 80 00 00 00 add $0x80,%rdx - 4334cd: 48 29 d7 sub %rdx,%rdi - 4334d0: 48 29 d6 sub %rdx,%rsi - 4334d3: 4c 8d 1d 96 00 07 00 lea 0x70096(%rip),%r11 # 4a3570 - 4334da: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 4334de: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 4334e2: ff e2 jmpq *%rdx - 4334e4: 0f 0b ud2 - 4334e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4334ed: 00 00 00 - 4334f0: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 4334f7: 0f 28 4e f9 movaps -0x7(%rsi),%xmm1 - 4334fb: 0f 28 56 09 movaps 0x9(%rsi),%xmm2 - 4334ff: 0f 28 5e 19 movaps 0x19(%rsi),%xmm3 - 433503: 0f 28 66 29 movaps 0x29(%rsi),%xmm4 - 433507: 0f 28 6e 39 movaps 0x39(%rsi),%xmm5 - 43350b: 0f 28 76 49 movaps 0x49(%rsi),%xmm6 - 43350f: 0f 28 7e 59 movaps 0x59(%rsi),%xmm7 - 433513: 44 0f 28 46 69 movaps 0x69(%rsi),%xmm8 - 433518: 44 0f 28 4e 79 movaps 0x79(%rsi),%xmm9 - 43351d: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi - 433524: 66 45 0f 3a 0f c8 07 palignr $0x7,%xmm8,%xmm9 - 43352b: 44 0f 29 4f 70 movaps %xmm9,0x70(%rdi) - 433530: 66 44 0f 3a 0f c7 07 palignr $0x7,%xmm7,%xmm8 - 433537: 44 0f 29 47 60 movaps %xmm8,0x60(%rdi) - 43353c: 66 0f 3a 0f fe 07 palignr $0x7,%xmm6,%xmm7 - 433542: 0f 29 7f 50 movaps %xmm7,0x50(%rdi) - 433546: 66 0f 3a 0f f5 07 palignr $0x7,%xmm5,%xmm6 - 43354c: 0f 29 77 40 movaps %xmm6,0x40(%rdi) - 433550: 66 0f 3a 0f ec 07 palignr $0x7,%xmm4,%xmm5 - 433556: 0f 29 6f 30 movaps %xmm5,0x30(%rdi) - 43355a: 66 0f 3a 0f e3 07 palignr $0x7,%xmm3,%xmm4 - 433560: 0f 29 67 20 movaps %xmm4,0x20(%rdi) - 433564: 66 0f 3a 0f da 07 palignr $0x7,%xmm2,%xmm3 - 43356a: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) - 43356e: 66 0f 3a 0f d1 07 palignr $0x7,%xmm1,%xmm2 - 433574: 0f 29 17 movaps %xmm2,(%rdi) - 433577: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi - 43357e: 0f 83 6c ff ff ff jae 4334f0 <__memmove_ssse3_back+0xb30> - 433584: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 433589: 48 81 c2 80 00 00 00 add $0x80,%rdx - 433590: 48 01 d7 add %rdx,%rdi - 433593: 48 01 d6 add %rdx,%rsi - 433596: 4c 8d 1d 13 02 07 00 lea 0x70213(%rip),%r11 # 4a37b0 - 43359d: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 4335a1: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 4335a5: ff e2 jmpq *%rdx - 4335a7: 0f 0b ud2 - 4335a9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4335b0: 0f 28 4e f9 movaps -0x7(%rsi),%xmm1 - 4335b4: 0f 28 56 e9 movaps -0x17(%rsi),%xmm2 - 4335b8: 66 0f 3a 0f ca 07 palignr $0x7,%xmm2,%xmm1 - 4335be: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 4335c2: 0f 28 5e d9 movaps -0x27(%rsi),%xmm3 - 4335c6: 66 0f 3a 0f d3 07 palignr $0x7,%xmm3,%xmm2 - 4335cc: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 4335d0: 0f 28 66 c9 movaps -0x37(%rsi),%xmm4 - 4335d4: 66 0f 3a 0f dc 07 palignr $0x7,%xmm4,%xmm3 - 4335da: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 4335de: 0f 28 6e b9 movaps -0x47(%rsi),%xmm5 - 4335e2: 66 0f 3a 0f e5 07 palignr $0x7,%xmm5,%xmm4 - 4335e8: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) - 4335ec: 0f 28 76 a9 movaps -0x57(%rsi),%xmm6 - 4335f0: 66 0f 3a 0f ee 07 palignr $0x7,%xmm6,%xmm5 - 4335f6: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) - 4335fa: 0f 28 7e 99 movaps -0x67(%rsi),%xmm7 - 4335fe: 66 0f 3a 0f f7 07 palignr $0x7,%xmm7,%xmm6 - 433604: 0f 29 77 a0 movaps %xmm6,-0x60(%rdi) - 433608: 44 0f 28 46 89 movaps -0x77(%rsi),%xmm8 - 43360d: 66 41 0f 3a 0f f8 07 palignr $0x7,%xmm8,%xmm7 - 433614: 0f 29 7f 90 movaps %xmm7,-0x70(%rdi) - 433618: 44 0f 28 8e 79 ff ff movaps -0x87(%rsi),%xmm9 - 43361f: ff - 433620: 66 45 0f 3a 0f c1 07 palignr $0x7,%xmm9,%xmm8 - 433627: 44 0f 29 47 80 movaps %xmm8,-0x80(%rdi) - 43362c: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 433633: 48 8d 7f 80 lea -0x80(%rdi),%rdi - 433637: 48 8d 76 80 lea -0x80(%rsi),%rsi - 43363b: 0f 83 6f ff ff ff jae 4335b0 <__memmove_ssse3_back+0xbf0> - 433641: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 433646: 48 81 c2 80 00 00 00 add $0x80,%rdx - 43364d: 48 29 d7 sub %rdx,%rdi - 433650: 48 29 d6 sub %rdx,%rsi - 433653: 4c 8d 1d 16 ff 06 00 lea 0x6ff16(%rip),%r11 # 4a3570 - 43365a: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 43365e: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 433662: ff e2 jmpq *%rdx - 433664: 0f 0b ud2 - 433666: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43366d: 00 00 00 - 433670: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 433677: 0f 28 4e f8 movaps -0x8(%rsi),%xmm1 - 43367b: 0f 28 56 08 movaps 0x8(%rsi),%xmm2 - 43367f: 0f 28 5e 18 movaps 0x18(%rsi),%xmm3 - 433683: 0f 28 66 28 movaps 0x28(%rsi),%xmm4 - 433687: 0f 28 6e 38 movaps 0x38(%rsi),%xmm5 - 43368b: 0f 28 76 48 movaps 0x48(%rsi),%xmm6 - 43368f: 0f 28 7e 58 movaps 0x58(%rsi),%xmm7 - 433693: 44 0f 28 46 68 movaps 0x68(%rsi),%xmm8 - 433698: 44 0f 28 4e 78 movaps 0x78(%rsi),%xmm9 - 43369d: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi - 4336a4: 66 45 0f 3a 0f c8 08 palignr $0x8,%xmm8,%xmm9 - 4336ab: 44 0f 29 4f 70 movaps %xmm9,0x70(%rdi) - 4336b0: 66 44 0f 3a 0f c7 08 palignr $0x8,%xmm7,%xmm8 - 4336b7: 44 0f 29 47 60 movaps %xmm8,0x60(%rdi) - 4336bc: 66 0f 3a 0f fe 08 palignr $0x8,%xmm6,%xmm7 - 4336c2: 0f 29 7f 50 movaps %xmm7,0x50(%rdi) - 4336c6: 66 0f 3a 0f f5 08 palignr $0x8,%xmm5,%xmm6 - 4336cc: 0f 29 77 40 movaps %xmm6,0x40(%rdi) - 4336d0: 66 0f 3a 0f ec 08 palignr $0x8,%xmm4,%xmm5 - 4336d6: 0f 29 6f 30 movaps %xmm5,0x30(%rdi) - 4336da: 66 0f 3a 0f e3 08 palignr $0x8,%xmm3,%xmm4 - 4336e0: 0f 29 67 20 movaps %xmm4,0x20(%rdi) - 4336e4: 66 0f 3a 0f da 08 palignr $0x8,%xmm2,%xmm3 - 4336ea: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) - 4336ee: 66 0f 3a 0f d1 08 palignr $0x8,%xmm1,%xmm2 - 4336f4: 0f 29 17 movaps %xmm2,(%rdi) - 4336f7: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi - 4336fe: 0f 83 6c ff ff ff jae 433670 <__memmove_ssse3_back+0xcb0> - 433704: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 433709: 48 81 c2 80 00 00 00 add $0x80,%rdx - 433710: 48 01 d7 add %rdx,%rdi - 433713: 48 01 d6 add %rdx,%rsi - 433716: 4c 8d 1d 93 00 07 00 lea 0x70093(%rip),%r11 # 4a37b0 - 43371d: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 433721: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 433725: ff e2 jmpq *%rdx - 433727: 0f 0b ud2 - 433729: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 433730: 0f 28 4e f8 movaps -0x8(%rsi),%xmm1 - 433734: 0f 28 56 e8 movaps -0x18(%rsi),%xmm2 - 433738: 66 0f 3a 0f ca 08 palignr $0x8,%xmm2,%xmm1 - 43373e: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 433742: 0f 28 5e d8 movaps -0x28(%rsi),%xmm3 - 433746: 66 0f 3a 0f d3 08 palignr $0x8,%xmm3,%xmm2 - 43374c: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 433750: 0f 28 66 c8 movaps -0x38(%rsi),%xmm4 - 433754: 66 0f 3a 0f dc 08 palignr $0x8,%xmm4,%xmm3 - 43375a: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 43375e: 0f 28 6e b8 movaps -0x48(%rsi),%xmm5 - 433762: 66 0f 3a 0f e5 08 palignr $0x8,%xmm5,%xmm4 - 433768: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) - 43376c: 0f 28 76 a8 movaps -0x58(%rsi),%xmm6 - 433770: 66 0f 3a 0f ee 08 palignr $0x8,%xmm6,%xmm5 - 433776: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) - 43377a: 0f 28 7e 98 movaps -0x68(%rsi),%xmm7 - 43377e: 66 0f 3a 0f f7 08 palignr $0x8,%xmm7,%xmm6 - 433784: 0f 29 77 a0 movaps %xmm6,-0x60(%rdi) - 433788: 44 0f 28 46 88 movaps -0x78(%rsi),%xmm8 - 43378d: 66 41 0f 3a 0f f8 08 palignr $0x8,%xmm8,%xmm7 - 433794: 0f 29 7f 90 movaps %xmm7,-0x70(%rdi) - 433798: 44 0f 28 8e 78 ff ff movaps -0x88(%rsi),%xmm9 - 43379f: ff - 4337a0: 66 45 0f 3a 0f c1 08 palignr $0x8,%xmm9,%xmm8 - 4337a7: 44 0f 29 47 80 movaps %xmm8,-0x80(%rdi) - 4337ac: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 4337b3: 48 8d 7f 80 lea -0x80(%rdi),%rdi - 4337b7: 48 8d 76 80 lea -0x80(%rsi),%rsi - 4337bb: 0f 83 6f ff ff ff jae 433730 <__memmove_ssse3_back+0xd70> - 4337c1: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 4337c6: 48 81 c2 80 00 00 00 add $0x80,%rdx - 4337cd: 48 29 d7 sub %rdx,%rdi - 4337d0: 48 29 d6 sub %rdx,%rsi - 4337d3: 4c 8d 1d 96 fd 06 00 lea 0x6fd96(%rip),%r11 # 4a3570 - 4337da: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 4337de: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 4337e2: ff e2 jmpq *%rdx - 4337e4: 0f 0b ud2 - 4337e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4337ed: 00 00 00 - 4337f0: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 4337f7: 0f 28 4e f7 movaps -0x9(%rsi),%xmm1 - 4337fb: 0f 28 56 07 movaps 0x7(%rsi),%xmm2 - 4337ff: 0f 28 5e 17 movaps 0x17(%rsi),%xmm3 - 433803: 0f 28 66 27 movaps 0x27(%rsi),%xmm4 - 433807: 0f 28 6e 37 movaps 0x37(%rsi),%xmm5 - 43380b: 0f 28 76 47 movaps 0x47(%rsi),%xmm6 - 43380f: 0f 28 7e 57 movaps 0x57(%rsi),%xmm7 - 433813: 44 0f 28 46 67 movaps 0x67(%rsi),%xmm8 - 433818: 44 0f 28 4e 77 movaps 0x77(%rsi),%xmm9 - 43381d: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi - 433824: 66 45 0f 3a 0f c8 09 palignr $0x9,%xmm8,%xmm9 - 43382b: 44 0f 29 4f 70 movaps %xmm9,0x70(%rdi) - 433830: 66 44 0f 3a 0f c7 09 palignr $0x9,%xmm7,%xmm8 - 433837: 44 0f 29 47 60 movaps %xmm8,0x60(%rdi) - 43383c: 66 0f 3a 0f fe 09 palignr $0x9,%xmm6,%xmm7 - 433842: 0f 29 7f 50 movaps %xmm7,0x50(%rdi) - 433846: 66 0f 3a 0f f5 09 palignr $0x9,%xmm5,%xmm6 - 43384c: 0f 29 77 40 movaps %xmm6,0x40(%rdi) - 433850: 66 0f 3a 0f ec 09 palignr $0x9,%xmm4,%xmm5 - 433856: 0f 29 6f 30 movaps %xmm5,0x30(%rdi) - 43385a: 66 0f 3a 0f e3 09 palignr $0x9,%xmm3,%xmm4 - 433860: 0f 29 67 20 movaps %xmm4,0x20(%rdi) - 433864: 66 0f 3a 0f da 09 palignr $0x9,%xmm2,%xmm3 - 43386a: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) - 43386e: 66 0f 3a 0f d1 09 palignr $0x9,%xmm1,%xmm2 - 433874: 0f 29 17 movaps %xmm2,(%rdi) - 433877: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi - 43387e: 0f 83 6c ff ff ff jae 4337f0 <__memmove_ssse3_back+0xe30> - 433884: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 433889: 48 81 c2 80 00 00 00 add $0x80,%rdx - 433890: 48 01 d7 add %rdx,%rdi - 433893: 48 01 d6 add %rdx,%rsi - 433896: 4c 8d 1d 13 ff 06 00 lea 0x6ff13(%rip),%r11 # 4a37b0 - 43389d: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 4338a1: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 4338a5: ff e2 jmpq *%rdx - 4338a7: 0f 0b ud2 - 4338a9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4338b0: 0f 28 4e f7 movaps -0x9(%rsi),%xmm1 - 4338b4: 0f 28 56 e7 movaps -0x19(%rsi),%xmm2 - 4338b8: 66 0f 3a 0f ca 09 palignr $0x9,%xmm2,%xmm1 - 4338be: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 4338c2: 0f 28 5e d7 movaps -0x29(%rsi),%xmm3 - 4338c6: 66 0f 3a 0f d3 09 palignr $0x9,%xmm3,%xmm2 - 4338cc: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 4338d0: 0f 28 66 c7 movaps -0x39(%rsi),%xmm4 - 4338d4: 66 0f 3a 0f dc 09 palignr $0x9,%xmm4,%xmm3 - 4338da: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 4338de: 0f 28 6e b7 movaps -0x49(%rsi),%xmm5 - 4338e2: 66 0f 3a 0f e5 09 palignr $0x9,%xmm5,%xmm4 - 4338e8: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) - 4338ec: 0f 28 76 a7 movaps -0x59(%rsi),%xmm6 - 4338f0: 66 0f 3a 0f ee 09 palignr $0x9,%xmm6,%xmm5 - 4338f6: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) - 4338fa: 0f 28 7e 97 movaps -0x69(%rsi),%xmm7 - 4338fe: 66 0f 3a 0f f7 09 palignr $0x9,%xmm7,%xmm6 - 433904: 0f 29 77 a0 movaps %xmm6,-0x60(%rdi) - 433908: 44 0f 28 46 87 movaps -0x79(%rsi),%xmm8 - 43390d: 66 41 0f 3a 0f f8 09 palignr $0x9,%xmm8,%xmm7 - 433914: 0f 29 7f 90 movaps %xmm7,-0x70(%rdi) - 433918: 44 0f 28 8e 77 ff ff movaps -0x89(%rsi),%xmm9 - 43391f: ff - 433920: 66 45 0f 3a 0f c1 09 palignr $0x9,%xmm9,%xmm8 - 433927: 44 0f 29 47 80 movaps %xmm8,-0x80(%rdi) - 43392c: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 433933: 48 8d 7f 80 lea -0x80(%rdi),%rdi - 433937: 48 8d 76 80 lea -0x80(%rsi),%rsi - 43393b: 0f 83 6f ff ff ff jae 4338b0 <__memmove_ssse3_back+0xef0> - 433941: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 433946: 48 81 c2 80 00 00 00 add $0x80,%rdx - 43394d: 48 29 d7 sub %rdx,%rdi - 433950: 48 29 d6 sub %rdx,%rsi - 433953: 4c 8d 1d 16 fc 06 00 lea 0x6fc16(%rip),%r11 # 4a3570 - 43395a: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 43395e: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 433962: ff e2 jmpq *%rdx - 433964: 0f 0b ud2 - 433966: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43396d: 00 00 00 - 433970: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 433977: 0f 28 4e f6 movaps -0xa(%rsi),%xmm1 - 43397b: 0f 28 56 06 movaps 0x6(%rsi),%xmm2 - 43397f: 0f 28 5e 16 movaps 0x16(%rsi),%xmm3 - 433983: 0f 28 66 26 movaps 0x26(%rsi),%xmm4 - 433987: 0f 28 6e 36 movaps 0x36(%rsi),%xmm5 - 43398b: 0f 28 76 46 movaps 0x46(%rsi),%xmm6 - 43398f: 0f 28 7e 56 movaps 0x56(%rsi),%xmm7 - 433993: 44 0f 28 46 66 movaps 0x66(%rsi),%xmm8 - 433998: 44 0f 28 4e 76 movaps 0x76(%rsi),%xmm9 - 43399d: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi - 4339a4: 66 45 0f 3a 0f c8 0a palignr $0xa,%xmm8,%xmm9 - 4339ab: 44 0f 29 4f 70 movaps %xmm9,0x70(%rdi) - 4339b0: 66 44 0f 3a 0f c7 0a palignr $0xa,%xmm7,%xmm8 - 4339b7: 44 0f 29 47 60 movaps %xmm8,0x60(%rdi) - 4339bc: 66 0f 3a 0f fe 0a palignr $0xa,%xmm6,%xmm7 - 4339c2: 0f 29 7f 50 movaps %xmm7,0x50(%rdi) - 4339c6: 66 0f 3a 0f f5 0a palignr $0xa,%xmm5,%xmm6 - 4339cc: 0f 29 77 40 movaps %xmm6,0x40(%rdi) - 4339d0: 66 0f 3a 0f ec 0a palignr $0xa,%xmm4,%xmm5 - 4339d6: 0f 29 6f 30 movaps %xmm5,0x30(%rdi) - 4339da: 66 0f 3a 0f e3 0a palignr $0xa,%xmm3,%xmm4 - 4339e0: 0f 29 67 20 movaps %xmm4,0x20(%rdi) - 4339e4: 66 0f 3a 0f da 0a palignr $0xa,%xmm2,%xmm3 - 4339ea: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) - 4339ee: 66 0f 3a 0f d1 0a palignr $0xa,%xmm1,%xmm2 - 4339f4: 0f 29 17 movaps %xmm2,(%rdi) - 4339f7: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi - 4339fe: 0f 83 6c ff ff ff jae 433970 <__memmove_ssse3_back+0xfb0> - 433a04: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 433a09: 48 81 c2 80 00 00 00 add $0x80,%rdx - 433a10: 48 01 d7 add %rdx,%rdi - 433a13: 48 01 d6 add %rdx,%rsi - 433a16: 4c 8d 1d 93 fd 06 00 lea 0x6fd93(%rip),%r11 # 4a37b0 - 433a1d: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 433a21: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 433a25: ff e2 jmpq *%rdx - 433a27: 0f 0b ud2 - 433a29: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 433a30: 0f 28 4e f6 movaps -0xa(%rsi),%xmm1 - 433a34: 0f 28 56 e6 movaps -0x1a(%rsi),%xmm2 - 433a38: 66 0f 3a 0f ca 0a palignr $0xa,%xmm2,%xmm1 - 433a3e: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 433a42: 0f 28 5e d6 movaps -0x2a(%rsi),%xmm3 - 433a46: 66 0f 3a 0f d3 0a palignr $0xa,%xmm3,%xmm2 - 433a4c: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 433a50: 0f 28 66 c6 movaps -0x3a(%rsi),%xmm4 - 433a54: 66 0f 3a 0f dc 0a palignr $0xa,%xmm4,%xmm3 - 433a5a: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 433a5e: 0f 28 6e b6 movaps -0x4a(%rsi),%xmm5 - 433a62: 66 0f 3a 0f e5 0a palignr $0xa,%xmm5,%xmm4 - 433a68: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) - 433a6c: 0f 28 76 a6 movaps -0x5a(%rsi),%xmm6 - 433a70: 66 0f 3a 0f ee 0a palignr $0xa,%xmm6,%xmm5 - 433a76: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) - 433a7a: 0f 28 7e 96 movaps -0x6a(%rsi),%xmm7 - 433a7e: 66 0f 3a 0f f7 0a palignr $0xa,%xmm7,%xmm6 - 433a84: 0f 29 77 a0 movaps %xmm6,-0x60(%rdi) - 433a88: 44 0f 28 46 86 movaps -0x7a(%rsi),%xmm8 - 433a8d: 66 41 0f 3a 0f f8 0a palignr $0xa,%xmm8,%xmm7 - 433a94: 0f 29 7f 90 movaps %xmm7,-0x70(%rdi) - 433a98: 44 0f 28 8e 76 ff ff movaps -0x8a(%rsi),%xmm9 - 433a9f: ff - 433aa0: 66 45 0f 3a 0f c1 0a palignr $0xa,%xmm9,%xmm8 - 433aa7: 44 0f 29 47 80 movaps %xmm8,-0x80(%rdi) - 433aac: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 433ab3: 48 8d 7f 80 lea -0x80(%rdi),%rdi - 433ab7: 48 8d 76 80 lea -0x80(%rsi),%rsi - 433abb: 0f 83 6f ff ff ff jae 433a30 <__memmove_ssse3_back+0x1070> - 433ac1: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 433ac6: 48 81 c2 80 00 00 00 add $0x80,%rdx - 433acd: 48 29 d7 sub %rdx,%rdi - 433ad0: 48 29 d6 sub %rdx,%rsi - 433ad3: 4c 8d 1d 96 fa 06 00 lea 0x6fa96(%rip),%r11 # 4a3570 - 433ada: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 433ade: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 433ae2: ff e2 jmpq *%rdx - 433ae4: 0f 0b ud2 - 433ae6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 433aed: 00 00 00 - 433af0: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 433af7: 0f 28 4e f5 movaps -0xb(%rsi),%xmm1 - 433afb: 0f 28 56 05 movaps 0x5(%rsi),%xmm2 - 433aff: 0f 28 5e 15 movaps 0x15(%rsi),%xmm3 - 433b03: 0f 28 66 25 movaps 0x25(%rsi),%xmm4 - 433b07: 0f 28 6e 35 movaps 0x35(%rsi),%xmm5 - 433b0b: 0f 28 76 45 movaps 0x45(%rsi),%xmm6 - 433b0f: 0f 28 7e 55 movaps 0x55(%rsi),%xmm7 - 433b13: 44 0f 28 46 65 movaps 0x65(%rsi),%xmm8 - 433b18: 44 0f 28 4e 75 movaps 0x75(%rsi),%xmm9 - 433b1d: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi - 433b24: 66 45 0f 3a 0f c8 0b palignr $0xb,%xmm8,%xmm9 - 433b2b: 44 0f 29 4f 70 movaps %xmm9,0x70(%rdi) - 433b30: 66 44 0f 3a 0f c7 0b palignr $0xb,%xmm7,%xmm8 - 433b37: 44 0f 29 47 60 movaps %xmm8,0x60(%rdi) - 433b3c: 66 0f 3a 0f fe 0b palignr $0xb,%xmm6,%xmm7 - 433b42: 0f 29 7f 50 movaps %xmm7,0x50(%rdi) - 433b46: 66 0f 3a 0f f5 0b palignr $0xb,%xmm5,%xmm6 - 433b4c: 0f 29 77 40 movaps %xmm6,0x40(%rdi) - 433b50: 66 0f 3a 0f ec 0b palignr $0xb,%xmm4,%xmm5 - 433b56: 0f 29 6f 30 movaps %xmm5,0x30(%rdi) - 433b5a: 66 0f 3a 0f e3 0b palignr $0xb,%xmm3,%xmm4 - 433b60: 0f 29 67 20 movaps %xmm4,0x20(%rdi) - 433b64: 66 0f 3a 0f da 0b palignr $0xb,%xmm2,%xmm3 - 433b6a: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) - 433b6e: 66 0f 3a 0f d1 0b palignr $0xb,%xmm1,%xmm2 - 433b74: 0f 29 17 movaps %xmm2,(%rdi) - 433b77: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi - 433b7e: 0f 83 6c ff ff ff jae 433af0 <__memmove_ssse3_back+0x1130> - 433b84: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 433b89: 48 81 c2 80 00 00 00 add $0x80,%rdx - 433b90: 48 01 d7 add %rdx,%rdi - 433b93: 48 01 d6 add %rdx,%rsi - 433b96: 4c 8d 1d 13 fc 06 00 lea 0x6fc13(%rip),%r11 # 4a37b0 - 433b9d: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 433ba1: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 433ba5: ff e2 jmpq *%rdx - 433ba7: 0f 0b ud2 - 433ba9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 433bb0: 0f 28 4e f5 movaps -0xb(%rsi),%xmm1 - 433bb4: 0f 28 56 e5 movaps -0x1b(%rsi),%xmm2 - 433bb8: 66 0f 3a 0f ca 0b palignr $0xb,%xmm2,%xmm1 - 433bbe: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 433bc2: 0f 28 5e d5 movaps -0x2b(%rsi),%xmm3 - 433bc6: 66 0f 3a 0f d3 0b palignr $0xb,%xmm3,%xmm2 - 433bcc: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 433bd0: 0f 28 66 c5 movaps -0x3b(%rsi),%xmm4 - 433bd4: 66 0f 3a 0f dc 0b palignr $0xb,%xmm4,%xmm3 - 433bda: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 433bde: 0f 28 6e b5 movaps -0x4b(%rsi),%xmm5 - 433be2: 66 0f 3a 0f e5 0b palignr $0xb,%xmm5,%xmm4 - 433be8: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) - 433bec: 0f 28 76 a5 movaps -0x5b(%rsi),%xmm6 - 433bf0: 66 0f 3a 0f ee 0b palignr $0xb,%xmm6,%xmm5 - 433bf6: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) - 433bfa: 0f 28 7e 95 movaps -0x6b(%rsi),%xmm7 - 433bfe: 66 0f 3a 0f f7 0b palignr $0xb,%xmm7,%xmm6 - 433c04: 0f 29 77 a0 movaps %xmm6,-0x60(%rdi) - 433c08: 44 0f 28 46 85 movaps -0x7b(%rsi),%xmm8 - 433c0d: 66 41 0f 3a 0f f8 0b palignr $0xb,%xmm8,%xmm7 - 433c14: 0f 29 7f 90 movaps %xmm7,-0x70(%rdi) - 433c18: 44 0f 28 8e 75 ff ff movaps -0x8b(%rsi),%xmm9 - 433c1f: ff - 433c20: 66 45 0f 3a 0f c1 0b palignr $0xb,%xmm9,%xmm8 - 433c27: 44 0f 29 47 80 movaps %xmm8,-0x80(%rdi) - 433c2c: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 433c33: 48 8d 7f 80 lea -0x80(%rdi),%rdi - 433c37: 48 8d 76 80 lea -0x80(%rsi),%rsi - 433c3b: 0f 83 6f ff ff ff jae 433bb0 <__memmove_ssse3_back+0x11f0> - 433c41: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 433c46: 48 81 c2 80 00 00 00 add $0x80,%rdx - 433c4d: 48 29 d7 sub %rdx,%rdi - 433c50: 48 29 d6 sub %rdx,%rsi - 433c53: 4c 8d 1d 16 f9 06 00 lea 0x6f916(%rip),%r11 # 4a3570 - 433c5a: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 433c5e: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 433c62: ff e2 jmpq *%rdx - 433c64: 0f 0b ud2 - 433c66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 433c6d: 00 00 00 - 433c70: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 433c77: 66 0f 6f 4e f4 movdqa -0xc(%rsi),%xmm1 - 433c7c: 0f 28 56 04 movaps 0x4(%rsi),%xmm2 - 433c80: 0f 28 5e 14 movaps 0x14(%rsi),%xmm3 - 433c84: 0f 28 66 24 movaps 0x24(%rsi),%xmm4 - 433c88: 0f 28 6e 34 movaps 0x34(%rsi),%xmm5 - 433c8c: 0f 28 76 44 movaps 0x44(%rsi),%xmm6 - 433c90: 0f 28 7e 54 movaps 0x54(%rsi),%xmm7 - 433c94: 44 0f 28 46 64 movaps 0x64(%rsi),%xmm8 - 433c99: 44 0f 28 4e 74 movaps 0x74(%rsi),%xmm9 - 433c9e: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi - 433ca5: 66 45 0f 3a 0f c8 0c palignr $0xc,%xmm8,%xmm9 - 433cac: 44 0f 29 4f 70 movaps %xmm9,0x70(%rdi) - 433cb1: 66 44 0f 3a 0f c7 0c palignr $0xc,%xmm7,%xmm8 - 433cb8: 44 0f 29 47 60 movaps %xmm8,0x60(%rdi) - 433cbd: 66 0f 3a 0f fe 0c palignr $0xc,%xmm6,%xmm7 - 433cc3: 0f 29 7f 50 movaps %xmm7,0x50(%rdi) - 433cc7: 66 0f 3a 0f f5 0c palignr $0xc,%xmm5,%xmm6 - 433ccd: 0f 29 77 40 movaps %xmm6,0x40(%rdi) - 433cd1: 66 0f 3a 0f ec 0c palignr $0xc,%xmm4,%xmm5 - 433cd7: 0f 29 6f 30 movaps %xmm5,0x30(%rdi) - 433cdb: 66 0f 3a 0f e3 0c palignr $0xc,%xmm3,%xmm4 - 433ce1: 0f 29 67 20 movaps %xmm4,0x20(%rdi) - 433ce5: 66 0f 3a 0f da 0c palignr $0xc,%xmm2,%xmm3 - 433ceb: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) - 433cef: 66 0f 3a 0f d1 0c palignr $0xc,%xmm1,%xmm2 - 433cf5: 0f 29 17 movaps %xmm2,(%rdi) - 433cf8: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi - 433cff: 0f 83 6b ff ff ff jae 433c70 <__memmove_ssse3_back+0x12b0> - 433d05: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 433d0a: 48 81 c2 80 00 00 00 add $0x80,%rdx - 433d11: 48 01 d7 add %rdx,%rdi - 433d14: 48 01 d6 add %rdx,%rsi - 433d17: 4c 8d 1d 92 fa 06 00 lea 0x6fa92(%rip),%r11 # 4a37b0 - 433d1e: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 433d22: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 433d26: ff e2 jmpq *%rdx - 433d28: 0f 0b ud2 - 433d2a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 433d30: 0f 28 4e f4 movaps -0xc(%rsi),%xmm1 - 433d34: 0f 28 56 e4 movaps -0x1c(%rsi),%xmm2 - 433d38: 66 0f 3a 0f ca 0c palignr $0xc,%xmm2,%xmm1 - 433d3e: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 433d42: 0f 28 5e d4 movaps -0x2c(%rsi),%xmm3 - 433d46: 66 0f 3a 0f d3 0c palignr $0xc,%xmm3,%xmm2 - 433d4c: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 433d50: 0f 28 66 c4 movaps -0x3c(%rsi),%xmm4 - 433d54: 66 0f 3a 0f dc 0c palignr $0xc,%xmm4,%xmm3 - 433d5a: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 433d5e: 0f 28 6e b4 movaps -0x4c(%rsi),%xmm5 - 433d62: 66 0f 3a 0f e5 0c palignr $0xc,%xmm5,%xmm4 - 433d68: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) - 433d6c: 0f 28 76 a4 movaps -0x5c(%rsi),%xmm6 - 433d70: 66 0f 3a 0f ee 0c palignr $0xc,%xmm6,%xmm5 - 433d76: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) - 433d7a: 0f 28 7e 94 movaps -0x6c(%rsi),%xmm7 - 433d7e: 66 0f 3a 0f f7 0c palignr $0xc,%xmm7,%xmm6 - 433d84: 0f 29 77 a0 movaps %xmm6,-0x60(%rdi) - 433d88: 44 0f 28 46 84 movaps -0x7c(%rsi),%xmm8 - 433d8d: 66 41 0f 3a 0f f8 0c palignr $0xc,%xmm8,%xmm7 - 433d94: 0f 29 7f 90 movaps %xmm7,-0x70(%rdi) - 433d98: 44 0f 28 8e 74 ff ff movaps -0x8c(%rsi),%xmm9 - 433d9f: ff - 433da0: 66 45 0f 3a 0f c1 0c palignr $0xc,%xmm9,%xmm8 - 433da7: 44 0f 29 47 80 movaps %xmm8,-0x80(%rdi) - 433dac: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 433db3: 48 8d 7f 80 lea -0x80(%rdi),%rdi - 433db7: 48 8d 76 80 lea -0x80(%rsi),%rsi - 433dbb: 0f 83 6f ff ff ff jae 433d30 <__memmove_ssse3_back+0x1370> - 433dc1: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 433dc6: 48 81 c2 80 00 00 00 add $0x80,%rdx - 433dcd: 48 29 d7 sub %rdx,%rdi - 433dd0: 48 29 d6 sub %rdx,%rsi - 433dd3: 4c 8d 1d 96 f7 06 00 lea 0x6f796(%rip),%r11 # 4a3570 - 433dda: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 433dde: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 433de2: ff e2 jmpq *%rdx - 433de4: 0f 0b ud2 - 433de6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 433ded: 00 00 00 - 433df0: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 433df7: 0f 28 4e f3 movaps -0xd(%rsi),%xmm1 - 433dfb: 0f 28 56 03 movaps 0x3(%rsi),%xmm2 - 433dff: 0f 28 5e 13 movaps 0x13(%rsi),%xmm3 - 433e03: 0f 28 66 23 movaps 0x23(%rsi),%xmm4 - 433e07: 0f 28 6e 33 movaps 0x33(%rsi),%xmm5 - 433e0b: 0f 28 76 43 movaps 0x43(%rsi),%xmm6 - 433e0f: 0f 28 7e 53 movaps 0x53(%rsi),%xmm7 - 433e13: 44 0f 28 46 63 movaps 0x63(%rsi),%xmm8 - 433e18: 44 0f 28 4e 73 movaps 0x73(%rsi),%xmm9 - 433e1d: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi - 433e24: 66 45 0f 3a 0f c8 0d palignr $0xd,%xmm8,%xmm9 - 433e2b: 44 0f 29 4f 70 movaps %xmm9,0x70(%rdi) - 433e30: 66 44 0f 3a 0f c7 0d palignr $0xd,%xmm7,%xmm8 - 433e37: 44 0f 29 47 60 movaps %xmm8,0x60(%rdi) - 433e3c: 66 0f 3a 0f fe 0d palignr $0xd,%xmm6,%xmm7 - 433e42: 0f 29 7f 50 movaps %xmm7,0x50(%rdi) - 433e46: 66 0f 3a 0f f5 0d palignr $0xd,%xmm5,%xmm6 - 433e4c: 0f 29 77 40 movaps %xmm6,0x40(%rdi) - 433e50: 66 0f 3a 0f ec 0d palignr $0xd,%xmm4,%xmm5 - 433e56: 0f 29 6f 30 movaps %xmm5,0x30(%rdi) - 433e5a: 66 0f 3a 0f e3 0d palignr $0xd,%xmm3,%xmm4 - 433e60: 0f 29 67 20 movaps %xmm4,0x20(%rdi) - 433e64: 66 0f 3a 0f da 0d palignr $0xd,%xmm2,%xmm3 - 433e6a: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) - 433e6e: 66 0f 3a 0f d1 0d palignr $0xd,%xmm1,%xmm2 - 433e74: 0f 29 17 movaps %xmm2,(%rdi) - 433e77: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi - 433e7e: 0f 83 6c ff ff ff jae 433df0 <__memmove_ssse3_back+0x1430> - 433e84: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 433e89: 48 81 c2 80 00 00 00 add $0x80,%rdx - 433e90: 48 01 d7 add %rdx,%rdi - 433e93: 48 01 d6 add %rdx,%rsi - 433e96: 4c 8d 1d 13 f9 06 00 lea 0x6f913(%rip),%r11 # 4a37b0 - 433e9d: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 433ea1: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 433ea5: ff e2 jmpq *%rdx - 433ea7: 0f 0b ud2 - 433ea9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 433eb0: 0f 28 4e f3 movaps -0xd(%rsi),%xmm1 - 433eb4: 0f 28 56 e3 movaps -0x1d(%rsi),%xmm2 - 433eb8: 66 0f 3a 0f ca 0d palignr $0xd,%xmm2,%xmm1 - 433ebe: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 433ec2: 0f 28 5e d3 movaps -0x2d(%rsi),%xmm3 - 433ec6: 66 0f 3a 0f d3 0d palignr $0xd,%xmm3,%xmm2 - 433ecc: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 433ed0: 0f 28 66 c3 movaps -0x3d(%rsi),%xmm4 - 433ed4: 66 0f 3a 0f dc 0d palignr $0xd,%xmm4,%xmm3 - 433eda: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 433ede: 0f 28 6e b3 movaps -0x4d(%rsi),%xmm5 - 433ee2: 66 0f 3a 0f e5 0d palignr $0xd,%xmm5,%xmm4 - 433ee8: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) - 433eec: 0f 28 76 a3 movaps -0x5d(%rsi),%xmm6 - 433ef0: 66 0f 3a 0f ee 0d palignr $0xd,%xmm6,%xmm5 - 433ef6: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) - 433efa: 0f 28 7e 93 movaps -0x6d(%rsi),%xmm7 - 433efe: 66 0f 3a 0f f7 0d palignr $0xd,%xmm7,%xmm6 - 433f04: 0f 29 77 a0 movaps %xmm6,-0x60(%rdi) - 433f08: 44 0f 28 46 83 movaps -0x7d(%rsi),%xmm8 - 433f0d: 66 41 0f 3a 0f f8 0d palignr $0xd,%xmm8,%xmm7 - 433f14: 0f 29 7f 90 movaps %xmm7,-0x70(%rdi) - 433f18: 44 0f 28 8e 73 ff ff movaps -0x8d(%rsi),%xmm9 - 433f1f: ff - 433f20: 66 45 0f 3a 0f c1 0d palignr $0xd,%xmm9,%xmm8 - 433f27: 44 0f 29 47 80 movaps %xmm8,-0x80(%rdi) - 433f2c: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 433f33: 48 8d 7f 80 lea -0x80(%rdi),%rdi - 433f37: 48 8d 76 80 lea -0x80(%rsi),%rsi - 433f3b: 0f 83 6f ff ff ff jae 433eb0 <__memmove_ssse3_back+0x14f0> - 433f41: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 433f46: 48 81 c2 80 00 00 00 add $0x80,%rdx - 433f4d: 48 29 d7 sub %rdx,%rdi - 433f50: 48 29 d6 sub %rdx,%rsi - 433f53: 4c 8d 1d 16 f6 06 00 lea 0x6f616(%rip),%r11 # 4a3570 - 433f5a: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 433f5e: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 433f62: ff e2 jmpq *%rdx - 433f64: 0f 0b ud2 - 433f66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 433f6d: 00 00 00 - 433f70: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 433f77: 0f 28 4e f2 movaps -0xe(%rsi),%xmm1 - 433f7b: 0f 28 56 02 movaps 0x2(%rsi),%xmm2 - 433f7f: 0f 28 5e 12 movaps 0x12(%rsi),%xmm3 - 433f83: 0f 28 66 22 movaps 0x22(%rsi),%xmm4 - 433f87: 0f 28 6e 32 movaps 0x32(%rsi),%xmm5 - 433f8b: 0f 28 76 42 movaps 0x42(%rsi),%xmm6 - 433f8f: 0f 28 7e 52 movaps 0x52(%rsi),%xmm7 - 433f93: 44 0f 28 46 62 movaps 0x62(%rsi),%xmm8 - 433f98: 44 0f 28 4e 72 movaps 0x72(%rsi),%xmm9 - 433f9d: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi - 433fa4: 66 45 0f 3a 0f c8 0e palignr $0xe,%xmm8,%xmm9 - 433fab: 44 0f 29 4f 70 movaps %xmm9,0x70(%rdi) - 433fb0: 66 44 0f 3a 0f c7 0e palignr $0xe,%xmm7,%xmm8 - 433fb7: 44 0f 29 47 60 movaps %xmm8,0x60(%rdi) - 433fbc: 66 0f 3a 0f fe 0e palignr $0xe,%xmm6,%xmm7 - 433fc2: 0f 29 7f 50 movaps %xmm7,0x50(%rdi) - 433fc6: 66 0f 3a 0f f5 0e palignr $0xe,%xmm5,%xmm6 - 433fcc: 0f 29 77 40 movaps %xmm6,0x40(%rdi) - 433fd0: 66 0f 3a 0f ec 0e palignr $0xe,%xmm4,%xmm5 - 433fd6: 0f 29 6f 30 movaps %xmm5,0x30(%rdi) - 433fda: 66 0f 3a 0f e3 0e palignr $0xe,%xmm3,%xmm4 - 433fe0: 0f 29 67 20 movaps %xmm4,0x20(%rdi) - 433fe4: 66 0f 3a 0f da 0e palignr $0xe,%xmm2,%xmm3 - 433fea: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) - 433fee: 66 0f 3a 0f d1 0e palignr $0xe,%xmm1,%xmm2 - 433ff4: 0f 29 17 movaps %xmm2,(%rdi) - 433ff7: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi - 433ffe: 0f 83 6c ff ff ff jae 433f70 <__memmove_ssse3_back+0x15b0> - 434004: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 434009: 48 81 c2 80 00 00 00 add $0x80,%rdx - 434010: 48 01 d7 add %rdx,%rdi - 434013: 48 01 d6 add %rdx,%rsi - 434016: 4c 8d 1d 93 f7 06 00 lea 0x6f793(%rip),%r11 # 4a37b0 - 43401d: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 434021: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 434025: ff e2 jmpq *%rdx - 434027: 0f 0b ud2 - 434029: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 434030: 0f 28 4e f2 movaps -0xe(%rsi),%xmm1 - 434034: 0f 28 56 e2 movaps -0x1e(%rsi),%xmm2 - 434038: 66 0f 3a 0f ca 0e palignr $0xe,%xmm2,%xmm1 - 43403e: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 434042: 0f 28 5e d2 movaps -0x2e(%rsi),%xmm3 - 434046: 66 0f 3a 0f d3 0e palignr $0xe,%xmm3,%xmm2 - 43404c: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 434050: 0f 28 66 c2 movaps -0x3e(%rsi),%xmm4 - 434054: 66 0f 3a 0f dc 0e palignr $0xe,%xmm4,%xmm3 - 43405a: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 43405e: 0f 28 6e b2 movaps -0x4e(%rsi),%xmm5 - 434062: 66 0f 3a 0f e5 0e palignr $0xe,%xmm5,%xmm4 - 434068: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) - 43406c: 0f 28 76 a2 movaps -0x5e(%rsi),%xmm6 - 434070: 66 0f 3a 0f ee 0e palignr $0xe,%xmm6,%xmm5 - 434076: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) - 43407a: 0f 28 7e 92 movaps -0x6e(%rsi),%xmm7 - 43407e: 66 0f 3a 0f f7 0e palignr $0xe,%xmm7,%xmm6 - 434084: 0f 29 77 a0 movaps %xmm6,-0x60(%rdi) - 434088: 44 0f 28 46 82 movaps -0x7e(%rsi),%xmm8 - 43408d: 66 41 0f 3a 0f f8 0e palignr $0xe,%xmm8,%xmm7 - 434094: 0f 29 7f 90 movaps %xmm7,-0x70(%rdi) - 434098: 44 0f 28 8e 72 ff ff movaps -0x8e(%rsi),%xmm9 - 43409f: ff - 4340a0: 66 45 0f 3a 0f c1 0e palignr $0xe,%xmm9,%xmm8 - 4340a7: 44 0f 29 47 80 movaps %xmm8,-0x80(%rdi) - 4340ac: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 4340b3: 48 8d 7f 80 lea -0x80(%rdi),%rdi - 4340b7: 48 8d 76 80 lea -0x80(%rsi),%rsi - 4340bb: 0f 83 6f ff ff ff jae 434030 <__memmove_ssse3_back+0x1670> - 4340c1: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 4340c6: 48 81 c2 80 00 00 00 add $0x80,%rdx - 4340cd: 48 29 d7 sub %rdx,%rdi - 4340d0: 48 29 d6 sub %rdx,%rsi - 4340d3: 4c 8d 1d 96 f4 06 00 lea 0x6f496(%rip),%r11 # 4a3570 - 4340da: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 4340de: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 4340e2: ff e2 jmpq *%rdx - 4340e4: 0f 0b ud2 - 4340e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4340ed: 00 00 00 - 4340f0: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 4340f7: 0f 28 4e f1 movaps -0xf(%rsi),%xmm1 - 4340fb: 0f 28 56 01 movaps 0x1(%rsi),%xmm2 - 4340ff: 0f 28 5e 11 movaps 0x11(%rsi),%xmm3 - 434103: 0f 28 66 21 movaps 0x21(%rsi),%xmm4 - 434107: 0f 28 6e 31 movaps 0x31(%rsi),%xmm5 - 43410b: 0f 28 76 41 movaps 0x41(%rsi),%xmm6 - 43410f: 0f 28 7e 51 movaps 0x51(%rsi),%xmm7 - 434113: 44 0f 28 46 61 movaps 0x61(%rsi),%xmm8 - 434118: 44 0f 28 4e 71 movaps 0x71(%rsi),%xmm9 - 43411d: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi - 434124: 66 45 0f 3a 0f c8 0f palignr $0xf,%xmm8,%xmm9 - 43412b: 44 0f 29 4f 70 movaps %xmm9,0x70(%rdi) - 434130: 66 44 0f 3a 0f c7 0f palignr $0xf,%xmm7,%xmm8 - 434137: 44 0f 29 47 60 movaps %xmm8,0x60(%rdi) - 43413c: 66 0f 3a 0f fe 0f palignr $0xf,%xmm6,%xmm7 - 434142: 0f 29 7f 50 movaps %xmm7,0x50(%rdi) - 434146: 66 0f 3a 0f f5 0f palignr $0xf,%xmm5,%xmm6 - 43414c: 0f 29 77 40 movaps %xmm6,0x40(%rdi) - 434150: 66 0f 3a 0f ec 0f palignr $0xf,%xmm4,%xmm5 - 434156: 0f 29 6f 30 movaps %xmm5,0x30(%rdi) - 43415a: 66 0f 3a 0f e3 0f palignr $0xf,%xmm3,%xmm4 - 434160: 0f 29 67 20 movaps %xmm4,0x20(%rdi) - 434164: 66 0f 3a 0f da 0f palignr $0xf,%xmm2,%xmm3 - 43416a: 0f 29 5f 10 movaps %xmm3,0x10(%rdi) - 43416e: 66 0f 3a 0f d1 0f palignr $0xf,%xmm1,%xmm2 - 434174: 0f 29 17 movaps %xmm2,(%rdi) - 434177: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi - 43417e: 0f 83 6c ff ff ff jae 4340f0 <__memmove_ssse3_back+0x1730> - 434184: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 434189: 48 81 c2 80 00 00 00 add $0x80,%rdx - 434190: 48 01 d7 add %rdx,%rdi - 434193: 48 01 d6 add %rdx,%rsi - 434196: 4c 8d 1d 13 f6 06 00 lea 0x6f613(%rip),%r11 # 4a37b0 - 43419d: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 4341a1: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 4341a5: ff e2 jmpq *%rdx - 4341a7: 0f 0b ud2 - 4341a9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4341b0: 0f 28 4e f1 movaps -0xf(%rsi),%xmm1 - 4341b4: 0f 28 56 e1 movaps -0x1f(%rsi),%xmm2 - 4341b8: 66 0f 3a 0f ca 0f palignr $0xf,%xmm2,%xmm1 - 4341be: 0f 29 4f f0 movaps %xmm1,-0x10(%rdi) - 4341c2: 0f 28 5e d1 movaps -0x2f(%rsi),%xmm3 - 4341c6: 66 0f 3a 0f d3 0f palignr $0xf,%xmm3,%xmm2 - 4341cc: 0f 29 57 e0 movaps %xmm2,-0x20(%rdi) - 4341d0: 0f 28 66 c1 movaps -0x3f(%rsi),%xmm4 - 4341d4: 66 0f 3a 0f dc 0f palignr $0xf,%xmm4,%xmm3 - 4341da: 0f 29 5f d0 movaps %xmm3,-0x30(%rdi) - 4341de: 0f 28 6e b1 movaps -0x4f(%rsi),%xmm5 - 4341e2: 66 0f 3a 0f e5 0f palignr $0xf,%xmm5,%xmm4 - 4341e8: 0f 29 67 c0 movaps %xmm4,-0x40(%rdi) - 4341ec: 0f 28 76 a1 movaps -0x5f(%rsi),%xmm6 - 4341f0: 66 0f 3a 0f ee 0f palignr $0xf,%xmm6,%xmm5 - 4341f6: 0f 29 6f b0 movaps %xmm5,-0x50(%rdi) - 4341fa: 0f 28 7e 91 movaps -0x6f(%rsi),%xmm7 - 4341fe: 66 0f 3a 0f f7 0f palignr $0xf,%xmm7,%xmm6 - 434204: 0f 29 77 a0 movaps %xmm6,-0x60(%rdi) - 434208: 44 0f 28 46 81 movaps -0x7f(%rsi),%xmm8 - 43420d: 66 41 0f 3a 0f f8 0f palignr $0xf,%xmm8,%xmm7 - 434214: 0f 29 7f 90 movaps %xmm7,-0x70(%rdi) - 434218: 44 0f 28 8e 71 ff ff movaps -0x8f(%rsi),%xmm9 - 43421f: ff - 434220: 66 45 0f 3a 0f c1 0f palignr $0xf,%xmm9,%xmm8 - 434227: 44 0f 29 47 80 movaps %xmm8,-0x80(%rdi) - 43422c: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 434233: 48 8d 7f 80 lea -0x80(%rdi),%rdi - 434237: 48 8d 76 80 lea -0x80(%rsi),%rsi - 43423b: 0f 83 6f ff ff ff jae 4341b0 <__memmove_ssse3_back+0x17f0> - 434241: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 434246: 48 81 c2 80 00 00 00 add $0x80,%rdx - 43424d: 48 29 d7 sub %rdx,%rdi - 434250: 48 29 d6 sub %rdx,%rsi - 434253: 4c 8d 1d 16 f3 06 00 lea 0x6f316(%rip),%r11 # 4a3570 - 43425a: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 43425e: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 434262: ff e2 jmpq *%rdx - 434264: 0f 0b ud2 - 434266: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43426d: 00 00 00 - 434270: f3 0f 6f 0e movdqu (%rsi),%xmm1 - 434274: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 434279: 66 0f 7f 0f movdqa %xmm1,(%rdi) - 43427d: 48 83 ea 10 sub $0x10,%rdx - 434281: 48 83 c6 10 add $0x10,%rsi - 434285: 48 83 c7 10 add $0x10,%rdi - 434289: 48 8b 0d 20 6e 29 00 mov 0x296e20(%rip),%rcx # 6cb0b0 <__x86_shared_cache_size_half> - 434290: 49 89 f1 mov %rsi,%r9 - 434293: 49 29 f9 sub %rdi,%r9 - 434296: 49 39 d1 cmp %rdx,%r9 - 434299: 73 09 jae 4342a4 <__memmove_ssse3_back+0x18e4> - 43429b: 49 39 c9 cmp %rcx,%r9 - 43429e: 0f 86 c1 00 00 00 jbe 434365 <__memmove_ssse3_back+0x19a5> - 4342a4: 48 39 ca cmp %rcx,%rdx - 4342a7: 77 03 ja 4342ac <__memmove_ssse3_back+0x18ec> - 4342a9: 48 89 d1 mov %rdx,%rcx - 4342ac: 48 29 ca sub %rcx,%rdx - 4342af: 48 81 fa 00 10 00 00 cmp $0x1000,%rdx - 4342b6: 0f 86 a6 00 00 00 jbe 434362 <__memmove_ssse3_back+0x19a2> - 4342bc: 49 89 c9 mov %rcx,%r9 - 4342bf: 49 c1 e1 03 shl $0x3,%r9 - 4342c3: 4c 39 ca cmp %r9,%rdx - 4342c6: 76 06 jbe 4342ce <__memmove_ssse3_back+0x190e> - 4342c8: 48 01 ca add %rcx,%rdx - 4342cb: 48 31 c9 xor %rcx,%rcx - 4342ce: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 4342d5: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 4342dc: 0f 18 8e 00 02 00 00 prefetcht0 0x200(%rsi) - 4342e3: 0f 18 8e 00 03 00 00 prefetcht0 0x300(%rsi) - 4342ea: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 4342ee: f3 0f 6f 4e 10 movdqu 0x10(%rsi),%xmm1 - 4342f3: f3 0f 6f 56 20 movdqu 0x20(%rsi),%xmm2 - 4342f8: f3 0f 6f 5e 30 movdqu 0x30(%rsi),%xmm3 - 4342fd: f3 0f 6f 66 40 movdqu 0x40(%rsi),%xmm4 - 434302: f3 0f 6f 6e 50 movdqu 0x50(%rsi),%xmm5 - 434307: f3 0f 6f 76 60 movdqu 0x60(%rsi),%xmm6 - 43430c: f3 0f 6f 7e 70 movdqu 0x70(%rsi),%xmm7 - 434311: 0f ae e8 lfence - 434314: 66 0f e7 07 movntdq %xmm0,(%rdi) - 434318: 66 0f e7 4f 10 movntdq %xmm1,0x10(%rdi) - 43431d: 66 0f e7 57 20 movntdq %xmm2,0x20(%rdi) - 434322: 66 0f e7 5f 30 movntdq %xmm3,0x30(%rdi) - 434327: 66 0f e7 67 40 movntdq %xmm4,0x40(%rdi) - 43432c: 66 0f e7 6f 50 movntdq %xmm5,0x50(%rdi) - 434331: 66 0f e7 77 60 movntdq %xmm6,0x60(%rdi) - 434336: 66 0f e7 7f 70 movntdq %xmm7,0x70(%rdi) - 43433b: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi - 434342: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi - 434349: 73 8a jae 4342d5 <__memmove_ssse3_back+0x1915> - 43434b: 0f ae f8 sfence - 43434e: 48 81 f9 80 00 00 00 cmp $0x80,%rcx - 434355: 0f 82 96 00 00 00 jb 4343f1 <__memmove_ssse3_back+0x1a31> - 43435b: 48 81 c2 80 00 00 00 add $0x80,%rdx - 434362: 48 01 ca add %rcx,%rdx - 434365: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 43436c: 0f 18 86 c0 01 00 00 prefetchnta 0x1c0(%rsi) - 434373: 0f 18 86 80 02 00 00 prefetchnta 0x280(%rsi) - 43437a: 0f 18 87 c0 01 00 00 prefetchnta 0x1c0(%rdi) - 434381: 0f 18 87 80 02 00 00 prefetchnta 0x280(%rdi) - 434388: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 43438f: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 434393: f3 0f 6f 4e 10 movdqu 0x10(%rsi),%xmm1 - 434398: f3 0f 6f 56 20 movdqu 0x20(%rsi),%xmm2 - 43439d: f3 0f 6f 5e 30 movdqu 0x30(%rsi),%xmm3 - 4343a2: f3 0f 6f 66 40 movdqu 0x40(%rsi),%xmm4 - 4343a7: f3 0f 6f 6e 50 movdqu 0x50(%rsi),%xmm5 - 4343ac: f3 0f 6f 76 60 movdqu 0x60(%rsi),%xmm6 - 4343b1: f3 0f 6f 7e 70 movdqu 0x70(%rsi),%xmm7 - 4343b6: 66 0f 7f 07 movdqa %xmm0,(%rdi) - 4343ba: 66 0f 7f 4f 10 movdqa %xmm1,0x10(%rdi) - 4343bf: 66 0f 7f 57 20 movdqa %xmm2,0x20(%rdi) - 4343c4: 66 0f 7f 5f 30 movdqa %xmm3,0x30(%rdi) - 4343c9: 66 0f 7f 67 40 movdqa %xmm4,0x40(%rdi) - 4343ce: 66 0f 7f 6f 50 movdqa %xmm5,0x50(%rdi) - 4343d3: 66 0f 7f 77 60 movdqa %xmm6,0x60(%rdi) - 4343d8: 66 0f 7f 7f 70 movdqa %xmm7,0x70(%rdi) - 4343dd: 48 8d b6 80 00 00 00 lea 0x80(%rsi),%rsi - 4343e4: 48 8d bf 80 00 00 00 lea 0x80(%rdi),%rdi - 4343eb: 0f 83 7b ff ff ff jae 43436c <__memmove_ssse3_back+0x19ac> - 4343f1: 48 81 c2 80 00 00 00 add $0x80,%rdx - 4343f8: 48 01 d6 add %rdx,%rsi - 4343fb: 48 01 d7 add %rdx,%rdi - 4343fe: 4c 8d 1d ab f3 06 00 lea 0x6f3ab(%rip),%r11 # 4a37b0 - 434405: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 434409: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 43440d: ff e2 jmpq *%rdx - 43440f: 0f 0b ud2 - 434411: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 434416: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43441d: 00 00 00 - 434420: 48 01 d6 add %rdx,%rsi - 434423: 48 01 d7 add %rdx,%rdi - 434426: f3 0f 6f 46 f0 movdqu -0x10(%rsi),%xmm0 - 43442b: 4c 8d 47 f0 lea -0x10(%rdi),%r8 - 43442f: 49 89 f9 mov %rdi,%r9 - 434432: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi - 434436: 49 29 f9 sub %rdi,%r9 - 434439: 4c 29 ce sub %r9,%rsi - 43443c: 4c 29 ca sub %r9,%rdx - 43443f: 48 8b 0d 6a 6c 29 00 mov 0x296c6a(%rip),%rcx # 6cb0b0 <__x86_shared_cache_size_half> - 434446: 49 89 f9 mov %rdi,%r9 - 434449: 49 29 f1 sub %rsi,%r9 - 43444c: 49 39 d1 cmp %rdx,%r9 - 43444f: 73 09 jae 43445a <__memmove_ssse3_back+0x1a9a> - 434451: 49 39 c9 cmp %rcx,%r9 - 434454: 0f 86 bf 00 00 00 jbe 434519 <__memmove_ssse3_back+0x1b59> - 43445a: 48 39 ca cmp %rcx,%rdx - 43445d: 77 03 ja 434462 <__memmove_ssse3_back+0x1aa2> - 43445f: 48 89 d1 mov %rdx,%rcx - 434462: 48 29 ca sub %rcx,%rdx - 434465: 48 81 fa 00 10 00 00 cmp $0x1000,%rdx - 43446c: 0f 86 a4 00 00 00 jbe 434516 <__memmove_ssse3_back+0x1b56> - 434472: 49 89 c9 mov %rcx,%r9 - 434475: 49 c1 e1 03 shl $0x3,%r9 - 434479: 4c 39 ca cmp %r9,%rdx - 43447c: 76 06 jbe 434484 <__memmove_ssse3_back+0x1ac4> - 43447e: 48 01 ca add %rcx,%rdx - 434481: 48 31 c9 xor %rcx,%rcx - 434484: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 43448b: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 434492: 0f 18 8e 00 fe ff ff prefetcht0 -0x200(%rsi) - 434499: 0f 18 8e 00 fd ff ff prefetcht0 -0x300(%rsi) - 4344a0: f3 0f 6f 4e f0 movdqu -0x10(%rsi),%xmm1 - 4344a5: f3 0f 6f 56 e0 movdqu -0x20(%rsi),%xmm2 - 4344aa: f3 0f 6f 5e d0 movdqu -0x30(%rsi),%xmm3 - 4344af: f3 0f 6f 66 c0 movdqu -0x40(%rsi),%xmm4 - 4344b4: f3 0f 6f 6e b0 movdqu -0x50(%rsi),%xmm5 - 4344b9: f3 0f 6f 76 a0 movdqu -0x60(%rsi),%xmm6 - 4344be: f3 0f 6f 7e 90 movdqu -0x70(%rsi),%xmm7 - 4344c3: f3 44 0f 6f 46 80 movdqu -0x80(%rsi),%xmm8 - 4344c9: 0f ae e8 lfence - 4344cc: 66 0f e7 4f f0 movntdq %xmm1,-0x10(%rdi) - 4344d1: 66 0f e7 57 e0 movntdq %xmm2,-0x20(%rdi) - 4344d6: 66 0f e7 5f d0 movntdq %xmm3,-0x30(%rdi) - 4344db: 66 0f e7 67 c0 movntdq %xmm4,-0x40(%rdi) - 4344e0: 66 0f e7 6f b0 movntdq %xmm5,-0x50(%rdi) - 4344e5: 66 0f e7 77 a0 movntdq %xmm6,-0x60(%rdi) - 4344ea: 66 0f e7 7f 90 movntdq %xmm7,-0x70(%rdi) - 4344ef: 66 44 0f e7 47 80 movntdq %xmm8,-0x80(%rdi) - 4344f5: 48 8d 76 80 lea -0x80(%rsi),%rsi - 4344f9: 48 8d 7f 80 lea -0x80(%rdi),%rdi - 4344fd: 73 8c jae 43448b <__memmove_ssse3_back+0x1acb> - 4344ff: 0f ae f8 sfence - 434502: 48 81 f9 80 00 00 00 cmp $0x80,%rcx - 434509: 0f 82 90 00 00 00 jb 43459f <__memmove_ssse3_back+0x1bdf> - 43450f: 48 81 c2 80 00 00 00 add $0x80,%rdx - 434516: 48 01 ca add %rcx,%rdx - 434519: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 434520: 0f 18 86 40 fe ff ff prefetchnta -0x1c0(%rsi) - 434527: 0f 18 86 80 fd ff ff prefetchnta -0x280(%rsi) - 43452e: 0f 18 87 40 fe ff ff prefetchnta -0x1c0(%rdi) - 434535: 0f 18 87 80 fd ff ff prefetchnta -0x280(%rdi) - 43453c: 48 81 ea 80 00 00 00 sub $0x80,%rdx - 434543: f3 0f 6f 4e f0 movdqu -0x10(%rsi),%xmm1 - 434548: f3 0f 6f 56 e0 movdqu -0x20(%rsi),%xmm2 - 43454d: f3 0f 6f 5e d0 movdqu -0x30(%rsi),%xmm3 - 434552: f3 0f 6f 66 c0 movdqu -0x40(%rsi),%xmm4 - 434557: f3 0f 6f 6e b0 movdqu -0x50(%rsi),%xmm5 - 43455c: f3 0f 6f 76 a0 movdqu -0x60(%rsi),%xmm6 - 434561: f3 0f 6f 7e 90 movdqu -0x70(%rsi),%xmm7 - 434566: f3 44 0f 6f 46 80 movdqu -0x80(%rsi),%xmm8 - 43456c: 66 0f 7f 4f f0 movdqa %xmm1,-0x10(%rdi) - 434571: 66 0f 7f 57 e0 movdqa %xmm2,-0x20(%rdi) - 434576: 66 0f 7f 5f d0 movdqa %xmm3,-0x30(%rdi) - 43457b: 66 0f 7f 67 c0 movdqa %xmm4,-0x40(%rdi) - 434580: 66 0f 7f 6f b0 movdqa %xmm5,-0x50(%rdi) - 434585: 66 0f 7f 77 a0 movdqa %xmm6,-0x60(%rdi) - 43458a: 66 0f 7f 7f 90 movdqa %xmm7,-0x70(%rdi) - 43458f: 66 44 0f 7f 47 80 movdqa %xmm8,-0x80(%rdi) - 434595: 48 8d 76 80 lea -0x80(%rsi),%rsi - 434599: 48 8d 7f 80 lea -0x80(%rdi),%rdi - 43459d: 73 81 jae 434520 <__memmove_ssse3_back+0x1b60> - 43459f: f3 41 0f 7f 00 movdqu %xmm0,(%r8) - 4345a4: 48 81 c2 80 00 00 00 add $0x80,%rdx - 4345ab: 48 29 d6 sub %rdx,%rsi - 4345ae: 48 29 d7 sub %rdx,%rdi - 4345b1: 4c 8d 1d b8 ef 06 00 lea 0x6efb8(%rip),%r11 # 4a3570 - 4345b8: 49 63 14 93 movslq (%r11,%rdx,4),%rdx - 4345bc: 49 8d 14 13 lea (%r11,%rdx,1),%rdx - 4345c0: ff e2 jmpq *%rdx - 4345c2: 0f 0b ud2 - 4345c4: 66 90 xchg %ax,%ax - 4345c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4345cd: 00 00 00 - 4345d0: f2 0f f0 46 80 lddqu -0x80(%rsi),%xmm0 - 4345d5: f3 0f 7f 47 80 movdqu %xmm0,-0x80(%rdi) - 4345da: f2 0f f0 46 90 lddqu -0x70(%rsi),%xmm0 - 4345df: f3 0f 7f 47 90 movdqu %xmm0,-0x70(%rdi) - 4345e4: f2 0f f0 46 a0 lddqu -0x60(%rsi),%xmm0 - 4345e9: f3 0f 7f 47 a0 movdqu %xmm0,-0x60(%rdi) - 4345ee: f2 0f f0 46 b0 lddqu -0x50(%rsi),%xmm0 - 4345f3: f3 0f 7f 47 b0 movdqu %xmm0,-0x50(%rdi) - 4345f8: f2 0f f0 46 c0 lddqu -0x40(%rsi),%xmm0 - 4345fd: f3 0f 7f 47 c0 movdqu %xmm0,-0x40(%rdi) - 434602: f2 0f f0 46 d0 lddqu -0x30(%rsi),%xmm0 - 434607: f3 0f 7f 47 d0 movdqu %xmm0,-0x30(%rdi) - 43460c: f2 0f f0 46 e0 lddqu -0x20(%rsi),%xmm0 - 434611: f3 0f 7f 47 e0 movdqu %xmm0,-0x20(%rdi) - 434616: f2 0f f0 46 f0 lddqu -0x10(%rsi),%xmm0 - 43461b: f3 0f 7f 47 f0 movdqu %xmm0,-0x10(%rdi) - 434620: c3 retq - 434621: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 434626: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43462d: 00 00 00 - 434630: f2 0f f0 86 71 ff ff lddqu -0x8f(%rsi),%xmm0 - 434637: ff - 434638: f3 0f 7f 87 71 ff ff movdqu %xmm0,-0x8f(%rdi) - 43463f: ff - 434640: f2 0f f0 46 81 lddqu -0x7f(%rsi),%xmm0 - 434645: f3 0f 7f 47 81 movdqu %xmm0,-0x7f(%rdi) - 43464a: f2 0f f0 46 91 lddqu -0x6f(%rsi),%xmm0 - 43464f: f3 0f 7f 47 91 movdqu %xmm0,-0x6f(%rdi) - 434654: f2 0f f0 46 a1 lddqu -0x5f(%rsi),%xmm0 - 434659: f3 0f 7f 47 a1 movdqu %xmm0,-0x5f(%rdi) - 43465e: f2 0f f0 46 b1 lddqu -0x4f(%rsi),%xmm0 - 434663: f3 0f 7f 47 b1 movdqu %xmm0,-0x4f(%rdi) - 434668: f2 0f f0 46 c1 lddqu -0x3f(%rsi),%xmm0 - 43466d: f3 0f 7f 47 c1 movdqu %xmm0,-0x3f(%rdi) - 434672: f2 0f f0 46 d1 lddqu -0x2f(%rsi),%xmm0 - 434677: f3 0f 7f 47 d1 movdqu %xmm0,-0x2f(%rdi) - 43467c: f2 0f f0 46 e1 lddqu -0x1f(%rsi),%xmm0 - 434681: f2 0f f0 4e f0 lddqu -0x10(%rsi),%xmm1 - 434686: f3 0f 7f 47 e1 movdqu %xmm0,-0x1f(%rdi) - 43468b: f3 0f 7f 4f f0 movdqu %xmm1,-0x10(%rdi) - 434690: c3 retq - 434691: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 434696: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43469d: 00 00 00 - 4346a0: 48 8b 56 f1 mov -0xf(%rsi),%rdx - 4346a4: 48 8b 4e f8 mov -0x8(%rsi),%rcx - 4346a8: 48 89 57 f1 mov %rdx,-0xf(%rdi) - 4346ac: 48 89 4f f8 mov %rcx,-0x8(%rdi) - 4346b0: c3 retq - 4346b1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4346b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4346bd: 00 00 00 - 4346c0: f2 0f f0 86 72 ff ff lddqu -0x8e(%rsi),%xmm0 - 4346c7: ff - 4346c8: f3 0f 7f 87 72 ff ff movdqu %xmm0,-0x8e(%rdi) - 4346cf: ff - 4346d0: f2 0f f0 46 82 lddqu -0x7e(%rsi),%xmm0 - 4346d5: f3 0f 7f 47 82 movdqu %xmm0,-0x7e(%rdi) - 4346da: f2 0f f0 46 92 lddqu -0x6e(%rsi),%xmm0 - 4346df: f3 0f 7f 47 92 movdqu %xmm0,-0x6e(%rdi) - 4346e4: f2 0f f0 46 a2 lddqu -0x5e(%rsi),%xmm0 - 4346e9: f3 0f 7f 47 a2 movdqu %xmm0,-0x5e(%rdi) - 4346ee: f2 0f f0 46 b2 lddqu -0x4e(%rsi),%xmm0 - 4346f3: f3 0f 7f 47 b2 movdqu %xmm0,-0x4e(%rdi) - 4346f8: f2 0f f0 46 c2 lddqu -0x3e(%rsi),%xmm0 - 4346fd: f3 0f 7f 47 c2 movdqu %xmm0,-0x3e(%rdi) - 434702: f2 0f f0 46 d2 lddqu -0x2e(%rsi),%xmm0 - 434707: f3 0f 7f 47 d2 movdqu %xmm0,-0x2e(%rdi) - 43470c: f2 0f f0 46 e2 lddqu -0x1e(%rsi),%xmm0 - 434711: f2 0f f0 4e f0 lddqu -0x10(%rsi),%xmm1 - 434716: f3 0f 7f 47 e2 movdqu %xmm0,-0x1e(%rdi) - 43471b: f3 0f 7f 4f f0 movdqu %xmm1,-0x10(%rdi) - 434720: c3 retq - 434721: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 434726: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43472d: 00 00 00 - 434730: 48 8b 56 f2 mov -0xe(%rsi),%rdx - 434734: 48 8b 4e f8 mov -0x8(%rsi),%rcx - 434738: 48 89 57 f2 mov %rdx,-0xe(%rdi) - 43473c: 48 89 4f f8 mov %rcx,-0x8(%rdi) - 434740: c3 retq - 434741: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 434746: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43474d: 00 00 00 - 434750: f2 0f f0 86 73 ff ff lddqu -0x8d(%rsi),%xmm0 - 434757: ff - 434758: f3 0f 7f 87 73 ff ff movdqu %xmm0,-0x8d(%rdi) - 43475f: ff - 434760: f2 0f f0 46 83 lddqu -0x7d(%rsi),%xmm0 - 434765: f3 0f 7f 47 83 movdqu %xmm0,-0x7d(%rdi) - 43476a: f2 0f f0 46 93 lddqu -0x6d(%rsi),%xmm0 - 43476f: f3 0f 7f 47 93 movdqu %xmm0,-0x6d(%rdi) - 434774: f2 0f f0 46 a3 lddqu -0x5d(%rsi),%xmm0 - 434779: f3 0f 7f 47 a3 movdqu %xmm0,-0x5d(%rdi) - 43477e: f2 0f f0 46 b3 lddqu -0x4d(%rsi),%xmm0 - 434783: f3 0f 7f 47 b3 movdqu %xmm0,-0x4d(%rdi) - 434788: f2 0f f0 46 c3 lddqu -0x3d(%rsi),%xmm0 - 43478d: f3 0f 7f 47 c3 movdqu %xmm0,-0x3d(%rdi) - 434792: f2 0f f0 46 d3 lddqu -0x2d(%rsi),%xmm0 - 434797: f3 0f 7f 47 d3 movdqu %xmm0,-0x2d(%rdi) - 43479c: f2 0f f0 46 e3 lddqu -0x1d(%rsi),%xmm0 - 4347a1: f2 0f f0 4e f0 lddqu -0x10(%rsi),%xmm1 - 4347a6: f3 0f 7f 47 e3 movdqu %xmm0,-0x1d(%rdi) - 4347ab: f3 0f 7f 4f f0 movdqu %xmm1,-0x10(%rdi) - 4347b0: c3 retq - 4347b1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4347b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4347bd: 00 00 00 - 4347c0: 48 8b 56 f3 mov -0xd(%rsi),%rdx - 4347c4: 48 8b 4e f8 mov -0x8(%rsi),%rcx - 4347c8: 48 89 57 f3 mov %rdx,-0xd(%rdi) - 4347cc: 48 89 4f f8 mov %rcx,-0x8(%rdi) - 4347d0: c3 retq - 4347d1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4347d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4347dd: 00 00 00 - 4347e0: f2 0f f0 86 74 ff ff lddqu -0x8c(%rsi),%xmm0 - 4347e7: ff - 4347e8: f3 0f 7f 87 74 ff ff movdqu %xmm0,-0x8c(%rdi) - 4347ef: ff - 4347f0: f2 0f f0 46 84 lddqu -0x7c(%rsi),%xmm0 - 4347f5: f3 0f 7f 47 84 movdqu %xmm0,-0x7c(%rdi) - 4347fa: f2 0f f0 46 94 lddqu -0x6c(%rsi),%xmm0 - 4347ff: f3 0f 7f 47 94 movdqu %xmm0,-0x6c(%rdi) - 434804: f2 0f f0 46 a4 lddqu -0x5c(%rsi),%xmm0 - 434809: f3 0f 7f 47 a4 movdqu %xmm0,-0x5c(%rdi) - 43480e: f2 0f f0 46 b4 lddqu -0x4c(%rsi),%xmm0 - 434813: f3 0f 7f 47 b4 movdqu %xmm0,-0x4c(%rdi) - 434818: f2 0f f0 46 c4 lddqu -0x3c(%rsi),%xmm0 - 43481d: f3 0f 7f 47 c4 movdqu %xmm0,-0x3c(%rdi) - 434822: f2 0f f0 46 d4 lddqu -0x2c(%rsi),%xmm0 - 434827: f3 0f 7f 47 d4 movdqu %xmm0,-0x2c(%rdi) - 43482c: f2 0f f0 46 e4 lddqu -0x1c(%rsi),%xmm0 - 434831: f2 0f f0 4e f0 lddqu -0x10(%rsi),%xmm1 - 434836: f3 0f 7f 47 e4 movdqu %xmm0,-0x1c(%rdi) - 43483b: f3 0f 7f 4f f0 movdqu %xmm1,-0x10(%rdi) - 434840: c3 retq - 434841: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 434846: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43484d: 00 00 00 - 434850: 48 8b 56 f4 mov -0xc(%rsi),%rdx - 434854: 8b 4e fc mov -0x4(%rsi),%ecx - 434857: 48 89 57 f4 mov %rdx,-0xc(%rdi) - 43485b: 89 4f fc mov %ecx,-0x4(%rdi) - 43485e: c3 retq - 43485f: 90 nop - 434860: f2 0f f0 86 75 ff ff lddqu -0x8b(%rsi),%xmm0 - 434867: ff - 434868: f3 0f 7f 87 75 ff ff movdqu %xmm0,-0x8b(%rdi) - 43486f: ff - 434870: f2 0f f0 46 85 lddqu -0x7b(%rsi),%xmm0 - 434875: f3 0f 7f 47 85 movdqu %xmm0,-0x7b(%rdi) - 43487a: f2 0f f0 46 95 lddqu -0x6b(%rsi),%xmm0 - 43487f: f3 0f 7f 47 95 movdqu %xmm0,-0x6b(%rdi) - 434884: f2 0f f0 46 a5 lddqu -0x5b(%rsi),%xmm0 - 434889: f3 0f 7f 47 a5 movdqu %xmm0,-0x5b(%rdi) - 43488e: f2 0f f0 46 b5 lddqu -0x4b(%rsi),%xmm0 - 434893: f3 0f 7f 47 b5 movdqu %xmm0,-0x4b(%rdi) - 434898: f2 0f f0 46 c5 lddqu -0x3b(%rsi),%xmm0 - 43489d: f3 0f 7f 47 c5 movdqu %xmm0,-0x3b(%rdi) - 4348a2: f2 0f f0 46 d5 lddqu -0x2b(%rsi),%xmm0 - 4348a7: f3 0f 7f 47 d5 movdqu %xmm0,-0x2b(%rdi) - 4348ac: f2 0f f0 46 e5 lddqu -0x1b(%rsi),%xmm0 - 4348b1: f2 0f f0 4e f0 lddqu -0x10(%rsi),%xmm1 - 4348b6: f3 0f 7f 47 e5 movdqu %xmm0,-0x1b(%rdi) - 4348bb: f3 0f 7f 4f f0 movdqu %xmm1,-0x10(%rdi) - 4348c0: c3 retq - 4348c1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4348c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4348cd: 00 00 00 - 4348d0: 48 8b 56 f5 mov -0xb(%rsi),%rdx - 4348d4: 8b 4e fc mov -0x4(%rsi),%ecx - 4348d7: 48 89 57 f5 mov %rdx,-0xb(%rdi) - 4348db: 89 4f fc mov %ecx,-0x4(%rdi) - 4348de: c3 retq - 4348df: 90 nop - 4348e0: f2 0f f0 86 76 ff ff lddqu -0x8a(%rsi),%xmm0 - 4348e7: ff - 4348e8: f3 0f 7f 87 76 ff ff movdqu %xmm0,-0x8a(%rdi) - 4348ef: ff - 4348f0: f2 0f f0 46 86 lddqu -0x7a(%rsi),%xmm0 - 4348f5: f3 0f 7f 47 86 movdqu %xmm0,-0x7a(%rdi) - 4348fa: f2 0f f0 46 96 lddqu -0x6a(%rsi),%xmm0 - 4348ff: f3 0f 7f 47 96 movdqu %xmm0,-0x6a(%rdi) - 434904: f2 0f f0 46 a6 lddqu -0x5a(%rsi),%xmm0 - 434909: f3 0f 7f 47 a6 movdqu %xmm0,-0x5a(%rdi) - 43490e: f2 0f f0 46 b6 lddqu -0x4a(%rsi),%xmm0 - 434913: f3 0f 7f 47 b6 movdqu %xmm0,-0x4a(%rdi) - 434918: f2 0f f0 46 c6 lddqu -0x3a(%rsi),%xmm0 - 43491d: f3 0f 7f 47 c6 movdqu %xmm0,-0x3a(%rdi) - 434922: f2 0f f0 46 d6 lddqu -0x2a(%rsi),%xmm0 - 434927: f3 0f 7f 47 d6 movdqu %xmm0,-0x2a(%rdi) - 43492c: f2 0f f0 46 e6 lddqu -0x1a(%rsi),%xmm0 - 434931: f2 0f f0 4e f0 lddqu -0x10(%rsi),%xmm1 - 434936: f3 0f 7f 47 e6 movdqu %xmm0,-0x1a(%rdi) - 43493b: f3 0f 7f 4f f0 movdqu %xmm1,-0x10(%rdi) - 434940: c3 retq - 434941: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 434946: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43494d: 00 00 00 - 434950: 48 8b 56 f6 mov -0xa(%rsi),%rdx - 434954: 8b 4e fc mov -0x4(%rsi),%ecx - 434957: 48 89 57 f6 mov %rdx,-0xa(%rdi) - 43495b: 89 4f fc mov %ecx,-0x4(%rdi) - 43495e: c3 retq - 43495f: 90 nop - 434960: f2 0f f0 86 77 ff ff lddqu -0x89(%rsi),%xmm0 - 434967: ff - 434968: f3 0f 7f 87 77 ff ff movdqu %xmm0,-0x89(%rdi) - 43496f: ff - 434970: f2 0f f0 46 87 lddqu -0x79(%rsi),%xmm0 - 434975: f3 0f 7f 47 87 movdqu %xmm0,-0x79(%rdi) - 43497a: f2 0f f0 46 97 lddqu -0x69(%rsi),%xmm0 - 43497f: f3 0f 7f 47 97 movdqu %xmm0,-0x69(%rdi) - 434984: f2 0f f0 46 a7 lddqu -0x59(%rsi),%xmm0 - 434989: f3 0f 7f 47 a7 movdqu %xmm0,-0x59(%rdi) - 43498e: f2 0f f0 46 b7 lddqu -0x49(%rsi),%xmm0 - 434993: f3 0f 7f 47 b7 movdqu %xmm0,-0x49(%rdi) - 434998: f2 0f f0 46 c7 lddqu -0x39(%rsi),%xmm0 - 43499d: f3 0f 7f 47 c7 movdqu %xmm0,-0x39(%rdi) - 4349a2: f2 0f f0 46 d7 lddqu -0x29(%rsi),%xmm0 - 4349a7: f3 0f 7f 47 d7 movdqu %xmm0,-0x29(%rdi) - 4349ac: f2 0f f0 46 e7 lddqu -0x19(%rsi),%xmm0 - 4349b1: f2 0f f0 4e f0 lddqu -0x10(%rsi),%xmm1 - 4349b6: f3 0f 7f 47 e7 movdqu %xmm0,-0x19(%rdi) - 4349bb: f3 0f 7f 4f f0 movdqu %xmm1,-0x10(%rdi) - 4349c0: c3 retq - 4349c1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4349c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4349cd: 00 00 00 - 4349d0: 48 8b 56 f7 mov -0x9(%rsi),%rdx - 4349d4: 8b 4e fc mov -0x4(%rsi),%ecx - 4349d7: 48 89 57 f7 mov %rdx,-0x9(%rdi) - 4349db: 89 4f fc mov %ecx,-0x4(%rdi) - 4349de: c3 retq - 4349df: 90 nop - 4349e0: f2 0f f0 86 78 ff ff lddqu -0x88(%rsi),%xmm0 - 4349e7: ff - 4349e8: f3 0f 7f 87 78 ff ff movdqu %xmm0,-0x88(%rdi) - 4349ef: ff - 4349f0: f2 0f f0 46 88 lddqu -0x78(%rsi),%xmm0 - 4349f5: f3 0f 7f 47 88 movdqu %xmm0,-0x78(%rdi) - 4349fa: f2 0f f0 46 98 lddqu -0x68(%rsi),%xmm0 - 4349ff: f3 0f 7f 47 98 movdqu %xmm0,-0x68(%rdi) - 434a04: f2 0f f0 46 a8 lddqu -0x58(%rsi),%xmm0 - 434a09: f3 0f 7f 47 a8 movdqu %xmm0,-0x58(%rdi) - 434a0e: f2 0f f0 46 b8 lddqu -0x48(%rsi),%xmm0 - 434a13: f3 0f 7f 47 b8 movdqu %xmm0,-0x48(%rdi) - 434a18: f2 0f f0 46 c8 lddqu -0x38(%rsi),%xmm0 - 434a1d: f3 0f 7f 47 c8 movdqu %xmm0,-0x38(%rdi) - 434a22: f2 0f f0 46 d8 lddqu -0x28(%rsi),%xmm0 - 434a27: f3 0f 7f 47 d8 movdqu %xmm0,-0x28(%rdi) - 434a2c: f2 0f f0 46 e8 lddqu -0x18(%rsi),%xmm0 - 434a31: f2 0f f0 4e f0 lddqu -0x10(%rsi),%xmm1 - 434a36: f3 0f 7f 47 e8 movdqu %xmm0,-0x18(%rdi) - 434a3b: f3 0f 7f 4f f0 movdqu %xmm1,-0x10(%rdi) - 434a40: c3 retq - 434a41: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 434a46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 434a4d: 00 00 00 - 434a50: 48 8b 56 f8 mov -0x8(%rsi),%rdx - 434a54: 48 89 57 f8 mov %rdx,-0x8(%rdi) - 434a58: c3 retq - 434a59: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 434a60: f2 0f f0 86 79 ff ff lddqu -0x87(%rsi),%xmm0 - 434a67: ff - 434a68: f3 0f 7f 87 79 ff ff movdqu %xmm0,-0x87(%rdi) - 434a6f: ff - 434a70: f2 0f f0 46 89 lddqu -0x77(%rsi),%xmm0 - 434a75: f3 0f 7f 47 89 movdqu %xmm0,-0x77(%rdi) - 434a7a: f2 0f f0 46 99 lddqu -0x67(%rsi),%xmm0 - 434a7f: f3 0f 7f 47 99 movdqu %xmm0,-0x67(%rdi) - 434a84: f2 0f f0 46 a9 lddqu -0x57(%rsi),%xmm0 - 434a89: f3 0f 7f 47 a9 movdqu %xmm0,-0x57(%rdi) - 434a8e: f2 0f f0 46 b9 lddqu -0x47(%rsi),%xmm0 - 434a93: f3 0f 7f 47 b9 movdqu %xmm0,-0x47(%rdi) - 434a98: f2 0f f0 46 c9 lddqu -0x37(%rsi),%xmm0 - 434a9d: f3 0f 7f 47 c9 movdqu %xmm0,-0x37(%rdi) - 434aa2: f2 0f f0 46 d9 lddqu -0x27(%rsi),%xmm0 - 434aa7: f3 0f 7f 47 d9 movdqu %xmm0,-0x27(%rdi) - 434aac: f2 0f f0 46 e9 lddqu -0x17(%rsi),%xmm0 - 434ab1: f2 0f f0 4e f0 lddqu -0x10(%rsi),%xmm1 - 434ab6: f3 0f 7f 47 e9 movdqu %xmm0,-0x17(%rdi) - 434abb: f3 0f 7f 4f f0 movdqu %xmm1,-0x10(%rdi) - 434ac0: c3 retq - 434ac1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 434ac6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 434acd: 00 00 00 - 434ad0: 8b 56 f9 mov -0x7(%rsi),%edx - 434ad3: 8b 4e fc mov -0x4(%rsi),%ecx - 434ad6: 89 57 f9 mov %edx,-0x7(%rdi) - 434ad9: 89 4f fc mov %ecx,-0x4(%rdi) - 434adc: c3 retq - 434add: 0f 1f 00 nopl (%rax) - 434ae0: f2 0f f0 86 7a ff ff lddqu -0x86(%rsi),%xmm0 - 434ae7: ff - 434ae8: f3 0f 7f 87 7a ff ff movdqu %xmm0,-0x86(%rdi) - 434aef: ff - 434af0: f2 0f f0 46 8a lddqu -0x76(%rsi),%xmm0 - 434af5: f3 0f 7f 47 8a movdqu %xmm0,-0x76(%rdi) - 434afa: f2 0f f0 46 9a lddqu -0x66(%rsi),%xmm0 - 434aff: f3 0f 7f 47 9a movdqu %xmm0,-0x66(%rdi) - 434b04: f2 0f f0 46 aa lddqu -0x56(%rsi),%xmm0 - 434b09: f3 0f 7f 47 aa movdqu %xmm0,-0x56(%rdi) - 434b0e: f2 0f f0 46 ba lddqu -0x46(%rsi),%xmm0 - 434b13: f3 0f 7f 47 ba movdqu %xmm0,-0x46(%rdi) - 434b18: f2 0f f0 46 ca lddqu -0x36(%rsi),%xmm0 - 434b1d: f3 0f 7f 47 ca movdqu %xmm0,-0x36(%rdi) - 434b22: f2 0f f0 46 da lddqu -0x26(%rsi),%xmm0 - 434b27: f3 0f 7f 47 da movdqu %xmm0,-0x26(%rdi) - 434b2c: f2 0f f0 46 ea lddqu -0x16(%rsi),%xmm0 - 434b31: f2 0f f0 4e f0 lddqu -0x10(%rsi),%xmm1 - 434b36: f3 0f 7f 47 ea movdqu %xmm0,-0x16(%rdi) - 434b3b: f3 0f 7f 4f f0 movdqu %xmm1,-0x10(%rdi) - 434b40: c3 retq - 434b41: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 434b46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 434b4d: 00 00 00 - 434b50: 8b 56 fa mov -0x6(%rsi),%edx - 434b53: 8b 4e fc mov -0x4(%rsi),%ecx - 434b56: 89 57 fa mov %edx,-0x6(%rdi) - 434b59: 89 4f fc mov %ecx,-0x4(%rdi) - 434b5c: c3 retq - 434b5d: 0f 1f 00 nopl (%rax) - 434b60: f2 0f f0 86 7b ff ff lddqu -0x85(%rsi),%xmm0 - 434b67: ff - 434b68: f3 0f 7f 87 7b ff ff movdqu %xmm0,-0x85(%rdi) - 434b6f: ff - 434b70: f2 0f f0 46 8b lddqu -0x75(%rsi),%xmm0 - 434b75: f3 0f 7f 47 8b movdqu %xmm0,-0x75(%rdi) - 434b7a: f2 0f f0 46 9b lddqu -0x65(%rsi),%xmm0 - 434b7f: f3 0f 7f 47 9b movdqu %xmm0,-0x65(%rdi) - 434b84: f2 0f f0 46 ab lddqu -0x55(%rsi),%xmm0 - 434b89: f3 0f 7f 47 ab movdqu %xmm0,-0x55(%rdi) - 434b8e: f2 0f f0 46 bb lddqu -0x45(%rsi),%xmm0 - 434b93: f3 0f 7f 47 bb movdqu %xmm0,-0x45(%rdi) - 434b98: f2 0f f0 46 cb lddqu -0x35(%rsi),%xmm0 - 434b9d: f3 0f 7f 47 cb movdqu %xmm0,-0x35(%rdi) - 434ba2: f2 0f f0 46 db lddqu -0x25(%rsi),%xmm0 - 434ba7: f3 0f 7f 47 db movdqu %xmm0,-0x25(%rdi) - 434bac: f2 0f f0 46 eb lddqu -0x15(%rsi),%xmm0 - 434bb1: f2 0f f0 4e f0 lddqu -0x10(%rsi),%xmm1 - 434bb6: f3 0f 7f 47 eb movdqu %xmm0,-0x15(%rdi) - 434bbb: f3 0f 7f 4f f0 movdqu %xmm1,-0x10(%rdi) - 434bc0: c3 retq - 434bc1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 434bc6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 434bcd: 00 00 00 - 434bd0: 8b 56 fb mov -0x5(%rsi),%edx - 434bd3: 8b 4e fc mov -0x4(%rsi),%ecx - 434bd6: 89 57 fb mov %edx,-0x5(%rdi) - 434bd9: 89 4f fc mov %ecx,-0x4(%rdi) - 434bdc: c3 retq - 434bdd: 0f 1f 00 nopl (%rax) - 434be0: f2 0f f0 86 7c ff ff lddqu -0x84(%rsi),%xmm0 - 434be7: ff - 434be8: f3 0f 7f 87 7c ff ff movdqu %xmm0,-0x84(%rdi) - 434bef: ff - 434bf0: f2 0f f0 46 8c lddqu -0x74(%rsi),%xmm0 - 434bf5: f3 0f 7f 47 8c movdqu %xmm0,-0x74(%rdi) - 434bfa: f2 0f f0 46 9c lddqu -0x64(%rsi),%xmm0 - 434bff: f3 0f 7f 47 9c movdqu %xmm0,-0x64(%rdi) - 434c04: f2 0f f0 46 ac lddqu -0x54(%rsi),%xmm0 - 434c09: f3 0f 7f 47 ac movdqu %xmm0,-0x54(%rdi) - 434c0e: f2 0f f0 46 bc lddqu -0x44(%rsi),%xmm0 - 434c13: f3 0f 7f 47 bc movdqu %xmm0,-0x44(%rdi) - 434c18: f2 0f f0 46 cc lddqu -0x34(%rsi),%xmm0 - 434c1d: f3 0f 7f 47 cc movdqu %xmm0,-0x34(%rdi) - 434c22: f2 0f f0 46 dc lddqu -0x24(%rsi),%xmm0 - 434c27: f3 0f 7f 47 dc movdqu %xmm0,-0x24(%rdi) - 434c2c: f2 0f f0 46 ec lddqu -0x14(%rsi),%xmm0 - 434c31: f2 0f f0 4e f0 lddqu -0x10(%rsi),%xmm1 - 434c36: f3 0f 7f 47 ec movdqu %xmm0,-0x14(%rdi) - 434c3b: f3 0f 7f 4f f0 movdqu %xmm1,-0x10(%rdi) - 434c40: c3 retq - 434c41: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 434c46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 434c4d: 00 00 00 - 434c50: 8b 56 fc mov -0x4(%rsi),%edx - 434c53: 89 57 fc mov %edx,-0x4(%rdi) - 434c56: c3 retq - 434c57: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 434c5e: 00 00 - 434c60: f2 0f f0 86 7d ff ff lddqu -0x83(%rsi),%xmm0 - 434c67: ff - 434c68: f3 0f 7f 87 7d ff ff movdqu %xmm0,-0x83(%rdi) - 434c6f: ff - 434c70: f2 0f f0 46 8d lddqu -0x73(%rsi),%xmm0 - 434c75: f3 0f 7f 47 8d movdqu %xmm0,-0x73(%rdi) - 434c7a: f2 0f f0 46 9d lddqu -0x63(%rsi),%xmm0 - 434c7f: f3 0f 7f 47 9d movdqu %xmm0,-0x63(%rdi) - 434c84: f2 0f f0 46 ad lddqu -0x53(%rsi),%xmm0 - 434c89: f3 0f 7f 47 ad movdqu %xmm0,-0x53(%rdi) - 434c8e: f2 0f f0 46 bd lddqu -0x43(%rsi),%xmm0 - 434c93: f3 0f 7f 47 bd movdqu %xmm0,-0x43(%rdi) - 434c98: f2 0f f0 46 cd lddqu -0x33(%rsi),%xmm0 - 434c9d: f3 0f 7f 47 cd movdqu %xmm0,-0x33(%rdi) - 434ca2: f2 0f f0 46 dd lddqu -0x23(%rsi),%xmm0 - 434ca7: f3 0f 7f 47 dd movdqu %xmm0,-0x23(%rdi) - 434cac: f2 0f f0 46 ed lddqu -0x13(%rsi),%xmm0 - 434cb1: f2 0f f0 4e f0 lddqu -0x10(%rsi),%xmm1 - 434cb6: f3 0f 7f 47 ed movdqu %xmm0,-0x13(%rdi) - 434cbb: f3 0f 7f 4f f0 movdqu %xmm1,-0x10(%rdi) - 434cc0: c3 retq - 434cc1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 434cc6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 434ccd: 00 00 00 - 434cd0: 66 8b 56 fd mov -0x3(%rsi),%dx - 434cd4: 66 8b 4e fe mov -0x2(%rsi),%cx - 434cd8: 66 89 57 fd mov %dx,-0x3(%rdi) - 434cdc: 66 89 4f fe mov %cx,-0x2(%rdi) - 434ce0: c3 retq - 434ce1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 434ce6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 434ced: 00 00 00 - 434cf0: f2 0f f0 86 7e ff ff lddqu -0x82(%rsi),%xmm0 - 434cf7: ff - 434cf8: f3 0f 7f 87 7e ff ff movdqu %xmm0,-0x82(%rdi) - 434cff: ff - 434d00: f2 0f f0 46 8e lddqu -0x72(%rsi),%xmm0 - 434d05: f3 0f 7f 47 8e movdqu %xmm0,-0x72(%rdi) - 434d0a: f2 0f f0 46 9e lddqu -0x62(%rsi),%xmm0 - 434d0f: f3 0f 7f 47 9e movdqu %xmm0,-0x62(%rdi) - 434d14: f2 0f f0 46 ae lddqu -0x52(%rsi),%xmm0 - 434d19: f3 0f 7f 47 ae movdqu %xmm0,-0x52(%rdi) - 434d1e: f2 0f f0 46 be lddqu -0x42(%rsi),%xmm0 - 434d23: f3 0f 7f 47 be movdqu %xmm0,-0x42(%rdi) - 434d28: f2 0f f0 46 ce lddqu -0x32(%rsi),%xmm0 - 434d2d: f3 0f 7f 47 ce movdqu %xmm0,-0x32(%rdi) - 434d32: f2 0f f0 46 de lddqu -0x22(%rsi),%xmm0 - 434d37: f3 0f 7f 47 de movdqu %xmm0,-0x22(%rdi) - 434d3c: f2 0f f0 46 ee lddqu -0x12(%rsi),%xmm0 - 434d41: f2 0f f0 4e f0 lddqu -0x10(%rsi),%xmm1 - 434d46: f3 0f 7f 47 ee movdqu %xmm0,-0x12(%rdi) - 434d4b: f3 0f 7f 4f f0 movdqu %xmm1,-0x10(%rdi) - 434d50: c3 retq - 434d51: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 434d56: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 434d5d: 00 00 00 - 434d60: 0f b7 56 fe movzwl -0x2(%rsi),%edx - 434d64: 66 89 57 fe mov %dx,-0x2(%rdi) - 434d68: c3 retq - 434d69: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 434d70: f2 0f f0 86 7f ff ff lddqu -0x81(%rsi),%xmm0 - 434d77: ff - 434d78: f3 0f 7f 87 7f ff ff movdqu %xmm0,-0x81(%rdi) - 434d7f: ff - 434d80: f2 0f f0 46 8f lddqu -0x71(%rsi),%xmm0 - 434d85: f3 0f 7f 47 8f movdqu %xmm0,-0x71(%rdi) - 434d8a: f2 0f f0 46 9f lddqu -0x61(%rsi),%xmm0 - 434d8f: f3 0f 7f 47 9f movdqu %xmm0,-0x61(%rdi) - 434d94: f2 0f f0 46 af lddqu -0x51(%rsi),%xmm0 - 434d99: f3 0f 7f 47 af movdqu %xmm0,-0x51(%rdi) - 434d9e: f2 0f f0 46 bf lddqu -0x41(%rsi),%xmm0 - 434da3: f3 0f 7f 47 bf movdqu %xmm0,-0x41(%rdi) - 434da8: f2 0f f0 46 cf lddqu -0x31(%rsi),%xmm0 - 434dad: f3 0f 7f 47 cf movdqu %xmm0,-0x31(%rdi) - 434db2: f2 0f f0 46 df lddqu -0x21(%rsi),%xmm0 - 434db7: f3 0f 7f 47 df movdqu %xmm0,-0x21(%rdi) - 434dbc: f2 0f f0 46 ef lddqu -0x11(%rsi),%xmm0 - 434dc1: f2 0f f0 4e f0 lddqu -0x10(%rsi),%xmm1 - 434dc6: f3 0f 7f 47 ef movdqu %xmm0,-0x11(%rdi) - 434dcb: f3 0f 7f 4f f0 movdqu %xmm1,-0x10(%rdi) - 434dd0: c3 retq - 434dd1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 434dd6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 434ddd: 00 00 00 - 434de0: 0f b6 56 ff movzbl -0x1(%rsi),%edx - 434de4: 88 57 ff mov %dl,-0x1(%rdi) - 434de7: c3 retq - 434de8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 434def: 00 - 434df0: f2 0f f0 46 70 lddqu 0x70(%rsi),%xmm0 - 434df5: f3 0f 7f 47 70 movdqu %xmm0,0x70(%rdi) - 434dfa: f2 0f f0 46 60 lddqu 0x60(%rsi),%xmm0 - 434dff: f3 0f 7f 47 60 movdqu %xmm0,0x60(%rdi) - 434e04: f2 0f f0 46 50 lddqu 0x50(%rsi),%xmm0 - 434e09: f3 0f 7f 47 50 movdqu %xmm0,0x50(%rdi) - 434e0e: f2 0f f0 46 40 lddqu 0x40(%rsi),%xmm0 - 434e13: f3 0f 7f 47 40 movdqu %xmm0,0x40(%rdi) - 434e18: f2 0f f0 46 30 lddqu 0x30(%rsi),%xmm0 - 434e1d: f3 0f 7f 47 30 movdqu %xmm0,0x30(%rdi) - 434e22: f2 0f f0 46 20 lddqu 0x20(%rsi),%xmm0 - 434e27: f3 0f 7f 47 20 movdqu %xmm0,0x20(%rdi) - 434e2c: f2 0f f0 46 10 lddqu 0x10(%rsi),%xmm0 - 434e31: f3 0f 7f 47 10 movdqu %xmm0,0x10(%rdi) - 434e36: f2 0f f0 06 lddqu (%rsi),%xmm0 - 434e3a: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 434e3e: c3 retq - 434e3f: 90 nop - 434e40: f2 0f f0 46 7f lddqu 0x7f(%rsi),%xmm0 - 434e45: f3 0f 7f 47 7f movdqu %xmm0,0x7f(%rdi) - 434e4a: f2 0f f0 46 6f lddqu 0x6f(%rsi),%xmm0 - 434e4f: f3 0f 7f 47 6f movdqu %xmm0,0x6f(%rdi) - 434e54: f2 0f f0 46 5f lddqu 0x5f(%rsi),%xmm0 - 434e59: f3 0f 7f 47 5f movdqu %xmm0,0x5f(%rdi) - 434e5e: f2 0f f0 46 4f lddqu 0x4f(%rsi),%xmm0 - 434e63: f3 0f 7f 47 4f movdqu %xmm0,0x4f(%rdi) - 434e68: f2 0f f0 46 3f lddqu 0x3f(%rsi),%xmm0 - 434e6d: f3 0f 7f 47 3f movdqu %xmm0,0x3f(%rdi) - 434e72: f2 0f f0 46 2f lddqu 0x2f(%rsi),%xmm0 - 434e77: f3 0f 7f 47 2f movdqu %xmm0,0x2f(%rdi) - 434e7c: f2 0f f0 46 1f lddqu 0x1f(%rsi),%xmm0 - 434e81: f3 0f 7f 47 1f movdqu %xmm0,0x1f(%rdi) - 434e86: f2 0f f0 46 0f lddqu 0xf(%rsi),%xmm0 - 434e8b: f2 0f f0 0e lddqu (%rsi),%xmm1 - 434e8f: f3 0f 7f 47 0f movdqu %xmm0,0xf(%rdi) - 434e94: f3 0f 7f 0f movdqu %xmm1,(%rdi) - 434e98: c3 retq - 434e99: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 434ea0: 48 8b 56 07 mov 0x7(%rsi),%rdx - 434ea4: 48 8b 0e mov (%rsi),%rcx - 434ea7: 48 89 57 07 mov %rdx,0x7(%rdi) - 434eab: 48 89 0f mov %rcx,(%rdi) - 434eae: c3 retq - 434eaf: 90 nop - 434eb0: f2 0f f0 46 7e lddqu 0x7e(%rsi),%xmm0 - 434eb5: f3 0f 7f 47 7e movdqu %xmm0,0x7e(%rdi) - 434eba: f2 0f f0 46 6e lddqu 0x6e(%rsi),%xmm0 - 434ebf: f3 0f 7f 47 6e movdqu %xmm0,0x6e(%rdi) - 434ec4: f2 0f f0 46 5e lddqu 0x5e(%rsi),%xmm0 - 434ec9: f3 0f 7f 47 5e movdqu %xmm0,0x5e(%rdi) - 434ece: f2 0f f0 46 4e lddqu 0x4e(%rsi),%xmm0 - 434ed3: f3 0f 7f 47 4e movdqu %xmm0,0x4e(%rdi) - 434ed8: f2 0f f0 46 3e lddqu 0x3e(%rsi),%xmm0 - 434edd: f3 0f 7f 47 3e movdqu %xmm0,0x3e(%rdi) - 434ee2: f2 0f f0 46 2e lddqu 0x2e(%rsi),%xmm0 - 434ee7: f3 0f 7f 47 2e movdqu %xmm0,0x2e(%rdi) - 434eec: f2 0f f0 46 1e lddqu 0x1e(%rsi),%xmm0 - 434ef1: f3 0f 7f 47 1e movdqu %xmm0,0x1e(%rdi) - 434ef6: f2 0f f0 46 0e lddqu 0xe(%rsi),%xmm0 - 434efb: f2 0f f0 0e lddqu (%rsi),%xmm1 - 434eff: f3 0f 7f 47 0e movdqu %xmm0,0xe(%rdi) - 434f04: f3 0f 7f 0f movdqu %xmm1,(%rdi) - 434f08: c3 retq - 434f09: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 434f10: 48 8b 56 06 mov 0x6(%rsi),%rdx - 434f14: 48 8b 0e mov (%rsi),%rcx - 434f17: 48 89 57 06 mov %rdx,0x6(%rdi) - 434f1b: 48 89 0f mov %rcx,(%rdi) - 434f1e: c3 retq - 434f1f: 90 nop - 434f20: f2 0f f0 46 7d lddqu 0x7d(%rsi),%xmm0 - 434f25: f3 0f 7f 47 7d movdqu %xmm0,0x7d(%rdi) - 434f2a: f2 0f f0 46 6d lddqu 0x6d(%rsi),%xmm0 - 434f2f: f3 0f 7f 47 6d movdqu %xmm0,0x6d(%rdi) - 434f34: f2 0f f0 46 5d lddqu 0x5d(%rsi),%xmm0 - 434f39: f3 0f 7f 47 5d movdqu %xmm0,0x5d(%rdi) - 434f3e: f2 0f f0 46 4d lddqu 0x4d(%rsi),%xmm0 - 434f43: f3 0f 7f 47 4d movdqu %xmm0,0x4d(%rdi) - 434f48: f2 0f f0 46 3d lddqu 0x3d(%rsi),%xmm0 - 434f4d: f3 0f 7f 47 3d movdqu %xmm0,0x3d(%rdi) - 434f52: f2 0f f0 46 2d lddqu 0x2d(%rsi),%xmm0 - 434f57: f3 0f 7f 47 2d movdqu %xmm0,0x2d(%rdi) - 434f5c: f2 0f f0 46 1d lddqu 0x1d(%rsi),%xmm0 - 434f61: f3 0f 7f 47 1d movdqu %xmm0,0x1d(%rdi) - 434f66: f2 0f f0 46 0d lddqu 0xd(%rsi),%xmm0 - 434f6b: f2 0f f0 0e lddqu (%rsi),%xmm1 - 434f6f: f3 0f 7f 47 0d movdqu %xmm0,0xd(%rdi) - 434f74: f3 0f 7f 0f movdqu %xmm1,(%rdi) - 434f78: c3 retq - 434f79: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 434f80: 48 8b 56 05 mov 0x5(%rsi),%rdx - 434f84: 48 8b 0e mov (%rsi),%rcx - 434f87: 48 89 57 05 mov %rdx,0x5(%rdi) - 434f8b: 48 89 0f mov %rcx,(%rdi) - 434f8e: c3 retq - 434f8f: 90 nop - 434f90: f2 0f f0 46 7c lddqu 0x7c(%rsi),%xmm0 - 434f95: f3 0f 7f 47 7c movdqu %xmm0,0x7c(%rdi) - 434f9a: f2 0f f0 46 6c lddqu 0x6c(%rsi),%xmm0 - 434f9f: f3 0f 7f 47 6c movdqu %xmm0,0x6c(%rdi) - 434fa4: f2 0f f0 46 5c lddqu 0x5c(%rsi),%xmm0 - 434fa9: f3 0f 7f 47 5c movdqu %xmm0,0x5c(%rdi) - 434fae: f2 0f f0 46 4c lddqu 0x4c(%rsi),%xmm0 - 434fb3: f3 0f 7f 47 4c movdqu %xmm0,0x4c(%rdi) - 434fb8: f2 0f f0 46 3c lddqu 0x3c(%rsi),%xmm0 - 434fbd: f3 0f 7f 47 3c movdqu %xmm0,0x3c(%rdi) - 434fc2: f2 0f f0 46 2c lddqu 0x2c(%rsi),%xmm0 - 434fc7: f3 0f 7f 47 2c movdqu %xmm0,0x2c(%rdi) - 434fcc: f2 0f f0 46 1c lddqu 0x1c(%rsi),%xmm0 - 434fd1: f3 0f 7f 47 1c movdqu %xmm0,0x1c(%rdi) - 434fd6: f2 0f f0 46 0c lddqu 0xc(%rsi),%xmm0 - 434fdb: f2 0f f0 0e lddqu (%rsi),%xmm1 - 434fdf: f3 0f 7f 47 0c movdqu %xmm0,0xc(%rdi) - 434fe4: f3 0f 7f 0f movdqu %xmm1,(%rdi) - 434fe8: c3 retq - 434fe9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 434ff0: 48 8b 56 04 mov 0x4(%rsi),%rdx - 434ff4: 48 8b 0e mov (%rsi),%rcx - 434ff7: 48 89 57 04 mov %rdx,0x4(%rdi) - 434ffb: 48 89 0f mov %rcx,(%rdi) - 434ffe: c3 retq - 434fff: 90 nop - 435000: f2 0f f0 46 7b lddqu 0x7b(%rsi),%xmm0 - 435005: f3 0f 7f 47 7b movdqu %xmm0,0x7b(%rdi) - 43500a: f2 0f f0 46 6b lddqu 0x6b(%rsi),%xmm0 - 43500f: f3 0f 7f 47 6b movdqu %xmm0,0x6b(%rdi) - 435014: f2 0f f0 46 5b lddqu 0x5b(%rsi),%xmm0 - 435019: f3 0f 7f 47 5b movdqu %xmm0,0x5b(%rdi) - 43501e: f2 0f f0 46 4b lddqu 0x4b(%rsi),%xmm0 - 435023: f3 0f 7f 47 4b movdqu %xmm0,0x4b(%rdi) - 435028: f2 0f f0 46 3b lddqu 0x3b(%rsi),%xmm0 - 43502d: f3 0f 7f 47 3b movdqu %xmm0,0x3b(%rdi) - 435032: f2 0f f0 46 2b lddqu 0x2b(%rsi),%xmm0 - 435037: f3 0f 7f 47 2b movdqu %xmm0,0x2b(%rdi) - 43503c: f2 0f f0 46 1b lddqu 0x1b(%rsi),%xmm0 - 435041: f3 0f 7f 47 1b movdqu %xmm0,0x1b(%rdi) - 435046: f2 0f f0 46 0b lddqu 0xb(%rsi),%xmm0 - 43504b: f2 0f f0 0e lddqu (%rsi),%xmm1 - 43504f: f3 0f 7f 47 0b movdqu %xmm0,0xb(%rdi) - 435054: f3 0f 7f 0f movdqu %xmm1,(%rdi) - 435058: c3 retq - 435059: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 435060: 48 8b 56 03 mov 0x3(%rsi),%rdx - 435064: 48 8b 0e mov (%rsi),%rcx - 435067: 48 89 57 03 mov %rdx,0x3(%rdi) - 43506b: 48 89 0f mov %rcx,(%rdi) - 43506e: c3 retq - 43506f: 90 nop - 435070: f2 0f f0 46 7a lddqu 0x7a(%rsi),%xmm0 - 435075: f3 0f 7f 47 7a movdqu %xmm0,0x7a(%rdi) - 43507a: f2 0f f0 46 6a lddqu 0x6a(%rsi),%xmm0 - 43507f: f3 0f 7f 47 6a movdqu %xmm0,0x6a(%rdi) - 435084: f2 0f f0 46 5a lddqu 0x5a(%rsi),%xmm0 - 435089: f3 0f 7f 47 5a movdqu %xmm0,0x5a(%rdi) - 43508e: f2 0f f0 46 4a lddqu 0x4a(%rsi),%xmm0 - 435093: f3 0f 7f 47 4a movdqu %xmm0,0x4a(%rdi) - 435098: f2 0f f0 46 3a lddqu 0x3a(%rsi),%xmm0 - 43509d: f3 0f 7f 47 3a movdqu %xmm0,0x3a(%rdi) - 4350a2: f2 0f f0 46 2a lddqu 0x2a(%rsi),%xmm0 - 4350a7: f3 0f 7f 47 2a movdqu %xmm0,0x2a(%rdi) - 4350ac: f2 0f f0 46 1a lddqu 0x1a(%rsi),%xmm0 - 4350b1: f3 0f 7f 47 1a movdqu %xmm0,0x1a(%rdi) - 4350b6: f2 0f f0 46 0a lddqu 0xa(%rsi),%xmm0 - 4350bb: f2 0f f0 0e lddqu (%rsi),%xmm1 - 4350bf: f3 0f 7f 47 0a movdqu %xmm0,0xa(%rdi) - 4350c4: f3 0f 7f 0f movdqu %xmm1,(%rdi) - 4350c8: c3 retq - 4350c9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4350d0: 48 8b 56 02 mov 0x2(%rsi),%rdx - 4350d4: 48 8b 0e mov (%rsi),%rcx - 4350d7: 48 89 57 02 mov %rdx,0x2(%rdi) - 4350db: 48 89 0f mov %rcx,(%rdi) - 4350de: c3 retq - 4350df: 90 nop - 4350e0: f2 0f f0 46 79 lddqu 0x79(%rsi),%xmm0 - 4350e5: f3 0f 7f 47 79 movdqu %xmm0,0x79(%rdi) - 4350ea: f2 0f f0 46 69 lddqu 0x69(%rsi),%xmm0 - 4350ef: f3 0f 7f 47 69 movdqu %xmm0,0x69(%rdi) - 4350f4: f2 0f f0 46 59 lddqu 0x59(%rsi),%xmm0 - 4350f9: f3 0f 7f 47 59 movdqu %xmm0,0x59(%rdi) - 4350fe: f2 0f f0 46 49 lddqu 0x49(%rsi),%xmm0 - 435103: f3 0f 7f 47 49 movdqu %xmm0,0x49(%rdi) - 435108: f2 0f f0 46 39 lddqu 0x39(%rsi),%xmm0 - 43510d: f3 0f 7f 47 39 movdqu %xmm0,0x39(%rdi) - 435112: f2 0f f0 46 29 lddqu 0x29(%rsi),%xmm0 - 435117: f3 0f 7f 47 29 movdqu %xmm0,0x29(%rdi) - 43511c: f2 0f f0 46 19 lddqu 0x19(%rsi),%xmm0 - 435121: f3 0f 7f 47 19 movdqu %xmm0,0x19(%rdi) - 435126: f2 0f f0 46 09 lddqu 0x9(%rsi),%xmm0 - 43512b: f2 0f f0 0e lddqu (%rsi),%xmm1 - 43512f: f3 0f 7f 47 09 movdqu %xmm0,0x9(%rdi) - 435134: f3 0f 7f 0f movdqu %xmm1,(%rdi) - 435138: c3 retq - 435139: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 435140: 48 8b 56 01 mov 0x1(%rsi),%rdx - 435144: 48 8b 0e mov (%rsi),%rcx - 435147: 48 89 57 01 mov %rdx,0x1(%rdi) - 43514b: 48 89 0f mov %rcx,(%rdi) - 43514e: c3 retq - 43514f: 90 nop - 435150: f2 0f f0 46 78 lddqu 0x78(%rsi),%xmm0 - 435155: f3 0f 7f 47 78 movdqu %xmm0,0x78(%rdi) - 43515a: f2 0f f0 46 68 lddqu 0x68(%rsi),%xmm0 - 43515f: f3 0f 7f 47 68 movdqu %xmm0,0x68(%rdi) - 435164: f2 0f f0 46 58 lddqu 0x58(%rsi),%xmm0 - 435169: f3 0f 7f 47 58 movdqu %xmm0,0x58(%rdi) - 43516e: f2 0f f0 46 48 lddqu 0x48(%rsi),%xmm0 - 435173: f3 0f 7f 47 48 movdqu %xmm0,0x48(%rdi) - 435178: f2 0f f0 46 38 lddqu 0x38(%rsi),%xmm0 - 43517d: f3 0f 7f 47 38 movdqu %xmm0,0x38(%rdi) - 435182: f2 0f f0 46 28 lddqu 0x28(%rsi),%xmm0 - 435187: f3 0f 7f 47 28 movdqu %xmm0,0x28(%rdi) - 43518c: f2 0f f0 46 18 lddqu 0x18(%rsi),%xmm0 - 435191: f3 0f 7f 47 18 movdqu %xmm0,0x18(%rdi) - 435196: f2 0f f0 46 08 lddqu 0x8(%rsi),%xmm0 - 43519b: f2 0f f0 0e lddqu (%rsi),%xmm1 - 43519f: f3 0f 7f 47 08 movdqu %xmm0,0x8(%rdi) - 4351a4: f3 0f 7f 0f movdqu %xmm1,(%rdi) - 4351a8: c3 retq - 4351a9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4351b0: 48 8b 16 mov (%rsi),%rdx - 4351b3: 48 89 17 mov %rdx,(%rdi) - 4351b6: c3 retq - 4351b7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 4351be: 00 00 - 4351c0: f2 0f f0 46 77 lddqu 0x77(%rsi),%xmm0 - 4351c5: f3 0f 7f 47 77 movdqu %xmm0,0x77(%rdi) - 4351ca: f2 0f f0 46 67 lddqu 0x67(%rsi),%xmm0 - 4351cf: f3 0f 7f 47 67 movdqu %xmm0,0x67(%rdi) - 4351d4: f2 0f f0 46 57 lddqu 0x57(%rsi),%xmm0 - 4351d9: f3 0f 7f 47 57 movdqu %xmm0,0x57(%rdi) - 4351de: f2 0f f0 46 47 lddqu 0x47(%rsi),%xmm0 - 4351e3: f3 0f 7f 47 47 movdqu %xmm0,0x47(%rdi) - 4351e8: f2 0f f0 46 37 lddqu 0x37(%rsi),%xmm0 - 4351ed: f3 0f 7f 47 37 movdqu %xmm0,0x37(%rdi) - 4351f2: f2 0f f0 46 27 lddqu 0x27(%rsi),%xmm0 - 4351f7: f3 0f 7f 47 27 movdqu %xmm0,0x27(%rdi) - 4351fc: f2 0f f0 46 17 lddqu 0x17(%rsi),%xmm0 - 435201: f3 0f 7f 47 17 movdqu %xmm0,0x17(%rdi) - 435206: f2 0f f0 46 07 lddqu 0x7(%rsi),%xmm0 - 43520b: f2 0f f0 0e lddqu (%rsi),%xmm1 - 43520f: f3 0f 7f 47 07 movdqu %xmm0,0x7(%rdi) - 435214: f3 0f 7f 0f movdqu %xmm1,(%rdi) - 435218: c3 retq - 435219: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 435220: 8b 56 03 mov 0x3(%rsi),%edx - 435223: 8b 0e mov (%rsi),%ecx - 435225: 89 57 03 mov %edx,0x3(%rdi) - 435228: 89 0f mov %ecx,(%rdi) - 43522a: c3 retq - 43522b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 435230: f2 0f f0 46 76 lddqu 0x76(%rsi),%xmm0 - 435235: f3 0f 7f 47 76 movdqu %xmm0,0x76(%rdi) - 43523a: f2 0f f0 46 66 lddqu 0x66(%rsi),%xmm0 - 43523f: f3 0f 7f 47 66 movdqu %xmm0,0x66(%rdi) - 435244: f2 0f f0 46 56 lddqu 0x56(%rsi),%xmm0 - 435249: f3 0f 7f 47 56 movdqu %xmm0,0x56(%rdi) - 43524e: f2 0f f0 46 46 lddqu 0x46(%rsi),%xmm0 - 435253: f3 0f 7f 47 46 movdqu %xmm0,0x46(%rdi) - 435258: f2 0f f0 46 36 lddqu 0x36(%rsi),%xmm0 - 43525d: f3 0f 7f 47 36 movdqu %xmm0,0x36(%rdi) - 435262: f2 0f f0 46 26 lddqu 0x26(%rsi),%xmm0 - 435267: f3 0f 7f 47 26 movdqu %xmm0,0x26(%rdi) - 43526c: f2 0f f0 46 16 lddqu 0x16(%rsi),%xmm0 - 435271: f3 0f 7f 47 16 movdqu %xmm0,0x16(%rdi) - 435276: f2 0f f0 46 06 lddqu 0x6(%rsi),%xmm0 - 43527b: f2 0f f0 0e lddqu (%rsi),%xmm1 - 43527f: f3 0f 7f 47 06 movdqu %xmm0,0x6(%rdi) - 435284: f3 0f 7f 0f movdqu %xmm1,(%rdi) - 435288: c3 retq - 435289: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 435290: 8b 56 02 mov 0x2(%rsi),%edx - 435293: 8b 0e mov (%rsi),%ecx - 435295: 89 57 02 mov %edx,0x2(%rdi) - 435298: 89 0f mov %ecx,(%rdi) - 43529a: c3 retq - 43529b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4352a0: f2 0f f0 46 75 lddqu 0x75(%rsi),%xmm0 - 4352a5: f3 0f 7f 47 75 movdqu %xmm0,0x75(%rdi) - 4352aa: f2 0f f0 46 65 lddqu 0x65(%rsi),%xmm0 - 4352af: f3 0f 7f 47 65 movdqu %xmm0,0x65(%rdi) - 4352b4: f2 0f f0 46 55 lddqu 0x55(%rsi),%xmm0 - 4352b9: f3 0f 7f 47 55 movdqu %xmm0,0x55(%rdi) - 4352be: f2 0f f0 46 45 lddqu 0x45(%rsi),%xmm0 - 4352c3: f3 0f 7f 47 45 movdqu %xmm0,0x45(%rdi) - 4352c8: f2 0f f0 46 35 lddqu 0x35(%rsi),%xmm0 - 4352cd: f3 0f 7f 47 35 movdqu %xmm0,0x35(%rdi) - 4352d2: f2 0f f0 46 25 lddqu 0x25(%rsi),%xmm0 - 4352d7: f3 0f 7f 47 25 movdqu %xmm0,0x25(%rdi) - 4352dc: f2 0f f0 46 15 lddqu 0x15(%rsi),%xmm0 - 4352e1: f3 0f 7f 47 15 movdqu %xmm0,0x15(%rdi) - 4352e6: f2 0f f0 46 05 lddqu 0x5(%rsi),%xmm0 - 4352eb: f2 0f f0 0e lddqu (%rsi),%xmm1 - 4352ef: f3 0f 7f 47 05 movdqu %xmm0,0x5(%rdi) - 4352f4: f3 0f 7f 0f movdqu %xmm1,(%rdi) - 4352f8: c3 retq - 4352f9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 435300: 8b 56 01 mov 0x1(%rsi),%edx - 435303: 8b 0e mov (%rsi),%ecx - 435305: 89 57 01 mov %edx,0x1(%rdi) - 435308: 89 0f mov %ecx,(%rdi) - 43530a: c3 retq - 43530b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 435310: f2 0f f0 46 74 lddqu 0x74(%rsi),%xmm0 - 435315: f3 0f 7f 47 74 movdqu %xmm0,0x74(%rdi) - 43531a: f2 0f f0 46 64 lddqu 0x64(%rsi),%xmm0 - 43531f: f3 0f 7f 47 64 movdqu %xmm0,0x64(%rdi) - 435324: f2 0f f0 46 54 lddqu 0x54(%rsi),%xmm0 - 435329: f3 0f 7f 47 54 movdqu %xmm0,0x54(%rdi) - 43532e: f2 0f f0 46 44 lddqu 0x44(%rsi),%xmm0 - 435333: f3 0f 7f 47 44 movdqu %xmm0,0x44(%rdi) - 435338: f2 0f f0 46 34 lddqu 0x34(%rsi),%xmm0 - 43533d: f3 0f 7f 47 34 movdqu %xmm0,0x34(%rdi) - 435342: f2 0f f0 46 24 lddqu 0x24(%rsi),%xmm0 - 435347: f3 0f 7f 47 24 movdqu %xmm0,0x24(%rdi) - 43534c: f2 0f f0 46 14 lddqu 0x14(%rsi),%xmm0 - 435351: f3 0f 7f 47 14 movdqu %xmm0,0x14(%rdi) - 435356: f2 0f f0 46 04 lddqu 0x4(%rsi),%xmm0 - 43535b: f2 0f f0 0e lddqu (%rsi),%xmm1 - 43535f: f3 0f 7f 47 04 movdqu %xmm0,0x4(%rdi) - 435364: f3 0f 7f 0f movdqu %xmm1,(%rdi) - 435368: c3 retq - 435369: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 435370: 8b 16 mov (%rsi),%edx - 435372: 89 17 mov %edx,(%rdi) - 435374: c3 retq - 435375: 90 nop - 435376: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43537d: 00 00 00 - 435380: f2 0f f0 46 73 lddqu 0x73(%rsi),%xmm0 - 435385: f3 0f 7f 47 73 movdqu %xmm0,0x73(%rdi) - 43538a: f2 0f f0 46 63 lddqu 0x63(%rsi),%xmm0 - 43538f: f3 0f 7f 47 63 movdqu %xmm0,0x63(%rdi) - 435394: f2 0f f0 46 53 lddqu 0x53(%rsi),%xmm0 - 435399: f3 0f 7f 47 53 movdqu %xmm0,0x53(%rdi) - 43539e: f2 0f f0 46 43 lddqu 0x43(%rsi),%xmm0 - 4353a3: f3 0f 7f 47 43 movdqu %xmm0,0x43(%rdi) - 4353a8: f2 0f f0 46 33 lddqu 0x33(%rsi),%xmm0 - 4353ad: f3 0f 7f 47 33 movdqu %xmm0,0x33(%rdi) - 4353b2: f2 0f f0 46 23 lddqu 0x23(%rsi),%xmm0 - 4353b7: f3 0f 7f 47 23 movdqu %xmm0,0x23(%rdi) - 4353bc: f2 0f f0 46 13 lddqu 0x13(%rsi),%xmm0 - 4353c1: f3 0f 7f 47 13 movdqu %xmm0,0x13(%rdi) - 4353c6: f2 0f f0 46 03 lddqu 0x3(%rsi),%xmm0 - 4353cb: f2 0f f0 0e lddqu (%rsi),%xmm1 - 4353cf: f3 0f 7f 47 03 movdqu %xmm0,0x3(%rdi) - 4353d4: f3 0f 7f 0f movdqu %xmm1,(%rdi) - 4353d8: c3 retq - 4353d9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4353e0: 66 8b 56 01 mov 0x1(%rsi),%dx - 4353e4: 66 8b 0e mov (%rsi),%cx - 4353e7: 66 89 57 01 mov %dx,0x1(%rdi) - 4353eb: 66 89 0f mov %cx,(%rdi) - 4353ee: c3 retq - 4353ef: 90 nop - 4353f0: f2 0f f0 46 72 lddqu 0x72(%rsi),%xmm0 - 4353f5: f3 0f 7f 47 72 movdqu %xmm0,0x72(%rdi) - 4353fa: f2 0f f0 46 62 lddqu 0x62(%rsi),%xmm0 - 4353ff: f3 0f 7f 47 62 movdqu %xmm0,0x62(%rdi) - 435404: f2 0f f0 46 52 lddqu 0x52(%rsi),%xmm0 - 435409: f3 0f 7f 47 52 movdqu %xmm0,0x52(%rdi) - 43540e: f2 0f f0 46 42 lddqu 0x42(%rsi),%xmm0 - 435413: f3 0f 7f 47 42 movdqu %xmm0,0x42(%rdi) - 435418: f2 0f f0 46 32 lddqu 0x32(%rsi),%xmm0 - 43541d: f3 0f 7f 47 32 movdqu %xmm0,0x32(%rdi) - 435422: f2 0f f0 46 22 lddqu 0x22(%rsi),%xmm0 - 435427: f3 0f 7f 47 22 movdqu %xmm0,0x22(%rdi) - 43542c: f2 0f f0 46 12 lddqu 0x12(%rsi),%xmm0 - 435431: f3 0f 7f 47 12 movdqu %xmm0,0x12(%rdi) - 435436: f2 0f f0 46 02 lddqu 0x2(%rsi),%xmm0 - 43543b: f2 0f f0 0e lddqu (%rsi),%xmm1 - 43543f: f3 0f 7f 47 02 movdqu %xmm0,0x2(%rdi) - 435444: f3 0f 7f 0f movdqu %xmm1,(%rdi) - 435448: c3 retq - 435449: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 435450: 0f b7 16 movzwl (%rsi),%edx - 435453: 66 89 17 mov %dx,(%rdi) - 435456: c3 retq - 435457: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 43545e: 00 00 - 435460: f2 0f f0 46 71 lddqu 0x71(%rsi),%xmm0 - 435465: f3 0f 7f 47 71 movdqu %xmm0,0x71(%rdi) - 43546a: f2 0f f0 46 61 lddqu 0x61(%rsi),%xmm0 - 43546f: f3 0f 7f 47 61 movdqu %xmm0,0x61(%rdi) - 435474: f2 0f f0 46 51 lddqu 0x51(%rsi),%xmm0 - 435479: f3 0f 7f 47 51 movdqu %xmm0,0x51(%rdi) - 43547e: f2 0f f0 46 41 lddqu 0x41(%rsi),%xmm0 - 435483: f3 0f 7f 47 41 movdqu %xmm0,0x41(%rdi) - 435488: f2 0f f0 46 31 lddqu 0x31(%rsi),%xmm0 - 43548d: f3 0f 7f 47 31 movdqu %xmm0,0x31(%rdi) - 435492: f2 0f f0 46 21 lddqu 0x21(%rsi),%xmm0 - 435497: f3 0f 7f 47 21 movdqu %xmm0,0x21(%rdi) - 43549c: f2 0f f0 46 11 lddqu 0x11(%rsi),%xmm0 - 4354a1: f3 0f 7f 47 11 movdqu %xmm0,0x11(%rdi) - 4354a6: f2 0f f0 46 01 lddqu 0x1(%rsi),%xmm0 - 4354ab: f2 0f f0 0e lddqu (%rsi),%xmm1 - 4354af: f3 0f 7f 47 01 movdqu %xmm0,0x1(%rdi) - 4354b4: f3 0f 7f 0f movdqu %xmm1,(%rdi) - 4354b8: c3 retq - 4354b9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4354c0: 0f b6 16 movzbl (%rsi),%edx - 4354c3: 88 17 mov %dl,(%rdi) - 4354c5: c3 retq - 4354c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4354cd: 00 00 00 - -00000000004354d0 <__memmove_chk_avx512_no_vzeroupper>: - 4354d0: 48 39 d1 cmp %rdx,%rcx - 4354d3: 0f 82 d7 d5 00 00 jb 442ab0 <__chk_fail> - 4354d9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - -00000000004354e0 <__memmove_avx512_no_vzeroupper>: - 4354e0: 48 89 f8 mov %rdi,%rax - 4354e3: 48 8d 0c 16 lea (%rsi,%rdx,1),%rcx - 4354e7: 4c 8d 0c 17 lea (%rdi,%rdx,1),%r9 - 4354eb: 48 81 fa 00 02 00 00 cmp $0x200,%rdx - 4354f2: 0f 87 5d 01 00 00 ja 435655 <__memmove_avx512_no_vzeroupper+0x175> - 4354f8: 48 83 fa 10 cmp $0x10,%rdx - 4354fc: 0f 86 0f 01 00 00 jbe 435611 <__memmove_avx512_no_vzeroupper+0x131> - 435502: 48 81 fa 00 01 00 00 cmp $0x100,%rdx - 435509: 72 6f jb 43557a <__memmove_avx512_no_vzeroupper+0x9a> - 43550b: 62 f1 7c 48 10 06 vmovups (%rsi),%zmm0 - 435511: 62 f1 7c 48 10 4e 01 vmovups 0x40(%rsi),%zmm1 - 435518: 62 f1 7c 48 10 56 02 vmovups 0x80(%rsi),%zmm2 - 43551f: 62 f1 7c 48 10 5e 03 vmovups 0xc0(%rsi),%zmm3 - 435526: 62 f1 7c 48 10 61 fc vmovups -0x100(%rcx),%zmm4 - 43552d: 62 f1 7c 48 10 69 fd vmovups -0xc0(%rcx),%zmm5 - 435534: 62 f1 7c 48 10 71 fe vmovups -0x80(%rcx),%zmm6 - 43553b: 62 f1 7c 48 10 79 ff vmovups -0x40(%rcx),%zmm7 - 435542: 62 f1 7c 48 11 07 vmovups %zmm0,(%rdi) - 435548: 62 f1 7c 48 11 4f 01 vmovups %zmm1,0x40(%rdi) - 43554f: 62 f1 7c 48 11 57 02 vmovups %zmm2,0x80(%rdi) - 435556: 62 f1 7c 48 11 5f 03 vmovups %zmm3,0xc0(%rdi) - 43555d: 62 d1 7c 48 11 61 fc vmovups %zmm4,-0x100(%r9) - 435564: 62 d1 7c 48 11 69 fd vmovups %zmm5,-0xc0(%r9) - 43556b: 62 d1 7c 48 11 71 fe vmovups %zmm6,-0x80(%r9) - 435572: 62 d1 7c 48 11 79 ff vmovups %zmm7,-0x40(%r9) - 435579: c3 retq - 43557a: 80 fa 80 cmp $0x80,%dl - 43557d: 72 37 jb 4355b6 <__memmove_avx512_no_vzeroupper+0xd6> - 43557f: 62 f1 7c 48 10 06 vmovups (%rsi),%zmm0 - 435585: 62 f1 7c 48 10 4e 01 vmovups 0x40(%rsi),%zmm1 - 43558c: 62 f1 7c 48 10 51 fe vmovups -0x80(%rcx),%zmm2 - 435593: 62 f1 7c 48 10 59 ff vmovups -0x40(%rcx),%zmm3 - 43559a: 62 f1 7c 48 11 07 vmovups %zmm0,(%rdi) - 4355a0: 62 f1 7c 48 11 4f 01 vmovups %zmm1,0x40(%rdi) - 4355a7: 62 d1 7c 48 11 51 fe vmovups %zmm2,-0x80(%r9) - 4355ae: 62 d1 7c 48 11 59 ff vmovups %zmm3,-0x40(%r9) - 4355b5: c3 retq - 4355b6: 80 fa 40 cmp $0x40,%dl - 4355b9: 72 29 jb 4355e4 <__memmove_avx512_no_vzeroupper+0x104> - 4355bb: c5 fe 6f 06 vmovdqu (%rsi),%ymm0 - 4355bf: c5 fe 6f 4e 20 vmovdqu 0x20(%rsi),%ymm1 - 4355c4: c5 fe 6f 51 c0 vmovdqu -0x40(%rcx),%ymm2 - 4355c9: c5 fe 6f 59 e0 vmovdqu -0x20(%rcx),%ymm3 - 4355ce: c5 fe 7f 07 vmovdqu %ymm0,(%rdi) - 4355d2: c5 fe 7f 4f 20 vmovdqu %ymm1,0x20(%rdi) - 4355d7: c4 c1 7e 7f 51 c0 vmovdqu %ymm2,-0x40(%r9) - 4355dd: c4 c1 7e 7f 59 e0 vmovdqu %ymm3,-0x20(%r9) - 4355e3: c3 retq - 4355e4: 80 fa 20 cmp $0x20,%dl - 4355e7: 72 14 jb 4355fd <__memmove_avx512_no_vzeroupper+0x11d> - 4355e9: c5 fe 6f 06 vmovdqu (%rsi),%ymm0 - 4355ed: c5 fe 6f 49 e0 vmovdqu -0x20(%rcx),%ymm1 - 4355f2: c5 fe 7f 07 vmovdqu %ymm0,(%rdi) - 4355f6: c4 c1 7e 7f 49 e0 vmovdqu %ymm1,-0x20(%r9) - 4355fc: c3 retq - 4355fd: c5 fa 6f 06 vmovdqu (%rsi),%xmm0 - 435601: c5 fa 6f 49 f0 vmovdqu -0x10(%rcx),%xmm1 - 435606: c5 fa 7f 07 vmovdqu %xmm0,(%rdi) - 43560a: c4 c1 7a 7f 49 f0 vmovdqu %xmm1,-0x10(%r9) - 435610: c3 retq - 435611: 80 fa 08 cmp $0x8,%dl - 435614: 72 0f jb 435625 <__memmove_avx512_no_vzeroupper+0x145> - 435616: 48 8b 36 mov (%rsi),%rsi - 435619: 48 8b 49 f8 mov -0x8(%rcx),%rcx - 43561d: 48 89 37 mov %rsi,(%rdi) - 435620: 49 89 49 f8 mov %rcx,-0x8(%r9) - 435624: c3 retq - 435625: 80 fa 04 cmp $0x4,%dl - 435628: 72 0c jb 435636 <__memmove_avx512_no_vzeroupper+0x156> - 43562a: 8b 36 mov (%rsi),%esi - 43562c: 8b 49 fc mov -0x4(%rcx),%ecx - 43562f: 89 37 mov %esi,(%rdi) - 435631: 41 89 49 fc mov %ecx,-0x4(%r9) - 435635: c3 retq - 435636: 80 fa 02 cmp $0x2,%dl - 435639: 72 10 jb 43564b <__memmove_avx512_no_vzeroupper+0x16b> - 43563b: 66 8b 36 mov (%rsi),%si - 43563e: 66 8b 49 fe mov -0x2(%rcx),%cx - 435642: 66 89 37 mov %si,(%rdi) - 435645: 66 41 89 49 fe mov %cx,-0x2(%r9) - 43564a: c3 retq - 43564b: 80 fa 01 cmp $0x1,%dl - 43564e: 72 04 jb 435654 <__memmove_avx512_no_vzeroupper+0x174> - 435650: 8a 0e mov (%rsi),%cl - 435652: 88 0f mov %cl,(%rdi) - 435654: c3 retq - 435655: 4c 8b 05 54 5a 29 00 mov 0x295a54(%rip),%r8 # 6cb0b0 <__x86_shared_cache_size_half> - 43565c: 4c 39 c2 cmp %r8,%rdx - 43565f: 0f 83 18 04 00 00 jae 435a7d <__memmove_avx512_no_vzeroupper+0x59d> - 435665: 48 81 fa 00 04 00 00 cmp $0x400,%rdx - 43566c: 0f 87 42 01 00 00 ja 4357b4 <__memmove_avx512_no_vzeroupper+0x2d4> - 435672: 0f 18 16 prefetcht1 (%rsi) - 435675: 0f 18 56 40 prefetcht1 0x40(%rsi) - 435679: 0f 18 96 80 00 00 00 prefetcht1 0x80(%rsi) - 435680: 0f 18 96 c0 00 00 00 prefetcht1 0xc0(%rsi) - 435687: 0f 18 96 00 01 00 00 prefetcht1 0x100(%rsi) - 43568e: 0f 18 96 40 01 00 00 prefetcht1 0x140(%rsi) - 435695: 0f 18 96 80 01 00 00 prefetcht1 0x180(%rsi) - 43569c: 0f 18 96 c0 01 00 00 prefetcht1 0x1c0(%rsi) - 4356a3: 0f 18 91 00 fe ff ff prefetcht1 -0x200(%rcx) - 4356aa: 0f 18 91 40 fe ff ff prefetcht1 -0x1c0(%rcx) - 4356b1: 0f 18 91 80 fe ff ff prefetcht1 -0x180(%rcx) - 4356b8: 0f 18 91 c0 fe ff ff prefetcht1 -0x140(%rcx) - 4356bf: 0f 18 91 00 ff ff ff prefetcht1 -0x100(%rcx) - 4356c6: 0f 18 91 40 ff ff ff prefetcht1 -0xc0(%rcx) - 4356cd: 0f 18 51 80 prefetcht1 -0x80(%rcx) - 4356d1: 0f 18 51 c0 prefetcht1 -0x40(%rcx) - 4356d5: 62 f1 7c 48 10 06 vmovups (%rsi),%zmm0 - 4356db: 62 f1 7c 48 10 4e 01 vmovups 0x40(%rsi),%zmm1 - 4356e2: 62 f1 7c 48 10 56 02 vmovups 0x80(%rsi),%zmm2 - 4356e9: 62 f1 7c 48 10 5e 03 vmovups 0xc0(%rsi),%zmm3 - 4356f0: 62 f1 7c 48 10 66 04 vmovups 0x100(%rsi),%zmm4 - 4356f7: 62 f1 7c 48 10 6e 05 vmovups 0x140(%rsi),%zmm5 - 4356fe: 62 f1 7c 48 10 76 06 vmovups 0x180(%rsi),%zmm6 - 435705: 62 f1 7c 48 10 7e 07 vmovups 0x1c0(%rsi),%zmm7 - 43570c: 62 71 7c 48 10 41 f8 vmovups -0x200(%rcx),%zmm8 - 435713: 62 71 7c 48 10 49 f9 vmovups -0x1c0(%rcx),%zmm9 - 43571a: 62 71 7c 48 10 51 fa vmovups -0x180(%rcx),%zmm10 - 435721: 62 71 7c 48 10 59 fb vmovups -0x140(%rcx),%zmm11 - 435728: 62 71 7c 48 10 61 fc vmovups -0x100(%rcx),%zmm12 - 43572f: 62 71 7c 48 10 69 fd vmovups -0xc0(%rcx),%zmm13 - 435736: 62 71 7c 48 10 71 fe vmovups -0x80(%rcx),%zmm14 - 43573d: 62 71 7c 48 10 79 ff vmovups -0x40(%rcx),%zmm15 - 435744: 62 f1 7c 48 11 07 vmovups %zmm0,(%rdi) - 43574a: 62 f1 7c 48 11 4f 01 vmovups %zmm1,0x40(%rdi) - 435751: 62 f1 7c 48 11 57 02 vmovups %zmm2,0x80(%rdi) - 435758: 62 f1 7c 48 11 5f 03 vmovups %zmm3,0xc0(%rdi) - 43575f: 62 f1 7c 48 11 67 04 vmovups %zmm4,0x100(%rdi) - 435766: 62 f1 7c 48 11 6f 05 vmovups %zmm5,0x140(%rdi) - 43576d: 62 f1 7c 48 11 77 06 vmovups %zmm6,0x180(%rdi) - 435774: 62 f1 7c 48 11 7f 07 vmovups %zmm7,0x1c0(%rdi) - 43577b: 62 51 7c 48 11 41 f8 vmovups %zmm8,-0x200(%r9) - 435782: 62 51 7c 48 11 49 f9 vmovups %zmm9,-0x1c0(%r9) - 435789: 62 51 7c 48 11 51 fa vmovups %zmm10,-0x180(%r9) - 435790: 62 51 7c 48 11 59 fb vmovups %zmm11,-0x140(%r9) - 435797: 62 51 7c 48 11 61 fc vmovups %zmm12,-0x100(%r9) - 43579e: 62 51 7c 48 11 69 fd vmovups %zmm13,-0xc0(%r9) - 4357a5: 62 51 7c 48 11 71 fe vmovups %zmm14,-0x80(%r9) - 4357ac: 62 51 7c 48 11 79 ff vmovups %zmm15,-0x40(%r9) - 4357b3: c3 retq - 4357b4: 48 39 f7 cmp %rsi,%rdi - 4357b7: 0f 87 5e 01 00 00 ja 43591b <__memmove_avx512_no_vzeroupper+0x43b> - 4357bd: 49 81 e9 00 02 00 00 sub $0x200,%r9 - 4357c4: 62 71 7c 48 10 41 f8 vmovups -0x200(%rcx),%zmm8 - 4357cb: 62 71 7c 48 10 49 f9 vmovups -0x1c0(%rcx),%zmm9 - 4357d2: 62 71 7c 48 10 51 fa vmovups -0x180(%rcx),%zmm10 - 4357d9: 62 71 7c 48 10 59 fb vmovups -0x140(%rcx),%zmm11 - 4357e0: 62 71 7c 48 10 61 fc vmovups -0x100(%rcx),%zmm12 - 4357e7: 62 71 7c 48 10 69 fd vmovups -0xc0(%rcx),%zmm13 - 4357ee: 62 71 7c 48 10 71 fe vmovups -0x80(%rcx),%zmm14 - 4357f5: 62 71 7c 48 10 79 ff vmovups -0x40(%rcx),%zmm15 - 4357fc: 0f 18 16 prefetcht1 (%rsi) - 4357ff: 0f 18 56 40 prefetcht1 0x40(%rsi) - 435803: 0f 18 96 80 00 00 00 prefetcht1 0x80(%rsi) - 43580a: 0f 18 96 c0 00 00 00 prefetcht1 0xc0(%rsi) - 435811: 0f 18 96 00 01 00 00 prefetcht1 0x100(%rsi) - 435818: 0f 18 96 40 01 00 00 prefetcht1 0x140(%rsi) - 43581f: 0f 18 96 80 01 00 00 prefetcht1 0x180(%rsi) - 435826: 0f 18 96 c0 01 00 00 prefetcht1 0x1c0(%rsi) - 43582d: 62 f1 7c 48 10 06 vmovups (%rsi),%zmm0 - 435833: 62 f1 7c 48 10 4e 01 vmovups 0x40(%rsi),%zmm1 - 43583a: 62 f1 7c 48 10 56 02 vmovups 0x80(%rsi),%zmm2 - 435841: 62 f1 7c 48 10 5e 03 vmovups 0xc0(%rsi),%zmm3 - 435848: 62 f1 7c 48 10 66 04 vmovups 0x100(%rsi),%zmm4 - 43584f: 62 f1 7c 48 10 6e 05 vmovups 0x140(%rsi),%zmm5 - 435856: 62 f1 7c 48 10 76 06 vmovups 0x180(%rsi),%zmm6 - 43585d: 62 f1 7c 48 10 7e 07 vmovups 0x1c0(%rsi),%zmm7 - 435864: 48 81 c6 00 02 00 00 add $0x200,%rsi - 43586b: 0f 18 16 prefetcht1 (%rsi) - 43586e: 0f 18 56 40 prefetcht1 0x40(%rsi) - 435872: 0f 18 96 80 00 00 00 prefetcht1 0x80(%rsi) - 435879: 0f 18 96 c0 00 00 00 prefetcht1 0xc0(%rsi) - 435880: 0f 18 96 00 01 00 00 prefetcht1 0x100(%rsi) - 435887: 0f 18 96 40 01 00 00 prefetcht1 0x140(%rsi) - 43588e: 0f 18 96 80 01 00 00 prefetcht1 0x180(%rsi) - 435895: 0f 18 96 c0 01 00 00 prefetcht1 0x1c0(%rsi) - 43589c: 62 f1 7c 48 11 07 vmovups %zmm0,(%rdi) - 4358a2: 62 f1 7c 48 11 4f 01 vmovups %zmm1,0x40(%rdi) - 4358a9: 62 f1 7c 48 11 57 02 vmovups %zmm2,0x80(%rdi) - 4358b0: 62 f1 7c 48 11 5f 03 vmovups %zmm3,0xc0(%rdi) - 4358b7: 62 f1 7c 48 11 67 04 vmovups %zmm4,0x100(%rdi) - 4358be: 62 f1 7c 48 11 6f 05 vmovups %zmm5,0x140(%rdi) - 4358c5: 62 f1 7c 48 11 77 06 vmovups %zmm6,0x180(%rdi) - 4358cc: 62 f1 7c 48 11 7f 07 vmovups %zmm7,0x1c0(%rdi) - 4358d3: 48 81 c7 00 02 00 00 add $0x200,%rdi - 4358da: 4c 39 cf cmp %r9,%rdi - 4358dd: 0f 82 4a ff ff ff jb 43582d <__memmove_avx512_no_vzeroupper+0x34d> - 4358e3: 62 51 7c 48 11 01 vmovups %zmm8,(%r9) - 4358e9: 62 51 7c 48 11 49 01 vmovups %zmm9,0x40(%r9) - 4358f0: 62 51 7c 48 11 51 02 vmovups %zmm10,0x80(%r9) - 4358f7: 62 51 7c 48 11 59 03 vmovups %zmm11,0xc0(%r9) - 4358fe: 62 51 7c 48 11 61 04 vmovups %zmm12,0x100(%r9) - 435905: 62 51 7c 48 11 69 05 vmovups %zmm13,0x140(%r9) - 43590c: 62 51 7c 48 11 71 06 vmovups %zmm14,0x180(%r9) - 435913: 62 51 7c 48 11 79 07 vmovups %zmm15,0x1c0(%r9) - 43591a: c3 retq - 43591b: 48 81 c7 00 02 00 00 add $0x200,%rdi - 435922: 62 71 7c 48 10 46 07 vmovups 0x1c0(%rsi),%zmm8 - 435929: 62 71 7c 48 10 4e 06 vmovups 0x180(%rsi),%zmm9 - 435930: 62 71 7c 48 10 56 05 vmovups 0x140(%rsi),%zmm10 - 435937: 62 71 7c 48 10 5e 04 vmovups 0x100(%rsi),%zmm11 - 43593e: 62 71 7c 48 10 66 03 vmovups 0xc0(%rsi),%zmm12 - 435945: 62 71 7c 48 10 6e 02 vmovups 0x80(%rsi),%zmm13 - 43594c: 62 71 7c 48 10 76 01 vmovups 0x40(%rsi),%zmm14 - 435953: 62 71 7c 48 10 3e vmovups (%rsi),%zmm15 - 435959: 0f 18 51 c0 prefetcht1 -0x40(%rcx) - 43595d: 0f 18 51 80 prefetcht1 -0x80(%rcx) - 435961: 0f 18 91 40 ff ff ff prefetcht1 -0xc0(%rcx) - 435968: 0f 18 91 00 ff ff ff prefetcht1 -0x100(%rcx) - 43596f: 0f 18 91 c0 fe ff ff prefetcht1 -0x140(%rcx) - 435976: 0f 18 91 80 fe ff ff prefetcht1 -0x180(%rcx) - 43597d: 0f 18 91 40 fe ff ff prefetcht1 -0x1c0(%rcx) - 435984: 0f 18 91 00 fe ff ff prefetcht1 -0x200(%rcx) - 43598b: 62 f1 7c 48 10 41 ff vmovups -0x40(%rcx),%zmm0 - 435992: 62 f1 7c 48 10 49 fe vmovups -0x80(%rcx),%zmm1 - 435999: 62 f1 7c 48 10 51 fd vmovups -0xc0(%rcx),%zmm2 - 4359a0: 62 f1 7c 48 10 59 fc vmovups -0x100(%rcx),%zmm3 - 4359a7: 62 f1 7c 48 10 61 fb vmovups -0x140(%rcx),%zmm4 - 4359ae: 62 f1 7c 48 10 69 fa vmovups -0x180(%rcx),%zmm5 - 4359b5: 62 f1 7c 48 10 71 f9 vmovups -0x1c0(%rcx),%zmm6 - 4359bc: 62 f1 7c 48 10 79 f8 vmovups -0x200(%rcx),%zmm7 - 4359c3: 48 81 e9 00 02 00 00 sub $0x200,%rcx - 4359ca: 0f 18 51 c0 prefetcht1 -0x40(%rcx) - 4359ce: 0f 18 51 80 prefetcht1 -0x80(%rcx) - 4359d2: 0f 18 91 40 ff ff ff prefetcht1 -0xc0(%rcx) - 4359d9: 0f 18 91 00 ff ff ff prefetcht1 -0x100(%rcx) - 4359e0: 0f 18 91 c0 fe ff ff prefetcht1 -0x140(%rcx) - 4359e7: 0f 18 91 80 fe ff ff prefetcht1 -0x180(%rcx) - 4359ee: 0f 18 91 40 fe ff ff prefetcht1 -0x1c0(%rcx) - 4359f5: 0f 18 91 00 fe ff ff prefetcht1 -0x200(%rcx) - 4359fc: 62 d1 7c 48 11 41 ff vmovups %zmm0,-0x40(%r9) - 435a03: 62 d1 7c 48 11 49 fe vmovups %zmm1,-0x80(%r9) - 435a0a: 62 d1 7c 48 11 51 fd vmovups %zmm2,-0xc0(%r9) - 435a11: 62 d1 7c 48 11 59 fc vmovups %zmm3,-0x100(%r9) - 435a18: 62 d1 7c 48 11 61 fb vmovups %zmm4,-0x140(%r9) - 435a1f: 62 d1 7c 48 11 69 fa vmovups %zmm5,-0x180(%r9) - 435a26: 62 d1 7c 48 11 71 f9 vmovups %zmm6,-0x1c0(%r9) - 435a2d: 62 d1 7c 48 11 79 f8 vmovups %zmm7,-0x200(%r9) - 435a34: 49 81 e9 00 02 00 00 sub $0x200,%r9 - 435a3b: 49 39 f9 cmp %rdi,%r9 - 435a3e: 0f 87 47 ff ff ff ja 43598b <__memmove_avx512_no_vzeroupper+0x4ab> - 435a44: 62 71 7c 48 11 47 ff vmovups %zmm8,-0x40(%rdi) - 435a4b: 62 71 7c 48 11 4f fe vmovups %zmm9,-0x80(%rdi) - 435a52: 62 71 7c 48 11 57 fd vmovups %zmm10,-0xc0(%rdi) - 435a59: 62 71 7c 48 11 5f fc vmovups %zmm11,-0x100(%rdi) - 435a60: 62 71 7c 48 11 67 fb vmovups %zmm12,-0x140(%rdi) - 435a67: 62 71 7c 48 11 6f fa vmovups %zmm13,-0x180(%rdi) - 435a6e: 62 71 7c 48 11 77 f9 vmovups %zmm14,-0x1c0(%rdi) - 435a75: 62 71 7c 48 11 7f f8 vmovups %zmm15,-0x200(%rdi) - 435a7c: c3 retq - 435a7d: 48 39 f7 cmp %rsi,%rdi - 435a80: 0f 87 c9 00 00 00 ja 435b4f <__memmove_avx512_no_vzeroupper+0x66f> - 435a86: 62 f1 7c 48 10 26 vmovups (%rsi),%zmm4 - 435a8c: 62 f1 7c 48 10 6e 01 vmovups 0x40(%rsi),%zmm5 - 435a93: 49 89 f8 mov %rdi,%r8 - 435a96: 48 83 e7 80 and $0xffffffffffffff80,%rdi - 435a9a: 48 81 c7 80 00 00 00 add $0x80,%rdi - 435aa1: 49 29 f8 sub %rdi,%r8 - 435aa4: 4c 29 c6 sub %r8,%rsi - 435aa7: 4c 01 c2 add %r8,%rdx - 435aaa: 0f 18 96 00 02 00 00 prefetcht1 0x200(%rsi) - 435ab1: 0f 18 96 40 02 00 00 prefetcht1 0x240(%rsi) - 435ab8: 0f 18 96 80 02 00 00 prefetcht1 0x280(%rsi) - 435abf: 0f 18 96 c0 02 00 00 prefetcht1 0x2c0(%rsi) - 435ac6: 0f 18 96 00 03 00 00 prefetcht1 0x300(%rsi) - 435acd: 0f 18 96 40 03 00 00 prefetcht1 0x340(%rsi) - 435ad4: 0f 18 96 80 03 00 00 prefetcht1 0x380(%rsi) - 435adb: 0f 18 96 c0 03 00 00 prefetcht1 0x3c0(%rsi) - 435ae2: 62 f1 fe 48 6f 06 vmovdqu64 (%rsi),%zmm0 - 435ae8: 62 f1 fe 48 6f 4e 01 vmovdqu64 0x40(%rsi),%zmm1 - 435aef: 62 f1 fe 48 6f 56 02 vmovdqu64 0x80(%rsi),%zmm2 - 435af6: 62 f1 fe 48 6f 5e 03 vmovdqu64 0xc0(%rsi),%zmm3 - 435afd: 62 f1 7d 48 e7 07 vmovntdq %zmm0,(%rdi) - 435b03: 62 f1 7d 48 e7 4f 01 vmovntdq %zmm1,0x40(%rdi) - 435b0a: 62 f1 7d 48 e7 57 02 vmovntdq %zmm2,0x80(%rdi) - 435b11: 62 f1 7d 48 e7 5f 03 vmovntdq %zmm3,0xc0(%rdi) - 435b18: 48 81 ea 00 01 00 00 sub $0x100,%rdx - 435b1f: 48 81 c6 00 01 00 00 add $0x100,%rsi - 435b26: 48 81 c7 00 01 00 00 add $0x100,%rdi - 435b2d: 48 81 fa 00 01 00 00 cmp $0x100,%rdx - 435b34: 0f 87 70 ff ff ff ja 435aaa <__memmove_avx512_no_vzeroupper+0x5ca> - 435b3a: 0f ae f8 sfence - 435b3d: 62 f1 7c 48 11 20 vmovups %zmm4,(%rax) - 435b43: 62 f1 7c 48 11 68 01 vmovups %zmm5,0x40(%rax) - 435b4a: e9 a9 f9 ff ff jmpq 4354f8 <__memmove_avx512_no_vzeroupper+0x18> - 435b4f: 62 f1 7c 48 10 61 fe vmovups -0x80(%rcx),%zmm4 - 435b56: 62 f1 7c 48 10 69 ff vmovups -0x40(%rcx),%zmm5 - 435b5d: 4d 89 c8 mov %r9,%r8 - 435b60: 49 83 e1 80 and $0xffffffffffffff80,%r9 - 435b64: 4d 29 c8 sub %r9,%r8 - 435b67: 4c 29 c1 sub %r8,%rcx - 435b6a: 4c 29 c2 sub %r8,%rdx - 435b6d: 4d 01 c8 add %r9,%r8 - 435b70: 0f 18 91 00 fc ff ff prefetcht1 -0x400(%rcx) - 435b77: 0f 18 91 40 fc ff ff prefetcht1 -0x3c0(%rcx) - 435b7e: 0f 18 91 80 fc ff ff prefetcht1 -0x380(%rcx) - 435b85: 0f 18 91 c0 fc ff ff prefetcht1 -0x340(%rcx) - 435b8c: 0f 18 91 00 fd ff ff prefetcht1 -0x300(%rcx) - 435b93: 0f 18 91 40 fd ff ff prefetcht1 -0x2c0(%rcx) - 435b9a: 0f 18 91 80 fd ff ff prefetcht1 -0x280(%rcx) - 435ba1: 0f 18 91 c0 fd ff ff prefetcht1 -0x240(%rcx) - 435ba8: 62 f1 fe 48 6f 41 fc vmovdqu64 -0x100(%rcx),%zmm0 - 435baf: 62 f1 fe 48 6f 49 fd vmovdqu64 -0xc0(%rcx),%zmm1 - 435bb6: 62 f1 fe 48 6f 51 fe vmovdqu64 -0x80(%rcx),%zmm2 - 435bbd: 62 f1 fe 48 6f 59 ff vmovdqu64 -0x40(%rcx),%zmm3 - 435bc4: 62 d1 7d 48 e7 41 fc vmovntdq %zmm0,-0x100(%r9) - 435bcb: 62 d1 7d 48 e7 49 fd vmovntdq %zmm1,-0xc0(%r9) - 435bd2: 62 d1 7d 48 e7 51 fe vmovntdq %zmm2,-0x80(%r9) - 435bd9: 62 d1 7d 48 e7 59 ff vmovntdq %zmm3,-0x40(%r9) - 435be0: 48 81 ea 00 01 00 00 sub $0x100,%rdx - 435be7: 48 81 e9 00 01 00 00 sub $0x100,%rcx - 435bee: 49 81 e9 00 01 00 00 sub $0x100,%r9 - 435bf5: 48 81 fa 00 01 00 00 cmp $0x100,%rdx - 435bfc: 0f 87 6e ff ff ff ja 435b70 <__memmove_avx512_no_vzeroupper+0x690> - 435c02: 0f ae f8 sfence - 435c05: 62 d1 7c 48 11 60 fe vmovups %zmm4,-0x80(%r8) - 435c0c: 62 d1 7c 48 11 68 ff vmovups %zmm5,-0x40(%r8) - 435c13: e9 e0 f8 ff ff jmpq 4354f8 <__memmove_avx512_no_vzeroupper+0x18> - 435c18: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 435c1f: 00 - -0000000000435c20 <__strcasecmp_ssse3>: - 435c20: 48 c7 c0 b8 ff ff ff mov $0xffffffffffffffb8,%rax - 435c27: 64 48 8b 10 mov %fs:(%rax),%rdx - 435c2b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - -0000000000435c30 <__strcasecmp_l_ssse3>: - 435c30: 48 8b 02 mov (%rdx),%rax - 435c33: f7 80 78 02 00 00 01 testl $0x1,0x278(%rax) - 435c3a: 00 00 00 - 435c3d: 0f 85 bd 86 00 00 jne 43e300 <__strcasecmp_l_nonascii> - 435c43: 89 f1 mov %esi,%ecx - 435c45: 89 f8 mov %edi,%eax - 435c47: 48 83 e1 3f and $0x3f,%rcx - 435c4b: 48 83 e0 3f and $0x3f,%rax - 435c4f: 66 0f 6f 2d 59 d4 06 movdqa 0x6d459(%rip),%xmm5 # 4a30b0 <__func__.10972+0xf0> - 435c56: 00 - 435c57: 66 0f 6f 35 61 d4 06 movdqa 0x6d461(%rip),%xmm6 # 4a30c0 <__func__.10972+0x100> - 435c5e: 00 - 435c5f: 66 0f 6f 3d 69 d4 06 movdqa 0x6d469(%rip),%xmm7 # 4a30d0 - 435c66: 00 - 435c67: 83 f9 30 cmp $0x30,%ecx - 435c6a: 0f 87 90 00 00 00 ja 435d00 <__strcasecmp_l_ssse3+0xd0> - 435c70: 83 f8 30 cmp $0x30,%eax - 435c73: 0f 87 87 00 00 00 ja 435d00 <__strcasecmp_l_ssse3+0xd0> - 435c79: 66 0f 12 0f movlpd (%rdi),%xmm1 - 435c7d: 66 0f 12 16 movlpd (%rsi),%xmm2 - 435c81: 66 0f 16 4f 08 movhpd 0x8(%rdi),%xmm1 - 435c86: 66 0f 16 56 08 movhpd 0x8(%rsi),%xmm2 - 435c8b: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 435c90: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 435c95: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 435c9a: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 435c9f: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 435ca4: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 435ca9: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 435cae: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 435cb3: 66 45 0f db c1 pand %xmm9,%xmm8 - 435cb8: 66 45 0f db d3 pand %xmm11,%xmm10 - 435cbd: 66 44 0f db c7 pand %xmm7,%xmm8 - 435cc2: 66 44 0f db d7 pand %xmm7,%xmm10 - 435cc7: 66 41 0f eb c8 por %xmm8,%xmm1 - 435ccc: 66 41 0f eb d2 por %xmm10,%xmm2 - 435cd1: 66 0f ef c0 pxor %xmm0,%xmm0 - 435cd5: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 435cd9: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 435cdd: 66 0f f8 c8 psubb %xmm0,%xmm1 - 435ce1: 66 0f d7 d1 pmovmskb %xmm1,%edx - 435ce5: 81 ea ff ff 00 00 sub $0xffff,%edx - 435ceb: 0f 85 3f 20 00 00 jne 437d30 <__strcasecmp_l_ssse3+0x2100> - 435cf1: 48 83 c6 10 add $0x10,%rsi - 435cf5: 48 83 c7 10 add $0x10,%rdi - 435cf9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 435d00: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi - 435d04: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi - 435d08: ba ff ff 00 00 mov $0xffff,%edx - 435d0d: 45 31 c0 xor %r8d,%r8d - 435d10: 83 e1 0f and $0xf,%ecx - 435d13: 83 e0 0f and $0xf,%eax - 435d16: 39 c1 cmp %eax,%ecx - 435d18: 74 26 je 435d40 <__strcasecmp_l_ssse3+0x110> - 435d1a: 77 07 ja 435d23 <__strcasecmp_l_ssse3+0xf3> - 435d1c: 41 89 d0 mov %edx,%r8d - 435d1f: 91 xchg %eax,%ecx - 435d20: 48 87 f7 xchg %rsi,%rdi - 435d23: 4c 8d 48 0f lea 0xf(%rax),%r9 - 435d27: 49 29 c9 sub %rcx,%r9 - 435d2a: 4c 8d 15 3f dd 06 00 lea 0x6dd3f(%rip),%r10 # 4a3a70 - 435d31: 4f 63 0c 8a movslq (%r10,%r9,4),%r9 - 435d35: 4f 8d 14 0a lea (%r10,%r9,1),%r10 - 435d39: 41 ff e2 jmpq *%r10 - 435d3c: 0f 1f 40 00 nopl 0x0(%rax) - 435d40: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 435d44: 66 0f ef c0 pxor %xmm0,%xmm0 - 435d48: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 435d4c: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 435d50: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 435d55: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 435d5a: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 435d5f: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 435d64: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 435d69: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 435d6e: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 435d73: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 435d78: 66 45 0f db c1 pand %xmm9,%xmm8 - 435d7d: 66 45 0f db d3 pand %xmm11,%xmm10 - 435d82: 66 44 0f db c7 pand %xmm7,%xmm8 - 435d87: 66 44 0f db d7 pand %xmm7,%xmm10 - 435d8c: 66 41 0f eb c8 por %xmm8,%xmm1 - 435d91: 66 41 0f eb d2 por %xmm10,%xmm2 - 435d96: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 435d9a: 66 0f f8 c8 psubb %xmm0,%xmm1 - 435d9e: 66 44 0f d7 c9 pmovmskb %xmm1,%r9d - 435da3: d3 ea shr %cl,%edx - 435da5: 41 d3 e9 shr %cl,%r9d - 435da8: 44 29 ca sub %r9d,%edx - 435dab: 0f 85 64 1f 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> - 435db1: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 435db8: 49 c7 c1 10 00 00 00 mov $0x10,%r9 - 435dbf: 66 0f ef c0 pxor %xmm0,%xmm0 - 435dc3: 0f 1f 00 nopl (%rax) - 435dc6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 435dcd: 00 00 00 - 435dd0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 435dd5: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 435dda: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 435ddf: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 435de4: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 435de9: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 435dee: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 435df3: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 435df8: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 435dfd: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 435e02: 66 45 0f db c1 pand %xmm9,%xmm8 - 435e07: 66 45 0f db d3 pand %xmm11,%xmm10 - 435e0c: 66 44 0f db c7 pand %xmm7,%xmm8 - 435e11: 66 44 0f db d7 pand %xmm7,%xmm10 - 435e16: 66 41 0f eb c8 por %xmm8,%xmm1 - 435e1b: 66 41 0f eb d2 por %xmm10,%xmm2 - 435e20: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 435e24: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 435e28: 66 0f f8 c8 psubb %xmm0,%xmm1 - 435e2c: 66 0f d7 d1 pmovmskb %xmm1,%edx - 435e30: 81 ea ff ff 00 00 sub $0xffff,%edx - 435e36: 0f 85 d4 1e 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 435e3c: 48 83 c1 10 add $0x10,%rcx - 435e40: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 435e45: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 435e4a: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 435e4f: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 435e54: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 435e59: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 435e5e: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 435e63: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 435e68: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 435e6d: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 435e72: 66 45 0f db c1 pand %xmm9,%xmm8 - 435e77: 66 45 0f db d3 pand %xmm11,%xmm10 - 435e7c: 66 44 0f db c7 pand %xmm7,%xmm8 - 435e81: 66 44 0f db d7 pand %xmm7,%xmm10 - 435e86: 66 41 0f eb c8 por %xmm8,%xmm1 - 435e8b: 66 41 0f eb d2 por %xmm10,%xmm2 - 435e90: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 435e94: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 435e98: 66 0f f8 c8 psubb %xmm0,%xmm1 - 435e9c: 66 0f d7 d1 pmovmskb %xmm1,%edx - 435ea0: 81 ea ff ff 00 00 sub $0xffff,%edx - 435ea6: 0f 85 64 1e 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 435eac: 48 83 c1 10 add $0x10,%rcx - 435eb0: e9 1b ff ff ff jmpq 435dd0 <__strcasecmp_l_ssse3+0x1a0> - 435eb5: 90 nop - 435eb6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 435ebd: 00 00 00 - 435ec0: 66 0f ef c0 pxor %xmm0,%xmm0 - 435ec4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 435ec8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 435ecc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 435ed0: 66 0f 73 fa 0f pslldq $0xf,%xmm2 - 435ed5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 435eda: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 435edf: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 435ee4: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 435ee9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 435eee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 435ef3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 435ef8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 435efd: 66 45 0f db c1 pand %xmm9,%xmm8 - 435f02: 66 45 0f db d3 pand %xmm11,%xmm10 - 435f07: 66 44 0f db c7 pand %xmm7,%xmm8 - 435f0c: 66 44 0f db d7 pand %xmm7,%xmm10 - 435f11: 66 41 0f eb c8 por %xmm8,%xmm1 - 435f16: 66 41 0f eb d2 por %xmm10,%xmm2 - 435f1b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 435f1f: 66 0f f8 d0 psubb %xmm0,%xmm2 - 435f23: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 435f28: d3 ea shr %cl,%edx - 435f2a: 41 d3 e9 shr %cl,%r9d - 435f2d: 44 29 ca sub %r9d,%edx - 435f30: 0f 85 df 1d 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> - 435f36: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 435f3a: 66 0f ef c0 pxor %xmm0,%xmm0 - 435f3e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 435f45: 41 b9 01 00 00 00 mov $0x1,%r9d - 435f4b: 4c 8d 57 01 lea 0x1(%rdi),%r10 - 435f4f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 435f56: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 435f5d: 0f 1f 00 nopl (%rax) - 435f60: 49 83 c2 10 add $0x10,%r10 - 435f64: 0f 8f 16 01 00 00 jg 436080 <__strcasecmp_l_ssse3+0x450> - 435f6a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 435f6f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 435f74: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 435f78: 66 0f 3a 0f d3 01 palignr $0x1,%xmm3,%xmm2 - 435f7e: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 435f83: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 435f88: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 435f8d: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 435f92: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 435f97: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 435f9c: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 435fa1: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 435fa6: 66 45 0f db c1 pand %xmm9,%xmm8 - 435fab: 66 45 0f db d3 pand %xmm11,%xmm10 - 435fb0: 66 44 0f db c7 pand %xmm7,%xmm8 - 435fb5: 66 44 0f db d7 pand %xmm7,%xmm10 - 435fba: 66 41 0f eb c8 por %xmm8,%xmm1 - 435fbf: 66 41 0f eb d2 por %xmm10,%xmm2 - 435fc4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 435fc8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 435fcc: 66 0f f8 c8 psubb %xmm0,%xmm1 - 435fd0: 66 0f d7 d1 pmovmskb %xmm1,%edx - 435fd4: 81 ea ff ff 00 00 sub $0xffff,%edx - 435fda: 0f 85 30 1d 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 435fe0: 48 83 c1 10 add $0x10,%rcx - 435fe4: 66 0f 6f dc movdqa %xmm4,%xmm3 - 435fe8: 49 83 c2 10 add $0x10,%r10 - 435fec: 0f 8f 8e 00 00 00 jg 436080 <__strcasecmp_l_ssse3+0x450> - 435ff2: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 435ff7: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 435ffc: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 436000: 66 0f 3a 0f d3 01 palignr $0x1,%xmm3,%xmm2 - 436006: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 43600b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 436010: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 436015: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 43601a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 43601f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 436024: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 436029: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 43602e: 66 45 0f db c1 pand %xmm9,%xmm8 - 436033: 66 45 0f db d3 pand %xmm11,%xmm10 - 436038: 66 44 0f db c7 pand %xmm7,%xmm8 - 43603d: 66 44 0f db d7 pand %xmm7,%xmm10 - 436042: 66 41 0f eb c8 por %xmm8,%xmm1 - 436047: 66 41 0f eb d2 por %xmm10,%xmm2 - 43604c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 436050: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 436054: 66 0f f8 c8 psubb %xmm0,%xmm1 - 436058: 66 0f d7 d1 pmovmskb %xmm1,%edx - 43605c: 81 ea ff ff 00 00 sub $0xffff,%edx - 436062: 0f 85 a8 1c 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 436068: 48 83 c1 10 add $0x10,%rcx - 43606c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 436070: e9 eb fe ff ff jmpq 435f60 <__strcasecmp_l_ssse3+0x330> - 436075: 90 nop - 436076: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43607d: 00 00 00 - 436080: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 436084: 66 0f d7 d0 pmovmskb %xmm0,%edx - 436088: f7 c2 fe ff 00 00 test $0xfffe,%edx - 43608e: 75 10 jne 4360a0 <__strcasecmp_l_ssse3+0x470> - 436090: 66 0f ef c0 pxor %xmm0,%xmm0 - 436094: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 43609b: e9 ca fe ff ff jmpq 435f6a <__strcasecmp_l_ssse3+0x33a> - 4360a0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4360a5: 66 0f 73 d8 01 psrldq $0x1,%xmm0 - 4360aa: 66 0f 73 db 01 psrldq $0x1,%xmm3 - 4360af: e9 fc 1b 00 00 jmpq 437cb0 <__strcasecmp_l_ssse3+0x2080> - 4360b4: 66 90 xchg %ax,%ax - 4360b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4360bd: 00 00 00 - 4360c0: 66 0f ef c0 pxor %xmm0,%xmm0 - 4360c4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 4360c8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 4360cc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4360d0: 66 0f 73 fa 0e pslldq $0xe,%xmm2 - 4360d5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 4360da: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 4360df: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 4360e4: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 4360e9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 4360ee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 4360f3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 4360f8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 4360fd: 66 45 0f db c1 pand %xmm9,%xmm8 - 436102: 66 45 0f db d3 pand %xmm11,%xmm10 - 436107: 66 44 0f db c7 pand %xmm7,%xmm8 - 43610c: 66 44 0f db d7 pand %xmm7,%xmm10 - 436111: 66 41 0f eb c8 por %xmm8,%xmm1 - 436116: 66 41 0f eb d2 por %xmm10,%xmm2 - 43611b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 43611f: 66 0f f8 d0 psubb %xmm0,%xmm2 - 436123: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 436128: d3 ea shr %cl,%edx - 43612a: 41 d3 e9 shr %cl,%r9d - 43612d: 44 29 ca sub %r9d,%edx - 436130: 0f 85 df 1b 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> - 436136: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 43613a: 66 0f ef c0 pxor %xmm0,%xmm0 - 43613e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 436145: 41 b9 02 00 00 00 mov $0x2,%r9d - 43614b: 4c 8d 57 02 lea 0x2(%rdi),%r10 - 43614f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 436156: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 43615d: 0f 1f 00 nopl (%rax) - 436160: 49 83 c2 10 add $0x10,%r10 - 436164: 0f 8f 16 01 00 00 jg 436280 <__strcasecmp_l_ssse3+0x650> - 43616a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 43616f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 436174: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 436178: 66 0f 3a 0f d3 02 palignr $0x2,%xmm3,%xmm2 - 43617e: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 436183: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 436188: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 43618d: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 436192: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 436197: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 43619c: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 4361a1: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 4361a6: 66 45 0f db c1 pand %xmm9,%xmm8 - 4361ab: 66 45 0f db d3 pand %xmm11,%xmm10 - 4361b0: 66 44 0f db c7 pand %xmm7,%xmm8 - 4361b5: 66 44 0f db d7 pand %xmm7,%xmm10 - 4361ba: 66 41 0f eb c8 por %xmm8,%xmm1 - 4361bf: 66 41 0f eb d2 por %xmm10,%xmm2 - 4361c4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4361c8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 4361cc: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4361d0: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4361d4: 81 ea ff ff 00 00 sub $0xffff,%edx - 4361da: 0f 85 30 1b 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 4361e0: 48 83 c1 10 add $0x10,%rcx - 4361e4: 66 0f 6f dc movdqa %xmm4,%xmm3 - 4361e8: 49 83 c2 10 add $0x10,%r10 - 4361ec: 0f 8f 8e 00 00 00 jg 436280 <__strcasecmp_l_ssse3+0x650> - 4361f2: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4361f7: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4361fc: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 436200: 66 0f 3a 0f d3 02 palignr $0x2,%xmm3,%xmm2 - 436206: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 43620b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 436210: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 436215: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 43621a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 43621f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 436224: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 436229: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 43622e: 66 45 0f db c1 pand %xmm9,%xmm8 - 436233: 66 45 0f db d3 pand %xmm11,%xmm10 - 436238: 66 44 0f db c7 pand %xmm7,%xmm8 - 43623d: 66 44 0f db d7 pand %xmm7,%xmm10 - 436242: 66 41 0f eb c8 por %xmm8,%xmm1 - 436247: 66 41 0f eb d2 por %xmm10,%xmm2 - 43624c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 436250: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 436254: 66 0f f8 c8 psubb %xmm0,%xmm1 - 436258: 66 0f d7 d1 pmovmskb %xmm1,%edx - 43625c: 81 ea ff ff 00 00 sub $0xffff,%edx - 436262: 0f 85 a8 1a 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 436268: 48 83 c1 10 add $0x10,%rcx - 43626c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 436270: e9 eb fe ff ff jmpq 436160 <__strcasecmp_l_ssse3+0x530> - 436275: 90 nop - 436276: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43627d: 00 00 00 - 436280: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 436284: 66 0f d7 d0 pmovmskb %xmm0,%edx - 436288: f7 c2 fc ff 00 00 test $0xfffc,%edx - 43628e: 75 10 jne 4362a0 <__strcasecmp_l_ssse3+0x670> - 436290: 66 0f ef c0 pxor %xmm0,%xmm0 - 436294: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 43629b: e9 ca fe ff ff jmpq 43616a <__strcasecmp_l_ssse3+0x53a> - 4362a0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4362a5: 66 0f 73 d8 02 psrldq $0x2,%xmm0 - 4362aa: 66 0f 73 db 02 psrldq $0x2,%xmm3 - 4362af: e9 fc 19 00 00 jmpq 437cb0 <__strcasecmp_l_ssse3+0x2080> - 4362b4: 66 90 xchg %ax,%ax - 4362b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4362bd: 00 00 00 - 4362c0: 66 0f ef c0 pxor %xmm0,%xmm0 - 4362c4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 4362c8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 4362cc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4362d0: 66 0f 73 fa 0d pslldq $0xd,%xmm2 - 4362d5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 4362da: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 4362df: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 4362e4: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 4362e9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 4362ee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 4362f3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 4362f8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 4362fd: 66 45 0f db c1 pand %xmm9,%xmm8 - 436302: 66 45 0f db d3 pand %xmm11,%xmm10 - 436307: 66 44 0f db c7 pand %xmm7,%xmm8 - 43630c: 66 44 0f db d7 pand %xmm7,%xmm10 - 436311: 66 41 0f eb c8 por %xmm8,%xmm1 - 436316: 66 41 0f eb d2 por %xmm10,%xmm2 - 43631b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 43631f: 66 0f f8 d0 psubb %xmm0,%xmm2 - 436323: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 436328: d3 ea shr %cl,%edx - 43632a: 41 d3 e9 shr %cl,%r9d - 43632d: 44 29 ca sub %r9d,%edx - 436330: 0f 85 df 19 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> - 436336: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 43633a: 66 0f ef c0 pxor %xmm0,%xmm0 - 43633e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 436345: 41 b9 03 00 00 00 mov $0x3,%r9d - 43634b: 4c 8d 57 03 lea 0x3(%rdi),%r10 - 43634f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 436356: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 43635d: 0f 1f 00 nopl (%rax) - 436360: 49 83 c2 10 add $0x10,%r10 - 436364: 0f 8f 16 01 00 00 jg 436480 <__strcasecmp_l_ssse3+0x850> - 43636a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 43636f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 436374: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 436378: 66 0f 3a 0f d3 03 palignr $0x3,%xmm3,%xmm2 - 43637e: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 436383: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 436388: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 43638d: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 436392: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 436397: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 43639c: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 4363a1: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 4363a6: 66 45 0f db c1 pand %xmm9,%xmm8 - 4363ab: 66 45 0f db d3 pand %xmm11,%xmm10 - 4363b0: 66 44 0f db c7 pand %xmm7,%xmm8 - 4363b5: 66 44 0f db d7 pand %xmm7,%xmm10 - 4363ba: 66 41 0f eb c8 por %xmm8,%xmm1 - 4363bf: 66 41 0f eb d2 por %xmm10,%xmm2 - 4363c4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4363c8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 4363cc: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4363d0: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4363d4: 81 ea ff ff 00 00 sub $0xffff,%edx - 4363da: 0f 85 30 19 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 4363e0: 48 83 c1 10 add $0x10,%rcx - 4363e4: 66 0f 6f dc movdqa %xmm4,%xmm3 - 4363e8: 49 83 c2 10 add $0x10,%r10 - 4363ec: 0f 8f 8e 00 00 00 jg 436480 <__strcasecmp_l_ssse3+0x850> - 4363f2: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4363f7: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4363fc: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 436400: 66 0f 3a 0f d3 03 palignr $0x3,%xmm3,%xmm2 - 436406: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 43640b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 436410: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 436415: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 43641a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 43641f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 436424: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 436429: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 43642e: 66 45 0f db c1 pand %xmm9,%xmm8 - 436433: 66 45 0f db d3 pand %xmm11,%xmm10 - 436438: 66 44 0f db c7 pand %xmm7,%xmm8 - 43643d: 66 44 0f db d7 pand %xmm7,%xmm10 - 436442: 66 41 0f eb c8 por %xmm8,%xmm1 - 436447: 66 41 0f eb d2 por %xmm10,%xmm2 - 43644c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 436450: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 436454: 66 0f f8 c8 psubb %xmm0,%xmm1 - 436458: 66 0f d7 d1 pmovmskb %xmm1,%edx - 43645c: 81 ea ff ff 00 00 sub $0xffff,%edx - 436462: 0f 85 a8 18 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 436468: 48 83 c1 10 add $0x10,%rcx - 43646c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 436470: e9 eb fe ff ff jmpq 436360 <__strcasecmp_l_ssse3+0x730> - 436475: 90 nop - 436476: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43647d: 00 00 00 - 436480: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 436484: 66 0f d7 d0 pmovmskb %xmm0,%edx - 436488: f7 c2 f8 ff 00 00 test $0xfff8,%edx - 43648e: 75 10 jne 4364a0 <__strcasecmp_l_ssse3+0x870> - 436490: 66 0f ef c0 pxor %xmm0,%xmm0 - 436494: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 43649b: e9 ca fe ff ff jmpq 43636a <__strcasecmp_l_ssse3+0x73a> - 4364a0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4364a5: 66 0f 73 d8 03 psrldq $0x3,%xmm0 - 4364aa: 66 0f 73 db 03 psrldq $0x3,%xmm3 - 4364af: e9 fc 17 00 00 jmpq 437cb0 <__strcasecmp_l_ssse3+0x2080> - 4364b4: 66 90 xchg %ax,%ax - 4364b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4364bd: 00 00 00 - 4364c0: 66 0f ef c0 pxor %xmm0,%xmm0 - 4364c4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 4364c8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 4364cc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4364d0: 66 0f 73 fa 0c pslldq $0xc,%xmm2 - 4364d5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 4364da: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 4364df: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 4364e4: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 4364e9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 4364ee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 4364f3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 4364f8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 4364fd: 66 45 0f db c1 pand %xmm9,%xmm8 - 436502: 66 45 0f db d3 pand %xmm11,%xmm10 - 436507: 66 44 0f db c7 pand %xmm7,%xmm8 - 43650c: 66 44 0f db d7 pand %xmm7,%xmm10 - 436511: 66 41 0f eb c8 por %xmm8,%xmm1 - 436516: 66 41 0f eb d2 por %xmm10,%xmm2 - 43651b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 43651f: 66 0f f8 d0 psubb %xmm0,%xmm2 - 436523: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 436528: d3 ea shr %cl,%edx - 43652a: 41 d3 e9 shr %cl,%r9d - 43652d: 44 29 ca sub %r9d,%edx - 436530: 0f 85 df 17 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> - 436536: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 43653a: 66 0f ef c0 pxor %xmm0,%xmm0 - 43653e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 436545: 41 b9 04 00 00 00 mov $0x4,%r9d - 43654b: 4c 8d 57 04 lea 0x4(%rdi),%r10 - 43654f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 436556: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 43655d: 0f 1f 00 nopl (%rax) - 436560: 49 83 c2 10 add $0x10,%r10 - 436564: 0f 8f 16 01 00 00 jg 436680 <__strcasecmp_l_ssse3+0xa50> - 43656a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 43656f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 436574: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 436578: 66 0f 3a 0f d3 04 palignr $0x4,%xmm3,%xmm2 - 43657e: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 436583: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 436588: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 43658d: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 436592: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 436597: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 43659c: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 4365a1: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 4365a6: 66 45 0f db c1 pand %xmm9,%xmm8 - 4365ab: 66 45 0f db d3 pand %xmm11,%xmm10 - 4365b0: 66 44 0f db c7 pand %xmm7,%xmm8 - 4365b5: 66 44 0f db d7 pand %xmm7,%xmm10 - 4365ba: 66 41 0f eb c8 por %xmm8,%xmm1 - 4365bf: 66 41 0f eb d2 por %xmm10,%xmm2 - 4365c4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4365c8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 4365cc: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4365d0: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4365d4: 81 ea ff ff 00 00 sub $0xffff,%edx - 4365da: 0f 85 30 17 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 4365e0: 48 83 c1 10 add $0x10,%rcx - 4365e4: 66 0f 6f dc movdqa %xmm4,%xmm3 - 4365e8: 49 83 c2 10 add $0x10,%r10 - 4365ec: 0f 8f 8e 00 00 00 jg 436680 <__strcasecmp_l_ssse3+0xa50> - 4365f2: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4365f7: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4365fc: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 436600: 66 0f 3a 0f d3 04 palignr $0x4,%xmm3,%xmm2 - 436606: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 43660b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 436610: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 436615: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 43661a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 43661f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 436624: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 436629: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 43662e: 66 45 0f db c1 pand %xmm9,%xmm8 - 436633: 66 45 0f db d3 pand %xmm11,%xmm10 - 436638: 66 44 0f db c7 pand %xmm7,%xmm8 - 43663d: 66 44 0f db d7 pand %xmm7,%xmm10 - 436642: 66 41 0f eb c8 por %xmm8,%xmm1 - 436647: 66 41 0f eb d2 por %xmm10,%xmm2 - 43664c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 436650: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 436654: 66 0f f8 c8 psubb %xmm0,%xmm1 - 436658: 66 0f d7 d1 pmovmskb %xmm1,%edx - 43665c: 81 ea ff ff 00 00 sub $0xffff,%edx - 436662: 0f 85 a8 16 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 436668: 48 83 c1 10 add $0x10,%rcx - 43666c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 436670: e9 eb fe ff ff jmpq 436560 <__strcasecmp_l_ssse3+0x930> - 436675: 90 nop - 436676: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43667d: 00 00 00 - 436680: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 436684: 66 0f d7 d0 pmovmskb %xmm0,%edx - 436688: f7 c2 f0 ff 00 00 test $0xfff0,%edx - 43668e: 75 10 jne 4366a0 <__strcasecmp_l_ssse3+0xa70> - 436690: 66 0f ef c0 pxor %xmm0,%xmm0 - 436694: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 43669b: e9 ca fe ff ff jmpq 43656a <__strcasecmp_l_ssse3+0x93a> - 4366a0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4366a5: 66 0f 73 d8 04 psrldq $0x4,%xmm0 - 4366aa: 66 0f 73 db 04 psrldq $0x4,%xmm3 - 4366af: e9 fc 15 00 00 jmpq 437cb0 <__strcasecmp_l_ssse3+0x2080> - 4366b4: 66 90 xchg %ax,%ax - 4366b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4366bd: 00 00 00 - 4366c0: 66 0f ef c0 pxor %xmm0,%xmm0 - 4366c4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 4366c8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 4366cc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4366d0: 66 0f 73 fa 0b pslldq $0xb,%xmm2 - 4366d5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 4366da: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 4366df: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 4366e4: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 4366e9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 4366ee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 4366f3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 4366f8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 4366fd: 66 45 0f db c1 pand %xmm9,%xmm8 - 436702: 66 45 0f db d3 pand %xmm11,%xmm10 - 436707: 66 44 0f db c7 pand %xmm7,%xmm8 - 43670c: 66 44 0f db d7 pand %xmm7,%xmm10 - 436711: 66 41 0f eb c8 por %xmm8,%xmm1 - 436716: 66 41 0f eb d2 por %xmm10,%xmm2 - 43671b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 43671f: 66 0f f8 d0 psubb %xmm0,%xmm2 - 436723: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 436728: d3 ea shr %cl,%edx - 43672a: 41 d3 e9 shr %cl,%r9d - 43672d: 44 29 ca sub %r9d,%edx - 436730: 0f 85 df 15 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> - 436736: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 43673a: 66 0f ef c0 pxor %xmm0,%xmm0 - 43673e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 436745: 41 b9 05 00 00 00 mov $0x5,%r9d - 43674b: 4c 8d 57 05 lea 0x5(%rdi),%r10 - 43674f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 436756: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 43675d: 0f 1f 00 nopl (%rax) - 436760: 49 83 c2 10 add $0x10,%r10 - 436764: 0f 8f 16 01 00 00 jg 436880 <__strcasecmp_l_ssse3+0xc50> - 43676a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 43676f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 436774: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 436778: 66 0f 3a 0f d3 05 palignr $0x5,%xmm3,%xmm2 - 43677e: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 436783: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 436788: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 43678d: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 436792: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 436797: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 43679c: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 4367a1: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 4367a6: 66 45 0f db c1 pand %xmm9,%xmm8 - 4367ab: 66 45 0f db d3 pand %xmm11,%xmm10 - 4367b0: 66 44 0f db c7 pand %xmm7,%xmm8 - 4367b5: 66 44 0f db d7 pand %xmm7,%xmm10 - 4367ba: 66 41 0f eb c8 por %xmm8,%xmm1 - 4367bf: 66 41 0f eb d2 por %xmm10,%xmm2 - 4367c4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4367c8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 4367cc: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4367d0: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4367d4: 81 ea ff ff 00 00 sub $0xffff,%edx - 4367da: 0f 85 30 15 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 4367e0: 48 83 c1 10 add $0x10,%rcx - 4367e4: 66 0f 6f dc movdqa %xmm4,%xmm3 - 4367e8: 49 83 c2 10 add $0x10,%r10 - 4367ec: 0f 8f 8e 00 00 00 jg 436880 <__strcasecmp_l_ssse3+0xc50> - 4367f2: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4367f7: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4367fc: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 436800: 66 0f 3a 0f d3 05 palignr $0x5,%xmm3,%xmm2 - 436806: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 43680b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 436810: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 436815: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 43681a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 43681f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 436824: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 436829: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 43682e: 66 45 0f db c1 pand %xmm9,%xmm8 - 436833: 66 45 0f db d3 pand %xmm11,%xmm10 - 436838: 66 44 0f db c7 pand %xmm7,%xmm8 - 43683d: 66 44 0f db d7 pand %xmm7,%xmm10 - 436842: 66 41 0f eb c8 por %xmm8,%xmm1 - 436847: 66 41 0f eb d2 por %xmm10,%xmm2 - 43684c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 436850: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 436854: 66 0f f8 c8 psubb %xmm0,%xmm1 - 436858: 66 0f d7 d1 pmovmskb %xmm1,%edx - 43685c: 81 ea ff ff 00 00 sub $0xffff,%edx - 436862: 0f 85 a8 14 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 436868: 48 83 c1 10 add $0x10,%rcx - 43686c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 436870: e9 eb fe ff ff jmpq 436760 <__strcasecmp_l_ssse3+0xb30> - 436875: 90 nop - 436876: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43687d: 00 00 00 - 436880: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 436884: 66 0f d7 d0 pmovmskb %xmm0,%edx - 436888: f7 c2 e0 ff 00 00 test $0xffe0,%edx - 43688e: 75 10 jne 4368a0 <__strcasecmp_l_ssse3+0xc70> - 436890: 66 0f ef c0 pxor %xmm0,%xmm0 - 436894: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 43689b: e9 ca fe ff ff jmpq 43676a <__strcasecmp_l_ssse3+0xb3a> - 4368a0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4368a5: 66 0f 73 d8 05 psrldq $0x5,%xmm0 - 4368aa: 66 0f 73 db 05 psrldq $0x5,%xmm3 - 4368af: e9 fc 13 00 00 jmpq 437cb0 <__strcasecmp_l_ssse3+0x2080> - 4368b4: 66 90 xchg %ax,%ax - 4368b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4368bd: 00 00 00 - 4368c0: 66 0f ef c0 pxor %xmm0,%xmm0 - 4368c4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 4368c8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 4368cc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4368d0: 66 0f 73 fa 0a pslldq $0xa,%xmm2 - 4368d5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 4368da: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 4368df: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 4368e4: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 4368e9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 4368ee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 4368f3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 4368f8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 4368fd: 66 45 0f db c1 pand %xmm9,%xmm8 - 436902: 66 45 0f db d3 pand %xmm11,%xmm10 - 436907: 66 44 0f db c7 pand %xmm7,%xmm8 - 43690c: 66 44 0f db d7 pand %xmm7,%xmm10 - 436911: 66 41 0f eb c8 por %xmm8,%xmm1 - 436916: 66 41 0f eb d2 por %xmm10,%xmm2 - 43691b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 43691f: 66 0f f8 d0 psubb %xmm0,%xmm2 - 436923: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 436928: d3 ea shr %cl,%edx - 43692a: 41 d3 e9 shr %cl,%r9d - 43692d: 44 29 ca sub %r9d,%edx - 436930: 0f 85 df 13 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> - 436936: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 43693a: 66 0f ef c0 pxor %xmm0,%xmm0 - 43693e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 436945: 41 b9 06 00 00 00 mov $0x6,%r9d - 43694b: 4c 8d 57 06 lea 0x6(%rdi),%r10 - 43694f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 436956: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 43695d: 0f 1f 00 nopl (%rax) - 436960: 49 83 c2 10 add $0x10,%r10 - 436964: 0f 8f 16 01 00 00 jg 436a80 <__strcasecmp_l_ssse3+0xe50> - 43696a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 43696f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 436974: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 436978: 66 0f 3a 0f d3 06 palignr $0x6,%xmm3,%xmm2 - 43697e: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 436983: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 436988: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 43698d: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 436992: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 436997: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 43699c: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 4369a1: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 4369a6: 66 45 0f db c1 pand %xmm9,%xmm8 - 4369ab: 66 45 0f db d3 pand %xmm11,%xmm10 - 4369b0: 66 44 0f db c7 pand %xmm7,%xmm8 - 4369b5: 66 44 0f db d7 pand %xmm7,%xmm10 - 4369ba: 66 41 0f eb c8 por %xmm8,%xmm1 - 4369bf: 66 41 0f eb d2 por %xmm10,%xmm2 - 4369c4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4369c8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 4369cc: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4369d0: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4369d4: 81 ea ff ff 00 00 sub $0xffff,%edx - 4369da: 0f 85 30 13 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 4369e0: 48 83 c1 10 add $0x10,%rcx - 4369e4: 66 0f 6f dc movdqa %xmm4,%xmm3 - 4369e8: 49 83 c2 10 add $0x10,%r10 - 4369ec: 0f 8f 8e 00 00 00 jg 436a80 <__strcasecmp_l_ssse3+0xe50> - 4369f2: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4369f7: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4369fc: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 436a00: 66 0f 3a 0f d3 06 palignr $0x6,%xmm3,%xmm2 - 436a06: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 436a0b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 436a10: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 436a15: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 436a1a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 436a1f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 436a24: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 436a29: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 436a2e: 66 45 0f db c1 pand %xmm9,%xmm8 - 436a33: 66 45 0f db d3 pand %xmm11,%xmm10 - 436a38: 66 44 0f db c7 pand %xmm7,%xmm8 - 436a3d: 66 44 0f db d7 pand %xmm7,%xmm10 - 436a42: 66 41 0f eb c8 por %xmm8,%xmm1 - 436a47: 66 41 0f eb d2 por %xmm10,%xmm2 - 436a4c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 436a50: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 436a54: 66 0f f8 c8 psubb %xmm0,%xmm1 - 436a58: 66 0f d7 d1 pmovmskb %xmm1,%edx - 436a5c: 81 ea ff ff 00 00 sub $0xffff,%edx - 436a62: 0f 85 a8 12 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 436a68: 48 83 c1 10 add $0x10,%rcx - 436a6c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 436a70: e9 eb fe ff ff jmpq 436960 <__strcasecmp_l_ssse3+0xd30> - 436a75: 90 nop - 436a76: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 436a7d: 00 00 00 - 436a80: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 436a84: 66 0f d7 d0 pmovmskb %xmm0,%edx - 436a88: f7 c2 c0 ff 00 00 test $0xffc0,%edx - 436a8e: 75 10 jne 436aa0 <__strcasecmp_l_ssse3+0xe70> - 436a90: 66 0f ef c0 pxor %xmm0,%xmm0 - 436a94: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 436a9b: e9 ca fe ff ff jmpq 43696a <__strcasecmp_l_ssse3+0xd3a> - 436aa0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 436aa5: 66 0f 73 d8 06 psrldq $0x6,%xmm0 - 436aaa: 66 0f 73 db 06 psrldq $0x6,%xmm3 - 436aaf: e9 fc 11 00 00 jmpq 437cb0 <__strcasecmp_l_ssse3+0x2080> - 436ab4: 66 90 xchg %ax,%ax - 436ab6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 436abd: 00 00 00 - 436ac0: 66 0f ef c0 pxor %xmm0,%xmm0 - 436ac4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 436ac8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 436acc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 436ad0: 66 0f 73 fa 09 pslldq $0x9,%xmm2 - 436ad5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 436ada: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 436adf: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 436ae4: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 436ae9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 436aee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 436af3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 436af8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 436afd: 66 45 0f db c1 pand %xmm9,%xmm8 - 436b02: 66 45 0f db d3 pand %xmm11,%xmm10 - 436b07: 66 44 0f db c7 pand %xmm7,%xmm8 - 436b0c: 66 44 0f db d7 pand %xmm7,%xmm10 - 436b11: 66 41 0f eb c8 por %xmm8,%xmm1 - 436b16: 66 41 0f eb d2 por %xmm10,%xmm2 - 436b1b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 436b1f: 66 0f f8 d0 psubb %xmm0,%xmm2 - 436b23: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 436b28: d3 ea shr %cl,%edx - 436b2a: 41 d3 e9 shr %cl,%r9d - 436b2d: 44 29 ca sub %r9d,%edx - 436b30: 0f 85 df 11 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> - 436b36: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 436b3a: 66 0f ef c0 pxor %xmm0,%xmm0 - 436b3e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 436b45: 41 b9 07 00 00 00 mov $0x7,%r9d - 436b4b: 4c 8d 57 07 lea 0x7(%rdi),%r10 - 436b4f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 436b56: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 436b5d: 0f 1f 00 nopl (%rax) - 436b60: 49 83 c2 10 add $0x10,%r10 - 436b64: 0f 8f 16 01 00 00 jg 436c80 <__strcasecmp_l_ssse3+0x1050> - 436b6a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 436b6f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 436b74: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 436b78: 66 0f 3a 0f d3 07 palignr $0x7,%xmm3,%xmm2 - 436b7e: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 436b83: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 436b88: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 436b8d: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 436b92: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 436b97: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 436b9c: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 436ba1: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 436ba6: 66 45 0f db c1 pand %xmm9,%xmm8 - 436bab: 66 45 0f db d3 pand %xmm11,%xmm10 - 436bb0: 66 44 0f db c7 pand %xmm7,%xmm8 - 436bb5: 66 44 0f db d7 pand %xmm7,%xmm10 - 436bba: 66 41 0f eb c8 por %xmm8,%xmm1 - 436bbf: 66 41 0f eb d2 por %xmm10,%xmm2 - 436bc4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 436bc8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 436bcc: 66 0f f8 c8 psubb %xmm0,%xmm1 - 436bd0: 66 0f d7 d1 pmovmskb %xmm1,%edx - 436bd4: 81 ea ff ff 00 00 sub $0xffff,%edx - 436bda: 0f 85 30 11 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 436be0: 48 83 c1 10 add $0x10,%rcx - 436be4: 66 0f 6f dc movdqa %xmm4,%xmm3 - 436be8: 49 83 c2 10 add $0x10,%r10 - 436bec: 0f 8f 8e 00 00 00 jg 436c80 <__strcasecmp_l_ssse3+0x1050> - 436bf2: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 436bf7: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 436bfc: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 436c00: 66 0f 3a 0f d3 07 palignr $0x7,%xmm3,%xmm2 - 436c06: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 436c0b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 436c10: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 436c15: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 436c1a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 436c1f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 436c24: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 436c29: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 436c2e: 66 45 0f db c1 pand %xmm9,%xmm8 - 436c33: 66 45 0f db d3 pand %xmm11,%xmm10 - 436c38: 66 44 0f db c7 pand %xmm7,%xmm8 - 436c3d: 66 44 0f db d7 pand %xmm7,%xmm10 - 436c42: 66 41 0f eb c8 por %xmm8,%xmm1 - 436c47: 66 41 0f eb d2 por %xmm10,%xmm2 - 436c4c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 436c50: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 436c54: 66 0f f8 c8 psubb %xmm0,%xmm1 - 436c58: 66 0f d7 d1 pmovmskb %xmm1,%edx - 436c5c: 81 ea ff ff 00 00 sub $0xffff,%edx - 436c62: 0f 85 a8 10 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 436c68: 48 83 c1 10 add $0x10,%rcx - 436c6c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 436c70: e9 eb fe ff ff jmpq 436b60 <__strcasecmp_l_ssse3+0xf30> - 436c75: 90 nop - 436c76: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 436c7d: 00 00 00 - 436c80: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 436c84: 66 0f d7 d0 pmovmskb %xmm0,%edx - 436c88: f7 c2 80 ff 00 00 test $0xff80,%edx - 436c8e: 75 10 jne 436ca0 <__strcasecmp_l_ssse3+0x1070> - 436c90: 66 0f ef c0 pxor %xmm0,%xmm0 - 436c94: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 436c9b: e9 ca fe ff ff jmpq 436b6a <__strcasecmp_l_ssse3+0xf3a> - 436ca0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 436ca5: 66 0f 73 d8 07 psrldq $0x7,%xmm0 - 436caa: 66 0f 73 db 07 psrldq $0x7,%xmm3 - 436caf: e9 fc 0f 00 00 jmpq 437cb0 <__strcasecmp_l_ssse3+0x2080> - 436cb4: 66 90 xchg %ax,%ax - 436cb6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 436cbd: 00 00 00 - 436cc0: 66 0f ef c0 pxor %xmm0,%xmm0 - 436cc4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 436cc8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 436ccc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 436cd0: 66 0f 73 fa 08 pslldq $0x8,%xmm2 - 436cd5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 436cda: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 436cdf: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 436ce4: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 436ce9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 436cee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 436cf3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 436cf8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 436cfd: 66 45 0f db c1 pand %xmm9,%xmm8 - 436d02: 66 45 0f db d3 pand %xmm11,%xmm10 - 436d07: 66 44 0f db c7 pand %xmm7,%xmm8 - 436d0c: 66 44 0f db d7 pand %xmm7,%xmm10 - 436d11: 66 41 0f eb c8 por %xmm8,%xmm1 - 436d16: 66 41 0f eb d2 por %xmm10,%xmm2 - 436d1b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 436d1f: 66 0f f8 d0 psubb %xmm0,%xmm2 - 436d23: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 436d28: d3 ea shr %cl,%edx - 436d2a: 41 d3 e9 shr %cl,%r9d - 436d2d: 44 29 ca sub %r9d,%edx - 436d30: 0f 85 df 0f 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> - 436d36: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 436d3a: 66 0f ef c0 pxor %xmm0,%xmm0 - 436d3e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 436d45: 41 b9 08 00 00 00 mov $0x8,%r9d - 436d4b: 4c 8d 57 08 lea 0x8(%rdi),%r10 - 436d4f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 436d56: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 436d5d: 0f 1f 00 nopl (%rax) - 436d60: 49 83 c2 10 add $0x10,%r10 - 436d64: 0f 8f 16 01 00 00 jg 436e80 <__strcasecmp_l_ssse3+0x1250> - 436d6a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 436d6f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 436d74: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 436d78: 66 0f 3a 0f d3 08 palignr $0x8,%xmm3,%xmm2 - 436d7e: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 436d83: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 436d88: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 436d8d: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 436d92: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 436d97: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 436d9c: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 436da1: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 436da6: 66 45 0f db c1 pand %xmm9,%xmm8 - 436dab: 66 45 0f db d3 pand %xmm11,%xmm10 - 436db0: 66 44 0f db c7 pand %xmm7,%xmm8 - 436db5: 66 44 0f db d7 pand %xmm7,%xmm10 - 436dba: 66 41 0f eb c8 por %xmm8,%xmm1 - 436dbf: 66 41 0f eb d2 por %xmm10,%xmm2 - 436dc4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 436dc8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 436dcc: 66 0f f8 c8 psubb %xmm0,%xmm1 - 436dd0: 66 0f d7 d1 pmovmskb %xmm1,%edx - 436dd4: 81 ea ff ff 00 00 sub $0xffff,%edx - 436dda: 0f 85 30 0f 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 436de0: 48 83 c1 10 add $0x10,%rcx - 436de4: 66 0f 6f dc movdqa %xmm4,%xmm3 - 436de8: 49 83 c2 10 add $0x10,%r10 - 436dec: 0f 8f 8e 00 00 00 jg 436e80 <__strcasecmp_l_ssse3+0x1250> - 436df2: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 436df7: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 436dfc: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 436e00: 66 0f 3a 0f d3 08 palignr $0x8,%xmm3,%xmm2 - 436e06: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 436e0b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 436e10: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 436e15: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 436e1a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 436e1f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 436e24: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 436e29: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 436e2e: 66 45 0f db c1 pand %xmm9,%xmm8 - 436e33: 66 45 0f db d3 pand %xmm11,%xmm10 - 436e38: 66 44 0f db c7 pand %xmm7,%xmm8 - 436e3d: 66 44 0f db d7 pand %xmm7,%xmm10 - 436e42: 66 41 0f eb c8 por %xmm8,%xmm1 - 436e47: 66 41 0f eb d2 por %xmm10,%xmm2 - 436e4c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 436e50: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 436e54: 66 0f f8 c8 psubb %xmm0,%xmm1 - 436e58: 66 0f d7 d1 pmovmskb %xmm1,%edx - 436e5c: 81 ea ff ff 00 00 sub $0xffff,%edx - 436e62: 0f 85 a8 0e 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 436e68: 48 83 c1 10 add $0x10,%rcx - 436e6c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 436e70: e9 eb fe ff ff jmpq 436d60 <__strcasecmp_l_ssse3+0x1130> - 436e75: 90 nop - 436e76: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 436e7d: 00 00 00 - 436e80: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 436e84: 66 0f d7 d0 pmovmskb %xmm0,%edx - 436e88: f7 c2 00 ff 00 00 test $0xff00,%edx - 436e8e: 75 10 jne 436ea0 <__strcasecmp_l_ssse3+0x1270> - 436e90: 66 0f ef c0 pxor %xmm0,%xmm0 - 436e94: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 436e9b: e9 ca fe ff ff jmpq 436d6a <__strcasecmp_l_ssse3+0x113a> - 436ea0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 436ea5: 66 0f 73 d8 08 psrldq $0x8,%xmm0 - 436eaa: 66 0f 73 db 08 psrldq $0x8,%xmm3 - 436eaf: e9 fc 0d 00 00 jmpq 437cb0 <__strcasecmp_l_ssse3+0x2080> - 436eb4: 66 90 xchg %ax,%ax - 436eb6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 436ebd: 00 00 00 - 436ec0: 66 0f ef c0 pxor %xmm0,%xmm0 - 436ec4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 436ec8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 436ecc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 436ed0: 66 0f 73 fa 07 pslldq $0x7,%xmm2 - 436ed5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 436eda: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 436edf: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 436ee4: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 436ee9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 436eee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 436ef3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 436ef8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 436efd: 66 45 0f db c1 pand %xmm9,%xmm8 - 436f02: 66 45 0f db d3 pand %xmm11,%xmm10 - 436f07: 66 44 0f db c7 pand %xmm7,%xmm8 - 436f0c: 66 44 0f db d7 pand %xmm7,%xmm10 - 436f11: 66 41 0f eb c8 por %xmm8,%xmm1 - 436f16: 66 41 0f eb d2 por %xmm10,%xmm2 - 436f1b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 436f1f: 66 0f f8 d0 psubb %xmm0,%xmm2 - 436f23: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 436f28: d3 ea shr %cl,%edx - 436f2a: 41 d3 e9 shr %cl,%r9d - 436f2d: 44 29 ca sub %r9d,%edx - 436f30: 0f 85 df 0d 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> - 436f36: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 436f3a: 66 0f ef c0 pxor %xmm0,%xmm0 - 436f3e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 436f45: 41 b9 09 00 00 00 mov $0x9,%r9d - 436f4b: 4c 8d 57 09 lea 0x9(%rdi),%r10 - 436f4f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 436f56: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 436f5d: 0f 1f 00 nopl (%rax) - 436f60: 49 83 c2 10 add $0x10,%r10 - 436f64: 0f 8f 16 01 00 00 jg 437080 <__strcasecmp_l_ssse3+0x1450> - 436f6a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 436f6f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 436f74: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 436f78: 66 0f 3a 0f d3 09 palignr $0x9,%xmm3,%xmm2 - 436f7e: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 436f83: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 436f88: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 436f8d: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 436f92: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 436f97: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 436f9c: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 436fa1: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 436fa6: 66 45 0f db c1 pand %xmm9,%xmm8 - 436fab: 66 45 0f db d3 pand %xmm11,%xmm10 - 436fb0: 66 44 0f db c7 pand %xmm7,%xmm8 - 436fb5: 66 44 0f db d7 pand %xmm7,%xmm10 - 436fba: 66 41 0f eb c8 por %xmm8,%xmm1 - 436fbf: 66 41 0f eb d2 por %xmm10,%xmm2 - 436fc4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 436fc8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 436fcc: 66 0f f8 c8 psubb %xmm0,%xmm1 - 436fd0: 66 0f d7 d1 pmovmskb %xmm1,%edx - 436fd4: 81 ea ff ff 00 00 sub $0xffff,%edx - 436fda: 0f 85 30 0d 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 436fe0: 48 83 c1 10 add $0x10,%rcx - 436fe4: 66 0f 6f dc movdqa %xmm4,%xmm3 - 436fe8: 49 83 c2 10 add $0x10,%r10 - 436fec: 0f 8f 8e 00 00 00 jg 437080 <__strcasecmp_l_ssse3+0x1450> - 436ff2: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 436ff7: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 436ffc: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 437000: 66 0f 3a 0f d3 09 palignr $0x9,%xmm3,%xmm2 - 437006: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 43700b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 437010: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 437015: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 43701a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 43701f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 437024: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 437029: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 43702e: 66 45 0f db c1 pand %xmm9,%xmm8 - 437033: 66 45 0f db d3 pand %xmm11,%xmm10 - 437038: 66 44 0f db c7 pand %xmm7,%xmm8 - 43703d: 66 44 0f db d7 pand %xmm7,%xmm10 - 437042: 66 41 0f eb c8 por %xmm8,%xmm1 - 437047: 66 41 0f eb d2 por %xmm10,%xmm2 - 43704c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 437050: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 437054: 66 0f f8 c8 psubb %xmm0,%xmm1 - 437058: 66 0f d7 d1 pmovmskb %xmm1,%edx - 43705c: 81 ea ff ff 00 00 sub $0xffff,%edx - 437062: 0f 85 a8 0c 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 437068: 48 83 c1 10 add $0x10,%rcx - 43706c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 437070: e9 eb fe ff ff jmpq 436f60 <__strcasecmp_l_ssse3+0x1330> - 437075: 90 nop - 437076: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43707d: 00 00 00 - 437080: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 437084: 66 0f d7 d0 pmovmskb %xmm0,%edx - 437088: f7 c2 00 fe 00 00 test $0xfe00,%edx - 43708e: 75 10 jne 4370a0 <__strcasecmp_l_ssse3+0x1470> - 437090: 66 0f ef c0 pxor %xmm0,%xmm0 - 437094: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 43709b: e9 ca fe ff ff jmpq 436f6a <__strcasecmp_l_ssse3+0x133a> - 4370a0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4370a5: 66 0f 73 d8 09 psrldq $0x9,%xmm0 - 4370aa: 66 0f 73 db 09 psrldq $0x9,%xmm3 - 4370af: e9 fc 0b 00 00 jmpq 437cb0 <__strcasecmp_l_ssse3+0x2080> - 4370b4: 66 90 xchg %ax,%ax - 4370b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4370bd: 00 00 00 - 4370c0: 66 0f ef c0 pxor %xmm0,%xmm0 - 4370c4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 4370c8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 4370cc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4370d0: 66 0f 73 fa 06 pslldq $0x6,%xmm2 - 4370d5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 4370da: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 4370df: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 4370e4: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 4370e9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 4370ee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 4370f3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 4370f8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 4370fd: 66 45 0f db c1 pand %xmm9,%xmm8 - 437102: 66 45 0f db d3 pand %xmm11,%xmm10 - 437107: 66 44 0f db c7 pand %xmm7,%xmm8 - 43710c: 66 44 0f db d7 pand %xmm7,%xmm10 - 437111: 66 41 0f eb c8 por %xmm8,%xmm1 - 437116: 66 41 0f eb d2 por %xmm10,%xmm2 - 43711b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 43711f: 66 0f f8 d0 psubb %xmm0,%xmm2 - 437123: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 437128: d3 ea shr %cl,%edx - 43712a: 41 d3 e9 shr %cl,%r9d - 43712d: 44 29 ca sub %r9d,%edx - 437130: 0f 85 df 0b 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> - 437136: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 43713a: 66 0f ef c0 pxor %xmm0,%xmm0 - 43713e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 437145: 41 b9 0a 00 00 00 mov $0xa,%r9d - 43714b: 4c 8d 57 0a lea 0xa(%rdi),%r10 - 43714f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 437156: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 43715d: 0f 1f 00 nopl (%rax) - 437160: 49 83 c2 10 add $0x10,%r10 - 437164: 0f 8f 16 01 00 00 jg 437280 <__strcasecmp_l_ssse3+0x1650> - 43716a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 43716f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 437174: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 437178: 66 0f 3a 0f d3 0a palignr $0xa,%xmm3,%xmm2 - 43717e: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 437183: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 437188: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 43718d: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 437192: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 437197: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 43719c: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 4371a1: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 4371a6: 66 45 0f db c1 pand %xmm9,%xmm8 - 4371ab: 66 45 0f db d3 pand %xmm11,%xmm10 - 4371b0: 66 44 0f db c7 pand %xmm7,%xmm8 - 4371b5: 66 44 0f db d7 pand %xmm7,%xmm10 - 4371ba: 66 41 0f eb c8 por %xmm8,%xmm1 - 4371bf: 66 41 0f eb d2 por %xmm10,%xmm2 - 4371c4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4371c8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 4371cc: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4371d0: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4371d4: 81 ea ff ff 00 00 sub $0xffff,%edx - 4371da: 0f 85 30 0b 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 4371e0: 48 83 c1 10 add $0x10,%rcx - 4371e4: 66 0f 6f dc movdqa %xmm4,%xmm3 - 4371e8: 49 83 c2 10 add $0x10,%r10 - 4371ec: 0f 8f 8e 00 00 00 jg 437280 <__strcasecmp_l_ssse3+0x1650> - 4371f2: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4371f7: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4371fc: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 437200: 66 0f 3a 0f d3 0a palignr $0xa,%xmm3,%xmm2 - 437206: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 43720b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 437210: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 437215: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 43721a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 43721f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 437224: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 437229: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 43722e: 66 45 0f db c1 pand %xmm9,%xmm8 - 437233: 66 45 0f db d3 pand %xmm11,%xmm10 - 437238: 66 44 0f db c7 pand %xmm7,%xmm8 - 43723d: 66 44 0f db d7 pand %xmm7,%xmm10 - 437242: 66 41 0f eb c8 por %xmm8,%xmm1 - 437247: 66 41 0f eb d2 por %xmm10,%xmm2 - 43724c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 437250: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 437254: 66 0f f8 c8 psubb %xmm0,%xmm1 - 437258: 66 0f d7 d1 pmovmskb %xmm1,%edx - 43725c: 81 ea ff ff 00 00 sub $0xffff,%edx - 437262: 0f 85 a8 0a 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 437268: 48 83 c1 10 add $0x10,%rcx - 43726c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 437270: e9 eb fe ff ff jmpq 437160 <__strcasecmp_l_ssse3+0x1530> - 437275: 90 nop - 437276: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43727d: 00 00 00 - 437280: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 437284: 66 0f d7 d0 pmovmskb %xmm0,%edx - 437288: f7 c2 00 fc 00 00 test $0xfc00,%edx - 43728e: 75 10 jne 4372a0 <__strcasecmp_l_ssse3+0x1670> - 437290: 66 0f ef c0 pxor %xmm0,%xmm0 - 437294: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 43729b: e9 ca fe ff ff jmpq 43716a <__strcasecmp_l_ssse3+0x153a> - 4372a0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4372a5: 66 0f 73 d8 0a psrldq $0xa,%xmm0 - 4372aa: 66 0f 73 db 0a psrldq $0xa,%xmm3 - 4372af: e9 fc 09 00 00 jmpq 437cb0 <__strcasecmp_l_ssse3+0x2080> - 4372b4: 66 90 xchg %ax,%ax - 4372b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4372bd: 00 00 00 - 4372c0: 66 0f ef c0 pxor %xmm0,%xmm0 - 4372c4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 4372c8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 4372cc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4372d0: 66 0f 73 fa 05 pslldq $0x5,%xmm2 - 4372d5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 4372da: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 4372df: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 4372e4: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 4372e9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 4372ee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 4372f3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 4372f8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 4372fd: 66 45 0f db c1 pand %xmm9,%xmm8 - 437302: 66 45 0f db d3 pand %xmm11,%xmm10 - 437307: 66 44 0f db c7 pand %xmm7,%xmm8 - 43730c: 66 44 0f db d7 pand %xmm7,%xmm10 - 437311: 66 41 0f eb c8 por %xmm8,%xmm1 - 437316: 66 41 0f eb d2 por %xmm10,%xmm2 - 43731b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 43731f: 66 0f f8 d0 psubb %xmm0,%xmm2 - 437323: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 437328: d3 ea shr %cl,%edx - 43732a: 41 d3 e9 shr %cl,%r9d - 43732d: 44 29 ca sub %r9d,%edx - 437330: 0f 85 df 09 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> - 437336: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 43733a: 66 0f ef c0 pxor %xmm0,%xmm0 - 43733e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 437345: 41 b9 0b 00 00 00 mov $0xb,%r9d - 43734b: 4c 8d 57 0b lea 0xb(%rdi),%r10 - 43734f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 437356: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 43735d: 0f 1f 00 nopl (%rax) - 437360: 49 83 c2 10 add $0x10,%r10 - 437364: 0f 8f 16 01 00 00 jg 437480 <__strcasecmp_l_ssse3+0x1850> - 43736a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 43736f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 437374: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 437378: 66 0f 3a 0f d3 0b palignr $0xb,%xmm3,%xmm2 - 43737e: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 437383: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 437388: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 43738d: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 437392: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 437397: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 43739c: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 4373a1: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 4373a6: 66 45 0f db c1 pand %xmm9,%xmm8 - 4373ab: 66 45 0f db d3 pand %xmm11,%xmm10 - 4373b0: 66 44 0f db c7 pand %xmm7,%xmm8 - 4373b5: 66 44 0f db d7 pand %xmm7,%xmm10 - 4373ba: 66 41 0f eb c8 por %xmm8,%xmm1 - 4373bf: 66 41 0f eb d2 por %xmm10,%xmm2 - 4373c4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4373c8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 4373cc: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4373d0: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4373d4: 81 ea ff ff 00 00 sub $0xffff,%edx - 4373da: 0f 85 30 09 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 4373e0: 48 83 c1 10 add $0x10,%rcx - 4373e4: 66 0f 6f dc movdqa %xmm4,%xmm3 - 4373e8: 49 83 c2 10 add $0x10,%r10 - 4373ec: 0f 8f 8e 00 00 00 jg 437480 <__strcasecmp_l_ssse3+0x1850> - 4373f2: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4373f7: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4373fc: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 437400: 66 0f 3a 0f d3 0b palignr $0xb,%xmm3,%xmm2 - 437406: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 43740b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 437410: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 437415: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 43741a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 43741f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 437424: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 437429: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 43742e: 66 45 0f db c1 pand %xmm9,%xmm8 - 437433: 66 45 0f db d3 pand %xmm11,%xmm10 - 437438: 66 44 0f db c7 pand %xmm7,%xmm8 - 43743d: 66 44 0f db d7 pand %xmm7,%xmm10 - 437442: 66 41 0f eb c8 por %xmm8,%xmm1 - 437447: 66 41 0f eb d2 por %xmm10,%xmm2 - 43744c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 437450: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 437454: 66 0f f8 c8 psubb %xmm0,%xmm1 - 437458: 66 0f d7 d1 pmovmskb %xmm1,%edx - 43745c: 81 ea ff ff 00 00 sub $0xffff,%edx - 437462: 0f 85 a8 08 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 437468: 48 83 c1 10 add $0x10,%rcx - 43746c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 437470: e9 eb fe ff ff jmpq 437360 <__strcasecmp_l_ssse3+0x1730> - 437475: 90 nop - 437476: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43747d: 00 00 00 - 437480: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 437484: 66 0f d7 d0 pmovmskb %xmm0,%edx - 437488: f7 c2 00 f8 00 00 test $0xf800,%edx - 43748e: 75 10 jne 4374a0 <__strcasecmp_l_ssse3+0x1870> - 437490: 66 0f ef c0 pxor %xmm0,%xmm0 - 437494: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 43749b: e9 ca fe ff ff jmpq 43736a <__strcasecmp_l_ssse3+0x173a> - 4374a0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4374a5: 66 0f 73 d8 0b psrldq $0xb,%xmm0 - 4374aa: 66 0f 73 db 0b psrldq $0xb,%xmm3 - 4374af: e9 fc 07 00 00 jmpq 437cb0 <__strcasecmp_l_ssse3+0x2080> - 4374b4: 66 90 xchg %ax,%ax - 4374b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4374bd: 00 00 00 - 4374c0: 66 0f ef c0 pxor %xmm0,%xmm0 - 4374c4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 4374c8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 4374cc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4374d0: 66 0f 73 fa 04 pslldq $0x4,%xmm2 - 4374d5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 4374da: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 4374df: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 4374e4: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 4374e9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 4374ee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 4374f3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 4374f8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 4374fd: 66 45 0f db c1 pand %xmm9,%xmm8 - 437502: 66 45 0f db d3 pand %xmm11,%xmm10 - 437507: 66 44 0f db c7 pand %xmm7,%xmm8 - 43750c: 66 44 0f db d7 pand %xmm7,%xmm10 - 437511: 66 41 0f eb c8 por %xmm8,%xmm1 - 437516: 66 41 0f eb d2 por %xmm10,%xmm2 - 43751b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 43751f: 66 0f f8 d0 psubb %xmm0,%xmm2 - 437523: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 437528: d3 ea shr %cl,%edx - 43752a: 41 d3 e9 shr %cl,%r9d - 43752d: 44 29 ca sub %r9d,%edx - 437530: 0f 85 df 07 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> - 437536: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 43753a: 66 0f ef c0 pxor %xmm0,%xmm0 - 43753e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 437545: 41 b9 0c 00 00 00 mov $0xc,%r9d - 43754b: 4c 8d 57 0c lea 0xc(%rdi),%r10 - 43754f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 437556: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 43755d: 0f 1f 00 nopl (%rax) - 437560: 49 83 c2 10 add $0x10,%r10 - 437564: 0f 8f 16 01 00 00 jg 437680 <__strcasecmp_l_ssse3+0x1a50> - 43756a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 43756f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 437574: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 437578: 66 0f 3a 0f d3 0c palignr $0xc,%xmm3,%xmm2 - 43757e: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 437583: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 437588: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 43758d: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 437592: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 437597: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 43759c: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 4375a1: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 4375a6: 66 45 0f db c1 pand %xmm9,%xmm8 - 4375ab: 66 45 0f db d3 pand %xmm11,%xmm10 - 4375b0: 66 44 0f db c7 pand %xmm7,%xmm8 - 4375b5: 66 44 0f db d7 pand %xmm7,%xmm10 - 4375ba: 66 41 0f eb c8 por %xmm8,%xmm1 - 4375bf: 66 41 0f eb d2 por %xmm10,%xmm2 - 4375c4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4375c8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 4375cc: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4375d0: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4375d4: 81 ea ff ff 00 00 sub $0xffff,%edx - 4375da: 0f 85 30 07 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 4375e0: 48 83 c1 10 add $0x10,%rcx - 4375e4: 66 0f 6f dc movdqa %xmm4,%xmm3 - 4375e8: 49 83 c2 10 add $0x10,%r10 - 4375ec: 0f 8f 8e 00 00 00 jg 437680 <__strcasecmp_l_ssse3+0x1a50> - 4375f2: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4375f7: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4375fc: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 437600: 66 0f 3a 0f d3 0c palignr $0xc,%xmm3,%xmm2 - 437606: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 43760b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 437610: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 437615: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 43761a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 43761f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 437624: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 437629: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 43762e: 66 45 0f db c1 pand %xmm9,%xmm8 - 437633: 66 45 0f db d3 pand %xmm11,%xmm10 - 437638: 66 44 0f db c7 pand %xmm7,%xmm8 - 43763d: 66 44 0f db d7 pand %xmm7,%xmm10 - 437642: 66 41 0f eb c8 por %xmm8,%xmm1 - 437647: 66 41 0f eb d2 por %xmm10,%xmm2 - 43764c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 437650: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 437654: 66 0f f8 c8 psubb %xmm0,%xmm1 - 437658: 66 0f d7 d1 pmovmskb %xmm1,%edx - 43765c: 81 ea ff ff 00 00 sub $0xffff,%edx - 437662: 0f 85 a8 06 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 437668: 48 83 c1 10 add $0x10,%rcx - 43766c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 437670: e9 eb fe ff ff jmpq 437560 <__strcasecmp_l_ssse3+0x1930> - 437675: 90 nop - 437676: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43767d: 00 00 00 - 437680: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 437684: 66 0f d7 d0 pmovmskb %xmm0,%edx - 437688: f7 c2 00 f0 00 00 test $0xf000,%edx - 43768e: 75 10 jne 4376a0 <__strcasecmp_l_ssse3+0x1a70> - 437690: 66 0f ef c0 pxor %xmm0,%xmm0 - 437694: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 43769b: e9 ca fe ff ff jmpq 43756a <__strcasecmp_l_ssse3+0x193a> - 4376a0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4376a5: 66 0f 73 d8 0c psrldq $0xc,%xmm0 - 4376aa: 66 0f 73 db 0c psrldq $0xc,%xmm3 - 4376af: e9 fc 05 00 00 jmpq 437cb0 <__strcasecmp_l_ssse3+0x2080> - 4376b4: 66 90 xchg %ax,%ax - 4376b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4376bd: 00 00 00 - 4376c0: 66 0f ef c0 pxor %xmm0,%xmm0 - 4376c4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 4376c8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 4376cc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4376d0: 66 0f 73 fa 03 pslldq $0x3,%xmm2 - 4376d5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 4376da: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 4376df: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 4376e4: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 4376e9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 4376ee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 4376f3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 4376f8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 4376fd: 66 45 0f db c1 pand %xmm9,%xmm8 - 437702: 66 45 0f db d3 pand %xmm11,%xmm10 - 437707: 66 44 0f db c7 pand %xmm7,%xmm8 - 43770c: 66 44 0f db d7 pand %xmm7,%xmm10 - 437711: 66 41 0f eb c8 por %xmm8,%xmm1 - 437716: 66 41 0f eb d2 por %xmm10,%xmm2 - 43771b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 43771f: 66 0f f8 d0 psubb %xmm0,%xmm2 - 437723: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 437728: d3 ea shr %cl,%edx - 43772a: 41 d3 e9 shr %cl,%r9d - 43772d: 44 29 ca sub %r9d,%edx - 437730: 0f 85 df 05 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> - 437736: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 43773a: 66 0f ef c0 pxor %xmm0,%xmm0 - 43773e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 437745: 41 b9 0d 00 00 00 mov $0xd,%r9d - 43774b: 4c 8d 57 0d lea 0xd(%rdi),%r10 - 43774f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 437756: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 43775d: 0f 1f 00 nopl (%rax) - 437760: 49 83 c2 10 add $0x10,%r10 - 437764: 0f 8f 16 01 00 00 jg 437880 <__strcasecmp_l_ssse3+0x1c50> - 43776a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 43776f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 437774: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 437778: 66 0f 3a 0f d3 0d palignr $0xd,%xmm3,%xmm2 - 43777e: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 437783: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 437788: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 43778d: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 437792: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 437797: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 43779c: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 4377a1: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 4377a6: 66 45 0f db c1 pand %xmm9,%xmm8 - 4377ab: 66 45 0f db d3 pand %xmm11,%xmm10 - 4377b0: 66 44 0f db c7 pand %xmm7,%xmm8 - 4377b5: 66 44 0f db d7 pand %xmm7,%xmm10 - 4377ba: 66 41 0f eb c8 por %xmm8,%xmm1 - 4377bf: 66 41 0f eb d2 por %xmm10,%xmm2 - 4377c4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4377c8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 4377cc: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4377d0: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4377d4: 81 ea ff ff 00 00 sub $0xffff,%edx - 4377da: 0f 85 30 05 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 4377e0: 48 83 c1 10 add $0x10,%rcx - 4377e4: 66 0f 6f dc movdqa %xmm4,%xmm3 - 4377e8: 49 83 c2 10 add $0x10,%r10 - 4377ec: 0f 8f 8e 00 00 00 jg 437880 <__strcasecmp_l_ssse3+0x1c50> - 4377f2: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4377f7: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4377fc: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 437800: 66 0f 3a 0f d3 0d palignr $0xd,%xmm3,%xmm2 - 437806: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 43780b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 437810: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 437815: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 43781a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 43781f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 437824: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 437829: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 43782e: 66 45 0f db c1 pand %xmm9,%xmm8 - 437833: 66 45 0f db d3 pand %xmm11,%xmm10 - 437838: 66 44 0f db c7 pand %xmm7,%xmm8 - 43783d: 66 44 0f db d7 pand %xmm7,%xmm10 - 437842: 66 41 0f eb c8 por %xmm8,%xmm1 - 437847: 66 41 0f eb d2 por %xmm10,%xmm2 - 43784c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 437850: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 437854: 66 0f f8 c8 psubb %xmm0,%xmm1 - 437858: 66 0f d7 d1 pmovmskb %xmm1,%edx - 43785c: 81 ea ff ff 00 00 sub $0xffff,%edx - 437862: 0f 85 a8 04 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 437868: 48 83 c1 10 add $0x10,%rcx - 43786c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 437870: e9 eb fe ff ff jmpq 437760 <__strcasecmp_l_ssse3+0x1b30> - 437875: 90 nop - 437876: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43787d: 00 00 00 - 437880: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 437884: 66 0f d7 d0 pmovmskb %xmm0,%edx - 437888: f7 c2 00 e0 00 00 test $0xe000,%edx - 43788e: 75 10 jne 4378a0 <__strcasecmp_l_ssse3+0x1c70> - 437890: 66 0f ef c0 pxor %xmm0,%xmm0 - 437894: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 43789b: e9 ca fe ff ff jmpq 43776a <__strcasecmp_l_ssse3+0x1b3a> - 4378a0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4378a5: 66 0f 73 d8 0d psrldq $0xd,%xmm0 - 4378aa: 66 0f 73 db 0d psrldq $0xd,%xmm3 - 4378af: e9 fc 03 00 00 jmpq 437cb0 <__strcasecmp_l_ssse3+0x2080> - 4378b4: 66 90 xchg %ax,%ax - 4378b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4378bd: 00 00 00 - 4378c0: 66 0f ef c0 pxor %xmm0,%xmm0 - 4378c4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 4378c8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 4378cc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4378d0: 66 0f 73 fa 02 pslldq $0x2,%xmm2 - 4378d5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 4378da: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 4378df: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 4378e4: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 4378e9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 4378ee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 4378f3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 4378f8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 4378fd: 66 45 0f db c1 pand %xmm9,%xmm8 - 437902: 66 45 0f db d3 pand %xmm11,%xmm10 - 437907: 66 44 0f db c7 pand %xmm7,%xmm8 - 43790c: 66 44 0f db d7 pand %xmm7,%xmm10 - 437911: 66 41 0f eb c8 por %xmm8,%xmm1 - 437916: 66 41 0f eb d2 por %xmm10,%xmm2 - 43791b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 43791f: 66 0f f8 d0 psubb %xmm0,%xmm2 - 437923: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 437928: d3 ea shr %cl,%edx - 43792a: 41 d3 e9 shr %cl,%r9d - 43792d: 44 29 ca sub %r9d,%edx - 437930: 0f 85 df 03 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> - 437936: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 43793a: 66 0f ef c0 pxor %xmm0,%xmm0 - 43793e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 437945: 41 b9 0e 00 00 00 mov $0xe,%r9d - 43794b: 4c 8d 57 0e lea 0xe(%rdi),%r10 - 43794f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 437956: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 43795d: 0f 1f 00 nopl (%rax) - 437960: 49 83 c2 10 add $0x10,%r10 - 437964: 0f 8f 16 01 00 00 jg 437a80 <__strcasecmp_l_ssse3+0x1e50> - 43796a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 43796f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 437974: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 437978: 66 0f 3a 0f d3 0e palignr $0xe,%xmm3,%xmm2 - 43797e: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 437983: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 437988: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 43798d: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 437992: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 437997: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 43799c: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 4379a1: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 4379a6: 66 45 0f db c1 pand %xmm9,%xmm8 - 4379ab: 66 45 0f db d3 pand %xmm11,%xmm10 - 4379b0: 66 44 0f db c7 pand %xmm7,%xmm8 - 4379b5: 66 44 0f db d7 pand %xmm7,%xmm10 - 4379ba: 66 41 0f eb c8 por %xmm8,%xmm1 - 4379bf: 66 41 0f eb d2 por %xmm10,%xmm2 - 4379c4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 4379c8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 4379cc: 66 0f f8 c8 psubb %xmm0,%xmm1 - 4379d0: 66 0f d7 d1 pmovmskb %xmm1,%edx - 4379d4: 81 ea ff ff 00 00 sub $0xffff,%edx - 4379da: 0f 85 30 03 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 4379e0: 48 83 c1 10 add $0x10,%rcx - 4379e4: 66 0f 6f dc movdqa %xmm4,%xmm3 - 4379e8: 49 83 c2 10 add $0x10,%r10 - 4379ec: 0f 8f 8e 00 00 00 jg 437a80 <__strcasecmp_l_ssse3+0x1e50> - 4379f2: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 4379f7: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 4379fc: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 437a00: 66 0f 3a 0f d3 0e palignr $0xe,%xmm3,%xmm2 - 437a06: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 437a0b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 437a10: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 437a15: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 437a1a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 437a1f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 437a24: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 437a29: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 437a2e: 66 45 0f db c1 pand %xmm9,%xmm8 - 437a33: 66 45 0f db d3 pand %xmm11,%xmm10 - 437a38: 66 44 0f db c7 pand %xmm7,%xmm8 - 437a3d: 66 44 0f db d7 pand %xmm7,%xmm10 - 437a42: 66 41 0f eb c8 por %xmm8,%xmm1 - 437a47: 66 41 0f eb d2 por %xmm10,%xmm2 - 437a4c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 437a50: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 437a54: 66 0f f8 c8 psubb %xmm0,%xmm1 - 437a58: 66 0f d7 d1 pmovmskb %xmm1,%edx - 437a5c: 81 ea ff ff 00 00 sub $0xffff,%edx - 437a62: 0f 85 a8 02 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 437a68: 48 83 c1 10 add $0x10,%rcx - 437a6c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 437a70: e9 eb fe ff ff jmpq 437960 <__strcasecmp_l_ssse3+0x1d30> - 437a75: 90 nop - 437a76: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 437a7d: 00 00 00 - 437a80: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 437a84: 66 0f d7 d0 pmovmskb %xmm0,%edx - 437a88: f7 c2 00 c0 00 00 test $0xc000,%edx - 437a8e: 75 10 jne 437aa0 <__strcasecmp_l_ssse3+0x1e70> - 437a90: 66 0f ef c0 pxor %xmm0,%xmm0 - 437a94: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 437a9b: e9 ca fe ff ff jmpq 43796a <__strcasecmp_l_ssse3+0x1d3a> - 437aa0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 437aa5: 66 0f 73 d8 0e psrldq $0xe,%xmm0 - 437aaa: 66 0f 73 db 0e psrldq $0xe,%xmm3 - 437aaf: e9 fc 01 00 00 jmpq 437cb0 <__strcasecmp_l_ssse3+0x2080> - 437ab4: 66 90 xchg %ax,%ax - 437ab6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 437abd: 00 00 00 - 437ac0: 66 0f ef c0 pxor %xmm0,%xmm0 - 437ac4: 66 0f 6f 17 movdqa (%rdi),%xmm2 - 437ac8: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 437acc: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 437ad0: 66 0f 73 fa 01 pslldq $0x1,%xmm2 - 437ad5: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 437ada: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 437adf: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 437ae4: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 437ae9: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 437aee: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 437af3: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 437af8: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 437afd: 66 45 0f db c1 pand %xmm9,%xmm8 - 437b02: 66 45 0f db d3 pand %xmm11,%xmm10 - 437b07: 66 44 0f db c7 pand %xmm7,%xmm8 - 437b0c: 66 44 0f db d7 pand %xmm7,%xmm10 - 437b11: 66 41 0f eb c8 por %xmm8,%xmm1 - 437b16: 66 41 0f eb d2 por %xmm10,%xmm2 - 437b1b: 66 0f 74 d1 pcmpeqb %xmm1,%xmm2 - 437b1f: 66 0f f8 d0 psubb %xmm0,%xmm2 - 437b23: 66 44 0f d7 ca pmovmskb %xmm2,%r9d - 437b28: d3 ea shr %cl,%edx - 437b2a: 41 d3 e9 shr %cl,%r9d - 437b2d: 44 29 ca sub %r9d,%edx - 437b30: 0f 85 df 01 00 00 jne 437d15 <__strcasecmp_l_ssse3+0x20e5> - 437b36: 66 0f 6f 1f movdqa (%rdi),%xmm3 - 437b3a: 66 0f ef c0 pxor %xmm0,%xmm0 - 437b3e: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 437b45: 41 b9 0f 00 00 00 mov $0xf,%r9d - 437b4b: 4c 8d 57 0f lea 0xf(%rdi),%r10 - 437b4f: 49 81 e2 ff 0f 00 00 and $0xfff,%r10 - 437b56: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 437b5d: 0f 1f 00 nopl (%rax) - 437b60: 49 83 c2 10 add $0x10,%r10 - 437b64: 0f 8f 16 01 00 00 jg 437c80 <__strcasecmp_l_ssse3+0x2050> - 437b6a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 437b6f: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 437b74: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 437b78: 66 0f 3a 0f d3 0f palignr $0xf,%xmm3,%xmm2 - 437b7e: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 437b83: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 437b88: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 437b8d: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 437b92: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 437b97: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 437b9c: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 437ba1: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 437ba6: 66 45 0f db c1 pand %xmm9,%xmm8 - 437bab: 66 45 0f db d3 pand %xmm11,%xmm10 - 437bb0: 66 44 0f db c7 pand %xmm7,%xmm8 - 437bb5: 66 44 0f db d7 pand %xmm7,%xmm10 - 437bba: 66 41 0f eb c8 por %xmm8,%xmm1 - 437bbf: 66 41 0f eb d2 por %xmm10,%xmm2 - 437bc4: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 437bc8: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 437bcc: 66 0f f8 c8 psubb %xmm0,%xmm1 - 437bd0: 66 0f d7 d1 pmovmskb %xmm1,%edx - 437bd4: 81 ea ff ff 00 00 sub $0xffff,%edx - 437bda: 0f 85 30 01 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 437be0: 48 83 c1 10 add $0x10,%rcx - 437be4: 66 0f 6f dc movdqa %xmm4,%xmm3 - 437be8: 49 83 c2 10 add $0x10,%r10 - 437bec: 0f 8f 8e 00 00 00 jg 437c80 <__strcasecmp_l_ssse3+0x2050> - 437bf2: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 437bf7: 66 0f 6f 14 0f movdqa (%rdi,%rcx,1),%xmm2 - 437bfc: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 437c00: 66 0f 3a 0f d3 0f palignr $0xf,%xmm3,%xmm2 - 437c06: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 437c0b: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 437c10: 66 44 0f 6f d2 movdqa %xmm2,%xmm10 - 437c15: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 437c1a: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 437c1f: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 437c24: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 437c29: 66 44 0f 64 da pcmpgtb %xmm2,%xmm11 - 437c2e: 66 45 0f db c1 pand %xmm9,%xmm8 - 437c33: 66 45 0f db d3 pand %xmm11,%xmm10 - 437c38: 66 44 0f db c7 pand %xmm7,%xmm8 - 437c3d: 66 44 0f db d7 pand %xmm7,%xmm10 - 437c42: 66 41 0f eb c8 por %xmm8,%xmm1 - 437c47: 66 41 0f eb d2 por %xmm10,%xmm2 - 437c4c: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 437c50: 66 0f 74 ca pcmpeqb %xmm2,%xmm1 - 437c54: 66 0f f8 c8 psubb %xmm0,%xmm1 - 437c58: 66 0f d7 d1 pmovmskb %xmm1,%edx - 437c5c: 81 ea ff ff 00 00 sub $0xffff,%edx - 437c62: 0f 85 a8 00 00 00 jne 437d10 <__strcasecmp_l_ssse3+0x20e0> - 437c68: 48 83 c1 10 add $0x10,%rcx - 437c6c: 66 0f 6f dc movdqa %xmm4,%xmm3 - 437c70: e9 eb fe ff ff jmpq 437b60 <__strcasecmp_l_ssse3+0x1f30> - 437c75: 90 nop - 437c76: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 437c7d: 00 00 00 - 437c80: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 437c84: 66 0f d7 d0 pmovmskb %xmm0,%edx - 437c88: f7 c2 00 80 00 00 test $0x8000,%edx - 437c8e: 75 10 jne 437ca0 <__strcasecmp_l_ssse3+0x2070> - 437c90: 66 0f ef c0 pxor %xmm0,%xmm0 - 437c94: 49 81 ea 00 10 00 00 sub $0x1000,%r10 - 437c9b: e9 ca fe ff ff jmpq 437b6a <__strcasecmp_l_ssse3+0x1f3a> - 437ca0: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 437ca5: 66 0f 73 db 0f psrldq $0xf,%xmm3 - 437caa: 66 0f 73 d8 0f psrldq $0xf,%xmm0 - 437caf: 90 nop - 437cb0: 66 44 0f 6f c1 movdqa %xmm1,%xmm8 - 437cb5: 66 44 0f 6f ce movdqa %xmm6,%xmm9 - 437cba: 66 44 0f 6f d3 movdqa %xmm3,%xmm10 - 437cbf: 66 44 0f 6f de movdqa %xmm6,%xmm11 - 437cc4: 66 44 0f 64 c5 pcmpgtb %xmm5,%xmm8 - 437cc9: 66 44 0f 64 c9 pcmpgtb %xmm1,%xmm9 - 437cce: 66 44 0f 64 d5 pcmpgtb %xmm5,%xmm10 - 437cd3: 66 44 0f 64 db pcmpgtb %xmm3,%xmm11 - 437cd8: 66 45 0f db c1 pand %xmm9,%xmm8 - 437cdd: 66 45 0f db d3 pand %xmm11,%xmm10 - 437ce2: 66 44 0f db c7 pand %xmm7,%xmm8 - 437ce7: 66 44 0f db d7 pand %xmm7,%xmm10 - 437cec: 66 41 0f eb c8 por %xmm8,%xmm1 - 437cf1: 66 41 0f eb da por %xmm10,%xmm3 - 437cf6: 66 0f 74 cb pcmpeqb %xmm3,%xmm1 - 437cfa: 66 0f f8 c8 psubb %xmm0,%xmm1 - 437cfe: 66 0f d7 d1 pmovmskb %xmm1,%edx - 437d02: f7 d2 not %edx - 437d04: 66 90 xchg %ax,%ax - 437d06: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 437d0d: 00 00 00 - 437d10: 49 8d 44 09 f0 lea -0x10(%r9,%rcx,1),%rax - 437d15: 48 8d 3c 07 lea (%rdi,%rax,1),%rdi - 437d19: 48 8d 34 0e lea (%rsi,%rcx,1),%rsi - 437d1d: 45 85 c0 test %r8d,%r8d - 437d20: 74 0e je 437d30 <__strcasecmp_l_ssse3+0x2100> - 437d22: 48 87 f7 xchg %rsi,%rdi - 437d25: 90 nop - 437d26: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 437d2d: 00 00 00 - 437d30: 48 0f bc d2 bsf %rdx,%rdx - 437d34: 0f b6 0c 16 movzbl (%rsi,%rdx,1),%ecx - 437d38: 0f b6 04 17 movzbl (%rdi,%rdx,1),%eax - 437d3c: 48 8d 15 fd f7 06 00 lea 0x6f7fd(%rip),%rdx # 4a7540 <_nl_C_LC_CTYPE_tolower+0x200> - 437d43: 8b 0c 8a mov (%rdx,%rcx,4),%ecx - 437d46: 8b 04 82 mov (%rdx,%rax,4),%eax - 437d49: 29 c8 sub %ecx,%eax - 437d4b: c3 retq - 437d4c: 31 c0 xor %eax,%eax - 437d4e: c3 retq - 437d4f: 90 nop - 437d50: 0f b6 0e movzbl (%rsi),%ecx - 437d53: 0f b6 07 movzbl (%rdi),%eax - 437d56: 48 8d 15 e3 f7 06 00 lea 0x6f7e3(%rip),%rdx # 4a7540 <_nl_C_LC_CTYPE_tolower+0x200> - 437d5d: 8b 0c 8a mov (%rdx,%rcx,4),%ecx - 437d60: 8b 04 82 mov (%rdx,%rax,4),%eax - 437d63: 29 c8 sub %ecx,%eax - 437d65: c3 retq - 437d66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 437d6d: 00 00 00 - -0000000000437d70 <__strcpy_ssse3>: - 437d70: 48 89 f1 mov %rsi,%rcx - 437d73: 48 89 fa mov %rdi,%rdx - 437d76: 80 39 00 cmpb $0x0,(%rcx) - 437d79: 0f 84 91 16 00 00 je 439410 <__strcpy_ssse3+0x16a0> - 437d7f: 80 79 01 00 cmpb $0x0,0x1(%rcx) - 437d83: 0f 84 97 16 00 00 je 439420 <__strcpy_ssse3+0x16b0> - 437d89: 80 79 02 00 cmpb $0x0,0x2(%rcx) - 437d8d: 0f 84 9d 16 00 00 je 439430 <__strcpy_ssse3+0x16c0> - 437d93: 80 79 03 00 cmpb $0x0,0x3(%rcx) - 437d97: 0f 84 a3 16 00 00 je 439440 <__strcpy_ssse3+0x16d0> - 437d9d: 80 79 04 00 cmpb $0x0,0x4(%rcx) - 437da1: 0f 84 a9 16 00 00 je 439450 <__strcpy_ssse3+0x16e0> - 437da7: 80 79 05 00 cmpb $0x0,0x5(%rcx) - 437dab: 0f 84 af 16 00 00 je 439460 <__strcpy_ssse3+0x16f0> - 437db1: 80 79 06 00 cmpb $0x0,0x6(%rcx) - 437db5: 0f 84 b5 16 00 00 je 439470 <__strcpy_ssse3+0x1700> - 437dbb: 80 79 07 00 cmpb $0x0,0x7(%rcx) - 437dbf: 0f 84 db 15 00 00 je 4393a0 <__strcpy_ssse3+0x1630> - 437dc5: 80 79 08 00 cmpb $0x0,0x8(%rcx) - 437dc9: 0f 84 b1 16 00 00 je 439480 <__strcpy_ssse3+0x1710> - 437dcf: 80 79 09 00 cmpb $0x0,0x9(%rcx) - 437dd3: 0f 84 b7 16 00 00 je 439490 <__strcpy_ssse3+0x1720> - 437dd9: 80 79 0a 00 cmpb $0x0,0xa(%rcx) - 437ddd: 0f 84 bd 16 00 00 je 4394a0 <__strcpy_ssse3+0x1730> - 437de3: 80 79 0b 00 cmpb $0x0,0xb(%rcx) - 437de7: 0f 84 c3 16 00 00 je 4394b0 <__strcpy_ssse3+0x1740> - 437ded: 80 79 0c 00 cmpb $0x0,0xc(%rcx) - 437df1: 0f 84 c9 16 00 00 je 4394c0 <__strcpy_ssse3+0x1750> - 437df7: 80 79 0d 00 cmpb $0x0,0xd(%rcx) - 437dfb: 0f 84 df 16 00 00 je 4394e0 <__strcpy_ssse3+0x1770> - 437e01: 80 79 0e 00 cmpb $0x0,0xe(%rcx) - 437e05: 0f 84 f5 16 00 00 je 439500 <__strcpy_ssse3+0x1790> - 437e0b: 80 79 0f 00 cmpb $0x0,0xf(%rcx) - 437e0f: 0f 84 db 15 00 00 je 4393f0 <__strcpy_ssse3+0x1680> - 437e15: 48 8d 71 10 lea 0x10(%rcx),%rsi - 437e19: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi - 437e1d: 66 0f ef c0 pxor %xmm0,%xmm0 - 437e21: 4c 8b 09 mov (%rcx),%r9 - 437e24: 4c 89 0a mov %r9,(%rdx) - 437e27: 66 0f 74 06 pcmpeqb (%rsi),%xmm0 - 437e2b: 4c 8b 49 08 mov 0x8(%rcx),%r9 - 437e2f: 4c 89 4a 08 mov %r9,0x8(%rdx) - 437e33: 66 0f d7 c0 pmovmskb %xmm0,%eax - 437e37: 48 29 ce sub %rcx,%rsi - 437e3a: 48 85 c0 test %rax,%rax - 437e3d: 0f 85 0d 15 00 00 jne 439350 <__strcpy_ssse3+0x15e0> - 437e43: 48 89 d0 mov %rdx,%rax - 437e46: 48 8d 52 10 lea 0x10(%rdx),%rdx - 437e4a: 48 83 e2 f0 and $0xfffffffffffffff0,%rdx - 437e4e: 48 29 d0 sub %rdx,%rax - 437e51: 48 29 c1 sub %rax,%rcx - 437e54: 48 89 c8 mov %rcx,%rax - 437e57: 48 83 e0 0f and $0xf,%rax - 437e5b: 48 c7 c6 00 00 00 00 mov $0x0,%rsi - 437e62: 0f 84 8e 00 00 00 je 437ef6 <__strcpy_ssse3+0x186> - 437e68: 48 83 f8 08 cmp $0x8,%rax - 437e6c: 73 41 jae 437eaf <__strcpy_ssse3+0x13f> - 437e6e: 48 83 f8 01 cmp $0x1,%rax - 437e72: 0f 84 f8 01 00 00 je 438070 <__strcpy_ssse3+0x300> - 437e78: 48 83 f8 02 cmp $0x2,%rax - 437e7c: 0f 84 2e 03 00 00 je 4381b0 <__strcpy_ssse3+0x440> - 437e82: 48 83 f8 03 cmp $0x3,%rax - 437e86: 0f 84 64 04 00 00 je 4382f0 <__strcpy_ssse3+0x580> - 437e8c: 48 83 f8 04 cmp $0x4,%rax - 437e90: 0f 84 9a 05 00 00 je 438430 <__strcpy_ssse3+0x6c0> - 437e96: 48 83 f8 05 cmp $0x5,%rax - 437e9a: 0f 84 d0 06 00 00 je 438570 <__strcpy_ssse3+0x800> - 437ea0: 48 83 f8 06 cmp $0x6,%rax - 437ea4: 0f 84 06 08 00 00 je 4386b0 <__strcpy_ssse3+0x940> - 437eaa: e9 51 09 00 00 jmpq 438800 <__strcpy_ssse3+0xa90> - 437eaf: 0f 84 9b 0a 00 00 je 438950 <__strcpy_ssse3+0xbe0> - 437eb5: 48 83 f8 09 cmp $0x9,%rax - 437eb9: 0f 84 d1 0b 00 00 je 438a90 <__strcpy_ssse3+0xd20> - 437ebf: 48 83 f8 0a cmp $0xa,%rax - 437ec3: 0f 84 07 0d 00 00 je 438bd0 <__strcpy_ssse3+0xe60> - 437ec9: 48 83 f8 0b cmp $0xb,%rax - 437ecd: 0f 84 3d 0e 00 00 je 438d10 <__strcpy_ssse3+0xfa0> - 437ed3: 48 83 f8 0c cmp $0xc,%rax - 437ed7: 0f 84 73 0f 00 00 je 438e50 <__strcpy_ssse3+0x10e0> - 437edd: 48 83 f8 0d cmp $0xd,%rax - 437ee1: 0f 84 a9 10 00 00 je 438f90 <__strcpy_ssse3+0x1220> - 437ee7: 48 83 f8 0e cmp $0xe,%rax - 437eeb: 0f 84 df 11 00 00 je 4390d0 <__strcpy_ssse3+0x1360> - 437ef1: e9 1a 13 00 00 jmpq 439210 <__strcpy_ssse3+0x14a0> - 437ef6: 0f 28 09 movaps (%rcx),%xmm1 - 437ef9: 0f 28 51 10 movaps 0x10(%rcx),%xmm2 - 437efd: 0f 29 0a movaps %xmm1,(%rdx) - 437f00: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 437f04: 66 0f d7 c0 pmovmskb %xmm0,%eax - 437f08: 48 8d 76 10 lea 0x10(%rsi),%rsi - 437f0c: 48 85 c0 test %rax,%rax - 437f0f: 0f 85 3b 14 00 00 jne 439350 <__strcpy_ssse3+0x15e0> - 437f15: 0f 28 5c 31 10 movaps 0x10(%rcx,%rsi,1),%xmm3 - 437f1a: 0f 29 14 32 movaps %xmm2,(%rdx,%rsi,1) - 437f1e: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 437f22: 66 0f d7 c0 pmovmskb %xmm0,%eax - 437f26: 48 8d 76 10 lea 0x10(%rsi),%rsi - 437f2a: 48 85 c0 test %rax,%rax - 437f2d: 0f 85 1d 14 00 00 jne 439350 <__strcpy_ssse3+0x15e0> - 437f33: 0f 28 64 31 10 movaps 0x10(%rcx,%rsi,1),%xmm4 - 437f38: 0f 29 1c 32 movaps %xmm3,(%rdx,%rsi,1) - 437f3c: 66 0f 74 c4 pcmpeqb %xmm4,%xmm0 - 437f40: 66 0f d7 c0 pmovmskb %xmm0,%eax - 437f44: 48 8d 76 10 lea 0x10(%rsi),%rsi - 437f48: 48 85 c0 test %rax,%rax - 437f4b: 0f 85 ff 13 00 00 jne 439350 <__strcpy_ssse3+0x15e0> - 437f51: 0f 28 4c 31 10 movaps 0x10(%rcx,%rsi,1),%xmm1 - 437f56: 0f 29 24 32 movaps %xmm4,(%rdx,%rsi,1) - 437f5a: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 437f5e: 66 0f d7 c0 pmovmskb %xmm0,%eax - 437f62: 48 8d 76 10 lea 0x10(%rsi),%rsi - 437f66: 48 85 c0 test %rax,%rax - 437f69: 0f 85 e1 13 00 00 jne 439350 <__strcpy_ssse3+0x15e0> - 437f6f: 0f 28 54 31 10 movaps 0x10(%rcx,%rsi,1),%xmm2 - 437f74: 0f 29 0c 32 movaps %xmm1,(%rdx,%rsi,1) - 437f78: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 437f7c: 66 0f d7 c0 pmovmskb %xmm0,%eax - 437f80: 48 8d 76 10 lea 0x10(%rsi),%rsi - 437f84: 48 85 c0 test %rax,%rax - 437f87: 0f 85 c3 13 00 00 jne 439350 <__strcpy_ssse3+0x15e0> - 437f8d: 0f 28 5c 31 10 movaps 0x10(%rcx,%rsi,1),%xmm3 - 437f92: 0f 29 14 32 movaps %xmm2,(%rdx,%rsi,1) - 437f96: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 437f9a: 66 0f d7 c0 pmovmskb %xmm0,%eax - 437f9e: 48 8d 76 10 lea 0x10(%rsi),%rsi - 437fa2: 48 85 c0 test %rax,%rax - 437fa5: 0f 85 a5 13 00 00 jne 439350 <__strcpy_ssse3+0x15e0> - 437fab: 0f 29 1c 32 movaps %xmm3,(%rdx,%rsi,1) - 437faf: 48 89 c8 mov %rcx,%rax - 437fb2: 48 8d 4c 31 10 lea 0x10(%rcx,%rsi,1),%rcx - 437fb7: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 437fbb: 48 29 c8 sub %rcx,%rax - 437fbe: 48 29 c2 sub %rax,%rdx - 437fc1: 48 c7 c6 c0 ff ff ff mov $0xffffffffffffffc0,%rsi - 437fc8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 437fcf: 00 - 437fd0: 0f 28 11 movaps (%rcx),%xmm2 - 437fd3: 0f 28 e2 movaps %xmm2,%xmm4 - 437fd6: 0f 28 69 10 movaps 0x10(%rcx),%xmm5 - 437fda: 0f 28 59 20 movaps 0x20(%rcx),%xmm3 - 437fde: 0f 28 f3 movaps %xmm3,%xmm6 - 437fe1: 0f 28 79 30 movaps 0x30(%rcx),%xmm7 - 437fe5: 66 0f da d5 pminub %xmm5,%xmm2 - 437fe9: 66 0f da df pminub %xmm7,%xmm3 - 437fed: 66 0f da da pminub %xmm2,%xmm3 - 437ff1: 66 0f 74 d8 pcmpeqb %xmm0,%xmm3 - 437ff5: 66 0f d7 c3 pmovmskb %xmm3,%eax - 437ff9: 48 8d 52 40 lea 0x40(%rdx),%rdx - 437ffd: 48 8d 49 40 lea 0x40(%rcx),%rcx - 438001: 48 85 c0 test %rax,%rax - 438004: 75 12 jne 438018 <__strcpy_ssse3+0x2a8> - 438006: 0f 29 62 c0 movaps %xmm4,-0x40(%rdx) - 43800a: 0f 29 6a d0 movaps %xmm5,-0x30(%rdx) - 43800e: 0f 29 72 e0 movaps %xmm6,-0x20(%rdx) - 438012: 0f 29 7a f0 movaps %xmm7,-0x10(%rdx) - 438016: eb b8 jmp 437fd0 <__strcpy_ssse3+0x260> - 438018: 66 0f 74 c4 pcmpeqb %xmm4,%xmm0 - 43801c: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438020: 48 85 c0 test %rax,%rax - 438023: 0f 85 27 13 00 00 jne 439350 <__strcpy_ssse3+0x15e0> - 438029: 66 0f 74 c5 pcmpeqb %xmm5,%xmm0 - 43802d: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438031: 0f 29 62 c0 movaps %xmm4,-0x40(%rdx) - 438035: 48 85 c0 test %rax,%rax - 438038: 48 8d 76 10 lea 0x10(%rsi),%rsi - 43803c: 0f 85 0e 13 00 00 jne 439350 <__strcpy_ssse3+0x15e0> - 438042: 66 0f 74 c6 pcmpeqb %xmm6,%xmm0 - 438046: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43804a: 0f 29 6a d0 movaps %xmm5,-0x30(%rdx) - 43804e: 48 85 c0 test %rax,%rax - 438051: 48 8d 76 10 lea 0x10(%rsi),%rsi - 438055: 0f 85 f5 12 00 00 jne 439350 <__strcpy_ssse3+0x15e0> - 43805b: 0f 29 72 e0 movaps %xmm6,-0x20(%rdx) - 43805f: 66 0f 74 c7 pcmpeqb %xmm7,%xmm0 - 438063: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438067: 48 8d 76 10 lea 0x10(%rsi),%rsi - 43806b: e9 e0 12 00 00 jmpq 439350 <__strcpy_ssse3+0x15e0> - 438070: 0f 28 49 ff movaps -0x1(%rcx),%xmm1 - 438074: 0f 28 51 0f movaps 0xf(%rcx),%xmm2 - 438078: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43807c: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438080: 0f 28 da movaps %xmm2,%xmm3 - 438083: 48 85 c0 test %rax,%rax - 438086: 0f 85 0e 01 00 00 jne 43819a <__strcpy_ssse3+0x42a> - 43808c: 66 0f 3a 0f d1 01 palignr $0x1,%xmm1,%xmm2 - 438092: 0f 29 12 movaps %xmm2,(%rdx) - 438095: 0f 28 51 1f movaps 0x1f(%rcx),%xmm2 - 438099: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43809d: 48 8d 52 10 lea 0x10(%rdx),%rdx - 4380a1: 66 0f d7 c0 pmovmskb %xmm0,%eax - 4380a5: 48 8d 49 10 lea 0x10(%rcx),%rcx - 4380a9: 0f 28 ca movaps %xmm2,%xmm1 - 4380ac: 48 85 c0 test %rax,%rax - 4380af: 0f 85 e5 00 00 00 jne 43819a <__strcpy_ssse3+0x42a> - 4380b5: 66 0f 3a 0f d3 01 palignr $0x1,%xmm3,%xmm2 - 4380bb: 0f 29 12 movaps %xmm2,(%rdx) - 4380be: 0f 28 51 1f movaps 0x1f(%rcx),%xmm2 - 4380c2: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 4380c6: 48 8d 52 10 lea 0x10(%rdx),%rdx - 4380ca: 66 0f d7 c0 pmovmskb %xmm0,%eax - 4380ce: 48 8d 49 10 lea 0x10(%rcx),%rcx - 4380d2: 0f 28 da movaps %xmm2,%xmm3 - 4380d5: 48 85 c0 test %rax,%rax - 4380d8: 0f 85 bc 00 00 00 jne 43819a <__strcpy_ssse3+0x42a> - 4380de: 66 0f 3a 0f d1 01 palignr $0x1,%xmm1,%xmm2 - 4380e4: 0f 29 12 movaps %xmm2,(%rdx) - 4380e7: 0f 28 51 1f movaps 0x1f(%rcx),%xmm2 - 4380eb: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 4380ef: 48 8d 52 10 lea 0x10(%rdx),%rdx - 4380f3: 66 0f d7 c0 pmovmskb %xmm0,%eax - 4380f7: 48 8d 49 10 lea 0x10(%rcx),%rcx - 4380fb: 48 85 c0 test %rax,%rax - 4380fe: 0f 85 96 00 00 00 jne 43819a <__strcpy_ssse3+0x42a> - 438104: 66 0f 3a 0f d3 01 palignr $0x1,%xmm3,%xmm2 - 43810a: 0f 29 12 movaps %xmm2,(%rdx) - 43810d: 48 8d 49 1f lea 0x1f(%rcx),%rcx - 438111: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438115: 48 89 c8 mov %rcx,%rax - 438118: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 43811c: 48 29 c8 sub %rcx,%rax - 43811f: 48 8d 49 f1 lea -0xf(%rcx),%rcx - 438123: 48 29 c2 sub %rax,%rdx - 438126: 0f 28 49 ff movaps -0x1(%rcx),%xmm1 - 43812a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 438130: 0f 28 51 0f movaps 0xf(%rcx),%xmm2 - 438134: 0f 28 59 1f movaps 0x1f(%rcx),%xmm3 - 438138: 0f 28 f3 movaps %xmm3,%xmm6 - 43813b: 0f 28 61 2f movaps 0x2f(%rcx),%xmm4 - 43813f: 0f 28 fc movaps %xmm4,%xmm7 - 438142: 0f 28 69 3f movaps 0x3f(%rcx),%xmm5 - 438146: 66 0f da f2 pminub %xmm2,%xmm6 - 43814a: 66 0f da fd pminub %xmm5,%xmm7 - 43814e: 66 0f da fe pminub %xmm6,%xmm7 - 438152: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 438156: 66 0f d7 c7 pmovmskb %xmm7,%eax - 43815a: 0f 28 fd movaps %xmm5,%xmm7 - 43815d: 66 0f 3a 0f ec 01 palignr $0x1,%xmm4,%xmm5 - 438163: 48 85 c0 test %rax,%rax - 438166: 66 0f 3a 0f e3 01 palignr $0x1,%xmm3,%xmm4 - 43816c: 0f 85 06 ff ff ff jne 438078 <__strcpy_ssse3+0x308> - 438172: 66 0f 3a 0f da 01 palignr $0x1,%xmm2,%xmm3 - 438178: 48 8d 49 40 lea 0x40(%rcx),%rcx - 43817c: 66 0f 3a 0f d1 01 palignr $0x1,%xmm1,%xmm2 - 438182: 0f 28 cf movaps %xmm7,%xmm1 - 438185: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) - 438189: 0f 29 62 20 movaps %xmm4,0x20(%rdx) - 43818d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) - 438191: 0f 29 12 movaps %xmm2,(%rdx) - 438194: 48 8d 52 40 lea 0x40(%rdx),%rdx - 438198: eb 96 jmp 438130 <__strcpy_ssse3+0x3c0> - 43819a: f3 0f 6f 49 ff movdqu -0x1(%rcx),%xmm1 - 43819f: 48 c7 c6 0f 00 00 00 mov $0xf,%rsi - 4381a6: f3 0f 7f 4a ff movdqu %xmm1,-0x1(%rdx) - 4381ab: e9 a0 11 00 00 jmpq 439350 <__strcpy_ssse3+0x15e0> - 4381b0: 0f 28 49 fe movaps -0x2(%rcx),%xmm1 - 4381b4: 0f 28 51 0e movaps 0xe(%rcx),%xmm2 - 4381b8: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 4381bc: 66 0f d7 c0 pmovmskb %xmm0,%eax - 4381c0: 0f 28 da movaps %xmm2,%xmm3 - 4381c3: 48 85 c0 test %rax,%rax - 4381c6: 0f 85 0e 01 00 00 jne 4382da <__strcpy_ssse3+0x56a> - 4381cc: 66 0f 3a 0f d1 02 palignr $0x2,%xmm1,%xmm2 - 4381d2: 0f 29 12 movaps %xmm2,(%rdx) - 4381d5: 0f 28 51 1e movaps 0x1e(%rcx),%xmm2 - 4381d9: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 4381dd: 48 8d 52 10 lea 0x10(%rdx),%rdx - 4381e1: 66 0f d7 c0 pmovmskb %xmm0,%eax - 4381e5: 48 8d 49 10 lea 0x10(%rcx),%rcx - 4381e9: 0f 28 ca movaps %xmm2,%xmm1 - 4381ec: 48 85 c0 test %rax,%rax - 4381ef: 0f 85 e5 00 00 00 jne 4382da <__strcpy_ssse3+0x56a> - 4381f5: 66 0f 3a 0f d3 02 palignr $0x2,%xmm3,%xmm2 - 4381fb: 0f 29 12 movaps %xmm2,(%rdx) - 4381fe: 0f 28 51 1e movaps 0x1e(%rcx),%xmm2 - 438202: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 438206: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43820a: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43820e: 48 8d 49 10 lea 0x10(%rcx),%rcx - 438212: 0f 28 da movaps %xmm2,%xmm3 - 438215: 48 85 c0 test %rax,%rax - 438218: 0f 85 bc 00 00 00 jne 4382da <__strcpy_ssse3+0x56a> - 43821e: 66 0f 3a 0f d1 02 palignr $0x2,%xmm1,%xmm2 - 438224: 0f 29 12 movaps %xmm2,(%rdx) - 438227: 0f 28 51 1e movaps 0x1e(%rcx),%xmm2 - 43822b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43822f: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438233: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438237: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43823b: 48 85 c0 test %rax,%rax - 43823e: 0f 85 96 00 00 00 jne 4382da <__strcpy_ssse3+0x56a> - 438244: 66 0f 3a 0f d3 02 palignr $0x2,%xmm3,%xmm2 - 43824a: 0f 29 12 movaps %xmm2,(%rdx) - 43824d: 48 8d 49 1e lea 0x1e(%rcx),%rcx - 438251: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438255: 48 89 c8 mov %rcx,%rax - 438258: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 43825c: 48 29 c8 sub %rcx,%rax - 43825f: 48 8d 49 f2 lea -0xe(%rcx),%rcx - 438263: 48 29 c2 sub %rax,%rdx - 438266: 0f 28 49 fe movaps -0x2(%rcx),%xmm1 - 43826a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 438270: 0f 28 51 0e movaps 0xe(%rcx),%xmm2 - 438274: 0f 28 59 1e movaps 0x1e(%rcx),%xmm3 - 438278: 0f 28 f3 movaps %xmm3,%xmm6 - 43827b: 0f 28 61 2e movaps 0x2e(%rcx),%xmm4 - 43827f: 0f 28 fc movaps %xmm4,%xmm7 - 438282: 0f 28 69 3e movaps 0x3e(%rcx),%xmm5 - 438286: 66 0f da f2 pminub %xmm2,%xmm6 - 43828a: 66 0f da fd pminub %xmm5,%xmm7 - 43828e: 66 0f da fe pminub %xmm6,%xmm7 - 438292: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 438296: 66 0f d7 c7 pmovmskb %xmm7,%eax - 43829a: 0f 28 fd movaps %xmm5,%xmm7 - 43829d: 66 0f 3a 0f ec 02 palignr $0x2,%xmm4,%xmm5 - 4382a3: 48 85 c0 test %rax,%rax - 4382a6: 66 0f 3a 0f e3 02 palignr $0x2,%xmm3,%xmm4 - 4382ac: 0f 85 06 ff ff ff jne 4381b8 <__strcpy_ssse3+0x448> - 4382b2: 66 0f 3a 0f da 02 palignr $0x2,%xmm2,%xmm3 - 4382b8: 48 8d 49 40 lea 0x40(%rcx),%rcx - 4382bc: 66 0f 3a 0f d1 02 palignr $0x2,%xmm1,%xmm2 - 4382c2: 0f 28 cf movaps %xmm7,%xmm1 - 4382c5: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) - 4382c9: 0f 29 62 20 movaps %xmm4,0x20(%rdx) - 4382cd: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) - 4382d1: 0f 29 12 movaps %xmm2,(%rdx) - 4382d4: 48 8d 52 40 lea 0x40(%rdx),%rdx - 4382d8: eb 96 jmp 438270 <__strcpy_ssse3+0x500> - 4382da: f3 0f 6f 49 fe movdqu -0x2(%rcx),%xmm1 - 4382df: 48 c7 c6 0e 00 00 00 mov $0xe,%rsi - 4382e6: f3 0f 7f 4a fe movdqu %xmm1,-0x2(%rdx) - 4382eb: e9 60 10 00 00 jmpq 439350 <__strcpy_ssse3+0x15e0> - 4382f0: 0f 28 49 fd movaps -0x3(%rcx),%xmm1 - 4382f4: 0f 28 51 0d movaps 0xd(%rcx),%xmm2 - 4382f8: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 4382fc: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438300: 0f 28 da movaps %xmm2,%xmm3 - 438303: 48 85 c0 test %rax,%rax - 438306: 0f 85 0e 01 00 00 jne 43841a <__strcpy_ssse3+0x6aa> - 43830c: 66 0f 3a 0f d1 03 palignr $0x3,%xmm1,%xmm2 - 438312: 0f 29 12 movaps %xmm2,(%rdx) - 438315: 0f 28 51 1d movaps 0x1d(%rcx),%xmm2 - 438319: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43831d: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438321: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438325: 48 8d 49 10 lea 0x10(%rcx),%rcx - 438329: 0f 28 ca movaps %xmm2,%xmm1 - 43832c: 48 85 c0 test %rax,%rax - 43832f: 0f 85 e5 00 00 00 jne 43841a <__strcpy_ssse3+0x6aa> - 438335: 66 0f 3a 0f d3 03 palignr $0x3,%xmm3,%xmm2 - 43833b: 0f 29 12 movaps %xmm2,(%rdx) - 43833e: 0f 28 51 1d movaps 0x1d(%rcx),%xmm2 - 438342: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 438346: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43834a: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43834e: 48 8d 49 10 lea 0x10(%rcx),%rcx - 438352: 0f 28 da movaps %xmm2,%xmm3 - 438355: 48 85 c0 test %rax,%rax - 438358: 0f 85 bc 00 00 00 jne 43841a <__strcpy_ssse3+0x6aa> - 43835e: 66 0f 3a 0f d1 03 palignr $0x3,%xmm1,%xmm2 - 438364: 0f 29 12 movaps %xmm2,(%rdx) - 438367: 0f 28 51 1d movaps 0x1d(%rcx),%xmm2 - 43836b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43836f: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438373: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438377: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43837b: 48 85 c0 test %rax,%rax - 43837e: 0f 85 96 00 00 00 jne 43841a <__strcpy_ssse3+0x6aa> - 438384: 66 0f 3a 0f d3 03 palignr $0x3,%xmm3,%xmm2 - 43838a: 0f 29 12 movaps %xmm2,(%rdx) - 43838d: 48 8d 49 1d lea 0x1d(%rcx),%rcx - 438391: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438395: 48 89 c8 mov %rcx,%rax - 438398: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 43839c: 48 29 c8 sub %rcx,%rax - 43839f: 48 8d 49 f3 lea -0xd(%rcx),%rcx - 4383a3: 48 29 c2 sub %rax,%rdx - 4383a6: 0f 28 49 fd movaps -0x3(%rcx),%xmm1 - 4383aa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4383b0: 0f 28 51 0d movaps 0xd(%rcx),%xmm2 - 4383b4: 0f 28 59 1d movaps 0x1d(%rcx),%xmm3 - 4383b8: 0f 28 f3 movaps %xmm3,%xmm6 - 4383bb: 0f 28 61 2d movaps 0x2d(%rcx),%xmm4 - 4383bf: 0f 28 fc movaps %xmm4,%xmm7 - 4383c2: 0f 28 69 3d movaps 0x3d(%rcx),%xmm5 - 4383c6: 66 0f da f2 pminub %xmm2,%xmm6 - 4383ca: 66 0f da fd pminub %xmm5,%xmm7 - 4383ce: 66 0f da fe pminub %xmm6,%xmm7 - 4383d2: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 4383d6: 66 0f d7 c7 pmovmskb %xmm7,%eax - 4383da: 0f 28 fd movaps %xmm5,%xmm7 - 4383dd: 66 0f 3a 0f ec 03 palignr $0x3,%xmm4,%xmm5 - 4383e3: 48 85 c0 test %rax,%rax - 4383e6: 66 0f 3a 0f e3 03 palignr $0x3,%xmm3,%xmm4 - 4383ec: 0f 85 06 ff ff ff jne 4382f8 <__strcpy_ssse3+0x588> - 4383f2: 66 0f 3a 0f da 03 palignr $0x3,%xmm2,%xmm3 - 4383f8: 48 8d 49 40 lea 0x40(%rcx),%rcx - 4383fc: 66 0f 3a 0f d1 03 palignr $0x3,%xmm1,%xmm2 - 438402: 0f 28 cf movaps %xmm7,%xmm1 - 438405: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) - 438409: 0f 29 62 20 movaps %xmm4,0x20(%rdx) - 43840d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) - 438411: 0f 29 12 movaps %xmm2,(%rdx) - 438414: 48 8d 52 40 lea 0x40(%rdx),%rdx - 438418: eb 96 jmp 4383b0 <__strcpy_ssse3+0x640> - 43841a: f3 0f 6f 49 fd movdqu -0x3(%rcx),%xmm1 - 43841f: 48 c7 c6 0d 00 00 00 mov $0xd,%rsi - 438426: f3 0f 7f 4a fd movdqu %xmm1,-0x3(%rdx) - 43842b: e9 20 0f 00 00 jmpq 439350 <__strcpy_ssse3+0x15e0> - 438430: 0f 28 49 fc movaps -0x4(%rcx),%xmm1 - 438434: 0f 28 51 0c movaps 0xc(%rcx),%xmm2 - 438438: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43843c: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438440: 0f 28 da movaps %xmm2,%xmm3 - 438443: 48 85 c0 test %rax,%rax - 438446: 0f 85 0e 01 00 00 jne 43855a <__strcpy_ssse3+0x7ea> - 43844c: 66 0f 3a 0f d1 04 palignr $0x4,%xmm1,%xmm2 - 438452: 0f 29 12 movaps %xmm2,(%rdx) - 438455: 0f 28 51 1c movaps 0x1c(%rcx),%xmm2 - 438459: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43845d: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438461: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438465: 48 8d 49 10 lea 0x10(%rcx),%rcx - 438469: 0f 28 ca movaps %xmm2,%xmm1 - 43846c: 48 85 c0 test %rax,%rax - 43846f: 0f 85 e5 00 00 00 jne 43855a <__strcpy_ssse3+0x7ea> - 438475: 66 0f 3a 0f d3 04 palignr $0x4,%xmm3,%xmm2 - 43847b: 0f 29 12 movaps %xmm2,(%rdx) - 43847e: 0f 28 51 1c movaps 0x1c(%rcx),%xmm2 - 438482: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 438486: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43848a: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43848e: 48 8d 49 10 lea 0x10(%rcx),%rcx - 438492: 0f 28 da movaps %xmm2,%xmm3 - 438495: 48 85 c0 test %rax,%rax - 438498: 0f 85 bc 00 00 00 jne 43855a <__strcpy_ssse3+0x7ea> - 43849e: 66 0f 3a 0f d1 04 palignr $0x4,%xmm1,%xmm2 - 4384a4: 0f 29 12 movaps %xmm2,(%rdx) - 4384a7: 0f 28 51 1c movaps 0x1c(%rcx),%xmm2 - 4384ab: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 4384af: 48 8d 52 10 lea 0x10(%rdx),%rdx - 4384b3: 66 0f d7 c0 pmovmskb %xmm0,%eax - 4384b7: 48 8d 49 10 lea 0x10(%rcx),%rcx - 4384bb: 48 85 c0 test %rax,%rax - 4384be: 0f 85 96 00 00 00 jne 43855a <__strcpy_ssse3+0x7ea> - 4384c4: 66 0f 3a 0f d3 04 palignr $0x4,%xmm3,%xmm2 - 4384ca: 0f 29 12 movaps %xmm2,(%rdx) - 4384cd: 48 8d 49 1c lea 0x1c(%rcx),%rcx - 4384d1: 48 8d 52 10 lea 0x10(%rdx),%rdx - 4384d5: 48 89 c8 mov %rcx,%rax - 4384d8: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 4384dc: 48 29 c8 sub %rcx,%rax - 4384df: 48 8d 49 f4 lea -0xc(%rcx),%rcx - 4384e3: 48 29 c2 sub %rax,%rdx - 4384e6: 0f 28 49 fc movaps -0x4(%rcx),%xmm1 - 4384ea: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4384f0: 0f 28 51 0c movaps 0xc(%rcx),%xmm2 - 4384f4: 0f 28 59 1c movaps 0x1c(%rcx),%xmm3 - 4384f8: 0f 28 f3 movaps %xmm3,%xmm6 - 4384fb: 0f 28 61 2c movaps 0x2c(%rcx),%xmm4 - 4384ff: 0f 28 fc movaps %xmm4,%xmm7 - 438502: 0f 28 69 3c movaps 0x3c(%rcx),%xmm5 - 438506: 66 0f da f2 pminub %xmm2,%xmm6 - 43850a: 66 0f da fd pminub %xmm5,%xmm7 - 43850e: 66 0f da fe pminub %xmm6,%xmm7 - 438512: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 438516: 66 0f d7 c7 pmovmskb %xmm7,%eax - 43851a: 0f 28 fd movaps %xmm5,%xmm7 - 43851d: 66 0f 3a 0f ec 04 palignr $0x4,%xmm4,%xmm5 - 438523: 48 85 c0 test %rax,%rax - 438526: 66 0f 3a 0f e3 04 palignr $0x4,%xmm3,%xmm4 - 43852c: 0f 85 06 ff ff ff jne 438438 <__strcpy_ssse3+0x6c8> - 438532: 66 0f 3a 0f da 04 palignr $0x4,%xmm2,%xmm3 - 438538: 48 8d 49 40 lea 0x40(%rcx),%rcx - 43853c: 66 0f 3a 0f d1 04 palignr $0x4,%xmm1,%xmm2 - 438542: 0f 28 cf movaps %xmm7,%xmm1 - 438545: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) - 438549: 0f 29 62 20 movaps %xmm4,0x20(%rdx) - 43854d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) - 438551: 0f 29 12 movaps %xmm2,(%rdx) - 438554: 48 8d 52 40 lea 0x40(%rdx),%rdx - 438558: eb 96 jmp 4384f0 <__strcpy_ssse3+0x780> - 43855a: f3 0f 6f 49 fc movdqu -0x4(%rcx),%xmm1 - 43855f: 48 c7 c6 0c 00 00 00 mov $0xc,%rsi - 438566: f3 0f 7f 4a fc movdqu %xmm1,-0x4(%rdx) - 43856b: e9 e0 0d 00 00 jmpq 439350 <__strcpy_ssse3+0x15e0> - 438570: 0f 28 49 fb movaps -0x5(%rcx),%xmm1 - 438574: 0f 28 51 0b movaps 0xb(%rcx),%xmm2 - 438578: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43857c: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438580: 0f 28 da movaps %xmm2,%xmm3 - 438583: 48 85 c0 test %rax,%rax - 438586: 0f 85 0e 01 00 00 jne 43869a <__strcpy_ssse3+0x92a> - 43858c: 66 0f 3a 0f d1 05 palignr $0x5,%xmm1,%xmm2 - 438592: 0f 29 12 movaps %xmm2,(%rdx) - 438595: 0f 28 51 1b movaps 0x1b(%rcx),%xmm2 - 438599: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43859d: 48 8d 52 10 lea 0x10(%rdx),%rdx - 4385a1: 66 0f d7 c0 pmovmskb %xmm0,%eax - 4385a5: 48 8d 49 10 lea 0x10(%rcx),%rcx - 4385a9: 0f 28 ca movaps %xmm2,%xmm1 - 4385ac: 48 85 c0 test %rax,%rax - 4385af: 0f 85 e5 00 00 00 jne 43869a <__strcpy_ssse3+0x92a> - 4385b5: 66 0f 3a 0f d3 05 palignr $0x5,%xmm3,%xmm2 - 4385bb: 0f 29 12 movaps %xmm2,(%rdx) - 4385be: 0f 28 51 1b movaps 0x1b(%rcx),%xmm2 - 4385c2: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 4385c6: 48 8d 52 10 lea 0x10(%rdx),%rdx - 4385ca: 66 0f d7 c0 pmovmskb %xmm0,%eax - 4385ce: 48 8d 49 10 lea 0x10(%rcx),%rcx - 4385d2: 0f 28 da movaps %xmm2,%xmm3 - 4385d5: 48 85 c0 test %rax,%rax - 4385d8: 0f 85 bc 00 00 00 jne 43869a <__strcpy_ssse3+0x92a> - 4385de: 66 0f 3a 0f d1 05 palignr $0x5,%xmm1,%xmm2 - 4385e4: 0f 29 12 movaps %xmm2,(%rdx) - 4385e7: 0f 28 51 1b movaps 0x1b(%rcx),%xmm2 - 4385eb: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 4385ef: 48 8d 52 10 lea 0x10(%rdx),%rdx - 4385f3: 66 0f d7 c0 pmovmskb %xmm0,%eax - 4385f7: 48 8d 49 10 lea 0x10(%rcx),%rcx - 4385fb: 48 85 c0 test %rax,%rax - 4385fe: 0f 85 96 00 00 00 jne 43869a <__strcpy_ssse3+0x92a> - 438604: 66 0f 3a 0f d3 05 palignr $0x5,%xmm3,%xmm2 - 43860a: 0f 29 12 movaps %xmm2,(%rdx) - 43860d: 48 8d 49 1b lea 0x1b(%rcx),%rcx - 438611: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438615: 48 89 c8 mov %rcx,%rax - 438618: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 43861c: 48 29 c8 sub %rcx,%rax - 43861f: 48 8d 49 f5 lea -0xb(%rcx),%rcx - 438623: 48 29 c2 sub %rax,%rdx - 438626: 0f 28 49 fb movaps -0x5(%rcx),%xmm1 - 43862a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 438630: 0f 28 51 0b movaps 0xb(%rcx),%xmm2 - 438634: 0f 28 59 1b movaps 0x1b(%rcx),%xmm3 - 438638: 0f 28 f3 movaps %xmm3,%xmm6 - 43863b: 0f 28 61 2b movaps 0x2b(%rcx),%xmm4 - 43863f: 0f 28 fc movaps %xmm4,%xmm7 - 438642: 0f 28 69 3b movaps 0x3b(%rcx),%xmm5 - 438646: 66 0f da f2 pminub %xmm2,%xmm6 - 43864a: 66 0f da fd pminub %xmm5,%xmm7 - 43864e: 66 0f da fe pminub %xmm6,%xmm7 - 438652: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 438656: 66 0f d7 c7 pmovmskb %xmm7,%eax - 43865a: 0f 28 fd movaps %xmm5,%xmm7 - 43865d: 66 0f 3a 0f ec 05 palignr $0x5,%xmm4,%xmm5 - 438663: 48 85 c0 test %rax,%rax - 438666: 66 0f 3a 0f e3 05 palignr $0x5,%xmm3,%xmm4 - 43866c: 0f 85 06 ff ff ff jne 438578 <__strcpy_ssse3+0x808> - 438672: 66 0f 3a 0f da 05 palignr $0x5,%xmm2,%xmm3 - 438678: 48 8d 49 40 lea 0x40(%rcx),%rcx - 43867c: 66 0f 3a 0f d1 05 palignr $0x5,%xmm1,%xmm2 - 438682: 0f 28 cf movaps %xmm7,%xmm1 - 438685: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) - 438689: 0f 29 62 20 movaps %xmm4,0x20(%rdx) - 43868d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) - 438691: 0f 29 12 movaps %xmm2,(%rdx) - 438694: 48 8d 52 40 lea 0x40(%rdx),%rdx - 438698: eb 96 jmp 438630 <__strcpy_ssse3+0x8c0> - 43869a: f3 0f 6f 49 fb movdqu -0x5(%rcx),%xmm1 - 43869f: 48 c7 c6 0b 00 00 00 mov $0xb,%rsi - 4386a6: f3 0f 7f 4a fb movdqu %xmm1,-0x5(%rdx) - 4386ab: e9 a0 0c 00 00 jmpq 439350 <__strcpy_ssse3+0x15e0> - 4386b0: 0f 28 49 fa movaps -0x6(%rcx),%xmm1 - 4386b4: 0f 28 51 0a movaps 0xa(%rcx),%xmm2 - 4386b8: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 4386bc: 66 0f d7 c0 pmovmskb %xmm0,%eax - 4386c0: 0f 28 da movaps %xmm2,%xmm3 - 4386c3: 48 85 c0 test %rax,%rax - 4386c6: 0f 85 0e 01 00 00 jne 4387da <__strcpy_ssse3+0xa6a> - 4386cc: 66 0f 3a 0f d1 06 palignr $0x6,%xmm1,%xmm2 - 4386d2: 0f 29 12 movaps %xmm2,(%rdx) - 4386d5: 0f 28 51 1a movaps 0x1a(%rcx),%xmm2 - 4386d9: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 4386dd: 48 8d 52 10 lea 0x10(%rdx),%rdx - 4386e1: 66 0f d7 c0 pmovmskb %xmm0,%eax - 4386e5: 48 8d 49 10 lea 0x10(%rcx),%rcx - 4386e9: 0f 28 ca movaps %xmm2,%xmm1 - 4386ec: 48 85 c0 test %rax,%rax - 4386ef: 0f 85 e5 00 00 00 jne 4387da <__strcpy_ssse3+0xa6a> - 4386f5: 66 0f 3a 0f d3 06 palignr $0x6,%xmm3,%xmm2 - 4386fb: 0f 29 12 movaps %xmm2,(%rdx) - 4386fe: 0f 28 51 1a movaps 0x1a(%rcx),%xmm2 - 438702: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 438706: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43870a: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43870e: 48 8d 49 10 lea 0x10(%rcx),%rcx - 438712: 0f 28 da movaps %xmm2,%xmm3 - 438715: 48 85 c0 test %rax,%rax - 438718: 0f 85 bc 00 00 00 jne 4387da <__strcpy_ssse3+0xa6a> - 43871e: 66 0f 3a 0f d1 06 palignr $0x6,%xmm1,%xmm2 - 438724: 0f 29 12 movaps %xmm2,(%rdx) - 438727: 0f 28 51 1a movaps 0x1a(%rcx),%xmm2 - 43872b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43872f: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438733: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438737: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43873b: 48 85 c0 test %rax,%rax - 43873e: 0f 85 96 00 00 00 jne 4387da <__strcpy_ssse3+0xa6a> - 438744: 66 0f 3a 0f d3 06 palignr $0x6,%xmm3,%xmm2 - 43874a: 0f 29 12 movaps %xmm2,(%rdx) - 43874d: 48 8d 49 1a lea 0x1a(%rcx),%rcx - 438751: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438755: 48 89 c8 mov %rcx,%rax - 438758: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 43875c: 48 29 c8 sub %rcx,%rax - 43875f: 48 8d 49 f6 lea -0xa(%rcx),%rcx - 438763: 48 29 c2 sub %rax,%rdx - 438766: 0f 28 49 fa movaps -0x6(%rcx),%xmm1 - 43876a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 438770: 0f 28 51 0a movaps 0xa(%rcx),%xmm2 - 438774: 0f 28 59 1a movaps 0x1a(%rcx),%xmm3 - 438778: 0f 28 f3 movaps %xmm3,%xmm6 - 43877b: 0f 28 61 2a movaps 0x2a(%rcx),%xmm4 - 43877f: 0f 28 fc movaps %xmm4,%xmm7 - 438782: 0f 28 69 3a movaps 0x3a(%rcx),%xmm5 - 438786: 66 0f da f2 pminub %xmm2,%xmm6 - 43878a: 66 0f da fd pminub %xmm5,%xmm7 - 43878e: 66 0f da fe pminub %xmm6,%xmm7 - 438792: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 438796: 66 0f d7 c7 pmovmskb %xmm7,%eax - 43879a: 0f 28 fd movaps %xmm5,%xmm7 - 43879d: 66 0f 3a 0f ec 06 palignr $0x6,%xmm4,%xmm5 - 4387a3: 48 85 c0 test %rax,%rax - 4387a6: 66 0f 3a 0f e3 06 palignr $0x6,%xmm3,%xmm4 - 4387ac: 0f 85 06 ff ff ff jne 4386b8 <__strcpy_ssse3+0x948> - 4387b2: 66 0f 3a 0f da 06 palignr $0x6,%xmm2,%xmm3 - 4387b8: 48 8d 49 40 lea 0x40(%rcx),%rcx - 4387bc: 66 0f 3a 0f d1 06 palignr $0x6,%xmm1,%xmm2 - 4387c2: 0f 28 cf movaps %xmm7,%xmm1 - 4387c5: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) - 4387c9: 0f 29 62 20 movaps %xmm4,0x20(%rdx) - 4387cd: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) - 4387d1: 0f 29 12 movaps %xmm2,(%rdx) - 4387d4: 48 8d 52 40 lea 0x40(%rdx),%rdx - 4387d8: eb 96 jmp 438770 <__strcpy_ssse3+0xa00> - 4387da: 4c 8b 09 mov (%rcx),%r9 - 4387dd: 8b 71 06 mov 0x6(%rcx),%esi - 4387e0: 4c 89 0a mov %r9,(%rdx) - 4387e3: 89 72 06 mov %esi,0x6(%rdx) - 4387e6: 48 c7 c6 0a 00 00 00 mov $0xa,%rsi - 4387ed: e9 5e 0b 00 00 jmpq 439350 <__strcpy_ssse3+0x15e0> - 4387f2: 0f 1f 40 00 nopl 0x0(%rax) - 4387f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4387fd: 00 00 00 - 438800: 0f 28 49 f9 movaps -0x7(%rcx),%xmm1 - 438804: 0f 28 51 09 movaps 0x9(%rcx),%xmm2 - 438808: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43880c: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438810: 0f 28 da movaps %xmm2,%xmm3 - 438813: 48 85 c0 test %rax,%rax - 438816: 0f 85 0e 01 00 00 jne 43892a <__strcpy_ssse3+0xbba> - 43881c: 66 0f 3a 0f d1 07 palignr $0x7,%xmm1,%xmm2 - 438822: 0f 29 12 movaps %xmm2,(%rdx) - 438825: 0f 28 51 19 movaps 0x19(%rcx),%xmm2 - 438829: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43882d: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438831: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438835: 48 8d 49 10 lea 0x10(%rcx),%rcx - 438839: 0f 28 ca movaps %xmm2,%xmm1 - 43883c: 48 85 c0 test %rax,%rax - 43883f: 0f 85 e5 00 00 00 jne 43892a <__strcpy_ssse3+0xbba> - 438845: 66 0f 3a 0f d3 07 palignr $0x7,%xmm3,%xmm2 - 43884b: 0f 29 12 movaps %xmm2,(%rdx) - 43884e: 0f 28 51 19 movaps 0x19(%rcx),%xmm2 - 438852: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 438856: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43885a: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43885e: 48 8d 49 10 lea 0x10(%rcx),%rcx - 438862: 0f 28 da movaps %xmm2,%xmm3 - 438865: 48 85 c0 test %rax,%rax - 438868: 0f 85 bc 00 00 00 jne 43892a <__strcpy_ssse3+0xbba> - 43886e: 66 0f 3a 0f d1 07 palignr $0x7,%xmm1,%xmm2 - 438874: 0f 29 12 movaps %xmm2,(%rdx) - 438877: 0f 28 51 19 movaps 0x19(%rcx),%xmm2 - 43887b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43887f: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438883: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438887: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43888b: 48 85 c0 test %rax,%rax - 43888e: 0f 85 96 00 00 00 jne 43892a <__strcpy_ssse3+0xbba> - 438894: 66 0f 3a 0f d3 07 palignr $0x7,%xmm3,%xmm2 - 43889a: 0f 29 12 movaps %xmm2,(%rdx) - 43889d: 48 8d 49 19 lea 0x19(%rcx),%rcx - 4388a1: 48 8d 52 10 lea 0x10(%rdx),%rdx - 4388a5: 48 89 c8 mov %rcx,%rax - 4388a8: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 4388ac: 48 29 c8 sub %rcx,%rax - 4388af: 48 8d 49 f7 lea -0x9(%rcx),%rcx - 4388b3: 48 29 c2 sub %rax,%rdx - 4388b6: 0f 28 49 f9 movaps -0x7(%rcx),%xmm1 - 4388ba: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4388c0: 0f 28 51 09 movaps 0x9(%rcx),%xmm2 - 4388c4: 0f 28 59 19 movaps 0x19(%rcx),%xmm3 - 4388c8: 0f 28 f3 movaps %xmm3,%xmm6 - 4388cb: 0f 28 61 29 movaps 0x29(%rcx),%xmm4 - 4388cf: 0f 28 fc movaps %xmm4,%xmm7 - 4388d2: 0f 28 69 39 movaps 0x39(%rcx),%xmm5 - 4388d6: 66 0f da f2 pminub %xmm2,%xmm6 - 4388da: 66 0f da fd pminub %xmm5,%xmm7 - 4388de: 66 0f da fe pminub %xmm6,%xmm7 - 4388e2: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 4388e6: 66 0f d7 c7 pmovmskb %xmm7,%eax - 4388ea: 0f 28 fd movaps %xmm5,%xmm7 - 4388ed: 66 0f 3a 0f ec 07 palignr $0x7,%xmm4,%xmm5 - 4388f3: 48 85 c0 test %rax,%rax - 4388f6: 66 0f 3a 0f e3 07 palignr $0x7,%xmm3,%xmm4 - 4388fc: 0f 85 06 ff ff ff jne 438808 <__strcpy_ssse3+0xa98> - 438902: 66 0f 3a 0f da 07 palignr $0x7,%xmm2,%xmm3 - 438908: 48 8d 49 40 lea 0x40(%rcx),%rcx - 43890c: 66 0f 3a 0f d1 07 palignr $0x7,%xmm1,%xmm2 - 438912: 0f 28 cf movaps %xmm7,%xmm1 - 438915: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) - 438919: 0f 29 62 20 movaps %xmm4,0x20(%rdx) - 43891d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) - 438921: 0f 29 12 movaps %xmm2,(%rdx) - 438924: 48 8d 52 40 lea 0x40(%rdx),%rdx - 438928: eb 96 jmp 4388c0 <__strcpy_ssse3+0xb50> - 43892a: 4c 8b 09 mov (%rcx),%r9 - 43892d: 8b 71 05 mov 0x5(%rcx),%esi - 438930: 4c 89 0a mov %r9,(%rdx) - 438933: 89 72 05 mov %esi,0x5(%rdx) - 438936: 48 c7 c6 09 00 00 00 mov $0x9,%rsi - 43893d: e9 0e 0a 00 00 jmpq 439350 <__strcpy_ssse3+0x15e0> - 438942: 0f 1f 40 00 nopl 0x0(%rax) - 438946: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43894d: 00 00 00 - 438950: 0f 28 49 f8 movaps -0x8(%rcx),%xmm1 - 438954: 0f 28 51 08 movaps 0x8(%rcx),%xmm2 - 438958: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43895c: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438960: 0f 28 da movaps %xmm2,%xmm3 - 438963: 48 85 c0 test %rax,%rax - 438966: 0f 85 0e 01 00 00 jne 438a7a <__strcpy_ssse3+0xd0a> - 43896c: 66 0f 3a 0f d1 08 palignr $0x8,%xmm1,%xmm2 - 438972: 0f 29 12 movaps %xmm2,(%rdx) - 438975: 0f 28 51 18 movaps 0x18(%rcx),%xmm2 - 438979: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43897d: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438981: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438985: 48 8d 49 10 lea 0x10(%rcx),%rcx - 438989: 0f 28 ca movaps %xmm2,%xmm1 - 43898c: 48 85 c0 test %rax,%rax - 43898f: 0f 85 e5 00 00 00 jne 438a7a <__strcpy_ssse3+0xd0a> - 438995: 66 0f 3a 0f d3 08 palignr $0x8,%xmm3,%xmm2 - 43899b: 0f 29 12 movaps %xmm2,(%rdx) - 43899e: 0f 28 51 18 movaps 0x18(%rcx),%xmm2 - 4389a2: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 4389a6: 48 8d 52 10 lea 0x10(%rdx),%rdx - 4389aa: 66 0f d7 c0 pmovmskb %xmm0,%eax - 4389ae: 48 8d 49 10 lea 0x10(%rcx),%rcx - 4389b2: 0f 28 da movaps %xmm2,%xmm3 - 4389b5: 48 85 c0 test %rax,%rax - 4389b8: 0f 85 bc 00 00 00 jne 438a7a <__strcpy_ssse3+0xd0a> - 4389be: 66 0f 3a 0f d1 08 palignr $0x8,%xmm1,%xmm2 - 4389c4: 0f 29 12 movaps %xmm2,(%rdx) - 4389c7: 0f 28 51 18 movaps 0x18(%rcx),%xmm2 - 4389cb: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 4389cf: 48 8d 52 10 lea 0x10(%rdx),%rdx - 4389d3: 66 0f d7 c0 pmovmskb %xmm0,%eax - 4389d7: 48 8d 49 10 lea 0x10(%rcx),%rcx - 4389db: 48 85 c0 test %rax,%rax - 4389de: 0f 85 96 00 00 00 jne 438a7a <__strcpy_ssse3+0xd0a> - 4389e4: 66 0f 3a 0f d3 08 palignr $0x8,%xmm3,%xmm2 - 4389ea: 0f 29 12 movaps %xmm2,(%rdx) - 4389ed: 48 8d 49 18 lea 0x18(%rcx),%rcx - 4389f1: 48 8d 52 10 lea 0x10(%rdx),%rdx - 4389f5: 48 89 c8 mov %rcx,%rax - 4389f8: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 4389fc: 48 29 c8 sub %rcx,%rax - 4389ff: 48 8d 49 f8 lea -0x8(%rcx),%rcx - 438a03: 48 29 c2 sub %rax,%rdx - 438a06: 0f 28 49 f8 movaps -0x8(%rcx),%xmm1 - 438a0a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 438a10: 0f 28 51 08 movaps 0x8(%rcx),%xmm2 - 438a14: 0f 28 59 18 movaps 0x18(%rcx),%xmm3 - 438a18: 0f 28 f3 movaps %xmm3,%xmm6 - 438a1b: 0f 28 61 28 movaps 0x28(%rcx),%xmm4 - 438a1f: 0f 28 fc movaps %xmm4,%xmm7 - 438a22: 0f 28 69 38 movaps 0x38(%rcx),%xmm5 - 438a26: 66 0f da f2 pminub %xmm2,%xmm6 - 438a2a: 66 0f da fd pminub %xmm5,%xmm7 - 438a2e: 66 0f da fe pminub %xmm6,%xmm7 - 438a32: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 438a36: 66 0f d7 c7 pmovmskb %xmm7,%eax - 438a3a: 0f 28 fd movaps %xmm5,%xmm7 - 438a3d: 66 0f 3a 0f ec 08 palignr $0x8,%xmm4,%xmm5 - 438a43: 48 85 c0 test %rax,%rax - 438a46: 66 0f 3a 0f e3 08 palignr $0x8,%xmm3,%xmm4 - 438a4c: 0f 85 06 ff ff ff jne 438958 <__strcpy_ssse3+0xbe8> - 438a52: 66 0f 3a 0f da 08 palignr $0x8,%xmm2,%xmm3 - 438a58: 48 8d 49 40 lea 0x40(%rcx),%rcx - 438a5c: 66 0f 3a 0f d1 08 palignr $0x8,%xmm1,%xmm2 - 438a62: 0f 28 cf movaps %xmm7,%xmm1 - 438a65: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) - 438a69: 0f 29 62 20 movaps %xmm4,0x20(%rdx) - 438a6d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) - 438a71: 0f 29 12 movaps %xmm2,(%rdx) - 438a74: 48 8d 52 40 lea 0x40(%rdx),%rdx - 438a78: eb 96 jmp 438a10 <__strcpy_ssse3+0xca0> - 438a7a: 4c 8b 09 mov (%rcx),%r9 - 438a7d: 48 c7 c6 08 00 00 00 mov $0x8,%rsi - 438a84: 4c 89 0a mov %r9,(%rdx) - 438a87: e9 c4 08 00 00 jmpq 439350 <__strcpy_ssse3+0x15e0> - 438a8c: 0f 1f 40 00 nopl 0x0(%rax) - 438a90: 0f 28 49 f7 movaps -0x9(%rcx),%xmm1 - 438a94: 0f 28 51 07 movaps 0x7(%rcx),%xmm2 - 438a98: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 438a9c: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438aa0: 0f 28 da movaps %xmm2,%xmm3 - 438aa3: 48 85 c0 test %rax,%rax - 438aa6: 0f 85 0e 01 00 00 jne 438bba <__strcpy_ssse3+0xe4a> - 438aac: 66 0f 3a 0f d1 09 palignr $0x9,%xmm1,%xmm2 - 438ab2: 0f 29 12 movaps %xmm2,(%rdx) - 438ab5: 0f 28 51 17 movaps 0x17(%rcx),%xmm2 - 438ab9: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 438abd: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438ac1: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438ac5: 48 8d 49 10 lea 0x10(%rcx),%rcx - 438ac9: 0f 28 ca movaps %xmm2,%xmm1 - 438acc: 48 85 c0 test %rax,%rax - 438acf: 0f 85 e5 00 00 00 jne 438bba <__strcpy_ssse3+0xe4a> - 438ad5: 66 0f 3a 0f d3 09 palignr $0x9,%xmm3,%xmm2 - 438adb: 0f 29 12 movaps %xmm2,(%rdx) - 438ade: 0f 28 51 17 movaps 0x17(%rcx),%xmm2 - 438ae2: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 438ae6: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438aea: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438aee: 48 8d 49 10 lea 0x10(%rcx),%rcx - 438af2: 0f 28 da movaps %xmm2,%xmm3 - 438af5: 48 85 c0 test %rax,%rax - 438af8: 0f 85 bc 00 00 00 jne 438bba <__strcpy_ssse3+0xe4a> - 438afe: 66 0f 3a 0f d1 09 palignr $0x9,%xmm1,%xmm2 - 438b04: 0f 29 12 movaps %xmm2,(%rdx) - 438b07: 0f 28 51 17 movaps 0x17(%rcx),%xmm2 - 438b0b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 438b0f: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438b13: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438b17: 48 8d 49 10 lea 0x10(%rcx),%rcx - 438b1b: 48 85 c0 test %rax,%rax - 438b1e: 0f 85 96 00 00 00 jne 438bba <__strcpy_ssse3+0xe4a> - 438b24: 66 0f 3a 0f d3 09 palignr $0x9,%xmm3,%xmm2 - 438b2a: 0f 29 12 movaps %xmm2,(%rdx) - 438b2d: 48 8d 49 17 lea 0x17(%rcx),%rcx - 438b31: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438b35: 48 89 c8 mov %rcx,%rax - 438b38: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 438b3c: 48 29 c8 sub %rcx,%rax - 438b3f: 48 8d 49 f9 lea -0x7(%rcx),%rcx - 438b43: 48 29 c2 sub %rax,%rdx - 438b46: 0f 28 49 f7 movaps -0x9(%rcx),%xmm1 - 438b4a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 438b50: 0f 28 51 07 movaps 0x7(%rcx),%xmm2 - 438b54: 0f 28 59 17 movaps 0x17(%rcx),%xmm3 - 438b58: 0f 28 f3 movaps %xmm3,%xmm6 - 438b5b: 0f 28 61 27 movaps 0x27(%rcx),%xmm4 - 438b5f: 0f 28 fc movaps %xmm4,%xmm7 - 438b62: 0f 28 69 37 movaps 0x37(%rcx),%xmm5 - 438b66: 66 0f da f2 pminub %xmm2,%xmm6 - 438b6a: 66 0f da fd pminub %xmm5,%xmm7 - 438b6e: 66 0f da fe pminub %xmm6,%xmm7 - 438b72: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 438b76: 66 0f d7 c7 pmovmskb %xmm7,%eax - 438b7a: 0f 28 fd movaps %xmm5,%xmm7 - 438b7d: 66 0f 3a 0f ec 09 palignr $0x9,%xmm4,%xmm5 - 438b83: 48 85 c0 test %rax,%rax - 438b86: 66 0f 3a 0f e3 09 palignr $0x9,%xmm3,%xmm4 - 438b8c: 0f 85 06 ff ff ff jne 438a98 <__strcpy_ssse3+0xd28> - 438b92: 66 0f 3a 0f da 09 palignr $0x9,%xmm2,%xmm3 - 438b98: 48 8d 49 40 lea 0x40(%rcx),%rcx - 438b9c: 66 0f 3a 0f d1 09 palignr $0x9,%xmm1,%xmm2 - 438ba2: 0f 28 cf movaps %xmm7,%xmm1 - 438ba5: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) - 438ba9: 0f 29 62 20 movaps %xmm4,0x20(%rdx) - 438bad: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) - 438bb1: 0f 29 12 movaps %xmm2,(%rdx) - 438bb4: 48 8d 52 40 lea 0x40(%rdx),%rdx - 438bb8: eb 96 jmp 438b50 <__strcpy_ssse3+0xde0> - 438bba: 4c 8b 49 ff mov -0x1(%rcx),%r9 - 438bbe: 48 c7 c6 07 00 00 00 mov $0x7,%rsi - 438bc5: 4c 89 4a ff mov %r9,-0x1(%rdx) - 438bc9: e9 82 07 00 00 jmpq 439350 <__strcpy_ssse3+0x15e0> - 438bce: 66 90 xchg %ax,%ax - 438bd0: 0f 28 49 f6 movaps -0xa(%rcx),%xmm1 - 438bd4: 0f 28 51 06 movaps 0x6(%rcx),%xmm2 - 438bd8: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 438bdc: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438be0: 0f 28 da movaps %xmm2,%xmm3 - 438be3: 48 85 c0 test %rax,%rax - 438be6: 0f 85 0e 01 00 00 jne 438cfa <__strcpy_ssse3+0xf8a> - 438bec: 66 0f 3a 0f d1 0a palignr $0xa,%xmm1,%xmm2 - 438bf2: 0f 29 12 movaps %xmm2,(%rdx) - 438bf5: 0f 28 51 16 movaps 0x16(%rcx),%xmm2 - 438bf9: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 438bfd: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438c01: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438c05: 48 8d 49 10 lea 0x10(%rcx),%rcx - 438c09: 0f 28 ca movaps %xmm2,%xmm1 - 438c0c: 48 85 c0 test %rax,%rax - 438c0f: 0f 85 e5 00 00 00 jne 438cfa <__strcpy_ssse3+0xf8a> - 438c15: 66 0f 3a 0f d3 0a palignr $0xa,%xmm3,%xmm2 - 438c1b: 0f 29 12 movaps %xmm2,(%rdx) - 438c1e: 0f 28 51 16 movaps 0x16(%rcx),%xmm2 - 438c22: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 438c26: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438c2a: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438c2e: 48 8d 49 10 lea 0x10(%rcx),%rcx - 438c32: 0f 28 da movaps %xmm2,%xmm3 - 438c35: 48 85 c0 test %rax,%rax - 438c38: 0f 85 bc 00 00 00 jne 438cfa <__strcpy_ssse3+0xf8a> - 438c3e: 66 0f 3a 0f d1 0a palignr $0xa,%xmm1,%xmm2 - 438c44: 0f 29 12 movaps %xmm2,(%rdx) - 438c47: 0f 28 51 16 movaps 0x16(%rcx),%xmm2 - 438c4b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 438c4f: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438c53: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438c57: 48 8d 49 10 lea 0x10(%rcx),%rcx - 438c5b: 48 85 c0 test %rax,%rax - 438c5e: 0f 85 96 00 00 00 jne 438cfa <__strcpy_ssse3+0xf8a> - 438c64: 66 0f 3a 0f d3 0a palignr $0xa,%xmm3,%xmm2 - 438c6a: 0f 29 12 movaps %xmm2,(%rdx) - 438c6d: 48 8d 49 16 lea 0x16(%rcx),%rcx - 438c71: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438c75: 48 89 c8 mov %rcx,%rax - 438c78: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 438c7c: 48 29 c8 sub %rcx,%rax - 438c7f: 48 8d 49 fa lea -0x6(%rcx),%rcx - 438c83: 48 29 c2 sub %rax,%rdx - 438c86: 0f 28 49 f6 movaps -0xa(%rcx),%xmm1 - 438c8a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 438c90: 0f 28 51 06 movaps 0x6(%rcx),%xmm2 - 438c94: 0f 28 59 16 movaps 0x16(%rcx),%xmm3 - 438c98: 0f 28 f3 movaps %xmm3,%xmm6 - 438c9b: 0f 28 61 26 movaps 0x26(%rcx),%xmm4 - 438c9f: 0f 28 fc movaps %xmm4,%xmm7 - 438ca2: 0f 28 69 36 movaps 0x36(%rcx),%xmm5 - 438ca6: 66 0f da f2 pminub %xmm2,%xmm6 - 438caa: 66 0f da fd pminub %xmm5,%xmm7 - 438cae: 66 0f da fe pminub %xmm6,%xmm7 - 438cb2: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 438cb6: 66 0f d7 c7 pmovmskb %xmm7,%eax - 438cba: 0f 28 fd movaps %xmm5,%xmm7 - 438cbd: 66 0f 3a 0f ec 0a palignr $0xa,%xmm4,%xmm5 - 438cc3: 48 85 c0 test %rax,%rax - 438cc6: 66 0f 3a 0f e3 0a palignr $0xa,%xmm3,%xmm4 - 438ccc: 0f 85 06 ff ff ff jne 438bd8 <__strcpy_ssse3+0xe68> - 438cd2: 66 0f 3a 0f da 0a palignr $0xa,%xmm2,%xmm3 - 438cd8: 48 8d 49 40 lea 0x40(%rcx),%rcx - 438cdc: 66 0f 3a 0f d1 0a palignr $0xa,%xmm1,%xmm2 - 438ce2: 0f 28 cf movaps %xmm7,%xmm1 - 438ce5: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) - 438ce9: 0f 29 62 20 movaps %xmm4,0x20(%rdx) - 438ced: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) - 438cf1: 0f 29 12 movaps %xmm2,(%rdx) - 438cf4: 48 8d 52 40 lea 0x40(%rdx),%rdx - 438cf8: eb 96 jmp 438c90 <__strcpy_ssse3+0xf20> - 438cfa: 4c 8b 49 fe mov -0x2(%rcx),%r9 - 438cfe: 48 c7 c6 06 00 00 00 mov $0x6,%rsi - 438d05: 4c 89 4a fe mov %r9,-0x2(%rdx) - 438d09: e9 42 06 00 00 jmpq 439350 <__strcpy_ssse3+0x15e0> - 438d0e: 66 90 xchg %ax,%ax - 438d10: 0f 28 49 f5 movaps -0xb(%rcx),%xmm1 - 438d14: 0f 28 51 05 movaps 0x5(%rcx),%xmm2 - 438d18: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 438d1c: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438d20: 0f 28 da movaps %xmm2,%xmm3 - 438d23: 48 85 c0 test %rax,%rax - 438d26: 0f 85 0e 01 00 00 jne 438e3a <__strcpy_ssse3+0x10ca> - 438d2c: 66 0f 3a 0f d1 0b palignr $0xb,%xmm1,%xmm2 - 438d32: 0f 29 12 movaps %xmm2,(%rdx) - 438d35: 0f 28 51 15 movaps 0x15(%rcx),%xmm2 - 438d39: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 438d3d: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438d41: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438d45: 48 8d 49 10 lea 0x10(%rcx),%rcx - 438d49: 0f 28 ca movaps %xmm2,%xmm1 - 438d4c: 48 85 c0 test %rax,%rax - 438d4f: 0f 85 e5 00 00 00 jne 438e3a <__strcpy_ssse3+0x10ca> - 438d55: 66 0f 3a 0f d3 0b palignr $0xb,%xmm3,%xmm2 - 438d5b: 0f 29 12 movaps %xmm2,(%rdx) - 438d5e: 0f 28 51 15 movaps 0x15(%rcx),%xmm2 - 438d62: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 438d66: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438d6a: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438d6e: 48 8d 49 10 lea 0x10(%rcx),%rcx - 438d72: 0f 28 da movaps %xmm2,%xmm3 - 438d75: 48 85 c0 test %rax,%rax - 438d78: 0f 85 bc 00 00 00 jne 438e3a <__strcpy_ssse3+0x10ca> - 438d7e: 66 0f 3a 0f d1 0b palignr $0xb,%xmm1,%xmm2 - 438d84: 0f 29 12 movaps %xmm2,(%rdx) - 438d87: 0f 28 51 15 movaps 0x15(%rcx),%xmm2 - 438d8b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 438d8f: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438d93: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438d97: 48 8d 49 10 lea 0x10(%rcx),%rcx - 438d9b: 48 85 c0 test %rax,%rax - 438d9e: 0f 85 96 00 00 00 jne 438e3a <__strcpy_ssse3+0x10ca> - 438da4: 66 0f 3a 0f d3 0b palignr $0xb,%xmm3,%xmm2 - 438daa: 0f 29 12 movaps %xmm2,(%rdx) - 438dad: 48 8d 49 15 lea 0x15(%rcx),%rcx - 438db1: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438db5: 48 89 c8 mov %rcx,%rax - 438db8: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 438dbc: 48 29 c8 sub %rcx,%rax - 438dbf: 48 8d 49 fb lea -0x5(%rcx),%rcx - 438dc3: 48 29 c2 sub %rax,%rdx - 438dc6: 0f 28 49 f5 movaps -0xb(%rcx),%xmm1 - 438dca: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 438dd0: 0f 28 51 05 movaps 0x5(%rcx),%xmm2 - 438dd4: 0f 28 59 15 movaps 0x15(%rcx),%xmm3 - 438dd8: 0f 28 f3 movaps %xmm3,%xmm6 - 438ddb: 0f 28 61 25 movaps 0x25(%rcx),%xmm4 - 438ddf: 0f 28 fc movaps %xmm4,%xmm7 - 438de2: 0f 28 69 35 movaps 0x35(%rcx),%xmm5 - 438de6: 66 0f da f2 pminub %xmm2,%xmm6 - 438dea: 66 0f da fd pminub %xmm5,%xmm7 - 438dee: 66 0f da fe pminub %xmm6,%xmm7 - 438df2: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 438df6: 66 0f d7 c7 pmovmskb %xmm7,%eax - 438dfa: 0f 28 fd movaps %xmm5,%xmm7 - 438dfd: 66 0f 3a 0f ec 0b palignr $0xb,%xmm4,%xmm5 - 438e03: 48 85 c0 test %rax,%rax - 438e06: 66 0f 3a 0f e3 0b palignr $0xb,%xmm3,%xmm4 - 438e0c: 0f 85 06 ff ff ff jne 438d18 <__strcpy_ssse3+0xfa8> - 438e12: 66 0f 3a 0f da 0b palignr $0xb,%xmm2,%xmm3 - 438e18: 48 8d 49 40 lea 0x40(%rcx),%rcx - 438e1c: 66 0f 3a 0f d1 0b palignr $0xb,%xmm1,%xmm2 - 438e22: 0f 28 cf movaps %xmm7,%xmm1 - 438e25: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) - 438e29: 0f 29 62 20 movaps %xmm4,0x20(%rdx) - 438e2d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) - 438e31: 0f 29 12 movaps %xmm2,(%rdx) - 438e34: 48 8d 52 40 lea 0x40(%rdx),%rdx - 438e38: eb 96 jmp 438dd0 <__strcpy_ssse3+0x1060> - 438e3a: 4c 8b 49 fd mov -0x3(%rcx),%r9 - 438e3e: 48 c7 c6 05 00 00 00 mov $0x5,%rsi - 438e45: 4c 89 4a fd mov %r9,-0x3(%rdx) - 438e49: e9 02 05 00 00 jmpq 439350 <__strcpy_ssse3+0x15e0> - 438e4e: 66 90 xchg %ax,%ax - 438e50: 0f 28 49 f4 movaps -0xc(%rcx),%xmm1 - 438e54: 0f 28 51 04 movaps 0x4(%rcx),%xmm2 - 438e58: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 438e5c: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438e60: 0f 28 da movaps %xmm2,%xmm3 - 438e63: 48 85 c0 test %rax,%rax - 438e66: 0f 85 0e 01 00 00 jne 438f7a <__strcpy_ssse3+0x120a> - 438e6c: 66 0f 3a 0f d1 0c palignr $0xc,%xmm1,%xmm2 - 438e72: 0f 29 12 movaps %xmm2,(%rdx) - 438e75: 0f 28 51 14 movaps 0x14(%rcx),%xmm2 - 438e79: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 438e7d: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438e81: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438e85: 48 8d 49 10 lea 0x10(%rcx),%rcx - 438e89: 0f 28 ca movaps %xmm2,%xmm1 - 438e8c: 48 85 c0 test %rax,%rax - 438e8f: 0f 85 e5 00 00 00 jne 438f7a <__strcpy_ssse3+0x120a> - 438e95: 66 0f 3a 0f d3 0c palignr $0xc,%xmm3,%xmm2 - 438e9b: 0f 29 12 movaps %xmm2,(%rdx) - 438e9e: 0f 28 51 14 movaps 0x14(%rcx),%xmm2 - 438ea2: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 438ea6: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438eaa: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438eae: 48 8d 49 10 lea 0x10(%rcx),%rcx - 438eb2: 0f 28 da movaps %xmm2,%xmm3 - 438eb5: 48 85 c0 test %rax,%rax - 438eb8: 0f 85 bc 00 00 00 jne 438f7a <__strcpy_ssse3+0x120a> - 438ebe: 66 0f 3a 0f d1 0c palignr $0xc,%xmm1,%xmm2 - 438ec4: 0f 29 12 movaps %xmm2,(%rdx) - 438ec7: 0f 28 51 14 movaps 0x14(%rcx),%xmm2 - 438ecb: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 438ecf: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438ed3: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438ed7: 48 8d 49 10 lea 0x10(%rcx),%rcx - 438edb: 48 85 c0 test %rax,%rax - 438ede: 0f 85 96 00 00 00 jne 438f7a <__strcpy_ssse3+0x120a> - 438ee4: 66 0f 3a 0f d3 0c palignr $0xc,%xmm3,%xmm2 - 438eea: 0f 29 12 movaps %xmm2,(%rdx) - 438eed: 48 8d 49 14 lea 0x14(%rcx),%rcx - 438ef1: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438ef5: 48 89 c8 mov %rcx,%rax - 438ef8: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 438efc: 48 29 c8 sub %rcx,%rax - 438eff: 48 8d 49 fc lea -0x4(%rcx),%rcx - 438f03: 48 29 c2 sub %rax,%rdx - 438f06: 0f 28 49 f4 movaps -0xc(%rcx),%xmm1 - 438f0a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 438f10: 0f 28 51 04 movaps 0x4(%rcx),%xmm2 - 438f14: 0f 28 59 14 movaps 0x14(%rcx),%xmm3 - 438f18: 0f 28 f3 movaps %xmm3,%xmm6 - 438f1b: 0f 28 61 24 movaps 0x24(%rcx),%xmm4 - 438f1f: 0f 28 fc movaps %xmm4,%xmm7 - 438f22: 0f 28 69 34 movaps 0x34(%rcx),%xmm5 - 438f26: 66 0f da f2 pminub %xmm2,%xmm6 - 438f2a: 66 0f da fd pminub %xmm5,%xmm7 - 438f2e: 66 0f da fe pminub %xmm6,%xmm7 - 438f32: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 438f36: 66 0f d7 c7 pmovmskb %xmm7,%eax - 438f3a: 0f 28 fd movaps %xmm5,%xmm7 - 438f3d: 66 0f 3a 0f ec 0c palignr $0xc,%xmm4,%xmm5 - 438f43: 48 85 c0 test %rax,%rax - 438f46: 66 0f 3a 0f e3 0c palignr $0xc,%xmm3,%xmm4 - 438f4c: 0f 85 06 ff ff ff jne 438e58 <__strcpy_ssse3+0x10e8> - 438f52: 66 0f 3a 0f da 0c palignr $0xc,%xmm2,%xmm3 - 438f58: 48 8d 49 40 lea 0x40(%rcx),%rcx - 438f5c: 66 0f 3a 0f d1 0c palignr $0xc,%xmm1,%xmm2 - 438f62: 0f 28 cf movaps %xmm7,%xmm1 - 438f65: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) - 438f69: 0f 29 62 20 movaps %xmm4,0x20(%rdx) - 438f6d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) - 438f71: 0f 29 12 movaps %xmm2,(%rdx) - 438f74: 48 8d 52 40 lea 0x40(%rdx),%rdx - 438f78: eb 96 jmp 438f10 <__strcpy_ssse3+0x11a0> - 438f7a: 44 8b 09 mov (%rcx),%r9d - 438f7d: 48 c7 c6 04 00 00 00 mov $0x4,%rsi - 438f84: 44 89 0a mov %r9d,(%rdx) - 438f87: e9 c4 03 00 00 jmpq 439350 <__strcpy_ssse3+0x15e0> - 438f8c: 0f 1f 40 00 nopl 0x0(%rax) - 438f90: 0f 28 49 f3 movaps -0xd(%rcx),%xmm1 - 438f94: 0f 28 51 03 movaps 0x3(%rcx),%xmm2 - 438f98: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 438f9c: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438fa0: 0f 28 da movaps %xmm2,%xmm3 - 438fa3: 48 85 c0 test %rax,%rax - 438fa6: 0f 85 0e 01 00 00 jne 4390ba <__strcpy_ssse3+0x134a> - 438fac: 66 0f 3a 0f d1 0d palignr $0xd,%xmm1,%xmm2 - 438fb2: 0f 29 12 movaps %xmm2,(%rdx) - 438fb5: 0f 28 51 13 movaps 0x13(%rcx),%xmm2 - 438fb9: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 438fbd: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438fc1: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438fc5: 48 8d 49 10 lea 0x10(%rcx),%rcx - 438fc9: 0f 28 ca movaps %xmm2,%xmm1 - 438fcc: 48 85 c0 test %rax,%rax - 438fcf: 0f 85 e5 00 00 00 jne 4390ba <__strcpy_ssse3+0x134a> - 438fd5: 66 0f 3a 0f d3 0d palignr $0xd,%xmm3,%xmm2 - 438fdb: 0f 29 12 movaps %xmm2,(%rdx) - 438fde: 0f 28 51 13 movaps 0x13(%rcx),%xmm2 - 438fe2: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 438fe6: 48 8d 52 10 lea 0x10(%rdx),%rdx - 438fea: 66 0f d7 c0 pmovmskb %xmm0,%eax - 438fee: 48 8d 49 10 lea 0x10(%rcx),%rcx - 438ff2: 0f 28 da movaps %xmm2,%xmm3 - 438ff5: 48 85 c0 test %rax,%rax - 438ff8: 0f 85 bc 00 00 00 jne 4390ba <__strcpy_ssse3+0x134a> - 438ffe: 66 0f 3a 0f d1 0d palignr $0xd,%xmm1,%xmm2 - 439004: 0f 29 12 movaps %xmm2,(%rdx) - 439007: 0f 28 51 13 movaps 0x13(%rcx),%xmm2 - 43900b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43900f: 48 8d 52 10 lea 0x10(%rdx),%rdx - 439013: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439017: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43901b: 48 85 c0 test %rax,%rax - 43901e: 0f 85 96 00 00 00 jne 4390ba <__strcpy_ssse3+0x134a> - 439024: 66 0f 3a 0f d3 0d palignr $0xd,%xmm3,%xmm2 - 43902a: 0f 29 12 movaps %xmm2,(%rdx) - 43902d: 48 8d 49 13 lea 0x13(%rcx),%rcx - 439031: 48 8d 52 10 lea 0x10(%rdx),%rdx - 439035: 48 89 c8 mov %rcx,%rax - 439038: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 43903c: 48 29 c8 sub %rcx,%rax - 43903f: 48 8d 49 fd lea -0x3(%rcx),%rcx - 439043: 48 29 c2 sub %rax,%rdx - 439046: 0f 28 49 f3 movaps -0xd(%rcx),%xmm1 - 43904a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 439050: 0f 28 51 03 movaps 0x3(%rcx),%xmm2 - 439054: 0f 28 59 13 movaps 0x13(%rcx),%xmm3 - 439058: 0f 28 f3 movaps %xmm3,%xmm6 - 43905b: 0f 28 61 23 movaps 0x23(%rcx),%xmm4 - 43905f: 0f 28 fc movaps %xmm4,%xmm7 - 439062: 0f 28 69 33 movaps 0x33(%rcx),%xmm5 - 439066: 66 0f da f2 pminub %xmm2,%xmm6 - 43906a: 66 0f da fd pminub %xmm5,%xmm7 - 43906e: 66 0f da fe pminub %xmm6,%xmm7 - 439072: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 439076: 66 0f d7 c7 pmovmskb %xmm7,%eax - 43907a: 0f 28 fd movaps %xmm5,%xmm7 - 43907d: 66 0f 3a 0f ec 0d palignr $0xd,%xmm4,%xmm5 - 439083: 48 85 c0 test %rax,%rax - 439086: 66 0f 3a 0f e3 0d palignr $0xd,%xmm3,%xmm4 - 43908c: 0f 85 06 ff ff ff jne 438f98 <__strcpy_ssse3+0x1228> - 439092: 66 0f 3a 0f da 0d palignr $0xd,%xmm2,%xmm3 - 439098: 48 8d 49 40 lea 0x40(%rcx),%rcx - 43909c: 66 0f 3a 0f d1 0d palignr $0xd,%xmm1,%xmm2 - 4390a2: 0f 28 cf movaps %xmm7,%xmm1 - 4390a5: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) - 4390a9: 0f 29 62 20 movaps %xmm4,0x20(%rdx) - 4390ad: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) - 4390b1: 0f 29 12 movaps %xmm2,(%rdx) - 4390b4: 48 8d 52 40 lea 0x40(%rdx),%rdx - 4390b8: eb 96 jmp 439050 <__strcpy_ssse3+0x12e0> - 4390ba: 44 8b 49 ff mov -0x1(%rcx),%r9d - 4390be: 48 c7 c6 03 00 00 00 mov $0x3,%rsi - 4390c5: 44 89 4a ff mov %r9d,-0x1(%rdx) - 4390c9: e9 82 02 00 00 jmpq 439350 <__strcpy_ssse3+0x15e0> - 4390ce: 66 90 xchg %ax,%ax - 4390d0: 0f 28 49 f2 movaps -0xe(%rcx),%xmm1 - 4390d4: 0f 28 51 02 movaps 0x2(%rcx),%xmm2 - 4390d8: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 4390dc: 66 0f d7 c0 pmovmskb %xmm0,%eax - 4390e0: 0f 28 da movaps %xmm2,%xmm3 - 4390e3: 48 85 c0 test %rax,%rax - 4390e6: 0f 85 0e 01 00 00 jne 4391fa <__strcpy_ssse3+0x148a> - 4390ec: 66 0f 3a 0f d1 0e palignr $0xe,%xmm1,%xmm2 - 4390f2: 0f 29 12 movaps %xmm2,(%rdx) - 4390f5: 0f 28 51 12 movaps 0x12(%rcx),%xmm2 - 4390f9: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 4390fd: 48 8d 52 10 lea 0x10(%rdx),%rdx - 439101: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439105: 48 8d 49 10 lea 0x10(%rcx),%rcx - 439109: 0f 28 ca movaps %xmm2,%xmm1 - 43910c: 48 85 c0 test %rax,%rax - 43910f: 0f 85 e5 00 00 00 jne 4391fa <__strcpy_ssse3+0x148a> - 439115: 66 0f 3a 0f d3 0e palignr $0xe,%xmm3,%xmm2 - 43911b: 0f 29 12 movaps %xmm2,(%rdx) - 43911e: 0f 28 51 12 movaps 0x12(%rcx),%xmm2 - 439122: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 439126: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43912a: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43912e: 48 8d 49 10 lea 0x10(%rcx),%rcx - 439132: 0f 28 da movaps %xmm2,%xmm3 - 439135: 48 85 c0 test %rax,%rax - 439138: 0f 85 bc 00 00 00 jne 4391fa <__strcpy_ssse3+0x148a> - 43913e: 66 0f 3a 0f d1 0e palignr $0xe,%xmm1,%xmm2 - 439144: 0f 29 12 movaps %xmm2,(%rdx) - 439147: 0f 28 51 12 movaps 0x12(%rcx),%xmm2 - 43914b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43914f: 48 8d 52 10 lea 0x10(%rdx),%rdx - 439153: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439157: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43915b: 48 85 c0 test %rax,%rax - 43915e: 0f 85 96 00 00 00 jne 4391fa <__strcpy_ssse3+0x148a> - 439164: 66 0f 3a 0f d3 0e palignr $0xe,%xmm3,%xmm2 - 43916a: 0f 29 12 movaps %xmm2,(%rdx) - 43916d: 48 8d 49 12 lea 0x12(%rcx),%rcx - 439171: 48 8d 52 10 lea 0x10(%rdx),%rdx - 439175: 48 89 c8 mov %rcx,%rax - 439178: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 43917c: 48 29 c8 sub %rcx,%rax - 43917f: 48 8d 49 fe lea -0x2(%rcx),%rcx - 439183: 48 29 c2 sub %rax,%rdx - 439186: 0f 28 49 f2 movaps -0xe(%rcx),%xmm1 - 43918a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 439190: 0f 28 51 02 movaps 0x2(%rcx),%xmm2 - 439194: 0f 28 59 12 movaps 0x12(%rcx),%xmm3 - 439198: 0f 28 f3 movaps %xmm3,%xmm6 - 43919b: 0f 28 61 22 movaps 0x22(%rcx),%xmm4 - 43919f: 0f 28 fc movaps %xmm4,%xmm7 - 4391a2: 0f 28 69 32 movaps 0x32(%rcx),%xmm5 - 4391a6: 66 0f da f2 pminub %xmm2,%xmm6 - 4391aa: 66 0f da fd pminub %xmm5,%xmm7 - 4391ae: 66 0f da fe pminub %xmm6,%xmm7 - 4391b2: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 4391b6: 66 0f d7 c7 pmovmskb %xmm7,%eax - 4391ba: 0f 28 fd movaps %xmm5,%xmm7 - 4391bd: 66 0f 3a 0f ec 0e palignr $0xe,%xmm4,%xmm5 - 4391c3: 48 85 c0 test %rax,%rax - 4391c6: 66 0f 3a 0f e3 0e palignr $0xe,%xmm3,%xmm4 - 4391cc: 0f 85 06 ff ff ff jne 4390d8 <__strcpy_ssse3+0x1368> - 4391d2: 66 0f 3a 0f da 0e palignr $0xe,%xmm2,%xmm3 - 4391d8: 48 8d 49 40 lea 0x40(%rcx),%rcx - 4391dc: 66 0f 3a 0f d1 0e palignr $0xe,%xmm1,%xmm2 - 4391e2: 0f 28 cf movaps %xmm7,%xmm1 - 4391e5: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) - 4391e9: 0f 29 62 20 movaps %xmm4,0x20(%rdx) - 4391ed: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) - 4391f1: 0f 29 12 movaps %xmm2,(%rdx) - 4391f4: 48 8d 52 40 lea 0x40(%rdx),%rdx - 4391f8: eb 96 jmp 439190 <__strcpy_ssse3+0x1420> - 4391fa: 44 8b 49 fe mov -0x2(%rcx),%r9d - 4391fe: 48 c7 c6 02 00 00 00 mov $0x2,%rsi - 439205: 44 89 4a fe mov %r9d,-0x2(%rdx) - 439209: e9 42 01 00 00 jmpq 439350 <__strcpy_ssse3+0x15e0> - 43920e: 66 90 xchg %ax,%ax - 439210: 0f 28 49 f1 movaps -0xf(%rcx),%xmm1 - 439214: 0f 28 51 01 movaps 0x1(%rcx),%xmm2 - 439218: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43921c: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439220: 0f 28 da movaps %xmm2,%xmm3 - 439223: 48 85 c0 test %rax,%rax - 439226: 0f 85 0e 01 00 00 jne 43933a <__strcpy_ssse3+0x15ca> - 43922c: 66 0f 3a 0f d1 0f palignr $0xf,%xmm1,%xmm2 - 439232: 0f 29 12 movaps %xmm2,(%rdx) - 439235: 0f 28 51 11 movaps 0x11(%rcx),%xmm2 - 439239: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43923d: 48 8d 52 10 lea 0x10(%rdx),%rdx - 439241: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439245: 48 8d 49 10 lea 0x10(%rcx),%rcx - 439249: 0f 28 ca movaps %xmm2,%xmm1 - 43924c: 48 85 c0 test %rax,%rax - 43924f: 0f 85 e5 00 00 00 jne 43933a <__strcpy_ssse3+0x15ca> - 439255: 66 0f 3a 0f d3 0f palignr $0xf,%xmm3,%xmm2 - 43925b: 0f 29 12 movaps %xmm2,(%rdx) - 43925e: 0f 28 51 11 movaps 0x11(%rcx),%xmm2 - 439262: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 439266: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43926a: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43926e: 48 8d 49 10 lea 0x10(%rcx),%rcx - 439272: 0f 28 da movaps %xmm2,%xmm3 - 439275: 48 85 c0 test %rax,%rax - 439278: 0f 85 bc 00 00 00 jne 43933a <__strcpy_ssse3+0x15ca> - 43927e: 66 0f 3a 0f d1 0f palignr $0xf,%xmm1,%xmm2 - 439284: 0f 29 12 movaps %xmm2,(%rdx) - 439287: 0f 28 51 11 movaps 0x11(%rcx),%xmm2 - 43928b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43928f: 48 8d 52 10 lea 0x10(%rdx),%rdx - 439293: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439297: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43929b: 48 85 c0 test %rax,%rax - 43929e: 0f 85 96 00 00 00 jne 43933a <__strcpy_ssse3+0x15ca> - 4392a4: 66 0f 3a 0f d3 0f palignr $0xf,%xmm3,%xmm2 - 4392aa: 0f 29 12 movaps %xmm2,(%rdx) - 4392ad: 48 8d 49 11 lea 0x11(%rcx),%rcx - 4392b1: 48 8d 52 10 lea 0x10(%rdx),%rdx - 4392b5: 48 89 c8 mov %rcx,%rax - 4392b8: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 4392bc: 48 29 c8 sub %rcx,%rax - 4392bf: 48 8d 49 ff lea -0x1(%rcx),%rcx - 4392c3: 48 29 c2 sub %rax,%rdx - 4392c6: 0f 28 49 f1 movaps -0xf(%rcx),%xmm1 - 4392ca: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4392d0: 0f 28 51 01 movaps 0x1(%rcx),%xmm2 - 4392d4: 0f 28 59 11 movaps 0x11(%rcx),%xmm3 - 4392d8: 0f 28 f3 movaps %xmm3,%xmm6 - 4392db: 0f 28 61 21 movaps 0x21(%rcx),%xmm4 - 4392df: 0f 28 fc movaps %xmm4,%xmm7 - 4392e2: 0f 28 69 31 movaps 0x31(%rcx),%xmm5 - 4392e6: 66 0f da f2 pminub %xmm2,%xmm6 - 4392ea: 66 0f da fd pminub %xmm5,%xmm7 - 4392ee: 66 0f da fe pminub %xmm6,%xmm7 - 4392f2: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 4392f6: 66 0f d7 c7 pmovmskb %xmm7,%eax - 4392fa: 0f 28 fd movaps %xmm5,%xmm7 - 4392fd: 66 0f 3a 0f ec 0f palignr $0xf,%xmm4,%xmm5 - 439303: 48 85 c0 test %rax,%rax - 439306: 66 0f 3a 0f e3 0f palignr $0xf,%xmm3,%xmm4 - 43930c: 0f 85 06 ff ff ff jne 439218 <__strcpy_ssse3+0x14a8> - 439312: 66 0f 3a 0f da 0f palignr $0xf,%xmm2,%xmm3 - 439318: 48 8d 49 40 lea 0x40(%rcx),%rcx - 43931c: 66 0f 3a 0f d1 0f palignr $0xf,%xmm1,%xmm2 - 439322: 0f 28 cf movaps %xmm7,%xmm1 - 439325: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) - 439329: 0f 29 62 20 movaps %xmm4,0x20(%rdx) - 43932d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) - 439331: 0f 29 12 movaps %xmm2,(%rdx) - 439334: 48 8d 52 40 lea 0x40(%rdx),%rdx - 439338: eb 96 jmp 4392d0 <__strcpy_ssse3+0x1560> - 43933a: 44 8b 49 fd mov -0x3(%rcx),%r9d - 43933e: 48 c7 c6 01 00 00 00 mov $0x1,%rsi - 439345: 44 89 4a fd mov %r9d,-0x3(%rdx) - 439349: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 439350: 48 01 f2 add %rsi,%rdx - 439353: 48 01 f1 add %rsi,%rcx - 439356: 84 c0 test %al,%al - 439358: 74 56 je 4393b0 <__strcpy_ssse3+0x1640> - 43935a: a8 01 test $0x1,%al - 43935c: 0f 85 ae 00 00 00 jne 439410 <__strcpy_ssse3+0x16a0> - 439362: a8 02 test $0x2,%al - 439364: 0f 85 b6 00 00 00 jne 439420 <__strcpy_ssse3+0x16b0> - 43936a: a8 04 test $0x4,%al - 43936c: 0f 85 be 00 00 00 jne 439430 <__strcpy_ssse3+0x16c0> - 439372: a8 08 test $0x8,%al - 439374: 0f 85 c6 00 00 00 jne 439440 <__strcpy_ssse3+0x16d0> - 43937a: a8 10 test $0x10,%al - 43937c: 0f 85 ce 00 00 00 jne 439450 <__strcpy_ssse3+0x16e0> - 439382: a8 20 test $0x20,%al - 439384: 0f 85 d6 00 00 00 jne 439460 <__strcpy_ssse3+0x16f0> - 43938a: a8 40 test $0x40,%al - 43938c: 0f 85 de 00 00 00 jne 439470 <__strcpy_ssse3+0x1700> - 439392: 0f 1f 40 00 nopl 0x0(%rax) - 439396: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43939d: 00 00 00 - 4393a0: 48 8b 01 mov (%rcx),%rax - 4393a3: 48 89 02 mov %rax,(%rdx) - 4393a6: 48 89 f8 mov %rdi,%rax - 4393a9: c3 retq - 4393aa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4393b0: f6 c4 01 test $0x1,%ah - 4393b3: 0f 85 c7 00 00 00 jne 439480 <__strcpy_ssse3+0x1710> - 4393b9: f6 c4 02 test $0x2,%ah - 4393bc: 0f 85 ce 00 00 00 jne 439490 <__strcpy_ssse3+0x1720> - 4393c2: f6 c4 04 test $0x4,%ah - 4393c5: 0f 85 d5 00 00 00 jne 4394a0 <__strcpy_ssse3+0x1730> - 4393cb: f6 c4 08 test $0x8,%ah - 4393ce: 0f 85 dc 00 00 00 jne 4394b0 <__strcpy_ssse3+0x1740> - 4393d4: f6 c4 10 test $0x10,%ah - 4393d7: 0f 85 e3 00 00 00 jne 4394c0 <__strcpy_ssse3+0x1750> - 4393dd: f6 c4 20 test $0x20,%ah - 4393e0: 0f 85 fa 00 00 00 jne 4394e0 <__strcpy_ssse3+0x1770> - 4393e6: f6 c4 40 test $0x40,%ah - 4393e9: 0f 85 11 01 00 00 jne 439500 <__strcpy_ssse3+0x1790> - 4393ef: 90 nop - 4393f0: 48 8b 01 mov (%rcx),%rax - 4393f3: 48 89 02 mov %rax,(%rdx) - 4393f6: 48 8b 41 08 mov 0x8(%rcx),%rax - 4393fa: 48 89 42 08 mov %rax,0x8(%rdx) - 4393fe: 48 89 f8 mov %rdi,%rax - 439401: c3 retq - 439402: 0f 1f 40 00 nopl 0x0(%rax) - 439406: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43940d: 00 00 00 - 439410: 8a 01 mov (%rcx),%al - 439412: 88 02 mov %al,(%rdx) - 439414: 48 89 f8 mov %rdi,%rax - 439417: c3 retq - 439418: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 43941f: 00 - 439420: 66 8b 01 mov (%rcx),%ax - 439423: 66 89 02 mov %ax,(%rdx) - 439426: 48 89 f8 mov %rdi,%rax - 439429: c3 retq - 43942a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 439430: 66 8b 01 mov (%rcx),%ax - 439433: 66 89 02 mov %ax,(%rdx) - 439436: 8a 41 02 mov 0x2(%rcx),%al - 439439: 88 42 02 mov %al,0x2(%rdx) - 43943c: 48 89 f8 mov %rdi,%rax - 43943f: c3 retq - 439440: 8b 01 mov (%rcx),%eax - 439442: 89 02 mov %eax,(%rdx) - 439444: 48 89 f8 mov %rdi,%rax - 439447: c3 retq - 439448: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 43944f: 00 - 439450: 8b 01 mov (%rcx),%eax - 439452: 89 02 mov %eax,(%rdx) - 439454: 8a 41 04 mov 0x4(%rcx),%al - 439457: 88 42 04 mov %al,0x4(%rdx) - 43945a: 48 89 f8 mov %rdi,%rax - 43945d: c3 retq - 43945e: 66 90 xchg %ax,%ax - 439460: 8b 01 mov (%rcx),%eax - 439462: 89 02 mov %eax,(%rdx) - 439464: 66 8b 41 04 mov 0x4(%rcx),%ax - 439468: 66 89 42 04 mov %ax,0x4(%rdx) - 43946c: 48 89 f8 mov %rdi,%rax - 43946f: c3 retq - 439470: 8b 01 mov (%rcx),%eax - 439472: 89 02 mov %eax,(%rdx) - 439474: 8b 41 03 mov 0x3(%rcx),%eax - 439477: 89 42 03 mov %eax,0x3(%rdx) - 43947a: 48 89 f8 mov %rdi,%rax - 43947d: c3 retq - 43947e: 66 90 xchg %ax,%ax - 439480: 48 8b 01 mov (%rcx),%rax - 439483: 48 89 02 mov %rax,(%rdx) - 439486: 8b 41 05 mov 0x5(%rcx),%eax - 439489: 89 42 05 mov %eax,0x5(%rdx) - 43948c: 48 89 f8 mov %rdi,%rax - 43948f: c3 retq - 439490: 48 8b 01 mov (%rcx),%rax - 439493: 48 89 02 mov %rax,(%rdx) - 439496: 8b 41 06 mov 0x6(%rcx),%eax - 439499: 89 42 06 mov %eax,0x6(%rdx) - 43949c: 48 89 f8 mov %rdi,%rax - 43949f: c3 retq - 4394a0: 48 8b 01 mov (%rcx),%rax - 4394a3: 48 89 02 mov %rax,(%rdx) - 4394a6: 8b 41 07 mov 0x7(%rcx),%eax - 4394a9: 89 42 07 mov %eax,0x7(%rdx) - 4394ac: 48 89 f8 mov %rdi,%rax - 4394af: c3 retq - 4394b0: 48 8b 01 mov (%rcx),%rax - 4394b3: 48 89 02 mov %rax,(%rdx) - 4394b6: 8b 41 08 mov 0x8(%rcx),%eax - 4394b9: 89 42 08 mov %eax,0x8(%rdx) - 4394bc: 48 89 f8 mov %rdi,%rax - 4394bf: c3 retq - 4394c0: 48 8b 01 mov (%rcx),%rax - 4394c3: 48 89 02 mov %rax,(%rdx) - 4394c6: 48 8b 41 05 mov 0x5(%rcx),%rax - 4394ca: 48 89 42 05 mov %rax,0x5(%rdx) - 4394ce: 48 89 f8 mov %rdi,%rax - 4394d1: c3 retq - 4394d2: 0f 1f 40 00 nopl 0x0(%rax) - 4394d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4394dd: 00 00 00 - 4394e0: 48 8b 01 mov (%rcx),%rax - 4394e3: 48 89 02 mov %rax,(%rdx) - 4394e6: 48 8b 41 06 mov 0x6(%rcx),%rax - 4394ea: 48 89 42 06 mov %rax,0x6(%rdx) - 4394ee: 48 89 f8 mov %rdi,%rax - 4394f1: c3 retq - 4394f2: 0f 1f 40 00 nopl 0x0(%rax) - 4394f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4394fd: 00 00 00 - 439500: 48 8b 01 mov (%rcx),%rax - 439503: 48 89 02 mov %rax,(%rdx) - 439506: 48 8b 41 07 mov 0x7(%rcx),%rax - 43950a: 48 89 42 07 mov %rax,0x7(%rdx) - 43950e: 48 89 f8 mov %rdi,%rax - 439511: c3 retq - 439512: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 439519: 00 00 00 - 43951c: 0f 1f 40 00 nopl 0x0(%rax) - -0000000000439520 <__stpcpy_ssse3>: - 439520: 48 89 f1 mov %rsi,%rcx - 439523: 48 89 fa mov %rdi,%rdx - 439526: 80 39 00 cmpb $0x0,(%rcx) - 439529: 0f 84 91 16 00 00 je 43abc0 <__stpcpy_ssse3+0x16a0> - 43952f: 80 79 01 00 cmpb $0x0,0x1(%rcx) - 439533: 0f 84 97 16 00 00 je 43abd0 <__stpcpy_ssse3+0x16b0> - 439539: 80 79 02 00 cmpb $0x0,0x2(%rcx) - 43953d: 0f 84 9d 16 00 00 je 43abe0 <__stpcpy_ssse3+0x16c0> - 439543: 80 79 03 00 cmpb $0x0,0x3(%rcx) - 439547: 0f 84 b3 16 00 00 je 43ac00 <__stpcpy_ssse3+0x16e0> - 43954d: 80 79 04 00 cmpb $0x0,0x4(%rcx) - 439551: 0f 84 b9 16 00 00 je 43ac10 <__stpcpy_ssse3+0x16f0> - 439557: 80 79 05 00 cmpb $0x0,0x5(%rcx) - 43955b: 0f 84 bf 16 00 00 je 43ac20 <__stpcpy_ssse3+0x1700> - 439561: 80 79 06 00 cmpb $0x0,0x6(%rcx) - 439565: 0f 84 d5 16 00 00 je 43ac40 <__stpcpy_ssse3+0x1720> - 43956b: 80 79 07 00 cmpb $0x0,0x7(%rcx) - 43956f: 0f 84 db 15 00 00 je 43ab50 <__stpcpy_ssse3+0x1630> - 439575: 80 79 08 00 cmpb $0x0,0x8(%rcx) - 439579: 0f 84 d1 16 00 00 je 43ac50 <__stpcpy_ssse3+0x1730> - 43957f: 80 79 09 00 cmpb $0x0,0x9(%rcx) - 439583: 0f 84 e7 16 00 00 je 43ac70 <__stpcpy_ssse3+0x1750> - 439589: 80 79 0a 00 cmpb $0x0,0xa(%rcx) - 43958d: 0f 84 fd 16 00 00 je 43ac90 <__stpcpy_ssse3+0x1770> - 439593: 80 79 0b 00 cmpb $0x0,0xb(%rcx) - 439597: 0f 84 13 17 00 00 je 43acb0 <__stpcpy_ssse3+0x1790> - 43959d: 80 79 0c 00 cmpb $0x0,0xc(%rcx) - 4395a1: 0f 84 29 17 00 00 je 43acd0 <__stpcpy_ssse3+0x17b0> - 4395a7: 80 79 0d 00 cmpb $0x0,0xd(%rcx) - 4395ab: 0f 84 3f 17 00 00 je 43acf0 <__stpcpy_ssse3+0x17d0> - 4395b1: 80 79 0e 00 cmpb $0x0,0xe(%rcx) - 4395b5: 0f 84 55 17 00 00 je 43ad10 <__stpcpy_ssse3+0x17f0> - 4395bb: 80 79 0f 00 cmpb $0x0,0xf(%rcx) - 4395bf: 0f 84 db 15 00 00 je 43aba0 <__stpcpy_ssse3+0x1680> - 4395c5: 48 8d 71 10 lea 0x10(%rcx),%rsi - 4395c9: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi - 4395cd: 66 0f ef c0 pxor %xmm0,%xmm0 - 4395d1: 4c 8b 09 mov (%rcx),%r9 - 4395d4: 4c 89 0a mov %r9,(%rdx) - 4395d7: 66 0f 74 06 pcmpeqb (%rsi),%xmm0 - 4395db: 4c 8b 49 08 mov 0x8(%rcx),%r9 - 4395df: 4c 89 4a 08 mov %r9,0x8(%rdx) - 4395e3: 66 0f d7 c0 pmovmskb %xmm0,%eax - 4395e7: 48 29 ce sub %rcx,%rsi - 4395ea: 48 85 c0 test %rax,%rax - 4395ed: 0f 85 0d 15 00 00 jne 43ab00 <__stpcpy_ssse3+0x15e0> - 4395f3: 48 89 d0 mov %rdx,%rax - 4395f6: 48 8d 52 10 lea 0x10(%rdx),%rdx - 4395fa: 48 83 e2 f0 and $0xfffffffffffffff0,%rdx - 4395fe: 48 29 d0 sub %rdx,%rax - 439601: 48 29 c1 sub %rax,%rcx - 439604: 48 89 c8 mov %rcx,%rax - 439607: 48 83 e0 0f and $0xf,%rax - 43960b: 48 c7 c6 00 00 00 00 mov $0x0,%rsi - 439612: 0f 84 8e 00 00 00 je 4396a6 <__stpcpy_ssse3+0x186> - 439618: 48 83 f8 08 cmp $0x8,%rax - 43961c: 73 41 jae 43965f <__stpcpy_ssse3+0x13f> - 43961e: 48 83 f8 01 cmp $0x1,%rax - 439622: 0f 84 f8 01 00 00 je 439820 <__stpcpy_ssse3+0x300> - 439628: 48 83 f8 02 cmp $0x2,%rax - 43962c: 0f 84 2e 03 00 00 je 439960 <__stpcpy_ssse3+0x440> - 439632: 48 83 f8 03 cmp $0x3,%rax - 439636: 0f 84 64 04 00 00 je 439aa0 <__stpcpy_ssse3+0x580> - 43963c: 48 83 f8 04 cmp $0x4,%rax - 439640: 0f 84 9a 05 00 00 je 439be0 <__stpcpy_ssse3+0x6c0> - 439646: 48 83 f8 05 cmp $0x5,%rax - 43964a: 0f 84 d0 06 00 00 je 439d20 <__stpcpy_ssse3+0x800> - 439650: 48 83 f8 06 cmp $0x6,%rax - 439654: 0f 84 06 08 00 00 je 439e60 <__stpcpy_ssse3+0x940> - 43965a: e9 51 09 00 00 jmpq 439fb0 <__stpcpy_ssse3+0xa90> - 43965f: 0f 84 9b 0a 00 00 je 43a100 <__stpcpy_ssse3+0xbe0> - 439665: 48 83 f8 09 cmp $0x9,%rax - 439669: 0f 84 d1 0b 00 00 je 43a240 <__stpcpy_ssse3+0xd20> - 43966f: 48 83 f8 0a cmp $0xa,%rax - 439673: 0f 84 07 0d 00 00 je 43a380 <__stpcpy_ssse3+0xe60> - 439679: 48 83 f8 0b cmp $0xb,%rax - 43967d: 0f 84 3d 0e 00 00 je 43a4c0 <__stpcpy_ssse3+0xfa0> - 439683: 48 83 f8 0c cmp $0xc,%rax - 439687: 0f 84 73 0f 00 00 je 43a600 <__stpcpy_ssse3+0x10e0> - 43968d: 48 83 f8 0d cmp $0xd,%rax - 439691: 0f 84 a9 10 00 00 je 43a740 <__stpcpy_ssse3+0x1220> - 439697: 48 83 f8 0e cmp $0xe,%rax - 43969b: 0f 84 df 11 00 00 je 43a880 <__stpcpy_ssse3+0x1360> - 4396a1: e9 1a 13 00 00 jmpq 43a9c0 <__stpcpy_ssse3+0x14a0> - 4396a6: 0f 28 09 movaps (%rcx),%xmm1 - 4396a9: 0f 28 51 10 movaps 0x10(%rcx),%xmm2 - 4396ad: 0f 29 0a movaps %xmm1,(%rdx) - 4396b0: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 4396b4: 66 0f d7 c0 pmovmskb %xmm0,%eax - 4396b8: 48 8d 76 10 lea 0x10(%rsi),%rsi - 4396bc: 48 85 c0 test %rax,%rax - 4396bf: 0f 85 3b 14 00 00 jne 43ab00 <__stpcpy_ssse3+0x15e0> - 4396c5: 0f 28 5c 31 10 movaps 0x10(%rcx,%rsi,1),%xmm3 - 4396ca: 0f 29 14 32 movaps %xmm2,(%rdx,%rsi,1) - 4396ce: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 4396d2: 66 0f d7 c0 pmovmskb %xmm0,%eax - 4396d6: 48 8d 76 10 lea 0x10(%rsi),%rsi - 4396da: 48 85 c0 test %rax,%rax - 4396dd: 0f 85 1d 14 00 00 jne 43ab00 <__stpcpy_ssse3+0x15e0> - 4396e3: 0f 28 64 31 10 movaps 0x10(%rcx,%rsi,1),%xmm4 - 4396e8: 0f 29 1c 32 movaps %xmm3,(%rdx,%rsi,1) - 4396ec: 66 0f 74 c4 pcmpeqb %xmm4,%xmm0 - 4396f0: 66 0f d7 c0 pmovmskb %xmm0,%eax - 4396f4: 48 8d 76 10 lea 0x10(%rsi),%rsi - 4396f8: 48 85 c0 test %rax,%rax - 4396fb: 0f 85 ff 13 00 00 jne 43ab00 <__stpcpy_ssse3+0x15e0> - 439701: 0f 28 4c 31 10 movaps 0x10(%rcx,%rsi,1),%xmm1 - 439706: 0f 29 24 32 movaps %xmm4,(%rdx,%rsi,1) - 43970a: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 43970e: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439712: 48 8d 76 10 lea 0x10(%rsi),%rsi - 439716: 48 85 c0 test %rax,%rax - 439719: 0f 85 e1 13 00 00 jne 43ab00 <__stpcpy_ssse3+0x15e0> - 43971f: 0f 28 54 31 10 movaps 0x10(%rcx,%rsi,1),%xmm2 - 439724: 0f 29 0c 32 movaps %xmm1,(%rdx,%rsi,1) - 439728: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43972c: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439730: 48 8d 76 10 lea 0x10(%rsi),%rsi - 439734: 48 85 c0 test %rax,%rax - 439737: 0f 85 c3 13 00 00 jne 43ab00 <__stpcpy_ssse3+0x15e0> - 43973d: 0f 28 5c 31 10 movaps 0x10(%rcx,%rsi,1),%xmm3 - 439742: 0f 29 14 32 movaps %xmm2,(%rdx,%rsi,1) - 439746: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 43974a: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43974e: 48 8d 76 10 lea 0x10(%rsi),%rsi - 439752: 48 85 c0 test %rax,%rax - 439755: 0f 85 a5 13 00 00 jne 43ab00 <__stpcpy_ssse3+0x15e0> - 43975b: 0f 29 1c 32 movaps %xmm3,(%rdx,%rsi,1) - 43975f: 48 89 c8 mov %rcx,%rax - 439762: 48 8d 4c 31 10 lea 0x10(%rcx,%rsi,1),%rcx - 439767: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 43976b: 48 29 c8 sub %rcx,%rax - 43976e: 48 29 c2 sub %rax,%rdx - 439771: 48 c7 c6 c0 ff ff ff mov $0xffffffffffffffc0,%rsi - 439778: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 43977f: 00 - 439780: 0f 28 11 movaps (%rcx),%xmm2 - 439783: 0f 28 e2 movaps %xmm2,%xmm4 - 439786: 0f 28 69 10 movaps 0x10(%rcx),%xmm5 - 43978a: 0f 28 59 20 movaps 0x20(%rcx),%xmm3 - 43978e: 0f 28 f3 movaps %xmm3,%xmm6 - 439791: 0f 28 79 30 movaps 0x30(%rcx),%xmm7 - 439795: 66 0f da d5 pminub %xmm5,%xmm2 - 439799: 66 0f da df pminub %xmm7,%xmm3 - 43979d: 66 0f da da pminub %xmm2,%xmm3 - 4397a1: 66 0f 74 d8 pcmpeqb %xmm0,%xmm3 - 4397a5: 66 0f d7 c3 pmovmskb %xmm3,%eax - 4397a9: 48 8d 52 40 lea 0x40(%rdx),%rdx - 4397ad: 48 8d 49 40 lea 0x40(%rcx),%rcx - 4397b1: 48 85 c0 test %rax,%rax - 4397b4: 75 12 jne 4397c8 <__stpcpy_ssse3+0x2a8> - 4397b6: 0f 29 62 c0 movaps %xmm4,-0x40(%rdx) - 4397ba: 0f 29 6a d0 movaps %xmm5,-0x30(%rdx) - 4397be: 0f 29 72 e0 movaps %xmm6,-0x20(%rdx) - 4397c2: 0f 29 7a f0 movaps %xmm7,-0x10(%rdx) - 4397c6: eb b8 jmp 439780 <__stpcpy_ssse3+0x260> - 4397c8: 66 0f 74 c4 pcmpeqb %xmm4,%xmm0 - 4397cc: 66 0f d7 c0 pmovmskb %xmm0,%eax - 4397d0: 48 85 c0 test %rax,%rax - 4397d3: 0f 85 27 13 00 00 jne 43ab00 <__stpcpy_ssse3+0x15e0> - 4397d9: 66 0f 74 c5 pcmpeqb %xmm5,%xmm0 - 4397dd: 66 0f d7 c0 pmovmskb %xmm0,%eax - 4397e1: 0f 29 62 c0 movaps %xmm4,-0x40(%rdx) - 4397e5: 48 85 c0 test %rax,%rax - 4397e8: 48 8d 76 10 lea 0x10(%rsi),%rsi - 4397ec: 0f 85 0e 13 00 00 jne 43ab00 <__stpcpy_ssse3+0x15e0> - 4397f2: 66 0f 74 c6 pcmpeqb %xmm6,%xmm0 - 4397f6: 66 0f d7 c0 pmovmskb %xmm0,%eax - 4397fa: 0f 29 6a d0 movaps %xmm5,-0x30(%rdx) - 4397fe: 48 85 c0 test %rax,%rax - 439801: 48 8d 76 10 lea 0x10(%rsi),%rsi - 439805: 0f 85 f5 12 00 00 jne 43ab00 <__stpcpy_ssse3+0x15e0> - 43980b: 0f 29 72 e0 movaps %xmm6,-0x20(%rdx) - 43980f: 66 0f 74 c7 pcmpeqb %xmm7,%xmm0 - 439813: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439817: 48 8d 76 10 lea 0x10(%rsi),%rsi - 43981b: e9 e0 12 00 00 jmpq 43ab00 <__stpcpy_ssse3+0x15e0> - 439820: 0f 28 49 ff movaps -0x1(%rcx),%xmm1 - 439824: 0f 28 51 0f movaps 0xf(%rcx),%xmm2 - 439828: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43982c: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439830: 0f 28 da movaps %xmm2,%xmm3 - 439833: 48 85 c0 test %rax,%rax - 439836: 0f 85 0e 01 00 00 jne 43994a <__stpcpy_ssse3+0x42a> - 43983c: 66 0f 3a 0f d1 01 palignr $0x1,%xmm1,%xmm2 - 439842: 0f 29 12 movaps %xmm2,(%rdx) - 439845: 0f 28 51 1f movaps 0x1f(%rcx),%xmm2 - 439849: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43984d: 48 8d 52 10 lea 0x10(%rdx),%rdx - 439851: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439855: 48 8d 49 10 lea 0x10(%rcx),%rcx - 439859: 0f 28 ca movaps %xmm2,%xmm1 - 43985c: 48 85 c0 test %rax,%rax - 43985f: 0f 85 e5 00 00 00 jne 43994a <__stpcpy_ssse3+0x42a> - 439865: 66 0f 3a 0f d3 01 palignr $0x1,%xmm3,%xmm2 - 43986b: 0f 29 12 movaps %xmm2,(%rdx) - 43986e: 0f 28 51 1f movaps 0x1f(%rcx),%xmm2 - 439872: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 439876: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43987a: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43987e: 48 8d 49 10 lea 0x10(%rcx),%rcx - 439882: 0f 28 da movaps %xmm2,%xmm3 - 439885: 48 85 c0 test %rax,%rax - 439888: 0f 85 bc 00 00 00 jne 43994a <__stpcpy_ssse3+0x42a> - 43988e: 66 0f 3a 0f d1 01 palignr $0x1,%xmm1,%xmm2 - 439894: 0f 29 12 movaps %xmm2,(%rdx) - 439897: 0f 28 51 1f movaps 0x1f(%rcx),%xmm2 - 43989b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43989f: 48 8d 52 10 lea 0x10(%rdx),%rdx - 4398a3: 66 0f d7 c0 pmovmskb %xmm0,%eax - 4398a7: 48 8d 49 10 lea 0x10(%rcx),%rcx - 4398ab: 48 85 c0 test %rax,%rax - 4398ae: 0f 85 96 00 00 00 jne 43994a <__stpcpy_ssse3+0x42a> - 4398b4: 66 0f 3a 0f d3 01 palignr $0x1,%xmm3,%xmm2 - 4398ba: 0f 29 12 movaps %xmm2,(%rdx) - 4398bd: 48 8d 49 1f lea 0x1f(%rcx),%rcx - 4398c1: 48 8d 52 10 lea 0x10(%rdx),%rdx - 4398c5: 48 89 c8 mov %rcx,%rax - 4398c8: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 4398cc: 48 29 c8 sub %rcx,%rax - 4398cf: 48 8d 49 f1 lea -0xf(%rcx),%rcx - 4398d3: 48 29 c2 sub %rax,%rdx - 4398d6: 0f 28 49 ff movaps -0x1(%rcx),%xmm1 - 4398da: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4398e0: 0f 28 51 0f movaps 0xf(%rcx),%xmm2 - 4398e4: 0f 28 59 1f movaps 0x1f(%rcx),%xmm3 - 4398e8: 0f 28 f3 movaps %xmm3,%xmm6 - 4398eb: 0f 28 61 2f movaps 0x2f(%rcx),%xmm4 - 4398ef: 0f 28 fc movaps %xmm4,%xmm7 - 4398f2: 0f 28 69 3f movaps 0x3f(%rcx),%xmm5 - 4398f6: 66 0f da f2 pminub %xmm2,%xmm6 - 4398fa: 66 0f da fd pminub %xmm5,%xmm7 - 4398fe: 66 0f da fe pminub %xmm6,%xmm7 - 439902: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 439906: 66 0f d7 c7 pmovmskb %xmm7,%eax - 43990a: 0f 28 fd movaps %xmm5,%xmm7 - 43990d: 66 0f 3a 0f ec 01 palignr $0x1,%xmm4,%xmm5 - 439913: 48 85 c0 test %rax,%rax - 439916: 66 0f 3a 0f e3 01 palignr $0x1,%xmm3,%xmm4 - 43991c: 0f 85 06 ff ff ff jne 439828 <__stpcpy_ssse3+0x308> - 439922: 66 0f 3a 0f da 01 palignr $0x1,%xmm2,%xmm3 - 439928: 48 8d 49 40 lea 0x40(%rcx),%rcx - 43992c: 66 0f 3a 0f d1 01 palignr $0x1,%xmm1,%xmm2 - 439932: 0f 28 cf movaps %xmm7,%xmm1 - 439935: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) - 439939: 0f 29 62 20 movaps %xmm4,0x20(%rdx) - 43993d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) - 439941: 0f 29 12 movaps %xmm2,(%rdx) - 439944: 48 8d 52 40 lea 0x40(%rdx),%rdx - 439948: eb 96 jmp 4398e0 <__stpcpy_ssse3+0x3c0> - 43994a: f3 0f 6f 49 ff movdqu -0x1(%rcx),%xmm1 - 43994f: 48 c7 c6 0f 00 00 00 mov $0xf,%rsi - 439956: f3 0f 7f 4a ff movdqu %xmm1,-0x1(%rdx) - 43995b: e9 a0 11 00 00 jmpq 43ab00 <__stpcpy_ssse3+0x15e0> - 439960: 0f 28 49 fe movaps -0x2(%rcx),%xmm1 - 439964: 0f 28 51 0e movaps 0xe(%rcx),%xmm2 - 439968: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43996c: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439970: 0f 28 da movaps %xmm2,%xmm3 - 439973: 48 85 c0 test %rax,%rax - 439976: 0f 85 0e 01 00 00 jne 439a8a <__stpcpy_ssse3+0x56a> - 43997c: 66 0f 3a 0f d1 02 palignr $0x2,%xmm1,%xmm2 - 439982: 0f 29 12 movaps %xmm2,(%rdx) - 439985: 0f 28 51 1e movaps 0x1e(%rcx),%xmm2 - 439989: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43998d: 48 8d 52 10 lea 0x10(%rdx),%rdx - 439991: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439995: 48 8d 49 10 lea 0x10(%rcx),%rcx - 439999: 0f 28 ca movaps %xmm2,%xmm1 - 43999c: 48 85 c0 test %rax,%rax - 43999f: 0f 85 e5 00 00 00 jne 439a8a <__stpcpy_ssse3+0x56a> - 4399a5: 66 0f 3a 0f d3 02 palignr $0x2,%xmm3,%xmm2 - 4399ab: 0f 29 12 movaps %xmm2,(%rdx) - 4399ae: 0f 28 51 1e movaps 0x1e(%rcx),%xmm2 - 4399b2: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 4399b6: 48 8d 52 10 lea 0x10(%rdx),%rdx - 4399ba: 66 0f d7 c0 pmovmskb %xmm0,%eax - 4399be: 48 8d 49 10 lea 0x10(%rcx),%rcx - 4399c2: 0f 28 da movaps %xmm2,%xmm3 - 4399c5: 48 85 c0 test %rax,%rax - 4399c8: 0f 85 bc 00 00 00 jne 439a8a <__stpcpy_ssse3+0x56a> - 4399ce: 66 0f 3a 0f d1 02 palignr $0x2,%xmm1,%xmm2 - 4399d4: 0f 29 12 movaps %xmm2,(%rdx) - 4399d7: 0f 28 51 1e movaps 0x1e(%rcx),%xmm2 - 4399db: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 4399df: 48 8d 52 10 lea 0x10(%rdx),%rdx - 4399e3: 66 0f d7 c0 pmovmskb %xmm0,%eax - 4399e7: 48 8d 49 10 lea 0x10(%rcx),%rcx - 4399eb: 48 85 c0 test %rax,%rax - 4399ee: 0f 85 96 00 00 00 jne 439a8a <__stpcpy_ssse3+0x56a> - 4399f4: 66 0f 3a 0f d3 02 palignr $0x2,%xmm3,%xmm2 - 4399fa: 0f 29 12 movaps %xmm2,(%rdx) - 4399fd: 48 8d 49 1e lea 0x1e(%rcx),%rcx - 439a01: 48 8d 52 10 lea 0x10(%rdx),%rdx - 439a05: 48 89 c8 mov %rcx,%rax - 439a08: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 439a0c: 48 29 c8 sub %rcx,%rax - 439a0f: 48 8d 49 f2 lea -0xe(%rcx),%rcx - 439a13: 48 29 c2 sub %rax,%rdx - 439a16: 0f 28 49 fe movaps -0x2(%rcx),%xmm1 - 439a1a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 439a20: 0f 28 51 0e movaps 0xe(%rcx),%xmm2 - 439a24: 0f 28 59 1e movaps 0x1e(%rcx),%xmm3 - 439a28: 0f 28 f3 movaps %xmm3,%xmm6 - 439a2b: 0f 28 61 2e movaps 0x2e(%rcx),%xmm4 - 439a2f: 0f 28 fc movaps %xmm4,%xmm7 - 439a32: 0f 28 69 3e movaps 0x3e(%rcx),%xmm5 - 439a36: 66 0f da f2 pminub %xmm2,%xmm6 - 439a3a: 66 0f da fd pminub %xmm5,%xmm7 - 439a3e: 66 0f da fe pminub %xmm6,%xmm7 - 439a42: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 439a46: 66 0f d7 c7 pmovmskb %xmm7,%eax - 439a4a: 0f 28 fd movaps %xmm5,%xmm7 - 439a4d: 66 0f 3a 0f ec 02 palignr $0x2,%xmm4,%xmm5 - 439a53: 48 85 c0 test %rax,%rax - 439a56: 66 0f 3a 0f e3 02 palignr $0x2,%xmm3,%xmm4 - 439a5c: 0f 85 06 ff ff ff jne 439968 <__stpcpy_ssse3+0x448> - 439a62: 66 0f 3a 0f da 02 palignr $0x2,%xmm2,%xmm3 - 439a68: 48 8d 49 40 lea 0x40(%rcx),%rcx - 439a6c: 66 0f 3a 0f d1 02 palignr $0x2,%xmm1,%xmm2 - 439a72: 0f 28 cf movaps %xmm7,%xmm1 - 439a75: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) - 439a79: 0f 29 62 20 movaps %xmm4,0x20(%rdx) - 439a7d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) - 439a81: 0f 29 12 movaps %xmm2,(%rdx) - 439a84: 48 8d 52 40 lea 0x40(%rdx),%rdx - 439a88: eb 96 jmp 439a20 <__stpcpy_ssse3+0x500> - 439a8a: f3 0f 6f 49 fe movdqu -0x2(%rcx),%xmm1 - 439a8f: 48 c7 c6 0e 00 00 00 mov $0xe,%rsi - 439a96: f3 0f 7f 4a fe movdqu %xmm1,-0x2(%rdx) - 439a9b: e9 60 10 00 00 jmpq 43ab00 <__stpcpy_ssse3+0x15e0> - 439aa0: 0f 28 49 fd movaps -0x3(%rcx),%xmm1 - 439aa4: 0f 28 51 0d movaps 0xd(%rcx),%xmm2 - 439aa8: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 439aac: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439ab0: 0f 28 da movaps %xmm2,%xmm3 - 439ab3: 48 85 c0 test %rax,%rax - 439ab6: 0f 85 0e 01 00 00 jne 439bca <__stpcpy_ssse3+0x6aa> - 439abc: 66 0f 3a 0f d1 03 palignr $0x3,%xmm1,%xmm2 - 439ac2: 0f 29 12 movaps %xmm2,(%rdx) - 439ac5: 0f 28 51 1d movaps 0x1d(%rcx),%xmm2 - 439ac9: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 439acd: 48 8d 52 10 lea 0x10(%rdx),%rdx - 439ad1: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439ad5: 48 8d 49 10 lea 0x10(%rcx),%rcx - 439ad9: 0f 28 ca movaps %xmm2,%xmm1 - 439adc: 48 85 c0 test %rax,%rax - 439adf: 0f 85 e5 00 00 00 jne 439bca <__stpcpy_ssse3+0x6aa> - 439ae5: 66 0f 3a 0f d3 03 palignr $0x3,%xmm3,%xmm2 - 439aeb: 0f 29 12 movaps %xmm2,(%rdx) - 439aee: 0f 28 51 1d movaps 0x1d(%rcx),%xmm2 - 439af2: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 439af6: 48 8d 52 10 lea 0x10(%rdx),%rdx - 439afa: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439afe: 48 8d 49 10 lea 0x10(%rcx),%rcx - 439b02: 0f 28 da movaps %xmm2,%xmm3 - 439b05: 48 85 c0 test %rax,%rax - 439b08: 0f 85 bc 00 00 00 jne 439bca <__stpcpy_ssse3+0x6aa> - 439b0e: 66 0f 3a 0f d1 03 palignr $0x3,%xmm1,%xmm2 - 439b14: 0f 29 12 movaps %xmm2,(%rdx) - 439b17: 0f 28 51 1d movaps 0x1d(%rcx),%xmm2 - 439b1b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 439b1f: 48 8d 52 10 lea 0x10(%rdx),%rdx - 439b23: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439b27: 48 8d 49 10 lea 0x10(%rcx),%rcx - 439b2b: 48 85 c0 test %rax,%rax - 439b2e: 0f 85 96 00 00 00 jne 439bca <__stpcpy_ssse3+0x6aa> - 439b34: 66 0f 3a 0f d3 03 palignr $0x3,%xmm3,%xmm2 - 439b3a: 0f 29 12 movaps %xmm2,(%rdx) - 439b3d: 48 8d 49 1d lea 0x1d(%rcx),%rcx - 439b41: 48 8d 52 10 lea 0x10(%rdx),%rdx - 439b45: 48 89 c8 mov %rcx,%rax - 439b48: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 439b4c: 48 29 c8 sub %rcx,%rax - 439b4f: 48 8d 49 f3 lea -0xd(%rcx),%rcx - 439b53: 48 29 c2 sub %rax,%rdx - 439b56: 0f 28 49 fd movaps -0x3(%rcx),%xmm1 - 439b5a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 439b60: 0f 28 51 0d movaps 0xd(%rcx),%xmm2 - 439b64: 0f 28 59 1d movaps 0x1d(%rcx),%xmm3 - 439b68: 0f 28 f3 movaps %xmm3,%xmm6 - 439b6b: 0f 28 61 2d movaps 0x2d(%rcx),%xmm4 - 439b6f: 0f 28 fc movaps %xmm4,%xmm7 - 439b72: 0f 28 69 3d movaps 0x3d(%rcx),%xmm5 - 439b76: 66 0f da f2 pminub %xmm2,%xmm6 - 439b7a: 66 0f da fd pminub %xmm5,%xmm7 - 439b7e: 66 0f da fe pminub %xmm6,%xmm7 - 439b82: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 439b86: 66 0f d7 c7 pmovmskb %xmm7,%eax - 439b8a: 0f 28 fd movaps %xmm5,%xmm7 - 439b8d: 66 0f 3a 0f ec 03 palignr $0x3,%xmm4,%xmm5 - 439b93: 48 85 c0 test %rax,%rax - 439b96: 66 0f 3a 0f e3 03 palignr $0x3,%xmm3,%xmm4 - 439b9c: 0f 85 06 ff ff ff jne 439aa8 <__stpcpy_ssse3+0x588> - 439ba2: 66 0f 3a 0f da 03 palignr $0x3,%xmm2,%xmm3 - 439ba8: 48 8d 49 40 lea 0x40(%rcx),%rcx - 439bac: 66 0f 3a 0f d1 03 palignr $0x3,%xmm1,%xmm2 - 439bb2: 0f 28 cf movaps %xmm7,%xmm1 - 439bb5: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) - 439bb9: 0f 29 62 20 movaps %xmm4,0x20(%rdx) - 439bbd: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) - 439bc1: 0f 29 12 movaps %xmm2,(%rdx) - 439bc4: 48 8d 52 40 lea 0x40(%rdx),%rdx - 439bc8: eb 96 jmp 439b60 <__stpcpy_ssse3+0x640> - 439bca: f3 0f 6f 49 fd movdqu -0x3(%rcx),%xmm1 - 439bcf: 48 c7 c6 0d 00 00 00 mov $0xd,%rsi - 439bd6: f3 0f 7f 4a fd movdqu %xmm1,-0x3(%rdx) - 439bdb: e9 20 0f 00 00 jmpq 43ab00 <__stpcpy_ssse3+0x15e0> - 439be0: 0f 28 49 fc movaps -0x4(%rcx),%xmm1 - 439be4: 0f 28 51 0c movaps 0xc(%rcx),%xmm2 - 439be8: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 439bec: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439bf0: 0f 28 da movaps %xmm2,%xmm3 - 439bf3: 48 85 c0 test %rax,%rax - 439bf6: 0f 85 0e 01 00 00 jne 439d0a <__stpcpy_ssse3+0x7ea> - 439bfc: 66 0f 3a 0f d1 04 palignr $0x4,%xmm1,%xmm2 - 439c02: 0f 29 12 movaps %xmm2,(%rdx) - 439c05: 0f 28 51 1c movaps 0x1c(%rcx),%xmm2 - 439c09: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 439c0d: 48 8d 52 10 lea 0x10(%rdx),%rdx - 439c11: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439c15: 48 8d 49 10 lea 0x10(%rcx),%rcx - 439c19: 0f 28 ca movaps %xmm2,%xmm1 - 439c1c: 48 85 c0 test %rax,%rax - 439c1f: 0f 85 e5 00 00 00 jne 439d0a <__stpcpy_ssse3+0x7ea> - 439c25: 66 0f 3a 0f d3 04 palignr $0x4,%xmm3,%xmm2 - 439c2b: 0f 29 12 movaps %xmm2,(%rdx) - 439c2e: 0f 28 51 1c movaps 0x1c(%rcx),%xmm2 - 439c32: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 439c36: 48 8d 52 10 lea 0x10(%rdx),%rdx - 439c3a: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439c3e: 48 8d 49 10 lea 0x10(%rcx),%rcx - 439c42: 0f 28 da movaps %xmm2,%xmm3 - 439c45: 48 85 c0 test %rax,%rax - 439c48: 0f 85 bc 00 00 00 jne 439d0a <__stpcpy_ssse3+0x7ea> - 439c4e: 66 0f 3a 0f d1 04 palignr $0x4,%xmm1,%xmm2 - 439c54: 0f 29 12 movaps %xmm2,(%rdx) - 439c57: 0f 28 51 1c movaps 0x1c(%rcx),%xmm2 - 439c5b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 439c5f: 48 8d 52 10 lea 0x10(%rdx),%rdx - 439c63: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439c67: 48 8d 49 10 lea 0x10(%rcx),%rcx - 439c6b: 48 85 c0 test %rax,%rax - 439c6e: 0f 85 96 00 00 00 jne 439d0a <__stpcpy_ssse3+0x7ea> - 439c74: 66 0f 3a 0f d3 04 palignr $0x4,%xmm3,%xmm2 - 439c7a: 0f 29 12 movaps %xmm2,(%rdx) - 439c7d: 48 8d 49 1c lea 0x1c(%rcx),%rcx - 439c81: 48 8d 52 10 lea 0x10(%rdx),%rdx - 439c85: 48 89 c8 mov %rcx,%rax - 439c88: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 439c8c: 48 29 c8 sub %rcx,%rax - 439c8f: 48 8d 49 f4 lea -0xc(%rcx),%rcx - 439c93: 48 29 c2 sub %rax,%rdx - 439c96: 0f 28 49 fc movaps -0x4(%rcx),%xmm1 - 439c9a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 439ca0: 0f 28 51 0c movaps 0xc(%rcx),%xmm2 - 439ca4: 0f 28 59 1c movaps 0x1c(%rcx),%xmm3 - 439ca8: 0f 28 f3 movaps %xmm3,%xmm6 - 439cab: 0f 28 61 2c movaps 0x2c(%rcx),%xmm4 - 439caf: 0f 28 fc movaps %xmm4,%xmm7 - 439cb2: 0f 28 69 3c movaps 0x3c(%rcx),%xmm5 - 439cb6: 66 0f da f2 pminub %xmm2,%xmm6 - 439cba: 66 0f da fd pminub %xmm5,%xmm7 - 439cbe: 66 0f da fe pminub %xmm6,%xmm7 - 439cc2: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 439cc6: 66 0f d7 c7 pmovmskb %xmm7,%eax - 439cca: 0f 28 fd movaps %xmm5,%xmm7 - 439ccd: 66 0f 3a 0f ec 04 palignr $0x4,%xmm4,%xmm5 - 439cd3: 48 85 c0 test %rax,%rax - 439cd6: 66 0f 3a 0f e3 04 palignr $0x4,%xmm3,%xmm4 - 439cdc: 0f 85 06 ff ff ff jne 439be8 <__stpcpy_ssse3+0x6c8> - 439ce2: 66 0f 3a 0f da 04 palignr $0x4,%xmm2,%xmm3 - 439ce8: 48 8d 49 40 lea 0x40(%rcx),%rcx - 439cec: 66 0f 3a 0f d1 04 palignr $0x4,%xmm1,%xmm2 - 439cf2: 0f 28 cf movaps %xmm7,%xmm1 - 439cf5: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) - 439cf9: 0f 29 62 20 movaps %xmm4,0x20(%rdx) - 439cfd: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) - 439d01: 0f 29 12 movaps %xmm2,(%rdx) - 439d04: 48 8d 52 40 lea 0x40(%rdx),%rdx - 439d08: eb 96 jmp 439ca0 <__stpcpy_ssse3+0x780> - 439d0a: f3 0f 6f 49 fc movdqu -0x4(%rcx),%xmm1 - 439d0f: 48 c7 c6 0c 00 00 00 mov $0xc,%rsi - 439d16: f3 0f 7f 4a fc movdqu %xmm1,-0x4(%rdx) - 439d1b: e9 e0 0d 00 00 jmpq 43ab00 <__stpcpy_ssse3+0x15e0> - 439d20: 0f 28 49 fb movaps -0x5(%rcx),%xmm1 - 439d24: 0f 28 51 0b movaps 0xb(%rcx),%xmm2 - 439d28: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 439d2c: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439d30: 0f 28 da movaps %xmm2,%xmm3 - 439d33: 48 85 c0 test %rax,%rax - 439d36: 0f 85 0e 01 00 00 jne 439e4a <__stpcpy_ssse3+0x92a> - 439d3c: 66 0f 3a 0f d1 05 palignr $0x5,%xmm1,%xmm2 - 439d42: 0f 29 12 movaps %xmm2,(%rdx) - 439d45: 0f 28 51 1b movaps 0x1b(%rcx),%xmm2 - 439d49: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 439d4d: 48 8d 52 10 lea 0x10(%rdx),%rdx - 439d51: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439d55: 48 8d 49 10 lea 0x10(%rcx),%rcx - 439d59: 0f 28 ca movaps %xmm2,%xmm1 - 439d5c: 48 85 c0 test %rax,%rax - 439d5f: 0f 85 e5 00 00 00 jne 439e4a <__stpcpy_ssse3+0x92a> - 439d65: 66 0f 3a 0f d3 05 palignr $0x5,%xmm3,%xmm2 - 439d6b: 0f 29 12 movaps %xmm2,(%rdx) - 439d6e: 0f 28 51 1b movaps 0x1b(%rcx),%xmm2 - 439d72: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 439d76: 48 8d 52 10 lea 0x10(%rdx),%rdx - 439d7a: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439d7e: 48 8d 49 10 lea 0x10(%rcx),%rcx - 439d82: 0f 28 da movaps %xmm2,%xmm3 - 439d85: 48 85 c0 test %rax,%rax - 439d88: 0f 85 bc 00 00 00 jne 439e4a <__stpcpy_ssse3+0x92a> - 439d8e: 66 0f 3a 0f d1 05 palignr $0x5,%xmm1,%xmm2 - 439d94: 0f 29 12 movaps %xmm2,(%rdx) - 439d97: 0f 28 51 1b movaps 0x1b(%rcx),%xmm2 - 439d9b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 439d9f: 48 8d 52 10 lea 0x10(%rdx),%rdx - 439da3: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439da7: 48 8d 49 10 lea 0x10(%rcx),%rcx - 439dab: 48 85 c0 test %rax,%rax - 439dae: 0f 85 96 00 00 00 jne 439e4a <__stpcpy_ssse3+0x92a> - 439db4: 66 0f 3a 0f d3 05 palignr $0x5,%xmm3,%xmm2 - 439dba: 0f 29 12 movaps %xmm2,(%rdx) - 439dbd: 48 8d 49 1b lea 0x1b(%rcx),%rcx - 439dc1: 48 8d 52 10 lea 0x10(%rdx),%rdx - 439dc5: 48 89 c8 mov %rcx,%rax - 439dc8: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 439dcc: 48 29 c8 sub %rcx,%rax - 439dcf: 48 8d 49 f5 lea -0xb(%rcx),%rcx - 439dd3: 48 29 c2 sub %rax,%rdx - 439dd6: 0f 28 49 fb movaps -0x5(%rcx),%xmm1 - 439dda: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 439de0: 0f 28 51 0b movaps 0xb(%rcx),%xmm2 - 439de4: 0f 28 59 1b movaps 0x1b(%rcx),%xmm3 - 439de8: 0f 28 f3 movaps %xmm3,%xmm6 - 439deb: 0f 28 61 2b movaps 0x2b(%rcx),%xmm4 - 439def: 0f 28 fc movaps %xmm4,%xmm7 - 439df2: 0f 28 69 3b movaps 0x3b(%rcx),%xmm5 - 439df6: 66 0f da f2 pminub %xmm2,%xmm6 - 439dfa: 66 0f da fd pminub %xmm5,%xmm7 - 439dfe: 66 0f da fe pminub %xmm6,%xmm7 - 439e02: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 439e06: 66 0f d7 c7 pmovmskb %xmm7,%eax - 439e0a: 0f 28 fd movaps %xmm5,%xmm7 - 439e0d: 66 0f 3a 0f ec 05 palignr $0x5,%xmm4,%xmm5 - 439e13: 48 85 c0 test %rax,%rax - 439e16: 66 0f 3a 0f e3 05 palignr $0x5,%xmm3,%xmm4 - 439e1c: 0f 85 06 ff ff ff jne 439d28 <__stpcpy_ssse3+0x808> - 439e22: 66 0f 3a 0f da 05 palignr $0x5,%xmm2,%xmm3 - 439e28: 48 8d 49 40 lea 0x40(%rcx),%rcx - 439e2c: 66 0f 3a 0f d1 05 palignr $0x5,%xmm1,%xmm2 - 439e32: 0f 28 cf movaps %xmm7,%xmm1 - 439e35: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) - 439e39: 0f 29 62 20 movaps %xmm4,0x20(%rdx) - 439e3d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) - 439e41: 0f 29 12 movaps %xmm2,(%rdx) - 439e44: 48 8d 52 40 lea 0x40(%rdx),%rdx - 439e48: eb 96 jmp 439de0 <__stpcpy_ssse3+0x8c0> - 439e4a: f3 0f 6f 49 fb movdqu -0x5(%rcx),%xmm1 - 439e4f: 48 c7 c6 0b 00 00 00 mov $0xb,%rsi - 439e56: f3 0f 7f 4a fb movdqu %xmm1,-0x5(%rdx) - 439e5b: e9 a0 0c 00 00 jmpq 43ab00 <__stpcpy_ssse3+0x15e0> - 439e60: 0f 28 49 fa movaps -0x6(%rcx),%xmm1 - 439e64: 0f 28 51 0a movaps 0xa(%rcx),%xmm2 - 439e68: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 439e6c: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439e70: 0f 28 da movaps %xmm2,%xmm3 - 439e73: 48 85 c0 test %rax,%rax - 439e76: 0f 85 0e 01 00 00 jne 439f8a <__stpcpy_ssse3+0xa6a> - 439e7c: 66 0f 3a 0f d1 06 palignr $0x6,%xmm1,%xmm2 - 439e82: 0f 29 12 movaps %xmm2,(%rdx) - 439e85: 0f 28 51 1a movaps 0x1a(%rcx),%xmm2 - 439e89: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 439e8d: 48 8d 52 10 lea 0x10(%rdx),%rdx - 439e91: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439e95: 48 8d 49 10 lea 0x10(%rcx),%rcx - 439e99: 0f 28 ca movaps %xmm2,%xmm1 - 439e9c: 48 85 c0 test %rax,%rax - 439e9f: 0f 85 e5 00 00 00 jne 439f8a <__stpcpy_ssse3+0xa6a> - 439ea5: 66 0f 3a 0f d3 06 palignr $0x6,%xmm3,%xmm2 - 439eab: 0f 29 12 movaps %xmm2,(%rdx) - 439eae: 0f 28 51 1a movaps 0x1a(%rcx),%xmm2 - 439eb2: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 439eb6: 48 8d 52 10 lea 0x10(%rdx),%rdx - 439eba: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439ebe: 48 8d 49 10 lea 0x10(%rcx),%rcx - 439ec2: 0f 28 da movaps %xmm2,%xmm3 - 439ec5: 48 85 c0 test %rax,%rax - 439ec8: 0f 85 bc 00 00 00 jne 439f8a <__stpcpy_ssse3+0xa6a> - 439ece: 66 0f 3a 0f d1 06 palignr $0x6,%xmm1,%xmm2 - 439ed4: 0f 29 12 movaps %xmm2,(%rdx) - 439ed7: 0f 28 51 1a movaps 0x1a(%rcx),%xmm2 - 439edb: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 439edf: 48 8d 52 10 lea 0x10(%rdx),%rdx - 439ee3: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439ee7: 48 8d 49 10 lea 0x10(%rcx),%rcx - 439eeb: 48 85 c0 test %rax,%rax - 439eee: 0f 85 96 00 00 00 jne 439f8a <__stpcpy_ssse3+0xa6a> - 439ef4: 66 0f 3a 0f d3 06 palignr $0x6,%xmm3,%xmm2 - 439efa: 0f 29 12 movaps %xmm2,(%rdx) - 439efd: 48 8d 49 1a lea 0x1a(%rcx),%rcx - 439f01: 48 8d 52 10 lea 0x10(%rdx),%rdx - 439f05: 48 89 c8 mov %rcx,%rax - 439f08: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 439f0c: 48 29 c8 sub %rcx,%rax - 439f0f: 48 8d 49 f6 lea -0xa(%rcx),%rcx - 439f13: 48 29 c2 sub %rax,%rdx - 439f16: 0f 28 49 fa movaps -0x6(%rcx),%xmm1 - 439f1a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 439f20: 0f 28 51 0a movaps 0xa(%rcx),%xmm2 - 439f24: 0f 28 59 1a movaps 0x1a(%rcx),%xmm3 - 439f28: 0f 28 f3 movaps %xmm3,%xmm6 - 439f2b: 0f 28 61 2a movaps 0x2a(%rcx),%xmm4 - 439f2f: 0f 28 fc movaps %xmm4,%xmm7 - 439f32: 0f 28 69 3a movaps 0x3a(%rcx),%xmm5 - 439f36: 66 0f da f2 pminub %xmm2,%xmm6 - 439f3a: 66 0f da fd pminub %xmm5,%xmm7 - 439f3e: 66 0f da fe pminub %xmm6,%xmm7 - 439f42: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 439f46: 66 0f d7 c7 pmovmskb %xmm7,%eax - 439f4a: 0f 28 fd movaps %xmm5,%xmm7 - 439f4d: 66 0f 3a 0f ec 06 palignr $0x6,%xmm4,%xmm5 - 439f53: 48 85 c0 test %rax,%rax - 439f56: 66 0f 3a 0f e3 06 palignr $0x6,%xmm3,%xmm4 - 439f5c: 0f 85 06 ff ff ff jne 439e68 <__stpcpy_ssse3+0x948> - 439f62: 66 0f 3a 0f da 06 palignr $0x6,%xmm2,%xmm3 - 439f68: 48 8d 49 40 lea 0x40(%rcx),%rcx - 439f6c: 66 0f 3a 0f d1 06 palignr $0x6,%xmm1,%xmm2 - 439f72: 0f 28 cf movaps %xmm7,%xmm1 - 439f75: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) - 439f79: 0f 29 62 20 movaps %xmm4,0x20(%rdx) - 439f7d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) - 439f81: 0f 29 12 movaps %xmm2,(%rdx) - 439f84: 48 8d 52 40 lea 0x40(%rdx),%rdx - 439f88: eb 96 jmp 439f20 <__stpcpy_ssse3+0xa00> - 439f8a: 4c 8b 09 mov (%rcx),%r9 - 439f8d: 8b 71 06 mov 0x6(%rcx),%esi - 439f90: 4c 89 0a mov %r9,(%rdx) - 439f93: 89 72 06 mov %esi,0x6(%rdx) - 439f96: 48 c7 c6 0a 00 00 00 mov $0xa,%rsi - 439f9d: e9 5e 0b 00 00 jmpq 43ab00 <__stpcpy_ssse3+0x15e0> - 439fa2: 0f 1f 40 00 nopl 0x0(%rax) - 439fa6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 439fad: 00 00 00 - 439fb0: 0f 28 49 f9 movaps -0x7(%rcx),%xmm1 - 439fb4: 0f 28 51 09 movaps 0x9(%rcx),%xmm2 - 439fb8: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 439fbc: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439fc0: 0f 28 da movaps %xmm2,%xmm3 - 439fc3: 48 85 c0 test %rax,%rax - 439fc6: 0f 85 0e 01 00 00 jne 43a0da <__stpcpy_ssse3+0xbba> - 439fcc: 66 0f 3a 0f d1 07 palignr $0x7,%xmm1,%xmm2 - 439fd2: 0f 29 12 movaps %xmm2,(%rdx) - 439fd5: 0f 28 51 19 movaps 0x19(%rcx),%xmm2 - 439fd9: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 439fdd: 48 8d 52 10 lea 0x10(%rdx),%rdx - 439fe1: 66 0f d7 c0 pmovmskb %xmm0,%eax - 439fe5: 48 8d 49 10 lea 0x10(%rcx),%rcx - 439fe9: 0f 28 ca movaps %xmm2,%xmm1 - 439fec: 48 85 c0 test %rax,%rax - 439fef: 0f 85 e5 00 00 00 jne 43a0da <__stpcpy_ssse3+0xbba> - 439ff5: 66 0f 3a 0f d3 07 palignr $0x7,%xmm3,%xmm2 - 439ffb: 0f 29 12 movaps %xmm2,(%rdx) - 439ffe: 0f 28 51 19 movaps 0x19(%rcx),%xmm2 - 43a002: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a006: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a00a: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a00e: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43a012: 0f 28 da movaps %xmm2,%xmm3 - 43a015: 48 85 c0 test %rax,%rax - 43a018: 0f 85 bc 00 00 00 jne 43a0da <__stpcpy_ssse3+0xbba> - 43a01e: 66 0f 3a 0f d1 07 palignr $0x7,%xmm1,%xmm2 - 43a024: 0f 29 12 movaps %xmm2,(%rdx) - 43a027: 0f 28 51 19 movaps 0x19(%rcx),%xmm2 - 43a02b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a02f: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a033: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a037: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43a03b: 48 85 c0 test %rax,%rax - 43a03e: 0f 85 96 00 00 00 jne 43a0da <__stpcpy_ssse3+0xbba> - 43a044: 66 0f 3a 0f d3 07 palignr $0x7,%xmm3,%xmm2 - 43a04a: 0f 29 12 movaps %xmm2,(%rdx) - 43a04d: 48 8d 49 19 lea 0x19(%rcx),%rcx - 43a051: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a055: 48 89 c8 mov %rcx,%rax - 43a058: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 43a05c: 48 29 c8 sub %rcx,%rax - 43a05f: 48 8d 49 f7 lea -0x9(%rcx),%rcx - 43a063: 48 29 c2 sub %rax,%rdx - 43a066: 0f 28 49 f9 movaps -0x7(%rcx),%xmm1 - 43a06a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43a070: 0f 28 51 09 movaps 0x9(%rcx),%xmm2 - 43a074: 0f 28 59 19 movaps 0x19(%rcx),%xmm3 - 43a078: 0f 28 f3 movaps %xmm3,%xmm6 - 43a07b: 0f 28 61 29 movaps 0x29(%rcx),%xmm4 - 43a07f: 0f 28 fc movaps %xmm4,%xmm7 - 43a082: 0f 28 69 39 movaps 0x39(%rcx),%xmm5 - 43a086: 66 0f da f2 pminub %xmm2,%xmm6 - 43a08a: 66 0f da fd pminub %xmm5,%xmm7 - 43a08e: 66 0f da fe pminub %xmm6,%xmm7 - 43a092: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 43a096: 66 0f d7 c7 pmovmskb %xmm7,%eax - 43a09a: 0f 28 fd movaps %xmm5,%xmm7 - 43a09d: 66 0f 3a 0f ec 07 palignr $0x7,%xmm4,%xmm5 - 43a0a3: 48 85 c0 test %rax,%rax - 43a0a6: 66 0f 3a 0f e3 07 palignr $0x7,%xmm3,%xmm4 - 43a0ac: 0f 85 06 ff ff ff jne 439fb8 <__stpcpy_ssse3+0xa98> - 43a0b2: 66 0f 3a 0f da 07 palignr $0x7,%xmm2,%xmm3 - 43a0b8: 48 8d 49 40 lea 0x40(%rcx),%rcx - 43a0bc: 66 0f 3a 0f d1 07 palignr $0x7,%xmm1,%xmm2 - 43a0c2: 0f 28 cf movaps %xmm7,%xmm1 - 43a0c5: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) - 43a0c9: 0f 29 62 20 movaps %xmm4,0x20(%rdx) - 43a0cd: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) - 43a0d1: 0f 29 12 movaps %xmm2,(%rdx) - 43a0d4: 48 8d 52 40 lea 0x40(%rdx),%rdx - 43a0d8: eb 96 jmp 43a070 <__stpcpy_ssse3+0xb50> - 43a0da: 4c 8b 09 mov (%rcx),%r9 - 43a0dd: 8b 71 05 mov 0x5(%rcx),%esi - 43a0e0: 4c 89 0a mov %r9,(%rdx) - 43a0e3: 89 72 05 mov %esi,0x5(%rdx) - 43a0e6: 48 c7 c6 09 00 00 00 mov $0x9,%rsi - 43a0ed: e9 0e 0a 00 00 jmpq 43ab00 <__stpcpy_ssse3+0x15e0> - 43a0f2: 0f 1f 40 00 nopl 0x0(%rax) - 43a0f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43a0fd: 00 00 00 - 43a100: 0f 28 49 f8 movaps -0x8(%rcx),%xmm1 - 43a104: 0f 28 51 08 movaps 0x8(%rcx),%xmm2 - 43a108: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a10c: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a110: 0f 28 da movaps %xmm2,%xmm3 - 43a113: 48 85 c0 test %rax,%rax - 43a116: 0f 85 0e 01 00 00 jne 43a22a <__stpcpy_ssse3+0xd0a> - 43a11c: 66 0f 3a 0f d1 08 palignr $0x8,%xmm1,%xmm2 - 43a122: 0f 29 12 movaps %xmm2,(%rdx) - 43a125: 0f 28 51 18 movaps 0x18(%rcx),%xmm2 - 43a129: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a12d: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a131: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a135: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43a139: 0f 28 ca movaps %xmm2,%xmm1 - 43a13c: 48 85 c0 test %rax,%rax - 43a13f: 0f 85 e5 00 00 00 jne 43a22a <__stpcpy_ssse3+0xd0a> - 43a145: 66 0f 3a 0f d3 08 palignr $0x8,%xmm3,%xmm2 - 43a14b: 0f 29 12 movaps %xmm2,(%rdx) - 43a14e: 0f 28 51 18 movaps 0x18(%rcx),%xmm2 - 43a152: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a156: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a15a: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a15e: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43a162: 0f 28 da movaps %xmm2,%xmm3 - 43a165: 48 85 c0 test %rax,%rax - 43a168: 0f 85 bc 00 00 00 jne 43a22a <__stpcpy_ssse3+0xd0a> - 43a16e: 66 0f 3a 0f d1 08 palignr $0x8,%xmm1,%xmm2 - 43a174: 0f 29 12 movaps %xmm2,(%rdx) - 43a177: 0f 28 51 18 movaps 0x18(%rcx),%xmm2 - 43a17b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a17f: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a183: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a187: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43a18b: 48 85 c0 test %rax,%rax - 43a18e: 0f 85 96 00 00 00 jne 43a22a <__stpcpy_ssse3+0xd0a> - 43a194: 66 0f 3a 0f d3 08 palignr $0x8,%xmm3,%xmm2 - 43a19a: 0f 29 12 movaps %xmm2,(%rdx) - 43a19d: 48 8d 49 18 lea 0x18(%rcx),%rcx - 43a1a1: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a1a5: 48 89 c8 mov %rcx,%rax - 43a1a8: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 43a1ac: 48 29 c8 sub %rcx,%rax - 43a1af: 48 8d 49 f8 lea -0x8(%rcx),%rcx - 43a1b3: 48 29 c2 sub %rax,%rdx - 43a1b6: 0f 28 49 f8 movaps -0x8(%rcx),%xmm1 - 43a1ba: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43a1c0: 0f 28 51 08 movaps 0x8(%rcx),%xmm2 - 43a1c4: 0f 28 59 18 movaps 0x18(%rcx),%xmm3 - 43a1c8: 0f 28 f3 movaps %xmm3,%xmm6 - 43a1cb: 0f 28 61 28 movaps 0x28(%rcx),%xmm4 - 43a1cf: 0f 28 fc movaps %xmm4,%xmm7 - 43a1d2: 0f 28 69 38 movaps 0x38(%rcx),%xmm5 - 43a1d6: 66 0f da f2 pminub %xmm2,%xmm6 - 43a1da: 66 0f da fd pminub %xmm5,%xmm7 - 43a1de: 66 0f da fe pminub %xmm6,%xmm7 - 43a1e2: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 43a1e6: 66 0f d7 c7 pmovmskb %xmm7,%eax - 43a1ea: 0f 28 fd movaps %xmm5,%xmm7 - 43a1ed: 66 0f 3a 0f ec 08 palignr $0x8,%xmm4,%xmm5 - 43a1f3: 48 85 c0 test %rax,%rax - 43a1f6: 66 0f 3a 0f e3 08 palignr $0x8,%xmm3,%xmm4 - 43a1fc: 0f 85 06 ff ff ff jne 43a108 <__stpcpy_ssse3+0xbe8> - 43a202: 66 0f 3a 0f da 08 palignr $0x8,%xmm2,%xmm3 - 43a208: 48 8d 49 40 lea 0x40(%rcx),%rcx - 43a20c: 66 0f 3a 0f d1 08 palignr $0x8,%xmm1,%xmm2 - 43a212: 0f 28 cf movaps %xmm7,%xmm1 - 43a215: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) - 43a219: 0f 29 62 20 movaps %xmm4,0x20(%rdx) - 43a21d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) - 43a221: 0f 29 12 movaps %xmm2,(%rdx) - 43a224: 48 8d 52 40 lea 0x40(%rdx),%rdx - 43a228: eb 96 jmp 43a1c0 <__stpcpy_ssse3+0xca0> - 43a22a: 4c 8b 09 mov (%rcx),%r9 - 43a22d: 48 c7 c6 08 00 00 00 mov $0x8,%rsi - 43a234: 4c 89 0a mov %r9,(%rdx) - 43a237: e9 c4 08 00 00 jmpq 43ab00 <__stpcpy_ssse3+0x15e0> - 43a23c: 0f 1f 40 00 nopl 0x0(%rax) - 43a240: 0f 28 49 f7 movaps -0x9(%rcx),%xmm1 - 43a244: 0f 28 51 07 movaps 0x7(%rcx),%xmm2 - 43a248: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a24c: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a250: 0f 28 da movaps %xmm2,%xmm3 - 43a253: 48 85 c0 test %rax,%rax - 43a256: 0f 85 0e 01 00 00 jne 43a36a <__stpcpy_ssse3+0xe4a> - 43a25c: 66 0f 3a 0f d1 09 palignr $0x9,%xmm1,%xmm2 - 43a262: 0f 29 12 movaps %xmm2,(%rdx) - 43a265: 0f 28 51 17 movaps 0x17(%rcx),%xmm2 - 43a269: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a26d: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a271: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a275: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43a279: 0f 28 ca movaps %xmm2,%xmm1 - 43a27c: 48 85 c0 test %rax,%rax - 43a27f: 0f 85 e5 00 00 00 jne 43a36a <__stpcpy_ssse3+0xe4a> - 43a285: 66 0f 3a 0f d3 09 palignr $0x9,%xmm3,%xmm2 - 43a28b: 0f 29 12 movaps %xmm2,(%rdx) - 43a28e: 0f 28 51 17 movaps 0x17(%rcx),%xmm2 - 43a292: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a296: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a29a: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a29e: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43a2a2: 0f 28 da movaps %xmm2,%xmm3 - 43a2a5: 48 85 c0 test %rax,%rax - 43a2a8: 0f 85 bc 00 00 00 jne 43a36a <__stpcpy_ssse3+0xe4a> - 43a2ae: 66 0f 3a 0f d1 09 palignr $0x9,%xmm1,%xmm2 - 43a2b4: 0f 29 12 movaps %xmm2,(%rdx) - 43a2b7: 0f 28 51 17 movaps 0x17(%rcx),%xmm2 - 43a2bb: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a2bf: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a2c3: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a2c7: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43a2cb: 48 85 c0 test %rax,%rax - 43a2ce: 0f 85 96 00 00 00 jne 43a36a <__stpcpy_ssse3+0xe4a> - 43a2d4: 66 0f 3a 0f d3 09 palignr $0x9,%xmm3,%xmm2 - 43a2da: 0f 29 12 movaps %xmm2,(%rdx) - 43a2dd: 48 8d 49 17 lea 0x17(%rcx),%rcx - 43a2e1: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a2e5: 48 89 c8 mov %rcx,%rax - 43a2e8: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 43a2ec: 48 29 c8 sub %rcx,%rax - 43a2ef: 48 8d 49 f9 lea -0x7(%rcx),%rcx - 43a2f3: 48 29 c2 sub %rax,%rdx - 43a2f6: 0f 28 49 f7 movaps -0x9(%rcx),%xmm1 - 43a2fa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43a300: 0f 28 51 07 movaps 0x7(%rcx),%xmm2 - 43a304: 0f 28 59 17 movaps 0x17(%rcx),%xmm3 - 43a308: 0f 28 f3 movaps %xmm3,%xmm6 - 43a30b: 0f 28 61 27 movaps 0x27(%rcx),%xmm4 - 43a30f: 0f 28 fc movaps %xmm4,%xmm7 - 43a312: 0f 28 69 37 movaps 0x37(%rcx),%xmm5 - 43a316: 66 0f da f2 pminub %xmm2,%xmm6 - 43a31a: 66 0f da fd pminub %xmm5,%xmm7 - 43a31e: 66 0f da fe pminub %xmm6,%xmm7 - 43a322: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 43a326: 66 0f d7 c7 pmovmskb %xmm7,%eax - 43a32a: 0f 28 fd movaps %xmm5,%xmm7 - 43a32d: 66 0f 3a 0f ec 09 palignr $0x9,%xmm4,%xmm5 - 43a333: 48 85 c0 test %rax,%rax - 43a336: 66 0f 3a 0f e3 09 palignr $0x9,%xmm3,%xmm4 - 43a33c: 0f 85 06 ff ff ff jne 43a248 <__stpcpy_ssse3+0xd28> - 43a342: 66 0f 3a 0f da 09 palignr $0x9,%xmm2,%xmm3 - 43a348: 48 8d 49 40 lea 0x40(%rcx),%rcx - 43a34c: 66 0f 3a 0f d1 09 palignr $0x9,%xmm1,%xmm2 - 43a352: 0f 28 cf movaps %xmm7,%xmm1 - 43a355: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) - 43a359: 0f 29 62 20 movaps %xmm4,0x20(%rdx) - 43a35d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) - 43a361: 0f 29 12 movaps %xmm2,(%rdx) - 43a364: 48 8d 52 40 lea 0x40(%rdx),%rdx - 43a368: eb 96 jmp 43a300 <__stpcpy_ssse3+0xde0> - 43a36a: 4c 8b 49 ff mov -0x1(%rcx),%r9 - 43a36e: 48 c7 c6 07 00 00 00 mov $0x7,%rsi - 43a375: 4c 89 4a ff mov %r9,-0x1(%rdx) - 43a379: e9 82 07 00 00 jmpq 43ab00 <__stpcpy_ssse3+0x15e0> - 43a37e: 66 90 xchg %ax,%ax - 43a380: 0f 28 49 f6 movaps -0xa(%rcx),%xmm1 - 43a384: 0f 28 51 06 movaps 0x6(%rcx),%xmm2 - 43a388: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a38c: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a390: 0f 28 da movaps %xmm2,%xmm3 - 43a393: 48 85 c0 test %rax,%rax - 43a396: 0f 85 0e 01 00 00 jne 43a4aa <__stpcpy_ssse3+0xf8a> - 43a39c: 66 0f 3a 0f d1 0a palignr $0xa,%xmm1,%xmm2 - 43a3a2: 0f 29 12 movaps %xmm2,(%rdx) - 43a3a5: 0f 28 51 16 movaps 0x16(%rcx),%xmm2 - 43a3a9: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a3ad: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a3b1: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a3b5: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43a3b9: 0f 28 ca movaps %xmm2,%xmm1 - 43a3bc: 48 85 c0 test %rax,%rax - 43a3bf: 0f 85 e5 00 00 00 jne 43a4aa <__stpcpy_ssse3+0xf8a> - 43a3c5: 66 0f 3a 0f d3 0a palignr $0xa,%xmm3,%xmm2 - 43a3cb: 0f 29 12 movaps %xmm2,(%rdx) - 43a3ce: 0f 28 51 16 movaps 0x16(%rcx),%xmm2 - 43a3d2: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a3d6: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a3da: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a3de: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43a3e2: 0f 28 da movaps %xmm2,%xmm3 - 43a3e5: 48 85 c0 test %rax,%rax - 43a3e8: 0f 85 bc 00 00 00 jne 43a4aa <__stpcpy_ssse3+0xf8a> - 43a3ee: 66 0f 3a 0f d1 0a palignr $0xa,%xmm1,%xmm2 - 43a3f4: 0f 29 12 movaps %xmm2,(%rdx) - 43a3f7: 0f 28 51 16 movaps 0x16(%rcx),%xmm2 - 43a3fb: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a3ff: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a403: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a407: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43a40b: 48 85 c0 test %rax,%rax - 43a40e: 0f 85 96 00 00 00 jne 43a4aa <__stpcpy_ssse3+0xf8a> - 43a414: 66 0f 3a 0f d3 0a palignr $0xa,%xmm3,%xmm2 - 43a41a: 0f 29 12 movaps %xmm2,(%rdx) - 43a41d: 48 8d 49 16 lea 0x16(%rcx),%rcx - 43a421: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a425: 48 89 c8 mov %rcx,%rax - 43a428: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 43a42c: 48 29 c8 sub %rcx,%rax - 43a42f: 48 8d 49 fa lea -0x6(%rcx),%rcx - 43a433: 48 29 c2 sub %rax,%rdx - 43a436: 0f 28 49 f6 movaps -0xa(%rcx),%xmm1 - 43a43a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43a440: 0f 28 51 06 movaps 0x6(%rcx),%xmm2 - 43a444: 0f 28 59 16 movaps 0x16(%rcx),%xmm3 - 43a448: 0f 28 f3 movaps %xmm3,%xmm6 - 43a44b: 0f 28 61 26 movaps 0x26(%rcx),%xmm4 - 43a44f: 0f 28 fc movaps %xmm4,%xmm7 - 43a452: 0f 28 69 36 movaps 0x36(%rcx),%xmm5 - 43a456: 66 0f da f2 pminub %xmm2,%xmm6 - 43a45a: 66 0f da fd pminub %xmm5,%xmm7 - 43a45e: 66 0f da fe pminub %xmm6,%xmm7 - 43a462: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 43a466: 66 0f d7 c7 pmovmskb %xmm7,%eax - 43a46a: 0f 28 fd movaps %xmm5,%xmm7 - 43a46d: 66 0f 3a 0f ec 0a palignr $0xa,%xmm4,%xmm5 - 43a473: 48 85 c0 test %rax,%rax - 43a476: 66 0f 3a 0f e3 0a palignr $0xa,%xmm3,%xmm4 - 43a47c: 0f 85 06 ff ff ff jne 43a388 <__stpcpy_ssse3+0xe68> - 43a482: 66 0f 3a 0f da 0a palignr $0xa,%xmm2,%xmm3 - 43a488: 48 8d 49 40 lea 0x40(%rcx),%rcx - 43a48c: 66 0f 3a 0f d1 0a palignr $0xa,%xmm1,%xmm2 - 43a492: 0f 28 cf movaps %xmm7,%xmm1 - 43a495: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) - 43a499: 0f 29 62 20 movaps %xmm4,0x20(%rdx) - 43a49d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) - 43a4a1: 0f 29 12 movaps %xmm2,(%rdx) - 43a4a4: 48 8d 52 40 lea 0x40(%rdx),%rdx - 43a4a8: eb 96 jmp 43a440 <__stpcpy_ssse3+0xf20> - 43a4aa: 4c 8b 49 fe mov -0x2(%rcx),%r9 - 43a4ae: 48 c7 c6 06 00 00 00 mov $0x6,%rsi - 43a4b5: 4c 89 4a fe mov %r9,-0x2(%rdx) - 43a4b9: e9 42 06 00 00 jmpq 43ab00 <__stpcpy_ssse3+0x15e0> - 43a4be: 66 90 xchg %ax,%ax - 43a4c0: 0f 28 49 f5 movaps -0xb(%rcx),%xmm1 - 43a4c4: 0f 28 51 05 movaps 0x5(%rcx),%xmm2 - 43a4c8: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a4cc: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a4d0: 0f 28 da movaps %xmm2,%xmm3 - 43a4d3: 48 85 c0 test %rax,%rax - 43a4d6: 0f 85 0e 01 00 00 jne 43a5ea <__stpcpy_ssse3+0x10ca> - 43a4dc: 66 0f 3a 0f d1 0b palignr $0xb,%xmm1,%xmm2 - 43a4e2: 0f 29 12 movaps %xmm2,(%rdx) - 43a4e5: 0f 28 51 15 movaps 0x15(%rcx),%xmm2 - 43a4e9: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a4ed: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a4f1: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a4f5: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43a4f9: 0f 28 ca movaps %xmm2,%xmm1 - 43a4fc: 48 85 c0 test %rax,%rax - 43a4ff: 0f 85 e5 00 00 00 jne 43a5ea <__stpcpy_ssse3+0x10ca> - 43a505: 66 0f 3a 0f d3 0b palignr $0xb,%xmm3,%xmm2 - 43a50b: 0f 29 12 movaps %xmm2,(%rdx) - 43a50e: 0f 28 51 15 movaps 0x15(%rcx),%xmm2 - 43a512: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a516: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a51a: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a51e: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43a522: 0f 28 da movaps %xmm2,%xmm3 - 43a525: 48 85 c0 test %rax,%rax - 43a528: 0f 85 bc 00 00 00 jne 43a5ea <__stpcpy_ssse3+0x10ca> - 43a52e: 66 0f 3a 0f d1 0b palignr $0xb,%xmm1,%xmm2 - 43a534: 0f 29 12 movaps %xmm2,(%rdx) - 43a537: 0f 28 51 15 movaps 0x15(%rcx),%xmm2 - 43a53b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a53f: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a543: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a547: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43a54b: 48 85 c0 test %rax,%rax - 43a54e: 0f 85 96 00 00 00 jne 43a5ea <__stpcpy_ssse3+0x10ca> - 43a554: 66 0f 3a 0f d3 0b palignr $0xb,%xmm3,%xmm2 - 43a55a: 0f 29 12 movaps %xmm2,(%rdx) - 43a55d: 48 8d 49 15 lea 0x15(%rcx),%rcx - 43a561: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a565: 48 89 c8 mov %rcx,%rax - 43a568: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 43a56c: 48 29 c8 sub %rcx,%rax - 43a56f: 48 8d 49 fb lea -0x5(%rcx),%rcx - 43a573: 48 29 c2 sub %rax,%rdx - 43a576: 0f 28 49 f5 movaps -0xb(%rcx),%xmm1 - 43a57a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43a580: 0f 28 51 05 movaps 0x5(%rcx),%xmm2 - 43a584: 0f 28 59 15 movaps 0x15(%rcx),%xmm3 - 43a588: 0f 28 f3 movaps %xmm3,%xmm6 - 43a58b: 0f 28 61 25 movaps 0x25(%rcx),%xmm4 - 43a58f: 0f 28 fc movaps %xmm4,%xmm7 - 43a592: 0f 28 69 35 movaps 0x35(%rcx),%xmm5 - 43a596: 66 0f da f2 pminub %xmm2,%xmm6 - 43a59a: 66 0f da fd pminub %xmm5,%xmm7 - 43a59e: 66 0f da fe pminub %xmm6,%xmm7 - 43a5a2: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 43a5a6: 66 0f d7 c7 pmovmskb %xmm7,%eax - 43a5aa: 0f 28 fd movaps %xmm5,%xmm7 - 43a5ad: 66 0f 3a 0f ec 0b palignr $0xb,%xmm4,%xmm5 - 43a5b3: 48 85 c0 test %rax,%rax - 43a5b6: 66 0f 3a 0f e3 0b palignr $0xb,%xmm3,%xmm4 - 43a5bc: 0f 85 06 ff ff ff jne 43a4c8 <__stpcpy_ssse3+0xfa8> - 43a5c2: 66 0f 3a 0f da 0b palignr $0xb,%xmm2,%xmm3 - 43a5c8: 48 8d 49 40 lea 0x40(%rcx),%rcx - 43a5cc: 66 0f 3a 0f d1 0b palignr $0xb,%xmm1,%xmm2 - 43a5d2: 0f 28 cf movaps %xmm7,%xmm1 - 43a5d5: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) - 43a5d9: 0f 29 62 20 movaps %xmm4,0x20(%rdx) - 43a5dd: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) - 43a5e1: 0f 29 12 movaps %xmm2,(%rdx) - 43a5e4: 48 8d 52 40 lea 0x40(%rdx),%rdx - 43a5e8: eb 96 jmp 43a580 <__stpcpy_ssse3+0x1060> - 43a5ea: 4c 8b 49 fd mov -0x3(%rcx),%r9 - 43a5ee: 48 c7 c6 05 00 00 00 mov $0x5,%rsi - 43a5f5: 4c 89 4a fd mov %r9,-0x3(%rdx) - 43a5f9: e9 02 05 00 00 jmpq 43ab00 <__stpcpy_ssse3+0x15e0> - 43a5fe: 66 90 xchg %ax,%ax - 43a600: 0f 28 49 f4 movaps -0xc(%rcx),%xmm1 - 43a604: 0f 28 51 04 movaps 0x4(%rcx),%xmm2 - 43a608: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a60c: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a610: 0f 28 da movaps %xmm2,%xmm3 - 43a613: 48 85 c0 test %rax,%rax - 43a616: 0f 85 0e 01 00 00 jne 43a72a <__stpcpy_ssse3+0x120a> - 43a61c: 66 0f 3a 0f d1 0c palignr $0xc,%xmm1,%xmm2 - 43a622: 0f 29 12 movaps %xmm2,(%rdx) - 43a625: 0f 28 51 14 movaps 0x14(%rcx),%xmm2 - 43a629: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a62d: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a631: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a635: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43a639: 0f 28 ca movaps %xmm2,%xmm1 - 43a63c: 48 85 c0 test %rax,%rax - 43a63f: 0f 85 e5 00 00 00 jne 43a72a <__stpcpy_ssse3+0x120a> - 43a645: 66 0f 3a 0f d3 0c palignr $0xc,%xmm3,%xmm2 - 43a64b: 0f 29 12 movaps %xmm2,(%rdx) - 43a64e: 0f 28 51 14 movaps 0x14(%rcx),%xmm2 - 43a652: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a656: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a65a: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a65e: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43a662: 0f 28 da movaps %xmm2,%xmm3 - 43a665: 48 85 c0 test %rax,%rax - 43a668: 0f 85 bc 00 00 00 jne 43a72a <__stpcpy_ssse3+0x120a> - 43a66e: 66 0f 3a 0f d1 0c palignr $0xc,%xmm1,%xmm2 - 43a674: 0f 29 12 movaps %xmm2,(%rdx) - 43a677: 0f 28 51 14 movaps 0x14(%rcx),%xmm2 - 43a67b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a67f: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a683: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a687: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43a68b: 48 85 c0 test %rax,%rax - 43a68e: 0f 85 96 00 00 00 jne 43a72a <__stpcpy_ssse3+0x120a> - 43a694: 66 0f 3a 0f d3 0c palignr $0xc,%xmm3,%xmm2 - 43a69a: 0f 29 12 movaps %xmm2,(%rdx) - 43a69d: 48 8d 49 14 lea 0x14(%rcx),%rcx - 43a6a1: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a6a5: 48 89 c8 mov %rcx,%rax - 43a6a8: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 43a6ac: 48 29 c8 sub %rcx,%rax - 43a6af: 48 8d 49 fc lea -0x4(%rcx),%rcx - 43a6b3: 48 29 c2 sub %rax,%rdx - 43a6b6: 0f 28 49 f4 movaps -0xc(%rcx),%xmm1 - 43a6ba: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43a6c0: 0f 28 51 04 movaps 0x4(%rcx),%xmm2 - 43a6c4: 0f 28 59 14 movaps 0x14(%rcx),%xmm3 - 43a6c8: 0f 28 f3 movaps %xmm3,%xmm6 - 43a6cb: 0f 28 61 24 movaps 0x24(%rcx),%xmm4 - 43a6cf: 0f 28 fc movaps %xmm4,%xmm7 - 43a6d2: 0f 28 69 34 movaps 0x34(%rcx),%xmm5 - 43a6d6: 66 0f da f2 pminub %xmm2,%xmm6 - 43a6da: 66 0f da fd pminub %xmm5,%xmm7 - 43a6de: 66 0f da fe pminub %xmm6,%xmm7 - 43a6e2: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 43a6e6: 66 0f d7 c7 pmovmskb %xmm7,%eax - 43a6ea: 0f 28 fd movaps %xmm5,%xmm7 - 43a6ed: 66 0f 3a 0f ec 0c palignr $0xc,%xmm4,%xmm5 - 43a6f3: 48 85 c0 test %rax,%rax - 43a6f6: 66 0f 3a 0f e3 0c palignr $0xc,%xmm3,%xmm4 - 43a6fc: 0f 85 06 ff ff ff jne 43a608 <__stpcpy_ssse3+0x10e8> - 43a702: 66 0f 3a 0f da 0c palignr $0xc,%xmm2,%xmm3 - 43a708: 48 8d 49 40 lea 0x40(%rcx),%rcx - 43a70c: 66 0f 3a 0f d1 0c palignr $0xc,%xmm1,%xmm2 - 43a712: 0f 28 cf movaps %xmm7,%xmm1 - 43a715: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) - 43a719: 0f 29 62 20 movaps %xmm4,0x20(%rdx) - 43a71d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) - 43a721: 0f 29 12 movaps %xmm2,(%rdx) - 43a724: 48 8d 52 40 lea 0x40(%rdx),%rdx - 43a728: eb 96 jmp 43a6c0 <__stpcpy_ssse3+0x11a0> - 43a72a: 44 8b 09 mov (%rcx),%r9d - 43a72d: 48 c7 c6 04 00 00 00 mov $0x4,%rsi - 43a734: 44 89 0a mov %r9d,(%rdx) - 43a737: e9 c4 03 00 00 jmpq 43ab00 <__stpcpy_ssse3+0x15e0> - 43a73c: 0f 1f 40 00 nopl 0x0(%rax) - 43a740: 0f 28 49 f3 movaps -0xd(%rcx),%xmm1 - 43a744: 0f 28 51 03 movaps 0x3(%rcx),%xmm2 - 43a748: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a74c: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a750: 0f 28 da movaps %xmm2,%xmm3 - 43a753: 48 85 c0 test %rax,%rax - 43a756: 0f 85 0e 01 00 00 jne 43a86a <__stpcpy_ssse3+0x134a> - 43a75c: 66 0f 3a 0f d1 0d palignr $0xd,%xmm1,%xmm2 - 43a762: 0f 29 12 movaps %xmm2,(%rdx) - 43a765: 0f 28 51 13 movaps 0x13(%rcx),%xmm2 - 43a769: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a76d: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a771: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a775: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43a779: 0f 28 ca movaps %xmm2,%xmm1 - 43a77c: 48 85 c0 test %rax,%rax - 43a77f: 0f 85 e5 00 00 00 jne 43a86a <__stpcpy_ssse3+0x134a> - 43a785: 66 0f 3a 0f d3 0d palignr $0xd,%xmm3,%xmm2 - 43a78b: 0f 29 12 movaps %xmm2,(%rdx) - 43a78e: 0f 28 51 13 movaps 0x13(%rcx),%xmm2 - 43a792: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a796: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a79a: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a79e: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43a7a2: 0f 28 da movaps %xmm2,%xmm3 - 43a7a5: 48 85 c0 test %rax,%rax - 43a7a8: 0f 85 bc 00 00 00 jne 43a86a <__stpcpy_ssse3+0x134a> - 43a7ae: 66 0f 3a 0f d1 0d palignr $0xd,%xmm1,%xmm2 - 43a7b4: 0f 29 12 movaps %xmm2,(%rdx) - 43a7b7: 0f 28 51 13 movaps 0x13(%rcx),%xmm2 - 43a7bb: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a7bf: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a7c3: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a7c7: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43a7cb: 48 85 c0 test %rax,%rax - 43a7ce: 0f 85 96 00 00 00 jne 43a86a <__stpcpy_ssse3+0x134a> - 43a7d4: 66 0f 3a 0f d3 0d palignr $0xd,%xmm3,%xmm2 - 43a7da: 0f 29 12 movaps %xmm2,(%rdx) - 43a7dd: 48 8d 49 13 lea 0x13(%rcx),%rcx - 43a7e1: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a7e5: 48 89 c8 mov %rcx,%rax - 43a7e8: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 43a7ec: 48 29 c8 sub %rcx,%rax - 43a7ef: 48 8d 49 fd lea -0x3(%rcx),%rcx - 43a7f3: 48 29 c2 sub %rax,%rdx - 43a7f6: 0f 28 49 f3 movaps -0xd(%rcx),%xmm1 - 43a7fa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43a800: 0f 28 51 03 movaps 0x3(%rcx),%xmm2 - 43a804: 0f 28 59 13 movaps 0x13(%rcx),%xmm3 - 43a808: 0f 28 f3 movaps %xmm3,%xmm6 - 43a80b: 0f 28 61 23 movaps 0x23(%rcx),%xmm4 - 43a80f: 0f 28 fc movaps %xmm4,%xmm7 - 43a812: 0f 28 69 33 movaps 0x33(%rcx),%xmm5 - 43a816: 66 0f da f2 pminub %xmm2,%xmm6 - 43a81a: 66 0f da fd pminub %xmm5,%xmm7 - 43a81e: 66 0f da fe pminub %xmm6,%xmm7 - 43a822: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 43a826: 66 0f d7 c7 pmovmskb %xmm7,%eax - 43a82a: 0f 28 fd movaps %xmm5,%xmm7 - 43a82d: 66 0f 3a 0f ec 0d palignr $0xd,%xmm4,%xmm5 - 43a833: 48 85 c0 test %rax,%rax - 43a836: 66 0f 3a 0f e3 0d palignr $0xd,%xmm3,%xmm4 - 43a83c: 0f 85 06 ff ff ff jne 43a748 <__stpcpy_ssse3+0x1228> - 43a842: 66 0f 3a 0f da 0d palignr $0xd,%xmm2,%xmm3 - 43a848: 48 8d 49 40 lea 0x40(%rcx),%rcx - 43a84c: 66 0f 3a 0f d1 0d palignr $0xd,%xmm1,%xmm2 - 43a852: 0f 28 cf movaps %xmm7,%xmm1 - 43a855: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) - 43a859: 0f 29 62 20 movaps %xmm4,0x20(%rdx) - 43a85d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) - 43a861: 0f 29 12 movaps %xmm2,(%rdx) - 43a864: 48 8d 52 40 lea 0x40(%rdx),%rdx - 43a868: eb 96 jmp 43a800 <__stpcpy_ssse3+0x12e0> - 43a86a: 44 8b 49 ff mov -0x1(%rcx),%r9d - 43a86e: 48 c7 c6 03 00 00 00 mov $0x3,%rsi - 43a875: 44 89 4a ff mov %r9d,-0x1(%rdx) - 43a879: e9 82 02 00 00 jmpq 43ab00 <__stpcpy_ssse3+0x15e0> - 43a87e: 66 90 xchg %ax,%ax - 43a880: 0f 28 49 f2 movaps -0xe(%rcx),%xmm1 - 43a884: 0f 28 51 02 movaps 0x2(%rcx),%xmm2 - 43a888: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a88c: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a890: 0f 28 da movaps %xmm2,%xmm3 - 43a893: 48 85 c0 test %rax,%rax - 43a896: 0f 85 0e 01 00 00 jne 43a9aa <__stpcpy_ssse3+0x148a> - 43a89c: 66 0f 3a 0f d1 0e palignr $0xe,%xmm1,%xmm2 - 43a8a2: 0f 29 12 movaps %xmm2,(%rdx) - 43a8a5: 0f 28 51 12 movaps 0x12(%rcx),%xmm2 - 43a8a9: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a8ad: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a8b1: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a8b5: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43a8b9: 0f 28 ca movaps %xmm2,%xmm1 - 43a8bc: 48 85 c0 test %rax,%rax - 43a8bf: 0f 85 e5 00 00 00 jne 43a9aa <__stpcpy_ssse3+0x148a> - 43a8c5: 66 0f 3a 0f d3 0e palignr $0xe,%xmm3,%xmm2 - 43a8cb: 0f 29 12 movaps %xmm2,(%rdx) - 43a8ce: 0f 28 51 12 movaps 0x12(%rcx),%xmm2 - 43a8d2: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a8d6: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a8da: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a8de: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43a8e2: 0f 28 da movaps %xmm2,%xmm3 - 43a8e5: 48 85 c0 test %rax,%rax - 43a8e8: 0f 85 bc 00 00 00 jne 43a9aa <__stpcpy_ssse3+0x148a> - 43a8ee: 66 0f 3a 0f d1 0e palignr $0xe,%xmm1,%xmm2 - 43a8f4: 0f 29 12 movaps %xmm2,(%rdx) - 43a8f7: 0f 28 51 12 movaps 0x12(%rcx),%xmm2 - 43a8fb: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a8ff: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a903: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a907: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43a90b: 48 85 c0 test %rax,%rax - 43a90e: 0f 85 96 00 00 00 jne 43a9aa <__stpcpy_ssse3+0x148a> - 43a914: 66 0f 3a 0f d3 0e palignr $0xe,%xmm3,%xmm2 - 43a91a: 0f 29 12 movaps %xmm2,(%rdx) - 43a91d: 48 8d 49 12 lea 0x12(%rcx),%rcx - 43a921: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a925: 48 89 c8 mov %rcx,%rax - 43a928: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 43a92c: 48 29 c8 sub %rcx,%rax - 43a92f: 48 8d 49 fe lea -0x2(%rcx),%rcx - 43a933: 48 29 c2 sub %rax,%rdx - 43a936: 0f 28 49 f2 movaps -0xe(%rcx),%xmm1 - 43a93a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43a940: 0f 28 51 02 movaps 0x2(%rcx),%xmm2 - 43a944: 0f 28 59 12 movaps 0x12(%rcx),%xmm3 - 43a948: 0f 28 f3 movaps %xmm3,%xmm6 - 43a94b: 0f 28 61 22 movaps 0x22(%rcx),%xmm4 - 43a94f: 0f 28 fc movaps %xmm4,%xmm7 - 43a952: 0f 28 69 32 movaps 0x32(%rcx),%xmm5 - 43a956: 66 0f da f2 pminub %xmm2,%xmm6 - 43a95a: 66 0f da fd pminub %xmm5,%xmm7 - 43a95e: 66 0f da fe pminub %xmm6,%xmm7 - 43a962: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 43a966: 66 0f d7 c7 pmovmskb %xmm7,%eax - 43a96a: 0f 28 fd movaps %xmm5,%xmm7 - 43a96d: 66 0f 3a 0f ec 0e palignr $0xe,%xmm4,%xmm5 - 43a973: 48 85 c0 test %rax,%rax - 43a976: 66 0f 3a 0f e3 0e palignr $0xe,%xmm3,%xmm4 - 43a97c: 0f 85 06 ff ff ff jne 43a888 <__stpcpy_ssse3+0x1368> - 43a982: 66 0f 3a 0f da 0e palignr $0xe,%xmm2,%xmm3 - 43a988: 48 8d 49 40 lea 0x40(%rcx),%rcx - 43a98c: 66 0f 3a 0f d1 0e palignr $0xe,%xmm1,%xmm2 - 43a992: 0f 28 cf movaps %xmm7,%xmm1 - 43a995: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) - 43a999: 0f 29 62 20 movaps %xmm4,0x20(%rdx) - 43a99d: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) - 43a9a1: 0f 29 12 movaps %xmm2,(%rdx) - 43a9a4: 48 8d 52 40 lea 0x40(%rdx),%rdx - 43a9a8: eb 96 jmp 43a940 <__stpcpy_ssse3+0x1420> - 43a9aa: 44 8b 49 fe mov -0x2(%rcx),%r9d - 43a9ae: 48 c7 c6 02 00 00 00 mov $0x2,%rsi - 43a9b5: 44 89 4a fe mov %r9d,-0x2(%rdx) - 43a9b9: e9 42 01 00 00 jmpq 43ab00 <__stpcpy_ssse3+0x15e0> - 43a9be: 66 90 xchg %ax,%ax - 43a9c0: 0f 28 49 f1 movaps -0xf(%rcx),%xmm1 - 43a9c4: 0f 28 51 01 movaps 0x1(%rcx),%xmm2 - 43a9c8: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a9cc: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a9d0: 0f 28 da movaps %xmm2,%xmm3 - 43a9d3: 48 85 c0 test %rax,%rax - 43a9d6: 0f 85 0e 01 00 00 jne 43aaea <__stpcpy_ssse3+0x15ca> - 43a9dc: 66 0f 3a 0f d1 0f palignr $0xf,%xmm1,%xmm2 - 43a9e2: 0f 29 12 movaps %xmm2,(%rdx) - 43a9e5: 0f 28 51 11 movaps 0x11(%rcx),%xmm2 - 43a9e9: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43a9ed: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43a9f1: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43a9f5: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43a9f9: 0f 28 ca movaps %xmm2,%xmm1 - 43a9fc: 48 85 c0 test %rax,%rax - 43a9ff: 0f 85 e5 00 00 00 jne 43aaea <__stpcpy_ssse3+0x15ca> - 43aa05: 66 0f 3a 0f d3 0f palignr $0xf,%xmm3,%xmm2 - 43aa0b: 0f 29 12 movaps %xmm2,(%rdx) - 43aa0e: 0f 28 51 11 movaps 0x11(%rcx),%xmm2 - 43aa12: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43aa16: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43aa1a: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43aa1e: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43aa22: 0f 28 da movaps %xmm2,%xmm3 - 43aa25: 48 85 c0 test %rax,%rax - 43aa28: 0f 85 bc 00 00 00 jne 43aaea <__stpcpy_ssse3+0x15ca> - 43aa2e: 66 0f 3a 0f d1 0f palignr $0xf,%xmm1,%xmm2 - 43aa34: 0f 29 12 movaps %xmm2,(%rdx) - 43aa37: 0f 28 51 11 movaps 0x11(%rcx),%xmm2 - 43aa3b: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43aa3f: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43aa43: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43aa47: 48 8d 49 10 lea 0x10(%rcx),%rcx - 43aa4b: 48 85 c0 test %rax,%rax - 43aa4e: 0f 85 96 00 00 00 jne 43aaea <__stpcpy_ssse3+0x15ca> - 43aa54: 66 0f 3a 0f d3 0f palignr $0xf,%xmm3,%xmm2 - 43aa5a: 0f 29 12 movaps %xmm2,(%rdx) - 43aa5d: 48 8d 49 11 lea 0x11(%rcx),%rcx - 43aa61: 48 8d 52 10 lea 0x10(%rdx),%rdx - 43aa65: 48 89 c8 mov %rcx,%rax - 43aa68: 48 83 e1 c0 and $0xffffffffffffffc0,%rcx - 43aa6c: 48 29 c8 sub %rcx,%rax - 43aa6f: 48 8d 49 ff lea -0x1(%rcx),%rcx - 43aa73: 48 29 c2 sub %rax,%rdx - 43aa76: 0f 28 49 f1 movaps -0xf(%rcx),%xmm1 - 43aa7a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43aa80: 0f 28 51 01 movaps 0x1(%rcx),%xmm2 - 43aa84: 0f 28 59 11 movaps 0x11(%rcx),%xmm3 - 43aa88: 0f 28 f3 movaps %xmm3,%xmm6 - 43aa8b: 0f 28 61 21 movaps 0x21(%rcx),%xmm4 - 43aa8f: 0f 28 fc movaps %xmm4,%xmm7 - 43aa92: 0f 28 69 31 movaps 0x31(%rcx),%xmm5 - 43aa96: 66 0f da f2 pminub %xmm2,%xmm6 - 43aa9a: 66 0f da fd pminub %xmm5,%xmm7 - 43aa9e: 66 0f da fe pminub %xmm6,%xmm7 - 43aaa2: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 43aaa6: 66 0f d7 c7 pmovmskb %xmm7,%eax - 43aaaa: 0f 28 fd movaps %xmm5,%xmm7 - 43aaad: 66 0f 3a 0f ec 0f palignr $0xf,%xmm4,%xmm5 - 43aab3: 48 85 c0 test %rax,%rax - 43aab6: 66 0f 3a 0f e3 0f palignr $0xf,%xmm3,%xmm4 - 43aabc: 0f 85 06 ff ff ff jne 43a9c8 <__stpcpy_ssse3+0x14a8> - 43aac2: 66 0f 3a 0f da 0f palignr $0xf,%xmm2,%xmm3 - 43aac8: 48 8d 49 40 lea 0x40(%rcx),%rcx - 43aacc: 66 0f 3a 0f d1 0f palignr $0xf,%xmm1,%xmm2 - 43aad2: 0f 28 cf movaps %xmm7,%xmm1 - 43aad5: 0f 29 6a 30 movaps %xmm5,0x30(%rdx) - 43aad9: 0f 29 62 20 movaps %xmm4,0x20(%rdx) - 43aadd: 0f 29 5a 10 movaps %xmm3,0x10(%rdx) - 43aae1: 0f 29 12 movaps %xmm2,(%rdx) - 43aae4: 48 8d 52 40 lea 0x40(%rdx),%rdx - 43aae8: eb 96 jmp 43aa80 <__stpcpy_ssse3+0x1560> - 43aaea: 44 8b 49 fd mov -0x3(%rcx),%r9d - 43aaee: 48 c7 c6 01 00 00 00 mov $0x1,%rsi - 43aaf5: 44 89 4a fd mov %r9d,-0x3(%rdx) - 43aaf9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43ab00: 48 01 f2 add %rsi,%rdx - 43ab03: 48 01 f1 add %rsi,%rcx - 43ab06: 84 c0 test %al,%al - 43ab08: 74 56 je 43ab60 <__stpcpy_ssse3+0x1640> - 43ab0a: a8 01 test $0x1,%al - 43ab0c: 0f 85 ae 00 00 00 jne 43abc0 <__stpcpy_ssse3+0x16a0> - 43ab12: a8 02 test $0x2,%al - 43ab14: 0f 85 b6 00 00 00 jne 43abd0 <__stpcpy_ssse3+0x16b0> - 43ab1a: a8 04 test $0x4,%al - 43ab1c: 0f 85 be 00 00 00 jne 43abe0 <__stpcpy_ssse3+0x16c0> - 43ab22: a8 08 test $0x8,%al - 43ab24: 0f 85 d6 00 00 00 jne 43ac00 <__stpcpy_ssse3+0x16e0> - 43ab2a: a8 10 test $0x10,%al - 43ab2c: 0f 85 de 00 00 00 jne 43ac10 <__stpcpy_ssse3+0x16f0> - 43ab32: a8 20 test $0x20,%al - 43ab34: 0f 85 e6 00 00 00 jne 43ac20 <__stpcpy_ssse3+0x1700> - 43ab3a: a8 40 test $0x40,%al - 43ab3c: 0f 85 fe 00 00 00 jne 43ac40 <__stpcpy_ssse3+0x1720> - 43ab42: 0f 1f 40 00 nopl 0x0(%rax) - 43ab46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43ab4d: 00 00 00 - 43ab50: 48 8b 01 mov (%rcx),%rax - 43ab53: 48 89 02 mov %rax,(%rdx) - 43ab56: 48 8d 42 07 lea 0x7(%rdx),%rax - 43ab5a: c3 retq - 43ab5b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43ab60: f6 c4 01 test $0x1,%ah - 43ab63: 0f 85 e7 00 00 00 jne 43ac50 <__stpcpy_ssse3+0x1730> - 43ab69: f6 c4 02 test $0x2,%ah - 43ab6c: 0f 85 fe 00 00 00 jne 43ac70 <__stpcpy_ssse3+0x1750> - 43ab72: f6 c4 04 test $0x4,%ah - 43ab75: 0f 85 15 01 00 00 jne 43ac90 <__stpcpy_ssse3+0x1770> - 43ab7b: f6 c4 08 test $0x8,%ah - 43ab7e: 0f 85 2c 01 00 00 jne 43acb0 <__stpcpy_ssse3+0x1790> - 43ab84: f6 c4 10 test $0x10,%ah - 43ab87: 0f 85 43 01 00 00 jne 43acd0 <__stpcpy_ssse3+0x17b0> - 43ab8d: f6 c4 20 test $0x20,%ah - 43ab90: 0f 85 5a 01 00 00 jne 43acf0 <__stpcpy_ssse3+0x17d0> - 43ab96: f6 c4 40 test $0x40,%ah - 43ab99: 0f 85 71 01 00 00 jne 43ad10 <__stpcpy_ssse3+0x17f0> - 43ab9f: 90 nop - 43aba0: 48 8b 01 mov (%rcx),%rax - 43aba3: 48 89 02 mov %rax,(%rdx) - 43aba6: 48 8b 41 08 mov 0x8(%rcx),%rax - 43abaa: 48 89 42 08 mov %rax,0x8(%rdx) - 43abae: 48 8d 42 0f lea 0xf(%rdx),%rax - 43abb2: c3 retq - 43abb3: 0f 1f 00 nopl (%rax) - 43abb6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43abbd: 00 00 00 - 43abc0: 8a 01 mov (%rcx),%al - 43abc2: 88 02 mov %al,(%rdx) - 43abc4: 48 8d 02 lea (%rdx),%rax - 43abc7: c3 retq - 43abc8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 43abcf: 00 - 43abd0: 66 8b 01 mov (%rcx),%ax - 43abd3: 66 89 02 mov %ax,(%rdx) - 43abd6: 48 8d 42 01 lea 0x1(%rdx),%rax - 43abda: c3 retq - 43abdb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43abe0: 66 8b 01 mov (%rcx),%ax - 43abe3: 66 89 02 mov %ax,(%rdx) - 43abe6: 8a 41 02 mov 0x2(%rcx),%al - 43abe9: 88 42 02 mov %al,0x2(%rdx) - 43abec: 48 8d 42 02 lea 0x2(%rdx),%rax - 43abf0: c3 retq - 43abf1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43abf6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43abfd: 00 00 00 - 43ac00: 8b 01 mov (%rcx),%eax - 43ac02: 89 02 mov %eax,(%rdx) - 43ac04: 48 8d 42 03 lea 0x3(%rdx),%rax - 43ac08: c3 retq - 43ac09: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43ac10: 8b 01 mov (%rcx),%eax - 43ac12: 89 02 mov %eax,(%rdx) - 43ac14: 8a 41 04 mov 0x4(%rcx),%al - 43ac17: 88 42 04 mov %al,0x4(%rdx) - 43ac1a: 48 8d 42 04 lea 0x4(%rdx),%rax - 43ac1e: c3 retq - 43ac1f: 90 nop - 43ac20: 8b 01 mov (%rcx),%eax - 43ac22: 89 02 mov %eax,(%rdx) - 43ac24: 66 8b 41 04 mov 0x4(%rcx),%ax - 43ac28: 66 89 42 04 mov %ax,0x4(%rdx) - 43ac2c: 48 8d 42 05 lea 0x5(%rdx),%rax - 43ac30: c3 retq - 43ac31: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43ac36: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43ac3d: 00 00 00 - 43ac40: 8b 01 mov (%rcx),%eax - 43ac42: 89 02 mov %eax,(%rdx) - 43ac44: 8b 41 03 mov 0x3(%rcx),%eax - 43ac47: 89 42 03 mov %eax,0x3(%rdx) - 43ac4a: 48 8d 42 06 lea 0x6(%rdx),%rax - 43ac4e: c3 retq - 43ac4f: 90 nop - 43ac50: 48 8b 01 mov (%rcx),%rax - 43ac53: 48 89 02 mov %rax,(%rdx) - 43ac56: 8b 41 05 mov 0x5(%rcx),%eax - 43ac59: 89 42 05 mov %eax,0x5(%rdx) - 43ac5c: 48 8d 42 08 lea 0x8(%rdx),%rax - 43ac60: c3 retq - 43ac61: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43ac66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43ac6d: 00 00 00 - 43ac70: 48 8b 01 mov (%rcx),%rax - 43ac73: 48 89 02 mov %rax,(%rdx) - 43ac76: 8b 41 06 mov 0x6(%rcx),%eax - 43ac79: 89 42 06 mov %eax,0x6(%rdx) - 43ac7c: 48 8d 42 09 lea 0x9(%rdx),%rax - 43ac80: c3 retq - 43ac81: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43ac86: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43ac8d: 00 00 00 - 43ac90: 48 8b 01 mov (%rcx),%rax - 43ac93: 48 89 02 mov %rax,(%rdx) - 43ac96: 8b 41 07 mov 0x7(%rcx),%eax - 43ac99: 89 42 07 mov %eax,0x7(%rdx) - 43ac9c: 48 8d 42 0a lea 0xa(%rdx),%rax - 43aca0: c3 retq - 43aca1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43aca6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43acad: 00 00 00 - 43acb0: 48 8b 01 mov (%rcx),%rax - 43acb3: 48 89 02 mov %rax,(%rdx) - 43acb6: 8b 41 08 mov 0x8(%rcx),%eax - 43acb9: 89 42 08 mov %eax,0x8(%rdx) - 43acbc: 48 8d 42 0b lea 0xb(%rdx),%rax - 43acc0: c3 retq - 43acc1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43acc6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43accd: 00 00 00 - 43acd0: 48 8b 01 mov (%rcx),%rax - 43acd3: 48 89 02 mov %rax,(%rdx) - 43acd6: 48 8b 41 05 mov 0x5(%rcx),%rax - 43acda: 48 89 42 05 mov %rax,0x5(%rdx) - 43acde: 48 8d 42 0c lea 0xc(%rdx),%rax - 43ace2: c3 retq - 43ace3: 0f 1f 00 nopl (%rax) - 43ace6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43aced: 00 00 00 - 43acf0: 48 8b 01 mov (%rcx),%rax - 43acf3: 48 89 02 mov %rax,(%rdx) - 43acf6: 48 8b 41 06 mov 0x6(%rcx),%rax - 43acfa: 48 89 42 06 mov %rax,0x6(%rdx) - 43acfe: 48 8d 42 0d lea 0xd(%rdx),%rax - 43ad02: c3 retq - 43ad03: 0f 1f 00 nopl (%rax) - 43ad06: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43ad0d: 00 00 00 - 43ad10: 48 8b 01 mov (%rcx),%rax - 43ad13: 48 89 02 mov %rax,(%rdx) - 43ad16: 48 8b 41 07 mov 0x7(%rcx),%rax - 43ad1a: 48 89 42 07 mov %rax,0x7(%rdx) - 43ad1e: 48 8d 42 0e lea 0xe(%rdx),%rax - 43ad22: c3 retq - 43ad23: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43ad2a: 00 00 00 - 43ad2d: 0f 1f 00 nopl (%rax) - -000000000043ad30 <__strcpy_sse2_unaligned>: - 43ad30: 48 89 f1 mov %rsi,%rcx - 43ad33: 48 89 f8 mov %rdi,%rax - 43ad36: 48 83 e1 3f and $0x3f,%rcx - 43ad3a: 48 83 f9 20 cmp $0x20,%rcx - 43ad3e: 0f 86 0f 02 00 00 jbe 43af53 <__strcpy_sse2_unaligned+0x223> - 43ad44: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi - 43ad48: 48 83 e1 0f and $0xf,%rcx - 43ad4c: 66 0f ef c0 pxor %xmm0,%xmm0 - 43ad50: 66 0f ef c9 pxor %xmm1,%xmm1 - 43ad54: 66 0f 74 0e pcmpeqb (%rsi),%xmm1 - 43ad58: 66 0f d7 d1 pmovmskb %xmm1,%edx - 43ad5c: 48 d3 ea shr %cl,%rdx - 43ad5f: 48 85 d2 test %rdx,%rdx - 43ad62: 0f 85 48 02 00 00 jne 43afb0 <__strcpy_sse2_unaligned+0x280> - 43ad68: 66 0f 74 46 10 pcmpeqb 0x10(%rsi),%xmm0 - 43ad6d: 66 0f d7 d0 pmovmskb %xmm0,%edx - 43ad71: 48 85 d2 test %rdx,%rdx - 43ad74: 0f 85 76 02 00 00 jne 43aff0 <__strcpy_sse2_unaligned+0x2c0> - 43ad7a: f3 0f 6f 0c 0e movdqu (%rsi,%rcx,1),%xmm1 - 43ad7f: f3 0f 7f 0f movdqu %xmm1,(%rdi) - 43ad83: 0f 1f 00 nopl (%rax) - 43ad86: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43ad8d: 00 00 00 - 43ad90: 48 29 cf sub %rcx,%rdi - 43ad93: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 43ad9a: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 43ad9f: 0f 28 54 0e 10 movaps 0x10(%rsi,%rcx,1),%xmm2 - 43ada4: f3 0f 7f 0c 0f movdqu %xmm1,(%rdi,%rcx,1) - 43ada9: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43adad: 66 0f d7 d0 pmovmskb %xmm0,%edx - 43adb1: 48 83 c1 10 add $0x10,%rcx - 43adb5: 48 85 d2 test %rdx,%rdx - 43adb8: 0f 85 d2 01 00 00 jne 43af90 <__strcpy_sse2_unaligned+0x260> - 43adbe: 0f 28 5c 0e 10 movaps 0x10(%rsi,%rcx,1),%xmm3 - 43adc3: f3 0f 7f 14 0f movdqu %xmm2,(%rdi,%rcx,1) - 43adc8: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 43adcc: 66 0f d7 d0 pmovmskb %xmm0,%edx - 43add0: 48 83 c1 10 add $0x10,%rcx - 43add4: 48 85 d2 test %rdx,%rdx - 43add7: 0f 85 b3 01 00 00 jne 43af90 <__strcpy_sse2_unaligned+0x260> - 43addd: 0f 28 64 0e 10 movaps 0x10(%rsi,%rcx,1),%xmm4 - 43ade2: f3 0f 7f 1c 0f movdqu %xmm3,(%rdi,%rcx,1) - 43ade7: 66 0f 74 c4 pcmpeqb %xmm4,%xmm0 - 43adeb: 66 0f d7 d0 pmovmskb %xmm0,%edx - 43adef: 48 83 c1 10 add $0x10,%rcx - 43adf3: 48 85 d2 test %rdx,%rdx - 43adf6: 0f 85 94 01 00 00 jne 43af90 <__strcpy_sse2_unaligned+0x260> - 43adfc: 0f 28 4c 0e 10 movaps 0x10(%rsi,%rcx,1),%xmm1 - 43ae01: f3 0f 7f 24 0f movdqu %xmm4,(%rdi,%rcx,1) - 43ae06: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 43ae0a: 66 0f d7 d0 pmovmskb %xmm0,%edx - 43ae0e: 48 83 c1 10 add $0x10,%rcx - 43ae12: 48 85 d2 test %rdx,%rdx - 43ae15: 0f 85 75 01 00 00 jne 43af90 <__strcpy_sse2_unaligned+0x260> - 43ae1b: 0f 28 54 0e 10 movaps 0x10(%rsi,%rcx,1),%xmm2 - 43ae20: f3 0f 7f 0c 0f movdqu %xmm1,(%rdi,%rcx,1) - 43ae25: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43ae29: 66 0f d7 d0 pmovmskb %xmm0,%edx - 43ae2d: 48 83 c1 10 add $0x10,%rcx - 43ae31: 48 85 d2 test %rdx,%rdx - 43ae34: 0f 85 56 01 00 00 jne 43af90 <__strcpy_sse2_unaligned+0x260> - 43ae3a: 0f 28 5c 0e 10 movaps 0x10(%rsi,%rcx,1),%xmm3 - 43ae3f: f3 0f 7f 14 0f movdqu %xmm2,(%rdi,%rcx,1) - 43ae44: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 43ae48: 66 0f d7 d0 pmovmskb %xmm0,%edx - 43ae4c: 48 83 c1 10 add $0x10,%rcx - 43ae50: 48 85 d2 test %rdx,%rdx - 43ae53: 0f 85 37 01 00 00 jne 43af90 <__strcpy_sse2_unaligned+0x260> - 43ae59: f3 0f 7f 1c 0f movdqu %xmm3,(%rdi,%rcx,1) - 43ae5e: 48 89 f2 mov %rsi,%rdx - 43ae61: 48 8d 74 0e 10 lea 0x10(%rsi,%rcx,1),%rsi - 43ae66: 48 83 e6 c0 and $0xffffffffffffffc0,%rsi - 43ae6a: 48 29 f2 sub %rsi,%rdx - 43ae6d: 48 29 d7 sub %rdx,%rdi - 43ae70: 0f 28 16 movaps (%rsi),%xmm2 - 43ae73: 0f 28 e2 movaps %xmm2,%xmm4 - 43ae76: 0f 28 6e 10 movaps 0x10(%rsi),%xmm5 - 43ae7a: 0f 28 5e 20 movaps 0x20(%rsi),%xmm3 - 43ae7e: 0f 28 f3 movaps %xmm3,%xmm6 - 43ae81: 0f 28 7e 30 movaps 0x30(%rsi),%xmm7 - 43ae85: 66 0f da d5 pminub %xmm5,%xmm2 - 43ae89: 66 0f da df pminub %xmm7,%xmm3 - 43ae8d: 66 0f da da pminub %xmm2,%xmm3 - 43ae91: 66 0f 74 d8 pcmpeqb %xmm0,%xmm3 - 43ae95: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43ae99: 48 85 d2 test %rdx,%rdx - 43ae9c: 75 4b jne 43aee9 <__strcpy_sse2_unaligned+0x1b9> - 43ae9e: 48 83 c7 40 add $0x40,%rdi - 43aea2: 48 83 c6 40 add $0x40,%rsi - 43aea6: f3 0f 7f 67 c0 movdqu %xmm4,-0x40(%rdi) - 43aeab: 0f 28 16 movaps (%rsi),%xmm2 - 43aeae: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 43aeb2: f3 0f 7f 6f d0 movdqu %xmm5,-0x30(%rdi) - 43aeb7: 0f 28 6e 10 movaps 0x10(%rsi),%xmm5 - 43aebb: 66 0f da d5 pminub %xmm5,%xmm2 - 43aebf: 0f 28 5e 20 movaps 0x20(%rsi),%xmm3 - 43aec3: f3 0f 7f 77 e0 movdqu %xmm6,-0x20(%rdi) - 43aec8: 0f 28 f3 movaps %xmm3,%xmm6 - 43aecb: f3 0f 7f 7f f0 movdqu %xmm7,-0x10(%rdi) - 43aed0: 0f 28 7e 30 movaps 0x30(%rsi),%xmm7 - 43aed4: 66 0f da df pminub %xmm7,%xmm3 - 43aed8: 66 0f da da pminub %xmm2,%xmm3 - 43aedc: 66 0f 74 d8 pcmpeqb %xmm0,%xmm3 - 43aee0: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43aee4: 48 85 d2 test %rdx,%rdx - 43aee7: 74 b5 je 43ae9e <__strcpy_sse2_unaligned+0x16e> - 43aee9: 66 0f ef c9 pxor %xmm1,%xmm1 - 43aeed: 66 0f 74 c4 pcmpeqb %xmm4,%xmm0 - 43aef1: 66 0f 74 cd pcmpeqb %xmm5,%xmm1 - 43aef5: 66 0f d7 d0 pmovmskb %xmm0,%edx - 43aef9: 66 0f d7 c9 pmovmskb %xmm1,%ecx - 43aefd: 48 85 d2 test %rdx,%rdx - 43af00: 0f 85 0a 01 00 00 jne 43b010 <__strcpy_sse2_unaligned+0x2e0> - 43af06: 48 85 c9 test %rcx,%rcx - 43af09: 0f 85 21 01 00 00 jne 43b030 <__strcpy_sse2_unaligned+0x300> - 43af0f: 66 0f 74 c6 pcmpeqb %xmm6,%xmm0 - 43af13: 66 0f 74 cf pcmpeqb %xmm7,%xmm1 - 43af17: 66 0f d7 d0 pmovmskb %xmm0,%edx - 43af1b: 66 0f d7 c9 pmovmskb %xmm1,%ecx - 43af1f: 48 85 d2 test %rdx,%rdx - 43af22: 0f 85 38 01 00 00 jne 43b060 <__strcpy_sse2_unaligned+0x330> - 43af28: 48 0f bc d1 bsf %rcx,%rdx - 43af2c: f3 0f 7f 27 movdqu %xmm4,(%rdi) - 43af30: f3 0f 7f 6f 10 movdqu %xmm5,0x10(%rdi) - 43af35: f3 0f 7f 77 20 movdqu %xmm6,0x20(%rdi) - 43af3a: 48 83 c6 30 add $0x30,%rsi - 43af3e: 48 83 c7 30 add $0x30,%rdi - 43af42: 4c 8d 1d 67 8b 06 00 lea 0x68b67(%rip),%r11 # 4a3ab0 - 43af49: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx - 43af4d: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx - 43af51: ff e1 jmpq *%rcx - 43af53: 66 0f ef c0 pxor %xmm0,%xmm0 - 43af57: f3 0f 6f 0e movdqu (%rsi),%xmm1 - 43af5b: f3 0f 6f 56 10 movdqu 0x10(%rsi),%xmm2 - 43af60: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 43af64: 66 0f d7 d0 pmovmskb %xmm0,%edx - 43af68: 48 85 d2 test %rdx,%rdx - 43af6b: 75 6b jne 43afd8 <__strcpy_sse2_unaligned+0x2a8> - 43af6d: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43af71: f3 0f 7f 0f movdqu %xmm1,(%rdi) - 43af75: 66 0f d7 d0 pmovmskb %xmm0,%edx - 43af79: 48 85 d2 test %rdx,%rdx - 43af7c: 75 52 jne 43afd0 <__strcpy_sse2_unaligned+0x2a0> - 43af7e: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi - 43af82: 48 83 e1 0f and $0xf,%rcx - 43af86: e9 05 fe ff ff jmpq 43ad90 <__strcpy_sse2_unaligned+0x60> - 43af8b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43af90: 48 01 cf add %rcx,%rdi - 43af93: 48 01 ce add %rcx,%rsi - 43af96: 48 0f bc d2 bsf %rdx,%rdx - 43af9a: 4c 8d 1d 0f 8b 06 00 lea 0x68b0f(%rip),%r11 # 4a3ab0 - 43afa1: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx - 43afa5: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx - 43afa9: ff e1 jmpq *%rcx - 43afab: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43afb0: 48 01 ce add %rcx,%rsi - 43afb3: 48 0f bc d2 bsf %rdx,%rdx - 43afb7: 4c 8d 1d f2 8a 06 00 lea 0x68af2(%rip),%r11 # 4a3ab0 - 43afbe: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx - 43afc2: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx - 43afc6: ff e1 jmpq *%rcx - 43afc8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 43afcf: 00 - 43afd0: 48 83 c6 10 add $0x10,%rsi - 43afd4: 48 83 c7 10 add $0x10,%rdi - 43afd8: 48 0f bc d2 bsf %rdx,%rdx - 43afdc: 4c 8d 1d cd 8a 06 00 lea 0x68acd(%rip),%r11 # 4a3ab0 - 43afe3: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx - 43afe7: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx - 43afeb: ff e1 jmpq *%rcx - 43afed: 0f 1f 00 nopl (%rax) - 43aff0: 48 0f bc d2 bsf %rdx,%rdx - 43aff4: 48 01 ce add %rcx,%rsi - 43aff7: 48 83 c2 10 add $0x10,%rdx - 43affb: 48 29 ca sub %rcx,%rdx - 43affe: 4c 8d 1d ab 8a 06 00 lea 0x68aab(%rip),%r11 # 4a3ab0 - 43b005: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx - 43b009: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx - 43b00d: ff e1 jmpq *%rcx - 43b00f: 90 nop - 43b010: 48 0f bc d2 bsf %rdx,%rdx - 43b014: 4c 8d 1d 95 8a 06 00 lea 0x68a95(%rip),%r11 # 4a3ab0 - 43b01b: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx - 43b01f: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx - 43b023: ff e1 jmpq *%rcx - 43b025: 90 nop - 43b026: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b02d: 00 00 00 - 43b030: 48 0f bc d1 bsf %rcx,%rdx - 43b034: f3 0f 7f 27 movdqu %xmm4,(%rdi) - 43b038: 48 83 c6 10 add $0x10,%rsi - 43b03c: 48 83 c7 10 add $0x10,%rdi - 43b040: 4c 8d 1d 69 8a 06 00 lea 0x68a69(%rip),%r11 # 4a3ab0 - 43b047: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx - 43b04b: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx - 43b04f: ff e1 jmpq *%rcx - 43b051: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43b056: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b05d: 00 00 00 - 43b060: 48 0f bc d2 bsf %rdx,%rdx - 43b064: f3 0f 7f 27 movdqu %xmm4,(%rdi) - 43b068: f3 0f 7f 6f 10 movdqu %xmm5,0x10(%rdi) - 43b06d: 48 83 c6 20 add $0x20,%rsi - 43b071: 48 83 c7 20 add $0x20,%rdi - 43b075: 4c 8d 1d 34 8a 06 00 lea 0x68a34(%rip),%r11 # 4a3ab0 - 43b07c: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx - 43b080: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx - 43b084: ff e1 jmpq *%rcx - 43b086: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b08d: 00 00 00 - 43b090: 88 37 mov %dh,(%rdi) - 43b092: c3 retq - 43b093: 0f 1f 00 nopl (%rax) - 43b096: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b09d: 00 00 00 - 43b0a0: 66 8b 16 mov (%rsi),%dx - 43b0a3: 66 89 17 mov %dx,(%rdi) - 43b0a6: c3 retq - 43b0a7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 43b0ae: 00 00 - 43b0b0: 66 8b 0e mov (%rsi),%cx - 43b0b3: 66 89 0f mov %cx,(%rdi) - 43b0b6: 88 77 02 mov %dh,0x2(%rdi) - 43b0b9: c3 retq - 43b0ba: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43b0c0: 8b 16 mov (%rsi),%edx - 43b0c2: 89 17 mov %edx,(%rdi) - 43b0c4: c3 retq - 43b0c5: 90 nop - 43b0c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b0cd: 00 00 00 - 43b0d0: 8b 0e mov (%rsi),%ecx - 43b0d2: 88 77 04 mov %dh,0x4(%rdi) - 43b0d5: 89 0f mov %ecx,(%rdi) - 43b0d7: c3 retq - 43b0d8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 43b0df: 00 - 43b0e0: 8b 0e mov (%rsi),%ecx - 43b0e2: 66 8b 56 04 mov 0x4(%rsi),%dx - 43b0e6: 89 0f mov %ecx,(%rdi) - 43b0e8: 66 89 57 04 mov %dx,0x4(%rdi) - 43b0ec: c3 retq - 43b0ed: 0f 1f 00 nopl (%rax) - 43b0f0: 8b 0e mov (%rsi),%ecx - 43b0f2: 8b 56 03 mov 0x3(%rsi),%edx - 43b0f5: 89 0f mov %ecx,(%rdi) - 43b0f7: 89 57 03 mov %edx,0x3(%rdi) - 43b0fa: c3 retq - 43b0fb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43b100: 48 8b 16 mov (%rsi),%rdx - 43b103: 48 89 17 mov %rdx,(%rdi) - 43b106: c3 retq - 43b107: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 43b10e: 00 00 - 43b110: 48 8b 0e mov (%rsi),%rcx - 43b113: 88 77 08 mov %dh,0x8(%rdi) - 43b116: 48 89 0f mov %rcx,(%rdi) - 43b119: c3 retq - 43b11a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43b120: 48 8b 0e mov (%rsi),%rcx - 43b123: 66 8b 56 08 mov 0x8(%rsi),%dx - 43b127: 48 89 0f mov %rcx,(%rdi) - 43b12a: 66 89 57 08 mov %dx,0x8(%rdi) - 43b12e: c3 retq - 43b12f: 90 nop - 43b130: 48 8b 0e mov (%rsi),%rcx - 43b133: 8b 56 07 mov 0x7(%rsi),%edx - 43b136: 48 89 0f mov %rcx,(%rdi) - 43b139: 89 57 07 mov %edx,0x7(%rdi) - 43b13c: c3 retq - 43b13d: 0f 1f 00 nopl (%rax) - 43b140: 48 8b 0e mov (%rsi),%rcx - 43b143: 8b 56 08 mov 0x8(%rsi),%edx - 43b146: 48 89 0f mov %rcx,(%rdi) - 43b149: 89 57 08 mov %edx,0x8(%rdi) - 43b14c: c3 retq - 43b14d: 0f 1f 00 nopl (%rax) - 43b150: 48 8b 0e mov (%rsi),%rcx - 43b153: 48 8b 56 05 mov 0x5(%rsi),%rdx - 43b157: 48 89 0f mov %rcx,(%rdi) - 43b15a: 48 89 57 05 mov %rdx,0x5(%rdi) - 43b15e: c3 retq - 43b15f: 90 nop - 43b160: 48 8b 0e mov (%rsi),%rcx - 43b163: 48 8b 56 06 mov 0x6(%rsi),%rdx - 43b167: 48 89 0f mov %rcx,(%rdi) - 43b16a: 48 89 57 06 mov %rdx,0x6(%rdi) - 43b16e: c3 retq - 43b16f: 90 nop - 43b170: 48 8b 0e mov (%rsi),%rcx - 43b173: 48 8b 56 07 mov 0x7(%rsi),%rdx - 43b177: 48 89 0f mov %rcx,(%rdi) - 43b17a: 48 89 57 07 mov %rdx,0x7(%rdi) - 43b17e: c3 retq - 43b17f: 90 nop - 43b180: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b184: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b188: c3 retq - 43b189: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43b190: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b194: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b198: 88 77 10 mov %dh,0x10(%rdi) - 43b19b: c3 retq - 43b19c: 0f 1f 40 00 nopl 0x0(%rax) - 43b1a0: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b1a4: 66 8b 4e 10 mov 0x10(%rsi),%cx - 43b1a8: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b1ac: 66 89 4f 10 mov %cx,0x10(%rdi) - 43b1b0: c3 retq - 43b1b1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43b1b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b1bd: 00 00 00 - 43b1c0: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b1c4: 8b 4e 0f mov 0xf(%rsi),%ecx - 43b1c7: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b1cb: 89 4f 0f mov %ecx,0xf(%rdi) - 43b1ce: c3 retq - 43b1cf: 90 nop - 43b1d0: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b1d4: 8b 4e 10 mov 0x10(%rsi),%ecx - 43b1d7: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b1db: 89 4f 10 mov %ecx,0x10(%rdi) - 43b1de: c3 retq - 43b1df: 90 nop - 43b1e0: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b1e4: 8b 4e 10 mov 0x10(%rsi),%ecx - 43b1e7: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b1eb: 89 4f 10 mov %ecx,0x10(%rdi) - 43b1ee: 88 77 14 mov %dh,0x14(%rdi) - 43b1f1: c3 retq - 43b1f2: 0f 1f 40 00 nopl 0x0(%rax) - 43b1f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b1fd: 00 00 00 - 43b200: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b204: 48 8b 4e 0e mov 0xe(%rsi),%rcx - 43b208: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b20c: 48 89 4f 0e mov %rcx,0xe(%rdi) - 43b210: c3 retq - 43b211: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43b216: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b21d: 00 00 00 - 43b220: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b224: 48 8b 4e 0f mov 0xf(%rsi),%rcx - 43b228: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b22c: 48 89 4f 0f mov %rcx,0xf(%rdi) - 43b230: c3 retq - 43b231: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43b236: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b23d: 00 00 00 - 43b240: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b244: 48 8b 4e 10 mov 0x10(%rsi),%rcx - 43b248: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b24c: 48 89 4f 10 mov %rcx,0x10(%rdi) - 43b250: c3 retq - 43b251: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43b256: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b25d: 00 00 00 - 43b260: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b264: 48 8b 4e 10 mov 0x10(%rsi),%rcx - 43b268: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b26c: 48 89 4f 10 mov %rcx,0x10(%rdi) - 43b270: 88 77 18 mov %dh,0x18(%rdi) - 43b273: c3 retq - 43b274: 66 90 xchg %ax,%ax - 43b276: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b27d: 00 00 00 - 43b280: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b284: 48 8b 56 10 mov 0x10(%rsi),%rdx - 43b288: 66 8b 4e 18 mov 0x18(%rsi),%cx - 43b28c: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b290: 48 89 57 10 mov %rdx,0x10(%rdi) - 43b294: 66 89 4f 18 mov %cx,0x18(%rdi) - 43b298: c3 retq - 43b299: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43b2a0: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b2a4: 48 8b 56 10 mov 0x10(%rsi),%rdx - 43b2a8: 8b 4e 17 mov 0x17(%rsi),%ecx - 43b2ab: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b2af: 48 89 57 10 mov %rdx,0x10(%rdi) - 43b2b3: 89 4f 17 mov %ecx,0x17(%rdi) - 43b2b6: c3 retq - 43b2b7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 43b2be: 00 00 - 43b2c0: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b2c4: 48 8b 56 10 mov 0x10(%rsi),%rdx - 43b2c8: 8b 4e 18 mov 0x18(%rsi),%ecx - 43b2cb: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b2cf: 48 89 57 10 mov %rdx,0x10(%rdi) - 43b2d3: 89 4f 18 mov %ecx,0x18(%rdi) - 43b2d6: c3 retq - 43b2d7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 43b2de: 00 00 - 43b2e0: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b2e4: f3 0f 6f 56 0d movdqu 0xd(%rsi),%xmm2 - 43b2e9: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b2ed: f3 0f 7f 57 0d movdqu %xmm2,0xd(%rdi) - 43b2f2: c3 retq - 43b2f3: 0f 1f 00 nopl (%rax) - 43b2f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b2fd: 00 00 00 - 43b300: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b304: f3 0f 6f 56 0e movdqu 0xe(%rsi),%xmm2 - 43b309: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b30d: f3 0f 7f 57 0e movdqu %xmm2,0xe(%rdi) - 43b312: c3 retq - 43b313: 0f 1f 00 nopl (%rax) - 43b316: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b31d: 00 00 00 - 43b320: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b324: f3 0f 6f 56 0f movdqu 0xf(%rsi),%xmm2 - 43b329: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b32d: f3 0f 7f 57 0f movdqu %xmm2,0xf(%rdi) - 43b332: c3 retq - 43b333: 0f 1f 00 nopl (%rax) - 43b336: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b33d: 00 00 00 - 43b340: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b344: f3 0f 6f 56 10 movdqu 0x10(%rsi),%xmm2 - 43b349: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b34d: f3 0f 7f 57 10 movdqu %xmm2,0x10(%rdi) - 43b352: c3 retq - 43b353: 0f 1f 00 nopl (%rax) - 43b356: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b35d: 00 00 00 - -000000000043b360 <__stpcpy_sse2_unaligned>: - 43b360: 48 89 f1 mov %rsi,%rcx - 43b363: 48 83 e1 3f and $0x3f,%rcx - 43b367: 48 83 f9 20 cmp $0x20,%rcx - 43b36b: 0f 86 02 02 00 00 jbe 43b573 <__stpcpy_sse2_unaligned+0x213> - 43b371: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi - 43b375: 48 83 e1 0f and $0xf,%rcx - 43b379: 66 0f ef c0 pxor %xmm0,%xmm0 - 43b37d: 66 0f ef c9 pxor %xmm1,%xmm1 - 43b381: 66 0f 74 0e pcmpeqb (%rsi),%xmm1 - 43b385: 66 0f d7 d1 pmovmskb %xmm1,%edx - 43b389: 48 d3 ea shr %cl,%rdx - 43b38c: 48 85 d2 test %rdx,%rdx - 43b38f: 0f 85 3b 02 00 00 jne 43b5d0 <__stpcpy_sse2_unaligned+0x270> - 43b395: 66 0f 74 46 10 pcmpeqb 0x10(%rsi),%xmm0 - 43b39a: 66 0f d7 d0 pmovmskb %xmm0,%edx - 43b39e: 48 85 d2 test %rdx,%rdx - 43b3a1: 0f 85 69 02 00 00 jne 43b610 <__stpcpy_sse2_unaligned+0x2b0> - 43b3a7: f3 0f 6f 0c 0e movdqu (%rsi,%rcx,1),%xmm1 - 43b3ac: f3 0f 7f 0f movdqu %xmm1,(%rdi) - 43b3b0: 48 29 cf sub %rcx,%rdi - 43b3b3: 48 c7 c1 10 00 00 00 mov $0x10,%rcx - 43b3ba: 66 0f 6f 0c 0e movdqa (%rsi,%rcx,1),%xmm1 - 43b3bf: 0f 28 54 0e 10 movaps 0x10(%rsi,%rcx,1),%xmm2 - 43b3c4: f3 0f 7f 0c 0f movdqu %xmm1,(%rdi,%rcx,1) - 43b3c9: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43b3cd: 66 0f d7 d0 pmovmskb %xmm0,%edx - 43b3d1: 48 83 c1 10 add $0x10,%rcx - 43b3d5: 48 85 d2 test %rdx,%rdx - 43b3d8: 0f 85 d2 01 00 00 jne 43b5b0 <__stpcpy_sse2_unaligned+0x250> - 43b3de: 0f 28 5c 0e 10 movaps 0x10(%rsi,%rcx,1),%xmm3 - 43b3e3: f3 0f 7f 14 0f movdqu %xmm2,(%rdi,%rcx,1) - 43b3e8: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 43b3ec: 66 0f d7 d0 pmovmskb %xmm0,%edx - 43b3f0: 48 83 c1 10 add $0x10,%rcx - 43b3f4: 48 85 d2 test %rdx,%rdx - 43b3f7: 0f 85 b3 01 00 00 jne 43b5b0 <__stpcpy_sse2_unaligned+0x250> - 43b3fd: 0f 28 64 0e 10 movaps 0x10(%rsi,%rcx,1),%xmm4 - 43b402: f3 0f 7f 1c 0f movdqu %xmm3,(%rdi,%rcx,1) - 43b407: 66 0f 74 c4 pcmpeqb %xmm4,%xmm0 - 43b40b: 66 0f d7 d0 pmovmskb %xmm0,%edx - 43b40f: 48 83 c1 10 add $0x10,%rcx - 43b413: 48 85 d2 test %rdx,%rdx - 43b416: 0f 85 94 01 00 00 jne 43b5b0 <__stpcpy_sse2_unaligned+0x250> - 43b41c: 0f 28 4c 0e 10 movaps 0x10(%rsi,%rcx,1),%xmm1 - 43b421: f3 0f 7f 24 0f movdqu %xmm4,(%rdi,%rcx,1) - 43b426: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 43b42a: 66 0f d7 d0 pmovmskb %xmm0,%edx - 43b42e: 48 83 c1 10 add $0x10,%rcx - 43b432: 48 85 d2 test %rdx,%rdx - 43b435: 0f 85 75 01 00 00 jne 43b5b0 <__stpcpy_sse2_unaligned+0x250> - 43b43b: 0f 28 54 0e 10 movaps 0x10(%rsi,%rcx,1),%xmm2 - 43b440: f3 0f 7f 0c 0f movdqu %xmm1,(%rdi,%rcx,1) - 43b445: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43b449: 66 0f d7 d0 pmovmskb %xmm0,%edx - 43b44d: 48 83 c1 10 add $0x10,%rcx - 43b451: 48 85 d2 test %rdx,%rdx - 43b454: 0f 85 56 01 00 00 jne 43b5b0 <__stpcpy_sse2_unaligned+0x250> - 43b45a: 0f 28 5c 0e 10 movaps 0x10(%rsi,%rcx,1),%xmm3 - 43b45f: f3 0f 7f 14 0f movdqu %xmm2,(%rdi,%rcx,1) - 43b464: 66 0f 74 c3 pcmpeqb %xmm3,%xmm0 - 43b468: 66 0f d7 d0 pmovmskb %xmm0,%edx - 43b46c: 48 83 c1 10 add $0x10,%rcx - 43b470: 48 85 d2 test %rdx,%rdx - 43b473: 0f 85 37 01 00 00 jne 43b5b0 <__stpcpy_sse2_unaligned+0x250> - 43b479: f3 0f 7f 1c 0f movdqu %xmm3,(%rdi,%rcx,1) - 43b47e: 48 89 f2 mov %rsi,%rdx - 43b481: 48 8d 74 0e 10 lea 0x10(%rsi,%rcx,1),%rsi - 43b486: 48 83 e6 c0 and $0xffffffffffffffc0,%rsi - 43b48a: 48 29 f2 sub %rsi,%rdx - 43b48d: 48 29 d7 sub %rdx,%rdi - 43b490: 0f 28 16 movaps (%rsi),%xmm2 - 43b493: 0f 28 e2 movaps %xmm2,%xmm4 - 43b496: 0f 28 6e 10 movaps 0x10(%rsi),%xmm5 - 43b49a: 0f 28 5e 20 movaps 0x20(%rsi),%xmm3 - 43b49e: 0f 28 f3 movaps %xmm3,%xmm6 - 43b4a1: 0f 28 7e 30 movaps 0x30(%rsi),%xmm7 - 43b4a5: 66 0f da d5 pminub %xmm5,%xmm2 - 43b4a9: 66 0f da df pminub %xmm7,%xmm3 - 43b4ad: 66 0f da da pminub %xmm2,%xmm3 - 43b4b1: 66 0f 74 d8 pcmpeqb %xmm0,%xmm3 - 43b4b5: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43b4b9: 48 85 d2 test %rdx,%rdx - 43b4bc: 75 4b jne 43b509 <__stpcpy_sse2_unaligned+0x1a9> - 43b4be: 48 83 c7 40 add $0x40,%rdi - 43b4c2: 48 83 c6 40 add $0x40,%rsi - 43b4c6: f3 0f 7f 67 c0 movdqu %xmm4,-0x40(%rdi) - 43b4cb: 0f 28 16 movaps (%rsi),%xmm2 - 43b4ce: 66 0f 6f e2 movdqa %xmm2,%xmm4 - 43b4d2: f3 0f 7f 6f d0 movdqu %xmm5,-0x30(%rdi) - 43b4d7: 0f 28 6e 10 movaps 0x10(%rsi),%xmm5 - 43b4db: 66 0f da d5 pminub %xmm5,%xmm2 - 43b4df: 0f 28 5e 20 movaps 0x20(%rsi),%xmm3 - 43b4e3: f3 0f 7f 77 e0 movdqu %xmm6,-0x20(%rdi) - 43b4e8: 0f 28 f3 movaps %xmm3,%xmm6 - 43b4eb: f3 0f 7f 7f f0 movdqu %xmm7,-0x10(%rdi) - 43b4f0: 0f 28 7e 30 movaps 0x30(%rsi),%xmm7 - 43b4f4: 66 0f da df pminub %xmm7,%xmm3 - 43b4f8: 66 0f da da pminub %xmm2,%xmm3 - 43b4fc: 66 0f 74 d8 pcmpeqb %xmm0,%xmm3 - 43b500: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43b504: 48 85 d2 test %rdx,%rdx - 43b507: 74 b5 je 43b4be <__stpcpy_sse2_unaligned+0x15e> - 43b509: 66 0f ef c9 pxor %xmm1,%xmm1 - 43b50d: 66 0f 74 c4 pcmpeqb %xmm4,%xmm0 - 43b511: 66 0f 74 cd pcmpeqb %xmm5,%xmm1 - 43b515: 66 0f d7 d0 pmovmskb %xmm0,%edx - 43b519: 66 0f d7 c9 pmovmskb %xmm1,%ecx - 43b51d: 48 85 d2 test %rdx,%rdx - 43b520: 0f 85 0a 01 00 00 jne 43b630 <__stpcpy_sse2_unaligned+0x2d0> - 43b526: 48 85 c9 test %rcx,%rcx - 43b529: 0f 85 21 01 00 00 jne 43b650 <__stpcpy_sse2_unaligned+0x2f0> - 43b52f: 66 0f 74 c6 pcmpeqb %xmm6,%xmm0 - 43b533: 66 0f 74 cf pcmpeqb %xmm7,%xmm1 - 43b537: 66 0f d7 d0 pmovmskb %xmm0,%edx - 43b53b: 66 0f d7 c9 pmovmskb %xmm1,%ecx - 43b53f: 48 85 d2 test %rdx,%rdx - 43b542: 0f 85 38 01 00 00 jne 43b680 <__stpcpy_sse2_unaligned+0x320> - 43b548: 48 0f bc d1 bsf %rcx,%rdx - 43b54c: f3 0f 7f 27 movdqu %xmm4,(%rdi) - 43b550: f3 0f 7f 6f 10 movdqu %xmm5,0x10(%rdi) - 43b555: f3 0f 7f 77 20 movdqu %xmm6,0x20(%rdi) - 43b55a: 48 83 c6 30 add $0x30,%rsi - 43b55e: 48 83 c7 30 add $0x30,%rdi - 43b562: 4c 8d 1d c7 85 06 00 lea 0x685c7(%rip),%r11 # 4a3b30 - 43b569: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx - 43b56d: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx - 43b571: ff e1 jmpq *%rcx - 43b573: 66 0f ef c0 pxor %xmm0,%xmm0 - 43b577: f3 0f 6f 0e movdqu (%rsi),%xmm1 - 43b57b: f3 0f 6f 56 10 movdqu 0x10(%rsi),%xmm2 - 43b580: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 43b584: 66 0f d7 d0 pmovmskb %xmm0,%edx - 43b588: 48 85 d2 test %rdx,%rdx - 43b58b: 75 6b jne 43b5f8 <__stpcpy_sse2_unaligned+0x298> - 43b58d: 66 0f 74 c2 pcmpeqb %xmm2,%xmm0 - 43b591: f3 0f 7f 0f movdqu %xmm1,(%rdi) - 43b595: 66 0f d7 d0 pmovmskb %xmm0,%edx - 43b599: 48 85 d2 test %rdx,%rdx - 43b59c: 75 52 jne 43b5f0 <__stpcpy_sse2_unaligned+0x290> - 43b59e: 48 83 e6 f0 and $0xfffffffffffffff0,%rsi - 43b5a2: 48 83 e1 0f and $0xf,%rcx - 43b5a6: e9 05 fe ff ff jmpq 43b3b0 <__stpcpy_sse2_unaligned+0x50> - 43b5ab: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43b5b0: 48 01 cf add %rcx,%rdi - 43b5b3: 48 01 ce add %rcx,%rsi - 43b5b6: 48 0f bc d2 bsf %rdx,%rdx - 43b5ba: 4c 8d 1d 6f 85 06 00 lea 0x6856f(%rip),%r11 # 4a3b30 - 43b5c1: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx - 43b5c5: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx - 43b5c9: ff e1 jmpq *%rcx - 43b5cb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43b5d0: 48 01 ce add %rcx,%rsi - 43b5d3: 48 0f bc d2 bsf %rdx,%rdx - 43b5d7: 4c 8d 1d 52 85 06 00 lea 0x68552(%rip),%r11 # 4a3b30 - 43b5de: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx - 43b5e2: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx - 43b5e6: ff e1 jmpq *%rcx - 43b5e8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 43b5ef: 00 - 43b5f0: 48 83 c6 10 add $0x10,%rsi - 43b5f4: 48 83 c7 10 add $0x10,%rdi - 43b5f8: 48 0f bc d2 bsf %rdx,%rdx - 43b5fc: 4c 8d 1d 2d 85 06 00 lea 0x6852d(%rip),%r11 # 4a3b30 - 43b603: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx - 43b607: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx - 43b60b: ff e1 jmpq *%rcx - 43b60d: 0f 1f 00 nopl (%rax) - 43b610: 48 0f bc d2 bsf %rdx,%rdx - 43b614: 48 01 ce add %rcx,%rsi - 43b617: 48 83 c2 10 add $0x10,%rdx - 43b61b: 48 29 ca sub %rcx,%rdx - 43b61e: 4c 8d 1d 0b 85 06 00 lea 0x6850b(%rip),%r11 # 4a3b30 - 43b625: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx - 43b629: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx - 43b62d: ff e1 jmpq *%rcx - 43b62f: 90 nop - 43b630: 48 0f bc d2 bsf %rdx,%rdx - 43b634: 4c 8d 1d f5 84 06 00 lea 0x684f5(%rip),%r11 # 4a3b30 - 43b63b: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx - 43b63f: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx - 43b643: ff e1 jmpq *%rcx - 43b645: 90 nop - 43b646: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b64d: 00 00 00 - 43b650: 48 0f bc d1 bsf %rcx,%rdx - 43b654: f3 0f 7f 27 movdqu %xmm4,(%rdi) - 43b658: 48 83 c6 10 add $0x10,%rsi - 43b65c: 48 83 c7 10 add $0x10,%rdi - 43b660: 4c 8d 1d c9 84 06 00 lea 0x684c9(%rip),%r11 # 4a3b30 - 43b667: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx - 43b66b: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx - 43b66f: ff e1 jmpq *%rcx - 43b671: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43b676: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b67d: 00 00 00 - 43b680: 48 0f bc d2 bsf %rdx,%rdx - 43b684: f3 0f 7f 27 movdqu %xmm4,(%rdi) - 43b688: f3 0f 7f 6f 10 movdqu %xmm5,0x10(%rdi) - 43b68d: 48 83 c6 20 add $0x20,%rsi - 43b691: 48 83 c7 20 add $0x20,%rdi - 43b695: 4c 8d 1d 94 84 06 00 lea 0x68494(%rip),%r11 # 4a3b30 - 43b69c: 49 63 0c 93 movslq (%r11,%rdx,4),%rcx - 43b6a0: 49 8d 0c 0b lea (%r11,%rcx,1),%rcx - 43b6a4: ff e1 jmpq *%rcx - 43b6a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b6ad: 00 00 00 - 43b6b0: 88 37 mov %dh,(%rdi) - 43b6b2: 48 8d 07 lea (%rdi),%rax - 43b6b5: c3 retq - 43b6b6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b6bd: 00 00 00 - 43b6c0: 66 8b 16 mov (%rsi),%dx - 43b6c3: 66 89 17 mov %dx,(%rdi) - 43b6c6: 48 8d 47 01 lea 0x1(%rdi),%rax - 43b6ca: c3 retq - 43b6cb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43b6d0: 66 8b 0e mov (%rsi),%cx - 43b6d3: 66 89 0f mov %cx,(%rdi) - 43b6d6: 88 77 02 mov %dh,0x2(%rdi) - 43b6d9: 48 8d 47 02 lea 0x2(%rdi),%rax - 43b6dd: c3 retq - 43b6de: 66 90 xchg %ax,%ax - 43b6e0: 8b 16 mov (%rsi),%edx - 43b6e2: 89 17 mov %edx,(%rdi) - 43b6e4: 48 8d 47 03 lea 0x3(%rdi),%rax - 43b6e8: c3 retq - 43b6e9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43b6f0: 8b 0e mov (%rsi),%ecx - 43b6f2: 88 77 04 mov %dh,0x4(%rdi) - 43b6f5: 89 0f mov %ecx,(%rdi) - 43b6f7: 48 8d 47 04 lea 0x4(%rdi),%rax - 43b6fb: c3 retq - 43b6fc: 0f 1f 40 00 nopl 0x0(%rax) - 43b700: 8b 0e mov (%rsi),%ecx - 43b702: 66 8b 56 04 mov 0x4(%rsi),%dx - 43b706: 89 0f mov %ecx,(%rdi) - 43b708: 66 89 57 04 mov %dx,0x4(%rdi) - 43b70c: 48 8d 47 05 lea 0x5(%rdi),%rax - 43b710: c3 retq - 43b711: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43b716: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b71d: 00 00 00 - 43b720: 8b 0e mov (%rsi),%ecx - 43b722: 8b 56 03 mov 0x3(%rsi),%edx - 43b725: 89 0f mov %ecx,(%rdi) - 43b727: 89 57 03 mov %edx,0x3(%rdi) - 43b72a: 48 8d 47 06 lea 0x6(%rdi),%rax - 43b72e: c3 retq - 43b72f: 90 nop - 43b730: 48 8b 16 mov (%rsi),%rdx - 43b733: 48 89 17 mov %rdx,(%rdi) - 43b736: 48 8d 47 07 lea 0x7(%rdi),%rax - 43b73a: c3 retq - 43b73b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43b740: 48 8b 0e mov (%rsi),%rcx - 43b743: 88 77 08 mov %dh,0x8(%rdi) - 43b746: 48 89 0f mov %rcx,(%rdi) - 43b749: 48 8d 47 08 lea 0x8(%rdi),%rax - 43b74d: c3 retq - 43b74e: 66 90 xchg %ax,%ax - 43b750: 48 8b 0e mov (%rsi),%rcx - 43b753: 66 8b 56 08 mov 0x8(%rsi),%dx - 43b757: 48 89 0f mov %rcx,(%rdi) - 43b75a: 66 89 57 08 mov %dx,0x8(%rdi) - 43b75e: 48 8d 47 09 lea 0x9(%rdi),%rax - 43b762: c3 retq - 43b763: 0f 1f 00 nopl (%rax) - 43b766: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b76d: 00 00 00 - 43b770: 48 8b 0e mov (%rsi),%rcx - 43b773: 8b 56 07 mov 0x7(%rsi),%edx - 43b776: 48 89 0f mov %rcx,(%rdi) - 43b779: 89 57 07 mov %edx,0x7(%rdi) - 43b77c: 48 8d 47 0a lea 0xa(%rdi),%rax - 43b780: c3 retq - 43b781: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43b786: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b78d: 00 00 00 - 43b790: 48 8b 0e mov (%rsi),%rcx - 43b793: 8b 56 08 mov 0x8(%rsi),%edx - 43b796: 48 89 0f mov %rcx,(%rdi) - 43b799: 89 57 08 mov %edx,0x8(%rdi) - 43b79c: 48 8d 47 0b lea 0xb(%rdi),%rax - 43b7a0: c3 retq - 43b7a1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43b7a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b7ad: 00 00 00 - 43b7b0: 48 8b 0e mov (%rsi),%rcx - 43b7b3: 48 8b 56 05 mov 0x5(%rsi),%rdx - 43b7b7: 48 89 0f mov %rcx,(%rdi) - 43b7ba: 48 89 57 05 mov %rdx,0x5(%rdi) - 43b7be: 48 8d 47 0c lea 0xc(%rdi),%rax - 43b7c2: c3 retq - 43b7c3: 0f 1f 00 nopl (%rax) - 43b7c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b7cd: 00 00 00 - 43b7d0: 48 8b 0e mov (%rsi),%rcx - 43b7d3: 48 8b 56 06 mov 0x6(%rsi),%rdx - 43b7d7: 48 89 0f mov %rcx,(%rdi) - 43b7da: 48 89 57 06 mov %rdx,0x6(%rdi) - 43b7de: 48 8d 47 0d lea 0xd(%rdi),%rax - 43b7e2: c3 retq - 43b7e3: 0f 1f 00 nopl (%rax) - 43b7e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b7ed: 00 00 00 - 43b7f0: 48 8b 0e mov (%rsi),%rcx - 43b7f3: 48 8b 56 07 mov 0x7(%rsi),%rdx - 43b7f7: 48 89 0f mov %rcx,(%rdi) - 43b7fa: 48 89 57 07 mov %rdx,0x7(%rdi) - 43b7fe: 48 8d 47 0e lea 0xe(%rdi),%rax - 43b802: c3 retq - 43b803: 0f 1f 00 nopl (%rax) - 43b806: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b80d: 00 00 00 - 43b810: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b814: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b818: 48 8d 47 0f lea 0xf(%rdi),%rax - 43b81c: c3 retq - 43b81d: 0f 1f 00 nopl (%rax) - 43b820: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b824: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b828: 88 77 10 mov %dh,0x10(%rdi) - 43b82b: 48 8d 47 10 lea 0x10(%rdi),%rax - 43b82f: c3 retq - 43b830: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b834: 66 8b 4e 10 mov 0x10(%rsi),%cx - 43b838: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b83c: 66 89 4f 10 mov %cx,0x10(%rdi) - 43b840: 48 8d 47 11 lea 0x11(%rdi),%rax - 43b844: c3 retq - 43b845: 90 nop - 43b846: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b84d: 00 00 00 - 43b850: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b854: 8b 4e 0f mov 0xf(%rsi),%ecx - 43b857: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b85b: 89 4f 0f mov %ecx,0xf(%rdi) - 43b85e: 48 8d 47 12 lea 0x12(%rdi),%rax - 43b862: c3 retq - 43b863: 0f 1f 00 nopl (%rax) - 43b866: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b86d: 00 00 00 - 43b870: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b874: 8b 4e 10 mov 0x10(%rsi),%ecx - 43b877: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b87b: 89 4f 10 mov %ecx,0x10(%rdi) - 43b87e: 48 8d 47 13 lea 0x13(%rdi),%rax - 43b882: c3 retq - 43b883: 0f 1f 00 nopl (%rax) - 43b886: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b88d: 00 00 00 - 43b890: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b894: 8b 4e 10 mov 0x10(%rsi),%ecx - 43b897: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b89b: 89 4f 10 mov %ecx,0x10(%rdi) - 43b89e: 88 77 14 mov %dh,0x14(%rdi) - 43b8a1: 48 8d 47 14 lea 0x14(%rdi),%rax - 43b8a5: c3 retq - 43b8a6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b8ad: 00 00 00 - 43b8b0: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b8b4: 48 8b 4e 0e mov 0xe(%rsi),%rcx - 43b8b8: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b8bc: 48 89 4f 0e mov %rcx,0xe(%rdi) - 43b8c0: 48 8d 47 15 lea 0x15(%rdi),%rax - 43b8c4: c3 retq - 43b8c5: 90 nop - 43b8c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b8cd: 00 00 00 - 43b8d0: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b8d4: 48 8b 4e 0f mov 0xf(%rsi),%rcx - 43b8d8: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b8dc: 48 89 4f 0f mov %rcx,0xf(%rdi) - 43b8e0: 48 8d 47 16 lea 0x16(%rdi),%rax - 43b8e4: c3 retq - 43b8e5: 90 nop - 43b8e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b8ed: 00 00 00 - 43b8f0: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b8f4: 48 8b 4e 10 mov 0x10(%rsi),%rcx - 43b8f8: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b8fc: 48 89 4f 10 mov %rcx,0x10(%rdi) - 43b900: 48 8d 47 17 lea 0x17(%rdi),%rax - 43b904: c3 retq - 43b905: 90 nop - 43b906: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43b90d: 00 00 00 - 43b910: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b914: 48 8b 4e 10 mov 0x10(%rsi),%rcx - 43b918: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b91c: 48 89 4f 10 mov %rcx,0x10(%rdi) - 43b920: 88 77 18 mov %dh,0x18(%rdi) - 43b923: 48 8d 47 18 lea 0x18(%rdi),%rax - 43b927: c3 retq - 43b928: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 43b92f: 00 - 43b930: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b934: 48 8b 56 10 mov 0x10(%rsi),%rdx - 43b938: 66 8b 4e 18 mov 0x18(%rsi),%cx - 43b93c: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b940: 48 89 57 10 mov %rdx,0x10(%rdi) - 43b944: 66 89 4f 18 mov %cx,0x18(%rdi) - 43b948: 48 8d 47 19 lea 0x19(%rdi),%rax - 43b94c: c3 retq - 43b94d: 0f 1f 00 nopl (%rax) - 43b950: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b954: 48 8b 56 10 mov 0x10(%rsi),%rdx - 43b958: 8b 4e 17 mov 0x17(%rsi),%ecx - 43b95b: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b95f: 48 89 57 10 mov %rdx,0x10(%rdi) - 43b963: 89 4f 17 mov %ecx,0x17(%rdi) - 43b966: 48 8d 47 1a lea 0x1a(%rdi),%rax - 43b96a: c3 retq - 43b96b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43b970: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b974: 48 8b 56 10 mov 0x10(%rsi),%rdx - 43b978: 8b 4e 18 mov 0x18(%rsi),%ecx - 43b97b: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b97f: 48 89 57 10 mov %rdx,0x10(%rdi) - 43b983: 89 4f 18 mov %ecx,0x18(%rdi) - 43b986: 48 8d 47 1b lea 0x1b(%rdi),%rax - 43b98a: c3 retq - 43b98b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43b990: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b994: f3 0f 6f 56 0d movdqu 0xd(%rsi),%xmm2 - 43b999: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b99d: f3 0f 7f 57 0d movdqu %xmm2,0xd(%rdi) - 43b9a2: 48 8d 47 1c lea 0x1c(%rdi),%rax - 43b9a6: c3 retq - 43b9a7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 43b9ae: 00 00 - 43b9b0: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b9b4: f3 0f 6f 56 0e movdqu 0xe(%rsi),%xmm2 - 43b9b9: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b9bd: f3 0f 7f 57 0e movdqu %xmm2,0xe(%rdi) - 43b9c2: 48 8d 47 1d lea 0x1d(%rdi),%rax - 43b9c6: c3 retq - 43b9c7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 43b9ce: 00 00 - 43b9d0: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b9d4: f3 0f 6f 56 0f movdqu 0xf(%rsi),%xmm2 - 43b9d9: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b9dd: f3 0f 7f 57 0f movdqu %xmm2,0xf(%rdi) - 43b9e2: 48 8d 47 1e lea 0x1e(%rdi),%rax - 43b9e6: c3 retq - 43b9e7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 43b9ee: 00 00 - 43b9f0: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43b9f4: f3 0f 6f 56 10 movdqu 0x10(%rsi),%xmm2 - 43b9f9: f3 0f 7f 07 movdqu %xmm0,(%rdi) - 43b9fd: f3 0f 7f 57 10 movdqu %xmm2,0x10(%rdi) - 43ba02: 48 8d 47 1f lea 0x1f(%rdi),%rax - 43ba06: c3 retq - 43ba07: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 43ba0e: 00 00 - -000000000043ba10 <__strchr_sse2_no_bsf>: - 43ba10: 66 0f 6e ce movd %esi,%xmm1 - 43ba14: 48 89 f9 mov %rdi,%rcx - 43ba17: 66 0f 60 c9 punpcklbw %xmm1,%xmm1 - 43ba1b: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi - 43ba1f: 66 0f ef d2 pxor %xmm2,%xmm2 - 43ba23: 66 0f 60 c9 punpcklbw %xmm1,%xmm1 - 43ba27: 83 ce ff or $0xffffffff,%esi - 43ba2a: 66 0f 6f 07 movdqa (%rdi),%xmm0 - 43ba2e: 66 0f 70 c9 00 pshufd $0x0,%xmm1,%xmm1 - 43ba33: 48 29 f9 sub %rdi,%rcx - 43ba36: 66 0f 6f d8 movdqa %xmm0,%xmm3 - 43ba3a: 48 8d 7f 10 lea 0x10(%rdi),%rdi - 43ba3e: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 43ba42: 66 0f 74 da pcmpeqb %xmm2,%xmm3 - 43ba46: d3 e6 shl %cl,%esi - 43ba48: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43ba4c: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43ba50: 21 f0 and %esi,%eax - 43ba52: 21 f2 and %esi,%edx - 43ba54: 85 c0 test %eax,%eax - 43ba56: 75 3c jne 43ba94 <__strchr_sse2_no_bsf+0x84> - 43ba58: 85 d2 test %edx,%edx - 43ba5a: 75 34 jne 43ba90 <__strchr_sse2_no_bsf+0x80> - 43ba5c: 66 0f 6f 07 movdqa (%rdi),%xmm0 - 43ba60: 48 8d 7f 10 lea 0x10(%rdi),%rdi - 43ba64: 66 0f 6f d8 movdqa %xmm0,%xmm3 - 43ba68: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 43ba6c: 66 0f 74 da pcmpeqb %xmm2,%xmm3 - 43ba70: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43ba74: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43ba78: 09 c2 or %eax,%edx - 43ba7a: 74 e0 je 43ba5c <__strchr_sse2_no_bsf+0x4c> - 43ba7c: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43ba80: 85 c0 test %eax,%eax - 43ba82: 75 10 jne 43ba94 <__strchr_sse2_no_bsf+0x84> - 43ba84: 66 90 xchg %ax,%ax - 43ba86: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43ba8d: 00 00 00 - 43ba90: 48 31 c0 xor %rax,%rax - 43ba93: c3 retq - 43ba94: 48 8d 7f f0 lea -0x10(%rdi),%rdi - 43ba98: 85 d2 test %edx,%edx - 43ba9a: 0f 84 10 01 00 00 je 43bbb0 <__strchr_sse2_no_bsf+0x1a0> - 43baa0: 84 c0 test %al,%al - 43baa2: 74 6c je 43bb10 <__strchr_sse2_no_bsf+0x100> - 43baa4: 88 c1 mov %al,%cl - 43baa6: 80 e1 0f and $0xf,%cl - 43baa9: 75 35 jne 43bae0 <__strchr_sse2_no_bsf+0xd0> - 43baab: 88 d5 mov %dl,%ch - 43baad: 80 e5 0f and $0xf,%ch - 43bab0: 75 de jne 43ba90 <__strchr_sse2_no_bsf+0x80> - 43bab2: a8 10 test $0x10,%al - 43bab4: 0f 85 d6 01 00 00 jne 43bc90 <__strchr_sse2_no_bsf+0x280> - 43baba: f6 c2 10 test $0x10,%dl - 43babd: 75 d1 jne 43ba90 <__strchr_sse2_no_bsf+0x80> - 43babf: a8 20 test $0x20,%al - 43bac1: 0f 85 d9 01 00 00 jne 43bca0 <__strchr_sse2_no_bsf+0x290> - 43bac7: f6 c2 20 test $0x20,%dl - 43baca: 75 c4 jne 43ba90 <__strchr_sse2_no_bsf+0x80> - 43bacc: a8 40 test $0x40,%al - 43bace: 0f 85 dc 01 00 00 jne 43bcb0 <__strchr_sse2_no_bsf+0x2a0> - 43bad4: f6 c2 40 test $0x40,%dl - 43bad7: 75 b7 jne 43ba90 <__strchr_sse2_no_bsf+0x80> - 43bad9: 48 8d 47 07 lea 0x7(%rdi),%rax - 43badd: c3 retq - 43bade: 66 90 xchg %ax,%ax - 43bae0: a8 01 test $0x1,%al - 43bae2: 0f 85 68 01 00 00 jne 43bc50 <__strchr_sse2_no_bsf+0x240> - 43bae8: f6 c2 01 test $0x1,%dl - 43baeb: 75 a3 jne 43ba90 <__strchr_sse2_no_bsf+0x80> - 43baed: a8 02 test $0x2,%al - 43baef: 0f 85 6b 01 00 00 jne 43bc60 <__strchr_sse2_no_bsf+0x250> - 43baf5: f6 c2 02 test $0x2,%dl - 43baf8: 75 96 jne 43ba90 <__strchr_sse2_no_bsf+0x80> - 43bafa: a8 04 test $0x4,%al - 43bafc: 0f 85 6e 01 00 00 jne 43bc70 <__strchr_sse2_no_bsf+0x260> - 43bb02: f6 c2 04 test $0x4,%dl - 43bb05: 75 89 jne 43ba90 <__strchr_sse2_no_bsf+0x80> - 43bb07: 48 8d 47 03 lea 0x3(%rdi),%rax - 43bb0b: c3 retq - 43bb0c: 0f 1f 40 00 nopl 0x0(%rax) - 43bb10: 84 d2 test %dl,%dl - 43bb12: 0f 85 78 ff ff ff jne 43ba90 <__strchr_sse2_no_bsf+0x80> - 43bb18: 88 e1 mov %ah,%cl - 43bb1a: 80 e1 0f and $0xf,%cl - 43bb1d: 75 51 jne 43bb70 <__strchr_sse2_no_bsf+0x160> - 43bb1f: 88 f5 mov %dh,%ch - 43bb21: 80 e5 0f and $0xf,%ch - 43bb24: 0f 85 66 ff ff ff jne 43ba90 <__strchr_sse2_no_bsf+0x80> - 43bb2a: f6 c4 10 test $0x10,%ah - 43bb2d: 0f 85 cd 01 00 00 jne 43bd00 <__strchr_sse2_no_bsf+0x2f0> - 43bb33: f6 c6 10 test $0x10,%dh - 43bb36: 0f 85 54 ff ff ff jne 43ba90 <__strchr_sse2_no_bsf+0x80> - 43bb3c: f6 c4 20 test $0x20,%ah - 43bb3f: 0f 85 cb 01 00 00 jne 43bd10 <__strchr_sse2_no_bsf+0x300> - 43bb45: f6 c6 20 test $0x20,%dh - 43bb48: 0f 85 42 ff ff ff jne 43ba90 <__strchr_sse2_no_bsf+0x80> - 43bb4e: f6 c4 40 test $0x40,%ah - 43bb51: 0f 85 c9 01 00 00 jne 43bd20 <__strchr_sse2_no_bsf+0x310> - 43bb57: f6 c6 40 test $0x40,%dh - 43bb5a: 0f 85 30 ff ff ff jne 43ba90 <__strchr_sse2_no_bsf+0x80> - 43bb60: 48 8d 47 0f lea 0xf(%rdi),%rax - 43bb64: c3 retq - 43bb65: 90 nop - 43bb66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43bb6d: 00 00 00 - 43bb70: f6 c4 01 test $0x1,%ah - 43bb73: 0f 85 47 01 00 00 jne 43bcc0 <__strchr_sse2_no_bsf+0x2b0> - 43bb79: f6 c6 01 test $0x1,%dh - 43bb7c: 0f 85 0e ff ff ff jne 43ba90 <__strchr_sse2_no_bsf+0x80> - 43bb82: f6 c4 02 test $0x2,%ah - 43bb85: 0f 85 45 01 00 00 jne 43bcd0 <__strchr_sse2_no_bsf+0x2c0> - 43bb8b: f6 c6 02 test $0x2,%dh - 43bb8e: 0f 85 fc fe ff ff jne 43ba90 <__strchr_sse2_no_bsf+0x80> - 43bb94: f6 c4 04 test $0x4,%ah - 43bb97: 0f 85 43 01 00 00 jne 43bce0 <__strchr_sse2_no_bsf+0x2d0> - 43bb9d: f6 c6 04 test $0x4,%dh - 43bba0: 0f 85 ea fe ff ff jne 43ba90 <__strchr_sse2_no_bsf+0x80> - 43bba6: 48 8d 47 0b lea 0xb(%rdi),%rax - 43bbaa: c3 retq - 43bbab: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43bbb0: 84 c0 test %al,%al - 43bbb2: 74 4c je 43bc00 <__strchr_sse2_no_bsf+0x1f0> - 43bbb4: a8 01 test $0x1,%al - 43bbb6: 0f 85 94 00 00 00 jne 43bc50 <__strchr_sse2_no_bsf+0x240> - 43bbbc: a8 02 test $0x2,%al - 43bbbe: 0f 85 9c 00 00 00 jne 43bc60 <__strchr_sse2_no_bsf+0x250> - 43bbc4: a8 04 test $0x4,%al - 43bbc6: 0f 85 a4 00 00 00 jne 43bc70 <__strchr_sse2_no_bsf+0x260> - 43bbcc: a8 08 test $0x8,%al - 43bbce: 0f 85 ac 00 00 00 jne 43bc80 <__strchr_sse2_no_bsf+0x270> - 43bbd4: a8 10 test $0x10,%al - 43bbd6: 0f 85 b4 00 00 00 jne 43bc90 <__strchr_sse2_no_bsf+0x280> - 43bbdc: a8 20 test $0x20,%al - 43bbde: 0f 85 bc 00 00 00 jne 43bca0 <__strchr_sse2_no_bsf+0x290> - 43bbe4: a8 40 test $0x40,%al - 43bbe6: 0f 85 c4 00 00 00 jne 43bcb0 <__strchr_sse2_no_bsf+0x2a0> - 43bbec: 48 8d 47 07 lea 0x7(%rdi),%rax - 43bbf0: c3 retq - 43bbf1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43bbf6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43bbfd: 00 00 00 - 43bc00: f6 c4 01 test $0x1,%ah - 43bc03: 0f 85 b7 00 00 00 jne 43bcc0 <__strchr_sse2_no_bsf+0x2b0> - 43bc09: f6 c4 02 test $0x2,%ah - 43bc0c: 0f 85 be 00 00 00 jne 43bcd0 <__strchr_sse2_no_bsf+0x2c0> - 43bc12: f6 c4 04 test $0x4,%ah - 43bc15: 0f 85 c5 00 00 00 jne 43bce0 <__strchr_sse2_no_bsf+0x2d0> - 43bc1b: f6 c4 08 test $0x8,%ah - 43bc1e: 0f 85 cc 00 00 00 jne 43bcf0 <__strchr_sse2_no_bsf+0x2e0> - 43bc24: f6 c4 10 test $0x10,%ah - 43bc27: 0f 85 d3 00 00 00 jne 43bd00 <__strchr_sse2_no_bsf+0x2f0> - 43bc2d: f6 c4 20 test $0x20,%ah - 43bc30: 0f 85 da 00 00 00 jne 43bd10 <__strchr_sse2_no_bsf+0x300> - 43bc36: f6 c4 40 test $0x40,%ah - 43bc39: 0f 85 e1 00 00 00 jne 43bd20 <__strchr_sse2_no_bsf+0x310> - 43bc3f: 48 8d 47 0f lea 0xf(%rdi),%rax - 43bc43: c3 retq - 43bc44: 66 90 xchg %ax,%ax - 43bc46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43bc4d: 00 00 00 - 43bc50: 48 8d 07 lea (%rdi),%rax - 43bc53: c3 retq - 43bc54: 66 90 xchg %ax,%ax - 43bc56: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43bc5d: 00 00 00 - 43bc60: 48 8d 47 01 lea 0x1(%rdi),%rax - 43bc64: c3 retq - 43bc65: 90 nop - 43bc66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43bc6d: 00 00 00 - 43bc70: 48 8d 47 02 lea 0x2(%rdi),%rax - 43bc74: c3 retq - 43bc75: 90 nop - 43bc76: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43bc7d: 00 00 00 - 43bc80: 48 8d 47 03 lea 0x3(%rdi),%rax - 43bc84: c3 retq - 43bc85: 90 nop - 43bc86: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43bc8d: 00 00 00 - 43bc90: 48 8d 47 04 lea 0x4(%rdi),%rax - 43bc94: c3 retq - 43bc95: 90 nop - 43bc96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43bc9d: 00 00 00 - 43bca0: 48 8d 47 05 lea 0x5(%rdi),%rax - 43bca4: c3 retq - 43bca5: 90 nop - 43bca6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43bcad: 00 00 00 - 43bcb0: 48 8d 47 06 lea 0x6(%rdi),%rax - 43bcb4: c3 retq - 43bcb5: 90 nop - 43bcb6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43bcbd: 00 00 00 - 43bcc0: 48 8d 47 08 lea 0x8(%rdi),%rax - 43bcc4: c3 retq - 43bcc5: 90 nop - 43bcc6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43bccd: 00 00 00 - 43bcd0: 48 8d 47 09 lea 0x9(%rdi),%rax - 43bcd4: c3 retq - 43bcd5: 90 nop - 43bcd6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43bcdd: 00 00 00 - 43bce0: 48 8d 47 0a lea 0xa(%rdi),%rax - 43bce4: c3 retq - 43bce5: 90 nop - 43bce6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43bced: 00 00 00 - 43bcf0: 48 8d 47 0b lea 0xb(%rdi),%rax - 43bcf4: c3 retq - 43bcf5: 90 nop - 43bcf6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43bcfd: 00 00 00 - 43bd00: 48 8d 47 0c lea 0xc(%rdi),%rax - 43bd04: c3 retq - 43bd05: 90 nop - 43bd06: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43bd0d: 00 00 00 - 43bd10: 48 8d 47 0d lea 0xd(%rdi),%rax - 43bd14: c3 retq - 43bd15: 90 nop - 43bd16: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43bd1d: 00 00 00 - 43bd20: 48 8d 47 0e lea 0xe(%rdi),%rax - 43bd24: c3 retq - 43bd25: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43bd2c: 00 00 00 - 43bd2f: 90 nop - -000000000043bd30 <__memcmp_ssse3>: - 43bd30: 48 89 d1 mov %rdx,%rcx - 43bd33: 48 89 fa mov %rdi,%rdx - 43bd36: 48 83 f9 30 cmp $0x30,%rcx - 43bd3a: 73 14 jae 43bd50 <__memcmp_ssse3+0x20> - 43bd3c: 48 01 ce add %rcx,%rsi - 43bd3f: 48 01 cf add %rcx,%rdi - 43bd42: e9 b9 12 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43bd47: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 43bd4e: 00 00 - 43bd50: f3 0f 6f 1f movdqu (%rdi),%xmm3 - 43bd54: f3 0f 6f 06 movdqu (%rsi),%xmm0 - 43bd58: 66 0f 74 d8 pcmpeqb %xmm0,%xmm3 - 43bd5c: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43bd60: 48 8d 7f 10 lea 0x10(%rdi),%rdi - 43bd64: 48 8d 76 10 lea 0x10(%rsi),%rsi - 43bd68: 81 ea ff ff 00 00 sub $0xffff,%edx - 43bd6e: 0f 85 98 11 00 00 jne 43cf0c <__memcmp_ssse3+0x11dc> - 43bd74: 89 fa mov %edi,%edx - 43bd76: 83 e2 0f and $0xf,%edx - 43bd79: 48 31 d7 xor %rdx,%rdi - 43bd7c: 48 29 d6 sub %rdx,%rsi - 43bd7f: 48 01 d1 add %rdx,%rcx - 43bd82: 89 f2 mov %esi,%edx - 43bd84: 83 e2 0f and $0xf,%edx - 43bd87: 0f 84 93 00 00 00 je 43be20 <__memcmp_ssse3+0xf0> - 43bd8d: 48 31 d6 xor %rdx,%rsi - 43bd90: 83 fa 08 cmp $0x8,%edx - 43bd93: 73 47 jae 43bddc <__memcmp_ssse3+0xac> - 43bd95: 83 fa 00 cmp $0x0,%edx - 43bd98: 0f 84 82 00 00 00 je 43be20 <__memcmp_ssse3+0xf0> - 43bd9e: 83 fa 01 cmp $0x1,%edx - 43bda1: 0f 84 59 01 00 00 je 43bf00 <__memcmp_ssse3+0x1d0> - 43bda7: 83 fa 02 cmp $0x2,%edx - 43bdaa: 0f 84 60 02 00 00 je 43c010 <__memcmp_ssse3+0x2e0> - 43bdb0: 83 fa 03 cmp $0x3,%edx - 43bdb3: 0f 84 67 03 00 00 je 43c120 <__memcmp_ssse3+0x3f0> - 43bdb9: 83 fa 04 cmp $0x4,%edx - 43bdbc: 0f 84 6e 04 00 00 je 43c230 <__memcmp_ssse3+0x500> - 43bdc2: 83 fa 05 cmp $0x5,%edx - 43bdc5: 0f 84 75 05 00 00 je 43c340 <__memcmp_ssse3+0x610> - 43bdcb: 83 fa 06 cmp $0x6,%edx - 43bdce: 0f 84 7c 06 00 00 je 43c450 <__memcmp_ssse3+0x720> - 43bdd4: e9 87 07 00 00 jmpq 43c560 <__memcmp_ssse3+0x830> - 43bdd9: 0f 1f 00 nopl (%rax) - 43bddc: 83 fa 08 cmp $0x8,%edx - 43bddf: 0f 84 8b 08 00 00 je 43c670 <__memcmp_ssse3+0x940> - 43bde5: 83 fa 09 cmp $0x9,%edx - 43bde8: 0f 84 92 09 00 00 je 43c780 <__memcmp_ssse3+0xa50> - 43bdee: 83 fa 0a cmp $0xa,%edx - 43bdf1: 0f 84 99 0a 00 00 je 43c890 <__memcmp_ssse3+0xb60> - 43bdf7: 83 fa 0b cmp $0xb,%edx - 43bdfa: 0f 84 a0 0b 00 00 je 43c9a0 <__memcmp_ssse3+0xc70> - 43be00: 83 fa 0c cmp $0xc,%edx - 43be03: 0f 84 a7 0c 00 00 je 43cab0 <__memcmp_ssse3+0xd80> - 43be09: 83 fa 0d cmp $0xd,%edx - 43be0c: 0f 84 ae 0d 00 00 je 43cbc0 <__memcmp_ssse3+0xe90> - 43be12: 83 fa 0e cmp $0xe,%edx - 43be15: 0f 84 b5 0e 00 00 je 43ccd0 <__memcmp_ssse3+0xfa0> - 43be1b: e9 c0 0f 00 00 jmpq 43cde0 <__memcmp_ssse3+0x10b0> - 43be20: 48 83 f9 50 cmp $0x50,%rcx - 43be24: 48 8d 49 d0 lea -0x30(%rcx),%rcx - 43be28: 73 46 jae 43be70 <__memcmp_ssse3+0x140> - 43be2a: 31 c0 xor %eax,%eax - 43be2c: 66 0f 6f 0e movdqa (%rsi),%xmm1 - 43be30: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 - 43be34: 66 0f 6f 56 10 movdqa 0x10(%rsi),%xmm2 - 43be39: 66 0f 74 57 10 pcmpeqb 0x10(%rdi),%xmm2 - 43be3e: 66 0f db d1 pand %xmm1,%xmm2 - 43be42: 66 0f d7 d2 pmovmskb %xmm2,%edx - 43be46: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43be4a: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43be4e: 81 ea ff ff 00 00 sub $0xffff,%edx - 43be54: 0f 85 96 10 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43be5a: 48 01 ce add %rcx,%rsi - 43be5d: 48 01 cf add %rcx,%rdi - 43be60: e9 9b 11 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43be65: 90 nop - 43be66: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43be6d: 00 00 00 - 43be70: 66 0f 6f 06 movdqa (%rsi),%xmm0 - 43be74: 31 c0 xor %eax,%eax - 43be76: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 43be7a: 48 83 e9 20 sub $0x20,%rcx - 43be7e: 66 0f 6f 56 10 movdqa 0x10(%rsi),%xmm2 - 43be83: 66 0f 74 57 10 pcmpeqb 0x10(%rdi),%xmm2 - 43be88: 66 0f db d0 pand %xmm0,%xmm2 - 43be8c: 48 83 e9 20 sub $0x20,%rcx - 43be90: 66 0f d7 d2 pmovmskb %xmm2,%edx - 43be94: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43be98: 66 0f 6f 46 20 movdqa 0x20(%rsi),%xmm0 - 43be9d: 66 0f 6f 56 30 movdqa 0x30(%rsi),%xmm2 - 43bea2: 81 da ff ff 00 00 sbb $0xffff,%edx - 43bea8: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 - 43bead: 66 0f 74 57 30 pcmpeqb 0x30(%rdi),%xmm2 - 43beb2: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43beb6: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43beba: 74 cc je 43be88 <__memcmp_ssse3+0x158> - 43bebc: 66 0f db d0 pand %xmm0,%xmm2 - 43bec0: 48 83 f9 00 cmp $0x0,%rcx - 43bec4: 7d 06 jge 43becc <__memcmp_ssse3+0x19c> - 43bec6: ff c2 inc %edx - 43bec8: 48 83 c1 20 add $0x20,%rcx - 43becc: 85 d2 test %edx,%edx - 43bece: 0f 85 1c 10 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43bed4: 66 0f d7 d2 pmovmskb %xmm2,%edx - 43bed8: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43bedc: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43bee0: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43bee4: 81 ea ff ff 00 00 sub $0xffff,%edx - 43beea: 0f 85 00 10 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43bef0: 48 01 ce add %rcx,%rsi - 43bef3: 48 01 cf add %rcx,%rdi - 43bef6: e9 05 11 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43befb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43bf00: 48 83 f9 50 cmp $0x50,%rcx - 43bf04: 48 8d 49 d0 lea -0x30(%rcx),%rcx - 43bf08: 89 d0 mov %edx,%eax - 43bf0a: 73 54 jae 43bf60 <__memcmp_ssse3+0x230> - 43bf0c: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 - 43bf11: 66 0f 6f d1 movdqa %xmm1,%xmm2 - 43bf15: 66 0f 3a 0f 0e 01 palignr $0x1,(%rsi),%xmm1 - 43bf1b: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 - 43bf1f: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 - 43bf24: 66 0f 3a 0f da 01 palignr $0x1,%xmm2,%xmm3 - 43bf2a: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 - 43bf2f: 66 0f db d9 pand %xmm1,%xmm3 - 43bf33: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43bf37: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43bf3b: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43bf3f: 81 ea ff ff 00 00 sub $0xffff,%edx - 43bf45: 0f 85 a5 0f 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43bf4b: 48 83 c6 01 add $0x1,%rsi - 43bf4f: 48 01 ce add %rcx,%rsi - 43bf52: 48 01 cf add %rcx,%rdi - 43bf55: e9 a6 10 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43bf5a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43bf60: 48 83 e9 20 sub $0x20,%rcx - 43bf64: 66 0f 6f 46 10 movdqa 0x10(%rsi),%xmm0 - 43bf69: 66 0f 3a 0f 06 01 palignr $0x1,(%rsi),%xmm0 - 43bf6f: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 43bf73: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 - 43bf78: 66 0f 3a 0f 5e 10 01 palignr $0x1,0x10(%rsi),%xmm3 - 43bf7f: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 - 43bf84: 66 0f db d8 pand %xmm0,%xmm3 - 43bf88: 48 83 e9 20 sub $0x20,%rcx - 43bf8c: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43bf90: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43bf94: 66 0f 6f 5e 40 movdqa 0x40(%rsi),%xmm3 - 43bf99: 66 0f 3a 0f 5e 30 01 palignr $0x1,0x30(%rsi),%xmm3 - 43bfa0: 81 da ff ff 00 00 sbb $0xffff,%edx - 43bfa6: 66 0f 6f 46 30 movdqa 0x30(%rsi),%xmm0 - 43bfab: 66 0f 3a 0f 46 20 01 palignr $0x1,0x20(%rsi),%xmm0 - 43bfb2: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 - 43bfb7: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43bfbb: 66 0f 74 5f 30 pcmpeqb 0x30(%rdi),%xmm3 - 43bfc0: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43bfc4: 74 be je 43bf84 <__memcmp_ssse3+0x254> - 43bfc6: 66 0f db d8 pand %xmm0,%xmm3 - 43bfca: 48 83 f9 00 cmp $0x0,%rcx - 43bfce: 7d 06 jge 43bfd6 <__memcmp_ssse3+0x2a6> - 43bfd0: ff c2 inc %edx - 43bfd2: 48 83 c1 20 add $0x20,%rcx - 43bfd6: 85 d2 test %edx,%edx - 43bfd8: 0f 85 12 0f 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43bfde: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43bfe2: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43bfe6: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43bfea: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43bfee: 81 ea ff ff 00 00 sub $0xffff,%edx - 43bff4: 0f 85 f6 0e 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43bffa: 48 8d 76 01 lea 0x1(%rsi),%rsi - 43bffe: 48 01 ce add %rcx,%rsi - 43c001: 48 01 cf add %rcx,%rdi - 43c004: e9 f7 0f 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43c009: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43c010: 48 83 f9 50 cmp $0x50,%rcx - 43c014: 48 8d 49 d0 lea -0x30(%rcx),%rcx - 43c018: 89 d0 mov %edx,%eax - 43c01a: 73 54 jae 43c070 <__memcmp_ssse3+0x340> - 43c01c: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 - 43c021: 66 0f 6f d1 movdqa %xmm1,%xmm2 - 43c025: 66 0f 3a 0f 0e 02 palignr $0x2,(%rsi),%xmm1 - 43c02b: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 - 43c02f: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 - 43c034: 66 0f 3a 0f da 02 palignr $0x2,%xmm2,%xmm3 - 43c03a: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 - 43c03f: 66 0f db d9 pand %xmm1,%xmm3 - 43c043: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43c047: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43c04b: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43c04f: 81 ea ff ff 00 00 sub $0xffff,%edx - 43c055: 0f 85 95 0e 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43c05b: 48 83 c6 02 add $0x2,%rsi - 43c05f: 48 01 ce add %rcx,%rsi - 43c062: 48 01 cf add %rcx,%rdi - 43c065: e9 96 0f 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43c06a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43c070: 48 83 e9 20 sub $0x20,%rcx - 43c074: 66 0f 6f 46 10 movdqa 0x10(%rsi),%xmm0 - 43c079: 66 0f 3a 0f 06 02 palignr $0x2,(%rsi),%xmm0 - 43c07f: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 43c083: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 - 43c088: 66 0f 3a 0f 5e 10 02 palignr $0x2,0x10(%rsi),%xmm3 - 43c08f: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 - 43c094: 66 0f db d8 pand %xmm0,%xmm3 - 43c098: 48 83 e9 20 sub $0x20,%rcx - 43c09c: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43c0a0: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43c0a4: 66 0f 6f 5e 40 movdqa 0x40(%rsi),%xmm3 - 43c0a9: 66 0f 3a 0f 5e 30 02 palignr $0x2,0x30(%rsi),%xmm3 - 43c0b0: 81 da ff ff 00 00 sbb $0xffff,%edx - 43c0b6: 66 0f 6f 46 30 movdqa 0x30(%rsi),%xmm0 - 43c0bb: 66 0f 3a 0f 46 20 02 palignr $0x2,0x20(%rsi),%xmm0 - 43c0c2: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 - 43c0c7: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43c0cb: 66 0f 74 5f 30 pcmpeqb 0x30(%rdi),%xmm3 - 43c0d0: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43c0d4: 74 be je 43c094 <__memcmp_ssse3+0x364> - 43c0d6: 66 0f db d8 pand %xmm0,%xmm3 - 43c0da: 48 83 f9 00 cmp $0x0,%rcx - 43c0de: 7d 06 jge 43c0e6 <__memcmp_ssse3+0x3b6> - 43c0e0: ff c2 inc %edx - 43c0e2: 48 83 c1 20 add $0x20,%rcx - 43c0e6: 85 d2 test %edx,%edx - 43c0e8: 0f 85 02 0e 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43c0ee: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43c0f2: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43c0f6: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43c0fa: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43c0fe: 81 ea ff ff 00 00 sub $0xffff,%edx - 43c104: 0f 85 e6 0d 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43c10a: 48 8d 76 02 lea 0x2(%rsi),%rsi - 43c10e: 48 01 ce add %rcx,%rsi - 43c111: 48 01 cf add %rcx,%rdi - 43c114: e9 e7 0e 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43c119: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43c120: 48 83 f9 50 cmp $0x50,%rcx - 43c124: 48 8d 49 d0 lea -0x30(%rcx),%rcx - 43c128: 89 d0 mov %edx,%eax - 43c12a: 73 54 jae 43c180 <__memcmp_ssse3+0x450> - 43c12c: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 - 43c131: 66 0f 6f d1 movdqa %xmm1,%xmm2 - 43c135: 66 0f 3a 0f 0e 03 palignr $0x3,(%rsi),%xmm1 - 43c13b: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 - 43c13f: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 - 43c144: 66 0f 3a 0f da 03 palignr $0x3,%xmm2,%xmm3 - 43c14a: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 - 43c14f: 66 0f db d9 pand %xmm1,%xmm3 - 43c153: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43c157: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43c15b: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43c15f: 81 ea ff ff 00 00 sub $0xffff,%edx - 43c165: 0f 85 85 0d 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43c16b: 48 83 c6 03 add $0x3,%rsi - 43c16f: 48 01 ce add %rcx,%rsi - 43c172: 48 01 cf add %rcx,%rdi - 43c175: e9 86 0e 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43c17a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43c180: 48 83 e9 20 sub $0x20,%rcx - 43c184: 66 0f 6f 46 10 movdqa 0x10(%rsi),%xmm0 - 43c189: 66 0f 3a 0f 06 03 palignr $0x3,(%rsi),%xmm0 - 43c18f: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 43c193: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 - 43c198: 66 0f 3a 0f 5e 10 03 palignr $0x3,0x10(%rsi),%xmm3 - 43c19f: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 - 43c1a4: 66 0f db d8 pand %xmm0,%xmm3 - 43c1a8: 48 83 e9 20 sub $0x20,%rcx - 43c1ac: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43c1b0: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43c1b4: 66 0f 6f 5e 40 movdqa 0x40(%rsi),%xmm3 - 43c1b9: 66 0f 3a 0f 5e 30 03 palignr $0x3,0x30(%rsi),%xmm3 - 43c1c0: 81 da ff ff 00 00 sbb $0xffff,%edx - 43c1c6: 66 0f 6f 46 30 movdqa 0x30(%rsi),%xmm0 - 43c1cb: 66 0f 3a 0f 46 20 03 palignr $0x3,0x20(%rsi),%xmm0 - 43c1d2: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 - 43c1d7: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43c1db: 66 0f 74 5f 30 pcmpeqb 0x30(%rdi),%xmm3 - 43c1e0: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43c1e4: 74 be je 43c1a4 <__memcmp_ssse3+0x474> - 43c1e6: 66 0f db d8 pand %xmm0,%xmm3 - 43c1ea: 48 83 f9 00 cmp $0x0,%rcx - 43c1ee: 7d 06 jge 43c1f6 <__memcmp_ssse3+0x4c6> - 43c1f0: ff c2 inc %edx - 43c1f2: 48 83 c1 20 add $0x20,%rcx - 43c1f6: 85 d2 test %edx,%edx - 43c1f8: 0f 85 f2 0c 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43c1fe: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43c202: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43c206: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43c20a: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43c20e: 81 ea ff ff 00 00 sub $0xffff,%edx - 43c214: 0f 85 d6 0c 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43c21a: 48 8d 76 03 lea 0x3(%rsi),%rsi - 43c21e: 48 01 ce add %rcx,%rsi - 43c221: 48 01 cf add %rcx,%rdi - 43c224: e9 d7 0d 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43c229: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43c230: 48 83 f9 50 cmp $0x50,%rcx - 43c234: 48 8d 49 d0 lea -0x30(%rcx),%rcx - 43c238: 89 d0 mov %edx,%eax - 43c23a: 73 54 jae 43c290 <__memcmp_ssse3+0x560> - 43c23c: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 - 43c241: 66 0f 6f d1 movdqa %xmm1,%xmm2 - 43c245: 66 0f 3a 0f 0e 04 palignr $0x4,(%rsi),%xmm1 - 43c24b: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 - 43c24f: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 - 43c254: 66 0f 3a 0f da 04 palignr $0x4,%xmm2,%xmm3 - 43c25a: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 - 43c25f: 66 0f db d9 pand %xmm1,%xmm3 - 43c263: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43c267: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43c26b: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43c26f: 81 ea ff ff 00 00 sub $0xffff,%edx - 43c275: 0f 85 75 0c 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43c27b: 48 83 c6 04 add $0x4,%rsi - 43c27f: 48 01 ce add %rcx,%rsi - 43c282: 48 01 cf add %rcx,%rdi - 43c285: e9 76 0d 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43c28a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43c290: 48 83 e9 20 sub $0x20,%rcx - 43c294: 66 0f 6f 46 10 movdqa 0x10(%rsi),%xmm0 - 43c299: 66 0f 3a 0f 06 04 palignr $0x4,(%rsi),%xmm0 - 43c29f: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 43c2a3: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 - 43c2a8: 66 0f 3a 0f 5e 10 04 palignr $0x4,0x10(%rsi),%xmm3 - 43c2af: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 - 43c2b4: 66 0f db d8 pand %xmm0,%xmm3 - 43c2b8: 48 83 e9 20 sub $0x20,%rcx - 43c2bc: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43c2c0: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43c2c4: 66 0f 6f 5e 40 movdqa 0x40(%rsi),%xmm3 - 43c2c9: 66 0f 3a 0f 5e 30 04 palignr $0x4,0x30(%rsi),%xmm3 - 43c2d0: 81 da ff ff 00 00 sbb $0xffff,%edx - 43c2d6: 66 0f 6f 46 30 movdqa 0x30(%rsi),%xmm0 - 43c2db: 66 0f 3a 0f 46 20 04 palignr $0x4,0x20(%rsi),%xmm0 - 43c2e2: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 - 43c2e7: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43c2eb: 66 0f 74 5f 30 pcmpeqb 0x30(%rdi),%xmm3 - 43c2f0: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43c2f4: 74 be je 43c2b4 <__memcmp_ssse3+0x584> - 43c2f6: 66 0f db d8 pand %xmm0,%xmm3 - 43c2fa: 48 83 f9 00 cmp $0x0,%rcx - 43c2fe: 7d 06 jge 43c306 <__memcmp_ssse3+0x5d6> - 43c300: ff c2 inc %edx - 43c302: 48 83 c1 20 add $0x20,%rcx - 43c306: 85 d2 test %edx,%edx - 43c308: 0f 85 e2 0b 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43c30e: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43c312: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43c316: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43c31a: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43c31e: 81 ea ff ff 00 00 sub $0xffff,%edx - 43c324: 0f 85 c6 0b 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43c32a: 48 8d 76 04 lea 0x4(%rsi),%rsi - 43c32e: 48 01 ce add %rcx,%rsi - 43c331: 48 01 cf add %rcx,%rdi - 43c334: e9 c7 0c 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43c339: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43c340: 48 83 f9 50 cmp $0x50,%rcx - 43c344: 48 8d 49 d0 lea -0x30(%rcx),%rcx - 43c348: 89 d0 mov %edx,%eax - 43c34a: 73 54 jae 43c3a0 <__memcmp_ssse3+0x670> - 43c34c: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 - 43c351: 66 0f 6f d1 movdqa %xmm1,%xmm2 - 43c355: 66 0f 3a 0f 0e 05 palignr $0x5,(%rsi),%xmm1 - 43c35b: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 - 43c35f: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 - 43c364: 66 0f 3a 0f da 05 palignr $0x5,%xmm2,%xmm3 - 43c36a: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 - 43c36f: 66 0f db d9 pand %xmm1,%xmm3 - 43c373: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43c377: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43c37b: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43c37f: 81 ea ff ff 00 00 sub $0xffff,%edx - 43c385: 0f 85 65 0b 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43c38b: 48 83 c6 05 add $0x5,%rsi - 43c38f: 48 01 ce add %rcx,%rsi - 43c392: 48 01 cf add %rcx,%rdi - 43c395: e9 66 0c 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43c39a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43c3a0: 48 83 e9 20 sub $0x20,%rcx - 43c3a4: 66 0f 6f 46 10 movdqa 0x10(%rsi),%xmm0 - 43c3a9: 66 0f 3a 0f 06 05 palignr $0x5,(%rsi),%xmm0 - 43c3af: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 43c3b3: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 - 43c3b8: 66 0f 3a 0f 5e 10 05 palignr $0x5,0x10(%rsi),%xmm3 - 43c3bf: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 - 43c3c4: 66 0f db d8 pand %xmm0,%xmm3 - 43c3c8: 48 83 e9 20 sub $0x20,%rcx - 43c3cc: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43c3d0: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43c3d4: 66 0f 6f 5e 40 movdqa 0x40(%rsi),%xmm3 - 43c3d9: 66 0f 3a 0f 5e 30 05 palignr $0x5,0x30(%rsi),%xmm3 - 43c3e0: 81 da ff ff 00 00 sbb $0xffff,%edx - 43c3e6: 66 0f 6f 46 30 movdqa 0x30(%rsi),%xmm0 - 43c3eb: 66 0f 3a 0f 46 20 05 palignr $0x5,0x20(%rsi),%xmm0 - 43c3f2: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 - 43c3f7: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43c3fb: 66 0f 74 5f 30 pcmpeqb 0x30(%rdi),%xmm3 - 43c400: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43c404: 74 be je 43c3c4 <__memcmp_ssse3+0x694> - 43c406: 66 0f db d8 pand %xmm0,%xmm3 - 43c40a: 48 83 f9 00 cmp $0x0,%rcx - 43c40e: 7d 06 jge 43c416 <__memcmp_ssse3+0x6e6> - 43c410: ff c2 inc %edx - 43c412: 48 83 c1 20 add $0x20,%rcx - 43c416: 85 d2 test %edx,%edx - 43c418: 0f 85 d2 0a 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43c41e: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43c422: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43c426: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43c42a: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43c42e: 81 ea ff ff 00 00 sub $0xffff,%edx - 43c434: 0f 85 b6 0a 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43c43a: 48 8d 76 05 lea 0x5(%rsi),%rsi - 43c43e: 48 01 ce add %rcx,%rsi - 43c441: 48 01 cf add %rcx,%rdi - 43c444: e9 b7 0b 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43c449: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43c450: 48 83 f9 50 cmp $0x50,%rcx - 43c454: 48 8d 49 d0 lea -0x30(%rcx),%rcx - 43c458: 89 d0 mov %edx,%eax - 43c45a: 73 54 jae 43c4b0 <__memcmp_ssse3+0x780> - 43c45c: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 - 43c461: 66 0f 6f d1 movdqa %xmm1,%xmm2 - 43c465: 66 0f 3a 0f 0e 06 palignr $0x6,(%rsi),%xmm1 - 43c46b: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 - 43c46f: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 - 43c474: 66 0f 3a 0f da 06 palignr $0x6,%xmm2,%xmm3 - 43c47a: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 - 43c47f: 66 0f db d9 pand %xmm1,%xmm3 - 43c483: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43c487: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43c48b: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43c48f: 81 ea ff ff 00 00 sub $0xffff,%edx - 43c495: 0f 85 55 0a 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43c49b: 48 83 c6 06 add $0x6,%rsi - 43c49f: 48 01 ce add %rcx,%rsi - 43c4a2: 48 01 cf add %rcx,%rdi - 43c4a5: e9 56 0b 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43c4aa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43c4b0: 48 83 e9 20 sub $0x20,%rcx - 43c4b4: 66 0f 6f 46 10 movdqa 0x10(%rsi),%xmm0 - 43c4b9: 66 0f 3a 0f 06 06 palignr $0x6,(%rsi),%xmm0 - 43c4bf: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 43c4c3: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 - 43c4c8: 66 0f 3a 0f 5e 10 06 palignr $0x6,0x10(%rsi),%xmm3 - 43c4cf: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 - 43c4d4: 66 0f db d8 pand %xmm0,%xmm3 - 43c4d8: 48 83 e9 20 sub $0x20,%rcx - 43c4dc: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43c4e0: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43c4e4: 66 0f 6f 5e 40 movdqa 0x40(%rsi),%xmm3 - 43c4e9: 66 0f 3a 0f 5e 30 06 palignr $0x6,0x30(%rsi),%xmm3 - 43c4f0: 81 da ff ff 00 00 sbb $0xffff,%edx - 43c4f6: 66 0f 6f 46 30 movdqa 0x30(%rsi),%xmm0 - 43c4fb: 66 0f 3a 0f 46 20 06 palignr $0x6,0x20(%rsi),%xmm0 - 43c502: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 - 43c507: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43c50b: 66 0f 74 5f 30 pcmpeqb 0x30(%rdi),%xmm3 - 43c510: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43c514: 74 be je 43c4d4 <__memcmp_ssse3+0x7a4> - 43c516: 66 0f db d8 pand %xmm0,%xmm3 - 43c51a: 48 83 f9 00 cmp $0x0,%rcx - 43c51e: 7d 06 jge 43c526 <__memcmp_ssse3+0x7f6> - 43c520: ff c2 inc %edx - 43c522: 48 83 c1 20 add $0x20,%rcx - 43c526: 85 d2 test %edx,%edx - 43c528: 0f 85 c2 09 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43c52e: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43c532: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43c536: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43c53a: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43c53e: 81 ea ff ff 00 00 sub $0xffff,%edx - 43c544: 0f 85 a6 09 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43c54a: 48 8d 76 06 lea 0x6(%rsi),%rsi - 43c54e: 48 01 ce add %rcx,%rsi - 43c551: 48 01 cf add %rcx,%rdi - 43c554: e9 a7 0a 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43c559: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43c560: 48 83 f9 50 cmp $0x50,%rcx - 43c564: 48 8d 49 d0 lea -0x30(%rcx),%rcx - 43c568: 89 d0 mov %edx,%eax - 43c56a: 73 54 jae 43c5c0 <__memcmp_ssse3+0x890> - 43c56c: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 - 43c571: 66 0f 6f d1 movdqa %xmm1,%xmm2 - 43c575: 66 0f 3a 0f 0e 07 palignr $0x7,(%rsi),%xmm1 - 43c57b: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 - 43c57f: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 - 43c584: 66 0f 3a 0f da 07 palignr $0x7,%xmm2,%xmm3 - 43c58a: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 - 43c58f: 66 0f db d9 pand %xmm1,%xmm3 - 43c593: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43c597: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43c59b: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43c59f: 81 ea ff ff 00 00 sub $0xffff,%edx - 43c5a5: 0f 85 45 09 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43c5ab: 48 83 c6 07 add $0x7,%rsi - 43c5af: 48 01 ce add %rcx,%rsi - 43c5b2: 48 01 cf add %rcx,%rdi - 43c5b5: e9 46 0a 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43c5ba: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43c5c0: 48 83 e9 20 sub $0x20,%rcx - 43c5c4: 66 0f 6f 46 10 movdqa 0x10(%rsi),%xmm0 - 43c5c9: 66 0f 3a 0f 06 07 palignr $0x7,(%rsi),%xmm0 - 43c5cf: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 43c5d3: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 - 43c5d8: 66 0f 3a 0f 5e 10 07 palignr $0x7,0x10(%rsi),%xmm3 - 43c5df: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 - 43c5e4: 66 0f db d8 pand %xmm0,%xmm3 - 43c5e8: 48 83 e9 20 sub $0x20,%rcx - 43c5ec: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43c5f0: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43c5f4: 66 0f 6f 5e 40 movdqa 0x40(%rsi),%xmm3 - 43c5f9: 66 0f 3a 0f 5e 30 07 palignr $0x7,0x30(%rsi),%xmm3 - 43c600: 81 da ff ff 00 00 sbb $0xffff,%edx - 43c606: 66 0f 6f 46 30 movdqa 0x30(%rsi),%xmm0 - 43c60b: 66 0f 3a 0f 46 20 07 palignr $0x7,0x20(%rsi),%xmm0 - 43c612: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 - 43c617: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43c61b: 66 0f 74 5f 30 pcmpeqb 0x30(%rdi),%xmm3 - 43c620: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43c624: 74 be je 43c5e4 <__memcmp_ssse3+0x8b4> - 43c626: 66 0f db d8 pand %xmm0,%xmm3 - 43c62a: 48 83 f9 00 cmp $0x0,%rcx - 43c62e: 7d 06 jge 43c636 <__memcmp_ssse3+0x906> - 43c630: ff c2 inc %edx - 43c632: 48 83 c1 20 add $0x20,%rcx - 43c636: 85 d2 test %edx,%edx - 43c638: 0f 85 b2 08 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43c63e: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43c642: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43c646: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43c64a: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43c64e: 81 ea ff ff 00 00 sub $0xffff,%edx - 43c654: 0f 85 96 08 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43c65a: 48 8d 76 07 lea 0x7(%rsi),%rsi - 43c65e: 48 01 ce add %rcx,%rsi - 43c661: 48 01 cf add %rcx,%rdi - 43c664: e9 97 09 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43c669: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43c670: 48 83 f9 50 cmp $0x50,%rcx - 43c674: 48 8d 49 d0 lea -0x30(%rcx),%rcx - 43c678: 89 d0 mov %edx,%eax - 43c67a: 73 54 jae 43c6d0 <__memcmp_ssse3+0x9a0> - 43c67c: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 - 43c681: 66 0f 6f d1 movdqa %xmm1,%xmm2 - 43c685: 66 0f 3a 0f 0e 08 palignr $0x8,(%rsi),%xmm1 - 43c68b: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 - 43c68f: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 - 43c694: 66 0f 3a 0f da 08 palignr $0x8,%xmm2,%xmm3 - 43c69a: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 - 43c69f: 66 0f db d9 pand %xmm1,%xmm3 - 43c6a3: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43c6a7: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43c6ab: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43c6af: 81 ea ff ff 00 00 sub $0xffff,%edx - 43c6b5: 0f 85 35 08 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43c6bb: 48 83 c6 08 add $0x8,%rsi - 43c6bf: 48 01 ce add %rcx,%rsi - 43c6c2: 48 01 cf add %rcx,%rdi - 43c6c5: e9 36 09 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43c6ca: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43c6d0: 48 83 e9 20 sub $0x20,%rcx - 43c6d4: 66 0f 6f 46 10 movdqa 0x10(%rsi),%xmm0 - 43c6d9: 66 0f 3a 0f 06 08 palignr $0x8,(%rsi),%xmm0 - 43c6df: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 43c6e3: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 - 43c6e8: 66 0f 3a 0f 5e 10 08 palignr $0x8,0x10(%rsi),%xmm3 - 43c6ef: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 - 43c6f4: 66 0f db d8 pand %xmm0,%xmm3 - 43c6f8: 48 83 e9 20 sub $0x20,%rcx - 43c6fc: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43c700: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43c704: 66 0f 6f 5e 40 movdqa 0x40(%rsi),%xmm3 - 43c709: 66 0f 3a 0f 5e 30 08 palignr $0x8,0x30(%rsi),%xmm3 - 43c710: 81 da ff ff 00 00 sbb $0xffff,%edx - 43c716: 66 0f 6f 46 30 movdqa 0x30(%rsi),%xmm0 - 43c71b: 66 0f 3a 0f 46 20 08 palignr $0x8,0x20(%rsi),%xmm0 - 43c722: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 - 43c727: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43c72b: 66 0f 74 5f 30 pcmpeqb 0x30(%rdi),%xmm3 - 43c730: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43c734: 74 be je 43c6f4 <__memcmp_ssse3+0x9c4> - 43c736: 66 0f db d8 pand %xmm0,%xmm3 - 43c73a: 48 83 f9 00 cmp $0x0,%rcx - 43c73e: 7d 06 jge 43c746 <__memcmp_ssse3+0xa16> - 43c740: ff c2 inc %edx - 43c742: 48 83 c1 20 add $0x20,%rcx - 43c746: 85 d2 test %edx,%edx - 43c748: 0f 85 a2 07 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43c74e: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43c752: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43c756: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43c75a: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43c75e: 81 ea ff ff 00 00 sub $0xffff,%edx - 43c764: 0f 85 86 07 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43c76a: 48 8d 76 08 lea 0x8(%rsi),%rsi - 43c76e: 48 01 ce add %rcx,%rsi - 43c771: 48 01 cf add %rcx,%rdi - 43c774: e9 87 08 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43c779: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43c780: 48 83 f9 50 cmp $0x50,%rcx - 43c784: 48 8d 49 d0 lea -0x30(%rcx),%rcx - 43c788: 89 d0 mov %edx,%eax - 43c78a: 73 54 jae 43c7e0 <__memcmp_ssse3+0xab0> - 43c78c: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 - 43c791: 66 0f 6f d1 movdqa %xmm1,%xmm2 - 43c795: 66 0f 3a 0f 0e 09 palignr $0x9,(%rsi),%xmm1 - 43c79b: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 - 43c79f: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 - 43c7a4: 66 0f 3a 0f da 09 palignr $0x9,%xmm2,%xmm3 - 43c7aa: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 - 43c7af: 66 0f db d9 pand %xmm1,%xmm3 - 43c7b3: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43c7b7: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43c7bb: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43c7bf: 81 ea ff ff 00 00 sub $0xffff,%edx - 43c7c5: 0f 85 25 07 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43c7cb: 48 83 c6 09 add $0x9,%rsi - 43c7cf: 48 01 ce add %rcx,%rsi - 43c7d2: 48 01 cf add %rcx,%rdi - 43c7d5: e9 26 08 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43c7da: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43c7e0: 48 83 e9 20 sub $0x20,%rcx - 43c7e4: 66 0f 6f 46 10 movdqa 0x10(%rsi),%xmm0 - 43c7e9: 66 0f 3a 0f 06 09 palignr $0x9,(%rsi),%xmm0 - 43c7ef: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 43c7f3: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 - 43c7f8: 66 0f 3a 0f 5e 10 09 palignr $0x9,0x10(%rsi),%xmm3 - 43c7ff: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 - 43c804: 66 0f db d8 pand %xmm0,%xmm3 - 43c808: 48 83 e9 20 sub $0x20,%rcx - 43c80c: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43c810: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43c814: 66 0f 6f 5e 40 movdqa 0x40(%rsi),%xmm3 - 43c819: 66 0f 3a 0f 5e 30 09 palignr $0x9,0x30(%rsi),%xmm3 - 43c820: 81 da ff ff 00 00 sbb $0xffff,%edx - 43c826: 66 0f 6f 46 30 movdqa 0x30(%rsi),%xmm0 - 43c82b: 66 0f 3a 0f 46 20 09 palignr $0x9,0x20(%rsi),%xmm0 - 43c832: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 - 43c837: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43c83b: 66 0f 74 5f 30 pcmpeqb 0x30(%rdi),%xmm3 - 43c840: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43c844: 74 be je 43c804 <__memcmp_ssse3+0xad4> - 43c846: 66 0f db d8 pand %xmm0,%xmm3 - 43c84a: 48 83 f9 00 cmp $0x0,%rcx - 43c84e: 7d 06 jge 43c856 <__memcmp_ssse3+0xb26> - 43c850: ff c2 inc %edx - 43c852: 48 83 c1 20 add $0x20,%rcx - 43c856: 85 d2 test %edx,%edx - 43c858: 0f 85 92 06 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43c85e: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43c862: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43c866: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43c86a: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43c86e: 81 ea ff ff 00 00 sub $0xffff,%edx - 43c874: 0f 85 76 06 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43c87a: 48 8d 76 09 lea 0x9(%rsi),%rsi - 43c87e: 48 01 ce add %rcx,%rsi - 43c881: 48 01 cf add %rcx,%rdi - 43c884: e9 77 07 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43c889: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43c890: 48 83 f9 50 cmp $0x50,%rcx - 43c894: 48 8d 49 d0 lea -0x30(%rcx),%rcx - 43c898: 89 d0 mov %edx,%eax - 43c89a: 73 54 jae 43c8f0 <__memcmp_ssse3+0xbc0> - 43c89c: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 - 43c8a1: 66 0f 6f d1 movdqa %xmm1,%xmm2 - 43c8a5: 66 0f 3a 0f 0e 0a palignr $0xa,(%rsi),%xmm1 - 43c8ab: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 - 43c8af: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 - 43c8b4: 66 0f 3a 0f da 0a palignr $0xa,%xmm2,%xmm3 - 43c8ba: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 - 43c8bf: 66 0f db d9 pand %xmm1,%xmm3 - 43c8c3: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43c8c7: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43c8cb: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43c8cf: 81 ea ff ff 00 00 sub $0xffff,%edx - 43c8d5: 0f 85 15 06 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43c8db: 48 83 c6 0a add $0xa,%rsi - 43c8df: 48 01 ce add %rcx,%rsi - 43c8e2: 48 01 cf add %rcx,%rdi - 43c8e5: e9 16 07 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43c8ea: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43c8f0: 48 83 e9 20 sub $0x20,%rcx - 43c8f4: 66 0f 6f 46 10 movdqa 0x10(%rsi),%xmm0 - 43c8f9: 66 0f 3a 0f 06 0a palignr $0xa,(%rsi),%xmm0 - 43c8ff: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 43c903: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 - 43c908: 66 0f 3a 0f 5e 10 0a palignr $0xa,0x10(%rsi),%xmm3 - 43c90f: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 - 43c914: 66 0f db d8 pand %xmm0,%xmm3 - 43c918: 48 83 e9 20 sub $0x20,%rcx - 43c91c: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43c920: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43c924: 66 0f 6f 5e 40 movdqa 0x40(%rsi),%xmm3 - 43c929: 66 0f 3a 0f 5e 30 0a palignr $0xa,0x30(%rsi),%xmm3 - 43c930: 81 da ff ff 00 00 sbb $0xffff,%edx - 43c936: 66 0f 6f 46 30 movdqa 0x30(%rsi),%xmm0 - 43c93b: 66 0f 3a 0f 46 20 0a palignr $0xa,0x20(%rsi),%xmm0 - 43c942: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 - 43c947: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43c94b: 66 0f 74 5f 30 pcmpeqb 0x30(%rdi),%xmm3 - 43c950: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43c954: 74 be je 43c914 <__memcmp_ssse3+0xbe4> - 43c956: 66 0f db d8 pand %xmm0,%xmm3 - 43c95a: 48 83 f9 00 cmp $0x0,%rcx - 43c95e: 7d 06 jge 43c966 <__memcmp_ssse3+0xc36> - 43c960: ff c2 inc %edx - 43c962: 48 83 c1 20 add $0x20,%rcx - 43c966: 85 d2 test %edx,%edx - 43c968: 0f 85 82 05 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43c96e: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43c972: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43c976: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43c97a: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43c97e: 81 ea ff ff 00 00 sub $0xffff,%edx - 43c984: 0f 85 66 05 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43c98a: 48 8d 76 0a lea 0xa(%rsi),%rsi - 43c98e: 48 01 ce add %rcx,%rsi - 43c991: 48 01 cf add %rcx,%rdi - 43c994: e9 67 06 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43c999: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43c9a0: 48 83 f9 50 cmp $0x50,%rcx - 43c9a4: 48 8d 49 d0 lea -0x30(%rcx),%rcx - 43c9a8: 89 d0 mov %edx,%eax - 43c9aa: 73 54 jae 43ca00 <__memcmp_ssse3+0xcd0> - 43c9ac: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 - 43c9b1: 66 0f 6f d1 movdqa %xmm1,%xmm2 - 43c9b5: 66 0f 3a 0f 0e 0b palignr $0xb,(%rsi),%xmm1 - 43c9bb: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 - 43c9bf: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 - 43c9c4: 66 0f 3a 0f da 0b palignr $0xb,%xmm2,%xmm3 - 43c9ca: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 - 43c9cf: 66 0f db d9 pand %xmm1,%xmm3 - 43c9d3: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43c9d7: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43c9db: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43c9df: 81 ea ff ff 00 00 sub $0xffff,%edx - 43c9e5: 0f 85 05 05 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43c9eb: 48 83 c6 0b add $0xb,%rsi - 43c9ef: 48 01 ce add %rcx,%rsi - 43c9f2: 48 01 cf add %rcx,%rdi - 43c9f5: e9 06 06 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43c9fa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43ca00: 48 83 e9 20 sub $0x20,%rcx - 43ca04: 66 0f 6f 46 10 movdqa 0x10(%rsi),%xmm0 - 43ca09: 66 0f 3a 0f 06 0b palignr $0xb,(%rsi),%xmm0 - 43ca0f: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 43ca13: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 - 43ca18: 66 0f 3a 0f 5e 10 0b palignr $0xb,0x10(%rsi),%xmm3 - 43ca1f: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 - 43ca24: 66 0f db d8 pand %xmm0,%xmm3 - 43ca28: 48 83 e9 20 sub $0x20,%rcx - 43ca2c: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43ca30: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43ca34: 66 0f 6f 5e 40 movdqa 0x40(%rsi),%xmm3 - 43ca39: 66 0f 3a 0f 5e 30 0b palignr $0xb,0x30(%rsi),%xmm3 - 43ca40: 81 da ff ff 00 00 sbb $0xffff,%edx - 43ca46: 66 0f 6f 46 30 movdqa 0x30(%rsi),%xmm0 - 43ca4b: 66 0f 3a 0f 46 20 0b palignr $0xb,0x20(%rsi),%xmm0 - 43ca52: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 - 43ca57: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43ca5b: 66 0f 74 5f 30 pcmpeqb 0x30(%rdi),%xmm3 - 43ca60: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43ca64: 74 be je 43ca24 <__memcmp_ssse3+0xcf4> - 43ca66: 66 0f db d8 pand %xmm0,%xmm3 - 43ca6a: 48 83 f9 00 cmp $0x0,%rcx - 43ca6e: 7d 06 jge 43ca76 <__memcmp_ssse3+0xd46> - 43ca70: ff c2 inc %edx - 43ca72: 48 83 c1 20 add $0x20,%rcx - 43ca76: 85 d2 test %edx,%edx - 43ca78: 0f 85 72 04 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43ca7e: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43ca82: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43ca86: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43ca8a: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43ca8e: 81 ea ff ff 00 00 sub $0xffff,%edx - 43ca94: 0f 85 56 04 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43ca9a: 48 8d 76 0b lea 0xb(%rsi),%rsi - 43ca9e: 48 01 ce add %rcx,%rsi - 43caa1: 48 01 cf add %rcx,%rdi - 43caa4: e9 57 05 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43caa9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43cab0: 48 83 f9 50 cmp $0x50,%rcx - 43cab4: 48 8d 49 d0 lea -0x30(%rcx),%rcx - 43cab8: 89 d0 mov %edx,%eax - 43caba: 73 54 jae 43cb10 <__memcmp_ssse3+0xde0> - 43cabc: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 - 43cac1: 66 0f 6f d1 movdqa %xmm1,%xmm2 - 43cac5: 66 0f 3a 0f 0e 0c palignr $0xc,(%rsi),%xmm1 - 43cacb: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 - 43cacf: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 - 43cad4: 66 0f 3a 0f da 0c palignr $0xc,%xmm2,%xmm3 - 43cada: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 - 43cadf: 66 0f db d9 pand %xmm1,%xmm3 - 43cae3: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43cae7: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43caeb: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43caef: 81 ea ff ff 00 00 sub $0xffff,%edx - 43caf5: 0f 85 f5 03 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43cafb: 48 83 c6 0c add $0xc,%rsi - 43caff: 48 01 ce add %rcx,%rsi - 43cb02: 48 01 cf add %rcx,%rdi - 43cb05: e9 f6 04 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43cb0a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43cb10: 48 83 e9 20 sub $0x20,%rcx - 43cb14: 66 0f 6f 46 10 movdqa 0x10(%rsi),%xmm0 - 43cb19: 66 0f 3a 0f 06 0c palignr $0xc,(%rsi),%xmm0 - 43cb1f: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 43cb23: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 - 43cb28: 66 0f 3a 0f 5e 10 0c palignr $0xc,0x10(%rsi),%xmm3 - 43cb2f: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 - 43cb34: 66 0f db d8 pand %xmm0,%xmm3 - 43cb38: 48 83 e9 20 sub $0x20,%rcx - 43cb3c: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43cb40: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43cb44: 66 0f 6f 5e 40 movdqa 0x40(%rsi),%xmm3 - 43cb49: 66 0f 3a 0f 5e 30 0c palignr $0xc,0x30(%rsi),%xmm3 - 43cb50: 81 da ff ff 00 00 sbb $0xffff,%edx - 43cb56: 66 0f 6f 46 30 movdqa 0x30(%rsi),%xmm0 - 43cb5b: 66 0f 3a 0f 46 20 0c palignr $0xc,0x20(%rsi),%xmm0 - 43cb62: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 - 43cb67: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43cb6b: 66 0f 74 5f 30 pcmpeqb 0x30(%rdi),%xmm3 - 43cb70: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43cb74: 74 be je 43cb34 <__memcmp_ssse3+0xe04> - 43cb76: 66 0f db d8 pand %xmm0,%xmm3 - 43cb7a: 48 83 f9 00 cmp $0x0,%rcx - 43cb7e: 7d 06 jge 43cb86 <__memcmp_ssse3+0xe56> - 43cb80: ff c2 inc %edx - 43cb82: 48 83 c1 20 add $0x20,%rcx - 43cb86: 85 d2 test %edx,%edx - 43cb88: 0f 85 62 03 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43cb8e: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43cb92: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43cb96: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43cb9a: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43cb9e: 81 ea ff ff 00 00 sub $0xffff,%edx - 43cba4: 0f 85 46 03 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43cbaa: 48 8d 76 0c lea 0xc(%rsi),%rsi - 43cbae: 48 01 ce add %rcx,%rsi - 43cbb1: 48 01 cf add %rcx,%rdi - 43cbb4: e9 47 04 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43cbb9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43cbc0: 48 83 f9 50 cmp $0x50,%rcx - 43cbc4: 48 8d 49 d0 lea -0x30(%rcx),%rcx - 43cbc8: 89 d0 mov %edx,%eax - 43cbca: 73 54 jae 43cc20 <__memcmp_ssse3+0xef0> - 43cbcc: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 - 43cbd1: 66 0f 6f d1 movdqa %xmm1,%xmm2 - 43cbd5: 66 0f 3a 0f 0e 0d palignr $0xd,(%rsi),%xmm1 - 43cbdb: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 - 43cbdf: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 - 43cbe4: 66 0f 3a 0f da 0d palignr $0xd,%xmm2,%xmm3 - 43cbea: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 - 43cbef: 66 0f db d9 pand %xmm1,%xmm3 - 43cbf3: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43cbf7: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43cbfb: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43cbff: 81 ea ff ff 00 00 sub $0xffff,%edx - 43cc05: 0f 85 e5 02 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43cc0b: 48 83 c6 0d add $0xd,%rsi - 43cc0f: 48 01 ce add %rcx,%rsi - 43cc12: 48 01 cf add %rcx,%rdi - 43cc15: e9 e6 03 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43cc1a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43cc20: 48 83 e9 20 sub $0x20,%rcx - 43cc24: 66 0f 6f 46 10 movdqa 0x10(%rsi),%xmm0 - 43cc29: 66 0f 3a 0f 06 0d palignr $0xd,(%rsi),%xmm0 - 43cc2f: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 43cc33: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 - 43cc38: 66 0f 3a 0f 5e 10 0d palignr $0xd,0x10(%rsi),%xmm3 - 43cc3f: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 - 43cc44: 66 0f db d8 pand %xmm0,%xmm3 - 43cc48: 48 83 e9 20 sub $0x20,%rcx - 43cc4c: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43cc50: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43cc54: 66 0f 6f 5e 40 movdqa 0x40(%rsi),%xmm3 - 43cc59: 66 0f 3a 0f 5e 30 0d palignr $0xd,0x30(%rsi),%xmm3 - 43cc60: 81 da ff ff 00 00 sbb $0xffff,%edx - 43cc66: 66 0f 6f 46 30 movdqa 0x30(%rsi),%xmm0 - 43cc6b: 66 0f 3a 0f 46 20 0d palignr $0xd,0x20(%rsi),%xmm0 - 43cc72: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 - 43cc77: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43cc7b: 66 0f 74 5f 30 pcmpeqb 0x30(%rdi),%xmm3 - 43cc80: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43cc84: 74 be je 43cc44 <__memcmp_ssse3+0xf14> - 43cc86: 66 0f db d8 pand %xmm0,%xmm3 - 43cc8a: 48 83 f9 00 cmp $0x0,%rcx - 43cc8e: 7d 06 jge 43cc96 <__memcmp_ssse3+0xf66> - 43cc90: ff c2 inc %edx - 43cc92: 48 83 c1 20 add $0x20,%rcx - 43cc96: 85 d2 test %edx,%edx - 43cc98: 0f 85 52 02 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43cc9e: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43cca2: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43cca6: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43ccaa: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43ccae: 81 ea ff ff 00 00 sub $0xffff,%edx - 43ccb4: 0f 85 36 02 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43ccba: 48 8d 76 0d lea 0xd(%rsi),%rsi - 43ccbe: 48 01 ce add %rcx,%rsi - 43ccc1: 48 01 cf add %rcx,%rdi - 43ccc4: e9 37 03 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43ccc9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43ccd0: 48 83 f9 50 cmp $0x50,%rcx - 43ccd4: 48 8d 49 d0 lea -0x30(%rcx),%rcx - 43ccd8: 89 d0 mov %edx,%eax - 43ccda: 73 54 jae 43cd30 <__memcmp_ssse3+0x1000> - 43ccdc: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 - 43cce1: 66 0f 6f d1 movdqa %xmm1,%xmm2 - 43cce5: 66 0f 3a 0f 0e 0e palignr $0xe,(%rsi),%xmm1 - 43cceb: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 - 43ccef: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 - 43ccf4: 66 0f 3a 0f da 0e palignr $0xe,%xmm2,%xmm3 - 43ccfa: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 - 43ccff: 66 0f db d9 pand %xmm1,%xmm3 - 43cd03: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43cd07: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43cd0b: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43cd0f: 81 ea ff ff 00 00 sub $0xffff,%edx - 43cd15: 0f 85 d5 01 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43cd1b: 48 83 c6 0e add $0xe,%rsi - 43cd1f: 48 01 ce add %rcx,%rsi - 43cd22: 48 01 cf add %rcx,%rdi - 43cd25: e9 d6 02 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43cd2a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43cd30: 48 83 e9 20 sub $0x20,%rcx - 43cd34: 66 0f 6f 46 10 movdqa 0x10(%rsi),%xmm0 - 43cd39: 66 0f 3a 0f 06 0e palignr $0xe,(%rsi),%xmm0 - 43cd3f: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 43cd43: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 - 43cd48: 66 0f 3a 0f 5e 10 0e palignr $0xe,0x10(%rsi),%xmm3 - 43cd4f: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 - 43cd54: 66 0f db d8 pand %xmm0,%xmm3 - 43cd58: 48 83 e9 20 sub $0x20,%rcx - 43cd5c: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43cd60: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43cd64: 66 0f 6f 5e 40 movdqa 0x40(%rsi),%xmm3 - 43cd69: 66 0f 3a 0f 5e 30 0e palignr $0xe,0x30(%rsi),%xmm3 - 43cd70: 81 da ff ff 00 00 sbb $0xffff,%edx - 43cd76: 66 0f 6f 46 30 movdqa 0x30(%rsi),%xmm0 - 43cd7b: 66 0f 3a 0f 46 20 0e palignr $0xe,0x20(%rsi),%xmm0 - 43cd82: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 - 43cd87: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43cd8b: 66 0f 74 5f 30 pcmpeqb 0x30(%rdi),%xmm3 - 43cd90: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43cd94: 74 be je 43cd54 <__memcmp_ssse3+0x1024> - 43cd96: 66 0f db d8 pand %xmm0,%xmm3 - 43cd9a: 48 83 f9 00 cmp $0x0,%rcx - 43cd9e: 7d 06 jge 43cda6 <__memcmp_ssse3+0x1076> - 43cda0: ff c2 inc %edx - 43cda2: 48 83 c1 20 add $0x20,%rcx - 43cda6: 85 d2 test %edx,%edx - 43cda8: 0f 85 42 01 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43cdae: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43cdb2: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43cdb6: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43cdba: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43cdbe: 81 ea ff ff 00 00 sub $0xffff,%edx - 43cdc4: 0f 85 26 01 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43cdca: 48 8d 76 0e lea 0xe(%rsi),%rsi - 43cdce: 48 01 ce add %rcx,%rsi - 43cdd1: 48 01 cf add %rcx,%rdi - 43cdd4: e9 27 02 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43cdd9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43cde0: 48 83 f9 50 cmp $0x50,%rcx - 43cde4: 48 8d 49 d0 lea -0x30(%rcx),%rcx - 43cde8: 89 d0 mov %edx,%eax - 43cdea: 73 54 jae 43ce40 <__memcmp_ssse3+0x1110> - 43cdec: 66 0f 6f 4e 10 movdqa 0x10(%rsi),%xmm1 - 43cdf1: 66 0f 6f d1 movdqa %xmm1,%xmm2 - 43cdf5: 66 0f 3a 0f 0e 0f palignr $0xf,(%rsi),%xmm1 - 43cdfb: 66 0f 74 0f pcmpeqb (%rdi),%xmm1 - 43cdff: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 - 43ce04: 66 0f 3a 0f da 0f palignr $0xf,%xmm2,%xmm3 - 43ce0a: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 - 43ce0f: 66 0f db d9 pand %xmm1,%xmm3 - 43ce13: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43ce17: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43ce1b: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43ce1f: 81 ea ff ff 00 00 sub $0xffff,%edx - 43ce25: 0f 85 c5 00 00 00 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43ce2b: 48 83 c6 0f add $0xf,%rsi - 43ce2f: 48 01 ce add %rcx,%rsi - 43ce32: 48 01 cf add %rcx,%rdi - 43ce35: e9 c6 01 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43ce3a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43ce40: 48 83 e9 20 sub $0x20,%rcx - 43ce44: 66 0f 6f 46 10 movdqa 0x10(%rsi),%xmm0 - 43ce49: 66 0f 3a 0f 06 0f palignr $0xf,(%rsi),%xmm0 - 43ce4f: 66 0f 74 07 pcmpeqb (%rdi),%xmm0 - 43ce53: 66 0f 6f 5e 20 movdqa 0x20(%rsi),%xmm3 - 43ce58: 66 0f 3a 0f 5e 10 0f palignr $0xf,0x10(%rsi),%xmm3 - 43ce5f: 66 0f 74 5f 10 pcmpeqb 0x10(%rdi),%xmm3 - 43ce64: 66 0f db d8 pand %xmm0,%xmm3 - 43ce68: 48 83 e9 20 sub $0x20,%rcx - 43ce6c: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43ce70: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43ce74: 66 0f 6f 5e 40 movdqa 0x40(%rsi),%xmm3 - 43ce79: 66 0f 3a 0f 5e 30 0f palignr $0xf,0x30(%rsi),%xmm3 - 43ce80: 81 da ff ff 00 00 sbb $0xffff,%edx - 43ce86: 66 0f 6f 46 30 movdqa 0x30(%rsi),%xmm0 - 43ce8b: 66 0f 3a 0f 46 20 0f palignr $0xf,0x20(%rsi),%xmm0 - 43ce92: 66 0f 74 47 20 pcmpeqb 0x20(%rdi),%xmm0 - 43ce97: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43ce9b: 66 0f 74 5f 30 pcmpeqb 0x30(%rdi),%xmm3 - 43cea0: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43cea4: 74 be je 43ce64 <__memcmp_ssse3+0x1134> - 43cea6: 66 0f db d8 pand %xmm0,%xmm3 - 43ceaa: 48 83 f9 00 cmp $0x0,%rcx - 43ceae: 7d 06 jge 43ceb6 <__memcmp_ssse3+0x1186> - 43ceb0: ff c2 inc %edx - 43ceb2: 48 83 c1 20 add $0x20,%rcx - 43ceb6: 85 d2 test %edx,%edx - 43ceb8: 75 36 jne 43cef0 <__memcmp_ssse3+0x11c0> - 43ceba: 66 0f d7 d3 pmovmskb %xmm3,%edx - 43cebe: 66 0f 6f c8 movdqa %xmm0,%xmm1 - 43cec2: 48 8d 7f 20 lea 0x20(%rdi),%rdi - 43cec6: 48 8d 76 20 lea 0x20(%rsi),%rsi - 43ceca: 81 ea ff ff 00 00 sub $0xffff,%edx - 43ced0: 75 1e jne 43cef0 <__memcmp_ssse3+0x11c0> - 43ced2: 48 8d 76 0f lea 0xf(%rsi),%rsi - 43ced6: 48 01 ce add %rcx,%rsi - 43ced9: 48 01 cf add %rcx,%rdi - 43cedc: e9 1f 01 00 00 jmpq 43d000 <__memcmp_ssse3+0x12d0> - 43cee1: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43cee6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43ceed: 00 00 00 - 43cef0: 66 44 0f d7 c1 pmovmskb %xmm1,%r8d - 43cef5: 41 81 e8 ff ff 00 00 sub $0xffff,%r8d - 43cefc: 74 0b je 43cf09 <__memcmp_ssse3+0x11d9> - 43cefe: 48 8d 76 f0 lea -0x10(%rsi),%rsi - 43cf02: 48 8d 7f f0 lea -0x10(%rdi),%rdi - 43cf06: 44 89 c2 mov %r8d,%edx - 43cf09: 48 01 c6 add %rax,%rsi - 43cf0c: 84 d2 test %dl,%dl - 43cf0e: 0f 84 ac 00 00 00 je 43cfc0 <__memcmp_ssse3+0x1290> - 43cf14: f6 c2 01 test $0x1,%dl - 43cf17: 75 37 jne 43cf50 <__memcmp_ssse3+0x1220> - 43cf19: f6 c2 02 test $0x2,%dl - 43cf1c: 75 42 jne 43cf60 <__memcmp_ssse3+0x1230> - 43cf1e: f6 c2 04 test $0x4,%dl - 43cf21: 75 4d jne 43cf70 <__memcmp_ssse3+0x1240> - 43cf23: f6 c2 08 test $0x8,%dl - 43cf26: 75 58 jne 43cf80 <__memcmp_ssse3+0x1250> - 43cf28: f6 c2 10 test $0x10,%dl - 43cf2b: 75 63 jne 43cf90 <__memcmp_ssse3+0x1260> - 43cf2d: f6 c2 20 test $0x20,%dl - 43cf30: 75 6e jne 43cfa0 <__memcmp_ssse3+0x1270> - 43cf32: f6 c2 40 test $0x40,%dl - 43cf35: 75 79 jne 43cfb0 <__memcmp_ssse3+0x1280> - 43cf37: 0f b6 47 f7 movzbl -0x9(%rdi),%eax - 43cf3b: 0f b6 56 f7 movzbl -0x9(%rsi),%edx - 43cf3f: 29 d0 sub %edx,%eax - 43cf41: c3 retq - 43cf42: 0f 1f 40 00 nopl 0x0(%rax) - 43cf46: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43cf4d: 00 00 00 - 43cf50: 0f b6 47 f0 movzbl -0x10(%rdi),%eax - 43cf54: 0f b6 56 f0 movzbl -0x10(%rsi),%edx - 43cf58: 29 d0 sub %edx,%eax - 43cf5a: c3 retq - 43cf5b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43cf60: 0f b6 47 f1 movzbl -0xf(%rdi),%eax - 43cf64: 0f b6 56 f1 movzbl -0xf(%rsi),%edx - 43cf68: 29 d0 sub %edx,%eax - 43cf6a: c3 retq - 43cf6b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43cf70: 0f b6 47 f2 movzbl -0xe(%rdi),%eax - 43cf74: 0f b6 56 f2 movzbl -0xe(%rsi),%edx - 43cf78: 29 d0 sub %edx,%eax - 43cf7a: c3 retq - 43cf7b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43cf80: 0f b6 47 f3 movzbl -0xd(%rdi),%eax - 43cf84: 0f b6 56 f3 movzbl -0xd(%rsi),%edx - 43cf88: 29 d0 sub %edx,%eax - 43cf8a: c3 retq - 43cf8b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43cf90: 0f b6 47 f4 movzbl -0xc(%rdi),%eax - 43cf94: 0f b6 56 f4 movzbl -0xc(%rsi),%edx - 43cf98: 29 d0 sub %edx,%eax - 43cf9a: c3 retq - 43cf9b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43cfa0: 0f b6 47 f5 movzbl -0xb(%rdi),%eax - 43cfa4: 0f b6 56 f5 movzbl -0xb(%rsi),%edx - 43cfa8: 29 d0 sub %edx,%eax - 43cfaa: c3 retq - 43cfab: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43cfb0: 0f b6 47 f6 movzbl -0xa(%rdi),%eax - 43cfb4: 0f b6 56 f6 movzbl -0xa(%rsi),%edx - 43cfb8: 29 d0 sub %edx,%eax - 43cfba: c3 retq - 43cfbb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43cfc0: 48 8d 7f 08 lea 0x8(%rdi),%rdi - 43cfc4: 48 8d 76 08 lea 0x8(%rsi),%rsi - 43cfc8: f6 c6 01 test $0x1,%dh - 43cfcb: 75 83 jne 43cf50 <__memcmp_ssse3+0x1220> - 43cfcd: f6 c6 02 test $0x2,%dh - 43cfd0: 75 8e jne 43cf60 <__memcmp_ssse3+0x1230> - 43cfd2: f6 c6 04 test $0x4,%dh - 43cfd5: 75 99 jne 43cf70 <__memcmp_ssse3+0x1240> - 43cfd7: f6 c6 08 test $0x8,%dh - 43cfda: 75 a4 jne 43cf80 <__memcmp_ssse3+0x1250> - 43cfdc: f6 c6 10 test $0x10,%dh - 43cfdf: 75 af jne 43cf90 <__memcmp_ssse3+0x1260> - 43cfe1: f6 c6 20 test $0x20,%dh - 43cfe4: 75 ba jne 43cfa0 <__memcmp_ssse3+0x1270> - 43cfe6: f6 c6 40 test $0x40,%dh - 43cfe9: 75 c5 jne 43cfb0 <__memcmp_ssse3+0x1280> - 43cfeb: 0f b6 47 f7 movzbl -0x9(%rdi),%eax - 43cfef: 0f b6 56 f7 movzbl -0x9(%rsi),%edx - 43cff3: 29 d0 sub %edx,%eax - 43cff5: c3 retq - 43cff6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43cffd: 00 00 00 - 43d000: 83 f9 08 cmp $0x8,%ecx - 43d003: 73 4b jae 43d050 <__memcmp_ssse3+0x1320> - 43d005: 83 f9 00 cmp $0x0,%ecx - 43d008: 0f 84 5c 02 00 00 je 43d26a <__memcmp_ssse3+0x153a> - 43d00e: 83 f9 01 cmp $0x1,%ecx - 43d011: 0f 84 f3 02 00 00 je 43d30a <__memcmp_ssse3+0x15da> - 43d017: 83 f9 02 cmp $0x2,%ecx - 43d01a: 0f 84 9a 03 00 00 je 43d3ba <__memcmp_ssse3+0x168a> - 43d020: 83 f9 03 cmp $0x3,%ecx - 43d023: 0f 84 29 04 00 00 je 43d452 <__memcmp_ssse3+0x1722> - 43d029: 83 f9 04 cmp $0x4,%ecx - 43d02c: 0f 84 2a 02 00 00 je 43d25c <__memcmp_ssse3+0x152c> - 43d032: 83 f9 05 cmp $0x5,%ecx - 43d035: 0f 84 c1 02 00 00 je 43d2fc <__memcmp_ssse3+0x15cc> - 43d03b: 83 f9 06 cmp $0x6,%ecx - 43d03e: 0f 84 68 03 00 00 je 43d3ac <__memcmp_ssse3+0x167c> - 43d044: e9 ff 03 00 00 jmpq 43d448 <__memcmp_ssse3+0x1718> - 43d049: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43d050: 83 f9 10 cmp $0x10,%ecx - 43d053: 73 4b jae 43d0a0 <__memcmp_ssse3+0x1370> - 43d055: 83 f9 08 cmp $0x8,%ecx - 43d058: 0f 84 f0 01 00 00 je 43d24e <__memcmp_ssse3+0x151e> - 43d05e: 83 f9 09 cmp $0x9,%ecx - 43d061: 0f 84 87 02 00 00 je 43d2ee <__memcmp_ssse3+0x15be> - 43d067: 83 f9 0a cmp $0xa,%ecx - 43d06a: 0f 84 2e 03 00 00 je 43d39e <__memcmp_ssse3+0x166e> - 43d070: 83 f9 0b cmp $0xb,%ecx - 43d073: 0f 84 c5 03 00 00 je 43d43e <__memcmp_ssse3+0x170e> - 43d079: 83 f9 0c cmp $0xc,%ecx - 43d07c: 0f 84 be 01 00 00 je 43d240 <__memcmp_ssse3+0x1510> - 43d082: 83 f9 0d cmp $0xd,%ecx - 43d085: 0f 84 55 02 00 00 je 43d2e0 <__memcmp_ssse3+0x15b0> - 43d08b: 83 f9 0e cmp $0xe,%ecx - 43d08e: 0f 84 fc 02 00 00 je 43d390 <__memcmp_ssse3+0x1660> - 43d094: e9 9b 03 00 00 jmpq 43d434 <__memcmp_ssse3+0x1704> - 43d099: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43d0a0: 83 f9 18 cmp $0x18,%ecx - 43d0a3: 73 4b jae 43d0f0 <__memcmp_ssse3+0x13c0> - 43d0a5: 83 f9 10 cmp $0x10,%ecx - 43d0a8: 0f 84 84 01 00 00 je 43d232 <__memcmp_ssse3+0x1502> - 43d0ae: 83 f9 11 cmp $0x11,%ecx - 43d0b1: 0f 84 1b 02 00 00 je 43d2d2 <__memcmp_ssse3+0x15a2> - 43d0b7: 83 f9 12 cmp $0x12,%ecx - 43d0ba: 0f 84 c2 02 00 00 je 43d382 <__memcmp_ssse3+0x1652> - 43d0c0: 83 f9 13 cmp $0x13,%ecx - 43d0c3: 0f 84 61 03 00 00 je 43d42a <__memcmp_ssse3+0x16fa> - 43d0c9: 83 f9 14 cmp $0x14,%ecx - 43d0cc: 0f 84 52 01 00 00 je 43d224 <__memcmp_ssse3+0x14f4> - 43d0d2: 83 f9 15 cmp $0x15,%ecx - 43d0d5: 0f 84 e9 01 00 00 je 43d2c4 <__memcmp_ssse3+0x1594> - 43d0db: 83 f9 16 cmp $0x16,%ecx - 43d0de: 0f 84 90 02 00 00 je 43d374 <__memcmp_ssse3+0x1644> - 43d0e4: e9 37 03 00 00 jmpq 43d420 <__memcmp_ssse3+0x16f0> - 43d0e9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43d0f0: 83 f9 20 cmp $0x20,%ecx - 43d0f3: 73 4b jae 43d140 <__memcmp_ssse3+0x1410> - 43d0f5: 83 f9 18 cmp $0x18,%ecx - 43d0f8: 0f 84 18 01 00 00 je 43d216 <__memcmp_ssse3+0x14e6> - 43d0fe: 83 f9 19 cmp $0x19,%ecx - 43d101: 0f 84 af 01 00 00 je 43d2b6 <__memcmp_ssse3+0x1586> - 43d107: 83 f9 1a cmp $0x1a,%ecx - 43d10a: 0f 84 56 02 00 00 je 43d366 <__memcmp_ssse3+0x1636> - 43d110: 83 f9 1b cmp $0x1b,%ecx - 43d113: 0f 84 fd 02 00 00 je 43d416 <__memcmp_ssse3+0x16e6> - 43d119: 83 f9 1c cmp $0x1c,%ecx - 43d11c: 0f 84 e6 00 00 00 je 43d208 <__memcmp_ssse3+0x14d8> - 43d122: 83 f9 1d cmp $0x1d,%ecx - 43d125: 0f 84 7d 01 00 00 je 43d2a8 <__memcmp_ssse3+0x1578> - 43d12b: 83 f9 1e cmp $0x1e,%ecx - 43d12e: 0f 84 24 02 00 00 je 43d358 <__memcmp_ssse3+0x1628> - 43d134: e9 d3 02 00 00 jmpq 43d40c <__memcmp_ssse3+0x16dc> - 43d139: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43d140: 83 f9 28 cmp $0x28,%ecx - 43d143: 73 4b jae 43d190 <__memcmp_ssse3+0x1460> - 43d145: 83 f9 20 cmp $0x20,%ecx - 43d148: 0f 84 ac 00 00 00 je 43d1fa <__memcmp_ssse3+0x14ca> - 43d14e: 83 f9 21 cmp $0x21,%ecx - 43d151: 0f 84 43 01 00 00 je 43d29a <__memcmp_ssse3+0x156a> - 43d157: 83 f9 22 cmp $0x22,%ecx - 43d15a: 0f 84 ea 01 00 00 je 43d34a <__memcmp_ssse3+0x161a> - 43d160: 83 f9 23 cmp $0x23,%ecx - 43d163: 0f 84 99 02 00 00 je 43d402 <__memcmp_ssse3+0x16d2> - 43d169: 83 f9 24 cmp $0x24,%ecx - 43d16c: 74 7e je 43d1ec <__memcmp_ssse3+0x14bc> - 43d16e: 83 f9 25 cmp $0x25,%ecx - 43d171: 0f 84 15 01 00 00 je 43d28c <__memcmp_ssse3+0x155c> - 43d177: 83 f9 26 cmp $0x26,%ecx - 43d17a: 0f 84 bc 01 00 00 je 43d33c <__memcmp_ssse3+0x160c> - 43d180: e9 73 02 00 00 jmpq 43d3f8 <__memcmp_ssse3+0x16c8> - 43d185: 90 nop - 43d186: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43d18d: 00 00 00 - 43d190: 83 f9 28 cmp $0x28,%ecx - 43d193: 74 49 je 43d1de <__memcmp_ssse3+0x14ae> - 43d195: 83 f9 29 cmp $0x29,%ecx - 43d198: 0f 84 e0 00 00 00 je 43d27e <__memcmp_ssse3+0x154e> - 43d19e: 83 f9 2a cmp $0x2a,%ecx - 43d1a1: 0f 84 87 01 00 00 je 43d32e <__memcmp_ssse3+0x15fe> - 43d1a7: 83 f9 2b cmp $0x2b,%ecx - 43d1aa: 0f 84 3e 02 00 00 je 43d3ee <__memcmp_ssse3+0x16be> - 43d1b0: 83 f9 2c cmp $0x2c,%ecx - 43d1b3: 74 1b je 43d1d0 <__memcmp_ssse3+0x14a0> - 43d1b5: 83 f9 2d cmp $0x2d,%ecx - 43d1b8: 0f 84 b2 00 00 00 je 43d270 <__memcmp_ssse3+0x1540> - 43d1be: 83 f9 2e cmp $0x2e,%ecx - 43d1c1: 0f 84 59 01 00 00 je 43d320 <__memcmp_ssse3+0x15f0> - 43d1c7: e9 14 02 00 00 jmpq 43d3e0 <__memcmp_ssse3+0x16b0> - 43d1cc: 0f 1f 40 00 nopl 0x0(%rax) - 43d1d0: 8b 47 d4 mov -0x2c(%rdi),%eax - 43d1d3: 8b 4e d4 mov -0x2c(%rsi),%ecx - 43d1d6: 39 c8 cmp %ecx,%eax - 43d1d8: 0f 85 92 02 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d1de: 8b 47 d8 mov -0x28(%rdi),%eax - 43d1e1: 8b 4e d8 mov -0x28(%rsi),%ecx - 43d1e4: 39 c8 cmp %ecx,%eax - 43d1e6: 0f 85 84 02 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d1ec: 8b 47 dc mov -0x24(%rdi),%eax - 43d1ef: 8b 4e dc mov -0x24(%rsi),%ecx - 43d1f2: 39 c8 cmp %ecx,%eax - 43d1f4: 0f 85 76 02 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d1fa: 8b 47 e0 mov -0x20(%rdi),%eax - 43d1fd: 8b 4e e0 mov -0x20(%rsi),%ecx - 43d200: 39 c8 cmp %ecx,%eax - 43d202: 0f 85 68 02 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d208: 8b 47 e4 mov -0x1c(%rdi),%eax - 43d20b: 8b 4e e4 mov -0x1c(%rsi),%ecx - 43d20e: 39 c8 cmp %ecx,%eax - 43d210: 0f 85 5a 02 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d216: 8b 47 e8 mov -0x18(%rdi),%eax - 43d219: 8b 4e e8 mov -0x18(%rsi),%ecx - 43d21c: 39 c8 cmp %ecx,%eax - 43d21e: 0f 85 4c 02 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d224: 8b 47 ec mov -0x14(%rdi),%eax - 43d227: 8b 4e ec mov -0x14(%rsi),%ecx - 43d22a: 39 c8 cmp %ecx,%eax - 43d22c: 0f 85 3e 02 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d232: 8b 47 f0 mov -0x10(%rdi),%eax - 43d235: 8b 4e f0 mov -0x10(%rsi),%ecx - 43d238: 39 c8 cmp %ecx,%eax - 43d23a: 0f 85 30 02 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d240: 8b 47 f4 mov -0xc(%rdi),%eax - 43d243: 8b 4e f4 mov -0xc(%rsi),%ecx - 43d246: 39 c8 cmp %ecx,%eax - 43d248: 0f 85 22 02 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d24e: 8b 47 f8 mov -0x8(%rdi),%eax - 43d251: 8b 4e f8 mov -0x8(%rsi),%ecx - 43d254: 39 c8 cmp %ecx,%eax - 43d256: 0f 85 14 02 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d25c: 8b 47 fc mov -0x4(%rdi),%eax - 43d25f: 8b 4e fc mov -0x4(%rsi),%ecx - 43d262: 39 c8 cmp %ecx,%eax - 43d264: 0f 85 06 02 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d26a: 31 c0 xor %eax,%eax - 43d26c: c3 retq - 43d26d: 0f 1f 00 nopl (%rax) - 43d270: 8b 47 d3 mov -0x2d(%rdi),%eax - 43d273: 8b 4e d3 mov -0x2d(%rsi),%ecx - 43d276: 39 c8 cmp %ecx,%eax - 43d278: 0f 85 f2 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d27e: 8b 47 d7 mov -0x29(%rdi),%eax - 43d281: 8b 4e d7 mov -0x29(%rsi),%ecx - 43d284: 39 c8 cmp %ecx,%eax - 43d286: 0f 85 e4 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d28c: 8b 47 db mov -0x25(%rdi),%eax - 43d28f: 8b 4e db mov -0x25(%rsi),%ecx - 43d292: 39 c8 cmp %ecx,%eax - 43d294: 0f 85 d6 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d29a: 8b 47 df mov -0x21(%rdi),%eax - 43d29d: 8b 4e df mov -0x21(%rsi),%ecx - 43d2a0: 39 c8 cmp %ecx,%eax - 43d2a2: 0f 85 c8 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d2a8: 8b 47 e3 mov -0x1d(%rdi),%eax - 43d2ab: 8b 4e e3 mov -0x1d(%rsi),%ecx - 43d2ae: 39 c8 cmp %ecx,%eax - 43d2b0: 0f 85 ba 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d2b6: 8b 47 e7 mov -0x19(%rdi),%eax - 43d2b9: 8b 4e e7 mov -0x19(%rsi),%ecx - 43d2bc: 39 c8 cmp %ecx,%eax - 43d2be: 0f 85 ac 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d2c4: 8b 47 eb mov -0x15(%rdi),%eax - 43d2c7: 8b 4e eb mov -0x15(%rsi),%ecx - 43d2ca: 39 c8 cmp %ecx,%eax - 43d2cc: 0f 85 9e 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d2d2: 8b 47 ef mov -0x11(%rdi),%eax - 43d2d5: 8b 4e ef mov -0x11(%rsi),%ecx - 43d2d8: 39 c8 cmp %ecx,%eax - 43d2da: 0f 85 90 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d2e0: 8b 47 f3 mov -0xd(%rdi),%eax - 43d2e3: 8b 4e f3 mov -0xd(%rsi),%ecx - 43d2e6: 39 c8 cmp %ecx,%eax - 43d2e8: 0f 85 82 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d2ee: 8b 47 f7 mov -0x9(%rdi),%eax - 43d2f1: 8b 4e f7 mov -0x9(%rsi),%ecx - 43d2f4: 39 c8 cmp %ecx,%eax - 43d2f6: 0f 85 74 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d2fc: 8b 47 fb mov -0x5(%rdi),%eax - 43d2ff: 8b 4e fb mov -0x5(%rsi),%ecx - 43d302: 39 c8 cmp %ecx,%eax - 43d304: 0f 85 66 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d30a: 0f b6 47 ff movzbl -0x1(%rdi),%eax - 43d30e: 3a 46 ff cmp -0x1(%rsi),%al - 43d311: 0f 85 6e 01 00 00 jne 43d485 <__memcmp_ssse3+0x1755> - 43d317: 31 c0 xor %eax,%eax - 43d319: c3 retq - 43d31a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43d320: 8b 47 d2 mov -0x2e(%rdi),%eax - 43d323: 8b 4e d2 mov -0x2e(%rsi),%ecx - 43d326: 39 c8 cmp %ecx,%eax - 43d328: 0f 85 42 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d32e: 8b 47 d6 mov -0x2a(%rdi),%eax - 43d331: 8b 4e d6 mov -0x2a(%rsi),%ecx - 43d334: 39 c8 cmp %ecx,%eax - 43d336: 0f 85 34 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d33c: 8b 47 da mov -0x26(%rdi),%eax - 43d33f: 8b 4e da mov -0x26(%rsi),%ecx - 43d342: 39 c8 cmp %ecx,%eax - 43d344: 0f 85 26 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d34a: 8b 47 de mov -0x22(%rdi),%eax - 43d34d: 8b 4e de mov -0x22(%rsi),%ecx - 43d350: 39 c8 cmp %ecx,%eax - 43d352: 0f 85 18 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d358: 8b 47 e2 mov -0x1e(%rdi),%eax - 43d35b: 8b 4e e2 mov -0x1e(%rsi),%ecx - 43d35e: 39 c8 cmp %ecx,%eax - 43d360: 0f 85 0a 01 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d366: 8b 47 e6 mov -0x1a(%rdi),%eax - 43d369: 8b 4e e6 mov -0x1a(%rsi),%ecx - 43d36c: 39 c8 cmp %ecx,%eax - 43d36e: 0f 85 fc 00 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d374: 8b 47 ea mov -0x16(%rdi),%eax - 43d377: 8b 4e ea mov -0x16(%rsi),%ecx - 43d37a: 39 c8 cmp %ecx,%eax - 43d37c: 0f 85 ee 00 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d382: 8b 47 ee mov -0x12(%rdi),%eax - 43d385: 8b 4e ee mov -0x12(%rsi),%ecx - 43d388: 39 c8 cmp %ecx,%eax - 43d38a: 0f 85 e0 00 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d390: 8b 47 f2 mov -0xe(%rdi),%eax - 43d393: 8b 4e f2 mov -0xe(%rsi),%ecx - 43d396: 39 c8 cmp %ecx,%eax - 43d398: 0f 85 d2 00 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d39e: 8b 47 f6 mov -0xa(%rdi),%eax - 43d3a1: 8b 4e f6 mov -0xa(%rsi),%ecx - 43d3a4: 39 c8 cmp %ecx,%eax - 43d3a6: 0f 85 c4 00 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d3ac: 8b 47 fa mov -0x6(%rdi),%eax - 43d3af: 8b 4e fa mov -0x6(%rsi),%ecx - 43d3b2: 39 c8 cmp %ecx,%eax - 43d3b4: 0f 85 b6 00 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d3ba: 0f b7 47 fe movzwl -0x2(%rdi),%eax - 43d3be: 0f b7 4e fe movzwl -0x2(%rsi),%ecx - 43d3c2: 38 c8 cmp %cl,%al - 43d3c4: 0f 85 bb 00 00 00 jne 43d485 <__memcmp_ssse3+0x1755> - 43d3ca: 39 c8 cmp %ecx,%eax - 43d3cc: 0f 85 b3 00 00 00 jne 43d485 <__memcmp_ssse3+0x1755> - 43d3d2: 31 c0 xor %eax,%eax - 43d3d4: c3 retq - 43d3d5: 90 nop - 43d3d6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43d3dd: 00 00 00 - 43d3e0: 8b 47 d1 mov -0x2f(%rdi),%eax - 43d3e3: 8b 4e d1 mov -0x2f(%rsi),%ecx - 43d3e6: 39 c8 cmp %ecx,%eax - 43d3e8: 0f 85 82 00 00 00 jne 43d470 <__memcmp_ssse3+0x1740> - 43d3ee: 8b 47 d5 mov -0x2b(%rdi),%eax - 43d3f1: 8b 4e d5 mov -0x2b(%rsi),%ecx - 43d3f4: 39 c8 cmp %ecx,%eax - 43d3f6: 75 78 jne 43d470 <__memcmp_ssse3+0x1740> - 43d3f8: 8b 47 d9 mov -0x27(%rdi),%eax - 43d3fb: 8b 4e d9 mov -0x27(%rsi),%ecx - 43d3fe: 39 c8 cmp %ecx,%eax - 43d400: 75 6e jne 43d470 <__memcmp_ssse3+0x1740> - 43d402: 8b 47 dd mov -0x23(%rdi),%eax - 43d405: 8b 4e dd mov -0x23(%rsi),%ecx - 43d408: 39 c8 cmp %ecx,%eax - 43d40a: 75 64 jne 43d470 <__memcmp_ssse3+0x1740> - 43d40c: 8b 47 e1 mov -0x1f(%rdi),%eax - 43d40f: 8b 4e e1 mov -0x1f(%rsi),%ecx - 43d412: 39 c8 cmp %ecx,%eax - 43d414: 75 5a jne 43d470 <__memcmp_ssse3+0x1740> - 43d416: 8b 47 e5 mov -0x1b(%rdi),%eax - 43d419: 8b 4e e5 mov -0x1b(%rsi),%ecx - 43d41c: 39 c8 cmp %ecx,%eax - 43d41e: 75 50 jne 43d470 <__memcmp_ssse3+0x1740> - 43d420: 8b 47 e9 mov -0x17(%rdi),%eax - 43d423: 8b 4e e9 mov -0x17(%rsi),%ecx - 43d426: 39 c8 cmp %ecx,%eax - 43d428: 75 46 jne 43d470 <__memcmp_ssse3+0x1740> - 43d42a: 8b 47 ed mov -0x13(%rdi),%eax - 43d42d: 8b 4e ed mov -0x13(%rsi),%ecx - 43d430: 39 c8 cmp %ecx,%eax - 43d432: 75 3c jne 43d470 <__memcmp_ssse3+0x1740> - 43d434: 8b 47 f1 mov -0xf(%rdi),%eax - 43d437: 8b 4e f1 mov -0xf(%rsi),%ecx - 43d43a: 39 c8 cmp %ecx,%eax - 43d43c: 75 32 jne 43d470 <__memcmp_ssse3+0x1740> - 43d43e: 8b 47 f5 mov -0xb(%rdi),%eax - 43d441: 8b 4e f5 mov -0xb(%rsi),%ecx - 43d444: 39 c8 cmp %ecx,%eax - 43d446: 75 28 jne 43d470 <__memcmp_ssse3+0x1740> - 43d448: 8b 47 f9 mov -0x7(%rdi),%eax - 43d44b: 8b 4e f9 mov -0x7(%rsi),%ecx - 43d44e: 39 c8 cmp %ecx,%eax - 43d450: 75 1e jne 43d470 <__memcmp_ssse3+0x1740> - 43d452: 0f b7 47 fd movzwl -0x3(%rdi),%eax - 43d456: 0f b7 4e fd movzwl -0x3(%rsi),%ecx - 43d45a: 38 c8 cmp %cl,%al - 43d45c: 75 27 jne 43d485 <__memcmp_ssse3+0x1755> - 43d45e: 39 c8 cmp %ecx,%eax - 43d460: 75 23 jne 43d485 <__memcmp_ssse3+0x1755> - 43d462: 0f b6 47 ff movzbl -0x1(%rdi),%eax - 43d466: 3a 46 ff cmp -0x1(%rsi),%al - 43d469: 75 1a jne 43d485 <__memcmp_ssse3+0x1755> - 43d46b: 31 c0 xor %eax,%eax - 43d46d: c3 retq - 43d46e: 66 90 xchg %ax,%ax - 43d470: 38 c8 cmp %cl,%al - 43d472: 75 11 jne 43d485 <__memcmp_ssse3+0x1755> - 43d474: 66 39 c8 cmp %cx,%ax - 43d477: 75 0c jne 43d485 <__memcmp_ssse3+0x1755> - 43d479: c1 e8 10 shr $0x10,%eax - 43d47c: c1 e9 10 shr $0x10,%ecx - 43d47f: 38 c8 cmp %cl,%al - 43d481: 75 02 jne 43d485 <__memcmp_ssse3+0x1755> - 43d483: 39 c8 cmp %ecx,%eax - 43d485: 19 c0 sbb %eax,%eax - 43d487: 83 d8 ff sbb $0xffffffff,%eax - 43d48a: c3 retq - 43d48b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43d490: 31 c0 xor %eax,%eax - 43d492: c3 retq - 43d493: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43d49a: 00 00 00 - 43d49d: 0f 1f 00 nopl (%rax) - -000000000043d4a0 <__strstr_sse2_unaligned>: - 43d4a0: 0f b6 06 movzbl (%rsi),%eax - 43d4a3: 84 c0 test %al,%al - 43d4a5: 0f 84 9c 01 00 00 je 43d647 <__strstr_sse2_unaligned+0x1a7> - 43d4ab: 0f b6 56 01 movzbl 0x1(%rsi),%edx - 43d4af: 84 d2 test %dl,%dl - 43d4b1: 0f 84 b9 00 00 00 je 43d570 <__strstr_sse2_unaligned+0xd0> - 43d4b7: 66 0f 6e c8 movd %eax,%xmm1 - 43d4bb: 66 0f 6e d2 movd %edx,%xmm2 - 43d4bf: 48 89 f8 mov %rdi,%rax - 43d4c2: 25 ff 0f 00 00 and $0xfff,%eax - 43d4c7: 66 0f 60 c9 punpcklbw %xmm1,%xmm1 - 43d4cb: 48 3d bf 0f 00 00 cmp $0xfbf,%rax - 43d4d1: 66 0f 60 d2 punpcklbw %xmm2,%xmm2 - 43d4d5: 66 0f 61 c9 punpcklwd %xmm1,%xmm1 - 43d4d9: 66 0f 61 d2 punpcklwd %xmm2,%xmm2 - 43d4dd: 66 0f 70 c9 00 pshufd $0x0,%xmm1,%xmm1 - 43d4e2: 66 0f 70 d2 00 pshufd $0x0,%xmm2,%xmm2 - 43d4e7: 0f 87 03 03 00 00 ja 43d7f0 <__strstr_sse2_unaligned+0x350> - 43d4ed: f3 0f 6f 1f movdqu (%rdi),%xmm3 - 43d4f1: 66 0f ef ed pxor %xmm5,%xmm5 - 43d4f5: f3 0f 6f 67 01 movdqu 0x1(%rdi),%xmm4 - 43d4fa: 66 0f 6f f3 movdqa %xmm3,%xmm6 - 43d4fe: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 - 43d502: 66 0f 74 e2 pcmpeqb %xmm2,%xmm4 - 43d506: f3 0f 6f 47 10 movdqu 0x10(%rdi),%xmm0 - 43d50b: 66 0f 74 f5 pcmpeqb %xmm5,%xmm6 - 43d50f: 66 0f da dc pminub %xmm4,%xmm3 - 43d513: 66 0f 6f e3 movdqa %xmm3,%xmm4 - 43d517: f3 0f 6f 5f 11 movdqu 0x11(%rdi),%xmm3 - 43d51c: 66 0f 74 e8 pcmpeqb %xmm0,%xmm5 - 43d520: 66 0f 74 da pcmpeqb %xmm2,%xmm3 - 43d524: 66 0f eb e6 por %xmm6,%xmm4 - 43d528: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 43d52c: 66 0f da c3 pminub %xmm3,%xmm0 - 43d530: 66 0f eb c5 por %xmm5,%xmm0 - 43d534: 66 44 0f d7 c4 pmovmskb %xmm4,%r8d - 43d539: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43d53d: 48 c1 e0 10 shl $0x10,%rax - 43d541: 49 09 c0 or %rax,%r8 - 43d544: 74 6a je 43d5b0 <__strstr_sse2_unaligned+0x110> - 43d546: 49 0f bc c0 bsf %r8,%rax - 43d54a: 48 01 f8 add %rdi,%rax - 43d54d: 80 38 00 cmpb $0x0,(%rax) - 43d550: 74 42 je 43d594 <__strstr_sse2_unaligned+0xf4> - 43d552: 0f b6 56 02 movzbl 0x2(%rsi),%edx - 43d556: 84 d2 test %dl,%dl - 43d558: 74 39 je 43d593 <__strstr_sse2_unaligned+0xf3> - 43d55a: 3a 50 02 cmp 0x2(%rax),%dl - 43d55d: 75 41 jne 43d5a0 <__strstr_sse2_unaligned+0x100> - 43d55f: 31 d2 xor %edx,%edx - 43d561: eb 27 jmp 43d58a <__strstr_sse2_unaligned+0xea> - 43d563: 0f 1f 00 nopl (%rax) - 43d566: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43d56d: 00 00 00 - 43d570: 0f b6 f0 movzbl %al,%esi - 43d573: e9 38 3b fe ff jmpq 4210b0 <__GI_strchr> - 43d578: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 43d57f: 00 - 43d580: 48 83 c2 01 add $0x1,%rdx - 43d584: 3a 4c 10 02 cmp 0x2(%rax,%rdx,1),%cl - 43d588: 75 16 jne 43d5a0 <__strstr_sse2_unaligned+0x100> - 43d58a: 0f b6 4c 16 03 movzbl 0x3(%rsi,%rdx,1),%ecx - 43d58f: 84 c9 test %cl,%cl - 43d591: 75 ed jne 43d580 <__strstr_sse2_unaligned+0xe0> - 43d593: c3 retq - 43d594: 31 c0 xor %eax,%eax - 43d596: c3 retq - 43d597: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 43d59e: 00 00 - 43d5a0: 49 8d 40 ff lea -0x1(%r8),%rax - 43d5a4: 49 21 c0 and %rax,%r8 - 43d5a7: 75 9d jne 43d546 <__strstr_sse2_unaligned+0xa6> - 43d5a9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43d5b0: f3 0f 6f 5f 20 movdqu 0x20(%rdi),%xmm3 - 43d5b5: 66 0f ef ed pxor %xmm5,%xmm5 - 43d5b9: f3 0f 6f 67 21 movdqu 0x21(%rdi),%xmm4 - 43d5be: 66 0f 6f f3 movdqa %xmm3,%xmm6 - 43d5c2: 66 0f 74 d9 pcmpeqb %xmm1,%xmm3 - 43d5c6: 66 0f 74 e2 pcmpeqb %xmm2,%xmm4 - 43d5ca: f3 0f 6f 47 30 movdqu 0x30(%rdi),%xmm0 - 43d5cf: 66 0f 74 f5 pcmpeqb %xmm5,%xmm6 - 43d5d3: 66 0f da dc pminub %xmm4,%xmm3 - 43d5d7: 66 0f 6f e3 movdqa %xmm3,%xmm4 - 43d5db: f3 0f 6f 5f 31 movdqu 0x31(%rdi),%xmm3 - 43d5e0: 66 0f 74 e8 pcmpeqb %xmm0,%xmm5 - 43d5e4: 66 0f 74 da pcmpeqb %xmm2,%xmm3 - 43d5e8: 66 0f eb e6 por %xmm6,%xmm4 - 43d5ec: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 43d5f0: 66 0f da c3 pminub %xmm3,%xmm0 - 43d5f4: 66 0f eb c5 por %xmm5,%xmm0 - 43d5f8: 66 0f d7 c4 pmovmskb %xmm4,%eax - 43d5fc: 48 c1 e0 20 shl $0x20,%rax - 43d600: 66 44 0f d7 c0 pmovmskb %xmm0,%r8d - 43d605: 49 c1 e0 30 shl $0x30,%r8 - 43d609: 49 09 c0 or %rax,%r8 - 43d60c: 74 4b je 43d659 <__strstr_sse2_unaligned+0x1b9> - 43d60e: 49 0f bc c0 bsf %r8,%rax - 43d612: 48 01 f8 add %rdi,%rax - 43d615: 80 38 00 cmpb $0x0,(%rax) - 43d618: 74 2a je 43d644 <__strstr_sse2_unaligned+0x1a4> - 43d61a: 0f b6 56 02 movzbl 0x2(%rsi),%edx - 43d61e: 84 d2 test %dl,%dl - 43d620: 74 21 je 43d643 <__strstr_sse2_unaligned+0x1a3> - 43d622: 3a 50 02 cmp 0x2(%rax),%dl - 43d625: 75 29 jne 43d650 <__strstr_sse2_unaligned+0x1b0> - 43d627: 31 d2 xor %edx,%edx - 43d629: eb 0f jmp 43d63a <__strstr_sse2_unaligned+0x19a> - 43d62b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43d630: 48 83 c2 01 add $0x1,%rdx - 43d634: 3a 4c 10 02 cmp 0x2(%rax,%rdx,1),%cl - 43d638: 75 16 jne 43d650 <__strstr_sse2_unaligned+0x1b0> - 43d63a: 0f b6 4c 16 03 movzbl 0x3(%rsi,%rdx,1),%ecx - 43d63f: 84 c9 test %cl,%cl - 43d641: 75 ed jne 43d630 <__strstr_sse2_unaligned+0x190> - 43d643: c3 retq - 43d644: 31 c0 xor %eax,%eax - 43d646: c3 retq - 43d647: 48 89 f8 mov %rdi,%rax - 43d64a: c3 retq - 43d64b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43d650: 49 8d 40 ff lea -0x1(%r8),%rax - 43d654: 49 21 c0 and %rax,%r8 - 43d657: 75 b5 jne 43d60e <__strstr_sse2_unaligned+0x16e> - 43d659: 49 c7 c3 00 fe ff ff mov $0xfffffffffffffe00,%r11 - 43d660: 49 89 f9 mov %rdi,%r9 - 43d663: 66 0f ef ff pxor %xmm7,%xmm7 - 43d667: 48 83 e7 c0 and $0xffffffffffffffc0,%rdi - 43d66b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43d670: 66 0f 6f 5f 40 movdqa 0x40(%rdi),%xmm3 - 43d675: f3 0f 6f 77 3f movdqu 0x3f(%rdi),%xmm6 - 43d67a: 66 0f 6f c3 movdqa %xmm3,%xmm0 - 43d67e: 66 0f ef da pxor %xmm2,%xmm3 - 43d682: 66 0f ef f1 pxor %xmm1,%xmm6 - 43d686: 66 44 0f 6f 57 50 movdqa 0x50(%rdi),%xmm10 - 43d68c: 66 0f eb f3 por %xmm3,%xmm6 - 43d690: 66 41 0f da c2 pminub %xmm10,%xmm0 - 43d695: f3 0f 6f 5f 4f movdqu 0x4f(%rdi),%xmm3 - 43d69a: 66 44 0f ef d2 pxor %xmm2,%xmm10 - 43d69f: 66 0f ef d9 pxor %xmm1,%xmm3 - 43d6a3: 66 44 0f 6f 4f 60 movdqa 0x60(%rdi),%xmm9 - 43d6a9: 66 41 0f eb da por %xmm10,%xmm3 - 43d6ae: 66 41 0f da c1 pminub %xmm9,%xmm0 - 43d6b3: 66 44 0f ef ca pxor %xmm2,%xmm9 - 43d6b8: 66 44 0f 6f 47 70 movdqa 0x70(%rdi),%xmm8 - 43d6be: 48 83 c7 40 add $0x40,%rdi - 43d6c2: 66 0f da de pminub %xmm6,%xmm3 - 43d6c6: f3 0f 6f 67 1f movdqu 0x1f(%rdi),%xmm4 - 43d6cb: 66 41 0f da c0 pminub %xmm8,%xmm0 - 43d6d0: 66 44 0f ef c2 pxor %xmm2,%xmm8 - 43d6d5: 66 0f ef e1 pxor %xmm1,%xmm4 - 43d6d9: 66 41 0f eb e1 por %xmm9,%xmm4 - 43d6de: 66 0f da dc pminub %xmm4,%xmm3 - 43d6e2: f3 0f 6f 6f 2f movdqu 0x2f(%rdi),%xmm5 - 43d6e7: 66 0f ef e9 pxor %xmm1,%xmm5 - 43d6eb: 66 41 0f eb e8 por %xmm8,%xmm5 - 43d6f0: 66 0f da dd pminub %xmm5,%xmm3 - 43d6f4: 66 0f da c3 pminub %xmm3,%xmm0 - 43d6f8: 66 0f 74 c7 pcmpeqb %xmm7,%xmm0 - 43d6fc: 66 0f d7 c0 pmovmskb %xmm0,%eax - 43d700: 85 c0 test %eax,%eax - 43d702: 0f 84 68 ff ff ff je 43d670 <__strstr_sse2_unaligned+0x1d0> - 43d708: 66 0f da 37 pminub (%rdi),%xmm6 - 43d70c: 66 0f da 67 20 pminub 0x20(%rdi),%xmm4 - 43d711: 66 0f da 6f 30 pminub 0x30(%rdi),%xmm5 - 43d716: 66 0f 74 f7 pcmpeqb %xmm7,%xmm6 - 43d71a: 66 0f 74 ef pcmpeqb %xmm7,%xmm5 - 43d71e: 66 0f d7 d6 pmovmskb %xmm6,%edx - 43d722: 66 44 0f 6f 47 10 movdqa 0x10(%rdi),%xmm8 - 43d728: 66 0f 74 e7 pcmpeqb %xmm7,%xmm4 - 43d72c: f3 0f 6f 47 0f movdqu 0xf(%rdi),%xmm0 - 43d731: 66 44 0f d7 c5 pmovmskb %xmm5,%r8d - 43d736: 66 41 0f 6f d8 movdqa %xmm8,%xmm3 - 43d73b: 66 0f d7 cc pmovmskb %xmm4,%ecx - 43d73f: 66 0f 74 c1 pcmpeqb %xmm1,%xmm0 - 43d743: 66 0f 74 da pcmpeqb %xmm2,%xmm3 - 43d747: 48 c1 e1 20 shl $0x20,%rcx - 43d74b: 66 44 0f 74 c7 pcmpeqb %xmm7,%xmm8 - 43d750: 49 c1 e0 30 shl $0x30,%r8 - 43d754: 66 0f da d8 pminub %xmm0,%xmm3 - 43d758: 48 09 ca or %rcx,%rdx - 43d75b: 66 44 0f eb c3 por %xmm3,%xmm8 - 43d760: 49 09 d0 or %rdx,%r8 - 43d763: 66 41 0f d7 c0 pmovmskb %xmm8,%eax - 43d768: 48 c1 e0 10 shl $0x10,%rax - 43d76c: 49 09 c0 or %rax,%r8 - 43d76f: 0f 84 fb fe ff ff je 43d670 <__strstr_sse2_unaligned+0x1d0> - 43d775: 49 0f bc c8 bsf %r8,%rcx - 43d779: 48 01 f9 add %rdi,%rcx - 43d77c: 80 39 00 cmpb $0x0,(%rcx) - 43d77f: 0f 84 ab 01 00 00 je 43d930 <__strstr_sse2_unaligned+0x490> - 43d785: 31 c0 xor %eax,%eax - 43d787: 0f b6 56 02 movzbl 0x2(%rsi),%edx - 43d78b: 84 d2 test %dl,%dl - 43d78d: 74 24 je 43d7b3 <__strstr_sse2_unaligned+0x313> - 43d78f: 3a 51 01 cmp 0x1(%rcx),%dl - 43d792: 75 2c jne 43d7c0 <__strstr_sse2_unaligned+0x320> - 43d794: eb 14 jmp 43d7aa <__strstr_sse2_unaligned+0x30a> - 43d796: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43d79d: 00 00 00 - 43d7a0: 48 83 c0 01 add $0x1,%rax - 43d7a4: 3a 54 01 01 cmp 0x1(%rcx,%rax,1),%dl - 43d7a8: 75 16 jne 43d7c0 <__strstr_sse2_unaligned+0x320> - 43d7aa: 0f b6 54 06 03 movzbl 0x3(%rsi,%rax,1),%edx - 43d7af: 84 d2 test %dl,%dl - 43d7b1: 75 ed jne 43d7a0 <__strstr_sse2_unaligned+0x300> - 43d7b3: 48 8d 41 ff lea -0x1(%rcx),%rax - 43d7b7: c3 retq - 43d7b8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 43d7bf: 00 - 43d7c0: 49 01 c3 add %rax,%r11 - 43d7c3: 48 89 f8 mov %rdi,%rax - 43d7c6: 4c 29 c8 sub %r9,%rax - 43d7c9: 4c 39 d8 cmp %r11,%rax - 43d7cc: 7c 12 jl 43d7e0 <__strstr_sse2_unaligned+0x340> - 43d7ce: 49 8d 40 ff lea -0x1(%r8),%rax - 43d7d2: 49 21 c0 and %rax,%r8 - 43d7d5: 75 9e jne 43d775 <__strstr_sse2_unaligned+0x2d5> - 43d7d7: e9 94 fe ff ff jmpq 43d670 <__strstr_sse2_unaligned+0x1d0> - 43d7dc: 0f 1f 40 00 nopl 0x0(%rax) - 43d7e0: 48 89 ff mov %rdi,%rdi - 43d7e3: e9 68 7d fe ff jmpq 425550 <__strstr_sse2> - 43d7e8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 43d7ef: 00 - 43d7f0: 48 89 f8 mov %rdi,%rax - 43d7f3: 66 0f ef c0 pxor %xmm0,%xmm0 - 43d7f7: 48 83 e0 c0 and $0xffffffffffffffc0,%rax - 43d7fb: 66 0f 6f 18 movdqa (%rax),%xmm3 - 43d7ff: f3 0f 6f 60 ff movdqu -0x1(%rax),%xmm4 - 43d804: 66 44 0f 6f c3 movdqa %xmm3,%xmm8 - 43d809: 66 0f 6f 68 10 movdqa 0x10(%rax),%xmm5 - 43d80e: 66 0f 74 e1 pcmpeqb %xmm1,%xmm4 - 43d812: 66 44 0f 74 c0 pcmpeqb %xmm0,%xmm8 - 43d817: 66 0f 74 da pcmpeqb %xmm2,%xmm3 - 43d81b: 66 0f 6f fd movdqa %xmm5,%xmm7 - 43d81f: 66 0f da dc pminub %xmm4,%xmm3 - 43d823: f3 0f 6f 60 0f movdqu 0xf(%rax),%xmm4 - 43d828: 66 0f 74 f8 pcmpeqb %xmm0,%xmm7 - 43d82c: 66 44 0f eb c3 por %xmm3,%xmm8 - 43d831: 66 0f 6f dd movdqa %xmm5,%xmm3 - 43d835: 66 0f 6f 68 20 movdqa 0x20(%rax),%xmm5 - 43d83a: 66 0f 74 e1 pcmpeqb %xmm1,%xmm4 - 43d83e: 66 0f 74 da pcmpeqb %xmm2,%xmm3 - 43d842: 66 0f 6f f5 movdqa %xmm5,%xmm6 - 43d846: 66 41 0f d7 c8 pmovmskb %xmm8,%ecx - 43d84b: 66 0f da dc pminub %xmm4,%xmm3 - 43d84f: f3 0f 6f 60 1f movdqu 0x1f(%rax),%xmm4 - 43d854: 66 0f eb fb por %xmm3,%xmm7 - 43d858: 66 0f 6f dd movdqa %xmm5,%xmm3 - 43d85c: 66 0f 74 f0 pcmpeqb %xmm0,%xmm6 - 43d860: 66 0f 6f 68 30 movdqa 0x30(%rax),%xmm5 - 43d865: 66 0f 74 e1 pcmpeqb %xmm1,%xmm4 - 43d869: 66 44 0f d7 c7 pmovmskb %xmm7,%r8d - 43d86e: 66 0f 74 da pcmpeqb %xmm2,%xmm3 - 43d872: 66 0f 74 c5 pcmpeqb %xmm5,%xmm0 - 43d876: 66 0f da dc pminub %xmm4,%xmm3 - 43d87a: f3 0f 6f 60 2f movdqu 0x2f(%rax),%xmm4 - 43d87f: 66 0f eb f3 por %xmm3,%xmm6 - 43d883: 66 0f 6f dd movdqa %xmm5,%xmm3 - 43d887: 49 c1 e0 10 shl $0x10,%r8 - 43d88b: 66 0f 74 e1 pcmpeqb %xmm1,%xmm4 - 43d88f: 66 0f 74 da pcmpeqb %xmm2,%xmm3 - 43d893: 66 44 0f d7 d6 pmovmskb %xmm6,%r10d - 43d898: 66 0f da dc pminub %xmm4,%xmm3 - 43d89c: 66 0f eb c3 por %xmm3,%xmm0 - 43d8a0: 49 c1 e2 20 shl $0x20,%r10 - 43d8a4: 4d 09 d0 or %r10,%r8 - 43d8a7: 49 09 c8 or %rcx,%r8 - 43d8aa: 89 f9 mov %edi,%ecx - 43d8ac: 66 0f d7 d0 pmovmskb %xmm0,%edx - 43d8b0: 29 c1 sub %eax,%ecx - 43d8b2: 48 c1 e2 30 shl $0x30,%rdx - 43d8b6: 49 09 d0 or %rdx,%r8 - 43d8b9: 49 d3 e8 shr %cl,%r8 - 43d8bc: 0f 84 97 fd ff ff je 43d659 <__strstr_sse2_unaligned+0x1b9> - 43d8c2: 49 0f bc c0 bsf %r8,%rax - 43d8c6: 48 01 f8 add %rdi,%rax - 43d8c9: 80 38 00 cmpb $0x0,(%rax) - 43d8cc: 74 62 je 43d930 <__strstr_sse2_unaligned+0x490> - 43d8ce: 48 39 c7 cmp %rax,%rdi - 43d8d1: 74 3d je 43d910 <__strstr_sse2_unaligned+0x470> - 43d8d3: 0f b6 56 02 movzbl 0x2(%rsi),%edx - 43d8d7: 84 d2 test %dl,%dl - 43d8d9: 74 28 je 43d903 <__strstr_sse2_unaligned+0x463> - 43d8db: 3a 50 01 cmp 0x1(%rax),%dl - 43d8de: 75 30 jne 43d910 <__strstr_sse2_unaligned+0x470> - 43d8e0: 31 d2 xor %edx,%edx - 43d8e2: eb 16 jmp 43d8fa <__strstr_sse2_unaligned+0x45a> - 43d8e4: 66 90 xchg %ax,%ax - 43d8e6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43d8ed: 00 00 00 - 43d8f0: 48 83 c2 01 add $0x1,%rdx - 43d8f4: 3a 4c 10 01 cmp 0x1(%rax,%rdx,1),%cl - 43d8f8: 75 16 jne 43d910 <__strstr_sse2_unaligned+0x470> - 43d8fa: 0f b6 4c 16 03 movzbl 0x3(%rsi,%rdx,1),%ecx - 43d8ff: 84 c9 test %cl,%cl - 43d901: 75 ed jne 43d8f0 <__strstr_sse2_unaligned+0x450> - 43d903: 48 83 e8 01 sub $0x1,%rax - 43d907: c3 retq - 43d908: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 43d90f: 00 - 43d910: 49 8d 40 ff lea -0x1(%r8),%rax - 43d914: 49 21 c0 and %rax,%r8 - 43d917: 75 a9 jne 43d8c2 <__strstr_sse2_unaligned+0x422> - 43d919: e9 3b fd ff ff jmpq 43d659 <__strstr_sse2_unaligned+0x1b9> - 43d91e: 66 90 xchg %ax,%ax - 43d920: f3 c3 repz retq - 43d922: 0f 1f 40 00 nopl 0x0(%rax) - 43d926: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43d92d: 00 00 00 - 43d930: 31 c0 xor %eax,%eax - 43d932: c3 retq - 43d933: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43d93a: 00 00 00 - 43d93d: 0f 1f 00 nopl (%rax) - -000000000043d940 <__memset_avx2>: - 43d940: c5 f9 ef c0 vpxor %xmm0,%xmm0,%xmm0 - 43d944: c5 f9 6e ce vmovd %esi,%xmm1 - 43d948: 48 8d 34 17 lea (%rdi,%rdx,1),%rsi - 43d94c: 48 89 f8 mov %rdi,%rax - 43d94f: c4 e2 71 00 c0 vpshufb %xmm0,%xmm1,%xmm0 - 43d954: 48 83 fa 10 cmp $0x10,%rdx - 43d958: 0f 82 c2 00 00 00 jb 43da20 <__memset_avx2+0xe0> - 43d95e: 48 81 fa 00 01 00 00 cmp $0x100,%rdx - 43d965: 0f 83 f5 00 00 00 jae 43da60 <__memset_avx2+0x120> - 43d96b: 80 fa 80 cmp $0x80,%dl - 43d96e: 72 50 jb 43d9c0 <__memset_avx2+0x80> - 43d970: c5 fa 7f 07 vmovdqu %xmm0,(%rdi) - 43d974: c5 fa 7f 47 10 vmovdqu %xmm0,0x10(%rdi) - 43d979: c5 fa 7f 47 20 vmovdqu %xmm0,0x20(%rdi) - 43d97e: c5 fa 7f 47 30 vmovdqu %xmm0,0x30(%rdi) - 43d983: c5 fa 7f 47 40 vmovdqu %xmm0,0x40(%rdi) - 43d988: c5 fa 7f 47 50 vmovdqu %xmm0,0x50(%rdi) - 43d98d: c5 fa 7f 47 60 vmovdqu %xmm0,0x60(%rdi) - 43d992: c5 fa 7f 47 70 vmovdqu %xmm0,0x70(%rdi) - 43d997: c5 fa 7f 46 80 vmovdqu %xmm0,-0x80(%rsi) - 43d99c: c5 fa 7f 46 90 vmovdqu %xmm0,-0x70(%rsi) - 43d9a1: c5 fa 7f 46 a0 vmovdqu %xmm0,-0x60(%rsi) - 43d9a6: c5 fa 7f 46 b0 vmovdqu %xmm0,-0x50(%rsi) - 43d9ab: c5 fa 7f 46 c0 vmovdqu %xmm0,-0x40(%rsi) - 43d9b0: c5 fa 7f 46 d0 vmovdqu %xmm0,-0x30(%rsi) - 43d9b5: c5 fa 7f 46 e0 vmovdqu %xmm0,-0x20(%rsi) - 43d9ba: c5 fa 7f 46 f0 vmovdqu %xmm0,-0x10(%rsi) - 43d9bf: c3 retq - 43d9c0: 80 fa 40 cmp $0x40,%dl - 43d9c3: 72 2b jb 43d9f0 <__memset_avx2+0xb0> - 43d9c5: c5 fa 7f 07 vmovdqu %xmm0,(%rdi) - 43d9c9: c5 fa 7f 47 10 vmovdqu %xmm0,0x10(%rdi) - 43d9ce: c5 fa 7f 47 20 vmovdqu %xmm0,0x20(%rdi) - 43d9d3: c5 fa 7f 47 30 vmovdqu %xmm0,0x30(%rdi) - 43d9d8: c5 fa 7f 46 c0 vmovdqu %xmm0,-0x40(%rsi) - 43d9dd: c5 fa 7f 46 d0 vmovdqu %xmm0,-0x30(%rsi) - 43d9e2: c5 fa 7f 46 e0 vmovdqu %xmm0,-0x20(%rsi) - 43d9e7: c5 fa 7f 46 f0 vmovdqu %xmm0,-0x10(%rsi) - 43d9ec: c3 retq - 43d9ed: 0f 1f 00 nopl (%rax) - 43d9f0: 80 fa 20 cmp $0x20,%dl - 43d9f3: 72 1b jb 43da10 <__memset_avx2+0xd0> - 43d9f5: c5 fa 7f 07 vmovdqu %xmm0,(%rdi) - 43d9f9: c5 fa 7f 47 10 vmovdqu %xmm0,0x10(%rdi) - 43d9fe: c5 fa 7f 46 e0 vmovdqu %xmm0,-0x20(%rsi) - 43da03: c5 fa 7f 46 f0 vmovdqu %xmm0,-0x10(%rsi) - 43da08: c3 retq - 43da09: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43da10: c5 fa 7f 07 vmovdqu %xmm0,(%rdi) - 43da14: c5 fa 7f 46 f0 vmovdqu %xmm0,-0x10(%rsi) - 43da19: c3 retq - 43da1a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43da20: 80 fa 08 cmp $0x8,%dl - 43da23: 72 0b jb 43da30 <__memset_avx2+0xf0> - 43da25: c5 f9 d6 07 vmovq %xmm0,(%rdi) - 43da29: c5 f9 d6 46 f8 vmovq %xmm0,-0x8(%rsi) - 43da2e: c3 retq - 43da2f: 90 nop - 43da30: c5 f9 7e c1 vmovd %xmm0,%ecx - 43da34: 80 fa 04 cmp $0x4,%dl - 43da37: 72 07 jb 43da40 <__memset_avx2+0x100> - 43da39: 89 0f mov %ecx,(%rdi) - 43da3b: 89 4e fc mov %ecx,-0x4(%rsi) - 43da3e: c3 retq - 43da3f: 90 nop - 43da40: 80 fa 02 cmp $0x2,%dl - 43da43: 72 0b jb 43da50 <__memset_avx2+0x110> - 43da45: 66 89 0f mov %cx,(%rdi) - 43da48: 66 89 4e fe mov %cx,-0x2(%rsi) - 43da4c: c3 retq - 43da4d: 0f 1f 00 nopl (%rax) - 43da50: 80 fa 01 cmp $0x1,%dl - 43da53: 72 02 jb 43da57 <__memset_avx2+0x117> - 43da55: 88 0f mov %cl,(%rdi) - 43da57: c3 retq - 43da58: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 43da5f: 00 - 43da60: c4 e3 7d 38 c0 01 vinserti128 $0x1,%xmm0,%ymm0,%ymm0 - 43da66: 48 83 e7 e0 and $0xffffffffffffffe0,%rdi - 43da6a: 48 83 c7 20 add $0x20,%rdi - 43da6e: c5 fe 7f 00 vmovdqu %ymm0,(%rax) - 43da72: 48 29 f8 sub %rdi,%rax - 43da75: 48 8d 4c 10 80 lea -0x80(%rax,%rdx,1),%rcx - 43da7a: 48 81 f9 00 10 00 00 cmp $0x1000,%rcx - 43da81: 77 3d ja 43dac0 <__memset_avx2+0x180> - 43da83: c5 fd 7f 07 vmovdqa %ymm0,(%rdi) - 43da87: c5 fd 7f 47 20 vmovdqa %ymm0,0x20(%rdi) - 43da8c: c5 fd 7f 47 40 vmovdqa %ymm0,0x40(%rdi) - 43da91: c5 fd 7f 47 60 vmovdqa %ymm0,0x60(%rdi) - 43da96: 48 83 ef 80 sub $0xffffffffffffff80,%rdi - 43da9a: 83 c1 80 add $0xffffff80,%ecx - 43da9d: 72 e4 jb 43da83 <__memset_avx2+0x143> - 43da9f: 48 89 f0 mov %rsi,%rax - 43daa2: c5 fe 7f 46 80 vmovdqu %ymm0,-0x80(%rsi) - 43daa7: c5 fe 7f 46 a0 vmovdqu %ymm0,-0x60(%rsi) - 43daac: c5 fe 7f 46 c0 vmovdqu %ymm0,-0x40(%rsi) - 43dab1: c5 fe 7f 46 e0 vmovdqu %ymm0,-0x20(%rsi) - 43dab6: 48 29 d0 sub %rdx,%rax - 43dab9: c5 f8 77 vzeroupper - 43dabc: c3 retq - 43dabd: 0f 1f 00 nopl (%rax) - 43dac0: 48 83 e9 80 sub $0xffffffffffffff80,%rcx - 43dac4: c5 f9 7e c0 vmovd %xmm0,%eax - 43dac8: f3 aa rep stos %al,%es:(%rdi) - 43daca: 48 89 f0 mov %rsi,%rax - 43dacd: 48 29 d0 sub %rdx,%rax - 43dad0: c5 f8 77 vzeroupper - 43dad3: c3 retq - 43dad4: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43dadb: 00 00 00 - 43dade: 66 90 xchg %ax,%ax - -000000000043dae0 <__memset_avx512_no_vzeroupper>: - 43dae0: c5 f9 ef c0 vpxor %xmm0,%xmm0,%xmm0 - 43dae4: c5 f9 6e ce vmovd %esi,%xmm1 - 43dae8: 48 8d 34 17 lea (%rdi,%rdx,1),%rsi - 43daec: 48 89 f8 mov %rdi,%rax - 43daef: c4 e2 71 00 c0 vpshufb %xmm0,%xmm1,%xmm0 - 43daf4: 48 83 fa 10 cmp $0x10,%rdx - 43daf8: 0f 82 a1 00 00 00 jb 43db9f <__memset_avx512_no_vzeroupper+0xbf> - 43dafe: 48 81 fa 00 02 00 00 cmp $0x200,%rdx - 43db05: 62 f2 7d 48 18 d0 vbroadcastss %xmm0,%zmm2 - 43db0b: 0f 87 c1 00 00 00 ja 43dbd2 <__memset_avx512_no_vzeroupper+0xf2> - 43db11: 48 81 fa 00 01 00 00 cmp $0x100,%rdx - 43db18: 72 38 jb 43db52 <__memset_avx512_no_vzeroupper+0x72> - 43db1a: 62 f1 7c 48 11 17 vmovups %zmm2,(%rdi) - 43db20: 62 f1 7c 48 11 57 01 vmovups %zmm2,0x40(%rdi) - 43db27: 62 f1 7c 48 11 57 02 vmovups %zmm2,0x80(%rdi) - 43db2e: 62 f1 7c 48 11 57 03 vmovups %zmm2,0xc0(%rdi) - 43db35: 62 f1 7c 48 11 56 fc vmovups %zmm2,-0x100(%rsi) - 43db3c: 62 f1 7c 48 11 56 fd vmovups %zmm2,-0xc0(%rsi) - 43db43: 62 f1 7c 48 11 56 fe vmovups %zmm2,-0x80(%rsi) - 43db4a: 62 f1 7c 48 11 56 ff vmovups %zmm2,-0x40(%rsi) - 43db51: c3 retq - 43db52: 80 fa 80 cmp $0x80,%dl - 43db55: 72 1c jb 43db73 <__memset_avx512_no_vzeroupper+0x93> - 43db57: 62 f1 7c 48 11 17 vmovups %zmm2,(%rdi) - 43db5d: 62 f1 7c 48 11 57 01 vmovups %zmm2,0x40(%rdi) - 43db64: 62 f1 7c 48 11 56 fe vmovups %zmm2,-0x80(%rsi) - 43db6b: 62 f1 7c 48 11 56 ff vmovups %zmm2,-0x40(%rsi) - 43db72: c3 retq - 43db73: 80 fa 40 cmp $0x40,%dl - 43db76: 72 0e jb 43db86 <__memset_avx512_no_vzeroupper+0xa6> - 43db78: 62 f1 7c 48 11 17 vmovups %zmm2,(%rdi) - 43db7e: 62 f1 7c 48 11 56 ff vmovups %zmm2,-0x40(%rsi) - 43db85: c3 retq - 43db86: 80 fa 20 cmp $0x20,%dl - 43db89: 72 0a jb 43db95 <__memset_avx512_no_vzeroupper+0xb5> - 43db8b: c5 fe 7f 17 vmovdqu %ymm2,(%rdi) - 43db8f: c5 fe 7f 56 e0 vmovdqu %ymm2,-0x20(%rsi) - 43db94: c3 retq - 43db95: c5 fa 7f 07 vmovdqu %xmm0,(%rdi) - 43db99: c5 fa 7f 46 f0 vmovdqu %xmm0,-0x10(%rsi) - 43db9e: c3 retq - 43db9f: 80 fa 08 cmp $0x8,%dl - 43dba2: 72 0a jb 43dbae <__memset_avx512_no_vzeroupper+0xce> - 43dba4: c5 f9 d6 07 vmovq %xmm0,(%rdi) - 43dba8: c5 f9 d6 46 f8 vmovq %xmm0,-0x8(%rsi) - 43dbad: c3 retq - 43dbae: c5 f9 7e c1 vmovd %xmm0,%ecx - 43dbb2: 80 fa 04 cmp $0x4,%dl - 43dbb5: 72 06 jb 43dbbd <__memset_avx512_no_vzeroupper+0xdd> - 43dbb7: 89 0f mov %ecx,(%rdi) - 43dbb9: 89 4e fc mov %ecx,-0x4(%rsi) - 43dbbc: c3 retq - 43dbbd: 80 fa 02 cmp $0x2,%dl - 43dbc0: 72 08 jb 43dbca <__memset_avx512_no_vzeroupper+0xea> - 43dbc2: 66 89 0f mov %cx,(%rdi) - 43dbc5: 66 89 4e fe mov %cx,-0x2(%rsi) - 43dbc9: c3 retq - 43dbca: 80 fa 01 cmp $0x1,%dl - 43dbcd: 72 02 jb 43dbd1 <__memset_avx512_no_vzeroupper+0xf1> - 43dbcf: 88 0f mov %cl,(%rdi) - 43dbd1: c3 retq - 43dbd2: 48 8b 0d d7 d4 28 00 mov 0x28d4d7(%rip),%rcx # 6cb0b0 <__x86_shared_cache_size_half> - 43dbd9: 48 39 ca cmp %rcx,%rdx - 43dbdc: 0f 87 d1 00 00 00 ja 43dcb3 <__memset_avx512_no_vzeroupper+0x1d3> - 43dbe2: 48 81 fa 00 04 00 00 cmp $0x400,%rdx - 43dbe9: 77 70 ja 43dc5b <__memset_avx512_no_vzeroupper+0x17b> - 43dbeb: 62 f1 7c 48 11 17 vmovups %zmm2,(%rdi) - 43dbf1: 62 f1 7c 48 11 57 01 vmovups %zmm2,0x40(%rdi) - 43dbf8: 62 f1 7c 48 11 57 02 vmovups %zmm2,0x80(%rdi) - 43dbff: 62 f1 7c 48 11 57 03 vmovups %zmm2,0xc0(%rdi) - 43dc06: 62 f1 7c 48 11 57 04 vmovups %zmm2,0x100(%rdi) - 43dc0d: 62 f1 7c 48 11 57 05 vmovups %zmm2,0x140(%rdi) - 43dc14: 62 f1 7c 48 11 57 06 vmovups %zmm2,0x180(%rdi) - 43dc1b: 62 f1 7c 48 11 57 07 vmovups %zmm2,0x1c0(%rdi) - 43dc22: 62 f1 7c 48 11 56 f8 vmovups %zmm2,-0x200(%rsi) - 43dc29: 62 f1 7c 48 11 56 f9 vmovups %zmm2,-0x1c0(%rsi) - 43dc30: 62 f1 7c 48 11 56 fa vmovups %zmm2,-0x180(%rsi) - 43dc37: 62 f1 7c 48 11 56 fb vmovups %zmm2,-0x140(%rsi) - 43dc3e: 62 f1 7c 48 11 56 fc vmovups %zmm2,-0x100(%rsi) - 43dc45: 62 f1 7c 48 11 56 fd vmovups %zmm2,-0xc0(%rsi) - 43dc4c: 62 f1 7c 48 11 56 fe vmovups %zmm2,-0x80(%rsi) - 43dc53: 62 f1 7c 48 11 56 ff vmovups %zmm2,-0x40(%rsi) - 43dc5a: c3 retq - 43dc5b: 48 81 ee 00 01 00 00 sub $0x100,%rsi - 43dc62: 62 f1 7c 48 11 10 vmovups %zmm2,(%rax) - 43dc68: 48 83 e7 c0 and $0xffffffffffffffc0,%rdi - 43dc6c: 48 83 c7 40 add $0x40,%rdi - 43dc70: 62 f1 7c 48 29 17 vmovaps %zmm2,(%rdi) - 43dc76: 62 f1 7c 48 29 57 01 vmovaps %zmm2,0x40(%rdi) - 43dc7d: 62 f1 7c 48 29 57 02 vmovaps %zmm2,0x80(%rdi) - 43dc84: 62 f1 7c 48 29 57 03 vmovaps %zmm2,0xc0(%rdi) - 43dc8b: 48 81 c7 00 01 00 00 add $0x100,%rdi - 43dc92: 48 39 f7 cmp %rsi,%rdi - 43dc95: 72 d9 jb 43dc70 <__memset_avx512_no_vzeroupper+0x190> - 43dc97: 62 f1 7c 48 11 16 vmovups %zmm2,(%rsi) - 43dc9d: 62 f1 7c 48 11 56 01 vmovups %zmm2,0x40(%rsi) - 43dca4: 62 f1 7c 48 11 56 02 vmovups %zmm2,0x80(%rsi) - 43dcab: 62 f1 7c 48 11 56 03 vmovups %zmm2,0xc0(%rsi) - 43dcb2: c3 retq - 43dcb3: 48 83 e7 80 and $0xffffffffffffff80,%rdi - 43dcb7: 48 81 c7 80 00 00 00 add $0x80,%rdi - 43dcbe: 62 f1 7c 48 11 10 vmovups %zmm2,(%rax) - 43dcc4: 62 f1 7c 48 11 50 01 vmovups %zmm2,0x40(%rax) - 43dccb: 48 81 ee 00 02 00 00 sub $0x200,%rsi - 43dcd2: 62 f1 7d 48 e7 17 vmovntdq %zmm2,(%rdi) - 43dcd8: 62 f1 7d 48 e7 57 01 vmovntdq %zmm2,0x40(%rdi) - 43dcdf: 62 f1 7d 48 e7 57 02 vmovntdq %zmm2,0x80(%rdi) - 43dce6: 62 f1 7d 48 e7 57 03 vmovntdq %zmm2,0xc0(%rdi) - 43dced: 62 f1 7d 48 e7 57 04 vmovntdq %zmm2,0x100(%rdi) - 43dcf4: 62 f1 7d 48 e7 57 05 vmovntdq %zmm2,0x140(%rdi) - 43dcfb: 62 f1 7d 48 e7 57 06 vmovntdq %zmm2,0x180(%rdi) - 43dd02: 62 f1 7d 48 e7 57 07 vmovntdq %zmm2,0x1c0(%rdi) - 43dd09: 48 81 c7 00 02 00 00 add $0x200,%rdi - 43dd10: 48 39 f7 cmp %rsi,%rdi - 43dd13: 72 bd jb 43dcd2 <__memset_avx512_no_vzeroupper+0x1f2> - 43dd15: 0f ae f8 sfence - 43dd18: 62 f1 7c 48 11 16 vmovups %zmm2,(%rsi) - 43dd1e: 62 f1 7c 48 11 56 01 vmovups %zmm2,0x40(%rsi) - 43dd25: 62 f1 7c 48 11 56 02 vmovups %zmm2,0x80(%rsi) - 43dd2c: 62 f1 7c 48 11 56 03 vmovups %zmm2,0xc0(%rsi) - 43dd33: 62 f1 7c 48 11 56 04 vmovups %zmm2,0x100(%rsi) - 43dd3a: 62 f1 7c 48 11 56 05 vmovups %zmm2,0x140(%rsi) - 43dd41: 62 f1 7c 48 11 56 06 vmovups %zmm2,0x180(%rsi) - 43dd48: 62 f1 7c 48 11 56 07 vmovups %zmm2,0x1c0(%rsi) - 43dd4f: c3 retq - -000000000043dd50 : - 43dd50: 85 f6 test %esi,%esi - 43dd52: 0f 88 16 02 00 00 js 43df6e - 43dd58: 44 8d 87 47 ff ff ff lea -0xb9(%rdi),%r8d - 43dd5f: 41 55 push %r13 - 43dd61: 41 54 push %r12 - 43dd63: 55 push %rbp - 43dd64: 53 push %rbx - 43dd65: 48 89 d3 mov %rdx,%rbx - 43dd68: 44 89 c0 mov %r8d,%eax - 43dd6b: ba 56 55 55 55 mov $0x55555556,%edx - 43dd70: 41 c1 f8 1f sar $0x1f,%r8d - 43dd74: f7 ea imul %edx - 43dd76: 48 83 ec 08 sub $0x8,%rsp - 43dd7a: 44 29 c2 sub %r8d,%edx - 43dd7d: 85 f6 test %esi,%esi - 43dd7f: 44 8d 1c 52 lea (%rdx,%rdx,2),%r11d - 43dd83: 0f 84 b8 00 00 00 je 43de41 - 43dd89: 83 3d 28 e9 28 00 0f cmpl $0xf,0x28e928(%rip) # 6cc6b8 <_dl_x86_cpu_features+0x38> - 43dd90: 40 0f 94 c5 sete %bpl - 43dd94: 83 3d 21 e9 28 00 06 cmpl $0x6,0x28e921(%rip) # 6cc6bc <_dl_x86_cpu_features+0x3c> - 43dd9b: 0f 94 c0 sete %al - 43dd9e: 21 c5 and %eax,%ebp - 43dda0: 40 0f b6 c6 movzbl %sil,%eax - 43dda4: 83 f8 40 cmp $0x40,%eax - 43dda7: 0f 84 b3 00 00 00 je 43de60 - 43ddad: 3d ff 00 00 00 cmp $0xff,%eax - 43ddb2: 0f 84 bd 00 00 00 je 43de75 - 43ddb8: 83 f8 49 cmp $0x49,%eax - 43ddbb: 75 14 jne 43ddd1 - 43ddbd: 41 83 fb 09 cmp $0x9,%r11d - 43ddc1: 75 0e jne 43ddd1 - 43ddc3: 40 84 ed test %bpl,%bpl - 43ddc6: 74 09 je 43ddd1 - 43ddc8: 83 ef 03 sub $0x3,%edi - 43ddcb: 41 bb 06 00 00 00 mov $0x6,%r11d - 43ddd1: 41 89 f1 mov %esi,%r9d - 43ddd4: 31 d2 xor %edx,%edx - 43ddd6: 41 ba 44 00 00 00 mov $0x44,%r10d - 43dddc: 0f 1f 40 00 nopl 0x0(%rax) - 43dde0: 49 8d 04 12 lea (%r10,%rdx,1),%rax - 43dde4: 48 d1 e8 shr %rax - 43dde7: 44 3a 0c c5 60 3d 4a cmp 0x4a3d60(,%rax,8),%r9b - 43ddee: 00 - 43ddef: 4c 8d 04 c5 60 3d 4a lea 0x4a3d60(,%rax,8),%r8 - 43ddf6: 00 - 43ddf7: 74 29 je 43de22 - 43ddf9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43de00: 73 4e jae 43de50 - 43de02: 48 39 d0 cmp %rdx,%rax - 43de05: 49 89 c2 mov %rax,%r10 - 43de08: 76 2c jbe 43de36 - 43de0a: 48 01 d0 add %rdx,%rax - 43de0d: 48 d1 e8 shr %rax - 43de10: 44 3a 0c c5 60 3d 4a cmp 0x4a3d60(,%rax,8),%r9b - 43de17: 00 - 43de18: 4c 8d 04 c5 60 3d 4a lea 0x4a3d60(,%rax,8),%r8 - 43de1f: 00 - 43de20: 75 de jne 43de00 - 43de22: 41 0f b6 50 03 movzbl 0x3(%r8),%edx - 43de27: 41 39 d3 cmp %edx,%r11d - 43de2a: 89 d0 mov %edx,%eax - 43de2c: 0f 84 3f 01 00 00 je 43df71 - 43de32: 3c 06 cmp $0x6,%al - 43de34: 74 3a je 43de70 - 43de36: c1 ee 08 shr $0x8,%esi - 43de39: 85 f6 test %esi,%esi - 43de3b: 0f 85 5f ff ff ff jne 43dda0 - 43de41: 31 c0 xor %eax,%eax - 43de43: 48 83 c4 08 add $0x8,%rsp - 43de47: 5b pop %rbx - 43de48: 5d pop %rbp - 43de49: 41 5c pop %r12 - 43de4b: 41 5d pop %r13 - 43de4d: c3 retq - 43de4e: 66 90 xchg %ax,%ax - 43de50: 48 8d 50 01 lea 0x1(%rax),%rdx - 43de54: 4c 39 d2 cmp %r10,%rdx - 43de57: 72 87 jb 43dde0 - 43de59: eb db jmp 43de36 - 43de5b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43de60: 41 83 fb 09 cmp $0x9,%r11d - 43de64: c6 01 01 movb $0x1,(%rcx) - 43de67: 75 cd jne 43de36 - 43de69: eb d6 jmp 43de41 - 43de6b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43de70: c6 03 01 movb $0x1,(%rbx) - 43de73: eb c1 jmp 43de36 - 43de75: 31 c9 xor %ecx,%ecx - 43de77: b8 04 00 00 00 mov $0x4,%eax - 43de7c: 0f a2 cpuid - 43de7e: 89 c6 mov %eax,%esi - 43de80: 83 e6 1f and $0x1f,%esi - 43de83: 74 bc je 43de41 - 43de85: c1 e8 05 shr $0x5,%eax - 43de88: 83 e0 07 and $0x7,%eax - 43de8b: 83 f8 01 cmp $0x1,%eax - 43de8e: 0f 94 c2 sete %dl - 43de91: 41 83 fb 03 cmp $0x3,%r11d - 43de95: 41 0f 94 c1 sete %r9b - 43de99: 83 fe 01 cmp $0x1,%esi - 43de9c: 41 0f 94 c0 sete %r8b - 43dea0: 45 84 c8 test %r9b,%r8b - 43dea3: 74 08 je 43dead - 43dea5: 84 d2 test %dl,%dl - 43dea7: 0f 85 8e 00 00 00 jne 43df3b - 43dead: 45 85 db test %r11d,%r11d - 43deb0: 41 0f 94 c2 sete %r10b - 43deb4: 83 fe 02 cmp $0x2,%esi - 43deb7: 40 0f 94 c6 sete %sil - 43debb: 44 84 d6 test %r10b,%sil - 43debe: 74 04 je 43dec4 - 43dec0: 84 d2 test %dl,%dl - 43dec2: 75 77 jne 43df3b - 43dec4: 41 83 fb 06 cmp $0x6,%r11d - 43dec8: 41 b8 04 00 00 00 mov $0x4,%r8d - 43dece: 40 0f 94 c5 sete %bpl - 43ded2: 31 f6 xor %esi,%esi - 43ded4: 0f 1f 40 00 nopl 0x0(%rax) - 43ded8: 83 f8 02 cmp $0x2,%eax - 43dedb: 75 05 jne 43dee2 - 43dedd: 40 84 ed test %bpl,%bpl - 43dee0: 75 59 jne 43df3b - 43dee2: 83 f8 03 cmp $0x3,%eax - 43dee5: 75 06 jne 43deed - 43dee7: 41 83 fb 09 cmp $0x9,%r11d - 43deeb: 74 4e je 43df3b - 43deed: 83 f8 04 cmp $0x4,%eax - 43def0: 75 06 jne 43def8 - 43def2: 41 83 fb 0c cmp $0xc,%r11d - 43def6: 74 43 je 43df3b - 43def8: 83 c6 01 add $0x1,%esi - 43defb: 44 89 c0 mov %r8d,%eax - 43defe: 89 f1 mov %esi,%ecx - 43df00: 0f a2 cpuid - 43df02: 89 c2 mov %eax,%edx - 43df04: 83 e2 1f and $0x1f,%edx - 43df07: 0f 84 34 ff ff ff je 43de41 - 43df0d: c1 e8 05 shr $0x5,%eax - 43df10: 83 e0 07 and $0x7,%eax - 43df13: 83 f8 01 cmp $0x1,%eax - 43df16: 41 0f 94 c4 sete %r12b - 43df1a: 83 fa 01 cmp $0x1,%edx - 43df1d: 41 0f 94 c5 sete %r13b - 43df21: 45 84 cd test %r9b,%r13b - 43df24: 74 05 je 43df2b - 43df26: 45 84 e4 test %r12b,%r12b - 43df29: 75 10 jne 43df3b - 43df2b: 83 fa 02 cmp $0x2,%edx - 43df2e: 0f 94 c2 sete %dl - 43df31: 44 84 d2 test %r10b,%dl - 43df34: 74 a2 je 43ded8 - 43df36: 45 84 e4 test %r12b,%r12b - 43df39: 74 9d je 43ded8 - 43df3b: 8d 87 47 ff ff ff lea -0xb9(%rdi),%eax - 43df41: 44 29 d8 sub %r11d,%eax - 43df44: 74 59 je 43df9f - 43df46: 83 f8 01 cmp $0x1,%eax - 43df49: 0f 84 82 00 00 00 je 43dfd1 - 43df4f: 83 f8 02 cmp $0x2,%eax - 43df52: 0f 85 a9 00 00 00 jne 43e001 - 43df58: 89 d8 mov %ebx,%eax - 43df5a: 48 83 c4 08 add $0x8,%rsp - 43df5e: 25 ff 0f 00 00 and $0xfff,%eax - 43df63: 5b pop %rbx - 43df64: 48 83 c0 01 add $0x1,%rax - 43df68: 5d pop %rbp - 43df69: 41 5c pop %r12 - 43df6b: 41 5d pop %r13 - 43df6d: c3 retq - 43df6e: 31 c0 xor %eax,%eax - 43df70: c3 retq - 43df71: 8d 87 47 ff ff ff lea -0xb9(%rdi),%eax - 43df77: 44 29 d8 sub %r11d,%eax - 43df7a: 74 14 je 43df90 - 43df7c: 83 f8 01 cmp $0x1,%eax - 43df7f: 74 5d je 43dfde - 43df81: 83 f8 02 cmp $0x2,%eax - 43df84: 75 62 jne 43dfe8 - 43df86: 41 0f b6 40 02 movzbl 0x2(%r8),%eax - 43df8b: e9 b3 fe ff ff jmpq 43de43 - 43df90: 41 8b 40 04 mov 0x4(%r8),%eax - 43df94: 48 83 c4 08 add $0x8,%rsp - 43df98: 5b pop %rbx - 43df99: 5d pop %rbp - 43df9a: 41 5c pop %r12 - 43df9c: 41 5d pop %r13 - 43df9e: c3 retq - 43df9f: 89 d8 mov %ebx,%eax - 43dfa1: 83 c1 01 add $0x1,%ecx - 43dfa4: c1 e8 16 shr $0x16,%eax - 43dfa7: 8d 50 01 lea 0x1(%rax),%edx - 43dfaa: 89 d8 mov %ebx,%eax - 43dfac: 25 ff 0f 00 00 and $0xfff,%eax - 43dfb1: 83 c0 01 add $0x1,%eax - 43dfb4: 0f af c2 imul %edx,%eax - 43dfb7: 0f af c1 imul %ecx,%eax - 43dfba: 89 c2 mov %eax,%edx - 43dfbc: 89 d8 mov %ebx,%eax - 43dfbe: c1 e8 0c shr $0xc,%eax - 43dfc1: 25 ff 03 00 00 and $0x3ff,%eax - 43dfc6: 83 c0 01 add $0x1,%eax - 43dfc9: 0f af c2 imul %edx,%eax - 43dfcc: e9 72 fe ff ff jmpq 43de43 - 43dfd1: 89 d8 mov %ebx,%eax - 43dfd3: c1 e8 16 shr $0x16,%eax - 43dfd6: 83 c0 01 add $0x1,%eax - 43dfd9: e9 65 fe ff ff jmpq 43de43 - 43dfde: 41 0f b6 40 01 movzbl 0x1(%r8),%eax - 43dfe3: e9 5b fe ff ff jmpq 43de43 - 43dfe8: b9 90 3f 4a 00 mov $0x4a3f90,%ecx - 43dfed: ba f1 00 00 00 mov $0xf1,%edx - 43dff2: be b0 3b 4a 00 mov $0x4a3bb0,%esi - 43dff7: bf ce 3b 4a 00 mov $0x4a3bce,%edi - 43dffc: e8 3f 37 fc ff callq 401740 <__assert_fail> - 43e001: b9 90 3f 4a 00 mov $0x4a3f90,%ecx - 43e006: ba c1 00 00 00 mov $0xc1,%edx - 43e00b: be b0 3b 4a 00 mov $0x4a3bb0,%esi - 43e010: bf ce 3b 4a 00 mov $0x4a3bce,%edi - 43e015: e8 26 37 fc ff callq 401740 <__assert_fail> - 43e01a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - -000000000043e020 : - 43e020: 83 fe 01 cmp $0x1,%esi - 43e023: 0f 86 f7 00 00 00 jbe 43e120 - 43e029: 41 57 push %r15 - 43e02b: 41 56 push %r14 - 43e02d: 41 bf 01 00 00 00 mov $0x1,%r15d - 43e033: 41 55 push %r13 - 43e035: 41 54 push %r12 - 43e037: 41 bc 01 00 00 00 mov $0x1,%r12d - 43e03d: 55 push %rbp - 43e03e: 53 push %rbx - 43e03f: 89 fd mov %edi,%ebp - 43e041: 48 83 ec 18 sub $0x18,%rsp - 43e045: c6 44 24 0e 00 movb $0x0,0xe(%rsp) - 43e04a: c6 44 24 0f 00 movb $0x0,0xf(%rsp) - 43e04f: eb 78 jmp 43e0c9 - 43e051: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43e058: 48 8d 4c 24 0e lea 0xe(%rsp),%rcx - 43e05d: 48 8d 54 24 0f lea 0xf(%rsp),%rdx - 43e062: 89 ef mov %ebp,%edi - 43e064: e8 e7 fc ff ff callq 43dd50 - 43e069: 48 85 c0 test %rax,%rax - 43e06c: 0f 85 97 00 00 00 jne 43e109 - 43e072: 48 8d 4c 24 0e lea 0xe(%rsp),%rcx - 43e077: 48 8d 54 24 0f lea 0xf(%rsp),%rdx - 43e07c: 89 de mov %ebx,%esi - 43e07e: 89 ef mov %ebp,%edi - 43e080: e8 cb fc ff ff callq 43dd50 - 43e085: 48 85 c0 test %rax,%rax - 43e088: 75 7f jne 43e109 - 43e08a: 48 8d 4c 24 0e lea 0xe(%rsp),%rcx - 43e08f: 48 8d 54 24 0f lea 0xf(%rsp),%rdx - 43e094: 44 89 ee mov %r13d,%esi - 43e097: 89 ef mov %ebp,%edi - 43e099: e8 b2 fc ff ff callq 43dd50 - 43e09e: 48 85 c0 test %rax,%rax - 43e0a1: 75 66 jne 43e109 - 43e0a3: 48 8d 4c 24 0e lea 0xe(%rsp),%rcx - 43e0a8: 48 8d 54 24 0f lea 0xf(%rsp),%rdx - 43e0ad: 44 89 f6 mov %r14d,%esi - 43e0b0: 89 ef mov %ebp,%edi - 43e0b2: e8 99 fc ff ff callq 43dd50 - 43e0b7: 48 85 c0 test %rax,%rax - 43e0ba: 75 4d jne 43e109 - 43e0bc: 45 39 e7 cmp %r12d,%r15d - 43e0bf: 41 8d 44 24 01 lea 0x1(%r12),%eax - 43e0c4: 76 2a jbe 43e0f0 - 43e0c6: 41 89 c4 mov %eax,%r12d - 43e0c9: b8 02 00 00 00 mov $0x2,%eax - 43e0ce: 0f a2 cpuid - 43e0d0: 41 83 fc 01 cmp $0x1,%r12d - 43e0d4: 41 89 d6 mov %edx,%r14d - 43e0d7: 41 89 cd mov %ecx,%r13d - 43e0da: 89 c6 mov %eax,%esi - 43e0dc: 0f 85 76 ff ff ff jne 43e058 - 43e0e2: 44 0f b6 f8 movzbl %al,%r15d - 43e0e6: 40 80 e6 00 and $0x0,%sil - 43e0ea: e9 69 ff ff ff jmpq 43e058 - 43e0ef: 90 nop - 43e0f0: 81 ed bf 00 00 00 sub $0xbf,%ebp - 43e0f6: 83 fd 05 cmp $0x5,%ebp - 43e0f9: 77 2d ja 43e128 - 43e0fb: 80 7c 24 0e 00 cmpb $0x0,0xe(%rsp) - 43e100: 74 26 je 43e128 - 43e102: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax - 43e109: 48 83 c4 18 add $0x18,%rsp - 43e10d: 5b pop %rbx - 43e10e: 5d pop %rbp - 43e10f: 41 5c pop %r12 - 43e111: 41 5d pop %r13 - 43e113: 41 5e pop %r14 - 43e115: 41 5f pop %r15 - 43e117: c3 retq - 43e118: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 43e11f: 00 - 43e120: 31 c0 xor %eax,%eax - 43e122: c3 retq - 43e123: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43e128: 48 83 c4 18 add $0x18,%rsp - 43e12c: 31 c0 xor %eax,%eax - 43e12e: 5b pop %rbx - 43e12f: 5d pop %rbp - 43e130: 41 5c pop %r12 - 43e132: 41 5d pop %r13 - 43e134: 41 5e pop %r14 - 43e136: 41 5f pop %r15 - 43e138: c3 retq - 43e139: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - -000000000043e140 : - 43e140: 53 push %rbx - 43e141: b8 00 00 00 80 mov $0x80000000,%eax - 43e146: 0f a2 cpuid - 43e148: 81 ff c4 00 00 00 cmp $0xc4,%edi - 43e14e: 7f 40 jg 43e190 - 43e150: 31 d2 xor %edx,%edx - 43e152: 81 ff be 00 00 00 cmp $0xbe,%edi - 43e158: 0f 9f c2 setg %dl - 43e15b: 81 ea fb ff ff 7f sub $0x7ffffffb,%edx - 43e161: 39 c2 cmp %eax,%edx - 43e163: 77 2b ja 43e190 - 43e165: 89 d0 mov %edx,%eax - 43e167: 0f a2 cpuid - 43e169: 81 ff bb 00 00 00 cmp $0xbb,%edi - 43e16f: 7e 27 jle 43e198 - 43e171: 81 ef bc 00 00 00 sub $0xbc,%edi - 43e177: 83 ff 08 cmp $0x8,%edi - 43e17a: 0f 87 30 01 00 00 ja 43e2b0 - 43e180: ff 24 fd 00 3c 4a 00 jmpq *0x4a3c00(,%rdi,8) - 43e187: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 43e18e: 00 00 - 43e190: 31 c0 xor %eax,%eax - 43e192: 5b pop %rbx - 43e193: c3 retq - 43e194: 0f 1f 40 00 nopl 0x0(%rax) - 43e198: 83 c7 03 add $0x3,%edi - 43e19b: 89 d1 mov %edx,%ecx - 43e19d: eb d2 jmp 43e171 - 43e19f: 90 nop - 43e1a0: 31 c0 xor %eax,%eax - 43e1a2: f6 c5 f0 test $0xf0,%ch - 43e1a5: 74 eb je 43e192 - 43e1a7: 0f b6 c1 movzbl %cl,%eax - 43e1aa: 5b pop %rbx - 43e1ab: c3 retq - 43e1ac: 0f 1f 40 00 nopl 0x0(%rax) - 43e1b0: 31 c0 xor %eax,%eax - 43e1b2: f6 c5 f0 test $0xf0,%ch - 43e1b5: 74 db je 43e192 - 43e1b7: 89 c8 mov %ecx,%eax - 43e1b9: c1 e8 06 shr $0x6,%eax - 43e1bc: 25 00 fc ff 03 and $0x3fffc00,%eax - 43e1c1: 5b pop %rbx - 43e1c2: c3 retq - 43e1c3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43e1c8: 31 c0 xor %eax,%eax - 43e1ca: f6 c6 f0 test $0xf0,%dh - 43e1cd: 74 c3 je 43e192 - 43e1cf: 0f b6 c2 movzbl %dl,%eax - 43e1d2: 5b pop %rbx - 43e1d3: c3 retq - 43e1d4: 0f 1f 40 00 nopl 0x0(%rax) - 43e1d8: 89 c8 mov %ecx,%eax - 43e1da: c1 e8 0e shr $0xe,%eax - 43e1dd: 25 00 fc 03 00 and $0x3fc00,%eax - 43e1e2: 5b pop %rbx - 43e1e3: c3 retq - 43e1e4: 0f 1f 40 00 nopl 0x0(%rax) - 43e1e8: c1 e9 10 shr $0x10,%ecx - 43e1eb: 0f b6 c1 movzbl %cl,%eax - 43e1ee: 3d ff 00 00 00 cmp $0xff,%eax - 43e1f3: 75 9d jne 43e192 - 43e1f5: 8d 04 8d 00 00 00 00 lea 0x0(,%rcx,4),%eax - 43e1fc: 5b pop %rbx - 43e1fd: 25 00 fc 03 00 and $0x3fc00,%eax - 43e202: c3 retq - 43e203: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43e208: 89 ca mov %ecx,%edx - 43e20a: c1 ea 0c shr $0xc,%edx - 43e20d: 83 e2 0f and $0xf,%edx - 43e210: ff 24 d5 48 3c 4a 00 jmpq *0x4a3c48(,%rdx,8) - 43e217: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 43e21e: 00 00 - 43e220: 31 c0 xor %eax,%eax - 43e222: f6 c6 f0 test $0xf0,%dh - 43e225: 0f 84 67 ff ff ff je 43e192 - 43e22b: 48 8d 04 12 lea (%rdx,%rdx,1),%rax - 43e22f: 5b pop %rbx - 43e230: 25 00 00 f8 7f and $0x7ff80000,%eax - 43e235: c3 retq - 43e236: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43e23d: 00 00 00 - 43e240: 89 d0 mov %edx,%eax - 43e242: c1 e8 0c shr $0xc,%eax - 43e245: 83 e0 0f and $0xf,%eax - 43e248: ff 24 c5 c8 3c 4a 00 jmpq *0x4a3cc8(,%rax,8) - 43e24f: b8 08 00 00 00 mov $0x8,%eax - 43e254: 5b pop %rbx - 43e255: c3 retq - 43e256: b8 80 00 00 00 mov $0x80,%eax - 43e25b: 5b pop %rbx - 43e25c: c3 retq - 43e25d: b8 60 00 00 00 mov $0x60,%eax - 43e262: 5b pop %rbx - 43e263: c3 retq - 43e264: b8 40 00 00 00 mov $0x40,%eax - 43e269: 5b pop %rbx - 43e26a: c3 retq - 43e26b: b8 30 00 00 00 mov $0x30,%eax - 43e270: 5b pop %rbx - 43e271: c3 retq - 43e272: b8 20 00 00 00 mov $0x20,%eax - 43e277: 5b pop %rbx - 43e278: c3 retq - 43e279: b8 10 00 00 00 mov $0x10,%eax - 43e27e: 5b pop %rbx - 43e27f: c3 retq - 43e280: 89 ca mov %ecx,%edx - 43e282: 0f b6 c9 movzbl %cl,%ecx - 43e285: c1 ea 06 shr $0x6,%edx - 43e288: 89 d0 mov %edx,%eax - 43e28a: 31 d2 xor %edx,%edx - 43e28c: 25 00 fc ff 03 and $0x3fffc00,%eax - 43e291: f7 f1 div %ecx - 43e293: 5b pop %rbx - 43e294: 89 c0 mov %eax,%eax - 43e296: c3 retq - 43e297: 48 89 d0 mov %rdx,%rax - 43e29a: 5b pop %rbx - 43e29b: c3 retq - 43e29c: 89 d0 mov %edx,%eax - 43e29e: 0f b6 ca movzbl %dl,%ecx - 43e2a1: 31 d2 xor %edx,%edx - 43e2a3: 25 00 00 fc 3f and $0x3ffc0000,%eax - 43e2a8: 01 c0 add %eax,%eax - 43e2aa: f7 f1 div %ecx - 43e2ac: 5b pop %rbx - 43e2ad: 89 c0 mov %eax,%eax - 43e2af: c3 retq - 43e2b0: b9 80 3f 4a 00 mov $0x4a3f80,%ecx - 43e2b5: ba b0 01 00 00 mov $0x1b0,%edx - 43e2ba: be b0 3b 4a 00 mov $0x4a3bb0,%esi - 43e2bf: bf da 3b 4a 00 mov $0x4a3bda,%edi - 43e2c4: e8 77 34 fc ff callq 401740 <__assert_fail> - 43e2c9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - -000000000043e2d0 <__cache_sysconf>: - 43e2d0: 8b 05 aa e3 28 00 mov 0x28e3aa(%rip),%eax # 6cc680 <_dl_x86_cpu_features> - 43e2d6: 83 f8 01 cmp $0x1,%eax - 43e2d9: 74 15 je 43e2f0 <__cache_sysconf+0x20> - 43e2db: 83 f8 02 cmp $0x2,%eax - 43e2de: 74 08 je 43e2e8 <__cache_sysconf+0x18> - 43e2e0: 31 c0 xor %eax,%eax - 43e2e2: c3 retq - 43e2e3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43e2e8: e9 53 fe ff ff jmpq 43e140 - 43e2ed: 0f 1f 00 nopl (%rax) - 43e2f0: 8b 35 8e e3 28 00 mov 0x28e38e(%rip),%esi # 6cc684 <_dl_x86_cpu_features+0x4> - 43e2f6: e9 25 fd ff ff jmpq 43e020 - 43e2fb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - -000000000043e300 <__strcasecmp_l_nonascii>: - 43e300: 48 39 f7 cmp %rsi,%rdi - 43e303: 74 33 je 43e338 <__strcasecmp_l_nonascii+0x38> - 43e305: 48 8b 52 70 mov 0x70(%rdx),%rdx - 43e309: eb 0e jmp 43e319 <__strcasecmp_l_nonascii+0x19> - 43e30b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43e310: 48 83 c7 01 add $0x1,%rdi - 43e314: 45 84 c0 test %r8b,%r8b - 43e317: 74 1f je 43e338 <__strcasecmp_l_nonascii+0x38> - 43e319: 48 83 c6 01 add $0x1,%rsi - 43e31d: 0f b6 07 movzbl (%rdi),%eax - 43e320: 0f b6 4e ff movzbl -0x1(%rsi),%ecx - 43e324: 49 89 c0 mov %rax,%r8 - 43e327: 8b 04 82 mov (%rdx,%rax,4),%eax - 43e32a: 2b 04 8a sub (%rdx,%rcx,4),%eax - 43e32d: 74 e1 je 43e310 <__strcasecmp_l_nonascii+0x10> - 43e32f: f3 c3 repz retq - 43e331: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43e338: 31 c0 xor %eax,%eax - 43e33a: c3 retq - 43e33b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - -000000000043e340 <__wmempcpy>: - 43e340: 48 c1 e2 02 shl $0x2,%rdx - 43e344: e9 77 82 fe ff jmpq 4265c0 <__mempcpy> - 43e349: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - -000000000043e350 <_nl_cleanup_ctype>: - 43e350: 53 push %rbx - 43e351: 48 8b 5f 28 mov 0x28(%rdi),%rbx - 43e355: 48 85 db test %rbx,%rbx - 43e358: 74 36 je 43e390 <_nl_cleanup_ctype+0x40> - 43e35a: 48 c7 47 28 00 00 00 movq $0x0,0x28(%rdi) - 43e361: 00 - 43e362: 48 c7 47 20 00 00 00 movq $0x0,0x20(%rdi) - 43e369: 00 - 43e36a: 48 8b 73 18 mov 0x18(%rbx),%rsi - 43e36e: 48 8b 7b 10 mov 0x10(%rbx),%rdi - 43e372: e8 79 75 00 00 callq 4458f0 <__gconv_close_transform> - 43e377: 48 8b 3b mov (%rbx),%rdi - 43e37a: 48 8b 73 08 mov 0x8(%rbx),%rsi - 43e37e: e8 6d 75 00 00 callq 4458f0 <__gconv_close_transform> - 43e383: 48 89 df mov %rbx,%rdi - 43e386: 5b pop %rbx - 43e387: e9 24 fa fd ff jmpq 41ddb0 <__cfree> - 43e38c: 0f 1f 40 00 nopl 0x0(%rax) - 43e390: 5b pop %rbx - 43e391: c3 retq - 43e392: 0f 1f 40 00 nopl 0x0(%rax) - 43e396: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43e39d: 00 00 00 - -000000000043e3a0 <__wcsmbs_getfct>: - 43e3a0: 53 push %rbx - 43e3a1: 48 89 d3 mov %rdx,%rbx - 43e3a4: 45 31 c0 xor %r8d,%r8d - 43e3a7: 48 83 ec 10 sub $0x10,%rsp - 43e3ab: 48 8d 54 24 08 lea 0x8(%rsp),%rdx - 43e3b0: 48 89 e1 mov %rsp,%rcx - 43e3b3: e8 58 72 00 00 callq 445610 <__gconv_find_transform> - 43e3b8: 85 c0 test %eax,%eax - 43e3ba: 75 34 jne 43e3f0 <__wcsmbs_getfct+0x50> - 43e3bc: 48 8b 34 24 mov (%rsp),%rsi - 43e3c0: 48 83 fe 01 cmp $0x1,%rsi - 43e3c4: 76 1a jbe 43e3e0 <__wcsmbs_getfct+0x40> - 43e3c6: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi - 43e3cb: e8 20 75 00 00 callq 4458f0 <__gconv_close_transform> - 43e3d0: 48 83 c4 10 add $0x10,%rsp - 43e3d4: 31 c0 xor %eax,%eax - 43e3d6: 5b pop %rbx - 43e3d7: c3 retq - 43e3d8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 43e3df: 00 - 43e3e0: 48 89 33 mov %rsi,(%rbx) - 43e3e3: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 43e3e8: 48 83 c4 10 add $0x10,%rsp - 43e3ec: 5b pop %rbx - 43e3ed: c3 retq - 43e3ee: 66 90 xchg %ax,%ax - 43e3f0: 48 83 c4 10 add $0x10,%rsp - 43e3f4: 31 c0 xor %eax,%eax - 43e3f6: 5b pop %rbx - 43e3f7: c3 retq - 43e3f8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 43e3ff: 00 - -000000000043e400 <__wcsmbs_load_conv>: - 43e400: 55 push %rbp - 43e401: b8 00 00 00 00 mov $0x0,%eax - 43e406: 48 89 e5 mov %rsp,%rbp - 43e409: 41 55 push %r13 - 43e40b: 41 54 push %r12 - 43e40d: 53 push %rbx - 43e40e: 48 89 fb mov %rdi,%rbx - 43e411: 48 83 ec 18 sub $0x18,%rsp - 43e415: 48 85 c0 test %rax,%rax - 43e418: 74 07 je 43e421 <__wcsmbs_load_conv+0x21> - 43e41a: bf 20 c7 6c 00 mov $0x6cc720,%edi - 43e41f: ff d0 callq *%rax - 43e421: 48 83 7b 28 00 cmpq $0x0,0x28(%rbx) - 43e426: 74 20 je 43e448 <__wcsmbs_load_conv+0x48> - 43e428: b8 00 00 00 00 mov $0x0,%eax - 43e42d: 48 85 c0 test %rax,%rax - 43e430: 74 07 je 43e439 <__wcsmbs_load_conv+0x39> - 43e432: bf 20 c7 6c 00 mov $0x6cc720,%edi - 43e437: ff d0 callq *%rax - 43e439: 48 8d 65 e8 lea -0x18(%rbp),%rsp - 43e43d: 5b pop %rbx - 43e43e: 41 5c pop %r12 - 43e440: 41 5d pop %r13 - 43e442: 5d pop %rbp - 43e443: c3 retq - 43e444: 0f 1f 40 00 nopl 0x0(%rax) - 43e448: be 20 00 00 00 mov $0x20,%esi - 43e44d: bf 01 00 00 00 mov $0x1,%edi - 43e452: e8 69 01 fe ff callq 41e5c0 <__calloc> - 43e457: 48 85 c0 test %rax,%rax - 43e45a: 49 89 c4 mov %rax,%r12 - 43e45d: 0f 84 5d 01 00 00 je 43e5c0 <__wcsmbs_load_conv+0x1c0> - 43e463: 8b 73 34 mov 0x34(%rbx),%esi - 43e466: 4c 8b 83 b0 00 00 00 mov 0xb0(%rbx),%r8 - 43e46d: 83 fe 01 cmp $0x1,%esi - 43e470: 4c 89 c0 mov %r8,%rax - 43e473: 48 19 ff sbb %rdi,%rdi - 43e476: 48 83 e7 f8 and $0xfffffffffffffff8,%rdi - 43e47a: 48 83 c7 0b add $0xb,%rdi - 43e47e: 83 fe 01 cmp $0x1,%esi - 43e481: 48 19 d2 sbb %rdx,%rdx - 43e484: 45 31 c9 xor %r9d,%r9d - 43e487: 48 f7 d2 not %rdx - 43e48a: 83 e2 08 and $0x8,%edx - 43e48d: eb 11 jmp 43e4a0 <__wcsmbs_load_conv+0xa0> - 43e48f: 90 nop - 43e490: 48 83 c0 01 add $0x1,%rax - 43e494: 80 f9 2f cmp $0x2f,%cl - 43e497: 0f 94 c1 sete %cl - 43e49a: 0f b6 c9 movzbl %cl,%ecx - 43e49d: 49 01 c9 add %rcx,%r9 - 43e4a0: 0f b6 08 movzbl (%rax),%ecx - 43e4a3: 84 c9 test %cl,%cl - 43e4a5: 75 e9 jne 43e490 <__wcsmbs_load_conv+0x90> - 43e4a7: 4c 29 c0 sub %r8,%rax - 43e4aa: 49 0f be 08 movsbq (%r8),%rcx - 43e4ae: 48 8d 44 07 1e lea 0x1e(%rdi,%rax,1),%rax - 43e4b3: 48 83 e0 f0 and $0xfffffffffffffff0,%rax - 43e4b7: 48 29 c4 sub %rax,%rsp - 43e4ba: 4c 8d 6c 24 0f lea 0xf(%rsp),%r13 - 43e4bf: 49 83 e5 f0 and $0xfffffffffffffff0,%r13 - 43e4c3: 84 c9 test %cl,%cl - 43e4c5: 0f 84 6c 01 00 00 je 43e637 <__wcsmbs_load_conv+0x237> - 43e4cb: 48 8b 3d 26 42 07 00 mov 0x74226(%rip),%rdi # 4b26f8 <_nl_C_locobj+0x78> - 43e4d2: 4c 89 e8 mov %r13,%rax - 43e4d5: 0f 1f 00 nopl (%rax) - 43e4d8: 8b 0c 8f mov (%rdi,%rcx,4),%ecx - 43e4db: 48 83 c0 01 add $0x1,%rax - 43e4df: 49 83 c0 01 add $0x1,%r8 - 43e4e3: 88 48 ff mov %cl,-0x1(%rax) - 43e4e6: 49 0f be 08 movsbq (%r8),%rcx - 43e4ea: 84 c9 test %cl,%cl - 43e4ec: 75 ea jne 43e4d8 <__wcsmbs_load_conv+0xd8> - 43e4ee: 49 83 f9 01 cmp $0x1,%r9 - 43e4f2: 0f 86 d8 00 00 00 jbe 43e5d0 <__wcsmbs_load_conv+0x1d0> - 43e4f8: 48 8d 4d d0 lea -0x30(%rbp),%rcx - 43e4fc: 48 8d 55 d8 lea -0x28(%rbp),%rdx - 43e500: 45 31 c0 xor %r8d,%r8d - 43e503: c6 00 00 movb $0x0,(%rax) - 43e506: 4c 89 ee mov %r13,%rsi - 43e509: bf 6d 52 4a 00 mov $0x4a526d,%edi - 43e50e: e8 fd 70 00 00 callq 445610 <__gconv_find_transform> - 43e513: 85 c0 test %eax,%eax - 43e515: 0f 85 06 01 00 00 jne 43e621 <__wcsmbs_load_conv+0x221> - 43e51b: 48 8b 75 d0 mov -0x30(%rbp),%rsi - 43e51f: 48 83 fe 01 cmp $0x1,%rsi - 43e523: 76 2b jbe 43e550 <__wcsmbs_load_conv+0x150> - 43e525: 48 8b 7d d8 mov -0x28(%rbp),%rdi - 43e529: e8 c2 73 00 00 callq 4458f0 <__gconv_close_transform> - 43e52e: 49 83 7c 24 10 00 cmpq $0x0,0x10(%r12) - 43e534: 49 c7 04 24 00 00 00 movq $0x0,(%r12) - 43e53b: 00 - 43e53c: 74 7a je 43e5b8 <__wcsmbs_load_conv+0x1b8> - 43e53e: 4c 89 63 28 mov %r12,0x28(%rbx) - 43e542: 48 c7 43 20 50 e3 43 movq $0x43e350,0x20(%rbx) - 43e549: 00 - 43e54a: e9 d9 fe ff ff jmpq 43e428 <__wcsmbs_load_conv+0x28> - 43e54f: 90 nop - 43e550: 48 8b 45 d8 mov -0x28(%rbp),%rax - 43e554: 49 89 74 24 08 mov %rsi,0x8(%r12) - 43e559: 48 85 c0 test %rax,%rax - 43e55c: 49 89 04 24 mov %rax,(%r12) - 43e560: 0f 84 c3 00 00 00 je 43e629 <__wcsmbs_load_conv+0x229> - 43e566: 48 8d 4d d0 lea -0x30(%rbp),%rcx - 43e56a: 48 8d 55 d8 lea -0x28(%rbp),%rdx - 43e56e: 45 31 c0 xor %r8d,%r8d - 43e571: be 6d 52 4a 00 mov $0x4a526d,%esi - 43e576: 4c 89 ef mov %r13,%rdi - 43e579: e8 92 70 00 00 callq 445610 <__gconv_find_transform> - 43e57e: 85 c0 test %eax,%eax - 43e580: 0f 85 b9 00 00 00 jne 43e63f <__wcsmbs_load_conv+0x23f> - 43e586: 48 8b 75 d0 mov -0x30(%rbp),%rsi - 43e58a: 48 83 fe 01 cmp $0x1,%rsi - 43e58e: 76 58 jbe 43e5e8 <__wcsmbs_load_conv+0x1e8> - 43e590: 48 8b 7d d8 mov -0x28(%rbp),%rdi - 43e594: e8 57 73 00 00 callq 4458f0 <__gconv_close_transform> - 43e599: 31 c0 xor %eax,%eax - 43e59b: 48 85 c0 test %rax,%rax - 43e59e: 49 89 44 24 10 mov %rax,0x10(%r12) - 43e5a3: 75 99 jne 43e53e <__wcsmbs_load_conv+0x13e> - 43e5a5: 49 8b 3c 24 mov (%r12),%rdi - 43e5a9: 48 85 ff test %rdi,%rdi - 43e5ac: 74 0a je 43e5b8 <__wcsmbs_load_conv+0x1b8> - 43e5ae: 49 8b 74 24 08 mov 0x8(%r12),%rsi - 43e5b3: e8 38 73 00 00 callq 4458f0 <__gconv_close_transform> - 43e5b8: 4c 89 e7 mov %r12,%rdi - 43e5bb: e8 f0 f7 fd ff callq 41ddb0 <__cfree> - 43e5c0: 48 c7 43 28 c0 3f 4a movq $0x4a3fc0,0x28(%rbx) - 43e5c7: 00 - 43e5c8: e9 5b fe ff ff jmpq 43e428 <__wcsmbs_load_conv+0x28> - 43e5cd: 0f 1f 00 nopl (%rax) - 43e5d0: 4d 85 c9 test %r9,%r9 - 43e5d3: c6 00 2f movb $0x2f,(%rax) - 43e5d6: 74 1b je 43e5f3 <__wcsmbs_load_conv+0x1f3> - 43e5d8: 48 83 c0 01 add $0x1,%rax - 43e5dc: e9 17 ff ff ff jmpq 43e4f8 <__wcsmbs_load_conv+0xf8> - 43e5e1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43e5e8: 49 89 74 24 18 mov %rsi,0x18(%r12) - 43e5ed: 48 8b 45 d8 mov -0x28(%rbp),%rax - 43e5f1: eb a8 jmp 43e59b <__wcsmbs_load_conv+0x19b> - 43e5f3: c6 40 01 2f movb $0x2f,0x1(%rax) - 43e5f7: 48 83 c0 02 add $0x2,%rax - 43e5fb: 48 85 d2 test %rdx,%rdx - 43e5fe: 0f 84 f4 fe ff ff je 43e4f8 <__wcsmbs_load_conv+0xf8> - 43e604: 85 f6 test %esi,%esi - 43e606: b9 25 67 4b 00 mov $0x4b6725,%ecx - 43e60b: be b1 3f 4a 00 mov $0x4a3fb1,%esi - 43e610: 48 0f 44 f1 cmove %rcx,%rsi - 43e614: 48 89 c7 mov %rax,%rdi - 43e617: e8 a4 7f fe ff callq 4265c0 <__mempcpy> - 43e61c: e9 d7 fe ff ff jmpq 43e4f8 <__wcsmbs_load_conv+0xf8> - 43e621: 49 c7 04 24 00 00 00 movq $0x0,(%r12) - 43e628: 00 - 43e629: 49 83 7c 24 10 00 cmpq $0x0,0x10(%r12) - 43e62f: 0f 85 09 ff ff ff jne 43e53e <__wcsmbs_load_conv+0x13e> - 43e635: eb 81 jmp 43e5b8 <__wcsmbs_load_conv+0x1b8> - 43e637: 4c 89 e8 mov %r13,%rax - 43e63a: e9 af fe ff ff jmpq 43e4ee <__wcsmbs_load_conv+0xee> - 43e63f: 31 c0 xor %eax,%eax - 43e641: e9 55 ff ff ff jmpq 43e59b <__wcsmbs_load_conv+0x19b> - 43e646: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43e64d: 00 00 00 - -000000000043e650 <__wcsmbs_clone_conv>: - 43e650: 55 push %rbp - 43e651: 53 push %rbx - 43e652: 48 89 fb mov %rdi,%rbx - 43e655: 48 83 ec 08 sub $0x8,%rsp - 43e659: 48 c7 c0 b0 ff ff ff mov $0xffffffffffffffb0,%rax - 43e660: 64 48 8b 00 mov %fs:(%rax),%rax - 43e664: 48 8b 28 mov (%rax),%rbp - 43e667: 48 8b 45 28 mov 0x28(%rbp),%rax - 43e66b: 48 85 c0 test %rax,%rax - 43e66e: 74 40 je 43e6b0 <__wcsmbs_clone_conv+0x60> - 43e670: 48 8b 10 mov (%rax),%rdx - 43e673: 48 89 13 mov %rdx,(%rbx) - 43e676: 48 8b 48 08 mov 0x8(%rax),%rcx - 43e67a: 48 83 3a 00 cmpq $0x0,(%rdx) - 43e67e: 48 89 4b 08 mov %rcx,0x8(%rbx) - 43e682: 48 8b 48 10 mov 0x10(%rax),%rcx - 43e686: 48 89 4b 10 mov %rcx,0x10(%rbx) - 43e68a: 48 8b 40 18 mov 0x18(%rax),%rax - 43e68e: 48 89 43 18 mov %rax,0x18(%rbx) - 43e692: 74 04 je 43e698 <__wcsmbs_clone_conv+0x48> - 43e694: 83 42 10 01 addl $0x1,0x10(%rdx) - 43e698: 48 8b 43 10 mov 0x10(%rbx),%rax - 43e69c: 48 83 38 00 cmpq $0x0,(%rax) - 43e6a0: 74 04 je 43e6a6 <__wcsmbs_clone_conv+0x56> - 43e6a2: 83 40 10 01 addl $0x1,0x10(%rax) - 43e6a6: 48 83 c4 08 add $0x8,%rsp - 43e6aa: 5b pop %rbx - 43e6ab: 5d pop %rbp - 43e6ac: c3 retq - 43e6ad: 0f 1f 00 nopl (%rax) - 43e6b0: 48 81 fd e0 69 4a 00 cmp $0x4a69e0,%rbp - 43e6b7: b8 c0 3f 4a 00 mov $0x4a3fc0,%eax - 43e6bc: 74 b2 je 43e670 <__wcsmbs_clone_conv+0x20> - 43e6be: 48 89 ef mov %rbp,%rdi - 43e6c1: e8 3a fd ff ff callq 43e400 <__wcsmbs_load_conv> - 43e6c6: 48 8b 45 28 mov 0x28(%rbp),%rax - 43e6ca: eb a4 jmp 43e670 <__wcsmbs_clone_conv+0x20> - 43e6cc: 0f 1f 40 00 nopl 0x0(%rax) - -000000000043e6d0 <__wcsmbs_named_conv>: - 43e6d0: 55 push %rbp - 43e6d1: 53 push %rbx - 43e6d2: 45 31 c0 xor %r8d,%r8d - 43e6d5: 48 89 fb mov %rdi,%rbx - 43e6d8: bf 6d 52 4a 00 mov $0x4a526d,%edi - 43e6dd: 48 89 f5 mov %rsi,%rbp - 43e6e0: 48 83 ec 18 sub $0x18,%rsp - 43e6e4: 48 8d 54 24 08 lea 0x8(%rsp),%rdx - 43e6e9: 48 89 e1 mov %rsp,%rcx - 43e6ec: e8 1f 6f 00 00 callq 445610 <__gconv_find_transform> - 43e6f1: 85 c0 test %eax,%eax - 43e6f3: 0f 85 a7 00 00 00 jne 43e7a0 <__wcsmbs_named_conv+0xd0> - 43e6f9: 48 8b 34 24 mov (%rsp),%rsi - 43e6fd: 48 83 fe 01 cmp $0x1,%rsi - 43e701: 76 1d jbe 43e720 <__wcsmbs_named_conv+0x50> - 43e703: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi - 43e708: e8 e3 71 00 00 callq 4458f0 <__gconv_close_transform> - 43e70d: 48 c7 03 00 00 00 00 movq $0x0,(%rbx) - 43e714: b8 01 00 00 00 mov $0x1,%eax - 43e719: 48 83 c4 18 add $0x18,%rsp - 43e71d: 5b pop %rbx - 43e71e: 5d pop %rbp - 43e71f: c3 retq - 43e720: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 43e725: 48 89 73 08 mov %rsi,0x8(%rbx) - 43e729: 48 85 c0 test %rax,%rax - 43e72c: 48 89 03 mov %rax,(%rbx) - 43e72f: 74 76 je 43e7a7 <__wcsmbs_named_conv+0xd7> - 43e731: 48 8d 54 24 08 lea 0x8(%rsp),%rdx - 43e736: 45 31 c0 xor %r8d,%r8d - 43e739: 48 89 e1 mov %rsp,%rcx - 43e73c: be 6d 52 4a 00 mov $0x4a526d,%esi - 43e741: 48 89 ef mov %rbp,%rdi - 43e744: e8 c7 6e 00 00 callq 445610 <__gconv_find_transform> - 43e749: 85 c0 test %eax,%eax - 43e74b: 75 6b jne 43e7b8 <__wcsmbs_named_conv+0xe8> - 43e74d: 48 8b 34 24 mov (%rsp),%rsi - 43e751: 48 83 fe 01 cmp $0x1,%rsi - 43e755: 76 29 jbe 43e780 <__wcsmbs_named_conv+0xb0> - 43e757: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi - 43e75c: e8 8f 71 00 00 callq 4458f0 <__gconv_close_transform> - 43e761: 48 c7 43 10 00 00 00 movq $0x0,0x10(%rbx) - 43e768: 00 - 43e769: 48 8b 73 08 mov 0x8(%rbx),%rsi - 43e76d: 48 8b 3b mov (%rbx),%rdi - 43e770: e8 7b 71 00 00 callq 4458f0 <__gconv_close_transform> - 43e775: b8 01 00 00 00 mov $0x1,%eax - 43e77a: eb 9d jmp 43e719 <__wcsmbs_named_conv+0x49> - 43e77c: 0f 1f 40 00 nopl 0x0(%rax) - 43e780: 48 8b 54 24 08 mov 0x8(%rsp),%rdx - 43e785: 48 89 73 18 mov %rsi,0x18(%rbx) - 43e789: 48 85 d2 test %rdx,%rdx - 43e78c: 48 89 53 10 mov %rdx,0x10(%rbx) - 43e790: 74 d7 je 43e769 <__wcsmbs_named_conv+0x99> - 43e792: 48 83 c4 18 add $0x18,%rsp - 43e796: 5b pop %rbx - 43e797: 5d pop %rbp - 43e798: c3 retq - 43e799: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43e7a0: 48 c7 03 00 00 00 00 movq $0x0,(%rbx) - 43e7a7: 48 83 c4 18 add $0x18,%rsp - 43e7ab: b8 01 00 00 00 mov $0x1,%eax - 43e7b0: 5b pop %rbx - 43e7b1: 5d pop %rbp - 43e7b2: c3 retq - 43e7b3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43e7b8: 48 c7 43 10 00 00 00 movq $0x0,0x10(%rbx) - 43e7bf: 00 - 43e7c0: eb a7 jmp 43e769 <__wcsmbs_named_conv+0x99> - 43e7c2: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43e7c9: 00 00 00 - 43e7cc: 0f 1f 40 00 nopl 0x0(%rax) - -000000000043e7d0 <_exit>: - 43e7d0: 48 63 d7 movslq %edi,%rdx - 43e7d3: 49 c7 c1 d0 ff ff ff mov $0xffffffffffffffd0,%r9 - 43e7da: 41 b8 e7 00 00 00 mov $0xe7,%r8d - 43e7e0: be 3c 00 00 00 mov $0x3c,%esi - 43e7e5: eb 19 jmp 43e800 <_exit+0x30> - 43e7e7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 43e7ee: 00 00 - 43e7f0: 48 89 d7 mov %rdx,%rdi - 43e7f3: 89 f0 mov %esi,%eax - 43e7f5: 0f 05 syscall - 43e7f7: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 43e7fd: 77 21 ja 43e820 <_exit+0x50> - 43e7ff: f4 hlt - 43e800: 48 89 d7 mov %rdx,%rdi - 43e803: 44 89 c0 mov %r8d,%eax - 43e806: 0f 05 syscall - 43e808: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 43e80e: 76 e0 jbe 43e7f0 <_exit+0x20> - 43e810: f7 d8 neg %eax - 43e812: 64 41 89 01 mov %eax,%fs:(%r9) - 43e816: eb d8 jmp 43e7f0 <_exit+0x20> - 43e818: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 43e81f: 00 - 43e820: f7 d8 neg %eax - 43e822: 64 41 89 01 mov %eax,%fs:(%r9) - 43e826: eb d7 jmp 43e7ff <_exit+0x2f> - 43e828: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 43e82f: 00 - -000000000043e830 <__sysconf_check_spec>: - 43e830: 55 push %rbp - 43e831: 48 89 e5 mov %rsp,%rbp - 43e834: 41 57 push %r15 - 43e836: 41 56 push %r14 - 43e838: 41 55 push %r13 - 43e83a: 41 54 push %r12 - 43e83c: 49 89 fd mov %rdi,%r13 - 43e83f: 53 push %rbx - 43e840: bf d9 40 4a 00 mov $0x4a40d9,%edi - 43e845: 48 81 ec 98 00 00 00 sub $0x98,%rsp - 43e84c: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 43e853: 64 44 8b 20 mov %fs:(%rax),%r12d - 43e857: e8 44 31 01 00 callq 4519a0 <__libc_secure_getenv> - 43e85c: 48 85 c0 test %rax,%rax - 43e85f: 0f 84 9b 00 00 00 je 43e900 <__sysconf_check_spec+0xd0> - 43e865: 48 89 c7 mov %rax,%rdi - 43e868: 49 89 c7 mov %rax,%r15 - 43e86b: e8 e0 4d fe ff callq 423650 - 43e870: 48 89 c3 mov %rax,%rbx - 43e873: 4c 89 ef mov %r13,%rdi - 43e876: e8 d5 4d fe ff callq 423650 - 43e87b: 49 89 c6 mov %rax,%r14 - 43e87e: 48 8d 44 03 1a lea 0x1a(%rbx,%rax,1),%rax - 43e883: 48 89 da mov %rbx,%rdx - 43e886: 4c 89 fe mov %r15,%rsi - 43e889: 48 83 e0 f0 and $0xfffffffffffffff0,%rax - 43e88d: 48 29 c4 sub %rax,%rsp - 43e890: 48 89 e7 mov %rsp,%rdi - 43e893: e8 28 7d fe ff callq 4265c0 <__mempcpy> - 43e898: ba 36 5f 00 00 mov $0x5f36,%edx - 43e89d: 48 b9 2f 50 4f 53 49 movabs $0x565f5849534f502f,%rcx - 43e8a4: 58 5f 56 - 43e8a7: 48 8d 78 0a lea 0xa(%rax),%rdi - 43e8ab: 66 89 50 08 mov %dx,0x8(%rax) - 43e8af: 49 8d 56 01 lea 0x1(%r14),%rdx - 43e8b3: 48 89 08 mov %rcx,(%rax) - 43e8b6: 4c 89 ee mov %r13,%rsi - 43e8b9: e8 62 d7 fe ff callq 42c020 - 43e8be: 48 8d 95 40 ff ff ff lea -0xc0(%rbp),%rdx - 43e8c5: 48 89 e6 mov %rsp,%rsi - 43e8c8: bf 01 00 00 00 mov $0x1,%edi - 43e8cd: e8 ae 07 00 00 callq 43f080 <__xstat> - 43e8d2: 48 c7 c1 d0 ff ff ff mov $0xffffffffffffffd0,%rcx - 43e8d9: 48 98 cltq - 43e8db: 48 c1 f8 3f sar $0x3f,%rax - 43e8df: 48 83 c8 01 or $0x1,%rax - 43e8e3: 64 44 89 21 mov %r12d,%fs:(%rcx) - 43e8e7: 48 8d 65 d8 lea -0x28(%rbp),%rsp - 43e8eb: 5b pop %rbx - 43e8ec: 41 5c pop %r12 - 43e8ee: 41 5d pop %r13 - 43e8f0: 41 5e pop %r14 - 43e8f2: 41 5f pop %r15 - 43e8f4: 5d pop %rbp - 43e8f5: c3 retq - 43e8f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43e8fd: 00 00 00 - 43e900: bb 10 00 00 00 mov $0x10,%ebx - 43e905: 41 bf c8 40 4a 00 mov $0x4a40c8,%r15d - 43e90b: e9 63 ff ff ff jmpq 43e873 <__sysconf_check_spec+0x43> - -000000000043e910 <__sysconf>: - 43e910: 55 push %rbp - 43e911: 53 push %rbx - 43e912: 89 fb mov %edi,%ebx - 43e914: 8d 83 47 ff ff ff lea -0xb9(%rbx),%eax - 43e91a: 48 83 ec 38 sub $0x38,%rsp - 43e91e: 83 f8 0e cmp $0xe,%eax - 43e921: 0f 86 19 01 00 00 jbe 43ea40 <__sysconf+0x130> - 43e927: 83 fb 22 cmp $0x22,%ebx - 43e92a: 0f 84 80 01 00 00 je 43eab0 <__sysconf+0x1a0> - 43e930: 0f 8f ba 00 00 00 jg 43e9f0 <__sysconf+0xe0> - 43e936: 85 db test %ebx,%ebx - 43e938: 0f 84 12 01 00 00 je 43ea50 <__sysconf+0x140> - 43e93e: 83 fb 03 cmp $0x3,%ebx - 43e941: bf 00 41 4a 00 mov $0x4a4100,%edi - 43e946: 0f 85 8c 00 00 00 jne 43e9d8 <__sysconf+0xc8> - 43e94c: 31 f6 xor %esi,%esi - 43e94e: b8 02 00 00 00 mov $0x2,%eax - 43e953: 0f 05 syscall - 43e955: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 43e95b: 0f 87 b7 06 00 00 ja 43f018 <__sysconf+0x708> - 43e961: 83 f8 ff cmp $0xffffffff,%eax - 43e964: 74 72 je 43e9d8 <__sysconf+0xc8> - 43e966: 48 8d 6c 24 10 lea 0x10(%rsp),%rbp - 43e96b: 4c 63 c0 movslq %eax,%r8 - 43e96e: 45 31 c9 xor %r9d,%r9d - 43e971: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43e978: ba 1f 00 00 00 mov $0x1f,%edx - 43e97d: 48 89 ee mov %rbp,%rsi - 43e980: 4c 89 c7 mov %r8,%rdi - 43e983: 44 89 c8 mov %r9d,%eax - 43e986: 0f 05 syscall - 43e988: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 43e98e: 0f 87 f4 00 00 00 ja 43ea88 <__sysconf+0x178> - 43e994: 48 89 c2 mov %rax,%rdx - 43e997: 4c 89 c7 mov %r8,%rdi - 43e99a: b8 03 00 00 00 mov $0x3,%eax - 43e99f: 0f 05 syscall - 43e9a1: 48 85 d2 test %rdx,%rdx - 43e9a4: 7e 32 jle 43e9d8 <__sysconf+0xc8> - 43e9a6: 48 8d 74 24 08 lea 0x8(%rsp),%rsi - 43e9ab: c6 44 14 10 00 movb $0x0,0x10(%rsp,%rdx,1) - 43e9b0: 48 89 ef mov %rbp,%rdi - 43e9b3: ba 0a 00 00 00 mov $0xa,%edx - 43e9b8: e8 13 30 01 00 callq 4519d0 <__strtol> - 43e9bd: 48 8b 54 24 08 mov 0x8(%rsp),%rdx - 43e9c2: 48 39 ea cmp %rbp,%rdx - 43e9c5: 74 11 je 43e9d8 <__sysconf+0xc8> - 43e9c7: 0f b6 12 movzbl (%rdx),%edx - 43e9ca: 84 d2 test %dl,%dl - 43e9cc: 74 61 je 43ea2f <__sysconf+0x11f> - 43e9ce: 80 fa 0a cmp $0xa,%dl - 43e9d1: 74 5c je 43ea2f <__sysconf+0x11f> - 43e9d3: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43e9d8: 81 fb f6 00 00 00 cmp $0xf6,%ebx - 43e9de: 0f 87 17 06 00 00 ja 43effb <__sysconf+0x6eb> - 43e9e4: ff 24 dd 38 41 4a 00 jmpq *0x4a4138(,%rbx,8) - 43e9eb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43e9f0: 81 fb 8a 00 00 00 cmp $0x8a,%ebx - 43e9f6: 7c e0 jl 43e9d8 <__sysconf+0xc8> - 43e9f8: 81 fb 8b 00 00 00 cmp $0x8b,%ebx - 43e9fe: b8 69 10 03 00 mov $0x31069,%eax - 43ea03: 7e 2a jle 43ea2f <__sysconf+0x11f> - 43ea05: 81 fb 95 00 00 00 cmp $0x95,%ebx - 43ea0b: 75 cb jne 43e9d8 <__sysconf+0xc8> - 43ea0d: 48 8d 74 24 10 lea 0x10(%rsp),%rsi - 43ea12: bf 01 00 00 00 mov $0x1,%edi - 43ea17: b8 e5 00 00 00 mov $0xe5,%eax - 43ea1c: 0f 05 syscall - 43ea1e: 3d 01 f0 ff ff cmp $0xfffff001,%eax - 43ea23: 48 19 c0 sbb %rax,%rax - 43ea26: 25 6a 10 03 00 and $0x3106a,%eax - 43ea2b: 48 83 e8 01 sub $0x1,%rax - 43ea2f: 48 83 c4 38 add $0x38,%rsp - 43ea33: 5b pop %rbx - 43ea34: 5d pop %rbp - 43ea35: c3 retq - 43ea36: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43ea3d: 00 00 00 - 43ea40: 89 df mov %ebx,%edi - 43ea42: e8 89 f8 ff ff callq 43e2d0 <__cache_sysconf> - 43ea47: 48 83 c4 38 add $0x38,%rsp - 43ea4b: 5b pop %rbx - 43ea4c: 5d pop %rbp - 43ea4d: c3 retq - 43ea4e: 66 90 xchg %ax,%ax - 43ea50: 48 8d 74 24 10 lea 0x10(%rsp),%rsi - 43ea55: bf 03 00 00 00 mov $0x3,%edi - 43ea5a: e8 71 10 00 00 callq 43fad0 <__getrlimit> - 43ea5f: 89 c2 mov %eax,%edx - 43ea61: b8 00 00 02 00 mov $0x20000,%eax - 43ea66: 85 d2 test %edx,%edx - 43ea68: 75 c5 jne 43ea2f <__sysconf+0x11f> - 43ea6a: 48 8b 54 24 10 mov 0x10(%rsp),%rdx - 43ea6f: 48 89 d1 mov %rdx,%rcx - 43ea72: 48 c1 e9 02 shr $0x2,%rcx - 43ea76: 48 81 fa 00 00 08 00 cmp $0x80000,%rdx - 43ea7d: 48 0f 43 c1 cmovae %rcx,%rax - 43ea81: eb ac jmp 43ea2f <__sysconf+0x11f> - 43ea83: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43ea88: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx - 43ea8f: f7 d8 neg %eax - 43ea91: 83 f8 04 cmp $0x4,%eax - 43ea94: 64 89 02 mov %eax,%fs:(%rdx) - 43ea97: 0f 84 db fe ff ff je 43e978 <__sysconf+0x68> - 43ea9d: 48 c7 c2 ff ff ff ff mov $0xffffffffffffffff,%rdx - 43eaa4: e9 ee fe ff ff jmpq 43e997 <__sysconf+0x87> - 43eaa9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43eab0: 48 8d 74 24 10 lea 0x10(%rsp),%rsi - 43eab5: bf 0b 00 00 00 mov $0xb,%edi - 43eaba: e8 11 10 00 00 callq 43fad0 <__getrlimit> - 43eabf: 85 c0 test %eax,%eax - 43eac1: 75 0d jne 43ead0 <__sysconf+0x1c0> - 43eac3: 48 8b 44 24 10 mov 0x10(%rsp),%rax - 43eac8: e9 62 ff ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eacd: 0f 1f 00 nopl (%rax) - 43ead0: bf e5 40 4a 00 mov $0x4a40e5,%edi - 43ead5: e9 72 fe ff ff jmpq 43e94c <__sysconf+0x3c> - 43eada: b8 ff ff ff 7f mov $0x7fffffff,%eax - 43eadf: e9 4b ff ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eae4: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax - 43eaeb: e9 3f ff ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eaf0: e8 5b 05 00 00 callq 43f050 <__get_child_max> - 43eaf5: e9 35 ff ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eafa: e8 c1 39 00 00 callq 4424c0 <__getclktck> - 43eaff: 48 98 cltq - 43eb01: e9 29 ff ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eb06: b8 00 00 01 00 mov $0x10000,%eax - 43eb0b: e9 1f ff ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eb10: e8 ab 10 00 00 callq 43fbc0 <__getdtablesize> - 43eb15: 48 98 cltq - 43eb17: e9 13 ff ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eb1c: b8 10 00 00 00 mov $0x10,%eax - 43eb21: e9 09 ff ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eb26: e8 b5 90 02 00 callq 467be0 <__tzname_max> - 43eb2b: 48 89 c2 mov %rax,%rdx - 43eb2e: b8 06 00 00 00 mov $0x6,%eax - 43eb33: 48 83 fa 06 cmp $0x6,%rdx - 43eb37: 0f 8e f2 fe ff ff jle 43ea2f <__sysconf+0x11f> - 43eb3d: e8 9e 90 02 00 callq 467be0 <__tzname_max> - 43eb42: e9 e8 fe ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eb47: b8 01 00 00 00 mov $0x1,%eax - 43eb4c: e9 de fe ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eb51: b8 01 00 00 00 mov $0x1,%eax - 43eb56: e9 d4 fe ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eb5b: b8 69 10 03 00 mov $0x31069,%eax - 43eb60: e9 ca fe ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eb65: b8 69 10 03 00 mov $0x31069,%eax - 43eb6a: e9 c0 fe ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eb6f: b8 69 10 03 00 mov $0x31069,%eax - 43eb74: e9 b6 fe ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eb79: b8 69 10 03 00 mov $0x31069,%eax - 43eb7e: e9 ac fe ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eb83: b8 69 10 03 00 mov $0x31069,%eax - 43eb88: e9 a2 fe ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eb8d: b8 69 10 03 00 mov $0x31069,%eax - 43eb92: e9 98 fe ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eb97: b8 69 10 03 00 mov $0x31069,%eax - 43eb9c: e9 8e fe ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eba1: b8 69 10 03 00 mov $0x31069,%eax - 43eba6: e9 84 fe ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ebab: b8 69 10 03 00 mov $0x31069,%eax - 43ebb0: e9 7a fe ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ebb5: b8 69 10 03 00 mov $0x31069,%eax - 43ebba: e9 70 fe ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ebbf: b8 69 10 03 00 mov $0x31069,%eax - 43ebc4: e9 66 fe ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ebc9: b8 69 10 03 00 mov $0x31069,%eax - 43ebce: e9 5c fe ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ebd3: b8 69 10 03 00 mov $0x31069,%eax - 43ebd8: e9 52 fe ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ebdd: b8 69 10 03 00 mov $0x31069,%eax - 43ebe2: e9 48 fe ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ebe7: bf 29 41 4a 00 mov $0x4a4129,%edi - 43ebec: e8 3f fc ff ff callq 43e830 <__sysconf_check_spec> - 43ebf1: e9 39 fe ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ebf6: b8 01 00 00 00 mov $0x1,%eax - 43ebfb: e9 2f fe ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ec00: b8 14 00 00 00 mov $0x14,%eax - 43ec05: e9 25 fe ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ec0a: b8 ff ff ff 7f mov $0x7fffffff,%eax - 43ec0f: e9 1b fe ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ec14: b8 01 00 00 00 mov $0x1,%eax - 43ec19: e9 11 fe ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ec1e: b8 00 80 00 00 mov $0x8000,%eax - 43ec23: e9 07 fe ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ec28: b8 69 10 03 00 mov $0x31069,%eax - 43ec2d: e9 fd fd ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ec32: e8 59 0f 00 00 callq 43fb90 <__getpagesize> - 43ec37: 48 98 cltq - 43ec39: e9 f1 fd ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ec3e: b8 20 00 00 00 mov $0x20,%eax - 43ec43: e9 e7 fd ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ec48: bf 29 41 4a 00 mov $0x4a4129,%edi - 43ec4d: e8 de fb ff ff callq 43e830 <__sysconf_check_spec> - 43ec52: e9 d8 fd ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ec57: b8 ff ff ff 7f mov $0x7fffffff,%eax - 43ec5c: e9 ce fd ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ec61: bf 1d 41 4a 00 mov $0x4a411d,%edi - 43ec66: e8 c5 fb ff ff callq 43e830 <__sysconf_check_spec> - 43ec6b: e9 bf fd ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ec70: b8 69 10 03 00 mov $0x31069,%eax - 43ec75: e9 b5 fd ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ec7a: b8 63 00 00 00 mov $0x63,%eax - 43ec7f: e9 ab fd ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ec84: b8 00 08 00 00 mov $0x800,%eax - 43ec89: e9 a1 fd ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ec8e: b8 63 00 00 00 mov $0x63,%eax - 43ec93: e9 97 fd ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ec98: b8 e8 03 00 00 mov $0x3e8,%eax - 43ec9d: e9 8d fd ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eca2: b8 ff 00 00 00 mov $0xff,%eax - 43eca7: e9 83 fd ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ecac: b8 20 00 00 00 mov $0x20,%eax - 43ecb1: e9 79 fd ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ecb6: b8 00 08 00 00 mov $0x800,%eax - 43ecbb: e9 6f fd ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ecc0: b8 ff 7f 00 00 mov $0x7fff,%eax - 43ecc5: e9 65 fd ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ecca: b8 00 08 00 00 mov $0x800,%eax - 43eccf: e9 5b fd ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ecd4: b8 69 10 03 00 mov $0x31069,%eax - 43ecd9: e9 51 fd ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ecde: b8 69 10 03 00 mov $0x31069,%eax - 43ece3: e9 47 fd ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ece8: b8 69 10 03 00 mov $0x31069,%eax - 43eced: e9 3d fd ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ecf2: b8 69 10 03 00 mov $0x31069,%eax - 43ecf7: e9 33 fd ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ecfc: b8 69 10 03 00 mov $0x31069,%eax - 43ed01: e9 29 fd ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ed06: b8 69 10 03 00 mov $0x31069,%eax - 43ed0b: e9 1f fd ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ed10: b8 69 10 03 00 mov $0x31069,%eax - 43ed15: e9 15 fd ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ed1a: b8 69 10 03 00 mov $0x31069,%eax - 43ed1f: e9 0b fd ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ed24: bf 1d 41 4a 00 mov $0x4a411d,%edi - 43ed29: e8 02 fb ff ff callq 43e830 <__sysconf_check_spec> - 43ed2e: e9 fc fc ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ed33: b8 01 00 00 00 mov $0x1,%eax - 43ed38: e9 f2 fc ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ed3d: b8 69 10 03 00 mov $0x31069,%eax - 43ed42: e9 e8 fc ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ed47: b8 01 00 00 00 mov $0x1,%eax - 43ed4c: e9 de fc ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ed51: b8 01 00 00 00 mov $0x1,%eax - 43ed56: e9 d4 fc ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ed5b: b8 40 00 00 00 mov $0x40,%eax - 43ed60: e9 ca fc ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ed65: b8 00 04 00 00 mov $0x400,%eax - 43ed6a: e9 c0 fc ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ed6f: b8 69 10 03 00 mov $0x31069,%eax - 43ed74: e9 b6 fc ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ed79: b8 01 00 00 00 mov $0x1,%eax - 43ed7e: e9 ac fc ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ed83: bf 29 41 4a 00 mov $0x4a4129,%edi - 43ed88: e8 a3 fa ff ff callq 43e830 <__sysconf_check_spec> - 43ed8d: e9 9d fc ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ed92: bf 1d 41 4a 00 mov $0x4a411d,%edi - 43ed97: e8 94 fa ff ff callq 43e830 <__sysconf_check_spec> - 43ed9c: e9 8e fc ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eda1: b8 69 10 03 00 mov $0x31069,%eax - 43eda6: e9 84 fc ff ff jmpq 43ea2f <__sysconf+0x11f> - 43edab: b8 01 00 00 00 mov $0x1,%eax - 43edb0: e9 7a fc ff ff jmpq 43ea2f <__sysconf+0x11f> - 43edb5: b8 69 10 03 00 mov $0x31069,%eax - 43edba: e9 70 fc ff ff jmpq 43ea2f <__sysconf+0x11f> - 43edbf: b8 69 10 03 00 mov $0x31069,%eax - 43edc4: e9 66 fc ff ff jmpq 43ea2f <__sysconf+0x11f> - 43edc9: b8 00 04 00 00 mov $0x400,%eax - 43edce: e9 5c fc ff ff jmpq 43ea2f <__sysconf+0x11f> - 43edd3: b8 00 04 00 00 mov $0x400,%eax - 43edd8: e9 52 fc ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eddd: b8 00 01 00 00 mov $0x100,%eax - 43ede2: e9 48 fc ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ede7: b8 20 00 00 00 mov $0x20,%eax - 43edec: e9 3e fc ff ff jmpq 43ea2f <__sysconf+0x11f> - 43edf1: b8 04 00 00 00 mov $0x4,%eax - 43edf6: e9 34 fc ff ff jmpq 43ea2f <__sysconf+0x11f> - 43edfb: b8 00 04 00 00 mov $0x400,%eax - 43ee00: e9 2a fc ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ee05: b8 00 40 00 00 mov $0x4000,%eax - 43ee0a: e9 20 fc ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ee0f: b8 69 10 03 00 mov $0x31069,%eax - 43ee14: e9 16 fc ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ee19: b8 69 10 03 00 mov $0x31069,%eax - 43ee1e: e9 0c fc ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ee23: b8 69 10 03 00 mov $0x31069,%eax - 43ee28: e9 02 fc ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ee2d: b8 69 10 03 00 mov $0x31069,%eax - 43ee32: e9 f8 fb ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ee37: b8 69 10 03 00 mov $0x31069,%eax - 43ee3c: e9 ee fb ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ee41: b8 69 10 03 00 mov $0x31069,%eax - 43ee46: e9 e4 fb ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ee4b: b8 69 10 03 00 mov $0x31069,%eax - 43ee50: e9 da fb ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ee55: e8 e6 34 00 00 callq 442340 <__get_nprocs_conf> - 43ee5a: 48 98 cltq - 43ee5c: e9 ce fb ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ee61: e8 da 31 00 00 callq 442040 <__get_nprocs> - 43ee66: 48 98 cltq - 43ee68: e9 c2 fb ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ee6d: e8 6e 35 00 00 callq 4423e0 <__get_phys_pages> - 43ee72: e9 b8 fb ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ee77: e8 d4 35 00 00 callq 442450 <__get_avphys_pages> - 43ee7c: e9 ae fb ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ee81: b8 ff ff ff 7f mov $0x7fffffff,%eax - 43ee86: e9 a4 fb ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ee8b: b8 00 20 00 00 mov $0x2000,%eax - 43ee90: e9 9a fb ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ee95: b8 bc 02 00 00 mov $0x2bc,%eax - 43ee9a: e9 90 fb ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ee9f: b8 04 00 00 00 mov $0x4,%eax - 43eea4: e9 86 fb ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eea9: b8 01 00 00 00 mov $0x1,%eax - 43eeae: e9 7c fb ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eeb3: b8 01 00 00 00 mov $0x1,%eax - 43eeb8: e9 72 fb ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eebd: b8 01 00 00 00 mov $0x1,%eax - 43eec2: e9 68 fb ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eec7: b8 01 00 00 00 mov $0x1,%eax - 43eecc: e9 5e fb ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eed1: b8 69 10 03 00 mov $0x31069,%eax - 43eed6: e9 54 fb ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eedb: b8 69 10 03 00 mov $0x31069,%eax - 43eee0: e9 4a fb ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eee5: b8 01 00 00 00 mov $0x1,%eax - 43eeea: e9 40 fb ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eeef: b8 01 00 00 00 mov $0x1,%eax - 43eef4: e9 36 fb ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eef9: b8 01 00 00 00 mov $0x1,%eax - 43eefe: e9 2c fb ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ef03: b8 01 00 00 00 mov $0x1,%eax - 43ef08: e9 22 fb ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ef0d: b8 08 00 00 00 mov $0x8,%eax - 43ef12: e9 18 fb ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ef17: b8 7f 00 00 00 mov $0x7f,%eax - 43ef1c: e9 0e fb ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ef21: 48 c7 c0 80 ff ff ff mov $0xffffffffffffff80,%rax - 43ef28: e9 02 fb ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ef2d: b8 ff ff ff 7f mov $0x7fffffff,%eax - 43ef32: e9 f8 fa ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ef37: 48 c7 c0 00 00 00 80 mov $0xffffffff80000000,%rax - 43ef3e: e9 ec fa ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ef43: b8 40 00 00 00 mov $0x40,%eax - 43ef48: e9 e2 fa ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ef4d: b8 20 00 00 00 mov $0x20,%eax - 43ef52: e9 d8 fa ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ef57: b8 10 00 00 00 mov $0x10,%eax - 43ef5c: e9 ce fa ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ef61: b8 14 00 00 00 mov $0x14,%eax - 43ef66: e9 c4 fa ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ef6b: b8 ff 7f 00 00 mov $0x7fff,%eax - 43ef70: e9 ba fa ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ef75: b8 7f 00 00 00 mov $0x7f,%eax - 43ef7a: e9 b0 fa ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ef7f: 48 c7 c0 80 ff ff ff mov $0xffffffffffffff80,%rax - 43ef86: e9 a4 fa ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ef8b: b8 ff 7f 00 00 mov $0x7fff,%eax - 43ef90: e9 9a fa ff ff jmpq 43ea2f <__sysconf+0x11f> - 43ef95: 48 c7 c0 00 80 ff ff mov $0xffffffffffff8000,%rax - 43ef9c: e9 8e fa ff ff jmpq 43ea2f <__sysconf+0x11f> - 43efa1: b8 ff 00 00 00 mov $0xff,%eax - 43efa6: e9 84 fa ff ff jmpq 43ea2f <__sysconf+0x11f> - 43efab: b8 ff ff ff ff mov $0xffffffff,%eax - 43efb0: e9 7a fa ff ff jmpq 43ea2f <__sysconf+0x11f> - 43efb5: b8 69 10 03 00 mov $0x31069,%eax - 43efba: e9 70 fa ff ff jmpq 43ea2f <__sysconf+0x11f> - 43efbf: b8 ff ff 00 00 mov $0xffff,%eax - 43efc4: e9 66 fa ff ff jmpq 43ea2f <__sysconf+0x11f> - 43efc9: b8 00 10 00 00 mov $0x1000,%eax - 43efce: e9 5c fa ff ff jmpq 43ea2f <__sysconf+0x11f> - 43efd3: b8 00 08 00 00 mov $0x800,%eax - 43efd8: e9 52 fa ff ff jmpq 43ea2f <__sysconf+0x11f> - 43efdd: b8 ff ff ff 7f mov $0x7fffffff,%eax - 43efe2: e9 48 fa ff ff jmpq 43ea2f <__sysconf+0x11f> - 43efe7: b8 ff ff ff 7f mov $0x7fffffff,%eax - 43efec: e9 3e fa ff ff jmpq 43ea2f <__sysconf+0x11f> - 43eff1: b8 ff ff ff 7f mov $0x7fffffff,%eax - 43eff6: e9 34 fa ff ff jmpq 43ea2f <__sysconf+0x11f> - 43effb: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 43f002: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) - 43f009: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax - 43f010: e9 1a fa ff ff jmpq 43ea2f <__sysconf+0x11f> - 43f015: 0f 1f 00 nopl (%rax) - 43f018: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx - 43f01f: f7 d8 neg %eax - 43f021: 64 89 02 mov %eax,%fs:(%rdx) - 43f024: e9 af f9 ff ff jmpq 43e9d8 <__sysconf+0xc8> - 43f029: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - -000000000043f030 <__sched_yield>: - 43f030: b8 18 00 00 00 mov $0x18,%eax - 43f035: 0f 05 syscall - 43f037: 48 3d 01 f0 ff ff cmp $0xfffffffffffff001,%rax - 43f03d: 0f 83 0d 51 00 00 jae 444150 <__syscall_error> - 43f043: c3 retq - 43f044: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43f04b: 00 00 00 - 43f04e: 66 90 xchg %ax,%ax - -000000000043f050 <__get_child_max>: - 43f050: 48 83 ec 18 sub $0x18,%rsp - 43f054: bf 06 00 00 00 mov $0x6,%edi - 43f059: 48 89 e6 mov %rsp,%rsi - 43f05c: e8 6f 0a 00 00 callq 43fad0 <__getrlimit> - 43f061: 85 c0 test %eax,%eax - 43f063: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax - 43f06a: 48 0f 44 04 24 cmove (%rsp),%rax - 43f06f: 48 83 c4 18 add $0x18,%rsp - 43f073: c3 retq - 43f074: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43f07b: 00 00 00 - 43f07e: 66 90 xchg %ax,%ax - -000000000043f080 <__xstat>: - 43f080: 83 ff 01 cmp $0x1,%edi - 43f083: 48 89 f0 mov %rsi,%rax - 43f086: 77 30 ja 43f0b8 <__xstat+0x38> - 43f088: 48 89 c7 mov %rax,%rdi - 43f08b: 48 89 d6 mov %rdx,%rsi - 43f08e: b8 04 00 00 00 mov $0x4,%eax - 43f093: 0f 05 syscall - 43f095: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 43f09b: 77 03 ja 43f0a0 <__xstat+0x20> - 43f09d: f3 c3 repz retq - 43f09f: 90 nop - 43f0a0: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx - 43f0a7: f7 d8 neg %eax - 43f0a9: 64 89 02 mov %eax,%fs:(%rdx) - 43f0ac: b8 ff ff ff ff mov $0xffffffff,%eax - 43f0b1: c3 retq - 43f0b2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43f0b8: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 43f0bf: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) - 43f0c6: b8 ff ff ff ff mov $0xffffffff,%eax - 43f0cb: c3 retq - 43f0cc: 0f 1f 40 00 nopl 0x0(%rax) - -000000000043f0d0 <__fxstat>: - 43f0d0: 83 ff 01 cmp $0x1,%edi - 43f0d3: 89 f0 mov %esi,%eax - 43f0d5: 77 31 ja 43f108 <__fxstat+0x38> - 43f0d7: 48 63 f8 movslq %eax,%rdi - 43f0da: 48 89 d6 mov %rdx,%rsi - 43f0dd: b8 05 00 00 00 mov $0x5,%eax - 43f0e2: 0f 05 syscall - 43f0e4: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 43f0ea: 77 04 ja 43f0f0 <__fxstat+0x20> - 43f0ec: f3 c3 repz retq - 43f0ee: 66 90 xchg %ax,%ax - 43f0f0: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx - 43f0f7: f7 d8 neg %eax - 43f0f9: 64 89 02 mov %eax,%fs:(%rdx) - 43f0fc: b8 ff ff ff ff mov $0xffffffff,%eax - 43f101: c3 retq - 43f102: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43f108: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 43f10f: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) - 43f116: b8 ff ff ff ff mov $0xffffffff,%eax - 43f11b: c3 retq - 43f11c: 0f 1f 40 00 nopl 0x0(%rax) - -000000000043f120 <__libc_open>: - 43f120: 83 3d 95 e0 28 00 00 cmpl $0x0,0x28e095(%rip) # 6cd1bc <__libc_multiple_threads> - 43f127: 75 14 jne 43f13d <__open_nocancel+0x14> - -000000000043f129 <__open_nocancel>: - 43f129: b8 02 00 00 00 mov $0x2,%eax - 43f12e: 0f 05 syscall - 43f130: 48 3d 01 f0 ff ff cmp $0xfffffffffffff001,%rax - 43f136: 0f 83 14 50 00 00 jae 444150 <__syscall_error> - 43f13c: c3 retq - 43f13d: 48 83 ec 08 sub $0x8,%rsp - 43f141: e8 da 34 00 00 callq 442620 <__libc_enable_asynccancel> - 43f146: 48 89 04 24 mov %rax,(%rsp) - 43f14a: b8 02 00 00 00 mov $0x2,%eax - 43f14f: 0f 05 syscall - 43f151: 48 8b 3c 24 mov (%rsp),%rdi - 43f155: 48 89 c2 mov %rax,%rdx - 43f158: e8 23 35 00 00 callq 442680 <__libc_disable_asynccancel> - 43f15d: 48 89 d0 mov %rdx,%rax - 43f160: 48 83 c4 08 add $0x8,%rsp - 43f164: 48 3d 01 f0 ff ff cmp $0xfffffffffffff001,%rax - 43f16a: 0f 83 e0 4f 00 00 jae 444150 <__syscall_error> - 43f170: c3 retq - 43f171: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43f178: 00 00 00 - 43f17b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - -000000000043f180 <__libc_read>: - 43f180: 83 3d 35 e0 28 00 00 cmpl $0x0,0x28e035(%rip) # 6cd1bc <__libc_multiple_threads> - 43f187: 75 14 jne 43f19d <__read_nocancel+0x14> - -000000000043f189 <__read_nocancel>: - 43f189: b8 00 00 00 00 mov $0x0,%eax - 43f18e: 0f 05 syscall - 43f190: 48 3d 01 f0 ff ff cmp $0xfffffffffffff001,%rax - 43f196: 0f 83 b4 4f 00 00 jae 444150 <__syscall_error> - 43f19c: c3 retq - 43f19d: 48 83 ec 08 sub $0x8,%rsp - 43f1a1: e8 7a 34 00 00 callq 442620 <__libc_enable_asynccancel> - 43f1a6: 48 89 04 24 mov %rax,(%rsp) - 43f1aa: b8 00 00 00 00 mov $0x0,%eax - 43f1af: 0f 05 syscall - 43f1b1: 48 8b 3c 24 mov (%rsp),%rdi - 43f1b5: 48 89 c2 mov %rax,%rdx - 43f1b8: e8 c3 34 00 00 callq 442680 <__libc_disable_asynccancel> - 43f1bd: 48 89 d0 mov %rdx,%rax - 43f1c0: 48 83 c4 08 add $0x8,%rsp - 43f1c4: 48 3d 01 f0 ff ff cmp $0xfffffffffffff001,%rax - 43f1ca: 0f 83 80 4f 00 00 jae 444150 <__syscall_error> - 43f1d0: c3 retq - 43f1d1: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43f1d8: 00 00 00 - 43f1db: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - -000000000043f1e0 <__libc_write>: - 43f1e0: 83 3d d5 df 28 00 00 cmpl $0x0,0x28dfd5(%rip) # 6cd1bc <__libc_multiple_threads> - 43f1e7: 75 14 jne 43f1fd <__write_nocancel+0x14> - -000000000043f1e9 <__write_nocancel>: - 43f1e9: b8 01 00 00 00 mov $0x1,%eax - 43f1ee: 0f 05 syscall - 43f1f0: 48 3d 01 f0 ff ff cmp $0xfffffffffffff001,%rax - 43f1f6: 0f 83 54 4f 00 00 jae 444150 <__syscall_error> - 43f1fc: c3 retq - 43f1fd: 48 83 ec 08 sub $0x8,%rsp - 43f201: e8 1a 34 00 00 callq 442620 <__libc_enable_asynccancel> - 43f206: 48 89 04 24 mov %rax,(%rsp) - 43f20a: b8 01 00 00 00 mov $0x1,%eax - 43f20f: 0f 05 syscall - 43f211: 48 8b 3c 24 mov (%rsp),%rdi - 43f215: 48 89 c2 mov %rax,%rdx - 43f218: e8 63 34 00 00 callq 442680 <__libc_disable_asynccancel> - 43f21d: 48 89 d0 mov %rdx,%rax - 43f220: 48 83 c4 08 add $0x8,%rsp - 43f224: 48 3d 01 f0 ff ff cmp $0xfffffffffffff001,%rax - 43f22a: 0f 83 20 4f 00 00 jae 444150 <__syscall_error> - 43f230: c3 retq - 43f231: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43f238: 00 00 00 - 43f23b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - -000000000043f240 <__fcntl_nocancel>: - 43f240: 48 8d 44 24 08 lea 0x8(%rsp),%rax - 43f245: 83 fe 09 cmp $0x9,%esi - 43f248: 48 89 54 24 d8 mov %rdx,-0x28(%rsp) - 43f24d: c7 44 24 b0 10 00 00 movl $0x10,-0x50(%rsp) - 43f254: 00 - 43f255: 48 89 44 24 b8 mov %rax,-0x48(%rsp) - 43f25a: 48 8d 44 24 c8 lea -0x38(%rsp),%rax - 43f25f: 48 89 44 24 c0 mov %rax,-0x40(%rsp) - 43f264: 74 1a je 43f280 <__fcntl_nocancel+0x40> - 43f266: 48 63 f6 movslq %esi,%rsi - 43f269: 48 63 ff movslq %edi,%rdi - 43f26c: b8 48 00 00 00 mov $0x48,%eax - 43f271: 0f 05 syscall - 43f273: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 43f279: 77 35 ja 43f2b0 <__fcntl_nocancel+0x70> - 43f27b: f3 c3 repz retq - 43f27d: 0f 1f 00 nopl (%rax) - 43f280: 48 8d 54 24 a8 lea -0x58(%rsp),%rdx - 43f285: be 10 00 00 00 mov $0x10,%esi - 43f28a: 48 63 ff movslq %edi,%rdi - 43f28d: b8 48 00 00 00 mov $0x48,%eax - 43f292: 0f 05 syscall - 43f294: 3d 00 f0 ff ff cmp $0xfffff000,%eax - 43f299: 77 15 ja 43f2b0 <__fcntl_nocancel+0x70> - 43f29b: 8b 44 24 ac mov -0x54(%rsp),%eax - 43f29f: 89 c2 mov %eax,%edx - 43f2a1: f7 da neg %edx - 43f2a3: 83 7c 24 a8 02 cmpl $0x2,-0x58(%rsp) - 43f2a8: 0f 44 c2 cmove %edx,%eax - 43f2ab: c3 retq - 43f2ac: 0f 1f 40 00 nopl 0x0(%rax) - 43f2b0: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx - 43f2b7: f7 d8 neg %eax - 43f2b9: 64 89 02 mov %eax,%fs:(%rdx) - 43f2bc: b8 ff ff ff ff mov $0xffffffff,%eax - 43f2c1: c3 retq - 43f2c2: 0f 1f 40 00 nopl 0x0(%rax) - 43f2c6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43f2cd: 00 00 00 - -000000000043f2d0 <__libc_fcntl>: - 43f2d0: 53 push %rbx - 43f2d1: 48 83 ec 60 sub $0x60,%rsp - 43f2d5: 48 8d 44 24 70 lea 0x70(%rsp),%rax - 43f2da: 48 89 54 24 40 mov %rdx,0x40(%rsp) - 43f2df: c7 44 24 18 10 00 00 movl $0x10,0x18(%rsp) - 43f2e6: 00 - 43f2e7: 48 89 44 24 20 mov %rax,0x20(%rsp) - 43f2ec: 48 8d 44 24 30 lea 0x30(%rsp),%rax - 43f2f1: 48 89 44 24 28 mov %rax,0x28(%rsp) - 43f2f6: 8b 05 c0 de 28 00 mov 0x28dec0(%rip),%eax # 6cd1bc <__libc_multiple_threads> - 43f2fc: 85 c0 test %eax,%eax - 43f2fe: 74 05 je 43f305 <__libc_fcntl+0x35> - 43f300: 83 fe 07 cmp $0x7,%esi - 43f303: 74 73 je 43f378 <__libc_fcntl+0xa8> - 43f305: 83 fe 09 cmp $0x9,%esi - 43f308: 74 1e je 43f328 <__libc_fcntl+0x58> - 43f30a: 48 63 f6 movslq %esi,%rsi - 43f30d: 48 63 ff movslq %edi,%rdi - 43f310: b8 48 00 00 00 mov $0x48,%eax - 43f315: 0f 05 syscall - 43f317: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 43f31d: 77 41 ja 43f360 <__libc_fcntl+0x90> - 43f31f: 48 83 c4 60 add $0x60,%rsp - 43f323: 5b pop %rbx - 43f324: c3 retq - 43f325: 0f 1f 00 nopl (%rax) - 43f328: 48 8d 54 24 10 lea 0x10(%rsp),%rdx - 43f32d: be 10 00 00 00 mov $0x10,%esi - 43f332: 48 63 ff movslq %edi,%rdi - 43f335: b8 48 00 00 00 mov $0x48,%eax - 43f33a: 0f 05 syscall - 43f33c: 3d 00 f0 ff ff cmp $0xfffff000,%eax - 43f341: 77 1d ja 43f360 <__libc_fcntl+0x90> - 43f343: 8b 44 24 14 mov 0x14(%rsp),%eax - 43f347: 89 c2 mov %eax,%edx - 43f349: f7 da neg %edx - 43f34b: 83 7c 24 10 02 cmpl $0x2,0x10(%rsp) - 43f350: 0f 44 c2 cmove %edx,%eax - 43f353: 48 83 c4 60 add $0x60,%rsp - 43f357: 5b pop %rbx - 43f358: c3 retq - 43f359: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43f360: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx - 43f367: f7 d8 neg %eax - 43f369: 64 89 02 mov %eax,%fs:(%rdx) - 43f36c: b8 ff ff ff ff mov $0xffffffff,%eax - 43f371: eb ac jmp 43f31f <__libc_fcntl+0x4f> - 43f373: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43f378: 89 fb mov %edi,%ebx - 43f37a: 48 89 54 24 08 mov %rdx,0x8(%rsp) - 43f37f: e8 9c 32 00 00 callq 442620 <__libc_enable_asynccancel> - 43f384: 48 8b 54 24 08 mov 0x8(%rsp),%rdx - 43f389: 41 89 c0 mov %eax,%r8d - 43f38c: be 07 00 00 00 mov $0x7,%esi - 43f391: 48 63 fb movslq %ebx,%rdi - 43f394: b8 48 00 00 00 mov $0x48,%eax - 43f399: 0f 05 syscall - 43f39b: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 43f3a1: 77 15 ja 43f3b8 <__libc_fcntl+0xe8> - 43f3a3: 44 89 c7 mov %r8d,%edi - 43f3a6: 89 44 24 08 mov %eax,0x8(%rsp) - 43f3aa: e8 d1 32 00 00 callq 442680 <__libc_disable_asynccancel> - 43f3af: 8b 44 24 08 mov 0x8(%rsp),%eax - 43f3b3: e9 67 ff ff ff jmpq 43f31f <__libc_fcntl+0x4f> - 43f3b8: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx - 43f3bf: f7 d8 neg %eax - 43f3c1: 64 89 02 mov %eax,%fs:(%rdx) - 43f3c4: b8 ff ff ff ff mov $0xffffffff,%eax - 43f3c9: eb d8 jmp 43f3a3 <__libc_fcntl+0xd3> - 43f3cb: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - -000000000043f3d0 <__getcwd>: - 43f3d0: 41 57 push %r15 - 43f3d2: 41 56 push %r14 - 43f3d4: 49 89 f6 mov %rsi,%r14 - 43f3d7: 41 55 push %r13 - 43f3d9: 41 54 push %r12 - 43f3db: 55 push %rbp - 43f3dc: 53 push %rbx - 43f3dd: 48 89 fb mov %rdi,%rbx - 43f3e0: 48 81 ec f8 00 00 00 sub $0xf8,%rsp - 43f3e7: 48 85 f6 test %rsi,%rsi - 43f3ea: 75 5c jne 43f448 <__getcwd+0x78> - 43f3ec: 48 85 ff test %rdi,%rdi - 43f3ef: 0f 85 2b 04 00 00 jne 43f820 <__getcwd+0x450> - 43f3f5: e8 96 07 00 00 callq 43fb90 <__getpagesize> - 43f3fa: be 00 10 00 00 mov $0x1000,%esi - 43f3ff: 3d 00 10 00 00 cmp $0x1000,%eax - 43f404: 0f 4d f0 cmovge %eax,%esi - 43f407: 48 63 f6 movslq %esi,%rsi - 43f40a: 48 89 f7 mov %rsi,%rdi - 43f40d: 48 89 74 24 10 mov %rsi,0x10(%rsp) - 43f412: e8 f9 e5 fd ff callq 41da10 <__libc_malloc> - 43f417: 48 85 c0 test %rax,%rax - 43f41a: 48 89 44 24 08 mov %rax,0x8(%rsp) - 43f41f: 48 8b 74 24 10 mov 0x10(%rsp),%rsi - 43f424: 75 2c jne 43f452 <__getcwd+0x82> - 43f426: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43f42d: 00 00 00 - 43f430: 31 c0 xor %eax,%eax - 43f432: 48 81 c4 f8 00 00 00 add $0xf8,%rsp - 43f439: 5b pop %rbx - 43f43a: 5d pop %rbp - 43f43b: 41 5c pop %r12 - 43f43d: 41 5d pop %r13 - 43f43f: 41 5e pop %r14 - 43f441: 41 5f pop %r15 - 43f443: c3 retq - 43f444: 0f 1f 40 00 nopl 0x0(%rax) - 43f448: 48 85 ff test %rdi,%rdi - 43f44b: 74 bd je 43f40a <__getcwd+0x3a> - 43f44d: 48 89 7c 24 08 mov %rdi,0x8(%rsp) - 43f452: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi - 43f457: b8 4f 00 00 00 mov $0x4f,%eax - 43f45c: 0f 05 syscall - 43f45e: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 43f464: 0f 87 9d 04 00 00 ja 43f907 <__getcwd+0x537> - 43f46a: 83 f8 00 cmp $0x0,%eax - 43f46d: 0f 8e 3d 04 00 00 jle 43f8b0 <__getcwd+0x4e0> - 43f473: 48 8b 54 24 08 mov 0x8(%rsp),%rdx - 43f478: 80 3a 2f cmpb $0x2f,(%rdx) - 43f47b: 0f 84 b7 03 00 00 je 43f838 <__getcwd+0x468> - 43f481: 48 c7 c5 d0 ff ff ff mov $0xffffffffffffffd0,%rbp - 43f488: 48 85 db test %rbx,%rbx - 43f48b: 0f 94 44 24 43 sete 0x43(%rsp) - 43f490: 4d 85 f6 test %r14,%r14 - 43f493: 0f b6 44 24 43 movzbl 0x43(%rsp),%eax - 43f498: 75 08 jne 43f4a2 <__getcwd+0xd2> - 43f49a: 84 c0 test %al,%al - 43f49c: 0f 85 c6 03 00 00 jne 43f868 <__getcwd+0x498> - 43f4a2: 4d 85 f6 test %r14,%r14 - 43f4a5: 0f 84 45 04 00 00 je 43f8f0 <__getcwd+0x520> - 43f4ab: 64 8b 45 00 mov %fs:0x0(%rbp),%eax - 43f4af: 4c 89 74 24 28 mov %r14,0x28(%rsp) - 43f4b4: 89 44 24 44 mov %eax,0x44(%rsp) - 43f4b8: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 43f4bd: 48 89 44 24 20 mov %rax,0x20(%rsp) - 43f4c2: 48 89 c3 mov %rax,%rbx - 43f4c5: 48 03 5c 24 28 add 0x28(%rsp),%rbx - 43f4ca: 48 8d 54 24 60 lea 0x60(%rsp),%rdx - 43f4cf: be f1 48 4a 00 mov $0x4a48f1,%esi - 43f4d4: bf 01 00 00 00 mov $0x1,%edi - 43f4d9: 48 8d 43 ff lea -0x1(%rbx),%rax - 43f4dd: c6 43 ff 00 movb $0x0,-0x1(%rbx) - 43f4e1: 48 89 44 24 38 mov %rax,0x38(%rsp) - 43f4e6: e8 55 b4 02 00 callq 46a940 <__lxstat> - 43f4eb: 85 c0 test %eax,%eax - 43f4ed: 0f 88 23 04 00 00 js 43f916 <__getcwd+0x546> - 43f4f3: 48 8b 44 24 68 mov 0x68(%rsp),%rax - 43f4f8: 48 8d 54 24 60 lea 0x60(%rsp),%rdx - 43f4fd: be ae 48 4b 00 mov $0x4b48ae,%esi - 43f502: bf 01 00 00 00 mov $0x1,%edi - 43f507: 4c 8b 7c 24 60 mov 0x60(%rsp),%r15 - 43f50c: 49 89 c5 mov %rax,%r13 - 43f50f: 48 89 44 24 18 mov %rax,0x18(%rsp) - 43f514: e8 27 b4 02 00 callq 46a940 <__lxstat> - 43f519: 85 c0 test %eax,%eax - 43f51b: 0f 88 f5 03 00 00 js 43f916 <__getcwd+0x546> - 43f521: 48 8b 44 24 60 mov 0x60(%rsp),%rax - 43f526: 48 89 c1 mov %rax,%rcx - 43f529: 48 89 44 24 48 mov %rax,0x48(%rsp) - 43f52e: 48 8b 44 24 68 mov 0x68(%rsp),%rax - 43f533: 48 89 c2 mov %rax,%rdx - 43f536: 48 89 44 24 50 mov %rax,0x50(%rsp) - 43f53b: 49 39 d5 cmp %rdx,%r13 - 43f53e: 75 09 jne 43f549 <__getcwd+0x179> - 43f540: 49 39 cf cmp %rcx,%r15 - 43f543: 0f 84 00 04 00 00 je 43f949 <__getcwd+0x579> - 43f549: ba 00 00 08 00 mov $0x80000,%edx - 43f54e: be f0 48 4a 00 mov $0x4a48f0,%esi - 43f553: 48 c7 c7 9c ff ff ff mov $0xffffffffffffff9c,%rdi - 43f55a: b8 01 01 00 00 mov $0x101,%eax - 43f55f: 0f 05 syscall - 43f561: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 43f567: 0f 87 44 04 00 00 ja 43f9b1 <__getcwd+0x5e1> - 43f56d: 85 c0 test %eax,%eax - 43f56f: 89 44 24 10 mov %eax,0x10(%rsp) - 43f573: 0f 88 19 05 00 00 js 43fa92 <__getcwd+0x6c2> - 43f579: 45 31 e4 xor %r12d,%r12d - 43f57c: 4c 89 74 24 30 mov %r14,0x30(%rsp) - 43f581: 89 c6 mov %eax,%esi - 43f583: 48 8d 54 24 60 lea 0x60(%rsp),%rdx - 43f588: bf 01 00 00 00 mov $0x1,%edi - 43f58d: e8 3e fb ff ff callq 43f0d0 <__fxstat> - 43f592: 85 c0 test %eax,%eax - 43f594: 0f 88 75 04 00 00 js 43fa0f <__getcwd+0x63f> - 43f59a: 4d 85 e4 test %r12,%r12 - 43f59d: 74 10 je 43f5af <__getcwd+0x1df> - 43f59f: 4c 89 e7 mov %r12,%rdi - 43f5a2: e8 09 b0 02 00 callq 46a5b0 <__closedir> - 43f5a7: 85 c0 test %eax,%eax - 43f5a9: 0f 85 50 04 00 00 jne 43f9ff <__getcwd+0x62f> - 43f5af: 48 8b 44 24 68 mov 0x68(%rsp),%rax - 43f5b4: 8b 7c 24 10 mov 0x10(%rsp),%edi - 43f5b8: 4c 8b 74 24 60 mov 0x60(%rsp),%r14 - 43f5bd: 48 89 44 24 58 mov %rax,0x58(%rsp) - 43f5c2: e8 79 b2 02 00 callq 46a840 <__fdopendir> - 43f5c7: 48 85 c0 test %rax,%rax - 43f5ca: 49 89 c4 mov %rax,%r12 - 43f5cd: 75 2d jne 43f5fc <__getcwd+0x22c> - 43f5cf: e9 2b 04 00 00 jmpq 43f9ff <__getcwd+0x62f> - 43f5d4: 0f 1f 40 00 nopl 0x0(%rax) - 43f5d8: f6 40 12 fb testb $0xfb,0x12(%rax) - 43f5dc: 75 24 jne 43f602 <__getcwd+0x232> - 43f5de: 80 78 13 2e cmpb $0x2e,0x13(%rax) - 43f5e2: 0f 84 b0 01 00 00 je 43f798 <__getcwd+0x3c8> - 43f5e8: 4d 39 f7 cmp %r14,%r15 - 43f5eb: 75 53 jne 43f640 <__getcwd+0x270> - 43f5ed: 45 84 ed test %r13b,%r13b - 43f5f0: 74 4e je 43f640 <__getcwd+0x270> - 43f5f2: 48 8b 4c 24 18 mov 0x18(%rsp),%rcx - 43f5f7: 48 3b 08 cmp (%rax),%rcx - 43f5fa: 74 44 je 43f640 <__getcwd+0x270> - 43f5fc: 41 bd 01 00 00 00 mov $0x1,%r13d - 43f602: 4c 89 e7 mov %r12,%rdi - 43f605: 64 c7 45 00 00 00 00 movl $0x0,%fs:0x0(%rbp) - 43f60c: 00 - 43f60d: e8 fe af 02 00 callq 46a610 <__readdir> - 43f612: 48 85 c0 test %rax,%rax - 43f615: 75 c1 jne 43f5d8 <__getcwd+0x208> - 43f617: 64 8b 45 00 mov %fs:0x0(%rbp),%eax - 43f61b: 85 c0 test %eax,%eax - 43f61d: 0f 85 82 03 00 00 jne 43f9a5 <__getcwd+0x5d5> - 43f623: 45 84 ed test %r13b,%r13b - 43f626: 0f 84 8c 01 00 00 je 43f7b8 <__getcwd+0x3e8> - 43f62c: 4c 89 e7 mov %r12,%rdi - 43f62f: 45 31 ed xor %r13d,%r13d - 43f632: e8 d9 b0 02 00 callq 46a710 <__rewinddir> - 43f637: eb c9 jmp 43f602 <__getcwd+0x232> - 43f639: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43f640: 48 8d 58 13 lea 0x13(%rax),%rbx - 43f644: 8b 74 24 10 mov 0x10(%rsp),%esi - 43f648: 48 8d 4c 24 60 lea 0x60(%rsp),%rcx - 43f64d: 41 b8 00 01 00 00 mov $0x100,%r8d - 43f653: bf 01 00 00 00 mov $0x1,%edi - 43f658: 48 89 da mov %rbx,%rdx - 43f65b: e8 30 b3 02 00 callq 46a990 <__GI___fxstatat64> - 43f660: 85 c0 test %eax,%eax - 43f662: 78 9e js 43f602 <__getcwd+0x232> - 43f664: 8b 44 24 78 mov 0x78(%rsp),%eax - 43f668: 25 00 f0 00 00 and $0xf000,%eax - 43f66d: 3d 00 40 00 00 cmp $0x4000,%eax - 43f672: 75 8e jne 43f602 <__getcwd+0x232> - 43f674: 4c 3b 7c 24 60 cmp 0x60(%rsp),%r15 - 43f679: 75 87 jne 43f602 <__getcwd+0x232> - 43f67b: 48 8b 44 24 18 mov 0x18(%rsp),%rax - 43f680: 48 3b 44 24 68 cmp 0x68(%rsp),%rax - 43f685: 0f 85 77 ff ff ff jne 43f602 <__getcwd+0x232> - 43f68b: 48 89 df mov %rbx,%rdi - 43f68e: e8 bd 3f fe ff callq 423650 - 43f693: 4c 8b 44 24 38 mov 0x38(%rsp),%r8 - 43f698: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi - 43f69d: 49 89 c7 mov %rax,%r15 - 43f6a0: 49 29 f8 sub %rdi,%r8 - 43f6a3: 4d 39 c7 cmp %r8,%r15 - 43f6a6: 4c 89 44 24 18 mov %r8,0x18(%rsp) - 43f6ab: 72 64 jb 43f711 <__getcwd+0x341> - 43f6ad: 48 83 7c 24 30 00 cmpq $0x0,0x30(%rsp) - 43f6b3: 0f 85 fd 03 00 00 jne 43fab6 <__getcwd+0x6e6> - 43f6b9: 48 8b 44 24 28 mov 0x28(%rsp),%rax - 43f6be: 49 39 c7 cmp %rax,%r15 - 43f6c1: 49 0f 43 c7 cmovae %r15,%rax - 43f6c5: 49 89 c5 mov %rax,%r13 - 43f6c8: 4d 01 ed add %r13,%r13 - 43f6cb: 4c 89 ee mov %r13,%rsi - 43f6ce: e8 9d e8 fd ff callq 41df70 <__libc_realloc> - 43f6d3: 48 85 c0 test %rax,%rax - 43f6d6: 4c 8b 44 24 18 mov 0x18(%rsp),%r8 - 43f6db: 0f 84 c7 03 00 00 je 43faa8 <__getcwd+0x6d8> - 43f6e1: 48 8b 54 24 08 mov 0x8(%rsp),%rdx - 43f6e6: 48 03 54 24 28 add 0x28(%rsp),%rdx - 43f6eb: 4c 89 ef mov %r13,%rdi - 43f6ee: 48 2b 54 24 38 sub 0x38(%rsp),%rdx - 43f6f3: 4a 8d 34 00 lea (%rax,%r8,1),%rsi - 43f6f7: 48 89 44 24 08 mov %rax,0x8(%rsp) - 43f6fc: 48 29 d7 sub %rdx,%rdi - 43f6ff: 48 01 c7 add %rax,%rdi - 43f702: e8 19 c9 fe ff callq 42c020 - 43f707: 4c 89 6c 24 28 mov %r13,0x28(%rsp) - 43f70c: 48 89 44 24 38 mov %rax,0x38(%rsp) - 43f711: 48 8b 4c 24 38 mov 0x38(%rsp),%rcx - 43f716: 4c 89 fa mov %r15,%rdx - 43f719: 48 89 de mov %rbx,%rsi - 43f71c: 4c 29 f9 sub %r15,%rcx - 43f71f: 48 89 cf mov %rcx,%rdi - 43f722: e8 f9 c8 fe ff callq 42c020 - 43f727: 4c 39 74 24 48 cmp %r14,0x48(%rsp) - 43f72c: 48 89 c1 mov %rax,%rcx - 43f72f: 48 8d 40 ff lea -0x1(%rax),%rax - 43f733: c6 41 ff 2f movb $0x2f,-0x1(%rcx) - 43f737: 48 89 44 24 38 mov %rax,0x38(%rsp) - 43f73c: 75 10 jne 43f74e <__getcwd+0x37e> - 43f73e: 48 8b 54 24 58 mov 0x58(%rsp),%rdx - 43f743: 48 39 54 24 50 cmp %rdx,0x50(%rsp) - 43f748: 0f 84 dc 01 00 00 je 43f92a <__getcwd+0x55a> - 43f74e: ba 00 00 08 00 mov $0x80000,%edx - 43f753: be f0 48 4a 00 mov $0x4a48f0,%esi - 43f758: 48 63 7c 24 10 movslq 0x10(%rsp),%rdi - 43f75d: b8 01 01 00 00 mov $0x101,%eax - 43f762: 0f 05 syscall - 43f764: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 43f76a: 0f 87 05 03 00 00 ja 43fa75 <__getcwd+0x6a5> - 43f770: 85 c0 test %eax,%eax - 43f772: 89 44 24 10 mov %eax,0x10(%rsp) - 43f776: 0f 88 e8 02 00 00 js 43fa64 <__getcwd+0x694> - 43f77c: 48 8b 44 24 58 mov 0x58(%rsp),%rax - 43f781: 4d 89 f7 mov %r14,%r15 - 43f784: 8b 74 24 10 mov 0x10(%rsp),%esi - 43f788: 48 89 44 24 18 mov %rax,0x18(%rsp) - 43f78d: e9 f1 fd ff ff jmpq 43f583 <__getcwd+0x1b3> - 43f792: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43f798: 80 78 14 00 cmpb $0x0,0x14(%rax) - 43f79c: 0f 84 60 fe ff ff je 43f602 <__getcwd+0x232> - 43f7a2: 66 83 78 14 2e cmpw $0x2e,0x14(%rax) - 43f7a7: 0f 85 3b fe ff ff jne 43f5e8 <__getcwd+0x218> - 43f7ad: e9 50 fe ff ff jmpq 43f602 <__getcwd+0x232> - 43f7b2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 43f7b8: 4c 8b 74 24 30 mov 0x30(%rsp),%r14 - 43f7bd: 64 c7 45 00 02 00 00 movl $0x2,%fs:0x0(%rbp) - 43f7c4: 00 - 43f7c5: bb 02 00 00 00 mov $0x2,%ebx - 43f7ca: 45 31 ed xor %r13d,%r13d - 43f7cd: 4c 89 e7 mov %r12,%rdi - 43f7d0: e8 db ad 02 00 callq 46a5b0 <__closedir> - 43f7d5: 45 84 ed test %r13b,%r13b - 43f7d8: 74 0c je 43f7e6 <__getcwd+0x416> - 43f7da: 48 63 7c 24 10 movslq 0x10(%rsp),%rdi - 43f7df: b8 03 00 00 00 mov $0x3,%eax - 43f7e4: 0f 05 syscall - 43f7e6: 48 83 7c 24 20 00 cmpq $0x0,0x20(%rsp) - 43f7ec: 0f 84 fe 01 00 00 je 43f9f0 <__getcwd+0x620> - 43f7f2: 64 89 5d 00 mov %ebx,%fs:0x0(%rbp) - 43f7f6: 4d 85 f6 test %r14,%r14 - 43f7f9: 0f 84 31 fc ff ff je 43f430 <__getcwd+0x60> - 43f7ff: 80 7c 24 43 00 cmpb $0x0,0x43(%rsp) - 43f804: 0f 84 26 fc ff ff je 43f430 <__getcwd+0x60> - 43f80a: 48 8b 7c 24 20 mov 0x20(%rsp),%rdi - 43f80f: e8 9c e5 fd ff callq 41ddb0 <__cfree> - 43f814: e9 17 fc ff ff jmpq 43f430 <__getcwd+0x60> - 43f819: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43f820: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 43f827: 64 c7 00 16 00 00 00 movl $0x16,%fs:(%rax) - 43f82e: 31 c0 xor %eax,%eax - 43f830: e9 fd fb ff ff jmpq 43f432 <__getcwd+0x62> - 43f835: 0f 1f 00 nopl (%rax) - 43f838: 48 85 db test %rbx,%rbx - 43f83b: 75 13 jne 43f850 <__getcwd+0x480> - 43f83d: 4d 85 f6 test %r14,%r14 - 43f840: 75 0e jne 43f850 <__getcwd+0x480> - 43f842: 48 89 d7 mov %rdx,%rdi - 43f845: 48 63 f0 movslq %eax,%rsi - 43f848: e8 23 e7 fd ff callq 41df70 <__libc_realloc> - 43f84d: 48 89 c3 mov %rax,%rbx - 43f850: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 43f855: 48 85 db test %rbx,%rbx - 43f858: 48 0f 45 c3 cmovne %rbx,%rax - 43f85c: e9 d1 fb ff ff jmpq 43f432 <__getcwd+0x62> - 43f861: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43f868: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi - 43f86d: e8 3e e5 fd ff callq 41ddb0 <__cfree> - 43f872: 64 8b 45 00 mov %fs:0x0(%rbp),%eax - 43f876: bf 01 10 00 00 mov $0x1001,%edi - 43f87b: 89 44 24 44 mov %eax,0x44(%rsp) - 43f87f: e8 8c e1 fd ff callq 41da10 <__libc_malloc> - 43f884: 48 85 c0 test %rax,%rax - 43f887: 48 89 44 24 08 mov %rax,0x8(%rsp) - 43f88c: 0f 84 9e 01 00 00 je 43fa30 <__getcwd+0x660> - 43f892: 48 c7 44 24 28 01 10 movq $0x1001,0x28(%rsp) - 43f899: 00 00 - 43f89b: 48 c7 44 24 20 00 00 movq $0x0,0x20(%rsp) - 43f8a2: 00 00 - 43f8a4: 48 89 c3 mov %rax,%rbx - 43f8a7: e9 19 fc ff ff jmpq 43f4c5 <__getcwd+0xf5> - 43f8ac: 0f 1f 40 00 nopl 0x0(%rax) - 43f8b0: 0f 84 cb fb ff ff je 43f481 <__getcwd+0xb1> - 43f8b6: 48 c7 c5 d0 ff ff ff mov $0xffffffffffffffd0,%rbp - 43f8bd: 64 8b 45 00 mov %fs:0x0(%rbp),%eax - 43f8c1: 83 f8 24 cmp $0x24,%eax - 43f8c4: 0f 84 be fb ff ff je 43f488 <__getcwd+0xb8> - 43f8ca: 83 f8 22 cmp $0x22,%eax - 43f8cd: 0f 84 eb 00 00 00 je 43f9be <__getcwd+0x5ee> - 43f8d3: 48 85 db test %rbx,%rbx - 43f8d6: 0f 85 54 fb ff ff jne 43f430 <__getcwd+0x60> - 43f8dc: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi - 43f8e1: e8 ca e4 fd ff callq 41ddb0 <__cfree> - 43f8e6: 31 c0 xor %eax,%eax - 43f8e8: e9 45 fb ff ff jmpq 43f432 <__getcwd+0x62> - 43f8ed: 0f 1f 00 nopl (%rax) - 43f8f0: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 43f8f5: 64 c7 45 00 16 00 00 movl $0x16,%fs:0x0(%rbp) - 43f8fc: 00 - 43f8fd: 48 89 44 24 20 mov %rax,0x20(%rsp) - 43f902: e9 ef fe ff ff jmpq 43f7f6 <__getcwd+0x426> - 43f907: 48 c7 c5 d0 ff ff ff mov $0xffffffffffffffd0,%rbp - 43f90e: f7 d8 neg %eax - 43f910: 64 89 45 00 mov %eax,%fs:0x0(%rbp) - 43f914: eb ab jmp 43f8c1 <__getcwd+0x4f1> - 43f916: c7 44 24 10 9c ff ff movl $0xffffff9c,0x10(%rsp) - 43f91d: ff - 43f91e: 45 31 ed xor %r13d,%r13d - 43f921: 64 8b 5d 00 mov %fs:0x0(%rbp),%ebx - 43f925: e9 ab fe ff ff jmpq 43f7d5 <__getcwd+0x405> - 43f92a: 4c 89 e7 mov %r12,%rdi - 43f92d: 4c 8b 74 24 30 mov 0x30(%rsp),%r14 - 43f932: e8 79 ac 02 00 callq 46a5b0 <__closedir> - 43f937: 85 c0 test %eax,%eax - 43f939: 0f 85 61 01 00 00 jne 43faa0 <__getcwd+0x6d0> - 43f93f: 48 8b 5c 24 08 mov 0x8(%rsp),%rbx - 43f944: 48 03 5c 24 28 add 0x28(%rsp),%rbx - 43f949: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 43f94e: 48 8b 54 24 28 mov 0x28(%rsp),%rdx - 43f953: 48 8d 44 10 ff lea -0x1(%rax,%rdx,1),%rax - 43f958: 48 3b 44 24 38 cmp 0x38(%rsp),%rax - 43f95d: 0f 84 f2 00 00 00 je 43fa55 <__getcwd+0x685> - 43f963: 48 8b 44 24 38 mov 0x38(%rsp),%rax - 43f968: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi - 43f96d: 48 29 c3 sub %rax,%rbx - 43f970: 48 89 c6 mov %rax,%rsi - 43f973: 48 89 da mov %rbx,%rdx - 43f976: e8 85 09 fc ff callq 400300 <__rela_iplt_end+0x38> - 43f97b: 4d 85 f6 test %r14,%r14 - 43f97e: 0f 84 ba 00 00 00 je 43fa3e <__getcwd+0x66e> - 43f984: 8b 54 24 44 mov 0x44(%rsp),%edx - 43f988: 48 8b 44 24 20 mov 0x20(%rsp),%rax - 43f98d: 64 89 55 00 mov %edx,%fs:0x0(%rbp) - 43f991: 48 8b 54 24 08 mov 0x8(%rsp),%rdx - 43f996: 48 85 c0 test %rax,%rax - 43f999: 48 0f 45 d0 cmovne %rax,%rdx - 43f99d: 48 89 d0 mov %rdx,%rax - 43f9a0: e9 8d fa ff ff jmpq 43f432 <__getcwd+0x62> - 43f9a5: 4c 8b 74 24 30 mov 0x30(%rsp),%r14 - 43f9aa: 89 c3 mov %eax,%ebx - 43f9ac: e9 19 fe ff ff jmpq 43f7ca <__getcwd+0x3fa> - 43f9b1: 89 c3 mov %eax,%ebx - 43f9b3: f7 db neg %ebx - 43f9b5: 64 89 5d 00 mov %ebx,%fs:0x0(%rbp) - 43f9b9: e9 28 fe ff ff jmpq 43f7e6 <__getcwd+0x416> - 43f9be: 48 85 db test %rbx,%rbx - 43f9c1: 0f 85 0c ff ff ff jne 43f8d3 <__getcwd+0x503> - 43f9c7: 4d 85 f6 test %r14,%r14 - 43f9ca: 0f 85 03 ff ff ff jne 43f8d3 <__getcwd+0x503> - 43f9d0: b9 50 49 4a 00 mov $0x4a4950,%ecx - 43f9d5: ba 79 00 00 00 mov $0x79,%edx - 43f9da: be f8 48 4a 00 mov $0x4a48f8,%esi - 43f9df: bf 20 49 4a 00 mov $0x4a4920,%edi - 43f9e4: e8 57 1d fc ff callq 401740 <__assert_fail> - 43f9e9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 43f9f0: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi - 43f9f5: e8 b6 e3 fd ff callq 41ddb0 <__cfree> - 43f9fa: e9 f3 fd ff ff jmpq 43f7f2 <__getcwd+0x422> - 43f9ff: 4c 8b 74 24 30 mov 0x30(%rsp),%r14 - 43fa04: 41 bd 01 00 00 00 mov $0x1,%r13d - 43fa0a: e9 12 ff ff ff jmpq 43f921 <__getcwd+0x551> - 43fa0f: 4d 85 e4 test %r12,%r12 - 43fa12: 4c 8b 74 24 30 mov 0x30(%rsp),%r14 - 43fa17: 64 8b 5d 00 mov %fs:0x0(%rbp),%ebx - 43fa1b: 0f 84 b9 fd ff ff je 43f7da <__getcwd+0x40a> - 43fa21: 41 bd 01 00 00 00 mov $0x1,%r13d - 43fa27: e9 a1 fd ff ff jmpq 43f7cd <__getcwd+0x3fd> - 43fa2c: 0f 1f 40 00 nopl 0x0(%rax) - 43fa30: 48 c7 44 24 20 00 00 movq $0x0,0x20(%rsp) - 43fa37: 00 00 - 43fa39: e9 b8 fd ff ff jmpq 43f7f6 <__getcwd+0x426> - 43fa3e: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi - 43fa43: 48 89 de mov %rbx,%rsi - 43fa46: e8 25 e5 fd ff callq 41df70 <__libc_realloc> - 43fa4b: 48 89 44 24 20 mov %rax,0x20(%rsp) - 43fa50: e9 2f ff ff ff jmpq 43f984 <__getcwd+0x5b4> - 43fa55: 48 83 6c 24 38 01 subq $0x1,0x38(%rsp) - 43fa5b: c6 40 ff 2f movb $0x2f,-0x1(%rax) - 43fa5f: e9 ff fe ff ff jmpq 43f963 <__getcwd+0x593> - 43fa64: 4c 8b 74 24 30 mov 0x30(%rsp),%r14 - 43fa69: 64 8b 5d 00 mov %fs:0x0(%rbp),%ebx - 43fa6d: 45 31 ed xor %r13d,%r13d - 43fa70: e9 58 fd ff ff jmpq 43f7cd <__getcwd+0x3fd> - 43fa75: 89 c3 mov %eax,%ebx - 43fa77: 4c 8b 74 24 30 mov 0x30(%rsp),%r14 - 43fa7c: c7 44 24 10 ff ff ff movl $0xffffffff,0x10(%rsp) - 43fa83: ff - 43fa84: f7 db neg %ebx - 43fa86: 45 31 ed xor %r13d,%r13d - 43fa89: 64 89 5d 00 mov %ebx,%fs:0x0(%rbp) - 43fa8d: e9 3b fd ff ff jmpq 43f7cd <__getcwd+0x3fd> - 43fa92: 64 8b 5d 00 mov %fs:0x0(%rbp),%ebx - 43fa96: e9 4b fd ff ff jmpq 43f7e6 <__getcwd+0x416> - 43fa9b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43faa0: 45 31 ed xor %r13d,%r13d - 43faa3: e9 79 fe ff ff jmpq 43f921 <__getcwd+0x551> - 43faa8: 4c 8b 74 24 30 mov 0x30(%rsp),%r14 - 43faad: 64 8b 5d 00 mov %fs:0x0(%rbp),%ebx - 43fab1: e9 14 fd ff ff jmpq 43f7ca <__getcwd+0x3fa> - 43fab6: 4c 8b 74 24 30 mov 0x30(%rsp),%r14 - 43fabb: 64 c7 45 00 22 00 00 movl $0x22,%fs:0x0(%rbp) - 43fac2: 00 - 43fac3: bb 22 00 00 00 mov $0x22,%ebx - 43fac8: e9 fd fc ff ff jmpq 43f7ca <__getcwd+0x3fa> - 43facd: 0f 1f 00 nopl (%rax) - -000000000043fad0 <__getrlimit>: - 43fad0: b8 61 00 00 00 mov $0x61,%eax - 43fad5: 0f 05 syscall - 43fad7: 48 3d 01 f0 ff ff cmp $0xfffffffffffff001,%rax - 43fadd: 0f 83 6d 46 00 00 jae 444150 <__syscall_error> - 43fae3: c3 retq - 43fae4: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43faeb: 00 00 00 - 43faee: 66 90 xchg %ax,%ax - -000000000043faf0 <__sbrk>: - 43faf0: 55 push %rbp - 43faf1: 53 push %rbx - 43faf2: 48 89 fd mov %rdi,%rbp - 43faf5: 48 83 ec 08 sub $0x8,%rsp - 43faf9: 48 8b 1d 70 ce 28 00 mov 0x28ce70(%rip),%rbx # 6cc970 <__curbrk> - 43fb00: 48 85 db test %rbx,%rbx - 43fb03: 74 43 je 43fb48 <__sbrk+0x58> - 43fb05: 8b 05 f5 bb 28 00 mov 0x28bbf5(%rip),%eax # 6cb700 <__libc_multiple_libcs> - 43fb0b: 85 c0 test %eax,%eax - 43fb0d: 75 39 jne 43fb48 <__sbrk+0x58> - 43fb0f: 48 83 fd 00 cmp $0x0,%rbp - 43fb13: 74 24 je 43fb39 <__sbrk+0x49> - 43fb15: 7e 69 jle 43fb80 <__sbrk+0x90> - 43fb17: 48 89 d8 mov %rbx,%rax - 43fb1a: 48 01 e8 add %rbp,%rax - 43fb1d: 0f 92 c0 setb %al - 43fb20: 84 c0 test %al,%al - 43fb22: 74 3c je 43fb60 <__sbrk+0x70> - 43fb24: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 43fb2b: 64 c7 00 0c 00 00 00 movl $0xc,%fs:(%rax) - 43fb32: 48 c7 c3 ff ff ff ff mov $0xffffffffffffffff,%rbx - 43fb39: 48 83 c4 08 add $0x8,%rsp - 43fb3d: 48 89 d8 mov %rbx,%rax - 43fb40: 5b pop %rbx - 43fb41: 5d pop %rbp - 43fb42: c3 retq - 43fb43: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 43fb48: 31 ff xor %edi,%edi - 43fb4a: e8 f1 af 02 00 callq 46ab40 <__brk> - 43fb4f: 85 c0 test %eax,%eax - 43fb51: 48 8b 1d 18 ce 28 00 mov 0x28ce18(%rip),%rbx # 6cc970 <__curbrk> - 43fb58: 79 b5 jns 43fb0f <__sbrk+0x1f> - 43fb5a: eb d6 jmp 43fb32 <__sbrk+0x42> - 43fb5c: 0f 1f 40 00 nopl 0x0(%rax) - 43fb60: 48 8d 3c 2b lea (%rbx,%rbp,1),%rdi - 43fb64: e8 d7 af 02 00 callq 46ab40 <__brk> - 43fb69: 85 c0 test %eax,%eax - 43fb6b: 78 c5 js 43fb32 <__sbrk+0x42> - 43fb6d: 48 83 c4 08 add $0x8,%rsp - 43fb71: 48 89 d8 mov %rbx,%rax - 43fb74: 5b pop %rbx - 43fb75: 5d pop %rbp - 43fb76: c3 retq - 43fb77: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 43fb7e: 00 00 - 43fb80: 48 89 e8 mov %rbp,%rax - 43fb83: 48 f7 d8 neg %rax - 43fb86: 48 39 c3 cmp %rax,%rbx - 43fb89: 0f 92 c0 setb %al - 43fb8c: eb 92 jmp 43fb20 <__sbrk+0x30> - 43fb8e: 66 90 xchg %ax,%ax - -000000000043fb90 <__getpagesize>: - 43fb90: 48 8b 05 e9 b5 28 00 mov 0x28b5e9(%rip),%rax # 6cb180 <_dl_pagesize> - 43fb97: 48 85 c0 test %rax,%rax - 43fb9a: 74 02 je 43fb9e <__getpagesize+0xe> - 43fb9c: f3 c3 repz retq - 43fb9e: 50 push %rax - 43fb9f: b9 90 49 4a 00 mov $0x4a4990,%ecx - 43fba4: ba 1c 00 00 00 mov $0x1c,%edx - 43fba9: be 60 49 4a 00 mov $0x4a4960,%esi - 43fbae: bf 9e 49 4a 00 mov $0x4a499e,%edi - 43fbb3: e8 88 1b fc ff callq 401740 <__assert_fail> - 43fbb8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 43fbbf: 00 - -000000000043fbc0 <__getdtablesize>: - 43fbc0: 48 83 ec 18 sub $0x18,%rsp - 43fbc4: bf 07 00 00 00 mov $0x7,%edi - 43fbc9: 48 89 e6 mov %rsp,%rsi - 43fbcc: e8 ff fe ff ff callq 43fad0 <__getrlimit> - 43fbd1: ba 00 01 00 00 mov $0x100,%edx - 43fbd6: 85 c0 test %eax,%eax - 43fbd8: 0f 49 14 24 cmovns (%rsp),%edx - 43fbdc: 48 83 c4 18 add $0x18,%rsp - 43fbe0: 89 d0 mov %edx,%eax - 43fbe2: c3 retq - 43fbe3: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43fbea: 00 00 00 - 43fbed: 0f 1f 00 nopl (%rax) - -000000000043fbf0 <__mmap>: - 43fbf0: 48 85 ff test %rdi,%rdi - 43fbf3: 41 57 push %r15 - 43fbf5: 4d 89 cf mov %r9,%r15 - 43fbf8: 41 56 push %r14 - 43fbfa: 41 89 ce mov %ecx,%r14d - 43fbfd: 41 55 push %r13 - 43fbff: 49 89 f5 mov %rsi,%r13 - 43fc02: 41 54 push %r12 - 43fc04: 49 89 fc mov %rdi,%r12 - 43fc07: 55 push %rbp - 43fc08: 53 push %rbx - 43fc09: 74 35 je 43fc40 <__mmap+0x50> - 43fc0b: 49 63 e8 movslq %r8d,%rbp - 43fc0e: 48 63 da movslq %edx,%rbx - 43fc11: 4d 89 f9 mov %r15,%r9 - 43fc14: 49 89 e8 mov %rbp,%r8 - 43fc17: 4d 63 d6 movslq %r14d,%r10 - 43fc1a: 48 89 da mov %rbx,%rdx - 43fc1d: 4c 89 ee mov %r13,%rsi - 43fc20: 4c 89 e7 mov %r12,%rdi - 43fc23: b8 09 00 00 00 mov $0x9,%eax - 43fc28: 0f 05 syscall - 43fc2a: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 43fc30: 77 4e ja 43fc80 <__mmap+0x90> - 43fc32: 5b pop %rbx - 43fc33: 5d pop %rbp - 43fc34: 41 5c pop %r12 - 43fc36: 41 5d pop %r13 - 43fc38: 41 5e pop %r14 - 43fc3a: 41 5f pop %r15 - 43fc3c: c3 retq - 43fc3d: 0f 1f 00 nopl (%rax) - 43fc40: f6 c2 04 test $0x4,%dl - 43fc43: 74 c6 je 43fc0b <__mmap+0x1b> - 43fc45: f6 05 76 ca 28 00 01 testb $0x1,0x28ca76(%rip) # 6cc6c2 <_dl_x86_cpu_features+0x42> - 43fc4c: 49 63 e8 movslq %r8d,%rbp - 43fc4f: 48 63 da movslq %edx,%rbx - 43fc52: 74 bd je 43fc11 <__mmap+0x21> - 43fc54: 41 89 ca mov %ecx,%r10d - 43fc57: 49 89 e8 mov %rbp,%r8 - 43fc5a: 48 89 da mov %rbx,%rdx - 43fc5d: 41 83 ca 40 or $0x40,%r10d - 43fc61: 31 ff xor %edi,%edi - 43fc63: b8 09 00 00 00 mov $0x9,%eax - 43fc68: 4d 63 d2 movslq %r10d,%r10 - 43fc6b: 0f 05 syscall - 43fc6d: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 43fc73: 77 20 ja 43fc95 <__mmap+0xa5> - 43fc75: 48 83 f8 ff cmp $0xffffffffffffffff,%rax - 43fc79: 75 b7 jne 43fc32 <__mmap+0x42> - 43fc7b: eb 94 jmp 43fc11 <__mmap+0x21> - 43fc7d: 0f 1f 00 nopl (%rax) - 43fc80: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx - 43fc87: f7 d8 neg %eax - 43fc89: 64 89 02 mov %eax,%fs:(%rdx) - 43fc8c: 48 c7 c0 ff ff ff ff mov $0xffffffffffffffff,%rax - 43fc93: eb 9d jmp 43fc32 <__mmap+0x42> - 43fc95: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx - 43fc9c: f7 d8 neg %eax - 43fc9e: 64 89 02 mov %eax,%fs:(%rdx) - 43fca1: e9 6b ff ff ff jmpq 43fc11 <__mmap+0x21> - 43fca6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43fcad: 00 00 00 - -000000000043fcb0 <__munmap>: - 43fcb0: b8 0b 00 00 00 mov $0xb,%eax - 43fcb5: 0f 05 syscall - 43fcb7: 48 3d 01 f0 ff ff cmp $0xfffffffffffff001,%rax - 43fcbd: 0f 83 8d 44 00 00 jae 444150 <__syscall_error> - 43fcc3: c3 retq - 43fcc4: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43fccb: 00 00 00 - 43fcce: 66 90 xchg %ax,%ax - -000000000043fcd0 <__mprotect>: - 43fcd0: b8 0a 00 00 00 mov $0xa,%eax - 43fcd5: 0f 05 syscall - 43fcd7: 48 3d 01 f0 ff ff cmp $0xfffffffffffff001,%rax - 43fcdd: 0f 83 6d 44 00 00 jae 444150 <__syscall_error> - 43fce3: c3 retq - 43fce4: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43fceb: 00 00 00 - 43fcee: 66 90 xchg %ax,%ax - -000000000043fcf0 <__madvise>: - 43fcf0: b8 1c 00 00 00 mov $0x1c,%eax - 43fcf5: 0f 05 syscall - 43fcf7: 48 3d 01 f0 ff ff cmp $0xfffffffffffff001,%rax - 43fcfd: 0f 83 4d 44 00 00 jae 444150 <__syscall_error> - 43fd03: c3 retq - 43fd04: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43fd0b: 00 00 00 - 43fd0e: 66 90 xchg %ax,%ax - -000000000043fd10 : - 43fd10: 41 54 push %r12 - 43fd12: 55 push %rbp - 43fd13: 48 89 f0 mov %rsi,%rax - 43fd16: 53 push %rbx - 43fd17: 48 83 7f 08 00 cmpq $0x0,0x8(%rdi) - 43fd1c: 74 62 je 43fd80 - 43fd1e: 48 89 fb mov %rdi,%rbx - 43fd21: 31 f6 xor %esi,%esi - 43fd23: 41 89 d4 mov %edx,%r12d - 43fd26: 48 89 c5 mov %rax,%rbp - 43fd29: ff d0 callq *%rax - 43fd2b: 48 8b 7b 08 mov 0x8(%rbx),%rdi - 43fd2f: 48 85 ff test %rdi,%rdi - 43fd32: 74 0d je 43fd41 - 43fd34: 41 8d 54 24 01 lea 0x1(%r12),%edx - 43fd39: 48 89 ee mov %rbp,%rsi - 43fd3c: e8 cf ff ff ff callq 43fd10 - 43fd41: 48 89 df mov %rbx,%rdi - 43fd44: 44 89 e2 mov %r12d,%edx - 43fd47: be 01 00 00 00 mov $0x1,%esi - 43fd4c: ff d5 callq *%rbp - 43fd4e: 48 8b 7b 10 mov 0x10(%rbx),%rdi - 43fd52: 48 85 ff test %rdi,%rdi - 43fd55: 74 0d je 43fd64 - 43fd57: 41 8d 54 24 01 lea 0x1(%r12),%edx - 43fd5c: 48 89 ee mov %rbp,%rsi - 43fd5f: e8 ac ff ff ff callq 43fd10 - 43fd64: 44 89 e2 mov %r12d,%edx - 43fd67: 48 89 df mov %rbx,%rdi - 43fd6a: 48 89 e8 mov %rbp,%rax - 43fd6d: 5b pop %rbx - 43fd6e: 5d pop %rbp - 43fd6f: 41 5c pop %r12 - 43fd71: be 02 00 00 00 mov $0x2,%esi - 43fd76: ff e0 jmpq *%rax - 43fd78: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 43fd7f: 00 - 43fd80: 48 83 7f 10 00 cmpq $0x0,0x10(%rdi) - 43fd85: 75 97 jne 43fd1e - 43fd87: 5b pop %rbx - 43fd88: 5d pop %rbp - 43fd89: 41 5c pop %r12 - 43fd8b: be 03 00 00 00 mov $0x3,%esi - 43fd90: ff e0 jmpq *%rax - 43fd92: 0f 1f 40 00 nopl 0x0(%rax) - 43fd96: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 43fd9d: 00 00 00 - -000000000043fda0 : - 43fda0: 41 57 push %r15 - 43fda2: 41 56 push %r14 - 43fda4: 41 55 push %r13 - 43fda6: 41 54 push %r12 - 43fda8: 49 89 fc mov %rdi,%r12 - 43fdab: 55 push %rbp - 43fdac: 53 push %rbx - 43fdad: 48 89 f3 mov %rsi,%rbx - 43fdb0: 48 83 ec 18 sub $0x18,%rsp - 43fdb4: 48 8b 6f 08 mov 0x8(%rdi),%rbp - 43fdb8: 48 85 ed test %rbp,%rbp - 43fdbb: 0f 84 0b 02 00 00 je 43ffcc - 43fdc1: 4c 8b 6d 08 mov 0x8(%rbp),%r13 - 43fdc5: 4d 85 ed test %r13,%r13 - 43fdc8: 0f 84 c9 00 00 00 je 43fe97 - 43fdce: 4d 8b 75 08 mov 0x8(%r13),%r14 - 43fdd2: 4d 85 f6 test %r14,%r14 - 43fdd5: 74 2c je 43fe03 - 43fdd7: 49 8b 7e 08 mov 0x8(%r14),%rdi - 43fddb: 48 85 ff test %rdi,%rdi - 43fdde: 74 05 je 43fde5 - 43fde0: e8 bb ff ff ff callq 43fda0 - 43fde5: 49 8b 7e 10 mov 0x10(%r14),%rdi - 43fde9: 48 85 ff test %rdi,%rdi - 43fdec: 74 08 je 43fdf6 - 43fdee: 48 89 de mov %rbx,%rsi - 43fdf1: e8 aa ff ff ff callq 43fda0 - 43fdf6: 49 8b 3e mov (%r14),%rdi - 43fdf9: ff d3 callq *%rbx - 43fdfb: 4c 89 f7 mov %r14,%rdi - 43fdfe: e8 ad df fd ff callq 41ddb0 <__cfree> - 43fe03: 4d 8b 75 10 mov 0x10(%r13),%r14 - 43fe07: 4d 85 f6 test %r14,%r14 - 43fe0a: 74 7d je 43fe89 - 43fe0c: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 43fe10: 4d 85 ff test %r15,%r15 - 43fe13: 74 2f je 43fe44 - 43fe15: 49 8b 7f 08 mov 0x8(%r15),%rdi - 43fe19: 48 85 ff test %rdi,%rdi - 43fe1c: 74 08 je 43fe26 - 43fe1e: 48 89 de mov %rbx,%rsi - 43fe21: e8 7a ff ff ff callq 43fda0 - 43fe26: 49 8b 7f 10 mov 0x10(%r15),%rdi - 43fe2a: 48 85 ff test %rdi,%rdi - 43fe2d: 74 08 je 43fe37 - 43fe2f: 48 89 de mov %rbx,%rsi - 43fe32: e8 69 ff ff ff callq 43fda0 - 43fe37: 49 8b 3f mov (%r15),%rdi - 43fe3a: ff d3 callq *%rbx - 43fe3c: 4c 89 ff mov %r15,%rdi - 43fe3f: e8 6c df fd ff callq 41ddb0 <__cfree> - 43fe44: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 43fe48: 4d 85 ff test %r15,%r15 - 43fe4b: 74 2f je 43fe7c - 43fe4d: 49 8b 7f 08 mov 0x8(%r15),%rdi - 43fe51: 48 85 ff test %rdi,%rdi - 43fe54: 74 08 je 43fe5e - 43fe56: 48 89 de mov %rbx,%rsi - 43fe59: e8 42 ff ff ff callq 43fda0 - 43fe5e: 49 8b 7f 10 mov 0x10(%r15),%rdi - 43fe62: 48 85 ff test %rdi,%rdi - 43fe65: 74 08 je 43fe6f - 43fe67: 48 89 de mov %rbx,%rsi - 43fe6a: e8 31 ff ff ff callq 43fda0 - 43fe6f: 49 8b 3f mov (%r15),%rdi - 43fe72: ff d3 callq *%rbx - 43fe74: 4c 89 ff mov %r15,%rdi - 43fe77: e8 34 df fd ff callq 41ddb0 <__cfree> - 43fe7c: 49 8b 3e mov (%r14),%rdi - 43fe7f: ff d3 callq *%rbx - 43fe81: 4c 89 f7 mov %r14,%rdi - 43fe84: e8 27 df fd ff callq 41ddb0 <__cfree> - 43fe89: 49 8b 7d 00 mov 0x0(%r13),%rdi - 43fe8d: ff d3 callq *%rbx - 43fe8f: 4c 89 ef mov %r13,%rdi - 43fe92: e8 19 df fd ff callq 41ddb0 <__cfree> - 43fe97: 4c 8b 6d 10 mov 0x10(%rbp),%r13 - 43fe9b: 4d 85 ed test %r13,%r13 - 43fe9e: 0f 84 1a 01 00 00 je 43ffbe - 43fea4: 4d 8b 75 08 mov 0x8(%r13),%r14 - 43fea8: 4d 85 f6 test %r14,%r14 - 43feab: 74 7d je 43ff2a - 43fead: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 43feb1: 4d 85 ff test %r15,%r15 - 43feb4: 74 2f je 43fee5 - 43feb6: 49 8b 7f 08 mov 0x8(%r15),%rdi - 43feba: 48 85 ff test %rdi,%rdi - 43febd: 74 08 je 43fec7 - 43febf: 48 89 de mov %rbx,%rsi - 43fec2: e8 d9 fe ff ff callq 43fda0 - 43fec7: 49 8b 7f 10 mov 0x10(%r15),%rdi - 43fecb: 48 85 ff test %rdi,%rdi - 43fece: 74 08 je 43fed8 - 43fed0: 48 89 de mov %rbx,%rsi - 43fed3: e8 c8 fe ff ff callq 43fda0 - 43fed8: 49 8b 3f mov (%r15),%rdi - 43fedb: ff d3 callq *%rbx - 43fedd: 4c 89 ff mov %r15,%rdi - 43fee0: e8 cb de fd ff callq 41ddb0 <__cfree> - 43fee5: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 43fee9: 4d 85 ff test %r15,%r15 - 43feec: 74 2f je 43ff1d - 43feee: 49 8b 7f 08 mov 0x8(%r15),%rdi - 43fef2: 48 85 ff test %rdi,%rdi - 43fef5: 74 08 je 43feff - 43fef7: 48 89 de mov %rbx,%rsi - 43fefa: e8 a1 fe ff ff callq 43fda0 - 43feff: 49 8b 7f 10 mov 0x10(%r15),%rdi - 43ff03: 48 85 ff test %rdi,%rdi - 43ff06: 74 08 je 43ff10 - 43ff08: 48 89 de mov %rbx,%rsi - 43ff0b: e8 90 fe ff ff callq 43fda0 - 43ff10: 49 8b 3f mov (%r15),%rdi - 43ff13: ff d3 callq *%rbx - 43ff15: 4c 89 ff mov %r15,%rdi - 43ff18: e8 93 de fd ff callq 41ddb0 <__cfree> - 43ff1d: 49 8b 3e mov (%r14),%rdi - 43ff20: ff d3 callq *%rbx - 43ff22: 4c 89 f7 mov %r14,%rdi - 43ff25: e8 86 de fd ff callq 41ddb0 <__cfree> - 43ff2a: 4d 8b 75 10 mov 0x10(%r13),%r14 - 43ff2e: 4d 85 f6 test %r14,%r14 - 43ff31: 74 7d je 43ffb0 - 43ff33: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 43ff37: 4d 85 ff test %r15,%r15 - 43ff3a: 74 2f je 43ff6b - 43ff3c: 49 8b 7f 08 mov 0x8(%r15),%rdi - 43ff40: 48 85 ff test %rdi,%rdi - 43ff43: 74 08 je 43ff4d - 43ff45: 48 89 de mov %rbx,%rsi - 43ff48: e8 53 fe ff ff callq 43fda0 - 43ff4d: 49 8b 7f 10 mov 0x10(%r15),%rdi - 43ff51: 48 85 ff test %rdi,%rdi - 43ff54: 74 08 je 43ff5e - 43ff56: 48 89 de mov %rbx,%rsi - 43ff59: e8 42 fe ff ff callq 43fda0 - 43ff5e: 49 8b 3f mov (%r15),%rdi - 43ff61: ff d3 callq *%rbx - 43ff63: 4c 89 ff mov %r15,%rdi - 43ff66: e8 45 de fd ff callq 41ddb0 <__cfree> - 43ff6b: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 43ff6f: 4d 85 ff test %r15,%r15 - 43ff72: 74 2f je 43ffa3 - 43ff74: 49 8b 7f 08 mov 0x8(%r15),%rdi - 43ff78: 48 85 ff test %rdi,%rdi - 43ff7b: 74 08 je 43ff85 - 43ff7d: 48 89 de mov %rbx,%rsi - 43ff80: e8 1b fe ff ff callq 43fda0 - 43ff85: 49 8b 7f 10 mov 0x10(%r15),%rdi - 43ff89: 48 85 ff test %rdi,%rdi - 43ff8c: 74 08 je 43ff96 - 43ff8e: 48 89 de mov %rbx,%rsi - 43ff91: e8 0a fe ff ff callq 43fda0 - 43ff96: 49 8b 3f mov (%r15),%rdi - 43ff99: ff d3 callq *%rbx - 43ff9b: 4c 89 ff mov %r15,%rdi - 43ff9e: e8 0d de fd ff callq 41ddb0 <__cfree> - 43ffa3: 49 8b 3e mov (%r14),%rdi - 43ffa6: ff d3 callq *%rbx - 43ffa8: 4c 89 f7 mov %r14,%rdi - 43ffab: e8 00 de fd ff callq 41ddb0 <__cfree> - 43ffb0: 49 8b 7d 00 mov 0x0(%r13),%rdi - 43ffb4: ff d3 callq *%rbx - 43ffb6: 4c 89 ef mov %r13,%rdi - 43ffb9: e8 f2 dd fd ff callq 41ddb0 <__cfree> - 43ffbe: 48 8b 7d 00 mov 0x0(%rbp),%rdi - 43ffc2: ff d3 callq *%rbx - 43ffc4: 48 89 ef mov %rbp,%rdi - 43ffc7: e8 e4 dd fd ff callq 41ddb0 <__cfree> - 43ffcc: 49 8b 6c 24 10 mov 0x10(%r12),%rbp - 43ffd1: 48 85 ed test %rbp,%rbp - 43ffd4: 0f 84 a5 02 00 00 je 44027f - 43ffda: 4c 8b 6d 08 mov 0x8(%rbp),%r13 - 43ffde: 4d 85 ed test %r13,%r13 - 43ffe1: 0f 84 1a 01 00 00 je 440101 - 43ffe7: 4d 8b 75 08 mov 0x8(%r13),%r14 - 43ffeb: 4d 85 f6 test %r14,%r14 - 43ffee: 74 7d je 44006d - 43fff0: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 43fff4: 4d 85 ff test %r15,%r15 - 43fff7: 74 2f je 440028 - 43fff9: 49 8b 7f 08 mov 0x8(%r15),%rdi - 43fffd: 48 85 ff test %rdi,%rdi - 440000: 74 08 je 44000a - 440002: 48 89 de mov %rbx,%rsi - 440005: e8 96 fd ff ff callq 43fda0 - 44000a: 49 8b 7f 10 mov 0x10(%r15),%rdi - 44000e: 48 85 ff test %rdi,%rdi - 440011: 74 08 je 44001b - 440013: 48 89 de mov %rbx,%rsi - 440016: e8 85 fd ff ff callq 43fda0 - 44001b: 49 8b 3f mov (%r15),%rdi - 44001e: ff d3 callq *%rbx - 440020: 4c 89 ff mov %r15,%rdi - 440023: e8 88 dd fd ff callq 41ddb0 <__cfree> - 440028: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 44002c: 4d 85 ff test %r15,%r15 - 44002f: 74 2f je 440060 - 440031: 49 8b 7f 08 mov 0x8(%r15),%rdi - 440035: 48 85 ff test %rdi,%rdi - 440038: 74 08 je 440042 - 44003a: 48 89 de mov %rbx,%rsi - 44003d: e8 5e fd ff ff callq 43fda0 - 440042: 49 8b 7f 10 mov 0x10(%r15),%rdi - 440046: 48 85 ff test %rdi,%rdi - 440049: 74 08 je 440053 - 44004b: 48 89 de mov %rbx,%rsi - 44004e: e8 4d fd ff ff callq 43fda0 - 440053: 49 8b 3f mov (%r15),%rdi - 440056: ff d3 callq *%rbx - 440058: 4c 89 ff mov %r15,%rdi - 44005b: e8 50 dd fd ff callq 41ddb0 <__cfree> - 440060: 49 8b 3e mov (%r14),%rdi - 440063: ff d3 callq *%rbx - 440065: 4c 89 f7 mov %r14,%rdi - 440068: e8 43 dd fd ff callq 41ddb0 <__cfree> - 44006d: 4d 8b 75 10 mov 0x10(%r13),%r14 - 440071: 4d 85 f6 test %r14,%r14 - 440074: 74 7d je 4400f3 - 440076: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 44007a: 4d 85 ff test %r15,%r15 - 44007d: 74 2f je 4400ae - 44007f: 49 8b 7f 08 mov 0x8(%r15),%rdi - 440083: 48 85 ff test %rdi,%rdi - 440086: 74 08 je 440090 - 440088: 48 89 de mov %rbx,%rsi - 44008b: e8 10 fd ff ff callq 43fda0 - 440090: 49 8b 7f 10 mov 0x10(%r15),%rdi - 440094: 48 85 ff test %rdi,%rdi - 440097: 74 08 je 4400a1 - 440099: 48 89 de mov %rbx,%rsi - 44009c: e8 ff fc ff ff callq 43fda0 - 4400a1: 49 8b 3f mov (%r15),%rdi - 4400a4: ff d3 callq *%rbx - 4400a6: 4c 89 ff mov %r15,%rdi - 4400a9: e8 02 dd fd ff callq 41ddb0 <__cfree> - 4400ae: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 4400b2: 4d 85 ff test %r15,%r15 - 4400b5: 74 2f je 4400e6 - 4400b7: 49 8b 7f 08 mov 0x8(%r15),%rdi - 4400bb: 48 85 ff test %rdi,%rdi - 4400be: 74 08 je 4400c8 - 4400c0: 48 89 de mov %rbx,%rsi - 4400c3: e8 d8 fc ff ff callq 43fda0 - 4400c8: 49 8b 7f 10 mov 0x10(%r15),%rdi - 4400cc: 48 85 ff test %rdi,%rdi - 4400cf: 74 08 je 4400d9 - 4400d1: 48 89 de mov %rbx,%rsi - 4400d4: e8 c7 fc ff ff callq 43fda0 - 4400d9: 49 8b 3f mov (%r15),%rdi - 4400dc: ff d3 callq *%rbx - 4400de: 4c 89 ff mov %r15,%rdi - 4400e1: e8 ca dc fd ff callq 41ddb0 <__cfree> - 4400e6: 49 8b 3e mov (%r14),%rdi - 4400e9: ff d3 callq *%rbx - 4400eb: 4c 89 f7 mov %r14,%rdi - 4400ee: e8 bd dc fd ff callq 41ddb0 <__cfree> - 4400f3: 49 8b 7d 00 mov 0x0(%r13),%rdi - 4400f7: ff d3 callq *%rbx - 4400f9: 4c 89 ef mov %r13,%rdi - 4400fc: e8 af dc fd ff callq 41ddb0 <__cfree> - 440101: 4c 8b 6d 10 mov 0x10(%rbp),%r13 - 440105: 4d 85 ed test %r13,%r13 - 440108: 0f 84 63 01 00 00 je 440271 - 44010e: 4d 8b 75 08 mov 0x8(%r13),%r14 - 440112: 4d 85 f6 test %r14,%r14 - 440115: 74 7d je 440194 - 440117: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 44011b: 4d 85 ff test %r15,%r15 - 44011e: 74 2f je 44014f - 440120: 49 8b 7f 08 mov 0x8(%r15),%rdi - 440124: 48 85 ff test %rdi,%rdi - 440127: 74 08 je 440131 - 440129: 48 89 de mov %rbx,%rsi - 44012c: e8 6f fc ff ff callq 43fda0 - 440131: 49 8b 7f 10 mov 0x10(%r15),%rdi - 440135: 48 85 ff test %rdi,%rdi - 440138: 74 08 je 440142 - 44013a: 48 89 de mov %rbx,%rsi - 44013d: e8 5e fc ff ff callq 43fda0 - 440142: 49 8b 3f mov (%r15),%rdi - 440145: ff d3 callq *%rbx - 440147: 4c 89 ff mov %r15,%rdi - 44014a: e8 61 dc fd ff callq 41ddb0 <__cfree> - 44014f: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 440153: 4d 85 ff test %r15,%r15 - 440156: 74 2f je 440187 - 440158: 49 8b 7f 08 mov 0x8(%r15),%rdi - 44015c: 48 85 ff test %rdi,%rdi - 44015f: 74 08 je 440169 - 440161: 48 89 de mov %rbx,%rsi - 440164: e8 37 fc ff ff callq 43fda0 - 440169: 49 8b 7f 10 mov 0x10(%r15),%rdi - 44016d: 48 85 ff test %rdi,%rdi - 440170: 74 08 je 44017a - 440172: 48 89 de mov %rbx,%rsi - 440175: e8 26 fc ff ff callq 43fda0 - 44017a: 49 8b 3f mov (%r15),%rdi - 44017d: ff d3 callq *%rbx - 44017f: 4c 89 ff mov %r15,%rdi - 440182: e8 29 dc fd ff callq 41ddb0 <__cfree> - 440187: 49 8b 3e mov (%r14),%rdi - 44018a: ff d3 callq *%rbx - 44018c: 4c 89 f7 mov %r14,%rdi - 44018f: e8 1c dc fd ff callq 41ddb0 <__cfree> - 440194: 4d 8b 75 10 mov 0x10(%r13),%r14 - 440198: 4d 85 f6 test %r14,%r14 - 44019b: 0f 84 c2 00 00 00 je 440263 - 4401a1: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 4401a5: 4d 85 ff test %r15,%r15 - 4401a8: 74 2f je 4401d9 - 4401aa: 49 8b 7f 08 mov 0x8(%r15),%rdi - 4401ae: 48 85 ff test %rdi,%rdi - 4401b1: 74 08 je 4401bb - 4401b3: 48 89 de mov %rbx,%rsi - 4401b6: e8 e5 fb ff ff callq 43fda0 - 4401bb: 49 8b 7f 10 mov 0x10(%r15),%rdi - 4401bf: 48 85 ff test %rdi,%rdi - 4401c2: 74 08 je 4401cc - 4401c4: 48 89 de mov %rbx,%rsi - 4401c7: e8 d4 fb ff ff callq 43fda0 - 4401cc: 49 8b 3f mov (%r15),%rdi - 4401cf: ff d3 callq *%rbx - 4401d1: 4c 89 ff mov %r15,%rdi - 4401d4: e8 d7 db fd ff callq 41ddb0 <__cfree> - 4401d9: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 4401dd: 4d 85 ff test %r15,%r15 - 4401e0: 74 74 je 440256 - 4401e2: 49 8b 7f 08 mov 0x8(%r15),%rdi - 4401e6: 48 85 ff test %rdi,%rdi - 4401e9: 74 08 je 4401f3 - 4401eb: 48 89 de mov %rbx,%rsi - 4401ee: e8 ad fb ff ff callq 43fda0 - 4401f3: 49 8b 47 10 mov 0x10(%r15),%rax - 4401f7: 48 85 c0 test %rax,%rax - 4401fa: 74 4d je 440249 - 4401fc: 48 8b 78 08 mov 0x8(%rax),%rdi - 440200: 48 85 ff test %rdi,%rdi - 440203: 74 12 je 440217 - 440205: 48 89 de mov %rbx,%rsi - 440208: 48 89 44 24 08 mov %rax,0x8(%rsp) - 44020d: e8 8e fb ff ff callq 43fda0 - 440212: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 440217: 48 8b 78 10 mov 0x10(%rax),%rdi - 44021b: 48 85 ff test %rdi,%rdi - 44021e: 74 12 je 440232 - 440220: 48 89 de mov %rbx,%rsi - 440223: 48 89 44 24 08 mov %rax,0x8(%rsp) - 440228: e8 73 fb ff ff callq 43fda0 - 44022d: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 440232: 48 8b 38 mov (%rax),%rdi - 440235: 48 89 44 24 08 mov %rax,0x8(%rsp) - 44023a: ff d3 callq *%rbx - 44023c: 48 8b 44 24 08 mov 0x8(%rsp),%rax - 440241: 48 89 c7 mov %rax,%rdi - 440244: e8 67 db fd ff callq 41ddb0 <__cfree> - 440249: 49 8b 3f mov (%r15),%rdi - 44024c: ff d3 callq *%rbx - 44024e: 4c 89 ff mov %r15,%rdi - 440251: e8 5a db fd ff callq 41ddb0 <__cfree> - 440256: 49 8b 3e mov (%r14),%rdi - 440259: ff d3 callq *%rbx - 44025b: 4c 89 f7 mov %r14,%rdi - 44025e: e8 4d db fd ff callq 41ddb0 <__cfree> - 440263: 49 8b 7d 00 mov 0x0(%r13),%rdi - 440267: ff d3 callq *%rbx - 440269: 4c 89 ef mov %r13,%rdi - 44026c: e8 3f db fd ff callq 41ddb0 <__cfree> - 440271: 48 8b 7d 00 mov 0x0(%rbp),%rdi - 440275: ff d3 callq *%rbx - 440277: 48 89 ef mov %rbp,%rdi - 44027a: e8 31 db fd ff callq 41ddb0 <__cfree> - 44027f: 49 8b 3c 24 mov (%r12),%rdi - 440283: ff d3 callq *%rbx - 440285: 48 83 c4 18 add $0x18,%rsp - 440289: 4c 89 e7 mov %r12,%rdi - 44028c: 5b pop %rbx - 44028d: 5d pop %rbp - 44028e: 41 5c pop %r12 - 440290: 41 5d pop %r13 - 440292: 41 5e pop %r14 - 440294: 41 5f pop %r15 - 440296: e9 15 db fd ff jmpq 41ddb0 <__cfree> - 44029b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - -00000000004402a0 <__tsearch>: - 4402a0: 41 57 push %r15 - 4402a2: 41 56 push %r14 - 4402a4: 41 55 push %r13 - 4402a6: 41 54 push %r12 - 4402a8: 55 push %rbp - 4402a9: 53 push %rbx - 4402aa: 48 83 ec 28 sub $0x28,%rsp - 4402ae: 48 85 f6 test %rsi,%rsi - 4402b1: 48 89 7c 24 10 mov %rdi,0x10(%rsp) - 4402b6: 48 89 54 24 18 mov %rdx,0x18(%rsp) - 4402bb: 0f 84 12 03 00 00 je 4405d3 <__tsearch+0x333> - 4402c1: 48 8b 06 mov (%rsi),%rax - 4402c4: 49 89 f4 mov %rsi,%r12 - 4402c7: 48 85 c0 test %rax,%rax - 4402ca: 0f 84 60 02 00 00 je 440530 <__tsearch+0x290> - 4402d0: 80 60 18 fe andb $0xfe,0x18(%rax) - 4402d4: c7 44 24 08 00 00 00 movl $0x0,0x8(%rsp) - 4402db: 00 - 4402dc: 45 31 f6 xor %r14d,%r14d - 4402df: 48 8b 1e mov (%rsi),%rbx - 4402e2: 31 ed xor %ebp,%ebp - 4402e4: 45 31 ed xor %r13d,%r13d - 4402e7: eb 29 jmp 440312 <__tsearch+0x72> - 4402e9: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4402f0: 48 8d 53 10 lea 0x10(%rbx),%rdx - 4402f4: 48 8b 5b 10 mov 0x10(%rbx),%rbx - 4402f8: 4c 89 ed mov %r13,%rbp - 4402fb: 44 89 74 24 08 mov %r14d,0x8(%rsp) - 440300: 48 85 db test %rbx,%rbx - 440303: 0f 84 f9 00 00 00 je 440402 <__tsearch+0x162> - 440309: 4d 89 e5 mov %r12,%r13 - 44030c: 45 89 fe mov %r15d,%r14d - 44030f: 49 89 d4 mov %rdx,%r12 - 440312: 48 85 db test %rbx,%rbx - 440315: 0f 84 15 02 00 00 je 440530 <__tsearch+0x290> - 44031b: 48 8b 33 mov (%rbx),%rsi - 44031e: 48 8b 7c 24 10 mov 0x10(%rsp),%rdi - 440323: 48 8b 44 24 18 mov 0x18(%rsp),%rax - 440328: ff d0 callq *%rax - 44032a: 85 c0 test %eax,%eax - 44032c: 41 89 c7 mov %eax,%r15d - 44032f: 0f 84 3b 02 00 00 je 440570 <__tsearch+0x2d0> - 440335: 49 8b 04 24 mov (%r12),%rax - 440339: 48 8b 50 10 mov 0x10(%rax),%rdx - 44033d: 48 85 d2 test %rdx,%rdx - 440340: 0f 84 9a 00 00 00 je 4403e0 <__tsearch+0x140> - 440346: 48 8b 70 08 mov 0x8(%rax),%rsi - 44034a: 48 85 f6 test %rsi,%rsi - 44034d: 0f 84 8d 00 00 00 je 4403e0 <__tsearch+0x140> - 440353: f6 42 18 01 testb $0x1,0x18(%rdx) - 440357: 0f 84 83 00 00 00 je 4403e0 <__tsearch+0x140> - 44035d: f6 46 18 01 testb $0x1,0x18(%rsi) - 440361: 74 7d je 4403e0 <__tsearch+0x140> - 440363: 80 48 18 01 orb $0x1,0x18(%rax) - 440367: 80 62 18 fe andb $0xfe,0x18(%rdx) - 44036b: 48 8b 50 08 mov 0x8(%rax),%rdx - 44036f: 48 85 d2 test %rdx,%rdx - 440372: 74 04 je 440378 <__tsearch+0xd8> - 440374: 80 62 18 fe andb $0xfe,0x18(%rdx) - 440378: 4d 85 ed test %r13,%r13 - 44037b: 74 63 je 4403e0 <__tsearch+0x140> - 44037d: 49 8b 55 00 mov 0x0(%r13),%rdx - 440381: 0f b6 72 18 movzbl 0x18(%rdx),%esi - 440385: 40 f6 c6 01 test $0x1,%sil - 440389: 74 55 je 4403e0 <__tsearch+0x140> - 44038b: 8b 4c 24 08 mov 0x8(%rsp),%ecx - 44038f: 45 85 f6 test %r14d,%r14d - 440392: 48 8b 7d 00 mov 0x0(%rbp),%rdi - 440396: 41 0f 9f c3 setg %r11b - 44039a: 85 c9 test %ecx,%ecx - 44039c: 41 0f 9f c2 setg %r10b - 4403a0: 45 38 d3 cmp %r10b,%r11b - 4403a3: 0f 84 37 01 00 00 je 4404e0 <__tsearch+0x240> - 4403a9: 83 ce 01 or $0x1,%esi - 4403ac: 40 88 72 18 mov %sil,0x18(%rdx) - 4403b0: 80 4f 18 01 orb $0x1,0x18(%rdi) - 4403b4: 80 60 18 fe andb $0xfe,0x18(%rax) - 4403b8: 45 85 f6 test %r14d,%r14d - 4403bb: 0f 88 4f 01 00 00 js 440510 <__tsearch+0x270> - 4403c1: 48 8b 70 08 mov 0x8(%rax),%rsi - 4403c5: 48 89 72 10 mov %rsi,0x10(%rdx) - 4403c9: 48 89 50 08 mov %rdx,0x8(%rax) - 4403cd: 48 8b 50 10 mov 0x10(%rax),%rdx - 4403d1: 48 89 57 08 mov %rdx,0x8(%rdi) - 4403d5: 48 89 78 10 mov %rdi,0x10(%rax) - 4403d9: 48 89 45 00 mov %rax,0x0(%rbp) - 4403dd: 0f 1f 00 nopl (%rax) - 4403e0: 45 85 ff test %r15d,%r15d - 4403e3: 0f 89 07 ff ff ff jns 4402f0 <__tsearch+0x50> - 4403e9: 48 8d 53 08 lea 0x8(%rbx),%rdx - 4403ed: 48 8b 5b 08 mov 0x8(%rbx),%rbx - 4403f1: 4c 89 ed mov %r13,%rbp - 4403f4: 44 89 74 24 08 mov %r14d,0x8(%rsp) - 4403f9: 48 85 db test %rbx,%rbx - 4403fc: 0f 85 07 ff ff ff jne 440309 <__tsearch+0x69> - 440402: bf 20 00 00 00 mov $0x20,%edi - 440407: 48 89 54 24 08 mov %rdx,0x8(%rsp) - 44040c: e8 ff d5 fd ff callq 41da10 <__libc_malloc> - 440411: 48 85 c0 test %rax,%rax - 440414: 48 89 c6 mov %rax,%rsi - 440417: 0f 84 b6 01 00 00 je 4405d3 <__tsearch+0x333> - 44041d: 48 8b 54 24 08 mov 0x8(%rsp),%rdx - 440422: 48 89 02 mov %rax,(%rdx) - 440425: 48 8b 44 24 10 mov 0x10(%rsp),%rax - 44042a: 80 4e 18 01 orb $0x1,0x18(%rsi) - 44042e: 49 39 d4 cmp %rdx,%r12 - 440431: 48 c7 46 10 00 00 00 movq $0x0,0x10(%rsi) - 440438: 00 - 440439: 48 c7 46 08 00 00 00 movq $0x0,0x8(%rsi) - 440440: 00 - 440441: 48 89 06 mov %rax,(%rsi) - 440444: 0f 84 a1 01 00 00 je 4405eb <__tsearch+0x34b> - 44044a: 48 8b 12 mov (%rdx),%rdx - 44044d: 48 8b 42 10 mov 0x10(%rdx),%rax - 440451: 80 4a 18 01 orb $0x1,0x18(%rdx) - 440455: 48 85 c0 test %rax,%rax - 440458: 74 04 je 44045e <__tsearch+0x1be> - 44045a: 80 60 18 fe andb $0xfe,0x18(%rax) - 44045e: 48 8b 42 08 mov 0x8(%rdx),%rax - 440462: 48 85 c0 test %rax,%rax - 440465: 74 04 je 44046b <__tsearch+0x1cb> - 440467: 80 60 18 fe andb $0xfe,0x18(%rax) - 44046b: 49 8b 0c 24 mov (%r12),%rcx - 44046f: 48 89 f0 mov %rsi,%rax - 440472: 0f b6 79 18 movzbl 0x18(%rcx),%edi - 440476: 40 f6 c7 01 test $0x1,%dil - 44047a: 74 53 je 4404cf <__tsearch+0x22f> - 44047c: 45 85 ff test %r15d,%r15d - 44047f: 4d 8b 55 00 mov 0x0(%r13),%r10 - 440483: 41 0f 9f c3 setg %r11b - 440487: 45 85 f6 test %r14d,%r14d - 44048a: 41 0f 9f c1 setg %r9b - 44048e: 45 38 cb cmp %r9b,%r11b - 440491: 0f 84 eb 00 00 00 je 440582 <__tsearch+0x2e2> - 440497: 83 cf 01 or $0x1,%edi - 44049a: 40 88 79 18 mov %dil,0x18(%rcx) - 44049e: 41 80 4a 18 01 orb $0x1,0x18(%r10) - 4404a3: 80 62 18 fe andb $0xfe,0x18(%rdx) - 4404a7: 45 85 ff test %r15d,%r15d - 4404aa: 0f 88 06 01 00 00 js 4405b6 <__tsearch+0x316> - 4404b0: 48 8b 42 08 mov 0x8(%rdx),%rax - 4404b4: 48 89 41 10 mov %rax,0x10(%rcx) - 4404b8: 48 8b 42 10 mov 0x10(%rdx),%rax - 4404bc: 48 89 4a 08 mov %rcx,0x8(%rdx) - 4404c0: 49 89 42 08 mov %rax,0x8(%r10) - 4404c4: 4c 89 52 10 mov %r10,0x10(%rdx) - 4404c8: 49 89 55 00 mov %rdx,0x0(%r13) - 4404cc: 48 89 f0 mov %rsi,%rax - 4404cf: 48 83 c4 28 add $0x28,%rsp - 4404d3: 5b pop %rbx - 4404d4: 5d pop %rbp - 4404d5: 41 5c pop %r12 - 4404d7: 41 5d pop %r13 - 4404d9: 41 5e pop %r14 - 4404db: 41 5f pop %r15 - 4404dd: c3 retq - 4404de: 66 90 xchg %ax,%ax - 4404e0: 48 89 55 00 mov %rdx,0x0(%rbp) - 4404e4: 80 62 18 fe andb $0xfe,0x18(%rdx) - 4404e8: 80 4f 18 01 orb $0x1,0x18(%rdi) - 4404ec: 45 85 f6 test %r14d,%r14d - 4404ef: 0f 88 b0 00 00 00 js 4405a5 <__tsearch+0x305> - 4404f5: 48 8b 42 08 mov 0x8(%rdx),%rax - 4404f9: 48 89 47 10 mov %rax,0x10(%rdi) - 4404fd: 48 89 7a 08 mov %rdi,0x8(%rdx) - 440501: e9 da fe ff ff jmpq 4403e0 <__tsearch+0x140> - 440506: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 44050d: 00 00 00 - 440510: 48 8b 70 10 mov 0x10(%rax),%rsi - 440514: 48 89 72 08 mov %rsi,0x8(%rdx) - 440518: 48 89 50 10 mov %rdx,0x10(%rax) - 44051c: 48 8b 50 08 mov 0x8(%rax),%rdx - 440520: 48 89 57 10 mov %rdx,0x10(%rdi) - 440524: 48 89 78 08 mov %rdi,0x8(%rax) - 440528: e9 ac fe ff ff jmpq 4403d9 <__tsearch+0x139> - 44052d: 0f 1f 00 nopl (%rax) - 440530: bf 20 00 00 00 mov $0x20,%edi - 440535: e8 d6 d4 fd ff callq 41da10 <__libc_malloc> - 44053a: 48 85 c0 test %rax,%rax - 44053d: 74 90 je 4404cf <__tsearch+0x22f> - 44053f: 48 8b 4c 24 10 mov 0x10(%rsp),%rcx - 440544: 49 89 04 24 mov %rax,(%r12) - 440548: 80 48 18 01 orb $0x1,0x18(%rax) - 44054c: 48 c7 40 10 00 00 00 movq $0x0,0x10(%rax) - 440553: 00 - 440554: 48 c7 40 08 00 00 00 movq $0x0,0x8(%rax) - 44055b: 00 - 44055c: 48 89 08 mov %rcx,(%rax) - 44055f: 48 83 c4 28 add $0x28,%rsp - 440563: 5b pop %rbx - 440564: 5d pop %rbp - 440565: 41 5c pop %r12 - 440567: 41 5d pop %r13 - 440569: 41 5e pop %r14 - 44056b: 41 5f pop %r15 - 44056d: c3 retq - 44056e: 66 90 xchg %ax,%ax - 440570: 48 83 c4 28 add $0x28,%rsp - 440574: 48 89 d8 mov %rbx,%rax - 440577: 5b pop %rbx - 440578: 5d pop %rbp - 440579: 41 5c pop %r12 - 44057b: 41 5d pop %r13 - 44057d: 41 5e pop %r14 - 44057f: 41 5f pop %r15 - 440581: c3 retq - 440582: 49 89 4d 00 mov %rcx,0x0(%r13) - 440586: 80 61 18 fe andb $0xfe,0x18(%rcx) - 44058a: 41 80 4a 18 01 orb $0x1,0x18(%r10) - 44058f: 45 85 ff test %r15d,%r15d - 440592: 78 46 js 4405da <__tsearch+0x33a> - 440594: 48 8b 51 08 mov 0x8(%rcx),%rdx - 440598: 49 89 52 10 mov %rdx,0x10(%r10) - 44059c: 4c 89 51 08 mov %r10,0x8(%rcx) - 4405a0: e9 2a ff ff ff jmpq 4404cf <__tsearch+0x22f> - 4405a5: 48 8b 42 10 mov 0x10(%rdx),%rax - 4405a9: 48 89 47 08 mov %rax,0x8(%rdi) - 4405ad: 48 89 7a 10 mov %rdi,0x10(%rdx) - 4405b1: e9 2a fe ff ff jmpq 4403e0 <__tsearch+0x140> - 4405b6: 48 8b 42 10 mov 0x10(%rdx),%rax - 4405ba: 48 89 41 08 mov %rax,0x8(%rcx) - 4405be: 48 8b 42 08 mov 0x8(%rdx),%rax - 4405c2: 48 89 4a 10 mov %rcx,0x10(%rdx) - 4405c6: 49 89 42 10 mov %rax,0x10(%r10) - 4405ca: 4c 89 52 08 mov %r10,0x8(%rdx) - 4405ce: e9 f5 fe ff ff jmpq 4404c8 <__tsearch+0x228> - 4405d3: 31 c0 xor %eax,%eax - 4405d5: e9 f5 fe ff ff jmpq 4404cf <__tsearch+0x22f> - 4405da: 48 8b 51 10 mov 0x10(%rcx),%rdx - 4405de: 49 89 52 08 mov %rdx,0x8(%r10) - 4405e2: 4c 89 51 10 mov %r10,0x10(%rcx) - 4405e6: e9 e4 fe ff ff jmpq 4404cf <__tsearch+0x22f> - 4405eb: 48 89 f0 mov %rsi,%rax - 4405ee: e9 dc fe ff ff jmpq 4404cf <__tsearch+0x22f> - 4405f3: 0f 1f 00 nopl (%rax) - 4405f6: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 4405fd: 00 00 00 - -0000000000440600 <__tfind>: - 440600: 48 85 f6 test %rsi,%rsi - 440603: 74 4b je 440650 <__tfind+0x50> - 440605: 41 54 push %r12 - 440607: 49 89 fc mov %rdi,%r12 - 44060a: 55 push %rbp - 44060b: 48 89 d5 mov %rdx,%rbp - 44060e: 53 push %rbx - 44060f: eb 21 jmp 440632 <__tfind+0x32> - 440611: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 440618: 48 8b 33 mov (%rbx),%rsi - 44061b: 4c 89 e7 mov %r12,%rdi - 44061e: ff d5 callq *%rbp - 440620: 85 c0 test %eax,%eax - 440622: 74 24 je 440648 <__tfind+0x48> - 440624: 48 8d 73 08 lea 0x8(%rbx),%rsi - 440628: 48 83 c3 10 add $0x10,%rbx - 44062c: 85 c0 test %eax,%eax - 44062e: 48 0f 49 f3 cmovns %rbx,%rsi - 440632: 48 8b 1e mov (%rsi),%rbx - 440635: 48 85 db test %rbx,%rbx - 440638: 75 de jne 440618 <__tfind+0x18> - 44063a: 5b pop %rbx - 44063b: 31 c0 xor %eax,%eax - 44063d: 5d pop %rbp - 44063e: 41 5c pop %r12 - 440640: c3 retq - 440641: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 440648: 48 89 d8 mov %rbx,%rax - 44064b: 5b pop %rbx - 44064c: 5d pop %rbp - 44064d: 41 5c pop %r12 - 44064f: c3 retq - 440650: 31 c0 xor %eax,%eax - 440652: c3 retq - 440653: 0f 1f 00 nopl (%rax) - 440656: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 44065d: 00 00 00 - -0000000000440660 <__tdelete>: - 440660: 55 push %rbp - 440661: 48 89 e5 mov %rsp,%rbp - 440664: 41 57 push %r15 - 440666: 41 56 push %r14 - 440668: 41 55 push %r13 - 44066a: 41 54 push %r12 - 44066c: 53 push %rbx - 44066d: 48 83 ec 28 sub $0x28,%rsp - 440671: 48 89 7d c0 mov %rdi,-0x40(%rbp) - 440675: 48 89 55 b8 mov %rdx,-0x48(%rbp) - 440679: 48 81 ec 50 01 00 00 sub $0x150,%rsp - 440680: 4c 8d 64 24 0f lea 0xf(%rsp),%r12 - 440685: 49 83 e4 f0 and $0xfffffffffffffff0,%r12 - 440689: 48 85 f6 test %rsi,%rsi - 44068c: 74 78 je 440706 <__tdelete+0xa6> - 44068e: 4c 8b 06 mov (%rsi),%r8 - 440691: 49 89 f6 mov %rsi,%r14 - 440694: 4d 85 c0 test %r8,%r8 - 440697: 74 6d je 440706 <__tdelete+0xa6> - 440699: 4d 89 c7 mov %r8,%r15 - 44069c: 31 db xor %ebx,%ebx - 44069e: c7 45 cc 28 00 00 00 movl $0x28,-0x34(%rbp) - 4406a5: 4c 89 c0 mov %r8,%rax - 4406a8: eb 17 jmp 4406c1 <__tdelete+0x61> - 4406aa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4406b0: 49 8b 47 10 mov 0x10(%r15),%rax - 4406b4: 48 83 c3 01 add $0x1,%rbx - 4406b8: 4d 8d 77 10 lea 0x10(%r15),%r14 - 4406bc: 48 85 c0 test %rax,%rax - 4406bf: 74 45 je 440706 <__tdelete+0xa6> - 4406c1: 48 8b 30 mov (%rax),%rsi - 4406c4: 48 8b 7d c0 mov -0x40(%rbp),%rdi - 4406c8: 41 89 dd mov %ebx,%r13d - 4406cb: 48 8b 45 b8 mov -0x48(%rbp),%rax - 4406cf: ff d0 callq *%rax - 4406d1: 85 c0 test %eax,%eax - 4406d3: 41 89 c1 mov %eax,%r9d - 4406d6: 0f 84 84 00 00 00 je 440760 <__tdelete+0x100> - 4406dc: 39 5d cc cmp %ebx,-0x34(%rbp) - 4406df: 74 3f je 440720 <__tdelete+0xc0> - 4406e1: 4c 8d 2c dd 00 00 00 lea 0x0(,%rbx,8),%r13 - 4406e8: 00 - 4406e9: 45 85 c9 test %r9d,%r9d - 4406ec: 4f 89 34 2c mov %r14,(%r12,%r13,1) - 4406f0: 4d 8b 3e mov (%r14),%r15 - 4406f3: 79 bb jns 4406b0 <__tdelete+0x50> - 4406f5: 49 8b 47 08 mov 0x8(%r15),%rax - 4406f9: 48 83 c3 01 add $0x1,%rbx - 4406fd: 4d 8d 77 08 lea 0x8(%r15),%r14 - 440701: 48 85 c0 test %rax,%rax - 440704: 75 bb jne 4406c1 <__tdelete+0x61> - 440706: 48 8d 65 d8 lea -0x28(%rbp),%rsp - 44070a: 31 c0 xor %eax,%eax - 44070c: 5b pop %rbx - 44070d: 41 5c pop %r12 - 44070f: 41 5d pop %r13 - 440711: 41 5e pop %r14 - 440713: 41 5f pop %r15 - 440715: 5d pop %rbp - 440716: c3 retq - 440717: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 44071e: 00 00 - 440720: 83 45 cc 14 addl $0x14,-0x34(%rbp) - 440724: 4c 8d 2c dd 00 00 00 lea 0x0(,%rbx,8),%r13 - 44072b: 00 - 44072c: 4c 89 e6 mov %r12,%rsi - 44072f: 48 63 45 cc movslq -0x34(%rbp),%rax - 440733: 44 89 4d b0 mov %r9d,-0x50(%rbp) - 440737: 4c 89 ea mov %r13,%rdx - 44073a: 48 8d 04 c5 1e 00 00 lea 0x1e(,%rax,8),%rax - 440741: 00 - 440742: 48 83 e0 f0 and $0xfffffffffffffff0,%rax - 440746: 48 29 c4 sub %rax,%rsp - 440749: 48 8d 7c 24 0f lea 0xf(%rsp),%rdi - 44074e: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi - 440752: e8 c9 b8 fe ff callq 42c020 - 440757: 44 8b 4d b0 mov -0x50(%rbp),%r9d - 44075b: 49 89 c4 mov %rax,%r12 - 44075e: eb 89 jmp 4406e9 <__tdelete+0x89> - 440760: 4d 8b 06 mov (%r14),%r8 - 440763: 49 8b 70 08 mov 0x8(%r8),%rsi - 440767: 49 8b 58 10 mov 0x10(%r8),%rbx - 44076b: 48 85 f6 test %rsi,%rsi - 44076e: 0f 84 94 00 00 00 je 440808 <__tdelete+0x1a8> - 440774: 48 85 db test %rbx,%rbx - 440777: 0f 84 8b 00 00 00 je 440808 <__tdelete+0x1a8> - 44077d: 49 63 c5 movslq %r13d,%rax - 440780: 4d 8d 48 10 lea 0x10(%r8),%r9 - 440784: 48 8d 0c c5 00 00 00 lea 0x0(,%rax,8),%rcx - 44078b: 00 - 44078c: eb 28 jmp 4407b6 <__tdelete+0x156> - 44078e: 66 90 xchg %ax,%ax - 440790: 48 8b 43 08 mov 0x8(%rbx),%rax - 440794: 41 83 c5 01 add $0x1,%r13d - 440798: 4d 89 34 0c mov %r14,(%r12,%rcx,1) - 44079c: 48 83 c1 08 add $0x8,%rcx - 4407a0: 48 85 c0 test %rax,%rax - 4407a3: 0f 84 2f 02 00 00 je 4409d8 <__tdelete+0x378> - 4407a9: 48 8d 53 08 lea 0x8(%rbx),%rdx - 4407ad: 4d 89 ce mov %r9,%r14 - 4407b0: 48 89 c3 mov %rax,%rbx - 4407b3: 49 89 d1 mov %rdx,%r9 - 4407b6: 44 39 6d cc cmp %r13d,-0x34(%rbp) - 4407ba: 75 d4 jne 440790 <__tdelete+0x130> - 4407bc: 83 45 cc 14 addl $0x14,-0x34(%rbp) - 4407c0: 48 89 ca mov %rcx,%rdx - 4407c3: 4c 89 e6 mov %r12,%rsi - 4407c6: 48 63 45 cc movslq -0x34(%rbp),%rax - 4407ca: 4c 89 45 b0 mov %r8,-0x50(%rbp) - 4407ce: 4c 89 4d b8 mov %r9,-0x48(%rbp) - 4407d2: 48 89 4d c0 mov %rcx,-0x40(%rbp) - 4407d6: 48 8d 04 c5 1e 00 00 lea 0x1e(,%rax,8),%rax - 4407dd: 00 - 4407de: 48 83 e0 f0 and $0xfffffffffffffff0,%rax - 4407e2: 48 29 c4 sub %rax,%rsp - 4407e5: 48 8d 7c 24 0f lea 0xf(%rsp),%rdi - 4407ea: 48 83 e7 f0 and $0xfffffffffffffff0,%rdi - 4407ee: e8 2d b8 fe ff callq 42c020 - 4407f3: 4c 8b 45 b0 mov -0x50(%rbp),%r8 - 4407f7: 49 89 c4 mov %rax,%r12 - 4407fa: 4c 8b 4d b8 mov -0x48(%rbp),%r9 - 4407fe: 48 8b 4d c0 mov -0x40(%rbp),%rcx - 440802: eb 8c jmp 440790 <__tdelete+0x130> - 440804: 0f 1f 40 00 nopl 0x0(%rax) - 440808: 48 85 f6 test %rsi,%rsi - 44080b: 48 0f 44 f3 cmove %rbx,%rsi - 44080f: 45 85 ed test %r13d,%r13d - 440812: 0f 85 69 02 00 00 jne 440a81 <__tdelete+0x421> - 440818: 49 89 36 mov %rsi,(%r14) - 44081b: 4c 89 c3 mov %r8,%rbx - 44081e: 49 39 d8 cmp %rbx,%r8 - 440821: 74 06 je 440829 <__tdelete+0x1c9> - 440823: 48 8b 03 mov (%rbx),%rax - 440826: 49 89 00 mov %rax,(%r8) - 440829: f6 43 18 01 testb $0x1,0x18(%rbx) - 44082d: 0f 85 b6 00 00 00 jne 4408e9 <__tdelete+0x289> - 440833: 45 85 ed test %r13d,%r13d - 440836: 0f 84 56 02 00 00 je 440a92 <__tdelete+0x432> - 44083c: 48 85 f6 test %rsi,%rsi - 44083f: 74 0a je 44084b <__tdelete+0x1eb> - 440841: f6 46 18 01 testb $0x1,0x18(%rsi) - 440845: 0f 85 7d 01 00 00 jne 4409c8 <__tdelete+0x368> - 44084b: 4d 63 cd movslq %r13d,%r9 - 44084e: 4b 8b 7c cc f8 mov -0x8(%r12,%r9,8),%rdi - 440853: 48 8b 17 mov (%rdi),%rdx - 440856: 48 8b 42 08 mov 0x8(%rdx),%rax - 44085a: 48 39 f0 cmp %rsi,%rax - 44085d: 0f 84 ed 00 00 00 je 440950 <__tdelete+0x2f0> - 440863: 0f b6 48 18 movzbl 0x18(%rax),%ecx - 440867: f6 c1 01 test $0x1,%cl - 44086a: 74 29 je 440895 <__tdelete+0x235> - 44086c: 83 e1 fe and $0xfffffffe,%ecx - 44086f: 41 83 c5 01 add $0x1,%r13d - 440873: 88 48 18 mov %cl,0x18(%rax) - 440876: 80 4a 18 01 orb $0x1,0x18(%rdx) - 44087a: 48 8b 48 10 mov 0x10(%rax),%rcx - 44087e: 48 89 4a 08 mov %rcx,0x8(%rdx) - 440882: 48 89 50 10 mov %rdx,0x10(%rax) - 440886: 48 89 07 mov %rax,(%rdi) - 440889: 48 8d 78 10 lea 0x10(%rax),%rdi - 44088d: 48 8b 42 08 mov 0x8(%rdx),%rax - 440891: 4b 89 3c cc mov %rdi,(%r12,%r9,8) - 440895: 48 8b 48 10 mov 0x10(%rax),%rcx - 440899: 48 85 c9 test %rcx,%rcx - 44089c: 74 6a je 440908 <__tdelete+0x2a8> - 44089e: f6 41 18 01 testb $0x1,0x18(%rcx) - 4408a2: 74 64 je 440908 <__tdelete+0x2a8> - 4408a4: 48 8b 70 08 mov 0x8(%rax),%rsi - 4408a8: 48 85 f6 test %rsi,%rsi - 4408ab: 74 06 je 4408b3 <__tdelete+0x253> - 4408ad: f6 46 18 01 testb $0x1,0x18(%rsi) - 4408b1: 75 6c jne 44091f <__tdelete+0x2bf> - 4408b3: 0f b6 72 18 movzbl 0x18(%rdx),%esi - 4408b7: 44 0f b6 49 18 movzbl 0x18(%rcx),%r9d - 4408bc: 83 e6 01 and $0x1,%esi - 4408bf: 41 83 e1 fe and $0xfffffffe,%r9d - 4408c3: 44 09 ce or %r9d,%esi - 4408c6: 40 88 71 18 mov %sil,0x18(%rcx) - 4408ca: 48 8b 71 10 mov 0x10(%rcx),%rsi - 4408ce: 48 89 72 08 mov %rsi,0x8(%rdx) - 4408d2: 48 8b 71 08 mov 0x8(%rcx),%rsi - 4408d6: 48 89 70 10 mov %rsi,0x10(%rax) - 4408da: 48 89 41 08 mov %rax,0x8(%rcx) - 4408de: 48 89 51 10 mov %rdx,0x10(%rcx) - 4408e2: 48 89 0f mov %rcx,(%rdi) - 4408e5: 80 62 18 fe andb $0xfe,0x18(%rdx) - 4408e9: 48 89 df mov %rbx,%rdi - 4408ec: e8 bf d4 fd ff callq 41ddb0 <__cfree> - 4408f1: 48 8d 65 d8 lea -0x28(%rbp),%rsp - 4408f5: 4c 89 f8 mov %r15,%rax - 4408f8: 5b pop %rbx - 4408f9: 41 5c pop %r12 - 4408fb: 41 5d pop %r13 - 4408fd: 41 5e pop %r14 - 4408ff: 41 5f pop %r15 - 440901: 5d pop %rbp - 440902: c3 retq - 440903: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 440908: 48 8b 70 08 mov 0x8(%rax),%rsi - 44090c: 48 85 f6 test %rsi,%rsi - 44090f: 0f 84 9b 00 00 00 je 4409b0 <__tdelete+0x350> - 440915: f6 46 18 01 testb $0x1,0x18(%rsi) - 440919: 0f 84 91 00 00 00 je 4409b0 <__tdelete+0x350> - 44091f: 44 0f b6 4a 18 movzbl 0x18(%rdx),%r9d - 440924: 44 0f b6 50 18 movzbl 0x18(%rax),%r10d - 440929: 41 83 e1 01 and $0x1,%r9d - 44092d: 41 83 e2 fe and $0xfffffffe,%r10d - 440931: 45 09 d1 or %r10d,%r9d - 440934: 44 88 48 18 mov %r9b,0x18(%rax) - 440938: 80 62 18 fe andb $0xfe,0x18(%rdx) - 44093c: 80 66 18 fe andb $0xfe,0x18(%rsi) - 440940: 48 89 4a 08 mov %rcx,0x8(%rdx) - 440944: 48 89 50 10 mov %rdx,0x10(%rax) - 440948: 48 89 07 mov %rax,(%rdi) - 44094b: eb 9c jmp 4408e9 <__tdelete+0x289> - 44094d: 0f 1f 00 nopl (%rax) - 440950: 48 8b 42 10 mov 0x10(%rdx),%rax - 440954: 0f b6 48 18 movzbl 0x18(%rax),%ecx - 440958: f6 c1 01 test $0x1,%cl - 44095b: 74 29 je 440986 <__tdelete+0x326> - 44095d: 83 e1 fe and $0xfffffffe,%ecx - 440960: 41 83 c5 01 add $0x1,%r13d - 440964: 88 48 18 mov %cl,0x18(%rax) - 440967: 80 4a 18 01 orb $0x1,0x18(%rdx) - 44096b: 48 8b 48 08 mov 0x8(%rax),%rcx - 44096f: 48 89 4a 10 mov %rcx,0x10(%rdx) - 440973: 48 89 50 08 mov %rdx,0x8(%rax) - 440977: 48 89 07 mov %rax,(%rdi) - 44097a: 48 8d 78 08 lea 0x8(%rax),%rdi - 44097e: 48 8b 42 10 mov 0x10(%rdx),%rax - 440982: 4b 89 3c cc mov %rdi,(%r12,%r9,8) - 440986: 48 8b 48 08 mov 0x8(%rax),%rcx - 44098a: 48 85 c9 test %rcx,%rcx - 44098d: 74 06 je 440995 <__tdelete+0x335> - 44098f: f6 41 18 01 testb $0x1,0x18(%rcx) - 440993: 75 6b jne 440a00 <__tdelete+0x3a0> - 440995: 48 8b 70 10 mov 0x10(%rax),%rsi - 440999: 48 85 f6 test %rsi,%rsi - 44099c: 74 12 je 4409b0 <__tdelete+0x350> - 44099e: f6 46 18 01 testb $0x1,0x18(%rsi) - 4409a2: 0f 85 a8 00 00 00 jne 440a50 <__tdelete+0x3f0> - 4409a8: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 4409af: 00 - 4409b0: 80 48 18 01 orb $0x1,0x18(%rax) - 4409b4: 41 83 ed 01 sub $0x1,%r13d - 4409b8: 48 89 d6 mov %rdx,%rsi - 4409bb: 0f 85 7b fe ff ff jne 44083c <__tdelete+0x1dc> - 4409c1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4409c8: 80 66 18 fe andb $0xfe,0x18(%rsi) - 4409cc: e9 18 ff ff ff jmpq 4408e9 <__tdelete+0x289> - 4409d1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 4409d8: 48 8b 73 10 mov 0x10(%rbx),%rsi - 4409dc: 49 63 c5 movslq %r13d,%rax - 4409df: 49 8b 44 c4 f8 mov -0x8(%r12,%rax,8),%rax - 4409e4: 48 8b 00 mov (%rax),%rax - 4409e7: 48 39 58 10 cmp %rbx,0x10(%rax) - 4409eb: 0f 84 98 00 00 00 je 440a89 <__tdelete+0x429> - 4409f1: 48 89 70 08 mov %rsi,0x8(%rax) - 4409f5: e9 24 fe ff ff jmpq 44081e <__tdelete+0x1be> - 4409fa: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 440a00: 48 8b 70 10 mov 0x10(%rax),%rsi - 440a04: 48 85 f6 test %rsi,%rsi - 440a07: 74 06 je 440a0f <__tdelete+0x3af> - 440a09: f6 46 18 01 testb $0x1,0x18(%rsi) - 440a0d: 75 41 jne 440a50 <__tdelete+0x3f0> - 440a0f: 0f b6 72 18 movzbl 0x18(%rdx),%esi - 440a13: 44 0f b6 49 18 movzbl 0x18(%rcx),%r9d - 440a18: 83 e6 01 and $0x1,%esi - 440a1b: 41 83 e1 fe and $0xfffffffe,%r9d - 440a1f: 44 09 ce or %r9d,%esi - 440a22: 40 88 71 18 mov %sil,0x18(%rcx) - 440a26: 48 8b 71 08 mov 0x8(%rcx),%rsi - 440a2a: 48 89 72 10 mov %rsi,0x10(%rdx) - 440a2e: 48 8b 71 10 mov 0x10(%rcx),%rsi - 440a32: 48 89 70 08 mov %rsi,0x8(%rax) - 440a36: 48 89 41 10 mov %rax,0x10(%rcx) - 440a3a: 48 89 51 08 mov %rdx,0x8(%rcx) - 440a3e: 48 89 0f mov %rcx,(%rdi) - 440a41: 80 62 18 fe andb $0xfe,0x18(%rdx) - 440a45: e9 9f fe ff ff jmpq 4408e9 <__tdelete+0x289> - 440a4a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 440a50: 44 0f b6 4a 18 movzbl 0x18(%rdx),%r9d - 440a55: 44 0f b6 50 18 movzbl 0x18(%rax),%r10d - 440a5a: 41 83 e1 01 and $0x1,%r9d - 440a5e: 41 83 e2 fe and $0xfffffffe,%r10d - 440a62: 45 09 d1 or %r10d,%r9d - 440a65: 44 88 48 18 mov %r9b,0x18(%rax) - 440a69: 80 62 18 fe andb $0xfe,0x18(%rdx) - 440a6d: 80 66 18 fe andb $0xfe,0x18(%rsi) - 440a71: 48 89 4a 10 mov %rcx,0x10(%rdx) - 440a75: 48 89 50 08 mov %rdx,0x8(%rax) - 440a79: 48 89 07 mov %rax,(%rdi) - 440a7c: e9 68 fe ff ff jmpq 4408e9 <__tdelete+0x289> - 440a81: 4c 89 c3 mov %r8,%rbx - 440a84: e9 53 ff ff ff jmpq 4409dc <__tdelete+0x37c> - 440a89: 48 89 70 10 mov %rsi,0x10(%rax) - 440a8d: e9 8c fd ff ff jmpq 44081e <__tdelete+0x1be> - 440a92: 48 85 f6 test %rsi,%rsi - 440a95: 0f 85 2d ff ff ff jne 4409c8 <__tdelete+0x368> - 440a9b: e9 49 fe ff ff jmpq 4408e9 <__tdelete+0x289> - -0000000000440aa0 <__twalk>: - 440aa0: 41 57 push %r15 - 440aa2: 41 56 push %r14 - 440aa4: 41 55 push %r13 - 440aa6: 41 54 push %r12 - 440aa8: 55 push %rbp - 440aa9: 53 push %rbx - 440aaa: 48 83 ec 08 sub $0x8,%rsp - 440aae: 48 85 ff test %rdi,%rdi - 440ab1: 0f 84 91 0a 00 00 je 441548 <__twalk+0xaa8> - 440ab7: 48 85 f6 test %rsi,%rsi - 440aba: 48 89 f0 mov %rsi,%rax - 440abd: 0f 84 85 0a 00 00 je 441548 <__twalk+0xaa8> - 440ac3: 48 83 7f 08 00 cmpq $0x0,0x8(%rdi) - 440ac8: 0f 84 d2 0a 00 00 je 4415a0 <__twalk+0xb00> - 440ace: 48 89 fd mov %rdi,%rbp - 440ad1: 31 d2 xor %edx,%edx - 440ad3: 31 f6 xor %esi,%esi - 440ad5: 48 89 c3 mov %rax,%rbx - 440ad8: ff d0 callq *%rax - 440ada: 4c 8b 65 08 mov 0x8(%rbp),%r12 - 440ade: 4d 85 e4 test %r12,%r12 - 440ae1: 0f 84 14 05 00 00 je 440ffb <__twalk+0x55b> - 440ae7: 49 83 7c 24 08 00 cmpq $0x0,0x8(%r12) - 440aed: ba 01 00 00 00 mov $0x1,%edx - 440af2: 0f 84 88 0a 00 00 je 441580 <__twalk+0xae0> - 440af8: 31 f6 xor %esi,%esi - 440afa: 4c 89 e7 mov %r12,%rdi - 440afd: ff d3 callq *%rbx - 440aff: 4d 8b 6c 24 08 mov 0x8(%r12),%r13 - 440b04: 4d 85 ed test %r13,%r13 - 440b07: 0f 84 61 02 00 00 je 440d6e <__twalk+0x2ce> - 440b0d: 49 83 7d 08 00 cmpq $0x0,0x8(%r13) - 440b12: ba 02 00 00 00 mov $0x2,%edx - 440b17: 0f 84 db 0a 00 00 je 4415f8 <__twalk+0xb58> - 440b1d: 31 f6 xor %esi,%esi - 440b1f: 4c 89 ef mov %r13,%rdi - 440b22: ff d3 callq *%rbx - 440b24: 4d 8b 75 08 mov 0x8(%r13),%r14 - 440b28: 4d 85 f6 test %r14,%r14 - 440b2b: 0f 84 09 01 00 00 je 440c3a <__twalk+0x19a> - 440b31: 49 83 7e 08 00 cmpq $0x0,0x8(%r14) - 440b36: ba 03 00 00 00 mov $0x3,%edx - 440b3b: 0f 84 f7 0a 00 00 je 441638 <__twalk+0xb98> - 440b41: 31 f6 xor %esi,%esi - 440b43: 4c 89 f7 mov %r14,%rdi - 440b46: ff d3 callq *%rbx - 440b48: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 440b4c: 4d 85 ff test %r15,%r15 - 440b4f: 74 61 je 440bb2 <__twalk+0x112> - 440b51: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) - 440b56: ba 04 00 00 00 mov $0x4,%edx - 440b5b: 0f 84 17 0d 00 00 je 441878 <__twalk+0xdd8> - 440b61: 31 f6 xor %esi,%esi - 440b63: 4c 89 ff mov %r15,%rdi - 440b66: ff d3 callq *%rbx - 440b68: 49 8b 7f 08 mov 0x8(%r15),%rdi - 440b6c: 48 85 ff test %rdi,%rdi - 440b6f: 74 0d je 440b7e <__twalk+0xde> - 440b71: ba 05 00 00 00 mov $0x5,%edx - 440b76: 48 89 de mov %rbx,%rsi - 440b79: e8 92 f1 ff ff callq 43fd10 - 440b7e: 4c 89 ff mov %r15,%rdi - 440b81: ba 04 00 00 00 mov $0x4,%edx - 440b86: be 01 00 00 00 mov $0x1,%esi - 440b8b: ff d3 callq *%rbx - 440b8d: 49 8b 7f 10 mov 0x10(%r15),%rdi - 440b91: 48 85 ff test %rdi,%rdi - 440b94: 74 0d je 440ba3 <__twalk+0x103> - 440b96: ba 05 00 00 00 mov $0x5,%edx - 440b9b: 48 89 de mov %rbx,%rsi - 440b9e: e8 6d f1 ff ff callq 43fd10 - 440ba3: ba 04 00 00 00 mov $0x4,%edx - 440ba8: be 02 00 00 00 mov $0x2,%esi - 440bad: 4c 89 ff mov %r15,%rdi - 440bb0: ff d3 callq *%rbx - 440bb2: ba 03 00 00 00 mov $0x3,%edx - 440bb7: be 01 00 00 00 mov $0x1,%esi - 440bbc: 4c 89 f7 mov %r14,%rdi - 440bbf: ff d3 callq *%rbx - 440bc1: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 440bc5: 4d 85 ff test %r15,%r15 - 440bc8: 74 61 je 440c2b <__twalk+0x18b> - 440bca: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) - 440bcf: ba 04 00 00 00 mov $0x4,%edx - 440bd4: 0f 84 fe 0c 00 00 je 4418d8 <__twalk+0xe38> - 440bda: 31 f6 xor %esi,%esi - 440bdc: 4c 89 ff mov %r15,%rdi - 440bdf: ff d3 callq *%rbx - 440be1: 49 8b 7f 08 mov 0x8(%r15),%rdi - 440be5: 48 85 ff test %rdi,%rdi - 440be8: 74 0d je 440bf7 <__twalk+0x157> - 440bea: ba 05 00 00 00 mov $0x5,%edx - 440bef: 48 89 de mov %rbx,%rsi - 440bf2: e8 19 f1 ff ff callq 43fd10 - 440bf7: 4c 89 ff mov %r15,%rdi - 440bfa: ba 04 00 00 00 mov $0x4,%edx - 440bff: be 01 00 00 00 mov $0x1,%esi - 440c04: ff d3 callq *%rbx - 440c06: 49 8b 7f 10 mov 0x10(%r15),%rdi - 440c0a: 48 85 ff test %rdi,%rdi - 440c0d: 74 0d je 440c1c <__twalk+0x17c> - 440c0f: ba 05 00 00 00 mov $0x5,%edx - 440c14: 48 89 de mov %rbx,%rsi - 440c17: e8 f4 f0 ff ff callq 43fd10 - 440c1c: ba 04 00 00 00 mov $0x4,%edx - 440c21: be 02 00 00 00 mov $0x2,%esi - 440c26: 4c 89 ff mov %r15,%rdi - 440c29: ff d3 callq *%rbx - 440c2b: ba 03 00 00 00 mov $0x3,%edx - 440c30: be 02 00 00 00 mov $0x2,%esi - 440c35: 4c 89 f7 mov %r14,%rdi - 440c38: ff d3 callq *%rbx - 440c3a: ba 02 00 00 00 mov $0x2,%edx - 440c3f: be 01 00 00 00 mov $0x1,%esi - 440c44: 4c 89 ef mov %r13,%rdi - 440c47: ff d3 callq *%rbx - 440c49: 4d 8b 75 10 mov 0x10(%r13),%r14 - 440c4d: 4d 85 f6 test %r14,%r14 - 440c50: 0f 84 09 01 00 00 je 440d5f <__twalk+0x2bf> - 440c56: 49 83 7e 08 00 cmpq $0x0,0x8(%r14) - 440c5b: ba 03 00 00 00 mov $0x3,%edx - 440c60: 0f 84 32 0a 00 00 je 441698 <__twalk+0xbf8> - 440c66: 31 f6 xor %esi,%esi - 440c68: 4c 89 f7 mov %r14,%rdi - 440c6b: ff d3 callq *%rbx - 440c6d: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 440c71: 4d 85 ff test %r15,%r15 - 440c74: 74 61 je 440cd7 <__twalk+0x237> - 440c76: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) - 440c7b: ba 04 00 00 00 mov $0x4,%edx - 440c80: 0f 84 92 0c 00 00 je 441918 <__twalk+0xe78> - 440c86: 31 f6 xor %esi,%esi - 440c88: 4c 89 ff mov %r15,%rdi - 440c8b: ff d3 callq *%rbx - 440c8d: 49 8b 7f 08 mov 0x8(%r15),%rdi - 440c91: 48 85 ff test %rdi,%rdi - 440c94: 74 0d je 440ca3 <__twalk+0x203> - 440c96: ba 05 00 00 00 mov $0x5,%edx - 440c9b: 48 89 de mov %rbx,%rsi - 440c9e: e8 6d f0 ff ff callq 43fd10 - 440ca3: 4c 89 ff mov %r15,%rdi - 440ca6: ba 04 00 00 00 mov $0x4,%edx - 440cab: be 01 00 00 00 mov $0x1,%esi - 440cb0: ff d3 callq *%rbx - 440cb2: 49 8b 7f 10 mov 0x10(%r15),%rdi - 440cb6: 48 85 ff test %rdi,%rdi - 440cb9: 74 0d je 440cc8 <__twalk+0x228> - 440cbb: ba 05 00 00 00 mov $0x5,%edx - 440cc0: 48 89 de mov %rbx,%rsi - 440cc3: e8 48 f0 ff ff callq 43fd10 - 440cc8: ba 04 00 00 00 mov $0x4,%edx - 440ccd: be 02 00 00 00 mov $0x2,%esi - 440cd2: 4c 89 ff mov %r15,%rdi - 440cd5: ff d3 callq *%rbx - 440cd7: ba 03 00 00 00 mov $0x3,%edx - 440cdc: be 01 00 00 00 mov $0x1,%esi - 440ce1: 4c 89 f7 mov %r14,%rdi - 440ce4: ff d3 callq *%rbx - 440ce6: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 440cea: 4d 85 ff test %r15,%r15 - 440ced: 74 61 je 440d50 <__twalk+0x2b0> - 440cef: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) - 440cf4: ba 04 00 00 00 mov $0x4,%edx - 440cf9: 0f 84 f9 0b 00 00 je 4418f8 <__twalk+0xe58> - 440cff: 31 f6 xor %esi,%esi - 440d01: 4c 89 ff mov %r15,%rdi - 440d04: ff d3 callq *%rbx - 440d06: 49 8b 7f 08 mov 0x8(%r15),%rdi - 440d0a: 48 85 ff test %rdi,%rdi - 440d0d: 74 0d je 440d1c <__twalk+0x27c> - 440d0f: ba 05 00 00 00 mov $0x5,%edx - 440d14: 48 89 de mov %rbx,%rsi - 440d17: e8 f4 ef ff ff callq 43fd10 - 440d1c: 4c 89 ff mov %r15,%rdi - 440d1f: ba 04 00 00 00 mov $0x4,%edx - 440d24: be 01 00 00 00 mov $0x1,%esi - 440d29: ff d3 callq *%rbx - 440d2b: 49 8b 7f 10 mov 0x10(%r15),%rdi - 440d2f: 48 85 ff test %rdi,%rdi - 440d32: 74 0d je 440d41 <__twalk+0x2a1> - 440d34: ba 05 00 00 00 mov $0x5,%edx - 440d39: 48 89 de mov %rbx,%rsi - 440d3c: e8 cf ef ff ff callq 43fd10 - 440d41: ba 04 00 00 00 mov $0x4,%edx - 440d46: be 02 00 00 00 mov $0x2,%esi - 440d4b: 4c 89 ff mov %r15,%rdi - 440d4e: ff d3 callq *%rbx - 440d50: ba 03 00 00 00 mov $0x3,%edx - 440d55: be 02 00 00 00 mov $0x2,%esi - 440d5a: 4c 89 f7 mov %r14,%rdi - 440d5d: ff d3 callq *%rbx - 440d5f: ba 02 00 00 00 mov $0x2,%edx - 440d64: be 02 00 00 00 mov $0x2,%esi - 440d69: 4c 89 ef mov %r13,%rdi - 440d6c: ff d3 callq *%rbx - 440d6e: ba 01 00 00 00 mov $0x1,%edx - 440d73: be 01 00 00 00 mov $0x1,%esi - 440d78: 4c 89 e7 mov %r12,%rdi - 440d7b: ff d3 callq *%rbx - 440d7d: 4d 8b 6c 24 10 mov 0x10(%r12),%r13 - 440d82: 4d 85 ed test %r13,%r13 - 440d85: 0f 84 61 02 00 00 je 440fec <__twalk+0x54c> - 440d8b: 49 83 7d 08 00 cmpq $0x0,0x8(%r13) - 440d90: ba 02 00 00 00 mov $0x2,%edx - 440d95: 0f 84 1d 08 00 00 je 4415b8 <__twalk+0xb18> - 440d9b: 31 f6 xor %esi,%esi - 440d9d: 4c 89 ef mov %r13,%rdi - 440da0: ff d3 callq *%rbx - 440da2: 4d 8b 75 08 mov 0x8(%r13),%r14 - 440da6: 4d 85 f6 test %r14,%r14 - 440da9: 0f 84 09 01 00 00 je 440eb8 <__twalk+0x418> - 440daf: 49 83 7e 08 00 cmpq $0x0,0x8(%r14) - 440db4: ba 03 00 00 00 mov $0x3,%edx - 440db9: 0f 84 b9 08 00 00 je 441678 <__twalk+0xbd8> - 440dbf: 31 f6 xor %esi,%esi - 440dc1: 4c 89 f7 mov %r14,%rdi - 440dc4: ff d3 callq *%rbx - 440dc6: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 440dca: 4d 85 ff test %r15,%r15 - 440dcd: 74 61 je 440e30 <__twalk+0x390> - 440dcf: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) - 440dd4: ba 04 00 00 00 mov $0x4,%edx - 440dd9: 0f 84 d9 0a 00 00 je 4418b8 <__twalk+0xe18> - 440ddf: 31 f6 xor %esi,%esi - 440de1: 4c 89 ff mov %r15,%rdi - 440de4: ff d3 callq *%rbx - 440de6: 49 8b 7f 08 mov 0x8(%r15),%rdi - 440dea: 48 85 ff test %rdi,%rdi - 440ded: 74 0d je 440dfc <__twalk+0x35c> - 440def: ba 05 00 00 00 mov $0x5,%edx - 440df4: 48 89 de mov %rbx,%rsi - 440df7: e8 14 ef ff ff callq 43fd10 - 440dfc: 4c 89 ff mov %r15,%rdi - 440dff: ba 04 00 00 00 mov $0x4,%edx - 440e04: be 01 00 00 00 mov $0x1,%esi - 440e09: ff d3 callq *%rbx - 440e0b: 49 8b 7f 10 mov 0x10(%r15),%rdi - 440e0f: 48 85 ff test %rdi,%rdi - 440e12: 74 0d je 440e21 <__twalk+0x381> - 440e14: ba 05 00 00 00 mov $0x5,%edx - 440e19: 48 89 de mov %rbx,%rsi - 440e1c: e8 ef ee ff ff callq 43fd10 - 440e21: ba 04 00 00 00 mov $0x4,%edx - 440e26: be 02 00 00 00 mov $0x2,%esi - 440e2b: 4c 89 ff mov %r15,%rdi - 440e2e: ff d3 callq *%rbx - 440e30: ba 03 00 00 00 mov $0x3,%edx - 440e35: be 01 00 00 00 mov $0x1,%esi - 440e3a: 4c 89 f7 mov %r14,%rdi - 440e3d: ff d3 callq *%rbx - 440e3f: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 440e43: 4d 85 ff test %r15,%r15 - 440e46: 74 61 je 440ea9 <__twalk+0x409> - 440e48: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) - 440e4d: ba 04 00 00 00 mov $0x4,%edx - 440e52: 0f 84 40 0a 00 00 je 441898 <__twalk+0xdf8> - 440e58: 31 f6 xor %esi,%esi - 440e5a: 4c 89 ff mov %r15,%rdi - 440e5d: ff d3 callq *%rbx - 440e5f: 49 8b 7f 08 mov 0x8(%r15),%rdi - 440e63: 48 85 ff test %rdi,%rdi - 440e66: 74 0d je 440e75 <__twalk+0x3d5> - 440e68: ba 05 00 00 00 mov $0x5,%edx - 440e6d: 48 89 de mov %rbx,%rsi - 440e70: e8 9b ee ff ff callq 43fd10 - 440e75: 4c 89 ff mov %r15,%rdi - 440e78: ba 04 00 00 00 mov $0x4,%edx - 440e7d: be 01 00 00 00 mov $0x1,%esi - 440e82: ff d3 callq *%rbx - 440e84: 49 8b 7f 10 mov 0x10(%r15),%rdi - 440e88: 48 85 ff test %rdi,%rdi - 440e8b: 74 0d je 440e9a <__twalk+0x3fa> - 440e8d: ba 05 00 00 00 mov $0x5,%edx - 440e92: 48 89 de mov %rbx,%rsi - 440e95: e8 76 ee ff ff callq 43fd10 - 440e9a: ba 04 00 00 00 mov $0x4,%edx - 440e9f: be 02 00 00 00 mov $0x2,%esi - 440ea4: 4c 89 ff mov %r15,%rdi - 440ea7: ff d3 callq *%rbx - 440ea9: ba 03 00 00 00 mov $0x3,%edx - 440eae: be 02 00 00 00 mov $0x2,%esi - 440eb3: 4c 89 f7 mov %r14,%rdi - 440eb6: ff d3 callq *%rbx - 440eb8: ba 02 00 00 00 mov $0x2,%edx - 440ebd: be 01 00 00 00 mov $0x1,%esi - 440ec2: 4c 89 ef mov %r13,%rdi - 440ec5: ff d3 callq *%rbx - 440ec7: 4d 8b 75 10 mov 0x10(%r13),%r14 - 440ecb: 4d 85 f6 test %r14,%r14 - 440ece: 0f 84 09 01 00 00 je 440fdd <__twalk+0x53d> - 440ed4: 49 83 7e 08 00 cmpq $0x0,0x8(%r14) - 440ed9: ba 03 00 00 00 mov $0x3,%edx - 440ede: 0f 84 74 07 00 00 je 441658 <__twalk+0xbb8> - 440ee4: 31 f6 xor %esi,%esi - 440ee6: 4c 89 f7 mov %r14,%rdi - 440ee9: ff d3 callq *%rbx - 440eeb: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 440eef: 4d 85 ff test %r15,%r15 - 440ef2: 74 61 je 440f55 <__twalk+0x4b5> - 440ef4: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) - 440ef9: ba 04 00 00 00 mov $0x4,%edx - 440efe: 0f 84 54 09 00 00 je 441858 <__twalk+0xdb8> - 440f04: 31 f6 xor %esi,%esi - 440f06: 4c 89 ff mov %r15,%rdi - 440f09: ff d3 callq *%rbx - 440f0b: 49 8b 7f 08 mov 0x8(%r15),%rdi - 440f0f: 48 85 ff test %rdi,%rdi - 440f12: 74 0d je 440f21 <__twalk+0x481> - 440f14: ba 05 00 00 00 mov $0x5,%edx - 440f19: 48 89 de mov %rbx,%rsi - 440f1c: e8 ef ed ff ff callq 43fd10 - 440f21: 4c 89 ff mov %r15,%rdi - 440f24: ba 04 00 00 00 mov $0x4,%edx - 440f29: be 01 00 00 00 mov $0x1,%esi - 440f2e: ff d3 callq *%rbx - 440f30: 49 8b 7f 10 mov 0x10(%r15),%rdi - 440f34: 48 85 ff test %rdi,%rdi - 440f37: 74 0d je 440f46 <__twalk+0x4a6> - 440f39: ba 05 00 00 00 mov $0x5,%edx - 440f3e: 48 89 de mov %rbx,%rsi - 440f41: e8 ca ed ff ff callq 43fd10 - 440f46: ba 04 00 00 00 mov $0x4,%edx - 440f4b: be 02 00 00 00 mov $0x2,%esi - 440f50: 4c 89 ff mov %r15,%rdi - 440f53: ff d3 callq *%rbx - 440f55: ba 03 00 00 00 mov $0x3,%edx - 440f5a: be 01 00 00 00 mov $0x1,%esi - 440f5f: 4c 89 f7 mov %r14,%rdi - 440f62: ff d3 callq *%rbx - 440f64: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 440f68: 4d 85 ff test %r15,%r15 - 440f6b: 74 61 je 440fce <__twalk+0x52e> - 440f6d: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) - 440f72: ba 04 00 00 00 mov $0x4,%edx - 440f77: 0f 84 bb 08 00 00 je 441838 <__twalk+0xd98> - 440f7d: 31 f6 xor %esi,%esi - 440f7f: 4c 89 ff mov %r15,%rdi - 440f82: ff d3 callq *%rbx - 440f84: 49 8b 7f 08 mov 0x8(%r15),%rdi - 440f88: 48 85 ff test %rdi,%rdi - 440f8b: 74 0d je 440f9a <__twalk+0x4fa> - 440f8d: ba 05 00 00 00 mov $0x5,%edx - 440f92: 48 89 de mov %rbx,%rsi - 440f95: e8 76 ed ff ff callq 43fd10 - 440f9a: 4c 89 ff mov %r15,%rdi - 440f9d: ba 04 00 00 00 mov $0x4,%edx - 440fa2: be 01 00 00 00 mov $0x1,%esi - 440fa7: ff d3 callq *%rbx - 440fa9: 49 8b 7f 10 mov 0x10(%r15),%rdi - 440fad: 48 85 ff test %rdi,%rdi - 440fb0: 74 0d je 440fbf <__twalk+0x51f> - 440fb2: ba 05 00 00 00 mov $0x5,%edx - 440fb7: 48 89 de mov %rbx,%rsi - 440fba: e8 51 ed ff ff callq 43fd10 - 440fbf: ba 04 00 00 00 mov $0x4,%edx - 440fc4: be 02 00 00 00 mov $0x2,%esi - 440fc9: 4c 89 ff mov %r15,%rdi - 440fcc: ff d3 callq *%rbx - 440fce: ba 03 00 00 00 mov $0x3,%edx - 440fd3: be 02 00 00 00 mov $0x2,%esi - 440fd8: 4c 89 f7 mov %r14,%rdi - 440fdb: ff d3 callq *%rbx - 440fdd: ba 02 00 00 00 mov $0x2,%edx - 440fe2: be 02 00 00 00 mov $0x2,%esi - 440fe7: 4c 89 ef mov %r13,%rdi - 440fea: ff d3 callq *%rbx - 440fec: ba 01 00 00 00 mov $0x1,%edx - 440ff1: be 02 00 00 00 mov $0x2,%esi - 440ff6: 4c 89 e7 mov %r12,%rdi - 440ff9: ff d3 callq *%rbx - 440ffb: 31 d2 xor %edx,%edx - 440ffd: be 01 00 00 00 mov $0x1,%esi - 441002: 48 89 ef mov %rbp,%rdi - 441005: ff d3 callq *%rbx - 441007: 4c 8b 65 10 mov 0x10(%rbp),%r12 - 44100b: 4d 85 e4 test %r12,%r12 - 44100e: 0f 84 14 05 00 00 je 441528 <__twalk+0xa88> - 441014: 49 83 7c 24 08 00 cmpq $0x0,0x8(%r12) - 44101a: ba 01 00 00 00 mov $0x1,%edx - 44101f: 0f 84 3b 05 00 00 je 441560 <__twalk+0xac0> - 441025: 31 f6 xor %esi,%esi - 441027: 4c 89 e7 mov %r12,%rdi - 44102a: ff d3 callq *%rbx - 44102c: 4d 8b 6c 24 08 mov 0x8(%r12),%r13 - 441031: 4d 85 ed test %r13,%r13 - 441034: 0f 84 61 02 00 00 je 44129b <__twalk+0x7fb> - 44103a: 49 83 7d 08 00 cmpq $0x0,0x8(%r13) - 44103f: ba 02 00 00 00 mov $0x2,%edx - 441044: 0f 84 8e 05 00 00 je 4415d8 <__twalk+0xb38> - 44104a: 31 f6 xor %esi,%esi - 44104c: 4c 89 ef mov %r13,%rdi - 44104f: ff d3 callq *%rbx - 441051: 4d 8b 75 08 mov 0x8(%r13),%r14 - 441055: 4d 85 f6 test %r14,%r14 - 441058: 0f 84 09 01 00 00 je 441167 <__twalk+0x6c7> - 44105e: 49 83 7e 08 00 cmpq $0x0,0x8(%r14) - 441063: ba 03 00 00 00 mov $0x3,%edx - 441068: 0f 84 aa 06 00 00 je 441718 <__twalk+0xc78> - 44106e: 31 f6 xor %esi,%esi - 441070: 4c 89 f7 mov %r14,%rdi - 441073: ff d3 callq *%rbx - 441075: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 441079: 4d 85 ff test %r15,%r15 - 44107c: 74 61 je 4410df <__twalk+0x63f> - 44107e: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) - 441083: ba 04 00 00 00 mov $0x4,%edx - 441088: 0f 84 ca 06 00 00 je 441758 <__twalk+0xcb8> - 44108e: 31 f6 xor %esi,%esi - 441090: 4c 89 ff mov %r15,%rdi - 441093: ff d3 callq *%rbx - 441095: 49 8b 7f 08 mov 0x8(%r15),%rdi - 441099: 48 85 ff test %rdi,%rdi - 44109c: 74 0d je 4410ab <__twalk+0x60b> - 44109e: ba 05 00 00 00 mov $0x5,%edx - 4410a3: 48 89 de mov %rbx,%rsi - 4410a6: e8 65 ec ff ff callq 43fd10 - 4410ab: 4c 89 ff mov %r15,%rdi - 4410ae: ba 04 00 00 00 mov $0x4,%edx - 4410b3: be 01 00 00 00 mov $0x1,%esi - 4410b8: ff d3 callq *%rbx - 4410ba: 49 8b 7f 10 mov 0x10(%r15),%rdi - 4410be: 48 85 ff test %rdi,%rdi - 4410c1: 74 0d je 4410d0 <__twalk+0x630> - 4410c3: ba 05 00 00 00 mov $0x5,%edx - 4410c8: 48 89 de mov %rbx,%rsi - 4410cb: e8 40 ec ff ff callq 43fd10 - 4410d0: ba 04 00 00 00 mov $0x4,%edx - 4410d5: be 02 00 00 00 mov $0x2,%esi - 4410da: 4c 89 ff mov %r15,%rdi - 4410dd: ff d3 callq *%rbx - 4410df: ba 03 00 00 00 mov $0x3,%edx - 4410e4: be 01 00 00 00 mov $0x1,%esi - 4410e9: 4c 89 f7 mov %r14,%rdi - 4410ec: ff d3 callq *%rbx - 4410ee: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 4410f2: 4d 85 ff test %r15,%r15 - 4410f5: 74 61 je 441158 <__twalk+0x6b8> - 4410f7: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) - 4410fc: ba 04 00 00 00 mov $0x4,%edx - 441101: 0f 84 31 06 00 00 je 441738 <__twalk+0xc98> - 441107: 31 f6 xor %esi,%esi - 441109: 4c 89 ff mov %r15,%rdi - 44110c: ff d3 callq *%rbx - 44110e: 49 8b 7f 08 mov 0x8(%r15),%rdi - 441112: 48 85 ff test %rdi,%rdi - 441115: 74 0d je 441124 <__twalk+0x684> - 441117: ba 05 00 00 00 mov $0x5,%edx - 44111c: 48 89 de mov %rbx,%rsi - 44111f: e8 ec eb ff ff callq 43fd10 - 441124: 4c 89 ff mov %r15,%rdi - 441127: ba 04 00 00 00 mov $0x4,%edx - 44112c: be 01 00 00 00 mov $0x1,%esi - 441131: ff d3 callq *%rbx - 441133: 49 8b 7f 10 mov 0x10(%r15),%rdi - 441137: 48 85 ff test %rdi,%rdi - 44113a: 74 0d je 441149 <__twalk+0x6a9> - 44113c: ba 05 00 00 00 mov $0x5,%edx - 441141: 48 89 de mov %rbx,%rsi - 441144: e8 c7 eb ff ff callq 43fd10 - 441149: ba 04 00 00 00 mov $0x4,%edx - 44114e: be 02 00 00 00 mov $0x2,%esi - 441153: 4c 89 ff mov %r15,%rdi - 441156: ff d3 callq *%rbx - 441158: ba 03 00 00 00 mov $0x3,%edx - 44115d: be 02 00 00 00 mov $0x2,%esi - 441162: 4c 89 f7 mov %r14,%rdi - 441165: ff d3 callq *%rbx - 441167: ba 02 00 00 00 mov $0x2,%edx - 44116c: be 01 00 00 00 mov $0x1,%esi - 441171: 4c 89 ef mov %r13,%rdi - 441174: ff d3 callq *%rbx - 441176: 4d 8b 75 10 mov 0x10(%r13),%r14 - 44117a: 4d 85 f6 test %r14,%r14 - 44117d: 0f 84 09 01 00 00 je 44128c <__twalk+0x7ec> - 441183: 49 83 7e 08 00 cmpq $0x0,0x8(%r14) - 441188: ba 03 00 00 00 mov $0x3,%edx - 44118d: 0f 84 65 05 00 00 je 4416f8 <__twalk+0xc58> - 441193: 31 f6 xor %esi,%esi - 441195: 4c 89 f7 mov %r14,%rdi - 441198: ff d3 callq *%rbx - 44119a: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 44119e: 4d 85 ff test %r15,%r15 - 4411a1: 74 61 je 441204 <__twalk+0x764> - 4411a3: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) - 4411a8: ba 04 00 00 00 mov $0x4,%edx - 4411ad: 0f 84 65 06 00 00 je 441818 <__twalk+0xd78> - 4411b3: 31 f6 xor %esi,%esi - 4411b5: 4c 89 ff mov %r15,%rdi - 4411b8: ff d3 callq *%rbx - 4411ba: 49 8b 7f 08 mov 0x8(%r15),%rdi - 4411be: 48 85 ff test %rdi,%rdi - 4411c1: 74 0d je 4411d0 <__twalk+0x730> - 4411c3: ba 05 00 00 00 mov $0x5,%edx - 4411c8: 48 89 de mov %rbx,%rsi - 4411cb: e8 40 eb ff ff callq 43fd10 - 4411d0: 4c 89 ff mov %r15,%rdi - 4411d3: ba 04 00 00 00 mov $0x4,%edx - 4411d8: be 01 00 00 00 mov $0x1,%esi - 4411dd: ff d3 callq *%rbx - 4411df: 49 8b 7f 10 mov 0x10(%r15),%rdi - 4411e3: 48 85 ff test %rdi,%rdi - 4411e6: 74 0d je 4411f5 <__twalk+0x755> - 4411e8: ba 05 00 00 00 mov $0x5,%edx - 4411ed: 48 89 de mov %rbx,%rsi - 4411f0: e8 1b eb ff ff callq 43fd10 - 4411f5: ba 04 00 00 00 mov $0x4,%edx - 4411fa: be 02 00 00 00 mov $0x2,%esi - 4411ff: 4c 89 ff mov %r15,%rdi - 441202: ff d3 callq *%rbx - 441204: ba 03 00 00 00 mov $0x3,%edx - 441209: be 01 00 00 00 mov $0x1,%esi - 44120e: 4c 89 f7 mov %r14,%rdi - 441211: ff d3 callq *%rbx - 441213: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 441217: 4d 85 ff test %r15,%r15 - 44121a: 74 61 je 44127d <__twalk+0x7dd> - 44121c: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) - 441221: ba 04 00 00 00 mov $0x4,%edx - 441226: 0f 84 cc 05 00 00 je 4417f8 <__twalk+0xd58> - 44122c: 31 f6 xor %esi,%esi - 44122e: 4c 89 ff mov %r15,%rdi - 441231: ff d3 callq *%rbx - 441233: 49 8b 7f 08 mov 0x8(%r15),%rdi - 441237: 48 85 ff test %rdi,%rdi - 44123a: 74 0d je 441249 <__twalk+0x7a9> - 44123c: ba 05 00 00 00 mov $0x5,%edx - 441241: 48 89 de mov %rbx,%rsi - 441244: e8 c7 ea ff ff callq 43fd10 - 441249: 4c 89 ff mov %r15,%rdi - 44124c: ba 04 00 00 00 mov $0x4,%edx - 441251: be 01 00 00 00 mov $0x1,%esi - 441256: ff d3 callq *%rbx - 441258: 49 8b 7f 10 mov 0x10(%r15),%rdi - 44125c: 48 85 ff test %rdi,%rdi - 44125f: 74 0d je 44126e <__twalk+0x7ce> - 441261: ba 05 00 00 00 mov $0x5,%edx - 441266: 48 89 de mov %rbx,%rsi - 441269: e8 a2 ea ff ff callq 43fd10 - 44126e: ba 04 00 00 00 mov $0x4,%edx - 441273: be 02 00 00 00 mov $0x2,%esi - 441278: 4c 89 ff mov %r15,%rdi - 44127b: ff d3 callq *%rbx - 44127d: ba 03 00 00 00 mov $0x3,%edx - 441282: be 02 00 00 00 mov $0x2,%esi - 441287: 4c 89 f7 mov %r14,%rdi - 44128a: ff d3 callq *%rbx - 44128c: ba 02 00 00 00 mov $0x2,%edx - 441291: be 02 00 00 00 mov $0x2,%esi - 441296: 4c 89 ef mov %r13,%rdi - 441299: ff d3 callq *%rbx - 44129b: ba 01 00 00 00 mov $0x1,%edx - 4412a0: be 01 00 00 00 mov $0x1,%esi - 4412a5: 4c 89 e7 mov %r12,%rdi - 4412a8: ff d3 callq *%rbx - 4412aa: 4d 8b 6c 24 10 mov 0x10(%r12),%r13 - 4412af: 4d 85 ed test %r13,%r13 - 4412b2: 0f 84 61 02 00 00 je 441519 <__twalk+0xa79> - 4412b8: 49 83 7d 08 00 cmpq $0x0,0x8(%r13) - 4412bd: ba 02 00 00 00 mov $0x2,%edx - 4412c2: 0f 84 50 03 00 00 je 441618 <__twalk+0xb78> - 4412c8: 31 f6 xor %esi,%esi - 4412ca: 4c 89 ef mov %r13,%rdi - 4412cd: ff d3 callq *%rbx - 4412cf: 4d 8b 75 08 mov 0x8(%r13),%r14 - 4412d3: 4d 85 f6 test %r14,%r14 - 4412d6: 0f 84 09 01 00 00 je 4413e5 <__twalk+0x945> - 4412dc: 49 83 7e 08 00 cmpq $0x0,0x8(%r14) - 4412e1: ba 03 00 00 00 mov $0x3,%edx - 4412e6: 0f 84 ec 03 00 00 je 4416d8 <__twalk+0xc38> - 4412ec: 31 f6 xor %esi,%esi - 4412ee: 4c 89 f7 mov %r14,%rdi - 4412f1: ff d3 callq *%rbx - 4412f3: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 4412f7: 4d 85 ff test %r15,%r15 - 4412fa: 74 61 je 44135d <__twalk+0x8bd> - 4412fc: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) - 441301: ba 04 00 00 00 mov $0x4,%edx - 441306: 0f 84 cc 04 00 00 je 4417d8 <__twalk+0xd38> - 44130c: 31 f6 xor %esi,%esi - 44130e: 4c 89 ff mov %r15,%rdi - 441311: ff d3 callq *%rbx - 441313: 49 8b 7f 08 mov 0x8(%r15),%rdi - 441317: 48 85 ff test %rdi,%rdi - 44131a: 74 0d je 441329 <__twalk+0x889> - 44131c: ba 05 00 00 00 mov $0x5,%edx - 441321: 48 89 de mov %rbx,%rsi - 441324: e8 e7 e9 ff ff callq 43fd10 - 441329: 4c 89 ff mov %r15,%rdi - 44132c: ba 04 00 00 00 mov $0x4,%edx - 441331: be 01 00 00 00 mov $0x1,%esi - 441336: ff d3 callq *%rbx - 441338: 49 8b 7f 10 mov 0x10(%r15),%rdi - 44133c: 48 85 ff test %rdi,%rdi - 44133f: 74 0d je 44134e <__twalk+0x8ae> - 441341: ba 05 00 00 00 mov $0x5,%edx - 441346: 48 89 de mov %rbx,%rsi - 441349: e8 c2 e9 ff ff callq 43fd10 - 44134e: ba 04 00 00 00 mov $0x4,%edx - 441353: be 02 00 00 00 mov $0x2,%esi - 441358: 4c 89 ff mov %r15,%rdi - 44135b: ff d3 callq *%rbx - 44135d: ba 03 00 00 00 mov $0x3,%edx - 441362: be 01 00 00 00 mov $0x1,%esi - 441367: 4c 89 f7 mov %r14,%rdi - 44136a: ff d3 callq *%rbx - 44136c: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 441370: 4d 85 ff test %r15,%r15 - 441373: 74 61 je 4413d6 <__twalk+0x936> - 441375: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) - 44137a: ba 04 00 00 00 mov $0x4,%edx - 44137f: 0f 84 33 04 00 00 je 4417b8 <__twalk+0xd18> - 441385: 31 f6 xor %esi,%esi - 441387: 4c 89 ff mov %r15,%rdi - 44138a: ff d3 callq *%rbx - 44138c: 49 8b 7f 08 mov 0x8(%r15),%rdi - 441390: 48 85 ff test %rdi,%rdi - 441393: 74 0d je 4413a2 <__twalk+0x902> - 441395: ba 05 00 00 00 mov $0x5,%edx - 44139a: 48 89 de mov %rbx,%rsi - 44139d: e8 6e e9 ff ff callq 43fd10 - 4413a2: 4c 89 ff mov %r15,%rdi - 4413a5: ba 04 00 00 00 mov $0x4,%edx - 4413aa: be 01 00 00 00 mov $0x1,%esi - 4413af: ff d3 callq *%rbx - 4413b1: 49 8b 7f 10 mov 0x10(%r15),%rdi - 4413b5: 48 85 ff test %rdi,%rdi - 4413b8: 74 0d je 4413c7 <__twalk+0x927> - 4413ba: ba 05 00 00 00 mov $0x5,%edx - 4413bf: 48 89 de mov %rbx,%rsi - 4413c2: e8 49 e9 ff ff callq 43fd10 - 4413c7: ba 04 00 00 00 mov $0x4,%edx - 4413cc: be 02 00 00 00 mov $0x2,%esi - 4413d1: 4c 89 ff mov %r15,%rdi - 4413d4: ff d3 callq *%rbx - 4413d6: ba 03 00 00 00 mov $0x3,%edx - 4413db: be 02 00 00 00 mov $0x2,%esi - 4413e0: 4c 89 f7 mov %r14,%rdi - 4413e3: ff d3 callq *%rbx - 4413e5: ba 02 00 00 00 mov $0x2,%edx - 4413ea: be 01 00 00 00 mov $0x1,%esi - 4413ef: 4c 89 ef mov %r13,%rdi - 4413f2: ff d3 callq *%rbx - 4413f4: 4d 8b 75 10 mov 0x10(%r13),%r14 - 4413f8: 4d 85 f6 test %r14,%r14 - 4413fb: 0f 84 09 01 00 00 je 44150a <__twalk+0xa6a> - 441401: 49 83 7e 08 00 cmpq $0x0,0x8(%r14) - 441406: ba 03 00 00 00 mov $0x3,%edx - 44140b: 0f 84 a7 02 00 00 je 4416b8 <__twalk+0xc18> - 441411: 31 f6 xor %esi,%esi - 441413: 4c 89 f7 mov %r14,%rdi - 441416: ff d3 callq *%rbx - 441418: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 44141c: 4d 85 ff test %r15,%r15 - 44141f: 74 61 je 441482 <__twalk+0x9e2> - 441421: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) - 441426: ba 04 00 00 00 mov $0x4,%edx - 44142b: 0f 84 67 03 00 00 je 441798 <__twalk+0xcf8> - 441431: 31 f6 xor %esi,%esi - 441433: 4c 89 ff mov %r15,%rdi - 441436: ff d3 callq *%rbx - 441438: 49 8b 7f 08 mov 0x8(%r15),%rdi - 44143c: 48 85 ff test %rdi,%rdi - 44143f: 74 0d je 44144e <__twalk+0x9ae> - 441441: ba 05 00 00 00 mov $0x5,%edx - 441446: 48 89 de mov %rbx,%rsi - 441449: e8 c2 e8 ff ff callq 43fd10 - 44144e: 4c 89 ff mov %r15,%rdi - 441451: ba 04 00 00 00 mov $0x4,%edx - 441456: be 01 00 00 00 mov $0x1,%esi - 44145b: ff d3 callq *%rbx - 44145d: 49 8b 7f 10 mov 0x10(%r15),%rdi - 441461: 48 85 ff test %rdi,%rdi - 441464: 74 0d je 441473 <__twalk+0x9d3> - 441466: ba 05 00 00 00 mov $0x5,%edx - 44146b: 48 89 de mov %rbx,%rsi - 44146e: e8 9d e8 ff ff callq 43fd10 - 441473: ba 04 00 00 00 mov $0x4,%edx - 441478: be 02 00 00 00 mov $0x2,%esi - 44147d: 4c 89 ff mov %r15,%rdi - 441480: ff d3 callq *%rbx - 441482: ba 03 00 00 00 mov $0x3,%edx - 441487: be 01 00 00 00 mov $0x1,%esi - 44148c: 4c 89 f7 mov %r14,%rdi - 44148f: ff d3 callq *%rbx - 441491: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 441495: 4d 85 ff test %r15,%r15 - 441498: 74 61 je 4414fb <__twalk+0xa5b> - 44149a: 49 83 7f 08 00 cmpq $0x0,0x8(%r15) - 44149f: ba 04 00 00 00 mov $0x4,%edx - 4414a4: 0f 84 ce 02 00 00 je 441778 <__twalk+0xcd8> - 4414aa: 31 f6 xor %esi,%esi - 4414ac: 4c 89 ff mov %r15,%rdi - 4414af: ff d3 callq *%rbx - 4414b1: 49 8b 7f 08 mov 0x8(%r15),%rdi - 4414b5: 48 85 ff test %rdi,%rdi - 4414b8: 74 0d je 4414c7 <__twalk+0xa27> - 4414ba: ba 05 00 00 00 mov $0x5,%edx - 4414bf: 48 89 de mov %rbx,%rsi - 4414c2: e8 49 e8 ff ff callq 43fd10 - 4414c7: 4c 89 ff mov %r15,%rdi - 4414ca: ba 04 00 00 00 mov $0x4,%edx - 4414cf: be 01 00 00 00 mov $0x1,%esi - 4414d4: ff d3 callq *%rbx - 4414d6: 49 8b 7f 10 mov 0x10(%r15),%rdi - 4414da: 48 85 ff test %rdi,%rdi - 4414dd: 74 0d je 4414ec <__twalk+0xa4c> - 4414df: ba 05 00 00 00 mov $0x5,%edx - 4414e4: 48 89 de mov %rbx,%rsi - 4414e7: e8 24 e8 ff ff callq 43fd10 - 4414ec: ba 04 00 00 00 mov $0x4,%edx - 4414f1: be 02 00 00 00 mov $0x2,%esi - 4414f6: 4c 89 ff mov %r15,%rdi - 4414f9: ff d3 callq *%rbx - 4414fb: ba 03 00 00 00 mov $0x3,%edx - 441500: be 02 00 00 00 mov $0x2,%esi - 441505: 4c 89 f7 mov %r14,%rdi - 441508: ff d3 callq *%rbx - 44150a: ba 02 00 00 00 mov $0x2,%edx - 44150f: be 02 00 00 00 mov $0x2,%esi - 441514: 4c 89 ef mov %r13,%rdi - 441517: ff d3 callq *%rbx - 441519: ba 01 00 00 00 mov $0x1,%edx - 44151e: be 02 00 00 00 mov $0x2,%esi - 441523: 4c 89 e7 mov %r12,%rdi - 441526: ff d3 callq *%rbx - 441528: 31 d2 xor %edx,%edx - 44152a: be 02 00 00 00 mov $0x2,%esi - 44152f: 48 89 ef mov %rbp,%rdi - 441532: 48 89 d8 mov %rbx,%rax - 441535: 48 83 c4 08 add $0x8,%rsp - 441539: 5b pop %rbx - 44153a: 5d pop %rbp - 44153b: 41 5c pop %r12 - 44153d: 41 5d pop %r13 - 44153f: 41 5e pop %r14 - 441541: 41 5f pop %r15 - 441543: ff e0 jmpq *%rax - 441545: 0f 1f 00 nopl (%rax) - 441548: 48 83 c4 08 add $0x8,%rsp - 44154c: 5b pop %rbx - 44154d: 5d pop %rbp - 44154e: 41 5c pop %r12 - 441550: 41 5d pop %r13 - 441552: 41 5e pop %r14 - 441554: 41 5f pop %r15 - 441556: c3 retq - 441557: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1) - 44155e: 00 00 - 441560: 49 83 7c 24 10 00 cmpq $0x0,0x10(%r12) - 441566: 0f 85 b9 fa ff ff jne 441025 <__twalk+0x585> - 44156c: be 03 00 00 00 mov $0x3,%esi - 441571: 4c 89 e7 mov %r12,%rdi - 441574: ff d3 callq *%rbx - 441576: eb b0 jmp 441528 <__twalk+0xa88> - 441578: 0f 1f 84 00 00 00 00 nopl 0x0(%rax,%rax,1) - 44157f: 00 - 441580: 49 83 7c 24 10 00 cmpq $0x0,0x10(%r12) - 441586: 0f 85 6c f5 ff ff jne 440af8 <__twalk+0x58> - 44158c: be 03 00 00 00 mov $0x3,%esi - 441591: 4c 89 e7 mov %r12,%rdi - 441594: ff d3 callq *%rbx - 441596: e9 60 fa ff ff jmpq 440ffb <__twalk+0x55b> - 44159b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1) - 4415a0: 31 d2 xor %edx,%edx - 4415a2: 48 83 7f 10 00 cmpq $0x0,0x10(%rdi) - 4415a7: be 03 00 00 00 mov $0x3,%esi - 4415ac: 0f 85 1c f5 ff ff jne 440ace <__twalk+0x2e> - 4415b2: eb 81 jmp 441535 <__twalk+0xa95> - 4415b4: 0f 1f 40 00 nopl 0x0(%rax) - 4415b8: 49 83 7d 10 00 cmpq $0x0,0x10(%r13) - 4415bd: 0f 85 d8 f7 ff ff jne 440d9b <__twalk+0x2fb> - 4415c3: be 03 00 00 00 mov $0x3,%esi - 4415c8: 4c 89 ef mov %r13,%rdi - 4415cb: ff d3 callq *%rbx - 4415cd: e9 1a fa ff ff jmpq 440fec <__twalk+0x54c> - 4415d2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4415d8: 49 83 7d 10 00 cmpq $0x0,0x10(%r13) - 4415dd: 0f 85 67 fa ff ff jne 44104a <__twalk+0x5aa> - 4415e3: be 03 00 00 00 mov $0x3,%esi - 4415e8: 4c 89 ef mov %r13,%rdi - 4415eb: ff d3 callq *%rbx - 4415ed: e9 a9 fc ff ff jmpq 44129b <__twalk+0x7fb> - 4415f2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4415f8: 49 83 7d 10 00 cmpq $0x0,0x10(%r13) - 4415fd: 0f 85 1a f5 ff ff jne 440b1d <__twalk+0x7d> - 441603: be 03 00 00 00 mov $0x3,%esi - 441608: 4c 89 ef mov %r13,%rdi - 44160b: ff d3 callq *%rbx - 44160d: e9 5c f7 ff ff jmpq 440d6e <__twalk+0x2ce> - 441612: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 441618: 49 83 7d 10 00 cmpq $0x0,0x10(%r13) - 44161d: 0f 85 a5 fc ff ff jne 4412c8 <__twalk+0x828> - 441623: be 03 00 00 00 mov $0x3,%esi - 441628: 4c 89 ef mov %r13,%rdi - 44162b: ff d3 callq *%rbx - 44162d: e9 e7 fe ff ff jmpq 441519 <__twalk+0xa79> - 441632: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 441638: 49 83 7e 10 00 cmpq $0x0,0x10(%r14) - 44163d: 0f 85 fe f4 ff ff jne 440b41 <__twalk+0xa1> - 441643: be 03 00 00 00 mov $0x3,%esi - 441648: 4c 89 f7 mov %r14,%rdi - 44164b: ff d3 callq *%rbx - 44164d: e9 e8 f5 ff ff jmpq 440c3a <__twalk+0x19a> - 441652: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 441658: 49 83 7e 10 00 cmpq $0x0,0x10(%r14) - 44165d: 0f 85 81 f8 ff ff jne 440ee4 <__twalk+0x444> - 441663: be 03 00 00 00 mov $0x3,%esi - 441668: 4c 89 f7 mov %r14,%rdi - 44166b: ff d3 callq *%rbx - 44166d: e9 6b f9 ff ff jmpq 440fdd <__twalk+0x53d> - 441672: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 441678: 49 83 7e 10 00 cmpq $0x0,0x10(%r14) - 44167d: 0f 85 3c f7 ff ff jne 440dbf <__twalk+0x31f> - 441683: be 03 00 00 00 mov $0x3,%esi - 441688: 4c 89 f7 mov %r14,%rdi - 44168b: ff d3 callq *%rbx - 44168d: e9 26 f8 ff ff jmpq 440eb8 <__twalk+0x418> - 441692: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 441698: 49 83 7e 10 00 cmpq $0x0,0x10(%r14) - 44169d: 0f 85 c3 f5 ff ff jne 440c66 <__twalk+0x1c6> - 4416a3: be 03 00 00 00 mov $0x3,%esi - 4416a8: 4c 89 f7 mov %r14,%rdi - 4416ab: ff d3 callq *%rbx - 4416ad: e9 ad f6 ff ff jmpq 440d5f <__twalk+0x2bf> - 4416b2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4416b8: 49 83 7e 10 00 cmpq $0x0,0x10(%r14) - 4416bd: 0f 85 4e fd ff ff jne 441411 <__twalk+0x971> - 4416c3: be 03 00 00 00 mov $0x3,%esi - 4416c8: 4c 89 f7 mov %r14,%rdi - 4416cb: ff d3 callq *%rbx - 4416cd: e9 38 fe ff ff jmpq 44150a <__twalk+0xa6a> - 4416d2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4416d8: 49 83 7e 10 00 cmpq $0x0,0x10(%r14) - 4416dd: 0f 85 09 fc ff ff jne 4412ec <__twalk+0x84c> - 4416e3: be 03 00 00 00 mov $0x3,%esi - 4416e8: 4c 89 f7 mov %r14,%rdi - 4416eb: ff d3 callq *%rbx - 4416ed: e9 f3 fc ff ff jmpq 4413e5 <__twalk+0x945> - 4416f2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4416f8: 49 83 7e 10 00 cmpq $0x0,0x10(%r14) - 4416fd: 0f 85 90 fa ff ff jne 441193 <__twalk+0x6f3> - 441703: be 03 00 00 00 mov $0x3,%esi - 441708: 4c 89 f7 mov %r14,%rdi - 44170b: ff d3 callq *%rbx - 44170d: e9 7a fb ff ff jmpq 44128c <__twalk+0x7ec> - 441712: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 441718: 49 83 7e 10 00 cmpq $0x0,0x10(%r14) - 44171d: 0f 85 4b f9 ff ff jne 44106e <__twalk+0x5ce> - 441723: be 03 00 00 00 mov $0x3,%esi - 441728: 4c 89 f7 mov %r14,%rdi - 44172b: ff d3 callq *%rbx - 44172d: e9 35 fa ff ff jmpq 441167 <__twalk+0x6c7> - 441732: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 441738: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) - 44173d: 0f 85 c4 f9 ff ff jne 441107 <__twalk+0x667> - 441743: be 03 00 00 00 mov $0x3,%esi - 441748: 4c 89 ff mov %r15,%rdi - 44174b: ff d3 callq *%rbx - 44174d: e9 06 fa ff ff jmpq 441158 <__twalk+0x6b8> - 441752: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 441758: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) - 44175d: 0f 85 2b f9 ff ff jne 44108e <__twalk+0x5ee> - 441763: be 03 00 00 00 mov $0x3,%esi - 441768: 4c 89 ff mov %r15,%rdi - 44176b: ff d3 callq *%rbx - 44176d: e9 6d f9 ff ff jmpq 4410df <__twalk+0x63f> - 441772: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 441778: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) - 44177d: 0f 85 27 fd ff ff jne 4414aa <__twalk+0xa0a> - 441783: be 03 00 00 00 mov $0x3,%esi - 441788: 4c 89 ff mov %r15,%rdi - 44178b: ff d3 callq *%rbx - 44178d: e9 69 fd ff ff jmpq 4414fb <__twalk+0xa5b> - 441792: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 441798: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) - 44179d: 0f 85 8e fc ff ff jne 441431 <__twalk+0x991> - 4417a3: be 03 00 00 00 mov $0x3,%esi - 4417a8: 4c 89 ff mov %r15,%rdi - 4417ab: ff d3 callq *%rbx - 4417ad: e9 d0 fc ff ff jmpq 441482 <__twalk+0x9e2> - 4417b2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4417b8: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) - 4417bd: 0f 85 c2 fb ff ff jne 441385 <__twalk+0x8e5> - 4417c3: be 03 00 00 00 mov $0x3,%esi - 4417c8: 4c 89 ff mov %r15,%rdi - 4417cb: ff d3 callq *%rbx - 4417cd: e9 04 fc ff ff jmpq 4413d6 <__twalk+0x936> - 4417d2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4417d8: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) - 4417dd: 0f 85 29 fb ff ff jne 44130c <__twalk+0x86c> - 4417e3: be 03 00 00 00 mov $0x3,%esi - 4417e8: 4c 89 ff mov %r15,%rdi - 4417eb: ff d3 callq *%rbx - 4417ed: e9 6b fb ff ff jmpq 44135d <__twalk+0x8bd> - 4417f2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4417f8: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) - 4417fd: 0f 85 29 fa ff ff jne 44122c <__twalk+0x78c> - 441803: be 03 00 00 00 mov $0x3,%esi - 441808: 4c 89 ff mov %r15,%rdi - 44180b: ff d3 callq *%rbx - 44180d: e9 6b fa ff ff jmpq 44127d <__twalk+0x7dd> - 441812: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 441818: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) - 44181d: 0f 85 90 f9 ff ff jne 4411b3 <__twalk+0x713> - 441823: be 03 00 00 00 mov $0x3,%esi - 441828: 4c 89 ff mov %r15,%rdi - 44182b: ff d3 callq *%rbx - 44182d: e9 d2 f9 ff ff jmpq 441204 <__twalk+0x764> - 441832: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 441838: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) - 44183d: 0f 85 3a f7 ff ff jne 440f7d <__twalk+0x4dd> - 441843: be 03 00 00 00 mov $0x3,%esi - 441848: 4c 89 ff mov %r15,%rdi - 44184b: ff d3 callq *%rbx - 44184d: e9 7c f7 ff ff jmpq 440fce <__twalk+0x52e> - 441852: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 441858: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) - 44185d: 0f 85 a1 f6 ff ff jne 440f04 <__twalk+0x464> - 441863: be 03 00 00 00 mov $0x3,%esi - 441868: 4c 89 ff mov %r15,%rdi - 44186b: ff d3 callq *%rbx - 44186d: e9 e3 f6 ff ff jmpq 440f55 <__twalk+0x4b5> - 441872: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 441878: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) - 44187d: 0f 85 de f2 ff ff jne 440b61 <__twalk+0xc1> - 441883: be 03 00 00 00 mov $0x3,%esi - 441888: 4c 89 ff mov %r15,%rdi - 44188b: ff d3 callq *%rbx - 44188d: e9 20 f3 ff ff jmpq 440bb2 <__twalk+0x112> - 441892: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 441898: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) - 44189d: 0f 85 b5 f5 ff ff jne 440e58 <__twalk+0x3b8> - 4418a3: be 03 00 00 00 mov $0x3,%esi - 4418a8: 4c 89 ff mov %r15,%rdi - 4418ab: ff d3 callq *%rbx - 4418ad: e9 f7 f5 ff ff jmpq 440ea9 <__twalk+0x409> - 4418b2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4418b8: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) - 4418bd: 0f 85 1c f5 ff ff jne 440ddf <__twalk+0x33f> - 4418c3: be 03 00 00 00 mov $0x3,%esi - 4418c8: 4c 89 ff mov %r15,%rdi - 4418cb: ff d3 callq *%rbx - 4418cd: e9 5e f5 ff ff jmpq 440e30 <__twalk+0x390> - 4418d2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4418d8: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) - 4418dd: 0f 85 f7 f2 ff ff jne 440bda <__twalk+0x13a> - 4418e3: be 03 00 00 00 mov $0x3,%esi - 4418e8: 4c 89 ff mov %r15,%rdi - 4418eb: ff d3 callq *%rbx - 4418ed: e9 39 f3 ff ff jmpq 440c2b <__twalk+0x18b> - 4418f2: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 4418f8: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) - 4418fd: 0f 85 fc f3 ff ff jne 440cff <__twalk+0x25f> - 441903: be 03 00 00 00 mov $0x3,%esi - 441908: 4c 89 ff mov %r15,%rdi - 44190b: ff d3 callq *%rbx - 44190d: e9 3e f4 ff ff jmpq 440d50 <__twalk+0x2b0> - 441912: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 441918: 49 83 7f 10 00 cmpq $0x0,0x10(%r15) - 44191d: 0f 85 63 f3 ff ff jne 440c86 <__twalk+0x1e6> - 441923: be 03 00 00 00 mov $0x3,%esi - 441928: 4c 89 ff mov %r15,%rdi - 44192b: ff d3 callq *%rbx - 44192d: e9 a5 f3 ff ff jmpq 440cd7 <__twalk+0x237> - 441932: 0f 1f 40 00 nopl 0x0(%rax) - 441936: 66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1) - 44193d: 00 00 00 - -0000000000441940 <__tdestroy>: - 441940: 48 85 ff test %rdi,%rdi - 441943: 0f 84 df 04 00 00 je 441e28 <__tdestroy+0x4e8> - 441949: 41 57 push %r15 - 44194b: 41 56 push %r14 - 44194d: 41 55 push %r13 - 44194f: 41 54 push %r12 - 441951: 55 push %rbp - 441952: 53 push %rbx - 441953: 48 89 fd mov %rdi,%rbp - 441956: 48 89 f3 mov %rsi,%rbx - 441959: 48 83 ec 08 sub $0x8,%rsp - 44195d: 4c 8b 67 08 mov 0x8(%rdi),%r12 - 441961: 4d 85 e4 test %r12,%r12 - 441964: 0f 84 5b 02 00 00 je 441bc5 <__tdestroy+0x285> - 44196a: 4d 8b 6c 24 08 mov 0x8(%r12),%r13 - 44196f: 4d 85 ed test %r13,%r13 - 441972: 0f 84 17 01 00 00 je 441a8f <__tdestroy+0x14f> - 441978: 4d 8b 75 08 mov 0x8(%r13),%r14 - 44197c: 4d 85 f6 test %r14,%r14 - 44197f: 74 7a je 4419fb <__tdestroy+0xbb> - 441981: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 441985: 4d 85 ff test %r15,%r15 - 441988: 74 2c je 4419b6 <__tdestroy+0x76> - 44198a: 49 8b 7f 08 mov 0x8(%r15),%rdi - 44198e: 48 85 ff test %rdi,%rdi - 441991: 74 05 je 441998 <__tdestroy+0x58> - 441993: e8 08 e4 ff ff callq 43fda0 - 441998: 49 8b 7f 10 mov 0x10(%r15),%rdi - 44199c: 48 85 ff test %rdi,%rdi - 44199f: 74 08 je 4419a9 <__tdestroy+0x69> - 4419a1: 48 89 de mov %rbx,%rsi - 4419a4: e8 f7 e3 ff ff callq 43fda0 - 4419a9: 49 8b 3f mov (%r15),%rdi - 4419ac: ff d3 callq *%rbx - 4419ae: 4c 89 ff mov %r15,%rdi - 4419b1: e8 fa c3 fd ff callq 41ddb0 <__cfree> - 4419b6: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 4419ba: 4d 85 ff test %r15,%r15 - 4419bd: 74 2f je 4419ee <__tdestroy+0xae> - 4419bf: 49 8b 7f 08 mov 0x8(%r15),%rdi - 4419c3: 48 85 ff test %rdi,%rdi - 4419c6: 74 08 je 4419d0 <__tdestroy+0x90> - 4419c8: 48 89 de mov %rbx,%rsi - 4419cb: e8 d0 e3 ff ff callq 43fda0 - 4419d0: 49 8b 7f 10 mov 0x10(%r15),%rdi - 4419d4: 48 85 ff test %rdi,%rdi - 4419d7: 74 08 je 4419e1 <__tdestroy+0xa1> - 4419d9: 48 89 de mov %rbx,%rsi - 4419dc: e8 bf e3 ff ff callq 43fda0 - 4419e1: 49 8b 3f mov (%r15),%rdi - 4419e4: ff d3 callq *%rbx - 4419e6: 4c 89 ff mov %r15,%rdi - 4419e9: e8 c2 c3 fd ff callq 41ddb0 <__cfree> - 4419ee: 49 8b 3e mov (%r14),%rdi - 4419f1: ff d3 callq *%rbx - 4419f3: 4c 89 f7 mov %r14,%rdi - 4419f6: e8 b5 c3 fd ff callq 41ddb0 <__cfree> - 4419fb: 4d 8b 75 10 mov 0x10(%r13),%r14 - 4419ff: 4d 85 f6 test %r14,%r14 - 441a02: 74 7d je 441a81 <__tdestroy+0x141> - 441a04: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 441a08: 4d 85 ff test %r15,%r15 - 441a0b: 74 2f je 441a3c <__tdestroy+0xfc> - 441a0d: 49 8b 7f 08 mov 0x8(%r15),%rdi - 441a11: 48 85 ff test %rdi,%rdi - 441a14: 74 08 je 441a1e <__tdestroy+0xde> - 441a16: 48 89 de mov %rbx,%rsi - 441a19: e8 82 e3 ff ff callq 43fda0 - 441a1e: 49 8b 7f 10 mov 0x10(%r15),%rdi - 441a22: 48 85 ff test %rdi,%rdi - 441a25: 74 08 je 441a2f <__tdestroy+0xef> - 441a27: 48 89 de mov %rbx,%rsi - 441a2a: e8 71 e3 ff ff callq 43fda0 - 441a2f: 49 8b 3f mov (%r15),%rdi - 441a32: ff d3 callq *%rbx - 441a34: 4c 89 ff mov %r15,%rdi - 441a37: e8 74 c3 fd ff callq 41ddb0 <__cfree> - 441a3c: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 441a40: 4d 85 ff test %r15,%r15 - 441a43: 74 2f je 441a74 <__tdestroy+0x134> - 441a45: 49 8b 7f 08 mov 0x8(%r15),%rdi - 441a49: 48 85 ff test %rdi,%rdi - 441a4c: 74 08 je 441a56 <__tdestroy+0x116> - 441a4e: 48 89 de mov %rbx,%rsi - 441a51: e8 4a e3 ff ff callq 43fda0 - 441a56: 49 8b 7f 10 mov 0x10(%r15),%rdi - 441a5a: 48 85 ff test %rdi,%rdi - 441a5d: 74 08 je 441a67 <__tdestroy+0x127> - 441a5f: 48 89 de mov %rbx,%rsi - 441a62: e8 39 e3 ff ff callq 43fda0 - 441a67: 49 8b 3f mov (%r15),%rdi - 441a6a: ff d3 callq *%rbx - 441a6c: 4c 89 ff mov %r15,%rdi - 441a6f: e8 3c c3 fd ff callq 41ddb0 <__cfree> - 441a74: 49 8b 3e mov (%r14),%rdi - 441a77: ff d3 callq *%rbx - 441a79: 4c 89 f7 mov %r14,%rdi - 441a7c: e8 2f c3 fd ff callq 41ddb0 <__cfree> - 441a81: 49 8b 7d 00 mov 0x0(%r13),%rdi - 441a85: ff d3 callq *%rbx - 441a87: 4c 89 ef mov %r13,%rdi - 441a8a: e8 21 c3 fd ff callq 41ddb0 <__cfree> - 441a8f: 4d 8b 6c 24 10 mov 0x10(%r12),%r13 - 441a94: 4d 85 ed test %r13,%r13 - 441a97: 0f 84 1a 01 00 00 je 441bb7 <__tdestroy+0x277> - 441a9d: 4d 8b 75 08 mov 0x8(%r13),%r14 - 441aa1: 4d 85 f6 test %r14,%r14 - 441aa4: 74 7d je 441b23 <__tdestroy+0x1e3> - 441aa6: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 441aaa: 4d 85 ff test %r15,%r15 - 441aad: 74 2f je 441ade <__tdestroy+0x19e> - 441aaf: 49 8b 7f 08 mov 0x8(%r15),%rdi - 441ab3: 48 85 ff test %rdi,%rdi - 441ab6: 74 08 je 441ac0 <__tdestroy+0x180> - 441ab8: 48 89 de mov %rbx,%rsi - 441abb: e8 e0 e2 ff ff callq 43fda0 - 441ac0: 49 8b 7f 10 mov 0x10(%r15),%rdi - 441ac4: 48 85 ff test %rdi,%rdi - 441ac7: 74 08 je 441ad1 <__tdestroy+0x191> - 441ac9: 48 89 de mov %rbx,%rsi - 441acc: e8 cf e2 ff ff callq 43fda0 - 441ad1: 49 8b 3f mov (%r15),%rdi - 441ad4: ff d3 callq *%rbx - 441ad6: 4c 89 ff mov %r15,%rdi - 441ad9: e8 d2 c2 fd ff callq 41ddb0 <__cfree> - 441ade: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 441ae2: 4d 85 ff test %r15,%r15 - 441ae5: 74 2f je 441b16 <__tdestroy+0x1d6> - 441ae7: 49 8b 7f 08 mov 0x8(%r15),%rdi - 441aeb: 48 85 ff test %rdi,%rdi - 441aee: 74 08 je 441af8 <__tdestroy+0x1b8> - 441af0: 48 89 de mov %rbx,%rsi - 441af3: e8 a8 e2 ff ff callq 43fda0 - 441af8: 49 8b 7f 10 mov 0x10(%r15),%rdi - 441afc: 48 85 ff test %rdi,%rdi - 441aff: 74 08 je 441b09 <__tdestroy+0x1c9> - 441b01: 48 89 de mov %rbx,%rsi - 441b04: e8 97 e2 ff ff callq 43fda0 - 441b09: 49 8b 3f mov (%r15),%rdi - 441b0c: ff d3 callq *%rbx - 441b0e: 4c 89 ff mov %r15,%rdi - 441b11: e8 9a c2 fd ff callq 41ddb0 <__cfree> - 441b16: 49 8b 3e mov (%r14),%rdi - 441b19: ff d3 callq *%rbx - 441b1b: 4c 89 f7 mov %r14,%rdi - 441b1e: e8 8d c2 fd ff callq 41ddb0 <__cfree> - 441b23: 4d 8b 75 10 mov 0x10(%r13),%r14 - 441b27: 4d 85 f6 test %r14,%r14 - 441b2a: 74 7d je 441ba9 <__tdestroy+0x269> - 441b2c: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 441b30: 4d 85 ff test %r15,%r15 - 441b33: 74 2f je 441b64 <__tdestroy+0x224> - 441b35: 49 8b 7f 08 mov 0x8(%r15),%rdi - 441b39: 48 85 ff test %rdi,%rdi - 441b3c: 74 08 je 441b46 <__tdestroy+0x206> - 441b3e: 48 89 de mov %rbx,%rsi - 441b41: e8 5a e2 ff ff callq 43fda0 - 441b46: 49 8b 7f 10 mov 0x10(%r15),%rdi - 441b4a: 48 85 ff test %rdi,%rdi - 441b4d: 74 08 je 441b57 <__tdestroy+0x217> - 441b4f: 48 89 de mov %rbx,%rsi - 441b52: e8 49 e2 ff ff callq 43fda0 - 441b57: 49 8b 3f mov (%r15),%rdi - 441b5a: ff d3 callq *%rbx - 441b5c: 4c 89 ff mov %r15,%rdi - 441b5f: e8 4c c2 fd ff callq 41ddb0 <__cfree> - 441b64: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 441b68: 4d 85 ff test %r15,%r15 - 441b6b: 74 2f je 441b9c <__tdestroy+0x25c> - 441b6d: 49 8b 7f 08 mov 0x8(%r15),%rdi - 441b71: 48 85 ff test %rdi,%rdi - 441b74: 74 08 je 441b7e <__tdestroy+0x23e> - 441b76: 48 89 de mov %rbx,%rsi - 441b79: e8 22 e2 ff ff callq 43fda0 - 441b7e: 49 8b 7f 10 mov 0x10(%r15),%rdi - 441b82: 48 85 ff test %rdi,%rdi - 441b85: 74 08 je 441b8f <__tdestroy+0x24f> - 441b87: 48 89 de mov %rbx,%rsi - 441b8a: e8 11 e2 ff ff callq 43fda0 - 441b8f: 49 8b 3f mov (%r15),%rdi - 441b92: ff d3 callq *%rbx - 441b94: 4c 89 ff mov %r15,%rdi - 441b97: e8 14 c2 fd ff callq 41ddb0 <__cfree> - 441b9c: 49 8b 3e mov (%r14),%rdi - 441b9f: ff d3 callq *%rbx - 441ba1: 4c 89 f7 mov %r14,%rdi - 441ba4: e8 07 c2 fd ff callq 41ddb0 <__cfree> - 441ba9: 49 8b 7d 00 mov 0x0(%r13),%rdi - 441bad: ff d3 callq *%rbx - 441baf: 4c 89 ef mov %r13,%rdi - 441bb2: e8 f9 c1 fd ff callq 41ddb0 <__cfree> - 441bb7: 49 8b 3c 24 mov (%r12),%rdi - 441bbb: ff d3 callq *%rbx - 441bbd: 4c 89 e7 mov %r12,%rdi - 441bc0: e8 eb c1 fd ff callq 41ddb0 <__cfree> - 441bc5: 4c 8b 65 10 mov 0x10(%rbp),%r12 - 441bc9: 4d 85 e4 test %r12,%r12 - 441bcc: 0f 84 37 02 00 00 je 441e09 <__tdestroy+0x4c9> - 441bd2: 4d 8b 6c 24 08 mov 0x8(%r12),%r13 - 441bd7: 4d 85 ed test %r13,%r13 - 441bda: 0f 84 1a 01 00 00 je 441cfa <__tdestroy+0x3ba> - 441be0: 4d 8b 75 08 mov 0x8(%r13),%r14 - 441be4: 4d 85 f6 test %r14,%r14 - 441be7: 74 7d je 441c66 <__tdestroy+0x326> - 441be9: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 441bed: 4d 85 ff test %r15,%r15 - 441bf0: 74 2f je 441c21 <__tdestroy+0x2e1> - 441bf2: 49 8b 7f 08 mov 0x8(%r15),%rdi - 441bf6: 48 85 ff test %rdi,%rdi - 441bf9: 74 08 je 441c03 <__tdestroy+0x2c3> - 441bfb: 48 89 de mov %rbx,%rsi - 441bfe: e8 9d e1 ff ff callq 43fda0 - 441c03: 49 8b 7f 10 mov 0x10(%r15),%rdi - 441c07: 48 85 ff test %rdi,%rdi - 441c0a: 74 08 je 441c14 <__tdestroy+0x2d4> - 441c0c: 48 89 de mov %rbx,%rsi - 441c0f: e8 8c e1 ff ff callq 43fda0 - 441c14: 49 8b 3f mov (%r15),%rdi - 441c17: ff d3 callq *%rbx - 441c19: 4c 89 ff mov %r15,%rdi - 441c1c: e8 8f c1 fd ff callq 41ddb0 <__cfree> - 441c21: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 441c25: 4d 85 ff test %r15,%r15 - 441c28: 74 2f je 441c59 <__tdestroy+0x319> - 441c2a: 49 8b 7f 08 mov 0x8(%r15),%rdi - 441c2e: 48 85 ff test %rdi,%rdi - 441c31: 74 08 je 441c3b <__tdestroy+0x2fb> - 441c33: 48 89 de mov %rbx,%rsi - 441c36: e8 65 e1 ff ff callq 43fda0 - 441c3b: 49 8b 7f 10 mov 0x10(%r15),%rdi - 441c3f: 48 85 ff test %rdi,%rdi - 441c42: 74 08 je 441c4c <__tdestroy+0x30c> - 441c44: 48 89 de mov %rbx,%rsi - 441c47: e8 54 e1 ff ff callq 43fda0 - 441c4c: 49 8b 3f mov (%r15),%rdi - 441c4f: ff d3 callq *%rbx - 441c51: 4c 89 ff mov %r15,%rdi - 441c54: e8 57 c1 fd ff callq 41ddb0 <__cfree> - 441c59: 49 8b 3e mov (%r14),%rdi - 441c5c: ff d3 callq *%rbx - 441c5e: 4c 89 f7 mov %r14,%rdi - 441c61: e8 4a c1 fd ff callq 41ddb0 <__cfree> - 441c66: 4d 8b 75 10 mov 0x10(%r13),%r14 - 441c6a: 4d 85 f6 test %r14,%r14 - 441c6d: 74 7d je 441cec <__tdestroy+0x3ac> - 441c6f: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 441c73: 4d 85 ff test %r15,%r15 - 441c76: 74 2f je 441ca7 <__tdestroy+0x367> - 441c78: 49 8b 7f 08 mov 0x8(%r15),%rdi - 441c7c: 48 85 ff test %rdi,%rdi - 441c7f: 74 08 je 441c89 <__tdestroy+0x349> - 441c81: 48 89 de mov %rbx,%rsi - 441c84: e8 17 e1 ff ff callq 43fda0 - 441c89: 49 8b 7f 10 mov 0x10(%r15),%rdi - 441c8d: 48 85 ff test %rdi,%rdi - 441c90: 74 08 je 441c9a <__tdestroy+0x35a> - 441c92: 48 89 de mov %rbx,%rsi - 441c95: e8 06 e1 ff ff callq 43fda0 - 441c9a: 49 8b 3f mov (%r15),%rdi - 441c9d: ff d3 callq *%rbx - 441c9f: 4c 89 ff mov %r15,%rdi - 441ca2: e8 09 c1 fd ff callq 41ddb0 <__cfree> - 441ca7: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 441cab: 4d 85 ff test %r15,%r15 - 441cae: 74 2f je 441cdf <__tdestroy+0x39f> - 441cb0: 49 8b 7f 08 mov 0x8(%r15),%rdi - 441cb4: 48 85 ff test %rdi,%rdi - 441cb7: 74 08 je 441cc1 <__tdestroy+0x381> - 441cb9: 48 89 de mov %rbx,%rsi - 441cbc: e8 df e0 ff ff callq 43fda0 - 441cc1: 49 8b 7f 10 mov 0x10(%r15),%rdi - 441cc5: 48 85 ff test %rdi,%rdi - 441cc8: 74 08 je 441cd2 <__tdestroy+0x392> - 441cca: 48 89 de mov %rbx,%rsi - 441ccd: e8 ce e0 ff ff callq 43fda0 - 441cd2: 49 8b 3f mov (%r15),%rdi - 441cd5: ff d3 callq *%rbx - 441cd7: 4c 89 ff mov %r15,%rdi - 441cda: e8 d1 c0 fd ff callq 41ddb0 <__cfree> - 441cdf: 49 8b 3e mov (%r14),%rdi - 441ce2: ff d3 callq *%rbx - 441ce4: 4c 89 f7 mov %r14,%rdi - 441ce7: e8 c4 c0 fd ff callq 41ddb0 <__cfree> - 441cec: 49 8b 7d 00 mov 0x0(%r13),%rdi - 441cf0: ff d3 callq *%rbx - 441cf2: 4c 89 ef mov %r13,%rdi - 441cf5: e8 b6 c0 fd ff callq 41ddb0 <__cfree> - 441cfa: 4d 8b 6c 24 10 mov 0x10(%r12),%r13 - 441cff: 4d 85 ed test %r13,%r13 - 441d02: 0f 84 f3 00 00 00 je 441dfb <__tdestroy+0x4bb> - 441d08: 4d 8b 75 08 mov 0x8(%r13),%r14 - 441d0c: 4d 85 f6 test %r14,%r14 - 441d0f: 74 7d je 441d8e <__tdestroy+0x44e> - 441d11: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 441d15: 4d 85 ff test %r15,%r15 - 441d18: 74 2f je 441d49 <__tdestroy+0x409> - 441d1a: 49 8b 7f 08 mov 0x8(%r15),%rdi - 441d1e: 48 85 ff test %rdi,%rdi - 441d21: 74 08 je 441d2b <__tdestroy+0x3eb> - 441d23: 48 89 de mov %rbx,%rsi - 441d26: e8 75 e0 ff ff callq 43fda0 - 441d2b: 49 8b 7f 10 mov 0x10(%r15),%rdi - 441d2f: 48 85 ff test %rdi,%rdi - 441d32: 74 08 je 441d3c <__tdestroy+0x3fc> - 441d34: 48 89 de mov %rbx,%rsi - 441d37: e8 64 e0 ff ff callq 43fda0 - 441d3c: 49 8b 3f mov (%r15),%rdi - 441d3f: ff d3 callq *%rbx - 441d41: 4c 89 ff mov %r15,%rdi - 441d44: e8 67 c0 fd ff callq 41ddb0 <__cfree> - 441d49: 4d 8b 7e 10 mov 0x10(%r14),%r15 - 441d4d: 4d 85 ff test %r15,%r15 - 441d50: 74 2f je 441d81 <__tdestroy+0x441> - 441d52: 49 8b 7f 08 mov 0x8(%r15),%rdi - 441d56: 48 85 ff test %rdi,%rdi - 441d59: 74 08 je 441d63 <__tdestroy+0x423> - 441d5b: 48 89 de mov %rbx,%rsi - 441d5e: e8 3d e0 ff ff callq 43fda0 - 441d63: 49 8b 7f 10 mov 0x10(%r15),%rdi - 441d67: 48 85 ff test %rdi,%rdi - 441d6a: 74 08 je 441d74 <__tdestroy+0x434> - 441d6c: 48 89 de mov %rbx,%rsi - 441d6f: e8 2c e0 ff ff callq 43fda0 - 441d74: 49 8b 3f mov (%r15),%rdi - 441d77: ff d3 callq *%rbx - 441d79: 4c 89 ff mov %r15,%rdi - 441d7c: e8 2f c0 fd ff callq 41ddb0 <__cfree> - 441d81: 49 8b 3e mov (%r14),%rdi - 441d84: ff d3 callq *%rbx - 441d86: 4c 89 f7 mov %r14,%rdi - 441d89: e8 22 c0 fd ff callq 41ddb0 <__cfree> - 441d8e: 4d 8b 75 10 mov 0x10(%r13),%r14 - 441d92: 4d 85 f6 test %r14,%r14 - 441d95: 74 56 je 441ded <__tdestroy+0x4ad> - 441d97: 4d 8b 7e 08 mov 0x8(%r14),%r15 - 441d9b: 4d 85 ff test %r15,%r15 - 441d9e: 74 2f je 441dcf <__tdestroy+0x48f> - 441da0: 49 8b 7f 08 mov 0x8(%r15),%rdi - 441da4: 48 85 ff test %rdi,%rdi - 441da7: 74 08 je 441db1 <__tdestroy+0x471> - 441da9: 48 89 de mov %rbx,%rsi - 441dac: e8 ef df ff ff callq 43fda0 - 441db1: 49 8b 7f 10 mov 0x10(%r15),%rdi - 441db5: 48 85 ff test %rdi,%rdi - 441db8: 74 08 je 441dc2 <__tdestroy+0x482> - 441dba: 48 89 de mov %rbx,%rsi - 441dbd: e8 de df ff ff callq 43fda0 - 441dc2: 49 8b 3f mov (%r15),%rdi - 441dc5: ff d3 callq *%rbx - 441dc7: 4c 89 ff mov %r15,%rdi - 441dca: e8 e1 bf fd ff callq 41ddb0 <__cfree> - 441dcf: 49 8b 7e 10 mov 0x10(%r14),%rdi - 441dd3: 48 85 ff test %rdi,%rdi - 441dd6: 74 08 je 441de0 <__tdestroy+0x4a0> - 441dd8: 48 89 de mov %rbx,%rsi - 441ddb: e8 c0 df ff ff callq 43fda0 - 441de0: 49 8b 3e mov (%r14),%rdi - 441de3: ff d3 callq *%rbx - 441de5: 4c 89 f7 mov %r14,%rdi - 441de8: e8 c3 bf fd ff callq 41ddb0 <__cfree> - 441ded: 49 8b 7d 00 mov 0x0(%r13),%rdi - 441df1: ff d3 callq *%rbx - 441df3: 4c 89 ef mov %r13,%rdi - 441df6: e8 b5 bf fd ff callq 41ddb0 <__cfree> - 441dfb: 49 8b 3c 24 mov (%r12),%rdi - 441dff: ff d3 callq *%rbx - 441e01: 4c 89 e7 mov %r12,%rdi - 441e04: e8 a7 bf fd ff callq 41ddb0 <__cfree> - 441e09: 48 8b 7d 00 mov 0x0(%rbp),%rdi - 441e0d: ff d3 callq *%rbx - 441e0f: 48 83 c4 08 add $0x8,%rsp - 441e13: 48 89 ef mov %rbp,%rdi - 441e16: 5b pop %rbx - 441e17: 5d pop %rbp - 441e18: 41 5c pop %r12 - 441e1a: 41 5d pop %r13 - 441e1c: 41 5e pop %r14 - 441e1e: 41 5f pop %r15 - 441e20: e9 8b bf fd ff jmpq 41ddb0 <__cfree> - 441e25: 0f 1f 00 nopl (%rax) - 441e28: f3 c3 repz retq - 441e2a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - -0000000000441e30 : - 441e30: 41 57 push %r15 - 441e32: 41 56 push %r14 - 441e34: 49 89 d7 mov %rdx,%r15 - 441e37: 41 55 push %r13 - 441e39: 41 54 push %r12 - 441e3b: 4d 89 c6 mov %r8,%r14 - 441e3e: 55 push %rbp - 441e3f: 53 push %rbx - 441e40: 48 89 cb mov %rcx,%rbx - 441e43: 48 83 ec 18 sub $0x18,%rsp - 441e47: 48 8b 29 mov (%rcx),%rbp - 441e4a: 4c 8b 22 mov (%rdx),%r12 - 441e4d: 89 7c 24 08 mov %edi,0x8(%rsp) - 441e51: 48 89 34 24 mov %rsi,(%rsp) - 441e55: be 0a 00 00 00 mov $0xa,%esi - 441e5a: 49 89 ed mov %rbp,%r13 - 441e5d: 4c 89 e7 mov %r12,%rdi - 441e60: 4d 29 e5 sub %r12,%r13 - 441e63: 4c 89 ea mov %r13,%rdx - 441e66: e8 d5 3c fe ff callq 425b40 <__memchr> - 441e6b: 48 85 c0 test %rax,%rax - 441e6e: 74 30 je 441ea0 - 441e70: 48 83 c0 01 add $0x1,%rax - 441e74: 49 89 07 mov %rax,(%r15) - 441e77: 48 8b 13 mov (%rbx),%rdx - 441e7a: 48 39 d0 cmp %rdx,%rax - 441e7d: 0f 87 95 01 00 00 ja 442018 - 441e83: 49 39 d4 cmp %rdx,%r12 - 441e86: 74 30 je 441eb8 - 441e88: 4c 89 e0 mov %r12,%rax - 441e8b: 48 83 c4 18 add $0x18,%rsp - 441e8f: 5b pop %rbx - 441e90: 5d pop %rbp - 441e91: 41 5c pop %r12 - 441e93: 41 5d pop %r13 - 441e95: 41 5e pop %r14 - 441e97: 41 5f pop %r15 - 441e99: c3 retq - 441e9a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1) - 441ea0: 4c 3b 24 24 cmp (%rsp),%r12 - 441ea4: 74 05 je 441eab - 441ea6: 4c 39 f5 cmp %r14,%rbp - 441ea9: 74 11 je 441ebc - 441eab: 48 8d 45 ff lea -0x1(%rbp),%rax - 441eaf: eb bf jmp 441e70 - 441eb1: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 441eb8: 31 c0 xor %eax,%eax - 441eba: eb cf jmp 441e8b - 441ebc: 4c 8b 34 24 mov (%rsp),%r14 - 441ec0: 4c 89 ea mov %r13,%rdx - 441ec3: 4c 89 e6 mov %r12,%rsi - 441ec6: 45 31 e4 xor %r12d,%r12d - 441ec9: 4c 89 f7 mov %r14,%rdi - 441ecc: e8 2f e4 fb ff callq 400300 <__rela_iplt_end+0x38> - 441ed1: 4c 89 f0 mov %r14,%rax - 441ed4: 49 2b 07 sub (%r15),%rax - 441ed7: 48 89 ea mov %rbp,%rdx - 441eda: 48 01 03 add %rax,(%rbx) - 441edd: 48 63 44 24 08 movslq 0x8(%rsp),%rax - 441ee2: 4d 89 37 mov %r14,(%r15) - 441ee5: 48 8b 33 mov (%rbx),%rsi - 441ee8: 48 89 44 24 08 mov %rax,0x8(%rsp) - 441eed: 48 89 c7 mov %rax,%rdi - 441ef0: 48 29 f2 sub %rsi,%rdx - 441ef3: 44 89 e0 mov %r12d,%eax - 441ef6: 0f 05 syscall - 441ef8: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 441efe: 76 13 jbe 441f13 - 441f00: 48 c7 c2 d0 ff ff ff mov $0xffffffffffffffd0,%rdx - 441f07: f7 d8 neg %eax - 441f09: 64 89 02 mov %eax,%fs:(%rdx) - 441f0c: 31 c0 xor %eax,%eax - 441f0e: e9 78 ff ff ff jmpq 441e8b - 441f13: 48 85 c0 test %rax,%rax - 441f16: 78 a0 js 441eb8 - 441f18: 48 03 03 add (%rbx),%rax - 441f1b: be 0a 00 00 00 mov $0xa,%esi - 441f20: 48 89 03 mov %rax,(%rbx) - 441f23: 4d 8b 37 mov (%r15),%r14 - 441f26: 48 89 c2 mov %rax,%rdx - 441f29: 49 89 c5 mov %rax,%r13 - 441f2c: 4c 29 f2 sub %r14,%rdx - 441f2f: 4c 89 f7 mov %r14,%rdi - 441f32: e8 09 3c fe ff callq 425b40 <__memchr> - 441f37: 48 85 c0 test %rax,%rax - 441f3a: 0f 85 c5 00 00 00 jne 442005 - 441f40: 4c 39 ed cmp %r13,%rbp - 441f43: 0f 85 e8 00 00 00 jne 442031 - 441f49: 48 8b 0c 24 mov (%rsp),%rcx - 441f4d: 48 89 e8 mov %rbp,%rax - 441f50: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi - 441f55: 48 29 c8 sub %rcx,%rax - 441f58: 4c 8d 34 40 lea (%rax,%rax,2),%r14 - 441f5c: 49 8d 46 03 lea 0x3(%r14),%rax - 441f60: 4d 85 f6 test %r14,%r14 - 441f63: 4c 0f 48 f0 cmovs %rax,%r14 - 441f67: 48 89 e8 mov %rbp,%rax - 441f6a: 49 c1 fe 02 sar $0x2,%r14 - 441f6e: 49 01 ce add %rcx,%r14 - 441f71: 4c 29 f0 sub %r14,%rax - 441f74: 4c 89 33 mov %r14,(%rbx) - 441f77: 4c 89 f6 mov %r14,%rsi - 441f7a: 48 89 04 24 mov %rax,(%rsp) - 441f7e: 48 89 c2 mov %rax,%rdx - 441f81: 44 89 e0 mov %r12d,%eax - 441f84: 0f 05 syscall - 441f86: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 441f8c: 49 89 c5 mov %rax,%r13 - 441f8f: 76 42 jbe 441fd3 - 441f91: 0f 1f 80 00 00 00 00 nopl 0x0(%rax) - 441f98: 48 c7 c0 d0 ff ff ff mov $0xffffffffffffffd0,%rax - 441f9f: 44 89 e9 mov %r13d,%ecx - 441fa2: f7 d9 neg %ecx - 441fa4: 64 89 08 mov %ecx,%fs:(%rax) - 441fa7: 31 c0 xor %eax,%eax - 441fa9: e9 dd fe ff ff jmpq 441e8b - 441fae: 66 90 xchg %ax,%ax - 441fb0: 48 39 cd cmp %rcx,%rbp - 441fb3: 75 58 jne 44200d - 441fb5: 4c 89 33 mov %r14,(%rbx) - 441fb8: 48 8b 14 24 mov (%rsp),%rdx - 441fbc: 4c 89 f6 mov %r14,%rsi - 441fbf: 48 8b 7c 24 08 mov 0x8(%rsp),%rdi - 441fc4: 31 c0 xor %eax,%eax - 441fc6: 0f 05 syscall - 441fc8: 48 3d 00 f0 ff ff cmp $0xfffffffffffff000,%rax - 441fce: 49 89 c5 mov %rax,%r13 - 441fd1: 77 c5 ja 441f98 - 441fd3: 4d 85 ed test %r13,%r13 - 441fd6: 0f 88 dc fe ff ff js 441eb8 - 441fdc: 4c 8b 23 mov (%rbx),%r12 - 441fdf: 4c 89 ea mov %r13,%rdx - 441fe2: be 0a 00 00 00 mov $0xa,%esi - 441fe7: 4c 89 e7 mov %r12,%rdi - 441fea: e8 51 3b fe ff callq 425b40 <__memchr> - 441fef: 41 c6 04 24 0a movb $0xa,(%r12) - 441ff4: 4c 89 e9 mov %r13,%rcx - 441ff7: 48 03 0b add (%rbx),%rcx - 441ffa: 48 85 c0 test %rax,%rax - 441ffd: 48 89 0b mov %rcx,(%rbx) - 442000: 74 ae je 441fb0 - 442002: 4d 8b 37 mov (%r15),%r14 - 442005: 4d 89 f4 mov %r14,%r12 - 442008: e9 63 fe ff ff jmpq 441e70 - 44200d: 48 89 cd mov %rcx,%rbp - 442010: 4d 8b 27 mov (%r15),%r12 - 442013: e9 93 fe ff ff jmpq 441eab - 442018: b9 08 4a 4a 00 mov $0x4a4a08,%ecx - 44201d: ba 77 00 00 00 mov $0x77,%edx - 442022: be b8 49 4a 00 mov $0x4a49b8,%esi - 442027: bf 12 4a 4a 00 mov $0x4a4a12,%edi - 44202c: e8 0f f7 fb ff callq 401740 <__assert_fail> - 442031: 4c 89 ed mov %r13,%rbp - 442034: 4d 89 f4 mov %r14,%r12 - 442037: e9 6f fe ff ff jmpq 441eab - 44203c: 0f 1f 40 00 nopl 0x0(%rax) - -0000000000442040 <__get_nprocs>: - 442040: 55 push %rbp - 442041: 31 ff xor %edi,%edi - 442043: 48 89 e5 mov %rsp,%rbp - 442046: 41 57 push %r15 - 442048: 41 56 push %r14 - 44204a: 41 55 push %r13 - 44204c: 41 54 push %r12 - 44204e: 53 push %rbx - 44204f: 48 83 ec 48 sub $0x48,%rsp - 442053: e8 68 4f 02 00 callq 466fc0
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z|Fn01@VK=fJZ|kb_ukraZOi*tz55T~{Ri-Vzdir^Prduwcz+x3f8le|O5^3Xn|E?crdiMwXUC3bC+8_4X zbN9LTrQZGScabM~|4vVV`u*?2{X)y}f8gsj{{F99`x8!4vmgHb=X>`*#NQ)!_y2G5 zvx)up@!b9R+3}_q(DmisufhkhU;gVI?Ei5hT(OsLKjh~h-PmJj!NSMw2ZIZ)Azt*p qHm%+G{nOtw{so^mXaa9y)7-o{wu*jk)&BG~)_!K#?stFv_WwV&2>&Yp literal 0 HcmV?d00001 diff --git a/semantics/common/library/common-c-library-stdio.k b/semantics/common/library/common-c-library-stdio.k index d952cc8fa..53d2c18af 100644 --- a/semantics/common/library/common-c-library-stdio.k +++ b/semantics/common/library/common-c-library-stdio.k @@ -123,35 +123,35 @@ module COMMON-C-LIBRARY-STDIO syntax KItem ::= getFD(FilePointer) rule (.K => getValidFD(FDPtr)) ~> getFD(FDPtr::FilePointer) - requires notBool isNull(FDPtr) + requires notBool isNullFDPtr(FDPtr) rule invalidLibCValue ~> getFD(_) => "" rule FD:FD ~> getFD(_) => FD rule getFD(FDPtr::FilePointer) => error(outOfBoundsMemoryAccess) - requires isNull(FDPtr) + requires isNullFDPtr(FDPtr) syntax KItem ::= setFD(FilePointer, Int) rule setFD(FDPtr::FilePointer, FD::Int) => setValidFD(FDPtr, FD) - requires notBool isNull(FDPtr) + requires notBool isNullFDPtr(FDPtr) rule setFD(FDPtr::FilePointer, _::Int) => error(outOfBoundsMemoryAccess) - requires isNull(FDPtr) + requires isNullFDPtr(FDPtr) syntax KItem ::= getFPos(FPosPointer) rule (.K => getValidFPos(PosPtr)) ~> getFPos(PosPtr::FPosPointer) - requires notBool isNull(PosPtr) + requires notBool isNullFPosPtr(PosPtr) rule invalidLibCValue ~> getFPos(_) => fpos("", 0) rule FPos:FPos ~> getFPos(_) => FPos rule getFPos(PosPtr::FPosPointer) => error(outOfBoundsMemoryAccess) - requires isNull(PosPtr) + requires isNullFPosPtr(PosPtr) syntax KItem ::= setFPos(FPosPointer, String, Int) rule setFPos(PosPtr::FPosPointer, Path::String, Pos::Int) => setValidFPos(PosPtr, Path, Pos) - requires notBool isNull(PosPtr) + requires notBool isNullFPosPtr(PosPtr) rule setFPos(PosPtr::FPosPointer, _::String, _::Int) => error(outOfBoundsMemoryAccess) - requires isNull(PosPtr) + requires isNullFPosPtr(PosPtr) syntax Bool ::= isReadWritable(String) [function] rule isReadWritable("r+") => true @@ -198,10 +198,10 @@ module COMMON-C-LIBRARY-STDIO [structural] rule stdio_fflush(FDPtr::FilePointer) => fflush(getFD(FDPtr)) - requires notBool isNull(FDPtr) + requires notBool isNullFDPtr(FDPtr) [structural] rule stdio_fflush(FDPtr::FilePointer) => flushAll ~> success - requires isNull(FDPtr) + requires isNullFDPtr(FDPtr) [structural] syntax KItem ::= fsetpos(K, K) [seqstrict(1,2)] @@ -441,10 +441,10 @@ module COMMON-C-LIBRARY-STDIO [structural] rule stdio_fclose(FDPtr::FilePointer) => fclose(getFD(FDPtr), FDPtr) - requires notBool isNull(FDPtr) + requires notBool isNullFDPtr(FDPtr) [structural] rule stdio_fclose(FDPtr::FilePointer) => eof - requires isNull(FDPtr) + requires isNullFDPtr(FDPtr) [structural] syntax KItem ::= fclose(K, FilePointer) [strict(1)] @@ -473,10 +473,10 @@ module COMMON-C-LIBRARY-STDIO FDPtr::FilePointer) => freopen(Filename, Mode, FDPtr, getFD(FDPtr)) - requires notBool isNull(FDPtr) + requires notBool isNullFDPtr(FDPtr) [structural] rule stdio_freopen( _, _, FDPtr::FilePointer) => nullFilePointer - requires isNull(FDPtr) + requires isNullFDPtr(FDPtr) [structural] syntax KItem ::= freopen(StringPointer, StringPointer, FilePointer, K) @@ -486,7 +486,7 @@ module COMMON-C-LIBRARY-STDIO => fclose'(FD) ~> discard ~> fopen(FDPtr, readString(Filename), readString(Mode)) - requires notBool isNull(Filename) + requires notBool isNullStrPtr(Filename) [structural] rule freopen(Filename::StringPointer, Mode::StringPointer, @@ -495,7 +495,7 @@ module COMMON-C-LIBRARY-STDIO ... FD Filename':String - requires isNull(Filename) + requires isNullStrPtr(Filename) [structural] syntax KItem ::= fopen(FilePointer, K, K) [seqstrict(2,3)] @@ -537,23 +537,23 @@ module COMMON-C-LIBRARY-STDIO => trapStrBuf(StrPtr, bufSiz) ~> setbuf(getFD(FDPtr), fullBuf, bufSiz) ~> discard - requires notBool isNull(StrPtr) + requires notBool isNullStrPtr(StrPtr) [structural] rule stdio_setbuf(FDPtr::FilePointer, StrPtr::StringPointer) => setbuf(getFD(FDPtr), noBuf, bufSiz) ~> discard - requires isNull(StrPtr) + requires isNullStrPtr(StrPtr) [structural] rule stdio_setbuffer(FDPtr::FilePointer, StrPtr::StringPointer, Sz::Int) => trapStrBuf(StrPtr, Sz) ~> setbuf(getFD(FDPtr), fullBuf, Sz) ~> discard - requires notBool isNull(StrPtr) + requires notBool isNullStrPtr(StrPtr) [structural] rule stdio_setbuffer(FDPtr::FilePointer, StrPtr::StringPointer, Sz::Int) => setbuf(getFD(FDPtr), noBuf, Sz) ~> discard - requires isNull(StrPtr) + requires isNullStrPtr(StrPtr) [structural] rule stdio_setvbuf(FDPtr::FilePointer, StrPtr::StringPointer, 0, Sz::Int) @@ -576,12 +576,12 @@ module COMMON-C-LIBRARY-STDIO syntax KItem ::= trapBuf(BufferPointer, Int) rule trapBuf(BufPtr::BufferPointer, Sz::Int) => writeTrapBytes(BufPtr, Sz) - requires notBool isNull(BufPtr) andBool Sz >Int 0 + requires notBool isNullBufPtr(BufPtr) andBool Sz >Int 0 rule trapBuf(_, _) => .K syntax KItem ::= trapStrBuf(StringPointer, Int) rule trapStrBuf(StrPtr::StringPointer, Sz::Int) => writeTrapBytes(StrPtr, Sz) - requires notBool isNull(StrPtr) andBool Sz >Int 0 + requires notBool isNullStrPtr(StrPtr) andBool Sz >Int 0 rule trapStrBuf(_, _) => .K syntax KItem ::= setbuf(K, BufMode, Int) [strict(1)] diff --git a/semantics/common/library/common-c-library.k b/semantics/common/library/common-c-library.k index 2aba40b28..3875055eb 100644 --- a/semantics/common/library/common-c-library.k +++ b/semantics/common/library/common-c-library.k @@ -41,10 +41,10 @@ module COMMON-C-LIBRARY-OPAQUE-SYNTAX imports STRING // The following functions check for null. - syntax Bool ::= isNull(FilePointer) [function, klabel(isNullFDPtr)] - syntax Bool ::= isNull(FPosPointer) [function, klabel(isNullFPosPtr)] - syntax Bool ::= isNull(StringPointer) [function, klabel(isNullStrPtr)] - syntax Bool ::= isNull(BufferPointer) [function, klabel(isNullBufPtr)] + syntax Bool ::= isNullFDPtr(FilePointer) [function] + syntax Bool ::= isNullFPosPtr(FPosPointer) [function] + syntax Bool ::= isNullStrPtr(StringPointer) [function] + syntax Bool ::= isNullBufPtr(BufferPointer) [function] // The following functions should perform appropriate pointer arithmetic. syntax StringPointer ::= StringPointer "+chars" Int [function] diff --git a/semantics/immediateInstructions/adcb_al_imm8.k b/semantics/immediateInstructions/adcb_al_imm8.k index 28521ea90..d1db6c394 100644 --- a/semantics/immediateInstructions/adcb_al_imm8.k +++ b/semantics/immediateInstructions/adcb_al_imm8.k @@ -5,26 +5,27 @@ module ADCB-AL-IMM8 imports X86-CONFIGURATION rule - execinstr (adcb Imm8:Imm, %al, .Operands) => . + execinstr (adcb Imm8:MInt, %al, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 56), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9)) +"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 56), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9)) -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/adcb_r8_imm8.k b/semantics/immediateInstructions/adcb_r8_imm8.k index 0eeaf0432..f65368f92 100644 --- a/semantics/immediateInstructions/adcb_r8_imm8.k +++ b/semantics/immediateInstructions/adcb_r8_imm8.k @@ -5,26 +5,27 @@ module ADCB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (adcb Imm8:Imm, R2:R8, .Operands) => . + execinstr (adcb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9)) -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/adcb_rh_imm8.k b/semantics/immediateInstructions/adcb_rh_imm8.k index a025b0120..f8b919377 100644 --- a/semantics/immediateInstructions/adcb_rh_imm8.k +++ b/semantics/immediateInstructions/adcb_rh_imm8.k @@ -5,26 +5,27 @@ module ADCB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (adcb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (adcb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 51, 52)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 51, 52)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/adcl_eax_imm32.k b/semantics/immediateInstructions/adcl_eax_imm32.k index b117c8ec5..86f4bcd28 100644 --- a/semantics/immediateInstructions/adcl_eax_imm32.k +++ b/semantics/immediateInstructions/adcl_eax_imm32.k @@ -5,26 +5,27 @@ module ADCL-EAX-IMM32 imports X86-CONFIGURATION rule - execinstr (adcl Imm32:Imm, %eax, .Operands) => . + execinstr (adcl Imm32:MInt, %eax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33)) +"RAX" |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33)) -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm32, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm32, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/adcl_r32_imm32.k b/semantics/immediateInstructions/adcl_r32_imm32.k index 14427f729..c9255bd51 100644 --- a/semantics/immediateInstructions/adcl_r32_imm32.k +++ b/semantics/immediateInstructions/adcl_r32_imm32.k @@ -5,26 +5,27 @@ module ADCL-R32-IMM32 imports X86-CONFIGURATION rule - execinstr (adcl Imm32:Imm, R2:R32, .Operands) => . + execinstr (adcl Imm32:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm32, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm32, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/adcl_r32_imm8.k b/semantics/immediateInstructions/adcl_r32_imm8.k index 5e6491637..c499ab214 100644 --- a/semantics/immediateInstructions/adcl_r32_imm8.k +++ b/semantics/immediateInstructions/adcl_r32_imm8.k @@ -5,26 +5,27 @@ module ADCL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (adcl Imm8:Imm, R2:R32, .Operands) => . + execinstr (adcl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/adcq_r64_imm32.k b/semantics/immediateInstructions/adcq_r64_imm32.k index 26791db3c..03716b33c 100644 --- a/semantics/immediateInstructions/adcq_r64_imm32.k +++ b/semantics/immediateInstructions/adcq_r64_imm32.k @@ -5,26 +5,27 @@ module ADCQ-R64-IMM32 imports X86-CONFIGURATION rule - execinstr (adcq Imm32:Imm, R2:R64, .Operands) => . + execinstr (adcq Imm32:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) +convToRegKeys(R2) |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/adcq_r64_imm8.k b/semantics/immediateInstructions/adcq_r64_imm8.k index e7163a91a..75584ef82 100644 --- a/semantics/immediateInstructions/adcq_r64_imm8.k +++ b/semantics/immediateInstructions/adcq_r64_imm8.k @@ -5,26 +5,27 @@ module ADCQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (adcq Imm8:Imm, R2:R64, .Operands) => . + execinstr (adcq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) +convToRegKeys(R2) |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/adcq_rax_imm32.k b/semantics/immediateInstructions/adcq_rax_imm32.k index 606ca2b44..b289e48e7 100644 --- a/semantics/immediateInstructions/adcq_rax_imm32.k +++ b/semantics/immediateInstructions/adcq_rax_imm32.k @@ -5,26 +5,27 @@ module ADCQ-RAX-IMM32 imports X86-CONFIGURATION rule - execinstr (adcq Imm32:Imm, %rax, .Operands) => . + execinstr (adcq Imm32:MInt, %rax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65) +"RAX" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65) -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/adcw_ax_imm16.k b/semantics/immediateInstructions/adcw_ax_imm16.k index a0769e94b..5afbf0b28 100644 --- a/semantics/immediateInstructions/adcw_ax_imm16.k +++ b/semantics/immediateInstructions/adcw_ax_imm16.k @@ -5,26 +5,27 @@ module ADCW-AX-IMM16 imports X86-CONFIGURATION rule - execinstr (adcw Imm16:Imm, %ax, .Operands) => . + execinstr (adcw Imm16:MInt, %ax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17)) +"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17)) -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm16, 11, 12), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm16, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm16, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/adcw_r16_imm16.k b/semantics/immediateInstructions/adcw_r16_imm16.k index 4b27cbf13..0af492233 100644 --- a/semantics/immediateInstructions/adcw_r16_imm16.k +++ b/semantics/immediateInstructions/adcw_r16_imm16.k @@ -5,26 +5,27 @@ module ADCW-R16-IMM16 imports X86-CONFIGURATION rule - execinstr (adcw Imm16:Imm, R2:R16, .Operands) => . + execinstr (adcw Imm16:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm16, 11, 12), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm16, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm16, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/adcw_r16_imm8.k b/semantics/immediateInstructions/adcw_r16_imm8.k index 15a937d48..78e8a17b6 100644 --- a/semantics/immediateInstructions/adcw_r16_imm8.k +++ b/semantics/immediateInstructions/adcw_r16_imm8.k @@ -5,26 +5,27 @@ module ADCW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (adcw Imm8:Imm, R2:R16, .Operands) => . + execinstr (adcw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/addb_al_imm8.k b/semantics/immediateInstructions/addb_al_imm8.k index 98c0a035b..1c5345128 100644 --- a/semantics/immediateInstructions/addb_al_imm8.k +++ b/semantics/immediateInstructions/addb_al_imm8.k @@ -5,26 +5,27 @@ module ADDB-AL-IMM8 imports X86-CONFIGURATION rule - execinstr (addb Imm8:Imm, %al, .Operands) => . + execinstr (addb Imm8:MInt, %al, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 56), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9)) +"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 56), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9)) -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/addb_r8_imm8.k b/semantics/immediateInstructions/addb_r8_imm8.k index 5dc756dbc..d20c14542 100644 --- a/semantics/immediateInstructions/addb_r8_imm8.k +++ b/semantics/immediateInstructions/addb_r8_imm8.k @@ -5,26 +5,27 @@ module ADDB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (addb Imm8:Imm, R2:R8, .Operands) => . + execinstr (addb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9)) -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/addb_rh_imm8.k b/semantics/immediateInstructions/addb_rh_imm8.k index df381909c..61d7e62bc 100644 --- a/semantics/immediateInstructions/addb_rh_imm8.k +++ b/semantics/immediateInstructions/addb_rh_imm8.k @@ -5,26 +5,27 @@ module ADDB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (addb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (addb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 51, 52)), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 51, 52)), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/addl_eax_imm32.k b/semantics/immediateInstructions/addl_eax_imm32.k index 92f764010..9a9fdcc44 100644 --- a/semantics/immediateInstructions/addl_eax_imm32.k +++ b/semantics/immediateInstructions/addl_eax_imm32.k @@ -5,26 +5,27 @@ module ADDL-EAX-IMM32 imports X86-CONFIGURATION rule - execinstr (addl Imm32:Imm, %eax, .Operands) => . + execinstr (addl Imm32:MInt, %eax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33)) +"RAX" |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33)) -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm32, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm32, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/addl_r32_imm32.k b/semantics/immediateInstructions/addl_r32_imm32.k index 7856f4492..082cee38a 100644 --- a/semantics/immediateInstructions/addl_r32_imm32.k +++ b/semantics/immediateInstructions/addl_r32_imm32.k @@ -5,26 +5,27 @@ module ADDL-R32-IMM32 imports X86-CONFIGURATION rule - execinstr (addl Imm32:Imm, R2:R32, .Operands) => . + execinstr (addl Imm32:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm32, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm32, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/addl_r32_imm8.k b/semantics/immediateInstructions/addl_r32_imm8.k index ea74935d9..5bbbebbbf 100644 --- a/semantics/immediateInstructions/addl_r32_imm8.k +++ b/semantics/immediateInstructions/addl_r32_imm8.k @@ -5,26 +5,27 @@ module ADDL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (addl Imm8:Imm, R2:R32, .Operands) => . + execinstr (addl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/addq_r64_imm32.k b/semantics/immediateInstructions/addq_r64_imm32.k index 4b5e64bfd..b70848610 100644 --- a/semantics/immediateInstructions/addq_r64_imm32.k +++ b/semantics/immediateInstructions/addq_r64_imm32.k @@ -5,26 +5,27 @@ module ADDQ-R64-IMM32 imports X86-CONFIGURATION rule - execinstr (addq Imm32:Imm, R2:R64, .Operands) => . + execinstr (addq Imm32:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) +convToRegKeys(R2) |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/addq_r64_imm8.k b/semantics/immediateInstructions/addq_r64_imm8.k index 6face7fbc..ee3e1fd81 100644 --- a/semantics/immediateInstructions/addq_r64_imm8.k +++ b/semantics/immediateInstructions/addq_r64_imm8.k @@ -5,26 +5,27 @@ module ADDQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (addq Imm8:Imm, R2:R64, .Operands) => . + execinstr (addq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) +convToRegKeys(R2) |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/addq_rax_imm32.k b/semantics/immediateInstructions/addq_rax_imm32.k index 6366ad150..dd4acff82 100644 --- a/semantics/immediateInstructions/addq_rax_imm32.k +++ b/semantics/immediateInstructions/addq_rax_imm32.k @@ -5,26 +5,27 @@ module ADDQ-RAX-IMM32 imports X86-CONFIGURATION rule - execinstr (addq Imm32:Imm, %rax, .Operands) => . + execinstr (addq Imm32:MInt, %rax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65) +"RAX" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65) -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/addw_ax_imm16.k b/semantics/immediateInstructions/addw_ax_imm16.k index ca187db86..4c5d171dc 100644 --- a/semantics/immediateInstructions/addw_ax_imm16.k +++ b/semantics/immediateInstructions/addw_ax_imm16.k @@ -5,26 +5,27 @@ module ADDW-AX-IMM16 imports X86-CONFIGURATION rule - execinstr (addw Imm16:Imm, %ax, .Operands) => . + execinstr (addw Imm16:MInt, %ax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 48), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17)) +"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 48), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17)) -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm16, 11, 12), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm16, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm16, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/addw_r16_imm16.k b/semantics/immediateInstructions/addw_r16_imm16.k index f053830ea..fa58fed71 100644 --- a/semantics/immediateInstructions/addw_r16_imm16.k +++ b/semantics/immediateInstructions/addw_r16_imm16.k @@ -5,26 +5,27 @@ module ADDW-R16-IMM16 imports X86-CONFIGURATION rule - execinstr (addw Imm16:Imm, R2:R16, .Operands) => . + execinstr (addw Imm16:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm16, 11, 12), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm16, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm16, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/addw_r16_imm8.k b/semantics/immediateInstructions/addw_r16_imm8.k index b88f7bb9b..7fa5d5e06 100644 --- a/semantics/immediateInstructions/addw_r16_imm8.k +++ b/semantics/immediateInstructions/addw_r16_imm8.k @@ -5,26 +5,27 @@ module ADDW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (addw Imm8:Imm, R2:R16, .Operands) => . + execinstr (addw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/andb_al_imm8.k b/semantics/immediateInstructions/andb_al_imm8.k index 3767e3011..fd3ad2eaa 100644 --- a/semantics/immediateInstructions/andb_al_imm8.k +++ b/semantics/immediateInstructions/andb_al_imm8.k @@ -5,26 +5,27 @@ module ANDB-AL-IMM8 imports X86-CONFIGURATION rule - execinstr (andb Imm8:Imm, %al, .Operands) => . + execinstr (andb Imm8:MInt, %al, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 56), andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 64), handleImmediateWithSignExtend(Imm8, 8, 8))) +"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 56), andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 64), Imm8)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 64), Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/andb_r8_imm8.k b/semantics/immediateInstructions/andb_r8_imm8.k index 7e490cbd1..c7a0b6542 100644 --- a/semantics/immediateInstructions/andb_r8_imm8.k +++ b/semantics/immediateInstructions/andb_r8_imm8.k @@ -5,26 +5,27 @@ module ANDB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (andb Imm8:Imm, R2:R8, .Operands) => . + execinstr (andb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), andMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), handleImmediateWithSignExtend(Imm8, 8, 8))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), andMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), Imm8)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/andb_rh_imm8.k b/semantics/immediateInstructions/andb_rh_imm8.k index 849ae23ba..d2312eaa2 100644 --- a/semantics/immediateInstructions/andb_rh_imm8.k +++ b/semantics/immediateInstructions/andb_rh_imm8.k @@ -5,26 +5,27 @@ module ANDB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (andb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (andb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), andMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), handleImmediateWithSignExtend(Imm8, 8, 8))), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), andMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), Imm8)), extractMInt( getParentValue(R2, RSMap), 56, 64)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 55, 56), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 54, 55), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 53, 54), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 52, 53), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 51, 52), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 50, 51), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 49, 50), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 55, 56), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 54, 55), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 53, 54), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 52, 53), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 51, 52), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 50, 51), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 49, 50), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/andl_eax_imm32.k b/semantics/immediateInstructions/andl_eax_imm32.k index 6575f6520..575bc8deb 100644 --- a/semantics/immediateInstructions/andl_eax_imm32.k +++ b/semantics/immediateInstructions/andl_eax_imm32.k @@ -5,26 +5,27 @@ module ANDL-EAX-IMM32 imports X86-CONFIGURATION rule - execinstr (andl Imm32:Imm, %eax, .Operands) => . + execinstr (andl Imm32:MInt, %eax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( mi(32, 0), andMInt( extractMInt( getParentValue(%rax, RSMap), 32, 64), handleImmediateWithSignExtend(Imm32, 32, 32))) +"RAX" |-> concatenateMInt( mi(32, 0), andMInt( extractMInt( getParentValue(%rax, RSMap), 32, 64), Imm32)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 32, 64), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 32, 64), Imm32), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), extractMInt( Imm32, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/andl_r32_imm32.k b/semantics/immediateInstructions/andl_r32_imm32.k index e8689d3ce..9357a7cb6 100644 --- a/semantics/immediateInstructions/andl_r32_imm32.k +++ b/semantics/immediateInstructions/andl_r32_imm32.k @@ -5,26 +5,27 @@ module ANDL-R32-IMM32 imports X86-CONFIGURATION rule - execinstr (andl Imm32:Imm, R2:R32, .Operands) => . + execinstr (andl Imm32:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), andMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), handleImmediateWithSignExtend(Imm32, 32, 32))) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), andMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), Imm32)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), Imm32), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), extractMInt( Imm32, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/andl_r32_imm8.k b/semantics/immediateInstructions/andl_r32_imm8.k index 126b2ae1f..0ba6528e3 100644 --- a/semantics/immediateInstructions/andl_r32_imm8.k +++ b/semantics/immediateInstructions/andl_r32_imm8.k @@ -5,26 +5,27 @@ module ANDL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (andl Imm8:Imm, R2:R32, .Operands) => . + execinstr (andl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), andMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), andMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, svalueMInt(Imm8)))) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, svalueMInt(Imm8))), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/andq_r64_imm32.k b/semantics/immediateInstructions/andq_r64_imm32.k index a366e4f75..bcabce0fd 100644 --- a/semantics/immediateInstructions/andq_r64_imm32.k +++ b/semantics/immediateInstructions/andq_r64_imm32.k @@ -5,26 +5,27 @@ module ANDQ-R64-IMM32 imports X86-CONFIGURATION rule - execinstr (andq Imm32:Imm, R2:R64, .Operands) => . + execinstr (andq Imm32:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> andMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) +convToRegKeys(R2) |-> andMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(Imm32))) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(Imm32))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/andq_r64_imm8.k b/semantics/immediateInstructions/andq_r64_imm8.k index aeb6a0d69..17c477e89 100644 --- a/semantics/immediateInstructions/andq_r64_imm8.k +++ b/semantics/immediateInstructions/andq_r64_imm8.k @@ -5,26 +5,27 @@ module ANDQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (andq Imm8:Imm, R2:R64, .Operands) => . + execinstr (andq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> andMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) +convToRegKeys(R2) |-> andMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(Imm8))) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(Imm8))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/andq_rax_imm32.k b/semantics/immediateInstructions/andq_rax_imm32.k index 004e0ca3a..03856141e 100644 --- a/semantics/immediateInstructions/andq_rax_imm32.k +++ b/semantics/immediateInstructions/andq_rax_imm32.k @@ -5,26 +5,27 @@ module ANDQ-RAX-IMM32 imports X86-CONFIGURATION rule - execinstr (andq Imm32:Imm, %rax, .Operands) => . + execinstr (andq Imm32:MInt, %rax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> andMInt( getParentValue(%rax, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) +"RAX" |-> andMInt( getParentValue(%rax, RSMap), mi(64, svalueMInt(Imm32))) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( getParentValue(%rax, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( getParentValue(%rax, RSMap), mi(64, svalueMInt(Imm32))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/andw_ax_imm16.k b/semantics/immediateInstructions/andw_ax_imm16.k index 57abcd076..23e3b7981 100644 --- a/semantics/immediateInstructions/andw_ax_imm16.k +++ b/semantics/immediateInstructions/andw_ax_imm16.k @@ -5,26 +5,27 @@ module ANDW-AX-IMM16 imports X86-CONFIGURATION rule - execinstr (andw Imm16:Imm, %ax, .Operands) => . + execinstr (andw Imm16:MInt, %ax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 48), andMInt( extractMInt( getParentValue(%rax, RSMap), 48, 64), handleImmediateWithSignExtend(Imm16, 16, 16))) +"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 48), andMInt( extractMInt( getParentValue(%rax, RSMap), 48, 64), Imm16)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 15, 16)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 14, 15)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 13, 14)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 12, 13)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 10, 11)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 9, 10)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm16, 15, 16)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm16, 14, 15)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm16, 13, 14)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm16, 12, 13)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm16, 11, 12)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm16, 10, 11)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm16, 9, 10)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm16, 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 48, 64), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 48, 64), Imm16), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), extractMInt( Imm16, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/andw_r16_imm16.k b/semantics/immediateInstructions/andw_r16_imm16.k index e84db6e52..932520799 100644 --- a/semantics/immediateInstructions/andw_r16_imm16.k +++ b/semantics/immediateInstructions/andw_r16_imm16.k @@ -5,26 +5,27 @@ module ANDW-R16-IMM16 imports X86-CONFIGURATION rule - execinstr (andw Imm16:Imm, R2:R16, .Operands) => . + execinstr (andw Imm16:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), andMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), handleImmediateWithSignExtend(Imm16, 16, 16))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), andMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), Imm16)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 15, 16)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 14, 15)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 13, 14)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 12, 13)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 10, 11)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 9, 10)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm16, 15, 16)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm16, 14, 15)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm16, 13, 14)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm16, 12, 13)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm16, 11, 12)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm16, 10, 11)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm16, 9, 10)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm16, 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), Imm16), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( Imm16, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/andw_r16_imm8.k b/semantics/immediateInstructions/andw_r16_imm8.k index 5438e4046..291b09534 100644 --- a/semantics/immediateInstructions/andw_r16_imm8.k +++ b/semantics/immediateInstructions/andw_r16_imm8.k @@ -5,26 +5,27 @@ module ANDW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (andw Imm8:Imm, R2:R16, .Operands) => . + execinstr (andw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), andMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), andMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(16, svalueMInt(Imm8)))) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(16, svalueMInt(Imm8))), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/blendpd_xmm_xmm_imm8.k b/semantics/immediateInstructions/blendpd_xmm_xmm_imm8.k index e9ebce867..718ab1618 100644 --- a/semantics/immediateInstructions/blendpd_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/blendpd_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module BLENDPD-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (blendpd Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (blendpd Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 192) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 256) #else extractMInt( getParentValue(R2, RSMap), 192, 256) #fi))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 192) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 256) #else extractMInt( getParentValue(R2, RSMap), 192, 256) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/blendps_xmm_xmm_imm8.k b/semantics/immediateInstructions/blendps_xmm_xmm_imm8.k index cbc2a8235..190d4481b 100644 --- a/semantics/immediateInstructions/blendps_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/blendps_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module BLENDPS-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (blendps Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (blendps Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 160, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 160, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/btcl_r32_imm8.k b/semantics/immediateInstructions/btcl_r32_imm8.k index 7994b200a..33479f647 100644 --- a/semantics/immediateInstructions/btcl_r32_imm8.k +++ b/semantics/immediateInstructions/btcl_r32_imm8.k @@ -5,13 +5,13 @@ module BTCL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (btcl Imm8:Imm, R2:R32, .Operands) => . + execinstr (btcl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), xorMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), shiftLeftMInt( mi(32, 1), uvalueMInt(mi(32, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))))))) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), xorMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), shiftLeftMInt( mi(32, 1), uvalueMInt(mi(32, svalueMInt(andMInt( Imm8, mi(8, 31)))))))) -"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(mi(32, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))))), 31, 32) +"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(mi(32, svalueMInt(andMInt( Imm8, mi(8, 31)))))), 31, 32) "PF" |-> (undefMInt) @@ -23,6 +23,7 @@ convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), xorMInt( extractMInt( getParen ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/btcq_r64_imm8.k b/semantics/immediateInstructions/btcq_r64_imm8.k index 6c7a97b5e..ac7ac1d96 100644 --- a/semantics/immediateInstructions/btcq_r64_imm8.k +++ b/semantics/immediateInstructions/btcq_r64_imm8.k @@ -5,13 +5,13 @@ module BTCQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (btcq Imm8:Imm, R2:R64, .Operands) => . + execinstr (btcq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> xorMInt( getParentValue(R2, RSMap), shiftLeftMInt( mi(64, 1), uvalueMInt(mi(64, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))))) +convToRegKeys(R2) |-> xorMInt( getParentValue(R2, RSMap), shiftLeftMInt( mi(64, 1), uvalueMInt(mi(64, svalueMInt(andMInt( Imm8, mi(8, 63))))))) -"CF" |-> extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(mi(64, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))))), 63, 64) +"CF" |-> extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(mi(64, svalueMInt(andMInt( Imm8, mi(8, 63)))))), 63, 64) "PF" |-> (undefMInt) @@ -23,6 +23,7 @@ convToRegKeys(R2) |-> xorMInt( getParentValue(R2, RSMap), shiftLeftMInt( mi(64, ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/btcw_r16_imm8.k b/semantics/immediateInstructions/btcw_r16_imm8.k index b817247be..433f69826 100644 --- a/semantics/immediateInstructions/btcw_r16_imm8.k +++ b/semantics/immediateInstructions/btcw_r16_imm8.k @@ -5,13 +5,13 @@ module BTCW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (btcw Imm8:Imm, R2:R16, .Operands) => . + execinstr (btcw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), shiftLeftMInt( mi(16, 1), uvalueMInt(mi(16, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 15)))))))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), shiftLeftMInt( mi(16, 1), uvalueMInt(mi(16, svalueMInt(andMInt( Imm8, mi(8, 15)))))))) -"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), uvalueMInt(mi(16, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 15)))))), 15, 16) +"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), uvalueMInt(mi(16, svalueMInt(andMInt( Imm8, mi(8, 15)))))), 15, 16) "PF" |-> (undefMInt) @@ -23,6 +23,7 @@ convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0 ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/btl_r32_imm8.k b/semantics/immediateInstructions/btl_r32_imm8.k index 5b3ef7855..f93177366 100644 --- a/semantics/immediateInstructions/btl_r32_imm8.k +++ b/semantics/immediateInstructions/btl_r32_imm8.k @@ -5,11 +5,11 @@ module BTL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (btl Imm8:Imm, R2:R32, .Operands) => . + execinstr (btl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(mi(32, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))))), 31, 32) +"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(mi(32, svalueMInt(andMInt( Imm8, mi(8, 31)))))), 31, 32) "PF" |-> (undefMInt) @@ -21,6 +21,7 @@ RSMap:Map => updateMap(RSMap, ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/btq_r64_imm8.k b/semantics/immediateInstructions/btq_r64_imm8.k index 490d355c5..3faba1fc7 100644 --- a/semantics/immediateInstructions/btq_r64_imm8.k +++ b/semantics/immediateInstructions/btq_r64_imm8.k @@ -5,11 +5,11 @@ module BTQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (btq Imm8:Imm, R2:R64, .Operands) => . + execinstr (btq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(mi(64, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))))), 63, 64) +"CF" |-> extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(mi(64, svalueMInt(andMInt( Imm8, mi(8, 63)))))), 63, 64) "PF" |-> (undefMInt) @@ -21,6 +21,7 @@ RSMap:Map => updateMap(RSMap, ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/btrl_r32_imm8.k b/semantics/immediateInstructions/btrl_r32_imm8.k index ef24cd754..18d7fc3f1 100644 --- a/semantics/immediateInstructions/btrl_r32_imm8.k +++ b/semantics/immediateInstructions/btrl_r32_imm8.k @@ -5,13 +5,13 @@ module BTRL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (btrl Imm8:Imm, R2:R32, .Operands) => . + execinstr (btrl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), andMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), negMInt( shiftLeftMInt( mi(32, 1), uvalueMInt(mi(32, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))))))) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), andMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), negMInt( shiftLeftMInt( mi(32, 1), uvalueMInt(mi(32, svalueMInt(andMInt( Imm8, mi(8, 31))))))))) -"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(mi(32, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))))), 31, 32) +"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(mi(32, svalueMInt(andMInt( Imm8, mi(8, 31)))))), 31, 32) "PF" |-> (undefMInt) @@ -23,6 +23,7 @@ convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), andMInt( extractMInt( getParen ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/btrq_r64_imm8.k b/semantics/immediateInstructions/btrq_r64_imm8.k index 155df1033..7553de254 100644 --- a/semantics/immediateInstructions/btrq_r64_imm8.k +++ b/semantics/immediateInstructions/btrq_r64_imm8.k @@ -5,13 +5,13 @@ module BTRQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (btrq Imm8:Imm, R2:R64, .Operands) => . + execinstr (btrq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> andMInt( getParentValue(R2, RSMap), negMInt( shiftLeftMInt( mi(64, 1), uvalueMInt(mi(64, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))))))) +convToRegKeys(R2) |-> andMInt( getParentValue(R2, RSMap), negMInt( shiftLeftMInt( mi(64, 1), uvalueMInt(mi(64, svalueMInt(andMInt( Imm8, mi(8, 63)))))))) -"CF" |-> extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(mi(64, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))))), 63, 64) +"CF" |-> extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(mi(64, svalueMInt(andMInt( Imm8, mi(8, 63)))))), 63, 64) "PF" |-> (undefMInt) @@ -23,6 +23,7 @@ convToRegKeys(R2) |-> andMInt( getParentValue(R2, RSMap), negMInt( shiftLeftMInt ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/btrw_r16_imm8.k b/semantics/immediateInstructions/btrw_r16_imm8.k index 5452e91bf..5c940cb10 100644 --- a/semantics/immediateInstructions/btrw_r16_imm8.k +++ b/semantics/immediateInstructions/btrw_r16_imm8.k @@ -5,13 +5,13 @@ module BTRW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (btrw Imm8:Imm, R2:R16, .Operands) => . + execinstr (btrw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), andMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), negMInt( shiftLeftMInt( mi(16, 1), uvalueMInt(mi(16, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 15))))))))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), andMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), negMInt( shiftLeftMInt( mi(16, 1), uvalueMInt(mi(16, svalueMInt(andMInt( Imm8, mi(8, 15))))))))) -"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), uvalueMInt(mi(16, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 15)))))), 15, 16) +"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), uvalueMInt(mi(16, svalueMInt(andMInt( Imm8, mi(8, 15)))))), 15, 16) "PF" |-> (undefMInt) @@ -23,6 +23,7 @@ convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0 ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/btsl_r32_imm8.k b/semantics/immediateInstructions/btsl_r32_imm8.k index 837d27cc6..021453338 100644 --- a/semantics/immediateInstructions/btsl_r32_imm8.k +++ b/semantics/immediateInstructions/btsl_r32_imm8.k @@ -5,13 +5,13 @@ module BTSL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (btsl Imm8:Imm, R2:R32, .Operands) => . + execinstr (btsl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), orMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), shiftLeftMInt( mi(32, 1), uvalueMInt(mi(32, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))))))) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), orMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), shiftLeftMInt( mi(32, 1), uvalueMInt(mi(32, svalueMInt(andMInt( Imm8, mi(8, 31)))))))) -"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(mi(32, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))))), 31, 32) +"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(mi(32, svalueMInt(andMInt( Imm8, mi(8, 31)))))), 31, 32) "PF" |-> (undefMInt) @@ -23,6 +23,7 @@ convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), orMInt( extractMInt( getParent ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/btsq_r64_imm8.k b/semantics/immediateInstructions/btsq_r64_imm8.k index 8a9cf93b1..025a173f9 100644 --- a/semantics/immediateInstructions/btsq_r64_imm8.k +++ b/semantics/immediateInstructions/btsq_r64_imm8.k @@ -5,13 +5,13 @@ module BTSQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (btsq Imm8:Imm, R2:R64, .Operands) => . + execinstr (btsq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> orMInt( getParentValue(R2, RSMap), shiftLeftMInt( mi(64, 1), uvalueMInt(mi(64, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))))) +convToRegKeys(R2) |-> orMInt( getParentValue(R2, RSMap), shiftLeftMInt( mi(64, 1), uvalueMInt(mi(64, svalueMInt(andMInt( Imm8, mi(8, 63))))))) -"CF" |-> extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(mi(64, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))))), 63, 64) +"CF" |-> extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(mi(64, svalueMInt(andMInt( Imm8, mi(8, 63)))))), 63, 64) "PF" |-> (undefMInt) @@ -23,6 +23,7 @@ convToRegKeys(R2) |-> orMInt( getParentValue(R2, RSMap), shiftLeftMInt( mi(64, 1 ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/btsw_r16_imm8.k b/semantics/immediateInstructions/btsw_r16_imm8.k index b8795b147..ea2a84a37 100644 --- a/semantics/immediateInstructions/btsw_r16_imm8.k +++ b/semantics/immediateInstructions/btsw_r16_imm8.k @@ -5,13 +5,13 @@ module BTSW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (btsw Imm8:Imm, R2:R16, .Operands) => . + execinstr (btsw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), orMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), shiftLeftMInt( mi(16, 1), uvalueMInt(mi(16, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 15)))))))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), orMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), shiftLeftMInt( mi(16, 1), uvalueMInt(mi(16, svalueMInt(andMInt( Imm8, mi(8, 15)))))))) -"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), uvalueMInt(mi(16, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 15)))))), 15, 16) +"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), uvalueMInt(mi(16, svalueMInt(andMInt( Imm8, mi(8, 15)))))), 15, 16) "PF" |-> (undefMInt) @@ -23,6 +23,7 @@ convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0 ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/btw_r16_imm8.k b/semantics/immediateInstructions/btw_r16_imm8.k index bd817430c..836f1d9e8 100644 --- a/semantics/immediateInstructions/btw_r16_imm8.k +++ b/semantics/immediateInstructions/btw_r16_imm8.k @@ -5,11 +5,11 @@ module BTW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (btw Imm8:Imm, R2:R16, .Operands) => . + execinstr (btw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), uvalueMInt(mi(16, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 15)))))), 15, 16) +"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), uvalueMInt(mi(16, svalueMInt(andMInt( Imm8, mi(8, 15)))))), 15, 16) "PF" |-> (undefMInt) @@ -21,6 +21,7 @@ RSMap:Map => updateMap(RSMap, ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/cmpb_al_imm8.k b/semantics/immediateInstructions/cmpb_al_imm8.k index 45332095a..cb9434fd3 100644 --- a/semantics/immediateInstructions/cmpb_al_imm8.k +++ b/semantics/immediateInstructions/cmpb_al_imm8.k @@ -5,24 +5,25 @@ module CMPB-AL-IMM8 imports X86-CONFIGURATION rule - execinstr (cmpb Imm8:Imm, %al, .Operands) => . + execinstr (cmpb Imm8:MInt, %al, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/cmpb_r8_imm8.k b/semantics/immediateInstructions/cmpb_r8_imm8.k index 7d9b2a57c..b2ecbead1 100644 --- a/semantics/immediateInstructions/cmpb_r8_imm8.k +++ b/semantics/immediateInstructions/cmpb_r8_imm8.k @@ -5,24 +5,25 @@ module CMPB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (cmpb Imm8:Imm, R2:R8, .Operands) => . + execinstr (cmpb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/cmpb_rh_imm8.k b/semantics/immediateInstructions/cmpb_rh_imm8.k index 7746acbe6..a7ddaa8b2 100644 --- a/semantics/immediateInstructions/cmpb_rh_imm8.k +++ b/semantics/immediateInstructions/cmpb_rh_imm8.k @@ -5,24 +5,25 @@ module CMPB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (cmpb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (cmpb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 51, 52)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 51, 52)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/cmpl_eax_imm32.k b/semantics/immediateInstructions/cmpl_eax_imm32.k index d9732c928..769fe7ea1 100644 --- a/semantics/immediateInstructions/cmpl_eax_imm32.k +++ b/semantics/immediateInstructions/cmpl_eax_imm32.k @@ -5,24 +5,25 @@ module CMPL-EAX-IMM32 imports X86-CONFIGURATION rule - execinstr (cmpl Imm32:Imm, %eax, .Operands) => . + execinstr (cmpl Imm32:MInt, %eax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/cmpl_r32_imm32.k b/semantics/immediateInstructions/cmpl_r32_imm32.k index 089410bf1..d135eaf95 100644 --- a/semantics/immediateInstructions/cmpl_r32_imm32.k +++ b/semantics/immediateInstructions/cmpl_r32_imm32.k @@ -5,24 +5,25 @@ module CMPL-R32-IMM32 imports X86-CONFIGURATION rule - execinstr (cmpl Imm32:Imm, R2:R32, .Operands) => . + execinstr (cmpl Imm32:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/cmpl_r32_imm8.k b/semantics/immediateInstructions/cmpl_r32_imm8.k index 553221e9d..fbe8ce041 100644 --- a/semantics/immediateInstructions/cmpl_r32_imm8.k +++ b/semantics/immediateInstructions/cmpl_r32_imm8.k @@ -5,24 +5,25 @@ module CMPL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (cmpl Imm8:Imm, R2:R32, .Operands) => . + execinstr (cmpl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/cmppd_xmm_xmm_imm8.k b/semantics/immediateInstructions/cmppd_xmm_xmm_imm8.k index c5e3ef429..ebad58d81 100644 --- a/semantics/immediateInstructions/cmppd_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/cmppd_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module CMPPD-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (cmppd Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (cmppd Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( getParentValue(R2, RSMap), 128, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( getParentValue(R2, RSMap), 128, 192), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/cmpps_xmm_xmm_imm8.k b/semantics/immediateInstructions/cmpps_xmm_xmm_imm8.k index 6daefaaac..58e1b5815 100644 --- a/semantics/immediateInstructions/cmpps_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/cmpps_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module CMPPS-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (cmpps Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (cmpps Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/cmpq_r64_imm32.k b/semantics/immediateInstructions/cmpq_r64_imm32.k index 098d0d7b1..e9fdeae98 100644 --- a/semantics/immediateInstructions/cmpq_r64_imm32.k +++ b/semantics/immediateInstructions/cmpq_r64_imm32.k @@ -5,24 +5,25 @@ module CMPQ-R64-IMM32 imports X86-CONFIGURATION rule - execinstr (cmpq Imm32:Imm, R2:R64, .Operands) => . + execinstr (cmpq Imm32:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/cmpq_r64_imm8.k b/semantics/immediateInstructions/cmpq_r64_imm8.k index 31afa9136..45c1feb53 100644 --- a/semantics/immediateInstructions/cmpq_r64_imm8.k +++ b/semantics/immediateInstructions/cmpq_r64_imm8.k @@ -5,24 +5,25 @@ module CMPQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (cmpq Imm8:Imm, R2:R64, .Operands) => . + execinstr (cmpq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/cmpq_rax_imm32.k b/semantics/immediateInstructions/cmpq_rax_imm32.k index c40b120a6..6235d4060 100644 --- a/semantics/immediateInstructions/cmpq_rax_imm32.k +++ b/semantics/immediateInstructions/cmpq_rax_imm32.k @@ -5,24 +5,25 @@ module CMPQ-RAX-IMM32 imports X86-CONFIGURATION rule - execinstr (cmpq Imm32:Imm, %rax, .Operands) => . + execinstr (cmpq Imm32:MInt, %rax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/cmpsd_xmm_xmm_imm8.k b/semantics/immediateInstructions/cmpsd_xmm_xmm_imm8.k index 67f323431..989ff62a4 100644 --- a/semantics/immediateInstructions/cmpsd_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/cmpsd_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module CMPSD-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (cmpsd Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (cmpsd Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 192), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi)) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 192), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/cmpss_xmm_xmm_imm8.k b/semantics/immediateInstructions/cmpss_xmm_xmm_imm8.k index 5921b29ba..361511237 100644 --- a/semantics/immediateInstructions/cmpss_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/cmpss_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module CMPSS-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (cmpss Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (cmpss Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 224), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi)) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 224), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/cmpw_ax_imm16.k b/semantics/immediateInstructions/cmpw_ax_imm16.k index 68c4909ad..bf10107bd 100644 --- a/semantics/immediateInstructions/cmpw_ax_imm16.k +++ b/semantics/immediateInstructions/cmpw_ax_imm16.k @@ -5,24 +5,25 @@ module CMPW-AX-IMM16 imports X86-CONFIGURATION rule - execinstr (cmpw Imm16:Imm, %ax, .Operands) => . + execinstr (cmpw Imm16:MInt, %ax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm16, 11, 12), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/cmpw_r16_imm16.k b/semantics/immediateInstructions/cmpw_r16_imm16.k index d237acdb4..b2e151a7d 100644 --- a/semantics/immediateInstructions/cmpw_r16_imm16.k +++ b/semantics/immediateInstructions/cmpw_r16_imm16.k @@ -5,24 +5,25 @@ module CMPW-R16-IMM16 imports X86-CONFIGURATION rule - execinstr (cmpw Imm16:Imm, R2:R16, .Operands) => . + execinstr (cmpw Imm16:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm16, 11, 12), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/cmpw_r16_imm8.k b/semantics/immediateInstructions/cmpw_r16_imm8.k index 6fce01d8b..b70c61ae8 100644 --- a/semantics/immediateInstructions/cmpw_r16_imm8.k +++ b/semantics/immediateInstructions/cmpw_r16_imm8.k @@ -5,24 +5,25 @@ module CMPW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (cmpw Imm8:Imm, R2:R16, .Operands) => . + execinstr (cmpw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/dppd_xmm_xmm_imm8.k b/semantics/immediateInstructions/dppd_xmm_xmm_imm8.k index b1fe5b276..d2b684705 100644 --- a/semantics/immediateInstructions/dppd_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/dppd_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module DPPD-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (dppd Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (dppd Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( getParentValue(R2, RSMap), 128, 192)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( getParentValue(R2, RSMap), 128, 192)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( getParentValue(R2, RSMap), 128, 192)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( getParentValue(R2, RSMap), 128, 192)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/dpps_xmm_xmm_imm8.k b/semantics/immediateInstructions/dpps_xmm_xmm_imm8.k index 400d5ae00..860c595e9 100644 --- a/semantics/immediateInstructions/dpps_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/dpps_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module DPPS-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (dpps Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (dpps Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/extractps_r32_xmm_imm8.k b/semantics/immediateInstructions/extractps_r32_xmm_imm8.k index 4a9873a3a..48f94246d 100644 --- a/semantics/immediateInstructions/extractps_r32_xmm_imm8.k +++ b/semantics/immediateInstructions/extractps_r32_xmm_imm8.k @@ -5,14 +5,15 @@ module EXTRACTPS-R32-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (extractps Imm8:Imm, R2:Xmm, R3:R32, .Operands) => . + execinstr (extractps Imm8:MInt, R2:Xmm, R3:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128)) +convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/extractps_r64_xmm_imm8.k b/semantics/immediateInstructions/extractps_r64_xmm_imm8.k index 8748b1321..438a0467f 100644 --- a/semantics/immediateInstructions/extractps_r64_xmm_imm8.k +++ b/semantics/immediateInstructions/extractps_r64_xmm_imm8.k @@ -5,14 +5,15 @@ module EXTRACTPS-R64-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (extractps Imm8:Imm, R2:Xmm, R3:R64, .Operands) => . + execinstr (extractps Imm8:MInt, R2:Xmm, R3:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128)) +convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/imull_r32_r32_imm32.k b/semantics/immediateInstructions/imull_r32_r32_imm32.k index 57702c445..67c1829d9 100644 --- a/semantics/immediateInstructions/imull_r32_r32_imm32.k +++ b/semantics/immediateInstructions/imull_r32_r32_imm32.k @@ -5,13 +5,13 @@ module IMULL-R32-R32-IMM32 imports X86-CONFIGURATION rule - execinstr (imull Imm32:Imm, R2:R32, R3:R32, .Operands) => . + execinstr (imull Imm32:MInt, R2:R32, R3:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), 32, 64)) +convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(Imm32))), 32, 64)) -"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(Imm32))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(Imm32))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) "PF" |-> (undefMInt) @@ -21,10 +21,11 @@ convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( mulMInt( mi(64, s "SF" |-> (undefMInt) -"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(Imm32))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(Imm32))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/imull_r32_r32_imm8.k b/semantics/immediateInstructions/imull_r32_r32_imm8.k index fb6071837..0c581bb88 100644 --- a/semantics/immediateInstructions/imull_r32_r32_imm8.k +++ b/semantics/immediateInstructions/imull_r32_r32_imm8.k @@ -5,13 +5,13 @@ module IMULL-R32-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (imull Imm8:Imm, R2:R32, R3:R32, .Operands) => . + execinstr (imull Imm8:MInt, R2:R32, R3:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 32, 64)) +convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(Imm8))), 32, 64)) -"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(Imm8))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(Imm8))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) "PF" |-> (undefMInt) @@ -21,10 +21,11 @@ convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( mulMInt( mi(64, s "SF" |-> (undefMInt) -"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(Imm8))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(Imm8))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/imulq_r64_r64_imm32.k b/semantics/immediateInstructions/imulq_r64_r64_imm32.k index f88104746..0e2abacb7 100644 --- a/semantics/immediateInstructions/imulq_r64_r64_imm32.k +++ b/semantics/immediateInstructions/imulq_r64_r64_imm32.k @@ -5,13 +5,13 @@ module IMULQ-R64-R64-IMM32 imports X86-CONFIGURATION rule - execinstr (imulq Imm32:Imm, R2:R64, R3:R64, .Operands) => . + execinstr (imulq Imm32:MInt, R2:R64, R3:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> extractMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), 64, 128) +convToRegKeys(R3) |-> extractMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(Imm32))), 64, 128) -"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(Imm32))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(Imm32))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) "PF" |-> (undefMInt) @@ -21,10 +21,11 @@ convToRegKeys(R3) |-> extractMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2 "SF" |-> (undefMInt) -"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(Imm32))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(Imm32))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/imulq_r64_r64_imm8.k b/semantics/immediateInstructions/imulq_r64_r64_imm8.k index 09f92931c..231eef2cd 100644 --- a/semantics/immediateInstructions/imulq_r64_r64_imm8.k +++ b/semantics/immediateInstructions/imulq_r64_r64_imm8.k @@ -5,13 +5,13 @@ module IMULQ-R64-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (imulq Imm8:Imm, R2:R64, R3:R64, .Operands) => . + execinstr (imulq Imm8:MInt, R2:R64, R3:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> extractMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 64, 128) +convToRegKeys(R3) |-> extractMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(Imm8))), 64, 128) -"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(Imm8))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(Imm8))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) "PF" |-> (undefMInt) @@ -21,10 +21,11 @@ convToRegKeys(R3) |-> extractMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2 "SF" |-> (undefMInt) -"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(Imm8))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(Imm8))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/imulw_r16_r16_imm16.k b/semantics/immediateInstructions/imulw_r16_r16_imm16.k index 5a83cb2cf..3815f7edc 100644 --- a/semantics/immediateInstructions/imulw_r16_r16_imm16.k +++ b/semantics/immediateInstructions/imulw_r16_r16_imm16.k @@ -5,13 +5,13 @@ module IMULW-R16-R16-IMM16 imports X86-CONFIGURATION rule - execinstr (imulw Imm16:Imm, R2:R16, R3:R16, .Operands) => . + execinstr (imulw Imm16:MInt, R2:R16, R3:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 48), extractMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm16, 16, 16)))), 16, 32)) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 48), extractMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(Imm16))), 16, 32)) -"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm16, 16, 16)))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm16, 16, 16)))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(Imm16))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(Imm16))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) "PF" |-> (undefMInt) @@ -21,10 +21,11 @@ convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0 "SF" |-> (undefMInt) -"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm16, 16, 16)))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm16, 16, 16)))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(Imm16))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(Imm16))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/imulw_r16_r16_imm8.k b/semantics/immediateInstructions/imulw_r16_r16_imm8.k index 24b0d6d3b..a7c5657ce 100644 --- a/semantics/immediateInstructions/imulw_r16_r16_imm8.k +++ b/semantics/immediateInstructions/imulw_r16_r16_imm8.k @@ -5,13 +5,13 @@ module IMULW-R16-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (imulw Imm8:Imm, R2:R16, R3:R16, .Operands) => . + execinstr (imulw Imm8:MInt, R2:R16, R3:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 48), extractMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 16, 32)) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 48), extractMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(Imm8))), 16, 32)) -"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(Imm8))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(Imm8))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) "PF" |-> (undefMInt) @@ -21,10 +21,11 @@ convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0 "SF" |-> (undefMInt) -"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(Imm8))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(Imm8))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/insertps_xmm_xmm_imm8.k b/semantics/immediateInstructions/insertps_xmm_xmm_imm8.k index 257c1c32b..9dfedb717 100644 --- a/semantics/immediateInstructions/insertps_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/insertps_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module INSERTPS-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (insertps Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (insertps Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #fi) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #else extractMInt( getParentValue(R3, RSMap), 160, 192) #fi) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #fi) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #else extractMInt( getParentValue(R3, RSMap), 160, 192) #fi) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/movb_r8_imm8.k b/semantics/immediateInstructions/movb_r8_imm8.k index f5f3fca11..b7ab26b3b 100644 --- a/semantics/immediateInstructions/movb_r8_imm8.k +++ b/semantics/immediateInstructions/movb_r8_imm8.k @@ -5,14 +5,15 @@ module MOVB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (movb Imm8:Imm, R2:R8, .Operands) => . + execinstr (movb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), handleImmediateWithSignExtend(Imm8, 8, 8)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), Imm8) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/movb_rh_imm8.k b/semantics/immediateInstructions/movb_rh_imm8.k index f4592e2b2..f8da98827 100644 --- a/semantics/immediateInstructions/movb_rh_imm8.k +++ b/semantics/immediateInstructions/movb_rh_imm8.k @@ -5,14 +5,15 @@ module MOVB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (movb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (movb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), handleImmediateWithSignExtend(Imm8, 8, 8)), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), Imm8), extractMInt( getParentValue(R2, RSMap), 56, 64)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/movl_r32_imm32.k b/semantics/immediateInstructions/movl_r32_imm32.k index 6555f7f5a..0fed3fbb9 100644 --- a/semantics/immediateInstructions/movl_r32_imm32.k +++ b/semantics/immediateInstructions/movl_r32_imm32.k @@ -5,14 +5,15 @@ module MOVL-R32-IMM32 imports X86-CONFIGURATION rule - execinstr (movl Imm32:Imm, R2:R32, .Operands) => . + execinstr (movl Imm32:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), Imm32) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/movq_r64_imm32.k b/semantics/immediateInstructions/movq_r64_imm32.k index 73f896b97..12a2bed0f 100644 --- a/semantics/immediateInstructions/movq_r64_imm32.k +++ b/semantics/immediateInstructions/movq_r64_imm32.k @@ -5,14 +5,15 @@ module MOVQ-R64-IMM32 imports X86-CONFIGURATION rule - execinstr (movq Imm32:Imm, R2:R64, .Operands) => . + execinstr (movq Imm32:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))) +convToRegKeys(R2) |-> mi(64, svalueMInt(Imm32)) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/movq_r64_imm64.k b/semantics/immediateInstructions/movq_r64_imm64.k index cc4a8e719..7f2cdfeb6 100644 --- a/semantics/immediateInstructions/movq_r64_imm64.k +++ b/semantics/immediateInstructions/movq_r64_imm64.k @@ -5,14 +5,15 @@ module MOVQ-R64-IMM64 imports X86-CONFIGURATION rule - execinstr (movq Imm64:Imm, R2:R64, .Operands) => . + execinstr (movq Imm64:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> handleImmediateWithSignExtend(Imm64, 64, 64) +convToRegKeys(R2) |-> Imm64 ) + requires bitwidthMInt(Imm64) ==Int 64 endmodule diff --git a/semantics/immediateInstructions/movw_r16_imm16.k b/semantics/immediateInstructions/movw_r16_imm16.k index d7cec4199..a6a1ff2dc 100644 --- a/semantics/immediateInstructions/movw_r16_imm16.k +++ b/semantics/immediateInstructions/movw_r16_imm16.k @@ -5,14 +5,15 @@ module MOVW-R16-IMM16 imports X86-CONFIGURATION rule - execinstr (movw Imm16:Imm, R2:R16, .Operands) => . + execinstr (movw Imm16:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), handleImmediateWithSignExtend(Imm16, 16, 16)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), Imm16) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/mpsadbw_xmm_xmm_imm8.k b/semantics/immediateInstructions/mpsadbw_xmm_xmm_imm8.k index 78725d1de..da0f7af7e 100644 --- a/semantics/immediateInstructions/mpsadbw_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/mpsadbw_xmm_xmm_imm8.k @@ -4,43 +4,44 @@ module MPSADBW-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (mpsadbw Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => + execinstr (mpsadbw Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => execinstr (mpsadbw selectSliceMPSAD(getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 7 , 0 ), + extractMInt(Imm8, 6, 8), 7 , 0 ), selectSliceMPSAD(getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 15, 8 ), + extractMInt(Imm8, 6, 8), 15, 8 ), selectSliceMPSAD(getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 23, 16), + extractMInt(Imm8, 6, 8), 23, 16), selectSliceMPSAD(getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 31, 24), + extractMInt(Imm8, 6, 8), 31, 24), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 7 , 0), + extractMInt(Imm8, 5, 6), 7 , 0), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 15, 8), + extractMInt(Imm8, 5, 6), 15, 8), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 23, 16), + extractMInt(Imm8, 5, 6), 23, 16), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 31, 24), + extractMInt(Imm8, 5, 6), 31, 24), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 39, 32), + extractMInt(Imm8, 5, 6), 39, 32), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 47, 40), + extractMInt(Imm8, 5, 6), 47, 40), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 55, 48), + extractMInt(Imm8, 5, 6), 55, 48), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 63, 56), + extractMInt(Imm8, 5, 6), 63, 56), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 71, 64), + extractMInt(Imm8, 5, 6), 71, 64), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 79, 72), + extractMInt(Imm8, 5, 6), 79, 72), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 87, 80), + extractMInt(Imm8, 5, 6), 87, 80), R3:Xmm, .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (mpsadbw diff --git a/semantics/immediateInstructions/orb_al_imm8.k b/semantics/immediateInstructions/orb_al_imm8.k index 3f6603153..c0010c1f5 100644 --- a/semantics/immediateInstructions/orb_al_imm8.k +++ b/semantics/immediateInstructions/orb_al_imm8.k @@ -5,26 +5,27 @@ module ORB-AL-IMM8 imports X86-CONFIGURATION rule - execinstr (orb Imm8:Imm, %al, .Operands) => . + execinstr (orb Imm8:MInt, %al, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 56), orMInt( extractMInt( getParentValue(%rax, RSMap), 56, 64), handleImmediateWithSignExtend(Imm8, 8, 8))) +"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 56), orMInt( extractMInt( getParentValue(%rax, RSMap), 56, 64), Imm8)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 56, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 56, 64), Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> orMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/orb_r8_imm8.k b/semantics/immediateInstructions/orb_r8_imm8.k index 37563bc7a..189af7d4b 100644 --- a/semantics/immediateInstructions/orb_r8_imm8.k +++ b/semantics/immediateInstructions/orb_r8_imm8.k @@ -5,26 +5,27 @@ module ORB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (orb Imm8:Imm, R2:R8, .Operands) => . + execinstr (orb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), orMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), handleImmediateWithSignExtend(Imm8, 8, 8))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), orMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), Imm8)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/orb_rh_imm8.k b/semantics/immediateInstructions/orb_rh_imm8.k index 627755af4..2a7e7d6d8 100644 --- a/semantics/immediateInstructions/orb_rh_imm8.k +++ b/semantics/immediateInstructions/orb_rh_imm8.k @@ -5,26 +5,27 @@ module ORB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (orb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (orb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), orMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), handleImmediateWithSignExtend(Imm8, 8, 8))), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), orMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), Imm8)), extractMInt( getParentValue(R2, RSMap), 56, 64)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 55, 56), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 54, 55), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 53, 54), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 52, 53), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 51, 52), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 50, 51), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 49, 50), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 55, 56), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 54, 55), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 53, 54), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 52, 53), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 51, 52), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 50, 51), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 49, 50), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/orl_eax_imm32.k b/semantics/immediateInstructions/orl_eax_imm32.k index d6f2b62e9..3eb01bf70 100644 --- a/semantics/immediateInstructions/orl_eax_imm32.k +++ b/semantics/immediateInstructions/orl_eax_imm32.k @@ -5,26 +5,27 @@ module ORL-EAX-IMM32 imports X86-CONFIGURATION rule - execinstr (orl Imm32:Imm, %eax, .Operands) => . + execinstr (orl Imm32:MInt, %eax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( mi(32, 0), orMInt( extractMInt( getParentValue(%rax, RSMap), 32, 64), handleImmediateWithSignExtend(Imm32, 32, 32))) +"RAX" |-> concatenateMInt( mi(32, 0), orMInt( extractMInt( getParentValue(%rax, RSMap), 32, 64), Imm32)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 32, 64), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 32, 64), Imm32), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)) +"SF" |-> orMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), extractMInt( Imm32, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/orl_r32_imm32.k b/semantics/immediateInstructions/orl_r32_imm32.k index c087060b6..37bf020a2 100644 --- a/semantics/immediateInstructions/orl_r32_imm32.k +++ b/semantics/immediateInstructions/orl_r32_imm32.k @@ -5,26 +5,27 @@ module ORL-R32-IMM32 imports X86-CONFIGURATION rule - execinstr (orl Imm32:Imm, R2:R32, .Operands) => . + execinstr (orl Imm32:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), orMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), handleImmediateWithSignExtend(Imm32, 32, 32))) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), orMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), Imm32)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), Imm32), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)) +"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), extractMInt( Imm32, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/orl_r32_imm8.k b/semantics/immediateInstructions/orl_r32_imm8.k index a06966384..51c069103 100644 --- a/semantics/immediateInstructions/orl_r32_imm8.k +++ b/semantics/immediateInstructions/orl_r32_imm8.k @@ -5,26 +5,27 @@ module ORL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (orl Imm8:Imm, R2:R32, .Operands) => . + execinstr (orl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), orMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), orMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, svalueMInt(Imm8)))) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, svalueMInt(Imm8))), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/orq_r64_imm32.k b/semantics/immediateInstructions/orq_r64_imm32.k index 127bcf860..e5418cf62 100644 --- a/semantics/immediateInstructions/orq_r64_imm32.k +++ b/semantics/immediateInstructions/orq_r64_imm32.k @@ -5,26 +5,27 @@ module ORQ-R64-IMM32 imports X86-CONFIGURATION rule - execinstr (orq Imm32:Imm, R2:R64, .Operands) => . + execinstr (orq Imm32:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> orMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) +convToRegKeys(R2) |-> orMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(Imm32))) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(Imm32))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)) +"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/orq_r64_imm8.k b/semantics/immediateInstructions/orq_r64_imm8.k index 2aa63623d..c086017f2 100644 --- a/semantics/immediateInstructions/orq_r64_imm8.k +++ b/semantics/immediateInstructions/orq_r64_imm8.k @@ -5,26 +5,27 @@ module ORQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (orq Imm8:Imm, R2:R64, .Operands) => . + execinstr (orq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> orMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) +convToRegKeys(R2) |-> orMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(Imm8))) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(Imm8))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/orq_rax_imm32.k b/semantics/immediateInstructions/orq_rax_imm32.k index 3dc8c82bb..e8759e7d4 100644 --- a/semantics/immediateInstructions/orq_rax_imm32.k +++ b/semantics/immediateInstructions/orq_rax_imm32.k @@ -5,26 +5,27 @@ module ORQ-RAX-IMM32 imports X86-CONFIGURATION rule - execinstr (orq Imm32:Imm, %rax, .Operands) => . + execinstr (orq Imm32:MInt, %rax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> orMInt( getParentValue(%rax, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) +"RAX" |-> orMInt( getParentValue(%rax, RSMap), mi(64, svalueMInt(Imm32))) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( getParentValue(%rax, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( getParentValue(%rax, RSMap), mi(64, svalueMInt(Imm32))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)) +"SF" |-> orMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/orw_ax_imm16.k b/semantics/immediateInstructions/orw_ax_imm16.k index 9be5a55b0..1b93b5fcd 100644 --- a/semantics/immediateInstructions/orw_ax_imm16.k +++ b/semantics/immediateInstructions/orw_ax_imm16.k @@ -5,26 +5,27 @@ module ORW-AX-IMM16 imports X86-CONFIGURATION rule - execinstr (orw Imm16:Imm, %ax, .Operands) => . + execinstr (orw Imm16:MInt, %ax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 48), orMInt( extractMInt( getParentValue(%rax, RSMap), 48, 64), handleImmediateWithSignExtend(Imm16, 16, 16))) +"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 48), orMInt( extractMInt( getParentValue(%rax, RSMap), 48, 64), Imm16)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 15, 16)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 14, 15)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 13, 14)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 12, 13)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 10, 11)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 9, 10)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm16, 15, 16)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm16, 14, 15)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm16, 13, 14)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm16, 12, 13)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm16, 11, 12)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm16, 10, 11)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm16, 9, 10)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm16, 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 48, 64), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 48, 64), Imm16), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)) +"SF" |-> orMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), extractMInt( Imm16, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/orw_r16_imm16.k b/semantics/immediateInstructions/orw_r16_imm16.k index 69c0d0b5c..415add486 100644 --- a/semantics/immediateInstructions/orw_r16_imm16.k +++ b/semantics/immediateInstructions/orw_r16_imm16.k @@ -5,26 +5,27 @@ module ORW-R16-IMM16 imports X86-CONFIGURATION rule - execinstr (orw Imm16:Imm, R2:R16, .Operands) => . + execinstr (orw Imm16:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), orMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), handleImmediateWithSignExtend(Imm16, 16, 16))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), orMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), Imm16)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 15, 16)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 14, 15)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 13, 14)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 12, 13)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 10, 11)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 9, 10)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm16, 15, 16)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm16, 14, 15)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm16, 13, 14)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm16, 12, 13)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm16, 11, 12)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm16, 10, 11)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm16, 9, 10)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm16, 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), Imm16), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)) +"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( Imm16, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/orw_r16_imm8.k b/semantics/immediateInstructions/orw_r16_imm8.k index 6ce996862..5c16b7b30 100644 --- a/semantics/immediateInstructions/orw_r16_imm8.k +++ b/semantics/immediateInstructions/orw_r16_imm8.k @@ -5,26 +5,27 @@ module ORW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (orw Imm8:Imm, R2:R16, .Operands) => . + execinstr (orw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), orMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), orMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(16, svalueMInt(Imm8)))) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(16, svalueMInt(Imm8))), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/palignr_xmm_xmm_imm8.k b/semantics/immediateInstructions/palignr_xmm_xmm_imm8.k index b28b23207..471323eac 100644 --- a/semantics/immediateInstructions/palignr_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/palignr_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module PALIGNR-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (palignr Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (palignr Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), extractMInt( getParentValue(R2, RSMap), 128, 256)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), uvalueMInt(mi(256, 3))))), 128, 256)) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), extractMInt( getParentValue(R2, RSMap), 128, 256)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), Imm8), uvalueMInt(mi(256, 3))))), 128, 256)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pblendw_xmm_xmm_imm8.k b/semantics/immediateInstructions/pblendw_xmm_xmm_imm8.k index f4bdb29d0..a6b216eb6 100644 --- a/semantics/immediateInstructions/pblendw_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/pblendw_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module PBLENDW-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (pblendw Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (pblendw Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 144) #else extractMInt( getParentValue(R2, RSMap), 128, 144) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 144, 160) #else extractMInt( getParentValue(R2, RSMap), 144, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 176) #else extractMInt( getParentValue(R2, RSMap), 160, 176) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 176, 192) #else extractMInt( getParentValue(R2, RSMap), 176, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 208) #else extractMInt( getParentValue(R2, RSMap), 192, 208) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 208, 224) #else extractMInt( getParentValue(R2, RSMap), 208, 224) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 240) #else extractMInt( getParentValue(R2, RSMap), 224, 240) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 240, 256) #else extractMInt( getParentValue(R2, RSMap), 240, 256) #fi))))))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 144) #else extractMInt( getParentValue(R2, RSMap), 128, 144) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 144, 160) #else extractMInt( getParentValue(R2, RSMap), 144, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 176) #else extractMInt( getParentValue(R2, RSMap), 160, 176) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 176, 192) #else extractMInt( getParentValue(R2, RSMap), 176, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 208) #else extractMInt( getParentValue(R2, RSMap), 192, 208) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 208, 224) #else extractMInt( getParentValue(R2, RSMap), 208, 224) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 240) #else extractMInt( getParentValue(R2, RSMap), 224, 240) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 240, 256) #else extractMInt( getParentValue(R2, RSMap), 240, 256) #fi))))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pclmulqdq_xmm_xmm_imm8.k b/semantics/immediateInstructions/pclmulqdq_xmm_xmm_imm8.k index 300dac9b0..0853b148d 100644 --- a/semantics/immediateInstructions/pclmulqdq_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/pclmulqdq_xmm_xmm_imm8.k @@ -49,15 +49,14 @@ module PCLMULQDQ-XMM-XMM-IMM8 TEMP2←SRC2 [127:64]; */ rule - execinstr (pclmulqdq Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => + execinstr (pclmulqdq Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => execinstr(pclmulqdq - selectSlice(getRegisterValue(R3, RSMap), handleImmediateWithSignExtend(Imm8, - 8, 8), 7, 64, 0), - selectSlice(getRegisterValue(R2, RSMap), handleImmediateWithSignExtend(Imm8, - 8, 8), 3, 64, 0), R3 + selectSlice(getRegisterValue(R3, RSMap), Imm8, 7, 64, 0), + selectSlice(getRegisterValue(R2, RSMap), Imm8, 3, 64, 0), R3 , .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (pclmulqdq TEMP1:MInt, TEMP2:MInt, R3:Xmm, .Operands) => diff --git a/semantics/immediateInstructions/pcmpestri_xmm_xmm_imm8.k b/semantics/immediateInstructions/pcmpestri_xmm_xmm_imm8.k index f5240fa90..e7f4be1ca 100644 --- a/semantics/immediateInstructions/pcmpestri_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/pcmpestri_xmm_xmm_imm8.k @@ -6,16 +6,17 @@ module PCMPESTRI-XMM-XMM-IMM8 // Find Limit Index rule - execinstr (pcmpestri Imm8:Imm, Xmm2:Xmm, Xmm1:Xmm, .Operands) => + execinstr (pcmpestri Imm8:MInt, Xmm2:Xmm, Xmm1:Xmm, .Operands) => execinstr (pcmpestri - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, getRegisterValue(Xmm2, RSMap), getRegisterValue(Xmm1, RSMap), - findLimitIndexE(getRegisterValue(Xmm2, RSMap), getRegisterValue(%rdx, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexE(getRegisterValue(Xmm2, RSMap), getRegisterValue(%rdx, RSMap), Imm8), + findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // pcmpestri 8'1 , 128'0 , 128'0 , 8'1 , 8'1 , 8'8 , 1'0 , 8'1 , .Operands diff --git a/semantics/immediateInstructions/pcmpestrm_xmm_xmm_imm8.k b/semantics/immediateInstructions/pcmpestrm_xmm_xmm_imm8.k index b3ece31d9..71661068d 100644 --- a/semantics/immediateInstructions/pcmpestrm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/pcmpestrm_xmm_xmm_imm8.k @@ -6,16 +6,17 @@ module PCMPESTRM-XMM-XMM-IMM8 // Find Limit Index rule - execinstr (pcmpestrm Imm8:Imm, Xmm2:Xmm, Xmm1:Xmm, .Operands) => + execinstr (pcmpestrm Imm8:MInt, Xmm2:Xmm, Xmm1:Xmm, .Operands) => execinstr (pcmpestrm - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, getRegisterValue(Xmm2, RSMap), getRegisterValue(Xmm1, RSMap), - findLimitIndexE(getRegisterValue(Xmm2, RSMap), getRegisterValue(%rdx, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexE(getRegisterValue(Xmm2, RSMap), getRegisterValue(%rdx, RSMap), Imm8), + findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // Find data size and interpretation rule diff --git a/semantics/immediateInstructions/pcmpistri_xmm_xmm_imm8.k b/semantics/immediateInstructions/pcmpistri_xmm_xmm_imm8.k index ef5b1777b..5e8630969 100644 --- a/semantics/immediateInstructions/pcmpistri_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/pcmpistri_xmm_xmm_imm8.k @@ -6,16 +6,17 @@ module PCMPISTRI-XMM-XMM-IMM8 // Find Limit Index rule - execinstr (pcmpistri Imm8:Imm, Xmm2:Xmm, Xmm1:Xmm, .Operands) => + execinstr (pcmpistri Imm8:MInt, Xmm2:Xmm, Xmm1:Xmm, .Operands) => execinstr (pcmpistri - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, getRegisterValue(Xmm2, RSMap), getRegisterValue(Xmm1, RSMap), - findLimitIndexI(getRegisterValue(Xmm2, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexI(getRegisterValue(Xmm1, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexI(getRegisterValue(Xmm2, RSMap), Imm8), + findLimitIndexI(getRegisterValue(Xmm1, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // Find data size and interpretation rule diff --git a/semantics/immediateInstructions/pcmpistrm_xmm_xmm_imm8.k b/semantics/immediateInstructions/pcmpistrm_xmm_xmm_imm8.k index 83616c053..5f54ea863 100644 --- a/semantics/immediateInstructions/pcmpistrm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/pcmpistrm_xmm_xmm_imm8.k @@ -6,16 +6,17 @@ module PCMPISTRM-XMM-XMM-IMM8 // Find Limit Index rule - execinstr (pcmpistrm Imm8:Imm, Xmm2:Xmm, Xmm1:Xmm, .Operands) => + execinstr (pcmpistrm Imm8:MInt, Xmm2:Xmm, Xmm1:Xmm, .Operands) => execinstr (pcmpistrm - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, getRegisterValue(Xmm2, RSMap), getRegisterValue(Xmm1, RSMap), - findLimitIndexI(getRegisterValue(Xmm2, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexI(getRegisterValue(Xmm1, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexI(getRegisterValue(Xmm2, RSMap), Imm8), + findLimitIndexI(getRegisterValue(Xmm1, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // Find data size and interpretation rule diff --git a/semantics/immediateInstructions/pextrb_r32_xmm_imm8.k b/semantics/immediateInstructions/pextrb_r32_xmm_imm8.k index fcc0aac02..1e4e7e063 100644 --- a/semantics/immediateInstructions/pextrb_r32_xmm_imm8.k +++ b/semantics/immediateInstructions/pextrb_r32_xmm_imm8.k @@ -5,14 +5,15 @@ module PEXTRB-R32-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (pextrb Imm8:Imm, R2:Xmm, R3:R32, .Operands) => . + execinstr (pextrb Imm8:MInt, R2:Xmm, R3:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(56, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3))))), 120, 128)) +convToRegKeys(R3) |-> concatenateMInt( mi(56, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3))))), 120, 128)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pextrb_r64_xmm_imm8.k b/semantics/immediateInstructions/pextrb_r64_xmm_imm8.k index c5a5d0f72..884104a0b 100644 --- a/semantics/immediateInstructions/pextrb_r64_xmm_imm8.k +++ b/semantics/immediateInstructions/pextrb_r64_xmm_imm8.k @@ -5,14 +5,15 @@ module PEXTRB-R64-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (pextrb Imm8:Imm, R2:Xmm, R3:R64, .Operands) => . + execinstr (pextrb Imm8:MInt, R2:Xmm, R3:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(56, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3))))), 120, 128)) +convToRegKeys(R3) |-> concatenateMInt( mi(56, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3))))), 120, 128)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pextrd_r32_xmm_imm8.k b/semantics/immediateInstructions/pextrd_r32_xmm_imm8.k index d955bd640..95448d3b5 100644 --- a/semantics/immediateInstructions/pextrd_r32_xmm_imm8.k +++ b/semantics/immediateInstructions/pextrd_r32_xmm_imm8.k @@ -5,14 +5,15 @@ module PEXTRD-R32-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (pextrd Imm8:Imm, R2:Xmm, R3:R32, .Operands) => . + execinstr (pextrd Imm8:MInt, R2:Xmm, R3:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128)) +convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pextrq_r64_xmm_imm8.k b/semantics/immediateInstructions/pextrq_r64_xmm_imm8.k index 93a1a246b..9e2f02047 100644 --- a/semantics/immediateInstructions/pextrq_r64_xmm_imm8.k +++ b/semantics/immediateInstructions/pextrq_r64_xmm_imm8.k @@ -5,14 +5,15 @@ module PEXTRQ-R64-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (pextrq Imm8:Imm, R2:Xmm, R3:R64, .Operands) => . + execinstr (pextrq Imm8:MInt, R2:Xmm, R3:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6))))), 64, 128) +convToRegKeys(R3) |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6))))), 64, 128) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pextrw_r32_xmm_imm8.k b/semantics/immediateInstructions/pextrw_r32_xmm_imm8.k index 47edbf2b0..a8af52190 100644 --- a/semantics/immediateInstructions/pextrw_r32_xmm_imm8.k +++ b/semantics/immediateInstructions/pextrw_r32_xmm_imm8.k @@ -5,14 +5,15 @@ module PEXTRW-R32-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (pextrw Imm8:Imm, R2:Xmm, R3:R32, .Operands) => . + execinstr (pextrw Imm8:MInt, R2:Xmm, R3:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(48, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4))))), 112, 128)) +convToRegKeys(R3) |-> concatenateMInt( mi(48, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4))))), 112, 128)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pextrw_r64_xmm_imm8.k b/semantics/immediateInstructions/pextrw_r64_xmm_imm8.k index 7d1b9d840..b4ad0a368 100644 --- a/semantics/immediateInstructions/pextrw_r64_xmm_imm8.k +++ b/semantics/immediateInstructions/pextrw_r64_xmm_imm8.k @@ -5,14 +5,15 @@ module PEXTRW-R64-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (pextrw Imm8:Imm, R2:Xmm, R3:R64, .Operands) => . + execinstr (pextrw Imm8:MInt, R2:Xmm, R3:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(48, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4))))), 112, 128)) +convToRegKeys(R3) |-> concatenateMInt( mi(48, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4))))), 112, 128)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pinsrb_xmm_r32_imm8.k b/semantics/immediateInstructions/pinsrb_xmm_r32_imm8.k index bda1687b8..53c3ef516 100644 --- a/semantics/immediateInstructions/pinsrb_xmm_r32_imm8.k +++ b/semantics/immediateInstructions/pinsrb_xmm_r32_imm8.k @@ -5,14 +5,15 @@ module PINSRB-XMM-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (pinsrb Imm8:Imm, R2:R32, R3:Xmm, .Operands) => . + execinstr (pinsrb Imm8:MInt, R2:R32, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3))))), shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3)))))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3))))), shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pinsrd_xmm_r32_imm8.k b/semantics/immediateInstructions/pinsrd_xmm_r32_imm8.k index 8a3be75ba..30f9332e3 100644 --- a/semantics/immediateInstructions/pinsrd_xmm_r32_imm8.k +++ b/semantics/immediateInstructions/pinsrd_xmm_r32_imm8.k @@ -5,14 +5,15 @@ module PINSRD-XMM-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (pinsrd Imm8:Imm, R2:R32, R3:Xmm, .Operands) => . + execinstr (pinsrd Imm8:MInt, R2:R32, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5)))))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pinsrq_xmm_r64_imm8.k b/semantics/immediateInstructions/pinsrq_xmm_r64_imm8.k index 2d4809e9f..a29d34cb3 100644 --- a/semantics/immediateInstructions/pinsrq_xmm_r64_imm8.k +++ b/semantics/immediateInstructions/pinsrq_xmm_r64_imm8.k @@ -5,13 +5,14 @@ module PINSRQ-XMM-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (pinsrq Imm8:Imm, R2:R64, R3:Xmm .Operands) => . + execinstr (pinsrq Imm8:MInt, R2:R64, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(64, 0), getParentValue(R2, RSMap)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6))))), shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6)))))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(64, 0), getParentValue(R2, RSMap)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6))))), shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pinsrw_xmm_r32_imm8.k b/semantics/immediateInstructions/pinsrw_xmm_r32_imm8.k index 272fdcb42..ca70f970d 100644 --- a/semantics/immediateInstructions/pinsrw_xmm_r32_imm8.k +++ b/semantics/immediateInstructions/pinsrw_xmm_r32_imm8.k @@ -5,14 +5,15 @@ module PINSRW-XMM-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (pinsrw Imm8:Imm, R2:R32, R3:Xmm, .Operands) => . + execinstr (pinsrw Imm8:MInt, R2:R32, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4))))), shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4)))))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4))))), shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pshufd_xmm_xmm_imm8.k b/semantics/immediateInstructions/pshufd_xmm_xmm_imm8.k index a554cd2b7..43d1089c6 100644 --- a/semantics/immediateInstructions/pshufd_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/pshufd_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module PSHUFD-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (pshufd Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (pshufd Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pshufhw_xmm_xmm_imm8.k b/semantics/immediateInstructions/pshufhw_xmm_xmm_imm8.k index 978de61d5..3e0456fe3 100644 --- a/semantics/immediateInstructions/pshufhw_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/pshufhw_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module PSHUFHW-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (pshufhw Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (pshufhw Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 4))))), 48, 64), extractMInt( getParentValue(R2, RSMap), 192, 256)))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 4))))), 48, 64), extractMInt( getParentValue(R2, RSMap), 192, 256)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pshuflw_xmm_xmm_imm8.k b/semantics/immediateInstructions/pshuflw_xmm_xmm_imm8.k index 8c53a8222..09abf1203 100644 --- a/semantics/immediateInstructions/pshuflw_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/pshuflw_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module PSHUFLW-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (pshuflw Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (pshuflw Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 4))))), 112, 128), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 4))))), 112, 128)))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 4))))), 112, 128), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 4))))), 112, 128)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pslld_xmm_imm8.k b/semantics/immediateInstructions/pslld_xmm_imm8.k index 2bde9c34b..1195b4be7 100644 --- a/semantics/immediateInstructions/pslld_xmm_imm8.k +++ b/semantics/immediateInstructions/pslld_xmm_imm8.k @@ -5,14 +5,15 @@ module PSLLD-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (pslld Imm8:Imm, R2:Xmm, .Operands) => . + execinstr (pslld Imm8:MInt, R2:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(128, 0) #else concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8))))))) #fi)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(128, 0) #else concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt(concatenateMInt( mi(24, 0), Imm8)))))) #fi)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pslldq_xmm_imm8.k b/semantics/immediateInstructions/pslldq_xmm_imm8.k index 6f44cfd8f..c365871eb 100644 --- a/semantics/immediateInstructions/pslldq_xmm_imm8.k +++ b/semantics/immediateInstructions/pslldq_xmm_imm8.k @@ -5,14 +5,15 @@ module PSLLDQ-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (pslldq Imm8:Imm, R2:Xmm, .Operands) => . + execinstr (pslldq Imm8:MInt, R2:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), uvalueMInt(mi(128, 3)))))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( Imm8, mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), Imm8) #fi), uvalueMInt(mi(128, 3)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/psllq_xmm_imm8.k b/semantics/immediateInstructions/psllq_xmm_imm8.k index ae6725194..9dce7d6cf 100644 --- a/semantics/immediateInstructions/psllq_xmm_imm8.k +++ b/semantics/immediateInstructions/psllq_xmm_imm8.k @@ -5,14 +5,15 @@ module PSLLQ-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (psllq Imm8:Imm, R2:Xmm, .Operands) => . + execinstr (psllq Imm8:MInt, R2:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 63)) #then mi(128, 0) #else concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 256), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8))))) #fi)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 63)) #then mi(128, 0) #else concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), uvalueMInt(concatenateMInt( mi(56, 0), Imm8))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 256), uvalueMInt(concatenateMInt( mi(56, 0), Imm8)))) #fi)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/psllw_xmm_imm8.k b/semantics/immediateInstructions/psllw_xmm_imm8.k index b233d1eff..dc461e5e1 100644 --- a/semantics/immediateInstructions/psllw_xmm_imm8.k +++ b/semantics/immediateInstructions/psllw_xmm_imm8.k @@ -5,14 +5,15 @@ module PSLLW-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (psllw Imm8:Imm, R2:Xmm, .Operands) => . + execinstr (psllw Imm8:MInt, R2:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(128, 0) #else concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8))))))))))) #fi)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(128, 0) #else concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt(concatenateMInt( mi(8, 0), Imm8)))))))))) #fi)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/psrad_xmm_imm8.k b/semantics/immediateInstructions/psrad_xmm_imm8.k index d90474807..3f1defe46 100644 --- a/semantics/immediateInstructions/psrad_xmm_imm8.k +++ b/semantics/immediateInstructions/psrad_xmm_imm8.k @@ -5,14 +5,15 @@ module PSRAD-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (psrad Imm8:Imm, R2:Xmm, .Operands) => . + execinstr (psrad Imm8:MInt, R2:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))))))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi))), aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/psraw_xmm_imm8.k b/semantics/immediateInstructions/psraw_xmm_imm8.k index 679082020..f9529c0ed 100644 --- a/semantics/immediateInstructions/psraw_xmm_imm8.k +++ b/semantics/immediateInstructions/psraw_xmm_imm8.k @@ -5,14 +5,15 @@ module PSRAW-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (psraw Imm8:Imm, R2:Xmm, .Operands) => . + execinstr (psraw Imm8:MInt, R2:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))))))))))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))))))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/psrld_xmm_imm8.k b/semantics/immediateInstructions/psrld_xmm_imm8.k index 776ad7486..3580b50ed 100644 --- a/semantics/immediateInstructions/psrld_xmm_imm8.k +++ b/semantics/immediateInstructions/psrld_xmm_imm8.k @@ -5,14 +5,15 @@ module PSRLD-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (psrld Imm8:Imm, R2:Xmm, .Operands) => . + execinstr (psrld Imm8:MInt, R2:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(128, 0) #else concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8))))))) #fi)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(128, 0) #else concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt(concatenateMInt( mi(24, 0), Imm8)))))) #fi)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/psrldq_xmm_imm8.k b/semantics/immediateInstructions/psrldq_xmm_imm8.k index 9bcb50167..f08003628 100644 --- a/semantics/immediateInstructions/psrldq_xmm_imm8.k +++ b/semantics/immediateInstructions/psrldq_xmm_imm8.k @@ -5,14 +5,15 @@ module PSRLDQ-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (psrldq Imm8:Imm, R2:Xmm, .Operands) => . + execinstr (psrldq Imm8:MInt, R2:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), uvalueMInt(mi(128, 3)))))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( Imm8, mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), Imm8) #fi), uvalueMInt(mi(128, 3)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/psrlq_xmm_imm8.k b/semantics/immediateInstructions/psrlq_xmm_imm8.k index 978a3fccf..023b4a50e 100644 --- a/semantics/immediateInstructions/psrlq_xmm_imm8.k +++ b/semantics/immediateInstructions/psrlq_xmm_imm8.k @@ -5,14 +5,15 @@ module PSRLQ-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (psrlq Imm8:Imm, R2:Xmm, .Operands) => . + execinstr (psrlq Imm8:MInt, R2:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 63)) #then mi(128, 0) #else concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 256), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8))))) #fi)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 63)) #then mi(128, 0) #else concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), uvalueMInt(concatenateMInt( mi(56, 0), Imm8))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 256), uvalueMInt(concatenateMInt( mi(56, 0), Imm8)))) #fi)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/psrlw_xmm_imm8.k b/semantics/immediateInstructions/psrlw_xmm_imm8.k index 6886c12b8..67ccc89a2 100644 --- a/semantics/immediateInstructions/psrlw_xmm_imm8.k +++ b/semantics/immediateInstructions/psrlw_xmm_imm8.k @@ -5,14 +5,15 @@ module PSRLW-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (psrlw Imm8:Imm, R2:Xmm, .Operands) => . + execinstr (psrlw Imm8:MInt, R2:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(128, 0) #else concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8))))))))))) #fi)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(128, 0) #else concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt(concatenateMInt( mi(8, 0), Imm8)))))))))) #fi)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pushq_imm32.k b/semantics/immediateInstructions/pushq_imm32.k index 143e8b115..08b4e40fd 100644 --- a/semantics/immediateInstructions/pushq_imm32.k +++ b/semantics/immediateInstructions/pushq_imm32.k @@ -11,12 +11,13 @@ module PUSHQ-IMM32 imports X86-CONFIGURATION rule - execinstr (pushq Imm32:Imm, .Operands) => + execinstr (pushq Imm32:MInt, .Operands) => storeToMemory( - handleImmediateWithSignExtend(Imm32, 32, 64), + signExtend(Imm32, 64), subMInt(getRegisterValue(%rsp, RSMap), mi(64, 8)), 64) ~> decRSPInBytes(8) ... RSMap + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/rclb_r8_imm8.k b/semantics/immediateInstructions/rclb_r8_imm8.k index 5913211ac..aeefc7462 100644 --- a/semantics/immediateInstructions/rclb_r8_imm8.k +++ b/semantics/immediateInstructions/rclb_r8_imm8.k @@ -5,18 +5,19 @@ module RCLB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (rclb Imm8:Imm, R2:R8, .Operands) => . + execinstr (rclb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 1, 9)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 1, 9)) -"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 0, 1) +"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rclb_rh_imm8.k b/semantics/immediateInstructions/rclb_rh_imm8.k index b2c83cd3a..e7e153a83 100644 --- a/semantics/immediateInstructions/rclb_rh_imm8.k +++ b/semantics/immediateInstructions/rclb_rh_imm8.k @@ -5,18 +5,19 @@ module RCLB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (rclb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (rclb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) -"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 0, 1) +"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rcll_r32_imm8.k b/semantics/immediateInstructions/rcll_r32_imm8.k index 55e61300a..3101cb06a 100644 --- a/semantics/immediateInstructions/rcll_r32_imm8.k +++ b/semantics/immediateInstructions/rcll_r32_imm8.k @@ -5,18 +5,19 @@ module RCLL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (rcll Imm8:Imm, R2:R32, .Operands) => . + execinstr (rcll Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 1, 33)) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 1, 33)) -"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 0, 1) +"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rclq_r64_imm8.k b/semantics/immediateInstructions/rclq_r64_imm8.k index 6db2c8413..13acfe879 100644 --- a/semantics/immediateInstructions/rclq_r64_imm8.k +++ b/semantics/immediateInstructions/rclq_r64_imm8.k @@ -5,18 +5,19 @@ module RCLQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (rclq Imm8:Imm, R2:R64, .Operands) => . + execinstr (rclq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 1, 65) +convToRegKeys(R2) |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 1, 65) -"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 0, 1) +"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rclw_r16_imm8.k b/semantics/immediateInstructions/rclw_r16_imm8.k index 9e404c89b..e95041838 100644 --- a/semantics/immediateInstructions/rclw_r16_imm8.k +++ b/semantics/immediateInstructions/rclw_r16_imm8.k @@ -5,18 +5,19 @@ module RCLW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (rclw Imm8:Imm, R2:R16, .Operands) => . + execinstr (rclw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 1, 17)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 1, 17)) -"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 0, 1) +"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rcrb_r8_imm8.k b/semantics/immediateInstructions/rcrb_r8_imm8.k index 1c33bd062..8e92aec8e 100644 --- a/semantics/immediateInstructions/rcrb_r8_imm8.k +++ b/semantics/immediateInstructions/rcrb_r8_imm8.k @@ -5,18 +5,19 @@ module RCRB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (rcrb Imm8:Imm, R2:R8, .Operands) => . + execinstr (rcrb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 1, 9)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 1, 9)) -"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 0, 1) +"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rcrb_rh_imm8.k b/semantics/immediateInstructions/rcrb_rh_imm8.k index a85daf27c..e72b8197c 100644 --- a/semantics/immediateInstructions/rcrb_rh_imm8.k +++ b/semantics/immediateInstructions/rcrb_rh_imm8.k @@ -5,18 +5,19 @@ module RCRB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (rcrb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (rcrb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) -"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 0, 1) +"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rcrl_r32_imm8.k b/semantics/immediateInstructions/rcrl_r32_imm8.k index 9679a672b..f97273ee8 100644 --- a/semantics/immediateInstructions/rcrl_r32_imm8.k +++ b/semantics/immediateInstructions/rcrl_r32_imm8.k @@ -5,18 +5,19 @@ module RCRL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (rcrl Imm8:Imm, R2:R32, .Operands) => . + execinstr (rcrl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 1, 33)) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 1, 33)) -"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 0, 1) +"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rcrq_r64_imm8.k b/semantics/immediateInstructions/rcrq_r64_imm8.k index 07b09df9a..432f62fde 100644 --- a/semantics/immediateInstructions/rcrq_r64_imm8.k +++ b/semantics/immediateInstructions/rcrq_r64_imm8.k @@ -5,18 +5,19 @@ module RCRQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (rcrq Imm8:Imm, R2:R64, .Operands) => . + execinstr (rcrq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 1, 65) +convToRegKeys(R2) |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 1, 65) -"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 0, 1) +"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rcrw_r16_imm8.k b/semantics/immediateInstructions/rcrw_r16_imm8.k index f55eb46d2..b245ac699 100644 --- a/semantics/immediateInstructions/rcrw_r16_imm8.k +++ b/semantics/immediateInstructions/rcrw_r16_imm8.k @@ -5,18 +5,19 @@ module RCRW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (rcrw Imm8:Imm, R2:R16, .Operands) => . + execinstr (rcrw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 1, 17)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 1, 17)) -"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 0, 1) +"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rolb_r8_imm8.k b/semantics/immediateInstructions/rolb_r8_imm8.k index a7f9e8fef..d697829d7 100644 --- a/semantics/immediateInstructions/rolb_r8_imm8.k +++ b/semantics/immediateInstructions/rolb_r8_imm8.k @@ -5,18 +5,19 @@ module ROLB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (rolb Imm8:Imm, R2:R8, .Operands) => . + execinstr (rolb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), rol( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), rol( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( Imm8, mi(8, 31)))) -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 7, 8), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( Imm8, mi(8, 31))), 7, 8), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 7, 8), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( Imm8, mi(8, 31))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( Imm8, mi(8, 31))), 7, 8), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rolb_rh_imm8.k b/semantics/immediateInstructions/rolb_rh_imm8.k index 8c0a498c8..ccbadbef3 100644 --- a/semantics/immediateInstructions/rolb_rh_imm8.k +++ b/semantics/immediateInstructions/rolb_rh_imm8.k @@ -5,18 +5,19 @@ module ROLB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (rolb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (rolb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), rol( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), rol( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( Imm8, mi(8, 31)))), extractMInt( getParentValue(R2, RSMap), 56, 64)) -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 7, 8), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( Imm8, mi(8, 31))), 7, 8), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 7, 8), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( Imm8, mi(8, 31))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( Imm8, mi(8, 31))), 7, 8), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/roll_r32_imm8.k b/semantics/immediateInstructions/roll_r32_imm8.k index c296aea97..8fef9cbdf 100644 --- a/semantics/immediateInstructions/roll_r32_imm8.k +++ b/semantics/immediateInstructions/roll_r32_imm8.k @@ -5,18 +5,19 @@ module ROLL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (roll Imm8:Imm, R2:R32, .Operands) => . + execinstr (roll Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), rol( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), rol( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31))))) -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 31, 32), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31)))), 31, 32), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 31, 32), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31)))), 31, 32), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rolq_r64_imm8.k b/semantics/immediateInstructions/rolq_r64_imm8.k index 429dd98c4..2017e2538 100644 --- a/semantics/immediateInstructions/rolq_r64_imm8.k +++ b/semantics/immediateInstructions/rolq_r64_imm8.k @@ -5,18 +5,19 @@ module ROLQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (rolq Imm8:Imm, R2:R64, .Operands) => . + execinstr (rolq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> rol( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))) +convToRegKeys(R2) |-> rol( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))) -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( rol( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))), 63, 64), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( rol( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))), 63, 64), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))), 63, 64), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))), 63, 64), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rolw_r16_imm8.k b/semantics/immediateInstructions/rolw_r16_imm8.k index 609fe7062..7a26343f5 100644 --- a/semantics/immediateInstructions/rolw_r16_imm8.k +++ b/semantics/immediateInstructions/rolw_r16_imm8.k @@ -5,18 +5,19 @@ module ROLW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (rolw Imm8:Imm, R2:R16, .Operands) => . + execinstr (rolw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), rol( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), rol( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31))))) -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 15, 16), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31)))), 15, 16), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 15, 16), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31)))), 15, 16), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rorb_r8_imm8.k b/semantics/immediateInstructions/rorb_r8_imm8.k index ccb445c16..6b68e25b3 100644 --- a/semantics/immediateInstructions/rorb_r8_imm8.k +++ b/semantics/immediateInstructions/rorb_r8_imm8.k @@ -5,18 +5,19 @@ module RORB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (rorb Imm8:Imm, R2:R8, .Operands) => . + execinstr (rorb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), ror( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), ror( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( Imm8, mi(8, 31)))) -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( Imm8, mi(8, 31))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( Imm8, mi(8, 31))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( Imm8, mi(8, 31))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rorb_rh_imm8.k b/semantics/immediateInstructions/rorb_rh_imm8.k index 82fccc58e..052e5e515 100644 --- a/semantics/immediateInstructions/rorb_rh_imm8.k +++ b/semantics/immediateInstructions/rorb_rh_imm8.k @@ -5,18 +5,19 @@ module RORB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (rorb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (rorb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), ror( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), ror( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( Imm8, mi(8, 31)))), extractMInt( getParentValue(R2, RSMap), 56, 64)) -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( Imm8, mi(8, 31))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( Imm8, mi(8, 31))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( Imm8, mi(8, 31))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rorl_r32_imm8.k b/semantics/immediateInstructions/rorl_r32_imm8.k index 357200c7b..5cc890f4e 100644 --- a/semantics/immediateInstructions/rorl_r32_imm8.k +++ b/semantics/immediateInstructions/rorl_r32_imm8.k @@ -5,18 +5,19 @@ module RORL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (rorl Imm8:Imm, R2:R32, .Operands) => . + execinstr (rorl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), ror( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), ror( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31))))) -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31)))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31)))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rorq_r64_imm8.k b/semantics/immediateInstructions/rorq_r64_imm8.k index da211c3f5..562b26a64 100644 --- a/semantics/immediateInstructions/rorq_r64_imm8.k +++ b/semantics/immediateInstructions/rorq_r64_imm8.k @@ -5,18 +5,19 @@ module RORQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (rorq Imm8:Imm, R2:R64, .Operands) => . + execinstr (rorq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> ror( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))) +convToRegKeys(R2) |-> ror( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))) -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( ror( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( ror( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rorw_r16_imm8.k b/semantics/immediateInstructions/rorw_r16_imm8.k index d1236b28a..fd8e8c85f 100644 --- a/semantics/immediateInstructions/rorw_r16_imm8.k +++ b/semantics/immediateInstructions/rorw_r16_imm8.k @@ -5,18 +5,19 @@ module RORW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (rorw Imm8:Imm, R2:R16, .Operands) => . + execinstr (rorw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), ror( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), ror( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31))))) -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31)))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31)))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rorxl_r32_r32_imm8.k b/semantics/immediateInstructions/rorxl_r32_r32_imm8.k index bfe177a88..b76598261 100644 --- a/semantics/immediateInstructions/rorxl_r32_r32_imm8.k +++ b/semantics/immediateInstructions/rorxl_r32_r32_imm8.k @@ -5,17 +5,18 @@ module RORXL-R32-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (rorx Imm8:Imm, R2:R32, R3:R32, .Operands) => execinstr (rorxl Imm8:Imm, R2:R32, R3:R32, .Operands) + execinstr (rorx Imm8:MInt, R2:R32, R3:R32, .Operands) => execinstr (rorxl Imm8:MInt, R2:R32, R3:R32, .Operands) ... rule - execinstr (rorxl Imm8:Imm, R2:R32, R3:R32, .Operands) => . + execinstr (rorxl Imm8:MInt, R2:R32, R3:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), orMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(andMInt( concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(32, 31)))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(subMInt( mi(32, 32), andMInt( concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(32, 31))))))) +convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), orMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(andMInt( concatenateMInt( mi(24, 0), Imm8), mi(32, 31)))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(subMInt( mi(32, 32), andMInt( concatenateMInt( mi(24, 0), Imm8), mi(32, 31))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rorxq_r64_r64_imm8.k b/semantics/immediateInstructions/rorxq_r64_r64_imm8.k index 9fd93462f..8f983cc46 100644 --- a/semantics/immediateInstructions/rorxq_r64_r64_imm8.k +++ b/semantics/immediateInstructions/rorxq_r64_r64_imm8.k @@ -5,18 +5,19 @@ module RORXQ-R64-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (rorx Imm8:Imm, R2:R64, R3:R64, .Operands) => execinstr (rorxq Imm8:Imm, R2:R64, R3:R64, .Operands) + execinstr (rorx Imm8:MInt, R2:R64, R3:R64, .Operands) => execinstr (rorxq Imm8:MInt, R2:R64, R3:R64, .Operands) ... rule - execinstr (rorxq Imm8:Imm, R2:R64, R3:R64, .Operands) => . + execinstr (rorxq Imm8:MInt, R2:R64, R3:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> orMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(andMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 63)))), shiftLeftMInt( getParentValue(R2, RSMap), uvalueMInt(subMInt( mi(64, 64), andMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 63)))))) +convToRegKeys(R3) |-> orMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(andMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 63)))), shiftLeftMInt( getParentValue(R2, RSMap), uvalueMInt(subMInt( mi(64, 64), andMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 63)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/roundpd_xmm_xmm_imm8.k b/semantics/immediateInstructions/roundpd_xmm_xmm_imm8.k index 3d905be1e..64d633062 100644 --- a/semantics/immediateInstructions/roundpd_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/roundpd_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module ROUNDPD-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (roundpd Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (roundpd Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 128, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 192, 256), handleImmediateWithSignExtend(Imm8, 8, 8)))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 128, 192), Imm8), cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 192, 256), Imm8))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/roundps_xmm_xmm_imm8.k b/semantics/immediateInstructions/roundps_xmm_xmm_imm8.k index 01122c836..2b65954aa 100644 --- a/semantics/immediateInstructions/roundps_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/roundps_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module ROUNDPS-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (roundps Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (roundps Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 128, 160), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 160, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 192, 224), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8)))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 128, 160), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 160, 192), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 192, 224), Imm8), cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), Imm8))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/roundsd_xmm_xmm_imm8.k b/semantics/immediateInstructions/roundsd_xmm_xmm_imm8.k index ac19aef92..b9a39369a 100644 --- a/semantics/immediateInstructions/roundsd_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/roundsd_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module ROUNDSD-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (roundsd Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (roundsd Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 192), cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 192, 256), handleImmediateWithSignExtend(Imm8, 8, 8))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 192), cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 192, 256), Imm8)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/roundss_xmm_xmm_imm8.k b/semantics/immediateInstructions/roundss_xmm_xmm_imm8.k index 1b4627a59..c9cb2ebcd 100644 --- a/semantics/immediateInstructions/roundss_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/roundss_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module ROUNDSS-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (roundss Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (roundss Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 224), cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 224), cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), Imm8)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/salb_r8_imm8.k b/semantics/immediateInstructions/salb_r8_imm8.k index eb1b8d658..731d7b207 100644 --- a/semantics/immediateInstructions/salb_r8_imm8.k +++ b/semantics/immediateInstructions/salb_r8_imm8.k @@ -5,26 +5,27 @@ module SALB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (salb Imm8:Imm, R2:R8, .Operands) => . + execinstr (salb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 9)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 9)) -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 9), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 9), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/salb_rh_imm8.k b/semantics/immediateInstructions/salb_rh_imm8.k index 18f26de8b..481c601af 100644 --- a/semantics/immediateInstructions/salb_rh_imm8.k +++ b/semantics/immediateInstructions/salb_rh_imm8.k @@ -5,26 +5,27 @@ module SALB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (salb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (salb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 9), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 9), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/sall_r32_imm8.k b/semantics/immediateInstructions/sall_r32_imm8.k index bd70d5bca..fc371c96a 100644 --- a/semantics/immediateInstructions/sall_r32_imm8.k +++ b/semantics/immediateInstructions/sall_r32_imm8.k @@ -5,26 +5,27 @@ module SALL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (sall Imm8:Imm, R2:R32, .Operands) => . + execinstr (sall Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 33)) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 33)) -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 25, 26), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 25, 26), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 33), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 33), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/salq_r64_imm8.k b/semantics/immediateInstructions/salq_r64_imm8.k index a97ab3904..b6a9da66f 100644 --- a/semantics/immediateInstructions/salq_r64_imm8.k +++ b/semantics/immediateInstructions/salq_r64_imm8.k @@ -5,26 +5,27 @@ module SALQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (salq Imm8:Imm, R2:R64, .Operands) => . + execinstr (salq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 65) +convToRegKeys(R2) |-> extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 65) -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 57, 58), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 57, 58), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 65), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 65), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/salw_r16_imm8.k b/semantics/immediateInstructions/salw_r16_imm8.k index daf6db4bc..3b91e6f6c 100644 --- a/semantics/immediateInstructions/salw_r16_imm8.k +++ b/semantics/immediateInstructions/salw_r16_imm8.k @@ -5,26 +5,27 @@ module SALW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (salw Imm8:Imm, R2:R16, .Operands) => . + execinstr (salw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 17)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 17)) -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 9, 10), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 9, 10), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 17), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 17), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/sarb_r8_imm8.k b/semantics/immediateInstructions/sarb_r8_imm8.k index aaa4f3119..33b127101 100644 --- a/semantics/immediateInstructions/sarb_r8_imm8.k +++ b/semantics/immediateInstructions/sarb_r8_imm8.k @@ -5,26 +5,27 @@ module SARB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (sarb Imm8:Imm, R2:R8, .Operands) => . + execinstr (sarb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 8)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 8)) -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 7, 8), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 7, 8), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 8), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 8), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/sarb_rh_imm8.k b/semantics/immediateInstructions/sarb_rh_imm8.k index a2bbb2422..484dbfa75 100644 --- a/semantics/immediateInstructions/sarb_rh_imm8.k +++ b/semantics/immediateInstructions/sarb_rh_imm8.k @@ -5,26 +5,27 @@ module SARB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (sarb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (sarb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 8)), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 8)), extractMInt( getParentValue(R2, RSMap), 56, 64)) -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 7, 8), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 7, 8), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 8), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 8), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/sarl_r32_imm8.k b/semantics/immediateInstructions/sarl_r32_imm8.k index 3c8ca235a..1d500a865 100644 --- a/semantics/immediateInstructions/sarl_r32_imm8.k +++ b/semantics/immediateInstructions/sarl_r32_imm8.k @@ -5,26 +5,27 @@ module SARL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (sarl Imm8:Imm, R2:R32, .Operands) => . + execinstr (sarl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 32)) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 32)) -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 32, 33), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 32, 33), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 31, 32), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 25, 26), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 24, 25), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 31, 32), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 25, 26), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 24, 25), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 32), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 32), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/sarq_r64_imm8.k b/semantics/immediateInstructions/sarq_r64_imm8.k index abe87b6c5..c1ddcbc44 100644 --- a/semantics/immediateInstructions/sarq_r64_imm8.k +++ b/semantics/immediateInstructions/sarq_r64_imm8.k @@ -5,26 +5,27 @@ module SARQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (sarq Imm8:Imm, R2:R64, .Operands) => . + execinstr (sarq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 64) +convToRegKeys(R2) |-> extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 64) -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 64, 65), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 64, 65), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 63, 64), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 57, 58), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 56, 57), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 63, 64), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 57, 58), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 56, 57), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 64), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 64), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/sarw_r16_imm8.k b/semantics/immediateInstructions/sarw_r16_imm8.k index b95200220..47c91a2eb 100644 --- a/semantics/immediateInstructions/sarw_r16_imm8.k +++ b/semantics/immediateInstructions/sarw_r16_imm8.k @@ -5,26 +5,27 @@ module SARW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (sarw Imm8:Imm, R2:R16, .Operands) => . + execinstr (sarw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 16)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 16)) -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 16, 17), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 16, 17), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 15, 16), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 9, 10), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 15, 16), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 9, 10), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 16), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 16), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/sbbb_al_imm8.k b/semantics/immediateInstructions/sbbb_al_imm8.k index b284f3086..7aa8d8a4a 100644 --- a/semantics/immediateInstructions/sbbb_al_imm8.k +++ b/semantics/immediateInstructions/sbbb_al_imm8.k @@ -5,26 +5,27 @@ module SBBB-AL-IMM8 imports X86-CONFIGURATION rule - execinstr (sbbb Imm8:Imm, %al, .Operands) => . + execinstr (sbbb Imm8:MInt, %al, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 56), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9)) +"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 56), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/sbbb_r8_imm8.k b/semantics/immediateInstructions/sbbb_r8_imm8.k index da7c9cc6f..02f1b4a23 100644 --- a/semantics/immediateInstructions/sbbb_r8_imm8.k +++ b/semantics/immediateInstructions/sbbb_r8_imm8.k @@ -5,26 +5,27 @@ module SBBB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (sbbb Imm8:Imm, R2:R8, .Operands) => . + execinstr (sbbb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/sbbb_rh_imm8.k b/semantics/immediateInstructions/sbbb_rh_imm8.k index aa2791741..cf51a6ad0 100644 --- a/semantics/immediateInstructions/sbbb_rh_imm8.k +++ b/semantics/immediateInstructions/sbbb_rh_imm8.k @@ -5,26 +5,27 @@ module SBBB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (sbbb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (sbbb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 51, 52)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 51, 52)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/sbbl_eax_imm32.k b/semantics/immediateInstructions/sbbl_eax_imm32.k index 144e8571d..2f8281dcb 100644 --- a/semantics/immediateInstructions/sbbl_eax_imm32.k +++ b/semantics/immediateInstructions/sbbl_eax_imm32.k @@ -5,26 +5,27 @@ module SBBL-EAX-IMM32 imports X86-CONFIGURATION rule - execinstr (sbbl Imm32:Imm, %eax, .Operands) => . + execinstr (sbbl Imm32:MInt, %eax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33)) +"RAX" |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/sbbl_r32_imm32.k b/semantics/immediateInstructions/sbbl_r32_imm32.k index 4cea53199..c84bf62d0 100644 --- a/semantics/immediateInstructions/sbbl_r32_imm32.k +++ b/semantics/immediateInstructions/sbbl_r32_imm32.k @@ -5,26 +5,27 @@ module SBBL-R32-IMM32 imports X86-CONFIGURATION rule - execinstr (sbbl Imm32:Imm, R2:R32, .Operands) => . + execinstr (sbbl Imm32:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/sbbl_r32_imm8.k b/semantics/immediateInstructions/sbbl_r32_imm8.k index b87231fa8..0dbacb0a0 100644 --- a/semantics/immediateInstructions/sbbl_r32_imm8.k +++ b/semantics/immediateInstructions/sbbl_r32_imm8.k @@ -5,26 +5,27 @@ module SBBL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (sbbl Imm8:Imm, R2:R32, .Operands) => . + execinstr (sbbl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/sbbq_r64_imm32.k b/semantics/immediateInstructions/sbbq_r64_imm32.k index 1bdf5cf0a..7ff40a0a7 100644 --- a/semantics/immediateInstructions/sbbq_r64_imm32.k +++ b/semantics/immediateInstructions/sbbq_r64_imm32.k @@ -5,26 +5,27 @@ module SBBQ-R64-IMM32 imports X86-CONFIGURATION rule - execinstr (sbbq Imm32:Imm, R2:R64, .Operands) => . + execinstr (sbbq Imm32:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) +convToRegKeys(R2) |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/sbbq_r64_imm8.k b/semantics/immediateInstructions/sbbq_r64_imm8.k index a6e618e39..4d44c0e40 100644 --- a/semantics/immediateInstructions/sbbq_r64_imm8.k +++ b/semantics/immediateInstructions/sbbq_r64_imm8.k @@ -5,26 +5,27 @@ module SBBQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (sbbq Imm8:Imm, R2:R64, .Operands) => . + execinstr (sbbq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) +convToRegKeys(R2) |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/sbbq_rax_imm32.k b/semantics/immediateInstructions/sbbq_rax_imm32.k index 5f33798ee..9568a36fb 100644 --- a/semantics/immediateInstructions/sbbq_rax_imm32.k +++ b/semantics/immediateInstructions/sbbq_rax_imm32.k @@ -5,26 +5,27 @@ module SBBQ-RAX-IMM32 imports X86-CONFIGURATION rule - execinstr (sbbq Imm32:Imm, %rax, .Operands) => . + execinstr (sbbq Imm32:MInt, %rax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65) +"RAX" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/sbbw_ax_imm16.k b/semantics/immediateInstructions/sbbw_ax_imm16.k index a8c2c5bd3..758b25a49 100644 --- a/semantics/immediateInstructions/sbbw_ax_imm16.k +++ b/semantics/immediateInstructions/sbbw_ax_imm16.k @@ -5,26 +5,27 @@ module SBBW-AX-IMM16 imports X86-CONFIGURATION rule - execinstr (sbbw Imm16:Imm, %ax, .Operands) => . + execinstr (sbbw Imm16:MInt, %ax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17)) +"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm16, 11, 12), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/sbbw_r16_imm16.k b/semantics/immediateInstructions/sbbw_r16_imm16.k index 251a054d1..6d0ae3c6d 100644 --- a/semantics/immediateInstructions/sbbw_r16_imm16.k +++ b/semantics/immediateInstructions/sbbw_r16_imm16.k @@ -5,26 +5,27 @@ module SBBW-R16-IMM16 imports X86-CONFIGURATION rule - execinstr (sbbw Imm16:Imm, R2:R16, .Operands) => . + execinstr (sbbw Imm16:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm16, 11, 12), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/sbbw_r16_imm8.k b/semantics/immediateInstructions/sbbw_r16_imm8.k index 0c9f975b2..3aeb7dd7d 100644 --- a/semantics/immediateInstructions/sbbw_r16_imm8.k +++ b/semantics/immediateInstructions/sbbw_r16_imm8.k @@ -5,26 +5,27 @@ module SBBW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (sbbw Imm8:Imm, R2:R16, .Operands) => . + execinstr (sbbw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/shlb_r8_imm8.k b/semantics/immediateInstructions/shlb_r8_imm8.k index 0174e9636..4040f4247 100644 --- a/semantics/immediateInstructions/shlb_r8_imm8.k +++ b/semantics/immediateInstructions/shlb_r8_imm8.k @@ -5,26 +5,27 @@ module SHLB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (shlb Imm8:Imm, R2:R8, .Operands) => . + execinstr (shlb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 9)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 9)) -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 9), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 9), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/shlb_rh_imm8.k b/semantics/immediateInstructions/shlb_rh_imm8.k index bfd30eb44..3e65a2faa 100644 --- a/semantics/immediateInstructions/shlb_rh_imm8.k +++ b/semantics/immediateInstructions/shlb_rh_imm8.k @@ -5,26 +5,27 @@ module SHLB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (shlb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (shlb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 9), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 9), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/shldl_r32_r32_imm8.k b/semantics/immediateInstructions/shldl_r32_r32_imm8.k index 4671643c0..9bcbd4c3d 100644 --- a/semantics/immediateInstructions/shldl_r32_r32_imm8.k +++ b/semantics/immediateInstructions/shldl_r32_r32_imm8.k @@ -5,11 +5,12 @@ module SHLDL-R32-R32 imports X86-CONFIGURATION rule - execinstr (shldl Imm8:Imm, R2:R32, R1:R32, .Operands) => + execinstr (shldl Imm8:MInt, R2:R32, R1:R32, .Operands) => execinstr (shldl R1, getRegisterValue(R1, RSMap), getRegisterValue(R2, RSMap), - shiftCountMask(handleImmediateWithSignExtend(Imm8, 8, 8), 32), .Operands) + shiftCountMask(Imm8, 32), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (shldl R, MIdest:MInt, MIsrc:MInt, MIcount:MInt, .Operands) => diff --git a/semantics/immediateInstructions/shldq_r64_r64_imm8.k b/semantics/immediateInstructions/shldq_r64_r64_imm8.k index d0ec22d65..c37d6046e 100644 --- a/semantics/immediateInstructions/shldq_r64_r64_imm8.k +++ b/semantics/immediateInstructions/shldq_r64_r64_imm8.k @@ -5,11 +5,12 @@ module SHLDQ-R64-R64 imports X86-CONFIGURATION rule - execinstr (shldq Imm8:Imm, R2:R64, R1:R64, .Operands) => + execinstr (shldq Imm8:MInt, R2:R64, R1:R64, .Operands) => execinstr (shldq R1, getRegisterValue(R1, RSMap), getRegisterValue(R2, RSMap), - shiftCountMask(handleImmediateWithSignExtend(Imm8, 8, 8), 64), .Operands) + shiftCountMask(Imm8, 64), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (shldq R, MIdest:MInt, MIsrc:MInt, MIcount:MInt, .Operands) => . diff --git a/semantics/immediateInstructions/shldw_r16_r16_imm8.k b/semantics/immediateInstructions/shldw_r16_r16_imm8.k index 184331886..a0ec3d9eb 100644 --- a/semantics/immediateInstructions/shldw_r16_r16_imm8.k +++ b/semantics/immediateInstructions/shldw_r16_r16_imm8.k @@ -5,11 +5,12 @@ module SHLDW-R16-R16 imports X86-CONFIGURATION rule - execinstr (shldw Imm8:Imm, R2:R16, R1:R16, .Operands) => + execinstr (shldw Imm8:MInt, R2:R16, R1:R16, .Operands) => execinstr (shldw R1, getRegisterValue(R1, RSMap), getRegisterValue(R2, RSMap), - shiftCountMask(handleImmediateWithSignExtend(Imm8, 8, 8), 32), .Operands) + shiftCountMask(Imm8, 32), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (shldw R, MIdest:MInt, MIsrc:MInt, MIcount:MInt, .Operands) => . diff --git a/semantics/immediateInstructions/shll_r32_imm8.k b/semantics/immediateInstructions/shll_r32_imm8.k index 4e7ca5115..96e44fdec 100644 --- a/semantics/immediateInstructions/shll_r32_imm8.k +++ b/semantics/immediateInstructions/shll_r32_imm8.k @@ -5,26 +5,27 @@ module SHLL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (shll Imm8:Imm, R2:R32, .Operands) => . + execinstr (shll Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 33)) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 33)) -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 25, 26), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 25, 26), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 33), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 33), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/shlq_r64_imm8.k b/semantics/immediateInstructions/shlq_r64_imm8.k index b48fe11d4..97e23d1e6 100644 --- a/semantics/immediateInstructions/shlq_r64_imm8.k +++ b/semantics/immediateInstructions/shlq_r64_imm8.k @@ -5,26 +5,27 @@ module SHLQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (shlq Imm8:Imm, R2:R64, .Operands) => . + execinstr (shlq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 65) +convToRegKeys(R2) |-> extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 65) -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 57, 58), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 57, 58), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 65), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 65), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/shlw_r16_imm8.k b/semantics/immediateInstructions/shlw_r16_imm8.k index 55df900af..26db433cf 100644 --- a/semantics/immediateInstructions/shlw_r16_imm8.k +++ b/semantics/immediateInstructions/shlw_r16_imm8.k @@ -5,26 +5,27 @@ module SHLW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (shlw Imm8:Imm, R2:R16, .Operands) => . + execinstr (shlw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 17)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 17)) -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 9, 10), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 9, 10), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 17), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 17), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/shrb_r8_imm8.k b/semantics/immediateInstructions/shrb_r8_imm8.k index 3b8d8c479..107f7f7fb 100644 --- a/semantics/immediateInstructions/shrb_r8_imm8.k +++ b/semantics/immediateInstructions/shrb_r8_imm8.k @@ -5,26 +5,27 @@ module SHRB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (shrb Imm8:Imm, R2:R8, .Operands) => . + execinstr (shrb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 8)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 8)) -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 7, 8), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 7, 8), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 8), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 8), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool eqMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), mi(1, 1))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool eqMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), mi(1, 1))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/shrb_rh_imm8.k b/semantics/immediateInstructions/shrb_rh_imm8.k index 2a21f3d61..b71d3a547 100644 --- a/semantics/immediateInstructions/shrb_rh_imm8.k +++ b/semantics/immediateInstructions/shrb_rh_imm8.k @@ -5,26 +5,27 @@ module SHRB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (shrb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (shrb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 8)), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 8)), extractMInt( getParentValue(R2, RSMap), 56, 64)) -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 7, 8), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 7, 8), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 8), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 8), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/shrdl_r32_r32_imm8.k b/semantics/immediateInstructions/shrdl_r32_r32_imm8.k index b005bfa99..69ffe4181 100644 --- a/semantics/immediateInstructions/shrdl_r32_r32_imm8.k +++ b/semantics/immediateInstructions/shrdl_r32_r32_imm8.k @@ -5,11 +5,12 @@ module SHRDL-R32-R32 imports X86-CONFIGURATION rule - execinstr (shrdl Imm8:Imm, R2:R32, R1:R32, .Operands) => + execinstr (shrdl Imm8:MInt, R2:R32, R1:R32, .Operands) => execinstr (shrdl R1, getRegisterValue(R1, RSMap), getRegisterValue(R2, RSMap), - shiftCountMask(handleImmediateWithSignExtend(Imm8, 8, 8), 32), .Operands) + shiftCountMask(Imm8, 32), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (shrdl R, MIdest:MInt, MIsrc:MInt, MIcount:MInt, .Operands) => diff --git a/semantics/immediateInstructions/shrdq_r64_r64_imm8.k b/semantics/immediateInstructions/shrdq_r64_r64_imm8.k index b3758651a..8186aa980 100644 --- a/semantics/immediateInstructions/shrdq_r64_r64_imm8.k +++ b/semantics/immediateInstructions/shrdq_r64_r64_imm8.k @@ -5,11 +5,12 @@ module SHLDQ-R64-R64 imports X86-CONFIGURATION rule - execinstr (shrdq Imm8:Imm, R2:R64, R1:R64, .Operands) => + execinstr (shrdq Imm8:MInt, R2:R64, R1:R64, .Operands) => execinstr (shrdq R1, getRegisterValue(R1, RSMap), getRegisterValue(R2, RSMap), - shiftCountMask(handleImmediateWithSignExtend(Imm8, 8, 8), 64), .Operands) + shiftCountMask(Imm8, 64), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (shrdq R, MIdest:MInt, MIsrc:MInt, MIcount:MInt, .Operands) => . diff --git a/semantics/immediateInstructions/shrdw_r16_r16_imm8.k b/semantics/immediateInstructions/shrdw_r16_r16_imm8.k index 85326f59b..bf4ba14cb 100644 --- a/semantics/immediateInstructions/shrdw_r16_r16_imm8.k +++ b/semantics/immediateInstructions/shrdw_r16_r16_imm8.k @@ -5,11 +5,12 @@ module SHLDW-R16-R16 imports X86-CONFIGURATION rule - execinstr (shrdw Imm8:Imm, R2:R16, R1:R16, .Operands) => + execinstr (shrdw Imm8:MInt, R2:R16, R1:R16, .Operands) => execinstr (shrdw R1, getRegisterValue(R1, RSMap), getRegisterValue(R2, RSMap), - shiftCountMask(handleImmediateWithSignExtend(Imm8, 8, 8), 32), .Operands) + shiftCountMask(Imm8, 32), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (shrdw R, MIdest:MInt, MIsrc:MInt, MIcount:MInt, .Operands) => . diff --git a/semantics/immediateInstructions/shrl_r32_imm8.k b/semantics/immediateInstructions/shrl_r32_imm8.k index 09e799d00..db234d059 100644 --- a/semantics/immediateInstructions/shrl_r32_imm8.k +++ b/semantics/immediateInstructions/shrl_r32_imm8.k @@ -5,26 +5,27 @@ module SHRL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (shrl Imm8:Imm, R2:R32, .Operands) => . + execinstr (shrl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 32)) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 32)) -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 32, 33), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 32, 33), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 31, 32), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 25, 26), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 24, 25), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 31, 32), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 25, 26), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 24, 25), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 32), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 32), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/shrq_r64_imm8.k b/semantics/immediateInstructions/shrq_r64_imm8.k index 4333f654e..b8fc04b9b 100644 --- a/semantics/immediateInstructions/shrq_r64_imm8.k +++ b/semantics/immediateInstructions/shrq_r64_imm8.k @@ -5,26 +5,27 @@ module SHRQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (shrq Imm8:Imm, R2:R64, .Operands) => . + execinstr (shrq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 64) +convToRegKeys(R2) |-> extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 64) -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 64, 65), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 64, 65), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 63, 64), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 57, 58), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 56, 57), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 63, 64), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 57, 58), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 56, 57), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 64), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 64), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1)) andBool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1)) andBool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/shrw_r16_imm8.k b/semantics/immediateInstructions/shrw_r16_imm8.k index 6770d033b..44c8c50a9 100644 --- a/semantics/immediateInstructions/shrw_r16_imm8.k +++ b/semantics/immediateInstructions/shrw_r16_imm8.k @@ -5,26 +5,27 @@ module SHRW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (shrw Imm8:Imm, R2:R16, .Operands) => . + execinstr (shrw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 16)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 16)) -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 16, 17), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 16, 17), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 15, 16), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 9, 10), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 15, 16), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 9, 10), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 16), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 16), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/shufpd_xmm_xmm_imm8.k b/semantics/immediateInstructions/shufpd_xmm_xmm_imm8.k index c86790412..cd66af7db 100644 --- a/semantics/immediateInstructions/shufpd_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/shufpd_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module SHUFPD-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (shufpd Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (shufpd Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 192) #else extractMInt( getParentValue(R2, RSMap), 192, 256) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R3, RSMap), 192, 256) #fi))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 192) #else extractMInt( getParentValue(R2, RSMap), 192, 256) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R3, RSMap), 192, 256) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/shufps_xmm_xmm_imm8.k b/semantics/immediateInstructions/shufps_xmm_xmm_imm8.k index 5c6a1c7f4..5db83df0e 100644 --- a/semantics/immediateInstructions/shufps_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/shufps_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module SHUFPS-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (shufps Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (shufps Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/subb_al_imm8.k b/semantics/immediateInstructions/subb_al_imm8.k index 618562cae..a8b857ea8 100644 --- a/semantics/immediateInstructions/subb_al_imm8.k +++ b/semantics/immediateInstructions/subb_al_imm8.k @@ -5,26 +5,27 @@ module SUBB-AL-IMM8 imports X86-CONFIGURATION rule - execinstr (subb Imm8:Imm, %al, .Operands) => . + execinstr (subb Imm8:MInt, %al, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 56), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9)) +"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 56), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/subb_r8_imm8.k b/semantics/immediateInstructions/subb_r8_imm8.k index 387d456f2..a43a7548d 100644 --- a/semantics/immediateInstructions/subb_r8_imm8.k +++ b/semantics/immediateInstructions/subb_r8_imm8.k @@ -5,26 +5,27 @@ module SUBB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (subb Imm8:Imm, R2:R8, .Operands) => . + execinstr (subb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/subb_rh_imm8.k b/semantics/immediateInstructions/subb_rh_imm8.k index e543de998..7c245cf10 100644 --- a/semantics/immediateInstructions/subb_rh_imm8.k +++ b/semantics/immediateInstructions/subb_rh_imm8.k @@ -5,26 +5,27 @@ module SUBB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (subb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (subb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 51, 52)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 51, 52)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/subl_eax_imm32.k b/semantics/immediateInstructions/subl_eax_imm32.k index 29cd97b6a..c0ff3bfaf 100644 --- a/semantics/immediateInstructions/subl_eax_imm32.k +++ b/semantics/immediateInstructions/subl_eax_imm32.k @@ -5,26 +5,27 @@ module SUBL-EAX-IMM32 imports X86-CONFIGURATION rule - execinstr (subl Imm32:Imm, %eax, .Operands) => . + execinstr (subl Imm32:MInt, %eax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33)) +"RAX" |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/subl_r32_imm32.k b/semantics/immediateInstructions/subl_r32_imm32.k index 0755bbf2d..33b4699d9 100644 --- a/semantics/immediateInstructions/subl_r32_imm32.k +++ b/semantics/immediateInstructions/subl_r32_imm32.k @@ -5,26 +5,27 @@ module SUBL-R32-IMM32 imports X86-CONFIGURATION rule - execinstr (subl Imm32:Imm, R2:R32, .Operands) => . + execinstr (subl Imm32:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/subl_r32_imm8.k b/semantics/immediateInstructions/subl_r32_imm8.k index 8bc784fb6..c211b17c1 100644 --- a/semantics/immediateInstructions/subl_r32_imm8.k +++ b/semantics/immediateInstructions/subl_r32_imm8.k @@ -5,26 +5,27 @@ module SUBL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (subl Imm8:Imm, R2:R32, .Operands) => . + execinstr (subl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/subq_r64_imm32.k b/semantics/immediateInstructions/subq_r64_imm32.k index 431209925..61eab8859 100644 --- a/semantics/immediateInstructions/subq_r64_imm32.k +++ b/semantics/immediateInstructions/subq_r64_imm32.k @@ -5,26 +5,27 @@ module SUBQ-R64-IMM32 imports X86-CONFIGURATION rule - execinstr (subq Imm32:Imm, R2:R64, .Operands) => . + execinstr (subq Imm32:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) +convToRegKeys(R2) |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/subq_r64_imm8.k b/semantics/immediateInstructions/subq_r64_imm8.k index 43dc68abb..7e7143bb6 100644 --- a/semantics/immediateInstructions/subq_r64_imm8.k +++ b/semantics/immediateInstructions/subq_r64_imm8.k @@ -5,26 +5,27 @@ module SUBQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (subq Imm8:Imm, R2:R64, .Operands) => . + execinstr (subq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) +convToRegKeys(R2) |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/subq_rax_imm32.k b/semantics/immediateInstructions/subq_rax_imm32.k index 55b2eea31..fcb689e44 100644 --- a/semantics/immediateInstructions/subq_rax_imm32.k +++ b/semantics/immediateInstructions/subq_rax_imm32.k @@ -5,26 +5,27 @@ module SUBQ-RAX-IMM32 imports X86-CONFIGURATION rule - execinstr (subq Imm32:Imm, %rax, .Operands) => . + execinstr (subq Imm32:MInt, %rax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65) +"RAX" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/subw_ax_imm16.k b/semantics/immediateInstructions/subw_ax_imm16.k index b06af6178..30e03aec1 100644 --- a/semantics/immediateInstructions/subw_ax_imm16.k +++ b/semantics/immediateInstructions/subw_ax_imm16.k @@ -5,26 +5,27 @@ module SUBW-AX-IMM16 imports X86-CONFIGURATION rule - execinstr (subw Imm16:Imm, %ax, .Operands) => . + execinstr (subw Imm16:MInt, %ax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 48), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17)) +"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 48), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm16, 11, 12), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/subw_r16_imm16.k b/semantics/immediateInstructions/subw_r16_imm16.k index adf372649..c7dcc5abe 100644 --- a/semantics/immediateInstructions/subw_r16_imm16.k +++ b/semantics/immediateInstructions/subw_r16_imm16.k @@ -5,26 +5,27 @@ module SUBW-R16-IMM16 imports X86-CONFIGURATION rule - execinstr (subw Imm16:Imm, R2:R16, .Operands) => . + execinstr (subw Imm16:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm16, 11, 12), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/subw_r16_imm8.k b/semantics/immediateInstructions/subw_r16_imm8.k index bcb7196b4..db1f91929 100644 --- a/semantics/immediateInstructions/subw_r16_imm8.k +++ b/semantics/immediateInstructions/subw_r16_imm8.k @@ -5,26 +5,27 @@ module SUBW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (subw Imm8:Imm, R2:R16, .Operands) => . + execinstr (subw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/testb_al_imm8.k b/semantics/immediateInstructions/testb_al_imm8.k index 00b0709b1..99ddee5e5 100644 --- a/semantics/immediateInstructions/testb_al_imm8.k +++ b/semantics/immediateInstructions/testb_al_imm8.k @@ -5,24 +5,25 @@ module TESTB-AL-IMM8 imports X86-CONFIGURATION rule - execinstr (testb Imm8:Imm, %al, .Operands) => . + execinstr (testb Imm8:MInt, %al, .Operands) => . ... RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 64), Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/testb_r8_imm8.k b/semantics/immediateInstructions/testb_r8_imm8.k index 2917ddb10..46ea4daed 100644 --- a/semantics/immediateInstructions/testb_r8_imm8.k +++ b/semantics/immediateInstructions/testb_r8_imm8.k @@ -5,24 +5,25 @@ module TESTB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (testb Imm8:Imm, R2:R8, .Operands) => . + execinstr (testb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/testb_rh_imm8.k b/semantics/immediateInstructions/testb_rh_imm8.k index d2535cf3d..fe652acf1 100644 --- a/semantics/immediateInstructions/testb_rh_imm8.k +++ b/semantics/immediateInstructions/testb_rh_imm8.k @@ -5,24 +5,25 @@ module TESTB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (testb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (testb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 55, 56), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 54, 55), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 53, 54), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 52, 53), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 51, 52), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 50, 51), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 49, 50), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 55, 56), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 54, 55), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 53, 54), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 52, 53), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 51, 52), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 50, 51), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 49, 50), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/testl_eax_imm32.k b/semantics/immediateInstructions/testl_eax_imm32.k index c74ce0f0b..ab7b1c10b 100644 --- a/semantics/immediateInstructions/testl_eax_imm32.k +++ b/semantics/immediateInstructions/testl_eax_imm32.k @@ -5,24 +5,25 @@ module TESTL-EAX-IMM32 imports X86-CONFIGURATION rule - execinstr (testl Imm32:Imm, %eax, .Operands) => . + execinstr (testl Imm32:MInt, %eax, .Operands) => . ... RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 32, 64), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 32, 64), Imm32), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), extractMInt( Imm32, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/testl_r32_imm32.k b/semantics/immediateInstructions/testl_r32_imm32.k index af624c5f6..4f2510169 100644 --- a/semantics/immediateInstructions/testl_r32_imm32.k +++ b/semantics/immediateInstructions/testl_r32_imm32.k @@ -5,24 +5,25 @@ module TESTL-R32-IMM32 imports X86-CONFIGURATION rule - execinstr (testl Imm32:Imm, R2:R32, .Operands) => . + execinstr (testl Imm32:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), Imm32), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), extractMInt( Imm32, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/testq_r64_imm32.k b/semantics/immediateInstructions/testq_r64_imm32.k index 0bae894e7..63c1b68be 100644 --- a/semantics/immediateInstructions/testq_r64_imm32.k +++ b/semantics/immediateInstructions/testq_r64_imm32.k @@ -5,24 +5,25 @@ module TESTQ-R64-IMM32 imports X86-CONFIGURATION rule - execinstr (testq Imm32:Imm, R2:R64, .Operands) => . + execinstr (testq Imm32:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(Imm32))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/testq_rax_imm32.k b/semantics/immediateInstructions/testq_rax_imm32.k index f470eeba8..bd2c6c983 100644 --- a/semantics/immediateInstructions/testq_rax_imm32.k +++ b/semantics/immediateInstructions/testq_rax_imm32.k @@ -5,24 +5,25 @@ module TESTQ-RAX-IMM32 imports X86-CONFIGURATION rule - execinstr (testq Imm32:Imm, %rax, .Operands) => . + execinstr (testq Imm32:MInt, %rax, .Operands) => . ... RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( getParentValue(%rax, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( getParentValue(%rax, RSMap), mi(64, svalueMInt(Imm32))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/testw_ax_imm16.k b/semantics/immediateInstructions/testw_ax_imm16.k index b1976b2ce..18d1030ff 100644 --- a/semantics/immediateInstructions/testw_ax_imm16.k +++ b/semantics/immediateInstructions/testw_ax_imm16.k @@ -5,24 +5,25 @@ module TESTW-AX-IMM16 imports X86-CONFIGURATION rule - execinstr (testw Imm16:Imm, %ax, .Operands) => . + execinstr (testw Imm16:MInt, %ax, .Operands) => . ... RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 15, 16)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 14, 15)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 13, 14)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 12, 13)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 10, 11)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 9, 10)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm16, 15, 16)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm16, 14, 15)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm16, 13, 14)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm16, 12, 13)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm16, 11, 12)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm16, 10, 11)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm16, 9, 10)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm16, 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 48, 64), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 48, 64), Imm16), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), extractMInt( Imm16, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/testw_r16_imm16.k b/semantics/immediateInstructions/testw_r16_imm16.k index b7ced050b..f1c729743 100644 --- a/semantics/immediateInstructions/testw_r16_imm16.k +++ b/semantics/immediateInstructions/testw_r16_imm16.k @@ -5,24 +5,25 @@ module TESTW-R16-IMM16 imports X86-CONFIGURATION rule - execinstr (testw Imm16:Imm, R2:R16, .Operands) => . + execinstr (testw Imm16:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 15, 16)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 14, 15)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 13, 14)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 12, 13)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 10, 11)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 9, 10)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm16, 15, 16)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm16, 14, 15)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm16, 13, 14)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm16, 12, 13)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm16, 11, 12)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm16, 10, 11)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm16, 9, 10)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm16, 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), Imm16), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( Imm16, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/vblendpd_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vblendpd_xmm_xmm_xmm_imm8.k index 3ee018fd2..6fedd58aa 100644 --- a/semantics/immediateInstructions/vblendpd_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vblendpd_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VBLENDPD-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vblendpd Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vblendpd Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 192) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 256) #else extractMInt( getParentValue(R2, RSMap), 192, 256) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 192) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 256) #else extractMInt( getParentValue(R2, RSMap), 192, 256) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vblendpd_ymm_ymm_ymm_imm8.k b/semantics/immediateInstructions/vblendpd_ymm_ymm_ymm_imm8.k index 2b4f0530f..41d9e07f4 100644 --- a/semantics/immediateInstructions/vblendpd_ymm_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vblendpd_ymm_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VBLENDPD-YMM-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vblendpd Imm8:Imm, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . + execinstr (vblendpd Imm8:MInt, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 64) #else extractMInt( getParentValue(R2, RSMap), 0, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 128) #else extractMInt( getParentValue(R2, RSMap), 64, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 192) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 256) #else extractMInt( getParentValue(R2, RSMap), 192, 256) #fi)))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 64) #else extractMInt( getParentValue(R2, RSMap), 0, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 128) #else extractMInt( getParentValue(R2, RSMap), 64, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 192) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 256) #else extractMInt( getParentValue(R2, RSMap), 192, 256) #fi)))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vblendps_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vblendps_xmm_xmm_xmm_imm8.k index f8ca5b094..efd6ef5d6 100644 --- a/semantics/immediateInstructions/vblendps_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vblendps_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VBLENDPS-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vblendps Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vblendps Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 160, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 160, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vblendps_ymm_ymm_ymm_imm8.k b/semantics/immediateInstructions/vblendps_ymm_ymm_ymm_imm8.k index b1879648f..800b2246c 100644 --- a/semantics/immediateInstructions/vblendps_ymm_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vblendps_ymm_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VBLENDPS-YMM-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vblendps Imm8:Imm, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . + execinstr (vblendps Imm8:MInt, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( getParentValue(R2, RSMap), 0, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 32, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 96) #else extractMInt( getParentValue(R2, RSMap), 64, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 96, 128) #else extractMInt( getParentValue(R2, RSMap), 96, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 160, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi)))))))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( getParentValue(R2, RSMap), 0, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 32, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 96) #else extractMInt( getParentValue(R2, RSMap), 64, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 96, 128) #else extractMInt( getParentValue(R2, RSMap), 96, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 160, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vcmppd_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vcmppd_xmm_xmm_xmm_imm8.k index 96ee895b5..a5fa7aef6 100644 --- a/semantics/immediateInstructions/vcmppd_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vcmppd_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VCMPPD-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vcmppd Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vcmppd Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( getParentValue(R2, RSMap), 128, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( getParentValue(R2, RSMap), 128, 192), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vcmppd_ymm_ymm_ymm_imm8.k b/semantics/immediateInstructions/vcmppd_ymm_ymm_ymm_imm8.k index cad4e5ef0..fe4085da0 100644 --- a/semantics/immediateInstructions/vcmppd_ymm_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vcmppd_ymm_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VCMPPD-YMM-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vcmppd Imm8:Imm, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . + execinstr (vcmppd Imm8:MInt, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 0, 64), extractMInt( getParentValue(R2, RSMap), 0, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 64, 128), extractMInt( getParentValue(R2, RSMap), 64, 128), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( getParentValue(R2, RSMap), 128, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi)))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 0, 64), extractMInt( getParentValue(R2, RSMap), 0, 64), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 64, 128), extractMInt( getParentValue(R2, RSMap), 64, 128), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( getParentValue(R2, RSMap), 128, 192), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi)))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vcmpps_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vcmpps_xmm_xmm_xmm_imm8.k index fa90167e3..c91209c6d 100644 --- a/semantics/immediateInstructions/vcmpps_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vcmpps_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VCMPPS-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vcmpps Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vcmpps Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vcmpps_ymm_ymm_ymm_imm8.k b/semantics/immediateInstructions/vcmpps_ymm_ymm_ymm_imm8.k index e08fe406c..0e602f16e 100644 --- a/semantics/immediateInstructions/vcmpps_ymm_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vcmpps_ymm_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VCMPPS-YMM-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vcmpps Imm8:Imm, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . + execinstr (vcmpps Imm8:MInt, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( getParentValue(R2, RSMap), 0, 32), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( getParentValue(R2, RSMap), 32, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( getParentValue(R2, RSMap), 64, 96), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( getParentValue(R2, RSMap), 96, 128), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi)))))))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( getParentValue(R2, RSMap), 0, 32), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( getParentValue(R2, RSMap), 32, 64), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( getParentValue(R2, RSMap), 64, 96), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( getParentValue(R2, RSMap), 96, 128), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vcmpsd_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vcmpsd_xmm_xmm_xmm_imm8.k index 49e9c555f..e0d0e21c1 100644 --- a/semantics/immediateInstructions/vcmpsd_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vcmpsd_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VCMPSD-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vcmpsd Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vcmpsd Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 192), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 192), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vcmpss_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vcmpss_xmm_xmm_xmm_imm8.k index 687eb73a4..a5980ae2c 100644 --- a/semantics/immediateInstructions/vcmpss_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vcmpss_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VCMPSS-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vcmpss Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vcmpss Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 224), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 224), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vcvtps2ph_xmm_xmm_imm8.k b/semantics/immediateInstructions/vcvtps2ph_xmm_xmm_imm8.k index 4fea4a289..d67bd86eb 100644 --- a/semantics/immediateInstructions/vcvtps2ph_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vcvtps2ph_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VCVTPS2PH-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vcvtps2ph Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vcvtps2ph Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(192, 0), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 128, 160), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 160, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 192, 224), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8)))))) +convToRegKeys(R3) |-> concatenateMInt( mi(192, 0), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 128, 160), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 160, 192), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 192, 224), Imm8), cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), Imm8))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vcvtps2ph_xmm_ymm_imm8.k b/semantics/immediateInstructions/vcvtps2ph_xmm_ymm_imm8.k index 8634980c7..1260fd796 100644 --- a/semantics/immediateInstructions/vcvtps2ph_xmm_ymm_imm8.k +++ b/semantics/immediateInstructions/vcvtps2ph_xmm_ymm_imm8.k @@ -5,14 +5,15 @@ module VCVTPS2PH-XMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vcvtps2ph Imm8:Imm, R2:Ymm, R3:Xmm, .Operands) => . + execinstr (vcvtps2ph Imm8:MInt, R2:Ymm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 0, 32), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 32, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 64, 96), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 96, 128), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 128, 160), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 160, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 192, 224), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8)))))))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 0, 32), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 32, 64), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 64, 96), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 96, 128), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 128, 160), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 160, 192), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 192, 224), Imm8), cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 224, 256), Imm8))))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vdppd_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vdppd_xmm_xmm_xmm_imm8.k index 7643dd596..2bdf3f065 100644 --- a/semantics/immediateInstructions/vdppd_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vdppd_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VDPPD-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vdppd Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vdppd Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( getParentValue(R2, RSMap), 128, 192)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( getParentValue(R2, RSMap), 128, 192)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( getParentValue(R2, RSMap), 128, 192)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( getParentValue(R2, RSMap), 128, 192)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vdpps_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vdpps_xmm_xmm_xmm_imm8.k index 84d86ff46..eae75de42 100644 --- a/semantics/immediateInstructions/vdpps_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vdpps_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VDPPS-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vdpps Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vdpps Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vdpps_ymm_ymm_ymm_imm8.k b/semantics/immediateInstructions/vdpps_ymm_ymm_ymm_imm8.k index cf31908f8..c75495cc8 100644 --- a/semantics/immediateInstructions/vdpps_ymm_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vdpps_ymm_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VDPPS-YMM-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vdpps Imm8:Imm, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . + execinstr (vdpps Imm8:MInt, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( getParentValue(R2, RSMap), 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( getParentValue(R2, RSMap), 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( getParentValue(R2, RSMap), 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( getParentValue(R2, RSMap), 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( getParentValue(R2, RSMap), 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( getParentValue(R2, RSMap), 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( getParentValue(R2, RSMap), 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( getParentValue(R2, RSMap), 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( getParentValue(R2, RSMap), 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( getParentValue(R2, RSMap), 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( getParentValue(R2, RSMap), 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( getParentValue(R2, RSMap), 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( getParentValue(R2, RSMap), 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( getParentValue(R2, RSMap), 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( getParentValue(R2, RSMap), 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( getParentValue(R2, RSMap), 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi))) +convToRegKeys(R4) |-> concatenateMInt( concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( getParentValue(R2, RSMap), 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( getParentValue(R2, RSMap), 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( getParentValue(R2, RSMap), 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( getParentValue(R2, RSMap), 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( getParentValue(R2, RSMap), 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( getParentValue(R2, RSMap), 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( getParentValue(R2, RSMap), 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( getParentValue(R2, RSMap), 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( getParentValue(R2, RSMap), 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( getParentValue(R2, RSMap), 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( getParentValue(R2, RSMap), 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( getParentValue(R2, RSMap), 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( getParentValue(R2, RSMap), 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( getParentValue(R2, RSMap), 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( getParentValue(R2, RSMap), 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( getParentValue(R2, RSMap), 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vextractf128_xmm_ymm_imm8.k b/semantics/immediateInstructions/vextractf128_xmm_ymm_imm8.k index ee009d9cc..ca0a85a25 100644 --- a/semantics/immediateInstructions/vextractf128_xmm_ymm_imm8.k +++ b/semantics/immediateInstructions/vextractf128_xmm_ymm_imm8.k @@ -5,14 +5,15 @@ module VEXTRACTF128-XMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vextractf128 Imm8:Imm, R2:Ymm, R3:Xmm, .Operands) => . + execinstr (vextractf128 Imm8:MInt, R2:Ymm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else extractMInt( getParentValue(R3, RSMap), 0, 128) #fi)) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else extractMInt( getParentValue(R3, RSMap), 0, 128) #fi)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vextracti128_xmm_ymm_imm8.k b/semantics/immediateInstructions/vextracti128_xmm_ymm_imm8.k index e2413f804..423412316 100644 --- a/semantics/immediateInstructions/vextracti128_xmm_ymm_imm8.k +++ b/semantics/immediateInstructions/vextracti128_xmm_ymm_imm8.k @@ -5,14 +5,15 @@ module VEXTRACTI128-XMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vextracti128 Imm8:Imm, R2:Ymm, R3:Xmm, .Operands) => . + execinstr (vextracti128 Imm8:MInt, R2:Ymm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else extractMInt( getParentValue(R3, RSMap), 0, 128) #fi)) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else extractMInt( getParentValue(R3, RSMap), 0, 128) #fi)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vextractps_r32_xmm_imm8.k b/semantics/immediateInstructions/vextractps_r32_xmm_imm8.k index 33b73fa68..c2449f05c 100644 --- a/semantics/immediateInstructions/vextractps_r32_xmm_imm8.k +++ b/semantics/immediateInstructions/vextractps_r32_xmm_imm8.k @@ -5,14 +5,15 @@ module VEXTRACTPS-R32-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vextractps Imm8:Imm, R2:Xmm, R3:R32, .Operands) => . + execinstr (vextractps Imm8:MInt, R2:Xmm, R3:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128)) +convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vinsertf128_ymm_ymm_xmm_imm8.k b/semantics/immediateInstructions/vinsertf128_ymm_ymm_xmm_imm8.k index f5b7f8f85..9974c3c3d 100644 --- a/semantics/immediateInstructions/vinsertf128_ymm_ymm_xmm_imm8.k +++ b/semantics/immediateInstructions/vinsertf128_ymm_ymm_xmm_imm8.k @@ -5,14 +5,15 @@ module VINSERTF128-YMM-YMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vinsertf128 Imm8:Imm, R2:Xmm, R3:Ymm, R4:Ymm, .Operands) => . + execinstr (vinsertf128 Imm8:MInt, R2:Xmm, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), extractMInt( getParentValue(R2, RSMap), 128, 256)) #else concatenateMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), extractMInt( getParentValue(R3, RSMap), 128, 256)) #fi) +convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), extractMInt( getParentValue(R2, RSMap), 128, 256)) #else concatenateMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), extractMInt( getParentValue(R3, RSMap), 128, 256)) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vinserti128_ymm_ymm_xmm_imm8.k b/semantics/immediateInstructions/vinserti128_ymm_ymm_xmm_imm8.k index f036b5da0..5164dbda5 100644 --- a/semantics/immediateInstructions/vinserti128_ymm_ymm_xmm_imm8.k +++ b/semantics/immediateInstructions/vinserti128_ymm_ymm_xmm_imm8.k @@ -5,14 +5,15 @@ module VINSERTI128-YMM-YMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vinserti128 Imm8:Imm, R2:Xmm, R3:Ymm, R4:Ymm, .Operands) => . + execinstr (vinserti128 Imm8:MInt, R2:Xmm, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), extractMInt( getParentValue(R2, RSMap), 128, 256)) #else concatenateMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), extractMInt( getParentValue(R3, RSMap), 128, 256)) #fi) +convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), extractMInt( getParentValue(R2, RSMap), 128, 256)) #else concatenateMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), extractMInt( getParentValue(R3, RSMap), 128, 256)) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vinsertps_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vinsertps_xmm_xmm_xmm_imm8.k index c21683704..59d10863a 100644 --- a/semantics/immediateInstructions/vinsertps_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vinsertps_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VINSERTPS-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vinsertps Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vinsertps Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #fi) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #else extractMInt( getParentValue(R3, RSMap), 160, 192) #fi) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #fi) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #else extractMInt( getParentValue(R3, RSMap), 160, 192) #fi) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vmpsadbw_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vmpsadbw_xmm_xmm_xmm_imm8.k index 46056ab72..23adeda1e 100644 --- a/semantics/immediateInstructions/vmpsadbw_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vmpsadbw_xmm_xmm_xmm_imm8.k @@ -4,43 +4,44 @@ module VMPSADBW-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vmpsadbw Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vmpsadbw Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => execinstr (vmpsadbw selectSliceMPSAD(getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 7 , 0 ), + extractMInt(Imm8, 6, 8), 7 , 0 ), selectSliceMPSAD(getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 15, 8 ), + extractMInt(Imm8, 6, 8), 15, 8 ), selectSliceMPSAD(getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 23, 16), + extractMInt(Imm8, 6, 8), 23, 16), selectSliceMPSAD(getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 31, 24), + extractMInt(Imm8, 6, 8), 31, 24), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 7 , 0), + extractMInt(Imm8, 5, 6), 7 , 0), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 15, 8), + extractMInt(Imm8, 5, 6), 15, 8), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 23, 16), + extractMInt(Imm8, 5, 6), 23, 16), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 31, 24), + extractMInt(Imm8, 5, 6), 31, 24), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 39, 32), + extractMInt(Imm8, 5, 6), 39, 32), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 47, 40), + extractMInt(Imm8, 5, 6), 47, 40), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 55, 48), + extractMInt(Imm8, 5, 6), 55, 48), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 63, 56), + extractMInt(Imm8, 5, 6), 63, 56), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 71, 64), + extractMInt(Imm8, 5, 6), 71, 64), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 79, 72), + extractMInt(Imm8, 5, 6), 79, 72), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 87, 80), + extractMInt(Imm8, 5, 6), 87, 80), R4:Xmm, .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (vmpsadbw diff --git a/semantics/immediateInstructions/vmpsadbw_ymm_ymm_ymm_imm8.k b/semantics/immediateInstructions/vmpsadbw_ymm_ymm_ymm_imm8.k index 18783c715..4939338ef 100644 --- a/semantics/immediateInstructions/vmpsadbw_ymm_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vmpsadbw_ymm_ymm_ymm_imm8.k @@ -5,93 +5,94 @@ module VMPSADBW-YMM-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vmpsadbw Imm8:Imm, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vmpsadbw Imm8:MInt, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => execinstr (vmpsadbw //Low slices selectSliceMPSAD(getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 7 , 0 ), + extractMInt(Imm8, 6, 8), 7 , 0 ), selectSliceMPSAD(getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 15, 8 ), + extractMInt(Imm8, 6, 8), 15, 8 ), selectSliceMPSAD(getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 23, 16), + extractMInt(Imm8, 6, 8), 23, 16), selectSliceMPSAD(getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 31, 24), + extractMInt(Imm8, 6, 8), 31, 24), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 7 , 0), + extractMInt(Imm8, 5, 6), 7 , 0), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 15, 8), + extractMInt(Imm8, 5, 6), 15, 8), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 23, 16), + extractMInt(Imm8, 5, 6), 23, 16), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 31, 24), + extractMInt(Imm8, 5, 6), 31, 24), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 39, 32), + extractMInt(Imm8, 5, 6), 39, 32), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 47, 40), + extractMInt(Imm8, 5, 6), 47, 40), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 55, 48), + extractMInt(Imm8, 5, 6), 55, 48), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 63, 56), + extractMInt(Imm8, 5, 6), 63, 56), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 71, 64), + extractMInt(Imm8, 5, 6), 71, 64), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 79, 72), + extractMInt(Imm8, 5, 6), 79, 72), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 87, 80), + extractMInt(Imm8, 5, 6), 87, 80), //High slices selectSliceMPSAD( getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 3, 5), 7 +Int + extractMInt(Imm8, 3, 5), 7 +Int 128, 0 +Int 128), selectSliceMPSAD( getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 3, 5), 15+Int + extractMInt(Imm8, 3, 5), 15+Int 128, 8 +Int 128), selectSliceMPSAD( getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 3, 5), 23+Int + extractMInt(Imm8, 3, 5), 23+Int 128, 16+Int 128), selectSliceMPSAD( getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 3, 5), 31+Int + extractMInt(Imm8, 3, 5), 31+Int 128, 24+Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 7 + extractMInt(Imm8, 2, 3), 7 +Int 128, 0 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 15 + extractMInt(Imm8, 2, 3), 15 +Int 128, 8 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 23 + extractMInt(Imm8, 2, 3), 23 +Int 128, 16 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 31 + extractMInt(Imm8, 2, 3), 31 +Int 128, 24 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 39 + extractMInt(Imm8, 2, 3), 39 +Int 128, 32 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 47 + extractMInt(Imm8, 2, 3), 47 +Int 128, 40 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 55 + extractMInt(Imm8, 2, 3), 55 +Int 128, 48 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 63 + extractMInt(Imm8, 2, 3), 63 +Int 128, 56 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 71 + extractMInt(Imm8, 2, 3), 71 +Int 128, 64 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 79 + extractMInt(Imm8, 2, 3), 79 +Int 128, 72 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 87 + extractMInt(Imm8, 2, 3), 87 +Int 128, 80 +Int 128), R4:Ymm, .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule diff --git a/semantics/immediateInstructions/vpalignr_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpalignr_xmm_xmm_xmm_imm8.k index f11895469..9e104f62b 100644 --- a/semantics/immediateInstructions/vpalignr_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpalignr_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPALIGNR-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpalignr Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vpalignr Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), extractMInt( getParentValue(R2, RSMap), 128, 256)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), uvalueMInt(mi(256, 3))))), 128, 256)) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), extractMInt( getParentValue(R2, RSMap), 128, 256)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), Imm8), uvalueMInt(mi(256, 3))))), 128, 256)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpalignr_ymm_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpalignr_ymm_ymm_ymm_imm8.k index f07e6a747..5bbc52a69 100644 --- a/semantics/immediateInstructions/vpalignr_ymm_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpalignr_ymm_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPALIGNR-YMM-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpalignr Imm8:Imm, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . + execinstr (vpalignr Imm8:MInt, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), extractMInt( getParentValue(R2, RSMap), 0, 128)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), uvalueMInt(mi(256, 3))))), 128, 256), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), extractMInt( getParentValue(R2, RSMap), 128, 256)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), uvalueMInt(mi(256, 3))))), 128, 256)) +convToRegKeys(R4) |-> concatenateMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), extractMInt( getParentValue(R2, RSMap), 0, 128)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), Imm8), uvalueMInt(mi(256, 3))))), 128, 256), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), extractMInt( getParentValue(R2, RSMap), 128, 256)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), Imm8), uvalueMInt(mi(256, 3))))), 128, 256)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpblendd_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpblendd_xmm_xmm_xmm_imm8.k index 43916d914..0a41f0c2b 100644 --- a/semantics/immediateInstructions/vpblendd_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpblendd_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPBLENDD-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpblendd Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vpblendd Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 160, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 160, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpblendd_ymm_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpblendd_ymm_ymm_ymm_imm8.k index 1d2114725..a126c731d 100644 --- a/semantics/immediateInstructions/vpblendd_ymm_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpblendd_ymm_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPBLENDD-YMM-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpblendd Imm8:Imm, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . + execinstr (vpblendd Imm8:MInt, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( getParentValue(R2, RSMap), 0, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 32, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 96) #else extractMInt( getParentValue(R2, RSMap), 64, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 96, 128) #else extractMInt( getParentValue(R2, RSMap), 96, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 160, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi)))))))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( getParentValue(R2, RSMap), 0, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 32, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 96) #else extractMInt( getParentValue(R2, RSMap), 64, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 96, 128) #else extractMInt( getParentValue(R2, RSMap), 96, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 160, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpblendw_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpblendw_xmm_xmm_xmm_imm8.k index b57e01ea0..5f7d8143f 100644 --- a/semantics/immediateInstructions/vpblendw_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpblendw_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPBLENDW-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpblendw Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vpblendw Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 144) #else extractMInt( getParentValue(R2, RSMap), 128, 144) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 144, 160) #else extractMInt( getParentValue(R2, RSMap), 144, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 176) #else extractMInt( getParentValue(R2, RSMap), 160, 176) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 176, 192) #else extractMInt( getParentValue(R2, RSMap), 176, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 208) #else extractMInt( getParentValue(R2, RSMap), 192, 208) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 208, 224) #else extractMInt( getParentValue(R2, RSMap), 208, 224) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 240) #else extractMInt( getParentValue(R2, RSMap), 224, 240) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 240, 256) #else extractMInt( getParentValue(R2, RSMap), 240, 256) #fi))))))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 144) #else extractMInt( getParentValue(R2, RSMap), 128, 144) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 144, 160) #else extractMInt( getParentValue(R2, RSMap), 144, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 176) #else extractMInt( getParentValue(R2, RSMap), 160, 176) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 176, 192) #else extractMInt( getParentValue(R2, RSMap), 176, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 208) #else extractMInt( getParentValue(R2, RSMap), 192, 208) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 208, 224) #else extractMInt( getParentValue(R2, RSMap), 208, 224) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 240) #else extractMInt( getParentValue(R2, RSMap), 224, 240) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 240, 256) #else extractMInt( getParentValue(R2, RSMap), 240, 256) #fi))))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpblendw_ymm_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpblendw_ymm_ymm_ymm_imm8.k index f92d32b14..e706ad81c 100644 --- a/semantics/immediateInstructions/vpblendw_ymm_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpblendw_ymm_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPBLENDW-YMM-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpblendw Imm8:Imm, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . + execinstr (vpblendw Imm8:MInt, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 16) #else extractMInt( getParentValue(R2, RSMap), 0, 16) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 16, 32) #else extractMInt( getParentValue(R2, RSMap), 16, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 32, 48) #else extractMInt( getParentValue(R2, RSMap), 32, 48) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 48, 64) #else extractMInt( getParentValue(R2, RSMap), 48, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 80) #else extractMInt( getParentValue(R2, RSMap), 64, 80) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 80, 96) #else extractMInt( getParentValue(R2, RSMap), 80, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 96, 112) #else extractMInt( getParentValue(R2, RSMap), 96, 112) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 112, 128) #else extractMInt( getParentValue(R2, RSMap), 112, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 144) #else extractMInt( getParentValue(R2, RSMap), 128, 144) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 144, 160) #else extractMInt( getParentValue(R2, RSMap), 144, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 176) #else extractMInt( getParentValue(R2, RSMap), 160, 176) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 176, 192) #else extractMInt( getParentValue(R2, RSMap), 176, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 208) #else extractMInt( getParentValue(R2, RSMap), 192, 208) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 208, 224) #else extractMInt( getParentValue(R2, RSMap), 208, 224) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 240) #else extractMInt( getParentValue(R2, RSMap), 224, 240) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 240, 256) #else extractMInt( getParentValue(R2, RSMap), 240, 256) #fi)))))))))))))))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 16) #else extractMInt( getParentValue(R2, RSMap), 0, 16) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 16, 32) #else extractMInt( getParentValue(R2, RSMap), 16, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 32, 48) #else extractMInt( getParentValue(R2, RSMap), 32, 48) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 48, 64) #else extractMInt( getParentValue(R2, RSMap), 48, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 80) #else extractMInt( getParentValue(R2, RSMap), 64, 80) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 80, 96) #else extractMInt( getParentValue(R2, RSMap), 80, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 96, 112) #else extractMInt( getParentValue(R2, RSMap), 96, 112) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 112, 128) #else extractMInt( getParentValue(R2, RSMap), 112, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 144) #else extractMInt( getParentValue(R2, RSMap), 128, 144) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 144, 160) #else extractMInt( getParentValue(R2, RSMap), 144, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 176) #else extractMInt( getParentValue(R2, RSMap), 160, 176) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 176, 192) #else extractMInt( getParentValue(R2, RSMap), 176, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 208) #else extractMInt( getParentValue(R2, RSMap), 192, 208) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 208, 224) #else extractMInt( getParentValue(R2, RSMap), 208, 224) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 240) #else extractMInt( getParentValue(R2, RSMap), 224, 240) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 240, 256) #else extractMInt( getParentValue(R2, RSMap), 240, 256) #fi)))))))))))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpclmulqdq_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpclmulqdq_xmm_xmm_xmm_imm8.k index 87678aeda..5f21aeeea 100644 --- a/semantics/immediateInstructions/vpclmulqdq_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpclmulqdq_xmm_xmm_xmm_imm8.k @@ -18,15 +18,14 @@ module VPCLMULQDQ-XMM-XMM-XMM-IMM8 TEMP2←SRC2 [127:64]; */ rule - execinstr (vpclmulqdq Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vpclmulqdq Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => execinstr(vpclmulqdq - selectSlice(getRegisterValue(R3, RSMap), handleImmediateWithSignExtend(Imm8, - 8, 8), 7, 64, 0), - selectSlice(getRegisterValue(R2, RSMap), handleImmediateWithSignExtend(Imm8, - 8, 8), 3, 64, 0), R4 + selectSlice(getRegisterValue(R3, RSMap), Imm8, 7, 64, 0), + selectSlice(getRegisterValue(R2, RSMap), Imm8, 3, 64, 0), R4 , .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (vpclmulqdq TEMP1:MInt, TEMP2:MInt, R4:Xmm, .Operands) => diff --git a/semantics/immediateInstructions/vpcmpestri_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpcmpestri_xmm_xmm_imm8.k index ecd631f0b..4efbc5984 100644 --- a/semantics/immediateInstructions/vpcmpestri_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpcmpestri_xmm_xmm_imm8.k @@ -6,16 +6,17 @@ module VPCMPESTRI-XMM-XMM-IMM8 // Find Limit Index rule - execinstr (vpcmpestri Imm8:Imm, Xmm2:Xmm, Xmm1:Xmm, .Operands) => + execinstr (vpcmpestri Imm8:MInt, Xmm2:Xmm, Xmm1:Xmm, .Operands) => execinstr (vpcmpestri - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, getRegisterValue(Xmm2, RSMap), getRegisterValue(Xmm1, RSMap), - findLimitIndexE(getRegisterValue(Xmm2, RSMap), getRegisterValue(%rdx, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexE(getRegisterValue(Xmm2, RSMap), getRegisterValue(%rdx, RSMap), Imm8), + findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // Find data size and interpretation rule diff --git a/semantics/immediateInstructions/vpcmpestrm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpcmpestrm_xmm_xmm_imm8.k index 49ea51ba3..dbc5620db 100644 --- a/semantics/immediateInstructions/vpcmpestrm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpcmpestrm_xmm_xmm_imm8.k @@ -6,16 +6,17 @@ module VPCMPESTRM-XMM-XMM-IMM8 // Find Limit Index rule - execinstr (vpcmpestrm Imm8:Imm, Xmm2:Xmm, Xmm1:Xmm, .Operands) => + execinstr (vpcmpestrm Imm8:MInt, Xmm2:Xmm, Xmm1:Xmm, .Operands) => execinstr (vpcmpestrm - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, getRegisterValue(Xmm2, RSMap), getRegisterValue(Xmm1, RSMap), - findLimitIndexE(getRegisterValue(Xmm2, RSMap), getRegisterValue(%rdx, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexE(getRegisterValue(Xmm2, RSMap), getRegisterValue(%rdx, RSMap), Imm8), + findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // Find data size and interpretation rule diff --git a/semantics/immediateInstructions/vpcmpistri_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpcmpistri_xmm_xmm_imm8.k index 01874f9fc..9adee87ad 100644 --- a/semantics/immediateInstructions/vpcmpistri_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpcmpistri_xmm_xmm_imm8.k @@ -6,16 +6,17 @@ module VPCMPISTRI-XMM-XMM-IMM8 // Find Limit Index rule - execinstr (vpcmpistri Imm8:Imm, Xmm2:Xmm, Xmm1:Xmm, .Operands) => + execinstr (vpcmpistri Imm8:MInt, Xmm2:Xmm, Xmm1:Xmm, .Operands) => execinstr (vpcmpistri - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, getRegisterValue(Xmm2, RSMap), getRegisterValue(Xmm1, RSMap), - findLimitIndexI(getRegisterValue(Xmm2, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexI(getRegisterValue(Xmm1, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexI(getRegisterValue(Xmm2, RSMap), Imm8), + findLimitIndexI(getRegisterValue(Xmm1, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // Find data size and interpretation rule diff --git a/semantics/immediateInstructions/vpcmpistrm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpcmpistrm_xmm_xmm_imm8.k index bb05a5a7d..fcfb65b8e 100644 --- a/semantics/immediateInstructions/vpcmpistrm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpcmpistrm_xmm_xmm_imm8.k @@ -6,16 +6,17 @@ module VPCMPISTRM-XMM-XMM-IMM8 // Find Limit Index rule - execinstr (vpcmpistrm Imm8:Imm, Xmm2:Xmm, Xmm1:Xmm, .Operands) => + execinstr (vpcmpistrm Imm8:MInt, Xmm2:Xmm, Xmm1:Xmm, .Operands) => execinstr (vpcmpistrm - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, getRegisterValue(Xmm2, RSMap), getRegisterValue(Xmm1, RSMap), - findLimitIndexI(getRegisterValue(Xmm2, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexI(getRegisterValue(Xmm1, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexI(getRegisterValue(Xmm2, RSMap), Imm8), + findLimitIndexI(getRegisterValue(Xmm1, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // Find data size and interpretation rule diff --git a/semantics/immediateInstructions/vperm2f128_ymm_ymm_ymm_imm8.k b/semantics/immediateInstructions/vperm2f128_ymm_ymm_ymm_imm8.k index 4c940b72c..1d22f5046 100644 --- a/semantics/immediateInstructions/vperm2f128_ymm_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vperm2f128_ymm_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPERM2F128-YMM-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vperm2f128 Imm8:Imm, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . + execinstr (vperm2f128 Imm8:MInt, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi)) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi), mi(128, 0)) #else concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi)) #fi) #fi) +convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi)) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi), mi(128, 0)) #else concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi)) #fi) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vperm2i128_ymm_ymm_ymm_imm8.k b/semantics/immediateInstructions/vperm2i128_ymm_ymm_ymm_imm8.k index b9a4907eb..40fd4a6c3 100644 --- a/semantics/immediateInstructions/vperm2i128_ymm_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vperm2i128_ymm_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPERM2I128-YMM-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vperm2i128 Imm8:Imm, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . + execinstr (vperm2i128 Imm8:MInt, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi)) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi), mi(128, 0)) #else concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi)) #fi) #fi) +convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi)) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi), mi(128, 0)) #else concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi)) #fi) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpermilpd_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpermilpd_xmm_xmm_imm8.k index c441f5301..e0fb6fd6f 100644 --- a/semantics/immediateInstructions/vpermilpd_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpermilpd_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPERMILPD-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpermilpd Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vpermilpd Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 192, 256) #else extractMInt( getParentValue(R2, RSMap), 128, 192) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 192, 256) #else extractMInt( getParentValue(R2, RSMap), 128, 192) #fi))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 192, 256) #else extractMInt( getParentValue(R2, RSMap), 128, 192) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 192, 256) #else extractMInt( getParentValue(R2, RSMap), 128, 192) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpermilpd_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpermilpd_ymm_ymm_imm8.k index 07ca15d3e..6651aa31b 100644 --- a/semantics/immediateInstructions/vpermilpd_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpermilpd_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPERMILPD-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpermilpd Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpermilpd Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 64, 128) #else extractMInt( getParentValue(R2, RSMap), 0, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 64, 128) #else extractMInt( getParentValue(R2, RSMap), 0, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 192, 256) #else extractMInt( getParentValue(R2, RSMap), 128, 192) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 192, 256) #else extractMInt( getParentValue(R2, RSMap), 128, 192) #fi)))) +convToRegKeys(R3) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 64, 128) #else extractMInt( getParentValue(R2, RSMap), 0, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 64, 128) #else extractMInt( getParentValue(R2, RSMap), 0, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 192, 256) #else extractMInt( getParentValue(R2, RSMap), 128, 192) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 192, 256) #else extractMInt( getParentValue(R2, RSMap), 128, 192) #fi)))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpermilps_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpermilps_xmm_xmm_imm8.k index 727ac08e7..5a164c79d 100644 --- a/semantics/immediateInstructions/vpermilps_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpermilps_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPERMILPS-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpermilps Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vpermilps Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpermilps_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpermilps_ymm_ymm_imm8.k index 8b3adeadc..3abae2dcc 100644 --- a/semantics/immediateInstructions/vpermilps_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpermilps_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPERMILPS-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpermilps Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpermilps Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 96, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 64, 96) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 96, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 64, 96) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 96, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 64, 96) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 96, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 64, 96) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi)))))))) +convToRegKeys(R3) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 96, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 64, 96) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 96, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 64, 96) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 96, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 64, 96) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 96, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 64, 96) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpermpd_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpermpd_ymm_ymm_imm8.k index b5e96219c..606dcc5c5 100644 --- a/semantics/immediateInstructions/vpermpd_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpermpd_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPERMPD-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpermpd Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpermpd Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(256, 6))))), 192, 256), extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(256, 6))))), 192, 256)))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(256, 6))))), 192, 256), extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(256, 6))))), 192, 256)))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpermq_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpermq_ymm_ymm_imm8.k index 3fe351a2a..1232ef014 100644 --- a/semantics/immediateInstructions/vpermq_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpermq_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPERMQ-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpermq Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpermq Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(256, 6))))), 192, 256), extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(256, 6))))), 192, 256)))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(256, 6))))), 192, 256), extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(256, 6))))), 192, 256)))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpextrb_r32_xmm_imm8.k b/semantics/immediateInstructions/vpextrb_r32_xmm_imm8.k index 35ecc3140..0524d2b45 100644 --- a/semantics/immediateInstructions/vpextrb_r32_xmm_imm8.k +++ b/semantics/immediateInstructions/vpextrb_r32_xmm_imm8.k @@ -5,14 +5,15 @@ module VPEXTRB-R32-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpextrb Imm8:Imm, R2:Xmm, R3:R32, .Operands) => . + execinstr (vpextrb Imm8:MInt, R2:Xmm, R3:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(56, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3))))), 120, 128)) +convToRegKeys(R3) |-> concatenateMInt( mi(56, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3))))), 120, 128)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpextrb_r64_xmm_imm8.k b/semantics/immediateInstructions/vpextrb_r64_xmm_imm8.k index a2ca89da4..40228395e 100644 --- a/semantics/immediateInstructions/vpextrb_r64_xmm_imm8.k +++ b/semantics/immediateInstructions/vpextrb_r64_xmm_imm8.k @@ -5,14 +5,15 @@ module VPEXTRB-R64-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpextrb Imm8:Imm, R2:Xmm, R3:R64, .Operands) => . + execinstr (vpextrb Imm8:MInt, R2:Xmm, R3:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(56, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3))))), 120, 128)) +convToRegKeys(R3) |-> concatenateMInt( mi(56, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3))))), 120, 128)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpextrd_r32_xmm_imm8.k b/semantics/immediateInstructions/vpextrd_r32_xmm_imm8.k index f0fda9e43..a81b794de 100644 --- a/semantics/immediateInstructions/vpextrd_r32_xmm_imm8.k +++ b/semantics/immediateInstructions/vpextrd_r32_xmm_imm8.k @@ -5,14 +5,15 @@ module VPEXTRD-R32-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpextrd Imm8:Imm, R2:Xmm, R3:R32, .Operands) => . + execinstr (vpextrd Imm8:MInt, R2:Xmm, R3:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128)) +convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpextrq_r64_xmm_imm8.k b/semantics/immediateInstructions/vpextrq_r64_xmm_imm8.k index ce49e9beb..5c4b560c7 100644 --- a/semantics/immediateInstructions/vpextrq_r64_xmm_imm8.k +++ b/semantics/immediateInstructions/vpextrq_r64_xmm_imm8.k @@ -5,14 +5,15 @@ module VPEXTRQ-R64-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpextrq Imm8:Imm, R2:Xmm, R3:R64, .Operands) => . + execinstr (vpextrq Imm8:MInt, R2:Xmm, R3:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6))))), 64, 128) +convToRegKeys(R3) |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6))))), 64, 128) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpextrw_r32_xmm_imm8.k b/semantics/immediateInstructions/vpextrw_r32_xmm_imm8.k index 259dfa487..63146196c 100644 --- a/semantics/immediateInstructions/vpextrw_r32_xmm_imm8.k +++ b/semantics/immediateInstructions/vpextrw_r32_xmm_imm8.k @@ -5,14 +5,15 @@ module VPEXTRW-R32-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpextrw Imm8:Imm, R2:Xmm, R3:R32, .Operands) => . + execinstr (vpextrw Imm8:MInt, R2:Xmm, R3:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(48, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4))))), 112, 128)) +convToRegKeys(R3) |-> concatenateMInt( mi(48, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4))))), 112, 128)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpextrw_r64_xmm_imm8.k b/semantics/immediateInstructions/vpextrw_r64_xmm_imm8.k index 5440cfd4e..e657e5e58 100644 --- a/semantics/immediateInstructions/vpextrw_r64_xmm_imm8.k +++ b/semantics/immediateInstructions/vpextrw_r64_xmm_imm8.k @@ -5,14 +5,15 @@ module VPEXTRW-R64-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpextrw Imm8:Imm, R2:Xmm, R3:R64, .Operands) => . + execinstr (vpextrw Imm8:MInt, R2:Xmm, R3:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(48, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4))))), 112, 128)) +convToRegKeys(R3) |-> concatenateMInt( mi(48, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4))))), 112, 128)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpinsrb_xmm_xmm_r32_imm8.k b/semantics/immediateInstructions/vpinsrb_xmm_xmm_r32_imm8.k index d26e5998c..e721c9609 100644 --- a/semantics/immediateInstructions/vpinsrb_xmm_xmm_r32_imm8.k +++ b/semantics/immediateInstructions/vpinsrb_xmm_xmm_r32_imm8.k @@ -5,14 +5,15 @@ module VPINSRB-XMM-XMM-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (vpinsrb Imm8:Imm, R2:R32, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vpinsrb Imm8:MInt, R2:R32, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3))))), shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3)))))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3))))), shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpinsrd_xmm_xmm_r32_imm8.k b/semantics/immediateInstructions/vpinsrd_xmm_xmm_r32_imm8.k index 3f23f16c6..418d8fc0b 100644 --- a/semantics/immediateInstructions/vpinsrd_xmm_xmm_r32_imm8.k +++ b/semantics/immediateInstructions/vpinsrd_xmm_xmm_r32_imm8.k @@ -5,14 +5,15 @@ module VPINSRD-XMM-XMM-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (vpinsrd Imm8:Imm, R2:R32, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vpinsrd Imm8:MInt, R2:R32, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5)))))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpinsrq_xmm_xmm_r64_imm8.k b/semantics/immediateInstructions/vpinsrq_xmm_xmm_r64_imm8.k index f3960b7c0..46fc1dc36 100644 --- a/semantics/immediateInstructions/vpinsrq_xmm_xmm_r64_imm8.k +++ b/semantics/immediateInstructions/vpinsrq_xmm_xmm_r64_imm8.k @@ -5,14 +5,15 @@ module VPINSRQ-XMM-XMM-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (vpinsrq Imm8:Imm, R2:R64, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vpinsrq Imm8:MInt, R2:R64, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(64, 0), getParentValue(R2, RSMap)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6))))), shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6)))))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(64, 0), getParentValue(R2, RSMap)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6))))), shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpinsrw_xmm_xmm_r32_imm8.k b/semantics/immediateInstructions/vpinsrw_xmm_xmm_r32_imm8.k index 31194b38f..c6cf508d8 100644 --- a/semantics/immediateInstructions/vpinsrw_xmm_xmm_r32_imm8.k +++ b/semantics/immediateInstructions/vpinsrw_xmm_xmm_r32_imm8.k @@ -5,14 +5,15 @@ module VPINSRW-XMM-XMM-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (vpinsrw Imm8:Imm, R2:R32, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vpinsrw Imm8:MInt, R2:R32, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4))))), shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4)))))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4))))), shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpshufd_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpshufd_xmm_xmm_imm8.k index 3472952e6..50fceb521 100644 --- a/semantics/immediateInstructions/vpshufd_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpshufd_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPSHUFD-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpshufd Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vpshufd Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpshufd_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpshufd_ymm_ymm_imm8.k index be4fe86ec..e04937d7d 100644 --- a/semantics/immediateInstructions/vpshufd_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpshufd_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPSHUFD-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpshufd Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpshufd Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128)))))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpshufhw_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpshufhw_xmm_xmm_imm8.k index d5fab0cf4..abe2a617d 100644 --- a/semantics/immediateInstructions/vpshufhw_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpshufhw_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPSHUFHW-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpshufhw Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vpshufhw Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 4))))), 48, 64), extractMInt( getParentValue(R2, RSMap), 192, 256)))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 4))))), 48, 64), extractMInt( getParentValue(R2, RSMap), 192, 256)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpshufhw_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpshufhw_ymm_ymm_imm8.k index d6e51ede8..d07b65afd 100644 --- a/semantics/immediateInstructions/vpshufhw_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpshufhw_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPSHUFHW-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpshufhw Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpshufhw Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( getParentValue(R2, RSMap), 64, 128), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(256, 4))))), 176, 192), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(256, 4))))), 176, 192), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(256, 4))))), 176, 192), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(256, 4))))), 176, 192), extractMInt( getParentValue(R2, RSMap), 192, 256)))))))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( getParentValue(R2, RSMap), 64, 128), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(256, 4))))), 176, 192), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(256, 4))))), 176, 192), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(256, 4))))), 176, 192), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(256, 4))))), 176, 192), extractMInt( getParentValue(R2, RSMap), 192, 256)))))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpshuflw_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpshuflw_xmm_xmm_imm8.k index 01bbf9e9e..3f9d64295 100644 --- a/semantics/immediateInstructions/vpshuflw_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpshuflw_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPSHUFLW-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpshuflw Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vpshuflw Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 4))))), 112, 128), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 4))))), 112, 128)))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 4))))), 112, 128), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 4))))), 112, 128)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpshuflw_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpshuflw_ymm_ymm_imm8.k index 399ccf9e8..94c3b26da 100644 --- a/semantics/immediateInstructions/vpshuflw_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpshuflw_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPSHUFLW-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpshuflw Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpshuflw Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 64), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(256, 4))))), 240, 256), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(256, 4))))), 240, 256), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(256, 4))))), 240, 256), extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(256, 4))))), 240, 256)))))))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 64), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(256, 4))))), 240, 256), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(256, 4))))), 240, 256), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(256, 4))))), 240, 256), extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(256, 4))))), 240, 256)))))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpslld_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpslld_xmm_xmm_imm8.k index 0416825d9..4f658a82d 100644 --- a/semantics/immediateInstructions/vpslld_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpslld_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPSLLD-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpslld Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vpslld Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))))))) #fi) +convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))))))) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpslld_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpslld_ymm_ymm_imm8.k index 5b56fa543..97f28fe8f 100644 --- a/semantics/immediateInstructions/vpslld_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpslld_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPSLLD-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpslld Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpslld Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(256, 0) #else concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 0, 32), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 64, 96), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 96, 128), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8))))))))))) #fi) +convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(256, 0) #else concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 0, 32), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 64, 96), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 96, 128), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt(concatenateMInt( mi(24, 0), Imm8)))))))))) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpslldq_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpslldq_xmm_xmm_imm8.k index 1e838d7c9..81cadc725 100644 --- a/semantics/immediateInstructions/vpslldq_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpslldq_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPSLLDQ-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpslldq Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vpslldq Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), uvalueMInt(mi(128, 3)))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( Imm8, mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), Imm8) #fi), uvalueMInt(mi(128, 3)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpslldq_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpslldq_ymm_ymm_imm8.k index e0009cadf..a43d3df54 100644 --- a/semantics/immediateInstructions/vpslldq_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpslldq_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPSLLDQ-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpslldq Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpslldq Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), uvalueMInt(mi(128, 3))))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), uvalueMInt(mi(128, 3)))))) +convToRegKeys(R3) |-> concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( Imm8, mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), Imm8) #fi), uvalueMInt(mi(128, 3))))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( Imm8, mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), Imm8) #fi), uvalueMInt(mi(128, 3)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsllq_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpsllq_xmm_xmm_imm8.k index e68b60273..d9e9e3493 100644 --- a/semantics/immediateInstructions/vpsllq_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpsllq_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPSLLQ-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsllq Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vpsllq Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 63)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 256), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))))) #fi) +convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 63)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), uvalueMInt(concatenateMInt( mi(56, 0), Imm8))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 256), uvalueMInt(concatenateMInt( mi(56, 0), Imm8))))) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsllq_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpsllq_ymm_ymm_imm8.k index 286cd7035..44c5bda6f 100644 --- a/semantics/immediateInstructions/vpsllq_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpsllq_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPSLLQ-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsllq Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpsllq Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 63)) #then mi(256, 0) #else concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 0, 64), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 64, 128), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 256), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8))))))) #fi) +convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 63)) #then mi(256, 0) #else concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 0, 64), uvalueMInt(concatenateMInt( mi(56, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 64, 128), uvalueMInt(concatenateMInt( mi(56, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), uvalueMInt(concatenateMInt( mi(56, 0), Imm8))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 256), uvalueMInt(concatenateMInt( mi(56, 0), Imm8)))))) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsllw_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpsllw_xmm_xmm_imm8.k index 0b59f484b..50ec2c8de 100644 --- a/semantics/immediateInstructions/vpsllw_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpsllw_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPSLLW-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsllw Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vpsllw Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))))))))))) #fi) +convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))))))))))) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsllw_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpsllw_ymm_ymm_imm8.k index 3fb79d024..437973add 100644 --- a/semantics/immediateInstructions/vpsllw_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpsllw_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPSLLW-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsllw Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpsllw Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(256, 0) #else concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 0, 16), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 16, 32), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 32, 48), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 64, 80), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 80, 96), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 96, 112), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 112, 128), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8))))))))))))))))))) #fi) +convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(256, 0) #else concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 0, 16), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 16, 32), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 32, 48), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 64, 80), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 80, 96), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 96, 112), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 112, 128), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt(concatenateMInt( mi(8, 0), Imm8)))))))))))))))))) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsrad_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpsrad_xmm_xmm_imm8.k index f0a77bc5d..1d2635672 100644 --- a/semantics/immediateInstructions/vpsrad_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpsrad_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPSRAD-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsrad Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vpsrad Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi))), aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsrad_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpsrad_ymm_ymm_imm8.k index 7b635e65b..f99b84776 100644 --- a/semantics/immediateInstructions/vpsrad_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpsrad_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPSRAD-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsrad Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpsrad Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 0, 32), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 64, 96), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 96, 128), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi)))))))))) +convToRegKeys(R3) |-> concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 0, 32), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 64, 96), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 96, 128), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi))), aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi)))))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsraw_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpsraw_xmm_xmm_imm8.k index 045c6f45b..7f20cbf0d 100644 --- a/semantics/immediateInstructions/vpsraw_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpsraw_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPSRAW-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsraw Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vpsraw Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))))))))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))))))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsraw_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpsraw_ymm_ymm_imm8.k index 175af874e..0e7743c82 100644 --- a/semantics/immediateInstructions/vpsraw_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpsraw_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPSRAW-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsraw Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpsraw Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 0, 16), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 16, 32), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 32, 48), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 64, 80), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 80, 96), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 96, 112), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 112, 128), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi)))))))))))))))))) +convToRegKeys(R3) |-> concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 0, 16), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 16, 32), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 32, 48), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 64, 80), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 80, 96), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 96, 112), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 112, 128), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi)))))))))))))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsrld_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpsrld_xmm_xmm_imm8.k index 15da742b1..2a39b8f50 100644 --- a/semantics/immediateInstructions/vpsrld_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpsrld_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPSRLD-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsrld Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vpsrld Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))))))) #fi) +convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))))))) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsrld_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpsrld_ymm_ymm_imm8.k index 72a349d0f..978b933b9 100644 --- a/semantics/immediateInstructions/vpsrld_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpsrld_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPSRLD-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsrld Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpsrld Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(256, 0) #else concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 32), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 64, 96), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 96, 128), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8))))))))))) #fi) +convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(256, 0) #else concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 32), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 64, 96), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 96, 128), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt(concatenateMInt( mi(24, 0), Imm8)))))))))) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsrldq_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpsrldq_xmm_xmm_imm8.k index 4fff94a26..694d609ba 100644 --- a/semantics/immediateInstructions/vpsrldq_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpsrldq_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPSRLDQ-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsrldq Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vpsrldq Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), uvalueMInt(mi(128, 3)))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( Imm8, mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), Imm8) #fi), uvalueMInt(mi(128, 3)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsrldq_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpsrldq_ymm_ymm_imm8.k index 1c84a8358..5b96863c9 100644 --- a/semantics/immediateInstructions/vpsrldq_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpsrldq_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPSRLDQ-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsrldq Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpsrldq Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), uvalueMInt(mi(128, 3))))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), uvalueMInt(mi(128, 3)))))) +convToRegKeys(R3) |-> concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( Imm8, mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), Imm8) #fi), uvalueMInt(mi(128, 3))))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( Imm8, mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), Imm8) #fi), uvalueMInt(mi(128, 3)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsrlq_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpsrlq_xmm_xmm_imm8.k index a9f028f37..e939ba5fb 100644 --- a/semantics/immediateInstructions/vpsrlq_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpsrlq_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPSRLQ-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsrlq Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vpsrlq Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 63)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 256), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))))) #fi) +convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 63)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), uvalueMInt(concatenateMInt( mi(56, 0), Imm8))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 256), uvalueMInt(concatenateMInt( mi(56, 0), Imm8))))) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsrlq_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpsrlq_ymm_ymm_imm8.k index dc8e3143c..e17bbf1b4 100644 --- a/semantics/immediateInstructions/vpsrlq_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpsrlq_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPSRLQ-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsrlq Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpsrlq Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 63)) #then mi(256, 0) #else concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 64), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 64, 128), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 256), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8))))))) #fi) +convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 63)) #then mi(256, 0) #else concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 64), uvalueMInt(concatenateMInt( mi(56, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 64, 128), uvalueMInt(concatenateMInt( mi(56, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), uvalueMInt(concatenateMInt( mi(56, 0), Imm8))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 256), uvalueMInt(concatenateMInt( mi(56, 0), Imm8)))))) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsrlw_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpsrlw_xmm_xmm_imm8.k index feaac5ed6..fdfc88fc9 100644 --- a/semantics/immediateInstructions/vpsrlw_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpsrlw_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPSRLW-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsrlw Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vpsrlw Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))))))))))) #fi) +convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))))))))))) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsrlw_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpsrlw_ymm_ymm_imm8.k index 468b8c297..895e2511d 100644 --- a/semantics/immediateInstructions/vpsrlw_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpsrlw_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPSRLW-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsrlw Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpsrlw Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(256, 0) #else concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 16), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 16, 32), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 32, 48), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 64, 80), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 80, 96), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 96, 112), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 112, 128), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8))))))))))))))))))) #fi) +convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(256, 0) #else concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 16), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 16, 32), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 32, 48), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 64, 80), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 80, 96), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 96, 112), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 112, 128), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt(concatenateMInt( mi(8, 0), Imm8)))))))))))))))))) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vroundpd_xmm_xmm_imm8.k b/semantics/immediateInstructions/vroundpd_xmm_xmm_imm8.k index 050188897..db640f24d 100644 --- a/semantics/immediateInstructions/vroundpd_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vroundpd_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VROUNDPD-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vroundpd Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vroundpd Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 128, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 192, 256), handleImmediateWithSignExtend(Imm8, 8, 8)))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 128, 192), Imm8), cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 192, 256), Imm8))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vroundpd_ymm_ymm_imm8.k b/semantics/immediateInstructions/vroundpd_ymm_ymm_imm8.k index 482e8f7d6..12b0c8742 100644 --- a/semantics/immediateInstructions/vroundpd_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vroundpd_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VROUNDPD-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vroundpd Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vroundpd Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 0, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 64, 128), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 128, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 192, 256), handleImmediateWithSignExtend(Imm8, 8, 8))))) +convToRegKeys(R3) |-> concatenateMInt( cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 0, 64), Imm8), concatenateMInt( cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 64, 128), Imm8), concatenateMInt( cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 128, 192), Imm8), cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 192, 256), Imm8)))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vroundps_xmm_xmm_imm8.k b/semantics/immediateInstructions/vroundps_xmm_xmm_imm8.k index 42d2190ce..9d699c753 100644 --- a/semantics/immediateInstructions/vroundps_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vroundps_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VROUNDPS-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vroundps Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vroundps Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 128, 160), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 160, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 192, 224), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8)))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 128, 160), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 160, 192), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 192, 224), Imm8), cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), Imm8))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vroundps_ymm_ymm_imm8.k b/semantics/immediateInstructions/vroundps_ymm_ymm_imm8.k index 72063c856..368824159 100644 --- a/semantics/immediateInstructions/vroundps_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vroundps_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VROUNDPS-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vroundps Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vroundps Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 0, 32), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 32, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 64, 96), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 96, 128), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 128, 160), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 160, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 192, 224), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8))))))))) +convToRegKeys(R3) |-> concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 0, 32), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 32, 64), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 64, 96), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 96, 128), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 128, 160), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 160, 192), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 192, 224), Imm8), cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), Imm8)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vroundsd_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vroundsd_xmm_xmm_xmm_imm8.k index 7d492fc1b..57adaac82 100644 --- a/semantics/immediateInstructions/vroundsd_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vroundsd_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VROUNDSD-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vroundsd Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vroundsd Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 192), cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 192, 256), handleImmediateWithSignExtend(Imm8, 8, 8)))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 192), cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 192, 256), Imm8))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vroundss_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vroundss_xmm_xmm_xmm_imm8.k index a6db9c2ce..ebbc20f6a 100644 --- a/semantics/immediateInstructions/vroundss_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vroundss_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VROUNDSS-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vroundss Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vroundss Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 224), cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8)))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 224), cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), Imm8))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vshufpd_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vshufpd_xmm_xmm_xmm_imm8.k index 329f78599..997df08cc 100644 --- a/semantics/immediateInstructions/vshufpd_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vshufpd_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VSHUFPD-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vshufpd Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vshufpd Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 192) #else extractMInt( getParentValue(R2, RSMap), 192, 256) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R3, RSMap), 192, 256) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 192) #else extractMInt( getParentValue(R2, RSMap), 192, 256) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R3, RSMap), 192, 256) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vshufpd_ymm_ymm_ymm_imm8.k b/semantics/immediateInstructions/vshufpd_ymm_ymm_ymm_imm8.k index 1ce14cee5..3460a1480 100644 --- a/semantics/immediateInstructions/vshufpd_ymm_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vshufpd_ymm_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VSHUFPD-YMM-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vshufpd Imm8:Imm, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . + execinstr (vshufpd Imm8:MInt, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 0, 64) #else extractMInt( getParentValue(R2, RSMap), 64, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 64) #else extractMInt( getParentValue(R3, RSMap), 64, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 192) #else extractMInt( getParentValue(R2, RSMap), 192, 256) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R3, RSMap), 192, 256) #fi)))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 0, 64) #else extractMInt( getParentValue(R2, RSMap), 64, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 64) #else extractMInt( getParentValue(R3, RSMap), 64, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 192) #else extractMInt( getParentValue(R2, RSMap), 192, 256) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R3, RSMap), 192, 256) #fi)))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vshufps_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vshufps_xmm_xmm_xmm_imm8.k index 3a944fb06..ca649b4cd 100644 --- a/semantics/immediateInstructions/vshufps_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vshufps_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VSHUFPS-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vshufps Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vshufps Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vshufps_ymm_ymm_ymm_imm8.k b/semantics/immediateInstructions/vshufps_ymm_ymm_ymm_imm8.k index 30a23256e..38a41a71d 100644 --- a/semantics/immediateInstructions/vshufps_ymm_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vshufps_ymm_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VSHUFPS-YMM-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vshufps Imm8:Imm, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . + execinstr (vshufps Imm8:MInt, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 0, 32) #else extractMInt( getParentValue(R2, RSMap), 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 0, 32) #else extractMInt( getParentValue(R2, RSMap), 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( getParentValue(R3, RSMap), 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( getParentValue(R3, RSMap), 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( getParentValue(R3, RSMap), 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( getParentValue(R3, RSMap), 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi)))))))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 0, 32) #else extractMInt( getParentValue(R2, RSMap), 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 0, 32) #else extractMInt( getParentValue(R2, RSMap), 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( getParentValue(R3, RSMap), 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( getParentValue(R3, RSMap), 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( getParentValue(R3, RSMap), 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( getParentValue(R3, RSMap), 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/xorb_al_imm8.k b/semantics/immediateInstructions/xorb_al_imm8.k index 0af254597..1018d6075 100644 --- a/semantics/immediateInstructions/xorb_al_imm8.k +++ b/semantics/immediateInstructions/xorb_al_imm8.k @@ -5,26 +5,27 @@ module XORB-AL-IMM8 imports X86-CONFIGURATION rule - execinstr (xorb Imm8:Imm, %al, .Operands) => . + execinstr (xorb Imm8:MInt, %al, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 56), xorMInt( extractMInt( getParentValue(%rax, RSMap), 56, 64), handleImmediateWithSignExtend(Imm8, 8, 8))) +"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 56), xorMInt( extractMInt( getParentValue(%rax, RSMap), 56, 64), Imm8)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 56, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 56, 64), Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> xorMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/xorb_r8_imm8.k b/semantics/immediateInstructions/xorb_r8_imm8.k index ec7753259..eae9a2526 100644 --- a/semantics/immediateInstructions/xorb_r8_imm8.k +++ b/semantics/immediateInstructions/xorb_r8_imm8.k @@ -5,26 +5,27 @@ module XORB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (xorb Imm8:Imm, R2:R8, .Operands) => . + execinstr (xorb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), handleImmediateWithSignExtend(Imm8, 8, 8))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), Imm8)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/xorb_rh_imm8.k b/semantics/immediateInstructions/xorb_rh_imm8.k index a9a3ea477..19c5fe0e3 100644 --- a/semantics/immediateInstructions/xorb_rh_imm8.k +++ b/semantics/immediateInstructions/xorb_rh_imm8.k @@ -5,26 +5,27 @@ module XORB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (xorb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (xorb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), handleImmediateWithSignExtend(Imm8, 8, 8))), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), Imm8)), extractMInt( getParentValue(R2, RSMap), 56, 64)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 55, 56), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 54, 55), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 53, 54), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 52, 53), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 51, 52), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 50, 51), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 49, 50), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 55, 56), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 54, 55), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 53, 54), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 52, 53), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 51, 52), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 50, 51), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 49, 50), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/xorl_eax_imm32.k b/semantics/immediateInstructions/xorl_eax_imm32.k index dc84f2486..1feaf1add 100644 --- a/semantics/immediateInstructions/xorl_eax_imm32.k +++ b/semantics/immediateInstructions/xorl_eax_imm32.k @@ -5,26 +5,27 @@ module XORL-EAX-IMM32 imports X86-CONFIGURATION rule - execinstr (xorl Imm32:Imm, %eax, .Operands) => . + execinstr (xorl Imm32:MInt, %eax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( mi(32, 0), xorMInt( extractMInt( getParentValue(%rax, RSMap), 32, 64), handleImmediateWithSignExtend(Imm32, 32, 32))) +"RAX" |-> concatenateMInt( mi(32, 0), xorMInt( extractMInt( getParentValue(%rax, RSMap), 32, 64), Imm32)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 32, 64), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 32, 64), Imm32), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)) +"SF" |-> xorMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), extractMInt( Imm32, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/xorl_r32_imm32.k b/semantics/immediateInstructions/xorl_r32_imm32.k index 8e127eefa..f279404c0 100644 --- a/semantics/immediateInstructions/xorl_r32_imm32.k +++ b/semantics/immediateInstructions/xorl_r32_imm32.k @@ -5,26 +5,27 @@ module XORL-R32-IMM32 imports X86-CONFIGURATION rule - execinstr (xorl Imm32:Imm, R2:R32, .Operands) => . + execinstr (xorl Imm32:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), xorMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), handleImmediateWithSignExtend(Imm32, 32, 32))) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), xorMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), Imm32)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), Imm32), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)) +"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), extractMInt( Imm32, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/xorl_r32_imm8.k b/semantics/immediateInstructions/xorl_r32_imm8.k index aa2031d02..5cf1b3a09 100644 --- a/semantics/immediateInstructions/xorl_r32_imm8.k +++ b/semantics/immediateInstructions/xorl_r32_imm8.k @@ -5,26 +5,27 @@ module XORL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (xorl Imm8:Imm, R2:R32, .Operands) => . + execinstr (xorl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), xorMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), xorMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, svalueMInt(Imm8)))) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, svalueMInt(Imm8))), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/xorq_r64_imm32.k b/semantics/immediateInstructions/xorq_r64_imm32.k index f70089ca8..f9e3547b8 100644 --- a/semantics/immediateInstructions/xorq_r64_imm32.k +++ b/semantics/immediateInstructions/xorq_r64_imm32.k @@ -5,26 +5,27 @@ module XORQ-R64-IMM32 imports X86-CONFIGURATION rule - execinstr (xorq Imm32:Imm, R2:R64, .Operands) => . + execinstr (xorq Imm32:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> xorMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) +convToRegKeys(R2) |-> xorMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(Imm32))) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(Imm32))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)) +"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/xorq_r64_imm8.k b/semantics/immediateInstructions/xorq_r64_imm8.k index 62f739c12..63a2c5565 100644 --- a/semantics/immediateInstructions/xorq_r64_imm8.k +++ b/semantics/immediateInstructions/xorq_r64_imm8.k @@ -5,26 +5,27 @@ module XORQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (xorq Imm8:Imm, R2:R64, .Operands) => . + execinstr (xorq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> xorMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) +convToRegKeys(R2) |-> xorMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(Imm8))) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(Imm8))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/xorq_rax_imm32.k b/semantics/immediateInstructions/xorq_rax_imm32.k index 3a645ba0b..48229bb94 100644 --- a/semantics/immediateInstructions/xorq_rax_imm32.k +++ b/semantics/immediateInstructions/xorq_rax_imm32.k @@ -5,26 +5,27 @@ module XORQ-RAX-IMM32 imports X86-CONFIGURATION rule - execinstr (xorq Imm32:Imm, %rax, .Operands) => . + execinstr (xorq Imm32:MInt, %rax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> xorMInt( getParentValue(%rax, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) +"RAX" |-> xorMInt( getParentValue(%rax, RSMap), mi(64, svalueMInt(Imm32))) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( getParentValue(%rax, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( getParentValue(%rax, RSMap), mi(64, svalueMInt(Imm32))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)) +"SF" |-> xorMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/xorw_ax_imm16.k b/semantics/immediateInstructions/xorw_ax_imm16.k index c5e109e8d..054d767ef 100644 --- a/semantics/immediateInstructions/xorw_ax_imm16.k +++ b/semantics/immediateInstructions/xorw_ax_imm16.k @@ -5,26 +5,27 @@ module XORW-AX-IMM16 imports X86-CONFIGURATION rule - execinstr (xorw Imm16:Imm, %ax, .Operands) => . + execinstr (xorw Imm16:MInt, %ax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 48), xorMInt( extractMInt( getParentValue(%rax, RSMap), 48, 64), handleImmediateWithSignExtend(Imm16, 16, 16))) +"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 48), xorMInt( extractMInt( getParentValue(%rax, RSMap), 48, 64), Imm16)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 15, 16)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 14, 15)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 13, 14)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 12, 13)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 10, 11)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 9, 10)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm16, 15, 16)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm16, 14, 15)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm16, 13, 14)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm16, 12, 13)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm16, 11, 12)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm16, 10, 11)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm16, 9, 10)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm16, 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 48, 64), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 48, 64), Imm16), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)) +"SF" |-> xorMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), extractMInt( Imm16, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/xorw_r16_imm16.k b/semantics/immediateInstructions/xorw_r16_imm16.k index fcd512cc9..b66317629 100644 --- a/semantics/immediateInstructions/xorw_r16_imm16.k +++ b/semantics/immediateInstructions/xorw_r16_imm16.k @@ -5,26 +5,27 @@ module XORW-R16-IMM16 imports X86-CONFIGURATION rule - execinstr (xorw Imm16:Imm, R2:R16, .Operands) => . + execinstr (xorw Imm16:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), handleImmediateWithSignExtend(Imm16, 16, 16))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), Imm16)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 15, 16)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 14, 15)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 13, 14)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 12, 13)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 10, 11)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 9, 10)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm16, 15, 16)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm16, 14, 15)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm16, 13, 14)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm16, 12, 13)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm16, 11, 12)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm16, 10, 11)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm16, 9, 10)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm16, 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), Imm16), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)) +"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( Imm16, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/xorw_r16_imm8.k b/semantics/immediateInstructions/xorw_r16_imm8.k index 2c9571a15..010dad89a 100644 --- a/semantics/immediateInstructions/xorw_r16_imm8.k +++ b/semantics/immediateInstructions/xorw_r16_imm8.k @@ -5,26 +5,27 @@ module XORW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (xorw Imm8:Imm, R2:R16, .Operands) => . + execinstr (xorw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(16, svalueMInt(Imm8)))) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(16, svalueMInt(Imm8))), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/adcb_m8_imm8.k b/semantics/memoryInstructions/adcb_m8_imm8.k index 5e7da5cb1..aeb2b1e6a 100644 --- a/semantics/memoryInstructions/adcb_m8_imm8.k +++ b/semantics/memoryInstructions/adcb_m8_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ADCB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(adcb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(adcb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (adcb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (adcb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (adcb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (adcb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (adcb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 9), + extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 9), MemOff, 8 ) @@ -25,17 +26,18 @@ module ADCB-M8-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), Mem8)), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), Mem8)), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), Mem8)), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), Mem8)), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), Mem8)), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), Mem8)), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), Mem8)), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), Mem8)), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), Mem8)), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), Mem8)), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), Mem8)), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), Mem8)), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), Mem8)), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), Mem8)), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), Mem8)), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), Mem8)), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem8, 3, 4)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), Mem8)), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem8, 3, 4)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), Mem8)), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem8, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem8, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/adcl_m32_imm32.k b/semantics/memoryInstructions/adcl_m32_imm32.k index aba9f1336..59969d39c 100644 --- a/semantics/memoryInstructions/adcl_m32_imm32.k +++ b/semantics/memoryInstructions/adcl_m32_imm32.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ADCL-M32-IMM32 imports X86-CONFIGURATION - context execinstr(adcl:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(adcl:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (adcl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (adcl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (adcl Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (adcl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (adcl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), + extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), MemOff, 32 ) @@ -25,17 +26,18 @@ module ADCL-M32-IMM32 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), Mem32)), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), Mem32)), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm32, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm32, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/adcl_m32_imm8.k b/semantics/memoryInstructions/adcl_m32_imm8.k index df520b7c7..75b1baffd 100644 --- a/semantics/memoryInstructions/adcl_m32_imm8.k +++ b/semantics/memoryInstructions/adcl_m32_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ADCL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(adcl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(adcl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (adcl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (adcl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (adcl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (adcl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (adcl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), + extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), MemOff, 32 ) @@ -25,17 +26,18 @@ module ADCL-M32-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem32)), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem32)), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/adcq_m64_imm32.k b/semantics/memoryInstructions/adcq_m64_imm32.k index a9231fbd6..4114ab313 100644 --- a/semantics/memoryInstructions/adcq_m64_imm32.k +++ b/semantics/memoryInstructions/adcq_m64_imm32.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ADCQ-M64-IMM32 imports X86-CONFIGURATION - context execinstr(adcq:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(adcq:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (adcq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (adcq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (adcq Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (adcq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (adcq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), + extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), MemOff, 64 ) @@ -25,17 +26,18 @@ module ADCQ-M64-IMM32 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), Mem64)), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/adcq_m64_imm8.k b/semantics/memoryInstructions/adcq_m64_imm8.k index 19d1c3614..ebe1b2d1b 100644 --- a/semantics/memoryInstructions/adcq_m64_imm8.k +++ b/semantics/memoryInstructions/adcq_m64_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ADCQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(adcq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(adcq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (adcq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (adcq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (adcq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (adcq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (adcq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), + extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), MemOff, 64 ) @@ -25,17 +26,18 @@ module ADCQ-M64-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem64)), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/adcw_m16_imm16.k b/semantics/memoryInstructions/adcw_m16_imm16.k index 7d42ab352..06bb87e88 100644 --- a/semantics/memoryInstructions/adcw_m16_imm16.k +++ b/semantics/memoryInstructions/adcw_m16_imm16.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ADCW-M16-IMM16 imports X86-CONFIGURATION - context execinstr(adcw:Opcode Imm16:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(adcw:Opcode Imm16:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (adcw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (adcw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (adcw Imm16, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm16) ==Int 16 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (adcw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (adcw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), + extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), MemOff, 16 ) @@ -25,17 +26,18 @@ module ADCW-M16-IMM16 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), Mem16)), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), Mem16)), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm16, 11, 12), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm16, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm16, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/memoryInstructions/adcw_m16_imm8.k b/semantics/memoryInstructions/adcw_m16_imm8.k index b665e40e5..619f4a481 100644 --- a/semantics/memoryInstructions/adcw_m16_imm8.k +++ b/semantics/memoryInstructions/adcw_m16_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ADCW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(adcw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(adcw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (adcw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (adcw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (adcw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (adcw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (adcw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), + extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), MemOff, 16 ) @@ -25,17 +26,18 @@ module ADCW-M16-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem16)), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem16)), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/addb_m8_imm8.k b/semantics/memoryInstructions/addb_m8_imm8.k index 95b1b0027..34879efa5 100644 --- a/semantics/memoryInstructions/addb_m8_imm8.k +++ b/semantics/memoryInstructions/addb_m8_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ADDB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(addb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(addb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (addb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (addb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (addb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (addb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (addb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), Mem8)), 1, 9), + extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), Mem8)), 1, 9), MemOff, 8 ) @@ -25,17 +26,18 @@ module ADDB-M8-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), Mem8)), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), Mem8)), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), Mem8)), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), Mem8)), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), Mem8)), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), Mem8)), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), Mem8)), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), Mem8)), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), Mem8)), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), Mem8)), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), Mem8)), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), Mem8)), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), Mem8)), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), Mem8)), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), Mem8)), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), Mem8)), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem8, 3, 4)), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), Mem8)), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem8, 3, 4)), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), Mem8)), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), Mem8)), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), Mem8)), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), Mem8)), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), Mem8)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem8, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem8, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/addl_m32_imm32.k b/semantics/memoryInstructions/addl_m32_imm32.k index 028c9ad0d..52363d96b 100644 --- a/semantics/memoryInstructions/addl_m32_imm32.k +++ b/semantics/memoryInstructions/addl_m32_imm32.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ADDL-M32-IMM32 imports X86-CONFIGURATION - context execinstr(addl:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(addl:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (addl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (addl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (addl Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (addl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (addl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), Mem32)), 1, 33), + extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), Mem32)), 1, 33), MemOff, 32 ) @@ -25,17 +26,18 @@ module ADDL-M32-IMM32 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), Mem32)), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), Mem32)), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), Mem32)), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), Mem32)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm32, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm32, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/addl_m32_imm8.k b/semantics/memoryInstructions/addl_m32_imm8.k index aecf5b636..0ef6c6e3b 100644 --- a/semantics/memoryInstructions/addl_m32_imm8.k +++ b/semantics/memoryInstructions/addl_m32_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ADDL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(addl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(addl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (addl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (addl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (addl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (addl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (addl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem32)), 1, 33), + extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem32)), 1, 33), MemOff, 32 ) @@ -25,17 +26,18 @@ module ADDL-M32-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem32)), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem32)), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem32)), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem32)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/addq_m64_imm32.k b/semantics/memoryInstructions/addq_m64_imm32.k index 88d7d7eca..bb7500194 100644 --- a/semantics/memoryInstructions/addq_m64_imm32.k +++ b/semantics/memoryInstructions/addq_m64_imm32.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ADDQ-M64-IMM32 imports X86-CONFIGURATION - context execinstr(addq:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(addq:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (addq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (addq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (addq Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (addq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (addq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), Mem64)), 1, 65), + extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), Mem64)), 1, 65), MemOff, 64 ) @@ -25,17 +26,18 @@ module ADDQ-M64-IMM32 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), Mem64)), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), Mem64)), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), Mem64)), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), Mem64)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/addq_m64_imm8.k b/semantics/memoryInstructions/addq_m64_imm8.k index 878771cb0..71c47e1ad 100644 --- a/semantics/memoryInstructions/addq_m64_imm8.k +++ b/semantics/memoryInstructions/addq_m64_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ADDQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(addq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(addq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (addq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (addq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (addq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (addq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (addq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem64)), 1, 65), + extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem64)), 1, 65), MemOff, 64 ) @@ -25,17 +26,18 @@ module ADDQ-M64-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem64)), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem64)), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem64)), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem64)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/addw_m16_imm16.k b/semantics/memoryInstructions/addw_m16_imm16.k index c25bfea41..a9f6efd35 100644 --- a/semantics/memoryInstructions/addw_m16_imm16.k +++ b/semantics/memoryInstructions/addw_m16_imm16.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ADDW-M16-IMM16 imports X86-CONFIGURATION - context execinstr(addw:Opcode Imm16:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(addw:Opcode Imm16:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (addw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (addw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (addw Imm16, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm16) ==Int 16 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (addw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (addw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), Mem16)), 1, 17), + extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), Mem16)), 1, 17), MemOff, 16 ) @@ -25,17 +26,18 @@ module ADDW-M16-IMM16 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), Mem16)), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), Mem16)), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm16, 11, 12), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), Mem16)), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), Mem16)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm16, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm16, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/memoryInstructions/addw_m16_imm8.k b/semantics/memoryInstructions/addw_m16_imm8.k index b4e762107..f794ce67e 100644 --- a/semantics/memoryInstructions/addw_m16_imm8.k +++ b/semantics/memoryInstructions/addw_m16_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ADDW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(addw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(addw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (addw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (addw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (addw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (addw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (addw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem16)), 1, 17), + extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem16)), 1, 17), MemOff, 16 ) @@ -25,17 +26,18 @@ module ADDW-M16-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem16)), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem16)), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem16)), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem16)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/andb_m8_imm8.k b/semantics/memoryInstructions/andb_m8_imm8.k index 4d8477121..773d06975 100644 --- a/semantics/memoryInstructions/andb_m8_imm8.k +++ b/semantics/memoryInstructions/andb_m8_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ANDB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(andb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(andb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (andb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (andb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (andb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (andb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (andb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - andMInt( Mem8, handleImmediateWithSignExtend(Imm8, 8, 8)), + andMInt( Mem8, Imm8), MemOff, 8 ) @@ -27,15 +28,16 @@ module ANDB-M8-IMM8 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem8, 7, 8), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem8, 6, 7), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 5, 6), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 4, 5), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 3, 4), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 2, 3), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 1, 2), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem8, 7, 8), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem8, 6, 7), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 5, 6), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 4, 5), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 3, 4), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 2, 3), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 1, 2), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 0, 1), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( Mem8, handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( Mem8, Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( Mem8, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> andMInt( extractMInt( Mem8, 0, 1), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/andl_m32_imm32.k b/semantics/memoryInstructions/andl_m32_imm32.k index 3db2f3670..43bb2a437 100644 --- a/semantics/memoryInstructions/andl_m32_imm32.k +++ b/semantics/memoryInstructions/andl_m32_imm32.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ANDL-M32-IMM32 imports X86-CONFIGURATION - context execinstr(andl:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(andl:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (andl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (andl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (andl Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (andl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (andl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - andMInt( Mem32, handleImmediateWithSignExtend(Imm32, 32, 32)), + andMInt( Mem32, Imm32), MemOff, 32 ) @@ -27,15 +28,16 @@ module ANDL-M32-IMM32 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem32, 31, 32), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem32, 30, 31), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 29, 30), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 28, 29), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 27, 28), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 26, 27), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 25, 26), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 24, 25), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem32, 31, 32), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem32, 30, 31), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 29, 30), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 28, 29), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 27, 28), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 26, 27), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 25, 26), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 24, 25), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( Mem32, handleImmediateWithSignExtend(Imm32, 32, 32)), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( Mem32, Imm32), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( Mem32, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)) +"SF" |-> andMInt( extractMInt( Mem32, 0, 1), extractMInt( Imm32, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/andl_m32_imm8.k b/semantics/memoryInstructions/andl_m32_imm8.k index 7456a323c..74bff59dd 100644 --- a/semantics/memoryInstructions/andl_m32_imm8.k +++ b/semantics/memoryInstructions/andl_m32_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ANDL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(andl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(andl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (andl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (andl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (andl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (andl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (andl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - andMInt( Mem32, mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), + andMInt( Mem32, mi(32, svalueMInt(Imm8))), MemOff, 32 ) @@ -27,15 +28,16 @@ module ANDL-M32-IMM8 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem32, 31, 32), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem32, 30, 31), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 29, 30), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 28, 29), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 27, 28), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 26, 27), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 25, 26), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 24, 25), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem32, 31, 32), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem32, 30, 31), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 29, 30), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 28, 29), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 27, 28), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 26, 27), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 25, 26), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 24, 25), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( Mem32, mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( Mem32, mi(32, svalueMInt(Imm8))), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( Mem32, 0, 1), extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> andMInt( extractMInt( Mem32, 0, 1), extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/andq_m64_imm32.k b/semantics/memoryInstructions/andq_m64_imm32.k index 9cde4fc91..363c9d58f 100644 --- a/semantics/memoryInstructions/andq_m64_imm32.k +++ b/semantics/memoryInstructions/andq_m64_imm32.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ANDQ-M64-IMM32 imports X86-CONFIGURATION - context execinstr(andq:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(andq:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (andq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (andq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (andq Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (andq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (andq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - andMInt( Mem64, mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), + andMInt( Mem64, mi(64, svalueMInt(Imm32))), MemOff, 64 ) @@ -27,15 +28,16 @@ module ANDQ-M64-IMM32 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem64, 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem64, 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem64, 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem64, 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( Mem64, mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( Mem64, mi(64, svalueMInt(Imm32))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( Mem64, 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)) +"SF" |-> andMInt( extractMInt( Mem64, 0, 1), extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/andq_m64_imm8.k b/semantics/memoryInstructions/andq_m64_imm8.k index b6a7c05d6..f1ce252b8 100644 --- a/semantics/memoryInstructions/andq_m64_imm8.k +++ b/semantics/memoryInstructions/andq_m64_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ANDQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(andq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(andq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (andq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (andq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (andq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (andq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (andq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - andMInt( Mem64, mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), + andMInt( Mem64, mi(64, svalueMInt(Imm8))), MemOff, 64 ) @@ -27,15 +28,16 @@ module ANDQ-M64-IMM8 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem64, 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem64, 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem64, 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem64, 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( Mem64, mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( Mem64, mi(64, svalueMInt(Imm8))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( Mem64, 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> andMInt( extractMInt( Mem64, 0, 1), extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/andw_m16_imm16.k b/semantics/memoryInstructions/andw_m16_imm16.k index 8de6251f8..c752696e8 100644 --- a/semantics/memoryInstructions/andw_m16_imm16.k +++ b/semantics/memoryInstructions/andw_m16_imm16.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ANDW-M16-IMM16 imports X86-CONFIGURATION - context execinstr(andw:Opcode Imm16:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(andw:Opcode Imm16:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (andw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (andw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (andw Imm16, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm16) ==Int 16 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (andw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (andw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - andMInt( Mem16, handleImmediateWithSignExtend(Imm16, 16, 16)), + andMInt( Mem16, Imm16), MemOff, 16 ) @@ -27,15 +28,16 @@ module ANDW-M16-IMM16 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem16, 15, 16), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 15, 16)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem16, 14, 15), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 14, 15)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 13, 14), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 13, 14)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 12, 13), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 12, 13)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 11, 12), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 10, 11), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 10, 11)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 9, 10), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 9, 10)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 8, 9), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem16, 15, 16), extractMInt( Imm16, 15, 16)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem16, 14, 15), extractMInt( Imm16, 14, 15)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 13, 14), extractMInt( Imm16, 13, 14)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 12, 13), extractMInt( Imm16, 12, 13)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 11, 12), extractMInt( Imm16, 11, 12)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 10, 11), extractMInt( Imm16, 10, 11)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 9, 10), extractMInt( Imm16, 9, 10)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 8, 9), extractMInt( Imm16, 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( Mem16, handleImmediateWithSignExtend(Imm16, 16, 16)), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( Mem16, Imm16), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( Mem16, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)) +"SF" |-> andMInt( extractMInt( Mem16, 0, 1), extractMInt( Imm16, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/memoryInstructions/andw_m16_imm8.k b/semantics/memoryInstructions/andw_m16_imm8.k index 21ab10b69..7306f6154 100644 --- a/semantics/memoryInstructions/andw_m16_imm8.k +++ b/semantics/memoryInstructions/andw_m16_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ANDW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(andw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(andw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (andw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (andw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (andw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (andw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (andw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - andMInt( Mem16, mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), + andMInt( Mem16, mi(16, svalueMInt(Imm8))), MemOff, 16 ) @@ -27,15 +28,16 @@ module ANDW-M16-IMM8 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem16, 15, 16), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem16, 14, 15), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 13, 14), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 12, 13), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 11, 12), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 10, 11), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 9, 10), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 8, 9), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem16, 15, 16), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem16, 14, 15), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 13, 14), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 12, 13), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 11, 12), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 10, 11), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 9, 10), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 8, 9), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( Mem16, mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( Mem16, mi(16, svalueMInt(Imm8))), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( Mem16, 0, 1), extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> andMInt( extractMInt( Mem16, 0, 1), extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/blendpd_xmm_m128_imm8.k b/semantics/memoryInstructions/blendpd_xmm_m128_imm8.k index 2b4e3e551..7bfcbde9f 100644 --- a/semantics/memoryInstructions/blendpd_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/blendpd_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module BLENDPD-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(blendpd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(blendpd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (blendpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (blendpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (blendpd Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (blendpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (blendpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( Mem128, 0, 64) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 256) #else extractMInt( Mem128, 64, 128) #fi))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( Mem128, 0, 64) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 256) #else extractMInt( Mem128, 64, 128) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/blendps_xmm_m128_imm8.k b/semantics/memoryInstructions/blendps_xmm_m128_imm8.k index 18406df58..0b92507e1 100644 --- a/semantics/memoryInstructions/blendps_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/blendps_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module BLENDPS-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(blendps:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(blendps:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (blendps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (blendps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (blendps Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (blendps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (blendps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( Mem128, 0, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( Mem128, 32, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( Mem128, 64, 96) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( Mem128, 96, 128) #fi))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( Mem128, 0, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( Mem128, 32, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( Mem128, 64, 96) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( Mem128, 96, 128) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/btcl_m32_imm8.k b/semantics/memoryInstructions/btcl_m32_imm8.k index 9b1e17548..db820437a 100644 --- a/semantics/memoryInstructions/btcl_m32_imm8.k +++ b/semantics/memoryInstructions/btcl_m32_imm8.k @@ -4,28 +4,29 @@ requires "x86-configuration.k" module BTCL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(btcl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(btcl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (btcl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => - loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 3)))), 8) ~> + execinstr (btcl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => + loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 3)))), 8) ~> execinstr (btcl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btcl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btcl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - xorMInt( Mem8, shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7)))))), - addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 3)))), + xorMInt( Mem8, shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7)))))), + addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 3)))), 8 ) ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7))))), 7, 8) +"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7))))), 7, 8) "PF" |-> (undefMInt) @@ -36,4 +37,5 @@ module BTCL-M32-IMM8 "OF" |-> (undefMInt) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/btcq_m64_imm8.k b/semantics/memoryInstructions/btcq_m64_imm8.k index 0c16168e9..c8074422c 100644 --- a/semantics/memoryInstructions/btcq_m64_imm8.k +++ b/semantics/memoryInstructions/btcq_m64_imm8.k @@ -4,28 +4,29 @@ requires "x86-configuration.k" module BTCQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(btcq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(btcq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (btcq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => - loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 7)))), 8) ~> + execinstr (btcq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => + loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 7)))), 8) ~> execinstr (btcq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btcq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btcq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - xorMInt( Mem8, shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7)))))), - addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 7)))), + xorMInt( Mem8, shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7)))))), + addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 7)))), 8 ) ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7))))), 7, 8) +"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7))))), 7, 8) "PF" |-> (undefMInt) @@ -36,4 +37,5 @@ module BTCQ-M64-IMM8 "OF" |-> (undefMInt) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/btcw_m16_imm8.k b/semantics/memoryInstructions/btcw_m16_imm8.k index 83d7d4257..610a98bce 100644 --- a/semantics/memoryInstructions/btcw_m16_imm8.k +++ b/semantics/memoryInstructions/btcw_m16_imm8.k @@ -4,28 +4,29 @@ requires "x86-configuration.k" module BTCW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(btcw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(btcw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (btcw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => - loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 1)))), 8) ~> + execinstr (btcw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => + loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 1)))), 8) ~> execinstr (btcw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btcw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btcw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - xorMInt( Mem8, shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7)))))), - addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 1)))), + xorMInt( Mem8, shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7)))))), + addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 1)))), 8 ) ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7))))), 7, 8) +"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7))))), 7, 8) "PF" |-> (undefMInt) @@ -36,4 +37,5 @@ module BTCW-M16-IMM8 "OF" |-> (undefMInt) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/btl_m32_imm8.k b/semantics/memoryInstructions/btl_m32_imm8.k index 5bc2facb9..788990aaf 100644 --- a/semantics/memoryInstructions/btl_m32_imm8.k +++ b/semantics/memoryInstructions/btl_m32_imm8.k @@ -4,22 +4,23 @@ requires "x86-configuration.k" module BTL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(btl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(btl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (btl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => - loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 3)))), 8) ~> + execinstr (btl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => + loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 3)))), 8) ~> execinstr (btl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7))))), 7, 8) +"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7))))), 7, 8) "PF" |-> (undefMInt) @@ -30,4 +31,5 @@ module BTL-M32-IMM8 "OF" |-> (undefMInt) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/btq_m64_imm8.k b/semantics/memoryInstructions/btq_m64_imm8.k index aa5f03472..6e5a81d94 100644 --- a/semantics/memoryInstructions/btq_m64_imm8.k +++ b/semantics/memoryInstructions/btq_m64_imm8.k @@ -4,22 +4,23 @@ requires "x86-configuration.k" module BTQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(btq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(btq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (btq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => - loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 7)))), 8) ~> + execinstr (btq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => + loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 7)))), 8) ~> execinstr (btq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7))))), 7, 8) +"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7))))), 7, 8) "PF" |-> (undefMInt) @@ -30,4 +31,5 @@ module BTQ-M64-IMM8 "OF" |-> (undefMInt) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/btrl_m32_imm8.k b/semantics/memoryInstructions/btrl_m32_imm8.k index b83a0c4b7..4a0d298bd 100644 --- a/semantics/memoryInstructions/btrl_m32_imm8.k +++ b/semantics/memoryInstructions/btrl_m32_imm8.k @@ -4,28 +4,29 @@ requires "x86-configuration.k" module BTRL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(btrl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(btrl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (btrl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => - loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 3)))), 8) ~> + execinstr (btrl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => + loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 3)))), 8) ~> execinstr (btrl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btrl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btrl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - andMInt( Mem8, negMInt( shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7))))))), - addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 3)))), + andMInt( Mem8, negMInt( shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7))))))), + addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 3)))), 8 ) ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7))))), 7, 8) +"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7))))), 7, 8) "PF" |-> (undefMInt) @@ -36,4 +37,5 @@ module BTRL-M32-IMM8 "OF" |-> (undefMInt) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/btrq_m64_imm8.k b/semantics/memoryInstructions/btrq_m64_imm8.k index 28c7f669d..4bebaff18 100644 --- a/semantics/memoryInstructions/btrq_m64_imm8.k +++ b/semantics/memoryInstructions/btrq_m64_imm8.k @@ -4,28 +4,29 @@ requires "x86-configuration.k" module BTRQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(btrq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(btrq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (btrq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => - loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 7)))), 8) ~> + execinstr (btrq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => + loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 7)))), 8) ~> execinstr (btrq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btrq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btrq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - andMInt( Mem8, negMInt( shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7))))))), - addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 7)))), + andMInt( Mem8, negMInt( shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7))))))), + addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 7)))), 8 ) ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7))))), 7, 8) +"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7))))), 7, 8) "PF" |-> (undefMInt) @@ -36,4 +37,5 @@ module BTRQ-M64-IMM8 "OF" |-> (undefMInt) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/btrw_m16_imm8.k b/semantics/memoryInstructions/btrw_m16_imm8.k index 3b46b7ec3..35772e165 100644 --- a/semantics/memoryInstructions/btrw_m16_imm8.k +++ b/semantics/memoryInstructions/btrw_m16_imm8.k @@ -4,28 +4,29 @@ requires "x86-configuration.k" module BTRW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(btrw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(btrw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (btrw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => - loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 1)))), 8) ~> + execinstr (btrw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => + loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 1)))), 8) ~> execinstr (btrw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btrw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btrw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - andMInt( Mem8, negMInt( shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7))))))), - addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 1)))), + andMInt( Mem8, negMInt( shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7))))))), + addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 1)))), 8 ) ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7))))), 7, 8) +"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7))))), 7, 8) "PF" |-> (undefMInt) @@ -36,4 +37,5 @@ module BTRW-M16-IMM8 "OF" |-> (undefMInt) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/btsl_m32_imm8.k b/semantics/memoryInstructions/btsl_m32_imm8.k index f4456f003..e0589bc22 100644 --- a/semantics/memoryInstructions/btsl_m32_imm8.k +++ b/semantics/memoryInstructions/btsl_m32_imm8.k @@ -4,28 +4,29 @@ requires "x86-configuration.k" module BTSL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(btsl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(btsl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (btsl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => - loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 3)))), 8) ~> + execinstr (btsl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => + loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 3)))), 8) ~> execinstr (btsl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btsl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btsl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - orMInt( Mem8, shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7)))))), - addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 3)))), + orMInt( Mem8, shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7)))))), + addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 3)))), 8 ) ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7))))), 7, 8) +"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7))))), 7, 8) "PF" |-> (undefMInt) @@ -36,4 +37,5 @@ module BTSL-M32-IMM8 "OF" |-> (undefMInt) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/btsq_m64_imm8.k b/semantics/memoryInstructions/btsq_m64_imm8.k index 8fc078d34..cb01a0318 100644 --- a/semantics/memoryInstructions/btsq_m64_imm8.k +++ b/semantics/memoryInstructions/btsq_m64_imm8.k @@ -4,28 +4,29 @@ requires "x86-configuration.k" module BTSQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(btsq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(btsq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (btsq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => - loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 7)))), 8) ~> + execinstr (btsq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => + loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 7)))), 8) ~> execinstr (btsq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btsq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btsq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - orMInt( Mem8, shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7)))))), - addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 7)))), + orMInt( Mem8, shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7)))))), + addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 7)))), 8 ) ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7))))), 7, 8) +"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7))))), 7, 8) "PF" |-> (undefMInt) @@ -36,4 +37,5 @@ module BTSQ-M64-IMM8 "OF" |-> (undefMInt) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/btsw_m16_imm8.k b/semantics/memoryInstructions/btsw_m16_imm8.k index 47add1981..f8ba9e111 100644 --- a/semantics/memoryInstructions/btsw_m16_imm8.k +++ b/semantics/memoryInstructions/btsw_m16_imm8.k @@ -4,28 +4,29 @@ requires "x86-configuration.k" module BTSW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(btsw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(btsw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (btsw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => - loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 1)))), 8) ~> + execinstr (btsw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => + loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 1)))), 8) ~> execinstr (btsw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btsw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btsw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - orMInt( Mem8, shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7)))))), - addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 1)))), + orMInt( Mem8, shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7)))))), + addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 1)))), 8 ) ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7))))), 7, 8) +"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7))))), 7, 8) "PF" |-> (undefMInt) @@ -36,4 +37,5 @@ module BTSW-M16-IMM8 "OF" |-> (undefMInt) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/btw_m16_imm8.k b/semantics/memoryInstructions/btw_m16_imm8.k index 7323d7516..c870485a3 100644 --- a/semantics/memoryInstructions/btw_m16_imm8.k +++ b/semantics/memoryInstructions/btw_m16_imm8.k @@ -4,22 +4,23 @@ requires "x86-configuration.k" module BTW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(btw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(btw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (btw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => - loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 1)))), 8) ~> + execinstr (btw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => + loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 1)))), 8) ~> execinstr (btw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7))))), 7, 8) +"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7))))), 7, 8) "PF" |-> (undefMInt) @@ -30,4 +31,5 @@ module BTW-M16-IMM8 "OF" |-> (undefMInt) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/cmpb_m8_imm8.k b/semantics/memoryInstructions/cmpb_m8_imm8.k index 7cd42a343..09fc6df54 100644 --- a/semantics/memoryInstructions/cmpb_m8_imm8.k +++ b/semantics/memoryInstructions/cmpb_m8_imm8.k @@ -4,32 +4,34 @@ requires "x86-configuration.k" module CMPB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(cmpb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(cmpb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (cmpb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (cmpb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (cmpb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (cmpb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (cmpb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem8, 3, 4)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem8, 3, 4)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem8, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem8, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/cmpl_m32_imm32.k b/semantics/memoryInstructions/cmpl_m32_imm32.k index a52295de7..309f2eb41 100644 --- a/semantics/memoryInstructions/cmpl_m32_imm32.k +++ b/semantics/memoryInstructions/cmpl_m32_imm32.k @@ -4,32 +4,34 @@ requires "x86-configuration.k" module CMPL-M32-IMM32 imports X86-CONFIGURATION - context execinstr(cmpl:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(cmpl:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (cmpl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (cmpl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (cmpl Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (cmpl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (cmpl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/cmpl_m32_imm8.k b/semantics/memoryInstructions/cmpl_m32_imm8.k index ad19aac8c..8541f59b0 100644 --- a/semantics/memoryInstructions/cmpl_m32_imm8.k +++ b/semantics/memoryInstructions/cmpl_m32_imm8.k @@ -4,32 +4,34 @@ requires "x86-configuration.k" module CMPL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(cmpl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(cmpl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (cmpl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (cmpl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (cmpl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (cmpl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (cmpl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/cmppd_xmm_m128_imm8.k b/semantics/memoryInstructions/cmppd_xmm_m128_imm8.k index bffc625cb..29759e606 100644 --- a/semantics/memoryInstructions/cmppd_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/cmppd_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module CMPPD-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(cmppd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(cmppd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (cmppd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (cmppd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (cmppd Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (cmppd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (cmppd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( Mem128, 0, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( Mem128, 64, 128), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( Mem128, 0, 64), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( Mem128, 64, 128), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/cmpps_xmm_m128_imm8.k b/semantics/memoryInstructions/cmpps_xmm_m128_imm8.k index d80631593..80103aeb9 100644 --- a/semantics/memoryInstructions/cmpps_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/cmpps_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module CMPPS-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(cmpps:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(cmpps:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (cmpps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (cmpps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (cmpps Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (cmpps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (cmpps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/cmpq_m64_imm32.k b/semantics/memoryInstructions/cmpq_m64_imm32.k index 7b4346fc7..a68829089 100644 --- a/semantics/memoryInstructions/cmpq_m64_imm32.k +++ b/semantics/memoryInstructions/cmpq_m64_imm32.k @@ -4,32 +4,34 @@ requires "x86-configuration.k" module CMPQ-M64-IMM32 imports X86-CONFIGURATION - context execinstr(cmpq:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(cmpq:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (cmpq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (cmpq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (cmpq Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (cmpq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (cmpq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/cmpq_m64_imm8.k b/semantics/memoryInstructions/cmpq_m64_imm8.k index 6e800adb5..0c49b2505 100644 --- a/semantics/memoryInstructions/cmpq_m64_imm8.k +++ b/semantics/memoryInstructions/cmpq_m64_imm8.k @@ -4,32 +4,34 @@ requires "x86-configuration.k" module CMPQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(cmpq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(cmpq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (cmpq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (cmpq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (cmpq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (cmpq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (cmpq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/cmpsd_xmm_m64_imm8.k b/semantics/memoryInstructions/cmpsd_xmm_m64_imm8.k index f30bf9a63..1cf993429 100644 --- a/semantics/memoryInstructions/cmpsd_xmm_m64_imm8.k +++ b/semantics/memoryInstructions/cmpsd_xmm_m64_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module CMPSD-XMM-M64-IMM8 imports X86-CONFIGURATION - context execinstr(cmpsd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(cmpsd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (cmpsd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (cmpsd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (cmpsd Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (cmpsd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (cmpsd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 192), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), Mem64, handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi)) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 192), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), Mem64, Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/cmpss_xmm_m32_imm8.k b/semantics/memoryInstructions/cmpss_xmm_m32_imm8.k index ef8caec79..028025abf 100644 --- a/semantics/memoryInstructions/cmpss_xmm_m32_imm8.k +++ b/semantics/memoryInstructions/cmpss_xmm_m32_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module CMPSS-XMM-M32-IMM8 imports X86-CONFIGURATION - context execinstr(cmpss:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(cmpss:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (cmpss:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (cmpss:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (cmpss Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (cmpss:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (cmpss:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 224), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), Mem32, handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi)) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 224), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), Mem32, Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/cmpw_m16_imm16.k b/semantics/memoryInstructions/cmpw_m16_imm16.k index d6dc438b0..a0e749569 100644 --- a/semantics/memoryInstructions/cmpw_m16_imm16.k +++ b/semantics/memoryInstructions/cmpw_m16_imm16.k @@ -4,32 +4,34 @@ requires "x86-configuration.k" module CMPW-M16-IMM16 imports X86-CONFIGURATION - context execinstr(cmpw:Opcode Imm16:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(cmpw:Opcode Imm16:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (cmpw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (cmpw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (cmpw Imm16, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm16) ==Int 16 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (cmpw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (cmpw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm16, 11, 12), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/memoryInstructions/cmpw_m16_imm8.k b/semantics/memoryInstructions/cmpw_m16_imm8.k index 4290ec3f9..a75df6a77 100644 --- a/semantics/memoryInstructions/cmpw_m16_imm8.k +++ b/semantics/memoryInstructions/cmpw_m16_imm8.k @@ -4,32 +4,34 @@ requires "x86-configuration.k" module CMPW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(cmpw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(cmpw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (cmpw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (cmpw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (cmpw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (cmpw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (cmpw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/dppd_xmm_m128_imm8.k b/semantics/memoryInstructions/dppd_xmm_m128_imm8.k index 7be89118c..97cb12f44 100644 --- a/semantics/memoryInstructions/dppd_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/dppd_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module DPPD-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(dppd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(dppd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (dppd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (dppd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (dppd Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (dppd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (dppd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( Mem128, 64, 128)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( Mem128, 0, 64)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( Mem128, 64, 128)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( Mem128, 0, 64)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( Mem128, 64, 128)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( Mem128, 0, 64)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( Mem128, 64, 128)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( Mem128, 0, 64)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/dpps_xmm_m128_imm8.k b/semantics/memoryInstructions/dpps_xmm_m128_imm8.k index 98bc51dbb..adb5c4c7e 100644 --- a/semantics/memoryInstructions/dpps_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/dpps_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module DPPS-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(dpps:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(dpps:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (dpps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (dpps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (dpps Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (dpps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (dpps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/extractps_m32_xmm_imm8.k b/semantics/memoryInstructions/extractps_m32_xmm_imm8.k index 0a8278596..699f00c6e 100644 --- a/semantics/memoryInstructions/extractps_m32_xmm_imm8.k +++ b/semantics/memoryInstructions/extractps_m32_xmm_imm8.k @@ -4,24 +4,26 @@ requires "x86-configuration.k" module EXTRACTPS-M32-XMM-IMM8 imports X86-CONFIGURATION - context execinstr(extractps:Opcode Imm8:Imm, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(extractps:Opcode Imm8:MInt, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (extractps:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (extractps:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (extractps Imm8, R2:Xmm, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (extractps:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (extractps:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128), + extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128), MemOff, 32 ) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/imull_r32_m32_imm32.k b/semantics/memoryInstructions/imull_r32_m32_imm32.k index 294774e3b..867105d6c 100644 --- a/semantics/memoryInstructions/imull_r32_m32_imm32.k +++ b/semantics/memoryInstructions/imull_r32_m32_imm32.k @@ -4,24 +4,25 @@ requires "x86-configuration.k" module IMULL-R32-M32-IMM32 imports X86-CONFIGURATION - context execinstr(imull:Opcode Imm32:Imm, HOLE:Mem, R3:R32, .Operands) [result(MemOffset)] + context execinstr(imull:Opcode Imm32:MInt, HOLE:Mem, R3:R32, .Operands) [result(MemOffset)] rule - execinstr (imull:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, R3:R32, .Operands) => + execinstr (imull:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, R3:R32, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (imull Imm32, memOffset( MemOff), R3, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (imull:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, R3:R32, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (imull:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, R3:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), 32, 64)) +convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(Imm32))), 32, 64)) -"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(Imm32))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(Imm32))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) "PF" |-> (undefMInt) @@ -31,7 +32,8 @@ convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( mulMInt( mi(64, s "SF" |-> (undefMInt) -"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(Imm32))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(Imm32))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/imull_r32_m32_imm8.k b/semantics/memoryInstructions/imull_r32_m32_imm8.k index d20b7193e..555aae15b 100644 --- a/semantics/memoryInstructions/imull_r32_m32_imm8.k +++ b/semantics/memoryInstructions/imull_r32_m32_imm8.k @@ -4,24 +4,25 @@ requires "x86-configuration.k" module IMULL-R32-M32-IMM8 imports X86-CONFIGURATION - context execinstr(imull:Opcode Imm8:Imm, HOLE:Mem, R3:R32, .Operands) [result(MemOffset)] + context execinstr(imull:Opcode Imm8:MInt, HOLE:Mem, R3:R32, .Operands) [result(MemOffset)] rule - execinstr (imull:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:R32, .Operands) => + execinstr (imull:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:R32, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (imull Imm8, memOffset( MemOff), R3, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (imull:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:R32, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (imull:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 32, 64)) +convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(Imm8))), 32, 64)) -"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(Imm8))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(Imm8))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) "PF" |-> (undefMInt) @@ -31,7 +32,8 @@ convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( mulMInt( mi(64, s "SF" |-> (undefMInt) -"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(Imm8))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(Imm8))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/imulq_r64_m64_imm32.k b/semantics/memoryInstructions/imulq_r64_m64_imm32.k index 85f0420d1..f21476843 100644 --- a/semantics/memoryInstructions/imulq_r64_m64_imm32.k +++ b/semantics/memoryInstructions/imulq_r64_m64_imm32.k @@ -4,24 +4,25 @@ requires "x86-configuration.k" module IMULQ-R64-M64-IMM32 imports X86-CONFIGURATION - context execinstr(imulq:Opcode Imm32:Imm, HOLE:Mem, R3:R64, .Operands) [result(MemOffset)] + context execinstr(imulq:Opcode Imm32:MInt, HOLE:Mem, R3:R64, .Operands) [result(MemOffset)] rule - execinstr (imulq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, R3:R64, .Operands) => + execinstr (imulq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, R3:R64, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (imulq Imm32, memOffset( MemOff), R3, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (imulq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, R3:R64, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (imulq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, R3:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> extractMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), 64, 128) +convToRegKeys(R3) |-> extractMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(Imm32))), 64, 128) -"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(Imm32))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(Imm32))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) "PF" |-> (undefMInt) @@ -31,7 +32,8 @@ convToRegKeys(R3) |-> extractMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, "SF" |-> (undefMInt) -"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(Imm32))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(Imm32))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/imulq_r64_m64_imm8.k b/semantics/memoryInstructions/imulq_r64_m64_imm8.k index bb77f0b52..8877ae2d1 100644 --- a/semantics/memoryInstructions/imulq_r64_m64_imm8.k +++ b/semantics/memoryInstructions/imulq_r64_m64_imm8.k @@ -4,24 +4,25 @@ requires "x86-configuration.k" module IMULQ-R64-M64-IMM8 imports X86-CONFIGURATION - context execinstr(imulq:Opcode Imm8:Imm, HOLE:Mem, R3:R64, .Operands) [result(MemOffset)] + context execinstr(imulq:Opcode Imm8:MInt, HOLE:Mem, R3:R64, .Operands) [result(MemOffset)] rule - execinstr (imulq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:R64, .Operands) => + execinstr (imulq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:R64, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (imulq Imm8, memOffset( MemOff), R3, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (imulq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:R64, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (imulq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> extractMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 64, 128) +convToRegKeys(R3) |-> extractMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(Imm8))), 64, 128) -"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(Imm8))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(Imm8))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) "PF" |-> (undefMInt) @@ -31,7 +32,8 @@ convToRegKeys(R3) |-> extractMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, "SF" |-> (undefMInt) -"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(Imm8))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(Imm8))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/imulw_r16_m16_imm16.k b/semantics/memoryInstructions/imulw_r16_m16_imm16.k index c129cfdfa..d0442984c 100644 --- a/semantics/memoryInstructions/imulw_r16_m16_imm16.k +++ b/semantics/memoryInstructions/imulw_r16_m16_imm16.k @@ -4,24 +4,25 @@ requires "x86-configuration.k" module IMULW-R16-M16-IMM16 imports X86-CONFIGURATION - context execinstr(imulw:Opcode Imm16:Imm, HOLE:Mem, R3:R16, .Operands) [result(MemOffset)] + context execinstr(imulw:Opcode Imm16:MInt, HOLE:Mem, R3:R16, .Operands) [result(MemOffset)] rule - execinstr (imulw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, R3:R16, .Operands) => + execinstr (imulw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, R3:R16, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (imulw Imm16, memOffset( MemOff), R3, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm16) ==Int 16 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (imulw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, R3:R16, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (imulw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, R3:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 48), extractMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm16, 16, 16)))), 16, 32)) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 48), extractMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(Imm16))), 16, 32)) -"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm16, 16, 16)))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm16, 16, 16)))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(Imm16))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(Imm16))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) "PF" |-> (undefMInt) @@ -31,7 +32,8 @@ convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0 "SF" |-> (undefMInt) -"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm16, 16, 16)))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm16, 16, 16)))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(Imm16))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(Imm16))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/memoryInstructions/imulw_r16_m16_imm8.k b/semantics/memoryInstructions/imulw_r16_m16_imm8.k index b9081447b..991155d3d 100644 --- a/semantics/memoryInstructions/imulw_r16_m16_imm8.k +++ b/semantics/memoryInstructions/imulw_r16_m16_imm8.k @@ -4,24 +4,25 @@ requires "x86-configuration.k" module IMULW-R16-M16-IMM8 imports X86-CONFIGURATION - context execinstr(imulw:Opcode Imm8:Imm, HOLE:Mem, R3:R16, .Operands) [result(MemOffset)] + context execinstr(imulw:Opcode Imm8:MInt, HOLE:Mem, R3:R16, .Operands) [result(MemOffset)] rule - execinstr (imulw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:R16, .Operands) => + execinstr (imulw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:R16, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (imulw Imm8, memOffset( MemOff), R3, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (imulw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:R16, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (imulw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 48), extractMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 16, 32)) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 48), extractMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(Imm8))), 16, 32)) -"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(Imm8))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(Imm8))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) "PF" |-> (undefMInt) @@ -31,7 +32,8 @@ convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0 "SF" |-> (undefMInt) -"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(Imm8))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(Imm8))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/insertps_xmm_m32_imm8.k b/semantics/memoryInstructions/insertps_xmm_m32_imm8.k index f6861f6a5..a8f37f333 100644 --- a/semantics/memoryInstructions/insertps_xmm_m32_imm8.k +++ b/semantics/memoryInstructions/insertps_xmm_m32_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module INSERTPS-XMM-M32-IMM8 imports X86-CONFIGURATION - context execinstr(insertps:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(insertps:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (insertps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (insertps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (insertps Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (insertps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (insertps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else Mem32 #fi) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then Mem32 #else extractMInt( getParentValue(R3, RSMap), 160, 192) #fi) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then Mem32 #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then Mem32 #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else Mem32 #fi) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then Mem32 #else extractMInt( getParentValue(R3, RSMap), 160, 192) #fi) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then Mem32 #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then Mem32 #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/movb_m8_imm8.k b/semantics/memoryInstructions/movb_m8_imm8.k index c20f4a528..3117cf52f 100644 --- a/semantics/memoryInstructions/movb_m8_imm8.k +++ b/semantics/memoryInstructions/movb_m8_imm8.k @@ -4,17 +4,18 @@ requires "x86-configuration.k" module MOVB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(movb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(movb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (movb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (movb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, MemOff, 8 ) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/movl_m32_imm32.k b/semantics/memoryInstructions/movl_m32_imm32.k index b92e8ce16..617a1b1b0 100644 --- a/semantics/memoryInstructions/movl_m32_imm32.k +++ b/semantics/memoryInstructions/movl_m32_imm32.k @@ -4,17 +4,18 @@ requires "x86-configuration.k" module MOVL-M32-IMM32 imports X86-CONFIGURATION - context execinstr(movl:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(movl:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (movl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (movl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - handleImmediateWithSignExtend(Imm32, 32, 32), + Imm32, MemOff, 32 ) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/movq_m64_imm32.k b/semantics/memoryInstructions/movq_m64_imm32.k index a7327cfbe..3cfb363fa 100644 --- a/semantics/memoryInstructions/movq_m64_imm32.k +++ b/semantics/memoryInstructions/movq_m64_imm32.k @@ -4,17 +4,18 @@ requires "x86-configuration.k" module MOVQ-M64-IMM32 imports X86-CONFIGURATION - context execinstr(movq:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(movq:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (movq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (movq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), + mi(64, svalueMInt(Imm32)), MemOff, 64 ) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/movw_m16_imm16.k b/semantics/memoryInstructions/movw_m16_imm16.k index b27741cec..ef60688ab 100644 --- a/semantics/memoryInstructions/movw_m16_imm16.k +++ b/semantics/memoryInstructions/movw_m16_imm16.k @@ -4,17 +4,18 @@ requires "x86-configuration.k" module MOVW-M16-IMM16 imports X86-CONFIGURATION - context execinstr(movw:Opcode Imm16:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(movw:Opcode Imm16:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (movw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (movw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - handleImmediateWithSignExtend(Imm16, 16, 16), + Imm16, MemOff, 16 ) ... RSMap:Map + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/memoryInstructions/mpsadbw_xmm_m128_imm8.k b/semantics/memoryInstructions/mpsadbw_xmm_m128_imm8.k index 371a5ad43..c9368664f 100644 --- a/semantics/memoryInstructions/mpsadbw_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/mpsadbw_xmm_m128_imm8.k @@ -15,43 +15,44 @@ module MPSADBW-XMM-M128-IMM8 rule memLoadValue(MemVal:MInt):MemLoadValue ~> - execinstr (mpsadbw Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (mpsadbw Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => execinstr (mpsadbw selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 7 , 0 ), + extractMInt(Imm8, 6, 8), 7 , 0 ), selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 15, 8 ), + extractMInt(Imm8, 6, 8), 15, 8 ), selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 23, 16), + extractMInt(Imm8, 6, 8), 23, 16), selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 31, 24), + extractMInt(Imm8, 6, 8), 31, 24), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 7 , 0), + extractMInt(Imm8, 5, 6), 7 , 0), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 15, 8), + extractMInt(Imm8, 5, 6), 15, 8), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 23, 16), + extractMInt(Imm8, 5, 6), 23, 16), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 31, 24), + extractMInt(Imm8, 5, 6), 31, 24), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 39, 32), + extractMInt(Imm8, 5, 6), 39, 32), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 47, 40), + extractMInt(Imm8, 5, 6), 47, 40), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 55, 48), + extractMInt(Imm8, 5, 6), 55, 48), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 63, 56), + extractMInt(Imm8, 5, 6), 63, 56), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 71, 64), + extractMInt(Imm8, 5, 6), 71, 64), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 79, 72), + extractMInt(Imm8, 5, 6), 79, 72), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 87, 80), + extractMInt(Imm8, 5, 6), 87, 80), R3:Xmm, .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (mpsadbw diff --git a/semantics/memoryInstructions/orb_m8_imm8.k b/semantics/memoryInstructions/orb_m8_imm8.k index b4ca5efcd..5ba532294 100644 --- a/semantics/memoryInstructions/orb_m8_imm8.k +++ b/semantics/memoryInstructions/orb_m8_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ORB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(orb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(orb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (orb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (orb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (orb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (orb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (orb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - orMInt( Mem8, handleImmediateWithSignExtend(Imm8, 8, 8)), + orMInt( Mem8, Imm8), MemOff, 8 ) @@ -27,15 +28,16 @@ module ORB-M8-IMM8 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( Mem8, 7, 8), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( Mem8, 6, 7), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem8, 5, 6), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem8, 4, 5), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem8, 3, 4), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem8, 2, 3), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem8, 1, 2), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem8, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( Mem8, 7, 8), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( Mem8, 6, 7), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem8, 5, 6), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem8, 4, 5), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem8, 3, 4), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem8, 2, 3), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem8, 1, 2), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem8, 0, 1), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( Mem8, handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( Mem8, Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( Mem8, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> orMInt( extractMInt( Mem8, 0, 1), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/orl_m32_imm32.k b/semantics/memoryInstructions/orl_m32_imm32.k index ea98dc7d6..3ecaaea14 100644 --- a/semantics/memoryInstructions/orl_m32_imm32.k +++ b/semantics/memoryInstructions/orl_m32_imm32.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ORL-M32-IMM32 imports X86-CONFIGURATION - context execinstr(orl:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(orl:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (orl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (orl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (orl Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (orl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (orl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - orMInt( Mem32, handleImmediateWithSignExtend(Imm32, 32, 32)), + orMInt( Mem32, Imm32), MemOff, 32 ) @@ -27,15 +28,16 @@ module ORL-M32-IMM32 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( Mem32, 31, 32), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( Mem32, 30, 31), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 29, 30), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 28, 29), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 27, 28), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 26, 27), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 25, 26), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 24, 25), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( Mem32, 31, 32), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( Mem32, 30, 31), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 29, 30), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 28, 29), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 27, 28), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 26, 27), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 25, 26), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 24, 25), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( Mem32, handleImmediateWithSignExtend(Imm32, 32, 32)), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( Mem32, Imm32), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( Mem32, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)) +"SF" |-> orMInt( extractMInt( Mem32, 0, 1), extractMInt( Imm32, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/orl_m32_imm8.k b/semantics/memoryInstructions/orl_m32_imm8.k index 04524a8c5..6340e5e0a 100644 --- a/semantics/memoryInstructions/orl_m32_imm8.k +++ b/semantics/memoryInstructions/orl_m32_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ORL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(orl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(orl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (orl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (orl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (orl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (orl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (orl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - orMInt( Mem32, mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), + orMInt( Mem32, mi(32, svalueMInt(Imm8))), MemOff, 32 ) @@ -27,15 +28,16 @@ module ORL-M32-IMM8 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( Mem32, 31, 32), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( Mem32, 30, 31), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 29, 30), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 28, 29), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 27, 28), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 26, 27), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 25, 26), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 24, 25), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( Mem32, 31, 32), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( Mem32, 30, 31), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 29, 30), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 28, 29), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 27, 28), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 26, 27), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 25, 26), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 24, 25), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( Mem32, mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( Mem32, mi(32, svalueMInt(Imm8))), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( Mem32, 0, 1), extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> orMInt( extractMInt( Mem32, 0, 1), extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/orq_m64_imm32.k b/semantics/memoryInstructions/orq_m64_imm32.k index eccfb584b..7bd639dc6 100644 --- a/semantics/memoryInstructions/orq_m64_imm32.k +++ b/semantics/memoryInstructions/orq_m64_imm32.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ORQ-M64-IMM32 imports X86-CONFIGURATION - context execinstr(orq:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(orq:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (orq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (orq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (orq Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (orq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (orq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - orMInt( Mem64, mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), + orMInt( Mem64, mi(64, svalueMInt(Imm32))), MemOff, 64 ) @@ -27,15 +28,16 @@ module ORQ-M64-IMM32 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( Mem64, 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( Mem64, 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( Mem64, 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( Mem64, 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( Mem64, mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( Mem64, mi(64, svalueMInt(Imm32))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( Mem64, 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)) +"SF" |-> orMInt( extractMInt( Mem64, 0, 1), extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/orq_m64_imm8.k b/semantics/memoryInstructions/orq_m64_imm8.k index af93c42cb..0b8480302 100644 --- a/semantics/memoryInstructions/orq_m64_imm8.k +++ b/semantics/memoryInstructions/orq_m64_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ORQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(orq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(orq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (orq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (orq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (orq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (orq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (orq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - orMInt( Mem64, mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), + orMInt( Mem64, mi(64, svalueMInt(Imm8))), MemOff, 64 ) @@ -27,15 +28,16 @@ module ORQ-M64-IMM8 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( Mem64, 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( Mem64, 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( Mem64, 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( Mem64, 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( Mem64, mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( Mem64, mi(64, svalueMInt(Imm8))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( Mem64, 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> orMInt( extractMInt( Mem64, 0, 1), extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/orw_m16_imm16.k b/semantics/memoryInstructions/orw_m16_imm16.k index 4a1e8e32c..4968ddc8f 100644 --- a/semantics/memoryInstructions/orw_m16_imm16.k +++ b/semantics/memoryInstructions/orw_m16_imm16.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ORW-M16-IMM16 imports X86-CONFIGURATION - context execinstr(orw:Opcode Imm16:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(orw:Opcode Imm16:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (orw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (orw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (orw Imm16, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm16) ==Int 16 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (orw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (orw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - orMInt( Mem16, handleImmediateWithSignExtend(Imm16, 16, 16)), + orMInt( Mem16, Imm16), MemOff, 16 ) @@ -27,15 +28,16 @@ module ORW-M16-IMM16 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( Mem16, 15, 16), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 15, 16)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( Mem16, 14, 15), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 14, 15)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 13, 14), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 13, 14)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 12, 13), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 12, 13)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 11, 12), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 10, 11), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 10, 11)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 9, 10), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 9, 10)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 8, 9), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( Mem16, 15, 16), extractMInt( Imm16, 15, 16)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( Mem16, 14, 15), extractMInt( Imm16, 14, 15)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 13, 14), extractMInt( Imm16, 13, 14)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 12, 13), extractMInt( Imm16, 12, 13)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 11, 12), extractMInt( Imm16, 11, 12)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 10, 11), extractMInt( Imm16, 10, 11)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 9, 10), extractMInt( Imm16, 9, 10)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 8, 9), extractMInt( Imm16, 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( Mem16, handleImmediateWithSignExtend(Imm16, 16, 16)), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( Mem16, Imm16), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( Mem16, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)) +"SF" |-> orMInt( extractMInt( Mem16, 0, 1), extractMInt( Imm16, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/memoryInstructions/orw_m16_imm8.k b/semantics/memoryInstructions/orw_m16_imm8.k index 3c5ace79a..0bfc5cc92 100644 --- a/semantics/memoryInstructions/orw_m16_imm8.k +++ b/semantics/memoryInstructions/orw_m16_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ORW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(orw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(orw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (orw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (orw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (orw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (orw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (orw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - orMInt( Mem16, mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), + orMInt( Mem16, mi(16, svalueMInt(Imm8))), MemOff, 16 ) @@ -27,15 +28,16 @@ module ORW-M16-IMM8 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( Mem16, 15, 16), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( Mem16, 14, 15), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 13, 14), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 12, 13), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 11, 12), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 10, 11), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 9, 10), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 8, 9), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( Mem16, 15, 16), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( Mem16, 14, 15), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 13, 14), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 12, 13), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 11, 12), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 10, 11), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 9, 10), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 8, 9), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( Mem16, mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( Mem16, mi(16, svalueMInt(Imm8))), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( Mem16, 0, 1), extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> orMInt( extractMInt( Mem16, 0, 1), extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/palignr_xmm_m128_imm8.k b/semantics/memoryInstructions/palignr_xmm_m128_imm8.k index c7c367b4d..4a180da4e 100644 --- a/semantics/memoryInstructions/palignr_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/palignr_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module PALIGNR-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(palignr:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(palignr:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (palignr:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (palignr:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (palignr Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (palignr:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (palignr:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), Mem128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), uvalueMInt(mi(256, 3))))), 128, 256)) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), Mem128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), Imm8), uvalueMInt(mi(256, 3))))), 128, 256)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/pblendw_xmm_m128_imm8.k b/semantics/memoryInstructions/pblendw_xmm_m128_imm8.k index 43af6e40d..aa6593bf9 100644 --- a/semantics/memoryInstructions/pblendw_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/pblendw_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module PBLENDW-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(pblendw:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(pblendw:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (pblendw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (pblendw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (pblendw Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (pblendw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (pblendw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 144) #else extractMInt( Mem128, 0, 16) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 144, 160) #else extractMInt( Mem128, 16, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 176) #else extractMInt( Mem128, 32, 48) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 176, 192) #else extractMInt( Mem128, 48, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 208) #else extractMInt( Mem128, 64, 80) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 208, 224) #else extractMInt( Mem128, 80, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 240) #else extractMInt( Mem128, 96, 112) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 240, 256) #else extractMInt( Mem128, 112, 128) #fi))))))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 144) #else extractMInt( Mem128, 0, 16) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 144, 160) #else extractMInt( Mem128, 16, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 176) #else extractMInt( Mem128, 32, 48) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 176, 192) #else extractMInt( Mem128, 48, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 208) #else extractMInt( Mem128, 64, 80) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 208, 224) #else extractMInt( Mem128, 80, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 240) #else extractMInt( Mem128, 96, 112) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 240, 256) #else extractMInt( Mem128, 112, 128) #fi))))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/pclmulqdq_xmm_m128_imm8.k b/semantics/memoryInstructions/pclmulqdq_xmm_m128_imm8.k index 99509379b..d7e6dd713 100644 --- a/semantics/memoryInstructions/pclmulqdq_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/pclmulqdq_xmm_m128_imm8.k @@ -59,15 +59,14 @@ module PCLMULQDQ-XMM-M128-IMM8 */ rule memLoadValue(MemVal:MInt):MemLoadValue ~> - execinstr (pclmulqdq Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (pclmulqdq Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => execinstr(pclmulqdq - selectSlice(getRegisterValue(R3, RSMap), handleImmediateWithSignExtend(Imm8, - 8, 8), 7, 64, 0), - selectSlice(MemVal, handleImmediateWithSignExtend(Imm8, - 8, 8), 3, 64, 0), R3 + selectSlice(getRegisterValue(R3, RSMap), Imm8, 7, 64, 0), + selectSlice(MemVal, Imm8, 3, 64, 0), R3 , .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (pclmulqdq TEMP1:MInt, TEMP2:MInt, R3:Xmm, .Operands) => diff --git a/semantics/memoryInstructions/pcmpestri_xmm_m128_imm8.k b/semantics/memoryInstructions/pcmpestri_xmm_m128_imm8.k index 61a510c17..45b1025e5 100644 --- a/semantics/memoryInstructions/pcmpestri_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/pcmpestri_xmm_m128_imm8.k @@ -4,27 +4,28 @@ requires "x86-configuration.k" module PCMPESTRI-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(pcmpestri:Opcode Imm8:Imm, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] + context execinstr(pcmpestri:Opcode Imm8:MInt, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] rule - execinstr (pcmpestri:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => + execinstr (pcmpestri:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (pcmpestri Imm8, memOffset( MemOff), Xmm1, .Operands) ... - + requires bitwidthMInt(Imm8) ==Int 8 // Find Limit Index rule memLoadValue(Mem128:MInt):MemLoadValue ~> - execinstr (pcmpestri Imm8:Imm, memOffset( MemOff), Xmm1:Xmm, .Operands) => + execinstr (pcmpestri Imm8:MInt, memOffset( MemOff), Xmm1:Xmm, .Operands) => execinstr (pcmpestri - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, Mem128, getRegisterValue(Xmm1, RSMap), - findLimitIndexE(Mem128, getRegisterValue(%rdx, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexE(Mem128, getRegisterValue(%rdx, RSMap), Imm8), + findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // Find data size and interpretation rule diff --git a/semantics/memoryInstructions/pcmpestrm_xmm_m128_imm8.k b/semantics/memoryInstructions/pcmpestrm_xmm_m128_imm8.k index 958a11c68..767460a26 100644 --- a/semantics/memoryInstructions/pcmpestrm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/pcmpestrm_xmm_m128_imm8.k @@ -4,26 +4,27 @@ requires "x86-configuration.k" module PCMPESTRM-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(pcmpestrm:Opcode Imm8:Imm, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] + context execinstr(pcmpestrm:Opcode Imm8:MInt, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] rule - execinstr (pcmpestrm:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => + execinstr (pcmpestrm:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (pcmpestrm Imm8, memOffset( MemOff), Xmm1, .Operands) ... - + requires bitwidthMInt(Imm8) ==Int 8 // Find Limit Index rule memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (pcmpestrm Imm8, memOffset( MemOff), Xmm1, .Operands) => execinstr (pcmpestrm - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, Mem128, getRegisterValue(Xmm1, RSMap), - findLimitIndexE(Mem128, getRegisterValue(%rdx, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexE(Mem128, getRegisterValue(%rdx, RSMap), Imm8), + findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // Find data size and interpretation rule diff --git a/semantics/memoryInstructions/pcmpistri_xmm_m128_imm8.k b/semantics/memoryInstructions/pcmpistri_xmm_m128_imm8.k index 5a15c9732..39b1d8978 100644 --- a/semantics/memoryInstructions/pcmpistri_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/pcmpistri_xmm_m128_imm8.k @@ -4,27 +4,28 @@ requires "x86-configuration.k" module PCMPISTRI-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(pcmpistri:Opcode Imm8:Imm, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] + context execinstr(pcmpistri:Opcode Imm8:MInt, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] rule - execinstr (pcmpistri:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => + execinstr (pcmpistri:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (pcmpistri Imm8, memOffset( MemOff), Xmm1, .Operands) ... - + requires bitwidthMInt(Imm8) ==Int 8 // Find Limit Index rule memLoadValue(Mem128:MInt):MemLoadValue ~> - execinstr (pcmpistri Imm8:Imm, Xmm2:Xmm, Xmm1:Xmm, .Operands) => + execinstr (pcmpistri Imm8:MInt, Xmm2:Xmm, Xmm1:Xmm, .Operands) => execinstr (pcmpistri - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, Mem128, getRegisterValue(Xmm1, RSMap), - findLimitIndexI(Mem128, handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexI(getRegisterValue(Xmm1, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexI(Mem128, Imm8), + findLimitIndexI(getRegisterValue(Xmm1, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // Find data size and interpretation rule diff --git a/semantics/memoryInstructions/pcmpistrm_xmm_m128_imm8.k b/semantics/memoryInstructions/pcmpistrm_xmm_m128_imm8.k index 62bca883f..6dd931b04 100644 --- a/semantics/memoryInstructions/pcmpistrm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/pcmpistrm_xmm_m128_imm8.k @@ -4,26 +4,28 @@ requires "x86-configuration.k" module PCMPISTRM-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(pcmpistrm:Opcode Imm8:Imm, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] + context execinstr(pcmpistrm:Opcode Imm8:MInt, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] rule - execinstr (pcmpistrm:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => + execinstr (pcmpistrm:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (pcmpistrm Imm8, memOffset( MemOff), Xmm1, .Operands) ... + requires bitwidthMInt(Imm8) ==Int 8 // Find Limit Index rule memLoadValue(Mem128:MInt):MemLoadValue ~> - execinstr (pcmpistrm Imm8:Imm, Xmm2:Xmm, Xmm1:Xmm, .Operands) => + execinstr (pcmpistrm Imm8:MInt, Xmm2:Xmm, Xmm1:Xmm, .Operands) => execinstr (pcmpistrm - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, Mem128, getRegisterValue(Xmm1, RSMap), - findLimitIndexI(Mem128, handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexI(getRegisterValue(Xmm1, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexI(Mem128, Imm8), + findLimitIndexI(getRegisterValue(Xmm1, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // Find data size and interpretation rule diff --git a/semantics/memoryInstructions/pextrb_m8_xmm_imm8.k b/semantics/memoryInstructions/pextrb_m8_xmm_imm8.k index d7ab2d23b..b73966a0d 100644 --- a/semantics/memoryInstructions/pextrb_m8_xmm_imm8.k +++ b/semantics/memoryInstructions/pextrb_m8_xmm_imm8.k @@ -4,24 +4,26 @@ requires "x86-configuration.k" module PEXTRB-M8-XMM-IMM8 imports X86-CONFIGURATION - context execinstr(pextrb:Opcode Imm8:Imm, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(pextrb:Opcode Imm8:MInt, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (pextrb:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (pextrb:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (pextrb Imm8, R2:Xmm, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (pextrb:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (pextrb:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3))))), 120, 128), + extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3))))), 120, 128), MemOff, 8 ) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/pextrd_m32_xmm_imm8.k b/semantics/memoryInstructions/pextrd_m32_xmm_imm8.k index f5407af77..7f06e8236 100644 --- a/semantics/memoryInstructions/pextrd_m32_xmm_imm8.k +++ b/semantics/memoryInstructions/pextrd_m32_xmm_imm8.k @@ -4,24 +4,26 @@ requires "x86-configuration.k" module PEXTRD-M32-XMM-IMM8 imports X86-CONFIGURATION - context execinstr(pextrd:Opcode Imm8:Imm, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(pextrd:Opcode Imm8:MInt, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (pextrd:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (pextrd:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (pextrd Imm8, R2:Xmm, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (pextrd:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (pextrd:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128), + extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128), MemOff, 32 ) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/pextrq_m64_xmm_imm8.k b/semantics/memoryInstructions/pextrq_m64_xmm_imm8.k index 0d61dfb30..5aa3bbb84 100644 --- a/semantics/memoryInstructions/pextrq_m64_xmm_imm8.k +++ b/semantics/memoryInstructions/pextrq_m64_xmm_imm8.k @@ -4,24 +4,26 @@ requires "x86-configuration.k" module PEXTRQ-M64-XMM-IMM8 imports X86-CONFIGURATION - context execinstr(pextrq:Opcode Imm8:Imm, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(pextrq:Opcode Imm8:MInt, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (pextrq:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (pextrq:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (pextrq Imm8, R2:Xmm, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (pextrq:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (pextrq:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6))))), 64, 128), + extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6))))), 64, 128), MemOff, 64 ) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/pextrw_m16_xmm_imm8.k b/semantics/memoryInstructions/pextrw_m16_xmm_imm8.k index f95eff99d..9935ae96a 100644 --- a/semantics/memoryInstructions/pextrw_m16_xmm_imm8.k +++ b/semantics/memoryInstructions/pextrw_m16_xmm_imm8.k @@ -4,24 +4,26 @@ requires "x86-configuration.k" module PEXTRW-M16-XMM-IMM8 imports X86-CONFIGURATION - context execinstr(pextrw:Opcode Imm8:Imm, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(pextrw:Opcode Imm8:MInt, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (pextrw:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (pextrw:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (pextrw Imm8, R2:Xmm, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (pextrw:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (pextrw:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4))))), 112, 128), + extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4))))), 112, 128), MemOff, 16 ) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/pinsrb_xmm_m8_imm8.k b/semantics/memoryInstructions/pinsrb_xmm_m8_imm8.k index 042e06a78..49e837687 100644 --- a/semantics/memoryInstructions/pinsrb_xmm_m8_imm8.k +++ b/semantics/memoryInstructions/pinsrb_xmm_m8_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module PINSRB-XMM-M8-IMM8 imports X86-CONFIGURATION - context execinstr(pinsrb:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(pinsrb:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (pinsrb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (pinsrb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (pinsrb Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (pinsrb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (pinsrb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(120, 0), Mem8), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3))))), shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3)))))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(120, 0), Mem8), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3))))), shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/pinsrd_xmm_m32_imm8.k b/semantics/memoryInstructions/pinsrd_xmm_m32_imm8.k index 56522bc13..0516c0b31 100644 --- a/semantics/memoryInstructions/pinsrd_xmm_m32_imm8.k +++ b/semantics/memoryInstructions/pinsrd_xmm_m32_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module PINSRD-XMM-M32-IMM8 imports X86-CONFIGURATION - context execinstr(pinsrd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(pinsrd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (pinsrd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (pinsrd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (pinsrd Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (pinsrd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (pinsrd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), Mem32), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5)))))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), Mem32), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/pinsrq_xmm_m64_imm8.k b/semantics/memoryInstructions/pinsrq_xmm_m64_imm8.k index edfe63203..7b9bc6903 100644 --- a/semantics/memoryInstructions/pinsrq_xmm_m64_imm8.k +++ b/semantics/memoryInstructions/pinsrq_xmm_m64_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module PINSRQ-XMM-M64-IMM8 imports X86-CONFIGURATION - context execinstr(pinsrq:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(pinsrq:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (pinsrq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (pinsrq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (pinsrq Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (pinsrq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (pinsrq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(64, 0), Mem64), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6))))), shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6)))))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(64, 0), Mem64), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6))))), shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/pinsrw_xmm_m16_imm8.k b/semantics/memoryInstructions/pinsrw_xmm_m16_imm8.k index 5bed131d4..7ae87cb30 100644 --- a/semantics/memoryInstructions/pinsrw_xmm_m16_imm8.k +++ b/semantics/memoryInstructions/pinsrw_xmm_m16_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module PINSRW-XMM-M16-IMM8 imports X86-CONFIGURATION - context execinstr(pinsrw:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(pinsrw:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (pinsrw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (pinsrw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (pinsrw Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (pinsrw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (pinsrw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(112, 0), Mem16), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4))))), shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4)))))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(112, 0), Mem16), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4))))), shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/pshufd_xmm_m128_imm8.k b/semantics/memoryInstructions/pshufd_xmm_m128_imm8.k index f0842f0ea..3a8776d47 100644 --- a/semantics/memoryInstructions/pshufd_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/pshufd_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module PSHUFD-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(pshufd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(pshufd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (pshufd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (pshufd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (pshufd Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (pshufd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (pshufd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/pshufhw_xmm_m128_imm8.k b/semantics/memoryInstructions/pshufhw_xmm_m128_imm8.k index 21db89b0b..ac5963cc5 100644 --- a/semantics/memoryInstructions/pshufhw_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/pshufhw_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module PSHUFHW-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(pshufhw:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(pshufhw:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (pshufhw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (pshufhw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (pshufhw Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (pshufhw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (pshufhw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 4))))), 48, 64), extractMInt( Mem128, 64, 128)))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 4))))), 48, 64), extractMInt( Mem128, 64, 128)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/pshuflw_xmm_m128_imm8.k b/semantics/memoryInstructions/pshuflw_xmm_m128_imm8.k index 40071f4bf..916bf22a1 100644 --- a/semantics/memoryInstructions/pshuflw_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/pshuflw_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module PSHUFLW-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(pshuflw:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(pshuflw:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (pshuflw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (pshuflw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (pshuflw Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (pshuflw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (pshuflw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( extractMInt( Mem128, 0, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 4))))), 112, 128), extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 4))))), 112, 128)))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( extractMInt( Mem128, 0, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 4))))), 112, 128), extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 4))))), 112, 128)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rclb_m8_imm8.k b/semantics/memoryInstructions/rclb_m8_imm8.k index 1e9c4b1a0..212f87c6f 100644 --- a/semantics/memoryInstructions/rclb_m8_imm8.k +++ b/semantics/memoryInstructions/rclb_m8_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module RCLB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(rclb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(rclb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (rclb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (rclb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (rclb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (rclb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (rclb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 1, 9), + extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 1, 9), MemOff, 8 ) @@ -25,9 +26,10 @@ module RCLB-M8-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 0, 1) +"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rcll_m32_imm8.k b/semantics/memoryInstructions/rcll_m32_imm8.k index 1820d2099..e0da5ed9c 100644 --- a/semantics/memoryInstructions/rcll_m32_imm8.k +++ b/semantics/memoryInstructions/rcll_m32_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module RCLL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(rcll:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(rcll:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (rcll:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (rcll:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (rcll Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (rcll:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (rcll:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 1, 33), + extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 1, 33), MemOff, 32 ) @@ -25,9 +26,10 @@ module RCLL-M32-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 0, 1) +"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rclq_m64_imm8.k b/semantics/memoryInstructions/rclq_m64_imm8.k index 8f5625314..cf3443d73 100644 --- a/semantics/memoryInstructions/rclq_m64_imm8.k +++ b/semantics/memoryInstructions/rclq_m64_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module RCLQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(rclq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(rclq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (rclq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (rclq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (rclq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (rclq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (rclq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 1, 65), + extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 1, 65), MemOff, 64 ) @@ -25,9 +26,10 @@ module RCLQ-M64-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 0, 1) +"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rclw_m16_imm8.k b/semantics/memoryInstructions/rclw_m16_imm8.k index bd9fdc138..db3ea085e 100644 --- a/semantics/memoryInstructions/rclw_m16_imm8.k +++ b/semantics/memoryInstructions/rclw_m16_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module RCLW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(rclw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(rclw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (rclw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (rclw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (rclw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (rclw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (rclw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 1, 17), + extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 1, 17), MemOff, 16 ) @@ -25,9 +26,10 @@ module RCLW-M16-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 0, 1) +"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rcrb_m8_imm8.k b/semantics/memoryInstructions/rcrb_m8_imm8.k index 56168eaba..6b37b602b 100644 --- a/semantics/memoryInstructions/rcrb_m8_imm8.k +++ b/semantics/memoryInstructions/rcrb_m8_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module RCRB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(rcrb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(rcrb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (rcrb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (rcrb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (rcrb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (rcrb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (rcrb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 1, 9), + extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 1, 9), MemOff, 8 ) @@ -25,9 +26,10 @@ module RCRB-M8-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 0, 1) +"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rcrl_m32_imm8.k b/semantics/memoryInstructions/rcrl_m32_imm8.k index eb957b2fb..aa3cd6441 100644 --- a/semantics/memoryInstructions/rcrl_m32_imm8.k +++ b/semantics/memoryInstructions/rcrl_m32_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module RCRL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(rcrl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(rcrl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (rcrl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (rcrl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (rcrl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (rcrl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (rcrl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 1, 33), + extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 1, 33), MemOff, 32 ) @@ -25,9 +26,10 @@ module RCRL-M32-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 0, 1) +"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rcrq_m64_imm8.k b/semantics/memoryInstructions/rcrq_m64_imm8.k index e4ff5d706..4b542beb5 100644 --- a/semantics/memoryInstructions/rcrq_m64_imm8.k +++ b/semantics/memoryInstructions/rcrq_m64_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module RCRQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(rcrq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(rcrq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (rcrq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (rcrq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (rcrq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (rcrq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (rcrq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 1, 65), + extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 1, 65), MemOff, 64 ) @@ -25,9 +26,10 @@ module RCRQ-M64-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 0, 1) +"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rcrw_m16_imm8.k b/semantics/memoryInstructions/rcrw_m16_imm8.k index d580ecd02..ba4cc16fe 100644 --- a/semantics/memoryInstructions/rcrw_m16_imm8.k +++ b/semantics/memoryInstructions/rcrw_m16_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module RCRW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(rcrw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(rcrw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (rcrw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (rcrw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (rcrw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (rcrw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (rcrw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 1, 17), + extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 1, 17), MemOff, 16 ) @@ -25,9 +26,10 @@ module RCRW-M16-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 0, 1) +"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rolb_m8_imm8.k b/semantics/memoryInstructions/rolb_m8_imm8.k index 115587aac..c825e8e4a 100644 --- a/semantics/memoryInstructions/rolb_m8_imm8.k +++ b/semantics/memoryInstructions/rolb_m8_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ROLB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(rolb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(rolb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (rolb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (rolb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (rolb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (rolb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (rolb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - rol( Mem8, andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), + rol( Mem8, andMInt( Imm8, mi(8, 31))), MemOff, 8 ) @@ -25,9 +26,10 @@ module ROLB-M8-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( rol( Mem8, andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 7, 8), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( rol( Mem8, andMInt( Imm8, mi(8, 31))), 7, 8), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( Mem8, andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( Mem8, andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 7, 8), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( Mem8, andMInt( Imm8, mi(8, 31))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( Mem8, andMInt( Imm8, mi(8, 31))), 7, 8), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/roll_m32_imm8.k b/semantics/memoryInstructions/roll_m32_imm8.k index 0e57abfb6..fe67f00e8 100644 --- a/semantics/memoryInstructions/roll_m32_imm8.k +++ b/semantics/memoryInstructions/roll_m32_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ROLL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(roll:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(roll:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (roll:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (roll:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (roll Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (roll:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (roll:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - rol( Mem32, concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), + rol( Mem32, concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31)))), MemOff, 32 ) @@ -25,9 +26,10 @@ module ROLL-M32-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( rol( Mem32, concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 31, 32), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( rol( Mem32, concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31)))), 31, 32), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( Mem32, concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( Mem32, concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 31, 32), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( Mem32, concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( Mem32, concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31)))), 31, 32), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rolq_m64_imm8.k b/semantics/memoryInstructions/rolq_m64_imm8.k index cc2e55f91..116062163 100644 --- a/semantics/memoryInstructions/rolq_m64_imm8.k +++ b/semantics/memoryInstructions/rolq_m64_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ROLQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(rolq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(rolq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (rolq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (rolq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (rolq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (rolq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (rolq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - rol( Mem64, concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))), + rol( Mem64, concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))), MemOff, 64 ) @@ -25,9 +26,10 @@ module ROLQ-M64-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( rol( Mem64, concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))), 63, 64), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( rol( Mem64, concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))), 63, 64), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( Mem64, concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( Mem64, concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))), 63, 64), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( Mem64, concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( Mem64, concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))), 63, 64), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rolw_m16_imm8.k b/semantics/memoryInstructions/rolw_m16_imm8.k index 7e03695af..83ebb9836 100644 --- a/semantics/memoryInstructions/rolw_m16_imm8.k +++ b/semantics/memoryInstructions/rolw_m16_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ROLW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(rolw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(rolw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (rolw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (rolw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (rolw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (rolw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (rolw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - rol( Mem16, concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), + rol( Mem16, concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31)))), MemOff, 16 ) @@ -25,9 +26,10 @@ module ROLW-M16-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( rol( Mem16, concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 15, 16), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( rol( Mem16, concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31)))), 15, 16), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( Mem16, concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( Mem16, concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 15, 16), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( Mem16, concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( Mem16, concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31)))), 15, 16), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rorb_m8_imm8.k b/semantics/memoryInstructions/rorb_m8_imm8.k index e22fbf7e7..80e919c13 100644 --- a/semantics/memoryInstructions/rorb_m8_imm8.k +++ b/semantics/memoryInstructions/rorb_m8_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module RORB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(rorb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(rorb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (rorb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (rorb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (rorb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (rorb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (rorb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - ror( Mem8, andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), + ror( Mem8, andMInt( Imm8, mi(8, 31))), MemOff, 8 ) @@ -25,9 +26,10 @@ module RORB-M8-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( ror( Mem8, andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( ror( Mem8, andMInt( Imm8, mi(8, 31))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( Mem8, andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( Mem8, andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( Mem8, andMInt( Imm8, mi(8, 31))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( Mem8, andMInt( Imm8, mi(8, 31))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rorl_m32_imm8.k b/semantics/memoryInstructions/rorl_m32_imm8.k index 8499c1983..50ef81eeb 100644 --- a/semantics/memoryInstructions/rorl_m32_imm8.k +++ b/semantics/memoryInstructions/rorl_m32_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module RORL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(rorl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(rorl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (rorl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (rorl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (rorl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (rorl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (rorl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - ror( Mem32, concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), + ror( Mem32, concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31)))), MemOff, 32 ) @@ -25,9 +26,10 @@ module RORL-M32-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( ror( Mem32, concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( ror( Mem32, concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31)))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( Mem32, concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( Mem32, concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( Mem32, concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( Mem32, concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31)))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rorq_m64_imm8.k b/semantics/memoryInstructions/rorq_m64_imm8.k index 8999aa369..d89905778 100644 --- a/semantics/memoryInstructions/rorq_m64_imm8.k +++ b/semantics/memoryInstructions/rorq_m64_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module RORQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(rorq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(rorq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (rorq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (rorq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (rorq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (rorq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (rorq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - ror( Mem64, concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))), + ror( Mem64, concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))), MemOff, 64 ) @@ -25,9 +26,10 @@ module RORQ-M64-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( ror( Mem64, concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( ror( Mem64, concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( Mem64, concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( Mem64, concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( Mem64, concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( Mem64, concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rorw_m16_imm8.k b/semantics/memoryInstructions/rorw_m16_imm8.k index 24b01f49f..b68cd20d0 100644 --- a/semantics/memoryInstructions/rorw_m16_imm8.k +++ b/semantics/memoryInstructions/rorw_m16_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module RORW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(rorw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(rorw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (rorw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (rorw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (rorw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (rorw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (rorw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - ror( Mem16, concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), + ror( Mem16, concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31)))), MemOff, 16 ) @@ -25,9 +26,10 @@ module RORW-M16-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( ror( Mem16, concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( ror( Mem16, concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31)))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( Mem16, concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( Mem16, concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( Mem16, concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( Mem16, concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31)))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rorxl_r32_m32_imm8.k b/semantics/memoryInstructions/rorxl_r32_m32_imm8.k index 403e4c689..93b6be969 100644 --- a/semantics/memoryInstructions/rorxl_r32_m32_imm8.k +++ b/semantics/memoryInstructions/rorxl_r32_m32_imm8.k @@ -5,24 +5,26 @@ module RORXL-R32-M32-IMM8 imports X86-CONFIGURATION rule - execinstr (rorx:Opcode Imm8:Imm, M:Mem, R3:R32, .Operands) => execinstr (rorxl:Opcode Imm8:Imm, M:Mem, R3:R32, .Operands) + execinstr (rorx:Opcode Imm8:MInt, M:Mem, R3:R32, .Operands) => execinstr (rorxl:Opcode Imm8:MInt, M:Mem, R3:R32, .Operands) ... - context execinstr(rorxl:Opcode Imm8:Imm, HOLE:Mem, R3:R32, .Operands) [result(MemOffset)] + context execinstr(rorxl:Opcode Imm8:MInt, HOLE:Mem, R3:R32, .Operands) [result(MemOffset)] rule - execinstr (rorxl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:R32, .Operands) => + execinstr (rorxl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:R32, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (rorxl Imm8, memOffset( MemOff), R3, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (rorxl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:R32, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (rorxl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), orMInt( lshrMInt( Mem32, uvalueMInt(andMInt( concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(32, 31)))), shiftLeftMInt( Mem32, uvalueMInt(subMInt( mi(32, 32), andMInt( concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(32, 31))))))) +convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), orMInt( lshrMInt( Mem32, uvalueMInt(andMInt( concatenateMInt( mi(24, 0), Imm8), mi(32, 31)))), shiftLeftMInt( Mem32, uvalueMInt(subMInt( mi(32, 32), andMInt( concatenateMInt( mi(24, 0), Imm8), mi(32, 31))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rorxq_r64_m64_imm8.k b/semantics/memoryInstructions/rorxq_r64_m64_imm8.k index 4c6ff662d..66e54a499 100644 --- a/semantics/memoryInstructions/rorxq_r64_m64_imm8.k +++ b/semantics/memoryInstructions/rorxq_r64_m64_imm8.k @@ -5,24 +5,26 @@ module RORXQ-R64-M64-IMM8 imports X86-CONFIGURATION rule - execinstr (rorx:Opcode Imm8:Imm, M:Mem, R3:R64, .Operands) => execinstr (rorxq:Opcode Imm8:Imm, M:Mem, R3:R64, .Operands) + execinstr (rorx:Opcode Imm8:MInt, M:Mem, R3:R64, .Operands) => execinstr (rorxq:Opcode Imm8:MInt, M:Mem, R3:R64, .Operands) ... - context execinstr(rorxq:Opcode Imm8:Imm, HOLE:Mem, R3:R64, .Operands) [result(MemOffset)] + context execinstr(rorxq:Opcode Imm8:MInt, HOLE:Mem, R3:R64, .Operands) [result(MemOffset)] rule - execinstr (rorxq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:R64, .Operands) => + execinstr (rorxq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:R64, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (rorxq Imm8, memOffset( MemOff), R3, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (rorxq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:R64, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (rorxq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> orMInt( lshrMInt( Mem64, uvalueMInt(andMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 63)))), shiftLeftMInt( Mem64, uvalueMInt(subMInt( mi(64, 64), andMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 63)))))) +convToRegKeys(R3) |-> orMInt( lshrMInt( Mem64, uvalueMInt(andMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 63)))), shiftLeftMInt( Mem64, uvalueMInt(subMInt( mi(64, 64), andMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 63)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/roundpd_xmm_m128_imm8.k b/semantics/memoryInstructions/roundpd_xmm_m128_imm8.k index ae8284b22..2b1e60e30 100644 --- a/semantics/memoryInstructions/roundpd_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/roundpd_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module ROUNDPD-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(roundpd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(roundpd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (roundpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (roundpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (roundpd Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (roundpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (roundpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( cvt_double_to_int64_rm(extractMInt( Mem128, 0, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_double_to_int64_rm(extractMInt( Mem128, 64, 128), handleImmediateWithSignExtend(Imm8, 8, 8)))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( cvt_double_to_int64_rm(extractMInt( Mem128, 0, 64), Imm8), cvt_double_to_int64_rm(extractMInt( Mem128, 64, 128), Imm8))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/roundps_xmm_m128_imm8.k b/semantics/memoryInstructions/roundps_xmm_m128_imm8.k index 53aba7948..1eafb838e 100644 --- a/semantics/memoryInstructions/roundps_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/roundps_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module ROUNDPS-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(roundps:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(roundps:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (roundps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (roundps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (roundps Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (roundps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (roundps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem128, 0, 32), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem128, 32, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem128, 64, 96), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_single_to_int32_rm(extractMInt( Mem128, 96, 128), handleImmediateWithSignExtend(Imm8, 8, 8)))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem128, 0, 32), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem128, 32, 64), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem128, 64, 96), Imm8), cvt_single_to_int32_rm(extractMInt( Mem128, 96, 128), Imm8))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/roundsd_xmm_m64_imm8.k b/semantics/memoryInstructions/roundsd_xmm_m64_imm8.k index 8cc87cd6b..7e64db1ec 100644 --- a/semantics/memoryInstructions/roundsd_xmm_m64_imm8.k +++ b/semantics/memoryInstructions/roundsd_xmm_m64_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module ROUNDSD-XMM-M64-IMM8 imports X86-CONFIGURATION - context execinstr(roundsd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(roundsd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (roundsd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (roundsd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (roundsd Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (roundsd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (roundsd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 192), cvt_double_to_int64_rm(Mem64, handleImmediateWithSignExtend(Imm8, 8, 8))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 192), cvt_double_to_int64_rm(Mem64, Imm8)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/roundss_xmm_m32_imm8.k b/semantics/memoryInstructions/roundss_xmm_m32_imm8.k index 40c5a4a58..87aa38cd2 100644 --- a/semantics/memoryInstructions/roundss_xmm_m32_imm8.k +++ b/semantics/memoryInstructions/roundss_xmm_m32_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module ROUNDSS-XMM-M32-IMM8 imports X86-CONFIGURATION - context execinstr(roundss:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(roundss:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (roundss:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (roundss:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (roundss Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (roundss:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (roundss:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 224), cvt_single_to_int32_rm(Mem32, handleImmediateWithSignExtend(Imm8, 8, 8))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 224), cvt_single_to_int32_rm(Mem32, Imm8)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/salb_m8_imm8.k b/semantics/memoryInstructions/salb_m8_imm8.k index 80244bebe..3f2288643 100644 --- a/semantics/memoryInstructions/salb_m8_imm8.k +++ b/semantics/memoryInstructions/salb_m8_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SALB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(salb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(salb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (salb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (salb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (salb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (salb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (salb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 9), + extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 9), MemOff, 8 ) @@ -25,17 +26,18 @@ module SALB-M8-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 9), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 9), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/sall_m32_imm8.k b/semantics/memoryInstructions/sall_m32_imm8.k index e0db794b1..429a7ea76 100644 --- a/semantics/memoryInstructions/sall_m32_imm8.k +++ b/semantics/memoryInstructions/sall_m32_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SALL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(sall:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(sall:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (sall:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (sall:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (sall Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (sall:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (sall:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 33), + extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 33), MemOff, 32 ) @@ -25,17 +26,18 @@ module SALL-M32-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 25, 26), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 25, 26), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 33), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 33), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/salq_m64_imm8.k b/semantics/memoryInstructions/salq_m64_imm8.k index 91a19ad89..055316671 100644 --- a/semantics/memoryInstructions/salq_m64_imm8.k +++ b/semantics/memoryInstructions/salq_m64_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SALQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(salq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(salq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (salq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (salq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (salq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (salq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (salq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 65), + extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 65), MemOff, 64 ) @@ -25,17 +26,18 @@ module SALQ-M64-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 57, 58), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 57, 58), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 65), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 65), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/salw_m16_imm8.k b/semantics/memoryInstructions/salw_m16_imm8.k index c83bfe219..496297d94 100644 --- a/semantics/memoryInstructions/salw_m16_imm8.k +++ b/semantics/memoryInstructions/salw_m16_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SALW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(salw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(salw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (salw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (salw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (salw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (salw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (salw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 17), + extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 17), MemOff, 16 ) @@ -25,17 +26,18 @@ module SALW-M16-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 9, 10), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 9, 10), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 17), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 17), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/sarb_m8_imm8.k b/semantics/memoryInstructions/sarb_m8_imm8.k index 59d97e5a7..5442d340f 100644 --- a/semantics/memoryInstructions/sarb_m8_imm8.k +++ b/semantics/memoryInstructions/sarb_m8_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SARB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(sarb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(sarb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (sarb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (sarb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (sarb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (sarb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (sarb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 8), + extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 8), MemOff, 8 ) @@ -25,17 +26,18 @@ module SARB-M8-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 7, 8), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 7, 8), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 8), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 8), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/sarl_m32_imm8.k b/semantics/memoryInstructions/sarl_m32_imm8.k index c73573a2f..bbbdd9d10 100644 --- a/semantics/memoryInstructions/sarl_m32_imm8.k +++ b/semantics/memoryInstructions/sarl_m32_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SARL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(sarl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(sarl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (sarl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (sarl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (sarl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (sarl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (sarl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 32), + extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 32), MemOff, 32 ) @@ -25,17 +26,18 @@ module SARL-M32-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 32, 33), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 32, 33), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 31, 32), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 25, 26), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 24, 25), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 31, 32), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 25, 26), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 24, 25), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 32), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 32), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/sarq_m64_imm8.k b/semantics/memoryInstructions/sarq_m64_imm8.k index 74a84be29..16befd942 100644 --- a/semantics/memoryInstructions/sarq_m64_imm8.k +++ b/semantics/memoryInstructions/sarq_m64_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SARQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(sarq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(sarq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (sarq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (sarq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (sarq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (sarq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (sarq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 64), + extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 64), MemOff, 64 ) @@ -25,17 +26,18 @@ module SARQ-M64-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 64, 65), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 64, 65), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 63, 64), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 57, 58), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 56, 57), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 63, 64), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 57, 58), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 56, 57), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 64), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 64), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/sarw_m16_imm8.k b/semantics/memoryInstructions/sarw_m16_imm8.k index 26983a601..12f5232da 100644 --- a/semantics/memoryInstructions/sarw_m16_imm8.k +++ b/semantics/memoryInstructions/sarw_m16_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SARW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(sarw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(sarw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (sarw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (sarw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (sarw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (sarw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (sarw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 16), + extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 16), MemOff, 16 ) @@ -25,17 +26,18 @@ module SARW-M16-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 16, 17), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 16, 17), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 15, 16), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 9, 10), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 15, 16), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 9, 10), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 16), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 16), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/sbbb_m8_imm8.k b/semantics/memoryInstructions/sbbb_m8_imm8.k index a468e8290..cc891bd13 100644 --- a/semantics/memoryInstructions/sbbb_m8_imm8.k +++ b/semantics/memoryInstructions/sbbb_m8_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SBBB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(sbbb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(sbbb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (sbbb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (sbbb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (sbbb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (sbbb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (sbbb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 9), + extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 9), MemOff, 8 ) @@ -25,17 +26,18 @@ module SBBB-M8-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem8, 3, 4)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem8, 3, 4)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem8, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem8, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/sbbl_m32_imm32.k b/semantics/memoryInstructions/sbbl_m32_imm32.k index 1ba0b6a37..876dc9a29 100644 --- a/semantics/memoryInstructions/sbbl_m32_imm32.k +++ b/semantics/memoryInstructions/sbbl_m32_imm32.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SBBL-M32-IMM32 imports X86-CONFIGURATION - context execinstr(sbbl:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(sbbl:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (sbbl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (sbbl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (sbbl Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (sbbl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (sbbl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), + extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), MemOff, 32 ) @@ -25,17 +26,18 @@ module SBBL-M32-IMM32 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/sbbl_m32_imm8.k b/semantics/memoryInstructions/sbbl_m32_imm8.k index 27e5f5e99..3c6ce1174 100644 --- a/semantics/memoryInstructions/sbbl_m32_imm8.k +++ b/semantics/memoryInstructions/sbbl_m32_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SBBL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(sbbl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(sbbl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (sbbl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (sbbl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (sbbl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (sbbl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (sbbl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), + extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), MemOff, 32 ) @@ -25,17 +26,18 @@ module SBBL-M32-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/sbbq_m64_imm32.k b/semantics/memoryInstructions/sbbq_m64_imm32.k index 411fc3817..b46c2d453 100644 --- a/semantics/memoryInstructions/sbbq_m64_imm32.k +++ b/semantics/memoryInstructions/sbbq_m64_imm32.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SBBQ-M64-IMM32 imports X86-CONFIGURATION - context execinstr(sbbq:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(sbbq:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (sbbq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (sbbq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (sbbq Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (sbbq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (sbbq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), + extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), MemOff, 64 ) @@ -25,17 +26,18 @@ module SBBQ-M64-IMM32 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/sbbq_m64_imm8.k b/semantics/memoryInstructions/sbbq_m64_imm8.k index 3e298d180..23649dcf3 100644 --- a/semantics/memoryInstructions/sbbq_m64_imm8.k +++ b/semantics/memoryInstructions/sbbq_m64_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SBBQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(sbbq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(sbbq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (sbbq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (sbbq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (sbbq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (sbbq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (sbbq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), + extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), MemOff, 64 ) @@ -25,17 +26,18 @@ module SBBQ-M64-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/sbbw_m16_imm16.k b/semantics/memoryInstructions/sbbw_m16_imm16.k index ae798b603..0b9c92500 100644 --- a/semantics/memoryInstructions/sbbw_m16_imm16.k +++ b/semantics/memoryInstructions/sbbw_m16_imm16.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SBBW-M16-IMM16 imports X86-CONFIGURATION - context execinstr(sbbw:Opcode Imm16:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(sbbw:Opcode Imm16:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (sbbw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (sbbw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (sbbw Imm16, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm16) ==Int 16 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (sbbw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (sbbw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), + extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), MemOff, 16 ) @@ -25,17 +26,18 @@ module SBBW-M16-IMM16 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm16, 11, 12), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/memoryInstructions/sbbw_m16_imm8.k b/semantics/memoryInstructions/sbbw_m16_imm8.k index e9c12872c..0676dff77 100644 --- a/semantics/memoryInstructions/sbbw_m16_imm8.k +++ b/semantics/memoryInstructions/sbbw_m16_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SBBW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(sbbw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(sbbw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (sbbw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (sbbw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (sbbw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (sbbw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (sbbw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), + extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), MemOff, 16 ) @@ -25,17 +26,18 @@ module SBBW-M16-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/shlb_m8_imm8.k b/semantics/memoryInstructions/shlb_m8_imm8.k index 740e7baee..91cb93dda 100644 --- a/semantics/memoryInstructions/shlb_m8_imm8.k +++ b/semantics/memoryInstructions/shlb_m8_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SHLB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(shlb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(shlb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (shlb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shlb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (shlb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (shlb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (shlb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 9), + extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 9), MemOff, 8 ) @@ -25,17 +26,18 @@ module SHLB-M8-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 9), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 9), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/shldl_m32_r32_imm8.k b/semantics/memoryInstructions/shldl_m32_r32_imm8.k index 1bbfba3b8..a0c66fe5f 100644 --- a/semantics/memoryInstructions/shldl_m32_r32_imm8.k +++ b/semantics/memoryInstructions/shldl_m32_r32_imm8.k @@ -4,21 +4,23 @@ requires "x86-configuration.k" module SHLDL-M32-R32-IMM8 imports X86-CONFIGURATION - context execinstr (shldl Imm8:Imm, R2:R32, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr (shldl Imm8:MInt, R2:R32, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (shldl Imm8:Imm, R2:R32, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shldl Imm8:MInt, R2:R32, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> - execinstr (shldl Imm8:Imm, R2, memOffset( MemOff), .Operands) + execinstr (shldl Imm8:MInt, R2, memOffset( MemOff), .Operands) ... + requires bitwidthMInt(Imm8) ==Int 8 rule memLoadValue(Mem32:MInt):MemLoadValue ~> - execinstr (shldl Imm8:Imm, R2:R32, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shldl Imm8:MInt, R2:R32, memOffset( MemOff:MInt):MemOffset, .Operands) => execinstr (shldl memOffset( MemOff), Mem32, getRegisterValue(R2, RSMap), - shiftCountMask(handleImmediateWithSignExtend(Imm8, 8, 8), 32), .Operands) + shiftCountMask(Imm8, 32), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (shldl memOffset( MemOff), MIdest:MInt, MIsrc:MInt, MIcount:MInt, .Operands) => . diff --git a/semantics/memoryInstructions/shldq_m64_r64_imm8.k b/semantics/memoryInstructions/shldq_m64_r64_imm8.k index df6839aed..447ebf1df 100644 --- a/semantics/memoryInstructions/shldq_m64_r64_imm8.k +++ b/semantics/memoryInstructions/shldq_m64_r64_imm8.k @@ -4,21 +4,23 @@ requires "x86-configuration.k" module SHLDQ-M64-R64-CL imports X86-CONFIGURATION - context execinstr (shldq Imm8:Imm, R2:R64, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr (shldq Imm8:MInt, R2:R64, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (shldq Imm8:Imm, R2:R64, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shldq Imm8:MInt, R2:R64, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> - execinstr (shldq Imm8:Imm, R2, memOffset( MemOff), .Operands) + execinstr (shldq Imm8:MInt, R2, memOffset( MemOff), .Operands) ... + requires bitwidthMInt(Imm8) ==Int 8 rule memLoadValue(Mem64:MInt):MemLoadValue ~> - execinstr (shldq Imm8:Imm, R2:R64, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shldq Imm8:MInt, R2:R64, memOffset( MemOff:MInt):MemOffset, .Operands) => execinstr (shldq memOffset( MemOff), Mem64, getRegisterValue(R2, RSMap), - shiftCountMask(handleImmediateWithSignExtend(Imm8, 8, 8), 64), .Operands) + shiftCountMask(Imm8, 64), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (shldq memOffset( MemOff), MIdest:MInt, MIsrc:MInt, MIcount:MInt, .Operands) => . diff --git a/semantics/memoryInstructions/shldw_m16_r16_imm8.k b/semantics/memoryInstructions/shldw_m16_r16_imm8.k index 2506c083d..4ba4a6f2e 100644 --- a/semantics/memoryInstructions/shldw_m16_r16_imm8.k +++ b/semantics/memoryInstructions/shldw_m16_r16_imm8.k @@ -4,21 +4,23 @@ requires "x86-configuration.k" module SHLDW-M16-R16-CL imports X86-CONFIGURATION - context execinstr (shldw Imm8:Imm, R2:R16, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr (shldw Imm8:MInt, R2:R16, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (shldw Imm8:Imm, R2:R16, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shldw Imm8:MInt, R2:R16, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> - execinstr (shldw Imm8:Imm, R2, memOffset( MemOff), .Operands) + execinstr (shldw Imm8:MInt, R2, memOffset( MemOff), .Operands) ... + requires bitwidthMInt(Imm8) ==Int 8 rule memLoadValue(Mem16:MInt):MemLoadValue ~> - execinstr (shldw Imm8:Imm, R2:R16, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shldw Imm8:MInt, R2:R16, memOffset( MemOff:MInt):MemOffset, .Operands) => execinstr (shldw memOffset( MemOff), Mem16, getRegisterValue(R2, RSMap), - shiftCountMask(handleImmediateWithSignExtend(Imm8, 8, 8), 32), .Operands) + shiftCountMask(Imm8, 32), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (shldw memOffset( MemOff), MIdest:MInt, MIsrc:MInt, MIcount:MInt, .Operands) => . diff --git a/semantics/memoryInstructions/shll_m32_imm8.k b/semantics/memoryInstructions/shll_m32_imm8.k index a5b988a0b..ea987184f 100644 --- a/semantics/memoryInstructions/shll_m32_imm8.k +++ b/semantics/memoryInstructions/shll_m32_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SHLL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(shll:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(shll:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (shll:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shll:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (shll Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (shll:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (shll:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 33), + extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 33), MemOff, 32 ) @@ -25,17 +26,18 @@ module SHLL-M32-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 25, 26), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 25, 26), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 33), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 33), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/shlq_m64_imm8.k b/semantics/memoryInstructions/shlq_m64_imm8.k index 7a96d38c0..62330d61f 100644 --- a/semantics/memoryInstructions/shlq_m64_imm8.k +++ b/semantics/memoryInstructions/shlq_m64_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SHLQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(shlq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(shlq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (shlq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shlq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (shlq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (shlq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (shlq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 65), + extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 65), MemOff, 64 ) @@ -25,17 +26,18 @@ module SHLQ-M64-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 57, 58), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 57, 58), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 65), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 65), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/shlw_m16_imm8.k b/semantics/memoryInstructions/shlw_m16_imm8.k index 3fcaebaf3..71db36930 100644 --- a/semantics/memoryInstructions/shlw_m16_imm8.k +++ b/semantics/memoryInstructions/shlw_m16_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SHLW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(shlw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(shlw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (shlw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shlw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (shlw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (shlw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (shlw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 17), + extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 17), MemOff, 16 ) @@ -25,17 +26,18 @@ module SHLW-M16-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 9, 10), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 9, 10), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 17), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 17), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/shrb_m8_imm8.k b/semantics/memoryInstructions/shrb_m8_imm8.k index 58f665a42..b6b5b4ebb 100644 --- a/semantics/memoryInstructions/shrb_m8_imm8.k +++ b/semantics/memoryInstructions/shrb_m8_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SHRB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(shrb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(shrb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (shrb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shrb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (shrb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (shrb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (shrb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 8), + extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 8), MemOff, 8 ) @@ -25,17 +26,18 @@ module SHRB-M8-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 7, 8), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 7, 8), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 8), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 8), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool eqMInt( extractMInt( Mem8, 0, 1), mi(1, 1))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool eqMInt( extractMInt( Mem8, 0, 1), mi(1, 1))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/shrdl_m32_r32_imm8.k b/semantics/memoryInstructions/shrdl_m32_r32_imm8.k index 8ca298761..5fc70efe8 100644 --- a/semantics/memoryInstructions/shrdl_m32_r32_imm8.k +++ b/semantics/memoryInstructions/shrdl_m32_r32_imm8.k @@ -4,21 +4,23 @@ requires "x86-configuration.k" module SHLDL-M32-R32-CL imports X86-CONFIGURATION - context execinstr (shrdl Imm8:Imm, R2:R32, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr (shrdl Imm8:MInt, R2:R32, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (shrdl Imm8:Imm, R2:R32, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shrdl Imm8:MInt, R2:R32, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> - execinstr (shrdl Imm8:Imm, R2, memOffset( MemOff), .Operands) + execinstr (shrdl Imm8:MInt, R2, memOffset( MemOff), .Operands) ... + requires bitwidthMInt(Imm8) ==Int 8 rule memLoadValue(Mem32:MInt):MemLoadValue ~> - execinstr (shrdl Imm8:Imm, R2:R32, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shrdl Imm8:MInt, R2:R32, memOffset( MemOff:MInt):MemOffset, .Operands) => execinstr (shrdl memOffset( MemOff), Mem32, getRegisterValue(R2, RSMap), - shiftCountMask(handleImmediateWithSignExtend(Imm8, 8, 8), 32), .Operands) + shiftCountMask(Imm8, 32), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (shrdl memOffset( MemOff), MIdest:MInt, MIsrc:MInt, MIcount:MInt, .Operands) => . diff --git a/semantics/memoryInstructions/shrdq_m64_r64_imm8.k b/semantics/memoryInstructions/shrdq_m64_r64_imm8.k index 2959c8819..2cb4686ca 100644 --- a/semantics/memoryInstructions/shrdq_m64_r64_imm8.k +++ b/semantics/memoryInstructions/shrdq_m64_r64_imm8.k @@ -4,21 +4,23 @@ requires "x86-configuration.k" module SHRDQ-M64-R64-CL imports X86-CONFIGURATION - context execinstr (shrdq Imm8:Imm, R2:R64, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr (shrdq Imm8:MInt, R2:R64, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (shrdq Imm8:Imm, R2:R64, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shrdq Imm8:MInt, R2:R64, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> - execinstr (shrdq Imm8:Imm, R2, memOffset( MemOff), .Operands) + execinstr (shrdq Imm8:MInt, R2, memOffset( MemOff), .Operands) ... + requires bitwidthMInt(Imm8) ==Int 8 rule memLoadValue(Mem64:MInt):MemLoadValue ~> - execinstr (shrdq Imm8:Imm, R2:R64, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shrdq Imm8:MInt, R2:R64, memOffset( MemOff:MInt):MemOffset, .Operands) => execinstr (shrdq memOffset( MemOff), Mem64, getRegisterValue(R2, RSMap), - shiftCountMask(handleImmediateWithSignExtend(Imm8, 8, 8), 64), .Operands) + shiftCountMask(Imm8, 64), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (shrdq memOffset( MemOff), MIdest:MInt, MIsrc:MInt, MIcount:MInt, .Operands) => . diff --git a/semantics/memoryInstructions/shrdw_m16_r16_imm8.k b/semantics/memoryInstructions/shrdw_m16_r16_imm8.k index 53c6df4b2..dca5679cf 100644 --- a/semantics/memoryInstructions/shrdw_m16_r16_imm8.k +++ b/semantics/memoryInstructions/shrdw_m16_r16_imm8.k @@ -4,21 +4,23 @@ requires "x86-configuration.k" module SHLDW-M16-R16-CL imports X86-CONFIGURATION - context execinstr (shrdw Imm8:Imm, R2:R16, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr (shrdw Imm8:MInt, R2:R16, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (shrdw Imm8:Imm, R2:R16, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shrdw Imm8:MInt, R2:R16, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> - execinstr (shrdw Imm8:Imm, R2, memOffset( MemOff), .Operands) + execinstr (shrdw Imm8:MInt, R2, memOffset( MemOff), .Operands) ... + requires bitwidthMInt(Imm8) ==Int 8 rule memLoadValue(Mem16:MInt):MemLoadValue ~> - execinstr (shrdw Imm8:Imm, R2:R16, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shrdw Imm8:MInt, R2:R16, memOffset( MemOff:MInt):MemOffset, .Operands) => execinstr (shrdw memOffset( MemOff), Mem16, getRegisterValue(R2, RSMap), - shiftCountMask(handleImmediateWithSignExtend(Imm8, 8, 8), 32), .Operands) + shiftCountMask(Imm8, 32), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (shrdw memOffset( MemOff), MIdest:MInt, MIsrc:MInt, MIcount:MInt, .Operands) => . diff --git a/semantics/memoryInstructions/shrl_m32_imm8.k b/semantics/memoryInstructions/shrl_m32_imm8.k index 971f379f2..b45c71d28 100644 --- a/semantics/memoryInstructions/shrl_m32_imm8.k +++ b/semantics/memoryInstructions/shrl_m32_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SHRL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(shrl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(shrl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (shrl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shrl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (shrl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (shrl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (shrl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 32), + extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 32), MemOff, 32 ) @@ -25,17 +26,18 @@ module SHRL-M32-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 32, 33), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 32, 33), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 31, 32), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 25, 26), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 24, 25), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 31, 32), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 25, 26), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 24, 25), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 32), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 32), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/shrq_m64_imm8.k b/semantics/memoryInstructions/shrq_m64_imm8.k index 476766193..24ad06c3a 100644 --- a/semantics/memoryInstructions/shrq_m64_imm8.k +++ b/semantics/memoryInstructions/shrq_m64_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SHRQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(shrq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(shrq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (shrq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shrq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (shrq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (shrq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (shrq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 64), + extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 64), MemOff, 64 ) @@ -25,17 +26,18 @@ module SHRQ-M64-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 64, 65), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 64, 65), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 63, 64), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 57, 58), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 56, 57), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 63, 64), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 57, 58), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 56, 57), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 64), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 64), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1)) andBool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1)) andBool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/shrw_m16_imm8.k b/semantics/memoryInstructions/shrw_m16_imm8.k index a86573f61..04927fdac 100644 --- a/semantics/memoryInstructions/shrw_m16_imm8.k +++ b/semantics/memoryInstructions/shrw_m16_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SHRW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(shrw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(shrw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (shrw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shrw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (shrw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (shrw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (shrw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 16), + extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 16), MemOff, 16 ) @@ -25,17 +26,18 @@ module SHRW-M16-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 16, 17), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 16, 17), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 15, 16), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 9, 10), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 15, 16), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 9, 10), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 16), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 16), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/shufpd_xmm_m128_imm8.k b/semantics/memoryInstructions/shufpd_xmm_m128_imm8.k index 464bcd45f..761fdce69 100644 --- a/semantics/memoryInstructions/shufpd_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/shufpd_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module SHUFPD-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(shufpd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(shufpd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (shufpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (shufpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (shufpd Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (shufpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (shufpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( Mem128, 0, 64) #else extractMInt( Mem128, 64, 128) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R3, RSMap), 192, 256) #fi))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( Mem128, 0, 64) #else extractMInt( Mem128, 64, 128) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R3, RSMap), 192, 256) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/shufps_xmm_m128_imm8.k b/semantics/memoryInstructions/shufps_xmm_m128_imm8.k index 97946c5ec..c51379b39 100644 --- a/semantics/memoryInstructions/shufps_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/shufps_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module SHUFPS-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(shufps:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(shufps:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (shufps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (shufps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (shufps Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (shufps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (shufps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( Mem128, 0, 32) #else extractMInt( Mem128, 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( Mem128, 0, 32) #else extractMInt( Mem128, 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( Mem128, 0, 32) #else extractMInt( Mem128, 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( Mem128, 0, 32) #else extractMInt( Mem128, 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/subb_m8_imm8.k b/semantics/memoryInstructions/subb_m8_imm8.k index d20f17076..a33f9a8b6 100644 --- a/semantics/memoryInstructions/subb_m8_imm8.k +++ b/semantics/memoryInstructions/subb_m8_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SUBB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(subb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(subb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (subb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (subb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (subb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (subb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (subb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 9), + extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 9), MemOff, 8 ) @@ -25,17 +26,18 @@ module SUBB-M8-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem8, 3, 4)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem8, 3, 4)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem8, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem8, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/subl_m32_imm32.k b/semantics/memoryInstructions/subl_m32_imm32.k index 8a939714d..0c9d0d0c1 100644 --- a/semantics/memoryInstructions/subl_m32_imm32.k +++ b/semantics/memoryInstructions/subl_m32_imm32.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SUBL-M32-IMM32 imports X86-CONFIGURATION - context execinstr(subl:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(subl:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (subl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (subl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (subl Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (subl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (subl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 33), + extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 33), MemOff, 32 ) @@ -25,17 +26,18 @@ module SUBL-M32-IMM32 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/subl_m32_imm8.k b/semantics/memoryInstructions/subl_m32_imm8.k index f59e7d68a..31ff4f755 100644 --- a/semantics/memoryInstructions/subl_m32_imm8.k +++ b/semantics/memoryInstructions/subl_m32_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SUBL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(subl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(subl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (subl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (subl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (subl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (subl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (subl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 33), + extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 33), MemOff, 32 ) @@ -25,17 +26,18 @@ module SUBL-M32-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/subq_m64_imm32.k b/semantics/memoryInstructions/subq_m64_imm32.k index 426fb7c3c..358e84cf9 100644 --- a/semantics/memoryInstructions/subq_m64_imm32.k +++ b/semantics/memoryInstructions/subq_m64_imm32.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SUBQ-M64-IMM32 imports X86-CONFIGURATION - context execinstr(subq:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(subq:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (subq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (subq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (subq Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (subq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (subq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 65), + extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 65), MemOff, 64 ) @@ -25,17 +26,18 @@ module SUBQ-M64-IMM32 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/subq_m64_imm8.k b/semantics/memoryInstructions/subq_m64_imm8.k index 60c284973..e890fec12 100644 --- a/semantics/memoryInstructions/subq_m64_imm8.k +++ b/semantics/memoryInstructions/subq_m64_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SUBQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(subq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(subq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (subq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (subq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (subq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (subq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (subq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 65), + extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 65), MemOff, 64 ) @@ -25,17 +26,18 @@ module SUBQ-M64-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/subw_m16_imm16.k b/semantics/memoryInstructions/subw_m16_imm16.k index fe95e04b7..f2c0ed3da 100644 --- a/semantics/memoryInstructions/subw_m16_imm16.k +++ b/semantics/memoryInstructions/subw_m16_imm16.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SUBW-M16-IMM16 imports X86-CONFIGURATION - context execinstr(subw:Opcode Imm16:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(subw:Opcode Imm16:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (subw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (subw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (subw Imm16, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm16) ==Int 16 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (subw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (subw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 17), + extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 17), MemOff, 16 ) @@ -25,17 +26,18 @@ module SUBW-M16-IMM16 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm16, 11, 12), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/memoryInstructions/subw_m16_imm8.k b/semantics/memoryInstructions/subw_m16_imm8.k index 67a007e25..b791b6e34 100644 --- a/semantics/memoryInstructions/subw_m16_imm8.k +++ b/semantics/memoryInstructions/subw_m16_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SUBW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(subw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(subw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (subw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (subw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (subw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (subw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (subw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 17), + extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 17), MemOff, 16 ) @@ -25,17 +26,18 @@ module SUBW-M16-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/testb_m8_imm8.k b/semantics/memoryInstructions/testb_m8_imm8.k index 9ebbc5ec5..57fe23957 100644 --- a/semantics/memoryInstructions/testb_m8_imm8.k +++ b/semantics/memoryInstructions/testb_m8_imm8.k @@ -4,32 +4,34 @@ requires "x86-configuration.k" module TESTB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(testb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(testb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (testb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (testb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (testb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (testb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (testb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => . ... RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem8, 7, 8), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem8, 6, 7), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 5, 6), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 4, 5), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 3, 4), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 2, 3), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 1, 2), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem8, 7, 8), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem8, 6, 7), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 5, 6), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 4, 5), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 3, 4), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 2, 3), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 1, 2), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 0, 1), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( Mem8, handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( Mem8, Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( Mem8, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> andMInt( extractMInt( Mem8, 0, 1), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/testl_m32_imm32.k b/semantics/memoryInstructions/testl_m32_imm32.k index f3584f5f9..c99574ca6 100644 --- a/semantics/memoryInstructions/testl_m32_imm32.k +++ b/semantics/memoryInstructions/testl_m32_imm32.k @@ -4,32 +4,34 @@ requires "x86-configuration.k" module TESTL-M32-IMM32 imports X86-CONFIGURATION - context execinstr(testl:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(testl:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (testl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (testl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (testl Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (testl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (testl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => . ... RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem32, 31, 32), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem32, 30, 31), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 29, 30), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 28, 29), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 27, 28), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 26, 27), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 25, 26), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 24, 25), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem32, 31, 32), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem32, 30, 31), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 29, 30), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 28, 29), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 27, 28), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 26, 27), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 25, 26), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 24, 25), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( Mem32, handleImmediateWithSignExtend(Imm32, 32, 32)), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( Mem32, Imm32), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( Mem32, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)) +"SF" |-> andMInt( extractMInt( Mem32, 0, 1), extractMInt( Imm32, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/testq_m64_imm32.k b/semantics/memoryInstructions/testq_m64_imm32.k index 5058291c1..6f173a07d 100644 --- a/semantics/memoryInstructions/testq_m64_imm32.k +++ b/semantics/memoryInstructions/testq_m64_imm32.k @@ -4,32 +4,34 @@ requires "x86-configuration.k" module TESTQ-M64-IMM32 imports X86-CONFIGURATION - context execinstr(testq:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(testq:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (testq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (testq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (testq Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (testq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (testq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => . ... RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem64, 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem64, 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem64, 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem64, 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( Mem64, mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( Mem64, mi(64, svalueMInt(Imm32))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( Mem64, 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)) +"SF" |-> andMInt( extractMInt( Mem64, 0, 1), extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/testw_m16_imm16.k b/semantics/memoryInstructions/testw_m16_imm16.k index 03e992232..a901cfbcd 100644 --- a/semantics/memoryInstructions/testw_m16_imm16.k +++ b/semantics/memoryInstructions/testw_m16_imm16.k @@ -4,32 +4,34 @@ requires "x86-configuration.k" module TESTW-M16-IMM16 imports X86-CONFIGURATION - context execinstr(testw:Opcode Imm16:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(testw:Opcode Imm16:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (testw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (testw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (testw Imm16, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm16) ==Int 16 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (testw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (testw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => . ... RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem16, 15, 16), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 15, 16)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem16, 14, 15), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 14, 15)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 13, 14), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 13, 14)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 12, 13), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 12, 13)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 11, 12), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 10, 11), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 10, 11)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 9, 10), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 9, 10)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 8, 9), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem16, 15, 16), extractMInt( Imm16, 15, 16)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem16, 14, 15), extractMInt( Imm16, 14, 15)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 13, 14), extractMInt( Imm16, 13, 14)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 12, 13), extractMInt( Imm16, 12, 13)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 11, 12), extractMInt( Imm16, 11, 12)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 10, 11), extractMInt( Imm16, 10, 11)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 9, 10), extractMInt( Imm16, 9, 10)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 8, 9), extractMInt( Imm16, 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( Mem16, handleImmediateWithSignExtend(Imm16, 16, 16)), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( Mem16, Imm16), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( Mem16, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)) +"SF" |-> andMInt( extractMInt( Mem16, 0, 1), extractMInt( Imm16, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/memoryInstructions/vblendpd_xmm_xmm_m128_imm8.k b/semantics/memoryInstructions/vblendpd_xmm_xmm_m128_imm8.k index ed8791ad7..4283994a4 100644 --- a/semantics/memoryInstructions/vblendpd_xmm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vblendpd_xmm_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VBLENDPD-XMM-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vblendpd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vblendpd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vblendpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vblendpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vblendpd Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vblendpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vblendpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( Mem128, 0, 64) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 256) #else extractMInt( Mem128, 64, 128) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( Mem128, 0, 64) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 256) #else extractMInt( Mem128, 64, 128) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vblendpd_ymm_ymm_m256_imm8.k b/semantics/memoryInstructions/vblendpd_ymm_ymm_m256_imm8.k index e889d3d3d..242024e71 100644 --- a/semantics/memoryInstructions/vblendpd_ymm_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vblendpd_ymm_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VBLENDPD-YMM-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vblendpd:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] + context execinstr(vblendpd:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vblendpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vblendpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vblendpd Imm8, memOffset( MemOff), R3:Ymm, R4:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vblendpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vblendpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 64) #else extractMInt( Mem256, 0, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 128) #else extractMInt( Mem256, 64, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( Mem256, 128, 192) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 256) #else extractMInt( Mem256, 192, 256) #fi)))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 64) #else extractMInt( Mem256, 0, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 128) #else extractMInt( Mem256, 64, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( Mem256, 128, 192) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 256) #else extractMInt( Mem256, 192, 256) #fi)))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vblendps_xmm_xmm_m128_imm8.k b/semantics/memoryInstructions/vblendps_xmm_xmm_m128_imm8.k index d1f1ab93a..47def516b 100644 --- a/semantics/memoryInstructions/vblendps_xmm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vblendps_xmm_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VBLENDPS-XMM-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vblendps:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vblendps:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vblendps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vblendps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vblendps Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vblendps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vblendps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( Mem128, 0, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( Mem128, 32, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( Mem128, 64, 96) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( Mem128, 96, 128) #fi))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( Mem128, 0, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( Mem128, 32, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( Mem128, 64, 96) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( Mem128, 96, 128) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vblendps_ymm_ymm_m256_imm8.k b/semantics/memoryInstructions/vblendps_ymm_ymm_m256_imm8.k index d386aeb48..b346a3093 100644 --- a/semantics/memoryInstructions/vblendps_ymm_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vblendps_ymm_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VBLENDPS-YMM-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vblendps:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] + context execinstr(vblendps:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vblendps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vblendps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vblendps Imm8, memOffset( MemOff), R3:Ymm, R4:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vblendps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vblendps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( Mem256, 0, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( Mem256, 32, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 96) #else extractMInt( Mem256, 64, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 96, 128) #else extractMInt( Mem256, 96, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( Mem256, 128, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( Mem256, 160, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( Mem256, 192, 224) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( Mem256, 224, 256) #fi)))))))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( Mem256, 0, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( Mem256, 32, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 96) #else extractMInt( Mem256, 64, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 96, 128) #else extractMInt( Mem256, 96, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( Mem256, 128, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( Mem256, 160, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( Mem256, 192, 224) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( Mem256, 224, 256) #fi)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vcmppd_xmm_xmm_m128_imm8.k b/semantics/memoryInstructions/vcmppd_xmm_xmm_m128_imm8.k index 8d785b0de..bea305dd9 100644 --- a/semantics/memoryInstructions/vcmppd_xmm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vcmppd_xmm_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VCMPPD-XMM-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vcmppd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vcmppd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vcmppd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vcmppd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vcmppd Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vcmppd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vcmppd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( Mem128, 0, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( Mem128, 64, 128), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( Mem128, 0, 64), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( Mem128, 64, 128), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vcmppd_ymm_ymm_m256_imm8.k b/semantics/memoryInstructions/vcmppd_ymm_ymm_m256_imm8.k index 8366dc03d..c31681d35 100644 --- a/semantics/memoryInstructions/vcmppd_ymm_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vcmppd_ymm_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VCMPPD-YMM-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vcmppd:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] + context execinstr(vcmppd:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vcmppd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vcmppd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vcmppd Imm8, memOffset( MemOff), R3:Ymm, R4:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vcmppd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vcmppd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 0, 64), extractMInt( Mem256, 0, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 64, 128), extractMInt( Mem256, 64, 128), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( Mem256, 128, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( Mem256, 192, 256), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi)))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 0, 64), extractMInt( Mem256, 0, 64), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 64, 128), extractMInt( Mem256, 64, 128), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( Mem256, 128, 192), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( Mem256, 192, 256), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi)))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vcmpps_xmm_xmm_m128_imm8.k b/semantics/memoryInstructions/vcmpps_xmm_xmm_m128_imm8.k index cc4f2e0c1..c88249a4e 100644 --- a/semantics/memoryInstructions/vcmpps_xmm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vcmpps_xmm_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VCMPPS-XMM-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vcmpps:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vcmpps:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vcmpps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vcmpps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vcmpps Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vcmpps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vcmpps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vcmpps_ymm_ymm_m256_imm8.k b/semantics/memoryInstructions/vcmpps_ymm_ymm_m256_imm8.k index 3d32d8c9c..7f735164b 100644 --- a/semantics/memoryInstructions/vcmpps_ymm_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vcmpps_ymm_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VCMPPS-YMM-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vcmpps:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] + context execinstr(vcmpps:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vcmpps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vcmpps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vcmpps Imm8, memOffset( MemOff), R3:Ymm, R4:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vcmpps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vcmpps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( Mem256, 0, 32), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( Mem256, 32, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( Mem256, 64, 96), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( Mem256, 96, 128), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem256, 128, 160), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem256, 160, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem256, 192, 224), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem256, 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi)))))))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( Mem256, 0, 32), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( Mem256, 32, 64), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( Mem256, 64, 96), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( Mem256, 96, 128), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem256, 128, 160), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem256, 160, 192), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem256, 192, 224), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem256, 224, 256), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vcmpsd_xmm_xmm_m64_imm8.k b/semantics/memoryInstructions/vcmpsd_xmm_xmm_m64_imm8.k index 674c8a278..878e37b39 100644 --- a/semantics/memoryInstructions/vcmpsd_xmm_xmm_m64_imm8.k +++ b/semantics/memoryInstructions/vcmpsd_xmm_xmm_m64_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VCMPSD-XMM-XMM-M64-IMM8 imports X86-CONFIGURATION - context execinstr(vcmpsd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vcmpsd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vcmpsd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vcmpsd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (vcmpsd Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (vcmpsd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (vcmpsd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 192), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), Mem64, handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 192), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), Mem64, Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vcmpss_xmm_xmm_m32_imm8.k b/semantics/memoryInstructions/vcmpss_xmm_xmm_m32_imm8.k index fee669aa4..5722e531c 100644 --- a/semantics/memoryInstructions/vcmpss_xmm_xmm_m32_imm8.k +++ b/semantics/memoryInstructions/vcmpss_xmm_xmm_m32_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VCMPSS-XMM-XMM-M32-IMM8 imports X86-CONFIGURATION - context execinstr(vcmpss:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vcmpss:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vcmpss:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vcmpss:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (vcmpss Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (vcmpss:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (vcmpss:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 224), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), Mem32, handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 224), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), Mem32, Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vcvtps2ph_m128_ymm_imm8.k b/semantics/memoryInstructions/vcvtps2ph_m128_ymm_imm8.k index 6f287ad40..4d80b2d96 100644 --- a/semantics/memoryInstructions/vcvtps2ph_m128_ymm_imm8.k +++ b/semantics/memoryInstructions/vcvtps2ph_m128_ymm_imm8.k @@ -4,24 +4,26 @@ requires "x86-configuration.k" module VCVTPS2PH-M128-YMM-IMM8 imports X86-CONFIGURATION - context execinstr(vcvtps2ph:Opcode Imm8:Imm, R2:Ymm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(vcvtps2ph:Opcode Imm8:MInt, R2:Ymm, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (vcvtps2ph:Opcode Imm8:Imm, R2:Ymm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (vcvtps2ph:Opcode Imm8:MInt, R2:Ymm, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vcvtps2ph Imm8, R2:Ymm, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vcvtps2ph:Opcode Imm8:Imm, R2:Ymm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vcvtps2ph:Opcode Imm8:MInt, R2:Ymm, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 0, 32), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 32, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 64, 96), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 96, 128), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 128, 160), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 160, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 192, 224), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8))))))))), + concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 0, 32), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 32, 64), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 64, 96), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 96, 128), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 128, 160), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 160, 192), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 192, 224), Imm8), cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), Imm8)))))))), MemOff, 128 ) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vcvtps2ph_m64_xmm_imm8.k b/semantics/memoryInstructions/vcvtps2ph_m64_xmm_imm8.k index 34710e494..6e9b8503b 100644 --- a/semantics/memoryInstructions/vcvtps2ph_m64_xmm_imm8.k +++ b/semantics/memoryInstructions/vcvtps2ph_m64_xmm_imm8.k @@ -4,24 +4,26 @@ requires "x86-configuration.k" module VCVTPS2PH-M64-XMM-IMM8 imports X86-CONFIGURATION - context execinstr(vcvtps2ph:Opcode Imm8:Imm, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(vcvtps2ph:Opcode Imm8:MInt, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (vcvtps2ph:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (vcvtps2ph:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (vcvtps2ph Imm8, R2:Xmm, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (vcvtps2ph:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (vcvtps2ph:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 128, 160), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 160, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 192, 224), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8))))), + concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 128, 160), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 160, 192), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 192, 224), Imm8), cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), Imm8)))), MemOff, 64 ) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vdppd_xmm_xmm_m128_imm8.k b/semantics/memoryInstructions/vdppd_xmm_xmm_m128_imm8.k index 3083d42da..ee49b48a4 100644 --- a/semantics/memoryInstructions/vdppd_xmm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vdppd_xmm_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VDPPD-XMM-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vdppd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vdppd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vdppd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vdppd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vdppd Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vdppd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vdppd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( Mem128, 64, 128)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( Mem128, 0, 64)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( Mem128, 64, 128)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( Mem128, 0, 64)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( Mem128, 64, 128)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( Mem128, 0, 64)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( Mem128, 64, 128)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( Mem128, 0, 64)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vdpps_xmm_xmm_m128_imm8.k b/semantics/memoryInstructions/vdpps_xmm_xmm_m128_imm8.k index dec7b45d3..0558c9571 100644 --- a/semantics/memoryInstructions/vdpps_xmm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vdpps_xmm_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VDPPS-XMM-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vdpps:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vdpps:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vdpps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vdpps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vdpps Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vdpps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vdpps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vdpps_ymm_ymm_m256_imm8.k b/semantics/memoryInstructions/vdpps_ymm_ymm_m256_imm8.k index 6df7c4137..58a41a41b 100644 --- a/semantics/memoryInstructions/vdpps_ymm_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vdpps_ymm_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VDPPS-YMM-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vdpps:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] + context execinstr(vdpps:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vdpps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vdpps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vdpps Imm8, memOffset( MemOff), R3:Ymm, R4:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vdpps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vdpps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( Mem256, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( Mem256, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( Mem256, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( Mem256, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( Mem256, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( Mem256, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( Mem256, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( Mem256, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( Mem256, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( Mem256, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( Mem256, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( Mem256, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( Mem256, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( Mem256, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( Mem256, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( Mem256, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem256, 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem256, 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem256, 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem256, 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem256, 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem256, 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem256, 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem256, 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem256, 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem256, 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem256, 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem256, 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem256, 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem256, 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem256, 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem256, 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi))) +convToRegKeys(R4) |-> concatenateMInt( concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( Mem256, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( Mem256, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( Mem256, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( Mem256, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( Mem256, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( Mem256, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( Mem256, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( Mem256, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( Mem256, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( Mem256, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( Mem256, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( Mem256, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( Mem256, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( Mem256, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( Mem256, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( Mem256, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem256, 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem256, 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem256, 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem256, 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem256, 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem256, 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem256, 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem256, 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem256, 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem256, 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem256, 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem256, 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem256, 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem256, 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem256, 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem256, 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vextractf128_m128_ymm_imm8.k b/semantics/memoryInstructions/vextractf128_m128_ymm_imm8.k index 270679406..d1fb6becd 100644 --- a/semantics/memoryInstructions/vextractf128_m128_ymm_imm8.k +++ b/semantics/memoryInstructions/vextractf128_m128_ymm_imm8.k @@ -4,24 +4,26 @@ requires "x86-configuration.k" module VEXTRACTF128-M128-YMM-IMM8 imports X86-CONFIGURATION - context execinstr(vextractf128:Opcode Imm8:Imm, R2:Ymm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(vextractf128:Opcode Imm8:MInt, R2:Ymm, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (vextractf128:Opcode Imm8:Imm, R2:Ymm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (vextractf128:Opcode Imm8:MInt, R2:Ymm, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vextractf128 Imm8, R2:Ymm, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vextractf128:Opcode Imm8:Imm, R2:Ymm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vextractf128:Opcode Imm8:MInt, R2:Ymm, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi), + (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi), MemOff, 128 ) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vextracti128_m128_ymm_imm8.k b/semantics/memoryInstructions/vextracti128_m128_ymm_imm8.k index edc4a4c40..56d8cf7c0 100644 --- a/semantics/memoryInstructions/vextracti128_m128_ymm_imm8.k +++ b/semantics/memoryInstructions/vextracti128_m128_ymm_imm8.k @@ -4,24 +4,26 @@ requires "x86-configuration.k" module VEXTRACTI128-M128-YMM-IMM8 imports X86-CONFIGURATION - context execinstr(vextracti128:Opcode Imm8:Imm, R2:Ymm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(vextracti128:Opcode Imm8:MInt, R2:Ymm, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (vextracti128:Opcode Imm8:Imm, R2:Ymm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (vextracti128:Opcode Imm8:MInt, R2:Ymm, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vextracti128 Imm8, R2:Ymm, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vextracti128:Opcode Imm8:Imm, R2:Ymm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vextracti128:Opcode Imm8:MInt, R2:Ymm, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi), + (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi), MemOff, 128 ) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vextractps_m32_xmm_imm8.k b/semantics/memoryInstructions/vextractps_m32_xmm_imm8.k index 0e7977b47..fadb3b7b6 100644 --- a/semantics/memoryInstructions/vextractps_m32_xmm_imm8.k +++ b/semantics/memoryInstructions/vextractps_m32_xmm_imm8.k @@ -4,24 +4,26 @@ requires "x86-configuration.k" module VEXTRACTPS-M32-XMM-IMM8 imports X86-CONFIGURATION - context execinstr(vextractps:Opcode Imm8:Imm, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(vextractps:Opcode Imm8:MInt, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (vextractps:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (vextractps:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (vextractps Imm8, R2:Xmm, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (vextractps:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (vextractps:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128), + extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128), MemOff, 32 ) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vinsertf128_ymm_ymm_m128_imm8.k b/semantics/memoryInstructions/vinsertf128_ymm_ymm_m128_imm8.k index d07b6a84e..97acdb03b 100644 --- a/semantics/memoryInstructions/vinsertf128_ymm_ymm_m128_imm8.k +++ b/semantics/memoryInstructions/vinsertf128_ymm_ymm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VINSERTF128-YMM-YMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vinsertf128:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] + context execinstr(vinsertf128:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vinsertf128:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vinsertf128:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vinsertf128 Imm8, memOffset( MemOff), R3:Ymm, R4:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vinsertf128:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vinsertf128:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), Mem128) #else concatenateMInt( Mem128, extractMInt( getParentValue(R3, RSMap), 128, 256)) #fi) +convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), Mem128) #else concatenateMInt( Mem128, extractMInt( getParentValue(R3, RSMap), 128, 256)) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vinserti128_ymm_ymm_m128_imm8.k b/semantics/memoryInstructions/vinserti128_ymm_ymm_m128_imm8.k index a978ac780..a7aef1819 100644 --- a/semantics/memoryInstructions/vinserti128_ymm_ymm_m128_imm8.k +++ b/semantics/memoryInstructions/vinserti128_ymm_ymm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VINSERTI128-YMM-YMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vinserti128:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] + context execinstr(vinserti128:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vinserti128:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vinserti128:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vinserti128 Imm8, memOffset( MemOff), R3:Ymm, R4:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vinserti128:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vinserti128:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), Mem128) #else concatenateMInt( Mem128, extractMInt( getParentValue(R3, RSMap), 128, 256)) #fi) +convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), Mem128) #else concatenateMInt( Mem128, extractMInt( getParentValue(R3, RSMap), 128, 256)) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vinsertps_xmm_xmm_m32_imm8.k b/semantics/memoryInstructions/vinsertps_xmm_xmm_m32_imm8.k index 9f9673cd7..543d56dda 100644 --- a/semantics/memoryInstructions/vinsertps_xmm_xmm_m32_imm8.k +++ b/semantics/memoryInstructions/vinsertps_xmm_xmm_m32_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VINSERTPS-XMM-XMM-M32-IMM8 imports X86-CONFIGURATION - context execinstr(vinsertps:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vinsertps:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vinsertps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vinsertps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (vinsertps Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (vinsertps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (vinsertps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else Mem32 #fi) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then Mem32 #else extractMInt( getParentValue(R3, RSMap), 160, 192) #fi) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then Mem32 #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then Mem32 #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else Mem32 #fi) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then Mem32 #else extractMInt( getParentValue(R3, RSMap), 160, 192) #fi) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then Mem32 #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then Mem32 #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vmpsadbw_xmm_xmm_m128_imm8.k b/semantics/memoryInstructions/vmpsadbw_xmm_xmm_m128_imm8.k index 2f4425bda..30a167788 100644 --- a/semantics/memoryInstructions/vmpsadbw_xmm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vmpsadbw_xmm_xmm_m128_imm8.k @@ -13,43 +13,44 @@ module VMPSADBW-XMM-XMM-M128-IMM8 rule memLoadValue(MemVal:MInt):MemLoadValue ~> - execinstr (vmpsadbw Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vmpsadbw Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => execinstr (vmpsadbw selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 7 , 0 ), + extractMInt(Imm8, 6, 8), 7 , 0 ), selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 15, 8 ), + extractMInt(Imm8, 6, 8), 15, 8 ), selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 23, 16), + extractMInt(Imm8, 6, 8), 23, 16), selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 31, 24), + extractMInt(Imm8, 6, 8), 31, 24), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 7 , 0), + extractMInt(Imm8, 5, 6), 7 , 0), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 15, 8), + extractMInt(Imm8, 5, 6), 15, 8), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 23, 16), + extractMInt(Imm8, 5, 6), 23, 16), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 31, 24), + extractMInt(Imm8, 5, 6), 31, 24), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 39, 32), + extractMInt(Imm8, 5, 6), 39, 32), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 47, 40), + extractMInt(Imm8, 5, 6), 47, 40), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 55, 48), + extractMInt(Imm8, 5, 6), 55, 48), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 63, 56), + extractMInt(Imm8, 5, 6), 63, 56), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 71, 64), + extractMInt(Imm8, 5, 6), 71, 64), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 79, 72), + extractMInt(Imm8, 5, 6), 79, 72), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 87, 80), + extractMInt(Imm8, 5, 6), 87, 80), R3:Xmm, .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (vmpsadbw diff --git a/semantics/memoryInstructions/vmpsadbw_ymm_ymm_m256_imm8.k b/semantics/memoryInstructions/vmpsadbw_ymm_ymm_m256_imm8.k index 6f5ecf59f..e196b0265 100644 --- a/semantics/memoryInstructions/vmpsadbw_ymm_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vmpsadbw_ymm_ymm_m256_imm8.k @@ -14,93 +14,94 @@ module VMPSADBW-YMM-YMM-M256-IMM8 rule memLoadValue(MemVal:MInt):MemLoadValue ~> - execinstr (vmpsadbw Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vmpsadbw Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => execinstr (vmpsadbw //Low slices selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 7 , 0 ), + extractMInt(Imm8, 6, 8), 7 , 0 ), selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 15, 8 ), + extractMInt(Imm8, 6, 8), 15, 8 ), selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 23, 16), + extractMInt(Imm8, 6, 8), 23, 16), selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 31, 24), + extractMInt(Imm8, 6, 8), 31, 24), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 7 , 0), + extractMInt(Imm8, 5, 6), 7 , 0), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 15, 8), + extractMInt(Imm8, 5, 6), 15, 8), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 23, 16), + extractMInt(Imm8, 5, 6), 23, 16), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 31, 24), + extractMInt(Imm8, 5, 6), 31, 24), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 39, 32), + extractMInt(Imm8, 5, 6), 39, 32), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 47, 40), + extractMInt(Imm8, 5, 6), 47, 40), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 55, 48), + extractMInt(Imm8, 5, 6), 55, 48), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 63, 56), + extractMInt(Imm8, 5, 6), 63, 56), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 71, 64), + extractMInt(Imm8, 5, 6), 71, 64), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 79, 72), + extractMInt(Imm8, 5, 6), 79, 72), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 87, 80), + extractMInt(Imm8, 5, 6), 87, 80), //High slices selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 3, 5), 7 +Int + extractMInt(Imm8, 3, 5), 7 +Int 128, 0 +Int 128), selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 3, 5), 15+Int + extractMInt(Imm8, 3, 5), 15+Int 128, 8 +Int 128), selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 3, 5), 23+Int + extractMInt(Imm8, 3, 5), 23+Int 128, 16+Int 128), selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 3, 5), 31+Int + extractMInt(Imm8, 3, 5), 31+Int 128, 24+Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 7 + extractMInt(Imm8, 2, 3), 7 +Int 128, 0 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 15 + extractMInt(Imm8, 2, 3), 15 +Int 128, 8 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 23 + extractMInt(Imm8, 2, 3), 23 +Int 128, 16 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 31 + extractMInt(Imm8, 2, 3), 31 +Int 128, 24 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 39 + extractMInt(Imm8, 2, 3), 39 +Int 128, 32 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 47 + extractMInt(Imm8, 2, 3), 47 +Int 128, 40 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 55 + extractMInt(Imm8, 2, 3), 55 +Int 128, 48 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 63 + extractMInt(Imm8, 2, 3), 63 +Int 128, 56 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 71 + extractMInt(Imm8, 2, 3), 71 +Int 128, 64 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 79 + extractMInt(Imm8, 2, 3), 79 +Int 128, 72 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 87 + extractMInt(Imm8, 2, 3), 87 +Int 128, 80 +Int 128), R4:Ymm, .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule diff --git a/semantics/memoryInstructions/vpalignr_xmm_xmm_m128_imm8.k b/semantics/memoryInstructions/vpalignr_xmm_xmm_m128_imm8.k index 673f8b7c3..cd2fab0fa 100644 --- a/semantics/memoryInstructions/vpalignr_xmm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vpalignr_xmm_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPALIGNR-XMM-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vpalignr:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpalignr:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpalignr:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vpalignr:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vpalignr Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpalignr:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpalignr:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), Mem128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), uvalueMInt(mi(256, 3))))), 128, 256)) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), Mem128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), Imm8), uvalueMInt(mi(256, 3))))), 128, 256)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpalignr_ymm_ymm_m256_imm8.k b/semantics/memoryInstructions/vpalignr_ymm_ymm_m256_imm8.k index d0fef964e..b3a5c2aff 100644 --- a/semantics/memoryInstructions/vpalignr_ymm_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vpalignr_ymm_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPALIGNR-YMM-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vpalignr:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] + context execinstr(vpalignr:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vpalignr:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vpalignr:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vpalignr Imm8, memOffset( MemOff), R3:Ymm, R4:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpalignr:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpalignr:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), extractMInt( Mem256, 0, 128)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), uvalueMInt(mi(256, 3))))), 128, 256), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), extractMInt( Mem256, 128, 256)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), uvalueMInt(mi(256, 3))))), 128, 256)) +convToRegKeys(R4) |-> concatenateMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), extractMInt( Mem256, 0, 128)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), Imm8), uvalueMInt(mi(256, 3))))), 128, 256), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), extractMInt( Mem256, 128, 256)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), Imm8), uvalueMInt(mi(256, 3))))), 128, 256)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpblendd_xmm_xmm_m128_imm8.k b/semantics/memoryInstructions/vpblendd_xmm_xmm_m128_imm8.k index 0c3aba64f..25d243aca 100644 --- a/semantics/memoryInstructions/vpblendd_xmm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vpblendd_xmm_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPBLENDD-XMM-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vpblendd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpblendd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpblendd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vpblendd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vpblendd Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpblendd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpblendd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( Mem128, 0, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( Mem128, 32, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( Mem128, 64, 96) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( Mem128, 96, 128) #fi))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( Mem128, 0, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( Mem128, 32, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( Mem128, 64, 96) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( Mem128, 96, 128) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpblendd_ymm_ymm_m256_imm8.k b/semantics/memoryInstructions/vpblendd_ymm_ymm_m256_imm8.k index 277454262..d1088492b 100644 --- a/semantics/memoryInstructions/vpblendd_ymm_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vpblendd_ymm_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPBLENDD-YMM-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vpblendd:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] + context execinstr(vpblendd:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vpblendd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vpblendd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vpblendd Imm8, memOffset( MemOff), R3:Ymm, R4:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpblendd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpblendd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( Mem256, 0, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( Mem256, 32, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 96) #else extractMInt( Mem256, 64, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 96, 128) #else extractMInt( Mem256, 96, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( Mem256, 128, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( Mem256, 160, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( Mem256, 192, 224) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( Mem256, 224, 256) #fi)))))))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( Mem256, 0, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( Mem256, 32, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 96) #else extractMInt( Mem256, 64, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 96, 128) #else extractMInt( Mem256, 96, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( Mem256, 128, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( Mem256, 160, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( Mem256, 192, 224) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( Mem256, 224, 256) #fi)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpblendw_xmm_xmm_m128_imm8.k b/semantics/memoryInstructions/vpblendw_xmm_xmm_m128_imm8.k index b32352650..d076858e6 100644 --- a/semantics/memoryInstructions/vpblendw_xmm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vpblendw_xmm_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPBLENDW-XMM-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vpblendw:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpblendw:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpblendw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vpblendw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vpblendw Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpblendw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpblendw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 144) #else extractMInt( Mem128, 0, 16) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 144, 160) #else extractMInt( Mem128, 16, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 176) #else extractMInt( Mem128, 32, 48) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 176, 192) #else extractMInt( Mem128, 48, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 208) #else extractMInt( Mem128, 64, 80) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 208, 224) #else extractMInt( Mem128, 80, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 240) #else extractMInt( Mem128, 96, 112) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 240, 256) #else extractMInt( Mem128, 112, 128) #fi))))))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 144) #else extractMInt( Mem128, 0, 16) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 144, 160) #else extractMInt( Mem128, 16, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 176) #else extractMInt( Mem128, 32, 48) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 176, 192) #else extractMInt( Mem128, 48, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 208) #else extractMInt( Mem128, 64, 80) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 208, 224) #else extractMInt( Mem128, 80, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 240) #else extractMInt( Mem128, 96, 112) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 240, 256) #else extractMInt( Mem128, 112, 128) #fi))))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpblendw_ymm_ymm_m256_imm8.k b/semantics/memoryInstructions/vpblendw_ymm_ymm_m256_imm8.k index 194bee6b5..06c48df3d 100644 --- a/semantics/memoryInstructions/vpblendw_ymm_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vpblendw_ymm_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPBLENDW-YMM-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vpblendw:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] + context execinstr(vpblendw:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vpblendw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vpblendw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vpblendw Imm8, memOffset( MemOff), R3:Ymm, R4:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpblendw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpblendw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 16) #else extractMInt( Mem256, 0, 16) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 16, 32) #else extractMInt( Mem256, 16, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 32, 48) #else extractMInt( Mem256, 32, 48) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 48, 64) #else extractMInt( Mem256, 48, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 80) #else extractMInt( Mem256, 64, 80) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 80, 96) #else extractMInt( Mem256, 80, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 96, 112) #else extractMInt( Mem256, 96, 112) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 112, 128) #else extractMInt( Mem256, 112, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 144) #else extractMInt( Mem256, 128, 144) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 144, 160) #else extractMInt( Mem256, 144, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 176) #else extractMInt( Mem256, 160, 176) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 176, 192) #else extractMInt( Mem256, 176, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 208) #else extractMInt( Mem256, 192, 208) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 208, 224) #else extractMInt( Mem256, 208, 224) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 240) #else extractMInt( Mem256, 224, 240) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 240, 256) #else extractMInt( Mem256, 240, 256) #fi)))))))))))))))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 16) #else extractMInt( Mem256, 0, 16) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 16, 32) #else extractMInt( Mem256, 16, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 32, 48) #else extractMInt( Mem256, 32, 48) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 48, 64) #else extractMInt( Mem256, 48, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 80) #else extractMInt( Mem256, 64, 80) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 80, 96) #else extractMInt( Mem256, 80, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 96, 112) #else extractMInt( Mem256, 96, 112) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 112, 128) #else extractMInt( Mem256, 112, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 144) #else extractMInt( Mem256, 128, 144) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 144, 160) #else extractMInt( Mem256, 144, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 176) #else extractMInt( Mem256, 160, 176) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 176, 192) #else extractMInt( Mem256, 176, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 208) #else extractMInt( Mem256, 192, 208) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 208, 224) #else extractMInt( Mem256, 208, 224) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 240) #else extractMInt( Mem256, 224, 240) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 240, 256) #else extractMInt( Mem256, 240, 256) #fi)))))))))))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpclmulqdq_xmm_xmm_m128_imm8.k b/semantics/memoryInstructions/vpclmulqdq_xmm_xmm_m128_imm8.k index 743703713..4e8bec553 100644 --- a/semantics/memoryInstructions/vpclmulqdq_xmm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vpclmulqdq_xmm_xmm_m128_imm8.k @@ -25,15 +25,14 @@ module VPCLMULQDQ-XMM-XMM-M128-IMM8 */ rule memLoadValue(MemVal:MInt):MemLoadValue ~> - execinstr (vpclmulqdq Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vpclmulqdq Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => execinstr(vpclmulqdq - selectSlice(getRegisterValue(R3, RSMap), handleImmediateWithSignExtend(Imm8, - 8, 8), 7, 64, 0), - selectSlice(MemVal, handleImmediateWithSignExtend(Imm8, - 8, 8), 3, 64, 0), R4 + selectSlice(getRegisterValue(R3, RSMap), Imm8, 7, 64, 0), + selectSlice(MemVal, Imm8, 3, 64, 0), R4 , .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (vpclmulqdq TEMP1:MInt, TEMP2:MInt, R4:Xmm, .Operands) => diff --git a/semantics/memoryInstructions/vpcmpestri_xmm_m128_imm8.k b/semantics/memoryInstructions/vpcmpestri_xmm_m128_imm8.k index e04fd30e8..f878aa16a 100644 --- a/semantics/memoryInstructions/vpcmpestri_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vpcmpestri_xmm_m128_imm8.k @@ -4,27 +4,28 @@ requires "x86-configuration.k" module VPCMPESTRI-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vpcmpestri:Opcode Imm8:Imm, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpcmpestri:Opcode Imm8:MInt, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpcmpestri:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => + execinstr (vpcmpestri:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vpcmpestri Imm8, memOffset( MemOff), Xmm1, .Operands) ... - + requires bitwidthMInt(Imm8) ==Int 8 // Find Limit Index rule memLoadValue(Mem128:MInt):MemLoadValue ~> - execinstr (vpcmpestri Imm8:Imm, memOffset( MemOff), Xmm1:Xmm, .Operands) => + execinstr (vpcmpestri Imm8:MInt, memOffset( MemOff), Xmm1:Xmm, .Operands) => execinstr (vpcmpestri - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, Mem128, getRegisterValue(Xmm1, RSMap), - findLimitIndexE(Mem128, getRegisterValue(%rdx, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexE(Mem128, getRegisterValue(%rdx, RSMap), Imm8), + findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // Find data size and interpretation rule diff --git a/semantics/memoryInstructions/vpcmpestrm_xmm_m128_imm8.k b/semantics/memoryInstructions/vpcmpestrm_xmm_m128_imm8.k index 94bf1d1a2..9c5f2e32e 100644 --- a/semantics/memoryInstructions/vpcmpestrm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vpcmpestrm_xmm_m128_imm8.k @@ -4,26 +4,27 @@ requires "x86-configuration.k" module VPCMPESTRM-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vpcmpestrm:Opcode Imm8:Imm, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpcmpestrm:Opcode Imm8:MInt, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpcmpestrm:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => + execinstr (vpcmpestrm:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vpcmpestrm Imm8, memOffset( MemOff), Xmm1, .Operands) ... - + requires bitwidthMInt(Imm8) ==Int 8 // Find Limit Index rule memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpcmpestrm Imm8, memOffset( MemOff), Xmm1, .Operands) => execinstr (vpcmpestrm - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, Mem128, getRegisterValue(Xmm1, RSMap), - findLimitIndexE(Mem128, getRegisterValue(%rdx, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexE(Mem128, getRegisterValue(%rdx, RSMap), Imm8), + findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // Find data size and interpretation rule diff --git a/semantics/memoryInstructions/vpcmpistri_xmm_m128_imm8.k b/semantics/memoryInstructions/vpcmpistri_xmm_m128_imm8.k index e511e15cf..44e726ab5 100644 --- a/semantics/memoryInstructions/vpcmpistri_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vpcmpistri_xmm_m128_imm8.k @@ -4,27 +4,28 @@ requires "x86-configuration.k" module VPCMPISTRI-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vpcmpistri:Opcode Imm8:Imm, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpcmpistri:Opcode Imm8:MInt, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpcmpistri:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => + execinstr (vpcmpistri:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vpcmpistri Imm8, memOffset( MemOff), Xmm1, .Operands) ... - + requires bitwidthMInt(Imm8) ==Int 8 // Find Limit Index rule memLoadValue(Mem128:MInt):MemLoadValue ~> - execinstr (vpcmpistri Imm8:Imm, Xmm2:Xmm, Xmm1:Xmm, .Operands) => + execinstr (vpcmpistri Imm8:MInt, Xmm2:Xmm, Xmm1:Xmm, .Operands) => execinstr (vpcmpistri - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, Mem128, getRegisterValue(Xmm1, RSMap), - findLimitIndexI(Mem128, handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexI(getRegisterValue(Xmm1, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexI(Mem128, Imm8), + findLimitIndexI(getRegisterValue(Xmm1, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // Find data size and interpretation rule diff --git a/semantics/memoryInstructions/vpcmpistrm_xmm_m128_imm8.k b/semantics/memoryInstructions/vpcmpistrm_xmm_m128_imm8.k index f13f75e4e..c65044991 100644 --- a/semantics/memoryInstructions/vpcmpistrm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vpcmpistrm_xmm_m128_imm8.k @@ -4,26 +4,28 @@ requires "x86-configuration.k" module VPCMPISTRM-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vpcmpistrm:Opcode Imm8:Imm, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpcmpistrm:Opcode Imm8:MInt, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpcmpistrm:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => + execinstr (vpcmpistrm:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vpcmpistrm Imm8, memOffset( MemOff), Xmm1, .Operands) ... + requires bitwidthMInt(Imm8) ==Int 8 // Find Limit Index rule memLoadValue(Mem128:MInt):MemLoadValue ~> - execinstr (vpcmpistrm Imm8:Imm, Xmm2:Xmm, Xmm1:Xmm, .Operands) => + execinstr (vpcmpistrm Imm8:MInt, Xmm2:Xmm, Xmm1:Xmm, .Operands) => execinstr (vpcmpistrm - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, Mem128, getRegisterValue(Xmm1, RSMap), - findLimitIndexI(Mem128, handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexI(getRegisterValue(Xmm1, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexI(Mem128, Imm8), + findLimitIndexI(getRegisterValue(Xmm1, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // Find data size and interpretation rule diff --git a/semantics/memoryInstructions/vperm2f128_ymm_ymm_m256_imm8.k b/semantics/memoryInstructions/vperm2f128_ymm_ymm_m256_imm8.k index e432ac1f1..c3ba655fe 100644 --- a/semantics/memoryInstructions/vperm2f128_ymm_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vperm2f128_ymm_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPERM2F128-YMM-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vperm2f128:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] + context execinstr(vperm2f128:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vperm2f128:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vperm2f128:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vperm2f128 Imm8, memOffset( MemOff), R3:Ymm, R4:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vperm2f128:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vperm2f128:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi)) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi), mi(128, 0)) #else concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi)) #fi) #fi) +convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi)) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi), mi(128, 0)) #else concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi)) #fi) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vperm2i128_ymm_ymm_m256_imm8.k b/semantics/memoryInstructions/vperm2i128_ymm_ymm_m256_imm8.k index 91bbba777..f9daa10d9 100644 --- a/semantics/memoryInstructions/vperm2i128_ymm_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vperm2i128_ymm_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPERM2I128-YMM-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vperm2i128:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] + context execinstr(vperm2i128:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vperm2i128:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vperm2i128:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vperm2i128 Imm8, memOffset( MemOff), R3:Ymm, R4:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vperm2i128:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vperm2i128:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi)) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi), mi(128, 0)) #else concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi)) #fi) #fi) +convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi)) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi), mi(128, 0)) #else concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi)) #fi) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpermilpd_xmm_m128_imm8.k b/semantics/memoryInstructions/vpermilpd_xmm_m128_imm8.k index 1cfdec4dc..38e7c5e5d 100644 --- a/semantics/memoryInstructions/vpermilpd_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vpermilpd_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPERMILPD-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vpermilpd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpermilpd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpermilpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (vpermilpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vpermilpd Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpermilpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpermilpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( Mem128, 64, 128) #else extractMInt( Mem128, 0, 64) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( Mem128, 64, 128) #else extractMInt( Mem128, 0, 64) #fi))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( Mem128, 64, 128) #else extractMInt( Mem128, 0, 64) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( Mem128, 64, 128) #else extractMInt( Mem128, 0, 64) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpermilpd_ymm_m256_imm8.k b/semantics/memoryInstructions/vpermilpd_ymm_m256_imm8.k index 2c2e6d0a5..e22576e01 100644 --- a/semantics/memoryInstructions/vpermilpd_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vpermilpd_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPERMILPD-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vpermilpd:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] + context execinstr(vpermilpd:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vpermilpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + execinstr (vpermilpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vpermilpd Imm8, memOffset( MemOff), R3:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpermilpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpermilpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( Mem256, 64, 128) #else extractMInt( Mem256, 0, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( Mem256, 64, 128) #else extractMInt( Mem256, 0, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( Mem256, 192, 256) #else extractMInt( Mem256, 128, 192) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( Mem256, 192, 256) #else extractMInt( Mem256, 128, 192) #fi)))) +convToRegKeys(R3) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( Mem256, 64, 128) #else extractMInt( Mem256, 0, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( Mem256, 64, 128) #else extractMInt( Mem256, 0, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( Mem256, 192, 256) #else extractMInt( Mem256, 128, 192) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( Mem256, 192, 256) #else extractMInt( Mem256, 128, 192) #fi)))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpermilps_xmm_m128_imm8.k b/semantics/memoryInstructions/vpermilps_xmm_m128_imm8.k index 31d3585ea..c02fd7fbf 100644 --- a/semantics/memoryInstructions/vpermilps_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vpermilps_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPERMILPS-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vpermilps:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpermilps:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpermilps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (vpermilps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vpermilps Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpermilps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpermilps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 0)) #then extractMInt( Mem128, 96, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 1)) #then extractMInt( Mem128, 64, 96) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 2)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( Mem128, 96, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( Mem128, 64, 96) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 0)) #then extractMInt( Mem128, 96, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 1)) #then extractMInt( Mem128, 64, 96) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 2)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 0, 32) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 0)) #then extractMInt( Mem128, 96, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 1)) #then extractMInt( Mem128, 64, 96) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 2)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 0, 32) #fi) #fi) #fi))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 0)) #then extractMInt( Mem128, 96, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 1)) #then extractMInt( Mem128, 64, 96) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 2)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( Mem128, 96, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( Mem128, 64, 96) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 0)) #then extractMInt( Mem128, 96, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 1)) #then extractMInt( Mem128, 64, 96) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 2)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 0, 32) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 0)) #then extractMInt( Mem128, 96, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 1)) #then extractMInt( Mem128, 64, 96) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 2)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 0, 32) #fi) #fi) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpermilps_ymm_m256_imm8.k b/semantics/memoryInstructions/vpermilps_ymm_m256_imm8.k index d8ed154f1..72f36a69e 100644 --- a/semantics/memoryInstructions/vpermilps_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vpermilps_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPERMILPS-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vpermilps:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] + context execinstr(vpermilps:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vpermilps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + execinstr (vpermilps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vpermilps Imm8, memOffset( MemOff), R3:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpermilps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpermilps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 0)) #then extractMInt( Mem256, 96, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 1)) #then extractMInt( Mem256, 64, 96) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 2)) #then extractMInt( Mem256, 32, 64) #else extractMInt( Mem256, 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( Mem256, 96, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( Mem256, 64, 96) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( Mem256, 32, 64) #else extractMInt( Mem256, 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 0)) #then extractMInt( Mem256, 96, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 1)) #then extractMInt( Mem256, 64, 96) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 2)) #then extractMInt( Mem256, 32, 64) #else extractMInt( Mem256, 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 0)) #then extractMInt( Mem256, 96, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 1)) #then extractMInt( Mem256, 64, 96) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 2)) #then extractMInt( Mem256, 32, 64) #else extractMInt( Mem256, 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 0)) #then extractMInt( Mem256, 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 1)) #then extractMInt( Mem256, 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 2)) #then extractMInt( Mem256, 160, 192) #else extractMInt( Mem256, 128, 160) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( Mem256, 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( Mem256, 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( Mem256, 160, 192) #else extractMInt( Mem256, 128, 160) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 0)) #then extractMInt( Mem256, 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 1)) #then extractMInt( Mem256, 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 2)) #then extractMInt( Mem256, 160, 192) #else extractMInt( Mem256, 128, 160) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 0)) #then extractMInt( Mem256, 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 1)) #then extractMInt( Mem256, 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 2)) #then extractMInt( Mem256, 160, 192) #else extractMInt( Mem256, 128, 160) #fi) #fi) #fi)))))))) +convToRegKeys(R3) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 0)) #then extractMInt( Mem256, 96, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 1)) #then extractMInt( Mem256, 64, 96) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 2)) #then extractMInt( Mem256, 32, 64) #else extractMInt( Mem256, 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( Mem256, 96, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( Mem256, 64, 96) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( Mem256, 32, 64) #else extractMInt( Mem256, 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 0)) #then extractMInt( Mem256, 96, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 1)) #then extractMInt( Mem256, 64, 96) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 2)) #then extractMInt( Mem256, 32, 64) #else extractMInt( Mem256, 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 0)) #then extractMInt( Mem256, 96, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 1)) #then extractMInt( Mem256, 64, 96) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 2)) #then extractMInt( Mem256, 32, 64) #else extractMInt( Mem256, 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 0)) #then extractMInt( Mem256, 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 1)) #then extractMInt( Mem256, 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 2)) #then extractMInt( Mem256, 160, 192) #else extractMInt( Mem256, 128, 160) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( Mem256, 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( Mem256, 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( Mem256, 160, 192) #else extractMInt( Mem256, 128, 160) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 0)) #then extractMInt( Mem256, 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 1)) #then extractMInt( Mem256, 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 2)) #then extractMInt( Mem256, 160, 192) #else extractMInt( Mem256, 128, 160) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 0)) #then extractMInt( Mem256, 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 1)) #then extractMInt( Mem256, 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 2)) #then extractMInt( Mem256, 160, 192) #else extractMInt( Mem256, 128, 160) #fi) #fi) #fi)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpermpd_ymm_m256_imm8.k b/semantics/memoryInstructions/vpermpd_ymm_m256_imm8.k index d2d475cfc..8f7b7aba0 100644 --- a/semantics/memoryInstructions/vpermpd_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vpermpd_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPERMPD-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vpermpd:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] + context execinstr(vpermpd:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vpermpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + execinstr (vpermpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vpermpd Imm8, memOffset( MemOff), R3:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpermpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpermpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(256, 6))))), 192, 256), extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(256, 6))))), 192, 256)))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(256, 6))))), 192, 256), extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(256, 6))))), 192, 256)))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpermq_ymm_m256_imm8.k b/semantics/memoryInstructions/vpermq_ymm_m256_imm8.k index 2c1a26624..f3a50a7c3 100644 --- a/semantics/memoryInstructions/vpermq_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vpermq_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPERMQ-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vpermq:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] + context execinstr(vpermq:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vpermq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + execinstr (vpermq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vpermq Imm8, memOffset( MemOff), R3:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpermq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpermq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(256, 6))))), 192, 256), extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(256, 6))))), 192, 256)))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(256, 6))))), 192, 256), extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(256, 6))))), 192, 256)))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpextrb_m8_xmm_imm8.k b/semantics/memoryInstructions/vpextrb_m8_xmm_imm8.k index 7e2f2350a..625b55a01 100644 --- a/semantics/memoryInstructions/vpextrb_m8_xmm_imm8.k +++ b/semantics/memoryInstructions/vpextrb_m8_xmm_imm8.k @@ -4,24 +4,26 @@ requires "x86-configuration.k" module VPEXTRB-M8-XMM-IMM8 imports X86-CONFIGURATION - context execinstr(vpextrb:Opcode Imm8:Imm, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(vpextrb:Opcode Imm8:MInt, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (vpextrb:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (vpextrb:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (vpextrb Imm8, R2:Xmm, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (vpextrb:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (vpextrb:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3))))), 120, 128), + extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3))))), 120, 128), MemOff, 8 ) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpextrd_m32_xmm_imm8.k b/semantics/memoryInstructions/vpextrd_m32_xmm_imm8.k index eda4b47f8..b1396072c 100644 --- a/semantics/memoryInstructions/vpextrd_m32_xmm_imm8.k +++ b/semantics/memoryInstructions/vpextrd_m32_xmm_imm8.k @@ -4,24 +4,26 @@ requires "x86-configuration.k" module VPEXTRD-M32-XMM-IMM8 imports X86-CONFIGURATION - context execinstr(vpextrd:Opcode Imm8:Imm, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(vpextrd:Opcode Imm8:MInt, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (vpextrd:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (vpextrd:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (vpextrd Imm8, R2:Xmm, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (vpextrd:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (vpextrd:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128), + extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128), MemOff, 32 ) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpextrq_m64_xmm_imm8.k b/semantics/memoryInstructions/vpextrq_m64_xmm_imm8.k index 69be5d404..2a21f97c0 100644 --- a/semantics/memoryInstructions/vpextrq_m64_xmm_imm8.k +++ b/semantics/memoryInstructions/vpextrq_m64_xmm_imm8.k @@ -4,24 +4,26 @@ requires "x86-configuration.k" module VPEXTRQ-M64-XMM-IMM8 imports X86-CONFIGURATION - context execinstr(vpextrq:Opcode Imm8:Imm, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(vpextrq:Opcode Imm8:MInt, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (vpextrq:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (vpextrq:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (vpextrq Imm8, R2:Xmm, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (vpextrq:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (vpextrq:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6))))), 64, 128), + extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6))))), 64, 128), MemOff, 64 ) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpextrw_m16_xmm_imm8.k b/semantics/memoryInstructions/vpextrw_m16_xmm_imm8.k index 1f11f47b0..3106f1c26 100644 --- a/semantics/memoryInstructions/vpextrw_m16_xmm_imm8.k +++ b/semantics/memoryInstructions/vpextrw_m16_xmm_imm8.k @@ -4,24 +4,26 @@ requires "x86-configuration.k" module VPEXTRW-M16-XMM-IMM8 imports X86-CONFIGURATION - context execinstr(vpextrw:Opcode Imm8:Imm, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(vpextrw:Opcode Imm8:MInt, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (vpextrw:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (vpextrw:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (vpextrw Imm8, R2:Xmm, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (vpextrw:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (vpextrw:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4))))), 112, 128), + extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4))))), 112, 128), MemOff, 16 ) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpinsrb_xmm_xmm_m8_imm8.k b/semantics/memoryInstructions/vpinsrb_xmm_xmm_m8_imm8.k index 538f03f1d..01a8938e8 100644 --- a/semantics/memoryInstructions/vpinsrb_xmm_xmm_m8_imm8.k +++ b/semantics/memoryInstructions/vpinsrb_xmm_xmm_m8_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPINSRB-XMM-XMM-M8-IMM8 imports X86-CONFIGURATION - context execinstr(vpinsrb:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpinsrb:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpinsrb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vpinsrb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (vpinsrb Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (vpinsrb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (vpinsrb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(120, 0), Mem8), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3))))), shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3)))))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(120, 0), Mem8), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3))))), shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpinsrd_xmm_xmm_m32_imm8.k b/semantics/memoryInstructions/vpinsrd_xmm_xmm_m32_imm8.k index ba1b77448..0ad1d3051 100644 --- a/semantics/memoryInstructions/vpinsrd_xmm_xmm_m32_imm8.k +++ b/semantics/memoryInstructions/vpinsrd_xmm_xmm_m32_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPINSRD-XMM-XMM-M32-IMM8 imports X86-CONFIGURATION - context execinstr(vpinsrd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpinsrd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpinsrd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vpinsrd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (vpinsrd Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (vpinsrd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (vpinsrd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), Mem32), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5)))))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), Mem32), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpinsrq_xmm_xmm_m64_imm8.k b/semantics/memoryInstructions/vpinsrq_xmm_xmm_m64_imm8.k index 369b02406..7d24dc328 100644 --- a/semantics/memoryInstructions/vpinsrq_xmm_xmm_m64_imm8.k +++ b/semantics/memoryInstructions/vpinsrq_xmm_xmm_m64_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPINSRQ-XMM-XMM-M64-IMM8 imports X86-CONFIGURATION - context execinstr(vpinsrq:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpinsrq:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpinsrq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vpinsrq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (vpinsrq Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (vpinsrq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (vpinsrq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(64, 0), Mem64), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6))))), shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6)))))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(64, 0), Mem64), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6))))), shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpinsrw_xmm_xmm_m16_imm8.k b/semantics/memoryInstructions/vpinsrw_xmm_xmm_m16_imm8.k index ce6b30e3f..29df94768 100644 --- a/semantics/memoryInstructions/vpinsrw_xmm_xmm_m16_imm8.k +++ b/semantics/memoryInstructions/vpinsrw_xmm_xmm_m16_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPINSRW-XMM-XMM-M16-IMM8 imports X86-CONFIGURATION - context execinstr(vpinsrw:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpinsrw:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpinsrw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vpinsrw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (vpinsrw Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (vpinsrw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (vpinsrw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(112, 0), Mem16), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4))))), shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4)))))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(112, 0), Mem16), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4))))), shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpshufd_xmm_m128_imm8.k b/semantics/memoryInstructions/vpshufd_xmm_m128_imm8.k index 87d0d7b6e..74ba9c1c1 100644 --- a/semantics/memoryInstructions/vpshufd_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vpshufd_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPSHUFD-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vpshufd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpshufd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpshufd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (vpshufd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vpshufd Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpshufd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpshufd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpshufd_ymm_m256_imm8.k b/semantics/memoryInstructions/vpshufd_ymm_m256_imm8.k index 0b6b17c78..d6a40a98b 100644 --- a/semantics/memoryInstructions/vpshufd_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vpshufd_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPSHUFD-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vpshufd:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] + context execinstr(vpshufd:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vpshufd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + execinstr (vpshufd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vpshufd Imm8, memOffset( MemOff), R3:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpshufd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpshufd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( extractMInt( Mem256, 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( Mem256, 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( Mem256, 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( Mem256, 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( Mem256, 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( Mem256, 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( Mem256, 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), extractMInt( lshrMInt( extractMInt( Mem256, 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128)))))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( extractMInt( Mem256, 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( Mem256, 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( Mem256, 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( Mem256, 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( Mem256, 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( Mem256, 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( Mem256, 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), extractMInt( lshrMInt( extractMInt( Mem256, 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpshufhw_xmm_m128_imm8.k b/semantics/memoryInstructions/vpshufhw_xmm_m128_imm8.k index eeb489202..957e825b1 100644 --- a/semantics/memoryInstructions/vpshufhw_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vpshufhw_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPSHUFHW-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vpshufhw:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpshufhw:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpshufhw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (vpshufhw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vpshufhw Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpshufhw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpshufhw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 4))))), 48, 64), extractMInt( Mem128, 64, 128)))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 4))))), 48, 64), extractMInt( Mem128, 64, 128)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpshufhw_ymm_m256_imm8.k b/semantics/memoryInstructions/vpshufhw_ymm_m256_imm8.k index a9b0def71..bbb390a6d 100644 --- a/semantics/memoryInstructions/vpshufhw_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vpshufhw_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPSHUFHW-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vpshufhw:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] + context execinstr(vpshufhw:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vpshufhw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + execinstr (vpshufhw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vpshufhw Imm8, memOffset( MemOff), R3:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpshufhw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpshufhw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( Mem256, 64, 128), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(256, 4))))), 176, 192), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(256, 4))))), 176, 192), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(256, 4))))), 176, 192), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(256, 4))))), 176, 192), extractMInt( Mem256, 192, 256)))))))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( Mem256, 64, 128), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(256, 4))))), 176, 192), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(256, 4))))), 176, 192), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(256, 4))))), 176, 192), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(256, 4))))), 176, 192), extractMInt( Mem256, 192, 256)))))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpshuflw_xmm_m128_imm8.k b/semantics/memoryInstructions/vpshuflw_xmm_m128_imm8.k index 4ea5e1628..e9ad30418 100644 --- a/semantics/memoryInstructions/vpshuflw_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vpshuflw_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPSHUFLW-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vpshuflw:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpshuflw:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpshuflw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (vpshuflw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vpshuflw Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpshuflw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpshuflw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( Mem128, 0, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 4))))), 112, 128), extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 4))))), 112, 128)))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( Mem128, 0, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 4))))), 112, 128), extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 4))))), 112, 128)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpshuflw_ymm_m256_imm8.k b/semantics/memoryInstructions/vpshuflw_ymm_m256_imm8.k index c2d6f93cb..da5dd0671 100644 --- a/semantics/memoryInstructions/vpshuflw_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vpshuflw_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPSHUFLW-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vpshuflw:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] + context execinstr(vpshuflw:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vpshuflw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + execinstr (vpshuflw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vpshuflw Imm8, memOffset( MemOff), R3:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpshuflw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpshuflw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( Mem256, 0, 64), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( Mem256, 128, 192), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(256, 4))))), 240, 256), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(256, 4))))), 240, 256), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(256, 4))))), 240, 256), extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(256, 4))))), 240, 256)))))))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( Mem256, 0, 64), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( Mem256, 128, 192), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(256, 4))))), 240, 256), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(256, 4))))), 240, 256), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(256, 4))))), 240, 256), extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(256, 4))))), 240, 256)))))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vroundpd_xmm_m128_imm8.k b/semantics/memoryInstructions/vroundpd_xmm_m128_imm8.k index 52c15f25c..eff64c13e 100644 --- a/semantics/memoryInstructions/vroundpd_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vroundpd_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VROUNDPD-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vroundpd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(vroundpd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vroundpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (vroundpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vroundpd Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vroundpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vroundpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( cvt_double_to_int64_rm(extractMInt( Mem128, 0, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_double_to_int64_rm(extractMInt( Mem128, 64, 128), handleImmediateWithSignExtend(Imm8, 8, 8)))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( cvt_double_to_int64_rm(extractMInt( Mem128, 0, 64), Imm8), cvt_double_to_int64_rm(extractMInt( Mem128, 64, 128), Imm8))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vroundpd_ymm_m256_imm8.k b/semantics/memoryInstructions/vroundpd_ymm_m256_imm8.k index 0d86ea5fa..29c4f53db 100644 --- a/semantics/memoryInstructions/vroundpd_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vroundpd_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VROUNDPD-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vroundpd:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] + context execinstr(vroundpd:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vroundpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + execinstr (vroundpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vroundpd Imm8, memOffset( MemOff), R3:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vroundpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vroundpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( cvt_double_to_int64_rm(extractMInt( Mem256, 0, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_double_to_int64_rm(extractMInt( Mem256, 64, 128), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_double_to_int64_rm(extractMInt( Mem256, 128, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_double_to_int64_rm(extractMInt( Mem256, 192, 256), handleImmediateWithSignExtend(Imm8, 8, 8))))) +convToRegKeys(R3) |-> concatenateMInt( cvt_double_to_int64_rm(extractMInt( Mem256, 0, 64), Imm8), concatenateMInt( cvt_double_to_int64_rm(extractMInt( Mem256, 64, 128), Imm8), concatenateMInt( cvt_double_to_int64_rm(extractMInt( Mem256, 128, 192), Imm8), cvt_double_to_int64_rm(extractMInt( Mem256, 192, 256), Imm8)))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vroundps_xmm_m128_imm8.k b/semantics/memoryInstructions/vroundps_xmm_m128_imm8.k index 3ffb0eb80..19b62e4dd 100644 --- a/semantics/memoryInstructions/vroundps_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vroundps_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VROUNDPS-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vroundps:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(vroundps:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vroundps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (vroundps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vroundps Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vroundps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vroundps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem128, 0, 32), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem128, 32, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem128, 64, 96), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_single_to_int32_rm(extractMInt( Mem128, 96, 128), handleImmediateWithSignExtend(Imm8, 8, 8)))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem128, 0, 32), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem128, 32, 64), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem128, 64, 96), Imm8), cvt_single_to_int32_rm(extractMInt( Mem128, 96, 128), Imm8))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vroundps_ymm_m256_imm8.k b/semantics/memoryInstructions/vroundps_ymm_m256_imm8.k index 653a1dc9f..870448c7c 100644 --- a/semantics/memoryInstructions/vroundps_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vroundps_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VROUNDPS-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vroundps:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] + context execinstr(vroundps:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vroundps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + execinstr (vroundps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vroundps Imm8, memOffset( MemOff), R3:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vroundps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vroundps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem256, 0, 32), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem256, 32, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem256, 64, 96), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem256, 96, 128), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem256, 128, 160), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem256, 160, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem256, 192, 224), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_single_to_int32_rm(extractMInt( Mem256, 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8))))))))) +convToRegKeys(R3) |-> concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem256, 0, 32), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem256, 32, 64), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem256, 64, 96), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem256, 96, 128), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem256, 128, 160), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem256, 160, 192), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem256, 192, 224), Imm8), cvt_single_to_int32_rm(extractMInt( Mem256, 224, 256), Imm8)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vroundsd_xmm_xmm_m64_imm8.k b/semantics/memoryInstructions/vroundsd_xmm_xmm_m64_imm8.k index 2b7aa82fb..b1b98e49a 100644 --- a/semantics/memoryInstructions/vroundsd_xmm_xmm_m64_imm8.k +++ b/semantics/memoryInstructions/vroundsd_xmm_xmm_m64_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VROUNDSD-XMM-XMM-M64-IMM8 imports X86-CONFIGURATION - context execinstr(vroundsd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vroundsd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vroundsd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vroundsd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (vroundsd Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (vroundsd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (vroundsd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 192), cvt_double_to_int64_rm(Mem64, handleImmediateWithSignExtend(Imm8, 8, 8)))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 192), cvt_double_to_int64_rm(Mem64, Imm8))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vroundss_xmm_xmm_m32_imm8.k b/semantics/memoryInstructions/vroundss_xmm_xmm_m32_imm8.k index 250e08378..3d8c7d7cf 100644 --- a/semantics/memoryInstructions/vroundss_xmm_xmm_m32_imm8.k +++ b/semantics/memoryInstructions/vroundss_xmm_xmm_m32_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VROUNDSS-XMM-XMM-M32-IMM8 imports X86-CONFIGURATION - context execinstr(vroundss:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vroundss:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vroundss:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vroundss:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (vroundss Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (vroundss:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (vroundss:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 224), cvt_single_to_int32_rm(Mem32, handleImmediateWithSignExtend(Imm8, 8, 8)))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 224), cvt_single_to_int32_rm(Mem32, Imm8))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vshufpd_xmm_xmm_m128_imm8.k b/semantics/memoryInstructions/vshufpd_xmm_xmm_m128_imm8.k index 6d9c32ce3..18c4fd73d 100644 --- a/semantics/memoryInstructions/vshufpd_xmm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vshufpd_xmm_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VSHUFPD-XMM-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vshufpd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vshufpd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vshufpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vshufpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vshufpd Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vshufpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vshufpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( Mem128, 0, 64) #else extractMInt( Mem128, 64, 128) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R3, RSMap), 192, 256) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( Mem128, 0, 64) #else extractMInt( Mem128, 64, 128) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R3, RSMap), 192, 256) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vshufpd_ymm_ymm_m256_imm8.k b/semantics/memoryInstructions/vshufpd_ymm_ymm_m256_imm8.k index 0743ec2af..e966968a3 100644 --- a/semantics/memoryInstructions/vshufpd_ymm_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vshufpd_ymm_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VSHUFPD-YMM-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vshufpd:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] + context execinstr(vshufpd:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vshufpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vshufpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vshufpd Imm8, memOffset( MemOff), R3:Ymm, R4:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vshufpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vshufpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( Mem256, 0, 64) #else extractMInt( Mem256, 64, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 64) #else extractMInt( getParentValue(R3, RSMap), 64, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( Mem256, 128, 192) #else extractMInt( Mem256, 192, 256) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R3, RSMap), 192, 256) #fi)))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( Mem256, 0, 64) #else extractMInt( Mem256, 64, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 64) #else extractMInt( getParentValue(R3, RSMap), 64, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( Mem256, 128, 192) #else extractMInt( Mem256, 192, 256) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R3, RSMap), 192, 256) #fi)))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vshufps_xmm_xmm_m128_imm8.k b/semantics/memoryInstructions/vshufps_xmm_xmm_m128_imm8.k index 18d1e9b47..65694b991 100644 --- a/semantics/memoryInstructions/vshufps_xmm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vshufps_xmm_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VSHUFPS-XMM-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vshufps:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vshufps:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vshufps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vshufps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vshufps Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vshufps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vshufps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( Mem128, 0, 32) #else extractMInt( Mem128, 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( Mem128, 0, 32) #else extractMInt( Mem128, 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( Mem128, 0, 32) #else extractMInt( Mem128, 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( Mem128, 0, 32) #else extractMInt( Mem128, 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vshufps_ymm_ymm_m256_imm8.k b/semantics/memoryInstructions/vshufps_ymm_ymm_m256_imm8.k index bf4ea4da0..470be85fa 100644 --- a/semantics/memoryInstructions/vshufps_ymm_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vshufps_ymm_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VSHUFPS-YMM-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vshufps:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] + context execinstr(vshufps:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vshufps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vshufps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vshufps Imm8, memOffset( MemOff), R3:Ymm, R4:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vshufps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vshufps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( Mem256, 0, 32) #else extractMInt( Mem256, 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( Mem256, 32, 64) #else extractMInt( Mem256, 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( Mem256, 0, 32) #else extractMInt( Mem256, 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( Mem256, 32, 64) #else extractMInt( Mem256, 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( getParentValue(R3, RSMap), 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( getParentValue(R3, RSMap), 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( getParentValue(R3, RSMap), 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( getParentValue(R3, RSMap), 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( Mem256, 128, 160) #else extractMInt( Mem256, 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( Mem256, 160, 192) #else extractMInt( Mem256, 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( Mem256, 128, 160) #else extractMInt( Mem256, 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( Mem256, 160, 192) #else extractMInt( Mem256, 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi)))))))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( Mem256, 0, 32) #else extractMInt( Mem256, 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( Mem256, 32, 64) #else extractMInt( Mem256, 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( Mem256, 0, 32) #else extractMInt( Mem256, 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( Mem256, 32, 64) #else extractMInt( Mem256, 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( getParentValue(R3, RSMap), 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( getParentValue(R3, RSMap), 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( getParentValue(R3, RSMap), 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( getParentValue(R3, RSMap), 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( Mem256, 128, 160) #else extractMInt( Mem256, 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( Mem256, 160, 192) #else extractMInt( Mem256, 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( Mem256, 128, 160) #else extractMInt( Mem256, 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( Mem256, 160, 192) #else extractMInt( Mem256, 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/xorb_m8_imm8.k b/semantics/memoryInstructions/xorb_m8_imm8.k index 1bfc2c39a..a338382b7 100644 --- a/semantics/memoryInstructions/xorb_m8_imm8.k +++ b/semantics/memoryInstructions/xorb_m8_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module XORB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(xorb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(xorb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (xorb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (xorb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (xorb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (xorb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (xorb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - xorMInt( Mem8, handleImmediateWithSignExtend(Imm8, 8, 8)), + xorMInt( Mem8, Imm8), MemOff, 8 ) @@ -27,15 +28,16 @@ module XORB-M8-IMM8 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( Mem8, 7, 8), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( Mem8, 6, 7), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem8, 5, 6), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem8, 4, 5), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem8, 3, 4), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem8, 2, 3), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem8, 1, 2), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem8, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( Mem8, 7, 8), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( Mem8, 6, 7), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem8, 5, 6), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem8, 4, 5), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem8, 3, 4), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem8, 2, 3), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem8, 1, 2), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem8, 0, 1), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( Mem8, handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( Mem8, Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( Mem8, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> xorMInt( extractMInt( Mem8, 0, 1), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/xorl_m32_imm32.k b/semantics/memoryInstructions/xorl_m32_imm32.k index db7bfde46..7830673db 100644 --- a/semantics/memoryInstructions/xorl_m32_imm32.k +++ b/semantics/memoryInstructions/xorl_m32_imm32.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module XORL-M32-IMM32 imports X86-CONFIGURATION - context execinstr(xorl:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(xorl:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (xorl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (xorl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (xorl Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (xorl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (xorl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - xorMInt( Mem32, handleImmediateWithSignExtend(Imm32, 32, 32)), + xorMInt( Mem32, Imm32), MemOff, 32 ) @@ -27,15 +28,16 @@ module XORL-M32-IMM32 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( Mem32, 31, 32), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( Mem32, 30, 31), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 29, 30), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 28, 29), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 27, 28), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 26, 27), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 25, 26), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 24, 25), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( Mem32, 31, 32), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( Mem32, 30, 31), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 29, 30), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 28, 29), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 27, 28), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 26, 27), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 25, 26), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 24, 25), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( Mem32, handleImmediateWithSignExtend(Imm32, 32, 32)), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( Mem32, Imm32), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( Mem32, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)) +"SF" |-> xorMInt( extractMInt( Mem32, 0, 1), extractMInt( Imm32, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/xorl_m32_imm8.k b/semantics/memoryInstructions/xorl_m32_imm8.k index b2a9bea6c..281094860 100644 --- a/semantics/memoryInstructions/xorl_m32_imm8.k +++ b/semantics/memoryInstructions/xorl_m32_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module XORL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(xorl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(xorl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (xorl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (xorl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (xorl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (xorl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (xorl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - xorMInt( Mem32, mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), + xorMInt( Mem32, mi(32, svalueMInt(Imm8))), MemOff, 32 ) @@ -27,15 +28,16 @@ module XORL-M32-IMM8 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( Mem32, 31, 32), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( Mem32, 30, 31), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 29, 30), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 28, 29), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 27, 28), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 26, 27), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 25, 26), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 24, 25), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( Mem32, 31, 32), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( Mem32, 30, 31), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 29, 30), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 28, 29), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 27, 28), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 26, 27), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 25, 26), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 24, 25), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( Mem32, mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( Mem32, mi(32, svalueMInt(Imm8))), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( Mem32, 0, 1), extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> xorMInt( extractMInt( Mem32, 0, 1), extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/xorq_m64_imm32.k b/semantics/memoryInstructions/xorq_m64_imm32.k index a77c4c11e..05f383ba0 100644 --- a/semantics/memoryInstructions/xorq_m64_imm32.k +++ b/semantics/memoryInstructions/xorq_m64_imm32.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module XORQ-M64-IMM32 imports X86-CONFIGURATION - context execinstr(xorq:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(xorq:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (xorq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (xorq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (xorq Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (xorq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (xorq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - xorMInt( Mem64, mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), + xorMInt( Mem64, mi(64, svalueMInt(Imm32))), MemOff, 64 ) @@ -27,15 +28,16 @@ module XORQ-M64-IMM32 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( Mem64, 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( Mem64, 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( Mem64, 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( Mem64, 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( Mem64, mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( Mem64, mi(64, svalueMInt(Imm32))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( Mem64, 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)) +"SF" |-> xorMInt( extractMInt( Mem64, 0, 1), extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/xorq_m64_imm8.k b/semantics/memoryInstructions/xorq_m64_imm8.k index 1f8e023ad..1727eae5b 100644 --- a/semantics/memoryInstructions/xorq_m64_imm8.k +++ b/semantics/memoryInstructions/xorq_m64_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module XORQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(xorq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(xorq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (xorq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (xorq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (xorq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (xorq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (xorq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - xorMInt( Mem64, mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), + xorMInt( Mem64, mi(64, svalueMInt(Imm8))), MemOff, 64 ) @@ -27,15 +28,16 @@ module XORQ-M64-IMM8 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( Mem64, 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( Mem64, 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( Mem64, 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( Mem64, 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( Mem64, mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( Mem64, mi(64, svalueMInt(Imm8))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( Mem64, 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> xorMInt( extractMInt( Mem64, 0, 1), extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/xorw_m16_imm16.k b/semantics/memoryInstructions/xorw_m16_imm16.k index b6c04a45b..6aab46f18 100644 --- a/semantics/memoryInstructions/xorw_m16_imm16.k +++ b/semantics/memoryInstructions/xorw_m16_imm16.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module XORW-M16-IMM16 imports X86-CONFIGURATION - context execinstr(xorw:Opcode Imm16:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(xorw:Opcode Imm16:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (xorw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (xorw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (xorw Imm16, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm16) ==Int 16 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (xorw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (xorw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - xorMInt( Mem16, handleImmediateWithSignExtend(Imm16, 16, 16)), + xorMInt( Mem16, Imm16), MemOff, 16 ) @@ -27,15 +28,16 @@ module XORW-M16-IMM16 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( Mem16, 15, 16), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 15, 16)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( Mem16, 14, 15), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 14, 15)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 13, 14), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 13, 14)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 12, 13), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 12, 13)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 11, 12), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 10, 11), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 10, 11)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 9, 10), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 9, 10)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 8, 9), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( Mem16, 15, 16), extractMInt( Imm16, 15, 16)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( Mem16, 14, 15), extractMInt( Imm16, 14, 15)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 13, 14), extractMInt( Imm16, 13, 14)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 12, 13), extractMInt( Imm16, 12, 13)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 11, 12), extractMInt( Imm16, 11, 12)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 10, 11), extractMInt( Imm16, 10, 11)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 9, 10), extractMInt( Imm16, 9, 10)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 8, 9), extractMInt( Imm16, 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( Mem16, handleImmediateWithSignExtend(Imm16, 16, 16)), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( Mem16, Imm16), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( Mem16, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)) +"SF" |-> xorMInt( extractMInt( Mem16, 0, 1), extractMInt( Imm16, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/memoryInstructions/xorw_m16_imm8.k b/semantics/memoryInstructions/xorw_m16_imm8.k index e3430d659..daea736e1 100644 --- a/semantics/memoryInstructions/xorw_m16_imm8.k +++ b/semantics/memoryInstructions/xorw_m16_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module XORW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(xorw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(xorw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (xorw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (xorw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (xorw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (xorw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (xorw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - xorMInt( Mem16, mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), + xorMInt( Mem16, mi(16, svalueMInt(Imm8))), MemOff, 16 ) @@ -27,15 +28,16 @@ module XORW-M16-IMM8 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( Mem16, 15, 16), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( Mem16, 14, 15), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 13, 14), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 12, 13), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 11, 12), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 10, 11), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 9, 10), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 8, 9), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( Mem16, 15, 16), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( Mem16, 14, 15), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 13, 14), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 12, 13), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 11, 12), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 10, 11), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 9, 10), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 8, 9), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( Mem16, mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( Mem16, mi(16, svalueMInt(Imm8))), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( Mem16, 0, 1), extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> xorMInt( extractMInt( Mem16, 0, 1), extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/registerInstructions/pushq_imm32.k b/semantics/registerInstructions/pushq_imm32.k deleted file mode 100644 index 143e8b115..000000000 --- a/semantics/registerInstructions/pushq_imm32.k +++ /dev/null @@ -1,22 +0,0 @@ -requires "x86-configuration.k" - - -/*@ - Push R: - 1. ValTostore = R - 2. *(RSP-8) = ValTostore - 3. RSP = RSP - 8 -*/ -module PUSHQ-IMM32 - imports X86-CONFIGURATION - - rule - execinstr (pushq Imm32:Imm, .Operands) => - storeToMemory( - handleImmediateWithSignExtend(Imm32, 32, 64), - subMInt(getRegisterValue(%rsp, RSMap), mi(64, 8)), - 64) ~> - decRSPInBytes(8) - ... - RSMap -endmodule diff --git a/semantics/registerInstructions/roll_r32_one.k b/semantics/registerInstructions/roll_r32_one.k index 34f3407b6..c2dfc627d 100644 --- a/semantics/registerInstructions/roll_r32_one.k +++ b/semantics/registerInstructions/roll_r32_one.k @@ -1,36 +1,25 @@ // Autogenerated using stratification. requires "x86-configuration.k" -module ROLL-M32-ONE +module ROLL-R32-ONE imports X86-CONFIGURATION - rule - execinstr (roll:Opcode M:Mem, .Operands) => execinstr (roll:Opcode $0x1, M:Mem, .Operands) - ... - context execinstr(roll:Opcode $0x1, HOLE:Mem, .Operands) [result(MemOffset)] - - rule - execinstr (roll:Opcode $0x1, memOffset( MemOff:MInt):MemOffset, .Operands) => - loadFromMemory( MemOff, 32) ~> - execinstr (roll $0x1, memOffset( MemOff), .Operands) - ... - RSMap:Map - rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (roll:Opcode $0x1, memOffset( MemOff:MInt):MemOffset, .Operands) => - - storeToMemory( - rol( Mem32, mi(32, 1)), - MemOff, - 32 - ) - + execinstr (roll $0x1, R2:R32, .Operands) => . ... - RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( rol( Mem32, mi(32, 1)), 31, 32) +RSMap:Map => updateMap(RSMap, +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), rol( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, 1))) + +"CF" |-> extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, 1)), 31, 32) + +"OF" |-> (#ifMInt (eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, 1)), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, 1)), 31, 32), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +) -"OF" |-> (#ifMInt (eqMInt( extractMInt( rol( Mem32, mi(32, 1)), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( Mem32, mi(32, 1)), 31, 32), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) - ) + +endmodule + +module ROLL-R32-ONE-SEMANTICS + imports ROLL-R32-ONE endmodule diff --git a/semantics/run-on-elf.py b/semantics/run-on-elf.py index 4d4528aea..067654376 100755 --- a/semantics/run-on-elf.py +++ b/semantics/run-on-elf.py @@ -111,7 +111,7 @@ def inum_file_pair_from_line(line): def get_instructions_from_inums(inums): with open(os.path.join(decoder_directory, "generator", "datafiles", "full-map.txt"), "r") as f: - return list(map(lambda pair: pair[1], filter(lambda pair: pair[0] in inums, map(inum_file_pair_from_line, f.readlines())))) + return list(set(map(lambda pair: pair[1], filter(lambda pair: pair[0] in inums, map(inum_file_pair_from_line, f.readlines()))))) def copy_instructions(full_names): for name in full_names: diff --git a/semantics/systemInstructions/callq_rel32.k b/semantics/systemInstructions/callq_rel32.k index 42e5a159b..abd054b19 100644 --- a/semantics/systemInstructions/callq_rel32.k +++ b/semantics/systemInstructions/callq_rel32.k @@ -13,16 +13,18 @@ module CALLQ-REL32 rule - execinstr (callq Imm32:Imm, .Operands) => + execinstr (callq Imm32:MInt, .Operands) => storeToMemory({RSMap["RIP"]}:>MInt, subMInt(getRegisterValue(%rsp, RSMap), mi(64, 8)), 64) ~> decRSPInBytes(8) ... - RSMap => updateMap(RSMap, ("RIP" |->addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)) )) + RSMap => updateMap(RSMap, ("RIP" |->addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)) )) SymMap - requires notBool HasBuiltinAtAddress(SymMap, addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64))) + requires notBool HasBuiltinAtAddress(SymMap, addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64))) + andBool bitwidthMInt(Imm32) ==Int 32 - rule execinstr (callq Imm32:Imm, .Operands) => execinstr(call GetBuiltinFromAddress(SymMap, addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) ... + rule execinstr (callq Imm32:MInt, .Operands) => execinstr(call GetBuiltinFromAddress(SymMap, addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) ... RSMap SymMap - requires HasBuiltinAtAddress(SymMap, addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64))) + requires HasBuiltinAtAddress(SymMap, addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64))) + andBool bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/systemInstructions/ja_rel32.k b/semantics/systemInstructions/ja_rel32.k index 7edfdbd8f..987f2fc69 100644 --- a/semantics/systemInstructions/ja_rel32.k +++ b/semantics/systemInstructions/ja_rel32.k @@ -4,7 +4,14 @@ module JA-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule execinstr (ja Imm32:Imm, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + rule execinstr (ja Imm32:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) + + requires bitwidthMInt(Imm32) ==Int 32 andBool + (eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) + + rule execinstr (ja Imm32:MInt, .Operands) => . ... + RSMap + requires bitwidthMInt(Imm32) ==Int 32 andBool + (eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) orBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1))) endmodule diff --git a/semantics/systemInstructions/ja_rel8.k b/semantics/systemInstructions/ja_rel8.k index 351771832..96bc20187 100644 --- a/semantics/systemInstructions/ja_rel8.k +++ b/semantics/systemInstructions/ja_rel8.k @@ -6,19 +6,20 @@ module JA-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (ja Imm8:Imm, .Operands) => . + execinstr (ja Imm8:MInt, .Operands) => . ... RSMap => updateMap(RSMap, ("RIP" |-> - addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, - 8, 64)))) + addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) - andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) + andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) rule - execinstr (ja Imm8:Imm, .Operands) => . + execinstr (ja Imm8:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) - orBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + orBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1))) endmodule diff --git a/semantics/systemInstructions/jae_rel32.k b/semantics/systemInstructions/jae_rel32.k index 8cd55a406..697ee5c2b 100644 --- a/semantics/systemInstructions/jae_rel32.k +++ b/semantics/systemInstructions/jae_rel32.k @@ -6,15 +6,17 @@ module JAE-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jae Imm32:Imm, .Operands) => . + execinstr (jae Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) rule - execinstr (jae Imm32:Imm, .Operands) => . + execinstr (jae Imm32:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jae_rel8.k b/semantics/systemInstructions/jae_rel8.k index 4b2189dc2..059459b19 100644 --- a/semantics/systemInstructions/jae_rel8.k +++ b/semantics/systemInstructions/jae_rel8.k @@ -6,15 +6,17 @@ module JAE-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jae Imm8:Imm, .Operands) => . + execinstr (jae Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) rule - execinstr (jae Imm8:Imm, .Operands) => . + execinstr (jae Imm8:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jb_rel32.k b/semantics/systemInstructions/jb_rel32.k index 004b1bd55..d951f3789 100644 --- a/semantics/systemInstructions/jb_rel32.k +++ b/semantics/systemInstructions/jb_rel32.k @@ -6,15 +6,17 @@ module JB-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jb Imm32:Imm, .Operands) => . + execinstr (jb Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) rule - execinstr (jb Imm32:Imm, .Operands) => . + execinstr (jb Imm32:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jb_rel8.k b/semantics/systemInstructions/jb_rel8.k index 2054d3e2b..dfb9fd6fe 100644 --- a/semantics/systemInstructions/jb_rel8.k +++ b/semantics/systemInstructions/jb_rel8.k @@ -6,15 +6,17 @@ module JB-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jb Imm8:Imm, .Operands) => . + execinstr (jb Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) rule - execinstr (jb Imm8:Imm, .Operands) => . + execinstr (jb Imm8:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jbe_rel32.k b/semantics/systemInstructions/jbe_rel32.k index 2682bbf2c..3f64d6359 100644 --- a/semantics/systemInstructions/jbe_rel32.k +++ b/semantics/systemInstructions/jbe_rel32.k @@ -6,17 +6,19 @@ module JBE-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jbe Imm32:Imm, .Operands) => . + execinstr (jbe Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) - orBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + (eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + orBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1))) rule - execinstr (jbe Imm32:Imm, .Operands) => . + execinstr (jbe Imm32:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) - andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + (eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) + andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) endmodule diff --git a/semantics/systemInstructions/jbe_rel8.k b/semantics/systemInstructions/jbe_rel8.k index ed8c2ceae..b0c3bb039 100644 --- a/semantics/systemInstructions/jbe_rel8.k +++ b/semantics/systemInstructions/jbe_rel8.k @@ -6,17 +6,19 @@ module JBE-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jbe Imm8:Imm, .Operands) => . + execinstr (jbe Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) - orBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + orBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1))) rule - execinstr (jbe Imm8:Imm, .Operands) => . + execinstr (jbe Imm8:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) - andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) + andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) endmodule diff --git a/semantics/systemInstructions/jc_rel32.k b/semantics/systemInstructions/jc_rel32.k index e33369bbe..d75d1231b 100644 --- a/semantics/systemInstructions/jc_rel32.k +++ b/semantics/systemInstructions/jc_rel32.k @@ -6,15 +6,17 @@ module JC-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jc Imm32:Imm, .Operands) => . + execinstr (jc Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) rule - execinstr (jc Imm32:Imm, .Operands) => . + execinstr (jc Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jc_rel8.k b/semantics/systemInstructions/jc_rel8.k index 656ff31d8..07e2e66a1 100644 --- a/semantics/systemInstructions/jc_rel8.k +++ b/semantics/systemInstructions/jc_rel8.k @@ -6,15 +6,17 @@ module JC-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jc Imm8:Imm, .Operands) => . + execinstr (jc Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) rule - execinstr (jc Imm8:Imm, .Operands) => . + execinstr (jc Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/je_rel32.k b/semantics/systemInstructions/je_rel32.k index 2948258c5..3071bf335 100644 --- a/semantics/systemInstructions/je_rel32.k +++ b/semantics/systemInstructions/je_rel32.k @@ -6,15 +6,17 @@ module JE-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (je Imm32:Imm, .Operands) => . + execinstr (je Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) rule - execinstr (je Imm32:Imm, .Operands) => . + execinstr (je Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/je_rel8.k b/semantics/systemInstructions/je_rel8.k index 4d35997ca..204e8355c 100644 --- a/semantics/systemInstructions/je_rel8.k +++ b/semantics/systemInstructions/je_rel8.k @@ -6,15 +6,17 @@ module JE-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (je Imm8:Imm, .Operands) => . + execinstr (je Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) rule - execinstr (je Imm8:Imm, .Operands) => . + execinstr (je Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jecxz_rel8.k b/semantics/systemInstructions/jecxz_rel8.k index c6fe21868..60e07b1de 100644 --- a/semantics/systemInstructions/jecxz_rel8.k +++ b/semantics/systemInstructions/jecxz_rel8.k @@ -6,15 +6,17 @@ module JECXZ-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jecxz Imm8:Imm, .Operands) => . + execinstr (jecxz Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt(getRegisterValue(%ecx, RSMap), mi(32, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt(getRegisterValue(%ecx, RSMap), mi(32, 0)) rule - execinstr (jecxz Imm8:Imm, .Operands) => . + execinstr (jecxz Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt(getRegisterValue(%ecx, RSMap), mi(32, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt(getRegisterValue(%ecx, RSMap), mi(32, 0)) endmodule diff --git a/semantics/systemInstructions/jg_rel32.k b/semantics/systemInstructions/jg_rel32.k index 34847e9a4..295492de4 100644 --- a/semantics/systemInstructions/jg_rel32.k +++ b/semantics/systemInstructions/jg_rel32.k @@ -4,19 +4,21 @@ module JG-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jg Imm32:Imm, .Operands) => . + execinstr (jg Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + (eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) andBool - eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) rule - execinstr (jg Imm32:Imm, .Operands) => . + execinstr (jg Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + (notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) orBool - notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) endmodule diff --git a/semantics/systemInstructions/jg_rel8.k b/semantics/systemInstructions/jg_rel8.k index 2109d3880..49e48a412 100644 --- a/semantics/systemInstructions/jg_rel8.k +++ b/semantics/systemInstructions/jg_rel8.k @@ -4,19 +4,21 @@ module JG-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jg Imm8:Imm, .Operands) => . + execinstr (jg Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) andBool - eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) rule - execinstr (jg Imm8:Imm, .Operands) => . + execinstr (jg Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) orBool - notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) endmodule diff --git a/semantics/systemInstructions/jge_rel32.k b/semantics/systemInstructions/jge_rel32.k index 0ef51e517..a5e4ba1bb 100644 --- a/semantics/systemInstructions/jge_rel32.k +++ b/semantics/systemInstructions/jge_rel32.k @@ -4,15 +4,17 @@ module JGE-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jge Imm32:Imm, .Operands) => . + execinstr (jge Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) rule - execinstr (jge Imm32:Imm, .Operands) => . + execinstr (jge Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm32) ==Int 32 andBool + notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) endmodule diff --git a/semantics/systemInstructions/jge_rel8.k b/semantics/systemInstructions/jge_rel8.k index c8743fdc1..751e1bfd5 100644 --- a/semantics/systemInstructions/jge_rel8.k +++ b/semantics/systemInstructions/jge_rel8.k @@ -4,15 +4,17 @@ module JGE-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jge Imm8:Imm, .Operands) => . + execinstr (jge Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) rule - execinstr (jge Imm8:Imm, .Operands) => . + execinstr (jge Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) endmodule diff --git a/semantics/systemInstructions/jl_rel32.k b/semantics/systemInstructions/jl_rel32.k index 339a7b9ec..407ce8bc6 100644 --- a/semantics/systemInstructions/jl_rel32.k +++ b/semantics/systemInstructions/jl_rel32.k @@ -4,15 +4,17 @@ module JL-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jl Imm32:Imm, .Operands) => . + execinstr (jl Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm32) ==Int 32 andBool + notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) rule - execinstr (jl Imm32:Imm, .Operands) => . + execinstr (jl Imm32:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) endmodule diff --git a/semantics/systemInstructions/jl_rel8.k b/semantics/systemInstructions/jl_rel8.k index 68260efd4..0a1ab84b9 100644 --- a/semantics/systemInstructions/jl_rel8.k +++ b/semantics/systemInstructions/jl_rel8.k @@ -4,15 +4,17 @@ module JL-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jl Imm8:Imm, .Operands) => . + execinstr (jl Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) rule - execinstr (jl Imm8:Imm, .Operands) => . + execinstr (jl Imm8:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) endmodule diff --git a/semantics/systemInstructions/jle_rel32.k b/semantics/systemInstructions/jle_rel32.k index 0449a5c20..c2f827b94 100644 --- a/semantics/systemInstructions/jle_rel32.k +++ b/semantics/systemInstructions/jle_rel32.k @@ -4,19 +4,21 @@ module JLE-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jle Imm32:Imm, .Operands) => . + execinstr (jle Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + (eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) orBool - (notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) + (notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt))) rule - execinstr (jle Imm32:Imm, .Operands) => . + execinstr (jle Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + (notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) andBool - eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) endmodule diff --git a/semantics/systemInstructions/jle_rel8.k b/semantics/systemInstructions/jle_rel8.k index c901c2d30..f818684b9 100644 --- a/semantics/systemInstructions/jle_rel8.k +++ b/semantics/systemInstructions/jle_rel8.k @@ -4,19 +4,21 @@ module JLE-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jle Imm8:Imm, .Operands) => . + execinstr (jle Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) orBool - (notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) + (notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt))) rule - execinstr (jle Imm8:Imm, .Operands) => . + execinstr (jle Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) andBool - eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) endmodule diff --git a/semantics/systemInstructions/jmp_rel32.k b/semantics/systemInstructions/jmp_rel32.k index 65e64af0e..20f25aa3c 100644 --- a/semantics/systemInstructions/jmp_rel32.k +++ b/semantics/systemInstructions/jmp_rel32.k @@ -5,9 +5,10 @@ module JMPQ-REL32 imports X86-CONFIGURATION rule - execinstr (jmp Imm32:Imm, .Operands) => . + execinstr (jmp Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/systemInstructions/jmp_rel8.k b/semantics/systemInstructions/jmp_rel8.k index c6b80b5ce..3c940e93e 100644 --- a/semantics/systemInstructions/jmp_rel8.k +++ b/semantics/systemInstructions/jmp_rel8.k @@ -5,9 +5,10 @@ module JMPQ-REL8 imports X86-CONFIGURATION rule - execinstr (jmp Imm8:Imm, .Operands) => . + execinstr (jmp Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/systemInstructions/jna_rel32.k b/semantics/systemInstructions/jna_rel32.k index 54a425921..a2740b9e3 100644 --- a/semantics/systemInstructions/jna_rel32.k +++ b/semantics/systemInstructions/jna_rel32.k @@ -6,17 +6,19 @@ module JNA-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jna Imm32:Imm, .Operands) => . + execinstr (jna Imm32:MInt, .Operands) => . ... RSMap => updateMap(RSMap, ("RIP" |-> - addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, - 32, 64)))) + addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, + 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) orBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + (eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) orBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1))) rule - execinstr (jna Imm32:Imm, .Operands) => . + execinstr (jna Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) andBool notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + (notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) andBool notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1))) endmodule diff --git a/semantics/systemInstructions/jna_rel8.k b/semantics/systemInstructions/jna_rel8.k index 810660cc5..ae854f827 100644 --- a/semantics/systemInstructions/jna_rel8.k +++ b/semantics/systemInstructions/jna_rel8.k @@ -6,17 +6,19 @@ module JNA-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jna Imm8:Imm, .Operands) => . + execinstr (jna Imm8:MInt, .Operands) => . ... RSMap => updateMap(RSMap, ("RIP" |-> - addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, - 8, 64)))) + addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, + 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) orBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) orBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1))) rule - execinstr (jna Imm8:Imm, .Operands) => . + execinstr (jna Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) andBool notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) andBool notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1))) endmodule diff --git a/semantics/systemInstructions/jnae_rel32.k b/semantics/systemInstructions/jnae_rel32.k index 9c8d96d54..ac18612a0 100644 --- a/semantics/systemInstructions/jnae_rel32.k +++ b/semantics/systemInstructions/jnae_rel32.k @@ -6,15 +6,17 @@ module JNAE-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnae Imm32:Imm, .Operands) => . + execinstr (jnae Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) rule - execinstr (jnae Imm32:Imm, .Operands) => . + execinstr (jnae Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jnae_rel8.k b/semantics/systemInstructions/jnae_rel8.k index 1080e3fd4..9f5afa5dc 100644 --- a/semantics/systemInstructions/jnae_rel8.k +++ b/semantics/systemInstructions/jnae_rel8.k @@ -6,15 +6,17 @@ module JNAE-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnae Imm8:Imm, .Operands) => . + execinstr (jnae Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) rule - execinstr (jnae Imm8:Imm, .Operands) => . + execinstr (jnae Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jnb_rel32.k b/semantics/systemInstructions/jnb_rel32.k index 471150ca7..23760c8a5 100644 --- a/semantics/systemInstructions/jnb_rel32.k +++ b/semantics/systemInstructions/jnb_rel32.k @@ -6,15 +6,17 @@ module JNB-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnb Imm32:Imm, .Operands) => . + execinstr (jnb Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) rule - execinstr (jnb Imm32:Imm, .Operands) => . + execinstr (jnb Imm32:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jnb_rel8.k b/semantics/systemInstructions/jnb_rel8.k index 215a340da..d831e9646 100644 --- a/semantics/systemInstructions/jnb_rel8.k +++ b/semantics/systemInstructions/jnb_rel8.k @@ -6,15 +6,17 @@ module JNB-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnb Imm8:Imm, .Operands) => . + execinstr (jnb Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) rule - execinstr (jnb Imm8:Imm, .Operands) => . + execinstr (jnb Imm8:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jnbe_rel32.k b/semantics/systemInstructions/jnbe_rel32.k index d63320a24..f042a5fbe 100644 --- a/semantics/systemInstructions/jnbe_rel32.k +++ b/semantics/systemInstructions/jnbe_rel32.k @@ -6,18 +6,20 @@ module JNBE-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnbe Imm32:Imm, .Operands) => . + execinstr (jnbe Imm32:MInt, .Operands) => . ... RSMap => updateMap(RSMap, ("RIP" |-> - addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, - 32, 64)))) + addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, + 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + (eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) rule - execinstr (jnbe Imm32:Imm, .Operands) => . + execinstr (jnbe Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) - orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + (notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) + orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) endmodule diff --git a/semantics/systemInstructions/jnbe_rel8.k b/semantics/systemInstructions/jnbe_rel8.k index 5790a0235..ea4ef54ac 100644 --- a/semantics/systemInstructions/jnbe_rel8.k +++ b/semantics/systemInstructions/jnbe_rel8.k @@ -6,18 +6,20 @@ module JNBE-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnbe Imm8:Imm, .Operands) => . + execinstr (jnbe Imm8:MInt, .Operands) => . ... RSMap => updateMap(RSMap, ("RIP" |-> - addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, - 8, 64)))) + addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, + 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) rule - execinstr (jnbe Imm8:Imm, .Operands) => . + execinstr (jnbe Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) - orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) + orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) endmodule diff --git a/semantics/systemInstructions/jnc_rel32.k b/semantics/systemInstructions/jnc_rel32.k index c83c6ce85..4c86fa2f7 100644 --- a/semantics/systemInstructions/jnc_rel32.k +++ b/semantics/systemInstructions/jnc_rel32.k @@ -6,15 +6,17 @@ module JNC-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnc Imm32:Imm, .Operands) => . + execinstr (jnc Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) rule - execinstr (jnc Imm32:Imm, .Operands) => . + execinstr (jnc Imm32:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jnc_rel8.k b/semantics/systemInstructions/jnc_rel8.k index 409270d14..348665660 100644 --- a/semantics/systemInstructions/jnc_rel8.k +++ b/semantics/systemInstructions/jnc_rel8.k @@ -6,15 +6,17 @@ module JNC-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnc Imm8:Imm, .Operands) => . + execinstr (jnc Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) rule - execinstr (jnc Imm8:Imm, .Operands) => . + execinstr (jnc Imm8:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jne_rel32.k b/semantics/systemInstructions/jne_rel32.k index df758fe3b..3ef4d9f48 100644 --- a/semantics/systemInstructions/jne_rel32.k +++ b/semantics/systemInstructions/jne_rel32.k @@ -6,15 +6,17 @@ module JNE-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jne Imm32:Imm, .Operands) => . + execinstr (jne Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) rule - execinstr (jne Imm32:Imm, .Operands) => . + execinstr (jne Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jne_rel8.k b/semantics/systemInstructions/jne_rel8.k index d6fbd8aca..d442a86c0 100644 --- a/semantics/systemInstructions/jne_rel8.k +++ b/semantics/systemInstructions/jne_rel8.k @@ -6,15 +6,17 @@ module JNE-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jne Imm8:Imm, .Operands) => . + execinstr (jne Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) rule - execinstr (jne Imm8:Imm, .Operands) => . + execinstr (jne Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jng_rel32.k b/semantics/systemInstructions/jng_rel32.k index 8706aaf5e..4f9fafeda 100644 --- a/semantics/systemInstructions/jng_rel32.k +++ b/semantics/systemInstructions/jng_rel32.k @@ -6,15 +6,17 @@ module JNG-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jng Imm32:Imm, .Operands) => . + execinstr (jng Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) orBool notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm32) ==Int 32 andBool + (eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) orBool notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) rule - execinstr (jng Imm32:Imm, .Operands) => . + execinstr (jng Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) andBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm32) ==Int 32 andBool + (notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) andBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) endmodule diff --git a/semantics/systemInstructions/jng_rel8.k b/semantics/systemInstructions/jng_rel8.k index b15e8f7c0..d8b505c01 100644 --- a/semantics/systemInstructions/jng_rel8.k +++ b/semantics/systemInstructions/jng_rel8.k @@ -6,15 +6,17 @@ module JNG-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jng Imm8:Imm, .Operands) => . + execinstr (jng Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) orBool notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) orBool notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) rule - execinstr (jng Imm8:Imm, .Operands) => . + execinstr (jng Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) andBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) andBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) endmodule diff --git a/semantics/systemInstructions/jnge_rel32.k b/semantics/systemInstructions/jnge_rel32.k index a49f5d310..a04ced00d 100644 --- a/semantics/systemInstructions/jnge_rel32.k +++ b/semantics/systemInstructions/jnge_rel32.k @@ -6,15 +6,17 @@ module JNGE-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnge Imm32:Imm, .Operands) => . + execinstr (jnge Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm32) ==Int 32 andBool + notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) rule - execinstr (jnge Imm32:Imm, .Operands) => . + execinstr (jnge Imm32:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) endmodule diff --git a/semantics/systemInstructions/jnge_rel8.k b/semantics/systemInstructions/jnge_rel8.k index e6cafc657..adf16426e 100644 --- a/semantics/systemInstructions/jnge_rel8.k +++ b/semantics/systemInstructions/jnge_rel8.k @@ -6,15 +6,17 @@ module JNGE-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnge Imm8:Imm, .Operands) => . + execinstr (jnge Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) rule - execinstr (jnge Imm8:Imm, .Operands) => . + execinstr (jnge Imm8:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) endmodule diff --git a/semantics/systemInstructions/jnl_rel32.k b/semantics/systemInstructions/jnl_rel32.k index 0777ad103..440ddf0ea 100644 --- a/semantics/systemInstructions/jnl_rel32.k +++ b/semantics/systemInstructions/jnl_rel32.k @@ -6,15 +6,17 @@ module JNL-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnl Imm32:Imm, .Operands) => . + execinstr (jnl Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) rule - execinstr (jnl Imm32:Imm, .Operands) => . + execinstr (jnl Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm32) ==Int 32 andBool + notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) endmodule diff --git a/semantics/systemInstructions/jnl_rel8.k b/semantics/systemInstructions/jnl_rel8.k index 0db8374fb..50f56302d 100644 --- a/semantics/systemInstructions/jnl_rel8.k +++ b/semantics/systemInstructions/jnl_rel8.k @@ -6,15 +6,17 @@ module JNL-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnl Imm8:Imm, .Operands) => . + execinstr (jnl Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) rule - execinstr (jnl Imm8:Imm, .Operands) => . + execinstr (jnl Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) endmodule diff --git a/semantics/systemInstructions/jnle_rel32.k b/semantics/systemInstructions/jnle_rel32.k index 038a3e6a5..e772fc77a 100644 --- a/semantics/systemInstructions/jnle_rel32.k +++ b/semantics/systemInstructions/jnle_rel32.k @@ -6,15 +6,17 @@ module JNLE-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnle Imm32:Imm, .Operands) => . + execinstr (jnle Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm32) ==Int 32 andBool + (eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) rule - execinstr (jnle Imm32:Imm, .Operands) => . + execinstr (jnle Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) orBool notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm32) ==Int 32 andBool + (notBool eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) orBool notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) endmodule diff --git a/semantics/systemInstructions/jnle_rel8.k b/semantics/systemInstructions/jnle_rel8.k index 188425453..44fd34677 100644 --- a/semantics/systemInstructions/jnle_rel8.k +++ b/semantics/systemInstructions/jnle_rel8.k @@ -6,15 +6,17 @@ module JNLE-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnle Imm8:Imm, .Operands) => . + execinstr (jnle Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) rule - execinstr (jnle Imm8:Imm, .Operands) => . + execinstr (jnle Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) orBool notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (notBool eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) orBool notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) endmodule diff --git a/semantics/systemInstructions/jno_rel32.k b/semantics/systemInstructions/jno_rel32.k index 52ca31290..593c31f33 100644 --- a/semantics/systemInstructions/jno_rel32.k +++ b/semantics/systemInstructions/jno_rel32.k @@ -6,15 +6,17 @@ module JNO-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jno Imm32:Imm, .Operands) => . + execinstr (jno Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["OF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["OF"]}:>MInt, mi(1, 0)) rule - execinstr (jno Imm32:Imm, .Operands) => . + execinstr (jno Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["OF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + notBool eqMInt({RSMap["OF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jno_rel8.k b/semantics/systemInstructions/jno_rel8.k index dbb1e0ce8..8741ffeef 100644 --- a/semantics/systemInstructions/jno_rel8.k +++ b/semantics/systemInstructions/jno_rel8.k @@ -6,15 +6,17 @@ module JNO-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jno Imm8:Imm, .Operands) => . + execinstr (jno Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["OF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["OF"]}:>MInt, mi(1, 0)) rule - execinstr (jno Imm8:Imm, .Operands) => . + execinstr (jno Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["OF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt({RSMap["OF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jnp_rel32.k b/semantics/systemInstructions/jnp_rel32.k index c44e8957b..68adf18c3 100644 --- a/semantics/systemInstructions/jnp_rel32.k +++ b/semantics/systemInstructions/jnp_rel32.k @@ -6,15 +6,17 @@ module JNP-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnp Imm32:Imm, .Operands) => . + execinstr (jnp Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) rule - execinstr (jnp Imm32:Imm, .Operands) => . + execinstr (jnp Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + notBool eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jnp_rel8.k b/semantics/systemInstructions/jnp_rel8.k index 0a0509c8b..9a54f70a8 100644 --- a/semantics/systemInstructions/jnp_rel8.k +++ b/semantics/systemInstructions/jnp_rel8.k @@ -6,15 +6,17 @@ module JNP-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnp Imm8:Imm, .Operands) => . + execinstr (jnp Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) rule - execinstr (jnp Imm8:Imm, .Operands) => . + execinstr (jnp Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jns_rel32.k b/semantics/systemInstructions/jns_rel32.k index e0f6b0b25..7e2a9b089 100644 --- a/semantics/systemInstructions/jns_rel32.k +++ b/semantics/systemInstructions/jns_rel32.k @@ -6,15 +6,17 @@ module JNS-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jns Imm32:Imm, .Operands) => . + execinstr (jns Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) rule - execinstr (jns Imm32:Imm, .Operands) => . + execinstr (jns Imm32:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["SF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["SF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jns_rel8.k b/semantics/systemInstructions/jns_rel8.k index ee3a25cdc..25353444d 100644 --- a/semantics/systemInstructions/jns_rel8.k +++ b/semantics/systemInstructions/jns_rel8.k @@ -6,15 +6,17 @@ module JNS-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jns Imm8:Imm, .Operands) => . + execinstr (jns Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) rule - execinstr (jns Imm8:Imm, .Operands) => . + execinstr (jns Imm8:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["SF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["SF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jnz_rel32.k b/semantics/systemInstructions/jnz_rel32.k index c4758b651..25380d73a 100644 --- a/semantics/systemInstructions/jnz_rel32.k +++ b/semantics/systemInstructions/jnz_rel32.k @@ -6,15 +6,17 @@ module JNZ-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnz Imm32:Imm, .Operands) => . + execinstr (jnz Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) rule - execinstr (jnz Imm32:Imm, .Operands) => . + execinstr (jnz Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jnz_rel8.k b/semantics/systemInstructions/jnz_rel8.k index 841e64a95..beeb4f24b 100644 --- a/semantics/systemInstructions/jnz_rel8.k +++ b/semantics/systemInstructions/jnz_rel8.k @@ -6,15 +6,17 @@ module JNZ-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnz Imm8:Imm, .Operands) => . + execinstr (jnz Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) rule - execinstr (jnz Imm8:Imm, .Operands) => . + execinstr (jnz Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jo_rel32.k b/semantics/systemInstructions/jo_rel32.k index 86a412670..fe453c6f6 100644 --- a/semantics/systemInstructions/jo_rel32.k +++ b/semantics/systemInstructions/jo_rel32.k @@ -6,15 +6,17 @@ module JO-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jo Imm32:Imm, .Operands) => . + execinstr (jo Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["OF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["OF"]}:>MInt, mi(1, 1)) rule - execinstr (jo Imm32:Imm, .Operands) => . + execinstr (jo Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["OF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + notBool eqMInt({RSMap["OF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jo_rel8.k b/semantics/systemInstructions/jo_rel8.k index 739212785..4affc1844 100644 --- a/semantics/systemInstructions/jo_rel8.k +++ b/semantics/systemInstructions/jo_rel8.k @@ -6,15 +6,17 @@ module JO-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jo Imm8:Imm, .Operands) => . + execinstr (jo Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["OF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["OF"]}:>MInt, mi(1, 1)) rule - execinstr (jo Imm8:Imm, .Operands) => . + execinstr (jo Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["OF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt({RSMap["OF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jp_rel32.k b/semantics/systemInstructions/jp_rel32.k index 8733bf2df..ad9524a68 100644 --- a/semantics/systemInstructions/jp_rel32.k +++ b/semantics/systemInstructions/jp_rel32.k @@ -6,15 +6,17 @@ module JP-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jp Imm32:Imm, .Operands) => . + execinstr (jp Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["PF"]}:>MInt, mi(1, 1)) rule - execinstr (jp Imm32:Imm, .Operands) => . + execinstr (jp Imm32:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jp_rel8.k b/semantics/systemInstructions/jp_rel8.k index f96cfcf61..1bcddf0b4 100644 --- a/semantics/systemInstructions/jp_rel8.k +++ b/semantics/systemInstructions/jp_rel8.k @@ -6,15 +6,17 @@ module JP-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jp Imm8:Imm, .Operands) => . + execinstr (jp Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["PF"]}:>MInt, mi(1, 1)) rule - execinstr (jp Imm8:Imm, .Operands) => . + execinstr (jp Imm8:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jpe_rel32.k b/semantics/systemInstructions/jpe_rel32.k index 6508fdad4..31522376b 100644 --- a/semantics/systemInstructions/jpe_rel32.k +++ b/semantics/systemInstructions/jpe_rel32.k @@ -6,15 +6,17 @@ module JPE-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jpe Imm32:Imm, .Operands) => . + execinstr (jpe Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["PF"]}:>MInt, mi(1, 1)) rule - execinstr (jpe Imm32:Imm, .Operands) => . + execinstr (jpe Imm32:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jpe_rel8.k b/semantics/systemInstructions/jpe_rel8.k index d812fa336..ef6bb2dbc 100644 --- a/semantics/systemInstructions/jpe_rel8.k +++ b/semantics/systemInstructions/jpe_rel8.k @@ -6,15 +6,17 @@ module JPE-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jpe Imm8:Imm, .Operands) => . + execinstr (jpe Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["PF"]}:>MInt, mi(1, 1)) rule - execinstr (jpe Imm8:Imm, .Operands) => . + execinstr (jpe Imm8:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jpo_rel32.k b/semantics/systemInstructions/jpo_rel32.k index 1c2b4518f..ee70f0267 100644 --- a/semantics/systemInstructions/jpo_rel32.k +++ b/semantics/systemInstructions/jpo_rel32.k @@ -6,15 +6,17 @@ module JPO-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jpo Imm32:Imm, .Operands) => . + execinstr (jpo Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) rule - execinstr (jpo Imm32:Imm, .Operands) => . + execinstr (jpo Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + notBool eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jpo_rel8.k b/semantics/systemInstructions/jpo_rel8.k index 3cafc614b..45a4d5ca6 100644 --- a/semantics/systemInstructions/jpo_rel8.k +++ b/semantics/systemInstructions/jpo_rel8.k @@ -6,15 +6,17 @@ module JPO-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jpo Imm8:Imm, .Operands) => . + execinstr (jpo Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) rule - execinstr (jpo Imm8:Imm, .Operands) => . + execinstr (jpo Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jrcxz_rel8.k b/semantics/systemInstructions/jrcxz_rel8.k index a95d4d5e6..6c5be105f 100644 --- a/semantics/systemInstructions/jrcxz_rel8.k +++ b/semantics/systemInstructions/jrcxz_rel8.k @@ -6,15 +6,17 @@ module JRCXZ-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jrcxz Imm8:Imm, .Operands) => . + execinstr (jrcxz Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt(getRegisterValue(%rcx, RSMap), mi(64, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt(getRegisterValue(%rcx, RSMap), mi(64, 0)) rule - execinstr (jrcxz Imm8:Imm, .Operands) => . + execinstr (jrcxz Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt(getRegisterValue(%rcx, RSMap), mi(64, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt(getRegisterValue(%rcx, RSMap), mi(64, 0)) endmodule diff --git a/semantics/systemInstructions/js_rel32.k b/semantics/systemInstructions/js_rel32.k index 1de9d7f0a..50b6dcf19 100644 --- a/semantics/systemInstructions/js_rel32.k +++ b/semantics/systemInstructions/js_rel32.k @@ -6,15 +6,17 @@ module JS-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (js Imm32:Imm, .Operands) => . + execinstr (js Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["SF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["SF"]}:>MInt, mi(1, 1)) rule - execinstr (js Imm32:Imm, .Operands) => . + execinstr (js Imm32:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/js_rel8.k b/semantics/systemInstructions/js_rel8.k index 4f4c10f99..4d1431c76 100644 --- a/semantics/systemInstructions/js_rel8.k +++ b/semantics/systemInstructions/js_rel8.k @@ -6,15 +6,17 @@ module JS-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (js Imm8:Imm, .Operands) => . + execinstr (js Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["SF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["SF"]}:>MInt, mi(1, 1)) rule - execinstr (js Imm8:Imm, .Operands) => . + execinstr (js Imm8:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jz_rel32.k b/semantics/systemInstructions/jz_rel32.k index 2b9b564ca..788921fe5 100644 --- a/semantics/systemInstructions/jz_rel32.k +++ b/semantics/systemInstructions/jz_rel32.k @@ -6,15 +6,17 @@ module JZ-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jz Imm32:Imm, .Operands) => . + execinstr (jz Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) rule - execinstr (jz Imm32:Imm, .Operands) => . + execinstr (jz Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jz_rel8.k b/semantics/systemInstructions/jz_rel8.k index 2e216103a..a57a3d65a 100644 --- a/semantics/systemInstructions/jz_rel8.k +++ b/semantics/systemInstructions/jz_rel8.k @@ -6,15 +6,17 @@ module JZ-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jz Imm8:Imm, .Operands) => . + execinstr (jz Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) rule - execinstr (jz Imm8:Imm, .Operands) => . + execinstr (jz Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/leaveq.k b/semantics/systemInstructions/leaveq.k index 8f32b5676..e68fc30f2 100644 --- a/semantics/systemInstructions/leaveq.k +++ b/semantics/systemInstructions/leaveq.k @@ -5,7 +5,7 @@ module RETQ imports X86-CONFIGURATION rule - execinstr (leave .Operands) => + execinstr (leaveq .Operands) => execinstr(movq %rbp, %rsp, .Operands) ~> execinstr(popq %rbp, .Operands) ... diff --git a/semantics/systemInstructions/loop_rel8.k b/semantics/systemInstructions/loop_rel8.k index afacd9541..e490e63f1 100644 --- a/semantics/systemInstructions/loop_rel8.k +++ b/semantics/systemInstructions/loop_rel8.k @@ -6,27 +6,30 @@ module LOOP-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (loop Imm8:Imm, .Operands) => execinstr (loop Imm8, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) + execinstr (loop Imm8:MInt, .Operands) => execinstr (loop Imm8, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule - execinstr (loop Imm8:Imm, Count:MInt, .Operands) => . + execinstr (loop Imm8:MInt, Count:MInt, .Operands) => . ... RSMap => updateMap(RSMap, - ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64))) + ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64))) ("RCX" |-> Count) ) - requires notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) rule - execinstr (loop Imm8:Imm, Count:MInt, .Operands) => . + execinstr (loop Imm8:MInt, Count:MInt, .Operands) => . ... RSMap => updateMap(RSMap, ("RCX" |-> Count) ) - requires eqMInt(Count, mi(bitwidthMInt(Count), 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt(Count, mi(bitwidthMInt(Count), 0)) endmodule diff --git a/semantics/systemInstructions/loope_rel8.k b/semantics/systemInstructions/loope_rel8.k index d904ef8a0..140a98d9d 100644 --- a/semantics/systemInstructions/loope_rel8.k +++ b/semantics/systemInstructions/loope_rel8.k @@ -6,29 +6,32 @@ module LOOPE-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (loope Imm8:Imm, .Operands) => execinstr (loope Imm8, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) + execinstr (loope Imm8:MInt, .Operands) => execinstr (loope Imm8, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule - execinstr (loope Imm8:Imm, Count:MInt, .Operands) => . + execinstr (loope Imm8:MInt, Count:MInt, .Operands) => . ... RSMap => updateMap(RSMap, - ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64))) + ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64))) ("RCX" |-> Count) ) - requires notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) - andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) + andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1))) rule - execinstr (loope Imm8:Imm, Count:MInt, .Operands) => . + execinstr (loope Imm8:MInt, Count:MInt, .Operands) => . ... RSMap => updateMap(RSMap, ("RCX" |-> Count) ) - requires eqMInt(Count, mi(bitwidthMInt(Count), 0)) - orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (eqMInt(Count, mi(bitwidthMInt(Count), 0)) + orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1))) endmodule diff --git a/semantics/systemInstructions/loopne_rel8.k b/semantics/systemInstructions/loopne_rel8.k index df3a61da7..a6cde7c73 100644 --- a/semantics/systemInstructions/loopne_rel8.k +++ b/semantics/systemInstructions/loopne_rel8.k @@ -6,29 +6,32 @@ module LOOPNE-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (loopne Imm8:Imm, .Operands) => execinstr (loope Imm8, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) + execinstr (loopne Imm8:MInt, .Operands) => execinstr (loope Imm8, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule - execinstr (loopne Imm8:Imm, Count:MInt, .Operands) => . + execinstr (loopne Imm8:MInt, Count:MInt, .Operands) => . ... RSMap => updateMap(RSMap, - ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64))) + ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64))) ("RCX" |-> Count) ) - requires notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) - andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) + andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) rule - execinstr (loopne Imm8:Imm, Count:MInt, .Operands) => . + execinstr (loopne Imm8:MInt, Count:MInt, .Operands) => . ... RSMap => updateMap(RSMap, ("RCX" |-> Count) ) - requires eqMInt(Count, mi(bitwidthMInt(Count), 0)) - orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (eqMInt(Count, mi(bitwidthMInt(Count), 0)) + orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) endmodule diff --git a/semantics/systemInstructions/loopnz_rel8.k b/semantics/systemInstructions/loopnz_rel8.k index c37403c96..bf1b354b7 100644 --- a/semantics/systemInstructions/loopnz_rel8.k +++ b/semantics/systemInstructions/loopnz_rel8.k @@ -6,29 +6,32 @@ module LOOPNE-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (loopnz Imm8:Imm, .Operands) => execinstr (loopnz Imm8, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) + execinstr (loopnz Imm8:MInt, .Operands) => execinstr (loopnz Imm8, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule - execinstr (loopnz Imm8:Imm, Count:MInt, .Operands) => . + execinstr (loopnz Imm8:MInt, Count:MInt, .Operands) => . ... RSMap => updateMap(RSMap, - ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64))) + ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64))) ("RCX" |-> Count) ) - requires notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) - andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + ( notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) + andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) rule - execinstr (loopnz Imm8:Imm, Count:MInt, .Operands) => . + execinstr (loopnz Imm8:MInt, Count:MInt, .Operands) => . ... RSMap => updateMap(RSMap, ("RCX" |-> Count) ) - requires eqMInt(Count, mi(bitwidthMInt(Count), 0)) - orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + ( eqMInt(Count, mi(bitwidthMInt(Count), 0)) + orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) endmodule diff --git a/semantics/systemInstructions/loopz_rel8.k b/semantics/systemInstructions/loopz_rel8.k index 444e23955..cfa525dd6 100644 --- a/semantics/systemInstructions/loopz_rel8.k +++ b/semantics/systemInstructions/loopz_rel8.k @@ -6,29 +6,32 @@ module LOOPE-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (loopz Imm8:Imm, .Operands) => execinstr (loopz Imm8, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) + execinstr (loopz Imm8:MInt, .Operands) => execinstr (loopz Imm8, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule - execinstr (loopz Imm8:Imm, Count:MInt, .Operands) => . + execinstr (loopz Imm8:MInt, Count:MInt, .Operands) => . ... RSMap => updateMap(RSMap, - ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64))) + ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64))) ("RCX" |-> Count) ) - requires notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) - andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + ( notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) + andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1))) rule - execinstr (loopz Imm8:Imm, Count:MInt, .Operands) => . + execinstr (loopz Imm8:MInt, Count:MInt, .Operands) => . ... RSMap => updateMap(RSMap, ("RCX" |-> Count) ) - requires eqMInt(Count, mi(bitwidthMInt(Count), 0)) - orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + ( eqMInt(Count, mi(bitwidthMInt(Count), 0)) + orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1))) endmodule diff --git a/semantics/test.c b/semantics/test.c index 6fe0ec8c0..08cf56f3c 100644 --- a/semantics/test.c +++ b/semantics/test.c @@ -1,13 +1,13 @@ #include #include -size_t fib(const int n) { +int fib(const int n) { if (n == 0) { return 0; } else if (n == 1) { return 1; } else { - size_t nums[n + 1]; + int nums[n + 1]; nums[0] = 0; nums[1] = 1; for (int i = 2; i <= n; ++i) { @@ -21,6 +21,6 @@ const int elems[] = {0, 1, 5, 10, 20, 40}; int main() { for (int i = 0; i < sizeof(elems) / sizeof(int); ++i) { - printf("%d: %lu\n", elems[i], fib(elems[i])); + printf("%d: %d\n", elems[i], fib(elems[i])); } } diff --git a/semantics/x86-abstract-semantics.k b/semantics/x86-abstract-semantics.k index 1c971d96f..79a6ce5d7 100644 --- a/semantics/x86-abstract-semantics.k +++ b/semantics/x86-abstract-semantics.k @@ -29,7 +29,8 @@ module X86-ABSTRACT-SEMANTICS instrcution. */ - // (%r64) + rule Address(A) => mi(64, A) ... + rule (R1:R64):Mem => 0 (R1:R64) ... rule I:Int (R1:R64):Mem => memOffset( addMInt(mi(64, I), getRegisterValue(R1, RSMap))) ... RSMap @@ -283,16 +284,21 @@ module X86-ABSTRACT-SEMANTICS setRegisterValue(MI, convSubRegsToRegs(R)) ... + + syntax MInt ::= KItemToMInt(KItem) [function] + rule KItemToMInt(MI:MInt) => MI + + /*@ Getting the registers values according to the register variants. */ - rule getRegisterValue(R:R8, RSMap) => extractMask({RSMap[convToRegKeys(R)]}:>MInt, 8, 0) - rule getRegisterValue(R:R16, RSMap) => extractMask({RSMap[convToRegKeys(R)]}:>MInt, 16, 0) - rule getRegisterValue(R:R32, RSMap) => extractMask({RSMap[convToRegKeys(R)]}:>MInt, 32, 0) - rule getRegisterValue(R:R64, RSMap) => {RSMap[convToRegKeys(R)]}:>MInt - rule getRegisterValue(R:Rh, RSMap) => extractMask({RSMap[convToRegKeys(R)]}:>MInt, 8, 8) - rule getRegisterValue(X:Xmm, RSMap) => extractMask({RSMap[convToRegKeys(X)]}:>MInt, 128, 0) - rule getRegisterValue(Y:Ymm, RSMap) => {RSMap[convToRegKeys(Y)]}:>MInt + rule getRegisterValue(R:R8, RSMap) => extractMask(KItemToMInt(RSMap[convToRegKeys(R)]), 8, 0) + rule getRegisterValue(R:R16, RSMap) => extractMask(KItemToMInt(RSMap[convToRegKeys(R)]), 16, 0) + rule getRegisterValue(R:R32, RSMap) => extractMask(KItemToMInt(RSMap[convToRegKeys(R)]), 32, 0) + rule getRegisterValue(R:R64, RSMap) => KItemToMInt(RSMap[convToRegKeys(R)]) + rule getRegisterValue(R:Rh, RSMap) => extractMask(KItemToMInt(RSMap[convToRegKeys(R)]), 8, 8) + rule getRegisterValue(X:Xmm, RSMap) => extractMask(KItemToMInt(RSMap[convToRegKeys(X)]), 128, 0) + rule getRegisterValue(Y:Ymm, RSMap) => KItemToMInt(RSMap[convToRegKeys(Y)]) /* rule getRegisterValue(M:Mm, RSMap) => {RSMap[convToRegKeys(M)]}:>MInt */ @@ -348,13 +354,13 @@ module X86-ABSTRACT-SEMANTICS rule decRSPInBytes(I:Int) => . ... RSMap:Map => updateMap( RSMap, - "RSP" |-> subMInt({RSMap["RSP"]}:>MInt, mi(64, I))) + "RSP" |-> subMInt(KItemToMInt(RSMap["RSP"]), mi(64, I))) rule incRSPInBytes(I:Int) => . ... RSMap:Map => updateMap( RSMap, - "RSP" |-> addMInt({RSMap["RSP"]}:>MInt, mi(64, I))) + "RSP" |-> addMInt(KItemToMInt(RSMap["RSP"]), mi(64, I))) /*@ @@ -519,12 +525,15 @@ module X86-ABSTRACT-SEMANTICS #ifMInt absInt(svalueMInt(Length)) >Int 16 #then mi(8, 16) #else mi(8, absInt(svalueMInt(Length))) #fi requires eqMInt(extractMInt(Imm8, 7, 8), mi(1, 0)) // Interpret as 16 bytes + syntax Int ::= KItemToInt(KItem) [function] + rule KItemToInt(I:Int) => I + /*@ findLimitIndexI */ rule findLimitIndexI(Value:MInt, Imm8:MInt) => findLimitIndexIHelper(Value, - {#ifInt eqMInt(extractMInt(Imm8, 7, 8), mi(1, 1)) #then 16 #else 8 #fi}:>Int, - {#ifInt eqMInt(extractMInt(Imm8, 7, 8), mi(1, 1)) #then 8 #else 16 #fi}:>Int, + KItemToInt(#ifInt eqMInt(extractMInt(Imm8, 7, 8), mi(1, 1)) #then 16 #else 8 #fi), + KItemToInt(#ifInt eqMInt(extractMInt(Imm8, 7, 8), mi(1, 1)) #then 8 #else 16 #fi}), 0) rule findLimitIndexIHelper(Value:MInt, BitLength:Int, NumElems:Int, Count:Int) => mi(8, Count) @@ -583,8 +592,8 @@ module X86-ABSTRACT-SEMANTICS rule compareEqual(Count2:Int, Count1:Int, Value2:MInt, Value1:MInt, Limit2:MInt, Limit1:MInt, NumElems:Int, SOrU:MInt) => compareEqualSignedOrUnsigned( - extractMask(Value2, {#ifInt NumElems ==Int 8 #then 16 #else 8 #fi}:>Int, Count2 *Int {#if NumElems ==Int 8 #then 16 #else 8 #fi}:>Int), - extractMask(Value1, {#ifInt NumElems ==Int 8 #then 16 #else 8 #fi}:>Int, Count1 *Int {#if NumElems ==Int 8 #then 16 #else 8 #fi}:>Int), + extractMask(Value2, KItemToInt(#ifInt NumElems ==Int 8 #then 16 #else 8 #fi}:>Int, Count2 *Int {#if NumElems ==Int 8 #then 16 #else 8 #fi)), + extractMask(Value1, KItemToInt(#ifInt NumElems ==Int 8 #then 16 #else 8 #fi}:>Int, Count1 *Int {#if NumElems ==Int 8 #then 16 #else 8 #fi)), SOrU ) requires Count1 compareEqualSignedOrUnsigned( - extractMask(Value2, {#ifInt NumElems ==Int 8 #then 16 #else 8 #fi}:>Int, Index *Int {#if NumElems ==Int 8 #then 16 #else 8 #fi}:>Int), - extractMask(Value1, {#ifInt NumElems ==Int 8 #then 16 #else 8 #fi}:>Int, Index *Int {#if NumElems ==Int 8 #then 16 #else 8 #fi}:>Int), + extractMask(Value2, KItemToInt(#ifInt NumElems ==Int 8 #then 16 #else 8 #fi}:>Int, Index *Int {#if NumElems ==Int 8 #then 16 #else 8 #fi)), + extractMask(Value1, KItemToINt(#ifInt NumElems ==Int 8 #then 16 #else 8 #fi}:>Int, Index *Int {#if NumElems ==Int 8 #then 16 #else 8 #fi)), SOrU ) requires // If both of the data are valid @@ -689,13 +698,13 @@ module X86-ABSTRACT-SEMANTICS rule compareRange(Count2:Int, Count1:Int, Value2:MInt, Value1:MInt, Limit2:MInt, Limit1:MInt, NumElems:Int, SOrU:MInt) => andMInt( compareGESignedOrUnsigned( - extractMask(Value2, {#ifInt NumElems ==Int 8 #then 16 #else 8 #fi}:>Int, Count2 *Int {#if NumElems ==Int 8 #then 16 #else 8 #fi}:>Int), - extractMask(Value1, {#ifInt NumElems ==Int 8 #then 16 #else 8 #fi}:>Int, Count1 *Int {#if NumElems ==Int 8 #then 16 #else 8 #fi}:>Int), + extractMask(Value2, KItemToInt(#ifInt NumElems ==Int 8 #then 16 #else 8 #fi}:>Int, Count2 *Int {#if NumElems ==Int 8 #then 16 #else 8 #fi)), + extractMask(Value1, KItemToInt(#ifInt NumElems ==Int 8 #then 16 #else 8 #fi}:>Int, Count1 *Int {#if NumElems ==Int 8 #then 16 #else 8 #fi)), SOrU ), compareLESignedOrUnsigned( - extractMask(Value2, {#ifInt NumElems ==Int 8 #then 16 #else 8 #fi}:>Int, Count2 *Int {#if NumElems ==Int 8 #then 16 #else 8 #fi}:>Int), - extractMask(Value1, {#ifInt NumElems ==Int 8 #then 16 #else 8 #fi}:>Int, Count1 *Int {#if NumElems ==Int 8 #then 16 #else 8 #fi}:>Int), + extractMask(Value2, KItemToInt(#ifInt NumElems ==Int 8 #then 16 #else 8 #fi}:>Int, Count2 *Int {#if NumElems ==Int 8 #then 16 #else 8 #fi)), + extractMask(Value1, KItemToInt(#ifInt NumElems ==Int 8 #then 16 #else 8 #fi}:>Int, Count1 *Int {#if NumElems ==Int 8 #then 16 #else 8 #fi)), SOrU )) @@ -749,8 +758,8 @@ module X86-ABSTRACT-SEMANTICS rule compareEqualOrdered(Count2:Int, Count1:Int, Value2:MInt, Value1:MInt, Limit2:MInt, Limit1:MInt, NumElems:Int, SOrU:MInt) => compareEqualSignedOrUnsigned( - extractMask(Value2, {#ifInt NumElems ==Int 8 #then 16 #else 8 #fi}:>Int, Count2 *Int {#if NumElems ==Int 8 #then 16 #else 8 #fi}:>Int), - extractMask(Value1, {#ifInt NumElems ==Int 8 #then 16 #else 8 #fi}:>Int, Count1 *Int {#if NumElems ==Int 8 #then 16 #else 8 #fi}:>Int), + extractMask(Value2, KItemToInt(#ifInt NumElems ==Int 8 #then 16 #else 8 #fi}:>Int, Count2 *Int {#if NumElems ==Int 8 #then 16 #else 8 #fi})), + extractMask(Value1, KItemToInt(#ifInt NumElems ==Int 8 #then 16 #else 8 #fi}:>Int, Count1 *Int {#if NumElems ==Int 8 #then 16 #else 8 #fi})), SOrU ) @@ -816,9 +825,9 @@ module X86-ABSTRACT-SEMANTICS rule expandMaskHelper(IntRes2:MInt, NumElems:Int, Count:Int) => #ifMInt eqMInt(extractMask(IntRes2, 1, Count), mi(1, 0)) #then - {#ifMInt NumElems ==Int 8 #then mi(16, 0) #else mi(8, 0) #fi}:>MInt + KItemToMInt(#ifMInt NumElems ==Int 8 #then mi(16, 0) #else mi(8, 0) #fi) #else - {#ifMInt NumElems ==Int 8 #then mi(16, -1) #else mi(8, -1) #fi}:>MInt + KItemToMInt(#ifMInt NumElems ==Int 8 #then mi(16, -1) #else mi(8, -1) #fi) #fi requires Count ==Int (NumElems -Int 1) @@ -828,9 +837,9 @@ module X86-ABSTRACT-SEMANTICS expandMaskHelper(IntRes2, NumElems, Count +Int 1), #ifMInt eqMInt(extractMask(IntRes2, 1, Count), mi(1, 0)) #then - {#ifMInt NumElems ==Int 8 #then mi(16, 0) #else mi(8, 0) #fi}:>MInt + KItemToMInt(#ifMInt NumElems ==Int 8 #then mi(16, 0) #else mi(8, 0) #fi) #else - {#ifMInt NumElems ==Int 8 #then mi(16, -1) #else mi(8, -1) #fi}:>MInt + KItemToMInt(#ifMInt NumElems ==Int 8 #then mi(16, -1) #else mi(8, -1) #fi) #fi ) requires Count =/=Int (NumElems -Int 1) diff --git a/semantics/x86-syntax.k b/semantics/x86-syntax.k index f8ed51a99..3d7d6ec93 100644 --- a/semantics/x86-syntax.k +++ b/semantics/x86-syntax.k @@ -133,6 +133,7 @@ module X86-SYNTAX | "(" R64 "," R64 ")" | Offset "(" R64 "," R64 "," Scale ")" | Offset "(" R64 "," R64 ")" + | Address(Int) //------------------------------------ //| Offset /* This solution would cause about a million problems with Mem matching incorrectly. I'll find a better way later (maybe wrap all Mems with some label). From 4eaeb6a9b7a331af3637722ffedd60a93f27cf55 Mon Sep 17 00:00:00 2001 From: andrew_miranti Date: Tue, 12 Mar 2019 11:31:40 -0500 Subject: [PATCH 13/15] Update to how relative jumps work, now consistent with disassembly format --- semantics/a.out | Bin 912816 -> 984800 bytes semantics/memoryInstructions/bsfl_r32_m32.k | 2 +- .../memoryInstructions/rep_movsq_m64_m64.k | 23 ++++++++++++ semantics/registerInstructions/bsfl_r32_r32.k | 2 +- semantics/registerInstructions/nop.k | 8 ++++ semantics/registerInstructions/sall_r32_cl.k | 2 +- semantics/registerInstructions/shrl_r32_cl.k | 2 +- semantics/systemInstructions/callq_m64.k | 6 +-- semantics/systemInstructions/callq_r64.k | 2 +- semantics/systemInstructions/callq_rel32.k | 12 +++--- semantics/systemInstructions/ja_rel32.k | 13 +++---- semantics/systemInstructions/ja_rel8.k | 25 ------------- semantics/systemInstructions/jae_rel32.k | 17 +++------ semantics/systemInstructions/jae_rel8.k | 22 ----------- semantics/systemInstructions/jb_rel32.k | 17 +++------ semantics/systemInstructions/jb_rel8.k | 22 ----------- semantics/systemInstructions/jbe_rel32.k | 19 +++------- semantics/systemInstructions/jbe_rel8.k | 24 ------------ semantics/systemInstructions/jc_rel32.k | 17 +++------ semantics/systemInstructions/jc_rel8.k | 22 ----------- semantics/systemInstructions/je_rel32.k | 20 +++------- semantics/systemInstructions/je_rel8.k | 22 ----------- semantics/systemInstructions/jecxz_rel8.k | 19 +++------- semantics/systemInstructions/jg_rel32.k | 23 +++--------- semantics/systemInstructions/jg_rel8.k | 24 ------------ semantics/systemInstructions/jge_rel32.k | 19 +++------- semantics/systemInstructions/jge_rel8.k | 20 ---------- semantics/systemInstructions/jl_rel32.k | 19 +++------- semantics/systemInstructions/jl_rel8.k | 20 ---------- semantics/systemInstructions/jle_rel32.k | 23 +++--------- semantics/systemInstructions/jle_rel8.k | 24 ------------ semantics/systemInstructions/jmp_rel32.k | 9 +---- semantics/systemInstructions/jmp_rel8.k | 14 ------- semantics/systemInstructions/jna_rel32.k | 19 +++------- semantics/systemInstructions/jna_rel8.k | 24 ------------ semantics/systemInstructions/jnae_rel32.k | 19 +++------- semantics/systemInstructions/jnae_rel8.k | 22 ----------- semantics/systemInstructions/jnb_rel32.k | 19 +++------- semantics/systemInstructions/jnb_rel8.k | 22 ----------- semantics/systemInstructions/jnbe_rel32.k | 22 +++-------- semantics/systemInstructions/jnbe_rel8.k | 25 ------------- semantics/systemInstructions/jnc_rel32.k | 19 +++------- semantics/systemInstructions/jnc_rel8.k | 22 ----------- semantics/systemInstructions/jne_rel32.k | 19 +++------- semantics/systemInstructions/jne_rel8.k | 22 ----------- semantics/systemInstructions/jng_rel32.k | 19 +++------- semantics/systemInstructions/jng_rel8.k | 22 ----------- semantics/systemInstructions/jnge_rel32.k | 19 +++------- semantics/systemInstructions/jnge_rel8.k | 22 ----------- semantics/systemInstructions/jnl_rel32.k | 19 +++------- semantics/systemInstructions/jnl_rel8.k | 22 ----------- semantics/systemInstructions/jnle_rel32.k | 19 +++------- semantics/systemInstructions/jnle_rel8.k | 22 ----------- semantics/systemInstructions/jno_rel32.k | 19 +++------- semantics/systemInstructions/jno_rel8.k | 22 ----------- semantics/systemInstructions/jnp_rel32.k | 19 +++------- semantics/systemInstructions/jnp_rel8.k | 22 ----------- semantics/systemInstructions/jns_rel32.k | 19 +++------- semantics/systemInstructions/jns_rel8.k | 22 ----------- semantics/systemInstructions/jnz_rel32.k | 19 +++------- semantics/systemInstructions/jnz_rel8.k | 22 ----------- semantics/systemInstructions/jo_rel32.k | 19 +++------- semantics/systemInstructions/jo_rel8.k | 22 ----------- semantics/systemInstructions/jp_rel32.k | 19 +++------- semantics/systemInstructions/jp_rel8.k | 22 ----------- semantics/systemInstructions/jpe_rel32.k | 19 +++------- semantics/systemInstructions/jpe_rel8.k | 22 ----------- semantics/systemInstructions/jpo_rel32.k | 19 +++------- semantics/systemInstructions/jpo_rel8.k | 22 ----------- semantics/systemInstructions/jrcxz_rel8.k | 19 +++------- semantics/systemInstructions/js_rel32.k | 19 +++------- semantics/systemInstructions/js_rel8.k | 22 ----------- semantics/systemInstructions/jz_rel32.k | 19 +++------- semantics/systemInstructions/loop_rel8.k | 31 ++++------------ semantics/systemInstructions/loope_rel8.k | 33 ++++------------- semantics/systemInstructions/loopne_rel8.k | 33 ++++------------- semantics/systemInstructions/loopnz_rel8.k | 35 ++++-------------- semantics/systemInstructions/loopz_rel8.k | 33 ++++------------- semantics/test.c | 34 ++++++----------- semantics/x86-abstract-semantics.k | 31 +++++++++------- semantics/x86-configuration.k | 1 + semantics/x86-fetch-execute.k | 9 ++++- semantics/x86-syntax.k | 4 +- 83 files changed, 307 insertions(+), 1275 deletions(-) create mode 100644 semantics/memoryInstructions/rep_movsq_m64_m64.k delete mode 100644 semantics/systemInstructions/ja_rel8.k delete mode 100644 semantics/systemInstructions/jae_rel8.k delete mode 100644 semantics/systemInstructions/jb_rel8.k delete mode 100644 semantics/systemInstructions/jbe_rel8.k delete mode 100644 semantics/systemInstructions/jc_rel8.k delete mode 100644 semantics/systemInstructions/je_rel8.k delete mode 100644 semantics/systemInstructions/jg_rel8.k delete mode 100644 semantics/systemInstructions/jge_rel8.k delete mode 100644 semantics/systemInstructions/jl_rel8.k delete mode 100644 semantics/systemInstructions/jle_rel8.k delete mode 100644 semantics/systemInstructions/jmp_rel8.k delete mode 100644 semantics/systemInstructions/jna_rel8.k delete mode 100644 semantics/systemInstructions/jnae_rel8.k delete mode 100644 semantics/systemInstructions/jnb_rel8.k delete mode 100644 semantics/systemInstructions/jnbe_rel8.k delete mode 100644 semantics/systemInstructions/jnc_rel8.k delete mode 100644 semantics/systemInstructions/jne_rel8.k delete mode 100644 semantics/systemInstructions/jng_rel8.k delete mode 100644 semantics/systemInstructions/jnge_rel8.k delete mode 100644 semantics/systemInstructions/jnl_rel8.k delete mode 100644 semantics/systemInstructions/jnle_rel8.k delete mode 100644 semantics/systemInstructions/jno_rel8.k delete mode 100644 semantics/systemInstructions/jnp_rel8.k delete mode 100644 semantics/systemInstructions/jns_rel8.k delete mode 100644 semantics/systemInstructions/jnz_rel8.k delete mode 100644 semantics/systemInstructions/jo_rel8.k delete mode 100644 semantics/systemInstructions/jp_rel8.k delete mode 100644 semantics/systemInstructions/jpe_rel8.k delete mode 100644 semantics/systemInstructions/jpo_rel8.k delete mode 100644 semantics/systemInstructions/js_rel8.k diff --git a/semantics/a.out b/semantics/a.out index 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RSMap:Map => updateMap(RSMap, - convToRegKeys(R2) |-> mi(32, scanForward(Mem32, 31, 32)) + convToRegKeys(R2) |-> mi(64, scanForward(Mem32, 31, 32)) "ZF" |-> mi(1,0) "SF" |-> (undefMInt) "CF" |-> (undefMInt) diff --git a/semantics/memoryInstructions/rep_movsq_m64_m64.k b/semantics/memoryInstructions/rep_movsq_m64_m64.k new file mode 100644 index 000000000..23c5c3801 --- /dev/null +++ b/semantics/memoryInstructions/rep_movsq_m64_m64.k @@ -0,0 +1,23 @@ +requires "x86-configuration.k" + +module MOVSQ + imports X86-CONFIGURATION + + rule execinstr (rep movsq M1:Mem, M2:Mem, .Operands) => . ... + RSMap + requires eqMInt(getRegisterValue(%rcx, RSMap), mi(64, 0)) + + rule + execinstr (rep movsq M1:Mem, M2:Mem, .Operands) => + loadFromMemory( getRegisterValue(%rsi, RSMap), 64) ~> + execinstr (movsq .Operands) ~> + setRegisterValue(subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), %rcx) ~> + execinstr(rep movsq M1, M2, .Operands) + ... + RSMap:Map + requires notBool eqMInt(getRegisterValue(%rcx, RSMap), mi(64, 0)) + + + + + endmodule diff --git a/semantics/registerInstructions/bsfl_r32_r32.k b/semantics/registerInstructions/bsfl_r32_r32.k index 0579f6118..5e577775e 100644 --- a/semantics/registerInstructions/bsfl_r32_r32.k +++ b/semantics/registerInstructions/bsfl_r32_r32.k @@ -26,7 +26,7 @@ RSMap:Map => updateMap(RSMap, ... RSMap:Map => updateMap(RSMap, - convToRegKeys(R2) |-> mi(32, scanForward(getRegisterValue(R1, RSMap), 31, 32)) + convToRegKeys(R2) |-> mi(64, scanForward(getRegisterValue(R1, RSMap), 31, 32)) "ZF" |-> mi(1,0) "SF" |-> (undefMInt) "CF" |-> (undefMInt) diff --git a/semantics/registerInstructions/nop.k b/semantics/registerInstructions/nop.k index cbd764db0..650f2dfd2 100644 --- a/semantics/registerInstructions/nop.k +++ b/semantics/registerInstructions/nop.k @@ -7,6 +7,14 @@ module NOP rule execinstr (nop .Operands) => . ... + + //TODO: Temporary + rule + execinstr (nopw Operands) => . + ... + rule + execinstr (nopl Operands) => . + ... endmodule module NOP-SEMANTICS diff --git a/semantics/registerInstructions/sall_r32_cl.k b/semantics/registerInstructions/sall_r32_cl.k index 8faacfc37..c8fc5085f 100644 --- a/semantics/registerInstructions/sall_r32_cl.k +++ b/semantics/registerInstructions/sall_r32_cl.k @@ -15,7 +15,7 @@ convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( shiftLeftMInt( co "PF" |-> (#ifMInt (((notBool eqMInt( andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31))))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31))))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31))))), 25, 26), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31)), mi(8, 0))))) #then undefMInt #else getFlag("AF", RSMap) #fi) "ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31))))), 1, 33), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) diff --git a/semantics/registerInstructions/shrl_r32_cl.k b/semantics/registerInstructions/shrl_r32_cl.k index ea8b1d652..6bfb4c755 100644 --- a/semantics/registerInstructions/shrl_r32_cl.k +++ b/semantics/registerInstructions/shrl_r32_cl.k @@ -15,7 +15,7 @@ convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( lshrMInt( concate "PF" |-> (#ifMInt (((notBool eqMInt( andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31))))), 31, 32), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31))))), 25, 26), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31))))), 24, 25), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (notBool eqMInt( andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31)), mi(8, 0))) #then undefMInt #else getFlag("AF", RSMap) #fi) "ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31))))), 0, 32), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( extractMInt( getParentValue(%rcx, RSMap), 56, 64), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) diff --git a/semantics/systemInstructions/callq_m64.k b/semantics/systemInstructions/callq_m64.k index 6ba6d46b3..d26d755cf 100644 --- a/semantics/systemInstructions/callq_m64.k +++ b/semantics/systemInstructions/callq_m64.k @@ -4,15 +4,15 @@ requires "x86-configuration.k" module CALLQ-M64 imports X86-CONFIGURATION - context execinstr(call:Opcode (HOLE:Mem, .Operands):Operands) [result(MemOffset)] + context execinstr(callq:Opcode (HOLE:Mem, .Operands):Operands) [result(MemOffset)] rule - execinstr (call memOffset(MemOff:MInt):MemOffset, .Operands) => + execinstr (callq memOffset(MemOff:MInt):MemOffset, .Operands) => loadFromMemory(MemOff, 64) ~> execinstr (call memOffset ( MemOff ), .Operands) ... rule - memLoadValue(MemVal:MInt):MemLoadValue ~> execinstr (call memOffset(MemOff:MInt):MemOffset, .Operands) => + memLoadValue(MemVal:MInt):MemLoadValue ~> execinstr (callq memOffset(MemOff:MInt):MemOffset, .Operands) => storeToMemory({RSMap["RIP"]}:>MInt, subMInt(getRegisterValue(%rsp, RSMap), mi(64, 8)), 64) ~> decRSPInBytes(8) ... diff --git a/semantics/systemInstructions/callq_r64.k b/semantics/systemInstructions/callq_r64.k index 25096ded9..2a92c7c1d 100644 --- a/semantics/systemInstructions/callq_r64.k +++ b/semantics/systemInstructions/callq_r64.k @@ -6,7 +6,7 @@ module CALLQ-R64 imports X86-CONFIGURATION rule - execinstr (call R1:R64, .Operands) => + execinstr (callq R1:R64, .Operands) => storeToMemory({RSMap["RIP"]}:>MInt, subMInt(getRegisterValue(%rsp, RSMap), mi(64, 8)), 64) ~> decRSPInBytes(8) ... diff --git a/semantics/systemInstructions/callq_rel32.k b/semantics/systemInstructions/callq_rel32.k index abd054b19..44b406e69 100644 --- a/semantics/systemInstructions/callq_rel32.k +++ b/semantics/systemInstructions/callq_rel32.k @@ -13,18 +13,16 @@ module CALLQ-REL32 rule - execinstr (callq Imm32:MInt, .Operands) => + execinstr (callq Imm64:MInt, .Operands) => storeToMemory({RSMap["RIP"]}:>MInt, subMInt(getRegisterValue(%rsp, RSMap), mi(64, 8)), 64) ~> decRSPInBytes(8) ... - RSMap => updateMap(RSMap, ("RIP" |->addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)) )) + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) SymMap - requires notBool HasBuiltinAtAddress(SymMap, addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64))) - andBool bitwidthMInt(Imm32) ==Int 32 + requires notBool HasBuiltinAtAddress(SymMap, Imm64) - rule execinstr (callq Imm32:MInt, .Operands) => execinstr(call GetBuiltinFromAddress(SymMap, addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) ... + rule execinstr (callq Imm64:MInt, .Operands) => execinstr(call GetBuiltinFromAddress(SymMap, Imm64)) ... RSMap SymMap - requires HasBuiltinAtAddress(SymMap, addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64))) - andBool bitwidthMInt(Imm32) ==Int 32 + requires HasBuiltinAtAddress(SymMap, Imm64) endmodule diff --git a/semantics/systemInstructions/ja_rel32.k b/semantics/systemInstructions/ja_rel32.k index 987f2fc69..7d827abcf 100644 --- a/semantics/systemInstructions/ja_rel32.k +++ b/semantics/systemInstructions/ja_rel32.k @@ -4,14 +4,11 @@ module JA-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule execinstr (ja Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) + rule execinstr (ja Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires (eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) - requires bitwidthMInt(Imm32) ==Int 32 andBool - (eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) - - rule execinstr (ja Imm32:MInt, .Operands) => . ... + rule execinstr (ja _:MInt, .Operands) => . ... RSMap - requires bitwidthMInt(Imm32) ==Int 32 andBool - (eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) orBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1))) + requires (eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) orBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1))) endmodule diff --git a/semantics/systemInstructions/ja_rel8.k b/semantics/systemInstructions/ja_rel8.k deleted file mode 100644 index 96bc20187..000000000 --- a/semantics/systemInstructions/ja_rel8.k +++ /dev/null @@ -1,25 +0,0 @@ -requires "x86-configuration.k" - - -module JA-REL8 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (ja Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> - addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - (eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) - andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) - - rule - execinstr (ja Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - (eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) - orBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1))) -endmodule diff --git a/semantics/systemInstructions/jae_rel32.k b/semantics/systemInstructions/jae_rel32.k index 697ee5c2b..89c6fe05c 100644 --- a/semantics/systemInstructions/jae_rel32.k +++ b/semantics/systemInstructions/jae_rel32.k @@ -5,18 +5,11 @@ module JAE-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (jae Imm32:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - - requires bitwidthMInt(Imm32) ==Int 32 andBool - eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) + rule execinstr (jae Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) - rule - execinstr (jae Imm32:MInt, .Operands) => . - ... + rule execinstr (jae Imm32:MInt, .Operands) => . ... RSMap:Map - requires bitwidthMInt(Imm32) ==Int 32 andBool - eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jae_rel8.k b/semantics/systemInstructions/jae_rel8.k deleted file mode 100644 index 059459b19..000000000 --- a/semantics/systemInstructions/jae_rel8.k +++ /dev/null @@ -1,22 +0,0 @@ -requires "x86-configuration.k" - - -module JAE-REL8 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jae Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) - - rule - execinstr (jae Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) -endmodule diff --git a/semantics/systemInstructions/jb_rel32.k b/semantics/systemInstructions/jb_rel32.k index d951f3789..7157f91fb 100644 --- a/semantics/systemInstructions/jb_rel32.k +++ b/semantics/systemInstructions/jb_rel32.k @@ -5,18 +5,11 @@ module JB-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (jb Imm32:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - - requires bitwidthMInt(Imm32) ==Int 32 andBool - eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + rule execinstr (jb Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) - rule - execinstr (jb Imm32:MInt, .Operands) => . - ... + rule execinstr (jb _:MInt, .Operands) => . ... RSMap:Map - requires bitwidthMInt(Imm32) ==Int 32 andBool - eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) + requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jb_rel8.k b/semantics/systemInstructions/jb_rel8.k deleted file mode 100644 index dfb9fd6fe..000000000 --- a/semantics/systemInstructions/jb_rel8.k +++ /dev/null @@ -1,22 +0,0 @@ -requires "x86-configuration.k" - - -module JB-REL8 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jb Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) - - rule - execinstr (jb Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) -endmodule diff --git a/semantics/systemInstructions/jbe_rel32.k b/semantics/systemInstructions/jbe_rel32.k index 3f64d6359..36583767b 100644 --- a/semantics/systemInstructions/jbe_rel32.k +++ b/semantics/systemInstructions/jbe_rel32.k @@ -5,20 +5,11 @@ module JBE-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (jbe Imm32:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - - requires bitwidthMInt(Imm32) ==Int 32 andBool - (eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) - orBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1))) + rule execinstr (jbe Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires (eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) orBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1))) - rule - execinstr (jbe Imm32:MInt, .Operands) => . - ... + rule execinstr (jbe Imm32:MInt, .Operands) => . ... RSMap:Map - requires bitwidthMInt(Imm32) ==Int 32 andBool - (eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) - andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) + requires (eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) endmodule diff --git a/semantics/systemInstructions/jbe_rel8.k b/semantics/systemInstructions/jbe_rel8.k deleted file mode 100644 index b0c3bb039..000000000 --- a/semantics/systemInstructions/jbe_rel8.k +++ /dev/null @@ -1,24 +0,0 @@ -requires "x86-configuration.k" - - -module JBE-REL8 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jbe Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - (eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) - orBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1))) - - rule - execinstr (jbe Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - (eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) - andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) -endmodule diff --git a/semantics/systemInstructions/jc_rel32.k b/semantics/systemInstructions/jc_rel32.k index d75d1231b..f4f165f51 100644 --- a/semantics/systemInstructions/jc_rel32.k +++ b/semantics/systemInstructions/jc_rel32.k @@ -5,18 +5,11 @@ module JC-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (jc Imm32:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - - requires bitwidthMInt(Imm32) ==Int 32 andBool - eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + rule execinstr (jc Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) - rule - execinstr (jc Imm32:MInt, .Operands) => . - ... + rule execinstr (jc _:MInt, .Operands) => . ... RSMap:Map - requires bitwidthMInt(Imm32) ==Int 32 andBool - notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jc_rel8.k b/semantics/systemInstructions/jc_rel8.k deleted file mode 100644 index 07e2e66a1..000000000 --- a/semantics/systemInstructions/jc_rel8.k +++ /dev/null @@ -1,22 +0,0 @@ -requires "x86-configuration.k" - - -module JC-REL8 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jc Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) - - rule - execinstr (jc Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) -endmodule diff --git a/semantics/systemInstructions/je_rel32.k b/semantics/systemInstructions/je_rel32.k index 3071bf335..17a5d4795 100644 --- a/semantics/systemInstructions/je_rel32.k +++ b/semantics/systemInstructions/je_rel32.k @@ -1,22 +1,14 @@ requires "x86-configuration.k" - module JE-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (je Imm32:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - - requires bitwidthMInt(Imm32) ==Int 32 andBool - eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + rule execinstr (je Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) - rule - execinstr (je Imm32:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm32) ==Int 32 andBool - notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + rule execinstr (je _:MInt, .Operands) => . ... + RSMap + requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/je_rel8.k b/semantics/systemInstructions/je_rel8.k deleted file mode 100644 index 204e8355c..000000000 --- a/semantics/systemInstructions/je_rel8.k +++ /dev/null @@ -1,22 +0,0 @@ -requires "x86-configuration.k" - - -module JE-REL8 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (je Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) - - rule - execinstr (je Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) -endmodule diff --git a/semantics/systemInstructions/jecxz_rel8.k b/semantics/systemInstructions/jecxz_rel8.k index 60e07b1de..9fc175d08 100644 --- a/semantics/systemInstructions/jecxz_rel8.k +++ b/semantics/systemInstructions/jecxz_rel8.k @@ -5,18 +5,11 @@ module JECXZ-REL8 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (jecxz Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt(getRegisterValue(%ecx, RSMap), mi(32, 0)) + rule execinstr (jecxz Imm8:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires eqMInt(getRegisterValue(%ecx, RSMap), mi(32, 0)) - rule - execinstr (jecxz Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - notBool eqMInt(getRegisterValue(%ecx, RSMap), mi(32, 0)) + rule execinstr (jecxz _:MInt, .Operands) => . ... + RSMap + requires notBool eqMInt(getRegisterValue(%ecx, RSMap), mi(32, 0)) endmodule diff --git a/semantics/systemInstructions/jg_rel32.k b/semantics/systemInstructions/jg_rel32.k index 295492de4..bd80b1778 100644 --- a/semantics/systemInstructions/jg_rel32.k +++ b/semantics/systemInstructions/jg_rel32.k @@ -3,22 +3,11 @@ module JG-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (jg Imm32:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - - requires bitwidthMInt(Imm32) ==Int 32 andBool - (eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) - andBool - eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) + rule execinstr (jg Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires (eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) - rule - execinstr (jg Imm32:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm32) ==Int 32 andBool - (notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) - orBool - notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) + rule execinstr (jg _:MInt, .Operands) => . ... + RSMap + requires (notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) orBool notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) endmodule diff --git a/semantics/systemInstructions/jg_rel8.k b/semantics/systemInstructions/jg_rel8.k deleted file mode 100644 index 49e48a412..000000000 --- a/semantics/systemInstructions/jg_rel8.k +++ /dev/null @@ -1,24 +0,0 @@ -requires "x86-configuration.k" -module JG-REL8 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jg Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - (eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) - andBool - eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) - - rule - execinstr (jg Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - (notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) - orBool - notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) -endmodule diff --git a/semantics/systemInstructions/jge_rel32.k b/semantics/systemInstructions/jge_rel32.k index a5e4ba1bb..1c34105ae 100644 --- a/semantics/systemInstructions/jge_rel32.k +++ b/semantics/systemInstructions/jge_rel32.k @@ -3,18 +3,11 @@ module JGE-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (jge Imm32:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - - requires bitwidthMInt(Imm32) ==Int 32 andBool - eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + rule execinstr (jge Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) - rule - execinstr (jge Imm32:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm32) ==Int 32 andBool - notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + rule execinstr (jge _:MInt, .Operands) => . ... + RSMap + requires notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) endmodule diff --git a/semantics/systemInstructions/jge_rel8.k b/semantics/systemInstructions/jge_rel8.k deleted file mode 100644 index 751e1bfd5..000000000 --- a/semantics/systemInstructions/jge_rel8.k +++ /dev/null @@ -1,20 +0,0 @@ -requires "x86-configuration.k" -module JGE-REL8 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jge Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) - - rule - execinstr (jge Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) -endmodule diff --git a/semantics/systemInstructions/jl_rel32.k b/semantics/systemInstructions/jl_rel32.k index 407ce8bc6..5c5ee6691 100644 --- a/semantics/systemInstructions/jl_rel32.k +++ b/semantics/systemInstructions/jl_rel32.k @@ -3,18 +3,11 @@ module JL-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (jl Imm32:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - - requires bitwidthMInt(Imm32) ==Int 32 andBool - notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + rule execinstr (jl Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) - rule - execinstr (jl Imm32:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm32) ==Int 32 andBool - eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + rule execinstr (jl _:MInt, .Operands) => . ... + RSMap + requires eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) endmodule diff --git a/semantics/systemInstructions/jl_rel8.k b/semantics/systemInstructions/jl_rel8.k deleted file mode 100644 index 0a1ab84b9..000000000 --- a/semantics/systemInstructions/jl_rel8.k +++ /dev/null @@ -1,20 +0,0 @@ -requires "x86-configuration.k" -module JL-REL8 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jl Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) - - rule - execinstr (jl Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) -endmodule diff --git a/semantics/systemInstructions/jle_rel32.k b/semantics/systemInstructions/jle_rel32.k index c2f827b94..7f1d406c1 100644 --- a/semantics/systemInstructions/jle_rel32.k +++ b/semantics/systemInstructions/jle_rel32.k @@ -3,22 +3,11 @@ module JLE-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (jle Imm32:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - - requires bitwidthMInt(Imm32) ==Int 32 andBool - (eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) - orBool - (notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt))) + rule execinstr (jle Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires (eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) orBool (notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt))) - rule - execinstr (jle Imm32:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm32) ==Int 32 andBool - (notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) - andBool - eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) + rule execinstr (jle _:MInt, .Operands) => . ... + RSMap + requires (notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) andBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) endmodule diff --git a/semantics/systemInstructions/jle_rel8.k b/semantics/systemInstructions/jle_rel8.k deleted file mode 100644 index f818684b9..000000000 --- a/semantics/systemInstructions/jle_rel8.k +++ /dev/null @@ -1,24 +0,0 @@ -requires "x86-configuration.k" -module JLE-REL8 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jle Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - (eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) - orBool - (notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt))) - - rule - execinstr (jle Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - (notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) - andBool - eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) -endmodule diff --git a/semantics/systemInstructions/jmp_rel32.k b/semantics/systemInstructions/jmp_rel32.k index 20f25aa3c..fa4fa185b 100644 --- a/semantics/systemInstructions/jmp_rel32.k +++ b/semantics/systemInstructions/jmp_rel32.k @@ -4,11 +4,6 @@ requires "x86-configuration.k" module JMPQ-REL32 imports X86-CONFIGURATION - rule - execinstr (jmp Imm32:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - - requires bitwidthMInt(Imm32) ==Int 32 - + rule execinstr (jmp Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) endmodule diff --git a/semantics/systemInstructions/jmp_rel8.k b/semantics/systemInstructions/jmp_rel8.k deleted file mode 100644 index 3c940e93e..000000000 --- a/semantics/systemInstructions/jmp_rel8.k +++ /dev/null @@ -1,14 +0,0 @@ -requires "x86-configuration.k" - - -module JMPQ-REL8 - imports X86-CONFIGURATION - - rule - execinstr (jmp Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 - -endmodule diff --git a/semantics/systemInstructions/jna_rel32.k b/semantics/systemInstructions/jna_rel32.k index a2740b9e3..5c362222e 100644 --- a/semantics/systemInstructions/jna_rel32.k +++ b/semantics/systemInstructions/jna_rel32.k @@ -5,20 +5,11 @@ module JNA-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (jna Imm32:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> - addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, - 64)))) - - requires bitwidthMInt(Imm32) ==Int 32 andBool - (eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) orBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1))) + rule execinstr (jna Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires (eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) orBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1))) - rule - execinstr (jna Imm32:MInt, .Operands) => . - ... + rule execinstr (jna _:MInt, .Operands) => . ... RSMap:Map - requires bitwidthMInt(Imm32) ==Int 32 andBool - (notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) andBool notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1))) + requires (notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) andBool notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1))) endmodule diff --git a/semantics/systemInstructions/jna_rel8.k b/semantics/systemInstructions/jna_rel8.k deleted file mode 100644 index ae854f827..000000000 --- a/semantics/systemInstructions/jna_rel8.k +++ /dev/null @@ -1,24 +0,0 @@ -requires "x86-configuration.k" - - -module JNA-REL8 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jna Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> - addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, - 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - (eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) orBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1))) - - rule - execinstr (jna Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - (notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) andBool notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1))) -endmodule diff --git a/semantics/systemInstructions/jnae_rel32.k b/semantics/systemInstructions/jnae_rel32.k index ac18612a0..eaf7decd5 100644 --- a/semantics/systemInstructions/jnae_rel32.k +++ b/semantics/systemInstructions/jnae_rel32.k @@ -5,18 +5,11 @@ module JNAE-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (jnae Imm32:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - - requires bitwidthMInt(Imm32) ==Int 32 andBool - eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + rule execinstr (jnae Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) - rule - execinstr (jnae Imm32:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm32) ==Int 32 andBool - notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + rule execinstr (jnae _:MInt, .Operands) => . ... + RSMap + requires notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jnae_rel8.k b/semantics/systemInstructions/jnae_rel8.k deleted file mode 100644 index 9f5afa5dc..000000000 --- a/semantics/systemInstructions/jnae_rel8.k +++ /dev/null @@ -1,22 +0,0 @@ -requires "x86-configuration.k" - - -module JNAE-REL8 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jnae Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) - - rule - execinstr (jnae Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) -endmodule diff --git a/semantics/systemInstructions/jnb_rel32.k b/semantics/systemInstructions/jnb_rel32.k index 23760c8a5..2cc8d92d3 100644 --- a/semantics/systemInstructions/jnb_rel32.k +++ b/semantics/systemInstructions/jnb_rel32.k @@ -5,18 +5,11 @@ module JNB-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (jnb Imm32:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - - requires bitwidthMInt(Imm32) ==Int 32 andBool - eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) + rule execinstr (jnb Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) - rule - execinstr (jnb Imm32:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm32) ==Int 32 andBool - eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + rule execinstr (jnb _:MInt, .Operands) => . ... + RSMap + requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jnb_rel8.k b/semantics/systemInstructions/jnb_rel8.k deleted file mode 100644 index d831e9646..000000000 --- a/semantics/systemInstructions/jnb_rel8.k +++ /dev/null @@ -1,22 +0,0 @@ -requires "x86-configuration.k" - - -module JNB-REL8 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jnb Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) - - rule - execinstr (jnb Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) -endmodule diff --git a/semantics/systemInstructions/jnbe_rel32.k b/semantics/systemInstructions/jnbe_rel32.k index f042a5fbe..ceabcb423 100644 --- a/semantics/systemInstructions/jnbe_rel32.k +++ b/semantics/systemInstructions/jnbe_rel32.k @@ -5,21 +5,11 @@ module JNBE-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (jnbe Imm32:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> - addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, - 64)))) - - requires bitwidthMInt(Imm32) ==Int 32 andBool - (eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) + rule execinstr (jnbe Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires (eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) - rule - execinstr (jnbe Imm32:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm32) ==Int 32 andBool - (notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) - orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) + rule execinstr (jnbe _:MInt, .Operands) => . ... + RSMap + requires (notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) endmodule diff --git a/semantics/systemInstructions/jnbe_rel8.k b/semantics/systemInstructions/jnbe_rel8.k deleted file mode 100644 index ea4ef54ac..000000000 --- a/semantics/systemInstructions/jnbe_rel8.k +++ /dev/null @@ -1,25 +0,0 @@ -requires "x86-configuration.k" - - -module JNBE-REL8 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jnbe Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> - addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, - 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - (eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) - - rule - execinstr (jnbe Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - (notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) - orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) -endmodule diff --git a/semantics/systemInstructions/jnc_rel32.k b/semantics/systemInstructions/jnc_rel32.k index 4c86fa2f7..5251269be 100644 --- a/semantics/systemInstructions/jnc_rel32.k +++ b/semantics/systemInstructions/jnc_rel32.k @@ -5,18 +5,11 @@ module JNC-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (jnc Imm32:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - - requires bitwidthMInt(Imm32) ==Int 32 andBool - eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) + rule execinstr (jnc Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) - rule - execinstr (jnc Imm32:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm32) ==Int 32 andBool - eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + rule execinstr (jnc _:MInt, .Operands) => . ... + RSMap + requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jnc_rel8.k b/semantics/systemInstructions/jnc_rel8.k deleted file mode 100644 index 348665660..000000000 --- a/semantics/systemInstructions/jnc_rel8.k +++ /dev/null @@ -1,22 +0,0 @@ -requires "x86-configuration.k" - - -module JNC-REL8 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jnc Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) - - rule - execinstr (jnc Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) -endmodule diff --git a/semantics/systemInstructions/jne_rel32.k b/semantics/systemInstructions/jne_rel32.k index 3ef4d9f48..4e0ec43fb 100644 --- a/semantics/systemInstructions/jne_rel32.k +++ b/semantics/systemInstructions/jne_rel32.k @@ -5,18 +5,11 @@ module JNE-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (jne Imm32:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - - requires bitwidthMInt(Imm32) ==Int 32 andBool - eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + rule execinstr (jne Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) - rule - execinstr (jne Imm32:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm32) ==Int 32 andBool - notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + rule execinstr (jne _:MInt, .Operands) => . ... + RSMap + requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jne_rel8.k b/semantics/systemInstructions/jne_rel8.k deleted file mode 100644 index d442a86c0..000000000 --- a/semantics/systemInstructions/jne_rel8.k +++ /dev/null @@ -1,22 +0,0 @@ -requires "x86-configuration.k" - - -module JNE-REL8 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jne Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) - - rule - execinstr (jne Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) -endmodule diff --git a/semantics/systemInstructions/jng_rel32.k b/semantics/systemInstructions/jng_rel32.k index 4f9fafeda..f69efec29 100644 --- a/semantics/systemInstructions/jng_rel32.k +++ b/semantics/systemInstructions/jng_rel32.k @@ -5,18 +5,11 @@ module JNG-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (jng Imm32:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - - requires bitwidthMInt(Imm32) ==Int 32 andBool - (eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) orBool notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) + rule execinstr (jng Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires (eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) orBool notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) - rule - execinstr (jng Imm32:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm32) ==Int 32 andBool - (notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) andBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) + rule execinstr (jng _:MInt, .Operands) => . ... + RSMap + requires (notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) andBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) endmodule diff --git a/semantics/systemInstructions/jng_rel8.k b/semantics/systemInstructions/jng_rel8.k deleted file mode 100644 index d8b505c01..000000000 --- a/semantics/systemInstructions/jng_rel8.k +++ /dev/null @@ -1,22 +0,0 @@ -requires "x86-configuration.k" - - -module JNG-REL8 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jng Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - (eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) orBool notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) - - rule - execinstr (jng Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - (notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) andBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) -endmodule diff --git a/semantics/systemInstructions/jnge_rel32.k b/semantics/systemInstructions/jnge_rel32.k index a04ced00d..9cf5623f2 100644 --- a/semantics/systemInstructions/jnge_rel32.k +++ b/semantics/systemInstructions/jnge_rel32.k @@ -5,18 +5,11 @@ module JNGE-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (jnge Imm32:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - - requires bitwidthMInt(Imm32) ==Int 32 andBool - notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + rule execinstr (jnge Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) - rule - execinstr (jnge Imm32:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm32) ==Int 32 andBool - eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + rule execinstr (jnge _:MInt, .Operands) => . ... + RSMap + requires eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) endmodule diff --git a/semantics/systemInstructions/jnge_rel8.k b/semantics/systemInstructions/jnge_rel8.k deleted file mode 100644 index adf16426e..000000000 --- a/semantics/systemInstructions/jnge_rel8.k +++ /dev/null @@ -1,22 +0,0 @@ -requires "x86-configuration.k" - - -module JNGE-REL8 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jnge Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) - - rule - execinstr (jnge Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) -endmodule diff --git a/semantics/systemInstructions/jnl_rel32.k b/semantics/systemInstructions/jnl_rel32.k index 440ddf0ea..e277a5d4e 100644 --- a/semantics/systemInstructions/jnl_rel32.k +++ b/semantics/systemInstructions/jnl_rel32.k @@ -5,18 +5,11 @@ module JNL-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (jnl Imm32:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - - requires bitwidthMInt(Imm32) ==Int 32 andBool - eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + rule execinstr (jnl Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) - rule - execinstr (jnl Imm32:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm32) ==Int 32 andBool - notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + rule execinstr (jnl _:MInt, .Operands) => . ... + RSMap + requires notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) endmodule diff --git a/semantics/systemInstructions/jnl_rel8.k b/semantics/systemInstructions/jnl_rel8.k deleted file mode 100644 index 50f56302d..000000000 --- a/semantics/systemInstructions/jnl_rel8.k +++ /dev/null @@ -1,22 +0,0 @@ -requires "x86-configuration.k" - - -module JNL-REL8 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jnl Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) - - rule - execinstr (jnl Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) -endmodule diff --git a/semantics/systemInstructions/jnle_rel32.k b/semantics/systemInstructions/jnle_rel32.k index e772fc77a..9e2101d3d 100644 --- a/semantics/systemInstructions/jnle_rel32.k +++ b/semantics/systemInstructions/jnle_rel32.k @@ -5,18 +5,11 @@ module JNLE-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (jnle Imm32:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - - requires bitwidthMInt(Imm32) ==Int 32 andBool - (eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) + rule execinstr (jnle Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires (eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) - rule - execinstr (jnle Imm32:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm32) ==Int 32 andBool - (notBool eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) orBool notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) + rule execinstr (jnle _:MInt, .Operands) => . ... + RSMap + requires (notBool eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) orBool notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) endmodule diff --git a/semantics/systemInstructions/jnle_rel8.k b/semantics/systemInstructions/jnle_rel8.k deleted file mode 100644 index 44fd34677..000000000 --- a/semantics/systemInstructions/jnle_rel8.k +++ /dev/null @@ -1,22 +0,0 @@ -requires "x86-configuration.k" - - -module JNLE-REL8 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jnle Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - (eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) - - rule - execinstr (jnle Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - (notBool eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) orBool notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) -endmodule diff --git a/semantics/systemInstructions/jno_rel32.k b/semantics/systemInstructions/jno_rel32.k index 593c31f33..a93c313ee 100644 --- a/semantics/systemInstructions/jno_rel32.k +++ b/semantics/systemInstructions/jno_rel32.k @@ -5,18 +5,11 @@ module JNO-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (jno Imm32:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - - requires bitwidthMInt(Imm32) ==Int 32 andBool - eqMInt({RSMap["OF"]}:>MInt, mi(1, 0)) + rule execinstr (jno Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires eqMInt({RSMap["OF"]}:>MInt, mi(1, 0)) - rule - execinstr (jno Imm32:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm32) ==Int 32 andBool - notBool eqMInt({RSMap["OF"]}:>MInt, mi(1, 0)) + rule execinstr (jno _:MInt, .Operands) => . ... + RSMap + requires notBool eqMInt({RSMap["OF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jno_rel8.k b/semantics/systemInstructions/jno_rel8.k deleted file mode 100644 index 8741ffeef..000000000 --- a/semantics/systemInstructions/jno_rel8.k +++ /dev/null @@ -1,22 +0,0 @@ -requires "x86-configuration.k" - - -module JNO-REL8 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jno Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt({RSMap["OF"]}:>MInt, mi(1, 0)) - - rule - execinstr (jno Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - notBool eqMInt({RSMap["OF"]}:>MInt, mi(1, 0)) -endmodule diff --git a/semantics/systemInstructions/jnp_rel32.k b/semantics/systemInstructions/jnp_rel32.k index 68adf18c3..49f5264c0 100644 --- a/semantics/systemInstructions/jnp_rel32.k +++ b/semantics/systemInstructions/jnp_rel32.k @@ -5,18 +5,11 @@ module JNP-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (jnp Imm32:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - - requires bitwidthMInt(Imm32) ==Int 32 andBool - eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) + rule execinstr (jnp Imm64, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) - rule - execinstr (jnp Imm32:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm32) ==Int 32 andBool - notBool eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) + rule execinstr (jnp _:MInt, .Operands) => . ... + RSMap + requires notBool eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jnp_rel8.k b/semantics/systemInstructions/jnp_rel8.k deleted file mode 100644 index 9a54f70a8..000000000 --- a/semantics/systemInstructions/jnp_rel8.k +++ /dev/null @@ -1,22 +0,0 @@ -requires "x86-configuration.k" - - -module JNP-REL8 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jnp Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) - - rule - execinstr (jnp Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - notBool eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) -endmodule diff --git a/semantics/systemInstructions/jns_rel32.k b/semantics/systemInstructions/jns_rel32.k index 7e2a9b089..43a956cc1 100644 --- a/semantics/systemInstructions/jns_rel32.k +++ b/semantics/systemInstructions/jns_rel32.k @@ -5,18 +5,11 @@ module JNS-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (jns Imm32:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - - requires bitwidthMInt(Imm32) ==Int 32 andBool - eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) + rule execinstr (jns Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) - rule - execinstr (jns Imm32:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm32) ==Int 32 andBool - eqMInt({RSMap["SF"]}:>MInt, mi(1, 1)) + rule execinstr (jns _:MInt, .Operands) => . ... + RSMap + requires eqMInt({RSMap["SF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jns_rel8.k b/semantics/systemInstructions/jns_rel8.k deleted file mode 100644 index 25353444d..000000000 --- a/semantics/systemInstructions/jns_rel8.k +++ /dev/null @@ -1,22 +0,0 @@ -requires "x86-configuration.k" - - -module JNS-REL8 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jns Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) - - rule - execinstr (jns Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt({RSMap["SF"]}:>MInt, mi(1, 1)) -endmodule diff --git a/semantics/systemInstructions/jnz_rel32.k b/semantics/systemInstructions/jnz_rel32.k index 25380d73a..d43a42410 100644 --- a/semantics/systemInstructions/jnz_rel32.k +++ b/semantics/systemInstructions/jnz_rel32.k @@ -5,18 +5,11 @@ module JNZ-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (jnz Imm32:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - - requires bitwidthMInt(Imm32) ==Int 32 andBool - eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + rule execinstr (jnz Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) - rule - execinstr (jnz Imm32:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm32) ==Int 32 andBool - notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + rule execinstr (jnz _:MInt, .Operands) => . ... + RSMap + requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jnz_rel8.k b/semantics/systemInstructions/jnz_rel8.k deleted file mode 100644 index beeb4f24b..000000000 --- a/semantics/systemInstructions/jnz_rel8.k +++ /dev/null @@ -1,22 +0,0 @@ -requires "x86-configuration.k" - - -module JNZ-REL8 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jnz Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) - - rule - execinstr (jnz Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) -endmodule diff --git a/semantics/systemInstructions/jo_rel32.k b/semantics/systemInstructions/jo_rel32.k index fe453c6f6..cfc8304c8 100644 --- a/semantics/systemInstructions/jo_rel32.k +++ b/semantics/systemInstructions/jo_rel32.k @@ -5,18 +5,11 @@ module JO-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (jo Imm32:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - - requires bitwidthMInt(Imm32) ==Int 32 andBool - eqMInt({RSMap["OF"]}:>MInt, mi(1, 1)) + rule execinstr (jo Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires eqMInt({RSMap["OF"]}:>MInt, mi(1, 1)) - rule - execinstr (jo Imm32:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm32) ==Int 32 andBool - notBool eqMInt({RSMap["OF"]}:>MInt, mi(1, 1)) + rule execinstr (jo _:MInt, .Operands) => . ... + RSMap + requires notBool eqMInt({RSMap["OF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jo_rel8.k b/semantics/systemInstructions/jo_rel8.k deleted file mode 100644 index 4affc1844..000000000 --- a/semantics/systemInstructions/jo_rel8.k +++ /dev/null @@ -1,22 +0,0 @@ -requires "x86-configuration.k" - - -module JO-REL8 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jo Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt({RSMap["OF"]}:>MInt, mi(1, 1)) - - rule - execinstr (jo Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - notBool eqMInt({RSMap["OF"]}:>MInt, mi(1, 1)) -endmodule diff --git a/semantics/systemInstructions/jp_rel32.k b/semantics/systemInstructions/jp_rel32.k index ad9524a68..f8574a048 100644 --- a/semantics/systemInstructions/jp_rel32.k +++ b/semantics/systemInstructions/jp_rel32.k @@ -5,18 +5,11 @@ module JP-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (jp Imm32:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - - requires bitwidthMInt(Imm32) ==Int 32 andBool - eqMInt({RSMap["PF"]}:>MInt, mi(1, 1)) + rule execinstr (jp Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 1)) - rule - execinstr (jp Imm32:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm32) ==Int 32 andBool - eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) + rule execinstr (jp _:MInt, .Operands) => . ... + RSMap + requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jp_rel8.k b/semantics/systemInstructions/jp_rel8.k deleted file mode 100644 index 1bcddf0b4..000000000 --- a/semantics/systemInstructions/jp_rel8.k +++ /dev/null @@ -1,22 +0,0 @@ -requires "x86-configuration.k" - - -module JP-REL8 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jp Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt({RSMap["PF"]}:>MInt, mi(1, 1)) - - rule - execinstr (jp Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) -endmodule diff --git a/semantics/systemInstructions/jpe_rel32.k b/semantics/systemInstructions/jpe_rel32.k index 31522376b..87ebae5e6 100644 --- a/semantics/systemInstructions/jpe_rel32.k +++ b/semantics/systemInstructions/jpe_rel32.k @@ -5,18 +5,11 @@ module JPE-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (jpe Imm32:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - - requires bitwidthMInt(Imm32) ==Int 32 andBool - eqMInt({RSMap["PF"]}:>MInt, mi(1, 1)) + rule execinstr (jpe Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 1)) - rule - execinstr (jpe Imm32:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm32) ==Int 32 andBool - eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) + rule execinstr (jpe Imm32:MInt, .Operands) => . ... + RSMap + requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jpe_rel8.k b/semantics/systemInstructions/jpe_rel8.k deleted file mode 100644 index ef6bb2dbc..000000000 --- a/semantics/systemInstructions/jpe_rel8.k +++ /dev/null @@ -1,22 +0,0 @@ -requires "x86-configuration.k" - - -module JPE-REL8 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jpe Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt({RSMap["PF"]}:>MInt, mi(1, 1)) - - rule - execinstr (jpe Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) -endmodule diff --git a/semantics/systemInstructions/jpo_rel32.k b/semantics/systemInstructions/jpo_rel32.k index ee70f0267..2794b1fd3 100644 --- a/semantics/systemInstructions/jpo_rel32.k +++ b/semantics/systemInstructions/jpo_rel32.k @@ -5,18 +5,11 @@ module JPO-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (jpo Imm32:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - - requires bitwidthMInt(Imm32) ==Int 32 andBool - eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) + rule execinstr (jpo Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) - rule - execinstr (jpo Imm32:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm32) ==Int 32 andBool - notBool eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) + rule execinstr (jpo _:MInt, .Operands) => . ... + RSMap + requires notBool eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jpo_rel8.k b/semantics/systemInstructions/jpo_rel8.k deleted file mode 100644 index 45a4d5ca6..000000000 --- a/semantics/systemInstructions/jpo_rel8.k +++ /dev/null @@ -1,22 +0,0 @@ -requires "x86-configuration.k" - - -module JPO-REL8 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jpo Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) - - rule - execinstr (jpo Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - notBool eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) -endmodule diff --git a/semantics/systemInstructions/jrcxz_rel8.k b/semantics/systemInstructions/jrcxz_rel8.k index 6c5be105f..691588fae 100644 --- a/semantics/systemInstructions/jrcxz_rel8.k +++ b/semantics/systemInstructions/jrcxz_rel8.k @@ -5,18 +5,11 @@ module JRCXZ-REL8 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (jrcxz Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt(getRegisterValue(%rcx, RSMap), mi(64, 0)) + rule execinstr (jrcxz Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires eqMInt(getRegisterValue(%rcx, RSMap), mi(64, 0)) - rule - execinstr (jrcxz Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - notBool eqMInt(getRegisterValue(%rcx, RSMap), mi(64, 0)) + rule execinstr (jrcxz _:MInt, .Operands) => . ... + RSMap + requires notBool eqMInt(getRegisterValue(%rcx, RSMap), mi(64, 0)) endmodule diff --git a/semantics/systemInstructions/js_rel32.k b/semantics/systemInstructions/js_rel32.k index 50b6dcf19..395962e59 100644 --- a/semantics/systemInstructions/js_rel32.k +++ b/semantics/systemInstructions/js_rel32.k @@ -5,18 +5,11 @@ module JS-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (js Imm32:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - - requires bitwidthMInt(Imm32) ==Int 32 andBool - eqMInt({RSMap["SF"]}:>MInt, mi(1, 1)) + rule execinstr (js Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires eqMInt({RSMap["SF"]}:>MInt, mi(1, 1)) - rule - execinstr (js Imm32:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm32) ==Int 32 andBool - eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) + rule execinstr (js _:MInt, .Operands) => . ... + RSMap + requires eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/js_rel8.k b/semantics/systemInstructions/js_rel8.k deleted file mode 100644 index 4d1431c76..000000000 --- a/semantics/systemInstructions/js_rel8.k +++ /dev/null @@ -1,22 +0,0 @@ -requires "x86-configuration.k" - - -module JS-REL8 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (js Imm8:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt({RSMap["SF"]}:>MInt, mi(1, 1)) - - rule - execinstr (js Imm8:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) -endmodule diff --git a/semantics/systemInstructions/jz_rel32.k b/semantics/systemInstructions/jz_rel32.k index 788921fe5..f33362be5 100644 --- a/semantics/systemInstructions/jz_rel32.k +++ b/semantics/systemInstructions/jz_rel32.k @@ -5,18 +5,11 @@ module JZ-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (jz Imm32:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - - requires bitwidthMInt(Imm32) ==Int 32 andBool - eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + rule execinstr (jz Imm64:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64)) + requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) - rule - execinstr (jz Imm32:MInt, .Operands) => . - ... - RSMap:Map - requires bitwidthMInt(Imm32) ==Int 32 andBool - notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + rule execinstr (jz _:MInt, .Operands) => . ... + RSMap + requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/loop_rel8.k b/semantics/systemInstructions/loop_rel8.k index e490e63f1..0e184a5c6 100644 --- a/semantics/systemInstructions/loop_rel8.k +++ b/semantics/systemInstructions/loop_rel8.k @@ -5,31 +5,14 @@ module LOOP-REL8 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (loop Imm8:MInt, .Operands) => execinstr (loop Imm8, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) - ... + rule execinstr (loop Imm64:MInt, .Operands) => execinstr (loop Imm64, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) ... RSMap - requires bitwidthMInt(Imm8) ==Int 8 - rule - execinstr (loop Imm8:MInt, Count:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, - ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64))) - ("RCX" |-> Count) - ) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) - - rule - execinstr (loop Imm8:MInt, Count:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, - ("RCX" |-> Count) - ) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - eqMInt(Count, mi(bitwidthMInt(Count), 0)) + rule execinstr (loop Imm64:MInt, Count:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64) ("RCX" |-> Count)) + requires notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) + rule execinstr (loop Imm64:MInt, Count:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RCX" |-> Count)) + requires eqMInt(Count, mi(bitwidthMInt(Count), 0)) endmodule diff --git a/semantics/systemInstructions/loope_rel8.k b/semantics/systemInstructions/loope_rel8.k index 140a98d9d..be83ec3ab 100644 --- a/semantics/systemInstructions/loope_rel8.k +++ b/semantics/systemInstructions/loope_rel8.k @@ -5,33 +5,14 @@ module LOOPE-REL8 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (loope Imm8:MInt, .Operands) => execinstr (loope Imm8, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) - ... + rule execinstr (loope Imm64:MInt, .Operands) => execinstr (loope Imm64, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) ... RSMap - requires bitwidthMInt(Imm8) ==Int 8 - rule - execinstr (loope Imm8:MInt, Count:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, - ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64))) - ("RCX" |-> Count) - ) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - (notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) - andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1))) - - rule - execinstr (loope Imm8:MInt, Count:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, - ("RCX" |-> Count) - ) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - (eqMInt(Count, mi(bitwidthMInt(Count), 0)) - orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1))) + rule execinstr (loope Imm64:MInt, Count:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64) ("RCX" |-> Count)) + requires (notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1))) + rule execinstr (loope Imm8:MInt, Count:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RCX" |-> Count)) + requires (eqMInt(Count, mi(bitwidthMInt(Count), 0)) orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1))) endmodule diff --git a/semantics/systemInstructions/loopne_rel8.k b/semantics/systemInstructions/loopne_rel8.k index a6cde7c73..46b889237 100644 --- a/semantics/systemInstructions/loopne_rel8.k +++ b/semantics/systemInstructions/loopne_rel8.k @@ -5,33 +5,14 @@ module LOOPNE-REL8 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (loopne Imm8:MInt, .Operands) => execinstr (loope Imm8, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) - ... + rule execinstr (loopne Imm64:MInt, .Operands) => execinstr (loope Imm64, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) ... RSMap - requires bitwidthMInt(Imm8) ==Int 8 - rule - execinstr (loopne Imm8:MInt, Count:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, - ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64))) - ("RCX" |-> Count) - ) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - (notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) - andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) - - rule - execinstr (loopne Imm8:MInt, Count:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, - ("RCX" |-> Count) - ) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - (eqMInt(Count, mi(bitwidthMInt(Count), 0)) - orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) + rule execinstr (loopne Imm64:MInt, Count:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64) ("RCX" |-> Count)) + requires (notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) + rule execinstr (loopne Imm64:MInt, Count:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RCX" |-> Count)) + requires (eqMInt(Count, mi(bitwidthMInt(Count), 0)) orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) endmodule diff --git a/semantics/systemInstructions/loopnz_rel8.k b/semantics/systemInstructions/loopnz_rel8.k index bf1b354b7..17203acb3 100644 --- a/semantics/systemInstructions/loopnz_rel8.k +++ b/semantics/systemInstructions/loopnz_rel8.k @@ -5,33 +5,14 @@ module LOOPNE-REL8 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (loopnz Imm8:MInt, .Operands) => execinstr (loopnz Imm8, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) - ... - RSMap - requires bitwidthMInt(Imm8) ==Int 8 + rule execinstr (loopnz Imm64:MInt, .Operands) => execinstr (loopnz Imm64, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) ... + RSMap - rule - execinstr (loopnz Imm8:MInt, Count:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, - ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64))) - ("RCX" |-> Count) - ) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - ( notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) - andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) - - rule - execinstr (loopnz Imm8:MInt, Count:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, - ("RCX" |-> Count) - ) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - ( eqMInt(Count, mi(bitwidthMInt(Count), 0)) - orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) + rule execinstr (loopnz Imm64:MInt, Count:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64) ("RCX" |-> Count)) + requires (notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) + rule execinstr (loopnz Imm64:MInt, Count:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RCX" |-> Count)) + requires (eqMInt(Count, mi(bitwidthMInt(Count), 0)) orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) endmodule diff --git a/semantics/systemInstructions/loopz_rel8.k b/semantics/systemInstructions/loopz_rel8.k index cfa525dd6..3f2dfb1ed 100644 --- a/semantics/systemInstructions/loopz_rel8.k +++ b/semantics/systemInstructions/loopz_rel8.k @@ -5,33 +5,14 @@ module LOOPE-REL8 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule - execinstr (loopz Imm8:MInt, .Operands) => execinstr (loopz Imm8, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) - ... + rule execinstr (loopz Imm64:MInt, .Operands) => execinstr (loopz Imm64, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) ... RSMap - requires bitwidthMInt(Imm8) ==Int 8 - rule - execinstr (loopz Imm8:MInt, Count:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, - ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64))) - ("RCX" |-> Count) - ) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - ( notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) - andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1))) - - rule - execinstr (loopz Imm8:MInt, Count:MInt, .Operands) => . - ... - RSMap => updateMap(RSMap, - ("RCX" |-> Count) - ) - - requires bitwidthMInt(Imm8) ==Int 8 andBool - ( eqMInt(Count, mi(bitwidthMInt(Count), 0)) - orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1))) + rule execinstr (loopz Imm64:MInt, Count:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> Imm64) ("RCX" |-> Count)) + requires (notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1))) + rule execinstr (loopz Imm64:MInt, Count:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RCX" |-> Count)) + requires (eqMInt(Count, mi(bitwidthMInt(Count), 0)) orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1))) endmodule diff --git a/semantics/test.c b/semantics/test.c index 08cf56f3c..755705369 100644 --- a/semantics/test.c +++ b/semantics/test.c @@ -1,26 +1,16 @@ #include +#include #include -int fib(const int n) { - if (n == 0) { - return 0; - } else if (n == 1) { - return 1; - } else { - int nums[n + 1]; - nums[0] = 0; - nums[1] = 1; - for (int i = 2; i <= n; ++i) { - nums[i] = nums[i - 1] + nums[i - 2]; - } - return nums[n]; - } -} - -const int elems[] = {0, 1, 5, 10, 20, 40}; - -int main() { - for (int i = 0; i < sizeof(elems) / sizeof(int); ++i) { - printf("%d: %d\n", elems[i], fib(elems[i])); - } +int main () { + const char * str = "The quick brown fox jumped over the lazy dog"; + const int len = strlen(str); + const char * space = " "; + char buf[len + 1]; + char * sptr = buf; + strncpy(buf, str, len); + while (sptr != NULL) { + puts(strsep(&sptr, space)); + } + return 0; } diff --git a/semantics/x86-abstract-semantics.k b/semantics/x86-abstract-semantics.k index 79a6ce5d7..08ea1e82c 100644 --- a/semantics/x86-abstract-semantics.k +++ b/semantics/x86-abstract-semantics.k @@ -35,6 +35,11 @@ module X86-ABSTRACT-SEMANTICS rule I:Int (R1:R64):Mem => memOffset( addMInt(mi(64, I), getRegisterValue(R1, RSMap))) ... RSMap + rule (R:Rip):Mem => 0 (R) ... + + rule I:Int (R:Rip) => memOffset(addMInt(mi(64, I), getRegisterValue(R, RSMap))) ... + RSMap + // (, %r64) rule (, R2:R64):Mem => 0 (, R2, 1) ... rule I:Int (, R2:R64):Mem => I (, R2, 1) ... @@ -296,12 +301,10 @@ module X86-ABSTRACT-SEMANTICS rule getRegisterValue(R:R16, RSMap) => extractMask(KItemToMInt(RSMap[convToRegKeys(R)]), 16, 0) rule getRegisterValue(R:R32, RSMap) => extractMask(KItemToMInt(RSMap[convToRegKeys(R)]), 32, 0) rule getRegisterValue(R:R64, RSMap) => KItemToMInt(RSMap[convToRegKeys(R)]) + rule getRegisterValue(R:Rip, RSMap) => KItemToMInt(RSMap["RIP"]) rule getRegisterValue(R:Rh, RSMap) => extractMask(KItemToMInt(RSMap[convToRegKeys(R)]), 8, 8) rule getRegisterValue(X:Xmm, RSMap) => extractMask(KItemToMInt(RSMap[convToRegKeys(X)]), 128, 0) rule getRegisterValue(Y:Ymm, RSMap) => KItemToMInt(RSMap[convToRegKeys(Y)]) -/* - rule getRegisterValue(M:Mm, RSMap) => {RSMap[convToRegKeys(M)]}:>MInt -*/ rule getParentValue(R:Register, RSMap) => getRegisterValue(convSubRegsToRegs(R), RSMap) /*@ @@ -533,7 +536,7 @@ module X86-ABSTRACT-SEMANTICS */ rule findLimitIndexI(Value:MInt, Imm8:MInt) => findLimitIndexIHelper(Value, KItemToInt(#ifInt eqMInt(extractMInt(Imm8, 7, 8), mi(1, 1)) #then 16 #else 8 #fi), - KItemToInt(#ifInt eqMInt(extractMInt(Imm8, 7, 8), mi(1, 1)) #then 8 #else 16 #fi}), + KItemToInt(#ifInt eqMInt(extractMInt(Imm8, 7, 8), mi(1, 1)) #then 8 #else 16 #fi), 0) rule findLimitIndexIHelper(Value:MInt, BitLength:Int, NumElems:Int, Count:Int) => mi(8, Count) @@ -592,8 +595,8 @@ module X86-ABSTRACT-SEMANTICS rule compareEqual(Count2:Int, Count1:Int, Value2:MInt, Value1:MInt, Limit2:MInt, Limit1:MInt, NumElems:Int, SOrU:MInt) => compareEqualSignedOrUnsigned( - extractMask(Value2, KItemToInt(#ifInt NumElems ==Int 8 #then 16 #else 8 #fi}:>Int, Count2 *Int {#if NumElems ==Int 8 #then 16 #else 8 #fi)), - extractMask(Value1, KItemToInt(#ifInt NumElems ==Int 8 #then 16 #else 8 #fi}:>Int, Count1 *Int {#if NumElems ==Int 8 #then 16 #else 8 #fi)), + extractMask(Value2, KItemToInt(#ifInt NumElems ==Int 8 #then 16 #else 8 #fi), Count2 *Int #if NumElems ==Int 8 #then 16 #else 8 #fi), + extractMask(Value1, KItemToInt(#ifInt NumElems ==Int 8 #then 16 #else 8 #fi), Count1 *Int #if NumElems ==Int 8 #then 16 #else 8 #fi), SOrU ) requires Count1 compareEqualSignedOrUnsigned( - extractMask(Value2, KItemToInt(#ifInt NumElems ==Int 8 #then 16 #else 8 #fi}:>Int, Index *Int {#if NumElems ==Int 8 #then 16 #else 8 #fi)), - extractMask(Value1, KItemToINt(#ifInt NumElems ==Int 8 #then 16 #else 8 #fi}:>Int, Index *Int {#if NumElems ==Int 8 #then 16 #else 8 #fi)), + extractMask(Value2, KItemToInt(#ifInt NumElems ==Int 8 #then 16 #else 8 #fi), Index *Int #if NumElems ==Int 8 #then 16 #else 8 #fi), + extractMask(Value1, KItemToInt(#ifInt NumElems ==Int 8 #then 16 #else 8 #fi), Index *Int #if NumElems ==Int 8 #then 16 #else 8 #fi), SOrU ) requires // If both of the data are valid @@ -698,13 +701,13 @@ module X86-ABSTRACT-SEMANTICS rule compareRange(Count2:Int, Count1:Int, Value2:MInt, Value1:MInt, Limit2:MInt, Limit1:MInt, NumElems:Int, SOrU:MInt) => andMInt( compareGESignedOrUnsigned( - extractMask(Value2, KItemToInt(#ifInt NumElems ==Int 8 #then 16 #else 8 #fi}:>Int, Count2 *Int {#if NumElems ==Int 8 #then 16 #else 8 #fi)), - extractMask(Value1, KItemToInt(#ifInt NumElems ==Int 8 #then 16 #else 8 #fi}:>Int, Count1 *Int {#if NumElems ==Int 8 #then 16 #else 8 #fi)), + extractMask(Value2, KItemToInt(#ifInt NumElems ==Int 8 #then 16 #else 8 #fi), Count2 *Int #if NumElems ==Int 8 #then 16 #else 8 #fi), + extractMask(Value1, KItemToInt(#ifInt NumElems ==Int 8 #then 16 #else 8 #fi), Count1 *Int #if NumElems ==Int 8 #then 16 #else 8 #fi), SOrU ), compareLESignedOrUnsigned( - extractMask(Value2, KItemToInt(#ifInt NumElems ==Int 8 #then 16 #else 8 #fi}:>Int, Count2 *Int {#if NumElems ==Int 8 #then 16 #else 8 #fi)), - extractMask(Value1, KItemToInt(#ifInt NumElems ==Int 8 #then 16 #else 8 #fi}:>Int, Count1 *Int {#if NumElems ==Int 8 #then 16 #else 8 #fi)), + extractMask(Value2, KItemToInt(#ifInt NumElems ==Int 8 #then 16 #else 8 #fi), Count2 *Int #if NumElems ==Int 8 #then 16 #else 8 #fi), + extractMask(Value1, KItemToInt(#ifInt NumElems ==Int 8 #then 16 #else 8 #fi), Count1 *Int #if NumElems ==Int 8 #then 16 #else 8 #fi), SOrU )) @@ -758,8 +761,8 @@ module X86-ABSTRACT-SEMANTICS rule compareEqualOrdered(Count2:Int, Count1:Int, Value2:MInt, Value1:MInt, Limit2:MInt, Limit1:MInt, NumElems:Int, SOrU:MInt) => compareEqualSignedOrUnsigned( - extractMask(Value2, KItemToInt(#ifInt NumElems ==Int 8 #then 16 #else 8 #fi}:>Int, Count2 *Int {#if NumElems ==Int 8 #then 16 #else 8 #fi})), - extractMask(Value1, KItemToInt(#ifInt NumElems ==Int 8 #then 16 #else 8 #fi}:>Int, Count1 *Int {#if NumElems ==Int 8 #then 16 #else 8 #fi})), + extractMask(Value2, KItemToInt(#ifInt NumElems ==Int 8 #then 16 #else 8 #fi), Count2 *Int #if NumElems ==Int 8 #then 16 #else 8 #fi), + extractMask(Value1, KItemToInt(#ifInt NumElems ==Int 8 #then 16 #else 8 #fi), Count1 *Int #if NumElems ==Int 8 #then 16 #else 8 #fi), SOrU ) diff --git a/semantics/x86-configuration.k b/semantics/x86-configuration.k index 615f796ef..6263b892f 100644 --- a/semantics/x86-configuration.k +++ b/semantics/x86-configuration.k @@ -107,4 +107,5 @@ module X86-CONFIGURATION + .List // For debugging, similar to regstatequeue endmodule diff --git a/semantics/x86-fetch-execute.k b/semantics/x86-fetch-execute.k index b0f7a5d3b..da03886b1 100644 --- a/semantics/x86-fetch-execute.k +++ b/semantics/x86-fetch-execute.k @@ -38,11 +38,16 @@ module X86-FETCH-EXECUTE rule memLoadValue(MI:MInt) ~> loadInstructionBytesFromMemoryAux(Ip, Is, I) => loadInstructionBytesFromMemoryAux(addMInt(Ip, mi(logicalAddressWidth, 1)), uvalueMInt(MI) Is, I +Int 1) [owise] rule loadInstructionBytesFromMemoryAux(_, Is, maxInstructionLength) => reverseInts(Is) + syntax K ::= IncrementRIP(Int) + rule invokeDecoder(I:Int, Is:Ints) => Decode(I, Is) - rule DecodedInstruction(Len:Int, _, I:Instruction, _) => execinstr(I) ... - RSMap => RSMap["RIP" <- addMInt({RSMap["RIP"]}:>MInt, mi(logicalAddressWidth, Len))] + rule DecodedInstruction(Len:Int, _, I:Instruction, _) => IncrementRIP(Len) ~> execinstr(I) ... + ... .List => ListItem(I) + rule IncrementRIP(Len) => . ... + RSMap => RSMap["RIP" <- addMInt({RSMap["RIP"]}:>MInt, mi(logicalAddressWidth, Len))] + syntax KItem ::= "exit_0" syntax KItem ::= "illegal_halt" diff --git a/semantics/x86-syntax.k b/semantics/x86-syntax.k index 3d7d6ec93..f98d2b767 100644 --- a/semantics/x86-syntax.k +++ b/semantics/x86-syntax.k @@ -86,8 +86,8 @@ module X86-SYNTAX * Adding Int and Float as operands helps in * testing float-conversion directly. */ - | Int - | Float +// | Int +// | Float /*@ * execinstr(Opcode (R:Operand .Operands):Operands) * are sometimes writen as From b7571492dff9facc04f1f56cf53e8c779dfe2d3b Mon Sep 17 00:00:00 2001 From: andrew_miranti Date: Thu, 14 Mar 2019 12:37:16 -0500 Subject: [PATCH 14/15] Use 0 rather than undefMInt for uninitialized memory --- semantics/x86-memory.k | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/semantics/x86-memory.k b/semantics/x86-memory.k index a6ac14fde..fada1b854 100644 --- a/semantics/x86-memory.k +++ b/semantics/x86-memory.k @@ -154,7 +154,7 @@ module X86-MEMORY rule findValueInROM(A, ListItem(StringSegment(Start, End, S)) L) => findValueInROM(A, L) requires uvalueMInt(A) =Int End - rule findValueInROM(A, .List) => undefMInt + rule findValueInROM(A, .List) => 0 rule loadFromMemory(Addr, 8) => memLoadValue(findValueInMemory(Addr, MemMap, ROMList)) ... MemMap => MemMap[Addr <- findValueInMemory(Addr, MemMap, ROMList)] From 859a0291fef0c9c541be31caee0ffcdeeb7fd847 Mon Sep 17 00:00:00 2001 From: andrew_miranti Date: Fri, 5 Apr 2019 13:35:36 -0500 Subject: [PATCH 15/15] Ran most of the gcc torture tests. Have now lost the results for the jobs 601 to 1465 twice. --- .gitignore | 2 + semantics/a.out | Bin 984800 -> 0 bytes semantics/crashed_files.txt | 51 + semantics/immediateInstructions/pushq_imm8.k | 23 + semantics/reran_files.txt | 42655 ++++++++++++++++ semantics/run-on-elf.py | 62 +- semantics/test.c | 10 +- semantics/tests-to-rerun.txt | 38 + semantics/x86-configuration.k | 2 + semantics/x86-fetch-execute.k | 25 +- semantics/x86-memory.k | 4 +- .../job_101_600/bin/20010224-1-0.asm | 368 - .../job_101_600/bin/20010325-1-0.asm | 293 - .../job_101_600/bin/20010329-1-0.asm | 293 - .../job_101_600/bin/20010403-1-0.asm | 338 - .../job_101_600/bin/20010409-1-0.asm | 402 - .../job_101_600/bin/20010422-1-0.asm | 296 - .../job_101_600/bin/20010518-1-0.asm | 331 - .../job_101_600/bin/20010518-2-0.asm | 320 - .../job_101_600/bin/20010520-1-0.asm | 286 - .../job_101_600/bin/20010604-1-0.asm | 328 - .../job_101_600/bin/20010605-1-0.asm | 305 - .../job_101_600/bin/20010605-2-0.asm | 430 - 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z{&u$izdipFJg?)|-UY$)eExYp@3-fFU+g^}eAxIGeAxK+DCxRC3HO12kMo}2&gZxD z`JMIO_2WeE`GCLk7))FH!(MytIrn#|_q_X^<4Hb0=P6LX|Gju#XgU55e8tA!{}pS0 z+$n1I!+-vC@A(J$`@-(||4n{2v;RJxdmcX{-gE(7FZcJg_#pPnzpi8d7mIMkF5iC0 z&pEoW$Iyc6BlZKpdDjqcdS9E?Zv6S_?-~EDn=xntf4&VR>E_L`RrGVK_D^`dwZDGY Ko_GKH?f+k(Lm4&z diff --git a/semantics/out.txt b/semantics/out.txt deleted file mode 100644 index 1eac0e415..000000000 --- a/semantics/out.txt +++ /dev/null @@ -1,33 +0,0 @@ -Entry(0x4009ae); -NamedSymbol(putchar, NotPresentInFile); -NamedSymbol(getchar, NotPresentInFile); -NamedSymbol(printf, 0x40f4b0); -NamedSymbol(fprintf, 0x45c5f0); -NamedSymbol(sprintf, NotPresentInFile); -NamedSymbol(snprintf, NotPresentInFile); -NamedSymbol(scanf, NotPresentInFile); -NamedSymbol(fscanf, NotPresentInFile); -NamedSymbol(__isoc99_fscanf, NotPresentInFile); -NamedSymbol(sscanf, 0x47a6a0); -NamedSymbol(_IO_putc, NotPresentInFile); -NamedSymbol(fputc, NotPresentInFile); -NamedSymbol(fopen, 0x40fc00); -NamedSymbol(freopen, NotPresentInFile); -NamedSymbol(fclose, 0x40f730); -NamedSymbol(fflush, 0x40f990); -NamedSymbol(fwrite, 0x462fd0); -NamedSymbol(fread, NotPresentInFile); -NamedSymbol(fputs, 0x462de0); -NamedSymbol(puts, NotPresentInFile); -NamedSymbol(feof, NotPresentInFile); -NamedSymbol(fgetc, NotPresentInFile); -NamedSymbol(getc, NotPresentInFile); -NamedSymbol(fgets, NotPresentInFile); -NamedSymbol(gets, NotPresentInFile); -NamedSymbol(fseek, 0x47a7d0); -NamedSymbol(rewind, NotPresentInFile); -NamedSymbol(malloc, 0x41dc60); -NamedSymbol(free, 0x41e000); -NamedSymbol(sqrt, NotPresentInFile); -Load(0x400000, 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0x3550); diff --git a/semantics/run-on-elf.py b/semantics/run-on-elf.py index 199603f1c..0677fe01c 100755 --- a/semantics/run-on-elf.py +++ b/semantics/run-on-elf.py @@ -2,7 +2,7 @@ import xml.etree.ElementTree as et import subprocess, sys, os, shutil, re, signal from collections import defaultdict -from functools import reduce +import functools default_backend = "ocaml" @@ -104,51 +104,14 @@ def delete_old_instructions(): shutil.rmtree(under_test_directory) os.mkdir(under_test_directory) -def read_inum_instruction_map(): - inums = None - instructions = None - with open(os.path.join(decoder_directory, "generator", "datafiles", "inums.txt"), "r") as f: - inums = [int(line) for line in f.readlines()] - with open(os.path.join(decoder_directory, "generator", "datafiles", "instructions.s"), "r") as f: - instructions = f.readlines() - assert len(inums) == len(instructions) - multimap = defaultdict(list) - for (inum, inst) in zip(inums, instructions): - multimap[inum].append(inst.strip()) - return multimap +def inum_file_pair_from_line(line): + split = line.split("|") + assert len(split) == 3 + return (int(split[2]), split[0]) def get_instructions_from_inums(inums): - inum_instruction_map = read_inum_instruction_map() - return sorted(list(reduce(lambda s1, s2: s1.union(s2), map(lambda inum: set(inum_instruction_map[inum]), inums)))) - - -def flatten(lst): - ret = [] - for l in lst: - ret.extend(l) - return ret - -def find_instructions(): - return sorted(flatten(map(lambda directory: [os.path.join(directory, name) for name in os.listdir(os.path.join(semantics_directory, instruction_directory_prefix, directory))], instruction_directories)), key=lambda x: os.path.basename(x)) - -# needed_names is of the form addb_r8_r8 ... available is of the form registerInstructions/addb_r8_r8.k. Need to match these up. -# It's important that both of these are sorted by the file name (aka the basename) so we can match efficiently. -def match_names(needed_names, available_names): - ret = [] - still_available_names = available_names - for needed in needed_names: - found = False - for i in range(len(still_available_names)): - available_name = still_available_names[i] - if available_name.find(needed) > -1: - ret.append(available_name) - still_available_names = still_available_names[i:] - found = True - break - if not found: - print("Could not find {0} in\n[{1}]".format(needed, ",\n".join(still_available_names)), file=sys.stderr) - assert False - return ret + with open(os.path.join(decoder_directory, "generator", "datafiles", "full-map.txt"), "r") as f: + return list(map(lambda pair: pair[1], filter(lambda pair: pair[0] in inums, map(inum_file_pair_from_line, f.readlines())))) def copy_instructions(full_names): for name in full_names: @@ -167,7 +130,7 @@ def make_single_file_definition(full_names): imports X86-FLAG-CHECKS-SYNTAX """ - epilogue = "endmodule" + epilogue = "endmodule" with open(single_file_definition, "w") as out_f: print(prologue, file=out_f) for name in full_names: @@ -179,10 +142,11 @@ def make_single_file_definition(full_names): def regenerate_semantics(inums): + assert len(inums) > 0 delete_old_instructions() - needed_names = get_instructions_from_inums(inums) - available_names = find_instructions() - full_names = match_names(needed_names, available_names) + full_names = get_instructions_from_inums(inums) + print(full_names) + assert len(full_names) > 0 copy_instructions(full_names) # This step is actually not necessary (we create the single file definition without using the copied files), but it's useful for debugging. make_single_file_definition(full_names) diff --git a/semantics/systemInstructions/jecxz_rel32.k b/semantics/systemInstructions/jecxz_rel32.k deleted file mode 100644 index cf80e86ad..000000000 --- a/semantics/systemInstructions/jecxz_rel32.k +++ /dev/null @@ -1,20 +0,0 @@ -requires "x86-configuration.k" - - -module JECXZ-REL32 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jecxz Imm32:Imm, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) - - requires eqMInt(getRegisterValue(%ecx, RSMap), mi(32, 0)) - - rule - execinstr (jecxz Imm32:Imm, .Operands) => . - ... - RSMap:Map - requires notBool eqMInt(getRegisterValue(%ecx, RSMap), mi(32, 0)) -endmodule diff --git a/semantics/systemInstructions/jrcxz_rel32.k b/semantics/systemInstructions/jrcxz_rel32.k deleted file mode 100644 index 21dd19c8b..000000000 --- a/semantics/systemInstructions/jrcxz_rel32.k +++ /dev/null @@ -1,20 +0,0 @@ -requires "x86-configuration.k" - - -module JRCXZ-REL32 - imports X86-CONFIGURATION - imports X86-FLAG-CHECS-SYNTAX - - rule - execinstr (jrcxz Imm32:Imm, .Operands) => . - ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) - - requires eqMInt(getRegisterValue(%rcx, RSMap), mi(64, 0)) - - rule - execinstr (jrcxz Imm32:Imm, .Operands) => . - ... - RSMap:Map - requires notBool eqMInt(getRegisterValue(%rcx, RSMap), mi(64, 0)) -endmodule From b3fb4fa4190b56d58730f2ebf7de6ac7833aaf59 Mon Sep 17 00:00:00 2001 From: andrew_miranti Date: Sat, 23 Feb 2019 23:13:08 -0600 Subject: [PATCH 10/15] New test case found issue with rel operands --- semantics/run-on-elf.py | 2 +- semantics/test.c | 44 +++++++++++++++++++---------------------- 2 files changed, 21 insertions(+), 25 deletions(-) diff --git a/semantics/run-on-elf.py b/semantics/run-on-elf.py index 0677fe01c..4d4528aea 100755 --- a/semantics/run-on-elf.py +++ b/semantics/run-on-elf.py @@ -171,7 +171,7 @@ def invoke_kompile(backend): def invoke_krun(elf_file, extra_args): - command = ["time", "krun", "--parser", parser_script, elf_file] + command = ["time", "krun", "-o", "none", "--parser", parser_script, elf_file] command.extend(extra_args) krun_process = subprocess.Popen(command, stdin=sys.stdin, stdout=sys.stdout, stderr=sys.stderr, cwd=definition_directory) await_process_or_interrupt("KRun", krun_process) diff --git a/semantics/test.c b/semantics/test.c index 7de787ad9..6fe0ec8c0 100644 --- a/semantics/test.c +++ b/semantics/test.c @@ -1,30 +1,26 @@ #include #include -int main() { - const int sz = 5; - int * a = (int*)malloc(sz*sizeof(int)); - for (int i = 0; i < sz; ++i) { - a[i] = i; - } - int * b = (int*)malloc(sz*sizeof(int)); - for (int i = 0; i < sz; ++i) { - b[i] = i; - } - for (int i = 0; i < sz; ++i) { - printf("%d\n", a[i]); - } - for (int i = 0; i < sz; ++i) { - printf("%d\n", b[i]); - } - free(a); - a = (int*)malloc(2*sz*sizeof(int)); - for (int i = 0; i < 2*sz; ++i) { - a[i] = 10*i; +size_t fib(const int n) { + if (n == 0) { + return 0; + } else if (n == 1) { + return 1; + } else { + size_t nums[n + 1]; + nums[0] = 0; + nums[1] = 1; + for (int i = 2; i <= n; ++i) { + nums[i] = nums[i - 1] + nums[i - 2]; + } + return nums[n]; } - for (int i = 0; i < sz; ++i) { - printf("%d\n", a[i]); +} + +const int elems[] = {0, 1, 5, 10, 20, 40}; + +int main() { + for (int i = 0; i < sizeof(elems) / sizeof(int); ++i) { + printf("%d: %lu\n", elems[i], fib(elems[i])); } - free(a); - free(b); } From a3bef8f91d8aaae01c863d35dae54588e1a6ae09 Mon Sep 17 00:00:00 2001 From: Sandeep Dasgupta Date: Mon, 25 Feb 2019 14:55:39 -0600 Subject: [PATCH 11/15] Convert Immediate operand from Int or hexconstant to MInt --- docs/z3_artifcats/array2.z3 | 11 ++++ docs/z3_artifcats/datatypes.z3 | 7 +++ .../immediateInstructions/adcb_al_imm8.k | 17 ++--- .../immediateInstructions/adcb_r8_imm8.k | 17 ++--- .../immediateInstructions/adcb_rh_imm8.k | 17 ++--- .../immediateInstructions/adcl_eax_imm32.k | 17 ++--- .../immediateInstructions/adcl_r32_imm32.k | 17 ++--- .../immediateInstructions/adcl_r32_imm8.k | 17 ++--- .../immediateInstructions/adcq_r64_imm32.k | 17 ++--- .../immediateInstructions/adcq_r64_imm8.k | 17 ++--- .../immediateInstructions/adcq_rax_imm32.k | 17 ++--- .../immediateInstructions/adcw_ax_imm16.k | 17 ++--- .../immediateInstructions/adcw_r16_imm16.k | 17 ++--- .../immediateInstructions/adcw_r16_imm8.k | 17 ++--- .../immediateInstructions/addb_al_imm8.k | 17 ++--- .../immediateInstructions/addb_r8_imm8.k | 17 ++--- .../immediateInstructions/addb_rh_imm8.k | 17 ++--- .../immediateInstructions/addl_eax_imm32.k | 17 ++--- .../immediateInstructions/addl_r32_imm32.k | 17 ++--- .../immediateInstructions/addl_r32_imm8.k | 17 ++--- .../immediateInstructions/addq_r64_imm32.k | 17 ++--- .../immediateInstructions/addq_r64_imm8.k | 17 ++--- .../immediateInstructions/addq_rax_imm32.k | 17 ++--- .../immediateInstructions/addw_ax_imm16.k | 17 ++--- .../immediateInstructions/addw_r16_imm16.k | 17 ++--- .../immediateInstructions/addw_r16_imm8.k | 17 ++--- .../immediateInstructions/andb_al_imm8.k | 11 ++-- .../immediateInstructions/andb_r8_imm8.k | 11 ++-- .../immediateInstructions/andb_rh_imm8.k | 11 ++-- .../immediateInstructions/andl_eax_imm32.k | 11 ++-- .../immediateInstructions/andl_r32_imm32.k | 11 ++-- .../immediateInstructions/andl_r32_imm8.k | 11 ++-- .../immediateInstructions/andq_r64_imm32.k | 11 ++-- .../immediateInstructions/andq_r64_imm8.k | 11 ++-- .../immediateInstructions/andq_rax_imm32.k | 11 ++-- .../immediateInstructions/andw_ax_imm16.k | 11 ++-- .../immediateInstructions/andw_r16_imm16.k | 11 ++-- .../immediateInstructions/andw_r16_imm8.k | 11 ++-- .../blendpd_xmm_xmm_imm8.k | 5 +- .../blendps_xmm_xmm_imm8.k | 5 +- .../immediateInstructions/btcl_r32_imm8.k | 7 ++- .../immediateInstructions/btcq_r64_imm8.k | 7 ++- .../immediateInstructions/btcw_r16_imm8.k | 7 ++- .../immediateInstructions/btl_r32_imm8.k | 5 +- .../immediateInstructions/btq_r64_imm8.k | 5 +- .../immediateInstructions/btrl_r32_imm8.k | 7 ++- .../immediateInstructions/btrq_r64_imm8.k | 7 ++- .../immediateInstructions/btrw_r16_imm8.k | 7 ++- .../immediateInstructions/btsl_r32_imm8.k | 7 ++- .../immediateInstructions/btsq_r64_imm8.k | 7 ++- .../immediateInstructions/btsw_r16_imm8.k | 7 ++- .../immediateInstructions/btw_r16_imm8.k | 5 +- .../immediateInstructions/cmpb_al_imm8.k | 15 ++--- .../immediateInstructions/cmpb_r8_imm8.k | 15 ++--- .../immediateInstructions/cmpb_rh_imm8.k | 15 ++--- .../immediateInstructions/cmpl_eax_imm32.k | 15 ++--- .../immediateInstructions/cmpl_r32_imm32.k | 15 ++--- .../immediateInstructions/cmpl_r32_imm8.k | 15 ++--- .../cmppd_xmm_xmm_imm8.k | 5 +- .../cmpps_xmm_xmm_imm8.k | 5 +- .../immediateInstructions/cmpq_r64_imm32.k | 15 ++--- .../immediateInstructions/cmpq_r64_imm8.k | 15 ++--- .../immediateInstructions/cmpq_rax_imm32.k | 15 ++--- .../cmpsd_xmm_xmm_imm8.k | 5 +- .../cmpss_xmm_xmm_imm8.k | 5 +- .../immediateInstructions/cmpw_ax_imm16.k | 15 ++--- .../immediateInstructions/cmpw_r16_imm16.k | 15 ++--- .../immediateInstructions/cmpw_r16_imm8.k | 15 ++--- .../immediateInstructions/dppd_xmm_xmm_imm8.k | 5 +- .../immediateInstructions/dpps_xmm_xmm_imm8.k | 5 +- .../extractps_r32_xmm_imm8.k | 5 +- .../extractps_r64_xmm_imm8.k | 5 +- .../imull_r32_r32_imm32.k | 9 +-- .../imull_r32_r32_imm8.k | 9 +-- .../imulq_r64_r64_imm32.k | 9 +-- .../imulq_r64_r64_imm8.k | 9 +-- .../imulw_r16_r16_imm16.k | 9 +-- .../imulw_r16_r16_imm8.k | 9 +-- .../insertps_xmm_xmm_imm8.k | 5 +- .../immediateInstructions/movb_r8_imm8.k | 5 +- .../immediateInstructions/movb_rh_imm8.k | 5 +- .../immediateInstructions/movl_r32_imm32.k | 5 +- .../immediateInstructions/movq_r64_imm32.k | 5 +- .../immediateInstructions/movq_r64_imm64.k | 5 +- .../immediateInstructions/movw_r16_imm16.k | 5 +- .../mpsadbw_xmm_xmm_imm8.k | 33 +++++----- semantics/immediateInstructions/orb_al_imm8.k | 11 ++-- semantics/immediateInstructions/orb_r8_imm8.k | 11 ++-- semantics/immediateInstructions/orb_rh_imm8.k | 11 ++-- .../immediateInstructions/orl_eax_imm32.k | 11 ++-- .../immediateInstructions/orl_r32_imm32.k | 11 ++-- .../immediateInstructions/orl_r32_imm8.k | 11 ++-- .../immediateInstructions/orq_r64_imm32.k | 11 ++-- .../immediateInstructions/orq_r64_imm8.k | 11 ++-- .../immediateInstructions/orq_rax_imm32.k | 11 ++-- .../immediateInstructions/orw_ax_imm16.k | 11 ++-- .../immediateInstructions/orw_r16_imm16.k | 11 ++-- .../immediateInstructions/orw_r16_imm8.k | 11 ++-- .../palignr_xmm_xmm_imm8.k | 5 +- .../pblendw_xmm_xmm_imm8.k | 5 +- .../pclmulqdq_xmm_xmm_imm8.k | 9 ++- .../pcmpestri_xmm_xmm_imm8.k | 9 +-- .../pcmpestrm_xmm_xmm_imm8.k | 9 +-- .../pcmpistri_xmm_xmm_imm8.k | 9 +-- .../pcmpistrm_xmm_xmm_imm8.k | 9 +-- .../pextrb_r32_xmm_imm8.k | 5 +- .../pextrb_r64_xmm_imm8.k | 5 +- .../pextrd_r32_xmm_imm8.k | 5 +- .../pextrq_r64_xmm_imm8.k | 5 +- .../pextrw_r32_xmm_imm8.k | 5 +- .../pextrw_r64_xmm_imm8.k | 5 +- .../pinsrb_xmm_r32_imm8.k | 5 +- .../pinsrd_xmm_r32_imm8.k | 5 +- .../pinsrq_xmm_r64_imm8.k | 5 +- .../pinsrw_xmm_r32_imm8.k | 5 +- .../pshufd_xmm_xmm_imm8.k | 5 +- .../pshufhw_xmm_xmm_imm8.k | 5 +- .../pshuflw_xmm_xmm_imm8.k | 5 +- .../immediateInstructions/pslld_xmm_imm8.k | 5 +- .../immediateInstructions/pslldq_xmm_imm8.k | 5 +- .../immediateInstructions/psllq_xmm_imm8.k | 5 +- .../immediateInstructions/psllw_xmm_imm8.k | 5 +- .../immediateInstructions/psrad_xmm_imm8.k | 5 +- .../immediateInstructions/psraw_xmm_imm8.k | 5 +- .../immediateInstructions/psrld_xmm_imm8.k | 5 +- .../immediateInstructions/psrldq_xmm_imm8.k | 5 +- .../immediateInstructions/psrlq_xmm_imm8.k | 5 +- .../immediateInstructions/psrlw_xmm_imm8.k | 5 +- semantics/immediateInstructions/pushq_imm32.k | 5 +- .../immediateInstructions/rclb_r8_imm8.k | 9 +-- .../immediateInstructions/rclb_rh_imm8.k | 9 +-- .../immediateInstructions/rcll_r32_imm8.k | 9 +-- .../immediateInstructions/rclq_r64_imm8.k | 9 +-- .../immediateInstructions/rclw_r16_imm8.k | 9 +-- .../immediateInstructions/rcrb_r8_imm8.k | 9 +-- .../immediateInstructions/rcrb_rh_imm8.k | 9 +-- .../immediateInstructions/rcrl_r32_imm8.k | 9 +-- .../immediateInstructions/rcrq_r64_imm8.k | 9 +-- .../immediateInstructions/rcrw_r16_imm8.k | 9 +-- .../immediateInstructions/rolb_r8_imm8.k | 9 +-- .../immediateInstructions/rolb_rh_imm8.k | 9 +-- .../immediateInstructions/roll_r32_imm8.k | 9 +-- .../immediateInstructions/rolq_r64_imm8.k | 9 +-- .../immediateInstructions/rolw_r16_imm8.k | 9 +-- .../immediateInstructions/rorb_r8_imm8.k | 9 +-- .../immediateInstructions/rorb_rh_imm8.k | 9 +-- .../immediateInstructions/rorl_r32_imm8.k | 9 +-- .../immediateInstructions/rorq_r64_imm8.k | 9 +-- .../immediateInstructions/rorw_r16_imm8.k | 9 +-- .../rorxl_r32_r32_imm8.k | 7 ++- .../rorxq_r64_r64_imm8.k | 7 ++- .../roundpd_xmm_xmm_imm8.k | 5 +- .../roundps_xmm_xmm_imm8.k | 5 +- .../roundsd_xmm_xmm_imm8.k | 5 +- .../roundss_xmm_xmm_imm8.k | 5 +- .../immediateInstructions/salb_r8_imm8.k | 17 ++--- .../immediateInstructions/salb_rh_imm8.k | 17 ++--- .../immediateInstructions/sall_r32_imm8.k | 17 ++--- .../immediateInstructions/salq_r64_imm8.k | 17 ++--- .../immediateInstructions/salw_r16_imm8.k | 17 ++--- .../immediateInstructions/sarb_r8_imm8.k | 17 ++--- .../immediateInstructions/sarb_rh_imm8.k | 17 ++--- .../immediateInstructions/sarl_r32_imm8.k | 17 ++--- .../immediateInstructions/sarq_r64_imm8.k | 17 ++--- .../immediateInstructions/sarw_r16_imm8.k | 17 ++--- .../immediateInstructions/sbbb_al_imm8.k | 17 ++--- .../immediateInstructions/sbbb_r8_imm8.k | 17 ++--- .../immediateInstructions/sbbb_rh_imm8.k | 17 ++--- .../immediateInstructions/sbbl_eax_imm32.k | 17 ++--- .../immediateInstructions/sbbl_r32_imm32.k | 17 ++--- .../immediateInstructions/sbbl_r32_imm8.k | 17 ++--- .../immediateInstructions/sbbq_r64_imm32.k | 17 ++--- .../immediateInstructions/sbbq_r64_imm8.k | 17 ++--- .../immediateInstructions/sbbq_rax_imm32.k | 17 ++--- .../immediateInstructions/sbbw_ax_imm16.k | 17 ++--- .../immediateInstructions/sbbw_r16_imm16.k | 17 ++--- .../immediateInstructions/sbbw_r16_imm8.k | 17 ++--- .../immediateInstructions/shlb_r8_imm8.k | 17 ++--- .../immediateInstructions/shlb_rh_imm8.k | 17 ++--- .../shldl_r32_r32_imm8.k | 5 +- .../shldq_r64_r64_imm8.k | 5 +- .../shldw_r16_r16_imm8.k | 5 +- .../immediateInstructions/shll_r32_imm8.k | 17 ++--- .../immediateInstructions/shlq_r64_imm8.k | 17 ++--- .../immediateInstructions/shlw_r16_imm8.k | 17 ++--- .../immediateInstructions/shrb_r8_imm8.k | 17 ++--- .../immediateInstructions/shrb_rh_imm8.k | 17 ++--- .../shrdl_r32_r32_imm8.k | 5 +- .../shrdq_r64_r64_imm8.k | 5 +- .../shrdw_r16_r16_imm8.k | 5 +- .../immediateInstructions/shrl_r32_imm8.k | 17 ++--- .../immediateInstructions/shrq_r64_imm8.k | 17 ++--- .../immediateInstructions/shrw_r16_imm8.k | 17 ++--- .../shufpd_xmm_xmm_imm8.k | 5 +- .../shufps_xmm_xmm_imm8.k | 5 +- .../immediateInstructions/subb_al_imm8.k | 17 ++--- .../immediateInstructions/subb_r8_imm8.k | 17 ++--- .../immediateInstructions/subb_rh_imm8.k | 17 ++--- .../immediateInstructions/subl_eax_imm32.k | 17 ++--- .../immediateInstructions/subl_r32_imm32.k | 17 ++--- .../immediateInstructions/subl_r32_imm8.k | 17 ++--- .../immediateInstructions/subq_r64_imm32.k | 17 ++--- .../immediateInstructions/subq_r64_imm8.k | 17 ++--- .../immediateInstructions/subq_rax_imm32.k | 17 ++--- .../immediateInstructions/subw_ax_imm16.k | 17 ++--- .../immediateInstructions/subw_r16_imm16.k | 17 ++--- .../immediateInstructions/subw_r16_imm8.k | 17 ++--- .../immediateInstructions/testb_al_imm8.k | 9 +-- .../immediateInstructions/testb_r8_imm8.k | 9 +-- .../immediateInstructions/testb_rh_imm8.k | 9 +-- .../immediateInstructions/testl_eax_imm32.k | 9 +-- .../immediateInstructions/testl_r32_imm32.k | 9 +-- .../immediateInstructions/testq_r64_imm32.k | 9 +-- .../immediateInstructions/testq_rax_imm32.k | 9 +-- .../immediateInstructions/testw_ax_imm16.k | 9 +-- .../immediateInstructions/testw_r16_imm16.k | 9 +-- .../vblendpd_xmm_xmm_xmm_imm8.k | 5 +- .../vblendpd_ymm_ymm_ymm_imm8.k | 5 +- .../vblendps_xmm_xmm_xmm_imm8.k | 5 +- .../vblendps_ymm_ymm_ymm_imm8.k | 5 +- .../vcmppd_xmm_xmm_xmm_imm8.k | 5 +- .../vcmppd_ymm_ymm_ymm_imm8.k | 5 +- .../vcmpps_xmm_xmm_xmm_imm8.k | 5 +- .../vcmpps_ymm_ymm_ymm_imm8.k | 5 +- .../vcmpsd_xmm_xmm_xmm_imm8.k | 5 +- .../vcmpss_xmm_xmm_xmm_imm8.k | 5 +- .../vcvtps2ph_xmm_xmm_imm8.k | 5 +- .../vcvtps2ph_xmm_ymm_imm8.k | 5 +- .../vdppd_xmm_xmm_xmm_imm8.k | 5 +- .../vdpps_xmm_xmm_xmm_imm8.k | 5 +- .../vdpps_ymm_ymm_ymm_imm8.k | 5 +- .../vextractf128_xmm_ymm_imm8.k | 5 +- .../vextracti128_xmm_ymm_imm8.k | 5 +- .../vextractps_r32_xmm_imm8.k | 5 +- .../vinsertf128_ymm_ymm_xmm_imm8.k | 5 +- .../vinserti128_ymm_ymm_xmm_imm8.k | 5 +- .../vinsertps_xmm_xmm_xmm_imm8.k | 5 +- .../vmpsadbw_xmm_xmm_xmm_imm8.k | 33 +++++----- .../vmpsadbw_ymm_ymm_ymm_imm8.k | 63 ++++++++++--------- .../vpalignr_xmm_xmm_xmm_imm8.k | 5 +- .../vpalignr_ymm_ymm_ymm_imm8.k | 5 +- .../vpblendd_xmm_xmm_xmm_imm8.k | 5 +- .../vpblendd_ymm_ymm_ymm_imm8.k | 5 +- .../vpblendw_xmm_xmm_xmm_imm8.k | 5 +- .../vpblendw_ymm_ymm_ymm_imm8.k | 5 +- .../vpclmulqdq_xmm_xmm_xmm_imm8.k | 9 ++- .../vpcmpestri_xmm_xmm_imm8.k | 9 +-- .../vpcmpestrm_xmm_xmm_imm8.k | 9 +-- .../vpcmpistri_xmm_xmm_imm8.k | 9 +-- .../vpcmpistrm_xmm_xmm_imm8.k | 9 +-- .../vperm2f128_ymm_ymm_ymm_imm8.k | 5 +- .../vperm2i128_ymm_ymm_ymm_imm8.k | 5 +- .../vpermilpd_xmm_xmm_imm8.k | 5 +- .../vpermilpd_ymm_ymm_imm8.k | 5 +- .../vpermilps_xmm_xmm_imm8.k | 5 +- .../vpermilps_ymm_ymm_imm8.k | 5 +- .../vpermpd_ymm_ymm_imm8.k | 5 +- .../vpermq_ymm_ymm_imm8.k | 5 +- .../vpextrb_r32_xmm_imm8.k | 5 +- .../vpextrb_r64_xmm_imm8.k | 5 +- .../vpextrd_r32_xmm_imm8.k | 5 +- .../vpextrq_r64_xmm_imm8.k | 5 +- .../vpextrw_r32_xmm_imm8.k | 5 +- .../vpextrw_r64_xmm_imm8.k | 5 +- .../vpinsrb_xmm_xmm_r32_imm8.k | 5 +- .../vpinsrd_xmm_xmm_r32_imm8.k | 5 +- .../vpinsrq_xmm_xmm_r64_imm8.k | 5 +- .../vpinsrw_xmm_xmm_r32_imm8.k | 5 +- .../vpshufd_xmm_xmm_imm8.k | 5 +- .../vpshufd_ymm_ymm_imm8.k | 5 +- .../vpshufhw_xmm_xmm_imm8.k | 5 +- .../vpshufhw_ymm_ymm_imm8.k | 5 +- .../vpshuflw_xmm_xmm_imm8.k | 5 +- .../vpshuflw_ymm_ymm_imm8.k | 5 +- .../vpslld_xmm_xmm_imm8.k | 5 +- .../vpslld_ymm_ymm_imm8.k | 5 +- .../vpslldq_xmm_xmm_imm8.k | 5 +- .../vpslldq_ymm_ymm_imm8.k | 5 +- .../vpsllq_xmm_xmm_imm8.k | 5 +- .../vpsllq_ymm_ymm_imm8.k | 5 +- .../vpsllw_xmm_xmm_imm8.k | 5 +- .../vpsllw_ymm_ymm_imm8.k | 5 +- .../vpsrad_xmm_xmm_imm8.k | 5 +- .../vpsrad_ymm_ymm_imm8.k | 5 +- .../vpsraw_xmm_xmm_imm8.k | 5 +- .../vpsraw_ymm_ymm_imm8.k | 5 +- .../vpsrld_xmm_xmm_imm8.k | 5 +- .../vpsrld_ymm_ymm_imm8.k | 5 +- .../vpsrldq_xmm_xmm_imm8.k | 5 +- .../vpsrldq_ymm_ymm_imm8.k | 5 +- .../vpsrlq_xmm_xmm_imm8.k | 5 +- .../vpsrlq_ymm_ymm_imm8.k | 5 +- .../vpsrlw_xmm_xmm_imm8.k | 5 +- .../vpsrlw_ymm_ymm_imm8.k | 5 +- .../vroundpd_xmm_xmm_imm8.k | 5 +- .../vroundpd_ymm_ymm_imm8.k | 5 +- .../vroundps_xmm_xmm_imm8.k | 5 +- .../vroundps_ymm_ymm_imm8.k | 5 +- .../vroundsd_xmm_xmm_xmm_imm8.k | 5 +- .../vroundss_xmm_xmm_xmm_imm8.k | 5 +- .../vshufpd_xmm_xmm_xmm_imm8.k | 5 +- .../vshufpd_ymm_ymm_ymm_imm8.k | 5 +- .../vshufps_xmm_xmm_xmm_imm8.k | 5 +- .../vshufps_ymm_ymm_ymm_imm8.k | 5 +- .../immediateInstructions/xorb_al_imm8.k | 11 ++-- .../immediateInstructions/xorb_r8_imm8.k | 11 ++-- .../immediateInstructions/xorb_rh_imm8.k | 11 ++-- .../immediateInstructions/xorl_eax_imm32.k | 11 ++-- .../immediateInstructions/xorl_r32_imm32.k | 11 ++-- .../immediateInstructions/xorl_r32_imm8.k | 11 ++-- .../immediateInstructions/xorq_r64_imm32.k | 11 ++-- .../immediateInstructions/xorq_r64_imm8.k | 11 ++-- .../immediateInstructions/xorq_rax_imm32.k | 11 ++-- .../immediateInstructions/xorw_ax_imm16.k | 11 ++-- .../immediateInstructions/xorw_r16_imm16.k | 11 ++-- .../immediateInstructions/xorw_r16_imm8.k | 11 ++-- semantics/memoryInstructions/adcb_m8_imm8.k | 22 ++++--- semantics/memoryInstructions/adcl_m32_imm32.k | 22 ++++--- semantics/memoryInstructions/adcl_m32_imm8.k | 22 ++++--- semantics/memoryInstructions/adcq_m64_imm32.k | 22 ++++--- semantics/memoryInstructions/adcq_m64_imm8.k | 22 ++++--- semantics/memoryInstructions/adcw_m16_imm16.k | 22 ++++--- semantics/memoryInstructions/adcw_m16_imm8.k | 22 ++++--- semantics/memoryInstructions/addb_m8_imm8.k | 22 ++++--- semantics/memoryInstructions/addl_m32_imm32.k | 22 ++++--- semantics/memoryInstructions/addl_m32_imm8.k | 22 ++++--- semantics/memoryInstructions/addq_m64_imm32.k | 22 ++++--- semantics/memoryInstructions/addq_m64_imm8.k | 22 ++++--- semantics/memoryInstructions/addw_m16_imm16.k | 22 ++++--- semantics/memoryInstructions/addw_m16_imm8.k | 22 ++++--- semantics/memoryInstructions/andb_m8_imm8.k | 16 ++--- semantics/memoryInstructions/andl_m32_imm32.k | 16 ++--- semantics/memoryInstructions/andl_m32_imm8.k | 16 ++--- semantics/memoryInstructions/andq_m64_imm32.k | 16 ++--- semantics/memoryInstructions/andq_m64_imm8.k | 16 ++--- semantics/memoryInstructions/andw_m16_imm16.k | 16 ++--- semantics/memoryInstructions/andw_m16_imm8.k | 16 ++--- .../blendpd_xmm_m128_imm8.k | 10 +-- .../blendps_xmm_m128_imm8.k | 10 +-- semantics/memoryInstructions/btcl_m32_imm8.k | 16 ++--- semantics/memoryInstructions/btcq_m64_imm8.k | 16 ++--- semantics/memoryInstructions/btcw_m16_imm8.k | 16 ++--- semantics/memoryInstructions/btl_m32_imm8.k | 12 ++-- semantics/memoryInstructions/btq_m64_imm8.k | 12 ++-- semantics/memoryInstructions/btrl_m32_imm8.k | 16 ++--- semantics/memoryInstructions/btrq_m64_imm8.k | 16 ++--- semantics/memoryInstructions/btrw_m16_imm8.k | 16 ++--- semantics/memoryInstructions/btsl_m32_imm8.k | 16 ++--- semantics/memoryInstructions/btsq_m64_imm8.k | 16 ++--- semantics/memoryInstructions/btsw_m16_imm8.k | 16 ++--- semantics/memoryInstructions/btw_m16_imm8.k | 12 ++-- semantics/memoryInstructions/cmpb_m8_imm8.k | 20 +++--- semantics/memoryInstructions/cmpl_m32_imm32.k | 20 +++--- semantics/memoryInstructions/cmpl_m32_imm8.k | 20 +++--- .../memoryInstructions/cmppd_xmm_m128_imm8.k | 10 +-- .../memoryInstructions/cmpps_xmm_m128_imm8.k | 10 +-- semantics/memoryInstructions/cmpq_m64_imm32.k | 20 +++--- semantics/memoryInstructions/cmpq_m64_imm8.k | 20 +++--- .../memoryInstructions/cmpsd_xmm_m64_imm8.k | 10 +-- .../memoryInstructions/cmpss_xmm_m32_imm8.k | 10 +-- semantics/memoryInstructions/cmpw_m16_imm16.k | 20 +++--- semantics/memoryInstructions/cmpw_m16_imm8.k | 20 +++--- .../memoryInstructions/dppd_xmm_m128_imm8.k | 10 +-- .../memoryInstructions/dpps_xmm_m128_imm8.k | 10 +-- .../extractps_m32_xmm_imm8.k | 10 +-- .../memoryInstructions/imull_r32_m32_imm32.k | 14 +++-- .../memoryInstructions/imull_r32_m32_imm8.k | 14 +++-- .../memoryInstructions/imulq_r64_m64_imm32.k | 14 +++-- .../memoryInstructions/imulq_r64_m64_imm8.k | 14 +++-- .../memoryInstructions/imulw_r16_m16_imm16.k | 14 +++-- .../memoryInstructions/imulw_r16_m16_imm8.k | 14 +++-- .../insertps_xmm_m32_imm8.k | 10 +-- semantics/memoryInstructions/movb_m8_imm8.k | 7 ++- semantics/memoryInstructions/movl_m32_imm32.k | 7 ++- semantics/memoryInstructions/movq_m64_imm32.k | 7 ++- semantics/memoryInstructions/movw_m16_imm16.k | 7 ++- .../mpsadbw_xmm_m128_imm8.k | 33 +++++----- semantics/memoryInstructions/orb_m8_imm8.k | 16 ++--- semantics/memoryInstructions/orl_m32_imm32.k | 16 ++--- semantics/memoryInstructions/orl_m32_imm8.k | 16 ++--- semantics/memoryInstructions/orq_m64_imm32.k | 16 ++--- semantics/memoryInstructions/orq_m64_imm8.k | 16 ++--- semantics/memoryInstructions/orw_m16_imm16.k | 16 ++--- semantics/memoryInstructions/orw_m16_imm8.k | 16 ++--- .../palignr_xmm_m128_imm8.k | 10 +-- .../pblendw_xmm_m128_imm8.k | 10 +-- .../pclmulqdq_xmm_m128_imm8.k | 9 ++- .../pcmpestri_xmm_m128_imm8.k | 15 ++--- .../pcmpestrm_xmm_m128_imm8.k | 13 ++-- .../pcmpistri_xmm_m128_imm8.k | 15 ++--- .../pcmpistrm_xmm_m128_imm8.k | 14 +++-- .../memoryInstructions/pextrb_m8_xmm_imm8.k | 10 +-- .../memoryInstructions/pextrd_m32_xmm_imm8.k | 10 +-- .../memoryInstructions/pextrq_m64_xmm_imm8.k | 10 +-- .../memoryInstructions/pextrw_m16_xmm_imm8.k | 10 +-- .../memoryInstructions/pinsrb_xmm_m8_imm8.k | 10 +-- .../memoryInstructions/pinsrd_xmm_m32_imm8.k | 10 +-- .../memoryInstructions/pinsrq_xmm_m64_imm8.k | 10 +-- .../memoryInstructions/pinsrw_xmm_m16_imm8.k | 10 +-- .../memoryInstructions/pshufd_xmm_m128_imm8.k | 10 +-- .../pshufhw_xmm_m128_imm8.k | 10 +-- .../pshuflw_xmm_m128_imm8.k | 10 +-- semantics/memoryInstructions/rclb_m8_imm8.k | 14 +++-- semantics/memoryInstructions/rcll_m32_imm8.k | 14 +++-- semantics/memoryInstructions/rclq_m64_imm8.k | 14 +++-- semantics/memoryInstructions/rclw_m16_imm8.k | 14 +++-- semantics/memoryInstructions/rcrb_m8_imm8.k | 14 +++-- semantics/memoryInstructions/rcrl_m32_imm8.k | 14 +++-- semantics/memoryInstructions/rcrq_m64_imm8.k | 14 +++-- semantics/memoryInstructions/rcrw_m16_imm8.k | 14 +++-- semantics/memoryInstructions/rolb_m8_imm8.k | 14 +++-- semantics/memoryInstructions/roll_m32_imm8.k | 14 +++-- semantics/memoryInstructions/rolq_m64_imm8.k | 14 +++-- semantics/memoryInstructions/rolw_m16_imm8.k | 14 +++-- semantics/memoryInstructions/rorb_m8_imm8.k | 14 +++-- semantics/memoryInstructions/rorl_m32_imm8.k | 14 +++-- semantics/memoryInstructions/rorq_m64_imm8.k | 14 +++-- semantics/memoryInstructions/rorw_m16_imm8.k | 14 +++-- .../memoryInstructions/rorxl_r32_m32_imm8.k | 12 ++-- .../memoryInstructions/rorxq_r64_m64_imm8.k | 12 ++-- .../roundpd_xmm_m128_imm8.k | 10 +-- .../roundps_xmm_m128_imm8.k | 10 +-- .../memoryInstructions/roundsd_xmm_m64_imm8.k | 10 +-- .../memoryInstructions/roundss_xmm_m32_imm8.k | 10 +-- semantics/memoryInstructions/salb_m8_imm8.k | 22 ++++--- semantics/memoryInstructions/sall_m32_imm8.k | 22 ++++--- semantics/memoryInstructions/salq_m64_imm8.k | 22 ++++--- semantics/memoryInstructions/salw_m16_imm8.k | 22 ++++--- semantics/memoryInstructions/sarb_m8_imm8.k | 22 ++++--- semantics/memoryInstructions/sarl_m32_imm8.k | 22 ++++--- semantics/memoryInstructions/sarq_m64_imm8.k | 22 ++++--- semantics/memoryInstructions/sarw_m16_imm8.k | 22 ++++--- semantics/memoryInstructions/sbbb_m8_imm8.k | 22 ++++--- semantics/memoryInstructions/sbbl_m32_imm32.k | 22 ++++--- semantics/memoryInstructions/sbbl_m32_imm8.k | 22 ++++--- semantics/memoryInstructions/sbbq_m64_imm32.k | 22 ++++--- semantics/memoryInstructions/sbbq_m64_imm8.k | 22 ++++--- semantics/memoryInstructions/sbbw_m16_imm16.k | 22 ++++--- semantics/memoryInstructions/sbbw_m16_imm8.k | 22 ++++--- semantics/memoryInstructions/shlb_m8_imm8.k | 22 ++++--- .../memoryInstructions/shldl_m32_r32_imm8.k | 12 ++-- .../memoryInstructions/shldq_m64_r64_imm8.k | 12 ++-- .../memoryInstructions/shldw_m16_r16_imm8.k | 12 ++-- semantics/memoryInstructions/shll_m32_imm8.k | 22 ++++--- semantics/memoryInstructions/shlq_m64_imm8.k | 22 ++++--- semantics/memoryInstructions/shlw_m16_imm8.k | 22 ++++--- semantics/memoryInstructions/shrb_m8_imm8.k | 22 ++++--- .../memoryInstructions/shrdl_m32_r32_imm8.k | 12 ++-- .../memoryInstructions/shrdq_m64_r64_imm8.k | 12 ++-- .../memoryInstructions/shrdw_m16_r16_imm8.k | 12 ++-- semantics/memoryInstructions/shrl_m32_imm8.k | 22 ++++--- semantics/memoryInstructions/shrq_m64_imm8.k | 22 ++++--- semantics/memoryInstructions/shrw_m16_imm8.k | 22 ++++--- .../memoryInstructions/shufpd_xmm_m128_imm8.k | 10 +-- .../memoryInstructions/shufps_xmm_m128_imm8.k | 10 +-- semantics/memoryInstructions/subb_m8_imm8.k | 22 ++++--- semantics/memoryInstructions/subl_m32_imm32.k | 22 ++++--- semantics/memoryInstructions/subl_m32_imm8.k | 22 ++++--- semantics/memoryInstructions/subq_m64_imm32.k | 22 ++++--- semantics/memoryInstructions/subq_m64_imm8.k | 22 ++++--- semantics/memoryInstructions/subw_m16_imm16.k | 22 ++++--- semantics/memoryInstructions/subw_m16_imm8.k | 22 ++++--- semantics/memoryInstructions/testb_m8_imm8.k | 14 +++-- .../memoryInstructions/testl_m32_imm32.k | 14 +++-- .../memoryInstructions/testq_m64_imm32.k | 14 +++-- .../memoryInstructions/testw_m16_imm16.k | 14 +++-- .../vblendpd_xmm_xmm_m128_imm8.k | 10 +-- .../vblendpd_ymm_ymm_m256_imm8.k | 10 +-- .../vblendps_xmm_xmm_m128_imm8.k | 10 +-- .../vblendps_ymm_ymm_m256_imm8.k | 10 +-- .../vcmppd_xmm_xmm_m128_imm8.k | 10 +-- .../vcmppd_ymm_ymm_m256_imm8.k | 10 +-- .../vcmpps_xmm_xmm_m128_imm8.k | 10 +-- .../vcmpps_ymm_ymm_m256_imm8.k | 10 +-- .../vcmpsd_xmm_xmm_m64_imm8.k | 10 +-- .../vcmpss_xmm_xmm_m32_imm8.k | 10 +-- .../vcvtps2ph_m128_ymm_imm8.k | 10 +-- .../vcvtps2ph_m64_xmm_imm8.k | 10 +-- .../vdppd_xmm_xmm_m128_imm8.k | 10 +-- .../vdpps_xmm_xmm_m128_imm8.k | 10 +-- .../vdpps_ymm_ymm_m256_imm8.k | 10 +-- .../vextractf128_m128_ymm_imm8.k | 10 +-- .../vextracti128_m128_ymm_imm8.k | 10 +-- .../vextractps_m32_xmm_imm8.k | 10 +-- .../vinsertf128_ymm_ymm_m128_imm8.k | 10 +-- .../vinserti128_ymm_ymm_m128_imm8.k | 10 +-- .../vinsertps_xmm_xmm_m32_imm8.k | 10 +-- .../vmpsadbw_xmm_xmm_m128_imm8.k | 33 +++++----- .../vmpsadbw_ymm_ymm_m256_imm8.k | 63 ++++++++++--------- .../vpalignr_xmm_xmm_m128_imm8.k | 10 +-- .../vpalignr_ymm_ymm_m256_imm8.k | 10 +-- .../vpblendd_xmm_xmm_m128_imm8.k | 10 +-- .../vpblendd_ymm_ymm_m256_imm8.k | 10 +-- .../vpblendw_xmm_xmm_m128_imm8.k | 10 +-- .../vpblendw_ymm_ymm_m256_imm8.k | 10 +-- .../vpclmulqdq_xmm_xmm_m128_imm8.k | 9 ++- .../vpcmpestri_xmm_m128_imm8.k | 15 ++--- .../vpcmpestrm_xmm_m128_imm8.k | 13 ++-- .../vpcmpistri_xmm_m128_imm8.k | 15 ++--- .../vpcmpistrm_xmm_m128_imm8.k | 14 +++-- .../vperm2f128_ymm_ymm_m256_imm8.k | 10 +-- .../vperm2i128_ymm_ymm_m256_imm8.k | 10 +-- .../vpermilpd_xmm_m128_imm8.k | 10 +-- .../vpermilpd_ymm_m256_imm8.k | 10 +-- .../vpermilps_xmm_m128_imm8.k | 10 +-- .../vpermilps_ymm_m256_imm8.k | 10 +-- .../vpermpd_ymm_m256_imm8.k | 10 +-- .../memoryInstructions/vpermq_ymm_m256_imm8.k | 10 +-- .../memoryInstructions/vpextrb_m8_xmm_imm8.k | 10 +-- .../memoryInstructions/vpextrd_m32_xmm_imm8.k | 10 +-- .../memoryInstructions/vpextrq_m64_xmm_imm8.k | 10 +-- .../memoryInstructions/vpextrw_m16_xmm_imm8.k | 10 +-- .../vpinsrb_xmm_xmm_m8_imm8.k | 10 +-- .../vpinsrd_xmm_xmm_m32_imm8.k | 10 +-- .../vpinsrq_xmm_xmm_m64_imm8.k | 10 +-- .../vpinsrw_xmm_xmm_m16_imm8.k | 10 +-- .../vpshufd_xmm_m128_imm8.k | 10 +-- .../vpshufd_ymm_m256_imm8.k | 10 +-- .../vpshufhw_xmm_m128_imm8.k | 10 +-- .../vpshufhw_ymm_m256_imm8.k | 10 +-- .../vpshuflw_xmm_m128_imm8.k | 10 +-- .../vpshuflw_ymm_m256_imm8.k | 10 +-- .../vroundpd_xmm_m128_imm8.k | 10 +-- .../vroundpd_ymm_m256_imm8.k | 10 +-- .../vroundps_xmm_m128_imm8.k | 10 +-- .../vroundps_ymm_m256_imm8.k | 10 +-- .../vroundsd_xmm_xmm_m64_imm8.k | 10 +-- .../vroundss_xmm_xmm_m32_imm8.k | 10 +-- .../vshufpd_xmm_xmm_m128_imm8.k | 10 +-- .../vshufpd_ymm_ymm_m256_imm8.k | 10 +-- .../vshufps_xmm_xmm_m128_imm8.k | 10 +-- .../vshufps_ymm_ymm_m256_imm8.k | 10 +-- semantics/memoryInstructions/xorb_m8_imm8.k | 16 ++--- semantics/memoryInstructions/xorl_m32_imm32.k | 16 ++--- semantics/memoryInstructions/xorl_m32_imm8.k | 16 ++--- semantics/memoryInstructions/xorq_m64_imm32.k | 16 ++--- semantics/memoryInstructions/xorq_m64_imm8.k | 16 ++--- semantics/memoryInstructions/xorw_m16_imm16.k | 16 ++--- semantics/memoryInstructions/xorw_m16_imm8.k | 16 ++--- semantics/registerInstructions/pushq_imm32.k | 22 ------- semantics/registerInstructions/roll_r32_one.k | 39 +++++------- semantics/systemInstructions/callq_rel32.k | 12 ++-- semantics/systemInstructions/ja_rel32.k | 13 +++- semantics/systemInstructions/ja_rel8.k | 17 ++--- semantics/systemInstructions/jae_rel32.k | 12 ++-- semantics/systemInstructions/jae_rel8.k | 12 ++-- semantics/systemInstructions/jb_rel32.k | 12 ++-- semantics/systemInstructions/jb_rel8.k | 12 ++-- semantics/systemInstructions/jbe_rel32.k | 16 ++--- semantics/systemInstructions/jbe_rel8.k | 16 ++--- semantics/systemInstructions/jc_rel32.k | 12 ++-- semantics/systemInstructions/jc_rel8.k | 12 ++-- semantics/systemInstructions/je_rel32.k | 12 ++-- semantics/systemInstructions/je_rel8.k | 12 ++-- semantics/systemInstructions/jecxz_rel8.k | 12 ++-- semantics/systemInstructions/jg_rel32.k | 16 ++--- semantics/systemInstructions/jg_rel8.k | 16 ++--- semantics/systemInstructions/jge_rel32.k | 12 ++-- semantics/systemInstructions/jge_rel8.k | 12 ++-- semantics/systemInstructions/jl_rel32.k | 12 ++-- semantics/systemInstructions/jl_rel8.k | 12 ++-- semantics/systemInstructions/jle_rel32.k | 16 ++--- semantics/systemInstructions/jle_rel8.k | 16 ++--- semantics/systemInstructions/jmp_rel32.k | 5 +- semantics/systemInstructions/jmp_rel8.k | 5 +- semantics/systemInstructions/jna_rel32.k | 14 +++-- semantics/systemInstructions/jna_rel8.k | 14 +++-- semantics/systemInstructions/jnae_rel32.k | 12 ++-- semantics/systemInstructions/jnae_rel8.k | 12 ++-- semantics/systemInstructions/jnb_rel32.k | 12 ++-- semantics/systemInstructions/jnb_rel8.k | 12 ++-- semantics/systemInstructions/jnbe_rel32.k | 16 ++--- semantics/systemInstructions/jnbe_rel8.k | 16 ++--- semantics/systemInstructions/jnc_rel32.k | 12 ++-- semantics/systemInstructions/jnc_rel8.k | 12 ++-- semantics/systemInstructions/jne_rel32.k | 12 ++-- semantics/systemInstructions/jne_rel8.k | 12 ++-- semantics/systemInstructions/jng_rel32.k | 12 ++-- semantics/systemInstructions/jng_rel8.k | 12 ++-- semantics/systemInstructions/jnge_rel32.k | 12 ++-- semantics/systemInstructions/jnge_rel8.k | 12 ++-- semantics/systemInstructions/jnl_rel32.k | 12 ++-- semantics/systemInstructions/jnl_rel8.k | 12 ++-- semantics/systemInstructions/jnle_rel32.k | 12 ++-- semantics/systemInstructions/jnle_rel8.k | 12 ++-- semantics/systemInstructions/jno_rel32.k | 12 ++-- semantics/systemInstructions/jno_rel8.k | 12 ++-- semantics/systemInstructions/jnp_rel32.k | 12 ++-- semantics/systemInstructions/jnp_rel8.k | 12 ++-- semantics/systemInstructions/jns_rel32.k | 12 ++-- semantics/systemInstructions/jns_rel8.k | 12 ++-- semantics/systemInstructions/jnz_rel32.k | 12 ++-- semantics/systemInstructions/jnz_rel8.k | 12 ++-- semantics/systemInstructions/jo_rel32.k | 12 ++-- semantics/systemInstructions/jo_rel8.k | 12 ++-- semantics/systemInstructions/jp_rel32.k | 12 ++-- semantics/systemInstructions/jp_rel8.k | 12 ++-- semantics/systemInstructions/jpe_rel32.k | 12 ++-- semantics/systemInstructions/jpe_rel8.k | 12 ++-- semantics/systemInstructions/jpo_rel32.k | 12 ++-- semantics/systemInstructions/jpo_rel8.k | 12 ++-- semantics/systemInstructions/jrcxz_rel8.k | 12 ++-- semantics/systemInstructions/js_rel32.k | 12 ++-- semantics/systemInstructions/js_rel8.k | 12 ++-- semantics/systemInstructions/jz_rel32.k | 12 ++-- semantics/systemInstructions/jz_rel8.k | 12 ++-- semantics/systemInstructions/loop_rel8.k | 15 +++-- semantics/systemInstructions/loope_rel8.k | 19 +++--- semantics/systemInstructions/loopne_rel8.k | 19 +++--- semantics/systemInstructions/loopnz_rel8.k | 19 +++--- semantics/systemInstructions/loopz_rel8.k | 19 +++--- 611 files changed, 4069 insertions(+), 3200 deletions(-) create mode 100644 docs/z3_artifcats/array2.z3 create mode 100644 docs/z3_artifcats/datatypes.z3 delete mode 100644 semantics/registerInstructions/pushq_imm32.k diff --git a/docs/z3_artifcats/array2.z3 b/docs/z3_artifcats/array2.z3 new file mode 100644 index 000000000..ce19c7f46 --- /dev/null +++ b/docs/z3_artifcats/array2.z3 @@ -0,0 +1,11 @@ +(declare-const x Int) +(declare-const y Int) +(declare-const z Int) +(declare-const a1 (Array Int Int)) +(declare-const a2 (Array Int Int)) +(declare-const a3 (Array Int Int)) +(assert (= (select a1 x) x)) +(assert (= (store a1 x y) a1)) +(assert (not (= x y))) +(check-sat) +(get-model) diff --git a/docs/z3_artifcats/datatypes.z3 b/docs/z3_artifcats/datatypes.z3 new file mode 100644 index 000000000..2792deac9 --- /dev/null +++ b/docs/z3_artifcats/datatypes.z3 @@ -0,0 +1,7 @@ +(declare-datatypes (T1 T2) ((Pair (mk-pair (first T1) (second T2))))) +(declare-const p1 (Pair Int Int)) +(declare-const p2 (Pair Int Int)) +(assert (= p1 p2)) +(assert (> (second p1) 20)) +(check-sat) +(get-model) diff --git a/semantics/immediateInstructions/adcb_al_imm8.k b/semantics/immediateInstructions/adcb_al_imm8.k index 28521ea90..d1db6c394 100644 --- a/semantics/immediateInstructions/adcb_al_imm8.k +++ b/semantics/immediateInstructions/adcb_al_imm8.k @@ -5,26 +5,27 @@ module ADCB-AL-IMM8 imports X86-CONFIGURATION rule - execinstr (adcb Imm8:Imm, %al, .Operands) => . + execinstr (adcb Imm8:MInt, %al, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 56), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9)) +"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 56), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9)) -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/adcb_r8_imm8.k b/semantics/immediateInstructions/adcb_r8_imm8.k index 0eeaf0432..f65368f92 100644 --- a/semantics/immediateInstructions/adcb_r8_imm8.k +++ b/semantics/immediateInstructions/adcb_r8_imm8.k @@ -5,26 +5,27 @@ module ADCB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (adcb Imm8:Imm, R2:R8, .Operands) => . + execinstr (adcb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9)) -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/adcb_rh_imm8.k b/semantics/immediateInstructions/adcb_rh_imm8.k index a025b0120..f8b919377 100644 --- a/semantics/immediateInstructions/adcb_rh_imm8.k +++ b/semantics/immediateInstructions/adcb_rh_imm8.k @@ -5,26 +5,27 @@ module ADCB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (adcb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (adcb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 51, 52)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 51, 52)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/adcl_eax_imm32.k b/semantics/immediateInstructions/adcl_eax_imm32.k index b117c8ec5..86f4bcd28 100644 --- a/semantics/immediateInstructions/adcl_eax_imm32.k +++ b/semantics/immediateInstructions/adcl_eax_imm32.k @@ -5,26 +5,27 @@ module ADCL-EAX-IMM32 imports X86-CONFIGURATION rule - execinstr (adcl Imm32:Imm, %eax, .Operands) => . + execinstr (adcl Imm32:MInt, %eax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33)) +"RAX" |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33)) -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm32, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm32, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/adcl_r32_imm32.k b/semantics/immediateInstructions/adcl_r32_imm32.k index 14427f729..c9255bd51 100644 --- a/semantics/immediateInstructions/adcl_r32_imm32.k +++ b/semantics/immediateInstructions/adcl_r32_imm32.k @@ -5,26 +5,27 @@ module ADCL-R32-IMM32 imports X86-CONFIGURATION rule - execinstr (adcl Imm32:Imm, R2:R32, .Operands) => . + execinstr (adcl Imm32:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm32, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm32, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/adcl_r32_imm8.k b/semantics/immediateInstructions/adcl_r32_imm8.k index 5e6491637..c499ab214 100644 --- a/semantics/immediateInstructions/adcl_r32_imm8.k +++ b/semantics/immediateInstructions/adcl_r32_imm8.k @@ -5,26 +5,27 @@ module ADCL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (adcl Imm8:Imm, R2:R32, .Operands) => . + execinstr (adcl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/adcq_r64_imm32.k b/semantics/immediateInstructions/adcq_r64_imm32.k index 26791db3c..03716b33c 100644 --- a/semantics/immediateInstructions/adcq_r64_imm32.k +++ b/semantics/immediateInstructions/adcq_r64_imm32.k @@ -5,26 +5,27 @@ module ADCQ-R64-IMM32 imports X86-CONFIGURATION rule - execinstr (adcq Imm32:Imm, R2:R64, .Operands) => . + execinstr (adcq Imm32:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) +convToRegKeys(R2) |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/adcq_r64_imm8.k b/semantics/immediateInstructions/adcq_r64_imm8.k index e7163a91a..75584ef82 100644 --- a/semantics/immediateInstructions/adcq_r64_imm8.k +++ b/semantics/immediateInstructions/adcq_r64_imm8.k @@ -5,26 +5,27 @@ module ADCQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (adcq Imm8:Imm, R2:R64, .Operands) => . + execinstr (adcq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) +convToRegKeys(R2) |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/adcq_rax_imm32.k b/semantics/immediateInstructions/adcq_rax_imm32.k index 606ca2b44..b289e48e7 100644 --- a/semantics/immediateInstructions/adcq_rax_imm32.k +++ b/semantics/immediateInstructions/adcq_rax_imm32.k @@ -5,26 +5,27 @@ module ADCQ-RAX-IMM32 imports X86-CONFIGURATION rule - execinstr (adcq Imm32:Imm, %rax, .Operands) => . + execinstr (adcq Imm32:MInt, %rax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65) +"RAX" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65) -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/adcw_ax_imm16.k b/semantics/immediateInstructions/adcw_ax_imm16.k index a0769e94b..5afbf0b28 100644 --- a/semantics/immediateInstructions/adcw_ax_imm16.k +++ b/semantics/immediateInstructions/adcw_ax_imm16.k @@ -5,26 +5,27 @@ module ADCW-AX-IMM16 imports X86-CONFIGURATION rule - execinstr (adcw Imm16:Imm, %ax, .Operands) => . + execinstr (adcw Imm16:MInt, %ax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17)) +"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17)) -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm16, 11, 12), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm16, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm16, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/adcw_r16_imm16.k b/semantics/immediateInstructions/adcw_r16_imm16.k index 4b27cbf13..0af492233 100644 --- a/semantics/immediateInstructions/adcw_r16_imm16.k +++ b/semantics/immediateInstructions/adcw_r16_imm16.k @@ -5,26 +5,27 @@ module ADCW-R16-IMM16 imports X86-CONFIGURATION rule - execinstr (adcw Imm16:Imm, R2:R16, .Operands) => . + execinstr (adcw Imm16:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm16, 11, 12), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm16, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm16, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/adcw_r16_imm8.k b/semantics/immediateInstructions/adcw_r16_imm8.k index 15a937d48..78e8a17b6 100644 --- a/semantics/immediateInstructions/adcw_r16_imm8.k +++ b/semantics/immediateInstructions/adcw_r16_imm8.k @@ -5,26 +5,27 @@ module ADCW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (adcw Imm8:Imm, R2:R16, .Operands) => . + execinstr (adcw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/addb_al_imm8.k b/semantics/immediateInstructions/addb_al_imm8.k index 98c0a035b..1c5345128 100644 --- a/semantics/immediateInstructions/addb_al_imm8.k +++ b/semantics/immediateInstructions/addb_al_imm8.k @@ -5,26 +5,27 @@ module ADDB-AL-IMM8 imports X86-CONFIGURATION rule - execinstr (addb Imm8:Imm, %al, .Operands) => . + execinstr (addb Imm8:MInt, %al, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 56), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9)) +"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 56), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9)) -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/addb_r8_imm8.k b/semantics/immediateInstructions/addb_r8_imm8.k index 5dc756dbc..d20c14542 100644 --- a/semantics/immediateInstructions/addb_r8_imm8.k +++ b/semantics/immediateInstructions/addb_r8_imm8.k @@ -5,26 +5,27 @@ module ADDB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (addb Imm8:Imm, R2:R8, .Operands) => . + execinstr (addb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9)) -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/addb_rh_imm8.k b/semantics/immediateInstructions/addb_rh_imm8.k index df381909c..61d7e62bc 100644 --- a/semantics/immediateInstructions/addb_rh_imm8.k +++ b/semantics/immediateInstructions/addb_rh_imm8.k @@ -5,26 +5,27 @@ module ADDB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (addb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (addb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 51, 52)), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 51, 52)), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/addl_eax_imm32.k b/semantics/immediateInstructions/addl_eax_imm32.k index 92f764010..9a9fdcc44 100644 --- a/semantics/immediateInstructions/addl_eax_imm32.k +++ b/semantics/immediateInstructions/addl_eax_imm32.k @@ -5,26 +5,27 @@ module ADDL-EAX-IMM32 imports X86-CONFIGURATION rule - execinstr (addl Imm32:Imm, %eax, .Operands) => . + execinstr (addl Imm32:MInt, %eax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33)) +"RAX" |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33)) -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm32, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm32, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/addl_r32_imm32.k b/semantics/immediateInstructions/addl_r32_imm32.k index 7856f4492..082cee38a 100644 --- a/semantics/immediateInstructions/addl_r32_imm32.k +++ b/semantics/immediateInstructions/addl_r32_imm32.k @@ -5,26 +5,27 @@ module ADDL-R32-IMM32 imports X86-CONFIGURATION rule - execinstr (addl Imm32:Imm, R2:R32, .Operands) => . + execinstr (addl Imm32:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm32, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm32, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/addl_r32_imm8.k b/semantics/immediateInstructions/addl_r32_imm8.k index ea74935d9..5bbbebbbf 100644 --- a/semantics/immediateInstructions/addl_r32_imm8.k +++ b/semantics/immediateInstructions/addl_r32_imm8.k @@ -5,26 +5,27 @@ module ADDL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (addl Imm8:Imm, R2:R32, .Operands) => . + execinstr (addl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/addq_r64_imm32.k b/semantics/immediateInstructions/addq_r64_imm32.k index 4b5e64bfd..b70848610 100644 --- a/semantics/immediateInstructions/addq_r64_imm32.k +++ b/semantics/immediateInstructions/addq_r64_imm32.k @@ -5,26 +5,27 @@ module ADDQ-R64-IMM32 imports X86-CONFIGURATION rule - execinstr (addq Imm32:Imm, R2:R64, .Operands) => . + execinstr (addq Imm32:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) +convToRegKeys(R2) |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/addq_r64_imm8.k b/semantics/immediateInstructions/addq_r64_imm8.k index 6face7fbc..ee3e1fd81 100644 --- a/semantics/immediateInstructions/addq_r64_imm8.k +++ b/semantics/immediateInstructions/addq_r64_imm8.k @@ -5,26 +5,27 @@ module ADDQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (addq Imm8:Imm, R2:R64, .Operands) => . + execinstr (addq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) +convToRegKeys(R2) |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/addq_rax_imm32.k b/semantics/immediateInstructions/addq_rax_imm32.k index 6366ad150..dd4acff82 100644 --- a/semantics/immediateInstructions/addq_rax_imm32.k +++ b/semantics/immediateInstructions/addq_rax_imm32.k @@ -5,26 +5,27 @@ module ADDQ-RAX-IMM32 imports X86-CONFIGURATION rule - execinstr (addq Imm32:Imm, %rax, .Operands) => . + execinstr (addq Imm32:MInt, %rax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65) +"RAX" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65) -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/addw_ax_imm16.k b/semantics/immediateInstructions/addw_ax_imm16.k index ca187db86..4c5d171dc 100644 --- a/semantics/immediateInstructions/addw_ax_imm16.k +++ b/semantics/immediateInstructions/addw_ax_imm16.k @@ -5,26 +5,27 @@ module ADDW-AX-IMM16 imports X86-CONFIGURATION rule - execinstr (addw Imm16:Imm, %ax, .Operands) => . + execinstr (addw Imm16:MInt, %ax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 48), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17)) +"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 48), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17)) -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm16, 11, 12), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm16, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm16, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/addw_r16_imm16.k b/semantics/immediateInstructions/addw_r16_imm16.k index f053830ea..fa58fed71 100644 --- a/semantics/immediateInstructions/addw_r16_imm16.k +++ b/semantics/immediateInstructions/addw_r16_imm16.k @@ -5,26 +5,27 @@ module ADDW-R16-IMM16 imports X86-CONFIGURATION rule - execinstr (addw Imm16:Imm, R2:R16, .Operands) => . + execinstr (addw Imm16:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm16, 11, 12), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm16, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm16, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/addw_r16_imm8.k b/semantics/immediateInstructions/addw_r16_imm8.k index b88f7bb9b..7fa5d5e06 100644 --- a/semantics/immediateInstructions/addw_r16_imm8.k +++ b/semantics/immediateInstructions/addw_r16_imm8.k @@ -5,26 +5,27 @@ module ADDW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (addw Imm8:Imm, R2:R16, .Operands) => . + execinstr (addw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/andb_al_imm8.k b/semantics/immediateInstructions/andb_al_imm8.k index 3767e3011..fd3ad2eaa 100644 --- a/semantics/immediateInstructions/andb_al_imm8.k +++ b/semantics/immediateInstructions/andb_al_imm8.k @@ -5,26 +5,27 @@ module ANDB-AL-IMM8 imports X86-CONFIGURATION rule - execinstr (andb Imm8:Imm, %al, .Operands) => . + execinstr (andb Imm8:MInt, %al, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 56), andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 64), handleImmediateWithSignExtend(Imm8, 8, 8))) +"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 56), andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 64), Imm8)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 64), Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/andb_r8_imm8.k b/semantics/immediateInstructions/andb_r8_imm8.k index 7e490cbd1..c7a0b6542 100644 --- a/semantics/immediateInstructions/andb_r8_imm8.k +++ b/semantics/immediateInstructions/andb_r8_imm8.k @@ -5,26 +5,27 @@ module ANDB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (andb Imm8:Imm, R2:R8, .Operands) => . + execinstr (andb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), andMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), handleImmediateWithSignExtend(Imm8, 8, 8))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), andMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), Imm8)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/andb_rh_imm8.k b/semantics/immediateInstructions/andb_rh_imm8.k index 849ae23ba..d2312eaa2 100644 --- a/semantics/immediateInstructions/andb_rh_imm8.k +++ b/semantics/immediateInstructions/andb_rh_imm8.k @@ -5,26 +5,27 @@ module ANDB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (andb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (andb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), andMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), handleImmediateWithSignExtend(Imm8, 8, 8))), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), andMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), Imm8)), extractMInt( getParentValue(R2, RSMap), 56, 64)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 55, 56), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 54, 55), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 53, 54), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 52, 53), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 51, 52), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 50, 51), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 49, 50), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 55, 56), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 54, 55), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 53, 54), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 52, 53), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 51, 52), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 50, 51), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 49, 50), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/andl_eax_imm32.k b/semantics/immediateInstructions/andl_eax_imm32.k index 6575f6520..575bc8deb 100644 --- a/semantics/immediateInstructions/andl_eax_imm32.k +++ b/semantics/immediateInstructions/andl_eax_imm32.k @@ -5,26 +5,27 @@ module ANDL-EAX-IMM32 imports X86-CONFIGURATION rule - execinstr (andl Imm32:Imm, %eax, .Operands) => . + execinstr (andl Imm32:MInt, %eax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( mi(32, 0), andMInt( extractMInt( getParentValue(%rax, RSMap), 32, 64), handleImmediateWithSignExtend(Imm32, 32, 32))) +"RAX" |-> concatenateMInt( mi(32, 0), andMInt( extractMInt( getParentValue(%rax, RSMap), 32, 64), Imm32)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 32, 64), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 32, 64), Imm32), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), extractMInt( Imm32, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/andl_r32_imm32.k b/semantics/immediateInstructions/andl_r32_imm32.k index e8689d3ce..9357a7cb6 100644 --- a/semantics/immediateInstructions/andl_r32_imm32.k +++ b/semantics/immediateInstructions/andl_r32_imm32.k @@ -5,26 +5,27 @@ module ANDL-R32-IMM32 imports X86-CONFIGURATION rule - execinstr (andl Imm32:Imm, R2:R32, .Operands) => . + execinstr (andl Imm32:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), andMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), handleImmediateWithSignExtend(Imm32, 32, 32))) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), andMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), Imm32)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), Imm32), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), extractMInt( Imm32, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/andl_r32_imm8.k b/semantics/immediateInstructions/andl_r32_imm8.k index 126b2ae1f..0ba6528e3 100644 --- a/semantics/immediateInstructions/andl_r32_imm8.k +++ b/semantics/immediateInstructions/andl_r32_imm8.k @@ -5,26 +5,27 @@ module ANDL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (andl Imm8:Imm, R2:R32, .Operands) => . + execinstr (andl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), andMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), andMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, svalueMInt(Imm8)))) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, svalueMInt(Imm8))), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/andq_r64_imm32.k b/semantics/immediateInstructions/andq_r64_imm32.k index a366e4f75..bcabce0fd 100644 --- a/semantics/immediateInstructions/andq_r64_imm32.k +++ b/semantics/immediateInstructions/andq_r64_imm32.k @@ -5,26 +5,27 @@ module ANDQ-R64-IMM32 imports X86-CONFIGURATION rule - execinstr (andq Imm32:Imm, R2:R64, .Operands) => . + execinstr (andq Imm32:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> andMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) +convToRegKeys(R2) |-> andMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(Imm32))) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(Imm32))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/andq_r64_imm8.k b/semantics/immediateInstructions/andq_r64_imm8.k index aeb6a0d69..17c477e89 100644 --- a/semantics/immediateInstructions/andq_r64_imm8.k +++ b/semantics/immediateInstructions/andq_r64_imm8.k @@ -5,26 +5,27 @@ module ANDQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (andq Imm8:Imm, R2:R64, .Operands) => . + execinstr (andq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> andMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) +convToRegKeys(R2) |-> andMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(Imm8))) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(Imm8))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/andq_rax_imm32.k b/semantics/immediateInstructions/andq_rax_imm32.k index 004e0ca3a..03856141e 100644 --- a/semantics/immediateInstructions/andq_rax_imm32.k +++ b/semantics/immediateInstructions/andq_rax_imm32.k @@ -5,26 +5,27 @@ module ANDQ-RAX-IMM32 imports X86-CONFIGURATION rule - execinstr (andq Imm32:Imm, %rax, .Operands) => . + execinstr (andq Imm32:MInt, %rax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> andMInt( getParentValue(%rax, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) +"RAX" |-> andMInt( getParentValue(%rax, RSMap), mi(64, svalueMInt(Imm32))) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( getParentValue(%rax, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( getParentValue(%rax, RSMap), mi(64, svalueMInt(Imm32))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/andw_ax_imm16.k b/semantics/immediateInstructions/andw_ax_imm16.k index 57abcd076..23e3b7981 100644 --- a/semantics/immediateInstructions/andw_ax_imm16.k +++ b/semantics/immediateInstructions/andw_ax_imm16.k @@ -5,26 +5,27 @@ module ANDW-AX-IMM16 imports X86-CONFIGURATION rule - execinstr (andw Imm16:Imm, %ax, .Operands) => . + execinstr (andw Imm16:MInt, %ax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 48), andMInt( extractMInt( getParentValue(%rax, RSMap), 48, 64), handleImmediateWithSignExtend(Imm16, 16, 16))) +"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 48), andMInt( extractMInt( getParentValue(%rax, RSMap), 48, 64), Imm16)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 15, 16)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 14, 15)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 13, 14)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 12, 13)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 10, 11)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 9, 10)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm16, 15, 16)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm16, 14, 15)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm16, 13, 14)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm16, 12, 13)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm16, 11, 12)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm16, 10, 11)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm16, 9, 10)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm16, 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 48, 64), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 48, 64), Imm16), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), extractMInt( Imm16, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/andw_r16_imm16.k b/semantics/immediateInstructions/andw_r16_imm16.k index e84db6e52..932520799 100644 --- a/semantics/immediateInstructions/andw_r16_imm16.k +++ b/semantics/immediateInstructions/andw_r16_imm16.k @@ -5,26 +5,27 @@ module ANDW-R16-IMM16 imports X86-CONFIGURATION rule - execinstr (andw Imm16:Imm, R2:R16, .Operands) => . + execinstr (andw Imm16:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), andMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), handleImmediateWithSignExtend(Imm16, 16, 16))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), andMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), Imm16)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 15, 16)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 14, 15)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 13, 14)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 12, 13)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 10, 11)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 9, 10)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm16, 15, 16)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm16, 14, 15)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm16, 13, 14)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm16, 12, 13)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm16, 11, 12)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm16, 10, 11)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm16, 9, 10)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm16, 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), Imm16), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( Imm16, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/andw_r16_imm8.k b/semantics/immediateInstructions/andw_r16_imm8.k index 5438e4046..291b09534 100644 --- a/semantics/immediateInstructions/andw_r16_imm8.k +++ b/semantics/immediateInstructions/andw_r16_imm8.k @@ -5,26 +5,27 @@ module ANDW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (andw Imm8:Imm, R2:R16, .Operands) => . + execinstr (andw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), andMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), andMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(16, svalueMInt(Imm8)))) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(16, svalueMInt(Imm8))), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/blendpd_xmm_xmm_imm8.k b/semantics/immediateInstructions/blendpd_xmm_xmm_imm8.k index e9ebce867..718ab1618 100644 --- a/semantics/immediateInstructions/blendpd_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/blendpd_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module BLENDPD-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (blendpd Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (blendpd Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 192) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 256) #else extractMInt( getParentValue(R2, RSMap), 192, 256) #fi))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 192) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 256) #else extractMInt( getParentValue(R2, RSMap), 192, 256) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/blendps_xmm_xmm_imm8.k b/semantics/immediateInstructions/blendps_xmm_xmm_imm8.k index cbc2a8235..190d4481b 100644 --- a/semantics/immediateInstructions/blendps_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/blendps_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module BLENDPS-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (blendps Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (blendps Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 160, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 160, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/btcl_r32_imm8.k b/semantics/immediateInstructions/btcl_r32_imm8.k index 7994b200a..33479f647 100644 --- a/semantics/immediateInstructions/btcl_r32_imm8.k +++ b/semantics/immediateInstructions/btcl_r32_imm8.k @@ -5,13 +5,13 @@ module BTCL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (btcl Imm8:Imm, R2:R32, .Operands) => . + execinstr (btcl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), xorMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), shiftLeftMInt( mi(32, 1), uvalueMInt(mi(32, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))))))) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), xorMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), shiftLeftMInt( mi(32, 1), uvalueMInt(mi(32, svalueMInt(andMInt( Imm8, mi(8, 31)))))))) -"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(mi(32, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))))), 31, 32) +"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(mi(32, svalueMInt(andMInt( Imm8, mi(8, 31)))))), 31, 32) "PF" |-> (undefMInt) @@ -23,6 +23,7 @@ convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), xorMInt( extractMInt( getParen ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/btcq_r64_imm8.k b/semantics/immediateInstructions/btcq_r64_imm8.k index 6c7a97b5e..ac7ac1d96 100644 --- a/semantics/immediateInstructions/btcq_r64_imm8.k +++ b/semantics/immediateInstructions/btcq_r64_imm8.k @@ -5,13 +5,13 @@ module BTCQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (btcq Imm8:Imm, R2:R64, .Operands) => . + execinstr (btcq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> xorMInt( getParentValue(R2, RSMap), shiftLeftMInt( mi(64, 1), uvalueMInt(mi(64, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))))) +convToRegKeys(R2) |-> xorMInt( getParentValue(R2, RSMap), shiftLeftMInt( mi(64, 1), uvalueMInt(mi(64, svalueMInt(andMInt( Imm8, mi(8, 63))))))) -"CF" |-> extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(mi(64, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))))), 63, 64) +"CF" |-> extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(mi(64, svalueMInt(andMInt( Imm8, mi(8, 63)))))), 63, 64) "PF" |-> (undefMInt) @@ -23,6 +23,7 @@ convToRegKeys(R2) |-> xorMInt( getParentValue(R2, RSMap), shiftLeftMInt( mi(64, ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/btcw_r16_imm8.k b/semantics/immediateInstructions/btcw_r16_imm8.k index b817247be..433f69826 100644 --- a/semantics/immediateInstructions/btcw_r16_imm8.k +++ b/semantics/immediateInstructions/btcw_r16_imm8.k @@ -5,13 +5,13 @@ module BTCW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (btcw Imm8:Imm, R2:R16, .Operands) => . + execinstr (btcw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), shiftLeftMInt( mi(16, 1), uvalueMInt(mi(16, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 15)))))))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), shiftLeftMInt( mi(16, 1), uvalueMInt(mi(16, svalueMInt(andMInt( Imm8, mi(8, 15)))))))) -"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), uvalueMInt(mi(16, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 15)))))), 15, 16) +"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), uvalueMInt(mi(16, svalueMInt(andMInt( Imm8, mi(8, 15)))))), 15, 16) "PF" |-> (undefMInt) @@ -23,6 +23,7 @@ convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0 ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/btl_r32_imm8.k b/semantics/immediateInstructions/btl_r32_imm8.k index 5b3ef7855..f93177366 100644 --- a/semantics/immediateInstructions/btl_r32_imm8.k +++ b/semantics/immediateInstructions/btl_r32_imm8.k @@ -5,11 +5,11 @@ module BTL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (btl Imm8:Imm, R2:R32, .Operands) => . + execinstr (btl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(mi(32, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))))), 31, 32) +"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(mi(32, svalueMInt(andMInt( Imm8, mi(8, 31)))))), 31, 32) "PF" |-> (undefMInt) @@ -21,6 +21,7 @@ RSMap:Map => updateMap(RSMap, ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/btq_r64_imm8.k b/semantics/immediateInstructions/btq_r64_imm8.k index 490d355c5..3faba1fc7 100644 --- a/semantics/immediateInstructions/btq_r64_imm8.k +++ b/semantics/immediateInstructions/btq_r64_imm8.k @@ -5,11 +5,11 @@ module BTQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (btq Imm8:Imm, R2:R64, .Operands) => . + execinstr (btq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(mi(64, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))))), 63, 64) +"CF" |-> extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(mi(64, svalueMInt(andMInt( Imm8, mi(8, 63)))))), 63, 64) "PF" |-> (undefMInt) @@ -21,6 +21,7 @@ RSMap:Map => updateMap(RSMap, ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/btrl_r32_imm8.k b/semantics/immediateInstructions/btrl_r32_imm8.k index ef24cd754..18d7fc3f1 100644 --- a/semantics/immediateInstructions/btrl_r32_imm8.k +++ b/semantics/immediateInstructions/btrl_r32_imm8.k @@ -5,13 +5,13 @@ module BTRL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (btrl Imm8:Imm, R2:R32, .Operands) => . + execinstr (btrl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), andMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), negMInt( shiftLeftMInt( mi(32, 1), uvalueMInt(mi(32, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))))))) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), andMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), negMInt( shiftLeftMInt( mi(32, 1), uvalueMInt(mi(32, svalueMInt(andMInt( Imm8, mi(8, 31))))))))) -"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(mi(32, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))))), 31, 32) +"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(mi(32, svalueMInt(andMInt( Imm8, mi(8, 31)))))), 31, 32) "PF" |-> (undefMInt) @@ -23,6 +23,7 @@ convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), andMInt( extractMInt( getParen ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/btrq_r64_imm8.k b/semantics/immediateInstructions/btrq_r64_imm8.k index 155df1033..7553de254 100644 --- a/semantics/immediateInstructions/btrq_r64_imm8.k +++ b/semantics/immediateInstructions/btrq_r64_imm8.k @@ -5,13 +5,13 @@ module BTRQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (btrq Imm8:Imm, R2:R64, .Operands) => . + execinstr (btrq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> andMInt( getParentValue(R2, RSMap), negMInt( shiftLeftMInt( mi(64, 1), uvalueMInt(mi(64, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))))))) +convToRegKeys(R2) |-> andMInt( getParentValue(R2, RSMap), negMInt( shiftLeftMInt( mi(64, 1), uvalueMInt(mi(64, svalueMInt(andMInt( Imm8, mi(8, 63)))))))) -"CF" |-> extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(mi(64, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))))), 63, 64) +"CF" |-> extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(mi(64, svalueMInt(andMInt( Imm8, mi(8, 63)))))), 63, 64) "PF" |-> (undefMInt) @@ -23,6 +23,7 @@ convToRegKeys(R2) |-> andMInt( getParentValue(R2, RSMap), negMInt( shiftLeftMInt ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/btrw_r16_imm8.k b/semantics/immediateInstructions/btrw_r16_imm8.k index 5452e91bf..5c940cb10 100644 --- a/semantics/immediateInstructions/btrw_r16_imm8.k +++ b/semantics/immediateInstructions/btrw_r16_imm8.k @@ -5,13 +5,13 @@ module BTRW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (btrw Imm8:Imm, R2:R16, .Operands) => . + execinstr (btrw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), andMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), negMInt( shiftLeftMInt( mi(16, 1), uvalueMInt(mi(16, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 15))))))))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), andMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), negMInt( shiftLeftMInt( mi(16, 1), uvalueMInt(mi(16, svalueMInt(andMInt( Imm8, mi(8, 15))))))))) -"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), uvalueMInt(mi(16, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 15)))))), 15, 16) +"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), uvalueMInt(mi(16, svalueMInt(andMInt( Imm8, mi(8, 15)))))), 15, 16) "PF" |-> (undefMInt) @@ -23,6 +23,7 @@ convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0 ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/btsl_r32_imm8.k b/semantics/immediateInstructions/btsl_r32_imm8.k index 837d27cc6..021453338 100644 --- a/semantics/immediateInstructions/btsl_r32_imm8.k +++ b/semantics/immediateInstructions/btsl_r32_imm8.k @@ -5,13 +5,13 @@ module BTSL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (btsl Imm8:Imm, R2:R32, .Operands) => . + execinstr (btsl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), orMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), shiftLeftMInt( mi(32, 1), uvalueMInt(mi(32, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))))))) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), orMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), shiftLeftMInt( mi(32, 1), uvalueMInt(mi(32, svalueMInt(andMInt( Imm8, mi(8, 31)))))))) -"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(mi(32, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))))), 31, 32) +"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(mi(32, svalueMInt(andMInt( Imm8, mi(8, 31)))))), 31, 32) "PF" |-> (undefMInt) @@ -23,6 +23,7 @@ convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), orMInt( extractMInt( getParent ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/btsq_r64_imm8.k b/semantics/immediateInstructions/btsq_r64_imm8.k index 8a9cf93b1..025a173f9 100644 --- a/semantics/immediateInstructions/btsq_r64_imm8.k +++ b/semantics/immediateInstructions/btsq_r64_imm8.k @@ -5,13 +5,13 @@ module BTSQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (btsq Imm8:Imm, R2:R64, .Operands) => . + execinstr (btsq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> orMInt( getParentValue(R2, RSMap), shiftLeftMInt( mi(64, 1), uvalueMInt(mi(64, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))))) +convToRegKeys(R2) |-> orMInt( getParentValue(R2, RSMap), shiftLeftMInt( mi(64, 1), uvalueMInt(mi(64, svalueMInt(andMInt( Imm8, mi(8, 63))))))) -"CF" |-> extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(mi(64, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))))), 63, 64) +"CF" |-> extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(mi(64, svalueMInt(andMInt( Imm8, mi(8, 63)))))), 63, 64) "PF" |-> (undefMInt) @@ -23,6 +23,7 @@ convToRegKeys(R2) |-> orMInt( getParentValue(R2, RSMap), shiftLeftMInt( mi(64, 1 ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/btsw_r16_imm8.k b/semantics/immediateInstructions/btsw_r16_imm8.k index b8795b147..ea2a84a37 100644 --- a/semantics/immediateInstructions/btsw_r16_imm8.k +++ b/semantics/immediateInstructions/btsw_r16_imm8.k @@ -5,13 +5,13 @@ module BTSW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (btsw Imm8:Imm, R2:R16, .Operands) => . + execinstr (btsw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), orMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), shiftLeftMInt( mi(16, 1), uvalueMInt(mi(16, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 15)))))))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), orMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), shiftLeftMInt( mi(16, 1), uvalueMInt(mi(16, svalueMInt(andMInt( Imm8, mi(8, 15)))))))) -"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), uvalueMInt(mi(16, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 15)))))), 15, 16) +"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), uvalueMInt(mi(16, svalueMInt(andMInt( Imm8, mi(8, 15)))))), 15, 16) "PF" |-> (undefMInt) @@ -23,6 +23,7 @@ convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0 ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/btw_r16_imm8.k b/semantics/immediateInstructions/btw_r16_imm8.k index bd817430c..836f1d9e8 100644 --- a/semantics/immediateInstructions/btw_r16_imm8.k +++ b/semantics/immediateInstructions/btw_r16_imm8.k @@ -5,11 +5,11 @@ module BTW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (btw Imm8:Imm, R2:R16, .Operands) => . + execinstr (btw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), uvalueMInt(mi(16, svalueMInt(andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 15)))))), 15, 16) +"CF" |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), uvalueMInt(mi(16, svalueMInt(andMInt( Imm8, mi(8, 15)))))), 15, 16) "PF" |-> (undefMInt) @@ -21,6 +21,7 @@ RSMap:Map => updateMap(RSMap, ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/cmpb_al_imm8.k b/semantics/immediateInstructions/cmpb_al_imm8.k index 45332095a..cb9434fd3 100644 --- a/semantics/immediateInstructions/cmpb_al_imm8.k +++ b/semantics/immediateInstructions/cmpb_al_imm8.k @@ -5,24 +5,25 @@ module CMPB-AL-IMM8 imports X86-CONFIGURATION rule - execinstr (cmpb Imm8:Imm, %al, .Operands) => . + execinstr (cmpb Imm8:MInt, %al, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/cmpb_r8_imm8.k b/semantics/immediateInstructions/cmpb_r8_imm8.k index 7d9b2a57c..b2ecbead1 100644 --- a/semantics/immediateInstructions/cmpb_r8_imm8.k +++ b/semantics/immediateInstructions/cmpb_r8_imm8.k @@ -5,24 +5,25 @@ module CMPB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (cmpb Imm8:Imm, R2:R8, .Operands) => . + execinstr (cmpb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/cmpb_rh_imm8.k b/semantics/immediateInstructions/cmpb_rh_imm8.k index 7746acbe6..a7ddaa8b2 100644 --- a/semantics/immediateInstructions/cmpb_rh_imm8.k +++ b/semantics/immediateInstructions/cmpb_rh_imm8.k @@ -5,24 +5,25 @@ module CMPB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (cmpb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (cmpb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 51, 52)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 51, 52)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/cmpl_eax_imm32.k b/semantics/immediateInstructions/cmpl_eax_imm32.k index d9732c928..769fe7ea1 100644 --- a/semantics/immediateInstructions/cmpl_eax_imm32.k +++ b/semantics/immediateInstructions/cmpl_eax_imm32.k @@ -5,24 +5,25 @@ module CMPL-EAX-IMM32 imports X86-CONFIGURATION rule - execinstr (cmpl Imm32:Imm, %eax, .Operands) => . + execinstr (cmpl Imm32:MInt, %eax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/cmpl_r32_imm32.k b/semantics/immediateInstructions/cmpl_r32_imm32.k index 089410bf1..d135eaf95 100644 --- a/semantics/immediateInstructions/cmpl_r32_imm32.k +++ b/semantics/immediateInstructions/cmpl_r32_imm32.k @@ -5,24 +5,25 @@ module CMPL-R32-IMM32 imports X86-CONFIGURATION rule - execinstr (cmpl Imm32:Imm, R2:R32, .Operands) => . + execinstr (cmpl Imm32:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/cmpl_r32_imm8.k b/semantics/immediateInstructions/cmpl_r32_imm8.k index 553221e9d..fbe8ce041 100644 --- a/semantics/immediateInstructions/cmpl_r32_imm8.k +++ b/semantics/immediateInstructions/cmpl_r32_imm8.k @@ -5,24 +5,25 @@ module CMPL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (cmpl Imm8:Imm, R2:R32, .Operands) => . + execinstr (cmpl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/cmppd_xmm_xmm_imm8.k b/semantics/immediateInstructions/cmppd_xmm_xmm_imm8.k index c5e3ef429..ebad58d81 100644 --- a/semantics/immediateInstructions/cmppd_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/cmppd_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module CMPPD-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (cmppd Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (cmppd Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( getParentValue(R2, RSMap), 128, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( getParentValue(R2, RSMap), 128, 192), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/cmpps_xmm_xmm_imm8.k b/semantics/immediateInstructions/cmpps_xmm_xmm_imm8.k index 6daefaaac..58e1b5815 100644 --- a/semantics/immediateInstructions/cmpps_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/cmpps_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module CMPPS-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (cmpps Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (cmpps Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/cmpq_r64_imm32.k b/semantics/immediateInstructions/cmpq_r64_imm32.k index 098d0d7b1..e9fdeae98 100644 --- a/semantics/immediateInstructions/cmpq_r64_imm32.k +++ b/semantics/immediateInstructions/cmpq_r64_imm32.k @@ -5,24 +5,25 @@ module CMPQ-R64-IMM32 imports X86-CONFIGURATION rule - execinstr (cmpq Imm32:Imm, R2:R64, .Operands) => . + execinstr (cmpq Imm32:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/cmpq_r64_imm8.k b/semantics/immediateInstructions/cmpq_r64_imm8.k index 31afa9136..45c1feb53 100644 --- a/semantics/immediateInstructions/cmpq_r64_imm8.k +++ b/semantics/immediateInstructions/cmpq_r64_imm8.k @@ -5,24 +5,25 @@ module CMPQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (cmpq Imm8:Imm, R2:R64, .Operands) => . + execinstr (cmpq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/cmpq_rax_imm32.k b/semantics/immediateInstructions/cmpq_rax_imm32.k index c40b120a6..6235d4060 100644 --- a/semantics/immediateInstructions/cmpq_rax_imm32.k +++ b/semantics/immediateInstructions/cmpq_rax_imm32.k @@ -5,24 +5,25 @@ module CMPQ-RAX-IMM32 imports X86-CONFIGURATION rule - execinstr (cmpq Imm32:Imm, %rax, .Operands) => . + execinstr (cmpq Imm32:MInt, %rax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/cmpsd_xmm_xmm_imm8.k b/semantics/immediateInstructions/cmpsd_xmm_xmm_imm8.k index 67f323431..989ff62a4 100644 --- a/semantics/immediateInstructions/cmpsd_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/cmpsd_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module CMPSD-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (cmpsd Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (cmpsd Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 192), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi)) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 192), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/cmpss_xmm_xmm_imm8.k b/semantics/immediateInstructions/cmpss_xmm_xmm_imm8.k index 5921b29ba..361511237 100644 --- a/semantics/immediateInstructions/cmpss_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/cmpss_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module CMPSS-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (cmpss Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (cmpss Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 224), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi)) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 224), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/cmpw_ax_imm16.k b/semantics/immediateInstructions/cmpw_ax_imm16.k index 68c4909ad..bf10107bd 100644 --- a/semantics/immediateInstructions/cmpw_ax_imm16.k +++ b/semantics/immediateInstructions/cmpw_ax_imm16.k @@ -5,24 +5,25 @@ module CMPW-AX-IMM16 imports X86-CONFIGURATION rule - execinstr (cmpw Imm16:Imm, %ax, .Operands) => . + execinstr (cmpw Imm16:MInt, %ax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm16, 11, 12), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/cmpw_r16_imm16.k b/semantics/immediateInstructions/cmpw_r16_imm16.k index d237acdb4..b2e151a7d 100644 --- a/semantics/immediateInstructions/cmpw_r16_imm16.k +++ b/semantics/immediateInstructions/cmpw_r16_imm16.k @@ -5,24 +5,25 @@ module CMPW-R16-IMM16 imports X86-CONFIGURATION rule - execinstr (cmpw Imm16:Imm, R2:R16, .Operands) => . + execinstr (cmpw Imm16:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm16, 11, 12), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/cmpw_r16_imm8.k b/semantics/immediateInstructions/cmpw_r16_imm8.k index 6fce01d8b..b70c61ae8 100644 --- a/semantics/immediateInstructions/cmpw_r16_imm8.k +++ b/semantics/immediateInstructions/cmpw_r16_imm8.k @@ -5,24 +5,25 @@ module CMPW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (cmpw Imm8:Imm, R2:R16, .Operands) => . + execinstr (cmpw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/dppd_xmm_xmm_imm8.k b/semantics/immediateInstructions/dppd_xmm_xmm_imm8.k index b1fe5b276..d2b684705 100644 --- a/semantics/immediateInstructions/dppd_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/dppd_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module DPPD-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (dppd Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (dppd Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( getParentValue(R2, RSMap), 128, 192)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( getParentValue(R2, RSMap), 128, 192)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( getParentValue(R2, RSMap), 128, 192)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( getParentValue(R2, RSMap), 128, 192)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/dpps_xmm_xmm_imm8.k b/semantics/immediateInstructions/dpps_xmm_xmm_imm8.k index 400d5ae00..860c595e9 100644 --- a/semantics/immediateInstructions/dpps_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/dpps_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module DPPS-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (dpps Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (dpps Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/extractps_r32_xmm_imm8.k b/semantics/immediateInstructions/extractps_r32_xmm_imm8.k index 4a9873a3a..48f94246d 100644 --- a/semantics/immediateInstructions/extractps_r32_xmm_imm8.k +++ b/semantics/immediateInstructions/extractps_r32_xmm_imm8.k @@ -5,14 +5,15 @@ module EXTRACTPS-R32-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (extractps Imm8:Imm, R2:Xmm, R3:R32, .Operands) => . + execinstr (extractps Imm8:MInt, R2:Xmm, R3:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128)) +convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/extractps_r64_xmm_imm8.k b/semantics/immediateInstructions/extractps_r64_xmm_imm8.k index 8748b1321..438a0467f 100644 --- a/semantics/immediateInstructions/extractps_r64_xmm_imm8.k +++ b/semantics/immediateInstructions/extractps_r64_xmm_imm8.k @@ -5,14 +5,15 @@ module EXTRACTPS-R64-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (extractps Imm8:Imm, R2:Xmm, R3:R64, .Operands) => . + execinstr (extractps Imm8:MInt, R2:Xmm, R3:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128)) +convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/imull_r32_r32_imm32.k b/semantics/immediateInstructions/imull_r32_r32_imm32.k index 57702c445..67c1829d9 100644 --- a/semantics/immediateInstructions/imull_r32_r32_imm32.k +++ b/semantics/immediateInstructions/imull_r32_r32_imm32.k @@ -5,13 +5,13 @@ module IMULL-R32-R32-IMM32 imports X86-CONFIGURATION rule - execinstr (imull Imm32:Imm, R2:R32, R3:R32, .Operands) => . + execinstr (imull Imm32:MInt, R2:R32, R3:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), 32, 64)) +convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(Imm32))), 32, 64)) -"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(Imm32))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(Imm32))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) "PF" |-> (undefMInt) @@ -21,10 +21,11 @@ convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( mulMInt( mi(64, s "SF" |-> (undefMInt) -"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(Imm32))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(Imm32))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/imull_r32_r32_imm8.k b/semantics/immediateInstructions/imull_r32_r32_imm8.k index fb6071837..0c581bb88 100644 --- a/semantics/immediateInstructions/imull_r32_r32_imm8.k +++ b/semantics/immediateInstructions/imull_r32_r32_imm8.k @@ -5,13 +5,13 @@ module IMULL-R32-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (imull Imm8:Imm, R2:R32, R3:R32, .Operands) => . + execinstr (imull Imm8:MInt, R2:R32, R3:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 32, 64)) +convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(Imm8))), 32, 64)) -"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(Imm8))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(Imm8))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) "PF" |-> (undefMInt) @@ -21,10 +21,11 @@ convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( mulMInt( mi(64, s "SF" |-> (undefMInt) -"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(Imm8))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(extractMInt( getParentValue(R2, RSMap), 32, 64))), mi(64, svalueMInt(Imm8))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/imulq_r64_r64_imm32.k b/semantics/immediateInstructions/imulq_r64_r64_imm32.k index f88104746..0e2abacb7 100644 --- a/semantics/immediateInstructions/imulq_r64_r64_imm32.k +++ b/semantics/immediateInstructions/imulq_r64_r64_imm32.k @@ -5,13 +5,13 @@ module IMULQ-R64-R64-IMM32 imports X86-CONFIGURATION rule - execinstr (imulq Imm32:Imm, R2:R64, R3:R64, .Operands) => . + execinstr (imulq Imm32:MInt, R2:R64, R3:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> extractMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), 64, 128) +convToRegKeys(R3) |-> extractMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(Imm32))), 64, 128) -"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(Imm32))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(Imm32))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) "PF" |-> (undefMInt) @@ -21,10 +21,11 @@ convToRegKeys(R3) |-> extractMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2 "SF" |-> (undefMInt) -"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(Imm32))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(Imm32))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/imulq_r64_r64_imm8.k b/semantics/immediateInstructions/imulq_r64_r64_imm8.k index 09f92931c..231eef2cd 100644 --- a/semantics/immediateInstructions/imulq_r64_r64_imm8.k +++ b/semantics/immediateInstructions/imulq_r64_r64_imm8.k @@ -5,13 +5,13 @@ module IMULQ-R64-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (imulq Imm8:Imm, R2:R64, R3:R64, .Operands) => . + execinstr (imulq Imm8:MInt, R2:R64, R3:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> extractMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 64, 128) +convToRegKeys(R3) |-> extractMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(Imm8))), 64, 128) -"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(Imm8))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(Imm8))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) "PF" |-> (undefMInt) @@ -21,10 +21,11 @@ convToRegKeys(R3) |-> extractMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2 "SF" |-> (undefMInt) -"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(Imm8))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(getParentValue(R2, RSMap))), mi(128, svalueMInt(Imm8))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/imulw_r16_r16_imm16.k b/semantics/immediateInstructions/imulw_r16_r16_imm16.k index 5a83cb2cf..3815f7edc 100644 --- a/semantics/immediateInstructions/imulw_r16_r16_imm16.k +++ b/semantics/immediateInstructions/imulw_r16_r16_imm16.k @@ -5,13 +5,13 @@ module IMULW-R16-R16-IMM16 imports X86-CONFIGURATION rule - execinstr (imulw Imm16:Imm, R2:R16, R3:R16, .Operands) => . + execinstr (imulw Imm16:MInt, R2:R16, R3:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 48), extractMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm16, 16, 16)))), 16, 32)) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 48), extractMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(Imm16))), 16, 32)) -"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm16, 16, 16)))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm16, 16, 16)))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(Imm16))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(Imm16))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) "PF" |-> (undefMInt) @@ -21,10 +21,11 @@ convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0 "SF" |-> (undefMInt) -"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm16, 16, 16)))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm16, 16, 16)))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(Imm16))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(Imm16))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/imulw_r16_r16_imm8.k b/semantics/immediateInstructions/imulw_r16_r16_imm8.k index 24b0d6d3b..a7c5657ce 100644 --- a/semantics/immediateInstructions/imulw_r16_r16_imm8.k +++ b/semantics/immediateInstructions/imulw_r16_r16_imm8.k @@ -5,13 +5,13 @@ module IMULW-R16-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (imulw Imm8:Imm, R2:R16, R3:R16, .Operands) => . + execinstr (imulw Imm8:MInt, R2:R16, R3:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 48), extractMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 16, 32)) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 48), extractMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(Imm8))), 16, 32)) -"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(Imm8))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(Imm8))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) "PF" |-> (undefMInt) @@ -21,10 +21,11 @@ convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0 "SF" |-> (undefMInt) -"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(Imm8))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(extractMInt( getParentValue(R2, RSMap), 48, 64))), mi(32, svalueMInt(Imm8))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/insertps_xmm_xmm_imm8.k b/semantics/immediateInstructions/insertps_xmm_xmm_imm8.k index 257c1c32b..9dfedb717 100644 --- a/semantics/immediateInstructions/insertps_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/insertps_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module INSERTPS-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (insertps Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (insertps Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #fi) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #else extractMInt( getParentValue(R3, RSMap), 160, 192) #fi) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #fi) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #else extractMInt( getParentValue(R3, RSMap), 160, 192) #fi) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/movb_r8_imm8.k b/semantics/immediateInstructions/movb_r8_imm8.k index f5f3fca11..b7ab26b3b 100644 --- a/semantics/immediateInstructions/movb_r8_imm8.k +++ b/semantics/immediateInstructions/movb_r8_imm8.k @@ -5,14 +5,15 @@ module MOVB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (movb Imm8:Imm, R2:R8, .Operands) => . + execinstr (movb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), handleImmediateWithSignExtend(Imm8, 8, 8)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), Imm8) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/movb_rh_imm8.k b/semantics/immediateInstructions/movb_rh_imm8.k index f4592e2b2..f8da98827 100644 --- a/semantics/immediateInstructions/movb_rh_imm8.k +++ b/semantics/immediateInstructions/movb_rh_imm8.k @@ -5,14 +5,15 @@ module MOVB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (movb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (movb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), handleImmediateWithSignExtend(Imm8, 8, 8)), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), Imm8), extractMInt( getParentValue(R2, RSMap), 56, 64)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/movl_r32_imm32.k b/semantics/immediateInstructions/movl_r32_imm32.k index 6555f7f5a..0fed3fbb9 100644 --- a/semantics/immediateInstructions/movl_r32_imm32.k +++ b/semantics/immediateInstructions/movl_r32_imm32.k @@ -5,14 +5,15 @@ module MOVL-R32-IMM32 imports X86-CONFIGURATION rule - execinstr (movl Imm32:Imm, R2:R32, .Operands) => . + execinstr (movl Imm32:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), Imm32) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/movq_r64_imm32.k b/semantics/immediateInstructions/movq_r64_imm32.k index 73f896b97..12a2bed0f 100644 --- a/semantics/immediateInstructions/movq_r64_imm32.k +++ b/semantics/immediateInstructions/movq_r64_imm32.k @@ -5,14 +5,15 @@ module MOVQ-R64-IMM32 imports X86-CONFIGURATION rule - execinstr (movq Imm32:Imm, R2:R64, .Operands) => . + execinstr (movq Imm32:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))) +convToRegKeys(R2) |-> mi(64, svalueMInt(Imm32)) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/movq_r64_imm64.k b/semantics/immediateInstructions/movq_r64_imm64.k index cc4a8e719..7f2cdfeb6 100644 --- a/semantics/immediateInstructions/movq_r64_imm64.k +++ b/semantics/immediateInstructions/movq_r64_imm64.k @@ -5,14 +5,15 @@ module MOVQ-R64-IMM64 imports X86-CONFIGURATION rule - execinstr (movq Imm64:Imm, R2:R64, .Operands) => . + execinstr (movq Imm64:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> handleImmediateWithSignExtend(Imm64, 64, 64) +convToRegKeys(R2) |-> Imm64 ) + requires bitwidthMInt(Imm64) ==Int 64 endmodule diff --git a/semantics/immediateInstructions/movw_r16_imm16.k b/semantics/immediateInstructions/movw_r16_imm16.k index d7cec4199..a6a1ff2dc 100644 --- a/semantics/immediateInstructions/movw_r16_imm16.k +++ b/semantics/immediateInstructions/movw_r16_imm16.k @@ -5,14 +5,15 @@ module MOVW-R16-IMM16 imports X86-CONFIGURATION rule - execinstr (movw Imm16:Imm, R2:R16, .Operands) => . + execinstr (movw Imm16:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), handleImmediateWithSignExtend(Imm16, 16, 16)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), Imm16) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/mpsadbw_xmm_xmm_imm8.k b/semantics/immediateInstructions/mpsadbw_xmm_xmm_imm8.k index 78725d1de..da0f7af7e 100644 --- a/semantics/immediateInstructions/mpsadbw_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/mpsadbw_xmm_xmm_imm8.k @@ -4,43 +4,44 @@ module MPSADBW-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (mpsadbw Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => + execinstr (mpsadbw Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => execinstr (mpsadbw selectSliceMPSAD(getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 7 , 0 ), + extractMInt(Imm8, 6, 8), 7 , 0 ), selectSliceMPSAD(getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 15, 8 ), + extractMInt(Imm8, 6, 8), 15, 8 ), selectSliceMPSAD(getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 23, 16), + extractMInt(Imm8, 6, 8), 23, 16), selectSliceMPSAD(getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 31, 24), + extractMInt(Imm8, 6, 8), 31, 24), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 7 , 0), + extractMInt(Imm8, 5, 6), 7 , 0), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 15, 8), + extractMInt(Imm8, 5, 6), 15, 8), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 23, 16), + extractMInt(Imm8, 5, 6), 23, 16), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 31, 24), + extractMInt(Imm8, 5, 6), 31, 24), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 39, 32), + extractMInt(Imm8, 5, 6), 39, 32), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 47, 40), + extractMInt(Imm8, 5, 6), 47, 40), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 55, 48), + extractMInt(Imm8, 5, 6), 55, 48), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 63, 56), + extractMInt(Imm8, 5, 6), 63, 56), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 71, 64), + extractMInt(Imm8, 5, 6), 71, 64), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 79, 72), + extractMInt(Imm8, 5, 6), 79, 72), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 87, 80), + extractMInt(Imm8, 5, 6), 87, 80), R3:Xmm, .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (mpsadbw diff --git a/semantics/immediateInstructions/orb_al_imm8.k b/semantics/immediateInstructions/orb_al_imm8.k index 3f6603153..c0010c1f5 100644 --- a/semantics/immediateInstructions/orb_al_imm8.k +++ b/semantics/immediateInstructions/orb_al_imm8.k @@ -5,26 +5,27 @@ module ORB-AL-IMM8 imports X86-CONFIGURATION rule - execinstr (orb Imm8:Imm, %al, .Operands) => . + execinstr (orb Imm8:MInt, %al, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 56), orMInt( extractMInt( getParentValue(%rax, RSMap), 56, 64), handleImmediateWithSignExtend(Imm8, 8, 8))) +"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 56), orMInt( extractMInt( getParentValue(%rax, RSMap), 56, 64), Imm8)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 56, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 56, 64), Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> orMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/orb_r8_imm8.k b/semantics/immediateInstructions/orb_r8_imm8.k index 37563bc7a..189af7d4b 100644 --- a/semantics/immediateInstructions/orb_r8_imm8.k +++ b/semantics/immediateInstructions/orb_r8_imm8.k @@ -5,26 +5,27 @@ module ORB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (orb Imm8:Imm, R2:R8, .Operands) => . + execinstr (orb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), orMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), handleImmediateWithSignExtend(Imm8, 8, 8))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), orMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), Imm8)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/orb_rh_imm8.k b/semantics/immediateInstructions/orb_rh_imm8.k index 627755af4..2a7e7d6d8 100644 --- a/semantics/immediateInstructions/orb_rh_imm8.k +++ b/semantics/immediateInstructions/orb_rh_imm8.k @@ -5,26 +5,27 @@ module ORB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (orb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (orb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), orMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), handleImmediateWithSignExtend(Imm8, 8, 8))), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), orMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), Imm8)), extractMInt( getParentValue(R2, RSMap), 56, 64)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 55, 56), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 54, 55), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 53, 54), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 52, 53), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 51, 52), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 50, 51), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 49, 50), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 55, 56), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 54, 55), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 53, 54), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 52, 53), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 51, 52), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 50, 51), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 49, 50), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/orl_eax_imm32.k b/semantics/immediateInstructions/orl_eax_imm32.k index d6f2b62e9..3eb01bf70 100644 --- a/semantics/immediateInstructions/orl_eax_imm32.k +++ b/semantics/immediateInstructions/orl_eax_imm32.k @@ -5,26 +5,27 @@ module ORL-EAX-IMM32 imports X86-CONFIGURATION rule - execinstr (orl Imm32:Imm, %eax, .Operands) => . + execinstr (orl Imm32:MInt, %eax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( mi(32, 0), orMInt( extractMInt( getParentValue(%rax, RSMap), 32, 64), handleImmediateWithSignExtend(Imm32, 32, 32))) +"RAX" |-> concatenateMInt( mi(32, 0), orMInt( extractMInt( getParentValue(%rax, RSMap), 32, 64), Imm32)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 32, 64), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 32, 64), Imm32), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)) +"SF" |-> orMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), extractMInt( Imm32, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/orl_r32_imm32.k b/semantics/immediateInstructions/orl_r32_imm32.k index c087060b6..37bf020a2 100644 --- a/semantics/immediateInstructions/orl_r32_imm32.k +++ b/semantics/immediateInstructions/orl_r32_imm32.k @@ -5,26 +5,27 @@ module ORL-R32-IMM32 imports X86-CONFIGURATION rule - execinstr (orl Imm32:Imm, R2:R32, .Operands) => . + execinstr (orl Imm32:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), orMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), handleImmediateWithSignExtend(Imm32, 32, 32))) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), orMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), Imm32)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), Imm32), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)) +"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), extractMInt( Imm32, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/orl_r32_imm8.k b/semantics/immediateInstructions/orl_r32_imm8.k index a06966384..51c069103 100644 --- a/semantics/immediateInstructions/orl_r32_imm8.k +++ b/semantics/immediateInstructions/orl_r32_imm8.k @@ -5,26 +5,27 @@ module ORL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (orl Imm8:Imm, R2:R32, .Operands) => . + execinstr (orl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), orMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), orMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, svalueMInt(Imm8)))) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, svalueMInt(Imm8))), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/orq_r64_imm32.k b/semantics/immediateInstructions/orq_r64_imm32.k index 127bcf860..e5418cf62 100644 --- a/semantics/immediateInstructions/orq_r64_imm32.k +++ b/semantics/immediateInstructions/orq_r64_imm32.k @@ -5,26 +5,27 @@ module ORQ-R64-IMM32 imports X86-CONFIGURATION rule - execinstr (orq Imm32:Imm, R2:R64, .Operands) => . + execinstr (orq Imm32:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> orMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) +convToRegKeys(R2) |-> orMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(Imm32))) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(Imm32))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)) +"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/orq_r64_imm8.k b/semantics/immediateInstructions/orq_r64_imm8.k index 2aa63623d..c086017f2 100644 --- a/semantics/immediateInstructions/orq_r64_imm8.k +++ b/semantics/immediateInstructions/orq_r64_imm8.k @@ -5,26 +5,27 @@ module ORQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (orq Imm8:Imm, R2:R64, .Operands) => . + execinstr (orq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> orMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) +convToRegKeys(R2) |-> orMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(Imm8))) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(Imm8))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/orq_rax_imm32.k b/semantics/immediateInstructions/orq_rax_imm32.k index 3dc8c82bb..e8759e7d4 100644 --- a/semantics/immediateInstructions/orq_rax_imm32.k +++ b/semantics/immediateInstructions/orq_rax_imm32.k @@ -5,26 +5,27 @@ module ORQ-RAX-IMM32 imports X86-CONFIGURATION rule - execinstr (orq Imm32:Imm, %rax, .Operands) => . + execinstr (orq Imm32:MInt, %rax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> orMInt( getParentValue(%rax, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) +"RAX" |-> orMInt( getParentValue(%rax, RSMap), mi(64, svalueMInt(Imm32))) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( getParentValue(%rax, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( getParentValue(%rax, RSMap), mi(64, svalueMInt(Imm32))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)) +"SF" |-> orMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/orw_ax_imm16.k b/semantics/immediateInstructions/orw_ax_imm16.k index 9be5a55b0..1b93b5fcd 100644 --- a/semantics/immediateInstructions/orw_ax_imm16.k +++ b/semantics/immediateInstructions/orw_ax_imm16.k @@ -5,26 +5,27 @@ module ORW-AX-IMM16 imports X86-CONFIGURATION rule - execinstr (orw Imm16:Imm, %ax, .Operands) => . + execinstr (orw Imm16:MInt, %ax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 48), orMInt( extractMInt( getParentValue(%rax, RSMap), 48, 64), handleImmediateWithSignExtend(Imm16, 16, 16))) +"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 48), orMInt( extractMInt( getParentValue(%rax, RSMap), 48, 64), Imm16)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 15, 16)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 14, 15)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 13, 14)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 12, 13)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 10, 11)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 9, 10)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm16, 15, 16)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm16, 14, 15)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm16, 13, 14)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm16, 12, 13)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm16, 11, 12)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm16, 10, 11)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm16, 9, 10)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm16, 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 48, 64), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(%rax, RSMap), 48, 64), Imm16), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)) +"SF" |-> orMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), extractMInt( Imm16, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/orw_r16_imm16.k b/semantics/immediateInstructions/orw_r16_imm16.k index 69c0d0b5c..415add486 100644 --- a/semantics/immediateInstructions/orw_r16_imm16.k +++ b/semantics/immediateInstructions/orw_r16_imm16.k @@ -5,26 +5,27 @@ module ORW-R16-IMM16 imports X86-CONFIGURATION rule - execinstr (orw Imm16:Imm, R2:R16, .Operands) => . + execinstr (orw Imm16:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), orMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), handleImmediateWithSignExtend(Imm16, 16, 16))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), orMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), Imm16)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 15, 16)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 14, 15)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 13, 14)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 12, 13)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 10, 11)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 9, 10)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm16, 15, 16)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm16, 14, 15)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm16, 13, 14)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm16, 12, 13)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm16, 11, 12)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm16, 10, 11)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm16, 9, 10)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm16, 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), Imm16), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)) +"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( Imm16, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/orw_r16_imm8.k b/semantics/immediateInstructions/orw_r16_imm8.k index 6ce996862..5c16b7b30 100644 --- a/semantics/immediateInstructions/orw_r16_imm8.k +++ b/semantics/immediateInstructions/orw_r16_imm8.k @@ -5,26 +5,27 @@ module ORW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (orw Imm8:Imm, R2:R16, .Operands) => . + execinstr (orw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), orMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), orMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(16, svalueMInt(Imm8)))) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(16, svalueMInt(Imm8))), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> orMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/palignr_xmm_xmm_imm8.k b/semantics/immediateInstructions/palignr_xmm_xmm_imm8.k index b28b23207..471323eac 100644 --- a/semantics/immediateInstructions/palignr_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/palignr_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module PALIGNR-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (palignr Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (palignr Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), extractMInt( getParentValue(R2, RSMap), 128, 256)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), uvalueMInt(mi(256, 3))))), 128, 256)) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), extractMInt( getParentValue(R2, RSMap), 128, 256)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), Imm8), uvalueMInt(mi(256, 3))))), 128, 256)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pblendw_xmm_xmm_imm8.k b/semantics/immediateInstructions/pblendw_xmm_xmm_imm8.k index f4bdb29d0..a6b216eb6 100644 --- a/semantics/immediateInstructions/pblendw_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/pblendw_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module PBLENDW-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (pblendw Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (pblendw Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 144) #else extractMInt( getParentValue(R2, RSMap), 128, 144) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 144, 160) #else extractMInt( getParentValue(R2, RSMap), 144, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 176) #else extractMInt( getParentValue(R2, RSMap), 160, 176) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 176, 192) #else extractMInt( getParentValue(R2, RSMap), 176, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 208) #else extractMInt( getParentValue(R2, RSMap), 192, 208) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 208, 224) #else extractMInt( getParentValue(R2, RSMap), 208, 224) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 240) #else extractMInt( getParentValue(R2, RSMap), 224, 240) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 240, 256) #else extractMInt( getParentValue(R2, RSMap), 240, 256) #fi))))))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 144) #else extractMInt( getParentValue(R2, RSMap), 128, 144) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 144, 160) #else extractMInt( getParentValue(R2, RSMap), 144, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 176) #else extractMInt( getParentValue(R2, RSMap), 160, 176) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 176, 192) #else extractMInt( getParentValue(R2, RSMap), 176, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 208) #else extractMInt( getParentValue(R2, RSMap), 192, 208) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 208, 224) #else extractMInt( getParentValue(R2, RSMap), 208, 224) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 240) #else extractMInt( getParentValue(R2, RSMap), 224, 240) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 240, 256) #else extractMInt( getParentValue(R2, RSMap), 240, 256) #fi))))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pclmulqdq_xmm_xmm_imm8.k b/semantics/immediateInstructions/pclmulqdq_xmm_xmm_imm8.k index 300dac9b0..0853b148d 100644 --- a/semantics/immediateInstructions/pclmulqdq_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/pclmulqdq_xmm_xmm_imm8.k @@ -49,15 +49,14 @@ module PCLMULQDQ-XMM-XMM-IMM8 TEMP2←SRC2 [127:64]; */ rule - execinstr (pclmulqdq Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => + execinstr (pclmulqdq Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => execinstr(pclmulqdq - selectSlice(getRegisterValue(R3, RSMap), handleImmediateWithSignExtend(Imm8, - 8, 8), 7, 64, 0), - selectSlice(getRegisterValue(R2, RSMap), handleImmediateWithSignExtend(Imm8, - 8, 8), 3, 64, 0), R3 + selectSlice(getRegisterValue(R3, RSMap), Imm8, 7, 64, 0), + selectSlice(getRegisterValue(R2, RSMap), Imm8, 3, 64, 0), R3 , .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (pclmulqdq TEMP1:MInt, TEMP2:MInt, R3:Xmm, .Operands) => diff --git a/semantics/immediateInstructions/pcmpestri_xmm_xmm_imm8.k b/semantics/immediateInstructions/pcmpestri_xmm_xmm_imm8.k index f5240fa90..e7f4be1ca 100644 --- a/semantics/immediateInstructions/pcmpestri_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/pcmpestri_xmm_xmm_imm8.k @@ -6,16 +6,17 @@ module PCMPESTRI-XMM-XMM-IMM8 // Find Limit Index rule - execinstr (pcmpestri Imm8:Imm, Xmm2:Xmm, Xmm1:Xmm, .Operands) => + execinstr (pcmpestri Imm8:MInt, Xmm2:Xmm, Xmm1:Xmm, .Operands) => execinstr (pcmpestri - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, getRegisterValue(Xmm2, RSMap), getRegisterValue(Xmm1, RSMap), - findLimitIndexE(getRegisterValue(Xmm2, RSMap), getRegisterValue(%rdx, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexE(getRegisterValue(Xmm2, RSMap), getRegisterValue(%rdx, RSMap), Imm8), + findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // pcmpestri 8'1 , 128'0 , 128'0 , 8'1 , 8'1 , 8'8 , 1'0 , 8'1 , .Operands diff --git a/semantics/immediateInstructions/pcmpestrm_xmm_xmm_imm8.k b/semantics/immediateInstructions/pcmpestrm_xmm_xmm_imm8.k index b3ece31d9..71661068d 100644 --- a/semantics/immediateInstructions/pcmpestrm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/pcmpestrm_xmm_xmm_imm8.k @@ -6,16 +6,17 @@ module PCMPESTRM-XMM-XMM-IMM8 // Find Limit Index rule - execinstr (pcmpestrm Imm8:Imm, Xmm2:Xmm, Xmm1:Xmm, .Operands) => + execinstr (pcmpestrm Imm8:MInt, Xmm2:Xmm, Xmm1:Xmm, .Operands) => execinstr (pcmpestrm - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, getRegisterValue(Xmm2, RSMap), getRegisterValue(Xmm1, RSMap), - findLimitIndexE(getRegisterValue(Xmm2, RSMap), getRegisterValue(%rdx, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexE(getRegisterValue(Xmm2, RSMap), getRegisterValue(%rdx, RSMap), Imm8), + findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // Find data size and interpretation rule diff --git a/semantics/immediateInstructions/pcmpistri_xmm_xmm_imm8.k b/semantics/immediateInstructions/pcmpistri_xmm_xmm_imm8.k index ef5b1777b..5e8630969 100644 --- a/semantics/immediateInstructions/pcmpistri_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/pcmpistri_xmm_xmm_imm8.k @@ -6,16 +6,17 @@ module PCMPISTRI-XMM-XMM-IMM8 // Find Limit Index rule - execinstr (pcmpistri Imm8:Imm, Xmm2:Xmm, Xmm1:Xmm, .Operands) => + execinstr (pcmpistri Imm8:MInt, Xmm2:Xmm, Xmm1:Xmm, .Operands) => execinstr (pcmpistri - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, getRegisterValue(Xmm2, RSMap), getRegisterValue(Xmm1, RSMap), - findLimitIndexI(getRegisterValue(Xmm2, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexI(getRegisterValue(Xmm1, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexI(getRegisterValue(Xmm2, RSMap), Imm8), + findLimitIndexI(getRegisterValue(Xmm1, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // Find data size and interpretation rule diff --git a/semantics/immediateInstructions/pcmpistrm_xmm_xmm_imm8.k b/semantics/immediateInstructions/pcmpistrm_xmm_xmm_imm8.k index 83616c053..5f54ea863 100644 --- a/semantics/immediateInstructions/pcmpistrm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/pcmpistrm_xmm_xmm_imm8.k @@ -6,16 +6,17 @@ module PCMPISTRM-XMM-XMM-IMM8 // Find Limit Index rule - execinstr (pcmpistrm Imm8:Imm, Xmm2:Xmm, Xmm1:Xmm, .Operands) => + execinstr (pcmpistrm Imm8:MInt, Xmm2:Xmm, Xmm1:Xmm, .Operands) => execinstr (pcmpistrm - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, getRegisterValue(Xmm2, RSMap), getRegisterValue(Xmm1, RSMap), - findLimitIndexI(getRegisterValue(Xmm2, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexI(getRegisterValue(Xmm1, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexI(getRegisterValue(Xmm2, RSMap), Imm8), + findLimitIndexI(getRegisterValue(Xmm1, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // Find data size and interpretation rule diff --git a/semantics/immediateInstructions/pextrb_r32_xmm_imm8.k b/semantics/immediateInstructions/pextrb_r32_xmm_imm8.k index fcc0aac02..1e4e7e063 100644 --- a/semantics/immediateInstructions/pextrb_r32_xmm_imm8.k +++ b/semantics/immediateInstructions/pextrb_r32_xmm_imm8.k @@ -5,14 +5,15 @@ module PEXTRB-R32-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (pextrb Imm8:Imm, R2:Xmm, R3:R32, .Operands) => . + execinstr (pextrb Imm8:MInt, R2:Xmm, R3:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(56, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3))))), 120, 128)) +convToRegKeys(R3) |-> concatenateMInt( mi(56, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3))))), 120, 128)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pextrb_r64_xmm_imm8.k b/semantics/immediateInstructions/pextrb_r64_xmm_imm8.k index c5a5d0f72..884104a0b 100644 --- a/semantics/immediateInstructions/pextrb_r64_xmm_imm8.k +++ b/semantics/immediateInstructions/pextrb_r64_xmm_imm8.k @@ -5,14 +5,15 @@ module PEXTRB-R64-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (pextrb Imm8:Imm, R2:Xmm, R3:R64, .Operands) => . + execinstr (pextrb Imm8:MInt, R2:Xmm, R3:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(56, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3))))), 120, 128)) +convToRegKeys(R3) |-> concatenateMInt( mi(56, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3))))), 120, 128)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pextrd_r32_xmm_imm8.k b/semantics/immediateInstructions/pextrd_r32_xmm_imm8.k index d955bd640..95448d3b5 100644 --- a/semantics/immediateInstructions/pextrd_r32_xmm_imm8.k +++ b/semantics/immediateInstructions/pextrd_r32_xmm_imm8.k @@ -5,14 +5,15 @@ module PEXTRD-R32-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (pextrd Imm8:Imm, R2:Xmm, R3:R32, .Operands) => . + execinstr (pextrd Imm8:MInt, R2:Xmm, R3:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128)) +convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pextrq_r64_xmm_imm8.k b/semantics/immediateInstructions/pextrq_r64_xmm_imm8.k index 93a1a246b..9e2f02047 100644 --- a/semantics/immediateInstructions/pextrq_r64_xmm_imm8.k +++ b/semantics/immediateInstructions/pextrq_r64_xmm_imm8.k @@ -5,14 +5,15 @@ module PEXTRQ-R64-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (pextrq Imm8:Imm, R2:Xmm, R3:R64, .Operands) => . + execinstr (pextrq Imm8:MInt, R2:Xmm, R3:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6))))), 64, 128) +convToRegKeys(R3) |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6))))), 64, 128) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pextrw_r32_xmm_imm8.k b/semantics/immediateInstructions/pextrw_r32_xmm_imm8.k index 47edbf2b0..a8af52190 100644 --- a/semantics/immediateInstructions/pextrw_r32_xmm_imm8.k +++ b/semantics/immediateInstructions/pextrw_r32_xmm_imm8.k @@ -5,14 +5,15 @@ module PEXTRW-R32-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (pextrw Imm8:Imm, R2:Xmm, R3:R32, .Operands) => . + execinstr (pextrw Imm8:MInt, R2:Xmm, R3:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(48, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4))))), 112, 128)) +convToRegKeys(R3) |-> concatenateMInt( mi(48, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4))))), 112, 128)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pextrw_r64_xmm_imm8.k b/semantics/immediateInstructions/pextrw_r64_xmm_imm8.k index 7d1b9d840..b4ad0a368 100644 --- a/semantics/immediateInstructions/pextrw_r64_xmm_imm8.k +++ b/semantics/immediateInstructions/pextrw_r64_xmm_imm8.k @@ -5,14 +5,15 @@ module PEXTRW-R64-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (pextrw Imm8:Imm, R2:Xmm, R3:R64, .Operands) => . + execinstr (pextrw Imm8:MInt, R2:Xmm, R3:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(48, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4))))), 112, 128)) +convToRegKeys(R3) |-> concatenateMInt( mi(48, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4))))), 112, 128)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pinsrb_xmm_r32_imm8.k b/semantics/immediateInstructions/pinsrb_xmm_r32_imm8.k index bda1687b8..53c3ef516 100644 --- a/semantics/immediateInstructions/pinsrb_xmm_r32_imm8.k +++ b/semantics/immediateInstructions/pinsrb_xmm_r32_imm8.k @@ -5,14 +5,15 @@ module PINSRB-XMM-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (pinsrb Imm8:Imm, R2:R32, R3:Xmm, .Operands) => . + execinstr (pinsrb Imm8:MInt, R2:R32, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3))))), shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3)))))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3))))), shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pinsrd_xmm_r32_imm8.k b/semantics/immediateInstructions/pinsrd_xmm_r32_imm8.k index 8a3be75ba..30f9332e3 100644 --- a/semantics/immediateInstructions/pinsrd_xmm_r32_imm8.k +++ b/semantics/immediateInstructions/pinsrd_xmm_r32_imm8.k @@ -5,14 +5,15 @@ module PINSRD-XMM-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (pinsrd Imm8:Imm, R2:R32, R3:Xmm, .Operands) => . + execinstr (pinsrd Imm8:MInt, R2:R32, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5)))))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pinsrq_xmm_r64_imm8.k b/semantics/immediateInstructions/pinsrq_xmm_r64_imm8.k index 2d4809e9f..a29d34cb3 100644 --- a/semantics/immediateInstructions/pinsrq_xmm_r64_imm8.k +++ b/semantics/immediateInstructions/pinsrq_xmm_r64_imm8.k @@ -5,13 +5,14 @@ module PINSRQ-XMM-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (pinsrq Imm8:Imm, R2:R64, R3:Xmm .Operands) => . + execinstr (pinsrq Imm8:MInt, R2:R64, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(64, 0), getParentValue(R2, RSMap)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6))))), shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6)))))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(64, 0), getParentValue(R2, RSMap)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6))))), shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pinsrw_xmm_r32_imm8.k b/semantics/immediateInstructions/pinsrw_xmm_r32_imm8.k index 272fdcb42..ca70f970d 100644 --- a/semantics/immediateInstructions/pinsrw_xmm_r32_imm8.k +++ b/semantics/immediateInstructions/pinsrw_xmm_r32_imm8.k @@ -5,14 +5,15 @@ module PINSRW-XMM-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (pinsrw Imm8:Imm, R2:R32, R3:Xmm, .Operands) => . + execinstr (pinsrw Imm8:MInt, R2:R32, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4))))), shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4)))))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4))))), shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pshufd_xmm_xmm_imm8.k b/semantics/immediateInstructions/pshufd_xmm_xmm_imm8.k index a554cd2b7..43d1089c6 100644 --- a/semantics/immediateInstructions/pshufd_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/pshufd_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module PSHUFD-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (pshufd Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (pshufd Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pshufhw_xmm_xmm_imm8.k b/semantics/immediateInstructions/pshufhw_xmm_xmm_imm8.k index 978de61d5..3e0456fe3 100644 --- a/semantics/immediateInstructions/pshufhw_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/pshufhw_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module PSHUFHW-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (pshufhw Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (pshufhw Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 4))))), 48, 64), extractMInt( getParentValue(R2, RSMap), 192, 256)))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 4))))), 48, 64), extractMInt( getParentValue(R2, RSMap), 192, 256)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pshuflw_xmm_xmm_imm8.k b/semantics/immediateInstructions/pshuflw_xmm_xmm_imm8.k index 8c53a8222..09abf1203 100644 --- a/semantics/immediateInstructions/pshuflw_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/pshuflw_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module PSHUFLW-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (pshuflw Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (pshuflw Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 4))))), 112, 128), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 4))))), 112, 128)))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 4))))), 112, 128), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 4))))), 112, 128)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pslld_xmm_imm8.k b/semantics/immediateInstructions/pslld_xmm_imm8.k index 2bde9c34b..1195b4be7 100644 --- a/semantics/immediateInstructions/pslld_xmm_imm8.k +++ b/semantics/immediateInstructions/pslld_xmm_imm8.k @@ -5,14 +5,15 @@ module PSLLD-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (pslld Imm8:Imm, R2:Xmm, .Operands) => . + execinstr (pslld Imm8:MInt, R2:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(128, 0) #else concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8))))))) #fi)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(128, 0) #else concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt(concatenateMInt( mi(24, 0), Imm8)))))) #fi)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pslldq_xmm_imm8.k b/semantics/immediateInstructions/pslldq_xmm_imm8.k index 6f44cfd8f..c365871eb 100644 --- a/semantics/immediateInstructions/pslldq_xmm_imm8.k +++ b/semantics/immediateInstructions/pslldq_xmm_imm8.k @@ -5,14 +5,15 @@ module PSLLDQ-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (pslldq Imm8:Imm, R2:Xmm, .Operands) => . + execinstr (pslldq Imm8:MInt, R2:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), uvalueMInt(mi(128, 3)))))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( Imm8, mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), Imm8) #fi), uvalueMInt(mi(128, 3)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/psllq_xmm_imm8.k b/semantics/immediateInstructions/psllq_xmm_imm8.k index ae6725194..9dce7d6cf 100644 --- a/semantics/immediateInstructions/psllq_xmm_imm8.k +++ b/semantics/immediateInstructions/psllq_xmm_imm8.k @@ -5,14 +5,15 @@ module PSLLQ-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (psllq Imm8:Imm, R2:Xmm, .Operands) => . + execinstr (psllq Imm8:MInt, R2:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 63)) #then mi(128, 0) #else concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 256), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8))))) #fi)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 63)) #then mi(128, 0) #else concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), uvalueMInt(concatenateMInt( mi(56, 0), Imm8))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 256), uvalueMInt(concatenateMInt( mi(56, 0), Imm8)))) #fi)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/psllw_xmm_imm8.k b/semantics/immediateInstructions/psllw_xmm_imm8.k index b233d1eff..dc461e5e1 100644 --- a/semantics/immediateInstructions/psllw_xmm_imm8.k +++ b/semantics/immediateInstructions/psllw_xmm_imm8.k @@ -5,14 +5,15 @@ module PSLLW-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (psllw Imm8:Imm, R2:Xmm, .Operands) => . + execinstr (psllw Imm8:MInt, R2:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(128, 0) #else concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8))))))))))) #fi)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(128, 0) #else concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt(concatenateMInt( mi(8, 0), Imm8)))))))))) #fi)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/psrad_xmm_imm8.k b/semantics/immediateInstructions/psrad_xmm_imm8.k index d90474807..3f1defe46 100644 --- a/semantics/immediateInstructions/psrad_xmm_imm8.k +++ b/semantics/immediateInstructions/psrad_xmm_imm8.k @@ -5,14 +5,15 @@ module PSRAD-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (psrad Imm8:Imm, R2:Xmm, .Operands) => . + execinstr (psrad Imm8:MInt, R2:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))))))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi))), aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/psraw_xmm_imm8.k b/semantics/immediateInstructions/psraw_xmm_imm8.k index 679082020..f9529c0ed 100644 --- a/semantics/immediateInstructions/psraw_xmm_imm8.k +++ b/semantics/immediateInstructions/psraw_xmm_imm8.k @@ -5,14 +5,15 @@ module PSRAW-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (psraw Imm8:Imm, R2:Xmm, .Operands) => . + execinstr (psraw Imm8:MInt, R2:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))))))))))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))))))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/psrld_xmm_imm8.k b/semantics/immediateInstructions/psrld_xmm_imm8.k index 776ad7486..3580b50ed 100644 --- a/semantics/immediateInstructions/psrld_xmm_imm8.k +++ b/semantics/immediateInstructions/psrld_xmm_imm8.k @@ -5,14 +5,15 @@ module PSRLD-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (psrld Imm8:Imm, R2:Xmm, .Operands) => . + execinstr (psrld Imm8:MInt, R2:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(128, 0) #else concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8))))))) #fi)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(128, 0) #else concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt(concatenateMInt( mi(24, 0), Imm8)))))) #fi)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/psrldq_xmm_imm8.k b/semantics/immediateInstructions/psrldq_xmm_imm8.k index 9bcb50167..f08003628 100644 --- a/semantics/immediateInstructions/psrldq_xmm_imm8.k +++ b/semantics/immediateInstructions/psrldq_xmm_imm8.k @@ -5,14 +5,15 @@ module PSRLDQ-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (psrldq Imm8:Imm, R2:Xmm, .Operands) => . + execinstr (psrldq Imm8:MInt, R2:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), uvalueMInt(mi(128, 3)))))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( Imm8, mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), Imm8) #fi), uvalueMInt(mi(128, 3)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/psrlq_xmm_imm8.k b/semantics/immediateInstructions/psrlq_xmm_imm8.k index 978a3fccf..023b4a50e 100644 --- a/semantics/immediateInstructions/psrlq_xmm_imm8.k +++ b/semantics/immediateInstructions/psrlq_xmm_imm8.k @@ -5,14 +5,15 @@ module PSRLQ-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (psrlq Imm8:Imm, R2:Xmm, .Operands) => . + execinstr (psrlq Imm8:MInt, R2:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 63)) #then mi(128, 0) #else concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 256), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8))))) #fi)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 63)) #then mi(128, 0) #else concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), uvalueMInt(concatenateMInt( mi(56, 0), Imm8))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 256), uvalueMInt(concatenateMInt( mi(56, 0), Imm8)))) #fi)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/psrlw_xmm_imm8.k b/semantics/immediateInstructions/psrlw_xmm_imm8.k index 6886c12b8..67ccc89a2 100644 --- a/semantics/immediateInstructions/psrlw_xmm_imm8.k +++ b/semantics/immediateInstructions/psrlw_xmm_imm8.k @@ -5,14 +5,15 @@ module PSRLW-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (psrlw Imm8:Imm, R2:Xmm, .Operands) => . + execinstr (psrlw Imm8:MInt, R2:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(128, 0) #else concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8))))))))))) #fi)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(128, 0) #else concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt(concatenateMInt( mi(8, 0), Imm8)))))))))) #fi)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/pushq_imm32.k b/semantics/immediateInstructions/pushq_imm32.k index 143e8b115..08b4e40fd 100644 --- a/semantics/immediateInstructions/pushq_imm32.k +++ b/semantics/immediateInstructions/pushq_imm32.k @@ -11,12 +11,13 @@ module PUSHQ-IMM32 imports X86-CONFIGURATION rule - execinstr (pushq Imm32:Imm, .Operands) => + execinstr (pushq Imm32:MInt, .Operands) => storeToMemory( - handleImmediateWithSignExtend(Imm32, 32, 64), + signExtend(Imm32, 64), subMInt(getRegisterValue(%rsp, RSMap), mi(64, 8)), 64) ~> decRSPInBytes(8) ... RSMap + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/rclb_r8_imm8.k b/semantics/immediateInstructions/rclb_r8_imm8.k index 5913211ac..aeefc7462 100644 --- a/semantics/immediateInstructions/rclb_r8_imm8.k +++ b/semantics/immediateInstructions/rclb_r8_imm8.k @@ -5,18 +5,19 @@ module RCLB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (rclb Imm8:Imm, R2:R8, .Operands) => . + execinstr (rclb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 1, 9)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 1, 9)) -"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 0, 1) +"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rclb_rh_imm8.k b/semantics/immediateInstructions/rclb_rh_imm8.k index b2c83cd3a..e7e153a83 100644 --- a/semantics/immediateInstructions/rclb_rh_imm8.k +++ b/semantics/immediateInstructions/rclb_rh_imm8.k @@ -5,18 +5,19 @@ module RCLB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (rclb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (rclb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) -"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 0, 1) +"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rcll_r32_imm8.k b/semantics/immediateInstructions/rcll_r32_imm8.k index 55e61300a..3101cb06a 100644 --- a/semantics/immediateInstructions/rcll_r32_imm8.k +++ b/semantics/immediateInstructions/rcll_r32_imm8.k @@ -5,18 +5,19 @@ module RCLL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (rcll Imm8:Imm, R2:R32, .Operands) => . + execinstr (rcll Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 1, 33)) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 1, 33)) -"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 0, 1) +"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rclq_r64_imm8.k b/semantics/immediateInstructions/rclq_r64_imm8.k index 6db2c8413..13acfe879 100644 --- a/semantics/immediateInstructions/rclq_r64_imm8.k +++ b/semantics/immediateInstructions/rclq_r64_imm8.k @@ -5,18 +5,19 @@ module RCLQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (rclq Imm8:Imm, R2:R64, .Operands) => . + execinstr (rclq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 1, 65) +convToRegKeys(R2) |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 1, 65) -"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 0, 1) +"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rclw_r16_imm8.k b/semantics/immediateInstructions/rclw_r16_imm8.k index 9e404c89b..e95041838 100644 --- a/semantics/immediateInstructions/rclw_r16_imm8.k +++ b/semantics/immediateInstructions/rclw_r16_imm8.k @@ -5,18 +5,19 @@ module RCLW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (rclw Imm8:Imm, R2:R16, .Operands) => . + execinstr (rclw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 1, 17)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 1, 17)) -"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 0, 1) +"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rcrb_r8_imm8.k b/semantics/immediateInstructions/rcrb_r8_imm8.k index 1c33bd062..8e92aec8e 100644 --- a/semantics/immediateInstructions/rcrb_r8_imm8.k +++ b/semantics/immediateInstructions/rcrb_r8_imm8.k @@ -5,18 +5,19 @@ module RCRB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (rcrb Imm8:Imm, R2:R8, .Operands) => . + execinstr (rcrb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 1, 9)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 1, 9)) -"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 0, 1) +"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 56, 64)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rcrb_rh_imm8.k b/semantics/immediateInstructions/rcrb_rh_imm8.k index a85daf27c..e72b8197c 100644 --- a/semantics/immediateInstructions/rcrb_rh_imm8.k +++ b/semantics/immediateInstructions/rcrb_rh_imm8.k @@ -5,18 +5,19 @@ module RCRB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (rcrb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (rcrb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) -"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 0, 1) +"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 56)), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rcrl_r32_imm8.k b/semantics/immediateInstructions/rcrl_r32_imm8.k index 9679a672b..f97273ee8 100644 --- a/semantics/immediateInstructions/rcrl_r32_imm8.k +++ b/semantics/immediateInstructions/rcrl_r32_imm8.k @@ -5,18 +5,19 @@ module RCRL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (rcrl Imm8:Imm, R2:R32, .Operands) => . + execinstr (rcrl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 1, 33)) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 1, 33)) -"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 0, 1) +"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 32, 64)), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rcrq_r64_imm8.k b/semantics/immediateInstructions/rcrq_r64_imm8.k index 07b09df9a..432f62fde 100644 --- a/semantics/immediateInstructions/rcrq_r64_imm8.k +++ b/semantics/immediateInstructions/rcrq_r64_imm8.k @@ -5,18 +5,19 @@ module RCRQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (rcrq Imm8:Imm, R2:R64, .Operands) => . + execinstr (rcrq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 1, 65) +convToRegKeys(R2) |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 1, 65) -"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 0, 1) +"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), getParentValue(R2, RSMap)), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rcrw_r16_imm8.k b/semantics/immediateInstructions/rcrw_r16_imm8.k index f55eb46d2..b245ac699 100644 --- a/semantics/immediateInstructions/rcrw_r16_imm8.k +++ b/semantics/immediateInstructions/rcrw_r16_imm8.k @@ -5,18 +5,19 @@ module RCRW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (rcrw Imm8:Imm, R2:R16, .Operands) => . + execinstr (rcrw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 1, 17)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 1, 17)) -"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 0, 1) +"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), extractMInt( getParentValue(R2, RSMap), 48, 64)), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rolb_r8_imm8.k b/semantics/immediateInstructions/rolb_r8_imm8.k index a7f9e8fef..d697829d7 100644 --- a/semantics/immediateInstructions/rolb_r8_imm8.k +++ b/semantics/immediateInstructions/rolb_r8_imm8.k @@ -5,18 +5,19 @@ module ROLB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (rolb Imm8:Imm, R2:R8, .Operands) => . + execinstr (rolb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), rol( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), rol( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( Imm8, mi(8, 31)))) -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 7, 8), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( Imm8, mi(8, 31))), 7, 8), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 7, 8), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( Imm8, mi(8, 31))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( Imm8, mi(8, 31))), 7, 8), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rolb_rh_imm8.k b/semantics/immediateInstructions/rolb_rh_imm8.k index 8c0a498c8..ccbadbef3 100644 --- a/semantics/immediateInstructions/rolb_rh_imm8.k +++ b/semantics/immediateInstructions/rolb_rh_imm8.k @@ -5,18 +5,19 @@ module ROLB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (rolb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (rolb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), rol( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), rol( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( Imm8, mi(8, 31)))), extractMInt( getParentValue(R2, RSMap), 56, 64)) -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 7, 8), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( Imm8, mi(8, 31))), 7, 8), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 7, 8), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( Imm8, mi(8, 31))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( Imm8, mi(8, 31))), 7, 8), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/roll_r32_imm8.k b/semantics/immediateInstructions/roll_r32_imm8.k index c296aea97..8fef9cbdf 100644 --- a/semantics/immediateInstructions/roll_r32_imm8.k +++ b/semantics/immediateInstructions/roll_r32_imm8.k @@ -5,18 +5,19 @@ module ROLL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (roll Imm8:Imm, R2:R32, .Operands) => . + execinstr (roll Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), rol( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), rol( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31))))) -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 31, 32), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31)))), 31, 32), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 31, 32), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31)))), 31, 32), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rolq_r64_imm8.k b/semantics/immediateInstructions/rolq_r64_imm8.k index 429dd98c4..2017e2538 100644 --- a/semantics/immediateInstructions/rolq_r64_imm8.k +++ b/semantics/immediateInstructions/rolq_r64_imm8.k @@ -5,18 +5,19 @@ module ROLQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (rolq Imm8:Imm, R2:R64, .Operands) => . + execinstr (rolq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> rol( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))) +convToRegKeys(R2) |-> rol( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))) -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( rol( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))), 63, 64), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( rol( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))), 63, 64), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))), 63, 64), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))), 63, 64), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rolw_r16_imm8.k b/semantics/immediateInstructions/rolw_r16_imm8.k index 609fe7062..7a26343f5 100644 --- a/semantics/immediateInstructions/rolw_r16_imm8.k +++ b/semantics/immediateInstructions/rolw_r16_imm8.k @@ -5,18 +5,19 @@ module ROLW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (rolw Imm8:Imm, R2:R16, .Operands) => . + execinstr (rolw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), rol( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), rol( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31))))) -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 15, 16), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31)))), 15, 16), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 15, 16), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31)))), 15, 16), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rorb_r8_imm8.k b/semantics/immediateInstructions/rorb_r8_imm8.k index ccb445c16..6b68e25b3 100644 --- a/semantics/immediateInstructions/rorb_r8_imm8.k +++ b/semantics/immediateInstructions/rorb_r8_imm8.k @@ -5,18 +5,19 @@ module RORB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (rorb Imm8:Imm, R2:R8, .Operands) => . + execinstr (rorb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), ror( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), ror( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( Imm8, mi(8, 31)))) -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( Imm8, mi(8, 31))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( Imm8, mi(8, 31))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 56, 64), andMInt( Imm8, mi(8, 31))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rorb_rh_imm8.k b/semantics/immediateInstructions/rorb_rh_imm8.k index 82fccc58e..052e5e515 100644 --- a/semantics/immediateInstructions/rorb_rh_imm8.k +++ b/semantics/immediateInstructions/rorb_rh_imm8.k @@ -5,18 +5,19 @@ module RORB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (rorb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (rorb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), ror( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), ror( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( Imm8, mi(8, 31)))), extractMInt( getParentValue(R2, RSMap), 56, 64)) -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( Imm8, mi(8, 31))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( Imm8, mi(8, 31))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 48, 56), andMInt( Imm8, mi(8, 31))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rorl_r32_imm8.k b/semantics/immediateInstructions/rorl_r32_imm8.k index 357200c7b..5cc890f4e 100644 --- a/semantics/immediateInstructions/rorl_r32_imm8.k +++ b/semantics/immediateInstructions/rorl_r32_imm8.k @@ -5,18 +5,19 @@ module RORL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (rorl Imm8:Imm, R2:R32, .Operands) => . + execinstr (rorl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), ror( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), ror( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31))))) -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31)))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 32, 64), concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31)))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rorq_r64_imm8.k b/semantics/immediateInstructions/rorq_r64_imm8.k index da211c3f5..562b26a64 100644 --- a/semantics/immediateInstructions/rorq_r64_imm8.k +++ b/semantics/immediateInstructions/rorq_r64_imm8.k @@ -5,18 +5,19 @@ module RORQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (rorq Imm8:Imm, R2:R64, .Operands) => . + execinstr (rorq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> ror( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))) +convToRegKeys(R2) |-> ror( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))) -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( ror( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( ror( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( getParentValue(R2, RSMap), concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rorw_r16_imm8.k b/semantics/immediateInstructions/rorw_r16_imm8.k index d1236b28a..fd8e8c85f 100644 --- a/semantics/immediateInstructions/rorw_r16_imm8.k +++ b/semantics/immediateInstructions/rorw_r16_imm8.k @@ -5,18 +5,19 @@ module RORW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (rorw Imm8:Imm, R2:R16, .Operands) => . + execinstr (rorw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), ror( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), ror( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31))))) -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31)))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( extractMInt( getParentValue(R2, RSMap), 48, 64), concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31)))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rorxl_r32_r32_imm8.k b/semantics/immediateInstructions/rorxl_r32_r32_imm8.k index bfe177a88..b76598261 100644 --- a/semantics/immediateInstructions/rorxl_r32_r32_imm8.k +++ b/semantics/immediateInstructions/rorxl_r32_r32_imm8.k @@ -5,17 +5,18 @@ module RORXL-R32-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (rorx Imm8:Imm, R2:R32, R3:R32, .Operands) => execinstr (rorxl Imm8:Imm, R2:R32, R3:R32, .Operands) + execinstr (rorx Imm8:MInt, R2:R32, R3:R32, .Operands) => execinstr (rorxl Imm8:MInt, R2:R32, R3:R32, .Operands) ... rule - execinstr (rorxl Imm8:Imm, R2:R32, R3:R32, .Operands) => . + execinstr (rorxl Imm8:MInt, R2:R32, R3:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), orMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(andMInt( concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(32, 31)))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(subMInt( mi(32, 32), andMInt( concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(32, 31))))))) +convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), orMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(andMInt( concatenateMInt( mi(24, 0), Imm8), mi(32, 31)))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(subMInt( mi(32, 32), andMInt( concatenateMInt( mi(24, 0), Imm8), mi(32, 31))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/rorxq_r64_r64_imm8.k b/semantics/immediateInstructions/rorxq_r64_r64_imm8.k index 9fd93462f..8f983cc46 100644 --- a/semantics/immediateInstructions/rorxq_r64_r64_imm8.k +++ b/semantics/immediateInstructions/rorxq_r64_r64_imm8.k @@ -5,18 +5,19 @@ module RORXQ-R64-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (rorx Imm8:Imm, R2:R64, R3:R64, .Operands) => execinstr (rorxq Imm8:Imm, R2:R64, R3:R64, .Operands) + execinstr (rorx Imm8:MInt, R2:R64, R3:R64, .Operands) => execinstr (rorxq Imm8:MInt, R2:R64, R3:R64, .Operands) ... rule - execinstr (rorxq Imm8:Imm, R2:R64, R3:R64, .Operands) => . + execinstr (rorxq Imm8:MInt, R2:R64, R3:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> orMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(andMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 63)))), shiftLeftMInt( getParentValue(R2, RSMap), uvalueMInt(subMInt( mi(64, 64), andMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 63)))))) +convToRegKeys(R3) |-> orMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(andMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 63)))), shiftLeftMInt( getParentValue(R2, RSMap), uvalueMInt(subMInt( mi(64, 64), andMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 63)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/roundpd_xmm_xmm_imm8.k b/semantics/immediateInstructions/roundpd_xmm_xmm_imm8.k index 3d905be1e..64d633062 100644 --- a/semantics/immediateInstructions/roundpd_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/roundpd_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module ROUNDPD-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (roundpd Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (roundpd Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 128, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 192, 256), handleImmediateWithSignExtend(Imm8, 8, 8)))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 128, 192), Imm8), cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 192, 256), Imm8))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/roundps_xmm_xmm_imm8.k b/semantics/immediateInstructions/roundps_xmm_xmm_imm8.k index 01122c836..2b65954aa 100644 --- a/semantics/immediateInstructions/roundps_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/roundps_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module ROUNDPS-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (roundps Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (roundps Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 128, 160), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 160, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 192, 224), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8)))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 128, 160), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 160, 192), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 192, 224), Imm8), cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), Imm8))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/roundsd_xmm_xmm_imm8.k b/semantics/immediateInstructions/roundsd_xmm_xmm_imm8.k index ac19aef92..b9a39369a 100644 --- a/semantics/immediateInstructions/roundsd_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/roundsd_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module ROUNDSD-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (roundsd Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (roundsd Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 192), cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 192, 256), handleImmediateWithSignExtend(Imm8, 8, 8))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 192), cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 192, 256), Imm8)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/roundss_xmm_xmm_imm8.k b/semantics/immediateInstructions/roundss_xmm_xmm_imm8.k index 1b4627a59..c9cb2ebcd 100644 --- a/semantics/immediateInstructions/roundss_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/roundss_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module ROUNDSS-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (roundss Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (roundss Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 224), cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 224), cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), Imm8)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/salb_r8_imm8.k b/semantics/immediateInstructions/salb_r8_imm8.k index eb1b8d658..731d7b207 100644 --- a/semantics/immediateInstructions/salb_r8_imm8.k +++ b/semantics/immediateInstructions/salb_r8_imm8.k @@ -5,26 +5,27 @@ module SALB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (salb Imm8:Imm, R2:R8, .Operands) => . + execinstr (salb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 9)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 9)) -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 9), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 9), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/salb_rh_imm8.k b/semantics/immediateInstructions/salb_rh_imm8.k index 18f26de8b..481c601af 100644 --- a/semantics/immediateInstructions/salb_rh_imm8.k +++ b/semantics/immediateInstructions/salb_rh_imm8.k @@ -5,26 +5,27 @@ module SALB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (salb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (salb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 9), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 9), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/sall_r32_imm8.k b/semantics/immediateInstructions/sall_r32_imm8.k index bd70d5bca..fc371c96a 100644 --- a/semantics/immediateInstructions/sall_r32_imm8.k +++ b/semantics/immediateInstructions/sall_r32_imm8.k @@ -5,26 +5,27 @@ module SALL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (sall Imm8:Imm, R2:R32, .Operands) => . + execinstr (sall Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 33)) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 33)) -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 25, 26), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 25, 26), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 33), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 33), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/salq_r64_imm8.k b/semantics/immediateInstructions/salq_r64_imm8.k index a97ab3904..b6a9da66f 100644 --- a/semantics/immediateInstructions/salq_r64_imm8.k +++ b/semantics/immediateInstructions/salq_r64_imm8.k @@ -5,26 +5,27 @@ module SALQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (salq Imm8:Imm, R2:R64, .Operands) => . + execinstr (salq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 65) +convToRegKeys(R2) |-> extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 65) -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 57, 58), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 57, 58), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 65), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 65), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/salw_r16_imm8.k b/semantics/immediateInstructions/salw_r16_imm8.k index daf6db4bc..3b91e6f6c 100644 --- a/semantics/immediateInstructions/salw_r16_imm8.k +++ b/semantics/immediateInstructions/salw_r16_imm8.k @@ -5,26 +5,27 @@ module SALW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (salw Imm8:Imm, R2:R16, .Operands) => . + execinstr (salw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 17)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 17)) -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 9, 10), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 9, 10), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 17), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 17), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/sarb_r8_imm8.k b/semantics/immediateInstructions/sarb_r8_imm8.k index aaa4f3119..33b127101 100644 --- a/semantics/immediateInstructions/sarb_r8_imm8.k +++ b/semantics/immediateInstructions/sarb_r8_imm8.k @@ -5,26 +5,27 @@ module SARB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (sarb Imm8:Imm, R2:R8, .Operands) => . + execinstr (sarb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 8)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 8)) -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 7, 8), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 7, 8), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 8), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 8), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/sarb_rh_imm8.k b/semantics/immediateInstructions/sarb_rh_imm8.k index a2bbb2422..484dbfa75 100644 --- a/semantics/immediateInstructions/sarb_rh_imm8.k +++ b/semantics/immediateInstructions/sarb_rh_imm8.k @@ -5,26 +5,27 @@ module SARB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (sarb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (sarb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 8)), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 8)), extractMInt( getParentValue(R2, RSMap), 56, 64)) -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 7, 8), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 7, 8), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 8), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 8), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/sarl_r32_imm8.k b/semantics/immediateInstructions/sarl_r32_imm8.k index 3c8ca235a..1d500a865 100644 --- a/semantics/immediateInstructions/sarl_r32_imm8.k +++ b/semantics/immediateInstructions/sarl_r32_imm8.k @@ -5,26 +5,27 @@ module SARL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (sarl Imm8:Imm, R2:R32, .Operands) => . + execinstr (sarl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 32)) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 32)) -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 32, 33), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 32, 33), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 31, 32), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 25, 26), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 24, 25), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 31, 32), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 25, 26), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 24, 25), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 32), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 32), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/sarq_r64_imm8.k b/semantics/immediateInstructions/sarq_r64_imm8.k index abe87b6c5..c1ddcbc44 100644 --- a/semantics/immediateInstructions/sarq_r64_imm8.k +++ b/semantics/immediateInstructions/sarq_r64_imm8.k @@ -5,26 +5,27 @@ module SARQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (sarq Imm8:Imm, R2:R64, .Operands) => . + execinstr (sarq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 64) +convToRegKeys(R2) |-> extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 64) -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 64, 65), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 64, 65), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 63, 64), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 57, 58), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 56, 57), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 63, 64), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 57, 58), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 56, 57), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 64), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 64), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/sarw_r16_imm8.k b/semantics/immediateInstructions/sarw_r16_imm8.k index b95200220..47c91a2eb 100644 --- a/semantics/immediateInstructions/sarw_r16_imm8.k +++ b/semantics/immediateInstructions/sarw_r16_imm8.k @@ -5,26 +5,27 @@ module SARW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (sarw Imm8:Imm, R2:R16, .Operands) => . + execinstr (sarw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 16)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 16)) -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 16, 17), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 16, 17), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 15, 16), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 9, 10), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 15, 16), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 9, 10), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 16), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 16), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/sbbb_al_imm8.k b/semantics/immediateInstructions/sbbb_al_imm8.k index b284f3086..7aa8d8a4a 100644 --- a/semantics/immediateInstructions/sbbb_al_imm8.k +++ b/semantics/immediateInstructions/sbbb_al_imm8.k @@ -5,26 +5,27 @@ module SBBB-AL-IMM8 imports X86-CONFIGURATION rule - execinstr (sbbb Imm8:Imm, %al, .Operands) => . + execinstr (sbbb Imm8:MInt, %al, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 56), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9)) +"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 56), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/sbbb_r8_imm8.k b/semantics/immediateInstructions/sbbb_r8_imm8.k index da7c9cc6f..02f1b4a23 100644 --- a/semantics/immediateInstructions/sbbb_r8_imm8.k +++ b/semantics/immediateInstructions/sbbb_r8_imm8.k @@ -5,26 +5,27 @@ module SBBB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (sbbb Imm8:Imm, R2:R8, .Operands) => . + execinstr (sbbb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/sbbb_rh_imm8.k b/semantics/immediateInstructions/sbbb_rh_imm8.k index aa2791741..cf51a6ad0 100644 --- a/semantics/immediateInstructions/sbbb_rh_imm8.k +++ b/semantics/immediateInstructions/sbbb_rh_imm8.k @@ -5,26 +5,27 @@ module SBBB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (sbbb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (sbbb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 51, 52)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 51, 52)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/sbbl_eax_imm32.k b/semantics/immediateInstructions/sbbl_eax_imm32.k index 144e8571d..2f8281dcb 100644 --- a/semantics/immediateInstructions/sbbl_eax_imm32.k +++ b/semantics/immediateInstructions/sbbl_eax_imm32.k @@ -5,26 +5,27 @@ module SBBL-EAX-IMM32 imports X86-CONFIGURATION rule - execinstr (sbbl Imm32:Imm, %eax, .Operands) => . + execinstr (sbbl Imm32:MInt, %eax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33)) +"RAX" |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/sbbl_r32_imm32.k b/semantics/immediateInstructions/sbbl_r32_imm32.k index 4cea53199..c84bf62d0 100644 --- a/semantics/immediateInstructions/sbbl_r32_imm32.k +++ b/semantics/immediateInstructions/sbbl_r32_imm32.k @@ -5,26 +5,27 @@ module SBBL-R32-IMM32 imports X86-CONFIGURATION rule - execinstr (sbbl Imm32:Imm, R2:R32, .Operands) => . + execinstr (sbbl Imm32:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/sbbl_r32_imm8.k b/semantics/immediateInstructions/sbbl_r32_imm8.k index b87231fa8..0dbacb0a0 100644 --- a/semantics/immediateInstructions/sbbl_r32_imm8.k +++ b/semantics/immediateInstructions/sbbl_r32_imm8.k @@ -5,26 +5,27 @@ module SBBL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (sbbl Imm8:Imm, R2:R32, .Operands) => . + execinstr (sbbl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/sbbq_r64_imm32.k b/semantics/immediateInstructions/sbbq_r64_imm32.k index 1bdf5cf0a..7ff40a0a7 100644 --- a/semantics/immediateInstructions/sbbq_r64_imm32.k +++ b/semantics/immediateInstructions/sbbq_r64_imm32.k @@ -5,26 +5,27 @@ module SBBQ-R64-IMM32 imports X86-CONFIGURATION rule - execinstr (sbbq Imm32:Imm, R2:R64, .Operands) => . + execinstr (sbbq Imm32:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) +convToRegKeys(R2) |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/sbbq_r64_imm8.k b/semantics/immediateInstructions/sbbq_r64_imm8.k index a6e618e39..4d44c0e40 100644 --- a/semantics/immediateInstructions/sbbq_r64_imm8.k +++ b/semantics/immediateInstructions/sbbq_r64_imm8.k @@ -5,26 +5,27 @@ module SBBQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (sbbq Imm8:Imm, R2:R64, .Operands) => . + execinstr (sbbq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) +convToRegKeys(R2) |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/sbbq_rax_imm32.k b/semantics/immediateInstructions/sbbq_rax_imm32.k index 5f33798ee..9568a36fb 100644 --- a/semantics/immediateInstructions/sbbq_rax_imm32.k +++ b/semantics/immediateInstructions/sbbq_rax_imm32.k @@ -5,26 +5,27 @@ module SBBQ-RAX-IMM32 imports X86-CONFIGURATION rule - execinstr (sbbq Imm32:Imm, %rax, .Operands) => . + execinstr (sbbq Imm32:MInt, %rax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65) +"RAX" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/sbbw_ax_imm16.k b/semantics/immediateInstructions/sbbw_ax_imm16.k index a8c2c5bd3..758b25a49 100644 --- a/semantics/immediateInstructions/sbbw_ax_imm16.k +++ b/semantics/immediateInstructions/sbbw_ax_imm16.k @@ -5,26 +5,27 @@ module SBBW-AX-IMM16 imports X86-CONFIGURATION rule - execinstr (sbbw Imm16:Imm, %ax, .Operands) => . + execinstr (sbbw Imm16:MInt, %ax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17)) +"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm16, 11, 12), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/sbbw_r16_imm16.k b/semantics/immediateInstructions/sbbw_r16_imm16.k index 251a054d1..6d0ae3c6d 100644 --- a/semantics/immediateInstructions/sbbw_r16_imm16.k +++ b/semantics/immediateInstructions/sbbw_r16_imm16.k @@ -5,26 +5,27 @@ module SBBW-R16-IMM16 imports X86-CONFIGURATION rule - execinstr (sbbw Imm16:Imm, R2:R16, .Operands) => . + execinstr (sbbw Imm16:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm16, 11, 12), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/sbbw_r16_imm8.k b/semantics/immediateInstructions/sbbw_r16_imm8.k index 0c9f975b2..3aeb7dd7d 100644 --- a/semantics/immediateInstructions/sbbw_r16_imm8.k +++ b/semantics/immediateInstructions/sbbw_r16_imm8.k @@ -5,26 +5,27 @@ module SBBW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (sbbw Imm8:Imm, R2:R16, .Operands) => . + execinstr (sbbw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/shlb_r8_imm8.k b/semantics/immediateInstructions/shlb_r8_imm8.k index 0174e9636..4040f4247 100644 --- a/semantics/immediateInstructions/shlb_r8_imm8.k +++ b/semantics/immediateInstructions/shlb_r8_imm8.k @@ -5,26 +5,27 @@ module SHLB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (shlb Imm8:Imm, R2:R8, .Operands) => . + execinstr (shlb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 9)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 9)) -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 9), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 9), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/shlb_rh_imm8.k b/semantics/immediateInstructions/shlb_rh_imm8.k index bfd30eb44..3e65a2faa 100644 --- a/semantics/immediateInstructions/shlb_rh_imm8.k +++ b/semantics/immediateInstructions/shlb_rh_imm8.k @@ -5,26 +5,27 @@ module SHLB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (shlb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (shlb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 9), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 9), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/shldl_r32_r32_imm8.k b/semantics/immediateInstructions/shldl_r32_r32_imm8.k index 4671643c0..9bcbd4c3d 100644 --- a/semantics/immediateInstructions/shldl_r32_r32_imm8.k +++ b/semantics/immediateInstructions/shldl_r32_r32_imm8.k @@ -5,11 +5,12 @@ module SHLDL-R32-R32 imports X86-CONFIGURATION rule - execinstr (shldl Imm8:Imm, R2:R32, R1:R32, .Operands) => + execinstr (shldl Imm8:MInt, R2:R32, R1:R32, .Operands) => execinstr (shldl R1, getRegisterValue(R1, RSMap), getRegisterValue(R2, RSMap), - shiftCountMask(handleImmediateWithSignExtend(Imm8, 8, 8), 32), .Operands) + shiftCountMask(Imm8, 32), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (shldl R, MIdest:MInt, MIsrc:MInt, MIcount:MInt, .Operands) => diff --git a/semantics/immediateInstructions/shldq_r64_r64_imm8.k b/semantics/immediateInstructions/shldq_r64_r64_imm8.k index d0ec22d65..c37d6046e 100644 --- a/semantics/immediateInstructions/shldq_r64_r64_imm8.k +++ b/semantics/immediateInstructions/shldq_r64_r64_imm8.k @@ -5,11 +5,12 @@ module SHLDQ-R64-R64 imports X86-CONFIGURATION rule - execinstr (shldq Imm8:Imm, R2:R64, R1:R64, .Operands) => + execinstr (shldq Imm8:MInt, R2:R64, R1:R64, .Operands) => execinstr (shldq R1, getRegisterValue(R1, RSMap), getRegisterValue(R2, RSMap), - shiftCountMask(handleImmediateWithSignExtend(Imm8, 8, 8), 64), .Operands) + shiftCountMask(Imm8, 64), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (shldq R, MIdest:MInt, MIsrc:MInt, MIcount:MInt, .Operands) => . diff --git a/semantics/immediateInstructions/shldw_r16_r16_imm8.k b/semantics/immediateInstructions/shldw_r16_r16_imm8.k index 184331886..a0ec3d9eb 100644 --- a/semantics/immediateInstructions/shldw_r16_r16_imm8.k +++ b/semantics/immediateInstructions/shldw_r16_r16_imm8.k @@ -5,11 +5,12 @@ module SHLDW-R16-R16 imports X86-CONFIGURATION rule - execinstr (shldw Imm8:Imm, R2:R16, R1:R16, .Operands) => + execinstr (shldw Imm8:MInt, R2:R16, R1:R16, .Operands) => execinstr (shldw R1, getRegisterValue(R1, RSMap), getRegisterValue(R2, RSMap), - shiftCountMask(handleImmediateWithSignExtend(Imm8, 8, 8), 32), .Operands) + shiftCountMask(Imm8, 32), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (shldw R, MIdest:MInt, MIsrc:MInt, MIcount:MInt, .Operands) => . diff --git a/semantics/immediateInstructions/shll_r32_imm8.k b/semantics/immediateInstructions/shll_r32_imm8.k index 4e7ca5115..96e44fdec 100644 --- a/semantics/immediateInstructions/shll_r32_imm8.k +++ b/semantics/immediateInstructions/shll_r32_imm8.k @@ -5,26 +5,27 @@ module SHLL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (shll Imm8:Imm, R2:R32, .Operands) => . + execinstr (shll Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 33)) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 33)) -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 25, 26), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 25, 26), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 33), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 33), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/shlq_r64_imm8.k b/semantics/immediateInstructions/shlq_r64_imm8.k index b48fe11d4..97e23d1e6 100644 --- a/semantics/immediateInstructions/shlq_r64_imm8.k +++ b/semantics/immediateInstructions/shlq_r64_imm8.k @@ -5,26 +5,27 @@ module SHLQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (shlq Imm8:Imm, R2:R64, .Operands) => . + execinstr (shlq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 65) +convToRegKeys(R2) |-> extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 65) -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 57, 58), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 57, 58), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 65), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 65), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), getParentValue(R2, RSMap)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/shlw_r16_imm8.k b/semantics/immediateInstructions/shlw_r16_imm8.k index 55df900af..26db433cf 100644 --- a/semantics/immediateInstructions/shlw_r16_imm8.k +++ b/semantics/immediateInstructions/shlw_r16_imm8.k @@ -5,26 +5,27 @@ module SHLW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (shlw Imm8:Imm, R2:R16, .Operands) => . + execinstr (shlw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 17)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 17)) -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 9, 10), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 9, 10), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 17), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 17), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/shrb_r8_imm8.k b/semantics/immediateInstructions/shrb_r8_imm8.k index 3b8d8c479..107f7f7fb 100644 --- a/semantics/immediateInstructions/shrb_r8_imm8.k +++ b/semantics/immediateInstructions/shrb_r8_imm8.k @@ -5,26 +5,27 @@ module SHRB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (shrb Imm8:Imm, R2:R8, .Operands) => . + execinstr (shrb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 8)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 8)) -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 7, 8), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 7, 8), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 8), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 8), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool eqMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), mi(1, 1))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool eqMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), mi(1, 1))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/shrb_rh_imm8.k b/semantics/immediateInstructions/shrb_rh_imm8.k index 2a21f3d61..b71d3a547 100644 --- a/semantics/immediateInstructions/shrb_rh_imm8.k +++ b/semantics/immediateInstructions/shrb_rh_imm8.k @@ -5,26 +5,27 @@ module SHRB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (shrb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (shrb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 8)), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 8)), extractMInt( getParentValue(R2, RSMap), 56, 64)) -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 7, 8), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 7, 8), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 8), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 8), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/shrdl_r32_r32_imm8.k b/semantics/immediateInstructions/shrdl_r32_r32_imm8.k index b005bfa99..69ffe4181 100644 --- a/semantics/immediateInstructions/shrdl_r32_r32_imm8.k +++ b/semantics/immediateInstructions/shrdl_r32_r32_imm8.k @@ -5,11 +5,12 @@ module SHRDL-R32-R32 imports X86-CONFIGURATION rule - execinstr (shrdl Imm8:Imm, R2:R32, R1:R32, .Operands) => + execinstr (shrdl Imm8:MInt, R2:R32, R1:R32, .Operands) => execinstr (shrdl R1, getRegisterValue(R1, RSMap), getRegisterValue(R2, RSMap), - shiftCountMask(handleImmediateWithSignExtend(Imm8, 8, 8), 32), .Operands) + shiftCountMask(Imm8, 32), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (shrdl R, MIdest:MInt, MIsrc:MInt, MIcount:MInt, .Operands) => diff --git a/semantics/immediateInstructions/shrdq_r64_r64_imm8.k b/semantics/immediateInstructions/shrdq_r64_r64_imm8.k index b3758651a..8186aa980 100644 --- a/semantics/immediateInstructions/shrdq_r64_r64_imm8.k +++ b/semantics/immediateInstructions/shrdq_r64_r64_imm8.k @@ -5,11 +5,12 @@ module SHLDQ-R64-R64 imports X86-CONFIGURATION rule - execinstr (shrdq Imm8:Imm, R2:R64, R1:R64, .Operands) => + execinstr (shrdq Imm8:MInt, R2:R64, R1:R64, .Operands) => execinstr (shrdq R1, getRegisterValue(R1, RSMap), getRegisterValue(R2, RSMap), - shiftCountMask(handleImmediateWithSignExtend(Imm8, 8, 8), 64), .Operands) + shiftCountMask(Imm8, 64), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (shrdq R, MIdest:MInt, MIsrc:MInt, MIcount:MInt, .Operands) => . diff --git a/semantics/immediateInstructions/shrdw_r16_r16_imm8.k b/semantics/immediateInstructions/shrdw_r16_r16_imm8.k index 85326f59b..bf4ba14cb 100644 --- a/semantics/immediateInstructions/shrdw_r16_r16_imm8.k +++ b/semantics/immediateInstructions/shrdw_r16_r16_imm8.k @@ -5,11 +5,12 @@ module SHLDW-R16-R16 imports X86-CONFIGURATION rule - execinstr (shrdw Imm8:Imm, R2:R16, R1:R16, .Operands) => + execinstr (shrdw Imm8:MInt, R2:R16, R1:R16, .Operands) => execinstr (shrdw R1, getRegisterValue(R1, RSMap), getRegisterValue(R2, RSMap), - shiftCountMask(handleImmediateWithSignExtend(Imm8, 8, 8), 32), .Operands) + shiftCountMask(Imm8, 32), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (shrdw R, MIdest:MInt, MIsrc:MInt, MIcount:MInt, .Operands) => . diff --git a/semantics/immediateInstructions/shrl_r32_imm8.k b/semantics/immediateInstructions/shrl_r32_imm8.k index 09e799d00..db234d059 100644 --- a/semantics/immediateInstructions/shrl_r32_imm8.k +++ b/semantics/immediateInstructions/shrl_r32_imm8.k @@ -5,26 +5,27 @@ module SHRL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (shrl Imm8:Imm, R2:R32, .Operands) => . + execinstr (shrl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 32)) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 32)) -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 32, 33), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 32, 33), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 31, 32), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 25, 26), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 24, 25), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 31, 32), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 25, 26), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 24, 25), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 32), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 32), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/shrq_r64_imm8.k b/semantics/immediateInstructions/shrq_r64_imm8.k index 4333f654e..b8fc04b9b 100644 --- a/semantics/immediateInstructions/shrq_r64_imm8.k +++ b/semantics/immediateInstructions/shrq_r64_imm8.k @@ -5,26 +5,27 @@ module SHRQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (shrq Imm8:Imm, R2:R64, .Operands) => . + execinstr (shrq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 64) +convToRegKeys(R2) |-> extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 64) -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 64, 65), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 64, 65), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 63, 64), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 57, 58), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 56, 57), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 63, 64), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 57, 58), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 56, 57), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 64), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 64), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( getParentValue(R2, RSMap), mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1)) andBool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1)) andBool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/shrw_r16_imm8.k b/semantics/immediateInstructions/shrw_r16_imm8.k index 6770d033b..44c8c50a9 100644 --- a/semantics/immediateInstructions/shrw_r16_imm8.k +++ b/semantics/immediateInstructions/shrw_r16_imm8.k @@ -5,26 +5,27 @@ module SHRW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (shrw Imm8:Imm, R2:R16, .Operands) => . + execinstr (shrw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 16)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 16)) -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 16, 17), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 16, 17), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 15, 16), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 9, 10), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 15, 16), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 9, 10), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 16), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 16), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/shufpd_xmm_xmm_imm8.k b/semantics/immediateInstructions/shufpd_xmm_xmm_imm8.k index c86790412..cd66af7db 100644 --- a/semantics/immediateInstructions/shufpd_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/shufpd_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module SHUFPD-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (shufpd Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (shufpd Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 192) #else extractMInt( getParentValue(R2, RSMap), 192, 256) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R3, RSMap), 192, 256) #fi))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 192) #else extractMInt( getParentValue(R2, RSMap), 192, 256) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R3, RSMap), 192, 256) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/shufps_xmm_xmm_imm8.k b/semantics/immediateInstructions/shufps_xmm_xmm_imm8.k index 5c6a1c7f4..5db83df0e 100644 --- a/semantics/immediateInstructions/shufps_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/shufps_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module SHUFPS-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (shufps Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (shufps Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/subb_al_imm8.k b/semantics/immediateInstructions/subb_al_imm8.k index 618562cae..a8b857ea8 100644 --- a/semantics/immediateInstructions/subb_al_imm8.k +++ b/semantics/immediateInstructions/subb_al_imm8.k @@ -5,26 +5,27 @@ module SUBB-AL-IMM8 imports X86-CONFIGURATION rule - execinstr (subb Imm8:Imm, %al, .Operands) => . + execinstr (subb Imm8:MInt, %al, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 56), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9)) +"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 56), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/subb_r8_imm8.k b/semantics/immediateInstructions/subb_r8_imm8.k index 387d456f2..a43a7548d 100644 --- a/semantics/immediateInstructions/subb_r8_imm8.k +++ b/semantics/immediateInstructions/subb_r8_imm8.k @@ -5,26 +5,27 @@ module SUBB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (subb Imm8:Imm, R2:R8, .Operands) => . + execinstr (subb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 56, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/subb_rh_imm8.k b/semantics/immediateInstructions/subb_rh_imm8.k index e543de998..7c245cf10 100644 --- a/semantics/immediateInstructions/subb_rh_imm8.k +++ b/semantics/immediateInstructions/subb_rh_imm8.k @@ -5,26 +5,27 @@ module SUBB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (subb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (subb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9)), extractMInt( getParentValue(R2, RSMap), 56, 64)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 51, 52)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 51, 52)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 56))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/subl_eax_imm32.k b/semantics/immediateInstructions/subl_eax_imm32.k index 29cd97b6a..c0ff3bfaf 100644 --- a/semantics/immediateInstructions/subl_eax_imm32.k +++ b/semantics/immediateInstructions/subl_eax_imm32.k @@ -5,26 +5,27 @@ module SUBL-EAX-IMM32 imports X86-CONFIGURATION rule - execinstr (subl Imm32:Imm, %eax, .Operands) => . + execinstr (subl Imm32:MInt, %eax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33)) +"RAX" |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/subl_r32_imm32.k b/semantics/immediateInstructions/subl_r32_imm32.k index 0755bbf2d..33b4699d9 100644 --- a/semantics/immediateInstructions/subl_r32_imm32.k +++ b/semantics/immediateInstructions/subl_r32_imm32.k @@ -5,26 +5,27 @@ module SUBL-R32-IMM32 imports X86-CONFIGURATION rule - execinstr (subl Imm32:Imm, R2:R32, .Operands) => . + execinstr (subl Imm32:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/subl_r32_imm8.k b/semantics/immediateInstructions/subl_r32_imm8.k index 8bc784fb6..c211b17c1 100644 --- a/semantics/immediateInstructions/subl_r32_imm8.k +++ b/semantics/immediateInstructions/subl_r32_imm8.k @@ -5,26 +5,27 @@ module SUBL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (subl Imm8:Imm, R2:R32, .Operands) => . + execinstr (subl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 32, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/subq_r64_imm32.k b/semantics/immediateInstructions/subq_r64_imm32.k index 431209925..61eab8859 100644 --- a/semantics/immediateInstructions/subq_r64_imm32.k +++ b/semantics/immediateInstructions/subq_r64_imm32.k @@ -5,26 +5,27 @@ module SUBQ-R64-IMM32 imports X86-CONFIGURATION rule - execinstr (subq Imm32:Imm, R2:R64, .Operands) => . + execinstr (subq Imm32:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) +convToRegKeys(R2) |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/subq_r64_imm8.k b/semantics/immediateInstructions/subq_r64_imm8.k index 43dc68abb..7e7143bb6 100644 --- a/semantics/immediateInstructions/subq_r64_imm8.k +++ b/semantics/immediateInstructions/subq_r64_imm8.k @@ -5,26 +5,27 @@ module SUBQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (subq Imm8:Imm, R2:R64, .Operands) => . + execinstr (subq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) +convToRegKeys(R2) |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(R2, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/subq_rax_imm32.k b/semantics/immediateInstructions/subq_rax_imm32.k index 55b2eea31..fcb689e44 100644 --- a/semantics/immediateInstructions/subq_rax_imm32.k +++ b/semantics/immediateInstructions/subq_rax_imm32.k @@ -5,26 +5,27 @@ module SUBQ-RAX-IMM32 imports X86-CONFIGURATION rule - execinstr (subq Imm32:Imm, %rax, .Operands) => . + execinstr (subq Imm32:MInt, %rax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65) +"RAX" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), getParentValue(%rax, RSMap))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/subw_ax_imm16.k b/semantics/immediateInstructions/subw_ax_imm16.k index b06af6178..30e03aec1 100644 --- a/semantics/immediateInstructions/subw_ax_imm16.k +++ b/semantics/immediateInstructions/subw_ax_imm16.k @@ -5,26 +5,27 @@ module SUBW-AX-IMM16 imports X86-CONFIGURATION rule - execinstr (subw Imm16:Imm, %ax, .Operands) => . + execinstr (subw Imm16:MInt, %ax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 48), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17)) +"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 48), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm16, 11, 12), extractMInt( getParentValue(%rax, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(%rax, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/subw_r16_imm16.k b/semantics/immediateInstructions/subw_r16_imm16.k index adf372649..c7dcc5abe 100644 --- a/semantics/immediateInstructions/subw_r16_imm16.k +++ b/semantics/immediateInstructions/subw_r16_imm16.k @@ -5,26 +5,27 @@ module SUBW-R16-IMM16 imports X86-CONFIGURATION rule - execinstr (subw Imm16:Imm, R2:R16, .Operands) => . + execinstr (subw Imm16:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm16, 11, 12), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/subw_r16_imm8.k b/semantics/immediateInstructions/subw_r16_imm8.k index bcb7196b4..db1f91929 100644 --- a/semantics/immediateInstructions/subw_r16_imm8.k +++ b/semantics/immediateInstructions/subw_r16_imm8.k @@ -5,26 +5,27 @@ module SUBW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (subw Imm8:Imm, R2:R16, .Operands) => . + execinstr (subw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17)) -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( getParentValue(R2, RSMap), 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), extractMInt( getParentValue(R2, RSMap), 48, 64))), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/testb_al_imm8.k b/semantics/immediateInstructions/testb_al_imm8.k index 00b0709b1..99ddee5e5 100644 --- a/semantics/immediateInstructions/testb_al_imm8.k +++ b/semantics/immediateInstructions/testb_al_imm8.k @@ -5,24 +5,25 @@ module TESTB-AL-IMM8 imports X86-CONFIGURATION rule - execinstr (testb Imm8:Imm, %al, .Operands) => . + execinstr (testb Imm8:MInt, %al, .Operands) => . ... RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 64), Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/testb_r8_imm8.k b/semantics/immediateInstructions/testb_r8_imm8.k index 2917ddb10..46ea4daed 100644 --- a/semantics/immediateInstructions/testb_r8_imm8.k +++ b/semantics/immediateInstructions/testb_r8_imm8.k @@ -5,24 +5,25 @@ module TESTB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (testb Imm8:Imm, R2:R8, .Operands) => . + execinstr (testb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/testb_rh_imm8.k b/semantics/immediateInstructions/testb_rh_imm8.k index d2535cf3d..fe652acf1 100644 --- a/semantics/immediateInstructions/testb_rh_imm8.k +++ b/semantics/immediateInstructions/testb_rh_imm8.k @@ -5,24 +5,25 @@ module TESTB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (testb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (testb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 55, 56), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 54, 55), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 53, 54), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 52, 53), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 51, 52), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 50, 51), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 49, 50), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 55, 56), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 54, 55), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 53, 54), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 52, 53), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 51, 52), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 50, 51), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 49, 50), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/testl_eax_imm32.k b/semantics/immediateInstructions/testl_eax_imm32.k index c74ce0f0b..ab7b1c10b 100644 --- a/semantics/immediateInstructions/testl_eax_imm32.k +++ b/semantics/immediateInstructions/testl_eax_imm32.k @@ -5,24 +5,25 @@ module TESTL-EAX-IMM32 imports X86-CONFIGURATION rule - execinstr (testl Imm32:Imm, %eax, .Operands) => . + execinstr (testl Imm32:MInt, %eax, .Operands) => . ... RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 32, 64), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 32, 64), Imm32), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), extractMInt( Imm32, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/testl_r32_imm32.k b/semantics/immediateInstructions/testl_r32_imm32.k index af624c5f6..4f2510169 100644 --- a/semantics/immediateInstructions/testl_r32_imm32.k +++ b/semantics/immediateInstructions/testl_r32_imm32.k @@ -5,24 +5,25 @@ module TESTL-R32-IMM32 imports X86-CONFIGURATION rule - execinstr (testl Imm32:Imm, R2:R32, .Operands) => . + execinstr (testl Imm32:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), Imm32), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), extractMInt( Imm32, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/testq_r64_imm32.k b/semantics/immediateInstructions/testq_r64_imm32.k index 0bae894e7..63c1b68be 100644 --- a/semantics/immediateInstructions/testq_r64_imm32.k +++ b/semantics/immediateInstructions/testq_r64_imm32.k @@ -5,24 +5,25 @@ module TESTQ-R64-IMM32 imports X86-CONFIGURATION rule - execinstr (testq Imm32:Imm, R2:R64, .Operands) => . + execinstr (testq Imm32:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(Imm32))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/testq_rax_imm32.k b/semantics/immediateInstructions/testq_rax_imm32.k index f470eeba8..bd2c6c983 100644 --- a/semantics/immediateInstructions/testq_rax_imm32.k +++ b/semantics/immediateInstructions/testq_rax_imm32.k @@ -5,24 +5,25 @@ module TESTQ-RAX-IMM32 imports X86-CONFIGURATION rule - execinstr (testq Imm32:Imm, %rax, .Operands) => . + execinstr (testq Imm32:MInt, %rax, .Operands) => . ... RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( getParentValue(%rax, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( getParentValue(%rax, RSMap), mi(64, svalueMInt(Imm32))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/testw_ax_imm16.k b/semantics/immediateInstructions/testw_ax_imm16.k index b1976b2ce..18d1030ff 100644 --- a/semantics/immediateInstructions/testw_ax_imm16.k +++ b/semantics/immediateInstructions/testw_ax_imm16.k @@ -5,24 +5,25 @@ module TESTW-AX-IMM16 imports X86-CONFIGURATION rule - execinstr (testw Imm16:Imm, %ax, .Operands) => . + execinstr (testw Imm16:MInt, %ax, .Operands) => . ... RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 15, 16)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 14, 15)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 13, 14)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 12, 13)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 10, 11)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 9, 10)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm16, 15, 16)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm16, 14, 15)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm16, 13, 14)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm16, 12, 13)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm16, 11, 12)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm16, 10, 11)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm16, 9, 10)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm16, 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 48, 64), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(%rax, RSMap), 48, 64), Imm16), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), extractMInt( Imm16, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/testw_r16_imm16.k b/semantics/immediateInstructions/testw_r16_imm16.k index b7ced050b..f1c729743 100644 --- a/semantics/immediateInstructions/testw_r16_imm16.k +++ b/semantics/immediateInstructions/testw_r16_imm16.k @@ -5,24 +5,25 @@ module TESTW-R16-IMM16 imports X86-CONFIGURATION rule - execinstr (testw Imm16:Imm, R2:R16, .Operands) => . + execinstr (testw Imm16:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 15, 16)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 14, 15)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 13, 14)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 12, 13)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 10, 11)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 9, 10)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm16, 15, 16)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm16, 14, 15)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm16, 13, 14)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm16, 12, 13)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm16, 11, 12)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm16, 10, 11)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm16, 9, 10)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm16, 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), Imm16), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)) +"SF" |-> andMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( Imm16, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/vblendpd_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vblendpd_xmm_xmm_xmm_imm8.k index 3ee018fd2..6fedd58aa 100644 --- a/semantics/immediateInstructions/vblendpd_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vblendpd_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VBLENDPD-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vblendpd Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vblendpd Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 192) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 256) #else extractMInt( getParentValue(R2, RSMap), 192, 256) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 192) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 256) #else extractMInt( getParentValue(R2, RSMap), 192, 256) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vblendpd_ymm_ymm_ymm_imm8.k b/semantics/immediateInstructions/vblendpd_ymm_ymm_ymm_imm8.k index 2b4f0530f..41d9e07f4 100644 --- a/semantics/immediateInstructions/vblendpd_ymm_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vblendpd_ymm_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VBLENDPD-YMM-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vblendpd Imm8:Imm, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . + execinstr (vblendpd Imm8:MInt, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 64) #else extractMInt( getParentValue(R2, RSMap), 0, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 128) #else extractMInt( getParentValue(R2, RSMap), 64, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 192) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 256) #else extractMInt( getParentValue(R2, RSMap), 192, 256) #fi)))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 64) #else extractMInt( getParentValue(R2, RSMap), 0, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 128) #else extractMInt( getParentValue(R2, RSMap), 64, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 192) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 256) #else extractMInt( getParentValue(R2, RSMap), 192, 256) #fi)))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vblendps_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vblendps_xmm_xmm_xmm_imm8.k index f8ca5b094..efd6ef5d6 100644 --- a/semantics/immediateInstructions/vblendps_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vblendps_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VBLENDPS-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vblendps Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vblendps Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 160, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 160, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vblendps_ymm_ymm_ymm_imm8.k b/semantics/immediateInstructions/vblendps_ymm_ymm_ymm_imm8.k index b1879648f..800b2246c 100644 --- a/semantics/immediateInstructions/vblendps_ymm_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vblendps_ymm_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VBLENDPS-YMM-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vblendps Imm8:Imm, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . + execinstr (vblendps Imm8:MInt, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( getParentValue(R2, RSMap), 0, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 32, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 96) #else extractMInt( getParentValue(R2, RSMap), 64, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 96, 128) #else extractMInt( getParentValue(R2, RSMap), 96, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 160, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi)))))))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( getParentValue(R2, RSMap), 0, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 32, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 96) #else extractMInt( getParentValue(R2, RSMap), 64, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 96, 128) #else extractMInt( getParentValue(R2, RSMap), 96, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 160, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vcmppd_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vcmppd_xmm_xmm_xmm_imm8.k index 96ee895b5..a5fa7aef6 100644 --- a/semantics/immediateInstructions/vcmppd_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vcmppd_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VCMPPD-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vcmppd Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vcmppd Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( getParentValue(R2, RSMap), 128, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( getParentValue(R2, RSMap), 128, 192), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vcmppd_ymm_ymm_ymm_imm8.k b/semantics/immediateInstructions/vcmppd_ymm_ymm_ymm_imm8.k index cad4e5ef0..fe4085da0 100644 --- a/semantics/immediateInstructions/vcmppd_ymm_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vcmppd_ymm_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VCMPPD-YMM-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vcmppd Imm8:Imm, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . + execinstr (vcmppd Imm8:MInt, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 0, 64), extractMInt( getParentValue(R2, RSMap), 0, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 64, 128), extractMInt( getParentValue(R2, RSMap), 64, 128), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( getParentValue(R2, RSMap), 128, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi)))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 0, 64), extractMInt( getParentValue(R2, RSMap), 0, 64), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 64, 128), extractMInt( getParentValue(R2, RSMap), 64, 128), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( getParentValue(R2, RSMap), 128, 192), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi)))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vcmpps_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vcmpps_xmm_xmm_xmm_imm8.k index fa90167e3..c91209c6d 100644 --- a/semantics/immediateInstructions/vcmpps_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vcmpps_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VCMPPS-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vcmpps Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vcmpps Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vcmpps_ymm_ymm_ymm_imm8.k b/semantics/immediateInstructions/vcmpps_ymm_ymm_ymm_imm8.k index e08fe406c..0e602f16e 100644 --- a/semantics/immediateInstructions/vcmpps_ymm_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vcmpps_ymm_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VCMPPS-YMM-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vcmpps Imm8:Imm, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . + execinstr (vcmpps Imm8:MInt, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( getParentValue(R2, RSMap), 0, 32), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( getParentValue(R2, RSMap), 32, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( getParentValue(R2, RSMap), 64, 96), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( getParentValue(R2, RSMap), 96, 128), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi)))))))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( getParentValue(R2, RSMap), 0, 32), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( getParentValue(R2, RSMap), 32, 64), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( getParentValue(R2, RSMap), 64, 96), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( getParentValue(R2, RSMap), 96, 128), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vcmpsd_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vcmpsd_xmm_xmm_xmm_imm8.k index 49e9c555f..e0d0e21c1 100644 --- a/semantics/immediateInstructions/vcmpsd_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vcmpsd_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VCMPSD-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vcmpsd Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vcmpsd Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 192), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 192), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vcmpss_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vcmpss_xmm_xmm_xmm_imm8.k index 687eb73a4..a5980ae2c 100644 --- a/semantics/immediateInstructions/vcmpss_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vcmpss_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VCMPSS-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vcmpss Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vcmpss Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 224), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 224), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vcvtps2ph_xmm_xmm_imm8.k b/semantics/immediateInstructions/vcvtps2ph_xmm_xmm_imm8.k index 4fea4a289..d67bd86eb 100644 --- a/semantics/immediateInstructions/vcvtps2ph_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vcvtps2ph_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VCVTPS2PH-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vcvtps2ph Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vcvtps2ph Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(192, 0), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 128, 160), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 160, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 192, 224), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8)))))) +convToRegKeys(R3) |-> concatenateMInt( mi(192, 0), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 128, 160), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 160, 192), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 192, 224), Imm8), cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), Imm8))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vcvtps2ph_xmm_ymm_imm8.k b/semantics/immediateInstructions/vcvtps2ph_xmm_ymm_imm8.k index 8634980c7..1260fd796 100644 --- a/semantics/immediateInstructions/vcvtps2ph_xmm_ymm_imm8.k +++ b/semantics/immediateInstructions/vcvtps2ph_xmm_ymm_imm8.k @@ -5,14 +5,15 @@ module VCVTPS2PH-XMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vcvtps2ph Imm8:Imm, R2:Ymm, R3:Xmm, .Operands) => . + execinstr (vcvtps2ph Imm8:MInt, R2:Ymm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 0, 32), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 32, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 64, 96), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 96, 128), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 128, 160), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 160, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 192, 224), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8)))))))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 0, 32), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 32, 64), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 64, 96), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 96, 128), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 128, 160), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 160, 192), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 192, 224), Imm8), cvt_single_to_fp16_rm(extractMInt( getParentValue(R3, RSMap), 224, 256), Imm8))))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vdppd_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vdppd_xmm_xmm_xmm_imm8.k index 7643dd596..2bdf3f065 100644 --- a/semantics/immediateInstructions/vdppd_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vdppd_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VDPPD-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vdppd Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vdppd Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( getParentValue(R2, RSMap), 128, 192)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( getParentValue(R2, RSMap), 128, 192)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( getParentValue(R2, RSMap), 128, 192)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( getParentValue(R2, RSMap), 192, 256)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( getParentValue(R2, RSMap), 128, 192)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vdpps_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vdpps_xmm_xmm_xmm_imm8.k index 84d86ff46..eae75de42 100644 --- a/semantics/immediateInstructions/vdpps_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vdpps_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VDPPS-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vdpps Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vdpps Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vdpps_ymm_ymm_ymm_imm8.k b/semantics/immediateInstructions/vdpps_ymm_ymm_ymm_imm8.k index cf31908f8..c75495cc8 100644 --- a/semantics/immediateInstructions/vdpps_ymm_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vdpps_ymm_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VDPPS-YMM-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vdpps Imm8:Imm, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . + execinstr (vdpps Imm8:MInt, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( getParentValue(R2, RSMap), 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( getParentValue(R2, RSMap), 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( getParentValue(R2, RSMap), 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( getParentValue(R2, RSMap), 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( getParentValue(R2, RSMap), 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( getParentValue(R2, RSMap), 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( getParentValue(R2, RSMap), 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( getParentValue(R2, RSMap), 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( getParentValue(R2, RSMap), 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( getParentValue(R2, RSMap), 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( getParentValue(R2, RSMap), 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( getParentValue(R2, RSMap), 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( getParentValue(R2, RSMap), 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( getParentValue(R2, RSMap), 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( getParentValue(R2, RSMap), 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( getParentValue(R2, RSMap), 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi))) +convToRegKeys(R4) |-> concatenateMInt( concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( getParentValue(R2, RSMap), 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( getParentValue(R2, RSMap), 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( getParentValue(R2, RSMap), 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( getParentValue(R2, RSMap), 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( getParentValue(R2, RSMap), 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( getParentValue(R2, RSMap), 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( getParentValue(R2, RSMap), 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( getParentValue(R2, RSMap), 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( getParentValue(R2, RSMap), 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( getParentValue(R2, RSMap), 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( getParentValue(R2, RSMap), 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( getParentValue(R2, RSMap), 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( getParentValue(R2, RSMap), 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( getParentValue(R2, RSMap), 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( getParentValue(R2, RSMap), 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( getParentValue(R2, RSMap), 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( getParentValue(R2, RSMap), 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( getParentValue(R2, RSMap), 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( getParentValue(R2, RSMap), 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( getParentValue(R2, RSMap), 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vextractf128_xmm_ymm_imm8.k b/semantics/immediateInstructions/vextractf128_xmm_ymm_imm8.k index ee009d9cc..ca0a85a25 100644 --- a/semantics/immediateInstructions/vextractf128_xmm_ymm_imm8.k +++ b/semantics/immediateInstructions/vextractf128_xmm_ymm_imm8.k @@ -5,14 +5,15 @@ module VEXTRACTF128-XMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vextractf128 Imm8:Imm, R2:Ymm, R3:Xmm, .Operands) => . + execinstr (vextractf128 Imm8:MInt, R2:Ymm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else extractMInt( getParentValue(R3, RSMap), 0, 128) #fi)) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else extractMInt( getParentValue(R3, RSMap), 0, 128) #fi)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vextracti128_xmm_ymm_imm8.k b/semantics/immediateInstructions/vextracti128_xmm_ymm_imm8.k index e2413f804..423412316 100644 --- a/semantics/immediateInstructions/vextracti128_xmm_ymm_imm8.k +++ b/semantics/immediateInstructions/vextracti128_xmm_ymm_imm8.k @@ -5,14 +5,15 @@ module VEXTRACTI128-XMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vextracti128 Imm8:Imm, R2:Ymm, R3:Xmm, .Operands) => . + execinstr (vextracti128 Imm8:MInt, R2:Ymm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else extractMInt( getParentValue(R3, RSMap), 0, 128) #fi)) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else extractMInt( getParentValue(R3, RSMap), 0, 128) #fi)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vextractps_r32_xmm_imm8.k b/semantics/immediateInstructions/vextractps_r32_xmm_imm8.k index 33b73fa68..c2449f05c 100644 --- a/semantics/immediateInstructions/vextractps_r32_xmm_imm8.k +++ b/semantics/immediateInstructions/vextractps_r32_xmm_imm8.k @@ -5,14 +5,15 @@ module VEXTRACTPS-R32-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vextractps Imm8:Imm, R2:Xmm, R3:R32, .Operands) => . + execinstr (vextractps Imm8:MInt, R2:Xmm, R3:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128)) +convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vinsertf128_ymm_ymm_xmm_imm8.k b/semantics/immediateInstructions/vinsertf128_ymm_ymm_xmm_imm8.k index f5b7f8f85..9974c3c3d 100644 --- a/semantics/immediateInstructions/vinsertf128_ymm_ymm_xmm_imm8.k +++ b/semantics/immediateInstructions/vinsertf128_ymm_ymm_xmm_imm8.k @@ -5,14 +5,15 @@ module VINSERTF128-YMM-YMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vinsertf128 Imm8:Imm, R2:Xmm, R3:Ymm, R4:Ymm, .Operands) => . + execinstr (vinsertf128 Imm8:MInt, R2:Xmm, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), extractMInt( getParentValue(R2, RSMap), 128, 256)) #else concatenateMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), extractMInt( getParentValue(R3, RSMap), 128, 256)) #fi) +convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), extractMInt( getParentValue(R2, RSMap), 128, 256)) #else concatenateMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), extractMInt( getParentValue(R3, RSMap), 128, 256)) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vinserti128_ymm_ymm_xmm_imm8.k b/semantics/immediateInstructions/vinserti128_ymm_ymm_xmm_imm8.k index f036b5da0..5164dbda5 100644 --- a/semantics/immediateInstructions/vinserti128_ymm_ymm_xmm_imm8.k +++ b/semantics/immediateInstructions/vinserti128_ymm_ymm_xmm_imm8.k @@ -5,14 +5,15 @@ module VINSERTI128-YMM-YMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vinserti128 Imm8:Imm, R2:Xmm, R3:Ymm, R4:Ymm, .Operands) => . + execinstr (vinserti128 Imm8:MInt, R2:Xmm, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), extractMInt( getParentValue(R2, RSMap), 128, 256)) #else concatenateMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), extractMInt( getParentValue(R3, RSMap), 128, 256)) #fi) +convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), extractMInt( getParentValue(R2, RSMap), 128, 256)) #else concatenateMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), extractMInt( getParentValue(R3, RSMap), 128, 256)) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vinsertps_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vinsertps_xmm_xmm_xmm_imm8.k index c21683704..59d10863a 100644 --- a/semantics/immediateInstructions/vinsertps_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vinsertps_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VINSERTPS-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vinsertps Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vinsertps Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #fi) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #else extractMInt( getParentValue(R3, RSMap), 160, 192) #fi) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #fi) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #else extractMInt( getParentValue(R3, RSMap), 160, 192) #fi) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vmpsadbw_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vmpsadbw_xmm_xmm_xmm_imm8.k index 46056ab72..23adeda1e 100644 --- a/semantics/immediateInstructions/vmpsadbw_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vmpsadbw_xmm_xmm_xmm_imm8.k @@ -4,43 +4,44 @@ module VMPSADBW-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vmpsadbw Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vmpsadbw Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => execinstr (vmpsadbw selectSliceMPSAD(getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 7 , 0 ), + extractMInt(Imm8, 6, 8), 7 , 0 ), selectSliceMPSAD(getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 15, 8 ), + extractMInt(Imm8, 6, 8), 15, 8 ), selectSliceMPSAD(getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 23, 16), + extractMInt(Imm8, 6, 8), 23, 16), selectSliceMPSAD(getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 31, 24), + extractMInt(Imm8, 6, 8), 31, 24), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 7 , 0), + extractMInt(Imm8, 5, 6), 7 , 0), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 15, 8), + extractMInt(Imm8, 5, 6), 15, 8), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 23, 16), + extractMInt(Imm8, 5, 6), 23, 16), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 31, 24), + extractMInt(Imm8, 5, 6), 31, 24), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 39, 32), + extractMInt(Imm8, 5, 6), 39, 32), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 47, 40), + extractMInt(Imm8, 5, 6), 47, 40), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 55, 48), + extractMInt(Imm8, 5, 6), 55, 48), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 63, 56), + extractMInt(Imm8, 5, 6), 63, 56), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 71, 64), + extractMInt(Imm8, 5, 6), 71, 64), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 79, 72), + extractMInt(Imm8, 5, 6), 79, 72), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 87, 80), + extractMInt(Imm8, 5, 6), 87, 80), R4:Xmm, .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (vmpsadbw diff --git a/semantics/immediateInstructions/vmpsadbw_ymm_ymm_ymm_imm8.k b/semantics/immediateInstructions/vmpsadbw_ymm_ymm_ymm_imm8.k index 18783c715..4939338ef 100644 --- a/semantics/immediateInstructions/vmpsadbw_ymm_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vmpsadbw_ymm_ymm_ymm_imm8.k @@ -5,93 +5,94 @@ module VMPSADBW-YMM-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vmpsadbw Imm8:Imm, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vmpsadbw Imm8:MInt, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => execinstr (vmpsadbw //Low slices selectSliceMPSAD(getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 7 , 0 ), + extractMInt(Imm8, 6, 8), 7 , 0 ), selectSliceMPSAD(getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 15, 8 ), + extractMInt(Imm8, 6, 8), 15, 8 ), selectSliceMPSAD(getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 23, 16), + extractMInt(Imm8, 6, 8), 23, 16), selectSliceMPSAD(getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 31, 24), + extractMInt(Imm8, 6, 8), 31, 24), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 7 , 0), + extractMInt(Imm8, 5, 6), 7 , 0), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 15, 8), + extractMInt(Imm8, 5, 6), 15, 8), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 23, 16), + extractMInt(Imm8, 5, 6), 23, 16), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 31, 24), + extractMInt(Imm8, 5, 6), 31, 24), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 39, 32), + extractMInt(Imm8, 5, 6), 39, 32), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 47, 40), + extractMInt(Imm8, 5, 6), 47, 40), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 55, 48), + extractMInt(Imm8, 5, 6), 55, 48), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 63, 56), + extractMInt(Imm8, 5, 6), 63, 56), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 71, 64), + extractMInt(Imm8, 5, 6), 71, 64), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 79, 72), + extractMInt(Imm8, 5, 6), 79, 72), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 87, 80), + extractMInt(Imm8, 5, 6), 87, 80), //High slices selectSliceMPSAD( getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 3, 5), 7 +Int + extractMInt(Imm8, 3, 5), 7 +Int 128, 0 +Int 128), selectSliceMPSAD( getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 3, 5), 15+Int + extractMInt(Imm8, 3, 5), 15+Int 128, 8 +Int 128), selectSliceMPSAD( getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 3, 5), 23+Int + extractMInt(Imm8, 3, 5), 23+Int 128, 16+Int 128), selectSliceMPSAD( getRegisterValue(R2, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 3, 5), 31+Int + extractMInt(Imm8, 3, 5), 31+Int 128, 24+Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 7 + extractMInt(Imm8, 2, 3), 7 +Int 128, 0 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 15 + extractMInt(Imm8, 2, 3), 15 +Int 128, 8 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 23 + extractMInt(Imm8, 2, 3), 23 +Int 128, 16 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 31 + extractMInt(Imm8, 2, 3), 31 +Int 128, 24 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 39 + extractMInt(Imm8, 2, 3), 39 +Int 128, 32 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 47 + extractMInt(Imm8, 2, 3), 47 +Int 128, 40 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 55 + extractMInt(Imm8, 2, 3), 55 +Int 128, 48 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 63 + extractMInt(Imm8, 2, 3), 63 +Int 128, 56 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 71 + extractMInt(Imm8, 2, 3), 71 +Int 128, 64 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 79 + extractMInt(Imm8, 2, 3), 79 +Int 128, 72 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 87 + extractMInt(Imm8, 2, 3), 87 +Int 128, 80 +Int 128), R4:Ymm, .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule diff --git a/semantics/immediateInstructions/vpalignr_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpalignr_xmm_xmm_xmm_imm8.k index f11895469..9e104f62b 100644 --- a/semantics/immediateInstructions/vpalignr_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpalignr_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPALIGNR-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpalignr Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vpalignr Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), extractMInt( getParentValue(R2, RSMap), 128, 256)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), uvalueMInt(mi(256, 3))))), 128, 256)) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), extractMInt( getParentValue(R2, RSMap), 128, 256)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), Imm8), uvalueMInt(mi(256, 3))))), 128, 256)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpalignr_ymm_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpalignr_ymm_ymm_ymm_imm8.k index f07e6a747..5bbc52a69 100644 --- a/semantics/immediateInstructions/vpalignr_ymm_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpalignr_ymm_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPALIGNR-YMM-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpalignr Imm8:Imm, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . + execinstr (vpalignr Imm8:MInt, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), extractMInt( getParentValue(R2, RSMap), 0, 128)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), uvalueMInt(mi(256, 3))))), 128, 256), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), extractMInt( getParentValue(R2, RSMap), 128, 256)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), uvalueMInt(mi(256, 3))))), 128, 256)) +convToRegKeys(R4) |-> concatenateMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), extractMInt( getParentValue(R2, RSMap), 0, 128)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), Imm8), uvalueMInt(mi(256, 3))))), 128, 256), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), extractMInt( getParentValue(R2, RSMap), 128, 256)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), Imm8), uvalueMInt(mi(256, 3))))), 128, 256)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpblendd_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpblendd_xmm_xmm_xmm_imm8.k index 43916d914..0a41f0c2b 100644 --- a/semantics/immediateInstructions/vpblendd_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpblendd_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPBLENDD-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpblendd Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vpblendd Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 160, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 160, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpblendd_ymm_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpblendd_ymm_ymm_ymm_imm8.k index 1d2114725..a126c731d 100644 --- a/semantics/immediateInstructions/vpblendd_ymm_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpblendd_ymm_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPBLENDD-YMM-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpblendd Imm8:Imm, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . + execinstr (vpblendd Imm8:MInt, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( getParentValue(R2, RSMap), 0, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 32, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 96) #else extractMInt( getParentValue(R2, RSMap), 64, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 96, 128) #else extractMInt( getParentValue(R2, RSMap), 96, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 160, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi)))))))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( getParentValue(R2, RSMap), 0, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 32, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 96) #else extractMInt( getParentValue(R2, RSMap), 64, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 96, 128) #else extractMInt( getParentValue(R2, RSMap), 96, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 160, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpblendw_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpblendw_xmm_xmm_xmm_imm8.k index b57e01ea0..5f7d8143f 100644 --- a/semantics/immediateInstructions/vpblendw_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpblendw_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPBLENDW-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpblendw Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vpblendw Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 144) #else extractMInt( getParentValue(R2, RSMap), 128, 144) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 144, 160) #else extractMInt( getParentValue(R2, RSMap), 144, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 176) #else extractMInt( getParentValue(R2, RSMap), 160, 176) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 176, 192) #else extractMInt( getParentValue(R2, RSMap), 176, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 208) #else extractMInt( getParentValue(R2, RSMap), 192, 208) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 208, 224) #else extractMInt( getParentValue(R2, RSMap), 208, 224) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 240) #else extractMInt( getParentValue(R2, RSMap), 224, 240) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 240, 256) #else extractMInt( getParentValue(R2, RSMap), 240, 256) #fi))))))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 144) #else extractMInt( getParentValue(R2, RSMap), 128, 144) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 144, 160) #else extractMInt( getParentValue(R2, RSMap), 144, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 176) #else extractMInt( getParentValue(R2, RSMap), 160, 176) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 176, 192) #else extractMInt( getParentValue(R2, RSMap), 176, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 208) #else extractMInt( getParentValue(R2, RSMap), 192, 208) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 208, 224) #else extractMInt( getParentValue(R2, RSMap), 208, 224) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 240) #else extractMInt( getParentValue(R2, RSMap), 224, 240) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 240, 256) #else extractMInt( getParentValue(R2, RSMap), 240, 256) #fi))))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpblendw_ymm_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpblendw_ymm_ymm_ymm_imm8.k index f92d32b14..e706ad81c 100644 --- a/semantics/immediateInstructions/vpblendw_ymm_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpblendw_ymm_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPBLENDW-YMM-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpblendw Imm8:Imm, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . + execinstr (vpblendw Imm8:MInt, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 16) #else extractMInt( getParentValue(R2, RSMap), 0, 16) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 16, 32) #else extractMInt( getParentValue(R2, RSMap), 16, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 32, 48) #else extractMInt( getParentValue(R2, RSMap), 32, 48) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 48, 64) #else extractMInt( getParentValue(R2, RSMap), 48, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 80) #else extractMInt( getParentValue(R2, RSMap), 64, 80) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 80, 96) #else extractMInt( getParentValue(R2, RSMap), 80, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 96, 112) #else extractMInt( getParentValue(R2, RSMap), 96, 112) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 112, 128) #else extractMInt( getParentValue(R2, RSMap), 112, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 144) #else extractMInt( getParentValue(R2, RSMap), 128, 144) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 144, 160) #else extractMInt( getParentValue(R2, RSMap), 144, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 176) #else extractMInt( getParentValue(R2, RSMap), 160, 176) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 176, 192) #else extractMInt( getParentValue(R2, RSMap), 176, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 208) #else extractMInt( getParentValue(R2, RSMap), 192, 208) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 208, 224) #else extractMInt( getParentValue(R2, RSMap), 208, 224) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 240) #else extractMInt( getParentValue(R2, RSMap), 224, 240) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 240, 256) #else extractMInt( getParentValue(R2, RSMap), 240, 256) #fi)))))))))))))))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 16) #else extractMInt( getParentValue(R2, RSMap), 0, 16) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 16, 32) #else extractMInt( getParentValue(R2, RSMap), 16, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 32, 48) #else extractMInt( getParentValue(R2, RSMap), 32, 48) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 48, 64) #else extractMInt( getParentValue(R2, RSMap), 48, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 80) #else extractMInt( getParentValue(R2, RSMap), 64, 80) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 80, 96) #else extractMInt( getParentValue(R2, RSMap), 80, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 96, 112) #else extractMInt( getParentValue(R2, RSMap), 96, 112) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 112, 128) #else extractMInt( getParentValue(R2, RSMap), 112, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 144) #else extractMInt( getParentValue(R2, RSMap), 128, 144) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 144, 160) #else extractMInt( getParentValue(R2, RSMap), 144, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 176) #else extractMInt( getParentValue(R2, RSMap), 160, 176) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 176, 192) #else extractMInt( getParentValue(R2, RSMap), 176, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 208) #else extractMInt( getParentValue(R2, RSMap), 192, 208) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 208, 224) #else extractMInt( getParentValue(R2, RSMap), 208, 224) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 240) #else extractMInt( getParentValue(R2, RSMap), 224, 240) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 240, 256) #else extractMInt( getParentValue(R2, RSMap), 240, 256) #fi)))))))))))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpclmulqdq_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpclmulqdq_xmm_xmm_xmm_imm8.k index 87678aeda..5f21aeeea 100644 --- a/semantics/immediateInstructions/vpclmulqdq_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpclmulqdq_xmm_xmm_xmm_imm8.k @@ -18,15 +18,14 @@ module VPCLMULQDQ-XMM-XMM-XMM-IMM8 TEMP2←SRC2 [127:64]; */ rule - execinstr (vpclmulqdq Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vpclmulqdq Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => execinstr(vpclmulqdq - selectSlice(getRegisterValue(R3, RSMap), handleImmediateWithSignExtend(Imm8, - 8, 8), 7, 64, 0), - selectSlice(getRegisterValue(R2, RSMap), handleImmediateWithSignExtend(Imm8, - 8, 8), 3, 64, 0), R4 + selectSlice(getRegisterValue(R3, RSMap), Imm8, 7, 64, 0), + selectSlice(getRegisterValue(R2, RSMap), Imm8, 3, 64, 0), R4 , .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (vpclmulqdq TEMP1:MInt, TEMP2:MInt, R4:Xmm, .Operands) => diff --git a/semantics/immediateInstructions/vpcmpestri_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpcmpestri_xmm_xmm_imm8.k index ecd631f0b..4efbc5984 100644 --- a/semantics/immediateInstructions/vpcmpestri_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpcmpestri_xmm_xmm_imm8.k @@ -6,16 +6,17 @@ module VPCMPESTRI-XMM-XMM-IMM8 // Find Limit Index rule - execinstr (vpcmpestri Imm8:Imm, Xmm2:Xmm, Xmm1:Xmm, .Operands) => + execinstr (vpcmpestri Imm8:MInt, Xmm2:Xmm, Xmm1:Xmm, .Operands) => execinstr (vpcmpestri - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, getRegisterValue(Xmm2, RSMap), getRegisterValue(Xmm1, RSMap), - findLimitIndexE(getRegisterValue(Xmm2, RSMap), getRegisterValue(%rdx, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexE(getRegisterValue(Xmm2, RSMap), getRegisterValue(%rdx, RSMap), Imm8), + findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // Find data size and interpretation rule diff --git a/semantics/immediateInstructions/vpcmpestrm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpcmpestrm_xmm_xmm_imm8.k index 49ea51ba3..dbc5620db 100644 --- a/semantics/immediateInstructions/vpcmpestrm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpcmpestrm_xmm_xmm_imm8.k @@ -6,16 +6,17 @@ module VPCMPESTRM-XMM-XMM-IMM8 // Find Limit Index rule - execinstr (vpcmpestrm Imm8:Imm, Xmm2:Xmm, Xmm1:Xmm, .Operands) => + execinstr (vpcmpestrm Imm8:MInt, Xmm2:Xmm, Xmm1:Xmm, .Operands) => execinstr (vpcmpestrm - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, getRegisterValue(Xmm2, RSMap), getRegisterValue(Xmm1, RSMap), - findLimitIndexE(getRegisterValue(Xmm2, RSMap), getRegisterValue(%rdx, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexE(getRegisterValue(Xmm2, RSMap), getRegisterValue(%rdx, RSMap), Imm8), + findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // Find data size and interpretation rule diff --git a/semantics/immediateInstructions/vpcmpistri_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpcmpistri_xmm_xmm_imm8.k index 01874f9fc..9adee87ad 100644 --- a/semantics/immediateInstructions/vpcmpistri_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpcmpistri_xmm_xmm_imm8.k @@ -6,16 +6,17 @@ module VPCMPISTRI-XMM-XMM-IMM8 // Find Limit Index rule - execinstr (vpcmpistri Imm8:Imm, Xmm2:Xmm, Xmm1:Xmm, .Operands) => + execinstr (vpcmpistri Imm8:MInt, Xmm2:Xmm, Xmm1:Xmm, .Operands) => execinstr (vpcmpistri - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, getRegisterValue(Xmm2, RSMap), getRegisterValue(Xmm1, RSMap), - findLimitIndexI(getRegisterValue(Xmm2, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexI(getRegisterValue(Xmm1, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexI(getRegisterValue(Xmm2, RSMap), Imm8), + findLimitIndexI(getRegisterValue(Xmm1, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // Find data size and interpretation rule diff --git a/semantics/immediateInstructions/vpcmpistrm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpcmpistrm_xmm_xmm_imm8.k index bb05a5a7d..fcfb65b8e 100644 --- a/semantics/immediateInstructions/vpcmpistrm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpcmpistrm_xmm_xmm_imm8.k @@ -6,16 +6,17 @@ module VPCMPISTRM-XMM-XMM-IMM8 // Find Limit Index rule - execinstr (vpcmpistrm Imm8:Imm, Xmm2:Xmm, Xmm1:Xmm, .Operands) => + execinstr (vpcmpistrm Imm8:MInt, Xmm2:Xmm, Xmm1:Xmm, .Operands) => execinstr (vpcmpistrm - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, getRegisterValue(Xmm2, RSMap), getRegisterValue(Xmm1, RSMap), - findLimitIndexI(getRegisterValue(Xmm2, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexI(getRegisterValue(Xmm1, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexI(getRegisterValue(Xmm2, RSMap), Imm8), + findLimitIndexI(getRegisterValue(Xmm1, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // Find data size and interpretation rule diff --git a/semantics/immediateInstructions/vperm2f128_ymm_ymm_ymm_imm8.k b/semantics/immediateInstructions/vperm2f128_ymm_ymm_ymm_imm8.k index 4c940b72c..1d22f5046 100644 --- a/semantics/immediateInstructions/vperm2f128_ymm_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vperm2f128_ymm_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPERM2F128-YMM-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vperm2f128 Imm8:Imm, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . + execinstr (vperm2f128 Imm8:MInt, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi)) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi), mi(128, 0)) #else concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi)) #fi) #fi) +convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi)) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi), mi(128, 0)) #else concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi)) #fi) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vperm2i128_ymm_ymm_ymm_imm8.k b/semantics/immediateInstructions/vperm2i128_ymm_ymm_ymm_imm8.k index b9a4907eb..40fd4a6c3 100644 --- a/semantics/immediateInstructions/vperm2i128_ymm_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vperm2i128_ymm_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPERM2I128-YMM-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vperm2i128 Imm8:Imm, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . + execinstr (vperm2i128 Imm8:MInt, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi)) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi), mi(128, 0)) #else concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi)) #fi) #fi) +convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi)) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi), mi(128, 0)) #else concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi) #fi) #fi)) #fi) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpermilpd_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpermilpd_xmm_xmm_imm8.k index c441f5301..e0fb6fd6f 100644 --- a/semantics/immediateInstructions/vpermilpd_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpermilpd_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPERMILPD-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpermilpd Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vpermilpd Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 192, 256) #else extractMInt( getParentValue(R2, RSMap), 128, 192) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 192, 256) #else extractMInt( getParentValue(R2, RSMap), 128, 192) #fi))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 192, 256) #else extractMInt( getParentValue(R2, RSMap), 128, 192) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 192, 256) #else extractMInt( getParentValue(R2, RSMap), 128, 192) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpermilpd_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpermilpd_ymm_ymm_imm8.k index 07ca15d3e..6651aa31b 100644 --- a/semantics/immediateInstructions/vpermilpd_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpermilpd_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPERMILPD-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpermilpd Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpermilpd Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 64, 128) #else extractMInt( getParentValue(R2, RSMap), 0, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 64, 128) #else extractMInt( getParentValue(R2, RSMap), 0, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 192, 256) #else extractMInt( getParentValue(R2, RSMap), 128, 192) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 192, 256) #else extractMInt( getParentValue(R2, RSMap), 128, 192) #fi)))) +convToRegKeys(R3) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 64, 128) #else extractMInt( getParentValue(R2, RSMap), 0, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 64, 128) #else extractMInt( getParentValue(R2, RSMap), 0, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 192, 256) #else extractMInt( getParentValue(R2, RSMap), 128, 192) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 192, 256) #else extractMInt( getParentValue(R2, RSMap), 128, 192) #fi)))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpermilps_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpermilps_xmm_xmm_imm8.k index 727ac08e7..5a164c79d 100644 --- a/semantics/immediateInstructions/vpermilps_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpermilps_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPERMILPS-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpermilps Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vpermilps Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpermilps_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpermilps_ymm_ymm_imm8.k index 8b3adeadc..3abae2dcc 100644 --- a/semantics/immediateInstructions/vpermilps_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpermilps_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPERMILPS-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpermilps Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpermilps Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 96, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 64, 96) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 96, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 64, 96) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 96, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 64, 96) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 96, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 64, 96) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi)))))))) +convToRegKeys(R3) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 96, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 64, 96) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 96, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 64, 96) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 96, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 64, 96) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 96, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 64, 96) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R2, RSMap), 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R2, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 2)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 128, 160) #fi) #fi) #fi)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpermpd_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpermpd_ymm_ymm_imm8.k index b5e96219c..606dcc5c5 100644 --- a/semantics/immediateInstructions/vpermpd_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpermpd_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPERMPD-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpermpd Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpermpd Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(256, 6))))), 192, 256), extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(256, 6))))), 192, 256)))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(256, 6))))), 192, 256), extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(256, 6))))), 192, 256)))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpermq_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpermq_ymm_ymm_imm8.k index 3fe351a2a..1232ef014 100644 --- a/semantics/immediateInstructions/vpermq_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpermq_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPERMQ-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpermq Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpermq Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(256, 6))))), 192, 256), extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(256, 6))))), 192, 256)))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(256, 6))))), 192, 256), extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(256, 6))))), 192, 256)))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpextrb_r32_xmm_imm8.k b/semantics/immediateInstructions/vpextrb_r32_xmm_imm8.k index 35ecc3140..0524d2b45 100644 --- a/semantics/immediateInstructions/vpextrb_r32_xmm_imm8.k +++ b/semantics/immediateInstructions/vpextrb_r32_xmm_imm8.k @@ -5,14 +5,15 @@ module VPEXTRB-R32-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpextrb Imm8:Imm, R2:Xmm, R3:R32, .Operands) => . + execinstr (vpextrb Imm8:MInt, R2:Xmm, R3:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(56, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3))))), 120, 128)) +convToRegKeys(R3) |-> concatenateMInt( mi(56, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3))))), 120, 128)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpextrb_r64_xmm_imm8.k b/semantics/immediateInstructions/vpextrb_r64_xmm_imm8.k index a2ca89da4..40228395e 100644 --- a/semantics/immediateInstructions/vpextrb_r64_xmm_imm8.k +++ b/semantics/immediateInstructions/vpextrb_r64_xmm_imm8.k @@ -5,14 +5,15 @@ module VPEXTRB-R64-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpextrb Imm8:Imm, R2:Xmm, R3:R64, .Operands) => . + execinstr (vpextrb Imm8:MInt, R2:Xmm, R3:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(56, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3))))), 120, 128)) +convToRegKeys(R3) |-> concatenateMInt( mi(56, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3))))), 120, 128)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpextrd_r32_xmm_imm8.k b/semantics/immediateInstructions/vpextrd_r32_xmm_imm8.k index f0fda9e43..a81b794de 100644 --- a/semantics/immediateInstructions/vpextrd_r32_xmm_imm8.k +++ b/semantics/immediateInstructions/vpextrd_r32_xmm_imm8.k @@ -5,14 +5,15 @@ module VPEXTRD-R32-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpextrd Imm8:Imm, R2:Xmm, R3:R32, .Operands) => . + execinstr (vpextrd Imm8:MInt, R2:Xmm, R3:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128)) +convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpextrq_r64_xmm_imm8.k b/semantics/immediateInstructions/vpextrq_r64_xmm_imm8.k index ce49e9beb..5c4b560c7 100644 --- a/semantics/immediateInstructions/vpextrq_r64_xmm_imm8.k +++ b/semantics/immediateInstructions/vpextrq_r64_xmm_imm8.k @@ -5,14 +5,15 @@ module VPEXTRQ-R64-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpextrq Imm8:Imm, R2:Xmm, R3:R64, .Operands) => . + execinstr (vpextrq Imm8:MInt, R2:Xmm, R3:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6))))), 64, 128) +convToRegKeys(R3) |-> extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6))))), 64, 128) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpextrw_r32_xmm_imm8.k b/semantics/immediateInstructions/vpextrw_r32_xmm_imm8.k index 259dfa487..63146196c 100644 --- a/semantics/immediateInstructions/vpextrw_r32_xmm_imm8.k +++ b/semantics/immediateInstructions/vpextrw_r32_xmm_imm8.k @@ -5,14 +5,15 @@ module VPEXTRW-R32-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpextrw Imm8:Imm, R2:Xmm, R3:R32, .Operands) => . + execinstr (vpextrw Imm8:MInt, R2:Xmm, R3:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(48, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4))))), 112, 128)) +convToRegKeys(R3) |-> concatenateMInt( mi(48, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4))))), 112, 128)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpextrw_r64_xmm_imm8.k b/semantics/immediateInstructions/vpextrw_r64_xmm_imm8.k index 5440cfd4e..e657e5e58 100644 --- a/semantics/immediateInstructions/vpextrw_r64_xmm_imm8.k +++ b/semantics/immediateInstructions/vpextrw_r64_xmm_imm8.k @@ -5,14 +5,15 @@ module VPEXTRW-R64-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpextrw Imm8:Imm, R2:Xmm, R3:R64, .Operands) => . + execinstr (vpextrw Imm8:MInt, R2:Xmm, R3:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(48, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4))))), 112, 128)) +convToRegKeys(R3) |-> concatenateMInt( mi(48, 0), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4))))), 112, 128)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpinsrb_xmm_xmm_r32_imm8.k b/semantics/immediateInstructions/vpinsrb_xmm_xmm_r32_imm8.k index d26e5998c..e721c9609 100644 --- a/semantics/immediateInstructions/vpinsrb_xmm_xmm_r32_imm8.k +++ b/semantics/immediateInstructions/vpinsrb_xmm_xmm_r32_imm8.k @@ -5,14 +5,15 @@ module VPINSRB-XMM-XMM-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (vpinsrb Imm8:Imm, R2:R32, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vpinsrb Imm8:MInt, R2:R32, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3))))), shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3)))))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3))))), shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpinsrd_xmm_xmm_r32_imm8.k b/semantics/immediateInstructions/vpinsrd_xmm_xmm_r32_imm8.k index 3f23f16c6..418d8fc0b 100644 --- a/semantics/immediateInstructions/vpinsrd_xmm_xmm_r32_imm8.k +++ b/semantics/immediateInstructions/vpinsrd_xmm_xmm_r32_imm8.k @@ -5,14 +5,15 @@ module VPINSRD-XMM-XMM-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (vpinsrd Imm8:Imm, R2:R32, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vpinsrd Imm8:MInt, R2:R32, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5)))))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpinsrq_xmm_xmm_r64_imm8.k b/semantics/immediateInstructions/vpinsrq_xmm_xmm_r64_imm8.k index f3960b7c0..46fc1dc36 100644 --- a/semantics/immediateInstructions/vpinsrq_xmm_xmm_r64_imm8.k +++ b/semantics/immediateInstructions/vpinsrq_xmm_xmm_r64_imm8.k @@ -5,14 +5,15 @@ module VPINSRQ-XMM-XMM-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (vpinsrq Imm8:Imm, R2:R64, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vpinsrq Imm8:MInt, R2:R64, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(64, 0), getParentValue(R2, RSMap)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6))))), shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6)))))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(64, 0), getParentValue(R2, RSMap)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6))))), shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpinsrw_xmm_xmm_r32_imm8.k b/semantics/immediateInstructions/vpinsrw_xmm_xmm_r32_imm8.k index 31194b38f..c6cf508d8 100644 --- a/semantics/immediateInstructions/vpinsrw_xmm_xmm_r32_imm8.k +++ b/semantics/immediateInstructions/vpinsrw_xmm_xmm_r32_imm8.k @@ -5,14 +5,15 @@ module VPINSRW-XMM-XMM-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (vpinsrw Imm8:Imm, R2:R32, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vpinsrw Imm8:MInt, R2:R32, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4))))), shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4)))))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), extractMInt( getParentValue(R2, RSMap), 32, 64)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4))))), shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpshufd_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpshufd_xmm_xmm_imm8.k index 3472952e6..50fceb521 100644 --- a/semantics/immediateInstructions/vpshufd_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpshufd_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPSHUFD-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpshufd Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vpshufd Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpshufd_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpshufd_ymm_ymm_imm8.k index be4fe86ec..e04937d7d 100644 --- a/semantics/immediateInstructions/vpshufd_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpshufd_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPSHUFD-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpshufd Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpshufd Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128)))))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpshufhw_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpshufhw_xmm_xmm_imm8.k index d5fab0cf4..abe2a617d 100644 --- a/semantics/immediateInstructions/vpshufhw_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpshufhw_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPSHUFHW-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpshufhw Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vpshufhw Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 4))))), 48, 64), extractMInt( getParentValue(R2, RSMap), 192, 256)))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 4))))), 48, 64), extractMInt( getParentValue(R2, RSMap), 192, 256)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpshufhw_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpshufhw_ymm_ymm_imm8.k index d6e51ede8..d07b65afd 100644 --- a/semantics/immediateInstructions/vpshufhw_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpshufhw_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPSHUFHW-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpshufhw Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpshufhw Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( getParentValue(R2, RSMap), 64, 128), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(256, 4))))), 176, 192), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(256, 4))))), 176, 192), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(256, 4))))), 176, 192), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(256, 4))))), 176, 192), extractMInt( getParentValue(R2, RSMap), 192, 256)))))))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( getParentValue(R2, RSMap), 64, 128), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(256, 4))))), 176, 192), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(256, 4))))), 176, 192), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(256, 4))))), 176, 192), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(256, 4))))), 176, 192), extractMInt( getParentValue(R2, RSMap), 192, 256)))))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpshuflw_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpshuflw_xmm_xmm_imm8.k index 01bbf9e9e..3f9d64295 100644 --- a/semantics/immediateInstructions/vpshuflw_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpshuflw_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPSHUFLW-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpshuflw Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vpshuflw Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 4))))), 112, 128), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 4))))), 112, 128)))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 4))))), 112, 128), extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 4))))), 112, 128)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpshuflw_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpshuflw_ymm_ymm_imm8.k index 399ccf9e8..94c3b26da 100644 --- a/semantics/immediateInstructions/vpshuflw_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpshuflw_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPSHUFLW-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpshuflw Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpshuflw Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 64), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(256, 4))))), 240, 256), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(256, 4))))), 240, 256), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(256, 4))))), 240, 256), extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(256, 4))))), 240, 256)))))))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 64), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(256, 4))))), 240, 256), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(256, 4))))), 240, 256), concatenateMInt( extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(256, 4))))), 240, 256), extractMInt( lshrMInt( getParentValue(R2, RSMap), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(256, 4))))), 240, 256)))))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpslld_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpslld_xmm_xmm_imm8.k index 0416825d9..4f658a82d 100644 --- a/semantics/immediateInstructions/vpslld_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpslld_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPSLLD-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpslld Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vpslld Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))))))) #fi) +convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))))))) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpslld_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpslld_ymm_ymm_imm8.k index 5b56fa543..97f28fe8f 100644 --- a/semantics/immediateInstructions/vpslld_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpslld_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPSLLD-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpslld Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpslld Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(256, 0) #else concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 0, 32), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 64, 96), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 96, 128), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8))))))))))) #fi) +convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(256, 0) #else concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 0, 32), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 64, 96), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 96, 128), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt(concatenateMInt( mi(24, 0), Imm8)))))))))) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpslldq_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpslldq_xmm_xmm_imm8.k index 1e838d7c9..81cadc725 100644 --- a/semantics/immediateInstructions/vpslldq_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpslldq_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPSLLDQ-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpslldq Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vpslldq Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), uvalueMInt(mi(128, 3)))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( Imm8, mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), Imm8) #fi), uvalueMInt(mi(128, 3)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpslldq_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpslldq_ymm_ymm_imm8.k index e0009cadf..a43d3df54 100644 --- a/semantics/immediateInstructions/vpslldq_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpslldq_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPSLLDQ-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpslldq Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpslldq Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), uvalueMInt(mi(128, 3))))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), uvalueMInt(mi(128, 3)))))) +convToRegKeys(R3) |-> concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( Imm8, mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), Imm8) #fi), uvalueMInt(mi(128, 3))))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( Imm8, mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), Imm8) #fi), uvalueMInt(mi(128, 3)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsllq_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpsllq_xmm_xmm_imm8.k index e68b60273..d9e9e3493 100644 --- a/semantics/immediateInstructions/vpsllq_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpsllq_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPSLLQ-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsllq Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vpsllq Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 63)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 256), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))))) #fi) +convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 63)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), uvalueMInt(concatenateMInt( mi(56, 0), Imm8))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 256), uvalueMInt(concatenateMInt( mi(56, 0), Imm8))))) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsllq_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpsllq_ymm_ymm_imm8.k index 286cd7035..44c5bda6f 100644 --- a/semantics/immediateInstructions/vpsllq_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpsllq_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPSLLQ-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsllq Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpsllq Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 63)) #then mi(256, 0) #else concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 0, 64), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 64, 128), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 256), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8))))))) #fi) +convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 63)) #then mi(256, 0) #else concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 0, 64), uvalueMInt(concatenateMInt( mi(56, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 64, 128), uvalueMInt(concatenateMInt( mi(56, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), uvalueMInt(concatenateMInt( mi(56, 0), Imm8))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 256), uvalueMInt(concatenateMInt( mi(56, 0), Imm8)))))) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsllw_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpsllw_xmm_xmm_imm8.k index 0b59f484b..50ec2c8de 100644 --- a/semantics/immediateInstructions/vpsllw_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpsllw_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPSLLW-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsllw Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vpsllw Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))))))))))) #fi) +convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))))))))))) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsllw_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpsllw_ymm_ymm_imm8.k index 3fb79d024..437973add 100644 --- a/semantics/immediateInstructions/vpsllw_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpsllw_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPSLLW-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsllw Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpsllw Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(256, 0) #else concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 0, 16), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 16, 32), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 32, 48), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 64, 80), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 80, 96), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 96, 112), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 112, 128), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8))))))))))))))))))) #fi) +convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(256, 0) #else concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 0, 16), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 16, 32), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 32, 48), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 64, 80), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 80, 96), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 96, 112), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 112, 128), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), shiftLeftMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt(concatenateMInt( mi(8, 0), Imm8)))))))))))))))))) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsrad_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpsrad_xmm_xmm_imm8.k index f0a77bc5d..1d2635672 100644 --- a/semantics/immediateInstructions/vpsrad_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpsrad_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPSRAD-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsrad Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vpsrad Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi))), aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsrad_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpsrad_ymm_ymm_imm8.k index 7b635e65b..f99b84776 100644 --- a/semantics/immediateInstructions/vpsrad_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpsrad_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPSRAD-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsrad Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpsrad Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 0, 32), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 64, 96), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 96, 128), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi)))))))))) +convToRegKeys(R3) |-> concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 0, 32), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 64, 96), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 96, 128), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi))), aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(32, 32) #else concatenateMInt( mi(24, 0), Imm8) #fi)))))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsraw_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpsraw_xmm_xmm_imm8.k index 045c6f45b..7f20cbf0d 100644 --- a/semantics/immediateInstructions/vpsraw_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpsraw_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPSRAW-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsraw Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vpsraw Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))))))))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))))))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsraw_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpsraw_ymm_ymm_imm8.k index 175af874e..0e7743c82 100644 --- a/semantics/immediateInstructions/vpsraw_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpsraw_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPSRAW-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsraw Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpsraw Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 0, 16), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 16, 32), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 32, 48), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 64, 80), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 80, 96), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 96, 112), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 112, 128), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi))), aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi)))))))))))))))))) +convToRegKeys(R3) |-> concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 0, 16), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 16, 32), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 32, 48), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 64, 80), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 80, 96), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 96, 112), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 112, 128), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), concatenateMInt( aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi))), aShiftRightMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt((#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(16, 16) #else concatenateMInt( mi(8, 0), Imm8) #fi)))))))))))))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsrld_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpsrld_xmm_xmm_imm8.k index 15da742b1..2a39b8f50 100644 --- a/semantics/immediateInstructions/vpsrld_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpsrld_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPSRLD-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsrld Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vpsrld Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))))))) #fi) +convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))))))) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsrld_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpsrld_ymm_ymm_imm8.k index 72a349d0f..978b933b9 100644 --- a/semantics/immediateInstructions/vpsrld_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpsrld_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPSRLD-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsrld Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpsrld Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 31)) #then mi(256, 0) #else concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 32), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 64, 96), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 96, 128), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt(concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8))))))))))) #fi) +convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 31)) #then mi(256, 0) #else concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 32), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 64, 96), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 96, 128), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 160), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 160, 192), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 224), uvalueMInt(concatenateMInt( mi(24, 0), Imm8))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 224, 256), uvalueMInt(concatenateMInt( mi(24, 0), Imm8)))))))))) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsrldq_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpsrldq_xmm_xmm_imm8.k index 4fff94a26..694d609ba 100644 --- a/semantics/immediateInstructions/vpsrldq_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpsrldq_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPSRLDQ-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsrldq Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vpsrldq Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), uvalueMInt(mi(128, 3)))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( Imm8, mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), Imm8) #fi), uvalueMInt(mi(128, 3)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsrldq_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpsrldq_ymm_ymm_imm8.k index 1c84a8358..5b96863c9 100644 --- a/semantics/immediateInstructions/vpsrldq_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpsrldq_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPSRLDQ-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsrldq Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpsrldq Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), uvalueMInt(mi(128, 3))))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), uvalueMInt(mi(128, 3)))))) +convToRegKeys(R3) |-> concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 128), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( Imm8, mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), Imm8) #fi), uvalueMInt(mi(128, 3))))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( (#ifMInt ugtMInt( Imm8, mi(8, 15)) #then concatenateMInt( mi(120, 0), mi(8, 16)) #else concatenateMInt( mi(120, 0), Imm8) #fi), uvalueMInt(mi(128, 3)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsrlq_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpsrlq_xmm_xmm_imm8.k index a9f028f37..e939ba5fb 100644 --- a/semantics/immediateInstructions/vpsrlq_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpsrlq_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPSRLQ-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsrlq Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vpsrlq Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 63)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 256), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))))) #fi) +convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 63)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), uvalueMInt(concatenateMInt( mi(56, 0), Imm8))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 256), uvalueMInt(concatenateMInt( mi(56, 0), Imm8))))) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsrlq_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpsrlq_ymm_ymm_imm8.k index dc8e3143c..e17bbf1b4 100644 --- a/semantics/immediateInstructions/vpsrlq_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpsrlq_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPSRLQ-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsrlq Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpsrlq Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 63)) #then mi(256, 0) #else concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 64), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 64, 128), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 256), uvalueMInt(concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8))))))) #fi) +convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 63)) #then mi(256, 0) #else concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 64), uvalueMInt(concatenateMInt( mi(56, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 64, 128), uvalueMInt(concatenateMInt( mi(56, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 192), uvalueMInt(concatenateMInt( mi(56, 0), Imm8))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 256), uvalueMInt(concatenateMInt( mi(56, 0), Imm8)))))) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsrlw_xmm_xmm_imm8.k b/semantics/immediateInstructions/vpsrlw_xmm_xmm_imm8.k index feaac5ed6..fdfc88fc9 100644 --- a/semantics/immediateInstructions/vpsrlw_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vpsrlw_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VPSRLW-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsrlw Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vpsrlw Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))))))))))) #fi) +convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))))))))))) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vpsrlw_ymm_ymm_imm8.k b/semantics/immediateInstructions/vpsrlw_ymm_ymm_imm8.k index 468b8c297..895e2511d 100644 --- a/semantics/immediateInstructions/vpsrlw_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vpsrlw_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VPSRLW-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vpsrlw Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vpsrlw Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 15)) #then mi(256, 0) #else concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 16), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 16, 32), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 32, 48), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 64, 80), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 80, 96), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 96, 112), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 112, 128), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8)))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt(concatenateMInt( mi(8, 0), handleImmediateWithSignExtend(Imm8, 8, 8))))))))))))))))))) #fi) +convToRegKeys(R3) |-> (#ifMInt ugtMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 15)) #then mi(256, 0) #else concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 0, 16), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 16, 32), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 32, 48), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 64, 80), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 80, 96), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 96, 112), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 112, 128), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 144), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 144, 160), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 160, 176), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 176, 192), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 192, 208), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 208, 224), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), concatenateMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 224, 240), uvalueMInt(concatenateMInt( mi(8, 0), Imm8))), lshrMInt( extractMInt( getParentValue(R2, RSMap), 240, 256), uvalueMInt(concatenateMInt( mi(8, 0), Imm8)))))))))))))))))) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vroundpd_xmm_xmm_imm8.k b/semantics/immediateInstructions/vroundpd_xmm_xmm_imm8.k index 050188897..db640f24d 100644 --- a/semantics/immediateInstructions/vroundpd_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vroundpd_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VROUNDPD-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vroundpd Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vroundpd Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 128, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 192, 256), handleImmediateWithSignExtend(Imm8, 8, 8)))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 128, 192), Imm8), cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 192, 256), Imm8))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vroundpd_ymm_ymm_imm8.k b/semantics/immediateInstructions/vroundpd_ymm_ymm_imm8.k index 482e8f7d6..12b0c8742 100644 --- a/semantics/immediateInstructions/vroundpd_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vroundpd_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VROUNDPD-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vroundpd Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vroundpd Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 0, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 64, 128), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 128, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 192, 256), handleImmediateWithSignExtend(Imm8, 8, 8))))) +convToRegKeys(R3) |-> concatenateMInt( cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 0, 64), Imm8), concatenateMInt( cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 64, 128), Imm8), concatenateMInt( cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 128, 192), Imm8), cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 192, 256), Imm8)))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vroundps_xmm_xmm_imm8.k b/semantics/immediateInstructions/vroundps_xmm_xmm_imm8.k index 42d2190ce..9d699c753 100644 --- a/semantics/immediateInstructions/vroundps_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vroundps_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VROUNDPS-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vroundps Imm8:Imm, R2:Xmm, R3:Xmm, .Operands) => . + execinstr (vroundps Imm8:MInt, R2:Xmm, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 128, 160), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 160, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 192, 224), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8)))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 128, 160), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 160, 192), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 192, 224), Imm8), cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), Imm8))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vroundps_ymm_ymm_imm8.k b/semantics/immediateInstructions/vroundps_ymm_ymm_imm8.k index 72063c856..368824159 100644 --- a/semantics/immediateInstructions/vroundps_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vroundps_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VROUNDPS-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vroundps Imm8:Imm, R2:Ymm, R3:Ymm, .Operands) => . + execinstr (vroundps Imm8:MInt, R2:Ymm, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 0, 32), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 32, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 64, 96), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 96, 128), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 128, 160), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 160, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 192, 224), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8))))))))) +convToRegKeys(R3) |-> concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 0, 32), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 32, 64), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 64, 96), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 96, 128), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 128, 160), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 160, 192), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 192, 224), Imm8), cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), Imm8)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vroundsd_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vroundsd_xmm_xmm_xmm_imm8.k index 7d492fc1b..57adaac82 100644 --- a/semantics/immediateInstructions/vroundsd_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vroundsd_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VROUNDSD-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vroundsd Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vroundsd Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 192), cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 192, 256), handleImmediateWithSignExtend(Imm8, 8, 8)))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 192), cvt_double_to_int64_rm(extractMInt( getParentValue(R2, RSMap), 192, 256), Imm8))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vroundss_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vroundss_xmm_xmm_xmm_imm8.k index a6db9c2ce..ebbc20f6a 100644 --- a/semantics/immediateInstructions/vroundss_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vroundss_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VROUNDSS-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vroundss Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vroundss Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 224), cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8)))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 224), cvt_single_to_int32_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), Imm8))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vshufpd_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vshufpd_xmm_xmm_xmm_imm8.k index 329f78599..997df08cc 100644 --- a/semantics/immediateInstructions/vshufpd_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vshufpd_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VSHUFPD-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vshufpd Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vshufpd Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 192) #else extractMInt( getParentValue(R2, RSMap), 192, 256) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R3, RSMap), 192, 256) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 192) #else extractMInt( getParentValue(R2, RSMap), 192, 256) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R3, RSMap), 192, 256) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vshufpd_ymm_ymm_ymm_imm8.k b/semantics/immediateInstructions/vshufpd_ymm_ymm_ymm_imm8.k index 1ce14cee5..3460a1480 100644 --- a/semantics/immediateInstructions/vshufpd_ymm_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vshufpd_ymm_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VSHUFPD-YMM-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vshufpd Imm8:Imm, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . + execinstr (vshufpd Imm8:MInt, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 0, 64) #else extractMInt( getParentValue(R2, RSMap), 64, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 64) #else extractMInt( getParentValue(R3, RSMap), 64, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 192) #else extractMInt( getParentValue(R2, RSMap), 192, 256) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R3, RSMap), 192, 256) #fi)))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 0, 64) #else extractMInt( getParentValue(R2, RSMap), 64, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 64) #else extractMInt( getParentValue(R3, RSMap), 64, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 192) #else extractMInt( getParentValue(R2, RSMap), 192, 256) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R3, RSMap), 192, 256) #fi)))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vshufps_xmm_xmm_xmm_imm8.k b/semantics/immediateInstructions/vshufps_xmm_xmm_xmm_imm8.k index 3a944fb06..ca649b4cd 100644 --- a/semantics/immediateInstructions/vshufps_xmm_xmm_xmm_imm8.k +++ b/semantics/immediateInstructions/vshufps_xmm_xmm_xmm_imm8.k @@ -5,14 +5,15 @@ module VSHUFPS-XMM-XMM-XMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vshufps Imm8:Imm, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . + execinstr (vshufps Imm8:MInt, R2:Xmm, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/vshufps_ymm_ymm_ymm_imm8.k b/semantics/immediateInstructions/vshufps_ymm_ymm_ymm_imm8.k index 30a23256e..38a41a71d 100644 --- a/semantics/immediateInstructions/vshufps_ymm_ymm_ymm_imm8.k +++ b/semantics/immediateInstructions/vshufps_ymm_ymm_ymm_imm8.k @@ -5,14 +5,15 @@ module VSHUFPS-YMM-YMM-YMM-IMM8 imports X86-CONFIGURATION rule - execinstr (vshufps Imm8:Imm, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . + execinstr (vshufps Imm8:MInt, R2:Ymm, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 0, 32) #else extractMInt( getParentValue(R2, RSMap), 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 0, 32) #else extractMInt( getParentValue(R2, RSMap), 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( getParentValue(R3, RSMap), 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( getParentValue(R3, RSMap), 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( getParentValue(R3, RSMap), 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( getParentValue(R3, RSMap), 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi)))))))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 0, 32) #else extractMInt( getParentValue(R2, RSMap), 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 0, 32) #else extractMInt( getParentValue(R2, RSMap), 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 32, 64) #else extractMInt( getParentValue(R2, RSMap), 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( getParentValue(R3, RSMap), 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( getParentValue(R3, RSMap), 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( getParentValue(R3, RSMap), 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( getParentValue(R3, RSMap), 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 128, 160) #else extractMInt( getParentValue(R2, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( getParentValue(R2, RSMap), 160, 192) #else extractMInt( getParentValue(R2, RSMap), 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/xorb_al_imm8.k b/semantics/immediateInstructions/xorb_al_imm8.k index 0af254597..1018d6075 100644 --- a/semantics/immediateInstructions/xorb_al_imm8.k +++ b/semantics/immediateInstructions/xorb_al_imm8.k @@ -5,26 +5,27 @@ module XORB-AL-IMM8 imports X86-CONFIGURATION rule - execinstr (xorb Imm8:Imm, %al, .Operands) => . + execinstr (xorb Imm8:MInt, %al, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 56), xorMInt( extractMInt( getParentValue(%rax, RSMap), 56, 64), handleImmediateWithSignExtend(Imm8, 8, 8))) +"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 56), xorMInt( extractMInt( getParentValue(%rax, RSMap), 56, 64), Imm8)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 56, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 56, 64), Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> xorMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/xorb_r8_imm8.k b/semantics/immediateInstructions/xorb_r8_imm8.k index ec7753259..eae9a2526 100644 --- a/semantics/immediateInstructions/xorb_r8_imm8.k +++ b/semantics/immediateInstructions/xorb_r8_imm8.k @@ -5,26 +5,27 @@ module XORB-R8-IMM8 imports X86-CONFIGURATION rule - execinstr (xorb Imm8:Imm, R2:R8, .Operands) => . + execinstr (xorb Imm8:MInt, R2:R8, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), handleImmediateWithSignExtend(Imm8, 8, 8))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 56), xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), Imm8)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 64), Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/xorb_rh_imm8.k b/semantics/immediateInstructions/xorb_rh_imm8.k index a9a3ea477..19c5fe0e3 100644 --- a/semantics/immediateInstructions/xorb_rh_imm8.k +++ b/semantics/immediateInstructions/xorb_rh_imm8.k @@ -5,26 +5,27 @@ module XORB-RH-IMM8 imports X86-CONFIGURATION rule - execinstr (xorb Imm8:Imm, R2:Rh, .Operands) => . + execinstr (xorb Imm8:MInt, R2:Rh, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), handleImmediateWithSignExtend(Imm8, 8, 8))), extractMInt( getParentValue(R2, RSMap), 56, 64)) +convToRegKeys(R2) |-> concatenateMInt( concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), Imm8)), extractMInt( getParentValue(R2, RSMap), 56, 64)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 55, 56), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 54, 55), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 53, 54), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 52, 53), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 51, 52), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 50, 51), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 49, 50), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 55, 56), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 54, 55), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 53, 54), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 52, 53), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 51, 52), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 50, 51), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 49, 50), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 56), Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/xorl_eax_imm32.k b/semantics/immediateInstructions/xorl_eax_imm32.k index dc84f2486..1feaf1add 100644 --- a/semantics/immediateInstructions/xorl_eax_imm32.k +++ b/semantics/immediateInstructions/xorl_eax_imm32.k @@ -5,26 +5,27 @@ module XORL-EAX-IMM32 imports X86-CONFIGURATION rule - execinstr (xorl Imm32:Imm, %eax, .Operands) => . + execinstr (xorl Imm32:MInt, %eax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( mi(32, 0), xorMInt( extractMInt( getParentValue(%rax, RSMap), 32, 64), handleImmediateWithSignExtend(Imm32, 32, 32))) +"RAX" |-> concatenateMInt( mi(32, 0), xorMInt( extractMInt( getParentValue(%rax, RSMap), 32, 64), Imm32)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 32, 64), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 32, 64), Imm32), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)) +"SF" |-> xorMInt( extractMInt( getParentValue(%rax, RSMap), 32, 33), extractMInt( Imm32, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/xorl_r32_imm32.k b/semantics/immediateInstructions/xorl_r32_imm32.k index 8e127eefa..f279404c0 100644 --- a/semantics/immediateInstructions/xorl_r32_imm32.k +++ b/semantics/immediateInstructions/xorl_r32_imm32.k @@ -5,26 +5,27 @@ module XORL-R32-IMM32 imports X86-CONFIGURATION rule - execinstr (xorl Imm32:Imm, R2:R32, .Operands) => . + execinstr (xorl Imm32:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), xorMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), handleImmediateWithSignExtend(Imm32, 32, 32))) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), xorMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), Imm32)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), Imm32), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)) +"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), extractMInt( Imm32, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/xorl_r32_imm8.k b/semantics/immediateInstructions/xorl_r32_imm8.k index aa2031d02..5cf1b3a09 100644 --- a/semantics/immediateInstructions/xorl_r32_imm8.k +++ b/semantics/immediateInstructions/xorl_r32_imm8.k @@ -5,26 +5,27 @@ module XORL-R32-IMM8 imports X86-CONFIGURATION rule - execinstr (xorl Imm8:Imm, R2:R32, .Operands) => . + execinstr (xorl Imm8:MInt, R2:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), xorMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), xorMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, svalueMInt(Imm8)))) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, svalueMInt(Imm8))), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 32, 33), extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/xorq_r64_imm32.k b/semantics/immediateInstructions/xorq_r64_imm32.k index f70089ca8..f9e3547b8 100644 --- a/semantics/immediateInstructions/xorq_r64_imm32.k +++ b/semantics/immediateInstructions/xorq_r64_imm32.k @@ -5,26 +5,27 @@ module XORQ-R64-IMM32 imports X86-CONFIGURATION rule - execinstr (xorq Imm32:Imm, R2:R64, .Operands) => . + execinstr (xorq Imm32:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> xorMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) +convToRegKeys(R2) |-> xorMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(Imm32))) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(Imm32))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)) +"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/xorq_r64_imm8.k b/semantics/immediateInstructions/xorq_r64_imm8.k index 62f739c12..63a2c5565 100644 --- a/semantics/immediateInstructions/xorq_r64_imm8.k +++ b/semantics/immediateInstructions/xorq_r64_imm8.k @@ -5,26 +5,27 @@ module XORQ-R64-IMM8 imports X86-CONFIGURATION rule - execinstr (xorq Imm8:Imm, R2:R64, .Operands) => . + execinstr (xorq Imm8:MInt, R2:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> xorMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) +convToRegKeys(R2) |-> xorMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(Imm8))) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( getParentValue(R2, RSMap), mi(64, svalueMInt(Imm8))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/immediateInstructions/xorq_rax_imm32.k b/semantics/immediateInstructions/xorq_rax_imm32.k index 3a645ba0b..48229bb94 100644 --- a/semantics/immediateInstructions/xorq_rax_imm32.k +++ b/semantics/immediateInstructions/xorq_rax_imm32.k @@ -5,26 +5,27 @@ module XORQ-RAX-IMM32 imports X86-CONFIGURATION rule - execinstr (xorq Imm32:Imm, %rax, .Operands) => . + execinstr (xorq Imm32:MInt, %rax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> xorMInt( getParentValue(%rax, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) +"RAX" |-> xorMInt( getParentValue(%rax, RSMap), mi(64, svalueMInt(Imm32))) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( getParentValue(%rax, RSMap), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( getParentValue(%rax, RSMap), mi(64, svalueMInt(Imm32))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)) +"SF" |-> xorMInt( extractMInt( getParentValue(%rax, RSMap), 0, 1), extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/immediateInstructions/xorw_ax_imm16.k b/semantics/immediateInstructions/xorw_ax_imm16.k index c5e109e8d..054d767ef 100644 --- a/semantics/immediateInstructions/xorw_ax_imm16.k +++ b/semantics/immediateInstructions/xorw_ax_imm16.k @@ -5,26 +5,27 @@ module XORW-AX-IMM16 imports X86-CONFIGURATION rule - execinstr (xorw Imm16:Imm, %ax, .Operands) => . + execinstr (xorw Imm16:MInt, %ax, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 48), xorMInt( extractMInt( getParentValue(%rax, RSMap), 48, 64), handleImmediateWithSignExtend(Imm16, 16, 16))) +"RAX" |-> concatenateMInt( extractMInt( getParentValue(%rax, RSMap), 0, 48), xorMInt( extractMInt( getParentValue(%rax, RSMap), 48, 64), Imm16)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 15, 16)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 14, 15)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 13, 14)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 12, 13)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 10, 11)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 9, 10)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 63, 64), extractMInt( Imm16, 15, 16)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 62, 63), extractMInt( Imm16, 14, 15)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 61, 62), extractMInt( Imm16, 13, 14)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 60, 61), extractMInt( Imm16, 12, 13)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 59, 60), extractMInt( Imm16, 11, 12)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 58, 59), extractMInt( Imm16, 10, 11)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 57, 58), extractMInt( Imm16, 9, 10)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 56, 57), extractMInt( Imm16, 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 48, 64), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(%rax, RSMap), 48, 64), Imm16), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)) +"SF" |-> xorMInt( extractMInt( getParentValue(%rax, RSMap), 48, 49), extractMInt( Imm16, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/xorw_r16_imm16.k b/semantics/immediateInstructions/xorw_r16_imm16.k index fcd512cc9..b66317629 100644 --- a/semantics/immediateInstructions/xorw_r16_imm16.k +++ b/semantics/immediateInstructions/xorw_r16_imm16.k @@ -5,26 +5,27 @@ module XORW-R16-IMM16 imports X86-CONFIGURATION rule - execinstr (xorw Imm16:Imm, R2:R16, .Operands) => . + execinstr (xorw Imm16:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), handleImmediateWithSignExtend(Imm16, 16, 16))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), Imm16)) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 15, 16)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 14, 15)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 13, 14)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 12, 13)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 10, 11)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 9, 10)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm16, 15, 16)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm16, 14, 15)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm16, 13, 14)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm16, 12, 13)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm16, 11, 12)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm16, 10, 11)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm16, 9, 10)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm16, 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), Imm16), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)) +"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( Imm16, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/immediateInstructions/xorw_r16_imm8.k b/semantics/immediateInstructions/xorw_r16_imm8.k index 2c9571a15..010dad89a 100644 --- a/semantics/immediateInstructions/xorw_r16_imm8.k +++ b/semantics/immediateInstructions/xorw_r16_imm8.k @@ -5,26 +5,27 @@ module XORW-R16-IMM8 imports X86-CONFIGURATION rule - execinstr (xorw Imm8:Imm, R2:R16, .Operands) => . + execinstr (xorw Imm8:MInt, R2:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) +convToRegKeys(R2) |-> concatenateMInt( extractMInt( getParentValue(R2, RSMap), 0, 48), xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(16, svalueMInt(Imm8)))) "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 64), mi(16, svalueMInt(Imm8))), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> xorMInt( extractMInt( getParentValue(R2, RSMap), 48, 49), extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/adcb_m8_imm8.k b/semantics/memoryInstructions/adcb_m8_imm8.k index 5e7da5cb1..aeb2b1e6a 100644 --- a/semantics/memoryInstructions/adcb_m8_imm8.k +++ b/semantics/memoryInstructions/adcb_m8_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ADCB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(adcb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(adcb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (adcb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (adcb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (adcb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (adcb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (adcb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 9), + extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 9), MemOff, 8 ) @@ -25,17 +26,18 @@ module ADCB-M8-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), Mem8)), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), Mem8)), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), Mem8)), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), Mem8)), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), Mem8)), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), Mem8)), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), Mem8)), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), Mem8)), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), Mem8)), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), Mem8)), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), Mem8)), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), Mem8)), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), Mem8)), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), Mem8)), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), Mem8)), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), Mem8)), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem8, 3, 4)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), Mem8)), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem8, 3, 4)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), Mem8)), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem8, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(9, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem8, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm8), mi(9, 1)) #else concatenateMInt( mi(1, 0), Imm8) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/adcl_m32_imm32.k b/semantics/memoryInstructions/adcl_m32_imm32.k index aba9f1336..59969d39c 100644 --- a/semantics/memoryInstructions/adcl_m32_imm32.k +++ b/semantics/memoryInstructions/adcl_m32_imm32.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ADCL-M32-IMM32 imports X86-CONFIGURATION - context execinstr(adcl:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(adcl:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (adcl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (adcl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (adcl Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (adcl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (adcl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), + extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), MemOff, 32 ) @@ -25,17 +26,18 @@ module ADCL-M32-IMM32 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), Mem32)), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), Mem32)), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), mi(33, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm32, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm32, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm32), mi(33, 1)) #else concatenateMInt( mi(1, 0), Imm32) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/adcl_m32_imm8.k b/semantics/memoryInstructions/adcl_m32_imm8.k index df520b7c7..75b1baffd 100644 --- a/semantics/memoryInstructions/adcl_m32_imm8.k +++ b/semantics/memoryInstructions/adcl_m32_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ADCL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(adcl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(adcl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (adcl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (adcl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (adcl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (adcl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (adcl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), + extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), MemOff, 32 ) @@ -25,17 +26,18 @@ module ADCL-M32-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem32)), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem32)), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), mi(33, 1)) #else concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/adcq_m64_imm32.k b/semantics/memoryInstructions/adcq_m64_imm32.k index a9231fbd6..4114ab313 100644 --- a/semantics/memoryInstructions/adcq_m64_imm32.k +++ b/semantics/memoryInstructions/adcq_m64_imm32.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ADCQ-M64-IMM32 imports X86-CONFIGURATION - context execinstr(adcq:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(adcq:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (adcq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (adcq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (adcq Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (adcq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (adcq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), + extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), MemOff, 64 ) @@ -25,17 +26,18 @@ module ADCQ-M64-IMM32 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), Mem64)), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/adcq_m64_imm8.k b/semantics/memoryInstructions/adcq_m64_imm8.k index 19d1c3614..ebe1b2d1b 100644 --- a/semantics/memoryInstructions/adcq_m64_imm8.k +++ b/semantics/memoryInstructions/adcq_m64_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ADCQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(adcq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(adcq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (adcq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (adcq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (adcq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (adcq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (adcq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), + extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), MemOff, 64 ) @@ -25,17 +26,18 @@ module ADCQ-M64-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem64)), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), mi(65, 1)) #else concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/adcw_m16_imm16.k b/semantics/memoryInstructions/adcw_m16_imm16.k index 7d42ab352..06bb87e88 100644 --- a/semantics/memoryInstructions/adcw_m16_imm16.k +++ b/semantics/memoryInstructions/adcw_m16_imm16.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ADCW-M16-IMM16 imports X86-CONFIGURATION - context execinstr(adcw:Opcode Imm16:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(adcw:Opcode Imm16:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (adcw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (adcw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (adcw Imm16, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm16) ==Int 16 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (adcw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (adcw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), + extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), MemOff, 16 ) @@ -25,17 +26,18 @@ module ADCW-M16-IMM16 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), Mem16)), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), Mem16)), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm16, 11, 12), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), mi(17, 1)) #else concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm16, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm16, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), Imm16), mi(17, 1)) #else concatenateMInt( mi(1, 0), Imm16) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/memoryInstructions/adcw_m16_imm8.k b/semantics/memoryInstructions/adcw_m16_imm8.k index b665e40e5..619f4a481 100644 --- a/semantics/memoryInstructions/adcw_m16_imm8.k +++ b/semantics/memoryInstructions/adcw_m16_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ADCW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(adcw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(adcw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (adcw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (adcw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (adcw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (adcw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (adcw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), + extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), MemOff, 16 ) @@ -25,17 +26,18 @@ module ADCW-M16-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem16)), 0, 1) +"CF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem16)), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), mi(17, 1)) #else concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/addb_m8_imm8.k b/semantics/memoryInstructions/addb_m8_imm8.k index 95b1b0027..34879efa5 100644 --- a/semantics/memoryInstructions/addb_m8_imm8.k +++ b/semantics/memoryInstructions/addb_m8_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ADDB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(addb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(addb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (addb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (addb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (addb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (addb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (addb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), Mem8)), 1, 9), + extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), Mem8)), 1, 9), MemOff, 8 ) @@ -25,17 +26,18 @@ module ADDB-M8-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), Mem8)), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), Mem8)), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), Mem8)), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), Mem8)), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), Mem8)), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), Mem8)), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), Mem8)), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), Mem8)), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), Mem8)), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), Mem8)), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), Mem8)), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), Mem8)), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), Mem8)), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), Mem8)), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), Mem8)), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), Mem8)), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem8, 3, 4)), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), Mem8)), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem8, 3, 4)), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), Mem8)), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), Mem8)), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), Mem8)), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), Mem8)), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), Mem8)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem8, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem8, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm8), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/addl_m32_imm32.k b/semantics/memoryInstructions/addl_m32_imm32.k index 028c9ad0d..52363d96b 100644 --- a/semantics/memoryInstructions/addl_m32_imm32.k +++ b/semantics/memoryInstructions/addl_m32_imm32.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ADDL-M32-IMM32 imports X86-CONFIGURATION - context execinstr(addl:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(addl:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (addl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (addl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (addl Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (addl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (addl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), Mem32)), 1, 33), + extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), Mem32)), 1, 33), MemOff, 32 ) @@ -25,17 +26,18 @@ module ADDL-M32-IMM32 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), Mem32)), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), Mem32)), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), Mem32)), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), Mem32)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm32, 32, 32)), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm32, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm32, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm32), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/addl_m32_imm8.k b/semantics/memoryInstructions/addl_m32_imm8.k index aecf5b636..0ef6c6e3b 100644 --- a/semantics/memoryInstructions/addl_m32_imm8.k +++ b/semantics/memoryInstructions/addl_m32_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ADDL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(addl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(addl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (addl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (addl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (addl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (addl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (addl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem32)), 1, 33), + extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem32)), 1, 33), MemOff, 32 ) @@ -25,17 +26,18 @@ module ADDL-M32-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem32)), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem32)), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem32)), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem32)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(32, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/addq_m64_imm32.k b/semantics/memoryInstructions/addq_m64_imm32.k index 88d7d7eca..bb7500194 100644 --- a/semantics/memoryInstructions/addq_m64_imm32.k +++ b/semantics/memoryInstructions/addq_m64_imm32.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ADDQ-M64-IMM32 imports X86-CONFIGURATION - context execinstr(addq:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(addq:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (addq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (addq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (addq Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (addq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (addq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), Mem64)), 1, 65), + extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), Mem64)), 1, 65), MemOff, 64 ) @@ -25,17 +26,18 @@ module ADDQ-M64-IMM32 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), Mem64)), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), Mem64)), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), Mem64)), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), Mem64)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm32))), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/addq_m64_imm8.k b/semantics/memoryInstructions/addq_m64_imm8.k index 878771cb0..71c47e1ad 100644 --- a/semantics/memoryInstructions/addq_m64_imm8.k +++ b/semantics/memoryInstructions/addq_m64_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ADDQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(addq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(addq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (addq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (addq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (addq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (addq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (addq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem64)), 1, 65), + extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem64)), 1, 65), MemOff, 64 ) @@ -25,17 +26,18 @@ module ADDQ-M64-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem64)), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem64)), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem64)), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem64)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(64, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/addw_m16_imm16.k b/semantics/memoryInstructions/addw_m16_imm16.k index c25bfea41..a9f6efd35 100644 --- a/semantics/memoryInstructions/addw_m16_imm16.k +++ b/semantics/memoryInstructions/addw_m16_imm16.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ADDW-M16-IMM16 imports X86-CONFIGURATION - context execinstr(addw:Opcode Imm16:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(addw:Opcode Imm16:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (addw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (addw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (addw Imm16, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm16) ==Int 16 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (addw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (addw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), Mem16)), 1, 17), + extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), Mem16)), 1, 17), MemOff, 16 ) @@ -25,17 +26,18 @@ module ADDW-M16-IMM16 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), Mem16)), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), Mem16)), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm16, 11, 12), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), Mem16)), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), Mem16)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), handleImmediateWithSignExtend(Imm16, 16, 16)), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( Imm16, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( Imm16, 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), Imm16), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/memoryInstructions/addw_m16_imm8.k b/semantics/memoryInstructions/addw_m16_imm8.k index b4e762107..f794ce67e 100644 --- a/semantics/memoryInstructions/addw_m16_imm8.k +++ b/semantics/memoryInstructions/addw_m16_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ADDW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(addw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(addw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (addw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (addw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (addw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (addw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (addw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem16)), 1, 17), + extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem16)), 1, 17), MemOff, 16 ) @@ -25,17 +26,18 @@ module ADDW-M16-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem16)), 0, 1) +"CF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem16)), 0, 1) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem16)), 1, 2) +"SF" |-> extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem16)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( concatenateMInt( mi(1, 0), mi(16, svalueMInt(Imm8))), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/andb_m8_imm8.k b/semantics/memoryInstructions/andb_m8_imm8.k index 4d8477121..773d06975 100644 --- a/semantics/memoryInstructions/andb_m8_imm8.k +++ b/semantics/memoryInstructions/andb_m8_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ANDB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(andb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(andb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (andb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (andb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (andb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (andb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (andb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - andMInt( Mem8, handleImmediateWithSignExtend(Imm8, 8, 8)), + andMInt( Mem8, Imm8), MemOff, 8 ) @@ -27,15 +28,16 @@ module ANDB-M8-IMM8 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem8, 7, 8), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem8, 6, 7), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 5, 6), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 4, 5), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 3, 4), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 2, 3), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 1, 2), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem8, 7, 8), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem8, 6, 7), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 5, 6), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 4, 5), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 3, 4), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 2, 3), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 1, 2), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 0, 1), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( Mem8, handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( Mem8, Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( Mem8, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> andMInt( extractMInt( Mem8, 0, 1), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/andl_m32_imm32.k b/semantics/memoryInstructions/andl_m32_imm32.k index 3db2f3670..43bb2a437 100644 --- a/semantics/memoryInstructions/andl_m32_imm32.k +++ b/semantics/memoryInstructions/andl_m32_imm32.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ANDL-M32-IMM32 imports X86-CONFIGURATION - context execinstr(andl:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(andl:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (andl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (andl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (andl Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (andl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (andl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - andMInt( Mem32, handleImmediateWithSignExtend(Imm32, 32, 32)), + andMInt( Mem32, Imm32), MemOff, 32 ) @@ -27,15 +28,16 @@ module ANDL-M32-IMM32 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem32, 31, 32), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem32, 30, 31), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 29, 30), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 28, 29), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 27, 28), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 26, 27), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 25, 26), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 24, 25), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem32, 31, 32), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem32, 30, 31), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 29, 30), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 28, 29), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 27, 28), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 26, 27), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 25, 26), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 24, 25), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( Mem32, handleImmediateWithSignExtend(Imm32, 32, 32)), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( Mem32, Imm32), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( Mem32, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)) +"SF" |-> andMInt( extractMInt( Mem32, 0, 1), extractMInt( Imm32, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/andl_m32_imm8.k b/semantics/memoryInstructions/andl_m32_imm8.k index 7456a323c..74bff59dd 100644 --- a/semantics/memoryInstructions/andl_m32_imm8.k +++ b/semantics/memoryInstructions/andl_m32_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ANDL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(andl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(andl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (andl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (andl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (andl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (andl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (andl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - andMInt( Mem32, mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), + andMInt( Mem32, mi(32, svalueMInt(Imm8))), MemOff, 32 ) @@ -27,15 +28,16 @@ module ANDL-M32-IMM8 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem32, 31, 32), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem32, 30, 31), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 29, 30), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 28, 29), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 27, 28), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 26, 27), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 25, 26), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 24, 25), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem32, 31, 32), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem32, 30, 31), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 29, 30), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 28, 29), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 27, 28), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 26, 27), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 25, 26), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 24, 25), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( Mem32, mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( Mem32, mi(32, svalueMInt(Imm8))), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( Mem32, 0, 1), extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> andMInt( extractMInt( Mem32, 0, 1), extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/andq_m64_imm32.k b/semantics/memoryInstructions/andq_m64_imm32.k index 9cde4fc91..363c9d58f 100644 --- a/semantics/memoryInstructions/andq_m64_imm32.k +++ b/semantics/memoryInstructions/andq_m64_imm32.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ANDQ-M64-IMM32 imports X86-CONFIGURATION - context execinstr(andq:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(andq:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (andq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (andq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (andq Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (andq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (andq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - andMInt( Mem64, mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), + andMInt( Mem64, mi(64, svalueMInt(Imm32))), MemOff, 64 ) @@ -27,15 +28,16 @@ module ANDQ-M64-IMM32 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem64, 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem64, 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem64, 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem64, 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( Mem64, mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( Mem64, mi(64, svalueMInt(Imm32))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( Mem64, 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)) +"SF" |-> andMInt( extractMInt( Mem64, 0, 1), extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/andq_m64_imm8.k b/semantics/memoryInstructions/andq_m64_imm8.k index b6a7c05d6..f1ce252b8 100644 --- a/semantics/memoryInstructions/andq_m64_imm8.k +++ b/semantics/memoryInstructions/andq_m64_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ANDQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(andq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(andq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (andq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (andq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (andq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (andq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (andq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - andMInt( Mem64, mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), + andMInt( Mem64, mi(64, svalueMInt(Imm8))), MemOff, 64 ) @@ -27,15 +28,16 @@ module ANDQ-M64-IMM8 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem64, 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem64, 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem64, 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem64, 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( Mem64, mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( Mem64, mi(64, svalueMInt(Imm8))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( Mem64, 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> andMInt( extractMInt( Mem64, 0, 1), extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/andw_m16_imm16.k b/semantics/memoryInstructions/andw_m16_imm16.k index 8de6251f8..c752696e8 100644 --- a/semantics/memoryInstructions/andw_m16_imm16.k +++ b/semantics/memoryInstructions/andw_m16_imm16.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ANDW-M16-IMM16 imports X86-CONFIGURATION - context execinstr(andw:Opcode Imm16:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(andw:Opcode Imm16:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (andw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (andw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (andw Imm16, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm16) ==Int 16 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (andw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (andw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - andMInt( Mem16, handleImmediateWithSignExtend(Imm16, 16, 16)), + andMInt( Mem16, Imm16), MemOff, 16 ) @@ -27,15 +28,16 @@ module ANDW-M16-IMM16 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem16, 15, 16), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 15, 16)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem16, 14, 15), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 14, 15)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 13, 14), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 13, 14)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 12, 13), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 12, 13)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 11, 12), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 10, 11), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 10, 11)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 9, 10), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 9, 10)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 8, 9), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem16, 15, 16), extractMInt( Imm16, 15, 16)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem16, 14, 15), extractMInt( Imm16, 14, 15)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 13, 14), extractMInt( Imm16, 13, 14)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 12, 13), extractMInt( Imm16, 12, 13)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 11, 12), extractMInt( Imm16, 11, 12)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 10, 11), extractMInt( Imm16, 10, 11)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 9, 10), extractMInt( Imm16, 9, 10)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 8, 9), extractMInt( Imm16, 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( Mem16, handleImmediateWithSignExtend(Imm16, 16, 16)), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( Mem16, Imm16), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( Mem16, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)) +"SF" |-> andMInt( extractMInt( Mem16, 0, 1), extractMInt( Imm16, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/memoryInstructions/andw_m16_imm8.k b/semantics/memoryInstructions/andw_m16_imm8.k index 21ab10b69..7306f6154 100644 --- a/semantics/memoryInstructions/andw_m16_imm8.k +++ b/semantics/memoryInstructions/andw_m16_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ANDW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(andw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(andw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (andw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (andw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (andw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (andw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (andw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - andMInt( Mem16, mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), + andMInt( Mem16, mi(16, svalueMInt(Imm8))), MemOff, 16 ) @@ -27,15 +28,16 @@ module ANDW-M16-IMM8 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem16, 15, 16), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem16, 14, 15), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 13, 14), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 12, 13), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 11, 12), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 10, 11), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 9, 10), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 8, 9), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem16, 15, 16), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem16, 14, 15), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 13, 14), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 12, 13), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 11, 12), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 10, 11), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 9, 10), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 8, 9), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( Mem16, mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( Mem16, mi(16, svalueMInt(Imm8))), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( Mem16, 0, 1), extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> andMInt( extractMInt( Mem16, 0, 1), extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/blendpd_xmm_m128_imm8.k b/semantics/memoryInstructions/blendpd_xmm_m128_imm8.k index 2b4e3e551..7bfcbde9f 100644 --- a/semantics/memoryInstructions/blendpd_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/blendpd_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module BLENDPD-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(blendpd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(blendpd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (blendpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (blendpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (blendpd Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (blendpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (blendpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( Mem128, 0, 64) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 256) #else extractMInt( Mem128, 64, 128) #fi))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( Mem128, 0, 64) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 256) #else extractMInt( Mem128, 64, 128) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/blendps_xmm_m128_imm8.k b/semantics/memoryInstructions/blendps_xmm_m128_imm8.k index 18406df58..0b92507e1 100644 --- a/semantics/memoryInstructions/blendps_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/blendps_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module BLENDPS-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(blendps:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(blendps:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (blendps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (blendps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (blendps Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (blendps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (blendps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( Mem128, 0, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( Mem128, 32, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( Mem128, 64, 96) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( Mem128, 96, 128) #fi))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( Mem128, 0, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( Mem128, 32, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( Mem128, 64, 96) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( Mem128, 96, 128) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/btcl_m32_imm8.k b/semantics/memoryInstructions/btcl_m32_imm8.k index 9b1e17548..db820437a 100644 --- a/semantics/memoryInstructions/btcl_m32_imm8.k +++ b/semantics/memoryInstructions/btcl_m32_imm8.k @@ -4,28 +4,29 @@ requires "x86-configuration.k" module BTCL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(btcl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(btcl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (btcl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => - loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 3)))), 8) ~> + execinstr (btcl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => + loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 3)))), 8) ~> execinstr (btcl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btcl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btcl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - xorMInt( Mem8, shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7)))))), - addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 3)))), + xorMInt( Mem8, shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7)))))), + addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 3)))), 8 ) ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7))))), 7, 8) +"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7))))), 7, 8) "PF" |-> (undefMInt) @@ -36,4 +37,5 @@ module BTCL-M32-IMM8 "OF" |-> (undefMInt) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/btcq_m64_imm8.k b/semantics/memoryInstructions/btcq_m64_imm8.k index 0c16168e9..c8074422c 100644 --- a/semantics/memoryInstructions/btcq_m64_imm8.k +++ b/semantics/memoryInstructions/btcq_m64_imm8.k @@ -4,28 +4,29 @@ requires "x86-configuration.k" module BTCQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(btcq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(btcq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (btcq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => - loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 7)))), 8) ~> + execinstr (btcq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => + loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 7)))), 8) ~> execinstr (btcq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btcq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btcq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - xorMInt( Mem8, shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7)))))), - addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 7)))), + xorMInt( Mem8, shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7)))))), + addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 7)))), 8 ) ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7))))), 7, 8) +"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7))))), 7, 8) "PF" |-> (undefMInt) @@ -36,4 +37,5 @@ module BTCQ-M64-IMM8 "OF" |-> (undefMInt) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/btcw_m16_imm8.k b/semantics/memoryInstructions/btcw_m16_imm8.k index 83d7d4257..610a98bce 100644 --- a/semantics/memoryInstructions/btcw_m16_imm8.k +++ b/semantics/memoryInstructions/btcw_m16_imm8.k @@ -4,28 +4,29 @@ requires "x86-configuration.k" module BTCW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(btcw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(btcw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (btcw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => - loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 1)))), 8) ~> + execinstr (btcw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => + loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 1)))), 8) ~> execinstr (btcw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btcw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btcw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - xorMInt( Mem8, shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7)))))), - addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 1)))), + xorMInt( Mem8, shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7)))))), + addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 1)))), 8 ) ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7))))), 7, 8) +"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7))))), 7, 8) "PF" |-> (undefMInt) @@ -36,4 +37,5 @@ module BTCW-M16-IMM8 "OF" |-> (undefMInt) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/btl_m32_imm8.k b/semantics/memoryInstructions/btl_m32_imm8.k index 5bc2facb9..788990aaf 100644 --- a/semantics/memoryInstructions/btl_m32_imm8.k +++ b/semantics/memoryInstructions/btl_m32_imm8.k @@ -4,22 +4,23 @@ requires "x86-configuration.k" module BTL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(btl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(btl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (btl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => - loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 3)))), 8) ~> + execinstr (btl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => + loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 3)))), 8) ~> execinstr (btl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7))))), 7, 8) +"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7))))), 7, 8) "PF" |-> (undefMInt) @@ -30,4 +31,5 @@ module BTL-M32-IMM8 "OF" |-> (undefMInt) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/btq_m64_imm8.k b/semantics/memoryInstructions/btq_m64_imm8.k index aa5f03472..6e5a81d94 100644 --- a/semantics/memoryInstructions/btq_m64_imm8.k +++ b/semantics/memoryInstructions/btq_m64_imm8.k @@ -4,22 +4,23 @@ requires "x86-configuration.k" module BTQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(btq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(btq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (btq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => - loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 7)))), 8) ~> + execinstr (btq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => + loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 7)))), 8) ~> execinstr (btq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7))))), 7, 8) +"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7))))), 7, 8) "PF" |-> (undefMInt) @@ -30,4 +31,5 @@ module BTQ-M64-IMM8 "OF" |-> (undefMInt) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/btrl_m32_imm8.k b/semantics/memoryInstructions/btrl_m32_imm8.k index b83a0c4b7..4a0d298bd 100644 --- a/semantics/memoryInstructions/btrl_m32_imm8.k +++ b/semantics/memoryInstructions/btrl_m32_imm8.k @@ -4,28 +4,29 @@ requires "x86-configuration.k" module BTRL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(btrl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(btrl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (btrl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => - loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 3)))), 8) ~> + execinstr (btrl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => + loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 3)))), 8) ~> execinstr (btrl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btrl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btrl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - andMInt( Mem8, negMInt( shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7))))))), - addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 3)))), + andMInt( Mem8, negMInt( shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7))))))), + addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 3)))), 8 ) ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7))))), 7, 8) +"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7))))), 7, 8) "PF" |-> (undefMInt) @@ -36,4 +37,5 @@ module BTRL-M32-IMM8 "OF" |-> (undefMInt) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/btrq_m64_imm8.k b/semantics/memoryInstructions/btrq_m64_imm8.k index 28c7f669d..4bebaff18 100644 --- a/semantics/memoryInstructions/btrq_m64_imm8.k +++ b/semantics/memoryInstructions/btrq_m64_imm8.k @@ -4,28 +4,29 @@ requires "x86-configuration.k" module BTRQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(btrq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(btrq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (btrq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => - loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 7)))), 8) ~> + execinstr (btrq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => + loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 7)))), 8) ~> execinstr (btrq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btrq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btrq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - andMInt( Mem8, negMInt( shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7))))))), - addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 7)))), + andMInt( Mem8, negMInt( shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7))))))), + addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 7)))), 8 ) ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7))))), 7, 8) +"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7))))), 7, 8) "PF" |-> (undefMInt) @@ -36,4 +37,5 @@ module BTRQ-M64-IMM8 "OF" |-> (undefMInt) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/btrw_m16_imm8.k b/semantics/memoryInstructions/btrw_m16_imm8.k index 3b46b7ec3..35772e165 100644 --- a/semantics/memoryInstructions/btrw_m16_imm8.k +++ b/semantics/memoryInstructions/btrw_m16_imm8.k @@ -4,28 +4,29 @@ requires "x86-configuration.k" module BTRW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(btrw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(btrw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (btrw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => - loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 1)))), 8) ~> + execinstr (btrw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => + loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 1)))), 8) ~> execinstr (btrw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btrw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btrw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - andMInt( Mem8, negMInt( shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7))))))), - addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 1)))), + andMInt( Mem8, negMInt( shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7))))))), + addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 1)))), 8 ) ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7))))), 7, 8) +"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7))))), 7, 8) "PF" |-> (undefMInt) @@ -36,4 +37,5 @@ module BTRW-M16-IMM8 "OF" |-> (undefMInt) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/btsl_m32_imm8.k b/semantics/memoryInstructions/btsl_m32_imm8.k index f4456f003..e0589bc22 100644 --- a/semantics/memoryInstructions/btsl_m32_imm8.k +++ b/semantics/memoryInstructions/btsl_m32_imm8.k @@ -4,28 +4,29 @@ requires "x86-configuration.k" module BTSL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(btsl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(btsl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (btsl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => - loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 3)))), 8) ~> + execinstr (btsl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => + loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 3)))), 8) ~> execinstr (btsl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btsl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btsl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - orMInt( Mem8, shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7)))))), - addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 3)))), + orMInt( Mem8, shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7)))))), + addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 3)))), 8 ) ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7))))), 7, 8) +"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7))))), 7, 8) "PF" |-> (undefMInt) @@ -36,4 +37,5 @@ module BTSL-M32-IMM8 "OF" |-> (undefMInt) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/btsq_m64_imm8.k b/semantics/memoryInstructions/btsq_m64_imm8.k index 8fc078d34..cb01a0318 100644 --- a/semantics/memoryInstructions/btsq_m64_imm8.k +++ b/semantics/memoryInstructions/btsq_m64_imm8.k @@ -4,28 +4,29 @@ requires "x86-configuration.k" module BTSQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(btsq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(btsq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (btsq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => - loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 7)))), 8) ~> + execinstr (btsq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => + loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 7)))), 8) ~> execinstr (btsq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btsq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btsq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - orMInt( Mem8, shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7)))))), - addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 7)))), + orMInt( Mem8, shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7)))))), + addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 7)))), 8 ) ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7))))), 7, 8) +"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7))))), 7, 8) "PF" |-> (undefMInt) @@ -36,4 +37,5 @@ module BTSQ-M64-IMM8 "OF" |-> (undefMInt) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/btsw_m16_imm8.k b/semantics/memoryInstructions/btsw_m16_imm8.k index 47add1981..f8ba9e111 100644 --- a/semantics/memoryInstructions/btsw_m16_imm8.k +++ b/semantics/memoryInstructions/btsw_m16_imm8.k @@ -4,28 +4,29 @@ requires "x86-configuration.k" module BTSW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(btsw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(btsw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (btsw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => - loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 1)))), 8) ~> + execinstr (btsw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => + loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 1)))), 8) ~> execinstr (btsw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btsw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btsw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - orMInt( Mem8, shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7)))))), - addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 1)))), + orMInt( Mem8, shiftLeftMInt( mi(8, 1), uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7)))))), + addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 1)))), 8 ) ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7))))), 7, 8) +"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7))))), 7, 8) "PF" |-> (undefMInt) @@ -36,4 +37,5 @@ module BTSW-M16-IMM8 "OF" |-> (undefMInt) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/btw_m16_imm8.k b/semantics/memoryInstructions/btw_m16_imm8.k index 7323d7516..c870485a3 100644 --- a/semantics/memoryInstructions/btw_m16_imm8.k +++ b/semantics/memoryInstructions/btw_m16_imm8.k @@ -4,22 +4,23 @@ requires "x86-configuration.k" module BTW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(btw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(btw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (btw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => - loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 5), mi(5, 1)))), 8) ~> + execinstr (btw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => + loadFromMemory( addMInt( MemOff, concatenateMInt( mi(59, 0), andMInt( extractMInt( Imm8, 0, 5), mi(5, 1)))), 8) ~> execinstr (btw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (btw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8), mi(3, 7))))), 7, 8) +"CF" |-> extractMInt( lshrMInt( Mem8, uvalueMInt(concatenateMInt( mi(5, 0), andMInt( extractMInt( Imm8, 5, 8), mi(3, 7))))), 7, 8) "PF" |-> (undefMInt) @@ -30,4 +31,5 @@ module BTW-M16-IMM8 "OF" |-> (undefMInt) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/cmpb_m8_imm8.k b/semantics/memoryInstructions/cmpb_m8_imm8.k index 7cd42a343..09fc6df54 100644 --- a/semantics/memoryInstructions/cmpb_m8_imm8.k +++ b/semantics/memoryInstructions/cmpb_m8_imm8.k @@ -4,32 +4,34 @@ requires "x86-configuration.k" module CMPB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(cmpb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(cmpb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (cmpb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (cmpb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (cmpb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (cmpb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (cmpb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem8, 3, 4)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem8, 3, 4)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem8, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem8, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/cmpl_m32_imm32.k b/semantics/memoryInstructions/cmpl_m32_imm32.k index a52295de7..309f2eb41 100644 --- a/semantics/memoryInstructions/cmpl_m32_imm32.k +++ b/semantics/memoryInstructions/cmpl_m32_imm32.k @@ -4,32 +4,34 @@ requires "x86-configuration.k" module CMPL-M32-IMM32 imports X86-CONFIGURATION - context execinstr(cmpl:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(cmpl:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (cmpl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (cmpl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (cmpl Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (cmpl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (cmpl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/cmpl_m32_imm8.k b/semantics/memoryInstructions/cmpl_m32_imm8.k index ad19aac8c..8541f59b0 100644 --- a/semantics/memoryInstructions/cmpl_m32_imm8.k +++ b/semantics/memoryInstructions/cmpl_m32_imm8.k @@ -4,32 +4,34 @@ requires "x86-configuration.k" module CMPL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(cmpl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(cmpl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (cmpl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (cmpl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (cmpl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (cmpl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (cmpl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/cmppd_xmm_m128_imm8.k b/semantics/memoryInstructions/cmppd_xmm_m128_imm8.k index bffc625cb..29759e606 100644 --- a/semantics/memoryInstructions/cmppd_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/cmppd_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module CMPPD-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(cmppd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(cmppd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (cmppd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (cmppd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (cmppd Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (cmppd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (cmppd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( Mem128, 0, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( Mem128, 64, 128), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( Mem128, 0, 64), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( Mem128, 64, 128), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/cmpps_xmm_m128_imm8.k b/semantics/memoryInstructions/cmpps_xmm_m128_imm8.k index d80631593..80103aeb9 100644 --- a/semantics/memoryInstructions/cmpps_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/cmpps_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module CMPPS-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(cmpps:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(cmpps:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (cmpps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (cmpps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (cmpps Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (cmpps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (cmpps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/cmpq_m64_imm32.k b/semantics/memoryInstructions/cmpq_m64_imm32.k index 7b4346fc7..a68829089 100644 --- a/semantics/memoryInstructions/cmpq_m64_imm32.k +++ b/semantics/memoryInstructions/cmpq_m64_imm32.k @@ -4,32 +4,34 @@ requires "x86-configuration.k" module CMPQ-M64-IMM32 imports X86-CONFIGURATION - context execinstr(cmpq:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(cmpq:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (cmpq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (cmpq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (cmpq Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (cmpq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (cmpq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/cmpq_m64_imm8.k b/semantics/memoryInstructions/cmpq_m64_imm8.k index 6e800adb5..0c49b2505 100644 --- a/semantics/memoryInstructions/cmpq_m64_imm8.k +++ b/semantics/memoryInstructions/cmpq_m64_imm8.k @@ -4,32 +4,34 @@ requires "x86-configuration.k" module CMPQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(cmpq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(cmpq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (cmpq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (cmpq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (cmpq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (cmpq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (cmpq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/cmpsd_xmm_m64_imm8.k b/semantics/memoryInstructions/cmpsd_xmm_m64_imm8.k index f30bf9a63..1cf993429 100644 --- a/semantics/memoryInstructions/cmpsd_xmm_m64_imm8.k +++ b/semantics/memoryInstructions/cmpsd_xmm_m64_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module CMPSD-XMM-M64-IMM8 imports X86-CONFIGURATION - context execinstr(cmpsd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(cmpsd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (cmpsd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (cmpsd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (cmpsd Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (cmpsd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (cmpsd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 192), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), Mem64, handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi)) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 192), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), Mem64, Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/cmpss_xmm_m32_imm8.k b/semantics/memoryInstructions/cmpss_xmm_m32_imm8.k index ef8caec79..028025abf 100644 --- a/semantics/memoryInstructions/cmpss_xmm_m32_imm8.k +++ b/semantics/memoryInstructions/cmpss_xmm_m32_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module CMPSS-XMM-M32-IMM8 imports X86-CONFIGURATION - context execinstr(cmpss:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(cmpss:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (cmpss:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (cmpss:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (cmpss Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (cmpss:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (cmpss:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 224), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), Mem32, handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi)) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 224), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), Mem32, Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/cmpw_m16_imm16.k b/semantics/memoryInstructions/cmpw_m16_imm16.k index d6dc438b0..a0e749569 100644 --- a/semantics/memoryInstructions/cmpw_m16_imm16.k +++ b/semantics/memoryInstructions/cmpw_m16_imm16.k @@ -4,32 +4,34 @@ requires "x86-configuration.k" module CMPW-M16-IMM16 imports X86-CONFIGURATION - context execinstr(cmpw:Opcode Imm16:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(cmpw:Opcode Imm16:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (cmpw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (cmpw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (cmpw Imm16, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm16) ==Int 16 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (cmpw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (cmpw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm16, 11, 12), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/memoryInstructions/cmpw_m16_imm8.k b/semantics/memoryInstructions/cmpw_m16_imm8.k index 4290ec3f9..a75df6a77 100644 --- a/semantics/memoryInstructions/cmpw_m16_imm8.k +++ b/semantics/memoryInstructions/cmpw_m16_imm8.k @@ -4,32 +4,34 @@ requires "x86-configuration.k" module CMPW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(cmpw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(cmpw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (cmpw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (cmpw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (cmpw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (cmpw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (cmpw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => . ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/dppd_xmm_m128_imm8.k b/semantics/memoryInstructions/dppd_xmm_m128_imm8.k index 7be89118c..97cb12f44 100644 --- a/semantics/memoryInstructions/dppd_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/dppd_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module DPPD-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(dppd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(dppd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (dppd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (dppd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (dppd Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (dppd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (dppd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( Mem128, 64, 128)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( Mem128, 0, 64)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( Mem128, 64, 128)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( Mem128, 0, 64)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( Mem128, 64, 128)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( Mem128, 0, 64)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( Mem128, 64, 128)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( Mem128, 0, 64)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/dpps_xmm_m128_imm8.k b/semantics/memoryInstructions/dpps_xmm_m128_imm8.k index 98bc51dbb..adb5c4c7e 100644 --- a/semantics/memoryInstructions/dpps_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/dpps_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module DPPS-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(dpps:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(dpps:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (dpps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (dpps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (dpps Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (dpps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (dpps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/extractps_m32_xmm_imm8.k b/semantics/memoryInstructions/extractps_m32_xmm_imm8.k index 0a8278596..699f00c6e 100644 --- a/semantics/memoryInstructions/extractps_m32_xmm_imm8.k +++ b/semantics/memoryInstructions/extractps_m32_xmm_imm8.k @@ -4,24 +4,26 @@ requires "x86-configuration.k" module EXTRACTPS-M32-XMM-IMM8 imports X86-CONFIGURATION - context execinstr(extractps:Opcode Imm8:Imm, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(extractps:Opcode Imm8:MInt, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (extractps:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (extractps:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (extractps Imm8, R2:Xmm, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (extractps:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (extractps:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128), + extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128), MemOff, 32 ) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/imull_r32_m32_imm32.k b/semantics/memoryInstructions/imull_r32_m32_imm32.k index 294774e3b..867105d6c 100644 --- a/semantics/memoryInstructions/imull_r32_m32_imm32.k +++ b/semantics/memoryInstructions/imull_r32_m32_imm32.k @@ -4,24 +4,25 @@ requires "x86-configuration.k" module IMULL-R32-M32-IMM32 imports X86-CONFIGURATION - context execinstr(imull:Opcode Imm32:Imm, HOLE:Mem, R3:R32, .Operands) [result(MemOffset)] + context execinstr(imull:Opcode Imm32:MInt, HOLE:Mem, R3:R32, .Operands) [result(MemOffset)] rule - execinstr (imull:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, R3:R32, .Operands) => + execinstr (imull:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, R3:R32, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (imull Imm32, memOffset( MemOff), R3, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (imull:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, R3:R32, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (imull:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, R3:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), 32, 64)) +convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(Imm32))), 32, 64)) -"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(Imm32))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(Imm32))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) "PF" |-> (undefMInt) @@ -31,7 +32,8 @@ convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( mulMInt( mi(64, s "SF" |-> (undefMInt) -"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(Imm32))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(Imm32))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/imull_r32_m32_imm8.k b/semantics/memoryInstructions/imull_r32_m32_imm8.k index d20b7193e..555aae15b 100644 --- a/semantics/memoryInstructions/imull_r32_m32_imm8.k +++ b/semantics/memoryInstructions/imull_r32_m32_imm8.k @@ -4,24 +4,25 @@ requires "x86-configuration.k" module IMULL-R32-M32-IMM8 imports X86-CONFIGURATION - context execinstr(imull:Opcode Imm8:Imm, HOLE:Mem, R3:R32, .Operands) [result(MemOffset)] + context execinstr(imull:Opcode Imm8:MInt, HOLE:Mem, R3:R32, .Operands) [result(MemOffset)] rule - execinstr (imull:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:R32, .Operands) => + execinstr (imull:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:R32, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (imull Imm8, memOffset( MemOff), R3, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (imull:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:R32, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (imull:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 32, 64)) +convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(Imm8))), 32, 64)) -"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(Imm8))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(Imm8))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) "PF" |-> (undefMInt) @@ -31,7 +32,8 @@ convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), extractMInt( mulMInt( mi(64, s "SF" |-> (undefMInt) -"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(Imm8))), mi(64, svalueMInt(extractMInt( mulMInt( mi(64, svalueMInt(Mem32)), mi(64, svalueMInt(Imm8))), 32, 64))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/imulq_r64_m64_imm32.k b/semantics/memoryInstructions/imulq_r64_m64_imm32.k index 85f0420d1..f21476843 100644 --- a/semantics/memoryInstructions/imulq_r64_m64_imm32.k +++ b/semantics/memoryInstructions/imulq_r64_m64_imm32.k @@ -4,24 +4,25 @@ requires "x86-configuration.k" module IMULQ-R64-M64-IMM32 imports X86-CONFIGURATION - context execinstr(imulq:Opcode Imm32:Imm, HOLE:Mem, R3:R64, .Operands) [result(MemOffset)] + context execinstr(imulq:Opcode Imm32:MInt, HOLE:Mem, R3:R64, .Operands) [result(MemOffset)] rule - execinstr (imulq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, R3:R64, .Operands) => + execinstr (imulq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, R3:R64, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (imulq Imm32, memOffset( MemOff), R3, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (imulq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, R3:R64, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (imulq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, R3:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> extractMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), 64, 128) +convToRegKeys(R3) |-> extractMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(Imm32))), 64, 128) -"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(Imm32))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(Imm32))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) "PF" |-> (undefMInt) @@ -31,7 +32,8 @@ convToRegKeys(R3) |-> extractMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, "SF" |-> (undefMInt) -"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(Imm32))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(Imm32))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/imulq_r64_m64_imm8.k b/semantics/memoryInstructions/imulq_r64_m64_imm8.k index bb77f0b52..8877ae2d1 100644 --- a/semantics/memoryInstructions/imulq_r64_m64_imm8.k +++ b/semantics/memoryInstructions/imulq_r64_m64_imm8.k @@ -4,24 +4,25 @@ requires "x86-configuration.k" module IMULQ-R64-M64-IMM8 imports X86-CONFIGURATION - context execinstr(imulq:Opcode Imm8:Imm, HOLE:Mem, R3:R64, .Operands) [result(MemOffset)] + context execinstr(imulq:Opcode Imm8:MInt, HOLE:Mem, R3:R64, .Operands) [result(MemOffset)] rule - execinstr (imulq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:R64, .Operands) => + execinstr (imulq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:R64, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (imulq Imm8, memOffset( MemOff), R3, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (imulq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:R64, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (imulq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> extractMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 64, 128) +convToRegKeys(R3) |-> extractMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(Imm8))), 64, 128) -"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(Imm8))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(Imm8))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) "PF" |-> (undefMInt) @@ -31,7 +32,8 @@ convToRegKeys(R3) |-> extractMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, "SF" |-> (undefMInt) -"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(Imm8))), mi(128, svalueMInt(extractMInt( mulMInt( mi(128, svalueMInt(Mem64)), mi(128, svalueMInt(Imm8))), 64, 128))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/imulw_r16_m16_imm16.k b/semantics/memoryInstructions/imulw_r16_m16_imm16.k index c129cfdfa..d0442984c 100644 --- a/semantics/memoryInstructions/imulw_r16_m16_imm16.k +++ b/semantics/memoryInstructions/imulw_r16_m16_imm16.k @@ -4,24 +4,25 @@ requires "x86-configuration.k" module IMULW-R16-M16-IMM16 imports X86-CONFIGURATION - context execinstr(imulw:Opcode Imm16:Imm, HOLE:Mem, R3:R16, .Operands) [result(MemOffset)] + context execinstr(imulw:Opcode Imm16:MInt, HOLE:Mem, R3:R16, .Operands) [result(MemOffset)] rule - execinstr (imulw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, R3:R16, .Operands) => + execinstr (imulw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, R3:R16, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (imulw Imm16, memOffset( MemOff), R3, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm16) ==Int 16 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (imulw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, R3:R16, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (imulw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, R3:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 48), extractMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm16, 16, 16)))), 16, 32)) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 48), extractMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(Imm16))), 16, 32)) -"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm16, 16, 16)))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm16, 16, 16)))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(Imm16))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(Imm16))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) "PF" |-> (undefMInt) @@ -31,7 +32,8 @@ convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0 "SF" |-> (undefMInt) -"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm16, 16, 16)))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm16, 16, 16)))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(Imm16))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(Imm16))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/memoryInstructions/imulw_r16_m16_imm8.k b/semantics/memoryInstructions/imulw_r16_m16_imm8.k index b9081447b..991155d3d 100644 --- a/semantics/memoryInstructions/imulw_r16_m16_imm8.k +++ b/semantics/memoryInstructions/imulw_r16_m16_imm8.k @@ -4,24 +4,25 @@ requires "x86-configuration.k" module IMULW-R16-M16-IMM8 imports X86-CONFIGURATION - context execinstr(imulw:Opcode Imm8:Imm, HOLE:Mem, R3:R16, .Operands) [result(MemOffset)] + context execinstr(imulw:Opcode Imm8:MInt, HOLE:Mem, R3:R16, .Operands) [result(MemOffset)] rule - execinstr (imulw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:R16, .Operands) => + execinstr (imulw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:R16, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (imulw Imm8, memOffset( MemOff), R3, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (imulw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:R16, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (imulw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:R16, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 48), extractMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 16, 32)) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 48), extractMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(Imm8))), 16, 32)) -"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(Imm8))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(Imm8))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) "PF" |-> (undefMInt) @@ -31,7 +32,8 @@ convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0 "SF" |-> (undefMInt) -"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt (notBool eqMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(Imm8))), mi(32, svalueMInt(extractMInt( mulMInt( mi(32, svalueMInt(Mem16)), mi(32, svalueMInt(Imm8))), 16, 32))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/insertps_xmm_m32_imm8.k b/semantics/memoryInstructions/insertps_xmm_m32_imm8.k index f6861f6a5..a8f37f333 100644 --- a/semantics/memoryInstructions/insertps_xmm_m32_imm8.k +++ b/semantics/memoryInstructions/insertps_xmm_m32_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module INSERTPS-XMM-M32-IMM8 imports X86-CONFIGURATION - context execinstr(insertps:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(insertps:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (insertps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (insertps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (insertps Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (insertps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (insertps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else Mem32 #fi) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then Mem32 #else extractMInt( getParentValue(R3, RSMap), 160, 192) #fi) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then Mem32 #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then Mem32 #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else Mem32 #fi) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then Mem32 #else extractMInt( getParentValue(R3, RSMap), 160, 192) #fi) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then Mem32 #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then Mem32 #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/movb_m8_imm8.k b/semantics/memoryInstructions/movb_m8_imm8.k index c20f4a528..3117cf52f 100644 --- a/semantics/memoryInstructions/movb_m8_imm8.k +++ b/semantics/memoryInstructions/movb_m8_imm8.k @@ -4,17 +4,18 @@ requires "x86-configuration.k" module MOVB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(movb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(movb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (movb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (movb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, MemOff, 8 ) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/movl_m32_imm32.k b/semantics/memoryInstructions/movl_m32_imm32.k index b92e8ce16..617a1b1b0 100644 --- a/semantics/memoryInstructions/movl_m32_imm32.k +++ b/semantics/memoryInstructions/movl_m32_imm32.k @@ -4,17 +4,18 @@ requires "x86-configuration.k" module MOVL-M32-IMM32 imports X86-CONFIGURATION - context execinstr(movl:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(movl:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (movl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (movl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - handleImmediateWithSignExtend(Imm32, 32, 32), + Imm32, MemOff, 32 ) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/movq_m64_imm32.k b/semantics/memoryInstructions/movq_m64_imm32.k index a7327cfbe..3cfb363fa 100644 --- a/semantics/memoryInstructions/movq_m64_imm32.k +++ b/semantics/memoryInstructions/movq_m64_imm32.k @@ -4,17 +4,18 @@ requires "x86-configuration.k" module MOVQ-M64-IMM32 imports X86-CONFIGURATION - context execinstr(movq:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(movq:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (movq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (movq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), + mi(64, svalueMInt(Imm32)), MemOff, 64 ) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/movw_m16_imm16.k b/semantics/memoryInstructions/movw_m16_imm16.k index b27741cec..ef60688ab 100644 --- a/semantics/memoryInstructions/movw_m16_imm16.k +++ b/semantics/memoryInstructions/movw_m16_imm16.k @@ -4,17 +4,18 @@ requires "x86-configuration.k" module MOVW-M16-IMM16 imports X86-CONFIGURATION - context execinstr(movw:Opcode Imm16:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(movw:Opcode Imm16:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (movw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (movw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - handleImmediateWithSignExtend(Imm16, 16, 16), + Imm16, MemOff, 16 ) ... RSMap:Map + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/memoryInstructions/mpsadbw_xmm_m128_imm8.k b/semantics/memoryInstructions/mpsadbw_xmm_m128_imm8.k index 371a5ad43..c9368664f 100644 --- a/semantics/memoryInstructions/mpsadbw_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/mpsadbw_xmm_m128_imm8.k @@ -15,43 +15,44 @@ module MPSADBW-XMM-M128-IMM8 rule memLoadValue(MemVal:MInt):MemLoadValue ~> - execinstr (mpsadbw Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (mpsadbw Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => execinstr (mpsadbw selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 7 , 0 ), + extractMInt(Imm8, 6, 8), 7 , 0 ), selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 15, 8 ), + extractMInt(Imm8, 6, 8), 15, 8 ), selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 23, 16), + extractMInt(Imm8, 6, 8), 23, 16), selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 31, 24), + extractMInt(Imm8, 6, 8), 31, 24), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 7 , 0), + extractMInt(Imm8, 5, 6), 7 , 0), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 15, 8), + extractMInt(Imm8, 5, 6), 15, 8), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 23, 16), + extractMInt(Imm8, 5, 6), 23, 16), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 31, 24), + extractMInt(Imm8, 5, 6), 31, 24), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 39, 32), + extractMInt(Imm8, 5, 6), 39, 32), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 47, 40), + extractMInt(Imm8, 5, 6), 47, 40), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 55, 48), + extractMInt(Imm8, 5, 6), 55, 48), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 63, 56), + extractMInt(Imm8, 5, 6), 63, 56), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 71, 64), + extractMInt(Imm8, 5, 6), 71, 64), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 79, 72), + extractMInt(Imm8, 5, 6), 79, 72), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 87, 80), + extractMInt(Imm8, 5, 6), 87, 80), R3:Xmm, .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (mpsadbw diff --git a/semantics/memoryInstructions/orb_m8_imm8.k b/semantics/memoryInstructions/orb_m8_imm8.k index b4ca5efcd..5ba532294 100644 --- a/semantics/memoryInstructions/orb_m8_imm8.k +++ b/semantics/memoryInstructions/orb_m8_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ORB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(orb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(orb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (orb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (orb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (orb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (orb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (orb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - orMInt( Mem8, handleImmediateWithSignExtend(Imm8, 8, 8)), + orMInt( Mem8, Imm8), MemOff, 8 ) @@ -27,15 +28,16 @@ module ORB-M8-IMM8 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( Mem8, 7, 8), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( Mem8, 6, 7), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem8, 5, 6), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem8, 4, 5), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem8, 3, 4), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem8, 2, 3), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem8, 1, 2), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem8, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( Mem8, 7, 8), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( Mem8, 6, 7), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem8, 5, 6), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem8, 4, 5), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem8, 3, 4), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem8, 2, 3), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem8, 1, 2), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem8, 0, 1), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( Mem8, handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( Mem8, Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( Mem8, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> orMInt( extractMInt( Mem8, 0, 1), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/orl_m32_imm32.k b/semantics/memoryInstructions/orl_m32_imm32.k index ea98dc7d6..3ecaaea14 100644 --- a/semantics/memoryInstructions/orl_m32_imm32.k +++ b/semantics/memoryInstructions/orl_m32_imm32.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ORL-M32-IMM32 imports X86-CONFIGURATION - context execinstr(orl:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(orl:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (orl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (orl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (orl Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (orl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (orl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - orMInt( Mem32, handleImmediateWithSignExtend(Imm32, 32, 32)), + orMInt( Mem32, Imm32), MemOff, 32 ) @@ -27,15 +28,16 @@ module ORL-M32-IMM32 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( Mem32, 31, 32), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( Mem32, 30, 31), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 29, 30), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 28, 29), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 27, 28), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 26, 27), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 25, 26), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 24, 25), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( Mem32, 31, 32), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( Mem32, 30, 31), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 29, 30), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 28, 29), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 27, 28), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 26, 27), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 25, 26), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 24, 25), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( Mem32, handleImmediateWithSignExtend(Imm32, 32, 32)), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( Mem32, Imm32), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( Mem32, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)) +"SF" |-> orMInt( extractMInt( Mem32, 0, 1), extractMInt( Imm32, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/orl_m32_imm8.k b/semantics/memoryInstructions/orl_m32_imm8.k index 04524a8c5..6340e5e0a 100644 --- a/semantics/memoryInstructions/orl_m32_imm8.k +++ b/semantics/memoryInstructions/orl_m32_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ORL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(orl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(orl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (orl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (orl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (orl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (orl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (orl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - orMInt( Mem32, mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), + orMInt( Mem32, mi(32, svalueMInt(Imm8))), MemOff, 32 ) @@ -27,15 +28,16 @@ module ORL-M32-IMM8 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( Mem32, 31, 32), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( Mem32, 30, 31), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 29, 30), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 28, 29), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 27, 28), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 26, 27), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 25, 26), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 24, 25), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( Mem32, 31, 32), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( Mem32, 30, 31), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 29, 30), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 28, 29), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 27, 28), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 26, 27), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 25, 26), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem32, 24, 25), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( Mem32, mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( Mem32, mi(32, svalueMInt(Imm8))), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( Mem32, 0, 1), extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> orMInt( extractMInt( Mem32, 0, 1), extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/orq_m64_imm32.k b/semantics/memoryInstructions/orq_m64_imm32.k index eccfb584b..7bd639dc6 100644 --- a/semantics/memoryInstructions/orq_m64_imm32.k +++ b/semantics/memoryInstructions/orq_m64_imm32.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ORQ-M64-IMM32 imports X86-CONFIGURATION - context execinstr(orq:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(orq:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (orq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (orq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (orq Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (orq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (orq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - orMInt( Mem64, mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), + orMInt( Mem64, mi(64, svalueMInt(Imm32))), MemOff, 64 ) @@ -27,15 +28,16 @@ module ORQ-M64-IMM32 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( Mem64, 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( Mem64, 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( Mem64, 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( Mem64, 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( Mem64, mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( Mem64, mi(64, svalueMInt(Imm32))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( Mem64, 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)) +"SF" |-> orMInt( extractMInt( Mem64, 0, 1), extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/orq_m64_imm8.k b/semantics/memoryInstructions/orq_m64_imm8.k index af93c42cb..0b8480302 100644 --- a/semantics/memoryInstructions/orq_m64_imm8.k +++ b/semantics/memoryInstructions/orq_m64_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ORQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(orq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(orq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (orq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (orq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (orq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (orq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (orq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - orMInt( Mem64, mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), + orMInt( Mem64, mi(64, svalueMInt(Imm8))), MemOff, 64 ) @@ -27,15 +28,16 @@ module ORQ-M64-IMM8 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( Mem64, 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( Mem64, 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( Mem64, 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( Mem64, 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem64, 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( Mem64, mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( Mem64, mi(64, svalueMInt(Imm8))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( Mem64, 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> orMInt( extractMInt( Mem64, 0, 1), extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/orw_m16_imm16.k b/semantics/memoryInstructions/orw_m16_imm16.k index 4a1e8e32c..4968ddc8f 100644 --- a/semantics/memoryInstructions/orw_m16_imm16.k +++ b/semantics/memoryInstructions/orw_m16_imm16.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ORW-M16-IMM16 imports X86-CONFIGURATION - context execinstr(orw:Opcode Imm16:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(orw:Opcode Imm16:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (orw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (orw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (orw Imm16, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm16) ==Int 16 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (orw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (orw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - orMInt( Mem16, handleImmediateWithSignExtend(Imm16, 16, 16)), + orMInt( Mem16, Imm16), MemOff, 16 ) @@ -27,15 +28,16 @@ module ORW-M16-IMM16 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( Mem16, 15, 16), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 15, 16)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( Mem16, 14, 15), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 14, 15)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 13, 14), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 13, 14)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 12, 13), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 12, 13)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 11, 12), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 10, 11), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 10, 11)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 9, 10), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 9, 10)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 8, 9), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( Mem16, 15, 16), extractMInt( Imm16, 15, 16)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( Mem16, 14, 15), extractMInt( Imm16, 14, 15)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 13, 14), extractMInt( Imm16, 13, 14)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 12, 13), extractMInt( Imm16, 12, 13)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 11, 12), extractMInt( Imm16, 11, 12)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 10, 11), extractMInt( Imm16, 10, 11)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 9, 10), extractMInt( Imm16, 9, 10)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 8, 9), extractMInt( Imm16, 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( Mem16, handleImmediateWithSignExtend(Imm16, 16, 16)), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( Mem16, Imm16), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( Mem16, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)) +"SF" |-> orMInt( extractMInt( Mem16, 0, 1), extractMInt( Imm16, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/memoryInstructions/orw_m16_imm8.k b/semantics/memoryInstructions/orw_m16_imm8.k index 3c5ace79a..0bfc5cc92 100644 --- a/semantics/memoryInstructions/orw_m16_imm8.k +++ b/semantics/memoryInstructions/orw_m16_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ORW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(orw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(orw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (orw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (orw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (orw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (orw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (orw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - orMInt( Mem16, mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), + orMInt( Mem16, mi(16, svalueMInt(Imm8))), MemOff, 16 ) @@ -27,15 +28,16 @@ module ORW-M16-IMM8 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( Mem16, 15, 16), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( Mem16, 14, 15), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 13, 14), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 12, 13), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 11, 12), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 10, 11), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 9, 10), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 8, 9), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( orMInt( extractMInt( Mem16, 15, 16), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( orMInt( extractMInt( Mem16, 14, 15), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 13, 14), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 12, 13), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 11, 12), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 10, 11), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 9, 10), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( orMInt( extractMInt( Mem16, 8, 9), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( orMInt( Mem16, mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( orMInt( Mem16, mi(16, svalueMInt(Imm8))), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> orMInt( extractMInt( Mem16, 0, 1), extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> orMInt( extractMInt( Mem16, 0, 1), extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/palignr_xmm_m128_imm8.k b/semantics/memoryInstructions/palignr_xmm_m128_imm8.k index c7c367b4d..4a180da4e 100644 --- a/semantics/memoryInstructions/palignr_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/palignr_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module PALIGNR-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(palignr:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(palignr:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (palignr:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (palignr:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (palignr Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (palignr:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (palignr:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), Mem128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), uvalueMInt(mi(256, 3))))), 128, 256)) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), Mem128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), Imm8), uvalueMInt(mi(256, 3))))), 128, 256)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/pblendw_xmm_m128_imm8.k b/semantics/memoryInstructions/pblendw_xmm_m128_imm8.k index 43af6e40d..aa6593bf9 100644 --- a/semantics/memoryInstructions/pblendw_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/pblendw_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module PBLENDW-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(pblendw:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(pblendw:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (pblendw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (pblendw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (pblendw Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (pblendw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (pblendw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 144) #else extractMInt( Mem128, 0, 16) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 144, 160) #else extractMInt( Mem128, 16, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 176) #else extractMInt( Mem128, 32, 48) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 176, 192) #else extractMInt( Mem128, 48, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 208) #else extractMInt( Mem128, 64, 80) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 208, 224) #else extractMInt( Mem128, 80, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 240) #else extractMInt( Mem128, 96, 112) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 240, 256) #else extractMInt( Mem128, 112, 128) #fi))))))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 144) #else extractMInt( Mem128, 0, 16) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 144, 160) #else extractMInt( Mem128, 16, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 176) #else extractMInt( Mem128, 32, 48) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 176, 192) #else extractMInt( Mem128, 48, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 208) #else extractMInt( Mem128, 64, 80) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 208, 224) #else extractMInt( Mem128, 80, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 240) #else extractMInt( Mem128, 96, 112) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 240, 256) #else extractMInt( Mem128, 112, 128) #fi))))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/pclmulqdq_xmm_m128_imm8.k b/semantics/memoryInstructions/pclmulqdq_xmm_m128_imm8.k index 99509379b..d7e6dd713 100644 --- a/semantics/memoryInstructions/pclmulqdq_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/pclmulqdq_xmm_m128_imm8.k @@ -59,15 +59,14 @@ module PCLMULQDQ-XMM-M128-IMM8 */ rule memLoadValue(MemVal:MInt):MemLoadValue ~> - execinstr (pclmulqdq Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (pclmulqdq Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => execinstr(pclmulqdq - selectSlice(getRegisterValue(R3, RSMap), handleImmediateWithSignExtend(Imm8, - 8, 8), 7, 64, 0), - selectSlice(MemVal, handleImmediateWithSignExtend(Imm8, - 8, 8), 3, 64, 0), R3 + selectSlice(getRegisterValue(R3, RSMap), Imm8, 7, 64, 0), + selectSlice(MemVal, Imm8, 3, 64, 0), R3 , .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (pclmulqdq TEMP1:MInt, TEMP2:MInt, R3:Xmm, .Operands) => diff --git a/semantics/memoryInstructions/pcmpestri_xmm_m128_imm8.k b/semantics/memoryInstructions/pcmpestri_xmm_m128_imm8.k index 61a510c17..45b1025e5 100644 --- a/semantics/memoryInstructions/pcmpestri_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/pcmpestri_xmm_m128_imm8.k @@ -4,27 +4,28 @@ requires "x86-configuration.k" module PCMPESTRI-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(pcmpestri:Opcode Imm8:Imm, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] + context execinstr(pcmpestri:Opcode Imm8:MInt, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] rule - execinstr (pcmpestri:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => + execinstr (pcmpestri:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (pcmpestri Imm8, memOffset( MemOff), Xmm1, .Operands) ... - + requires bitwidthMInt(Imm8) ==Int 8 // Find Limit Index rule memLoadValue(Mem128:MInt):MemLoadValue ~> - execinstr (pcmpestri Imm8:Imm, memOffset( MemOff), Xmm1:Xmm, .Operands) => + execinstr (pcmpestri Imm8:MInt, memOffset( MemOff), Xmm1:Xmm, .Operands) => execinstr (pcmpestri - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, Mem128, getRegisterValue(Xmm1, RSMap), - findLimitIndexE(Mem128, getRegisterValue(%rdx, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexE(Mem128, getRegisterValue(%rdx, RSMap), Imm8), + findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // Find data size and interpretation rule diff --git a/semantics/memoryInstructions/pcmpestrm_xmm_m128_imm8.k b/semantics/memoryInstructions/pcmpestrm_xmm_m128_imm8.k index 958a11c68..767460a26 100644 --- a/semantics/memoryInstructions/pcmpestrm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/pcmpestrm_xmm_m128_imm8.k @@ -4,26 +4,27 @@ requires "x86-configuration.k" module PCMPESTRM-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(pcmpestrm:Opcode Imm8:Imm, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] + context execinstr(pcmpestrm:Opcode Imm8:MInt, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] rule - execinstr (pcmpestrm:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => + execinstr (pcmpestrm:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (pcmpestrm Imm8, memOffset( MemOff), Xmm1, .Operands) ... - + requires bitwidthMInt(Imm8) ==Int 8 // Find Limit Index rule memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (pcmpestrm Imm8, memOffset( MemOff), Xmm1, .Operands) => execinstr (pcmpestrm - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, Mem128, getRegisterValue(Xmm1, RSMap), - findLimitIndexE(Mem128, getRegisterValue(%rdx, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexE(Mem128, getRegisterValue(%rdx, RSMap), Imm8), + findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // Find data size and interpretation rule diff --git a/semantics/memoryInstructions/pcmpistri_xmm_m128_imm8.k b/semantics/memoryInstructions/pcmpistri_xmm_m128_imm8.k index 5a15c9732..39b1d8978 100644 --- a/semantics/memoryInstructions/pcmpistri_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/pcmpistri_xmm_m128_imm8.k @@ -4,27 +4,28 @@ requires "x86-configuration.k" module PCMPISTRI-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(pcmpistri:Opcode Imm8:Imm, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] + context execinstr(pcmpistri:Opcode Imm8:MInt, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] rule - execinstr (pcmpistri:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => + execinstr (pcmpistri:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (pcmpistri Imm8, memOffset( MemOff), Xmm1, .Operands) ... - + requires bitwidthMInt(Imm8) ==Int 8 // Find Limit Index rule memLoadValue(Mem128:MInt):MemLoadValue ~> - execinstr (pcmpistri Imm8:Imm, Xmm2:Xmm, Xmm1:Xmm, .Operands) => + execinstr (pcmpistri Imm8:MInt, Xmm2:Xmm, Xmm1:Xmm, .Operands) => execinstr (pcmpistri - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, Mem128, getRegisterValue(Xmm1, RSMap), - findLimitIndexI(Mem128, handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexI(getRegisterValue(Xmm1, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexI(Mem128, Imm8), + findLimitIndexI(getRegisterValue(Xmm1, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // Find data size and interpretation rule diff --git a/semantics/memoryInstructions/pcmpistrm_xmm_m128_imm8.k b/semantics/memoryInstructions/pcmpistrm_xmm_m128_imm8.k index 62bca883f..6dd931b04 100644 --- a/semantics/memoryInstructions/pcmpistrm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/pcmpistrm_xmm_m128_imm8.k @@ -4,26 +4,28 @@ requires "x86-configuration.k" module PCMPISTRM-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(pcmpistrm:Opcode Imm8:Imm, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] + context execinstr(pcmpistrm:Opcode Imm8:MInt, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] rule - execinstr (pcmpistrm:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => + execinstr (pcmpistrm:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (pcmpistrm Imm8, memOffset( MemOff), Xmm1, .Operands) ... + requires bitwidthMInt(Imm8) ==Int 8 // Find Limit Index rule memLoadValue(Mem128:MInt):MemLoadValue ~> - execinstr (pcmpistrm Imm8:Imm, Xmm2:Xmm, Xmm1:Xmm, .Operands) => + execinstr (pcmpistrm Imm8:MInt, Xmm2:Xmm, Xmm1:Xmm, .Operands) => execinstr (pcmpistrm - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, Mem128, getRegisterValue(Xmm1, RSMap), - findLimitIndexI(Mem128, handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexI(getRegisterValue(Xmm1, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexI(Mem128, Imm8), + findLimitIndexI(getRegisterValue(Xmm1, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // Find data size and interpretation rule diff --git a/semantics/memoryInstructions/pextrb_m8_xmm_imm8.k b/semantics/memoryInstructions/pextrb_m8_xmm_imm8.k index d7ab2d23b..b73966a0d 100644 --- a/semantics/memoryInstructions/pextrb_m8_xmm_imm8.k +++ b/semantics/memoryInstructions/pextrb_m8_xmm_imm8.k @@ -4,24 +4,26 @@ requires "x86-configuration.k" module PEXTRB-M8-XMM-IMM8 imports X86-CONFIGURATION - context execinstr(pextrb:Opcode Imm8:Imm, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(pextrb:Opcode Imm8:MInt, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (pextrb:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (pextrb:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (pextrb Imm8, R2:Xmm, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (pextrb:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (pextrb:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3))))), 120, 128), + extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3))))), 120, 128), MemOff, 8 ) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/pextrd_m32_xmm_imm8.k b/semantics/memoryInstructions/pextrd_m32_xmm_imm8.k index f5407af77..7f06e8236 100644 --- a/semantics/memoryInstructions/pextrd_m32_xmm_imm8.k +++ b/semantics/memoryInstructions/pextrd_m32_xmm_imm8.k @@ -4,24 +4,26 @@ requires "x86-configuration.k" module PEXTRD-M32-XMM-IMM8 imports X86-CONFIGURATION - context execinstr(pextrd:Opcode Imm8:Imm, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(pextrd:Opcode Imm8:MInt, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (pextrd:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (pextrd:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (pextrd Imm8, R2:Xmm, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (pextrd:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (pextrd:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128), + extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128), MemOff, 32 ) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/pextrq_m64_xmm_imm8.k b/semantics/memoryInstructions/pextrq_m64_xmm_imm8.k index 0d61dfb30..5aa3bbb84 100644 --- a/semantics/memoryInstructions/pextrq_m64_xmm_imm8.k +++ b/semantics/memoryInstructions/pextrq_m64_xmm_imm8.k @@ -4,24 +4,26 @@ requires "x86-configuration.k" module PEXTRQ-M64-XMM-IMM8 imports X86-CONFIGURATION - context execinstr(pextrq:Opcode Imm8:Imm, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(pextrq:Opcode Imm8:MInt, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (pextrq:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (pextrq:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (pextrq Imm8, R2:Xmm, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (pextrq:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (pextrq:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6))))), 64, 128), + extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6))))), 64, 128), MemOff, 64 ) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/pextrw_m16_xmm_imm8.k b/semantics/memoryInstructions/pextrw_m16_xmm_imm8.k index f95eff99d..9935ae96a 100644 --- a/semantics/memoryInstructions/pextrw_m16_xmm_imm8.k +++ b/semantics/memoryInstructions/pextrw_m16_xmm_imm8.k @@ -4,24 +4,26 @@ requires "x86-configuration.k" module PEXTRW-M16-XMM-IMM8 imports X86-CONFIGURATION - context execinstr(pextrw:Opcode Imm8:Imm, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(pextrw:Opcode Imm8:MInt, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (pextrw:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (pextrw:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (pextrw Imm8, R2:Xmm, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (pextrw:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (pextrw:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4))))), 112, 128), + extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4))))), 112, 128), MemOff, 16 ) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/pinsrb_xmm_m8_imm8.k b/semantics/memoryInstructions/pinsrb_xmm_m8_imm8.k index 042e06a78..49e837687 100644 --- a/semantics/memoryInstructions/pinsrb_xmm_m8_imm8.k +++ b/semantics/memoryInstructions/pinsrb_xmm_m8_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module PINSRB-XMM-M8-IMM8 imports X86-CONFIGURATION - context execinstr(pinsrb:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(pinsrb:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (pinsrb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (pinsrb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (pinsrb Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (pinsrb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (pinsrb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(120, 0), Mem8), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3))))), shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3)))))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(120, 0), Mem8), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3))))), shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/pinsrd_xmm_m32_imm8.k b/semantics/memoryInstructions/pinsrd_xmm_m32_imm8.k index 56522bc13..0516c0b31 100644 --- a/semantics/memoryInstructions/pinsrd_xmm_m32_imm8.k +++ b/semantics/memoryInstructions/pinsrd_xmm_m32_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module PINSRD-XMM-M32-IMM8 imports X86-CONFIGURATION - context execinstr(pinsrd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(pinsrd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (pinsrd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (pinsrd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (pinsrd Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (pinsrd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (pinsrd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), Mem32), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5)))))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), Mem32), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/pinsrq_xmm_m64_imm8.k b/semantics/memoryInstructions/pinsrq_xmm_m64_imm8.k index edfe63203..7b9bc6903 100644 --- a/semantics/memoryInstructions/pinsrq_xmm_m64_imm8.k +++ b/semantics/memoryInstructions/pinsrq_xmm_m64_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module PINSRQ-XMM-M64-IMM8 imports X86-CONFIGURATION - context execinstr(pinsrq:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(pinsrq:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (pinsrq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (pinsrq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (pinsrq Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (pinsrq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (pinsrq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(64, 0), Mem64), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6))))), shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6)))))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(64, 0), Mem64), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6))))), shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/pinsrw_xmm_m16_imm8.k b/semantics/memoryInstructions/pinsrw_xmm_m16_imm8.k index 5bed131d4..7ae87cb30 100644 --- a/semantics/memoryInstructions/pinsrw_xmm_m16_imm8.k +++ b/semantics/memoryInstructions/pinsrw_xmm_m16_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module PINSRW-XMM-M16-IMM8 imports X86-CONFIGURATION - context execinstr(pinsrw:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(pinsrw:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (pinsrw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (pinsrw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (pinsrw Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (pinsrw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (pinsrw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(112, 0), Mem16), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4))))), shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4)))))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(112, 0), Mem16), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4))))), shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/pshufd_xmm_m128_imm8.k b/semantics/memoryInstructions/pshufd_xmm_m128_imm8.k index f0842f0ea..3a8776d47 100644 --- a/semantics/memoryInstructions/pshufd_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/pshufd_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module PSHUFD-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(pshufd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(pshufd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (pshufd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (pshufd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (pshufd Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (pshufd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (pshufd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/pshufhw_xmm_m128_imm8.k b/semantics/memoryInstructions/pshufhw_xmm_m128_imm8.k index 21db89b0b..ac5963cc5 100644 --- a/semantics/memoryInstructions/pshufhw_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/pshufhw_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module PSHUFHW-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(pshufhw:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(pshufhw:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (pshufhw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (pshufhw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (pshufhw Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (pshufhw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (pshufhw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 4))))), 48, 64), extractMInt( Mem128, 64, 128)))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 4))))), 48, 64), extractMInt( Mem128, 64, 128)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/pshuflw_xmm_m128_imm8.k b/semantics/memoryInstructions/pshuflw_xmm_m128_imm8.k index 40071f4bf..916bf22a1 100644 --- a/semantics/memoryInstructions/pshuflw_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/pshuflw_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module PSHUFLW-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(pshuflw:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(pshuflw:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (pshuflw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (pshuflw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (pshuflw Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (pshuflw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (pshuflw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( extractMInt( Mem128, 0, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 4))))), 112, 128), extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 4))))), 112, 128)))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( extractMInt( Mem128, 0, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 4))))), 112, 128), extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 4))))), 112, 128)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rclb_m8_imm8.k b/semantics/memoryInstructions/rclb_m8_imm8.k index 1e9c4b1a0..212f87c6f 100644 --- a/semantics/memoryInstructions/rclb_m8_imm8.k +++ b/semantics/memoryInstructions/rclb_m8_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module RCLB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(rclb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(rclb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (rclb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (rclb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (rclb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (rclb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (rclb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 1, 9), + extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 1, 9), MemOff, 8 ) @@ -25,9 +26,10 @@ module RCLB-M8-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 0, 1) +"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rcll_m32_imm8.k b/semantics/memoryInstructions/rcll_m32_imm8.k index 1820d2099..e0da5ed9c 100644 --- a/semantics/memoryInstructions/rcll_m32_imm8.k +++ b/semantics/memoryInstructions/rcll_m32_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module RCLL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(rcll:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(rcll:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (rcll:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (rcll:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (rcll Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (rcll:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (rcll:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 1, 33), + extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 1, 33), MemOff, 32 ) @@ -25,9 +26,10 @@ module RCLL-M32-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 0, 1) +"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rclq_m64_imm8.k b/semantics/memoryInstructions/rclq_m64_imm8.k index 8f5625314..cf3443d73 100644 --- a/semantics/memoryInstructions/rclq_m64_imm8.k +++ b/semantics/memoryInstructions/rclq_m64_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module RCLQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(rclq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(rclq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (rclq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (rclq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (rclq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (rclq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (rclq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 1, 65), + extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 1, 65), MemOff, 64 ) @@ -25,9 +26,10 @@ module RCLQ-M64-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 0, 1) +"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rclw_m16_imm8.k b/semantics/memoryInstructions/rclw_m16_imm8.k index bd9fdc138..db3ea085e 100644 --- a/semantics/memoryInstructions/rclw_m16_imm8.k +++ b/semantics/memoryInstructions/rclw_m16_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module RCLW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(rclw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(rclw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (rclw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (rclw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (rclw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (rclw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (rclw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 1, 17), + extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 1, 17), MemOff, 16 ) @@ -25,9 +26,10 @@ module RCLW-M16-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 0, 1) +"CF" |-> extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1)) andBool (eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rcrb_m8_imm8.k b/semantics/memoryInstructions/rcrb_m8_imm8.k index 56168eaba..6b37b602b 100644 --- a/semantics/memoryInstructions/rcrb_m8_imm8.k +++ b/semantics/memoryInstructions/rcrb_m8_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module RCRB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(rcrb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(rcrb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (rcrb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (rcrb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (rcrb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (rcrb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (rcrb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 1, 9), + extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 1, 9), MemOff, 8 ) @@ -25,9 +26,10 @@ module RCRB-M8-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 0, 1) +"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem8), uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))), mi(9, 9)), 1, 9), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rcrl_m32_imm8.k b/semantics/memoryInstructions/rcrl_m32_imm8.k index eb957b2fb..aa3cd6441 100644 --- a/semantics/memoryInstructions/rcrl_m32_imm8.k +++ b/semantics/memoryInstructions/rcrl_m32_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module RCRL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(rcrl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(rcrl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (rcrl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (rcrl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (rcrl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (rcrl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (rcrl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 1, 33), + extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 1, 33), MemOff, 32 ) @@ -25,9 +26,10 @@ module RCRL-M32-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 0, 1) +"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem32), uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))), mi(33, 33)), 25, 33), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rcrq_m64_imm8.k b/semantics/memoryInstructions/rcrq_m64_imm8.k index e4ff5d706..4b542beb5 100644 --- a/semantics/memoryInstructions/rcrq_m64_imm8.k +++ b/semantics/memoryInstructions/rcrq_m64_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module RCRQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(rcrq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(rcrq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (rcrq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (rcrq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (rcrq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (rcrq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (rcrq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 1, 65), + extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 1, 65), MemOff, 64 ) @@ -25,9 +26,10 @@ module RCRQ-M64-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 0, 1) +"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem64), uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))), mi(65, 65)), 57, 65), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rcrw_m16_imm8.k b/semantics/memoryInstructions/rcrw_m16_imm8.k index d580ecd02..ba4cc16fe 100644 --- a/semantics/memoryInstructions/rcrw_m16_imm8.k +++ b/semantics/memoryInstructions/rcrw_m16_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module RCRW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(rcrw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(rcrw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (rcrw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (rcrw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (rcrw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (rcrw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (rcrw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 1, 17), + extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 1, 17), MemOff, 16 ) @@ -25,9 +26,10 @@ module RCRW-M16-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 0, 1) +"CF" |-> extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 0, 1) -"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1)) andBool (eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 1, 2), mi(1, 1)) xorBool eqMInt( extractMInt( ror( concatenateMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then mi(1, 1) #else mi(1, 0) #fi), Mem16), uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17))), 2, 3), mi(1, 1)))) orBool ((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 1))) andBool (((notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( extractMInt( uremMInt( concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))), mi(17, 17)), 9, 17), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rolb_m8_imm8.k b/semantics/memoryInstructions/rolb_m8_imm8.k index 115587aac..c825e8e4a 100644 --- a/semantics/memoryInstructions/rolb_m8_imm8.k +++ b/semantics/memoryInstructions/rolb_m8_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ROLB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(rolb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(rolb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (rolb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (rolb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (rolb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (rolb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (rolb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - rol( Mem8, andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), + rol( Mem8, andMInt( Imm8, mi(8, 31))), MemOff, 8 ) @@ -25,9 +26,10 @@ module ROLB-M8-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( rol( Mem8, andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 7, 8), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( rol( Mem8, andMInt( Imm8, mi(8, 31))), 7, 8), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( Mem8, andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( Mem8, andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 7, 8), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( Mem8, andMInt( Imm8, mi(8, 31))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( Mem8, andMInt( Imm8, mi(8, 31))), 7, 8), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/roll_m32_imm8.k b/semantics/memoryInstructions/roll_m32_imm8.k index 0e57abfb6..fe67f00e8 100644 --- a/semantics/memoryInstructions/roll_m32_imm8.k +++ b/semantics/memoryInstructions/roll_m32_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ROLL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(roll:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(roll:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (roll:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (roll:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (roll Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (roll:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (roll:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - rol( Mem32, concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), + rol( Mem32, concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31)))), MemOff, 32 ) @@ -25,9 +26,10 @@ module ROLL-M32-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( rol( Mem32, concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 31, 32), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( rol( Mem32, concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31)))), 31, 32), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( Mem32, concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( Mem32, concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 31, 32), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( Mem32, concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( Mem32, concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31)))), 31, 32), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rolq_m64_imm8.k b/semantics/memoryInstructions/rolq_m64_imm8.k index cc2e55f91..116062163 100644 --- a/semantics/memoryInstructions/rolq_m64_imm8.k +++ b/semantics/memoryInstructions/rolq_m64_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ROLQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(rolq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(rolq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (rolq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (rolq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (rolq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (rolq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (rolq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - rol( Mem64, concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))), + rol( Mem64, concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))), MemOff, 64 ) @@ -25,9 +26,10 @@ module ROLQ-M64-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( rol( Mem64, concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))), 63, 64), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( rol( Mem64, concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))), 63, 64), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( Mem64, concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( Mem64, concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))), 63, 64), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( Mem64, concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( Mem64, concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))), 63, 64), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rolw_m16_imm8.k b/semantics/memoryInstructions/rolw_m16_imm8.k index 7e03695af..83ebb9836 100644 --- a/semantics/memoryInstructions/rolw_m16_imm8.k +++ b/semantics/memoryInstructions/rolw_m16_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module ROLW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(rolw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(rolw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (rolw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (rolw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (rolw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (rolw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (rolw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - rol( Mem16, concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), + rol( Mem16, concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31)))), MemOff, 16 ) @@ -25,9 +26,10 @@ module ROLW-M16-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( rol( Mem16, concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 15, 16), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( rol( Mem16, concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31)))), 15, 16), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( Mem16, concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( Mem16, concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 15, 16), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( rol( Mem16, concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( Mem16, concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31)))), 15, 16), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rorb_m8_imm8.k b/semantics/memoryInstructions/rorb_m8_imm8.k index e22fbf7e7..80e919c13 100644 --- a/semantics/memoryInstructions/rorb_m8_imm8.k +++ b/semantics/memoryInstructions/rorb_m8_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module RORB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(rorb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(rorb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (rorb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (rorb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (rorb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (rorb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (rorb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - ror( Mem8, andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), + ror( Mem8, andMInt( Imm8, mi(8, 31))), MemOff, 8 ) @@ -25,9 +26,10 @@ module RORB-M8-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( ror( Mem8, andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( ror( Mem8, andMInt( Imm8, mi(8, 31))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( Mem8, andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( Mem8, andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( Mem8, andMInt( Imm8, mi(8, 31))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( Mem8, andMInt( Imm8, mi(8, 31))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rorl_m32_imm8.k b/semantics/memoryInstructions/rorl_m32_imm8.k index 8499c1983..50ef81eeb 100644 --- a/semantics/memoryInstructions/rorl_m32_imm8.k +++ b/semantics/memoryInstructions/rorl_m32_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module RORL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(rorl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(rorl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (rorl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (rorl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (rorl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (rorl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (rorl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - ror( Mem32, concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), + ror( Mem32, concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31)))), MemOff, 32 ) @@ -25,9 +26,10 @@ module RORL-M32-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( ror( Mem32, concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( ror( Mem32, concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31)))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( Mem32, concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( Mem32, concatenateMInt( mi(24, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( Mem32, concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( Mem32, concatenateMInt( mi(24, 0), andMInt( Imm8, mi(8, 31)))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rorq_m64_imm8.k b/semantics/memoryInstructions/rorq_m64_imm8.k index 8999aa369..d89905778 100644 --- a/semantics/memoryInstructions/rorq_m64_imm8.k +++ b/semantics/memoryInstructions/rorq_m64_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module RORQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(rorq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(rorq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (rorq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (rorq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (rorq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (rorq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (rorq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - ror( Mem64, concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))), + ror( Mem64, concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))), MemOff, 64 ) @@ -25,9 +26,10 @@ module RORQ-M64-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( ror( Mem64, concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( ror( Mem64, concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( Mem64, concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( Mem64, concatenateMInt( mi(56, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( Mem64, concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( Mem64, concatenateMInt( mi(56, 0), andMInt( Imm8, mi(8, 63)))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rorw_m16_imm8.k b/semantics/memoryInstructions/rorw_m16_imm8.k index 24b01f49f..b68cd20d0 100644 --- a/semantics/memoryInstructions/rorw_m16_imm8.k +++ b/semantics/memoryInstructions/rorw_m16_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module RORW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(rorw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(rorw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (rorw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (rorw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (rorw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (rorw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (rorw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - ror( Mem16, concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), + ror( Mem16, concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31)))), MemOff, 16 ) @@ -25,9 +26,10 @@ module RORW-M16-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( ror( Mem16, concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( ror( Mem16, concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31)))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( Mem16, concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( Mem16, concatenateMInt( mi(8, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (eqMInt( extractMInt( ror( Mem16, concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31)))), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( ror( Mem16, concatenateMInt( mi(8, 0), andMInt( Imm8, mi(8, 31)))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rorxl_r32_m32_imm8.k b/semantics/memoryInstructions/rorxl_r32_m32_imm8.k index 403e4c689..93b6be969 100644 --- a/semantics/memoryInstructions/rorxl_r32_m32_imm8.k +++ b/semantics/memoryInstructions/rorxl_r32_m32_imm8.k @@ -5,24 +5,26 @@ module RORXL-R32-M32-IMM8 imports X86-CONFIGURATION rule - execinstr (rorx:Opcode Imm8:Imm, M:Mem, R3:R32, .Operands) => execinstr (rorxl:Opcode Imm8:Imm, M:Mem, R3:R32, .Operands) + execinstr (rorx:Opcode Imm8:MInt, M:Mem, R3:R32, .Operands) => execinstr (rorxl:Opcode Imm8:MInt, M:Mem, R3:R32, .Operands) ... - context execinstr(rorxl:Opcode Imm8:Imm, HOLE:Mem, R3:R32, .Operands) [result(MemOffset)] + context execinstr(rorxl:Opcode Imm8:MInt, HOLE:Mem, R3:R32, .Operands) [result(MemOffset)] rule - execinstr (rorxl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:R32, .Operands) => + execinstr (rorxl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:R32, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (rorxl Imm8, memOffset( MemOff), R3, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (rorxl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:R32, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (rorxl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:R32, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), orMInt( lshrMInt( Mem32, uvalueMInt(andMInt( concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(32, 31)))), shiftLeftMInt( Mem32, uvalueMInt(subMInt( mi(32, 32), andMInt( concatenateMInt( mi(24, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(32, 31))))))) +convToRegKeys(R3) |-> concatenateMInt( mi(32, 0), orMInt( lshrMInt( Mem32, uvalueMInt(andMInt( concatenateMInt( mi(24, 0), Imm8), mi(32, 31)))), shiftLeftMInt( Mem32, uvalueMInt(subMInt( mi(32, 32), andMInt( concatenateMInt( mi(24, 0), Imm8), mi(32, 31))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/rorxq_r64_m64_imm8.k b/semantics/memoryInstructions/rorxq_r64_m64_imm8.k index 4c6ff662d..66e54a499 100644 --- a/semantics/memoryInstructions/rorxq_r64_m64_imm8.k +++ b/semantics/memoryInstructions/rorxq_r64_m64_imm8.k @@ -5,24 +5,26 @@ module RORXQ-R64-M64-IMM8 imports X86-CONFIGURATION rule - execinstr (rorx:Opcode Imm8:Imm, M:Mem, R3:R64, .Operands) => execinstr (rorxq:Opcode Imm8:Imm, M:Mem, R3:R64, .Operands) + execinstr (rorx:Opcode Imm8:MInt, M:Mem, R3:R64, .Operands) => execinstr (rorxq:Opcode Imm8:MInt, M:Mem, R3:R64, .Operands) ... - context execinstr(rorxq:Opcode Imm8:Imm, HOLE:Mem, R3:R64, .Operands) [result(MemOffset)] + context execinstr(rorxq:Opcode Imm8:MInt, HOLE:Mem, R3:R64, .Operands) [result(MemOffset)] rule - execinstr (rorxq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:R64, .Operands) => + execinstr (rorxq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:R64, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (rorxq Imm8, memOffset( MemOff), R3, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (rorxq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:R64, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (rorxq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:R64, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> orMInt( lshrMInt( Mem64, uvalueMInt(andMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 63)))), shiftLeftMInt( Mem64, uvalueMInt(subMInt( mi(64, 64), andMInt( concatenateMInt( mi(56, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(64, 63)))))) +convToRegKeys(R3) |-> orMInt( lshrMInt( Mem64, uvalueMInt(andMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 63)))), shiftLeftMInt( Mem64, uvalueMInt(subMInt( mi(64, 64), andMInt( concatenateMInt( mi(56, 0), Imm8), mi(64, 63)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/roundpd_xmm_m128_imm8.k b/semantics/memoryInstructions/roundpd_xmm_m128_imm8.k index ae8284b22..2b1e60e30 100644 --- a/semantics/memoryInstructions/roundpd_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/roundpd_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module ROUNDPD-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(roundpd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(roundpd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (roundpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (roundpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (roundpd Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (roundpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (roundpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( cvt_double_to_int64_rm(extractMInt( Mem128, 0, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_double_to_int64_rm(extractMInt( Mem128, 64, 128), handleImmediateWithSignExtend(Imm8, 8, 8)))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( cvt_double_to_int64_rm(extractMInt( Mem128, 0, 64), Imm8), cvt_double_to_int64_rm(extractMInt( Mem128, 64, 128), Imm8))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/roundps_xmm_m128_imm8.k b/semantics/memoryInstructions/roundps_xmm_m128_imm8.k index 53aba7948..1eafb838e 100644 --- a/semantics/memoryInstructions/roundps_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/roundps_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module ROUNDPS-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(roundps:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(roundps:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (roundps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (roundps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (roundps Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (roundps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (roundps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem128, 0, 32), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem128, 32, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem128, 64, 96), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_single_to_int32_rm(extractMInt( Mem128, 96, 128), handleImmediateWithSignExtend(Imm8, 8, 8)))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem128, 0, 32), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem128, 32, 64), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem128, 64, 96), Imm8), cvt_single_to_int32_rm(extractMInt( Mem128, 96, 128), Imm8))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/roundsd_xmm_m64_imm8.k b/semantics/memoryInstructions/roundsd_xmm_m64_imm8.k index 8cc87cd6b..7e64db1ec 100644 --- a/semantics/memoryInstructions/roundsd_xmm_m64_imm8.k +++ b/semantics/memoryInstructions/roundsd_xmm_m64_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module ROUNDSD-XMM-M64-IMM8 imports X86-CONFIGURATION - context execinstr(roundsd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(roundsd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (roundsd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (roundsd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (roundsd Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (roundsd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (roundsd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 192), cvt_double_to_int64_rm(Mem64, handleImmediateWithSignExtend(Imm8, 8, 8))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 192), cvt_double_to_int64_rm(Mem64, Imm8)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/roundss_xmm_m32_imm8.k b/semantics/memoryInstructions/roundss_xmm_m32_imm8.k index 40c5a4a58..87aa38cd2 100644 --- a/semantics/memoryInstructions/roundss_xmm_m32_imm8.k +++ b/semantics/memoryInstructions/roundss_xmm_m32_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module ROUNDSS-XMM-M32-IMM8 imports X86-CONFIGURATION - context execinstr(roundss:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(roundss:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (roundss:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (roundss:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (roundss Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (roundss:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (roundss:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 224), cvt_single_to_int32_rm(Mem32, handleImmediateWithSignExtend(Imm8, 8, 8))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 224), cvt_single_to_int32_rm(Mem32, Imm8)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/salb_m8_imm8.k b/semantics/memoryInstructions/salb_m8_imm8.k index 80244bebe..3f2288643 100644 --- a/semantics/memoryInstructions/salb_m8_imm8.k +++ b/semantics/memoryInstructions/salb_m8_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SALB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(salb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(salb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (salb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (salb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (salb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (salb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (salb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 9), + extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 9), MemOff, 8 ) @@ -25,17 +26,18 @@ module SALB-M8-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 9), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 9), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/sall_m32_imm8.k b/semantics/memoryInstructions/sall_m32_imm8.k index e0db794b1..429a7ea76 100644 --- a/semantics/memoryInstructions/sall_m32_imm8.k +++ b/semantics/memoryInstructions/sall_m32_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SALL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(sall:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(sall:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (sall:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (sall:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (sall Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (sall:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (sall:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 33), + extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 33), MemOff, 32 ) @@ -25,17 +26,18 @@ module SALL-M32-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 25, 26), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 25, 26), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 33), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 33), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/salq_m64_imm8.k b/semantics/memoryInstructions/salq_m64_imm8.k index 91a19ad89..055316671 100644 --- a/semantics/memoryInstructions/salq_m64_imm8.k +++ b/semantics/memoryInstructions/salq_m64_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SALQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(salq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(salq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (salq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (salq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (salq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (salq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (salq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 65), + extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 65), MemOff, 64 ) @@ -25,17 +26,18 @@ module SALQ-M64-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 57, 58), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 57, 58), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 65), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 65), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/salw_m16_imm8.k b/semantics/memoryInstructions/salw_m16_imm8.k index c83bfe219..496297d94 100644 --- a/semantics/memoryInstructions/salw_m16_imm8.k +++ b/semantics/memoryInstructions/salw_m16_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SALW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(salw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(salw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (salw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (salw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (salw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (salw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (salw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 17), + extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 17), MemOff, 16 ) @@ -25,17 +26,18 @@ module SALW-M16-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 9, 10), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 9, 10), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 17), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 17), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/sarb_m8_imm8.k b/semantics/memoryInstructions/sarb_m8_imm8.k index 59d97e5a7..5442d340f 100644 --- a/semantics/memoryInstructions/sarb_m8_imm8.k +++ b/semantics/memoryInstructions/sarb_m8_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SARB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(sarb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(sarb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (sarb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (sarb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (sarb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (sarb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (sarb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 8), + extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 8), MemOff, 8 ) @@ -25,17 +26,18 @@ module SARB-M8-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 7, 8), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 7, 8), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 8), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 8), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/sarl_m32_imm8.k b/semantics/memoryInstructions/sarl_m32_imm8.k index c73573a2f..bbbdd9d10 100644 --- a/semantics/memoryInstructions/sarl_m32_imm8.k +++ b/semantics/memoryInstructions/sarl_m32_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SARL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(sarl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(sarl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (sarl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (sarl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (sarl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (sarl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (sarl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 32), + extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 32), MemOff, 32 ) @@ -25,17 +26,18 @@ module SARL-M32-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 32, 33), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 32, 33), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 31, 32), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 25, 26), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 24, 25), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 31, 32), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 25, 26), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 24, 25), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 32), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 32), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/sarq_m64_imm8.k b/semantics/memoryInstructions/sarq_m64_imm8.k index 74a84be29..16befd942 100644 --- a/semantics/memoryInstructions/sarq_m64_imm8.k +++ b/semantics/memoryInstructions/sarq_m64_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SARQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(sarq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(sarq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (sarq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (sarq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (sarq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (sarq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (sarq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 64), + extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 64), MemOff, 64 ) @@ -25,17 +26,18 @@ module SARQ-M64-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 64, 65), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 64, 65), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 63, 64), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 57, 58), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 56, 57), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 63, 64), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 57, 58), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 56, 57), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 64), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 64), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/sarw_m16_imm8.k b/semantics/memoryInstructions/sarw_m16_imm8.k index 26983a601..12f5232da 100644 --- a/semantics/memoryInstructions/sarw_m16_imm8.k +++ b/semantics/memoryInstructions/sarw_m16_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SARW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(sarw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(sarw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (sarw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (sarw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (sarw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (sarw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (sarw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 16), + extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 16), MemOff, 16 ) @@ -25,17 +26,18 @@ module SARW-M16-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 16, 17), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 16, 17), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 15, 16), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 9, 10), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 15, 16), mi(1, 1)) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 9, 10), mi(1, 1))) xorBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 16), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 16), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( aShiftRightMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool false) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/sbbb_m8_imm8.k b/semantics/memoryInstructions/sbbb_m8_imm8.k index a468e8290..cc891bd13 100644 --- a/semantics/memoryInstructions/sbbb_m8_imm8.k +++ b/semantics/memoryInstructions/sbbb_m8_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SBBB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(sbbb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(sbbb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (sbbb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (sbbb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (sbbb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (sbbb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (sbbb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 9), + extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 9), MemOff, 8 ) @@ -25,17 +26,18 @@ module SBBB-M8-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem8, 3, 4)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem8, 3, 4)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem8, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem8, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm8)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)) #fi), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/sbbl_m32_imm32.k b/semantics/memoryInstructions/sbbl_m32_imm32.k index 1ba0b6a37..876dc9a29 100644 --- a/semantics/memoryInstructions/sbbl_m32_imm32.k +++ b/semantics/memoryInstructions/sbbl_m32_imm32.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SBBL-M32-IMM32 imports X86-CONFIGURATION - context execinstr(sbbl:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(sbbl:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (sbbl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (sbbl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (sbbl Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (sbbl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (sbbl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), + extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), MemOff, 32 ) @@ -25,17 +26,18 @@ module SBBL-M32-IMM32 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm32)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/sbbl_m32_imm8.k b/semantics/memoryInstructions/sbbl_m32_imm8.k index 27e5f5e99..3c6ce1174 100644 --- a/semantics/memoryInstructions/sbbl_m32_imm8.k +++ b/semantics/memoryInstructions/sbbl_m32_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SBBL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(sbbl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(sbbl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (sbbl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (sbbl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (sbbl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (sbbl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (sbbl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), + extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), MemOff, 32 ) @@ -25,17 +26,18 @@ module SBBL-M32-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)) #fi), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/sbbq_m64_imm32.k b/semantics/memoryInstructions/sbbq_m64_imm32.k index 411fc3817..b46c2d453 100644 --- a/semantics/memoryInstructions/sbbq_m64_imm32.k +++ b/semantics/memoryInstructions/sbbq_m64_imm32.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SBBQ-M64-IMM32 imports X86-CONFIGURATION - context execinstr(sbbq:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(sbbq:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (sbbq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (sbbq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (sbbq Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (sbbq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (sbbq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), + extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), MemOff, 64 ) @@ -25,17 +26,18 @@ module SBBQ-M64-IMM32 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/sbbq_m64_imm8.k b/semantics/memoryInstructions/sbbq_m64_imm8.k index 3e298d180..23649dcf3 100644 --- a/semantics/memoryInstructions/sbbq_m64_imm8.k +++ b/semantics/memoryInstructions/sbbq_m64_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SBBQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(sbbq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(sbbq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (sbbq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (sbbq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (sbbq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (sbbq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (sbbq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), + extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), MemOff, 64 ) @@ -25,17 +26,18 @@ module SBBQ-M64-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)) #fi), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/sbbw_m16_imm16.k b/semantics/memoryInstructions/sbbw_m16_imm16.k index ae798b603..0b9c92500 100644 --- a/semantics/memoryInstructions/sbbw_m16_imm16.k +++ b/semantics/memoryInstructions/sbbw_m16_imm16.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SBBW-M16-IMM16 imports X86-CONFIGURATION - context execinstr(sbbw:Opcode Imm16:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(sbbw:Opcode Imm16:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (sbbw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (sbbw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (sbbw Imm16, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm16) ==Int 16 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (sbbw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (sbbw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), + extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), MemOff, 16 ) @@ -25,17 +26,18 @@ module SBBW-M16-IMM16 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm16, 11, 12), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( Imm16)) #else addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/memoryInstructions/sbbw_m16_imm8.k b/semantics/memoryInstructions/sbbw_m16_imm8.k index e9c12872c..0676dff77 100644 --- a/semantics/memoryInstructions/sbbw_m16_imm8.k +++ b/semantics/memoryInstructions/sbbw_m16_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SBBW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(sbbw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(sbbw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (sbbw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (sbbw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (sbbw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (sbbw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (sbbw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), + extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), MemOff, 16 ) @@ -25,17 +26,18 @@ module SBBW-M16-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2) +"SF" |-> extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( (#ifMInt eqMInt(getFlag("CF", RSMap), mi(1,1)) #then concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))) #else addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)) #fi), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/shlb_m8_imm8.k b/semantics/memoryInstructions/shlb_m8_imm8.k index 740e7baee..91cb93dda 100644 --- a/semantics/memoryInstructions/shlb_m8_imm8.k +++ b/semantics/memoryInstructions/shlb_m8_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SHLB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(shlb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(shlb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (shlb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shlb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (shlb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (shlb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (shlb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 9), + extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 9), MemOff, 8 ) @@ -25,17 +26,18 @@ module SHLB-M8-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 9), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 9), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem8), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/shldl_m32_r32_imm8.k b/semantics/memoryInstructions/shldl_m32_r32_imm8.k index 1bbfba3b8..a0c66fe5f 100644 --- a/semantics/memoryInstructions/shldl_m32_r32_imm8.k +++ b/semantics/memoryInstructions/shldl_m32_r32_imm8.k @@ -4,21 +4,23 @@ requires "x86-configuration.k" module SHLDL-M32-R32-IMM8 imports X86-CONFIGURATION - context execinstr (shldl Imm8:Imm, R2:R32, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr (shldl Imm8:MInt, R2:R32, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (shldl Imm8:Imm, R2:R32, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shldl Imm8:MInt, R2:R32, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> - execinstr (shldl Imm8:Imm, R2, memOffset( MemOff), .Operands) + execinstr (shldl Imm8:MInt, R2, memOffset( MemOff), .Operands) ... + requires bitwidthMInt(Imm8) ==Int 8 rule memLoadValue(Mem32:MInt):MemLoadValue ~> - execinstr (shldl Imm8:Imm, R2:R32, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shldl Imm8:MInt, R2:R32, memOffset( MemOff:MInt):MemOffset, .Operands) => execinstr (shldl memOffset( MemOff), Mem32, getRegisterValue(R2, RSMap), - shiftCountMask(handleImmediateWithSignExtend(Imm8, 8, 8), 32), .Operands) + shiftCountMask(Imm8, 32), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (shldl memOffset( MemOff), MIdest:MInt, MIsrc:MInt, MIcount:MInt, .Operands) => . diff --git a/semantics/memoryInstructions/shldq_m64_r64_imm8.k b/semantics/memoryInstructions/shldq_m64_r64_imm8.k index df6839aed..447ebf1df 100644 --- a/semantics/memoryInstructions/shldq_m64_r64_imm8.k +++ b/semantics/memoryInstructions/shldq_m64_r64_imm8.k @@ -4,21 +4,23 @@ requires "x86-configuration.k" module SHLDQ-M64-R64-CL imports X86-CONFIGURATION - context execinstr (shldq Imm8:Imm, R2:R64, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr (shldq Imm8:MInt, R2:R64, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (shldq Imm8:Imm, R2:R64, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shldq Imm8:MInt, R2:R64, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> - execinstr (shldq Imm8:Imm, R2, memOffset( MemOff), .Operands) + execinstr (shldq Imm8:MInt, R2, memOffset( MemOff), .Operands) ... + requires bitwidthMInt(Imm8) ==Int 8 rule memLoadValue(Mem64:MInt):MemLoadValue ~> - execinstr (shldq Imm8:Imm, R2:R64, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shldq Imm8:MInt, R2:R64, memOffset( MemOff:MInt):MemOffset, .Operands) => execinstr (shldq memOffset( MemOff), Mem64, getRegisterValue(R2, RSMap), - shiftCountMask(handleImmediateWithSignExtend(Imm8, 8, 8), 64), .Operands) + shiftCountMask(Imm8, 64), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (shldq memOffset( MemOff), MIdest:MInt, MIsrc:MInt, MIcount:MInt, .Operands) => . diff --git a/semantics/memoryInstructions/shldw_m16_r16_imm8.k b/semantics/memoryInstructions/shldw_m16_r16_imm8.k index 2506c083d..4ba4a6f2e 100644 --- a/semantics/memoryInstructions/shldw_m16_r16_imm8.k +++ b/semantics/memoryInstructions/shldw_m16_r16_imm8.k @@ -4,21 +4,23 @@ requires "x86-configuration.k" module SHLDW-M16-R16-CL imports X86-CONFIGURATION - context execinstr (shldw Imm8:Imm, R2:R16, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr (shldw Imm8:MInt, R2:R16, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (shldw Imm8:Imm, R2:R16, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shldw Imm8:MInt, R2:R16, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> - execinstr (shldw Imm8:Imm, R2, memOffset( MemOff), .Operands) + execinstr (shldw Imm8:MInt, R2, memOffset( MemOff), .Operands) ... + requires bitwidthMInt(Imm8) ==Int 8 rule memLoadValue(Mem16:MInt):MemLoadValue ~> - execinstr (shldw Imm8:Imm, R2:R16, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shldw Imm8:MInt, R2:R16, memOffset( MemOff:MInt):MemOffset, .Operands) => execinstr (shldw memOffset( MemOff), Mem16, getRegisterValue(R2, RSMap), - shiftCountMask(handleImmediateWithSignExtend(Imm8, 8, 8), 32), .Operands) + shiftCountMask(Imm8, 32), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (shldw memOffset( MemOff), MIdest:MInt, MIsrc:MInt, MIcount:MInt, .Operands) => . diff --git a/semantics/memoryInstructions/shll_m32_imm8.k b/semantics/memoryInstructions/shll_m32_imm8.k index a5b988a0b..ea987184f 100644 --- a/semantics/memoryInstructions/shll_m32_imm8.k +++ b/semantics/memoryInstructions/shll_m32_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SHLL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(shll:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(shll:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (shll:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shll:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (shll Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (shll:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (shll:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 33), + extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 33), MemOff, 32 ) @@ -25,17 +26,18 @@ module SHLL-M32-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 25, 26), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 25, 26), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 33), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 33), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem32), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/shlq_m64_imm8.k b/semantics/memoryInstructions/shlq_m64_imm8.k index 7a96d38c0..62330d61f 100644 --- a/semantics/memoryInstructions/shlq_m64_imm8.k +++ b/semantics/memoryInstructions/shlq_m64_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SHLQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(shlq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(shlq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (shlq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shlq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (shlq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (shlq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (shlq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 65), + extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 65), MemOff, 64 ) @@ -25,17 +26,18 @@ module SHLQ-M64-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 57, 58), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 57, 58), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 65), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 65), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem64), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/shlw_m16_imm8.k b/semantics/memoryInstructions/shlw_m16_imm8.k index 3fcaebaf3..71db36930 100644 --- a/semantics/memoryInstructions/shlw_m16_imm8.k +++ b/semantics/memoryInstructions/shlw_m16_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SHLW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(shlw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(shlw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (shlw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shlw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (shlw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (shlw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (shlw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 17), + extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 17), MemOff, 16 ) @@ -25,17 +26,18 @@ module SHLW-M16-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 9, 10), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 9, 10), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 17), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 17), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool (((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) xorBool eqMInt( extractMInt( shiftLeftMInt( concatenateMInt( mi(1, 0), Mem16), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1)))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/shrb_m8_imm8.k b/semantics/memoryInstructions/shrb_m8_imm8.k index 58f665a42..b6b5b4ebb 100644 --- a/semantics/memoryInstructions/shrb_m8_imm8.k +++ b/semantics/memoryInstructions/shrb_m8_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SHRB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(shrb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(shrb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (shrb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shrb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (shrb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (shrb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (shrb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 8), + extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 8), MemOff, 8 ) @@ -25,17 +26,18 @@ module SHRB-M8-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 8))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 7, 8), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 1, 2), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 7, 8), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 1, 2), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 8), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 8), mi(8, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem8, mi(1, 0)), uvalueMInt(concatenateMInt( mi(1, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool eqMInt( extractMInt( Mem8, 0, 1), mi(1, 1))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool eqMInt( extractMInt( Mem8, 0, 1), mi(1, 1))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/shrdl_m32_r32_imm8.k b/semantics/memoryInstructions/shrdl_m32_r32_imm8.k index 8ca298761..5fc70efe8 100644 --- a/semantics/memoryInstructions/shrdl_m32_r32_imm8.k +++ b/semantics/memoryInstructions/shrdl_m32_r32_imm8.k @@ -4,21 +4,23 @@ requires "x86-configuration.k" module SHLDL-M32-R32-CL imports X86-CONFIGURATION - context execinstr (shrdl Imm8:Imm, R2:R32, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr (shrdl Imm8:MInt, R2:R32, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (shrdl Imm8:Imm, R2:R32, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shrdl Imm8:MInt, R2:R32, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> - execinstr (shrdl Imm8:Imm, R2, memOffset( MemOff), .Operands) + execinstr (shrdl Imm8:MInt, R2, memOffset( MemOff), .Operands) ... + requires bitwidthMInt(Imm8) ==Int 8 rule memLoadValue(Mem32:MInt):MemLoadValue ~> - execinstr (shrdl Imm8:Imm, R2:R32, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shrdl Imm8:MInt, R2:R32, memOffset( MemOff:MInt):MemOffset, .Operands) => execinstr (shrdl memOffset( MemOff), Mem32, getRegisterValue(R2, RSMap), - shiftCountMask(handleImmediateWithSignExtend(Imm8, 8, 8), 32), .Operands) + shiftCountMask(Imm8, 32), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (shrdl memOffset( MemOff), MIdest:MInt, MIsrc:MInt, MIcount:MInt, .Operands) => . diff --git a/semantics/memoryInstructions/shrdq_m64_r64_imm8.k b/semantics/memoryInstructions/shrdq_m64_r64_imm8.k index 2959c8819..2cb4686ca 100644 --- a/semantics/memoryInstructions/shrdq_m64_r64_imm8.k +++ b/semantics/memoryInstructions/shrdq_m64_r64_imm8.k @@ -4,21 +4,23 @@ requires "x86-configuration.k" module SHRDQ-M64-R64-CL imports X86-CONFIGURATION - context execinstr (shrdq Imm8:Imm, R2:R64, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr (shrdq Imm8:MInt, R2:R64, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (shrdq Imm8:Imm, R2:R64, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shrdq Imm8:MInt, R2:R64, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> - execinstr (shrdq Imm8:Imm, R2, memOffset( MemOff), .Operands) + execinstr (shrdq Imm8:MInt, R2, memOffset( MemOff), .Operands) ... + requires bitwidthMInt(Imm8) ==Int 8 rule memLoadValue(Mem64:MInt):MemLoadValue ~> - execinstr (shrdq Imm8:Imm, R2:R64, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shrdq Imm8:MInt, R2:R64, memOffset( MemOff:MInt):MemOffset, .Operands) => execinstr (shrdq memOffset( MemOff), Mem64, getRegisterValue(R2, RSMap), - shiftCountMask(handleImmediateWithSignExtend(Imm8, 8, 8), 64), .Operands) + shiftCountMask(Imm8, 64), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (shrdq memOffset( MemOff), MIdest:MInt, MIsrc:MInt, MIcount:MInt, .Operands) => . diff --git a/semantics/memoryInstructions/shrdw_m16_r16_imm8.k b/semantics/memoryInstructions/shrdw_m16_r16_imm8.k index 53c6df4b2..dca5679cf 100644 --- a/semantics/memoryInstructions/shrdw_m16_r16_imm8.k +++ b/semantics/memoryInstructions/shrdw_m16_r16_imm8.k @@ -4,21 +4,23 @@ requires "x86-configuration.k" module SHLDW-M16-R16-CL imports X86-CONFIGURATION - context execinstr (shrdw Imm8:Imm, R2:R16, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr (shrdw Imm8:MInt, R2:R16, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (shrdw Imm8:Imm, R2:R16, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shrdw Imm8:MInt, R2:R16, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> - execinstr (shrdw Imm8:Imm, R2, memOffset( MemOff), .Operands) + execinstr (shrdw Imm8:MInt, R2, memOffset( MemOff), .Operands) ... + requires bitwidthMInt(Imm8) ==Int 8 rule memLoadValue(Mem16:MInt):MemLoadValue ~> - execinstr (shrdw Imm8:Imm, R2:R16, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shrdw Imm8:MInt, R2:R16, memOffset( MemOff:MInt):MemOffset, .Operands) => execinstr (shrdw memOffset( MemOff), Mem16, getRegisterValue(R2, RSMap), - shiftCountMask(handleImmediateWithSignExtend(Imm8, 8, 8), 32), .Operands) + shiftCountMask(Imm8, 32), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (shrdw memOffset( MemOff), MIdest:MInt, MIsrc:MInt, MIcount:MInt, .Operands) => . diff --git a/semantics/memoryInstructions/shrl_m32_imm8.k b/semantics/memoryInstructions/shrl_m32_imm8.k index 971f379f2..b45c71d28 100644 --- a/semantics/memoryInstructions/shrl_m32_imm8.k +++ b/semantics/memoryInstructions/shrl_m32_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SHRL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(shrl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(shrl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (shrl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shrl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (shrl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (shrl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (shrl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 32), + extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 32), MemOff, 32 ) @@ -25,17 +26,18 @@ module SHRL-M32-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 32, 33), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 32))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 32, 33), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 31, 32), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 25, 26), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 24, 25), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 31, 32), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 25, 26), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 24, 25), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 32), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 32), mi(32, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem32, mi(1, 0)), uvalueMInt(concatenateMInt( mi(25, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/shrq_m64_imm8.k b/semantics/memoryInstructions/shrq_m64_imm8.k index 476766193..24ad06c3a 100644 --- a/semantics/memoryInstructions/shrq_m64_imm8.k +++ b/semantics/memoryInstructions/shrq_m64_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SHRQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(shrq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(shrq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (shrq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shrq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (shrq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (shrq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (shrq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 64), + extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 64), MemOff, 64 ) @@ -25,17 +26,18 @@ module SHRQ-M64-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 64, 65), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 63)), mi(8, 64))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 64, 65), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 63, 64), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 57, 58), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 56, 57), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 63, 64), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 57, 58), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 56, 57), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 64), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 64), mi(64, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem64, mi(1, 0)), uvalueMInt(concatenateMInt( mi(57, 0), andMInt( Imm8, mi(8, 63))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1)) andBool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1)) andBool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 63)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/shrw_m16_imm8.k b/semantics/memoryInstructions/shrw_m16_imm8.k index a86573f61..04927fdac 100644 --- a/semantics/memoryInstructions/shrw_m16_imm8.k +++ b/semantics/memoryInstructions/shrw_m16_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SHRW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(shrw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(shrw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (shrw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (shrw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (shrw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (shrw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (shrw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 16), + extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 16), MemOff, 16 ) @@ -25,17 +26,18 @@ module SHRW-M16-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt ((ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 16, 17), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt ((ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16)) andBool (undefBool)) orBool ((notBool ugeMInt( andMInt( Imm8, mi(8, 31)), mi(8, 16))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 16, 17), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("CF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 15, 16), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 9, 10), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 8, 9), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (notBool (((((((eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 15, 16), mi(1, 1)) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 9, 10), mi(1, 1))) xorBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 8, 9), mi(1, 1))))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("PF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"AF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("AF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 16), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 16), mi(16, 0))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("ZF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"SF" |-> (#ifMInt (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool eqMInt( extractMInt( lshrMInt( concatenateMInt( Mem16, mi(1, 0)), uvalueMInt(concatenateMInt( mi(9, 0), andMInt( Imm8, mi(8, 31))))), 0, 1), mi(1, 1))) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("SF", RSMap), mi(1,1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"OF" |-> (#ifMInt ((eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1)) andBool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) orBool ((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( handleImmediateWithSignExtend(Imm8, 8, 8), mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1)) andBool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) orBool ((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 1))) andBool (((notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0))) andBool (undefBool)) orBool ((notBool (notBool eqMInt( andMInt( Imm8, mi(8, 31)), mi(8, 0)))) andBool eqMInt(getFlag("OF", RSMap), mi(1,1)))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/shufpd_xmm_m128_imm8.k b/semantics/memoryInstructions/shufpd_xmm_m128_imm8.k index 464bcd45f..761fdce69 100644 --- a/semantics/memoryInstructions/shufpd_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/shufpd_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module SHUFPD-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(shufpd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(shufpd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (shufpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (shufpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (shufpd Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (shufpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (shufpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( Mem128, 0, 64) #else extractMInt( Mem128, 64, 128) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R3, RSMap), 192, 256) #fi))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( Mem128, 0, 64) #else extractMInt( Mem128, 64, 128) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R3, RSMap), 192, 256) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/shufps_xmm_m128_imm8.k b/semantics/memoryInstructions/shufps_xmm_m128_imm8.k index 97946c5ec..c51379b39 100644 --- a/semantics/memoryInstructions/shufps_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/shufps_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module SHUFPS-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(shufps:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(shufps:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (shufps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (shufps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (shufps Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (shufps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (shufps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( Mem128, 0, 32) #else extractMInt( Mem128, 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( Mem128, 0, 32) #else extractMInt( Mem128, 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( Mem128, 0, 32) #else extractMInt( Mem128, 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( Mem128, 0, 32) #else extractMInt( Mem128, 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/subb_m8_imm8.k b/semantics/memoryInstructions/subb_m8_imm8.k index d20f17076..a33f9a8b6 100644 --- a/semantics/memoryInstructions/subb_m8_imm8.k +++ b/semantics/memoryInstructions/subb_m8_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SUBB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(subb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(subb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (subb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (subb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (subb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (subb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (subb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 9), + extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 9), MemOff, 8 ) @@ -25,17 +26,18 @@ module SUBB-M8-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 8, 9), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 7, 8), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 6, 7), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 5, 6), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 4, 5), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 3, 4), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 2, 3), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem8, 3, 4)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 4, 5)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem8, 3, 4)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 4, 5)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 9), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem8, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm8, 8, 8))), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem8, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm8, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm8)), mi(9, 1)), concatenateMInt( mi(1, 0), Mem8)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/subl_m32_imm32.k b/semantics/memoryInstructions/subl_m32_imm32.k index 8a939714d..0c9d0d0c1 100644 --- a/semantics/memoryInstructions/subl_m32_imm32.k +++ b/semantics/memoryInstructions/subl_m32_imm32.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SUBL-M32-IMM32 imports X86-CONFIGURATION - context execinstr(subl:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(subl:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (subl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (subl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (subl Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (subl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (subl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 33), + extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 33), MemOff, 32 ) @@ -25,17 +26,18 @@ module SUBL-M32-IMM32 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm32, 32, 32))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm32, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm32)), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/subl_m32_imm8.k b/semantics/memoryInstructions/subl_m32_imm8.k index f59e7d68a..31ff4f755 100644 --- a/semantics/memoryInstructions/subl_m32_imm8.k +++ b/semantics/memoryInstructions/subl_m32_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SUBL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(subl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(subl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (subl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (subl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (subl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (subl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (subl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 33), + extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 33), MemOff, 32 ) @@ -25,17 +26,18 @@ module SUBL-M32-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 32, 33), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 31, 32), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 30, 31), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 29, 30), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 27, 28), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 26, 27), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 25, 26), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem32, 27, 28)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 28, 29)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 33), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem32, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(32, svalueMInt(Imm8)))), mi(33, 1)), concatenateMInt( mi(1, 0), Mem32)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/subq_m64_imm32.k b/semantics/memoryInstructions/subq_m64_imm32.k index 426fb7c3c..358e84cf9 100644 --- a/semantics/memoryInstructions/subq_m64_imm32.k +++ b/semantics/memoryInstructions/subq_m64_imm32.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SUBQ-M64-IMM32 imports X86-CONFIGURATION - context execinstr(subq:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(subq:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (subq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (subq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (subq Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (subq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (subq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 65), + extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 65), MemOff, 64 ) @@ -25,17 +26,18 @@ module SUBQ-M64-IMM32 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm32, 27, 28), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm32)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/subq_m64_imm8.k b/semantics/memoryInstructions/subq_m64_imm8.k index 60c284973..e890fec12 100644 --- a/semantics/memoryInstructions/subq_m64_imm8.k +++ b/semantics/memoryInstructions/subq_m64_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SUBQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(subq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(subq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (subq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (subq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (subq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (subq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (subq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 65), + extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 65), MemOff, 64 ) @@ -25,17 +26,18 @@ module SUBQ-M64-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 64, 65), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 63, 64), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 62, 63), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 61, 62), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 59, 60), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 58, 59), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 57, 58), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem64, 59, 60)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 60, 61)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 65), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem64, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(64, svalueMInt(Imm8)))), mi(65, 1)), concatenateMInt( mi(1, 0), Mem64)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/subw_m16_imm16.k b/semantics/memoryInstructions/subw_m16_imm16.k index fe95e04b7..f2c0ed3da 100644 --- a/semantics/memoryInstructions/subw_m16_imm16.k +++ b/semantics/memoryInstructions/subw_m16_imm16.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SUBW-M16-IMM16 imports X86-CONFIGURATION - context execinstr(subw:Opcode Imm16:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(subw:Opcode Imm16:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (subw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (subw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (subw Imm16, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm16) ==Int 16 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (subw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (subw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 17), + extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 17), MemOff, 16 ) @@ -25,17 +26,18 @@ module SUBW-M16-IMM16 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm16, 11, 12), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( handleImmediateWithSignExtend(Imm16, 16, 16))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( Imm16, 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( Imm16)), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/memoryInstructions/subw_m16_imm8.k b/semantics/memoryInstructions/subw_m16_imm8.k index 67a007e25..b791b6e34 100644 --- a/semantics/memoryInstructions/subw_m16_imm8.k +++ b/semantics/memoryInstructions/subw_m16_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module SUBW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(subw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(subw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (subw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (subw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (subw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (subw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (subw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 17), + extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 17), MemOff, 16 ) @@ -25,17 +26,18 @@ module SUBW-M16-IMM8 ... RSMap:Map => updateMap(RSMap, -"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +"CF" |-> (#ifMInt (notBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 0, 1), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 16, 17), mi(1, 1)) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 15, 16), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 14, 15), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 13, 14), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 11, 12), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 10, 11), mi(1, 1))) xorBool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 9, 10), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) -"AF" |-> xorMInt( xorMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) +"AF" |-> xorMInt( xorMInt( extractMInt( Imm8, 3, 4), extractMInt( Mem16, 11, 12)), extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 12, 13)) -"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 17), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2) +"SF" |-> extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2) -"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) +"OF" |-> (#ifMInt ((eqMInt( negMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( Mem16, 0, 1), mi(1, 1))) andBool (notBool (eqMInt( negMInt( extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)), mi(1, 1)) ==Bool eqMInt( extractMInt( addMInt( addMInt( concatenateMInt( mi(1, 0), negMInt( mi(16, svalueMInt(Imm8)))), mi(17, 1)), concatenateMInt( mi(1, 0), Mem16)), 1, 2), mi(1, 1))))) #then mi(1, 1) #else mi(1, 0) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/testb_m8_imm8.k b/semantics/memoryInstructions/testb_m8_imm8.k index 9ebbc5ec5..57fe23957 100644 --- a/semantics/memoryInstructions/testb_m8_imm8.k +++ b/semantics/memoryInstructions/testb_m8_imm8.k @@ -4,32 +4,34 @@ requires "x86-configuration.k" module TESTB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(testb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(testb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (testb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (testb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (testb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (testb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (testb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => . ... RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem8, 7, 8), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem8, 6, 7), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 5, 6), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 4, 5), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 3, 4), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 2, 3), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 1, 2), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem8, 7, 8), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem8, 6, 7), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 5, 6), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 4, 5), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 3, 4), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 2, 3), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 1, 2), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem8, 0, 1), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( Mem8, handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( Mem8, Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( Mem8, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> andMInt( extractMInt( Mem8, 0, 1), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/testl_m32_imm32.k b/semantics/memoryInstructions/testl_m32_imm32.k index f3584f5f9..c99574ca6 100644 --- a/semantics/memoryInstructions/testl_m32_imm32.k +++ b/semantics/memoryInstructions/testl_m32_imm32.k @@ -4,32 +4,34 @@ requires "x86-configuration.k" module TESTL-M32-IMM32 imports X86-CONFIGURATION - context execinstr(testl:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(testl:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (testl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (testl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (testl Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (testl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (testl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => . ... RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem32, 31, 32), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem32, 30, 31), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 29, 30), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 28, 29), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 27, 28), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 26, 27), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 25, 26), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 24, 25), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem32, 31, 32), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem32, 30, 31), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 29, 30), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 28, 29), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 27, 28), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 26, 27), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 25, 26), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem32, 24, 25), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( Mem32, handleImmediateWithSignExtend(Imm32, 32, 32)), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( Mem32, Imm32), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( Mem32, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)) +"SF" |-> andMInt( extractMInt( Mem32, 0, 1), extractMInt( Imm32, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/testq_m64_imm32.k b/semantics/memoryInstructions/testq_m64_imm32.k index 5058291c1..6f173a07d 100644 --- a/semantics/memoryInstructions/testq_m64_imm32.k +++ b/semantics/memoryInstructions/testq_m64_imm32.k @@ -4,32 +4,34 @@ requires "x86-configuration.k" module TESTQ-M64-IMM32 imports X86-CONFIGURATION - context execinstr(testq:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(testq:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (testq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (testq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (testq Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (testq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (testq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => . ... RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem64, 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem64, 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem64, 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem64, 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem64, 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( Mem64, mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( Mem64, mi(64, svalueMInt(Imm32))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( Mem64, 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)) +"SF" |-> andMInt( extractMInt( Mem64, 0, 1), extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/testw_m16_imm16.k b/semantics/memoryInstructions/testw_m16_imm16.k index 03e992232..a901cfbcd 100644 --- a/semantics/memoryInstructions/testw_m16_imm16.k +++ b/semantics/memoryInstructions/testw_m16_imm16.k @@ -4,32 +4,34 @@ requires "x86-configuration.k" module TESTW-M16-IMM16 imports X86-CONFIGURATION - context execinstr(testw:Opcode Imm16:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(testw:Opcode Imm16:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (testw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (testw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (testw Imm16, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm16) ==Int 16 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (testw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (testw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => . ... RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem16, 15, 16), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 15, 16)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem16, 14, 15), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 14, 15)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 13, 14), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 13, 14)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 12, 13), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 12, 13)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 11, 12), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 10, 11), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 10, 11)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 9, 10), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 9, 10)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 8, 9), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( andMInt( extractMInt( Mem16, 15, 16), extractMInt( Imm16, 15, 16)), mi(1, 1)) xorBool eqMInt( andMInt( extractMInt( Mem16, 14, 15), extractMInt( Imm16, 14, 15)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 13, 14), extractMInt( Imm16, 13, 14)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 12, 13), extractMInt( Imm16, 12, 13)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 11, 12), extractMInt( Imm16, 11, 12)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 10, 11), extractMInt( Imm16, 10, 11)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 9, 10), extractMInt( Imm16, 9, 10)), mi(1, 1))) xorBool eqMInt( andMInt( extractMInt( Mem16, 8, 9), extractMInt( Imm16, 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( andMInt( Mem16, handleImmediateWithSignExtend(Imm16, 16, 16)), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( andMInt( Mem16, Imm16), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> andMInt( extractMInt( Mem16, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)) +"SF" |-> andMInt( extractMInt( Mem16, 0, 1), extractMInt( Imm16, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/memoryInstructions/vblendpd_xmm_xmm_m128_imm8.k b/semantics/memoryInstructions/vblendpd_xmm_xmm_m128_imm8.k index ed8791ad7..4283994a4 100644 --- a/semantics/memoryInstructions/vblendpd_xmm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vblendpd_xmm_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VBLENDPD-XMM-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vblendpd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vblendpd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vblendpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vblendpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vblendpd Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vblendpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vblendpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( Mem128, 0, 64) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 256) #else extractMInt( Mem128, 64, 128) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( Mem128, 0, 64) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 256) #else extractMInt( Mem128, 64, 128) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vblendpd_ymm_ymm_m256_imm8.k b/semantics/memoryInstructions/vblendpd_ymm_ymm_m256_imm8.k index e889d3d3d..242024e71 100644 --- a/semantics/memoryInstructions/vblendpd_ymm_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vblendpd_ymm_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VBLENDPD-YMM-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vblendpd:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] + context execinstr(vblendpd:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vblendpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vblendpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vblendpd Imm8, memOffset( MemOff), R3:Ymm, R4:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vblendpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vblendpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 64) #else extractMInt( Mem256, 0, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 128) #else extractMInt( Mem256, 64, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( Mem256, 128, 192) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 256) #else extractMInt( Mem256, 192, 256) #fi)))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 64) #else extractMInt( Mem256, 0, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 128) #else extractMInt( Mem256, 64, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( Mem256, 128, 192) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 256) #else extractMInt( Mem256, 192, 256) #fi)))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vblendps_xmm_xmm_m128_imm8.k b/semantics/memoryInstructions/vblendps_xmm_xmm_m128_imm8.k index d1f1ab93a..47def516b 100644 --- a/semantics/memoryInstructions/vblendps_xmm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vblendps_xmm_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VBLENDPS-XMM-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vblendps:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vblendps:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vblendps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vblendps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vblendps Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vblendps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vblendps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( Mem128, 0, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( Mem128, 32, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( Mem128, 64, 96) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( Mem128, 96, 128) #fi))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( Mem128, 0, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( Mem128, 32, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( Mem128, 64, 96) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( Mem128, 96, 128) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vblendps_ymm_ymm_m256_imm8.k b/semantics/memoryInstructions/vblendps_ymm_ymm_m256_imm8.k index d386aeb48..b346a3093 100644 --- a/semantics/memoryInstructions/vblendps_ymm_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vblendps_ymm_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VBLENDPS-YMM-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vblendps:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] + context execinstr(vblendps:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vblendps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vblendps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vblendps Imm8, memOffset( MemOff), R3:Ymm, R4:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vblendps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vblendps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( Mem256, 0, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( Mem256, 32, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 96) #else extractMInt( Mem256, 64, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 96, 128) #else extractMInt( Mem256, 96, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( Mem256, 128, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( Mem256, 160, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( Mem256, 192, 224) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( Mem256, 224, 256) #fi)))))))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( Mem256, 0, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( Mem256, 32, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 96) #else extractMInt( Mem256, 64, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 96, 128) #else extractMInt( Mem256, 96, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( Mem256, 128, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( Mem256, 160, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( Mem256, 192, 224) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( Mem256, 224, 256) #fi)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vcmppd_xmm_xmm_m128_imm8.k b/semantics/memoryInstructions/vcmppd_xmm_xmm_m128_imm8.k index 8d785b0de..bea305dd9 100644 --- a/semantics/memoryInstructions/vcmppd_xmm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vcmppd_xmm_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VCMPPD-XMM-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vcmppd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vcmppd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vcmppd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vcmppd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vcmppd Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vcmppd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vcmppd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( Mem128, 0, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( Mem128, 64, 128), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( Mem128, 0, 64), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( Mem128, 64, 128), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vcmppd_ymm_ymm_m256_imm8.k b/semantics/memoryInstructions/vcmppd_ymm_ymm_m256_imm8.k index 8366dc03d..c31681d35 100644 --- a/semantics/memoryInstructions/vcmppd_ymm_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vcmppd_ymm_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VCMPPD-YMM-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vcmppd:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] + context execinstr(vcmppd:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vcmppd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vcmppd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vcmppd Imm8, memOffset( MemOff), R3:Ymm, R4:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vcmppd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vcmppd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 0, 64), extractMInt( Mem256, 0, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 64, 128), extractMInt( Mem256, 64, 128), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( Mem256, 128, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( Mem256, 192, 256), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi)))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 0, 64), extractMInt( Mem256, 0, 64), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 64, 128), extractMInt( Mem256, 64, 128), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( Mem256, 128, 192), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( Mem256, 192, 256), Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi)))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vcmpps_xmm_xmm_m128_imm8.k b/semantics/memoryInstructions/vcmpps_xmm_xmm_m128_imm8.k index cc4f2e0c1..c88249a4e 100644 --- a/semantics/memoryInstructions/vcmpps_xmm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vcmpps_xmm_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VCMPPS-XMM-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vcmpps:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vcmpps:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vcmpps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vcmpps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vcmpps Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vcmpps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vcmpps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vcmpps_ymm_ymm_m256_imm8.k b/semantics/memoryInstructions/vcmpps_ymm_ymm_m256_imm8.k index 3d32d8c9c..7f735164b 100644 --- a/semantics/memoryInstructions/vcmpps_ymm_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vcmpps_ymm_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VCMPPS-YMM-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vcmpps:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] + context execinstr(vcmpps:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vcmpps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vcmpps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vcmpps Imm8, memOffset( MemOff), R3:Ymm, R4:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vcmpps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vcmpps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( Mem256, 0, 32), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( Mem256, 32, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( Mem256, 64, 96), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( Mem256, 96, 128), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem256, 128, 160), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem256, 160, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem256, 192, 224), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem256, 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi)))))))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( Mem256, 0, 32), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( Mem256, 32, 64), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( Mem256, 64, 96), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( Mem256, 96, 128), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem256, 128, 160), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem256, 160, 192), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), concatenateMInt( (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem256, 192, 224), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem256, 224, 256), Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vcmpsd_xmm_xmm_m64_imm8.k b/semantics/memoryInstructions/vcmpsd_xmm_xmm_m64_imm8.k index 674c8a278..878e37b39 100644 --- a/semantics/memoryInstructions/vcmpsd_xmm_xmm_m64_imm8.k +++ b/semantics/memoryInstructions/vcmpsd_xmm_xmm_m64_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VCMPSD-XMM-XMM-M64-IMM8 imports X86-CONFIGURATION - context execinstr(vcmpsd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vcmpsd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vcmpsd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vcmpsd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (vcmpsd Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (vcmpsd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (vcmpsd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 192), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), Mem64, handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 192), (#ifMInt eqMInt( cmp_double_pred(extractMInt( getParentValue(R3, RSMap), 192, 256), Mem64, Imm8), mi(1, 1)) #then mi(64, 18446744073709551615) #else mi(64, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vcmpss_xmm_xmm_m32_imm8.k b/semantics/memoryInstructions/vcmpss_xmm_xmm_m32_imm8.k index fee669aa4..5722e531c 100644 --- a/semantics/memoryInstructions/vcmpss_xmm_xmm_m32_imm8.k +++ b/semantics/memoryInstructions/vcmpss_xmm_xmm_m32_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VCMPSS-XMM-XMM-M32-IMM8 imports X86-CONFIGURATION - context execinstr(vcmpss:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vcmpss:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vcmpss:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vcmpss:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (vcmpss Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (vcmpss:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (vcmpss:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 224), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), Mem32, handleImmediateWithSignExtend(Imm8, 8, 8)), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 224), (#ifMInt eqMInt( cmp_single_pred(extractMInt( getParentValue(R3, RSMap), 224, 256), Mem32, Imm8), mi(1, 1)) #then mi(32, 4294967295) #else mi(32, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vcvtps2ph_m128_ymm_imm8.k b/semantics/memoryInstructions/vcvtps2ph_m128_ymm_imm8.k index 6f287ad40..4d80b2d96 100644 --- a/semantics/memoryInstructions/vcvtps2ph_m128_ymm_imm8.k +++ b/semantics/memoryInstructions/vcvtps2ph_m128_ymm_imm8.k @@ -4,24 +4,26 @@ requires "x86-configuration.k" module VCVTPS2PH-M128-YMM-IMM8 imports X86-CONFIGURATION - context execinstr(vcvtps2ph:Opcode Imm8:Imm, R2:Ymm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(vcvtps2ph:Opcode Imm8:MInt, R2:Ymm, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (vcvtps2ph:Opcode Imm8:Imm, R2:Ymm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (vcvtps2ph:Opcode Imm8:MInt, R2:Ymm, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vcvtps2ph Imm8, R2:Ymm, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vcvtps2ph:Opcode Imm8:Imm, R2:Ymm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vcvtps2ph:Opcode Imm8:MInt, R2:Ymm, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 0, 32), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 32, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 64, 96), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 96, 128), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 128, 160), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 160, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 192, 224), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8))))))))), + concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 0, 32), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 32, 64), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 64, 96), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 96, 128), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 128, 160), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 160, 192), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 192, 224), Imm8), cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), Imm8)))))))), MemOff, 128 ) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vcvtps2ph_m64_xmm_imm8.k b/semantics/memoryInstructions/vcvtps2ph_m64_xmm_imm8.k index 34710e494..6e9b8503b 100644 --- a/semantics/memoryInstructions/vcvtps2ph_m64_xmm_imm8.k +++ b/semantics/memoryInstructions/vcvtps2ph_m64_xmm_imm8.k @@ -4,24 +4,26 @@ requires "x86-configuration.k" module VCVTPS2PH-M64-XMM-IMM8 imports X86-CONFIGURATION - context execinstr(vcvtps2ph:Opcode Imm8:Imm, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(vcvtps2ph:Opcode Imm8:MInt, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (vcvtps2ph:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (vcvtps2ph:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (vcvtps2ph Imm8, R2:Xmm, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (vcvtps2ph:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (vcvtps2ph:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 128, 160), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 160, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 192, 224), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8))))), + concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 128, 160), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 160, 192), Imm8), concatenateMInt( cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 192, 224), Imm8), cvt_single_to_fp16_rm(extractMInt( getParentValue(R2, RSMap), 224, 256), Imm8)))), MemOff, 64 ) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vdppd_xmm_xmm_m128_imm8.k b/semantics/memoryInstructions/vdppd_xmm_xmm_m128_imm8.k index 3083d42da..ee49b48a4 100644 --- a/semantics/memoryInstructions/vdppd_xmm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vdppd_xmm_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VDPPD-XMM-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vdppd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vdppd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vdppd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vdppd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vdppd Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vdppd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vdppd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( Mem128, 64, 128)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( Mem128, 0, 64)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( Mem128, 64, 128)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( Mem128, 0, 64)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( Mem128, 64, 128)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( Mem128, 0, 64)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then add_double((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 192, 256), extractMInt( Mem128, 64, 128)) #else mi(64, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_double(extractMInt( getParentValue(R3, RSMap), 128, 192), extractMInt( Mem128, 0, 64)) #else mi(64, 0) #fi)) #else mi(64, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vdpps_xmm_xmm_m128_imm8.k b/semantics/memoryInstructions/vdpps_xmm_xmm_m128_imm8.k index dec7b45d3..0558c9571 100644 --- a/semantics/memoryInstructions/vdpps_xmm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vdpps_xmm_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VDPPS-XMM-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vdpps:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vdpps:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vdpps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vdpps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vdpps Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vdpps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vdpps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem128, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem128, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem128, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem128, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vdpps_ymm_ymm_m256_imm8.k b/semantics/memoryInstructions/vdpps_ymm_ymm_m256_imm8.k index 6df7c4137..58a41a41b 100644 --- a/semantics/memoryInstructions/vdpps_ymm_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vdpps_ymm_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VDPPS-YMM-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vdpps:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] + context execinstr(vdpps:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vdpps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vdpps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vdpps Imm8, memOffset( MemOff), R3:Ymm, R4:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vdpps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vdpps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( Mem256, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( Mem256, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( Mem256, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( Mem256, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( Mem256, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( Mem256, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( Mem256, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( Mem256, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( Mem256, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( Mem256, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( Mem256, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( Mem256, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( Mem256, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( Mem256, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( Mem256, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( Mem256, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem256, 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem256, 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem256, 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem256, 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem256, 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem256, 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem256, 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem256, 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem256, 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem256, 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem256, 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem256, 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem256, 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem256, 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem256, 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem256, 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi))) +convToRegKeys(R4) |-> concatenateMInt( concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( Mem256, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( Mem256, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( Mem256, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( Mem256, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( Mem256, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( Mem256, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( Mem256, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( Mem256, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( Mem256, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( Mem256, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( Mem256, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( Mem256, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 96, 128), extractMInt( Mem256, 96, 128)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 64, 96), extractMInt( Mem256, 64, 96)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 32, 64), extractMInt( Mem256, 32, 64)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 0, 32), extractMInt( Mem256, 0, 32)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem256, 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem256, 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem256, 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem256, 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem256, 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem256, 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem256, 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem256, 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem256, 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem256, 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem256, 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem256, 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then add_single(add_single((#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 224, 256), extractMInt( Mem256, 224, 256)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 192, 224), extractMInt( Mem256, 192, 224)) #else mi(32, 0) #fi)), add_single((#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 160, 192), extractMInt( Mem256, 160, 192)) #else mi(32, 0) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then mul_single(extractMInt( getParentValue(R3, RSMap), 128, 160), extractMInt( Mem256, 128, 160)) #else mi(32, 0) #fi))) #else mi(32, 0) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vextractf128_m128_ymm_imm8.k b/semantics/memoryInstructions/vextractf128_m128_ymm_imm8.k index 270679406..d1fb6becd 100644 --- a/semantics/memoryInstructions/vextractf128_m128_ymm_imm8.k +++ b/semantics/memoryInstructions/vextractf128_m128_ymm_imm8.k @@ -4,24 +4,26 @@ requires "x86-configuration.k" module VEXTRACTF128-M128-YMM-IMM8 imports X86-CONFIGURATION - context execinstr(vextractf128:Opcode Imm8:Imm, R2:Ymm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(vextractf128:Opcode Imm8:MInt, R2:Ymm, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (vextractf128:Opcode Imm8:Imm, R2:Ymm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (vextractf128:Opcode Imm8:MInt, R2:Ymm, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vextractf128 Imm8, R2:Ymm, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vextractf128:Opcode Imm8:Imm, R2:Ymm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vextractf128:Opcode Imm8:MInt, R2:Ymm, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi), + (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi), MemOff, 128 ) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vextracti128_m128_ymm_imm8.k b/semantics/memoryInstructions/vextracti128_m128_ymm_imm8.k index edc4a4c40..56d8cf7c0 100644 --- a/semantics/memoryInstructions/vextracti128_m128_ymm_imm8.k +++ b/semantics/memoryInstructions/vextracti128_m128_ymm_imm8.k @@ -4,24 +4,26 @@ requires "x86-configuration.k" module VEXTRACTI128-M128-YMM-IMM8 imports X86-CONFIGURATION - context execinstr(vextracti128:Opcode Imm8:Imm, R2:Ymm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(vextracti128:Opcode Imm8:MInt, R2:Ymm, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (vextracti128:Opcode Imm8:Imm, R2:Ymm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (vextracti128:Opcode Imm8:MInt, R2:Ymm, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vextracti128 Imm8, R2:Ymm, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vextracti128:Opcode Imm8:Imm, R2:Ymm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vextracti128:Opcode Imm8:MInt, R2:Ymm, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi), + (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R2, RSMap), 128, 256) #else extractMInt( getParentValue(R2, RSMap), 0, 128) #fi), MemOff, 128 ) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vextractps_m32_xmm_imm8.k b/semantics/memoryInstructions/vextractps_m32_xmm_imm8.k index 0e7977b47..fadb3b7b6 100644 --- a/semantics/memoryInstructions/vextractps_m32_xmm_imm8.k +++ b/semantics/memoryInstructions/vextractps_m32_xmm_imm8.k @@ -4,24 +4,26 @@ requires "x86-configuration.k" module VEXTRACTPS-M32-XMM-IMM8 imports X86-CONFIGURATION - context execinstr(vextractps:Opcode Imm8:Imm, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(vextractps:Opcode Imm8:MInt, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (vextractps:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (vextractps:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (vextractps Imm8, R2:Xmm, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (vextractps:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (vextractps:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128), + extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128), MemOff, 32 ) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vinsertf128_ymm_ymm_m128_imm8.k b/semantics/memoryInstructions/vinsertf128_ymm_ymm_m128_imm8.k index d07b6a84e..97acdb03b 100644 --- a/semantics/memoryInstructions/vinsertf128_ymm_ymm_m128_imm8.k +++ b/semantics/memoryInstructions/vinsertf128_ymm_ymm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VINSERTF128-YMM-YMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vinsertf128:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] + context execinstr(vinsertf128:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vinsertf128:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vinsertf128:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vinsertf128 Imm8, memOffset( MemOff), R3:Ymm, R4:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vinsertf128:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vinsertf128:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), Mem128) #else concatenateMInt( Mem128, extractMInt( getParentValue(R3, RSMap), 128, 256)) #fi) +convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), Mem128) #else concatenateMInt( Mem128, extractMInt( getParentValue(R3, RSMap), 128, 256)) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vinserti128_ymm_ymm_m128_imm8.k b/semantics/memoryInstructions/vinserti128_ymm_ymm_m128_imm8.k index a978ac780..a7aef1819 100644 --- a/semantics/memoryInstructions/vinserti128_ymm_ymm_m128_imm8.k +++ b/semantics/memoryInstructions/vinserti128_ymm_ymm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VINSERTI128-YMM-YMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vinserti128:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] + context execinstr(vinserti128:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vinserti128:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vinserti128:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vinserti128 Imm8, memOffset( MemOff), R3:Ymm, R4:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vinserti128:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vinserti128:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), Mem128) #else concatenateMInt( Mem128, extractMInt( getParentValue(R3, RSMap), 128, 256)) #fi) +convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), Mem128) #else concatenateMInt( Mem128, extractMInt( getParentValue(R3, RSMap), 128, 256)) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vinsertps_xmm_xmm_m32_imm8.k b/semantics/memoryInstructions/vinsertps_xmm_xmm_m32_imm8.k index 9f9673cd7..543d56dda 100644 --- a/semantics/memoryInstructions/vinsertps_xmm_xmm_m32_imm8.k +++ b/semantics/memoryInstructions/vinsertps_xmm_xmm_m32_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VINSERTPS-XMM-XMM-M32-IMM8 imports X86-CONFIGURATION - context execinstr(vinsertps:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vinsertps:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vinsertps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vinsertps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (vinsertps Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (vinsertps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (vinsertps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else Mem32 #fi) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then Mem32 #else extractMInt( getParentValue(R3, RSMap), 160, 192) #fi) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then Mem32 #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then Mem32 #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( concatenateMInt( concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else Mem32 #fi) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then Mem32 #else extractMInt( getParentValue(R3, RSMap), 160, 192) #fi) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then Mem32 #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #fi) #fi)), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then mi(32, 0) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then Mem32 #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vmpsadbw_xmm_xmm_m128_imm8.k b/semantics/memoryInstructions/vmpsadbw_xmm_xmm_m128_imm8.k index 2f4425bda..30a167788 100644 --- a/semantics/memoryInstructions/vmpsadbw_xmm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vmpsadbw_xmm_xmm_m128_imm8.k @@ -13,43 +13,44 @@ module VMPSADBW-XMM-XMM-M128-IMM8 rule memLoadValue(MemVal:MInt):MemLoadValue ~> - execinstr (vmpsadbw Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vmpsadbw Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => execinstr (vmpsadbw selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 7 , 0 ), + extractMInt(Imm8, 6, 8), 7 , 0 ), selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 15, 8 ), + extractMInt(Imm8, 6, 8), 15, 8 ), selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 23, 16), + extractMInt(Imm8, 6, 8), 23, 16), selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 31, 24), + extractMInt(Imm8, 6, 8), 31, 24), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 7 , 0), + extractMInt(Imm8, 5, 6), 7 , 0), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 15, 8), + extractMInt(Imm8, 5, 6), 15, 8), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 23, 16), + extractMInt(Imm8, 5, 6), 23, 16), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 31, 24), + extractMInt(Imm8, 5, 6), 31, 24), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 39, 32), + extractMInt(Imm8, 5, 6), 39, 32), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 47, 40), + extractMInt(Imm8, 5, 6), 47, 40), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 55, 48), + extractMInt(Imm8, 5, 6), 55, 48), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 63, 56), + extractMInt(Imm8, 5, 6), 63, 56), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 71, 64), + extractMInt(Imm8, 5, 6), 71, 64), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 79, 72), + extractMInt(Imm8, 5, 6), 79, 72), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 87, 80), + extractMInt(Imm8, 5, 6), 87, 80), R3:Xmm, .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (vmpsadbw diff --git a/semantics/memoryInstructions/vmpsadbw_ymm_ymm_m256_imm8.k b/semantics/memoryInstructions/vmpsadbw_ymm_ymm_m256_imm8.k index 6f5ecf59f..e196b0265 100644 --- a/semantics/memoryInstructions/vmpsadbw_ymm_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vmpsadbw_ymm_ymm_m256_imm8.k @@ -14,93 +14,94 @@ module VMPSADBW-YMM-YMM-M256-IMM8 rule memLoadValue(MemVal:MInt):MemLoadValue ~> - execinstr (vmpsadbw Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vmpsadbw Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => execinstr (vmpsadbw //Low slices selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 7 , 0 ), + extractMInt(Imm8, 6, 8), 7 , 0 ), selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 15, 8 ), + extractMInt(Imm8, 6, 8), 15, 8 ), selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 23, 16), + extractMInt(Imm8, 6, 8), 23, 16), selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), 31, 24), + extractMInt(Imm8, 6, 8), 31, 24), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 7 , 0), + extractMInt(Imm8, 5, 6), 7 , 0), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 15, 8), + extractMInt(Imm8, 5, 6), 15, 8), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 23, 16), + extractMInt(Imm8, 5, 6), 23, 16), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 31, 24), + extractMInt(Imm8, 5, 6), 31, 24), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 39, 32), + extractMInt(Imm8, 5, 6), 39, 32), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 47, 40), + extractMInt(Imm8, 5, 6), 47, 40), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 55, 48), + extractMInt(Imm8, 5, 6), 55, 48), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 63, 56), + extractMInt(Imm8, 5, 6), 63, 56), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 71, 64), + extractMInt(Imm8, 5, 6), 71, 64), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 79, 72), + extractMInt(Imm8, 5, 6), 79, 72), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), 87, 80), + extractMInt(Imm8, 5, 6), 87, 80), //High slices selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 3, 5), 7 +Int + extractMInt(Imm8, 3, 5), 7 +Int 128, 0 +Int 128), selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 3, 5), 15+Int + extractMInt(Imm8, 3, 5), 15+Int 128, 8 +Int 128), selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 3, 5), 23+Int + extractMInt(Imm8, 3, 5), 23+Int 128, 16+Int 128), selectSliceMPSAD(MemVal, - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 3, 5), 31+Int + extractMInt(Imm8, 3, 5), 31+Int 128, 24+Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 7 + extractMInt(Imm8, 2, 3), 7 +Int 128, 0 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 15 + extractMInt(Imm8, 2, 3), 15 +Int 128, 8 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 23 + extractMInt(Imm8, 2, 3), 23 +Int 128, 16 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 31 + extractMInt(Imm8, 2, 3), 31 +Int 128, 24 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 39 + extractMInt(Imm8, 2, 3), 39 +Int 128, 32 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 47 + extractMInt(Imm8, 2, 3), 47 +Int 128, 40 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 55 + extractMInt(Imm8, 2, 3), 55 +Int 128, 48 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 63 + extractMInt(Imm8, 2, 3), 63 +Int 128, 56 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 71 + extractMInt(Imm8, 2, 3), 71 +Int 128, 64 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 79 + extractMInt(Imm8, 2, 3), 79 +Int 128, 72 +Int 128), selectSliceMPSAD(getRegisterValue(R3, RSMap), - extractMInt(handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), 87 + extractMInt(Imm8, 2, 3), 87 +Int 128, 80 +Int 128), R4:Ymm, .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule diff --git a/semantics/memoryInstructions/vpalignr_xmm_xmm_m128_imm8.k b/semantics/memoryInstructions/vpalignr_xmm_xmm_m128_imm8.k index 673f8b7c3..cd2fab0fa 100644 --- a/semantics/memoryInstructions/vpalignr_xmm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vpalignr_xmm_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPALIGNR-XMM-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vpalignr:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpalignr:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpalignr:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vpalignr:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vpalignr Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpalignr:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpalignr:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), Mem128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), uvalueMInt(mi(256, 3))))), 128, 256)) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), Mem128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), Imm8), uvalueMInt(mi(256, 3))))), 128, 256)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpalignr_ymm_ymm_m256_imm8.k b/semantics/memoryInstructions/vpalignr_ymm_ymm_m256_imm8.k index d0fef964e..b3a5c2aff 100644 --- a/semantics/memoryInstructions/vpalignr_ymm_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vpalignr_ymm_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPALIGNR-YMM-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vpalignr:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] + context execinstr(vpalignr:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vpalignr:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vpalignr:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vpalignr Imm8, memOffset( MemOff), R3:Ymm, R4:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpalignr:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpalignr:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), extractMInt( Mem256, 0, 128)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), uvalueMInt(mi(256, 3))))), 128, 256), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), extractMInt( Mem256, 128, 256)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), handleImmediateWithSignExtend(Imm8, 8, 8)), uvalueMInt(mi(256, 3))))), 128, 256)) +convToRegKeys(R4) |-> concatenateMInt( extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 0, 128), extractMInt( Mem256, 0, 128)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), Imm8), uvalueMInt(mi(256, 3))))), 128, 256), extractMInt( lshrMInt( concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), extractMInt( Mem256, 128, 256)), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(248, 0), Imm8), uvalueMInt(mi(256, 3))))), 128, 256)) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpblendd_xmm_xmm_m128_imm8.k b/semantics/memoryInstructions/vpblendd_xmm_xmm_m128_imm8.k index 0c3aba64f..25d243aca 100644 --- a/semantics/memoryInstructions/vpblendd_xmm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vpblendd_xmm_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPBLENDD-XMM-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vpblendd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpblendd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpblendd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vpblendd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vpblendd Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpblendd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpblendd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( Mem128, 0, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( Mem128, 32, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( Mem128, 64, 96) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( Mem128, 96, 128) #fi))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( Mem128, 0, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( Mem128, 32, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( Mem128, 64, 96) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( Mem128, 96, 128) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpblendd_ymm_ymm_m256_imm8.k b/semantics/memoryInstructions/vpblendd_ymm_ymm_m256_imm8.k index 277454262..d1088492b 100644 --- a/semantics/memoryInstructions/vpblendd_ymm_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vpblendd_ymm_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPBLENDD-YMM-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vpblendd:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] + context execinstr(vpblendd:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vpblendd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vpblendd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vpblendd Imm8, memOffset( MemOff), R3:Ymm, R4:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpblendd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpblendd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( Mem256, 0, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( Mem256, 32, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 96) #else extractMInt( Mem256, 64, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 96, 128) #else extractMInt( Mem256, 96, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( Mem256, 128, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( Mem256, 160, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( Mem256, 192, 224) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( Mem256, 224, 256) #fi)))))))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( Mem256, 0, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( Mem256, 32, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 96) #else extractMInt( Mem256, 64, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 96, 128) #else extractMInt( Mem256, 96, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( Mem256, 128, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( Mem256, 160, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 224) #else extractMInt( Mem256, 192, 224) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 256) #else extractMInt( Mem256, 224, 256) #fi)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpblendw_xmm_xmm_m128_imm8.k b/semantics/memoryInstructions/vpblendw_xmm_xmm_m128_imm8.k index b32352650..d076858e6 100644 --- a/semantics/memoryInstructions/vpblendw_xmm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vpblendw_xmm_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPBLENDW-XMM-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vpblendw:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpblendw:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpblendw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vpblendw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vpblendw Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpblendw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpblendw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 144) #else extractMInt( Mem128, 0, 16) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 144, 160) #else extractMInt( Mem128, 16, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 176) #else extractMInt( Mem128, 32, 48) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 176, 192) #else extractMInt( Mem128, 48, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 208) #else extractMInt( Mem128, 64, 80) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 208, 224) #else extractMInt( Mem128, 80, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 240) #else extractMInt( Mem128, 96, 112) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 240, 256) #else extractMInt( Mem128, 112, 128) #fi))))))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 144) #else extractMInt( Mem128, 0, 16) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 144, 160) #else extractMInt( Mem128, 16, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 176) #else extractMInt( Mem128, 32, 48) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 176, 192) #else extractMInt( Mem128, 48, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 208) #else extractMInt( Mem128, 64, 80) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 208, 224) #else extractMInt( Mem128, 80, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 240) #else extractMInt( Mem128, 96, 112) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 240, 256) #else extractMInt( Mem128, 112, 128) #fi))))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpblendw_ymm_ymm_m256_imm8.k b/semantics/memoryInstructions/vpblendw_ymm_ymm_m256_imm8.k index 194bee6b5..06c48df3d 100644 --- a/semantics/memoryInstructions/vpblendw_ymm_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vpblendw_ymm_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPBLENDW-YMM-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vpblendw:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] + context execinstr(vpblendw:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vpblendw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vpblendw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vpblendw Imm8, memOffset( MemOff), R3:Ymm, R4:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpblendw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpblendw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 16) #else extractMInt( Mem256, 0, 16) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 16, 32) #else extractMInt( Mem256, 16, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 32, 48) #else extractMInt( Mem256, 32, 48) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 48, 64) #else extractMInt( Mem256, 48, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 80) #else extractMInt( Mem256, 64, 80) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 80, 96) #else extractMInt( Mem256, 80, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 96, 112) #else extractMInt( Mem256, 96, 112) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 112, 128) #else extractMInt( Mem256, 112, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 144) #else extractMInt( Mem256, 128, 144) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 144, 160) #else extractMInt( Mem256, 144, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 176) #else extractMInt( Mem256, 160, 176) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 176, 192) #else extractMInt( Mem256, 176, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 208) #else extractMInt( Mem256, 192, 208) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 208, 224) #else extractMInt( Mem256, 208, 224) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 240) #else extractMInt( Mem256, 224, 240) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 240, 256) #else extractMInt( Mem256, 240, 256) #fi)))))))))))))))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 0, 16) #else extractMInt( Mem256, 0, 16) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 16, 32) #else extractMInt( Mem256, 16, 32) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 32, 48) #else extractMInt( Mem256, 32, 48) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 48, 64) #else extractMInt( Mem256, 48, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 64, 80) #else extractMInt( Mem256, 64, 80) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 80, 96) #else extractMInt( Mem256, 80, 96) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 96, 112) #else extractMInt( Mem256, 96, 112) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 112, 128) #else extractMInt( Mem256, 112, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 144) #else extractMInt( Mem256, 128, 144) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 144, 160) #else extractMInt( Mem256, 144, 160) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 160, 176) #else extractMInt( Mem256, 160, 176) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 176, 192) #else extractMInt( Mem256, 176, 192) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 192, 208) #else extractMInt( Mem256, 192, 208) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 208, 224) #else extractMInt( Mem256, 208, 224) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 224, 240) #else extractMInt( Mem256, 224, 240) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( getParentValue(R3, RSMap), 240, 256) #else extractMInt( Mem256, 240, 256) #fi)))))))))))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpclmulqdq_xmm_xmm_m128_imm8.k b/semantics/memoryInstructions/vpclmulqdq_xmm_xmm_m128_imm8.k index 743703713..4e8bec553 100644 --- a/semantics/memoryInstructions/vpclmulqdq_xmm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vpclmulqdq_xmm_xmm_m128_imm8.k @@ -25,15 +25,14 @@ module VPCLMULQDQ-XMM-XMM-M128-IMM8 */ rule memLoadValue(MemVal:MInt):MemLoadValue ~> - execinstr (vpclmulqdq Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vpclmulqdq Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => execinstr(vpclmulqdq - selectSlice(getRegisterValue(R3, RSMap), handleImmediateWithSignExtend(Imm8, - 8, 8), 7, 64, 0), - selectSlice(MemVal, handleImmediateWithSignExtend(Imm8, - 8, 8), 3, 64, 0), R4 + selectSlice(getRegisterValue(R3, RSMap), Imm8, 7, 64, 0), + selectSlice(MemVal, Imm8, 3, 64, 0), R4 , .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule execinstr (vpclmulqdq TEMP1:MInt, TEMP2:MInt, R4:Xmm, .Operands) => diff --git a/semantics/memoryInstructions/vpcmpestri_xmm_m128_imm8.k b/semantics/memoryInstructions/vpcmpestri_xmm_m128_imm8.k index e04fd30e8..f878aa16a 100644 --- a/semantics/memoryInstructions/vpcmpestri_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vpcmpestri_xmm_m128_imm8.k @@ -4,27 +4,28 @@ requires "x86-configuration.k" module VPCMPESTRI-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vpcmpestri:Opcode Imm8:Imm, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpcmpestri:Opcode Imm8:MInt, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpcmpestri:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => + execinstr (vpcmpestri:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vpcmpestri Imm8, memOffset( MemOff), Xmm1, .Operands) ... - + requires bitwidthMInt(Imm8) ==Int 8 // Find Limit Index rule memLoadValue(Mem128:MInt):MemLoadValue ~> - execinstr (vpcmpestri Imm8:Imm, memOffset( MemOff), Xmm1:Xmm, .Operands) => + execinstr (vpcmpestri Imm8:MInt, memOffset( MemOff), Xmm1:Xmm, .Operands) => execinstr (vpcmpestri - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, Mem128, getRegisterValue(Xmm1, RSMap), - findLimitIndexE(Mem128, getRegisterValue(%rdx, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexE(Mem128, getRegisterValue(%rdx, RSMap), Imm8), + findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // Find data size and interpretation rule diff --git a/semantics/memoryInstructions/vpcmpestrm_xmm_m128_imm8.k b/semantics/memoryInstructions/vpcmpestrm_xmm_m128_imm8.k index 94bf1d1a2..9c5f2e32e 100644 --- a/semantics/memoryInstructions/vpcmpestrm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vpcmpestrm_xmm_m128_imm8.k @@ -4,26 +4,27 @@ requires "x86-configuration.k" module VPCMPESTRM-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vpcmpestrm:Opcode Imm8:Imm, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpcmpestrm:Opcode Imm8:MInt, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpcmpestrm:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => + execinstr (vpcmpestrm:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vpcmpestrm Imm8, memOffset( MemOff), Xmm1, .Operands) ... - + requires bitwidthMInt(Imm8) ==Int 8 // Find Limit Index rule memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpcmpestrm Imm8, memOffset( MemOff), Xmm1, .Operands) => execinstr (vpcmpestrm - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, Mem128, getRegisterValue(Xmm1, RSMap), - findLimitIndexE(Mem128, getRegisterValue(%rdx, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexE(Mem128, getRegisterValue(%rdx, RSMap), Imm8), + findLimitIndexE(getRegisterValue(Xmm1, RSMap), getRegisterValue(%rax, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // Find data size and interpretation rule diff --git a/semantics/memoryInstructions/vpcmpistri_xmm_m128_imm8.k b/semantics/memoryInstructions/vpcmpistri_xmm_m128_imm8.k index e511e15cf..44e726ab5 100644 --- a/semantics/memoryInstructions/vpcmpistri_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vpcmpistri_xmm_m128_imm8.k @@ -4,27 +4,28 @@ requires "x86-configuration.k" module VPCMPISTRI-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vpcmpistri:Opcode Imm8:Imm, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpcmpistri:Opcode Imm8:MInt, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpcmpistri:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => + execinstr (vpcmpistri:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vpcmpistri Imm8, memOffset( MemOff), Xmm1, .Operands) ... - + requires bitwidthMInt(Imm8) ==Int 8 // Find Limit Index rule memLoadValue(Mem128:MInt):MemLoadValue ~> - execinstr (vpcmpistri Imm8:Imm, Xmm2:Xmm, Xmm1:Xmm, .Operands) => + execinstr (vpcmpistri Imm8:MInt, Xmm2:Xmm, Xmm1:Xmm, .Operands) => execinstr (vpcmpistri - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, Mem128, getRegisterValue(Xmm1, RSMap), - findLimitIndexI(Mem128, handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexI(getRegisterValue(Xmm1, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexI(Mem128, Imm8), + findLimitIndexI(getRegisterValue(Xmm1, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // Find data size and interpretation rule diff --git a/semantics/memoryInstructions/vpcmpistrm_xmm_m128_imm8.k b/semantics/memoryInstructions/vpcmpistrm_xmm_m128_imm8.k index f13f75e4e..c65044991 100644 --- a/semantics/memoryInstructions/vpcmpistrm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vpcmpistrm_xmm_m128_imm8.k @@ -4,26 +4,28 @@ requires "x86-configuration.k" module VPCMPISTRM-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vpcmpistrm:Opcode Imm8:Imm, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpcmpistrm:Opcode Imm8:MInt, HOLE:Mem, Xmm1:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpcmpistrm:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => + execinstr (vpcmpistrm:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, Xmm1:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vpcmpistrm Imm8, memOffset( MemOff), Xmm1, .Operands) ... + requires bitwidthMInt(Imm8) ==Int 8 // Find Limit Index rule memLoadValue(Mem128:MInt):MemLoadValue ~> - execinstr (vpcmpistrm Imm8:Imm, Xmm2:Xmm, Xmm1:Xmm, .Operands) => + execinstr (vpcmpistrm Imm8:MInt, Xmm2:Xmm, Xmm1:Xmm, .Operands) => execinstr (vpcmpistrm - handleImmediateWithSignExtend(Imm8, 8, 8), + Imm8, Mem128, getRegisterValue(Xmm1, RSMap), - findLimitIndexI(Mem128, handleImmediateWithSignExtend(Imm8, 8, 8)), - findLimitIndexI(getRegisterValue(Xmm1, RSMap), handleImmediateWithSignExtend(Imm8, 8, 8)), + findLimitIndexI(Mem128, Imm8), + findLimitIndexI(getRegisterValue(Xmm1, RSMap), Imm8), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 // Find data size and interpretation rule diff --git a/semantics/memoryInstructions/vperm2f128_ymm_ymm_m256_imm8.k b/semantics/memoryInstructions/vperm2f128_ymm_ymm_m256_imm8.k index e432ac1f1..c3ba655fe 100644 --- a/semantics/memoryInstructions/vperm2f128_ymm_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vperm2f128_ymm_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPERM2F128-YMM-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vperm2f128:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] + context execinstr(vperm2f128:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vperm2f128:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vperm2f128:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vperm2f128 Imm8, memOffset( MemOff), R3:Ymm, R4:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vperm2f128:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vperm2f128:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi)) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi), mi(128, 0)) #else concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi)) #fi) #fi) +convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi)) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi), mi(128, 0)) #else concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi)) #fi) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vperm2i128_ymm_ymm_m256_imm8.k b/semantics/memoryInstructions/vperm2i128_ymm_ymm_m256_imm8.k index 91bbba777..f9daa10d9 100644 --- a/semantics/memoryInstructions/vperm2i128_ymm_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vperm2i128_ymm_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPERM2I128-YMM-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vperm2i128:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] + context execinstr(vperm2i128:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vperm2i128:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vperm2i128:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vperm2i128 Imm8, memOffset( MemOff), R3:Ymm, R4:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vperm2i128:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vperm2i128:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi)) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi), mi(128, 0)) #else concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi)) #fi) #fi) +convToRegKeys(R4) |-> (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then concatenateMInt( mi(128, 0), mi(128, 0)) #else concatenateMInt( mi(128, 0), (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi)) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi), mi(128, 0)) #else concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 0)) #then extractMInt( getParentValue(R3, RSMap), 128, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 2)) #then extractMInt( Mem256, 128, 256) #else extractMInt( Mem256, 0, 128) #fi) #fi) #fi)) #fi) #fi) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpermilpd_xmm_m128_imm8.k b/semantics/memoryInstructions/vpermilpd_xmm_m128_imm8.k index 1cfdec4dc..38e7c5e5d 100644 --- a/semantics/memoryInstructions/vpermilpd_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vpermilpd_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPERMILPD-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vpermilpd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpermilpd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpermilpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (vpermilpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vpermilpd Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpermilpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpermilpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( Mem128, 64, 128) #else extractMInt( Mem128, 0, 64) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( Mem128, 64, 128) #else extractMInt( Mem128, 0, 64) #fi))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( Mem128, 64, 128) #else extractMInt( Mem128, 0, 64) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( Mem128, 64, 128) #else extractMInt( Mem128, 0, 64) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpermilpd_ymm_m256_imm8.k b/semantics/memoryInstructions/vpermilpd_ymm_m256_imm8.k index 2c2e6d0a5..e22576e01 100644 --- a/semantics/memoryInstructions/vpermilpd_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vpermilpd_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPERMILPD-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vpermilpd:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] + context execinstr(vpermilpd:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vpermilpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + execinstr (vpermilpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vpermilpd Imm8, memOffset( MemOff), R3:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpermilpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpermilpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 0)) #then extractMInt( Mem256, 64, 128) #else extractMInt( Mem256, 0, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 0)) #then extractMInt( Mem256, 64, 128) #else extractMInt( Mem256, 0, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 0)) #then extractMInt( Mem256, 192, 256) #else extractMInt( Mem256, 128, 192) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 0)) #then extractMInt( Mem256, 192, 256) #else extractMInt( Mem256, 128, 192) #fi)))) +convToRegKeys(R3) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 0)) #then extractMInt( Mem256, 64, 128) #else extractMInt( Mem256, 0, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 0)) #then extractMInt( Mem256, 64, 128) #else extractMInt( Mem256, 0, 64) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 0)) #then extractMInt( Mem256, 192, 256) #else extractMInt( Mem256, 128, 192) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 0)) #then extractMInt( Mem256, 192, 256) #else extractMInt( Mem256, 128, 192) #fi)))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpermilps_xmm_m128_imm8.k b/semantics/memoryInstructions/vpermilps_xmm_m128_imm8.k index 31d3585ea..c02fd7fbf 100644 --- a/semantics/memoryInstructions/vpermilps_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vpermilps_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPERMILPS-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vpermilps:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpermilps:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpermilps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (vpermilps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vpermilps Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpermilps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpermilps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 0)) #then extractMInt( Mem128, 96, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 1)) #then extractMInt( Mem128, 64, 96) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 2)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( Mem128, 96, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( Mem128, 64, 96) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 0)) #then extractMInt( Mem128, 96, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 1)) #then extractMInt( Mem128, 64, 96) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 2)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 0, 32) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 0)) #then extractMInt( Mem128, 96, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 1)) #then extractMInt( Mem128, 64, 96) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 2)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 0, 32) #fi) #fi) #fi))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 0)) #then extractMInt( Mem128, 96, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 1)) #then extractMInt( Mem128, 64, 96) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 2)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( Mem128, 96, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( Mem128, 64, 96) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 0)) #then extractMInt( Mem128, 96, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 1)) #then extractMInt( Mem128, 64, 96) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 2)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 0, 32) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 0)) #then extractMInt( Mem128, 96, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 1)) #then extractMInt( Mem128, 64, 96) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 2)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 0, 32) #fi) #fi) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpermilps_ymm_m256_imm8.k b/semantics/memoryInstructions/vpermilps_ymm_m256_imm8.k index d8ed154f1..72f36a69e 100644 --- a/semantics/memoryInstructions/vpermilps_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vpermilps_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPERMILPS-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vpermilps:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] + context execinstr(vpermilps:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vpermilps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + execinstr (vpermilps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vpermilps Imm8, memOffset( MemOff), R3:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpermilps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpermilps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 0)) #then extractMInt( Mem256, 96, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 1)) #then extractMInt( Mem256, 64, 96) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 2)) #then extractMInt( Mem256, 32, 64) #else extractMInt( Mem256, 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( Mem256, 96, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( Mem256, 64, 96) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( Mem256, 32, 64) #else extractMInt( Mem256, 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 0)) #then extractMInt( Mem256, 96, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 1)) #then extractMInt( Mem256, 64, 96) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 2)) #then extractMInt( Mem256, 32, 64) #else extractMInt( Mem256, 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 0)) #then extractMInt( Mem256, 96, 128) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 1)) #then extractMInt( Mem256, 64, 96) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 2)) #then extractMInt( Mem256, 32, 64) #else extractMInt( Mem256, 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 0)) #then extractMInt( Mem256, 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 1)) #then extractMInt( Mem256, 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2), mi(2, 2)) #then extractMInt( Mem256, 160, 192) #else extractMInt( Mem256, 128, 160) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 0)) #then extractMInt( Mem256, 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 1)) #then extractMInt( Mem256, 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4), mi(2, 2)) #then extractMInt( Mem256, 160, 192) #else extractMInt( Mem256, 128, 160) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 0)) #then extractMInt( Mem256, 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 1)) #then extractMInt( Mem256, 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6), mi(2, 2)) #then extractMInt( Mem256, 160, 192) #else extractMInt( Mem256, 128, 160) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 0)) #then extractMInt( Mem256, 224, 256) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 1)) #then extractMInt( Mem256, 192, 224) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8), mi(2, 2)) #then extractMInt( Mem256, 160, 192) #else extractMInt( Mem256, 128, 160) #fi) #fi) #fi)))))))) +convToRegKeys(R3) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 0)) #then extractMInt( Mem256, 96, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 1)) #then extractMInt( Mem256, 64, 96) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 2)) #then extractMInt( Mem256, 32, 64) #else extractMInt( Mem256, 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( Mem256, 96, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( Mem256, 64, 96) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( Mem256, 32, 64) #else extractMInt( Mem256, 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 0)) #then extractMInt( Mem256, 96, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 1)) #then extractMInt( Mem256, 64, 96) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 2)) #then extractMInt( Mem256, 32, 64) #else extractMInt( Mem256, 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 0)) #then extractMInt( Mem256, 96, 128) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 1)) #then extractMInt( Mem256, 64, 96) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 2)) #then extractMInt( Mem256, 32, 64) #else extractMInt( Mem256, 0, 32) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 0)) #then extractMInt( Mem256, 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 1)) #then extractMInt( Mem256, 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 2), mi(2, 2)) #then extractMInt( Mem256, 160, 192) #else extractMInt( Mem256, 128, 160) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 0)) #then extractMInt( Mem256, 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 1)) #then extractMInt( Mem256, 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 4), mi(2, 2)) #then extractMInt( Mem256, 160, 192) #else extractMInt( Mem256, 128, 160) #fi) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 0)) #then extractMInt( Mem256, 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 1)) #then extractMInt( Mem256, 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 6), mi(2, 2)) #then extractMInt( Mem256, 160, 192) #else extractMInt( Mem256, 128, 160) #fi) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 0)) #then extractMInt( Mem256, 224, 256) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 1)) #then extractMInt( Mem256, 192, 224) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 8), mi(2, 2)) #then extractMInt( Mem256, 160, 192) #else extractMInt( Mem256, 128, 160) #fi) #fi) #fi)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpermpd_ymm_m256_imm8.k b/semantics/memoryInstructions/vpermpd_ymm_m256_imm8.k index d2d475cfc..8f7b7aba0 100644 --- a/semantics/memoryInstructions/vpermpd_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vpermpd_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPERMPD-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vpermpd:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] + context execinstr(vpermpd:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vpermpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + execinstr (vpermpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vpermpd Imm8, memOffset( MemOff), R3:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpermpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpermpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(256, 6))))), 192, 256), extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(256, 6))))), 192, 256)))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(256, 6))))), 192, 256), extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(256, 6))))), 192, 256)))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpermq_ymm_m256_imm8.k b/semantics/memoryInstructions/vpermq_ymm_m256_imm8.k index 2c1a26624..f3a50a7c3 100644 --- a/semantics/memoryInstructions/vpermq_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vpermq_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPERMQ-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vpermq:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] + context execinstr(vpermq:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vpermq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + execinstr (vpermq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vpermq Imm8, memOffset( MemOff), R3:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpermq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpermq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(256, 6))))), 192, 256), extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(256, 6))))), 192, 256)))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(256, 6))))), 192, 256), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(256, 6))))), 192, 256), extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(256, 6))))), 192, 256)))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpextrb_m8_xmm_imm8.k b/semantics/memoryInstructions/vpextrb_m8_xmm_imm8.k index 7e2f2350a..625b55a01 100644 --- a/semantics/memoryInstructions/vpextrb_m8_xmm_imm8.k +++ b/semantics/memoryInstructions/vpextrb_m8_xmm_imm8.k @@ -4,24 +4,26 @@ requires "x86-configuration.k" module VPEXTRB-M8-XMM-IMM8 imports X86-CONFIGURATION - context execinstr(vpextrb:Opcode Imm8:Imm, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(vpextrb:Opcode Imm8:MInt, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (vpextrb:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (vpextrb:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (vpextrb Imm8, R2:Xmm, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (vpextrb:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (vpextrb:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3))))), 120, 128), + extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3))))), 120, 128), MemOff, 8 ) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpextrd_m32_xmm_imm8.k b/semantics/memoryInstructions/vpextrd_m32_xmm_imm8.k index eda4b47f8..b1396072c 100644 --- a/semantics/memoryInstructions/vpextrd_m32_xmm_imm8.k +++ b/semantics/memoryInstructions/vpextrd_m32_xmm_imm8.k @@ -4,24 +4,26 @@ requires "x86-configuration.k" module VPEXTRD-M32-XMM-IMM8 imports X86-CONFIGURATION - context execinstr(vpextrd:Opcode Imm8:Imm, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(vpextrd:Opcode Imm8:MInt, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (vpextrd:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (vpextrd:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (vpextrd Imm8, R2:Xmm, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (vpextrd:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (vpextrd:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128), + extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128), MemOff, 32 ) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpextrq_m64_xmm_imm8.k b/semantics/memoryInstructions/vpextrq_m64_xmm_imm8.k index 69be5d404..2a21f97c0 100644 --- a/semantics/memoryInstructions/vpextrq_m64_xmm_imm8.k +++ b/semantics/memoryInstructions/vpextrq_m64_xmm_imm8.k @@ -4,24 +4,26 @@ requires "x86-configuration.k" module VPEXTRQ-M64-XMM-IMM8 imports X86-CONFIGURATION - context execinstr(vpextrq:Opcode Imm8:Imm, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(vpextrq:Opcode Imm8:MInt, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (vpextrq:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (vpextrq:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (vpextrq Imm8, R2:Xmm, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (vpextrq:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (vpextrq:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6))))), 64, 128), + extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6))))), 64, 128), MemOff, 64 ) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpextrw_m16_xmm_imm8.k b/semantics/memoryInstructions/vpextrw_m16_xmm_imm8.k index 1f11f47b0..3106f1c26 100644 --- a/semantics/memoryInstructions/vpextrw_m16_xmm_imm8.k +++ b/semantics/memoryInstructions/vpextrw_m16_xmm_imm8.k @@ -4,24 +4,26 @@ requires "x86-configuration.k" module VPEXTRW-M16-XMM-IMM8 imports X86-CONFIGURATION - context execinstr(vpextrw:Opcode Imm8:Imm, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(vpextrw:Opcode Imm8:MInt, R2:Xmm, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (vpextrw:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (vpextrw:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (vpextrw Imm8, R2:Xmm, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (vpextrw:Opcode Imm8:Imm, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (vpextrw:Opcode Imm8:MInt, R2:Xmm, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4))))), 112, 128), + extractMInt( lshrMInt( extractMInt( getParentValue(R2, RSMap), 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4))))), 112, 128), MemOff, 16 ) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpinsrb_xmm_xmm_m8_imm8.k b/semantics/memoryInstructions/vpinsrb_xmm_xmm_m8_imm8.k index 538f03f1d..01a8938e8 100644 --- a/semantics/memoryInstructions/vpinsrb_xmm_xmm_m8_imm8.k +++ b/semantics/memoryInstructions/vpinsrb_xmm_xmm_m8_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPINSRB-XMM-XMM-M8-IMM8 imports X86-CONFIGURATION - context execinstr(vpinsrb:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpinsrb:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpinsrb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vpinsrb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (vpinsrb Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (vpinsrb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (vpinsrb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(120, 0), Mem8), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3))))), shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 8)), uvalueMInt(mi(128, 3)))))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(120, 0), Mem8), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3))))), shiftLeftMInt( mi(128, 255), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(124, 0), extractMInt( Imm8, 4, 8)), uvalueMInt(mi(128, 3)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpinsrd_xmm_xmm_m32_imm8.k b/semantics/memoryInstructions/vpinsrd_xmm_xmm_m32_imm8.k index ba1b77448..0ad1d3051 100644 --- a/semantics/memoryInstructions/vpinsrd_xmm_xmm_m32_imm8.k +++ b/semantics/memoryInstructions/vpinsrd_xmm_xmm_m32_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPINSRD-XMM-XMM-M32-IMM8 imports X86-CONFIGURATION - context execinstr(vpinsrd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpinsrd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpinsrd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vpinsrd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (vpinsrd Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (vpinsrd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (vpinsrd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), Mem32), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5)))))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(96, 0), Mem32), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), shiftLeftMInt( mi(128, 4294967295), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpinsrq_xmm_xmm_m64_imm8.k b/semantics/memoryInstructions/vpinsrq_xmm_xmm_m64_imm8.k index 369b02406..7d24dc328 100644 --- a/semantics/memoryInstructions/vpinsrq_xmm_xmm_m64_imm8.k +++ b/semantics/memoryInstructions/vpinsrq_xmm_xmm_m64_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPINSRQ-XMM-XMM-M64-IMM8 imports X86-CONFIGURATION - context execinstr(vpinsrq:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpinsrq:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpinsrq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vpinsrq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (vpinsrq Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (vpinsrq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (vpinsrq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(64, 0), Mem64), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6))))), shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), uvalueMInt(mi(128, 6)))))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(64, 0), Mem64), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6))))), shiftLeftMInt( mi(128, 18446744073709551615), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(127, 0), extractMInt( Imm8, 7, 8)), uvalueMInt(mi(128, 6)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpinsrw_xmm_xmm_m16_imm8.k b/semantics/memoryInstructions/vpinsrw_xmm_xmm_m16_imm8.k index ce6b30e3f..29df94768 100644 --- a/semantics/memoryInstructions/vpinsrw_xmm_xmm_m16_imm8.k +++ b/semantics/memoryInstructions/vpinsrw_xmm_xmm_m16_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPINSRW-XMM-XMM-M16-IMM8 imports X86-CONFIGURATION - context execinstr(vpinsrw:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpinsrw:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpinsrw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vpinsrw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (vpinsrw Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (vpinsrw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (vpinsrw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(112, 0), Mem16), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4))))), shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 8)), uvalueMInt(mi(128, 4)))))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), orMInt( andMInt( extractMInt( getParentValue(R3, RSMap), 128, 256), negMInt( shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4))))))), andMInt( shiftLeftMInt( concatenateMInt( mi(112, 0), Mem16), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4))))), shiftLeftMInt( mi(128, 65535), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(125, 0), extractMInt( Imm8, 5, 8)), uvalueMInt(mi(128, 4)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpshufd_xmm_m128_imm8.k b/semantics/memoryInstructions/vpshufd_xmm_m128_imm8.k index 87d0d7b6e..74ba9c1c1 100644 --- a/semantics/memoryInstructions/vpshufd_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vpshufd_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPSHUFD-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vpshufd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpshufd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpshufd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (vpshufd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vpshufd Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpshufd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpshufd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpshufd_ymm_m256_imm8.k b/semantics/memoryInstructions/vpshufd_ymm_m256_imm8.k index 0b6b17c78..d6a40a98b 100644 --- a/semantics/memoryInstructions/vpshufd_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vpshufd_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPSHUFD-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vpshufd:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] + context execinstr(vpshufd:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vpshufd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + execinstr (vpshufd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vpshufd Imm8, memOffset( MemOff), R3:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpshufd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpshufd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( extractMInt( Mem256, 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( Mem256, 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( Mem256, 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( Mem256, 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( Mem256, 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( Mem256, 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( Mem256, 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), extractMInt( lshrMInt( extractMInt( Mem256, 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128)))))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( extractMInt( Mem256, 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( Mem256, 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( Mem256, 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( Mem256, 0, 128), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( Mem256, 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( Mem256, 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 5))))), 96, 128), concatenateMInt( extractMInt( lshrMInt( extractMInt( Mem256, 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 5))))), 96, 128), extractMInt( lshrMInt( extractMInt( Mem256, 128, 256), uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 5))))), 96, 128)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpshufhw_xmm_m128_imm8.k b/semantics/memoryInstructions/vpshufhw_xmm_m128_imm8.k index eeb489202..957e825b1 100644 --- a/semantics/memoryInstructions/vpshufhw_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vpshufhw_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPSHUFHW-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vpshufhw:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpshufhw:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpshufhw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (vpshufhw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vpshufhw Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpshufhw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpshufhw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 4))))), 48, 64), extractMInt( Mem128, 64, 128)))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 4))))), 48, 64), extractMInt( Mem128, 64, 128)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpshufhw_ymm_m256_imm8.k b/semantics/memoryInstructions/vpshufhw_ymm_m256_imm8.k index a9b0def71..bbb390a6d 100644 --- a/semantics/memoryInstructions/vpshufhw_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vpshufhw_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPSHUFHW-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vpshufhw:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] + context execinstr(vpshufhw:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vpshufhw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + execinstr (vpshufhw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vpshufhw Imm8, memOffset( MemOff), R3:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpshufhw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpshufhw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( Mem256, 64, 128), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(256, 4))))), 176, 192), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(256, 4))))), 176, 192), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(256, 4))))), 176, 192), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(256, 4))))), 176, 192), extractMInt( Mem256, 192, 256)))))))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(256, 4))))), 48, 64), concatenateMInt( extractMInt( Mem256, 64, 128), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(256, 4))))), 176, 192), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(256, 4))))), 176, 192), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(256, 4))))), 176, 192), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(256, 4))))), 176, 192), extractMInt( Mem256, 192, 256)))))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpshuflw_xmm_m128_imm8.k b/semantics/memoryInstructions/vpshuflw_xmm_m128_imm8.k index 4ea5e1628..e9ad30418 100644 --- a/semantics/memoryInstructions/vpshuflw_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vpshuflw_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPSHUFLW-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vpshuflw:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(vpshuflw:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vpshuflw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (vpshuflw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vpshuflw Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpshuflw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vpshuflw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( Mem128, 0, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(128, 4))))), 112, 128), extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(128, 4))))), 112, 128)))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( Mem128, 0, 64), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(128, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(128, 4))))), 112, 128), extractMInt( lshrMInt( Mem128, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(126, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(128, 4))))), 112, 128)))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vpshuflw_ymm_m256_imm8.k b/semantics/memoryInstructions/vpshuflw_ymm_m256_imm8.k index c2d6f93cb..da5dd0671 100644 --- a/semantics/memoryInstructions/vpshuflw_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vpshuflw_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VPSHUFLW-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vpshuflw:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] + context execinstr(vpshuflw:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vpshuflw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + execinstr (vpshuflw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vpshuflw Imm8, memOffset( MemOff), R3:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpshuflw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vpshuflw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( extractMInt( Mem256, 0, 64), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( Mem256, 128, 192), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 2)), uvalueMInt(mi(256, 4))))), 240, 256), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 4)), uvalueMInt(mi(256, 4))))), 240, 256), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 6)), uvalueMInt(mi(256, 4))))), 240, 256), extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 8)), uvalueMInt(mi(256, 4))))), 240, 256)))))))))) +convToRegKeys(R3) |-> concatenateMInt( extractMInt( Mem256, 0, 64), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(256, 4))))), 112, 128), concatenateMInt( extractMInt( Mem256, 128, 192), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 0, 2)), uvalueMInt(mi(256, 4))))), 240, 256), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 2, 4)), uvalueMInt(mi(256, 4))))), 240, 256), concatenateMInt( extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 4, 6)), uvalueMInt(mi(256, 4))))), 240, 256), extractMInt( lshrMInt( Mem256, uvalueMInt(shiftLeftMInt( concatenateMInt( mi(254, 0), extractMInt( Imm8, 6, 8)), uvalueMInt(mi(256, 4))))), 240, 256)))))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vroundpd_xmm_m128_imm8.k b/semantics/memoryInstructions/vroundpd_xmm_m128_imm8.k index 52c15f25c..eff64c13e 100644 --- a/semantics/memoryInstructions/vroundpd_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vroundpd_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VROUNDPD-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vroundpd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(vroundpd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vroundpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (vroundpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vroundpd Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vroundpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vroundpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( cvt_double_to_int64_rm(extractMInt( Mem128, 0, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_double_to_int64_rm(extractMInt( Mem128, 64, 128), handleImmediateWithSignExtend(Imm8, 8, 8)))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( cvt_double_to_int64_rm(extractMInt( Mem128, 0, 64), Imm8), cvt_double_to_int64_rm(extractMInt( Mem128, 64, 128), Imm8))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vroundpd_ymm_m256_imm8.k b/semantics/memoryInstructions/vroundpd_ymm_m256_imm8.k index 0d86ea5fa..29c4f53db 100644 --- a/semantics/memoryInstructions/vroundpd_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vroundpd_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VROUNDPD-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vroundpd:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] + context execinstr(vroundpd:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vroundpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + execinstr (vroundpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vroundpd Imm8, memOffset( MemOff), R3:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vroundpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vroundpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( cvt_double_to_int64_rm(extractMInt( Mem256, 0, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_double_to_int64_rm(extractMInt( Mem256, 64, 128), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_double_to_int64_rm(extractMInt( Mem256, 128, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_double_to_int64_rm(extractMInt( Mem256, 192, 256), handleImmediateWithSignExtend(Imm8, 8, 8))))) +convToRegKeys(R3) |-> concatenateMInt( cvt_double_to_int64_rm(extractMInt( Mem256, 0, 64), Imm8), concatenateMInt( cvt_double_to_int64_rm(extractMInt( Mem256, 64, 128), Imm8), concatenateMInt( cvt_double_to_int64_rm(extractMInt( Mem256, 128, 192), Imm8), cvt_double_to_int64_rm(extractMInt( Mem256, 192, 256), Imm8)))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vroundps_xmm_m128_imm8.k b/semantics/memoryInstructions/vroundps_xmm_m128_imm8.k index 3ffb0eb80..19b62e4dd 100644 --- a/semantics/memoryInstructions/vroundps_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vroundps_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VROUNDPS-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vroundps:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] + context execinstr(vroundps:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vroundps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + execinstr (vroundps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vroundps Imm8, memOffset( MemOff), R3:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vroundps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vroundps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem128, 0, 32), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem128, 32, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem128, 64, 96), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_single_to_int32_rm(extractMInt( Mem128, 96, 128), handleImmediateWithSignExtend(Imm8, 8, 8)))))) +convToRegKeys(R3) |-> concatenateMInt( mi(128, 0), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem128, 0, 32), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem128, 32, 64), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem128, 64, 96), Imm8), cvt_single_to_int32_rm(extractMInt( Mem128, 96, 128), Imm8))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vroundps_ymm_m256_imm8.k b/semantics/memoryInstructions/vroundps_ymm_m256_imm8.k index 653a1dc9f..870448c7c 100644 --- a/semantics/memoryInstructions/vroundps_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vroundps_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VROUNDPS-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vroundps:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] + context execinstr(vroundps:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vroundps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + execinstr (vroundps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vroundps Imm8, memOffset( MemOff), R3:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vroundps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vroundps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R3) |-> concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem256, 0, 32), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem256, 32, 64), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem256, 64, 96), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem256, 96, 128), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem256, 128, 160), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem256, 160, 192), handleImmediateWithSignExtend(Imm8, 8, 8)), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem256, 192, 224), handleImmediateWithSignExtend(Imm8, 8, 8)), cvt_single_to_int32_rm(extractMInt( Mem256, 224, 256), handleImmediateWithSignExtend(Imm8, 8, 8))))))))) +convToRegKeys(R3) |-> concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem256, 0, 32), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem256, 32, 64), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem256, 64, 96), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem256, 96, 128), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem256, 128, 160), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem256, 160, 192), Imm8), concatenateMInt( cvt_single_to_int32_rm(extractMInt( Mem256, 192, 224), Imm8), cvt_single_to_int32_rm(extractMInt( Mem256, 224, 256), Imm8)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vroundsd_xmm_xmm_m64_imm8.k b/semantics/memoryInstructions/vroundsd_xmm_xmm_m64_imm8.k index 2b7aa82fb..b1b98e49a 100644 --- a/semantics/memoryInstructions/vroundsd_xmm_xmm_m64_imm8.k +++ b/semantics/memoryInstructions/vroundsd_xmm_xmm_m64_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VROUNDSD-XMM-XMM-M64-IMM8 imports X86-CONFIGURATION - context execinstr(vroundsd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vroundsd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vroundsd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vroundsd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (vroundsd Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (vroundsd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (vroundsd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 192), cvt_double_to_int64_rm(Mem64, handleImmediateWithSignExtend(Imm8, 8, 8)))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 192), cvt_double_to_int64_rm(Mem64, Imm8))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vroundss_xmm_xmm_m32_imm8.k b/semantics/memoryInstructions/vroundss_xmm_xmm_m32_imm8.k index 250e08378..3d8c7d7cf 100644 --- a/semantics/memoryInstructions/vroundss_xmm_xmm_m32_imm8.k +++ b/semantics/memoryInstructions/vroundss_xmm_xmm_m32_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VROUNDSS-XMM-XMM-M32-IMM8 imports X86-CONFIGURATION - context execinstr(vroundss:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vroundss:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vroundss:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vroundss:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (vroundss Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (vroundss:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (vroundss:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 224), cvt_single_to_int32_rm(Mem32, handleImmediateWithSignExtend(Imm8, 8, 8)))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( extractMInt( getParentValue(R3, RSMap), 128, 224), cvt_single_to_int32_rm(Mem32, Imm8))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vshufpd_xmm_xmm_m128_imm8.k b/semantics/memoryInstructions/vshufpd_xmm_xmm_m128_imm8.k index 6d9c32ce3..18c4fd73d 100644 --- a/semantics/memoryInstructions/vshufpd_xmm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vshufpd_xmm_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VSHUFPD-XMM-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vshufpd:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vshufpd:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vshufpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vshufpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vshufpd Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vshufpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vshufpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( Mem128, 0, 64) #else extractMInt( Mem128, 64, 128) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R3, RSMap), 192, 256) #fi))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( Mem128, 0, 64) #else extractMInt( Mem128, 64, 128) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R3, RSMap), 192, 256) #fi))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vshufpd_ymm_ymm_m256_imm8.k b/semantics/memoryInstructions/vshufpd_ymm_ymm_m256_imm8.k index 0743ec2af..e966968a3 100644 --- a/semantics/memoryInstructions/vshufpd_ymm_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vshufpd_ymm_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VSHUFPD-YMM-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vshufpd:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] + context execinstr(vshufpd:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vshufpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vshufpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vshufpd Imm8, memOffset( MemOff), R3:Ymm, R4:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vshufpd:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vshufpd:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( Mem256, 0, 64) #else extractMInt( Mem256, 64, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 64) #else extractMInt( getParentValue(R3, RSMap), 64, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( Mem256, 128, 192) #else extractMInt( Mem256, 192, 256) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R3, RSMap), 192, 256) #fi)))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( Mem256, 0, 64) #else extractMInt( Mem256, 64, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 64) #else extractMInt( getParentValue(R3, RSMap), 64, 128) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( Mem256, 128, 192) #else extractMInt( Mem256, 192, 256) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 192) #else extractMInt( getParentValue(R3, RSMap), 192, 256) #fi)))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vshufps_xmm_xmm_m128_imm8.k b/semantics/memoryInstructions/vshufps_xmm_xmm_m128_imm8.k index 18d1e9b47..65694b991 100644 --- a/semantics/memoryInstructions/vshufps_xmm_xmm_m128_imm8.k +++ b/semantics/memoryInstructions/vshufps_xmm_xmm_m128_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VSHUFPS-XMM-XMM-M128-IMM8 imports X86-CONFIGURATION - context execinstr(vshufps:Opcode Imm8:Imm, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] + context execinstr(vshufps:Opcode Imm8:MInt, HOLE:Mem, R3:Xmm, R4:Xmm, .Operands) [result(MemOffset)] rule - execinstr (vshufps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + execinstr (vshufps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => loadFromMemory( MemOff, 128) ~> execinstr (vshufps Imm8, memOffset( MemOff), R3:Xmm, R4:Xmm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vshufps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => + memLoadValue(Mem128:MInt):MemLoadValue ~> execinstr (vshufps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Xmm, R4:Xmm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( Mem128, 0, 32) #else extractMInt( Mem128, 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( Mem128, 0, 32) #else extractMInt( Mem128, 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))))) +convToRegKeys(R4) |-> concatenateMInt( mi(128, 0), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( Mem128, 0, 32) #else extractMInt( Mem128, 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( Mem128, 0, 32) #else extractMInt( Mem128, 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( Mem128, 32, 64) #else extractMInt( Mem128, 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/vshufps_ymm_ymm_m256_imm8.k b/semantics/memoryInstructions/vshufps_ymm_ymm_m256_imm8.k index bf4ea4da0..470be85fa 100644 --- a/semantics/memoryInstructions/vshufps_ymm_ymm_m256_imm8.k +++ b/semantics/memoryInstructions/vshufps_ymm_ymm_m256_imm8.k @@ -4,22 +4,24 @@ requires "x86-configuration.k" module VSHUFPS-YMM-YMM-M256-IMM8 imports X86-CONFIGURATION - context execinstr(vshufps:Opcode Imm8:Imm, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] + context execinstr(vshufps:Opcode Imm8:MInt, HOLE:Mem, R3:Ymm, R4:Ymm, .Operands) [result(MemOffset)] rule - execinstr (vshufps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + execinstr (vshufps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => loadFromMemory( MemOff, 256) ~> execinstr (vshufps Imm8, memOffset( MemOff), R3:Ymm, R4:Ymm, .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vshufps:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => + memLoadValue(Mem256:MInt):MemLoadValue ~> execinstr (vshufps:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, R3:Ymm, R4:Ymm, .Operands) => . ... RSMap:Map => updateMap(RSMap, -convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( Mem256, 0, 32) #else extractMInt( Mem256, 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( Mem256, 32, 64) #else extractMInt( Mem256, 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( Mem256, 0, 32) #else extractMInt( Mem256, 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( Mem256, 32, 64) #else extractMInt( Mem256, 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( getParentValue(R3, RSMap), 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( getParentValue(R3, RSMap), 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( getParentValue(R3, RSMap), 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( getParentValue(R3, RSMap), 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( Mem256, 128, 160) #else extractMInt( Mem256, 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1), mi(1, 1)) #then extractMInt( Mem256, 160, 192) #else extractMInt( Mem256, 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( Mem256, 128, 160) #else extractMInt( Mem256, 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3), mi(1, 1)) #then extractMInt( Mem256, 160, 192) #else extractMInt( Mem256, 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi), (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi)))))))) +convToRegKeys(R4) |-> concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( Mem256, 0, 32) #else extractMInt( Mem256, 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( Mem256, 32, 64) #else extractMInt( Mem256, 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( Mem256, 0, 32) #else extractMInt( Mem256, 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( Mem256, 32, 64) #else extractMInt( Mem256, 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( getParentValue(R3, RSMap), 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( getParentValue(R3, RSMap), 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 0, 32) #else extractMInt( getParentValue(R3, RSMap), 64, 96) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 32, 64) #else extractMInt( getParentValue(R3, RSMap), 96, 128) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 1, 2), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( Mem256, 128, 160) #else extractMInt( Mem256, 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 0, 1), mi(1, 1)) #then extractMInt( Mem256, 160, 192) #else extractMInt( Mem256, 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 3, 4), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( Mem256, 128, 160) #else extractMInt( Mem256, 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 2, 3), mi(1, 1)) #then extractMInt( Mem256, 160, 192) #else extractMInt( Mem256, 224, 256) #fi) #fi), concatenateMInt( (#ifMInt eqMInt( extractMInt( Imm8, 5, 6), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 4, 5), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi), (#ifMInt eqMInt( extractMInt( Imm8, 7, 8), mi(1, 1)) #then (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 128, 160) #else extractMInt( getParentValue(R3, RSMap), 192, 224) #fi) #else (#ifMInt eqMInt( extractMInt( Imm8, 6, 7), mi(1, 1)) #then extractMInt( getParentValue(R3, RSMap), 160, 192) #else extractMInt( getParentValue(R3, RSMap), 224, 256) #fi) #fi)))))))) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/xorb_m8_imm8.k b/semantics/memoryInstructions/xorb_m8_imm8.k index 1bfc2c39a..a338382b7 100644 --- a/semantics/memoryInstructions/xorb_m8_imm8.k +++ b/semantics/memoryInstructions/xorb_m8_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module XORB-M8-IMM8 imports X86-CONFIGURATION - context execinstr(xorb:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(xorb:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (xorb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (xorb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 8) ~> execinstr (xorb Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (xorb:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem8:MInt):MemLoadValue ~> execinstr (xorb:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - xorMInt( Mem8, handleImmediateWithSignExtend(Imm8, 8, 8)), + xorMInt( Mem8, Imm8), MemOff, 8 ) @@ -27,15 +28,16 @@ module XORB-M8-IMM8 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( Mem8, 7, 8), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( Mem8, 6, 7), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem8, 5, 6), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem8, 4, 5), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem8, 3, 4), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem8, 2, 3), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem8, 1, 2), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem8, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( Mem8, 7, 8), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( Mem8, 6, 7), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem8, 5, 6), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem8, 4, 5), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem8, 3, 4), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem8, 2, 3), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem8, 1, 2), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem8, 0, 1), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( Mem8, handleImmediateWithSignExtend(Imm8, 8, 8)), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( Mem8, Imm8), mi(8, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( Mem8, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)) +"SF" |-> xorMInt( extractMInt( Mem8, 0, 1), extractMInt( Imm8, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/xorl_m32_imm32.k b/semantics/memoryInstructions/xorl_m32_imm32.k index db7bfde46..7830673db 100644 --- a/semantics/memoryInstructions/xorl_m32_imm32.k +++ b/semantics/memoryInstructions/xorl_m32_imm32.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module XORL-M32-IMM32 imports X86-CONFIGURATION - context execinstr(xorl:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(xorl:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (xorl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (xorl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (xorl Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (xorl:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (xorl:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - xorMInt( Mem32, handleImmediateWithSignExtend(Imm32, 32, 32)), + xorMInt( Mem32, Imm32), MemOff, 32 ) @@ -27,15 +28,16 @@ module XORL-M32-IMM32 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( Mem32, 31, 32), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( Mem32, 30, 31), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 29, 30), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 28, 29), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 27, 28), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 26, 27), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 25, 26), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 24, 25), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( Mem32, 31, 32), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( Mem32, 30, 31), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 29, 30), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 28, 29), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 27, 28), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 26, 27), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 25, 26), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 24, 25), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( Mem32, handleImmediateWithSignExtend(Imm32, 32, 32)), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( Mem32, Imm32), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( Mem32, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 0, 1)) +"SF" |-> xorMInt( extractMInt( Mem32, 0, 1), extractMInt( Imm32, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/xorl_m32_imm8.k b/semantics/memoryInstructions/xorl_m32_imm8.k index b2a9bea6c..281094860 100644 --- a/semantics/memoryInstructions/xorl_m32_imm8.k +++ b/semantics/memoryInstructions/xorl_m32_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module XORL-M32-IMM8 imports X86-CONFIGURATION - context execinstr(xorl:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(xorl:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (xorl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (xorl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 32) ~> execinstr (xorl Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (xorl:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (xorl:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - xorMInt( Mem32, mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), + xorMInt( Mem32, mi(32, svalueMInt(Imm8))), MemOff, 32 ) @@ -27,15 +28,16 @@ module XORL-M32-IMM8 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( Mem32, 31, 32), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( Mem32, 30, 31), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 29, 30), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 28, 29), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 27, 28), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 26, 27), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 25, 26), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 24, 25), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( Mem32, 31, 32), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( Mem32, 30, 31), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 29, 30), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 28, 29), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 27, 28), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 26, 27), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 25, 26), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem32, 24, 25), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( Mem32, mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( Mem32, mi(32, svalueMInt(Imm8))), mi(32, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( Mem32, 0, 1), extractMInt( mi(32, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> xorMInt( extractMInt( Mem32, 0, 1), extractMInt( mi(32, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/xorq_m64_imm32.k b/semantics/memoryInstructions/xorq_m64_imm32.k index a77c4c11e..05f383ba0 100644 --- a/semantics/memoryInstructions/xorq_m64_imm32.k +++ b/semantics/memoryInstructions/xorq_m64_imm32.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module XORQ-M64-IMM32 imports X86-CONFIGURATION - context execinstr(xorq:Opcode Imm32:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(xorq:Opcode Imm32:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (xorq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (xorq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (xorq Imm32, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm32) ==Int 32 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (xorq:Opcode Imm32:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (xorq:Opcode Imm32:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - xorMInt( Mem64, mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), + xorMInt( Mem64, mi(64, svalueMInt(Imm32))), MemOff, 64 ) @@ -27,15 +28,16 @@ module XORQ-M64-IMM32 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( Mem64, 63, 64), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 31, 32)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( Mem64, 62, 63), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 30, 31)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 61, 62), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 29, 30)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 60, 61), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 28, 29)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 59, 60), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 27, 28)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 58, 59), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 26, 27)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 57, 58), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 25, 26)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 56, 57), extractMInt( handleImmediateWithSignExtend(Imm32, 32, 32), 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( Mem64, 63, 64), extractMInt( Imm32, 31, 32)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( Mem64, 62, 63), extractMInt( Imm32, 30, 31)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 61, 62), extractMInt( Imm32, 29, 30)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 60, 61), extractMInt( Imm32, 28, 29)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 59, 60), extractMInt( Imm32, 27, 28)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 58, 59), extractMInt( Imm32, 26, 27)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 57, 58), extractMInt( Imm32, 25, 26)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 56, 57), extractMInt( Imm32, 24, 25)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( Mem64, mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( Mem64, mi(64, svalueMInt(Imm32))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( Mem64, 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm32, 32, 32))), 0, 1)) +"SF" |-> xorMInt( extractMInt( Mem64, 0, 1), extractMInt( mi(64, svalueMInt(Imm32)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/memoryInstructions/xorq_m64_imm8.k b/semantics/memoryInstructions/xorq_m64_imm8.k index 1f8e023ad..1727eae5b 100644 --- a/semantics/memoryInstructions/xorq_m64_imm8.k +++ b/semantics/memoryInstructions/xorq_m64_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module XORQ-M64-IMM8 imports X86-CONFIGURATION - context execinstr(xorq:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(xorq:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (xorq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (xorq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 64) ~> execinstr (xorq Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (xorq:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem64:MInt):MemLoadValue ~> execinstr (xorq:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - xorMInt( Mem64, mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), + xorMInt( Mem64, mi(64, svalueMInt(Imm8))), MemOff, 64 ) @@ -27,15 +28,16 @@ module XORQ-M64-IMM8 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( Mem64, 63, 64), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( Mem64, 62, 63), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 61, 62), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 60, 61), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 59, 60), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 58, 59), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 57, 58), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 56, 57), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( Mem64, 63, 64), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( Mem64, 62, 63), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 61, 62), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 60, 61), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 59, 60), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 58, 59), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 57, 58), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem64, 56, 57), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( Mem64, mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( Mem64, mi(64, svalueMInt(Imm8))), mi(64, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( Mem64, 0, 1), extractMInt( mi(64, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> xorMInt( extractMInt( Mem64, 0, 1), extractMInt( mi(64, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/memoryInstructions/xorw_m16_imm16.k b/semantics/memoryInstructions/xorw_m16_imm16.k index b6c04a45b..6aab46f18 100644 --- a/semantics/memoryInstructions/xorw_m16_imm16.k +++ b/semantics/memoryInstructions/xorw_m16_imm16.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module XORW-M16-IMM16 imports X86-CONFIGURATION - context execinstr(xorw:Opcode Imm16:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(xorw:Opcode Imm16:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (xorw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (xorw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (xorw Imm16, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm16) ==Int 16 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (xorw:Opcode Imm16:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (xorw:Opcode Imm16:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - xorMInt( Mem16, handleImmediateWithSignExtend(Imm16, 16, 16)), + xorMInt( Mem16, Imm16), MemOff, 16 ) @@ -27,15 +28,16 @@ module XORW-M16-IMM16 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( Mem16, 15, 16), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 15, 16)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( Mem16, 14, 15), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 14, 15)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 13, 14), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 13, 14)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 12, 13), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 12, 13)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 11, 12), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 11, 12)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 10, 11), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 10, 11)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 9, 10), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 9, 10)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 8, 9), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( Mem16, 15, 16), extractMInt( Imm16, 15, 16)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( Mem16, 14, 15), extractMInt( Imm16, 14, 15)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 13, 14), extractMInt( Imm16, 13, 14)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 12, 13), extractMInt( Imm16, 12, 13)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 11, 12), extractMInt( Imm16, 11, 12)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 10, 11), extractMInt( Imm16, 10, 11)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 9, 10), extractMInt( Imm16, 9, 10)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 8, 9), extractMInt( Imm16, 8, 9)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( Mem16, handleImmediateWithSignExtend(Imm16, 16, 16)), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( Mem16, Imm16), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( Mem16, 0, 1), extractMInt( handleImmediateWithSignExtend(Imm16, 16, 16), 0, 1)) +"SF" |-> xorMInt( extractMInt( Mem16, 0, 1), extractMInt( Imm16, 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm16) ==Int 16 endmodule diff --git a/semantics/memoryInstructions/xorw_m16_imm8.k b/semantics/memoryInstructions/xorw_m16_imm8.k index e3430d659..daea736e1 100644 --- a/semantics/memoryInstructions/xorw_m16_imm8.k +++ b/semantics/memoryInstructions/xorw_m16_imm8.k @@ -4,20 +4,21 @@ requires "x86-configuration.k" module XORW-M16-IMM8 imports X86-CONFIGURATION - context execinstr(xorw:Opcode Imm8:Imm, HOLE:Mem, .Operands) [result(MemOffset)] + context execinstr(xorw:Opcode Imm8:MInt, HOLE:Mem, .Operands) [result(MemOffset)] rule - execinstr (xorw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + execinstr (xorw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => loadFromMemory( MemOff, 16) ~> execinstr (xorw Imm8, memOffset( MemOff), .Operands) ... RSMap:Map + requires bitwidthMInt(Imm8) ==Int 8 rule - memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (xorw:Opcode Imm8:Imm, memOffset( MemOff:MInt):MemOffset, .Operands) => + memLoadValue(Mem16:MInt):MemLoadValue ~> execinstr (xorw:Opcode Imm8:MInt, memOffset( MemOff:MInt):MemOffset, .Operands) => storeToMemory( - xorMInt( Mem16, mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), + xorMInt( Mem16, mi(16, svalueMInt(Imm8))), MemOff, 16 ) @@ -27,15 +28,16 @@ module XORW-M16-IMM8 RSMap:Map => updateMap(RSMap, "CF" |-> mi(1, 0) -"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( Mem16, 15, 16), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( Mem16, 14, 15), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 13, 14), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 12, 13), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 11, 12), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 10, 11), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 9, 10), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 8, 9), extractMInt( handleImmediateWithSignExtend(Imm8, 8, 8), 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) +"PF" |-> (#ifMInt (notBool (((((((eqMInt( xorMInt( extractMInt( Mem16, 15, 16), extractMInt( Imm8, 7, 8)), mi(1, 1)) xorBool eqMInt( xorMInt( extractMInt( Mem16, 14, 15), extractMInt( Imm8, 6, 7)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 13, 14), extractMInt( Imm8, 5, 6)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 12, 13), extractMInt( Imm8, 4, 5)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 11, 12), extractMInt( Imm8, 3, 4)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 10, 11), extractMInt( Imm8, 2, 3)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 9, 10), extractMInt( Imm8, 1, 2)), mi(1, 1))) xorBool eqMInt( xorMInt( extractMInt( Mem16, 8, 9), extractMInt( Imm8, 0, 1)), mi(1, 1)))) #then mi(1, 1) #else mi(1, 0) #fi) "AF" |-> (undefMInt) -"ZF" |-> (#ifMInt eqMInt( xorMInt( Mem16, mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8)))), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) +"ZF" |-> (#ifMInt eqMInt( xorMInt( Mem16, mi(16, svalueMInt(Imm8))), mi(16, 0)) #then mi(1, 1) #else mi(1, 0) #fi) -"SF" |-> xorMInt( extractMInt( Mem16, 0, 1), extractMInt( mi(16, svalueMInt(handleImmediateWithSignExtend(Imm8, 8, 8))), 0, 1)) +"SF" |-> xorMInt( extractMInt( Mem16, 0, 1), extractMInt( mi(16, svalueMInt(Imm8)), 0, 1)) "OF" |-> mi(1, 0) ) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/registerInstructions/pushq_imm32.k b/semantics/registerInstructions/pushq_imm32.k deleted file mode 100644 index 143e8b115..000000000 --- a/semantics/registerInstructions/pushq_imm32.k +++ /dev/null @@ -1,22 +0,0 @@ -requires "x86-configuration.k" - - -/*@ - Push R: - 1. ValTostore = R - 2. *(RSP-8) = ValTostore - 3. RSP = RSP - 8 -*/ -module PUSHQ-IMM32 - imports X86-CONFIGURATION - - rule - execinstr (pushq Imm32:Imm, .Operands) => - storeToMemory( - handleImmediateWithSignExtend(Imm32, 32, 64), - subMInt(getRegisterValue(%rsp, RSMap), mi(64, 8)), - 64) ~> - decRSPInBytes(8) - ... - RSMap -endmodule diff --git a/semantics/registerInstructions/roll_r32_one.k b/semantics/registerInstructions/roll_r32_one.k index 34f3407b6..c2dfc627d 100644 --- a/semantics/registerInstructions/roll_r32_one.k +++ b/semantics/registerInstructions/roll_r32_one.k @@ -1,36 +1,25 @@ // Autogenerated using stratification. requires "x86-configuration.k" -module ROLL-M32-ONE +module ROLL-R32-ONE imports X86-CONFIGURATION - rule - execinstr (roll:Opcode M:Mem, .Operands) => execinstr (roll:Opcode $0x1, M:Mem, .Operands) - ... - context execinstr(roll:Opcode $0x1, HOLE:Mem, .Operands) [result(MemOffset)] - - rule - execinstr (roll:Opcode $0x1, memOffset( MemOff:MInt):MemOffset, .Operands) => - loadFromMemory( MemOff, 32) ~> - execinstr (roll $0x1, memOffset( MemOff), .Operands) - ... - RSMap:Map - rule - memLoadValue(Mem32:MInt):MemLoadValue ~> execinstr (roll:Opcode $0x1, memOffset( MemOff:MInt):MemOffset, .Operands) => - - storeToMemory( - rol( Mem32, mi(32, 1)), - MemOff, - 32 - ) - + execinstr (roll $0x1, R2:R32, .Operands) => . ... - RSMap:Map => updateMap(RSMap, -"CF" |-> extractMInt( rol( Mem32, mi(32, 1)), 31, 32) +RSMap:Map => updateMap(RSMap, +convToRegKeys(R2) |-> concatenateMInt( mi(32, 0), rol( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, 1))) + +"CF" |-> extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, 1)), 31, 32) + +"OF" |-> (#ifMInt (eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, 1)), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( extractMInt( getParentValue(R2, RSMap), 32, 64), mi(32, 1)), 31, 32), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) +) -"OF" |-> (#ifMInt (eqMInt( extractMInt( rol( Mem32, mi(32, 1)), 0, 1), mi(1, 1)) xorBool eqMInt( extractMInt( rol( Mem32, mi(32, 1)), 31, 32), mi(1, 1))) #then mi(1, 1) #else mi(1, 0) #fi) - ) + +endmodule + +module ROLL-R32-ONE-SEMANTICS + imports ROLL-R32-ONE endmodule diff --git a/semantics/systemInstructions/callq_rel32.k b/semantics/systemInstructions/callq_rel32.k index 42e5a159b..abd054b19 100644 --- a/semantics/systemInstructions/callq_rel32.k +++ b/semantics/systemInstructions/callq_rel32.k @@ -13,16 +13,18 @@ module CALLQ-REL32 rule - execinstr (callq Imm32:Imm, .Operands) => + execinstr (callq Imm32:MInt, .Operands) => storeToMemory({RSMap["RIP"]}:>MInt, subMInt(getRegisterValue(%rsp, RSMap), mi(64, 8)), 64) ~> decRSPInBytes(8) ... - RSMap => updateMap(RSMap, ("RIP" |->addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)) )) + RSMap => updateMap(RSMap, ("RIP" |->addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)) )) SymMap - requires notBool HasBuiltinAtAddress(SymMap, addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64))) + requires notBool HasBuiltinAtAddress(SymMap, addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64))) + andBool bitwidthMInt(Imm32) ==Int 32 - rule execinstr (callq Imm32:Imm, .Operands) => execinstr(call GetBuiltinFromAddress(SymMap, addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) ... + rule execinstr (callq Imm32:MInt, .Operands) => execinstr(call GetBuiltinFromAddress(SymMap, addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) ... RSMap SymMap - requires HasBuiltinAtAddress(SymMap, addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64))) + requires HasBuiltinAtAddress(SymMap, addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64))) + andBool bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/systemInstructions/ja_rel32.k b/semantics/systemInstructions/ja_rel32.k index 7edfdbd8f..987f2fc69 100644 --- a/semantics/systemInstructions/ja_rel32.k +++ b/semantics/systemInstructions/ja_rel32.k @@ -4,7 +4,14 @@ module JA-REL32 imports X86-CONFIGURATION imports X86-FLAG-CHECS-SYNTAX - rule execinstr (ja Imm32:Imm, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + rule execinstr (ja Imm32:MInt, .Operands) => . ... + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) + + requires bitwidthMInt(Imm32) ==Int 32 andBool + (eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) + + rule execinstr (ja Imm32:MInt, .Operands) => . ... + RSMap + requires bitwidthMInt(Imm32) ==Int 32 andBool + (eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) orBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1))) endmodule diff --git a/semantics/systemInstructions/ja_rel8.k b/semantics/systemInstructions/ja_rel8.k index 351771832..96bc20187 100644 --- a/semantics/systemInstructions/ja_rel8.k +++ b/semantics/systemInstructions/ja_rel8.k @@ -6,19 +6,20 @@ module JA-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (ja Imm8:Imm, .Operands) => . + execinstr (ja Imm8:MInt, .Operands) => . ... RSMap => updateMap(RSMap, ("RIP" |-> - addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, - 8, 64)))) + addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) - andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) + andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) rule - execinstr (ja Imm8:Imm, .Operands) => . + execinstr (ja Imm8:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) - orBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + orBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1))) endmodule diff --git a/semantics/systemInstructions/jae_rel32.k b/semantics/systemInstructions/jae_rel32.k index 8cd55a406..697ee5c2b 100644 --- a/semantics/systemInstructions/jae_rel32.k +++ b/semantics/systemInstructions/jae_rel32.k @@ -6,15 +6,17 @@ module JAE-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jae Imm32:Imm, .Operands) => . + execinstr (jae Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) rule - execinstr (jae Imm32:Imm, .Operands) => . + execinstr (jae Imm32:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jae_rel8.k b/semantics/systemInstructions/jae_rel8.k index 4b2189dc2..059459b19 100644 --- a/semantics/systemInstructions/jae_rel8.k +++ b/semantics/systemInstructions/jae_rel8.k @@ -6,15 +6,17 @@ module JAE-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jae Imm8:Imm, .Operands) => . + execinstr (jae Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) rule - execinstr (jae Imm8:Imm, .Operands) => . + execinstr (jae Imm8:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jb_rel32.k b/semantics/systemInstructions/jb_rel32.k index 004b1bd55..d951f3789 100644 --- a/semantics/systemInstructions/jb_rel32.k +++ b/semantics/systemInstructions/jb_rel32.k @@ -6,15 +6,17 @@ module JB-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jb Imm32:Imm, .Operands) => . + execinstr (jb Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) rule - execinstr (jb Imm32:Imm, .Operands) => . + execinstr (jb Imm32:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jb_rel8.k b/semantics/systemInstructions/jb_rel8.k index 2054d3e2b..dfb9fd6fe 100644 --- a/semantics/systemInstructions/jb_rel8.k +++ b/semantics/systemInstructions/jb_rel8.k @@ -6,15 +6,17 @@ module JB-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jb Imm8:Imm, .Operands) => . + execinstr (jb Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) rule - execinstr (jb Imm8:Imm, .Operands) => . + execinstr (jb Imm8:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jbe_rel32.k b/semantics/systemInstructions/jbe_rel32.k index 2682bbf2c..3f64d6359 100644 --- a/semantics/systemInstructions/jbe_rel32.k +++ b/semantics/systemInstructions/jbe_rel32.k @@ -6,17 +6,19 @@ module JBE-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jbe Imm32:Imm, .Operands) => . + execinstr (jbe Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) - orBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + (eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + orBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1))) rule - execinstr (jbe Imm32:Imm, .Operands) => . + execinstr (jbe Imm32:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) - andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + (eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) + andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) endmodule diff --git a/semantics/systemInstructions/jbe_rel8.k b/semantics/systemInstructions/jbe_rel8.k index ed8c2ceae..b0c3bb039 100644 --- a/semantics/systemInstructions/jbe_rel8.k +++ b/semantics/systemInstructions/jbe_rel8.k @@ -6,17 +6,19 @@ module JBE-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jbe Imm8:Imm, .Operands) => . + execinstr (jbe Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) - orBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + orBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1))) rule - execinstr (jbe Imm8:Imm, .Operands) => . + execinstr (jbe Imm8:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) - andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) + andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) endmodule diff --git a/semantics/systemInstructions/jc_rel32.k b/semantics/systemInstructions/jc_rel32.k index e33369bbe..d75d1231b 100644 --- a/semantics/systemInstructions/jc_rel32.k +++ b/semantics/systemInstructions/jc_rel32.k @@ -6,15 +6,17 @@ module JC-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jc Imm32:Imm, .Operands) => . + execinstr (jc Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) rule - execinstr (jc Imm32:Imm, .Operands) => . + execinstr (jc Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jc_rel8.k b/semantics/systemInstructions/jc_rel8.k index 656ff31d8..07e2e66a1 100644 --- a/semantics/systemInstructions/jc_rel8.k +++ b/semantics/systemInstructions/jc_rel8.k @@ -6,15 +6,17 @@ module JC-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jc Imm8:Imm, .Operands) => . + execinstr (jc Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) rule - execinstr (jc Imm8:Imm, .Operands) => . + execinstr (jc Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/je_rel32.k b/semantics/systemInstructions/je_rel32.k index 2948258c5..3071bf335 100644 --- a/semantics/systemInstructions/je_rel32.k +++ b/semantics/systemInstructions/je_rel32.k @@ -6,15 +6,17 @@ module JE-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (je Imm32:Imm, .Operands) => . + execinstr (je Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) rule - execinstr (je Imm32:Imm, .Operands) => . + execinstr (je Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/je_rel8.k b/semantics/systemInstructions/je_rel8.k index 4d35997ca..204e8355c 100644 --- a/semantics/systemInstructions/je_rel8.k +++ b/semantics/systemInstructions/je_rel8.k @@ -6,15 +6,17 @@ module JE-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (je Imm8:Imm, .Operands) => . + execinstr (je Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) rule - execinstr (je Imm8:Imm, .Operands) => . + execinstr (je Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jecxz_rel8.k b/semantics/systemInstructions/jecxz_rel8.k index c6fe21868..60e07b1de 100644 --- a/semantics/systemInstructions/jecxz_rel8.k +++ b/semantics/systemInstructions/jecxz_rel8.k @@ -6,15 +6,17 @@ module JECXZ-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jecxz Imm8:Imm, .Operands) => . + execinstr (jecxz Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt(getRegisterValue(%ecx, RSMap), mi(32, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt(getRegisterValue(%ecx, RSMap), mi(32, 0)) rule - execinstr (jecxz Imm8:Imm, .Operands) => . + execinstr (jecxz Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt(getRegisterValue(%ecx, RSMap), mi(32, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt(getRegisterValue(%ecx, RSMap), mi(32, 0)) endmodule diff --git a/semantics/systemInstructions/jg_rel32.k b/semantics/systemInstructions/jg_rel32.k index 34847e9a4..295492de4 100644 --- a/semantics/systemInstructions/jg_rel32.k +++ b/semantics/systemInstructions/jg_rel32.k @@ -4,19 +4,21 @@ module JG-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jg Imm32:Imm, .Operands) => . + execinstr (jg Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + (eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) andBool - eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) rule - execinstr (jg Imm32:Imm, .Operands) => . + execinstr (jg Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + (notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) orBool - notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) endmodule diff --git a/semantics/systemInstructions/jg_rel8.k b/semantics/systemInstructions/jg_rel8.k index 2109d3880..49e48a412 100644 --- a/semantics/systemInstructions/jg_rel8.k +++ b/semantics/systemInstructions/jg_rel8.k @@ -4,19 +4,21 @@ module JG-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jg Imm8:Imm, .Operands) => . + execinstr (jg Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) andBool - eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) rule - execinstr (jg Imm8:Imm, .Operands) => . + execinstr (jg Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) orBool - notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) endmodule diff --git a/semantics/systemInstructions/jge_rel32.k b/semantics/systemInstructions/jge_rel32.k index 0ef51e517..a5e4ba1bb 100644 --- a/semantics/systemInstructions/jge_rel32.k +++ b/semantics/systemInstructions/jge_rel32.k @@ -4,15 +4,17 @@ module JGE-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jge Imm32:Imm, .Operands) => . + execinstr (jge Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) rule - execinstr (jge Imm32:Imm, .Operands) => . + execinstr (jge Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm32) ==Int 32 andBool + notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) endmodule diff --git a/semantics/systemInstructions/jge_rel8.k b/semantics/systemInstructions/jge_rel8.k index c8743fdc1..751e1bfd5 100644 --- a/semantics/systemInstructions/jge_rel8.k +++ b/semantics/systemInstructions/jge_rel8.k @@ -4,15 +4,17 @@ module JGE-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jge Imm8:Imm, .Operands) => . + execinstr (jge Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) rule - execinstr (jge Imm8:Imm, .Operands) => . + execinstr (jge Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) endmodule diff --git a/semantics/systemInstructions/jl_rel32.k b/semantics/systemInstructions/jl_rel32.k index 339a7b9ec..407ce8bc6 100644 --- a/semantics/systemInstructions/jl_rel32.k +++ b/semantics/systemInstructions/jl_rel32.k @@ -4,15 +4,17 @@ module JL-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jl Imm32:Imm, .Operands) => . + execinstr (jl Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm32) ==Int 32 andBool + notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) rule - execinstr (jl Imm32:Imm, .Operands) => . + execinstr (jl Imm32:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) endmodule diff --git a/semantics/systemInstructions/jl_rel8.k b/semantics/systemInstructions/jl_rel8.k index 68260efd4..0a1ab84b9 100644 --- a/semantics/systemInstructions/jl_rel8.k +++ b/semantics/systemInstructions/jl_rel8.k @@ -4,15 +4,17 @@ module JL-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jl Imm8:Imm, .Operands) => . + execinstr (jl Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) rule - execinstr (jl Imm8:Imm, .Operands) => . + execinstr (jl Imm8:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) endmodule diff --git a/semantics/systemInstructions/jle_rel32.k b/semantics/systemInstructions/jle_rel32.k index 0449a5c20..c2f827b94 100644 --- a/semantics/systemInstructions/jle_rel32.k +++ b/semantics/systemInstructions/jle_rel32.k @@ -4,19 +4,21 @@ module JLE-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jle Imm32:Imm, .Operands) => . + execinstr (jle Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + (eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) orBool - (notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) + (notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt))) rule - execinstr (jle Imm32:Imm, .Operands) => . + execinstr (jle Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + (notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) andBool - eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) endmodule diff --git a/semantics/systemInstructions/jle_rel8.k b/semantics/systemInstructions/jle_rel8.k index c901c2d30..f818684b9 100644 --- a/semantics/systemInstructions/jle_rel8.k +++ b/semantics/systemInstructions/jle_rel8.k @@ -4,19 +4,21 @@ module JLE-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jle Imm8:Imm, .Operands) => . + execinstr (jle Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) orBool - (notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) + (notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt))) rule - execinstr (jle Imm8:Imm, .Operands) => . + execinstr (jle Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) andBool - eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) endmodule diff --git a/semantics/systemInstructions/jmp_rel32.k b/semantics/systemInstructions/jmp_rel32.k index 65e64af0e..20f25aa3c 100644 --- a/semantics/systemInstructions/jmp_rel32.k +++ b/semantics/systemInstructions/jmp_rel32.k @@ -5,9 +5,10 @@ module JMPQ-REL32 imports X86-CONFIGURATION rule - execinstr (jmp Imm32:Imm, .Operands) => . + execinstr (jmp Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) + requires bitwidthMInt(Imm32) ==Int 32 endmodule diff --git a/semantics/systemInstructions/jmp_rel8.k b/semantics/systemInstructions/jmp_rel8.k index c6b80b5ce..3c940e93e 100644 --- a/semantics/systemInstructions/jmp_rel8.k +++ b/semantics/systemInstructions/jmp_rel8.k @@ -5,9 +5,10 @@ module JMPQ-REL8 imports X86-CONFIGURATION rule - execinstr (jmp Imm8:Imm, .Operands) => . + execinstr (jmp Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) + requires bitwidthMInt(Imm8) ==Int 8 endmodule diff --git a/semantics/systemInstructions/jna_rel32.k b/semantics/systemInstructions/jna_rel32.k index 54a425921..a2740b9e3 100644 --- a/semantics/systemInstructions/jna_rel32.k +++ b/semantics/systemInstructions/jna_rel32.k @@ -6,17 +6,19 @@ module JNA-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jna Imm32:Imm, .Operands) => . + execinstr (jna Imm32:MInt, .Operands) => . ... RSMap => updateMap(RSMap, ("RIP" |-> - addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, - 32, 64)))) + addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, + 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) orBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + (eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) orBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1))) rule - execinstr (jna Imm32:Imm, .Operands) => . + execinstr (jna Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) andBool notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + (notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) andBool notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1))) endmodule diff --git a/semantics/systemInstructions/jna_rel8.k b/semantics/systemInstructions/jna_rel8.k index 810660cc5..ae854f827 100644 --- a/semantics/systemInstructions/jna_rel8.k +++ b/semantics/systemInstructions/jna_rel8.k @@ -6,17 +6,19 @@ module JNA-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jna Imm8:Imm, .Operands) => . + execinstr (jna Imm8:MInt, .Operands) => . ... RSMap => updateMap(RSMap, ("RIP" |-> - addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, - 8, 64)))) + addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, + 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) orBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) orBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1))) rule - execinstr (jna Imm8:Imm, .Operands) => . + execinstr (jna Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) andBool notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) andBool notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1))) endmodule diff --git a/semantics/systemInstructions/jnae_rel32.k b/semantics/systemInstructions/jnae_rel32.k index 9c8d96d54..ac18612a0 100644 --- a/semantics/systemInstructions/jnae_rel32.k +++ b/semantics/systemInstructions/jnae_rel32.k @@ -6,15 +6,17 @@ module JNAE-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnae Imm32:Imm, .Operands) => . + execinstr (jnae Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) rule - execinstr (jnae Imm32:Imm, .Operands) => . + execinstr (jnae Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jnae_rel8.k b/semantics/systemInstructions/jnae_rel8.k index 1080e3fd4..9f5afa5dc 100644 --- a/semantics/systemInstructions/jnae_rel8.k +++ b/semantics/systemInstructions/jnae_rel8.k @@ -6,15 +6,17 @@ module JNAE-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnae Imm8:Imm, .Operands) => . + execinstr (jnae Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) rule - execinstr (jnae Imm8:Imm, .Operands) => . + execinstr (jnae Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jnb_rel32.k b/semantics/systemInstructions/jnb_rel32.k index 471150ca7..23760c8a5 100644 --- a/semantics/systemInstructions/jnb_rel32.k +++ b/semantics/systemInstructions/jnb_rel32.k @@ -6,15 +6,17 @@ module JNB-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnb Imm32:Imm, .Operands) => . + execinstr (jnb Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) rule - execinstr (jnb Imm32:Imm, .Operands) => . + execinstr (jnb Imm32:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jnb_rel8.k b/semantics/systemInstructions/jnb_rel8.k index 215a340da..d831e9646 100644 --- a/semantics/systemInstructions/jnb_rel8.k +++ b/semantics/systemInstructions/jnb_rel8.k @@ -6,15 +6,17 @@ module JNB-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnb Imm8:Imm, .Operands) => . + execinstr (jnb Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) rule - execinstr (jnb Imm8:Imm, .Operands) => . + execinstr (jnb Imm8:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jnbe_rel32.k b/semantics/systemInstructions/jnbe_rel32.k index d63320a24..f042a5fbe 100644 --- a/semantics/systemInstructions/jnbe_rel32.k +++ b/semantics/systemInstructions/jnbe_rel32.k @@ -6,18 +6,20 @@ module JNBE-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnbe Imm32:Imm, .Operands) => . + execinstr (jnbe Imm32:MInt, .Operands) => . ... RSMap => updateMap(RSMap, ("RIP" |-> - addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, - 32, 64)))) + addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, + 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + (eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) rule - execinstr (jnbe Imm32:Imm, .Operands) => . + execinstr (jnbe Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) - orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + (notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) + orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) endmodule diff --git a/semantics/systemInstructions/jnbe_rel8.k b/semantics/systemInstructions/jnbe_rel8.k index 5790a0235..ea4ef54ac 100644 --- a/semantics/systemInstructions/jnbe_rel8.k +++ b/semantics/systemInstructions/jnbe_rel8.k @@ -6,18 +6,20 @@ module JNBE-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnbe Imm8:Imm, .Operands) => . + execinstr (jnbe Imm8:MInt, .Operands) => . ... RSMap => updateMap(RSMap, ("RIP" |-> - addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, - 8, 64)))) + addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, + 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) rule - execinstr (jnbe Imm8:Imm, .Operands) => . + execinstr (jnbe Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) - orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (notBool eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) + orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) endmodule diff --git a/semantics/systemInstructions/jnc_rel32.k b/semantics/systemInstructions/jnc_rel32.k index c83c6ce85..4c86fa2f7 100644 --- a/semantics/systemInstructions/jnc_rel32.k +++ b/semantics/systemInstructions/jnc_rel32.k @@ -6,15 +6,17 @@ module JNC-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnc Imm32:Imm, .Operands) => . + execinstr (jnc Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) rule - execinstr (jnc Imm32:Imm, .Operands) => . + execinstr (jnc Imm32:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jnc_rel8.k b/semantics/systemInstructions/jnc_rel8.k index 409270d14..348665660 100644 --- a/semantics/systemInstructions/jnc_rel8.k +++ b/semantics/systemInstructions/jnc_rel8.k @@ -6,15 +6,17 @@ module JNC-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnc Imm8:Imm, .Operands) => . + execinstr (jnc Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 0)) rule - execinstr (jnc Imm8:Imm, .Operands) => . + execinstr (jnc Imm8:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["CF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jne_rel32.k b/semantics/systemInstructions/jne_rel32.k index df758fe3b..3ef4d9f48 100644 --- a/semantics/systemInstructions/jne_rel32.k +++ b/semantics/systemInstructions/jne_rel32.k @@ -6,15 +6,17 @@ module JNE-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jne Imm32:Imm, .Operands) => . + execinstr (jne Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) rule - execinstr (jne Imm32:Imm, .Operands) => . + execinstr (jne Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jne_rel8.k b/semantics/systemInstructions/jne_rel8.k index d6fbd8aca..d442a86c0 100644 --- a/semantics/systemInstructions/jne_rel8.k +++ b/semantics/systemInstructions/jne_rel8.k @@ -6,15 +6,17 @@ module JNE-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jne Imm8:Imm, .Operands) => . + execinstr (jne Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) rule - execinstr (jne Imm8:Imm, .Operands) => . + execinstr (jne Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jng_rel32.k b/semantics/systemInstructions/jng_rel32.k index 8706aaf5e..4f9fafeda 100644 --- a/semantics/systemInstructions/jng_rel32.k +++ b/semantics/systemInstructions/jng_rel32.k @@ -6,15 +6,17 @@ module JNG-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jng Imm32:Imm, .Operands) => . + execinstr (jng Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) orBool notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm32) ==Int 32 andBool + (eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) orBool notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) rule - execinstr (jng Imm32:Imm, .Operands) => . + execinstr (jng Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) andBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm32) ==Int 32 andBool + (notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) andBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) endmodule diff --git a/semantics/systemInstructions/jng_rel8.k b/semantics/systemInstructions/jng_rel8.k index b15e8f7c0..d8b505c01 100644 --- a/semantics/systemInstructions/jng_rel8.k +++ b/semantics/systemInstructions/jng_rel8.k @@ -6,15 +6,17 @@ module JNG-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jng Imm8:Imm, .Operands) => . + execinstr (jng Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) orBool notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) orBool notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) rule - execinstr (jng Imm8:Imm, .Operands) => . + execinstr (jng Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) andBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) andBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) endmodule diff --git a/semantics/systemInstructions/jnge_rel32.k b/semantics/systemInstructions/jnge_rel32.k index a49f5d310..a04ced00d 100644 --- a/semantics/systemInstructions/jnge_rel32.k +++ b/semantics/systemInstructions/jnge_rel32.k @@ -6,15 +6,17 @@ module JNGE-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnge Imm32:Imm, .Operands) => . + execinstr (jnge Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm32) ==Int 32 andBool + notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) rule - execinstr (jnge Imm32:Imm, .Operands) => . + execinstr (jnge Imm32:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) endmodule diff --git a/semantics/systemInstructions/jnge_rel8.k b/semantics/systemInstructions/jnge_rel8.k index e6cafc657..adf16426e 100644 --- a/semantics/systemInstructions/jnge_rel8.k +++ b/semantics/systemInstructions/jnge_rel8.k @@ -6,15 +6,17 @@ module JNGE-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnge Imm8:Imm, .Operands) => . + execinstr (jnge Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) rule - execinstr (jnge Imm8:Imm, .Operands) => . + execinstr (jnge Imm8:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) endmodule diff --git a/semantics/systemInstructions/jnl_rel32.k b/semantics/systemInstructions/jnl_rel32.k index 0777ad103..440ddf0ea 100644 --- a/semantics/systemInstructions/jnl_rel32.k +++ b/semantics/systemInstructions/jnl_rel32.k @@ -6,15 +6,17 @@ module JNL-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnl Imm32:Imm, .Operands) => . + execinstr (jnl Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) rule - execinstr (jnl Imm32:Imm, .Operands) => . + execinstr (jnl Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm32) ==Int 32 andBool + notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) endmodule diff --git a/semantics/systemInstructions/jnl_rel8.k b/semantics/systemInstructions/jnl_rel8.k index 0db8374fb..50f56302d 100644 --- a/semantics/systemInstructions/jnl_rel8.k +++ b/semantics/systemInstructions/jnl_rel8.k @@ -6,15 +6,17 @@ module JNL-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnl Imm8:Imm, .Operands) => . + execinstr (jnl Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) rule - execinstr (jnl Imm8:Imm, .Operands) => . + execinstr (jnl Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) endmodule diff --git a/semantics/systemInstructions/jnle_rel32.k b/semantics/systemInstructions/jnle_rel32.k index 038a3e6a5..e772fc77a 100644 --- a/semantics/systemInstructions/jnle_rel32.k +++ b/semantics/systemInstructions/jnle_rel32.k @@ -6,15 +6,17 @@ module JNLE-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnle Imm32:Imm, .Operands) => . + execinstr (jnle Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm32) ==Int 32 andBool + (eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) rule - execinstr (jnle Imm32:Imm, .Operands) => . + execinstr (jnle Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) orBool notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm32) ==Int 32 andBool + (notBool eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) orBool notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) endmodule diff --git a/semantics/systemInstructions/jnle_rel8.k b/semantics/systemInstructions/jnle_rel8.k index 188425453..44fd34677 100644 --- a/semantics/systemInstructions/jnle_rel8.k +++ b/semantics/systemInstructions/jnle_rel8.k @@ -6,15 +6,17 @@ module JNLE-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnle Imm8:Imm, .Operands) => . + execinstr (jnle Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) andBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) rule - execinstr (jnle Imm8:Imm, .Operands) => . + execinstr (jnle Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) orBool notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (notBool eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) orBool notBool eqMInt({RSMap["SF"]}:>MInt, {RSMap["OF"]}:>MInt)) endmodule diff --git a/semantics/systemInstructions/jno_rel32.k b/semantics/systemInstructions/jno_rel32.k index 52ca31290..593c31f33 100644 --- a/semantics/systemInstructions/jno_rel32.k +++ b/semantics/systemInstructions/jno_rel32.k @@ -6,15 +6,17 @@ module JNO-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jno Imm32:Imm, .Operands) => . + execinstr (jno Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["OF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["OF"]}:>MInt, mi(1, 0)) rule - execinstr (jno Imm32:Imm, .Operands) => . + execinstr (jno Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["OF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + notBool eqMInt({RSMap["OF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jno_rel8.k b/semantics/systemInstructions/jno_rel8.k index dbb1e0ce8..8741ffeef 100644 --- a/semantics/systemInstructions/jno_rel8.k +++ b/semantics/systemInstructions/jno_rel8.k @@ -6,15 +6,17 @@ module JNO-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jno Imm8:Imm, .Operands) => . + execinstr (jno Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["OF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["OF"]}:>MInt, mi(1, 0)) rule - execinstr (jno Imm8:Imm, .Operands) => . + execinstr (jno Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["OF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt({RSMap["OF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jnp_rel32.k b/semantics/systemInstructions/jnp_rel32.k index c44e8957b..68adf18c3 100644 --- a/semantics/systemInstructions/jnp_rel32.k +++ b/semantics/systemInstructions/jnp_rel32.k @@ -6,15 +6,17 @@ module JNP-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnp Imm32:Imm, .Operands) => . + execinstr (jnp Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) rule - execinstr (jnp Imm32:Imm, .Operands) => . + execinstr (jnp Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + notBool eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jnp_rel8.k b/semantics/systemInstructions/jnp_rel8.k index 0a0509c8b..9a54f70a8 100644 --- a/semantics/systemInstructions/jnp_rel8.k +++ b/semantics/systemInstructions/jnp_rel8.k @@ -6,15 +6,17 @@ module JNP-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnp Imm8:Imm, .Operands) => . + execinstr (jnp Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) rule - execinstr (jnp Imm8:Imm, .Operands) => . + execinstr (jnp Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jns_rel32.k b/semantics/systemInstructions/jns_rel32.k index e0f6b0b25..7e2a9b089 100644 --- a/semantics/systemInstructions/jns_rel32.k +++ b/semantics/systemInstructions/jns_rel32.k @@ -6,15 +6,17 @@ module JNS-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jns Imm32:Imm, .Operands) => . + execinstr (jns Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) rule - execinstr (jns Imm32:Imm, .Operands) => . + execinstr (jns Imm32:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["SF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["SF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jns_rel8.k b/semantics/systemInstructions/jns_rel8.k index ee3a25cdc..25353444d 100644 --- a/semantics/systemInstructions/jns_rel8.k +++ b/semantics/systemInstructions/jns_rel8.k @@ -6,15 +6,17 @@ module JNS-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jns Imm8:Imm, .Operands) => . + execinstr (jns Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) rule - execinstr (jns Imm8:Imm, .Operands) => . + execinstr (jns Imm8:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["SF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["SF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jnz_rel32.k b/semantics/systemInstructions/jnz_rel32.k index c4758b651..25380d73a 100644 --- a/semantics/systemInstructions/jnz_rel32.k +++ b/semantics/systemInstructions/jnz_rel32.k @@ -6,15 +6,17 @@ module JNZ-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnz Imm32:Imm, .Operands) => . + execinstr (jnz Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) rule - execinstr (jnz Imm32:Imm, .Operands) => . + execinstr (jnz Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jnz_rel8.k b/semantics/systemInstructions/jnz_rel8.k index 841e64a95..beeb4f24b 100644 --- a/semantics/systemInstructions/jnz_rel8.k +++ b/semantics/systemInstructions/jnz_rel8.k @@ -6,15 +6,17 @@ module JNZ-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jnz Imm8:Imm, .Operands) => . + execinstr (jnz Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) rule - execinstr (jnz Imm8:Imm, .Operands) => . + execinstr (jnz Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jo_rel32.k b/semantics/systemInstructions/jo_rel32.k index 86a412670..fe453c6f6 100644 --- a/semantics/systemInstructions/jo_rel32.k +++ b/semantics/systemInstructions/jo_rel32.k @@ -6,15 +6,17 @@ module JO-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jo Imm32:Imm, .Operands) => . + execinstr (jo Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["OF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["OF"]}:>MInt, mi(1, 1)) rule - execinstr (jo Imm32:Imm, .Operands) => . + execinstr (jo Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["OF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + notBool eqMInt({RSMap["OF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jo_rel8.k b/semantics/systemInstructions/jo_rel8.k index 739212785..4affc1844 100644 --- a/semantics/systemInstructions/jo_rel8.k +++ b/semantics/systemInstructions/jo_rel8.k @@ -6,15 +6,17 @@ module JO-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jo Imm8:Imm, .Operands) => . + execinstr (jo Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["OF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["OF"]}:>MInt, mi(1, 1)) rule - execinstr (jo Imm8:Imm, .Operands) => . + execinstr (jo Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["OF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt({RSMap["OF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jp_rel32.k b/semantics/systemInstructions/jp_rel32.k index 8733bf2df..ad9524a68 100644 --- a/semantics/systemInstructions/jp_rel32.k +++ b/semantics/systemInstructions/jp_rel32.k @@ -6,15 +6,17 @@ module JP-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jp Imm32:Imm, .Operands) => . + execinstr (jp Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["PF"]}:>MInt, mi(1, 1)) rule - execinstr (jp Imm32:Imm, .Operands) => . + execinstr (jp Imm32:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jp_rel8.k b/semantics/systemInstructions/jp_rel8.k index f96cfcf61..1bcddf0b4 100644 --- a/semantics/systemInstructions/jp_rel8.k +++ b/semantics/systemInstructions/jp_rel8.k @@ -6,15 +6,17 @@ module JP-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jp Imm8:Imm, .Operands) => . + execinstr (jp Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["PF"]}:>MInt, mi(1, 1)) rule - execinstr (jp Imm8:Imm, .Operands) => . + execinstr (jp Imm8:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jpe_rel32.k b/semantics/systemInstructions/jpe_rel32.k index 6508fdad4..31522376b 100644 --- a/semantics/systemInstructions/jpe_rel32.k +++ b/semantics/systemInstructions/jpe_rel32.k @@ -6,15 +6,17 @@ module JPE-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jpe Imm32:Imm, .Operands) => . + execinstr (jpe Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["PF"]}:>MInt, mi(1, 1)) rule - execinstr (jpe Imm32:Imm, .Operands) => . + execinstr (jpe Imm32:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jpe_rel8.k b/semantics/systemInstructions/jpe_rel8.k index d812fa336..ef6bb2dbc 100644 --- a/semantics/systemInstructions/jpe_rel8.k +++ b/semantics/systemInstructions/jpe_rel8.k @@ -6,15 +6,17 @@ module JPE-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jpe Imm8:Imm, .Operands) => . + execinstr (jpe Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["PF"]}:>MInt, mi(1, 1)) rule - execinstr (jpe Imm8:Imm, .Operands) => . + execinstr (jpe Imm8:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jpo_rel32.k b/semantics/systemInstructions/jpo_rel32.k index 1c2b4518f..ee70f0267 100644 --- a/semantics/systemInstructions/jpo_rel32.k +++ b/semantics/systemInstructions/jpo_rel32.k @@ -6,15 +6,17 @@ module JPO-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jpo Imm32:Imm, .Operands) => . + execinstr (jpo Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) rule - execinstr (jpo Imm32:Imm, .Operands) => . + execinstr (jpo Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + notBool eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jpo_rel8.k b/semantics/systemInstructions/jpo_rel8.k index 3cafc614b..45a4d5ca6 100644 --- a/semantics/systemInstructions/jpo_rel8.k +++ b/semantics/systemInstructions/jpo_rel8.k @@ -6,15 +6,17 @@ module JPO-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jpo Imm8:Imm, .Operands) => . + execinstr (jpo Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) rule - execinstr (jpo Imm8:Imm, .Operands) => . + execinstr (jpo Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt({RSMap["PF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jrcxz_rel8.k b/semantics/systemInstructions/jrcxz_rel8.k index a95d4d5e6..6c5be105f 100644 --- a/semantics/systemInstructions/jrcxz_rel8.k +++ b/semantics/systemInstructions/jrcxz_rel8.k @@ -6,15 +6,17 @@ module JRCXZ-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jrcxz Imm8:Imm, .Operands) => . + execinstr (jrcxz Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt(getRegisterValue(%rcx, RSMap), mi(64, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt(getRegisterValue(%rcx, RSMap), mi(64, 0)) rule - execinstr (jrcxz Imm8:Imm, .Operands) => . + execinstr (jrcxz Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt(getRegisterValue(%rcx, RSMap), mi(64, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt(getRegisterValue(%rcx, RSMap), mi(64, 0)) endmodule diff --git a/semantics/systemInstructions/js_rel32.k b/semantics/systemInstructions/js_rel32.k index 1de9d7f0a..50b6dcf19 100644 --- a/semantics/systemInstructions/js_rel32.k +++ b/semantics/systemInstructions/js_rel32.k @@ -6,15 +6,17 @@ module JS-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (js Imm32:Imm, .Operands) => . + execinstr (js Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["SF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["SF"]}:>MInt, mi(1, 1)) rule - execinstr (js Imm32:Imm, .Operands) => . + execinstr (js Imm32:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/js_rel8.k b/semantics/systemInstructions/js_rel8.k index 4f4c10f99..4d1431c76 100644 --- a/semantics/systemInstructions/js_rel8.k +++ b/semantics/systemInstructions/js_rel8.k @@ -6,15 +6,17 @@ module JS-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (js Imm8:Imm, .Operands) => . + execinstr (js Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["SF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["SF"]}:>MInt, mi(1, 1)) rule - execinstr (js Imm8:Imm, .Operands) => . + execinstr (js Imm8:MInt, .Operands) => . ... RSMap:Map - requires eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["SF"]}:>MInt, mi(1, 0)) endmodule diff --git a/semantics/systemInstructions/jz_rel32.k b/semantics/systemInstructions/jz_rel32.k index 2b9b564ca..788921fe5 100644 --- a/semantics/systemInstructions/jz_rel32.k +++ b/semantics/systemInstructions/jz_rel32.k @@ -6,15 +6,17 @@ module JZ-REL32 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jz Imm32:Imm, .Operands) => . + execinstr (jz Imm32:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm32, 32, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm32, 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) rule - execinstr (jz Imm32:Imm, .Operands) => . + execinstr (jz Imm32:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm32) ==Int 32 andBool + notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/jz_rel8.k b/semantics/systemInstructions/jz_rel8.k index 2e216103a..a57a3d65a 100644 --- a/semantics/systemInstructions/jz_rel8.k +++ b/semantics/systemInstructions/jz_rel8.k @@ -6,15 +6,17 @@ module JZ-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (jz Imm8:Imm, .Operands) => . + execinstr (jz Imm8:MInt, .Operands) => . ... - RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64)))) + RSMap => updateMap(RSMap, ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64)))) - requires eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) rule - execinstr (jz Imm8:Imm, .Operands) => . + execinstr (jz Imm8:MInt, .Operands) => . ... RSMap:Map - requires notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) endmodule diff --git a/semantics/systemInstructions/loop_rel8.k b/semantics/systemInstructions/loop_rel8.k index afacd9541..e490e63f1 100644 --- a/semantics/systemInstructions/loop_rel8.k +++ b/semantics/systemInstructions/loop_rel8.k @@ -6,27 +6,30 @@ module LOOP-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (loop Imm8:Imm, .Operands) => execinstr (loop Imm8, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) + execinstr (loop Imm8:MInt, .Operands) => execinstr (loop Imm8, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule - execinstr (loop Imm8:Imm, Count:MInt, .Operands) => . + execinstr (loop Imm8:MInt, Count:MInt, .Operands) => . ... RSMap => updateMap(RSMap, - ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64))) + ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64))) ("RCX" |-> Count) ) - requires notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) rule - execinstr (loop Imm8:Imm, Count:MInt, .Operands) => . + execinstr (loop Imm8:MInt, Count:MInt, .Operands) => . ... RSMap => updateMap(RSMap, ("RCX" |-> Count) ) - requires eqMInt(Count, mi(bitwidthMInt(Count), 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + eqMInt(Count, mi(bitwidthMInt(Count), 0)) endmodule diff --git a/semantics/systemInstructions/loope_rel8.k b/semantics/systemInstructions/loope_rel8.k index d904ef8a0..140a98d9d 100644 --- a/semantics/systemInstructions/loope_rel8.k +++ b/semantics/systemInstructions/loope_rel8.k @@ -6,29 +6,32 @@ module LOOPE-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (loope Imm8:Imm, .Operands) => execinstr (loope Imm8, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) + execinstr (loope Imm8:MInt, .Operands) => execinstr (loope Imm8, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule - execinstr (loope Imm8:Imm, Count:MInt, .Operands) => . + execinstr (loope Imm8:MInt, Count:MInt, .Operands) => . ... RSMap => updateMap(RSMap, - ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64))) + ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64))) ("RCX" |-> Count) ) - requires notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) - andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) + andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1))) rule - execinstr (loope Imm8:Imm, Count:MInt, .Operands) => . + execinstr (loope Imm8:MInt, Count:MInt, .Operands) => . ... RSMap => updateMap(RSMap, ("RCX" |-> Count) ) - requires eqMInt(Count, mi(bitwidthMInt(Count), 0)) - orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (eqMInt(Count, mi(bitwidthMInt(Count), 0)) + orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1))) endmodule diff --git a/semantics/systemInstructions/loopne_rel8.k b/semantics/systemInstructions/loopne_rel8.k index df3a61da7..a6cde7c73 100644 --- a/semantics/systemInstructions/loopne_rel8.k +++ b/semantics/systemInstructions/loopne_rel8.k @@ -6,29 +6,32 @@ module LOOPNE-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (loopne Imm8:Imm, .Operands) => execinstr (loope Imm8, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) + execinstr (loopne Imm8:MInt, .Operands) => execinstr (loope Imm8, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule - execinstr (loopne Imm8:Imm, Count:MInt, .Operands) => . + execinstr (loopne Imm8:MInt, Count:MInt, .Operands) => . ... RSMap => updateMap(RSMap, - ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64))) + ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64))) ("RCX" |-> Count) ) - requires notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) - andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) + andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) rule - execinstr (loopne Imm8:Imm, Count:MInt, .Operands) => . + execinstr (loopne Imm8:MInt, Count:MInt, .Operands) => . ... RSMap => updateMap(RSMap, ("RCX" |-> Count) ) - requires eqMInt(Count, mi(bitwidthMInt(Count), 0)) - orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + (eqMInt(Count, mi(bitwidthMInt(Count), 0)) + orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) endmodule diff --git a/semantics/systemInstructions/loopnz_rel8.k b/semantics/systemInstructions/loopnz_rel8.k index c37403c96..bf1b354b7 100644 --- a/semantics/systemInstructions/loopnz_rel8.k +++ b/semantics/systemInstructions/loopnz_rel8.k @@ -6,29 +6,32 @@ module LOOPNE-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (loopnz Imm8:Imm, .Operands) => execinstr (loopnz Imm8, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) + execinstr (loopnz Imm8:MInt, .Operands) => execinstr (loopnz Imm8, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule - execinstr (loopnz Imm8:Imm, Count:MInt, .Operands) => . + execinstr (loopnz Imm8:MInt, Count:MInt, .Operands) => . ... RSMap => updateMap(RSMap, - ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64))) + ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64))) ("RCX" |-> Count) ) - requires notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) - andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + ( notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) + andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) rule - execinstr (loopnz Imm8:Imm, Count:MInt, .Operands) => . + execinstr (loopnz Imm8:MInt, Count:MInt, .Operands) => . ... RSMap => updateMap(RSMap, ("RCX" |-> Count) ) - requires eqMInt(Count, mi(bitwidthMInt(Count), 0)) - orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + ( eqMInt(Count, mi(bitwidthMInt(Count), 0)) + orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 0))) endmodule diff --git a/semantics/systemInstructions/loopz_rel8.k b/semantics/systemInstructions/loopz_rel8.k index 444e23955..cfa525dd6 100644 --- a/semantics/systemInstructions/loopz_rel8.k +++ b/semantics/systemInstructions/loopz_rel8.k @@ -6,29 +6,32 @@ module LOOPE-REL8 imports X86-FLAG-CHECS-SYNTAX rule - execinstr (loopz Imm8:Imm, .Operands) => execinstr (loopz Imm8, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) + execinstr (loopz Imm8:MInt, .Operands) => execinstr (loopz Imm8, subMInt(getRegisterValue(%rcx, RSMap), mi(64, 1)), .Operands) ... RSMap + requires bitwidthMInt(Imm8) ==Int 8 rule - execinstr (loopz Imm8:Imm, Count:MInt, .Operands) => . + execinstr (loopz Imm8:MInt, Count:MInt, .Operands) => . ... RSMap => updateMap(RSMap, - ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, handleImmediateWithSignExtend(Imm8, 8, 64))) + ("RIP" |-> addMInt({RSMap["RIP"]}:>MInt, signExtend(Imm8, 64))) ("RCX" |-> Count) ) - requires notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) - andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + ( notBool eqMInt(Count, mi(bitwidthMInt(Count), 0)) + andBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1))) rule - execinstr (loopz Imm8:Imm, Count:MInt, .Operands) => . + execinstr (loopz Imm8:MInt, Count:MInt, .Operands) => . ... RSMap => updateMap(RSMap, ("RCX" |-> Count) ) - requires eqMInt(Count, mi(bitwidthMInt(Count), 0)) - orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1)) + requires bitwidthMInt(Imm8) ==Int 8 andBool + ( eqMInt(Count, mi(bitwidthMInt(Count), 0)) + orBool notBool eqMInt({RSMap["ZF"]}:>MInt, mi(1, 1))) endmodule From 5286c220625f34e7f0112ee5d7dd882071d6f1d2 Mon Sep 17 00:00:00 2001 From: andrew_miranti Date: Thu, 28 Feb 2019 13:41:36 -0600 Subject: [PATCH 12/15] Woops --- docs/z3_artifcats/array2.z3 | 11 +++ docs/z3_artifcats/datatypes.z3 | 7 ++ semantics/a.out | Bin 0 -> 912816 bytes .../common/library/common-c-library-stdio.k | 44 ++++++------ semantics/common/library/common-c-library.k | 8 +-- .../immediateInstructions/adcb_al_imm8.k | 17 ++--- .../immediateInstructions/adcb_r8_imm8.k | 17 ++--- .../immediateInstructions/adcb_rh_imm8.k | 17 ++--- .../immediateInstructions/adcl_eax_imm32.k | 17 ++--- .../immediateInstructions/adcl_r32_imm32.k | 17 ++--- .../immediateInstructions/adcl_r32_imm8.k | 17 ++--- .../immediateInstructions/adcq_r64_imm32.k | 17 ++--- .../immediateInstructions/adcq_r64_imm8.k | 17 ++--- .../immediateInstructions/adcq_rax_imm32.k | 17 ++--- .../immediateInstructions/adcw_ax_imm16.k | 17 ++--- .../immediateInstructions/adcw_r16_imm16.k | 17 ++--- .../immediateInstructions/adcw_r16_imm8.k | 17 ++--- .../immediateInstructions/addb_al_imm8.k | 17 ++--- .../immediateInstructions/addb_r8_imm8.k | 17 ++--- .../immediateInstructions/addb_rh_imm8.k | 17 ++--- .../immediateInstructions/addl_eax_imm32.k | 17 ++--- .../immediateInstructions/addl_r32_imm32.k | 17 ++--- .../immediateInstructions/addl_r32_imm8.k | 17 ++--- .../immediateInstructions/addq_r64_imm32.k | 17 ++--- .../immediateInstructions/addq_r64_imm8.k | 17 ++--- .../immediateInstructions/addq_rax_imm32.k | 17 ++--- .../immediateInstructions/addw_ax_imm16.k | 17 ++--- .../immediateInstructions/addw_r16_imm16.k | 17 ++--- .../immediateInstructions/addw_r16_imm8.k | 17 ++--- .../immediateInstructions/andb_al_imm8.k | 11 +-- .../immediateInstructions/andb_r8_imm8.k | 11 +-- .../immediateInstructions/andb_rh_imm8.k | 11 +-- .../immediateInstructions/andl_eax_imm32.k | 11 +-- .../immediateInstructions/andl_r32_imm32.k | 11 +-- .../immediateInstructions/andl_r32_imm8.k | 11 +-- .../immediateInstructions/andq_r64_imm32.k | 11 +-- .../immediateInstructions/andq_r64_imm8.k | 11 +-- .../immediateInstructions/andq_rax_imm32.k | 11 +-- .../immediateInstructions/andw_ax_imm16.k | 11 +-- .../immediateInstructions/andw_r16_imm16.k | 11 +-- .../immediateInstructions/andw_r16_imm8.k | 11 +-- .../blendpd_xmm_xmm_imm8.k | 5 +- .../blendps_xmm_xmm_imm8.k | 5 +- .../immediateInstructions/btcl_r32_imm8.k | 7 +- .../immediateInstructions/btcq_r64_imm8.k | 7 +- .../immediateInstructions/btcw_r16_imm8.k | 7 +- .../immediateInstructions/btl_r32_imm8.k | 5 +- .../immediateInstructions/btq_r64_imm8.k | 5 +- .../immediateInstructions/btrl_r32_imm8.k | 7 +- .../immediateInstructions/btrq_r64_imm8.k | 7 +- .../immediateInstructions/btrw_r16_imm8.k | 7 +- .../immediateInstructions/btsl_r32_imm8.k | 7 +- .../immediateInstructions/btsq_r64_imm8.k | 7 +- .../immediateInstructions/btsw_r16_imm8.k | 7 +- .../immediateInstructions/btw_r16_imm8.k | 5 +- .../immediateInstructions/cmpb_al_imm8.k | 15 +++-- .../immediateInstructions/cmpb_r8_imm8.k | 15 +++-- .../immediateInstructions/cmpb_rh_imm8.k | 15 +++-- .../immediateInstructions/cmpl_eax_imm32.k | 15 +++-- .../immediateInstructions/cmpl_r32_imm32.k | 15 +++-- .../immediateInstructions/cmpl_r32_imm8.k | 15 +++-- .../cmppd_xmm_xmm_imm8.k | 5 +- .../cmpps_xmm_xmm_imm8.k | 5 +- .../immediateInstructions/cmpq_r64_imm32.k | 15 +++-- .../immediateInstructions/cmpq_r64_imm8.k | 15 +++-- .../immediateInstructions/cmpq_rax_imm32.k | 15 +++-- .../cmpsd_xmm_xmm_imm8.k | 5 +- .../cmpss_xmm_xmm_imm8.k | 5 +- .../immediateInstructions/cmpw_ax_imm16.k | 15 +++-- .../immediateInstructions/cmpw_r16_imm16.k | 15 +++-- .../immediateInstructions/cmpw_r16_imm8.k | 15 +++-- .../immediateInstructions/dppd_xmm_xmm_imm8.k | 5 +- .../immediateInstructions/dpps_xmm_xmm_imm8.k | 5 +- .../extractps_r32_xmm_imm8.k | 5 +- .../extractps_r64_xmm_imm8.k | 5 +- .../imull_r32_r32_imm32.k | 9 +-- .../imull_r32_r32_imm8.k | 9 +-- .../imulq_r64_r64_imm32.k | 9 +-- .../imulq_r64_r64_imm8.k | 9 +-- .../imulw_r16_r16_imm16.k | 9 +-- .../imulw_r16_r16_imm8.k | 9 +-- .../insertps_xmm_xmm_imm8.k | 5 +- .../immediateInstructions/movb_r8_imm8.k | 5 +- .../immediateInstructions/movb_rh_imm8.k | 5 +- .../immediateInstructions/movl_r32_imm32.k | 5 +- .../immediateInstructions/movq_r64_imm32.k | 5 +- .../immediateInstructions/movq_r64_imm64.k | 5 +- .../immediateInstructions/movw_r16_imm16.k | 5 +- .../mpsadbw_xmm_xmm_imm8.k | 33 ++++----- semantics/immediateInstructions/orb_al_imm8.k | 11 +-- semantics/immediateInstructions/orb_r8_imm8.k | 11 +-- semantics/immediateInstructions/orb_rh_imm8.k | 11 +-- .../immediateInstructions/orl_eax_imm32.k | 11 +-- .../immediateInstructions/orl_r32_imm32.k | 11 +-- .../immediateInstructions/orl_r32_imm8.k | 11 +-- .../immediateInstructions/orq_r64_imm32.k | 11 +-- .../immediateInstructions/orq_r64_imm8.k | 11 +-- .../immediateInstructions/orq_rax_imm32.k | 11 +-- .../immediateInstructions/orw_ax_imm16.k | 11 +-- .../immediateInstructions/orw_r16_imm16.k | 11 +-- .../immediateInstructions/orw_r16_imm8.k | 11 +-- .../palignr_xmm_xmm_imm8.k | 5 +- .../pblendw_xmm_xmm_imm8.k | 5 +- .../pclmulqdq_xmm_xmm_imm8.k | 9 ++- .../pcmpestri_xmm_xmm_imm8.k | 9 +-- .../pcmpestrm_xmm_xmm_imm8.k | 9 +-- .../pcmpistri_xmm_xmm_imm8.k | 9 +-- .../pcmpistrm_xmm_xmm_imm8.k | 9 +-- .../pextrb_r32_xmm_imm8.k | 5 +- .../pextrb_r64_xmm_imm8.k | 5 +- .../pextrd_r32_xmm_imm8.k | 5 +- .../pextrq_r64_xmm_imm8.k | 5 +- .../pextrw_r32_xmm_imm8.k | 5 +- .../pextrw_r64_xmm_imm8.k | 5 +- .../pinsrb_xmm_r32_imm8.k | 5 +- .../pinsrd_xmm_r32_imm8.k | 5 +- .../pinsrq_xmm_r64_imm8.k | 5 +- .../pinsrw_xmm_r32_imm8.k | 5 +- .../pshufd_xmm_xmm_imm8.k | 5 +- .../pshufhw_xmm_xmm_imm8.k | 5 +- .../pshuflw_xmm_xmm_imm8.k | 5 +- .../immediateInstructions/pslld_xmm_imm8.k | 5 +- .../immediateInstructions/pslldq_xmm_imm8.k | 5 +- .../immediateInstructions/psllq_xmm_imm8.k | 5 +- .../immediateInstructions/psllw_xmm_imm8.k | 5 +- .../immediateInstructions/psrad_xmm_imm8.k | 5 +- .../immediateInstructions/psraw_xmm_imm8.k | 5 +- .../immediateInstructions/psrld_xmm_imm8.k | 5 +- .../immediateInstructions/psrldq_xmm_imm8.k | 5 +- .../immediateInstructions/psrlq_xmm_imm8.k | 5 +- .../immediateInstructions/psrlw_xmm_imm8.k | 5 +- semantics/immediateInstructions/pushq_imm32.k | 5 +- .../immediateInstructions/rclb_r8_imm8.k | 9 +-- .../immediateInstructions/rclb_rh_imm8.k | 9 +-- .../immediateInstructions/rcll_r32_imm8.k | 9 +-- .../immediateInstructions/rclq_r64_imm8.k | 9 +-- .../immediateInstructions/rclw_r16_imm8.k | 9 +-- .../immediateInstructions/rcrb_r8_imm8.k | 9 +-- .../immediateInstructions/rcrb_rh_imm8.k | 9 +-- .../immediateInstructions/rcrl_r32_imm8.k | 9 +-- .../immediateInstructions/rcrq_r64_imm8.k | 9 +-- .../immediateInstructions/rcrw_r16_imm8.k | 9 +-- .../immediateInstructions/rolb_r8_imm8.k | 9 +-- .../immediateInstructions/rolb_rh_imm8.k | 9 +-- .../immediateInstructions/roll_r32_imm8.k | 9 +-- .../immediateInstructions/rolq_r64_imm8.k | 9 +-- .../immediateInstructions/rolw_r16_imm8.k | 9 +-- .../immediateInstructions/rorb_r8_imm8.k | 9 +-- .../immediateInstructions/rorb_rh_imm8.k | 9 +-- .../immediateInstructions/rorl_r32_imm8.k | 9 +-- .../immediateInstructions/rorq_r64_imm8.k | 9 +-- .../immediateInstructions/rorw_r16_imm8.k | 9 +-- .../rorxl_r32_r32_imm8.k | 7 +- .../rorxq_r64_r64_imm8.k | 7 +- .../roundpd_xmm_xmm_imm8.k | 5 +- .../roundps_xmm_xmm_imm8.k | 5 +- .../roundsd_xmm_xmm_imm8.k | 5 +- .../roundss_xmm_xmm_imm8.k | 5 +- .../immediateInstructions/salb_r8_imm8.k | 17 ++--- .../immediateInstructions/salb_rh_imm8.k | 17 ++--- .../immediateInstructions/sall_r32_imm8.k | 17 ++--- .../immediateInstructions/salq_r64_imm8.k | 17 ++--- .../immediateInstructions/salw_r16_imm8.k | 17 ++--- .../immediateInstructions/sarb_r8_imm8.k | 17 ++--- .../immediateInstructions/sarb_rh_imm8.k | 17 ++--- .../immediateInstructions/sarl_r32_imm8.k | 17 ++--- .../immediateInstructions/sarq_r64_imm8.k | 17 ++--- .../immediateInstructions/sarw_r16_imm8.k | 17 ++--- .../immediateInstructions/sbbb_al_imm8.k | 17 ++--- .../immediateInstructions/sbbb_r8_imm8.k | 17 ++--- .../immediateInstructions/sbbb_rh_imm8.k | 17 ++--- .../immediateInstructions/sbbl_eax_imm32.k | 17 ++--- .../immediateInstructions/sbbl_r32_imm32.k | 17 ++--- .../immediateInstructions/sbbl_r32_imm8.k | 17 ++--- .../immediateInstructions/sbbq_r64_imm32.k | 17 ++--- .../immediateInstructions/sbbq_r64_imm8.k | 17 ++--- .../immediateInstructions/sbbq_rax_imm32.k | 17 ++--- .../immediateInstructions/sbbw_ax_imm16.k | 17 ++--- .../immediateInstructions/sbbw_r16_imm16.k | 17 ++--- .../immediateInstructions/sbbw_r16_imm8.k | 17 ++--- .../immediateInstructions/shlb_r8_imm8.k | 17 ++--- .../immediateInstructions/shlb_rh_imm8.k | 17 ++--- .../shldl_r32_r32_imm8.k | 5 +- .../shldq_r64_r64_imm8.k | 5 +- .../shldw_r16_r16_imm8.k | 5 +- .../immediateInstructions/shll_r32_imm8.k | 17 ++--- .../immediateInstructions/shlq_r64_imm8.k | 17 ++--- .../immediateInstructions/shlw_r16_imm8.k | 17 ++--- .../immediateInstructions/shrb_r8_imm8.k | 17 ++--- .../immediateInstructions/shrb_rh_imm8.k | 17 ++--- .../shrdl_r32_r32_imm8.k | 5 +- .../shrdq_r64_r64_imm8.k | 5 +- .../shrdw_r16_r16_imm8.k | 5 +- .../immediateInstructions/shrl_r32_imm8.k | 17 ++--- .../immediateInstructions/shrq_r64_imm8.k | 17 ++--- .../immediateInstructions/shrw_r16_imm8.k | 17 ++--- .../shufpd_xmm_xmm_imm8.k | 5 +- .../shufps_xmm_xmm_imm8.k | 5 +- .../immediateInstructions/subb_al_imm8.k | 17 ++--- .../immediateInstructions/subb_r8_imm8.k | 17 ++--- .../immediateInstructions/subb_rh_imm8.k | 17 ++--- .../immediateInstructions/subl_eax_imm32.k | 17 ++--- .../immediateInstructions/subl_r32_imm32.k | 17 ++--- .../immediateInstructions/subl_r32_imm8.k | 17 ++--- .../immediateInstructions/subq_r64_imm32.k | 17 ++--- .../immediateInstructions/subq_r64_imm8.k | 17 ++--- .../immediateInstructions/subq_rax_imm32.k | 17 ++--- .../immediateInstructions/subw_ax_imm16.k | 17 ++--- .../immediateInstructions/subw_r16_imm16.k | 17 ++--- .../immediateInstructions/subw_r16_imm8.k | 17 ++--- .../immediateInstructions/testb_al_imm8.k | 9 +-- .../immediateInstructions/testb_r8_imm8.k | 9 +-- .../immediateInstructions/testb_rh_imm8.k | 9 +-- .../immediateInstructions/testl_eax_imm32.k | 9 +-- .../immediateInstructions/testl_r32_imm32.k | 9 +-- .../immediateInstructions/testq_r64_imm32.k | 9 +-- .../immediateInstructions/testq_rax_imm32.k | 9 +-- .../immediateInstructions/testw_ax_imm16.k | 9 +-- .../immediateInstructions/testw_r16_imm16.k | 9 +-- .../vblendpd_xmm_xmm_xmm_imm8.k | 5 +- .../vblendpd_ymm_ymm_ymm_imm8.k | 5 +- .../vblendps_xmm_xmm_xmm_imm8.k | 5 +- .../vblendps_ymm_ymm_ymm_imm8.k | 5 +- .../vcmppd_xmm_xmm_xmm_imm8.k | 5 +- .../vcmppd_ymm_ymm_ymm_imm8.k | 5 +- .../vcmpps_xmm_xmm_xmm_imm8.k | 5 +- .../vcmpps_ymm_ymm_ymm_imm8.k | 5 +- .../vcmpsd_xmm_xmm_xmm_imm8.k | 5 +- .../vcmpss_xmm_xmm_xmm_imm8.k | 5 +- .../vcvtps2ph_xmm_xmm_imm8.k | 5 +- .../vcvtps2ph_xmm_ymm_imm8.k | 5 +- .../vdppd_xmm_xmm_xmm_imm8.k | 5 +- .../vdpps_xmm_xmm_xmm_imm8.k | 5 +- .../vdpps_ymm_ymm_ymm_imm8.k | 5 +- .../vextractf128_xmm_ymm_imm8.k | 5 +- .../vextracti128_xmm_ymm_imm8.k | 5 +- .../vextractps_r32_xmm_imm8.k | 5 +- .../vinsertf128_ymm_ymm_xmm_imm8.k | 5 +- .../vinserti128_ymm_ymm_xmm_imm8.k | 5 +- .../vinsertps_xmm_xmm_xmm_imm8.k | 5 +- .../vmpsadbw_xmm_xmm_xmm_imm8.k | 33 ++++----- .../vmpsadbw_ymm_ymm_ymm_imm8.k | 63 +++++++++--------- .../vpalignr_xmm_xmm_xmm_imm8.k | 5 +- .../vpalignr_ymm_ymm_ymm_imm8.k | 5 +- .../vpblendd_xmm_xmm_xmm_imm8.k | 5 +- .../vpblendd_ymm_ymm_ymm_imm8.k | 5 +- .../vpblendw_xmm_xmm_xmm_imm8.k | 5 +- .../vpblendw_ymm_ymm_ymm_imm8.k | 5 +- .../vpclmulqdq_xmm_xmm_xmm_imm8.k | 9 ++- .../vpcmpestri_xmm_xmm_imm8.k | 9 +-- .../vpcmpestrm_xmm_xmm_imm8.k | 9 +-- .../vpcmpistri_xmm_xmm_imm8.k | 9 +-- .../vpcmpistrm_xmm_xmm_imm8.k | 9 +-- .../vperm2f128_ymm_ymm_ymm_imm8.k | 5 +- .../vperm2i128_ymm_ymm_ymm_imm8.k | 5 +- .../vpermilpd_xmm_xmm_imm8.k | 5 +- .../vpermilpd_ymm_ymm_imm8.k | 5 +- .../vpermilps_xmm_xmm_imm8.k | 5 +- .../vpermilps_ymm_ymm_imm8.k | 5 +- .../vpermpd_ymm_ymm_imm8.k | 5 +- .../vpermq_ymm_ymm_imm8.k | 5 +- .../vpextrb_r32_xmm_imm8.k | 5 +- .../vpextrb_r64_xmm_imm8.k | 5 +- .../vpextrd_r32_xmm_imm8.k | 5 +- .../vpextrq_r64_xmm_imm8.k | 5 +- .../vpextrw_r32_xmm_imm8.k | 5 +- .../vpextrw_r64_xmm_imm8.k | 5 +- .../vpinsrb_xmm_xmm_r32_imm8.k | 5 +- .../vpinsrd_xmm_xmm_r32_imm8.k | 5 +- .../vpinsrq_xmm_xmm_r64_imm8.k | 5 +- .../vpinsrw_xmm_xmm_r32_imm8.k | 5 +- .../vpshufd_xmm_xmm_imm8.k | 5 +- .../vpshufd_ymm_ymm_imm8.k | 5 +- .../vpshufhw_xmm_xmm_imm8.k | 5 +- .../vpshufhw_ymm_ymm_imm8.k | 5 +- .../vpshuflw_xmm_xmm_imm8.k | 5 +- .../vpshuflw_ymm_ymm_imm8.k | 5 +- .../vpslld_xmm_xmm_imm8.k | 5 +- .../vpslld_ymm_ymm_imm8.k | 5 +- .../vpslldq_xmm_xmm_imm8.k | 5 +- .../vpslldq_ymm_ymm_imm8.k | 5 +- .../vpsllq_xmm_xmm_imm8.k | 5 +- .../vpsllq_ymm_ymm_imm8.k | 5 +- .../vpsllw_xmm_xmm_imm8.k | 5 +- .../vpsllw_ymm_ymm_imm8.k | 5 +- .../vpsrad_xmm_xmm_imm8.k | 5 +- .../vpsrad_ymm_ymm_imm8.k | 5 +- .../vpsraw_xmm_xmm_imm8.k | 5 +- .../vpsraw_ymm_ymm_imm8.k | 5 +- .../vpsrld_xmm_xmm_imm8.k | 5 +- .../vpsrld_ymm_ymm_imm8.k | 5 +- .../vpsrldq_xmm_xmm_imm8.k | 5 +- .../vpsrldq_ymm_ymm_imm8.k | 5 +- .../vpsrlq_xmm_xmm_imm8.k | 5 +- .../vpsrlq_ymm_ymm_imm8.k | 5 +- .../vpsrlw_xmm_xmm_imm8.k | 5 +- .../vpsrlw_ymm_ymm_imm8.k | 5 +- .../vroundpd_xmm_xmm_imm8.k | 5 +- .../vroundpd_ymm_ymm_imm8.k | 5 +- .../vroundps_xmm_xmm_imm8.k | 5 +- .../vroundps_ymm_ymm_imm8.k | 5 +- .../vroundsd_xmm_xmm_xmm_imm8.k | 5 +- .../vroundss_xmm_xmm_xmm_imm8.k | 5 +- .../vshufpd_xmm_xmm_xmm_imm8.k | 5 +- .../vshufpd_ymm_ymm_ymm_imm8.k | 5 +- .../vshufps_xmm_xmm_xmm_imm8.k | 5 +- .../vshufps_ymm_ymm_ymm_imm8.k | 5 +- .../immediateInstructions/xorb_al_imm8.k | 11 +-- .../immediateInstructions/xorb_r8_imm8.k | 11 +-- .../immediateInstructions/xorb_rh_imm8.k | 11 +-- .../immediateInstructions/xorl_eax_imm32.k | 11 +-- .../immediateInstructions/xorl_r32_imm32.k | 11 +-- .../immediateInstructions/xorl_r32_imm8.k | 11 +-- .../immediateInstructions/xorq_r64_imm32.k | 11 +-- .../immediateInstructions/xorq_r64_imm8.k | 11 +-- .../immediateInstructions/xorq_rax_imm32.k | 11 +-- .../immediateInstructions/xorw_ax_imm16.k | 11 +-- .../immediateInstructions/xorw_r16_imm16.k | 11 +-- .../immediateInstructions/xorw_r16_imm8.k | 11 +-- semantics/memoryInstructions/adcb_m8_imm8.k | 22 +++--- semantics/memoryInstructions/adcl_m32_imm32.k | 22 +++--- semantics/memoryInstructions/adcl_m32_imm8.k | 22 +++--- semantics/memoryInstructions/adcq_m64_imm32.k | 22 +++--- semantics/memoryInstructions/adcq_m64_imm8.k | 22 +++--- semantics/memoryInstructions/adcw_m16_imm16.k | 22 +++--- semantics/memoryInstructions/adcw_m16_imm8.k | 22 +++--- semantics/memoryInstructions/addb_m8_imm8.k | 22 +++--- semantics/memoryInstructions/addl_m32_imm32.k | 22 +++--- semantics/memoryInstructions/addl_m32_imm8.k | 22 +++--- semantics/memoryInstructions/addq_m64_imm32.k | 22 +++--- semantics/memoryInstructions/addq_m64_imm8.k | 22 +++--- semantics/memoryInstructions/addw_m16_imm16.k | 22 +++--- semantics/memoryInstructions/addw_m16_imm8.k | 22 +++--- semantics/memoryInstructions/andb_m8_imm8.k | 16 +++-- semantics/memoryInstructions/andl_m32_imm32.k | 16 +++-- semantics/memoryInstructions/andl_m32_imm8.k | 16 +++-- semantics/memoryInstructions/andq_m64_imm32.k | 16 +++-- semantics/memoryInstructions/andq_m64_imm8.k | 16 +++-- semantics/memoryInstructions/andw_m16_imm16.k | 16 +++-- semantics/memoryInstructions/andw_m16_imm8.k | 16 +++-- .../blendpd_xmm_m128_imm8.k | 10 +-- .../blendps_xmm_m128_imm8.k | 10 +-- semantics/memoryInstructions/btcl_m32_imm8.k | 16 +++-- semantics/memoryInstructions/btcq_m64_imm8.k | 16 +++-- semantics/memoryInstructions/btcw_m16_imm8.k | 16 +++-- semantics/memoryInstructions/btl_m32_imm8.k | 12 ++-- semantics/memoryInstructions/btq_m64_imm8.k | 12 ++-- semantics/memoryInstructions/btrl_m32_imm8.k | 16 +++-- semantics/memoryInstructions/btrq_m64_imm8.k | 16 +++-- semantics/memoryInstructions/btrw_m16_imm8.k | 16 +++-- semantics/memoryInstructions/btsl_m32_imm8.k | 16 +++-- semantics/memoryInstructions/btsq_m64_imm8.k | 16 +++-- semantics/memoryInstructions/btsw_m16_imm8.k | 16 +++-- semantics/memoryInstructions/btw_m16_imm8.k | 12 ++-- semantics/memoryInstructions/cmpb_m8_imm8.k | 20 +++--- semantics/memoryInstructions/cmpl_m32_imm32.k | 20 +++--- semantics/memoryInstructions/cmpl_m32_imm8.k | 20 +++--- .../memoryInstructions/cmppd_xmm_m128_imm8.k | 10 +-- .../memoryInstructions/cmpps_xmm_m128_imm8.k | 10 +-- semantics/memoryInstructions/cmpq_m64_imm32.k | 20 +++--- semantics/memoryInstructions/cmpq_m64_imm8.k | 20 +++--- .../memoryInstructions/cmpsd_xmm_m64_imm8.k | 10 +-- .../memoryInstructions/cmpss_xmm_m32_imm8.k | 10 +-- semantics/memoryInstructions/cmpw_m16_imm16.k | 20 +++--- semantics/memoryInstructions/cmpw_m16_imm8.k | 20 +++--- .../memoryInstructions/dppd_xmm_m128_imm8.k | 10 +-- .../memoryInstructions/dpps_xmm_m128_imm8.k | 10 +-- .../extractps_m32_xmm_imm8.k | 10 +-- .../memoryInstructions/imull_r32_m32_imm32.k | 14 ++-- .../memoryInstructions/imull_r32_m32_imm8.k | 14 ++-- .../memoryInstructions/imulq_r64_m64_imm32.k | 14 ++-- .../memoryInstructions/imulq_r64_m64_imm8.k | 14 ++-- .../memoryInstructions/imulw_r16_m16_imm16.k | 14 ++-- .../memoryInstructions/imulw_r16_m16_imm8.k | 14 ++-- .../insertps_xmm_m32_imm8.k | 10 +-- semantics/memoryInstructions/movb_m8_imm8.k | 7 +- semantics/memoryInstructions/movl_m32_imm32.k | 7 +- semantics/memoryInstructions/movq_m64_imm32.k | 7 +- semantics/memoryInstructions/movw_m16_imm16.k | 7 +- .../mpsadbw_xmm_m128_imm8.k | 33 ++++----- semantics/memoryInstructions/orb_m8_imm8.k | 16 +++-- semantics/memoryInstructions/orl_m32_imm32.k | 16 +++-- semantics/memoryInstructions/orl_m32_imm8.k | 16 +++-- semantics/memoryInstructions/orq_m64_imm32.k | 16 +++-- semantics/memoryInstructions/orq_m64_imm8.k | 16 +++-- semantics/memoryInstructions/orw_m16_imm16.k | 16 +++-- semantics/memoryInstructions/orw_m16_imm8.k | 16 +++-- .../palignr_xmm_m128_imm8.k | 10 +-- .../pblendw_xmm_m128_imm8.k | 10 +-- .../pclmulqdq_xmm_m128_imm8.k | 9 ++- .../pcmpestri_xmm_m128_imm8.k | 15 +++-- .../pcmpestrm_xmm_m128_imm8.k | 13 ++-- .../pcmpistri_xmm_m128_imm8.k | 15 +++-- .../pcmpistrm_xmm_m128_imm8.k | 14 ++-- .../memoryInstructions/pextrb_m8_xmm_imm8.k | 10 +-- .../memoryInstructions/pextrd_m32_xmm_imm8.k | 10 +-- .../memoryInstructions/pextrq_m64_xmm_imm8.k | 10 +-- .../memoryInstructions/pextrw_m16_xmm_imm8.k | 10 +-- .../memoryInstructions/pinsrb_xmm_m8_imm8.k | 10 +-- .../memoryInstructions/pinsrd_xmm_m32_imm8.k | 10 +-- .../memoryInstructions/pinsrq_xmm_m64_imm8.k | 10 +-- .../memoryInstructions/pinsrw_xmm_m16_imm8.k | 10 +-- .../memoryInstructions/pshufd_xmm_m128_imm8.k | 10 +-- .../pshufhw_xmm_m128_imm8.k | 10 +-- .../pshuflw_xmm_m128_imm8.k | 10 +-- semantics/memoryInstructions/rclb_m8_imm8.k | 14 ++-- semantics/memoryInstructions/rcll_m32_imm8.k | 14 ++-- semantics/memoryInstructions/rclq_m64_imm8.k | 14 ++-- semantics/memoryInstructions/rclw_m16_imm8.k | 14 ++-- semantics/memoryInstructions/rcrb_m8_imm8.k | 14 ++-- semantics/memoryInstructions/rcrl_m32_imm8.k | 14 ++-- semantics/memoryInstructions/rcrq_m64_imm8.k | 14 ++-- semantics/memoryInstructions/rcrw_m16_imm8.k | 14 ++-- semantics/memoryInstructions/rolb_m8_imm8.k | 14 ++-- semantics/memoryInstructions/roll_m32_imm8.k | 14 ++-- semantics/memoryInstructions/rolq_m64_imm8.k | 14 ++-- semantics/memoryInstructions/rolw_m16_imm8.k | 14 ++-- semantics/memoryInstructions/rorb_m8_imm8.k | 14 ++-- semantics/memoryInstructions/rorl_m32_imm8.k | 14 ++-- semantics/memoryInstructions/rorq_m64_imm8.k | 14 ++-- semantics/memoryInstructions/rorw_m16_imm8.k | 14 ++-- .../memoryInstructions/rorxl_r32_m32_imm8.k | 12 ++-- .../memoryInstructions/rorxq_r64_m64_imm8.k | 12 ++-- .../roundpd_xmm_m128_imm8.k | 10 +-- .../roundps_xmm_m128_imm8.k | 10 +-- .../memoryInstructions/roundsd_xmm_m64_imm8.k | 10 +-- .../memoryInstructions/roundss_xmm_m32_imm8.k | 10 +-- semantics/memoryInstructions/salb_m8_imm8.k | 22 +++--- semantics/memoryInstructions/sall_m32_imm8.k | 22 +++--- semantics/memoryInstructions/salq_m64_imm8.k | 22 +++--- semantics/memoryInstructions/salw_m16_imm8.k | 22 +++--- semantics/memoryInstructions/sarb_m8_imm8.k | 22 +++--- semantics/memoryInstructions/sarl_m32_imm8.k | 22 +++--- semantics/memoryInstructions/sarq_m64_imm8.k | 22 +++--- semantics/memoryInstructions/sarw_m16_imm8.k | 22 +++--- semantics/memoryInstructions/sbbb_m8_imm8.k | 22 +++--- semantics/memoryInstructions/sbbl_m32_imm32.k | 22 +++--- semantics/memoryInstructions/sbbl_m32_imm8.k | 22 +++--- semantics/memoryInstructions/sbbq_m64_imm32.k | 22 +++--- semantics/memoryInstructions/sbbq_m64_imm8.k | 22 +++--- semantics/memoryInstructions/sbbw_m16_imm16.k | 22 +++--- semantics/memoryInstructions/sbbw_m16_imm8.k | 22 +++--- semantics/memoryInstructions/shlb_m8_imm8.k | 22 +++--- .../memoryInstructions/shldl_m32_r32_imm8.k | 12 ++-- .../memoryInstructions/shldq_m64_r64_imm8.k | 12 ++-- .../memoryInstructions/shldw_m16_r16_imm8.k | 12 ++-- semantics/memoryInstructions/shll_m32_imm8.k | 22 +++--- semantics/memoryInstructions/shlq_m64_imm8.k | 22 +++--- semantics/memoryInstructions/shlw_m16_imm8.k | 22 +++--- semantics/memoryInstructions/shrb_m8_imm8.k | 22 +++--- .../memoryInstructions/shrdl_m32_r32_imm8.k | 12 ++-- .../memoryInstructions/shrdq_m64_r64_imm8.k | 12 ++-- .../memoryInstructions/shrdw_m16_r16_imm8.k | 12 ++-- semantics/memoryInstructions/shrl_m32_imm8.k | 22 +++--- semantics/memoryInstructions/shrq_m64_imm8.k | 22 +++--- semantics/memoryInstructions/shrw_m16_imm8.k | 22 +++--- .../memoryInstructions/shufpd_xmm_m128_imm8.k | 10 +-- .../memoryInstructions/shufps_xmm_m128_imm8.k | 10 +-- semantics/memoryInstructions/subb_m8_imm8.k | 22 +++--- semantics/memoryInstructions/subl_m32_imm32.k | 22 +++--- semantics/memoryInstructions/subl_m32_imm8.k | 22 +++--- semantics/memoryInstructions/subq_m64_imm32.k | 22 +++--- semantics/memoryInstructions/subq_m64_imm8.k | 22 +++--- semantics/memoryInstructions/subw_m16_imm16.k | 22 +++--- semantics/memoryInstructions/subw_m16_imm8.k | 22 +++--- semantics/memoryInstructions/testb_m8_imm8.k | 14 ++-- .../memoryInstructions/testl_m32_imm32.k | 14 ++-- .../memoryInstructions/testq_m64_imm32.k | 14 ++-- .../memoryInstructions/testw_m16_imm16.k | 14 ++-- .../vblendpd_xmm_xmm_m128_imm8.k | 10 +-- .../vblendpd_ymm_ymm_m256_imm8.k | 10 +-- .../vblendps_xmm_xmm_m128_imm8.k | 10 +-- .../vblendps_ymm_ymm_m256_imm8.k | 10 +-- .../vcmppd_xmm_xmm_m128_imm8.k | 10 +-- .../vcmppd_ymm_ymm_m256_imm8.k | 10 +-- .../vcmpps_xmm_xmm_m128_imm8.k | 10 +-- .../vcmpps_ymm_ymm_m256_imm8.k | 10 +-- .../vcmpsd_xmm_xmm_m64_imm8.k | 10 +-- .../vcmpss_xmm_xmm_m32_imm8.k | 10 +-- .../vcvtps2ph_m128_ymm_imm8.k | 10 +-- .../vcvtps2ph_m64_xmm_imm8.k | 10 +-- .../vdppd_xmm_xmm_m128_imm8.k | 10 +-- .../vdpps_xmm_xmm_m128_imm8.k | 10 +-- .../vdpps_ymm_ymm_m256_imm8.k | 10 +-- .../vextractf128_m128_ymm_imm8.k | 10 +-- .../vextracti128_m128_ymm_imm8.k | 10 +-- .../vextractps_m32_xmm_imm8.k | 10 +-- .../vinsertf128_ymm_ymm_m128_imm8.k | 10 +-- .../vinserti128_ymm_ymm_m128_imm8.k | 10 +-- .../vinsertps_xmm_xmm_m32_imm8.k | 10 +-- .../vmpsadbw_xmm_xmm_m128_imm8.k | 33 ++++----- .../vmpsadbw_ymm_ymm_m256_imm8.k | 63 +++++++++--------- .../vpalignr_xmm_xmm_m128_imm8.k | 10 +-- .../vpalignr_ymm_ymm_m256_imm8.k | 10 +-- .../vpblendd_xmm_xmm_m128_imm8.k | 10 +-- .../vpblendd_ymm_ymm_m256_imm8.k | 10 +-- .../vpblendw_xmm_xmm_m128_imm8.k | 10 +-- .../vpblendw_ymm_ymm_m256_imm8.k | 10 +-- .../vpclmulqdq_xmm_xmm_m128_imm8.k | 9 ++- .../vpcmpestri_xmm_m128_imm8.k | 15 +++-- .../vpcmpestrm_xmm_m128_imm8.k | 13 ++-- .../vpcmpistri_xmm_m128_imm8.k | 15 +++-- .../vpcmpistrm_xmm_m128_imm8.k | 14 ++-- .../vperm2f128_ymm_ymm_m256_imm8.k | 10 +-- .../vperm2i128_ymm_ymm_m256_imm8.k | 10 +-- .../vpermilpd_xmm_m128_imm8.k | 10 +-- .../vpermilpd_ymm_m256_imm8.k | 10 +-- .../vpermilps_xmm_m128_imm8.k | 10 +-- .../vpermilps_ymm_m256_imm8.k | 10 +-- .../vpermpd_ymm_m256_imm8.k | 10 +-- .../memoryInstructions/vpermq_ymm_m256_imm8.k | 10 +-- .../memoryInstructions/vpextrb_m8_xmm_imm8.k | 10 +-- .../memoryInstructions/vpextrd_m32_xmm_imm8.k | 10 +-- .../memoryInstructions/vpextrq_m64_xmm_imm8.k | 10 +-- .../memoryInstructions/vpextrw_m16_xmm_imm8.k | 10 +-- .../vpinsrb_xmm_xmm_m8_imm8.k | 10 +-- .../vpinsrd_xmm_xmm_m32_imm8.k | 10 +-- .../vpinsrq_xmm_xmm_m64_imm8.k | 10 +-- .../vpinsrw_xmm_xmm_m16_imm8.k | 10 +-- .../vpshufd_xmm_m128_imm8.k | 10 +-- .../vpshufd_ymm_m256_imm8.k | 10 +-- .../vpshufhw_xmm_m128_imm8.k | 10 +-- .../vpshufhw_ymm_m256_imm8.k | 10 +-- .../vpshuflw_xmm_m128_imm8.k | 10 +-- .../vpshuflw_ymm_m256_imm8.k | 10 +-- .../vroundpd_xmm_m128_imm8.k | 10 +-- .../vroundpd_ymm_m256_imm8.k | 10 +-- .../vroundps_xmm_m128_imm8.k | 10 +-- .../vroundps_ymm_m256_imm8.k | 10 +-- .../vroundsd_xmm_xmm_m64_imm8.k | 10 +-- .../vroundss_xmm_xmm_m32_imm8.k | 10 +-- .../vshufpd_xmm_xmm_m128_imm8.k | 10 +-- .../vshufpd_ymm_ymm_m256_imm8.k | 10 +-- .../vshufps_xmm_xmm_m128_imm8.k | 10 +-- .../vshufps_ymm_ymm_m256_imm8.k | 10 +-- semantics/memoryInstructions/xorb_m8_imm8.k | 16 +++-- semantics/memoryInstructions/xorl_m32_imm32.k | 16 +++-- semantics/memoryInstructions/xorl_m32_imm8.k | 16 +++-- semantics/memoryInstructions/xorq_m64_imm32.k | 16 +++-- semantics/memoryInstructions/xorq_m64_imm8.k | 16 +++-- semantics/memoryInstructions/xorw_m16_imm16.k | 16 +++-- semantics/memoryInstructions/xorw_m16_imm8.k | 16 +++-- semantics/registerInstructions/pushq_imm32.k | 22 ------ semantics/registerInstructions/roll_r32_one.k | 39 ++++------- semantics/run-on-elf.py | 2 +- semantics/systemInstructions/callq_rel32.k | 12 ++-- semantics/systemInstructions/ja_rel32.k | 13 +++- semantics/systemInstructions/ja_rel8.k | 17 ++--- semantics/systemInstructions/jae_rel32.k | 12 ++-- semantics/systemInstructions/jae_rel8.k | 12 ++-- semantics/systemInstructions/jb_rel32.k | 12 ++-- semantics/systemInstructions/jb_rel8.k | 12 ++-- semantics/systemInstructions/jbe_rel32.k | 16 +++-- semantics/systemInstructions/jbe_rel8.k | 16 +++-- semantics/systemInstructions/jc_rel32.k | 12 ++-- semantics/systemInstructions/jc_rel8.k | 12 ++-- semantics/systemInstructions/je_rel32.k | 12 ++-- semantics/systemInstructions/je_rel8.k | 12 ++-- semantics/systemInstructions/jecxz_rel8.k | 12 ++-- semantics/systemInstructions/jg_rel32.k | 16 +++-- semantics/systemInstructions/jg_rel8.k | 16 +++-- semantics/systemInstructions/jge_rel32.k | 12 ++-- semantics/systemInstructions/jge_rel8.k | 12 ++-- semantics/systemInstructions/jl_rel32.k | 12 ++-- semantics/systemInstructions/jl_rel8.k | 12 ++-- semantics/systemInstructions/jle_rel32.k | 16 +++-- semantics/systemInstructions/jle_rel8.k | 16 +++-- semantics/systemInstructions/jmp_rel32.k | 5 +- semantics/systemInstructions/jmp_rel8.k | 5 +- semantics/systemInstructions/jna_rel32.k | 14 ++-- semantics/systemInstructions/jna_rel8.k | 14 ++-- semantics/systemInstructions/jnae_rel32.k | 12 ++-- semantics/systemInstructions/jnae_rel8.k | 12 ++-- semantics/systemInstructions/jnb_rel32.k | 12 ++-- semantics/systemInstructions/jnb_rel8.k | 12 ++-- semantics/systemInstructions/jnbe_rel32.k | 16 +++-- semantics/systemInstructions/jnbe_rel8.k | 16 +++-- semantics/systemInstructions/jnc_rel32.k | 12 ++-- semantics/systemInstructions/jnc_rel8.k | 12 ++-- semantics/systemInstructions/jne_rel32.k | 12 ++-- semantics/systemInstructions/jne_rel8.k | 12 ++-- semantics/systemInstructions/jng_rel32.k | 12 ++-- semantics/systemInstructions/jng_rel8.k | 12 ++-- semantics/systemInstructions/jnge_rel32.k | 12 ++-- semantics/systemInstructions/jnge_rel8.k | 12 ++-- semantics/systemInstructions/jnl_rel32.k | 12 ++-- semantics/systemInstructions/jnl_rel8.k | 12 ++-- semantics/systemInstructions/jnle_rel32.k | 12 ++-- semantics/systemInstructions/jnle_rel8.k | 12 ++-- semantics/systemInstructions/jno_rel32.k | 12 ++-- semantics/systemInstructions/jno_rel8.k | 12 ++-- semantics/systemInstructions/jnp_rel32.k | 12 ++-- semantics/systemInstructions/jnp_rel8.k | 12 ++-- semantics/systemInstructions/jns_rel32.k | 12 ++-- semantics/systemInstructions/jns_rel8.k | 12 ++-- semantics/systemInstructions/jnz_rel32.k | 12 ++-- semantics/systemInstructions/jnz_rel8.k | 12 ++-- semantics/systemInstructions/jo_rel32.k | 12 ++-- semantics/systemInstructions/jo_rel8.k | 12 ++-- semantics/systemInstructions/jp_rel32.k | 12 ++-- semantics/systemInstructions/jp_rel8.k | 12 ++-- semantics/systemInstructions/jpe_rel32.k | 12 ++-- semantics/systemInstructions/jpe_rel8.k | 12 ++-- semantics/systemInstructions/jpo_rel32.k | 12 ++-- semantics/systemInstructions/jpo_rel8.k | 12 ++-- semantics/systemInstructions/jrcxz_rel8.k | 12 ++-- semantics/systemInstructions/js_rel32.k | 12 ++-- semantics/systemInstructions/js_rel8.k | 12 ++-- semantics/systemInstructions/jz_rel32.k | 12 ++-- semantics/systemInstructions/jz_rel8.k | 12 ++-- semantics/systemInstructions/leaveq.k | 2 +- semantics/systemInstructions/loop_rel8.k | 15 +++-- semantics/systemInstructions/loope_rel8.k | 19 +++--- semantics/systemInstructions/loopne_rel8.k | 19 +++--- semantics/systemInstructions/loopnz_rel8.k | 19 +++--- semantics/systemInstructions/loopz_rel8.k | 19 +++--- semantics/test.c | 6 +- semantics/x86-abstract-semantics.k | 61 +++++++++-------- semantics/x86-syntax.k | 1 + 619 files changed, 4136 insertions(+), 3257 deletions(-) create mode 100644 docs/z3_artifcats/array2.z3 create mode 100644 docs/z3_artifcats/datatypes.z3 create mode 100755 semantics/a.out delete mode 100644 semantics/registerInstructions/pushq_imm32.k diff --git a/docs/z3_artifcats/array2.z3 b/docs/z3_artifcats/array2.z3 new file mode 100644 index 000000000..ce19c7f46 --- /dev/null +++ b/docs/z3_artifcats/array2.z3 @@ -0,0 +1,11 @@ +(declare-const x Int) +(declare-const y Int) +(declare-const z Int) +(declare-const a1 (Array Int Int)) +(declare-const a2 (Array Int Int)) +(declare-const a3 (Array Int Int)) +(assert (= (select a1 x) x)) +(assert (= (store a1 x y) a1)) +(assert (not (= x y))) +(check-sat) +(get-model) diff --git a/docs/z3_artifcats/datatypes.z3 b/docs/z3_artifcats/datatypes.z3 new file mode 100644 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